Add batch 12 (WangXuan95_FPGA-UART, chipsalliance_VeeRwolf, bluespec_Piccolo, 16SalomonArs_Pcileech-DMA-NVMe-VMD, marmolejo_zet)
c22be57 verified - 16SalomonArs_Pcileech-DMA-NVMe-VMD
- AngeloJacobo_UberDDR3
- Arlet_verilog-6502
- EttusResearch_uhd
- Evensgn_RISC-V-CPU
- FPGAwars_icezum
- IBM_AccDNN
- KastnerRG_riffa
- LeiWang1999_ZYNQ-NVDLA
- Luthiraa_TALOS-V2
- MiSTer-devel_ao486_MiSTer
- MoonbaseOtago_vroom
- NetFPGA_netfpga
- Nitcloud_Digital-IDE
- Obijuan_open-fpga-verilog-tutorial
- OpenROAD
- OpenTimer_OpenTimer
- QShen3_CNN-FPGA
- SymbioticEDA_riscv-formal
- T-K-233_RISC-V-Single-Cycle-CPU
- TILOS-AI-Institute_MacroPlacement
- The-OpenROAD-Project_OpenROAD-flow-scripts
- The-OpenROAD-Project_OpenROAD
- The-OpenROAD-Project_OpenSTA
- VerticalResearchGroup_miaow
- WangXuan95_FPGA-CAN
- WangXuan95_FPGA-FOC
- WangXuan95_FPGA-SDcard-Reader
- WangXuan95_FPGA-UART
- WangXuan95_FPGA-USB-Device
- WangXuan95_FPGA-ftdi245fifo
- Wren6991_Hazard3
- XUANTIE-RV_openc906
- XUANTIE-RV_openc910
- XUANTIE-RV_wujian100_open
- YosysHQ_picorv32
- ZipCPU_sdspi
- ZipCPU_wb2axip
- ZipCPU_wbuart32
- ZipCPU_zipcpu
- abdelazeem201_ASIC-Design-Roadmap
- abdelazeem201_Systolic-array-implementation-in-RTL-for-TPU
- adki_AMBA_AXI_AHB_APB
- alexforencich_verilog-axi
- alexforencich_verilog-ethernet
- alexforencich_verilog-i2c
- alexforencich_verilog-pcie
- alexforencich_verilog-uart
- analogdevicesinc_hdl
- antonblanchard_microwatt