Add batch 2 (danielholanda_LeFlow, The-OpenROAD-Project_OpenSTA, omarelhedaby_CNN-FPGA, QShen3_CNN-FPGA, openrisc_mor1kx)

.gitattributes

@@ -487,3 +487,20 @@ OpenTimer_OpenTimer/benchmark/wb_dma/wb_dma.ops filter=lfs diff=lfs merge=lfs -t
 OpenTimer_OpenTimer/benchmark/wb_dma/wb_dma.ops.back filter=lfs diff=lfs merge=lfs -text
 OpenTimer_OpenTimer/benchmark/wb_dma/wb_dma.output filter=lfs diff=lfs merge=lfs -text
 OpenTimer_OpenTimer/wiki/reference/TAU[[:space:]]2018[[:space:]]Contest[[:space:]]Education.docx filter=lfs diff=lfs merge=lfs -text
+The-OpenROAD-Project_OpenSTA/test/sky130hd/sky130_fd_sc_hd__ff_n40C_1v95.lib filter=lfs diff=lfs merge=lfs -text
+The-OpenROAD-Project_OpenSTA/test/sky130hd/sky130_fd_sc_hd__ss_n40C_1v40.lib filter=lfs diff=lfs merge=lfs -text
+The-OpenROAD-Project_OpenSTA/test/sky130hd/sky130_fd_sc_hd__tt_025C_1v80.lib filter=lfs diff=lfs merge=lfs -text
+The-OpenROAD-Project_OpenSTA/test/sky130hd/sky130hd_tt.lib filter=lfs diff=lfs merge=lfs -text
+The-OpenROAD-Project_OpenSTA/test/sky130hs/sky130_fd_sc_hs__tt_025C_1v80.lib filter=lfs diff=lfs merge=lfs -text
+The-OpenROAD-Project_OpenSTA/test/sky130hs/sky130hs_tt.lib filter=lfs diff=lfs merge=lfs -text
+danielholanda_LeFlow/src/ip/stratixiv_pcie_hip_atoms.v filter=lfs diff=lfs merge=lfs -text
+danielholanda_LeFlow/src/ip/stratixv_hssi_atoms_ncrypt.v filter=lfs diff=lfs merge=lfs -text
+danielholanda_LeFlow/src/ip/stratixv_pcie_hip_atoms_ncrypt.v filter=lfs diff=lfs merge=lfs -text
+danielholanda_LeFlow/src/tensorflow/tensorflow-1.6.0-cp27-cp27mu-linux_x86_64.whl filter=lfs diff=lfs merge=lfs -text
+omarelhedaby_CNN-FPGA/CNN-FPGA-Vivado/CNN-FPGA-Vivado.sim/sim_1/behav/convLayerMulti_TB_behav.wdb filter=lfs diff=lfs merge=lfs -text
+omarelhedaby_CNN-FPGA/CNN-FPGA-Vivado/CNN-FPGA-Vivado.sim/sim_1/behav/xsim.dir/convLayerMulti_TB_behav/xsim.xdbg filter=lfs diff=lfs merge=lfs -text
+omarelhedaby_CNN-FPGA/Screenshots[[:space:]]and[[:space:]]Reports/Part[[:space:]]2-[[:space:]]TanH[[:space:]]activation/SimulationImages/PostSynthesisSimulationFullKernel.PNG filter=lfs diff=lfs merge=lfs -text
+omarelhedaby_CNN-FPGA/Screenshots[[:space:]]and[[:space:]]Reports/Part[[:space:]]2-[[:space:]]TanH[[:space:]]activation/SimulationImages/SimulatingFullKernelSize.PNG filter=lfs diff=lfs merge=lfs -text
+omarelhedaby_CNN-FPGA/Screenshots[[:space:]]and[[:space:]]Reports/Part[[:space:]]3-[[:space:]]SoftMax[[:space:]]activation/Synthesis[[:space:]]Reports[[:space:]]and[[:space:]]Screenshots/SoftMax[[:space:]]Comparison[[:space:]]Report.docx filter=lfs diff=lfs merge=lfs -text
+omarelhedaby_CNN-FPGA/Screenshots[[:space:]]and[[:space:]]Reports/Part[[:space:]]5-[[:space:]]Integration/FC[[:space:]]layer[[:space:]]Waveform.PNG filter=lfs diff=lfs merge=lfs -text
+omarelhedaby_CNN-FPGA/Test.xlsx filter=lfs diff=lfs merge=lfs -text

QShen3_CNN-FPGA/LICENSE

@@ -0,0 +1,21 @@
+MIT License
+
+Copyright (c) 2018 Shen
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.

QShen3_CNN-FPGA/README.md

@@ -0,0 +1,188 @@
+# CNN - FPGA
+
+<!-- TOC -->
+
+- [CNN - FPGA](#cnn---fpga)
+    - [项目由来](#项目由来)
+    - [使用](#使用)
+        - [Conv2d](#conv2d)
+        - [Max_pool](#max_pool)
+        - [Avg_pool](#avg_pool)
+        - [Relu_activation](#relu_activation)
+        - [FullConnect](#fullconnect)
+    - [使用示例](#使用示例)
+
+<!-- /TOC -->
+
+## 项目由来
+
+&emsp;&emsp;毕业设计，为了蹭热点，选了几个和人工智能相关的课题，本意是希望通过毕业设计让自己了解一下机器学习，比如CNN一类的。很不幸，被体系结构实验室的老师抢走了。于是就面临了这个偏硬件的课题，用FPGA加速人工智能算法。</Br>
+&emsp;&emsp;毕竟只是本科毕业设计，这个课题在我手里就变成了用FPGA加速CNN，本来的目的还是要完成，在大致了解了CNN之后，还是在极不情愿中做完了这个项目。</Br>
+&emsp;&emsp;项目本质很简单，使用Verilog实现了一些CNN的模块。~~几乎没有多少实用价值。~~ 另外，和大多数FPGA加速CNN的项目一样，本项目只能运行推断，不能学习，所以没有后向传播~~这不怪我，Xilinx自己都已经放弃治疗了。~~
+
+## 使用
+
+&emsp;&emsp;模块设计上参照了tensorflow。因为使用了全并行的设计，所以没有引入时序，也没有做流水线~~我不信哪块FPGA板子的部件延迟会大过总线周期~~，所以在资源占用上很不合理，可能需要在规模很大的FPGA板子上才能实现一个较大的网络吧~~也就是说本项目毫无卵用~~</Br></Br>
+
+有以下几个模块：
+
+### Conv2d
+
+**说明：**
+
+&emsp;&emsp;卷积模块，可以进行二维卷积。支持多个卷积核，不同步长，是否启用边缘0填充等
+
+**可配置参数：**
+
+| 名称          | 说明                                | 默认值 |
+| ------------- | ----------------------------------- | ------ |
+| BITWIDTH      | 数据位宽                            | 8      |
+| DATAWIDTH     | 图像的宽度                          | 28     |
+| DATAHEIGHT    | 图像的高度                          | 28     |
+| DATACHANNEL   | 图像通道数                          | 3      |
+| FILTERHEIGHT  | 卷积核的高度                        | 5      |
+| FILTERWIDTH   | 卷积核的宽度                        | 5      |
+| FILTERBATCH   | 卷积核的数量                        | 1      |
+| STRIDEHEIGHT  | 纵向步长                            | 1      |
+| STRIDEWIDTH   | 横向步长                            | 1      |
+| PADDINGENABLE | 边缘是否使用0填充，1代表是，0代表否 | 0      |
+
+**输入输出：**
+
+| 名称         | 类型   | 说明                                                                               | 长度                                                                                                                                                                                                                          |
+| ------------ | ------ | ---------------------------------------------------------------------------------- | ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- |
+| data         | input  | 输入的图像，数据从第一个通道左上至最后一个通道右下排列，每一个像素值为有符号定点数 | BITWIDTH × DATAWIDTH × DATAHEIGHT × DATACHANNEL                                                                                                                                                                               |
+| filterWeight | input  | 卷积核权值，从第一个卷积核左上开始，到最后一个卷积核右下，每一个值为有符号定点数   | BITWIDTH × FILTERHEIGHT × FILTERWIDTH × DATACHANNEL × FILTERBATCH                                                                                                                                                             |
+| filterBias   | input  | 卷积核偏置，按卷积核顺序排列，每一个值为有符号定点数                               | BITWIDTH × FILTERBATCH                                                                                                                                                                                                        |
+| result       | output | 输出的特征图，从第一张左上开始，到最后一张右下，每一个值为有符号定点数             | BITWIDTH × FILTERBATCH × (PADDINGENABLE == 0 ? (DATAWIDTH - FILTERWIDTH + 1) ÷ STRIDEWIDTH : (DATAWIDTH ÷ STRIDEWIDTH)) × (PADDINGENABLE == 0 ? (DATAHEIGHT - FILTERHEIGHT + 1) ÷ STRIDEHEIGHT : (DATAHEIGHT ÷ STRIDEHEIGHT)) |
+
+### Max_pool
+
+**说明：**
+
+&emsp;&emsp;最大池化模块，可以对输入进行最大池化运算。
+
+**可配置参数：**
+
+| 名称        | 说明         | 默认值 |
+| ----------- | ------------ | ------ |
+| BITWIDTH    | 数据位宽     | 8      |
+| DATAWIDTH   | 特征图的宽度 | 28     |
+| DATAHEIGHT  | 特征图的高度 | 28     |
+| DATACHANNEL | 特征图通道数 | 3      |
+| KWIDTH      | 池化窗口宽度 | 2      |
+| KHEIGHT     | 池化窗口高度 | 2      |
+
+**输入输出：**
+
+| 名称   | 类型   | 说明                                                                     | 长度                                                               |
+| ------ | ------ | ------------------------------------------------------------------------ | ------------------------------------------------------------------ |
+| data   | input  | 输入的特征图，像素数据从左上至右下排列，每一个值为有符号定点数           | BITWIDTH × DATAWIDTH × DATAHEIGHT × DATACHANNEL                    |
+| result | output | 输出的特征图，从第一个通道左上到最后一个通道右下，每一个值为有符号定点数 | BITWIDTH × DATAWIDTH ÷ KWIDTH × DATAHEIGHT ÷ KHEIGHT × DATACHANNEL |
+
+### Avg_pool
+
+**说明：**
+
+&emsp;&emsp;平均池化模块，可以对输入进行平均池化运算。
+
+**可配置参数：**
+
+| 名称        | 说明         | 默认值 |
+| ----------- | ------------ | ------ |
+| BITWIDTH    | 数据位宽     | 8      |
+| DATAWIDTH   | 特征图的宽度 | 28     |
+| DATAHEIGHT  | 特征图的高度 | 28     |
+| DATACHANNEL | 特征图通道数 | 3      |
+| KWIDTH      | 池化窗口宽度 | 2      |
+| KHEIGHT     | 池化窗口高度 | 2      |
+
+**输入输出：**
+
+| 名称   | 类型   | 说明                                                                             | 长度                                                               |
+| ------ | ------ | -------------------------------------------------------------------------------- | ------------------------------------------------------------------ |
+| data   | input  | 输入的特征图，数据从第一个通道左上至最后一个通道右下排列，每一个值为有符号定点数 | BITWIDTH × DATAWIDTH × DATAHEIGHT × DATACHANNEL                    |
+| result | output | 输出的特征图，从第一个通道左上到最后一个通道右下，每一个值为有符号定点数         | BITWIDTH × DATAWIDTH ÷ KWIDTH × DATAHEIGHT ÷ KHEIGHT × DATACHANNEL |
+
+### Relu_activation
+
+**说明：**
+
+&emsp;&emsp;ReLU激活函数模块。可以根据情况决定卷积之后的特征图要不要连接激活函数。
+
+**可配置参数：**
+
+| 名称        | 说明         | 默认值 |
+| ----------- | ------------ | ------ |
+| BITWIDTH    | 数据位宽     | 8      |
+| DATAWIDTH   | 特征图的宽度 | 28     |
+| DATAHEIGHT  | 特征图的高度 | 28     |
+| DATACHANNEL | 特征图通道数 | 3      |
+
+**输入输出：**
+
+| 名称   | 类型   | 说明                                                                             | 长度                                            |
+| ------ | ------ | -------------------------------------------------------------------------------- | ----------------------------------------------- |
+| data   | input  | 输入的特征图，数据从第一个通道左上至最后一个通道右下排列，每一个值为有符号定点数 | BITWIDTH × DATAWIDTH × DATAHEIGHT × DATACHANNEL |
+| result | output | 输出的特征图，从第一个通道左上到最后一个通道右下，每一个值为有符号定点数         | BITWIDTH × DATAHEIGHT × DATAWIDTH × DATACHANNEL |
+
+### FullConnect
+
+**说明：**
+
+&emsp;&emsp;全连接层模块。数据会被展开为一维矩阵，进行全连接运算。
+
+**可配置参数：**
+
+| 名称        | 说明                   | 默认值 |
+| ----------- | ---------------------- | ------ |
+| BITWIDTH    | 数据位宽               | 8      |
+| LENGTH      | 输入数据展开后的长度   | 25     |
+| FILTERBATCH | 全连接层参数矩阵的个数 | 1      |
+
+**输入输出：**
+
+| 名称   | 类型   | 说明                                                                               | 长度                            |
+| ------ | ------ | ---------------------------------------------------------------------------------- | ------------------------------- |
+| data   | input  | 输入的特征图，数据从第一个通道左上至最后一个通道右下排列，每一个值为有符号定点数   | BITWIDTH × LENGTH               |
+| weight | input  | 参数矩阵的权值，从第一个参数矩阵开头至最后一个参数矩阵结尾，每一个值为有符号定点数 | BITWIDTH × LENGTH × FILTERBATCH |
+| bias   | input  | 参数矩阵的偏置，按参数矩阵顺序排列，每一个值为有符号定点数                         | BITWIDTH × FILTERBATCH          |
+| result | output | 输出结果也为一维矩阵，每一个值为有符号定点数，顺序对应权值矩阵的顺序               | BITWIDTH × FILTERBATCH          |
+
+## 使用示例
+
+```verilog
+input [4703:0] data;
+output [7:0] result;
+
+reg [1295:0] weight1;
+reg [47:0] bias1;
+wire [6911:0] cov_result1;
+wire [1727:0] result1, result1_activation;
+
+reg [1295:0] weight2;
+reg [23:0] bias2;
+wire [383:0] cov_result2;
+wire [95:0] result2, result2_activation;
+
+reg [1919:0] weight3;
+reg [159:0] bias3;
+wire [159:0] result3;
+
+reg [159:0] weight4;
+reg [7:0] bias4;
+
+Conv2d#(8, 14, 14, 3, 3, 3, 6, 1, 1, 0) conv2d_1(data, weight1, bias1, cov_result1);
+Max_pool#(8, 12, 12, 6, 2, 2) max_pool_1(cov_result1, result1);
+Relu_activation#(8, 6, 6, 6) relu_activation_1(result1, result1_activation);
+
+Conv2d#(8, 6, 6, 6, 3, 3, 3, 1, 1, 0) conv2d_2(result1_activation, weight2, bias2, cov_result2);
+Max_pool#(8, 4, 4, 3, 2, 2) max_pool_2(cov_result2, result2);
+Relu_activation#(8, 2, 2, 3) relu_activation_2(result2, result2_activation);
+
+FullConnect#(8, 12, 20) fullConnect_1(result2_activation, weight3, bias3, result3);
+
+FullConnect#(8, 20, 1) fullConnect_2(result3, weight4, bias4, result);
+```
+
+上面这段代码创建了一个输入为14×14，包含两个卷积层，两个全连接层的CNN。卷积核大小是3×3，卷积层采用最大池化，窗口大小为2×2，并且使用ReLU激活函数，第一个卷积层有6个卷积核，第二个卷积层有3个卷积核。

QShen3_CNN-FPGA/src/Avg.v

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+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2018/04/15 14:18:06
+// Design Name: 
+// Module Name: Avg
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module Avg#(
+    parameter BITWIDTH = 8,
+    parameter LENGTH = 4
+    )
+    (
+    input [BITWIDTH * LENGTH - 1 : 0] data,
+    output reg signed [BITWIDTH - 1 : 0] result
+    );
+    
+    wire signed [BITWIDTH - 1:0] dataArray[0:LENGTH - 1];
+    genvar i;
+    generate      
+        for(i = 0; i < LENGTH; i = i + 1) begin
+            assign dataArray[i] = data[i * BITWIDTH + BITWIDTH - 1: i * BITWIDTH];
+        end
+    endgenerate
+    
+    integer j, sum;
+    always @(*) begin
+        sum = 0;
+        for(j = 0; j < LENGTH; j = j + 1) begin
+            sum = sum + dataArray[j];
+        end
+        result = sum / LENGTH;
+    end
+    
+endmodule

QShen3_CNN-FPGA/src/Avg_pool.v

@@ -0,0 +1,86 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2018/04/15 14:29:19
+// Design Name: 
+// Module Name: Avg_pool
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module Avg_pool#(
+    parameter integer BITWIDTH = 8,
+    
+    parameter integer DATAWIDTH = 28,
+    parameter integer DATAHEIGHT = 28,
+    parameter integer DATACHANNEL = 3,
+    
+    parameter integer KWIDTH = 2,
+    parameter integer KHEIGHT = 2
+    )
+    (
+    //input clk,
+    //input clken,
+    input [BITWIDTH * DATAWIDTH * DATAHEIGHT * DATACHANNEL - 1 : 0]data,
+    output [BITWIDTH * DATAWIDTH / KWIDTH * DATAHEIGHT / KHEIGHT * DATACHANNEL - 1 : 0] result
+    );
+    
+    wire [BITWIDTH - 1 : 0] dataArray[0 : DATACHANNEL - 1][0 : DATAHEIGHT-1][0 : DATAWIDTH - 1];
+    wire [BITWIDTH * KHEIGHT * KWIDTH - 1 : 0]paramArray [0: DATACHANNEL - 1][0: DATAHEIGHT / KHEIGHT - 1][0: DATAWIDTH / KWIDTH - 1];
+    
+    //wire [BITWIDTH * DATAWIDTH / KWIDTH * DATAHEIGHT / KHEIGHT * DATACHANNEL - 1 : 0] out;
+    
+    genvar i, j, k, m, n;
+    generate       
+        for(i = 0; i < DATACHANNEL; i = i + 1) begin
+            for(j = 0; j < DATAHEIGHT; j = j + 1) begin
+                for(k = 0; k < DATAWIDTH; k = k + 1) begin
+                    assign dataArray[i][j][k] = data[(i * DATAHEIGHT * DATAWIDTH + j * DATAHEIGHT + k) * BITWIDTH + BITWIDTH - 1:(i * DATAHEIGHT * DATAWIDTH + j * DATAHEIGHT + k) * BITWIDTH];
+                end
+            end
+        end      
+    endgenerate
+    
+    generate 
+        for(i = 0; i < DATACHANNEL; i = i + 1) begin
+            for(j = 0; j < DATAHEIGHT / KHEIGHT; j = j + 1) begin
+                for(k = 0; k < DATAWIDTH / KWIDTH; k = k + 1) begin
+                    for(m = j * 2; m < j * 2 + KHEIGHT; m = m + 1) begin
+                        for(n = k * 2; n < k * 2 + KWIDTH; n = n + 1) begin
+                            assign paramArray[i][j][k][((m - j * 2) * KWIDTH + n - k * 2) * BITWIDTH + BITWIDTH - 1:((m - j * 2) * KWIDTH + n - k * 2) * BITWIDTH] = dataArray[i][m][n];
+                        end
+                    end
+                end
+            end
+        end
+    endgenerate
+    
+    generate
+        for(i = 0; i < DATACHANNEL; i = i + 1) begin
+            for(j = 0; j < DATAHEIGHT / KHEIGHT; j = j + 1) begin
+                for(k = 0; k < DATAWIDTH / KWIDTH; k = k + 1) begin
+                    Avg#(BITWIDTH, KHEIGHT * KWIDTH) avg(paramArray[i][j][k], result[(i * DATAHEIGHT / KHEIGHT * DATAWIDTH / KWIDTH + j * DATAWIDTH / KWIDTH + k) * BITWIDTH + BITWIDTH - 1:(i * DATAHEIGHT / KHEIGHT * DATAWIDTH / KWIDTH + j * DATAWIDTH / KWIDTH + k) * BITWIDTH]);
+                end
+            end
+        end
+    endgenerate
+    
+    // always @(posedge clk) begin
+    //     if(clken == 1) begin
+    //         result = out;
+    //     end
+    // end
+    
+endmodule

QShen3_CNN-FPGA/src/Conv2d.v

@@ -0,0 +1,129 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2018/04/11 15:34:00
+// Design Name: 
+// Module Name: Conv2d
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module Conv2d #(
+    parameter integer BITWIDTH = 8,
+    
+    parameter integer DATAWIDTH = 28,
+    parameter integer DATAHEIGHT = 28,
+    parameter integer DATACHANNEL = 3,
+    
+    parameter integer FILTERHEIGHT = 5,
+    parameter integer FILTERWIDTH = 5,
+    parameter integer FILTERBATCH = 1,
+    
+    parameter integer STRIDEHEIGHT = 1,
+    parameter integer STRIDEWIDTH = 1,
+    
+    parameter integer PADDINGENABLE = 0
+    )
+    (
+    //input clk,
+    //input clken,
+    input [BITWIDTH * DATAWIDTH * DATAHEIGHT * DATACHANNEL - 1 : 0]data,
+    input [BITWIDTH * FILTERHEIGHT * FILTERWIDTH * DATACHANNEL * FILTERBATCH - 1 : 0]filterWeight,
+    input [BITWIDTH * FILTERBATCH - 1 : 0] filterBias,
+    output [(BITWIDTH * 2) * FILTERBATCH * (PADDINGENABLE == 0 ? (DATAWIDTH - FILTERWIDTH + 1) / STRIDEWIDTH : (DATAWIDTH / STRIDEWIDTH)) * (PADDINGENABLE == 0 ? (DATAHEIGHT - FILTERHEIGHT + 1) / STRIDEHEIGHT : (DATAHEIGHT / STRIDEHEIGHT)) - 1 : 0] result
+    );
+    
+    wire [BITWIDTH - 1 : 0] dataArray[0 : DATACHANNEL - 1][0 : DATAHEIGHT-1][0 : DATAWIDTH - 1];
+    wire [BITWIDTH - 1 : 0] dataArrayWithPadding[0 : DATACHANNEL - 1][0 : (PADDINGENABLE == 1 ? DATAHEIGHT + FILTERHEIGHT - 1 : DATAHEIGHT)-1][0 : (PADDINGENABLE == 1 ? DATAWIDTH + FILTERWIDTH - 1 : DATAWIDTH)-1];
+    wire [BITWIDTH * FILTERHEIGHT * FILTERWIDTH * DATACHANNEL - 1 : 0] paramArray[0: (PADDINGENABLE == 1 ? DATAHEIGHT / STRIDEHEIGHT: (DATAHEIGHT - FILTERHEIGHT + 1) / STRIDEHEIGHT)-1][0: (PADDINGENABLE == 1 ? DATAWIDTH / STRIDEWIDTH : (DATAWIDTH - FILTERWIDTH + 1) / STRIDEWIDTH)-1];
+    wire [BITWIDTH * DATACHANNEL * FILTERHEIGHT * FILTERWIDTH - 1 : 0] filterWeightArray[0: FILTERBATCH - 1];
+ 
+    wire [(BITWIDTH * 2) * FILTERBATCH * (PADDINGENABLE == 0 ? (DATAWIDTH - FILTERWIDTH + 1) / STRIDEWIDTH : (DATAWIDTH / STRIDEWIDTH)) * (PADDINGENABLE == 0 ? (DATAHEIGHT - FILTERHEIGHT + 1) / STRIDEHEIGHT : (DATAHEIGHT / STRIDEHEIGHT)) - 1 : 0] out;
+    
+    genvar i, j, k, m, n;
+    generate       
+        for(i = 0; i < DATACHANNEL; i = i + 1) begin
+            for(j = 0; j < DATAHEIGHT; j = j + 1) begin
+                for(k = 0; k < DATAWIDTH; k = k + 1) begin
+                    assign dataArray[i][j][k] = data[(i * DATAHEIGHT * DATAWIDTH + j * DATAHEIGHT + k) * BITWIDTH + BITWIDTH - 1:(i * DATAHEIGHT * DATAWIDTH + j * DATAHEIGHT + k) * BITWIDTH];
+                end
+            end
+        end      
+    endgenerate
+    
+    generate
+        for(i = 0; i < DATACHANNEL; i = i + 1) begin
+            for(m = 0; m < (PADDINGENABLE == 1 ? DATAHEIGHT + FILTERHEIGHT - 1 : DATAHEIGHT); m = m + 1) begin
+                for(n = 0; n < (PADDINGENABLE == 1 ? DATAWIDTH + FILTERWIDTH - 1 : DATAWIDTH); n = n + 1) begin
+                    if(PADDINGENABLE == 1) begin
+                        if(m < (FILTERHEIGHT / 2) || m > (DATAHEIGHT + FILTERHEIGHT / 2 - 1)) begin
+                            assign dataArrayWithPadding[i][m][n] = 0;
+                        end
+                        else if(n < (FILTERWIDTH / 2) || n > (DATAWIDTH + FILTERWIDTH / 2 - 1)) begin
+                            assign dataArrayWithPadding[i][m][n] = 0;
+                        end
+                        else begin
+                            assign dataArrayWithPadding[i][m][n] = dataArray[i][m - FILTERHEIGHT / 2][n - FILTERWIDTH / 2];
+                        end
+                    end
+                    else begin
+                        assign dataArrayWithPadding[i][m][n] = dataArray[i][m][n];
+                    end
+                end
+            end
+        end
+    endgenerate
+    
+    generate
+            for(j = FILTERHEIGHT / 2; j < (PADDINGENABLE == 1 ? DATAHEIGHT + FILTERHEIGHT - 1 - FILTERHEIGHT / 2: DATAHEIGHT - FILTERHEIGHT / 2); j = j + STRIDEHEIGHT) begin
+                for(k = FILTERWIDTH / 2; k < (PADDINGENABLE == 1 ? DATAWIDTH + FILTERWIDTH - 1 - FILTERWIDTH / 2 : DATAWIDTH - FILTERWIDTH / 2); k = k + STRIDEWIDTH) begin
+                    for(i = 0; i < DATACHANNEL; i = i + 1) begin
+                        for(m = j - FILTERHEIGHT / 2; m <= j + FILTERHEIGHT / 2; m = m + 1) begin
+                            for(n = k - FILTERWIDTH / 2; n <= k + FILTERWIDTH / 2; n = n + 1) begin
+                                assign paramArray[(j - FILTERHEIGHT / 2) / STRIDEHEIGHT][(k - FILTERWIDTH / 2) / STRIDEWIDTH][(i * FILTERHEIGHT * FILTERWIDTH + (m - j + FILTERHEIGHT / 2) * FILTERWIDTH + (n - k + FILTERWIDTH / 2)) * BITWIDTH + BITWIDTH - 1:(i * FILTERHEIGHT * FILTERWIDTH + (m - j + FILTERHEIGHT / 2) * FILTERWIDTH + (n - k + FILTERWIDTH / 2)) * BITWIDTH] = 
+                                    dataArrayWithPadding[i][m][n];
+                            end
+                        end
+                    end
+                end
+            end
+    endgenerate
+    
+    generate 
+        for(i = 0; i < FILTERBATCH; i = i + 1) begin
+            assign filterWeightArray[i] = filterWeight[(i + 1) * DATACHANNEL * FILTERHEIGHT * FILTERWIDTH * BITWIDTH - 1: i * DATACHANNEL * FILTERHEIGHT * FILTERWIDTH * BITWIDTH];
+        end
+    endgenerate
+    
+    generate
+        for(i = 0; i < FILTERBATCH; i = i + 1) begin
+            for(m = 0; m < (PADDINGENABLE == 1 ? DATAHEIGHT / STRIDEHEIGHT: (DATAHEIGHT - FILTERHEIGHT + 1) / STRIDEHEIGHT); m = m + 1) begin
+                for(n = 0; n < (PADDINGENABLE == 1 ? DATAWIDTH / STRIDEWIDTH : (DATAWIDTH - FILTERWIDTH + 1) / STRIDEWIDTH); n = n + 1) begin
+                        ConvKernel#(BITWIDTH, DATACHANNEL, FILTERHEIGHT, FILTERWIDTH) convKernel(paramArray[m][n], 
+                        filterWeightArray[i], 
+                        filterBias[(i + 1) * BITWIDTH - 1 :i * BITWIDTH],
+                        result[(i * (PADDINGENABLE == 1 ? DATAHEIGHT / STRIDEHEIGHT: (DATAHEIGHT - FILTERHEIGHT + 1) / STRIDEHEIGHT) * (PADDINGENABLE == 1 ? DATAWIDTH / STRIDEWIDTH : (DATAWIDTH - FILTERWIDTH + 1) / STRIDEWIDTH) * BITWIDTH * 2 + m * (PADDINGENABLE == 1 ? DATAWIDTH / STRIDEWIDTH : (DATAWIDTH - FILTERWIDTH + 1) / STRIDEWIDTH) * BITWIDTH * 2 + n) * 2 * BITWIDTH + 2 * BITWIDTH - 1:(i * (PADDINGENABLE == 1 ? DATAHEIGHT / STRIDEHEIGHT: (DATAHEIGHT - FILTERHEIGHT + 1) / STRIDEHEIGHT) * (PADDINGENABLE == 1 ? DATAWIDTH / STRIDEWIDTH : (DATAWIDTH - FILTERWIDTH + 1) / STRIDEWIDTH) * BITWIDTH * 2 + m * (PADDINGENABLE == 1 ? DATAWIDTH / STRIDEWIDTH : (DATAWIDTH - FILTERWIDTH + 1) / STRIDEWIDTH) * BITWIDTH * 2 + n * 2 * BITWIDTH)]);
+                end
+            end            
+        end
+    endgenerate
+    
+    // always @(posedge clk) begin
+    //     if(clken == 1) begin
+    //         result = out;
+    //     end
+    // end
+    
+endmodule

QShen3_CNN-FPGA/src/ConvKernel.v

@@ -0,0 +1,56 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2018/04/11 16:12:39
+// Design Name: 
+// Module Name: ConvKernel
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module ConvKernel#(
+    parameter integer BITWIDTH = 8,   
+    
+    parameter integer DATACHANNEL = 3, 
+    
+    parameter integer FILTERHEIGHT = 5,
+    parameter integer FILTERWIDTH = 5
+    )
+    (
+    input [BITWIDTH * DATACHANNEL * FILTERHEIGHT * FILTERWIDTH - 1 : 0]data,
+    input [BITWIDTH * DATACHANNEL * FILTERHEIGHT * FILTERWIDTH - 1 : 0]weight,
+    input [BITWIDTH - 1 : 0] bias,
+    output reg signed [BITWIDTH * 2 -1 : 0]result
+    );
+    
+    wire signed [BITWIDTH * 2 - 1 : 0]out[FILTERHEIGHT * FILTERWIDTH * DATACHANNEL - 1 : 0];
+    
+    generate
+        genvar i;
+        for(i = 0; i < FILTERHEIGHT * FILTERWIDTH * DATACHANNEL; i = i + 1) begin
+            Mult#(BITWIDTH) mult(data[(i + 1) * BITWIDTH - 1 : i * BITWIDTH], weight[(i + 1) * BITWIDTH - 1 : i * BITWIDTH], out[i]);
+        end
+    endgenerate
+    
+    integer j;
+    always @(*) begin
+        result = 0;
+        for(j = 0; j < FILTERHEIGHT * FILTERWIDTH * DATACHANNEL; j = j + 1) begin
+            result = result + out[j];
+        end
+        result = result + bias;
+    end
+    
+endmodule

QShen3_CNN-FPGA/src/FullConnect.v

@@ -0,0 +1,80 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2018/04/18 13:47:58
+// Design Name: 
+// Module Name: FullConnect
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module FullConnect#(
+    parameter BITWIDTH = 8,
+    
+    parameter LENGTH = 25,
+    
+    parameter FILTERBATCH = 1
+    )
+    (
+    //input clk,
+    //input clken,
+    input [BITWIDTH * LENGTH - 1 : 0] data,
+    input [BITWIDTH * LENGTH * FILTERBATCH - 1 : 0] weight,
+    input [BITWIDTH * FILTERBATCH - 1 : 0] bias,
+    output [BITWIDTH * 2 * FILTERBATCH - 1 : 0] result
+    );
+    
+    //reg [BITWIDTH * 2 * LENGTH * FILTERBATCH- 1:0] out;
+    wire [BITWIDTH * 2 - 1:0] out [0:FILTERBATCH - 1][0:LENGTH - 1];
+    wire signed [BITWIDTH - 1:0] biasArray[0:FILTERBATCH - 1];
+    reg signed [BITWIDTH * 2 - 1:0] resultArray [0:FILTERBATCH - 1];
+    
+    //wire [BITWIDTH * 2 * FILTERBATCH - 1 : 0] out2;
+    
+    genvar i, j;
+    generate
+        for(i = 0; i < FILTERBATCH; i = i + 1) begin
+            assign biasArray[i] = bias[(i + 1) * BITWIDTH - 1: i * BITWIDTH];
+            assign result[(i + 1) * BITWIDTH * 2 - 1: i * BITWIDTH * 2] = resultArray[i];
+        end
+    endgenerate
+    
+    generate 
+        for(i = 0; i < FILTERBATCH; i = i + 1) begin
+            for(j = 0; j < LENGTH; j = j + 1) begin
+                Mult#(BITWIDTH) mult(data[(j + 1) * BITWIDTH - 1:j * BITWIDTH], weight[(i * LENGTH + j) * BITWIDTH + BITWIDTH - 1 : (i * LENGTH + j) * BITWIDTH], out[i][j]);
+            end
+        end
+    endgenerate
+    
+    integer sum, m, n;
+    always @(*) begin
+        for(m = 0; m < FILTERBATCH; m = m + 1) begin
+            sum = 0;
+            for(n = 0; n < LENGTH; n = n + 1) begin
+                sum = sum + out[m][n];
+            end
+            sum = sum + biasArray[m];
+            resultArray[m] = sum;
+        end
+    end
+    
+    // always @(posedge clk) begin
+    //     if(clken == 1) begin
+    //         result = out2;
+    //     end
+    // end 
+    
+endmodule

QShen3_CNN-FPGA/src/Max.v

@@ -0,0 +1,50 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2018/04/15 13:56:38
+// Design Name: 
+// Module Name: Max
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module Max#(
+    parameter BITWIDTH = 8,
+    parameter LENGTH = 4
+    )
+    (
+    input [BITWIDTH * LENGTH - 1 : 0] data,
+    output reg signed [BITWIDTH - 1 : 0] result
+    );
+    
+    wire signed [BITWIDTH - 1:0] dataArray[0:LENGTH - 1];
+    genvar i;
+    generate      
+        for(i = 0; i < LENGTH; i = i + 1) begin
+            assign dataArray[i] = data[i * BITWIDTH + BITWIDTH - 1: i * BITWIDTH];
+        end
+    endgenerate
+    
+    integer j;
+    always @(*) begin
+        result = -127;
+        for(j = 0; j < LENGTH; j = j + 1) begin
+            if(dataArray[j] > result) begin
+                result = dataArray[j];
+            end
+        end
+    end
+    
+endmodule

QShen3_CNN-FPGA/src/Max_pool.v

@@ -0,0 +1,86 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2018/04/15 14:29:19
+// Design Name: 
+// Module Name: Max_pool
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module Max_pool#(
+    parameter integer BITWIDTH = 8,
+    
+    parameter integer DATAWIDTH = 28,
+    parameter integer DATAHEIGHT = 28,
+    parameter integer DATACHANNEL = 3,
+    
+    parameter integer KWIDTH = 2,
+    parameter integer KHEIGHT = 2
+    )
+    (
+    //input clk,
+    //input clken,
+    input [BITWIDTH * DATAWIDTH * DATAHEIGHT * DATACHANNEL - 1 : 0]data,
+    output reg [BITWIDTH * DATAWIDTH / KWIDTH * DATAHEIGHT / KHEIGHT * DATACHANNEL - 1 : 0] result
+    );
+    
+    wire [BITWIDTH - 1 : 0] dataArray[0 : DATACHANNEL - 1][0 : DATAHEIGHT-1][0 : DATAWIDTH - 1];
+    wire [BITWIDTH * KHEIGHT * KWIDTH - 1 : 0]paramArray [0: DATACHANNEL - 1][0: DATAHEIGHT / KHEIGHT - 1][0: DATAWIDTH / KWIDTH - 1];
+    
+    //wire [BITWIDTH * DATAWIDTH / KWIDTH * DATAHEIGHT / KHEIGHT * DATACHANNEL - 1 : 0] out;
+    
+    genvar i, j, k, m, n;
+    generate       
+        for(i = 0; i < DATACHANNEL; i = i + 1) begin
+            for(j = 0; j < DATAHEIGHT; j = j + 1) begin
+                for(k = 0; k < DATAWIDTH; k = k + 1) begin
+                    assign dataArray[i][j][k] = data[(i * DATAHEIGHT * DATAWIDTH + j * DATAHEIGHT + k) * BITWIDTH + BITWIDTH - 1:(i * DATAHEIGHT * DATAWIDTH + j * DATAHEIGHT + k) * BITWIDTH];
+                end
+            end
+        end      
+    endgenerate
+    
+    generate 
+        for(i = 0; i < DATACHANNEL; i = i + 1) begin
+            for(j = 0; j < DATAHEIGHT / KHEIGHT; j = j + 1) begin
+                for(k = 0; k < DATAWIDTH / KWIDTH; k = k + 1) begin
+                    for(m = j * 2; m < j * 2 + KHEIGHT; m = m + 1) begin
+                        for(n = k * 2; n < k * 2 + KWIDTH; n = n + 1) begin
+                            assign paramArray[i][j][k][((m - j * 2) * KWIDTH + n - k * 2) * BITWIDTH + BITWIDTH - 1:((m - j * 2) * KWIDTH + n - k * 2) * BITWIDTH] = dataArray[i][m][n];
+                        end
+                    end                   
+                end
+            end
+        end
+    endgenerate
+    
+    generate
+        for(i = 0; i < DATACHANNEL; i = i + 1) begin
+            for(j = 0; j < DATAHEIGHT / KHEIGHT; j = j + 1) begin
+                for(k = 0; k < DATAWIDTH / KWIDTH; k = k + 1) begin
+                    Max#(BITWIDTH, KHEIGHT * KWIDTH) max(paramArray[i][j][k], result[(i * DATAHEIGHT / KHEIGHT * DATAWIDTH / KWIDTH + j * DATAWIDTH / KWIDTH + k) * BITWIDTH + BITWIDTH - 1:(i * DATAHEIGHT / KHEIGHT * DATAWIDTH / KWIDTH + j * DATAWIDTH / KWIDTH + k) * BITWIDTH]);
+                end
+            end
+        end
+    endgenerate
+    
+    // always @(posedge clk) begin
+    //     if(clken == 1) begin
+    //         result = out;
+    //     end
+    // end
+    
+endmodule

QShen3_CNN-FPGA/src/Mult.v

@@ -0,0 +1,35 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2018/04/11 16:17:19
+// Design Name: 
+// Module Name: Mult
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module Mult#(
+    parameter BITWIDTH = 8
+    )
+    (
+    input signed [BITWIDTH-1:0] a,
+    input signed [BITWIDTH-1:0] b,
+    output signed [BITWIDTH * 2 - 1:0] c
+    );
+    
+    assign c = a * b;
+    //assign c = 1;
+    
+endmodule

QShen3_CNN-FPGA/src/Relu.v

@@ -0,0 +1,33 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2018/04/16 16:52:03
+// Design Name: 
+// Module Name: Relu
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module Relu#(
+    parameter BITWIDTH = 8,
+    parameter THRESSHOLD = 0
+    )
+    (
+    input signed [BITWIDTH - 1:0] data,
+    output signed [BITWIDTH - 1:0] result
+    );
+    
+    assign result = data > THRESSHOLD ? data : THRESSHOLD;
+endmodule

QShen3_CNN-FPGA/src/Relu_activation.v

@@ -0,0 +1,56 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 2018/04/16 16:57:49
+// Design Name: 
+// Module Name: Relu_activation
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module Relu_activation#(
+    parameter integer BITWIDTH = 8,
+
+    parameter integer DATAWIDTH = 28,
+    parameter integer DATAHEIGHT = 28,
+    parameter integer DATACHANNEL = 3
+    )
+    (
+    //input clk,
+    //input clken,
+    input [BITWIDTH * DATAHEIGHT * DATAWIDTH * DATACHANNEL - 1:0] data,
+    output reg [BITWIDTH * DATAHEIGHT * DATAWIDTH * DATACHANNEL - 1:0] result
+    );
+    
+    //wire [BITWIDTH * DATAHEIGHT * DATAWIDTH * DATACHANNEL - 1:0] out;
+    
+    genvar i, j, k;
+    generate
+        for(i = 0; i < DATACHANNEL; i = i + 1) begin
+            for(j = 0; j < DATAHEIGHT; j = j + 1) begin
+                for(k = 0; k < DATAWIDTH; k = k + 1) begin
+                    Relu#(BITWIDTH) relu(data[(i * DATAHEIGHT * DATAWIDTH + j * DATAWIDTH + k) * BITWIDTH + BITWIDTH - 1:(i * DATAHEIGHT * DATAWIDTH + j * DATAWIDTH + k) * BITWIDTH], result[(i * DATAHEIGHT * DATAWIDTH + j * DATAWIDTH + k) * BITWIDTH + BITWIDTH - 1:(i * DATAHEIGHT * DATAWIDTH + j * DATAWIDTH + k) * BITWIDTH]);
+                end
+            end
+        end
+    endgenerate
+
+    // always @(posedge clk) begin
+    //     if(clken == 1) begin
+    //         result = out;
+    //     end
+    // end    
+    
+endmodule

The-OpenROAD-Project_OpenSTA/.clang-format

@@ -0,0 +1,31 @@
+# This is "close" to correct but has a number of bugs that prevent
+# using it on the source tree.
+Language: Cpp
+BasedOnStyle: Google
+AccessModifierOffset: -2
+AlignOperands: false
+AllowAllArgumentsOnNextLine: false
+AllowAllConstructorInitializersOnNextLine: false
+AllowAllParametersOfDeclarationOnNextLine: false
+AllowShortIfStatementsOnASingleLine: Never
+AllowShortLoopsOnASingleLine: false
+AlwaysBreakAfterReturnType: TopLevel
+BinPackArguments: true
+# fails
+BinPackParameters: AlwaysOnePerLine
+BraceWrapping:   
+  AfterClass: true
+  AfterStruct: true
+  AfterFunction: true
+  BeforeElse: true
+BreakBeforeBinaryOperators: NonAssignment
+BreakBeforeBraces: Custom
+# fails if all initializers fit on one line
+BreakConstructorInitializers: AfterColon
+ColumnLimit: 85
+# fails
+ConstructorInitializerIndentWidth: 2
+IncludeBlocks: Preserve
+PackConstructorInitializers: Never
+PointerAlignment: Right
+SortIncludes: Never

The-OpenROAD-Project_OpenSTA/.clang-tidy

@@ -0,0 +1,82 @@
+Checks: >
+  clang-diagnostic-*,
+  clang-analyzer-*,
+  -clang-analyzer-core.NonNullParamChecker,
+  -clang-analyzer-core.CallAndMessage,
+  -clang-analyzer-core.uninitialized.UndefReturn,
+  -clang-analyzer-cplusplus.NewDeleteLeaks,
+  -clang-analyzer-optin.performance.Padding,
+  readability-*,
+  -readability-identifier-naming,
+  -readability-braces-around-statements,
+  -readability-convert-member-functions-to-static,
+  -readability-else-after-return,
+  -readability-function-cognitive-complexity,
+  -readability-inconsistent-ifelse-braces,
+  -readability-identifier-length,
+  -readability-implicit-bool-conversion,
+  -readability-isolate-declaration,
+  -readability-magic-numbers,
+  -readability-make-member-function-const,
+  -readability-math-missing-parentheses,
+  -readability-named-parameter,
+  -readability-qualified-auto,
+  -readability-redundant-access-specifiers,
+  -readability-simplify-boolean-expr,
+  -readability-static-definition-in-anonymous-namespace,
+  -readability-suspicious-call-argument,
+  -readability-uppercase-literal-suffix,
+  -readability-use-anyofallof,
+  google-*,
+  -google-readability-avoid-underscore-in-googletest-name,
+  -google-readability-braces-around-statements,
+  -google-readability-casting,
+  -google-readability-todo,
+  -google-runtime-references,
+  -google-explicit-constructor,
+  performance-*,
+  -performance-enum-size,
+  bugprone-*,
+  -bugprone-branch-clone,
+  -bugprone-easily-swappable-parameters,
+  -bugprone-exception-escape,
+  -bugprone-macro-parentheses,
+  -bugprone-move-forwarding-reference,
+  -bugprone-narrowing-conversions,
+  -bugprone-suspicious-missing-comma,
+  -bugprone-throwing-static-initialization,
+  modernize-*,
+  -modernize-avoid-bind,
+  -modernize-avoid-c-arrays,
+  -modernize-concat-nested-namespaces,
+  -modernize-macro-to-enum,
+  -modernize-pass-by-value,
+  -modernize-raw-string-literal,
+  -modernize-return-braced-init-list,
+  -modernize-use-auto,
+  -modernize-use-nodiscard,
+  -modernize-use-trailing-return-type,
+  -modernize-use-transparent-functors,
+  misc-*,
+  -misc-const-correctness,
+  -misc-multiple-inheritance,
+  -misc-no-recursion,
+  -misc-non-private-member-variables-in-classes,
+  -misc-redundant-expression,
+  -misc-unused-parameters,
+  -misc-use-anonymous-namespace,
+  -misc-use-internal-linkage,
+  -misc-include-cleaner
+
+# Only report diagnostics in headers under this tree (app/, include/sta/, build-generated
+# headers, etc.).
+# Excludes system and third-party paths such as /opt/local/include.
+HeaderFilterRegex: '.*/(app|cmake|dcalc|graph|liberty|network|parasitics|power|sdc|sdf|search|spice|tcl|util|verilog|include/sta|build/include/sta)/.*'
+
+# util/gzstream.hh
+# util/FlexDisableRegister.hh
+# Bison-generated parser headers (build/{Liberty,Verilog,...}Parse.hh)
+# Homebrew and MacPorts third-party headers.
+ExcludeHeaderFilterRegex: '(^/opt/(homebrew|local)/.*)|((.*/)?(gzstream\.hh|FlexDisableRegister\.hh|(Liberty|Verilog|Sdf|Spef|Saif|LibExpr)Parse\.hh)$)'
+SystemHeaders: false
+FormatStyle: none

The-OpenROAD-Project_OpenSTA/.cursor/rules/cpp-coding-standards.mdc

@@ -0,0 +1,73 @@
+---
+description: C++ coding standards and formatting for OpenSTA
+globs: ["**/*.cc", "**/*.hh", "**/*.h"]
+alwaysApply: true
+---
+
+# C++ Coding Standards
+
+## File-internal helpers (translation-unit local)
+
+- For helpers used only in one `.cc` file, put them in the **same namespace** as the rest of the implementation (e.g. `namespace sta { ... }`).
+- Mark them **`static`** at namespace scope so they have internal linkage.
+- **Do not** wrap them in an **anonymous namespace** in this project (no `namespace { ... }` file-static helpers). The user preference is `static` inside the real namespace, not a nested anonymous namespace inside `sta` or at file scope before `sta`.
+
+## Line Width
+
+- **Keep lines under 90 characters** to match `.clang-format` (ColumnLimit: 90).
+- Only break a line when it would exceed 90 characters. Do not introduce unnecessary line breaks when the expression fits on one line.
+- When a break is needed, break at logical points: after commas, before operators. Keep the first argument on the same line as the opening paren (do not break immediately after an opening paren).
+
+## Naming Conventions
+
+- **Classes**: Upper camel case (`ClassName`)
+- **Member functions**: Lower camel case (`memberFunction`)
+- **Member variables**: Snake case with trailing underscore (`member_variable_`)
+- **Functions**: Lower camel case (`functionName`)
+- **Variables**: Snake case
+
+## Code Style
+
+- Use `#pragma once` for header guards.
+- Return type on the line before the function name; arguments on separate lines when long.
+- No braces for single-line if/for; use braces for multi-line bodies.
+- Prefer `std::string` over `char*` for string members.
+- Prefer pass-by-value and move for sink parameters (parameters that get stored).
+
+## Control flow
+
+- Prefer positive `if` conditions that wrap the main logic instead of early
+  `continue` or `return` to skip work.
+- Example: use `if (!visited.contains(vertex)) { ... }` rather than
+  `if (visited.contains(vertex)) continue;`.
+
+## File Extensions
+
+- C++ source: `.cc`
+- C++ headers: `.hh`
+
+## Include order
+
+Sort `#include` lines **lexicographically by the path inside** `<>`
+or `""` (case-sensitive). Separate **groups** with a single blank line.
+
+### Translation units (`*.cc`)
+
+1. **Primary header(s)** for this file only:
+   - `#include "Stem.hh"` where `Stem` matches the basename of the `.cc` file (e.g. `Foo.cc` → `Foo.hh`).
+   - If the file uses a paired private header, include `#include "StemPvt.hh"` **immediately after** `Stem.hh` (e.g. `MakeTimingModel.cc` → `MakeTimingModel.hh` then `MakeTimingModelPvt.hh`).
+   - Do **not** pull in other headers just because their names share a prefix with `Stem` (e.g. `SearchClass.hh` is not a “primary” include for `Search.cc`; it belongs in the project group below).
+
+2. **System / standard library** headers: `#include <...>` lines, sorted alphabetically.
+
+3. **All other project** headers: `#include "..."` lines, sorted alphabetically (including `search/Crpr.hh`-style paths and includes from `liberty/`, etc.).
+
+If a **comment or special block** intentionally splits the include list (e.g. a third-party note before `#include "cudd.h"`), keep that structure; sort only within each contiguous run of `#include` lines unless merging groups is clearly safe.
+
+### Headers (`*.hh`)
+
+After `#pragma once` (and the file’s license block, if present):
+
+1. **System** `#include <...>` lines, sorted alphabetically.
+
+2. **Project** `#include "..."` lines, sorted alphabetically.

The-OpenROAD-Project_OpenSTA/.cursor/rules/cpp-indentation.mdc

@@ -0,0 +1,43 @@
+---
+description: C++ function call indentation for OpenSTA
+globs: ["**/*.cc", "**/*.hh", "**/*.h"]
+alwaysApply: false
+---
+
+# C++ Function Call Indentation
+
+## Short Calls — Single Line
+
+When arguments fit within the column limit (90 chars), keep them on one line:
+
+```cpp
+// ✅ GOOD
+adjusted_data_arrival = delaySum(required, data_shift_to_enable_clk, this);
+
+// ❌ BAD
+adjusted_data_arrival = delaySum(required,
+                 data_shift_to_enable_clk,
+                 this);
+```
+
+## Nested Function Calls — Align Under Inner Call
+
+When breaking nested calls across lines:
+- Indent continuation lines of the inner call under its first argument (align with content after `innerFunc(`).
+- Place remaining outer arguments on the same line as the inner call's closing `)`, indented under the outer function.
+
+```cpp
+// ✅ GOOD
+required = delayDiff(delaySum(max_delay,
+                              search_->clkPathArrival(disable_path),
+                              this),
+                     margin, this);
+
+// ❌ BAD
+required = delayDiff(
+             delaySum(max_delay,
+                      search_->clkPathArrival(disable_path),
+                      this),
+             margin,
+             this);
+```

The-OpenROAD-Project_OpenSTA/.cursor/rules/opensta-tests.mdc

@@ -0,0 +1,13 @@
+---
+description: Where OpenSTA regression tests live (pvt/test vs public test/)
+alwaysApply: true
+---
+
+# OpenSTA tests and regression
+
+- **Primary suite:** Most regression tests, Tcl drivers, and golden `.ok` files live under **`pvt/test/`** (private / separate repo, often opened as a second workspace root alongside `master`).
+- **Public subset:** **`test/`** at the OpenSTA repo root holds a smaller set of tests shipped with the public tree (e.g. `test/regression`, `*.tcl`, `*.ok` there).
+
+When searching for a test name, regression lists, or updating goldens, **check `pvt/test` first**, then `test/`.
+
+Typical driver: `pvt/test/regression` (or `test/regression` for the public list). Built `sta` binary is usually `master/build/sta` relative to the main checkout.

The-OpenROAD-Project_OpenSTA/.dockerignore

@@ -0,0 +1,4 @@
+.gitignore
+Dockerfile
+README
+INSTALL

The-OpenROAD-Project_OpenSTA/.github/ISSUE_TEMPLATE/bug_report.md

@@ -0,0 +1,10 @@
+---
+name: Bug report
+about: File upstream
+title: ''
+labels: ''
+assignees: ''
+
+---
+
+Issues or PRs should be filed with the upstream [parallaxsw/OpenSTA](https://github.com/parallaxsw/OpenSTA).  This is effectively a fork (though not strictly for historical reasons).

The-OpenROAD-Project_OpenSTA/.github/dependabot.yml

@@ -0,0 +1,25 @@
+version: 2
+updates:
+  - package-ecosystem: "github-actions"
+    directory: "/"
+    schedule:
+      interval: "daily"
+    open-pull-requests-limit: 5
+    cooldown:
+      default-days: 7
+    groups:
+      actions:
+        patterns:
+          - "*"
+
+  - package-ecosystem: "docker"
+    directory: "/"
+    schedule:
+      interval: "daily"
+    open-pull-requests-limit: 5
+    cooldown:
+      default-days: 7
+    groups:
+      images:
+        patterns:
+          - "*"

The-OpenROAD-Project_OpenSTA/.github/workflows/buildifier.yaml

@@ -0,0 +1,44 @@
+name: Lint Bazel
+
+on:
+  push:
+    branches:
+      - master
+  pull_request:
+    branches:
+      - master
+
+jobs:
+  buildifier:
+    runs-on: 'ubuntu-latest'
+    strategy:
+      fail-fast: false
+      matrix:
+        check:
+          - name: Run buildifier format
+            run: ./buildifier -r -mode=check -lint=off .
+          - name: Run buildifier lint
+            run: ./buildifier -r -lint=warn .
+    name: ${{ matrix.check.name }}
+    env:
+      BUILDIFIER_VERSION: v8.2.1
+
+    steps:
+      - name: Checkout Code
+        uses: actions/checkout@de0fac2e4500dabe0009e67214ff5f5447ce83dd  # v6.0.2
+
+      - name: Cache buildifier
+        id: cache-buildifier
+        uses: actions/cache@27d5ce7f107fe9357f9df03efb73ab90386fccae  # v5.0.5
+        with:
+          path: ./buildifier
+          key: ${{ runner.os }}-buildifier-${{ env.BUILDIFIER_VERSION }}
+
+      - name: Download buildifier
+        if: steps.cache-buildifier.outputs.cache-hit != 'true'
+        run: |
+          wget https://github.com/bazelbuild/buildtools/releases/download/${BUILDIFIER_VERSION}/buildifier-linux-amd64 -O buildifier
+          chmod +x buildifier
+
+      - name: ${{ matrix.check.name }}
+        run: ${{ matrix.check.run }}

The-OpenROAD-Project_OpenSTA/.github/workflows/ci.yml

@@ -0,0 +1,108 @@
+name: CI
+
+on:
+  push:
+  pull_request:
+
+jobs:
+  # Primary native Linux build used for install artifacts.
+  linux-ubuntu:
+    if: github.repository_owner != 'The-OpenROAD-Project-private'
+    runs-on: ubuntu-latest
+    steps:
+      - name: Checkout
+        uses: actions/checkout@9c091bb21b7c1c1d1991bb908d89e4e9dddfe3e0  # v7.0.0
+        with:
+          submodules: true
+
+      - name: Set up dependencies
+        run: |
+          sudo apt-get update
+          sudo apt-get install -y \
+                flex \
+                libfl-dev \
+                bison \
+                tcl-dev \
+                tcl-tclreadline \
+                libeigen3-dev \
+                ninja-build \
+                libgtest-dev
+
+      - name: Set up cudd-3.0.0
+        run: |
+          wget https://github.com/oscc-ip/artifact/releases/download/cudd-3.0.0/build.tar.gz
+          mkdir -p cudd
+          tar -zxvf build.tar.gz -Ccudd
+
+      - name: Build
+        run: |
+          mkdir build
+          cd build
+          cmake .. -G Ninja -DCUDD_DIR=$(pwd)/../cudd -DCMAKE_INSTALL_PREFIX=$(pwd)/install -DCMAKE_BUILD_TYPE=Release
+          cmake --build . --target all -- -j $(nproc)
+          cmake --install .
+          tar -zcvf build.tar.gz -Cinstall .
+
+      - name: Test
+        run: |
+          cd test
+          ./regression
+
+      - name: Upload Artifacts
+        uses: actions/upload-artifact@043fb46d1a93c77aae656e7c1c64a875d1fc6a0a  # v7.0.1
+        if: ${{ !cancelled() }}
+        with:
+          name: artifact-ubuntu
+          path: |
+            build/install/*
+          retention-days: 1
+
+      - name: Upload Test Result
+        uses: actions/upload-artifact@043fb46d1a93c77aae656e7c1c64a875d1fc6a0a  # v7.0.1
+        if: ${{ !cancelled() }}
+        with:
+          name: result-ubuntu
+          path: |
+            test/results/*
+
+  # Native macOS coverage via Brewfile.
+  macos:
+    if: github.repository_owner != 'The-OpenROAD-Project-private'
+    runs-on: macos-latest
+    timeout-minutes: 30
+    steps:
+      - name: Checkout
+        uses: actions/checkout@9c091bb21b7c1c1d1991bb908d89e4e9dddfe3e0  # v7.0.0
+        with:
+          submodules: true
+
+      - name: Install dependencies
+        run: brew bundle
+
+      - name: Build
+        run: |
+          eval "$(/opt/homebrew/bin/brew shellenv)"
+          export PATH="$(brew --prefix flex)/bin:$PATH"
+          export PATH="$(brew --prefix bison)/bin:$PATH"
+          export TCL_LIBRARY="$(brew --prefix tcl-tk@8)/lib/libtcl8.6.dylib"
+          export TCL_INCLUDE_PATH="$(brew --prefix tcl-tk@8)/include/tcl-tk"
+          export FLEX_INCLUDE_DIR="$(brew --prefix flex)/include"
+          cmake -S . -B build \
+            -D TCL_LIBRARY=$TCL_LIBRARY \
+            -D TCL_INCLUDE_PATH=$TCL_INCLUDE_PATH \
+            -D FLEX_INCLUDE_DIR=$FLEX_INCLUDE_DIR \
+            -DCMAKE_BUILD_TYPE=Release
+          cmake --build build -j "$(sysctl -n hw.ncpu)"
+
+      - name: Test
+        run: |
+          cd test
+          ./regression || (cat results/diffs && exit 1)
+
+      - name: Upload Test Result
+        uses: actions/upload-artifact@043fb46d1a93c77aae656e7c1c64a875d1fc6a0a  # v7.0.1
+        if: ${{ !cancelled() }}
+        with:
+          name: result-macos
+          path: |
+            test/results/*

The-OpenROAD-Project_OpenSTA/.github/workflows/github-actions-are-differences-found.yml

@@ -0,0 +1,20 @@
+name: Check that OK files are up to date
+
+on:
+  pull_request:
+
+jobs:
+  No-Diffs-In-Ok-Files:
+    runs-on: ${{ vars.USE_SELF_HOSTED == 'true' && 'self-hosted' || 'ubuntu-latest' }}
+    steps:
+      - name: Check out repository code
+        uses: actions/checkout@de0fac2e4500dabe0009e67214ff5f5447ce83dd  # v6.0.2
+        with:
+          fetch-depth: 0
+      - name: Check ok files
+        run: |
+          set +e
+          grep --include="*.ok" -Rn "Differences found "
+          if [[ "$?" == "0" ]]; then
+            exit 1
+          fi

The-OpenROAD-Project_OpenSTA/.github/workflows/on-delete.yml

@@ -0,0 +1,34 @@
+name: Cleanup staging branch on delete
+
+on:
+  delete:
+
+env:
+  ROT13_STAGING_OWNER: ${{ secrets.ROT13_STAGING_OWNER }}
+  ROT13_UPSTREAM_OWNER: ${{ secrets.ROT13_UPSTREAM_OWNER }}
+  ROT13_UPSTREAM_BRANCH: ${{ secrets.ROT13_UPSTREAM_BRANCH }}
+
+jobs:
+  Delete-From-Staging:
+    name: Delete branch from staging
+
+    runs-on: ${{ vars.USE_SELF_HOSTED == 'true' && 'self-hosted' || 'ubuntu-latest' }}
+
+    permissions:
+      # Read-only access so we don't accidentally try to push to *this* repository.
+      contents: read
+
+    # Only run on the private repository.
+    if: github.event.repository.private
+    steps:
+    - name: Detect configuration.
+      uses: The-OpenROAD-Project/actions/auto_config@main
+
+    - name: Delete branch from staging repository.
+      uses: The-OpenROAD-Project/actions/delete_from@main
+      continue-on-error: true
+      with:
+        owner: ${{ env.STAGING_OWNER }}
+        repo: ${{ env.STAGING_REPO }}
+        branch: ${{ env.STAGING_BRANCH }}
+        deployToken: ${{ secrets.STAGING_GITHUB_TOKEN }}

The-OpenROAD-Project_OpenSTA/.github/workflows/on-label.yml

@@ -0,0 +1,90 @@
+name: Labelled Ready to Sync Public
+
+on:
+  pull_request:
+    types: [labeled]
+
+env:
+  ROT13_STAGING_OWNER: ${{ secrets.ROT13_STAGING_OWNER }}
+  ROT13_UPSTREAM_OWNER: ${{ secrets.ROT13_UPSTREAM_OWNER }}
+  ROT13_UPSTREAM_BRANCH: ${{ secrets.ROT13_UPSTREAM_BRANCH }}
+
+jobs:
+  Push-To-Staging:
+    name: Push to staging
+    runs-on: ${{ vars.USE_SELF_HOSTED == 'true' && 'self-hosted' || 'ubuntu-latest' }}
+
+    permissions:
+      # Read-only access so we don't accidentally try to push to *this* repository.
+      contents: read
+      # Pull request write access, so we can remove the label.
+      issues: write
+      pull-requests: write
+      # Deployment write access, so we can add the nice deployment info.
+      deployments: write
+
+    # Only run on the private repository.
+    if: github.event.repository.private && github.event.label.name == 'Ready To Sync Public'
+    steps:
+    - name: Detect configuration
+      uses: The-OpenROAD-Project/actions/auto_config@main
+
+    - name: Removing label '${{ github.event.label.name }}'
+      uses: The-OpenROAD-Project/actions/remove_label@main
+      continue-on-error: true
+
+    - name: Clone repository
+      uses: The-OpenROAD-Project/actions/clone_from@main
+      with:
+        branch: ${{ env.PRIVATE_BRANCH }}
+        checkout: true
+
+    - name: Run security scan
+      uses: The-OpenROAD-Project/actions/security_scan_on_push@main
+
+    - name: Push to staging repository.
+      uses: The-OpenROAD-Project/actions/push_to@main
+      with:
+        owner: ${{ env.STAGING_OWNER }}
+        repo: ${{ env.STAGING_REPO }}
+        branch: ${{ env.STAGING_BRANCH }}
+        deployToken: ${{ secrets.STAGING_GITHUB_TOKEN }}
+        force: true
+
+    - id: resolve_key
+      name: Compute per-user secret key
+      env:
+        PR_AUTHOR: ${{ github.event.pull_request.user.login }}
+      run: |
+        key=$(echo "$PR_AUTHOR" | tr 'a-z-' 'A-Z_')
+        echo "key=$key" >> "$GITHUB_OUTPUT"
+
+    - id: resolve_token
+      name: Pick per-user PAT or fall back to bot token
+      env:
+        USER_PAT: ${{ secrets[format('PAT_{0}', steps.resolve_key.outputs.key)] }}
+        BOT_TOKEN: ${{ secrets.STAGING_GITHUB_TOKEN }}
+      run: |
+        if [ -n "$USER_PAT" ]; then
+          echo "::add-mask::$USER_PAT"
+          echo "token=$USER_PAT" >> "$GITHUB_OUTPUT"
+          echo "source=user-pat" >> "$GITHUB_OUTPUT"
+          echo "Using per-user PAT for PR creation"
+        else
+          echo "::add-mask::$BOT_TOKEN"
+          echo "token=$BOT_TOKEN" >> "$GITHUB_OUTPUT"
+          echo "source=bot-fallback" >> "$GITHUB_OUTPUT"
+          echo "No per-user PAT found; falling back to bot token"
+        fi
+
+    - id: send_pr
+      name: Create PR if needed.
+      uses: The-OpenROAD-Project/actions/send_pr@main
+      env:
+        STAGING_GITHUB_TOKEN: ${{ steps.resolve_token.outputs.token }}
+
+    - name: Linking to PR using deployment.
+      uses: The-OpenROAD-Project/actions/link_pr@main
+      env:
+        GITHUB_TOKEN: ${{ github.token }}
+        UPSTREAM_PR: ${{ steps.send_pr.outputs.pr }}

The-OpenROAD-Project_OpenSTA/.github/workflows/on-push.yml

@@ -0,0 +1,16 @@
+name: Scan Code with pre commit trigger
+
+on:
+  push:
+  pull_request:
+    branches:
+    - master
+
+jobs:
+  Security-Scan:
+    runs-on: ${{ vars.USE_SELF_HOSTED == 'true' && 'self-hosted' || 'ubuntu-latest' }}
+    steps:
+      - name: Check out repository code
+        uses: actions/checkout@de0fac2e4500dabe0009e67214ff5f5447ce83dd  # v6.0.2
+      - name: run security_scan_on_push
+        uses: The-OpenROAD-Project/actions/security_scan_on_push@main

The-OpenROAD-Project_OpenSTA/.github/workflows/sync-from-upstream.yml

@@ -0,0 +1,46 @@
+name: Automatically sync branch from upstream.
+
+on:
+  schedule:
+  - cron: "*/5 * * * *"
+
+  workflow_dispatch:
+    inputs:
+      force:
+        description: Use GitHub --force push.
+        default:
+
+  repository_dispatch:
+
+
+jobs:
+  Sync-Branch-From-Upstream:
+    name: Automatic sync 'master' from The-OpenROAD-Project/OpenSTA
+    runs-on: ${{ vars.USE_SELF_HOSTED == 'true' && 'self-hosted' || 'ubuntu-latest' }}
+
+    # Only allow one action to run at a time.
+    concurrency: sync-branch-from-upstream
+
+    # Action needs no permissions, as push is granted via adding a deploy key
+    # with write access to the $DEPLOY_KEY secret.
+    permissions:
+      contents: read
+
+    # Don't run on the upstream repository and only run on the right branch.
+    if: ${{ (github.repository != 'The-OpenROAD-Project/OpenSTA') && endsWith(github.ref, '/master') }}
+
+    steps:
+
+    - uses: The-OpenROAD-Project/actions/upstream_sync@main
+      env:
+        HAS_DEPLOY_KEY: ${{ !!(secrets.DEPLOY_KEY) }}
+      if: ${{ env.HAS_DEPLOY_KEY == 'true' }}
+      with:
+        upstreamRepo: The-OpenROAD-Project/OpenSTA
+        upstreamBranch: master
+        # To always overwrite master branch, set UPSTREAM_SYNC to the exact
+        # string 'always overwrite master branch'.
+        # You can also manually trigger a workflow dispatch with the force
+        # value equal to 'true'.
+        force: ${{ github.event.inputs.force || (secrets.UPSTREAM_SYNC == 'always overwrite master branch') }}
+        deployKey: ${{ secrets.DEPLOY_KEY }}

The-OpenROAD-Project_OpenSTA/.gitignore

@@ -0,0 +1,35 @@
+*.rej
+*.orig
+TAGS
+*~
+\#*#
+.#*
+.~lock.*\.*#
+.DS_Store
+.vscode
+.idea
+Makefile
+gmon.out
+
+cmake-build-debug
+coverage-output
+build
+pvt
+
+# iverilog turd
+examples/gcd_tb
+
+doc/._Sta.docx
+
+test/results
+*/test/results
+# ngspice turd
+test/b3v3_1check.log
+
+doc/messages.txt
+
+# clangd turds
+.cache/
+
+# openroad ctest turds
+cmake_test*

The-OpenROAD-Project_OpenSTA/BUILD.bazel

@@ -0,0 +1,419 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright (c) 2025, The OpenROAD Authors
+
+load("@rules_cc//cc:cc_binary.bzl", "cc_binary")
+load("@rules_cc//cc:cc_library.bzl", "cc_library")
+load("//bazel:bison.bzl", "genyacc")
+load("//bazel:flex.bzl", "genlex")
+load("//bazel:tcl_encode_sta.bzl", "tcl_encode_sta")
+load("//bazel:tcl_wrap_cc.bzl", "tcl_wrap_cc")
+
+package(
+    default_visibility = ["//:__subpackages__"],
+    #    features = ["layering_check"],
+)
+
+genlex(
+    name = "LibExprLex",
+    src = "liberty/LibExprLex.ll",
+    out = "liberty/LibExprLex.cc",
+    prefix = "LibExprLex_",
+)
+
+genyacc(
+    name = "LibExprParse",
+    src = "liberty/LibExprParse.yy",
+    header_out = "liberty/LibExprParse.hh",
+    prefix = "LibExprParse_",
+    source_out = "liberty/LibExprParse.cc",
+)
+
+# Liberty Parser
+genlex(
+    name = "LibertyLex",
+    src = "liberty/LibertyLex.ll",
+    out = "liberty/LibertyLex.cc",
+    prefix = "LibertyLex_",
+)
+
+genyacc(
+    name = "LibertyParser",
+    src = "liberty/LibertyParse.yy",
+    extra_outs = ["liberty/LibertyLocation.hh"],
+    header_out = "liberty/LibertyParse.hh",
+    prefix = "LibertyParse_",
+    source_out = "liberty/LibertyParse.cc",
+)
+
+# Spef scan/parse.
+genlex(
+    name = "SpefLex",
+    src = "parasitics/SpefLex.ll",
+    out = "parasitics/SpefLex.cc",
+    prefix = "SpefLex_",
+)
+
+genyacc(
+    name = "SpefParser",
+    src = "parasitics/SpefParse.yy",
+    extra_outs = ["parasitics/SpefLocation.hh"],
+    header_out = "parasitics/SpefParse.hh",
+    prefix = "SpefParse_",
+    source_out = "parasitics/SpefParse.cc",
+)
+
+# Verilog scan/parse.
+genlex(
+    name = "VerilogLex",
+    src = "verilog/VerilogLex.ll",
+    out = "verilog/VerilogLex.cc",
+    prefix = "VerilogLex_",
+)
+
+genyacc(
+    name = "VerilogParser",
+    src = "verilog/VerilogParse.yy",
+    extra_outs = ["verilog/VerilogLocation.hh"],
+    header_out = "verilog/VerilogParse.hh",
+    prefix = "VerilogParse_",
+    source_out = "verilog/VerilogParse.cc",
+)
+
+# sdf scan/parse.
+genlex(
+    name = "SdfLex",
+    src = "sdf/SdfLex.ll",
+    out = "sdf/SdfLex.cc",
+    prefix = "SdfLex_",
+)
+
+genyacc(
+    name = "SdfParser",
+    src = "sdf/SdfParse.yy",
+    extra_outs = ["sdf/SdfLocation.hh"],
+    header_out = "sdf/SdfParse.hh",
+    prefix = "SdfParse_",
+    source_out = "sdf/SdfParse.cc",
+)
+
+genlex(
+    name = "SaifLex",
+    src = "power/SaifLex.ll",
+    out = "power/SaifLex.cc",
+    prefix = "SaifLex_",
+)
+
+genyacc(
+    name = "SaifParser",
+    src = "power/SaifParse.yy",
+    extra_outs = ["power/SaifLocation.hh"],
+    header_out = "power/SaifParse.hh",
+    prefix = "SaifParse_",
+    source_out = "power/SaifParse.cc",
+)
+
+# The order here is very important as the script to encode these relies on it
+tcl_srcs = [
+    "tcl/Util.tcl",
+    "tcl/CmdUtil.tcl",
+    "tcl/Init.tcl",
+    "tcl/CmdArgs.tcl",
+    "tcl/Property.tcl",
+    "tcl/Sta.tcl",
+    "sdc/Variables.tcl",
+    "tcl/Splash.tcl",
+    "graph/Graph.tcl",
+    "liberty/Liberty.tcl",
+    "network/Link.tcl",
+    "network/Network.tcl",
+    "network/NetworkEdit.tcl",
+    "search/Search.tcl",
+    "dcalc/DelayCalc.tcl",
+    "parasitics/Parasitics.tcl",
+    "power/Power.tcl",
+    "sdc/Sdc.tcl",
+    "sdf/Sdf.tcl",
+    "verilog/Verilog.tcl",
+    "spice/WriteSpice.tcl",
+]
+
+exports_files([
+    "etc/TclEncode.tcl",
+])
+
+# Files used only by the standalone OpenSTA shell. OpenROAD supplies its own
+# equivalents (Init via ord, Link/Verilog via dbSta), so they are excluded from
+# the set re-exported to dbSta.
+sta_only_tcl = [
+    "tcl/Init.tcl",
+    "network/Link.tcl",
+    "verilog/Verilog.tcl",
+]
+
+# Re-exported to dbSta (and thus the OpenROAD binary). Derived from tcl_srcs so
+# a new command file added there automatically flows here unless explicitly
+# listed in sta_only_tcl. Single source of truth = tcl_srcs.
+exported_tcl = [f for f in tcl_srcs if f not in sta_only_tcl]
+
+filegroup(
+    name = "tcl_scripts",
+    srcs = exported_tcl,
+    visibility = [
+        "//:__subpackages__",
+    ],
+)
+
+tcl_encode_sta(
+    name = "StaTclInitVar",
+    srcs = tcl_srcs,
+    char_array_name = "tcl_inits",
+)
+
+genrule(
+    name = "StaConfig",
+    srcs = [],
+    outs = ["include/sta/StaConfig.hh"],
+    cmd = """echo -e '
+    #pragma once
+    #define STA_VERSION "2.7.0"
+    #define STA_GIT_SHA1 "f21d4a3878e2531e3af4930818d9b5968aad9416"
+    #define SSTA 0
+    #define ZLIB_FOUND
+    #define HAVE_CXX_STD_FORMAT 1' > \"$@\"
+    """,
+    visibility = ["//:__subpackages__"],
+)
+
+cc_library(
+    name = "config",
+    hdrs = [":StaConfig"],
+    includes = [
+        "include",
+        "include/sta",
+    ],
+)
+
+filegroup(
+    name = "sta_swig_files",
+    srcs = [
+        "app/StaApp.i",
+        "dcalc/DelayCalc.i",
+        "graph/Graph.i",
+        "liberty/Liberty.i",
+        "network/Network.i",
+        "network/NetworkEdit.i",
+        "parasitics/Parasitics.i",
+        "power/Power.i",
+        "sdc/Sdc.i",
+        "sdf/Sdf.i",
+        "search/Property.i",
+        "search/Search.i",
+        "spice/WriteSpice.i",
+        "tcl/Exception.i",
+        "tcl/StaTclTypes.i",
+        "util/Util.i",
+        "verilog/Verilog.i",
+    ],
+    visibility = ["//:__subpackages__"],
+)
+
+tcl_wrap_cc(
+    name = "StaApp",
+    srcs = [
+        ":sta_swig_files",
+    ],
+    namespace_prefix = "sta",
+    root_swig_src = "app/StaApp.i",
+    swig_includes = [
+        ".",
+    ],
+)
+
+parser_cc = [
+    # Liberty Expression Parser
+    ":liberty/LibExprParse.cc",
+    ":liberty/LibExprLex.cc",
+    # Liberty Parser
+    ":liberty/LibertyLex.cc",
+    ":liberty/LibertyParse.cc",
+    # Spef scan/parse.
+    ":parasitics/SpefLex.cc",
+    ":parasitics/SpefParse.cc",
+    # Verilog scan/parse.
+    ":verilog/VerilogLex.cc",
+    ":verilog/VerilogParse.cc",
+    # sdf scan/parse.
+    ":sdf/SdfLex.cc",
+    ":sdf/SdfParse.cc",
+    # Saif scan/parse.
+    ":power/SaifLex.cc",
+    ":power/SaifParse.cc",
+]
+
+parser_headers = [
+    # Liberty Expression Parser
+    ":liberty/LibExprParse.hh",
+    # Liberty Parser
+    ":liberty/LibertyParse.hh",
+    ":liberty/LibertyLocation.hh",
+    # Spef scan/parse.
+    ":parasitics/SpefParse.hh",
+    ":parasitics/SpefLocation.hh",
+    # Verilog scan/parse.
+    ":verilog/VerilogParse.hh",
+    ":verilog/VerilogLocation.hh",
+    # sdf scan/parse.
+    ":sdf/SdfParse.hh",
+    ":sdf/SdfLocation.hh",
+    # Saif scan/parse.
+    ":power/SaifParse.hh",
+    ":power/SaifLocation.hh",
+]
+
+cc_binary(
+    name = "opensta",
+    srcs = [
+        "app/Main.cc",
+        ":StaApp",
+        ":StaTclInitVar",
+    ],
+    copts = [
+        "-Wno-error",
+        "-Wall",
+        "-Wextra",
+        "-pedantic",
+        "-Wno-cast-qual",  # typically from TCL swigging
+        "-Wno-missing-braces",  # typically from TCL swigging
+        "-Wredundant-decls",
+        "-Wformat-security",
+        "-Wno-unused-parameter",
+        "-Wno-sign-compare",
+    ],
+    defines = ["BAZEL_BUILD"],
+    features = ["-use_header_modules"],
+    includes = [
+        "",
+        "dcalc",
+        "include/sta",
+        "util",
+    ],
+    malloc = "@tcmalloc//tcmalloc",
+    visibility = ["//visibility:public"],
+    deps = [
+        ":config",
+        ":opensta_lib",
+        "//:tcl_readline_setup",
+        "//bazel:tcl_library_init",
+        "@tcl_lang//:tcl",
+    ],
+)
+
+cc_library(
+    name = "opensta_lib",
+    srcs = parser_cc +
+           parser_headers + glob(
+        include = [
+            "dcalc/*.cc",
+            "dcalc/*.hh",
+            "graph/*.cc",
+            "liberty/*.cc",
+            "liberty/*.hh",
+            "network/*.cc",
+            "parasitics/*.cc",
+            "parasitics/*.hh",
+            "power/*.cc",
+            "power/*.hh",
+            "sdc/*.cc",
+            "sdc/*.hh",
+            "sdf/*.cc",
+            "sdf/*.hh",
+            "search/*.cc",
+            "search/*.hh",
+            "spice/*.cc",
+            "spice/*.hh",
+            "tcl/*.cc",
+            "util/*.cc",
+            "util/*.hh",
+            "verilog/*.cc",
+            "verilog/*.hh",
+        ],
+        exclude = [
+            "graph/Delay.cc",
+            "liberty/LibertyExt.cc",
+            "util/Machine*.cc",
+        ],
+    ) + [
+        "app/StaMain.cc",
+    ] + select({
+        "@platforms//os:linux": ["util/MachineLinux.cc"],
+        "@platforms//os:osx": ["util/MachineApple.cc"],
+        "@platforms//os:windows": ["util/MachineWin32.cc"],
+        "//conditions:default": ["util/MachineUnknown.cc"],
+    }),
+    hdrs = glob(
+        include = ["include/sta/*.hh"],
+    ) + [
+        # Required for swig
+        "search/Tag.hh",
+        "dcalc/ArcDcalcWaveforms.hh",
+        "power/Power.hh",
+        "power/VcdParse.hh",
+        "power/VcdReader.hh",
+        "power/SaifReader.hh",
+        "sdf/SdfReader.hh",
+        "sdf/ReportAnnotation.hh",
+        "sdf/SdfWriter.hh",
+        "search/Levelize.hh",
+        "search/ReportPath.hh",
+        "spice/WritePathSpice.hh",
+        "dcalc/PrimaDelayCalc.hh",
+        # Needed by src/dbSta to synthesize LibertyCells programmatically.
+        "liberty/LibertyBuilder.hh",
+    ],
+    copts = [
+        "-Wno-error",
+        "-Wall",
+        "-Wextra",
+        "-pedantic",
+        "-Wno-cast-qual",  # typically from TCL swigging
+        "-Wno-missing-braces",  # typically from TCL swigging
+        "-Wredundant-decls",
+        "-Wformat-security",
+        "-Wno-unused-parameter",
+        "-Wno-sign-compare",
+        "-fopenmp",
+    ],
+    features = [
+        "-use_header_modules",
+    ],
+    includes = [
+        ".",
+        "dcalc",
+        "include",
+        "include/sta",
+        "liberty",
+        "parasitics",
+        "power",
+        "sdf",
+        "util",
+        "verilog",
+    ],
+    visibility = ["//:__subpackages__"],
+    deps = [
+        ":config",
+        "@cudd",
+        "@eigen",  # keep. Is used, but with <>-includes
+        "@openmp",  # keep. Is needed ? Nobody includes omp.h
+        "@rules_flex//flex:current_flex_toolchain",
+        "@tcl_lang//:tcl",  # keep. Is used, but with <>-includes
+        "@zlib",  # keep. Is used, but with <>-includes
+    ],
+)
+
+filegroup(
+    name = "tcl_util",
+    srcs = [
+        "tcl/Util.tcl",
+    ],
+    visibility = ["//visibility:public"],
+)

The-OpenROAD-Project_OpenSTA/Brewfile

@@ -0,0 +1,10 @@
+brew "bison"
+brew "cmake"
+brew "eigen"
+brew "flex"
+brew "googletest"
+brew "swig"
+brew "tcl-tk@8"
+
+tap "mht208/formal"
+brew "mht208/formal/cudd", trusted: true

The-OpenROAD-Project_OpenSTA/CMakeLists.txt

@@ -0,0 +1,731 @@
+# OpenSTA, Static Timing Analyzer
+# Copyright (c) 2026, Parallax Software, Inc.
+# 
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+# 
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+# 
+# You should have received a copy of the GNU General Public License
+# along with this program. If not, see <https://www.gnu.org/licenses/>.
+# 
+# The origin of this software must not be misrepresented; you must not
+# claim that you wrote the original software.
+# 
+# Altered source versions must be plainly marked as such, and must not be
+# misrepresented as being the original software.
+# 
+# This notice may not be removed or altered from any source distribution.
+
+cmake_minimum_required (VERSION 3.16)
+
+project(STA VERSION 3.1.0
+  LANGUAGES CXX
+)
+
+option(CUDD_DIR "CUDD BDD package directory")
+option(USE_TCL_READLINE "Use TCL readline package" ON)
+option(ENABLE_TSAN "Compile with thread santizer enabled" OFF)
+option(ENABLE_ASAN "Compile with address santizer enabled" OFF)
+
+# Turn on to debug compiler args.
+set(CMAKE_VERBOSE_MAKEFILE OFF)
+
+# Write compile_commands.json to the build directory for clang-tidy.
+set(CMAKE_EXPORT_COMPILE_COMMANDS ON)
+
+set(STA_HOME ${PROJECT_SOURCE_DIR})
+message(STATUS "STA version: ${PROJECT_VERSION}")
+
+list(APPEND CMAKE_MODULE_PATH "${CMAKE_CURRENT_SOURCE_DIR}/cmake")
+include(GetGitRevisionDescription)
+get_git_head_revision(GIT_REFSPEC STA_GIT_SHA1)
+message(STATUS "STA git sha: ${STA_GIT_SHA1}")
+
+# Default to bulding optimnized/release executable.
+if(NOT CMAKE_BUILD_TYPE)
+  set(CMAKE_BUILD_TYPE RELEASE)
+endif()
+
+message(STATUS "System name: ${CMAKE_SYSTEM_NAME}")
+message(STATUS "Compiler: ${CMAKE_CXX_COMPILER_ID} ${CMAKE_CXX_COMPILER_VERSION}")
+message(STATUS "Build type: ${CMAKE_BUILD_TYPE}")
+message(STATUS "Build CXX_FLAGS: ${CMAKE_CXX_FLAGS_${CMAKE_BUILD_TYPE}}")
+message(STATUS "Install prefix: ${CMAKE_INSTALL_PREFIX}")
+
+# Enable Link-Time Optimization (LTO) for Release builds.
+include(CheckIPOSupported)
+check_ipo_supported(RESULT ipo_supported OUTPUT ipo_error)
+if(ipo_supported)
+  set(CMAKE_INTERPROCEDURAL_OPTIMIZATION_RELEASE TRUE)
+  message(STATUS "IPO/LTO: enabled for Release builds")
+else()
+  message(STATUS "IPO/LTO: not supported - ${ipo_error}")
+endif()
+
+################################################################
+#
+# Source files.
+#
+################################################################
+
+set(STA_SOURCE
+  app/StaMain.cc
+  
+  dcalc/ArcDcalcWaveforms.cc
+  dcalc/ArcDelayCalc.cc
+  dcalc/ArnoldiDelayCalc.cc
+  dcalc/ArnoldiReduce.cc
+  dcalc/CcsCeffDelayCalc.cc
+  dcalc/Delay.cc
+  dcalc/DelayCalc.cc
+  dcalc/DelayCalcBase.cc
+  dcalc/DelayNormal.cc
+  dcalc/DelayScalar.cc
+  dcalc/DelaySkewNormal.cc
+  dcalc/DmpCeff.cc
+  dcalc/DmpDelayCalc.cc
+  dcalc/FindRoot.cc
+  dcalc/GraphDelayCalc.cc
+  dcalc/LumpedCapDelayCalc.cc
+  dcalc/NetCaps.cc
+  dcalc/ParallelDelayCalc.cc
+  dcalc/PrimaDelayCalc.cc
+  dcalc/UnitDelayCalc.cc
+  
+  graph/Graph.cc
+  graph/GraphCmp.cc
+  
+  liberty/EquivCells.cc
+  liberty/FuncExpr.cc
+  liberty/InternalPower.cc
+  liberty/LeakagePower.cc
+  liberty/Liberty.cc
+  liberty/LibertyBuilder.cc
+  liberty/LibExprReader.cc
+  liberty/LibertyParser.cc
+  liberty/LibertyReader.cc
+  liberty/LibertyWriter.cc
+  liberty/LinearModel.cc
+  liberty/Sequential.cc
+  liberty/TableModel.cc
+  liberty/TimingArc.cc
+  liberty/TimingModel.cc
+  liberty/TimingRole.cc
+  liberty/Units.cc
+  liberty/Wireload.cc
+  
+  network/ConcreteLibrary.cc
+  network/ConcreteNetwork.cc
+  network/HpinDrvrLoad.cc
+  network/Network.cc
+  network/NetworkCmp.cc
+  network/ParseBus.cc
+  network/PortDirection.cc
+  network/SdcNetwork.cc
+  network/VerilogNamespace.cc
+  
+  parasitics/ConcreteParasitics.cc
+  parasitics/EstimateParasitics.cc
+  parasitics/Parasitics.cc
+  parasitics/ReduceParasitics.cc
+  parasitics/ReportParasiticAnnotation.cc
+  parasitics/SpefNamespace.cc
+  parasitics/SpefReader.cc
+  parasitics/SpefReaderPvt.hh
+
+  power/Power.cc
+  power/ReportPower.cc
+  power/VcdReader.cc
+  power/SaifReader.cc
+  power/VcdParse.cc
+  
+  sdc/Clock.cc
+  sdc/ClockGatingCheck.cc
+  sdc/ClockGroups.cc
+  sdc/ClockInsertion.cc
+  sdc/ClockLatency.cc
+  sdc/CycleAccting.cc
+  sdc/DataCheck.cc
+  sdc/DeratingFactors.cc
+  sdc/DisabledPorts.cc
+  sdc/ExceptionPath.cc
+  sdc/FilterObjects.cc
+  sdc/InputDrive.cc
+  sdc/PinPair.cc
+  sdc/PortDelay.cc
+  sdc/PortExtCap.cc
+  sdc/Sdc.cc
+  sdc/SdcCmdComment.cc
+  sdc/Variables.cc
+  sdc/WriteSdc.cc
+  
+  sdf/ReportAnnotation.cc
+  sdf/SdfReader.cc
+  sdf/SdfWriter.cc
+  
+  search/Bdd.cc
+  search/Bfs.cc
+  search/CheckMaxSkews.cc
+  search/CheckMinPeriods.cc
+  search/CheckMinPulseWidths.cc
+  search/CheckCapacitances.cc
+  search/CheckFanouts.cc
+  search/CheckSlews.cc
+  search/CheckTiming.cc
+  search/ClkInfo.cc
+  search/ClkLatency.cc
+  search/ClkNetwork.cc
+  search/ClkSkew.cc
+  search/Crpr.cc
+  search/FindRegister.cc
+  search/GatedClk.cc
+  search/Genclks.cc
+  search/Latches.cc
+  search/Levelize.cc
+  search/MakeTimingModel.cc
+  search/Mode.cc
+  search/Path.cc
+  search/Path.cc
+  search/PathEnd.cc
+  search/PathEnum.cc
+  search/PathExpanded.cc
+  search/PathGroup.cc
+  search/PocvMode.cc
+  search/Property.cc
+  search/ReportPath.cc
+  search/Search.cc
+  search/SearchPred.cc
+  search/Scene.cc
+  search/Sim.cc
+  search/Sta.cc
+  search/StaState.cc
+  search/Tag.cc
+  search/TagGroup.cc
+  search/VertexVisitor.cc
+  search/VisitPathEnds.cc
+  search/WorstSlack.cc
+
+  spice/WritePathSpice.cc
+  spice/WriteSpice.cc
+  spice/Xyce.cc
+
+  tcl/TclTypeHelpers.cc
+
+  util/Debug.cc
+  util/DispatchQueue.cc
+  util/Error.cc
+  util/Fuzzy.cc
+  util/Hash.cc
+  util/MinMax.cc
+  util/PatternMatch.cc
+  util/Report.cc
+  util/ReportStd.cc
+  util/ReportTcl.cc
+  util/RiseFallMinMax.cc
+  util/RiseFallMinMaxDelay.cc
+  util/RiseFallValues.cc
+  util/Stats.cc
+  util/StringUtil.cc
+  util/Transition.cc
+  
+  verilog/VerilogReader.cc
+  verilog/VerilogWriter.cc
+  )
+
+if(APPLE)
+  list(APPEND STA_SOURCE util/MachineApple.cc)
+elseif(CMAKE_SYSTEM_NAME STREQUAL "Linux")
+  list(APPEND STA_SOURCE util/MachineLinux.cc)
+elseif(WIN32)
+  list(APPEND STA_SOURCE util/MachineWin32.cc)
+else()
+  list(APPEND STA_SOURCE util/MachineUnknown.cc)
+endif()
+
+# Source files.
+set(STA_TCL_FILES
+  tcl/Init.tcl
+  tcl/Util.tcl
+  tcl/CmdArgs.tcl
+  tcl/CmdUtil.tcl
+  tcl/Property.tcl
+  tcl/Sta.tcl
+  tcl/Splash.tcl
+  dcalc/DelayCalc.tcl
+  graph/Graph.tcl
+  liberty/Liberty.tcl
+  network/Link.tcl
+  network/Network.tcl
+  network/NetworkEdit.tcl
+  parasitics/Parasitics.tcl
+  power/Power.tcl
+  sdc/Sdc.tcl
+  sdc/Variables.tcl
+  sdf/Sdf.tcl
+  search/Search.tcl
+  spice/WriteSpice.tcl
+  verilog/Verilog.tcl
+  )
+
+################################################################
+#
+# Flex/bison scanner/parsers
+#
+################################################################
+
+# Earlier versions of flex use 'register' declarations that are illegal in c++17.
+#find_package(FLEX 2.6.4)
+find_package(FLEX)
+find_package(BISON REQUIRED 3.2)
+
+# Verilog scan/parse.
+flex_target(VerilogLex ${STA_HOME}/verilog/VerilogLex.ll
+  ${CMAKE_CURRENT_BINARY_DIR}/VerilogLex.cc)
+bison_target(VerilogParse ${STA_HOME}/verilog/VerilogParse.yy
+  ${CMAKE_CURRENT_BINARY_DIR}/VerilogParse.cc)
+add_flex_bison_dependency(VerilogLex VerilogParse)
+
+# Liberty scan/parse.
+flex_target(LibertyLex ${STA_HOME}/liberty/LibertyLex.ll
+  ${CMAKE_CURRENT_BINARY_DIR}/LibertyLex.cc)
+bison_target(LibertyParse ${STA_HOME}/liberty/LibertyParse.yy
+  ${CMAKE_CURRENT_BINARY_DIR}/LibertyParse.cc)
+add_flex_bison_dependency(LibertyLex LibertyParse)
+
+# Liberty Expr scan/parse.
+flex_target(LibExprLex ${STA_HOME}/liberty/LibExprLex.ll
+  ${CMAKE_CURRENT_BINARY_DIR}/LibExprLex.cc)
+bison_target(LibExprParse ${STA_HOME}/liberty/LibExprParse.yy
+  ${CMAKE_CURRENT_BINARY_DIR}/LibExprParse.cc)
+add_flex_bison_dependency(LibExprLex LibExprParse)
+
+# Sdf scan/parse.
+flex_target(SdfLex ${STA_HOME}/sdf/SdfLex.ll
+  ${CMAKE_CURRENT_BINARY_DIR}/SdfLex.cc)
+bison_target(SdfParse ${STA_HOME}/sdf/SdfParse.yy
+  ${CMAKE_CURRENT_BINARY_DIR}/SdfParse.cc)
+add_flex_bison_dependency(SdfLex SdfParse)
+
+# Spef scan/parse.
+flex_target(SpefLex ${STA_HOME}/parasitics/SpefLex.ll
+  ${CMAKE_CURRENT_BINARY_DIR}/SpefLex.cc)
+bison_target(SpefParse ${STA_HOME}/parasitics/SpefParse.yy
+  ${CMAKE_CURRENT_BINARY_DIR}/SpefParse.cc)
+add_flex_bison_dependency(SpefLex SpefParse)
+
+# Saif scan/parse.
+flex_target(SaifLex ${STA_HOME}/power/SaifLex.ll
+  ${CMAKE_CURRENT_BINARY_DIR}/SaifLex.cc)
+bison_target(SaifParse ${STA_HOME}/power/SaifParse.yy
+  ${CMAKE_CURRENT_BINARY_DIR}/SaifParse.cc)
+add_flex_bison_dependency(SaifLex SaifParse)
+
+# Suppress -Wsign-compare in flex-generated code (yyleng vs int loop counter).
+# Only needed with older GCC (e.g. CentOS 7 stock 4.8.5); newer GCC/flex handle it.
+if(CMAKE_CXX_COMPILER_ID STREQUAL "GNU")
+  set_source_files_properties(
+    ${FLEX_VerilogLex_OUTPUTS}
+    ${FLEX_LibertyLex_OUTPUTS}
+    ${FLEX_LibExprLex_OUTPUTS}
+    ${FLEX_SdfLex_OUTPUTS}
+    ${FLEX_SpefLex_OUTPUTS}
+    ${FLEX_SaifLex_OUTPUTS}
+    PROPERTIES COMPILE_FLAGS "-Wno-sign-compare"
+  )
+endif()
+
+################################################################
+
+set(STA_TCL_INIT ${CMAKE_CURRENT_BINARY_DIR}/StaTclInitVar.cc)
+
+# TCL files included as part of the executable are shoved into StaTclInitVar.cc.
+# These files are encoded and shipped as part of the executable 
+# so that they do not have to be installed on the client host.
+add_custom_command(OUTPUT ${STA_TCL_INIT}
+  COMMAND etc/TclEncode.tcl ${STA_TCL_INIT} tcl_inits ${STA_TCL_FILES}
+  WORKING_DIRECTORY ${STA_HOME}
+  DEPENDS ${STA_TCL_FILES} etc/TclEncode.tcl
+  )
+
+################################################################
+#
+# Library dependencies
+#
+################################################################
+
+# OSX tcl is deprecated and prints a warning, so look for a user installed
+# version before using the system version.
+# I tried to override the library search order instead but failed.
+# CMAKE_FIND_FRAMEWORK LAST bypasses the version in the framework directory
+# but not the one in /usr/lib.
+# This calls cmake/FindTCL.cmake
+# Do not use REQUIRED because it also requires TK, which is not used by OpenSTA.
+find_package(TCL)
+
+# Referenced by util/StaConfig.hh.cmake
+set(TCL_READLINE 0)
+# check for tclReadline
+if (USE_TCL_READLINE)
+  set(TCL_READLINE_POSSIBLE_NAMES
+    tclreadline-2.1.0
+    tclreadline-2.3.2
+    tclreadline-2.3.6
+    tclreadline-2.3.7
+    tclreadline-2.3.8
+    )
+  find_library(TCL_READLINE_LIBRARY
+    NAMES tclreadline ${TCL_READLINE_POSSIBLE_NAMES}
+    PATHS ${TCL_LIB_PATHS}
+    )
+  if (TCL_READLINE_LIBRARY)
+    message(STATUS "TCL readline library: ${TCL_READLINE_LIBRARY}")
+  else()
+    message(STATUS "TCL readline library: NOT FOUND")
+  endif()
+
+  find_path(TCL_READLINE_INCLUDE tclreadline.h)
+  if (TCL_READLINE_INCLUDE)
+    message(STATUS "TCL readline header: ${TCL_READLINE_INCLUDE}/tclreadline.h")
+  else()
+    message(STATUS "TCL readline header: NOT FOUND")
+  endif()
+
+  if (TCL_READLINE_LIBRARY AND TCL_READLINE_INCLUDE)
+    set(TCL_READLINE 1)
+  endif()
+endif()
+
+# Zlib
+include(FindZLIB)
+
+find_package(Threads)
+
+find_package(Eigen3 REQUIRED)
+
+# See if std::format is available and if nor install fmt.
+include(CheckCXXSourceCompiles)
+set(_sta_fmt_check_saved_flags "${CMAKE_REQUIRED_FLAGS}")
+if(MSVC)
+  string(APPEND CMAKE_REQUIRED_FLAGS " /std:c++20")
+else()
+  string(APPEND CMAKE_REQUIRED_FLAGS " -std=c++20")
+endif()
+check_cxx_source_compiles("
+#include <format>
+#include <string>
+int main() { (void)std::format(\"{}\", 42); return 0; }
+" HAVE_CXX_STD_FORMAT)
+set(CMAKE_REQUIRED_FLAGS "${_sta_fmt_check_saved_flags}")
+
+if(HAVE_CXX_STD_FORMAT)
+  message(STATUS "std::format: available")
+else()
+  # Use spdlog's bundled fmt when available to avoid ODR violations.
+  find_package(spdlog QUIET)
+  if(spdlog_FOUND)
+    message(STATUS "std::format: using spdlog's bundled fmt")
+    set(STA_USE_SPDLOG_FMT TRUE)
+    get_target_property(_spdlog_inc spdlog::spdlog INTERFACE_INCLUDE_DIRECTORIES)
+    set(_fmt_dir "${CMAKE_CURRENT_BINARY_DIR}/_spdlog_fmt")
+    file(MAKE_DIRECTORY "${_fmt_dir}")
+    file(CREATE_LINK "${_spdlog_inc}/spdlog/fmt/bundled" "${_fmt_dir}/fmt" SYMBOLIC)
+  else()
+    message(STATUS "std::format: building fmt library")
+    include(FetchContent)
+    FetchContent_Declare(fmt
+      GIT_REPOSITORY https://github.com/fmtlib/fmt.git
+      GIT_TAG 11.0.2
+    )
+    FetchContent_MakeAvailable(fmt)
+  endif()
+endif()
+
+include(cmake/FindCUDD.cmake)
+
+# configure a header file to pass some of the CMake settings
+configure_file(${STA_HOME}/util/StaConfig.hh.cmake
+  ${CMAKE_CURRENT_BINARY_DIR}/include/sta/StaConfig.hh
+  )
+
+###########################################################
+# Swig
+###########################################################
+
+find_package(SWIG 3.0 REQUIRED)
+message(STATUS "SWIG version: ${SWIG_VERSION}")
+include(UseSWIG)
+
+set(STA_SWIG_FILE app/StaApp.i)
+
+set_property(SOURCE ${STA_SWIG_FILE}
+  PROPERTY CPLUSPLUS ON
+)
+# SWIG flags (CMake UseSWIG).
+set_property(SOURCE ${STA_SWIG_FILE}
+  PROPERTY COMPILE_OPTIONS
+  -module sta
+  -namespace
+  -prefix sta
+)
+
+set(SWIG_FILES
+  ${STA_HOME}/dcalc/DelayCalc.i
+  ${STA_HOME}/graph/Graph.i
+  ${STA_HOME}/liberty/Liberty.i
+  ${STA_HOME}/network/Network.i
+  ${STA_HOME}/network/NetworkEdit.i
+  ${STA_HOME}/parasitics/Parasitics.i
+  ${STA_HOME}/power/Power.i
+  ${STA_HOME}/sdc/Sdc.i
+  ${STA_HOME}/sdf/Sdf.i
+  ${STA_HOME}/search/Property.i
+  ${STA_HOME}/search/Search.i
+  ${STA_HOME}/spice/WriteSpice.i
+  ${STA_HOME}/tcl/Exception.i
+  ${STA_HOME}/tcl/StaTclTypes.i
+  ${STA_HOME}/util/Util.i
+  ${STA_HOME}/verilog/Verilog.i
+  )
+
+set_property(SOURCE ${STA_SWIG_FILE}
+  PROPERTY DEPENDS ${SWIG_FILES}
+)
+
+swig_add_library(sta_swig
+  LANGUAGE tcl
+  TYPE STATIC
+  SOURCES ${STA_SWIG_FILE}
+)
+
+get_target_property(STA_SWIG_CXX_FILE sta_swig SOURCES)
+
+set_source_files_properties(${STA_SWIG_CXX_FILE}
+  PROPERTIES
+  # No simple way to modify the swig template that emits code full of warnings
+  # so suppress them.
+  COMPILE_OPTIONS "-Wunused-variable;-Wno-cast-qual;-Wno-missing-braces;-Wno-deprecated-declarations"
+  )
+
+target_link_libraries(sta_swig
+  PUBLIC
+  OpenSTA
+)
+
+# result build/CMakeFiles/sta_swig.dir/StaAppTCL_wrap.cxx
+target_include_directories(sta_swig
+  PUBLIC
+  include/sta
+
+  PRIVATE
+  ${STA_HOME}
+  ${TCL_INCLUDE_PATH}
+  ${CMAKE_CURRENT_BINARY_DIR}/include/sta
+)
+
+# Pass sta_swig include directories to SWIG as -I (same paths as the C++ build).
+set_property(TARGET sta_swig PROPERTY SWIG_USE_TARGET_INCLUDE_DIRECTORIES TRUE)
+
+###########################################################
+# Library
+###########################################################
+
+add_library(OpenSTA)
+
+target_sources(OpenSTA
+  PRIVATE
+  ${STA_SOURCE}
+
+  ${STA_TCL_INIT}
+
+  ${FLEX_LibExprLex_OUTPUTS}
+  ${BISON_LibExprParse_OUTPUTS}
+  ${FLEX_LibertyLex_OUTPUTS}
+  ${BISON_LibertyParse_OUTPUTS}
+
+  ${FLEX_SpefLex_OUTPUTS}
+  ${BISON_SpefParse_OUTPUTS}
+
+  ${FLEX_SdfLex_OUTPUTS}
+  ${BISON_SdfParse_OUTPUTS}
+
+  ${FLEX_VerilogLex_OUTPUTS}
+  ${BISON_VerilogParse_OUTPUTS}
+
+  ${FLEX_SaifLex_OUTPUTS}
+  ${BISON_SaifParse_OUTPUTS}
+)
+
+target_link_libraries(OpenSTA
+  Eigen3::Eigen
+  ${TCL_LIBRARY}
+  ${CMAKE_THREAD_LIBS_INIT}
+  ${CUDD_LIB}
+  )
+
+if(NOT HAVE_CXX_STD_FORMAT)
+  if(STA_USE_SPDLOG_FMT)
+    target_include_directories(OpenSTA PUBLIC "${_fmt_dir}")
+    target_link_libraries(OpenSTA spdlog::spdlog)
+  else()
+    target_link_libraries(OpenSTA fmt::fmt)
+  endif()
+endif()
+
+if (ZLIB_LIBRARIES)
+  target_link_libraries(OpenSTA ${ZLIB_LIBRARIES})
+endif()
+
+target_include_directories(OpenSTA
+  PUBLIC
+  include
+  ${TCL_INCLUDE_PATH}
+  ${FLEX_INCLUDE_DIRS}
+  ${CMAKE_CURRENT_BINARY_DIR}/include/sta
+
+  PRIVATE
+  include/sta
+  ${STA_HOME}
+  ${CUDD_INCLUDE}
+  # For flex to find location.hh
+  ${CMAKE_CURRENT_BINARY_DIR}
+  )
+
+if (TCL_READLINE)
+  target_link_libraries(OpenSTA ${TCL_READLINE_LIBRARY})
+  target_include_directories(OpenSTA
+    PUBLIC
+    ${TCL_READLINE_INCLUDE})
+endif()
+
+# common to gcc/clang
+set(CXX_FLAGS -Wall -Wextra -pedantic -Wcast-qual -Wredundant-decls
+  -Wformat-security -Werror=misleading-indentation -Wundef)
+
+if(ENABLE_TSAN)
+  message(STATUS "Thread sanitizer: ${ENABLE_TSAN}")
+  set(CXX_FLAGS "${CXX_FLAGS};-fsanitize=thread")
+  string(APPEND CMAKE_EXE_LINKER_FLAGS " -fsanitize=thread")
+endif()
+
+if(ENABLE_ASAN)
+  message(STATUS "Address sanitizer: ${ENABLE_ASAN}")
+  set(CXX_FLAGS "${CXX_FLAGS};-fsanitize=address")
+  string(APPEND CMAKE_EXE_LINKER_FLAGS " -fsanitize=address")
+endif()
+
+target_compile_options(OpenSTA
+  PRIVATE
+  $<$<CXX_COMPILER_ID:GNU>:${CXX_FLAGS} -Wno-format-zero-length>
+  $<$<CXX_COMPILER_ID:Clang>:${CXX_FLAGS} -Wno-gnu-zero-variadic-macro-arguments>
+  $<$<CXX_COMPILER_ID:AppleClang>:${CXX_FLAGS} -Wno-gnu-zero-variadic-macro-arguments>
+  )
+
+# Disable compiler specific extensions like gnu++11.
+set_target_properties(OpenSTA PROPERTIES CXX_EXTENSIONS OFF)
+target_compile_features(OpenSTA PUBLIC cxx_std_20)
+
+message(STATUS "STA library: ${CMAKE_BINARY_DIR}/libOpenSTA.a")
+
+###########################################################
+# Executable
+###########################################################
+
+# Note executable and lib name cannot be the same because
+# on osx something is case insensitive. Using STA for the
+# lib name results in "No rule to make target ../depend.
+add_executable(sta app/Main.cc)
+
+target_link_libraries(sta
+  PRIVATE
+  sta_swig
+  OpenSTA
+  )
+
+message(STATUS "STA executable: ${CMAKE_BINARY_DIR}/sta")
+
+################################################################
+# Install
+# cmake .. -DCMAKE_INSTALL_PREFIX=<prefix_path>
+
+# executable
+install(TARGETS sta DESTINATION bin)
+
+# library
+install(TARGETS OpenSTA DESTINATION lib)
+
+# include
+install(DIRECTORY include/sta  DESTINATION include)
+install(DIRECTORY ${CMAKE_CURRENT_BINARY_DIR}/include/sta  DESTINATION include)
+
+################################################################
+
+add_custom_target(sta_tags
+  COMMAND etags -o TAGS
+  ${STA_SOURCE}
+  */*.hh
+  include/sta/*.hh
+  ${CMAKE_CURRENT_BINARY_DIR}/include/sta/*.hh
+  ${SWIG_FILES}
+  ${SWIG_FILES}
+
+  # Append tcl tags.
+  # Note that the regexp used for tcl files is broken in etags so provide one that works.
+  COMMAND etags -a -o TAGS --language=none
+  --regex='/^[ \\t]*proc[ \\t]+[a-zA-Z0-9_]+/'
+  ${STA_TCL_FILES}
+  WORKING_DIRECTORY ${STA_HOME}
+)
+
+add_custom_command(
+  TARGET OpenSTA
+  POST_BUILD
+  COMMAND ${STA_HOME}/etc/FindMessages.tcl > ${STA_HOME}/doc/messages.txt || true
+  WORKING_DIRECTORY ${STA_HOME}
+)
+
+################################################################
+# Tests
+################################################################
+
+option(BUILD_TESTS "Build unit tests" ON)
+if(BUILD_TESTS)
+  enable_testing()
+  find_package(GTest REQUIRED)
+  include(GoogleTest)
+
+  # Helper: register a list of Tcl tests for a module.
+  # Usage:
+  #   sta_module_tests("search" TESTS timing analysis ...)
+  function(sta_module_tests module_name)
+    cmake_parse_arguments(ARG "" "" "TESTS" ${ARGN})
+    foreach(test_name ${ARG_TESTS})
+      add_test(
+        NAME tcl.${module_name}.${test_name}
+        COMMAND bash ${STA_HOME}/test/regression.sh $<TARGET_FILE:sta> ${module_name}_${test_name}
+        WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}
+      )
+      set_tests_properties(tcl.${module_name}.${test_name} PROPERTIES LABELS "tcl;module_${module_name}")
+    endforeach()
+  endfunction()
+
+  add_subdirectory(test)
+  # Per-module tests
+  add_subdirectory(util/test)
+  add_subdirectory(liberty/test)
+  add_subdirectory(graph/test)
+  add_subdirectory(network/test)
+  add_subdirectory(sdc/test)
+  add_subdirectory(sdf/test)
+  add_subdirectory(dcalc/test)
+  add_subdirectory(search/test)
+  add_subdirectory(parasitics/test)
+  add_subdirectory(power/test)
+  add_subdirectory(verilog/test)
+  add_subdirectory(spice/test)
+endif()

The-OpenROAD-Project_OpenSTA/Dockerfile.ubuntu22.04

@@ -0,0 +1,47 @@
+FROM ubuntu:22.04
+LABEL author="James Cherry"
+LABEL maintainer="James Cherry <cherry@parallaxsw.com>"
+
+# Install basics
+ARG DEBIAN_FRONTEND=noninteractive
+RUN apt-get update && \
+    apt-get install -y \
+    git \
+    wget \
+    cmake \
+    gcc \
+    gdb \
+    tcl-dev \
+    tcl-tclreadline \
+    swig \
+    bison \
+    flex \
+    automake \
+    autotools-dev \
+    libgtest-dev \
+    libeigen3-dev \
+    libfmt-dev
+
+# Download CUDD
+RUN wget https://raw.githubusercontent.com/davidkebo/cudd/main/cudd_versions/cudd-3.0.0.tar.gz && \
+    tar -xvf cudd-3.0.0.tar.gz && \
+    rm cudd-3.0.0.tar.gz
+
+# Build CUDD
+RUN cd cudd-3.0.0 && \
+    mkdir ../cudd && \
+    ./configure && \
+    make -j`nproc`
+
+# Copy files and install OpenSTA
+RUN mkdir OpenSTA
+COPY . OpenSTA
+RUN cd OpenSTA && \
+    rm -rf build && \
+    mkdir build && \
+    cd build && \
+    cmake -DCUDD_DIR=../cudd-3.0.0 .. && \
+    make -j`nproc`
+
+# Run sta on entry
+ENTRYPOINT ["OpenSTA/build/sta"]

The-OpenROAD-Project_OpenSTA/Dockerfile.ubuntu24.04

@@ -0,0 +1,46 @@
+FROM ubuntu:24.04
+LABEL author="James Cherry"
+LABEL maintainer="James Cherry <cherry@parallaxsw.com>"
+
+# Install basics
+ARG DEBIAN_FRONTEND=noninteractive
+RUN apt-get update && \
+    apt-get install -y \
+    git \
+    wget \
+    cmake \
+    gcc \
+    gdb \
+    tcl-dev \
+    tcl-tclreadline \
+    swig \
+    bison \
+    flex \
+    automake \
+    autotools-dev \
+    libeigen3-dev \
+    libfmt-dev
+
+# Download CUDD
+RUN wget https://raw.githubusercontent.com/davidkebo/cudd/main/cudd_versions/cudd-3.0.0.tar.gz && \
+    tar -xvf cudd-3.0.0.tar.gz && \
+    rm cudd-3.0.0.tar.gz
+
+# Build CUDD
+RUN cd cudd-3.0.0 && \
+    mkdir ../cudd && \
+    ./configure && \
+    make -j`nproc`
+
+# Copy files and install OpenSTA
+RUN mkdir OpenSTA
+COPY . OpenSTA
+RUN cd OpenSTA && \
+    rm -rf build && \
+    mkdir build && \
+    cd build && \
+    cmake -DCUDD_DIR=../cudd-3.0.0 .. && \
+    make -j`nproc`
+
+# Run sta on entry
+ENTRYPOINT ["OpenSTA/build/sta"]

The-OpenROAD-Project_OpenSTA/Jenkinsfile

@@ -0,0 +1,5 @@
+@Library('utils@main') _
+
+k8sPodTemplate(coordinator: true, cloud: utilPickCloud()) {
+    pipelineOpenSTA(k8s: true)
+}

The-OpenROAD-Project_OpenSTA/LICENSE

@@ -0,0 +1,674 @@
+                    GNU GENERAL PUBLIC LICENSE
+                       Version 3, 29 June 2007
+
+ Copyright (C) 2007 Free Software Foundation, Inc. <https://fsf.org/>
+ Everyone is permitted to copy and distribute verbatim copies
+ of this license document, but changing it is not allowed.
+
+                            Preamble
+
+  The GNU General Public License is a free, copyleft license for
+software and other kinds of works.
+
+  The licenses for most software and other practical works are designed
+to take away your freedom to share and change the works.  By contrast,
+the GNU General Public License is intended to guarantee your freedom to
+share and change all versions of a program--to make sure it remains free
+software for all its users.  We, the Free Software Foundation, use the
+GNU General Public License for most of our software; it applies also to
+any other work released this way by its authors.  You can apply it to
+your programs, too.
+
+  When we speak of free software, we are referring to freedom, not
+price.  Our General Public Licenses are designed to make sure that you
+have the freedom to distribute copies of free software (and charge for
+them if you wish), that you receive source code or can get it if you
+want it, that you can change the software or use pieces of it in new
+free programs, and that you know you can do these things.
+
+  To protect your rights, we need to prevent others from denying you
+these rights or asking you to surrender the rights.  Therefore, you have
+certain responsibilities if you distribute copies of the software, or if
+you modify it: responsibilities to respect the freedom of others.
+
+  For example, if you distribute copies of such a program, whether
+gratis or for a fee, you must pass on to the recipients the same
+freedoms that you received.  You must make sure that they, too, receive
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+
+  Developers that use the GNU GPL protect your rights with two steps:
+(1) assert copyright on the software, and (2) offer you this License
+giving you legal permission to copy, distribute and/or modify it.
+
+  For the developers' and authors' protection, the GPL clearly explains
+that there is no warranty for this free software.  For both users' and
+authors' sake, the GPL requires that modified versions be marked as
+changed, so that their problems will not be attributed erroneously to
+authors of previous versions.
+
+  Some devices are designed to deny users access to install or run
+modified versions of the software inside them, although the manufacturer
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+pattern of such abuse occurs in the area of products for individuals to
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+
+  Finally, every program is threatened constantly by software patents.
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The-OpenROAD-Project_OpenSTA/README.md

@@ -0,0 +1,317 @@
+# Parallax Static Timing Analyzer
+
+OpenSTA is a gate level static timing verifier. As a stand-alone
+executable it can be used to verify the timing of a design using
+standard file formats.
+
+* Verilog netlist
+* Liberty library
+* SDC timing constraints
+* SDF delay annotation
+* SPEF parasitics
+* VCD power acitivies
+* SAIF power acitivies
+
+OpenSTA uses a TCL command interpreter to read the design, specify
+timing constraints and print timing reports.
+
+##### Clocks
+* Generated
+* Latency
+* Source latency (insertion delay)
+* Uncertainty
+* Propagated/Ideal
+* Gated clock checks
+* Multiple frequency clocks
+
+##### Exception paths
+* False path
+* Multicycle path
+* Min/Max path delay
+* Exception points
+*  -from clock/pin/instance -through pin/net -to clock/pin/instance
+*  Edge specific exception points
+*   -rise_from/-fall_from, -rise_through/-fall_through, -rise_to/-fall_to
+
+##### Delay calculation
+* Integrated Dartu/Menezes/Pileggi RC effective capacitance algorithm
+* External delay calculator API
+
+##### Analysis
+* Report timing checks -from, -through, -to, multiple paths to endpoint
+* Report delay calculation
+* Check timing setup
+
+##### Timing Engine
+OpenSTA is architected to be easily bolted on to other tools as a
+timing engine.  By using a network adapter, OpenSTA can access the host
+netlist data structures without duplicating them.
+
+* Query based incremental update of delays, arrival and required times
+* Simulator to propagate constants from constraints and netlist tie high/low
+
+See doc/OpenSTA.pdf for command documentation.
+See doc/ChangeLog.txt for changes to commands.
+See doc/StaApi.txt for timing engine API documentation.
+
+OpenSTA is dual licensed. It is released under GPL v3 as OpenSTA and
+is also licensed for commerical applications by Parallax Software without
+the GPL's requirements.
+
+OpenSTA is open source, meaning the sources are published and can be
+compiled locally.  Derivative works are supported as long as they
+adhere to the GPL license requirements.  However, OpenSTA is not
+supported by a public community of developers as many other open
+source projects are. The copyright and development are exclusive to
+Parallax Software.
+
+Removing copyright and license notices from OpenSTA sources (or any
+other open source project for that matter) is illegal. This should be
+obvious, but the author of OpenSTA has discovered two different cases
+where the copyright and license were removed from source files that
+were copied.
+
+The official git repository is located at
+https://github.com/parallaxsw/OpenSTA.git. Any forks from this code
+base have not passed extensive regression testing which is not
+publicly available.
+
+## Build from source
+
+OpenSTA is built with CMake.
+
+### Prerequisites
+
+The build dependency versions are shown below.  Other versions may
+work, but these are the versions used for development.
+
+```
+         Ubuntu   Macos
+        22.04.2   14.5
+cmake    3.24.2    3.29.2
+clang             15.0.0
+gcc      11.4.0
+tcl       8.6      8.6.16
+swig      4.1.0    4.1.1
+bison     3.8.2    3.8.2
+flex      2.6.4    2.6.4
+```
+
+External library dependencies:
+```
+           Ubuntu   Darwin  License
+eigen       3.4.0   3.4.0   MPL2  required
+cudd        3.0.0   3.0.0   BSD   required
+tclreadline 2.3.8   2.3.8   BSD   optional
+zLib        1.2.5   1.2.8   zlib  optional
+libfmt      8.1.1   N/A     MIT   required if std::format not available
+```
+
+The [TCL readline library](https://tclreadline.sourceforge.net/tclreadline.html)
+links the GNU readline library to the TCL interpreter for command line
+editing To enable TCL readline support use the following Cmake option:
+See (https://tclreadline.sourceforge.net/) for TCL readline
+documentation. To change the overly verbose default prompt, add
+something this to your ~/.sta init file:
+
+```
+if { ![catch {package require tclreadline}] } {
+  proc tclreadline::prompt1 {} {
+    return "> "
+  }
+}
+```
+
+The Zlib library is an optional.  If CMake finds libz, OpenSTA can
+read Liberty, Verilog, SDF, SPF, and SPEF files compressed with gzip.
+
+[CUDD](https://github.com/cuddorg/cudd) is a binary decision diagram (BDD)
+package that is used to improve conditional timing arc handling, constant
+propagation, power activity propagation and spice netlist generation.
+
+Download and build CUDD:
+
+```
+git clone https://github.com/cuddorg/cudd.git
+cd cudd
+git checkout 3.0.0
+./configure
+make
+```
+
+You can use the "configure --prefix" option and "make install" to install CUDD
+in a different directory.
+
+Modern c++ compilers that support c++20 include support for std::format.
+With older compilers like gcc 11 on Ubuntu 22.04 and Centos7 the fmt library
+is used instead. If it is not installed locally, the github repository is
+downloaded and compiled in the build directory.
+
+### Building with CMake
+
+Use the following commands to checkout the git repository and build the
+OpenSTA library and excutable.
+
+```
+git clone https://github.com/parallaxsw/OpenSTA.git
+cd OpenSTA
+mkdir build
+cd build
+cmake -DCUDD_DIR=<CUDD_INSTALL_DIR> ..
+make
+```
+The default build type is release to compile optimized code.
+The resulting executable is in `build/sta`.
+The library without a `main()` procedure is `build/libOpenSTA.a`.
+
+Optional CMake variables passed as -D<var>=<value> arguments to CMake are show below.
+
+```
+CMAKE_BUILD_TYPE DEBUG|RELEASE
+CMAKE_CXX_FLAGS - additional compiler flags
+TCL_LIBRARY - path to tcl library
+TCL_HEADER - path to tcl.h
+CUDD_DIR - path to cudd installation
+ZLIB_ROOT - path to zlib
+CMAKE_INSTALL_PREFIX
+```
+
+If `TCL_LIBRARY` is specified the CMake script will attempt to locate
+the header from the library path.
+
+The default install directory is `/usr/local`.
+To install in a different directory with CMake use the CMAKE_INSTALL_PREFIX option.
+
+If you make changes to `CMakeLists.txt` you may need to clean out
+existing CMake cached variable values by deleting all of the
+files in the build directory.
+
+## Build with Docker
+
+AN alternative way to build and run OpenSTA is with
+[Docker](https://www.docker.com).  After installing Docker, the
+following command builds a Docker image.
+
+```
+cd OpenSTA
+docker build --file Dockerfile.ubuntu24.04 --tag opensta_ubuntu24.04 .
+or
+docker build --file Dockerfile.centos7 --tag opensta_centos7 .
+```
+
+The centos7 build on mac/OsX with ARM processorts requires the platform
+to be specified.
+
+```
+docker build --file Dockerfile.centos7 --platform=linux/amd64 --tag opensta_centos7 .
+
+```
+
+To run a docker container using the OpenSTA image, use the -v option
+to docker to mount direcories with data to use and -i to run
+interactively.
+
+```
+docker run -i -v $HOME:/data opensta
+```
+
+## Build on Macos/Darwin
+
+The XCode versions of Tcl, Flex and Bison cannot be used to build OpenSTA.
+Use Homebrew to install them. The following command installs the tools
+required to build OpenSTA in the Brewfile.
+
+```
+brew bundle install
+```
+
+Set these variables before using cmake to cirumvent the Xcode versions.
+
+```
+  # flex/bison override apple version
+  export PATH="$(brew --prefix bison)/bin:${PATH}"
+  export PATH="$(brew --prefix flex)/bin:${PATH}"
+  export CMAKE_INCLUDE_PATH="$(brew --prefix flex)/include"
+  export CMAKE_LIBRARY_PATH="$(brew --prefix flex)/lib;$(brew --prefix bison)/lib"
+```
+
+Homebrew does not support tclreadline, but the macports system does
+(see https://www.macports.org). 
+
+## Install using a package manager
+
+### Guix
+
+OpenSTA is available in the [default repositories](https://hpc.guix.info/package/opensta):
+
+```
+  guix install opensta
+```
+
+## Bug Reports
+
+Use the Issues tab on the github repository to report bugs.
+
+Each issue/bug should be a separate issue. The subject of the issue
+should be a short description of the problem. Attach a test case to
+reproduce the issue as described below. Issues without test cases are
+unlikely to get a response.
+
+The test case should have a tcl command file recreates the issue named
+run.tcl. If is are more than one command file using the same data
+files, there should be separate command files, run1.tcl, run2.tcl
+etc. The bug report can refer to these command files by name.
+
+Command files should not have absolute filenames like
+"/home/john/OpenSTA_bug/write_path_spice/dump_spice" in them.
+These obviously are not portable. Use filenames relative to the test
+case directory.
+
+The files in the test case should be collected into a directory.
+The contents of the directory should be collected into a compressed
+tarfile.
+
+## Contributions
+
+Contributors must sign the Contributor License Agreement (doc/CLA.txt)
+when submitting pull requests.
+
+All contributors should read doc/CodingGuidelines.txt for notes on
+making code that adheres to the existing naming and formatting style.
+
+Contributions that claim 4% performance improvements in OpenROAD flow
+scripts will largely be ignored. Small performance improvements
+simply do not justify the time required to audit and verify the changes.
+
+Contributions that add dependencies on external libraries like boost,
+abseil and Intel TBB will not be accepted.
+
+As the author of OpenSTA I vastly prefer writing code to reviewing
+code.  I don't have the patience to go round after round to correct
+code formatting that is not consistent with the rest of the code.
+
+## Authors
+
+* James Cherry
+
+* William Scott authored the arnoldi delay calculator at Blaze, Inc
+  which was subsequently licensed to Nefelus, Inc that has graciously
+  contributed it to OpenSTA.
+
+## License
+
+OpenSTA, Static Timing Analyzer
+Copyright (c) 2023, Parallax Software, Inc.
+
+This program is free software: you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation, either version 3 of the License, or
+(at your option) any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program. If not, see <https://www.gnu.org/licenses/>.

The-OpenROAD-Project_OpenSTA/app/Main.cc

@@ -0,0 +1,215 @@
+// OpenSTA, Static Timing Analyzer
+// Copyright (c) 2025, Parallax Software, Inc.
+// 
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+// 
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+// 
+// You should have received a copy of the GNU General Public License
+// along with this program. If not, see <https://www.gnu.org/licenses/>.
+// 
+// The origin of this software must not be misrepresented; you must not
+// claim that you wrote the original software.
+// 
+// Altered source versions must be plainly marked as such, and must not be
+// misrepresented as being the original software.
+// 
+// This notice may not be removed or altered from any source distribution.
+
+#include "StaMain.hh"
+#include "StaConfig.hh"  // STA_VERSION
+
+#include <stdio.h>
+#include <cstdlib>              // exit
+#include <filesystem>
+#include <string_view>
+#include <tcl.h>
+
+#ifdef BAZEL_BUILD
+  #include "bazel/tcl_library_init.h"
+  #include "src/tcl_readline_setup.h"
+#endif
+
+#if TCL_READLINE
+  #include <tclreadline.h>
+#endif
+
+#include "Sta.hh"
+
+namespace sta {
+extern const char *tcl_inits[];
+}
+
+using sta::stringEq;
+using sta::findCmdLineFlag;
+using sta::Sta;
+using sta::initSta;
+using sta::evalTclInit;
+using sta::sourceTclFile;
+using sta::parseThreadsArg;
+using sta::tcl_inits;
+
+// Swig uses C linkage for init functions.
+extern "C" {
+extern int Sta_Init(Tcl_Interp *interp);
+}
+
+static int cmd_argc;
+static char **cmd_argv;
+static const char *init_filename = ".sta";
+
+static void
+showUsage(std::string_view prog,
+          std::string_view init_filename);
+static int
+tclAppInit(Tcl_Interp *interp);
+static int
+staTclAppInit(int argc,
+              char *argv[],
+              std::string_view init_filename,
+              Tcl_Interp *interp);
+static void
+initStaApp(int &argc,
+           char *argv[],
+           Tcl_Interp *interp);
+
+int
+main(int argc,
+     char *argv[])
+{
+  if (argc == 2 && stringEq(argv[1], "-help")) {
+    showUsage(argv[0], init_filename);
+    return 0;
+  }
+  else if (argc == 2 && stringEq(argv[1], "-version")) {
+    printf("%s\n", STA_VERSION);
+    return 0;
+  }
+  else {
+    // Set argc to 1 so Tcl_Main doesn't source any files.
+    // Store argc and argv in static variables for tclAppInit.
+    cmd_argc = argc;
+    cmd_argv = argv;
+    // Tcl_Main never returns.
+    Tcl_Main(1, argv, tclAppInit);
+    return 0;
+  }
+}
+
+static int
+tclAppInit(Tcl_Interp *interp)
+{
+  return staTclAppInit(cmd_argc, cmd_argv, init_filename, interp);
+}
+
+// Tcl init executed inside Tcl_Main.
+static int
+staTclAppInit(int argc,
+              char *argv[],
+              std::string_view init_filename,
+              Tcl_Interp *interp)
+{
+#ifdef BAZEL_BUILD
+    if (in_bazel::SetupTclEnvironment(interp) == TCL_ERROR) {
+      return TCL_ERROR;
+    }
+#endif
+
+  // source init.tcl
+  if (Tcl_Init(interp) == TCL_ERROR)
+    return TCL_ERROR;
+
+  bool has_readline = false;
+#ifdef BAZEL_BUILD
+  has_readline = (ord::SetupTclReadlineLibrary(interp) == TCL_OK);
+#endif
+#if TCL_READLINE
+  if (Tclreadline_Init(interp) == TCL_ERROR)
+    return TCL_ERROR;
+  Tcl_StaticPackage(interp, "tclreadline", Tclreadline_Init, Tclreadline_SafeInit);
+  if (Tcl_EvalFile(interp, TCLRL_LIBRARY "/tclreadlineInit.tcl") != TCL_OK)
+    printf("Failed to load tclreadline.tcl\n");
+  else
+    has_readline = true;
+#endif
+
+  initStaApp(argc, argv, interp);
+
+  if (!findCmdLineFlag(argc, argv, "-no_splash"))
+    Tcl_Eval(interp, "sta::show_splash");
+
+  if (!findCmdLineFlag(argc, argv, "-no_init")) {
+    const char *home = getenv("HOME");
+    if (home) {
+      std::string init_path = home;
+      init_path += "/";
+      init_path.append(init_filename);
+      if (std::filesystem::is_regular_file(init_path.c_str()))
+        sourceTclFile(init_path.c_str(), true, true, interp);
+    }
+  }
+
+  bool exit_after_cmd_file = findCmdLineFlag(argc, argv, "-exit");
+
+  if (argc > 2
+      || (argc > 1 && argv[1][0] == '-')) {
+    showUsage(argv[0], init_filename);
+    exit(1);
+  }
+  else {
+    if (argc == 2) {
+      char *cmd_file = argv[1];
+      if (cmd_file) {
+        int result = sourceTclFile(cmd_file, false, false, interp);
+        if (exit_after_cmd_file) {
+          int exit_code = (result == TCL_OK) ? EXIT_SUCCESS : EXIT_FAILURE;
+          exit(exit_code);
+        }
+      }
+    }
+  }
+
+  return has_readline ? Tcl_Eval(interp, "::tclreadline::Loop") : TCL_OK;
+}
+
+static void
+initStaApp(int &argc,
+           char *argv[],
+           Tcl_Interp *interp)
+{
+  initSta();
+  Sta *sta = new Sta;
+  Sta::setSta(sta);
+  sta->makeComponents();
+  sta->setTclInterp(interp);
+  int thread_count = parseThreadsArg(argc, argv);
+  sta->setThreadCount(thread_count);
+
+  // Define swig TCL commands.
+  Sta_Init(interp);
+  // Eval encoded sta TCL sources.
+  evalTclInit(interp, tcl_inits);
+  Tcl_Eval(interp, "init_sta_cmds");
+}
+
+static void
+showUsage(std::string_view prog,
+          std::string_view init_filename)
+{
+  sta::print(stdout, "Usage: {} [-help] [-version] [-no_init] [-exit] cmd_file\n",
+             prog);
+  sta::print(stdout, "  -help              show help and exit\n");
+  sta::print(stdout, "  -version           show version and exit\n");
+  sta::print(stdout, "  -no_init           do not read {} init file\n",
+             init_filename);
+  sta::print(stdout, "  -threads count|max use count threads\n");
+  sta::print(stdout, "  -no_splash         do not show the license splash at startup\n");
+  sta::print(stdout, "  -exit              exit after reading cmd_file\n");
+  sta::print(stdout, "  cmd_file           source cmd_file\n");
+}

The-OpenROAD-Project_OpenSTA/app/StaApp.i

@@ -0,0 +1,42 @@
+%module sta
+
+// OpenSTA, Static Timing Analyzer
+// Copyright (c) 2025, Parallax Software, Inc.
+// 
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+// 
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+// 
+// You should have received a copy of the GNU General Public License
+// along with this program. If not, see <https://www.gnu.org/licenses/>.
+// 
+// The origin of this software must not be misrepresented; you must not
+// claim that you wrote the original software.
+// 
+// Altered source versions must be plainly marked as such, and must not be
+// misrepresented as being the original software.
+// 
+// This notice may not be removed or altered from any source distribution.
+
+%include "tcl/Exception.i"
+%include "tcl/StaTclTypes.i"
+%include "dcalc/DelayCalc.i"
+%include "graph/Graph.i"
+%include "liberty/Liberty.i"
+%include "network/Network.i"
+%include "network/NetworkEdit.i"
+%include "parasitics/Parasitics.i"
+%include "power/Power.i"
+%include "sdc/Sdc.i"
+%include "sdf/Sdf.i"
+%include "search/Search.i"
+%include "search/Property.i"
+%include "util/Util.i"
+%include "spice/WriteSpice.i"
+%include "verilog/Verilog.i"

The-OpenROAD-Project_OpenSTA/app/StaMain.cc

@@ -0,0 +1,151 @@
+// OpenSTA, Static Timing Analyzer
+// Copyright (c) 2026, Parallax Software, Inc.
+// 
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+// 
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+// 
+// You should have received a copy of the GNU General Public License
+// along with this program. If not, see <https://www.gnu.org/licenses/>.
+// 
+// The origin of this software must not be misrepresented; you must not
+// claim that you wrote the original software.
+// 
+// Altered source versions must be plainly marked as such, and must not be
+// misrepresented as being the original software.
+// 
+// This notice may not be removed or altered from any source distribution.
+
+#include "StaMain.hh"
+
+#include <string>
+#include <string_view>
+#include <tcl.h>
+#include <cstdlib>
+#include <sys/stat.h>
+
+#include "Machine.hh"
+#include "StringUtil.hh"
+#include "Sta.hh"
+
+namespace sta {
+
+int
+parseThreadsArg(int &argc,
+                char *argv[])
+{
+  char *thread_arg = findCmdLineKey(argc, argv, "-threads");
+  if (thread_arg) {
+    if (stringEqual(thread_arg, "max"))
+      return processorCount();
+    else if (isDigits(thread_arg))
+      return std::stoi(thread_arg);
+    else
+      fprintf(stderr,"Warning: -threads must be max or a positive integer.\n");
+  }
+  return 1;
+}
+
+bool
+findCmdLineFlag(int &argc,
+                char *argv[],
+                std::string_view flag)
+{
+  for (int i = 1; i < argc; i++) {
+    char *arg = argv[i];
+    if (std::string_view(arg) == flag) {
+      // Remove flag from argv.
+      for (int j = i + 1; j < argc; j++, i++)
+        argv[i] = argv[j];
+      argc--;
+      argv[argc] = nullptr;
+      return true;
+    }
+  }
+  return false;
+}
+
+char *
+findCmdLineKey(int &argc,
+               char *argv[],
+               std::string_view key)
+{
+  for (int i = 1; i < argc; i++) {
+    char *arg = argv[i];
+    if (std::string_view(arg) == key && i + 1 < argc) {
+      char *value = argv[i + 1];
+      // Remove key and value from argv.
+      for (int j = i + 2; j < argc; j++, i++)
+        argv[i] = argv[j];
+      argc -= 2;
+      argv[argc] = nullptr;
+      return value;
+    }
+  }
+  return nullptr;
+}
+
+// Use overridden version of source to echo cmds and results.
+int
+sourceTclFile(const char *filename,
+              bool echo,
+              bool verbose,
+              Tcl_Interp *interp)
+{
+  std::string cmd = sta::format("sta::include_file {} {} {}",
+                                filename,
+                                echo ? "1" : "0",
+                                verbose ? "1" : "0");
+  int code = Tcl_Eval(interp, cmd.c_str());
+  const char *result = Tcl_GetStringResult(interp);
+  if (result[0] != '\0')
+    printf("%s\n", result);
+  return code;
+}
+
+void
+evalTclInit(Tcl_Interp *interp,
+            const char *inits[])
+{
+  char *unencoded = unencode(inits);
+  if (Tcl_Eval(interp, unencoded) != TCL_OK) {
+    // Get a backtrace for the error.
+    Tcl_Eval(interp, "$errorInfo");
+    const char *tcl_err = Tcl_GetStringResult(interp);
+    fprintf(stderr, "Error: TCL init script: %s.\n", tcl_err);
+    fprintf(stderr, "       Try deleting TclInitVar.cc and rebuilding.\n");
+    exit(0);
+  }
+  delete [] unencoded;
+}
+
+char *
+unencode(const char *inits[])
+{
+  size_t length = 0;
+  for (const char **e = inits; *e; e++) {
+    const char *init = *e;
+    length += strlen(init);
+  }
+  char *unencoded = new char[length / 3 + 1];
+  char *u = unencoded;
+  for (const char **e = inits; *e; e++) {
+    const char *init = *e;
+    size_t init_length = strlen(init);
+    for (const char *s = init; s < &init[init_length]; s += 3) {
+      char code[4] = {s[0], s[1], s[2], '\0'};
+      char ch = atoi(code);
+      *u++ = ch;
+    }
+  }
+  *u = '\0';
+  return unencoded;
+}
+
+} // namespace sta

The-OpenROAD-Project_OpenSTA/cmake/FindCUDD.cmake

@@ -0,0 +1,25 @@
+################################################################
+#
+# Locate CUDD bdd package.
+#
+################################################################
+find_library(CUDD_LIB
+  NAME cudd
+  PATHS ${CUDD_DIR}
+  PATH_SUFFIXES lib lib/cudd cudd/.libs
+  )
+if (CUDD_LIB)
+  message(STATUS "CUDD library: ${CUDD_LIB}")
+  get_filename_component(CUDD_LIB_DIR "${CUDD_LIB}" PATH)
+  get_filename_component(CUDD_LIB_PARENT1 "${CUDD_LIB_DIR}" PATH)
+  find_file(CUDD_HEADER cudd.h
+    PATHS ${CUDD_LIB_PARENT1} ${CUDD_LIB_PARENT1}/include ${CUDD_LIB_PARENT1}/include/cudd)
+  if (CUDD_HEADER)
+    get_filename_component(CUDD_INCLUDE "${CUDD_HEADER}" PATH)
+    message(STATUS "CUDD header: ${CUDD_HEADER}")
+  else()
+    message(STATUS "CUDD header: not found")
+  endif()
+else()
+  message(STATUS "CUDD library: not found")
+endif()

The-OpenROAD-Project_OpenSTA/cmake/FindTCL.cmake

@@ -0,0 +1,81 @@
+# OpenSTA, Static Timing Analyzer
+# Copyright (c) 2019, Parallax Software, Inc.
+# 
+# This program is free software: you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation, either version 3 of the License, or
+# (at your option) any later version.
+# 
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+# 
+# You should have received a copy of the GNU General Public License
+# along with this program.  If not, see <https://www.gnu.org/licenses/>.
+
+################################################################
+#
+# Locate TCL library.
+#
+# Note that the cmake findTcl module is hopeless for OSX
+# because there doesn't appear to be a way to override
+# searching OSX system directories before unix directories.
+
+set(TCL_POSSIBLE_NAMES
+  #tcl90 tcl9.0
+  tcl87 tcl8.7
+  tcl86 tcl8.6
+  tcl85 tcl8.5
+  )
+
+# TCL lib path guesses.
+if (NOT TCL_LIB_PATHS)
+  if (CMAKE_SYSTEM_NAME STREQUAL "Darwin")
+    file(GLOB tcl_homebrew_libs
+      /opt/homebrew/Cellar/tcl-tk@8/*/lib
+    )
+    set(TCL_LIB_PATHS
+      ${tcl_homebrew_libs}
+      /opt/homebrew/opt/tcl-tk/lib /usr/local/lib)
+    set(TCL_NO_DEFAULT_PATH TRUE)
+  elseif (CMAKE_SYSTEM_NAME STREQUAL "Linux")
+    set(TCL_LIB_PATHS /usr/lib /usr/lib64 /usr/local/lib)
+    set(TCL_NO_DEFAULT_PATH FALSE)
+  endif()
+endif()
+
+if (NOT TCL_LIBRARY)
+  # bagbiter cmake doesn't have a way to pass NO_DEFAULT_PATH as a parameter.
+  if (TCL_NO_DEFAULT_PATH)
+    find_library(TCL_LIBRARY
+      NAMES tcl ${TCL_POSSIBLE_NAMES}
+      PATHS ${TCL_LIB_PATHS}
+      NO_DEFAULT_PATH
+      )
+  else()
+    find_library(TCL_LIBRARY
+      NAMES tcl ${TCL_POSSIBLE_NAMES}
+      PATHS ${TCL_LIB_PATHS}
+      )
+  endif()
+endif()
+message(STATUS "TCL library: ${TCL_LIBRARY}")
+
+get_filename_component(TCL_LIB_DIR "${TCL_LIBRARY}" PATH)
+get_filename_component(TCL_LIB_PARENT1 "${TCL_LIB_DIR}" PATH)
+get_filename_component(TCL_LIB_PARENT2 "${TCL_LIB_PARENT1}" PATH)
+
+# Locate tcl.h
+if (NOT TCL_HEADER)
+  find_file(TCL_HEADER tcl.h
+    PATHS ${TCL_LIB_PARENT1} ${TCL_LIB_PARENT2}
+    PATH_SUFFIXES include include/tcl include/tcl-tk
+    NO_DEFAULT_PATH
+    )
+endif()
+message(STATUS "TCL header: ${TCL_HEADER}")
+
+if (TCL_HEADER)
+  get_filename_component(TCL_INCLUDE_PATH "${TCL_HEADER}" PATH)
+endif()

The-OpenROAD-Project_OpenSTA/cmake/GetGitRevisionDescription.cmake

@@ -0,0 +1,168 @@
+# - Returns a version string from Git
+#
+# These functions force a re-configure on each git commit so that you can
+# trust the values of the variables in your build system.
+#
+#  get_git_head_revision(<refspecvar> <hashvar> [<additional arguments to git describe> ...])
+#
+# Returns the refspec and sha hash of the current head revision
+#
+#  git_describe(<var> [<additional arguments to git describe> ...])
+#
+# Returns the results of git describe on the source tree, and adjusting
+# the output so that it tests false if an error occurs.
+#
+#  git_get_exact_tag(<var> [<additional arguments to git describe> ...])
+#
+# Returns the results of git describe --exact-match on the source tree,
+# and adjusting the output so that it tests false if there was no exact
+# matching tag.
+#
+#  git_local_changes(<var>)
+#
+# Returns either "CLEAN" or "DIRTY" with respect to uncommitted changes.
+# Uses the return code of "git diff-index --quiet HEAD --".
+# Does not regard untracked files.
+#
+# Requires CMake 2.6 or newer (uses the 'function' command)
+#
+# Original Author:
+# 2009-2010 Ryan Pavlik <rpavlik@iastate.edu> <abiryan@ryand.net>
+# http://academic.cleardefinition.com
+# Iowa State University HCI Graduate Program/VRAC
+#
+# Copyright Iowa State University 2009-2010.
+# Distributed under the Boost Software License, Version 1.0.
+# (See accompanying file LICENSE_1_0.txt or copy at
+# http://www.boost.org/LICENSE_1_0.txt)
+
+if(__get_git_revision_description)
+	return()
+endif()
+set(__get_git_revision_description YES)
+
+# We must run the following at "include" time, not at function call time,
+# to find the path to this module rather than the path to a calling list file
+get_filename_component(_gitdescmoddir ${CMAKE_CURRENT_LIST_FILE} PATH)
+
+function(get_git_head_revision _refspecvar _hashvar)
+	set(GIT_PARENT_DIR "${CMAKE_CURRENT_SOURCE_DIR}")
+	set(GIT_DIR "${GIT_PARENT_DIR}/.git")
+	while(NOT EXISTS "${GIT_DIR}")	# .git dir not found, search parent directories
+		set(GIT_PREVIOUS_PARENT "${GIT_PARENT_DIR}")
+		get_filename_component(GIT_PARENT_DIR ${GIT_PARENT_DIR} PATH)
+		if(GIT_PARENT_DIR STREQUAL GIT_PREVIOUS_PARENT)
+			# We have reached the root directory, we are not in git
+			set(${_refspecvar} "GITDIR-NOTFOUND" PARENT_SCOPE)
+			set(${_hashvar} "GITDIR-NOTFOUND" PARENT_SCOPE)
+			return()
+		endif()
+		set(GIT_DIR "${GIT_PARENT_DIR}/.git")
+	endwhile()
+	# check if this is a submodule
+	if(NOT IS_DIRECTORY ${GIT_DIR})
+		file(READ ${GIT_DIR} submodule)
+		string(REGEX REPLACE "gitdir: (.*)\n$" "\\1" GIT_DIR_RELATIVE ${submodule})
+		get_filename_component(SUBMODULE_DIR ${GIT_DIR} PATH)
+		get_filename_component(GIT_DIR ${SUBMODULE_DIR}/${GIT_DIR_RELATIVE} ABSOLUTE)
+	endif()
+	set(GIT_DATA "${CMAKE_CURRENT_BINARY_DIR}/CMakeFiles/git-data")
+	if(NOT EXISTS "${GIT_DATA}")
+		file(MAKE_DIRECTORY "${GIT_DATA}")
+	endif()
+
+	if(NOT EXISTS "${GIT_DIR}/HEAD")
+		return()
+	endif()
+	set(HEAD_FILE "${GIT_DATA}/HEAD")
+	configure_file("${GIT_DIR}/HEAD" "${HEAD_FILE}" COPYONLY)
+
+	configure_file("${_gitdescmoddir}/GetGitRevisionDescription.cmake.in"
+		"${GIT_DATA}/grabRef.cmake"
+		@ONLY)
+	include("${GIT_DATA}/grabRef.cmake")
+
+	set(${_refspecvar} "${HEAD_REF}" PARENT_SCOPE)
+	set(${_hashvar} "${HEAD_HASH}" PARENT_SCOPE)
+endfunction()
+
+function(git_describe _var)
+	if(NOT GIT_FOUND)
+		find_package(Git QUIET)
+	endif()
+	get_git_head_revision(refspec hash)
+	if(NOT GIT_FOUND)
+		set(${_var} "GIT-NOTFOUND" PARENT_SCOPE)
+		return()
+	endif()
+	if(NOT hash)
+		set(${_var} "HEAD-HASH-NOTFOUND" PARENT_SCOPE)
+		return()
+	endif()
+
+	# TODO sanitize
+	#if((${ARGN}" MATCHES "&&") OR
+	#	(ARGN MATCHES "||") OR
+	#	(ARGN MATCHES "\\;"))
+	#	message("Please report the following error to the project!")
+	#	message(FATAL_ERROR "Looks like someone's doing something nefarious with git_describe! Passed arguments ${ARGN}")
+	#endif()
+
+	#message(STATUS "Arguments to execute_process: ${ARGN}")
+
+	execute_process(COMMAND
+		"${GIT_EXECUTABLE}"
+		describe
+		${hash}
+		${ARGN}
+		WORKING_DIRECTORY
+		"${CMAKE_CURRENT_SOURCE_DIR}"
+		RESULT_VARIABLE
+		res
+		OUTPUT_VARIABLE
+		out
+		ERROR_QUIET
+		OUTPUT_STRIP_TRAILING_WHITESPACE)
+	if(NOT res EQUAL 0)
+		set(out "${out}-${res}-NOTFOUND")
+	endif()
+
+	set(${_var} "${out}" PARENT_SCOPE)
+endfunction()
+
+function(git_get_exact_tag _var)
+	git_describe(out --exact-match ${ARGN})
+	set(${_var} "${out}" PARENT_SCOPE)
+endfunction()
+
+function(git_local_changes _var)
+	if(NOT GIT_FOUND)
+		find_package(Git QUIET)
+	endif()
+	get_git_head_revision(refspec hash)
+	if(NOT GIT_FOUND)
+		set(${_var} "GIT-NOTFOUND" PARENT_SCOPE)
+		return()
+	endif()
+	if(NOT hash)
+		set(${_var} "HEAD-HASH-NOTFOUND" PARENT_SCOPE)
+		return()
+	endif()
+
+	execute_process(COMMAND
+		"${GIT_EXECUTABLE}"
+		diff-index --quiet HEAD --
+		WORKING_DIRECTORY
+		"${CMAKE_CURRENT_SOURCE_DIR}"
+		RESULT_VARIABLE
+		res
+		OUTPUT_VARIABLE
+		out
+		ERROR_QUIET
+		OUTPUT_STRIP_TRAILING_WHITESPACE)
+	if(res EQUAL 0)
+		set(${_var} "CLEAN" PARENT_SCOPE)
+	else()
+		set(${_var} "DIRTY" PARENT_SCOPE)
+	endif()
+endfunction()

The-OpenROAD-Project_OpenSTA/cmake/GetGitRevisionDescription.cmake.in

@@ -0,0 +1,41 @@
+#
+# Internal file for GetGitRevisionDescription.cmake
+#
+# Requires CMake 2.6 or newer (uses the 'function' command)
+#
+# Original Author:
+# 2009-2010 Ryan Pavlik <rpavlik@iastate.edu> <abiryan@ryand.net>
+# http://academic.cleardefinition.com
+# Iowa State University HCI Graduate Program/VRAC
+#
+# Copyright Iowa State University 2009-2010.
+# Distributed under the Boost Software License, Version 1.0.
+# (See accompanying file LICENSE_1_0.txt or copy at
+# http://www.boost.org/LICENSE_1_0.txt)
+
+set(HEAD_HASH)
+
+file(READ "@HEAD_FILE@" HEAD_CONTENTS LIMIT 1024)
+
+string(STRIP "${HEAD_CONTENTS}" HEAD_CONTENTS)
+if(HEAD_CONTENTS MATCHES "ref")
+	# named branch
+	string(REPLACE "ref: " "" HEAD_REF "${HEAD_CONTENTS}")
+	if(EXISTS "@GIT_DIR@/${HEAD_REF}")
+		configure_file("@GIT_DIR@/${HEAD_REF}" "@GIT_DATA@/head-ref" COPYONLY)
+	else()
+		configure_file("@GIT_DIR@/packed-refs" "@GIT_DATA@/packed-refs" COPYONLY)
+		file(READ "@GIT_DATA@/packed-refs" PACKED_REFS)
+		if(${PACKED_REFS} MATCHES "([0-9a-z]*) ${HEAD_REF}")
+			set(HEAD_HASH "${CMAKE_MATCH_1}")
+		endif()
+	endif()
+else()
+	# detached HEAD
+	configure_file("@GIT_DIR@/HEAD" "@GIT_DATA@/head-ref" COPYONLY)
+endif()
+
+if(NOT HEAD_HASH)
+	file(READ "@GIT_DATA@/head-ref" HEAD_HASH LIMIT 1024)
+	string(STRIP "${HEAD_HASH}" HEAD_HASH)
+endif()

The-OpenROAD-Project_OpenSTA/dcalc/ArcDcalcWaveforms.cc

@@ -0,0 +1,87 @@
+// OpenSTA, Static Timing Analyzer
+// Copyright (c) 2026, Parallax Software, Inc.
+// 
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+// 
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+// 
+// You should have received a copy of the GNU General Public License
+// along with this program. If not, see <https://www.gnu.org/licenses/>.
+// 
+// The origin of this software must not be misrepresented; you must not
+// claim that you wrote the original software.
+// 
+// Altered source versions must be plainly marked as such, and must not be
+// misrepresented as being the original software.
+// 
+// This notice may not be removed or altered from any source distribution.
+
+#include "ArcDcalcWaveforms.hh"
+
+#include <memory>
+
+#include "ArcDelayCalc.hh"
+#include "Graph.hh"
+#include "GraphDelayCalc.hh"
+#include "Liberty.hh"
+#include "Network.hh"
+#include "Report.hh"
+
+namespace sta {
+
+Waveform
+ArcDcalcWaveforms::inputWaveform(ArcDcalcArg &dcalc_arg,
+                                 const Scene *scene,
+                                 const MinMax *min_max,
+                                 const StaState *sta)
+{
+  const Network *network = sta->network();
+  Graph *graph = sta->graph();
+  Report *report = sta->report();
+  const Pin *in_pin = dcalc_arg.inPin();
+  LibertyPort *link_port = network->libertyPort(in_pin);
+  if (link_port) {
+    LibertyPort *port = link_port->scenePort(scene, min_max);
+    const RiseFall *in_rf = dcalc_arg.inEdge();
+    DriverWaveform *driver_waveform = port->driverWaveform(in_rf);
+    if (driver_waveform) {
+      const Vertex *in_vertex = graph->pinLoadVertex(in_pin);
+      GraphDelayCalc *graph_dcalc = sta->graphDelayCalc();
+      Slew in_slew = graph_dcalc->edgeFromSlew(in_vertex, in_rf,
+                                               dcalc_arg.arc()->role(),
+                                               scene, min_max);
+      LibertyLibrary *library = port->libertyLibrary();
+      float vdd;
+      bool vdd_exists;
+      library->supplyVoltage("VDD", vdd, vdd_exists);
+      if (!vdd_exists)
+        report->error(1751, "VDD not defined in library {}", library->name());
+      float slew1 = delayAsFloat(in_slew, min_max, sta);
+      Waveform in_waveform = driver_waveform->waveform(slew1);
+      // Delay time axis.
+      FloatSeq time_values;
+      for (float time : in_waveform.axis1()->values())
+        time_values.push_back(time + dcalc_arg.inputDelay());
+      TableAxisPtr time_axis = std::make_shared<TableAxis>(TableAxisVariable::time,
+                                                           std::move(time_values));
+      // Scale the waveform from 0:vdd.
+      FloatSeq *scaled_values = new FloatSeq;
+      for (float value : *in_waveform.values()) {
+        float scaled_value = (in_rf == RiseFall::rise())
+          ? value * vdd
+          : (1.0 - value) * vdd;
+        scaled_values->push_back(scaled_value);
+      }
+      return Waveform(scaled_values, time_axis);
+    }
+  }
+  return Waveform();
+}
+
+} // namespace sta

The-OpenROAD-Project_OpenSTA/dcalc/ArcDcalcWaveforms.hh

@@ -0,0 +1,55 @@
+// OpenSTA, Static Timing Analyzer
+// Copyright (c) 2026, Parallax Software, Inc.
+// 
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+// 
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+// 
+// You should have received a copy of the GNU General Public License
+// along with this program. If not, see <https://www.gnu.org/licenses/>.
+// 
+// The origin of this software must not be misrepresented; you must not
+// claim that you wrote the original software.
+// 
+// Altered source versions must be plainly marked as such, and must not be
+// misrepresented as being the original software.
+// 
+// This notice may not be removed or altered from any source distribution.
+
+#pragma once
+
+#include "MinMax.hh"
+#include "TableModel.hh"
+#include "NetworkClass.hh"
+
+namespace sta {
+
+class StaState;
+class Scene;
+class ArcDcalcArg;
+
+// Abstract class for delay calculation waveforms for ploting.
+class ArcDcalcWaveforms
+{
+public:
+  // Record waveform for drvr/load pin.
+  virtual void watchPin(const Pin *pin) = 0;
+  virtual void clearWatchPins() = 0;
+  virtual PinSeq watchPins() const = 0;
+  virtual Waveform watchWaveform(const Pin *pin) = 0;
+
+protected:
+  Waveform inputWaveform(ArcDcalcArg &dcalc_arg,
+                         const Scene *scene,
+                         const MinMax *min_max,
+                         const StaState *sta);
+};
+
+} // namespace sta
+

The-OpenROAD-Project_OpenSTA/dcalc/ArcDelayCalc.cc

@@ -0,0 +1,305 @@
+// OpenSTA, Static Timing Analyzer
+// Copyright (c) 2026, Parallax Software, Inc.
+// 
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+// 
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+// 
+// You should have received a copy of the GNU General Public License
+// along with this program. If not, see <https://www.gnu.org/licenses/>.
+// 
+// The origin of this software must not be misrepresented; you must not
+// claim that you wrote the original software.
+// 
+// Altered source versions must be plainly marked as such, and must not be
+// misrepresented as being the original software.
+// 
+// This notice may not be removed or altered from any source distribution.
+
+#include "ArcDelayCalc.hh"
+
+#include <cstdlib>
+#include <string>
+
+#include "Graph.hh"
+#include "Liberty.hh"
+#include "Network.hh"
+#include "StringUtil.hh"
+#include "TimingArc.hh"
+#include "Units.hh"
+
+namespace sta {
+
+ArcDelayCalc::ArcDelayCalc(StaState *sta):
+  StaState(sta)
+{
+}
+
+void
+ArcDelayCalc::gateDelay(const TimingArc *arc,
+                        const Slew &in_slew,
+                        float load_cap,
+                        const Parasitic *parasitic,
+                        float,
+                        const Pvt *,
+                        const Scene *scene,
+                        const MinMax *min_max,
+                        // Return values.
+                        ArcDelay &gate_delay,
+                        Slew &drvr_slew)
+{
+  LoadPinIndexMap load_pin_index_map(network_);
+  ArcDcalcResult dcalc_result = gateDelay(nullptr, arc, in_slew, load_cap, parasitic,
+                                          load_pin_index_map, scene, min_max);
+  gate_delay = dcalc_result.gateDelay();
+  drvr_slew = dcalc_result.drvrSlew();
+}
+
+////////////////////////////////////////////////////////////////
+
+// For TCL %typemap(in) ArcDcalcArg.
+ArcDcalcArg
+makeArcDcalcArg(std::string_view inst_name,
+                std::string_view in_port_name,
+                std::string_view in_rf_name,
+                std::string_view drvr_port_name,
+                std::string_view drvr_rf_name,
+                std::string_view input_delay_str,
+                const StaState *sta)
+{
+  Report *report = sta->report();
+  const Network *network = sta->sdcNetwork();
+  const Instance *inst = network->findInstance(inst_name);
+  if (inst) {
+    const Pin *in_pin = network->findPin(inst, in_port_name);
+    if (in_pin) {
+      const RiseFall *in_rf = RiseFall::find(in_rf_name);
+      if (in_rf) {
+        const Pin *drvr_pin = network->findPin(inst, drvr_port_name);
+        if (drvr_pin) {
+          const RiseFall *drvr_rf = RiseFall::find(drvr_rf_name);
+          if (drvr_rf) {
+            const std::string input_delay_buf(input_delay_str);
+            auto [input_delay, valid] = stringFloat(input_delay_buf);
+            input_delay = sta->units()->timeUnit()->userToSta(input_delay);
+
+            const Graph *graph = sta->graph();
+            Edge *edge;
+            const TimingArc *arc;
+            graph->gateEdgeArc(in_pin, in_rf, drvr_pin, drvr_rf, edge, arc);
+            if (edge)
+              return ArcDcalcArg(in_pin, drvr_pin, edge, arc, input_delay);
+            else {
+              const Network *network = sta->network();
+              const Instance *inst = network->instance(in_pin);
+              report->warn(2100, "no timing arc for {} input/driver pins.",
+                           network->pathName(inst));
+            }
+          }
+          else
+            report->warn(2101, "{} not a valid rise/fall.", drvr_rf_name);
+        }
+        else
+          report->warn(2102, "Pin {}/{} not found.", inst_name, drvr_port_name);
+      }
+      else
+        report->warn(2103, "{} not a valid rise/fall.", in_rf_name);
+    }
+    else
+      report->warn(2104, "Pin {}/{} not found.", inst_name, in_port_name);
+  }
+  else
+    report->warn(2105, "Instance {} not found.", inst_name);
+  return ArcDcalcArg();
+}
+
+ArcDcalcArg::ArcDcalcArg() :
+  in_pin_(nullptr),
+  drvr_pin_(nullptr),
+  edge_(nullptr),
+  arc_(nullptr),
+  in_slew_(0.0),
+  load_cap_(0.0),
+  parasitic_(nullptr),
+  input_delay_(0.0)
+{
+}
+
+ArcDcalcArg::ArcDcalcArg(const Pin *in_pin,
+                         const Pin *drvr_pin,
+                         Edge *edge,
+                         const TimingArc *arc,
+                         Slew in_slew,
+                         float load_cap,
+                         const Parasitic *parasitic) :
+  in_pin_(in_pin),
+  drvr_pin_(drvr_pin),
+  edge_(edge),
+  arc_(arc),
+  in_slew_(in_slew),
+  load_cap_(load_cap),
+  parasitic_(parasitic),
+  input_delay_(0.0)
+{
+}
+
+ArcDcalcArg::ArcDcalcArg(const Pin *in_pin,
+                         const Pin *drvr_pin,
+                         Edge *edge,
+                         const TimingArc *arc,
+                         float input_delay) :
+  in_pin_(in_pin),
+  drvr_pin_(drvr_pin),
+  edge_(edge),
+  arc_(arc),
+  in_slew_(0.0),
+  load_cap_(0.0),
+  parasitic_(nullptr),
+  input_delay_(input_delay)
+{
+}
+
+ArcDcalcArg::ArcDcalcArg(const ArcDcalcArg &arg) = default;
+
+const RiseFall *
+ArcDcalcArg::inEdge() const
+{
+  return arc_->fromEdge()->asRiseFall();
+}
+
+Vertex *
+ArcDcalcArg::drvrVertex(const Graph *graph) const
+{
+  return edge_->to(graph);
+}
+
+LibertyCell *
+ArcDcalcArg::drvrCell() const
+{
+
+  return arc_->to()->libertyCell();
+}
+
+LibertyLibrary *
+ArcDcalcArg::drvrLibrary() const
+{
+  return arc_->to()->libertyLibrary();
+}
+
+const RiseFall *
+ArcDcalcArg::drvrEdge() const
+{
+  return arc_->toEdge()->asRiseFall();
+}
+
+void
+ArcDcalcArg::setSceneArc(const Scene *scene,
+                         const MinMax *min_max)
+{
+  arc_ = arc_->sceneArc(scene->libertyIndex(min_max));
+}
+
+const Net *
+ArcDcalcArg::drvrNet(const Network *network) const
+{
+  return network->net(drvr_pin_);
+}
+
+float
+ArcDcalcArg::inSlewFlt() const
+{
+  return delayAsFloat(in_slew_);
+}
+
+void
+ArcDcalcArg::setInSlew(Slew in_slew)
+{
+  in_slew_ = in_slew;
+}
+
+void
+ArcDcalcArg::setParasitic(const Parasitic *parasitic)
+{
+  parasitic_ = parasitic;
+}
+
+void
+ArcDcalcArg::setLoadCap(float load_cap)
+{
+  load_cap_ = load_cap;
+}
+
+void
+ArcDcalcArg::setInputDelay(float input_delay)
+{
+  input_delay_ = input_delay;
+}
+
+////////////////////////////////////////////////////////////////
+
+ArcDcalcResult::ArcDcalcResult() :
+  gate_delay_(0.0),
+  drvr_slew_(0.0)
+{
+}
+
+ArcDcalcResult::ArcDcalcResult(size_t load_count) :
+  gate_delay_(0.0),
+  drvr_slew_(0.0)
+{
+  wire_delays_.resize(load_count);
+  load_slews_.resize(load_count);
+}
+
+void
+ArcDcalcResult::setGateDelay(const ArcDelay &gate_delay)
+{
+  gate_delay_ = gate_delay;
+}
+
+void
+ArcDcalcResult::setDrvrSlew(const Slew &drvr_slew)
+{
+  drvr_slew_ = drvr_slew;
+}
+
+const ArcDelay &
+ArcDcalcResult::wireDelay(size_t load_idx) const
+{
+  return wire_delays_[load_idx];
+}
+
+void
+ArcDcalcResult::setWireDelay(size_t load_idx,
+                             const ArcDelay &wire_delay)
+{
+  wire_delays_[load_idx] = wire_delay;
+}
+
+void
+ArcDcalcResult::setLoadCount(size_t load_count)
+{
+  wire_delays_.resize(load_count);
+  load_slews_.resize(load_count);
+}
+
+const Slew &
+ArcDcalcResult::loadSlew(size_t load_idx) const
+{
+  return load_slews_[load_idx];
+}
+
+void
+ArcDcalcResult::setLoadSlew(size_t load_idx,
+                            const Slew &load_slew)
+{
+  load_slews_[load_idx] = load_slew;
+}
+
+} // namespace sta

The-OpenROAD-Project_OpenSTA/dcalc/Arnoldi.hh

@@ -0,0 +1,88 @@
+// OpenSTA, Static Timing Analyzer
+// Copyright (c) 2026, Parallax Software, Inc.
+// 
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+// 
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+// 
+// You should have received a copy of the GNU General Public License
+// along with this program. If not, see <https://www.gnu.org/licenses/>.
+// 
+// The origin of this software must not be misrepresented; you must not
+// claim that you wrote the original software.
+// 
+// Altered source versions must be plainly marked as such, and must not be
+// misrepresented as being the original software.
+// 
+// This notice may not be removed or altered from any source distribution.
+
+// (c) 2018 Nefelus, Inc.
+//
+// Author: W. Scott
+
+#pragma once
+
+#include "parasitics/ConcreteParasiticsPvt.hh"
+
+namespace sta {
+
+struct delay_work;
+
+class GateTableModel;
+class Pin;
+
+//
+// single-driver arnoldi model
+//
+class arnoldi1
+{
+public:
+  arnoldi1() { order=0; n=0; d=nullptr; e=nullptr; U=nullptr; ctot=0.0; sqc=0.0; }
+  ~arnoldi1();
+  double elmore(int k);
+
+  //
+  // calculate poles/residues for given rdrive
+  //
+  void calculate_poles_res(delay_work *D,double rdrive);
+
+public:
+  int order;
+  int n;     // number of terms, including driver
+  double *d; // [order]
+  double *e; // [order-1]
+  double **U; // [order][n]
+  double ctot;
+  double sqc;
+};
+
+// This is the rcmodel, without Rd.
+// n is the number of terms
+// The vectors U[j] are of size n
+class rcmodel : public ConcreteParasitic,
+                public arnoldi1
+{
+public:
+  ~rcmodel() override;
+  float capacitance() const override;
+  PinSet unannotatedLoads(const Pin *drvr_pin,
+                          const Parasitics *parasitics) const override;
+
+  const Pin **pinV{nullptr}; // [n]
+};
+
+struct timing_table
+{
+  const GateTableModel *table;
+  const LibertyCell *cell;
+  const Pvt *pvt;
+  float in_slew;
+};
+
+} // namespace sta

The-OpenROAD-Project_OpenSTA/dcalc/Arnoldi.txt

@@ -0,0 +1,57 @@
+The method is used for simulation with a time-and-voltage-dependent
+current source.  But it is simpler to describe with a linear driver.
+Suppose we are given:
+  voltage nodes 1,..n initialized to V[j]=1.0
+  a resistor network described by a conductance matrix G[j,k]
+  a drive resistance from node 1 to ground, Rdrv
+  capacitance of the nodes, c[j], also written as a
+  diagonal matrix C[j,k]
+The node voltages will fall to zero with time.
+Matrix equation:
+  GV+CdV/dt = -(V[0]/Rdrv)e0
+where e0 is the unit vector (1,0,0,..0).
+Let G' be the matrix formed by taking G and adding 1/Rdrv in the
+[0,0] position.  Then we are solving  G'V + CdV/dt = 0.
+Let R be the inverse of G'.  (In implementation, R may not actually
+be formed as a matrix, instead some method of producing RV given V).
+The exact solution would diagonalize sqrt(C) R sqrt(C).
+
+The Arnoldi method takes a matrix M and a vector of interest V, and
+considers the subspace of vectors near V in terms of the action of M,
+that is, the space spanned by V, MV, MMV, etc, for a small number of
+powers.  We do this here, but instead of finding the part of MV orthogonal
+to V, we find the part of RCV that is C-orthogonal of V.  We use C
+as the metric, so the basis vectors U0, U1, U2 that we generate satisfy
+  Ui.CUj = (i==j?1:0)
+
+U0 = (1,1,..1)/sqrt(sum C)
+  representing the initial value of V, V[j] = sqrt(n)U0[j] at t=0.
+  sum(C) = C[0]+..C[n-1], so U0.C U0 = 1.
+Let:
+  W = R C U0
+  d0 = U0.C W
+  W' = W - d0 U0
+  e0 = sqrt(W'.C W')
+  U1 = W'/e0
+Then:  U0.C U0 = U1.C U1 = 1, U0.C U1 = 0, and
+  R C U0 = d0 U0 + e0 U1
+Next step:
+  W = R C U1
+  d1 = U1.C W
+  W' = W - d1 U1 - e0 U0
+  e1 = sqrt(W'.C W')
+  U2 = W'/e1
+and we have U2.C U2 = 1, U2.C U1 = U2.C U0 = 0, and
+  RC U1 = e0 U0 + d1 U1 + e1 U2
+In this way, RC, which in nonsymmetric in the original basis,
+becomes a symmetric tridiagonal matrix in the U0,U1,.. basis.
+We stop at, say, U3.  The resulting 4x4 tridiagonal matrix is
+positive definite, because it is the projection of sqrt(C)R sqrt(C)
+to a subspace.  So the eigenvalues of this small tridiagonal matrix
+are guaranteed to be positive.  This is the advantage over AWE.
+
+In the actual implementation, I remember there was some way of
+isolating the node 0 where drive resistance is attached, so that the
+tridiagonal matrix (d,e) can be recalculated without knowing Rdrv,
+and then just the first d0,e0 updated when the Rdrv is known, or 
+when Rdrv changes in a simulation.

The-OpenROAD-Project_OpenSTA/dcalc/ArnoldiDelayCalc.cc

@@ -0,0 +1,1529 @@
+// OpenSTA, Static Timing Analyzer
+// Copyright (c) 2026, Parallax Software, Inc.
+// 
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+// 
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+// 
+// You should have received a copy of the GNU General Public License
+// along with this program. If not, see <https://www.gnu.org/licenses/>.
+// 
+// The origin of this software must not be misrepresented; you must not
+// claim that you wrote the original software.
+// 
+// Altered source versions must be plainly marked as such, and must not be
+// misrepresented as being the original software.
+// 
+// This notice may not be removed or altered from any source distribution.
+
+// (c) 2018 Nefelus, Inc.
+//
+// Author: W. Scott
+
+#include "ArnoldiDelayCalc.hh"
+
+#include <algorithm>
+#include <cmath> // abs
+#include <cstddef>
+#include <cstdio>
+#include <numbers>
+
+#include "ArcDelayCalc.hh"
+#include "Arnoldi.hh"
+#include "ArnoldiReduce.hh"
+#include "Debug.hh"
+#include "DelayCalc.hh"
+#include "Graph.hh"
+#include "GraphDelayCalc.hh"
+#include "Liberty.hh"
+#include "LumpedCapDelayCalc.hh"
+#include "Network.hh"
+#include "Parasitics.hh"
+#include "PortDirection.hh"
+#include "Report.hh"
+#include "Sdc.hh"
+#include "TableModel.hh"
+#include "TimingArc.hh"
+#include "TimingModel.hh"
+#include "Units.hh"
+#include "Variables.hh"
+
+namespace sta {
+// NOLINTBEGIN(modernize-avoid-c-style-cast)
+
+// wireload8 is n^2
+// do not delete arnoldi parasitics
+// handle rspf parasitics?
+
+// mv static functions to ArnoldiDelayCalc
+// need slew only lookup for
+//  ra_delay
+//  ra_get_r
+//  ra_get_s
+
+struct delay_work;
+struct delay_c;
+
+////////////////////////////////////////////////////////////////
+
+static delay_work *delay_work_create();
+static void
+delay_work_destroy(delay_work *D);
+static double *
+delay_work_get_residues(delay_work *D,
+                        int term_index);
+
+static bool
+tridiagEV(int n,
+          const double *din,
+          const double *ein,
+          double *d,
+          double **v);
+
+//////////////////////////////////////////////////////////////
+
+struct delay_c
+{
+  double slew_derate;
+  double vlo;
+  double vhi;
+  double vlg;
+  double smin;
+  double x1;
+  double y1;
+  double vmid;  // falling convention, should be >= 0.5
+};
+
+// workspace for pole-residue -> delay calculations
+// delay_work
+// max order is 32
+struct delay_work
+{
+  double slew_derate;
+  double slew_factor;   // (0,1.0] table_slew = slew_factor * full_slew
+  delay_c cV[2];
+  delay_c *c;
+
+  double lo_thresh;
+  double hi_thresh;
+
+  int nmax;
+  double poles[32];     // 1/tau
+  double **resi;        // resi[jrec][h]  h=0,..order
+  double *v[32];
+  double *w[32];
+  double aa[32];
+};
+
+////////////////////////////////////////////////////////////////
+
+class ArnoldiDelayCalc : public LumpedCapDelayCalc
+{
+public:
+  ArnoldiDelayCalc(StaState *sta);
+  ArnoldiDelayCalc(const ArnoldiDelayCalc &dcalc);
+  ~ArnoldiDelayCalc() override;
+  ArcDelayCalc *copy() override;
+  std::string_view name() const override { return "arnoldi"; }
+  Parasitic *findParasitic(const Pin *drvr_pin,
+                           const RiseFall *rf,
+                           const Scene *scene,
+                           const MinMax *min_max) override;
+  Parasitic *reduceParasitic(const Parasitic *parasitic_network,
+                             const Pin *drvr_pin,
+                             const RiseFall *rf,
+                             const Scene *scene,
+                             const MinMax *min_max) override;
+  ArcDcalcResult inputPortDelay(const Pin *port_pin,
+                                float in_slew,
+                                const RiseFall *rf,
+                                const Parasitic *parasitic,
+                                const LoadPinIndexMap &load_pin_index_map,
+                                const Scene *scene,
+                                const MinMax *min_max) override;
+  ArcDcalcResult gateDelay(const Pin *drvr_pin,
+                           const TimingArc *arc,
+                           const Slew &in_slew,
+                           // Pass in load_cap or parasitic.
+                           float load_cap,
+                           const Parasitic *parasitic,
+                           const LoadPinIndexMap &load_pin_index_map,
+                           const Scene *scene,
+                           const MinMax *min_max) override;
+  std::string reportGateDelay(const Pin *drvr_pin,
+                              const TimingArc *arc,
+                              const Slew &in_slew,
+                              float load_cap,
+                              const Parasitic *parasitic,
+                              const LoadPinIndexMap &load_pin_index_map,
+                              const Scene *scene,
+                              const MinMax *min_max,
+                              int digits) override;
+  void finishDrvrPin() override;
+  void delay_work_set_thresholds(delay_work *D,
+                                 double lo,
+                                 double hi,
+                                 bool rising,
+                                 double derate);
+
+private:
+  ArcDcalcResult gateDelaySlew(const LibertyCell *drvr_cell,
+                               const TimingArc *arc,
+                               const GateTableModel *table_model,
+                               const Slew &in_slew,
+                               const LoadPinIndexMap &load_pin_index_map,
+                               const Pvt *pvt);
+  void ar1_ceff_delay(delay_work *D,
+                      timing_table *tab,
+                      arnoldi1 *mod,
+                      double *delays,
+                      double *slews);
+  double ra_rdelay_1(timing_table *tab,
+                     double ctot);
+  double ra_get_r(delay_work *D,
+                  timing_table *tab,
+                  double rdelay,
+                  double ctot);
+  double ra_get_s(delay_work *D,
+                  timing_table *tab,
+                  double r,
+                  double c);
+  void ra_solve_for_s(delay_work *D,
+                      double p,
+                      double tlohi,
+                      double &s);
+  // from poles and residues, solve for t20,t50,t80
+  void pr_solve1(double s,
+                 int order,
+                 double *p,
+                 double *rr,
+                 double v1,
+                 double *t1);
+  void pr_solve3(double s,
+                 int order,
+                 double *p,
+                 double *rr,
+                 double vhi,
+                 double *thi,
+                 double vmid,
+                 double *tmid,
+                 double vlo,
+                 double *tlo);
+
+  //
+  // routines for linear drive model and ceff
+  //
+ double pr_ceff(double s,
+                double rdrive,
+                int order,
+                double *p,
+                double *rr,
+                double ceff_time);
+  double ra_solve_for_t(double p,
+                        double s,
+                        double v);
+  void ra_solve_for_pt(double ps,
+                       double v,
+                       double *pt,
+                       double *d);
+  void ra_calc_c(double lo,
+                 double hi,
+                 double *c_smin,
+                 double *c_x1,
+                 double *c_y1);
+
+  rcmodel *rcmodel_{nullptr};
+  int _pinNmax;
+  double *_delayV;
+  double *_slewV;
+  int pin_n_;
+  ArnoldiReduce *reduce_;
+  delay_work *delay_work_;
+};
+
+ArcDelayCalc *
+makeArnoldiDelayCalc(StaState *sta)
+{
+  return new ArnoldiDelayCalc(sta);
+}
+
+ArnoldiDelayCalc::ArnoldiDelayCalc(StaState *sta) :
+  LumpedCapDelayCalc(sta),
+  reduce_(new ArnoldiReduce(sta)),
+  delay_work_(delay_work_create())
+{
+  _pinNmax = 1024;
+  _delayV = (double*)malloc(_pinNmax * sizeof(double));
+  _slewV = (double*)malloc(_pinNmax * sizeof(double));
+}
+
+ArnoldiDelayCalc::ArnoldiDelayCalc(const ArnoldiDelayCalc &dcalc) :
+  LumpedCapDelayCalc(dcalc),
+  reduce_(new ArnoldiReduce(this)),
+  delay_work_(delay_work_create())
+{
+  _pinNmax = dcalc._pinNmax;
+  _delayV = (double*)malloc(_pinNmax * sizeof(double));
+  _slewV = (double*)malloc(_pinNmax * sizeof(double));
+}
+
+ArcDelayCalc *
+ArnoldiDelayCalc::copy()
+{
+  return new ArnoldiDelayCalc(*this);
+}
+
+ArnoldiDelayCalc::~ArnoldiDelayCalc()
+{
+  delay_work_destroy(delay_work_);
+  free(_delayV);
+  free(_slewV);
+  delete reduce_;
+  delete rcmodel_;
+}
+
+Parasitic *
+ArnoldiDelayCalc::findParasitic(const Pin *drvr_pin,
+                                const RiseFall *drvr_rf,
+                                const Scene *scene,
+                                const MinMax *min_max)
+{
+  Parasitic *parasitic = nullptr;
+  const Sdc *sdc = scene->sdc();
+  Parasitics *parasitics = scene->parasitics(min_max);
+  if (parasitics == nullptr
+      // set_load net has precedence over parasitics.
+      || network_->direction(drvr_pin)->isInternal())
+    return nullptr;
+  Parasitic *parasitic_network =
+    parasitics->findParasiticNetwork(drvr_pin);
+  if (parasitic_network == nullptr) {
+    Wireload *wireload = sdc->wireload(min_max);
+    if (wireload) {
+      float pin_cap, wire_cap, fanout;
+      bool has_wire_cap;
+      graph_delay_calc_->netCaps(drvr_pin, drvr_rf, scene, min_max,
+                                 pin_cap, wire_cap, fanout, has_wire_cap);
+      parasitic_network = parasitics->makeWireloadNetwork(drvr_pin, wireload,
+                                                          fanout, scene, min_max);
+    }
+  }
+    
+  if (parasitic_network) {
+    rcmodel_ = reduce_->reduceToArnoldi(parasitic_network, drvr_pin,
+                                        parasitics->couplingCapFactor(),
+                                        drvr_rf, scene, min_max);
+    // Arnoldi parasitics are their own class that are not saved in the parasitic db.
+    parasitic = rcmodel_;
+  }
+  return parasitic;
+}
+
+Parasitic *
+ArnoldiDelayCalc::reduceParasitic(const Parasitic *,
+                                  const Pin *,
+                                  const RiseFall *,
+                                  const Scene *,
+                                  const MinMax *)
+{
+  // Decline because reduced arnoldi parasitics are not stored in the parasitics db.
+  return nullptr;
+}
+
+void
+ArnoldiDelayCalc::finishDrvrPin()
+{
+  delete rcmodel_;
+  rcmodel_ = nullptr;
+}
+
+ArcDcalcResult
+ArnoldiDelayCalc::inputPortDelay(const Pin *,
+                                 float in_slew,
+                                 const RiseFall *rf,
+                                 const Parasitic *parasitic,
+                                 const LoadPinIndexMap &load_pin_index_map,
+                                 const Scene *,
+                                 const MinMax *)
+{
+  rcmodel_ = nullptr;
+  _delayV[0] = 0.0;
+  _slewV[0] = in_slew;
+
+  LibertyLibrary *drvr_library = network_->defaultLibertyLibrary();
+  ArcDcalcResult dcalc_result(load_pin_index_map.size());
+  if (parasitic) {
+    rcmodel_ = reinterpret_cast<rcmodel*>(const_cast<Parasitic*>(parasitic));
+    pin_n_ = rcmodel_->n;
+    if (pin_n_ >= _pinNmax) {
+      _pinNmax *= 2;
+      if (pin_n_ >= _pinNmax) _pinNmax += pin_n_;
+      _pinNmax *= 2;
+      _delayV = (double*)realloc(_delayV,_pinNmax * sizeof(double));
+      _slewV = (double*)realloc(_slewV,_pinNmax * sizeof(double));
+    }
+
+    pin_n_ = rcmodel_->n;
+    double slew_derate = drvr_library->slewDerateFromLibrary();
+    double lo_thresh = drvr_library->slewLowerThreshold(rf);
+    double hi_thresh = drvr_library->slewUpperThreshold(rf);
+    bool rising = (rf == RiseFall::rise());
+    delay_work_set_thresholds(delay_work_, lo_thresh, hi_thresh, rising, slew_derate);
+    delay_c *c = delay_work_->c;
+    double c_log = c->vlg;
+
+    for (int j=1;j<pin_n_;j++) {
+      double elmore = rcmodel_->elmore(j);
+      double wire_delay = std::numbers::ln2 * elmore;
+      double load_slew = in_slew + c_log*elmore/slew_derate;
+      _delayV[j] = wire_delay;
+      _slewV[j] = load_slew;
+
+      const Pin *load_pin = rcmodel_->pinV[j];
+      auto load_idx_itr = load_pin_index_map.find(load_pin);
+      if (load_idx_itr != load_pin_index_map.end()) {
+        size_t load_idx = load_idx_itr->second;
+        dcalc_result.setWireDelay(load_idx, wire_delay);
+        dcalc_result.setLoadSlew(load_idx, load_slew);
+      }
+    }
+  }
+  else
+    dcalc_result = makeResult(drvr_library, rf, 0.0, in_slew, load_pin_index_map);
+  return dcalc_result;
+}
+
+ArcDcalcResult
+ArnoldiDelayCalc::gateDelay(const Pin *drvr_pin,
+                            const TimingArc *arc,
+                            const Slew &in_slew,
+                            float load_cap,
+                            const Parasitic *parasitic,
+                            const LoadPinIndexMap &load_pin_index_map,
+                            const Scene *scene,
+                            const MinMax *min_max)
+{
+  const LibertyCell *drvr_cell = arc->from()->libertyCell();
+  ConcreteParasitic *cparasitic =
+    reinterpret_cast<ConcreteParasitic*>(const_cast<Parasitic*>(parasitic));
+  rcmodel_ = dynamic_cast<rcmodel*>(cparasitic);
+  GateTableModel *table_model = arc->gateTableModel(scene, min_max);
+  if (table_model && rcmodel_) {
+    const Pvt *pvt = pinPvt(drvr_pin, scene, min_max);
+    return gateDelaySlew(drvr_cell, arc, table_model, in_slew, load_pin_index_map, pvt);
+  }
+  else
+    return LumpedCapDelayCalc::gateDelay(drvr_pin, arc, in_slew, load_cap,
+                                         parasitic, load_pin_index_map, scene, min_max);
+}
+
+ArcDcalcResult
+ArnoldiDelayCalc::gateDelaySlew(const LibertyCell *drvr_cell,
+                                const TimingArc *arc,
+                                const GateTableModel *table_model,
+                                const Slew &in_slew,
+                                const LoadPinIndexMap &load_pin_index_map,
+                                const Pvt *pvt)
+{
+  pin_n_ = rcmodel_->n;
+  if (pin_n_ >= _pinNmax) {
+    _pinNmax *= 2;
+    if (pin_n_ >= _pinNmax) _pinNmax += pin_n_;
+    _delayV = (double*)realloc(_delayV,_pinNmax * sizeof(double));
+    _slewV = (double*)realloc(_slewV,_pinNmax * sizeof(double));
+  }
+
+  ArcDcalcResult dcalc_result(load_pin_index_map.size());
+  pin_n_ = rcmodel_->n;
+  const RiseFall *rf = arc->toEdge()->asRiseFall();
+  if (table_model && rf) {
+    const LibertyLibrary *drvr_library = drvr_cell->libertyLibrary();
+    double slew_derate = drvr_library->slewDerateFromLibrary();
+    double lo_thresh = drvr_library->slewLowerThreshold(rf);
+    double hi_thresh = drvr_library->slewUpperThreshold(rf);
+    bool rising = (rf == RiseFall::rise());
+    delay_work_set_thresholds(delay_work_, lo_thresh, hi_thresh, rising,
+                              slew_derate);
+    if (rcmodel_->order > 0) {
+      timing_table tab;
+      tab.table = table_model;
+      tab.cell = drvr_cell;
+      tab.pvt = pvt;
+      tab.in_slew = delayAsFloat(in_slew);
+      ar1_ceff_delay(delay_work_, &tab, rcmodel_,
+                     _delayV, _slewV);
+    }
+    dcalc_result.setGateDelay(_delayV[0]);
+    dcalc_result.setDrvrSlew(_slewV[0]);
+
+    if (rcmodel_) {
+      for (int i = 0; i < rcmodel_->n; i++) {
+        const Pin *load_pin = rcmodel_->pinV[i];
+        auto load_idx_itr = load_pin_index_map.find(load_pin);
+        if (load_idx_itr != load_pin_index_map.end()) {
+          size_t load_idx = load_idx_itr->second;
+          double wire_delay = _delayV[i] - _delayV[0];
+          double load_slew = _slewV[i];
+          thresholdAdjust(load_pin, drvr_library, rf, wire_delay, load_slew);
+          dcalc_result.setWireDelay(load_idx, wire_delay);
+          dcalc_result.setLoadSlew(load_idx, load_slew);
+        }
+      }
+    }
+  }
+  return dcalc_result;
+}
+
+std::string
+ArnoldiDelayCalc::reportGateDelay(const Pin *drvr_pin,
+                                  const TimingArc *arc,
+                                  const Slew &in_slew,
+                                  float load_cap,
+                                  const Parasitic *parasitic,
+                                  const LoadPinIndexMap &load_pin_index_map,
+                                  const Scene *scene,
+                                  const MinMax *min_max,
+                                  int digits)
+{
+  return LumpedCapDelayCalc::reportGateDelay(drvr_pin, arc, in_slew, load_cap,
+                                             parasitic, load_pin_index_map,
+                                             scene, min_max, digits);
+}
+
+////////////////////////////////////////////////////////////////
+
+//
+// arnoldi1.cpp
+//
+
+arnoldi1::~arnoldi1()
+{
+  free(d);
+  free(reinterpret_cast<void *>(U));
+}
+
+double
+arnoldi1::elmore(int k)
+{
+  if (order==0) return 0.0;
+  if (order==1) return d[0];
+  double sqctot = 1.0/U[0][0];
+  double tau = d[0] + e[0]*U[1][k]*sqctot;
+  return tau;
+}
+
+delay_work *
+delay_work_create()
+{
+  int j;
+  delay_work *D = (delay_work*)malloc(sizeof(delay_work));
+  D->nmax = 256;
+  D->resi = (double**)malloc(static_cast<size_t>(D->nmax) * sizeof(double *));
+  D->resi[0] = (double*)malloc(static_cast<size_t>(D->nmax) * 32u * sizeof(double));
+  for (j=1;j<D->nmax;j++)
+    D->resi[j] = D->resi[0] + static_cast<ptrdiff_t>(j) * 32;
+  D->v[0] = (double*)malloc(static_cast<size_t>(32) * 32u * sizeof(double));
+  for (j=1;j<32;j++)
+    D->v[j] = D->v[0] + static_cast<ptrdiff_t>(j) * 32;
+  D->w[0] = (double*)malloc(32u * static_cast<size_t>(D->nmax) * sizeof(double));
+  for (j=1;j<32;j++)
+    D->w[j] = D->w[0] + static_cast<ptrdiff_t>(j) * D->nmax;
+  D->lo_thresh = 0.0;
+  D->hi_thresh = 0.0;
+  D->slew_derate = 0.0;
+  D->slew_factor = 0.0;
+  for (j=0;j<2;j++) {
+    D->cV[j].slew_derate = 0.0;
+    D->cV[j].vlo = 0.0;
+    D->cV[j].vhi = 0.0;
+    D->cV[j].vlg = 0.0;
+    D->cV[j].smin = 0.0;
+    D->cV[j].x1 = 0.0;
+    D->cV[j].y1 = 0.0;
+    D->cV[j].vmid = 0.0;
+  }
+  D->c = D->cV;
+  return D;
+}
+
+static void
+delay_work_destroy(delay_work *D)
+{
+  free(D->resi[0]);
+  free(reinterpret_cast<void *>(D->resi));
+  free(D->v[0]);
+  free(D->w[0]);
+  free(D);
+}
+
+static void
+delay_work_alloc(delay_work *D,int n)
+{
+  if (n<=D->nmax) return;
+  free(D->w[0]);
+  free(D->resi[0]);
+  free(reinterpret_cast<void *>(D->resi));
+  D->nmax *= 2;
+  D->nmax = std::max(n, D->nmax);
+  int j;
+  D->resi = (double**)malloc(static_cast<size_t>(D->nmax) * sizeof(double *));
+  D->resi[0] = (double*)malloc(static_cast<size_t>(D->nmax) * 32u * sizeof(double));
+  for (j=1;j<D->nmax;j++)
+    D->resi[j] = D->resi[0] + static_cast<ptrdiff_t>(j) * 32;
+  D->w[0] = (double*)malloc(32u * static_cast<size_t>(D->nmax) * sizeof(double));
+  for (j=1;j<32;j++)
+    D->w[j] = D->w[0] + static_cast<ptrdiff_t>(j) * D->nmax;
+}
+
+void
+ArnoldiDelayCalc::delay_work_set_thresholds(delay_work *D,
+                                            double lo,
+                                            double hi,
+                                            bool rising,
+                                            double derate)
+{
+  double mid = 0.5;  // 0.0:1.0
+  int i = rising?1:0;
+  D->c = D->cV+ i;
+  // WRONG
+  bool changed = (lo != D->c->vlo || hi != D->c->vhi);
+  if (changed) {
+    if (!(lo>0.01 && hi<0.99)) {
+      lo = 0.1;
+      hi = 0.9;
+      derate = 0.8;
+    }
+    D->c->slew_derate = derate;
+    D->c->vlo = lo;
+    D->c->vhi = hi;
+    D->c->vmid = mid;
+    D->c->vlg = log(hi/lo);
+    ra_calc_c(lo,hi,
+              &(D->c->smin), &(D->c->x1),&(D->c->y1));
+  }
+  D->lo_thresh = D->c->vlo;
+  D->hi_thresh = D->c->vhi;
+  D->slew_derate = derate;
+  double measured_swing = D->c->vhi - D->c->vlo;
+  double reported_swing = measured_swing/D->slew_derate;
+  D->slew_factor = reported_swing;
+}
+
+static double *
+delay_work_get_residues(delay_work *D,int term_index)
+{
+  return D->resi[term_index];
+}
+
+//////////////////////////////////////////////////////////////
+//
+// calculate_poles_res
+//
+
+void arnoldi1::calculate_poles_res(delay_work *D,
+                                   double rdrive)
+{
+  if (n > D->nmax) delay_work_alloc(D,n);
+  double *p = D->poles;
+  double **v = D->v;
+  double **w = D->w;
+  double *aa = D->aa;
+  double **resi = D->resi;
+  int h,j,k;
+  double sum, dsave;
+
+  dsave = d[0];
+  d[0] += rdrive*ctot;
+  if (!tridiagEV(order,d,e,p,v))
+    criticalError(204, "arnoldi delay calc failed.");
+  d[0] = dsave;
+
+  for (h=0;h<order;h++) {
+    p[h] = std::max(p[h], 1e-14); // .01ps floor
+    p[h] = 1.0/p[h];
+  }
+
+  for (h=0;h<order;h++) {
+    for (k=0;k<n;k++) {
+      sum = 0.0;
+      for (j=0;j<order;j++)
+        sum += v[h][j]*U[j][k];
+      w[h][k] = sum;
+    }
+    aa[h] = sqc*v[h][0];
+  }
+
+  for (j=0;j<n;j++) {
+    for (h=0;h<order;h++)
+      resi[j][h] = aa[h]*w[h][j];
+  }
+}
+
+////////////////////////////////////////////////////////////////
+
+//
+// tridiag.cpp
+//
+
+//
+//  tridiagonal eigenvalues and eigenvectors
+//   assuming all eigenvalues are positive
+//
+//  tridiagEV(n, din, ein, d, v)
+//   din[0]..din[n-1]  diagonal elements (input)
+//   ein[0]..ein[n-2]  off-diagonal elements (input)
+//   d[0],..d[n-1] the eigenvalues (output)
+//   v[0],..v[n-1] the eigenvectors
+//    M*v[j] = p[j]*v[j]
+//
+//   (M*v[j])[0] = d[0]*v[j][0]+e[0]*v[j][1]
+//   (M*v[j])[k] = d[k]*v[j][k]+e[k-1]*v[j][k-1]+e[k]*v[j][k+1]  0<k<n-1
+//   (M*v[j])[n-1] = d[n-1]*v[j][n-1]+e[n-2]*v[j][n-2]
+//
+static bool
+tridiagEV(int n,
+          const double *din,
+          const double *ein,
+          double *d,
+          double **v)
+{
+  int j,k;
+  for (j=0;j<n;j++) for (k=0;k<n;k++) v[j][k]=0.0;
+  for (j=0;j<n;j++) v[j][j] = 1.0;
+
+  int m,h,iter,i;
+  double s,r,p,g,f,c,b;
+  double e[32];
+  if (n>32)
+    return false;
+
+  for (i=0;i<n;i++) d[i] = din[i];
+
+  for (i=0;i<n-1;i++) e[i+1] = ein[i];
+  e[0] = 0.0;
+  for (h=n-1;h>=1;h--) {
+    iter = 0;
+    while (std::abs(e[h])>1e-18) { // 1e-6ps
+      m=0;
+      if (m != h) {
+        if (iter++ == 20)
+          return false;
+        g = (d[h-1]-d[h])/(2.0*e[h]);
+        r = sqrt(1.0+g*g);  // watch overflow
+        g = d[m]-d[h]+e[h]/(g + (g<0?-r:r));
+        s = c = 1.0;
+        p = 0.0;
+        for (i=m+1;i<=h;i++) {
+          f = s*e[i];
+          b = c*e[i];
+          e[i-1] = r = sqrt(f*f+g*g);  // watch
+          if (r == 0.0) {
+            d[i-1] -= p;
+            e[m] = 0.0;
+            break;
+          }
+          s = f/r;
+          c = g/r;
+          g = d[i-1]-p;
+          r = (d[i]-g)*s+2.0*c*b;
+          d[i-1] = g + (p=s*r);
+          g = c*r-b;
+          for (k=0;k<n;k++) {
+            f = v[i-1][k];
+            v[i-1][k] = s*v[i][k]+c*f;
+            v[i][k] = c*v[i][k]-s*f;
+          }
+        }
+        if (r == 0.0 && i <= h) continue;
+        d[h] -= p;
+        e[h] = g;
+        e[m] = 0.0;
+      }
+    }
+  }
+
+  for (i=0;i<n-1;i++) {
+    k = i;
+    p = d[k];
+    for (j=i+1;j<n;j++)
+      if (d[j] > p) { k=j; p=d[k]; }
+    if (k != i) {
+      d[k] = d[i];
+      d[i] = p;
+      for (j=0;j<n;j++) {
+        p = v[i][j];
+        v[i][j] = v[k][j];
+        v[k][j] = p;
+      }
+    }
+  }
+
+  return true;
+}
+
+////////////////////////////////////////////////////////////////
+
+// prsolve.cpp
+
+// get a waveform point
+static void
+pr_get_v(double t,
+         double s,
+         int order,
+         const double *p,
+         const double *rr,
+         double *va)
+{
+  *va = 0.0;
+  int h;
+  for (h=0;h<order;h++) {
+    double pt = p[h]*t;
+    double ps = p[h]*s;
+    double f;
+    if (t<s) {
+      f = 1.0-t/s + (1.0-exp(-pt))/ps;
+    } else {
+      f = exp(ps-pt)*(1.0-exp(-ps))/ps;
+    }
+    *va += rr[h]*f;
+  }
+}
+
+static void
+get_dv(double t,
+       double s,
+       int order,
+       const double *p,
+       const double *rr,
+       double *va,
+       double *dva)
+{
+  *va = 0.0;
+  *dva = 0.0;
+  int h;
+  for (h=0;h<order;h++) {
+    double p1 = p[h];
+    double pt = p1*t;
+    double ps = p1*s;
+    double f,df,xtmp;
+    if (t<s) {
+      xtmp = (1.0-exp(-pt))/ps;
+      f = 1.0-t/s + xtmp;
+      df = -p1*xtmp;
+    } else {
+      f = exp(ps-pt)*(1.0-exp(-ps))/ps;
+      df = -p1*f;
+    }
+    *va += rr[h]*f;
+    *dva += rr[h]*df;
+  }
+}
+
+static double
+solve_t_bracketed(double s,
+                  int order,
+                  const double *p,
+                  const double *rr,
+                  double val,
+                  double x1,
+                  double x2,
+                  double v1,
+                  double v2)
+{
+  int j;
+  double df,dx,dxold,f,f2,f1;
+  double temp,xh,x_lo,rts;
+  double xacc = .001e-12; // .001ps
+  f1 = v1-val;
+  f2 = v2-val;
+  if (f1==0.0) return x1;
+  if (f2==0.0) return x2;
+  rts = (f1*x2-f2*x1)/(f1-f2);
+  if (f1<f2) {
+    x_lo = x1;
+    xh = x2;
+    if (0.0<f1) return x1;
+    if (f2<0.0) return x2;
+  } else {
+    x_lo = x2;
+    xh = x1;
+    if (0.0<f2) return x2;
+    if (f1<0.0) return x1;
+  }
+  dxold = std::abs(x2-x1);
+  dx = dxold;
+  get_dv(rts,s,order,p,rr,&f,&df);
+  f -= val;
+  double flast = 0.0;
+  for (j=1;j<10;j++) {
+    if ((((rts-xh)*df-f)*((rts-x_lo)*df-f) >= 0.0)
+        || (std::abs(2.0*f) > std::abs(dxold*df))) {
+      dxold = dx;
+      dx = 0.5*(xh-x_lo);
+      if (flast*f >0.0) {
+        // 2 successive bisections in same direction,
+        // accelerate
+        if (f<0.0) dx = 0.9348*(xh-x_lo);
+        else dx = 0.0625*(xh-x_lo);
+      }
+      flast = f;
+      rts = x_lo+dx;
+      if (x_lo == rts) {
+        return rts;
+      }
+    } else {
+      dxold = dx;
+      dx = f/df;
+      flast = 0.0;
+      temp = rts;
+      rts -= dx;
+      if (temp == rts) {
+        return rts;
+      }
+    }
+    if (std::abs(dx) < xacc) {
+      return rts;
+    }
+    get_dv(rts,s,order,p,rr,&f,&df); f -= val;
+    if (f<0.0)
+      x_lo = rts;
+    else
+      xh = rts;
+  }
+  if (std::abs(f)<1e-6) // 1uV
+    return rts;
+  return 0.5*(x_lo+xh);
+}
+
+void
+ArnoldiDelayCalc::pr_solve1(double s,
+                            int order,
+                            double *p,
+                            double *rr,
+                            double v1,
+                            double *t1)
+{
+  double tmin = 0.0,tmax = 0.0,vmin = 0.0,vmax = 0.0;
+  int h, h0 = 0;
+  while (order>1
+         && rr[order-1]<1e-8 // 1e-8V
+         && rr[order-1]>-1e-8)
+    order--;
+  if (rr[0]<0.5) {
+    for (h=1;h<order;h++) if (rr[h]>0.3 && rr[h]>rr[0]) { h0 = h; break; }
+  }
+  double p0 = p[h0];
+  double ps,vs,ta,va;
+  vs = 0.0;
+  for (h=0;h<order;h++) {
+    ps = p[h]*s;
+    vs += rr[h]*(1-exp(-ps))/ps;
+  }
+  if (vs<v1) {
+    // s dominates
+    ta = 0.5*(1+v1)*s;
+    pr_get_v(ta,s,order,p,rr,&va);
+    if (va<v1) {
+      tmax = ta; vmax = va;
+      ta = v1*s;
+      pr_get_v(ta,s,order,p,rr,&va);
+      if (va<v1) {
+        // ignoring a typical error at drive node, that comes
+        // from slight inaccuracies in rr
+        if (!(rr[order-1]>1.0 && p[order-1]>500.0 && va>v1-0.002))
+          debugPrint(debug_, "arnoldi", 1, "err, pr_solve1, va<v1");
+      }
+      tmin = ta; vmin = va;
+    } else {
+      tmin = ta; vmin = va;
+      ta = s;
+      pr_get_v(ta,s,order,p,rr,&va);
+      while (va>v1) {
+        tmin = ta; vmin = va;
+        ta *= 2.0;
+        pr_get_v(ta,s,order,p,rr,&va);
+      }
+      if (va>v1)
+        debugPrint(debug_, "arnoldi", 1, "err, pr_solve1, va>v1");
+      tmax = ta; vmax = va;
+    }
+  } else {
+    // s is irrelevant
+    ta = s; va = vs;
+    while (va >= v1) {
+      tmin = ta;
+      vmin = va;
+      ta += 1.0/p0;
+      pr_get_v(ta,s,order,p,rr,&va);
+    }
+    tmax = ta; vmax = va;
+  }
+  *t1 = solve_t_bracketed(s,order,p,rr,v1,tmin,tmax,vmin,vmax);
+}
+
+void
+ArnoldiDelayCalc::pr_solve3(double s,
+                            int order,
+                            double *p,
+                            double *rr,
+                            double vhi,
+                            double *thi,
+                            double vmid,
+                            double *tmid,
+                            double vlo,
+                            double *tlo)
+{
+  // falling, thi<tmin<tlo
+  double tmin2,tmax2,vmin2,vmax2;
+  double tmin5,tmax5,vmin5,vmax5;
+  double tmin8,tmax8,vmin8,vmax8;
+  int h, h0 = 0;
+  while (order>1
+         && rr[order-1]<1e-8 // 1e-8V
+         && rr[order-1]>-1e-8)
+    order--;
+  if (rr[0]<0.5) {
+    for (h=1;h<order;h++) if (rr[h]>0.3 && rr[h]>rr[0]) { h0 = h; break; }
+  }
+  double p0 = p[h0];
+  p0 = std::min(p0, 10e+9);  // 1/10ns cap
+  double ps,vs,ta,va;
+  vs = 0.0;
+  for (h=0;h<order;h++) {
+    ps = p[h]*s;
+    vs += rr[h]*(1-exp(-ps))/ps;
+  }
+  if (vs<vlo) {
+    // s dominates
+    tmax8 = s; vmax8 = vs;
+    ta = vhi*s;
+    pr_get_v(ta,s,order,p,rr,&va);
+    if (va < vmid) {
+      tmax2 = tmax5 = tmin8 = ta;
+      vmax2 = vmax5 = vmin8 = va;
+      ta = vmid*s;
+      pr_get_v(ta,s,order,p,rr,&va);
+      if (va>vhi) {
+        tmin2 = tmin5 = ta;
+        vmin2 = vmin5 = va;
+        tmin8 = ta; vmin8 = va;
+        if (va<vmid) {
+          tmax5 = ta; vmax5 = va;
+        } else {
+          tmin5 = ta; vmin5 = va;
+        }
+      } else {
+        tmax2 = tmin5 = ta;
+        vmax2 = vmin5 = va;
+        ta = vlo*s;
+        pr_get_v(ta,s,order,p,rr,&va);
+        tmin2 = ta; vmin2 = va;
+      }
+    } else {
+      // rare, s dominates but t=vhi*s is still above vmid
+      tmin5 = tmin8 = ta;
+      vmin5 = vmin8 = va;
+      tmax5 = tmax8;
+      vmax5 = vmax8;
+      if (va > vhi) {
+        tmin2 = tmin5;
+        vmin2 = vmin5;
+        tmax2 = tmax5;
+        vmax2 = tmax5;
+      } else {
+        tmax2 = tmin5;
+        vmax2 = vmin5;
+        ta = vlo*s;
+        pr_get_v(ta,s,order,p,rr,&va);
+        tmin2 = ta; vmin2 = va;
+      }
+    }
+  } else if (vs<vmid) {
+    // not far from s
+    tmax2 = tmax5 = tmin8 = s;
+    vmax2 = vmax5 = vmin8 = vs;
+    ta = s + 1.6/p0;
+    pr_get_v(ta,s,order,p,rr,&va);
+    while (va>vlo) {
+      tmin8 = ta; vmin8 = va;
+      ta += 1.0/p0;
+      pr_get_v(ta,s,order,p,rr,&va);
+    }
+    tmax8 = ta; vmax8 = va;
+    ta = vmid*s;
+    pr_get_v(ta,s,order,p,rr,&va);
+    tmin5 = ta; vmin5 = va;
+    if (va>vhi) {
+      tmin2 = ta; vmin2 = va;
+    } else {
+      tmax2 = ta; vmax2 = va;
+      ta = vlo*s;
+      pr_get_v(ta,s,order,p,rr,&va);
+      tmin2 = ta; vmin2 = va;
+    }
+  } else if (vs<vhi) {
+    tmax2 = tmin5 = tmin8 = s;
+    vmax2 = vmin5 = vmin8 = vs;
+    ta = vlo*s;
+    pr_get_v(ta,s,order,p,rr,&va);
+    tmin2 = ta; vmin2 = va;
+    ta = s + 0.7/p0;
+    pr_get_v(ta,s,order,p,rr,&va);
+    while (va>vmid) {
+      tmin5 = ta;
+      tmin8 = ta;
+      vmin5 = va;
+      ta += 0.7/p0;
+      pr_get_v(ta,s,order,p,rr,&va);
+    }
+    tmax5 = ta; vmax5 = va;
+    if (va < vlo) {
+      tmax8 = ta; vmax8 = va;
+    } else {
+      tmin8 = ta; vmin8 = va;
+      ta += 1.0/p0;
+      pr_get_v(ta,s,order,p,rr,&va);
+      while (va>vlo) {
+        tmin8 = ta; vmin8 = va;
+        ta += 1.0/p0;
+        pr_get_v(ta,s,order,p,rr,&va);
+      }
+      tmax8 = ta; vmax8 = va;
+    }
+  } else {
+    // s is irrelevant
+    ta = s; va = vs;
+    tmin2 = tmin5 = tmin8 = ta;
+    vmin2 = vmin5 = vmin8 = va;
+    while (va > vhi) {
+      tmin2 = tmin5 = tmin8 = ta;
+      vmin2 = vmin5 = vmin8 = va;
+      ta += 1.0/p0;
+      pr_get_v(ta,s,order,p,rr,&va);
+    }
+    tmax2 = ta; vmax2 = va;
+    while (va > vmid) {
+      tmin5 = tmin8 = ta;
+      vmin5 = vmin8 = va;
+      ta += 1.0/p0;
+      pr_get_v(ta,s,order,p,rr,&va);
+    }
+    tmax5 = ta; vmax5 = va;
+    while (va > vlo) {
+      tmin8 = ta;
+      vmin8 = va;
+      ta += 1.0/p0;
+      pr_get_v(ta,s,order,p,rr,&va);
+    }
+    tmax8 = ta; vmax8 = va;
+  }
+
+  *thi = solve_t_bracketed(s,order,p,rr,vhi,tmin2,tmax2,vmin2,vmax2);
+  *tmid= solve_t_bracketed(s,order,p,rr,vmid,tmin5,tmax5,vmin5,vmax5);
+  *tlo= solve_t_bracketed(s,order,p,rr,vlo,tmin8,tmax8,vmin8,vmax8);
+}
+
+static double
+calc_integ(double p,double s,double t)
+{
+  // integral of f(t)-vin(t)
+  double ps = p*s;
+  double pt = p*t;
+  double y,ept,eps;
+  if (t<=s) {
+    ept = (pt>40.0)?0.0:exp(-pt);
+    y = ept-1.0+pt;
+  } else {
+    pt = pt-ps;
+    ept = (pt>40.0)?0.0:exp(-pt);
+    eps = (ps>40.0)?0.0:exp(-ps);
+    y = ps - (1.0-eps)*ept;
+  }
+  y /= ps*p;
+  return y;
+}
+
+
+double
+ArnoldiDelayCalc::pr_ceff(double s,
+                          double rdrive,
+                          int order,
+                          double *p,
+                          double *rr,
+                          double ceff_time)
+{
+  double integi = 0.0;
+  double ceff, v0;
+  int j;
+  for (j=0;j<order;j++) {
+    integi += rr[j]*calc_integ(p[j],s,ceff_time);
+  }
+  integi /= rdrive;
+  pr_get_v(ceff_time,s,order,p,rr,&v0);
+  ceff = integi/(1.0-v0);
+  return ceff;
+}
+
+//////////////////////////////////////////////////////////////////
+
+static double
+ra_hinv(double y,
+        Debug *debug)
+{
+  double x;
+  if (y<1.0) {
+    x = sqrt(2*y)+0.4*y;
+    if (y<1e-4) return x;
+  } else {
+    x = y+1.0;
+  }
+  double ex = exp(-x);
+  double f = x+ex-1.0-y;
+  x += f/(ex-1.0);
+  ex = exp(-x);
+  f =  x+ex-1.0-y;
+  x += f/(ex-1.0);
+  ex = exp(-x);
+  f =  x+ex-1.0-y;
+  x += f/(ex-1.0);
+   ex = exp(-x);
+   f =  x+ex-1.0-y;
+   if (f<-1e-8 || f>1e-8)
+     debugPrint(debug, "arnoldi", 1, "y f {:g} {:g}", y, f);
+  return x;
+}
+
+double
+ArnoldiDelayCalc::ra_solve_for_t(double p,
+                                 double s,
+                                 double v)
+{
+  double t;
+  double ps = p*s;
+  if (ps>30.0) {
+    t = (1.0+ps*(1.0-v)) / p;
+    return t;
+  }
+  double eps = exp(ps);
+  if ((1-ps*v)*eps >= 1.0) {
+    t =  log((eps-1.0)/(ps*v)) / p;
+  } else {
+    t =  ra_hinv((1-v)*ps, debug_)/p;
+  }
+  return t;
+}
+
+void
+ArnoldiDelayCalc::ra_solve_for_pt(double ps,
+                                  double v,
+                                  double *pt,
+                                  double *d)
+{
+  if (ps>30.0) {
+    *pt = 1.0+ps*(1.0-v);
+    *d = 1.0-v;
+    return;
+  }
+  double eps = exp(ps);
+  if ((1-ps*v)*eps >= 1.0) {
+    *pt =  log((eps-1.0)/(ps*v));
+    *d = eps/(eps-1.0) - 1.0/ps;
+  } else {
+    *pt =  ra_hinv((1-v)*ps, debug_);
+    *d = (1.0-v)/(*pt - (1-v)*ps);
+  }
+}
+
+void
+ArnoldiDelayCalc::ra_calc_c(double vlo,
+                            double vhi,
+                            double *c_smin,
+                            double *c_x1,
+                            double *c_y1)
+{
+  double a = log(1.0/vhi);
+  *c_smin =  a + ra_hinv((1.0-vhi)/vhi - a, debug_);
+  double b = log(1.0/vlo);
+  double c_s1 =  b + ra_hinv((1.0-vlo)/vlo - b, debug_);
+  double a1 = (exp(c_s1)-1.0)/c_s1;
+  double den = log(a1/vlo) - ra_hinv((1.0-vhi)*c_s1, debug_);
+  *c_x1 = (vhi-vlo)/den;
+  *c_y1 = c_s1*(*c_x1);
+}
+
+////////////////////////////////////////////////////////////////
+
+//
+// ceff.cpp
+//
+
+void
+ArnoldiDelayCalc::ra_solve_for_s(delay_work *D,
+                                 double p,
+                                 double tlohi,
+                                 double &s)
+{
+  delay_c *c = D->c;
+  double vhi = c->vhi;
+  double vlo = c->vlo;
+  // s is 0-100
+  // solve f(x,y)=0 with f = x*(ptlo(y/x)-pthi(y/x))-(vhi-vlo)
+  // (x=0,y=1)
+  // (x=x1,y=y1)  c->x1,y1
+  // (x=x2,y=y2)  x2=(vhi-vlo)/log(vhi/vlo)  y2=(c->smin)*x2
+  double x1 = c->x1;
+  double y1 = c->y1;
+  double x2 = (vhi-vlo)/c->vlg;
+  double y2 = (c->smin)*x2;
+  double ptlo,dlo;
+  double pthi,dhi;
+  double f,df,x,y;
+  x = c->vlg/(p*tlohi);
+
+  if (x <= x1) {
+    y = y1 - 0.5*(x-x1);
+    y = std::min(y, 1.0);
+  } else {
+    y =  y1 - (x-x1)*(0.5 + 8*(x-x1));
+    y = std::max(y, y2);
+  }
+  (void)y;
+
+  ra_solve_for_pt(p*s,vlo,&ptlo,&dlo);
+  ra_solve_for_pt(p*s,vhi,&pthi,&dhi);
+  f = (ptlo-pthi)/p - tlohi;
+  df = dlo-dhi;
+  s = s - f/df;
+  if (std::abs(f)<.001e-12) return;  // .001ps
+
+  ra_solve_for_pt(p*s,vlo,&ptlo,&dlo);
+  ra_solve_for_pt(p*s,vhi,&pthi,&dhi);
+  f = (ptlo-pthi)/p - tlohi;
+  df = dlo-dhi;
+  s = s - f/df;
+  if (std::abs(f)<.001e-12) return;  // .001ps
+
+  ra_solve_for_pt(p*s,vlo,&ptlo,&dlo);
+  ra_solve_for_pt(p*s,vhi,&pthi,&dhi);
+  f = (ptlo-pthi)/p - tlohi;
+  df = dlo-dhi;
+  s = s - f/df;
+  if (std::abs(f)<.001e-12) return;  // .001ps
+
+  ra_solve_for_pt(p*s,vlo,&ptlo,&dlo);
+  ra_solve_for_pt(p*s,vhi,&pthi,&dhi);
+  f = (ptlo-pthi)/p - tlohi;
+  df = dlo-dhi;
+  s = s - f/df;
+  if (std::abs(f)<.001e-12) return;  // .001ps
+
+  ra_solve_for_pt(p*s,vlo,&ptlo,&dlo);
+  ra_solve_for_pt(p*s,vhi,&pthi,&dhi);
+  f = (ptlo-pthi)/p - tlohi;
+  df = dlo-dhi;
+  s = s - f/df;
+
+  if (std::abs(f)>.5e-12) // .5ps
+    debugPrint(debug_, "arnoldi", 1, "ra_solve_for_s p {:g} tlohi {} err {}",
+               p,
+               units_->timeUnit()->asString(tlohi),
+               units_->timeUnit()->asString(f));
+}
+
+/////////////////////////////////////////////////////////////////////
+// method 0:
+// r = a match to slew to (ctot, limited by cmin,cmax)
+// if r>rdelay, lower r
+// Now at any ceff (limited)
+//   If slew(r,0,ceff) is too big
+//     s = s_start(r,ceff), not smaller than Smin
+//     accept the pessimistic output slew
+//   Else
+//     solve for s
+
+// Rough translation of ra_get_r(sy_table) used by ar1_ceff_delay.
+double
+ArnoldiDelayCalc::ra_get_r(delay_work *D,
+                           timing_table *tab,
+                           double rdelay,
+                           double ctot)
+{
+  // find the maximum r that allows a solution for s of
+  // (s,r,ctot)-> output_slew
+  // If this maximum is greater than rdelay, use rdelay.
+  delay_c *c = D->c;
+  double slew_derate = c->slew_derate;
+  double c_log = c->vlg;
+  float  c1;
+  double tlohi,r;
+  c1 = ctot;
+  float d1, s1;
+  tab->table->gateDelay(tab->pvt, tab->in_slew, c1, d1, s1);
+  tlohi = slew_derate*delayAsFloat(s1);
+  r = tlohi/(c_log*c1);
+  if (rdelay>0.0 && r > rdelay)
+    r = rdelay;
+  return r;
+}
+
+double
+ArnoldiDelayCalc::ra_get_s(delay_work *D,
+                           timing_table *tab,
+                           double r,
+                           double c)
+{
+  delay_c *con = D->c;
+  double slew_derate = con->slew_derate;
+  double c_log = con->vlg;
+  double c_smin = con->smin;
+  double tlohi,smin,s;
+  float d1, s1;
+  tab->table->gateDelay(tab->pvt, tab->in_slew, c, d1, s1);
+  tlohi = slew_derate*delayAsFloat(s1);
+  smin = r*c*c_smin; // c_smin = ra_hinv((1-vhi)/vhi-log(vhi)) + log(vhi);
+  if (c_log*r*c >= tlohi) {
+    s = smin;
+  } else {
+    s = smin+0.3*tlohi;
+    ra_solve_for_s(D,1.0/(r*c),tlohi,s);
+  }
+  return s;
+}
+
+/////////////////////////////////////////////////////////////////////
+// method 1:
+// determine the drive resistance from change in delay versus ctot
+// find the maximum r that allows a solution for s of
+// (s,r,ctot)-> output_slew
+// If this maximum is greater than rdelay, use rdelay.
+// calculate s,r,mod -> t50_srmod,
+// then   t50_srmod+t50_sy-t50_sr
+
+double
+ArnoldiDelayCalc::ra_rdelay_1(timing_table *tab,
+                              double ctot)
+{
+  // determine the drive resistance from change in delay versus ctot
+  float c1 = ctot;
+  float c2 = 0.5*c1;
+  if (c1==c2)
+    return 0.0;
+  float d1, d2, s1, s2;
+  tab->table->gateDelay(tab->pvt, tab->in_slew, c1, d1, s1);
+  tab->table->gateDelay(tab->pvt, tab->in_slew, c2, d2, s2);
+  double dt50 = delayAsFloat(d1)-delayAsFloat(d2);
+  if (dt50 <= 0.0)
+    return 0.0;
+  double rdelay = dt50/(c1-c2);
+  return rdelay;
+}
+
+void
+ArnoldiDelayCalc::ar1_ceff_delay(delay_work *D,
+                                 timing_table *tab,
+                                 arnoldi1 *mod,
+                                 double *delays,
+                                 double *slews)
+{
+  delay_c *con = D->c;
+  double slew_derate = con->slew_derate;
+  double vhi = con->vhi;
+  double vlo = con->vlo;
+  double ctot = mod->ctot;
+  double ceff,tlohi,t50_sy,r,s,t50_sr,rdelay;
+  float df, sf;
+
+  debugPrint(debug_, "arnoldi", 1, "ctot={}",
+             units_->capacitanceUnit()->asString(ctot));
+
+  rdelay = ra_rdelay_1(tab,ctot);
+  if (rdelay == 0.0) {
+    rdelay = 1e+3; // 1kohm
+  }
+  r = ra_get_r(D,tab,rdelay,ctot);
+  if (! (r>0.0
+         && r<100e+3)) // 100khom
+    rdelay = 1e+3; // 1kohm
+
+  bool bad = (r<rdelay);
+  s = ra_get_s(D,tab,r,ctot);
+  if (! (s>0.0
+         && s<100e-9)) // 100ns
+    s = 0.5e-9; // .5ns
+
+  if (debug_->check("arnoldi", 1)) {
+    double p = 1.0/(r*ctot);
+    double thix,tlox;
+    debugPrint(debug_, "arnoldi", 1, "at r={} s={}",
+               units_->resistanceUnit()->asString(r),
+               units_->timeUnit()->asString(s));
+    thix = ra_solve_for_t(p,s,vhi);
+    tlox = ra_solve_for_t(p,s,vlo);
+    tab->table->gateDelay(tab->pvt,tab->in_slew, ctot, df, sf);
+    debugPrint(debug_, "arnoldi", 1, "table slew (in_slew {} ctot {}) = {}",
+               units_->timeUnit()->asString(tab->in_slew),
+               units_->capacitanceUnit()->asString(ctot),
+               delayAsString(sf, this));
+    tlohi = slew_derate*delayAsFloat(sf);
+    debugPrint(debug_, "arnoldi", 1, "tlohi {} {}",
+               units_->timeUnit()->asString(tlohi),
+               units_->timeUnit()->asString(tlox-thix));
+  }
+  ceff = ctot;
+
+  // calculate s,r,mod -> t50_srmod,
+  // then   t50_srmod+t50_sy-t50_sr
+
+  mod->calculate_poles_res(D,r);
+  double *p = D->poles;
+  double *rr = delay_work_get_residues(D,0);
+  double thi,tlo,t50_srmod;
+  pr_solve1(s,mod->order,p,rr,0.5,&t50_srmod);
+
+  int ceff_it,j;
+  double ceff_time=0.0;
+
+  if (!bad) {
+    for (ceff_it=0;ceff_it<3;ceff_it++) {
+
+      // calculate ceff
+      ceff_time = s;
+      ceff = pr_ceff(s,r,mod->order,p,rr,ceff_time);
+
+      if ((ceff-1e-20) < 0.0) {  // 1e-8pf
+        debugPrint(debug_, "arnoldi", 1,
+                    "Invalid effective capacitance, using total capacitance");
+        ceff = ctot;
+      }
+
+      // new mvs at ceff
+      s = ra_get_s(D,tab,r,ceff);
+      debugPrint(debug_, "arnoldi", 1, "new mvs  s = {}",
+                 units_->timeUnit()->asString(s));
+    }
+  }
+  debugPrint(debug_, "arnoldi", 1, "r {} s {} ceff_time {} ceff {}",
+             units_->resistanceUnit()->asString(r),
+             units_->timeUnit()->asString(s),
+             units_->timeUnit()->asString(ceff_time),
+             units_->capacitanceUnit()->asString(ceff));
+
+  tab->table->gateDelay(tab->pvt, tab->in_slew, ceff, df, sf);
+  t50_sy = delayAsFloat(df);
+  t50_sr = ra_solve_for_t(1.0/(r*ceff),s,0.5);
+  for (j=0;j<mod->n;j++) {
+    rr = delay_work_get_residues(D,j);
+    pr_solve3(s,mod->order,p,rr,vhi,&thi,0.5,&t50_srmod,vlo,&tlo);
+    delays[j] = t50_srmod + t50_sy - t50_sr;
+    slews[j] = (tlo-thi)/slew_derate;
+  }
+}
+
+// NOLINTEND(modernize-avoid-c-style-cast)
+} // namespace sta