Add batch 2 (lnis-uofu_OpenFPGA, splinedrive_kianRiscV, Wren6991_Hazard3, odriverobotics_ODriveHardware, mntmn_amiga2000-gfxcard)

.gitattributes

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Wren6991_Hazard3/.gitignore

@@ -0,0 +1,2 @@
+.DS_Store
+*.todo

Wren6991_Hazard3/.gitmodules

@@ -0,0 +1,18 @@
+[submodule "test/sim/riscv-compliance/riscv-arch-test"]
+	path = test/sim/riscv-compliance/riscv-arch-test
+	url = https://github.com/wren6991/riscv-arch-test.git
+[submodule "scripts"]
+	path = scripts
+	url = https://github.com/Wren6991/fpgascripts
+[submodule "test/formal/riscv-formal"]
+	path = test/formal/riscv-formal/riscv-formal
+	url = https://github.com/Wren6991/riscv-formal.git
+[submodule "example_soc/libfpga"]
+	path = example_soc/libfpga
+	url = https://github.com/Wren6991/libfpga.git
+[submodule "test/sim/riscv-tests/riscv-tests"]
+	path = test/sim/riscv-tests/riscv-tests
+	url = https://github.com/Wren6991/riscv-tests.git
+[submodule "test/sim/embench/embench-iot"]
+	path = test/sim/embench/embench-iot
+	url = https://github.com/Wren6991/embench-iot.git

Wren6991_Hazard3/.vscode/settings.json

@@ -0,0 +1,24 @@
+{
+    "rtlDebugger.command": [
+        "${workspaceFolder}/test/sim/tb_cxxrtl/tb",
+        "--bin",
+        "${workspaceFolder}/test/sim/hellow/tmp/hellow.bin",
+        "--debug"
+    ],
+    "rtlDebugger.variableOptions": {
+        "cpu i_haddr": {
+            "radix": 16
+        }
+    },
+    "rtlDebugger.watchList": [
+        {
+            "id": "cpu clk"
+        },
+        {
+            "id": "cpu i_haddr"
+        },
+        {
+            "id": "d_haddr"
+        }
+    ]
+}

Wren6991_Hazard3/Contributing.md

@@ -0,0 +1,103 @@
+# Contributing
+
+There are two main ways you can contribute to Hazard3: _pull requests_ and _issues_.
+
+## Pull Requests
+
+I am grateful for any of the following pull requests:
+
+* New documentation, or fixes for existing documentation
+* New tests, or syncing new versions of upstream tests
+	* For upstream tests with downstream patches, please first raise a PR on the submodule for those upstream tests (just merging down is fine)
+* Improvements and expansion to the example SoC
+* Bug fixes for the example SoC
+* Porting the example SoC to new FPGA platforms
+	* Preferably ones supported by Yosys + nextpnr, with an inexpensive commercially-available development board that I can order for testing
+* Improvements to automation and scripting
+* Improvements to RTL in project dependencies like `example_soc/libfpga/`
+* General project maintenance (such as fixing accidental use of SSH URLs for submodules)
+
+Please do not raise pull requests for the following:
+
+* Changes to RTL sources in the top-level `hdl/` directory
+* Cosmetic changes (except for comment-only changes)
+
+Raise pull requests against the [develop](https://github.com/Wren6991/Hazard3/tree/develop) branch. Do not raise pull requests directly against [stable](https://github.com/Wren6991/Hazard3/tree/stable).
+
+### Changes to Core RTL
+
+I do not merge pull requests which modify hardware sources in the `hdl/` directory. I close these pull requests without reading the patch.
+
+The contents of the `hdl/` directory have a single author. I will not expose people taping out Hazard3 to the possibility of your employer chasing you for your contribution by harassing them legally. A contribution agreement does not solve this, because you may sign it without the legal capability to do so, and **what is taped out cannot be taped back in.**
+
+If you are reading this as a software engineer, please understand that the ASIC industry is more hostile to open-source projects than the software industry is, and I am trying my hardest to build a core that other people can safely use.
+
+(I am not trying to be obstructive; if a community fork of Hazard3 gets traction I am happy to contribute and help out with issues and questions. However, the core RTL in this repository will remain single-author.)
+
+Do not raise issues with suggested code changes to core RTL. This is the same thing as a pull request, and I will close the issue without reading the patch. Please clearly identify the issue and I will fix it.
+
+## Issues
+
+There are three main categories of issues which are helpful to the project: _bug reports_, _feature requests_ and _questions_.
+
+### Bug Reports
+
+If you find a bug in the Hazard3 repository, please report it. This includes:
+
+1. A functional bug in Hazard3 such as mis-execution, or ISA non-compliance
+2. A compatibility issue with your tools
+	* Please do not raise cosmetic lint issues: the intersection of clean Verilog across all lint tools is the empty set. Hazard3 is lint-clean with Verilator lint.
+	* A lint issue relating to simulation/synthesis mismatch is important though, and falls under point **1** above.
+3. An incorrect or incomplete statement in documentation
+4. A test which fails when it should pass, or vice versa
+
+#### Reproducibility
+
+Before I fix a bug I must reproduce it on my own machine. I cannot fix issues on faith as this is unlikely to result in a reliable or complete fix. Please include the following in a bug report to ensure I can reproduce the issue:
+
+* A description of expected behaviour
+* A description of actual, observed behaviour (which differs from expected)
+* A description of the platform where you observed the issue
+	* Preferred platforms are the CXXRTL simulator, and the iCEBreaker and ULX3S FPGA SoCs
+	* You can attach a patch for a preferred platform if it is necessary to reproduce the issue
+* All files necessary to reproduce the issue
+	* For software the minimum is an ELF and disassembly file for your binary
+	* Do not strip symbols from ELF files
+	* Please attach source code if possible (but the ELF is more important as I may not be able to reproduce your build exactly)
+* A sequence of bash commands which can be invoked on the above files to reproduce the faulty behaviour
+
+I develop Hazard3 on the latest Ubuntu LTS release (currently 24.04) and testing your reproduction on this platform is much appreciated.
+
+### Feature Requests
+
+I am happy to field feature requests. Please be aware the answer may be "no" for any of the following reasons:
+
+* Future maintenance burden which I feel is excessive
+* Impact on performance or functionality of existing features
+* I don't like the feature, for reasons of aesthetics or toolchain compatibility
+* I don't expect to have time to implement the feature in a reasonable timeframe
+
+Please describe **why** the requested feature is useful. This helps me prioritise the request, and I might realise I also want this feature!
+
+I am overwhelmingly more likely to implement requests for standard RISC-V ISA features than custom ones. As a rule, I don't implement standard RISC-V features that are not at least in the Frozen state. Please also consider the availability of toolchain support and upstream tests.
+
+### Questions
+
+The following questions are relevant to this repository and I am happy to answer them:
+
+* Questions about Hazard3's implementation-defined behaviour in relation to the RISC-V standards
+* Questions about tools used to build the Hazard3 simulator or tests (which are not covered by [Readme.md](Readme.md))
+
+The following questions are not relevant and I am likely to either ignore or close them:
+
+* Questions about Verilog
+	* The IEEE 1364-2005 PDF can be found online
+	* The best way to learn is to just do it ([instructional video](https://www.youtube.com/watch?v=ZXsQAXx_ao0))
+	* Get an FPGA board like an iCEBreaker and get hacking
+	* Yosys and nextpnr are great if you are already familiar with software tooling
+	* Start with blinking an LED, then PWM the LED, then implement UART TX, then UART RX
+* Questions about the RISC-V ISA
+	* Get the latest ISA manual [here](https://github.com/riscv/riscv-isa-manual/releases/latest) (you want the _unprivileged_ manual first -- I find the HTML version more readable these days)
+	* There are some excellent books on the topic. I recommend the RISC-V edition of _Computer Organization and Design_ by Patterson & Hennessy for a gentle introduction to computer architecture as well as the RISC-V ISA.
+* Questions which are not questions, i.e. telling me how clever you are
+	* I have ChatGPT for this purpose

Wren6991_Hazard3/LICENSE

@@ -0,0 +1,201 @@
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Wren6991_Hazard3/Readme.md

@@ -0,0 +1,475 @@
+# Hazard3
+
+Hazard3 is a 3-stage RISC-V processor, implementing the `RV32I` or `RV32E` instruction set and the following optional extensions:
+
+* `M`: integer multiply/divide/modulo
+* `A` : atomic memory operations, with AHB5 global exclusives
+* `C`: compressed instructions
+* `Zicsr`: CSR access
+* `Zilsd`: load/store pair instructions
+* `Zba`: address generation
+* `Zbb`: basic bit manipulation
+* `Zbc`: carry-less multiplication
+* `Zbs`: single-bit manipulation
+* `Zbkb`: basic bit manipulation for scalar cryptography
+* `Zbkx`: crossbar permutation instructions
+* `Zcb`: basic additional compressed instructions
+* `Zclsd`: compressed load/store pair instructions
+* `Zcmp`: push/pop instructions
+* Debug, Machine and User privilege/execution modes
+* Privileged instructions `ecall`, `ebreak`, `mret` and `wfi`
+* Physical memory protection (PMP) with up to 16 regions (configurable support for NAPOT and/or TOR matching)
+* External debug support (JTAG or APB)
+* Instruction address trigger unit (hardware breakpoints)
+
+Download the Hazard3 reference manual [here (PDF)](https://github.com/Wren6991/Hazard3/releases/download/v1.1/hazard3.pdf). You can also [read the documentation online](https://wren.wtf/hazard3/doc).
+
+This repository contains the source for the Hazard3 core and its associated debug components. The [example SoC integration](example_soc/soc/example_soc.v) shows how you can assemble these components to create a minimal system with a JTAG-enabled RISC-V processor, some RAM, a serial port and a platform timer.
+
+Please read [Contributing.md](Contributing.md) before raising an issue or pull request.
+
+# Cloning This Repository
+
+For the purpose of using Hazard3 in your design, this repository is self-contained. However, you need the submodules for simulation scripts, tests and example SoC components. In the latter case you should do a recursive clone:
+
+```bash
+git clone --recursive https://github.com/Wren6991/Hazard3.git hazard3
+```
+
+To initialise submodules in an already-cloned repository:
+
+```bash
+git submodule update --init --recursive
+```
+
+The default branch for clones is [stable](https://github.com/Wren6991/Hazard3/tree/stable). I strongly recommend this branch for ASIC tapeouts. The head of stable is always the latest non-development release under [releases](https://github.com/Wren6991/Hazard3/releases).
+
+See the [develop](https://github.com/Wren6991/Hazard3/tree/develop) branch to try the latest features and optimisations.
+
+# Running Hello World
+
+These instructions walk through:
+
+* Setting up the tools for building the Hazard3 simulator from Verilog source
+* Setting up the tools for building RISC-V binaries to run on the simulator
+* Building a "Hello, world!" binary and running it on the simulator
+
+These instructions are for Ubuntu 24.04. If you are running on Windows you may have some success with Ubuntu under WSL.
+
+You will need:
+
+* A recent Yosys build to process the Verilog (these instructions were last tested with `a0e94e506`)
+* A `riscv32-unknown-elf-` toolchain to build software for the core
+* A native `clang-16` to build the simulator
+
+`clang-17` is also known to work fine. `clang-18` does work, but has a serious compile time regression with CXXRTL output, which is why the `tb_cxxrtl` Makefile explicitly selects `clang-16`.
+
+## Yosys
+
+The [Yosys GitHub repo](https://github.com/YosysHQ/yosys) has instructions for building Yosys from source.
+
+The following steps work for me on Ubuntu 24.04 using version `a0e94e506` mentioned above.
+
+```bash
+sudo apt install build-essential clang lld bison flex libreadline-dev gawk tcl-dev libffi-dev git graphviz xdot pkg-config python3 libboost-system-dev libboost-python-dev libboost-filesystem-dev zlib1g-dev
+
+git clone https://github.com/YosysHQ/yosys.git
+cd yosys
+git submodule update --init
+make -j$(nproc)
+sudo make install
+```
+
+On MacOS the dependencies can be installed with:
+
+```bash
+brew install graphviz python3 boost zlib bison flex xdot pkg-config gawk lld
+```
+
+## RISC-V Toolchain
+
+I recommend _building_ a toolchain to get libraries with the correct ISA support. Follow the below instructions to build a 32-bit version of the [RISC-V GNU toolchain](https://github.com/riscv/riscv-gnu-toolchain) with a multilib setup suitable for Hazard3 development.
+
+```bash
+# Prerequisites for Ubuntu 24.04
+sudo apt install autoconf automake autotools-dev curl python3 python3-pip libmpc-dev libmpfr-dev libgmp-dev gawk build-essential bison flex texinfo gperf libtool patchutils bc zlib1g-dev libexpat-dev ninja-build git cmake libglib2.0-dev libslirp-dev
+
+cd /tmp
+git clone https://github.com/riscv/riscv-gnu-toolchain
+cd riscv-gnu-toolchain
+
+./configure --prefix=/opt/riscv/gcc15 --with-arch=rv32ia_zicsr_zifencei --with-abi=ilp32 --with-multilib-generator="rv32i_zicsr_zifencei-ilp32--;rv32im_zicsr_zifencei-ilp32--;rv32ia_zicsr_zifencei-ilp32--;rv32ima_zicsr_zifencei-ilp32--;rv32ic_zicsr_zifencei-ilp32--;rv32imc_zicsr_zifencei-ilp32--;rv32iac_zicsr_zifencei-ilp32--;rv32imac_zicsr_zifencei-ilp32--;rv32im_zba_zbb_zbs_zicsr_zifencei-ilp32--;rv32ima_zba_zbb_zbs_zicsr_zifencei-ilp32--;rv32imc_zba_zbb_zbs_zicsr_zifencei-ilp32--;rv32imac_zba_zbb_zbs_zicsr_zifencei-ilp32--;rv32im_zba_zbb_zbs_zbkb_zicsr_zifencei-ilp32--;rv32ima_zba_zbb_zbs_zbkb_zicsr_zifencei-ilp32--;rv32imc_zba_zbb_zbs_zbkb_zicsr_zifencei-ilp32--;rv32imac_zba_zbb_zbs_zbkb_zicsr_zifencei-ilp32--;rv32im_zba_zbb_zbc_zbs_zbkb_zicsr_zifencei-ilp32--;rv32ima_zba_zbb_zbc_zbs_zbkb_zicsr_zifencei-ilp32--;rv32imc_zba_zbb_zbc_zbs_zbkb_zicsr_zifencei-ilp32--;rv32imac_zba_zbb_zbc_zbs_zbkb_zicsr_zifencei-ilp32--;rv32im_zba_zbb_zbs_zbkb_zbkx_zicsr_zifencei-ilp32--;rv32ima_zba_zbb_zbs_zbkb_zbkx_zicsr_zifencei-ilp32--;rv32imc_zba_zbb_zbs_zbkb_zbkx_zicsr_zifencei-ilp32--;rv32imac_zba_zbb_zbs_zbkb_zbkx_zicsr_zifencei-ilp32--;rv32im_zba_zbb_zbc_zbs_zbkb_zbkx_zicsr_zifencei-ilp32--;rv32ima_zba_zbb_zbc_zbs_zbkb_zbkx_zicsr_zifencei-ilp32--;rv32imc_zba_zbb_zbc_zbs_zbkb_zbkx_zicsr_zifencei-ilp32--;rv32imac_zba_zbb_zbc_zbs_zbkb_zbkx_zicsr_zifencei-ilp32--;rv32i_zca_zicsr_zifencei-ilp32--;rv32im_zca_zicsr_zifencei-ilp32--;rv32ia_zca_zicsr_zifencei-ilp32--;rv32ima_zca_zicsr_zifencei-ilp32--;rv32im_zba_zbb_zbs_zca_zicsr_zifencei-ilp32--;rv32ima_zba_zbb_zbs_zca_zicsr_zifencei-ilp32--;rv32im_zba_zbb_zbs_zbkb_zca_zicsr_zifencei-ilp32--;rv32ima_zba_zbb_zbs_zbkb_zca_zicsr_zifencei-ilp32--;rv32im_zba_zbb_zbc_zbs_zbkb_zca_zicsr_zifencei-ilp32--;rv32ima_zba_zbb_zbc_zbs_zbkb_zca_zicsr_zifencei-ilp32--;rv32im_zba_zbb_zbs_zbkb_zbkx_zca_zicsr_zifencei-ilp32--;rv32ima_zba_zbb_zbs_zbkb_zbkx_zca_zicsr_zifencei-ilp32--;rv32im_zba_zbb_zbc_zbs_zbkb_zbkx_zca_zicsr_zifencei-ilp32--;rv32ima_zba_zbb_zbc_zbs_zbkb_zbkx_zca_zicsr_zifencei-ilp32--;rv32i_zca_zcb_zicsr_zifencei-ilp32--;rv32im_zca_zcb_zicsr_zifencei-ilp32--;rv32ia_zca_zcb_zicsr_zifencei-ilp32--;rv32ima_zca_zcb_zicsr_zifencei-ilp32--;rv32im_zba_zbb_zbs_zca_zcb_zicsr_zifencei-ilp32--;rv32ima_zba_zbb_zbs_zca_zcb_zicsr_zifencei-ilp32--;rv32im_zba_zbb_zbs_zbkb_zca_zcb_zicsr_zifencei-ilp32--;rv32ima_zba_zbb_zbs_zbkb_zca_zcb_zicsr_zifencei-ilp32--;rv32im_zba_zbb_zbc_zbs_zbkb_zca_zcb_zicsr_zifencei-ilp32--;rv32ima_zba_zbb_zbc_zbs_zbkb_zca_zcb_zicsr_zifencei-ilp32--;rv32im_zba_zbb_zbs_zbkb_zbkx_zca_zcb_zicsr_zifencei-ilp32--;rv32ima_zba_zbb_zbs_zbkb_zbkx_zca_zcb_zicsr_zifencei-ilp32--;rv32im_zba_zbb_zbc_zbs_zbkb_zbkx_zca_zcb_zicsr_zifencei-ilp32--;rv32ima_zba_zbb_zbc_zbs_zbkb_zbkx_zca_zcb_zicsr_zifencei-ilp32--;rv32i_zca_zcb_zcmp_zicsr_zifencei-ilp32--;rv32im_zca_zcb_zcmp_zicsr_zifencei-ilp32--;rv32ia_zca_zcb_zcmp_zicsr_zifencei-ilp32--;rv32ima_zca_zcb_zcmp_zicsr_zifencei-ilp32--;rv32im_zba_zbb_zbs_zca_zcb_zcmp_zicsr_zifencei-ilp32--;rv32ima_zba_zbb_zbs_zca_zcb_zcmp_zicsr_zifencei-ilp32--;rv32im_zba_zbb_zbs_zbkb_zca_zcb_zcmp_zicsr_zifencei-ilp32--;rv32ima_zba_zbb_zbs_zbkb_zca_zcb_zcmp_zicsr_zifencei-ilp32--;rv32im_zba_zbb_zbc_zbs_zbkb_zca_zcb_zcmp_zicsr_zifencei-ilp32--;rv32ima_zba_zbb_zbc_zbs_zbkb_zca_zcb_zcmp_zicsr_zifencei-ilp32--;rv32im_zba_zbb_zbs_zbkb_zbkx_zca_zcb_zcmp_zicsr_zifencei-ilp32--;rv32ima_zba_zbb_zbs_zbkb_zbkx_zca_zcb_zcmp_zicsr_zifencei-ilp32--;rv32im_zba_zbb_zbc_zbs_zbkb_zbkx_zca_zcb_zcmp_zicsr_zifencei-ilp32--;rv32ima_zba_zbb_zbc_zbs_zbkb_zbkx_zca_zcb_zcmp_zicsr_zifencei-ilp32--;rv32i_zmmul_zicsr_zifencei-ilp32--;rv32ia_zmmul_zicsr_zifencei-ilp32--;rv32ic_zmmul_zicsr_zifencei-ilp32--;rv32iac_zmmul_zicsr_zifencei-ilp32--;rv32i_zca_zmmul_zicsr_zifencei-ilp32--;rv32ia_zca_zmmul_zicsr_zifencei-ilp32--;rv32i_zca_zcb_zmmul_zicsr_zifencei-ilp32--;rv32ia_zca_zcb_zmmul_zicsr_zifencei-ilp32--;rv32i_zca_zcb_zcmp_zmmul_zicsr_zifencei-ilp32--;rv32ia_zca_zcb_zcmp_zmmul_zicsr_zifencei-ilp32--;rv32e_zicsr_zifencei-ilp32e--;rv32ema_zicsr_zifencei-ilp32e--;rv32emac_zicsr_zifencei-ilp32e--;rv32ema_zicsr_zifencei_zba_zbb_zbc_zbkb_zbkx_zbs_zca_zcb_zcmp-ilp32e--"
+sudo mkdir -p /opt/riscv/gcc15
+sudo chown $(whoami) /opt/riscv/gcc15
+make -j $(nproc)
+```
+
+The `--with-multilib-generator=` flag builds multiple versions of the standard library, to match possible `-march` flags provided at link time. The multilib-generator command line above was generated using [multilib-gen-gen.py](test/sim/common/multilib-gen-gen.py)
+
+Make sure this toolchain can be found on your `PATH` (as `riscv32-unknown-elf-*`):
+
+```bash
+export PATH="$PATH:/opt/riscv/gcc15/bin"
+```
+
+### Non-multilib (Smaller Install Size)
+
+For a faster build and a smaller install size, use this `./configure` line instead:
+
+```bash
+./configure --prefix=/opt/riscv/gcc15 --with-arch=rv32imac_zicsr_zifencei_zba_zbb_zbkb_zbs --with-abi=ilp32
+```
+
+Adjust the `--with-arch` line as necessary for your Hazard3 configuration. You may need to adjust architectures used in software Makefiles in this repository to fit your chosen architecture variant.
+
+### Building Toolchain on MacOS
+
+These are my hacks to build the latest `riscv-gnu-toolchain` on MacOS Sequoia on M4 (Arm).
+
+```bash
+brew install python3 gawk gnu-sed make gmp mpfr libmpc isl zlib expat texinfo flock libslirp
+git clone https://github.com/riscv/riscv-gnu-toolchain
+cd riscv-gnu-toolchain
+git submodule update --init -- binutils gdb
+# HACK for a macro definition which conflicts with a system header:
+gsed -i 's,#        define fdopen,//#define fdopen,' binutils/zlib/zutil.h gdb/zlib/zutil.h
+
+export PATH="/opt/homebrew/bin:$PATH"
+export LDFLAGS="-L/opt/homebrew/lib"
+export CPPFLAGS="-I/opt/homebrew/include"
+./configure --prefix=/opt/riscv/gcc15 --with-arch=rv32imac_zicsr_zifencei_zba_zbb_zbkb_zbs --with-abi=ilp32
+gmake -j10
+```
+
+## Actually Running Hello World
+
+Make sure you have done a _recursive_ clone of the Hazard3 repository. Build the CXXRTL-based simulator:
+
+```bash
+cd hazard3
+cd test/sim/tb_cxxrtl
+make
+```
+
+Build and run the hello world binary:
+
+```bash
+cd ../hellow
+make
+```
+
+All going well you should see something like:
+
+```
+$ make
+mkdir -p tmp/
+riscv32-unknown-elf-gcc -march=rv32imac_zicsr_zifencei_zba_zbb_zbkb_zbs -Os -Wl,--no-warn-rwx-segments ../common/init.S main.c -T ../common/memmap.ld -I../common -o tmp/hellow.elf
+riscv32-unknown-elf-objcopy -O binary tmp/hellow.elf tmp/hellow.bin
+riscv32-unknown-elf-objdump -h tmp/hellow.elf > tmp/hellow.dis
+riscv32-unknown-elf-objdump -d tmp/hellow.elf >> tmp/hellow.dis
+../tb_cxxrtl/tb --bin tmp/hellow.bin --vcd tmp/hellow_run.vcd --cycles 100000
+Hello world from Hazard3 + CXXRTL!
+CPU requested halt. Exit code 123
+Ran for 897 cycles
+```
+
+This will have created a waveform dump called `tmp/hellow_run.vcd` which you can view with GTKWave:
+
+```bash
+gtkwave tmp/hellow_run.vcd
+```
+
+Installing GTKWave on Ubuntu 24.04 is just `sudo apt install gtkwave`.
+
+# Loading Hello World with the Debugger
+
+Invoking the simulator built in the previous step, with no arguments, shows the following usage message:
+
+```
+$ ./tb
+At least one of --bin or --port must be specified.
+Usage: tb [--bin x.bin] [--vcd x.vcd] [--dump start end] [--cycles n] [--port n]
+    --bin x.bin      : Flat binary file loaded to address 0x0 in RAM
+    --vcd x.vcd      : Path to dump waveforms to
+    --dump start end : Print out memory contents from start to end (exclusive)
+                       after execution finishes. Can be passed multiple times.
+    --cycles n       : Maximum number of cycles to run before exiting.
+                       Default is 0 (no maximum).
+    --port n         : Port number to listen for openocd remote bitbang. Sim
+                       runs in lockstep with JTAG bitbang, not free-running.
+```
+
+This simulator contains:
+
+- Hardware:
+	- The processor
+	- A Debug Module (DM)
+	- A JTAG Debug Transport Module (DTM)
+- Software:
+	- RAM model
+	- Routines for loading binary files, dumping VCDs
+	- Routines for bitbanging the JTAG DTM through a TCP socket
+
+Running hello world in the previous section used the `--bin` argument to load the linked hello world executable directly into the testbench's RAM. If we invoke the simulator with the `--port` argument, it will instead wait for a connection on that port, and then accept JTAG bitbang commands in OpenOCD's `remote-bitbang` format. The simulation runs in lockstep with the JTAG bitbanging, for more predictable results.
+
+We need to build a copy of `riscv-openocd` before going any further. OpenOCD's role is to translate the abstract debug commands issued by gdb, e.g. "set the program counter to address `x`", to more concrete operations, e.g. "shift this JTAG DR".
+
+## Building riscv-openocd
+
+We need a recent build of [riscv-openocd](https://github.com/riscv/riscv-openocd) with the `remote-bitbang` protocol enabled.
+
+On Ubuntu:
+
+```bash
+cd /tmp
+git clone https://github.com/riscv/riscv-openocd.git
+cd riscv-openocd
+./bootstrap
+# Prefix is optional
+./configure --enable-remote-bitbang --enable-ftdi --program-prefix=riscv-
+make -j $(nproc)
+sudo make install
+```
+
+On MacOS:
+
+```bash
+brew install autoconf automake libusb jimtcl
+cd /tmp
+git clone https://github.com/riscv/riscv-openocd.git
+cd riscv-openocd
+./bootstrap
+# Workarounds:
+# - System clang has a warning for the GCC constant VLA thing, and OpenOCD is -Werror by default
+# - amtjtagaccel driver tries to pull in a Linux header
+CFLAGS=-Wno-gnu-folding-constant ./configure --enable-remote-bitbang --enable-ftdi --enable-amtjtagaccel=no --program-prefix=riscv-
+```
+## Loading and Running
+
+You're going to want three terminal tabs in the `tb_cxxrtl` directory.
+
+```bash
+cd hazard3/test/sim/tb_cxxrtl
+```
+
+In the first of them type:
+
+```bash
+./tb --port 9824
+```
+
+You should see something like
+
+```
+Waiting for connection on port 9824
+```
+
+The simulation will start once OpenOCD connects. In your second terminal in the same directory, start riscv-openocd:
+
+```bash
+riscv-openocd -f openocd.cfg
+```
+
+If you see something like:
+
+```
+Info : Initializing remote_bitbang driver
+Info : Connecting to localhost:9824
+Info : remote_bitbang driver initialized
+Info : Note: The adapter "remote_bitbang" doesn't support configurable speed
+Info : JTAG tap: hazard3.cpu tap/device found: 0xdeadbeef (mfg: 0x777 (Fabric of Truth Inc), part: 0xeadb, ver: 0xd)
+Info : [hazard3.cpu] datacount=1 progbufsize=2
+Info : [hazard3.cpu] Examined RISC-V core
+Info : [hazard3.cpu]  XLEN=32, misa=0x40901107
+[hazard3.cpu] Target successfully examined.
+Info : [hazard3.cpu] Examination succeed
+Info : [hazard3.cpu] starting gdb server on 3333
+Info : Listening on port 3333 for gdb connections
+hazard3.cpu halted due to debug-request.
+Info : Listening on port 6666 for tcl connections
+Info : Listening on port 4444 for telnet connections
+```
+
+Then openocd is successfully connected to the processor's debug hardware. We're going to use riscv-gdb to load and run the hello world executable, which is what the third terminal is for:
+
+```bash
+riscv32-unknown-elf-gdb
+# Remaining commands are typed into the gdb prompt. This one tells gdb to shut up:
+set confirm off
+# Connect to openocd on its default port:
+target extended-remote localhost:3333
+# Load hello world, and check that it loaded correctly
+file ../hellow/tmp/hellow.elf
+load
+compare-sections
+# The processor will quit the simulation when after returning from main(), by
+# writing to a magic MMIO register. openocd will be quite unhappy that the
+# other end of its socket disappeared, so to avoid the resulting error
+# messages, add a breakpoint before _exit.
+break _exit
+run
+# Should break at _exit. Check the terminal with the simulator, you should see
+# the hello world message. The exit code is in register a0, it should be 123:
+info reg a0
+```
+
+# Simulating with Verilator
+
+There is a Verilator harness with the same features and interface as the CXXRTL harness, except it does not support VCD dumping. First build Verilator:
+
+```
+git clone https://github.com/verilator/verilator.git
+cd verilator
+mkdir build
+cd build
+cmake ..
+make -j$(nproc)
+sudo make install
+```
+
+Then go to the Hazard3 repository and build the simulator. You should be able to run the hello world binary you compiled earlier:
+
+```bash
+cd test/sim/tb_verilator
+make tb
+./tb --bin ../hellow/tmp/hellow.bin
+```
+
+# Building an Example SoC
+
+There is a tiny [example SoC](example_soc/soc/example_soc.v) which builds on iCEBreaker, ULX3S and Arty A7-100T boards. The SoC contains:
+
+- A Hazard3 processor, in a single-ported RV32IMA configuration, with debug support
+- A Debug Transport Module and Debug Module to access Hazard3's debug interface
+- 128 kB of RAM (fits in UP5k SPRAMs)
+- A UART
+- A standard RISC-V platform timer
+
+Note there is no software tree for this SoC. For now you'll have to read the source and hack on the test software build. At least you can attach to the processor, poke registers/memory, and convince yourself you really are debugging a RISC-V core.
+
+## Comparison of Supported Boards
+
+On [iCEBreaker](https://1bitsquared.com/products/icebreaker) (a iCE40 UP5k development board), the processor can be debugged using the onboard FT2232H bridge, through a standard RISCV-V JTAG-DTM exposed on four IO pins. Connecting JTAG requires two solder jumpers to be bridged on the back to connect the JTAG -- see the comments in the [pin constraints file](example_soc/synth/fpga_icebreaker.pcf). FT2232H is a dual-channel FTDI device, so the UART and JTAG can be accessed simultaneously for a very civilised debug experience, with JTAG running at the full 30 MHz supported by the FTDI.
+
+[ULX3S](https://radiona.org/ulx3s/) is based on a much larger ECP5 FPGA. Thanks to [this ECP5 JTAG adapter](hdl/debug/dtm/hazard3_ecp5_jtag_dtm.v), it is possible to attach the guts of a RISC-V JTAG-DTM to the custom DR hooks in ECP5's chip TAP. With the right config file you can then convince OpenOCD that the FPGA's own TAP *is* a JTAG-DTM. You can debug Hazard3 on ULX3S using the same micro USB cable you use to load the bitstream, no soldering required. The downside is that the FT231X device on the ULX3S is actually a UART bridge which supports JTAG by bitbanging the auxiliary UART signals, which is incredibly slow. The UART cannot be used simultaneously with JTAG access. The debugging experience is worse than iCEBreaker because of this.
+
+Arty A7-100T uses an Artix-7 FPGA. This is the fastest and most capacious of the boards supported by this example SoC integration, but it's also the most expensive. The board has an FT2232H debug probe, similar to iCEBreaker. The probe is intended for programming the FPGA, or for Xilinx debug functionality like ILA. Using the probe, you can tunnel RISC-V debug traffic through the Artix-7 chip TAP [in a similar way](hdl/debug/dtm/hazard3_xilinx7_jtag_dtm.v) to ECP5, using the `BSCANE2` primitive. There is no performance cost to this tunnelling as the DTM registers are exposed directly as DRs on the FPGA chip TAP, so this is an excellent combination of a fast FPGA and a fast debug interface.
+
+## Building for iCEBreaker
+
+You must have `nextpnr-ice40`, `yosys`, and `iceprog` (from icestorm) on your PATH.
+
+```bash
+cd hazard3
+cd example_soc/synth
+make -f Icebreaker.mk prog
+# Should be able to attach to the processor
+riscv-openocd -f ../icebreaker-openocd.cfg
+```
+
+## Building for ULX3S
+
+You must have `nextpnr-ecp5`, `yosys` and [ujprog](https://github.com/f32c/tools/blob/master/ujprog/README.md) on your PATH.
+
+```bash
+cd hazard3
+cd example_soc/synth
+make -f ULX3S.mk flash
+# Should be able to attach to the processor
+riscv-openocd -f ../ulx3s-openocd.cfg
+```
+
+## Building for Arty A7-100T
+
+These scripts use Vivado to build and load the bitstream. You must have `vivado` on your `PATH`; I used version 2025.1. The free version of Vivado supports the A7-100T, so just type some swear words into AMD's export compliance form and away you go.
+
+```bash
+cd hazard3
+cd example_soc/synth_vivado
+make prog
+# Should be able to attach to the processor
+riscv-openocd -f ../arty7-openocd.cfg
+```
+
+Vivado and OpenOCD cannot simultaneously connect to the FTDI. If OpenOCD is connected then Vivado will fail to reprogram the FPGA.
+
+# Performance
+
+## RP2350
+
+The RP2350 configuration of Hazard3 achieves 4.15 CoreMark/MHz.
+
+```
+2K performance run parameters for coremark.
+CoreMark Size    : 666
+Total ticks      : 14440822
+Total time (secs): 14.440822
+Iterations/Sec   : 4.154888
+Iterations       : 60
+Compiler version : GCC15.1.0
+Compiler flags   : -O3 -g -march=rv32ima_zicsr_zifencei_zba_zbb_zbkb_zbs -mbranch-cost=1 -funroll-all-loops --param max-inline-insns-auto=200 -finline-limit=10000 -fno-code-hoisting -fno-if-conversion2 -DPERFORMANCE_RUN=1  
+Memory location  : STACK
+seedcrc          : 0xe9f5
+[0]crclist       : 0xe714
+[0]crcmatrix     : 0x1fd7
+[0]crcstate      : 0x8e3a
+[0]crcfinal      : 0xa14c
+Correct operation validated. See README.md for run and reporting rules.
+CoreMark 1.0 : 4.154888 / GCC15.1.0 -O3 -g -march=rv32ima_zicsr_zifencei_zba_zbb_zbkb_zbs -mbranch-cost=1 -funroll-all-loops --param max-inline-insns-auto=200 -finline-limit=10000 -fno-code-hoisting -fno-if-conversion2 -DPERFORMANCE_RUN=1   / STACK
+```
+
+To reproduce this in the RTL simulator, use the top-level Makefile in [test/sim/coremark](test/sim/coremark) after you have followed all the steps to get set up for running a "Hello, world!" binary above. Expect the simulation to take a couple of minutes.
+
+```bash
+cd test/sim/coremark
+make
+```
+
+The default flags are appropriate for the non-multilib toolchain build, and achieve 4.10 CoreMark/MHz. To achieve the full 4.15 CoreMark/MHz, change the ISA variant in `core_portme.mak` to `rv32ima_zicsr_zifencei_zba_zbb_zbkb_zbs`. See the comments in that file for an explanation of why this makes a difference.
+
+See the RP2350 datasheet for details of the Hazard3 configuration used by that chip. The default `tb_cxxrtl` build uses the same configuration as RP2350, except that it also enables the Zbc extension (which is not emitted by GCC 14 as it is not useful for general-purpose code).
+
+## Maximum
+
+As of GCC 15, GCC can infer `clmul` and `clmulh` instructions in the CoreMark CRC function. The Zbc extension was dropped from the RP2350 configuration as compilers were not able to exploit it at the time. Enabling Zbc increases the score to 4.25 CoreMark/MHz.
+
+```
+CoreMark Size    : 666
+Total ticks      : 14121622
+Total time (secs): 14.121622
+Iterations/Sec   : 4.248804
+Iterations       : 60
+Compiler version : GCC15.1.0
+Compiler flags   : -O3 -g -march=rv32ima_zicsr_zifencei_zba_zbb_zbkb_zbs_zbc -mbranch-cost=1 -funroll-all-loops --param max-inline-insns-auto=200 -finline-limit=10000 -fno-code-hoisting -fno-if-conversion2 -falign-functions=4 -falign-jumps=4 -falign-loops=4 -DPERFORMANCE_RUN=1  
+Memory location  : STACK
+seedcrc          : 0xe9f5
+[0]crclist       : 0xe714
+[0]crcmatrix     : 0x1fd7
+[0]crcstate      : 0x8e3a
+[0]crcfinal      : 0xa14c
+Correct operation validated. See README.md for run and reporting rules.
+CoreMark 1.0 : 4.248804 / GCC15.1.0 -O3 -g -march=rv32ima_zicsr_zifencei_zba_zbb_zbkb_zbs_zbc -mbranch-cost=1 -funroll-all-loops --param max-inline-insns-auto=200 -finline-limit=10000 -fno-code-hoisting -fno-if-conversion2 -falign-functions=4 -falign-jumps=4 -falign-loops=4 -DPERFORMANCE_RUN=1   / STACK
+```
+
+## RV32E
+
+Reducing the number of GPRs from 31 to 15 carries around a 5% penalty, at 4.02 CoreMark/MHz.
+
+```
+2K performance run parameters for coremark.
+CoreMark Size    : 666
+Total ticks      : 14908801
+Total time (secs): 14.908801
+Iterations/Sec   : 4.024469
+Iterations       : 60
+Compiler version : GCC15.1.0
+Compiler flags   : -O3 -g -march=rv32ema_zba_zbb_zbc_zbkb_zbkx_zbs_zicsr_zifencei -mabi=ilp32e -mbranch-cost=1 -funroll-all-loops --param max-inline-insns-auto=200 -finline-limit=10000 -fno-code-hoisting -fno-if-conversion2 -falign-functions=4 -falign-jumps=4 -falign-loops=4 -DPERFORMANCE_RUN=1  
+Memory location  : STACK
+seedcrc          : 0xe9f5
+[0]crclist       : 0xe714
+[0]crcmatrix     : 0x1fd7
+[0]crcstate      : 0x8e3a
+[0]crcfinal      : 0xa14c
+Correct operation validated. See README.md for run and reporting rules.
+CoreMark 1.0 : 4.024469 / GCC15.1.0 -O3 -g -march=rv32ema_zba_zbb_zbc_zbkb_zbkx_zbs_zicsr_zifencei -mabi=ilp32e -mbranch-cost=1 -funroll-all-loops --param max-inline-insns-auto=200 -finline-limit=10000 -fno-code-hoisting -fno-if-conversion2 -falign-functions=4 -falign-jumps=4 -falign-loops=4 -DPERFORMANCE_RUN=1   / STACK
+```

Wren6991_Hazard3/doc/.gitignore

@@ -0,0 +1,3 @@
+rev.adoc
+*.pdf
+*.html

Wren6991_Hazard3/doc/Makefile

@@ -0,0 +1,36 @@
+TOP=hazard3
+DEPS=$(shell find -name "*.adoc" | grep -v rev.adoc) diagrams/* *.yml
+
+.PHONY: all clean view spell rev
+
+all: spell $(TOP).pdf $(TOP).html
+
+# `xdg-open` for Ubuntu and friends; `open` for MacOS
+view: all
+ifneq (,$(shell which xdg-open))
+	xdg-open $(TOP).pdf
+else
+	open $(TOP).pdf
+endif
+
+clean:
+	rm -f $(TOP).pdf
+
+spell:
+ifeq (,$(shell which codespell))
+	@echo "Install codespell to check spelling"
+else
+	@find -name "*.adoc" | xargs codespell -L hart
+	@echo "No spelling errors found"
+endif
+
+rev:
+	@echo ":revdate: Updated: `date +%Y-%b-%d`" > rev.adoc
+
+$(TOP).pdf: $(DEPS) rev
+	asciidoctor-pdf -a compress $(TOP).adoc
+
+# data-uri attribute: embed images etc in the HTML as base64. Fine as they are
+# small, means the whole doc is one file.
+$(TOP).html: $(DEPS) rev
+	asciidoctor --section-numbers -a HTMLBUILD $(TOP).adoc

Wren6991_Hazard3/doc/Readme.md

@@ -0,0 +1,19 @@
+Building
+--------
+
+## Ubuntu
+
+```bash
+# Get tools
+sudo apt install ruby-asciidoctor-pdf codespell
+# Build
+make
+```
+
+
+## MacOS
+
+```bash
+brew install asciidoctor codespell
+make
+```

Wren6991_Hazard3/doc/diagrams/debug_topology.drawio

@@ -0,0 +1 @@
+<mxfile host="app.diagrams.net" modified="2021-11-28T05:22:40.327Z" agent="5.0 (X11)" etag="nTSUjZuznzFSxSvFVrET" version="15.8.6" type="device"><diagram id="9fEN5FmfpFAiGjkGDVgf" name="Page-1">7Vpdc9o6EP01PKbjDzDkEUza9E47kymdSfOo2outW2ExsgjQX98VljG2HOqOcXBmkgcirVayfPborCQYuP5q90mQdfyVh8AGjhXuBu584Dhjb4yfyrDPDKOxNkSChpnJLgwL+hu00dLWDQ0hLTlKzpmk67Ix4EkCgSzZiBB8W3ZbclZ+6ppEYBgWAWGm9ZGGMs6sE2dc2O+BRnH+ZNu7zVpWJHfWb5LGJOTbE5N7N3B9wbnMSqudD0xhl+OS9fv4QutxYgIS2aRD8mMRfBPjL7PHe5lMp58f2dPkxtazfSZso99Yz1bucwgE3yQhqFGsgTvbxlTCYk0C1brFmKMtliuGNRuLIUnjg6+q6LFBSNi9OGv7iAVyCPgKpNijS95houHT/HFudX1bRMPNIY5PIuHmDCKaAdFx7AIkLGic/gUz741hZjfFzLa6wmxsQDZ9mBmoQYhrT1e5kDGPeELYXWGdlXEtfL5wvtYA/g9S7rWQkI3kZaxhR+UP1f3DSNeeTlrmOz3yobLPKwlCcNJJVZ9O24puh1reL5VEyKkSITQEjKQpDXLzR8pYKeLq3c/HG6HiGxHAOWpqhSQiAnnGz6nnjwBGJH0uz+PiXJgYXPjv+/RTf8hgnSXDlYLaIli66wOn+OSjSLjDirBW135GIt2rEvLjNFqoaI2IekwqOaTPWIxUcQ4/NxF6fRckSdcYYSzjFmOD4dfO+OwT/5ohctNPUbVUu7aR8AuotlPNdENTte061fa6Eu26PGfg63MBN+kaArrEhdA0KkgqEEuFZrNgvGeGliLiNMwMw7McvbE+eKOxfua/CRC+LdmfOKyVsKTN9Wk4rGxvK/5D56w/FrIZVHrn0+HLZQrdCJ3z9+3iK9C7v5Sz2ya4ViJXFx1Dru7JbyJCt7G85XnrfK7qWcJxr55w8iNbH4T//C7w7Qi/2074X2kRDo1V+Bmr0/sr7wSc5luBhpGFJMydEp5AZtHtVgeRv/i5wXERFuvkb1QSkVFVHDo+RjgjgznzPjBnfHHm9J8Zt71ihttFYlenncHhqNzPlG5VNsHetVO6Yx4i35W97fptm6tfOHH1a/065p3xu7JfhxnDUa+YYW4WL6fs9pu5L3S9vmm9bd7pLvaphBXavsHhesXyOZ6HOGMgrg5g9cao7vzrvSp+JrH9uX91nIyL6UlDojmdAVWTGvSNi8948Av/z/mK0MTADlGQ1XsxwX+BzxkXReZeojhXTITRKFEyDurqGg0KUxoQNtUNKxqGh1xTF5FyzC7+he9tJUL5qegvTHY72/VZRoAeBA8gTRHS9yBl4NvN5Ka7IJlfxB7lerZJr687lcPMqCbBHbWope5gtfglTrZPKX7O5N79AQ==</diagram></mxfile>

Wren6991_Hazard3/doc/diagrams/hazard3_backend.drawio

@@ -0,0 +1 @@
+<mxfile modified="2021-11-04T15:44:57.753Z" host="app.diagrams.net" agent="5.0 (X11)" etag="1fTGXkcA6LinXzucZQNY" version="15.4.0" type="device"><diagram name="Page-1" id="7e0a89b8-554c-2b80-1dc8-d5c74ca68de4">7V1tc5s4EP41/liPxDsfEye5600zl0nmru19I0a2aW3jA9w49+tPYMSLJBtsgwTEnmljZJDxPvtIq93VMlInq91vgbNZPPouWo4U4O5G6t1IUSC0dPwnbnlPW3RL3bfMA89N2/KGF+8/lDaCtHXruSgsnRj5/jLyNuXGqb9eo2lUanOCwH8rnzbzl+Vv3ThzxDS8TJ0l2/rVc6MF+WEA5B/8jrz5Iv1qS08/eHWmP+eBv12n3zdS1Fny2n+8ckhf6fnhwnH9t0KTej9SJ4HvR/t3q90ELWPhErHtr3s48Gl23wFaR3UumK3u1hFY/Xb7Fsx+rHff0fwf+MlIb+6Xs9wi8juSu43eiYTQ2r2JBY2P1v4aN966TrhAcbcQHyyi1TJ9u78UuYzE83skEDvBHKVNDzD6Ogd///Hw+Gtibf9ZTv5G95+gZmcywsqH/BWKgnd85VsOEkFiUYCHtAVo6UTer/KNOKmuzLPusm948j18iwogim1ZqSBSvTYsUO4j9LfBFKWXFcXO9gTHNrDzV6lfnep2LximW/ymIIW8KcH4BLyJJDqHtykTbYNw9FKwmY5aQ5dPGt1uEt4Q325EnXsQYUYL9jLrNMUxMWEJL5Om4wksL48XUBELvar0CPlOkd2kSXou2UVDbloswhiKl/TQD6KFP/fXzvI+b71NDJYEcoCP8nO++P4mBf8HiqL31FBztpFfVg2086Jvhfff467Genp0t0t7Tg7eycEa/9JvxYPCVfFhfllyRK7jqWHS9uDFokqvyJR6unTC0JvuG9NT4DHNrVRUpebsZVhcKrAqXlt3S8pyqmawY0EQ4u8ylvg33L4G+N08fvf8gE96Ro6L/zxhVWDUqawsbwsvQi8bJ5HYG14OlBVjhgU+8Zd+kFyrug6yZtMEsMD/iQqfGFMLvc6O4fILBRHaHRVk+qlulDmokmVFYSzJeFkcTGjSNyZ707yysmVWqnVZaXeKlSqHlcqHYKUmnZXZInywrDyfThpLJ+7aUW+aTXyzyoTGuLBatq2SKumm2AWzwTGjh6g4dRbxjWnSgXWfmGFYY4bhyedndhgewLCr67KHXZWd8yZLf/qTES7+hRG9BC1KKjUzimJNm5ylN1/HZgaWG8Ltt7G8vKmzvEk/WHmum7CSB1kZ1AYwMAC1KAQsBhoHAnrt2BwErL4TZZ/5ybibw2D8u/XJB5/CZHC6wSdAY7PLPyQEeYliz7oC7r6R/vD97bs8wKDBgGwr2tgqz0s2h2oQjBVNINSGyYGawiCOWGzqiyCLuzivpAdwVDQQUIMQTzJcBkDa6docBSxGLjdf/mp0gEfQ1ZHJG+Btw1Qdg6t3x0Gs1kaJEj3LzyxSfJVWqhhno03NBuqZvka6H9CaFcy3mc4KE17xPjeORHXTXpCQjzbrP7yizY36UMae3QzctNa0DTfPQrzCLQxu4YO5fsW7Ht56BVC1o8O6XIIbV8DPAryn0ze73LnC3Sq/q6z8tgFnV2N/bm4YzLvqfrl0GUxCv5IdbUSZSij0xwnWEApQOgxshuMzCrdLNo46VCR2RMJUEFY2MOyqcuKv8A/3Qn/90cDhOEUNoWCwgZkb1/1oKNAUyYJjsjhCgttyos1grJAQ8/dRIcLMDTeXsoDyHJ9iIlDSN2No5llAl6UtNJ9zdyAfQQdjaAPNNNL/SyqDmTwufIb/F2r6mRzTXqTCmFeFYRTGgh1WGLJfq0/5LKmWkZQWODqe0CI9P5EoWmWCIvEvNKyR+Jc574UTNrEyhYcV1qaTaDVqJ1nV+TqgVHV/B40mYinDV1yuMjSngnyxqn3UOKVhjTsqw4KNfPu+wYNFy8liZ/nbTs5hMandKx3InFevxm9tfjee2n6O8atKNn6lTgk9M34FKcxx41eywlhGD20IpWfGr13T+DXb0ciTTRGNcpNWmSL0+VCAKQJJjkafNLeotj3YVVZbcaGmDkJzdVWEEc3GJgdsRMvf6GZJHSjywaHaJOrtQGHWHSj0xt07l62vaiRthwtnE7+NML/Qf37c3+0GBR6+gziKk7c/5Y1VzAz8CP86Pw762E1twLAo3nECN5bIwI0FGVFeadcs7QielbTTGjcsL1ONGrnzPaWdKpt2EDZaz+qSsjfSkthUqqLY+ZXKtEPhcFHlq6DCoDnw7aJQpSjFSQwRmoEA4bWqUNszmV63gElGwLa9dlDVDxhUoqivsLPk3e0WrxLBjesGKF4vgqeFEyJGOy9ZJc5myJhy9+W7pv0KGiM5tfJWa6Z/NbFK5Fe1kGquCnGEcolzHl8h2cVdTdh9kqMsUzO7UXqnMziQAtv9mhYsd6S7WKBynSJbnyJr1wkmKi/ZGQtVldLTCm9s1QVtBRKuutu27mbxgRqRBKNp5b1sZNPYtPCXyA+SMi9O5AyiShKeUeCYZJNlO/TAmLgS5M0reg/D073jplGbm3U3KwripiV15D7FxSw92aWFcfXAJK4bcKwCPXuZpWFFM+2xbVvZyy733/aamrPve0CxV6iDjo7jxtXGan8cN+uO47U3nYuysdgqbbfvUWxifXHWKFmrb5bedB+7GQRRDUM6UfkFbXtYqlvelgJYf00u2QvG2QL+5MVRJKxIWCLgxZuvP93vIjwY9ZFOOqj2JoteuUhl0odIf4Bk/3zdR2d1Z8bj7Pxn1KUnGRDQrEE+sSkQBivdoQfNLUMZl+0J6WFzg/WcNVtm+fHDVVmGBgRVIBu6UJBZ0z0NUn8NvCj3kvY3Um0p6tjs4praZIsWxoXHHx6Hq/+mVgYim1eKKHBAgO2BwOo/lv/D1+FiYIGuYWCxE83AMYC6btD+A80UhwPXd6D1PlajVC15Rmf5Do49OqiyGsEeLtGxe5uy6fWqjVR0nqxZEeoHdKHJUy/AHKA0toUKG+wMe7/bOLGPBHzGHcaG5x/x+9UKuZ4TobBRA6e284TzjApGJQ/PqdSGLV1kNhG/AMfVCXnCQHLa5mLhA4lZ1i7yhNiDAwl1viaikA67C6xE8xf876/B0Vyki5Q/uEotbnIKzRtkazPTOSd1jsoJVdoruHzkd5VDeIGzni5GxXR1/A5bz/0jD/sIJ84zzLjutfYmSdZh3FH2dCFfvW5o3JJjbdPkPbFsgdpwwQ2+wvVwedcphetSsbkLFU4RUeGF9aw9TQaRbks/lFSRvuLSJJcNuzxYbQp03SicZPYO+W4gOGALHvatMMOBAN+KwgsPUkooLgR+kXlIFwHI4m0CIuBc2ao9LHkzljVV87JI2qHzZWN0jUfZ4m68TYiqSeCEGzSNf+vM28WQ0xMhSF6HAiRNUEYt54Ur5LgYyebMgG0Jt84DovojXCrpXpUrXH3wyd8NjkZQ4USGjiV1SsthUzj5B/vUj2fkuKP+Z37QxV+k1yjQ2b3smZPtGf27RWG3H+l0mQ+O3h3Ms7J4cNCe0ObgYAnw52wWoiGDwDpC2amFV9oJqm2BwNnRxRtvBgwBZ3ZvC4Lj2dXFB8w9jPIUwCc8fTc6AQjaFm0pdFKtykuyEeqq4WbV9tdSpZYBmlxL1ajz3O/eCNewy8LVzZaEiw8DP07Rzv1DWBqLR99F8Rn/Aw==</diagram></mxfile>

Wren6991_Hazard3/doc/hazard3-theme.yml

@@ -0,0 +1,11 @@
+extends: default-sans
+title-page:
+  title:
+    top: 90%
+  logo:
+    image: image:diagrams/hazard3_logo_riscv_colors.svg[pdfwidth=80%]
+    align: center
+    top: 25%
+
+codespan:
+  font-color: "#00509E"

Wren6991_Hazard3/doc/hazard3.adoc

@@ -0,0 +1,40 @@
+:sectnums:
+:toc:
+:toclevels: 3
+:doctype: book
+:pdf-fontsdir: fonts
+:pdf-theme: hazard3-theme.yml
+ifdef::HTMLBUILD[]
+:data-uri:
+:toc: left
+endif::[]
+:times: ×
+
+include::rev.adoc[]
+
+ifdef::HTMLBUILD[]
+= Hazard3: Design Guide and Reference Manual
+endif::[]
+
+ifndef::HTMLBUILD[]
+= Design Guide and Reference Manual
+endif::[]
+
+include::sections/introduction.adoc[]
+
+include::sections/configuration_and_integration.adoc[]
+
+include::sections/bus_behaviour.adoc[]
+
+include::sections/csr.adoc[]
+
+include::sections/custom_extensions.adoc[]
+
+[[debug-chapter]]
+include::sections/debug.adoc[]
+
+[appendix]
+include::sections/instruction_timings.adoc[]
+
+[appendix]
+include::sections/release_notes.adoc[]

Wren6991_Hazard3/doc/sections/bus_behaviour.adoc

@@ -0,0 +1,77 @@
+
+== Bus Behaviour
+
+Hazard3 implements one or two AHB5 bus manager ports. <<port-descriptions-1port>> describes the signal-level implementation for a single-ported processor, and <<port-descriptions-2port>> for dual-ported. This section describes their behaviour at a higher level, and the requirements Hazard3 imposes on your bus subsystem.
+
+=== Protocol
+
+Hazard3 implements the AHB5 protocol, as described in the https://documentation-service.arm.com/static/5f91607cf86e16515cdc3b4b[AMBA 5 AHB protocol specification].
+
+=== Single and Dual-port
+
+In a dual-ported processor, loads and stores issue to the D port and instruction fetch issues to the I port. In a single-ported processor, all accesses issue to the single available port.
+
+When the processor experiences internal contention, loads and stores take priority over instruction fetch. The rationale for this behaviour is that stalling a load or store will always increase the number of cycles required to execute a program, but stalling an instruction fetch has no cycle cost if the prefetch buffer is able to cover the gap.
+
+For single-ported implementations it's highly recommended to enable compressed instruction support (<<param-EXTENSION_C>> = `1`). This reduces contention between instruction fetch and load/store, increasing performance.
+
+=== Bursts
+
+Hazard3 never generates bursts. `HTRANS` is always `IDLE` or `NSEQ`; `HBURST` is always `SINGLE`.
+
+=== Alignment
+
+All Hazard3 bus accesses are naturally aligned. That is, address modulo access size is always zero; `HADDR % (1 << HSIZE) == 0` (if `HTRANS` is not `IDLE`). Additionally, instruction fetch is always word-aligned and word-sized.
+
+The Zilsd instructions `ld` and `sd` notionally perform 64-bit accesses, but Hazard3 issues these as pairs of 32-bit accesses over its 32-bit AHB bus. The alignment of each access is still four bytes.
+
+[[section-memory-ordering]]
+=== Memory Ordering for Loads and Stores
+
+Hazard3 is sequentially consistent for loads and stores when it is connected to a sequentially consistent memory subsystem. Equivalently, if a load/store A is before another load/store B in program order, then A issues before B on the core's AHB5 load/store interface. Architecturally this is a (stronger) subset of the RVTSO memory model.
+
+When executing a `fence` instruction, the core waits for all earlier loads and stores to complete before raising the `fence_d_vld` signal, then waits for `fence_rdy` before issuing more loads or stores. This has no effect on the order the core issues loads and stores to the bus, as they already unconditionally issue in program order. See <<memory-ordering-signals>> for more information about the core's external fence signals.
+
+If a core A executes a `fence` and core B also executes a `fence` at a later time, the memory subsystem must perform any necessary synchronisation to ensure A's load/store accesses issued before A's fence are observed by B's load/store accesses issued after B's fence. Hazard3 does not distinguish different types of data fences: all fences should be treated as `fence rwio, rwio`.
+
+The core is guaranteed not to issue any load or store accesses while `fence_d_vld` is asserted. For a two-ported implementation this is a good opportunity for system hardware to manipulate any logic such as cache controllers attached to the core's load/store port. No such guarantee is made for instruction fetch, so in a single-ported implementation you cannot assume based on `fence_d_vld` that the AHB5 port is idle.
+
+=== Memory Ordering for Instruction Fetch
+
+Hazard3 does not order stores before instruction fetch except with an explicit `fence.i` instruction. This instruction waits for in-progress stores to complete, asserts `fence_i_vld`, waits for `fence_rdy`, and then flushes the prefetch buffer to ensure the next instruction data to be executed is fetched after the instruction fence was observed by the system. It is up to the system designer to ensure that the instruction fetch AHB5 port observes earlier writes from the load/store AHB5 port; this may require flushing of external caches.
+
+In system implementations which lack core-local caches it is usually sufficient to ignore the `fence_i_vld` and `fence_d_vld` signals, and tie `fence_rdy` high.
+
+=== Cacheable and Bufferable Attributes
+
+Hazard3 marks all transfers as non-cacheable and non-bufferable using `HPROT[3:2]`. These signals are tied off to constants and are not controllable by software.
+
+All loads are issued to the external bus, even if they alias with a prior store; there is no store-to-load forwarding. All stores are issued to the external bus, even if they alias with a later store; there is no dead store elimination or write merging. Stores are issued immediately to the bus without buffering inside the core.
+
+It is possible to use Hazard3 in systems with caches, but an alternative mechanism must be implemented to control cacheability of accesses. For example, implement multiple mirrors of the cached memory with attributes decoded from the address.
+
+=== Idempotency
+
+Hazard3 expects that all memory used for instruction fetch is read-idempotent. This limitation comes about because PMP execute permissions are checked at the point an instruction is _executed_, not the point it is fetched. This is a deliberate design decision that reduces the logic depth of fetch address generation logic. As a consequence it is possible to trigger reads from arbitrary addresses by jumping to them (though the data returned by that read is discarded if it lacks execute permissions).
+
+You must not permit instruction fetch from IO regions if <<param-U_MODE>> is configured, because this would allow U-mode software to cause IO read side effects on privileged registers by (fatally) jumping to an IO address. This can be enforced in one of two ways:
+
+* For a 2-port processor, do not connect instruction fetch to IO regions. This is already desirable to improve routing and logic complexity.
+
+* For a 1-port processor, filter instruction fetch from IO regions by rejecting transfers if `HPROT[0]` is `0`.
+
+This limitation does not apply to load/store; Hazard3 checks load/store addresses for PMP read/write permissions before issuing the transfer to the bus. However, idempotency is still a concern for instructions which generate multiple bus accesses, namely:
+
+* Zcmp: `cm.push`, `cm.pop`, `cm.popret`, `cm.popretz`
+* Zilsd: `ld`, `sd`
+* Zclsd: `c.ld`, `c.ldsp`, `c.sd`, `c.sdsp`
+
+An interrupt occurring mid-instruction terminates its execution immediately. When returning from the interrupt, the instruction restarts from the beginning, as there is no provision in RISC-V for saving and restoring the execution progress. Therefore each individual read or write may execute multiple times before the instruction eventually completes uninterrupted. This can cause lost or duplicated data when accessing IO regions. For this reason these instructions should be avoided when accessing non-idempotent memory.
+
+=== 64-bit Accesses
+
+Hazard3 implements the Zilsd and Zclsd extensions, which perform 64-bit loads and stores to and from pairs of registers. The register pair is always an even register plus the consecutively next higher-numbered register.
+
+64-bit loads and stores are implemented as pairs of 32-bit AHB5 transfers. Since these accesses only require 4-byte alignment, the load/store address can also be 4-byte-aligned, even though it is notionally an 8-byte transfer.
+
+The RISC-V specification does not guarantee the order in which these two writes are issued, and Hazard3 takes advantage of this to simplify fault handling. When the base address register `rs1` is an even-numbered register, the odd-numbered register in the `rd` or `rs2` pair is transferred first. Conversely, when `rs1` is an odd-numbered register, the even register in the pair is transferred first. This ensures that a fault occurring on the second half of an `ld` instruction does not modify `rs1`. It also means that a consecutively-addressed sequence of 64-bit load/stores is not necessarily consecutively addressed on the AHB5 port. When using `ld` and `sd` instructions for IO, ensure that the peripheral is not sensitive to the order of transfers.

Wren6991_Hazard3/doc/sections/configuration_and_integration.adoc

@@ -0,0 +1,805 @@
+== Configuration and Integration
+
+Hazard3 is a soft processor design distributed as HDL source files. To use it in your project you must:
+
+* Download the source files from the public git repository.
+* Configure your synthesis and simulation flows to read Hazard3 source files.
+* Select the appropriate top-level module for your bus architecture (`hazard3_cpu_1port` or `hazard3_cpu_2port`).
+* Select the appropriate configuration parameters for your use case.
+* Instantiate the top-level module, and connect or tie-off _all_ ports.
+* Instantiate any optional external components such as the Debug Module (`hazard3_dm`) and JTAG Debug Transport Module (`hazard3_jtag_dtm`).
+
+The choice of configuration depends on your requirements for performance, code density, area, maximum frequency, level of memory protection, and number of system interrupts and interrupt priority levels. <<config-parameters-section>> documents the available configuration parameters.
+
+The minimal https://github.com/Wren6991/Hazard3/blob/stable/example_soc/soc/example_soc.v[example SoC] shows a complete example of a single-ported Hazard3 core connected to SRAM, a UART, a RISC-V platform timer and external debug components.
+
+=== Hazard3 Source Files
+
+Hazard3's source is written in Verilog 2005, and is self-contained. It can be found here: https://github.com/Wren6991/Hazard3/tree/stable/hdl[github.com/Wren6991/Hazard3/blob/stable/hdl]. The file https://github.com/Wren6991/Hazard3/blob/stable/hdl/hazard3.f[hdl/hazard3.f] is a list of all the source files required to instantiate Hazard3. Hazard3 is distributed under the permissive Apache 2.0 licence; a full copy of the licence text is available in the git repository.
+
+For more information on the Verilog 2005 language, refer to standard IEEE 1364-2005.
+
+Files ending with `.vh` are preprocessor include files used by the Hazard3 source. The following two are particularly noteworthy:
+
+* https://github.com/Wren6991/Hazard3/blob/stable/hdl/hazard3_config.vh[hazard3_config.vh]: the main Hazard3 configuration header. Lists and describes Hazard3's global configuration parameters, such as ISA extension support
+* https://github.com/Wren6991/Hazard3/blob/stable/hdl/hazard3_config_inst.vh[hazard3_config_inst.vh]: a file which propagates configuration parameters through module instantiations, all the way down from Hazard3's top-level modules through the internals
+
+There are two ways to configure Hazard3 using these two files:
+
+* Directly edit the parameter defaults in `hazard3_config.vh` in your local Hazard3 checkout (and then let the top-level parameters default when instantiating Hazard3)
+* Set all configuration parameters in your Hazard3 instantiation, and let the parameters propagate down through the hierarchy
+
+The latter method is recommended for mature projects because it supports multiple distinct configurations of Hazard3 in the same system (for instance, a high-performance applications core and a low-area control-plane core). You may find the former method more convenient for quick hacking on the configuration.
+
+[[top-level-modules]]
+=== Top-level Modules
+
+Hazard3 has two top-level modules:
+
+* https://github.com/Wren6991/Hazard3/blob/stable/hdl/hazard3_cpu_1port.v[hazard3_cpu_1port]
+* https://github.com/Wren6991/Hazard3/blob/stable/hdl/hazard3_cpu_2port.v[hazard3_cpu_2port]
+
+These are both thin wrappers around the https://github.com/Wren6991/Hazard3/blob/stable/hdl/hazard3_core.v[hazard3_core] module. `hazard3_cpu_1port` has a single AHB5 bus port which is shared for instruction fetch, loads, stores and AMOs. `hazard3_cpu_2port` has two AHB5 bus ports, one for instruction fetch, and the other for loads, stores and AMOs. The 2-port wrapper has higher potential for performance, but the 1-port wrapper may be simpler to integrate, since there is no need to arbitrate multiple bus managers externally.
+
+The core module `hazard3_core` can also be instantiated directly, which may be more efficient if support for some other bus standard is desired. However, the interface of `hazard3_core` will not be documented and is not guaranteed to be stable. By instantiating this module directly you are taking on the risk that future Hazard3 releases may be incompatible with your integration.
+
+=== FPGA Synthesis
+
+Hazard3 supports FPGA synthesis using tools such as Yosys and Vivado. You should set <<param-RESET_REGFILE>> to zero, as FPGA block RAMs and LUT RAMs often do not support reset, or are limited in the types of reset they support. Setting <<param-RESET_REGFILE>> to one is likely to result in the register file being implemented with logic fabric flops, which has a significant area and frequency impact.
+
+You should synchronise the `rst_n` reset input externally. An example reset synchroniser is included in the example SoC file, but the details depend on your FPGA synthesis flow and your platform-level reset requirements.
+
+It's recommended to tie `clk` and `clk_always_on` to the exact same clock net to conserve global buffer resources. Clock gating _is_ supported on FPGA, but you must consult your toolchain documentation for the correct primitives or inference techniques.
+
+=== ASIC Synthesis
+
+Hazard3 supports ASIC synthesis using common commercial tool flows. There are no particular requirements for configuration parameters, but your choice of configuration has an impact on area and frequency. Please raise an issue https://github.com/Wren6991/Hazard3/issues[here] if you find a compatibility issue with your tools.
+
+When applying the `clk_en` clock enable signal to the `clk` input in conjunction with the Xh3power extension, you must instantiate an external clock gate cell appropriate to your platform (such as an AND-and-latch type). Do not use a behavioural AND gate to gate the clock.
+
+You must synchronise resets externally according to your STA constraints and your system-level reset strategy. Hazard3 uses an asynchronous active-low reset internally, but this can be adapted to other types by inserting an appropriate synchroniser in your core integration.
+
+==== Register File Macros
+
+Generally the register file should be synthesised. Synthesised register files offer the best portability and the most flexibility during layout. However there may be an area advantage to implementing the register file using a hard layout macro.
+
+Hazard3 supports the use of register file or SRAM macros, by modifying `hazard3_regfile_1w2r.v` to instantiate the appropriate macros. The configuration should be one of the following:
+
+* One instance: two read ports, one write port
+* Two instances: one read port, one write port, with the write ports tied together
+
+The memory dimensions are:
+
+* 32 bits wide
+* 32 rows deep (RV32I) or 16 rows deep (RV32E) -- depends on configuration of <<param-EXTENSION_E>>
+* No requirement for bit write enable
+
+When a write and a read simultaneously occur at the same address, the write must succeed. The read data in this case is don't-care.
+
+The read data from address 0 is don't-care, because the special case for register `x0` is handled in the register bypass logic. This means a full 32-row or 16-row RAM can be used.
+
+[[port-descriptions]]
+=== Interfaces (Top-level Ports)
+
+Most ports are common to the two top-level wrappers, `hazard3_cpu_1port` and `hazard3_cpu_2port`. The only difference is the number of AHB5 manager ports used to access the bus: `hazard3_cpu_1port` has a single port used for all accesses, whereas `hazard3_cpu_2port` adds a separate, dedicated port for instruction fetch.
+
+NOTE: Hazard3 adopts the convention that all signals are active-high, with the exception of the reset input `rst_n`.
+
+[[interfaces-clock-and-reset]]
+==== Clock and Reset Inputs
+
+[options="header",cols="1,1,3,4"]
+|===
+| Width | In/Out | Name | Description
+| 1          | In  | `clk`                        | Clock for all processor logic not driven by `clk_always_on`. Must be the same as the AHB5 bus clock (`HCLK`). If the Xh3power extension is configured, you should instantiate an external clock gate on this clock, controlled by the `clk_en` output.
+| 1          | In  | `clk_always_on`              | Clock for logic required to wake from a low-power state. Connect to the same clock as `clk`, but do not insert an external clock gate.
+| 1          | In  | `rst_n`                      | Active-low asynchronous reset for all processor logic. There is no internal synchroniser, so you must arrange externally for reset assertion/removal times to be met. For example, add an external reset synchroniser.
+
+When <<param-RESET_REGFILE>> is one, this input also resets the register file. You should avoid resetting the register file on FPGA, as this can prevent the register file being implemented with block RAM or LUT RAM primitives.
+|===
+
+==== Power Control Signals
+
+These signals are used in the implementation of internal sleep states as configured by the <<reg-h3.msleep>> csr. They are used only when the Xh3power extension is enabled.
+
+[options="header",cols="1,1,3,4"]
+|===
+| Width | In/Out | Name | Description
+| 1          | Out | `pwrup_req`                  | Power-up request. Disconnect if Xh3power is not configured. Part of a four-phase (Gray code) req/ack handshake for negotiating power or clocks with your system power controller. The processor releases `pwrup_req` on entering a sufficiently deep `wfi` or `h3.block` state, as configured by the `h3.msleep` CSR. It then waits for deassertion of `pwrup_ack` before taking further action.
+
+The processor asserts `pwrup_req` when it intends to wake from its low-power state. It then waits for `pwrup_ack` before fetching the first instruction from the bus.
+| 1          | In  | `pwrup_ack`                  | Power-up acknowledged. Tie back to `pwrup_req` if Xh3power is not configured, or if there is no external system power controller. The processor does not access the bus when either `pwrup_req` or `pwrup_ack` is low.
+| 1          | Out | `clk_en`                     | Control output for an external top-level clock gate on `clk`. Active-high enable. Hazard3 tolerates up to one cycle of delay between the assertion of `clk_en` and the resulting clock pulse on `clk`.
+| 1          | Out | `unblock_out`                | Pulses high when an `h3.unblock` instruction executes. Disconnect if Xh3power is not configured.
+| 1          | In  | `unblock_in`                 | A high input pulse will release a blocked `h3.block` instruction, or cause the next `h3.block` instruction to immediately fall through. Tie low if Xh3power is not configured.
+|===
+
+[[memory-ordering-signals]]
+==== Memory Ordering Signals
+
+Also see <<section-memory-ordering>> for more information on Hazard3's memory model.
+
+[options="header",cols="1,1,3,4"]
+|===
+| Width | In/Out | Name | Description
+| 1          | Out | `fence_i_vld`                | Indicates the core is executing a `fence.i` instruction. Remains asserted until `fence_rdy` goes high. Never asserted at the same time as `fence_d_vld`.
+
+The core waits for all in-progress bus accesses (load/store and instruction fetch) to complete before asserting this signal, and does not issue further instruction fetches for as long as this signal is asserted.
+
+Once `fetch_rdy` is seen high, the core flushes its prefetch buffer to order the fetch of younger instructions against the fence. It then resumes normal execution.
+
+| 1          | Out | `fence_d_vld`                | Indicates the core is executing a non-instruction fence, such as `fence rw, rw`. Remains asserted until `fence_rdy` goes high. Never asserted at the same time as `fence_i_vld`.
+
+The core waits for any in-progress load/store bus accesses to complete before asserting this signal, and does not issue further loads/stores for as long as this signal is asserted.
+| 1          | In  | `fence_rdy`                  | Signal to the core that the memory subsystem has finished processing the fence requested by `fence_i_vld` or `fence_d_vld`.
+
+If no special handling of fences is required, tie this signal high.
+|===
+
+==== Debug Module Controls
+
+All Debug Module signals should be connected to the signal with the matching name on the Hazard3 Debug Module implementation (https://github.com/Wren6991/Hazard3/blob/stable/hdl/debug/dm/hazard3_dm.v[hazard3_dm]).
+
+[options="header",cols="1,1,3,4"]
+|===
+| Width | In/Out | Name | Description
+| 1          | In  | `dbg_req_halt`               | Debugger halt request. Tie low if debug support is not configured.
+| 1          | In  | `dbg_req_halt_on_reset`      | Debugger halt-on-reset request. Tie low if debug support is not configured.
+| 1          | In  | `dbg_req_resume`             | Debugger resume request. Tie low if debug support is not configured.
+| 1          | Out | `dbg_halted`                 | Debug halted status. Asserts when the processor is halted in Debug mode. Disconnect if debug support is not configured.
+| 1          | Out | `dbg_running`                | Debug halted status. Asserts when the processor is not halted and not transitioning between halted/running states. Disconnect if debug support is not configured.
+| 32         | In  | `dbg_data0_rdata`            | Read data bus for mapping Debug Module `dmdata0` register as a CSR. Tie to zeroes if debug support is not configured.
+| 32         | Out | `dbg_data0_wdata`            | Write data bus for mapping Debug Module `dmdata0` register as a CSR. Disconnect if debug support is not configured.
+| 1          | Out | `dbg_data0_wen`              | Write data strobe for mapping Debug Module `dmdata0` register as a CSR. Disconnect if debug support is not configured.
+| 32         | In  | `dbg_instr_data`             | Instruction injection interface. Tie to zeroes if debug support is not configured.
+| 1          | In  | `dbg_instr_data_vld`         | Instruction injection interface. Tie low if debug support is not configured.
+| 1          | Out | `dbg_instr_data_rdy`         | Instruction injection interface. Disconnect if debug support is not configured.
+| 1          | Out | `dbg_instr_caught_exception` | Exception caught during Program Buffer execution. Disconnect if debug support is not configured.
+| 1          | Out | `dbg_instr_caught_ebreak`    | Breakpoint instruction caught during Program Buffer execution. Disconnect if debug support is not configured.
+|===
+
+==== Shared System Bus Access
+
+This subordinate bus port allows the standard System Bus Access (SBA) feature of the Debug Module to share bus access with the core. Alternatively, use the standalone https://github.com/Wren6991/Hazard3/blob/stable/hdl/debug/dm/hazard3_sbus_to_ahb.v[hazard3_sbus_to_ahb] adapter to provide dedicated SBA access from the Debug Module to the system bus.
+
+[options="header",cols="1,1,3,4"]
+|===
+| Width | In/Out | Name | Description
+| 32         | In  | `dbg_sbus_addr`              | Address for SBA arbitrated with this core's load/store access. Tie to zeroes if this feature is not used.
+| 1          | In  | `dbg_sbus_write`             | Write/not-Read flag for SBA arbitrated with this core's load/store access. Tie low if this feature is not used.
+| 2          | In  | `dbg_sbus_size`              | Transfer size (`0`/`1`/`2` = byte/halfword/word) for SBA arbitrated with this core's load/store access. Tie low if this feature is not used.
+| 1          | In  | `dbg_sbus_vld`               | Transfer enable signal for SBA arbitrated with this core's load/store access. Tie low if this feature is not used.
+| 1          | Out | `dbg_sbus_rdy`               | Transfer stall signal for SBA arbitrated with this core's load/store access. Disconnect if this feature is not used.
+| 1          | Out | `dbg_sbus_err`               | Bus fault signal for SBA arbitrated with this core's load/store access. Disconnect if this feature is not used.
+| 32         | In  | `dbg_sbus_wdata`             | Write data bus for SBA arbitrated with this core's load/store access. Tie to zeroes if this feature is not used.
+| 32         | Out | `dbg_sbus_rdata`             | Read data bus for SBA arbitrated with this core's load/store access. Disconnect if this feature is not used.
+|===
+
+==== Interrupt Requests
+
+All interrupts are level-sensitive and synchronous to `clk`. Asynchronous interrupts must be synchronised externally before entering the processor. You must use the ungated version of `clk` (`clk_always_on`) for synchronisation if you use the interrupt to wake from sleep states.
+
+Briefly asserting then deasserting an interrupt signal is not guaranteed to cause the processor to enter the relevant handler; the processor ignores interrupts it is not able to take at that time, for example when interrupts are disabled via `mstatus.mie`. There is also no guarantee that the processor will _not_ take such an interrupt. Peripherals and software should follow these guidelines for reliable interrupt handling:
+
+* When an interrupt is asserted, it should remain asserted until the condition which caused the interrupt is cleared. For example, an RX FIFO valid interrupt should remain asserted until the processor pops data from the FIFO.
+* Interrupt handlers should check the peripheral status at the top of the handler to see if it still requires servicing. If an interrupt is synchronised externally, it may still briefly be observed as asserted after returning from the handler, causing re-entry.
+* To avoid the previous issue, interrupt handlers should acknowledge (clear) the peripheral interrupt as soon as possible in the handler, to ensure the interrupt is seen deasserted before the processor returns from the interrupt handler.
+
+[options="header",cols="1,1,3,4"]
+|===
+| Width | In/Out | Name | Description
+| `NUM_IRQS` | In  | `irq`                        | If Xh3irq is not configured, this is the RISC-V external interrupt line (`mip.meip`) which you should connect to an external interrupt controller such as a standard RISC-V PLIC.
+
+If Xh3irq is configured, this is a vector of level-sensitive active-high system interrupt requests, which the core's internal interrupt controller can route through the `mip.meip` vector. Tie low if unused.
+| 1          | In  | `soft_irq`                   | This is the standard RISC-V software interrupt signal, `mip.msip`. It should be connected to a register accessible to M-mode software on your system bus. Tie low if unused.
+| 1          | In  | `timer_irq`                  | This is the standard RISC-V timer interrupt signal, `mip.mtip`. It should be connected to a standard RISC-V platform timer peripheral (`mtime`/`mtimecmp`) accessible to M-mode software on your system bus. Tie low if unused.
+|===
+
+[[identification-signals]]
+==== Identification Signals
+
+[options="header",cols="1,1,3,4"]
+|===
+| Width | In/Out | Name | Description
+| 32         | In  | `mhartid_val`                | Set the value of the <<reg-mhartid>> CSR, which software uses to determine on which hart it is running. Hazard3 implements one hart per core, so this is effectively a per-core identification value.
+
+At least one hart must have the value of all-zeroes.
+
+Generally you should tie this off to a unique constant value per core. Dynamic <<reg-mhartid>> is useful in scenarios such as dual-core lockstep: cores must execute identically when lockstep is engaged so their `mhartid_val` should be driven to the same value.
+| 4          | In  | `eco_version`                | Set the value of the `eco` version number in <<reg-mimpid>>.
+
+On ASIC this should be connected to metal-programmable tie cells so that it can be incremented with metal changes. The initial value should be all-zeroes. On FPGA this should be tied to all-zeroes.
+
+|===
+
+[[port-descriptions-1port]]
+==== AHB5 Signals for 1-port CPU
+
+This wrapper (`hazard3_cpu_1port`) adds a single standard AHB5 manager port. See the AMBA 5 AHB specification from Arm for definitions of these signals in the context of the bus protocol.
+
+[options="header",cols="1,1,2,5"]
+|===
+| Width | In/Out | Name | Description
+| 32 | Out | `haddr`      | Address output. AHB is always byte-addressed. Hazard3 always issues naturally-aligned accesses.
+| 1  | Out | `hwrite`     | Driven high for a write transfer, low for a read transfer.
+| 2  | Out | `htrans`     | Driven to `0` (`IDLE`) to indicate no transfer in the current address phase, and `2` (`NSEQ`) to indicate there is a transfer. Other types are not used.
+| 3  | Out | `hsize`      | Driven to `0`, `1` or `2` to indicate byte, halfword or word sized transfers respectively. Other sizes are not used.
+| 3  | Out | `hburst`     | Tied off to `0` (`SINGLE`). Hazard3 does not issue bursts.
+| 4  | Out | `hprot`      | Bits `3:2` are always `0` to indicate nonbufferable and noncacheable access.
+
+Bit `1` (privileged) is `0` for U-mode access, and `1` for M-mode and Debug-mode access.
+
+Bit `0` is `0` for instruction fetch and `1` for data access (load/store or SBA).
+| 1  | Out | `hmastlock`  | Hazard3 does not use legacy bus locking, so this bit is tied to 0.
+| 8  | Out | `hmaster`    | 8-bit manager ID. A value of `0x00` indicates access from the core (including Debug mode access via the Program Buffer), and `0x01` indicates an SBA access.
+
+Non-SBA Debug-mode load/store access can be detected by checking the `dbg_halted` status.
+| 1  | Out | `hexcl`      | Asserts high to indicate the current transfer is an Exclusive read/write as part of a read-modify-write sequence. This can be disconnected if you have not configured the A extension, or if you do not require global exclusive monitoring (for example in a single-core deployment).
+| 1  | In  | `hready`     | Negative stall signal. Assert low to indicate the current data phase continues on the next cycle.
+| 1  | In  | `hresp`      | Bus error signal. You _must_ generate the complete two-phase AHB `ERROR` response as per the AHB5 specification.
+| 1  | In  | `hexokay`    | Exclusive transfer success. Hazard3 always queries the global monitor, so tie this input *high* if you do not implement global exclusive monitoring (for example in a single-core deployment). Similarly, ensure your global monitor returns a successful status for non-shared memory regions such as tightly-coupled memories.
+| 32 | Out | `hwdata`     | Write data bus. The LSB of the bus is always aligned to a 4-byte boundary. Hazard3 drives the correct byte lanes depending on the transfer size and bits `1:0` of the address. Remaining byte lanes have undefined contents.
+| 32 | In  | `hrdata`     | Read data bus. The LSB of the bus is always aligned to a 4-byte boundary, so ensure you drive the correct byte lanes for narrow transfers.
+|===
+
+[[port-descriptions-2port]]
+==== AHB5 Signals for 2-port CPU
+
+This wrapper (`hazard3_cpu_2port`) adds two standard AHB5 manager ports, with signals prefixed `i_` for instruction and `d_` for data. See the AMBA 5 AHB specification from Arm for definitions of these signals in the context of the bus protocol.
+
+The I port only generates word-aligned word-sized read accesses. It does not use AHB5 exclusives.
+
+When shared System Bus Access (SBA) is used, the SBA bus accesses are routed through the D port.
+
+[options="header",cols="1,1,2,5"]
+|===
+4+| **Port I (Instruction)**
+| Width | In/Out | Name | Description
+| 32 | Out | `i_haddr`      | Address output. AHB is always byte-addressed. This port always issues word-aligned accesses (address bits `1:0` are zero).
+| 1  | Out | `i_hwrite`     | Always driven low to indicate a read transfer.
+| 2  | Out | `i_htrans`     | Driven to `0` (`IDLE`) to indicate no transfer in the current address phase, and `2` (`NSEQ`) to indicate there is a transfer. Other types are not used.
+| 3  | Out | `i_hsize`      | Always driven to `2` to indicate a word-sized transfer. Other sizes are not used.
+| 3  | Out | `i_hburst`     | Tied off to `0` (`SINGLE`). Hazard3 does not issue bursts.
+| 4  | Out | `i_hprot`      | Bits `3:2` are always `0` to indicate nonbufferable and noncacheable access.
+
+Bit `1` (privileged) is `0` for U-mode access, and `1` for M-mode and Debug-mode access.
+
+Bit `0` is tied to `0` to indicate instruction fetch.
+| 1  | Out | `i_hmastlock`  | Hazard3 does not use legacy bus locking, so this bit is tied to 0.
+| 8  | Out | `i_hmaster`    | 8-bit manager ID. Tied to `0x00`.
+| 1  | In  | `i_hready`     | Negative stall signal. Assert low to indicate the current data phase continues on the next cycle.
+| 1  | In  | `i_hresp`      | Bus error signal. You _must_ generate the complete two-phase AHB `ERROR` response as per the AHB5 specification.
+| 32 | Out | `i_hwdata`     | Write data bus. Tied to all-zeroes as this port is read-only.
+| 32 | In  | `i_hrdata`     | Read data bus. Valid on cycles where `i_hready` is high during non-`IDLE` data phases.
+4+| **Port D (Data)**
+| 32 | Out | `d_haddr`      | Address output. AHB is always byte-addressed. Hazard3 always issues naturally-aligned accesses.
+| 1  | Out | `d_hwrite`     | Driven high for a write transfer, low for a read transfer.
+| 2  | Out | `d_htrans`     | Driven to `0` (`IDLE`) to indicate no transfer in the current address phase, and `2` (`NSEQ`) to indicate there is a transfer. Other types are not used.
+| 3  | Out | `d_hsize`      | Driven to `0`, `1` or `2` to indicate byte, halfword or word sized transfers respectively. Other sizes are not used.
+| 3  | Out | `d_hburst`     | Tied off to `0` (`SINGLE`). Hazard3 does not issue bursts.
+| 4  | Out | `d_hprot`      | Bits `3:2` are always `0` to indicate nonbufferable and noncacheable access.
+
+Bit `1` (privileged) is `0` for U-mode access, and `1` for M-mode access.
+
+Bit `0` is tied to `1` to indicate data access (load/store or SBA).
+| 1  | Out | `d_hmastlock`  | Hazard3 does not use legacy bus locking, so this bit is tied to 0.
+| 8  | Out | `d_hmaster`    | 8-bit manager ID. A value of `0x00` indicates access from the core (including Debug-mode access via the Program Buffer), and `0x01` indicates an SBA access.
+
+Non-SBA Debug-mode load/store access can be detected by checking the `dbg_halted` status.
+| 1  | Out | `d_hexcl`      | Asserts high to indicate the current transfer is an Exclusive read/write as part of a read-modify-write sequence. This can be disconnected if you have not configured the A extension, or if you do not require global exclusive monitoring (for example in a single-core deployment).
+| 1  | In  | `d_hready`     | Negative stall signal. Assert low to indicate the current data phase continues on the next cycle.
+| 1  | In  | `d_hresp`      | Bus error signal. You _must_ generate the complete two-phase AHB `ERROR` response as per the AHB5 specification.
+| 1  | In  | `d_hexokay`    | Exclusive transfer success. Hazard3 always queries the global monitor, so tie this input _high_ if you do not implement global exclusive monitoring (for example in a single-core deployment). Similarly, ensure your global monitor returns a successful status for non-shared memory regions such as tightly-coupled memories.
+| 32 | Out | `d_hwdata`     | Write data bus. The LSB of the bus is always aligned to a 4-byte boundary. Hazard3 drives the correct byte lanes depending on the transfer size and bits `1:0` of the address. Remaining byte lanes have undefined contents.
+| 32 | In  | `d_hrdata`     | Read data bus. The LSB of the bus is always aligned to a 4-byte boundary, so ensure you drive the correct byte lanes for narrow transfers.
+|===
+
+[[config-parameters-section]]
+=== Configuration Parameters
+
+==== Reset state configuration
+
+[[param-RESET_VECTOR]]
+===== RESET_VECTOR
+
+Address of the first instruction executed after Hazard3 comes out of reset.
+
+Default value: all-zeroes.
+
+[[param-MTVEC_INIT]]
+===== MTVEC_INIT
+
+Initial value of the machine trap vector base CSR (<<reg-mtvec>>).
+
+Bits clear in <<param-MTVEC_WMASK>> will never change from this initial value.
+Bits set in <<param-MTVEC_WMASK>> can be written/set/cleared as normal.
+
+Default value: all-zeroes.
+
+==== Standard RISC-V ISA support
+
+[[param-EXTENSION_A]]
+===== EXTENSION_A
+
+Support for the A extension: atomic read/modify/write. `0` for disable, `1` for enable.
+
+Default value: `1`
+
+[[param-EXTENSION_C]]
+===== EXTENSION_C
+
+Support for the C extension: compressed (variable-width). `0` for disable, `1` for enable.
+
+C is equivalent here to the Zca extension, because Hazard3 does not implement F or D.
+
+Hazard3 supports some other extensions which use 16-bit instructions: Zcmp (<<param-EXTENSION_ZCMP>>), Zcb (<<param-EXTENSION_ZCB>>) and Zclsd (<<param-EXTENSION_ZCLSD>>). You must set <<param-EXTENSION_C>> to enable basic compressed instruction support before enabling any of these other extensions.
+
+Default value: `1`
+
+[[param-EXTENSION_E]]
+===== EXTENSION_E
+
+Implement the RV32E base extension rather than RV32I. RV32E reduces the number of integer registers from 31 to 15. Set `1` to select RV32E, `0` to select RV32I.
+
+Default value: `0`
+
+[[param-EXTENSION_M]]
+===== EXTENSION_M
+
+Support for the M extension: hardware multiply/divide/modulo. `0` for disable, `1` for enable.
+
+The exact circuit used to implement these instructions, and the resulting area and performance, depends on the following parameters: <<param-MULDIV_UNROLL>>, <<param-MUL_FAST>>, <<param-MUL_FASTER>>, and <<param-MULH_FAST>>.
+
+Default value: `1`
+
+[[param-EXTENSION_ZBA]]
+===== EXTENSION_ZBA
+
+Support for Zba address generation instructions. `0` for disable, `1` for enable.
+
+Default value: `0`
+
+[[param-EXTENSION_ZBB]]
+===== EXTENSION_ZBB
+
+Support for Zbb basic bit manipulation instructions. `0` for disable, `1` for enable.
+
+Default value: `0`
+
+[[param-EXTENSION_ZBC]]
+===== EXTENSION_ZBC
+
+Support for Zbc carry-less multiplication instructions. `0` for disable, `1` for enable.
+
+Default value: `0`
+
+[[param-EXTENSION_ZBKB]]
+===== EXTENSION_ZBKB
+
+Support for Zbkb basic bit manipulation for cryptography.
+
+Requires: <<param-EXTENSION_ZBB>> = `1`.
+
+NOTE: Since Zbb and Zbkb have a large overlap, this flag enables only those instructions which are in Zbkb but aren't in Zbb. Therefore both flags must be set for full Zbkb support.
+
+Default value: `0`
+
+[[param-EXTENSION_ZBKX]]
+===== EXTENSION_ZBKX
+
+Support for Zbkx crossbar permutation instructions. `0` for disable, `1` for enable.
+
+Default value: `0`
+
+
+[[param-EXTENSION_ZBS]]
+===== EXTENSION_ZBS
+
+Support for Zbs single-bit manipulation instructions. `0` for disable, `1` for enable.
+
+Default value: `0`
+
+[[param-EXTENSION_ZCB]]
+===== EXTENSION_ZCB
+
+Support for Zcb basic additional compressed instructions.
+
+Requires: <<param-EXTENSION_C>> = `1`, <<param-EXTENSION_M>> = `1` and <<param-EXTENSION_ZBB>> = `1`.
+
+NOTE: The RISC-V specifications state that Zcb depends on Zca; on Hazard3, Zca is synonymous with C, as the F and D extensions are not supported.
+
+NOTE: Some of the 16-bit opcodes from Zcb are compressed aliases for 32-bit opcodes from M and Zbb, which is why those extensions must also be enabled.
+
+Default value: `0`
+
+
+[[param-EXTENSION_ZCLSD]]
+===== EXTENSION_ZCLSD
+
+Support for Zclsd compressed load/store pair instructions.
+
+Requires: <<param-EXTENSION_ZILSD>> = `1` and <<param-EXTENSION_C>> = `1`.
+
+Default value: `0`
+
+[[param-EXTENSION_ZCMP]]
+===== EXTENSION_ZCMP
+Support for Zcmp push/pop and double-move instructions.
+
+Requires: <<param-EXTENSION_C>> = `1`.
+
+NOTE: The RISC-V specifications state that Zcmp depends on Zca; on Hazard3, Zca is synonymous with C, as the F and D extensions are not supported.
+
+Default value: `0`
+
+[[param-EXTENSION_ZIFENCEI]]
+===== EXTENSION_ZIFENCEI
+
+Support for the `fence.i` instruction. When the branch predictor is not present,
+this instruction is optional, since a plain branch/jump is sufficient to
+flush the instruction prefetch queue. When the branch predictor is enabled
+(<<param-BRANCH_PREDICTOR>> = 1), this instruction must be implemented.
+
+Default value: `0`
+
+[[param-EXTENSION_ZILSD]]
+===== EXTENSION_ZILSD
+
+Support for Zilsd load/store pair instructions.
+
+Hazard3 issues a 64-bit load or store instruction as two 32-bit memory accesses. Therefore this extension improves code density but does not directly improve performance.
+
+Default value: `0`
+
+[[cfg-custom-extensions]]
+==== Custom Hazard3 Extensions
+
+[[param-EXTENSION_XH3BEXTM]]
+===== EXTENSION_XH3BEXTM
+
+Custom bit manipulation instructions for Hazard3: `h3.bextm` and `h3.bextmi`. See <<extension-xh3bextm-section>>.
+
+Default value: `0`
+
+[[param-EXTENSION_XH3IRQ]]
+===== EXTENSION_XH3IRQ
+
+Custom preemptive, prioritised interrupt support. Can be disabled if an
+external interrupt controller (e.g. PLIC) is used. If disabled, and
+<<param-NUM_IRQS>> > `1`, the external interrupts are simply OR'd into
+`mip.meip`. See <<extension-xh3irq-section>>.
+
+Default value: `0`
+
+[[param-EXTENSION_XH3PMPM]]
+===== EXTENSION_XH3PMPM
+
+Enable the custom PMPCFGMx CSRs, which can enforce PMP regions in M-mode
+without locking the regions. See <<extension-xh3pmpm-section>>.
+
+Default value: `0`
+
+[[param-EXTENSION_XH3POWER]]
+===== EXTENSION_XH3POWER
+
+Custom power management controls for Hazard3. This adds the <<reg-h3.msleep>> CSR, and the `h3.block` and `h3.unblock` hint instructions. See <<extension-xh3power-section>>
+
+Default value: `0`
+
+==== CSR support
+
+NOTE: the Zicsr extension is implied by any of <<param-CSR_M_MANDATORY>>, <<param-CSR_M_TRAP>>,
+<<param-CSR_COUNTER>>.
+
+[[param-CSR_M_MANDATORY]]
+===== CSR_M_MANDATORY
+
+Bare minimum CSR support e.g. <<reg-misa>>. This flag is an absolute
+requirement for compliance with the RISC-V privileged specification. However,
+the privileged specification itself is an optional extension. Hazard3 allows
+the mandatory CSRs to be disabled to save a small amount of area in
+deeply-embedded implementations.
+
+Default value: `1`
+
+[[param-CSR_M_TRAP]]
+===== CSR_M_TRAP
+
+Include M-mode trap-handling CSRs, and enable trap support.
+
+Setting this parameter to `0` makes the core incapable of handling exceptions and interrupts. Instructions which would raise exceptions, such as illegal opcodes or unaligned load/store addresses, instead execute as NOPs.
+
+Default value: `1`
+
+[[param-CSR_COUNTER]]
+===== CSR_COUNTER
+
+Include the basic performance counters (`cycle`/`instret`) and relevant CSRs. Note that these performance counters are now in their own separate extension (Zicntr) and are no longer mandatory.
+
+Default value: `0`
+
+[[param-U_MODE]]
+===== U_MODE
+
+Support the U (user) privilege level. In U-mode, the core performs unprivileged
+bus accesses, and software's access to CSRs is restricted. Additionally, if
+the PMP is included, the core may restrict U-mode software's access to
+memory.
+
+Requires: <<param-CSR_M_TRAP>> = `1`.
+
+Default value: `0`
+
+[[param-PMP_REGIONS]]
+===== PMP_REGIONS
+
+Number of physical memory protection regions, or 0 for no PMP. PMP is more
+useful if U-mode is supported, but this is not a requirement.
+
+Hazard3 implements all PMP registers `pmpaddr0` through `pmpaddr15` and `pmpcfg0` through `pmpcfg3` if <<param-PMP_REGIONS>> is greater than zero. They are implemented in the sense that software can read and write them without trapping. However, configuration bits for regions <<param-PMP_REGIONS>> through 15 are hardwired to zero.
+
+Requires: <<param-CSR_M_TRAP>> = `1`.
+
+Default value: `0`
+
+[[param-PMP_GRAIN]]
+===== PMP_GRAIN
+
+This is the _G_ parameter in the privileged spec, which defines the
+granularity of PMP regions. Minimum PMP region size is 1 << (_G_ + 2) bytes. For example, _G_ = `3` means 32-byte protection granularity.
+
+If _G_ > 0, `pmcfg.a` cannot be set to NA4; attempting to do so will set the region to OFF instead. The _G_ LSBs of each `pmpaddr` register read back as all-zeroes when `pmpcfg.a` is set to TOR or OFF.
+
+If _G_ > 1, the _G_ - 1 LSBs of pmpaddr are read-only-1 when `pmpcfg.a` is
+NAPOT.
+
+Increasing <<param-PMP_GRAIN>> from its default value reduces the area and
+delay cost associated with the PMP unit.
+
+Default value: `0`
+
+[[param-PMP_MATCH_NAPOT]]
+===== PMP_MATCH_NAPOT
+
+PMP_MATCH_NAPOT: Enable PMP support for the NAPOT (naturally-aligned
+power-of-two) and NA4 (naturally-aligned four-byte) matching modes. When
+disabled, attempting to select these modes will set the PMP region to OFF.
+
+Default value: `1`
+
+[[param-PMP_MATCH_TOR]]
+===== PMP_MATCH_TOR
+
+PMP_MATCH_TOR: Enable PMP support for the TOR (top-of-range) matching mode.
+When disabled, attempting to select this mode will set the region to OFF.
+
+Note that NA4 and NAPOT use a separate comparator circuit from TOR
+comparisons. Setting both <<param-PMP_MATCH_NAPOT>> and
+<<param-PMP_MATCH_TOR>> incurs the area cost of both circuits. For best area
+efficiency, select the best single comparator type for your application,
+noting that TOR covers all the possibilities of NAPOT if there are no gaps
+between the regions. Also consider whether <<param-PMP_GRAIN>> can be
+increased from its default value.
+
+Default value: `0`
+
+[[param-PMP_HARDWIRED]]
+===== PMP_HARDWIRED
+
+If a bit is 1, the corresponding region's `pmpaddr` and `pmpcfg` registers are read-only, with their values fixed when the processor is instantiated. PMP_GRAIN is ignored on hardwired regions.
+
+Hardwired regions are far cheaper, both in area and comparison delay, than dynamically configurable regions.
+
+Hardwired PMP regions are a good option for setting default U-mode permissions on regions which have access controls outside of the processor, such as peripheral regions. For this case it's recommended to make hardwired regions the highest-numbered, so they can be overridden by lower-numbered dynamic
+regions.
+
+Default value: all-zeroes.
+
+[[param-PMP_HARDWIRED_ADDR]]
+===== PMP_HARDWIRED_ADDR
+
+Values of `pmpaddr` registers whose <<param-PMP_HARDWIRED>> bits are set to `1`. Has no effect on PMP regions which are not hardwired.
+
+Default value: all-zeroes.
+
+[[param-PMP_HARDWIRED_CFG]]
+===== PMP_HARDWIRED_CFG
+
+Values of `pmpcfg` registers whose <<param-PMP_HARDWIRED>> bits are set to `1`. Has no effect on PMP regions which are not hardwired.
+
+Default value: all-zeroes.
+
+[[param-DEBUG_SUPPORT]]
+===== DEBUG_SUPPORT
+
+Enable the following hardware functionality:
+
+* Support for run/halt and instruction injection from an external Debug Module,
+* Support for Debug Mode
+* Debug Mode CSRs
+* A minimal Trigger Module with an exception trigger, an interrupt trigger and an instruction count trigger (see <<section-trigger-module>>)
+
+If the Hazard3 Debug Module is also instantiated and correctly connected to
+the core, this is sufficient for debugging the core from any RISC-V-compliant
+debug host.
+
+Consider also enabling hardware breakpoints using
+<<param-BREAKPOINT_TRIGGERS>> if debugging code in read-only memory is an
+anticipated use case.
+
+Requires: <<param-CSR_M_MANDATORY>> = `1` and <<param-CSR_M_TRAP>> = `1`.
+
+Default value: `0`
+
+[[param-BREAKPOINT_TRIGGERS]]
+===== BREAKPOINT_TRIGGERS
+
+Number of hardware breakpoints. A breakpoint is implemented as a trigger that
+supports only exact execution address matches, ignoring instruction size.
+That is, a trigger which supports type=2 execute=1 (but not store/load=1,
+i.e. not a watchpoint).
+
+Requires: <<param-DEBUG_SUPPORT>> = `1`.
+
+Default value: `0`
+
+==== External interrupt support
+
+[[param-NUM_IRQS]]
+===== NUM_IRQS
+
+Number of external IRQs. Minimum 1, maximum 512. Note that if
+<<param-EXTENSION_XH3IRQ>> = `0`, the internal interrupt controller is not
+present. In this case multiple external interrupts are simply OR'd into
+`mip.meip`.
+
+Default value: `1`
+
+[[param-IRQ_PRIORITY_BITS]]
+===== IRQ_PRIORITY_BITS
+
+IRQ_PRIORITY_BITS: Number of priority bits implemented for each interrupt in
+the internal interrupt controller described in <<extension-xh3irq-section>>.
+The <<reg-h3.meipra>> array CSR configures the individual priorities.
+
+The number of distinct levels is `(1 << IRQ_PRIORITY_BITS)`. The minimum value
+is `0` (1 level), and the maximum value is `4` (16 levels).  Note that
+multiple priority levels with a large number of IRQs will have a severe effect
+on timing.
+
+Requires: <<param-EXTENSION_XH3IRQ>> = `1`.
+
+Default value: `0`
+
+[[param-IRQ_INPUT_BYPASS]]
+===== IRQ_INPUT_BYPASS
+
+Disable the input registers on the external interrupts, to reduce latency by one cycle. Can be applied on an IRQ-by-IRQ basis. Use this when the interrupt already comes straight from a register, e.g. when you have synchronised an interrupt to the processor clock from an asynchronous source; the additional register inside the processor is redundant in this case.
+
+Ignored if <<param-EXTENSION_XH3IRQ>> = `0`. In this case, when the internal interrupt controller is not present, all external IRQ inputs are OR'd together before being registered in a single flip-flop.
+
+Default value: all-zeroes (not bypassed).
+
+==== Identification Registers
+
+[[param-MVENDORID_VAL]]
+===== MVENDORID_VAL
+
+Value of the <<reg-mvendorid>> CSR. Should be either a JEDEC JEP-106-compliant vendor ID, or
+all-zeroes.
+
+Bits `31:7` store the continuation code count, and bits `6:0` are the ID. The
+parity bit is not stored.
+
+[IMPORTANT]
+====
+The number of continuation codes is _one less than_ the JEP106 bank number.
+
+For example, Raspberry Pi has an ID of `0x13` (19 decimal) in bank 10 (decimal). This has a continuation code count of 9, yielding an `mvendorid` of `0x00000493`.
+====
+
+Requires: <<param-CSR_M_MANDATORY>> = `1`.
+
+Default value: all-zeroes.
+
+[[param-MCONFIGPTR_VAL]]
+===== MCONFIGPTR_VAL
+
+Value of the <<reg-mconfigptr>> CSR. Pointer to configuration structure blob,
+or all-zeroes. Must be at least 4-byte-aligned.
+
+Requires: <<param-CSR_M_MANDATORY>> = `1`.
+
+Default value: all-zeroes.
+
+==== Performance/size options
+
+[[param-REDUCED_BYPASS]]
+===== REDUCED_BYPASS
+
+Remove all forwarding paths except X->X (so back-to-back ALU ops can still run
+at 1 CPI), to save area. This has a significant impact on per-clock
+performance, so should only be considered for extremely low-area
+implementations.
+
+Default value: `0`
+
+[[param-MULDIV_UNROLL]]
+===== MULDIV_UNROLL
+
+Configure bits-per-clock for the sequential multiply/divide circuit, if present. Must be a power of 2.
+
+Default value: `1`
+
+[[param-MUL_FAST]]
+===== MUL_FAST
+
+Use a single-cycle multiply circuit for `MUL` instructions, retiring to stage 3 by default (one throughput cycle, two latency cycles).
+
+The sequential multiply/divide circuit is still used for `mulh`, `mulhu` and `mulhsu`.
+
+Default value: `0`
+
+[[param-MUL_FASTER]]
+===== MUL_FASTER
+
+Retire fast multiply results to stage 2 instead of stage 3.
+The throughput is the same, but latency is reduced from 2 cycles to 1 cycle.
+
+Requires: <<param-MUL_FAST>> = `1`.
+
+Default value: `0`
+
+[[param-MULH_FAST]]
+===== MULH_FAST
+
+Extend the fast multiply circuit to also cover `mulh`, `mulhu` and `mulhsu`. Removethe multiply functionality from the sequential multiply/divide circuit.
+
+Requires: <<param-MUL_FAST>> = `1`.
+
+Default value: `0`
+
+[[param-FAST_BRANCHCMP]]
+===== FAST_BRANCHCMP
+
+Instantiate a separate comparator (equal, less-than-signed, less-than-unsigned) for branch comparisons, rather
+than using the ALU. Enabling the separate comparator improves the address-phase timing for instruction fetch, especially if the `Zba`
+extension is enabled (<<param-EXTENSION_ZBA>>). Disabling may save area.
+
+Default value: `1`
+
+[[param-RESET_REGFILE]]
+===== RESET_REGFILE
+
+If `1`, the `rst_n` input resets all general purpose registers to all-zeroes. If `0`, it does not. There are around 1k
+bits in the register file, so the reset can be disabled to permit
+block RAM and LUT RAM inference on FPGA, or to reduce flop area on ASIC.
+
+Outside of the register file, all other flops in Hazard3 are always reset by the `rst_n` input, no matter the value of this parameter.
+
+Default value: `1`
+
+[[param-BRANCH_PREDICTOR]]
+===== BRANCH_PREDICTOR
+
+Enable branch prediction. The branch predictor consists of a single BTB entry which is allocated on a taken backward branch, and cleared on a mispredicted non-taken branch, a `fence.i` or a trap.
+
+Successful prediction eliminates the 1-cyle fetch bubble on a taken branch, so tight loops execute faster. See <<instruction-timings-branch-predictor>> for more information on this feature.
+
+Requires: <<param-EXTENSION_ZIFENCEI>> = `1`.
+
+Default value: `0`
+
+[[param-MTVEC_WMASK]]
+===== MTVEC_WMASK
+
+MTVEC_WMASK: Mask of which bits in mtvec are writable. Full writability (except for bit 1) is
+recommended, because a common idiom in setup code is to set mtvec just
+past code that may trap, as a hardware `try {...} catch` block.
+
+
+The vectoring mode, in bits `1:0`, can be made fixed by clearing the LSB of `MTVEC_WMASK`.
+
+In vectored mode, the vector table must be aligned to its size, rounded up to a power of two. If all four standard M-mode vectors (exception, `msip`, `mtip` and `meip`) are in use, this means 64-byte alignment.
+
+Default: All writable except for bit `1`.

Wren6991_Hazard3/doc/sections/csr.adoc

@@ -0,0 +1,1009 @@
+== CSRs
+
+The RISC-V privileged specification affords flexibility as to which CSRs are implemented, and how they behave. This section documents the concrete behaviour of Hazard3's standard and nonstandard M-mode CSRs, as implemented.
+
+All CSRs are 32-bit; MXLEN is fixed at 32 bits on Hazard3. All CSR addresses not listed in this section are unimplemented. Accessing an unimplemented CSR will cause an illegal instruction exception (`mcause` = 2). This includes all U-mode and S-mode CSRs.
+
+
+IMPORTANT: The https://github.com/riscv/riscv-isa-manual/releases/download/Priv-v1.12/riscv-privileged-20211203.pdf[RISC-V Privileged Specification] should be your primary reference for writing software to run on Hazard3. This section specifies those details which are left implementation-defined by the RISC-V Privileged Specification, for sake of completeness, but portable RISC-V software should not rely on these details.
+
+=== Standard M-mode Identification CSRs
+
+[[reg-mvendorid]]
+==== mvendorid
+
+Address: `0xf11`
+
+Vendor identifier. Read-only, configurable constant. Should contain either all-zeroes, or a valid JEDEC JEP106 vendor ID using the encoding in the RISC-V specification. The <<param-MVENDORID_VAL>> parameter sets the value.
+
+[cols="10h,20h,~", options="header"]
+|===
+| Bits | Name | Description
+| 31:7 | `bank` | The number of continuation codes in the vendor JEP106 ID. _One less than the JEP106 bank number._
+| 6:0 | `offset` | Vendor ID within the specified bank. LSB (parity) is not stored.
+|===
+
+==== marchid
+
+Address: `0xf12`
+
+Architecture identifier for Hazard3. Read-only, constant.
+
+[cols="10h,20h,~", options="header"]
+|===
+| Bits | Name | Description
+| 31 | - | 0: Open-source implementation
+| 30:0 | - | 0x1b (decimal 27): the https://github.com/riscv/riscv-isa-manual/blob/master/marchid.md[registered] architecture ID for Hazard3
+|===
+
+[[reg-mimpid]]
+==== mimpid
+
+Address: `0xf13`
+
+Implementation identifier. Most of this register is hardwired to indicate the release version of the Hazard3 RTL.
+
+[cols="10h,20h,~", options="header"]
+|===
+| Bits   | Name       | Description
+| 31     | `prerelease` | Value of 1 indicates this Hazard3 instance was synthesised from RTL not yet released to the `stable` branch.
+| 30:28  | -          | RES0
+| 27:24  | `major`    | Major release version, i.e. the `1` in `v1.2.3`
+| 23:16  | `minor`    | Minor release version, i.e. the `2` in `v1.2.3`
+| 15:8   | `patch`    | Patch version, i.e. the `3` in `v1.2.3`
+| 7:4    | `eco`      | Connected to external signals, initially zero
+| 3:0    | -          | RES0
+|===
+
+This should match the version of the Github release of the processor's source code. For example, version https://github.com/Wren6991/Hazard3/releases/tag/v1.0.2[1.0.2] would have a `major` of 1, `minor` of 0 and `patch` of 2.
+
+`eco` is connected to the `eco_version` input port at Hazard3 top level; the implementer may connect this to metal tie cells in their integration so that they can increment the ECO (engineering change order) number with metal revisions that affect the processor, or may simply tie it to 0. See <<identification-signals>>.
+
+NOTE: Versions of Hazard3 older than v1.1 allowed the implementer to set the `mimpid` contents arbitrarily, with a recommendation to set it to the git hash. The hashes of released versions are: `86fc4e3f` (RP2350, v1.0-rc1), `918aaee10` (v1.0), `82729101` (v1.0.1) and `787da131a` (v1.0.2).
+
+[[reg-mhartid]]
+==== mhartid
+
+Address: `0xf14`
+
+Hart identification register. Read-only.
+
+The value of this register is configured by the `mhartid_val` input port (see <<identification-signals>>). In a correctly configured system, the value of `mhartid` is unique on each hart, and one hart has an ID of all-zeroes. There is no strict requirement to assign hart IDs consecutively, but there may be performance or memory usage advantages to doing so on certain operating systems.
+
+[cols="10h,20h,~", options="header"]
+|===
+| Bits | Name | Description
+| 31:0 | - | Hazard3 cores possess only one hardware thread, so this is a unique per-core identifier.
+|===
+
+[[reg-mconfigptr]]
+==== mconfigptr
+
+Address: `0xf15`
+
+Pointer to configuration data structure. Read-only, configurable constant.
+
+[cols="10h,20h,~", options="header"]
+|===
+| Bits | Name | Description
+| 31:0 | - | Either pointer to configuration data structure, containing information about the harts and system, or all-zeroes. At least 4-byte-aligned.
+|===
+
+[[reg-misa]]
+==== misa
+
+Address: `0x301`
+
+Read-only, constant. Value depends on which ISA extensions Hazard3 is configured with. The table below lists the fields which are _not_ always hardwired to 0:
+
+[cols="10h,20h,~", options="header"]
+|===
+| Bits | Name | Description
+| 31:30 | `mxl` | Always `0x1`. Indicates this is a 32-bit processor.
+| 23 | `x` | Always 1 to indicate presence of <<extension-xh3misa-section>>, and possibly other custom extensions.
+| 20 | `u` | 1 if User mode is supported, otherwise 0.
+| 12 | `m` | 1 if the M extension is present (<<param-EXTENSION_M>> is `1`)
+| 8 | `i` | 1 if the base ISA is RV32I (<<param-EXTENSION_E>> is `0`)
+| 4 | `e` | 1 if the base ISA is RV32E (<<param-EXTENSION_E>> is `1`)
+| 2 | `c` | 1 if the C extension is present (<<param-EXTENSION_C>> is `1`)
+| 1 | `b` | 1 if Zba, Zbb and Zbs are all present (<<param-EXTENSION_ZBA>>, <<param-EXTENSION_ZBB>> and <<param-EXTENSION_ZBS>> are `1`)
+| 0 | `a` | 1 if the A extension is present (<<param-EXTENSION_A>> is `1`)
+|===
+
+=== Standard M-mode Trap Handling CSRs
+
+==== mstatus
+
+Address: `0x300`
+
+The below table lists the fields which are _not_ hardwired to 0:
+
+[cols="10h,20h,~", options="header"]
+|===
+| Bits | Name | Description
+| 21    | `tw`  | Timeout wait. Only present if U-mode is supported. When 1, attempting to execute a WFI instruction in U-mode will instantly cause an illegal instruction exception.
+| 17    | `mprv` | Modify privilege. Only present if U-mode is supported. If 1, loads and stores behave as though the current privilege level were `mpp`. This includes physical memory protection checks, and the privilege level asserted on the system bus alongside the load/store address.
+| 12:11 | `mpp` | Previous privilege level. If U-mode is supported, this register can store the values 3 (M-mode) or 0 (U-mode). Otherwise, only 3 (M-mode). If another value is written, hardware rounds to the nearest supported mode.
+| 7 | `mpie` | Previous interrupt enable. Readable and writable. Is set to the current value of `mstatus.mie` on trap entry. Is set to 1 on trap return.
+| 3 | `mie` | Interrupt enable. Readable and writable. Is set to 0 on trap entry. Is set to the current value of `mstatus.mpie` on trap return.
+|===
+
+==== mstatush
+
+Address: `0x310`
+
+Hardwired to `0`.
+
+
+==== medeleg
+
+Address: `0x302`
+
+Unimplemented, as neither U-mode traps nor S-mode are supported. Access will cause an illegal instruction exception.
+
+==== mideleg
+
+Address: `0x303`
+
+Unimplemented, as neither U-mode traps nor S-mode are supported. Access will cause an illegal instruction exception.
+
+==== mie
+
+Address: `0x304`
+
+Interrupt enable register. This is not to be confused with `mstatus.mie`, which is a global enable, and has the final say in whether any interrupt which is both enabled in `mie` and pending in `mip` will actually cause the processor to transfer control to a handler.
+
+The table below lists the fields which are _not_ hardwired to 0:
+
+[cols="10h,20h,~", options="header"]
+|===
+|Bits | Name | Description
+| 11 | `meie` | External interrupt enable. Hazard3 has internal custom CSRs to further filter external interrupts, see <<reg-h3.meiea>>.
+| 7 | `mtie` | Timer interrupt enable. A timer interrupt is requested when `mie.mtie`, `mip.mtip` and `mstatus.mie` are all 1.
+| 3 | `msie` | Software interrupt enable. A software interrupt is requested when  `mie.msie`, `mip.mtip` and `mstatus.mie` are all 1.
+|===
+
+NOTE: RISC-V reserves bits 16+ of `mie`/`mip` for platform use, which Hazard3 could use for external interrupt control. On RV32I this could only control 16 external interrupts, so Hazard3 instead adds nonstandard interrupt enable registers starting at <<reg-h3.meiea>>, and keeps the upper half of `mie` reserved.
+
+[[reg-mip]]
+==== mip
+
+Address: `0x344`
+
+Interrupt pending register. Read-only.
+
+NOTE: The RISC-V specification lists `mip` as a read-write register, but the bits which are writable correspond to lower privilege modes (S- and U-mode) which are not implemented on Hazard3, so it is documented here as read-only.
+
+The table below lists the fields which are _not_ hardwired to 0:
+
+[cols="10h,20h,~", options="header"]
+|===
+|Bits | Name | Description
+| 11 | `meip` | External interrupt pending. When 1, indicates there is at least one interrupt which is asserted (hence pending in <<reg-h3.meipa>>) and enabled in <<reg-h3.meiea>>.
+| 7 | `mtip` | Timer interrupt pending. Level-sensitive interrupt signal from outside the core. Connected to a standard, external RISC-V 64-bit timer.
+| 3 | `msip` | Software interrupt pending. In spite of the name, this is not triggered by an instruction on this core, rather it is wired to an external memory-mapped register to provide a cross-hart level-sensitive doorbell interrupt.
+|===
+
+[[reg-mtvec]]
+==== mtvec
+
+Address: `0x305`
+
+Trap vector base address. Read-write. Exactly which bits of `mtvec` can be modified (possibly none) is configurable when instantiating the processor, but by default the entire register is writable. The reset value of `mtvec` is also configurable.
+
+[cols="10h,20h,~", options="header"]
+|===
+|Bits | Name | Description
+| 31:2 | `base` | Base address for trap entry. In Vectored mode, this is _OR'd_ with the trap offset to calculate the trap entry address, so the table must be aligned to its total size, rounded up to a power of 2. In Direct mode, `base` is word-aligned.
+| 0 | `mode` | 0 selects Direct mode -- all traps (whether exception or interrupt) jump to `base`. 1 selects Vectored mode -- exceptions go to `base`, interrupts go to `base \| mcause << 2`.
+|===
+
+NOTE: In the RISC-V specification, `mode` is a 2-bit write-any read-legal field in bits 1:0. Hazard3 implements this by hardwiring bit 1 to 0.
+
+[[reg-mscratch]]
+==== mscratch
+
+Address: `0x340`
+
+Read-write 32-bit register. No specific hardware function -- available for software to swap with a register when entering a trap handler.
+
+[[reg-mepc]]
+==== mepc
+
+Address: `0x341`
+
+Exception program counter. When entering a trap, the current value of the program counter is recorded here. When executing an `mret`, the processor jumps to `mepc`. Can also be read and written by software.
+
+On Hazard3, bits 31:2 of `mepc` are capable of holding all 30-bit values. Bit 1 is writable only if the C extension is implemented, and is otherwise hardwired to 0. Bit 0 is hardwired to 0, as per the specification.
+
+All traps on Hazard3 are precise. For example, a load/store bus error will set `mepc` to the exact address of the load/store instruction which encountered the fault.
+
+[[reg-mcause]]
+==== mcause
+
+Address: `0x342`
+
+Exception cause. Set when entering a trap to indicate the reason for the trap. Readable and writable by software.
+
+NOTE: On Hazard3, most bits of `mcause` are hardwired to 0. Only bit 31, and enough least-significant bits to index all exception and all interrupt causes (at least four bits), are backed by registers. Only these bits are writable; the RISC-V specification only requires that `mcause` be able to hold all legal cause values.
+
+The most significant bit of `mcause` is set to 1 to indicate an interrupt cause, and 0 to indicate an exception cause. The following interrupt causes may be set by Hazard3 hardware:
+
+[cols="10h,~", options="header"]
+|===
+| Cause | Description
+| 3 | Software interrupt (`mip.msip`)
+| 7 | Timer interrupt (`mip.mtip`)
+| 11 | External interrupt (`mip.meip`)
+|===
+
+The following exception causes may be set by Hazard3 hardware:
+
+[cols="10h,~", options="header"]
+|===
+| Cause | Description
+| 0 | Instruction address misaligned
+| 1 | Instruction access fault
+| 2 | Illegal instruction
+| 3 | Breakpoint
+| 4 | Load address misaligned
+| 5 | Load access fault
+| 6 | Store/AMO address misaligned
+| 7 | Store/AMO access fault
+| 8 | Environment call from U-mode
+| 11 | Environment call from M-mode
+|===
+
+==== mtval
+
+Address: `0x343`
+
+Hardwired to 0.
+
+==== mcounteren
+
+Address: `0x306`
+
+Counter enable. Control access to counters from U-mode. Not to be confused with <<reg-mcountinhibit>>.
+
+This register only exists if U-mode is supported.
+
+[cols="10h,20h,~", options="header"]
+|===
+|Bits | Name | Description
+| 31:3 | -    | RES0
+| 2    | `ir` | If 1, U-mode is permitted to access the `instret`/`instreth` instruction retire counter CSRs. Otherwise, U-mode accesses to these CSRs will trap.
+| 1    | `tm` | No hardware effect, as the `time`/`timeh` CSRs are not implemented. However, this field still exists, as M-mode software can use it to track whether it should emulate U-mode attempts to access those CSRs.
+| 0   | `cy`  |If 1, U-mode is permitted to access the `cycle`/`cycleh` cycle counter CSRs. Otherwise, U-mode accesses to these CSRs will trap.
+|===
+
+=== Standard Memory Protection CSRs
+
+==== pmpcfg0...3
+
+Address: `0x3a0` through `0x3a3`
+
+Configuration registers for up to 16 physical memory protection regions. Only present if PMP support is configured. If so, all 4 registers are present, but some registers may be partially/completely hardwired depending on the number of PMP regions present.
+
+By default, M-mode has full permissions (RWX) on all of memory, and U-mode has no permissions. A PMP region can be configured to alter this default within some range of addresses. For every memory location executed, loaded or stored, the processor looks up the _lowest active region_ that overlaps that memory location, and applies its permissions to determine whether this access is allowed. The full description can be found in the RISC-V privileged ISA manual.
+
+Each `pmpcfg` register divides into four identical 8-bit chunks, each corresponding to one region, and laid out as below:
+
+[cols="10h,20h,~", options="header"]
+|===
+|Bits | Name | Description
+| 7   | `L` | Lock region, and additionally enforce its permissions on M-mode as well as U-mode.
+| 6:5 | -   | RES0
+| 4:3 | `A` | Address-matching mode. Values supported are 0 (OFF), 2 (NA4, naturally aligned 4-byte) and 3 (NAPOT, naturally aligned power-of-two). 1 (TOR, top of range) is not supported. Attempting to write an unsupported value will set the region to OFF.
+| 2    | `X` | Execute permission
+| 1    | `W` | Write permission
+| 0    | `R` | Read permission
+|===
+
+==== pmpaddr0...15
+
+Address: `0x3b0` through `0x3bf`
+
+Address registers for up to 16 physical memory protection regions. Only present if PMP support is configured. If so, all 16 registers are present, but some may fully/partially hardwired.
+
+`pmpaddr` registers express addresses in units of 4 bytes, so on Hazard3 (a 32-bit processor with no virtual address support) only the lower 30 bits of each address register are implemented.
+
+The interpretation of the `pmpaddr` bits depends on the `A` mode configured in the corresponding `pmpcfg` register field:
+
+* For NA4, the entire 30-bit PMP address is matched against the 30 MSBs of the checked address.
+* For NAPOT, `pmpaddr` bits up to and including the least-significant zero bit are ignored, and the remaining bits are matched against the MSBs of the checked address.
+
+=== Standard M-mode Performance Counters
+
+==== mcycle
+
+Address: `0xb00`
+
+Lower half of the 64-bit cycle counter. Readable and writable by software. Increments every cycle, unless `mcountinhibit.cy` is 1, or the processor is in Debug Mode (as <<reg-dcsr>>.`stopcount` is hardwired to 1).
+
+If written with a value `n` and read on the very next cycle, the value read will be exactly `n`. The RISC-V spec says this about `mcycle`: "Any CSR write takes effect after the writing instruction has otherwise completed."
+
+==== mcycleh
+
+Address: `0xb80`
+
+Upper half of the 64-bit cycle counter. Readable and writable by software. Increments on cycles where `mcycle` has the value `0xffffffff`, unless `mcountinhibit.cy` is 1, or the processor is in Debug Mode.
+
+This includes when `mcycle` is written on that same cycle, since RISC-V specifies the CSR write takes place _after_ the increment for that cycle.
+
+==== minstret
+
+Address: `0xb02`
+
+Lower half of the 64-bit instruction retire counter. Readable and writable by software. Increments with every instruction executed, unless `mcountinhibit.ir` is 1, or the processor is in Debug Mode (as <<reg-dcsr>>.`stopcount` is hardwired to 1).
+
+If some value `n` is written to `minstret`, and it is read back by the very next instruction, the value read will be exactly `n`. This is because the CSR write logically takes place after the instruction has otherwise completed.
+
+==== minstreth
+
+Address: `0xb82`
+
+Upper half of the 64-bit instruction retire counter. Readable and writable by software. Increments when the core retires an instruction and the value of `minstret` is `0xffffffff`, unless `mcountinhibit.ir` is 1, or the processor is in Debug Mode.
+
+==== mhpmcounter3...31
+
+Address: `0xb03` through `0xb1f`
+
+Hardwired to 0.
+
+==== mhpmcounter3...31h
+
+Address: `0xb83` through `0xb9f`
+
+Hardwired to 0.
+
+
+[[reg-mcountinhibit]]
+==== mcountinhibit
+
+Address: `0x320`
+
+Counter inhibit. Read-write. The table below lists the fields which are _not_ hardwired to 0:
+
+[cols="10h,20h,~", options="header"]
+|===
+| Bits | Name | Description
+| 2 | `ir` | When 1, inhibit counting of `minstret`/`minstreth`. Resets to 1.
+| 0 | `cy` | When 1, inhibit counting of `mcycle`/`mcycleh`. Resets to 1.
+|===
+
+==== mhpmevent3...31
+
+Address: `0x323` through `0x33f`
+
+Hardwired to 0.
+
+=== Standard Trigger CSRs
+
+Trigger CSRs control Hazard3's trigger module, described in <<section-trigger-module>>. They are implemented if <<param-DEBUG_SUPPORT>> = `1`, and otherwise raise illegal instruction exceptions when accessed.
+
+[[reg-tselect]]
+==== tselect
+
+Address: `0x7a0`
+
+Select a trigger for configuration. The selected trigger is described in <<reg-tinfo>> and can be configured through <<reg-tdata1>> and <<reg-tdata2>>. See <<section-trigger-module>> for an overview of Hazard3's trigger capabilities.
+
+This register implements exactly enough bits to index the configured number of triggers. Remaining bits are hardwired to zero.
+
+[[reg-tdata1]]
+==== tdata1
+
+Address: `0x7a1`
+
+Configure the trigger selected by <<reg-tselect>>.
+
+[cols="10h,20h,~", options="header"]
+|===
+| Bits | Name | Description
+| 31:28 | `type` a| On Hazard3 this field is hardwired for a given value of <<reg-tselect>>:
+
+* `0`: no trigger
+* `2`: address/data match
+* `3`: instruction count
+* `4`: interrupt
+* `5`: exception
+
+| 27 | `dmode` | Claim this trigger for Debug Mode use. Only writable by Debug Mode. When set to 1, other modes cannot write to `tdata*` registers for this trigger. This bit must be set to enable Debug Mode entry from a trigger (`action` = `1`).
+
+Hazard3 hardwires this field to zero for the instruction count trigger, which only supports breaking to M-mode. It has normal read/write behaviour for other trigger types.
+|===
+
+The layout of bits `26:0` of this register depends on the value of `type`.
+
+[[reg-mcontrol]]
+===== mcontrol
+
+`mcontrol` is the alias for `tdata1` when `type` is `2` (address/data match trigger). Hazard3 implements only exact instruction address match (breakpoints).
+
+[cols="10h,20h,~", options="header"]
+|===
+| Bits | Name | Description
+| 26:21 | `maskmax` | Hardwired to zero; only exact matches are supported
+| 20 | `hit` | Hardwired to zero; this feature is not implemented
+| 19 | `select` | Hardwired to zero; only address matching is supported (not data matching)
+| 18 | `timing` | Hardwired to zero; the breakpoint takes place before the matching instruction executes (but after all earlier instructions in program order are observed to have completed)
+| 17:16 | `sizelo` | Hardwired to zero; all instruction sizes are matched
+| 15:12 | `action` | Supports the values `0` (break to M-mode `ebreak` exception handler) and `1` (break to Debug Mode). Bits 15:13 are hardwired to zero.
+
+An `action` of `0` is ignored when `tcontrol.mte` is `0`. An `action` of `1` is ignored when `tdata1.dmode` is `0`.
+| 11 | `chain` | Hardwired to zero; chaining is not supported
+| 10:7 | `match` | Hardwired to zero; match is always on the exact address
+| 6 | `m` | Write 1 to enable matching during M-mode execution
+| 3 | `u` | Write 1 to enable matching during U-mode execution. Hardwired to zero if <<param-U_MODE>> = `0`.
+| 2 | `execute` | Write 1 to enable matching on instruction addresses
+| 1 | `store` | Hardwired to zero; store address/data matching is not supported
+| 0 | `load` | Hardwired to zero; load address/data matching is not supported
+|===
+
+[[reg-icount]]
+===== icount
+
+`icount` is the alias for `tdata1` when `type` is `3` (instruction count trigger).
+
+[cols="10h,20h,~", options="header"]
+|===
+| Bits | Name | Description
+| 24 | `hit` | Hardwired to zero; this feature is not implemented
+| 23:10 | `count` | Hardwired to `1`; only single-stepping is supported
+| 9 | `m` | Write 1 to enable matching during M-mode execution, if `tcontrol.mte` is also set. Self-clears when this trigger fires (in any privilege mode).
+| 6 | `u` | Write 1 to enable matching during U-mode execution. Hardwired to zero if <<param-U_MODE>> = `0`. Self-clears when this trigger fires (in any privilege mode).
+| 5:0 | `action` | Hardwired to `0`; this trigger only supports breaking to M-mode with an exception cause of `3` (`ebreak`). The corresponding Debug Mode functionality is already provided by `dcsr.step`.
+|===
+
+See <<section-icount-trigger>> for more information about this trigger's behaviour on Hazard3.
+
+[[reg-itrigger]]
+===== itrigger
+
+`itrigger` is the alias for `tdata1` when `type` is `4` (interrupt trigger).
+
+[cols="10h,20h,~", options="header"]
+|===
+| Bits | Name | Description
+| 24 | `hit` | Hardwired to zero; this feature is not implemented
+| 9 | `m` | Write 1 to enable matching during M-mode execution, if `tcontrol.mte` is also set.
+| 6 | `u` | Write 1 to enable matching during U-mode execution. Hardwired to zero if <<param-U_MODE>> = `0`.
+| 5:0 | `action` | Hardwired to `1`; this trigger only supports breaking to Debug Mode (as an M-mode breakpoint exception triggered immediately after M-mode interrupt entry would be unrecoverable).
+|===
+
+See <<section-interrupt-trigger>> for more information about this trigger's behaviour on Hazard3.
+
+[[reg-etrigger]]
+===== etrigger
+
+`etrigger` is the alias for `tdata1` when `type` is `5` (exception trigger).
+
+[cols="10h,20h,~", options="header"]
+|===
+| Bits | Name | Description
+| 24 | `hit` | Hardwired to zero; this feature is not implemented
+| 9 | `m` | Write 1 to enable matching during M-mode execution, if `tcontrol.mte` is also set.
+| 6 | `u` | Write 1 to enable matching during U-mode execution. Hardwired to zero if <<param-U_MODE>> = `0`.
+| 5:0 | `action` | Hardwired to `1`; this trigger only supports breaking to Debug Mode (as an M-mode breakpoint exception triggered immediately after M-mode interrupt entry would be unrecoverable).
+|===
+
+See <<section-exception-trigger>> for more information about this trigger's behaviour on Hazard3.
+
+[[reg-tdata2]]
+==== tdata2
+
+Address: `0x7a2`
+
+The interpretation of this CSR depends on the `type` field of <<reg-tdata1>>:
+
+[horizontal]
+`type` = `2`:: Address/data trigger: `tdata2` contains the address/data to be matched. On Hazard3 this is always an instruction address, and `tdata2` only implemenents enough bits to store any valid program counter (multiple of IALIGN).
+
+`type` = `3`:: Instruction count trigger: `tdata2` is hardwired to zero.
+
+`type` = `4`:: Interrupt trigger: `tdata2` contains a bitmap of the interrupt `mcause` values upon which this trigger will match. For example, setting bit `11` (value `0x800`) enables triggering on the machine external IRQ vector (`mip.meip`).
+
+`type` = `5`:: Exception trigger: `tdata2` contains a bitmap of the non-interrupt `mcause` values upon which this trigger will match. For example, setting bit `2` (value `0x4`) enables triggering on illegal instruction exceptions.
+
+[[reg-tdata3]]
+==== tdata3
+
+Address: `0x7a3`
+
+Hardwired to zero.
+
+[[reg-tinfo]]
+==== tinfo
+
+Address: `0x7a4`
+
+Lists the capabilities of the trigger currently selected by <<reg-tselect>>. This takes the form of a bitmap of values supported by `tdata1.type`. For example, bit `2` being set (a value of `0x4`) indicates the trigger supports `type` = `2`, "address/data match".
+
+[cols="10h,~", options="header"]
+|===
+| Bits | Description
+| 5 | Supports `type` = `5`, exception trigger
+| 4 | Supports `type` = `4`, interrupt trigger
+| 3 | Supports `type` = `3`, instruction count trigger
+| 2 | Supports `type` = `2`, address/data match trigger
+| 0 | Supports `type` = `0`, disabled or no trigger
+|===
+
+Hazard3 triggers support only a single `type` each. Therefore `tinfo` always has exactly one bit set, and the `tdata1.type` field is read-only.
+
+If bit `0` is set, and no other bit is set, there is no trigger corresponding to the current value of `tselect`. There are also no triggers at higher values of `tselect`; trigger enumeration terminates at this point.
+
+[[debug-csr-section]]
+=== Standard Debug Mode CSRs
+
+This section describes the Debug Mode CSRs, which follow the 0.13.2 RISC-V debug specification. The <<debug-chapter>> section gives more detail on the remainder of Hazard3's debug implementation, including the Debug Module.
+
+All Debug Mode CSRs are 32-bit; DXLEN is always 32.
+
+[[reg-dcsr]]
+==== dcsr
+
+Address: `0x7b0`
+
+Debug control and status register. Access outside of Debug Mode will cause an illegal instruction exception. Relevant fields are implemented as follows:
+
+[cols="10h,20h,~", options="header"]
+|===
+| Bits | Name | Description
+| 31:28 | `xdebugver` | Hardwired to 4: external debug support as per RISC-V 0.13.2 debug specification.
+| 15 | `ebreakm` | When 1, `ebreak` instructions executed in M-mode will break to Debug Mode instead of trapping
+| 12 | `ebreaku` | When 1, `ebreak` instructions executed in U-mode will break to Debug Mode instead of trapping. Hardwired to 0 if U-mode is not supported.
+| 11 | `stepie` | Hardwired to 0: no interrupts are taken during hardware single-stepping.
+| 10 | `stopcount` | Hardwired to 1: `mcycle`/`mcycleh` and `minstret`/`minstreth` do not increment in Debug Mode.
+| 9 | `stoptime` | Hardwired to 1: core-local timers don't increment in debug mode. This requires cooperation of external hardware based on the halt status to implement correctly.
+| 8:6 | `cause` | Read-only, set by hardware -- see table below.
+| 2 | `step` | When 1, re-enter Debug Mode after each instruction executed in M-mode.
+| 1:0 | `prv` | Read the privilege state the core was in when it entered Debug Mode, and set the privilege state it will be in when it exits Debug Mode. If U-mode is implemented, the values 3 and 0 are supported. Otherwise hardwired to 3.
+|===
+
+Fields not mentioned above are hardwired to 0.
+
+Hazard3 may set the following `dcsr.cause` values on entry to Debug Mode:
+
+[cols="10h,~", options="header"]
+|===
+| Cause | Description
+| `1` | An `ebreak` instruction executed in M-mode when `dcsr.ebreakm` was set, or U-mode when `dcsr.ebreaku` was set.
+| `2` | A trigger fired.
+| `3` | The Debug Module requested a processor halt, or a reset-halt request was present when the core reset was released.
+| `4` | The processor executed one instruction with single-stepping enabled via `dcsr.step`.
+|===
+
+Cause `5` (`resethaltreq`) is never set by hardware. This event is reported as a normal halt, cause `3`.
+
+==== dpc
+
+Address: `0x7b1`
+
+Debug program counter. When entering Debug Mode, `dpc` samples the current program counter, e.g. the address of an `ebreak` which caused Debug Mode entry. When leaving debug mode, the processor jumps to `dpc`. The host may read/write this register whilst in Debug Mode.
+
+==== dscratch0
+
+Address: `0x7b2`
+
+Not implemented. Access will cause an illegal instruction exception.
+
+To provide data exchange between the Debug Module and the core, the Debug Module's `data0` register is mapped into the core's CSR space at a read/write M-custom address -- see <<reg-dmdata0>>.
+
+==== dscratch1
+
+Address: `0x7b3`
+
+Not implemented. Access will cause an illegal instruction exception.
+
+=== Custom Debug Mode CSRs
+
+[[reg-h3.dmdata0]]
+==== h3.dmdata0
+
+Address: `0xbff`
+
+The Debug Module's internal `data0` register is mapped to this CSR address when the core is in debug mode. At any other time, access to this CSR address will cause an illegal instruction exception.
+
+NOTE: The 0.13.2 debug specification allows for the Debug Module's abstract data registers to be mapped into the core's CSR address space, but there is no Debug-custom space, so the read/write M-custom space is used instead to avoid conflict with future versions of the debug specification.
+
+The Debug Module uses this mapping to exchange data with the core by injecting `csrr`/`csrw` instructions into the prefetch buffer. This in turn is used to implement the Abstract Access Register command. See <<debug-chapter>>.
+
+This CSR address is given by the `dataaddress` field of the Debug Module's `hartinfo` register, and `hartinfo.dataaccess` is set to 0 to indicate this is a CSR mapping, not a memory mapping.
+
+=== Custom Interrupt Handling CSRs
+
+[[reg-h3.meiea]]
+==== h3.meiea
+
+Address: `0xbe0`
+
+External interrupt enable array. Contains a read-write bit for each external interrupt request: a `1` bit indicates that interrupt is currently enabled. At reset, all external interrupts are disabled.
+
+If enabled, an external interrupt can cause assertion of the standard RISC-V machine external interrupt pending flag (`mip.meip`), and therefore cause the processor to enter the external interrupt vector. See <<reg-h3.meipa>>.
+
+There are up to 512 external interrupts. The upper half of this register contains a 16-bit window into the full 512-bit vector. The window is indexed by the 5 LSBs of the write data. For example:
+
+----
+csrrs a0, meiea, a0 // Read IRQ enables from the window selected by a0
+csrw meiea, a0      // Write a0[31:16] to the window selected by a0[4:0]
+csrr a0, meiea      // Read from window 0 (edge case)
+----
+
+The purpose of this scheme is to allow software to _index_ an array of interrupt enables (something not usually possible in the CSR space) without introducing a stateful CSR index register which may have to be saved/restored around IRQs.
+
+[cols="10h,20h,~", options="header"]
+|===
+| Bits  | Name   | Description
+| 31:16 | `window` | 16-bit read/write window into the external interrupt enable array
+| 15:5  | -        | RES0
+| 4:0   | `index`  | Write-only self-clearing field (no value is stored) used to control which window of the array appears in `window`. 
+|===
+
+[[reg-h3.meipa]]
+==== h3.meipa
+
+Address: `0xbe1`
+
+External interrupt pending array. Contains a read-only bit for each external interrupt request. Similarly to `h3.meiea`, this register is a window into an array of up to 512 external interrupt flags. The status appears in the upper 16 bits of the value read from `h3.meipa`, and the lower 5 bits of the value _written_ by the same CSR instruction (or 0 if no write takes place) select a 16-bit window of the full interrupt pending array.
+
+A `1` bit indicates that interrupt is currently asserted. IRQs are assumed to be level-sensitive, and the relevant `h3.meipa` bit is cleared by servicing the requester so that it deasserts its interrupt request.
+
+When any interrupt of sufficient priority is both set in `h3.meipa` and enabled in `h3.meiea`, the standard RISC-V external interrupt pending bit `mip.meip` is asserted. In other words, `h3.meipa` is filtered by `h3.meiea` to generate the standard `mip.meip` flag. So, an external interrupt is taken when _all_ of the following are true:
+
+* An interrupt is currently asserted in `h3.meipa`
+* The matching interrupt enable bit is set in `h3.meiea`
+* The interrupt priority is greater than or equal to the preemption priority in `h3.meicontext`
+* The standard M-mode interrupt enable `mstatus.mie` is set
+* The standard M-mode global external interrupt enable `mie.meie` is set
+
+In this case, the processor jumps to either:
+
+* `mtvec` directly, if vectoring is disabled (`mtvec[0]` is 0)
+* `mtvec + 0x2c`, if vectoring is enabled (`mtvec[0]` is 1)
+
+[cols="10h,20h,~", options="header"]
+|===
+| Bits  | Name   | Description
+| 31:16 | `window` | 16-bit read-only window into the external interrupt pending array
+| 15:5  | -        | RES0
+| 4:0   | `index`  | Write-only, self-clearing field (no value is stored) used to control which window of the array appears in `window`. 
+|===
+
+[[reg-h3.meifa]]
+==== h3.meifa
+
+Address: `0xbe2`
+
+External interrupt force array. Contains a read-write bit for every interrupt request. Writing a 1 to a bit in the interrupt force array causes the corresponding bit to become pending in `h3.meipa`. Software can use this feature to manually trigger a particular interrupt.
+
+There are no restrictions on using `h3.meifa` inside of an interrupt. The more useful case here is to schedule some lower-priority handler from within a high-priority interrupt, so that it will execute before the core returns to the foreground code. Implementers may wish to reserve some external IRQs with their external inputs tied to 0 for this purpose.
+
+Bits can be cleared by software, and are cleared automatically by hardware upon a read of `h3.meinext` which returns the corresponding IRQ number in `h3.meinext.irq` (no matter whether `h3.meinext.update` is written).
+
+`h3.meifa` implements the same array window indexing scheme as `h3.meiea` and `h3.meipa`. 
+
+[cols="10h,20h,~", options="header"]
+|===
+| Bits  | Name   | Description
+| 31:16 | `window` | 16-bit read/write window into the external interrupt force array
+| 15:5  | -        | RES0
+| 4:0   | `index`  | Write-only, self-clearing field (no value is stored) used to control which window of the array appears in `window`. 
+|===
+
+[[reg-h3.meipra]]
+==== h3.meipra
+
+Address: `0xbe3`
+
+External interrupt priority array. Each interrupt has an (up to) 4-bit priority value associated with it, and each access to this register reads and/or writes a 16-bit window containing four such priority values. When less than 16 priority levels are available, the LSBs of the priority fields are hardwired to 0.
+
+When an interrupt's priority is lower than the current preemption priority `h3.meicontext.preempt`, it is treated as not being pending. The pending bit in `h3.meipa` will still assert, but the machine external interrupt pending bit `mip.meip` will not, so the processor will ignore this interrupt. See <<reg-h3.meicontext>>.
+
+[cols="10h,20h,~", options="header"]
+|===
+| Bits  | Name   | Description
+| 31:16 | `window` | 16-bit read/write window into the external interrupt priority array, containing four 4-bit priority values.
+| 15:7  | -        | RES0
+| 6:0   | `index`  | Write-only, self-clearing field (no value is stored) used to control which window of the array appears in `window`. 
+|===
+
+[[reg-h3.meinext]]
+==== h3.meinext
+
+Address: `0xbe4`
+
+Get next interrupt. Contains the index of the highest-priority external interrupt which is both asserted in `h3.meipa` and enabled in `h3.meiea`, left-shifted by 2 so that it can be used to index an array of 32-bit function pointers. If there is no such interrupt, the MSB is set.
+
+When multiple interrupts of the same priority are both pending and enabled, the lowest-numbered wins. Interrupts with priority less than `h3.meicontext.ppreempt` -- the _previous_ preemption priority -- are treated as though they are not pending. This is to ensure that a preempting interrupt frame does not service interrupts which may be in progress in the frame that was preempted.
+
+[cols="10h,20h,~", options="header"]
+|===
+| Bits  | Name     | Description
+| 31    | `noirq`  | Set when there is no external interrupt which is enabled, pending, and has sufficient priority. Can be efficiently tested with a `bltz` or `bgez` instruction.
+| 30:11 | -        | RES0
+| 10:2  | `irq`    | Index of the highest-priority active external interrupt. Zero when no external interrupts with sufficient priority are both pending and enabled.
+| 1     | -        | RES0
+| 0     | `update` | Writing 1 (self-clearing) causes hardware to update `h3.meicontext` according to the IRQ number and preemption priority of the interrupt indicated in `noirq`/`irq`. This should be done in a single atomic operation, i.e. `csrrsi a0, meinext, 0x1`.
+|===
+
+[[reg-h3.meicontext]]
+==== h3.meicontext
+
+Address: `0xbe5`
+
+External interrupt context register. Configures the priority level for interrupt preemption, and helps software track which interrupt it is currently in. The latter is useful when a common interrupt service routine handles interrupt requests from multiple instances of the same peripheral.
+
+A three-level stack of preemption priorities is maintained in the `preempt`, `ppreempt` and `pppreempt` fields. The priority stack is saved when hardware enters the external interrupt vector, and restored by an `mret` instruction if `h3.meicontext.mreteirq` is set.
+
+The top entry of the priority stack, `preempt`, is used by hardware to ensure that only higher-priority interrupts can preempt the current interrupt. The next entry, `ppreempt`, is used to avoid servicing interrupts which may already be in progress in a frame that was preempted. The third entry, `pppreempt`, has no hardware effect, but ensures that `preempt` and `ppreempt` can be correctly saved/restored across arbitrary levels of preemption.
+
+[cols="10h,20h,~", options="header"]
+|===
+| Bits  | Name        | Description
+| 31:28 | `pppreempt` | Previous `ppreempt`. Set to `ppreempt` on priority save, set to zero on priority restore.  Has no hardware effect, but ensures that when `h3.meicontext` is saved/restored correctly, `preempt` and `ppreempt` stack correctly through arbitrarily many preemption frames.
+| 27:24 | `ppreempt`  | Previous `preempt`. Set to `preempt` on priority save, restored to to `pppreempt` on priority restore.
+
+IRQs of lower priority than `ppreempt` are not visible in `h3.meinext`, so that a preemptee is not re-taken in the preempting frame.
+| 23:21 | -           | RES0
+| 20:16 | `preempt`   | Minimum interrupt priority to preempt the current interrupt. Interrupts with lower priority than `preempt` do not cause the core to transfer to an interrupt handler. Updated by hardware when when `h3.meinext.update` is written, or when hardware enters the external interrupt vector.
+
+If an interrupt is present in `h3.meinext`, then `preempt` is set to one level greater than that interrupt's priority. Otherwise, `preempt` is set to one level greater than the maximum interrupt priority, disabling preemption.
+| 15    | `noirq`     | Not in interrupt (read/write). Set to 1 at reset. Set to `h3.meinext.noirq` when `h3.meinext.update` is written. No hardware effect.
+| 14:13  | -           | RES0
+| 12:4   | `irq`       | Current IRQ number (read/write). Set to `h3.meinext.irq` when `h3.meinext.update` is written.
+| 3      | `mtiesave`  | Reads as the current value of `mie.mtie`, if `clearts` is set. Otherwise reads as 0. Writes are ORed into `mie.mtie`.
+| 2      | `msiesave`  | Reads as the current value of `mie.msie`, if `clearts` is set. Otherwise reads as 0. Writes are ORed into `mie.msie`.
+| 1      | `clearts`   | Write-1 self-clearing field. Writing 1 will clear `mie.mtie` and `mie.msie`, and present their prior values in the `mtiesave` and `msiesave` of this register. This makes it safe to re-enable IRQs (via `mstatus.mie`) without the possibility of being preempted by the standard timer and soft interrupt handlers, which may not be aware of Hazard3's interrupt hardware.
+
+The clear due to `clearts` takes precedence over the set due to `mtiesave`/`msiesave`, although it would be unusual for software to write both on the same cycle.
+| 0      | `mreteirq` | Enable restore of the preemption priority stack on `mret`. This bit is set on entering the external interrupt vector, cleared by `mret`, and cleared upon taking any trap other than an external interrupt.
+
+Provided `h3.meicontext` is saved on entry to the external interrupt vector (before enabling preemption), is restored before exiting, and the standard software/timer IRQs are prevented from preempting (e.g. by using `clearts`), this flag allows the hardware to safely manage the preemption priority stack even when an external interrupt handler may take exceptions.
+|===
+
+The following is an example of an external interrupt vector (`mip.meip`) which implements nested, prioritised interrupt dispatch using `h3.meicontext` and `h3.meinext`:
+
+----
+isr_external_irq:
+	// Save caller saves and exception return state whilst IRQs are disabled.
+	// We can't be preempted during this time, but if a higher-priority IRQ
+	// arrives ("late arrival"), that will be the one displayed in h3.meinext. 
+	addi sp, sp, -80
+	sw ra,  0(sp)
+	... snip
+	sw t6, 60(sp)
+
+	csrr a0, mepc
+	sw a0, 64(sp)
+	// Set bit 1 when reading to clear+save mie.mtie and mie.msie
+	csrrsi a0, h3.meicontext, 0x2
+	sw a0, 68(sp)
+	csrr a0, mstatus
+	sw a0, 72(sp)
+
+	j get_next_irq
+
+dispatch_irq:
+	// Preemption priority was configured by h3.meinext update, so enable preemption:
+	csrsi mstatus, 0x8
+	// h3.meinext is pre-shifted by 2, so only an add is required to index table
+	la a1, _external_irq_table
+	add a1, a1, a0
+	jalr ra, a1
+
+	// Disable IRQs on returning so we can sample the next IRQ
+	csrci mstatus, 0x8
+
+get_next_irq:
+	// Sample the current highest-priority active IRQ (left-shifted by 2) from
+	// h3.meinext, and write 1 to the LSB to tell hardware to tell hw to update
+	// h3.meicontext with the preemption priority (and IRQ number) of this IRQ
+	csrrsi a0, h3.meinext, 0x1
+	// MSB will be set if there is no active IRQ at the current priority level
+	bgez a0, dispatch_irq
+
+no_more_irqs:
+	// Restore saved context and return from handler
+	lw a0, 64(sp)
+	csrw mepc, a0
+	lw a0, 68(sp)
+	csrw h3.meicontext, a0
+	lw a0, 72(sp)
+	csrw mstatus, a0
+
+	lw ra,  0(sp)
+	... snip
+	lw t6, 60(sp)
+	addi sp, sp, 80
+	mret
+----
+
+=== Custom Memory Protection CSRs
+
+[[reg-h3.pmpcfgm0]]
+==== h3.pmpcfgm0
+
+Address: 0xbd0
+
+PMP M-mode configuration. One bit per PMP region. Setting a bit makes the corresponding region apply to M-mode (like the `pmpcfg.L` bit) but does not lock the region.
+
+PMP is useful for non-security-related purposes, such as stack guarding and peripheral emulation. This extension allows M-mode to freely use any currently unlocked regions for its own purposes, without the inconvenience of having to lock them.
+
+Note that this does not grant any new capabilities to M-mode, since in the base standard it is already possible to apply unlocked regions to M-mode by locking them. In general, PMP regions should be locked in ascending region number order so they can't be subsequently overridden by currently unlocked regions.
+
+Note also that this is not the same as the "rule locking bypass" bit in the ePMP extension, which does not permit locked and unlocked M-mode regions to coexist.
+
+[cols="10h,20h,~", options="header"]
+|===
+| Bits  | Name     | Description
+| 31:16 | -        | RES0
+| 15:0  | `m`      | Regions apply to M-mode if this bit _or_ the corresponding `pmpcfg.L` bit is set. Regions are locked if and only if the corresponding `pmpcfg.L` bit is set.
+|===
+
+=== Custom Power Control CSRs
+
+[[reg-h3.msleep]]
+==== h3.msleep
+
+Address: `0xbf0`
+
+M-mode sleep control register. Resets to all-zeroes.
+
+[cols="10h,20h,~", options="header"]
+|===
+| Bits | Name | Description
+| 31:3 | - | RES0
+| 2    | `sleeponblock` | Enter the deep sleep state on a `h3.block` instruction as well as a standard `wfi`. If this bit is clear, a `h3.block` is always implemented as a simple pipeline stall.
+| 1    | `powerdown`    | Release the external power request when going to sleep. The function of this is platform-defined -- it may do nothing, it may do something simple like clock-gating the fabric, or it may be tied to some complex system-level power controller.
+
+When waking, the processor reasserts its external power-up request, and will not fetch any instructions until the request is acknowledged. This may add considerable latency to the wakeup.
+| 0   | `deepsleep` | Deassert the processor clock enable when entering the sleep state. If a clock gate is instantiated, this allows most of the processor (everything except the power state machine and the interrupt and halt input registers) to be clock gated whilst asleep, which may reduce the sleep current. This adds one cycle to the wakeup latency.
+|===
+
+=== Custom Identification CSRs
+
+[[reg-h3.misa]]
+==== h3.misa
+
+Address: `0xbf1`
+
+M-mode ISA identification register.
+
+The `h3.misa` register provides a simple list of which standard RISC-V ISA extensions are supported. It is conceptually similar to the standard <<reg-misa>> register, but stores a larger bit array, sufficient to enumerate all standard extensions. This register comprises the entirety of the Xh3misa extension, as described in <<extension-xh3misa-section>>.
+
+The bit assignment is provided by the RISC-V C API documentation here: https://github.com/riscv-non-isa/riscv-c-api-doc/blob/main/src/c-api.adoc#extension-bitmask-definitions[https://github.com/riscv-non-isa/riscv-c-api-doc/blob/main/src/c-api.adoc#extension-bitmask-definitions]. The latest assignment can always be found in the upstream documentation, but at time of writing the following bits are assigned:
+
+[%autowidth,options="header"]
+|====
+| Extension | groupid | bit position
+| A | 0 | 0
+| B | 0 | 1
+| C | 0 | 2
+| D | 0 | 3
+| E | 0 | 4
+| F | 0 | 5
+| H | 0 | 7
+| I | 0 | 8
+| M | 0 | 12
+| Q | 0 | 16
+| V | 0 | 21
+| Zacas | 0 | 26
+| Zba | 0 | 27
+| Zbb | 0 | 28
+| Zbc | 0 | 29
+| Zbkb | 0 | 30
+| Zbkc | 0 | 31
+| Zbkx | 0 | 32
+| Zbs | 0 | 33
+| Zfa | 0 | 34
+| Zfh | 0 | 35
+| Zfhmin | 0 | 36
+| Zicboz | 0 | 37
+| Zicond | 0 | 38
+| Zihintntl | 0 | 39
+| Zihintpause | 0 | 40
+| Zknd | 0 | 41
+| Zkne | 0 | 42
+| Zknh | 0 | 43
+| Zksed | 0 | 44
+| Zksh | 0 | 45
+| Zkt | 0 | 46
+| Ztso | 0 | 47
+| Zvbb | 0 | 48
+| Zvbc | 0 | 49
+| Zvfh | 0 | 50
+| Zvfhmin | 0 | 51
+| Zvkb | 0 | 52
+| Zvkg | 0 | 53
+| Zvkned | 0 | 54
+| Zvknha | 0 | 55
+| Zvknhb | 0 | 56
+| Zvksed | 0 | 57
+| Zvksh | 0 | 58
+| Zvkt | 0 | 59
+| Zve32x | 0 | 60
+| Zve32f | 0 | 61
+| Zve64x | 0 | 62
+| Zve64f | 0 | 63
+| Zve64d | 1 | 0
+| Zimop | 1 | 1
+| Zca | 1 | 2
+| Zcb | 1 | 3
+| Zcd | 1 | 4
+| Zcf | 1 | 5
+| Zcmop | 1 | 6
+| Zawrs | 1 | 7
+| Zilsd | 1 | 8
+| Zclsd | 1 | 9
+| Zcmp | 1 | 10
+| Zifencei | 1 | 11
+| Zmmul | 1 | 12
+|====
+
+The bit index within the `h3.misa` bitmap can be calculated as `64 * groupid + bit position`. A read from <<reg-h3.misa>> returns a 32-bit slice of the bitmap, indexed by the write data of the same CSR instruction. For example, Zcmp is at bit index 74, which is bit 10 of word 2.
+
+----
+// Get bits 95:64 of the ISA bitmap:
+csrrwi a0, h3.misa, 2
+// Get bit 10 of the result:
+bexti a0, a0, 10
+// a0 is 1 if Zcmp is supported.
+----
+
+The implementation is not required to decode all bits of the index. The length of the bitmap can be checked by reading from the special index `0x400`. Software should ignore data from bit indices higher than the indicated bitmap length.
+
+The following is an example of testing for an extension based on the `groupid` and `bit_position` from the RISC-V C API documentation:
+
+----
+uint32_t h3_misa_read(uint32_t index) {
+	uint32_t ret;
+	asm (
+		"csrrw %0, 0xbf1, %1\n"
+		: "=r" (ret)
+		: "r" (index)
+	);
+	return ret;
+}
+
+bool h3_misa_extension_supported(unsigned int groupid, unsigned int bit_position) {
+	unsigned int index = groupid * 64u + bit_position;
+	if (index >= h3_misa_read(0x400u)) {
+		return false;
+	}
+	return h3_misa_read(index >> 5) & (1u << (index & 0x1f));
+}
+----
+
+Index `0x401` contains the length in _words_ of the custom extension listing, which starts from index `0x500`.
+
+Indices `0x500` onward contain versions of custom Hazard3 extensions:
+
+[options="header"]
+|===
+| Word index  | Extension
+| `0x500` | Xh3misa
+| `0x501` | Xh3irq
+| `0x502` | Xh3pmpm
+| `0x503` | Xh3power
+| `0x504` | Xh3bextm
+|===
+
+The custom extension entries have the same `major.minor.patch` format as <<reg-mimpid>>:
+
+[cols="10h,20h,~", options="header"]
+|===
+| Bits   | Name       | Description
+| 31:28  | -          | RES0
+| 27:24  | `major`    | Major release version, i.e. the `1` in `v1.2.3`
+| 23:16  | `minor`    | Minor release version, i.e. the `2` in `v1.2.3`
+| 15:8   | `patch`    | Patch version, i.e. the `3` in `v1.2.3`
+| 7:0    | -          | RES0
+|===
+
+
+A value of all-zeroes indicates the custom extension is not implemented.
+
+
+

Wren6991_Hazard3/doc/sections/custom_extensions.adoc

@@ -0,0 +1,228 @@
+== Custom Extensions
+
+Hazard3 implements a small number of custom extensions. Xh3misa is always included; the remaining custom extensions are only included if the relevant feature flags are set to `1` when instantiating the processor (<<config-parameters-section>>).
+
+The `x` bit in <<reg-misa>> is always set, to indicate (at least) the presence of the Xh3misa extension.
+
+[[extension-xh3misa-section]]
+=== Xh3misa: Hazard3 ISA identification register
+
+This document describes Xh3misa version: 1.0
+
+This extension is enabled by: <<param-CSR_M_MANDATORY>>.
+
+This extension adds the <<reg-h3.misa>> CSR. This is an extended version of the standard <<reg-misa>> register, capable of enumerating all standard RISC-V extensions (not just the single-letter ones).
+
+It describes presence and absence of extensions using the bitmap format described in the RISC-V C API documentation:
+
+https://github.com/riscv-non-isa/riscv-c-api-doc/blob/main/src/c-api.adoc#extension-bitmask-definitions[https://github.com/riscv-non-isa/riscv-c-api-doc/blob/main/src/c-api.adoc#extension-bitmask-definitions]
+
+This register also lists the versions of any custom Hazard3 extensions which may be present, including Xh3misa itself. For more details see the description of the <<reg-h3.misa>> register.
+
+[[extension-xh3irq-section]]
+=== Xh3irq: Hazard3 interrupt controller
+
+This document describes Xh3irq version: 1.0
+
+This extension is enabled by: <<param-EXTENSION_XH3IRQ>>
+
+This lightweight extension controls up to 512 external interrupts, with up to 16 levels of preemption. It adds no new instructions, but several CSRs:
+
+* <<reg-h3.meiea>>
+* <<reg-h3.meipa>>
+* <<reg-h3.meifa>>
+* <<reg-h3.meipra>>
+* <<reg-h3.meinext>>
+* <<reg-h3.meicontext>>
+
+If this extension is disabled then Hazard3 supports a single external interrupt input (or multiple inputs that it simply ORs together in an uncontrolled fashion), so an external PLIC can be used for standard interrupt support.
+
+Note that, besides the additional CSRs, this extension is effectively a slightly more complicated way of driving the standard `mip.meip` flag (<<reg-mip>>). The RISC-V trap handling CSRs themselves are always completely standard.
+
+[[extension-xh3pmpm-section]]
+=== Xh3pmpm: M-mode PMP regions
+
+This document describes Xh3pmpm version: 1.0
+
+This extension is enabled by: <<param-EXTENSION_XH3PMPM>>
+
+This extension adds a new M-mode CSR, <<reg-h3.pmpcfgm0>>, which allows a PMP region to be enforced in M-mode without locking the region.
+
+This is useful when the PMP is used for non-security-related purposes such as stack guarding, or trapping and emulation of peripheral accesses.
+
+[[extension-xh3power-section]]
+=== Xh3power: Hazard3 power management
+
+This document describes Xh3power version: 1.0
+
+This extension is enabled by: <<param-EXTENSION_XH3POWER>>
+
+This extension adds a new M-mode CSR (<<reg-h3.msleep>>), and two new hint instructions, `h3.block` and `h3.unblock`, in the `slt` nop-compatible custom hint space.
+
+The `h3.msleep` CSR controls how deeply the processor sleeps in the WFI sleep state. By default, a WFI is implemented as a normal pipeline stall. By configuring `h3.msleep` appropriately, the processor can gate its own clock when asleep or, with a simple 4-phase req/ack handshake, negotiate with an external power controller for power up/down of external hardware. These options can improve the sleep current at the cost of greater wakeup latency.
+
+The hints allow processors to sleep until woken by other processors in a multiprocessor environment. They are implemented on top of the standard WFI state, which means they interact in the same way with external debug, and benefit from the same deep sleep states in `h3.msleep`.
+
+==== h3.block
+
+Enter a WFI sleep state until either an unblock signal is received, or an interrupt is asserted that would cause a WFI to exit.
+
+If `mstatus.tw` is set, attempting to execute this instruction in privilege modes lower than M-mode will generate an illegal instruction exception.
+
+If an unblock signal has been received in the time since the last `h3.block`, this instruction executes as a `nop`, and the processor does not enter the sleep state. Conceptually, the sleep state falls through immediately because the corresponding unblock signal has already been received.
+
+An unblock signal is received when a neighbouring processor (the exact definition of "neighbouring" being left to the implementer) executes an `h3.unblock` instruction, or for some other platform-defined reason.
+
+This instruction is encoded as `slt x0, x0, x0`, which is part of the custom nop-compatible hint encoding space.
+
+Example C macro:
+
+----
+#define __h3_block() asm ("slt x0, x0, x0")
+----
+
+Example assembly macro:
+
+----
+.macro h3.block
+	slt x0, x0, x0
+.endm
+----
+
+==== h3.unblock
+
+Post an unblock signal to other processors in the system. For example, to notify another processor that a work queue is now nonempty.
+
+If `mstatus.tw` is set, attempting to execute this instruction in privilege modes lower than M-mode will generate an illegal instruction exception.
+
+This instruction is encoded as `slt x0, x0, x1`, which is part of the custom nop-compatible hint encoding space.
+
+Example C macro:
+
+----
+#define __h3_unblock() asm ("slt x0, x0, x1")
+----
+
+Example assembly macro:
+
+----
+.macro h3.unblock
+	slt x0, x0, x1
+.endm
+----
+
+[[extension-xh3bextm-section]]
+=== Xh3bextm: Hazard3 bit extract multiple
+
+This document describes Xh3bextm version: 1.0
+
+This extension is enabled by: <<param-EXTENSION_XH3BEXTM>>
+
+This is a small extension with multi-bit versions of the "bit extract" instructions from Zbs, used for extracting small, contiguous bit fields.
+
+==== h3.bextm
+
+"Bit extract multiple", a multi-bit version of the `bext` instruction from Zbs. Perform a right-shift followed by a mask of 1-8 LSBs.
+
+Encoding (R-type):
+
+[cols="10h,20h,20h,~", options="header"]
+|===
+| Bits  | Name          | Value    | Description
+| 31:29 | `funct7[6:4]` | `0b000`  | RES0
+| 28:26 | `size`        | -        | Number of ones in mask, values 0->7 encode 1->8 bits.
+| 25    | `funct7[0]`   | `0b0`    | RES0, because aligns with `shamt[5]` of potential RV64 version of `h3.bextmi` 
+| 24:20 | `rs2`         | -        | Source register 2 (shift amount)
+| 19:15 | `rs1`         | -        | Source register 1
+| 14:12 | `funct3`      | `0b000`  | `h3.bextm`
+| 11:7  | `rd`          | -        | Destination register
+| 6:2   | `opc`         | `0b00010`| custom0 opcode
+| 1:0   | `size`        | `0b11`   | 32-bit instruction
+|===
+
+Example C macro (using GCC statement expressions):
+
+----
+// nbits must be a constant expression
+#define __h3_bextm(nbits, rs1, rs2) ({\
+	uint32_t __h3_bextm_rd; \
+	asm (".insn r 0x0b, 0, %3, %0, %1, %2"\
+		: "=r" (__h3_bextm_rd) \
+		: "r" (rs1), "r" (rs2), "i" ((((nbits) - 1) & 0x7) << 1)\
+	); \
+	__h3_bextm_rd; \
+})
+----
+
+Example assembly macro:
+
+----
+// rd = (rs1 >> rs2[4:0]) & ~(-1 << nbits)
+.macro h3.bextm rd rs1 rs2 nbits
+.if (\nbits < 1) || (\nbits > 8)
+.err
+.endif
+#if NO_HAZARD3_CUSTOM
+    srl  \rd, \rs1, \rs2
+    andi \rd, \rd, ((1 << \nbits) - 1)
+#else
+.insn r 0x0b, 0x0, (((\nbits - 1) & 0x7 ) << 1), \rd, \rs1, \rs2
+#endif
+.endm
+----
+
+==== h3.bextmi
+
+
+Immediate variant of `h3.bextm`.
+
+Encoding (I-type):
+
+[cols="10h,20h,20h,~", options="header"]
+|===
+| Bits  | Name          | Value    | Description
+| 31:29 | `imm[11:9]`   | `0b000`  | RES0
+| 28:26 | `size`        | -        | Number of ones in mask, values 0->7 encode 1->8 bits.
+| 25    | `imm[5]`      | `0b0`    | RES0, for potential future RV64 version 
+| 24:20 | `shamt`       | -        | Shift amount, 0 through 31 
+| 19:15 | `rs1`         | -        | Source register 1
+| 14:12 | `funct3`      | `0b100`  | `h3.bextmi`
+| 11:7  | `rd`          | -        | Destination register
+| 6:2   | `opc`         | `0b00010`| custom0 opcode
+| 1:0   | `size`        | `0b11`   | 32-bit instruction
+|===
+
+Example C macro (using GCC statement expressions):
+
+----
+// nbits and shamt must be constant expressions
+#define __h3_bextmi(nbits, rs1, shamt) ({\
+	uint32_t __h3_bextmi_rd; \
+	asm (".insn i 0x0b, 0x4, %0, %1, %2"\
+		: "=r" (__h3_bextmi_rd) \
+		: "r" (rs1), "i" ((((nbits) - 1) & 0x7) << 6 | ((shamt) & 0x1f)) \
+	); \
+	__h3_bextmi_rd; \
+})
+----
+
+Example assembly macro:
+
+----
+// rd = (rs1 >> shamt) & ~(-1 << nbits)
+.macro h3.bextmi rd rs1 shamt nbits
+.if (\nbits < 1) || (\nbits > 8)
+.err
+.endif
+.if (\shamt < 0) || (\shamt > 31)
+.err
+.endif
+#if NO_HAZARD3_CUSTOM
+    srli \rd, \rs1, \shamt
+    andi \rd, \rd, ((1 << \nbits) - 1)
+#else
+.insn i 0x0b, 0x4, \rd, \rs1, (\shamt & 0x1f) | (((\nbits - 1) & 0x7 ) << 6)
+#endif
+.endm
+----
+

Wren6991_Hazard3/doc/sections/debug.adoc

@@ -0,0 +1,179 @@
+== Debug
+
+Hazard3 implements version 0.13.2 of the RISC-V debug specification, including:
+
+* Run/halt/reset control (including halt-on-reset for each hart)
+* Abstract GPR access
+* Program Buffer: 2 words plus `impebreak`
+* Automatic trigger of abstract command (`abstractauto`) on `data0` or Program Buffer access for efficient memory block transfers from the host
+* Support for multiple harts (multiple Hazard3 cores) connected to a single Debug Module (DM)
+* The hart array mask registers, for applying run/halt/reset controls to multiple cores simultaneously
+* (Optional) System Bus Access, either through a dedicated AHB5 manager interface, or multiplexed with a processor load/store port
+* A trigger unit with exception, interrupt and instruction count triggers
+** Exception and interrupt triggers are hardwired with `action` = `1` (break to Debug mode only)
+** Instruction count trigger is hardwired with `action` = `0` and `count` = `1` (provides single-stepping of U-mode or M-mode from an M-mode exception handler)
+** The `tcontrol.mte` and `mpte` bits prevent trigger loops under M-mode trigger usage
+* (Optional) Instruction address match triggers (hardware breakpoints)
+** Usable from both Debug mode and M-mode
+
+=== Debug Topologies
+
+Hazard3's Debug Module (DM) has the following interfaces:
+
+* An upstream AMBA 3 APB port -- the "Debug Module Interface" -- for host access to the Debug Module
+* A downstream Hazard3-specific interface to one or more cores
+* Some reset request/acknowledge signals which require careful handshaking with system-level reset logic
+
+This is shown in the example topology below.
+
+image::diagrams/debug_topology.png[pdfwidth=50%, width=50%]
+
+The DM is implemented by the `hazard3_dm` module, found in https://github.com/Wren6991/Hazard3/blob/stable/hdl/debug/dm/hazard3_dm.v[hdl/debug/dm/hazard3_dm.v]. The DM _must_ be connected directly to the processors without intervening registers. This implies the DM is in the same clock domain as the processors, so multiple processors on the same DM must share a common clock.
+
+Upstream of the DM is at least one Debug Transport Module, which bridges some host-facing interface such as JTAG to the APB DM Interface. Hazard3 provides an implementation of a standard RISC-V JTAG-DTM, but any APB manager could be used. The DM requires at least 7 bits of word addressing, i.e. 9 bits of byte address space. The top-level module for Hazard3's JTAG-DTM implementation is `hazard3_jtag_dtm`, found in https://github.com/Wren6991/Hazard3/blob/stable/hdl/debug/dtm/hazard3_jtag_dtm.v[hdl/debug/dtm/hazard3_jtag_dtm.v].
+
+An APB arbiter could be inserted here, to allow multiple transports to be used, provided the host(s) avoid using multiple transports concurrently. This also admits simple implementation of self-hosted debug, by mapping the DM to a system-level peripheral address space.
+
+The clock domain crossing (if any) occurs on the downstream port of the Debug Transport Module. Hazard3's JTAG-DTM implementation runs entirely in the TCK domain, and instantiates a bus clock-crossing module internally to bridge a TCK-domain internal APB bus to an external bus in the processor clock domain.
+
+It is possible to instantiate multiple DMs, one per core, and attach them to a single Debug Transport Module. This is not the preferred topology, but it does allow multiple cores to be independently clocked. In this case, the first DM must be located at address `0x0` in the DMI address space, and you must set the `NEXT_DM_ADDR` parameter on each DM so that the debugger can walk the (null-terminated) linked list and discover all the DMs.
+
+[[section-trigger-module]]
+=== Trigger Module
+
+Hazard3's Trigger Module generates synchronous traps to either Debug Mode or M-mode when certain pre-programmed conditions are met. It support four types of trigger: instruction address (breakpoint), interrupt, exception, and instruction count. The number of instruction address match triggers is configurable, and the remaining trigger types have one instance each.
+
+Use the following CSRs to configure individual triggers:
+
+* <<reg-tselect>>: Choose a trigger to configure. Implements exactly enough bits to index all implemented triggers; remaining bits are hardwired to 0
+* <<reg-tinfo>>: List the capabilities of the currently selected trigger (the supported values for `tdata1.type`)
+* <<reg-tdata1>>: Configure the trigger. Layout changes based on the value of `tdata1.type`
+* <<reg-tdata2>>: Further configuration, or address/data to match on
+* <<reg-tdata3>>: Supports filtering of triggers based on context -- not implemented on Hazard3, so hardwired to zero
+
+A compliant debugger can enumerate the triggers on a particular Hazard3 implementation using the standard method: incrementing `tselect` from 0, checking `tinfo` for each `tselect` index, and terminating when `tinfo` is 0 or `tselect` wraps.
+
+Hazard3 implements only a single trigger type for each `tselect` index. Therefore `tinfo` has only one bit set, and the `tdata1.type` field for each trigger is read-only, matching the bit set in `tinfo`.
+
+Most of Hazard3's triggers support a programmable `action` field, which determines whether the trigger targets M-mode (`action` = `0`) or Debug Mode (`action` = `1`).
+
+M-mode triggers generate an `ebreak` exception (`mcause` = `3`) with `mepc` pointing to the instruction which generated the trigger condition. This provides hardware support for self-hosted debuggers, such as an M-mode operating system supporting debug of U-mode applications on the same core.
+
+Debug Mode triggers enter Debug Mode with `dpc` pointing to the instruction which generated the trigger condition. The core ceases to execute instructions autonomously, and its internals become accessible to the external debug host.
+
+An `action` of `1` is ignored when that trigger's `tdata1.dmode` bit is clear. Only Debug Mode can modify this bit, and setting this bit prevents other modes from modifying the trigger's configuration. This effectively claims the trigger for external debugger use, and makes it unavailable to self-hosted debug software.
+
+==== Instruction Address Triggers
+
+The <<param-BREAKPOINT_TRIGGERS>> parameter configures the trigger unit with 0 or more hardware breakpoint comparators, assigned <<reg-tselect>> indices `0` through `BREAKPOINT_TRIGGERS - 1`. Each comparator continuously monitors the program counter for an exact match for its programmed address. When the comparator matches, the core takes a trap with `dpc` or `mepc` equal to the programmed breakpoint address.
+
+In standard RISC-V terms, these are instruction address match triggers, with the following characteristics as described by hardwired fields in `mcontrol` (aka <<reg-tdata1>>):
+
+* `tdata1.type` = `2`: address/data match
+* `mcontrol.timing` = `0`: trigger fires before the instruction executes
+* `mcontrol.select` = `0`: match on address (not data)
+* `mcontrol.match` = `0`: match on exact address
+* `mcontrol.store` = `load` = `0`: load/store address comparison not supported
+
+The `mcontrol.u` and `mcontrol.m` bits are fully implemented, and determine in which privilege modes the trigger will fire.
+
+The `mcontrol.action` field can be programmed with the value `0` or `1`, indicating a break to M-mode or D-mode respectively. D-mode breaks are taken only when `mcontrol.dmode` is set.
+
+`tdata2` contains the address to be matched on. The LSB of this register is hardwired to zero, as the RISC-V program counter never contains odd addresses. When compressed instruction support is disabled (<<param-EXTENSION_C>> is `0`), bit `1` is also hardwired to zero.
+
+The `mcontrol.execute` flag enables and disables the trigger (1/0).
+
+[[section-icount-trigger]]
+==== Instruction Count Trigger
+
+Hazard3 implements a single instruction count trigger, assigned <<reg-tselect>> index `BREAKPOINT_TRIGGERS`. For example, if no breakpoint triggers are configured, it is accessed at `tselect` = `0`.
+
+This trigger is hardwired with a `count` of `1`, and is intended to be a lightweight feature to support self-hosted M-mode single-stepping. Debug Mode already has this capability in the form of the `dcsr.step` flag, so the instruction count trigger supports `action` = `0` only (break to M-mode).
+
+The following configuration bits in <<reg-tdata1>> are _not_ hardwired:
+
+* `icount.m`: if `1`, enable the trigger in M-mode
+* `icount.u`: if `1`, enable the trigger in U-mode (only available when the <<param-U_MODE>> parameter is `1`)
+
+The trigger fires after one instruction successfully executes. `mepc` points to the next instruction in program order. Since `icount.count` is hardwired to `1`, hardware clears both the `m` and `u` flags after the trigger fires, to avoid repeat fires.
+
+IMPORTANT: As a deliberate departure from the 0.13.2 specification, the trigger does not fire on exceptions, because the resulting breakpoint exception would make the original exception unrecoverable and impossible to diagnose. To handle an exception occurring during single-stepping, catch the exception directly.
+
+To single-step a U-mode context from M-mode, set `icount.u` before returning to U-mode via `mret.` The U-mode context will trap back out after executing one instruction.
+
+To single-step an M-mode target, clear `tcontrol.mte`, then set `tcontrol.mpte` and `icount.m` before returning to an M-mode context via `mret`. The trigger is enabled after the return completes (via `mpte` shifting to `mte`), and the core traps back to the M-mode handler after executing one instruction in the M-mode returnee. The handler executes normally, because `mte` is cleared by the trap, and `icount.m` is cleared by the trigger match.
+
+To support the above behaviour, hardware does not clear `icount.m` or `icount.u` while `tcontrol.mte` is clear. See discussion https://github.com/riscv/riscv-debug-spec/pull/829#issuecomment-1492260861[here].
+
+[[section-interrupt-trigger]]
+==== Interrupt Trigger
+
+Hazard3 implements a single interrupt trigger, assigned <<reg-tselect>> index `BREAKPOINT_TRIGGERS + 1`. For example, if no breakpoint triggers are configured, it is accessed at `tselect` = `1`.
+
+This trigger fires on a configurable subset of the interrupt cause values listed in the <<reg-mcause>> register description. `tdata2` contains a bitmap with one bit per cause value. The break is taken after the hardware interrupt entry sequence has taken place (e.g. the setting of `mcause`), but before the first instruction in the interrupt handler executes. `dpc` points to the first instruction in the interrupt handler.
+
+`action` is hardwired to `1` (Debug Mode entry), because all interrupts on Hazard3 target M-mode, so a breakpoint exception triggered by interrupt entry would make it impossible to return from the interrupt.
+
+The implemented bits are `11`, `7` and `3`, corresponding to `mip.meip`, `mip.mtip` and `mip.msip` respectively.
+
+[[section-exception-trigger]]
+==== Exception Trigger
+
+Hazard3 implements a single exception trigger, assigned <<reg-tselect>> index `BREAKPOINT_TRIGGERS + 2`. For example, if no breakpoint triggers are configured, it is accessed at `tselect` = `2`.
+
+This trigger fires on a configurable subset of the exception cause values listed in the <<reg-mcause>> register description. `tdata2` contains a bitmap with one bit per cause value. The break is taken after the hardware exception entry sequence has taken place (e.g. the setting of `mcause`) but before the first instruction in the exception handler executes. `dpc` points to the first instruction in the exception handler.
+
+`action` is hardwired to `1` (Debug Mode entry) because all exceptions on Hazard3 target M-mode, so a breakpoint exception triggered by another exception would always make the original exception unrecoverable.
+
+Bits corresponding to causes impossible on a given Hazard3 implementation are hardwired to zero. For example, bit `0` (`mcause` = `0`, fetch alignment exception) is not implemented when <<param-EXTENSION_C>> is `1`, because there are no fetch alignment exceptions if compressed instructions are implemented.
+
+Bit `3` (`ebreak`) is also unimplemented. To catch `ebreak` execution from an external debugger, use the `dcsr.ebreakm` and `dcsr.ebreaku` flags.
+
+=== Implementation-defined behaviour
+
+Features implemented by the Hazard3 Debug Module (beyond the mandatory):
+
+* Halt-on-reset, selectable per-hart
+* Program Buffer, size 2 words, `impebreak` = 1.
+* A single data register (`data0`) is implemented as a per-hart CSR accessible by the DM
+* `abstractauto` is supported on the `data0`, `progbuf0` and `progbuf1` registers
+* Up to 32 harts selectable via `hartsel`
+* Hart array mask selection
+* System bus access (optional)
+
+Not implemented:
+
+* Abstract access memory
+* Abstract access CSR
+* Post-incrementing abstract access GPR
+
+The core behaves as follows:
+
+* Branch, `jal`, `jalr` and `auipc` are illegal in debug mode, because they observe PC: attempting to execute will halt Program Buffer execution and report an exception in `abstractcs.cmderr`
+* The `dret` instruction is not implemented (a special purpose DM-to-core signal is used to signal resume)
+* The `dscratch` CSRs are not implemented
+* The DM's `data0` register is mapped into the core as a CSR, <<reg-h3.dmdata0>>, address `0xbff`.
+** Raises an illegal instruction exception when accessed outside of Debug Mode
+** The DM ignores attempted core writes to the CSR, unless the DM is currently executing an abstract command on that core
+** Used by the DM to implement abstract GPR access, by injecting CSR read/write instructions
+* `dcsr.stepie` is hardwired to `0` (no interrupts during single stepping)
+* `dcsr.stopcount` and `dcsr.stoptime` are hardwired to `1` (no counter or internal timer increment in debug mode)
+* `dcsr.mprven` is hardwired to `0`
+* `dcsr.prv` supports the values `3` (M-mode) and `0` (U-mode). If U-mode support is not configured, it is hardwired to `3`.
+
+See also <<debug-csr-section>> for more details on the core-side Debug Mode registers.
+
+The debug host must use the Program Buffer to access CSRs and memory. This carries some overhead for individual accesses, but is efficient for bulk transfers: the `abstractauto` feature allows the DM to trigger the Program Buffer and/or a GPR transfer automatically following every `data0` access, which can be used for e.g. autoincrementing read/write memory bursts. Program Buffer read/writes can also be used as `abstractauto` triggers: this is less useful than the `data0` trigger, but takes little extra effort to implement, and can be used to read/write a large number of CSRs efficiently.
+
+Abstract memory access is not implemented because, for bulk transfers, it offers no better throughput than Program Buffer execution with `abstractauto`. Non-bulk transfers, while slower, are still instantaneous from the perspective of the human at the other end of the wire.
+
+The Hazard3 DM supports multi-core debug. Each core possesses exactly one hardware thread (hart) which is exposed to the debugger. The RISC-V specification does not mandate what mapping is used between the DM hart index `hartsel` and each core's `mhartid` CSR, but a 1:1 match of these values is the least likely to cause issues.
+
+Each core's `mhartid` CSR is configured using the `mhartid_val` input port on that core. In a correctly configured system, each core must have a unique value, and one core has the value of all-zeroes.
+
+=== Debug Module to Core Interface
+
+The DM can inject instructions directly into the core's instruction prefetch buffer. This mechanism is used to execute the Program Buffer, or used directly by the DM, issuing hardcoded instructions to manipulate core state.
+
+The DM's `data0` register is exposed to the core as a debug mode CSR. By issuing instructions to make the core read or write this dummy CSR, the DM can exchange data with the core. To read from a GPR `x` into `data0`, the DM issues a `csrw data0, x` instruction. Similarly `csrr x, data0` will write `data0` to that GPR. The DM always follows the CSR instruction with an `ebreak`, just like the implicit `ebreak` at the end of the Program Buffer, so that it is notified by the core when the GPR read instruction sequence completes.
+

Wren6991_Hazard3/doc/sections/instruction_pseudocode.adoc

@@ -0,0 +1,1219 @@
+== Instruction Pseudocode
+
+This section is a quick reference for the operation of the instructions supported by Hazard3, in Verilog syntax. Conventions used in this section:
+
+* `rs1`, `rs2` and `rd` are 32-bit unsigned vector variables referring to the two register operands and the destination register
+* `imm` is a 32-bit unsigned vector referring to the instruction's immediate value
+* `pc` is a 32-bit unsigned vector referring to the program counter
+* `mem` is an array of 8-bit unsigned vectors, each corresponding to a byte address in memory.
+
+=== RV32I: Register-register
+
+With the exception of the shift instructions, all instructions in this section have an immediate range of -2048 to 2047. Negative immediates can be useful for the bitwise operations too: for example `not rd, rs1` is a pseudo-op for `xori rd, rs1, -1`.
+
+Shift instructions have an immediate range of 0 to 31.
+
+==== add
+
+Add register to register.
+
+Syntax:
+
+    add rd, rs1, rs2
+
+Operation:
+
+    rd = rs1 + rs2;
+
+==== sub
+
+Subtract register from register.
+
+Syntax:
+
+    sub rd, rs1, rs2
+
+Operation:
+
+    rd = rs1 - rs2;
+
+==== slt
+
+Set if less than (signed).
+
+Syntax:
+
+    slt rd, rs1, rs2
+
+Operation:
+
+    rd = $signed(rs1) < $signed(rs2);
+
+==== sltu
+
+Set if less than (unsigned).
+
+Syntax:
+
+    sltu rd, rs1, rs
+
+Operation:
+
+    rd = rs1 < rs2;
+
+==== and
+
+Bitwise AND.
+
+Syntax:
+
+    and rd, rs1, rs2
+
+Operation:
+
+    rd = rs1 & rs2;
+
+
+==== or
+
+Bitwise OR.
+
+Syntax:
+
+    or rd, rs1, rs2`
+
+Operation:
+
+    rd = rs1 | rs2;
+
+
+==== xor
+
+Bitwise XOR.
+
+Syntax:
+
+    xor rd, rs1, rs2
+
+Operation:
+
+    rd = rs1 ^ rs2;
+
+==== sll
+
+Shift left, logical.
+
+Syntax:
+
+    sll rd, rs1, rs2
+
+Operation:
+
+    rd = rs1 << rs2;
+
+
+==== srl
+
+Shift right, logical.
+
+Syntax:
+
+    srl rd, rs1, rs2
+
+Operation:
+
+    rd = rs1 >> rs2;
+
+
+==== sra
+
+Shift right, arithmetic.
+
+Syntax:
+
+    sra rd, rs1, rs2
+
+Operation:
+
+    rd = rs1 >>> rs2;
+
+
+=== RV32I: Register-immediate
+
+
+==== addi
+
+Add register to immediate.
+
+Syntax:
+
+    addi rd, rs1, imm
+
+Operation:
+
+    rd = rs1 + imm
+
+==== slti
+
+Set if less than immediate (signed).
+
+Syntax:
+
+    slti rd, rs1, imm
+
+Operation:
+
+    rd = $signed(rs1) < $signed(imm);
+
+==== sltiu
+
+Set if less than immediate (unsigned).
+
+Syntax:
+
+    sltiu rd, rs1, imm
+
+Operation:
+
+    rd = rs1 < imm;
+
+==== andi
+
+Bitwise AND with immediate.
+
+Syntax:
+
+    andi rd, rs1, imm
+
+Operation:
+
+    rd = rs1 & imm;
+
+==== ori
+
+Bitwise OR with immediate.
+
+Syntax:
+
+    ori rd, rs1, imm
+
+Operation:
+
+    rd = rs1 \| imm;
+
+==== xori
+
+Bitwise XOR with immediate.
+
+Syntax:
+
+    xori rd, rs1, imm
+
+Operation:
+
+    rd = rs1 ^ imm;
+
+==== slli
+
+Shift left, logical, immediate.
+
+Syntax:
+
+    slli rd, rs1, imm
+
+Operation:
+
+    rd = rs1 << imm;
+
+==== srli
+
+Shift right, logical, immediate.
+
+Syntax:
+
+    srli rd, rs1, imm
+
+Operation:
+
+    rd = rs1 >> imm;
+
+==== srai
+
+Shift right, arithmetic, immediate.
+
+Syntax:
+
+    srai rd, rs1, imm
+
+Operation:
+
+    rd = rs1 >>> imm;
+
+=== RV32I: Large immediate
+
+==== lui
+
+Load upper immediate.
+
+Syntax:
+
+    lui rd, imm
+
+Operation:
+
+    rd = imm;
+
+(`imm` is a 20-bit value followed by 12 zeroes)
+
+==== auipc
+
+Add upper immediate to program counter.
+
+Syntax:
+
+	auipc rd, imm
+
+Operation:
+
+	rd = pc + imm;
+
+(`imm` is a 20-bit value followed by 12 zeroes)
+
+=== RV32I: Control transfer
+
+
+==== jal
+
+Jump and link.
+
+Syntax:
+
+    jal rd, label
+    j label        // rd is implicitly x0
+
+Operation:
+
+    rd = pc + 4;
+    pc = label;
+
+NOTE: the 16-bit variant, `c.jal`, writes `pc + 2` to `rd`, rather than `pc + 4`. The `rd` value always points to the sequentially-next instruction.
+
+==== jalr
+
+Jump and link, target is register.
+
+Syntax:
+
+    jalr rd, rs1, imm // imm is implicitly 0 if omitted.
+    jr rs1, imm       // rd is implicitly x0. imm is implicitly 0 if omitted.
+    ret               // pseudo-op for jr ra
+
+Operation:
+
+    rd = pc + 4;
+    pc = rs1 + imm;
+
+NOTE: the 16-bit variant, `c.jalr`, writes `pc + 2` to `rd`, rather than `pc + 4`. The `rd` value always points to the sequentially-next instruction.
+
+==== beq
+
+Branch if equal.
+
+Syntax:
+
+    beq rs1, rs2, label
+
+Operation:
+
+    if (rs1 == rs2)
+        pc = label;
+
+==== bne
+
+Branch if not equal.
+
+Syntax:
+
+    bne rs1, rs2, label
+
+Operation:
+
+    if (rs1 != rs2)
+        pc = label;
+
+==== blt
+
+Branch if less than (signed).
+
+Syntax:
+
+    blt rs1, rs2, label
+
+Operation:
+
+    if ($signed(rs1) < $signed(rs2))
+        pc = label;
+
+==== bge
+
+Branch if greater than or equal (signed).
+
+Syntax:
+
+    bge rs1, rs2, label
+
+Operation:
+
+    if ($signed(rs1) >= $signed(rs2))
+        pc = label;
+
+==== bltu
+
+Branch if less than (unsigned).
+
+Syntax:
+
+    bltu rs1, rs2, label
+
+Operation:
+
+    if (rs1 < rs2)
+        pc = label;
+
+==== bgeu
+
+Branch if less than or equal (unsigned).
+
+Syntax:
+
+    bgeu rs1, rs2, label
+
+Operation:
+
+    if (rs1 >= rs2)
+        pc = label;
+
+=== RV32I: Load and Store
+
+==== lw
+
+Load word.
+
+Syntax:
+
+    lw rd, imm(rs1)
+    lw rd, (rs1)    // imm is implicitly 0 if omitted.
+
+
+Operation:
+
+    rd = {
+        mem[rs1 + imm + 3],
+        mem[rs1 + imm + 2],
+        mem[rs1 + imm + 1],
+        mem[rs1 + imm]
+    };
+
+==== lh
+
+Load halfword (signed).
+
+Syntax:
+
+    lh rd, imm(rs1)
+    lh rd, (rs1)    // imm is implicitly 0 if omitted.
+
+Operation:
+
+	rd = {
+		{16{mem[rs1 + imm + 1][7]}}, // Sign-extend
+		mem[rs1 + imm + 1],
+		mem[rs1 + imm]
+	};
+
+==== lhu
+
+Load halfword (unsigned).
+
+Syntax:
+
+    lhu rd, imm(rs1)
+    lhu rd, (rs1)    // imm is implicitly 0 if omitted.
+
+Operation:
+
+	rd = {
+		16'h0000, // Zero-extend
+		mem[rs1 + imm + 1],
+		mem[rs1 + imm]
+	};
+
+==== lb
+
+Load byte (signed).
+
+Syntax:
+
+	lb rd, imm(rs1)
+    lb rd, (rs1)    // imm is implicitly 0 if omitted.
+
+Operation:
+
+    rd = {
+        {24{mem[rs1 + imm][7]}}, // Sign-extend
+        mem[rs1 + imm]
+    };
+
+
+
+==== lbu
+
+Load byte (unsigned).
+
+Syntax:
+
+	lbu rd, imm(rs1)
+    lbu rd, (rs1)    // imm is implicitly 0 if omitted.
+
+Operation:
+
+    rd = {
+        24'h000000, // Zero-extend
+        mem[rs1 + imm]
+    };
+
+==== sw
+
+Store word.
+
+Syntax:
+
+    sw rs2, imm(rs1)
+    sw rs2, (rs1)    // imm is implicitly 0 if omitted.
+
+Operation:
+
+    mem[rs1 + imm]     = rs2[7:0];
+    mem[rs1 + imm + 1] = rs2[15:8];
+    mem[rs1 + imm + 2] = rs2[23:16];
+    mem[rs1 + imm + 3] = rs2[31:24];
+
+==== sh
+
+Store halfword.
+
+Syntax:
+
+    sh rs2, imm(rs1)
+    sh rs2, (rs1)    // imm is implicitly 0 if omitted.
+
+Operation:
+
+    mem[rs1 + imm]     = rs2[7:0];
+    mem[rs1 + imm + 1] = rs2[15:8];
+
+==== sb
+
+Store byte.
+
+Syntax:
+
+    sb rs2, imm(rs1)
+    sb rs2, (rs1)    // imm is implicitly 0 if omitted.
+
+Operation:
+
+    mem[rs1 + imm] = rs2[7:0];
+
+=== M Extension
+
+
+==== mul
+
+Multiply 32 × 32 -> 32.
+
+Syntax:
+
+    mul rd, rs1, rs2
+
+
+Operation:
+
+    rd = rs1 * rs2;
+
+==== mulh
+
+Multiply signed (32) by signed (32), return upper 32 bits of the 64-bit result.
+
+Syntax:
+
+    mulh rd, rs1, rs2
+
+Operation:
+
+    // Both operands are sign-extended to 64 bits:
+    wire [63:0] result_full = {{32{rs1[31]}}, rs1} * {{32{rs2[31]}}, rs2};
+    rd = result_full[63:32];
+
+==== mulhsu
+
+Multiply signed (32) by unsigned (32), return upper 32 bits of the 64-bit result.
+
+Syntax:
+
+    mulhsu rd, rs1, rs2
+
+Operation:
+
+    // rs1 is sign-extended, rs2 is zero-extended:
+    wire [63:0] result_full = {{32{rs1[31}}, rs1} * {32'h00000000, rs2};
+    rd = result_full[63:32];
+
+==== mulhu
+
+Multiply unsigned (32) by unsigned (32), return upper 32 bits of the 64-bit result.
+
+Syntax:
+
+    mulhu rd, rs1, rs2
+
+Operation:
+
+    wire [63:0] result_full = {32'h00000000, rs1} * {32'h00000000, rs2};
+    rd = result_full[63:32];
+
+==== div
+
+Divide (signed).
+
+Syntax:
+
+    div rd, rs1, rs2
+
+Operation:
+
+    if (rs2 == 32'h0)
+        rd = 32'hffffffff;
+    else if (rs1 == 32'h80000000 && rs2 == 32'hffffffff) // Signed overflow
+        rd = 32'h80000000;
+    else
+        rd = $signed(rs1) / $signed(rs2);
+
+==== divu
+
+Divide (unsigned).
+
+Syntax:
+
+    divu rd, rs1, rs2
+
+Operation:
+
+    if (rs2 == 32'h0)
+        rd = 32'hffffffff;
+    else
+        rd = rs1 / rs2;
+
+==== rem
+
+Remainder (signed).
+
+Syntax:
+
+    rem rd, rs1, rs2
+
+Operation:
+
+    if (rs2 == 32'h0)
+        rd = rs1;
+    else
+        rd = $signed(rs1) % $signed(rs2);
+
+==== remu
+
+Remainder (unsigned).
+
+Syntax:
+
+    remu rd, rs1, rs2
+
+Operation:
+
+    if (rs2 == 32'h0)
+        rd = rs1;
+    else
+        rd = rs1 % rs2;
+
+=== A Extension
+
+(TODO)
+
+=== C Extension
+
+All C extension instructions are 16-bit aliases of 32-bit instructions from other extensions (in the case of Hazard3, entirely from the RV32I base extension). They behave identically to their 32-bit counterparts.
+
+=== Zba: Bit manipulation (address generation)
+
+==== sh1add
+
+Add, with the first addend shifted left by 1.
+
+Syntax:
+
+    sh1add rd, rs1, rs2
+
+Operation:
+
+    rd = (rs1 << 1) + rs2;
+
+==== sh2add
+
+Add, with the first addend shifted left by 2.
+
+Syntax:
+
+    sh2add rd, rs1, rs2
+
+Operation:
+
+    rd = (rs1 << 2) + rs2;
+
+==== sh3add
+
+Add, with the first addend shifted left by 3.
+
+Syntax:
+
+    sh3add rd, rs1, rs2
+
+Operation:
+
+    rd = (rs1 << 3) + rs2;
+
+=== Zbb: Bit manipulation (basic)
+
+==== andn
+
+Bitwise AND with inverted operand.
+
+Syntax:
+
+    andn rd, rs1, rs2
+
+Operation:
+
+    rd = rs1 & ~rs2;
+
+==== clz
+
+Count leading zeroes (starting from MSB, searching LSB-ward).
+
+Syntax:
+
+    clz rd, rs1
+
+Operation:
+
+----
+rd = 32;          // Default = 32 if no set bits
+reg found = 1'b0; // Local variable
+
+for (i = 0; i < 32; i = i + 1) begin
+    if (rs1[31 - i] && !found) begin
+        found = 1'b1;
+        rd = i;
+    end
+end
+----
+
+==== cpop
+
+Population count.
+
+Syntax:
+
+    cpop rd, rs1
+
+Operation:
+
+    rd = 0;
+    for (i = 0; i < 32; i = i + 1)
+        rd = rd + rs1[i];
+
+==== ctz
+
+Count trailing zeroes (starting from LSB, searching MSB-ward).
+
+Syntax:
+
+    ctz rd, rs1
+
+Operation:
+
+----
+rd = 32;          // Default = 32 if no set bits
+reg found = 1'b0; // Local variable
+
+for (i = 0; i < 32; i = i + 1) begin
+    if (rs1[i] && !found) begin
+        found = 1'b1;
+        rd = i;
+    end
+end
+----
+
+==== max
+
+Maximum of two values (signed).
+
+Syntax:
+
+    max rd, rs1, rs2
+
+Operation:
+
+    if ($signed(rs1) < $signed(rs2))
+        rd = rs2;
+    else
+        rd = rs1;
+
+==== maxu
+
+Maximum of two values (unsigned).
+
+Syntax:
+
+    maxu rd, rs1, rs2
+
+Operation:
+
+    if (rs1 < rs2)
+        rd = rs2;
+    else
+        rd = rs1;
+
+==== min
+
+Minimum of two values (signed).
+
+Syntax:
+
+    min rd, rs1, rs2
+
+Operation:
+
+    if ($signed(rs1) < $signed(rs2))
+        rd = rd1;
+    else
+        rd = rs2;
+
+==== minu
+
+Minimum of two values (unsigned).
+
+Syntax:
+
+    minu rd, rs1, rs2
+
+Operation:
+
+    if (rs1 < rs2)
+        rd = rs1;
+    else
+        rd = rs2;
+
+==== orc.b
+
+Or-combine of bits within each byte.
+
+Syntax:
+
+    orc.b rd, rs1
+
+Operation:
+
+    rd = {
+        {8{|rs1[31:24]}},
+        {8{|rs1[23:16]}},
+        {8{|rs1[15:8]}},
+        {8{|rs1[7:0]}}
+    };
+
+==== orn
+
+Bitwise OR with inverted operand.
+
+Syntax:
+
+    orn rd, rs1, rs2
+
+Operation:
+
+    rd = rs1 | ~rs2;
+
+==== rev8
+
+Reverse bytes within word.
+
+Syntax:
+
+    rev8 rd, rs1
+
+Operation:
+
+    rd = {
+        rs1[7:0],
+        rs1[15:8],
+        rs1[23:16],
+        rs1[31:24]
+    };
+
+==== rol
+
+Rotate left.
+
+Syntax:
+
+    rol rd, rs1, rs2
+
+Operation:
+
+    if (rs2[4:0] == 0)
+        rd = rs1;
+    else
+        rd = (rs1 << rs2[4:0]) | (rs1 >> (32 - rs2[4:0]));
+
+==== ror
+
+Rotate right.
+
+Syntax:
+
+    ror rd, rs1, rs2
+
+Operation:
+
+    if (rs2[4:0] == 0)
+        rd = rs1;
+    else
+        rd = (rs1 >> rs2[4:0]) | (rs1 << (32 - rs2[4:0]));
+
+==== rori
+
+Rotate right, immediate.
+
+Syntax:
+
+    ror rd, rs1, imm
+
+Operation:
+
+    if (imm[4:0] == 0)
+        rd = rs1;
+    else
+        rd = (rs1 >> imm[4:0]) | (rs1 << (32 - imm[4:0]));
+
+==== sext.b
+
+Sign-extend from byte.
+
+Syntax:
+
+    sext.b rd, rs1
+
+Operation:
+
+    rd = {
+        {24{rs1[7]}},
+        rs1[7:0]
+    };
+
+==== sext.h
+
+Sign-extend from halfword.
+
+Syntax:
+
+    sext.h rd, rs1
+
+Operation:
+
+    rd = {
+        {16{rs1[15]}},
+        rs1[15:0]
+    };
+
+==== xnor
+
+Bitwise XOR with inverted operand.
+
+Syntax:
+
+    xnor rd, rs1, rs2
+
+Operation:
+
+    rd = rs1 ^ ~rs2;
+
+==== zext.h
+
+Zero-extend from halfword.
+
+Syntax:
+
+    zext.h rd, rs1
+
+Operation:
+
+    rd = {
+        16'h0000,
+        rs1[15:0]
+    };
+
+==== zext.b
+
+Zero-extend from byte.
+
+Syntax:
+
+    zext.b rd, rs1
+
+Operation:
+
+    // Pseudo-op for RV32I instruction
+    andi rd, rs1, 0xff
+
+=== Zbc: Bit manipulation (carry-less multiply)
+
+Each of these three instructions returns a 32-bit slice of the following 64-bit result:
+
+----
+reg [63:0] clmul_result;
+
+always @ (*) begin
+    clmul_result = 0;
+    for (i = 0; i < 32; i = i + 1) begin
+        if (rs2[i])) begin
+            clmul_result = clmul_result ^ ({32'h0, rs1} << i);
+        end
+    end
+end
+----
+
+==== clmul
+
+Carry-less multiply, low half.
+
+Syntax:
+
+    clmul rd, rs1, rs2
+
+Operation:
+
+    rd = cmul_result[31:0];
+
+==== clmulh
+
+Carry-les multiply, high half.
+
+Syntax:
+
+    clmulh rd, rs1, rs2
+
+Operation:
+
+    rd = clmul_result[63:32];
+
+==== clmulr
+
+Bit-reverse of carry-less multiply of bit-reverse.
+
+Syntax:
+
+    clmulr rd, rs1, rs2
+
+Operation:
+
+    rd = clmul_result[32:1];
+
+
+=== Zbs: Bit manipulation (single-bit)
+
+==== bclr
+
+Clear single bit.
+
+Syntax:
+
+    bclr rd, rs1, rs2
+
+Operation:
+
+    rd = rs1 & ~(32'h1 << rs2[4:0]);
+
+==== bclri
+
+Clear single bit (immediate).
+
+Syntax:
+
+    bclri rd, rs1, imm
+
+Operation:
+
+    rd = rs1 & ~(32'h1 << imm[4:0]);
+
+
+==== bext
+
+Extract single bit.
+
+Syntax:
+
+    bext rd, rs1, rs2
+
+Operation:
+
+    rd = (rs1 >> rs2[4:0]) & 32'h1;
+
+==== bexti
+
+Extract single bit (immediate).
+
+Syntax:
+
+    bexti rd, rs1, imm
+
+Operation:
+
+    rd = (rs1 >> imm[4:0]) & 32'h1;
+
+==== binv
+
+Invert single bit.
+
+Syntax:
+
+    binv rd, rs1, rs2
+
+Operation:
+
+    rd = rs1 ^ (32'h1 << rs2[4:0]);
+
+==== binvi
+
+Invert single bit (immediate).
+
+Syntax:
+
+    binvi rd, rs1, imm
+
+Operation:
+
+    rd = rs1 ^ (32'h1 << imm[4:0]);
+
+==== bset
+
+Set single bit.
+
+Syntax:
+
+    bset rd, rs1, rs2
+
+Operation:
+
+    rd = rs1 | (32'h1 << rs2[4:0])
+
+==== bseti
+
+Set single bit (immediate).
+
+Syntax:
+
+    bseti rd, rs1, imm
+
+Operation:
+
+    rd = rs1 | (32'h1 << imm[4:0]);
+
+=== Zbkb: Basic bit manipulation for cryptography
+
+NOTE: Zbkb has a large overlap with Zbb (basic bit manipulation). This section covers only those instruction in Zbkb but not in Zbb.
+
+==== brev8
+
+Bit-reverse within each byte.
+
+Syntax:
+
+    brev8 rd, rs1
+
+Operation:
+
+    for (i = 0; i < 32; i = i + 8) begin
+        for (j = 0; j < 8; j = j + 1) begin
+            rd[i + j] = rs1[i + (7 - j)];
+        end
+    end
+
+==== pack
+
+Pack halfwords into word.
+
+Syntax:
+
+    pack rd, rs1, rs2
+
+Operation:
+
+    rd = {
+        rs2[15:0],
+        rs1[15:0]
+    };
+
+==== packh
+
+Pack bytes into halfword.
+
+Syntax:
+
+    packh rd, rs1, rs2
+
+Operation:
+
+    rd = {
+        16'h0000,
+        rs2[7:0],
+        rs1[7:0]
+    };
+
+==== zip
+
+Interleave upper/lower half of register into odd/even bits of result.
+
+Syntax:
+
+    zip rd, rs1
+
+Operation:
+
+    for (i = 0; i < 32; i = i + 2) begin
+        rd[i]     = rs1[i / 2];
+        rd[i + 1] = rs1[i / 2 + 16];
+    end
+
+==== unzip
+
+Deinterleave odd/even bits of register into upper/lower half of result.
+
+Syntax:
+
+    unzip rd, rs1
+
+Operation:
+
+    for (i = 0; i < 32; i = i + 2) begin
+        rd[i / 2]      = rs1[i];
+        rd[i / 2 + 16] = rs1[i + 1];
+    end
+

Wren6991_Hazard3/doc/sections/instruction_timings.adoc

@@ -0,0 +1,220 @@
+== Instruction Cycle Counts
+
+All timings are given assuming perfect bus behaviour (no downstream bus stalls), and that the core is configured with `MULDIV_UNROLL = 2` and all other configuration options set for maximum performance.
+
+=== Base Instruction Set (RV32I)
+
+[%autowidth.stretch, options="header"]
+|===
+| Instruction | Cycles | Note
+3+| Integer Register-register
+| `add rd, rs1, rs2` | 1 |
+| `sub rd, rs1, rs2` | 1 |
+| `slt rd, rs1, rs2` | 1 |
+| `sltu rd, rs1, rs2` | 1 |
+| `and rd, rs1, rs2` | 1 |
+| `or rd, rs1, rs2` | 1 |
+| `xor rd, rs1, rs2` | 1 |
+| `sll rd, rs1, rs2` | 1 |
+| `srl rd, rs1, rs2` | 1 |
+| `sra rd, rs1, rs2` | 1 |
+3+| Integer Register-immediate
+| `addi rd, rs1, imm` | 1 | `nop` is a pseudo-op for `addi x0, x0, 0`
+| `slti rd, rs1, imm` | 1 |
+| `sltiu rd, rs1, imm` | 1 |
+| `andi rd, rs1, imm` | 1 |
+| `ori rd, rs1, imm` | 1 |
+| `xori rd, rs1, imm` | 1 |
+| `slli rd, rs1, imm` | 1 |
+| `srli rd, rs1, imm` | 1 |
+| `srai rd, rs1, imm` | 1 |
+3+| Large Immediate
+| `lui rd, imm` | 1 |
+| `auipc rd, imm` | 1 |
+3+| Control Transfer
+| `jal rd, label` | 2footnote:unaligned_branch[A jump or branch to a 32-bit instruction which is not 32-bit-aligned requires one additional cycle, because two naturally aligned bus cycles are required to fetch the target instruction.]|
+| `jalr rd, rs1, imm` | 2footnote:unaligned_branch[] |
+| `beq rs1, rs2, label`| 1 or 2footnote:unaligned_branch[] | 1 if correctly predicted, 2 if mispredicted.
+| `bne rs1, rs2, label`| 1 or 2footnote:unaligned_branch[] | 1 if correctly predicted, 2 if mispredicted.
+| `blt rs1, rs2, label`| 1 or 2footnote:unaligned_branch[] | 1 if correctly predicted, 2 if mispredicted.
+| `bge rs1, rs2, label`| 1 or 2footnote:unaligned_branch[] | 1 if correctly predicted, 2 if mispredicted.
+| `bltu rs1, rs2, label`| 1 or 2footnote:unaligned_branch[] | 1 if correctly predicted, 2 if mispredicted.
+| `bgeu rs1, rs2, label`| 1 or 2footnote:unaligned_branch[] | 1 if correctly predicted, 2 if mispredicted.
+3+| Load and Store
+| `lw rd, imm(rs1)` | 1 or 2 | 1 if next instruction is independent, 2 if dependent.footnote:data_dependency[If an instruction in stage 2 (e.g. an `add`) uses data from stage 3 (e.g. a `lw` result), a 1-cycle bubble is inserted between the pair. A load data -> store data dependency is _not_ an example of this, because data is produced and consumed in stage 3. However, load data -> load address _would_ qualify, as would e.g. `sc.w` -> `beqz`.]
+| `lh rd, imm(rs1)` | 1 or 2 | 1 if next instruction is independent, 2 if dependent.footnote:data_dependency[]
+| `lhu rd, imm(rs1)` | 1 or 2 | 1 if next instruction is independent, 2 if dependent.footnote:data_dependency[]
+| `lb rd, imm(rs1)` | 1 or 2 | 1 if next instruction is independent, 2 if dependent.footnote:data_dependency[]
+| `lbu rd, imm(rs1)` | 1 or 2 | 1 if next instruction is independent, 2 if dependent.footnote:data_dependency[]
+| `sw rs2, imm(rs1)` | 1 |
+| `sh rs2, imm(rs1)` | 1 |
+| `sb rs2, imm(rs1)` | 1 |
+|===
+
+=== Integer Multiply and Divide (M)
+
+Timings assume the core is configured with `MULDIV_UNROLL = 2` and `MUL_FAST = 1`. I.e. the sequential multiply/divide circuit processes two bits per cycle, and a separate dedicated multiplier is present for the `mul` instruction.
+
+
+[%autowidth.stretch, options="header"]
+|===
+| Instruction | Cycles | Note
+3+| 32 {times} 32 -> 32 Multiply
+| `mul rd, rs1, rs2` | 1  |
+3+| 32 {times} 32 -> 64 Multiply, Upper Half
+| `mulh rd, rs1, rs2` | 1 |
+| `mulhsu rd, rs1, rs2` | 1 |
+| `mulhu rd, rs1, rs2` | 1 |
+3+| Divide and Remainder
+| `div rd, rs1, rs2` | 18 or 19 | Depending on sign correction
+| `divu rd, rs1, rs2` | 18 |
+| `rem rd, rs1, rs2` | 18 or 19 | Depending on sign correction
+| `remu rd, rs1, rs2` | 18 |
+|===
+
+=== Atomics (A)
+
+[%autowidth.stretch, options="header"]
+|===
+| Instruction | Cycles | Note
+3+| Load-Reserved/Store-Conditional
+| `lr.w rd, (rs1)` | 1 or 2 | 2 if next instruction is dependentfootnote:data_dependency[], an `lr.w`, `sc.w` or `amo*.w`.footnote:exclusive_pipelining[A pipeline bubble is inserted between `lr.w`/`sc.w` and an immediately-following `lr.w`/`sc.w`/`amo*`, because the AHB5 bus standard does not permit pipelined exclusive accesses. A stall would be inserted between `lr.w` and `sc.w` anyhow, so the local monitor can be updated based on the `lr.w` data phase in time to suppress the `sc.w` address phase.]
+| `sc.w rd, rs2, (rs1)` | 1 or 2 | 2 if next instruction is dependentfootnote:data_dependency[], an `lr.w`, `sc.w` or `amo*.w`.footnote:exclusive_pipelining[]
+3+| Atomic Memory Operations
+|`amoswap.w rd, rs2, (rs1)` | 4+ | 4 per attempt. Multiple attempts if reservation is lost.footnote:amo_timing[AMOs are issued as a paired exclusive read and exclusive write on the bus, at the maximum speed of 2 cycles per access, since the bus does not permit pipelining of exclusive reads/writes. If the write phase fails due to the global monitor reporting a lost reservation, the instruction loops at a rate of 4 cycles per loop, until success. If the read reservation is refused by the global monitor, the instruction generates a Store/AMO Fault exception, to avoid an infinite loop.]
+|`amoadd.w rd, rs2, (rs1)`  | 4+ | 4 per attempt. Multiple attempts if reservation is lost.footnote:amo_timing[]
+|`amoxor.w rd, rs2, (rs1)`  | 4+ | 4 per attempt. Multiple attempts if reservation is lost.footnote:amo_timing[]
+|`amoand.w rd, rs2, (rs1)`  | 4+ | 4 per attempt. Multiple attempts if reservation is lost.footnote:amo_timing[]
+|`amoor.w rd, rs2, (rs1)`   | 4+ | 4 per attempt. Multiple attempts if reservation is lost.footnote:amo_timing[]
+|`amomin.w rd, rs2, (rs1)`  | 4+ | 4 per attempt. Multiple attempts if reservation is lost.footnote:amo_timing[]
+|`amomax.w rd, rs2, (rs1)`  | 4+ | 4 per attempt. Multiple attempts if reservation is lost.footnote:amo_timing[]
+|`amominu.w rd, rs2, (rs1)` | 4+ | 4 per attempt. Multiple attempts if reservation is lost.footnote:amo_timing[]
+|`amomaxu.w rd, rs2, (rs1)` | 4+ | 4 per attempt. Multiple attempts if reservation is lost.footnote:amo_timing[]
+|===
+
+=== Compressed Instructions (C or Zca)
+
+All C extension 16-bit instructions are aliases of base RV32I instructions. On Hazard3, they perform identically to their 32-bit counterparts.
+
+A consequence of the C extension is that 32-bit instructions can be non-naturally-aligned. This has no penalty during sequential execution, but branching to a 32-bit instruction that is not 32-bit-aligned carries a 1 cycle penalty, because the instruction fetch is cracked into two naturally-aligned bus accesses.
+
+=== Privileged Instructions (including Zicsr)
+
+[%autowidth.stretch, options="header"]
+|===
+| Instruction | Cycles | Note
+3+| CSR Access
+| `csrrw rd, csr, rs1` | 1footnote:csr_fetch_ordering[Writes to the following CSRs take 3 cycles, plus an additional 1 cycle if the following instruction is misaligned 32-bit: `pmpaddr*`, `pmpcfg*`, `tcontrol`, `tdata1`, `tdata2`. These CSRs require an instruction fetch flush to enforce CSR-write-to-fetch ordering.] |
+| `csrrc rd, csr, rs1` | 1footnote:csr_fetch_ordering[] |
+| `csrrs rd, csr, rs1` | 1footnote:csr_fetch_ordering[] |
+| `csrrwi rd, csr, imm` | 1footnote:csr_fetch_ordering[] |
+| `csrrci rd, csr, imm` | 1footnote:csr_fetch_ordering[] |
+| `csrrsi rd, csr, imm` | 1footnote:csr_fetch_ordering[] |
+3+| Trap Request
+| `ecall` | 3 | Time given is for jumping to `mtvec`
+| `ebreak` | 3 | Time given is for jumping to `mtvec`
+|===
+
+=== Load/Store Pair (Zilsd)
+
+[%autowidth.stretch, options="header"]
+|===
+| Instruction | Cycles | Note
+3+| Load/Store Pair
+| `ld rd, imm(rs1)` | 2 | Issues as two `lw`
+| `sd rs2, imm(rs1)` | 2 | Issues as two `sw`
+|===
+
+=== Bit Manipulation (Zba, Zbb, Zbc, Zbs)
+
+[%autowidth.stretch, options="header"]
+|===
+| Instruction | Cycles | Note
+3+| Zba (address generation)
+|`sh1add rd, rs1, rs2` | 1 |
+|`sh2add rd, rs1, rs2` | 1 |
+|`sh3add rd, rs1, rs2` | 1 |
+3+| Zbb (basic bit manipulation)
+|`andn rd, rs1, rs2`   | 1 |
+|`clz rd, rs1`         | 1 |
+|`cpop rd, rs1`        | 1 |
+|`ctz rd, rs1`         | 1 |
+|`max rd, rs1, rs2`    | 1 |
+|`maxu rd, rs1, rs2`   | 1 |
+|`min rd, rs1, rs2`    | 1 |
+|`minu rd, rs1, rs2`   | 1 |
+|`orc.b rd, rs1`       | 1 |
+|`orn rd, rs1, rs2`    | 1 |
+|`rev8 rd, rs1`        | 1 |
+|`rol rd, rs1, rs2`    | 1 |
+|`ror rd, rs1, rs2`    | 1 |
+|`rori rd, rs1, imm`   | 1 |
+|`sext.b rd, rs1`      | 1 |
+|`sext.h rd, rs1`      | 1 |
+|`xnor rd, rs1, rs2`   | 1 |
+|`zext.h rd, rs1`      | 1 |
+|`zext.b rd, rs1`      | 1 | `zext.b` is a pseudo-op for `andi rd, rs1, 0xff`
+3+| Zbc (carry-less multiply)
+|`clmul rd, rs1, rs2`  | 1 |
+|`clmulh rd, rs1, rs2` | 1 |
+|`clmulr rd, rs1, rs2` | 1 |
+3+| Zbs (single-bit manipulation)
+|`bclr rd, rs1, rs2`   | 1 |
+|`bclri rd, rs1, imm`  | 1 |
+|`bext rd, rs1, rs2`   | 1 |
+|`bexti rd, rs1, imm`  | 1 |
+|`binv rd, rs1, rs2`   | 1 |
+|`binvi rd, rs1, imm`  | 1 |
+|`bset rd, rs1, rs2`   | 1 |
+|`bseti rd, rs1, imm`  | 1 |
+3+| Zbkb (basic bit manipulation for cryptography)
+|`pack rd, rs1, rs2`   | 1 |
+|`packh rd, rs1, rs2`  | 1 |
+|`brev8 rd, rs1`       | 1 |
+|`zip   rd, rs1`       | 1 |
+|`unzip rd, rs1`       | 1 |
+|===
+
+=== Additional Basic Compressed Instructions (Zcb)
+
+Similarly to the C extension, this extension contains 16-bit variants of common 32-bit instructions:
+
+* RV32I base ISA: `lbu`, `lh`, `lhu`, `sb`, `sh`, `zext.b` (alias of `andi`), `not` (alias of `xori`)
+* Zbb extension: `sext.b`, `zext.h`, `sext.h`
+* M extension: `mul`
+
+They perform identically to their 32-bit counterparts.
+
+=== Compressed Load/Store Pair (Zclsd)
+
+These 16-bit instructions behave identically to their 32-bit counterparts, namely:
+
+* `c.ld` expands to Zilsd `ld`
+* `c.ldsp` expands to Zilsd `ld`
+* `c.sd` expands to Zilsd `sd`
+* `c.sdsp` expands to Zilsd `sd`
+
+=== Push, Pop and Double Move (Zcmp)
+
+[%autowidth.stretch, options="header"]
+|===
+| Instruction | Cycles | Note
+|`cm.push {rlist}, -imm` | 1 + _n_ | _n_ is number of registers in rlist
+|`cm.pop {rlist}, imm` | 1 + _n_ | _n_ is number of registers in rlist
+|`cm.popret {rlist}, imm` | 4 (_n_ = 1)footnote:popret_stall[The single-register variant of `cm.popret` takes the same number of cycles as the two-register variant, because of an internal load-use dependency on the loaded return address.] or 2 + _n_ (_n_ >= 2)footnote:unaligned_branch[] | _n_ is number of registers in rlist
+|`cm.popretz {rlist}, imm` | 3 + __n__footnote:unaligned_branch[] | _n_ is number of registers in rlist
+|`cm.mva01s r1s', r2s'` | 2 |
+|`cm.mvsa01 r1s', r2s'` | 2 |
+|===
+
+[[instruction-timings-branch-predictor]]
+=== Branch Predictor
+
+Hazard3 includes a minimal branch predictor, to accelerate tight loops:
+
+* The instruction frontend remembers the last taken, backward branch
+* If the same branch is seen again, it is predicted taken
+* All other branches are predicted nontaken
+* If a predicted-taken branch is not taken, the predictor state is cleared, and it will be predicted nontaken on its next execution.
+
+Correctly predicted branches execute in one cycle: the frontend is able to stitch together the two nonsequential fetch paths so that they appear sequential. Mispredicted branches incur a penalty cycle, since a nonsequential fetch address must be issued when the branch is executed.

Wren6991_Hazard3/doc/sections/introduction.adoc

@@ -0,0 +1,139 @@
+== Introduction
+
+Hazard3 is a configurable 3-stage RISC-V processor, implementing:
+
+* `RV32I` or `RV32E`: 32-bit base instruction set
+* `M`: integer multiply/divide/modulo
+* `A`: atomic memory operations, with AHB5 global exclusives
+* `C`: compressed instructions
+* `Zicsr`: CSR access
+* `Zilsd`: load/store pair
+* `Zba`: address generation
+* `Zbb`: basic bit manipulation
+* `Zbc`: carry-less multiplication
+* `Zbs`: single-bit manipulation
+* `Zbkb`: basic bit manipulation for scalar cryptography
+* `Zbkx`: crossbar permutation instructions
+* `Zcb`: basic additional compressed instructions
+* `Zcmp`: push/pop and double-move compressed instructions
+* `Zclsd`: compressed load/store pair instructions
+* Debug, Machine and User privilege/execution modes
+* Privileged instructions `ecall`, `ebreak`, `mret` and `wfi`
+* Physical memory protection (PMP) with up to 16 regions (configurable support for NAPOT and/or TOR matching)
+* External debug support
+* Instruction address trigger unit (hardware breakpoints)
+
+This document describes Hazard3 version https://github.com/Wren6991/Hazard3/releases/tag/v1.1.1[v1.1.1]. See <<section-release-notes>> for changes introduced in this and earlier versions.
+
+<<<
+
+=== Architecture Overview
+
+==== Interfaces
+
+Hazard3 communicates with system hardware using the following groups of signals:
+
+image::diagrams/hazard3_interfaces_both.drawio.png[width=60%, pdfwidth=60%, align="center"]
+
+AHB:: The core accesses the bus using either 1 {times} or 2 {times} 32-bit AHB5 bus manager ports, depending on choice of top-level module (see <<top-level-modules>>).
+IRQ:: The core implements standard RISC-V timer and software IRQ inputs, and a choice of a single external IRQ input or an integrated interrupt controller with support for up to 512 external IRQs.
+Debug:: Allows the Hazard3 Debug Module implementation to access core internals, and optionally to access the system bus directly by arbitrating with the core's load/store access.
+Power:: The core can negotiate power up/down of external hardware based on sleep state, and enter/exit sleep states cooperatively with other cores in the same multiprocessor system.
+Fence:: The core can request memory orderings; the system can stall the request (e.g. for a cache flush).
+
+See <<port-descriptions>> for a full description of these interfaces.
+
+// Hard line break because there is a huge diagram on the next page and it needs to flow with the text
+<<<
+
+==== Pipeline Stages
+
+The diagram shows how hardware components are distributed through three pipeline stages. A dotted outline means an optional component. Dotted vertical lines are clock boundaries between stages; blocks that straddle these lines are synchronous elements, either registers or bus signals that are notionally registered outside the core. Dependencies (and time) flow from left to right.
+
+image::diagrams/hazard3_pipeline.drawio.png[width=90%, align="center", pdfwidth=100%]
+
+The three stages are:
+
+* `F`: Fetch
+** Contains the data phase for instruction fetch
+** Contains the instruction prefetch buffer
+** Predecodes register numbers `rs1`/`rs2`, for faster register file read and register bypass
+** Contains the address match logic for the optional branch predictor
+** Compares data-phase fetch address with breakpoint addresses
+** Looks up data-phase fetch address against PMP regions
+* `X`: Execute
+** Decodes and execute instructions
+** Looks up load/store/AMO addresses against PMP regions
+** Drives the address phase for load/store/AMO
+** Generates jump/branch addresses
+** Contains the read and write ports for the CSR file
+** Unbypassed register values are available at the beginning of stage `X`
+** The ALU result is valid by the end of stage `X`
+* `M`: Memory
+** Contains the data phase for load/store/AMO
+** Generates exception addresses
+** Register writeback is at the end of stage `M`
+
+The instruction fetch address phase is best thought of as residing in stage `X`. The 2-cycle feedback loop between jump/branch decode into address issue in stage `X`, and the fetch data phase in stage `F`, is what defines Hazard3's jump/branch performance.
+
+This document often refers to `F`, `X` and `M` as stages 1, 2 and 3 respectively. This numbering is useful when describing dependencies between values held in different pipeline stages, as it makes the direction and distance of the dependency more apparent.
+
+==== Bus Interfaces
+
+Hazard3 implements either one or two AHB5 bus manager ports. The dual-port configuration adds a dedicated port for instruction fetch. Use the single-port configuration when ease of integration is a priority, since it supports simpler bus topologies. The dual-port configuration supports higher maximum frequency and greater clock-for-clock performance provided you either have a split (Harvard) bus architecture, or can handle multiple AHB5 managers on the same bus.
+
+One of the key additions to AHB5 over older AHB versions is *exclusive accesses*, using the `HEXCL` and `HEXOKAY` signals. Exclusive accesses enable an ordered read-modify-write sequence with the guarantee that no other processor has written to the same memory location in between the read and write. Hazard3 uses AHB5 exclusives to implement multiprocessor support for the A (atomics) extension. Single-processor support for the A extension does not require these additional signals.
+
+AHB5 is one of the two protocols described in the https://documentation-service.arm.com/static/5f91607cf86e16515cdc3b4b[AMBA 5 AHB protocol specification]. Its full name is (perhaps surprisingly) AMBA 5 AHB5. Refer to the protocol specification for more information about this standard bus protocol.
+
+==== Multiply/Divide
+
+For minimal M-extension support, as enabled by <<param-EXTENSION_M>>, Hazard3 instantiates a sequential multiply/divide circuit (restoring divide, naive repeated-addition multiply). Instructions stall in stage `X` until the multiply/divide completes. Optionally, the circuit can be unrolled by a small factor to produce multiple bits ber clock. A throughput of one, two or four bits per cycle is achievable in practice, with the internal logic delay becoming quite significant at four.
+
+Set <<param-MUL_FAST>> to instantiate the single-cycle multiplier circuit. The fast multiplier returns results either to stage 3 or stage 2, depending on the <<param-MUL_FASTER>> parameter.
+
+By default the single-cycle multiplier only supports 32-bit `mul`, which is by far the most common of the four multiply instructions. The remaining instructions still execute on the sequential multiply/divide circuit. Set the <<param-MULH_FAST>> parameter to add single-cycle support for the high-half instructions (`mulh`, `mulhu` and `mulhsu`), at the cost of additional logic delay and area.
+
+The single-cycle multiplier is implemented as a simple `*` behavioural multiply, so that your tools can infer the best multiply circuit for your platform. For example, Yosys infers DSP tiles on iCE40 UP5k FPGAs. The multiplier is a self-contained module (in `hdl/arith/hazard3_mul_fast.v`), so you can replace its implementation if you know of a faster or lower-area method for your platform.
+
+// ** magic comment to reset sublime text asciidoc lexer
+
+==== Constant-time Execution
+
+Hazard3 supports `Zkt` constant-time execution in the following configurations:
+
+* <<param-EXTENSION_M>> is `0`
+* <<param-EXTENSION_M>> is `1`, <<param-MUL_FAST>> is `1` and <<param-MULH_FAST>> is `1`
+
+The source of data-dependent timing is conditional sign correction in the `mulh` and `mulhsu` instructions when executed on the sequential multiply/divide circuit. You can avoid this by configuring these instructions to execute on the single-cycle multiplier instead. The remaining `Zkt` instructions are constant-time for all configurations.
+
+Constant-time here refers to **data-independent timing**. Execution time can still be affected by other factors such as instruction alignment and external bus stalls.
+
+Software can read the `Zkt` bit in <<reg-h3.misa>> to check whether a given implementation has constant execution time for the `Zkt` instruction list.
+
+=== List of RISC-V Specifications
+
+These are links to the ratified versions of the base instruction set and extensions implemented by Hazard3.
+
+[%autowidth.stretch, options="header"]
+|===
+| Extension         | Specification
+| `RV32I` v2.1      | https://github.com/riscv/riscv-isa-manual/releases/download/Ratified-IMAFDQC/riscv-spec-20191213.pdf[Unprivileged ISA 20191213]
+| `M` v2.0          | https://github.com/riscv/riscv-isa-manual/releases/download/Ratified-IMAFDQC/riscv-spec-20191213.pdf[Unprivileged ISA 20191213]
+| `A` v2.1          | https://github.com/riscv/riscv-isa-manual/releases/download/Ratified-IMAFDQC/riscv-spec-20191213.pdf[Unprivileged ISA 20191213]
+| `C` v2.0          | https://github.com/riscv/riscv-isa-manual/releases/download/Ratified-IMAFDQC/riscv-spec-20191213.pdf[Unprivileged ISA 20191213]
+| `Zicsr` v2.0      | https://github.com/riscv/riscv-isa-manual/releases/download/Ratified-IMAFDQC/riscv-spec-20191213.pdf[Unprivileged ISA 20191213]
+| `Zifencei` v2.0   | https://github.com/riscv/riscv-isa-manual/releases/download/Ratified-IMAFDQC/riscv-spec-20191213.pdf[Unprivileged ISA 20191213]
+| `Zilsd` v1.0-rc3 | https://github.com/riscv/riscv-zilsd/releases/download/v1.0-rc3/riscv-zilsd-v1.0-rc3.pdf[Load/Store Pair for RV32 frozen v1.0-rc3]
+| `Zba` v1.0.0      | https://github.com/riscv/riscv-bitmanip/releases/download/1.0.0/bitmanip-1.0.0-38-g865e7a7.pdf[Bit Manipulation ISA extensions 20210628]
+| `Zbb` v1.0.0      | https://github.com/riscv/riscv-bitmanip/releases/download/1.0.0/bitmanip-1.0.0-38-g865e7a7.pdf[Bit Manipulation ISA extensions 20210628]
+| `Zbc` v1.0.0      | https://github.com/riscv/riscv-bitmanip/releases/download/1.0.0/bitmanip-1.0.0-38-g865e7a7.pdf[Bit Manipulation ISA extensions 20210628]
+| `Zbs` v1.0.0      | https://github.com/riscv/riscv-bitmanip/releases/download/1.0.0/bitmanip-1.0.0-38-g865e7a7.pdf[Bit Manipulation ISA extensions 20210628]
+| `Zbkb` v1.0.1     | https://github.com/riscv/riscv-crypto/releases/download/v1.0.1-scalar/riscv-crypto-spec-scalar-v1.0.1.pdf[Scalar Cryptography ISA extensions 20220218]
+| `Zbkx` v1.0.1     | https://github.com/riscv/riscv-crypto/releases/download/v1.0.1-scalar/riscv-crypto-spec-scalar-v1.0.1.pdf[Scalar Cryptography ISA extensions 20220218]
+| `Zcb` v1.0.3-1    | https://github.com/riscv/riscv-code-size-reduction/releases/download/v1.0.3-1/Zc-v1.0.3-1.pdf[Code Size Reduction extensions frozen v1.0.3-1]
+| `Zclsd` v1.0-rc3 | https://github.com/riscv/riscv-zilsd/releases/download/v1.0-rc3/riscv-zilsd-v1.0-rc3.pdf[Load/Store Pair for RV32 frozen v1.0-rc3]
+| `Zcmp` v1.0.3-1   | https://github.com/riscv/riscv-code-size-reduction/releases/download/v1.0.3-1/Zc-v1.0.3-1.pdf[Code Size Reduction extensions frozen v1.0.3-1]
+| Machine ISA v1.12 | https://github.com/riscv/riscv-isa-manual/releases/download/Priv-v1.12/riscv-privileged-20211203.pdf[Privileged Architecture 20211203]
+| Debug v0.13.2     | https://riscv.org/wp-content/uploads/2019/03/riscv-debug-release.pdf[RISC-V External Debug Support 20190322]
+|===

Wren6991_Hazard3/doc/sections/release_notes.adoc

@@ -0,0 +1,106 @@
+[[section-release-notes]]
+== Release Notes
+:sectnums!:
+
+=== Version 1.1.1
+
+Fixed errata:
+
+* Fix repeated transfer when `hazard3_apb_async_bridge` is connected to a standard APB Requester.
+** This behaviour did not affect instantiation inside of `hazard3_jtag_dtm`.
+* Fix breakpoint trigger on a CSR write not inhibiting the write to the CSR register file.
+* Fix non-synthesisable statement included in RVFI monitor when `HAZARD3_RVFI_STANDALONE` is defined.
+
+Other changes:
+
+* Improve riscv-formal coverage for AHB5 exclusives and the A extension.
+
+See the Github release notes https://github.com/Wren6991/Hazard3/releases/tag/v1.1[here].
+
+=== Version 1.1
+
+Incompatible changes:
+
+* The `MHARTID_VAL` parameter has been removed, and replaced with the `mhartid_val` port.
+* The `MIMPID_VAL` parameter has been removed.
+* The <<reg-mimpid>> CSR has been redefined to contain the hardcoded Hazard3 release version.
+
+New signals:
+
+* `fence_i_vld`, `fence_d_vld` and `fence_rdy` allow external hardware to enforce memory orderings or trigger cache flushes (see <<memory-ordering-signals,Memory Ordering Signals>>).
+* `mhartid_val` allows a dynamic `mhartid` CSR value.
+* `eco_version` allows modifying part of the processor's reported version number (see <<reg-mimpid>>).
+
+New features:
+
+* Implement the Zilsd extension (load/store pair), enabled by <<param-EXTENSION_ZILSD>>.
+* Implement the Zclsd extension (compressed load/store pair), enabled by <<param-EXTENSION_ZCLSD>>.
+* Implement the Zbkx extension (crossbar permutation), enabled by <<param-EXTENSION_ZBKX>>.
+* Implement TOR region support for PMP, enabled by <<param-PMP_MATCH_TOR>>.
+** NAPOT/NA4 matching is now optional, enabled by <<param-PMP_MATCH_NAPOT>>.
+* Implement interrupt, exception and instruction count trigger in the <<section-trigger-module>>.
+** These triggers are present whenever debug support is enabled by <<param-DEBUG_SUPPORT>>.
+* Implement the RV32E base extension, enabled by <<param-EXTENSION_E>>.
+* Implement new custom extension: <<extension-xh3misa-section>>, for detecting processor ISA support at finer granularity than the standard `misa` register. Enabled by `CSR_M_MANDATORY`, so it is reliably present.
+* Add `hazard3_xilinx7_jtag_dtm` for tunneling RISC-V debug through Xilinx 7-series FPGA TAPs.
+
+Fixed errata:
+
+* Fix `fence.i` only ordering against the address phase of a preceding store (a multi-manager AHB fabric may reorder address phases, so order against the data phase instead).
+* Fix local monitor flag being cleared by trap entry as well as trap exit (only `xRET` should clear it).
+** This behaviour continues to not affect entry/exit to Debug Mode, so LR/SC sequences can be single-stepped.
+* Fix the Debug Module PROGBUF1 register being writable when an abstract command is executing, and not setting `abstracts.cmderr` to `busy` when written.
+* Fix spurious dependency of CSR instructions on `rs2`, causing read-after-write stall.
+* Fix processor lockup on AMOs that fail PMP checks.
+* Fix Debug Mode loads and stores during Program Buffer execution being subject to PMP checks on M-mode-enforced (locked) regions.
+* Fix a data-phase fault on the final load of a `cm.popret` which loads at least two registers reporting the return address as the exception PC.
+** The following were not affected: `cm.pop`, `cm.popretz`, 1-register `cm.popret`, PMP traps and alignment traps.
+
+
+PPA optimisations:
+
+* Move breakpoint PC comparator from stage 2 to stage 1.
+* Move PMP X permission lookup from stage 2 to stage 1.
+* Simplify PMP X permission lookup by looking up naturally-aligned fetches instead of both halfwords of a potentially unaligned instruction.
+* Move compressed instruction expansion from stage 2 to stage 1.
+* Pre-decode `rs1`/`rs2` bypass controls in stage 1.
+* Restore register on `op_b` input of `hazard3_muldiv_seq` for better routing locality.
+
+General improvements:
+
+* Relax PMP X permission checking to allow instructions to straddle two PMP regions which both have the necessary permissions.
+* RTL is now lint-clean with Verilator v5.038.
+* Add Verilator testbench, command-line-compatible with existing CXXRTL testbench.
+* Update to latest versions of `riscv-arch-test`, `riscv-test`  and `riscv-formal`.
+* Enable `riscv-formal` checks for B extension and other bit manipulation extensions.
+* Update `hazard3_rvfi_monitor` to support running existing `riscv-formal` checks with the A, Zcmp, Zilsd and Zclsd extensions enabled.
+* Allow synthesising the processor with the RVFI trace monitor included by defining the `HAZARD3_RVFI_STANDALONE` macro.
+** This is an intermediate step towards E-trace support, and useful for tracing processor execution on FPGA or in simulation.
+
+
+Other changes:
+
+* Writes to CSRs which affect instruction fetch now cost three cycles plus an additional cycle if the following instruction is unaligned 32-bit.
+** Specifically this affects `pmpaddr*`, `pmpcfg*`, `tcontrol`, `tdata1` and `tdata2`.
+** These CSR writes now require an instruction fetch flush to enforce the necessary orderings.
+** All other CSRs remain single-cycle write.
+* Writes to `minstret`/`minstreth` or `mcycle`/`mcycleh` now inhibit the increment of the entire underlying 64-bit counter.
+** The spec wording was recently changed to clarify this issue: see https://github.com/riscv/riscv-isa-manual/issues/1255[here].
+
+See the Github release notes https://github.com/Wren6991/Hazard3/releases/tag/v1.1[here].
+
+=== Version 1.0.2
+
+* Coding style change in `hazard3_frontend` for Verilator compatibility
+
+See the Github release notes https://github.com/Wren6991/Hazard3/releases/tag/v1.0.2[here].
+
+=== Version 1.0.1
+
+* Fix: abstract access commands initiated via `abstractauto` access the wrong core GPR
+
+See the Github release notes https://github.com/Wren6991/Hazard3/releases/tag/v1.0.1[here].
+
+=== Version 1.0
+
+This is the first stable version of Hazard3. See the Github release notes https://github.com/Wren6991/Hazard3/releases/tag/v1.0[here].

Wren6991_Hazard3/example_soc/arty7-openocd.cfg

@@ -0,0 +1,34 @@
+# Notes on Arty A7 FTDI JTAG connectivity
+# (Digilent censored their schematic, lol):
+#
+# TCK (out) is ADBUS0
+# TDI (out) is ADBUS1
+# TDO (in)  is ADBUS2
+# TMS (out) is ADBUS3
+#
+# Supply monitoring (in) is on ADBUS4
+#
+# Reset output is ADBUS6
+#
+# LED LD9  is connected to bit 0x0800, active-low
+# LED LD10 is connected to bit 0x1000, active-low
+
+adapter driver ftdi
+adapter speed 10000
+ftdi vid_pid 0x0403 0x6010
+ftdi channel 0
+ftdi layout_init 0x00e8 0x60eb
+
+transport select jtag
+
+set _CHIPNAME artix7
+jtag newtap artix7 hazard3 -expected-id 0x13631093 -irlen 6
+
+set _TARGETNAME $_CHIPNAME.hazard3
+target create $_TARGETNAME riscv -chain-position $_TARGETNAME
+riscv set_ir dtmcs 0x22
+riscv set_ir dmi 0x23
+
+gdb_report_data_abort enable
+init
+halt

Wren6991_Hazard3/example_soc/fpga/fpga_arty_a7.f

@@ -0,0 +1,9 @@
+file fpga_arty_a7.v
+file ../libfpga/common/reset_sync.v
+file ../libfpga/common/fpga_reset.v
+file ../libfpga/common/blinky.v
+
+list ../soc/soc.f
+
+file ../../hdl/debug/dtm/hazard3_xilinx7_jtag_dtm.v
+

Wren6991_Hazard3/example_soc/fpga/fpga_arty_a7.v

@@ -0,0 +1,158 @@
+/*****************************************************************************\
+|                        Copyright (C) 2021 Luke Wren                         |
+|                     SPDX-License-Identifier: Apache-2.0                     |
+\*****************************************************************************/
+
+`default_nettype none
+
+module fpga (
+	input wire        clk_osc,
+
+	output wire [3:0] led,
+
+	output wire       uart_tx,
+	input  wire       uart_rx
+);
+
+wire clk_sys;
+wire locked;
+wire clkfbout;
+wire clkfbout_buf;
+BUFG bufg_clkfbout (
+	.I (clkfbout),
+	.O (clkfbout_buf)
+);
+
+// Configured for 100 -> 80 MHz
+MMCME2_ADV #(
+	.BANDWIDTH            ("OPTIMIZED"),
+	.CLKOUT4_CASCADE      ("FALSE"),
+	.COMPENSATION         ("ZHOLD"),
+	.STARTUP_WAIT         ("FALSE"),
+	.DIVCLK_DIVIDE        (1),
+	.CLKFBOUT_MULT_F      (10.000),
+	.CLKFBOUT_PHASE       (0.000),
+	.CLKFBOUT_USE_FINE_PS ("FALSE"),
+	.CLKOUT0_DIVIDE_F     (12.500),
+	.CLKOUT0_PHASE        (0.000),
+	.CLKOUT0_DUTY_CYCLE   (0.500),
+	.CLKOUT0_USE_FINE_PS  ("FALSE"),
+	.CLKIN1_PERIOD        (10.000)
+) mmcm_adv_inst (
+	.CLKFBOUT            (clkfbout),
+	.CLKFBOUTB           (/* unused */),
+	.CLKOUT0             (clk_sys),
+	.CLKOUT0B            (/* unused */),
+	.CLKOUT1             (/* unused */),
+	.CLKOUT1B            (/* unused */),
+	.CLKOUT2             (/* unused */),
+	.CLKOUT2B            (/* unused */),
+	.CLKOUT3             (/* unused */),
+	.CLKOUT3B            (/* unused */),
+	.CLKOUT4             (/* unused */),
+	.CLKOUT5             (/* unused */),
+	.CLKOUT6             (/* unused */),
+	// Input clock control
+	.CLKFBIN             (clkfbout_buf),
+	.CLKIN1              (clk_osc),
+	.CLKIN2              (1'b0),
+	// Tied to always select the primary input clock
+	.CLKINSEL            (1'b1),
+	// Ports for dynamic reconfiguration
+	.DADDR               (7'h0),
+	.DCLK                (1'b0),
+	.DEN                 (1'b0),
+	.DI                  (16'h0),
+	.DO                  (/* unused */),
+	.DRDY                (/* unused */),
+	.DWE                 (1'b0),
+	// Ports for dynamic phase shift
+	.PSCLK               (1'b0),
+	.PSEN                (1'b0),
+	.PSINCDEC            (1'b0),
+	.PSDONE              (/* unused */),
+	// Other control and status signals
+	.LOCKED              (locked),
+	.CLKINSTOPPED        (/* unused */),
+	.CLKFBSTOPPED        (/* unused */),
+	.PWRDWN              (1'b0),
+	.RST                 (1'b0) // TODO???
+);
+
+blinky #(
+	.CLK_HZ (100_000_000),
+	.BLINK_HZ (1)
+) blinky_clk_osc (
+	.clk (clk_osc),
+	.blink (led[0])
+);
+
+blinky #(
+	.CLK_HZ (80_000_000),
+	.BLINK_HZ (2)
+) blinky_clk_sys (
+	.clk (clk_sys),
+	.blink (led[1])
+);
+
+wire rst_n_sys;
+
+fpga_reset #(
+	.SHIFT (3)
+) rstgen (
+	.clk         (clk_sys),
+	.force_rst_n (1'b1),
+	.rst_n       (rst_n_sys)
+);
+
+example_soc #(
+	.DTM_TYPE            ("XILINX7"),
+
+	.SRAM_DEPTH          (1 << 15),
+
+	.CLK_MHZ             (80),
+
+	.EXTENSION_A         (1),
+	.EXTENSION_C         (0),
+	.EXTENSION_M         (1),
+	.EXTENSION_ZBA       (0),
+	.EXTENSION_ZBB       (0),
+	.EXTENSION_ZBC       (0),
+	.EXTENSION_ZBS       (0),
+	.EXTENSION_ZBKB      (0),
+	.EXTENSION_ZCMP      (0),
+	.EXTENSION_ZCLSD     (0),
+	.EXTENSION_ZCB       (0),
+	.EXTENSION_ZILSD     (0),
+	.EXTENSION_ZIFENCEI  (0),
+	.EXTENSION_XH3BEXTM  (0),
+	.EXTENSION_XH3PMPM   (0),
+	.EXTENSION_XH3POWER  (0),
+
+	.CSR_COUNTER         (0),
+	.U_MODE              (0),
+	.PMP_REGIONS         (0),
+	.BREAKPOINT_TRIGGERS (0),
+	.IRQ_PRIORITY_BITS   (0),
+	.REDUCED_BYPASS      (0),
+	.MULDIV_UNROLL       (1),
+	.MUL_FAST            (0),
+	.MUL_FASTER          (0),
+	.MULH_FAST           (0),
+	.FAST_BRANCHCMP      (1),
+	.BRANCH_PREDICTOR    (0)
+) soc_u (
+	.clk            (clk_sys),
+	.rst_n          (rst_n_sys),
+
+	.tck            (1'b0),
+	.trst_n         (1'b0),
+	.tms            (1'b0),
+	.tdi            (1'b0),
+	.tdo            (/* unused */),
+
+	.uart_tx        (uart_tx),
+	.uart_rx        (uart_rx)
+);
+
+endmodule

Wren6991_Hazard3/example_soc/fpga/fpga_icebreaker.f

@@ -0,0 +1,6 @@
+file fpga_icebreaker.v
+file ../libfpga/common/reset_sync.v
+file ../libfpga/common/fpga_reset.v
+list ../libfpga/common/activity_led.f
+
+list ../soc/soc.f

Wren6991_Hazard3/example_soc/fpga/fpga_icebreaker.v

@@ -0,0 +1,104 @@
+/*****************************************************************************\
+|                        Copyright (C) 2021 Luke Wren                         |
+|                     SPDX-License-Identifier: Apache-2.0                     |
+\*****************************************************************************/
+
+// FPGA toplevel for ../soc/example_soc.v on an iCEBreaker dev board
+
+`default_nettype none
+
+module fpga_icebreaker (
+	input wire        clk_osc,
+
+	// No external trst_n as iCEBreaker can't easily drive it from FTDI, so we
+	// generate a pulse internally from FPGA PoR.
+	input  wire       tck,
+	input  wire       tms,
+	input  wire       tdi,
+	output wire       tdo,
+
+	output wire       led,
+
+	output wire       mirror_tck,
+	output wire       mirror_tms,
+	output wire       mirror_tdi,
+	output wire       mirror_tdo,
+
+	output wire       uart_tx,
+	input  wire       uart_rx
+);
+
+assign mirror_tck = tck;
+assign mirror_tms = tms;
+assign mirror_tdi = tdi;
+assign mirror_tdo = tdo;
+
+wire clk_sys = clk_osc;
+wire rst_n_sys;
+wire trst_n;
+
+fpga_reset #(
+	.SHIFT (3)
+) rstgen (
+	.clk         (clk_sys),
+	.force_rst_n (1'b1),
+	.rst_n       (rst_n_sys)
+);
+
+reset_sync trst_sync_u (
+	.clk       (tck),
+	.rst_n_in  (rst_n_sys),
+	.rst_n_out (trst_n)
+);
+
+activity_led #(
+	.WIDTH (1 << 8),
+	.ACTIVE_LEVEL (1'b0)
+) tck_led_u (
+	.clk   (clk_sys),
+	.rst_n (rst_n_sys),
+	.i     (tck),
+	.o     (led)
+);
+
+example_soc #(
+	.CLK_MHZ             (12),
+	.EXTENSION_A         (1),
+	.EXTENSION_C         (0),
+	.EXTENSION_M         (1),
+	.EXTENSION_ZBA       (0),
+	.EXTENSION_ZBB       (0),
+	.EXTENSION_ZBC       (0),
+	.EXTENSION_ZBS       (0),
+	.EXTENSION_ZBKB      (0),
+	.EXTENSION_ZIFENCEI  (0),
+	.EXTENSION_XH3BEXTM  (0),
+	.EXTENSION_XH3PMPM   (0),
+	.EXTENSION_XH3POWER  (0),
+	.CSR_COUNTER         (0),
+	.U_MODE              (0),
+	.PMP_REGIONS         (0),
+	.BREAKPOINT_TRIGGERS (0),
+	.IRQ_PRIORITY_BITS   (0),
+	.REDUCED_BYPASS      (0),
+	.MULDIV_UNROLL       (1),
+	.MUL_FAST            (0),
+	.MUL_FASTER          (0),
+	.MULH_FAST           (0),
+	.FAST_BRANCHCMP      (1),
+	.BRANCH_PREDICTOR    (0)
+) soc_u (
+	.clk            (clk_sys),
+	.rst_n          (rst_n_sys),
+
+	.tck            (tck),
+	.trst_n         (trst_n),
+	.tms            (tms),
+	.tdi            (tdi),
+	.tdo            (tdo),
+
+	.uart_tx        (uart_tx),
+	.uart_rx        (uart_rx)
+);
+
+endmodule

Wren6991_Hazard3/example_soc/fpga/fpga_orangecrab_25f.f

@@ -0,0 +1,10 @@
+file fpga_orangecrab_25f.v
+file ../libfpga/common/reset_sync.v
+file ../libfpga/common/fpga_reset.v
+
+list ../soc/soc.f
+
+# ECP5 DTM is not in main SoC list because the JTAGG primitive doesn't exist
+# on most platforms
+list ../../hdl/debug/dtm/hazard3_ecp5_jtag_dtm.f
+

Wren6991_Hazard3/example_soc/fpga/fpga_orangecrab_25f.v

@@ -0,0 +1,98 @@
+/*****************************************************************************\
+|                        Copyright (C) 2021 Luke Wren                         |
+|                     SPDX-License-Identifier: Apache-2.0                     |
+\*****************************************************************************/
+
+`default_nettype none
+
+module fpga_orangecrab_25f (
+	input  wire       clk_osc,
+	output wire [7:0] dbg,
+
+	output wire       uart_tx,
+	input  wire       uart_rx,
+
+	output rgb_led0_r,
+	output rgb_led0_g,
+	output rgb_led0_b,
+
+	output rst_n,
+	input usr_btn
+);
+
+wire clk_sys = clk_osc;
+wire rst_n_sys;
+wire trst_n;
+
+fpga_reset #(
+	.SHIFT (3)
+) rstgen (
+	.clk         (clk_sys),
+	.force_rst_n (1'b1),
+	.rst_n       (rst_n_sys)
+);
+
+example_soc #(
+	.DTM_TYPE           ("ECP5"),
+	.SRAM_DEPTH         (1 << 14),
+	.CLK_MHZ            (48),
+
+	.EXTENSION_M         (1),
+	.EXTENSION_A         (1),
+	.EXTENSION_C         (0),
+	.EXTENSION_ZBA       (0),
+	.EXTENSION_ZBB       (0),
+	.EXTENSION_ZBC       (0),
+	.EXTENSION_ZBS       (0),
+	.EXTENSION_ZBKB      (0),
+	.EXTENSION_ZIFENCEI  (1),
+	.EXTENSION_XH3BEXTM  (0),
+	.EXTENSION_XH3PMPM   (0),
+	.EXTENSION_XH3POWER  (0),
+	.CSR_COUNTER         (1),
+	.MUL_FAST            (1),
+	.MUL_FASTER          (0),
+	.MULH_FAST           (0),
+	.MULDIV_UNROLL       (1),
+	.FAST_BRANCHCMP      (1),
+	.BRANCH_PREDICTOR    (1)
+) soc_u (
+	.clk     (clk_sys),
+	.rst_n   (rst_n_sys),
+
+	// JTAG connections provided internally by ECP5 JTAGG primitive
+	.tck     (1'b0),
+	.trst_n  (1'b0),
+	.tms     (1'b0),
+	.tdi     (1'b0),
+	.tdo     (/* unused */),
+
+	.uart_tx (uart_tx),
+	.uart_rx (uart_rx)
+);
+
+	// Create a 27 bit register
+	reg [26:0] counter = 0;
+
+	// Every positive edge increment register by 1
+	always @(posedge clk_sys) begin
+		counter <= counter + 1;
+	end
+
+	// Output inverted values of counter onto LEDs
+	assign rgb_led0_r = ~counter[24];
+	assign rgb_led0_g = ~counter[25];
+	assign rgb_led0_b = 0;
+
+	assign dbg = 8'hff;
+
+	// Reset logic on button press.
+	// this will enter the bootloader
+	reg reset_sr = 1'b1;
+	always @(posedge clk_sys) begin
+		reset_sr <= {usr_btn};
+	end
+	assign rst_n = reset_sr;
+
+
+endmodule

Wren6991_Hazard3/example_soc/fpga/fpga_ulx3s.f

@@ -0,0 +1,12 @@
+file fpga_ulx3s.v
+file pll_25_50.v
+file pll_25_40.v
+file ../libfpga/common/reset_sync.v
+file ../libfpga/common/fpga_reset.v
+
+list ../soc/soc.f
+
+# ECP5 DTM is not in main SoC list because the JTAGG primitive doesn't exist
+# on most platforms
+list ../../hdl/debug/dtm/hazard3_ecp5_jtag_dtm.f
+

Wren6991_Hazard3/example_soc/fpga/fpga_ulx3s.v

@@ -0,0 +1,75 @@
+/*****************************************************************************\
+|                        Copyright (C) 2021 Luke Wren                         |
+|                     SPDX-License-Identifier: Apache-2.0                     |
+\*****************************************************************************/
+
+`default_nettype none
+
+module fpga_ulx3s (
+	input  wire       clk_osc,
+	output wire [7:0] dbg,
+
+	output wire       uart_tx,
+	input  wire       uart_rx
+);
+
+wire clk_sys;
+wire pll_sys_locked;
+wire rst_n_sys;
+
+pll_25_50 pll_sys (
+	.clkin   (clk_osc),
+	.clkout0 (clk_sys),
+	.locked  (pll_sys_locked)
+);
+
+fpga_reset #(
+	.SHIFT (3)
+) rstgen (
+	.clk         (clk_sys),
+	.force_rst_n (pll_sys_locked),
+	.rst_n       (rst_n_sys)
+);
+
+example_soc #(
+	.DTM_TYPE           ("ECP5"),
+	.SRAM_DEPTH         (1 << 15),
+	.CLK_MHZ            (50),
+
+	.EXTENSION_M         (1),
+	.EXTENSION_A         (1),
+	.EXTENSION_C         (0),
+	.EXTENSION_ZBA       (0),
+	.EXTENSION_ZBB       (0),
+	.EXTENSION_ZBC       (0),
+	.EXTENSION_ZBS       (0),
+	.EXTENSION_ZBKB      (0),
+	.EXTENSION_ZIFENCEI  (1),
+	.EXTENSION_XH3BEXTM  (0),
+	.EXTENSION_XH3PMPM   (0),
+	.EXTENSION_XH3POWER  (0),
+	.CSR_COUNTER         (1),
+	.MUL_FAST            (1),
+	.MUL_FASTER          (0),
+	.MULH_FAST           (0),
+	.MULDIV_UNROLL       (1),
+	.FAST_BRANCHCMP      (1),
+	.BRANCH_PREDICTOR    (1)
+) soc_u (
+	.clk     (clk_sys),
+	.rst_n   (rst_n_sys),
+
+	// JTAG connections provided internally by ECP5 JTAGG primitive
+	.tck     (1'b0),
+	.trst_n  (1'b0),
+	.tms     (1'b0),
+	.tdi     (1'b0),
+	.tdo     (/* unused */),
+
+	.uart_tx (uart_tx),
+	.uart_rx (uart_rx)
+);
+
+assign dbg = 8'h00;
+
+endmodule

Wren6991_Hazard3/example_soc/fpga/pll_25_40.v

@@ -0,0 +1,46 @@
+// diamond 3.7 accepts this PLL
+// diamond 3.8-3.9 is untested
+// diamond 3.10 or higher is likely to abort with error about unable to use feedback signal
+// cause of this could be from wrong CPHASE/FPHASE parameters
+module pll_25_40
+(
+    input clkin, // 25 MHz, 0 deg
+    output clkout0, // 40 MHz, 0 deg
+    output locked
+);
+(* FREQUENCY_PIN_CLKI="25" *)
+(* FREQUENCY_PIN_CLKOP="40" *)
+(* ICP_CURRENT="12" *) (* LPF_RESISTOR="8" *) (* MFG_ENABLE_FILTEROPAMP="1" *) (* MFG_GMCREF_SEL="2" *)
+EHXPLLL #(
+        .PLLRST_ENA("DISABLED"),
+        .INTFB_WAKE("DISABLED"),
+        .STDBY_ENABLE("DISABLED"),
+        .DPHASE_SOURCE("DISABLED"),
+        .OUTDIVIDER_MUXA("DIVA"),
+        .OUTDIVIDER_MUXB("DIVB"),
+        .OUTDIVIDER_MUXC("DIVC"),
+        .OUTDIVIDER_MUXD("DIVD"),
+        .CLKI_DIV(5),
+        .CLKOP_ENABLE("ENABLED"),
+        .CLKOP_DIV(15),
+        .CLKOP_CPHASE(7),
+        .CLKOP_FPHASE(0),
+        .FEEDBK_PATH("CLKOP"),
+        .CLKFB_DIV(8)
+    ) pll_i (
+        .RST(1'b0),
+        .STDBY(1'b0),
+        .CLKI(clkin),
+        .CLKOP(clkout0),
+        .CLKFB(clkout0),
+        .CLKINTFB(),
+        .PHASESEL0(1'b0),
+        .PHASESEL1(1'b0),
+        .PHASEDIR(1'b1),
+        .PHASESTEP(1'b1),
+        .PHASELOADREG(1'b1),
+        .PLLWAKESYNC(1'b0),
+        .ENCLKOP(1'b0),
+        .LOCK(locked)
+	);
+endmodule

Wren6991_Hazard3/example_soc/fpga/pll_25_50.v

@@ -0,0 +1,46 @@
+// diamond 3.7 accepts this PLL
+// diamond 3.8-3.9 is untested
+// diamond 3.10 or higher is likely to abort with error about unable to use feedback signal
+// cause of this could be from wrong CPHASE/FPHASE parameters
+module pll_25_50
+(
+    input clkin, // 25 MHz, 0 deg
+    output clkout0, // 50 MHz, 0 deg
+    output locked
+);
+(* FREQUENCY_PIN_CLKI="25" *)
+(* FREQUENCY_PIN_CLKOP="50" *)
+(* ICP_CURRENT="12" *) (* LPF_RESISTOR="8" *) (* MFG_ENABLE_FILTEROPAMP="1" *) (* MFG_GMCREF_SEL="2" *)
+EHXPLLL #(
+        .PLLRST_ENA("DISABLED"),
+        .INTFB_WAKE("DISABLED"),
+        .STDBY_ENABLE("DISABLED"),
+        .DPHASE_SOURCE("DISABLED"),
+        .OUTDIVIDER_MUXA("DIVA"),
+        .OUTDIVIDER_MUXB("DIVB"),
+        .OUTDIVIDER_MUXC("DIVC"),
+        .OUTDIVIDER_MUXD("DIVD"),
+        .CLKI_DIV(1),
+        .CLKOP_ENABLE("ENABLED"),
+        .CLKOP_DIV(12),
+        .CLKOP_CPHASE(5),
+        .CLKOP_FPHASE(0),
+        .FEEDBK_PATH("CLKOP"),
+        .CLKFB_DIV(2)
+    ) pll_i (
+        .RST(1'b0),
+        .STDBY(1'b0),
+        .CLKI(clkin),
+        .CLKOP(clkout0),
+        .CLKFB(clkout0),
+        .CLKINTFB(),
+        .PHASESEL0(1'b0),
+        .PHASESEL1(1'b0),
+        .PHASEDIR(1'b1),
+        .PHASESTEP(1'b1),
+        .PHASELOADREG(1'b1),
+        .PLLWAKESYNC(1'b0),
+        .ENCLKOP(1'b0),
+        .LOCK(locked)
+	);
+endmodule

Wren6991_Hazard3/example_soc/icebreaker-openocd.cfg

@@ -0,0 +1,30 @@
+adapter driver ftdi
+
+# 30 MHz -- a bit exciting but it seems reliable
+adapter speed 30000
+ftdi_tdo_sample_edge falling
+
+# JTAG is on FTDI B channel so it doesn't inadvertently assert flash CS pin
+# (usually UART would be on the B channel).
+
+# Note TDO/TMS require two of the solder jumpers on the back of the board to
+# be bridged. On the v1.0e board these are jumpers J3/J4. To find these, look
+# for the box of 5 x 2 jumpers (with a few others hanging off the side) and
+# they are the two in the central column. They line up with the space in
+# between "Jump" and "for" in the silk text "Jump for FTDI FIFO".
+
+ftdi_device_desc "Dual RS232-HS"
+ftdi_vid_pid 0x0403 0x6010
+# Use BDBUS0-3 on iCEBreaker to avoid toggling flash chip select
+ftdi_channel 1
+
+ftdi_layout_init 0x0000 0xffff
+
+set _CHIPNAME hazard3
+jtag newtap $_CHIPNAME cpu -irlen 5
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME riscv -chain-position $_TARGETNAME
+
+gdb_report_data_abort enable
+init
+halt

Wren6991_Hazard3/example_soc/project_paths.mk

@@ -0,0 +1,2 @@
+# Link up to project root
+include $(dir $(abspath $(lastword $(MAKEFILE_LIST))))/../project_paths.mk

Wren6991_Hazard3/example_soc/soc/example_soc.v

@@ -0,0 +1,613 @@
+/*****************************************************************************\
+|                      Copyright (C) 2021-2022 Luke Wren                      |
+|                     SPDX-License-Identifier: Apache-2.0                     |
+\*****************************************************************************/
+
+// Example file integrating a Hazard3 processor, processor JTAG + debug
+// components, some memory and a UART.
+
+`default_nettype none
+
+module example_soc #(
+	parameter DTM_TYPE   = "JTAG",  // Can be "JTAG", "ECP5" or "XILINX7"
+	parameter SRAM_DEPTH = 1 << 15, // Default 32 kwords -> 128 kB
+	parameter CLK_MHZ    = 12,      // For timer timebase
+
+	`include "hazard3_config.vh"
+) (
+	// System clock + reset
+	input wire               clk,
+	input wire               rst_n,
+
+	// JTAG port to RISC-V JTAG-DTM
+	input  wire              tck,
+	input  wire              trst_n,
+	input  wire              tms,
+	input  wire              tdi,
+	output wire              tdo,
+
+	// IO
+	output wire              uart_tx,
+	input  wire              uart_rx
+);
+
+// ----------------------------------------------------------------------------
+// Processor debug
+
+wire              dmi_psel;
+wire              dmi_penable;
+wire              dmi_pwrite;
+wire [8:0]        dmi_paddr;
+wire [31:0]       dmi_pwdata;
+wire [31:0]       dmi_prdata;
+wire              dmi_pready;
+wire              dmi_pslverr;
+
+
+// TCK-domain DTM logic can force a hard reset
+wire dmihardreset_req;
+wire assert_dmi_reset = !rst_n || dmihardreset_req;
+wire rst_n_dmi;
+
+reset_sync dmi_reset_sync_u (
+	.clk       (clk),
+	.rst_n_in  (!assert_dmi_reset),
+	.rst_n_out (rst_n_dmi)
+);
+
+generate
+if (DTM_TYPE == "JTAG") begin
+
+	// Standard RISC-V JTAG-DTM connected to external IOs.
+	// JTAG-DTM IDCODE should be a JEP106-compliant ID:
+	localparam IDCODE = 32'hdeadbeef;
+
+	hazard3_jtag_dtm #(
+		.IDCODE (IDCODE)
+	) dtm_u (
+		.tck              (tck),
+		.trst_n           (trst_n),
+		.tms              (tms),
+		.tdi              (tdi),
+		.tdo              (tdo),
+
+		.dmihardreset_req (dmihardreset_req),
+
+		.clk_dmi          (clk),
+		.rst_n_dmi        (rst_n_dmi),
+
+		.dmi_psel         (dmi_psel),
+		.dmi_penable      (dmi_penable),
+		.dmi_pwrite       (dmi_pwrite),
+		.dmi_paddr        (dmi_paddr),
+		.dmi_pwdata       (dmi_pwdata),
+		.dmi_prdata       (dmi_prdata),
+		.dmi_pready       (dmi_pready),
+		.dmi_pslverr      (dmi_pslverr)
+	);
+
+end else if (DTM_TYPE == "ECP5") begin
+
+	// Attach RISC-V DTM's DTMCS/DMI registers to ECP5 ER1/ER2 registers. This
+	// allows the processor to be debugged through the ECP5 chip TAP, using
+	// regular upstream OpenOCD.
+
+	// Connects to ECP5 TAP internally by instantiating a JTAGG primitive.
+	assign tdo = 1'b0;
+
+	hazard3_ecp5_jtag_dtm dtm_u (
+		.dmihardreset_req (dmihardreset_req),
+
+		.clk_dmi          (clk),
+		.rst_n_dmi        (rst_n_dmi),
+
+		.dmi_psel         (dmi_psel),
+		.dmi_penable      (dmi_penable),
+		.dmi_pwrite       (dmi_pwrite),
+		.dmi_paddr        (dmi_paddr),
+		.dmi_pwdata       (dmi_pwdata),
+		.dmi_prdata       (dmi_prdata),
+		.dmi_pready       (dmi_pready),
+		.dmi_pslverr      (dmi_pslverr)
+	);
+
+end else if (DTM_TYPE == "XILINX7") begin
+
+	assign tdo = 1'b0;
+
+	hazard3_xilinx7_jtag_dtm dtm_u (
+		.dmihardreset_req (dmihardreset_req),
+
+		.clk_dmi          (clk),
+		.rst_n_dmi        (rst_n_dmi),
+
+		.dmi_psel         (dmi_psel),
+		.dmi_penable      (dmi_penable),
+		.dmi_pwrite       (dmi_pwrite),
+		.dmi_paddr        (dmi_paddr),
+		.dmi_pwdata       (dmi_pwdata),
+		.dmi_prdata       (dmi_prdata),
+		.dmi_pready       (dmi_pready),
+		.dmi_pslverr      (dmi_pslverr)
+	);
+
+end
+endgenerate
+
+
+localparam N_HARTS = 1;
+localparam XLEN = 32;
+
+wire                      sys_reset_req;
+wire                      sys_reset_done;
+wire [N_HARTS-1:0]        hart_reset_req;
+wire [N_HARTS-1:0]        hart_reset_done;
+
+wire [N_HARTS-1:0]        hart_req_halt;
+wire [N_HARTS-1:0]        hart_req_halt_on_reset;
+wire [N_HARTS-1:0]        hart_req_resume;
+wire [N_HARTS-1:0]        hart_halted;
+wire [N_HARTS-1:0]        hart_running;
+
+wire [N_HARTS*XLEN-1:0]   hart_data0_rdata;
+wire [N_HARTS*XLEN-1:0]   hart_data0_wdata;
+wire [N_HARTS-1:0]        hart_data0_wen;
+
+wire [N_HARTS*XLEN-1:0]   hart_instr_data;
+wire [N_HARTS-1:0]        hart_instr_data_vld;
+wire [N_HARTS-1:0]        hart_instr_data_rdy;
+wire [N_HARTS-1:0]        hart_instr_caught_exception;
+wire [N_HARTS-1:0]        hart_instr_caught_ebreak;
+
+wire [31:0]               sbus_addr;
+wire                      sbus_write;
+wire [1:0]                sbus_size;
+wire                      sbus_vld;
+wire                      sbus_rdy;
+wire                      sbus_err;
+wire [31:0]               sbus_wdata;
+wire [31:0]               sbus_rdata;
+
+hazard3_dm #(
+	.N_HARTS      (N_HARTS),
+	.HAVE_SBA     (0),
+	.NEXT_DM_ADDR (0)
+) dm (
+	.clk                         (clk),
+	.rst_n                       (rst_n),
+
+	.dmi_psel                    (dmi_psel),
+	.dmi_penable                 (dmi_penable),
+	.dmi_pwrite                  (dmi_pwrite),
+	.dmi_paddr                   (dmi_paddr),
+	.dmi_pwdata                  (dmi_pwdata),
+	.dmi_prdata                  (dmi_prdata),
+	.dmi_pready                  (dmi_pready),
+	.dmi_pslverr                 (dmi_pslverr),
+
+	.sys_reset_req               (sys_reset_req),
+	.sys_reset_done              (sys_reset_done),
+	.hart_reset_req              (hart_reset_req),
+	.hart_reset_done             (hart_reset_done),
+
+	.hart_req_halt               (hart_req_halt),
+	.hart_req_halt_on_reset      (hart_req_halt_on_reset),
+	.hart_req_resume             (hart_req_resume),
+	.hart_halted                 (hart_halted),
+	.hart_running                (hart_running),
+
+	.hart_data0_rdata            (hart_data0_rdata),
+	.hart_data0_wdata            (hart_data0_wdata),
+	.hart_data0_wen              (hart_data0_wen),
+
+	.hart_instr_data             (hart_instr_data),
+	.hart_instr_data_vld         (hart_instr_data_vld),
+	.hart_instr_data_rdy         (hart_instr_data_rdy),
+	.hart_instr_caught_exception (hart_instr_caught_exception),
+	.hart_instr_caught_ebreak    (hart_instr_caught_ebreak),
+
+	.sbus_addr                   (sbus_addr),
+	.sbus_write                  (sbus_write),
+	.sbus_size                   (sbus_size),
+	.sbus_vld                    (sbus_vld),
+	.sbus_rdy                    (sbus_rdy),
+	.sbus_err                    (sbus_err),
+	.sbus_wdata                  (sbus_wdata),
+	.sbus_rdata                  (sbus_rdata)
+);
+
+
+// Generate resynchronised reset for CPU based on upstream system reset and on
+// system/hart reset requests from DM.
+
+wire assert_cpu_reset = !rst_n || sys_reset_req || hart_reset_req[0];
+wire rst_n_cpu;
+
+reset_sync cpu_reset_sync (
+	.clk       (clk),
+	.rst_n_in  (!assert_cpu_reset),
+	.rst_n_out (rst_n_cpu)
+);
+
+// Still some work to be done on the reset handshake -- this ought to be
+// resynchronised to DM's reset domain here, and the DM should wait for a
+// rising edge after it has asserted the reset pulse, to make sure the tail
+// of the previous "done" is not passed on.
+assign sys_reset_done = rst_n_cpu;
+assign hart_reset_done = rst_n_cpu;
+
+// ----------------------------------------------------------------------------
+// Processor
+
+wire [W_ADDR-1:0] proc_haddr;
+wire              proc_hwrite;
+wire [1:0]        proc_htrans;
+wire [2:0]        proc_hsize;
+wire [2:0]        proc_hburst;
+wire [3:0]        proc_hprot;
+wire              proc_hmastlock;
+wire [7:0]        proc_hmaster;
+wire              proc_hexcl;
+wire              proc_hready;
+wire              proc_hresp;
+wire              proc_hexokay = 1'b1; // No global monitor
+wire [W_DATA-1:0] proc_hwdata;
+wire [W_DATA-1:0] proc_hrdata;
+
+wire              pwrup_req;
+wire              unblock_out;
+
+wire              uart_irq;
+wire              timer_irq;
+
+hazard3_cpu_1port #(
+	// These must have the values given here for you to end up with a useful SoC:
+	.RESET_VECTOR    (32'h0000_0040),
+	.MTVEC_INIT      (32'h0000_0000),
+	.CSR_M_MANDATORY (1),
+	.CSR_M_TRAP      (1),
+	.DEBUG_SUPPORT   (1),
+	.NUM_IRQS        (1),
+	.RESET_REGFILE   (0),
+	// Can be overridden from the defaults in hazard3_config.vh during
+	// instantiation of example_soc():
+	.EXTENSION_A         (EXTENSION_A),
+	.EXTENSION_C         (EXTENSION_C),
+	.EXTENSION_E         (EXTENSION_E),
+	.EXTENSION_M         (EXTENSION_M),
+	.EXTENSION_ZBA       (EXTENSION_ZBA),
+	.EXTENSION_ZBB       (EXTENSION_ZBB),
+	.EXTENSION_ZBC       (EXTENSION_ZBC),
+	.EXTENSION_ZBKB      (EXTENSION_ZBKB),
+	.EXTENSION_ZBKX      (EXTENSION_ZBKX),
+	.EXTENSION_ZBS       (EXTENSION_ZBS),
+	.EXTENSION_ZCB       (EXTENSION_ZCB),
+	.EXTENSION_ZCLSD     (EXTENSION_ZCLSD),
+	.EXTENSION_ZCMP      (EXTENSION_ZCMP),
+	.EXTENSION_ZIFENCEI  (EXTENSION_ZIFENCEI),
+	.EXTENSION_ZILSD     (EXTENSION_ZILSD),
+	.EXTENSION_XH3BEXTM  (EXTENSION_XH3BEXTM),
+	.EXTENSION_XH3IRQ    (EXTENSION_XH3IRQ),
+	.EXTENSION_XH3PMPM   (EXTENSION_XH3PMPM),
+	.EXTENSION_XH3POWER  (EXTENSION_XH3POWER),
+	.CSR_COUNTER         (CSR_COUNTER),
+	.U_MODE              (U_MODE),
+	.PMP_REGIONS         (PMP_REGIONS),
+	.PMP_GRAIN           (PMP_GRAIN),
+	.PMP_HARDWIRED       (PMP_HARDWIRED),
+	.PMP_HARDWIRED_ADDR  (PMP_HARDWIRED_ADDR),
+	.PMP_HARDWIRED_CFG   (PMP_HARDWIRED_CFG),
+	.MVENDORID_VAL       (MVENDORID_VAL),
+	.BREAKPOINT_TRIGGERS (BREAKPOINT_TRIGGERS),
+	.IRQ_PRIORITY_BITS   (IRQ_PRIORITY_BITS),
+	.REDUCED_BYPASS      (REDUCED_BYPASS),
+	.MULDIV_UNROLL       (MULDIV_UNROLL),
+	.MUL_FAST            (MUL_FAST),
+	.MUL_FASTER          (MUL_FASTER),
+	.MULH_FAST           (MULH_FAST),
+	.FAST_BRANCHCMP      (FAST_BRANCHCMP),
+	.BRANCH_PREDICTOR    (BRANCH_PREDICTOR),
+	.MTVEC_WMASK         (MTVEC_WMASK)
+) cpu (
+	.clk                        (clk),
+	.clk_always_on              (clk),
+	.rst_n                      (rst_n_cpu),
+
+	.pwrup_req                  (pwrup_req),
+	.pwrup_ack                  (pwrup_req),   // Tied back
+	.clk_en                     (/* unused */),
+	.unblock_out                (unblock_out),
+	.unblock_in                 (unblock_out), // Tied back
+
+	.haddr                      (proc_haddr),
+	.hwrite                     (proc_hwrite),
+	.htrans                     (proc_htrans),
+	.hsize                      (proc_hsize),
+	.hburst                     (proc_hburst),
+	.hprot                      (proc_hprot),
+	.hmastlock                  (proc_hmastlock),
+	.hmaster                    (proc_hmaster),
+	.hexcl                      (proc_hexcl),
+	.hready                     (proc_hready),
+	.hresp                      (proc_hresp),
+	.hexokay                    (proc_hexokay),
+	.hwdata                     (proc_hwdata),
+	.hrdata                     (proc_hrdata),
+
+	.fence_i_vld                (/* unused */),
+	.fence_d_vld                (/* unused */),
+	.fence_rdy                  (1'b1),
+
+	.dbg_req_halt               (hart_req_halt),
+	.dbg_req_halt_on_reset      (hart_req_halt_on_reset),
+	.dbg_req_resume             (hart_req_resume),
+	.dbg_halted                 (hart_halted),
+	.dbg_running                (hart_running),
+
+	.dbg_data0_rdata            (hart_data0_rdata),
+	.dbg_data0_wdata            (hart_data0_wdata),
+	.dbg_data0_wen              (hart_data0_wen),
+
+	.dbg_instr_data             (hart_instr_data),
+	.dbg_instr_data_vld         (hart_instr_data_vld),
+	.dbg_instr_data_rdy         (hart_instr_data_rdy),
+	.dbg_instr_caught_exception (hart_instr_caught_exception),
+	.dbg_instr_caught_ebreak    (hart_instr_caught_ebreak),
+
+	.dbg_sbus_addr              (sbus_addr),
+	.dbg_sbus_write             (sbus_write),
+	.dbg_sbus_size              (sbus_size),
+	.dbg_sbus_vld               (sbus_vld),
+	.dbg_sbus_rdy               (sbus_rdy),
+	.dbg_sbus_err               (sbus_err),
+	.dbg_sbus_wdata             (sbus_wdata),
+	.dbg_sbus_rdata             (sbus_rdata),
+
+	.mhartid_val                (32'd0),
+	.eco_version                (4'd0),
+
+	.irq                        (uart_irq),
+
+	.soft_irq                   (1'b0),
+	.timer_irq                  (timer_irq)
+);
+
+
+// ----------------------------------------------------------------------------
+// Bus fabric
+
+// - 128 kB SRAM at... 0x0000_0000
+// - System timer at.. 0x4000_0000
+// - UART at.......... 0x4000_4000
+
+// AHBL layer
+
+wire               sram0_hready_resp;
+wire               sram0_hready;
+wire               sram0_hresp;
+wire [W_ADDR-1:0]  sram0_haddr;
+wire               sram0_hwrite;
+wire [1:0]         sram0_htrans;
+wire [2:0]         sram0_hsize;
+wire [2:0]         sram0_hburst;
+wire [3:0]         sram0_hprot;
+wire               sram0_hmastlock;
+wire [W_DATA-1:0]  sram0_hwdata;
+wire [W_DATA-1:0]  sram0_hrdata;
+
+wire               bridge_hready_resp;
+wire               bridge_hready;
+wire               bridge_hresp;
+wire [W_ADDR-1:0]  bridge_haddr;
+wire               bridge_hwrite;
+wire [1:0]         bridge_htrans;
+wire [2:0]         bridge_hsize;
+wire [2:0]         bridge_hburst;
+wire [3:0]         bridge_hprot;
+wire               bridge_hmastlock;
+wire [W_DATA-1:0]  bridge_hwdata;
+wire [W_DATA-1:0]  bridge_hrdata;
+
+ahbl_splitter #(
+	.N_PORTS     (2),
+	.ADDR_MAP    (64'h40000000_00000000),
+	.ADDR_MASK   (64'he0000000_e0000000)
+) splitter_u (
+	.clk             (clk),
+	.rst_n           (rst_n),
+
+	.src_hready_resp (proc_hready   ),
+	.src_hready      (proc_hready   ),
+	.src_hresp       (proc_hresp    ),
+	.src_haddr       (proc_haddr    ),
+	.src_hwrite      (proc_hwrite   ),
+	.src_htrans      (proc_htrans   ),
+	.src_hsize       (proc_hsize    ),
+	.src_hburst      (proc_hburst   ),
+	.src_hprot       (proc_hprot    ),
+	.src_hmastlock   (proc_hmastlock),
+	.src_hwdata      (proc_hwdata   ),
+	.src_hrdata      (proc_hrdata   ),
+
+	.dst_hready_resp ({bridge_hready_resp , sram0_hready_resp}),
+	.dst_hready      ({bridge_hready      , sram0_hready     }),
+	.dst_hresp       ({bridge_hresp       , sram0_hresp      }),
+	.dst_haddr       ({bridge_haddr       , sram0_haddr      }),
+	.dst_hwrite      ({bridge_hwrite      , sram0_hwrite     }),
+	.dst_htrans      ({bridge_htrans      , sram0_htrans     }),
+	.dst_hsize       ({bridge_hsize       , sram0_hsize      }),
+	.dst_hburst      ({bridge_hburst      , sram0_hburst     }),
+	.dst_hprot       ({bridge_hprot       , sram0_hprot      }),
+	.dst_hmastlock   ({bridge_hmastlock   , sram0_hmastlock  }),
+	.dst_hwdata      ({bridge_hwdata      , sram0_hwdata     }),
+	.dst_hrdata      ({bridge_hrdata      , sram0_hrdata     })
+);
+
+// APB layer
+
+wire        bridge_psel;
+wire        bridge_penable;
+wire        bridge_pwrite;
+wire [15:0] bridge_paddr;
+wire [31:0] bridge_pwdata;
+wire [31:0] bridge_prdata;
+wire        bridge_pready;
+wire        bridge_pslverr;
+
+wire        uart_psel;
+wire        uart_penable;
+wire        uart_pwrite;
+wire [15:0] uart_paddr;
+wire [31:0] uart_pwdata;
+wire [31:0] uart_prdata;
+wire        uart_pready;
+wire        uart_pslverr;
+
+wire        timer_psel;
+wire        timer_penable;
+wire        timer_pwrite;
+wire [15:0] timer_paddr;
+wire [31:0] timer_pwdata;
+wire [31:0] timer_prdata;
+wire        timer_pready;
+wire        timer_pslverr;
+
+ahbl_to_apb apb_bridge_u (
+	.clk               (clk),
+	.rst_n             (rst_n),
+
+	.ahbls_hready      (bridge_hready),
+	.ahbls_hready_resp (bridge_hready_resp),
+	.ahbls_hresp       (bridge_hresp),
+	.ahbls_haddr       (bridge_haddr),
+	.ahbls_hwrite      (bridge_hwrite),
+	.ahbls_htrans      (bridge_htrans),
+	.ahbls_hsize       (bridge_hsize),
+	.ahbls_hburst      (bridge_hburst),
+	.ahbls_hprot       (bridge_hprot),
+	.ahbls_hmastlock   (bridge_hmastlock),
+	.ahbls_hwdata      (bridge_hwdata),
+	.ahbls_hrdata      (bridge_hrdata),
+
+	.apbm_paddr        (bridge_paddr),
+	.apbm_psel         (bridge_psel),
+	.apbm_penable      (bridge_penable),
+	.apbm_pwrite       (bridge_pwrite),
+	.apbm_pwdata       (bridge_pwdata),
+	.apbm_pready       (bridge_pready),
+	.apbm_prdata       (bridge_prdata),
+	.apbm_pslverr      (bridge_pslverr)
+);
+
+apb_splitter #(
+	.N_SLAVES   (2),
+	.ADDR_MAP   (32'h4000_0000),
+	.ADDR_MASK  (32'hc000_c000)
+) inst_apb_splitter (
+	.apbs_paddr   (bridge_paddr),
+	.apbs_psel    (bridge_psel),
+	.apbs_penable (bridge_penable),
+	.apbs_pwrite  (bridge_pwrite),
+	.apbs_pwdata  (bridge_pwdata),
+	.apbs_pready  (bridge_pready),
+	.apbs_prdata  (bridge_prdata),
+	.apbs_pslverr (bridge_pslverr),
+
+	.apbm_paddr   ({uart_paddr   , timer_paddr  }),
+	.apbm_psel    ({uart_psel    , timer_psel   }),
+	.apbm_penable ({uart_penable , timer_penable}),
+	.apbm_pwrite  ({uart_pwrite  , timer_pwrite }),
+	.apbm_pwdata  ({uart_pwdata  , timer_pwdata }),
+	.apbm_pready  ({uart_pready  , timer_pready }),
+	.apbm_prdata  ({uart_prdata  , timer_prdata }),
+	.apbm_pslverr ({uart_pslverr , timer_pslverr})
+);
+
+// ----------------------------------------------------------------------------
+// Memory and peripherals
+
+// No preloaded bootloader -- just use the debugger! (the processor will
+// actually enter an infinite crash loop after reset if memory is
+// zero-initialised so don't leave the little guy hanging too long)
+
+ahb_sync_sram #(
+	.DEPTH (SRAM_DEPTH)
+) sram0 (
+	.clk               (clk),
+	.rst_n             (rst_n),
+
+	.ahbls_hready_resp (sram0_hready_resp),
+	.ahbls_hready      (sram0_hready),
+	.ahbls_hresp       (sram0_hresp),
+	.ahbls_haddr       (sram0_haddr),
+	.ahbls_hwrite      (sram0_hwrite),
+	.ahbls_htrans      (sram0_htrans),
+	.ahbls_hsize       (sram0_hsize),	
+	.ahbls_hburst      (sram0_hburst),
+	.ahbls_hprot       (sram0_hprot),
+	.ahbls_hmastlock   (sram0_hmastlock),
+	.ahbls_hwdata      (sram0_hwdata),
+	.ahbls_hrdata      (sram0_hrdata)
+);
+
+uart_mini uart_u (
+	.clk          (clk),
+	.rst_n        (rst_n),
+
+	.apbs_psel    (uart_psel),
+	.apbs_penable (uart_penable),
+	.apbs_pwrite  (uart_pwrite),
+	.apbs_paddr   (uart_paddr),
+	.apbs_pwdata  (uart_pwdata),
+	.apbs_prdata  (uart_prdata),
+	.apbs_pready  (uart_pready),
+	.apbs_pslverr (uart_pslverr),
+
+	.rx           (uart_rx),
+	.tx           (uart_tx),
+	.cts          (1'b0),
+	.rts          (/* unused */),
+	.irq          (uart_irq),
+	.dreq         (/* unused */)
+);
+
+// Microsecond timebase for timer
+
+reg [$clog2(CLK_MHZ)-1:0] timer_tick_ctr;
+reg                       timer_tick;
+
+always @ (posedge clk or negedge rst_n) begin
+	if (!rst_n) begin
+		timer_tick_ctr <= {$clog2(CLK_MHZ){1'b0}};
+		timer_tick <= 1'b0;
+	end else begin
+		if (|timer_tick_ctr) begin
+			timer_tick_ctr <= timer_tick_ctr - 1'b1;
+		end else begin
+			timer_tick_ctr <= CLK_MHZ - 1;
+		end
+		timer_tick <= ~|timer_tick_ctr;
+	end
+end
+
+hazard3_riscv_timer timer_u (
+	.clk       (clk),
+	.rst_n     (rst_n),
+
+	.psel      (timer_psel),
+	.penable   (timer_penable),
+	.pwrite    (timer_pwrite),
+	.paddr     (timer_paddr),
+	.pwdata    (timer_pwdata),
+	.prdata    (timer_prdata),
+	.pready    (timer_pready),
+	.pslverr   (timer_pslverr),
+
+	.dbg_halt  (&hart_halted),
+
+	.tick      (timer_tick),
+
+	.timer_irq (timer_irq)
+);
+
+endmodule

Wren6991_Hazard3/example_soc/soc/peri/hazard3_riscv_timer.f

@@ -0,0 +1,2 @@
+file hazard3_riscv_timer.v
+file ../../../hdl/debug/cdc/hazard3_sync_1bit.v

Wren6991_Hazard3/example_soc/soc/peri/hazard3_riscv_timer.v

@@ -0,0 +1,142 @@
+/*****************************************************************************\
+|                        Copyright (C) 2022 Luke Wren                         |
+|                     SPDX-License-Identifier: Apache-2.0                     |
+\*****************************************************************************/
+
+`default_nettype none
+
+// Basic implementation of standard 64-bit RISC-V timer with 32-bit APB.
+
+// TICK_IS_NRZ = 1: tick is an NRZ signal that is asynchronous to clk.
+// TICK_IS_NRZ = 0: tick is a level-sensitive signal that is synchronous to clk.
+
+module hazard3_riscv_timer #(
+	parameter TICK_IS_NRZ = 0
+) (
+	input  wire               clk,
+	input  wire               rst_n,
+
+	input  wire [15:0]        paddr,
+	input  wire               psel,
+	input  wire               penable,
+	input  wire               pwrite,
+	input  wire [31:0]        pwdata,
+	output reg  [31:0]        prdata,
+	output wire               pready,
+	output wire               pslverr,
+
+	input  wire               dbg_halt,
+	input  wire               tick,
+
+	output reg                timer_irq
+);
+
+localparam ADDR_CTRL      = 16'h0000;
+localparam ADDR_MTIME     = 16'h0008;
+localparam ADDR_MTIMEH    = 16'h000c;
+localparam ADDR_MTIMECMP  = 16'h0010;
+localparam ADDR_MTIMECMPH = 16'h0014;
+
+// ----------------------------------------------------------------------------
+// Timer tick logic
+
+wire tick_event;
+
+generate
+if (TICK_IS_NRZ) begin: edge_detect
+
+	wire tick_nrz_sync;
+
+	hazard3_sync_1bit tick_sync_u (
+		.clk    (clk),
+		.rst_n  (rst_n),
+		.i      (tick),
+		.o      (tick_nrz_sync)
+	);
+
+	reg tick_nrz_sync_prev;
+	always @ (posedge clk or negedge rst_n) begin
+		if (!rst_n) begin
+			tick_nrz_sync_prev <= 1'b0;
+		end else begin
+			tick_nrz_sync_prev <= tick_nrz_sync;
+		end
+	end
+
+	assign tick_event = tick_nrz_sync ^ tick_nrz_sync_prev;
+
+end else begin: no_edge_detect
+
+	assign tick_event = tick;
+
+end
+endgenerate
+
+reg ctrl_en;
+wire tick_now = tick_event && ctrl_en && !dbg_halt;
+
+// ----------------------------------------------------------------------------
+// Counter registers
+
+wire bus_write = pwrite && psel && penable;
+wire bus_read = !pwrite && psel && penable;
+
+always @ (posedge clk or negedge rst_n) begin
+	if (!rst_n) begin
+		ctrl_en <= 1'b1;
+	end else if (bus_write && paddr == ADDR_CTRL) begin
+		ctrl_en <= pwdata[0];
+	end
+end
+
+reg [63:0] mtime;
+
+always @ (posedge clk or negedge rst_n) begin
+	if (!rst_n) begin
+		mtime <= 64'h0;
+	end else begin
+		if (tick_now)
+			mtime <= mtime + 1'b1;
+		if (bus_write && paddr == ADDR_MTIME)
+			mtime[31:0] <= pwdata;
+		if (bus_write && paddr == ADDR_MTIMEH)
+			mtime[63:32] <= pwdata;
+	end
+end
+
+// mtimecmp is stored inverted for minor LUT savings on iCE40
+reg  [63:0] mtimecmp;
+wire [64:0] cmp_diff = {1'b0, mtime} + {1'b0, mtimecmp} + 65'd1;
+
+always @ (posedge clk or negedge rst_n) begin
+	if (!rst_n) begin
+		mtimecmp <= 64'h0;
+		timer_irq <= 1'b0;
+	end else begin
+		if (bus_write && paddr == ADDR_MTIMECMP)
+			mtimecmp[31:0] <= ~pwdata;
+		if (bus_write && paddr == ADDR_MTIMECMPH)
+			mtimecmp[63:32] <= ~pwdata;
+		timer_irq <= cmp_diff[64];
+	end
+end
+
+always @ (*) begin
+	case (paddr)
+	ADDR_CTRL:      prdata = {31'h0, ctrl_en};
+	ADDR_MTIME:     prdata = mtime[31:0];
+	ADDR_MTIMEH:    prdata = mtime[63:32];
+	ADDR_MTIMECMP:  prdata = ~mtimecmp[31:0];
+	ADDR_MTIMECMPH: prdata = ~mtimecmp[63:32];
+	default:        prdata = 32'h0;
+	endcase
+end
+
+assign pready = 1'b1;
+assign pslverr = 1'b0;
+
+endmodule
+
+`ifndef YOSYS
+`default_nettype none
+`endif

Wren6991_Hazard3/example_soc/soc/soc.f

@@ -0,0 +1,27 @@
+# SoC integration file
+
+file example_soc.v
+
+# CPU + debug components
+
+list $HDL/hazard3.f
+list $HDL/debug/dtm/hazard3_jtag_dtm.f
+list $HDL/debug/dm/hazard3_dm.f
+
+# RISC-V timer
+
+list peri/hazard3_riscv_timer.f
+
+# Generic SoC components from libfpga
+
+file ../libfpga/common/reset_sync.v
+
+list ../libfpga/peris/uart/uart.f
+list ../libfpga/peris/spi_03h_xip/spi_03h_xip.f
+list ../libfpga/mem/ahb_cache.f
+list ../libfpga/mem/ahb_sync_sram.f
+
+list ../libfpga/busfabric/ahbl_crossbar.f
+file ../libfpga/busfabric/ahbl_to_apb.v
+file ../libfpga/busfabric/apb_splitter.v
+

Wren6991_Hazard3/example_soc/synth/.gitignore

@@ -0,0 +1,10 @@
+srcs.mk
+*.blif
+*.asc
+*.hex
+*.bin
+*.json
+*.log
+*.config
+*.svf
+*.bit

Wren6991_Hazard3/example_soc/synth/Icebreaker.mk

@@ -0,0 +1,14 @@
+include ../project_paths.mk
+
+CHIPNAME=fpga_icebreaker
+DOTF=../fpga/fpga_icebreaker.f
+SYNTH_OPT=-dsp
+PNR_OPT=--timing-allow-fail --detailed-timing-report
+
+DEVICE=up5k
+PACKAGE=sg48
+
+include $(SCRIPTS)/synth_ice40.mk
+
+prog: bit
+	iceprog $(CHIPNAME).bin

Wren6991_Hazard3/example_soc/synth/Makefile

@@ -0,0 +1 @@
+include Icebreaker.mk

Wren6991_Hazard3/example_soc/synth/ULX3S.mk

@@ -0,0 +1,20 @@
+include ../project_paths.mk
+
+CHIPNAME=fpga_ulx3s
+TOP=fpga_ulx3s
+DOTF=../fpga/fpga_ulx3s.f
+
+SYNTH_OPT=-abc9
+PNR_OPT=--timing-allow-fail
+
+DEVICE=um5g-85k
+PACKAGE=CABGA381
+
+include $(SCRIPTS)/synth_ecp5.mk
+
+# Get ujprog from: git@github.com:emard/tools.git
+prog: bit
+	ujprog $(CHIPNAME).bit
+
+flash: bit
+	ujprog -j flash $(CHIPNAME).bit

Wren6991_Hazard3/example_soc/synth/fpga_icebreaker.pcf

@@ -0,0 +1,43 @@
+# 12 MHz oscillator
+set_io clk_osc 35
+
+# JTAG is on FTDI B channel so it doesn't inadvertently assert flash CS pin
+# (usually UART would be on the B channel).
+
+# Note TDO/TMS require two of the solder jumpers on the back of the board to
+# be bridged. On the v1.0e board these are jumpers J3/J4. To find these, look
+# for the box of 5 x 2 jumpers (with a few others hanging off the side) and
+# they are the two in the central column. They line up with the space in
+# between "Jump" and "for" in the silk text "Jump for FTDI FIFO".
+
+set_io tck  6 # FTDI BDBUS0
+set_io tdi  9 # FTDI BDBUS1
+set_io tdo 18 # FTDI BDBUS2
+set_io tms 19 # FTDI BDBUS3
+
+# UART is moved over to FTDI A channel -- this means flash is inaccessible
+# (and stays in a quiescent state since CSn is disconnected and pulled high)
+set_io uart_rx 15 # FTDI ADBUS0, flash SCK, iCE SCK
+set_io uart_tx 14 # FTDI ADBUS1, flash MOSI, iCE SO (if jumper J15 connected)
+
+set_io led 37 # Green on main board
+
+# # Buttons
+# set_io dpad_u 20 # Snapoff top
+# set_io dpad_d 18 # Snapoff bottom
+# set_io dpad_l 10 # Main board
+# set_io dpad_r 19 # Snapoff middle
+
+set_io mirror_tck 27 # Left on snapoff   (L2)
+set_io mirror_tms 25 # Right on snapoff  (L3)
+set_io mirror_tdi 23 # Top on snapoff    (L4)
+set_io mirror_tdo 21 # Bottom on snapoff (L5)
+
+# # LEDs
+# set_io led[0] 37 # Green on main board
+# set_io led[1] 11 # Red on main board
+# set_io led[2] 26 # Middle on snapoff (L1)
+# set_io led[3] 27 # Left on snapoff   (L2)
+# set_io led[4] 25 # Right on snapoff  (L3)
+# set_io led[5] 23 # Top on snapoff    (L4)
+# set_io led[6] 21 # Bottom on snapoff (L5)

Wren6991_Hazard3/example_soc/synth/fpga_orangecrab_25f.lpf

@@ -0,0 +1,44 @@
+# Reference: https://github.com/emard/ulx3s/blob/master/doc/constraints/ulx3s_v20.lpf
+
+LOCATE COMP "clk_osc" SITE "A9";
+IOBUF PORT "clk_osc" PULLMODE=NONE IO_TYPE=LVCMOS33;
+FREQUENCY PORT "clk_osc" 48 MHZ;
+
+# UART TX/RX (from FPGA's point of view, i.e. TX is an output)
+
+LOCATE COMP "uart_tx" SITE "N17"; # FPGA transmits to ftdi
+LOCATE COMP "uart_rx" SITE "M18"; # FPGA receives from ftdi
+IOBUF  PORT "uart_tx" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "uart_rx" PULLMODE=UP IO_TYPE=LVCMOS33;
+
+# 8 pins on an IO header for bringing signals out to a logic analyser
+
+LOCATE COMP "dbg[0]"  SITE "H2"; # PCLK      # "gn[0]"
+LOCATE COMP "dbg[1]"  SITE "A8"; # PCLK      # "gn[1]"
+LOCATE COMP "dbg[2]"  SITE "B8"; # GR_PCLK   # "gn[2]"
+LOCATE COMP "dbg[3]"  SITE "C8";             # "gn[3]"
+LOCATE COMP "dbg[4]"  SITE "B9"; # PCLK      # "gp[0]"
+LOCATE COMP "dbg[5]"  SITE "B10"; # PCLK      # "gp[1]"
+LOCATE COMP "dbg[6]"  SITE "L4";  # GR_PCLK   # "gp[2]"
+LOCATE COMP "dbg[7]"  SITE "N3";              # "gp[3]"
+
+IOBUF PORT  "dbg[0]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT  "dbg[1]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT  "dbg[2]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT  "dbg[3]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT  "dbg[4]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT  "dbg[5]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT  "dbg[6]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT  "dbg[7]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+
+LOCATE COMP "rgb_led0_r" SITE "K4";
+IOBUF PORT "rgb_led0_r" IO_TYPE=LVCMOS33;
+LOCATE COMP "rgb_led0_g" SITE "M3";
+IOBUF PORT "rgb_led0_g" IO_TYPE=LVCMOS33;
+LOCATE COMP "rgb_led0_b" SITE "J3";
+IOBUF PORT "rgb_led0_b" IO_TYPE=LVCMOS33;
+
+LOCATE COMP "usr_btn" SITE "J17";
+IOBUF PORT "usr_btn" IO_TYPE=SSTL135_I;
+LOCATE COMP "rst_n" SITE "V17";
+IOBUF PORT "rst_n" IO_TYPE=LVCMOS33;

Wren6991_Hazard3/example_soc/synth/fpga_ulx3s.lpf

@@ -0,0 +1,32 @@
+# Reference: https://github.com/emard/ulx3s/blob/master/doc/constraints/ulx3s_v20.lpf
+
+LOCATE COMP "clk_osc" SITE "G2";
+IOBUF PORT "clk_osc" PULLMODE=NONE IO_TYPE=LVCMOS33;
+FREQUENCY PORT "clk_osc" 25 MHZ;
+
+# UART TX/RX (from FPGA's point of view, i.e. TX is an output)
+
+LOCATE COMP "uart_tx" SITE "L4"; # FPGA transmits to ftdi
+LOCATE COMP "uart_rx" SITE "M1"; # FPGA receives from ftdi
+IOBUF  PORT "uart_tx" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF  PORT "uart_rx" PULLMODE=UP IO_TYPE=LVCMOS33;
+
+# 8 pins on an IO header for bringing signals out to a logic analyser
+
+LOCATE COMP "dbg[0]"  SITE "C11"; # PCLK      # "gn[0]"
+LOCATE COMP "dbg[1]"  SITE "A11"; # PCLK      # "gn[1]"
+LOCATE COMP "dbg[2]"  SITE "B10"; # GR_PCLK   # "gn[2]"
+LOCATE COMP "dbg[3]"  SITE "C10";             # "gn[3]"
+LOCATE COMP "dbg[4]"  SITE "B11"; # PCLK      # "gp[0]"
+LOCATE COMP "dbg[5]"  SITE "A10"; # PCLK      # "gp[1]"
+LOCATE COMP "dbg[6]"  SITE "A9";  # GR_PCLK   # "gp[2]"
+LOCATE COMP "dbg[7]"  SITE "B9";              # "gp[3]"
+
+IOBUF PORT  "dbg[0]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT  "dbg[1]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT  "dbg[2]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT  "dbg[3]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT  "dbg[4]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT  "dbg[5]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT  "dbg[6]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
+IOBUF PORT  "dbg[7]" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;

Wren6991_Hazard3/example_soc/synth/orangecrab-25f.mk

@@ -0,0 +1,23 @@
+CHIPNAME=fpga_orangecrab_25f
+TOP=fpga_orangecrab_25f
+DOTF=../fpga/fpga_orangecrab_25f.f
+
+SYNTH_OPT=-abc9
+PNR_OPT=--timing-allow-fail
+
+DEVICE=25k
+PACKAGE=CSFBGA285
+
+DEVICE_IDCODE=0x41111043
+
+include $(SCRIPTS)/synth_ecp5.mk
+
+$(CHIPNAME).dfu: bit
+	cp $(CHIPNAME).bit $@
+	dfu-suffix -v 1209 -p 5af0 -a $@
+
+prog: bit
+	ujprog $(CHIPNAME).bit
+
+flash: $(CHIPNAME).dfu
+	dfu-util -d 1209:5af0 -D $<

Wren6991_Hazard3/example_soc/synth_vivado/.gitignore

@@ -0,0 +1,8 @@
+*.dcp
+*.log
+*.jou
+*.bit
+*.rpt
+*.txt
+.Xil
+filelist.tcl