Add batch 10 (abdelazeem201_Systolic-array-implementation-in-RTL-for-TPU, MiSTer-devel_ao486_MiSTer, pulp-platform_cheshire, WangXuan95_FPGA-ftdi245fifo, wuxx_Colorlight-FPGA-Projects)

.gitattributes

@@ -854,3 +854,72 @@ suisuisi_FPGAandCNN/DigitalRecognition/verilog/imp/incremental_db/compiled_parti
 suisuisi_FPGAandCNN/DigitalRecognition/verilog/imp/output_file.jic filter=lfs diff=lfs merge=lfs -text
 suisuisi_FPGAandCNN/DigitalRecognition/verilog/imp/output_files/cam_proj.pof filter=lfs diff=lfs merge=lfs -text
 suisuisi_FPGAandCNN/DnnKernelHLS/learning/mnist_dataset/mnist_dataset/train-images-idx3-ubyte/train-images.idx3-ubyte filter=lfs diff=lfs merge=lfs -text
+MiSTer-devel_ao486_MiSTer/releases/ao486_20170803.rbf filter=lfs diff=lfs merge=lfs -text
+MiSTer-devel_ao486_MiSTer/releases/ao486_20170805.rbf filter=lfs diff=lfs merge=lfs -text
+MiSTer-devel_ao486_MiSTer/releases/ao486_20170806.rbf filter=lfs diff=lfs merge=lfs -text
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+MiSTer-devel_ao486_MiSTer/releases/ao486_20170824.rbf filter=lfs diff=lfs merge=lfs -text
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+MiSTer-devel_ao486_MiSTer/releases/ao486_20180123.rbf filter=lfs diff=lfs merge=lfs -text
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+MiSTer-devel_ao486_MiSTer/sim/modelsim/cpu/lua_tests/FASM.EXE filter=lfs diff=lfs merge=lfs -text
+abdelazeem201_Systolic-array-implementation-in-RTL-for-TPU/Pics/Capture.PNG filter=lfs diff=lfs merge=lfs -text
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+abdelazeem201_Systolic-array-implementation-in-RTL-for-TPU/pnr/pna_output/tpu_top.VDD.pw_hl.pna filter=lfs diff=lfs merge=lfs -text
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+wuxx_Colorlight-FPGA-Projects/doc/E_ETRON_EM_EM638325BK.PDF filter=lfs diff=lfs merge=lfs -text
+wuxx_Colorlight-FPGA-Projects/tools/ujprog.bit2svf.arm filter=lfs diff=lfs merge=lfs -text
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MiSTer-devel_ao486_MiSTer/.gitignore

@@ -0,0 +1,40 @@
+db
+greybox_tmp
+incremental_db
+output_files
+simulation
+hc_output
+scaler
+hps_isw_handoff
+vip
+system
+*_sim
+.qsys_edit
+PLLJ_PLLSPE_INFO.txt
+*.bak
+*.orig
+*.rej
+*.qdf
+*.rpt
+*.smsg
+*.summary
+*.done
+*.jdi
+*.pin
+*.sof
+*.qws
+*.ppf
+*.ddb
+build_id.v
+c5_pin_model_dump.txt
+*.sopcinfo
+*.csv
+*.f
+*.cmp
+*.sip
+*.spd
+*.bsf
+*~
+*.xml
+*_netlist
+*.cdf

MiSTer-devel_ao486_MiSTer/LICENSE

@@ -0,0 +1,47 @@
+All files in the following directories:
+- rtl
+- ao486_tool
+- sim
+are licensed under the BSD license:
+
+--------------------------------------------------------------------------------
+
+Copyright (c) 2014, Aleksander Osman
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+  list of conditions and the following disclaimer.
+
+* Redistributions in binary form must reproduce the above copyright notice,
+  this list of conditions and the following disclaimer in the documentation
+  and/or other materials provided with the distribution.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+--------------------------------------------------------------------------------
+
+All files in the following directories:
+- bochs486
+- bochsDevs
+are taken from the Bochs Project and are licensed under the LGPL license.
+
+--------------------------------------------------------------------------------
+
+The binary file sd/fd_1_44m/fdboot.img is taken from the FreeDOS project.
+
+The binary file sd/bios/bochs_legacy is a compiled BIOS from the Bochs project.
+
+The binary file sd/vgabios/vgabios-lgpl is a compiled VGA BIOS from the vgabios
+project.

MiSTer-devel_ao486_MiSTer/README.md

@@ -0,0 +1,119 @@
+# ao486 port for MiSTer by Sorgelig.
+
+MiSTer port of the ao486 core originally written by Aleksander Osman, which has been greatly reworked with many new features and performance added.
+
+Original Core [repository](https://github.com/alfikpl/ao486)
+
+## Features:
+* 486SX33 performance (no-FPU).
+* 256MB RAM
+* SVGA with up to 1280x1024@256, 1024x768@64K, 640x480@16M resolutions
+* Sound Blaster 16 (DSP v4.05) and Sound Blaster Pro (DSP v3.02) with OPL3 and C/MS
+* High speed UART (3Mbps) internet connection
+* MIDI port (dumb and fake-smart modes)
+* External MIDI device support (MT32-pi and generic MIDI)
+* 4 HDDs with up to 137GB each
+* 2 CD-ROMs
+* Shared folder support
+
+## How to install
+
+* Copy ao486.rbf to the _Computer folder on your SD card.  This will be automatically copied there if you are using the update script.
+* Create games/ao486/ directory on SD card and copy [boot0.rom](https://github.com/MiSTer-devel/ao486_MiSTer/blob/master/releases/boot0.rom), [boot1.rom](https://github.com/MiSTer-devel/ao486_MiSTer/blob/master/releases/boot1.rom) there.
+* For CD images, the typical location is games/ao486/cd/ and you can either have the game folders, or CHD, IMG, ISO, BIN/CUE files in the root for mounting.  The imgset command can be used in DOS to mount/unmount images placed here by passing the exact path.
+* For floppy: copy desired floppy raw image with extension **img** to games/ao486/floppy/ directory.  The imgset command can be used in DOS to mount/unmount images placed here by passing the exact path.
+* For HDD: create an empty file of desired size with extension **vhd** in ao486 directory (or prepare .vhd file separately with any tool supporting .vhd or hard disk .img files and copy to games/ao486/ folder)
+* Boot ao486 and in OSD choose desired floppy, hdd, cd, and boot order.  A valid DOS or supported OS boot is required for the core to boot an OS.  Typical use cases: DOS Install disks on floppy with a clean VHD mounted for HDD. Pre-configured VHDs with OS and programs, Boot CDs, etc.
+* Save settings and press "Reset and apply HDD"
+* Optional shared folder can be used in conjuction with [MisterFS.exe](https://github.com/MiSTer-devel/ao486_MiSTer/blob/master/releases/drv/misterfs.exe) running as a TSR in your DOS image to exchange files between games/ao486/shared from inside DOS.
+
+HDD image is a raw image with MBR. It can be opened in Windows/Linux by many applications,
+so it's possible to prepare a HDD in windows/linux (in most cases you need to work with .img files, then just rename it to .vhd extension)
+
+### Core Speed and Options and Drivers
+The default core speed is set to 90Mhz with both L1 and L2 caches enabled.  This will give you the maximum speed for the release version of ao486.  Some games, especially older games, are sensitive to speed and cache so you can change the speed options and cache to fit the game.
+Optionally you can use the sysctl.exe program to automatically change these settings before launching your game.  This is especially useful for batch scripts where you want to change those options and then set it back after the game exits.
+
+Core options under Hardware:
+* CPU Clock: 15MHz, 30Mhz, 56MHz, 90Mhz (90MHz)
+* L1 Cache: On, Off (On)
+* L2 Cache: On, Off (On)
+* RAM Size: 256MB, 16MB (256MB)
+
+Optional programs and drivers:  https://github.com/MiSTer-devel/ao486_MiSTer/tree/master/releases/drv
+* MISTERFB.DRV/INF: Windows Video Driver
+* imgset.exe: Used for mounting fdd, cd, and ide drives. Run 'imgset' for options.
+* misterfs.exe:  You will need to copy this file to a VHD and run it using, "misterfs LETTER" where letter is the drive letter you want to mount the shared folder to.  Create a /games/ao486/shared folder and copy files named to the 8.3 filename standard (SFN - short filename). This allows for file copy from the shared folder and accessable from within dos on a mounted drive.  The tool is basic so it should be mainly used for file copy and not for running programs.
+* modem9x.inf: Used for Windows modem setup.
+* mpuctl.exe: tool for sending commands to the optional mt32-pi baremetal synth.  See reference below.
+* sbctl.exe: set Sound Blaster configs.  Supported: I5,I7,I10,H5,H1,T4,T6
+* sysctl.exe: Used for setting core options and cache referenced above from command line. Usase: SYSCTL SYS/MENU 90Mhz/56Mhz/15Mhz L1+/L1- L2+/L2-
+
+### Gravis UltraSound
+Default config: baseport=240, IRQ1=7, IRQ2=7, DMA1=7, DMA2=7. (SET ULTRASND=240,7,7,7,7)
+If you changed(sbctl.exe tool) SB IRQ to 7, GUS IRQ1&2 changed to 5.
+Supported GUS 1MB DRAM(required SDRAM module). Any CPU frequency, except 15MHz(too slow).
+
+### Sound Blaster
+Default config: A220 I5 D1 H5 T6
+Supported alternative configs with IRQ 7 or 10 and/or no-HDMA (16bit DMA through 8bit DMA).
+Standard SB16 config (diagnose) can be used to set alternative settings, or included sbctl util. Windows driver manages alternative settings by itself when manually configured.
+
+Current implementation supports SoundBlaster Pro specific commands (not available in SB16 originally) as well. Compatible config for SBPro is "A220 I5 D1 T4" in case if some game will require it.
+
+ASP/CSP is not implemented, but some specific commands with dummy replies are added to let Windows driver work.
+
+Simple volume (only master volume) is implemented in mixer so windows volume can be used in additional to standard MiSTer volume control.
+
+### C/MS Audio
+C/MS (dual SAA1099) can be enabled in OSD. When enabled it prevents OPL2/3 access on ports 220-223. OPL2/3 still can be accessed on ports 388-38B (AdLib).
+
+### OPL2/3 (Adlib)
+OPL2/3 can be accessed as a part of Sound Blaster board at ports 220-223 (if C/MS is not enabled) and 228-229(OPL2 only). However it's recommended to use AdLib ports 388-38B instead.
+
+### MIDI settings:
+* address: 330h
+* IRQ: 9
+
+### MT32-pi support:
+[MT32-pi](https://github.com/dwhinham/mt32-pi) connection is supported through USER I/O port. MT32-pi is automatically detected.
+Supported straight and crossed RX<->TX cables.
+
+MT32-pi config and settings are [here](https://github.com/dwhinham/mt32-pi/wiki/MiSTer-FPGA-user-port-connection).
+
+MT32-pi interface board is on [Hardware repository](https://github.com/MiSTer-devel/Hardware_MiSTer)
+
+LCD and buttons are for convenience but not required. Basically only USER I/O connector is required, so it can be assembled without interface board.
+
+### Note:
+* Press **WIN+F12** to access **OSD on ao486 core**. F12 alone acts as generic F12 PC key.
+
+### CD-ROM
+Currently only data portion of CD is supported. Best image format is ISO, but BIN/CUE and CHD format discs still can be mounted. You just need to mount bin file or if it's multi-file image, then usually first track is data which you need to mount.
+
+IDE 1-0 has special function - it's a placeholder for CD. So you can hot-swap CD images in this drive. Regardless special function this drive also supports HDD images. Once HDD image is loaded upon reboot this drive loses CD placeholder feature.
+
+### Hard Disk and CD-ROM in Windows
+Core supports up to 4 HDD images up to 137GB each. Up to 2 CD-ROMs are supported.
+
+Currently due to unknown source of issue Windows works with IDE devices through BIOS. Most likely some BIOS function doesn't supply correct info for Windows drivers.
+It doesn't prevent windows from working but you need to keep in mind some specifics:
+* Hard disks mounted on Primary IDE (0-0/0-1) need no attentions. They simply work.
+* Driver for Secondary IDE (1-0/1-1) have yellow mark. It's recommended to delete this device from device list - it's not used anyway but will be installed every time you start automatic HW detection procedure.
+* CD-ROM needs oakcdrom.sys and mscdex.exe added to config.sys and autoexec.bat respectively (you may find them on bootable Window98 CD). Windows will use it to access CD-ROM.
+* CD-ROM autostart won't be automatically triggered (because work through BIOS). After replacing image file in CD-ROM you need to refresh the folder with drives (F5) and icon of CD will be changed if provided by image. Autostart will be triggered when you click on CD icon.
+
+### Building core
+* Quartus 17.0 doesn't install properly on newer Linux distros, so use Docker instead. Install Docker for your dist https://docs.docker.com/engine/install/
+* Download Docker image containing Quartus Lite Edition 17.0 from https://github.com/raetro/sdk-docker-fpga:
+
+        docker pull ghcr.io/raetro/quartus:mister
+
+* Build project
+    * After cloning this repo and changing to the directory:
+
+            docker run -it --rm -v $(pwd):/build raetro/quartus:mister quartus_sh --flow compile ao486.qpf
+
+* Access GUI
+
+        docker run --rm -ti --net=host --ipc=host -e DISPLAY=$DISPLAY -v /tmp/.X11-unix:/tmp/.X11-unix --env="QT_X11_NO_MITSHM=1" -v $(pwd):/build raetro/quartus:mister quartus

MiSTer-devel_ao486_MiSTer/ao486.qpf

@@ -0,0 +1,2 @@
+QUARTUS_VERSION = "17.0"
+PROJECT_REVISION = "ao486"

MiSTer-devel_ao486_MiSTer/ao486.qsf

@@ -0,0 +1,70 @@
+# --------------------------------------------------------------------------
+#
+# MiSTer project
+#
+# WARNING WARNING WARNING:
+# Do not add files to project in Quartus IDE! It will mess this file!
+# Add the files manually to files.qip file.
+#
+# --------------------------------------------------------------------------
+
+set_global_assignment -name TOP_LEVEL_ENTITY sys_top
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+
+set_global_assignment -name LAST_QUARTUS_VERSION "17.0.2 Standard Edition"
+
+set_global_assignment -name GENERATE_RBF_FILE ON
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
+set_global_assignment -name SAVE_DISK_SPACE OFF
+set_global_assignment -name SMART_RECOMPILE ON
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP "-40"
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 100
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS OFF
+set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING OFF
+set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS
+set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
+set_global_assignment -name OPTIMIZATION_MODE "HIGH PERFORMANCE EFFORT"
+set_global_assignment -name ALLOW_POWER_UP_DONT_CARE ON
+set_global_assignment -name QII_AUTO_PACKED_REGISTERS "SPARSE AUTO"
+set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
+set_global_assignment -name OPTIMIZATION_TECHNIQUE SPEED
+set_global_assignment -name MUX_RESTRUCTURE ON
+set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS ON
+set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON
+set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON
+set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION ON
+set_global_assignment -name PRE_MAPPING_RESYNTHESIS ON
+set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS ON
+set_global_assignment -name ECO_OPTIMIZE_TIMING ON
+set_global_assignment -name PERIPHERY_TO_CORE_PLACEMENT_AND_ROUTING_OPTIMIZATION ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON
+set_global_assignment -name ALM_REGISTER_PACKING_EFFORT LOW
+set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS OFF
+set_global_assignment -name ROUTER_REGISTER_DUPLICATION ON
+set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION ALWAYS
+set_global_assignment -name SEED 1
+
+set_global_assignment -name VERILOG_MACRO "MISTER_FB=1"
+
+#enable it only if 8bit indexed mode is used in core
+set_global_assignment -name VERILOG_MACRO "MISTER_FB_PALETTE=1"
+
+#set_global_assignment -name VERILOG_MACRO "MISTER_DUAL_SDRAM=1"
+
+#do not enable DEBUG_NOHDMI in release!
+#set_global_assignment -name VERILOG_MACRO "MISTER_DEBUG_NOHDMI=1"
+
+source sys/sys.tcl
+source sys/sys_analog.tcl
+source files.qip
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

MiSTer-devel_ao486_MiSTer/ao486.sdc

@@ -0,0 +1,26 @@
+derive_pll_clocks
+derive_clock_uncertainty
+
+set clk_sys   {*|pll|pll_inst|altera_pll_i|*[0].*|divclk}
+set clk_uart1 {*|pll|pll_inst|altera_pll_i|*[1].*|divclk}
+set clk_mpu   {*|pll|pll_inst|altera_pll_i|*[2].*|divclk}
+set clk_audio {pll_audio|pll_audio_inst|altera_pll_i|*[0].*|divclk}
+set clk_vga   {*|pll|pll_inst|altera_pll_i|*[4].*|divclk}
+set clk_uart2 {*|pll|pll_inst|altera_pll_i|*[5].*|divclk}
+
+set_false_path -from [get_clocks $clk_sys]   -to [get_clocks $clk_vga]
+set_false_path -from [get_clocks $clk_vga]   -to [get_clocks $clk_sys]
+
+set_false_path -from [get_clocks $clk_audio] -to [get_clocks $clk_sys]
+set_false_path -from [get_clocks $clk_sys]   -to [get_clocks $clk_audio]
+
+set_false_path -from [get_clocks $clk_sys]   -to [get_clocks $clk_uart1]
+set_false_path -from [get_clocks $clk_uart1] -to [get_clocks $clk_sys]
+set_false_path -from [get_clocks $clk_sys]   -to [get_clocks $clk_uart2]
+set_false_path -from [get_clocks $clk_uart2] -to [get_clocks $clk_sys]
+
+set_false_path -from [get_clocks $clk_sys]   -to [get_clocks $clk_mpu]
+set_false_path -from [get_clocks $clk_mpu]   -to [get_clocks $clk_sys]
+
+set_multicycle_path -from {emu:emu|reset*} -setup 2
+set_multicycle_path -from {emu:emu|reset*} -hold 1

MiSTer-devel_ao486_MiSTer/ao486.srf

@@ -0,0 +1,25 @@
+{ "" "" "" "System.pll_0: Able to implement PLL - Actual settings differ from Requested settings" {  } {  } 0 12251 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "Port \"extclk\" on the entity instantiation of \"cyclonev_pll\" is connected to a signal of width 1. The formal width of the signal in the module is 2.  The extra bits will be left dangling without any fan-out logic." {  } {  } 0 12030 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "RST port on the PLL is not properly connected on instance emu:emu\|system:u0\|system_pll_0:pll_0\|altera_pll:altera_pll_i\|general\[0\].gpll. The reset port on the PLL should be connected. If the PLL loses lock for any reason, you might need to manually reset the PLL in order to re-establish lock to the reference clock." {  } {  } 0 0 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "RST port on the PLL is not properly connected on instance emu:emu\|system:u0\|system_pll_0:pll_0\|altera_pll:altera_pll_i\|general\[1\].gpll. The reset port on the PLL should be connected. If the PLL loses lock for any reason, you might need to manually reset the PLL in order to re-establish lock to the reference clock." {  } {  } 0 0 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "RST port on the PLL is not properly connected on instance emu:emu\|system:u0\|system_pll_0:pll_0\|altera_pll:altera_pll_i\|general\[2\].gpll. The reset port on the PLL should be connected. If the PLL loses lock for any reason, you might need to manually reset the PLL in order to re-establish lock to the reference clock." {  } {  } 0 0 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "LOCKED port on the PLL is not properly connected on instance \"emu:emu\|system:u0\|system_pll_0:pll_0\|altera_pll:altera_pll_i\|general\[0\].gpll\". The LOCKED port on the PLL should be connected when the FBOUTCLK port is connected. Although it is unnecessary to connect the LOCKED signal, any logic driven off of an output clock of the PLL will not know when the PLL is locked and ready." {  } {  } 0 21300 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "RST port on the PLL is not properly connected on instance pll_audio:pll_audio\|pll_audio_0002:pll_audio_inst\|altera_pll:altera_pll_i\|general\[0\].gpll. The reset port on the PLL should be connected. If the PLL loses lock for any reason, you might need to manually reset the PLL in order to re-establish lock to the reference clock." {  } {  } 0 0 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "LOCKED port on the PLL is not properly connected on instance \"pll_audio:pll_audio\|pll_audio_0002:pll_audio_inst\|altera_pll:altera_pll_i\|general\[0\].gpll\". The LOCKED port on the PLL should be connected when the FBOUTCLK port is connected. Although it is unnecessary to connect the LOCKED signal, any logic driven off of an output clock of the PLL will not know when the PLL is locked and ready." {  } {  } 0 21300 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "RST port on the PLL is not properly connected on instance emu:emu\|pll2:pll\|pll2_0002:pll_inst\|altera_pll:altera_pll_i\|general\[0\].gpll. The reset port on the PLL should be connected. If the PLL loses lock for any reason, you might need to manually reset the PLL in order to re-establish lock to the reference clock." {  } {  } 0 0 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "LOCKED port on the PLL is not properly connected on instance \"emu:emu\|pll2:pll\|pll2_0002:pll_inst\|altera_pll:altera_pll_i\|general\[0\].gpll\". The LOCKED port on the PLL should be connected when the FBOUTCLK port is connected. Although it is unnecessary to connect the LOCKED signal, any logic driven off of an output clock of the PLL will not know when the PLL is locked and ready." {  } {  } 0 21300 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "Found RAM instances implemented as ROM because the write logic is disabled. One instance is listed below as an example." {  } {  } 0 18550 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "RST port on the PLL is not properly connected on instance emu:emu\|pll2:pll\|pll2_0002:pll_inst\|altera_pll:altera_pll_i\|general\[1\].gpll. The reset port on the PLL should be connected. If the PLL loses lock for any reason, you might need to manually reset the PLL in order to re-establish lock to the reference clock." {  } {  } 0 0 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "RST port on the PLL is not properly connected on instance emu:emu\|pll:pll\|pll_0002:pll_inst\|altera_pll:altera_pll_i\|general\[0\].gpll. The reset port on the PLL should be connected. If the PLL loses lock for any reason, you might need to manually reset the PLL in order to re-establish lock to the reference clock." {  } {  } 0 0 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "LOCKED port on the PLL is not properly connected on instance \"emu:emu\|pll:pll\|pll_0002:pll_inst\|altera_pll:altera_pll_i\|general\[0\].gpll\". The LOCKED port on the PLL should be connected when the FBOUTCLK port is connected. Although it is unnecessary to connect the LOCKED signal, any logic driven off of an output clock of the PLL will not know when the PLL is locked and ready." {  } {  } 0 21300 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "RST port on the PLL is not properly connected on instance emu:emu\|pll:pll\|pll_0002:pll_inst\|altera_pll:altera_pll_i\|general\[1\].gpll. The reset port on the PLL should be connected. If the PLL loses lock for any reason, you might need to manually reset the PLL in order to re-establish lock to the reference clock." {  } {  } 0 0 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "Variable or input pin \"outclock\" is defined but never used." {  } {  } 0 287013 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "*" {  } {  } 0 276027 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "*" {  } {  } 0 276020 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "*" {  } {  } 0 20013 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "altera_pll.v" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "altera_cyclonev_pll.v" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "altera_pll_reconfig_core.v" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "altera_merlin_width_adapter.sv" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "altera_merlin_burst_adapter_13_1.sv" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}
+{ "" "" "" "altera_merlin_address_alignment.sv" {  } {  } 0 9999 "" 0 0 "Design Software" 0 -1 0 ""}

MiSTer-devel_ao486_MiSTer/ao486.sv

@@ -0,0 +1,1048 @@
+//============================================================================
+//  ao486
+//
+//  Port to MiSTer.
+//  Copyright (C) 2017-2020 Alexey Melnikov
+//
+//  This program is free software; you can redistribute it and/or modify it
+//  under the terms of the GNU General Public License as published by the Free
+//  Software Foundation; either version 2 of the License, or (at your option)
+//  any later version.
+//
+//  This program is distributed in the hope that it will be useful, but WITHOUT
+//  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+//  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+//  more details.
+//
+//  You should have received a copy of the GNU General Public License along
+//  with this program; if not, write to the Free Software Foundation, Inc.,
+//  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+//============================================================================
+
+module emu
+(
+	`include "sys/emu_ports.vh"
+);
+
+//`define DEBUG
+
+assign ADC_BUS  = 'Z;
+assign {SDRAM_A, SDRAM_BA, SDRAM_DQ, SDRAM_CLK, SDRAM_CKE, SDRAM_DQML, SDRAM_DQMH, SDRAM_nWE, SDRAM_nCAS, SDRAM_nRAS, SDRAM_nCS} = 'Z;
+assign {SD_SCK, SD_MOSI, SD_CS} = 'Z;
+
+assign LED_DISK[1] = 0;
+assign LED_POWER   = 0;
+assign BUTTONS     = {~ps2_reset_n, 1'b0};
+assign HDMI_FREEZE = 0;
+assign HDMI_BLACKOUT = 0;
+assign HDMI_BOB_DEINT = 0;
+assign VGA_DISABLE = 0;
+
+led hdd_led(clk_sys, |mgmt_req[5:0], LED_DISK[0]);
+led fdd_led(clk_sys, |mgmt_req[7:6], LED_USER);
+
+// Status Bit Map:
+// 0         1         2         3          4         5         6
+// 01234567890123456789012345678901 23456789012345678901234567890123
+// 0123456789ABCDEFGHIJKLMNOPQRSTUV 0123456789ABCDEFGHIJKLMNOPQRSTUV
+// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXXXXXXXXXX
+
+`include "build_id.v"
+localparam CONF_STR =
+{
+	"AO486;UART115200:4000000(Turbo 115200),MIDI;",
+	"S0,IMGIMAVFD,Floppy A:;",
+	"S1,IMGIMAVFD,Floppy B:;",
+	"O12,Write Protect,None,A:,B:,A: & B:;",
+	"-;",
+	"S2,VHD,IDE 0-0;",
+	"S3,VHD,IDE 0-1;",
+	"-;",
+	"S4,VHDISOCUECHD,IDE 1-0;",
+	"S5,VHDISOCUECHD,IDE 1-1;",
+	"-;",
+	"oJM,CPU Preset,User Defined,~PC XT-7MHz,~PC AT-8MHz,~PC AT-10MHz,~PC AT-20MHz,~PS/2-20MHz,~386SX-25MHz,~386DX-33Mhz,~386DX-40Mhz,~486SX-33Mhz,~486DX-33Mhz,MAX (unstable);",
+	"-;",
+	"P1,Audio & Video;",
+	"P1-;",
+	"P1OMN,Aspect ratio,Original,Full Screen,[ARC1],[ARC2];",
+	"P1O4,VSync,60Hz,Variable;",
+	"P1O8,16/24bit mode,BGR,RGB;",
+	"P1O9,16bit format,1555,565;",
+	"P1OE,Low-Res,Native,4x;",
+	"P1oDE,Scale,Normal,V-Integer,Narrower HV-Integer,Wider HV-Integer;",
+	"P1oN,Border,No,Yes;",
+	"P1-;",
+	"P1O3,FM mode,OPL2,OPL3;",
+	"P1OH,C/MS,Disable,Enable;",
+	"P1OIJ,PC Speaker Volume,1,2,3,4;",
+	"P1OKL,Audio Boost,No,2x,4x;",
+	"P1oBC,Stereo Mix,none,25%,50%,100%;",
+	"P1oO,SB Swap L/R,Off,On;",
+	"P1OP,MT32 Volume Ctl,MIDI,Line-In;",
+
+	"P2,Hardware;",
+	"P2o01,Boot 1st,Floppy/Hard Disk,Floppy,Hard Disk,CD-ROM;",
+	"P2o23,Boot 2nd,NONE,Floppy,Hard Disk,CD-ROM;",
+	"P2o45,Boot 3rd,NONE,Floppy,Hard Disk,CD-ROM;",
+	"P2-;",
+	"P2o6,IDE 1-0 CD Hot-Swap,Yes,No;",
+	"P2o7,IDE 1-1 CD Hot-Swap,No,Yes;",
+	"P2-;",
+	"P2OB,RAM Size,256MB,16MB;",
+	"P2oP,D0000h-EFFFFh RAM,Off,On;",
+`ifndef DEBUG
+	"H5P2-;",
+	"H5D2D1P2O56,CPU Clock,90MHz,15MHz,30MHz,56MHz;",
+	"H5h0P2O7,Overclock,Off,100Mhz;",
+	"H5D2P2OF,L1 Cache,On,Off;",
+	"H5D2P2OG,L2 Cache,On,Off;",
+`endif
+	"P2-;",
+	"P2OA,USER I/O,MIDI,COM2;",
+	"P2-;",
+	"P2OCD,Joystick Type,2 Buttons,4 Buttons,Gravis Pro,None;",
+	"P2oFG,Joystick Mode,2 Joysticks,2 Sticks,2 Wheels,4-axes Wheel;",
+	"P2oQR,Joystick Axes,Timed,Count 8+141,Count 0+256,Count 6+256;",
+	"P2oH,Joystick 1,Enabled,Disabled;",
+	"P2oI,Joystick 2,Enabled,Disabled;",
+
+	"h3P3,MT32-pi;",
+	"h3P3-;",
+	"h3P3OO,Use MT32-pi,Yes,No;",
+	"h3P3o9A,Show Info,No,Yes,LCD-On(non-FB),LCD-Auto(non-FB);",
+	"h3P3-;",
+	"h3P3-,Default Config:;",
+	"h3P3OQ,Synth,Munt,FluidSynth;",
+	"h3P3ORS,Munt ROM,MT-32 v1,MT-32 v2,CM-32L;",
+	"h3P3OTV,SoundFont,0,1,2,3,4,5,6,7;",
+	"h3P3-;",
+	"h3P3r8,Reset Hanging Notes;",
+	"-;",
+	"R0,Reset and apply HDD;",
+	"J,Button 1,Button 2,Button 3,Button 4,Start,Select,R1,L1,R2,L2;",
+	"jn,A,B,X,Y,Start,Select,R,L;",
+	"I,",
+	"MT32-pi: SoundFont #0,",
+	"MT32-pi: SoundFont #1,",
+	"MT32-pi: SoundFont #2,",
+	"MT32-pi: SoundFont #3,",
+	"MT32-pi: SoundFont #4,",
+	"MT32-pi: SoundFont #5,",
+	"MT32-pi: SoundFont #6,",
+	"MT32-pi: SoundFont #7,",
+	"MT32-pi: MT-32 v1,",
+	"MT32-pi: MT-32 v2,",
+	"MT32-pi: CM-32L,",
+	"MT32-pi: Unknown mode;",
+	"V,v",`BUILD_DATE
+};
+
+////////////////////////////////////////////////////////////////////////
+
+wire        ps2_kbd_clk_out;
+wire        ps2_kbd_data_out;
+wire        ps2_kbd_clk_in;
+wire        ps2_kbd_data_in;
+wire [10:0] ps2_key;
+
+wire        ps2_mouse_clk_out;
+wire        ps2_mouse_data_out;
+wire        ps2_mouse_clk_in;
+wire        ps2_mouse_data_in;
+
+wire  [1:0] buttons;
+wire [63:0] status;
+
+wire [13:0] joystick_0;
+wire [13:0] joystick_1;
+wire [15:0] joystick_l_analog_0;
+wire [15:0] joystick_l_analog_1;
+wire [15:0] joystick_r_analog_0;
+wire [15:0] joystick_r_analog_1;
+
+wire [21:0] gamma_bus;
+wire  [7:0] uart1_mode;
+wire [31:0] uart1_speed;
+
+hps_io #(.CONF_STR(CONF_STR), .CONF_STR_BRAM(0), .PS2DIV(2000), .PS2WE(1), .WIDE(1)) hps_io
+(
+	.clk_sys(clk_sys),
+	.HPS_BUS(HPS_BUS),
+
+	.ps2_key(ps2_key),
+	.ps2_kbd_clk_out(ps2_kbd_clk_out),
+	.ps2_kbd_data_out(ps2_kbd_data_out),
+	.ps2_kbd_clk_in(ps2_kbd_clk_in),
+	.ps2_kbd_data_in(ps2_kbd_data_in),
+
+	.ps2_mouse_clk_out(ps2_mouse_clk_out),
+	.ps2_mouse_data_out(ps2_mouse_data_out),
+	.ps2_mouse_clk_in(ps2_mouse_clk_in),
+	.ps2_mouse_data_in(ps2_mouse_data_in),
+
+	.buttons(buttons),
+	.status(status),
+	.status_menumask({|status[54:51],mt32_newmode,mt32_available,syscfg[7],status[7],dbg_menu}),
+	.info_req(mt32_info_req),
+	.info(mt32_info_disp),
+
+	.new_vmode(status[4]),
+	.gamma_bus(gamma_bus),
+
+	.uart_mode(uart1_mode),
+	.uart_speed(uart1_speed),
+
+	.joystick_0(joystick_0),
+	.joystick_1(joystick_1),
+	.joystick_l_analog_0(joystick_l_analog_0),
+	.joystick_l_analog_1(joystick_l_analog_1),
+	.joystick_r_analog_0(joystick_r_analog_0),
+	.joystick_r_analog_1(joystick_r_analog_1),
+
+	.EXT_BUS(EXT_BUS)
+);
+
+wire [15:0] mgmt_din;
+wire [15:0] mgmt_dout;
+wire [15:0] mgmt_addr;
+wire        mgmt_rd;
+wire        mgmt_wr;
+wire  [7:0] mgmt_req;
+
+wire [35:0] EXT_BUS;
+hps_ext hps_ext
+(
+	.clk_sys(clk_sys),
+	.EXT_BUS(EXT_BUS),
+
+	.ext_din(mgmt_din),
+	.ext_dout(mgmt_dout),
+	.ext_addr(mgmt_addr),
+	.ext_rd(mgmt_rd),
+	.ext_wr(mgmt_wr),
+
+	.cdda_req(cdda_req),
+	.cdda_wr(cdda_wr),
+	.cdda_dout(cdda_dout),
+
+	.ext_req(mgmt_req),
+	.ext_hotswap(status[39:38])
+);
+
+/////////////////////////////  PLL  ////////////////////////////////////
+
+wire clk_sys, clk_uart1, clk_uart2, clk_mpu, clk_vga;
+reg [27:0] cur_rate;
+
+`ifdef DEBUG
+
+pll2 pll
+(
+	.refclk(CLK_50M),
+	.outclk_0(clk_vga),
+	.outclk_1(clk_uart1),
+	.outclk_2(clk_mpu),
+	.outclk_3(),
+	.outclk_4(clk_sys),
+	.outclk_5(clk_uart2)
+);
+
+always @(posedge clk_sys) cur_rate <= 30000000;
+
+`else
+
+
+wire pll_locked;
+pll pll
+(
+	.refclk(CLK_50M),
+	.rst(0),
+	.outclk_0(clk_sys),
+	.outclk_1(clk_uart1),
+	.outclk_2(clk_mpu),
+	.outclk_3(), // 14.285714 instead of 14.318181 which is within tolerance of typical resonator
+	.outclk_4(clk_vga),
+	.outclk_5(clk_uart2),
+	.locked(pll_locked),
+	.reconfig_to_pll(reconfig_to_pll),
+	.reconfig_from_pll(reconfig_from_pll)
+);
+
+wire [63:0] reconfig_to_pll;
+wire [63:0] reconfig_from_pll;
+wire        cfg_waitrequest;
+reg         cfg_write;
+reg   [5:0] cfg_address;
+reg  [31:0] cfg_data;
+
+pll_cfg pll_cfg
+(
+	.mgmt_clk(CLK_50M),
+	.mgmt_reset(0),
+	.mgmt_waitrequest(cfg_waitrequest),
+	.mgmt_read(0),
+	.mgmt_readdata(),
+	.mgmt_write(cfg_write),
+	.mgmt_address(cfg_address),
+	.mgmt_writedata(cfg_data),
+	.reconfig_to_pll(reconfig_to_pll),
+	.reconfig_from_pll(reconfig_from_pll)
+);
+
+reg [2:0] clk_req;
+reg l1, l2;
+always @(posedge clk_sys) begin
+	case(status[54:51])
+		'd1: begin clk_req <= 'd3; l1 <= 1'b1; l2 <= 1'b1; end  // ao486 XT 7
+		'd2: begin clk_req <= 'd1; l1 <= 1'b1; l2 <= 1'b0; end  // ao486 AT 8
+		'd3: begin clk_req <= 'd2; l1 <= 1'b0; l2 <= 1'b1; end  // ao486 AT 10
+		'd4: begin clk_req <= 'd2; l1 <= 1'b1; l2 <= 1'b0; end  // ao486 AT 20
+		'd5: begin clk_req <= 'd1; l1 <= 1'b0; l2 <= 1'b0; end  // ao486 PS/2 20
+		'd6: begin clk_req <= 'd3; l1 <= 1'b1; l2 <= 1'b0; end  // ao486 3SX 25
+		'd7: begin clk_req <= 'd2; l1 <= 1'b0; l2 <= 1'b0; end  // ao486 3DX 33
+		'd8: begin clk_req <= 'd0; l1 <= 1'b1; l2 <= 1'b0; end  // ao486 3DX 40
+		'd9: begin clk_req <= 'd3; l1 <= 1'b0; l2 <= 1'b0; end  // ao486 4SX 33
+		'd10: begin clk_req <= 'd0; l1 <= 1'b0; l2 <= 1'b0; end // ao486 MAX (stable)
+		'd11: begin clk_req <= 'd4; l1 <= 1'b0; l2 <= 1'b0; end // ao486 MAX+ (unstable)
+		default: begin
+		// CPU & Cache config
+		clk_req <= {status[7], syscfg[7] ? syscfg[1:0] : status[6:5]};
+		l1 <= syscfg[7] ? syscfg[4] : status[15];
+		l2 <= syscfg[7] ? syscfg[5] : status[16];
+		end
+	endcase
+end
+
+reg [2:0] speed;
+always @(posedge CLK_50M) begin
+	reg [2:0] sp1, sp2;
+
+	sp1 <= clk_req;
+	sp2 <= sp1;
+
+	if(sp2 == sp1) speed <= sp2;
+end
+
+reg uspeed_sys;
+always @(posedge clk_sys) uspeed_sys <= (uart1_speed <= 115200);
+
+reg uspeed;
+always @(posedge CLK_50M) begin
+	reg sp1, sp2;
+
+	sp1 <= uspeed_sys;
+	sp2 <= sp1;
+
+	if(sp2 == sp1) uspeed <= sp2;
+end
+
+(* romstyle = "logic" *) wire [27:0] clk_rate[8]  = '{90000000, 15000000, 30000000, 56250000, 100000000, 100000000, 100000000, 100000000 };
+(* romstyle = "logic" *) wire [17:0] speed_div[8] = '{  'h0505,   'h1e1e,   'h0f0f,   'h0808,   'h20504,   'h20504,   'h20504,   'h20504 };
+
+always @(posedge CLK_50M) begin
+	reg [2:0] old_speed = 0;
+	reg [2:0] state = 0;
+	reg       old_uspeed = 0;
+	reg       old_rst = 0;
+
+	if(!cfg_waitrequest) begin
+
+		cfg_write <= 0;
+
+		if(pll_locked) begin
+			if(state) state<=state+1'd1;
+			case(state)
+				0: begin
+						old_rst <= reset;
+						old_speed <= speed;
+						old_uspeed <= uspeed;
+						if((old_speed != speed) || (old_uspeed != uspeed) || (old_rst & ~reset)) state <= 1;
+					end
+				1: begin
+						cfg_address <= 0;
+						cfg_data <= 0;
+						cfg_write <= 1;
+					end
+				3: begin
+						cfg_address <= 5;
+						cfg_data <= speed_div[speed];
+						cfg_write <= 1;
+					end
+				5: begin
+						cfg_address <= 5;
+						cfg_data <= uspeed ? 32'h4F4F4 : 32'h40909;
+						cfg_write <= 1;
+					end
+				7: begin
+						cfg_address <= 2;
+						cfg_data <= 0;
+						cfg_write <= 1;
+					end
+			endcase
+		end
+	end
+end
+
+always @(posedge clk_sys) cur_rate <= clk_rate[clk_req];
+
+`endif
+
+////////////////////////////  UART  ////////////////////////////////////
+
+/// UART1
+
+wire uart1_cts, uart1_dcd, uart1_dsr, uart1_rts, uart1_dtr;
+wire uart1_tx, uart1_rx;
+wire mpu_tx, mpu_rx;
+
+wire hps_mpu = (uart1_mode >= 3);
+
+assign UART_RTS  = ~hps_mpu & uart1_rts;
+assign UART_DTR  = ~hps_mpu & uart1_dtr;
+assign uart1_cts = ~hps_mpu & UART_CTS;
+assign uart1_dcd = ~hps_mpu & UART_DSR;
+assign uart1_dsr = ~hps_mpu & UART_DSR;
+assign uart1_rx  = ~hps_mpu & UART_RXD;
+assign mpu_rx    = ~hps_mpu ? midi_rx : UART_RXD;
+assign UART_TXD  = ~hps_mpu ? uart1_tx : (mpu_tx & ~mt32_use);
+
+/// UART2
+
+wire user_io_mode = status[10];
+
+assign USER_OUT = user_io_mode ? {1'b1, 1'b1, uart2_dtr, 1'b1, uart2_rts, uart2_tx, 1'b1} : mt32_out;
+
+//
+// Pin | USB Name |   |Signal
+// ----+----------+---+-------------
+// 0   | D+       | I |RX
+// 1   | D-       | O |TX
+// 2   | TX-      | O |RTS
+// 3   | GND_d    | I |CTS
+// 4   | RX+      | O |DTR
+// 5   | RX-      | I |DSR
+// 6   | TX+      | I |DCD
+//
+
+wire uart2_tx, uart2_rts, uart2_dtr;
+
+wire uart2_rx  = ~user_io_mode | USER_IN[0];
+wire uart2_cts = ~user_io_mode | USER_IN[3];
+wire uart2_dsr = ~user_io_mode | USER_IN[5];
+wire uart2_dcd = ~user_io_mode | USER_IN[6];
+
+////////////////////////////  VIDEO  ///////////////////////////////////
+
+assign VGA_F1 = 0;
+assign VGA_SL = 0;
+assign VGA_SCALER = 1;
+assign CLK_VIDEO = clk_vga;
+assign CE_PIXEL = vga_ce;
+
+wire [7:0] r,g,b;
+wire       HSync,VSync;
+wire       ce_pix;
+
+video_cleaner video_cleaner
+(
+	.clk_vid(CLK_VIDEO),
+	.ce_pix(vga_ce),
+
+	.R(r),
+	.G(g),
+	.B(b),
+
+	.HSync(HSync),
+	.VSync(VSync),
+	.DE_in(vga_de),
+
+	.VGA_R(R),
+	.VGA_G(G),
+	.VGA_B(B),
+	.VGA_VS(vs),
+	.VGA_HS(hs),
+	.DE_out(de1)
+);
+
+wire hs,vs,de1;
+wire [7:0] R,G,B;
+
+gamma_fast gamma
+(
+	.clk_vid(CLK_VIDEO),
+	.ce_pix(CE_PIXEL),
+
+	.gamma_bus(gamma_bus),
+
+	.HSync(hs),
+	.VSync(vs),
+	.DE(de1),
+	.RGB_in(mt32_lcd ? {{2{mt32_lcd_pix}},R[7:2], {2{mt32_lcd_pix}},G[7:2], {2{mt32_lcd_pix}},B[7:2]} : {R,G,B}),
+
+	.HSync_out(VGA_HS),
+	.VSync_out(VGA_VS),
+	.DE_out(VGA_DE),
+	.RGB_out({VGA_R,VGA_G,VGA_B})
+);
+
+wire  [7:0] vga_pal_a;
+wire [17:0] vga_pal_d;
+wire        vga_pal_we;
+
+wire [19:0] vga_start_addr;
+wire  [8:0] vga_width;
+wire  [8:0] vga_stride;
+wire [10:0] vga_height;
+wire  [3:0] vga_flags;
+wire        vga_off;
+wire        vga_ce;
+wire        vga_de;
+
+reg         fb_en;
+reg  [31:0] fb_base;
+reg  [11:0] fb_height;
+reg  [11:0] fb_width;
+reg  [13:0] fb_stride;
+reg   [4:0] fb_fmt;
+reg         fb_off;
+
+always @(posedge clk_sys) begin
+	fb_en       <= ~vga_flags[2] && |vga_flags[1:0]; // framebuffer enabled for high resolution and 16-bit/24-bit/32-bit color modes
+	fb_base     <= {4'h3, 6'b111110, vga_start_addr, 2'b00};
+	fb_width    <= (vga_flags[1:0] == 3) ? 12'd640 /*({vga_width, 3'b000}/3)*/ : vga_flags[2] ? {vga_width, 2'b00} : {vga_width, 3'b000};
+	fb_stride   <= {vga_stride, 3'b000};
+	fb_height   <= ~status[14] && vga_flags[3] ? vga_height[10:1] : vga_height;
+	fb_fmt[2:0] <= (vga_flags[1:0] == 3) ? 3'b101 : (vga_flags[1:0] == 2) ? 3'b100 : 3'b011; // 011=8bpp 100=16bpp 101=24bpp 110=32bpp
+	fb_fmt[4:3] <= {~status[8],~status[9]};
+	fb_off      <= vga_off;
+end
+
+assign FB_PAL_CLK     = clk_sys;
+assign FB_PAL_ADDR    = vga_pal_a;
+assign FB_PAL_DOUT    = {vga_pal_d[17:12], vga_pal_d[17:16], vga_pal_d[11:6], vga_pal_d[11:10], vga_pal_d[5:0], vga_pal_d[5:4]};
+assign FB_PAL_WR      = vga_pal_we;
+assign FB_EN          = fb_en;
+assign FB_BASE        = fb_base;
+assign FB_FORMAT      = fb_fmt;
+assign FB_WIDTH       = fb_width;
+assign FB_HEIGHT      = fb_height;
+assign FB_STRIDE      = fb_stride;
+assign FB_FORCE_BLANK = fb_off;
+
+reg f60;
+always @(posedge clk_sys) f60 <= fb_en || (fb_width > 760);
+
+reg  [2:0] ar,SCALE;
+reg [11:0] arx_i,ary_i;
+always @(posedge CLK_VIDEO) begin
+	ar    <= status[23:22];
+	SCALE <= status[46:45];
+	arx_i <= (!ar) ? 8'd4 : (ar - 1'd1);
+	ary_i <= (!ar) ? 8'd3 : 8'd0;
+end
+
+wire [12:0] fb_arx, arx, fb_ary, ary;
+
+video_scale_int fb_scale
+(
+	.*,
+	.hsize(fb_width),
+	.vsize(fb_height),
+	.arx_o(fb_arx),
+	.ary_o(fb_ary)
+);
+
+video_freak video_freak
+(
+	.*,
+	.VGA_DE_IN(VGA_DE),
+	.VGA_DE(),
+	.ARX(arx_i),
+	.ARY(ary_i),
+	.CROP_SIZE(0),
+	.CROP_OFF(0),
+	.VIDEO_ARX(arx),
+	.VIDEO_ARY(ary)
+);
+
+assign VIDEO_ARX = fb_en ? fb_arx : arx;
+assign VIDEO_ARY = fb_en ? fb_ary : ary;
+
+////////////////////////////////////////////////////////////////////////
+
+assign DDRAM_ADDR[28:25] = 4'h3;
+
+system system
+(
+	.clk_sys              (clk_sys),
+	.clk_audio            (CLK_AUDIO),
+	.clk_uart1            (clk_uart1),
+	.clk_uart2            (clk_uart2),
+	.clk_mpu              (clk_mpu),
+	.clk_vga              (clk_vga),
+
+	.reset                (reset),
+
+	.clock_rate           (cur_rate),
+
+	.syscfg               (syscfg),
+	.l1_disable           (l1),
+	.l2_disable           (l2),
+
+	.video_ce             (vga_ce),
+	.video_f60            (~status[4] | f60),
+	.video_blank_n        (vga_de),
+	.video_hsync          (HSync),
+	.video_vsync          (VSync),
+	.video_r              (r),
+	.video_g              (g),
+	.video_b              (b),
+
+	.clock_rate_vga       (90000000),
+	.video_pal_a          (vga_pal_a),
+	.video_pal_d          (vga_pal_d),
+	.video_pal_we         (vga_pal_we),
+	.video_start_addr     (vga_start_addr),
+	.video_width          (vga_width),
+	.video_stride         (vga_stride),
+	.video_height         (vga_height),
+	.video_flags          (vga_flags),
+	.video_off            (vga_off),
+	.video_fb_en          (fb_en),
+	.video_lores          (~status[14]),
+	.video_border         (status[55] && ~fb_en), // hide border for high resolution and 16/24/32 bpp color modes (when fb_en)
+
+	.sample_cms_l         (cms_out_l),
+	.sample_cms_r         (cms_out_r),
+	.sample_sb_l          (sb_out_l),
+	.sample_sb_r          (sb_out_r),
+	.sample_opl_l         (opl_out_l),
+	.sample_opl_r         (opl_out_r),
+	.sample_gus_l         (gus_out_l),
+	.sample_gus_r         (gus_out_r),
+	.sound_fm_mode        (status[3]),
+	.sound_cms_en         (status[17]),
+	.sbp                  (sbp),
+	.vol_master_l         (vol_master_l),
+	.vol_master_r         (vol_master_r),
+	.vol_voice_l          (vol_voice_l),
+	.vol_voice_r          (vol_voice_r),
+	.vol_midi_l           (vol_midi_l),
+	.vol_midi_r           (vol_midi_r),
+	.vol_cd_l             (vol_cd_l),
+	.vol_cd_r             (vol_cd_r),
+	.vol_line_l           (vol_line_l),
+	.vol_line_r           (vol_line_r),
+	.vol_spk              (vol_spk),
+	.vol_en               (vol_en),
+	.speaker_out          (speaker_out),
+
+	.ps2_reset_n          (ps2_reset_n),
+
+	.ps2_kbclk_in         (ps2_kbd_clk_out),
+	.ps2_kbdat_in         (ps2_kbd_data_out),
+	.ps2_kbclk_out        (ps2_kbd_clk_in),
+	.ps2_kbdat_out        (ps2_kbd_data_in),
+
+	.ps2_mouseclk_in      (ps2_mouse_clk_out),
+	.ps2_mousedat_in      (ps2_mouse_data_out),
+	.ps2_mouseclk_out     (ps2_mouse_clk_in),
+	.ps2_mousedat_out     (ps2_mouse_data_in),
+
+	.joystick_dis         (joystick_dis),
+	.joystick_dig_1       (joystick_0 & dig_mask),
+	.joystick_dig_2       (status[47] ? 14'd0 : (joystick_1 & dig_mask)),
+	.joystick_ana_1       ({ja_1y,ja_1x}),
+	.joystick_ana_2       ({ja_2y,ja_2x}),
+	.joystick_mode        (status[13:12]),
+	.joystick_timed       (status[59:58]),
+
+	.mgmt_readdata        (mgmt_din),
+	.mgmt_writedata       (mgmt_dout),
+	.mgmt_address         (mgmt_addr),
+	.mgmt_write           (mgmt_wr),
+	.mgmt_read            (mgmt_rd),
+
+	.ide0_request         (mgmt_req[2:0]),
+	.ide1_request         (mgmt_req[5:3]),
+	.fdd_request          (mgmt_req[7:6]),
+	.floppy_wp            (status[2:1]),
+
+	.uart1_rx             (uart1_rx),
+	.uart1_tx             (uart1_tx),
+	.uart1_cts_n          (uart1_cts),
+	.uart1_dcd_n          (uart1_dcd),
+	.uart1_dsr_n          (uart1_dsr),
+	.uart1_rts_n          (uart1_rts),
+	.uart1_dtr_n          (uart1_dtr),
+
+	.uart2_rx             (uart2_rx),
+	.uart2_tx             (uart2_tx),
+	.uart2_cts_n          (uart2_cts),
+	.uart2_dcd_n          (uart2_dcd),
+	.uart2_dsr_n          (uart2_dsr),
+	.uart2_rts_n          (uart2_rts),
+	.uart2_dtr_n          (uart2_dtr),
+
+	.mpu_rx               (mpu_rx),
+	.mpu_tx               (mpu_tx),
+
+	.uma_ram              (status[57]),
+	.bootcfg              (status[37:32]),
+
+	.DDRAM_CLK            (DDRAM_CLK),
+	.DDRAM_ADDR           (DDRAM_ADDR[24:0]),
+	.DDRAM_DIN            (DDRAM_DIN),
+	.DDRAM_DOUT           (DDRAM_DOUT),
+	.DDRAM_DOUT_READY     (DDRAM_DOUT_READY),
+	.DDRAM_BE             (DDRAM_BE),
+	.DDRAM_BURSTCNT       (DDRAM_BURSTCNT),
+	.DDRAM_BUSY           (DDRAM_BUSY),
+	.DDRAM_RD             (DDRAM_RD),
+	.DDRAM_WE             (DDRAM_WE),
+
+	.pll_locked           (pll_locked),
+	.SDRAM_DQ             (SDRAM_DQ),
+	.SDRAM_A              (SDRAM_A),
+	.SDRAM_DQML           (SDRAM_DQML),
+	.SDRAM_DQMH           (SDRAM_DQMH),
+	.SDRAM_BA             (SDRAM_BA),
+	.SDRAM_nCS            (SDRAM_nCS),
+	.SDRAM_nWE            (SDRAM_nWE),
+	.SDRAM_nRAS           (SDRAM_nRAS),
+	.SDRAM_nCAS           (SDRAM_nCAS),
+	.SDRAM_CLK            (SDRAM_CLK),
+	.SDRAM_CKE            (SDRAM_CKE)
+);
+
+wire [7:0] syscfg;
+wire       ps2_reset_n;
+
+reg reset;
+always @(posedge clk_sys) begin
+	reg init_reset_n = 0;
+	reg old_rst = 0;
+
+	reset <= buttons[1] | status[0] | RESET | ~init_reset_n;
+
+	old_rst <= status[0];
+	if(old_rst & ~status[0]) init_reset_n <= 1;
+end
+
+reg dbg_menu = 0;
+always @(posedge clk_sys) begin
+	reg old_stb;
+	reg enter = 0;
+	reg esc = 0;
+
+	old_stb <= ps2_key[10];
+	if(old_stb ^ ps2_key[10]) begin
+		if(ps2_key[7:0] == 'h5A) enter <= ps2_key[9];
+		if(ps2_key[7:0] == 'h76) esc   <= ps2_key[9];
+	end
+
+	if(enter & esc) begin
+		dbg_menu <= ~dbg_menu;
+		enter <= 0;
+		esc <= 0;
+	end
+
+	if(status[7]) dbg_menu <= 1;
+end
+
+
+wire  [7:0] ja_1x,ja_1y,ja_2x,ja_2y;
+wire [15:0] dig_mask;
+wire  [1:0] joystick_dis;
+
+wire [7:0] pedal_combo;
+always_comb begin
+	ja_1x = joystick_l_analog_0[7:0];
+	ja_1y = joystick_l_analog_0[15:8];
+	ja_2x = joystick_l_analog_1[7:0];
+	ja_2y = joystick_l_analog_1[15:8];
+	dig_mask = '1;
+	joystick_dis = status[50:49];
+
+	case(status[48:47])
+		1: begin
+				ja_2x = joystick_r_analog_0[7:0];
+				ja_2y = joystick_r_analog_0[15:8];
+				joystick_dis[1] = status[49];
+			end
+		2: begin
+				ja_1y = 0;
+				if(joystick_l_analog_0[15]) ja_1y = joystick_l_analog_0[15:8];
+				if(joystick_r_analog_0[15]) ja_1y = ja_1y - joystick_r_analog_0[15:8];
+				ja_2y = 0;
+				if(joystick_l_analog_1[15]) ja_2y = joystick_l_analog_1[15:8];
+				if(joystick_r_analog_1[15]) ja_2y = ja_2y - joystick_r_analog_1[15:8];
+				dig_mask[3:0] = 0;
+			end
+		3: begin
+				ja_1y = joystick_l_analog_0[15] ? {joystick_l_analog_0[14:8] + 7'd63, 1'b0} : 8'd127;
+				ja_2y = joystick_r_analog_0[15] ? {joystick_r_analog_0[14:8] + 7'd63, 1'b0} : 8'd127;
+				ja_2x = joystick_r_analog_0[7]  ? {joystick_r_analog_0[6:0]  + 7'd63, 1'b0} : 8'd127;
+				dig_mask[3:0] = 0;
+				joystick_dis[1] = status[49];
+			end
+		default:;
+	endcase
+end
+
+////////////////////////////  MT32pi  //////////////////////////////////
+
+wire        mt32_reset    = status[40] | reset;
+wire        mt32_disable  = status[24];
+wire        mt32_mode_req = status[26];
+wire  [1:0] mt32_rom_req  = status[28:27];
+wire  [7:0] mt32_sf_req   = status[31:29];
+wire  [1:0] mt32_info     = status[42:41];
+
+wire [15:0] mt32_i2s_r, mt32_i2s_l;
+wire  [7:0] mt32_mode, mt32_rom, mt32_sf;
+wire        mt32_lcd_en, mt32_lcd_pix, mt32_lcd_update;
+wire        midi_rx;
+
+wire mt32_newmode;
+wire mt32_available;
+wire mt32_use  = mt32_available & ~mt32_disable;
+wire mt32_mute = mt32_available &  mt32_disable;
+
+wire [6:0] mt32_out;
+mt32pi mt32pi
+(
+	.*,
+	.reset(mt32_reset),
+	.USER_IN(user_io_mode ? 7'h7F : USER_IN),
+	.USER_OUT(mt32_out),
+	.midi_tx(mpu_tx | mt32_mute)
+);
+
+reg mt32_info_req;
+reg [3:0] mt32_info_disp;
+always @(posedge clk_sys) begin
+	reg old_mode;
+
+	old_mode <= mt32_newmode;
+	mt32_info_req <= (old_mode ^ mt32_newmode) && (mt32_info == 1);
+
+	mt32_info_disp <= (mt32_mode == 'hA2) ? (4'd1 + mt32_sf[2:0]) :
+	                  (mt32_mode == 'hA1 && mt32_rom == 0) ?  4'd9 :
+	                  (mt32_mode == 'hA1 && mt32_rom == 1) ?  4'd10 :
+	                  (mt32_mode == 'hA1 && mt32_rom == 2) ?  4'd11 : 4'd12;
+end
+
+reg mt32_lcd_on;
+always @(posedge CLK_VIDEO) begin
+	int to;
+	reg old_update;
+
+	old_update <= mt32_lcd_update;
+	if(to) to <= to - 1;
+
+	if(mt32_info == 2) mt32_lcd_on <= 1;
+	else if(mt32_info != 3) mt32_lcd_on <= 0;
+	else begin
+		if(!to) mt32_lcd_on <= 0;
+		if(old_update ^ mt32_lcd_update) begin
+			mt32_lcd_on <= 1;
+			to <= 90000000 * 2;
+		end
+	end
+end
+
+wire mt32_lcd = mt32_lcd_on & mt32_lcd_en;
+
+////////////////////////////  AUDIO  ///////////////////////////////////
+
+// PC Speaker
+wire        speaker_out, speaker_out_clk_audio;
+wire  [1:0] vol_spk;
+reg  [16:0] spk_out;
+
+synchronizer speaker_out_sync
+(
+	.clk(CLK_AUDIO),
+	.in(speaker_out),
+	.out(speaker_out_clk_audio)
+);
+
+always @(posedge CLK_AUDIO) begin
+	reg [16:0] spk;
+	spk <= {2'b00, {3'b000,speaker_out_clk_audio} << status[19:18], 11'd0};
+	spk_out <= spk >> ~vol_spk;
+end
+
+wire [15:0] gus_out_l, gus_out_r;
+
+// CD-DA (Redbook audio)
+wire [15:0] cdda_l;
+wire [15:0] cdda_r;
+wire [31:0] cdda_dout;
+wire        cdda_req;
+wire        cdda_wr;
+
+cdda #(24576000) cdda
+(
+	.CLK(clk_sys),
+	.CDDA_REQ(cdda_req),
+	.CDDA_WR(cdda_wr),
+	.CDDA_DATA(cdda_dout),
+
+	.VOLUME_L(4'b1111),
+	.VOLUME_R(4'b1111),
+
+	.CLK_AUDIO(CLK_AUDIO),
+	.AUDIO_L(cdda_l),
+	.AUDIO_R(cdda_r)
+);
+
+wire  [8:0] cms_out_l, cms_out_r;
+wire [15:0] sb_out_l,  sb_out_r;
+wire [15:0] opl_out_l, opl_out_r;
+
+wire        sbp;
+wire  [4:0] vol_master_l, vol_master_r, vol_voice_l, vol_voice_r, vol_midi_l, vol_midi_r, vol_cd_l, vol_cd_r, vol_line_l, vol_line_r;
+wire  [4:0] vol_en;
+
+// Select MT-32 volume control
+wire  [4:0] vol_mt32_l = ~status[25] ? vol_midi_l : vol_en[4] ? vol_line_l : 5'd0;
+wire  [4:0] vol_mt32_r = ~status[25] ? vol_midi_r : vol_en[3] ? vol_line_r : 5'd0;
+
+// Apply per-channel volume controls
+wire [15:0] master_l, master_r, sb_l, sb_r, opl_l, opl_r, cd_l, cd_r, mt32_l, mt32_r;
+wire        sb_volume_valid;
+sb_volume #(.NUM_CH(10), .SAMPLE_WIDTH(16)) sb_volume_inst (
+	.clk(CLK_AUDIO),
+	.sbp(sbp),
+	// Volume controls
+	.volumes_in({vol_master_l, vol_master_r,  // Master volume  
+	             vol_voice_l,  vol_voice_r,   // Voice (SB DAC/DMA)
+	             vol_midi_l,   vol_midi_r,    // MIDI (FM/OPL)
+	             vol_cd_l,     vol_cd_r,      // CD
+	             vol_mt32_l,   vol_mt32_r}),  // MT-32
+	// Pre-volume audio samples
+	.samples_in({mix_pre_l,    mix_pre_r,     // Master mix (pre-volume)
+	             sb_out_l,     sb_out_r,      // SB DAC/DMA
+	             opl_out_l,    opl_out_r,     // OPL2/3 FM synthesis
+	             cdda_l,       cdda_r,        // CD-DA (Redbook audio)
+	             mt32_i2s_l,   mt32_i2s_r}),  // MT-32 I2S
+	// Post-volume audio samples
+	.samples_out({master_l,    master_r,
+	              sb_l,        sb_r,
+	              opl_l,       opl_r,
+	              cd_l,        cd_r,
+	              mt32_l,      mt32_r}),
+	.valid(sb_volume_valid)
+);
+
+// SB channel swap after volume stage
+wire [15:0] sb_l_swap = status[56] ? sb_r : sb_l;
+wire [15:0] sb_r_swap = status[56] ? sb_l : sb_r;
+
+reg [15:0] mix_dry_l, mix_dry_r;
+reg [15:0] audio_l, audio_r;
+always @(posedge CLK_AUDIO) begin
+	reg [16:0] mix_tmp_l, mix_tmp_r;
+
+	if (sb_volume_valid) begin
+		audio_l <= master_l;
+		audio_r <= master_r;
+
+		mix_tmp_l <= spk_out                                    // PC Speaker
+		           + {2'b00, cms_out_l, cms_out_l[8:4]}         // C/MS or Game Blaster
+		           + {sb_l_swap[15],sb_l_swap}                  // SB DAC/DMA
+		           + {opl_l[15],opl_l}                          // OPL2/3 FM synthesis
+		           + (vol_en[2] ? {cd_l[15],cd_l} : 17'd0)      // CD-DA (Redbook audio)
+		           + (mt32_mute ? 17'd0 : {mt32_l[15],mt32_l})  // MT-32
+		           + {gus_out_l[15],gus_out_l};                 // GUS
+		mix_tmp_r <= spk_out
+		           + {2'b00, cms_out_r, cms_out_r[8:4]}
+		           + {sb_r_swap[15],sb_r_swap}
+		           + {opl_r[15],opl_r}
+		           + (vol_en[1] ? {cd_r[15],cd_r} : 17'd0)
+		           + (mt32_mute ? 17'd0 : {mt32_r[15],mt32_r})
+		           + {gus_out_r[15],gus_out_r};
+	end
+
+	// Hard clip to prevent overflow
+	mix_dry_l <= (^mix_tmp_l[16:15]) ? {mix_tmp_l[16], {15{mix_tmp_l[15]}}} : mix_tmp_l[15:0];
+	mix_dry_r <= (^mix_tmp_r[16:15]) ? {mix_tmp_r[16], {15{mix_tmp_r[15]}}} : mix_tmp_r[15:0];
+end
+
+// Audio compression
+wire [15:0] mix_cmp_l, mix_cmp_r;
+acompr acompr_l(CLK_AUDIO, status[21], mix_dry_l, mix_cmp_l);
+acompr acompr_r(CLK_AUDIO, status[21], mix_dry_r, mix_cmp_r);
+
+// Select between compressed/dry pre-volume master mix
+wire [15:0] mix_pre_l = status[21:20] ? mix_cmp_l : mix_dry_l;
+wire [15:0] mix_pre_r = status[21:20] ? mix_cmp_r : mix_dry_r;
+
+assign AUDIO_L   = audio_l;
+assign AUDIO_R   = audio_r;
+assign AUDIO_S   = 1;
+assign AUDIO_MIX = status[44:43];
+
+////////////////////////////////////////////////////////////////////////
+
+endmodule
+
+module led
+(
+	input      clk,
+	input      in,
+	output reg out
+);
+
+integer counter = 0;
+always @(posedge clk) begin
+	if(!counter) out <= 0;
+	else begin
+		counter <= counter - 1'b1;
+		out <= 1;
+	end
+
+	if(in) counter <= 4500000;
+end
+
+endmodule
+
+module acompr
+(
+	input             clk,
+	input             mode,
+	input      [15:0] inp,
+	output reg [15:0] out
+);
+
+localparam [3:0] comp_f1 = 4;
+localparam [3:0] comp_a1 = 2;
+localparam       comp_x1 = ((32767 * (comp_f1 - 1)) / ((comp_f1 * comp_a1) - 1)) + 1; // +1 to make sure it won't overflow
+localparam       comp_b1 = comp_x1 * comp_a1;
+
+localparam [3:0] comp_f2 = 8;
+localparam [3:0] comp_a2 = 4;
+localparam       comp_x2 = ((32767 * (comp_f2 - 1)) / ((comp_f2 * comp_a2) - 1)) + 1; // +1 to make sure it won't overflow
+localparam       comp_b2 = comp_x2 * comp_a2;
+
+always @(posedge clk) begin
+	reg [15:0] v, v1, v2, v3;
+	reg vs, vs1, vs3;
+
+	v   <= inp[15] ? -inp : inp;
+	vs  <= inp[15];
+
+	v1  <= (v < comp_x1[15:0]) ? (v * comp_a1) : (((v - comp_x1[15:0])/comp_f1) + comp_b1[15:0]);
+	v2  <= (v < comp_x2[15:0]) ? (v * comp_a2) : (((v - comp_x2[15:0])/comp_f2) + comp_b2[15:0]);
+	vs1 <= vs;
+
+	v3  <= mode ? v2 : v1;
+	vs3 <= vs1;
+
+	out <= vs3 ? -v3 : v3;
+end
+
+endmodule

MiSTer-devel_ao486_MiSTer/clean.bat

@@ -0,0 +1,36 @@
+@echo off
+del /s *.bak
+del /s *.orig
+del /s *.rej
+del /s *~
+rmdir /s /q db
+rmdir /s /q incremental_db
+rmdir /s /q output_files
+rmdir /s /q simulation
+rmdir /s /q greybox_tmp
+rmdir /s /q hc_output
+rmdir /s /q .qsys_edit
+rmdir /s /q hps_isw_handoff
+rmdir /s /q sys\.qsys_edit
+rmdir /s /q sys\vip
+for /d %%i in (sys\*_sim) do rmdir /s /q "%%i"
+for /d %%i in (rtl\*_sim) do rmdir /s /q "%%i"
+del build_id.v
+del c5_pin_model_dump.txt
+del PLLJ_PLLSPE_INFO.txt
+del /s *.qws
+del /s *.ppf
+del /s *.ddb
+del /s *.csv
+del /s *.cmp
+del /s *.sip
+del /s *.spd
+del /s *.bsf
+del /s *.f
+del /s *.sopcinfo
+del /s *.xml
+del *.cdf
+del *.rpt
+del /s new_rtl_netlist
+del /s old_rtl_netlist
+pause

MiSTer-devel_ao486_MiSTer/clean.sh

@@ -0,0 +1,35 @@
+#!/bin/sh
+rm -rf *.bak
+rm -rf *.orig
+rm -rf *.rej
+rm -rf *~
+rm -rf db
+rm -rf incremental_db
+rm -rf output_files
+rm -rf simulation
+rm -rf greybox_tmp
+rm -rf hc_output
+rm -rf .qsys_edit
+rm -rf hps_isw_handoff
+rm -rf sys/.qsys_edit
+rm -rf sys/vip
+rm -rf sys/*_sim
+rm -rf rtl/*_sim
+rm -rf build_id.v
+rm -rf c5_pin_morm_dump.txt
+rm -rf PLLJ_PLLSPE_INFO.txt
+rm -rf *.qws
+rm -rf *.ppf
+rm -rf *.ddb
+rm -rf *.csv
+rm -rf *.cmp
+rm -rf *.sip
+rm -rf *.spd
+rm -rf *.bsf
+rm -rf *.f
+rm -rf *.sopcinfo
+rm -rf *.xml
+rm -rf *.cdf
+rm -rf *.rpt
+rm -rf new_rtl_netlist
+rm -rf old_rtl_netlist

MiSTer-devel_ao486_MiSTer/files.qip

@@ -0,0 +1,24 @@
+set_global_assignment -name SEARCH_PATH ./rtl/ao486
+set_global_assignment -name QIP_FILE rtl/pll2.qip
+set_global_assignment -name QIP_FILE rtl/ao486/ao486.qip
+set_global_assignment -name QIP_FILE rtl/cache/cache.qip
+set_global_assignment -name QIP_FILE rtl/soc/uart/uart.qip
+set_global_assignment -name QIP_FILE rtl/soc/sound/sound.qip
+set_global_assignment -name QIP_FILE rtl/soc/gus/gus.qip
+set_global_assignment -name QIP_FILE rtl/common/common.qip
+set_global_assignment -name VERILOG_FILE rtl/soc/iobus.v
+set_global_assignment -name VERILOG_FILE rtl/soc/floppy.v
+set_global_assignment -name VERILOG_FILE rtl/soc/ide.v
+set_global_assignment -name VERILOG_FILE rtl/soc/cdda.v
+set_global_assignment -name VERILOG_FILE rtl/soc/joystick.v
+set_global_assignment -name VERILOG_FILE rtl/soc/dma.v
+set_global_assignment -name VERILOG_FILE rtl/soc/pic.v
+set_global_assignment -name VERILOG_FILE rtl/soc/pit.v
+set_global_assignment -name VERILOG_FILE rtl/soc/pit_counter.v
+set_global_assignment -name VERILOG_FILE rtl/soc/ps2.v
+set_global_assignment -name VERILOG_FILE rtl/soc/rtc.v
+set_global_assignment -name VERILOG_FILE rtl/soc/vga.v
+set_global_assignment -name VERILOG_FILE rtl/system.v
+set_global_assignment -name VERILOG_FILE rtl/hps_ext.v
+set_global_assignment -name SDC_FILE ao486.sdc
+set_global_assignment -name SYSTEMVERILOG_FILE ao486.sv

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