Add batch 5 (vicharak-in_shrike, hunterlew_convolution_network_on_FPGA, jhshi_openofdm, dpretet_async_fifo, AngeloJacobo_UberDDR3)

.gitattributes

@@ -569,3 +569,17 @@ danfoisy_vdatp/mech/LED[[:space:]]mount1.stl filter=lfs diff=lfs merge=lfs -text
 danfoisy_vdatp/mech/bracket.stl filter=lfs diff=lfs merge=lfs -text
 danfoisy_vdatp/media/colorballsm.JPG filter=lfs diff=lfs merge=lfs -text
 zephray_VerilogBoy/sim/vb_sim filter=lfs diff=lfs merge=lfs -text
+AngeloJacobo_UberDDR3/example_demo/orangecrab_ecp5/orangecrab_ecp5_ddr3.dfu filter=lfs diff=lfs merge=lfs -text
+hunterlew_convolution_network_on_FPGA/validation_with_matlab/net-epoch-73.mat filter=lfs diff=lfs merge=lfs -text
+jhshi_openofdm/testing_inputs/conducted/dot11a_12mbps_qos_data_e4_90_7e_15_2a_16_e8_de_27_90_6e_42.dat filter=lfs diff=lfs merge=lfs -text
+jhshi_openofdm/testing_inputs/conducted/dot11a_6mbps_qos_data_e4_90_7e_15_2a_16_e8_de_27_90_6e_42.dat filter=lfs diff=lfs merge=lfs -text
+jhshi_openofdm/testing_inputs/conducted/dot11a_9mbps_qos_data_e4_90_7e_15_2a_16_e8_de_27_90_6e_42.dat filter=lfs diff=lfs merge=lfs -text
+jhshi_openofdm/testing_inputs/conducted/dot11n_13mbps_98_5f_d3_c7_06_27_e8_de_27_90_6e_42.dat filter=lfs diff=lfs merge=lfs -text
+jhshi_openofdm/testing_inputs/conducted/dot11n_19.5mbps_98_5f_d3_c7_06_27_e8_de_27_90_6e_42.dat filter=lfs diff=lfs merge=lfs -text
+jhshi_openofdm/testing_inputs/conducted/dot11n_6.5mbps_98_5f_d3_c7_06_27_e8_de_27_90_6e_42.dat filter=lfs diff=lfs merge=lfs -text
+jhshi_openofdm/testing_inputs/conducted/dot11n_7.2mbps_98_5f_d3_c7_06_27_e8_de_27_90_6e_42.dat filter=lfs diff=lfs merge=lfs -text
+jhshi_openofdm/testing_inputs/radiated/dot11n_26mbps.dat filter=lfs diff=lfs merge=lfs -text
+jhshi_openofdm/testing_inputs/radiated/dot11n_6.5mbps.dat filter=lfs diff=lfs merge=lfs -text
+vicharak-in_shrike/archive/firmware/shrike-lite_v_0.uf2 filter=lfs diff=lfs merge=lfs -text
+vicharak-in_shrike/archive/shrike_1.0_r0.2_v1.uf2 filter=lfs diff=lfs merge=lfs -text
+vicharak-in_shrike/examples/shrike_picorv32_xip/firmware/rp2040/shrike_xip.uf2 filter=lfs diff=lfs merge=lfs -text

AngeloJacobo_UberDDR3/.gitignore

@@ -0,0 +1,27 @@
+formal/ddr3_multiconfig*prf*
+formal/ddr3_multiconfig_default/
+formal/ddr3_multiconfig_ecc/
+formal/ecc/
+formal/ddr3_singleconfig/
+example_demo/nexys_video/build/
+testbench/xsim/xsim*
+testbench/xsim/*backup*
+testbench/xsim/*.log
+testbench/xsim/*.pb
+testbench/xsim/*.wdb
+example_demo/*/build/*
+example_demo/build_logs*
+*.fasm
+*.frames
+*.bin
+*.json
+*.bba
+*toolchain-nix*
+testbench/ddr3_dimm_micron_sim_behav.wcfg
+testbench/icarus_sim/*.log
+testbench/icarus_sim/uberddr3_sim
+*jobid
+.caas*
+
+# But do not ignore testbench/xsim/test_*.log
+!testbench/xsim/test_*.log

AngeloJacobo_UberDDR3/LICENSE

@@ -0,0 +1,674 @@
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AngeloJacobo_UberDDR3/README.md

@@ -0,0 +1,234 @@
+
+# Table of Contents  
+ - [Brief Description](https://github.com/AngeloJacobo/DDR3_Controller#brief-description)
+ - [Open IP Hub Blog Posts](https://github.com/AngeloJacobo/UberDDR3/edit/main/README.md#open-ip-hub-blog-posts)
+ - [Getting Started](https://github.com/AngeloJacobo/DDR3_Controller#getting-started)
+    - [Instantiate Design](https://github.com/AngeloJacobo/DDR3_Controller#heavy_check_mark-instantiate-design)
+    - [Create Constraint File](https://github.com/AngeloJacobo/DDR3_Controller#heavy_check_mark-create-constraint-file)
+    - [Edit Localparams](https://github.com/AngeloJacobo/DDR3_Controller#heavy_check_mark-edit-localparams)
+ - [Lint and Formal Verification](https://github.com/AngeloJacobo/DDR3_Controller#lint-and-formal-verification)
+ - [Simulation](https://github.com/AngeloJacobo/DDR3_Controller#simulation)
+ - [Demo Projects](https://github.com/AngeloJacobo/UberDDR3/tree/main?tab=readme-ov-file#demo-projects)
+
+   
+# Brief Description
+This DDR3 controller was originally designed to be used on the [10-Gigabit Ethernet Project](https://github.com/ZipCPU/eth10g) for an 8-lane x8 DDR3 module running at 800 MHz DDR, but this is now being designed to be a more general-purpose DDR3 memory controller with multiple supported FPGA boards. This is a 4:1 memory controller with configurable timing parameters and mode registers so it can be configured to any DDR3 memory device. The user-interface is the basic Wishbone. Optional features include:
+- AXI4 User Interface ([blog post here](https://www.openiphub.com/post/uberddr3-new-feature-axi4-interface))
+- SECDEC for error correction ([blog post here](https://www.openiphub.com/post/uberddr3-feature-update-error-correction-part-1-post-5))
+- Self-Refresh ([blog post here](https://www.openiphub.com/post/uberddr3-self-refresh-reducing-power-consumption-in-idle-periods-post-9))
+- Dual-rank Support ([blog post here](https://www.openiphub.com/post/unlocking-more-memory-dual-rank-dimm-support-in-uberddr3-post-10))
+- Integratable with MicroBlaze ([blog post here](https://www.openiphub.com/post/uberddr3-microblaze-part-1-post-7))
+- Built-in self test
+  
+This memory controller is optimized to maintain a high data throughput and continuous sequential burst operations. The controller handles the reset sequence, refresh sequence, mode register configuration, bank status tracking, timing delay tracking, command issuing, and the PHY's calibration. The PHY's calibration handles the bitslip training, read-DQ/DQS alignment via MPR (read calibration), write-DQ/DQS alignment via write leveling (write calibration), and also an optional comprehensive read/write test. 
+
+The optional built-in self read/write tests made it easier to test the memory controller without needing an external CPU. These tests include a burst access, random access, and alternating read-write access tests. Only if no error is found on these tests will the calibration end and user can start accessing the wishbone interface. 
+
+This design is [formally verified](https://github.com/AngeloJacobo/DDR3_Controller#lint-and-formal-verification) and [simulated using the Micron DDR3 model](https://github.com/AngeloJacobo/DDR3_Controller#simulation).
+
+# Open IP Hub Blog Posts
+Check out these blog posts for detailed explanations on new features of UberDDR3, how to use them, and project demos:  
+- [UberDDR3: An Opensource DDR3 Controller - Post #1](https://www.openiphub.com/post/uberddr3-an-opensource-ddr3-controller-post-1)  
+- [Getting Started with UberDDR3 (Part 1) - Post #2](https://www.openiphub.com/post/getting-started-with-uberddr3-part-1-post-2)  
+- [Getting Started with UberDDR3 (Part 2) - Post #3](https://www.openiphub.com/post/getting-started-with-uberddr3-part-2-post-3)  
+- [UberDDR3 Update: AXI4 Interface - Post #4](https://www.openiphub.com/post/uberddr3-new-feature-axi4-interface)  
+- [UberDDR3 Update: Error Correction (Part 1) - Post #5](https://www.openiphub.com/post/uberddr3-feature-update-error-correction-part-1-post-5)  
+- [UberDDR3 Feature Update: Error Correction (Part 2) - Post #6](https://www.openiphub.com/post/uberddr3-feature-update-error-correction-part-2-post-6)  
+- [UberDDR3 + MicroBlaze (Part 1) - Post #7](https://www.openiphub.com/post/uberddr3-microblaze-part-1-post-7)  
+- [UberDDR3 + MicroBlaze (Part 2) - Post #8](https://www.openiphub.com/post/uberddr3-microblaze-part-2-post-8)  
+- [UberDDR3 Self-Refresh: Reducing Power Consumption in Idle Periods - Post #9](https://www.openiphub.com/post/uberddr3-self-refresh-reducing-power-consumption-in-idle-periods-post-9)  
+- [Unlocking More Memory: Dual-Rank DIMM Support in UberDDR3 - Post #10](https://www.openiphub.com/post/unlocking-more-memory-dual-rank-dimm-support-in-uberddr3-post-10)   
+
+# Getting Started
+The recommended way to instantiate this IP is to use the top module [`rtl/ddr3_top.v`](https://github.com/AngeloJacobo/DDR3_Controller/blob/main/rtl/ddr3_top.v), a template for instantiation is also included in that file. Steps to include this DDR3 memory controller IP is to instantiate design, create the constraint file, then edit the localparams. 
+
+## :heavy_check_mark: Instantiate Design
+The first thing to edit are the **top-level parameters**:
+
+| Parameter | Function |
+| :---:        |     :---       | 
+| CONTROLLER_CLK_PERIOD   | clock period of the controller interface in picoseconds. Tested values range from `12_000` ps (83.33 MHz) to `10_000` ps (100 MHz).     | 
+| DDR3_CLK_PERIOD     | clock period of the DDR3 RAM device in picoseconds which must be 1/4 of the `CONTROLLER_CLK_PERIOD`. Tested values range from `3_000` ps (333.33 MHz) to `2_500` ps (400 MHz).     |
+| ROW_BITS     | width of row address. Use chapter _2.11 DDR3 SDRAM Addressing_ from [JEDEC DDR3 doc (page 15)](https://www.jedec.org/sites/default/files/docs/JESD79-3F.pdf) as a guide. Possible values range from `12` to `16`.     |
+| COL_BITS     | width of column address. Use chapter _2.11 DDR3 SDRAM Addressing_ from [JEDEC DDR3 doc (page 15)](https://www.jedec.org/sites/default/files/docs/JESD79-3F.pdf) as a guide. Possible values range from `10` to `12`.     |
+| BA_BITS     | width of bank address. Use chapter _2.11 DDR3 SDRAM Addressing_ from [JEDEC DDR3 doc (page 15)](https://www.jedec.org/sites/default/files/docs/JESD79-3F.pdf) as a guide. Usual value is `3`.      
+| BYTE_LANES  | number of bytes based on width of DQ. <sup>[[1]](https://github.com/AngeloJacobo/DDR3_Controller#note) </sup> |
+| AUX_WIDTH | width of auxiliary line. Value must be >= 4.  <sup>[[2]](https://github.com/AngeloJacobo/DDR3_Controller#note) </sup>  |
+| WB2_ADDR_BITS | width of 2nd wishbone address bus for debugging (only relevant if SECOND_WISHBONE = 1).   |
+| WB2_DATA_BITS  | width of 2nd wishbone data bus for debugging (only relevant if SECOND_WISHBONE = 1).  |
+| MICRON_SIM  | set to 1 if used in Micron DDR3 model to shorten power-on sequence, otherwise 0. |
+| ODELAY_SUPPORTED | set to 1 if ODELAYE2 primitive is supported by the FPGA, otherwise 0.  <sup>[[3]](https://github.com/AngeloJacobo/DDR3_Controller#note) </sup>  |
+| SECOND_WISHBONE | set to 1 if 2nd wishbone for debugging is needed , otherwise 0.|
+| WB_ERROR | set to 1 to support Wishbone error (asserts at ECC double bit error assuming ECCE_ENABLE != 0) |
+| SKIP_INTERNAL_TEST | set to 1 to skip built-in self test which usually takes > 2 seconds|
+| ECC_ENABLE |  set to 0 to disable ECC OR: 1 = Side-band ECC per burst, 2 = Side-band ECC per 8 bursts , 3 = Inline ECC (more about [ECC on this blog post](https://www.openiphub.com/post/uberddr3-feature-update-error-correction-part-1-post-5))|
+| DIC | Output Driver Impedance Control (2'b00 = RZQ/6, 2'b01 = RZQ/7, RZQ = 240ohms) (only change this when you know what you are doing) |
+| RTT_NOM | RTT Nominal (3'b000 = disabled, 3'b001 = RZQ/4, 3'b010 = RZQ/2 , 3'b011 = RZQ/6, RZQ = 240ohms)  (only change when you know what you are doing) |
+| SELF_REFRESH | 0 = use i_user_self_refresh input, 1 = Self-refresh mode is enabled after 64 controller clock cycles of no requests, 2 = 128 cycles, 3 = 256 cycles (more on [self-refresh on this blog post](https://www.openiphub.com/post/uberddr3-self-refresh-reducing-power-consumption-in-idle-periods-post-9))|
+***
+
+After the parameters, connect the ports of the top module to your design. Below are the **ports for clocks and reset**:
+| Ports | Function |
+| :---:        |     :---       | 
+| i_controller_clk   | clock of the controller interface with period of `CONTROLLER_CLK_PERIOD` | 
+| i_ddr3_clk   | clock of the DDR3 interface with period of `DDR3_CLK_PERIOD` | 
+| i_ref_clk   | reference clock for IDELAYCTRL primitive with frequency of 200 MHz | 
+| i_ddr3_clk_90   | clock required only if ODELAY_SUPPORTED = 0, otherwise can be left unconnected. Has a period of `DDR3_CLK_PERIOD` with 90° phase shift. | 
+| i_rst_n   | Active-low synchronous reset for the entire DDR3 controller and PHY | 
+
+It is recommended to generate all these clocks from a single PLL or clock-generator.
+
+***
+
+Next are the **main wishbone ports**:
+
+| Ports | Function |
+| :---:        |     :---       | 
+| i_wb_cyc   | Indicates if a bus cycle is active. A high value (1) signifies normal operation, while a low value (0) signals the cancellation of all ongoing transactions. | 
+| i_wb_stb   |  Strobe or transfer request signal. It's asserted (set to 1) to request a data transfer. | 
+| i_wb_we   | Write-enable signal. A high value (1) indicates a write operation, and a low value (0) indicates a read operation. | 
+| i_wb_addr  | Address bus. Used to specify the address for the current read or write operation. Formatted as {row, bank, column}. | 
+| i_wb_data   | Data bus for write operations. In a 4:1 controller, the data width is 8 times the DDR3 pins `8`x`DQ_BITS`x`LANES`. | 
+| i_wb_sel   | Byte select for write operations. Indicates which bytes of the data bus are to be overwritten for the write operation. | 
+| o_wb_stall   | Indicates if the controller is busy (1)and cannot accept any new requests. | 
+| o_wb_ack   |  Acknowledgement signal. Indicates that a read or write request has been completed. | 
+| o_wb_data   | Data bus for read operations. Similar to `i_wb_data`, the data width for a 4:1 controller is 8 times the DDR3 pins `8`x`DQ_BITS`x`LANES`. |
+
+***
+
+Below are the **auxiliary ports** associated with the main wishbone. This is not required for normal operation, but is intended for AXI-interface compatibility *which is not yet available*:  
+| Ports | Function |
+| :---:        |     :---       | 
+| i_aux   | Request ID line with width of `AUX_WIDTH`. The Request ID is retrieved simultaneously with the strobe request. | 
+| o_aux   | Request ID line with width of `AUX_WIDTH`. The Request ID is sent back concurrently with the acknowledgement signal.  | 
+
+
+***
+
+After main wishbone port are the **second-wishbone ports**. This interface is only for debugging-purposes and would normally not be needed thus can be left unconnected by setting `SECOND_WISHBONE` = 0. The ports for the second-wishbone is very much the same as the main wishbone.
+
+Next are the **DDR3 I/O ports**, these will be connected directly to the top-level pins of your design thus port-names must match what is indicated on your constraint file. You do not need to understand what each DDR3 I/O ports does but if you're curious, details on each DDR3 I/O pins are described on _2.10 Pinout Description_ from [JEDEC DDR3 doc (page 13)](https://www.jedec.org/sites/default/files/docs/JESD79-3F.pdf).
+
+Finally are the **debug ports**, these are connected to relevant registers containing information on current state of the controller. Trace each `o_debug_*` inside `ddr3_controller.v` to edit the registers to be monitored.
+
+## :heavy_check_mark: Create Constraint File
+* One example of constraint file is from the [Kintex-7 Ethernet Switch Project](https://github.com/AngeloJacobo/DDR3_Controller/blob/main/example_demo/klusterlab/kluster.xdc#L227-L389)  <sup>[[4]](https://github.com/AngeloJacobo/DDR3_Controller#note) </sup>, highlighted are all the DDR3 pins. This constraint file assumes a dual-rank DDR3 RAM (thus 2 pairs of `o_ddr3_clk`, `o_ddr3_cke`, `o_ddr3_s_n`, and `o_ddr3_odt`)  with 8 lanes of x8 DDR3 (thus 8 `o_ddr3_dm`, 8 `io_ddr3_dqs`, and 64 `io_ddr3_dq`). The constraint file also has [set_property](https://github.com/AngeloJacobo/DDR3_Controller/blob/main/example_demo/klusterlab/kluster.xdc#L453-L457) required for proper operation. The property `INTERNAL_VREF` must be set to half of the bank voltage (1.5V thus set to `0.75`). The property `BITSTREAM.STARTUP.MATCH_CYCLE` ([page 240 of UG628: Command Line Guide](https://docs.xilinx.com/v/u/en-US/devref)) is verified to work properly when value is set to `6`. Kintex-7 has HP bank where the DDR3 is connected thus allow the use of DCI (Digitally-Controlled Impedance) for impedance matching by using `SSTL15_T_DCI` type of `IOSTANDARD`.
+
+* Another example of constraint file is for the [Arty-S7 project]( https://github.com/AngeloJacobo/UberDDR3/blob/main/example_demo/arty_s7/Arty-S7-50-Master.xdc#L24-L244), highlighted are the DDR3 pins. The Arty-S7 has x16 DDR3 and it works like two x8 (thus 2 `ddr3_dm`, 2 `ddr3_dqs`, and 16 `io_ddr3_dq`) <sup>[[1]](https://github.com/AngeloJacobo/DDR3_Controller#note) </sup>. Arty-S7 only has HR bank where the DDR3 is connected, this restricts the design to use on-chip split-termination [(UG471 7-Series Select Guide page 33)](https://docs.xilinx.com/v/u/en-US/ug471_7Series_SelectIO) for impedance matching instead of DCI used in HP banks. `IN_TERM UNTUNED_SPLIT_50` signifies that the input termination is set to an untuned split termination of 50 ohms. The constraint file was  easily created by retrieving the pin constraints generated by the Vivado Memory Interface Generator (MIG) together with the [`.prj` file](https://github.com/Digilent/vivado-boards/blob/master/new/board_files/arty-s7-50/B.0/mig.prj#L47-L96) provided by Digilent for Arty-S7. The generated `.xdc` file by the MIG can be located at `[vivado_proj].gen/sources_1/ip/mig_7series_0/mig_7series_0/user_design/constraints/mig_7series_0.xdc`
+
+## :heavy_check_mark: Edit Localparams
+The verilog file [`rtl/ddr3_controller`](https://github.com/AngeloJacobo/DDR3_Controller/blob/main/rtl/ddr3_controller.v) contains the timing parameters that needs to be configured by the user to align with the DDR3 device. User should base the timing values on _Chapter 13 Electrical Characteristics and AC Timing_ from [JEDEC DDR3 doc (page 169)](https://www.jedec.org/sites/default/files/docs/JESD79-3F.pdf). _The default values on the verilog file should generally work for DDR3-800_. 
+
+### Note:  
+[1]: For x16 DDR3 like in Arty S7, use `BYTE_LANES` of 2. If the memory configuration is a SO-DIMM with 8 DDR3 RAM modules, each being x8 to form a total of 64 bits of data, then BYTE_LANES would be 8.  
+[2]: The auxiliary line is intended for AXI-interface compatibility but is also utilized in the reset sequence, which is the origin of the minimum required width of 4.  
+[3]: ODELAYE2 is supported if DDR3 device is connected to an HP (High-Powered) bank of FPGA. HR (High-Rank) bank does not support ODELAYE2 as based on [UG471 7-Series Select Guide (page 134)](https://docs.xilinx.com/v/u/en-US/ug471_7Series_SelectIO).   
+[4]: This is the open-sourced [10Gb Ethernet Project](https://github.com/ZipCPU/eth10g).
+
+
+***
+
+#  Lint and Formal Verification
+The easiest way to compile, lint, and formally verify the design is to run [`./run_compile.sh`](https://github.com/AngeloJacobo/DDR3_Controller/blob/main/run_compile.sh) on the top-level directory. This will first run [Verilator](https://verilator.org/guide/latest/install.html) lint.
+
+Next is compilation with [Yosys](https://github.com/YosysHQ/yosys), this will show warnings: 
+> Warning: Replacing memory ... with list of registers.
+
+Disregards this kind of warning as it just converts small memory elements in the design into a series of register elements.
+
+After Yosys compilation is [Icarus Verilog](https://github.com/steveicarus/iverilog) compilation, this should not show any warning or errors but will display the `Test Functions` to verify that the verilog-functions return the correct values, and `Controller Parameters` to verify the top-level parameters are set properly. Delay values for some timing parameters are also shown.
+
+Last is the [Symbiyosys Formal Verification](https://symbiyosys.readthedocs.io/en/latest/install.html), this will run the [single and multiple configuration sby](https://github.com/AngeloJacobo/UberDDR3/tree/main/formal) for formal verification. A summary is shown at the end where all tasks passed:  
+
+![image](https://github.com/AngeloJacobo/DDR3_Controller/assets/87559347/de554a92-880c-4513-83ba-a096da682f3b)
+
+
+# Simulation
+
+For simulation, the DDR3 SDRAM Verilog [Model from Micron](https://www.micron.com/search-results?searchRequest=DDR3+SDRAM+Verilog+Model&SelectedValues=%2Fsim-model--%2Fsim-model%2Fbdsl--%2Fsim-model%2Fbfm--%2Fsim-model%2Fcadence-dml--%2Fsim-model%2Fhspice--%2Fsim-model%2Fhyperlynx--%2Fsim-model%2Fibis--%2Fsim-model%2Fibis-ami--%2Fsim-model%2Fmentor-icx--%2Fsim-model%2Fs-parameter--%2Fsim-model%2Fspice--%2Fsim-model%2Fsisoft--%2Fsim-model%2Fsystem-c--%2Fsim-model%2Fsystem-verilog--%2Fsim-model%2Fthermal--%2Fsim-model%2Fverilog#accordion-db73c0b4db-item-4671aec5a3) is used. Import all simulation files under [./testbench](https://github.com/AngeloJacobo/DDR3_Controller/tree/main/testbench) to Vivado. [`ddr3_dimm_micron_sim.sv`](https://github.com/AngeloJacobo/DDR3_Controller/blob/main/testbench/ddr3_dimm_micron_sim.sv) is the top-level module which instantiates both the DDR3 memory controller and the Micron DDR3 model. This module issues read and write requests to the controller via the wishbone bus, then the returned data from read requests are verified if it matches the data written. Both sequential and random accesses are tested.
+
+Currently, there are 2 general options for running the simulation and is defined by a `define` directive on the `ddr3_dimm_micron_sim.sv` file: `TWO_LANES_x8` and `EIGHT_LANES_x8`. `TWO_LANES_x8` simulates an Arty-S7 FPGA board which has an x16 DDR3, meanwhile `EIGHT_LANES_x8` simulates 8-lanes of x8 DDR3 module. **Make sure to change the organization via a `define` directive under [ddr3.sv](https://github.com/AngeloJacobo/DDR3_Controller/blob/main/testbench/ddr3.sv)** (`TWO_LANES_x8` must use `define x8` while `EIGHT_LANES_x8` must use `define x16`).
+
+
+After configuring, run simulation. The `ddr3_dimm_micron_sim_behav.wcfg` contains the waveform. Shown below are the clocks:    
+![image](https://github.com/AngeloJacobo/DDR3_Controller/assets/87559347/f11afd00-ea17-4669-bebb-9f22e8ae6f6d)  
+
+
+As shown below, `command_used` shows the command issued at a specific time. During reads the `dqs` should toggle and `dq` should have a valid value, else they must be in high-impedance `Z`. Precharge and activate also happens between reads when row addresses are different. 
+![image](https://github.com/AngeloJacobo/DDR3_Controller/assets/87559347/a289066f-2a5c-4d08-9660-a76cf537383a)
+
+
+A part of internal test is to do alternate write then read consecutively as shown below. The data written must match the data read. `dqs` should also toggle along with the data written and read.  
+![image](https://github.com/AngeloJacobo/DDR3_Controller/assets/87559347/817124fa-43d0-4e9f-94c4-2889614d7c87)
+
+
+There are counters for the number of correct and wrong read data during the internal read/write test: `correct_read_data` and `wrong_read_data`. As shown below, the `wrong_read_data` must remain zero while `correct_read_data` must increment until it reaches the maximum (3499 on this example).  
+![image](https://github.com/AngeloJacobo/DDR3_Controller/assets/87559347/06d7b4c0-cd40-4fd1-9bc3-6329237e46e3)
+
+The simulation also reports the status of the simulation. For example, the report below:
+> [10000 ps]  RD @ (0,   840) -> [10000 ps]  RD @ (0,   848) -> [10000 ps]  RD @ (0,   856) -> [10000 ps]  RD @ (0,   864) -> [10000 ps]  RD @ (0,   872) -> 
+
+The format is [`time_delay`] `command` @ (`bank`, `address`), so `[10000 ps]  RD @ (0,   840)` means 10000 ps delay before a read command with bank 0 and address 840. Notice how each read command has a delay of 10000 ps or 10 ns from each other, since this has a controller clock of 100 MHz (10 ns clock period) this shows that there are no interruptions between sequential read commands resulting in a very high throughput. 
+
+A short report is also shown in each test section:  
+> DONE TEST 1: LAST ROW  
+Number of Operations: 2304  
+Time Started: 363390 ns  
+Time Done: 387980 ns  
+Average Rate: 10 ns/request  
+
+
+This report is after a burst write then burst read. This report means there were 2304 write and read operation, and the average time per request is 10 ns (1 controller clock period of 100 MHz). The average rate is optimal since this is a burst write and read. But for random writes and reads:  
+> DONE TEST 2: RANDOM  
+Number of Operations: 2304  
+Time Started: 387980 ns  
+Time Done: 497660 ns  
+Average Rate: 47 ns/request  
+
+
+Notice how the average rate increased to 47 ns/request. Random access requires occasional precharge and activate which takes time and thus prolong the time for every read or write access. At the very end of the report shows a summary:
+
+> TEST CALIBRATION  
+[-]: write_test_address_counter = 5000  
+[-]: read_test_address_counter = 2000  
+[-]: correct_read_data = 3499  
+[-]: wrong_read_data = 0  
+
+> ------- SUMMARY -------  
+Number of Writes = 4608  
+Number of Reads = 4608  
+Number of Success = 4604  
+Number of Fails = 4  
+Number of Injected Errors = 4  
+
+The summary under `TEST CALIBRATION` are the results from the **internal** read/write test as part of the internal calibration. These are the same counters on the waveform shown before where the `wrong_read_data` should be zero. Under `SUMMARY` is the report from the **external** read/write test where the top-level simulation file `ddr3_dimm_micron_sim.sv` sends read/write request to the DDR3 controller via the wishbone bus. Notice that the number of fails (4) matches the number of injected errors (4) which is only proper.  
+
+# Demo Projects
+- The [Arty-S7 demo project](./example_demo/arty_s7) is a basic project for testing the DDR3 controller. The gist is that the 4 LEDS should light-up which means reset sequence is done and all internal read/write test passed during calibration. This project also uses a UART line, sending small letters via UART will write those corresponding small letters to memory, meanwhile sending capital letters will read those small letters back from memory.
+   - To run this project on your Arty-S7 board, import all verilog files and xdc file under `example_demo/arty_s7/` and `rtl/`. Run synthesis-to-bitstream generation then upload the bitfile. After around 2 seconds, the 4 LEDS should light up then you can start interacting with the UART line. BTN0 button is for reset.
+   - Or just upload the [bitfile already given in the repo](./example_demo/arty_s7).
+
+- The [Nexys Video demo project](./example_demo/nexys_video)  utilizes the DDR3 chip on the Digilent Nexys Video board with xc7a200t. Only one lane is used for simplicity. Supports OpenXC7 toolchain. Makefiles have been included for quick start, just run the following command in the root directory of repo:
+
+  - Vivado compilation: `source /opt/Xilinx/Vivado/2019.1/settings64.sh` then `make -C example_demo/nexys_video -f Makefile.vivado`
+  - OpenXC7 compilation (using toolchain in Docker): `docker run --rm -v .:/mnt -v /chipdb:/chipdb regymm/openxc7 make -C /mnt/nexys_video -f Makefile.openxc7`
+
+  The bitstream will be compiled as `nexys_video/build/top.bit`. 
+
+  - Board test: after programming bitstream, the 8 LEDs will show some pattern, then become all lit up after calibration. When pressing BTND(D22), LD7/LD6 will show a blinky, and LD5-LD0 will show 101110 after successful calibration. BTNC(B22) resets the controller, and calibration will be redone. 9600 baud UART will be the same as the Arty-S7 case: type small `abcd` to write to memory, and type capital `ABCD` to read back. For example, type `abcd` then `ABCDEFGH` will show `abcd����` (because EFGH memory locations are not written yet). 
+- The [QMTech Wukong demo project](./example_demo/qmtech_wukong) is just the same as the arty-s7 demo mentioned above.
+   - To run this project on your [QMTech Wukong board](https://github.com/ChinaQMTECH/QM_XC7A100T_WUKONG_BOARD/tree/master/V3), import all verilog files and xdc file under `example_demo/qmtech_wukong/` and `rtl/`. Run synthesis-to-bitstream generation then upload the bitfile. After around 2 seconds, the 2 LEDS should light up then you can start interacting with the UART line. SW2 button is for reset.
+   - Or just upload the [bitfile already given in the repo](./example_demo/qmtech_wukong).
+- The [10Gb Ethernet Switch](https://github.com/ZipCPU/eth10g) project utilizes this DDR3 controller for accessing a single-rank DDR3 module (8 lanes of x8 DDR3) at DDR3-800 (100 MHz controller and 400 MHz PHY).
+
+# Other Open-Sourced DDR3 Controllers
+(soon...)
+
+# Developer Documentation 
+There is no developer documentation yet. But may I include here the [notes I compiled](https://github.com/AngeloJacobo/DDR3-Notes) when I did an intensive study on DDR3 before I started this project.
+
+# Acknowledgement
+This project is funded through [NGI0 Entrust](https://nlnet.nl/entrust), a fund established by [NLnet](https://nlnet.nl) with financial support from the European Commission's [Next Generation Internet](https://ngi.eu) program. Learn more at the [NLnet project page](https://nlnet.nl/project/UberDDR3).
+
+[<img src="https://nlnet.nl/logo/banner.png" alt="NLnet foundation logo" width="20%" />](https://nlnet.nl)
+[<img src="https://nlnet.nl/image/logos/NGI0_tag.svg" alt="NGI Zero Logo" width="20%" />](https://nlnet.nl/entrust)

AngeloJacobo_UberDDR3/example_demo/alinx_ax7103b/Makefile

@@ -0,0 +1,113 @@
+PROJECT = ax7103_ddr3
+FAMILY = artix7
+PART = xc7a100tfgg484-2
+CHIPDB  = ${ARTIX7_CHIPDB}
+ADDITIONAL_SOURCES = ../../rtl/ddr3_controller.v  ../../rtl/ddr3_phy.v  ../../rtl/ddr3_top.v  uart_rx.v  uart_tx.v clk_wiz.v 
+
+#############################################################################################
+NEXTPNR_XILINX_DIR ?= /snap/openxc7/current/opt/nextpnr-xilinx
+NEXTPNR_XILINX_PYTHON_DIR ?= ${NEXTPNR_XILINX_DIR}/python
+PRJXRAY_DB_DIR ?= ${NEXTPNR_XILINX_DIR}/external/prjxray-db
+
+DBPART = $(shell echo ${PART} | sed -e 's/-[0-9]//g')
+SPEEDGRADE = $(shell echo ${PART} | sed -e 's/.*\-\([0-9]\)/\1/g')
+
+CHIPDB ?= ./
+ifeq ($(CHIPDB),)
+CHIPDB = ./
+endif
+
+PYPY3 ?= pypy3
+
+TOP ?= ${PROJECT}
+TOP_MODULE ?= ${TOP}
+TOP_VERILOG ?= ${TOP}.v
+
+PNR_DEBUG ?= # --verbose --debug
+
+JTAG_LINK ?= -c digilent_hs2
+
+XDC ?= ${PROJECT}.xdc
+
+.PHONY: openxc7
+openxc7: ${PROJECT}_openxc7.bit
+
+.PHONY: program
+program: ${PROJECT}_openxc7.bit
+	openFPGALoader ${JTAG_LINK} --bitstream $<
+
+${PROJECT}.json: ${TOP_VERILOG} ${ADDITIONAL_SOURCES}
+	yosys -p "synth_xilinx -flatten -abc9 ${SYNTH_OPTS} -arch xc7 -top ${TOP_MODULE}; write_json ${PROJECT}.json" $< ${ADDITIONAL_SOURCES}
+
+# The chip database only needs to be generated once
+# that is why we don't clean it with make clean
+${CHIPDB}/${DBPART}.bin:
+	${PYPY3} ${NEXTPNR_XILINX_PYTHON_DIR}/bbaexport.py --device ${PART} --bba ${DBPART}.bba
+	bbasm -l ${DBPART}.bba ${CHIPDB}/${DBPART}.bin
+	rm -f ${DBPART}.bba
+
+${PROJECT}.fasm: ${PROJECT}.json ${CHIPDB}/${DBPART}.bin ${XDC}
+	nextpnr-xilinx --chipdb ${CHIPDB}/${DBPART}.bin --xdc ${XDC} --json ${PROJECT}.json --fasm $@ ${PNR_ARGS} ${PNR_DEBUG}
+	
+${PROJECT}.frames: ${PROJECT}.fasm
+	fasm2frames --part ${PART} --db-root ${PRJXRAY_DB_DIR}/${FAMILY} $< > $@
+
+${PROJECT}_openxc7.bit: ${PROJECT}.frames
+	xc7frames2bit --part_file ${PRJXRAY_DB_DIR}/${FAMILY}/${PART}/part.yaml --part_name ${PART} --frm_file $< --output_file $@
+
+
+#############################################################################################
+# SPDX-License-Identifier: MIT
+# Generated from https://github.com/FPGAOL-CE/caas-wizard
+#
+BUILDDIR := ${CURDIR}/build
+
+LOGFILE := ${BUILDDIR}/top.log
+
+# Build design
+.PHONY: vivado
+vivado: ${BUILDDIR}/${PROJECT}_vivado.bit
+
+${BUILDDIR}:
+	mkdir -m 777 -p ${BUILDDIR} && chown -R nobody ${BUILDDIR} | true
+
+.ONESHELL: 
+${BUILDDIR}/vivado.tcl: ${BUILDDIR}
+	cat << EOF > $@
+	# vivado.tcl generated for FPGAOL-CE/caas-wizard
+	# can be launched from any directory
+	cd ${BUILDDIR}
+	create_project -part ${PART} -force v_proj
+	set_property target_language Verilog [current_project]
+	cd ..
+	read_verilog [glob ${PROJECT}.v ${ADDITIONAL_SOURCES}]
+	read_xdc [glob  $(wildcard ${PROJECT}.xdc) ]
+	cd build
+	synth_design -top ${PROJECT}
+	opt_design
+	place_design
+	phys_opt_design
+	route_design
+	write_bitstream -verbose -force ${PROJECT}_vivado.bit
+	# report_utilization -file util.rpt
+	# report_timing_summary -file timing.rpt
+	EOF
+
+${BUILDDIR}/${PROJECT}_vivado.bit: ${BUILDDIR}/vivado.tcl
+	cd ${BUILDDIR} && vivado -mode batch -source $< > ${LOGFILE} 2>&1
+
+.PHONY: program_vivado
+program_vivado: 
+	openFPGALoader ${JTAG_LINK} --bitstream ${BUILDDIR}/${PROJECT}_vivado.bit
+
+#############################################################################################
+
+.PHONY: clean
+clean:
+	rm -f *.bit
+	rm -f *.frames
+	rm -f *.fasm
+	rm -f *.json
+	rm -f *.bin
+	rm -f *.bba
+	rm -rf ${BUILDDIR}

AngeloJacobo_UberDDR3/example_demo/alinx_ax7103b/ax7103_ddr3.v

@@ -0,0 +1,245 @@
+////////////////////////////////////////////////////////////////////////////////
+//
+// Filename: ax7103_ddr3.v
+// Project: UberDDR3 - An Open Source DDR3 Controller
+//
+// Purpose: Example demo of UberDDR3 for ALINX AX7103 (xc7a100tfgg484-2). Mechanism:
+//          - four LEDs will light up once UberDDR3 is done calibrating
+//          - if UART (9600 Baud Rate)receives small letter ASCII (a-z), this value will be written to DDR3 
+//          - if UART receives capital letter ASCII (A-Z), the small letter equivalent will be retrieved from DDR3 by doing
+//          - a read request, once read data is available this will be sent to UART to be streamed out.
+//          THUS:
+//          - Sendng "abcdefg" to the UART terminal will store that small latter to DDR3
+//          - Then sending "ABCDEFG" to the UART terminal will return the small letter equivalent: "abcdefg"
+//
+// Engineer: Angelo C. Jacobo
+//
+////////////////////////////////////////////////////////////////////////////////
+//
+// Copyright (C) 2023-2025  Angelo Jacobo
+// 
+//     This program is free software: you can redistribute it and/or modify
+//     it under the terms of the GNU General Public License as published by
+//     the Free Software Foundation, either version 3 of the License, or
+//     (at your option) any later version.
+// 
+//     This program is distributed in the hope that it will be useful,
+//     but WITHOUT ANY WARRANTY; without even the implied warranty of
+//     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//     GNU General Public License for more details.
+// 
+//     You should have received a copy of the GNU General Public License
+//     along with this program.  If not, see <https://www.gnu.org/licenses/>.
+//
+////////////////////////////////////////////////////////////////////////////////
+
+`timescale 1ns / 1ps
+
+   module ax7103_ddr3
+	(
+        input wire sys_clk_p, // system clock positive on board
+        input wire sys_clk_n, //system clock negative on board
+        input wire i_rst_n,
+        // DDR3 I/O Interface
+        output wire ddr3_ck_p, ddr3_ck_n,
+        output wire ddr3_reset_n,
+        output wire ddr3_cke, 
+        output wire ddr3_cs_n, 
+        output wire ddr3_ras_n, 
+        output wire ddr3_cas_n, 
+        output wire ddr3_we_n,
+        output wire[15-1:0] ddr3_addr,
+        output wire[3-1:0] ddr3_ba,
+        inout wire[32-1:0] ddr3_dq,
+        inout wire[4-1:0] ddr3_dqs_p, ddr3_dqs_n,
+        output wire[4-1:0] ddr3_dm,
+        output wire ddr3_odt, 
+        // UART line
+        input wire rx,
+        output wire tx,
+        //Debug LEDs
+        output wire[3:0] led
+    );
+     wire sys_clk_200MHz;
+     
+    IBUFDS sys_clk_ibufgds
+    (
+        .O(sys_clk_200MHz),
+        .I(sys_clk_p),
+        .IB(sys_clk_n)
+    );
+
+     wire i_controller_clk, i_ddr3_clk, i_ref_clk, i_ddr3_clk_90;
+     wire m_axis_tvalid;
+     wire rx_empty;
+     wire tx_full;
+     wire o_wb_ack;
+     wire[7:0] o_wb_data;
+     wire o_aux;
+     wire[7:0] rd_data;
+     wire o_wb_stall;
+     reg i_wb_stb = 0, i_wb_we;
+     wire[63:0] o_debug1;
+     reg[7:0] i_wb_data;
+     reg[7:0] i_wb_addr;
+     // o_debug1 taps on value of state_calibrate (can be traced inside ddr3_controller module)
+     assign led[0] = !(o_debug1[4:0] != 23); //light up if not at DONE_CALIBRATE
+     assign led[1] = !(o_debug1[4:0] == 23); //light up if at DONE_CALIBRATE
+     assign led[2] = !(o_debug1[4:0] == 23); //light up if at DONE_CALIBRATE
+     assign led[3] = !(o_debug1[4:0] == 23); //light up if at DONE_CALIBRATE
+     
+    always @(posedge i_controller_clk) begin
+        begin
+            i_wb_stb <= 0;
+            i_wb_we <= 0;
+            i_wb_addr <= 0;
+            i_wb_data <= 0;
+            if(!o_wb_stall && m_axis_tvalid) begin
+                if(rd_data >= 97 && rd_data <= 122) begin //write to DDR3 if ASCII is small letter
+                    i_wb_stb <= 1;                 
+                    i_wb_we <= 1;                  
+                    i_wb_addr <= ~rd_data ;                
+                    i_wb_data <= rd_data; 
+                end
+                else if(rd_data >= 65 && rd_data <= 90) begin //read from DDR3 if ASCII is capital letter
+                    i_wb_stb <= 1; //make request
+                    i_wb_we <= 0; //read
+                    i_wb_addr <= ~(rd_data + 8'd32);
+                end
+            end
+        end
+    end
+     
+    wire clk_locked;
+    clk_wiz clk_wiz_inst
+    (
+        // Clock out ports
+        .clk_out1(i_controller_clk), //83.333 Mhz
+        .clk_out2(i_ddr3_clk), // 333.333 MHz
+        .clk_out3(i_ref_clk), // 200 MHz 
+        .clk_out4(i_ddr3_clk_90), // 333.333 MHz 90-degree
+        // Status and control signals
+        .reset(!i_rst_n),
+        .locked(clk_locked),
+        // Clock in ports
+        .clk_in1(sys_clk_200MHz)
+    );
+
+    // UART TX/RXmodule from https://github.com/ben-marshall/uart
+    uart_tx #(
+        .BIT_RATE(9600),
+        .CLK_HZ(83_333_333),
+        .PAYLOAD_BITS(8),
+        .STOP_BITS(1)
+        ) uart_tx_inst (
+        .clk(i_controller_clk), // Top level system clock input.
+        .resetn(i_rst_n && clk_locked && o_debug1[4:0] == 23), // Asynchronous active low reset.
+        .uart_txd(tx), // UART transmit pin.
+        .uart_tx_busy(), // Module busy sending previous item.
+        .uart_tx_en(o_wb_ack), // Send the data on uart_tx_data
+        .uart_tx_data(o_wb_data) // The data to be sent
+    );
+    uart_rx #(
+        .BIT_RATE(9600),
+        .CLK_HZ(83_333_333),
+        .PAYLOAD_BITS(8),
+        .STOP_BITS(1)
+    ) uart_rx_inst (
+        .clk(i_controller_clk), // Top level system clock input.
+        .resetn(i_rst_n && clk_locked && o_debug1[4:0] == 23), // Asynchronous active low reset.
+        .uart_rxd(rx), // UART Recieve pin.
+        .uart_rx_en(o_debug1[4:0] == 23), // Recieve enable
+        .uart_rx_break(), // Did we get a BREAK message?
+        .uart_rx_valid(m_axis_tvalid), // Valid data recieved/available.
+        .uart_rx_data(rd_data)   // The recieved data.
+    );
+    
+
+    // UART module from https://github.com/alexforencich/verilog-uart (DOES NOT WORK ON OPENXC7, UberDDR3 cannot finish calibration when this UART is used)
+    //    uart #(.DATA_WIDTH(8)) uart_m
+    //    (
+    //         .clk(i_controller_clk),
+    //         .rst(!i_rst_n),
+    //         .s_axis_tdata(o_wb_data),
+    //         .s_axis_tvalid(o_wb_ack),
+    //         .s_axis_tready(),
+    //         .m_axis_tdata(rd_data),
+    //         .m_axis_tvalid(m_axis_tvalid),
+    //         .m_axis_tready(1),
+    //         .rxd(rx),
+    //         .txd(tx),
+    //        .prescale(1085) //9600 Baud Rate (83.33MHz/(8*9600))
+    //    );
+    
+    // DDR3 Controller 
+    ddr3_top #(
+        .CONTROLLER_CLK_PERIOD(12_000), //ps, clock period of the controller interface
+        .DDR3_CLK_PERIOD(3_000), //ps, clock period of the DDR3 RAM device (must be 1/4 of the CONTROLLER_CLK_PERIOD) 
+        .ROW_BITS(15), //width of row address
+        .COL_BITS(10), //width of column address
+        .BA_BITS(3), //width of bank address
+        .BYTE_LANES(4), //number of DDR3 modules to be controlled
+        .AUX_WIDTH(16), //width of aux line (must be >= 4) 
+        .WB2_ADDR_BITS(32), //width of 2nd wishbone address bus 
+        .WB2_DATA_BITS(32), //width of 2nd wishbone data bus
+        .MICRON_SIM(0), //enable faster simulation for micron ddr3 model (shorten POWER_ON_RESET_HIGH and INITIAL_CKE_LOW)
+        .ODELAY_SUPPORTED(0), //set to 1 when ODELAYE2 is supported
+        .SECOND_WISHBONE(0), //set to 1 if 2nd wishbone is needed 
+        .ECC_ENABLE(0), // set to 1 or 2 to add ECC (1 = Side-band ECC per burst, 2 = Side-band ECC per 8 bursts , 3 = Inline ECC ) 
+        .WB_ERROR(0), // set to 1 to support Wishbone error (asserts at ECC double bit error)
+        .DIC(2'b01), //Output Driver Impedance Control (2'b00 = RZQ/6, 2'b01 = RZQ/7, RZQ = 240ohms) (only change when you know what you are doing)
+        .RTT_NOM(3'b001) //RTT Nominal (3'b000 = disabled, 3'b001 = RZQ/4, 3'b010 = RZQ/2 , 3'b011 = RZQ/6, RZQ = 240ohms)  (only change when you know what you 
+        ) ddr3_top
+        (
+            //clock and reset
+            .i_controller_clk(i_controller_clk),
+            .i_ddr3_clk(i_ddr3_clk), //i_controller_clk has period of CONTROLLER_CLK_PERIOD, i_ddr3_clk has period of DDR3_CLK_PERIOD 
+            .i_ref_clk(i_ref_clk),
+            .i_ddr3_clk_90(i_ddr3_clk_90),
+            .i_rst_n(i_rst_n && clk_locked), 
+            // Wishbone inputs
+            .i_wb_cyc(1), //bus cycle active (1 = normal operation, 0 = all ongoing transaction are to be cancelled)
+            .i_wb_stb(i_wb_stb), //request a transfer
+            .i_wb_we(i_wb_we), //write-enable (1 = write, 0 = read)
+            .i_wb_addr(i_wb_addr), //burst-addressable {row,bank,col} 
+            .i_wb_data(i_wb_data), //write data, for a 4:1 controller data width is 8 times the number of pins on the device
+            .i_wb_sel(16'hffff), //byte strobe for write (1 = write the byte)
+            .i_aux(i_wb_we), //for AXI-interface compatibility (given upon strobe)
+            // Wishbone outputs
+            .o_wb_stall(o_wb_stall), //1 = busy, cannot accept requests
+            .o_wb_ack(o_wb_ack), //1 = read/write request has completed
+            .o_wb_data(o_wb_data), //read data, for a 4:1 controller data width is 8 times the number of pins on the device
+            .o_aux(o_aux),
+            // Wishbone 2 (PHY) inputs
+            .i_wb2_cyc(), //bus cycle active (1 = normal operation, 0 = all ongoing transaction are to be cancelled)
+            .i_wb2_stb(), //request a transfer
+            .i_wb2_we(), //write-enable (1 = write, 0 = read)
+            .i_wb2_addr(), //burst-addressable {row,bank,col} 
+            .i_wb2_data(), //write data, for a 4:1 controller data width is 8 times the number of pins on the device
+            .i_wb2_sel(), //byte strobe for write (1 = write the byte)
+            // Wishbone 2 (Controller) outputs
+            .o_wb2_stall(), //1 = busy, cannot accept requests
+            .o_wb2_ack(), //1 = read/write request has completed
+            .o_wb2_data(), //read data, for a 4:1 controller data width is 8 times the number of pins on the device
+            // PHY Interface (to be added later)
+            // DDR3 I/O Interface
+            .o_ddr3_clk_p(ddr3_ck_p),
+            .o_ddr3_clk_n(ddr3_ck_n),
+            .o_ddr3_reset_n(ddr3_reset_n),
+            .o_ddr3_cke(ddr3_cke), // CKE
+            .o_ddr3_cs_n(ddr3_cs_n), // chip select signal (controls rank 1 only)
+            .o_ddr3_ras_n(ddr3_ras_n), // RAS#
+            .o_ddr3_cas_n(ddr3_cas_n), // CAS#
+            .o_ddr3_we_n(ddr3_we_n), // WE#
+            .o_ddr3_addr(ddr3_addr),
+            .o_ddr3_ba_addr(ddr3_ba),
+            .io_ddr3_dq(ddr3_dq),
+            .io_ddr3_dqs(ddr3_dqs_p),
+            .io_ddr3_dqs_n(ddr3_dqs_n),
+            .o_ddr3_dm(ddr3_dm),
+            .o_ddr3_odt(ddr3_odt), // on-die termination
+            .o_debug1(o_debug1)
+        );
+
+endmodule
+

AngeloJacobo_UberDDR3/example_demo/alinx_ax7103b/ax7103_ddr3.xdc

@@ -0,0 +1,442 @@
+############## NET - IOSTANDARD #####################
+set_property CFGBVS VCCO [current_design]
+set_property CONFIG_VOLTAGE 3.3 [current_design]
+#############SPI Configurate Setting##################
+set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design] 
+set_property CONFIG_MODE SPIx4 [current_design] 
+set_property BITSTREAM.CONFIG.CONFIGRATE 50 [current_design] 
+############## clock define###########################
+create_clock -period 5 [get_ports sys_clk_p]
+set_property PACKAGE_PIN R4 [get_ports sys_clk_p]
+set_property IOSTANDARD DIFF_SSTL15 [get_ports sys_clk_p]
+
+set_property PACKAGE_PIN T4 [get_ports sys_clk_n]
+set_property IOSTANDARD DIFF_SSTL15 [get_ports sys_clk_n]
+##############reset key define########################
+set_property PACKAGE_PIN J21 [get_ports i_rst_n] 
+set_property IOSTANDARD LVCMOS33 [get_ports i_rst_n]
+
+
+##############LED define##########################
+set_property PACKAGE_PIN B13 [get_ports {led[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}]
+
+set_property PACKAGE_PIN C13 [get_ports {led[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}]
+
+set_property PACKAGE_PIN D14 [get_ports {led[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}]
+
+set_property PACKAGE_PIN D15 [get_ports {led[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}]
+
+
+##############UART define##########################
+set_property PACKAGE_PIN P20 [get_ports {rx}]
+set_property IOSTANDARD LVCMOS33 [get_ports {rx}]
+
+set_property PACKAGE_PIN N15 [get_ports {tx}]
+set_property IOSTANDARD LVCMOS33 [get_ports {tx}]
+
+############## NET - IOSTANDARD ##################
+
+
+# PadFunction: IO_L2P_T0_AD12P_35 
+set_property SLEW FAST [get_ports {ddr3_dq[0]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[0]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[0]}]
+set_property PACKAGE_PIN C2 [get_ports {ddr3_dq[0]}]
+
+# PadFunction: IO_L5P_T0_AD13P_35 
+set_property SLEW FAST [get_ports {ddr3_dq[1]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[1]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[1]}]
+set_property PACKAGE_PIN G1 [get_ports {ddr3_dq[1]}]
+
+# PadFunction: IO_L1N_T0_AD4N_35 
+set_property SLEW FAST [get_ports {ddr3_dq[2]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[2]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[2]}]
+set_property PACKAGE_PIN A1 [get_ports {ddr3_dq[2]}]
+
+# PadFunction: IO_L6P_T0_35 
+set_property SLEW FAST [get_ports {ddr3_dq[3]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[3]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[3]}]
+set_property PACKAGE_PIN F3 [get_ports {ddr3_dq[3]}]
+
+# PadFunction: IO_L2N_T0_AD12N_35 
+set_property SLEW FAST [get_ports {ddr3_dq[4]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[4]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[4]}]
+set_property PACKAGE_PIN B2 [get_ports {ddr3_dq[4]}]
+
+# PadFunction: IO_L5N_T0_AD13N_35 
+set_property SLEW FAST [get_ports {ddr3_dq[5]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[5]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[5]}]
+set_property PACKAGE_PIN F1 [get_ports {ddr3_dq[5]}]
+
+# PadFunction: IO_L1P_T0_AD4P_35 
+set_property SLEW FAST [get_ports {ddr3_dq[6]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[6]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[6]}]
+set_property PACKAGE_PIN B1 [get_ports {ddr3_dq[6]}]
+
+# PadFunction: IO_L4P_T0_35 
+set_property SLEW FAST [get_ports {ddr3_dq[7]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[7]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[7]}]
+set_property PACKAGE_PIN E2 [get_ports {ddr3_dq[7]}]
+
+# PadFunction: IO_L11P_T1_SRCC_35 
+set_property SLEW FAST [get_ports {ddr3_dq[8]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[8]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[8]}]
+set_property PACKAGE_PIN H3 [get_ports {ddr3_dq[8]}]
+
+# PadFunction: IO_L11N_T1_SRCC_35 
+set_property SLEW FAST [get_ports {ddr3_dq[9]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[9]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[9]}]
+set_property PACKAGE_PIN G3 [get_ports {ddr3_dq[9]}]
+
+# PadFunction: IO_L8P_T1_AD14P_35 
+set_property SLEW FAST [get_ports {ddr3_dq[10]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[10]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[10]}]
+set_property PACKAGE_PIN H2 [get_ports {ddr3_dq[10]}]
+
+# PadFunction: IO_L10N_T1_AD15N_35 
+set_property SLEW FAST [get_ports {ddr3_dq[11]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[11]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[11]}]
+set_property PACKAGE_PIN H5 [get_ports {ddr3_dq[11]}]
+
+# PadFunction: IO_L7N_T1_AD6N_35 
+set_property SLEW FAST [get_ports {ddr3_dq[12]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[12]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[12]}]
+set_property PACKAGE_PIN J1 [get_ports {ddr3_dq[12]}]
+
+# PadFunction: IO_L10P_T1_AD15P_35 
+set_property SLEW FAST [get_ports {ddr3_dq[13]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[13]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[13]}]
+set_property PACKAGE_PIN J5 [get_ports {ddr3_dq[13]}]
+
+# PadFunction: IO_L7P_T1_AD6P_35 
+set_property SLEW FAST [get_ports {ddr3_dq[14]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[14]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[14]}]
+set_property PACKAGE_PIN K1 [get_ports {ddr3_dq[14]}]
+
+# PadFunction: IO_L12P_T1_MRCC_35 
+set_property SLEW FAST [get_ports {ddr3_dq[15]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[15]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[15]}]
+set_property PACKAGE_PIN H4 [get_ports {ddr3_dq[15]}]
+
+# PadFunction: IO_L18N_T2_35 
+set_property SLEW FAST [get_ports {ddr3_dq[16]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[16]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[16]}]
+set_property PACKAGE_PIN L4 [get_ports {ddr3_dq[16]}]
+
+# PadFunction: IO_L16P_T2_35 
+set_property SLEW FAST [get_ports {ddr3_dq[17]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[17]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[17]}]
+set_property PACKAGE_PIN M3 [get_ports {ddr3_dq[17]}]
+
+# PadFunction: IO_L14P_T2_SRCC_35 
+set_property SLEW FAST [get_ports {ddr3_dq[18]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[18]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[18]}]
+set_property PACKAGE_PIN L3 [get_ports {ddr3_dq[18]}]
+
+# PadFunction: IO_L17N_T2_35 
+set_property SLEW FAST [get_ports {ddr3_dq[19]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[19]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[19]}]
+set_property PACKAGE_PIN J6 [get_ports {ddr3_dq[19]}]
+
+# PadFunction: IO_L14N_T2_SRCC_35 
+set_property SLEW FAST [get_ports {ddr3_dq[20]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[20]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[20]}]
+set_property PACKAGE_PIN K3 [get_ports {ddr3_dq[20]}]
+
+# PadFunction: IO_L17P_T2_35 
+set_property SLEW FAST [get_ports {ddr3_dq[21]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[21]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[21]}]
+set_property PACKAGE_PIN K6 [get_ports {ddr3_dq[21]}]
+
+# PadFunction: IO_L13N_T2_MRCC_35 
+set_property SLEW FAST [get_ports {ddr3_dq[22]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[22]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[22]}]
+set_property PACKAGE_PIN J4 [get_ports {ddr3_dq[22]}]
+
+# PadFunction: IO_L18P_T2_35 
+set_property SLEW FAST [get_ports {ddr3_dq[23]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[23]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[23]}]
+set_property PACKAGE_PIN L5 [get_ports {ddr3_dq[23]}]
+
+# PadFunction: IO_L20N_T3_35 
+set_property SLEW FAST [get_ports {ddr3_dq[24]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[24]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[24]}]
+set_property PACKAGE_PIN P1 [get_ports {ddr3_dq[24]}]
+
+# PadFunction: IO_L19P_T3_35 
+set_property SLEW FAST [get_ports {ddr3_dq[25]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[25]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[25]}]
+set_property PACKAGE_PIN N4 [get_ports {ddr3_dq[25]}]
+
+# PadFunction: IO_L20P_T3_35 
+set_property SLEW FAST [get_ports {ddr3_dq[26]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[26]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[26]}]
+set_property PACKAGE_PIN R1 [get_ports {ddr3_dq[26]}]
+
+# PadFunction: IO_L22N_T3_35 
+set_property SLEW FAST [get_ports {ddr3_dq[27]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[27]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[27]}]
+set_property PACKAGE_PIN N2 [get_ports {ddr3_dq[27]}]
+
+# PadFunction: IO_L23P_T3_35 
+set_property SLEW FAST [get_ports {ddr3_dq[28]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[28]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[28]}]
+set_property PACKAGE_PIN M6 [get_ports {ddr3_dq[28]}]
+
+# PadFunction: IO_L24N_T3_35 
+set_property SLEW FAST [get_ports {ddr3_dq[29]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[29]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[29]}]
+set_property PACKAGE_PIN N5 [get_ports {ddr3_dq[29]}]
+
+# PadFunction: IO_L24P_T3_35 
+set_property SLEW FAST [get_ports {ddr3_dq[30]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[30]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[30]}]
+set_property PACKAGE_PIN P6 [get_ports {ddr3_dq[30]}]
+
+# PadFunction: IO_L22P_T3_35 
+set_property SLEW FAST [get_ports {ddr3_dq[31]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[31]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[31]}]
+set_property PACKAGE_PIN P2 [get_ports {ddr3_dq[31]}]
+
+# PadFunction: IO_L6N_T0_VREF_34 
+set_property SLEW FAST [get_ports {ddr3_addr[14]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[14]}]
+set_property PACKAGE_PIN V3 [get_ports {ddr3_addr[14]}]
+
+# PadFunction: IO_L1N_T0_34 
+set_property SLEW FAST [get_ports {ddr3_addr[13]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[13]}]
+set_property PACKAGE_PIN U1 [get_ports {ddr3_addr[13]}]
+
+# PadFunction: IO_L4N_T0_34 
+set_property SLEW FAST [get_ports {ddr3_addr[12]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[12]}]
+set_property PACKAGE_PIN Y2 [get_ports {ddr3_addr[12]}]
+
+# PadFunction: IO_L4P_T0_34 
+set_property SLEW FAST [get_ports {ddr3_addr[11]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[11]}]
+set_property PACKAGE_PIN W2 [get_ports {ddr3_addr[11]}]
+
+# PadFunction: IO_L5N_T0_34 
+set_property SLEW FAST [get_ports {ddr3_addr[10]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[10]}]
+set_property PACKAGE_PIN Y1 [get_ports {ddr3_addr[10]}]
+
+# PadFunction: IO_L2P_T0_34 
+set_property SLEW FAST [get_ports {ddr3_addr[9]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[9]}]
+set_property PACKAGE_PIN U2 [get_ports {ddr3_addr[9]}]
+
+# PadFunction: IO_L2N_T0_34 
+set_property SLEW FAST [get_ports {ddr3_addr[8]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[8]}]
+set_property PACKAGE_PIN V2 [get_ports {ddr3_addr[8]}]
+
+# PadFunction: IO_L1P_T0_34 
+set_property SLEW FAST [get_ports {ddr3_addr[7]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[7]}]
+set_property PACKAGE_PIN T1 [get_ports {ddr3_addr[7]}]
+
+# PadFunction: IO_L5P_T0_34 
+set_property SLEW FAST [get_ports {ddr3_addr[6]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[6]}]
+set_property PACKAGE_PIN W1 [get_ports {ddr3_addr[6]}]
+
+# PadFunction: IO_L6P_T0_34 
+set_property SLEW FAST [get_ports {ddr3_addr[5]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[5]}]
+set_property PACKAGE_PIN U3 [get_ports {ddr3_addr[5]}]
+
+# PadFunction: IO_L7N_T1_34 
+set_property SLEW FAST [get_ports {ddr3_addr[4]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[4]}]
+set_property PACKAGE_PIN AB1 [get_ports {ddr3_addr[4]}]
+
+# PadFunction: IO_L10N_T1_34 
+set_property SLEW FAST [get_ports {ddr3_addr[3]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[3]}]
+set_property PACKAGE_PIN AB5 [get_ports {ddr3_addr[3]}]
+
+# PadFunction: IO_L10P_T1_34 
+set_property SLEW FAST [get_ports {ddr3_addr[2]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[2]}]
+set_property PACKAGE_PIN AA5 [get_ports {ddr3_addr[2]}]
+
+# PadFunction: IO_L8N_T1_34 
+set_property SLEW FAST [get_ports {ddr3_addr[1]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[1]}]
+set_property PACKAGE_PIN AB2 [get_ports {ddr3_addr[1]}]
+
+# PadFunction: IO_L11N_T1_SRCC_34 
+set_property SLEW FAST [get_ports {ddr3_addr[0]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[0]}]
+set_property PACKAGE_PIN AA4 [get_ports {ddr3_addr[0]}]
+
+# PadFunction: IO_L11P_T1_SRCC_34 
+set_property SLEW FAST [get_ports {ddr3_ba[2]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_ba[2]}]
+set_property PACKAGE_PIN Y4 [get_ports {ddr3_ba[2]}]
+
+# PadFunction: IO_L9P_T1_DQS_34 
+set_property SLEW FAST [get_ports {ddr3_ba[1]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_ba[1]}]
+set_property PACKAGE_PIN Y3 [get_ports {ddr3_ba[1]}]
+
+# PadFunction: IO_L9N_T1_DQS_34 
+set_property SLEW FAST [get_ports {ddr3_ba[0]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_ba[0]}]
+set_property PACKAGE_PIN AA3 [get_ports {ddr3_ba[0]}]
+
+# PadFunction: IO_L12P_T1_MRCC_34 
+set_property SLEW FAST [get_ports {ddr3_ras_n}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_ras_n}]
+set_property PACKAGE_PIN V4 [get_ports {ddr3_ras_n}]
+
+# PadFunction: IO_L12N_T1_MRCC_34 
+set_property SLEW FAST [get_ports {ddr3_cas_n}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_cas_n}]
+set_property PACKAGE_PIN W4 [get_ports {ddr3_cas_n}]
+
+# PadFunction: IO_L7P_T1_34 
+set_property SLEW FAST [get_ports {ddr3_we_n}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_we_n}]
+set_property PACKAGE_PIN AA1 [get_ports {ddr3_we_n}]
+
+# PadFunction: IO_L15P_T2_DQS_34 
+set_property SLEW FAST [get_ports {ddr3_reset_n}]
+set_property IOSTANDARD LVCMOS15 [get_ports {ddr3_reset_n}]
+set_property PACKAGE_PIN W6 [get_ports {ddr3_reset_n}]
+
+# PadFunction: IO_L14P_T2_SRCC_34 
+set_property SLEW FAST [get_ports {ddr3_cke}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_cke}]
+set_property PACKAGE_PIN T5 [get_ports {ddr3_cke}]
+
+# PadFunction: IO_L14N_T2_SRCC_34 
+set_property SLEW FAST [get_ports {ddr3_odt}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_odt}]
+set_property PACKAGE_PIN U5 [get_ports {ddr3_odt}]
+
+# PadFunction: IO_L8P_T1_34 
+set_property SLEW FAST [get_ports {ddr3_cs_n}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_cs_n}]
+set_property PACKAGE_PIN AB3 [get_ports {ddr3_cs_n}]
+
+# PadFunction: IO_L4N_T0_35 
+set_property SLEW FAST [get_ports {ddr3_dm[0]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[0]}]
+set_property PACKAGE_PIN D2 [get_ports {ddr3_dm[0]}]
+
+# PadFunction: IO_L8N_T1_AD14N_35 
+set_property SLEW FAST [get_ports {ddr3_dm[1]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[1]}]
+set_property PACKAGE_PIN G2 [get_ports {ddr3_dm[1]}]
+
+# PadFunction: IO_L16N_T2_35 
+set_property SLEW FAST [get_ports {ddr3_dm[2]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[2]}]
+set_property PACKAGE_PIN M2 [get_ports {ddr3_dm[2]}]
+
+# PadFunction: IO_L23N_T3_35 
+set_property SLEW FAST [get_ports {ddr3_dm[3]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[3]}]
+set_property PACKAGE_PIN M5 [get_ports {ddr3_dm[3]}]
+
+# PadFunction: IO_L3P_T0_DQS_AD5P_35 
+set_property SLEW FAST [get_ports {ddr3_dqs_p[0]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dqs_p[0]}]
+set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_p[0]}]
+set_property PACKAGE_PIN E1 [get_ports {ddr3_dqs_p[0]}]
+
+# PadFunction: IO_L3N_T0_DQS_AD5N_35 
+set_property SLEW FAST [get_ports {ddr3_dqs_n[0]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dqs_n[0]}]
+set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_n[0]}]
+set_property PACKAGE_PIN D1 [get_ports {ddr3_dqs_n[0]}]
+
+# PadFunction: IO_L9P_T1_DQS_AD7P_35 
+set_property SLEW FAST [get_ports {ddr3_dqs_p[1]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dqs_p[1]}]
+set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_p[1]}]
+set_property PACKAGE_PIN K2 [get_ports {ddr3_dqs_p[1]}]
+
+# PadFunction: IO_L9N_T1_DQS_AD7N_35 
+set_property SLEW FAST [get_ports {ddr3_dqs_n[1]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dqs_n[1]}]
+set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_n[1]}]
+set_property PACKAGE_PIN J2 [get_ports {ddr3_dqs_n[1]}]
+
+# PadFunction: IO_L15P_T2_DQS_35 
+set_property SLEW FAST [get_ports {ddr3_dqs_p[2]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dqs_p[2]}]
+set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_p[2]}]
+set_property PACKAGE_PIN M1 [get_ports {ddr3_dqs_p[2]}]
+
+# PadFunction: IO_L15N_T2_DQS_35 
+set_property SLEW FAST [get_ports {ddr3_dqs_n[2]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dqs_n[2]}]
+set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_n[2]}]
+set_property PACKAGE_PIN L1 [get_ports {ddr3_dqs_n[2]}]
+
+# PadFunction: IO_L21P_T3_DQS_35 
+set_property SLEW FAST [get_ports {ddr3_dqs_p[3]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dqs_p[3]}]
+set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_p[3]}]
+set_property PACKAGE_PIN P5 [get_ports {ddr3_dqs_p[3]}]
+
+# PadFunction: IO_L21N_T3_DQS_35 
+set_property SLEW FAST [get_ports {ddr3_dqs_n[3]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dqs_n[3]}]
+set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_n[3]}]
+set_property PACKAGE_PIN P4 [get_ports {ddr3_dqs_n[3]}]
+
+# PadFunction: IO_L3P_T0_DQS_34 
+set_property SLEW FAST [get_ports {ddr3_ck_p}]
+set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_ck_p}]
+set_property PACKAGE_PIN R3 [get_ports {ddr3_ck_p}]
+
+# PadFunction: IO_L3N_T0_DQS_34 
+set_property SLEW FAST [get_ports {ddr3_ck_n}]
+set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_ck_n}]
+set_property PACKAGE_PIN R2 [get_ports {ddr3_ck_n}]
+
+
+
+
+

AngeloJacobo_UberDDR3/example_demo/alinx_ax7103b/caas.conf

@@ -0,0 +1,11 @@
+[project]
+Backend = openxc7
+Part = xc7a100tfgg484-2
+Top = ax7103_ddr3
+Constraint = ax7103_ddr3.xdc
+Sources = *.v
+
+[caas]
+Server = https://caas.symbioticeda.com:18888/
+
+

AngeloJacobo_UberDDR3/example_demo/alinx_ax7103b/clk_wiz.v

@@ -0,0 +1,66 @@
+`timescale 1ps/1ps
+
+module clk_wiz
+ (
+  input wire         clk_in1,
+  output wire        clk_out1,
+  output wire        clk_out2,
+  output wire        clk_out3,
+  output wire        clk_out4,
+  input wire         reset,
+  output wire        locked
+ );
+  wire        clk_out1_clk_wiz_0;
+  wire        clk_out2_clk_wiz_0;
+  wire        clk_out3_clk_wiz_0;
+  wire        clk_out4_clk_wiz_0;
+
+  wire clkfbout;
+
+  PLLE2_ADV
+  #(.BANDWIDTH            ("OPTIMIZED"),
+    .COMPENSATION         ("INTERNAL"),
+    .STARTUP_WAIT         ("FALSE"),
+    .DIVCLK_DIVIDE        (1),
+    .CLKFBOUT_MULT        (5), // 200 MHz * 5 = 1000 MHz
+    .CLKFBOUT_PHASE       (0.000),
+    .CLKOUT0_DIVIDE       (12), // 1000 MHz / 12 = 83.333 MHz
+    .CLKOUT0_PHASE        (0.000),
+    .CLKOUT0_DUTY_CYCLE   (0.500),
+    .CLKOUT1_DIVIDE       (3), // 1000 MHz / 3 = 333.333 MHz
+    .CLKOUT1_PHASE        (0.000),
+    .CLKOUT1_DUTY_CYCLE   (0.500),
+    .CLKOUT2_DIVIDE       (5), // 1000 MHz / 5 = 200 MHz
+    .CLKOUT2_PHASE        (0.000),
+    .CLKOUT2_DUTY_CYCLE   (0.500),
+    .CLKOUT3_DIVIDE       (3), // 1000 MHz / 3 = 333.333 MHz
+    .CLKOUT3_PHASE        (90),
+    .CLKOUT3_DUTY_CYCLE   (0.500),
+    .CLKIN1_PERIOD        (5.000) // 200 MHz input
+  )
+  plle2_adv_inst
+   (
+    .CLKFBOUT            (clkfbout),
+    .CLKOUT0             (clk_out1_clk_wiz_0),
+    .CLKOUT1             (clk_out2_clk_wiz_0),
+    .CLKOUT2             (clk_out3_clk_wiz_0),
+    .CLKOUT3             (clk_out4_clk_wiz_0),
+    .CLKFBIN             (clkfbout),
+	.CLKIN1              (clk_in1),
+    .LOCKED              (locked),
+    .RST                 (reset)
+  );
+  BUFG clkout1_buf
+   (.O   (clk_out1),
+    .I   (clk_out1_clk_wiz_0));
+  BUFG clkout2_buf
+   (.O   (clk_out2),
+    .I   (clk_out2_clk_wiz_0));
+  BUFG clkout3_buf
+   (.O   (clk_out3),
+    .I   (clk_out3_clk_wiz_0));
+  BUFG clkout4_buf
+   (.O   (clk_out4),
+    .I   (clk_out4_clk_wiz_0));
+
+endmodule

AngeloJacobo_UberDDR3/example_demo/alinx_ax7103b/ddr3_phy.v

@@ -0,0 +1,1462 @@
+////////////////////////////////////////////////////////////////////////////////
+//
+// Filename: ddr3_phy.v
+// Project: UberDDR3 - An Open Source DDR3 Controller
+//
+// Purpose: PHY component for the DDR3 controller. Handles the primitives such
+// as IOSERDES, IODELAY, and IOBUF. These generates the signals connected to 
+// the DDR3 RAM.
+//
+// Engineer: Angelo C. Jacobo
+//
+////////////////////////////////////////////////////////////////////////////////
+//
+// Copyright (C) 2023-2025  Angelo Jacobo
+// 
+//     This program is free software: you can redistribute it and/or modify
+//     it under the terms of the GNU General Public License as published by
+//     the Free Software Foundation, either version 3 of the License, or
+//     (at your option) any later version.
+// 
+//     This program is distributed in the hope that it will be useful,
+//     but WITHOUT ANY WARRANTY; without even the implied warranty of
+//     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//     GNU General Public License for more details.
+// 
+//     You should have received a copy of the GNU General Public License
+//     along with this program.  If not, see <https://www.gnu.org/licenses/>.
+//
+////////////////////////////////////////////////////////////////////////////////
+
+`default_nettype none
+`timescale 1ps / 1ps
+//`define DEBUG_DQS // uncomment to route the raw DQS to output port for debugging
+
+module ddr3_phy #(
+    parameter     CONTROLLER_CLK_PERIOD = 10_000, //ps, clock period of the controller interface
+                  DDR3_CLK_PERIOD = 2_500, //ps, clock period of the DDR3 RAM device (must be 1/4 of the CONTROLLER_CLK_PERIOD) 
+                  ROW_BITS = 14,   //width of row address
+                  BA_BITS = 3,
+                  DQ_BITS = 8,
+                  LANES = 8,
+                  DUAL_RANK_DIMM = 0, // enable dual rank DIMM (1 =  enable, 0 = disable)
+    parameter[0:0] ODELAY_SUPPORTED = 1, //set to 1 when ODELAYE2 is supported
+                   USE_IO_TERMINATION = 0, //use IOBUF_DCIEN and IOBUFDS_DCIEN when 1
+                   NO_IOSERDES_LOOPBACK = 1, // don't use IOSERDES loopback for bitslip training
+              // The next parameters act more like a localparam (since user does not have to set this manually) but was added here to simplify port declaration
+    parameter serdes_ratio = 4, // this controller is fixed as a 4:1 memory controller (CONTROLLER_CLK_PERIOD/DDR3_CLK_PERIOD = 4)
+              wb_data_bits = DQ_BITS*LANES*serdes_ratio*2,
+              wb_sel_bits = wb_data_bits / 8,
+              //4 is the width of a single ddr3 command {cs_n, ras_n, cas_n, we_n} plus 3 (ck_en, odt, reset_n) plus bank bits plus row bits
+              cmd_len = 4 + 3 + BA_BITS + ROW_BITS + 2*DUAL_RANK_DIMM
+    )(
+        input wire i_controller_clk, i_ddr3_clk, i_ref_clk,
+        input wire i_ddr3_clk_90, //required only when ODELAY_SUPPORTED is zero
+        input wire i_rst_n,
+        // Controller Interface
+        input wire i_controller_reset,
+        input wire[cmd_len*serdes_ratio-1:0] i_controller_cmd,
+        input wire i_controller_dqs_tri_control, i_controller_dq_tri_control,
+        input wire i_controller_toggle_dqs,
+        input wire[wb_data_bits-1:0] i_controller_data,
+        input wire[wb_sel_bits-1:0] i_controller_dm,
+        input wire[4:0] i_controller_odelay_data_cntvaluein,i_controller_odelay_dqs_cntvaluein,
+        input wire[4:0] i_controller_idelay_data_cntvaluein,i_controller_idelay_dqs_cntvaluein,
+        input wire[LANES-1:0] i_controller_odelay_data_ld, i_controller_odelay_dqs_ld,
+        input wire[LANES-1:0] i_controller_idelay_data_ld, i_controller_idelay_dqs_ld,
+        input wire[LANES-1:0] i_controller_bitslip,
+        input wire i_controller_write_leveling_calib,
+        output wire[DQ_BITS*LANES*8-1:0] o_controller_iserdes_data,
+        output wire[LANES*8-1:0] o_controller_iserdes_dqs,
+        output wire[LANES*8-1:0] o_controller_iserdes_bitslip_reference,
+        output wire o_controller_idelayctrl_rdy,
+        // DDR3 I/O Interface
+        output wire[DUAL_RANK_DIMM:0] o_ddr3_clk_p,o_ddr3_clk_n,
+        output wire o_ddr3_reset_n,
+        output wire[DUAL_RANK_DIMM:0] o_ddr3_cke, // CKE
+        output wire[DUAL_RANK_DIMM:0] o_ddr3_cs_n, // chip select signal
+        output wire o_ddr3_ras_n, // RAS#
+        output wire o_ddr3_cas_n, // CAS#
+        output wire o_ddr3_we_n, // WE#
+        output wire[ROW_BITS-1:0] o_ddr3_addr,
+        output wire[BA_BITS-1:0] o_ddr3_ba_addr,
+        inout wire[(DQ_BITS*LANES)-1:0] io_ddr3_dq,
+        inout wire[(DQ_BITS*LANES)/8-1:0] io_ddr3_dqs, io_ddr3_dqs_n,
+        output wire[LANES-1:0] o_ddr3_dm,
+        output wire[DUAL_RANK_DIMM:0] o_ddr3_odt, // on-die termination
+        // DEBUG PHY
+        output wire[(DQ_BITS*LANES)/8-1:0] o_ddr3_debug_read_dqs_p,
+        output wire[(DQ_BITS*LANES)/8-1:0] o_ddr3_debug_read_dqs_n
+    );
+
+    // cmd bit assignment
+    localparam CMD_CS_N_2 = cmd_len - 1,
+                CMD_CS_N =  DUAL_RANK_DIMM[0]? cmd_len - 2 : cmd_len - 1,
+                CMD_RAS_N = DUAL_RANK_DIMM[0]? cmd_len - 3 : cmd_len - 2,
+                CMD_CAS_N = DUAL_RANK_DIMM[0]? cmd_len - 4 : cmd_len - 3,
+                CMD_WE_N =  DUAL_RANK_DIMM[0]? cmd_len - 5 : cmd_len - 4,
+                CMD_ODT =   DUAL_RANK_DIMM[0]? cmd_len - 6 : cmd_len - 5,
+                CMD_CKE_2 = DUAL_RANK_DIMM[0]? cmd_len - 7 : cmd_len - 6,
+                CMD_CKE =   DUAL_RANK_DIMM[0]? cmd_len - 8 : cmd_len - 6,
+                CMD_RESET_N = DUAL_RANK_DIMM[0]? cmd_len - 9 : cmd_len - 7,
+                CMD_BANK_START = BA_BITS + ROW_BITS - 1,
+                CMD_ADDRESS_START = ROW_BITS - 1;
+    localparam SYNC_RESET_DELAY = $rtoi($ceil(52_000/CONTROLLER_CLK_PERIOD)); //52_000 ps of reset pulse width required for IDELAYCTRL 
+    //cmd needs to be center-aligned to the positive edge of the 
+    //ddr3_clk. This means cmd needs to be delayed by half the ddr3
+    //clk period. Subtract by 600ps to include the IODELAY insertion
+    //delay. Divide by a delay resolution of 78.125ps per tap to get 
+    //the needed tap value.
+    localparam CMD_ODELAY_TAP = ((DDR3_CLK_PERIOD/2) - 600)/78.125;
+
+    // Data does not have to be delayed (DQS is the on that has to be
+    // delayed and center-aligned to the center eye of data)
+    localparam DATA_ODELAY_TAP = 0; 
+
+    //DQS needs to be edge-aligned to the center eye of the data. 
+    //This means DQS needs to be delayed by a quarter of the ddr3
+    //clk period relative to the data. Subtract by 600ps to include
+    //the IODELAY insertion delay. Divide by a delay resolution of 
+    //78.125ps per tap to get the needed tap value. Then add the tap
+    //value used in data to have the delay relative to the data.
+    localparam DQS_ODELAY_TAP = ((DDR3_CLK_PERIOD/4))/78.125 + DATA_ODELAY_TAP;
+    
+    //Incoming DQS should be 90 degree delayed relative to incoming data
+    localparam DATA_IDELAY_TAP = 0; //600ps delay
+    localparam DQS_IDELAY_TAP = ((DDR3_CLK_PERIOD/4))/78.125 + DATA_IDELAY_TAP;
+    
+    genvar gen_index;
+    wire[cmd_len-1:0] oserdes_cmd, //serialized(4:1) i_controller_cmd_slot_x 
+                      cmd;//delayed oserdes_cmd
+    wire[(DQ_BITS*LANES)-1:0] oserdes_data, odelay_data, idelay_data, read_dq;
+    wire[LANES-1:0] oserdes_dm, odelay_dm;
+    wire[LANES-1:0] odelay_dqs, read_dqs, idelay_dqs;
+    wire[DQ_BITS*LANES-1:0] oserdes_dq_tri_control;
+    wire[LANES-1:0] oserdes_dqs;
+    wire[LANES-1:0] oserdes_dqs_tri_control;
+    wire[LANES-1:0] oserdes_bitslip_reference;
+    reg[$clog2(SYNC_RESET_DELAY):0] delay_before_release_reset;
+    reg sync_rst = 0;
+    wire ddr3_clk;
+    reg toggle_dqs_q; //past value of i_controller_toggle_dqs
+    wire ddr3_clk_delayed;
+    wire idelayctrl_rdy;
+    wire dci_locked;
+    reg[LANES*8-1:0] o_controller_iserdes_bitslip_reference_reg;
+    reg[LANES - 1 : 0] shift_bitslip_index;
+    
+    // initial value of bitslip reference
+    initial begin
+        o_controller_iserdes_bitslip_reference_reg = {LANES{8'b0001_1110}};
+        shift_bitslip_index = 0;
+    end
+                
+    assign o_controller_idelayctrl_rdy = idelayctrl_rdy && dci_locked;
+    
+`ifdef DEBUG_DQS
+    assign o_ddr3_debug_read_dqs_p = io_ddr3_dqs;
+    assign o_ddr3_debug_read_dqs_n = io_ddr3_dqs_n;
+`else
+    assign o_ddr3_debug_read_dqs_p = 0;
+    assign o_ddr3_debug_read_dqs_n = 0;
+`endif
+
+    //synchronous reset
+    always @(posedge i_controller_clk) begin
+        if(!i_rst_n || i_controller_reset) begin
+            sync_rst <= 1'b1;
+            delay_before_release_reset <= SYNC_RESET_DELAY[$clog2(SYNC_RESET_DELAY):0];
+            toggle_dqs_q <= 0;
+        end
+        else begin
+            delay_before_release_reset <= (delay_before_release_reset == 0)? 0: delay_before_release_reset - 1;
+            sync_rst <= !(delay_before_release_reset == 0);
+            toggle_dqs_q <= i_controller_toggle_dqs;
+        end
+    end
+
+    //PHY cmd 
+    generate
+        for(gen_index = 0; gen_index < cmd_len; gen_index = gen_index + 1) begin
+            // OSERDESE2: Output SERial/DESerializer with bitslip
+            //7 Series
+            // Xilinx HDL Libraries Guide, version 13.4
+            `ifndef SIM_MODEL
+                OSERDESE2 #(
+            `else 
+                OSERDESE2_model #(
+            `endif
+                .DATA_RATE_OQ("SDR"), // DDR, SDR
+                .DATA_RATE_TQ("SDR"), // DDR, SDR
+                .DATA_WIDTH(4), // Parallel data width (2-8,10,14)
+                .INIT_OQ(1'b0), // Initial value of OQ output (1'b0,1'b1)
+                .TRISTATE_WIDTH(1)
+            )
+            OSERDESE2_cmd(
+                .OFB(), // 1-bit output: Feedback path for data
+                .OQ(oserdes_cmd[gen_index]), // 1-bit output: Data path output
+                .CLK(i_ddr3_clk), // 1-bit input: High speed clock
+                .CLKDIV(i_controller_clk), // 1-bit input: Divided clock
+                // D1 - D8: 1-bit (each) input: Parallel data inputs (1-bit each)
+                .D1(i_controller_cmd[cmd_len*0 + gen_index]),
+                .D2(i_controller_cmd[cmd_len*1 + gen_index]),
+                .D3(i_controller_cmd[cmd_len*2 + gen_index]),
+                .D4(i_controller_cmd[cmd_len*3 + gen_index]),
+                .OCE(1'b1), // 1-bit input: Output data clock enable
+                .RST(sync_rst), // 1-bit input: Reset
+                // unused signals but were added here to make vivado happy
+                .SHIFTOUT1(), // SHIFTOUT1 / SHIFTOUT2: 1-bit (each) output: Data output expansion (1-bit each)
+                .SHIFTOUT2(),
+                .TBYTEOUT(), // 1-bit output: Byte group tristate
+                .TFB(), // 1-bit output: 3-state control
+                .TQ(), // 1-bit output: 3-state control
+                .D5(),
+                .D6(),
+                .D7(),
+                .D8(),
+                // SHIFTIN1 / SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each)
+                .SHIFTIN1(0),
+                .SHIFTIN2(0),
+                // T1 - T4: 1-bit (each) input: Parallel 3-state inputs
+                .T1(0),
+                .T2(0),
+                .T3(0),
+                .T4(0),
+                .TBYTEIN(0),
+                // 1-bit input: Byte group tristate
+                .TCE(0)
+                // 1-bit input: 3-state clock enable
+            );
+            // End of OSERDESE2_inst instantiation
+      
+        end
+
+        if(DUAL_RANK_DIMM) begin // if dual rank enabled, odt_2 and odt_1 will be generated separately
+            // OSERDESE2: Output SERial/DESerializer with bitslip
+            //7 Series
+            // Xilinx HDL Libraries Guide, version 13.4
+            `ifndef SIM_MODEL
+                OSERDESE2 #(
+            `else 
+                OSERDESE2_model #(
+            `endif
+                .DATA_RATE_OQ("SDR"), // DDR, SDR
+                .DATA_RATE_TQ("SDR"), // DDR, SDR
+                .DATA_WIDTH(4), // Parallel data width (2-8,10,14)
+                .INIT_OQ(1'b0), // Initial value of OQ output (1'b0,1'b1)
+                .TRISTATE_WIDTH(1)
+            )
+            OSERDESE2_cmd(
+                .OFB(), // 1-bit output: Feedback path for data
+                .OQ(o_ddr3_odt[1]), // 1-bit output: Data path output
+                .CLK(i_ddr3_clk), // 1-bit input: High speed clock
+                .CLKDIV(i_controller_clk), // 1-bit input: Divided clock
+                // D1 - D8: 1-bit (each) input: Parallel data inputs (1-bit each)
+                .D1(i_controller_cmd[cmd_len*0 + CMD_ODT]),
+                .D2(i_controller_cmd[cmd_len*1 + CMD_ODT]),
+                .D3(i_controller_cmd[cmd_len*2 + CMD_ODT]),
+                .D4(i_controller_cmd[cmd_len*3 + CMD_ODT]),
+                .OCE(1'b1), // 1-bit input: Output data clock enable
+                .RST(sync_rst), // 1-bit input: Reset
+                // unused signals but were added here to make vivado happy
+                .SHIFTOUT1(), // SHIFTOUT1 / SHIFTOUT2: 1-bit (each) output: Data output expansion (1-bit each)
+                .SHIFTOUT2(),
+                .TBYTEOUT(), // 1-bit output: Byte group tristate
+                .TFB(), // 1-bit output: 3-state control
+                .TQ(), // 1-bit output: 3-state control
+                .D5(),
+                .D6(),
+                .D7(),
+                .D8(),
+                // SHIFTIN1 / SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each)
+                .SHIFTIN1(0),
+                .SHIFTIN2(0),
+                // T1 - T4: 1-bit (each) input: Parallel 3-state inputs
+                .T1(0),
+                .T2(0),
+                .T3(0),
+                .T4(0),
+                .TBYTEIN(0),
+                // 1-bit input: Byte group tristate
+                .TCE(0)
+                // 1-bit input: 3-state clock enable
+            );
+            // End of OSERDESE2_inst instantiation
+        end
+    endgenerate 
+
+    // cs[1] when DUAL_RANK_DIMM enabled
+    generate    
+        if(DUAL_RANK_DIMM) begin
+            assign o_ddr3_cs_n[1] = oserdes_cmd[CMD_CS_N_2];
+            assign o_ddr3_cs_n[0] = oserdes_cmd[CMD_CS_N];
+            assign o_ddr3_cke[1] = oserdes_cmd[CMD_CKE_2];
+            assign o_ddr3_cke[0] = oserdes_cmd[CMD_CKE];
+            assign o_ddr3_odt[0] = oserdes_cmd[CMD_ODT];
+            // o_ddr3_odt[1] will be generated directly by a separate OSERDES
+            // if odt[1] and odt[0] uses same output from oserdes, one of them will be unroutable
+        end
+        else begin
+            assign o_ddr3_cs_n = oserdes_cmd[CMD_CS_N];
+            assign o_ddr3_cke = oserdes_cmd[CMD_CKE];
+            assign o_ddr3_odt = oserdes_cmd[CMD_ODT];
+        end
+    endgenerate
+    assign o_ddr3_ras_n = oserdes_cmd[CMD_RAS_N],
+           o_ddr3_cas_n = oserdes_cmd[CMD_CAS_N],
+           o_ddr3_we_n = oserdes_cmd[CMD_WE_N],
+           o_ddr3_reset_n = oserdes_cmd[CMD_RESET_N],
+           o_ddr3_ba_addr = oserdes_cmd[CMD_BANK_START:CMD_ADDRESS_START+1],
+           o_ddr3_addr = oserdes_cmd[CMD_ADDRESS_START:0];
+    
+    if(ODELAY_SUPPORTED) begin
+        // OSERDESE2: Output SERial/DESerializer with bitslip
+        //7 Series
+        // Xilinx HDL Libraries Guide, version 13.4
+        `ifndef SIM_MODEL
+            OSERDESE2 #(
+        `else 
+            OSERDESE2_model #(
+        `endif
+            .DATA_RATE_OQ("DDR"), // DDR, SDR
+            .DATA_RATE_TQ("SDR"), // DDR, SDR
+            .DATA_WIDTH(8), // Parallel data width (2-8,10,14)
+            .INIT_OQ(1'b0), // Initial value of OQ output (1'b0,1'b1)
+            .TRISTATE_WIDTH(1)
+        )
+        OSERDESE2_clk(
+            .OFB(ddr3_clk), // 1-bit output: Feedback path for data
+            .OQ(), // 1-bit output: Data path output
+            .CLK(i_ddr3_clk), // 1-bit input: High speed clock
+            .CLKDIV(i_controller_clk), // 1-bit input: Divided clock
+            // D1 - D8: 1-bit (each) input: Parallel data inputs (1-bit each)
+            .D1(1'b1),
+            .D2(1'b0),
+            .D3(1'b1),
+            .D4(1'b0),
+            .D5(1'b1),
+            .D6(1'b0),
+            .D7(1'b1),
+            .D8(1'b0),
+            .OCE(1'b1), // 1-bit input: Output data clock enable
+            .RST(sync_rst), // 1-bit input: Reset
+             // unused signals but were added here to make vivado happy
+            .SHIFTOUT1(), // SHIFTOUT1 / SHIFTOUT2: 1-bit (each) output: Data output expansion (1-bit each)
+            .SHIFTOUT2(),
+            .TBYTEOUT(), // 1-bit output: Byte group tristate
+            .TFB(), // 1-bit output: 3-state control
+            .TQ(), // 1-bit output: 3-state control
+            // SHIFTIN1 / SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each)
+            .SHIFTIN1(0),
+            .SHIFTIN2(0),
+            // T1 - T4: 1-bit (each) input: Parallel 3-state inputs
+            .T1(0),
+            .T2(0),
+            .T3(0),
+            .T4(0),
+            .TBYTEIN(0),
+            // 1-bit input: Byte group tristate
+            .TCE(0)
+            // 1-bit input: 3-state clock enable
+        );
+        // End of OSERDESE2_inst instantiation
+
+            //Delay the DQ
+            // Delay resolution: 1/(32 x 2 x F REF ) = 78.125ps
+            (* IODELAY_GROUP="DDR3-GROUP" *)
+            `ifndef SIM_MODEL
+                ODELAYE2 #(
+            `else 
+                ODELAYE2_model #(
+            `endif
+                .DELAY_SRC("ODATAIN"), // Delay input (ODATAIN, CLKIN)
+                .HIGH_PERFORMANCE_MODE("TRUE"), // Reduced jitter to 5ps ("TRUE"), Reduced power but high jitter 9ns ("FALSE")
+                .ODELAY_TYPE("FIXED"), // FIXED, VARIABLE, VAR_LOAD, VAR_LOAD_PIPE
+                .ODELAY_VALUE(CMD_ODELAY_TAP), // Output delay tap setting (0-31)
+                .REFCLK_FREQUENCY(200.0), // IDELAYCTRL clock input frequency in MHz (190.0-210.0).
+                .SIGNAL_PATTERN("DATA") // DATA, CLOCK input signal
+            )
+            ODELAYE2_clk (
+                .CNTVALUEOUT(), // 5-bit output: Counter value output
+                .DATAOUT(ddr3_clk_delayed), // 1-bit output: Delayed data/clock output
+                .C(i_controller_clk), // 1-bit input: Clock input, when using OSERDESE2, C is connected to CLKDIV
+                .CE(1'b0), // 1-bit input: Active high enable increment/decrement input
+                .CINVCTRL(1'b0), // 1-bit input: Dynamic clock inversion input
+                .CLKIN(1'b0), // 1-bit input: Clock delay input
+                .CNTVALUEIN(5'd0), // 5-bit input: Counter value input
+                .INC(1'b0), // 1-bit input: Increment / Decrement tap delay input
+                .LD(1'b0), // 1-bit input: Loads ODELAY_VALUE tap delay in VARIABLE mode, in VAR_LOAD or
+                            // VAR_LOAD_PIPE mode, loads the value of CNTVALUEIN
+                .LDPIPEEN(1'b0), // 1-bit input: Enables the pipeline register to load data
+                .ODATAIN(ddr3_clk), // 1-bit input: Output delay data input
+                .REGRST(1'b0) // 1-bit input: Active-high reset tap-delay input
+            );
+        // if dual rank enabled, then there will be two clk
+        if(DUAL_RANK_DIMM) begin
+            // OBUFDS: Differential Output Buffer
+            // 7 Series
+            // Xilinx HDL Libraries Guide, version 13.4
+            `ifndef SIM_MODEL
+                OBUFDS OBUFDS0_inst (
+            `else 
+                OBUFDS_model OBUFDS0_inst (
+            `endif
+                .O(o_ddr3_clk_p[0]), // Diff_p output (connect directly to top-level port)
+                .OB(o_ddr3_clk_n[0]), // Diff_n output (connect directly to top-level port)
+                .I(ddr3_clk_delayed) // Buffer input
+            );
+            `ifndef SIM_MODEL
+                OBUFDS OBUFDS1_inst (
+            `else 
+                OBUFDS_model OBUFDS1_inst (
+            `endif
+                .O(o_ddr3_clk_p[1]), // Diff_p output (connect directly to top-level port)
+                .OB(o_ddr3_clk_n[1]), // Diff_n output (connect directly to top-level port)
+                .I(ddr3_clk_delayed) // Buffer input
+            );
+            // End of OBUFDS_inst instantiation
+        end
+        else begin
+            // OBUFDS: Differential Output Buffer
+            // 7 Series
+            // Xilinx HDL Libraries Guide, version 13.4
+            `ifndef SIM_MODEL
+                OBUFDS OBUFDS_inst (
+            `else 
+                OBUFDS_model OBUFDS_inst (
+            `endif
+                .O(o_ddr3_clk_p), // Diff_p output (connect directly to top-level port)
+                .OB(o_ddr3_clk_n), // Diff_n output (connect directly to top-level port)
+                .I(ddr3_clk_delayed) // Buffer input
+            );
+            // End of OBUFDS_inst instantiation
+        end
+    end
+    else begin //ODELAY is not supported
+
+                // if dual rank enabled, then there will be two clk
+        if(DUAL_RANK_DIMM) begin
+            // OBUFDS: Differential Output Buffer
+            // 7 Series
+            // Xilinx HDL Libraries Guide, version 13.4
+            `ifndef SIM_MODEL
+                OBUFDS OBUFDS0_inst (
+            `else 
+                OBUFDS_model OBUFDS0_inst (
+            `endif
+                .O(o_ddr3_clk_p[1]), // Diff_p output (connect directly to top-level port)
+                .OB(o_ddr3_clk_n[1]), // Diff_n output (connect directly to top-level port)
+                .I(!i_ddr3_clk) // Buffer input
+            );
+            `ifndef SIM_MODEL
+                OBUFDS OBUFDS1_inst (
+            `else 
+                OBUFDS_model OBUFDS1_inst (
+            `endif
+                .O(o_ddr3_clk_p[0]), // Diff_p output (connect directly to top-level port)
+                .OB(o_ddr3_clk_n[0]), // Diff_n output (connect directly to top-level port)
+                .I(!i_ddr3_clk) // Buffer input
+            );
+            // End of OBUFDS_inst instantiation
+        end
+        else begin
+            // OBUFDS: Differential Output Buffer
+            // 7 Series
+            // Xilinx HDL Libraries Guide, version 13.4
+            `ifndef SIM_MODEL
+                OBUFDS OBUFDS_inst (
+            `else 
+                OBUFDS_model OBUFDS_inst (
+            `endif
+                .O(o_ddr3_clk_p), // Diff_p output (connect directly to top-level port)
+                .OB(o_ddr3_clk_n), // Diff_n output (connect directly to top-level port)
+                .I(!i_ddr3_clk) // Buffer input
+            );
+        end
+    end
+    
+    
+    // PHY data and dm
+    generate
+        // data: oserdes -> odelay -> iobuf
+        for(gen_index = 0; gen_index < (DQ_BITS*LANES); gen_index = gen_index + 1) begin
+            
+            if (ODELAY_SUPPORTED) begin
+                // OSERDESE2: Output SERial/DESerializer with bitslip
+                //7 Series
+                // Xilinx HDL Libraries Guide, version 13.4
+                `ifndef SIM_MODEL
+                    OSERDESE2 #(
+                `else 
+                    OSERDESE2_model #(
+                `endif
+                    .DATA_RATE_OQ("DDR"), // DDR, SDR
+                    .DATA_RATE_TQ("BUF"), // DDR, SDR
+                    .DATA_WIDTH(8), // Parallel data width (2-8,10,14)
+                    .INIT_OQ(1'b0), // Initial value of OQ output (1'b0,1'b1)
+                    .TRISTATE_WIDTH(1)
+                )
+                OSERDESE2_data(
+                    .OFB(oserdes_data[gen_index]), // 1-bit output: Feedback path for data
+                    .OQ(), // 1-bit output: Data path output
+                    .TQ(oserdes_dq_tri_control[gen_index]),
+                    .CLK(i_ddr3_clk), // 1-bit input: High speed clock
+                    .CLKDIV(i_controller_clk), // 1-bit input: Divided clock
+                    // D1 - D8: 1-bit (each) input: Parallel data inputs (1-bit each)
+                    .D1(i_controller_data[gen_index + (DQ_BITS*LANES)*0]),
+                    .D2(i_controller_data[gen_index + (DQ_BITS*LANES)*1]),
+                    .D3(i_controller_data[gen_index + (DQ_BITS*LANES)*2]),
+                    .D4(i_controller_data[gen_index + (DQ_BITS*LANES)*3]),
+                    .D5(i_controller_data[gen_index + (DQ_BITS*LANES)*4]),
+                    .D6(i_controller_data[gen_index + (DQ_BITS*LANES)*5]),
+                    .D7(i_controller_data[gen_index + (DQ_BITS*LANES)*6]),
+                    .D8(i_controller_data[gen_index + (DQ_BITS*LANES)*7]),
+                    .T1(i_controller_dq_tri_control),
+                    .TCE(1'b1),
+                    .OCE(1'b1), // 1-bit input: Output data clock enable
+                    .RST(sync_rst), // 1-bit input: Reset
+                    // unused signals but were added here to make vivado happy
+                    .SHIFTOUT1(), // SHIFTOUT1 / SHIFTOUT2: 1-bit (each) output: Data output expansion (1-bit each)
+                    .SHIFTOUT2(),
+                    .TBYTEOUT(), // 1-bit output: Byte group tristate
+                    .TFB(), // 1-bit output: 3-state control
+                    // SHIFTIN1 / SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each)
+                    .SHIFTIN1(0),
+                    .SHIFTIN2(0),
+                    // T1 - T4: 1-bit (each) input: Parallel 3-state inputs
+                    .T2(0),
+                    .T3(0),
+                    .T4(0),
+                    .TBYTEIN(0)
+                    // 1-bit input: Byte group tristate
+                );
+                // End of OSERDESE2_inst instantiation
+            
+                // ODELAYE2: Output Fixed or Variable Delay Element
+                // 7 Series
+                // Xilinx HDL Libraries Guide, version 13.4
+                //odelay adds an insertion delay of 600ps to the actual delay setting: https://support.xilinx.com/s/article/42133?language=en_US
+                //Delay the DQ
+                // Delay resolution: 1/(32 x 2 x F REF ) = 78.125ps
+                (* IODELAY_GROUP="DDR3-GROUP" *)
+                `ifndef SIM_MODEL
+                    ODELAYE2 #(
+                `else 
+                    ODELAYE2_model #(
+                `endif
+                    .DELAY_SRC("ODATAIN"), // Delay input (ODATAIN, CLKIN)
+                    .HIGH_PERFORMANCE_MODE("TRUE"), // Reduced jitter to 5ps ("TRUE"), Reduced power but high jitter 9ns ("FALSE")
+                    .ODELAY_TYPE("VAR_LOAD"), // FIXED, VARIABLE, VAR_LOAD, VAR_LOAD_PIPE
+                    .ODELAY_VALUE(DATA_ODELAY_TAP), // Output delay tap setting (0-31)
+                    .REFCLK_FREQUENCY(200.0), // IDELAYCTRL clock input frequency in MHz (190.0-210.0).
+                    .SIGNAL_PATTERN("DATA") // DATA, CLOCK input signal
+                )
+                ODELAYE2_data (
+                    .CNTVALUEOUT(), // 5-bit output: Counter value output
+                    .DATAOUT(odelay_data[gen_index]), // 1-bit output: Delayed data/clock output
+                    .C(i_controller_clk), // 1-bit input: Clock input, when using OSERDESE2, C is connected to CLKDIV
+                    .CE(1'b0), // 1-bit input: Active high enable increment/decrement input
+                    .CINVCTRL(1'b0), // 1-bit input: Dynamic clock inversion input
+                    .CLKIN(1'b0), // 1-bit input: Clock delay input
+                    .CNTVALUEIN(i_controller_odelay_data_cntvaluein), // 5-bit input: Counter value input
+                    .INC(1'b0), // 1-bit input: Increment / Decrement tap delay input
+                    .LD(i_controller_odelay_data_ld[gen_index/8]), // 1-bit input: Loads ODELAY_VALUE tap delay in VARIABLE mode, in VAR_LOAD or
+                                // VAR_LOAD_PIPE mode, loads the value of CNTVALUEIN
+                    .LDPIPEEN(1'b0), // 1-bit input: Enables the pipeline register to load data
+                    .ODATAIN(oserdes_data[gen_index]), // 1-bit input: Output delay data input
+                    .REGRST(1'b0) // 1-bit input: Active-high reset tap-delay input
+                );
+
+                if(USE_IO_TERMINATION) begin 
+                    // IOBUF_DCIEN: Single-ended Bi-directional Buffer with Digital Controlled Impedance (DCI)
+                    // and Input path enable/disable
+                    // May only be placed in High Performance (HP) Banks
+                    // 7 Series
+                    // Xilinx HDL Libraries Guide, version 13.4
+                    `ifndef SIM_MODEL
+                        IOBUF_DCIEN #(
+                    `else 
+                        IOBUF_DCIEN_model #(
+                    `endif
+                    .IBUF_LOW_PWR("FALSE"), // Low Power - "TRUE", High Performance = "FALSE"
+                    .SLEW("FAST"), // Specify the output slew rate
+                    .USE_IBUFDISABLE("FALSE") // Use IBUFDISABLE function, "TRUE" or "FALSE"
+                    ) IOBUF_DCIEN_data (
+                        .O(read_dq[gen_index]), // Buffer output
+                        .IO(io_ddr3_dq[gen_index]), // Buffer inout port (connect directly to top-level port)
+                        .DCITERMDISABLE(1'b0), // DCI Termination enable input
+                        .I(odelay_data[gen_index]), // Buffer input
+                        .IBUFDISABLE(1'b0), // Input disable input, low=disable
+                        .T(oserdes_dq_tri_control[gen_index]) // 3-state enable input, high=input, low=output
+                    );
+                    // End of IOBUF_DCIEN_inst instantiation
+
+                 end
+                 else begin                         
+                    // IOBUF: Single-ended Bi-directional Buffer
+                    //All devices
+                    // Xilinx HDL Libraries Guide, version 13.4
+                    `ifndef SIM_MODEL
+                        IOBUF #(
+                    `else 
+                        IOBUF_model #(
+                    `endif
+                        //.DRIVE(12), // Specify the output drive strength
+                        .IBUF_LOW_PWR("FALSE"), // Low Power - "TRUE", High Performance = "FALSE"
+                        //.IOSTANDARD("SSTL15"), // Specify the I/O standard
+                        .SLEW("FAST") // Specify the output slew rate
+                    ) IOBUF_data (
+                        .O(read_dq[gen_index]),// Buffer output
+                        .IO(io_ddr3_dq[gen_index]), // Buffer inout port (connect directly to top-level port)
+                        .I(odelay_data[gen_index]), // Buffer input
+                        .T(oserdes_dq_tri_control[gen_index]) // 3-state enable input, high=read, low=write
+                    );
+                 end
+            end
+            else begin //ODELAY is not supported
+                // OSERDESE2: Output SERial/DESerializer with bitslip
+                //7 Series
+                // Xilinx HDL Libraries Guide, version 13.4
+                `ifndef SIM_MODEL
+                    OSERDESE2 #(
+                `else 
+                    OSERDESE2_model #(
+                `endif
+                    .DATA_RATE_OQ("DDR"), // DDR, SDR
+                    .DATA_RATE_TQ("BUF"), // DDR, SDR
+                    .DATA_WIDTH(8), // Parallel data width (2-8,10,14)
+                    .INIT_OQ(1'b0), // Initial value of OQ output (1'b0,1'b1)
+                    .TRISTATE_WIDTH(1)
+                )
+                OSERDESE2_data(
+                    .OFB(), // 1-bit output: Feedback path for data
+                    .OQ(oserdes_data[gen_index]), // 1-bit output: Data path output
+                    .TQ(oserdes_dq_tri_control[gen_index]),
+                    .CLK(i_ddr3_clk_90), // 1-bit input: High speed clock
+                    .CLKDIV(i_controller_clk), // 1-bit input: Divided clock
+                    // D1 - D8: 1-bit (each) input: Parallel data inputs (1-bit each)
+                    .D1(i_controller_data[gen_index + (DQ_BITS*LANES)*0]),
+                    .D2(i_controller_data[gen_index + (DQ_BITS*LANES)*1]),
+                    .D3(i_controller_data[gen_index + (DQ_BITS*LANES)*2]),
+                    .D4(i_controller_data[gen_index + (DQ_BITS*LANES)*3]),
+                    .D5(i_controller_data[gen_index + (DQ_BITS*LANES)*4]),
+                    .D6(i_controller_data[gen_index + (DQ_BITS*LANES)*5]),
+                    .D7(i_controller_data[gen_index + (DQ_BITS*LANES)*6]),
+                    .D8(i_controller_data[gen_index + (DQ_BITS*LANES)*7]),
+                    .T1(i_controller_dq_tri_control),
+                    .TCE(1'b1),
+                    .OCE(1'b1), // 1-bit input: Output data clock enable
+                    .RST(sync_rst), // 1-bit input: Reset
+                    // unused signals but were added here to make vivado happy
+                    .SHIFTOUT1(), // SHIFTOUT1 / SHIFTOUT2: 1-bit (each) output: Data output expansion (1-bit each)
+                    .SHIFTOUT2(),
+                    .TBYTEOUT(), // 1-bit output: Byte group tristate
+                    .TFB(), // 1-bit output: 3-state control
+                    // SHIFTIN1 / SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each)
+                    .SHIFTIN1(0),
+                    .SHIFTIN2(0),
+                    // T1 - T4: 1-bit (each) input: Parallel 3-state inputs
+                    .T2(0),
+                    .T3(0),
+                    .T4(0),
+                    .TBYTEIN(0)
+                    // 1-bit input: Byte group tristate
+                );
+                // End of OSERDESE2_inst instantiation
+                
+                // IOBUF: Single-ended Bi-directional Buffer
+                //All devices
+                // Xilinx HDL Libraries Guide, version 13.4
+                `ifndef SIM_MODEL
+                    IOBUF #(
+                `else 
+                    IOBUF_model #(
+                `endif
+                    //.DRIVE(12), // Specify the output drive strength
+                    .IBUF_LOW_PWR("FALSE"), // Low Power - "TRUE", High Performance = "FALSE"
+                    //.IOSTANDARD("SSTL15"), // Specify the I/O standard
+                    .SLEW("FAST") // Specify the output slew rate
+                ) IOBUF_data (
+                    .O(read_dq[gen_index]),// Buffer output
+                    .IO(io_ddr3_dq[gen_index]), // Buffer inout port (connect directly to top-level port)
+                    .I(oserdes_data[gen_index]), // Buffer input
+                    .T(oserdes_dq_tri_control[gen_index]) // 3-state enable input, high=read, low=write
+                );
+            end
+
+            // IDELAYE2: Input Fixed or Variable Delay Element
+            // 7 Series
+            // Xilinx HDL Libraries Guide, version 13.4
+            (* IODELAY_GROUP="DDR3-GROUP" *)
+            `ifndef SIM_MODEL
+                IDELAYE2 #(
+            `else 
+                IDELAYE2_model #(
+            `endif
+                .DELAY_SRC("IDATAIN"), // Delay input (IDATAIN, DATAIN)
+                .HIGH_PERFORMANCE_MODE("TRUE"), //Reduced jitter ("TRUE"), Reduced power ("FALSE")
+                .IDELAY_TYPE("VAR_LOAD"), //FIXED, VARIABLE, VAR_LOAD, VAR_LOAD_PIPE
+                .IDELAY_VALUE(DATA_IDELAY_TAP), //Input delay tap setting (0-31)
+                .PIPE_SEL("FALSE"),  //Select pipelined mode, FALSE, TRUE
+                .REFCLK_FREQUENCY(200.0), //IDELAYCTRL clock input frequency in MHz (190.0-210.0).
+                .SIGNAL_PATTERN("DATA") //DATA, CLOCK input signal
+            )
+            IDELAYE2_data (
+                .CNTVALUEOUT(), // 5-bit output: Counter value output
+                .DATAOUT(idelay_data[gen_index]), // 1-bit output: Delayed data output
+                .C(i_controller_clk), // 1-bit input: Clock input
+                .CE(1'b0), // 1-bit input: Active high enable increment/decrement input
+                .CINVCTRL(1'b0),// 1-bit input: Dynamic clock inversion input
+                .CNTVALUEIN(i_controller_idelay_data_cntvaluein), // 5-bit input: Counter value input
+                .DATAIN(), //1-bit input: Internal delay data input
+                .IDATAIN(read_dq[gen_index]), // 1-bit input: Data input from the I/O
+                .INC(1'b0), // 1-bit input: Increment / Decrement tap delay input
+                .LD(i_controller_idelay_data_ld[gen_index/8]), // 1-bit input: Load IDELAY_VALUE input
+                .LDPIPEEN(1'b0), // 1-bit input: Enable PIPELINE register to load data input
+                .REGRST(1'b0) // 1-bit input: Active-high reset tap-delay input
+            );
+            // End of IDELAYE2_inst instantiation
+
+            // End of IOBUF_inst instantiation                 
+            // ISERDESE2: Input SERial/DESerializer with bitslip
+            //7 Series
+            // Xilinx HDL Libraries Guide, version 13.4
+            `ifndef SIM_MODEL
+                ISERDESE2 #(
+            `else 
+                ISERDESE2_model #(
+            `endif
+                .DATA_RATE("DDR"), // DDR, SDR
+                .DATA_WIDTH(8), // Parallel data width (2-8,10,14)
+                // INIT_Q1 - INIT_Q4: Initial value on the Q outputs (0/1)
+                .INIT_Q1(1'b0),
+                .INIT_Q2(1'b0),
+                .INIT_Q3(1'b0),
+                .INIT_Q4(1'b0),
+                .INTERFACE_TYPE("NETWORKING"), // MEMORY, MEMORY_DDR3, MEMORY_QDR, NETWORKING, OVERSAMPLE
+                .IOBDELAY("IFD"), // NONE, BOTH, IBUF, IFD
+                .NUM_CE(1),// Number of clock enables (1,2)
+                .OFB_USED("FALSE"), // Select OFB path (FALSE, TRUE)
+                // SRVAL_Q1 - SRVAL_Q4: Q output values when SR is used (0/1)
+                .SRVAL_Q1(1'b0),
+                .SRVAL_Q2(1'b0),
+                .SRVAL_Q3(1'b0),
+                .SRVAL_Q4(1'b0)
+            )
+            ISERDESE2_data (
+                .O(),
+                // 1-bit output: Combinatorial output
+                // Q1 - Q8: 1-bit (each) output: Registered data outputs
+                .Q1(o_controller_iserdes_data[(DQ_BITS*LANES)*7 + gen_index]),//56
+                .Q2(o_controller_iserdes_data[(DQ_BITS*LANES)*6 + gen_index]), //48
+                .Q3(o_controller_iserdes_data[(DQ_BITS*LANES)*5 + gen_index]),
+                .Q4(o_controller_iserdes_data[(DQ_BITS*LANES)*4 + gen_index]),   
+                .Q5(o_controller_iserdes_data[(DQ_BITS*LANES)*3 + gen_index]),
+                .Q6(o_controller_iserdes_data[(DQ_BITS*LANES)*2 + gen_index]),
+                .Q7(o_controller_iserdes_data[(DQ_BITS*LANES)*1 + gen_index]), 
+                .Q8(o_controller_iserdes_data[(DQ_BITS*LANES)*0 + gen_index]),
+                // SHIFTOUT1-SHIFTOUT2: 1-bit (each) output: Data width expansion output ports
+                .SHIFTOUT1(),
+                .SHIFTOUT2(),
+                .BITSLIP(i_controller_bitslip[gen_index/8]),
+                // 1-bit input: The BITSLIP pin performs a Bitslip operation synchronous to
+                // CLKDIV when asserted (active High). Subsequently, the data seen on the Q1
+                // to Q8 output ports will shift, as in a barrel-shifter operation, one
+                // position every time Bitslip is invoked (DDR operation is different from
+                // SDR).
+                // CE1, CE2: 1-bit (each) input: Data register clock enable inputs
+                .CE1(1'b1),
+                .CE2(1'b1),
+                .CLKDIVP(), // 1-bit input: TBD
+                // Clocks: 1-bit (each) input: ISERDESE2 clock input ports
+                .CLK(i_ddr3_clk), // 1-bit input: High-speed clock
+                .CLKB(!i_ddr3_clk), // 1-bit input: High-speed secondary clock
+                .CLKDIV(i_controller_clk), // 1-bit input: Divided clock
+                .OCLK(), // 1-bit input: High speed output clock used when INTERFACE_TYPE="MEMORY"
+                // Dynamic Clock Inversions: 1-bit (each) input: Dynamic clock inversion pins to switch clock polarity
+                .DYNCLKDIVSEL(), // 1-bit input: Dynamic CLKDIV inversion
+                .DYNCLKSEL(), // 1-bit input: Dynamic CLK/CLKB inversion
+                // Input Data: 1-bit (each) input: ISERDESE2 data input ports
+                .D(), // 1-bit input: Data input
+                .DDLY(idelay_data[gen_index]), // 1-bit input: Serial data from IDELAYE2
+                .OFB(), // 1-bit input: Data feedback from OSERDESE2
+                .OCLKB(), // 1-bit input: High speed negative edge output clock
+                .RST(sync_rst), // 1-bit input: Active high asynchronous reset
+                // SHIFTIN1-SHIFTIN2: 1-bit (each) input: Data width expansion input ports
+                .SHIFTIN1(),
+                .SHIFTIN2()
+            );
+            // End of ISERDESE2_inst instantiation
+  
+        end
+        
+        // data mask: oserdes -> odelay -> obuf
+        for(gen_index = 0; gen_index < LANES; gen_index = gen_index + 1) begin
+ 
+            
+            if(ODELAY_SUPPORTED) begin
+                // OSERDESE2: Output SERial/DESerializer with bitslip
+                //7 Series
+                // Xilinx HDL Libraries Guide, version 13.4
+                `ifndef SIM_MODEL
+                    OSERDESE2 #(
+                `else 
+                    OSERDESE2_model #(
+                `endif
+                    .DATA_RATE_OQ("DDR"), // DDR, SDR
+                    .DATA_RATE_TQ("BUF"), // DDR, SDR
+                    .DATA_WIDTH(8), // Parallel data width (2-8,10,14)
+                    .INIT_OQ(1'b0), // Initial value of OQ output (1'b0,1'b1)
+                    .TRISTATE_WIDTH(1)
+                )
+                OSERDESE2_dm(
+                    .OFB(oserdes_dm[gen_index]), // 1-bit output: Feedback path for data
+                    .OQ(), // 1-bit output: Data path output
+                    .CLK(i_ddr3_clk), // 1-bit input: High speed clock
+                    .CLKDIV(i_controller_clk), // 1-bit input: Divided clock
+                    // D1 - D8: 1-bit (each) input: Parallel data inputs (1-bit each)
+                    .D1(i_controller_dm[gen_index + LANES*0]),
+                    .D2(i_controller_dm[gen_index + LANES*1]),
+                    .D3(i_controller_dm[gen_index + LANES*2]),
+                    .D4(i_controller_dm[gen_index + LANES*3]),
+                    .D5(i_controller_dm[gen_index + LANES*4]),
+                    .D6(i_controller_dm[gen_index + LANES*5]),
+                    .D7(i_controller_dm[gen_index + LANES*6]),
+                    .D8(i_controller_dm[gen_index + LANES*7]), 
+                    .TCE(1'b0),
+                    .OCE(1'b1), // 1-bit input: Output data clock enable
+                    .RST(sync_rst), // 1-bit input: Reset
+                     // unused signals but were added here to make vivado happy
+                    .SHIFTOUT1(), // SHIFTOUT1 / SHIFTOUT2: 1-bit (each) output: Data output expansion (1-bit each)
+                    .SHIFTOUT2(),
+                    .TBYTEOUT(), // 1-bit output: Byte group tristate
+                    .TFB(), // 1-bit output: 3-state control
+                    .TQ(), // 1-bit output: 3-state control
+                    // SHIFTIN1 / SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each)
+                    .SHIFTIN1(0),
+                    .SHIFTIN2(0),
+                    // T1 - T4: 1-bit (each) input: Parallel 3-state inputs
+                    .T1(0),
+                    .T2(0),
+                    .T3(0),
+                    .T4(0),
+                    .TBYTEIN(0)
+                    // 1-bit input: Byte group tristate
+                );
+                // End of OSERDESE2_inst instantiation
+            
+                // ODELAYE2: Output Fixed or Variable Delay Element
+                // 7 Series
+                // Xilinx HDL Libraries Guide, version 13.4
+                //odelay adds an insertion delay of 600ps to the actual delay setting: https://support.xilinx.com/s/article/42133?language=en_US
+                //Delay the DQ
+                // Delay resolution: 1/(32 x 2 x F REF ) = 78.125ps
+                (* IODELAY_GROUP="DDR3-GROUP" *)
+                `ifndef SIM_MODEL
+                    ODELAYE2 #(
+                `else 
+                    ODELAYE2_model #(
+                `endif
+                    .DELAY_SRC("ODATAIN"), // Delay input (ODATAIN, CLKIN)
+                    .HIGH_PERFORMANCE_MODE("TRUE"), // Reduced jitter to 5ps ("TRUE"), Reduced power but high jitter 9ns ("FALSE")
+                    .ODELAY_TYPE("VAR_LOAD"), // FIXED, VARIABLE, VAR_LOAD, VAR_LOAD_PIPE
+                    .ODELAY_VALUE(DATA_ODELAY_TAP), // Output delay tap setting (0-31)
+                    .REFCLK_FREQUENCY(200.0), // IDELAYCTRL clock input frequency in MHz (190.0-210.0).
+                    .SIGNAL_PATTERN("DATA") // DATA, CLOCK input signal
+                )
+                ODELAYE2_dm (
+                    .CNTVALUEOUT(), // 5-bit output: Counter value output
+                    .DATAOUT(odelay_dm[gen_index]), // 1-bit output: Delayed data/clock output
+                    .C(i_controller_clk), // 1-bit input: Clock input, when using OSERDESE2, C is connected to CLKDIV
+                    .CE(1'b0), // 1-bit input: Active high enable increment/decrement input
+                    .CINVCTRL(1'b0), // 1-bit input: Dynamic clock inversion input
+                    .CLKIN(1'b0), // 1-bit input: Clock delay input
+                    .CNTVALUEIN(i_controller_odelay_data_cntvaluein), // 5-bit input: Counter value input
+                    .INC(1'b0), // 1-bit input: Increment / Decrement tap delay input
+                    .LD(i_controller_odelay_data_ld[gen_index]), // 1-bit input: Loads ODELAY_VALUE tap delay in VARIABLE mode, in VAR_LOAD or
+                                // VAR_LOAD_PIPE mode, loads the value of CNTVALUEIN
+                    .LDPIPEEN(1'b0), // 1-bit input: Enables the pipeline register to load data
+                    .ODATAIN(oserdes_dm[gen_index]), // 1-bit input: Output delay data input
+                    .REGRST(1'b0) // 1-bit input: Active-high reset tap-delay input
+                );
+                
+                // OBUF: Single-ended Output Buffer
+                // 7 Series
+                // Xilinx HDL Libraries Guide, version 13.4
+                `ifndef SIM_MODEL
+                    OBUF #(
+                `else 
+                    OBUF_model #(
+                `endif
+                //.IOSTANDARD("SSTL_15"), // Specify the output I/O standard
+                .SLEW("FAST") // Specify the output slew rate
+                ) OBUF_dm (
+                    .O(o_ddr3_dm[gen_index]), // Buffer output (connect directly to top-level port)
+                    .I(odelay_dm[gen_index]) // Buffer input
+                );
+                // End of OBUF_inst instantiation
+            end
+            else begin
+                // OSERDESE2: Output SERial/DESerializer with bitslip
+                //7 Series
+                // Xilinx HDL Libraries Guide, version 13.4
+                `ifndef SIM_MODEL
+                    OSERDESE2 #(
+                `else 
+                    OSERDESE2_model #(
+                `endif
+                    .DATA_RATE_OQ("DDR"), // DDR, SDR
+                    .DATA_RATE_TQ("BUF"), // DDR, SDR
+                    .DATA_WIDTH(8), // Parallel data width (2-8,10,14)
+                    .INIT_OQ(1'b0), // Initial value of OQ output (1'b0,1'b1)
+                    .TRISTATE_WIDTH(1)
+                )
+                OSERDESE2_dm(
+                    .OFB(), // 1-bit output: Feedback path for data
+                    .OQ(oserdes_dm[gen_index]), // 1-bit output: Data path output
+                    .CLK(i_ddr3_clk_90), // 1-bit input: High speed clock
+                    .CLKDIV(i_controller_clk), // 1-bit input: Divided clock
+                    // D1 - D8: 1-bit (each) input: Parallel data inputs (1-bit each)
+                    .D1(i_controller_dm[gen_index + LANES*0]),
+                    .D2(i_controller_dm[gen_index + LANES*1]),
+                    .D3(i_controller_dm[gen_index + LANES*2]),
+                    .D4(i_controller_dm[gen_index + LANES*3]),
+                    .D5(i_controller_dm[gen_index + LANES*4]),
+                    .D6(i_controller_dm[gen_index + LANES*5]),
+                    .D7(i_controller_dm[gen_index + LANES*6]),
+                    .D8(i_controller_dm[gen_index + LANES*7]), 
+                    .TCE(1'b0),
+                    .OCE(1'b1), // 1-bit input: Output data clock enable
+                    .RST(sync_rst), // 1-bit input: Reset
+                     // unused signals but were added here to make vivado happy
+                    .SHIFTOUT1(), // SHIFTOUT1 / SHIFTOUT2: 1-bit (each) output: Data output expansion (1-bit each)
+                    .SHIFTOUT2(),
+                    .TBYTEOUT(), // 1-bit output: Byte group tristate
+                    .TFB(), // 1-bit output: 3-state control
+                    .TQ(), // 1-bit output: 3-state control
+                    // SHIFTIN1 / SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each)
+                    .SHIFTIN1(0),
+                    .SHIFTIN2(0),
+                    // T1 - T4: 1-bit (each) input: Parallel 3-state inputs
+                    .T1(0),
+                    .T2(0),
+                    .T3(0),
+                    .T4(0),
+                    .TBYTEIN(0)
+                    // 1-bit input: Byte group tristate
+                );
+                // End of OSERDESE2_inst instantiation
+            
+                // OBUF: Single-ended Output Buffer
+                // 7 Series
+                // Xilinx HDL Libraries Guide, version 13.4
+                `ifndef SIM_MODEL
+                    OBUF #(
+                `else 
+                    OBUF_model #(
+                `endif
+                //.IOSTANDARD("SSTL_15"), // Specify the output I/O standard
+                .SLEW("FAST") // Specify the output slew rate
+                ) OBUF_dm (
+                    .O(o_ddr3_dm[gen_index]), // Buffer output (connect directly to top-level port)
+                    .I(oserdes_dm[gen_index]) // Buffer input
+                );
+                // End of OBUF_inst instantiation
+            
+            end
+        end
+
+        // dqs: odelay -> iobuf
+        for(gen_index = 0; gen_index < LANES; gen_index = gen_index + 1) begin
+`ifndef DEBUG_DQS  //remove the logic for dqs if needs to be debugged (directed to output instead)  
+            if(ODELAY_SUPPORTED) begin 
+                // OSERDESE2: Output SERial/DESerializer with bitslip
+                //7 Series
+                // Xilinx HDL Libraries Guide, version 13.4
+                `ifndef SIM_MODEL
+                    OSERDESE2 #(
+                `else 
+                    OSERDESE2_model #(
+                `endif
+                    .DATA_RATE_OQ("DDR"), // DDR, SDR
+                    .DATA_RATE_TQ("BUF"), // DDR, SDR
+                    .DATA_WIDTH(8), // Parallel data width (2-8,10,14)
+                    .INIT_OQ(1'b1), // Initial value of OQ output (1'b0,1'b1)
+                    .TRISTATE_WIDTH(1)
+                )
+                OSERDESE2_dqs(
+                    .OFB(oserdes_dqs[gen_index]), // 1-bit output: Feedback path for data
+                    .OQ(), // 1-bit output: Data path output
+                    .TQ(oserdes_dqs_tri_control[gen_index]),
+                    .CLK(i_ddr3_clk), // 1-bit input: High speed clock
+                    .CLKDIV(i_controller_clk), // 1-bit input: Divided clock
+                    // D1 - D8: 1-bit (each) input: Parallel data inputs (1-bit each)
+                    .D1(1'b1 && (i_controller_toggle_dqs || toggle_dqs_q)), //the last part will still have half dqs series
+                    .D2(1'b0 && (i_controller_toggle_dqs || toggle_dqs_q)),
+                    .D3(1'b1 && (i_controller_toggle_dqs || toggle_dqs_q) && !i_controller_write_leveling_calib),
+                    .D4(1'b0 && (i_controller_toggle_dqs || toggle_dqs_q)),
+                    .D5(1'b1 && i_controller_toggle_dqs && !i_controller_write_leveling_calib),
+                    .D6(1'b0 && i_controller_toggle_dqs),
+                    .D7(1'b1 && i_controller_toggle_dqs && !i_controller_write_leveling_calib),
+                    .D8(1'b0 && i_controller_toggle_dqs),
+                    .T1(i_controller_dqs_tri_control),
+                    .TCE(1'b1),
+                    .OCE(1'b1), // 1-bit input: Output data clock enable
+                    .RST(sync_rst), // 1-bit input: Reset
+                     // unused signals but were added here to make vivado happy
+                    .SHIFTOUT1(), // SHIFTOUT1 / SHIFTOUT2: 1-bit (each) output: Data output expansion (1-bit each)
+                    .SHIFTOUT2(),
+                    .TBYTEOUT(), // 1-bit output: Byte group tristate
+                    .TFB(), // 1-bit output: 3-state control
+                    // SHIFTIN1 / SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each)
+                    .SHIFTIN1(0),
+                    .SHIFTIN2(0),
+                    // T1 - T4: 1-bit (each) input: Parallel 3-state inputs
+                    .T2(0),
+                    .T3(0),
+                    .T4(0),
+                    .TBYTEIN(0)
+                    // 1-bit input: Byte group tristate
+                );
+                // End of OSERDESE2_inst instantiation
+            
+            
+                // ODELAYE2: Output Fixed or Variable Delay Element
+                // 7 Series
+                // Xilinx HDL Libraries Guide, version 13.4
+                //Delay the DQ
+                (* IODELAY_GROUP="DDR3-GROUP" *)
+                `ifndef SIM_MODEL
+                    ODELAYE2 #(
+                `else 
+                    ODELAYE2_model #(
+                `endif
+                    .DELAY_SRC("ODATAIN"), // Delay input (ODATAIN, CLKIN)
+                    .HIGH_PERFORMANCE_MODE("TRUE"), // Reduced jitter ("TRUE"), Reduced power ("FALSE")
+                    .ODELAY_TYPE("VAR_LOAD"), // FIXED, VARIABLE, VAR_LOAD, VAR_LOAD_PIPE
+                    .ODELAY_VALUE(DQS_ODELAY_TAP), // delay to align odelay_dqs to oserdes_dqs due to 600ps insertion delay: (1/800MHz - 600ps)/78.125ps = 8.32 taps
+                    .REFCLK_FREQUENCY(200.0), // IDELAYCTRL clock input frequency in MHz (190.0-210.0).
+                    .SIGNAL_PATTERN("DATA") // DATA, CLOCK input signal
+                )
+                ODELAYE2_dqs (
+                    .CNTVALUEOUT(), // 5-bit output: Counter value output
+                    .DATAOUT(odelay_dqs[gen_index]), // 1-bit output: Delayed data/clock output
+                    .C(i_controller_clk), // 1-bit input: Clock input, when using OSERDESE2, C is connected to CLKDIV
+                    .CE(1'b0), // 1-bit input: Active high enable increment/decrement input
+                    .CINVCTRL(1'b0), // 1-bit input: Dynamic clock inversion input
+                    .CLKIN(1'b0), // 1-bit input: Clock delay input
+                    .CNTVALUEIN(i_controller_odelay_dqs_cntvaluein), // 5-bit input: Counter value input
+                    .INC(1'b0), // 1-bit input: Increment / Decrement tap delay input
+                    .LD(i_controller_odelay_dqs_ld[gen_index]), // 1-bit input: Loads ODELAY_VALUE tap delay in VARIABLE mode, in VAR_LOAD or
+                                // VAR_LOAD_PIPE mode, loads the value of CNTVALUEIN
+                    .LDPIPEEN(1'b0), // 1-bit input: Enables the pipeline register to load data
+                    .ODATAIN(oserdes_dqs[gen_index]), // 1-bit input: Output delay data input
+                    .REGRST(1'b0) // 1-bit input: Active-high reset tap-delay input
+                );
+                
+                if(USE_IO_TERMINATION) begin 
+                    // IOBUFDS_DCIEN: Differential Bi-directional Buffer with Digital Controlled Impedance (DCI)
+                    // and Input path enable/disable
+                    // May only be placed in High Performance (HP) Banks
+                    // 7 Series
+                    // Xilinx HDL Libraries Guide, version 13.4
+                    `ifndef SIM_MODEL
+                        IOBUFDS_DCIEN #(
+                    `else 
+                        IOBUFDS_DCIEN_model #(
+                    `endif
+                        .IBUF_LOW_PWR("FALSE"), // Low Power - "TRUE", High Performance = "FALSE"
+                        .SLEW("FAST"), // Specify the output slew rate
+                        .USE_IBUFDISABLE("FALSE") // Use IBUFDISABLE function, "TRUE" or "FALSE"
+                    ) IOBUFDS_DCIEN_inst (
+                        .O(read_dqs[gen_index]),  // Buffer output
+                        .IO(io_ddr3_dqs[gen_index]), // Diff_p inout (connect directly to top-level port)
+                        .IOB(io_ddr3_dqs_n[gen_index]), // Diff_n inout (connect directly to top-level port)
+                        .DCITERMDISABLE(1'b0), // DCI Termination enable input
+                        .I(odelay_dqs[gen_index]), // Buffer input
+                        .IBUFDISABLE(1'b0), // Input disable input, low=disable
+                        .T(oserdes_dqs_tri_control[gen_index]) // 3-state enable input, high=input, low=output
+                    );
+                    // End of IOBUFDS_DCIEN_inst instantiation
+
+                end
+                else begin
+                    // IOBUFDS: Differential Bi-directional Buffer
+                    //7 Series
+                    // Xilinx HDL Libraries Guide, version 13.4
+                    `ifndef SIM_MODEL
+                        IOBUFDS #(
+                    `else 
+                        IOBUFDS_model #(
+                    `endif
+                        //.DIFF_TERM("FALSE"), // Differential Termination ("TRUE"/"FALSE")
+                        .IBUF_LOW_PWR("FALSE") // Low Power - "TRUE", High Performance = "FALSE"
+                        //.IOSTANDARD("DIFF_SSTL15") // Specify the I/O standard. CONSULT WITH DATASHEET
+                        //.SLEW("FAST") // Specify the output slew rate
+                    ) IOBUFDS_dqs (
+                        .O(read_dqs[gen_index]), // Buffer output
+                        .IO(io_ddr3_dqs[gen_index]), // Diff_p inout (connect directly to top-level port)
+                        .IOB(io_ddr3_dqs_n[gen_index]), // Diff_n inout (connect directly to top-level port)
+                        .I(odelay_dqs[gen_index]), // Buffer input
+                        .T(/*!dqs_tri_control[gen_index]*/oserdes_dqs_tri_control[gen_index]) // 3-state enable input, high=input, low=output
+                    ); // End of IOBUFDS_inst instantiation
+                end
+                
+            end
+            
+            else begin //ODELAY not supported
+                // OSERDESE2: Output SERial/DESerializer with bitslip
+                //7 Series
+                // Xilinx HDL Libraries Guide, version 13.4
+                `ifndef SIM_MODEL
+                    OSERDESE2 #(
+                `else 
+                    OSERDESE2_model #(
+                `endif
+                    .DATA_RATE_OQ("DDR"), // DDR, SDR
+                    .DATA_RATE_TQ("BUF"), // DDR, SDR
+                    .DATA_WIDTH(8), // Parallel data width (2-8,10,14)
+                    .INIT_OQ(1'b1), // Initial value of OQ output (1'b0,1'b1)
+                    .TRISTATE_WIDTH(1)
+                )
+                OSERDESE2_dqs(
+                    .OFB(), // 1-bit output: Feedback path for data
+                    .OQ(oserdes_dqs[gen_index]), // 1-bit output: Data path output
+                    .TQ(oserdes_dqs_tri_control[gen_index]),
+                    .CLK(!i_ddr3_clk), // 1-bit input: High speed clock
+                    .CLKDIV(i_controller_clk), // 1-bit input: Divided clock
+                    // D1 - D8: 1-bit (each) input: Parallel data inputs (1-bit each)
+                    .D1(1'b1 && (i_controller_toggle_dqs || toggle_dqs_q)), //the last part will still have half dqs series
+                    .D2(1'b0 && (i_controller_toggle_dqs || toggle_dqs_q)),
+                    .D3(1'b1 && (i_controller_toggle_dqs || toggle_dqs_q) && !i_controller_write_leveling_calib),
+                    .D4(1'b0 && (i_controller_toggle_dqs || toggle_dqs_q)),
+                    .D5(1'b1 && i_controller_toggle_dqs && !i_controller_write_leveling_calib),
+                    .D6(1'b0 && i_controller_toggle_dqs),
+                    .D7(1'b1 && i_controller_toggle_dqs && !i_controller_write_leveling_calib),
+                    .D8(1'b0 && i_controller_toggle_dqs),
+                    .T1(i_controller_dqs_tri_control),
+                    .TCE(1'b1),
+                    .OCE(1'b1), // 1-bit input: Output data clock enable
+                    .RST(sync_rst), // 1-bit input: Reset
+                     // unused signals but were added here to make vivado happy
+                    .SHIFTOUT1(), // SHIFTOUT1 / SHIFTOUT2: 1-bit (each) output: Data output expansion (1-bit each)
+                    .SHIFTOUT2(),
+                    .TBYTEOUT(), // 1-bit output: Byte group tristate
+                    .TFB(), // 1-bit output: 3-state control
+                    // SHIFTIN1 / SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each)
+                    .SHIFTIN1(0),
+                    .SHIFTIN2(0),
+                    // T1 - T4: 1-bit (each) input: Parallel 3-state inputs
+                    .T2(0),
+                    .T3(0),
+                    .T4(0),
+                    .TBYTEIN(0)
+                    // 1-bit input: Byte group tristate
+                );
+                // End of OSERDESE2_inst instantiation
+                
+                // IOBUFDS: Differential Bi-directional Buffer
+                //7 Series
+                // Xilinx HDL Libraries Guide, version 13.4
+                `ifndef SIM_MODEL
+                    IOBUFDS #(
+                `else 
+                    IOBUFDS_model #(
+                `endif
+                    //.DIFF_TERM("FALSE"), // Differential Termination ("TRUE"/"FALSE")
+                    .IBUF_LOW_PWR("FALSE") // Low Power - "TRUE", High Performance = "FALSE"
+                    //.IOSTANDARD("DIFF_SSTL15") // Specify the I/O standard. CONSULT WITH DATASHEET
+                    //.SLEW("FAST") // Specify the output slew rate
+                ) IOBUFDS_dqs (
+                    .O(read_dqs[gen_index]), // Buffer output
+                    .IO(io_ddr3_dqs[gen_index]), // Diff_p inout (connect directly to top-level port)
+                    .IOB(io_ddr3_dqs_n[gen_index]), // Diff_n inout (connect directly to top-level port)
+                    .I(oserdes_dqs[gen_index]), // Buffer input
+                    .T(/*!dqs_tri_control[gen_index]*/oserdes_dqs_tri_control[gen_index]) // 3-state enable input, high=input, low=output
+                ); // End of IOBUFDS_inst instantiation
+                
+            end
+            
+            // IDELAYE2: Input Fixed or Variable Delay Element
+            // 7 Series
+            // Xilinx HDL Libraries Guide, version 13.4
+            (* IODELAY_GROUP="DDR3-GROUP" *)
+            `ifndef SIM_MODEL
+                IDELAYE2 #(
+            `else 
+                IDELAYE2_model #(
+            `endif
+                .DELAY_SRC("IDATAIN"), // Delay input (IDATAIN, DATAIN)
+                .HIGH_PERFORMANCE_MODE("TRUE"), //Reduced jitter ("TRUE"), Reduced power ("FALSE")
+                .IDELAY_TYPE("VAR_LOAD"), //FIXED, VARIABLE, VAR_LOAD, VAR_LOAD_PIPE
+                .IDELAY_VALUE(DQS_IDELAY_TAP), //Input delay tap setting (0-31)
+                .PIPE_SEL("FALSE"),  //Select pipelined mode, FALSE, TRUE
+                .REFCLK_FREQUENCY(200.0), //IDELAYCTRL clock input frequency in MHz (190.0-210.0).
+                .SIGNAL_PATTERN("CLOCK") //DATA, CLOCK input signal
+            )
+            IDELAYE2_dqs (
+                .CNTVALUEOUT(), // 5-bit output: Counter value output
+                .DATAOUT(idelay_dqs[gen_index]), // 1-bit output: Delayed data output
+                .C(i_controller_clk), // 1-bit input: Clock input
+                .CE(1'b0), // 1-bit input: Active high enable increment/decrement input
+                .CINVCTRL(1'b0),// 1-bit input: Dynamic clock inversion input
+                .CNTVALUEIN(i_controller_idelay_dqs_cntvaluein), // 5-bit input: Counter value input
+                .DATAIN(), //1-bit input: Internal delay data input
+                .IDATAIN(read_dqs[gen_index]), // 1-bit input: Data input from the I/O
+                .INC(1'b0), // 1-bit input: Increment / Decrement tap delay input
+                .LD(i_controller_idelay_dqs_ld[gen_index]), // 1-bit input: Load IDELAY_VALUE input
+                .LDPIPEEN(1'b0), // 1-bit input: Enable PIPELINE register to load data input
+                .REGRST(1'b0) // 1-bit input: Active-high reset tap-delay input
+            );
+            // End of IDELAYE2_inst instantiation
+            
+             
+              // End of IOBUF_inst instantiation                 
+            // ISERDESE2: Input SERial/DESerializer with bitslip
+            //7 Series
+            // Xilinx HDL Libraries Guide, version 13.4
+            `ifndef SIM_MODEL
+                ISERDESE2 #(
+            `else 
+                ISERDESE2_model #(
+            `endif
+                .DATA_RATE("DDR"), // DDR, SDR
+                .DATA_WIDTH(serdes_ratio*2), // Parallel data width (2-8,10,14)
+                // INIT_Q1 - INIT_Q4: Initial value on the Q outputs (0/1)
+                .INIT_Q1(1'b0),
+                .INIT_Q2(1'b0),
+                .INIT_Q3(1'b0),
+                .INIT_Q4(1'b0),
+                .INTERFACE_TYPE("NETWORKING"), // MEMORY, MEMORY_DDR3, MEMORY_QDR, NETWORKING, OVERSAMPLE
+                .IOBDELAY("IFD"), // NONE, BOTH, IBUF, IFD
+                .NUM_CE(1),// Number of clock enables (1,2)
+                .OFB_USED("FALSE"), // Select OFB path (FALSE, TRUE)
+                // SRVAL_Q1 - SRVAL_Q4: Q output values when SR is used (0/1)
+                .SRVAL_Q1(1'b0),
+                .SRVAL_Q2(1'b0),
+                .SRVAL_Q3(1'b0),
+                .SRVAL_Q4(1'b0)
+            )
+            ISERDESE2_dqs (
+                .O(),
+                // 1-bit output: Combinatorial output
+                // Q1 - Q8: 1-bit (each) output: Registered data outputs
+                .Q1(o_controller_iserdes_dqs[serdes_ratio*2*gen_index + 7]),
+                .Q2(o_controller_iserdes_dqs[serdes_ratio*2*gen_index + 6]),
+                .Q3(o_controller_iserdes_dqs[serdes_ratio*2*gen_index + 5]),
+                .Q4(o_controller_iserdes_dqs[serdes_ratio*2*gen_index + 4]),   
+                .Q5(o_controller_iserdes_dqs[serdes_ratio*2*gen_index + 3]),
+                .Q6(o_controller_iserdes_dqs[serdes_ratio*2*gen_index + 2]), //
+                .Q7(o_controller_iserdes_dqs[serdes_ratio*2*gen_index + 1]), //3
+                .Q8(o_controller_iserdes_dqs[serdes_ratio*2*gen_index + 0]), //2
+                // SHIFTOUT1-SHIFTOUT2: 1-bit (each) output: Data width expansion output ports
+                .SHIFTOUT1(),
+                .SHIFTOUT2(),
+                .BITSLIP(i_controller_bitslip[gen_index]),
+                // 1-bit input: The BITSLIP pin performs a Bitslip operation synchronous to
+                // CLKDIV when asserted (active High). Subsequently, the data seen on the Q1
+                // to Q8 output ports will shift, as in a barrel-shifter operation, one
+                // position every time Bitslip is invoked (DDR operation is different from
+                // SDR).
+                // CE1, CE2: 1-bit (each) input: Data register clock enable inputs
+                .CE1(1'b1),
+                .CE2(1'b1),
+                .CLKDIVP(), // 1-bit input: TBD
+                // Clocks: 1-bit (each) input: ISERDESE2 clock input ports
+                .CLK(i_ddr3_clk), // 1-bit input: High-speed clock
+                .CLKB(!i_ddr3_clk), // 1-bit input: High-speed secondary clock
+                .CLKDIV(i_controller_clk), // 1-bit input: Divided clock
+                .OCLK(), // 1-bit input: High speed output clock used when INTERFACE_TYPE="MEMORY"
+                // Dynamic Clock Inversions: 1-bit (each) input: Dynamic clock inversion pins to switch clock polarity
+                .DYNCLKDIVSEL(), // 1-bit input: Dynamic CLKDIV inversion
+                .DYNCLKSEL(), // 1-bit input: Dynamic CLK/CLKB inversion
+                // Input Data: 1-bit (each) input: ISERDESE2 data input ports
+                .D(), // 1-bit input: Data input
+                .DDLY(idelay_dqs[gen_index]), // 1-bit input: Serial data from IDELAYE2
+                .OFB(), // 1-bit input: Data feedback from OSERDESE2
+                .OCLKB(), // 1-bit input: High speed negative edge output clock
+                .RST(sync_rst), // 1-bit input: Active high asynchronous reset
+                // SHIFTIN1-SHIFTIN2: 1-bit (each) input: Data width expansion input ports
+                .SHIFTIN1(),
+                .SHIFTIN2()
+            );
+            // End of ISERDESE2_inst instantiation
+`endif
+            
+            // generate IOSERDES loopback or not for bitslip training
+            if(NO_IOSERDES_LOOPBACK) begin                    
+                // logic that models OSERDES loopback to ISERDES     
+                // accdg to IOSELECT (UG471) for 7-series:    
+                // " In DDR mode, every Bitslip operation causes the output pattern to alternate between
+                //   a shift right by one and shift left by three"
+                always @(posedge i_controller_clk) begin
+                    if(!i_rst_n || i_controller_reset) begin
+                        o_controller_iserdes_bitslip_reference_reg[(serdes_ratio*2*gen_index + 7) : (serdes_ratio*2*gen_index + 0)] <= 8'b0001_1110;
+                        shift_bitslip_index[gen_index] <= 0;
+                    end
+                    else if(i_controller_bitslip[gen_index]) begin
+                    // if shift_bitslip_index high, shift right by 3, else shift left by 1 (this is reverse of the IOSelect document for ISERDES since vector o_controller_iserdes_bitslip_reference is reversed)
+                        o_controller_iserdes_bitslip_reference_reg[(serdes_ratio*2*gen_index + 7) : (serdes_ratio*2*gen_index + 0)] <= 
+                            shift_bitslip_index[gen_index]? {o_controller_iserdes_bitslip_reference_reg[(serdes_ratio*2*gen_index + 2) : (serdes_ratio*2*gen_index + 0)], o_controller_iserdes_bitslip_reference_reg[(serdes_ratio*2*gen_index + 7) : (serdes_ratio*2*gen_index + 3)]}
+                            : {o_controller_iserdes_bitslip_reference_reg[(serdes_ratio*2*gen_index + 6) : (serdes_ratio*2*gen_index + 0)], o_controller_iserdes_bitslip_reference_reg[(serdes_ratio*2*gen_index + 7)]};
+                        shift_bitslip_index[gen_index] <= !shift_bitslip_index[gen_index];         
+                    end
+                end
+                assign o_controller_iserdes_bitslip_reference = o_controller_iserdes_bitslip_reference_reg;
+            end
+            else begin // OSERDES will loopback to ISERDES for bitslip training    
+                //ISERDES train
+                // End of IOBUF_inst instantiation                 
+                // ISERDESE2: Input SERial/DESerializer with bitslip
+                //7 Series
+                // Xilinx HDL Libraries Guide, version 13.4
+                `ifndef SIM_MODEL
+                    ISERDESE2 #(
+                `else 
+                    ISERDESE2_model #(
+                `endif
+                    .DATA_RATE("DDR"), // DDR, SDR
+                    .DATA_WIDTH(serdes_ratio*2), // Parallel data width (2-8,10,14)
+                    // INIT_Q1 - INIT_Q4: Initial value on the Q outputs (0/1)
+                    .INIT_Q1(1'b0),
+                    .INIT_Q2(1'b0),
+                    .INIT_Q3(1'b0),
+                    .INIT_Q4(1'b0),
+                    .INTERFACE_TYPE("NETWORKING"), // MEMORY, MEMORY_DDR3, MEMORY_QDR, NETWORKING, OVERSAMPLE
+                    .IOBDELAY("NONE"), // NONE, BOTH, IBUF, IFD
+                    .NUM_CE(1),// Number of clock enables (1,2)
+                    .OFB_USED("TRUE"), // Select OFB path (FALSE, TRUE)
+                    // SRVAL_Q1 - SRVAL_Q4: Q output values when SR is used (0/1)
+                    .SRVAL_Q1(1'b0),
+                    .SRVAL_Q2(1'b0),
+                    .SRVAL_Q3(1'b0),
+                    .SRVAL_Q4(1'b0)
+                )
+                ISERDESE2_train (
+                    .O(),
+                    // 1-bit output: Combinatorial output
+                    // Q1 - Q8: 1-bit (each) output: Registered data outputs
+                    .Q1(o_controller_iserdes_bitslip_reference[gen_index*serdes_ratio*2 + 7]),
+                    .Q2(o_controller_iserdes_bitslip_reference[gen_index*serdes_ratio*2 + 6]),
+                    .Q3(o_controller_iserdes_bitslip_reference[gen_index*serdes_ratio*2 + 5]),
+                    .Q4(o_controller_iserdes_bitslip_reference[gen_index*serdes_ratio*2 + 4]),   
+                    .Q5(o_controller_iserdes_bitslip_reference[gen_index*serdes_ratio*2 + 3]),
+                    .Q6(o_controller_iserdes_bitslip_reference[gen_index*serdes_ratio*2 + 2]),
+                    .Q7(o_controller_iserdes_bitslip_reference[gen_index*serdes_ratio*2 + 1]),
+                    .Q8(o_controller_iserdes_bitslip_reference[gen_index*serdes_ratio*2 + 0]),
+                    // SHIFTOUT1-SHIFTOUT2: 1-bit (each) output: Data width expansion output ports
+                    .SHIFTOUT1(),
+                    .SHIFTOUT2(),
+                    .BITSLIP(i_controller_bitslip[gen_index]),
+                    // 1-bit input: The BITSLIP pin performs a Bitslip operation synchronous to
+                    // CLKDIV when asserted (active High). Subsequently, the data seen on the Q1
+                    // to Q8 output ports will shift, as in a barrel-shifter operation, one
+                    // position every time Bitslip is invoked (DDR operation is different from
+                    // SDR).
+                    // CE1, CE2: 1-bit (each) input: Data register clock enable inputs
+                    .CE1(1'b1),
+                    .CE2(1'b1),
+                    .CLKDIVP(), // 1-bit input: TBD
+                    // Clocks: 1-bit (each) input: ISERDESE2 clock input ports
+                    .CLK(i_ddr3_clk), // 1-bit input: High-speed clock
+                    .CLKB(!i_ddr3_clk), // 1-bit input: High-speed secondary clock
+                    .CLKDIV(i_controller_clk), // 1-bit input: Divided clock
+                    .OCLK(), // 1-bit input: High speed output clock used when INTERFACE_TYPE="MEMORY"
+                    // Dynamic Clock Inversions: 1-bit (each) input: Dynamic clock inversion pins to switch clock polarity
+                    .DYNCLKDIVSEL(), // 1-bit input: Dynamic CLKDIV inversion
+                    .DYNCLKSEL(), // 1-bit input: Dynamic CLK/CLKB inversion
+                    // Input Data: 1-bit (each) input: ISERDESE2 data input ports
+                    .D(), // 1-bit input: Data input
+                    .DDLY(), // 1-bit input: Serial data from IDELAYE2
+                    .OFB(oserdes_bitslip_reference[gen_index]), // 1-bit input: Data feedback from OSERDESE2
+                    .OCLKB(), // 1-bit input: High speed negative edge output clock
+                    .RST(sync_rst), // 1-bit input: Active high asynchronous reset
+                    // SHIFTIN1-SHIFTIN2: 1-bit (each) input: Data width expansion input ports
+                    .SHIFTIN1(),
+                    .SHIFTIN2()
+                );
+                // End of ISERDESE2_inst instantiation
+                
+                // OSERDESE2: Output SERial/DESerializer with bitslip
+                //7 Series
+                // Xilinx HDL Libraries Guide, version 13.4
+                `ifndef SIM_MODEL
+                    OSERDESE2 #(
+                `else 
+                    OSERDESE2_model #(
+                `endif
+                    .DATA_RATE_OQ("DDR"), // DDR, SDR
+                    .DATA_RATE_TQ("BUF"), // DDR, SDR
+                    .DATA_WIDTH(8), // Parallel data width (2-8,10,14)
+                    .INIT_OQ(1'b1), // Initial value of OQ output (1'b0,1'b1)
+                    .TRISTATE_WIDTH(1)
+                )
+                OSERDESE2_train(
+                    .OFB(oserdes_bitslip_reference[gen_index]), // 1-bit output: Feedback path for data
+                    .OQ(), // 1-bit output: Data path output
+                    .CLK(i_ddr3_clk), // 1-bit input: High speed clock
+                    .CLKDIV(i_controller_clk), // 1-bit input: Divided clock
+                    // D1 - D8: 1-bit (each) input: Parallel data inputs (1-bit each)
+                    .D1(1'b0),
+                    .D2(1'b0),
+                    .D3(1'b0),
+                    .D4(1'b0),
+                    .D5(1'b1),
+                    .D6(1'b1),
+                    .D7(1'b1),
+                    .D8(1'b1),
+                    .OCE(1'b1), // 1-bit input: Output data clock enable
+                    .RST(sync_rst), // 1-bit input: Reset
+                     // unused signals but were added here to make vivado happy
+                    .SHIFTOUT1(), // SHIFTOUT1 / SHIFTOUT2: 1-bit (each) output: Data output expansion (1-bit each)
+                    .SHIFTOUT2(),
+                    .TBYTEOUT(), // 1-bit output: Byte group tristate
+                    .TFB(), // 1-bit output: 3-state control
+                    .TQ(), // 1-bit output: 3-state control
+                    // SHIFTIN1 / SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each)
+                    .SHIFTIN1(0),
+                    .SHIFTIN2(0),
+                    // T1 - T4: 1-bit (each) input: Parallel 3-state inputs
+                    .T1(0),
+                    .T2(0),
+                    .T3(0),
+                    .T4(0),
+                    .TBYTEIN(0),
+                    // 1-bit input: Byte group tristate
+                    .TCE(0)
+                    // 1-bit input: 3-state clock enable
+                );
+                // End of OSERDESE2_inst instantiation  
+            end
+            
+        end
+     endgenerate 
+     
+
+    // IDELAYCTRL: IDELAYE2/ODELAYE2 Tap Delay Value Control
+    // 7 Series
+    // Xilinx HDL Libraries Guide, version 13.4
+    (* IODELAY_GROUP="DDR3-GROUP" *)
+    `ifndef SIM_MODEL
+        IDELAYCTRL IDELAYCTRL_inst (
+    `else 
+        IDELAYCTRL_model IDELAYCTRL_inst (
+    `endif
+        .RDY(idelayctrl_rdy), // 1-bit output: Ready output
+        .REFCLK(i_ref_clk), // 1-bit input: Reference clock input.The frequency of REFCLK must be 200 MHz to guarantee the tap-delay value specified in the applicable data sheet.
+        .RST(sync_rst) // 1-bit input: Active high reset input, To ,Minimum Reset pulse width is 52ns
+    );
+    // End of IDELAYCTRL_inst instantiation
+
+
+    // DCIRESET: Digitially Controlled Impedence Reset Component
+    //7 Series
+    // Xilinx HDL Libraries Guide, version 13.4
+    // DCIRESET DCIRESET_inst (
+    //     .LOCKED(dci_locked), // 1-bit output: LOCK status output (When low, DCI I/O impedance is being calibrated and DCI I/Os are unavailable)
+    //     .RST(sync_rst) // 1-bit input: Active-high asynchronous reset input
+    // );
+    assign dci_locked = 1;
+    // End of DCIRESET_inst instantiation
+         
+endmodule

AngeloJacobo_UberDDR3/example_demo/alinx_ax7103b/ddr3_top.v

@@ -0,0 +1,475 @@
+////////////////////////////////////////////////////////////////////////////////
+//
+// Filename: ddr3_top.v
+// Project: UberDDR3 - An Open Source DDR3 Controller
+//
+// Purpose: Top module which instantiates the ddr3_controller and ddr3_phy modules
+// Use this as top module for instantiating UberDDR3 with Wishbone Interface.
+//
+// Engineer: Angelo C. Jacobo
+//
+////////////////////////////////////////////////////////////////////////////////
+//
+// Copyright (C) 2023-2025  Angelo Jacobo
+// 
+//     This program is free software: you can redistribute it and/or modify
+//     it under the terms of the GNU General Public License as published by
+//     the Free Software Foundation, either version 3 of the License, or
+//     (at your option) any later version.
+// 
+//     This program is distributed in the hope that it will be useful,
+//     but WITHOUT ANY WARRANTY; without even the implied warranty of
+//     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//     GNU General Public License for more details.
+// 
+//     You should have received a copy of the GNU General Public License
+//     along with this program.  If not, see <https://www.gnu.org/licenses/>.
+//
+////////////////////////////////////////////////////////////////////////////////
+
+`default_nettype none
+`timescale 1ps / 1ps
+
+module ddr3_top #(
+    parameter      CONTROLLER_CLK_PERIOD = 12_000, //ps, clock period of the controller interface
+                   DDR3_CLK_PERIOD = 3_000, //ps, clock period of the DDR3 RAM device (must be 1/4 of the CONTROLLER_CLK_PERIOD) 
+                   ROW_BITS = 14,   //width of row address
+                   COL_BITS = 10, //width of column address
+                   BA_BITS = 3, //width of bank address
+                   BYTE_LANES = 2, //number of byte lanes of DDR3 RAM
+                   AUX_WIDTH = 4, //width of aux line (must be >= 4) 
+                   WB2_ADDR_BITS = 7, //width of 2nd wishbone address bus 
+                   WB2_DATA_BITS = 32, //width of 2nd wishbone data bus 
+                   DUAL_RANK_DIMM = 0, // enable dual rank DIMM (1 =  enable, 0 = disable)
+    // DDR3 timing parameter values
+    parameter      SPEED_BIN = 3, // 0 = Use top-level parameters , 1 = DDR3-1066 (7-7-7) , 2 = DR3-1333 (9-9-9) , 3 = DDR3-1600 (11-11-11)
+                   SDRAM_CAPACITY = 5, // 0 = 256Mb, 1 = 512Mb, 2 = 1Gb, 3 = 2Gb, 4 = 4Gb, 5 = 8Gb, 6 = 16Gb
+                   TRCD = 13_750, // ps Active to Read/Write command time (only used if SPEED_BIN = 0)
+                   TRP = 13_750, // ps Precharge command period (only used if SPEED_BIN = 0)
+                   TRAS = 35_000, // ps ACT to PRE command period (only used if SPEED_BIN = 0)
+    parameter[0:0] MICRON_SIM = 0, //enable faster simulation for micron ddr3 model (shorten POWER_ON_RESET_HIGH and INITIAL_CKE_LOW)
+                   ODELAY_SUPPORTED = 0, //set to 1 when ODELAYE2 is supported
+                   SECOND_WISHBONE = 0, //set to 1 if 2nd wishbone for debugging is needed 
+                   DLL_OFF = 0, // 1 = DLL off for low frequency ddr3 clock (< 125MHz)
+                   WB_ERROR = 0, // set to 1 to support Wishbone error (asserts at ECC double bit error)
+    parameter[1:0] BIST_MODE = 1, // 0 = No BIST, 1 = run through all address space ONCE , 2 = run through all address space for every test (burst w/r, random w/r, alternating r/w)
+    parameter[0:0] BIST_TEST_DATAMASK = 1, // 1 = include per-byte DM writes in BIST, 0 = all-byte writes only
+    parameter[1:0] ECC_ENABLE = 0, // set to 1 or 2 to add ECC (1 = Side-band ECC per burst, 2 = Side-band ECC per 8 bursts , 3 = Inline ECC ) 
+    parameter[1:0] DIC = 2'b00, //Output Driver Impedance Control (2'b00 = RZQ/6, 2'b01 = RZQ/7, RZQ = 240ohms) (only change when you know what you are doing)
+    parameter[2:0] RTT_NOM = 3'b011, //RTT Nominal (3'b000 = disabled, 3'b001 = RZQ/4, 3'b010 = RZQ/2 , 3'b011 = RZQ/6, RZQ = 240ohms)  (only change when you know what you are doing)
+    parameter[1:0] SELF_REFRESH = 2'b00, // 0 = use i_user_self_refresh input, 1 = Self-refresh mode is enabled after 64 controller clock cycles of no requests, 2 = 128 cycles, 3 = 256 cycles
+    parameter // The next parameters act more like a localparam (since user does not have to set this manually) but was added here to simplify port declaration
+                DQ_BITS = 8,  //device width (fixed to 8, if DDR3 is x16 then BYTE_LANES will be 2 while )
+                serdes_ratio = 4, // this controller is fixed as a 4:1 memory controller (CONTROLLER_CLK_PERIOD/DDR3_CLK_PERIOD = 4)
+                wb_addr_bits = ROW_BITS + COL_BITS + BA_BITS - $clog2(serdes_ratio*2) + DUAL_RANK_DIMM,
+                wb_data_bits = DQ_BITS*BYTE_LANES*serdes_ratio*2,
+                wb_sel_bits = wb_data_bits / 8,
+                wb2_sel_bits = WB2_DATA_BITS / 8,
+                //4 is the width of a single ddr3 command {cs_n, ras_n, cas_n, we_n} plus 3 (ck_en, odt, reset_n) plus bank bits plus row bits
+                cmd_len = 4 + 3 + BA_BITS + ROW_BITS + 2*DUAL_RANK_DIMM
+    ) 
+    (
+        input wire i_controller_clk, i_ddr3_clk, i_ref_clk, //i_controller_clk = CONTROLLER_CLK_PERIOD, i_ddr3_clk = DDR3_CLK_PERIOD, i_ref_clk = 200MHz
+        input wire i_ddr3_clk_90, //required only when ODELAY_SUPPORTED is zero
+        input wire i_rst_n,
+        //
+        // Wishbone inputs
+        input wire i_wb_cyc, //bus cycle active (1 = normal operation, 0 = all ongoing transaction are to be cancelled)
+        input wire i_wb_stb, //request a transfer
+        input wire i_wb_we, //write-enable (1 = write, 0 = read)
+        input wire[wb_addr_bits - 1:0] i_wb_addr, //burst-addressable {row,bank,col} 
+        input wire[wb_data_bits - 1:0] i_wb_data, //write data, for a 4:1 controller data width is 8 times the number of pins on the device
+        input wire[wb_sel_bits - 1:0] i_wb_sel, //byte strobe for write (1 = write the byte)
+        input wire[AUX_WIDTH - 1:0]  i_aux, //for AXI-interface compatibility (given upon strobe)
+        // Wishbone outputs
+        output wire o_wb_stall, //1 = busy, cannot accept requests
+        output wire o_wb_ack, //1 = read/write request has completed
+        output wire o_wb_err, //1 = Error due to ECC double bit error (fixed to 0 if WB_ERROR = 0)
+        output wire[wb_data_bits - 1:0] o_wb_data, //read data, for a 4:1 controller data width is 8 times the number of pins on the device
+        output wire[AUX_WIDTH - 1:0]  o_aux, //for AXI-interface compatibility (given upon strobe)
+        //
+        // Wishbone 2 (PHY) inputs
+        input wire i_wb2_cyc, //bus cycle active (1 = normal operation, 0 = all ongoing transaction are to be cancelled)
+        input wire i_wb2_stb, //request a transfer
+        input wire i_wb2_we, //write-enable (1 = write, 0 = read)
+        input wire[WB2_ADDR_BITS - 1:0] i_wb2_addr, // memory-mapped register to be accessed
+        input wire[WB2_DATA_BITS - 1:0] i_wb2_data, //write data
+        input wire[wb2_sel_bits - 1:0] i_wb2_sel, //byte strobe for write (1 = write the byte)
+        // Wishbone 2 (Controller) outputs
+        output wire o_wb2_stall, //1 = busy, cannot accept requests
+        output wire o_wb2_ack, //1 = read/write request has completed
+        output wire[WB2_DATA_BITS - 1:0] o_wb2_data, //read data
+        //
+        // DDR3 I/O Interface
+        output wire[DUAL_RANK_DIMM:0] o_ddr3_clk_p, o_ddr3_clk_n,
+        output wire o_ddr3_reset_n,
+        output wire[DUAL_RANK_DIMM:0] o_ddr3_cke, // CKE
+        output wire[DUAL_RANK_DIMM:0] o_ddr3_cs_n, // chip select signal
+        output wire o_ddr3_ras_n, // RAS#
+        output wire o_ddr3_cas_n, // CAS#
+        output wire o_ddr3_we_n, // WE#
+        output wire[ROW_BITS-1:0] o_ddr3_addr,
+        output wire[BA_BITS-1:0] o_ddr3_ba_addr,
+        inout wire[(DQ_BITS*BYTE_LANES)-1:0] io_ddr3_dq,
+        inout wire[BYTE_LANES-1:0] io_ddr3_dqs, io_ddr3_dqs_n,
+        output wire[BYTE_LANES-1:0] o_ddr3_dm,
+        output wire[DUAL_RANK_DIMM:0] o_ddr3_odt, // on-die termination
+        //
+        // Done Calibration pin
+        output wire o_calib_complete,
+        // Debug outputs
+        output wire[31:0] o_debug1,
+//        output wire[31:0] o_debug2,
+//        output wire[31:0] o_debug3,
+//        output wire[(DQ_BITS*BYTE_LANES)/8-1:0] o_ddr3_debug_read_dqs_p,
+//        output wire[(DQ_BITS*BYTE_LANES)/8-1:0] o_ddr3_debug_read_dqs_n
+        // 
+        // User enabled self-refresh
+        input wire i_user_self_refresh,
+        output wire uart_tx
+    );
+    
+// Instantiation Template (DEFAULT VALUE IS FOR ARTY S7)
+/*
+// DDR3 Controller 
+ddr3_top #(
+    .CONTROLLER_CLK_PERIOD(12_000), //ps, clock period of the controller interface
+    .DDR3_CLK_PERIOD(3_000), //ps, clock period of the DDR3 RAM device (must be 1/4 of the CONTROLLER_CLK_PERIOD) 
+    .ROW_BITS(14), //width of row address
+    .COL_BITS(10), //width of column address
+    .BA_BITS(3), //width of bank address
+    .BYTE_LANES(2), //number of byte lanes of DDR3 RAM
+    .AUX_WIDTH(4), //width of aux line (must be >= 4) 
+    .MICRON_SIM(0), //enable faster simulation for micron ddr3 model (shorten POWER_ON_RESET_HIGH and INITIAL_CKE_LOW)
+    .ODELAY_SUPPORTED(0), //set to 1 if ODELAYE2 is supported
+    .SECOND_WISHBONE(0), //set to 1 if 2nd wishbone for debugging is needed 
+    .ECC_ENABLE(0), // set to 1 or 2 to add ECC (1 = Side-band ECC per burst, 2 = Side-band ECC per 8 bursts , 3 = Inline ECC ) 
+    .WB_ERROR(0), // set to 1 to support Wishbone error (asserts at ECC double bit error)
+    ) ddr3_top
+    (
+        //clock and reset
+        .i_controller_clk(i_controller_clk),
+        .i_ddr3_clk(i_ddr3_clk), //i_controller_clk has period of CONTROLLER_CLK_PERIOD, i_ddr3_clk has period of DDR3_CLK_PERIOD 
+        .i_ref_clk(i_ref_clk), // usually set to 200 MHz 
+        .i_ddr3_clk_90(i_ddr3_clk_90), //90 degree phase shifted version i_ddr3_clk (required only when ODELAY_SUPPORTED is zero)
+        .i_rst_n(!i_rst && clk_locked), 
+        //
+        // Wishbone inputs
+        .i_wb_cyc(1), //bus cycle active (1 = normal operation, 0 = all ongoing transaction are to be cancelled)
+        .i_wb_stb(i_wb_stb), //request a transfer
+        .i_wb_we(i_wb_we), //write-enable (1 = write, 0 = read)
+        .i_wb_addr(i_wb_addr), //burst-addressable {row,bank,col} 
+        .i_wb_data(i_wb_data), //write data, for a 4:1 controller data width is 8 times the number of pins on the device
+        .i_wb_sel(16'hffff), //byte strobe for write (1 = write the byte)
+        .i_aux(i_wb_we), //for AXI-interface compatibility (given upon strobe)
+        // Wishbone outputs
+        .o_wb_stall(o_wb_stall), //1 = busy, cannot accept requests
+        .o_wb_ack(o_wb_ack), //1 = read/write request has completed
+        .o_wb_err(o_wb_err), //1 = Error due to ECC double bit error (fixed to 0 if WB_ERROR = 0)
+        .o_wb_data(o_wb_data), //read data, for a 4:1 controller data width is 8 times the number of pins on the device
+        .o_aux(o_aux),
+        //
+        // Wishbone 2 (PHY) inputs
+        .i_wb2_cyc(0), //bus cycle active (1 = normal operation, 0 = all ongoing transaction are to be cancelled)
+        .i_wb2_stb(0), //request a transfer
+        .i_wb2_we(0), //write-enable (1 = write, 0 = read)
+        .i_wb2_addr(0), //burst-addressable {row,bank,col} 
+        .i_wb2_data(0), //write data, for a 4:1 controller data width is 8 times the number of pins on the device
+        .i_wb2_sel(0), //byte strobe for write (1 = write the byte)
+        // Wishbone 2 (Controller) outputs
+        .o_wb2_stall(), //1 = busy, cannot accept requests
+        .o_wb2_ack(), //1 = read/write request has completed
+        .o_wb2_data(), //read data, for a 4:1 controller data width is 8 times the number of pins on the device
+        //
+        // DDR3 I/O Interface
+        .o_ddr3_clk_p(ddr3_clk_p), 
+        .o_ddr3_clk_n(ddr3_clk_n),
+        .o_ddr3_reset_n(ddr3_reset_n),
+        .o_ddr3_cke(ddr3_cke), 
+        .o_ddr3_cs_n(ddr3_cs_n), // width = number of DDR3 ranks
+        .o_ddr3_ras_n(ddr3_ras_n), 
+        .o_ddr3_cas_n(ddr3_cas_n), 
+        .o_ddr3_we_n(ddr3_we_n), 
+        .o_ddr3_addr(ddr3_addr), // width = ROW_BITS
+        .o_ddr3_ba_addr(ddr3_ba), // width = BA_BITS
+        .io_ddr3_dq(ddr3_dq), // width = BYTE_LANES*8
+        .io_ddr3_dqs(ddr3_dqs_p), // width = BYTE_LANES
+        .io_ddr3_dqs_n(ddr3_dqs_n), // width = BYTE_LANES
+        .o_ddr3_dm(ddr3_dm), // width = BYTE_LANES
+        .o_ddr3_odt(ddr3_odt),
+        // Debug outputs
+        .o_debug1(),
+        ////////////////////////////////////
+    );
+*/
+    
+    // Wire connections between controller and phy
+    wire[cmd_len*serdes_ratio-1:0] cmd;
+    wire dqs_tri_control, dq_tri_control;
+    wire toggle_dqs;
+    wire[wb_data_bits-1:0] data;
+    wire[wb_sel_bits-1:0] dm;
+    wire[BYTE_LANES-1:0] bitslip;
+    wire[DQ_BITS*BYTE_LANES*8-1:0] iserdes_data;
+    wire[BYTE_LANES*8-1:0] iserdes_dqs;
+    wire[BYTE_LANES*8-1:0] iserdes_bitslip_reference;
+    wire idelayctrl_rdy;
+    wire[4:0] odelay_data_cntvaluein, odelay_dqs_cntvaluein;
+    wire[4:0] idelay_data_cntvaluein, idelay_dqs_cntvaluein;
+    wire[BYTE_LANES-1:0] odelay_data_ld, odelay_dqs_ld;
+    wire[BYTE_LANES-1:0] idelay_data_ld, idelay_dqs_ld;
+    wire write_leveling_calib;
+    wire reset;
+    
+    // logic for self-refresh
+    reg[8:0] refresh_counter = 0;
+    reg user_self_refresh;
+    // refresh counter 
+    always @(posedge i_controller_clk) begin
+        if(i_wb_stb && i_wb_cyc) begin // if there is Wishbone request, then reset counter
+            refresh_counter <= 0;
+        end
+        else if(!o_wb_stall || user_self_refresh) begin // if no request (but not stalled) OR already on self-refresh, then increment counter
+            refresh_counter <= refresh_counter + 1;
+        end
+    end
+    // choose self-refresh options
+    always @* begin
+        case(SELF_REFRESH) 
+            2'b00: user_self_refresh = i_user_self_refresh; // use input i_user_self_refresh (high = enter self-refresh, low = exit self-refresh)
+            2'b01: user_self_refresh = refresh_counter[6];  // Self-refresh mode is enabled after 64 controller clock cycles of no requests, then exit Self-refresh after another 64 controller clk cycles
+            2'b10: user_self_refresh = refresh_counter[7];  // Self-refresh mode is enabled after 128 controller clock cycles of no requests, then exit Self-refresh after another 128 controller clk cycles
+            2'b11: user_self_refresh = refresh_counter[8];  // Self-refresh mode is enabled after 256 controller clock cycles of no requests, then exit Self-refresh after another 256 controller clk cycles
+        endcase
+    end
+    
+
+    
+    //module instantiations
+    ddr3_controller #(
+            .CONTROLLER_CLK_PERIOD(CONTROLLER_CLK_PERIOD), //ps, clock period of the controller interface
+            .DDR3_CLK_PERIOD(DDR3_CLK_PERIOD), //ps, clock period of the DDR3 RAM device (must be 1/4 of the CONTROLLER_CLK_PERIOD) 
+            .ROW_BITS(ROW_BITS), //width of row address
+            .COL_BITS(COL_BITS), //width of column address
+            .BA_BITS(BA_BITS), //width of bank address
+            .DQ_BITS(DQ_BITS),  //width of DQ
+            .LANES(BYTE_LANES), // byte lanes
+            .AUX_WIDTH(AUX_WIDTH), //width of aux line (must be >= 4) 
+            .WB2_ADDR_BITS(WB2_ADDR_BITS), //width of 2nd wishbone address bus 
+            .WB2_DATA_BITS(WB2_DATA_BITS),  //width of 2nd wishbone data bus
+            .MICRON_SIM(MICRON_SIM), //simulation for micron ddr3 model (shorten POWER_ON_RESET_HIGH and INITIAL_CKE_LOW)
+            .ODELAY_SUPPORTED(ODELAY_SUPPORTED),  //set to 1 when ODELAYE2 is supported
+            .SECOND_WISHBONE(SECOND_WISHBONE), //set to 1 if 2nd wishbone is needed 
+            .ECC_ENABLE(ECC_ENABLE), // set to 1 or 2 to add ECC (1 = Side-band ECC per burst, 2 = Side-band ECC per 8 bursts , 3 = Inline ECC ) 
+            .DLL_OFF(DLL_OFF), // 1 = DLL off for low frequency ddr3 clock (< 125MHz)
+            .WB_ERROR(WB_ERROR), // set to 1 to support Wishbone error (asserts at ECC double bit error)
+            .BIST_MODE(BIST_MODE), // 0 = No BIST, 1 = run through all address space ONCE , 2 = run through all address space for every test (burst w/r, random w/r, alternating r/w)
+            .BIST_TEST_DATAMASK(BIST_TEST_DATAMASK), // 1 = include per-byte DM writes in BIST, 0 = all-byte writes only
+            .DIC(DIC), //Output Driver Impedance Control (2'b00 = RZQ/6, 2'b01 = RZQ/7, RZQ = 240ohms)
+            .RTT_NOM(RTT_NOM), //RTT Nominal (3'b000 = disabled, 3'b001 = RZQ/4, 3'b010 = RZQ/2 , 3'b011 = RZQ/6, RZQ = 240ohms)
+            .DUAL_RANK_DIMM(DUAL_RANK_DIMM), // enable dual rank DIMM (1 =  enable, 0 = disable)
+            .SPEED_BIN(SPEED_BIN), // 0 = Use top-level parameters , 1 = DDR3-1066 (7-7-7) , 2 = DR3-1333 (9-9-9) , 3 = DDR3-1600 (11-11-11)
+            .SDRAM_CAPACITY(SDRAM_CAPACITY), // 0 = 256Mb, 1 = 512Mb, 2 = 1Gb, 3 = 2Gb, 4 = 4Gb, 5 = 8Gb, 6 = 16Gb
+            .TRCD(TRCD), // ps Active to Read/Write command time (only used if SPEED_BIN = 0)
+            .TRP(TRP), // ps Precharge command period (only used if SPEED_BIN = 0)
+            .TRAS(TRAS) // ps ACT to PRE command period (only used if SPEED_BIN = 0)
+        ) ddr3_controller_inst (
+            .i_controller_clk(i_controller_clk), //i_controller_clk has period of CONTROLLER_CLK_PERIOD 
+            .i_rst_n(i_rst_n), //200MHz input clock
+            // Wishbone inputs
+            .i_wb_cyc(i_wb_cyc), //bus cycle active (1 = normal operation, 0 = all ongoing transaction are to be cancelled)
+            .i_wb_stb(i_wb_stb), //request a transfer
+            .i_wb_we(i_wb_we), //write-enable (1 = write, 0 = read)
+            .i_wb_addr(i_wb_addr), //burst-addressable {row,bank,col} 
+            .i_wb_data(i_wb_data), //write data, for a 4:1 controller data width is 8 times the number of pins on the device
+            .i_wb_sel(i_wb_sel), //byte strobe for write (1 = write the byte)
+            .i_aux(i_aux), //for AXI-interface compatibility (given upon strobe)
+            // Wishbone outputs
+            .o_wb_stall(o_wb_stall), //1 = busy, cannot accept requests
+            .o_wb_ack(o_wb_ack), //1 = read/write request has completed
+            .o_wb_err(o_wb_err), //1 = Error due to ECC double bit error (fixed to 0 if WB_ERROR = 0)
+            .o_wb_data(o_wb_data), //read data, for a 4:1 controller data width is 8 times the number of pins on the device
+            .o_aux(o_aux), //for AXI-interface compatibility (returned upon ack)
+            // Wishbone 2 (PHY) inputs
+            .i_wb2_cyc(i_wb2_cyc), //bus cycle active (1 = normal operation, 0 = all ongoing transaction are to be cancelled)
+            .i_wb2_stb(i_wb2_stb), //request a transfer
+            .i_wb2_we(i_wb2_we), //write-enable (1 = write, 0 = read)
+            .i_wb2_addr(i_wb2_addr), // memory-mapped register to be accessed 
+            .i_wb2_data(i_wb2_data), //write data
+            .i_wb2_sel(i_wb2_sel), //byte strobe for write (1 = write the byte)
+            // Wishbone 2 (Controller) outputs
+            .o_wb2_stall(o_wb2_stall), //1 = busy, cannot accept requests
+            .o_wb2_ack(o_wb2_ack), //1 = read/write request has completed
+            .o_wb2_data(o_wb2_data), //read data
+            //
+            // PHY interface
+            .i_phy_iserdes_data(iserdes_data),
+            .i_phy_iserdes_dqs(iserdes_dqs),
+            .i_phy_iserdes_bitslip_reference(iserdes_bitslip_reference),
+            .i_phy_idelayctrl_rdy(idelayctrl_rdy),
+            .o_phy_cmd(cmd),
+            .o_phy_dqs_tri_control(dqs_tri_control), 
+            .o_phy_dq_tri_control(dq_tri_control),
+            .o_phy_toggle_dqs(toggle_dqs),
+            .o_phy_data(data),
+            .o_phy_dm(dm),
+            .o_phy_odelay_data_cntvaluein(odelay_data_cntvaluein),
+            .o_phy_odelay_dqs_cntvaluein(odelay_dqs_cntvaluein),
+            .o_phy_idelay_data_cntvaluein(idelay_data_cntvaluein), 
+            .o_phy_idelay_dqs_cntvaluein(idelay_dqs_cntvaluein),
+            .o_phy_odelay_data_ld(odelay_data_ld),
+            .o_phy_odelay_dqs_ld(odelay_dqs_ld),
+            .o_phy_idelay_data_ld(idelay_data_ld), 
+            .o_phy_idelay_dqs_ld(idelay_dqs_ld),
+            .o_phy_bitslip(bitslip),
+            .o_phy_write_leveling_calib(write_leveling_calib),
+            .o_phy_reset(reset),
+            // Done Calibration pin
+            .o_calib_complete(o_calib_complete),
+            // Debug outputs
+            .o_debug1(o_debug1),
+//            .o_debug2(o_debug2),
+//            .o_debug3(o_debug3)
+            // User enabled self-refresh
+            .i_user_self_refresh(user_self_refresh),
+            .uart_tx(uart_tx)
+        );
+    `ifndef LATTICE_ECP5_PHY // XILINX PHY
+        ddr3_phy #(
+                .ROW_BITS(ROW_BITS), //width of row address
+                .BA_BITS(BA_BITS), //width of bank address
+                .DQ_BITS(DQ_BITS),  //width of DQ
+                .LANES(BYTE_LANES), //8 lanes of DQ
+                .CONTROLLER_CLK_PERIOD(CONTROLLER_CLK_PERIOD), //ps, period of clock input to this DDR3 controller module
+                .DDR3_CLK_PERIOD(DDR3_CLK_PERIOD), //ps, period of clock input to DDR3 RAM device 
+                .ODELAY_SUPPORTED(ODELAY_SUPPORTED), //set to 1 when ODELAYE2 is supported
+                .DUAL_RANK_DIMM(DUAL_RANK_DIMM) // enable dual rank DIMM (1 =  enable, 0 = disable)
+            ) ddr3_phy_inst (
+                .i_controller_clk(i_controller_clk), 
+                .i_ddr3_clk(i_ddr3_clk),
+                .i_ref_clk(i_ref_clk),
+                .i_ddr3_clk_90(i_ddr3_clk_90), 
+                .i_rst_n(i_rst_n),
+                // Controller Interface
+                .i_controller_reset(reset),
+                .i_controller_cmd(cmd),
+                .i_controller_dqs_tri_control(dqs_tri_control), 
+                .i_controller_dq_tri_control(dq_tri_control),
+                .i_controller_toggle_dqs(toggle_dqs),
+                .i_controller_data(data),
+                .i_controller_dm(dm),
+                .i_controller_odelay_data_cntvaluein(odelay_data_cntvaluein),
+                .i_controller_odelay_dqs_cntvaluein(odelay_dqs_cntvaluein),
+                .i_controller_idelay_data_cntvaluein(idelay_data_cntvaluein),
+                .i_controller_idelay_dqs_cntvaluein(idelay_dqs_cntvaluein),
+                .i_controller_odelay_data_ld(odelay_data_ld), 
+                .i_controller_odelay_dqs_ld(odelay_dqs_ld),
+                .i_controller_idelay_data_ld(idelay_data_ld), 
+                .i_controller_idelay_dqs_ld(idelay_dqs_ld),
+                .i_controller_bitslip(bitslip),
+                .i_controller_write_leveling_calib(write_leveling_calib),
+                .o_controller_iserdes_data(iserdes_data),
+                .o_controller_iserdes_dqs(iserdes_dqs),
+                .o_controller_iserdes_bitslip_reference(iserdes_bitslip_reference),
+                .o_controller_idelayctrl_rdy(idelayctrl_rdy),
+                // DDR3 I/O Interface
+                .o_ddr3_clk_p(o_ddr3_clk_p),
+                .o_ddr3_clk_n(o_ddr3_clk_n),
+                .o_ddr3_reset_n(o_ddr3_reset_n),
+                .o_ddr3_cke(o_ddr3_cke), // CKE
+                .o_ddr3_cs_n(o_ddr3_cs_n), // chip select signal
+                .o_ddr3_ras_n(o_ddr3_ras_n), // RAS#
+                .o_ddr3_cas_n(o_ddr3_cas_n), // CAS#
+                .o_ddr3_we_n(o_ddr3_we_n), // WE#
+                .o_ddr3_addr(o_ddr3_addr),
+                .o_ddr3_ba_addr(o_ddr3_ba_addr),
+                .io_ddr3_dq(io_ddr3_dq),
+                .io_ddr3_dqs(io_ddr3_dqs),
+                .io_ddr3_dqs_n(io_ddr3_dqs_n),
+                .o_ddr3_dm(o_ddr3_dm),
+                .o_ddr3_odt(o_ddr3_odt), // on-die termination
+                .o_ddr3_debug_read_dqs_p(/*o_ddr3_debug_read_dqs_p*/),
+                .o_ddr3_debug_read_dqs_n(/*o_ddr3_debug_read_dqs_n*/)
+            );
+    `else // LATTICE ECP5 PHY
+        ddr3_phy_ecp5 #(
+                .ROW_BITS(ROW_BITS), //width of row address
+                .BA_BITS(BA_BITS), //width of bank address
+                .DQ_BITS(DQ_BITS),  //width of DQ
+                .LANES(BYTE_LANES), //8 lanes of DQ
+                .CONTROLLER_CLK_PERIOD(CONTROLLER_CLK_PERIOD) //ps, period of clock input to this DDR3 controller module
+            ) ddr3_phy_inst (
+                .i_controller_clk(i_controller_clk), 
+                .i_ddr3_clk(i_ddr3_clk),
+                .i_ref_clk(i_ref_clk),
+                .i_ddr3_clk_90(i_ddr3_clk_90), 
+                .i_rst_n(i_rst_n),
+                // Controller Interface
+                .i_controller_reset(reset),
+                .i_controller_cmd(cmd),
+                .i_controller_dqs_tri_control(dqs_tri_control), 
+                .i_controller_dq_tri_control(dq_tri_control),
+                .i_controller_toggle_dqs(toggle_dqs),
+                .i_controller_data(data),
+                .i_controller_dm(dm),
+                .i_controller_odelay_data_cntvaluein(odelay_data_cntvaluein),
+                .i_controller_odelay_dqs_cntvaluein(odelay_dqs_cntvaluein),
+                .i_controller_idelay_data_cntvaluein(idelay_data_cntvaluein),
+                .i_controller_idelay_dqs_cntvaluein(idelay_dqs_cntvaluein),
+                .i_controller_odelay_data_ld(odelay_data_ld), 
+                .i_controller_odelay_dqs_ld(odelay_dqs_ld),
+                .i_controller_idelay_data_ld(idelay_data_ld), 
+                .i_controller_idelay_dqs_ld(idelay_dqs_ld),
+                .i_controller_bitslip(bitslip),
+                .i_controller_write_leveling_calib(write_leveling_calib),
+                .o_controller_iserdes_data(iserdes_data),
+                .o_controller_iserdes_dqs(iserdes_dqs),
+                .o_controller_iserdes_bitslip_reference(iserdes_bitslip_reference),
+                .o_controller_idelayctrl_rdy(idelayctrl_rdy),
+                // DDR3 I/O Interface
+                .o_ddr3_clk_p(o_ddr3_clk_p),
+                .o_ddr3_clk_n(o_ddr3_clk_n),
+                .o_ddr3_reset_n(o_ddr3_reset_n),
+                .o_ddr3_cke(o_ddr3_cke), // CKE
+                .o_ddr3_cs_n(o_ddr3_cs_n), // chip select signal
+                .o_ddr3_ras_n(o_ddr3_ras_n), // RAS#
+                .o_ddr3_cas_n(o_ddr3_cas_n), // CAS#
+                .o_ddr3_we_n(o_ddr3_we_n), // WE#
+                .o_ddr3_addr(o_ddr3_addr),
+                .o_ddr3_ba_addr(o_ddr3_ba_addr),
+                .io_ddr3_dq(io_ddr3_dq),
+                .io_ddr3_dqs(io_ddr3_dqs),
+                .io_ddr3_dqs_n(io_ddr3_dqs_n),
+                .o_ddr3_dm(o_ddr3_dm),
+                .o_ddr3_odt(o_ddr3_odt), // on-die termination
+                .o_ddr3_debug_read_dqs_p(/*o_ddr3_debug_read_dqs_p*/),
+                .o_ddr3_debug_read_dqs_n(/*o_ddr3_debug_read_dqs_n*/)
+            );
+    `endif 
+
+        // // display value of parameters for easy debugging
+        // initial begin
+        //     $display("\nDDR3 TOP PARAMETERS:\n-----------------------------");
+        //     $display("CONTROLLER_CLK_PERIOD = %0d", CONTROLLER_CLK_PERIOD);
+        //     $display("DDR3_CLK_PERIOD = %0d", DDR3_CLK_PERIOD);
+        //     $display("ROW_BITS = %0d", ROW_BITS);
+        //     $display("COL_BITS = %0d", COL_BITS);
+        //     $display("BA_BITS = %0d", BA_BITS);
+        //     $display("BYTE_LANES = %0d", BYTE_LANES);
+        //     $display("AUX_WIDTH = %0d", AUX_WIDTH);
+        //     $display("WB2_ADDR_BITS = %0d", WB2_ADDR_BITS);
+        //     $display("WB2_DATA_BITS = %0d", WB2_DATA_BITS);
+        //     $display("MICRON_SIM = %0d", MICRON_SIM);
+        //     $display("ODELAY_SUPPORTED = %0d", ODELAY_SUPPORTED);
+        //     $display("SECOND_WISHBONE = %0d", SECOND_WISHBONE);
+        //     $display("WB_ERROR = %0d", WB_ERROR);
+        //     $display("BIST_MODE = %0d", BIST_MODE);
+        //     $display("ECC_ENABLE = %0d", ECC_ENABLE);
+        //     $display("DIC = %0d", DIC);
+        //     $display("RTT_NOM = %0d", RTT_NOM);
+        //     $display("SELF_REFRESH = %0d", SELF_REFRESH);
+        //     $display("DUAL_RANK_DIMM = %0d", DUAL_RANK_DIMM);
+        //     $display("End of DDR3 TOP PARAMETERS\n-----------------------------");
+        // end
+
+endmodule

AngeloJacobo_UberDDR3/example_demo/alinx_ax7103b/uart_rx.v

@@ -0,0 +1,207 @@
+
+// 
+// Module: uart_rx 
+// 
+// Notes:
+// - UART reciever module.
+//
+
+module uart_rx(
+input  wire       clk          , // Top level system clock input.
+input  wire       resetn       , // Asynchronous active low reset.
+input  wire       uart_rxd     , // UART Recieve pin.
+input  wire       uart_rx_en   , // Recieve enable
+output wire       uart_rx_break, // Did we get a BREAK message?
+output wire       uart_rx_valid, // Valid data recieved and available.
+output reg  [PAYLOAD_BITS-1:0] uart_rx_data   // The recieved data.
+);
+
+// --------------------------------------------------------------------------- 
+// External parameters.
+// 
+
+//
+// Input bit rate of the UART line.
+parameter   BIT_RATE        = 9600; // bits / sec
+localparam  BIT_P           = 1_000_000_000 * 1/BIT_RATE; // nanoseconds
+
+//
+// Clock frequency in hertz.
+parameter   CLK_HZ          =    50_000_000;
+localparam  CLK_P           = 1_000_000_000 * 1/CLK_HZ; // nanoseconds
+
+//
+// Number of data bits recieved per UART packet.
+parameter   PAYLOAD_BITS    = 8;
+
+//
+// Number of stop bits indicating the end of a packet.
+parameter   STOP_BITS       = 1;
+
+// -------------------------------------------------------------------------- 
+// Internal parameters.
+// 
+
+//
+// Number of clock cycles per uart bit.
+localparam       CYCLES_PER_BIT     = BIT_P / CLK_P;
+
+//
+// Size of the registers which store sample counts and bit durations.
+localparam       COUNT_REG_LEN      = 1+$clog2(CYCLES_PER_BIT);
+
+// -------------------------------------------------------------------------- 
+// Internal registers.
+// 
+
+//
+// Internally latched value of the uart_rxd line. Helps break long timing
+// paths from input pins into the logic.
+reg rxd_reg;
+reg rxd_reg_0;
+
+//
+// Storage for the recieved serial data.
+reg [PAYLOAD_BITS-1:0] recieved_data;
+
+//
+// Counter for the number of cycles over a packet bit.
+reg [COUNT_REG_LEN-1:0] cycle_counter;
+
+//
+// Counter for the number of recieved bits of the packet.
+reg [3:0] bit_counter;
+
+//
+// Sample of the UART input line whenever we are in the middle of a bit frame.
+reg bit_sample;
+
+//
+// Current and next states of the internal FSM.
+reg [2:0] fsm_state;
+reg [2:0] n_fsm_state;
+
+localparam FSM_IDLE = 0;
+localparam FSM_START= 1;
+localparam FSM_RECV = 2;
+localparam FSM_STOP = 3;
+
+// --------------------------------------------------------------------------- 
+// Output assignment
+// 
+
+assign uart_rx_break = uart_rx_valid && ~|recieved_data;
+assign uart_rx_valid = fsm_state == FSM_STOP && n_fsm_state == FSM_IDLE;
+
+always @(posedge clk) begin
+    if(!resetn) begin
+        uart_rx_data  <= {PAYLOAD_BITS{1'b0}};
+    end else if (fsm_state == FSM_STOP) begin
+        uart_rx_data  <= recieved_data;
+    end
+end
+
+// --------------------------------------------------------------------------- 
+// FSM next state selection.
+// 
+
+wire next_bit     = cycle_counter == CYCLES_PER_BIT ||
+                        fsm_state       == FSM_STOP && 
+                        cycle_counter   == CYCLES_PER_BIT/2;
+wire payload_done = bit_counter   == PAYLOAD_BITS  ;
+
+//
+// Handle picking the next state.
+always @(*) begin : p_n_fsm_state
+    case(fsm_state)
+        FSM_IDLE : n_fsm_state = rxd_reg      ? FSM_IDLE : FSM_START;
+        FSM_START: n_fsm_state = next_bit     ? FSM_RECV : FSM_START;
+        FSM_RECV : n_fsm_state = payload_done ? FSM_STOP : FSM_RECV ;
+        FSM_STOP : n_fsm_state = next_bit     ? FSM_IDLE : FSM_STOP ;
+        default  : n_fsm_state = FSM_IDLE;
+    endcase
+end
+
+// --------------------------------------------------------------------------- 
+// Internal register setting and re-setting.
+// 
+
+//
+// Handle updates to the recieved data register.
+integer i = 0;
+always @(posedge clk) begin : p_recieved_data
+    if(!resetn) begin
+        recieved_data <= {PAYLOAD_BITS{1'b0}};
+    end else if(fsm_state == FSM_IDLE             ) begin
+        recieved_data <= {PAYLOAD_BITS{1'b0}};
+    end else if(fsm_state == FSM_RECV && next_bit ) begin
+        recieved_data[PAYLOAD_BITS-1] <= bit_sample;
+        for ( i = PAYLOAD_BITS-2; i >= 0; i = i - 1) begin
+            recieved_data[i] <= recieved_data[i+1];
+        end
+    end
+end
+
+//
+// Increments the bit counter when recieving.
+always @(posedge clk) begin : p_bit_counter
+    if(!resetn) begin
+        bit_counter <= 4'b0;
+    end else if(fsm_state != FSM_RECV) begin
+        bit_counter <= {COUNT_REG_LEN{1'b0}};
+    end else if(fsm_state == FSM_RECV && next_bit) begin
+        bit_counter <= bit_counter + 1'b1;
+    end
+end
+
+//
+// Sample the recieved bit when in the middle of a bit frame.
+always @(posedge clk) begin : p_bit_sample
+    if(!resetn) begin
+        bit_sample <= 1'b0;
+    end else if (cycle_counter == CYCLES_PER_BIT/2) begin
+        bit_sample <= rxd_reg;
+    end
+end
+
+
+//
+// Increments the cycle counter when recieving.
+always @(posedge clk) begin : p_cycle_counter
+    if(!resetn) begin
+        cycle_counter <= {COUNT_REG_LEN{1'b0}};
+    end else if(next_bit) begin
+        cycle_counter <= {COUNT_REG_LEN{1'b0}};
+    end else if(fsm_state == FSM_START || 
+                fsm_state == FSM_RECV  || 
+                fsm_state == FSM_STOP   ) begin
+        cycle_counter <= cycle_counter + 1'b1;
+    end
+end
+
+
+//
+// Progresses the next FSM state.
+always @(posedge clk) begin : p_fsm_state
+    if(!resetn) begin
+        fsm_state <= FSM_IDLE;
+    end else begin
+        fsm_state <= n_fsm_state;
+    end
+end
+
+
+//
+// Responsible for updating the internal value of the rxd_reg.
+always @(posedge clk) begin : p_rxd_reg
+    if(!resetn) begin
+        rxd_reg     <= 1'b1;
+        rxd_reg_0   <= 1'b1;
+    end else if(uart_rx_en) begin
+        rxd_reg     <= rxd_reg_0;
+        rxd_reg_0   <= uart_rxd;
+    end
+end
+
+
+endmodule

AngeloJacobo_UberDDR3/example_demo/alinx_ax7103b/uart_tx.v

@@ -0,0 +1,187 @@
+
+
+// 
+// Module: uart_tx 
+// 
+// Notes:
+// - UART transmitter module.
+//
+
+module uart_tx(
+input  wire         clk         , // Top level system clock input.
+input  wire         resetn      , // Asynchronous active low reset.
+output wire         uart_txd    , // UART transmit pin.
+output wire         uart_tx_busy, // Module busy sending previous item.
+input  wire         uart_tx_en  , // Send the data on uart_tx_data
+input  wire [PAYLOAD_BITS-1:0]   uart_tx_data  // The data to be sent
+);
+
+// --------------------------------------------------------------------------- 
+// External parameters.
+// 
+
+//
+// Input bit rate of the UART line.
+parameter   BIT_RATE        = 9600; // bits / sec
+localparam  BIT_P           = 1_000_000_000 * 1/BIT_RATE; // nanoseconds
+
+//
+// Clock frequency in hertz.
+parameter   CLK_HZ          =    50_000_000;
+localparam  CLK_P           = 1_000_000_000 * 1/CLK_HZ; // nanoseconds
+
+//
+// Number of data bits recieved per UART packet.
+parameter   PAYLOAD_BITS    = 8;
+
+//
+// Number of stop bits indicating the end of a packet.
+parameter   STOP_BITS       = 1;
+
+// --------------------------------------------------------------------------- 
+// Internal parameters.
+// 
+
+//
+// Number of clock cycles per uart bit.
+localparam       CYCLES_PER_BIT     = BIT_P / CLK_P;
+
+//
+// Size of the registers which store sample counts and bit durations.
+localparam       COUNT_REG_LEN      = 1+$clog2(CYCLES_PER_BIT);
+
+// --------------------------------------------------------------------------- 
+// Internal registers.
+// 
+
+//
+// Internally latched value of the uart_txd line. Helps break long timing
+// paths from the logic to the output pins.
+reg txd_reg;
+
+//
+// Storage for the serial data to be sent.
+reg [PAYLOAD_BITS-1:0] data_to_send;
+
+//
+// Counter for the number of cycles over a packet bit.
+reg [COUNT_REG_LEN-1:0] cycle_counter;
+
+//
+// Counter for the number of sent bits of the packet.
+reg [3:0] bit_counter;
+
+//
+// Current and next states of the internal FSM.
+reg [2:0] fsm_state;
+reg [2:0] n_fsm_state;
+
+localparam FSM_IDLE = 0;
+localparam FSM_START= 1;
+localparam FSM_SEND = 2;
+localparam FSM_STOP = 3;
+
+
+// --------------------------------------------------------------------------- 
+// FSM next state selection.
+// 
+
+assign uart_tx_busy = fsm_state != FSM_IDLE;
+assign uart_txd     = txd_reg;
+
+wire next_bit     = cycle_counter == CYCLES_PER_BIT;
+wire payload_done = bit_counter   == PAYLOAD_BITS  ;
+wire stop_done    = bit_counter   == STOP_BITS && fsm_state == FSM_STOP;
+
+//
+// Handle picking the next state.
+always @(*) begin : p_n_fsm_state
+    case(fsm_state)
+        FSM_IDLE : n_fsm_state = uart_tx_en   ? FSM_START: FSM_IDLE ;
+        FSM_START: n_fsm_state = next_bit     ? FSM_SEND : FSM_START;
+        FSM_SEND : n_fsm_state = payload_done ? FSM_STOP : FSM_SEND ;
+        FSM_STOP : n_fsm_state = stop_done    ? FSM_IDLE : FSM_STOP ;
+        default  : n_fsm_state = FSM_IDLE;
+    endcase
+end
+
+// --------------------------------------------------------------------------- 
+// Internal register setting and re-setting.
+// 
+
+//
+// Handle updates to the sent data register.
+integer i = 0;
+always @(posedge clk) begin : p_data_to_send
+    if(!resetn) begin
+        data_to_send <= {PAYLOAD_BITS{1'b0}};
+    end else if(fsm_state == FSM_IDLE && uart_tx_en) begin
+        data_to_send <= uart_tx_data;
+    end else if(fsm_state       == FSM_SEND       && next_bit ) begin
+        for ( i = PAYLOAD_BITS-2; i >= 0; i = i - 1) begin
+            data_to_send[i] <= data_to_send[i+1];
+        end
+    end
+end
+
+
+//
+// Increments the bit counter each time a new bit frame is sent.
+always @(posedge clk) begin : p_bit_counter
+    if(!resetn) begin
+        bit_counter <= 4'b0;
+    end else if(fsm_state != FSM_SEND && fsm_state != FSM_STOP) begin
+        bit_counter <= {COUNT_REG_LEN{1'b0}};
+    end else if(fsm_state == FSM_SEND && n_fsm_state == FSM_STOP) begin
+        bit_counter <= {COUNT_REG_LEN{1'b0}};
+    end else if(fsm_state == FSM_STOP&& next_bit) begin
+        bit_counter <= bit_counter + 1'b1;
+    end else if(fsm_state == FSM_SEND && next_bit) begin
+        bit_counter <= bit_counter + 1'b1;
+    end
+end
+
+
+//
+// Increments the cycle counter when sending.
+always @(posedge clk) begin : p_cycle_counter
+    if(!resetn) begin
+        cycle_counter <= {COUNT_REG_LEN{1'b0}};
+    end else if(next_bit) begin
+        cycle_counter <= {COUNT_REG_LEN{1'b0}};
+    end else if(fsm_state == FSM_START || 
+                fsm_state == FSM_SEND  || 
+                fsm_state == FSM_STOP   ) begin
+        cycle_counter <= cycle_counter + 1'b1;
+    end
+end
+
+
+//
+// Progresses the next FSM state.
+always @(posedge clk) begin : p_fsm_state
+    if(!resetn) begin
+        fsm_state <= FSM_IDLE;
+    end else begin
+        fsm_state <= n_fsm_state;
+    end
+end
+
+
+//
+// Responsible for updating the internal value of the txd_reg.
+always @(posedge clk) begin : p_txd_reg
+    if(!resetn) begin
+        txd_reg <= 1'b1;
+    end else if(fsm_state == FSM_IDLE) begin
+        txd_reg <= 1'b1;
+    end else if(fsm_state == FSM_START) begin
+        txd_reg <= 1'b0;
+    end else if(fsm_state == FSM_SEND) begin
+        txd_reg <= data_to_send[0];
+    end else if(fsm_state == FSM_STOP) begin
+        txd_reg <= 1'b1;
+    end
+end
+
+endmodule

AngeloJacobo_UberDDR3/example_demo/alinx_ax7325b/Makefile

@@ -0,0 +1,115 @@
+PROJECT = ax7325b_ddr3
+FAMILY = kintex7
+PART = xc7k325tffg900-2
+CHIPDB  = ${KINTEX7_CHIPDB}
+ADDITIONAL_SOURCES = ../../rtl/ddr3_controller.v  ../../rtl/ddr3_phy.v  ../../rtl/ddr3_top.v  uart_rx.v  uart_tx.v clk_wiz.v 
+
+
+#############################################################################################
+NEXTPNR_XILINX_DIR ?= /snap/openxc7/current/opt/nextpnr-xilinx
+NEXTPNR_XILINX_PYTHON_DIR ?= ${NEXTPNR_XILINX_DIR}/python
+PRJXRAY_DB_DIR ?= ${NEXTPNR_XILINX_DIR}/external/prjxray-db
+
+DBPART = $(shell echo ${PART} | sed -e 's/-[0-9]//g')
+SPEEDGRADE = $(shell echo ${PART} | sed -e 's/.*\-\([0-9]\)/\1/g')
+
+CHIPDB ?= ./
+ifeq ($(CHIPDB),)
+CHIPDB = ./
+endif
+
+PYPY3 ?= pypy3
+
+TOP ?= ${PROJECT}
+TOP_MODULE ?= ${TOP}
+TOP_VERILOG ?= ${TOP}.v
+
+PNR_DEBUG ?= # --verbose --debug
+
+JTAG_LINK ?= -c digilent_hs2
+
+XDC ?= ${PROJECT}.xdc
+
+.PHONY: openxc7
+openxc7: ${PROJECT}_openxc7.bit
+
+.PHONY: program
+program: ${PROJECT}_openxc7.bit
+	openFPGALoader ${JTAG_LINK} --bitstream $<
+
+${PROJECT}.json: ${TOP_VERILOG} ${ADDITIONAL_SOURCES}
+	yosys -p "synth_xilinx -flatten -abc9 ${SYNTH_OPTS} -arch xc7 -top ${TOP_MODULE}; write_json ${PROJECT}.json" $< ${ADDITIONAL_SOURCES}
+
+# The chip database only needs to be generated once
+# that is why we don't clean it with make clean
+${CHIPDB}/${DBPART}.bin:
+	${PYPY3} ${NEXTPNR_XILINX_PYTHON_DIR}/bbaexport.py --device ${PART} --bba ${DBPART}.bba
+	bbasm -l ${DBPART}.bba ${CHIPDB}/${DBPART}.bin
+	rm -f ${DBPART}.bba
+
+${PROJECT}.fasm: ${PROJECT}.json ${CHIPDB}/${DBPART}.bin ${XDC}
+	nextpnr-xilinx --chipdb ${CHIPDB}/${DBPART}.bin --xdc ${XDC} --json ${PROJECT}.json --fasm $@ ${PNR_ARGS} ${PNR_DEBUG}
+	
+${PROJECT}.frames: ${PROJECT}.fasm
+	fasm2frames --part ${PART} --db-root ${PRJXRAY_DB_DIR}/${FAMILY} $< > $@
+
+${PROJECT}_openxc7.bit: ${PROJECT}.frames
+	xc7frames2bit --part_file ${PRJXRAY_DB_DIR}/${FAMILY}/${PART}/part.yaml --part_name ${PART} --frm_file $< --output_file $@
+
+
+#############################################################################################
+# SPDX-License-Identifier: MIT
+# Generated from https://github.com/FPGAOL-CE/caas-wizard
+#
+BUILDDIR := ${CURDIR}/build
+
+LOGFILE := ${BUILDDIR}/top.log
+
+# Build design
+.PHONY: vivado
+vivado: ${BUILDDIR}/${PROJECT}_vivado.bit
+
+${BUILDDIR}:
+	mkdir -m 777 -p ${BUILDDIR} && chown -R nobody ${BUILDDIR} | true
+
+.ONESHELL: 
+${BUILDDIR}/vivado.tcl: ${BUILDDIR}
+	cat << EOF > $@
+	# vivado.tcl generated for FPGAOL-CE/caas-wizard
+	# can be launched from any directory
+	cd ${BUILDDIR}
+	create_project -part ${PART} -force v_proj
+	set_property target_language Verilog [current_project]
+	cd ..
+	read_verilog [glob ${PROJECT}.v ${ADDITIONAL_SOURCES}]
+	read_xdc [glob  $(wildcard ${PROJECT}.xdc) ]
+	cd build
+	synth_design -top ${PROJECT}
+	opt_design
+	place_design
+	phys_opt_design
+	route_design
+	write_bitstream -verbose -force ${PROJECT}_vivado.bit
+	# report_utilization -file util.rpt
+	# report_timing_summary -file timing.rpt
+	EOF
+
+${BUILDDIR}/${PROJECT}_vivado.bit: ${BUILDDIR}/vivado.tcl
+	cd ${BUILDDIR} && vivado -mode batch -source $< > ${LOGFILE} 2>&1
+
+.PHONY: program_vivado
+program_vivado: 
+	openFPGALoader ${JTAG_LINK} --bitstream ${BUILDDIR}/${PROJECT}_vivado.bit
+
+
+#############################################################################################
+
+.PHONY: clean
+clean:
+	rm -f *.bit
+	rm -f *.frames
+	rm -f *.fasm
+	rm -f *.json
+	rm -f *.bin
+	rm -f *.bba
+	rm -rf ${BUILDDIR}

AngeloJacobo_UberDDR3/example_demo/alinx_ax7325b/ax7325b_ddr3.v

@@ -0,0 +1,236 @@
+////////////////////////////////////////////////////////////////////////////////
+//
+// Filename: ax7325b_ddr3.v
+// Project: UberDDR3 - An Open Source DDR3 Controller
+//
+// Purpose: Example demo of UberDDR3 for AX7325B FPGA board from ALINX (xc7k325tffg900-2).
+//          Mechanism:
+//          - four LEDs will light up once UberDDR3 is done calibrating
+//          - if UART (9600 Baud Rate)receives small letter ASCII (a-z), this value will be written to DDR3 
+//          - if UART receives capital letter ASCII (A-Z), the small letter equivalent will be retrieved from DDR3 by doing
+//          - a read request, once read data is available this will be sent to UART to be streamed out.
+//          THUS:
+//          - Sendng "abcdefg" to the UART terminal will store that small latter to DDR3
+//          - Then sending "ABCDEFG" to the UART terminal will return the small letter equivalent: "abcdefg"
+//
+// Engineer: Angelo C. Jacobo
+//
+////////////////////////////////////////////////////////////////////////////////
+//
+// Copyright (C) 2023-2025  Angelo Jacobo
+// 
+//     This program is free software: you can redistribute it and/or modify
+//     it under the terms of the GNU General Public License as published by
+//     the Free Software Foundation, either version 3 of the License, or
+//     (at your option) any later version.
+// 
+//     This program is distributed in the hope that it will be useful,
+//     but WITHOUT ANY WARRANTY; without even the implied warranty of
+//     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//     GNU General Public License for more details.
+// 
+//     You should have received a copy of the GNU General Public License
+//     along with this program.  If not, see <https://www.gnu.org/licenses/>.
+//
+////////////////////////////////////////////////////////////////////////////////
+
+`timescale 1ns / 1ps
+
+   module ax7325b_ddr3
+	(
+	    //Differential system clocks   
+        input wire sys_clk_p, sys_clk_n, 
+        input wire i_rst_n,
+        output wire fan_pwm,
+        // DDR3 I/O Interface
+        output wire ddr3_ck_p, ddr3_ck_n,
+        output wire ddr3_reset_n,
+        output wire ddr3_cke, 
+        output wire ddr3_cs_n, 
+        output wire ddr3_ras_n, 
+        output wire ddr3_cas_n, 
+        output wire ddr3_we_n,
+        output wire[15-1:0] ddr3_addr,
+        output wire[3-1:0] ddr3_ba,
+        inout wire[64-1:0] ddr3_dq,
+        inout wire[8-1:0] ddr3_dqs_p, ddr3_dqs_n,
+        output wire[8-1:0] ddr3_dm,
+        output wire ddr3_odt, 
+        // UART line
+        input wire rx,
+        output wire tx,
+        //Debug LEDs
+        output wire[3:0] led
+    );
+    // for dual-rank, all [0:0] will become [1:0]
+     wire i_controller_clk, i_ddr3_clk, i_ref_clk, i_ddr3_clk_90;
+     wire m_axis_tvalid;
+     wire rx_empty;
+     wire tx_full;
+     wire o_wb_ack;
+     wire[7:0] o_wb_data;
+     wire o_aux;
+     wire[7:0] rd_data;
+     wire o_wb_stall;
+     reg i_wb_stb = 0, i_wb_we;
+     wire[63:0] o_debug1;
+     reg[7:0] i_wb_data;
+     reg[7:0] i_wb_addr;
+     // o_debug1 taps on value of state_calibrate (can be traced inside ddr3_controller module)
+     assign led[0] = (o_debug1[4:0] == 23); //light up if at DONE_CALIBRATE
+     assign led[1] = (o_debug1[4:0] == 23); //light up if at DONE_CALIBRATE
+     assign led[2] = (o_debug1[4:0] == 23); //light up if at DONE_CALIBRATE
+     assign led[3] = (o_debug1[4:0] == 23); //light up if at DONE_CALIBRATE
+     assign fan_pwm = 1'b0; // turn on fan
+     //assign ddr3_cs_n[1] = 1'b1;
+
+    //===========================================================================
+    //Differential system clock to single end clock
+    //===========================================================================
+    wire sys_clk; // 200MHz
+    IBUFDS u_ibufg_sys_clk   
+    (
+        .I  (sys_clk_p),            
+        .IB (sys_clk_n),          
+        .O  (sys_clk)        
+    );          
+      
+    always @(posedge i_controller_clk) begin
+        begin
+            i_wb_stb <= 0;
+            i_wb_we <= 0;
+            i_wb_addr <= 0;
+            i_wb_data <= 0;
+            if(!o_wb_stall && m_axis_tvalid) begin
+                if(rd_data >= 97 && rd_data <= 122) begin //write to DDR3 if ASCII is small letter
+                    i_wb_stb <= 1;                 
+                    i_wb_we <= 1;                  
+                    i_wb_addr <= ~rd_data ;                
+                    i_wb_data <= rd_data; 
+                end
+                else if(rd_data >= 65 && rd_data <= 90) begin //read from DDR3 if ASCII is capital letter
+                    i_wb_stb <= 1; //make request
+                    i_wb_we <= 0; //read
+                    i_wb_addr <= ~(rd_data + 8'd32);
+                end
+            end
+        end
+    end
+     
+    wire clk_locked;
+    clk_wiz clk_wiz_inst
+    (
+    // Clock out ports
+    .clk_out1(i_controller_clk), //83.3333 Mhz
+    .clk_out2(i_ddr3_clk), // 333.333 MHz
+    .clk_out3(i_ref_clk), // 200 MHz 
+    .clk_out4(i_ddr3_clk_90), // 333.333 MHz with 90 degree shift
+    // Status and control signals
+    .reset(!i_rst_n),
+    .locked(clk_locked),
+    // Clock in ports
+    .clk_in1(sys_clk)
+    );
+
+    
+    // UART TX/RX module from https://github.com/ben-marshall/uart
+    uart_tx #(
+        .BIT_RATE(9600),
+        .CLK_HZ(83_333_333),
+        .PAYLOAD_BITS(8),
+        .STOP_BITS(1)
+        ) uart_tx_inst (
+        .clk(i_controller_clk), // Top level system clock input.
+        .resetn(i_rst_n && clk_locked && o_debug1[4:0] == 23), // Asynchronous active low reset.
+        .uart_txd(tx), // UART transmit pin.
+        .uart_tx_busy(), // Module busy sending previous item.
+        .uart_tx_en(o_wb_ack), // Send the data on uart_tx_data
+        .uart_tx_data(o_wb_data) // The data to be sent
+    );
+    uart_rx #(
+        .BIT_RATE(9600),
+        .CLK_HZ(83_333_333),
+        .PAYLOAD_BITS(8),
+        .STOP_BITS(1)
+    ) uart_rx_inst (
+        .clk(i_controller_clk), // Top level system clock input.
+        .resetn(i_rst_n && clk_locked && o_debug1[4:0] == 23), // Asynchronous active low reset.
+        .uart_rxd(rx), // UART Recieve pin.
+        .uart_rx_en(o_debug1[4:0] == 23), // Recieve enable
+        .uart_rx_break(), // Did we get a BREAK message?
+        .uart_rx_valid(m_axis_tvalid), // Valid data recieved/available.
+        .uart_rx_data(rd_data)   // The recieved data.
+    );
+
+    // DDR3 Controller 
+    ddr3_top #(
+        .CONTROLLER_CLK_PERIOD(10_000), //ps, clock period of the controller interface
+        .DDR3_CLK_PERIOD(2_500), //ps, clock period of the DDR3 RAM device (must be 1/4 of the CONTROLLER_CLK_PERIOD) 
+        .ROW_BITS(15), //width of row address
+        .COL_BITS(10), //width of column address
+        .BA_BITS(3), //width of bank address
+        .BYTE_LANES(2), //number of DDR3 modules to be controlled
+        .AUX_WIDTH(4), //width of aux line (must be >= 4) 
+        .WB2_ADDR_BITS(32), //width of 2nd wishbone address bus 
+        .WB2_DATA_BITS(32), //width of 2nd wishbone data bus
+        .MICRON_SIM(0), //enable faster simulation for micron ddr3 model (shorten POWER_ON_RESET_HIGH and INITIAL_CKE_LOW)
+        .ODELAY_SUPPORTED(1), //set to 1 when ODELAYE2 is supported
+        .SECOND_WISHBONE(0), //set to 1 if 2nd wishbone is needed 
+        .ECC_ENABLE(0), // set to 1 or 2 to add ECC (1 = Side-band ECC per burst, 2 = Side-band ECC per 8 bursts , 3 = Inline ECC ) 
+        .WB_ERROR(0), // set to 1 to support Wishbone error (asserts at ECC double bit error)
+        .BIST_MODE(1), // 0 = No BIST, 1 = run through all address space ONCE , 2 = run through all address space for every test (burst w/r, random w/r, alternating r/w)
+        .SPEED_BIN(1) // 0 = Use top-level parameters , 1 = DDR3-1066 (7-7-7) , 2 = DR3-1333 (9-9-9) , 3 = DDR3-1600 (11-11-11)
+        ) ddr3_top
+        (
+            //clock and reset
+            .i_controller_clk(i_controller_clk),
+            .i_ddr3_clk(i_ddr3_clk), //i_controller_clk has period of CONTROLLER_CLK_PERIOD, i_ddr3_clk has period of DDR3_CLK_PERIOD 
+            .i_ref_clk(i_ref_clk),
+            .i_ddr3_clk_90(i_ddr3_clk_90),
+            .i_rst_n(i_rst_n && clk_locked), 
+            // Wishbone inputs
+            .i_wb_cyc(1), //bus cycle active (1 = normal operation, 0 = all ongoing transaction are to be cancelled)
+            .i_wb_stb(i_wb_stb), //request a transfer
+            .i_wb_we(i_wb_we), //write-enable (1 = write, 0 = read)
+            .i_wb_addr(i_wb_addr), //burst-addressable {row,bank,col} 
+            .i_wb_data(i_wb_data), //write data, for a 4:1 controller data width is 8 times the number of pins on the device
+            .i_wb_sel(16'hffff), //byte strobe for write (1 = write the byte)
+            .i_aux(i_wb_we), //for AXI-interface compatibility (given upon strobe)
+            // Wishbone outputs
+            .o_wb_stall(o_wb_stall), //1 = busy, cannot accept requests
+            .o_wb_ack(o_wb_ack), //1 = read/write request has completed
+            .o_wb_data(o_wb_data), //read data, for a 4:1 controller data width is 8 times the number of pins on the device
+            .o_aux(o_aux),
+            // Wishbone 2 (PHY) inputs
+            .i_wb2_cyc(), //bus cycle active (1 = normal operation, 0 = all ongoing transaction are to be cancelled)
+            .i_wb2_stb(), //request a transfer
+            .i_wb2_we(), //write-enable (1 = write, 0 = read)
+            .i_wb2_addr(), //burst-addressable {row,bank,col} 
+            .i_wb2_data(), //write data, for a 4:1 controller data width is 8 times the number of pins on the device
+            .i_wb2_sel(), //byte strobe for write (1 = write the byte)
+            // Wishbone 2 (Controller) outputs
+            .o_wb2_stall(), //1 = busy, cannot accept requests
+            .o_wb2_ack(), //1 = read/write request has completed
+            .o_wb2_data(), //read data, for a 4:1 controller data width is 8 times the number of pins on the device
+            // PHY Interface (to be added later)
+            // DDR3 I/O Interface
+            .o_ddr3_clk_p(ddr3_ck_p),
+            .o_ddr3_clk_n(ddr3_ck_n),
+            .o_ddr3_reset_n(ddr3_reset_n),
+            .o_ddr3_cke(ddr3_cke), // CKE
+            .o_ddr3_cs_n(ddr3_cs_n), // chip select signal (controls rank 1 only)
+            .o_ddr3_ras_n(ddr3_ras_n), // RAS#
+            .o_ddr3_cas_n(ddr3_cas_n), // CAS#
+            .o_ddr3_we_n(ddr3_we_n), // WE#
+            .o_ddr3_addr(ddr3_addr),
+            .o_ddr3_ba_addr(ddr3_ba),
+            .io_ddr3_dq(ddr3_dq),
+            .io_ddr3_dqs(ddr3_dqs_p),
+            .io_ddr3_dqs_n(ddr3_dqs_n),
+            .o_ddr3_dm(ddr3_dm),
+            .o_ddr3_odt(ddr3_odt), // on-die termination
+            .o_debug1(o_debug1)
+        );
+
+endmodule
+

AngeloJacobo_UberDDR3/example_demo/alinx_ax7325b/ax7325b_ddr3.xdc

@@ -0,0 +1,759 @@
+############## clock define##################
+create_clock -period 5.000 [get_ports sys_clk_p]
+set_property PACKAGE_PIN AE10 [get_ports sys_clk_p]
+set_property IOSTANDARD DIFF_SSTL15 [get_ports sys_clk_p]
+
+# no need to constrain N side (only P side) or else tool will analyze interclock oaths and show failure in timing
+# https://support.xilinx.com/s/article/57109?language=en_US
+#create_clock -period 5.000 [get_ports sys_clk_n]
+set_property PACKAGE_PIN AF10 [get_ports sys_clk_n]
+set_property IOSTANDARD DIFF_SSTL15 [get_ports sys_clk_n]
+
+
+############## key define##################
+set_property PACKAGE_PIN AG27 [get_ports i_rst_n]
+set_property IOSTANDARD LVCMOS25 [get_ports i_rst_n]
+
+
+############## fan define##################
+set_property IOSTANDARD LVCMOS25 [get_ports fan_pwm]
+set_property PACKAGE_PIN AE26 [get_ports fan_pwm]
+
+
+##############LED define##################
+set_property PACKAGE_PIN A22 [get_ports {led[0]}]
+set_property IOSTANDARD LVCMOS15 [get_ports {led[0]}]
+
+set_property PACKAGE_PIN C19 [get_ports {led[1]}]
+set_property IOSTANDARD LVCMOS15 [get_ports {led[1]}]
+
+set_property PACKAGE_PIN B19 [get_ports {led[2]}]
+set_property IOSTANDARD LVCMOS15 [get_ports {led[2]}]
+
+set_property PACKAGE_PIN E18 [get_ports {led[3]}]
+set_property IOSTANDARD LVCMOS15 [get_ports {led[3]}]
+
+
+##############uart define###########################
+set_property IOSTANDARD LVCMOS25 [get_ports rx]
+set_property PACKAGE_PIN AJ26 [get_ports rx]
+
+set_property IOSTANDARD LVCMOS25 [get_ports tx]
+set_property PACKAGE_PIN AK26 [get_ports tx]
+
+############## NET - IOSTANDARD ##################
+
+
+############## NET - IOSTANDARD ##################
+
+
+# PadFunction: IO_L13P_T2_MRCC_32 
+set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[0]}]
+set_property SLEW FAST [get_ports {ddr3_dq[0]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[0]}]
+set_property PACKAGE_PIN AD18 [get_ports {ddr3_dq[0]}]
+
+# PadFunction: IO_L16N_T2_32 
+set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[1]}]
+set_property SLEW FAST [get_ports {ddr3_dq[1]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[1]}]
+set_property PACKAGE_PIN AB18 [get_ports {ddr3_dq[1]}]
+
+# PadFunction: IO_L14P_T2_SRCC_32 
+set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[2]}]
+set_property SLEW FAST [get_ports {ddr3_dq[2]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[2]}]
+set_property PACKAGE_PIN AD17 [get_ports {ddr3_dq[2]}]
+
+# PadFunction: IO_L17P_T2_32 
+set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[3]}]
+set_property SLEW FAST [get_ports {ddr3_dq[3]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[3]}]
+set_property PACKAGE_PIN AB19 [get_ports {ddr3_dq[3]}]
+
+# PadFunction: IO_L14N_T2_SRCC_32 
+set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[4]}]
+set_property SLEW FAST [get_ports {ddr3_dq[4]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[4]}]
+set_property PACKAGE_PIN AD16 [get_ports {ddr3_dq[4]}]
+
+# PadFunction: IO_L17N_T2_32 
+set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[5]}]
+set_property SLEW FAST [get_ports {ddr3_dq[5]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[5]}]
+set_property PACKAGE_PIN AC19 [get_ports {ddr3_dq[5]}]
+
+# PadFunction: IO_L13N_T2_MRCC_32 
+set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[6]}]
+set_property SLEW FAST [get_ports {ddr3_dq[6]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[6]}]
+set_property PACKAGE_PIN AE18 [get_ports {ddr3_dq[6]}]
+
+# PadFunction: IO_L18P_T2_32 
+set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[7]}]
+set_property SLEW FAST [get_ports {ddr3_dq[7]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[7]}]
+set_property PACKAGE_PIN AB17 [get_ports {ddr3_dq[7]}]
+
+# PadFunction: IO_L8P_T1_32 
+set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[8]}]
+set_property SLEW FAST [get_ports {ddr3_dq[8]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[8]}]
+set_property PACKAGE_PIN AG19 [get_ports {ddr3_dq[8]}]
+
+# PadFunction: IO_L7N_T1_32 
+set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[9]}]
+set_property SLEW FAST [get_ports {ddr3_dq[9]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[9]}]
+set_property PACKAGE_PIN AK19 [get_ports {ddr3_dq[9]}]
+
+# PadFunction: IO_L10P_T1_32 
+set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[10]}]
+set_property SLEW FAST [get_ports {ddr3_dq[10]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[10]}]
+set_property PACKAGE_PIN AD19 [get_ports {ddr3_dq[10]}]
+
+# PadFunction: IO_L7P_T1_32 
+set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[11]}]
+set_property SLEW FAST [get_ports {ddr3_dq[11]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[11]}]
+set_property PACKAGE_PIN AJ19 [get_ports {ddr3_dq[11]}]
+
+# PadFunction: IO_L11P_T1_SRCC_32 
+set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[12]}]
+set_property SLEW FAST [get_ports {ddr3_dq[12]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[12]}]
+set_property PACKAGE_PIN AF18 [get_ports {ddr3_dq[12]}]
+
+# PadFunction: IO_L8N_T1_32 
+set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[13]}]
+set_property SLEW FAST [get_ports {ddr3_dq[13]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[13]}]
+set_property PACKAGE_PIN AH19 [get_ports {ddr3_dq[13]}]
+
+# PadFunction: IO_L10N_T1_32 
+set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[14]}]
+set_property SLEW FAST [get_ports {ddr3_dq[14]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[14]}]
+set_property PACKAGE_PIN AE19 [get_ports {ddr3_dq[14]}]
+
+# PadFunction: IO_L11N_T1_SRCC_32 
+set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[15]}]
+set_property SLEW FAST [get_ports {ddr3_dq[15]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[15]}]
+set_property PACKAGE_PIN AG18 [get_ports {ddr3_dq[15]}]
+
+# PadFunction: IO_L1N_T0_32 
+set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[16]}]
+set_property SLEW FAST [get_ports {ddr3_dq[16]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[16]}]
+set_property PACKAGE_PIN AK15 [get_ports {ddr3_dq[16]}]
+
+# PadFunction: IO_L5N_T0_32 
+set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[17]}]
+set_property SLEW FAST [get_ports {ddr3_dq[17]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[17]}]
+set_property PACKAGE_PIN AJ17 [get_ports {ddr3_dq[17]}]
+
+# PadFunction: IO_L2N_T0_32 
+set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[18]}]
+set_property SLEW FAST [get_ports {ddr3_dq[18]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[18]}]
+set_property PACKAGE_PIN AH15 [get_ports {ddr3_dq[18]}]
+
+# PadFunction: IO_L4P_T0_32 
+set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[19]}]
+set_property SLEW FAST [get_ports {ddr3_dq[19]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[19]}]
+set_property PACKAGE_PIN AF15 [get_ports {ddr3_dq[19]}]
+
+# PadFunction: IO_L4N_T0_32 
+set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[20]}]
+set_property SLEW FAST [get_ports {ddr3_dq[20]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[20]}]
+set_property PACKAGE_PIN AG14 [get_ports {ddr3_dq[20]}]
+
+# PadFunction: IO_L5P_T0_32 
+set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[21]}]
+set_property SLEW FAST [get_ports {ddr3_dq[21]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[21]}]
+set_property PACKAGE_PIN AH17 [get_ports {ddr3_dq[21]}]
+
+# PadFunction: IO_L2P_T0_32 
+set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[22]}]
+set_property SLEW FAST [get_ports {ddr3_dq[22]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[22]}]
+set_property PACKAGE_PIN AG15 [get_ports {ddr3_dq[22]}]
+
+# PadFunction: IO_L1P_T0_32 
+set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[23]}]
+set_property SLEW FAST [get_ports {ddr3_dq[23]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[23]}]
+set_property PACKAGE_PIN AK16 [get_ports {ddr3_dq[23]}]
+
+# PadFunction: IO_L19P_T3_32 
+set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[24]}]
+set_property SLEW FAST [get_ports {ddr3_dq[24]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[24]}]
+set_property PACKAGE_PIN AE15 [get_ports {ddr3_dq[24]}]
+
+# PadFunction: IO_L24P_T3_32 
+set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[25]}]
+set_property SLEW FAST [get_ports {ddr3_dq[25]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[25]}]
+set_property PACKAGE_PIN Y16 [get_ports {ddr3_dq[25]}]
+
+# PadFunction: IO_L22P_T3_32 
+set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[26]}]
+set_property SLEW FAST [get_ports {ddr3_dq[26]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[26]}]
+set_property PACKAGE_PIN AC14 [get_ports {ddr3_dq[26]}]
+
+# PadFunction: IO_L20P_T3_32 
+set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[27]}]
+set_property SLEW FAST [get_ports {ddr3_dq[27]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[27]}]
+set_property PACKAGE_PIN AA15 [get_ports {ddr3_dq[27]}]
+
+# PadFunction: IO_L23P_T3_32 
+set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[28]}]
+set_property SLEW FAST [get_ports {ddr3_dq[28]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[28]}]
+set_property PACKAGE_PIN AA17 [get_ports {ddr3_dq[28]}]
+
+# PadFunction: IO_L22N_T3_32 
+set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[29]}]
+set_property SLEW FAST [get_ports {ddr3_dq[29]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[29]}]
+set_property PACKAGE_PIN AD14 [get_ports {ddr3_dq[29]}]
+
+# PadFunction: IO_L23N_T3_32 
+set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[30]}]
+set_property SLEW FAST [get_ports {ddr3_dq[30]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[30]}]
+set_property PACKAGE_PIN AA16 [get_ports {ddr3_dq[30]}]
+
+# PadFunction: IO_L20N_T3_32 
+set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[31]}]
+set_property SLEW FAST [get_ports {ddr3_dq[31]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[31]}]
+set_property PACKAGE_PIN AB15 [get_ports {ddr3_dq[31]}]
+
+# PadFunction: IO_L22N_T3_34 
+set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[32]}]
+set_property SLEW FAST [get_ports {ddr3_dq[32]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[32]}]
+set_property PACKAGE_PIN AK6 [get_ports {ddr3_dq[32]}]
+
+# PadFunction: IO_L23P_T3_34 
+set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[33]}]
+set_property SLEW FAST [get_ports {ddr3_dq[33]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[33]}]
+set_property PACKAGE_PIN AJ8 [get_ports {ddr3_dq[33]}]
+
+# PadFunction: IO_L22P_T3_34 
+set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[34]}]
+set_property SLEW FAST [get_ports {ddr3_dq[34]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[34]}]
+set_property PACKAGE_PIN AJ6 [get_ports {ddr3_dq[34]}]
+
+# PadFunction: IO_L19P_T3_34 
+set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[35]}]
+set_property SLEW FAST [get_ports {ddr3_dq[35]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[35]}]
+set_property PACKAGE_PIN AF8 [get_ports {ddr3_dq[35]}]
+
+# PadFunction: IO_L24N_T3_34 
+set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[36]}]
+set_property SLEW FAST [get_ports {ddr3_dq[36]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[36]}]
+set_property PACKAGE_PIN AK4 [get_ports {ddr3_dq[36]}]
+
+# PadFunction: IO_L23N_T3_34 
+set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[37]}]
+set_property SLEW FAST [get_ports {ddr3_dq[37]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[37]}]
+set_property PACKAGE_PIN AK8 [get_ports {ddr3_dq[37]}]
+
+# PadFunction: IO_L24P_T3_34 
+set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[38]}]
+set_property SLEW FAST [get_ports {ddr3_dq[38]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[38]}]
+set_property PACKAGE_PIN AK5 [get_ports {ddr3_dq[38]}]
+
+# PadFunction: IO_L20N_T3_34 
+set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[39]}]
+set_property SLEW FAST [get_ports {ddr3_dq[39]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[39]}]
+set_property PACKAGE_PIN AG7 [get_ports {ddr3_dq[39]}]
+
+# PadFunction: IO_L10P_T1_34 
+set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[40]}]
+set_property SLEW FAST [get_ports {ddr3_dq[40]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[40]}]
+set_property PACKAGE_PIN AE4 [get_ports {ddr3_dq[40]}]
+
+# PadFunction: IO_L8N_T1_34 
+set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[41]}]
+set_property SLEW FAST [get_ports {ddr3_dq[41]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[41]}]
+set_property PACKAGE_PIN AF1 [get_ports {ddr3_dq[41]}]
+
+# PadFunction: IO_L11P_T1_SRCC_34 
+set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[42]}]
+set_property SLEW FAST [get_ports {ddr3_dq[42]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[42]}]
+set_property PACKAGE_PIN AE5 [get_ports {ddr3_dq[42]}]
+
+# PadFunction: IO_L8P_T1_34 
+set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[43]}]
+set_property SLEW FAST [get_ports {ddr3_dq[43]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[43]}]
+set_property PACKAGE_PIN AE1 [get_ports {ddr3_dq[43]}]
+
+# PadFunction: IO_L12P_T1_MRCC_34 
+set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[44]}]
+set_property SLEW FAST [get_ports {ddr3_dq[44]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[44]}]
+set_property PACKAGE_PIN AF6 [get_ports {ddr3_dq[44]}]
+
+# PadFunction: IO_L10N_T1_34 
+set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[45]}]
+set_property SLEW FAST [get_ports {ddr3_dq[45]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[45]}]
+set_property PACKAGE_PIN AE3 [get_ports {ddr3_dq[45]}]
+
+# PadFunction: IO_L11N_T1_SRCC_34 
+set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[46]}]
+set_property SLEW FAST [get_ports {ddr3_dq[46]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[46]}]
+set_property PACKAGE_PIN AF5 [get_ports {ddr3_dq[46]}]
+
+# PadFunction: IO_L7N_T1_34 
+set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[47]}]
+set_property SLEW FAST [get_ports {ddr3_dq[47]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[47]}]
+set_property PACKAGE_PIN AF2 [get_ports {ddr3_dq[47]}]
+
+# PadFunction: IO_L13P_T2_MRCC_34 
+set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[48]}]
+set_property SLEW FAST [get_ports {ddr3_dq[48]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[48]}]
+set_property PACKAGE_PIN AH4 [get_ports {ddr3_dq[48]}]
+
+# PadFunction: IO_L16N_T2_34 
+set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[49]}]
+set_property SLEW FAST [get_ports {ddr3_dq[49]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[49]}]
+set_property PACKAGE_PIN AJ2 [get_ports {ddr3_dq[49]}]
+
+# PadFunction: IO_L14N_T2_SRCC_34 
+set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[50]}]
+set_property SLEW FAST [get_ports {ddr3_dq[50]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[50]}]
+set_property PACKAGE_PIN AH5 [get_ports {ddr3_dq[50]}]
+
+# PadFunction: IO_L13N_T2_MRCC_34 
+set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[51]}]
+set_property SLEW FAST [get_ports {ddr3_dq[51]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[51]}]
+set_property PACKAGE_PIN AJ4 [get_ports {ddr3_dq[51]}]
+
+# PadFunction: IO_L16P_T2_34 
+set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[52]}]
+set_property SLEW FAST [get_ports {ddr3_dq[52]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[52]}]
+set_property PACKAGE_PIN AH2 [get_ports {ddr3_dq[52]}]
+
+# PadFunction: IO_L17N_T2_34 
+set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[53]}]
+set_property SLEW FAST [get_ports {ddr3_dq[53]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[53]}]
+set_property PACKAGE_PIN AK1 [get_ports {ddr3_dq[53]}]
+
+# PadFunction: IO_L14P_T2_SRCC_34 
+set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[54]}]
+set_property SLEW FAST [get_ports {ddr3_dq[54]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[54]}]
+set_property PACKAGE_PIN AH6 [get_ports {ddr3_dq[54]}]
+
+# PadFunction: IO_L17P_T2_34 
+set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[55]}]
+set_property SLEW FAST [get_ports {ddr3_dq[55]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[55]}]
+set_property PACKAGE_PIN AJ1 [get_ports {ddr3_dq[55]}]
+
+# PadFunction: IO_L2P_T0_34 
+set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[56]}]
+set_property SLEW FAST [get_ports {ddr3_dq[56]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[56]}]
+set_property PACKAGE_PIN AC2 [get_ports {ddr3_dq[56]}]
+
+# PadFunction: IO_L4P_T0_34 
+set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[57]}]
+set_property SLEW FAST [get_ports {ddr3_dq[57]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[57]}]
+set_property PACKAGE_PIN AC5 [get_ports {ddr3_dq[57]}]
+
+# PadFunction: IO_L1N_T0_34 
+set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[58]}]
+set_property SLEW FAST [get_ports {ddr3_dq[58]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[58]}]
+set_property PACKAGE_PIN AD3 [get_ports {ddr3_dq[58]}]
+
+# PadFunction: IO_L6P_T0_34 
+set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[59]}]
+set_property SLEW FAST [get_ports {ddr3_dq[59]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[59]}]
+set_property PACKAGE_PIN AC7 [get_ports {ddr3_dq[59]}]
+
+# PadFunction: IO_L5N_T0_34 
+set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[60]}]
+set_property SLEW FAST [get_ports {ddr3_dq[60]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[60]}]
+set_property PACKAGE_PIN AE6 [get_ports {ddr3_dq[60]}]
+
+# PadFunction: IO_L5P_T0_34 
+set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[61]}]
+set_property SLEW FAST [get_ports {ddr3_dq[61]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[61]}]
+set_property PACKAGE_PIN AD6 [get_ports {ddr3_dq[61]}]
+
+# PadFunction: IO_L2N_T0_34 
+set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[62]}]
+set_property SLEW FAST [get_ports {ddr3_dq[62]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[62]}]
+set_property PACKAGE_PIN AC1 [get_ports {ddr3_dq[62]}]
+
+# PadFunction: IO_L4N_T0_34 
+set_property VCCAUX_IO HIGH [get_ports {ddr3_dq[63]}]
+set_property SLEW FAST [get_ports {ddr3_dq[63]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dq[63]}]
+set_property PACKAGE_PIN AC4 [get_ports {ddr3_dq[63]}]
+
+# PadFunction: IO_L15P_T2_DQS_33 
+set_property VCCAUX_IO HIGH [get_ports {ddr3_addr[14]}]
+set_property SLEW FAST [get_ports {ddr3_addr[14]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[14]}]
+set_property PACKAGE_PIN AJ9 [get_ports {ddr3_addr[14]}]
+
+# PadFunction: IO_L7N_T1_33 
+set_property VCCAUX_IO HIGH [get_ports {ddr3_addr[13]}]
+set_property SLEW FAST [get_ports {ddr3_addr[13]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[13]}]
+set_property PACKAGE_PIN AC10 [get_ports {ddr3_addr[13]}]
+
+# PadFunction: IO_L7P_T1_33 
+set_property VCCAUX_IO HIGH [get_ports {ddr3_addr[12]}]
+set_property SLEW FAST [get_ports {ddr3_addr[12]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[12]}]
+set_property PACKAGE_PIN AB10 [get_ports {ddr3_addr[12]}]
+
+# PadFunction: IO_L8P_T1_33 
+set_property VCCAUX_IO HIGH [get_ports {ddr3_addr[11]}]
+set_property SLEW FAST [get_ports {ddr3_addr[11]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[11]}]
+set_property PACKAGE_PIN AD8 [get_ports {ddr3_addr[11]}]
+
+# PadFunction: IO_L6P_T0_33 
+set_property VCCAUX_IO HIGH [get_ports {ddr3_addr[10]}]
+set_property SLEW FAST [get_ports {ddr3_addr[10]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[10]}]
+set_property PACKAGE_PIN AA13 [get_ports {ddr3_addr[10]}]
+
+# PadFunction: IO_L5N_T0_33 
+set_property VCCAUX_IO HIGH [get_ports {ddr3_addr[9]}]
+set_property SLEW FAST [get_ports {ddr3_addr[9]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[9]}]
+set_property PACKAGE_PIN AA10 [get_ports {ddr3_addr[9]}]
+
+# PadFunction: IO_L5P_T0_33 
+set_property VCCAUX_IO HIGH [get_ports {ddr3_addr[8]}]
+set_property SLEW FAST [get_ports {ddr3_addr[8]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[8]}]
+set_property PACKAGE_PIN AA11 [get_ports {ddr3_addr[8]}]
+
+# PadFunction: IO_L4N_T0_33 
+set_property VCCAUX_IO HIGH [get_ports {ddr3_addr[7]}]
+set_property SLEW FAST [get_ports {ddr3_addr[7]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[7]}]
+set_property PACKAGE_PIN Y10 [get_ports {ddr3_addr[7]}]
+
+# PadFunction: IO_L6N_T0_VREF_33 
+set_property VCCAUX_IO HIGH [get_ports {ddr3_addr[6]}]
+set_property SLEW FAST [get_ports {ddr3_addr[6]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[6]}]
+set_property PACKAGE_PIN AB13 [get_ports {ddr3_addr[6]}]
+
+# PadFunction: IO_L3N_T0_DQS_33 
+set_property VCCAUX_IO HIGH [get_ports {ddr3_addr[5]}]
+set_property SLEW FAST [get_ports {ddr3_addr[5]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[5]}]
+set_property PACKAGE_PIN AC9 [get_ports {ddr3_addr[5]}]
+
+# PadFunction: IO_L3P_T0_DQS_33 
+set_property VCCAUX_IO HIGH [get_ports {ddr3_addr[4]}]
+set_property SLEW FAST [get_ports {ddr3_addr[4]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[4]}]
+set_property PACKAGE_PIN AB9 [get_ports {ddr3_addr[4]}]
+
+# PadFunction: IO_L2N_T0_33 
+set_property VCCAUX_IO HIGH [get_ports {ddr3_addr[3]}]
+set_property SLEW FAST [get_ports {ddr3_addr[3]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[3]}]
+set_property PACKAGE_PIN AB8 [get_ports {ddr3_addr[3]}]
+
+# PadFunction: IO_L2P_T0_33 
+set_property VCCAUX_IO HIGH [get_ports {ddr3_addr[2]}]
+set_property SLEW FAST [get_ports {ddr3_addr[2]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[2]}]
+set_property PACKAGE_PIN AA8 [get_ports {ddr3_addr[2]}]
+
+# PadFunction: IO_L1N_T0_33 
+set_property VCCAUX_IO HIGH [get_ports {ddr3_addr[1]}]
+set_property SLEW FAST [get_ports {ddr3_addr[1]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[1]}]
+set_property PACKAGE_PIN AB12 [get_ports {ddr3_addr[1]}]
+
+# PadFunction: IO_L1P_T0_33 
+set_property VCCAUX_IO HIGH [get_ports {ddr3_addr[0]}]
+set_property SLEW FAST [get_ports {ddr3_addr[0]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_addr[0]}]
+set_property PACKAGE_PIN AA12 [get_ports {ddr3_addr[0]}]
+
+# PadFunction: IO_L9N_T1_DQS_33 
+set_property VCCAUX_IO HIGH [get_ports {ddr3_ba[2]}]
+set_property SLEW FAST [get_ports {ddr3_ba[2]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_ba[2]}]
+set_property PACKAGE_PIN AC11 [get_ports {ddr3_ba[2]}]
+
+# PadFunction: IO_L9P_T1_DQS_33 
+set_property VCCAUX_IO HIGH [get_ports {ddr3_ba[1]}]
+set_property SLEW FAST [get_ports {ddr3_ba[1]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_ba[1]}]
+set_property PACKAGE_PIN AC12 [get_ports {ddr3_ba[1]}]
+
+# PadFunction: IO_L8N_T1_33 
+set_property VCCAUX_IO HIGH [get_ports {ddr3_ba[0]}]
+set_property SLEW FAST [get_ports {ddr3_ba[0]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_ba[0]}]
+set_property PACKAGE_PIN AE8 [get_ports {ddr3_ba[0]}]
+
+# PadFunction: IO_L10N_T1_33 
+set_property VCCAUX_IO HIGH [get_ports {ddr3_ras_n}]
+set_property SLEW FAST [get_ports {ddr3_ras_n}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_ras_n}]
+set_property PACKAGE_PIN AE9 [get_ports {ddr3_ras_n}]
+
+# PadFunction: IO_L11P_T1_SRCC_33 
+set_property VCCAUX_IO HIGH [get_ports {ddr3_cas_n}]
+set_property SLEW FAST [get_ports {ddr3_cas_n}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_cas_n}]
+set_property PACKAGE_PIN AE11 [get_ports {ddr3_cas_n}]
+
+# PadFunction: IO_L10P_T1_33 
+set_property VCCAUX_IO HIGH [get_ports {ddr3_we_n}]
+set_property SLEW FAST [get_ports {ddr3_we_n}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_we_n}]
+set_property PACKAGE_PIN AD9 [get_ports {ddr3_we_n}]
+
+# PadFunction: IO_L4P_T0_33 
+set_property VCCAUX_IO HIGH [get_ports {ddr3_reset_n}]
+set_property SLEW FAST [get_ports {ddr3_reset_n}]
+set_property IOSTANDARD LVCMOS15 [get_ports {ddr3_reset_n}]
+set_property PACKAGE_PIN Y11 [get_ports {ddr3_reset_n}]
+
+# PadFunction: IO_L12P_T1_MRCC_33 
+set_property VCCAUX_IO HIGH [get_ports {ddr3_cke}]
+set_property SLEW FAST [get_ports {ddr3_cke}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_cke}]
+set_property PACKAGE_PIN AD12 [get_ports {ddr3_cke}]
+
+# PadFunction: IO_L12N_T1_MRCC_33 
+set_property VCCAUX_IO HIGH [get_ports {ddr3_odt}]
+set_property SLEW FAST [get_ports {ddr3_odt}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_odt}]
+set_property PACKAGE_PIN AD11 [get_ports {ddr3_odt}]
+
+# PadFunction: IO_L11N_T1_SRCC_33 
+set_property VCCAUX_IO HIGH [get_ports {ddr3_cs_n}]
+set_property SLEW FAST [get_ports {ddr3_cs_n}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_cs_n}]
+set_property PACKAGE_PIN AF11 [get_ports {ddr3_cs_n}]
+
+# PadFunction: IO_L16P_T2_32 
+set_property VCCAUX_IO HIGH [get_ports {ddr3_dm[0]}]
+set_property SLEW FAST [get_ports {ddr3_dm[0]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[0]}]
+set_property PACKAGE_PIN AA18 [get_ports {ddr3_dm[0]}]
+
+# PadFunction: IO_L12P_T1_MRCC_32 
+set_property VCCAUX_IO HIGH [get_ports {ddr3_dm[1]}]
+set_property SLEW FAST [get_ports {ddr3_dm[1]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[1]}]
+set_property PACKAGE_PIN AF17 [get_ports {ddr3_dm[1]}]
+
+# PadFunction: IO_L6P_T0_32 
+set_property VCCAUX_IO HIGH [get_ports {ddr3_dm[2]}]
+set_property SLEW FAST [get_ports {ddr3_dm[2]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[2]}]
+set_property PACKAGE_PIN AE16 [get_ports {ddr3_dm[2]}]
+
+# PadFunction: IO_L24N_T3_32 
+set_property VCCAUX_IO HIGH [get_ports {ddr3_dm[3]}]
+set_property SLEW FAST [get_ports {ddr3_dm[3]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[3]}]
+set_property PACKAGE_PIN Y15 [get_ports {ddr3_dm[3]}]
+
+# PadFunction: IO_L20P_T3_34 
+set_property VCCAUX_IO HIGH [get_ports {ddr3_dm[4]}]
+set_property SLEW FAST [get_ports {ddr3_dm[4]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[4]}]
+set_property PACKAGE_PIN AF7 [get_ports {ddr3_dm[4]}]
+
+# PadFunction: IO_L7P_T1_34 
+set_property VCCAUX_IO HIGH [get_ports {ddr3_dm[5]}]
+set_property SLEW FAST [get_ports {ddr3_dm[5]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[5]}]
+set_property PACKAGE_PIN AF3 [get_ports {ddr3_dm[5]}]
+
+# PadFunction: IO_L18P_T2_34 
+set_property VCCAUX_IO HIGH [get_ports {ddr3_dm[6]}]
+set_property SLEW FAST [get_ports {ddr3_dm[6]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[6]}]
+set_property PACKAGE_PIN AJ3 [get_ports {ddr3_dm[6]}]
+
+# PadFunction: IO_L1P_T0_34 
+set_property VCCAUX_IO HIGH [get_ports {ddr3_dm[7]}]
+set_property SLEW FAST [get_ports {ddr3_dm[7]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dm[7]}]
+set_property PACKAGE_PIN AD4 [get_ports {ddr3_dm[7]}]
+
+# PadFunction: IO_L15P_T2_DQS_32 
+set_property VCCAUX_IO HIGH [get_ports {ddr3_dqs_p[0]}]
+set_property SLEW FAST [get_ports {ddr3_dqs_p[0]}]
+set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_p[0]}]
+set_property PACKAGE_PIN Y19 [get_ports {ddr3_dqs_p[0]}]
+
+# PadFunction: IO_L15N_T2_DQS_32 
+set_property VCCAUX_IO HIGH [get_ports {ddr3_dqs_n[0]}]
+set_property SLEW FAST [get_ports {ddr3_dqs_n[0]}]
+set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_n[0]}]
+set_property PACKAGE_PIN Y18 [get_ports {ddr3_dqs_n[0]}]
+
+# PadFunction: IO_L9P_T1_DQS_32 
+set_property VCCAUX_IO HIGH [get_ports {ddr3_dqs_p[1]}]
+set_property SLEW FAST [get_ports {ddr3_dqs_p[1]}]
+set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_p[1]}]
+set_property PACKAGE_PIN AJ18 [get_ports {ddr3_dqs_p[1]}]
+
+# PadFunction: IO_L9N_T1_DQS_32 
+set_property VCCAUX_IO HIGH [get_ports {ddr3_dqs_n[1]}]
+set_property SLEW FAST [get_ports {ddr3_dqs_n[1]}]
+set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_dqs_n[1]}]
+set_property PACKAGE_PIN AK18 [get_ports {ddr3_dqs_n[1]}]
+
+# PadFunction: IO_L3P_T0_DQS_32 
+set_property VCCAUX_IO HIGH [get_ports {ddr3_dqs_p[2]}]
+set_property SLEW FAST [get_ports {ddr3_dqs_p[2]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dqs_p[2]}]
+set_property PACKAGE_PIN AH16 [get_ports {ddr3_dqs_p[2]}]
+
+# PadFunction: IO_L3N_T0_DQS_32 
+set_property VCCAUX_IO HIGH [get_ports {ddr3_dqs_n[2]}]
+set_property SLEW FAST [get_ports {ddr3_dqs_n[2]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dqs_n[2]}]
+set_property PACKAGE_PIN AJ16 [get_ports {ddr3_dqs_n[2]}]
+
+# PadFunction: IO_L21P_T3_DQS_32 
+set_property VCCAUX_IO HIGH [get_ports {ddr3_dqs_p[3]}]
+set_property SLEW FAST [get_ports {ddr3_dqs_p[3]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dqs_p[3]}]
+set_property PACKAGE_PIN AC16 [get_ports {ddr3_dqs_p[3]}]
+
+# PadFunction: IO_L21N_T3_DQS_32 
+set_property VCCAUX_IO HIGH [get_ports {ddr3_dqs_n[3]}]
+set_property SLEW FAST [get_ports {ddr3_dqs_n[3]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dqs_n[3]}]
+set_property PACKAGE_PIN AC15 [get_ports {ddr3_dqs_n[3]}]
+
+# PadFunction: IO_L21P_T3_DQS_34 
+set_property VCCAUX_IO HIGH [get_ports {ddr3_dqs_p[4]}]
+set_property SLEW FAST [get_ports {ddr3_dqs_p[4]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dqs_p[4]}]
+set_property PACKAGE_PIN AH7 [get_ports {ddr3_dqs_p[4]}]
+
+# PadFunction: IO_L21N_T3_DQS_34 
+set_property VCCAUX_IO HIGH [get_ports {ddr3_dqs_n[4]}]
+set_property SLEW FAST [get_ports {ddr3_dqs_n[4]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dqs_n[4]}]
+set_property PACKAGE_PIN AJ7 [get_ports {ddr3_dqs_n[4]}]
+
+# PadFunction: IO_L9P_T1_DQS_34 
+set_property VCCAUX_IO HIGH [get_ports {ddr3_dqs_p[5]}]
+set_property SLEW FAST [get_ports {ddr3_dqs_p[5]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dqs_p[5]}]
+set_property PACKAGE_PIN AG4 [get_ports {ddr3_dqs_p[5]}]
+
+# PadFunction: IO_L9N_T1_DQS_34 
+set_property VCCAUX_IO HIGH [get_ports {ddr3_dqs_n[5]}]
+set_property SLEW FAST [get_ports {ddr3_dqs_n[5]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dqs_n[5]}]
+set_property PACKAGE_PIN AG3 [get_ports {ddr3_dqs_n[5]}]
+
+# PadFunction: IO_L15P_T2_DQS_34 
+set_property VCCAUX_IO HIGH [get_ports {ddr3_dqs_p[6]}]
+set_property SLEW FAST [get_ports {ddr3_dqs_p[6]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dqs_p[6]}]
+set_property PACKAGE_PIN AG2 [get_ports {ddr3_dqs_p[6]}]
+
+# PadFunction: IO_L15N_T2_DQS_34 
+set_property VCCAUX_IO HIGH [get_ports {ddr3_dqs_n[6]}]
+set_property SLEW FAST [get_ports {ddr3_dqs_n[6]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dqs_n[6]}]
+set_property PACKAGE_PIN AH1 [get_ports {ddr3_dqs_n[6]}]
+
+# PadFunction: IO_L3P_T0_DQS_34 
+set_property VCCAUX_IO HIGH [get_ports {ddr3_dqs_p[7]}]
+set_property SLEW FAST [get_ports {ddr3_dqs_p[7]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dqs_p[7]}]
+set_property PACKAGE_PIN AD2 [get_ports {ddr3_dqs_p[7]}]
+
+# PadFunction: IO_L3N_T0_DQS_34 
+set_property VCCAUX_IO HIGH [get_ports {ddr3_dqs_n[7]}]
+set_property SLEW FAST [get_ports {ddr3_dqs_n[7]}]
+set_property IOSTANDARD SSTL15 [get_ports {ddr3_dqs_n[7]}]
+set_property PACKAGE_PIN AD1 [get_ports {ddr3_dqs_n[7]}]
+
+# PadFunction: IO_L13P_T2_MRCC_33 
+set_property VCCAUX_IO HIGH [get_ports {ddr3_ck_p}]
+set_property SLEW FAST [get_ports {ddr3_ck_p}]
+set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_ck_p}]
+set_property PACKAGE_PIN AG10 [get_ports {ddr3_ck_p}]
+
+# PadFunction: IO_L13N_T2_MRCC_33 
+set_property VCCAUX_IO HIGH [get_ports {ddr3_ck_n}]
+set_property SLEW FAST [get_ports {ddr3_ck_n}]
+set_property IOSTANDARD DIFF_SSTL15 [get_ports {ddr3_ck_n}]
+set_property PACKAGE_PIN AH10 [get_ports {ddr3_ck_n}]
+
+
+
+
+#############SPI Configurate Setting##################
+set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
+set_property CONFIG_MODE SPIx4 [current_design]
+set_property BITSTREAM.CONFIG.CONFIGRATE 50 [current_design]
+set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
+set_property BITSTREAM.CONFIG.UNUSEDPIN Pullup [current_design]
+set_property CFGBVS VCCO [current_design]
+set_property CONFIG_VOLTAGE 3.3 [current_design]
+
+
+
+
+
+
+
+
+

AngeloJacobo_UberDDR3/example_demo/alinx_ax7325b/ax7325b_spd_reader.xdc

@@ -0,0 +1,37 @@
+############## clock define##################
+create_clock -period 5.000 [get_ports sys_clk_p]
+set_property IOSTANDARD DIFF_SSTL15 [get_ports sys_clk_p]
+# no need to create_clock for N side (only P side) or else tool will analyze interclock oaths and show failure in timing
+# https://support.xilinx.com/s/article/57109?language=en_US
+#create_clock -period 5.000 [get_ports sys_clk_n]
+set_property PACKAGE_PIN AE10 [get_ports sys_clk_p]
+set_property PACKAGE_PIN AF10 [get_ports sys_clk_n]
+set_property IOSTANDARD DIFF_SSTL15 [get_ports sys_clk_n]
+
+############## SODIMM SPD define##################
+set_property IOSTANDARD LVCMOS33 [get_ports i2c_scl]
+set_property PACKAGE_PIN B20 [get_ports i2c_scl]
+set_property IOSTANDARD LVCMOS33 [get_ports i2c_sda]
+set_property PACKAGE_PIN C20 [get_ports i2c_sda]
+
+############## fan define##################
+set_property IOSTANDARD LVCMOS25 [get_ports fan_pwm]
+set_property PACKAGE_PIN AE26 [get_ports fan_pwm]
+
+############## key define##################
+set_property PACKAGE_PIN AG27 [get_ports i_rst_n]
+set_property IOSTANDARD LVCMOS25 [get_ports i_rst_n]
+
+##############LED define##################
+set_property PACKAGE_PIN A22 [get_ports {led[0]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}]
+set_property PACKAGE_PIN C19 [get_ports {led[1]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}]
+set_property PACKAGE_PIN B19 [get_ports {led[2]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}]
+set_property PACKAGE_PIN E18 [get_ports {led[3]}]
+set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}]
+
+##############uart define###########################
+set_property IOSTANDARD LVCMOS25 [get_ports uart_tx]
+set_property PACKAGE_PIN AK26 [get_ports uart_tx]

AngeloJacobo_UberDDR3/example_demo/alinx_ax7325b/caas.conf

@@ -0,0 +1,11 @@
+[project]
+Backend = openxc7
+Part = xc7k325tffg900-2
+Top = ax7325b_ddr3
+Constraint = ax7325b_ddr3.xdc
+Sources = *.v
+
+[caas]
+Server = https://caas.symbioticeda.com:18888/
+
+

AngeloJacobo_UberDDR3/example_demo/alinx_ax7325b/clk_wiz.v

@@ -0,0 +1,66 @@
+`timescale 1ps/1ps
+
+module clk_wiz
+ (
+  input wire         clk_in1,
+  output wire        clk_out1,
+  output wire        clk_out2,
+  output wire        clk_out3,
+  output wire        clk_out4,
+  input wire         reset,
+  output wire        locked
+ );
+  wire        clk_out1_clk_wiz_0;
+  wire        clk_out2_clk_wiz_0;
+  wire        clk_out3_clk_wiz_0;
+  wire        clk_out4_clk_wiz_0;
+
+
+  wire clkfbout;
+
+  PLLE2_ADV
+  #(.BANDWIDTH            ("OPTIMIZED"),
+    .COMPENSATION         ("INTERNAL"),
+    .STARTUP_WAIT         ("FALSE"),
+    .DIVCLK_DIVIDE        (1),
+    .CLKFBOUT_MULT        (8), // 200 MHz * 8 = 1600 MHz
+    .CLKFBOUT_PHASE       (0.000),
+    .CLKOUT0_DIVIDE       (12), // 1600 MHz / 12 = 133.333 MHz
+    .CLKOUT0_PHASE        (0.000),
+    .CLKOUT0_DUTY_CYCLE   (0.500),
+    .CLKOUT1_DIVIDE       (3), // 1600 MHz / 3 = 533.333 MHz, 0 phase
+    .CLKOUT1_PHASE        (0.000),
+    .CLKOUT1_DUTY_CYCLE   (0.500),
+    .CLKOUT2_DIVIDE       (8), // 1600 MHz / 8 = 200 MHz
+    .CLKOUT2_PHASE        (0.000),
+    .CLKOUT2_DUTY_CYCLE   (0.500),
+    .CLKOUT3_DIVIDE       (3), // 1600 MHz / 3 = 533.333 MHz, 90 phase
+    .CLKOUT3_PHASE        (90.000),
+    .CLKOUT3_DUTY_CYCLE   (0.500),
+    .CLKIN1_PERIOD        (5.000) // 200 MHz input
+  )
+  plle2_adv_inst
+   (
+    .CLKFBOUT            (clkfbout),
+    .CLKOUT0             (clk_out1_clk_wiz_0),
+    .CLKOUT1             (clk_out2_clk_wiz_0),
+    .CLKOUT2             (clk_out3_clk_wiz_0),
+    .CLKOUT3             (clk_out4_clk_wiz_0),
+    .CLKFBIN             (clkfbout),
+	.CLKIN1              (clk_in1),
+    .LOCKED              (locked),
+    .RST                 (reset)
+  );
+  BUFG clkout1_buf
+   (.O   (clk_out1),
+    .I   (clk_out1_clk_wiz_0));
+  BUFG clkout2_buf
+   (.O   (clk_out2),
+    .I   (clk_out2_clk_wiz_0));
+  BUFG clkout3_buf
+   (.O   (clk_out3),
+    .I   (clk_out3_clk_wiz_0));
+  BUFG clkout4_buf
+   (.O   (clk_out4),
+    .I   (clk_out4_clk_wiz_0));
+endmodule

AngeloJacobo_UberDDR3/example_demo/alinx_ax7325b/ddr3_phy.v

@@ -0,0 +1,1462 @@
+////////////////////////////////////////////////////////////////////////////////
+//
+// Filename: ddr3_phy.v
+// Project: UberDDR3 - An Open Source DDR3 Controller
+//
+// Purpose: PHY component for the DDR3 controller. Handles the primitives such
+// as IOSERDES, IODELAY, and IOBUF. These generates the signals connected to 
+// the DDR3 RAM.
+//
+// Engineer: Angelo C. Jacobo
+//
+////////////////////////////////////////////////////////////////////////////////
+//
+// Copyright (C) 2023-2025  Angelo Jacobo
+// 
+//     This program is free software: you can redistribute it and/or modify
+//     it under the terms of the GNU General Public License as published by
+//     the Free Software Foundation, either version 3 of the License, or
+//     (at your option) any later version.
+// 
+//     This program is distributed in the hope that it will be useful,
+//     but WITHOUT ANY WARRANTY; without even the implied warranty of
+//     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//     GNU General Public License for more details.
+// 
+//     You should have received a copy of the GNU General Public License
+//     along with this program.  If not, see <https://www.gnu.org/licenses/>.
+//
+////////////////////////////////////////////////////////////////////////////////
+
+`default_nettype none
+`timescale 1ps / 1ps
+//`define DEBUG_DQS // uncomment to route the raw DQS to output port for debugging
+
+module ddr3_phy #(
+    parameter     CONTROLLER_CLK_PERIOD = 10_000, //ps, clock period of the controller interface
+                  DDR3_CLK_PERIOD = 2_500, //ps, clock period of the DDR3 RAM device (must be 1/4 of the CONTROLLER_CLK_PERIOD) 
+                  ROW_BITS = 14,   //width of row address
+                  BA_BITS = 3,
+                  DQ_BITS = 8,
+                  LANES = 8,
+                  DUAL_RANK_DIMM = 0, // enable dual rank DIMM (1 =  enable, 0 = disable)
+    parameter[0:0] ODELAY_SUPPORTED = 1, //set to 1 when ODELAYE2 is supported
+                   USE_IO_TERMINATION = 0, //use IOBUF_DCIEN and IOBUFDS_DCIEN when 1
+                   NO_IOSERDES_LOOPBACK = 1, // don't use IOSERDES loopback for bitslip training
+              // The next parameters act more like a localparam (since user does not have to set this manually) but was added here to simplify port declaration
+    parameter serdes_ratio = 4, // this controller is fixed as a 4:1 memory controller (CONTROLLER_CLK_PERIOD/DDR3_CLK_PERIOD = 4)
+              wb_data_bits = DQ_BITS*LANES*serdes_ratio*2,
+              wb_sel_bits = wb_data_bits / 8,
+              //4 is the width of a single ddr3 command {cs_n, ras_n, cas_n, we_n} plus 3 (ck_en, odt, reset_n) plus bank bits plus row bits
+              cmd_len = 4 + 3 + BA_BITS + ROW_BITS + 2*DUAL_RANK_DIMM
+    )(
+        input wire i_controller_clk, i_ddr3_clk, i_ref_clk,
+        input wire i_ddr3_clk_90, //required only when ODELAY_SUPPORTED is zero
+        input wire i_rst_n,
+        // Controller Interface
+        input wire i_controller_reset,
+        input wire[cmd_len*serdes_ratio-1:0] i_controller_cmd,
+        input wire i_controller_dqs_tri_control, i_controller_dq_tri_control,
+        input wire i_controller_toggle_dqs,
+        input wire[wb_data_bits-1:0] i_controller_data,
+        input wire[wb_sel_bits-1:0] i_controller_dm,
+        input wire[4:0] i_controller_odelay_data_cntvaluein,i_controller_odelay_dqs_cntvaluein,
+        input wire[4:0] i_controller_idelay_data_cntvaluein,i_controller_idelay_dqs_cntvaluein,
+        input wire[LANES-1:0] i_controller_odelay_data_ld, i_controller_odelay_dqs_ld,
+        input wire[LANES-1:0] i_controller_idelay_data_ld, i_controller_idelay_dqs_ld,
+        input wire[LANES-1:0] i_controller_bitslip,
+        input wire i_controller_write_leveling_calib,
+        output wire[DQ_BITS*LANES*8-1:0] o_controller_iserdes_data,
+        output wire[LANES*8-1:0] o_controller_iserdes_dqs,
+        output wire[LANES*8-1:0] o_controller_iserdes_bitslip_reference,
+        output wire o_controller_idelayctrl_rdy,
+        // DDR3 I/O Interface
+        output wire[DUAL_RANK_DIMM:0] o_ddr3_clk_p,o_ddr3_clk_n,
+        output wire o_ddr3_reset_n,
+        output wire[DUAL_RANK_DIMM:0] o_ddr3_cke, // CKE
+        output wire[DUAL_RANK_DIMM:0] o_ddr3_cs_n, // chip select signal
+        output wire o_ddr3_ras_n, // RAS#
+        output wire o_ddr3_cas_n, // CAS#
+        output wire o_ddr3_we_n, // WE#
+        output wire[ROW_BITS-1:0] o_ddr3_addr,
+        output wire[BA_BITS-1:0] o_ddr3_ba_addr,
+        inout wire[(DQ_BITS*LANES)-1:0] io_ddr3_dq,
+        inout wire[(DQ_BITS*LANES)/8-1:0] io_ddr3_dqs, io_ddr3_dqs_n,
+        output wire[LANES-1:0] o_ddr3_dm,
+        output wire[DUAL_RANK_DIMM:0] o_ddr3_odt, // on-die termination
+        // DEBUG PHY
+        output wire[(DQ_BITS*LANES)/8-1:0] o_ddr3_debug_read_dqs_p,
+        output wire[(DQ_BITS*LANES)/8-1:0] o_ddr3_debug_read_dqs_n
+    );
+
+    // cmd bit assignment
+    localparam CMD_CS_N_2 = cmd_len - 1,
+                CMD_CS_N =  DUAL_RANK_DIMM[0]? cmd_len - 2 : cmd_len - 1,
+                CMD_RAS_N = DUAL_RANK_DIMM[0]? cmd_len - 3 : cmd_len - 2,
+                CMD_CAS_N = DUAL_RANK_DIMM[0]? cmd_len - 4 : cmd_len - 3,
+                CMD_WE_N =  DUAL_RANK_DIMM[0]? cmd_len - 5 : cmd_len - 4,
+                CMD_ODT =   DUAL_RANK_DIMM[0]? cmd_len - 6 : cmd_len - 5,
+                CMD_CKE_2 = DUAL_RANK_DIMM[0]? cmd_len - 7 : cmd_len - 6,
+                CMD_CKE =   DUAL_RANK_DIMM[0]? cmd_len - 8 : cmd_len - 6,
+                CMD_RESET_N = DUAL_RANK_DIMM[0]? cmd_len - 9 : cmd_len - 7,
+                CMD_BANK_START = BA_BITS + ROW_BITS - 1,
+                CMD_ADDRESS_START = ROW_BITS - 1;
+    localparam SYNC_RESET_DELAY = $rtoi($ceil(52_000/CONTROLLER_CLK_PERIOD)); //52_000 ps of reset pulse width required for IDELAYCTRL 
+    //cmd needs to be center-aligned to the positive edge of the 
+    //ddr3_clk. This means cmd needs to be delayed by half the ddr3
+    //clk period. Subtract by 600ps to include the IODELAY insertion
+    //delay. Divide by a delay resolution of 78.125ps per tap to get 
+    //the needed tap value.
+    localparam CMD_ODELAY_TAP = ((DDR3_CLK_PERIOD/2) - 600)/78.125;
+
+    // Data does not have to be delayed (DQS is the on that has to be
+    // delayed and center-aligned to the center eye of data)
+    localparam DATA_ODELAY_TAP = 0; 
+
+    //DQS needs to be edge-aligned to the center eye of the data. 
+    //This means DQS needs to be delayed by a quarter of the ddr3
+    //clk period relative to the data. Subtract by 600ps to include
+    //the IODELAY insertion delay. Divide by a delay resolution of 
+    //78.125ps per tap to get the needed tap value. Then add the tap
+    //value used in data to have the delay relative to the data.
+    localparam DQS_ODELAY_TAP = ((DDR3_CLK_PERIOD/4))/78.125 + DATA_ODELAY_TAP;
+    
+    //Incoming DQS should be 90 degree delayed relative to incoming data
+    localparam DATA_IDELAY_TAP = 0; //600ps delay
+    localparam DQS_IDELAY_TAP = ((DDR3_CLK_PERIOD/4))/78.125 + DATA_IDELAY_TAP;
+    
+    genvar gen_index;
+    wire[cmd_len-1:0] oserdes_cmd, //serialized(4:1) i_controller_cmd_slot_x 
+                      cmd;//delayed oserdes_cmd
+    wire[(DQ_BITS*LANES)-1:0] oserdes_data, odelay_data, idelay_data, read_dq;
+    wire[LANES-1:0] oserdes_dm, odelay_dm;
+    wire[LANES-1:0] odelay_dqs, read_dqs, idelay_dqs;
+    wire[DQ_BITS*LANES-1:0] oserdes_dq_tri_control;
+    wire[LANES-1:0] oserdes_dqs;
+    wire[LANES-1:0] oserdes_dqs_tri_control;
+    wire[LANES-1:0] oserdes_bitslip_reference;
+    reg[$clog2(SYNC_RESET_DELAY):0] delay_before_release_reset;
+    reg sync_rst = 0;
+    wire ddr3_clk;
+    reg toggle_dqs_q; //past value of i_controller_toggle_dqs
+    wire ddr3_clk_delayed;
+    wire idelayctrl_rdy;
+    wire dci_locked;
+    reg[LANES*8-1:0] o_controller_iserdes_bitslip_reference_reg;
+    reg[LANES - 1 : 0] shift_bitslip_index;
+    
+    // initial value of bitslip reference
+    initial begin
+        o_controller_iserdes_bitslip_reference_reg = {LANES{8'b0001_1110}};
+        shift_bitslip_index = 0;
+    end
+                
+    assign o_controller_idelayctrl_rdy = idelayctrl_rdy && dci_locked;
+    
+`ifdef DEBUG_DQS
+    assign o_ddr3_debug_read_dqs_p = io_ddr3_dqs;
+    assign o_ddr3_debug_read_dqs_n = io_ddr3_dqs_n;
+`else
+    assign o_ddr3_debug_read_dqs_p = 0;
+    assign o_ddr3_debug_read_dqs_n = 0;
+`endif
+
+    //synchronous reset
+    always @(posedge i_controller_clk) begin
+        if(!i_rst_n || i_controller_reset) begin
+            sync_rst <= 1'b1;
+            delay_before_release_reset <= SYNC_RESET_DELAY[$clog2(SYNC_RESET_DELAY):0];
+            toggle_dqs_q <= 0;
+        end
+        else begin
+            delay_before_release_reset <= (delay_before_release_reset == 0)? 0: delay_before_release_reset - 1;
+            sync_rst <= !(delay_before_release_reset == 0);
+            toggle_dqs_q <= i_controller_toggle_dqs;
+        end
+    end
+
+    //PHY cmd 
+    generate
+        for(gen_index = 0; gen_index < cmd_len; gen_index = gen_index + 1) begin
+            // OSERDESE2: Output SERial/DESerializer with bitslip
+            //7 Series
+            // Xilinx HDL Libraries Guide, version 13.4
+            `ifndef SIM_MODEL
+                OSERDESE2 #(
+            `else 
+                OSERDESE2_model #(
+            `endif
+                .DATA_RATE_OQ("SDR"), // DDR, SDR
+                .DATA_RATE_TQ("SDR"), // DDR, SDR
+                .DATA_WIDTH(4), // Parallel data width (2-8,10,14)
+                .INIT_OQ(1'b0), // Initial value of OQ output (1'b0,1'b1)
+                .TRISTATE_WIDTH(1)
+            )
+            OSERDESE2_cmd(
+                .OFB(), // 1-bit output: Feedback path for data
+                .OQ(oserdes_cmd[gen_index]), // 1-bit output: Data path output
+                .CLK(i_ddr3_clk), // 1-bit input: High speed clock
+                .CLKDIV(i_controller_clk), // 1-bit input: Divided clock
+                // D1 - D8: 1-bit (each) input: Parallel data inputs (1-bit each)
+                .D1(i_controller_cmd[cmd_len*0 + gen_index]),
+                .D2(i_controller_cmd[cmd_len*1 + gen_index]),
+                .D3(i_controller_cmd[cmd_len*2 + gen_index]),
+                .D4(i_controller_cmd[cmd_len*3 + gen_index]),
+                .OCE(1'b1), // 1-bit input: Output data clock enable
+                .RST(sync_rst), // 1-bit input: Reset
+                // unused signals but were added here to make vivado happy
+                .SHIFTOUT1(), // SHIFTOUT1 / SHIFTOUT2: 1-bit (each) output: Data output expansion (1-bit each)
+                .SHIFTOUT2(),
+                .TBYTEOUT(), // 1-bit output: Byte group tristate
+                .TFB(), // 1-bit output: 3-state control
+                .TQ(), // 1-bit output: 3-state control
+                .D5(),
+                .D6(),
+                .D7(),
+                .D8(),
+                // SHIFTIN1 / SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each)
+                .SHIFTIN1(0),
+                .SHIFTIN2(0),
+                // T1 - T4: 1-bit (each) input: Parallel 3-state inputs
+                .T1(0),
+                .T2(0),
+                .T3(0),
+                .T4(0),
+                .TBYTEIN(0),
+                // 1-bit input: Byte group tristate
+                .TCE(0)
+                // 1-bit input: 3-state clock enable
+            );
+            // End of OSERDESE2_inst instantiation
+      
+        end
+
+        if(DUAL_RANK_DIMM) begin // if dual rank enabled, odt_2 and odt_1 will be generated separately
+            // OSERDESE2: Output SERial/DESerializer with bitslip
+            //7 Series
+            // Xilinx HDL Libraries Guide, version 13.4
+            `ifndef SIM_MODEL
+                OSERDESE2 #(
+            `else 
+                OSERDESE2_model #(
+            `endif
+                .DATA_RATE_OQ("SDR"), // DDR, SDR
+                .DATA_RATE_TQ("SDR"), // DDR, SDR
+                .DATA_WIDTH(4), // Parallel data width (2-8,10,14)
+                .INIT_OQ(1'b0), // Initial value of OQ output (1'b0,1'b1)
+                .TRISTATE_WIDTH(1)
+            )
+            OSERDESE2_cmd(
+                .OFB(), // 1-bit output: Feedback path for data
+                .OQ(o_ddr3_odt[1]), // 1-bit output: Data path output
+                .CLK(i_ddr3_clk), // 1-bit input: High speed clock
+                .CLKDIV(i_controller_clk), // 1-bit input: Divided clock
+                // D1 - D8: 1-bit (each) input: Parallel data inputs (1-bit each)
+                .D1(i_controller_cmd[cmd_len*0 + CMD_ODT]),
+                .D2(i_controller_cmd[cmd_len*1 + CMD_ODT]),
+                .D3(i_controller_cmd[cmd_len*2 + CMD_ODT]),
+                .D4(i_controller_cmd[cmd_len*3 + CMD_ODT]),
+                .OCE(1'b1), // 1-bit input: Output data clock enable
+                .RST(sync_rst), // 1-bit input: Reset
+                // unused signals but were added here to make vivado happy
+                .SHIFTOUT1(), // SHIFTOUT1 / SHIFTOUT2: 1-bit (each) output: Data output expansion (1-bit each)
+                .SHIFTOUT2(),
+                .TBYTEOUT(), // 1-bit output: Byte group tristate
+                .TFB(), // 1-bit output: 3-state control
+                .TQ(), // 1-bit output: 3-state control
+                .D5(),
+                .D6(),
+                .D7(),
+                .D8(),
+                // SHIFTIN1 / SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each)
+                .SHIFTIN1(0),
+                .SHIFTIN2(0),
+                // T1 - T4: 1-bit (each) input: Parallel 3-state inputs
+                .T1(0),
+                .T2(0),
+                .T3(0),
+                .T4(0),
+                .TBYTEIN(0),
+                // 1-bit input: Byte group tristate
+                .TCE(0)
+                // 1-bit input: 3-state clock enable
+            );
+            // End of OSERDESE2_inst instantiation
+        end
+    endgenerate 
+
+    // cs[1] when DUAL_RANK_DIMM enabled
+    generate    
+        if(DUAL_RANK_DIMM) begin
+            assign o_ddr3_cs_n[1] = oserdes_cmd[CMD_CS_N_2];
+            assign o_ddr3_cs_n[0] = oserdes_cmd[CMD_CS_N];
+            assign o_ddr3_cke[1] = oserdes_cmd[CMD_CKE_2];
+            assign o_ddr3_cke[0] = oserdes_cmd[CMD_CKE];
+            assign o_ddr3_odt[0] = oserdes_cmd[CMD_ODT];
+            // o_ddr3_odt[1] will be generated directly by a separate OSERDES
+            // if odt[1] and odt[0] uses same output from oserdes, one of them will be unroutable
+        end
+        else begin
+            assign o_ddr3_cs_n = oserdes_cmd[CMD_CS_N];
+            assign o_ddr3_cke = oserdes_cmd[CMD_CKE];
+            assign o_ddr3_odt = oserdes_cmd[CMD_ODT];
+        end
+    endgenerate
+    assign o_ddr3_ras_n = oserdes_cmd[CMD_RAS_N],
+           o_ddr3_cas_n = oserdes_cmd[CMD_CAS_N],
+           o_ddr3_we_n = oserdes_cmd[CMD_WE_N],
+           o_ddr3_reset_n = oserdes_cmd[CMD_RESET_N],
+           o_ddr3_ba_addr = oserdes_cmd[CMD_BANK_START:CMD_ADDRESS_START+1],
+           o_ddr3_addr = oserdes_cmd[CMD_ADDRESS_START:0];
+    
+    if(ODELAY_SUPPORTED) begin
+        // OSERDESE2: Output SERial/DESerializer with bitslip
+        //7 Series
+        // Xilinx HDL Libraries Guide, version 13.4
+        `ifndef SIM_MODEL
+            OSERDESE2 #(
+        `else 
+            OSERDESE2_model #(
+        `endif
+            .DATA_RATE_OQ("DDR"), // DDR, SDR
+            .DATA_RATE_TQ("SDR"), // DDR, SDR
+            .DATA_WIDTH(8), // Parallel data width (2-8,10,14)
+            .INIT_OQ(1'b0), // Initial value of OQ output (1'b0,1'b1)
+            .TRISTATE_WIDTH(1)
+        )
+        OSERDESE2_clk(
+            .OFB(ddr3_clk), // 1-bit output: Feedback path for data
+            .OQ(), // 1-bit output: Data path output
+            .CLK(i_ddr3_clk), // 1-bit input: High speed clock
+            .CLKDIV(i_controller_clk), // 1-bit input: Divided clock
+            // D1 - D8: 1-bit (each) input: Parallel data inputs (1-bit each)
+            .D1(1'b1),
+            .D2(1'b0),
+            .D3(1'b1),
+            .D4(1'b0),
+            .D5(1'b1),
+            .D6(1'b0),
+            .D7(1'b1),
+            .D8(1'b0),
+            .OCE(1'b1), // 1-bit input: Output data clock enable
+            .RST(sync_rst), // 1-bit input: Reset
+             // unused signals but were added here to make vivado happy
+            .SHIFTOUT1(), // SHIFTOUT1 / SHIFTOUT2: 1-bit (each) output: Data output expansion (1-bit each)
+            .SHIFTOUT2(),
+            .TBYTEOUT(), // 1-bit output: Byte group tristate
+            .TFB(), // 1-bit output: 3-state control
+            .TQ(), // 1-bit output: 3-state control
+            // SHIFTIN1 / SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each)
+            .SHIFTIN1(0),
+            .SHIFTIN2(0),
+            // T1 - T4: 1-bit (each) input: Parallel 3-state inputs
+            .T1(0),
+            .T2(0),
+            .T3(0),
+            .T4(0),
+            .TBYTEIN(0),
+            // 1-bit input: Byte group tristate
+            .TCE(0)
+            // 1-bit input: 3-state clock enable
+        );
+        // End of OSERDESE2_inst instantiation
+
+            //Delay the DQ
+            // Delay resolution: 1/(32 x 2 x F REF ) = 78.125ps
+            (* IODELAY_GROUP="DDR3-GROUP" *)
+            `ifndef SIM_MODEL
+                ODELAYE2 #(
+            `else 
+                ODELAYE2_model #(
+            `endif
+                .DELAY_SRC("ODATAIN"), // Delay input (ODATAIN, CLKIN)
+                .HIGH_PERFORMANCE_MODE("TRUE"), // Reduced jitter to 5ps ("TRUE"), Reduced power but high jitter 9ns ("FALSE")
+                .ODELAY_TYPE("FIXED"), // FIXED, VARIABLE, VAR_LOAD, VAR_LOAD_PIPE
+                .ODELAY_VALUE(CMD_ODELAY_TAP), // Output delay tap setting (0-31)
+                .REFCLK_FREQUENCY(200.0), // IDELAYCTRL clock input frequency in MHz (190.0-210.0).
+                .SIGNAL_PATTERN("DATA") // DATA, CLOCK input signal
+            )
+            ODELAYE2_clk (
+                .CNTVALUEOUT(), // 5-bit output: Counter value output
+                .DATAOUT(ddr3_clk_delayed), // 1-bit output: Delayed data/clock output
+                .C(i_controller_clk), // 1-bit input: Clock input, when using OSERDESE2, C is connected to CLKDIV
+                .CE(1'b0), // 1-bit input: Active high enable increment/decrement input
+                .CINVCTRL(1'b0), // 1-bit input: Dynamic clock inversion input
+                .CLKIN(1'b0), // 1-bit input: Clock delay input
+                .CNTVALUEIN(5'd0), // 5-bit input: Counter value input
+                .INC(1'b0), // 1-bit input: Increment / Decrement tap delay input
+                .LD(1'b0), // 1-bit input: Loads ODELAY_VALUE tap delay in VARIABLE mode, in VAR_LOAD or
+                            // VAR_LOAD_PIPE mode, loads the value of CNTVALUEIN
+                .LDPIPEEN(1'b0), // 1-bit input: Enables the pipeline register to load data
+                .ODATAIN(ddr3_clk), // 1-bit input: Output delay data input
+                .REGRST(1'b0) // 1-bit input: Active-high reset tap-delay input
+            );
+        // if dual rank enabled, then there will be two clk
+        if(DUAL_RANK_DIMM) begin
+            // OBUFDS: Differential Output Buffer
+            // 7 Series
+            // Xilinx HDL Libraries Guide, version 13.4
+            `ifndef SIM_MODEL
+                OBUFDS OBUFDS0_inst (
+            `else 
+                OBUFDS_model OBUFDS0_inst (
+            `endif
+                .O(o_ddr3_clk_p[0]), // Diff_p output (connect directly to top-level port)
+                .OB(o_ddr3_clk_n[0]), // Diff_n output (connect directly to top-level port)
+                .I(ddr3_clk_delayed) // Buffer input
+            );
+            `ifndef SIM_MODEL
+                OBUFDS OBUFDS1_inst (
+            `else 
+                OBUFDS_model OBUFDS1_inst (
+            `endif
+                .O(o_ddr3_clk_p[1]), // Diff_p output (connect directly to top-level port)
+                .OB(o_ddr3_clk_n[1]), // Diff_n output (connect directly to top-level port)
+                .I(ddr3_clk_delayed) // Buffer input
+            );
+            // End of OBUFDS_inst instantiation
+        end
+        else begin
+            // OBUFDS: Differential Output Buffer
+            // 7 Series
+            // Xilinx HDL Libraries Guide, version 13.4
+            `ifndef SIM_MODEL
+                OBUFDS OBUFDS_inst (
+            `else 
+                OBUFDS_model OBUFDS_inst (
+            `endif
+                .O(o_ddr3_clk_p), // Diff_p output (connect directly to top-level port)
+                .OB(o_ddr3_clk_n), // Diff_n output (connect directly to top-level port)
+                .I(ddr3_clk_delayed) // Buffer input
+            );
+            // End of OBUFDS_inst instantiation
+        end
+    end
+    else begin //ODELAY is not supported
+
+                // if dual rank enabled, then there will be two clk
+        if(DUAL_RANK_DIMM) begin
+            // OBUFDS: Differential Output Buffer
+            // 7 Series
+            // Xilinx HDL Libraries Guide, version 13.4
+            `ifndef SIM_MODEL
+                OBUFDS OBUFDS0_inst (
+            `else 
+                OBUFDS_model OBUFDS0_inst (
+            `endif
+                .O(o_ddr3_clk_p[1]), // Diff_p output (connect directly to top-level port)
+                .OB(o_ddr3_clk_n[1]), // Diff_n output (connect directly to top-level port)
+                .I(!i_ddr3_clk) // Buffer input
+            );
+            `ifndef SIM_MODEL
+                OBUFDS OBUFDS1_inst (
+            `else 
+                OBUFDS_model OBUFDS1_inst (
+            `endif
+                .O(o_ddr3_clk_p[0]), // Diff_p output (connect directly to top-level port)
+                .OB(o_ddr3_clk_n[0]), // Diff_n output (connect directly to top-level port)
+                .I(!i_ddr3_clk) // Buffer input
+            );
+            // End of OBUFDS_inst instantiation
+        end
+        else begin
+            // OBUFDS: Differential Output Buffer
+            // 7 Series
+            // Xilinx HDL Libraries Guide, version 13.4
+            `ifndef SIM_MODEL
+                OBUFDS OBUFDS_inst (
+            `else 
+                OBUFDS_model OBUFDS_inst (
+            `endif
+                .O(o_ddr3_clk_p), // Diff_p output (connect directly to top-level port)
+                .OB(o_ddr3_clk_n), // Diff_n output (connect directly to top-level port)
+                .I(!i_ddr3_clk) // Buffer input
+            );
+        end
+    end
+    
+    
+    // PHY data and dm
+    generate
+        // data: oserdes -> odelay -> iobuf
+        for(gen_index = 0; gen_index < (DQ_BITS*LANES); gen_index = gen_index + 1) begin
+            
+            if (ODELAY_SUPPORTED) begin
+                // OSERDESE2: Output SERial/DESerializer with bitslip
+                //7 Series
+                // Xilinx HDL Libraries Guide, version 13.4
+                `ifndef SIM_MODEL
+                    OSERDESE2 #(
+                `else 
+                    OSERDESE2_model #(
+                `endif
+                    .DATA_RATE_OQ("DDR"), // DDR, SDR
+                    .DATA_RATE_TQ("BUF"), // DDR, SDR
+                    .DATA_WIDTH(8), // Parallel data width (2-8,10,14)
+                    .INIT_OQ(1'b0), // Initial value of OQ output (1'b0,1'b1)
+                    .TRISTATE_WIDTH(1)
+                )
+                OSERDESE2_data(
+                    .OFB(oserdes_data[gen_index]), // 1-bit output: Feedback path for data
+                    .OQ(), // 1-bit output: Data path output
+                    .TQ(oserdes_dq_tri_control[gen_index]),
+                    .CLK(i_ddr3_clk), // 1-bit input: High speed clock
+                    .CLKDIV(i_controller_clk), // 1-bit input: Divided clock
+                    // D1 - D8: 1-bit (each) input: Parallel data inputs (1-bit each)
+                    .D1(i_controller_data[gen_index + (DQ_BITS*LANES)*0]),
+                    .D2(i_controller_data[gen_index + (DQ_BITS*LANES)*1]),
+                    .D3(i_controller_data[gen_index + (DQ_BITS*LANES)*2]),
+                    .D4(i_controller_data[gen_index + (DQ_BITS*LANES)*3]),
+                    .D5(i_controller_data[gen_index + (DQ_BITS*LANES)*4]),
+                    .D6(i_controller_data[gen_index + (DQ_BITS*LANES)*5]),
+                    .D7(i_controller_data[gen_index + (DQ_BITS*LANES)*6]),
+                    .D8(i_controller_data[gen_index + (DQ_BITS*LANES)*7]),
+                    .T1(i_controller_dq_tri_control),
+                    .TCE(1'b1),
+                    .OCE(1'b1), // 1-bit input: Output data clock enable
+                    .RST(sync_rst), // 1-bit input: Reset
+                    // unused signals but were added here to make vivado happy
+                    .SHIFTOUT1(), // SHIFTOUT1 / SHIFTOUT2: 1-bit (each) output: Data output expansion (1-bit each)
+                    .SHIFTOUT2(),
+                    .TBYTEOUT(), // 1-bit output: Byte group tristate
+                    .TFB(), // 1-bit output: 3-state control
+                    // SHIFTIN1 / SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each)
+                    .SHIFTIN1(0),
+                    .SHIFTIN2(0),
+                    // T1 - T4: 1-bit (each) input: Parallel 3-state inputs
+                    .T2(0),
+                    .T3(0),
+                    .T4(0),
+                    .TBYTEIN(0)
+                    // 1-bit input: Byte group tristate
+                );
+                // End of OSERDESE2_inst instantiation
+            
+                // ODELAYE2: Output Fixed or Variable Delay Element
+                // 7 Series
+                // Xilinx HDL Libraries Guide, version 13.4
+                //odelay adds an insertion delay of 600ps to the actual delay setting: https://support.xilinx.com/s/article/42133?language=en_US
+                //Delay the DQ
+                // Delay resolution: 1/(32 x 2 x F REF ) = 78.125ps
+                (* IODELAY_GROUP="DDR3-GROUP" *)
+                `ifndef SIM_MODEL
+                    ODELAYE2 #(
+                `else 
+                    ODELAYE2_model #(
+                `endif
+                    .DELAY_SRC("ODATAIN"), // Delay input (ODATAIN, CLKIN)
+                    .HIGH_PERFORMANCE_MODE("TRUE"), // Reduced jitter to 5ps ("TRUE"), Reduced power but high jitter 9ns ("FALSE")
+                    .ODELAY_TYPE("VAR_LOAD"), // FIXED, VARIABLE, VAR_LOAD, VAR_LOAD_PIPE
+                    .ODELAY_VALUE(DATA_ODELAY_TAP), // Output delay tap setting (0-31)
+                    .REFCLK_FREQUENCY(200.0), // IDELAYCTRL clock input frequency in MHz (190.0-210.0).
+                    .SIGNAL_PATTERN("DATA") // DATA, CLOCK input signal
+                )
+                ODELAYE2_data (
+                    .CNTVALUEOUT(), // 5-bit output: Counter value output
+                    .DATAOUT(odelay_data[gen_index]), // 1-bit output: Delayed data/clock output
+                    .C(i_controller_clk), // 1-bit input: Clock input, when using OSERDESE2, C is connected to CLKDIV
+                    .CE(1'b0), // 1-bit input: Active high enable increment/decrement input
+                    .CINVCTRL(1'b0), // 1-bit input: Dynamic clock inversion input
+                    .CLKIN(1'b0), // 1-bit input: Clock delay input
+                    .CNTVALUEIN(i_controller_odelay_data_cntvaluein), // 5-bit input: Counter value input
+                    .INC(1'b0), // 1-bit input: Increment / Decrement tap delay input
+                    .LD(i_controller_odelay_data_ld[gen_index/8]), // 1-bit input: Loads ODELAY_VALUE tap delay in VARIABLE mode, in VAR_LOAD or
+                                // VAR_LOAD_PIPE mode, loads the value of CNTVALUEIN
+                    .LDPIPEEN(1'b0), // 1-bit input: Enables the pipeline register to load data
+                    .ODATAIN(oserdes_data[gen_index]), // 1-bit input: Output delay data input
+                    .REGRST(1'b0) // 1-bit input: Active-high reset tap-delay input
+                );
+
+                if(USE_IO_TERMINATION) begin 
+                    // IOBUF_DCIEN: Single-ended Bi-directional Buffer with Digital Controlled Impedance (DCI)
+                    // and Input path enable/disable
+                    // May only be placed in High Performance (HP) Banks
+                    // 7 Series
+                    // Xilinx HDL Libraries Guide, version 13.4
+                    `ifndef SIM_MODEL
+                        IOBUF_DCIEN #(
+                    `else 
+                        IOBUF_DCIEN_model #(
+                    `endif
+                    .IBUF_LOW_PWR("FALSE"), // Low Power - "TRUE", High Performance = "FALSE"
+                    .SLEW("FAST"), // Specify the output slew rate
+                    .USE_IBUFDISABLE("FALSE") // Use IBUFDISABLE function, "TRUE" or "FALSE"
+                    ) IOBUF_DCIEN_data (
+                        .O(read_dq[gen_index]), // Buffer output
+                        .IO(io_ddr3_dq[gen_index]), // Buffer inout port (connect directly to top-level port)
+                        .DCITERMDISABLE(1'b0), // DCI Termination enable input
+                        .I(odelay_data[gen_index]), // Buffer input
+                        .IBUFDISABLE(1'b0), // Input disable input, low=disable
+                        .T(oserdes_dq_tri_control[gen_index]) // 3-state enable input, high=input, low=output
+                    );
+                    // End of IOBUF_DCIEN_inst instantiation
+
+                 end
+                 else begin                         
+                    // IOBUF: Single-ended Bi-directional Buffer
+                    //All devices
+                    // Xilinx HDL Libraries Guide, version 13.4
+                    `ifndef SIM_MODEL
+                        IOBUF #(
+                    `else 
+                        IOBUF_model #(
+                    `endif
+                        //.DRIVE(12), // Specify the output drive strength
+                        .IBUF_LOW_PWR("FALSE"), // Low Power - "TRUE", High Performance = "FALSE"
+                        //.IOSTANDARD("SSTL15"), // Specify the I/O standard
+                        .SLEW("FAST") // Specify the output slew rate
+                    ) IOBUF_data (
+                        .O(read_dq[gen_index]),// Buffer output
+                        .IO(io_ddr3_dq[gen_index]), // Buffer inout port (connect directly to top-level port)
+                        .I(odelay_data[gen_index]), // Buffer input
+                        .T(oserdes_dq_tri_control[gen_index]) // 3-state enable input, high=read, low=write
+                    );
+                 end
+            end
+            else begin //ODELAY is not supported
+                // OSERDESE2: Output SERial/DESerializer with bitslip
+                //7 Series
+                // Xilinx HDL Libraries Guide, version 13.4
+                `ifndef SIM_MODEL
+                    OSERDESE2 #(
+                `else 
+                    OSERDESE2_model #(
+                `endif
+                    .DATA_RATE_OQ("DDR"), // DDR, SDR
+                    .DATA_RATE_TQ("BUF"), // DDR, SDR
+                    .DATA_WIDTH(8), // Parallel data width (2-8,10,14)
+                    .INIT_OQ(1'b0), // Initial value of OQ output (1'b0,1'b1)
+                    .TRISTATE_WIDTH(1)
+                )
+                OSERDESE2_data(
+                    .OFB(), // 1-bit output: Feedback path for data
+                    .OQ(oserdes_data[gen_index]), // 1-bit output: Data path output
+                    .TQ(oserdes_dq_tri_control[gen_index]),
+                    .CLK(i_ddr3_clk_90), // 1-bit input: High speed clock
+                    .CLKDIV(i_controller_clk), // 1-bit input: Divided clock
+                    // D1 - D8: 1-bit (each) input: Parallel data inputs (1-bit each)
+                    .D1(i_controller_data[gen_index + (DQ_BITS*LANES)*0]),
+                    .D2(i_controller_data[gen_index + (DQ_BITS*LANES)*1]),
+                    .D3(i_controller_data[gen_index + (DQ_BITS*LANES)*2]),
+                    .D4(i_controller_data[gen_index + (DQ_BITS*LANES)*3]),
+                    .D5(i_controller_data[gen_index + (DQ_BITS*LANES)*4]),
+                    .D6(i_controller_data[gen_index + (DQ_BITS*LANES)*5]),
+                    .D7(i_controller_data[gen_index + (DQ_BITS*LANES)*6]),
+                    .D8(i_controller_data[gen_index + (DQ_BITS*LANES)*7]),
+                    .T1(i_controller_dq_tri_control),
+                    .TCE(1'b1),
+                    .OCE(1'b1), // 1-bit input: Output data clock enable
+                    .RST(sync_rst), // 1-bit input: Reset
+                    // unused signals but were added here to make vivado happy
+                    .SHIFTOUT1(), // SHIFTOUT1 / SHIFTOUT2: 1-bit (each) output: Data output expansion (1-bit each)
+                    .SHIFTOUT2(),
+                    .TBYTEOUT(), // 1-bit output: Byte group tristate
+                    .TFB(), // 1-bit output: 3-state control
+                    // SHIFTIN1 / SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each)
+                    .SHIFTIN1(0),
+                    .SHIFTIN2(0),
+                    // T1 - T4: 1-bit (each) input: Parallel 3-state inputs
+                    .T2(0),
+                    .T3(0),
+                    .T4(0),
+                    .TBYTEIN(0)
+                    // 1-bit input: Byte group tristate
+                );
+                // End of OSERDESE2_inst instantiation
+                
+                // IOBUF: Single-ended Bi-directional Buffer
+                //All devices
+                // Xilinx HDL Libraries Guide, version 13.4
+                `ifndef SIM_MODEL
+                    IOBUF #(
+                `else 
+                    IOBUF_model #(
+                `endif
+                    //.DRIVE(12), // Specify the output drive strength
+                    .IBUF_LOW_PWR("FALSE"), // Low Power - "TRUE", High Performance = "FALSE"
+                    //.IOSTANDARD("SSTL15"), // Specify the I/O standard
+                    .SLEW("FAST") // Specify the output slew rate
+                ) IOBUF_data (
+                    .O(read_dq[gen_index]),// Buffer output
+                    .IO(io_ddr3_dq[gen_index]), // Buffer inout port (connect directly to top-level port)
+                    .I(oserdes_data[gen_index]), // Buffer input
+                    .T(oserdes_dq_tri_control[gen_index]) // 3-state enable input, high=read, low=write
+                );
+            end
+
+            // IDELAYE2: Input Fixed or Variable Delay Element
+            // 7 Series
+            // Xilinx HDL Libraries Guide, version 13.4
+            (* IODELAY_GROUP="DDR3-GROUP" *)
+            `ifndef SIM_MODEL
+                IDELAYE2 #(
+            `else 
+                IDELAYE2_model #(
+            `endif
+                .DELAY_SRC("IDATAIN"), // Delay input (IDATAIN, DATAIN)
+                .HIGH_PERFORMANCE_MODE("TRUE"), //Reduced jitter ("TRUE"), Reduced power ("FALSE")
+                .IDELAY_TYPE("VAR_LOAD"), //FIXED, VARIABLE, VAR_LOAD, VAR_LOAD_PIPE
+                .IDELAY_VALUE(DATA_IDELAY_TAP), //Input delay tap setting (0-31)
+                .PIPE_SEL("FALSE"),  //Select pipelined mode, FALSE, TRUE
+                .REFCLK_FREQUENCY(200.0), //IDELAYCTRL clock input frequency in MHz (190.0-210.0).
+                .SIGNAL_PATTERN("DATA") //DATA, CLOCK input signal
+            )
+            IDELAYE2_data (
+                .CNTVALUEOUT(), // 5-bit output: Counter value output
+                .DATAOUT(idelay_data[gen_index]), // 1-bit output: Delayed data output
+                .C(i_controller_clk), // 1-bit input: Clock input
+                .CE(1'b0), // 1-bit input: Active high enable increment/decrement input
+                .CINVCTRL(1'b0),// 1-bit input: Dynamic clock inversion input
+                .CNTVALUEIN(i_controller_idelay_data_cntvaluein), // 5-bit input: Counter value input
+                .DATAIN(), //1-bit input: Internal delay data input
+                .IDATAIN(read_dq[gen_index]), // 1-bit input: Data input from the I/O
+                .INC(1'b0), // 1-bit input: Increment / Decrement tap delay input
+                .LD(i_controller_idelay_data_ld[gen_index/8]), // 1-bit input: Load IDELAY_VALUE input
+                .LDPIPEEN(1'b0), // 1-bit input: Enable PIPELINE register to load data input
+                .REGRST(1'b0) // 1-bit input: Active-high reset tap-delay input
+            );
+            // End of IDELAYE2_inst instantiation
+
+            // End of IOBUF_inst instantiation                 
+            // ISERDESE2: Input SERial/DESerializer with bitslip
+            //7 Series
+            // Xilinx HDL Libraries Guide, version 13.4
+            `ifndef SIM_MODEL
+                ISERDESE2 #(
+            `else 
+                ISERDESE2_model #(
+            `endif
+                .DATA_RATE("DDR"), // DDR, SDR
+                .DATA_WIDTH(8), // Parallel data width (2-8,10,14)
+                // INIT_Q1 - INIT_Q4: Initial value on the Q outputs (0/1)
+                .INIT_Q1(1'b0),
+                .INIT_Q2(1'b0),
+                .INIT_Q3(1'b0),
+                .INIT_Q4(1'b0),
+                .INTERFACE_TYPE("NETWORKING"), // MEMORY, MEMORY_DDR3, MEMORY_QDR, NETWORKING, OVERSAMPLE
+                .IOBDELAY("IFD"), // NONE, BOTH, IBUF, IFD
+                .NUM_CE(1),// Number of clock enables (1,2)
+                .OFB_USED("FALSE"), // Select OFB path (FALSE, TRUE)
+                // SRVAL_Q1 - SRVAL_Q4: Q output values when SR is used (0/1)
+                .SRVAL_Q1(1'b0),
+                .SRVAL_Q2(1'b0),
+                .SRVAL_Q3(1'b0),
+                .SRVAL_Q4(1'b0)
+            )
+            ISERDESE2_data (
+                .O(),
+                // 1-bit output: Combinatorial output
+                // Q1 - Q8: 1-bit (each) output: Registered data outputs
+                .Q1(o_controller_iserdes_data[(DQ_BITS*LANES)*7 + gen_index]),//56
+                .Q2(o_controller_iserdes_data[(DQ_BITS*LANES)*6 + gen_index]), //48
+                .Q3(o_controller_iserdes_data[(DQ_BITS*LANES)*5 + gen_index]),
+                .Q4(o_controller_iserdes_data[(DQ_BITS*LANES)*4 + gen_index]),   
+                .Q5(o_controller_iserdes_data[(DQ_BITS*LANES)*3 + gen_index]),
+                .Q6(o_controller_iserdes_data[(DQ_BITS*LANES)*2 + gen_index]),
+                .Q7(o_controller_iserdes_data[(DQ_BITS*LANES)*1 + gen_index]), 
+                .Q8(o_controller_iserdes_data[(DQ_BITS*LANES)*0 + gen_index]),
+                // SHIFTOUT1-SHIFTOUT2: 1-bit (each) output: Data width expansion output ports
+                .SHIFTOUT1(),
+                .SHIFTOUT2(),
+                .BITSLIP(i_controller_bitslip[gen_index/8]),
+                // 1-bit input: The BITSLIP pin performs a Bitslip operation synchronous to
+                // CLKDIV when asserted (active High). Subsequently, the data seen on the Q1
+                // to Q8 output ports will shift, as in a barrel-shifter operation, one
+                // position every time Bitslip is invoked (DDR operation is different from
+                // SDR).
+                // CE1, CE2: 1-bit (each) input: Data register clock enable inputs
+                .CE1(1'b1),
+                .CE2(1'b1),
+                .CLKDIVP(), // 1-bit input: TBD
+                // Clocks: 1-bit (each) input: ISERDESE2 clock input ports
+                .CLK(i_ddr3_clk), // 1-bit input: High-speed clock
+                .CLKB(!i_ddr3_clk), // 1-bit input: High-speed secondary clock
+                .CLKDIV(i_controller_clk), // 1-bit input: Divided clock
+                .OCLK(), // 1-bit input: High speed output clock used when INTERFACE_TYPE="MEMORY"
+                // Dynamic Clock Inversions: 1-bit (each) input: Dynamic clock inversion pins to switch clock polarity
+                .DYNCLKDIVSEL(), // 1-bit input: Dynamic CLKDIV inversion
+                .DYNCLKSEL(), // 1-bit input: Dynamic CLK/CLKB inversion
+                // Input Data: 1-bit (each) input: ISERDESE2 data input ports
+                .D(), // 1-bit input: Data input
+                .DDLY(idelay_data[gen_index]), // 1-bit input: Serial data from IDELAYE2
+                .OFB(), // 1-bit input: Data feedback from OSERDESE2
+                .OCLKB(), // 1-bit input: High speed negative edge output clock
+                .RST(sync_rst), // 1-bit input: Active high asynchronous reset
+                // SHIFTIN1-SHIFTIN2: 1-bit (each) input: Data width expansion input ports
+                .SHIFTIN1(),
+                .SHIFTIN2()
+            );
+            // End of ISERDESE2_inst instantiation
+  
+        end
+        
+        // data mask: oserdes -> odelay -> obuf
+        for(gen_index = 0; gen_index < LANES; gen_index = gen_index + 1) begin
+ 
+            
+            if(ODELAY_SUPPORTED) begin
+                // OSERDESE2: Output SERial/DESerializer with bitslip
+                //7 Series
+                // Xilinx HDL Libraries Guide, version 13.4
+                `ifndef SIM_MODEL
+                    OSERDESE2 #(
+                `else 
+                    OSERDESE2_model #(
+                `endif
+                    .DATA_RATE_OQ("DDR"), // DDR, SDR
+                    .DATA_RATE_TQ("BUF"), // DDR, SDR
+                    .DATA_WIDTH(8), // Parallel data width (2-8,10,14)
+                    .INIT_OQ(1'b0), // Initial value of OQ output (1'b0,1'b1)
+                    .TRISTATE_WIDTH(1)
+                )
+                OSERDESE2_dm(
+                    .OFB(oserdes_dm[gen_index]), // 1-bit output: Feedback path for data
+                    .OQ(), // 1-bit output: Data path output
+                    .CLK(i_ddr3_clk), // 1-bit input: High speed clock
+                    .CLKDIV(i_controller_clk), // 1-bit input: Divided clock
+                    // D1 - D8: 1-bit (each) input: Parallel data inputs (1-bit each)
+                    .D1(i_controller_dm[gen_index + LANES*0]),
+                    .D2(i_controller_dm[gen_index + LANES*1]),
+                    .D3(i_controller_dm[gen_index + LANES*2]),
+                    .D4(i_controller_dm[gen_index + LANES*3]),
+                    .D5(i_controller_dm[gen_index + LANES*4]),
+                    .D6(i_controller_dm[gen_index + LANES*5]),
+                    .D7(i_controller_dm[gen_index + LANES*6]),
+                    .D8(i_controller_dm[gen_index + LANES*7]), 
+                    .TCE(1'b0),
+                    .OCE(1'b1), // 1-bit input: Output data clock enable
+                    .RST(sync_rst), // 1-bit input: Reset
+                     // unused signals but were added here to make vivado happy
+                    .SHIFTOUT1(), // SHIFTOUT1 / SHIFTOUT2: 1-bit (each) output: Data output expansion (1-bit each)
+                    .SHIFTOUT2(),
+                    .TBYTEOUT(), // 1-bit output: Byte group tristate
+                    .TFB(), // 1-bit output: 3-state control
+                    .TQ(), // 1-bit output: 3-state control
+                    // SHIFTIN1 / SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each)
+                    .SHIFTIN1(0),
+                    .SHIFTIN2(0),
+                    // T1 - T4: 1-bit (each) input: Parallel 3-state inputs
+                    .T1(0),
+                    .T2(0),
+                    .T3(0),
+                    .T4(0),
+                    .TBYTEIN(0)
+                    // 1-bit input: Byte group tristate
+                );
+                // End of OSERDESE2_inst instantiation
+            
+                // ODELAYE2: Output Fixed or Variable Delay Element
+                // 7 Series
+                // Xilinx HDL Libraries Guide, version 13.4
+                //odelay adds an insertion delay of 600ps to the actual delay setting: https://support.xilinx.com/s/article/42133?language=en_US
+                //Delay the DQ
+                // Delay resolution: 1/(32 x 2 x F REF ) = 78.125ps
+                (* IODELAY_GROUP="DDR3-GROUP" *)
+                `ifndef SIM_MODEL
+                    ODELAYE2 #(
+                `else 
+                    ODELAYE2_model #(
+                `endif
+                    .DELAY_SRC("ODATAIN"), // Delay input (ODATAIN, CLKIN)
+                    .HIGH_PERFORMANCE_MODE("TRUE"), // Reduced jitter to 5ps ("TRUE"), Reduced power but high jitter 9ns ("FALSE")
+                    .ODELAY_TYPE("VAR_LOAD"), // FIXED, VARIABLE, VAR_LOAD, VAR_LOAD_PIPE
+                    .ODELAY_VALUE(DATA_ODELAY_TAP), // Output delay tap setting (0-31)
+                    .REFCLK_FREQUENCY(200.0), // IDELAYCTRL clock input frequency in MHz (190.0-210.0).
+                    .SIGNAL_PATTERN("DATA") // DATA, CLOCK input signal
+                )
+                ODELAYE2_dm (
+                    .CNTVALUEOUT(), // 5-bit output: Counter value output
+                    .DATAOUT(odelay_dm[gen_index]), // 1-bit output: Delayed data/clock output
+                    .C(i_controller_clk), // 1-bit input: Clock input, when using OSERDESE2, C is connected to CLKDIV
+                    .CE(1'b0), // 1-bit input: Active high enable increment/decrement input
+                    .CINVCTRL(1'b0), // 1-bit input: Dynamic clock inversion input
+                    .CLKIN(1'b0), // 1-bit input: Clock delay input
+                    .CNTVALUEIN(i_controller_odelay_data_cntvaluein), // 5-bit input: Counter value input
+                    .INC(1'b0), // 1-bit input: Increment / Decrement tap delay input
+                    .LD(i_controller_odelay_data_ld[gen_index]), // 1-bit input: Loads ODELAY_VALUE tap delay in VARIABLE mode, in VAR_LOAD or
+                                // VAR_LOAD_PIPE mode, loads the value of CNTVALUEIN
+                    .LDPIPEEN(1'b0), // 1-bit input: Enables the pipeline register to load data
+                    .ODATAIN(oserdes_dm[gen_index]), // 1-bit input: Output delay data input
+                    .REGRST(1'b0) // 1-bit input: Active-high reset tap-delay input
+                );
+                
+                // OBUF: Single-ended Output Buffer
+                // 7 Series
+                // Xilinx HDL Libraries Guide, version 13.4
+                `ifndef SIM_MODEL
+                    OBUF #(
+                `else 
+                    OBUF_model #(
+                `endif
+                //.IOSTANDARD("SSTL_15"), // Specify the output I/O standard
+                .SLEW("FAST") // Specify the output slew rate
+                ) OBUF_dm (
+                    .O(o_ddr3_dm[gen_index]), // Buffer output (connect directly to top-level port)
+                    .I(odelay_dm[gen_index]) // Buffer input
+                );
+                // End of OBUF_inst instantiation
+            end
+            else begin
+                // OSERDESE2: Output SERial/DESerializer with bitslip
+                //7 Series
+                // Xilinx HDL Libraries Guide, version 13.4
+                `ifndef SIM_MODEL
+                    OSERDESE2 #(
+                `else 
+                    OSERDESE2_model #(
+                `endif
+                    .DATA_RATE_OQ("DDR"), // DDR, SDR
+                    .DATA_RATE_TQ("BUF"), // DDR, SDR
+                    .DATA_WIDTH(8), // Parallel data width (2-8,10,14)
+                    .INIT_OQ(1'b0), // Initial value of OQ output (1'b0,1'b1)
+                    .TRISTATE_WIDTH(1)
+                )
+                OSERDESE2_dm(
+                    .OFB(), // 1-bit output: Feedback path for data
+                    .OQ(oserdes_dm[gen_index]), // 1-bit output: Data path output
+                    .CLK(i_ddr3_clk_90), // 1-bit input: High speed clock
+                    .CLKDIV(i_controller_clk), // 1-bit input: Divided clock
+                    // D1 - D8: 1-bit (each) input: Parallel data inputs (1-bit each)
+                    .D1(i_controller_dm[gen_index + LANES*0]),
+                    .D2(i_controller_dm[gen_index + LANES*1]),
+                    .D3(i_controller_dm[gen_index + LANES*2]),
+                    .D4(i_controller_dm[gen_index + LANES*3]),
+                    .D5(i_controller_dm[gen_index + LANES*4]),
+                    .D6(i_controller_dm[gen_index + LANES*5]),
+                    .D7(i_controller_dm[gen_index + LANES*6]),
+                    .D8(i_controller_dm[gen_index + LANES*7]), 
+                    .TCE(1'b0),
+                    .OCE(1'b1), // 1-bit input: Output data clock enable
+                    .RST(sync_rst), // 1-bit input: Reset
+                     // unused signals but were added here to make vivado happy
+                    .SHIFTOUT1(), // SHIFTOUT1 / SHIFTOUT2: 1-bit (each) output: Data output expansion (1-bit each)
+                    .SHIFTOUT2(),
+                    .TBYTEOUT(), // 1-bit output: Byte group tristate
+                    .TFB(), // 1-bit output: 3-state control
+                    .TQ(), // 1-bit output: 3-state control
+                    // SHIFTIN1 / SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each)
+                    .SHIFTIN1(0),
+                    .SHIFTIN2(0),
+                    // T1 - T4: 1-bit (each) input: Parallel 3-state inputs
+                    .T1(0),
+                    .T2(0),
+                    .T3(0),
+                    .T4(0),
+                    .TBYTEIN(0)
+                    // 1-bit input: Byte group tristate
+                );
+                // End of OSERDESE2_inst instantiation
+            
+                // OBUF: Single-ended Output Buffer
+                // 7 Series
+                // Xilinx HDL Libraries Guide, version 13.4
+                `ifndef SIM_MODEL
+                    OBUF #(
+                `else 
+                    OBUF_model #(
+                `endif
+                //.IOSTANDARD("SSTL_15"), // Specify the output I/O standard
+                .SLEW("FAST") // Specify the output slew rate
+                ) OBUF_dm (
+                    .O(o_ddr3_dm[gen_index]), // Buffer output (connect directly to top-level port)
+                    .I(oserdes_dm[gen_index]) // Buffer input
+                );
+                // End of OBUF_inst instantiation
+            
+            end
+        end
+
+        // dqs: odelay -> iobuf
+        for(gen_index = 0; gen_index < LANES; gen_index = gen_index + 1) begin
+`ifndef DEBUG_DQS  //remove the logic for dqs if needs to be debugged (directed to output instead)  
+            if(ODELAY_SUPPORTED) begin 
+                // OSERDESE2: Output SERial/DESerializer with bitslip
+                //7 Series
+                // Xilinx HDL Libraries Guide, version 13.4
+                `ifndef SIM_MODEL
+                    OSERDESE2 #(
+                `else 
+                    OSERDESE2_model #(
+                `endif
+                    .DATA_RATE_OQ("DDR"), // DDR, SDR
+                    .DATA_RATE_TQ("BUF"), // DDR, SDR
+                    .DATA_WIDTH(8), // Parallel data width (2-8,10,14)
+                    .INIT_OQ(1'b1), // Initial value of OQ output (1'b0,1'b1)
+                    .TRISTATE_WIDTH(1)
+                )
+                OSERDESE2_dqs(
+                    .OFB(oserdes_dqs[gen_index]), // 1-bit output: Feedback path for data
+                    .OQ(), // 1-bit output: Data path output
+                    .TQ(oserdes_dqs_tri_control[gen_index]),
+                    .CLK(i_ddr3_clk), // 1-bit input: High speed clock
+                    .CLKDIV(i_controller_clk), // 1-bit input: Divided clock
+                    // D1 - D8: 1-bit (each) input: Parallel data inputs (1-bit each)
+                    .D1(1'b1 && (i_controller_toggle_dqs || toggle_dqs_q)), //the last part will still have half dqs series
+                    .D2(1'b0 && (i_controller_toggle_dqs || toggle_dqs_q)),
+                    .D3(1'b1 && (i_controller_toggle_dqs || toggle_dqs_q) && !i_controller_write_leveling_calib),
+                    .D4(1'b0 && (i_controller_toggle_dqs || toggle_dqs_q)),
+                    .D5(1'b1 && i_controller_toggle_dqs && !i_controller_write_leveling_calib),
+                    .D6(1'b0 && i_controller_toggle_dqs),
+                    .D7(1'b1 && i_controller_toggle_dqs && !i_controller_write_leveling_calib),
+                    .D8(1'b0 && i_controller_toggle_dqs),
+                    .T1(i_controller_dqs_tri_control),
+                    .TCE(1'b1),
+                    .OCE(1'b1), // 1-bit input: Output data clock enable
+                    .RST(sync_rst), // 1-bit input: Reset
+                     // unused signals but were added here to make vivado happy
+                    .SHIFTOUT1(), // SHIFTOUT1 / SHIFTOUT2: 1-bit (each) output: Data output expansion (1-bit each)
+                    .SHIFTOUT2(),
+                    .TBYTEOUT(), // 1-bit output: Byte group tristate
+                    .TFB(), // 1-bit output: 3-state control
+                    // SHIFTIN1 / SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each)
+                    .SHIFTIN1(0),
+                    .SHIFTIN2(0),
+                    // T1 - T4: 1-bit (each) input: Parallel 3-state inputs
+                    .T2(0),
+                    .T3(0),
+                    .T4(0),
+                    .TBYTEIN(0)
+                    // 1-bit input: Byte group tristate
+                );
+                // End of OSERDESE2_inst instantiation
+            
+            
+                // ODELAYE2: Output Fixed or Variable Delay Element
+                // 7 Series
+                // Xilinx HDL Libraries Guide, version 13.4
+                //Delay the DQ
+                (* IODELAY_GROUP="DDR3-GROUP" *)
+                `ifndef SIM_MODEL
+                    ODELAYE2 #(
+                `else 
+                    ODELAYE2_model #(
+                `endif
+                    .DELAY_SRC("ODATAIN"), // Delay input (ODATAIN, CLKIN)
+                    .HIGH_PERFORMANCE_MODE("TRUE"), // Reduced jitter ("TRUE"), Reduced power ("FALSE")
+                    .ODELAY_TYPE("VAR_LOAD"), // FIXED, VARIABLE, VAR_LOAD, VAR_LOAD_PIPE
+                    .ODELAY_VALUE(DQS_ODELAY_TAP), // delay to align odelay_dqs to oserdes_dqs due to 600ps insertion delay: (1/800MHz - 600ps)/78.125ps = 8.32 taps
+                    .REFCLK_FREQUENCY(200.0), // IDELAYCTRL clock input frequency in MHz (190.0-210.0).
+                    .SIGNAL_PATTERN("DATA") // DATA, CLOCK input signal
+                )
+                ODELAYE2_dqs (
+                    .CNTVALUEOUT(), // 5-bit output: Counter value output
+                    .DATAOUT(odelay_dqs[gen_index]), // 1-bit output: Delayed data/clock output
+                    .C(i_controller_clk), // 1-bit input: Clock input, when using OSERDESE2, C is connected to CLKDIV
+                    .CE(1'b0), // 1-bit input: Active high enable increment/decrement input
+                    .CINVCTRL(1'b0), // 1-bit input: Dynamic clock inversion input
+                    .CLKIN(1'b0), // 1-bit input: Clock delay input
+                    .CNTVALUEIN(i_controller_odelay_dqs_cntvaluein), // 5-bit input: Counter value input
+                    .INC(1'b0), // 1-bit input: Increment / Decrement tap delay input
+                    .LD(i_controller_odelay_dqs_ld[gen_index]), // 1-bit input: Loads ODELAY_VALUE tap delay in VARIABLE mode, in VAR_LOAD or
+                                // VAR_LOAD_PIPE mode, loads the value of CNTVALUEIN
+                    .LDPIPEEN(1'b0), // 1-bit input: Enables the pipeline register to load data
+                    .ODATAIN(oserdes_dqs[gen_index]), // 1-bit input: Output delay data input
+                    .REGRST(1'b0) // 1-bit input: Active-high reset tap-delay input
+                );
+                
+                if(USE_IO_TERMINATION) begin 
+                    // IOBUFDS_DCIEN: Differential Bi-directional Buffer with Digital Controlled Impedance (DCI)
+                    // and Input path enable/disable
+                    // May only be placed in High Performance (HP) Banks
+                    // 7 Series
+                    // Xilinx HDL Libraries Guide, version 13.4
+                    `ifndef SIM_MODEL
+                        IOBUFDS_DCIEN #(
+                    `else 
+                        IOBUFDS_DCIEN_model #(
+                    `endif
+                        .IBUF_LOW_PWR("FALSE"), // Low Power - "TRUE", High Performance = "FALSE"
+                        .SLEW("FAST"), // Specify the output slew rate
+                        .USE_IBUFDISABLE("FALSE") // Use IBUFDISABLE function, "TRUE" or "FALSE"
+                    ) IOBUFDS_DCIEN_inst (
+                        .O(read_dqs[gen_index]),  // Buffer output
+                        .IO(io_ddr3_dqs[gen_index]), // Diff_p inout (connect directly to top-level port)
+                        .IOB(io_ddr3_dqs_n[gen_index]), // Diff_n inout (connect directly to top-level port)
+                        .DCITERMDISABLE(1'b0), // DCI Termination enable input
+                        .I(odelay_dqs[gen_index]), // Buffer input
+                        .IBUFDISABLE(1'b0), // Input disable input, low=disable
+                        .T(oserdes_dqs_tri_control[gen_index]) // 3-state enable input, high=input, low=output
+                    );
+                    // End of IOBUFDS_DCIEN_inst instantiation
+
+                end
+                else begin
+                    // IOBUFDS: Differential Bi-directional Buffer
+                    //7 Series
+                    // Xilinx HDL Libraries Guide, version 13.4
+                    `ifndef SIM_MODEL
+                        IOBUFDS #(
+                    `else 
+                        IOBUFDS_model #(
+                    `endif
+                        //.DIFF_TERM("FALSE"), // Differential Termination ("TRUE"/"FALSE")
+                        .IBUF_LOW_PWR("FALSE") // Low Power - "TRUE", High Performance = "FALSE"
+                        //.IOSTANDARD("DIFF_SSTL15") // Specify the I/O standard. CONSULT WITH DATASHEET
+                        //.SLEW("FAST") // Specify the output slew rate
+                    ) IOBUFDS_dqs (
+                        .O(read_dqs[gen_index]), // Buffer output
+                        .IO(io_ddr3_dqs[gen_index]), // Diff_p inout (connect directly to top-level port)
+                        .IOB(io_ddr3_dqs_n[gen_index]), // Diff_n inout (connect directly to top-level port)
+                        .I(odelay_dqs[gen_index]), // Buffer input
+                        .T(/*!dqs_tri_control[gen_index]*/oserdes_dqs_tri_control[gen_index]) // 3-state enable input, high=input, low=output
+                    ); // End of IOBUFDS_inst instantiation
+                end
+                
+            end
+            
+            else begin //ODELAY not supported
+                // OSERDESE2: Output SERial/DESerializer with bitslip
+                //7 Series
+                // Xilinx HDL Libraries Guide, version 13.4
+                `ifndef SIM_MODEL
+                    OSERDESE2 #(
+                `else 
+                    OSERDESE2_model #(
+                `endif
+                    .DATA_RATE_OQ("DDR"), // DDR, SDR
+                    .DATA_RATE_TQ("BUF"), // DDR, SDR
+                    .DATA_WIDTH(8), // Parallel data width (2-8,10,14)
+                    .INIT_OQ(1'b1), // Initial value of OQ output (1'b0,1'b1)
+                    .TRISTATE_WIDTH(1)
+                )
+                OSERDESE2_dqs(
+                    .OFB(), // 1-bit output: Feedback path for data
+                    .OQ(oserdes_dqs[gen_index]), // 1-bit output: Data path output
+                    .TQ(oserdes_dqs_tri_control[gen_index]),
+                    .CLK(!i_ddr3_clk), // 1-bit input: High speed clock
+                    .CLKDIV(i_controller_clk), // 1-bit input: Divided clock
+                    // D1 - D8: 1-bit (each) input: Parallel data inputs (1-bit each)
+                    .D1(1'b1 && (i_controller_toggle_dqs || toggle_dqs_q)), //the last part will still have half dqs series
+                    .D2(1'b0 && (i_controller_toggle_dqs || toggle_dqs_q)),
+                    .D3(1'b1 && (i_controller_toggle_dqs || toggle_dqs_q) && !i_controller_write_leveling_calib),
+                    .D4(1'b0 && (i_controller_toggle_dqs || toggle_dqs_q)),
+                    .D5(1'b1 && i_controller_toggle_dqs && !i_controller_write_leveling_calib),
+                    .D6(1'b0 && i_controller_toggle_dqs),
+                    .D7(1'b1 && i_controller_toggle_dqs && !i_controller_write_leveling_calib),
+                    .D8(1'b0 && i_controller_toggle_dqs),
+                    .T1(i_controller_dqs_tri_control),
+                    .TCE(1'b1),
+                    .OCE(1'b1), // 1-bit input: Output data clock enable
+                    .RST(sync_rst), // 1-bit input: Reset
+                     // unused signals but were added here to make vivado happy
+                    .SHIFTOUT1(), // SHIFTOUT1 / SHIFTOUT2: 1-bit (each) output: Data output expansion (1-bit each)
+                    .SHIFTOUT2(),
+                    .TBYTEOUT(), // 1-bit output: Byte group tristate
+                    .TFB(), // 1-bit output: 3-state control
+                    // SHIFTIN1 / SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each)
+                    .SHIFTIN1(0),
+                    .SHIFTIN2(0),
+                    // T1 - T4: 1-bit (each) input: Parallel 3-state inputs
+                    .T2(0),
+                    .T3(0),
+                    .T4(0),
+                    .TBYTEIN(0)
+                    // 1-bit input: Byte group tristate
+                );
+                // End of OSERDESE2_inst instantiation
+                
+                // IOBUFDS: Differential Bi-directional Buffer
+                //7 Series
+                // Xilinx HDL Libraries Guide, version 13.4
+                `ifndef SIM_MODEL
+                    IOBUFDS #(
+                `else 
+                    IOBUFDS_model #(
+                `endif
+                    //.DIFF_TERM("FALSE"), // Differential Termination ("TRUE"/"FALSE")
+                    .IBUF_LOW_PWR("FALSE") // Low Power - "TRUE", High Performance = "FALSE"
+                    //.IOSTANDARD("DIFF_SSTL15") // Specify the I/O standard. CONSULT WITH DATASHEET
+                    //.SLEW("FAST") // Specify the output slew rate
+                ) IOBUFDS_dqs (
+                    .O(read_dqs[gen_index]), // Buffer output
+                    .IO(io_ddr3_dqs[gen_index]), // Diff_p inout (connect directly to top-level port)
+                    .IOB(io_ddr3_dqs_n[gen_index]), // Diff_n inout (connect directly to top-level port)
+                    .I(oserdes_dqs[gen_index]), // Buffer input
+                    .T(/*!dqs_tri_control[gen_index]*/oserdes_dqs_tri_control[gen_index]) // 3-state enable input, high=input, low=output
+                ); // End of IOBUFDS_inst instantiation
+                
+            end
+            
+            // IDELAYE2: Input Fixed or Variable Delay Element
+            // 7 Series
+            // Xilinx HDL Libraries Guide, version 13.4
+            (* IODELAY_GROUP="DDR3-GROUP" *)
+            `ifndef SIM_MODEL
+                IDELAYE2 #(
+            `else 
+                IDELAYE2_model #(
+            `endif
+                .DELAY_SRC("IDATAIN"), // Delay input (IDATAIN, DATAIN)
+                .HIGH_PERFORMANCE_MODE("TRUE"), //Reduced jitter ("TRUE"), Reduced power ("FALSE")
+                .IDELAY_TYPE("VAR_LOAD"), //FIXED, VARIABLE, VAR_LOAD, VAR_LOAD_PIPE
+                .IDELAY_VALUE(DQS_IDELAY_TAP), //Input delay tap setting (0-31)
+                .PIPE_SEL("FALSE"),  //Select pipelined mode, FALSE, TRUE
+                .REFCLK_FREQUENCY(200.0), //IDELAYCTRL clock input frequency in MHz (190.0-210.0).
+                .SIGNAL_PATTERN("CLOCK") //DATA, CLOCK input signal
+            )
+            IDELAYE2_dqs (
+                .CNTVALUEOUT(), // 5-bit output: Counter value output
+                .DATAOUT(idelay_dqs[gen_index]), // 1-bit output: Delayed data output
+                .C(i_controller_clk), // 1-bit input: Clock input
+                .CE(1'b0), // 1-bit input: Active high enable increment/decrement input
+                .CINVCTRL(1'b0),// 1-bit input: Dynamic clock inversion input
+                .CNTVALUEIN(i_controller_idelay_dqs_cntvaluein), // 5-bit input: Counter value input
+                .DATAIN(), //1-bit input: Internal delay data input
+                .IDATAIN(read_dqs[gen_index]), // 1-bit input: Data input from the I/O
+                .INC(1'b0), // 1-bit input: Increment / Decrement tap delay input
+                .LD(i_controller_idelay_dqs_ld[gen_index]), // 1-bit input: Load IDELAY_VALUE input
+                .LDPIPEEN(1'b0), // 1-bit input: Enable PIPELINE register to load data input
+                .REGRST(1'b0) // 1-bit input: Active-high reset tap-delay input
+            );
+            // End of IDELAYE2_inst instantiation
+            
+             
+              // End of IOBUF_inst instantiation                 
+            // ISERDESE2: Input SERial/DESerializer with bitslip
+            //7 Series
+            // Xilinx HDL Libraries Guide, version 13.4
+            `ifndef SIM_MODEL
+                ISERDESE2 #(
+            `else 
+                ISERDESE2_model #(
+            `endif
+                .DATA_RATE("DDR"), // DDR, SDR
+                .DATA_WIDTH(serdes_ratio*2), // Parallel data width (2-8,10,14)
+                // INIT_Q1 - INIT_Q4: Initial value on the Q outputs (0/1)
+                .INIT_Q1(1'b0),
+                .INIT_Q2(1'b0),
+                .INIT_Q3(1'b0),
+                .INIT_Q4(1'b0),
+                .INTERFACE_TYPE("NETWORKING"), // MEMORY, MEMORY_DDR3, MEMORY_QDR, NETWORKING, OVERSAMPLE
+                .IOBDELAY("IFD"), // NONE, BOTH, IBUF, IFD
+                .NUM_CE(1),// Number of clock enables (1,2)
+                .OFB_USED("FALSE"), // Select OFB path (FALSE, TRUE)
+                // SRVAL_Q1 - SRVAL_Q4: Q output values when SR is used (0/1)
+                .SRVAL_Q1(1'b0),
+                .SRVAL_Q2(1'b0),
+                .SRVAL_Q3(1'b0),
+                .SRVAL_Q4(1'b0)
+            )
+            ISERDESE2_dqs (
+                .O(),
+                // 1-bit output: Combinatorial output
+                // Q1 - Q8: 1-bit (each) output: Registered data outputs
+                .Q1(o_controller_iserdes_dqs[serdes_ratio*2*gen_index + 7]),
+                .Q2(o_controller_iserdes_dqs[serdes_ratio*2*gen_index + 6]),
+                .Q3(o_controller_iserdes_dqs[serdes_ratio*2*gen_index + 5]),
+                .Q4(o_controller_iserdes_dqs[serdes_ratio*2*gen_index + 4]),   
+                .Q5(o_controller_iserdes_dqs[serdes_ratio*2*gen_index + 3]),
+                .Q6(o_controller_iserdes_dqs[serdes_ratio*2*gen_index + 2]), //
+                .Q7(o_controller_iserdes_dqs[serdes_ratio*2*gen_index + 1]), //3
+                .Q8(o_controller_iserdes_dqs[serdes_ratio*2*gen_index + 0]), //2
+                // SHIFTOUT1-SHIFTOUT2: 1-bit (each) output: Data width expansion output ports
+                .SHIFTOUT1(),
+                .SHIFTOUT2(),
+                .BITSLIP(i_controller_bitslip[gen_index]),
+                // 1-bit input: The BITSLIP pin performs a Bitslip operation synchronous to
+                // CLKDIV when asserted (active High). Subsequently, the data seen on the Q1
+                // to Q8 output ports will shift, as in a barrel-shifter operation, one
+                // position every time Bitslip is invoked (DDR operation is different from
+                // SDR).
+                // CE1, CE2: 1-bit (each) input: Data register clock enable inputs
+                .CE1(1'b1),
+                .CE2(1'b1),
+                .CLKDIVP(), // 1-bit input: TBD
+                // Clocks: 1-bit (each) input: ISERDESE2 clock input ports
+                .CLK(i_ddr3_clk), // 1-bit input: High-speed clock
+                .CLKB(!i_ddr3_clk), // 1-bit input: High-speed secondary clock
+                .CLKDIV(i_controller_clk), // 1-bit input: Divided clock
+                .OCLK(), // 1-bit input: High speed output clock used when INTERFACE_TYPE="MEMORY"
+                // Dynamic Clock Inversions: 1-bit (each) input: Dynamic clock inversion pins to switch clock polarity
+                .DYNCLKDIVSEL(), // 1-bit input: Dynamic CLKDIV inversion
+                .DYNCLKSEL(), // 1-bit input: Dynamic CLK/CLKB inversion
+                // Input Data: 1-bit (each) input: ISERDESE2 data input ports
+                .D(), // 1-bit input: Data input
+                .DDLY(idelay_dqs[gen_index]), // 1-bit input: Serial data from IDELAYE2
+                .OFB(), // 1-bit input: Data feedback from OSERDESE2
+                .OCLKB(), // 1-bit input: High speed negative edge output clock
+                .RST(sync_rst), // 1-bit input: Active high asynchronous reset
+                // SHIFTIN1-SHIFTIN2: 1-bit (each) input: Data width expansion input ports
+                .SHIFTIN1(),
+                .SHIFTIN2()
+            );
+            // End of ISERDESE2_inst instantiation
+`endif
+            
+            // generate IOSERDES loopback or not for bitslip training
+            if(NO_IOSERDES_LOOPBACK) begin                    
+                // logic that models OSERDES loopback to ISERDES     
+                // accdg to IOSELECT (UG471) for 7-series:    
+                // " In DDR mode, every Bitslip operation causes the output pattern to alternate between
+                //   a shift right by one and shift left by three"
+                always @(posedge i_controller_clk) begin
+                    if(!i_rst_n || i_controller_reset) begin
+                        o_controller_iserdes_bitslip_reference_reg[(serdes_ratio*2*gen_index + 7) : (serdes_ratio*2*gen_index + 0)] <= 8'b0001_1110;
+                        shift_bitslip_index[gen_index] <= 0;
+                    end
+                    else if(i_controller_bitslip[gen_index]) begin
+                    // if shift_bitslip_index high, shift right by 3, else shift left by 1 (this is reverse of the IOSelect document for ISERDES since vector o_controller_iserdes_bitslip_reference is reversed)
+                        o_controller_iserdes_bitslip_reference_reg[(serdes_ratio*2*gen_index + 7) : (serdes_ratio*2*gen_index + 0)] <= 
+                            shift_bitslip_index[gen_index]? {o_controller_iserdes_bitslip_reference_reg[(serdes_ratio*2*gen_index + 2) : (serdes_ratio*2*gen_index + 0)], o_controller_iserdes_bitslip_reference_reg[(serdes_ratio*2*gen_index + 7) : (serdes_ratio*2*gen_index + 3)]}
+                            : {o_controller_iserdes_bitslip_reference_reg[(serdes_ratio*2*gen_index + 6) : (serdes_ratio*2*gen_index + 0)], o_controller_iserdes_bitslip_reference_reg[(serdes_ratio*2*gen_index + 7)]};
+                        shift_bitslip_index[gen_index] <= !shift_bitslip_index[gen_index];         
+                    end
+                end
+                assign o_controller_iserdes_bitslip_reference = o_controller_iserdes_bitslip_reference_reg;
+            end
+            else begin // OSERDES will loopback to ISERDES for bitslip training    
+                //ISERDES train
+                // End of IOBUF_inst instantiation                 
+                // ISERDESE2: Input SERial/DESerializer with bitslip
+                //7 Series
+                // Xilinx HDL Libraries Guide, version 13.4
+                `ifndef SIM_MODEL
+                    ISERDESE2 #(
+                `else 
+                    ISERDESE2_model #(
+                `endif
+                    .DATA_RATE("DDR"), // DDR, SDR
+                    .DATA_WIDTH(serdes_ratio*2), // Parallel data width (2-8,10,14)
+                    // INIT_Q1 - INIT_Q4: Initial value on the Q outputs (0/1)
+                    .INIT_Q1(1'b0),
+                    .INIT_Q2(1'b0),
+                    .INIT_Q3(1'b0),
+                    .INIT_Q4(1'b0),
+                    .INTERFACE_TYPE("NETWORKING"), // MEMORY, MEMORY_DDR3, MEMORY_QDR, NETWORKING, OVERSAMPLE
+                    .IOBDELAY("NONE"), // NONE, BOTH, IBUF, IFD
+                    .NUM_CE(1),// Number of clock enables (1,2)
+                    .OFB_USED("TRUE"), // Select OFB path (FALSE, TRUE)
+                    // SRVAL_Q1 - SRVAL_Q4: Q output values when SR is used (0/1)
+                    .SRVAL_Q1(1'b0),
+                    .SRVAL_Q2(1'b0),
+                    .SRVAL_Q3(1'b0),
+                    .SRVAL_Q4(1'b0)
+                )
+                ISERDESE2_train (
+                    .O(),
+                    // 1-bit output: Combinatorial output
+                    // Q1 - Q8: 1-bit (each) output: Registered data outputs
+                    .Q1(o_controller_iserdes_bitslip_reference[gen_index*serdes_ratio*2 + 7]),
+                    .Q2(o_controller_iserdes_bitslip_reference[gen_index*serdes_ratio*2 + 6]),
+                    .Q3(o_controller_iserdes_bitslip_reference[gen_index*serdes_ratio*2 + 5]),
+                    .Q4(o_controller_iserdes_bitslip_reference[gen_index*serdes_ratio*2 + 4]),   
+                    .Q5(o_controller_iserdes_bitslip_reference[gen_index*serdes_ratio*2 + 3]),
+                    .Q6(o_controller_iserdes_bitslip_reference[gen_index*serdes_ratio*2 + 2]),
+                    .Q7(o_controller_iserdes_bitslip_reference[gen_index*serdes_ratio*2 + 1]),
+                    .Q8(o_controller_iserdes_bitslip_reference[gen_index*serdes_ratio*2 + 0]),
+                    // SHIFTOUT1-SHIFTOUT2: 1-bit (each) output: Data width expansion output ports
+                    .SHIFTOUT1(),
+                    .SHIFTOUT2(),
+                    .BITSLIP(i_controller_bitslip[gen_index]),
+                    // 1-bit input: The BITSLIP pin performs a Bitslip operation synchronous to
+                    // CLKDIV when asserted (active High). Subsequently, the data seen on the Q1
+                    // to Q8 output ports will shift, as in a barrel-shifter operation, one
+                    // position every time Bitslip is invoked (DDR operation is different from
+                    // SDR).
+                    // CE1, CE2: 1-bit (each) input: Data register clock enable inputs
+                    .CE1(1'b1),
+                    .CE2(1'b1),
+                    .CLKDIVP(), // 1-bit input: TBD
+                    // Clocks: 1-bit (each) input: ISERDESE2 clock input ports
+                    .CLK(i_ddr3_clk), // 1-bit input: High-speed clock
+                    .CLKB(!i_ddr3_clk), // 1-bit input: High-speed secondary clock
+                    .CLKDIV(i_controller_clk), // 1-bit input: Divided clock
+                    .OCLK(), // 1-bit input: High speed output clock used when INTERFACE_TYPE="MEMORY"
+                    // Dynamic Clock Inversions: 1-bit (each) input: Dynamic clock inversion pins to switch clock polarity
+                    .DYNCLKDIVSEL(), // 1-bit input: Dynamic CLKDIV inversion
+                    .DYNCLKSEL(), // 1-bit input: Dynamic CLK/CLKB inversion
+                    // Input Data: 1-bit (each) input: ISERDESE2 data input ports
+                    .D(), // 1-bit input: Data input
+                    .DDLY(), // 1-bit input: Serial data from IDELAYE2
+                    .OFB(oserdes_bitslip_reference[gen_index]), // 1-bit input: Data feedback from OSERDESE2
+                    .OCLKB(), // 1-bit input: High speed negative edge output clock
+                    .RST(sync_rst), // 1-bit input: Active high asynchronous reset
+                    // SHIFTIN1-SHIFTIN2: 1-bit (each) input: Data width expansion input ports
+                    .SHIFTIN1(),
+                    .SHIFTIN2()
+                );
+                // End of ISERDESE2_inst instantiation
+                
+                // OSERDESE2: Output SERial/DESerializer with bitslip
+                //7 Series
+                // Xilinx HDL Libraries Guide, version 13.4
+                `ifndef SIM_MODEL
+                    OSERDESE2 #(
+                `else 
+                    OSERDESE2_model #(
+                `endif
+                    .DATA_RATE_OQ("DDR"), // DDR, SDR
+                    .DATA_RATE_TQ("BUF"), // DDR, SDR
+                    .DATA_WIDTH(8), // Parallel data width (2-8,10,14)
+                    .INIT_OQ(1'b1), // Initial value of OQ output (1'b0,1'b1)
+                    .TRISTATE_WIDTH(1)
+                )
+                OSERDESE2_train(
+                    .OFB(oserdes_bitslip_reference[gen_index]), // 1-bit output: Feedback path for data
+                    .OQ(), // 1-bit output: Data path output
+                    .CLK(i_ddr3_clk), // 1-bit input: High speed clock
+                    .CLKDIV(i_controller_clk), // 1-bit input: Divided clock
+                    // D1 - D8: 1-bit (each) input: Parallel data inputs (1-bit each)
+                    .D1(1'b0),
+                    .D2(1'b0),
+                    .D3(1'b0),
+                    .D4(1'b0),
+                    .D5(1'b1),
+                    .D6(1'b1),
+                    .D7(1'b1),
+                    .D8(1'b1),
+                    .OCE(1'b1), // 1-bit input: Output data clock enable
+                    .RST(sync_rst), // 1-bit input: Reset
+                     // unused signals but were added here to make vivado happy
+                    .SHIFTOUT1(), // SHIFTOUT1 / SHIFTOUT2: 1-bit (each) output: Data output expansion (1-bit each)
+                    .SHIFTOUT2(),
+                    .TBYTEOUT(), // 1-bit output: Byte group tristate
+                    .TFB(), // 1-bit output: 3-state control
+                    .TQ(), // 1-bit output: 3-state control
+                    // SHIFTIN1 / SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each)
+                    .SHIFTIN1(0),
+                    .SHIFTIN2(0),
+                    // T1 - T4: 1-bit (each) input: Parallel 3-state inputs
+                    .T1(0),
+                    .T2(0),
+                    .T3(0),
+                    .T4(0),
+                    .TBYTEIN(0),
+                    // 1-bit input: Byte group tristate
+                    .TCE(0)
+                    // 1-bit input: 3-state clock enable
+                );
+                // End of OSERDESE2_inst instantiation  
+            end
+            
+        end
+     endgenerate 
+     
+
+    // IDELAYCTRL: IDELAYE2/ODELAYE2 Tap Delay Value Control
+    // 7 Series
+    // Xilinx HDL Libraries Guide, version 13.4
+    (* IODELAY_GROUP="DDR3-GROUP" *)
+    `ifndef SIM_MODEL
+        IDELAYCTRL IDELAYCTRL_inst (
+    `else 
+        IDELAYCTRL_model IDELAYCTRL_inst (
+    `endif
+        .RDY(idelayctrl_rdy), // 1-bit output: Ready output
+        .REFCLK(i_ref_clk), // 1-bit input: Reference clock input.The frequency of REFCLK must be 200 MHz to guarantee the tap-delay value specified in the applicable data sheet.
+        .RST(sync_rst) // 1-bit input: Active high reset input, To ,Minimum Reset pulse width is 52ns
+    );
+    // End of IDELAYCTRL_inst instantiation
+
+
+    // DCIRESET: Digitially Controlled Impedence Reset Component
+    //7 Series
+    // Xilinx HDL Libraries Guide, version 13.4
+    // DCIRESET DCIRESET_inst (
+    //     .LOCKED(dci_locked), // 1-bit output: LOCK status output (When low, DCI I/O impedance is being calibrated and DCI I/Os are unavailable)
+    //     .RST(sync_rst) // 1-bit input: Active-high asynchronous reset input
+    // );
+    assign dci_locked = 1;
+    // End of DCIRESET_inst instantiation
+         
+endmodule

AngeloJacobo_UberDDR3/example_demo/alinx_ax7325b/ddr3_top.v

@@ -0,0 +1,475 @@
+////////////////////////////////////////////////////////////////////////////////
+//
+// Filename: ddr3_top.v
+// Project: UberDDR3 - An Open Source DDR3 Controller
+//
+// Purpose: Top module which instantiates the ddr3_controller and ddr3_phy modules
+// Use this as top module for instantiating UberDDR3 with Wishbone Interface.
+//
+// Engineer: Angelo C. Jacobo
+//
+////////////////////////////////////////////////////////////////////////////////
+//
+// Copyright (C) 2023-2025  Angelo Jacobo
+// 
+//     This program is free software: you can redistribute it and/or modify
+//     it under the terms of the GNU General Public License as published by
+//     the Free Software Foundation, either version 3 of the License, or
+//     (at your option) any later version.
+// 
+//     This program is distributed in the hope that it will be useful,
+//     but WITHOUT ANY WARRANTY; without even the implied warranty of
+//     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//     GNU General Public License for more details.
+// 
+//     You should have received a copy of the GNU General Public License
+//     along with this program.  If not, see <https://www.gnu.org/licenses/>.
+//
+////////////////////////////////////////////////////////////////////////////////
+
+`default_nettype none
+`timescale 1ps / 1ps
+
+module ddr3_top #(
+    parameter      CONTROLLER_CLK_PERIOD = 12_000, //ps, clock period of the controller interface
+                   DDR3_CLK_PERIOD = 3_000, //ps, clock period of the DDR3 RAM device (must be 1/4 of the CONTROLLER_CLK_PERIOD) 
+                   ROW_BITS = 14,   //width of row address
+                   COL_BITS = 10, //width of column address
+                   BA_BITS = 3, //width of bank address
+                   BYTE_LANES = 2, //number of byte lanes of DDR3 RAM
+                   AUX_WIDTH = 4, //width of aux line (must be >= 4) 
+                   WB2_ADDR_BITS = 7, //width of 2nd wishbone address bus 
+                   WB2_DATA_BITS = 32, //width of 2nd wishbone data bus 
+                   DUAL_RANK_DIMM = 0, // enable dual rank DIMM (1 =  enable, 0 = disable)
+    // DDR3 timing parameter values
+    parameter      SPEED_BIN = 3, // 0 = Use top-level parameters , 1 = DDR3-1066 (7-7-7) , 2 = DR3-1333 (9-9-9) , 3 = DDR3-1600 (11-11-11)
+                   SDRAM_CAPACITY = 5, // 0 = 256Mb, 1 = 512Mb, 2 = 1Gb, 3 = 2Gb, 4 = 4Gb, 5 = 8Gb, 6 = 16Gb
+                   TRCD = 13_750, // ps Active to Read/Write command time (only used if SPEED_BIN = 0)
+                   TRP = 13_750, // ps Precharge command period (only used if SPEED_BIN = 0)
+                   TRAS = 35_000, // ps ACT to PRE command period (only used if SPEED_BIN = 0)
+    parameter[0:0] MICRON_SIM = 0, //enable faster simulation for micron ddr3 model (shorten POWER_ON_RESET_HIGH and INITIAL_CKE_LOW)
+                   ODELAY_SUPPORTED = 0, //set to 1 when ODELAYE2 is supported
+                   SECOND_WISHBONE = 0, //set to 1 if 2nd wishbone for debugging is needed 
+                   DLL_OFF = 0, // 1 = DLL off for low frequency ddr3 clock (< 125MHz)
+                   WB_ERROR = 0, // set to 1 to support Wishbone error (asserts at ECC double bit error)
+    parameter[1:0] BIST_MODE = 1, // 0 = No BIST, 1 = run through all address space ONCE , 2 = run through all address space for every test (burst w/r, random w/r, alternating r/w)
+    parameter[0:0] BIST_TEST_DATAMASK = 1, // 1 = include per-byte DM writes in BIST, 0 = all-byte writes only
+    parameter[1:0] ECC_ENABLE = 0, // set to 1 or 2 to add ECC (1 = Side-band ECC per burst, 2 = Side-band ECC per 8 bursts , 3 = Inline ECC ) 
+    parameter[1:0] DIC = 2'b00, //Output Driver Impedance Control (2'b00 = RZQ/6, 2'b01 = RZQ/7, RZQ = 240ohms) (only change when you know what you are doing)
+    parameter[2:0] RTT_NOM = 3'b011, //RTT Nominal (3'b000 = disabled, 3'b001 = RZQ/4, 3'b010 = RZQ/2 , 3'b011 = RZQ/6, RZQ = 240ohms)  (only change when you know what you are doing)
+    parameter[1:0] SELF_REFRESH = 2'b00, // 0 = use i_user_self_refresh input, 1 = Self-refresh mode is enabled after 64 controller clock cycles of no requests, 2 = 128 cycles, 3 = 256 cycles
+    parameter // The next parameters act more like a localparam (since user does not have to set this manually) but was added here to simplify port declaration
+                DQ_BITS = 8,  //device width (fixed to 8, if DDR3 is x16 then BYTE_LANES will be 2 while )
+                serdes_ratio = 4, // this controller is fixed as a 4:1 memory controller (CONTROLLER_CLK_PERIOD/DDR3_CLK_PERIOD = 4)
+                wb_addr_bits = ROW_BITS + COL_BITS + BA_BITS - $clog2(serdes_ratio*2) + DUAL_RANK_DIMM,
+                wb_data_bits = DQ_BITS*BYTE_LANES*serdes_ratio*2,
+                wb_sel_bits = wb_data_bits / 8,
+                wb2_sel_bits = WB2_DATA_BITS / 8,
+                //4 is the width of a single ddr3 command {cs_n, ras_n, cas_n, we_n} plus 3 (ck_en, odt, reset_n) plus bank bits plus row bits
+                cmd_len = 4 + 3 + BA_BITS + ROW_BITS + 2*DUAL_RANK_DIMM
+    ) 
+    (
+        input wire i_controller_clk, i_ddr3_clk, i_ref_clk, //i_controller_clk = CONTROLLER_CLK_PERIOD, i_ddr3_clk = DDR3_CLK_PERIOD, i_ref_clk = 200MHz
+        input wire i_ddr3_clk_90, //required only when ODELAY_SUPPORTED is zero
+        input wire i_rst_n,
+        //
+        // Wishbone inputs
+        input wire i_wb_cyc, //bus cycle active (1 = normal operation, 0 = all ongoing transaction are to be cancelled)
+        input wire i_wb_stb, //request a transfer
+        input wire i_wb_we, //write-enable (1 = write, 0 = read)
+        input wire[wb_addr_bits - 1:0] i_wb_addr, //burst-addressable {row,bank,col} 
+        input wire[wb_data_bits - 1:0] i_wb_data, //write data, for a 4:1 controller data width is 8 times the number of pins on the device
+        input wire[wb_sel_bits - 1:0] i_wb_sel, //byte strobe for write (1 = write the byte)
+        input wire[AUX_WIDTH - 1:0]  i_aux, //for AXI-interface compatibility (given upon strobe)
+        // Wishbone outputs
+        output wire o_wb_stall, //1 = busy, cannot accept requests
+        output wire o_wb_ack, //1 = read/write request has completed
+        output wire o_wb_err, //1 = Error due to ECC double bit error (fixed to 0 if WB_ERROR = 0)
+        output wire[wb_data_bits - 1:0] o_wb_data, //read data, for a 4:1 controller data width is 8 times the number of pins on the device
+        output wire[AUX_WIDTH - 1:0]  o_aux, //for AXI-interface compatibility (given upon strobe)
+        //
+        // Wishbone 2 (PHY) inputs
+        input wire i_wb2_cyc, //bus cycle active (1 = normal operation, 0 = all ongoing transaction are to be cancelled)
+        input wire i_wb2_stb, //request a transfer
+        input wire i_wb2_we, //write-enable (1 = write, 0 = read)
+        input wire[WB2_ADDR_BITS - 1:0] i_wb2_addr, // memory-mapped register to be accessed
+        input wire[WB2_DATA_BITS - 1:0] i_wb2_data, //write data
+        input wire[wb2_sel_bits - 1:0] i_wb2_sel, //byte strobe for write (1 = write the byte)
+        // Wishbone 2 (Controller) outputs
+        output wire o_wb2_stall, //1 = busy, cannot accept requests
+        output wire o_wb2_ack, //1 = read/write request has completed
+        output wire[WB2_DATA_BITS - 1:0] o_wb2_data, //read data
+        //
+        // DDR3 I/O Interface
+        output wire[DUAL_RANK_DIMM:0] o_ddr3_clk_p, o_ddr3_clk_n,
+        output wire o_ddr3_reset_n,
+        output wire[DUAL_RANK_DIMM:0] o_ddr3_cke, // CKE
+        output wire[DUAL_RANK_DIMM:0] o_ddr3_cs_n, // chip select signal
+        output wire o_ddr3_ras_n, // RAS#
+        output wire o_ddr3_cas_n, // CAS#
+        output wire o_ddr3_we_n, // WE#
+        output wire[ROW_BITS-1:0] o_ddr3_addr,
+        output wire[BA_BITS-1:0] o_ddr3_ba_addr,
+        inout wire[(DQ_BITS*BYTE_LANES)-1:0] io_ddr3_dq,
+        inout wire[BYTE_LANES-1:0] io_ddr3_dqs, io_ddr3_dqs_n,
+        output wire[BYTE_LANES-1:0] o_ddr3_dm,
+        output wire[DUAL_RANK_DIMM:0] o_ddr3_odt, // on-die termination
+        //
+        // Done Calibration pin
+        output wire o_calib_complete,
+        // Debug outputs
+        output wire[31:0] o_debug1,
+//        output wire[31:0] o_debug2,
+//        output wire[31:0] o_debug3,
+//        output wire[(DQ_BITS*BYTE_LANES)/8-1:0] o_ddr3_debug_read_dqs_p,
+//        output wire[(DQ_BITS*BYTE_LANES)/8-1:0] o_ddr3_debug_read_dqs_n
+        // 
+        // User enabled self-refresh
+        input wire i_user_self_refresh,
+        output wire uart_tx
+    );
+    
+// Instantiation Template (DEFAULT VALUE IS FOR ARTY S7)
+/*
+// DDR3 Controller 
+ddr3_top #(
+    .CONTROLLER_CLK_PERIOD(12_000), //ps, clock period of the controller interface
+    .DDR3_CLK_PERIOD(3_000), //ps, clock period of the DDR3 RAM device (must be 1/4 of the CONTROLLER_CLK_PERIOD) 
+    .ROW_BITS(14), //width of row address
+    .COL_BITS(10), //width of column address
+    .BA_BITS(3), //width of bank address
+    .BYTE_LANES(2), //number of byte lanes of DDR3 RAM
+    .AUX_WIDTH(4), //width of aux line (must be >= 4) 
+    .MICRON_SIM(0), //enable faster simulation for micron ddr3 model (shorten POWER_ON_RESET_HIGH and INITIAL_CKE_LOW)
+    .ODELAY_SUPPORTED(0), //set to 1 if ODELAYE2 is supported
+    .SECOND_WISHBONE(0), //set to 1 if 2nd wishbone for debugging is needed 
+    .ECC_ENABLE(0), // set to 1 or 2 to add ECC (1 = Side-band ECC per burst, 2 = Side-band ECC per 8 bursts , 3 = Inline ECC ) 
+    .WB_ERROR(0), // set to 1 to support Wishbone error (asserts at ECC double bit error)
+    ) ddr3_top
+    (
+        //clock and reset
+        .i_controller_clk(i_controller_clk),
+        .i_ddr3_clk(i_ddr3_clk), //i_controller_clk has period of CONTROLLER_CLK_PERIOD, i_ddr3_clk has period of DDR3_CLK_PERIOD 
+        .i_ref_clk(i_ref_clk), // usually set to 200 MHz 
+        .i_ddr3_clk_90(i_ddr3_clk_90), //90 degree phase shifted version i_ddr3_clk (required only when ODELAY_SUPPORTED is zero)
+        .i_rst_n(!i_rst && clk_locked), 
+        //
+        // Wishbone inputs
+        .i_wb_cyc(1), //bus cycle active (1 = normal operation, 0 = all ongoing transaction are to be cancelled)
+        .i_wb_stb(i_wb_stb), //request a transfer
+        .i_wb_we(i_wb_we), //write-enable (1 = write, 0 = read)
+        .i_wb_addr(i_wb_addr), //burst-addressable {row,bank,col} 
+        .i_wb_data(i_wb_data), //write data, for a 4:1 controller data width is 8 times the number of pins on the device
+        .i_wb_sel(16'hffff), //byte strobe for write (1 = write the byte)
+        .i_aux(i_wb_we), //for AXI-interface compatibility (given upon strobe)
+        // Wishbone outputs
+        .o_wb_stall(o_wb_stall), //1 = busy, cannot accept requests
+        .o_wb_ack(o_wb_ack), //1 = read/write request has completed
+        .o_wb_err(o_wb_err), //1 = Error due to ECC double bit error (fixed to 0 if WB_ERROR = 0)
+        .o_wb_data(o_wb_data), //read data, for a 4:1 controller data width is 8 times the number of pins on the device
+        .o_aux(o_aux),
+        //
+        // Wishbone 2 (PHY) inputs
+        .i_wb2_cyc(0), //bus cycle active (1 = normal operation, 0 = all ongoing transaction are to be cancelled)
+        .i_wb2_stb(0), //request a transfer
+        .i_wb2_we(0), //write-enable (1 = write, 0 = read)
+        .i_wb2_addr(0), //burst-addressable {row,bank,col} 
+        .i_wb2_data(0), //write data, for a 4:1 controller data width is 8 times the number of pins on the device
+        .i_wb2_sel(0), //byte strobe for write (1 = write the byte)
+        // Wishbone 2 (Controller) outputs
+        .o_wb2_stall(), //1 = busy, cannot accept requests
+        .o_wb2_ack(), //1 = read/write request has completed
+        .o_wb2_data(), //read data, for a 4:1 controller data width is 8 times the number of pins on the device
+        //
+        // DDR3 I/O Interface
+        .o_ddr3_clk_p(ddr3_clk_p), 
+        .o_ddr3_clk_n(ddr3_clk_n),
+        .o_ddr3_reset_n(ddr3_reset_n),
+        .o_ddr3_cke(ddr3_cke), 
+        .o_ddr3_cs_n(ddr3_cs_n), // width = number of DDR3 ranks
+        .o_ddr3_ras_n(ddr3_ras_n), 
+        .o_ddr3_cas_n(ddr3_cas_n), 
+        .o_ddr3_we_n(ddr3_we_n), 
+        .o_ddr3_addr(ddr3_addr), // width = ROW_BITS
+        .o_ddr3_ba_addr(ddr3_ba), // width = BA_BITS
+        .io_ddr3_dq(ddr3_dq), // width = BYTE_LANES*8
+        .io_ddr3_dqs(ddr3_dqs_p), // width = BYTE_LANES
+        .io_ddr3_dqs_n(ddr3_dqs_n), // width = BYTE_LANES
+        .o_ddr3_dm(ddr3_dm), // width = BYTE_LANES
+        .o_ddr3_odt(ddr3_odt),
+        // Debug outputs
+        .o_debug1(),
+        ////////////////////////////////////
+    );
+*/
+    
+    // Wire connections between controller and phy
+    wire[cmd_len*serdes_ratio-1:0] cmd;
+    wire dqs_tri_control, dq_tri_control;
+    wire toggle_dqs;
+    wire[wb_data_bits-1:0] data;
+    wire[wb_sel_bits-1:0] dm;
+    wire[BYTE_LANES-1:0] bitslip;
+    wire[DQ_BITS*BYTE_LANES*8-1:0] iserdes_data;
+    wire[BYTE_LANES*8-1:0] iserdes_dqs;
+    wire[BYTE_LANES*8-1:0] iserdes_bitslip_reference;
+    wire idelayctrl_rdy;
+    wire[4:0] odelay_data_cntvaluein, odelay_dqs_cntvaluein;
+    wire[4:0] idelay_data_cntvaluein, idelay_dqs_cntvaluein;
+    wire[BYTE_LANES-1:0] odelay_data_ld, odelay_dqs_ld;
+    wire[BYTE_LANES-1:0] idelay_data_ld, idelay_dqs_ld;
+    wire write_leveling_calib;
+    wire reset;
+    
+    // logic for self-refresh
+    reg[8:0] refresh_counter = 0;
+    reg user_self_refresh;
+    // refresh counter 
+    always @(posedge i_controller_clk) begin
+        if(i_wb_stb && i_wb_cyc) begin // if there is Wishbone request, then reset counter
+            refresh_counter <= 0;
+        end
+        else if(!o_wb_stall || user_self_refresh) begin // if no request (but not stalled) OR already on self-refresh, then increment counter
+            refresh_counter <= refresh_counter + 1;
+        end
+    end
+    // choose self-refresh options
+    always @* begin
+        case(SELF_REFRESH) 
+            2'b00: user_self_refresh = i_user_self_refresh; // use input i_user_self_refresh (high = enter self-refresh, low = exit self-refresh)
+            2'b01: user_self_refresh = refresh_counter[6];  // Self-refresh mode is enabled after 64 controller clock cycles of no requests, then exit Self-refresh after another 64 controller clk cycles
+            2'b10: user_self_refresh = refresh_counter[7];  // Self-refresh mode is enabled after 128 controller clock cycles of no requests, then exit Self-refresh after another 128 controller clk cycles
+            2'b11: user_self_refresh = refresh_counter[8];  // Self-refresh mode is enabled after 256 controller clock cycles of no requests, then exit Self-refresh after another 256 controller clk cycles
+        endcase
+    end
+    
+
+    
+    //module instantiations
+    ddr3_controller #(
+            .CONTROLLER_CLK_PERIOD(CONTROLLER_CLK_PERIOD), //ps, clock period of the controller interface
+            .DDR3_CLK_PERIOD(DDR3_CLK_PERIOD), //ps, clock period of the DDR3 RAM device (must be 1/4 of the CONTROLLER_CLK_PERIOD) 
+            .ROW_BITS(ROW_BITS), //width of row address
+            .COL_BITS(COL_BITS), //width of column address
+            .BA_BITS(BA_BITS), //width of bank address
+            .DQ_BITS(DQ_BITS),  //width of DQ
+            .LANES(BYTE_LANES), // byte lanes
+            .AUX_WIDTH(AUX_WIDTH), //width of aux line (must be >= 4) 
+            .WB2_ADDR_BITS(WB2_ADDR_BITS), //width of 2nd wishbone address bus 
+            .WB2_DATA_BITS(WB2_DATA_BITS),  //width of 2nd wishbone data bus
+            .MICRON_SIM(MICRON_SIM), //simulation for micron ddr3 model (shorten POWER_ON_RESET_HIGH and INITIAL_CKE_LOW)
+            .ODELAY_SUPPORTED(ODELAY_SUPPORTED),  //set to 1 when ODELAYE2 is supported
+            .SECOND_WISHBONE(SECOND_WISHBONE), //set to 1 if 2nd wishbone is needed 
+            .ECC_ENABLE(ECC_ENABLE), // set to 1 or 2 to add ECC (1 = Side-band ECC per burst, 2 = Side-band ECC per 8 bursts , 3 = Inline ECC ) 
+            .DLL_OFF(DLL_OFF), // 1 = DLL off for low frequency ddr3 clock (< 125MHz)
+            .WB_ERROR(WB_ERROR), // set to 1 to support Wishbone error (asserts at ECC double bit error)
+            .BIST_MODE(BIST_MODE), // 0 = No BIST, 1 = run through all address space ONCE , 2 = run through all address space for every test (burst w/r, random w/r, alternating r/w)
+            .BIST_TEST_DATAMASK(BIST_TEST_DATAMASK), // 1 = include per-byte DM writes in BIST, 0 = all-byte writes only
+            .DIC(DIC), //Output Driver Impedance Control (2'b00 = RZQ/6, 2'b01 = RZQ/7, RZQ = 240ohms)
+            .RTT_NOM(RTT_NOM), //RTT Nominal (3'b000 = disabled, 3'b001 = RZQ/4, 3'b010 = RZQ/2 , 3'b011 = RZQ/6, RZQ = 240ohms)
+            .DUAL_RANK_DIMM(DUAL_RANK_DIMM), // enable dual rank DIMM (1 =  enable, 0 = disable)
+            .SPEED_BIN(SPEED_BIN), // 0 = Use top-level parameters , 1 = DDR3-1066 (7-7-7) , 2 = DR3-1333 (9-9-9) , 3 = DDR3-1600 (11-11-11)
+            .SDRAM_CAPACITY(SDRAM_CAPACITY), // 0 = 256Mb, 1 = 512Mb, 2 = 1Gb, 3 = 2Gb, 4 = 4Gb, 5 = 8Gb, 6 = 16Gb
+            .TRCD(TRCD), // ps Active to Read/Write command time (only used if SPEED_BIN = 0)
+            .TRP(TRP), // ps Precharge command period (only used if SPEED_BIN = 0)
+            .TRAS(TRAS) // ps ACT to PRE command period (only used if SPEED_BIN = 0)
+        ) ddr3_controller_inst (
+            .i_controller_clk(i_controller_clk), //i_controller_clk has period of CONTROLLER_CLK_PERIOD 
+            .i_rst_n(i_rst_n), //200MHz input clock
+            // Wishbone inputs
+            .i_wb_cyc(i_wb_cyc), //bus cycle active (1 = normal operation, 0 = all ongoing transaction are to be cancelled)
+            .i_wb_stb(i_wb_stb), //request a transfer
+            .i_wb_we(i_wb_we), //write-enable (1 = write, 0 = read)
+            .i_wb_addr(i_wb_addr), //burst-addressable {row,bank,col} 
+            .i_wb_data(i_wb_data), //write data, for a 4:1 controller data width is 8 times the number of pins on the device
+            .i_wb_sel(i_wb_sel), //byte strobe for write (1 = write the byte)
+            .i_aux(i_aux), //for AXI-interface compatibility (given upon strobe)
+            // Wishbone outputs
+            .o_wb_stall(o_wb_stall), //1 = busy, cannot accept requests
+            .o_wb_ack(o_wb_ack), //1 = read/write request has completed
+            .o_wb_err(o_wb_err), //1 = Error due to ECC double bit error (fixed to 0 if WB_ERROR = 0)
+            .o_wb_data(o_wb_data), //read data, for a 4:1 controller data width is 8 times the number of pins on the device
+            .o_aux(o_aux), //for AXI-interface compatibility (returned upon ack)
+            // Wishbone 2 (PHY) inputs
+            .i_wb2_cyc(i_wb2_cyc), //bus cycle active (1 = normal operation, 0 = all ongoing transaction are to be cancelled)
+            .i_wb2_stb(i_wb2_stb), //request a transfer
+            .i_wb2_we(i_wb2_we), //write-enable (1 = write, 0 = read)
+            .i_wb2_addr(i_wb2_addr), // memory-mapped register to be accessed 
+            .i_wb2_data(i_wb2_data), //write data
+            .i_wb2_sel(i_wb2_sel), //byte strobe for write (1 = write the byte)
+            // Wishbone 2 (Controller) outputs
+            .o_wb2_stall(o_wb2_stall), //1 = busy, cannot accept requests
+            .o_wb2_ack(o_wb2_ack), //1 = read/write request has completed
+            .o_wb2_data(o_wb2_data), //read data
+            //
+            // PHY interface
+            .i_phy_iserdes_data(iserdes_data),
+            .i_phy_iserdes_dqs(iserdes_dqs),
+            .i_phy_iserdes_bitslip_reference(iserdes_bitslip_reference),
+            .i_phy_idelayctrl_rdy(idelayctrl_rdy),
+            .o_phy_cmd(cmd),
+            .o_phy_dqs_tri_control(dqs_tri_control), 
+            .o_phy_dq_tri_control(dq_tri_control),
+            .o_phy_toggle_dqs(toggle_dqs),
+            .o_phy_data(data),
+            .o_phy_dm(dm),
+            .o_phy_odelay_data_cntvaluein(odelay_data_cntvaluein),
+            .o_phy_odelay_dqs_cntvaluein(odelay_dqs_cntvaluein),
+            .o_phy_idelay_data_cntvaluein(idelay_data_cntvaluein), 
+            .o_phy_idelay_dqs_cntvaluein(idelay_dqs_cntvaluein),
+            .o_phy_odelay_data_ld(odelay_data_ld),
+            .o_phy_odelay_dqs_ld(odelay_dqs_ld),
+            .o_phy_idelay_data_ld(idelay_data_ld), 
+            .o_phy_idelay_dqs_ld(idelay_dqs_ld),
+            .o_phy_bitslip(bitslip),
+            .o_phy_write_leveling_calib(write_leveling_calib),
+            .o_phy_reset(reset),
+            // Done Calibration pin
+            .o_calib_complete(o_calib_complete),
+            // Debug outputs
+            .o_debug1(o_debug1),
+//            .o_debug2(o_debug2),
+//            .o_debug3(o_debug3)
+            // User enabled self-refresh
+            .i_user_self_refresh(user_self_refresh),
+            .uart_tx(uart_tx)
+        );
+    `ifndef LATTICE_ECP5_PHY // XILINX PHY
+        ddr3_phy #(
+                .ROW_BITS(ROW_BITS), //width of row address
+                .BA_BITS(BA_BITS), //width of bank address
+                .DQ_BITS(DQ_BITS),  //width of DQ
+                .LANES(BYTE_LANES), //8 lanes of DQ
+                .CONTROLLER_CLK_PERIOD(CONTROLLER_CLK_PERIOD), //ps, period of clock input to this DDR3 controller module
+                .DDR3_CLK_PERIOD(DDR3_CLK_PERIOD), //ps, period of clock input to DDR3 RAM device 
+                .ODELAY_SUPPORTED(ODELAY_SUPPORTED), //set to 1 when ODELAYE2 is supported
+                .DUAL_RANK_DIMM(DUAL_RANK_DIMM) // enable dual rank DIMM (1 =  enable, 0 = disable)
+            ) ddr3_phy_inst (
+                .i_controller_clk(i_controller_clk), 
+                .i_ddr3_clk(i_ddr3_clk),
+                .i_ref_clk(i_ref_clk),
+                .i_ddr3_clk_90(i_ddr3_clk_90), 
+                .i_rst_n(i_rst_n),
+                // Controller Interface
+                .i_controller_reset(reset),
+                .i_controller_cmd(cmd),
+                .i_controller_dqs_tri_control(dqs_tri_control), 
+                .i_controller_dq_tri_control(dq_tri_control),
+                .i_controller_toggle_dqs(toggle_dqs),
+                .i_controller_data(data),
+                .i_controller_dm(dm),
+                .i_controller_odelay_data_cntvaluein(odelay_data_cntvaluein),
+                .i_controller_odelay_dqs_cntvaluein(odelay_dqs_cntvaluein),
+                .i_controller_idelay_data_cntvaluein(idelay_data_cntvaluein),
+                .i_controller_idelay_dqs_cntvaluein(idelay_dqs_cntvaluein),
+                .i_controller_odelay_data_ld(odelay_data_ld), 
+                .i_controller_odelay_dqs_ld(odelay_dqs_ld),
+                .i_controller_idelay_data_ld(idelay_data_ld), 
+                .i_controller_idelay_dqs_ld(idelay_dqs_ld),
+                .i_controller_bitslip(bitslip),
+                .i_controller_write_leveling_calib(write_leveling_calib),
+                .o_controller_iserdes_data(iserdes_data),
+                .o_controller_iserdes_dqs(iserdes_dqs),
+                .o_controller_iserdes_bitslip_reference(iserdes_bitslip_reference),
+                .o_controller_idelayctrl_rdy(idelayctrl_rdy),
+                // DDR3 I/O Interface
+                .o_ddr3_clk_p(o_ddr3_clk_p),
+                .o_ddr3_clk_n(o_ddr3_clk_n),
+                .o_ddr3_reset_n(o_ddr3_reset_n),
+                .o_ddr3_cke(o_ddr3_cke), // CKE
+                .o_ddr3_cs_n(o_ddr3_cs_n), // chip select signal
+                .o_ddr3_ras_n(o_ddr3_ras_n), // RAS#
+                .o_ddr3_cas_n(o_ddr3_cas_n), // CAS#
+                .o_ddr3_we_n(o_ddr3_we_n), // WE#
+                .o_ddr3_addr(o_ddr3_addr),
+                .o_ddr3_ba_addr(o_ddr3_ba_addr),
+                .io_ddr3_dq(io_ddr3_dq),
+                .io_ddr3_dqs(io_ddr3_dqs),
+                .io_ddr3_dqs_n(io_ddr3_dqs_n),
+                .o_ddr3_dm(o_ddr3_dm),
+                .o_ddr3_odt(o_ddr3_odt), // on-die termination
+                .o_ddr3_debug_read_dqs_p(/*o_ddr3_debug_read_dqs_p*/),
+                .o_ddr3_debug_read_dqs_n(/*o_ddr3_debug_read_dqs_n*/)
+            );
+    `else // LATTICE ECP5 PHY
+        ddr3_phy_ecp5 #(
+                .ROW_BITS(ROW_BITS), //width of row address
+                .BA_BITS(BA_BITS), //width of bank address
+                .DQ_BITS(DQ_BITS),  //width of DQ
+                .LANES(BYTE_LANES), //8 lanes of DQ
+                .CONTROLLER_CLK_PERIOD(CONTROLLER_CLK_PERIOD) //ps, period of clock input to this DDR3 controller module
+            ) ddr3_phy_inst (
+                .i_controller_clk(i_controller_clk), 
+                .i_ddr3_clk(i_ddr3_clk),
+                .i_ref_clk(i_ref_clk),
+                .i_ddr3_clk_90(i_ddr3_clk_90), 
+                .i_rst_n(i_rst_n),
+                // Controller Interface
+                .i_controller_reset(reset),
+                .i_controller_cmd(cmd),
+                .i_controller_dqs_tri_control(dqs_tri_control), 
+                .i_controller_dq_tri_control(dq_tri_control),
+                .i_controller_toggle_dqs(toggle_dqs),
+                .i_controller_data(data),
+                .i_controller_dm(dm),
+                .i_controller_odelay_data_cntvaluein(odelay_data_cntvaluein),
+                .i_controller_odelay_dqs_cntvaluein(odelay_dqs_cntvaluein),
+                .i_controller_idelay_data_cntvaluein(idelay_data_cntvaluein),
+                .i_controller_idelay_dqs_cntvaluein(idelay_dqs_cntvaluein),
+                .i_controller_odelay_data_ld(odelay_data_ld), 
+                .i_controller_odelay_dqs_ld(odelay_dqs_ld),
+                .i_controller_idelay_data_ld(idelay_data_ld), 
+                .i_controller_idelay_dqs_ld(idelay_dqs_ld),
+                .i_controller_bitslip(bitslip),
+                .i_controller_write_leveling_calib(write_leveling_calib),
+                .o_controller_iserdes_data(iserdes_data),
+                .o_controller_iserdes_dqs(iserdes_dqs),
+                .o_controller_iserdes_bitslip_reference(iserdes_bitslip_reference),
+                .o_controller_idelayctrl_rdy(idelayctrl_rdy),
+                // DDR3 I/O Interface
+                .o_ddr3_clk_p(o_ddr3_clk_p),
+                .o_ddr3_clk_n(o_ddr3_clk_n),
+                .o_ddr3_reset_n(o_ddr3_reset_n),
+                .o_ddr3_cke(o_ddr3_cke), // CKE
+                .o_ddr3_cs_n(o_ddr3_cs_n), // chip select signal
+                .o_ddr3_ras_n(o_ddr3_ras_n), // RAS#
+                .o_ddr3_cas_n(o_ddr3_cas_n), // CAS#
+                .o_ddr3_we_n(o_ddr3_we_n), // WE#
+                .o_ddr3_addr(o_ddr3_addr),
+                .o_ddr3_ba_addr(o_ddr3_ba_addr),
+                .io_ddr3_dq(io_ddr3_dq),
+                .io_ddr3_dqs(io_ddr3_dqs),
+                .io_ddr3_dqs_n(io_ddr3_dqs_n),
+                .o_ddr3_dm(o_ddr3_dm),
+                .o_ddr3_odt(o_ddr3_odt), // on-die termination
+                .o_ddr3_debug_read_dqs_p(/*o_ddr3_debug_read_dqs_p*/),
+                .o_ddr3_debug_read_dqs_n(/*o_ddr3_debug_read_dqs_n*/)
+            );
+    `endif 
+
+        // // display value of parameters for easy debugging
+        // initial begin
+        //     $display("\nDDR3 TOP PARAMETERS:\n-----------------------------");
+        //     $display("CONTROLLER_CLK_PERIOD = %0d", CONTROLLER_CLK_PERIOD);
+        //     $display("DDR3_CLK_PERIOD = %0d", DDR3_CLK_PERIOD);
+        //     $display("ROW_BITS = %0d", ROW_BITS);
+        //     $display("COL_BITS = %0d", COL_BITS);
+        //     $display("BA_BITS = %0d", BA_BITS);
+        //     $display("BYTE_LANES = %0d", BYTE_LANES);
+        //     $display("AUX_WIDTH = %0d", AUX_WIDTH);
+        //     $display("WB2_ADDR_BITS = %0d", WB2_ADDR_BITS);
+        //     $display("WB2_DATA_BITS = %0d", WB2_DATA_BITS);
+        //     $display("MICRON_SIM = %0d", MICRON_SIM);
+        //     $display("ODELAY_SUPPORTED = %0d", ODELAY_SUPPORTED);
+        //     $display("SECOND_WISHBONE = %0d", SECOND_WISHBONE);
+        //     $display("WB_ERROR = %0d", WB_ERROR);
+        //     $display("BIST_MODE = %0d", BIST_MODE);
+        //     $display("ECC_ENABLE = %0d", ECC_ENABLE);
+        //     $display("DIC = %0d", DIC);
+        //     $display("RTT_NOM = %0d", RTT_NOM);
+        //     $display("SELF_REFRESH = %0d", SELF_REFRESH);
+        //     $display("DUAL_RANK_DIMM = %0d", DUAL_RANK_DIMM);
+        //     $display("End of DDR3 TOP PARAMETERS\n-----------------------------");
+        // end
+
+endmodule

AngeloJacobo_UberDDR3/example_demo/alinx_ax7325b/uart_rx.v

@@ -0,0 +1,207 @@
+
+// 
+// Module: uart_rx 
+// 
+// Notes:
+// - UART reciever module.
+//
+
+module uart_rx(
+input  wire       clk          , // Top level system clock input.
+input  wire       resetn       , // Asynchronous active low reset.
+input  wire       uart_rxd     , // UART Recieve pin.
+input  wire       uart_rx_en   , // Recieve enable
+output wire       uart_rx_break, // Did we get a BREAK message?
+output wire       uart_rx_valid, // Valid data recieved and available.
+output reg  [PAYLOAD_BITS-1:0] uart_rx_data   // The recieved data.
+);
+
+// --------------------------------------------------------------------------- 
+// External parameters.
+// 
+
+//
+// Input bit rate of the UART line.
+parameter   BIT_RATE        = 9600; // bits / sec
+localparam  BIT_P           = 1_000_000_000 * 1/BIT_RATE; // nanoseconds
+
+//
+// Clock frequency in hertz.
+parameter   CLK_HZ          =    50_000_000;
+localparam  CLK_P           = 1_000_000_000 * 1/CLK_HZ; // nanoseconds
+
+//
+// Number of data bits recieved per UART packet.
+parameter   PAYLOAD_BITS    = 8;
+
+//
+// Number of stop bits indicating the end of a packet.
+parameter   STOP_BITS       = 1;
+
+// -------------------------------------------------------------------------- 
+// Internal parameters.
+// 
+
+//
+// Number of clock cycles per uart bit.
+localparam       CYCLES_PER_BIT     = BIT_P / CLK_P;
+
+//
+// Size of the registers which store sample counts and bit durations.
+localparam       COUNT_REG_LEN      = 1+$clog2(CYCLES_PER_BIT);
+
+// -------------------------------------------------------------------------- 
+// Internal registers.
+// 
+
+//
+// Internally latched value of the uart_rxd line. Helps break long timing
+// paths from input pins into the logic.
+reg rxd_reg;
+reg rxd_reg_0;
+
+//
+// Storage for the recieved serial data.
+reg [PAYLOAD_BITS-1:0] recieved_data;
+
+//
+// Counter for the number of cycles over a packet bit.
+reg [COUNT_REG_LEN-1:0] cycle_counter;
+
+//
+// Counter for the number of recieved bits of the packet.
+reg [3:0] bit_counter;
+
+//
+// Sample of the UART input line whenever we are in the middle of a bit frame.
+reg bit_sample;
+
+//
+// Current and next states of the internal FSM.
+reg [2:0] fsm_state;
+reg [2:0] n_fsm_state;
+
+localparam FSM_IDLE = 0;
+localparam FSM_START= 1;
+localparam FSM_RECV = 2;
+localparam FSM_STOP = 3;
+
+// --------------------------------------------------------------------------- 
+// Output assignment
+// 
+
+assign uart_rx_break = uart_rx_valid && ~|recieved_data;
+assign uart_rx_valid = fsm_state == FSM_STOP && n_fsm_state == FSM_IDLE;
+
+always @(posedge clk) begin
+    if(!resetn) begin
+        uart_rx_data  <= {PAYLOAD_BITS{1'b0}};
+    end else if (fsm_state == FSM_STOP) begin
+        uart_rx_data  <= recieved_data;
+    end
+end
+
+// --------------------------------------------------------------------------- 
+// FSM next state selection.
+// 
+
+wire next_bit     = cycle_counter == CYCLES_PER_BIT ||
+                        fsm_state       == FSM_STOP && 
+                        cycle_counter   == CYCLES_PER_BIT/2;
+wire payload_done = bit_counter   == PAYLOAD_BITS  ;
+
+//
+// Handle picking the next state.
+always @(*) begin : p_n_fsm_state
+    case(fsm_state)
+        FSM_IDLE : n_fsm_state = rxd_reg      ? FSM_IDLE : FSM_START;
+        FSM_START: n_fsm_state = next_bit     ? FSM_RECV : FSM_START;
+        FSM_RECV : n_fsm_state = payload_done ? FSM_STOP : FSM_RECV ;
+        FSM_STOP : n_fsm_state = next_bit     ? FSM_IDLE : FSM_STOP ;
+        default  : n_fsm_state = FSM_IDLE;
+    endcase
+end
+
+// --------------------------------------------------------------------------- 
+// Internal register setting and re-setting.
+// 
+
+//
+// Handle updates to the recieved data register.
+integer i = 0;
+always @(posedge clk) begin : p_recieved_data
+    if(!resetn) begin
+        recieved_data <= {PAYLOAD_BITS{1'b0}};
+    end else if(fsm_state == FSM_IDLE             ) begin
+        recieved_data <= {PAYLOAD_BITS{1'b0}};
+    end else if(fsm_state == FSM_RECV && next_bit ) begin
+        recieved_data[PAYLOAD_BITS-1] <= bit_sample;
+        for ( i = PAYLOAD_BITS-2; i >= 0; i = i - 1) begin
+            recieved_data[i] <= recieved_data[i+1];
+        end
+    end
+end
+
+//
+// Increments the bit counter when recieving.
+always @(posedge clk) begin : p_bit_counter
+    if(!resetn) begin
+        bit_counter <= 4'b0;
+    end else if(fsm_state != FSM_RECV) begin
+        bit_counter <= {COUNT_REG_LEN{1'b0}};
+    end else if(fsm_state == FSM_RECV && next_bit) begin
+        bit_counter <= bit_counter + 1'b1;
+    end
+end
+
+//
+// Sample the recieved bit when in the middle of a bit frame.
+always @(posedge clk) begin : p_bit_sample
+    if(!resetn) begin
+        bit_sample <= 1'b0;
+    end else if (cycle_counter == CYCLES_PER_BIT/2) begin
+        bit_sample <= rxd_reg;
+    end
+end
+
+
+//
+// Increments the cycle counter when recieving.
+always @(posedge clk) begin : p_cycle_counter
+    if(!resetn) begin
+        cycle_counter <= {COUNT_REG_LEN{1'b0}};
+    end else if(next_bit) begin
+        cycle_counter <= {COUNT_REG_LEN{1'b0}};
+    end else if(fsm_state == FSM_START || 
+                fsm_state == FSM_RECV  || 
+                fsm_state == FSM_STOP   ) begin
+        cycle_counter <= cycle_counter + 1'b1;
+    end
+end
+
+
+//
+// Progresses the next FSM state.
+always @(posedge clk) begin : p_fsm_state
+    if(!resetn) begin
+        fsm_state <= FSM_IDLE;
+    end else begin
+        fsm_state <= n_fsm_state;
+    end
+end
+
+
+//
+// Responsible for updating the internal value of the rxd_reg.
+always @(posedge clk) begin : p_rxd_reg
+    if(!resetn) begin
+        rxd_reg     <= 1'b1;
+        rxd_reg_0   <= 1'b1;
+    end else if(uart_rx_en) begin
+        rxd_reg     <= rxd_reg_0;
+        rxd_reg_0   <= uart_rxd;
+    end
+end
+
+
+endmodule

AngeloJacobo_UberDDR3/example_demo/alinx_ax7325b/uart_tx.v

@@ -0,0 +1,187 @@
+
+
+// 
+// Module: uart_tx 
+// 
+// Notes:
+// - UART transmitter module.
+//
+
+module uart_tx(
+input  wire         clk         , // Top level system clock input.
+input  wire         resetn      , // Asynchronous active low reset.
+output wire         uart_txd    , // UART transmit pin.
+output wire         uart_tx_busy, // Module busy sending previous item.
+input  wire         uart_tx_en  , // Send the data on uart_tx_data
+input  wire [PAYLOAD_BITS-1:0]   uart_tx_data  // The data to be sent
+);
+
+// --------------------------------------------------------------------------- 
+// External parameters.
+// 
+
+//
+// Input bit rate of the UART line.
+parameter   BIT_RATE        = 9600; // bits / sec
+localparam  BIT_P           = 1_000_000_000 * 1/BIT_RATE; // nanoseconds
+
+//
+// Clock frequency in hertz.
+parameter   CLK_HZ          =    50_000_000;
+localparam  CLK_P           = 1_000_000_000 * 1/CLK_HZ; // nanoseconds
+
+//
+// Number of data bits recieved per UART packet.
+parameter   PAYLOAD_BITS    = 8;
+
+//
+// Number of stop bits indicating the end of a packet.
+parameter   STOP_BITS       = 1;
+
+// --------------------------------------------------------------------------- 
+// Internal parameters.
+// 
+
+//
+// Number of clock cycles per uart bit.
+localparam       CYCLES_PER_BIT     = BIT_P / CLK_P;
+
+//
+// Size of the registers which store sample counts and bit durations.
+localparam       COUNT_REG_LEN      = 1+$clog2(CYCLES_PER_BIT);
+
+// --------------------------------------------------------------------------- 
+// Internal registers.
+// 
+
+//
+// Internally latched value of the uart_txd line. Helps break long timing
+// paths from the logic to the output pins.
+reg txd_reg;
+
+//
+// Storage for the serial data to be sent.
+reg [PAYLOAD_BITS-1:0] data_to_send;
+
+//
+// Counter for the number of cycles over a packet bit.
+reg [COUNT_REG_LEN-1:0] cycle_counter;
+
+//
+// Counter for the number of sent bits of the packet.
+reg [3:0] bit_counter;
+
+//
+// Current and next states of the internal FSM.
+reg [2:0] fsm_state;
+reg [2:0] n_fsm_state;
+
+localparam FSM_IDLE = 0;
+localparam FSM_START= 1;
+localparam FSM_SEND = 2;
+localparam FSM_STOP = 3;
+
+
+// --------------------------------------------------------------------------- 
+// FSM next state selection.
+// 
+
+assign uart_tx_busy = fsm_state != FSM_IDLE;
+assign uart_txd     = txd_reg;
+
+wire next_bit     = cycle_counter == CYCLES_PER_BIT;
+wire payload_done = bit_counter   == PAYLOAD_BITS  ;
+wire stop_done    = bit_counter   == STOP_BITS && fsm_state == FSM_STOP;
+
+//
+// Handle picking the next state.
+always @(*) begin : p_n_fsm_state
+    case(fsm_state)
+        FSM_IDLE : n_fsm_state = uart_tx_en   ? FSM_START: FSM_IDLE ;
+        FSM_START: n_fsm_state = next_bit     ? FSM_SEND : FSM_START;
+        FSM_SEND : n_fsm_state = payload_done ? FSM_STOP : FSM_SEND ;
+        FSM_STOP : n_fsm_state = stop_done    ? FSM_IDLE : FSM_STOP ;
+        default  : n_fsm_state = FSM_IDLE;
+    endcase
+end
+
+// --------------------------------------------------------------------------- 
+// Internal register setting and re-setting.
+// 
+
+//
+// Handle updates to the sent data register.
+integer i = 0;
+always @(posedge clk) begin : p_data_to_send
+    if(!resetn) begin
+        data_to_send <= {PAYLOAD_BITS{1'b0}};
+    end else if(fsm_state == FSM_IDLE && uart_tx_en) begin
+        data_to_send <= uart_tx_data;
+    end else if(fsm_state       == FSM_SEND       && next_bit ) begin
+        for ( i = PAYLOAD_BITS-2; i >= 0; i = i - 1) begin
+            data_to_send[i] <= data_to_send[i+1];
+        end
+    end
+end
+
+
+//
+// Increments the bit counter each time a new bit frame is sent.
+always @(posedge clk) begin : p_bit_counter
+    if(!resetn) begin
+        bit_counter <= 4'b0;
+    end else if(fsm_state != FSM_SEND && fsm_state != FSM_STOP) begin
+        bit_counter <= {COUNT_REG_LEN{1'b0}};
+    end else if(fsm_state == FSM_SEND && n_fsm_state == FSM_STOP) begin
+        bit_counter <= {COUNT_REG_LEN{1'b0}};
+    end else if(fsm_state == FSM_STOP&& next_bit) begin
+        bit_counter <= bit_counter + 1'b1;
+    end else if(fsm_state == FSM_SEND && next_bit) begin
+        bit_counter <= bit_counter + 1'b1;
+    end
+end
+
+
+//
+// Increments the cycle counter when sending.
+always @(posedge clk) begin : p_cycle_counter
+    if(!resetn) begin
+        cycle_counter <= {COUNT_REG_LEN{1'b0}};
+    end else if(next_bit) begin
+        cycle_counter <= {COUNT_REG_LEN{1'b0}};
+    end else if(fsm_state == FSM_START || 
+                fsm_state == FSM_SEND  || 
+                fsm_state == FSM_STOP   ) begin
+        cycle_counter <= cycle_counter + 1'b1;
+    end
+end
+
+
+//
+// Progresses the next FSM state.
+always @(posedge clk) begin : p_fsm_state
+    if(!resetn) begin
+        fsm_state <= FSM_IDLE;
+    end else begin
+        fsm_state <= n_fsm_state;
+    end
+end
+
+
+//
+// Responsible for updating the internal value of the txd_reg.
+always @(posedge clk) begin : p_txd_reg
+    if(!resetn) begin
+        txd_reg <= 1'b1;
+    end else if(fsm_state == FSM_IDLE) begin
+        txd_reg <= 1'b1;
+    end else if(fsm_state == FSM_START) begin
+        txd_reg <= 1'b0;
+    end else if(fsm_state == FSM_SEND) begin
+        txd_reg <= data_to_send[0];
+    end else if(fsm_state == FSM_STOP) begin
+        txd_reg <= 1'b1;
+    end
+end
+
+endmodule

AngeloJacobo_UberDDR3/example_demo/arty_s7/Makefile

@@ -0,0 +1,116 @@
+PROJECT = arty_ddr3
+BOARD = arty_s7_50
+FAMILY = spartan7
+PART = xc7s50csga324-1
+CHIPDB  = ${SPARTAN7_CHIPDB}
+ADDITIONAL_SOURCES = ../../rtl/ddr3_controller.v  ../../rtl/ddr3_phy.v  ../../rtl/ddr3_top.v  uart_rx.v  uart_tx.v clk_wiz.v 
+
+
+#############################################################################################
+NEXTPNR_XILINX_DIR ?= /snap/openxc7/current/opt/nextpnr-xilinx
+NEXTPNR_XILINX_PYTHON_DIR ?= ${NEXTPNR_XILINX_DIR}/python
+PRJXRAY_DB_DIR ?= ${NEXTPNR_XILINX_DIR}/external/prjxray-db
+
+DBPART = $(shell echo ${PART} | sed -e 's/-[0-9]//g')
+SPEEDGRADE = $(shell echo ${PART} | sed -e 's/.*\-\([0-9]\)/\1/g')
+
+CHIPDB ?= ./
+ifeq ($(CHIPDB),)
+CHIPDB = ./
+endif
+
+PYPY3 ?= pypy3
+
+TOP ?= ${PROJECT}
+TOP_MODULE ?= ${TOP}
+TOP_VERILOG ?= ${TOP}.v
+
+PNR_DEBUG ?= # --verbose --debug
+
+JTAG_LINK ?= --board ${BOARD}
+
+XDC ?= ${PROJECT}.xdc
+
+.PHONY: openxc7
+openxc7: ${PROJECT}_openxc7.bit
+
+.PHONY: program
+program: ${PROJECT}_openxc7.bit
+	openFPGALoader ${JTAG_LINK} --bitstream $<
+
+${PROJECT}.json: ${TOP_VERILOG} ${ADDITIONAL_SOURCES}
+	yosys -p "synth_xilinx -flatten -abc9 ${SYNTH_OPTS} -arch xc7 -top ${TOP_MODULE}; write_json ${PROJECT}.json" $< ${ADDITIONAL_SOURCES}
+
+# The chip database only needs to be generated once
+# that is why we don't clean it with make clean
+${CHIPDB}/${DBPART}.bin:
+	${PYPY3} ${NEXTPNR_XILINX_PYTHON_DIR}/bbaexport.py --device ${PART} --bba ${DBPART}.bba
+	bbasm -l ${DBPART}.bba ${CHIPDB}/${DBPART}.bin
+	rm -f ${DBPART}.bba
+
+${PROJECT}.fasm: ${PROJECT}.json ${CHIPDB}/${DBPART}.bin ${XDC}
+	nextpnr-xilinx --chipdb ${CHIPDB}/${DBPART}.bin --xdc ${XDC} --json ${PROJECT}.json --fasm $@ ${PNR_ARGS} ${PNR_DEBUG}
+	
+${PROJECT}.frames: ${PROJECT}.fasm
+	fasm2frames --part ${PART} --db-root ${PRJXRAY_DB_DIR}/${FAMILY} $< > $@
+
+${PROJECT}_openxc7.bit: ${PROJECT}.frames
+	xc7frames2bit --part_file ${PRJXRAY_DB_DIR}/${FAMILY}/${PART}/part.yaml --part_name ${PART} --frm_file $< --output_file $@
+
+
+#############################################################################################
+# SPDX-License-Identifier: MIT
+# Generated from https://github.com/FPGAOL-CE/caas-wizard
+#
+BUILDDIR := ${CURDIR}/build
+
+LOGFILE := ${BUILDDIR}/top.log
+
+# Build design
+.PHONY: vivado
+vivado: ${BUILDDIR}/${PROJECT}_vivado.bit
+
+${BUILDDIR}:
+	mkdir -m 777 -p ${BUILDDIR} && chown -R nobody ${BUILDDIR} | true
+
+.ONESHELL: 
+${BUILDDIR}/vivado.tcl: ${BUILDDIR}
+	cat << EOF > $@
+	# vivado.tcl generated for FPGAOL-CE/caas-wizard
+	# can be launched from any directory
+	cd ${BUILDDIR}
+	create_project -part ${PART} -force v_proj
+	set_property target_language Verilog [current_project]
+	cd ..
+	read_verilog [glob ${PROJECT}.v ${ADDITIONAL_SOURCES}]
+	read_xdc [glob  $(wildcard ${PROJECT}_vivado.xdc) ]
+	cd build
+	synth_design -top ${PROJECT}
+	opt_design
+	place_design
+	phys_opt_design
+	route_design
+	write_bitstream -verbose -force ${PROJECT}_vivado.bit
+	# report_utilization -file util.rpt
+	# report_timing_summary -file timing.rpt
+	EOF
+
+${BUILDDIR}/${PROJECT}_vivado.bit: ${BUILDDIR}/vivado.tcl
+	cd ${BUILDDIR} && vivado -mode batch -source $< > ${LOGFILE} 2>&1
+
+.PHONY: program_vivado
+program_vivado: 
+	openFPGALoader ${JTAG_LINK} --bitstream ${BUILDDIR}/${PROJECT}_vivado.bit
+
+
+#############################################################################################
+
+.PHONY: clean
+clean:
+	rm -f *.bit
+	rm -f *.frames
+	rm -f *.fasm
+	rm -f *.json
+	rm -f *.bin
+	rm -f *.bba
+	rm -rf ${BUILDDIR}

AngeloJacobo_UberDDR3/example_demo/arty_s7/arty_ddr3.v

@@ -0,0 +1,247 @@
+////////////////////////////////////////////////////////////////////////////////
+//
+// Filename: arty_ddr3.v
+// Project: UberDDR3 - An Open Source DDR3 Controller
+//
+// Purpose: Example demo of UberDDR3 for Arty-S7. Mechanism:
+//          - four LEDs will light up once UberDDR3 is done calibrating
+//          - if UART (9600 Baud Rate)receives small letter ASCII (a-z), this value will be written to DDR3 
+//          - if UART receives capital letter ASCII (A-Z), the small letter equivalent will be retrieved from DDR3 by doing
+//          - a read request, once read data is available this will be sent to UART to be streamed out.
+//          THUS:
+//          - Sendng "abcdefg" to the UART terminal will store that small latter to DDR3
+//          - Then sending "ABCDEFG" to the UART terminal will return the small letter equivalent: "abcdefg"
+//
+// Engineer: Angelo C. Jacobo
+//
+////////////////////////////////////////////////////////////////////////////////
+//
+// Copyright (C) 2023-2025  Angelo Jacobo
+// 
+//     This program is free software: you can redistribute it and/or modify
+//     it under the terms of the GNU General Public License as published by
+//     the Free Software Foundation, either version 3 of the License, or
+//     (at your option) any later version.
+// 
+//     This program is distributed in the hope that it will be useful,
+//     but WITHOUT ANY WARRANTY; without even the implied warranty of
+//     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//     GNU General Public License for more details.
+// 
+//     You should have received a copy of the GNU General Public License
+//     along with this program.  If not, see <https://www.gnu.org/licenses/>.
+//
+////////////////////////////////////////////////////////////////////////////////
+
+`timescale 1ns / 1ps
+
+   module arty_ddr3
+	(
+	input wire i_clk, 
+	input wire i_rst,
+	// DDR3 I/O Interface
+    output wire ddr3_clk_p, ddr3_clk_n,
+    output wire ddr3_reset_n,
+    output wire ddr3_cke, // CKE
+    output wire ddr3_cs_n, // chip select signal
+    output wire ddr3_ras_n, // RAS#
+    output wire ddr3_cas_n, // CAS#
+    output wire ddr3_we_n, // WE#
+    output wire[14-1:0] ddr3_addr,
+    output wire[3-1:0] ddr3_ba,
+    inout wire[16-1:0] ddr3_dq,
+    inout wire[2-1:0] ddr3_dqs_p, ddr3_dqs_n,
+    output wire[2-1:0] ddr3_dm,
+    output wire ddr3_odt, // on-die termination
+    // UART line
+	input wire rx,
+	output wire tx,
+	//Debug LEDs
+	output wire[3:0] led
+    );
+     
+     wire i_controller_clk, i_ddr3_clk, i_ref_clk, i_ddr3_clk_90;
+     wire m_axis_tvalid;
+     wire rx_empty;
+     wire tx_full;
+     wire o_wb_ack;
+     wire[7:0] o_wb_data;
+     wire[7:0] rd_data;
+     wire o_wb_stall;
+     reg i_wb_stb = 0, i_wb_we;
+     wire[31:0] o_debug1;
+     reg[7:0] i_wb_data;
+     reg[7:0] i_wb_addr;
+     wire user_temp_alarm_out; // asserts if XADC detects internal temp to be above user temp alarm
+     
+     // o_debug1 taps on value of state_calibrate (can be traced inside ddr3_controller module)
+     assign led[0] = (o_debug1[4:0] != 23); //light up if not at DONE_CALIBRATE
+     assign led[1] = (o_debug1[4:0] == 23 && !user_temp_alarm_out); //light up if at DONE_CALIBRATE
+     assign led[2] = (o_debug1[4:0] == 23 && !user_temp_alarm_out); //light up if at DONE_CALIBRATE
+     assign led[3] = (o_debug1[4:0] == 23 && !user_temp_alarm_out); //light up if at DONE_CALIBRATE
+     
+    // always @(posedge i_controller_clk) begin
+    //     begin
+    //         i_wb_stb <= 0;
+    //         i_wb_we <= 0;
+    //         i_wb_addr <= 0;
+    //         i_wb_data <= 0;
+    //         if(!o_wb_stall && m_axis_tvalid) begin
+    //             if(rd_data >= 97 && rd_data <= 122) begin //write to DDR3 if ASCII is small letter
+    //                 i_wb_stb <= 1;                 
+    //                 i_wb_we <= 1;                  
+    //                 i_wb_addr <= ~rd_data ;                
+    //                 i_wb_data <= rd_data; 
+    //             end
+    //             else if(rd_data >= 65 && rd_data <= 90) begin //read from DDR3 if ASCII is capital letter
+    //                 i_wb_stb <= 1; //make request
+    //                 i_wb_we <= 0; //read
+    //                 i_wb_addr <= ~(rd_data + 8'd32);
+    //             end
+    //         end
+    //     end
+    // end
+     
+    (* mark_debug = "true" *) wire clk_locked;
+    clk_wiz clk_wiz_inst
+    (
+    // Clock out ports
+    .clk_out1(i_controller_clk), //83.333 Mhz
+    .clk_out2(i_ddr3_clk), // 333.333 MHz
+    .clk_out3(i_ref_clk), //200MHz
+    .clk_out4(i_ddr3_clk_90), // 333.333 MHz with 90degree shift
+    // Status and control signals
+    .reset(i_rst),
+    .locked(clk_locked),
+    // Clock in ports
+    .clk_in1(i_clk)
+    );
+    
+    // // UART TX/RXmodule from https://github.com/ben-marshall/uart
+    // uart_tx #(
+    //     .BIT_RATE(9600),
+    //     .CLK_HZ(83_333_333),
+    //     .PAYLOAD_BITS(8),
+    //     .STOP_BITS(1)
+    //     ) uart_tx_inst (
+    //     .clk(i_controller_clk), // Top level system clock input.
+    //     .resetn(!i_rst && clk_locked && o_debug1[4:0] == 23), // Asynchronous active low reset.
+    //     .uart_txd(tx), // UART transmit pin.
+    //     .uart_tx_busy(), // Module busy sending previous item.
+    //     .uart_tx_en(o_wb_ack), // Send the data on uart_tx_data
+    //     .uart_tx_data(o_wb_data) // The data to be sent
+    // );
+    // uart_rx #(
+    //     .BIT_RATE(9600),
+    //     .CLK_HZ(83_333_333),
+    //     .PAYLOAD_BITS(8),
+    //     .STOP_BITS(1)
+    // ) uart_rx_inst (
+    //     .clk(i_controller_clk), // Top level system clock input.
+    //     .resetn(!i_rst && clk_locked && o_debug1[4:0] == 23), // Asynchronous active low reset.
+    //     .uart_rxd(rx), // UART Recieve pin.
+    //     .uart_rx_en(o_debug1[4:0] == 23), // Recieve enable
+    //     .uart_rx_break(), // Did we get a BREAK message?
+    //     .uart_rx_valid(m_axis_tvalid), // Valid data recieved/available.
+    //     .uart_rx_data(rd_data)   // The recieved data.
+    // );
+    
+    // `define XADC
+     `ifdef XADC
+         xadc_wiz_0 xadc_inst (
+              .dclk_in(i_controller_clk), // Clock input for the dynamic reconfiguration port
+              .user_temp_alarm_out(user_temp_alarm_out) // Temperature-sensor alarm output
+            );
+      `else
+            assign user_temp_alarm_out = 1'b0;
+    `endif
+
+    // UART module from https://github.com/alexforencich/verilog-uart (DOES NOT WORK ON OPENXC7, UberDDR3 cannot finish calibration when this UART is used)
+    //    uart #(.DATA_WIDTH(8)) uart_m
+    //    (
+    //         .clk(i_controller_clk),
+    //         .rst(i_rst),
+    //         .s_axis_tdata(o_wb_data),
+    //         .s_axis_tvalid(o_wb_ack),
+    //         .s_axis_tready(),
+    //         .m_axis_tdata(rd_data),
+    //         .m_axis_tvalid(m_axis_tvalid),
+    //         .m_axis_tready(1),
+    //         .rxd(rx),
+    //         .txd(tx),
+    //        .prescale(1085) //9600 Baud Rate (83.33MHz/(8*9600))
+    //    );
+    
+    // DDR3 Controller 
+    ddr3_top #(
+        .CONTROLLER_CLK_PERIOD(12_000), //ps, clock period of the controller interface
+        .DDR3_CLK_PERIOD(3_000), //ps, clock period of the DDR3 RAM device (must be 1/4 of the CONTROLLER_CLK_PERIOD) 
+        .ROW_BITS(14), //width of row address
+        .COL_BITS(10), //width of column address
+        .BA_BITS(3), //width of bank address
+        .BYTE_LANES(2), //number of DDR3 modules to be controlled
+        .AUX_WIDTH(4), //width of aux line (must be >= 4) 
+        .WB2_ADDR_BITS(32), //width of 2nd wishbone address bus 
+        .WB2_DATA_BITS(32), //width of 2nd wishbone data bus
+        .MICRON_SIM(0), //enable faster simulation for micron ddr3 model (shorten POWER_ON_RESET_HIGH and INITIAL_CKE_LOW)
+        .ODELAY_SUPPORTED(0), //set to 1 when ODELAYE2 is supported
+        .SECOND_WISHBONE(0), //set to 1 if 2nd wishbone is needed 
+        .ECC_ENABLE(0), // set to 1 or 2 to add ECC (1 = Side-band ECC per burst, 2 = Side-band ECC per 8 bursts , 3 = Inline ECC ) 
+        .WB_ERROR(0), // set to 1 to support Wishbone error (asserts at ECC double bit error)
+        .BIST_MODE(1), // 0 = No BIST, 1 = run through all address space ONCE , 2 = run through all address space for every test (burst w/r, random w/r, alternating r/w)
+        .SPEED_BIN(1) // 0 = Use top-level parameters , 1 = DDR3-1066 (7-7-7) , 2 = DR3-1333 (9-9-9) , 3 = DDR3-1600 (11-11-11)
+        ) ddr3_top
+        (
+            //clock and reset
+            .i_controller_clk(i_controller_clk),
+            .i_ddr3_clk(i_ddr3_clk), //i_controller_clk has period of CONTROLLER_CLK_PERIOD, i_ddr3_clk has period of DDR3_CLK_PERIOD 
+            .i_ref_clk(i_ref_clk),
+            .i_ddr3_clk_90(i_ddr3_clk_90),
+            .i_rst_n(!i_rst && clk_locked && !user_temp_alarm_out), 
+            // Wishbone inputs
+            .i_wb_cyc(1), //bus cycle active (1 = normal operation, 0 = all ongoing transaction are to be cancelled)
+            .i_wb_stb(i_wb_stb), //request a transfer
+            .i_wb_we(i_wb_we), //write-enable (1 = write, 0 = read)
+            .i_wb_addr(i_wb_addr), //burst-addressable {row,bank,col} 
+            .i_wb_data(i_wb_data), //write data, for a 4:1 controller data width is 8 times the number of pins on the device
+            .i_wb_sel(16'hffff), //byte strobe for write (1 = write the byte)
+            .i_aux(i_wb_we), //for AXI-interface compatibility (given upon strobe)
+            // Wishbone outputs
+            .o_wb_stall(o_wb_stall), //1 = busy, cannot accept requests
+            .o_wb_ack(o_wb_ack), //1 = read/write request has completed
+            .o_wb_err(), //1 = Error due to ECC double bit error (fixed to 0 if WB_ERROR = 0)
+            .o_wb_data(o_wb_data), //read data, for a 4:1 controller data width is 8 times the number of pins on the device
+            .o_aux(),
+            // Wishbone 2 (PHY) inputs
+            .i_wb2_cyc(), //bus cycle active (1 = normal operation, 0 = all ongoing transaction are to be cancelled)
+            .i_wb2_stb(), //request a transfer
+            .i_wb2_we(), //write-enable (1 = write, 0 = read)
+            .i_wb2_addr(), //burst-addressable {row,bank,col} 
+            .i_wb2_data(), //write data, for a 4:1 controller data width is 8 times the number of pins on the device
+            .i_wb2_sel(), //byte strobe for write (1 = write the byte)
+            // Wishbone 2 (Controller) outputs
+            .o_wb2_stall(), //1 = busy, cannot accept requests
+            .o_wb2_ack(), //1 = read/write request has completed
+            .o_wb2_data(), //read data, for a 4:1 controller data width is 8 times the number of pins on the device
+            // PHY Interface (to be added later)
+            // DDR3 I/O Interface
+            .o_ddr3_clk_p(ddr3_clk_p),
+            .o_ddr3_clk_n(ddr3_clk_n),
+            .o_ddr3_reset_n(ddr3_reset_n),
+            .o_ddr3_cke(ddr3_cke), // CKE
+            .o_ddr3_cs_n(ddr3_cs_n), // chip select signal (controls rank 1 only)
+            .o_ddr3_ras_n(ddr3_ras_n), // RAS#
+            .o_ddr3_cas_n(ddr3_cas_n), // CAS#
+            .o_ddr3_we_n(ddr3_we_n), // WE#
+            .o_ddr3_addr(ddr3_addr),
+            .o_ddr3_ba_addr(ddr3_ba),
+            .io_ddr3_dq(ddr3_dq),
+            .io_ddr3_dqs(ddr3_dqs_p),
+            .io_ddr3_dqs_n(ddr3_dqs_n),
+            .o_ddr3_dm(ddr3_dm),
+            .o_ddr3_odt(ddr3_odt), // on-die termination
+            .o_debug1(o_debug1)
+        );
+
+endmodule
+

AngeloJacobo_UberDDR3/example_demo/arty_s7/arty_ddr3.xdc

@@ -0,0 +1,265 @@
+## This file is a general .xdc for the Arty S7-50 Rev. E
+## To use it in a project:
+## - uncomment the lines corresponding to used pins
+## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
+
+## Clock Signals
+set_property -dict {PACKAGE_PIN R2 IOSTANDARD SSTL135} [get_ports i_clk]
+create_clock -period 10.000 -name sys_clk_pin -waveform {0.000 5.000} -add [get_ports i_clk]
+
+## LEDs
+set_property -dict {PACKAGE_PIN E18 IOSTANDARD LVCMOS33} [get_ports {led[0]}]
+set_property -dict {PACKAGE_PIN F13 IOSTANDARD LVCMOS33} [get_ports {led[1]}]
+set_property -dict {PACKAGE_PIN E13 IOSTANDARD LVCMOS33} [get_ports {led[2]}]
+set_property -dict {PACKAGE_PIN H15 IOSTANDARD LVCMOS33} [get_ports {led[3]}]
+
+## Buttons
+set_property -dict {PACKAGE_PIN G15 IOSTANDARD LVCMOS33} [get_ports i_rst]
+
+## USB-UART Interface
+set_property -dict {PACKAGE_PIN R12 IOSTANDARD LVCMOS33} [get_ports tx]
+set_property -dict {PACKAGE_PIN V12 IOSTANDARD LVCMOS33} [get_ports rx]
+
+
+############## DDR3 ##################
+# DQ PINS
+set_property SLEW FAST [get_ports {ddr3_dq[0]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[0]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[0]}]
+set_property PACKAGE_PIN K2 [get_ports {ddr3_dq[0]}]
+
+set_property SLEW FAST [get_ports {ddr3_dq[1]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[1]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[1]}]
+set_property PACKAGE_PIN K3 [get_ports {ddr3_dq[1]}]
+
+set_property SLEW FAST [get_ports {ddr3_dq[2]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[2]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[2]}]
+set_property PACKAGE_PIN L4 [get_ports {ddr3_dq[2]}]
+
+set_property SLEW FAST [get_ports {ddr3_dq[3]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[3]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[3]}]
+set_property PACKAGE_PIN M6 [get_ports {ddr3_dq[3]}]
+
+set_property SLEW FAST [get_ports {ddr3_dq[4]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[4]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[4]}]
+set_property PACKAGE_PIN K6 [get_ports {ddr3_dq[4]}]
+
+set_property SLEW FAST [get_ports {ddr3_dq[5]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[5]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[5]}]
+set_property PACKAGE_PIN M4 [get_ports {ddr3_dq[5]}]
+
+set_property SLEW FAST [get_ports {ddr3_dq[6]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[6]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[6]}]
+set_property PACKAGE_PIN L5 [get_ports {ddr3_dq[6]}]
+
+set_property SLEW FAST [get_ports {ddr3_dq[7]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[7]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[7]}]
+set_property PACKAGE_PIN L6 [get_ports {ddr3_dq[7]}]
+
+set_property SLEW FAST [get_ports {ddr3_dq[8]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[8]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[8]}]
+set_property PACKAGE_PIN N4 [get_ports {ddr3_dq[8]}]
+
+set_property SLEW FAST [get_ports {ddr3_dq[9]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[9]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[9]}]
+set_property PACKAGE_PIN R1 [get_ports {ddr3_dq[9]}]
+
+set_property SLEW FAST [get_ports {ddr3_dq[10]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[10]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[10]}]
+set_property PACKAGE_PIN N1 [get_ports {ddr3_dq[10]}]
+
+set_property SLEW FAST [get_ports {ddr3_dq[11]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[11]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[11]}]
+set_property PACKAGE_PIN N5 [get_ports {ddr3_dq[11]}]
+
+set_property SLEW FAST [get_ports {ddr3_dq[12]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[12]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[12]}]
+set_property PACKAGE_PIN M2 [get_ports {ddr3_dq[12]}]
+
+set_property SLEW FAST [get_ports {ddr3_dq[13]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[13]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[13]}]
+set_property PACKAGE_PIN P1 [get_ports {ddr3_dq[13]}]
+
+set_property SLEW FAST [get_ports {ddr3_dq[14]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[14]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[14]}]
+set_property PACKAGE_PIN M1 [get_ports {ddr3_dq[14]}]
+
+set_property SLEW FAST [get_ports {ddr3_dq[15]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[15]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[15]}]
+set_property PACKAGE_PIN P2 [get_ports {ddr3_dq[15]}]
+
+# Address Pins
+set_property SLEW FAST [get_ports {ddr3_addr[13]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[13]}]
+set_property PACKAGE_PIN U6 [get_ports {ddr3_addr[13]}]
+
+set_property SLEW FAST [get_ports {ddr3_addr[12]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[12]}]
+set_property PACKAGE_PIN R6 [get_ports {ddr3_addr[12]}]
+
+set_property SLEW FAST [get_ports {ddr3_addr[11]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[11]}]
+set_property PACKAGE_PIN T5 [get_ports {ddr3_addr[11]}]
+
+set_property SLEW FAST [get_ports {ddr3_addr[10]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[10]}]
+set_property PACKAGE_PIN P6 [get_ports {ddr3_addr[10]}]
+
+set_property SLEW FAST [get_ports {ddr3_addr[9]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[9]}]
+set_property PACKAGE_PIN V7 [get_ports {ddr3_addr[9]}]
+
+set_property SLEW FAST [get_ports {ddr3_addr[8]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[8]}]
+set_property PACKAGE_PIN U7 [get_ports {ddr3_addr[8]}]
+
+set_property SLEW FAST [get_ports {ddr3_addr[7]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[7]}]
+set_property PACKAGE_PIN T6 [get_ports {ddr3_addr[7]}]
+
+set_property SLEW FAST [get_ports {ddr3_addr[6]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[6]}]
+set_property PACKAGE_PIN V6 [get_ports {ddr3_addr[6]}]
+
+set_property SLEW FAST [get_ports {ddr3_addr[5]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[5]}]
+set_property PACKAGE_PIN R7 [get_ports {ddr3_addr[5]}]
+
+set_property SLEW FAST [get_ports {ddr3_addr[4]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[4]}]
+set_property PACKAGE_PIN T3 [get_ports {ddr3_addr[4]}]
+
+set_property SLEW FAST [get_ports {ddr3_addr[3]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[3]}]
+set_property PACKAGE_PIN V4 [get_ports {ddr3_addr[3]}]
+
+set_property SLEW FAST [get_ports {ddr3_addr[2]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[2]}]
+set_property PACKAGE_PIN V2 [get_ports {ddr3_addr[2]}]
+
+set_property SLEW FAST [get_ports {ddr3_addr[1]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[1]}]
+set_property PACKAGE_PIN R4 [get_ports {ddr3_addr[1]}]
+
+set_property SLEW FAST [get_ports {ddr3_addr[0]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[0]}]
+set_property PACKAGE_PIN U2 [get_ports {ddr3_addr[0]}]
+
+# Bank Pins
+set_property SLEW FAST [get_ports {ddr3_ba[2]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_ba[2]}]
+set_property PACKAGE_PIN U3 [get_ports {ddr3_ba[2]}]
+
+set_property SLEW FAST [get_ports {ddr3_ba[1]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_ba[1]}]
+set_property PACKAGE_PIN T1 [get_ports {ddr3_ba[1]}]
+
+set_property SLEW FAST [get_ports {ddr3_ba[0]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_ba[0]}]
+set_property PACKAGE_PIN V5 [get_ports {ddr3_ba[0]}]
+
+# Command Pins
+set_property SLEW FAST [get_ports ddr3_ras_n]
+set_property IOSTANDARD SSTL135 [get_ports ddr3_ras_n]
+set_property PACKAGE_PIN U1 [get_ports ddr3_ras_n]
+
+set_property SLEW FAST [get_ports ddr3_cas_n]
+set_property IOSTANDARD SSTL135 [get_ports ddr3_cas_n]
+set_property PACKAGE_PIN V3 [get_ports ddr3_cas_n]
+
+set_property SLEW FAST [get_ports ddr3_we_n]
+set_property IOSTANDARD SSTL135 [get_ports ddr3_we_n]
+set_property PACKAGE_PIN P7 [get_ports ddr3_we_n]
+
+set_property SLEW FAST [get_ports ddr3_reset_n]
+set_property IOSTANDARD SSTL135 [get_ports ddr3_reset_n]
+set_property PACKAGE_PIN J6 [get_ports ddr3_reset_n]
+
+set_property SLEW FAST [get_ports ddr3_cke]
+set_property IOSTANDARD SSTL135 [get_ports ddr3_cke]
+set_property PACKAGE_PIN T2 [get_ports ddr3_cke]
+
+
+set_property SLEW FAST [get_ports ddr3_odt]
+set_property IOSTANDARD SSTL135 [get_ports ddr3_odt]
+set_property PACKAGE_PIN P5 [get_ports ddr3_odt]
+
+
+set_property SLEW FAST [get_ports ddr3_cs_n]
+set_property IOSTANDARD SSTL135 [get_ports ddr3_cs_n]
+set_property PACKAGE_PIN R3 [get_ports ddr3_cs_n]
+
+# Data Mask Pins
+set_property SLEW FAST [get_ports {ddr3_dm[0]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_dm[0]}]
+set_property PACKAGE_PIN K4 [get_ports {ddr3_dm[0]}]
+
+set_property SLEW FAST [get_ports {ddr3_dm[1]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_dm[1]}]
+set_property PACKAGE_PIN M3 [get_ports {ddr3_dm[1]}]
+
+# DQS Pins
+set_property SLEW FAST [get_ports {ddr3_dqs_p[0]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dqs_p[0]}]
+set_property IOSTANDARD DIFF_SSTL135 [get_ports {ddr3_dqs_p[0]}]
+
+set_property SLEW FAST [get_ports {ddr3_dqs_n[0]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dqs_n[0]}]
+set_property IOSTANDARD DIFF_SSTL135 [get_ports {ddr3_dqs_n[0]}]
+set_property PACKAGE_PIN K1 [get_ports {ddr3_dqs_p[0]}]
+set_property PACKAGE_PIN L1 [get_ports {ddr3_dqs_n[0]}]
+
+set_property SLEW FAST [get_ports {ddr3_dqs_p[1]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dqs_p[1]}]
+set_property IOSTANDARD DIFF_SSTL135 [get_ports {ddr3_dqs_p[1]}]
+
+set_property SLEW FAST [get_ports {ddr3_dqs_n[1]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dqs_n[1]}]
+set_property IOSTANDARD DIFF_SSTL135 [get_ports {ddr3_dqs_n[1]}]
+set_property PACKAGE_PIN N3 [get_ports {ddr3_dqs_p[1]}]
+set_property PACKAGE_PIN N2 [get_ports {ddr3_dqs_n[1]}]
+
+# Clock Pins
+set_property SLEW FAST [get_ports ddr3_clk_p]
+set_property IOSTANDARD DIFF_SSTL135 [get_ports ddr3_clk_p]
+
+set_property SLEW FAST [get_ports ddr3_clk_n]
+set_property IOSTANDARD DIFF_SSTL135 [get_ports ddr3_clk_n]
+set_property PACKAGE_PIN R5 [get_ports ddr3_clk_p]
+set_property PACKAGE_PIN T4 [get_ports ddr3_clk_n]
+
+
+
+
+
+## Configuration options, can be used for all designs
+set_property BITSTREAM.CONFIG.CONFIGRATE 50 [current_design]
+set_property CONFIG_VOLTAGE 3.3 [current_design]
+set_property CFGBVS VCCO [current_design]
+set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
+set_property CONFIG_MODE SPIx4 [current_design]
+
+## SW3 is assigned to a pin M5 in the 1.35v bank. This pin can also be used as
+## the VREF for BANK 34. To ensure that SW3 does not define the reference voltage
+## and to be able to use this pin as an ordinary I/O the following property must
+## be set to enable an internal VREF for BANK 34. Since a 1.35v supply is being
+## used the internal reference is set to half that value (i.e. 0.675v). Note that
+## this property must be set even if SW3 is not used in the design.
+#  set_property INTERNAL_VREF 0.675 [get_iobanks 34]
+
+

AngeloJacobo_UberDDR3/example_demo/arty_s7/arty_ddr3_vivado.xdc

@@ -0,0 +1,265 @@
+## This file is a general .xdc for the Arty S7-50 Rev. E
+## To use it in a project:
+## - uncomment the lines corresponding to used pins
+## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
+
+## Clock Signals
+set_property -dict {PACKAGE_PIN R2 IOSTANDARD SSTL135} [get_ports i_clk]
+create_clock -period 10.000 -name sys_clk_pin -waveform {0.000 5.000} -add [get_ports i_clk]
+
+## LEDs
+set_property -dict {PACKAGE_PIN E18 IOSTANDARD LVCMOS33} [get_ports {led[0]}]
+set_property -dict {PACKAGE_PIN F13 IOSTANDARD LVCMOS33} [get_ports {led[1]}]
+set_property -dict {PACKAGE_PIN E13 IOSTANDARD LVCMOS33} [get_ports {led[2]}]
+set_property -dict {PACKAGE_PIN H15 IOSTANDARD LVCMOS33} [get_ports {led[3]}]
+
+## Buttons
+set_property -dict {PACKAGE_PIN G15 IOSTANDARD LVCMOS33} [get_ports i_rst]
+
+## USB-UART Interface
+set_property -dict {PACKAGE_PIN R12 IOSTANDARD LVCMOS33} [get_ports tx]
+set_property -dict {PACKAGE_PIN V12 IOSTANDARD LVCMOS33} [get_ports rx]
+
+
+############## DDR3 ##################
+# DQ PINS
+set_property SLEW FAST [get_ports {ddr3_dq[0]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[0]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[0]}]
+set_property PACKAGE_PIN K2 [get_ports {ddr3_dq[0]}]
+
+set_property SLEW FAST [get_ports {ddr3_dq[1]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[1]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[1]}]
+set_property PACKAGE_PIN K3 [get_ports {ddr3_dq[1]}]
+
+set_property SLEW FAST [get_ports {ddr3_dq[2]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[2]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[2]}]
+set_property PACKAGE_PIN L4 [get_ports {ddr3_dq[2]}]
+
+set_property SLEW FAST [get_ports {ddr3_dq[3]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[3]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[3]}]
+set_property PACKAGE_PIN M6 [get_ports {ddr3_dq[3]}]
+
+set_property SLEW FAST [get_ports {ddr3_dq[4]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[4]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[4]}]
+set_property PACKAGE_PIN K6 [get_ports {ddr3_dq[4]}]
+
+set_property SLEW FAST [get_ports {ddr3_dq[5]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[5]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[5]}]
+set_property PACKAGE_PIN M4 [get_ports {ddr3_dq[5]}]
+
+set_property SLEW FAST [get_ports {ddr3_dq[6]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[6]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[6]}]
+set_property PACKAGE_PIN L5 [get_ports {ddr3_dq[6]}]
+
+set_property SLEW FAST [get_ports {ddr3_dq[7]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[7]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[7]}]
+set_property PACKAGE_PIN L6 [get_ports {ddr3_dq[7]}]
+
+set_property SLEW FAST [get_ports {ddr3_dq[8]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[8]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[8]}]
+set_property PACKAGE_PIN N4 [get_ports {ddr3_dq[8]}]
+
+set_property SLEW FAST [get_ports {ddr3_dq[9]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[9]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[9]}]
+set_property PACKAGE_PIN R1 [get_ports {ddr3_dq[9]}]
+
+set_property SLEW FAST [get_ports {ddr3_dq[10]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[10]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[10]}]
+set_property PACKAGE_PIN N1 [get_ports {ddr3_dq[10]}]
+
+set_property SLEW FAST [get_ports {ddr3_dq[11]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[11]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[11]}]
+set_property PACKAGE_PIN N5 [get_ports {ddr3_dq[11]}]
+
+set_property SLEW FAST [get_ports {ddr3_dq[12]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[12]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[12]}]
+set_property PACKAGE_PIN M2 [get_ports {ddr3_dq[12]}]
+
+set_property SLEW FAST [get_ports {ddr3_dq[13]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[13]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[13]}]
+set_property PACKAGE_PIN P1 [get_ports {ddr3_dq[13]}]
+
+set_property SLEW FAST [get_ports {ddr3_dq[14]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[14]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[14]}]
+set_property PACKAGE_PIN M1 [get_ports {ddr3_dq[14]}]
+
+set_property SLEW FAST [get_ports {ddr3_dq[15]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dq[15]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_dq[15]}]
+set_property PACKAGE_PIN P2 [get_ports {ddr3_dq[15]}]
+
+# Address Pins
+set_property SLEW FAST [get_ports {ddr3_addr[13]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[13]}]
+set_property PACKAGE_PIN U6 [get_ports {ddr3_addr[13]}]
+
+set_property SLEW FAST [get_ports {ddr3_addr[12]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[12]}]
+set_property PACKAGE_PIN R6 [get_ports {ddr3_addr[12]}]
+
+set_property SLEW FAST [get_ports {ddr3_addr[11]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[11]}]
+set_property PACKAGE_PIN T5 [get_ports {ddr3_addr[11]}]
+
+set_property SLEW FAST [get_ports {ddr3_addr[10]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[10]}]
+set_property PACKAGE_PIN P6 [get_ports {ddr3_addr[10]}]
+
+set_property SLEW FAST [get_ports {ddr3_addr[9]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[9]}]
+set_property PACKAGE_PIN V7 [get_ports {ddr3_addr[9]}]
+
+set_property SLEW FAST [get_ports {ddr3_addr[8]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[8]}]
+set_property PACKAGE_PIN U7 [get_ports {ddr3_addr[8]}]
+
+set_property SLEW FAST [get_ports {ddr3_addr[7]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[7]}]
+set_property PACKAGE_PIN T6 [get_ports {ddr3_addr[7]}]
+
+set_property SLEW FAST [get_ports {ddr3_addr[6]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[6]}]
+set_property PACKAGE_PIN V6 [get_ports {ddr3_addr[6]}]
+
+set_property SLEW FAST [get_ports {ddr3_addr[5]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[5]}]
+set_property PACKAGE_PIN R7 [get_ports {ddr3_addr[5]}]
+
+set_property SLEW FAST [get_ports {ddr3_addr[4]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[4]}]
+set_property PACKAGE_PIN T3 [get_ports {ddr3_addr[4]}]
+
+set_property SLEW FAST [get_ports {ddr3_addr[3]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[3]}]
+set_property PACKAGE_PIN V4 [get_ports {ddr3_addr[3]}]
+
+set_property SLEW FAST [get_ports {ddr3_addr[2]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[2]}]
+set_property PACKAGE_PIN V2 [get_ports {ddr3_addr[2]}]
+
+set_property SLEW FAST [get_ports {ddr3_addr[1]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[1]}]
+set_property PACKAGE_PIN R4 [get_ports {ddr3_addr[1]}]
+
+set_property SLEW FAST [get_ports {ddr3_addr[0]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_addr[0]}]
+set_property PACKAGE_PIN U2 [get_ports {ddr3_addr[0]}]
+
+# Bank Pins
+set_property SLEW FAST [get_ports {ddr3_ba[2]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_ba[2]}]
+set_property PACKAGE_PIN U3 [get_ports {ddr3_ba[2]}]
+
+set_property SLEW FAST [get_ports {ddr3_ba[1]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_ba[1]}]
+set_property PACKAGE_PIN T1 [get_ports {ddr3_ba[1]}]
+
+set_property SLEW FAST [get_ports {ddr3_ba[0]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_ba[0]}]
+set_property PACKAGE_PIN V5 [get_ports {ddr3_ba[0]}]
+
+# Command Pins
+set_property SLEW FAST [get_ports ddr3_ras_n]
+set_property IOSTANDARD SSTL135 [get_ports ddr3_ras_n]
+set_property PACKAGE_PIN U1 [get_ports ddr3_ras_n]
+
+set_property SLEW FAST [get_ports ddr3_cas_n]
+set_property IOSTANDARD SSTL135 [get_ports ddr3_cas_n]
+set_property PACKAGE_PIN V3 [get_ports ddr3_cas_n]
+
+set_property SLEW FAST [get_ports ddr3_we_n]
+set_property IOSTANDARD SSTL135 [get_ports ddr3_we_n]
+set_property PACKAGE_PIN P7 [get_ports ddr3_we_n]
+
+set_property SLEW FAST [get_ports ddr3_reset_n]
+set_property IOSTANDARD SSTL135 [get_ports ddr3_reset_n]
+set_property PACKAGE_PIN J6 [get_ports ddr3_reset_n]
+
+set_property SLEW FAST [get_ports ddr3_cke]
+set_property IOSTANDARD SSTL135 [get_ports ddr3_cke]
+set_property PACKAGE_PIN T2 [get_ports ddr3_cke]
+
+
+set_property SLEW FAST [get_ports ddr3_odt]
+set_property IOSTANDARD SSTL135 [get_ports ddr3_odt]
+set_property PACKAGE_PIN P5 [get_ports ddr3_odt]
+
+
+set_property SLEW FAST [get_ports ddr3_cs_n]
+set_property IOSTANDARD SSTL135 [get_ports ddr3_cs_n]
+set_property PACKAGE_PIN R3 [get_ports ddr3_cs_n]
+
+# Data Mask Pins
+set_property SLEW FAST [get_ports {ddr3_dm[0]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_dm[0]}]
+set_property PACKAGE_PIN K4 [get_ports {ddr3_dm[0]}]
+
+set_property SLEW FAST [get_ports {ddr3_dm[1]}]
+set_property IOSTANDARD SSTL135 [get_ports {ddr3_dm[1]}]
+set_property PACKAGE_PIN M3 [get_ports {ddr3_dm[1]}]
+
+# DQS Pins
+set_property SLEW FAST [get_ports {ddr3_dqs_p[0]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dqs_p[0]}]
+set_property IOSTANDARD DIFF_SSTL135 [get_ports {ddr3_dqs_p[0]}]
+
+set_property SLEW FAST [get_ports {ddr3_dqs_n[0]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dqs_n[0]}]
+set_property IOSTANDARD DIFF_SSTL135 [get_ports {ddr3_dqs_n[0]}]
+set_property PACKAGE_PIN K1 [get_ports {ddr3_dqs_p[0]}]
+set_property PACKAGE_PIN L1 [get_ports {ddr3_dqs_n[0]}]
+
+set_property SLEW FAST [get_ports {ddr3_dqs_p[1]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dqs_p[1]}]
+set_property IOSTANDARD DIFF_SSTL135 [get_ports {ddr3_dqs_p[1]}]
+
+set_property SLEW FAST [get_ports {ddr3_dqs_n[1]}]
+set_property IN_TERM UNTUNED_SPLIT_50 [get_ports {ddr3_dqs_n[1]}]
+set_property IOSTANDARD DIFF_SSTL135 [get_ports {ddr3_dqs_n[1]}]
+set_property PACKAGE_PIN N3 [get_ports {ddr3_dqs_p[1]}]
+set_property PACKAGE_PIN N2 [get_ports {ddr3_dqs_n[1]}]
+
+# Clock Pins
+set_property SLEW FAST [get_ports ddr3_clk_p]
+set_property IOSTANDARD DIFF_SSTL135 [get_ports ddr3_clk_p]
+
+set_property SLEW FAST [get_ports ddr3_clk_n]
+set_property IOSTANDARD DIFF_SSTL135 [get_ports ddr3_clk_n]
+set_property PACKAGE_PIN R5 [get_ports ddr3_clk_p]
+set_property PACKAGE_PIN T4 [get_ports ddr3_clk_n]
+
+
+
+
+
+## Configuration options, can be used for all designs
+set_property BITSTREAM.CONFIG.CONFIGRATE 50 [current_design]
+set_property CONFIG_VOLTAGE 3.3 [current_design]
+set_property CFGBVS VCCO [current_design]
+set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
+set_property CONFIG_MODE SPIx4 [current_design]
+
+## SW3 is assigned to a pin M5 in the 1.35v bank. This pin can also be used as
+## the VREF for BANK 34. To ensure that SW3 does not define the reference voltage
+## and to be able to use this pin as an ordinary I/O the following property must
+## be set to enable an internal VREF for BANK 34. Since a 1.35v supply is being
+## used the internal reference is set to half that value (i.e. 0.675v). Note that
+## this property must be set even if SW3 is not used in the design.
+ set_property INTERNAL_VREF 0.675 [get_iobanks 34]
+
+

AngeloJacobo_UberDDR3/example_demo/arty_s7/caas.conf

@@ -0,0 +1,11 @@
+[project]
+Backend = openxc7
+Part = xc7s50csga324-1
+Top = arty_ddr3
+Constraint = arty_ddr3.xdc
+Sources = *.v
+
+[caas]
+Server = https://caas.symbioticeda.com:18888/
+
+

AngeloJacobo_UberDDR3/example_demo/arty_s7/clk_wiz.v

@@ -0,0 +1,66 @@
+`timescale 1ps/1ps
+
+module clk_wiz
+ (
+  input wire         clk_in1,
+  output wire        clk_out1,
+  output wire        clk_out2,
+  output wire        clk_out3,
+  output wire        clk_out4,
+  input wire         reset,
+  output wire        locked
+ );
+  wire        clk_out1_clk_wiz_0;
+  wire        clk_out2_clk_wiz_0;
+  wire        clk_out3_clk_wiz_0;
+  wire        clk_out4_clk_wiz_0;
+
+  wire clkfbout;
+
+  PLLE2_ADV
+  #(.BANDWIDTH            ("OPTIMIZED"),
+    .COMPENSATION         ("INTERNAL"),
+    .STARTUP_WAIT         ("FALSE"),
+    .DIVCLK_DIVIDE        (1),
+    .CLKFBOUT_MULT        (12), // 100 MHz * 12 = 1200 MHz
+    .CLKFBOUT_PHASE       (0.000),
+    .CLKOUT0_DIVIDE       (12), // 1200 MHz / 12 = 100 MHz
+    .CLKOUT0_PHASE        (0.000),
+    .CLKOUT0_DUTY_CYCLE   (0.500),
+    .CLKOUT1_DIVIDE       (3), // 1200 MHz / 3 = 400 MHz
+    .CLKOUT1_PHASE        (0.000),
+    .CLKOUT1_DUTY_CYCLE   (0.500),
+    .CLKOUT2_DIVIDE       (6), // 1200 MHz / 6 = 200 MHz
+    .CLKOUT2_PHASE        (0.000),
+    .CLKOUT2_DUTY_CYCLE   (0.500),
+    .CLKOUT3_DIVIDE       (3), // 1200 MHz / 3 = 400 MHz, 90 phase
+    .CLKOUT3_PHASE        (90.000),
+    .CLKOUT3_DUTY_CYCLE   (0.500),
+    .CLKIN1_PERIOD        (10.000) // 100 MHz input
+  )
+  plle2_adv_inst
+   (
+    .CLKFBOUT            (clkfbout),
+    .CLKOUT0             (clk_out1_clk_wiz_0),
+    .CLKOUT1             (clk_out2_clk_wiz_0),
+    .CLKOUT2             (clk_out3_clk_wiz_0),
+    .CLKOUT3             (clk_out4_clk_wiz_0),
+    .CLKFBIN             (clkfbout),
+	.CLKIN1              (clk_in1),
+    .LOCKED              (locked),
+    .RST                 (reset)
+  );
+  BUFG clkout1_buf
+   (.O   (clk_out1),
+    .I   (clk_out1_clk_wiz_0));
+  BUFG clkout2_buf
+   (.O   (clk_out2),
+    .I   (clk_out2_clk_wiz_0));
+  BUFG clkout3_buf
+   (.O   (clk_out3),
+    .I   (clk_out3_clk_wiz_0));
+  BUFG clkout4_buf
+   (.O   (clk_out4),
+    .I   (clk_out4_clk_wiz_0));
+
+endmodule

AngeloJacobo_UberDDR3/example_demo/arty_s7/ddr3_phy.v

@@ -0,0 +1,1462 @@
+////////////////////////////////////////////////////////////////////////////////
+//
+// Filename: ddr3_phy.v
+// Project: UberDDR3 - An Open Source DDR3 Controller
+//
+// Purpose: PHY component for the DDR3 controller. Handles the primitives such
+// as IOSERDES, IODELAY, and IOBUF. These generates the signals connected to 
+// the DDR3 RAM.
+//
+// Engineer: Angelo C. Jacobo
+//
+////////////////////////////////////////////////////////////////////////////////
+//
+// Copyright (C) 2023-2025  Angelo Jacobo
+// 
+//     This program is free software: you can redistribute it and/or modify
+//     it under the terms of the GNU General Public License as published by
+//     the Free Software Foundation, either version 3 of the License, or
+//     (at your option) any later version.
+// 
+//     This program is distributed in the hope that it will be useful,
+//     but WITHOUT ANY WARRANTY; without even the implied warranty of
+//     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//     GNU General Public License for more details.
+// 
+//     You should have received a copy of the GNU General Public License
+//     along with this program.  If not, see <https://www.gnu.org/licenses/>.
+//
+////////////////////////////////////////////////////////////////////////////////
+
+`default_nettype none
+`timescale 1ps / 1ps
+//`define DEBUG_DQS // uncomment to route the raw DQS to output port for debugging
+
+module ddr3_phy #(
+    parameter     CONTROLLER_CLK_PERIOD = 10_000, //ps, clock period of the controller interface
+                  DDR3_CLK_PERIOD = 2_500, //ps, clock period of the DDR3 RAM device (must be 1/4 of the CONTROLLER_CLK_PERIOD) 
+                  ROW_BITS = 14,   //width of row address
+                  BA_BITS = 3,
+                  DQ_BITS = 8,
+                  LANES = 8,
+                  DUAL_RANK_DIMM = 0, // enable dual rank DIMM (1 =  enable, 0 = disable)
+    parameter[0:0] ODELAY_SUPPORTED = 1, //set to 1 when ODELAYE2 is supported
+                   USE_IO_TERMINATION = 0, //use IOBUF_DCIEN and IOBUFDS_DCIEN when 1
+                   NO_IOSERDES_LOOPBACK = 1, // don't use IOSERDES loopback for bitslip training
+              // The next parameters act more like a localparam (since user does not have to set this manually) but was added here to simplify port declaration
+    parameter serdes_ratio = 4, // this controller is fixed as a 4:1 memory controller (CONTROLLER_CLK_PERIOD/DDR3_CLK_PERIOD = 4)
+              wb_data_bits = DQ_BITS*LANES*serdes_ratio*2,
+              wb_sel_bits = wb_data_bits / 8,
+              //4 is the width of a single ddr3 command {cs_n, ras_n, cas_n, we_n} plus 3 (ck_en, odt, reset_n) plus bank bits plus row bits
+              cmd_len = 4 + 3 + BA_BITS + ROW_BITS + 2*DUAL_RANK_DIMM
+    )(
+        input wire i_controller_clk, i_ddr3_clk, i_ref_clk,
+        input wire i_ddr3_clk_90, //required only when ODELAY_SUPPORTED is zero
+        input wire i_rst_n,
+        // Controller Interface
+        input wire i_controller_reset,
+        input wire[cmd_len*serdes_ratio-1:0] i_controller_cmd,
+        input wire i_controller_dqs_tri_control, i_controller_dq_tri_control,
+        input wire i_controller_toggle_dqs,
+        input wire[wb_data_bits-1:0] i_controller_data,
+        input wire[wb_sel_bits-1:0] i_controller_dm,
+        input wire[4:0] i_controller_odelay_data_cntvaluein,i_controller_odelay_dqs_cntvaluein,
+        input wire[4:0] i_controller_idelay_data_cntvaluein,i_controller_idelay_dqs_cntvaluein,
+        input wire[LANES-1:0] i_controller_odelay_data_ld, i_controller_odelay_dqs_ld,
+        input wire[LANES-1:0] i_controller_idelay_data_ld, i_controller_idelay_dqs_ld,
+        input wire[LANES-1:0] i_controller_bitslip,
+        input wire i_controller_write_leveling_calib,
+        output wire[DQ_BITS*LANES*8-1:0] o_controller_iserdes_data,
+        output wire[LANES*8-1:0] o_controller_iserdes_dqs,
+        output wire[LANES*8-1:0] o_controller_iserdes_bitslip_reference,
+        output wire o_controller_idelayctrl_rdy,
+        // DDR3 I/O Interface
+        output wire[DUAL_RANK_DIMM:0] o_ddr3_clk_p,o_ddr3_clk_n,
+        output wire o_ddr3_reset_n,
+        output wire[DUAL_RANK_DIMM:0] o_ddr3_cke, // CKE
+        output wire[DUAL_RANK_DIMM:0] o_ddr3_cs_n, // chip select signal
+        output wire o_ddr3_ras_n, // RAS#
+        output wire o_ddr3_cas_n, // CAS#
+        output wire o_ddr3_we_n, // WE#
+        output wire[ROW_BITS-1:0] o_ddr3_addr,
+        output wire[BA_BITS-1:0] o_ddr3_ba_addr,
+        inout wire[(DQ_BITS*LANES)-1:0] io_ddr3_dq,
+        inout wire[(DQ_BITS*LANES)/8-1:0] io_ddr3_dqs, io_ddr3_dqs_n,
+        output wire[LANES-1:0] o_ddr3_dm,
+        output wire[DUAL_RANK_DIMM:0] o_ddr3_odt, // on-die termination
+        // DEBUG PHY
+        output wire[(DQ_BITS*LANES)/8-1:0] o_ddr3_debug_read_dqs_p,
+        output wire[(DQ_BITS*LANES)/8-1:0] o_ddr3_debug_read_dqs_n
+    );
+
+    // cmd bit assignment
+    localparam CMD_CS_N_2 = cmd_len - 1,
+                CMD_CS_N =  DUAL_RANK_DIMM[0]? cmd_len - 2 : cmd_len - 1,
+                CMD_RAS_N = DUAL_RANK_DIMM[0]? cmd_len - 3 : cmd_len - 2,
+                CMD_CAS_N = DUAL_RANK_DIMM[0]? cmd_len - 4 : cmd_len - 3,
+                CMD_WE_N =  DUAL_RANK_DIMM[0]? cmd_len - 5 : cmd_len - 4,
+                CMD_ODT =   DUAL_RANK_DIMM[0]? cmd_len - 6 : cmd_len - 5,
+                CMD_CKE_2 = DUAL_RANK_DIMM[0]? cmd_len - 7 : cmd_len - 6,
+                CMD_CKE =   DUAL_RANK_DIMM[0]? cmd_len - 8 : cmd_len - 6,
+                CMD_RESET_N = DUAL_RANK_DIMM[0]? cmd_len - 9 : cmd_len - 7,
+                CMD_BANK_START = BA_BITS + ROW_BITS - 1,
+                CMD_ADDRESS_START = ROW_BITS - 1;
+    localparam SYNC_RESET_DELAY = $rtoi($ceil(52_000/CONTROLLER_CLK_PERIOD)); //52_000 ps of reset pulse width required for IDELAYCTRL 
+    //cmd needs to be center-aligned to the positive edge of the 
+    //ddr3_clk. This means cmd needs to be delayed by half the ddr3
+    //clk period. Subtract by 600ps to include the IODELAY insertion
+    //delay. Divide by a delay resolution of 78.125ps per tap to get 
+    //the needed tap value.
+    localparam CMD_ODELAY_TAP = ((DDR3_CLK_PERIOD/2) - 600)/78.125;
+
+    // Data does not have to be delayed (DQS is the on that has to be
+    // delayed and center-aligned to the center eye of data)
+    localparam DATA_ODELAY_TAP = 0; 
+
+    //DQS needs to be edge-aligned to the center eye of the data. 
+    //This means DQS needs to be delayed by a quarter of the ddr3
+    //clk period relative to the data. Subtract by 600ps to include
+    //the IODELAY insertion delay. Divide by a delay resolution of 
+    //78.125ps per tap to get the needed tap value. Then add the tap
+    //value used in data to have the delay relative to the data.
+    localparam DQS_ODELAY_TAP = ((DDR3_CLK_PERIOD/4))/78.125 + DATA_ODELAY_TAP;
+    
+    //Incoming DQS should be 90 degree delayed relative to incoming data
+    localparam DATA_IDELAY_TAP = 0; //600ps delay
+    localparam DQS_IDELAY_TAP = ((DDR3_CLK_PERIOD/4))/78.125 + DATA_IDELAY_TAP;
+    
+    genvar gen_index;
+    wire[cmd_len-1:0] oserdes_cmd, //serialized(4:1) i_controller_cmd_slot_x 
+                      cmd;//delayed oserdes_cmd
+    wire[(DQ_BITS*LANES)-1:0] oserdes_data, odelay_data, idelay_data, read_dq;
+    wire[LANES-1:0] oserdes_dm, odelay_dm;
+    wire[LANES-1:0] odelay_dqs, read_dqs, idelay_dqs;
+    wire[DQ_BITS*LANES-1:0] oserdes_dq_tri_control;
+    wire[LANES-1:0] oserdes_dqs;
+    wire[LANES-1:0] oserdes_dqs_tri_control;
+    wire[LANES-1:0] oserdes_bitslip_reference;
+    reg[$clog2(SYNC_RESET_DELAY):0] delay_before_release_reset;
+    reg sync_rst = 0;
+    wire ddr3_clk;
+    reg toggle_dqs_q; //past value of i_controller_toggle_dqs
+    wire ddr3_clk_delayed;
+    wire idelayctrl_rdy;
+    wire dci_locked;
+    reg[LANES*8-1:0] o_controller_iserdes_bitslip_reference_reg;
+    reg[LANES - 1 : 0] shift_bitslip_index;
+    
+    // initial value of bitslip reference
+    initial begin
+        o_controller_iserdes_bitslip_reference_reg = {LANES{8'b0001_1110}};
+        shift_bitslip_index = 0;
+    end
+                
+    assign o_controller_idelayctrl_rdy = idelayctrl_rdy && dci_locked;
+    
+`ifdef DEBUG_DQS
+    assign o_ddr3_debug_read_dqs_p = io_ddr3_dqs;
+    assign o_ddr3_debug_read_dqs_n = io_ddr3_dqs_n;
+`else
+    assign o_ddr3_debug_read_dqs_p = 0;
+    assign o_ddr3_debug_read_dqs_n = 0;
+`endif
+
+    //synchronous reset
+    always @(posedge i_controller_clk) begin
+        if(!i_rst_n || i_controller_reset) begin
+            sync_rst <= 1'b1;
+            delay_before_release_reset <= SYNC_RESET_DELAY[$clog2(SYNC_RESET_DELAY):0];
+            toggle_dqs_q <= 0;
+        end
+        else begin
+            delay_before_release_reset <= (delay_before_release_reset == 0)? 0: delay_before_release_reset - 1;
+            sync_rst <= !(delay_before_release_reset == 0);
+            toggle_dqs_q <= i_controller_toggle_dqs;
+        end
+    end
+
+    //PHY cmd 
+    generate
+        for(gen_index = 0; gen_index < cmd_len; gen_index = gen_index + 1) begin
+            // OSERDESE2: Output SERial/DESerializer with bitslip
+            //7 Series
+            // Xilinx HDL Libraries Guide, version 13.4
+            `ifndef SIM_MODEL
+                OSERDESE2 #(
+            `else 
+                OSERDESE2_model #(
+            `endif
+                .DATA_RATE_OQ("SDR"), // DDR, SDR
+                .DATA_RATE_TQ("SDR"), // DDR, SDR
+                .DATA_WIDTH(4), // Parallel data width (2-8,10,14)
+                .INIT_OQ(1'b0), // Initial value of OQ output (1'b0,1'b1)
+                .TRISTATE_WIDTH(1)
+            )
+            OSERDESE2_cmd(
+                .OFB(), // 1-bit output: Feedback path for data
+                .OQ(oserdes_cmd[gen_index]), // 1-bit output: Data path output
+                .CLK(i_ddr3_clk), // 1-bit input: High speed clock
+                .CLKDIV(i_controller_clk), // 1-bit input: Divided clock
+                // D1 - D8: 1-bit (each) input: Parallel data inputs (1-bit each)
+                .D1(i_controller_cmd[cmd_len*0 + gen_index]),
+                .D2(i_controller_cmd[cmd_len*1 + gen_index]),
+                .D3(i_controller_cmd[cmd_len*2 + gen_index]),
+                .D4(i_controller_cmd[cmd_len*3 + gen_index]),
+                .OCE(1'b1), // 1-bit input: Output data clock enable
+                .RST(sync_rst), // 1-bit input: Reset
+                // unused signals but were added here to make vivado happy
+                .SHIFTOUT1(), // SHIFTOUT1 / SHIFTOUT2: 1-bit (each) output: Data output expansion (1-bit each)
+                .SHIFTOUT2(),
+                .TBYTEOUT(), // 1-bit output: Byte group tristate
+                .TFB(), // 1-bit output: 3-state control
+                .TQ(), // 1-bit output: 3-state control
+                .D5(),
+                .D6(),
+                .D7(),
+                .D8(),
+                // SHIFTIN1 / SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each)
+                .SHIFTIN1(0),
+                .SHIFTIN2(0),
+                // T1 - T4: 1-bit (each) input: Parallel 3-state inputs
+                .T1(0),
+                .T2(0),
+                .T3(0),
+                .T4(0),
+                .TBYTEIN(0),
+                // 1-bit input: Byte group tristate
+                .TCE(0)
+                // 1-bit input: 3-state clock enable
+            );
+            // End of OSERDESE2_inst instantiation
+      
+        end
+
+        if(DUAL_RANK_DIMM) begin // if dual rank enabled, odt_2 and odt_1 will be generated separately
+            // OSERDESE2: Output SERial/DESerializer with bitslip
+            //7 Series
+            // Xilinx HDL Libraries Guide, version 13.4
+            `ifndef SIM_MODEL
+                OSERDESE2 #(
+            `else 
+                OSERDESE2_model #(
+            `endif
+                .DATA_RATE_OQ("SDR"), // DDR, SDR
+                .DATA_RATE_TQ("SDR"), // DDR, SDR
+                .DATA_WIDTH(4), // Parallel data width (2-8,10,14)
+                .INIT_OQ(1'b0), // Initial value of OQ output (1'b0,1'b1)
+                .TRISTATE_WIDTH(1)
+            )
+            OSERDESE2_cmd(
+                .OFB(), // 1-bit output: Feedback path for data
+                .OQ(o_ddr3_odt[1]), // 1-bit output: Data path output
+                .CLK(i_ddr3_clk), // 1-bit input: High speed clock
+                .CLKDIV(i_controller_clk), // 1-bit input: Divided clock
+                // D1 - D8: 1-bit (each) input: Parallel data inputs (1-bit each)
+                .D1(i_controller_cmd[cmd_len*0 + CMD_ODT]),
+                .D2(i_controller_cmd[cmd_len*1 + CMD_ODT]),
+                .D3(i_controller_cmd[cmd_len*2 + CMD_ODT]),
+                .D4(i_controller_cmd[cmd_len*3 + CMD_ODT]),
+                .OCE(1'b1), // 1-bit input: Output data clock enable
+                .RST(sync_rst), // 1-bit input: Reset
+                // unused signals but were added here to make vivado happy
+                .SHIFTOUT1(), // SHIFTOUT1 / SHIFTOUT2: 1-bit (each) output: Data output expansion (1-bit each)
+                .SHIFTOUT2(),
+                .TBYTEOUT(), // 1-bit output: Byte group tristate
+                .TFB(), // 1-bit output: 3-state control
+                .TQ(), // 1-bit output: 3-state control
+                .D5(),
+                .D6(),
+                .D7(),
+                .D8(),
+                // SHIFTIN1 / SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each)
+                .SHIFTIN1(0),
+                .SHIFTIN2(0),
+                // T1 - T4: 1-bit (each) input: Parallel 3-state inputs
+                .T1(0),
+                .T2(0),
+                .T3(0),
+                .T4(0),
+                .TBYTEIN(0),
+                // 1-bit input: Byte group tristate
+                .TCE(0)
+                // 1-bit input: 3-state clock enable
+            );
+            // End of OSERDESE2_inst instantiation
+        end
+    endgenerate 
+
+    // cs[1] when DUAL_RANK_DIMM enabled
+    generate    
+        if(DUAL_RANK_DIMM) begin
+            assign o_ddr3_cs_n[1] = oserdes_cmd[CMD_CS_N_2];
+            assign o_ddr3_cs_n[0] = oserdes_cmd[CMD_CS_N];
+            assign o_ddr3_cke[1] = oserdes_cmd[CMD_CKE_2];
+            assign o_ddr3_cke[0] = oserdes_cmd[CMD_CKE];
+            assign o_ddr3_odt[0] = oserdes_cmd[CMD_ODT];
+            // o_ddr3_odt[1] will be generated directly by a separate OSERDES
+            // if odt[1] and odt[0] uses same output from oserdes, one of them will be unroutable
+        end
+        else begin
+            assign o_ddr3_cs_n = oserdes_cmd[CMD_CS_N];
+            assign o_ddr3_cke = oserdes_cmd[CMD_CKE];
+            assign o_ddr3_odt = oserdes_cmd[CMD_ODT];
+        end
+    endgenerate
+    assign o_ddr3_ras_n = oserdes_cmd[CMD_RAS_N],
+           o_ddr3_cas_n = oserdes_cmd[CMD_CAS_N],
+           o_ddr3_we_n = oserdes_cmd[CMD_WE_N],
+           o_ddr3_reset_n = oserdes_cmd[CMD_RESET_N],
+           o_ddr3_ba_addr = oserdes_cmd[CMD_BANK_START:CMD_ADDRESS_START+1],
+           o_ddr3_addr = oserdes_cmd[CMD_ADDRESS_START:0];
+    
+    if(ODELAY_SUPPORTED) begin
+        // OSERDESE2: Output SERial/DESerializer with bitslip
+        //7 Series
+        // Xilinx HDL Libraries Guide, version 13.4
+        `ifndef SIM_MODEL
+            OSERDESE2 #(
+        `else 
+            OSERDESE2_model #(
+        `endif
+            .DATA_RATE_OQ("DDR"), // DDR, SDR
+            .DATA_RATE_TQ("SDR"), // DDR, SDR
+            .DATA_WIDTH(8), // Parallel data width (2-8,10,14)
+            .INIT_OQ(1'b0), // Initial value of OQ output (1'b0,1'b1)
+            .TRISTATE_WIDTH(1)
+        )
+        OSERDESE2_clk(
+            .OFB(ddr3_clk), // 1-bit output: Feedback path for data
+            .OQ(), // 1-bit output: Data path output
+            .CLK(i_ddr3_clk), // 1-bit input: High speed clock
+            .CLKDIV(i_controller_clk), // 1-bit input: Divided clock
+            // D1 - D8: 1-bit (each) input: Parallel data inputs (1-bit each)
+            .D1(1'b1),
+            .D2(1'b0),
+            .D3(1'b1),
+            .D4(1'b0),
+            .D5(1'b1),
+            .D6(1'b0),
+            .D7(1'b1),
+            .D8(1'b0),
+            .OCE(1'b1), // 1-bit input: Output data clock enable
+            .RST(sync_rst), // 1-bit input: Reset
+             // unused signals but were added here to make vivado happy
+            .SHIFTOUT1(), // SHIFTOUT1 / SHIFTOUT2: 1-bit (each) output: Data output expansion (1-bit each)
+            .SHIFTOUT2(),
+            .TBYTEOUT(), // 1-bit output: Byte group tristate
+            .TFB(), // 1-bit output: 3-state control
+            .TQ(), // 1-bit output: 3-state control
+            // SHIFTIN1 / SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each)
+            .SHIFTIN1(0),
+            .SHIFTIN2(0),
+            // T1 - T4: 1-bit (each) input: Parallel 3-state inputs
+            .T1(0),
+            .T2(0),
+            .T3(0),
+            .T4(0),
+            .TBYTEIN(0),
+            // 1-bit input: Byte group tristate
+            .TCE(0)
+            // 1-bit input: 3-state clock enable
+        );
+        // End of OSERDESE2_inst instantiation
+
+            //Delay the DQ
+            // Delay resolution: 1/(32 x 2 x F REF ) = 78.125ps
+            (* IODELAY_GROUP="DDR3-GROUP" *)
+            `ifndef SIM_MODEL
+                ODELAYE2 #(
+            `else 
+                ODELAYE2_model #(
+            `endif
+                .DELAY_SRC("ODATAIN"), // Delay input (ODATAIN, CLKIN)
+                .HIGH_PERFORMANCE_MODE("TRUE"), // Reduced jitter to 5ps ("TRUE"), Reduced power but high jitter 9ns ("FALSE")
+                .ODELAY_TYPE("FIXED"), // FIXED, VARIABLE, VAR_LOAD, VAR_LOAD_PIPE
+                .ODELAY_VALUE(CMD_ODELAY_TAP), // Output delay tap setting (0-31)
+                .REFCLK_FREQUENCY(200.0), // IDELAYCTRL clock input frequency in MHz (190.0-210.0).
+                .SIGNAL_PATTERN("DATA") // DATA, CLOCK input signal
+            )
+            ODELAYE2_clk (
+                .CNTVALUEOUT(), // 5-bit output: Counter value output
+                .DATAOUT(ddr3_clk_delayed), // 1-bit output: Delayed data/clock output
+                .C(i_controller_clk), // 1-bit input: Clock input, when using OSERDESE2, C is connected to CLKDIV
+                .CE(1'b0), // 1-bit input: Active high enable increment/decrement input
+                .CINVCTRL(1'b0), // 1-bit input: Dynamic clock inversion input
+                .CLKIN(1'b0), // 1-bit input: Clock delay input
+                .CNTVALUEIN(5'd0), // 5-bit input: Counter value input
+                .INC(1'b0), // 1-bit input: Increment / Decrement tap delay input
+                .LD(1'b0), // 1-bit input: Loads ODELAY_VALUE tap delay in VARIABLE mode, in VAR_LOAD or
+                            // VAR_LOAD_PIPE mode, loads the value of CNTVALUEIN
+                .LDPIPEEN(1'b0), // 1-bit input: Enables the pipeline register to load data
+                .ODATAIN(ddr3_clk), // 1-bit input: Output delay data input
+                .REGRST(1'b0) // 1-bit input: Active-high reset tap-delay input
+            );
+        // if dual rank enabled, then there will be two clk
+        if(DUAL_RANK_DIMM) begin
+            // OBUFDS: Differential Output Buffer
+            // 7 Series
+            // Xilinx HDL Libraries Guide, version 13.4
+            `ifndef SIM_MODEL
+                OBUFDS OBUFDS0_inst (
+            `else 
+                OBUFDS_model OBUFDS0_inst (
+            `endif
+                .O(o_ddr3_clk_p[0]), // Diff_p output (connect directly to top-level port)
+                .OB(o_ddr3_clk_n[0]), // Diff_n output (connect directly to top-level port)
+                .I(ddr3_clk_delayed) // Buffer input
+            );
+            `ifndef SIM_MODEL
+                OBUFDS OBUFDS1_inst (
+            `else 
+                OBUFDS_model OBUFDS1_inst (
+            `endif
+                .O(o_ddr3_clk_p[1]), // Diff_p output (connect directly to top-level port)
+                .OB(o_ddr3_clk_n[1]), // Diff_n output (connect directly to top-level port)
+                .I(ddr3_clk_delayed) // Buffer input
+            );
+            // End of OBUFDS_inst instantiation
+        end
+        else begin
+            // OBUFDS: Differential Output Buffer
+            // 7 Series
+            // Xilinx HDL Libraries Guide, version 13.4
+            `ifndef SIM_MODEL
+                OBUFDS OBUFDS_inst (
+            `else 
+                OBUFDS_model OBUFDS_inst (
+            `endif
+                .O(o_ddr3_clk_p), // Diff_p output (connect directly to top-level port)
+                .OB(o_ddr3_clk_n), // Diff_n output (connect directly to top-level port)
+                .I(ddr3_clk_delayed) // Buffer input
+            );
+            // End of OBUFDS_inst instantiation
+        end
+    end
+    else begin //ODELAY is not supported
+
+                // if dual rank enabled, then there will be two clk
+        if(DUAL_RANK_DIMM) begin
+            // OBUFDS: Differential Output Buffer
+            // 7 Series
+            // Xilinx HDL Libraries Guide, version 13.4
+            `ifndef SIM_MODEL
+                OBUFDS OBUFDS0_inst (
+            `else 
+                OBUFDS_model OBUFDS0_inst (
+            `endif
+                .O(o_ddr3_clk_p[1]), // Diff_p output (connect directly to top-level port)
+                .OB(o_ddr3_clk_n[1]), // Diff_n output (connect directly to top-level port)
+                .I(!i_ddr3_clk) // Buffer input
+            );
+            `ifndef SIM_MODEL
+                OBUFDS OBUFDS1_inst (
+            `else 
+                OBUFDS_model OBUFDS1_inst (
+            `endif
+                .O(o_ddr3_clk_p[0]), // Diff_p output (connect directly to top-level port)
+                .OB(o_ddr3_clk_n[0]), // Diff_n output (connect directly to top-level port)
+                .I(!i_ddr3_clk) // Buffer input
+            );
+            // End of OBUFDS_inst instantiation
+        end
+        else begin
+            // OBUFDS: Differential Output Buffer
+            // 7 Series
+            // Xilinx HDL Libraries Guide, version 13.4
+            `ifndef SIM_MODEL
+                OBUFDS OBUFDS_inst (
+            `else 
+                OBUFDS_model OBUFDS_inst (
+            `endif
+                .O(o_ddr3_clk_p), // Diff_p output (connect directly to top-level port)
+                .OB(o_ddr3_clk_n), // Diff_n output (connect directly to top-level port)
+                .I(!i_ddr3_clk) // Buffer input
+            );
+        end
+    end
+    
+    
+    // PHY data and dm
+    generate
+        // data: oserdes -> odelay -> iobuf
+        for(gen_index = 0; gen_index < (DQ_BITS*LANES); gen_index = gen_index + 1) begin
+            
+            if (ODELAY_SUPPORTED) begin
+                // OSERDESE2: Output SERial/DESerializer with bitslip
+                //7 Series
+                // Xilinx HDL Libraries Guide, version 13.4
+                `ifndef SIM_MODEL
+                    OSERDESE2 #(
+                `else 
+                    OSERDESE2_model #(
+                `endif
+                    .DATA_RATE_OQ("DDR"), // DDR, SDR
+                    .DATA_RATE_TQ("BUF"), // DDR, SDR
+                    .DATA_WIDTH(8), // Parallel data width (2-8,10,14)
+                    .INIT_OQ(1'b0), // Initial value of OQ output (1'b0,1'b1)
+                    .TRISTATE_WIDTH(1)
+                )
+                OSERDESE2_data(
+                    .OFB(oserdes_data[gen_index]), // 1-bit output: Feedback path for data
+                    .OQ(), // 1-bit output: Data path output
+                    .TQ(oserdes_dq_tri_control[gen_index]),
+                    .CLK(i_ddr3_clk), // 1-bit input: High speed clock
+                    .CLKDIV(i_controller_clk), // 1-bit input: Divided clock
+                    // D1 - D8: 1-bit (each) input: Parallel data inputs (1-bit each)
+                    .D1(i_controller_data[gen_index + (DQ_BITS*LANES)*0]),
+                    .D2(i_controller_data[gen_index + (DQ_BITS*LANES)*1]),
+                    .D3(i_controller_data[gen_index + (DQ_BITS*LANES)*2]),
+                    .D4(i_controller_data[gen_index + (DQ_BITS*LANES)*3]),
+                    .D5(i_controller_data[gen_index + (DQ_BITS*LANES)*4]),
+                    .D6(i_controller_data[gen_index + (DQ_BITS*LANES)*5]),
+                    .D7(i_controller_data[gen_index + (DQ_BITS*LANES)*6]),
+                    .D8(i_controller_data[gen_index + (DQ_BITS*LANES)*7]),
+                    .T1(i_controller_dq_tri_control),
+                    .TCE(1'b1),
+                    .OCE(1'b1), // 1-bit input: Output data clock enable
+                    .RST(sync_rst), // 1-bit input: Reset
+                    // unused signals but were added here to make vivado happy
+                    .SHIFTOUT1(), // SHIFTOUT1 / SHIFTOUT2: 1-bit (each) output: Data output expansion (1-bit each)
+                    .SHIFTOUT2(),
+                    .TBYTEOUT(), // 1-bit output: Byte group tristate
+                    .TFB(), // 1-bit output: 3-state control
+                    // SHIFTIN1 / SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each)
+                    .SHIFTIN1(0),
+                    .SHIFTIN2(0),
+                    // T1 - T4: 1-bit (each) input: Parallel 3-state inputs
+                    .T2(0),
+                    .T3(0),
+                    .T4(0),
+                    .TBYTEIN(0)
+                    // 1-bit input: Byte group tristate
+                );
+                // End of OSERDESE2_inst instantiation
+            
+                // ODELAYE2: Output Fixed or Variable Delay Element
+                // 7 Series
+                // Xilinx HDL Libraries Guide, version 13.4
+                //odelay adds an insertion delay of 600ps to the actual delay setting: https://support.xilinx.com/s/article/42133?language=en_US
+                //Delay the DQ
+                // Delay resolution: 1/(32 x 2 x F REF ) = 78.125ps
+                (* IODELAY_GROUP="DDR3-GROUP" *)
+                `ifndef SIM_MODEL
+                    ODELAYE2 #(
+                `else 
+                    ODELAYE2_model #(
+                `endif
+                    .DELAY_SRC("ODATAIN"), // Delay input (ODATAIN, CLKIN)
+                    .HIGH_PERFORMANCE_MODE("TRUE"), // Reduced jitter to 5ps ("TRUE"), Reduced power but high jitter 9ns ("FALSE")
+                    .ODELAY_TYPE("VAR_LOAD"), // FIXED, VARIABLE, VAR_LOAD, VAR_LOAD_PIPE
+                    .ODELAY_VALUE(DATA_ODELAY_TAP), // Output delay tap setting (0-31)
+                    .REFCLK_FREQUENCY(200.0), // IDELAYCTRL clock input frequency in MHz (190.0-210.0).
+                    .SIGNAL_PATTERN("DATA") // DATA, CLOCK input signal
+                )
+                ODELAYE2_data (
+                    .CNTVALUEOUT(), // 5-bit output: Counter value output
+                    .DATAOUT(odelay_data[gen_index]), // 1-bit output: Delayed data/clock output
+                    .C(i_controller_clk), // 1-bit input: Clock input, when using OSERDESE2, C is connected to CLKDIV
+                    .CE(1'b0), // 1-bit input: Active high enable increment/decrement input
+                    .CINVCTRL(1'b0), // 1-bit input: Dynamic clock inversion input
+                    .CLKIN(1'b0), // 1-bit input: Clock delay input
+                    .CNTVALUEIN(i_controller_odelay_data_cntvaluein), // 5-bit input: Counter value input
+                    .INC(1'b0), // 1-bit input: Increment / Decrement tap delay input
+                    .LD(i_controller_odelay_data_ld[gen_index/8]), // 1-bit input: Loads ODELAY_VALUE tap delay in VARIABLE mode, in VAR_LOAD or
+                                // VAR_LOAD_PIPE mode, loads the value of CNTVALUEIN
+                    .LDPIPEEN(1'b0), // 1-bit input: Enables the pipeline register to load data
+                    .ODATAIN(oserdes_data[gen_index]), // 1-bit input: Output delay data input
+                    .REGRST(1'b0) // 1-bit input: Active-high reset tap-delay input
+                );
+
+                if(USE_IO_TERMINATION) begin 
+                    // IOBUF_DCIEN: Single-ended Bi-directional Buffer with Digital Controlled Impedance (DCI)
+                    // and Input path enable/disable
+                    // May only be placed in High Performance (HP) Banks
+                    // 7 Series
+                    // Xilinx HDL Libraries Guide, version 13.4
+                    `ifndef SIM_MODEL
+                        IOBUF_DCIEN #(
+                    `else 
+                        IOBUF_DCIEN_model #(
+                    `endif
+                    .IBUF_LOW_PWR("FALSE"), // Low Power - "TRUE", High Performance = "FALSE"
+                    .SLEW("FAST"), // Specify the output slew rate
+                    .USE_IBUFDISABLE("FALSE") // Use IBUFDISABLE function, "TRUE" or "FALSE"
+                    ) IOBUF_DCIEN_data (
+                        .O(read_dq[gen_index]), // Buffer output
+                        .IO(io_ddr3_dq[gen_index]), // Buffer inout port (connect directly to top-level port)
+                        .DCITERMDISABLE(1'b0), // DCI Termination enable input
+                        .I(odelay_data[gen_index]), // Buffer input
+                        .IBUFDISABLE(1'b0), // Input disable input, low=disable
+                        .T(oserdes_dq_tri_control[gen_index]) // 3-state enable input, high=input, low=output
+                    );
+                    // End of IOBUF_DCIEN_inst instantiation
+
+                 end
+                 else begin                         
+                    // IOBUF: Single-ended Bi-directional Buffer
+                    //All devices
+                    // Xilinx HDL Libraries Guide, version 13.4
+                    `ifndef SIM_MODEL
+                        IOBUF #(
+                    `else 
+                        IOBUF_model #(
+                    `endif
+                        //.DRIVE(12), // Specify the output drive strength
+                        .IBUF_LOW_PWR("FALSE"), // Low Power - "TRUE", High Performance = "FALSE"
+                        //.IOSTANDARD("SSTL15"), // Specify the I/O standard
+                        .SLEW("FAST") // Specify the output slew rate
+                    ) IOBUF_data (
+                        .O(read_dq[gen_index]),// Buffer output
+                        .IO(io_ddr3_dq[gen_index]), // Buffer inout port (connect directly to top-level port)
+                        .I(odelay_data[gen_index]), // Buffer input
+                        .T(oserdes_dq_tri_control[gen_index]) // 3-state enable input, high=read, low=write
+                    );
+                 end
+            end
+            else begin //ODELAY is not supported
+                // OSERDESE2: Output SERial/DESerializer with bitslip
+                //7 Series
+                // Xilinx HDL Libraries Guide, version 13.4
+                `ifndef SIM_MODEL
+                    OSERDESE2 #(
+                `else 
+                    OSERDESE2_model #(
+                `endif
+                    .DATA_RATE_OQ("DDR"), // DDR, SDR
+                    .DATA_RATE_TQ("BUF"), // DDR, SDR
+                    .DATA_WIDTH(8), // Parallel data width (2-8,10,14)
+                    .INIT_OQ(1'b0), // Initial value of OQ output (1'b0,1'b1)
+                    .TRISTATE_WIDTH(1)
+                )
+                OSERDESE2_data(
+                    .OFB(), // 1-bit output: Feedback path for data
+                    .OQ(oserdes_data[gen_index]), // 1-bit output: Data path output
+                    .TQ(oserdes_dq_tri_control[gen_index]),
+                    .CLK(i_ddr3_clk_90), // 1-bit input: High speed clock
+                    .CLKDIV(i_controller_clk), // 1-bit input: Divided clock
+                    // D1 - D8: 1-bit (each) input: Parallel data inputs (1-bit each)
+                    .D1(i_controller_data[gen_index + (DQ_BITS*LANES)*0]),
+                    .D2(i_controller_data[gen_index + (DQ_BITS*LANES)*1]),
+                    .D3(i_controller_data[gen_index + (DQ_BITS*LANES)*2]),
+                    .D4(i_controller_data[gen_index + (DQ_BITS*LANES)*3]),
+                    .D5(i_controller_data[gen_index + (DQ_BITS*LANES)*4]),
+                    .D6(i_controller_data[gen_index + (DQ_BITS*LANES)*5]),
+                    .D7(i_controller_data[gen_index + (DQ_BITS*LANES)*6]),
+                    .D8(i_controller_data[gen_index + (DQ_BITS*LANES)*7]),
+                    .T1(i_controller_dq_tri_control),
+                    .TCE(1'b1),
+                    .OCE(1'b1), // 1-bit input: Output data clock enable
+                    .RST(sync_rst), // 1-bit input: Reset
+                    // unused signals but were added here to make vivado happy
+                    .SHIFTOUT1(), // SHIFTOUT1 / SHIFTOUT2: 1-bit (each) output: Data output expansion (1-bit each)
+                    .SHIFTOUT2(),
+                    .TBYTEOUT(), // 1-bit output: Byte group tristate
+                    .TFB(), // 1-bit output: 3-state control
+                    // SHIFTIN1 / SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each)
+                    .SHIFTIN1(0),
+                    .SHIFTIN2(0),
+                    // T1 - T4: 1-bit (each) input: Parallel 3-state inputs
+                    .T2(0),
+                    .T3(0),
+                    .T4(0),
+                    .TBYTEIN(0)
+                    // 1-bit input: Byte group tristate
+                );
+                // End of OSERDESE2_inst instantiation
+                
+                // IOBUF: Single-ended Bi-directional Buffer
+                //All devices
+                // Xilinx HDL Libraries Guide, version 13.4
+                `ifndef SIM_MODEL
+                    IOBUF #(
+                `else 
+                    IOBUF_model #(
+                `endif
+                    //.DRIVE(12), // Specify the output drive strength
+                    .IBUF_LOW_PWR("FALSE"), // Low Power - "TRUE", High Performance = "FALSE"
+                    //.IOSTANDARD("SSTL15"), // Specify the I/O standard
+                    .SLEW("FAST") // Specify the output slew rate
+                ) IOBUF_data (
+                    .O(read_dq[gen_index]),// Buffer output
+                    .IO(io_ddr3_dq[gen_index]), // Buffer inout port (connect directly to top-level port)
+                    .I(oserdes_data[gen_index]), // Buffer input
+                    .T(oserdes_dq_tri_control[gen_index]) // 3-state enable input, high=read, low=write
+                );
+            end
+
+            // IDELAYE2: Input Fixed or Variable Delay Element
+            // 7 Series
+            // Xilinx HDL Libraries Guide, version 13.4
+            (* IODELAY_GROUP="DDR3-GROUP" *)
+            `ifndef SIM_MODEL
+                IDELAYE2 #(
+            `else 
+                IDELAYE2_model #(
+            `endif
+                .DELAY_SRC("IDATAIN"), // Delay input (IDATAIN, DATAIN)
+                .HIGH_PERFORMANCE_MODE("TRUE"), //Reduced jitter ("TRUE"), Reduced power ("FALSE")
+                .IDELAY_TYPE("VAR_LOAD"), //FIXED, VARIABLE, VAR_LOAD, VAR_LOAD_PIPE
+                .IDELAY_VALUE(DATA_IDELAY_TAP), //Input delay tap setting (0-31)
+                .PIPE_SEL("FALSE"),  //Select pipelined mode, FALSE, TRUE
+                .REFCLK_FREQUENCY(200.0), //IDELAYCTRL clock input frequency in MHz (190.0-210.0).
+                .SIGNAL_PATTERN("DATA") //DATA, CLOCK input signal
+            )
+            IDELAYE2_data (
+                .CNTVALUEOUT(), // 5-bit output: Counter value output
+                .DATAOUT(idelay_data[gen_index]), // 1-bit output: Delayed data output
+                .C(i_controller_clk), // 1-bit input: Clock input
+                .CE(1'b0), // 1-bit input: Active high enable increment/decrement input
+                .CINVCTRL(1'b0),// 1-bit input: Dynamic clock inversion input
+                .CNTVALUEIN(i_controller_idelay_data_cntvaluein), // 5-bit input: Counter value input
+                .DATAIN(), //1-bit input: Internal delay data input
+                .IDATAIN(read_dq[gen_index]), // 1-bit input: Data input from the I/O
+                .INC(1'b0), // 1-bit input: Increment / Decrement tap delay input
+                .LD(i_controller_idelay_data_ld[gen_index/8]), // 1-bit input: Load IDELAY_VALUE input
+                .LDPIPEEN(1'b0), // 1-bit input: Enable PIPELINE register to load data input
+                .REGRST(1'b0) // 1-bit input: Active-high reset tap-delay input
+            );
+            // End of IDELAYE2_inst instantiation
+
+            // End of IOBUF_inst instantiation                 
+            // ISERDESE2: Input SERial/DESerializer with bitslip
+            //7 Series
+            // Xilinx HDL Libraries Guide, version 13.4
+            `ifndef SIM_MODEL
+                ISERDESE2 #(
+            `else 
+                ISERDESE2_model #(
+            `endif
+                .DATA_RATE("DDR"), // DDR, SDR
+                .DATA_WIDTH(8), // Parallel data width (2-8,10,14)
+                // INIT_Q1 - INIT_Q4: Initial value on the Q outputs (0/1)
+                .INIT_Q1(1'b0),
+                .INIT_Q2(1'b0),
+                .INIT_Q3(1'b0),
+                .INIT_Q4(1'b0),
+                .INTERFACE_TYPE("NETWORKING"), // MEMORY, MEMORY_DDR3, MEMORY_QDR, NETWORKING, OVERSAMPLE
+                .IOBDELAY("IFD"), // NONE, BOTH, IBUF, IFD
+                .NUM_CE(1),// Number of clock enables (1,2)
+                .OFB_USED("FALSE"), // Select OFB path (FALSE, TRUE)
+                // SRVAL_Q1 - SRVAL_Q4: Q output values when SR is used (0/1)
+                .SRVAL_Q1(1'b0),
+                .SRVAL_Q2(1'b0),
+                .SRVAL_Q3(1'b0),
+                .SRVAL_Q4(1'b0)
+            )
+            ISERDESE2_data (
+                .O(),
+                // 1-bit output: Combinatorial output
+                // Q1 - Q8: 1-bit (each) output: Registered data outputs
+                .Q1(o_controller_iserdes_data[(DQ_BITS*LANES)*7 + gen_index]),//56
+                .Q2(o_controller_iserdes_data[(DQ_BITS*LANES)*6 + gen_index]), //48
+                .Q3(o_controller_iserdes_data[(DQ_BITS*LANES)*5 + gen_index]),
+                .Q4(o_controller_iserdes_data[(DQ_BITS*LANES)*4 + gen_index]),   
+                .Q5(o_controller_iserdes_data[(DQ_BITS*LANES)*3 + gen_index]),
+                .Q6(o_controller_iserdes_data[(DQ_BITS*LANES)*2 + gen_index]),
+                .Q7(o_controller_iserdes_data[(DQ_BITS*LANES)*1 + gen_index]), 
+                .Q8(o_controller_iserdes_data[(DQ_BITS*LANES)*0 + gen_index]),
+                // SHIFTOUT1-SHIFTOUT2: 1-bit (each) output: Data width expansion output ports
+                .SHIFTOUT1(),
+                .SHIFTOUT2(),
+                .BITSLIP(i_controller_bitslip[gen_index/8]),
+                // 1-bit input: The BITSLIP pin performs a Bitslip operation synchronous to
+                // CLKDIV when asserted (active High). Subsequently, the data seen on the Q1
+                // to Q8 output ports will shift, as in a barrel-shifter operation, one
+                // position every time Bitslip is invoked (DDR operation is different from
+                // SDR).
+                // CE1, CE2: 1-bit (each) input: Data register clock enable inputs
+                .CE1(1'b1),
+                .CE2(1'b1),
+                .CLKDIVP(), // 1-bit input: TBD
+                // Clocks: 1-bit (each) input: ISERDESE2 clock input ports
+                .CLK(i_ddr3_clk), // 1-bit input: High-speed clock
+                .CLKB(!i_ddr3_clk), // 1-bit input: High-speed secondary clock
+                .CLKDIV(i_controller_clk), // 1-bit input: Divided clock
+                .OCLK(), // 1-bit input: High speed output clock used when INTERFACE_TYPE="MEMORY"
+                // Dynamic Clock Inversions: 1-bit (each) input: Dynamic clock inversion pins to switch clock polarity
+                .DYNCLKDIVSEL(), // 1-bit input: Dynamic CLKDIV inversion
+                .DYNCLKSEL(), // 1-bit input: Dynamic CLK/CLKB inversion
+                // Input Data: 1-bit (each) input: ISERDESE2 data input ports
+                .D(), // 1-bit input: Data input
+                .DDLY(idelay_data[gen_index]), // 1-bit input: Serial data from IDELAYE2
+                .OFB(), // 1-bit input: Data feedback from OSERDESE2
+                .OCLKB(), // 1-bit input: High speed negative edge output clock
+                .RST(sync_rst), // 1-bit input: Active high asynchronous reset
+                // SHIFTIN1-SHIFTIN2: 1-bit (each) input: Data width expansion input ports
+                .SHIFTIN1(),
+                .SHIFTIN2()
+            );
+            // End of ISERDESE2_inst instantiation
+  
+        end
+        
+        // data mask: oserdes -> odelay -> obuf
+        for(gen_index = 0; gen_index < LANES; gen_index = gen_index + 1) begin
+ 
+            
+            if(ODELAY_SUPPORTED) begin
+                // OSERDESE2: Output SERial/DESerializer with bitslip
+                //7 Series
+                // Xilinx HDL Libraries Guide, version 13.4
+                `ifndef SIM_MODEL
+                    OSERDESE2 #(
+                `else 
+                    OSERDESE2_model #(
+                `endif
+                    .DATA_RATE_OQ("DDR"), // DDR, SDR
+                    .DATA_RATE_TQ("BUF"), // DDR, SDR
+                    .DATA_WIDTH(8), // Parallel data width (2-8,10,14)
+                    .INIT_OQ(1'b0), // Initial value of OQ output (1'b0,1'b1)
+                    .TRISTATE_WIDTH(1)
+                )
+                OSERDESE2_dm(
+                    .OFB(oserdes_dm[gen_index]), // 1-bit output: Feedback path for data
+                    .OQ(), // 1-bit output: Data path output
+                    .CLK(i_ddr3_clk), // 1-bit input: High speed clock
+                    .CLKDIV(i_controller_clk), // 1-bit input: Divided clock
+                    // D1 - D8: 1-bit (each) input: Parallel data inputs (1-bit each)
+                    .D1(i_controller_dm[gen_index + LANES*0]),
+                    .D2(i_controller_dm[gen_index + LANES*1]),
+                    .D3(i_controller_dm[gen_index + LANES*2]),
+                    .D4(i_controller_dm[gen_index + LANES*3]),
+                    .D5(i_controller_dm[gen_index + LANES*4]),
+                    .D6(i_controller_dm[gen_index + LANES*5]),
+                    .D7(i_controller_dm[gen_index + LANES*6]),
+                    .D8(i_controller_dm[gen_index + LANES*7]), 
+                    .TCE(1'b0),
+                    .OCE(1'b1), // 1-bit input: Output data clock enable
+                    .RST(sync_rst), // 1-bit input: Reset
+                     // unused signals but were added here to make vivado happy
+                    .SHIFTOUT1(), // SHIFTOUT1 / SHIFTOUT2: 1-bit (each) output: Data output expansion (1-bit each)
+                    .SHIFTOUT2(),
+                    .TBYTEOUT(), // 1-bit output: Byte group tristate
+                    .TFB(), // 1-bit output: 3-state control
+                    .TQ(), // 1-bit output: 3-state control
+                    // SHIFTIN1 / SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each)
+                    .SHIFTIN1(0),
+                    .SHIFTIN2(0),
+                    // T1 - T4: 1-bit (each) input: Parallel 3-state inputs
+                    .T1(0),
+                    .T2(0),
+                    .T3(0),
+                    .T4(0),
+                    .TBYTEIN(0)
+                    // 1-bit input: Byte group tristate
+                );
+                // End of OSERDESE2_inst instantiation
+            
+                // ODELAYE2: Output Fixed or Variable Delay Element
+                // 7 Series
+                // Xilinx HDL Libraries Guide, version 13.4
+                //odelay adds an insertion delay of 600ps to the actual delay setting: https://support.xilinx.com/s/article/42133?language=en_US
+                //Delay the DQ
+                // Delay resolution: 1/(32 x 2 x F REF ) = 78.125ps
+                (* IODELAY_GROUP="DDR3-GROUP" *)
+                `ifndef SIM_MODEL
+                    ODELAYE2 #(
+                `else 
+                    ODELAYE2_model #(
+                `endif
+                    .DELAY_SRC("ODATAIN"), // Delay input (ODATAIN, CLKIN)
+                    .HIGH_PERFORMANCE_MODE("TRUE"), // Reduced jitter to 5ps ("TRUE"), Reduced power but high jitter 9ns ("FALSE")
+                    .ODELAY_TYPE("VAR_LOAD"), // FIXED, VARIABLE, VAR_LOAD, VAR_LOAD_PIPE
+                    .ODELAY_VALUE(DATA_ODELAY_TAP), // Output delay tap setting (0-31)
+                    .REFCLK_FREQUENCY(200.0), // IDELAYCTRL clock input frequency in MHz (190.0-210.0).
+                    .SIGNAL_PATTERN("DATA") // DATA, CLOCK input signal
+                )
+                ODELAYE2_dm (
+                    .CNTVALUEOUT(), // 5-bit output: Counter value output
+                    .DATAOUT(odelay_dm[gen_index]), // 1-bit output: Delayed data/clock output
+                    .C(i_controller_clk), // 1-bit input: Clock input, when using OSERDESE2, C is connected to CLKDIV
+                    .CE(1'b0), // 1-bit input: Active high enable increment/decrement input
+                    .CINVCTRL(1'b0), // 1-bit input: Dynamic clock inversion input
+                    .CLKIN(1'b0), // 1-bit input: Clock delay input
+                    .CNTVALUEIN(i_controller_odelay_data_cntvaluein), // 5-bit input: Counter value input
+                    .INC(1'b0), // 1-bit input: Increment / Decrement tap delay input
+                    .LD(i_controller_odelay_data_ld[gen_index]), // 1-bit input: Loads ODELAY_VALUE tap delay in VARIABLE mode, in VAR_LOAD or
+                                // VAR_LOAD_PIPE mode, loads the value of CNTVALUEIN
+                    .LDPIPEEN(1'b0), // 1-bit input: Enables the pipeline register to load data
+                    .ODATAIN(oserdes_dm[gen_index]), // 1-bit input: Output delay data input
+                    .REGRST(1'b0) // 1-bit input: Active-high reset tap-delay input
+                );
+                
+                // OBUF: Single-ended Output Buffer
+                // 7 Series
+                // Xilinx HDL Libraries Guide, version 13.4
+                `ifndef SIM_MODEL
+                    OBUF #(
+                `else 
+                    OBUF_model #(
+                `endif
+                //.IOSTANDARD("SSTL_15"), // Specify the output I/O standard
+                .SLEW("FAST") // Specify the output slew rate
+                ) OBUF_dm (
+                    .O(o_ddr3_dm[gen_index]), // Buffer output (connect directly to top-level port)
+                    .I(odelay_dm[gen_index]) // Buffer input
+                );
+                // End of OBUF_inst instantiation
+            end
+            else begin
+                // OSERDESE2: Output SERial/DESerializer with bitslip
+                //7 Series
+                // Xilinx HDL Libraries Guide, version 13.4
+                `ifndef SIM_MODEL
+                    OSERDESE2 #(
+                `else 
+                    OSERDESE2_model #(
+                `endif
+                    .DATA_RATE_OQ("DDR"), // DDR, SDR
+                    .DATA_RATE_TQ("BUF"), // DDR, SDR
+                    .DATA_WIDTH(8), // Parallel data width (2-8,10,14)
+                    .INIT_OQ(1'b0), // Initial value of OQ output (1'b0,1'b1)
+                    .TRISTATE_WIDTH(1)
+                )
+                OSERDESE2_dm(
+                    .OFB(), // 1-bit output: Feedback path for data
+                    .OQ(oserdes_dm[gen_index]), // 1-bit output: Data path output
+                    .CLK(i_ddr3_clk_90), // 1-bit input: High speed clock
+                    .CLKDIV(i_controller_clk), // 1-bit input: Divided clock
+                    // D1 - D8: 1-bit (each) input: Parallel data inputs (1-bit each)
+                    .D1(i_controller_dm[gen_index + LANES*0]),
+                    .D2(i_controller_dm[gen_index + LANES*1]),
+                    .D3(i_controller_dm[gen_index + LANES*2]),
+                    .D4(i_controller_dm[gen_index + LANES*3]),
+                    .D5(i_controller_dm[gen_index + LANES*4]),
+                    .D6(i_controller_dm[gen_index + LANES*5]),
+                    .D7(i_controller_dm[gen_index + LANES*6]),
+                    .D8(i_controller_dm[gen_index + LANES*7]), 
+                    .TCE(1'b0),
+                    .OCE(1'b1), // 1-bit input: Output data clock enable
+                    .RST(sync_rst), // 1-bit input: Reset
+                     // unused signals but were added here to make vivado happy
+                    .SHIFTOUT1(), // SHIFTOUT1 / SHIFTOUT2: 1-bit (each) output: Data output expansion (1-bit each)
+                    .SHIFTOUT2(),
+                    .TBYTEOUT(), // 1-bit output: Byte group tristate
+                    .TFB(), // 1-bit output: 3-state control
+                    .TQ(), // 1-bit output: 3-state control
+                    // SHIFTIN1 / SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each)
+                    .SHIFTIN1(0),
+                    .SHIFTIN2(0),
+                    // T1 - T4: 1-bit (each) input: Parallel 3-state inputs
+                    .T1(0),
+                    .T2(0),
+                    .T3(0),
+                    .T4(0),
+                    .TBYTEIN(0)
+                    // 1-bit input: Byte group tristate
+                );
+                // End of OSERDESE2_inst instantiation
+            
+                // OBUF: Single-ended Output Buffer
+                // 7 Series
+                // Xilinx HDL Libraries Guide, version 13.4
+                `ifndef SIM_MODEL
+                    OBUF #(
+                `else 
+                    OBUF_model #(
+                `endif
+                //.IOSTANDARD("SSTL_15"), // Specify the output I/O standard
+                .SLEW("FAST") // Specify the output slew rate
+                ) OBUF_dm (
+                    .O(o_ddr3_dm[gen_index]), // Buffer output (connect directly to top-level port)
+                    .I(oserdes_dm[gen_index]) // Buffer input
+                );
+                // End of OBUF_inst instantiation
+            
+            end
+        end
+
+        // dqs: odelay -> iobuf
+        for(gen_index = 0; gen_index < LANES; gen_index = gen_index + 1) begin
+`ifndef DEBUG_DQS  //remove the logic for dqs if needs to be debugged (directed to output instead)  
+            if(ODELAY_SUPPORTED) begin 
+                // OSERDESE2: Output SERial/DESerializer with bitslip
+                //7 Series
+                // Xilinx HDL Libraries Guide, version 13.4
+                `ifndef SIM_MODEL
+                    OSERDESE2 #(
+                `else 
+                    OSERDESE2_model #(
+                `endif
+                    .DATA_RATE_OQ("DDR"), // DDR, SDR
+                    .DATA_RATE_TQ("BUF"), // DDR, SDR
+                    .DATA_WIDTH(8), // Parallel data width (2-8,10,14)
+                    .INIT_OQ(1'b1), // Initial value of OQ output (1'b0,1'b1)
+                    .TRISTATE_WIDTH(1)
+                )
+                OSERDESE2_dqs(
+                    .OFB(oserdes_dqs[gen_index]), // 1-bit output: Feedback path for data
+                    .OQ(), // 1-bit output: Data path output
+                    .TQ(oserdes_dqs_tri_control[gen_index]),
+                    .CLK(i_ddr3_clk), // 1-bit input: High speed clock
+                    .CLKDIV(i_controller_clk), // 1-bit input: Divided clock
+                    // D1 - D8: 1-bit (each) input: Parallel data inputs (1-bit each)
+                    .D1(1'b1 && (i_controller_toggle_dqs || toggle_dqs_q)), //the last part will still have half dqs series
+                    .D2(1'b0 && (i_controller_toggle_dqs || toggle_dqs_q)),
+                    .D3(1'b1 && (i_controller_toggle_dqs || toggle_dqs_q) && !i_controller_write_leveling_calib),
+                    .D4(1'b0 && (i_controller_toggle_dqs || toggle_dqs_q)),
+                    .D5(1'b1 && i_controller_toggle_dqs && !i_controller_write_leveling_calib),
+                    .D6(1'b0 && i_controller_toggle_dqs),
+                    .D7(1'b1 && i_controller_toggle_dqs && !i_controller_write_leveling_calib),
+                    .D8(1'b0 && i_controller_toggle_dqs),
+                    .T1(i_controller_dqs_tri_control),
+                    .TCE(1'b1),
+                    .OCE(1'b1), // 1-bit input: Output data clock enable
+                    .RST(sync_rst), // 1-bit input: Reset
+                     // unused signals but were added here to make vivado happy
+                    .SHIFTOUT1(), // SHIFTOUT1 / SHIFTOUT2: 1-bit (each) output: Data output expansion (1-bit each)
+                    .SHIFTOUT2(),
+                    .TBYTEOUT(), // 1-bit output: Byte group tristate
+                    .TFB(), // 1-bit output: 3-state control
+                    // SHIFTIN1 / SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each)
+                    .SHIFTIN1(0),
+                    .SHIFTIN2(0),
+                    // T1 - T4: 1-bit (each) input: Parallel 3-state inputs
+                    .T2(0),
+                    .T3(0),
+                    .T4(0),
+                    .TBYTEIN(0)
+                    // 1-bit input: Byte group tristate
+                );
+                // End of OSERDESE2_inst instantiation
+            
+            
+                // ODELAYE2: Output Fixed or Variable Delay Element
+                // 7 Series
+                // Xilinx HDL Libraries Guide, version 13.4
+                //Delay the DQ
+                (* IODELAY_GROUP="DDR3-GROUP" *)
+                `ifndef SIM_MODEL
+                    ODELAYE2 #(
+                `else 
+                    ODELAYE2_model #(
+                `endif
+                    .DELAY_SRC("ODATAIN"), // Delay input (ODATAIN, CLKIN)
+                    .HIGH_PERFORMANCE_MODE("TRUE"), // Reduced jitter ("TRUE"), Reduced power ("FALSE")
+                    .ODELAY_TYPE("VAR_LOAD"), // FIXED, VARIABLE, VAR_LOAD, VAR_LOAD_PIPE
+                    .ODELAY_VALUE(DQS_ODELAY_TAP), // delay to align odelay_dqs to oserdes_dqs due to 600ps insertion delay: (1/800MHz - 600ps)/78.125ps = 8.32 taps
+                    .REFCLK_FREQUENCY(200.0), // IDELAYCTRL clock input frequency in MHz (190.0-210.0).
+                    .SIGNAL_PATTERN("DATA") // DATA, CLOCK input signal
+                )
+                ODELAYE2_dqs (
+                    .CNTVALUEOUT(), // 5-bit output: Counter value output
+                    .DATAOUT(odelay_dqs[gen_index]), // 1-bit output: Delayed data/clock output
+                    .C(i_controller_clk), // 1-bit input: Clock input, when using OSERDESE2, C is connected to CLKDIV
+                    .CE(1'b0), // 1-bit input: Active high enable increment/decrement input
+                    .CINVCTRL(1'b0), // 1-bit input: Dynamic clock inversion input
+                    .CLKIN(1'b0), // 1-bit input: Clock delay input
+                    .CNTVALUEIN(i_controller_odelay_dqs_cntvaluein), // 5-bit input: Counter value input
+                    .INC(1'b0), // 1-bit input: Increment / Decrement tap delay input
+                    .LD(i_controller_odelay_dqs_ld[gen_index]), // 1-bit input: Loads ODELAY_VALUE tap delay in VARIABLE mode, in VAR_LOAD or
+                                // VAR_LOAD_PIPE mode, loads the value of CNTVALUEIN
+                    .LDPIPEEN(1'b0), // 1-bit input: Enables the pipeline register to load data
+                    .ODATAIN(oserdes_dqs[gen_index]), // 1-bit input: Output delay data input
+                    .REGRST(1'b0) // 1-bit input: Active-high reset tap-delay input
+                );
+                
+                if(USE_IO_TERMINATION) begin 
+                    // IOBUFDS_DCIEN: Differential Bi-directional Buffer with Digital Controlled Impedance (DCI)
+                    // and Input path enable/disable
+                    // May only be placed in High Performance (HP) Banks
+                    // 7 Series
+                    // Xilinx HDL Libraries Guide, version 13.4
+                    `ifndef SIM_MODEL
+                        IOBUFDS_DCIEN #(
+                    `else 
+                        IOBUFDS_DCIEN_model #(
+                    `endif
+                        .IBUF_LOW_PWR("FALSE"), // Low Power - "TRUE", High Performance = "FALSE"
+                        .SLEW("FAST"), // Specify the output slew rate
+                        .USE_IBUFDISABLE("FALSE") // Use IBUFDISABLE function, "TRUE" or "FALSE"
+                    ) IOBUFDS_DCIEN_inst (
+                        .O(read_dqs[gen_index]),  // Buffer output
+                        .IO(io_ddr3_dqs[gen_index]), // Diff_p inout (connect directly to top-level port)
+                        .IOB(io_ddr3_dqs_n[gen_index]), // Diff_n inout (connect directly to top-level port)
+                        .DCITERMDISABLE(1'b0), // DCI Termination enable input
+                        .I(odelay_dqs[gen_index]), // Buffer input
+                        .IBUFDISABLE(1'b0), // Input disable input, low=disable
+                        .T(oserdes_dqs_tri_control[gen_index]) // 3-state enable input, high=input, low=output
+                    );
+                    // End of IOBUFDS_DCIEN_inst instantiation
+
+                end
+                else begin
+                    // IOBUFDS: Differential Bi-directional Buffer
+                    //7 Series
+                    // Xilinx HDL Libraries Guide, version 13.4
+                    `ifndef SIM_MODEL
+                        IOBUFDS #(
+                    `else 
+                        IOBUFDS_model #(
+                    `endif
+                        //.DIFF_TERM("FALSE"), // Differential Termination ("TRUE"/"FALSE")
+                        .IBUF_LOW_PWR("FALSE") // Low Power - "TRUE", High Performance = "FALSE"
+                        //.IOSTANDARD("DIFF_SSTL15") // Specify the I/O standard. CONSULT WITH DATASHEET
+                        //.SLEW("FAST") // Specify the output slew rate
+                    ) IOBUFDS_dqs (
+                        .O(read_dqs[gen_index]), // Buffer output
+                        .IO(io_ddr3_dqs[gen_index]), // Diff_p inout (connect directly to top-level port)
+                        .IOB(io_ddr3_dqs_n[gen_index]), // Diff_n inout (connect directly to top-level port)
+                        .I(odelay_dqs[gen_index]), // Buffer input
+                        .T(/*!dqs_tri_control[gen_index]*/oserdes_dqs_tri_control[gen_index]) // 3-state enable input, high=input, low=output
+                    ); // End of IOBUFDS_inst instantiation
+                end
+                
+            end
+            
+            else begin //ODELAY not supported
+                // OSERDESE2: Output SERial/DESerializer with bitslip
+                //7 Series
+                // Xilinx HDL Libraries Guide, version 13.4
+                `ifndef SIM_MODEL
+                    OSERDESE2 #(
+                `else 
+                    OSERDESE2_model #(
+                `endif
+                    .DATA_RATE_OQ("DDR"), // DDR, SDR
+                    .DATA_RATE_TQ("BUF"), // DDR, SDR
+                    .DATA_WIDTH(8), // Parallel data width (2-8,10,14)
+                    .INIT_OQ(1'b1), // Initial value of OQ output (1'b0,1'b1)
+                    .TRISTATE_WIDTH(1)
+                )
+                OSERDESE2_dqs(
+                    .OFB(), // 1-bit output: Feedback path for data
+                    .OQ(oserdes_dqs[gen_index]), // 1-bit output: Data path output
+                    .TQ(oserdes_dqs_tri_control[gen_index]),
+                    .CLK(!i_ddr3_clk), // 1-bit input: High speed clock
+                    .CLKDIV(i_controller_clk), // 1-bit input: Divided clock
+                    // D1 - D8: 1-bit (each) input: Parallel data inputs (1-bit each)
+                    .D1(1'b1 && (i_controller_toggle_dqs || toggle_dqs_q)), //the last part will still have half dqs series
+                    .D2(1'b0 && (i_controller_toggle_dqs || toggle_dqs_q)),
+                    .D3(1'b1 && (i_controller_toggle_dqs || toggle_dqs_q) && !i_controller_write_leveling_calib),
+                    .D4(1'b0 && (i_controller_toggle_dqs || toggle_dqs_q)),
+                    .D5(1'b1 && i_controller_toggle_dqs && !i_controller_write_leveling_calib),
+                    .D6(1'b0 && i_controller_toggle_dqs),
+                    .D7(1'b1 && i_controller_toggle_dqs && !i_controller_write_leveling_calib),
+                    .D8(1'b0 && i_controller_toggle_dqs),
+                    .T1(i_controller_dqs_tri_control),
+                    .TCE(1'b1),
+                    .OCE(1'b1), // 1-bit input: Output data clock enable
+                    .RST(sync_rst), // 1-bit input: Reset
+                     // unused signals but were added here to make vivado happy
+                    .SHIFTOUT1(), // SHIFTOUT1 / SHIFTOUT2: 1-bit (each) output: Data output expansion (1-bit each)
+                    .SHIFTOUT2(),
+                    .TBYTEOUT(), // 1-bit output: Byte group tristate
+                    .TFB(), // 1-bit output: 3-state control
+                    // SHIFTIN1 / SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each)
+                    .SHIFTIN1(0),
+                    .SHIFTIN2(0),
+                    // T1 - T4: 1-bit (each) input: Parallel 3-state inputs
+                    .T2(0),
+                    .T3(0),
+                    .T4(0),
+                    .TBYTEIN(0)
+                    // 1-bit input: Byte group tristate
+                );
+                // End of OSERDESE2_inst instantiation
+                
+                // IOBUFDS: Differential Bi-directional Buffer
+                //7 Series
+                // Xilinx HDL Libraries Guide, version 13.4
+                `ifndef SIM_MODEL
+                    IOBUFDS #(
+                `else 
+                    IOBUFDS_model #(
+                `endif
+                    //.DIFF_TERM("FALSE"), // Differential Termination ("TRUE"/"FALSE")
+                    .IBUF_LOW_PWR("FALSE") // Low Power - "TRUE", High Performance = "FALSE"
+                    //.IOSTANDARD("DIFF_SSTL15") // Specify the I/O standard. CONSULT WITH DATASHEET
+                    //.SLEW("FAST") // Specify the output slew rate
+                ) IOBUFDS_dqs (
+                    .O(read_dqs[gen_index]), // Buffer output
+                    .IO(io_ddr3_dqs[gen_index]), // Diff_p inout (connect directly to top-level port)
+                    .IOB(io_ddr3_dqs_n[gen_index]), // Diff_n inout (connect directly to top-level port)
+                    .I(oserdes_dqs[gen_index]), // Buffer input
+                    .T(/*!dqs_tri_control[gen_index]*/oserdes_dqs_tri_control[gen_index]) // 3-state enable input, high=input, low=output
+                ); // End of IOBUFDS_inst instantiation
+                
+            end
+            
+            // IDELAYE2: Input Fixed or Variable Delay Element
+            // 7 Series
+            // Xilinx HDL Libraries Guide, version 13.4
+            (* IODELAY_GROUP="DDR3-GROUP" *)
+            `ifndef SIM_MODEL
+                IDELAYE2 #(
+            `else 
+                IDELAYE2_model #(
+            `endif
+                .DELAY_SRC("IDATAIN"), // Delay input (IDATAIN, DATAIN)
+                .HIGH_PERFORMANCE_MODE("TRUE"), //Reduced jitter ("TRUE"), Reduced power ("FALSE")
+                .IDELAY_TYPE("VAR_LOAD"), //FIXED, VARIABLE, VAR_LOAD, VAR_LOAD_PIPE
+                .IDELAY_VALUE(DQS_IDELAY_TAP), //Input delay tap setting (0-31)
+                .PIPE_SEL("FALSE"),  //Select pipelined mode, FALSE, TRUE
+                .REFCLK_FREQUENCY(200.0), //IDELAYCTRL clock input frequency in MHz (190.0-210.0).
+                .SIGNAL_PATTERN("CLOCK") //DATA, CLOCK input signal
+            )
+            IDELAYE2_dqs (
+                .CNTVALUEOUT(), // 5-bit output: Counter value output
+                .DATAOUT(idelay_dqs[gen_index]), // 1-bit output: Delayed data output
+                .C(i_controller_clk), // 1-bit input: Clock input
+                .CE(1'b0), // 1-bit input: Active high enable increment/decrement input
+                .CINVCTRL(1'b0),// 1-bit input: Dynamic clock inversion input
+                .CNTVALUEIN(i_controller_idelay_dqs_cntvaluein), // 5-bit input: Counter value input
+                .DATAIN(), //1-bit input: Internal delay data input
+                .IDATAIN(read_dqs[gen_index]), // 1-bit input: Data input from the I/O
+                .INC(1'b0), // 1-bit input: Increment / Decrement tap delay input
+                .LD(i_controller_idelay_dqs_ld[gen_index]), // 1-bit input: Load IDELAY_VALUE input
+                .LDPIPEEN(1'b0), // 1-bit input: Enable PIPELINE register to load data input
+                .REGRST(1'b0) // 1-bit input: Active-high reset tap-delay input
+            );
+            // End of IDELAYE2_inst instantiation
+            
+             
+              // End of IOBUF_inst instantiation                 
+            // ISERDESE2: Input SERial/DESerializer with bitslip
+            //7 Series
+            // Xilinx HDL Libraries Guide, version 13.4
+            `ifndef SIM_MODEL
+                ISERDESE2 #(
+            `else 
+                ISERDESE2_model #(
+            `endif
+                .DATA_RATE("DDR"), // DDR, SDR
+                .DATA_WIDTH(serdes_ratio*2), // Parallel data width (2-8,10,14)
+                // INIT_Q1 - INIT_Q4: Initial value on the Q outputs (0/1)
+                .INIT_Q1(1'b0),
+                .INIT_Q2(1'b0),
+                .INIT_Q3(1'b0),
+                .INIT_Q4(1'b0),
+                .INTERFACE_TYPE("NETWORKING"), // MEMORY, MEMORY_DDR3, MEMORY_QDR, NETWORKING, OVERSAMPLE
+                .IOBDELAY("IFD"), // NONE, BOTH, IBUF, IFD
+                .NUM_CE(1),// Number of clock enables (1,2)
+                .OFB_USED("FALSE"), // Select OFB path (FALSE, TRUE)
+                // SRVAL_Q1 - SRVAL_Q4: Q output values when SR is used (0/1)
+                .SRVAL_Q1(1'b0),
+                .SRVAL_Q2(1'b0),
+                .SRVAL_Q3(1'b0),
+                .SRVAL_Q4(1'b0)
+            )
+            ISERDESE2_dqs (
+                .O(),
+                // 1-bit output: Combinatorial output
+                // Q1 - Q8: 1-bit (each) output: Registered data outputs
+                .Q1(o_controller_iserdes_dqs[serdes_ratio*2*gen_index + 7]),
+                .Q2(o_controller_iserdes_dqs[serdes_ratio*2*gen_index + 6]),
+                .Q3(o_controller_iserdes_dqs[serdes_ratio*2*gen_index + 5]),
+                .Q4(o_controller_iserdes_dqs[serdes_ratio*2*gen_index + 4]),   
+                .Q5(o_controller_iserdes_dqs[serdes_ratio*2*gen_index + 3]),
+                .Q6(o_controller_iserdes_dqs[serdes_ratio*2*gen_index + 2]), //
+                .Q7(o_controller_iserdes_dqs[serdes_ratio*2*gen_index + 1]), //3
+                .Q8(o_controller_iserdes_dqs[serdes_ratio*2*gen_index + 0]), //2
+                // SHIFTOUT1-SHIFTOUT2: 1-bit (each) output: Data width expansion output ports
+                .SHIFTOUT1(),
+                .SHIFTOUT2(),
+                .BITSLIP(i_controller_bitslip[gen_index]),
+                // 1-bit input: The BITSLIP pin performs a Bitslip operation synchronous to
+                // CLKDIV when asserted (active High). Subsequently, the data seen on the Q1
+                // to Q8 output ports will shift, as in a barrel-shifter operation, one
+                // position every time Bitslip is invoked (DDR operation is different from
+                // SDR).
+                // CE1, CE2: 1-bit (each) input: Data register clock enable inputs
+                .CE1(1'b1),
+                .CE2(1'b1),
+                .CLKDIVP(), // 1-bit input: TBD
+                // Clocks: 1-bit (each) input: ISERDESE2 clock input ports
+                .CLK(i_ddr3_clk), // 1-bit input: High-speed clock
+                .CLKB(!i_ddr3_clk), // 1-bit input: High-speed secondary clock
+                .CLKDIV(i_controller_clk), // 1-bit input: Divided clock
+                .OCLK(), // 1-bit input: High speed output clock used when INTERFACE_TYPE="MEMORY"
+                // Dynamic Clock Inversions: 1-bit (each) input: Dynamic clock inversion pins to switch clock polarity
+                .DYNCLKDIVSEL(), // 1-bit input: Dynamic CLKDIV inversion
+                .DYNCLKSEL(), // 1-bit input: Dynamic CLK/CLKB inversion
+                // Input Data: 1-bit (each) input: ISERDESE2 data input ports
+                .D(), // 1-bit input: Data input
+                .DDLY(idelay_dqs[gen_index]), // 1-bit input: Serial data from IDELAYE2
+                .OFB(), // 1-bit input: Data feedback from OSERDESE2
+                .OCLKB(), // 1-bit input: High speed negative edge output clock
+                .RST(sync_rst), // 1-bit input: Active high asynchronous reset
+                // SHIFTIN1-SHIFTIN2: 1-bit (each) input: Data width expansion input ports
+                .SHIFTIN1(),
+                .SHIFTIN2()
+            );
+            // End of ISERDESE2_inst instantiation
+`endif
+            
+            // generate IOSERDES loopback or not for bitslip training
+            if(NO_IOSERDES_LOOPBACK) begin                    
+                // logic that models OSERDES loopback to ISERDES     
+                // accdg to IOSELECT (UG471) for 7-series:    
+                // " In DDR mode, every Bitslip operation causes the output pattern to alternate between
+                //   a shift right by one and shift left by three"
+                always @(posedge i_controller_clk) begin
+                    if(!i_rst_n || i_controller_reset) begin
+                        o_controller_iserdes_bitslip_reference_reg[(serdes_ratio*2*gen_index + 7) : (serdes_ratio*2*gen_index + 0)] <= 8'b0001_1110;
+                        shift_bitslip_index[gen_index] <= 0;
+                    end
+                    else if(i_controller_bitslip[gen_index]) begin
+                    // if shift_bitslip_index high, shift right by 3, else shift left by 1 (this is reverse of the IOSelect document for ISERDES since vector o_controller_iserdes_bitslip_reference is reversed)
+                        o_controller_iserdes_bitslip_reference_reg[(serdes_ratio*2*gen_index + 7) : (serdes_ratio*2*gen_index + 0)] <= 
+                            shift_bitslip_index[gen_index]? {o_controller_iserdes_bitslip_reference_reg[(serdes_ratio*2*gen_index + 2) : (serdes_ratio*2*gen_index + 0)], o_controller_iserdes_bitslip_reference_reg[(serdes_ratio*2*gen_index + 7) : (serdes_ratio*2*gen_index + 3)]}
+                            : {o_controller_iserdes_bitslip_reference_reg[(serdes_ratio*2*gen_index + 6) : (serdes_ratio*2*gen_index + 0)], o_controller_iserdes_bitslip_reference_reg[(serdes_ratio*2*gen_index + 7)]};
+                        shift_bitslip_index[gen_index] <= !shift_bitslip_index[gen_index];         
+                    end
+                end
+                assign o_controller_iserdes_bitslip_reference = o_controller_iserdes_bitslip_reference_reg;
+            end
+            else begin // OSERDES will loopback to ISERDES for bitslip training    
+                //ISERDES train
+                // End of IOBUF_inst instantiation                 
+                // ISERDESE2: Input SERial/DESerializer with bitslip
+                //7 Series
+                // Xilinx HDL Libraries Guide, version 13.4
+                `ifndef SIM_MODEL
+                    ISERDESE2 #(
+                `else 
+                    ISERDESE2_model #(
+                `endif
+                    .DATA_RATE("DDR"), // DDR, SDR
+                    .DATA_WIDTH(serdes_ratio*2), // Parallel data width (2-8,10,14)
+                    // INIT_Q1 - INIT_Q4: Initial value on the Q outputs (0/1)
+                    .INIT_Q1(1'b0),
+                    .INIT_Q2(1'b0),
+                    .INIT_Q3(1'b0),
+                    .INIT_Q4(1'b0),
+                    .INTERFACE_TYPE("NETWORKING"), // MEMORY, MEMORY_DDR3, MEMORY_QDR, NETWORKING, OVERSAMPLE
+                    .IOBDELAY("NONE"), // NONE, BOTH, IBUF, IFD
+                    .NUM_CE(1),// Number of clock enables (1,2)
+                    .OFB_USED("TRUE"), // Select OFB path (FALSE, TRUE)
+                    // SRVAL_Q1 - SRVAL_Q4: Q output values when SR is used (0/1)
+                    .SRVAL_Q1(1'b0),
+                    .SRVAL_Q2(1'b0),
+                    .SRVAL_Q3(1'b0),
+                    .SRVAL_Q4(1'b0)
+                )
+                ISERDESE2_train (
+                    .O(),
+                    // 1-bit output: Combinatorial output
+                    // Q1 - Q8: 1-bit (each) output: Registered data outputs
+                    .Q1(o_controller_iserdes_bitslip_reference[gen_index*serdes_ratio*2 + 7]),
+                    .Q2(o_controller_iserdes_bitslip_reference[gen_index*serdes_ratio*2 + 6]),
+                    .Q3(o_controller_iserdes_bitslip_reference[gen_index*serdes_ratio*2 + 5]),
+                    .Q4(o_controller_iserdes_bitslip_reference[gen_index*serdes_ratio*2 + 4]),   
+                    .Q5(o_controller_iserdes_bitslip_reference[gen_index*serdes_ratio*2 + 3]),
+                    .Q6(o_controller_iserdes_bitslip_reference[gen_index*serdes_ratio*2 + 2]),
+                    .Q7(o_controller_iserdes_bitslip_reference[gen_index*serdes_ratio*2 + 1]),
+                    .Q8(o_controller_iserdes_bitslip_reference[gen_index*serdes_ratio*2 + 0]),
+                    // SHIFTOUT1-SHIFTOUT2: 1-bit (each) output: Data width expansion output ports
+                    .SHIFTOUT1(),
+                    .SHIFTOUT2(),
+                    .BITSLIP(i_controller_bitslip[gen_index]),
+                    // 1-bit input: The BITSLIP pin performs a Bitslip operation synchronous to
+                    // CLKDIV when asserted (active High). Subsequently, the data seen on the Q1
+                    // to Q8 output ports will shift, as in a barrel-shifter operation, one
+                    // position every time Bitslip is invoked (DDR operation is different from
+                    // SDR).
+                    // CE1, CE2: 1-bit (each) input: Data register clock enable inputs
+                    .CE1(1'b1),
+                    .CE2(1'b1),
+                    .CLKDIVP(), // 1-bit input: TBD
+                    // Clocks: 1-bit (each) input: ISERDESE2 clock input ports
+                    .CLK(i_ddr3_clk), // 1-bit input: High-speed clock
+                    .CLKB(!i_ddr3_clk), // 1-bit input: High-speed secondary clock
+                    .CLKDIV(i_controller_clk), // 1-bit input: Divided clock
+                    .OCLK(), // 1-bit input: High speed output clock used when INTERFACE_TYPE="MEMORY"
+                    // Dynamic Clock Inversions: 1-bit (each) input: Dynamic clock inversion pins to switch clock polarity
+                    .DYNCLKDIVSEL(), // 1-bit input: Dynamic CLKDIV inversion
+                    .DYNCLKSEL(), // 1-bit input: Dynamic CLK/CLKB inversion
+                    // Input Data: 1-bit (each) input: ISERDESE2 data input ports
+                    .D(), // 1-bit input: Data input
+                    .DDLY(), // 1-bit input: Serial data from IDELAYE2
+                    .OFB(oserdes_bitslip_reference[gen_index]), // 1-bit input: Data feedback from OSERDESE2
+                    .OCLKB(), // 1-bit input: High speed negative edge output clock
+                    .RST(sync_rst), // 1-bit input: Active high asynchronous reset
+                    // SHIFTIN1-SHIFTIN2: 1-bit (each) input: Data width expansion input ports
+                    .SHIFTIN1(),
+                    .SHIFTIN2()
+                );
+                // End of ISERDESE2_inst instantiation
+                
+                // OSERDESE2: Output SERial/DESerializer with bitslip
+                //7 Series
+                // Xilinx HDL Libraries Guide, version 13.4
+                `ifndef SIM_MODEL
+                    OSERDESE2 #(
+                `else 
+                    OSERDESE2_model #(
+                `endif
+                    .DATA_RATE_OQ("DDR"), // DDR, SDR
+                    .DATA_RATE_TQ("BUF"), // DDR, SDR
+                    .DATA_WIDTH(8), // Parallel data width (2-8,10,14)
+                    .INIT_OQ(1'b1), // Initial value of OQ output (1'b0,1'b1)
+                    .TRISTATE_WIDTH(1)
+                )
+                OSERDESE2_train(
+                    .OFB(oserdes_bitslip_reference[gen_index]), // 1-bit output: Feedback path for data
+                    .OQ(), // 1-bit output: Data path output
+                    .CLK(i_ddr3_clk), // 1-bit input: High speed clock
+                    .CLKDIV(i_controller_clk), // 1-bit input: Divided clock
+                    // D1 - D8: 1-bit (each) input: Parallel data inputs (1-bit each)
+                    .D1(1'b0),
+                    .D2(1'b0),
+                    .D3(1'b0),
+                    .D4(1'b0),
+                    .D5(1'b1),
+                    .D6(1'b1),
+                    .D7(1'b1),
+                    .D8(1'b1),
+                    .OCE(1'b1), // 1-bit input: Output data clock enable
+                    .RST(sync_rst), // 1-bit input: Reset
+                     // unused signals but were added here to make vivado happy
+                    .SHIFTOUT1(), // SHIFTOUT1 / SHIFTOUT2: 1-bit (each) output: Data output expansion (1-bit each)
+                    .SHIFTOUT2(),
+                    .TBYTEOUT(), // 1-bit output: Byte group tristate
+                    .TFB(), // 1-bit output: 3-state control
+                    .TQ(), // 1-bit output: 3-state control
+                    // SHIFTIN1 / SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each)
+                    .SHIFTIN1(0),
+                    .SHIFTIN2(0),
+                    // T1 - T4: 1-bit (each) input: Parallel 3-state inputs
+                    .T1(0),
+                    .T2(0),
+                    .T3(0),
+                    .T4(0),
+                    .TBYTEIN(0),
+                    // 1-bit input: Byte group tristate
+                    .TCE(0)
+                    // 1-bit input: 3-state clock enable
+                );
+                // End of OSERDESE2_inst instantiation  
+            end
+            
+        end
+     endgenerate 
+     
+
+    // IDELAYCTRL: IDELAYE2/ODELAYE2 Tap Delay Value Control
+    // 7 Series
+    // Xilinx HDL Libraries Guide, version 13.4
+    (* IODELAY_GROUP="DDR3-GROUP" *)
+    `ifndef SIM_MODEL
+        IDELAYCTRL IDELAYCTRL_inst (
+    `else 
+        IDELAYCTRL_model IDELAYCTRL_inst (
+    `endif
+        .RDY(idelayctrl_rdy), // 1-bit output: Ready output
+        .REFCLK(i_ref_clk), // 1-bit input: Reference clock input.The frequency of REFCLK must be 200 MHz to guarantee the tap-delay value specified in the applicable data sheet.
+        .RST(sync_rst) // 1-bit input: Active high reset input, To ,Minimum Reset pulse width is 52ns
+    );
+    // End of IDELAYCTRL_inst instantiation
+
+
+    // DCIRESET: Digitially Controlled Impedence Reset Component
+    //7 Series
+    // Xilinx HDL Libraries Guide, version 13.4
+    // DCIRESET DCIRESET_inst (
+    //     .LOCKED(dci_locked), // 1-bit output: LOCK status output (When low, DCI I/O impedance is being calibrated and DCI I/Os are unavailable)
+    //     .RST(sync_rst) // 1-bit input: Active-high asynchronous reset input
+    // );
+    assign dci_locked = 1;
+    // End of DCIRESET_inst instantiation
+         
+endmodule

AngeloJacobo_UberDDR3/example_demo/arty_s7/ddr3_top.v

@@ -0,0 +1,475 @@
+////////////////////////////////////////////////////////////////////////////////
+//
+// Filename: ddr3_top.v
+// Project: UberDDR3 - An Open Source DDR3 Controller
+//
+// Purpose: Top module which instantiates the ddr3_controller and ddr3_phy modules
+// Use this as top module for instantiating UberDDR3 with Wishbone Interface.
+//
+// Engineer: Angelo C. Jacobo
+//
+////////////////////////////////////////////////////////////////////////////////
+//
+// Copyright (C) 2023-2025  Angelo Jacobo
+// 
+//     This program is free software: you can redistribute it and/or modify
+//     it under the terms of the GNU General Public License as published by
+//     the Free Software Foundation, either version 3 of the License, or
+//     (at your option) any later version.
+// 
+//     This program is distributed in the hope that it will be useful,
+//     but WITHOUT ANY WARRANTY; without even the implied warranty of
+//     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//     GNU General Public License for more details.
+// 
+//     You should have received a copy of the GNU General Public License
+//     along with this program.  If not, see <https://www.gnu.org/licenses/>.
+//
+////////////////////////////////////////////////////////////////////////////////
+
+`default_nettype none
+`timescale 1ps / 1ps
+
+module ddr3_top #(
+    parameter      CONTROLLER_CLK_PERIOD = 12_000, //ps, clock period of the controller interface
+                   DDR3_CLK_PERIOD = 3_000, //ps, clock period of the DDR3 RAM device (must be 1/4 of the CONTROLLER_CLK_PERIOD) 
+                   ROW_BITS = 14,   //width of row address
+                   COL_BITS = 10, //width of column address
+                   BA_BITS = 3, //width of bank address
+                   BYTE_LANES = 2, //number of byte lanes of DDR3 RAM
+                   AUX_WIDTH = 4, //width of aux line (must be >= 4) 
+                   WB2_ADDR_BITS = 7, //width of 2nd wishbone address bus 
+                   WB2_DATA_BITS = 32, //width of 2nd wishbone data bus 
+                   DUAL_RANK_DIMM = 0, // enable dual rank DIMM (1 =  enable, 0 = disable)
+    // DDR3 timing parameter values
+    parameter      SPEED_BIN = 3, // 0 = Use top-level parameters , 1 = DDR3-1066 (7-7-7) , 2 = DR3-1333 (9-9-9) , 3 = DDR3-1600 (11-11-11)
+                   SDRAM_CAPACITY = 5, // 0 = 256Mb, 1 = 512Mb, 2 = 1Gb, 3 = 2Gb, 4 = 4Gb, 5 = 8Gb, 6 = 16Gb
+                   TRCD = 13_750, // ps Active to Read/Write command time (only used if SPEED_BIN = 0)
+                   TRP = 13_750, // ps Precharge command period (only used if SPEED_BIN = 0)
+                   TRAS = 35_000, // ps ACT to PRE command period (only used if SPEED_BIN = 0)
+    parameter[0:0] MICRON_SIM = 0, //enable faster simulation for micron ddr3 model (shorten POWER_ON_RESET_HIGH and INITIAL_CKE_LOW)
+                   ODELAY_SUPPORTED = 0, //set to 1 when ODELAYE2 is supported
+                   SECOND_WISHBONE = 0, //set to 1 if 2nd wishbone for debugging is needed 
+                   DLL_OFF = 0, // 1 = DLL off for low frequency ddr3 clock (< 125MHz)
+                   WB_ERROR = 0, // set to 1 to support Wishbone error (asserts at ECC double bit error)
+    parameter[1:0] BIST_MODE = 1, // 0 = No BIST, 1 = run through all address space ONCE , 2 = run through all address space for every test (burst w/r, random w/r, alternating r/w)
+    parameter[0:0] BIST_TEST_DATAMASK = 1, // 1 = include per-byte DM writes in BIST, 0 = all-byte writes only
+    parameter[1:0] ECC_ENABLE = 0, // set to 1 or 2 to add ECC (1 = Side-band ECC per burst, 2 = Side-band ECC per 8 bursts , 3 = Inline ECC ) 
+    parameter[1:0] DIC = 2'b00, //Output Driver Impedance Control (2'b00 = RZQ/6, 2'b01 = RZQ/7, RZQ = 240ohms) (only change when you know what you are doing)
+    parameter[2:0] RTT_NOM = 3'b011, //RTT Nominal (3'b000 = disabled, 3'b001 = RZQ/4, 3'b010 = RZQ/2 , 3'b011 = RZQ/6, RZQ = 240ohms)  (only change when you know what you are doing)
+    parameter[1:0] SELF_REFRESH = 2'b00, // 0 = use i_user_self_refresh input, 1 = Self-refresh mode is enabled after 64 controller clock cycles of no requests, 2 = 128 cycles, 3 = 256 cycles
+    parameter // The next parameters act more like a localparam (since user does not have to set this manually) but was added here to simplify port declaration
+                DQ_BITS = 8,  //device width (fixed to 8, if DDR3 is x16 then BYTE_LANES will be 2 while )
+                serdes_ratio = 4, // this controller is fixed as a 4:1 memory controller (CONTROLLER_CLK_PERIOD/DDR3_CLK_PERIOD = 4)
+                wb_addr_bits = ROW_BITS + COL_BITS + BA_BITS - $clog2(serdes_ratio*2) + DUAL_RANK_DIMM,
+                wb_data_bits = DQ_BITS*BYTE_LANES*serdes_ratio*2,
+                wb_sel_bits = wb_data_bits / 8,
+                wb2_sel_bits = WB2_DATA_BITS / 8,
+                //4 is the width of a single ddr3 command {cs_n, ras_n, cas_n, we_n} plus 3 (ck_en, odt, reset_n) plus bank bits plus row bits
+                cmd_len = 4 + 3 + BA_BITS + ROW_BITS + 2*DUAL_RANK_DIMM
+    ) 
+    (
+        input wire i_controller_clk, i_ddr3_clk, i_ref_clk, //i_controller_clk = CONTROLLER_CLK_PERIOD, i_ddr3_clk = DDR3_CLK_PERIOD, i_ref_clk = 200MHz
+        input wire i_ddr3_clk_90, //required only when ODELAY_SUPPORTED is zero
+        input wire i_rst_n,
+        //
+        // Wishbone inputs
+        input wire i_wb_cyc, //bus cycle active (1 = normal operation, 0 = all ongoing transaction are to be cancelled)
+        input wire i_wb_stb, //request a transfer
+        input wire i_wb_we, //write-enable (1 = write, 0 = read)
+        input wire[wb_addr_bits - 1:0] i_wb_addr, //burst-addressable {row,bank,col} 
+        input wire[wb_data_bits - 1:0] i_wb_data, //write data, for a 4:1 controller data width is 8 times the number of pins on the device
+        input wire[wb_sel_bits - 1:0] i_wb_sel, //byte strobe for write (1 = write the byte)
+        input wire[AUX_WIDTH - 1:0]  i_aux, //for AXI-interface compatibility (given upon strobe)
+        // Wishbone outputs
+        output wire o_wb_stall, //1 = busy, cannot accept requests
+        output wire o_wb_ack, //1 = read/write request has completed
+        output wire o_wb_err, //1 = Error due to ECC double bit error (fixed to 0 if WB_ERROR = 0)
+        output wire[wb_data_bits - 1:0] o_wb_data, //read data, for a 4:1 controller data width is 8 times the number of pins on the device
+        output wire[AUX_WIDTH - 1:0]  o_aux, //for AXI-interface compatibility (given upon strobe)
+        //
+        // Wishbone 2 (PHY) inputs
+        input wire i_wb2_cyc, //bus cycle active (1 = normal operation, 0 = all ongoing transaction are to be cancelled)
+        input wire i_wb2_stb, //request a transfer
+        input wire i_wb2_we, //write-enable (1 = write, 0 = read)
+        input wire[WB2_ADDR_BITS - 1:0] i_wb2_addr, // memory-mapped register to be accessed
+        input wire[WB2_DATA_BITS - 1:0] i_wb2_data, //write data
+        input wire[wb2_sel_bits - 1:0] i_wb2_sel, //byte strobe for write (1 = write the byte)
+        // Wishbone 2 (Controller) outputs
+        output wire o_wb2_stall, //1 = busy, cannot accept requests
+        output wire o_wb2_ack, //1 = read/write request has completed
+        output wire[WB2_DATA_BITS - 1:0] o_wb2_data, //read data
+        //
+        // DDR3 I/O Interface
+        output wire[DUAL_RANK_DIMM:0] o_ddr3_clk_p, o_ddr3_clk_n,
+        output wire o_ddr3_reset_n,
+        output wire[DUAL_RANK_DIMM:0] o_ddr3_cke, // CKE
+        output wire[DUAL_RANK_DIMM:0] o_ddr3_cs_n, // chip select signal
+        output wire o_ddr3_ras_n, // RAS#
+        output wire o_ddr3_cas_n, // CAS#
+        output wire o_ddr3_we_n, // WE#
+        output wire[ROW_BITS-1:0] o_ddr3_addr,
+        output wire[BA_BITS-1:0] o_ddr3_ba_addr,
+        inout wire[(DQ_BITS*BYTE_LANES)-1:0] io_ddr3_dq,
+        inout wire[BYTE_LANES-1:0] io_ddr3_dqs, io_ddr3_dqs_n,
+        output wire[BYTE_LANES-1:0] o_ddr3_dm,
+        output wire[DUAL_RANK_DIMM:0] o_ddr3_odt, // on-die termination
+        //
+        // Done Calibration pin
+        output wire o_calib_complete,
+        // Debug outputs
+        output wire[31:0] o_debug1,
+//        output wire[31:0] o_debug2,
+//        output wire[31:0] o_debug3,
+//        output wire[(DQ_BITS*BYTE_LANES)/8-1:0] o_ddr3_debug_read_dqs_p,
+//        output wire[(DQ_BITS*BYTE_LANES)/8-1:0] o_ddr3_debug_read_dqs_n
+        // 
+        // User enabled self-refresh
+        input wire i_user_self_refresh,
+        output wire uart_tx
+    );
+    
+// Instantiation Template (DEFAULT VALUE IS FOR ARTY S7)
+/*
+// DDR3 Controller 
+ddr3_top #(
+    .CONTROLLER_CLK_PERIOD(12_000), //ps, clock period of the controller interface
+    .DDR3_CLK_PERIOD(3_000), //ps, clock period of the DDR3 RAM device (must be 1/4 of the CONTROLLER_CLK_PERIOD) 
+    .ROW_BITS(14), //width of row address
+    .COL_BITS(10), //width of column address
+    .BA_BITS(3), //width of bank address
+    .BYTE_LANES(2), //number of byte lanes of DDR3 RAM
+    .AUX_WIDTH(4), //width of aux line (must be >= 4) 
+    .MICRON_SIM(0), //enable faster simulation for micron ddr3 model (shorten POWER_ON_RESET_HIGH and INITIAL_CKE_LOW)
+    .ODELAY_SUPPORTED(0), //set to 1 if ODELAYE2 is supported
+    .SECOND_WISHBONE(0), //set to 1 if 2nd wishbone for debugging is needed 
+    .ECC_ENABLE(0), // set to 1 or 2 to add ECC (1 = Side-band ECC per burst, 2 = Side-band ECC per 8 bursts , 3 = Inline ECC ) 
+    .WB_ERROR(0), // set to 1 to support Wishbone error (asserts at ECC double bit error)
+    ) ddr3_top
+    (
+        //clock and reset
+        .i_controller_clk(i_controller_clk),
+        .i_ddr3_clk(i_ddr3_clk), //i_controller_clk has period of CONTROLLER_CLK_PERIOD, i_ddr3_clk has period of DDR3_CLK_PERIOD 
+        .i_ref_clk(i_ref_clk), // usually set to 200 MHz 
+        .i_ddr3_clk_90(i_ddr3_clk_90), //90 degree phase shifted version i_ddr3_clk (required only when ODELAY_SUPPORTED is zero)
+        .i_rst_n(!i_rst && clk_locked), 
+        //
+        // Wishbone inputs
+        .i_wb_cyc(1), //bus cycle active (1 = normal operation, 0 = all ongoing transaction are to be cancelled)
+        .i_wb_stb(i_wb_stb), //request a transfer
+        .i_wb_we(i_wb_we), //write-enable (1 = write, 0 = read)
+        .i_wb_addr(i_wb_addr), //burst-addressable {row,bank,col} 
+        .i_wb_data(i_wb_data), //write data, for a 4:1 controller data width is 8 times the number of pins on the device
+        .i_wb_sel(16'hffff), //byte strobe for write (1 = write the byte)
+        .i_aux(i_wb_we), //for AXI-interface compatibility (given upon strobe)
+        // Wishbone outputs
+        .o_wb_stall(o_wb_stall), //1 = busy, cannot accept requests
+        .o_wb_ack(o_wb_ack), //1 = read/write request has completed
+        .o_wb_err(o_wb_err), //1 = Error due to ECC double bit error (fixed to 0 if WB_ERROR = 0)
+        .o_wb_data(o_wb_data), //read data, for a 4:1 controller data width is 8 times the number of pins on the device
+        .o_aux(o_aux),
+        //
+        // Wishbone 2 (PHY) inputs
+        .i_wb2_cyc(0), //bus cycle active (1 = normal operation, 0 = all ongoing transaction are to be cancelled)
+        .i_wb2_stb(0), //request a transfer
+        .i_wb2_we(0), //write-enable (1 = write, 0 = read)
+        .i_wb2_addr(0), //burst-addressable {row,bank,col} 
+        .i_wb2_data(0), //write data, for a 4:1 controller data width is 8 times the number of pins on the device
+        .i_wb2_sel(0), //byte strobe for write (1 = write the byte)
+        // Wishbone 2 (Controller) outputs
+        .o_wb2_stall(), //1 = busy, cannot accept requests
+        .o_wb2_ack(), //1 = read/write request has completed
+        .o_wb2_data(), //read data, for a 4:1 controller data width is 8 times the number of pins on the device
+        //
+        // DDR3 I/O Interface
+        .o_ddr3_clk_p(ddr3_clk_p), 
+        .o_ddr3_clk_n(ddr3_clk_n),
+        .o_ddr3_reset_n(ddr3_reset_n),
+        .o_ddr3_cke(ddr3_cke), 
+        .o_ddr3_cs_n(ddr3_cs_n), // width = number of DDR3 ranks
+        .o_ddr3_ras_n(ddr3_ras_n), 
+        .o_ddr3_cas_n(ddr3_cas_n), 
+        .o_ddr3_we_n(ddr3_we_n), 
+        .o_ddr3_addr(ddr3_addr), // width = ROW_BITS
+        .o_ddr3_ba_addr(ddr3_ba), // width = BA_BITS
+        .io_ddr3_dq(ddr3_dq), // width = BYTE_LANES*8
+        .io_ddr3_dqs(ddr3_dqs_p), // width = BYTE_LANES
+        .io_ddr3_dqs_n(ddr3_dqs_n), // width = BYTE_LANES
+        .o_ddr3_dm(ddr3_dm), // width = BYTE_LANES
+        .o_ddr3_odt(ddr3_odt),
+        // Debug outputs
+        .o_debug1(),
+        ////////////////////////////////////
+    );
+*/
+    
+    // Wire connections between controller and phy
+    wire[cmd_len*serdes_ratio-1:0] cmd;
+    wire dqs_tri_control, dq_tri_control;
+    wire toggle_dqs;
+    wire[wb_data_bits-1:0] data;
+    wire[wb_sel_bits-1:0] dm;
+    wire[BYTE_LANES-1:0] bitslip;
+    wire[DQ_BITS*BYTE_LANES*8-1:0] iserdes_data;
+    wire[BYTE_LANES*8-1:0] iserdes_dqs;
+    wire[BYTE_LANES*8-1:0] iserdes_bitslip_reference;
+    wire idelayctrl_rdy;
+    wire[4:0] odelay_data_cntvaluein, odelay_dqs_cntvaluein;
+    wire[4:0] idelay_data_cntvaluein, idelay_dqs_cntvaluein;
+    wire[BYTE_LANES-1:0] odelay_data_ld, odelay_dqs_ld;
+    wire[BYTE_LANES-1:0] idelay_data_ld, idelay_dqs_ld;
+    wire write_leveling_calib;
+    wire reset;
+    
+    // logic for self-refresh
+    reg[8:0] refresh_counter = 0;
+    reg user_self_refresh;
+    // refresh counter 
+    always @(posedge i_controller_clk) begin
+        if(i_wb_stb && i_wb_cyc) begin // if there is Wishbone request, then reset counter
+            refresh_counter <= 0;
+        end
+        else if(!o_wb_stall || user_self_refresh) begin // if no request (but not stalled) OR already on self-refresh, then increment counter
+            refresh_counter <= refresh_counter + 1;
+        end
+    end
+    // choose self-refresh options
+    always @* begin
+        case(SELF_REFRESH) 
+            2'b00: user_self_refresh = i_user_self_refresh; // use input i_user_self_refresh (high = enter self-refresh, low = exit self-refresh)
+            2'b01: user_self_refresh = refresh_counter[6];  // Self-refresh mode is enabled after 64 controller clock cycles of no requests, then exit Self-refresh after another 64 controller clk cycles
+            2'b10: user_self_refresh = refresh_counter[7];  // Self-refresh mode is enabled after 128 controller clock cycles of no requests, then exit Self-refresh after another 128 controller clk cycles
+            2'b11: user_self_refresh = refresh_counter[8];  // Self-refresh mode is enabled after 256 controller clock cycles of no requests, then exit Self-refresh after another 256 controller clk cycles
+        endcase
+    end
+    
+
+    
+    //module instantiations
+    ddr3_controller #(
+            .CONTROLLER_CLK_PERIOD(CONTROLLER_CLK_PERIOD), //ps, clock period of the controller interface
+            .DDR3_CLK_PERIOD(DDR3_CLK_PERIOD), //ps, clock period of the DDR3 RAM device (must be 1/4 of the CONTROLLER_CLK_PERIOD) 
+            .ROW_BITS(ROW_BITS), //width of row address
+            .COL_BITS(COL_BITS), //width of column address
+            .BA_BITS(BA_BITS), //width of bank address
+            .DQ_BITS(DQ_BITS),  //width of DQ
+            .LANES(BYTE_LANES), // byte lanes
+            .AUX_WIDTH(AUX_WIDTH), //width of aux line (must be >= 4) 
+            .WB2_ADDR_BITS(WB2_ADDR_BITS), //width of 2nd wishbone address bus 
+            .WB2_DATA_BITS(WB2_DATA_BITS),  //width of 2nd wishbone data bus
+            .MICRON_SIM(MICRON_SIM), //simulation for micron ddr3 model (shorten POWER_ON_RESET_HIGH and INITIAL_CKE_LOW)
+            .ODELAY_SUPPORTED(ODELAY_SUPPORTED),  //set to 1 when ODELAYE2 is supported
+            .SECOND_WISHBONE(SECOND_WISHBONE), //set to 1 if 2nd wishbone is needed 
+            .ECC_ENABLE(ECC_ENABLE), // set to 1 or 2 to add ECC (1 = Side-band ECC per burst, 2 = Side-band ECC per 8 bursts , 3 = Inline ECC ) 
+            .DLL_OFF(DLL_OFF), // 1 = DLL off for low frequency ddr3 clock (< 125MHz)
+            .WB_ERROR(WB_ERROR), // set to 1 to support Wishbone error (asserts at ECC double bit error)
+            .BIST_MODE(BIST_MODE), // 0 = No BIST, 1 = run through all address space ONCE , 2 = run through all address space for every test (burst w/r, random w/r, alternating r/w)
+            .BIST_TEST_DATAMASK(BIST_TEST_DATAMASK), // 1 = include per-byte DM writes in BIST, 0 = all-byte writes only
+            .DIC(DIC), //Output Driver Impedance Control (2'b00 = RZQ/6, 2'b01 = RZQ/7, RZQ = 240ohms)
+            .RTT_NOM(RTT_NOM), //RTT Nominal (3'b000 = disabled, 3'b001 = RZQ/4, 3'b010 = RZQ/2 , 3'b011 = RZQ/6, RZQ = 240ohms)
+            .DUAL_RANK_DIMM(DUAL_RANK_DIMM), // enable dual rank DIMM (1 =  enable, 0 = disable)
+            .SPEED_BIN(SPEED_BIN), // 0 = Use top-level parameters , 1 = DDR3-1066 (7-7-7) , 2 = DR3-1333 (9-9-9) , 3 = DDR3-1600 (11-11-11)
+            .SDRAM_CAPACITY(SDRAM_CAPACITY), // 0 = 256Mb, 1 = 512Mb, 2 = 1Gb, 3 = 2Gb, 4 = 4Gb, 5 = 8Gb, 6 = 16Gb
+            .TRCD(TRCD), // ps Active to Read/Write command time (only used if SPEED_BIN = 0)
+            .TRP(TRP), // ps Precharge command period (only used if SPEED_BIN = 0)
+            .TRAS(TRAS) // ps ACT to PRE command period (only used if SPEED_BIN = 0)
+        ) ddr3_controller_inst (
+            .i_controller_clk(i_controller_clk), //i_controller_clk has period of CONTROLLER_CLK_PERIOD 
+            .i_rst_n(i_rst_n), //200MHz input clock
+            // Wishbone inputs
+            .i_wb_cyc(i_wb_cyc), //bus cycle active (1 = normal operation, 0 = all ongoing transaction are to be cancelled)
+            .i_wb_stb(i_wb_stb), //request a transfer
+            .i_wb_we(i_wb_we), //write-enable (1 = write, 0 = read)
+            .i_wb_addr(i_wb_addr), //burst-addressable {row,bank,col} 
+            .i_wb_data(i_wb_data), //write data, for a 4:1 controller data width is 8 times the number of pins on the device
+            .i_wb_sel(i_wb_sel), //byte strobe for write (1 = write the byte)
+            .i_aux(i_aux), //for AXI-interface compatibility (given upon strobe)
+            // Wishbone outputs
+            .o_wb_stall(o_wb_stall), //1 = busy, cannot accept requests
+            .o_wb_ack(o_wb_ack), //1 = read/write request has completed
+            .o_wb_err(o_wb_err), //1 = Error due to ECC double bit error (fixed to 0 if WB_ERROR = 0)
+            .o_wb_data(o_wb_data), //read data, for a 4:1 controller data width is 8 times the number of pins on the device
+            .o_aux(o_aux), //for AXI-interface compatibility (returned upon ack)
+            // Wishbone 2 (PHY) inputs
+            .i_wb2_cyc(i_wb2_cyc), //bus cycle active (1 = normal operation, 0 = all ongoing transaction are to be cancelled)
+            .i_wb2_stb(i_wb2_stb), //request a transfer
+            .i_wb2_we(i_wb2_we), //write-enable (1 = write, 0 = read)
+            .i_wb2_addr(i_wb2_addr), // memory-mapped register to be accessed 
+            .i_wb2_data(i_wb2_data), //write data
+            .i_wb2_sel(i_wb2_sel), //byte strobe for write (1 = write the byte)
+            // Wishbone 2 (Controller) outputs
+            .o_wb2_stall(o_wb2_stall), //1 = busy, cannot accept requests
+            .o_wb2_ack(o_wb2_ack), //1 = read/write request has completed
+            .o_wb2_data(o_wb2_data), //read data
+            //
+            // PHY interface
+            .i_phy_iserdes_data(iserdes_data),
+            .i_phy_iserdes_dqs(iserdes_dqs),
+            .i_phy_iserdes_bitslip_reference(iserdes_bitslip_reference),
+            .i_phy_idelayctrl_rdy(idelayctrl_rdy),
+            .o_phy_cmd(cmd),
+            .o_phy_dqs_tri_control(dqs_tri_control), 
+            .o_phy_dq_tri_control(dq_tri_control),
+            .o_phy_toggle_dqs(toggle_dqs),
+            .o_phy_data(data),
+            .o_phy_dm(dm),
+            .o_phy_odelay_data_cntvaluein(odelay_data_cntvaluein),
+            .o_phy_odelay_dqs_cntvaluein(odelay_dqs_cntvaluein),
+            .o_phy_idelay_data_cntvaluein(idelay_data_cntvaluein), 
+            .o_phy_idelay_dqs_cntvaluein(idelay_dqs_cntvaluein),
+            .o_phy_odelay_data_ld(odelay_data_ld),
+            .o_phy_odelay_dqs_ld(odelay_dqs_ld),
+            .o_phy_idelay_data_ld(idelay_data_ld), 
+            .o_phy_idelay_dqs_ld(idelay_dqs_ld),
+            .o_phy_bitslip(bitslip),
+            .o_phy_write_leveling_calib(write_leveling_calib),
+            .o_phy_reset(reset),
+            // Done Calibration pin
+            .o_calib_complete(o_calib_complete),
+            // Debug outputs
+            .o_debug1(o_debug1),
+//            .o_debug2(o_debug2),
+//            .o_debug3(o_debug3)
+            // User enabled self-refresh
+            .i_user_self_refresh(user_self_refresh),
+            .uart_tx(uart_tx)
+        );
+    `ifndef LATTICE_ECP5_PHY // XILINX PHY
+        ddr3_phy #(
+                .ROW_BITS(ROW_BITS), //width of row address
+                .BA_BITS(BA_BITS), //width of bank address
+                .DQ_BITS(DQ_BITS),  //width of DQ
+                .LANES(BYTE_LANES), //8 lanes of DQ
+                .CONTROLLER_CLK_PERIOD(CONTROLLER_CLK_PERIOD), //ps, period of clock input to this DDR3 controller module
+                .DDR3_CLK_PERIOD(DDR3_CLK_PERIOD), //ps, period of clock input to DDR3 RAM device 
+                .ODELAY_SUPPORTED(ODELAY_SUPPORTED), //set to 1 when ODELAYE2 is supported
+                .DUAL_RANK_DIMM(DUAL_RANK_DIMM) // enable dual rank DIMM (1 =  enable, 0 = disable)
+            ) ddr3_phy_inst (
+                .i_controller_clk(i_controller_clk), 
+                .i_ddr3_clk(i_ddr3_clk),
+                .i_ref_clk(i_ref_clk),
+                .i_ddr3_clk_90(i_ddr3_clk_90), 
+                .i_rst_n(i_rst_n),
+                // Controller Interface
+                .i_controller_reset(reset),
+                .i_controller_cmd(cmd),
+                .i_controller_dqs_tri_control(dqs_tri_control), 
+                .i_controller_dq_tri_control(dq_tri_control),
+                .i_controller_toggle_dqs(toggle_dqs),
+                .i_controller_data(data),
+                .i_controller_dm(dm),
+                .i_controller_odelay_data_cntvaluein(odelay_data_cntvaluein),
+                .i_controller_odelay_dqs_cntvaluein(odelay_dqs_cntvaluein),
+                .i_controller_idelay_data_cntvaluein(idelay_data_cntvaluein),
+                .i_controller_idelay_dqs_cntvaluein(idelay_dqs_cntvaluein),
+                .i_controller_odelay_data_ld(odelay_data_ld), 
+                .i_controller_odelay_dqs_ld(odelay_dqs_ld),
+                .i_controller_idelay_data_ld(idelay_data_ld), 
+                .i_controller_idelay_dqs_ld(idelay_dqs_ld),
+                .i_controller_bitslip(bitslip),
+                .i_controller_write_leveling_calib(write_leveling_calib),
+                .o_controller_iserdes_data(iserdes_data),
+                .o_controller_iserdes_dqs(iserdes_dqs),
+                .o_controller_iserdes_bitslip_reference(iserdes_bitslip_reference),
+                .o_controller_idelayctrl_rdy(idelayctrl_rdy),
+                // DDR3 I/O Interface
+                .o_ddr3_clk_p(o_ddr3_clk_p),
+                .o_ddr3_clk_n(o_ddr3_clk_n),
+                .o_ddr3_reset_n(o_ddr3_reset_n),
+                .o_ddr3_cke(o_ddr3_cke), // CKE
+                .o_ddr3_cs_n(o_ddr3_cs_n), // chip select signal
+                .o_ddr3_ras_n(o_ddr3_ras_n), // RAS#
+                .o_ddr3_cas_n(o_ddr3_cas_n), // CAS#
+                .o_ddr3_we_n(o_ddr3_we_n), // WE#
+                .o_ddr3_addr(o_ddr3_addr),
+                .o_ddr3_ba_addr(o_ddr3_ba_addr),
+                .io_ddr3_dq(io_ddr3_dq),
+                .io_ddr3_dqs(io_ddr3_dqs),
+                .io_ddr3_dqs_n(io_ddr3_dqs_n),
+                .o_ddr3_dm(o_ddr3_dm),
+                .o_ddr3_odt(o_ddr3_odt), // on-die termination
+                .o_ddr3_debug_read_dqs_p(/*o_ddr3_debug_read_dqs_p*/),
+                .o_ddr3_debug_read_dqs_n(/*o_ddr3_debug_read_dqs_n*/)
+            );
+    `else // LATTICE ECP5 PHY
+        ddr3_phy_ecp5 #(
+                .ROW_BITS(ROW_BITS), //width of row address
+                .BA_BITS(BA_BITS), //width of bank address
+                .DQ_BITS(DQ_BITS),  //width of DQ
+                .LANES(BYTE_LANES), //8 lanes of DQ
+                .CONTROLLER_CLK_PERIOD(CONTROLLER_CLK_PERIOD) //ps, period of clock input to this DDR3 controller module
+            ) ddr3_phy_inst (
+                .i_controller_clk(i_controller_clk), 
+                .i_ddr3_clk(i_ddr3_clk),
+                .i_ref_clk(i_ref_clk),
+                .i_ddr3_clk_90(i_ddr3_clk_90), 
+                .i_rst_n(i_rst_n),
+                // Controller Interface
+                .i_controller_reset(reset),
+                .i_controller_cmd(cmd),
+                .i_controller_dqs_tri_control(dqs_tri_control), 
+                .i_controller_dq_tri_control(dq_tri_control),
+                .i_controller_toggle_dqs(toggle_dqs),
+                .i_controller_data(data),
+                .i_controller_dm(dm),
+                .i_controller_odelay_data_cntvaluein(odelay_data_cntvaluein),
+                .i_controller_odelay_dqs_cntvaluein(odelay_dqs_cntvaluein),
+                .i_controller_idelay_data_cntvaluein(idelay_data_cntvaluein),
+                .i_controller_idelay_dqs_cntvaluein(idelay_dqs_cntvaluein),
+                .i_controller_odelay_data_ld(odelay_data_ld), 
+                .i_controller_odelay_dqs_ld(odelay_dqs_ld),
+                .i_controller_idelay_data_ld(idelay_data_ld), 
+                .i_controller_idelay_dqs_ld(idelay_dqs_ld),
+                .i_controller_bitslip(bitslip),
+                .i_controller_write_leveling_calib(write_leveling_calib),
+                .o_controller_iserdes_data(iserdes_data),
+                .o_controller_iserdes_dqs(iserdes_dqs),
+                .o_controller_iserdes_bitslip_reference(iserdes_bitslip_reference),
+                .o_controller_idelayctrl_rdy(idelayctrl_rdy),
+                // DDR3 I/O Interface
+                .o_ddr3_clk_p(o_ddr3_clk_p),
+                .o_ddr3_clk_n(o_ddr3_clk_n),
+                .o_ddr3_reset_n(o_ddr3_reset_n),
+                .o_ddr3_cke(o_ddr3_cke), // CKE
+                .o_ddr3_cs_n(o_ddr3_cs_n), // chip select signal
+                .o_ddr3_ras_n(o_ddr3_ras_n), // RAS#
+                .o_ddr3_cas_n(o_ddr3_cas_n), // CAS#
+                .o_ddr3_we_n(o_ddr3_we_n), // WE#
+                .o_ddr3_addr(o_ddr3_addr),
+                .o_ddr3_ba_addr(o_ddr3_ba_addr),
+                .io_ddr3_dq(io_ddr3_dq),
+                .io_ddr3_dqs(io_ddr3_dqs),
+                .io_ddr3_dqs_n(io_ddr3_dqs_n),
+                .o_ddr3_dm(o_ddr3_dm),
+                .o_ddr3_odt(o_ddr3_odt), // on-die termination
+                .o_ddr3_debug_read_dqs_p(/*o_ddr3_debug_read_dqs_p*/),
+                .o_ddr3_debug_read_dqs_n(/*o_ddr3_debug_read_dqs_n*/)
+            );
+    `endif 
+
+        // // display value of parameters for easy debugging
+        // initial begin
+        //     $display("\nDDR3 TOP PARAMETERS:\n-----------------------------");
+        //     $display("CONTROLLER_CLK_PERIOD = %0d", CONTROLLER_CLK_PERIOD);
+        //     $display("DDR3_CLK_PERIOD = %0d", DDR3_CLK_PERIOD);
+        //     $display("ROW_BITS = %0d", ROW_BITS);
+        //     $display("COL_BITS = %0d", COL_BITS);
+        //     $display("BA_BITS = %0d", BA_BITS);
+        //     $display("BYTE_LANES = %0d", BYTE_LANES);
+        //     $display("AUX_WIDTH = %0d", AUX_WIDTH);
+        //     $display("WB2_ADDR_BITS = %0d", WB2_ADDR_BITS);
+        //     $display("WB2_DATA_BITS = %0d", WB2_DATA_BITS);
+        //     $display("MICRON_SIM = %0d", MICRON_SIM);
+        //     $display("ODELAY_SUPPORTED = %0d", ODELAY_SUPPORTED);
+        //     $display("SECOND_WISHBONE = %0d", SECOND_WISHBONE);
+        //     $display("WB_ERROR = %0d", WB_ERROR);
+        //     $display("BIST_MODE = %0d", BIST_MODE);
+        //     $display("ECC_ENABLE = %0d", ECC_ENABLE);
+        //     $display("DIC = %0d", DIC);
+        //     $display("RTT_NOM = %0d", RTT_NOM);
+        //     $display("SELF_REFRESH = %0d", SELF_REFRESH);
+        //     $display("DUAL_RANK_DIMM = %0d", DUAL_RANK_DIMM);
+        //     $display("End of DDR3 TOP PARAMETERS\n-----------------------------");
+        // end
+
+endmodule

AngeloJacobo_UberDDR3/example_demo/arty_s7/uart_rx.v

@@ -0,0 +1,207 @@
+
+// 
+// Module: uart_rx 
+// 
+// Notes:
+// - UART reciever module.
+//
+
+module uart_rx(
+input  wire       clk          , // Top level system clock input.
+input  wire       resetn       , // Asynchronous active low reset.
+input  wire       uart_rxd     , // UART Recieve pin.
+input  wire       uart_rx_en   , // Recieve enable
+output wire       uart_rx_break, // Did we get a BREAK message?
+output wire       uart_rx_valid, // Valid data recieved and available.
+output reg  [PAYLOAD_BITS-1:0] uart_rx_data   // The recieved data.
+);
+
+// --------------------------------------------------------------------------- 
+// External parameters.
+// 
+
+//
+// Input bit rate of the UART line.
+parameter   BIT_RATE        = 9600; // bits / sec
+localparam  BIT_P           = 1_000_000_000 * 1/BIT_RATE; // nanoseconds
+
+//
+// Clock frequency in hertz.
+parameter   CLK_HZ          =    50_000_000;
+localparam  CLK_P           = 1_000_000_000 * 1/CLK_HZ; // nanoseconds
+
+//
+// Number of data bits recieved per UART packet.
+parameter   PAYLOAD_BITS    = 8;
+
+//
+// Number of stop bits indicating the end of a packet.
+parameter   STOP_BITS       = 1;
+
+// -------------------------------------------------------------------------- 
+// Internal parameters.
+// 
+
+//
+// Number of clock cycles per uart bit.
+localparam       CYCLES_PER_BIT     = BIT_P / CLK_P;
+
+//
+// Size of the registers which store sample counts and bit durations.
+localparam       COUNT_REG_LEN      = 1+$clog2(CYCLES_PER_BIT);
+
+// -------------------------------------------------------------------------- 
+// Internal registers.
+// 
+
+//
+// Internally latched value of the uart_rxd line. Helps break long timing
+// paths from input pins into the logic.
+reg rxd_reg;
+reg rxd_reg_0;
+
+//
+// Storage for the recieved serial data.
+reg [PAYLOAD_BITS-1:0] recieved_data;
+
+//
+// Counter for the number of cycles over a packet bit.
+reg [COUNT_REG_LEN-1:0] cycle_counter;
+
+//
+// Counter for the number of recieved bits of the packet.
+reg [3:0] bit_counter;
+
+//
+// Sample of the UART input line whenever we are in the middle of a bit frame.
+reg bit_sample;
+
+//
+// Current and next states of the internal FSM.
+reg [2:0] fsm_state;
+reg [2:0] n_fsm_state;
+
+localparam FSM_IDLE = 0;
+localparam FSM_START= 1;
+localparam FSM_RECV = 2;
+localparam FSM_STOP = 3;
+
+// --------------------------------------------------------------------------- 
+// Output assignment
+// 
+
+assign uart_rx_break = uart_rx_valid && ~|recieved_data;
+assign uart_rx_valid = fsm_state == FSM_STOP && n_fsm_state == FSM_IDLE;
+
+always @(posedge clk) begin
+    if(!resetn) begin
+        uart_rx_data  <= {PAYLOAD_BITS{1'b0}};
+    end else if (fsm_state == FSM_STOP) begin
+        uart_rx_data  <= recieved_data;
+    end
+end
+
+// --------------------------------------------------------------------------- 
+// FSM next state selection.
+// 
+
+wire next_bit     = cycle_counter == CYCLES_PER_BIT ||
+                        fsm_state       == FSM_STOP && 
+                        cycle_counter   == CYCLES_PER_BIT/2;
+wire payload_done = bit_counter   == PAYLOAD_BITS  ;
+
+//
+// Handle picking the next state.
+always @(*) begin : p_n_fsm_state
+    case(fsm_state)
+        FSM_IDLE : n_fsm_state = rxd_reg      ? FSM_IDLE : FSM_START;
+        FSM_START: n_fsm_state = next_bit     ? FSM_RECV : FSM_START;
+        FSM_RECV : n_fsm_state = payload_done ? FSM_STOP : FSM_RECV ;
+        FSM_STOP : n_fsm_state = next_bit     ? FSM_IDLE : FSM_STOP ;
+        default  : n_fsm_state = FSM_IDLE;
+    endcase
+end
+
+// --------------------------------------------------------------------------- 
+// Internal register setting and re-setting.
+// 
+
+//
+// Handle updates to the recieved data register.
+integer i = 0;
+always @(posedge clk) begin : p_recieved_data
+    if(!resetn) begin
+        recieved_data <= {PAYLOAD_BITS{1'b0}};
+    end else if(fsm_state == FSM_IDLE             ) begin
+        recieved_data <= {PAYLOAD_BITS{1'b0}};
+    end else if(fsm_state == FSM_RECV && next_bit ) begin
+        recieved_data[PAYLOAD_BITS-1] <= bit_sample;
+        for ( i = PAYLOAD_BITS-2; i >= 0; i = i - 1) begin
+            recieved_data[i] <= recieved_data[i+1];
+        end
+    end
+end
+
+//
+// Increments the bit counter when recieving.
+always @(posedge clk) begin : p_bit_counter
+    if(!resetn) begin
+        bit_counter <= 4'b0;
+    end else if(fsm_state != FSM_RECV) begin
+        bit_counter <= {COUNT_REG_LEN{1'b0}};
+    end else if(fsm_state == FSM_RECV && next_bit) begin
+        bit_counter <= bit_counter + 1'b1;
+    end
+end
+
+//
+// Sample the recieved bit when in the middle of a bit frame.
+always @(posedge clk) begin : p_bit_sample
+    if(!resetn) begin
+        bit_sample <= 1'b0;
+    end else if (cycle_counter == CYCLES_PER_BIT/2) begin
+        bit_sample <= rxd_reg;
+    end
+end
+
+
+//
+// Increments the cycle counter when recieving.
+always @(posedge clk) begin : p_cycle_counter
+    if(!resetn) begin
+        cycle_counter <= {COUNT_REG_LEN{1'b0}};
+    end else if(next_bit) begin
+        cycle_counter <= {COUNT_REG_LEN{1'b0}};
+    end else if(fsm_state == FSM_START || 
+                fsm_state == FSM_RECV  || 
+                fsm_state == FSM_STOP   ) begin
+        cycle_counter <= cycle_counter + 1'b1;
+    end
+end
+
+
+//
+// Progresses the next FSM state.
+always @(posedge clk) begin : p_fsm_state
+    if(!resetn) begin
+        fsm_state <= FSM_IDLE;
+    end else begin
+        fsm_state <= n_fsm_state;
+    end
+end
+
+
+//
+// Responsible for updating the internal value of the rxd_reg.
+always @(posedge clk) begin : p_rxd_reg
+    if(!resetn) begin
+        rxd_reg     <= 1'b1;
+        rxd_reg_0   <= 1'b1;
+    end else if(uart_rx_en) begin
+        rxd_reg     <= rxd_reg_0;
+        rxd_reg_0   <= uart_rxd;
+    end
+end
+
+
+endmodule

AngeloJacobo_UberDDR3/example_demo/arty_s7/uart_tx.v

@@ -0,0 +1,187 @@
+
+
+// 
+// Module: uart_tx 
+// 
+// Notes:
+// - UART transmitter module.
+//
+
+module uart_tx(
+input  wire         clk         , // Top level system clock input.
+input  wire         resetn      , // Asynchronous active low reset.
+output wire         uart_txd    , // UART transmit pin.
+output wire         uart_tx_busy, // Module busy sending previous item.
+input  wire         uart_tx_en  , // Send the data on uart_tx_data
+input  wire [PAYLOAD_BITS-1:0]   uart_tx_data  // The data to be sent
+);
+
+// --------------------------------------------------------------------------- 
+// External parameters.
+// 
+
+//
+// Input bit rate of the UART line.
+parameter   BIT_RATE        = 9600; // bits / sec
+localparam  BIT_P           = 1_000_000_000 * 1/BIT_RATE; // nanoseconds
+
+//
+// Clock frequency in hertz.
+parameter   CLK_HZ          =    50_000_000;
+localparam  CLK_P           = 1_000_000_000 * 1/CLK_HZ; // nanoseconds
+
+//
+// Number of data bits recieved per UART packet.
+parameter   PAYLOAD_BITS    = 8;
+
+//
+// Number of stop bits indicating the end of a packet.
+parameter   STOP_BITS       = 1;
+
+// --------------------------------------------------------------------------- 
+// Internal parameters.
+// 
+
+//
+// Number of clock cycles per uart bit.
+localparam       CYCLES_PER_BIT     = BIT_P / CLK_P;
+
+//
+// Size of the registers which store sample counts and bit durations.
+localparam       COUNT_REG_LEN      = 1+$clog2(CYCLES_PER_BIT);
+
+// --------------------------------------------------------------------------- 
+// Internal registers.
+// 
+
+//
+// Internally latched value of the uart_txd line. Helps break long timing
+// paths from the logic to the output pins.
+reg txd_reg;
+
+//
+// Storage for the serial data to be sent.
+reg [PAYLOAD_BITS-1:0] data_to_send;
+
+//
+// Counter for the number of cycles over a packet bit.
+reg [COUNT_REG_LEN-1:0] cycle_counter;
+
+//
+// Counter for the number of sent bits of the packet.
+reg [3:0] bit_counter;
+
+//
+// Current and next states of the internal FSM.
+reg [2:0] fsm_state;
+reg [2:0] n_fsm_state;
+
+localparam FSM_IDLE = 0;
+localparam FSM_START= 1;
+localparam FSM_SEND = 2;
+localparam FSM_STOP = 3;
+
+
+// --------------------------------------------------------------------------- 
+// FSM next state selection.
+// 
+
+assign uart_tx_busy = fsm_state != FSM_IDLE;
+assign uart_txd     = txd_reg;
+
+wire next_bit     = cycle_counter == CYCLES_PER_BIT;
+wire payload_done = bit_counter   == PAYLOAD_BITS  ;
+wire stop_done    = bit_counter   == STOP_BITS && fsm_state == FSM_STOP;
+
+//
+// Handle picking the next state.
+always @(*) begin : p_n_fsm_state
+    case(fsm_state)
+        FSM_IDLE : n_fsm_state = uart_tx_en   ? FSM_START: FSM_IDLE ;
+        FSM_START: n_fsm_state = next_bit     ? FSM_SEND : FSM_START;
+        FSM_SEND : n_fsm_state = payload_done ? FSM_STOP : FSM_SEND ;
+        FSM_STOP : n_fsm_state = stop_done    ? FSM_IDLE : FSM_STOP ;
+        default  : n_fsm_state = FSM_IDLE;
+    endcase
+end
+
+// --------------------------------------------------------------------------- 
+// Internal register setting and re-setting.
+// 
+
+//
+// Handle updates to the sent data register.
+integer i = 0;
+always @(posedge clk) begin : p_data_to_send
+    if(!resetn) begin
+        data_to_send <= {PAYLOAD_BITS{1'b0}};
+    end else if(fsm_state == FSM_IDLE && uart_tx_en) begin
+        data_to_send <= uart_tx_data;
+    end else if(fsm_state       == FSM_SEND       && next_bit ) begin
+        for ( i = PAYLOAD_BITS-2; i >= 0; i = i - 1) begin
+            data_to_send[i] <= data_to_send[i+1];
+        end
+    end
+end
+
+
+//
+// Increments the bit counter each time a new bit frame is sent.
+always @(posedge clk) begin : p_bit_counter
+    if(!resetn) begin
+        bit_counter <= 4'b0;
+    end else if(fsm_state != FSM_SEND && fsm_state != FSM_STOP) begin
+        bit_counter <= {COUNT_REG_LEN{1'b0}};
+    end else if(fsm_state == FSM_SEND && n_fsm_state == FSM_STOP) begin
+        bit_counter <= {COUNT_REG_LEN{1'b0}};
+    end else if(fsm_state == FSM_STOP&& next_bit) begin
+        bit_counter <= bit_counter + 1'b1;
+    end else if(fsm_state == FSM_SEND && next_bit) begin
+        bit_counter <= bit_counter + 1'b1;
+    end
+end
+
+
+//
+// Increments the cycle counter when sending.
+always @(posedge clk) begin : p_cycle_counter
+    if(!resetn) begin
+        cycle_counter <= {COUNT_REG_LEN{1'b0}};
+    end else if(next_bit) begin
+        cycle_counter <= {COUNT_REG_LEN{1'b0}};
+    end else if(fsm_state == FSM_START || 
+                fsm_state == FSM_SEND  || 
+                fsm_state == FSM_STOP   ) begin
+        cycle_counter <= cycle_counter + 1'b1;
+    end
+end
+
+
+//
+// Progresses the next FSM state.
+always @(posedge clk) begin : p_fsm_state
+    if(!resetn) begin
+        fsm_state <= FSM_IDLE;
+    end else begin
+        fsm_state <= n_fsm_state;
+    end
+end
+
+
+//
+// Responsible for updating the internal value of the txd_reg.
+always @(posedge clk) begin : p_txd_reg
+    if(!resetn) begin
+        txd_reg <= 1'b1;
+    end else if(fsm_state == FSM_IDLE) begin
+        txd_reg <= 1'b1;
+    end else if(fsm_state == FSM_START) begin
+        txd_reg <= 1'b0;
+    end else if(fsm_state == FSM_SEND) begin
+        txd_reg <= data_to_send[0];
+    end else if(fsm_state == FSM_STOP) begin
+        txd_reg <= 1'b1;
+    end
+end
+
+endmodule

AngeloJacobo_UberDDR3/example_demo/enclustra_kx2_st1/Makefile

@@ -0,0 +1,114 @@
+FAMILY  = kintex7
+PART    = xc7k160tffg676-2
+BOARD   = qmtechKintex7
+PROJECT = enclustra_ddr3
+CHIPDB  = ${KINTEX7_CHIPDB}
+ADDITIONAL_SOURCES = ../../rtl/ddr3_controller.v  ../../rtl/ddr3_phy.v  ../../rtl/ddr3_top.v  uart_rx.v  uart_tx.v clk_wiz.v 
+
+#############################################################################################
+NEXTPNR_XILINX_DIR ?= /snap/openxc7/current/opt/nextpnr-xilinx
+NEXTPNR_XILINX_PYTHON_DIR ?= ${NEXTPNR_XILINX_DIR}/python
+PRJXRAY_DB_DIR ?= ${NEXTPNR_XILINX_DIR}/external/prjxray-db
+
+DBPART = $(shell echo ${PART} | sed -e 's/-[0-9]//g')
+SPEEDGRADE = $(shell echo ${PART} | sed -e 's/.*\-\([0-9]\)/\1/g')
+
+CHIPDB ?= ./
+ifeq ($(CHIPDB),)
+CHIPDB = ./
+endif
+
+PYPY3 ?= pypy3
+
+TOP ?= ${PROJECT}
+TOP_MODULE ?= ${TOP}
+TOP_VERILOG ?= ${TOP}.v
+
+PNR_DEBUG ?= # --verbose --debug
+
+JTAG_LINK ?= -c digilent_hs2
+
+XDC ?= ${PROJECT}.xdc
+
+.PHONY: openxc7
+openxc7: ${PROJECT}_openxc7.bit
+
+.PHONY: program
+program: ${PROJECT}_openxc7.bit
+	openFPGALoader ${JTAG_LINK} --bitstream $<
+
+${PROJECT}.json: ${TOP_VERILOG} ${ADDITIONAL_SOURCES}
+	yosys -p "synth_xilinx -flatten -abc9 ${SYNTH_OPTS} -arch xc7 -top ${TOP_MODULE}; write_json ${PROJECT}.json" $< ${ADDITIONAL_SOURCES}
+
+# The chip database only needs to be generated once
+# that is why we don't clean it with make clean
+${CHIPDB}/${DBPART}.bin:
+	${PYPY3} ${NEXTPNR_XILINX_PYTHON_DIR}/bbaexport.py --device ${PART} --bba ${DBPART}.bba
+	bbasm -l ${DBPART}.bba ${CHIPDB}/${DBPART}.bin
+	rm -f ${DBPART}.bba
+
+${PROJECT}.fasm: ${PROJECT}.json ${CHIPDB}/${DBPART}.bin ${XDC}
+	nextpnr-xilinx --chipdb ${CHIPDB}/${DBPART}.bin --xdc ${XDC} --json ${PROJECT}.json --fasm $@ ${PNR_ARGS} ${PNR_DEBUG}
+	
+${PROJECT}.frames: ${PROJECT}.fasm
+	fasm2frames --part ${PART} --db-root ${PRJXRAY_DB_DIR}/${FAMILY} $< > $@
+
+${PROJECT}_openxc7.bit: ${PROJECT}.frames
+	xc7frames2bit --part_file ${PRJXRAY_DB_DIR}/${FAMILY}/${PART}/part.yaml --part_name ${PART} --frm_file $< --output_file $@
+
+
+#############################################################################################
+# SPDX-License-Identifier: MIT
+# Generated from https://github.com/FPGAOL-CE/caas-wizard
+#
+BUILDDIR := ${CURDIR}/build
+
+LOGFILE := ${BUILDDIR}/top.log
+
+# Build design
+.PHONY: vivado
+vivado: ${BUILDDIR}/${PROJECT}_vivado.bit
+
+${BUILDDIR}:
+	mkdir -m 777 -p ${BUILDDIR} && chown -R nobody ${BUILDDIR} | true
+
+.ONESHELL: 
+${BUILDDIR}/vivado.tcl: ${BUILDDIR}
+	cat << EOF > $@
+	# vivado.tcl generated for FPGAOL-CE/caas-wizard
+	# can be launched from any directory
+	cd ${BUILDDIR}
+	create_project -part ${PART} -force v_proj
+	set_property target_language Verilog [current_project]
+	cd ..
+	read_verilog [glob ${PROJECT}.v ${ADDITIONAL_SOURCES}]
+	read_xdc [glob  $(wildcard ${PROJECT}.xdc) ]
+	cd build
+	synth_design -top ${PROJECT}
+	opt_design
+	place_design
+	phys_opt_design
+	route_design
+	write_bitstream -verbose -force ${PROJECT}_vivado.bit
+	# report_utilization -file util.rpt
+	# report_timing_summary -file timing.rpt
+	EOF
+
+${BUILDDIR}/${PROJECT}_vivado.bit: ${BUILDDIR}/vivado.tcl
+	cd ${BUILDDIR} && vivado -mode batch -source $< > ${LOGFILE} 2>&1
+
+.PHONY: program_vivado
+program_vivado: 
+	openFPGALoader ${JTAG_LINK} --bitstream ${BUILDDIR}/${PROJECT}_vivado.bit
+
+#############################################################################################
+
+.PHONY: clean
+clean:
+	rm -f *.bit
+	rm -f *.frames
+	rm -f *.fasm
+	rm -f *.json
+	rm -f *.bin
+	rm -f *.bba
+	rm -rf ${BUILDDIR}

AngeloJacobo_UberDDR3/example_demo/enclustra_kx2_st1/caas.conf

@@ -0,0 +1,11 @@
+[project]
+Backend = openxc7
+Part = xc7k160tffg676-2
+Top = enclustra_ddr3
+Constraint = enclustra_ddr3.xdc
+Sources = ./ddr3_top.v,./ddr3_controller.v,./ddr3_phy.v,./enclustra_ddr3.v,./uart_rx.v,./uart_tx.v,./clk_wiz.v 
+
+[caas]
+Server = https://caas.symbioticeda.com:18888/
+
+

AngeloJacobo_UberDDR3/example_demo/enclustra_kx2_st1/clk_wiz.v

@@ -0,0 +1,74 @@
+`timescale 1ps/1ps
+
+module clk_wiz
+ (
+  input wire         clk_in1,
+  output wire        clk_out1,
+  output wire        clk_out2,
+  output wire        clk_out3,
+  output wire        clk_out4,
+  output wire        clk_out5,
+  input wire         reset,
+  output wire        locked
+ );
+  wire        clk_out1_clk_wiz_0;
+  wire        clk_out2_clk_wiz_0;
+  wire        clk_out3_clk_wiz_0;
+  // wire        clk_out4_clk_wiz_0;
+  // wire        clk_out5_clk_wiz_0;
+
+  wire clkfbout;
+
+  PLLE2_ADV
+  #(.BANDWIDTH            ("OPTIMIZED"),
+    .COMPENSATION         ("INTERNAL"),
+    .STARTUP_WAIT         ("FALSE"),
+    .DIVCLK_DIVIDE        (1),
+    .CLKFBOUT_MULT        (5), // 200 MHz * 5 = 1000 MHz
+    .CLKFBOUT_PHASE       (0.000),
+    .CLKOUT0_DIVIDE       (12), // 1000 MHz / 12 = 83.333 MHz
+    .CLKOUT0_PHASE        (0.000),
+    .CLKOUT0_DUTY_CYCLE   (0.500),
+    .CLKOUT1_DIVIDE       (3), // 1000 MHz / 3 = 333.333 MHz
+    .CLKOUT1_PHASE        (0.000),
+    .CLKOUT1_DUTY_CYCLE   (0.500),
+    .CLKOUT2_DIVIDE       (5), // 1000 MHz / 5 = 200 MHz
+    .CLKOUT2_PHASE        (0.000),
+    .CLKOUT2_DUTY_CYCLE   (0.500),
+    // .CLKOUT3_DIVIDE       (3), // 1000 MHz / 3 = 333.333 MHz, 90 phase
+    // .CLKOUT3_PHASE        (90.000),
+    // .CLKOUT3_DUTY_CYCLE   (0.500),
+    // .CLKOUT4_DIVIDE       (3), // 1000 MHz / 3 = 333.333 MHz, 180 phase
+    // .CLKOUT4_PHASE        (180),
+    // .CLKOUT4_DUTY_CYCLE   (0.500),
+    .CLKIN1_PERIOD        (5) // 200 MHz input
+  )
+  plle2_adv_inst
+   (
+    .CLKFBOUT            (clkfbout),
+    .CLKOUT0             (clk_out1_clk_wiz_0),
+    .CLKOUT1             (clk_out2_clk_wiz_0),
+    .CLKOUT2             (clk_out3_clk_wiz_0),
+    // .CLKOUT3             (clk_out4_clk_wiz_0),
+    // .CLKOUT4             (clk_out5_clk_wiz_0),
+    .CLKFBIN             (clkfbout),
+	.CLKIN1              (clk_in1),
+    .LOCKED              (locked),
+    .RST                 (reset)
+  );
+  BUFG clkout1_buf
+   (.O   (clk_out1),
+    .I   (clk_out1_clk_wiz_0));
+  BUFG clkout2_buf
+   (.O   (clk_out2),
+    .I   (clk_out2_clk_wiz_0));
+  BUFG clkout3_buf
+   (.O   (clk_out3),
+    .I   (clk_out3_clk_wiz_0));
+  // BUFG clkout4_buf
+  //  (.O   (clk_out4),
+  //   .I   (clk_out4_clk_wiz_0));
+  // BUFG clkout5_buf
+  //  (.O   (clk_out5),
+  //   .I   (clk_out5_clk_wiz_0));
+endmodule

AngeloJacobo_UberDDR3/example_demo/enclustra_kx2_st1/ddr3_phy.v

@@ -0,0 +1,1462 @@
+////////////////////////////////////////////////////////////////////////////////
+//
+// Filename: ddr3_phy.v
+// Project: UberDDR3 - An Open Source DDR3 Controller
+//
+// Purpose: PHY component for the DDR3 controller. Handles the primitives such
+// as IOSERDES, IODELAY, and IOBUF. These generates the signals connected to 
+// the DDR3 RAM.
+//
+// Engineer: Angelo C. Jacobo
+//
+////////////////////////////////////////////////////////////////////////////////
+//
+// Copyright (C) 2023-2025  Angelo Jacobo
+// 
+//     This program is free software: you can redistribute it and/or modify
+//     it under the terms of the GNU General Public License as published by
+//     the Free Software Foundation, either version 3 of the License, or
+//     (at your option) any later version.
+// 
+//     This program is distributed in the hope that it will be useful,
+//     but WITHOUT ANY WARRANTY; without even the implied warranty of
+//     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//     GNU General Public License for more details.
+// 
+//     You should have received a copy of the GNU General Public License
+//     along with this program.  If not, see <https://www.gnu.org/licenses/>.
+//
+////////////////////////////////////////////////////////////////////////////////
+
+`default_nettype none
+`timescale 1ps / 1ps
+//`define DEBUG_DQS // uncomment to route the raw DQS to output port for debugging
+
+module ddr3_phy #(
+    parameter     CONTROLLER_CLK_PERIOD = 10_000, //ps, clock period of the controller interface
+                  DDR3_CLK_PERIOD = 2_500, //ps, clock period of the DDR3 RAM device (must be 1/4 of the CONTROLLER_CLK_PERIOD) 
+                  ROW_BITS = 14,   //width of row address
+                  BA_BITS = 3,
+                  DQ_BITS = 8,
+                  LANES = 8,
+                  DUAL_RANK_DIMM = 0, // enable dual rank DIMM (1 =  enable, 0 = disable)
+    parameter[0:0] ODELAY_SUPPORTED = 1, //set to 1 when ODELAYE2 is supported
+                   USE_IO_TERMINATION = 0, //use IOBUF_DCIEN and IOBUFDS_DCIEN when 1
+                   NO_IOSERDES_LOOPBACK = 1, // don't use IOSERDES loopback for bitslip training
+              // The next parameters act more like a localparam (since user does not have to set this manually) but was added here to simplify port declaration
+    parameter serdes_ratio = 4, // this controller is fixed as a 4:1 memory controller (CONTROLLER_CLK_PERIOD/DDR3_CLK_PERIOD = 4)
+              wb_data_bits = DQ_BITS*LANES*serdes_ratio*2,
+              wb_sel_bits = wb_data_bits / 8,
+              //4 is the width of a single ddr3 command {cs_n, ras_n, cas_n, we_n} plus 3 (ck_en, odt, reset_n) plus bank bits plus row bits
+              cmd_len = 4 + 3 + BA_BITS + ROW_BITS + 2*DUAL_RANK_DIMM
+    )(
+        input wire i_controller_clk, i_ddr3_clk, i_ref_clk,
+        input wire i_ddr3_clk_90, //required only when ODELAY_SUPPORTED is zero
+        input wire i_rst_n,
+        // Controller Interface
+        input wire i_controller_reset,
+        input wire[cmd_len*serdes_ratio-1:0] i_controller_cmd,
+        input wire i_controller_dqs_tri_control, i_controller_dq_tri_control,
+        input wire i_controller_toggle_dqs,
+        input wire[wb_data_bits-1:0] i_controller_data,
+        input wire[wb_sel_bits-1:0] i_controller_dm,
+        input wire[4:0] i_controller_odelay_data_cntvaluein,i_controller_odelay_dqs_cntvaluein,
+        input wire[4:0] i_controller_idelay_data_cntvaluein,i_controller_idelay_dqs_cntvaluein,
+        input wire[LANES-1:0] i_controller_odelay_data_ld, i_controller_odelay_dqs_ld,
+        input wire[LANES-1:0] i_controller_idelay_data_ld, i_controller_idelay_dqs_ld,
+        input wire[LANES-1:0] i_controller_bitslip,
+        input wire i_controller_write_leveling_calib,
+        output wire[DQ_BITS*LANES*8-1:0] o_controller_iserdes_data,
+        output wire[LANES*8-1:0] o_controller_iserdes_dqs,
+        output wire[LANES*8-1:0] o_controller_iserdes_bitslip_reference,
+        output wire o_controller_idelayctrl_rdy,
+        // DDR3 I/O Interface
+        output wire[DUAL_RANK_DIMM:0] o_ddr3_clk_p,o_ddr3_clk_n,
+        output wire o_ddr3_reset_n,
+        output wire[DUAL_RANK_DIMM:0] o_ddr3_cke, // CKE
+        output wire[DUAL_RANK_DIMM:0] o_ddr3_cs_n, // chip select signal
+        output wire o_ddr3_ras_n, // RAS#
+        output wire o_ddr3_cas_n, // CAS#
+        output wire o_ddr3_we_n, // WE#
+        output wire[ROW_BITS-1:0] o_ddr3_addr,
+        output wire[BA_BITS-1:0] o_ddr3_ba_addr,
+        inout wire[(DQ_BITS*LANES)-1:0] io_ddr3_dq,
+        inout wire[(DQ_BITS*LANES)/8-1:0] io_ddr3_dqs, io_ddr3_dqs_n,
+        output wire[LANES-1:0] o_ddr3_dm,
+        output wire[DUAL_RANK_DIMM:0] o_ddr3_odt, // on-die termination
+        // DEBUG PHY
+        output wire[(DQ_BITS*LANES)/8-1:0] o_ddr3_debug_read_dqs_p,
+        output wire[(DQ_BITS*LANES)/8-1:0] o_ddr3_debug_read_dqs_n
+    );
+
+    // cmd bit assignment
+    localparam CMD_CS_N_2 = cmd_len - 1,
+                CMD_CS_N =  DUAL_RANK_DIMM[0]? cmd_len - 2 : cmd_len - 1,
+                CMD_RAS_N = DUAL_RANK_DIMM[0]? cmd_len - 3 : cmd_len - 2,
+                CMD_CAS_N = DUAL_RANK_DIMM[0]? cmd_len - 4 : cmd_len - 3,
+                CMD_WE_N =  DUAL_RANK_DIMM[0]? cmd_len - 5 : cmd_len - 4,
+                CMD_ODT =   DUAL_RANK_DIMM[0]? cmd_len - 6 : cmd_len - 5,
+                CMD_CKE_2 = DUAL_RANK_DIMM[0]? cmd_len - 7 : cmd_len - 6,
+                CMD_CKE =   DUAL_RANK_DIMM[0]? cmd_len - 8 : cmd_len - 6,
+                CMD_RESET_N = DUAL_RANK_DIMM[0]? cmd_len - 9 : cmd_len - 7,
+                CMD_BANK_START = BA_BITS + ROW_BITS - 1,
+                CMD_ADDRESS_START = ROW_BITS - 1;
+    localparam SYNC_RESET_DELAY = $rtoi($ceil(52_000/CONTROLLER_CLK_PERIOD)); //52_000 ps of reset pulse width required for IDELAYCTRL 
+    //cmd needs to be center-aligned to the positive edge of the 
+    //ddr3_clk. This means cmd needs to be delayed by half the ddr3
+    //clk period. Subtract by 600ps to include the IODELAY insertion
+    //delay. Divide by a delay resolution of 78.125ps per tap to get 
+    //the needed tap value.
+    localparam CMD_ODELAY_TAP = ((DDR3_CLK_PERIOD/2) - 600)/78.125;
+
+    // Data does not have to be delayed (DQS is the on that has to be
+    // delayed and center-aligned to the center eye of data)
+    localparam DATA_ODELAY_TAP = 0; 
+
+    //DQS needs to be edge-aligned to the center eye of the data. 
+    //This means DQS needs to be delayed by a quarter of the ddr3
+    //clk period relative to the data. Subtract by 600ps to include
+    //the IODELAY insertion delay. Divide by a delay resolution of 
+    //78.125ps per tap to get the needed tap value. Then add the tap
+    //value used in data to have the delay relative to the data.
+    localparam DQS_ODELAY_TAP = ((DDR3_CLK_PERIOD/4))/78.125 + DATA_ODELAY_TAP;
+    
+    //Incoming DQS should be 90 degree delayed relative to incoming data
+    localparam DATA_IDELAY_TAP = 0; //600ps delay
+    localparam DQS_IDELAY_TAP = ((DDR3_CLK_PERIOD/4))/78.125 + DATA_IDELAY_TAP;
+    
+    genvar gen_index;
+    wire[cmd_len-1:0] oserdes_cmd, //serialized(4:1) i_controller_cmd_slot_x 
+                      cmd;//delayed oserdes_cmd
+    wire[(DQ_BITS*LANES)-1:0] oserdes_data, odelay_data, idelay_data, read_dq;
+    wire[LANES-1:0] oserdes_dm, odelay_dm;
+    wire[LANES-1:0] odelay_dqs, read_dqs, idelay_dqs;
+    wire[DQ_BITS*LANES-1:0] oserdes_dq_tri_control;
+    wire[LANES-1:0] oserdes_dqs;
+    wire[LANES-1:0] oserdes_dqs_tri_control;
+    wire[LANES-1:0] oserdes_bitslip_reference;
+    reg[$clog2(SYNC_RESET_DELAY):0] delay_before_release_reset;
+    reg sync_rst = 0;
+    wire ddr3_clk;
+    reg toggle_dqs_q; //past value of i_controller_toggle_dqs
+    wire ddr3_clk_delayed;
+    wire idelayctrl_rdy;
+    wire dci_locked;
+    reg[LANES*8-1:0] o_controller_iserdes_bitslip_reference_reg;
+    reg[LANES - 1 : 0] shift_bitslip_index;
+    
+    // initial value of bitslip reference
+    initial begin
+        o_controller_iserdes_bitslip_reference_reg = {LANES{8'b0001_1110}};
+        shift_bitslip_index = 0;
+    end
+                
+    assign o_controller_idelayctrl_rdy = idelayctrl_rdy && dci_locked;
+    
+`ifdef DEBUG_DQS
+    assign o_ddr3_debug_read_dqs_p = io_ddr3_dqs;
+    assign o_ddr3_debug_read_dqs_n = io_ddr3_dqs_n;
+`else
+    assign o_ddr3_debug_read_dqs_p = 0;
+    assign o_ddr3_debug_read_dqs_n = 0;
+`endif
+
+    //synchronous reset
+    always @(posedge i_controller_clk) begin
+        if(!i_rst_n || i_controller_reset) begin
+            sync_rst <= 1'b1;
+            delay_before_release_reset <= SYNC_RESET_DELAY[$clog2(SYNC_RESET_DELAY):0];
+            toggle_dqs_q <= 0;
+        end
+        else begin
+            delay_before_release_reset <= (delay_before_release_reset == 0)? 0: delay_before_release_reset - 1;
+            sync_rst <= !(delay_before_release_reset == 0);
+            toggle_dqs_q <= i_controller_toggle_dqs;
+        end
+    end
+
+    //PHY cmd 
+    generate
+        for(gen_index = 0; gen_index < cmd_len; gen_index = gen_index + 1) begin
+            // OSERDESE2: Output SERial/DESerializer with bitslip
+            //7 Series
+            // Xilinx HDL Libraries Guide, version 13.4
+            `ifndef SIM_MODEL
+                OSERDESE2 #(
+            `else 
+                OSERDESE2_model #(
+            `endif
+                .DATA_RATE_OQ("SDR"), // DDR, SDR
+                .DATA_RATE_TQ("SDR"), // DDR, SDR
+                .DATA_WIDTH(4), // Parallel data width (2-8,10,14)
+                .INIT_OQ(1'b0), // Initial value of OQ output (1'b0,1'b1)
+                .TRISTATE_WIDTH(1)
+            )
+            OSERDESE2_cmd(
+                .OFB(), // 1-bit output: Feedback path for data
+                .OQ(oserdes_cmd[gen_index]), // 1-bit output: Data path output
+                .CLK(i_ddr3_clk), // 1-bit input: High speed clock
+                .CLKDIV(i_controller_clk), // 1-bit input: Divided clock
+                // D1 - D8: 1-bit (each) input: Parallel data inputs (1-bit each)
+                .D1(i_controller_cmd[cmd_len*0 + gen_index]),
+                .D2(i_controller_cmd[cmd_len*1 + gen_index]),
+                .D3(i_controller_cmd[cmd_len*2 + gen_index]),
+                .D4(i_controller_cmd[cmd_len*3 + gen_index]),
+                .OCE(1'b1), // 1-bit input: Output data clock enable
+                .RST(sync_rst), // 1-bit input: Reset
+                // unused signals but were added here to make vivado happy
+                .SHIFTOUT1(), // SHIFTOUT1 / SHIFTOUT2: 1-bit (each) output: Data output expansion (1-bit each)
+                .SHIFTOUT2(),
+                .TBYTEOUT(), // 1-bit output: Byte group tristate
+                .TFB(), // 1-bit output: 3-state control
+                .TQ(), // 1-bit output: 3-state control
+                .D5(),
+                .D6(),
+                .D7(),
+                .D8(),
+                // SHIFTIN1 / SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each)
+                .SHIFTIN1(0),
+                .SHIFTIN2(0),
+                // T1 - T4: 1-bit (each) input: Parallel 3-state inputs
+                .T1(0),
+                .T2(0),
+                .T3(0),
+                .T4(0),
+                .TBYTEIN(0),
+                // 1-bit input: Byte group tristate
+                .TCE(0)
+                // 1-bit input: 3-state clock enable
+            );
+            // End of OSERDESE2_inst instantiation
+      
+        end
+
+        if(DUAL_RANK_DIMM) begin // if dual rank enabled, odt_2 and odt_1 will be generated separately
+            // OSERDESE2: Output SERial/DESerializer with bitslip
+            //7 Series
+            // Xilinx HDL Libraries Guide, version 13.4
+            `ifndef SIM_MODEL
+                OSERDESE2 #(
+            `else 
+                OSERDESE2_model #(
+            `endif
+                .DATA_RATE_OQ("SDR"), // DDR, SDR
+                .DATA_RATE_TQ("SDR"), // DDR, SDR
+                .DATA_WIDTH(4), // Parallel data width (2-8,10,14)
+                .INIT_OQ(1'b0), // Initial value of OQ output (1'b0,1'b1)
+                .TRISTATE_WIDTH(1)
+            )
+            OSERDESE2_cmd(
+                .OFB(), // 1-bit output: Feedback path for data
+                .OQ(o_ddr3_odt[1]), // 1-bit output: Data path output
+                .CLK(i_ddr3_clk), // 1-bit input: High speed clock
+                .CLKDIV(i_controller_clk), // 1-bit input: Divided clock
+                // D1 - D8: 1-bit (each) input: Parallel data inputs (1-bit each)
+                .D1(i_controller_cmd[cmd_len*0 + CMD_ODT]),
+                .D2(i_controller_cmd[cmd_len*1 + CMD_ODT]),
+                .D3(i_controller_cmd[cmd_len*2 + CMD_ODT]),
+                .D4(i_controller_cmd[cmd_len*3 + CMD_ODT]),
+                .OCE(1'b1), // 1-bit input: Output data clock enable
+                .RST(sync_rst), // 1-bit input: Reset
+                // unused signals but were added here to make vivado happy
+                .SHIFTOUT1(), // SHIFTOUT1 / SHIFTOUT2: 1-bit (each) output: Data output expansion (1-bit each)
+                .SHIFTOUT2(),
+                .TBYTEOUT(), // 1-bit output: Byte group tristate
+                .TFB(), // 1-bit output: 3-state control
+                .TQ(), // 1-bit output: 3-state control
+                .D5(),
+                .D6(),
+                .D7(),
+                .D8(),
+                // SHIFTIN1 / SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each)
+                .SHIFTIN1(0),
+                .SHIFTIN2(0),
+                // T1 - T4: 1-bit (each) input: Parallel 3-state inputs
+                .T1(0),
+                .T2(0),
+                .T3(0),
+                .T4(0),
+                .TBYTEIN(0),
+                // 1-bit input: Byte group tristate
+                .TCE(0)
+                // 1-bit input: 3-state clock enable
+            );
+            // End of OSERDESE2_inst instantiation
+        end
+    endgenerate 
+
+    // cs[1] when DUAL_RANK_DIMM enabled
+    generate    
+        if(DUAL_RANK_DIMM) begin
+            assign o_ddr3_cs_n[1] = oserdes_cmd[CMD_CS_N_2];
+            assign o_ddr3_cs_n[0] = oserdes_cmd[CMD_CS_N];
+            assign o_ddr3_cke[1] = oserdes_cmd[CMD_CKE_2];
+            assign o_ddr3_cke[0] = oserdes_cmd[CMD_CKE];
+            assign o_ddr3_odt[0] = oserdes_cmd[CMD_ODT];
+            // o_ddr3_odt[1] will be generated directly by a separate OSERDES
+            // if odt[1] and odt[0] uses same output from oserdes, one of them will be unroutable
+        end
+        else begin
+            assign o_ddr3_cs_n = oserdes_cmd[CMD_CS_N];
+            assign o_ddr3_cke = oserdes_cmd[CMD_CKE];
+            assign o_ddr3_odt = oserdes_cmd[CMD_ODT];
+        end
+    endgenerate
+    assign o_ddr3_ras_n = oserdes_cmd[CMD_RAS_N],
+           o_ddr3_cas_n = oserdes_cmd[CMD_CAS_N],
+           o_ddr3_we_n = oserdes_cmd[CMD_WE_N],
+           o_ddr3_reset_n = oserdes_cmd[CMD_RESET_N],
+           o_ddr3_ba_addr = oserdes_cmd[CMD_BANK_START:CMD_ADDRESS_START+1],
+           o_ddr3_addr = oserdes_cmd[CMD_ADDRESS_START:0];
+    
+    if(ODELAY_SUPPORTED) begin
+        // OSERDESE2: Output SERial/DESerializer with bitslip
+        //7 Series
+        // Xilinx HDL Libraries Guide, version 13.4
+        `ifndef SIM_MODEL
+            OSERDESE2 #(
+        `else 
+            OSERDESE2_model #(
+        `endif
+            .DATA_RATE_OQ("DDR"), // DDR, SDR
+            .DATA_RATE_TQ("SDR"), // DDR, SDR
+            .DATA_WIDTH(8), // Parallel data width (2-8,10,14)
+            .INIT_OQ(1'b0), // Initial value of OQ output (1'b0,1'b1)
+            .TRISTATE_WIDTH(1)
+        )
+        OSERDESE2_clk(
+            .OFB(ddr3_clk), // 1-bit output: Feedback path for data
+            .OQ(), // 1-bit output: Data path output
+            .CLK(i_ddr3_clk), // 1-bit input: High speed clock
+            .CLKDIV(i_controller_clk), // 1-bit input: Divided clock
+            // D1 - D8: 1-bit (each) input: Parallel data inputs (1-bit each)
+            .D1(1'b1),
+            .D2(1'b0),
+            .D3(1'b1),
+            .D4(1'b0),
+            .D5(1'b1),
+            .D6(1'b0),
+            .D7(1'b1),
+            .D8(1'b0),
+            .OCE(1'b1), // 1-bit input: Output data clock enable
+            .RST(sync_rst), // 1-bit input: Reset
+             // unused signals but were added here to make vivado happy
+            .SHIFTOUT1(), // SHIFTOUT1 / SHIFTOUT2: 1-bit (each) output: Data output expansion (1-bit each)
+            .SHIFTOUT2(),
+            .TBYTEOUT(), // 1-bit output: Byte group tristate
+            .TFB(), // 1-bit output: 3-state control
+            .TQ(), // 1-bit output: 3-state control
+            // SHIFTIN1 / SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each)
+            .SHIFTIN1(0),
+            .SHIFTIN2(0),
+            // T1 - T4: 1-bit (each) input: Parallel 3-state inputs
+            .T1(0),
+            .T2(0),
+            .T3(0),
+            .T4(0),
+            .TBYTEIN(0),
+            // 1-bit input: Byte group tristate
+            .TCE(0)
+            // 1-bit input: 3-state clock enable
+        );
+        // End of OSERDESE2_inst instantiation
+
+            //Delay the DQ
+            // Delay resolution: 1/(32 x 2 x F REF ) = 78.125ps
+            (* IODELAY_GROUP="DDR3-GROUP" *)
+            `ifndef SIM_MODEL
+                ODELAYE2 #(
+            `else 
+                ODELAYE2_model #(
+            `endif
+                .DELAY_SRC("ODATAIN"), // Delay input (ODATAIN, CLKIN)
+                .HIGH_PERFORMANCE_MODE("TRUE"), // Reduced jitter to 5ps ("TRUE"), Reduced power but high jitter 9ns ("FALSE")
+                .ODELAY_TYPE("FIXED"), // FIXED, VARIABLE, VAR_LOAD, VAR_LOAD_PIPE
+                .ODELAY_VALUE(CMD_ODELAY_TAP), // Output delay tap setting (0-31)
+                .REFCLK_FREQUENCY(200.0), // IDELAYCTRL clock input frequency in MHz (190.0-210.0).
+                .SIGNAL_PATTERN("DATA") // DATA, CLOCK input signal
+            )
+            ODELAYE2_clk (
+                .CNTVALUEOUT(), // 5-bit output: Counter value output
+                .DATAOUT(ddr3_clk_delayed), // 1-bit output: Delayed data/clock output
+                .C(i_controller_clk), // 1-bit input: Clock input, when using OSERDESE2, C is connected to CLKDIV
+                .CE(1'b0), // 1-bit input: Active high enable increment/decrement input
+                .CINVCTRL(1'b0), // 1-bit input: Dynamic clock inversion input
+                .CLKIN(1'b0), // 1-bit input: Clock delay input
+                .CNTVALUEIN(5'd0), // 5-bit input: Counter value input
+                .INC(1'b0), // 1-bit input: Increment / Decrement tap delay input
+                .LD(1'b0), // 1-bit input: Loads ODELAY_VALUE tap delay in VARIABLE mode, in VAR_LOAD or
+                            // VAR_LOAD_PIPE mode, loads the value of CNTVALUEIN
+                .LDPIPEEN(1'b0), // 1-bit input: Enables the pipeline register to load data
+                .ODATAIN(ddr3_clk), // 1-bit input: Output delay data input
+                .REGRST(1'b0) // 1-bit input: Active-high reset tap-delay input
+            );
+        // if dual rank enabled, then there will be two clk
+        if(DUAL_RANK_DIMM) begin
+            // OBUFDS: Differential Output Buffer
+            // 7 Series
+            // Xilinx HDL Libraries Guide, version 13.4
+            `ifndef SIM_MODEL
+                OBUFDS OBUFDS0_inst (
+            `else 
+                OBUFDS_model OBUFDS0_inst (
+            `endif
+                .O(o_ddr3_clk_p[0]), // Diff_p output (connect directly to top-level port)
+                .OB(o_ddr3_clk_n[0]), // Diff_n output (connect directly to top-level port)
+                .I(ddr3_clk_delayed) // Buffer input
+            );
+            `ifndef SIM_MODEL
+                OBUFDS OBUFDS1_inst (
+            `else 
+                OBUFDS_model OBUFDS1_inst (
+            `endif
+                .O(o_ddr3_clk_p[1]), // Diff_p output (connect directly to top-level port)
+                .OB(o_ddr3_clk_n[1]), // Diff_n output (connect directly to top-level port)
+                .I(ddr3_clk_delayed) // Buffer input
+            );
+            // End of OBUFDS_inst instantiation
+        end
+        else begin
+            // OBUFDS: Differential Output Buffer
+            // 7 Series
+            // Xilinx HDL Libraries Guide, version 13.4
+            `ifndef SIM_MODEL
+                OBUFDS OBUFDS_inst (
+            `else 
+                OBUFDS_model OBUFDS_inst (
+            `endif
+                .O(o_ddr3_clk_p), // Diff_p output (connect directly to top-level port)
+                .OB(o_ddr3_clk_n), // Diff_n output (connect directly to top-level port)
+                .I(ddr3_clk_delayed) // Buffer input
+            );
+            // End of OBUFDS_inst instantiation
+        end
+    end
+    else begin //ODELAY is not supported
+
+                // if dual rank enabled, then there will be two clk
+        if(DUAL_RANK_DIMM) begin
+            // OBUFDS: Differential Output Buffer
+            // 7 Series
+            // Xilinx HDL Libraries Guide, version 13.4
+            `ifndef SIM_MODEL
+                OBUFDS OBUFDS0_inst (
+            `else 
+                OBUFDS_model OBUFDS0_inst (
+            `endif
+                .O(o_ddr3_clk_p[1]), // Diff_p output (connect directly to top-level port)
+                .OB(o_ddr3_clk_n[1]), // Diff_n output (connect directly to top-level port)
+                .I(!i_ddr3_clk) // Buffer input
+            );
+            `ifndef SIM_MODEL
+                OBUFDS OBUFDS1_inst (
+            `else 
+                OBUFDS_model OBUFDS1_inst (
+            `endif
+                .O(o_ddr3_clk_p[0]), // Diff_p output (connect directly to top-level port)
+                .OB(o_ddr3_clk_n[0]), // Diff_n output (connect directly to top-level port)
+                .I(!i_ddr3_clk) // Buffer input
+            );
+            // End of OBUFDS_inst instantiation
+        end
+        else begin
+            // OBUFDS: Differential Output Buffer
+            // 7 Series
+            // Xilinx HDL Libraries Guide, version 13.4
+            `ifndef SIM_MODEL
+                OBUFDS OBUFDS_inst (
+            `else 
+                OBUFDS_model OBUFDS_inst (
+            `endif
+                .O(o_ddr3_clk_p), // Diff_p output (connect directly to top-level port)
+                .OB(o_ddr3_clk_n), // Diff_n output (connect directly to top-level port)
+                .I(!i_ddr3_clk) // Buffer input
+            );
+        end
+    end
+    
+    
+    // PHY data and dm
+    generate
+        // data: oserdes -> odelay -> iobuf
+        for(gen_index = 0; gen_index < (DQ_BITS*LANES); gen_index = gen_index + 1) begin
+            
+            if (ODELAY_SUPPORTED) begin
+                // OSERDESE2: Output SERial/DESerializer with bitslip
+                //7 Series
+                // Xilinx HDL Libraries Guide, version 13.4
+                `ifndef SIM_MODEL
+                    OSERDESE2 #(
+                `else 
+                    OSERDESE2_model #(
+                `endif
+                    .DATA_RATE_OQ("DDR"), // DDR, SDR
+                    .DATA_RATE_TQ("BUF"), // DDR, SDR
+                    .DATA_WIDTH(8), // Parallel data width (2-8,10,14)
+                    .INIT_OQ(1'b0), // Initial value of OQ output (1'b0,1'b1)
+                    .TRISTATE_WIDTH(1)
+                )
+                OSERDESE2_data(
+                    .OFB(oserdes_data[gen_index]), // 1-bit output: Feedback path for data
+                    .OQ(), // 1-bit output: Data path output
+                    .TQ(oserdes_dq_tri_control[gen_index]),
+                    .CLK(i_ddr3_clk), // 1-bit input: High speed clock
+                    .CLKDIV(i_controller_clk), // 1-bit input: Divided clock
+                    // D1 - D8: 1-bit (each) input: Parallel data inputs (1-bit each)
+                    .D1(i_controller_data[gen_index + (DQ_BITS*LANES)*0]),
+                    .D2(i_controller_data[gen_index + (DQ_BITS*LANES)*1]),
+                    .D3(i_controller_data[gen_index + (DQ_BITS*LANES)*2]),
+                    .D4(i_controller_data[gen_index + (DQ_BITS*LANES)*3]),
+                    .D5(i_controller_data[gen_index + (DQ_BITS*LANES)*4]),
+                    .D6(i_controller_data[gen_index + (DQ_BITS*LANES)*5]),
+                    .D7(i_controller_data[gen_index + (DQ_BITS*LANES)*6]),
+                    .D8(i_controller_data[gen_index + (DQ_BITS*LANES)*7]),
+                    .T1(i_controller_dq_tri_control),
+                    .TCE(1'b1),
+                    .OCE(1'b1), // 1-bit input: Output data clock enable
+                    .RST(sync_rst), // 1-bit input: Reset
+                    // unused signals but were added here to make vivado happy
+                    .SHIFTOUT1(), // SHIFTOUT1 / SHIFTOUT2: 1-bit (each) output: Data output expansion (1-bit each)
+                    .SHIFTOUT2(),
+                    .TBYTEOUT(), // 1-bit output: Byte group tristate
+                    .TFB(), // 1-bit output: 3-state control
+                    // SHIFTIN1 / SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each)
+                    .SHIFTIN1(0),
+                    .SHIFTIN2(0),
+                    // T1 - T4: 1-bit (each) input: Parallel 3-state inputs
+                    .T2(0),
+                    .T3(0),
+                    .T4(0),
+                    .TBYTEIN(0)
+                    // 1-bit input: Byte group tristate
+                );
+                // End of OSERDESE2_inst instantiation
+            
+                // ODELAYE2: Output Fixed or Variable Delay Element
+                // 7 Series
+                // Xilinx HDL Libraries Guide, version 13.4
+                //odelay adds an insertion delay of 600ps to the actual delay setting: https://support.xilinx.com/s/article/42133?language=en_US
+                //Delay the DQ
+                // Delay resolution: 1/(32 x 2 x F REF ) = 78.125ps
+                (* IODELAY_GROUP="DDR3-GROUP" *)
+                `ifndef SIM_MODEL
+                    ODELAYE2 #(
+                `else 
+                    ODELAYE2_model #(
+                `endif
+                    .DELAY_SRC("ODATAIN"), // Delay input (ODATAIN, CLKIN)
+                    .HIGH_PERFORMANCE_MODE("TRUE"), // Reduced jitter to 5ps ("TRUE"), Reduced power but high jitter 9ns ("FALSE")
+                    .ODELAY_TYPE("VAR_LOAD"), // FIXED, VARIABLE, VAR_LOAD, VAR_LOAD_PIPE
+                    .ODELAY_VALUE(DATA_ODELAY_TAP), // Output delay tap setting (0-31)
+                    .REFCLK_FREQUENCY(200.0), // IDELAYCTRL clock input frequency in MHz (190.0-210.0).
+                    .SIGNAL_PATTERN("DATA") // DATA, CLOCK input signal
+                )
+                ODELAYE2_data (
+                    .CNTVALUEOUT(), // 5-bit output: Counter value output
+                    .DATAOUT(odelay_data[gen_index]), // 1-bit output: Delayed data/clock output
+                    .C(i_controller_clk), // 1-bit input: Clock input, when using OSERDESE2, C is connected to CLKDIV
+                    .CE(1'b0), // 1-bit input: Active high enable increment/decrement input
+                    .CINVCTRL(1'b0), // 1-bit input: Dynamic clock inversion input
+                    .CLKIN(1'b0), // 1-bit input: Clock delay input
+                    .CNTVALUEIN(i_controller_odelay_data_cntvaluein), // 5-bit input: Counter value input
+                    .INC(1'b0), // 1-bit input: Increment / Decrement tap delay input
+                    .LD(i_controller_odelay_data_ld[gen_index/8]), // 1-bit input: Loads ODELAY_VALUE tap delay in VARIABLE mode, in VAR_LOAD or
+                                // VAR_LOAD_PIPE mode, loads the value of CNTVALUEIN
+                    .LDPIPEEN(1'b0), // 1-bit input: Enables the pipeline register to load data
+                    .ODATAIN(oserdes_data[gen_index]), // 1-bit input: Output delay data input
+                    .REGRST(1'b0) // 1-bit input: Active-high reset tap-delay input
+                );
+
+                if(USE_IO_TERMINATION) begin 
+                    // IOBUF_DCIEN: Single-ended Bi-directional Buffer with Digital Controlled Impedance (DCI)
+                    // and Input path enable/disable
+                    // May only be placed in High Performance (HP) Banks
+                    // 7 Series
+                    // Xilinx HDL Libraries Guide, version 13.4
+                    `ifndef SIM_MODEL
+                        IOBUF_DCIEN #(
+                    `else 
+                        IOBUF_DCIEN_model #(
+                    `endif
+                    .IBUF_LOW_PWR("FALSE"), // Low Power - "TRUE", High Performance = "FALSE"
+                    .SLEW("FAST"), // Specify the output slew rate
+                    .USE_IBUFDISABLE("FALSE") // Use IBUFDISABLE function, "TRUE" or "FALSE"
+                    ) IOBUF_DCIEN_data (
+                        .O(read_dq[gen_index]), // Buffer output
+                        .IO(io_ddr3_dq[gen_index]), // Buffer inout port (connect directly to top-level port)
+                        .DCITERMDISABLE(1'b0), // DCI Termination enable input
+                        .I(odelay_data[gen_index]), // Buffer input
+                        .IBUFDISABLE(1'b0), // Input disable input, low=disable
+                        .T(oserdes_dq_tri_control[gen_index]) // 3-state enable input, high=input, low=output
+                    );
+                    // End of IOBUF_DCIEN_inst instantiation
+
+                 end
+                 else begin                         
+                    // IOBUF: Single-ended Bi-directional Buffer
+                    //All devices
+                    // Xilinx HDL Libraries Guide, version 13.4
+                    `ifndef SIM_MODEL
+                        IOBUF #(
+                    `else 
+                        IOBUF_model #(
+                    `endif
+                        //.DRIVE(12), // Specify the output drive strength
+                        .IBUF_LOW_PWR("FALSE"), // Low Power - "TRUE", High Performance = "FALSE"
+                        //.IOSTANDARD("SSTL15"), // Specify the I/O standard
+                        .SLEW("FAST") // Specify the output slew rate
+                    ) IOBUF_data (
+                        .O(read_dq[gen_index]),// Buffer output
+                        .IO(io_ddr3_dq[gen_index]), // Buffer inout port (connect directly to top-level port)
+                        .I(odelay_data[gen_index]), // Buffer input
+                        .T(oserdes_dq_tri_control[gen_index]) // 3-state enable input, high=read, low=write
+                    );
+                 end
+            end
+            else begin //ODELAY is not supported
+                // OSERDESE2: Output SERial/DESerializer with bitslip
+                //7 Series
+                // Xilinx HDL Libraries Guide, version 13.4
+                `ifndef SIM_MODEL
+                    OSERDESE2 #(
+                `else 
+                    OSERDESE2_model #(
+                `endif
+                    .DATA_RATE_OQ("DDR"), // DDR, SDR
+                    .DATA_RATE_TQ("BUF"), // DDR, SDR
+                    .DATA_WIDTH(8), // Parallel data width (2-8,10,14)
+                    .INIT_OQ(1'b0), // Initial value of OQ output (1'b0,1'b1)
+                    .TRISTATE_WIDTH(1)
+                )
+                OSERDESE2_data(
+                    .OFB(), // 1-bit output: Feedback path for data
+                    .OQ(oserdes_data[gen_index]), // 1-bit output: Data path output
+                    .TQ(oserdes_dq_tri_control[gen_index]),
+                    .CLK(i_ddr3_clk_90), // 1-bit input: High speed clock
+                    .CLKDIV(i_controller_clk), // 1-bit input: Divided clock
+                    // D1 - D8: 1-bit (each) input: Parallel data inputs (1-bit each)
+                    .D1(i_controller_data[gen_index + (DQ_BITS*LANES)*0]),
+                    .D2(i_controller_data[gen_index + (DQ_BITS*LANES)*1]),
+                    .D3(i_controller_data[gen_index + (DQ_BITS*LANES)*2]),
+                    .D4(i_controller_data[gen_index + (DQ_BITS*LANES)*3]),
+                    .D5(i_controller_data[gen_index + (DQ_BITS*LANES)*4]),
+                    .D6(i_controller_data[gen_index + (DQ_BITS*LANES)*5]),
+                    .D7(i_controller_data[gen_index + (DQ_BITS*LANES)*6]),
+                    .D8(i_controller_data[gen_index + (DQ_BITS*LANES)*7]),
+                    .T1(i_controller_dq_tri_control),
+                    .TCE(1'b1),
+                    .OCE(1'b1), // 1-bit input: Output data clock enable
+                    .RST(sync_rst), // 1-bit input: Reset
+                    // unused signals but were added here to make vivado happy
+                    .SHIFTOUT1(), // SHIFTOUT1 / SHIFTOUT2: 1-bit (each) output: Data output expansion (1-bit each)
+                    .SHIFTOUT2(),
+                    .TBYTEOUT(), // 1-bit output: Byte group tristate
+                    .TFB(), // 1-bit output: 3-state control
+                    // SHIFTIN1 / SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each)
+                    .SHIFTIN1(0),
+                    .SHIFTIN2(0),
+                    // T1 - T4: 1-bit (each) input: Parallel 3-state inputs
+                    .T2(0),
+                    .T3(0),
+                    .T4(0),
+                    .TBYTEIN(0)
+                    // 1-bit input: Byte group tristate
+                );
+                // End of OSERDESE2_inst instantiation
+                
+                // IOBUF: Single-ended Bi-directional Buffer
+                //All devices
+                // Xilinx HDL Libraries Guide, version 13.4
+                `ifndef SIM_MODEL
+                    IOBUF #(
+                `else 
+                    IOBUF_model #(
+                `endif
+                    //.DRIVE(12), // Specify the output drive strength
+                    .IBUF_LOW_PWR("FALSE"), // Low Power - "TRUE", High Performance = "FALSE"
+                    //.IOSTANDARD("SSTL15"), // Specify the I/O standard
+                    .SLEW("FAST") // Specify the output slew rate
+                ) IOBUF_data (
+                    .O(read_dq[gen_index]),// Buffer output
+                    .IO(io_ddr3_dq[gen_index]), // Buffer inout port (connect directly to top-level port)
+                    .I(oserdes_data[gen_index]), // Buffer input
+                    .T(oserdes_dq_tri_control[gen_index]) // 3-state enable input, high=read, low=write
+                );
+            end
+
+            // IDELAYE2: Input Fixed or Variable Delay Element
+            // 7 Series
+            // Xilinx HDL Libraries Guide, version 13.4
+            (* IODELAY_GROUP="DDR3-GROUP" *)
+            `ifndef SIM_MODEL
+                IDELAYE2 #(
+            `else 
+                IDELAYE2_model #(
+            `endif
+                .DELAY_SRC("IDATAIN"), // Delay input (IDATAIN, DATAIN)
+                .HIGH_PERFORMANCE_MODE("TRUE"), //Reduced jitter ("TRUE"), Reduced power ("FALSE")
+                .IDELAY_TYPE("VAR_LOAD"), //FIXED, VARIABLE, VAR_LOAD, VAR_LOAD_PIPE
+                .IDELAY_VALUE(DATA_IDELAY_TAP), //Input delay tap setting (0-31)
+                .PIPE_SEL("FALSE"),  //Select pipelined mode, FALSE, TRUE
+                .REFCLK_FREQUENCY(200.0), //IDELAYCTRL clock input frequency in MHz (190.0-210.0).
+                .SIGNAL_PATTERN("DATA") //DATA, CLOCK input signal
+            )
+            IDELAYE2_data (
+                .CNTVALUEOUT(), // 5-bit output: Counter value output
+                .DATAOUT(idelay_data[gen_index]), // 1-bit output: Delayed data output
+                .C(i_controller_clk), // 1-bit input: Clock input
+                .CE(1'b0), // 1-bit input: Active high enable increment/decrement input
+                .CINVCTRL(1'b0),// 1-bit input: Dynamic clock inversion input
+                .CNTVALUEIN(i_controller_idelay_data_cntvaluein), // 5-bit input: Counter value input
+                .DATAIN(), //1-bit input: Internal delay data input
+                .IDATAIN(read_dq[gen_index]), // 1-bit input: Data input from the I/O
+                .INC(1'b0), // 1-bit input: Increment / Decrement tap delay input
+                .LD(i_controller_idelay_data_ld[gen_index/8]), // 1-bit input: Load IDELAY_VALUE input
+                .LDPIPEEN(1'b0), // 1-bit input: Enable PIPELINE register to load data input
+                .REGRST(1'b0) // 1-bit input: Active-high reset tap-delay input
+            );
+            // End of IDELAYE2_inst instantiation
+
+            // End of IOBUF_inst instantiation                 
+            // ISERDESE2: Input SERial/DESerializer with bitslip
+            //7 Series
+            // Xilinx HDL Libraries Guide, version 13.4
+            `ifndef SIM_MODEL
+                ISERDESE2 #(
+            `else 
+                ISERDESE2_model #(
+            `endif
+                .DATA_RATE("DDR"), // DDR, SDR
+                .DATA_WIDTH(8), // Parallel data width (2-8,10,14)
+                // INIT_Q1 - INIT_Q4: Initial value on the Q outputs (0/1)
+                .INIT_Q1(1'b0),
+                .INIT_Q2(1'b0),
+                .INIT_Q3(1'b0),
+                .INIT_Q4(1'b0),
+                .INTERFACE_TYPE("NETWORKING"), // MEMORY, MEMORY_DDR3, MEMORY_QDR, NETWORKING, OVERSAMPLE
+                .IOBDELAY("IFD"), // NONE, BOTH, IBUF, IFD
+                .NUM_CE(1),// Number of clock enables (1,2)
+                .OFB_USED("FALSE"), // Select OFB path (FALSE, TRUE)
+                // SRVAL_Q1 - SRVAL_Q4: Q output values when SR is used (0/1)
+                .SRVAL_Q1(1'b0),
+                .SRVAL_Q2(1'b0),
+                .SRVAL_Q3(1'b0),
+                .SRVAL_Q4(1'b0)
+            )
+            ISERDESE2_data (
+                .O(),
+                // 1-bit output: Combinatorial output
+                // Q1 - Q8: 1-bit (each) output: Registered data outputs
+                .Q1(o_controller_iserdes_data[(DQ_BITS*LANES)*7 + gen_index]),//56
+                .Q2(o_controller_iserdes_data[(DQ_BITS*LANES)*6 + gen_index]), //48
+                .Q3(o_controller_iserdes_data[(DQ_BITS*LANES)*5 + gen_index]),
+                .Q4(o_controller_iserdes_data[(DQ_BITS*LANES)*4 + gen_index]),   
+                .Q5(o_controller_iserdes_data[(DQ_BITS*LANES)*3 + gen_index]),
+                .Q6(o_controller_iserdes_data[(DQ_BITS*LANES)*2 + gen_index]),
+                .Q7(o_controller_iserdes_data[(DQ_BITS*LANES)*1 + gen_index]), 
+                .Q8(o_controller_iserdes_data[(DQ_BITS*LANES)*0 + gen_index]),
+                // SHIFTOUT1-SHIFTOUT2: 1-bit (each) output: Data width expansion output ports
+                .SHIFTOUT1(),
+                .SHIFTOUT2(),
+                .BITSLIP(i_controller_bitslip[gen_index/8]),
+                // 1-bit input: The BITSLIP pin performs a Bitslip operation synchronous to
+                // CLKDIV when asserted (active High). Subsequently, the data seen on the Q1
+                // to Q8 output ports will shift, as in a barrel-shifter operation, one
+                // position every time Bitslip is invoked (DDR operation is different from
+                // SDR).
+                // CE1, CE2: 1-bit (each) input: Data register clock enable inputs
+                .CE1(1'b1),
+                .CE2(1'b1),
+                .CLKDIVP(), // 1-bit input: TBD
+                // Clocks: 1-bit (each) input: ISERDESE2 clock input ports
+                .CLK(i_ddr3_clk), // 1-bit input: High-speed clock
+                .CLKB(!i_ddr3_clk), // 1-bit input: High-speed secondary clock
+                .CLKDIV(i_controller_clk), // 1-bit input: Divided clock
+                .OCLK(), // 1-bit input: High speed output clock used when INTERFACE_TYPE="MEMORY"
+                // Dynamic Clock Inversions: 1-bit (each) input: Dynamic clock inversion pins to switch clock polarity
+                .DYNCLKDIVSEL(), // 1-bit input: Dynamic CLKDIV inversion
+                .DYNCLKSEL(), // 1-bit input: Dynamic CLK/CLKB inversion
+                // Input Data: 1-bit (each) input: ISERDESE2 data input ports
+                .D(), // 1-bit input: Data input
+                .DDLY(idelay_data[gen_index]), // 1-bit input: Serial data from IDELAYE2
+                .OFB(), // 1-bit input: Data feedback from OSERDESE2
+                .OCLKB(), // 1-bit input: High speed negative edge output clock
+                .RST(sync_rst), // 1-bit input: Active high asynchronous reset
+                // SHIFTIN1-SHIFTIN2: 1-bit (each) input: Data width expansion input ports
+                .SHIFTIN1(),
+                .SHIFTIN2()
+            );
+            // End of ISERDESE2_inst instantiation
+  
+        end
+        
+        // data mask: oserdes -> odelay -> obuf
+        for(gen_index = 0; gen_index < LANES; gen_index = gen_index + 1) begin
+ 
+            
+            if(ODELAY_SUPPORTED) begin
+                // OSERDESE2: Output SERial/DESerializer with bitslip
+                //7 Series
+                // Xilinx HDL Libraries Guide, version 13.4
+                `ifndef SIM_MODEL
+                    OSERDESE2 #(
+                `else 
+                    OSERDESE2_model #(
+                `endif
+                    .DATA_RATE_OQ("DDR"), // DDR, SDR
+                    .DATA_RATE_TQ("BUF"), // DDR, SDR
+                    .DATA_WIDTH(8), // Parallel data width (2-8,10,14)
+                    .INIT_OQ(1'b0), // Initial value of OQ output (1'b0,1'b1)
+                    .TRISTATE_WIDTH(1)
+                )
+                OSERDESE2_dm(
+                    .OFB(oserdes_dm[gen_index]), // 1-bit output: Feedback path for data
+                    .OQ(), // 1-bit output: Data path output
+                    .CLK(i_ddr3_clk), // 1-bit input: High speed clock
+                    .CLKDIV(i_controller_clk), // 1-bit input: Divided clock
+                    // D1 - D8: 1-bit (each) input: Parallel data inputs (1-bit each)
+                    .D1(i_controller_dm[gen_index + LANES*0]),
+                    .D2(i_controller_dm[gen_index + LANES*1]),
+                    .D3(i_controller_dm[gen_index + LANES*2]),
+                    .D4(i_controller_dm[gen_index + LANES*3]),
+                    .D5(i_controller_dm[gen_index + LANES*4]),
+                    .D6(i_controller_dm[gen_index + LANES*5]),
+                    .D7(i_controller_dm[gen_index + LANES*6]),
+                    .D8(i_controller_dm[gen_index + LANES*7]), 
+                    .TCE(1'b0),
+                    .OCE(1'b1), // 1-bit input: Output data clock enable
+                    .RST(sync_rst), // 1-bit input: Reset
+                     // unused signals but were added here to make vivado happy
+                    .SHIFTOUT1(), // SHIFTOUT1 / SHIFTOUT2: 1-bit (each) output: Data output expansion (1-bit each)
+                    .SHIFTOUT2(),
+                    .TBYTEOUT(), // 1-bit output: Byte group tristate
+                    .TFB(), // 1-bit output: 3-state control
+                    .TQ(), // 1-bit output: 3-state control
+                    // SHIFTIN1 / SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each)
+                    .SHIFTIN1(0),
+                    .SHIFTIN2(0),
+                    // T1 - T4: 1-bit (each) input: Parallel 3-state inputs
+                    .T1(0),
+                    .T2(0),
+                    .T3(0),
+                    .T4(0),
+                    .TBYTEIN(0)
+                    // 1-bit input: Byte group tristate
+                );
+                // End of OSERDESE2_inst instantiation
+            
+                // ODELAYE2: Output Fixed or Variable Delay Element
+                // 7 Series
+                // Xilinx HDL Libraries Guide, version 13.4
+                //odelay adds an insertion delay of 600ps to the actual delay setting: https://support.xilinx.com/s/article/42133?language=en_US
+                //Delay the DQ
+                // Delay resolution: 1/(32 x 2 x F REF ) = 78.125ps
+                (* IODELAY_GROUP="DDR3-GROUP" *)
+                `ifndef SIM_MODEL
+                    ODELAYE2 #(
+                `else 
+                    ODELAYE2_model #(
+                `endif
+                    .DELAY_SRC("ODATAIN"), // Delay input (ODATAIN, CLKIN)
+                    .HIGH_PERFORMANCE_MODE("TRUE"), // Reduced jitter to 5ps ("TRUE"), Reduced power but high jitter 9ns ("FALSE")
+                    .ODELAY_TYPE("VAR_LOAD"), // FIXED, VARIABLE, VAR_LOAD, VAR_LOAD_PIPE
+                    .ODELAY_VALUE(DATA_ODELAY_TAP), // Output delay tap setting (0-31)
+                    .REFCLK_FREQUENCY(200.0), // IDELAYCTRL clock input frequency in MHz (190.0-210.0).
+                    .SIGNAL_PATTERN("DATA") // DATA, CLOCK input signal
+                )
+                ODELAYE2_dm (
+                    .CNTVALUEOUT(), // 5-bit output: Counter value output
+                    .DATAOUT(odelay_dm[gen_index]), // 1-bit output: Delayed data/clock output
+                    .C(i_controller_clk), // 1-bit input: Clock input, when using OSERDESE2, C is connected to CLKDIV
+                    .CE(1'b0), // 1-bit input: Active high enable increment/decrement input
+                    .CINVCTRL(1'b0), // 1-bit input: Dynamic clock inversion input
+                    .CLKIN(1'b0), // 1-bit input: Clock delay input
+                    .CNTVALUEIN(i_controller_odelay_data_cntvaluein), // 5-bit input: Counter value input
+                    .INC(1'b0), // 1-bit input: Increment / Decrement tap delay input
+                    .LD(i_controller_odelay_data_ld[gen_index]), // 1-bit input: Loads ODELAY_VALUE tap delay in VARIABLE mode, in VAR_LOAD or
+                                // VAR_LOAD_PIPE mode, loads the value of CNTVALUEIN
+                    .LDPIPEEN(1'b0), // 1-bit input: Enables the pipeline register to load data
+                    .ODATAIN(oserdes_dm[gen_index]), // 1-bit input: Output delay data input
+                    .REGRST(1'b0) // 1-bit input: Active-high reset tap-delay input
+                );
+                
+                // OBUF: Single-ended Output Buffer
+                // 7 Series
+                // Xilinx HDL Libraries Guide, version 13.4
+                `ifndef SIM_MODEL
+                    OBUF #(
+                `else 
+                    OBUF_model #(
+                `endif
+                //.IOSTANDARD("SSTL_15"), // Specify the output I/O standard
+                .SLEW("FAST") // Specify the output slew rate
+                ) OBUF_dm (
+                    .O(o_ddr3_dm[gen_index]), // Buffer output (connect directly to top-level port)
+                    .I(odelay_dm[gen_index]) // Buffer input
+                );
+                // End of OBUF_inst instantiation
+            end
+            else begin
+                // OSERDESE2: Output SERial/DESerializer with bitslip
+                //7 Series
+                // Xilinx HDL Libraries Guide, version 13.4
+                `ifndef SIM_MODEL
+                    OSERDESE2 #(
+                `else 
+                    OSERDESE2_model #(
+                `endif
+                    .DATA_RATE_OQ("DDR"), // DDR, SDR
+                    .DATA_RATE_TQ("BUF"), // DDR, SDR
+                    .DATA_WIDTH(8), // Parallel data width (2-8,10,14)
+                    .INIT_OQ(1'b0), // Initial value of OQ output (1'b0,1'b1)
+                    .TRISTATE_WIDTH(1)
+                )
+                OSERDESE2_dm(
+                    .OFB(), // 1-bit output: Feedback path for data
+                    .OQ(oserdes_dm[gen_index]), // 1-bit output: Data path output
+                    .CLK(i_ddr3_clk_90), // 1-bit input: High speed clock
+                    .CLKDIV(i_controller_clk), // 1-bit input: Divided clock
+                    // D1 - D8: 1-bit (each) input: Parallel data inputs (1-bit each)
+                    .D1(i_controller_dm[gen_index + LANES*0]),
+                    .D2(i_controller_dm[gen_index + LANES*1]),
+                    .D3(i_controller_dm[gen_index + LANES*2]),
+                    .D4(i_controller_dm[gen_index + LANES*3]),
+                    .D5(i_controller_dm[gen_index + LANES*4]),
+                    .D6(i_controller_dm[gen_index + LANES*5]),
+                    .D7(i_controller_dm[gen_index + LANES*6]),
+                    .D8(i_controller_dm[gen_index + LANES*7]), 
+                    .TCE(1'b0),
+                    .OCE(1'b1), // 1-bit input: Output data clock enable
+                    .RST(sync_rst), // 1-bit input: Reset
+                     // unused signals but were added here to make vivado happy
+                    .SHIFTOUT1(), // SHIFTOUT1 / SHIFTOUT2: 1-bit (each) output: Data output expansion (1-bit each)
+                    .SHIFTOUT2(),
+                    .TBYTEOUT(), // 1-bit output: Byte group tristate
+                    .TFB(), // 1-bit output: 3-state control
+                    .TQ(), // 1-bit output: 3-state control
+                    // SHIFTIN1 / SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each)
+                    .SHIFTIN1(0),
+                    .SHIFTIN2(0),
+                    // T1 - T4: 1-bit (each) input: Parallel 3-state inputs
+                    .T1(0),
+                    .T2(0),
+                    .T3(0),
+                    .T4(0),
+                    .TBYTEIN(0)
+                    // 1-bit input: Byte group tristate
+                );
+                // End of OSERDESE2_inst instantiation
+            
+                // OBUF: Single-ended Output Buffer
+                // 7 Series
+                // Xilinx HDL Libraries Guide, version 13.4
+                `ifndef SIM_MODEL
+                    OBUF #(
+                `else 
+                    OBUF_model #(
+                `endif
+                //.IOSTANDARD("SSTL_15"), // Specify the output I/O standard
+                .SLEW("FAST") // Specify the output slew rate
+                ) OBUF_dm (
+                    .O(o_ddr3_dm[gen_index]), // Buffer output (connect directly to top-level port)
+                    .I(oserdes_dm[gen_index]) // Buffer input
+                );
+                // End of OBUF_inst instantiation
+            
+            end
+        end
+
+        // dqs: odelay -> iobuf
+        for(gen_index = 0; gen_index < LANES; gen_index = gen_index + 1) begin
+`ifndef DEBUG_DQS  //remove the logic for dqs if needs to be debugged (directed to output instead)  
+            if(ODELAY_SUPPORTED) begin 
+                // OSERDESE2: Output SERial/DESerializer with bitslip
+                //7 Series
+                // Xilinx HDL Libraries Guide, version 13.4
+                `ifndef SIM_MODEL
+                    OSERDESE2 #(
+                `else 
+                    OSERDESE2_model #(
+                `endif
+                    .DATA_RATE_OQ("DDR"), // DDR, SDR
+                    .DATA_RATE_TQ("BUF"), // DDR, SDR
+                    .DATA_WIDTH(8), // Parallel data width (2-8,10,14)
+                    .INIT_OQ(1'b1), // Initial value of OQ output (1'b0,1'b1)
+                    .TRISTATE_WIDTH(1)
+                )
+                OSERDESE2_dqs(
+                    .OFB(oserdes_dqs[gen_index]), // 1-bit output: Feedback path for data
+                    .OQ(), // 1-bit output: Data path output
+                    .TQ(oserdes_dqs_tri_control[gen_index]),
+                    .CLK(i_ddr3_clk), // 1-bit input: High speed clock
+                    .CLKDIV(i_controller_clk), // 1-bit input: Divided clock
+                    // D1 - D8: 1-bit (each) input: Parallel data inputs (1-bit each)
+                    .D1(1'b1 && (i_controller_toggle_dqs || toggle_dqs_q)), //the last part will still have half dqs series
+                    .D2(1'b0 && (i_controller_toggle_dqs || toggle_dqs_q)),
+                    .D3(1'b1 && (i_controller_toggle_dqs || toggle_dqs_q) && !i_controller_write_leveling_calib),
+                    .D4(1'b0 && (i_controller_toggle_dqs || toggle_dqs_q)),
+                    .D5(1'b1 && i_controller_toggle_dqs && !i_controller_write_leveling_calib),
+                    .D6(1'b0 && i_controller_toggle_dqs),
+                    .D7(1'b1 && i_controller_toggle_dqs && !i_controller_write_leveling_calib),
+                    .D8(1'b0 && i_controller_toggle_dqs),
+                    .T1(i_controller_dqs_tri_control),
+                    .TCE(1'b1),
+                    .OCE(1'b1), // 1-bit input: Output data clock enable
+                    .RST(sync_rst), // 1-bit input: Reset
+                     // unused signals but were added here to make vivado happy
+                    .SHIFTOUT1(), // SHIFTOUT1 / SHIFTOUT2: 1-bit (each) output: Data output expansion (1-bit each)
+                    .SHIFTOUT2(),
+                    .TBYTEOUT(), // 1-bit output: Byte group tristate
+                    .TFB(), // 1-bit output: 3-state control
+                    // SHIFTIN1 / SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each)
+                    .SHIFTIN1(0),
+                    .SHIFTIN2(0),
+                    // T1 - T4: 1-bit (each) input: Parallel 3-state inputs
+                    .T2(0),
+                    .T3(0),
+                    .T4(0),
+                    .TBYTEIN(0)
+                    // 1-bit input: Byte group tristate
+                );
+                // End of OSERDESE2_inst instantiation
+            
+            
+                // ODELAYE2: Output Fixed or Variable Delay Element
+                // 7 Series
+                // Xilinx HDL Libraries Guide, version 13.4
+                //Delay the DQ
+                (* IODELAY_GROUP="DDR3-GROUP" *)
+                `ifndef SIM_MODEL
+                    ODELAYE2 #(
+                `else 
+                    ODELAYE2_model #(
+                `endif
+                    .DELAY_SRC("ODATAIN"), // Delay input (ODATAIN, CLKIN)
+                    .HIGH_PERFORMANCE_MODE("TRUE"), // Reduced jitter ("TRUE"), Reduced power ("FALSE")
+                    .ODELAY_TYPE("VAR_LOAD"), // FIXED, VARIABLE, VAR_LOAD, VAR_LOAD_PIPE
+                    .ODELAY_VALUE(DQS_ODELAY_TAP), // delay to align odelay_dqs to oserdes_dqs due to 600ps insertion delay: (1/800MHz - 600ps)/78.125ps = 8.32 taps
+                    .REFCLK_FREQUENCY(200.0), // IDELAYCTRL clock input frequency in MHz (190.0-210.0).
+                    .SIGNAL_PATTERN("DATA") // DATA, CLOCK input signal
+                )
+                ODELAYE2_dqs (
+                    .CNTVALUEOUT(), // 5-bit output: Counter value output
+                    .DATAOUT(odelay_dqs[gen_index]), // 1-bit output: Delayed data/clock output
+                    .C(i_controller_clk), // 1-bit input: Clock input, when using OSERDESE2, C is connected to CLKDIV
+                    .CE(1'b0), // 1-bit input: Active high enable increment/decrement input
+                    .CINVCTRL(1'b0), // 1-bit input: Dynamic clock inversion input
+                    .CLKIN(1'b0), // 1-bit input: Clock delay input
+                    .CNTVALUEIN(i_controller_odelay_dqs_cntvaluein), // 5-bit input: Counter value input
+                    .INC(1'b0), // 1-bit input: Increment / Decrement tap delay input
+                    .LD(i_controller_odelay_dqs_ld[gen_index]), // 1-bit input: Loads ODELAY_VALUE tap delay in VARIABLE mode, in VAR_LOAD or
+                                // VAR_LOAD_PIPE mode, loads the value of CNTVALUEIN
+                    .LDPIPEEN(1'b0), // 1-bit input: Enables the pipeline register to load data
+                    .ODATAIN(oserdes_dqs[gen_index]), // 1-bit input: Output delay data input
+                    .REGRST(1'b0) // 1-bit input: Active-high reset tap-delay input
+                );
+                
+                if(USE_IO_TERMINATION) begin 
+                    // IOBUFDS_DCIEN: Differential Bi-directional Buffer with Digital Controlled Impedance (DCI)
+                    // and Input path enable/disable
+                    // May only be placed in High Performance (HP) Banks
+                    // 7 Series
+                    // Xilinx HDL Libraries Guide, version 13.4
+                    `ifndef SIM_MODEL
+                        IOBUFDS_DCIEN #(
+                    `else 
+                        IOBUFDS_DCIEN_model #(
+                    `endif
+                        .IBUF_LOW_PWR("FALSE"), // Low Power - "TRUE", High Performance = "FALSE"
+                        .SLEW("FAST"), // Specify the output slew rate
+                        .USE_IBUFDISABLE("FALSE") // Use IBUFDISABLE function, "TRUE" or "FALSE"
+                    ) IOBUFDS_DCIEN_inst (
+                        .O(read_dqs[gen_index]),  // Buffer output
+                        .IO(io_ddr3_dqs[gen_index]), // Diff_p inout (connect directly to top-level port)
+                        .IOB(io_ddr3_dqs_n[gen_index]), // Diff_n inout (connect directly to top-level port)
+                        .DCITERMDISABLE(1'b0), // DCI Termination enable input
+                        .I(odelay_dqs[gen_index]), // Buffer input
+                        .IBUFDISABLE(1'b0), // Input disable input, low=disable
+                        .T(oserdes_dqs_tri_control[gen_index]) // 3-state enable input, high=input, low=output
+                    );
+                    // End of IOBUFDS_DCIEN_inst instantiation
+
+                end
+                else begin
+                    // IOBUFDS: Differential Bi-directional Buffer
+                    //7 Series
+                    // Xilinx HDL Libraries Guide, version 13.4
+                    `ifndef SIM_MODEL
+                        IOBUFDS #(
+                    `else 
+                        IOBUFDS_model #(
+                    `endif
+                        //.DIFF_TERM("FALSE"), // Differential Termination ("TRUE"/"FALSE")
+                        .IBUF_LOW_PWR("FALSE") // Low Power - "TRUE", High Performance = "FALSE"
+                        //.IOSTANDARD("DIFF_SSTL15") // Specify the I/O standard. CONSULT WITH DATASHEET
+                        //.SLEW("FAST") // Specify the output slew rate
+                    ) IOBUFDS_dqs (
+                        .O(read_dqs[gen_index]), // Buffer output
+                        .IO(io_ddr3_dqs[gen_index]), // Diff_p inout (connect directly to top-level port)
+                        .IOB(io_ddr3_dqs_n[gen_index]), // Diff_n inout (connect directly to top-level port)
+                        .I(odelay_dqs[gen_index]), // Buffer input
+                        .T(/*!dqs_tri_control[gen_index]*/oserdes_dqs_tri_control[gen_index]) // 3-state enable input, high=input, low=output
+                    ); // End of IOBUFDS_inst instantiation
+                end
+                
+            end
+            
+            else begin //ODELAY not supported
+                // OSERDESE2: Output SERial/DESerializer with bitslip
+                //7 Series
+                // Xilinx HDL Libraries Guide, version 13.4
+                `ifndef SIM_MODEL
+                    OSERDESE2 #(
+                `else 
+                    OSERDESE2_model #(
+                `endif
+                    .DATA_RATE_OQ("DDR"), // DDR, SDR
+                    .DATA_RATE_TQ("BUF"), // DDR, SDR
+                    .DATA_WIDTH(8), // Parallel data width (2-8,10,14)
+                    .INIT_OQ(1'b1), // Initial value of OQ output (1'b0,1'b1)
+                    .TRISTATE_WIDTH(1)
+                )
+                OSERDESE2_dqs(
+                    .OFB(), // 1-bit output: Feedback path for data
+                    .OQ(oserdes_dqs[gen_index]), // 1-bit output: Data path output
+                    .TQ(oserdes_dqs_tri_control[gen_index]),
+                    .CLK(!i_ddr3_clk), // 1-bit input: High speed clock
+                    .CLKDIV(i_controller_clk), // 1-bit input: Divided clock
+                    // D1 - D8: 1-bit (each) input: Parallel data inputs (1-bit each)
+                    .D1(1'b1 && (i_controller_toggle_dqs || toggle_dqs_q)), //the last part will still have half dqs series
+                    .D2(1'b0 && (i_controller_toggle_dqs || toggle_dqs_q)),
+                    .D3(1'b1 && (i_controller_toggle_dqs || toggle_dqs_q) && !i_controller_write_leveling_calib),
+                    .D4(1'b0 && (i_controller_toggle_dqs || toggle_dqs_q)),
+                    .D5(1'b1 && i_controller_toggle_dqs && !i_controller_write_leveling_calib),
+                    .D6(1'b0 && i_controller_toggle_dqs),
+                    .D7(1'b1 && i_controller_toggle_dqs && !i_controller_write_leveling_calib),
+                    .D8(1'b0 && i_controller_toggle_dqs),
+                    .T1(i_controller_dqs_tri_control),
+                    .TCE(1'b1),
+                    .OCE(1'b1), // 1-bit input: Output data clock enable
+                    .RST(sync_rst), // 1-bit input: Reset
+                     // unused signals but were added here to make vivado happy
+                    .SHIFTOUT1(), // SHIFTOUT1 / SHIFTOUT2: 1-bit (each) output: Data output expansion (1-bit each)
+                    .SHIFTOUT2(),
+                    .TBYTEOUT(), // 1-bit output: Byte group tristate
+                    .TFB(), // 1-bit output: 3-state control
+                    // SHIFTIN1 / SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each)
+                    .SHIFTIN1(0),
+                    .SHIFTIN2(0),
+                    // T1 - T4: 1-bit (each) input: Parallel 3-state inputs
+                    .T2(0),
+                    .T3(0),
+                    .T4(0),
+                    .TBYTEIN(0)
+                    // 1-bit input: Byte group tristate
+                );
+                // End of OSERDESE2_inst instantiation
+                
+                // IOBUFDS: Differential Bi-directional Buffer
+                //7 Series
+                // Xilinx HDL Libraries Guide, version 13.4
+                `ifndef SIM_MODEL
+                    IOBUFDS #(
+                `else 
+                    IOBUFDS_model #(
+                `endif
+                    //.DIFF_TERM("FALSE"), // Differential Termination ("TRUE"/"FALSE")
+                    .IBUF_LOW_PWR("FALSE") // Low Power - "TRUE", High Performance = "FALSE"
+                    //.IOSTANDARD("DIFF_SSTL15") // Specify the I/O standard. CONSULT WITH DATASHEET
+                    //.SLEW("FAST") // Specify the output slew rate
+                ) IOBUFDS_dqs (
+                    .O(read_dqs[gen_index]), // Buffer output
+                    .IO(io_ddr3_dqs[gen_index]), // Diff_p inout (connect directly to top-level port)
+                    .IOB(io_ddr3_dqs_n[gen_index]), // Diff_n inout (connect directly to top-level port)
+                    .I(oserdes_dqs[gen_index]), // Buffer input
+                    .T(/*!dqs_tri_control[gen_index]*/oserdes_dqs_tri_control[gen_index]) // 3-state enable input, high=input, low=output
+                ); // End of IOBUFDS_inst instantiation
+                
+            end
+            
+            // IDELAYE2: Input Fixed or Variable Delay Element
+            // 7 Series
+            // Xilinx HDL Libraries Guide, version 13.4
+            (* IODELAY_GROUP="DDR3-GROUP" *)
+            `ifndef SIM_MODEL
+                IDELAYE2 #(
+            `else 
+                IDELAYE2_model #(
+            `endif
+                .DELAY_SRC("IDATAIN"), // Delay input (IDATAIN, DATAIN)
+                .HIGH_PERFORMANCE_MODE("TRUE"), //Reduced jitter ("TRUE"), Reduced power ("FALSE")
+                .IDELAY_TYPE("VAR_LOAD"), //FIXED, VARIABLE, VAR_LOAD, VAR_LOAD_PIPE
+                .IDELAY_VALUE(DQS_IDELAY_TAP), //Input delay tap setting (0-31)
+                .PIPE_SEL("FALSE"),  //Select pipelined mode, FALSE, TRUE
+                .REFCLK_FREQUENCY(200.0), //IDELAYCTRL clock input frequency in MHz (190.0-210.0).
+                .SIGNAL_PATTERN("CLOCK") //DATA, CLOCK input signal
+            )
+            IDELAYE2_dqs (
+                .CNTVALUEOUT(), // 5-bit output: Counter value output
+                .DATAOUT(idelay_dqs[gen_index]), // 1-bit output: Delayed data output
+                .C(i_controller_clk), // 1-bit input: Clock input
+                .CE(1'b0), // 1-bit input: Active high enable increment/decrement input
+                .CINVCTRL(1'b0),// 1-bit input: Dynamic clock inversion input
+                .CNTVALUEIN(i_controller_idelay_dqs_cntvaluein), // 5-bit input: Counter value input
+                .DATAIN(), //1-bit input: Internal delay data input
+                .IDATAIN(read_dqs[gen_index]), // 1-bit input: Data input from the I/O
+                .INC(1'b0), // 1-bit input: Increment / Decrement tap delay input
+                .LD(i_controller_idelay_dqs_ld[gen_index]), // 1-bit input: Load IDELAY_VALUE input
+                .LDPIPEEN(1'b0), // 1-bit input: Enable PIPELINE register to load data input
+                .REGRST(1'b0) // 1-bit input: Active-high reset tap-delay input
+            );
+            // End of IDELAYE2_inst instantiation
+            
+             
+              // End of IOBUF_inst instantiation                 
+            // ISERDESE2: Input SERial/DESerializer with bitslip
+            //7 Series
+            // Xilinx HDL Libraries Guide, version 13.4
+            `ifndef SIM_MODEL
+                ISERDESE2 #(
+            `else 
+                ISERDESE2_model #(
+            `endif
+                .DATA_RATE("DDR"), // DDR, SDR
+                .DATA_WIDTH(serdes_ratio*2), // Parallel data width (2-8,10,14)
+                // INIT_Q1 - INIT_Q4: Initial value on the Q outputs (0/1)
+                .INIT_Q1(1'b0),
+                .INIT_Q2(1'b0),
+                .INIT_Q3(1'b0),
+                .INIT_Q4(1'b0),
+                .INTERFACE_TYPE("NETWORKING"), // MEMORY, MEMORY_DDR3, MEMORY_QDR, NETWORKING, OVERSAMPLE
+                .IOBDELAY("IFD"), // NONE, BOTH, IBUF, IFD
+                .NUM_CE(1),// Number of clock enables (1,2)
+                .OFB_USED("FALSE"), // Select OFB path (FALSE, TRUE)
+                // SRVAL_Q1 - SRVAL_Q4: Q output values when SR is used (0/1)
+                .SRVAL_Q1(1'b0),
+                .SRVAL_Q2(1'b0),
+                .SRVAL_Q3(1'b0),
+                .SRVAL_Q4(1'b0)
+            )
+            ISERDESE2_dqs (
+                .O(),
+                // 1-bit output: Combinatorial output
+                // Q1 - Q8: 1-bit (each) output: Registered data outputs
+                .Q1(o_controller_iserdes_dqs[serdes_ratio*2*gen_index + 7]),
+                .Q2(o_controller_iserdes_dqs[serdes_ratio*2*gen_index + 6]),
+                .Q3(o_controller_iserdes_dqs[serdes_ratio*2*gen_index + 5]),
+                .Q4(o_controller_iserdes_dqs[serdes_ratio*2*gen_index + 4]),   
+                .Q5(o_controller_iserdes_dqs[serdes_ratio*2*gen_index + 3]),
+                .Q6(o_controller_iserdes_dqs[serdes_ratio*2*gen_index + 2]), //
+                .Q7(o_controller_iserdes_dqs[serdes_ratio*2*gen_index + 1]), //3
+                .Q8(o_controller_iserdes_dqs[serdes_ratio*2*gen_index + 0]), //2
+                // SHIFTOUT1-SHIFTOUT2: 1-bit (each) output: Data width expansion output ports
+                .SHIFTOUT1(),
+                .SHIFTOUT2(),
+                .BITSLIP(i_controller_bitslip[gen_index]),
+                // 1-bit input: The BITSLIP pin performs a Bitslip operation synchronous to
+                // CLKDIV when asserted (active High). Subsequently, the data seen on the Q1
+                // to Q8 output ports will shift, as in a barrel-shifter operation, one
+                // position every time Bitslip is invoked (DDR operation is different from
+                // SDR).
+                // CE1, CE2: 1-bit (each) input: Data register clock enable inputs
+                .CE1(1'b1),
+                .CE2(1'b1),
+                .CLKDIVP(), // 1-bit input: TBD
+                // Clocks: 1-bit (each) input: ISERDESE2 clock input ports
+                .CLK(i_ddr3_clk), // 1-bit input: High-speed clock
+                .CLKB(!i_ddr3_clk), // 1-bit input: High-speed secondary clock
+                .CLKDIV(i_controller_clk), // 1-bit input: Divided clock
+                .OCLK(), // 1-bit input: High speed output clock used when INTERFACE_TYPE="MEMORY"
+                // Dynamic Clock Inversions: 1-bit (each) input: Dynamic clock inversion pins to switch clock polarity
+                .DYNCLKDIVSEL(), // 1-bit input: Dynamic CLKDIV inversion
+                .DYNCLKSEL(), // 1-bit input: Dynamic CLK/CLKB inversion
+                // Input Data: 1-bit (each) input: ISERDESE2 data input ports
+                .D(), // 1-bit input: Data input
+                .DDLY(idelay_dqs[gen_index]), // 1-bit input: Serial data from IDELAYE2
+                .OFB(), // 1-bit input: Data feedback from OSERDESE2
+                .OCLKB(), // 1-bit input: High speed negative edge output clock
+                .RST(sync_rst), // 1-bit input: Active high asynchronous reset
+                // SHIFTIN1-SHIFTIN2: 1-bit (each) input: Data width expansion input ports
+                .SHIFTIN1(),
+                .SHIFTIN2()
+            );
+            // End of ISERDESE2_inst instantiation
+`endif
+            
+            // generate IOSERDES loopback or not for bitslip training
+            if(NO_IOSERDES_LOOPBACK) begin                    
+                // logic that models OSERDES loopback to ISERDES     
+                // accdg to IOSELECT (UG471) for 7-series:    
+                // " In DDR mode, every Bitslip operation causes the output pattern to alternate between
+                //   a shift right by one and shift left by three"
+                always @(posedge i_controller_clk) begin
+                    if(!i_rst_n || i_controller_reset) begin
+                        o_controller_iserdes_bitslip_reference_reg[(serdes_ratio*2*gen_index + 7) : (serdes_ratio*2*gen_index + 0)] <= 8'b0001_1110;
+                        shift_bitslip_index[gen_index] <= 0;
+                    end
+                    else if(i_controller_bitslip[gen_index]) begin
+                    // if shift_bitslip_index high, shift right by 3, else shift left by 1 (this is reverse of the IOSelect document for ISERDES since vector o_controller_iserdes_bitslip_reference is reversed)
+                        o_controller_iserdes_bitslip_reference_reg[(serdes_ratio*2*gen_index + 7) : (serdes_ratio*2*gen_index + 0)] <= 
+                            shift_bitslip_index[gen_index]? {o_controller_iserdes_bitslip_reference_reg[(serdes_ratio*2*gen_index + 2) : (serdes_ratio*2*gen_index + 0)], o_controller_iserdes_bitslip_reference_reg[(serdes_ratio*2*gen_index + 7) : (serdes_ratio*2*gen_index + 3)]}
+                            : {o_controller_iserdes_bitslip_reference_reg[(serdes_ratio*2*gen_index + 6) : (serdes_ratio*2*gen_index + 0)], o_controller_iserdes_bitslip_reference_reg[(serdes_ratio*2*gen_index + 7)]};
+                        shift_bitslip_index[gen_index] <= !shift_bitslip_index[gen_index];         
+                    end
+                end
+                assign o_controller_iserdes_bitslip_reference = o_controller_iserdes_bitslip_reference_reg;
+            end
+            else begin // OSERDES will loopback to ISERDES for bitslip training    
+                //ISERDES train
+                // End of IOBUF_inst instantiation                 
+                // ISERDESE2: Input SERial/DESerializer with bitslip
+                //7 Series
+                // Xilinx HDL Libraries Guide, version 13.4
+                `ifndef SIM_MODEL
+                    ISERDESE2 #(
+                `else 
+                    ISERDESE2_model #(
+                `endif
+                    .DATA_RATE("DDR"), // DDR, SDR
+                    .DATA_WIDTH(serdes_ratio*2), // Parallel data width (2-8,10,14)
+                    // INIT_Q1 - INIT_Q4: Initial value on the Q outputs (0/1)
+                    .INIT_Q1(1'b0),
+                    .INIT_Q2(1'b0),
+                    .INIT_Q3(1'b0),
+                    .INIT_Q4(1'b0),
+                    .INTERFACE_TYPE("NETWORKING"), // MEMORY, MEMORY_DDR3, MEMORY_QDR, NETWORKING, OVERSAMPLE
+                    .IOBDELAY("NONE"), // NONE, BOTH, IBUF, IFD
+                    .NUM_CE(1),// Number of clock enables (1,2)
+                    .OFB_USED("TRUE"), // Select OFB path (FALSE, TRUE)
+                    // SRVAL_Q1 - SRVAL_Q4: Q output values when SR is used (0/1)
+                    .SRVAL_Q1(1'b0),
+                    .SRVAL_Q2(1'b0),
+                    .SRVAL_Q3(1'b0),
+                    .SRVAL_Q4(1'b0)
+                )
+                ISERDESE2_train (
+                    .O(),
+                    // 1-bit output: Combinatorial output
+                    // Q1 - Q8: 1-bit (each) output: Registered data outputs
+                    .Q1(o_controller_iserdes_bitslip_reference[gen_index*serdes_ratio*2 + 7]),
+                    .Q2(o_controller_iserdes_bitslip_reference[gen_index*serdes_ratio*2 + 6]),
+                    .Q3(o_controller_iserdes_bitslip_reference[gen_index*serdes_ratio*2 + 5]),
+                    .Q4(o_controller_iserdes_bitslip_reference[gen_index*serdes_ratio*2 + 4]),   
+                    .Q5(o_controller_iserdes_bitslip_reference[gen_index*serdes_ratio*2 + 3]),
+                    .Q6(o_controller_iserdes_bitslip_reference[gen_index*serdes_ratio*2 + 2]),
+                    .Q7(o_controller_iserdes_bitslip_reference[gen_index*serdes_ratio*2 + 1]),
+                    .Q8(o_controller_iserdes_bitslip_reference[gen_index*serdes_ratio*2 + 0]),
+                    // SHIFTOUT1-SHIFTOUT2: 1-bit (each) output: Data width expansion output ports
+                    .SHIFTOUT1(),
+                    .SHIFTOUT2(),
+                    .BITSLIP(i_controller_bitslip[gen_index]),
+                    // 1-bit input: The BITSLIP pin performs a Bitslip operation synchronous to
+                    // CLKDIV when asserted (active High). Subsequently, the data seen on the Q1
+                    // to Q8 output ports will shift, as in a barrel-shifter operation, one
+                    // position every time Bitslip is invoked (DDR operation is different from
+                    // SDR).
+                    // CE1, CE2: 1-bit (each) input: Data register clock enable inputs
+                    .CE1(1'b1),
+                    .CE2(1'b1),
+                    .CLKDIVP(), // 1-bit input: TBD
+                    // Clocks: 1-bit (each) input: ISERDESE2 clock input ports
+                    .CLK(i_ddr3_clk), // 1-bit input: High-speed clock
+                    .CLKB(!i_ddr3_clk), // 1-bit input: High-speed secondary clock
+                    .CLKDIV(i_controller_clk), // 1-bit input: Divided clock
+                    .OCLK(), // 1-bit input: High speed output clock used when INTERFACE_TYPE="MEMORY"
+                    // Dynamic Clock Inversions: 1-bit (each) input: Dynamic clock inversion pins to switch clock polarity
+                    .DYNCLKDIVSEL(), // 1-bit input: Dynamic CLKDIV inversion
+                    .DYNCLKSEL(), // 1-bit input: Dynamic CLK/CLKB inversion
+                    // Input Data: 1-bit (each) input: ISERDESE2 data input ports
+                    .D(), // 1-bit input: Data input
+                    .DDLY(), // 1-bit input: Serial data from IDELAYE2
+                    .OFB(oserdes_bitslip_reference[gen_index]), // 1-bit input: Data feedback from OSERDESE2
+                    .OCLKB(), // 1-bit input: High speed negative edge output clock
+                    .RST(sync_rst), // 1-bit input: Active high asynchronous reset
+                    // SHIFTIN1-SHIFTIN2: 1-bit (each) input: Data width expansion input ports
+                    .SHIFTIN1(),
+                    .SHIFTIN2()
+                );
+                // End of ISERDESE2_inst instantiation
+                
+                // OSERDESE2: Output SERial/DESerializer with bitslip
+                //7 Series
+                // Xilinx HDL Libraries Guide, version 13.4
+                `ifndef SIM_MODEL
+                    OSERDESE2 #(
+                `else 
+                    OSERDESE2_model #(
+                `endif
+                    .DATA_RATE_OQ("DDR"), // DDR, SDR
+                    .DATA_RATE_TQ("BUF"), // DDR, SDR
+                    .DATA_WIDTH(8), // Parallel data width (2-8,10,14)
+                    .INIT_OQ(1'b1), // Initial value of OQ output (1'b0,1'b1)
+                    .TRISTATE_WIDTH(1)
+                )
+                OSERDESE2_train(
+                    .OFB(oserdes_bitslip_reference[gen_index]), // 1-bit output: Feedback path for data
+                    .OQ(), // 1-bit output: Data path output
+                    .CLK(i_ddr3_clk), // 1-bit input: High speed clock
+                    .CLKDIV(i_controller_clk), // 1-bit input: Divided clock
+                    // D1 - D8: 1-bit (each) input: Parallel data inputs (1-bit each)
+                    .D1(1'b0),
+                    .D2(1'b0),
+                    .D3(1'b0),
+                    .D4(1'b0),
+                    .D5(1'b1),
+                    .D6(1'b1),
+                    .D7(1'b1),
+                    .D8(1'b1),
+                    .OCE(1'b1), // 1-bit input: Output data clock enable
+                    .RST(sync_rst), // 1-bit input: Reset
+                     // unused signals but were added here to make vivado happy
+                    .SHIFTOUT1(), // SHIFTOUT1 / SHIFTOUT2: 1-bit (each) output: Data output expansion (1-bit each)
+                    .SHIFTOUT2(),
+                    .TBYTEOUT(), // 1-bit output: Byte group tristate
+                    .TFB(), // 1-bit output: 3-state control
+                    .TQ(), // 1-bit output: 3-state control
+                    // SHIFTIN1 / SHIFTIN2: 1-bit (each) input: Data input expansion (1-bit each)
+                    .SHIFTIN1(0),
+                    .SHIFTIN2(0),
+                    // T1 - T4: 1-bit (each) input: Parallel 3-state inputs
+                    .T1(0),
+                    .T2(0),
+                    .T3(0),
+                    .T4(0),
+                    .TBYTEIN(0),
+                    // 1-bit input: Byte group tristate
+                    .TCE(0)
+                    // 1-bit input: 3-state clock enable
+                );
+                // End of OSERDESE2_inst instantiation  
+            end
+            
+        end
+     endgenerate 
+     
+
+    // IDELAYCTRL: IDELAYE2/ODELAYE2 Tap Delay Value Control
+    // 7 Series
+    // Xilinx HDL Libraries Guide, version 13.4
+    (* IODELAY_GROUP="DDR3-GROUP" *)
+    `ifndef SIM_MODEL
+        IDELAYCTRL IDELAYCTRL_inst (
+    `else 
+        IDELAYCTRL_model IDELAYCTRL_inst (
+    `endif
+        .RDY(idelayctrl_rdy), // 1-bit output: Ready output
+        .REFCLK(i_ref_clk), // 1-bit input: Reference clock input.The frequency of REFCLK must be 200 MHz to guarantee the tap-delay value specified in the applicable data sheet.
+        .RST(sync_rst) // 1-bit input: Active high reset input, To ,Minimum Reset pulse width is 52ns
+    );
+    // End of IDELAYCTRL_inst instantiation
+
+
+    // DCIRESET: Digitially Controlled Impedence Reset Component
+    //7 Series
+    // Xilinx HDL Libraries Guide, version 13.4
+    // DCIRESET DCIRESET_inst (
+    //     .LOCKED(dci_locked), // 1-bit output: LOCK status output (When low, DCI I/O impedance is being calibrated and DCI I/Os are unavailable)
+    //     .RST(sync_rst) // 1-bit input: Active-high asynchronous reset input
+    // );
+    assign dci_locked = 1;
+    // End of DCIRESET_inst instantiation
+         
+endmodule

AngeloJacobo_UberDDR3/example_demo/enclustra_kx2_st1/ddr3_test.c

@@ -0,0 +1,114 @@
+/******************************************************************************
+*
+* Copyright (C) 2009 - 2014 Xilinx, Inc.  All rights reserved.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a copy
+* of this software and associated documentation files (the "Software"), to deal
+* in the Software without restriction, including without limitation the rights
+* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+* copies of the Software, and to permit persons to whom the Software is
+* furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included in
+* all copies or substantial portions of the Software.
+*
+* Use of the Software is limited solely to applications:
+* (a) running on a Xilinx device, or
+* (b) that interact with a Xilinx device through a bus or interconnect.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
+* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+* SOFTWARE.
+*
+* Except as contained in this notice, the name of the Xilinx shall not be used
+* in advertising or otherwise to promote the sale, use or other dealings in
+* this Software without prior written authorization from Xilinx.
+*
+******************************************************************************/
+
+/*
+ * helloworld.c: simple test application
+ *
+ * This application configures UART 16550 to baud rate 9600.
+ * PS7 UART (Zynq) is not initialized by this application, since
+ * bootrom/bsp configures it to baud rate 115200
+ *
+ * ------------------------------------------------
+ * | UART TYPE   BAUD RATE                        |
+ * ------------------------------------------------
+ *   uartns550   9600
+ *   uartlite    Configurable only in HW design
+ *   ps7_uart    115200 (configured by bootrom/bsp)
+ */
+#include <stdio.h>
+#include <stdint.h>
+#include "xparameters.h"
+#include "platform.h"
+#include "xil_printf.h"
+#include "xil_io.h"
+#include "sleep.h"
+
+#define DDR3_MONITOR_BASE  0x00010000
+
+#define REG_MATCH_LOW      0x00
+#define REG_MATCH_HIGH     0x04
+#define REG_MISMATCH_LOW   0x08
+#define REG_MISMATCH_HIGH  0x0C
+#define REG_TIMER_LOW      0x10
+#define REG_TIMER_HIGH     0x14
+#define REG_FAULTS         0x18
+
+#define TIMER_FREQ_HZ      100000000  // Adjust based on actual hardware clock
+
+int main()
+{
+    init_platform();
+    print("Hello World\n\r");
+    print("Successfully ran Hello World application\n\r");
+
+    while (1)  // Infinite loop
+    {
+        // Read 64-bit counters
+        uint32_t correct_lower_32 = *(volatile uint32_t *)(DDR3_MONITOR_BASE + REG_MATCH_LOW);
+        uint32_t correct_upper_32 = *(volatile uint32_t *)(DDR3_MONITOR_BASE + REG_MATCH_HIGH);
+        uint32_t wrong_lower_32   = *(volatile uint32_t *)(DDR3_MONITOR_BASE + REG_MISMATCH_LOW);
+        uint32_t wrong_upper_32   = *(volatile uint32_t *)(DDR3_MONITOR_BASE + REG_MISMATCH_HIGH);
+        uint32_t timer_lower_32   = *(volatile uint32_t *)(DDR3_MONITOR_BASE + REG_TIMER_LOW);
+        uint32_t timer_upper_32   = *(volatile uint32_t *)(DDR3_MONITOR_BASE + REG_TIMER_HIGH);
+        uint32_t injected_faults  = *(volatile uint32_t *)(DDR3_MONITOR_BASE + REG_FAULTS);
+
+        // Combine into 64-bit values
+        long long match_count    = ((long long) correct_upper_32 << 32) | correct_lower_32;
+        long long mismatch_count = ((long long) wrong_upper_32 << 32) | wrong_lower_32;
+        long long timer_count    = ((long long) timer_upper_32 << 32) | timer_lower_32;
+
+        // Convert timer count to time in days, hours, and minutes
+        long long elapsed_seconds = timer_count / TIMER_FREQ_HZ;
+        uint32_t days    = elapsed_seconds / (24 * 3600);
+        uint32_t hours   = (elapsed_seconds % (24 * 3600)) / 3600;
+        uint32_t minutes = (elapsed_seconds % 3600) / 60;
+
+        // Print results
+        xil_printf("\n=============================\n\r");
+        xil_printf("        SYSTEM STATUS        \n\r");
+        xil_printf("=============================\n\r");
+        xil_printf(" Matched Reads   : %u M\n\r", match_count / 1000000);
+        xil_printf(" Mismatched Reads: %u \n\r", mismatch_count);
+        xil_printf(" Injected Faults : %u\n\r", injected_faults);
+        xil_printf("-----------------------------\n\r");
+        xil_printf(" Elapsed Time    : %u days, %u hours, %u minutes\n\r", days, hours, minutes);
+        xil_printf("=============================\n\r\n");
+
+
+
+        // Wait 1 second
+        usleep(1000000);
+    }
+
+    cleanup_platform();
+    return 0;  // (Will never reach here due to infinite loop)
+}

AngeloJacobo_UberDDR3/example_demo/enclustra_kx2_st1/ddr3_test.v

@@ -0,0 +1,379 @@
+////////////////////////////////////////////////////////////////////////////////
+//
+// Filename: ddr3_test.v
+// Project: Test the UberDDR3 by sending traffic via the Wishbone interface
+//
+// Purpose: Sends traffic over Wishbone interface of UberDDR3. This has 3 tests:
+//  - burst write/read
+//  - random write/read
+//  - alternating write/read
+// Uses MicroBlaze to report via UART the number of read matches, mismatches, and
+// total time elapsed. Report summary is sent every second.
+//
+// Engineer: Angelo C. Jacobo
+//
+////////////////////////////////////////////////////////////////////////////////
+//
+// Copyright (C) 2023-2025  Angelo Jacobo
+// 
+//     This program is free software: you can redistribute it and/or modify
+//     it under the terms of the GNU General Public License as published by
+//     the Free Software Foundation, either version 3 of the License, or
+//     (at your option) any later version.
+// 
+//     This program is distributed in the hope that it will be useful,
+//     but WITHOUT ANY WARRANTY; without even the implied warranty of
+//     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//     GNU General Public License for more details.
+// 
+//     You should have received a copy of the GNU General Public License
+//     along with this program.  If not, see <https://www.gnu.org/licenses/>.
+//
+////////////////////////////////////////////////////////////////////////////////
+
+// `default_nettype none
+`timescale 1ps / 1ps
+
+module ddr3_test #(
+    parameter   WB_ADDR_BITS = 25,
+                WB_DATA_BITS = 512,
+                WB_SEL_BITS = WB_DATA_BITS / 8,
+                AUX_WIDTH = 4,
+                DATA_MASK = 1,
+    parameter[0:0] MICRON_SIM = 0
+    ) 
+    (
+        input wire i_clk, // ddr3 test clock
+        input wire i_clk100, // microblaze clock
+        input wire i_rst_n,
+        //
+        // Wishbone inputs
+        output reg o_wb_cyc, //bus cycle active (1 = normal operation, 0 = all ongoing transaction are to be cancelled)
+        output reg o_wb_stb, //request a transfer
+        output reg o_wb_we, //write-enable (1 = write, 0 = read)
+        output reg[WB_ADDR_BITS - 1:0] o_wb_addr, //burst-addressable {row,bank,col} 
+        output reg[WB_DATA_BITS - 1:0] o_wb_data, //write data, for a 4:1 controller data width is 8 times the number of pins on the device
+        output reg[WB_SEL_BITS - 1:0] o_wb_sel, //byte strobe for write (1 = write the byte)
+        output reg[AUX_WIDTH - 1:0]  o_aux, //for AXI-interface compatibility (given upon strobe)
+        //
+        // Wishbone outputs
+        input wire i_wb_stall, //1 = busy, cannot accept requests
+        input wire i_wb_ack, //1 = read/write request has completed
+        input wire i_wb_err, //1 = Error due to ECC double bit error (fixed to 0 if WB_ERROR = 0)
+        input wire[WB_DATA_BITS - 1:0] i_wb_data, //read data, for a 4:1 controller data width is 8 times the number of pins on the device
+        input wire[AUX_WIDTH - 1:0]  i_aux, //for AXI-interface compatibility (given upon strobe)
+        //
+        // Done Calibration pin
+        input wire i_calib_complete,
+        // 
+        // UART line
+        input wire rx,
+	    output wire tx,
+        // Button for fault-injection
+        input wire btn,
+        //
+        // Debug
+        output wire timer_pulse,
+        output wire wrong_data_counter_non_zero
+    );
+    localparam IDLE=0,
+                BURST_WRITE=1,
+                BURST_READ=2,
+                RANDOM_WRITE=3,
+                RANDOM_READ=4,
+                ALTERNATE_WRITE_READ=5,
+                DONE_TEST=6;
+    localparam SIM_ADDRESS_INCR_LOG2 = WB_ADDR_BITS-2-6; // 2^(WB_ADDR_BITS-2)/64
+    localparam HALF_ADDRESS = 13;
+    localparam SIM_ADDRESS_START = {(WB_ADDR_BITS){1'b1}} - 99; // minus odd number so result is even (similar to default address start of zero)
+    (* mark_debug = "true" *) reg[3:0] state=IDLE;
+    reg[3:0] rest_counter=0;
+    wire[WB_DATA_BITS-1:0] correct_data;
+    wire[WB_DATA_BITS-1:0] wb_data_randomized;
+    reg[WB_ADDR_BITS-1:0] write_test_address_counter = 0, read_test_address_counter = 0;
+    reg[WB_ADDR_BITS-1:0] check_test_address_counter = 0; 
+    reg[$clog2(WB_SEL_BITS)-1:0] write_by_byte_counter = 0;
+    (* mark_debug = "true" *) reg[63:0] correct_read_data_counter = 0, wrong_read_data_counter = 0; // 64-bit counter for correct and wrong read data, this make sure the counter will not overflow when several day's worth of DDR3 test is done on hardware
+    reg increment_wrong_read_data_counter = 0;
+    reg increment_correct_read_data_counter = 0;
+    (* mark_debug = "true" *) reg[WB_DATA_BITS-1:0] wrong_data, expected_data;
+    reg[63:0] time_counter = 0; 
+    (* mark_debug = "true" *) reg[31:0] injected_faults_counter = 0;
+    assign timer_pulse = time_counter[27]; // 1.34 sec
+    assign wrong_data_counter_non_zero = wrong_read_data_counter != 0; // pulse when there is wrong data
+
+    always @(posedge i_clk, negedge i_rst_n) begin
+        if(!i_rst_n) begin
+            state <= IDLE;
+            rest_counter <= 0;
+            o_wb_cyc <= 0;
+            o_wb_stb <= 0;
+            o_wb_we <= 0;
+            o_wb_addr <= 0;
+            o_wb_data <= 0;
+            o_wb_sel <= 0;
+            o_aux <= 0;
+            write_test_address_counter <= MICRON_SIM? SIM_ADDRESS_START : 0;
+            rest_counter <= 0;
+            read_test_address_counter <= MICRON_SIM? SIM_ADDRESS_START : 0;
+            write_by_byte_counter <= 0;
+            injected_faults_counter <= 0;
+        end
+        else begin
+            case(state)
+                IDLE: if(i_calib_complete) begin // wait until DDR3 is done calibrating
+                        rest_counter = rest_counter + 1;
+                        if(rest_counter == 4'hf) begin // rest for 16 cycles before starting test
+                            state <= BURST_WRITE;
+                            o_wb_cyc <= 1'b1;
+                        end
+                    end
+                    else begin
+                        o_wb_cyc <= 0;
+                        o_wb_stb <= 0;
+                        o_wb_we <= 0;
+                        o_wb_addr <= 0;
+                        o_wb_data <= 0;
+                        o_wb_sel <= 0;
+                        o_aux <= 0;
+                        write_test_address_counter <= MICRON_SIM? SIM_ADDRESS_START : 0;
+                        rest_counter <= 0;
+                        read_test_address_counter <= MICRON_SIM? SIM_ADDRESS_START : 0;
+                        write_by_byte_counter <= 0;
+                        injected_faults_counter <= 0;
+                    end
+
+                BURST_WRITE: if(!i_wb_stall) begin // Test 1: Burst write (per byte write to test datamask feature), then burst read
+                                o_wb_stb <= 1'b1; 
+                                o_aux <= 2; // write
+                                o_wb_we <= 1; 
+                                if(DATA_MASK) begin // If datamasking is available, test datamask by writing 8 bytes at a time
+                                    o_wb_sel <= {{WB_SEL_BITS-8{1'b0}}, 8'hff} << write_by_byte_counter; // write_by_byte_counter increments by 8 from 0 to (WB_SEL_BITS-8)
+                                    o_wb_addr <= write_test_address_counter;
+                                    o_wb_data <= {WB_SEL_BITS{8'haa}}; // fill data initially by 8'haa
+                                    o_wb_data[8*write_by_byte_counter +: 64] <= btn_pulse? {64{1'b0}} : wb_data_randomized[8*write_by_byte_counter +: 64]; // place the real data at the datamasked bytes
+                                    injected_faults_counter <= btn_pulse? injected_faults_counter + 1 : injected_faults_counter;
+                                    if(write_by_byte_counter == (WB_SEL_BITS-8)) begin // once every 64bytes of data is written, go to next address
+                                         write_test_address_counter <= write_test_address_counter + 1;  
+                                        /* verilator lint_off WIDTHEXPAND */
+                                        if( write_test_address_counter == {(WB_ADDR_BITS){1'b1}} ) begin  // wait until all address space is writtten
+                                        /* verilator lint_on WIDTHEXPAND */
+                                            write_test_address_counter <= MICRON_SIM? SIM_ADDRESS_START : 0;
+                                            state <= BURST_READ;
+                                        end 
+                                    end
+                                    write_by_byte_counter <= write_by_byte_counter + 8;
+                                end
+                                else begin // Burst write to all bytes (all datamask on)
+                                    o_wb_sel <= {WB_SEL_BITS{1'b1}};
+                                    o_wb_addr <= write_test_address_counter;
+                                    o_wb_data <= btn_pulse? {WB_DATA_BITS{1'b0}} : wb_data_randomized;
+                                    injected_faults_counter <= btn_pulse? injected_faults_counter + 1 : injected_faults_counter;
+                                    write_test_address_counter <= write_test_address_counter + 1;  
+                                    /* verilator lint_off WIDTHEXPAND */
+                                    if( write_test_address_counter == {WB_ADDR_BITS{1'b1}} ) begin  // wait until all address space is writtten
+                                    /* verilator lint_on WIDTHEXPAND */
+                                        write_test_address_counter <= MICRON_SIM? SIM_ADDRESS_START : 0;
+                                        state <= BURST_READ;
+                                    end 
+                                end
+                            end
+                        
+                BURST_READ: if(!i_wb_stall) begin
+                                o_wb_stb <= 1'b1; 
+                                o_aux <= 3; // read
+                                o_wb_we <= 0; 
+                                o_wb_addr <= read_test_address_counter;
+                                read_test_address_counter <= read_test_address_counter + 1; 
+                                /* verilator lint_off WIDTHEXPAND */
+                                if( read_test_address_counter == {(WB_ADDR_BITS){1'b1}} ) begin // wait until all address space is read
+                                /* verilator lint_on WIDTHEXPAND */
+                                    read_test_address_counter <= MICRON_SIM? SIM_ADDRESS_START : 0;
+                                    state <= RANDOM_WRITE;
+                                end  
+                            end
+                            
+                RANDOM_WRITE: if(!i_wb_stall) begin // Test 2: Random write (increments row address to force precharge-act-r/w) then random read
+                                    o_wb_stb <= 1'b1; 
+                                    o_aux <= 2; // write
+                                    o_wb_sel <= {WB_SEL_BITS{1'b1}};
+                                    o_wb_we <= 1; 
+                                    // swap the halves of address counter, since address mapping is {row,bank,col} then every increment of address counter will now increment the {row, bank} preventing burst operation and forcing precharge-activate before write/read
+                                    o_wb_addr[WB_ADDR_BITS-1:HALF_ADDRESS] <= write_test_address_counter[HALF_ADDRESS-1:0]; // [25:13] <= [12:0] 
+                                    o_wb_addr[HALF_ADDRESS-1:0] <= write_test_address_counter[WB_ADDR_BITS-1:HALF_ADDRESS]; // [12:0] <= [25:13] 
+                                    o_wb_data <= btn_pulse? {WB_DATA_BITS{1'b0}} : wb_data_randomized;
+                                    injected_faults_counter <= btn_pulse? injected_faults_counter + 1 : injected_faults_counter;
+                                    write_test_address_counter <= write_test_address_counter + 1;  
+                                    /* verilator lint_off WIDTHEXPAND */
+                                    if( write_test_address_counter == {(WB_ADDR_BITS){1'b1}} ) begin // wait until all address space is writtten
+                                    /* verilator lint_on WIDTHEXPAND */
+                                        write_test_address_counter <= MICRON_SIM? SIM_ADDRESS_START : 0;
+                                        state <= RANDOM_READ;
+                                    end
+                                end
+                        
+                RANDOM_READ: if(!i_wb_stall) begin
+                                o_wb_stb <= 1'b1; 
+                                o_aux <= 3; // read
+                                o_wb_we <= 0; 
+                                // swap the halves of address counter, since address mapping is {row,bank,col} then every increment of address counter will now increment the {row, bank} preventing burst operation and forcing precharge-activate before write/read
+                                o_wb_addr[WB_ADDR_BITS-1:HALF_ADDRESS] <= read_test_address_counter[HALF_ADDRESS-1:0]; // [25:13] <= [12:0] 
+                                o_wb_addr[HALF_ADDRESS-1:0] <= read_test_address_counter[WB_ADDR_BITS-1:HALF_ADDRESS]; // [12:0] <= [25:13]
+                                read_test_address_counter <=  read_test_address_counter + 1;  
+                                /* verilator lint_off WIDTHEXPAND */
+                                if( read_test_address_counter == {(WB_ADDR_BITS){1'b1}} ) begin // wait until all address space is read
+                                /* verilator lint_on WIDTHEXPAND */
+                                    read_test_address_counter <= MICRON_SIM? SIM_ADDRESS_START : 0;
+                                    state <= ALTERNATE_WRITE_READ;
+                                end
+                                end
+                                
+                ALTERNATE_WRITE_READ: if(!i_wb_stall) begin
+                                o_wb_stb <= 1'b1; 
+                                o_aux <= 2 + (o_wb_we? 1:0); //2 (write), 3 (read)
+                                o_wb_sel <= {WB_SEL_BITS{1'b1}};
+                                o_wb_we <= !o_wb_we; // alternating write-read
+                                o_wb_addr <= write_test_address_counter; 
+                                o_wb_data <= btn_pulse? {WB_DATA_BITS{1'b0}} : wb_data_randomized;
+                                injected_faults_counter <= btn_pulse? injected_faults_counter + 1 : injected_faults_counter;
+                                // if current operation is write, then dont increment address since we wil read the same address next
+                                if(o_wb_we) begin // current operation is read thus increment address
+                                    write_test_address_counter <= write_test_address_counter + 1;  
+                                end
+                                /* verilator lint_off WIDTHEXPAND */
+                                if( (o_wb_addr == {(WB_ADDR_BITS){1'b1}}) && !o_wb_we ) begin // only 
+                                /* verilator lint_on WIDTHEXPAND */
+                                    write_test_address_counter <= MICRON_SIM? SIM_ADDRESS_START : 0;
+                                    state <= DONE_TEST;
+                                    rest_counter <= 0;
+                                end
+                            end         
+                DONE_TEST: begin
+                                o_wb_stb <= 0;
+                                rest_counter <= rest_counter + 1;
+                                if(rest_counter == 4'hf) begin // rest for 16 cycles before repeating test
+                                    state <= BURST_WRITE;
+                                end
+                            end
+            endcase
+        end
+    end
+    // Uses different operations (XOR, addition, subtraction, bit rotation) to generate different values per byte.
+    assign wb_data_randomized = {
+        {(WB_SEL_BITS/8){write_test_address_counter[0 +: 8] ^ 8'hA5,  // Byte 7
+        write_test_address_counter[0 +: 8] | 8'h1A,  // Byte 6
+        write_test_address_counter[0 +: 8] & 8'h33,  // Byte 5
+        write_test_address_counter[0 +: 8] ^ 8'h5A,  // Byte 4
+        write_test_address_counter[0 +: 8] & 8'h21,  // Byte 3
+        write_test_address_counter[0 +: 8] | 8'hC7,  // Byte 2
+        write_test_address_counter[0 +: 8] ^ 8'h7E,  // Byte 1
+        write_test_address_counter[0 +: 8] ^ 8'h3C}}   // Byte 0
+    };
+
+    /******************************************************* Test Receiver *******************************************************/
+    assign correct_data = {
+        {(WB_SEL_BITS/8){check_test_address_counter[0 +: 8] ^ 8'hA5,  // Byte 7
+        check_test_address_counter[0 +: 8] | 8'h1A,  // Byte 6
+        check_test_address_counter[0 +: 8] & 8'h33,  // Byte 5
+        check_test_address_counter[0 +: 8] ^ 8'h5A,  // Byte 4
+        check_test_address_counter[0 +: 8] & 8'h21,  // Byte 3
+        check_test_address_counter[0 +: 8] | 8'hC7,  // Byte 2
+        check_test_address_counter[0 +: 8] ^ 8'h7E,  // Byte 1
+        check_test_address_counter[0 +: 8] ^ 8'h3C }}  // Byte 0
+    };
+
+    always @(posedge i_clk, negedge i_rst_n) begin
+        if(!i_rst_n) begin
+            check_test_address_counter <= MICRON_SIM? SIM_ADDRESS_START : 0;
+            correct_read_data_counter <= 64'd0;
+            wrong_read_data_counter <= 64'd0;
+            wrong_data <= 512'd0;
+            expected_data <= 512'd0;
+            increment_wrong_read_data_counter <= 0;
+        end
+        else begin
+            if(i_calib_complete) begin          
+                increment_wrong_read_data_counter <= 1'b0;
+                increment_correct_read_data_counter <= 1'b0;
+                if ( i_wb_ack && i_aux[2:0] == 3'd3 ) begin //o_aux = 3 is for read requests from DDR3 test
+                    if(i_wb_data == correct_data) begin // if read data matches the expected, increment correct_read_data_counter
+                        increment_correct_read_data_counter <= 1'b1;
+                    end
+                    else begin
+                        increment_wrong_read_data_counter <= 1'b1;
+                        wrong_data <= i_wb_data;
+                        expected_data <= correct_data;
+                    end
+                    /* verilator lint_off WIDTHEXPAND */
+                    check_test_address_counter <= check_test_address_counter + 1;
+                    if(check_test_address_counter+1'b1 == {(WB_ADDR_BITS){1'b0}}) begin // if next address returns to zero, then if in MICRON_SIM jump to SIM_ADDRESS_START
+                        check_test_address_counter <= MICRON_SIM? SIM_ADDRESS_START : {(WB_ADDR_BITS){1'b0}};
+                    end
+                    /* verilator lint_on WIDTHEXPAND */
+                end
+            end
+            else begin
+                check_test_address_counter <= MICRON_SIM? SIM_ADDRESS_START : 0;
+                correct_read_data_counter <= 64'd0;
+                wrong_read_data_counter <= 64'd0;
+                wrong_data <= 512'd0;
+                expected_data <= 512'd0;
+            end
+            if(increment_wrong_read_data_counter) begin
+                wrong_read_data_counter <= wrong_read_data_counter + 64'd1;
+            end
+            if(increment_correct_read_data_counter) begin
+                correct_read_data_counter <= correct_read_data_counter + 64'd1;
+            end
+        end
+
+    end
+    /*********************************************************************************************************************************************/
+    // 64-bit counter to know how much time had passed and also debounce of btn for fault-injection
+    (* mark_debug = "true" *) reg[27:0] btn_debounce_delay;
+    (* mark_debug = "true" *) reg btn_pulse_long, btn_pulse_long_prev;
+    (* mark_debug = "true" *) wire btn_pulse;
+    assign btn_pulse = btn_pulse_long && !btn_pulse_long_prev; // if current btn_pulse is high but previously low (posedge) then make pulse
+    
+    always @(posedge i_clk, negedge i_rst_n) begin
+        if(!i_rst_n) begin
+            btn_pulse_long_prev <= 1'b0;
+            btn_debounce_delay <= 0;
+            btn_pulse_long <= 0;
+        end
+        else begin
+            btn_pulse_long_prev <= btn_pulse_long;
+            if(btn && !btn_pulse_long) begin // when btn asserts and  btn_pulse_long is still low
+                btn_pulse_long <= 1'b1;
+            end
+            if(btn_debounce_delay[27]) begin // if ~1.3s had passed, set btn_pulse_long low and reset delay
+                btn_pulse_long <= 0;
+                btn_debounce_delay <= 0;
+            end
+            else begin 
+                btn_debounce_delay <= btn_pulse_long? btn_debounce_delay + 1 : 0;
+            end
+        end
+    end
+
+    always @(posedge i_clk100, negedge i_rst_n) begin
+        if(!i_rst_n) begin
+            time_counter <= 64'd0;
+        end
+        else begin
+            time_counter <= time_counter + 1;
+        end
+    end 
+
+    design_1_wrapper microblaze_inst
+    (   .clk_in1_0(i_clk100),
+        .correct_read_data_counter_0(correct_read_data_counter),
+        .reset_rtl_0(i_rst_n),
+        .time_counter_0(time_counter),
+        .injected_faults_counter_0(injected_faults_counter),
+        .uart_rtl_0_rxd(rx),
+        .uart_rtl_0_txd(tx),
+        .wrong_read_data_counter_0(wrong_read_data_counter)
+    );
+endmodule
+

AngeloJacobo_UberDDR3/example_demo/enclustra_kx2_st1/ddr3_test_monitor_axi_1.0/bd/bd.tcl

@@ -0,0 +1,86 @@
+
+proc init { cellpath otherInfo } {                                                                   
+                                                                                                             
+	set cell_handle [get_bd_cells $cellpath]                                                                 
+	set all_busif [get_bd_intf_pins $cellpath/*]		                                                     
+	set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
+	set full_sbusif_list [list  ]
+			                                                                                                 
+	foreach busif $all_busif {                                                                               
+		if { [string equal -nocase [get_property MODE $busif] "slave"] == 1 } {                            
+			set busif_param_list [list]                                                                      
+			set busif_name [get_property NAME $busif]					                                     
+			if { [lsearch -exact -nocase $full_sbusif_list $busif_name ] == -1 } {					         
+			    continue                                                                                     
+			}                                                                                                
+			foreach tparam $axi_standard_param_list {                                                        
+				lappend busif_param_list "C_${busif_name}_${tparam}"                                       
+			}                                                                                                
+			bd::mark_propagate_only $cell_handle $busif_param_list			                                 
+		}		                                                                                             
+	}                                                                                                        
+}
+
+
+proc pre_propagate {cellpath otherInfo } {                                                           
+                                                                                                             
+	set cell_handle [get_bd_cells $cellpath]                                                                 
+	set all_busif [get_bd_intf_pins $cellpath/*]		                                                     
+	set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
+	                                                                                                         
+	foreach busif $all_busif {	                                                                             
+		if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } {                  
+			continue                                                                                         
+		}                                                                                                    
+		if { [string equal -nocase [get_property MODE $busif] "master"] != 1 } {                           
+			continue                                                                                         
+		}			                                                                                         
+		                                                                                                     
+		set busif_name [get_property NAME $busif]			                                                 
+		foreach tparam $axi_standard_param_list {		                                                     
+			set busif_param_name "C_${busif_name}_${tparam}"			                                     
+			                                                                                                 
+			set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif]                                  
+			set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle]                           
+			                                                                                                 
+			if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } {                          
+				if { $val_on_cell != "" } {                                                                  
+					set_property CONFIG.${tparam} $val_on_cell $busif                                        
+				}                                                                                            
+			}			                                                                                     
+		}		                                                                                             
+	}                                                                                                        
+}
+
+
+proc propagate {cellpath otherInfo } {                                                               
+                                                                                                             
+	set cell_handle [get_bd_cells $cellpath]                                                                 
+	set all_busif [get_bd_intf_pins $cellpath/*]		                                                     
+	set axi_standard_param_list [list ID_WIDTH AWUSER_WIDTH ARUSER_WIDTH WUSER_WIDTH RUSER_WIDTH BUSER_WIDTH]
+	                                                                                                         
+	foreach busif $all_busif {                                                                               
+		if { [string equal -nocase [get_property CONFIG.PROTOCOL $busif] "AXI4"] != 1 } {                  
+			continue                                                                                         
+		}                                                                                                    
+		if { [string equal -nocase [get_property MODE $busif] "slave"] != 1 } {                            
+			continue                                                                                         
+		}			                                                                                         
+	                                                                                                         
+		set busif_name [get_property NAME $busif]		                                                     
+		foreach tparam $axi_standard_param_list {			                                                 
+			set busif_param_name "C_${busif_name}_${tparam}"			                                     
+                                                                                                             
+			set val_on_cell_intf_pin [get_property CONFIG.${tparam} $busif]                                  
+			set val_on_cell [get_property CONFIG.${busif_param_name} $cell_handle]                           
+			                                                                                                 
+			if { [string equal -nocase $val_on_cell_intf_pin $val_on_cell] != 1 } {                          
+				#override property of bd_interface_net to bd_cell -- only for slaves.  May check for supported values..
+				if { $val_on_cell_intf_pin != "" } {                                                         
+					set_property CONFIG.${busif_param_name} $val_on_cell_intf_pin $cell_handle               
+				}                                                                                            
+			}                                                                                                
+		}		                                                                                             
+	}                                                                                                        
+}
+

AngeloJacobo_UberDDR3/example_demo/enclustra_kx2_st1/ddr3_test_monitor_axi_1.0/component.xml

@@ -0,0 +1,900 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+  <spirit:vendor>user.org</spirit:vendor>
+  <spirit:library>user</spirit:library>
+  <spirit:name>ddr3_test_monitor_axi</spirit:name>
+  <spirit:version>1.0</spirit:version>
+  <spirit:busInterfaces>
+    <spirit:busInterface>
+      <spirit:name>s00_axi</spirit:name>
+      <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+      <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+      <spirit:slave>
+        <spirit:memoryMapRef spirit:memoryMapRef="s00_axi"/>
+      </spirit:slave>
+      <spirit:portMaps>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWADDR</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s00_axi_awaddr</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWPROT</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s00_axi_awprot</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s00_axi_awvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>AWREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s00_axi_awready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WDATA</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s00_axi_wdata</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WSTRB</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s00_axi_wstrb</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WVALID</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s00_axi_wvalid</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>WREADY</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
+            <spirit:name>s00_axi_wready</spirit:name>
+          </spirit:physicalPort>
+        </spirit:portMap>
+        <spirit:portMap>
+          <spirit:logicalPort>
+            <spirit:name>BRESP</spirit:name>
+          </spirit:logicalPort>
+          <spirit:physicalPort>
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+        <spirit:name>s00_axi_arvalid</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>wire</spirit:typeName>
+              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>s00_axi_arready</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>wire</spirit:typeName>
+              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>s00_axi_rdata</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id(&apos;MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH&apos;)) - 1)">31</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>wire</spirit:typeName>
+              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>s00_axi_rresp</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:vector>
+            <spirit:left spirit:format="long">1</spirit:left>
+            <spirit:right spirit:format="long">0</spirit:right>
+          </spirit:vector>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>wire</spirit:typeName>
+              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>s00_axi_rvalid</spirit:name>
+        <spirit:wire>
+          <spirit:direction>out</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>wire</spirit:typeName>
+              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+        </spirit:wire>
+      </spirit:port>
+      <spirit:port>
+        <spirit:name>s00_axi_rready</spirit:name>
+        <spirit:wire>
+          <spirit:direction>in</spirit:direction>
+          <spirit:wireTypeDefs>
+            <spirit:wireTypeDef>
+              <spirit:typeName>wire</spirit:typeName>
+              <spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
+              <spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
+            </spirit:wireTypeDef>
+          </spirit:wireTypeDefs>
+          <spirit:driver>
+            <spirit:defaultValue spirit:format="long">0</spirit:defaultValue>
+          </spirit:driver>
+        </spirit:wire>
+      </spirit:port>
+    </spirit:ports>
+    <spirit:modelParameters>
+      <spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
+        <spirit:name>C_S00_AXI_DATA_WIDTH</spirit:name>
+        <spirit:displayName>C S00 AXI DATA WIDTH</spirit:displayName>
+        <spirit:description>Width of S_AXI data bus</spirit:description>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH" spirit:order="3" spirit:rangeType="long">32</spirit:value>
+      </spirit:modelParameter>
+      <spirit:modelParameter spirit:dataType="integer">
+        <spirit:name>C_S00_AXI_ADDR_WIDTH</spirit:name>
+        <spirit:displayName>C S00 AXI ADDR WIDTH</spirit:displayName>
+        <spirit:description>Width of S_AXI address bus</spirit:description>
+        <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH" spirit:order="4" spirit:rangeType="long">7</spirit:value>
+      </spirit:modelParameter>
+    </spirit:modelParameters>
+  </spirit:model>
+  <spirit:choices>
+    <spirit:choice>
+      <spirit:name>choice_list_6fc15197</spirit:name>
+      <spirit:enumeration>32</spirit:enumeration>
+    </spirit:choice>
+    <spirit:choice>
+      <spirit:name>choice_list_74b5137e</spirit:name>
+      <spirit:enumeration>ACTIVE_HIGH</spirit:enumeration>
+      <spirit:enumeration>ACTIVE_LOW</spirit:enumeration>
+    </spirit:choice>
+  </spirit:choices>
+  <spirit:fileSets>
+    <spirit:fileSet>
+      <spirit:name>xilinx_verilogsynthesis_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>hdl/ddr3_test_monitor_axi_v1_0_S00_AXI.v</spirit:name>
+        <spirit:fileType>verilogSource</spirit:fileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>hdl/ddr3_test_monitor_axi_v1_0.v</spirit:name>
+        <spirit:fileType>verilogSource</spirit:fileType>
+        <spirit:userFileType>CHECKSUM_e4de66a6</spirit:userFileType>
+      </spirit:file>
+    </spirit:fileSet>
+    <spirit:fileSet>
+      <spirit:name>xilinx_verilogbehavioralsimulation_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>hdl/ddr3_test_monitor_axi_v1_0_S00_AXI.v</spirit:name>
+        <spirit:fileType>verilogSource</spirit:fileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>hdl/ddr3_test_monitor_axi_v1_0.v</spirit:name>
+        <spirit:fileType>verilogSource</spirit:fileType>
+      </spirit:file>
+    </spirit:fileSet>
+    <spirit:fileSet>
+      <spirit:name>xilinx_softwaredriver_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>drivers/ddr3_test_monitor_axi_v1_0/data/ddr3_test_monitor_axi.mdd</spirit:name>
+        <spirit:userFileType>mdd</spirit:userFileType>
+        <spirit:userFileType>driver_mdd</spirit:userFileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>drivers/ddr3_test_monitor_axi_v1_0/data/ddr3_test_monitor_axi.tcl</spirit:name>
+        <spirit:fileType>tclSource</spirit:fileType>
+        <spirit:userFileType>driver_tcl</spirit:userFileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>drivers/ddr3_test_monitor_axi_v1_0/src/Makefile</spirit:name>
+        <spirit:userFileType>driver_src</spirit:userFileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>drivers/ddr3_test_monitor_axi_v1_0/src/ddr3_test_monitor_axi.h</spirit:name>
+        <spirit:fileType>cSource</spirit:fileType>
+        <spirit:userFileType>driver_src</spirit:userFileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>drivers/ddr3_test_monitor_axi_v1_0/src/ddr3_test_monitor_axi.c</spirit:name>
+        <spirit:fileType>cSource</spirit:fileType>
+        <spirit:userFileType>driver_src</spirit:userFileType>
+      </spirit:file>
+      <spirit:file>
+        <spirit:name>drivers/ddr3_test_monitor_axi_v1_0/src/ddr3_test_monitor_axi_selftest.c</spirit:name>
+        <spirit:fileType>cSource</spirit:fileType>
+        <spirit:userFileType>driver_src</spirit:userFileType>
+      </spirit:file>
+    </spirit:fileSet>
+    <spirit:fileSet>
+      <spirit:name>xilinx_xpgui_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>xgui/ddr3_test_monitor_axi_v1_0.tcl</spirit:name>
+        <spirit:fileType>tclSource</spirit:fileType>
+        <spirit:userFileType>CHECKSUM_080b65eb</spirit:userFileType>
+        <spirit:userFileType>XGUI_VERSION_2</spirit:userFileType>
+      </spirit:file>
+    </spirit:fileSet>
+    <spirit:fileSet>
+      <spirit:name>bd_tcl_view_fileset</spirit:name>
+      <spirit:file>
+        <spirit:name>bd/bd.tcl</spirit:name>
+        <spirit:fileType>tclSource</spirit:fileType>
+      </spirit:file>
+    </spirit:fileSet>
+  </spirit:fileSets>
+  <spirit:description>monitors ddr3 test results</spirit:description>
+  <spirit:parameters>
+    <spirit:parameter>
+      <spirit:name>C_S00_AXI_DATA_WIDTH</spirit:name>
+      <spirit:displayName>C S00 AXI DATA WIDTH</spirit:displayName>
+      <spirit:description>Width of S_AXI data bus</spirit:description>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S00_AXI_DATA_WIDTH" spirit:choiceRef="choice_list_6fc15197" spirit:order="3">32</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.C_S00_AXI_DATA_WIDTH">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_S00_AXI_ADDR_WIDTH</spirit:name>
+      <spirit:displayName>C S00 AXI ADDR WIDTH</spirit:displayName>
+      <spirit:description>Width of S_AXI address bus</spirit:description>
+      <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S00_AXI_ADDR_WIDTH" spirit:order="4" spirit:rangeType="long">7</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.C_S00_AXI_ADDR_WIDTH">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_S00_AXI_BASEADDR</spirit:name>
+      <spirit:displayName>C S00 AXI BASEADDR</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S00_AXI_BASEADDR" spirit:order="5" spirit:bitStringLength="32">0xFFFFFFFF</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.C_S00_AXI_BASEADDR">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>C_S00_AXI_HIGHADDR</spirit:name>
+      <spirit:displayName>C S00 AXI HIGHADDR</spirit:displayName>
+      <spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S00_AXI_HIGHADDR" spirit:order="6" spirit:bitStringLength="32">0x00000000</spirit:value>
+      <spirit:vendorExtensions>
+        <xilinx:parameterInfo>
+          <xilinx:enablement>
+            <xilinx:isEnabled xilinx:id="PARAM_ENABLEMENT.C_S00_AXI_HIGHADDR">false</xilinx:isEnabled>
+          </xilinx:enablement>
+        </xilinx:parameterInfo>
+      </spirit:vendorExtensions>
+    </spirit:parameter>
+    <spirit:parameter>
+      <spirit:name>Component_Name</spirit:name>
+      <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">ddr3_test_monitor_axi_v1_0</spirit:value>
+    </spirit:parameter>
+  </spirit:parameters>
+  <spirit:vendorExtensions>
+    <xilinx:coreExtensions>
+      <xilinx:supportedFamilies>
+        <xilinx:family xilinx:lifeCycle="Pre-Production">kintex7</xilinx:family>
+      </xilinx:supportedFamilies>
+      <xilinx:taxonomies>
+        <xilinx:taxonomy>AXI_Peripheral</xilinx:taxonomy>
+      </xilinx:taxonomies>
+      <xilinx:displayName>ddr3_test_monitor_axi_v1.0</xilinx:displayName>
+      <xilinx:coreRevision>9</xilinx:coreRevision>
+      <xilinx:coreCreationDateTime>2025-02-09T12:59:49Z</xilinx:coreCreationDateTime>
+    </xilinx:coreExtensions>
+    <xilinx:packagingInfo>
+      <xilinx:xilinxVersion>2022.1</xilinx:xilinxVersion>
+      <xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="2149db2e"/>
+      <xilinx:checksum xilinx:scope="memoryMaps" xilinx:value="0c04c4c2"/>
+      <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="f7195f90"/>
+      <xilinx:checksum xilinx:scope="ports" xilinx:value="9e6f557d"/>
+      <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="a0a6f17f"/>
+      <xilinx:checksum xilinx:scope="parameters" xilinx:value="07777575"/>
+    </xilinx:packagingInfo>
+  </spirit:vendorExtensions>
+</spirit:component>

AngeloJacobo_UberDDR3/example_demo/enclustra_kx2_st1/ddr3_test_monitor_axi_1.0/drivers/ddr3_test_monitor_axi_v1_0/data/ddr3_test_monitor_axi.mdd

@@ -0,0 +1,10 @@
+
+
+OPTION psf_version = 2.1;
+
+BEGIN DRIVER ddr3_test_monitor_axi
+	OPTION supported_peripherals = (ddr3_test_monitor_axi);
+	OPTION copyfiles = all;
+	OPTION VERSION = 1.0;
+	OPTION NAME = ddr3_test_monitor_axi;
+END DRIVER

AngeloJacobo_UberDDR3/example_demo/enclustra_kx2_st1/ddr3_test_monitor_axi_1.0/drivers/ddr3_test_monitor_axi_v1_0/data/ddr3_test_monitor_axi.tcl

@@ -0,0 +1,5 @@
+
+
+proc generate {drv_handle} {
+	xdefine_include_file $drv_handle "xparameters.h" "ddr3_test_monitor_axi" "NUM_INSTANCES" "DEVICE_ID"  "C_S00_AXI_BASEADDR" "C_S00_AXI_HIGHADDR"
+}

AngeloJacobo_UberDDR3/example_demo/enclustra_kx2_st1/ddr3_test_monitor_axi_1.0/drivers/ddr3_test_monitor_axi_v1_0/src/Makefile

@@ -0,0 +1,26 @@
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+INCLUDEFILES=*.h
+LIBSOURCES=*.c
+OUTS = *.o
+
+libs:
+	echo "Compiling ddr3_test_monitor_axi..."
+	$(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
+	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS}
+	make clean
+
+include:
+	${CP} $(INCLUDEFILES) $(INCLUDEDIR)
+
+clean:
+	rm -rf ${OUTS}

AngeloJacobo_UberDDR3/example_demo/enclustra_kx2_st1/ddr3_test_monitor_axi_1.0/drivers/ddr3_test_monitor_axi_v1_0/src/ddr3_test_monitor_axi.c

@@ -0,0 +1,6 @@
+
+
+/***************************** Include Files *******************************/
+#include "ddr3_test_monitor_axi.h"
+
+/************************** Function Definitions ***************************/

AngeloJacobo_UberDDR3/example_demo/enclustra_kx2_st1/ddr3_test_monitor_axi_1.0/drivers/ddr3_test_monitor_axi_v1_0/src/ddr3_test_monitor_axi.h

@@ -0,0 +1,107 @@
+
+#ifndef DDR3_TEST_MONITOR_AXI_H
+#define DDR3_TEST_MONITOR_AXI_H
+
+
+/****************** Include Files ********************/
+#include "xil_types.h"
+#include "xstatus.h"
+
+#define DDR3_TEST_MONITOR_AXI_S00_AXI_SLV_REG0_OFFSET 0
+#define DDR3_TEST_MONITOR_AXI_S00_AXI_SLV_REG1_OFFSET 4
+#define DDR3_TEST_MONITOR_AXI_S00_AXI_SLV_REG2_OFFSET 8
+#define DDR3_TEST_MONITOR_AXI_S00_AXI_SLV_REG3_OFFSET 12
+#define DDR3_TEST_MONITOR_AXI_S00_AXI_SLV_REG4_OFFSET 16
+#define DDR3_TEST_MONITOR_AXI_S00_AXI_SLV_REG5_OFFSET 20
+#define DDR3_TEST_MONITOR_AXI_S00_AXI_SLV_REG6_OFFSET 24
+#define DDR3_TEST_MONITOR_AXI_S00_AXI_SLV_REG7_OFFSET 28
+#define DDR3_TEST_MONITOR_AXI_S00_AXI_SLV_REG8_OFFSET 32
+#define DDR3_TEST_MONITOR_AXI_S00_AXI_SLV_REG9_OFFSET 36
+#define DDR3_TEST_MONITOR_AXI_S00_AXI_SLV_REG10_OFFSET 40
+#define DDR3_TEST_MONITOR_AXI_S00_AXI_SLV_REG11_OFFSET 44
+#define DDR3_TEST_MONITOR_AXI_S00_AXI_SLV_REG12_OFFSET 48
+#define DDR3_TEST_MONITOR_AXI_S00_AXI_SLV_REG13_OFFSET 52
+#define DDR3_TEST_MONITOR_AXI_S00_AXI_SLV_REG14_OFFSET 56
+#define DDR3_TEST_MONITOR_AXI_S00_AXI_SLV_REG15_OFFSET 60
+#define DDR3_TEST_MONITOR_AXI_S00_AXI_SLV_REG16_OFFSET 64
+#define DDR3_TEST_MONITOR_AXI_S00_AXI_SLV_REG17_OFFSET 68
+#define DDR3_TEST_MONITOR_AXI_S00_AXI_SLV_REG18_OFFSET 72
+#define DDR3_TEST_MONITOR_AXI_S00_AXI_SLV_REG19_OFFSET 76
+#define DDR3_TEST_MONITOR_AXI_S00_AXI_SLV_REG20_OFFSET 80
+#define DDR3_TEST_MONITOR_AXI_S00_AXI_SLV_REG21_OFFSET 84
+#define DDR3_TEST_MONITOR_AXI_S00_AXI_SLV_REG22_OFFSET 88
+#define DDR3_TEST_MONITOR_AXI_S00_AXI_SLV_REG23_OFFSET 92
+#define DDR3_TEST_MONITOR_AXI_S00_AXI_SLV_REG24_OFFSET 96
+#define DDR3_TEST_MONITOR_AXI_S00_AXI_SLV_REG25_OFFSET 100
+#define DDR3_TEST_MONITOR_AXI_S00_AXI_SLV_REG26_OFFSET 104
+#define DDR3_TEST_MONITOR_AXI_S00_AXI_SLV_REG27_OFFSET 108
+#define DDR3_TEST_MONITOR_AXI_S00_AXI_SLV_REG28_OFFSET 112
+#define DDR3_TEST_MONITOR_AXI_S00_AXI_SLV_REG29_OFFSET 116
+#define DDR3_TEST_MONITOR_AXI_S00_AXI_SLV_REG30_OFFSET 120
+#define DDR3_TEST_MONITOR_AXI_S00_AXI_SLV_REG31_OFFSET 124
+
+
+/**************************** Type Definitions *****************************/
+/**
+ *
+ * Write a value to a DDR3_TEST_MONITOR_AXI register. A 32 bit write is performed.
+ * If the component is implemented in a smaller width, only the least
+ * significant data is written.
+ *
+ * @param   BaseAddress is the base address of the DDR3_TEST_MONITOR_AXIdevice.
+ * @param   RegOffset is the register offset from the base to write to.
+ * @param   Data is the data written to the register.
+ *
+ * @return  None.
+ *
+ * @note
+ * C-style signature:
+ * 	void DDR3_TEST_MONITOR_AXI_mWriteReg(u32 BaseAddress, unsigned RegOffset, u32 Data)
+ *
+ */
+#define DDR3_TEST_MONITOR_AXI_mWriteReg(BaseAddress, RegOffset, Data) \
+  	Xil_Out32((BaseAddress) + (RegOffset), (u32)(Data))
+
+/**
+ *
+ * Read a value from a DDR3_TEST_MONITOR_AXI register. A 32 bit read is performed.
+ * If the component is implemented in a smaller width, only the least
+ * significant data is read from the register. The most significant data
+ * will be read as 0.
+ *
+ * @param   BaseAddress is the base address of the DDR3_TEST_MONITOR_AXI device.
+ * @param   RegOffset is the register offset from the base to write to.
+ *
+ * @return  Data is the data from the register.
+ *
+ * @note
+ * C-style signature:
+ * 	u32 DDR3_TEST_MONITOR_AXI_mReadReg(u32 BaseAddress, unsigned RegOffset)
+ *
+ */
+#define DDR3_TEST_MONITOR_AXI_mReadReg(BaseAddress, RegOffset) \
+    Xil_In32((BaseAddress) + (RegOffset))
+
+/************************** Function Prototypes ****************************/
+/**
+ *
+ * Run a self-test on the driver/device. Note this may be a destructive test if
+ * resets of the device are performed.
+ *
+ * If the hardware system is not built correctly, this function may never
+ * return to the caller.
+ *
+ * @param   baseaddr_p is the base address of the DDR3_TEST_MONITOR_AXI instance to be worked on.
+ *
+ * @return
+ *
+ *    - XST_SUCCESS   if all self-test code passed
+ *    - XST_FAILURE   if any self-test code failed
+ *
+ * @note    Caching must be turned off for this function to work.
+ * @note    Self test may fail if data memory and device are not on the same bus.
+ *
+ */
+XStatus DDR3_TEST_MONITOR_AXI_Reg_SelfTest(void * baseaddr_p);
+
+#endif // DDR3_TEST_MONITOR_AXI_H