Add batch 11 (FPGAwars_icezum, WangXuan95_FPGA-CAN, TILOS-AI-Institute_MacroPlacement, ZipCPU_wbuart32, WangXuan95_FPGA-SDcard-Reader)

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+                    GNU GENERAL PUBLIC LICENSE
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FPGAwars_icezum/Manufacturing-GERBERs/from-kicad/Readme.md

@@ -0,0 +1,11 @@
+* **icezum-Edge.cuts.gbr**: Mechanical layer 1 (*icezum-GM1*)
+* **icezum-F.Cu.gbr**: Copper Top layer (*icezum-GTL*)
+* **icezum-B.Cu.gbr**: Copper Bottom layer (*icezum-GBL*)
+* **icezum-In1.Cu.gbr**: Copper Inner layer 1 (*icezum-G1*)
+* **icezum-In2.Cu.gbr**: Copper Inner layer 2 (*icezum-G2*)
+* **icezum-F.SilkS.gbr**: Top SilkScreen Layer (*icezum-GTO*)
+* **icezum-B.SilkS.gbr**: Bottom SilkScreen Layer (*icezum-GBO*)
+* **icezum-F.Mask.gbr**: Top Solder Mask Layer (*icezum-GTS*)
+* **icezum-B.Mask.gbr**: Bottom Solder Mask Layer (*icezum-GBS*)
+* **icezum-F.Paste.gbr**: Top Paste layer (*icezum-GTP*)
+* **icezum.drl**: Drills

FPGAwars_icezum/Manufacturing-GERBERs/from-kicad/icezum-B.Mask.gbr

@@ -0,0 +1,335 @@
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FPGAwars_icezum/Manufacturing-GERBERs/from-kicad/icezum.drl

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FPGAwars_icezum/README.md

@@ -0,0 +1,105 @@
+# Icezum Alhambra
+Arduino/zum compatible **Open FPGA** electronic board.  Synthesize hardware easily, using **only open source tools**
+
+![](https://github.com/FPGAwars/icezum/raw/master/wiki/V1.1-RC1/icezum-alhambra-v1.1.jpg)
+
+## Features
+
+* FPGA development board ([iCE40HX1K-TQ144](https://github.com/Obijuan/open-fpga-verilog-tutorial/raw/master/tutorial/doc/iCE40LPHXFamilyDataSheet.pdf) from lattice)
+* Open hardware
+* Compatible with the [opensource icestorm toolchain](http://www.clifford.at/icestorm/)
+* Arduino like board: similar pinout than Arduino one / [BQ zum](https://store.bq.com/es/placa-zum-core).
+* You can Reuse most of available shields
+* Control your robots / printbots from an FPGA
+* 12 MHZ MEMS oscillator
+* ON/OFF switch (turn off your mobile robot easily)
+* Input power voltage: 6 - 17v
+* Max input current: 3A (Perfect for powering your robots)
+* 20 Input/output 5v pins
+* 8 Input/Output 3.3V pins
+* USB micro-B connector for programming the FPGA from the PC (same as zum board)
+* [FTDI 2232H](www.ftdichip.com/Documents/DataSheets/ICs/DS_FT2232H.pdf) USB device allows FPGA programming and UART interface to a PC
+* Reset pushbutton
+* 8 general purpose leds (user leds)
+* 2 general purpose pushbuttons
+* 4 analogue inputs though I2C bus ([ADS7924](http://www.ti.com/lit/ds/symlink/ads7924.pdf) from TI)
+
+## Documentation
+
+[The project documentation is located in the wiki](https://github.com/FPGAwars/icezum/wiki)
+
+## History
+
+### Icezum Alhambra releases and EDA tools used over time
+
+![](https://github.com/FPGAwars/icezum/raw/master/wiki/Icezum-alhambra-releases-tools-diagram.png)
+
+### V1.0
+* **2015-12-20**: The icezum board was conceived in the **BQlabs**, the robotics and innovation department at [BQ](https://www.bq.com/es/). The idea was to have a very easy to use FPGA board, fully openhardware, similar to Arduino/ZUM boards, so that anyone can connect sensors and create robots or small projects using an FPGA instead of a processor. We wanted to extend the educational approach of BQ to the digital circuits design. At that time, Juan Gonzalez (Obijuan) was the head of the department. Eladio Delgado, a very-skilled senior external engineer was assigned the task of designing the board. He was already involve in other projects with BQ
+
+* **2016-02-18**: [The icezum board bqlabs repo](https://github.com/bqlabs/icezum) at github is created and all the V1.0 files released
+
+*  **2016-02-29**: The board was renamed to **Icezum Alhambra** because Eladio lives in a small town in Granada. The name was suggested by **Sebastián Gallardo** in [this post in the FPGAwars community](https://groups.google.com/d/msg/fpga-wars-explorando-el-lado-libre/f1W0Vtt5NdE/LEDRSXudGwAJ) (In Spanish)
+
+* **2016-03-05**: The first prototype is built and a bitstream is successfully upload into the board! [Images](https://github.com/FPGAwars/icezum/raw/master/doc/2016-03-04-Mounting-first-prototype/icezum-alhambra-mounting-15.jpg) 10 PCBs were manufactured in total. 5 Prototypes were mounted (by hand) by Eladio and his sister María. 5 more were mounted one mounth later
+
+* **2016-04-14**: BQlabs was disolved and this proyect was stopped. Many thanks to BQ  for all its help during this period. Thanks for sponsoring the Icezum board
+
+
+### V1.0K
+* **2016-04-20**: The project is continued by the FPGAwars community, lead by Obijuan. The [FPGAwars github organization](https://github.com/FPGAwars)) is created and all the repositories related to openfpgas are moved there
+
+* **2016-05-01**: A Small local crowdfunding is organized in the FPGAwars community ([Original message, in spanish](https://groups.google.com/d/msg/fpga-wars-explorando-el-lado-libre/oLFzYPqCOcQ/OsMxYKnuAQAJ)). Only 100 V1.1 boards will be manufactured if an amount of 6500€ is raised
+
+* **2016/05/18**: After two weeks, we already have the commitment of the people for paying the money for building the boards ([Board funded!](https://groups.google.com/d/msg/fpga-wars-explorando-el-lado-libre/oLFzYPqCOcQ/luBcnXpBBwAJ))
+
+* **2016/05/30**: The icezum Alhambra is being **migrated to Kicad** by Juan Gonzalez (Obijuan). Also the 3D models were designed with FreeCAD, so that the Icezum Alhambra is not only an openhardware board, but also a board **designed with opensource tools**. This way, anyone in the world can easily have access to all the designs, to study them, modify them and creating new boards from them. This version will be called V1.0K (K stands for kicad). It is not going to be manufactured, but rather a starting point for the future versions
+
+* **2016/07/03**: All the money (6500€ in total) is received from the backers! Thanks a lot!!! ([Backers list](https://docs.google.com/spreadsheets/d/1yngU6kfMr5JWJYXrxBMJ7l1Cai2iuucMDoND4NpgU5Y))
+
+* **2016/07/28**: V1.0K is released!
+
+### V1.1
+
+ * **2016/04/20**: In paralell with the V1.0K version, Eladio started to work on the V1.1, which is the one that will be manufactured for the backers. As there were still no Kicad version when Eladio started, It is being designed in Altium and will be migrated later to Kicad as the V1.1K version
+ 
+ * **2016/09/22**: Three Icezum Alhambra V1.1-RC1 are hand mounted and tested. They work ok!. The PCBs were manufactured in pcbway. The design is validated
+
+ * **2016/10/03**: [Icezum Alhambra v1.1-RC1 is released](https://github.com/FPGAwars/icezum/releases/tag/v1.1-RC1)
+ 
+### V1.1K
+ 
+ TODO
+
+## Authors
+
+* **V1.0**: [Eladio Delgado Mingorance](https://twitter.com/EladioDM). Sponsored by [BQ](https://www.bq.com/es/)
+* **V1.0K**: Migrated to Kicad by Juan González (Obijuan). 3D models designed with FreeCAD. Everything is generated using only opensource tools (schematics, pcb, 3D models, pinout, BOM...). This version belongs to our T**echnological Heritage**
+* **V1.1**: Eladio Delgado Mingorance, from Pinos del Valle, Granada, Spain
+
+## Credits
+* [BQ](https://www.bq.com/es/). Thanks for funding this project from 2015-12-20 to 2016-04-14. During this period, the icezum V1.0 was born and 10 prototypes were manufactured.
+* María Delgado Mingorance, for helping in the manufacturing and design of the V1.0
+* V1.0 was derived from the [Arduino Uno board](https://www.arduino.cc/en/Main/ArduinoBoardUno)
+* V1.0 was derived from the [zum core board](https://github.com/bq/zum/tree/master/zum-core) by BQ
+* V1.0 was derived from the [Icestick](http://www.latticesemi.com/icestick) by Lattice
+* V1.0K was derived from Icezum Alhambra V1.0 by BQ
+* V1.1 was derived from Icezum Alhambra V1.0 by BQ
+* [Icestorm project](http://www.clifford.at/icestorm/), by Clifford Wolf and Mathias Lasser
+* Icezum Pinout, by [Alberto Piganti](http://www.pighixxx.com/test/2016/05/icezum-pinout/)
+* [Jairo Zerberos](https://github.com/zerberros). Migration of the FT2232H schematic symbol from altium to kicad. Thanks!
+* [altium2kicad](https://github.com/thesourcerer8/altium2kicad]). Tool used for the migration from Altium to Kicad. Many thanks to the developers!
+* [Kicadstepup](https://sourceforge.net/projects/kicadstepup/). Tool for exporting the board to FreeCAD
+* [Alhambra festival picture](http://beentheredrawnthat.blogspot.com.es/2016/07/festivales-de-musica-y-danza-alhambra.html), by Cristina Urdiales. Thanks for this beautiful paiting!
+* Juan González (Obijuan): V1.0 specifications. Migration to Kicad (V1.0K)
+
+## Acknowledges
+* Many thanks to [BQ](https://www.bq.com/es/), for funding the initial prototype V1.0, during the period 2015-12-20 to 2016-04-14. Thanks a lot for increasing our technological heritage by sponsoring openhardware boards.
+
+![](https://github.com/FPGAwars/icezum/raw/master/wiki/bq-logo.png)
+
+## License
+
+![](https://github.com/FPGAwars/icezum/raw/master/wiki/attribution-share-alike-creative-commons-license.png)
+
+Licensed under [Creative Commons Attribution-ShareAlike 4.0 International License](http://creativecommons.org/licenses/by-sa/4.0/)

FPGAwars_icezum/doc/BOM/icezum-bom.ods

@@ -0,0 +1,3 @@
+version https://git-lfs.github.com/spec/v1
+oid sha256:1d8e11c426d1866911a1961abf58d361696574bbb45438d287cdb9b53438c33f
+size 2295041

FPGAwars_icezum/examples/leds/leds_on/.gitignore

@@ -0,0 +1 @@
+.pioenvs

FPGAwars_icezum/examples/leds/leds_on/lib/readme.txt

@@ -0,0 +1,38 @@
+
+This directory is intended for the project specific (private) libraries.
+PlatformIO will compile them to static libraries and link to executable file.
+
+The source code of each library should be placed in separate directory, like
+"lib/private_lib/[here are source files]".
+
+For example, see how can be organized `Foo` and `Bar` libraries:
+
+|--lib
+|  |--Bar
+|  |  |--docs
+|  |  |--examples
+|  |  |--src
+|  |     |- Bar.c
+|  |     |- Bar.h
+|  |--Foo
+|  |  |- Foo.c
+|  |  |- Foo.h
+|  |- readme.txt --> THIS FILE
+|- platformio.ini
+|--src
+   |- main.c
+
+Then in `src/main.c` you should use:
+
+#include <Foo.h>
+#include <Bar.h>
+
+// rest H/C/CPP code
+
+PlatformIO will find your libraries automatically, configure preprocessor's
+include paths and build them.
+
+See additional options for PlatformIO Library Dependency Finder `lib_*`:
+
+http://docs.platformio.org/en/latest/projectconf.html#lib-install
+

FPGAwars_icezum/examples/leds/leds_on/platformio.ini

@@ -0,0 +1,23 @@
+#
+# Project Configuration File
+#
+# A detailed documentation with the EXAMPLES is located here:
+# http://docs.platformio.org/en/latest/projectconf.html
+#
+
+# A sign `#` at the beginning of the line indicates a comment
+# Comment lines are ignored.
+
+# Simple and base environment
+# [env:mybaseenv]
+# platform = %INSTALLED_PLATFORM_NAME_HERE%
+# framework =
+# board =
+#
+# Automatic targets - enable auto-uploading
+# targets = upload
+
+[env:icestick]
+platform = lattice_ice40
+framework = icestorm
+board = icestick

FPGAwars_icezum/examples/leds/leds_on/src/Makefile

@@ -0,0 +1,63 @@
+#-----------------------------------------------------
+#-- Project 1
+#-----------------------------------------------------
+NAME = leds_on
+DEPS =
+
+#------------- Simulation of project 1 ---------
+sim: $(NAME)_tb.vcd
+	gtkwave $< $(<:.vcd=.gtkw) &
+
+#-- set the dependencies for simulation
+$(NAME)_tb.vcd: $(NAME).v $(DEPS) $(NAME)_tb.v
+
+#---- Synthesis of project 1 ------------------
+sint: $(NAME).bin
+
+#-- Set the dependencies for synthetization
+$(NAME).blif: $(NAME).v $(DEPS)
+
+#-- Set the dependencies for the place and route
+$(NAME).asc: $(NAME).blif $(NAME).pcf
+
+#---- Upload into FPGA of project 1 ------
+prog: $(NAME).bin
+	iceprog $<
+
+# --- Time report
+time: $(NAME).rpt
+
+
+#--------------------------------
+#-- General Compilation rules
+#--------------------------------
+
+.SUFFIXES: .asc .bin .blif .v .vcd .rpt
+
+# -- Rule for generating time reports
+.asc.rpt:
+	icetime -d hx1k -mtr $@ $^
+
+#-- Rule for generating the simulations
+.v.vcd:
+		iverilog $^ -o $(@:.vcd=.out)
+		./$(@:.vcd=.out)
+
+#-- Rule to perform the synthesis
+.v.blif:
+	yosys -p "synth_ice40 -blif $@" $^
+
+#-- Rule to perform the place and route
+#-- The .pcf file should have the same name than the .blif file
+.blif.asc:
+	arachne-pnr -d 1k -p $(@:.asc=.pcf) $< -o $@
+
+#-- Rule to obtain the .bin bitstream from the .txt ascii files
+.asc.bin:
+	icepack $< $@
+
+#-- Clean the project
+clean:
+	rm -f *.bin *.asc *.blif *.out *.vcd examples/*~ *.rpt
+
+.PHONY: all clean

FPGAwars_icezum/examples/leds/leds_on/src/SConstruct

@@ -0,0 +1,132 @@
+# ----------------------------------------------------------------------
+# -- Generic Scons script for Sintesizing hardware with APIO or scons
+# -- on an icestick or Icezum Alhambra
+# ----------------------------------------------------------------------
+import os
+from os.path import join
+import platform
+import glob
+from SCons.Script import (Builder, DefaultEnvironment, Default, AlwaysBuild,
+                          GetOption, Environment, Exit, COMMAND_LINE_TARGETS)
+
+# -- Executables extension
+EXT = ''
+if 'Windows' == platform.system():
+    EXT = '.exe'
+
+# -- Target name
+TARGET = 'hardware'
+
+# -- Get a list of all the verilog files in the src folfer, in ASCII, with
+# -- the full path. All these files are used for the simulation
+v_nodes = glob.glob('*.v')
+src_sim = ["{}".format(f) for f in v_nodes]
+
+# --------- Get the Testbench file (there should be only 1)
+# -- Create a list with all the files finished in _tb.v. It should contain
+# -- the test bench
+list_tb = [f for f in src_sim if f[-5:].upper() == "_TB.V"]
+
+if len(list_tb) > 1:
+    print("---> WARNING: More than one testbenches used")
+
+# -- Error checking
+try:
+    testbench = list_tb[0]
+
+# -- there is no testbench
+except IndexError:
+    testbench = None
+
+if 'sim' in COMMAND_LINE_TARGETS:
+    if testbench is None:
+        print("ERROR!!! NO testbench found for simulation")
+        Exit(1)
+
+    # -- Simulation name
+    SIMULNAME, ext = os.path.splitext(testbench)
+else:
+    SIMULNAME = ''
+
+# -------- Get the synthesis files.  They are ALL the files except the
+# -------- testbench
+src_synth = [f for f in src_sim if f not in list_tb]
+
+# -- For debugging
+print("----> Testbench: {}".format(testbench))
+# print("SIM NAME: {}".format(SIMULNAME))
+
+# -- Get the PCF file
+PCF_list = glob.glob('*.pcf')
+
+try:
+    PCF = PCF_list[0]
+except IndexError:
+    print("\n--------> WARNING: no .pcf file found <----------\n")
+    PCF = 'ERROR.pcf'
+
+# -- Debug
+print("----> PCF Found: {}".format(PCF))
+
+
+# -- Define the Sintesizing Builder
+synth = Builder(action='yosys{0} -p \"synth_ice40 -blif $TARGET\" $SOURCE'.format(EXT),
+                suffix='.blif',
+                src_suffix='.v')
+
+pnr = Builder(action='arachne-pnr{0} -d 1k -o $TARGET -p {1} $SOURCE'.format(EXT, PCF),
+              suffix='.asc',
+              src_suffix='.blif')
+
+bitstream = Builder(action='icepack{0} $SOURCE $TARGET'.format(EXT),
+                    suffix='.bin',
+                    src_suffix='.asc')
+
+# -- Icetime builder
+time_rpt = Builder(action='icetime{0} -d hx1k -mtr $TARGET $SOURCE'.format(EXT),
+                   suffix='.rpt',
+                   src_suffix='.asc')
+
+# -- Build the environment
+env = DefaultEnvironment(BUILDERS={'Synth': synth, 'PnR': pnr,
+                                   'Bin': bitstream, 'Time': time_rpt},
+                         ENV=os.environ, tools=[])
+
+# -- Generate the bitstream
+blif = env.Synth(TARGET, [src_synth])
+asc = env.PnR(TARGET, [blif, PCF])
+bitstream = env.Bin(TARGET, asc)
+
+# -- Upload the bitstream into FPGA
+upload = env.Alias('upload', bitstream, 'iceprog{0} $SOURCE'.format(EXT))
+AlwaysBuild(upload)
+
+# -- Target time: calculate the time
+rpt = env.Time(asc)
+t = env.Alias('time', rpt)
+AlwaysBuild(t)
+
+# -------------------- Simulation ------------------
+# -- Constructor para generar simulacion: icarus Verilog
+iverilog = Builder(action='iverilog $SOURCES -o $TARGET',
+                   suffix='.out',
+                   src_suffix='.v')
+
+vcd = Builder(action=join(glob.os.getcwd(), "$SOURCE"),
+              suffix='.vcd', src_suffix='.out')
+
+simenv = Environment(BUILDERS={'IVerilog': iverilog, 'VCD': vcd},
+                     ENV=os.environ)
+
+out = simenv.IVerilog(SIMULNAME, src_sim)
+vcd_file = simenv.VCD(SIMULNAME, out)
+
+waves = simenv.Alias('sim', SIMULNAME+'.vcd', 'gtkwave ' +
+                     "{} ".format(vcd_file[0]) + " " + SIMULNAME + ".gtkw")
+AlwaysBuild(waves)
+
+Default(bitstream)
+
+# -- These is for cleaning the files generated using the alias targets
+if GetOption('clean'):
+    env.Default([out, t, vcd_file])

FPGAwars_icezum/examples/leds/leds_on/src/leds_on.json

@@ -0,0 +1,235 @@
+{
+  "nodes": [
+    {
+      "label": "",
+      "type": "output",
+      "params": [
+        "95"
+      ],
+      "id": 10,
+      "x": 814,
+      "y": 156,
+      "width": 56,
+      "inputConnectors": [
+        {
+          "label": "95"
+        }
+      ]
+    },
+    {
+      "label": "",
+      "type": "output",
+      "params": [
+        "96"
+      ],
+      "id": 11,
+      "x": 812,
+      "y": 213,
+      "width": 56,
+      "inputConnectors": [
+        {
+          "label": "96"
+        }
+      ]
+    },
+    {
+      "label": "",
+      "type": "output",
+      "params": [
+        "97"
+      ],
+      "id": 12,
+      "x": 812,
+      "y": 273,
+      "width": 56,
+      "inputConnectors": [
+        {
+          "label": "97"
+        }
+      ]
+    },
+    {
+      "label": "",
+      "type": "output",
+      "params": [
+        "98"
+      ],
+      "id": 13,
+      "x": 812,
+      "y": 333,
+      "width": 56,
+      "inputConnectors": [
+        {
+          "label": "98"
+        }
+      ]
+    },
+    {
+      "label": "",
+      "type": "output",
+      "params": [
+        "99"
+      ],
+      "id": 14,
+      "x": 812,
+      "y": 393,
+      "width": 56,
+      "inputConnectors": [
+        {
+          "label": "99"
+        }
+      ]
+    },
+    {
+      "label": "",
+      "type": "output",
+      "params": [
+        "101"
+      ],
+      "id": 16,
+      "x": 812,
+      "y": 461,
+      "width": 64,
+      "inputConnectors": [
+        {
+          "label": "101"
+        }
+      ]
+    },
+    {
+      "label": "",
+      "type": "output",
+      "params": [
+        "102"
+      ],
+      "id": 17,
+      "x": 812,
+      "y": 521,
+      "width": 64,
+      "inputConnectors": [
+        {
+          "label": "102"
+        }
+      ]
+    },
+    {
+      "label": "",
+      "type": "output",
+      "params": [
+        "104"
+      ],
+      "id": 18,
+      "x": 812,
+      "y": 581,
+      "width": 64,
+      "inputConnectors": [
+        {
+          "label": "104"
+        }
+      ]
+    },
+    {
+      "label": "",
+      "type": "driver",
+      "params": [
+        {
+          "name": "B",
+          "value": "1'b1"
+        }
+      ],
+      "vcode": "module driver #(parameter B = 1'b0)(output o);\nassign o = B;\nendmodule\n",
+      "id": 19,
+      "x": 509,
+      "y": 153,
+      "width": 55,
+      "outputConnectors": [
+        {
+          "name": "o",
+          "label": "\"1\""
+        }
+      ]
+    }
+  ],
+  "connections": [
+    {
+      "source": {
+        "nodeID": 19,
+        "connectorIndex": 0
+      },
+      "dest": {
+        "nodeID": 10,
+        "connectorIndex": 0
+      }
+    },
+    {
+      "source": {
+        "nodeID": 19,
+        "connectorIndex": 0
+      },
+      "dest": {
+        "nodeID": 11,
+        "connectorIndex": 0
+      }
+    },
+    {
+      "source": {
+        "nodeID": 19,
+        "connectorIndex": 0
+      },
+      "dest": {
+        "nodeID": 12,
+        "connectorIndex": 0
+      }
+    },
+    {
+      "source": {
+        "nodeID": 19,
+        "connectorIndex": 0
+      },
+      "dest": {
+        "nodeID": 13,
+        "connectorIndex": 0
+      }
+    },
+    {
+      "source": {
+        "nodeID": 19,
+        "connectorIndex": 0
+      },
+      "dest": {
+        "nodeID": 14,
+        "connectorIndex": 0
+      }
+    },
+    {
+      "source": {
+        "nodeID": 19,
+        "connectorIndex": 0
+      },
+      "dest": {
+        "nodeID": 16,
+        "connectorIndex": 0
+      }
+    },
+    {
+      "source": {
+        "nodeID": 19,
+        "connectorIndex": 0
+      },
+      "dest": {
+        "nodeID": 17,
+        "connectorIndex": 0
+      }
+    },
+    {
+      "source": {
+        "nodeID": 19,
+        "connectorIndex": 0
+      },
+      "dest": {
+        "nodeID": 18,
+        "connectorIndex": 0
+      }
+    }
+  ]
+}

FPGAwars_icezum/examples/leds/leds_on/src/leds_on.pcf

@@ -0,0 +1,11 @@
+# -- IceZUM Alhambra leds
+
+set_io LPORT[0] 95 
+set_io LPORT[1] 96
+set_io LPORT[2] 97
+set_io LPORT[3] 98
+
+set_io LPORT[4] 99
+set_io LPORT[5] 101
+set_io LPORT[6] 102
+set_io LPORT[7] 104

FPGAwars_icezum/examples/leds/leds_on/src/leds_on.v

@@ -0,0 +1,16 @@
+//--------------------------------------------------------------------
+//-- IceZUM Alhambra test
+//-- Hello world example
+//-- Turn on all the yellow leds
+//--------------------------------------------------------------------
+//-- (c) BQ March, 2016. Written by Juan Gonzalez (obijuan)
+//--------------------------------------------------------------------
+//-- Releases under the GPL v2+ license
+//--------------------------------------------------------------------
+
+module leds_on(output wire [7:0] LPORT);
+
+//-- Turn on all the leds
+assign LPORT = 8'hFF;
+
+endmodule

FPGAwars_icezum/examples/leds/leds_on/src/leds_on_tb.gtkw

@@ -0,0 +1,23 @@
+[*]
+[*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI
+[*] Tue Mar 15 08:22:44 2016
+[*]
+[dumpfile] "/home/obijuan/development/icezum/examples/leds/leds_on/src/leds_on_tb.vcd"
+[dumpfile_mtime] "Tue Mar 15 08:22:30 2016"
+[dumpfile_size] 460
+[savefile] "/home/obijuan/development/icezum/examples/leds/leds_on/src/leds_on_tb.gtkw"
+[timestart] 0
+[size] 1000 600
+[pos] -1 -1
+*-8.314166 964 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[treeopen] leds_on_tb.
+[sst_width] 223
+[signals_width] 134
+[sst_expanded] 1
+[sst_vpaned_height] 160
+@29
+leds_on_tb.clk
+@22
+leds_on_tb.UUT.LPORT[7:0]
+[pattern_trace] 1
+[pattern_trace] 0

FPGAwars_icezum/examples/leds/leds_on/src/leds_on_tb.v

@@ -0,0 +1,36 @@
+//-------------------------------------------------------------------
+//-- leds_on_tb.v
+//-- Testbench
+//-------------------------------------------------------------------
+//-- BQ March 2016. Written by Juan Gonzalez (Obijuan)
+//-------------------------------------------------------------------
+`default_nettype none
+`timescale 100 ns / 10 ns
+
+module leds_on_tb();
+
+//-- Simulation time: 1us (10 * 100ns)
+parameter DURATION = 10;
+
+//-- Clock signal. It is not used in this simulation
+reg clk = 0;
+always #0.5 clk = ~clk;
+
+//-- Leds port
+wire [7:0] lport;
+
+//-- Instantiate the unit to test
+leds_on UUT (.LPORT(lport));
+
+
+initial begin
+
+  //-- File were to store the simulation results
+  $dumpfile("leds_on_tb.vcd");
+  $dumpvars(0, leds_on_tb);
+
+   #(DURATION) $display("End of simulation");
+  $finish;
+end
+
+endmodule