Add batch 3 (alexforencich_verilog-uart, schlae_graphics-gremlin, quanzaihh_Neural-Network-Accelerator, google_CFU-Playground, abdelazeem201_ASIC-Design-Roadmap)

.gitattributes

@@ -504,3 +504,10 @@ omarelhedaby_CNN-FPGA/Screenshots[[:space:]]and[[:space:]]Reports/Part[[:space:]
 omarelhedaby_CNN-FPGA/Screenshots[[:space:]]and[[:space:]]Reports/Part[[:space:]]3-[[:space:]]SoftMax[[:space:]]activation/Synthesis[[:space:]]Reports[[:space:]]and[[:space:]]Screenshots/SoftMax[[:space:]]Comparison[[:space:]]Report.docx filter=lfs diff=lfs merge=lfs -text
 omarelhedaby_CNN-FPGA/Screenshots[[:space:]]and[[:space:]]Reports/Part[[:space:]]5-[[:space:]]Integration/FC[[:space:]]layer[[:space:]]Waveform.PNG filter=lfs diff=lfs merge=lfs -text
 omarelhedaby_CNN-FPGA/Test.xlsx filter=lfs diff=lfs merge=lfs -text
+quanzaihh_Neural-Network-Accelerator/compile/yolov8/simsun.ttc filter=lfs diff=lfs merge=lfs -text
+quanzaihh_Neural-Network-Accelerator/fig/PPT论文图/机器学习深度学习绘图模板.pptx filter=lfs diff=lfs merge=lfs -text
+quanzaihh_Neural-Network-Accelerator/fig/PPT论文图/机器学习绘图模板.pptx filter=lfs diff=lfs merge=lfs -text
+quanzaihh_Neural-Network-Accelerator/fig/PPT论文图/论文总图.pptx filter=lfs diff=lfs merge=lfs -text
+quanzaihh_Neural-Network-Accelerator/fig/系统框图.vsdx filter=lfs diff=lfs merge=lfs -text
+schlae_graphics-gremlin/isabracket.stl filter=lfs diff=lfs merge=lfs -text
+schlae_graphics-gremlin/verilog/isavideo.binm filter=lfs diff=lfs merge=lfs -text

abdelazeem201_ASIC-Design-Roadmap/.github/workflows/blank.yml

@@ -0,0 +1,36 @@
+# This is a basic workflow to help you get started with Actions
+
+name: CI
+
+# Controls when the workflow will run
+on:
+  # Triggers the workflow on push or pull request events but only for the "main" branch
+  push:
+    branches: [ "main" ]
+  pull_request:
+    branches: [ "main" ]
+
+  # Allows you to run this workflow manually from the Actions tab
+  workflow_dispatch:
+
+# A workflow run is made up of one or more jobs that can run sequentially or in parallel
+jobs:
+  # This workflow contains a single job called "build"
+  build:
+    # The type of runner that the job will run on
+    runs-on: ubuntu-latest
+
+    # Steps represent a sequence of tasks that will be executed as part of the job
+    steps:
+      # Checks-out your repository under $GITHUB_WORKSPACE, so your job can access it
+      - uses: actions/checkout@v3
+
+      # Runs a single command using the runners shell
+      - name: Run a one-line script
+        run: echo Hello, world!
+
+      # Runs a set of commands using the runners shell
+      - name: Run a multi-line script
+        run: |
+          echo Add other actions to build,
+          echo test, and deploy your project.

abdelazeem201_ASIC-Design-Roadmap/Guide to HDL Coding Styles for Synthesis/ReadMe

@@ -0,0 +1 @@
+Guide to HDL Coding Styles for Synthesis

abdelazeem201_ASIC-Design-Roadmap/HDL Compiler for Verilog Reference Manual/ReadMe

@@ -0,0 +1,2 @@
+
+HDL Compiler for Verilog Reference Manual

abdelazeem201_ASIC-Design-Roadmap/IC Compiler II/Memory_NDM_Generation.tcl

@@ -0,0 +1,119 @@
+#--------------------------------------------------
+# Script: Memory NDM Generation for Multiple SRAM Macros
+# Description:
+#   - Reads LEF and multiple CCS timing DBs for each memory macro
+#   - Creates a workspace per macro
+#   - Generates corresponding NDM files
+#--------------------------------------------------
+
+#-------------------------------
+# Configuration
+#-------------------------------
+
+# Technology file
+set tech_file "xx.tf"
+
+# List of memory macros to process
+set MEM_LIST "
+MEM1
+MEM2
+MEM3
+MEM4
+MEM5
+MEM6
+MEM7
+MEM8
+"
+
+# Paths to required files
+set lef_dir     "SRAM/LEF"
+set db_dir      "SRAM/DB"
+set mem_ndm_dir "./ndm"
+
+# Bus delimiter configuration
+set bus_delimiter {[]}
+
+# Continue execution even if errors occur
+set sh_continue_on_error true
+
+#-------------------------------
+# Set Common App Options
+#-------------------------------
+
+# General workspace and modeling options
+set_app_options -as_user_default -name lib.workspace.group_libs_naming_strategies        "common_prefix common_suffix common_prefix_and_common_suffix first_logical_lib_name"
+set_app_options -as_user_default -name lib.workspace.group_libs_create_slg              false
+set_app_options -as_user_default -name lib.workspace.allow_missing_related_pg_pins      true
+set_app_options -as_user_default -name lib.workspace.remove_frame_bus_properties        true
+set_app_options -as_user_default -name lib.workspace.save_design_views                  true
+set_app_options -as_user_default -name link.require_physical                            true
+set_app_options -as_user_default -name design.bus_delimiters                            $bus_delimiter
+set_app_options -as_user_default -name lib.logic_model.require_same_opt_attrs           false
+set_app_options -as_user_default -name lib.logic_model.use_db_rail_names                true
+set_app_options -as_user_default -name lib.logic_model.auto_remove_timing_only_designs  true
+set_app_options -as_user_default -name lib.physical_model.connect_within_pin            true
+set_app_options -as_user_default -name lib.physical_model.hierarchical                  true
+set_app_options -as_user_default -name lib.physical_model.merge_metal_blockage          false
+set_app_options -as_user_default -name lib.physical_model.block_all                     auto
+set_app_options -as_user_default -name lib.physical_model.preserve_metal_blockage       auto
+
+#-------------------------------
+# Process Each Memory Macro
+#-------------------------------
+
+foreach mem $MEM_LIST {
+    puts "\n### Processing Memory: $mem"
+
+    # Create workspace for this memory
+    create_workspace $mem -tech $tech_file
+
+    # Locate LEF file
+    set lef_file "${lef_dir}/${mem}.lef"
+    if {![file exists $lef_file]} {
+        puts "Warning: LEF file not found for $mem: $lef_file"
+        continue
+    }
+
+    # Read LEF file
+    read_lef $lef_file
+
+    # Prepare DB file list for multiple PVTs
+    set db_files {}
+    foreach pattern {
+        "${mem}*ssgnp0p72vm40c.db"
+        "${mem}*ssgnp0p72v125c.db"
+        "${mem}*ffgnp0p88v125c.db"
+        "${mem}*ffgnp0p88vm40c.db"
+        "${mem}*tt0p8v85c.db"
+    } {
+        foreach db [glob -nocomplain "${db_dir}/$pattern"] {
+            lappend db_files $db
+        }
+    }
+
+    # Read all valid DB files
+    foreach db $db_files {
+        set db_name [file tail $db]
+        # Extract process_label from filename: MEMNAME_<view>_<label>.db
+        set tokens [split $db_name "_"]
+        if {[llength $tokens] >= 3} {
+            set label_token [lindex $tokens 2]
+            set label_name [lindex [split $label_token "."] 0]
+            puts "  - Reading DB: $db (label: $label_name)"
+            read_db $db -process_label $label_name
+        } else {
+            puts "  - Skipping unrecognized DB format: $db_name"
+        }
+    }
+
+    # Check and commit workspace
+    check_workspace -allow_missing
+    commit_workspace -output "${mem_ndm_dir}/${mem}.ndm"
+    remove_workspace
+
+    puts "✅ Finished: $mem"
+}
+
+#-------------------------------
+# End of Script
+#-------------------------------

abdelazeem201_ASIC-Design-Roadmap/IC Compiler II/NDM_Creation.tcl

@@ -0,0 +1,135 @@
+#---------------------------------------------------------------------
+# Script to create a Synopsys NDM Workspace for a standard cell library
+# with multiple PVT corners and physical data
+#----------------------------------------------------------------------
+
+#-------------------------------
+# Configuration Section
+#-------------------------------
+
+# Technology file (defines layers, rules, etc.)
+set tech_file "xxx.tf"
+
+# Physical-only NDM file (contains placement, pin info, etc.)
+set physical_ndm "_physicalonly.ndm"
+
+# Directory paths
+set lef_dir      "LEF"
+set db_dir       "db"
+
+# Library name
+set lib_name     "lib_name"
+
+# Bus delimiter for naming convention
+set bus_delimiter {[]}
+
+# Ensure script continues even if errors occur
+set sh_continue_on_error true
+
+#-------------------------------
+# App Options Setup
+#-------------------------------
+
+# Set workspace-related options for better library merging and naming
+set_app_options -as_user_default -name lib.workspace.group_libs_naming_strategies "common_prefix common_suffix common_prefix_and_common_suffix first_logical_lib_name"
+set_app_options -as_user_default -name lib.workspace.group_libs_create_slg false
+set_app_options -as_user_default -name lib.workspace.allow_missing_related_pg_pins true
+set_app_options -as_user_default -name lib.workspace.remove_frame_bus_properties true
+set_app_options -as_user_default -name lib.workspace.save_design_views true
+set_app_options -as_user_default -name link.require_physical true
+
+# Set delimiter options for bus structures
+set_app_options -as_user_default -name design.bus_delimiters $bus_delimiter
+
+# Logic model configuration
+set_app_options -as_user_default -name lib.logic_model.require_same_opt_attrs false
+set_app_options -as_user_default -name lib.logic_model.use_db_rail_names true
+set_app_options -as_user_default -name lib.logic_model.auto_remove_timing_only_designs true
+
+# Physical model configuration
+set_app_options -as_user_default -name lib.physical_model.connect_within_pin true
+set_app_options -as_user_default -name lib.physical_model.hierarchical true
+set_app_options -as_user_default -name lib.physical_model.merge_metal_blockage false
+set_app_options -as_user_default -name lib.physical_model.block_all auto
+set_app_options -as_user_default -name lib.physical_model.preserve_metal_blockage auto
+
+#-------------------------------
+# Workspace Initialization
+#-------------------------------
+
+# Create a new workspace using the tech file
+create_workspace STD -tech $tech_file -flow normal
+
+# Read physical-only NDM data
+read_ndm $physical_ndm
+
+#-------------------------------
+# Read CCS Timing DB Files per PVT Corner
+#-------------------------------
+foreach pvt {pvt1 pvt2} {
+    set db_file [glob $db_dir/${lib_name}${pvt}_ccs.db]
+    if {[file exists $db_file]} {
+        read_db $db_file -process_label $pvt
+    } else {
+        puts "Warning: Missing DB file for $pvt: $db_file"
+    }
+}
+
+#-------------------------------
+# Setup Site Attributes
+#-------------------------------
+
+# Set default site (typically used for placement grid)
+set_attribute [get_site_defs unit] is_default true
+set_attribute [get_site_defs unit] symmetry Y
+
+#-------------------------------
+# Routing Layer Direction Setup
+#-------------------------------
+
+# Define vertical and horizontal routing layers
+set routing_layers_vertical   {M0 M3 M5 M7 M9 M11}
+set routing_layers_horizontal {M1 M2 M4 M6 M8 M10 AP}
+
+# Set routing directions
+set_attribute [get_layers $routing_layers_vertical]   routing_direction vertical
+set_attribute [get_layers $routing_layers_horizontal] routing_direction horizontal
+
+#-------------------------------
+# Power Pin Attributes
+#-------------------------------
+
+# Classify special VPP power pins as primary power
+foreach pattern {"*/TAP*VPP*VSS*/VPP" "*/TAP*VPP*VBB*/VPP"} {
+    set_attribute -o [get_lib_pins $pattern] port_type power
+    set_attribute -o [get_lib_pins $pattern] pg_type   primary
+}
+
+#-------------------------------
+# Diode Cell Identification
+#-------------------------------
+
+# Identify antenna diode cells and mark accordingly
+set diode_cells [get_object_name [get_lib_cells */ANTENNA*]]
+foreach diode $diode_cells {
+    puts "Marking diode cell: $diode"
+    set_attr -q [get_lib_pins -q $diode/I] -name is_diode -value true 
+    set_attr -q -o [get_lib_cells -q $diode] -name is_diode_cell -value true 
+}
+
+#-------------------------------
+# Final Workspace Checks and Commit
+#-------------------------------
+
+# Check workspace consistency, allow missing views
+check_workspace -allow_missing
+
+# Save the final workspace as an NDM file
+commit_workspace -output "${lib_name}.ndm"
+
+# Clean up
+remove_workspace
+
+#-------------------------------
+# End of Script
+#-------------------------------

abdelazeem201_ASIC-Design-Roadmap/IC Compiler II/NDR_rule.pl

@@ -0,0 +1,105 @@
+#!/usr/bin/perl
+
+#----------------------------------------------------------------------------
+# Script Name: NDR_rule.pl
+#
+# Description:
+# This script is designed to help define **Nondefault Routing Rules (NDRs)** 
+# automatically in Synopsys **IC Compiler II (ICC2)**.
+#
+# In ICC2, nondefault routing rules define special constraints such as increased 
+# width and spacing for clock nets or other critical nets. Normally, these rules 
+# are defined manually for each metal layer, which can be tedious and error-prone.
+#
+# This script reads a Synopsys technology file (.tf), extracts the default 
+# `defaultWidth` and `minSpacing` for each metal layer (M1, M2, ..., M9), and applies 
+# user-specified multipliers to generate NDR-compliant values.
+#
+# It outputs two Tcl variables: WIDTH and SPACE, which can then be used inside ICC2
+# to define routing rules automatically.
+#
+#----------------------------------------------------------------------------
+# Example ICC2 Usage:
+#
+# icc2_shell> set NDR [sh ./NDR_rule.pl TECH_FILE 2 2]
+# icc2_shell> eval $NDR
+# icc2_shell> create_routing_rule 2Wx2S -default -widths $WIDTH -spacings $SPACE
+#
+#----------------------------------------------------------------------------
+# Example Command Line Usage:
+#
+#   perl NDR_rule.pl technology_file spacing_multiplier width_multiplier
+#
+#   e.g. perl NDR_rule.pl saed32nm.tf 2 2
+#
+#----------------------------------------------------------------------------
+# Output:
+#
+#   set WIDTH {M9 0.84 M8 0.84 ... M1 0.24};
+#   set SPACE {M9 0.84 M8 0.84 ... M1 0.24};
+#
+# You can then use these Tcl variables directly in ICC2 to define a routing rule:
+#
+#   create_routing_rule 2Wx2S -default -widths $WIDTH -spacings $SPACE
+#
+#----------------------------------------------------------------------------
+
+use strict;
+use warnings;
+
+# Check for minimum number of arguments
+die "Usage: NDR_rule.pl <techfile> <spacing_multiplier> <width_multiplier>\n"
+    if (@ARGV < 3);
+
+# Read command-line arguments
+my ($techfile, $SM, $WM) = @ARGV;
+
+# Variables to store final WIDTH and SPACE strings
+my ($W, $S) = ("", "");
+
+# Open techfile for reading
+open(my $TECH, "<", $techfile) or die "Cannot open file $techfile: $!";
+
+# Layer processing
+my ($found, $name, $width, $space);
+
+while (my $line = <$TECH>) {
+    chomp $line;
+
+    # End of a layer definition
+    $found = 0 if $line =~ /\}/;
+
+    # Start of a new layer
+    if ($line =~ /^Layer\s+(\S+)/) {
+        $name = $1;
+        $name =~ s/[\"\s]//g;
+        $found = ($name =~ /^M\d+$/) ? 0 : -1;  # Only process metal layers like M1, M2, etc.
+    }
+
+    # Extract defaultWidth
+    if ($line =~ /defaultWidth\s+([\d.]+)/) {
+        $width = $1;
+        $found++ if ($width > 0 && $width < 1);
+    }
+
+    # Extract minSpacing
+    if ($line =~ /minSpacing\s+([\d.]+)/) {
+        $space = $1;
+        $found++ if ($space > 0 && $space < 1);
+    }
+
+    # When all conditions are met
+    if ($found == 2) {
+        my $scaled_width  = $width * $WM;
+        my $scaled_space  = $space * $SM;
+        $W = "$name $scaled_width $W";
+        $S = "$name $scaled_space $S";
+        $found = 0;
+    }
+}
+
+close $TECH;
+
+# Print out the TCL-style formatted outputs
+print "set WIDTH \{$W\};\n";
+print "set SPACE \{$S\};\n";

abdelazeem201_ASIC-Design-Roadmap/IC Compiler II/PnR.tcl

@@ -0,0 +1,210 @@
+set_host_options -max_cores 16
+source ./input/common_setup.tcl
+
+set link_library $LINK_LIBRARY_FILES_MVT
+set target_library $TARGET_LIBRARY_FILES_MVT
+
+set power "VDD"
+set ground "VSS"
+create_lib -ref_libs $NDM_REFERENCE_LIB_DIRS_MVT -technology $TECH_FILE ../work/chiptop
+
+read_parasitic_tech -tlup $TLUPLUS_MAX_FILE -layermap $MAP_FILE
+read_parasitic_tech -tlup $TLUPLUS_MIN_FILE -layermap $MAP_FILE
+
+set TOP_DESIGN ChipTop
+set gate_verilog "../../dc/output/compile.v"
+
+read_verilog -top $TOP_DESIGN $gate_verilog
+current_design $TOP_DESIGN
+
+set_attribute [get_layers M1] routing_direction vertical
+set_attribute [get_layers M2] routing_direction horizontal
+set_attribute [get_layers M3] routing_direction vertical
+set_attribute [get_layers M4] routing_direction horizontal
+set_attribute [get_layers M5] routing_direction vertical
+set_attribute [get_layers M6] routing_direction horizontal
+set_attribute [get_layers M7] routing_direction vertical
+set_attribute [get_layers M8] routing_direction horizontal
+set_attribute [get_layers M9] routing_direction vertical
+set_attribute [get_layers MRDL] routing_direction horizontal
+
+set_wire_track_pattern -site_def unit -layer M1 -mode uniform -mask_constraint{mask_two mask_one} 
+\-coord 0.037 -space 0.074 -direction vertical
+
+source ../scripts/mcmm.tcl
+
+#./output/ChipTop_pads.v
+
+initialize_floorplan -flip_first_row true -boundary {{0 0} {400 400}} -core_offset {15 15 15 15}
+
+place_pins -ports [get_ports *]
+
+create_net -power $NDM_POWER_NET
+create_net -ground $NDM_GROUND_NET
+
+connect_pg_net -net $NDM_POWER_NET [get_pins -hierarchical "*/VDD"]
+connect_pg_net -net $NDM_GROUND_NET [get_pins -hierarchical "*/VSS"]
+
+#########################################SRAMs'Placement################################################################
+set sram_width 54.468
+set sram_space 40
+set sram_start_x 55.4690
+set sram_start_y 246.60
+
+set_attribute [get_cells MemYHier_MemXb] orientation R0
+set_attribute [get_cells MemYHier_MemXa] orientation R0
+set_attribute [get_cells MemXHier_MemXb] orientation R0
+set_attribute [get_cells MemXHier_MemXa] orientation R0
+set_attribute [get_cells MemYHier_MemXb] origin "$sram_start_x $sram_start_y"
+set_attribute [get_cells MemYHier_MemXa] origin "[expr $sram_start_x + $sram_width 
++ $sram_space] $sram_start_y"
+set_attribute [get_cells MemXHier_MemXb] origin "[expr $sram_start_x + 
+2*($sram_width + $sram_space)] $sram_start_y"
+set_attribute [get_cells MemXHier_MemXa] origin "[expr $sram_start_x + 
+3*($sram_width + $sram_space)] $sram_start_y"
+set_fixed_objects [get_cell MemXHier_MemXa]
+set_fixed_objects [get_cell MemXHier_MemXb]
+set_fixed_objects [get_cell MemYHier_MemXa]
+set_fixed_objects [get_cell MemYHier_MemXb]
+create_keepout_margin -type hard -outer {20 20 20 20} [get_cells Mem?Hier_MemX?]
+
+###################################################################################
+#########################################
+create_placement -floorplan -timing_driven
+legalize_placement
+#########################################Routing Blockages On Macro 
+Cells################################################################
+create_routing_blockage -layers {M1 M2 M3 M4 M5} -boundary [get_attribute 
+[get_cells MemXHier_MemXa] boundary]
+create_routing_blockage -layers {M1 M2 M3 M4 M5} -boundary [get_attribute 
+[get_cells MemYHier_MemXa] boundary]
+create_routing_blockage -layers {M1 M2 M3 M4 M5} -boundary [get_attribute 
+[get_cells MemXHier_MemXb] boundary]
+create_routing_blockage -layers {M1 M2 M3 M4 M5} -boundary [get_attribute 
+[get_cells MemYHier_MemXb] boundary]
+####Connect P/G Pins and Create Power Rails#################
+create_pg_mesh_pattern P_top_two \
+-layers { \
+{ {horizontal_layer: M7} {width: 0.2} {spacing: interleaving} {pitch: 
+30} {offset: 0.856} {trim : true} } \
+{ {vertical_layer: M6} {width: 0.2} {spacing: interleaving} {pitch: 
+30} {offset: 6.08} {trim : true} } \
+} 
+set_pg_strategy S_default_vddvss \
+-core \
+-pattern { {name: P_top_two} {nets:{VSS VDD}} } \
+-extension { {{stop:design_boundary_and_generate_pin}} }
+compile_pg -strategies {S_default_vddvss} 
+remove_routing_blockages *
+####Rings Creation Around Macro Cells#################
+set macro_list {MemXHier_MemXa MemYHier_MemXa MemXHier_MemXb MemYHier_MemXb} 
+
+create_pg_ring_pattern P_HM_ring -horizontal_layer M7 -horizontal_width {1} -vertical_layer M6 -vertical_width {1} -corner_bridge false
+set_pg_strategy S_HM_ring_top -macros $macro_list -pattern { {pattern: 
+P_HM_ring} {nets: {VSS VDD}} {offset: {0.1 0.1}} }
+compile_pg -strategies {S_HM_ring_top } 
+create_routing_blockage -layers * -boundary { {45 425} {305 617} }
+## Create std rail
+#VDD VSS
+create_pg_std_cell_conn_pattern std_rail_conn1 -rail_width 0.094 -layers M1
+set_pg_strategy std_rail_1 -pattern {{name : std_rail_conn1} {nets: "VDD VSS"}} -core
+compile_pg -strategies std_rail_1
+#####################################################################################
+####################Analyze IR drop##################################################
+set die_llx [lindex [lindex [ get_attribute [get_core_area] bbox] 0] 0]
+set die_lly [lindex [lindex [ get_attribute [get_core_area] bbox] 0] 1]
+set die_urx [lindex [lindex [ get_attribute [get_core_area] bbox] 1] 0]
+set die_ury [lindex [lindex [ get_attribute [get_core_area] bbox] 1] 1]
+
+for {set i "[expr $die_llx + 20]"} {$i < "[expr $die_urx - 40]"} {set i [expr $i + 80]} {
+	set_virtual_pad -net VSS -coordinate [format {%.1f %.1f} $i $die_lly]
+	set_virtual_pad -net VDD -coordinate [format {%.1f %.1f} [expr $i + 40] $die_lly]
+
+	set_virtual_pad -net VSS -coordinate [format {%.1f %.1f}  $i $die_ury]
+	set_virtual_pad -net VDD -coordinate [format {%.1f %.1f} [expr $i + 40] $die_ury]
+}
+for {set i "[expr $die_lly + 20]"} {$i < "[expr $die_ury - 40]"} {set i [expr $i + 80]} {
+	set_virtual_pad -net VSS -coordinate [format {%.1f %.1f} $die_llx $i]
+	set_virtual_pad -net VDD -coordinate [format {%.1f %.1f} $die_llx [expr $i + 40]]
+
+	set_virtual_pad -net VSS -coordinate [format {%.1f %.1f} $die_urx $i]
+	set_virtual_pad -net VDD -coordinate [format {%.1f %.1f} $die_urx [expr $i + 40] ]
+}
+
+analyze_power_plan -power_budget 250 -voltage 1.2 -nets {VDD VSS} -use_terminals_as_pads
+###################################################################################
+###########################
+############place_opt#################################
+set_app_options -name time.disable_recovery_removal_checks -value false
+set_app_options -name time.disable_case_analysis -value false
+set_app_options -name place.coarse.continue_on_missing_scandef -value true
+place_opt
+legalize_placement
+report_placement
+###################################################################################
+#########################
+## std filler
+set pnr_std_fillers "SAEDRVT14_FILL*"
+set std_fillers ""
+foreach filler $pnr_std_fillers { lappend std_fillers "*/${filler}" }
+create_stdcell_filler -lib_cell $std_fillers
+connect_pg_net -net $power [get_pins -hierarchical "*/VDD"]
+connect_pg_net -net $ground [get_pins -hierarchical "*/VSS"]
+remove_cells [get_cells -filter ref_name=~"*FILL*" ]
+#########################Setting CTS Options###############################
+remove_routing_blockages *
+create_routing_rule ROUTE_RULES_1 \
+ -widths {M3 0.2 M4 0.2 } \
+ -spacings {M3 0.42 M4 0.63 }
+set_clock_routing_rules -rules CLK_SPACING -min_routing_layer M2 -max_routing_layer
+M4
+set_clock_tree_options -target_latency 0.000 -target_skew 0.000 
+###################################################################################
+###########################
+############clock_opt#################################
+
+clock_opt 
+###################################################################################
+#########################
+
+############route_opt#################################
+remove_ignored_layers -all
+set_ignored_layers \
+ -min_routing_layer $MIN_ROUTING_LAYER \
+ -max_routing_layer $MAX_ROUTING_LAYER
+route_opt
+###################################################################################
+#########################
+## std filler
+set pnr_std_fillers "SAEDRVT14_FILL*"
+set std_fillers ""
+foreach filler $pnr_std_fillers { lappend std_fillers "*/${filler}" }
+create_stdcell_filler -lib_cell $std_fillers
+connect_pg_net -net $NDM_POWER_NET [get_pins -hierarchical "*/VDD"]
+connect_pg_net -net $NDM_GROUND_NET [get_pins -hierarchical "*/VSS"]
+###########reports##########################
+#report_area
+report_design -all
+report_timing
+report_power 
+save_block -as "${TOP_DESIGN}_Final"
+save_lib
+change_names -rules verilog -verbose
+write_parasitics -output {../output/${TOP_DESIGN}.spef}
+write_verilog \
+-include {pg_netlist unconnected_ports} \
+../output/${TOP_DESIGN}_pg.v
+write_verilog \
+-exclude {pg_netlist} \
+../output/${TOP_DESIGN}.v
+write_gds -design ${TOP_DESIGN}_Final \
+ -layer_map $GDS_MAP_FILE \
+ -keep_data_type \
+ -fill include \
+ -output_pin all \
+ -merge_files [list $STD_CELL_GDS $SRAM_SINGLE_GDS] \
+ -long_names \
+ ../output/${TOP_DESIGN}.gds
+#close_block
+#close_lib
+#exit

abdelazeem201_ASIC-Design-Roadmap/IC Compiler II/Scripts/01_common_setup.tcl

@@ -0,0 +1,36 @@
+##############################################################
+# Common design settings
+# Created by Ahmed Abdelazeem
+##############################################################
+set_host_options -max_cores 16
+set_app_var sh_continue_on_error true
+### design information
+set DESIGN_NAME  		  "pit_top";
+
+set Design_LIBRARY                "/home/abdelazeem/Desktop/Abdelazeem/PGDip/Project/StandardCell/NangateOpenCellLibrary_PDKv1_3_v2010_12";
+set DESIGN_REF_PATH		  "$Design_LIBRARY/lib/Front_End/Liberty/NLDM"
+set DESIGN_REF_TECH_PATH    	  "$Design_LIBRARY/tech/techfile/milkyway"
+set_app_var search_path           "$Design_LIBRARY $DESIGN_REF_PATH $DESIGN_REF_TECH_PATH"
+set NDM_REFERENCE_LIB_DIRS  	  "$Design_LIBRARY/CLIBS/NangateOpenCellLibrary_ss0p95v125c.ndm \
+				   $Design_LIBRARY/CLIBS/NangateOpenCellLibrary_ff1p25v0c.ndm"
+
+set TECH_FILE                     "${DESIGN_REF_TECH_PATH}/FreePDK45_10m.tf" 
+set MAP_FILE                      "$Design_LIBRARY/tech/rcxt/FreePDK45_10m.map"  ;#  Mapping file for TLUplus
+set TLUPLUS_MAX_FILE              "$Design_LIBRARY/tech/rcxt/FreePDK45_10m_Cmax.tlup"  ;#  Max TLUplus file
+set TLUPLUS_MIN_FILE              "$Design_LIBRARY/tech/rcxt/FreePDK45_10m_Cmin.tlup"  ;#  Min TLUplus file
+set GDS_MAP_FILE		  "$Design_LIBRARY/tech/strmout/FreePDK45_10m_gdsout.map"	
+set STD_CELL_GDS          	  "$Design_LIBRARY/lib/Back_End/gds/NangateOpenCellLibrary.gds"
+
+set ROUTING_LAYER_DIRECTION_OFFSET_LIST "{metal1 horizontal} {metal2 vertical} {metal3 horizontal} {metal4 vertical} {metal5 horizontal} {metal6 vertical} {metal7 horizontal} {metal8 vertical} {metal9 horizontal} {metal10 vertical}"
+set MIN_ROUTING_LAYER		"metal1"	;# Min routing layer name; normally should be specified; otherwise tool can use all metal layers
+set MAX_ROUTING_LAYER		"metal10"	;# Max routing layer name; normally should be specified; otherwise tool can use all metal layers
+
+set NDM_POWER_NET                "VDD" ;#
+set NDM_POWER_PORT               "VDD" ;#
+set NDM_GROUND_NET               "VSS" ;#
+set NDM_GROUND_PORT              "VSS" ;#
+
+
+set SYN_DIR                      "/home/abdelazeem/Desktop/Abdelazeem/PGDip/Project/syn"
+set VERILOG_NETLIST_FILES	 "$SYN_DIR/output/${DESIGN_NAME}.v"	;# Verilog netlist files; 
+set SDC_CONSTRAINTS 		 "$SYN_DIR/output/${DESIGN_NAME}.sdc"	

abdelazeem201_ASIC-Design-Roadmap/IC Compiler II/Scripts/02_mcmm_setup.tcl

@@ -0,0 +1,60 @@
+##############################################################
+# MCMM design settings
+# Created by Ahmed Abdelazeem
+##############################################################
+########################################
+## Variables
+########################################
+## Scenario constraints; expand the section as needed
+set SDC_CONSTRAINTS 		 "$SYN_DIR/output/${DESIGN_NAME}.sdc"
+
+########################################
+## Create modes, and corners
+########################################
+remove_modes -all; 
+remove_corners -all; 
+remove_scenarios -all
+
+create_corner slow
+create_corner fast
+
+create_mode func
+current_mode func
+##############################################################################################
+# The following is a sample script to read two TLU+ files, 
+# which you can expand to accomodate your design.
+##############################################################################################
+
+read_parasitic_tech \
+	-tlup $TLUPLUS_MAX_FILE \
+	-layermap $MAP_FILE \
+	-name tlup_max
+
+read_parasitic_tech \
+	-tlup $TLUPLUS_MIN_FILE \
+	-layermap $MAP_FILE \
+	-name tlup_min
+set_parasitics_parameters \
+	-early_spec tlup_min \
+	-late_spec tlup_min \
+	-corners {fast}
+
+set_parasitics_parameters \
+	-early_spec tlup_max \
+	-late_spec tlup_max \
+	-corners {slow}	
+########################################
+## Create scenario
+########################################
+create_scenario -mode func -corner fast -name func_fast
+create_scenario -mode func -corner slow -name func_slow
+
+current_scenario func_fast
+source $SDC_CONSTRAINTS
+
+current_scenario func_slow
+source $SDC_CONSTRAINTS
+########################################
+## Configure analysis settings for scenarios
+########################################
+remove_duplicate_timing_contexts

abdelazeem201_ASIC-Design-Roadmap/IC Compiler II/Scripts/03_PnR_setup.tcl

@@ -0,0 +1,536 @@
+##########################################################################################
+# Tool: IC Compiler II
+# Script: PnR.tcl (template)
+# Version: P-2020.03-SP4
+# Copyright (C) 2023-2024 Ahmed Abdelazeem, Inc. All rights reserved.
+##########################################################################################
+
+##############################################
+########### 1. DESIGN SETUP ##################
+##############################################
+
+##################################
+## Setup variables and settings
+##################################
+
+source -echo 01_common_setup.tcl
+
+printvar search_path
+printvar NDM_REFERENCE_LIB_DIRS
+report_host_options
+print_suppressed_messages
+
+##################################
+## Create the design library
+## Load the netlist, SDC, and UPF
+##################################
+create_lib -technology $TECH_FILE  -ref_libs $NDM_REFERENCE_LIB_DIRS ${DESIGN_NAME}.dlib
+
+read_verilog -top ${DESIGN_NAME} $VERILOG_NETLIST_FILES
+
+link_block
+
+report_ref_libs
+
+get_blocks $DESIGN_NAME
+get_blocks ${DESIGN_NAME}.design
+get_blocks ${DESIGN_NAME}.dlib:$DESIGN_NAME
+get_blocks ${DESIGN_NAME}.dlib:${DESIGN_NAME}.design
+
+##################################
+## RC parasitics, placement site
+## and routing layer setup
+##################################
+
+read_parasitic_tech  -tlup $TLUPLUS_MAX_FILE -layermap $MAP_FILE -name tlup_max
+
+read_parasitic_tech  -tlup $TLUPLUS_MIN_FILE -layermap $MAP_FILE -name tlup_min
+
+report_lib -parasitic_tech [current_lib]
+
+get_site_defs
+set_attribute [get_site_defs unit] symmetry Y
+set_attribute [get_site_defs unit] is_default true
+
+set_attribute [get_layers {metal1 metal3 metal5 metal7 metal9}] routing_direction horizontal
+set_attribute [get_layers {metal2 metal4 metal6 metal8 metal10}] routing_direction vertical
+get_attribute [get_layers metal?] routing_direction
+
+report_ignored_layers
+
+####################################
+# Check Design: Pre-Floorplanning
+####################################
+ check_design -checks dp_pre_floorplan
+ 
+##################################
+## Save the block
+##################################
+rename_block -to_block ${DESIGN_NAME}/init_design
+save_block
+close_blocks 
+##############################################
+########### 2. Floorplan #####################
+##############################################
+
+open_block  ${DESIGN_NAME}.dlib:${DESIGN_NAME}/init_design
+# OR
+#open_lib  ${DESIGN_NAME}.dlib
+#open_block  ${DESIGN_NAME}/init_design
+copy_block -from_block pit_top.dlib:pit_top/init_design -to pit_top.dlib:pit_top/floorplan_design 
+## Create Starting Floorplan
+############################
+##################################
+## Load UPF, floorplan, scan-DEF
+##################################
+
+#load_upf ${DESIGN_NAME}.upf
+#commit_upf
+
+set_parasitic_parameters -late_spec tlup_max -early_spec tlup_min
+
+
+source $SDC_CONSTRAINTS
+source 02_mcmm_setup.tcl
+
+## Create Starting Floorplan
+############################
+initialize_floorplan -core_utilization 0.25 -flip_first_row true -core_offset {10 10 10 10}
+
+## CONSTRAINTS
+##############
+## Here, We define more constraints on your design that are related to floorplan stage.
+#report_ignored_layers
+#remove_ignored_layers -all
+#set_ignored_layers -max_routing_layer metal6
+
+## Initial Virtual Flat Placement
+#################################
+## Use the following command with any of its options to meet a specific target
+#    create_placement -floorplan -timing_driven -congestion -buffering_aware_timing_driven 
+place_pins -ports [get_ports *]
+
+create_placement -floorplan
+legalize_placement
+set_block_pin_constraints -self -allowed_layers {M3 M4 M5 M6}
+
+##AH## ## To show design-specific blocks
+##AH## gui_set_highlight_options -current_color yellow
+##AH## change_selection [get_cells  wishbone_addr_latch_reg_0_
+
+##AH## gui_set_highlight_options -current_color blue
+##AH##  change_selection [get_cells   wishbone_addr_latch_reg_2_ 
+
+##AH## gui_set_highlight_options -current_color green
+##AH## change_selection [get_cells   */*]
+
+##AH## gui_set_highlight_options -current_color orange
+##AH## change_selection [get_cells   egs_mod_value_reg_1_]
+
+## ASSESSMENT
+#############
+## Analyze Congestion
+# report_congestion -rerun_global_router 
+route_global -congestion_map_only true -effort high   
+# View Congestion map : In GUI,  > Global Route Congestion Map.
+
+## Analyze Timing
+# estimate_timing; # Improves accuracy of timing after updated GR.
+
+#report_timing -nosplit; # For Worst Setup violation report
+#report_timing -nosplit -delay_type min; # For Worst Hold violation report
+
+#report_constraint -all_violators -nosplit -max_delay; # For all Setup violation report
+#report_constraint -all_violators -nosplit -min_delay; # For all Hold violations report
+
+##Based on your assessment, you may need to do any of the following fixes
+
+## FIXES
+########
+## You can use one or all of the follwoing based on your need.
+#   estimate_timing 
+#
+#   create_bound -name "temp" -coordinate {55 0 270 270} datamem
+#   create_bound -name "temp1" -coordinate {0 0 104 270} reg_file
+#
+#   set_congestion_options -max_util 0.4 -coordinate {x1 y1 x2 y2}; # if cell density is causing congestion.
+#
+#   create_placement_blockage -name PB -type hard -bbox {x1 y1 x2 y2}
+#
+#   create_placement -floorplan -congestion_effort high
+#
+## Then you need to re-run create_placement -floorplan 
+#   create_placement -floorplan  -incremental; 
+## Note:  use -incremental option if you want to refine the current virtual placement. Don't use it if you want to re-place the design from scratch 
+
+## If there still congestion, change ignored layers, if it is still there, increase floorplan area.
+
+#################################
+## Perform timing sanity check	
+#################################
+
+report_qor -summary -include setup
+set_app_options -list {time.delay_calculation_style zero_interconnect}
+report_qor -summary -include setup
+
+set_app_options -list {time.high_fanout_net_pin_capacitance 0pF
+                       time.high_fanout_net_threshold 50}
+update_timing -full
+report_qor -summary -include setup
+
+view report_timing -max_paths 5
+
+####################################
+## PG Pin connections
+#####################################
+create_net -power $NDM_POWER_NET
+create_net -ground $NDM_GROUND_NET 
+
+connect_pg_net -net $NDM_POWER_NET [get_pins -hierarchical "*/VDD"]
+connect_pg_net -net $NDM_GROUND_NET [get_pins -hierarchical "*/VSS"]
+
+check_mv_design 
+
+### Write floorplan for later re-use in ICC2
+write_floorplan -net_types {power ground} \
+   -include_physical_status {fixed locked} \
+   -read_def_options {-add_def_only_objects all -no_incremental} \
+   -force -output ./output/{DESIGN_NAME}.fp/
+
+### Write floorplan for DCG:
+write_floorplan -net_types {power ground} \
+   -include_physical_status {fixed locked} \
+   -format icc \
+   -force -output ./output/${DESIGN_NAME}.fp.dc
+
+##################################
+## Save the block
+##################################
+
+save_block -as pit_top.dlib:pit_top/floorplan.design
+save_block
+# or:
+# save_lib
+
+
+##################################################
+########### 3. POWER NETWORK #####################
+##################################################
+copy_block -from_block pit_top.dlib:pit_top/floorplan_design.design -to_block power_plan_1
+current_block power_plan_1.design
+## Defining Logical POWER/GROUND Connections
+############################################
+set_app_option -name plan.pgroute.auto_connect_pg_net -value true
+set_app_option -name plan.pgroute.connect_user_route_shapes -value true
+set_app_option -name plan.pgroute.disable_floating_removal -value true
+set_app_option -name plan.pgroute.disable_trimming -value true
+
+
+create_net -power $NDM_POWER_NET
+create_net -ground $NDM_GROUND_NET 
+
+connect_pg_net -net $NDM_POWER_NET [get_pins -hierarchical "*/VDD"]
+connect_pg_net -net $NDM_GROUND_NET [get_pins -hierarchical "*/VSS"]
+check_mv_design
+
+remove_pg_via_master_rules -all
+remove_pg_patterns -all
+remove_pg_strategies -all
+remove_pg_strategy_via_rules -all
+
+################################################################################
+#-------------------------------------------------------------------------------
+# P G   R I N G   C R E A T I O N
+#-------------------------------------------------------------------------------
+################################################################################
+create_pg_ring_pattern ring_pattern -horizontal_layer metal9 \
+    -horizontal_width {5} -horizontal_spacing {0.8} \
+    -vertical_layer metal10 -vertical_width {5} \
+    -vertical_spacing {0.8} -corner_bridge false
+set_pg_strategy core_ring -core -pattern \
+    {{pattern: ring_pattern}{nets: {VDD VSS}}{offset: {0.8 0.8}}} \
+    -extension {{stop: innermost_ring}}
+
+compile_pg -strategies core_ring
+################################################################################
+#-------------------------------------------------------------------------------
+# P G   M E S H   C R E A T I O N
+#-------------------------------------------------------------------------------
+################################################################################
+
+create_pg_mesh_pattern pg_mesh1 \
+   -parameters {w1 p1 w2 p2 f t} \
+   -layers {{{vertical_layer: metal10} {width: @w1} {spacing: interleaving} \
+        {pitch: @p1} {offset: @f} {trim: @t}} \
+ 	     {{horizontal_layer: metal9 } {width: @w2} {spacing: interleaving} \
+        {pitch: @p2} {offset: @f} {trim: @t}}}
+
+
+set_pg_strategy s_mesh1 \
+   -pattern {{pattern: pg_mesh1} {nets: {VDD VSS VSS VDD}} \
+{offset_start: 5 5} {parameters: 5 80 5 120 5 false}} \
+   -core -extension {{stop: outermost_ring}}
+
+
+compile_pg -strategies s_mesh1
+################################################################################
+#-------------------------------------------------------------------------------
+# S T A N D A R D    C E L L    R A I L    I N S E R T I O N
+#-------------------------------------------------------------------------------
+################################################################################
+create_pg_std_cell_conn_pattern \
+    std_cell_rail  \
+    -layers {metal1} \
+    -rail_width 0.06
+
+set_pg_strategy rail_strat -core \
+    -pattern {{name: std_cell_rail} {nets: VDD VSS} }
+    
+compile_pg -strategies rail_strat    
+################################################################################
+#-------------------------------------------------------------------------------
+# IR Drop Map
+#-------------------------------------------------------------------------------
+################################################################################
+set die_llx [lindex [lindex [ get_attribute [get_core_area] bbox] 0] 0]
+set die_lly [lindex [lindex [ get_attribute [get_core_area] bbox] 0] 1]
+set die_urx [lindex [lindex [ get_attribute [get_core_area] bbox] 1] 0]
+set die_ury [lindex [lindex [ get_attribute [get_core_area] bbox] 1] 1]
+
+for {set i "[expr $die_llx + 20]"} {$i < "[expr $die_urx - 40]"} {set i [expr $i + 80]} {
+	set_virtual_pad -net VSS -coordinate [format {%.1f %.1f} $i $die_lly]
+	set_virtual_pad -net VDD -coordinate [format {%.1f %.1f} [expr $i + 40] $die_lly]
+
+	set_virtual_pad -net VSS -coordinate [format {%.1f %.1f}  $i $die_ury]
+	set_virtual_pad -net VDD -coordinate [format {%.1f %.1f} [expr $i + 40] $die_ury]
+}
+for {set i "[expr $die_lly + 20]"} {$i < "[expr $die_ury - 40]"} {set i [expr $i + 80]} {
+	set_virtual_pad -net VSS -coordinate [format {%.1f %.1f} $die_llx $i]
+	set_virtual_pad -net VDD -coordinate [format {%.1f %.1f} $die_llx [expr $i + 40]]
+
+	set_virtual_pad -net VSS -coordinate [format {%.1f %.1f} $die_urx $i]
+	set_virtual_pad -net VDD -coordinate [format {%.1f %.1f} $die_urx [expr $i + 40] ]
+}
+
+analyze_power_plan -power_budget 250 -voltage 1.2 -nets {VDD VSS} -use_terminals_as_pads
+
+
+save_block
+##############################################
+########### 4. Placement #####################
+##############################################
+puts "start_place"
+copy_block -from_block power_plan_1.design -to placement.design
+current_block placement.design
+
+set_app_options -name time.disable_recovery_removal_checks -value false
+set_app_options -name time.disable_case_analysis -value false
+set_app_options -name place.coarse.continue_on_missing_scandef -value true
+set_app_options -name opt.common.user_instance_name_prefix -value place
+
+set_app_options -list {time.delay_calculation_style auto}
+set_voltage 0.95
+place_opt
+legalize_placement
+check_legality -verbos
+
+report_qor > ./report/placement/qor.rpt
+report_utilization > ./report/placement/utilization.rpt
+
+save_block
+
+##############################################
+########### 5. CTS       #####################
+##############################################
+copy_block -from_block placement.design -to cts.design
+current_block cts.design
+
+puts "start_cts"
+
+## CHECKS
+#########
+report_qor -summary
+report_clocks
+report_clocks -skew
+report_clocks -groups
+
+####################################
+## Clock Tree Targets
+
+set_clock_tree_options -target_skew 0.5  -clock [get_clocks *]
+set_clock_tree_options -target_latency 0.1  -clock [get_clocks *]
+
+report_clock_tree_options
+
+####################################
+## CTS Cell Selection
+
+derive_clock_cell_references -output cts_leq_set.tcl > /dev/null
+
+set CTS_CELLS [get_lib_cells */CLKBUF*]
+set_dont_touch $CTS_CELLS false
+set_lib_cell_purpose -exclude cts [get_lib_cells] 
+set_lib_cell_purpose -include cts $CTS_CELLS
+
+report_lib_cells -objects [get_lib_cells] -columns {name:20 valid_purposes dont_touch}
+
+## CTS NDRs
+####################################
+set CTS_NDR_MIN_ROUTING_LAYER	"metal4"
+set CTS_NDR_MAX_ROUTING_LAYER	"metal5"
+set CTS_LEAF_NDR_MIN_ROUTING_LAYER	"metal1"
+set CTS_LEAF_NDR_MAX_ROUTING_LAYER	"metal5"
+set CTS_NDR_RULE_NAME 		"cts_w2_s2_vlg"
+set CTS_LEAF_NDR_RULE_NAME	"cts_w1_s2"
+
+create_routing_rule $CTS_NDR_RULE_NAME\
+		-default_reference_rule \
+		-taper_distance 0.4 \
+		-driver_taper_distance 0.4 \
+  	 	-widths   {metal3 0.14 metal4 0.28 metal5 0.28} \
+  	 	-spacings {metal3 0.14 metal4 0.28 metal5 0.28}
+
+set_clock_routing_rules -rules $CTS_NDR_RULE_NAME \
+		-min_routing_layer $CTS_NDR_MIN_ROUTING_LAYER \
+		-max_routing_layer $CTS_NDR_MAX_ROUTING_LAYER
+		
+report_routing_rules -verbose
+
+report_clock_routing_rules
+
+## Timing and DRC Setup
+####################################
+
+#      Ensure that driving cells are specified on all clock ports
+report_ports -verbose [get_ports *clk*]
+set_driving_cell -scenarios [all_scenarios] -lib_cell CLKBUF_X3 [get_ports *clk*]
+
+report_ports -verbose [get_ports *clk*]
+
+report_clocks -skew
+#      Change the uncertainty for all clocks in all scenarios
+foreach_in_collection scen [all_scenarios] {
+  current_scenario $scen
+  set_clock_uncertainty 0.1 -setup [all_clocks]
+  set_clock_uncertainty 0.05 -hold [all_clocks]
+}
+
+set_app_options -name time.remove_clock_reconvergence_pessimism -value true
+
+report_clock_settings
+
+set_app_options -name clock_opt.flow.enable_ccd -value false
+clock_opt
+
+report_qor -summary
+
+report_timing
+
+puts "finish_cts"
+save_block
+
+##############################################
+########### 6. Routing   #####################
+##############################################
+copy_block -from_block cts.design -to route.design
+current_block route.design
+puts "start_route"
+
+# Design should have been loaded using load.tcl
+
+report_qor -summary
+
+
+#      check for any issues that might cause problems during routing
+#      the app option allows for more detailed reporting
+set_app_options -name route.common.verbose_level -value 1
+check_design -checks pre_route_stage
+set_app_options -name route.common.verbose_level -value 0
+
+report_ignored_layers
+update_timing
+
+connect_pg_net -net $NDM_POWER_NET [get_pins -hierarchical "*/VDD"]
+connect_pg_net -net $NDM_GROUND_NET [get_pins -hierarchical "*/VSS"]
+connect_pg_net -net $NDM_POWER_NET [get_ports -physical_context "*/VDD"]
+connect_pg_net -net $NDM_GROUND_NET [get_ports -physical_context "*/VSS"]
+
+#      Set application options for the specific routers
+set_app_options -name route.global.timing_driven    -value true
+set_app_options -name route.global.crosstalk_driven -value false
+set_app_options -name route.track.timing_driven     -value true
+set_app_options -name route.track.crosstalk_driven  -value true
+set_app_options -name route.detail.timing_driven    -value true
+set_app_options -name route.detail.force_max_number_iterations -value false
+
+## Routing
+####################################
+route_auto
+
+check_routes
+
+route_opt
+report_qor -summary
+
+
+puts "finish_route"
+save_block
+##############################################
+########### 7. Finishing #####################
+##############################################
+copy_block -from_block route.design -to finish.design
+current_block finish.design
+puts "start_finish"
+
+##create_stdcell_fillers -lib_cells {*decap_?}
+##connect_pg_net -automatic
+##remove_stdcell_fillers_with_violation
+create_stdcell_fillers -lib_cells {FILLCELL*}
+connect_pg_net -automatic
+remove_stdcell_fillers_with_violation
+check_legality
+check_lvs
+puts "finish_finish"
+save_block
+
+##############################################
+########### 8. Checks and Outputs ############
+##############################################
+
+write_verilog -include {pg_netlist unconnected_ports} ${DESIGN_NAME }.pg.v
+
+write_verilog -exclude {physical_only_cells} -top_module_first ${DESIGN_NAME}.v
+
+write_verilog -include "scalar_wire_declarations diode_cells spare_cells" ${DESIGN_NAME}.lvs.v
+
+write_verilog -include {pg_netlist} ${DESIGN_NAME}_for_pt_v.v
+
+######## SDC_OUT
+write_sdc -output ${DESIGN_NAME}.out.sdc
+######## SDC_OUT for primetime
+write_sdc -output ${DESIGN_NAME}.pt.sdc.tcl -exclude {ideal_network pvt timing_derate} 
+write_sdc -output ${DESIGN_NAME}.pt_clock_latency.sdc.tcl -include {clock_latency}
+####### SPEF_OUT
+report_timing -crosstalk_delta
+write_parasitics -format SPEF -output ${DESIGN_NAME}.out.spef
+######DEF_OUT
+write_def ${DESIGN_NAME}.out.def
+##########GDS_OUT
+write_gds \
+-view design \
+-lib_cell_view frame \
+-output_pin all \
+-fill include \
+-exclude_empty_block \
+-long_names \
+-layer_map "$GDS_MAP_FILE" \
+-keep_data_type \
+-merge_files "$STD_CELL_GDS"\
+./output/${DESIGN_NAME}.gds
+
+
+
+save_block
+save_lib
+exit
+close_block

abdelazeem201_ASIC-Design-Roadmap/IC Compiler II/Vpad.tcl

@@ -0,0 +1,21 @@
+set die_llx [lindex [lindex [ get_attribute [get_core_area] bbox] 0] 0]
+set die_lly [lindex [lindex [ get_attribute [get_core_area] bbox] 0] 1]
+set die_urx [lindex [lindex [ get_attribute [get_core_area] bbox] 1] 0]
+set die_ury [lindex [lindex [ get_attribute [get_core_area] bbox] 1] 1]
+
+for {set i "[expr $die_llx + 20]"} {$i < "[expr $die_urx - 40]"} {set i [expr $i + 80]} {
+	set_virtual_pad -net VSS -coordinate [format {%.1f %.1f} $i $die_lly]
+	set_virtual_pad -net VDD -coordinate [format {%.1f %.1f} [expr $i + 40] $die_lly]
+
+	set_virtual_pad -net VSS -coordinate [format {%.1f %.1f}  $i $die_ury]
+	set_virtual_pad -net VDD -coordinate [format {%.1f %.1f} [expr $i + 40] $die_ury]
+}
+for {set i "[expr $die_lly + 20]"} {$i < "[expr $die_ury - 40]"} {set i [expr $i + 80]} {
+	set_virtual_pad -net VSS -coordinate [format {%.1f %.1f} $die_llx $i]
+	set_virtual_pad -net VDD -coordinate [format {%.1f %.1f} $die_llx [expr $i + 40]]
+
+	set_virtual_pad -net VSS -coordinate [format {%.1f %.1f} $die_urx $i]
+	set_virtual_pad -net VDD -coordinate [format {%.1f %.1f} $die_urx [expr $i + 40] ]
+}
+
+analyze_power_plan -power_budget 250 -voltage 1.2 -nets {VDD VSS} -use_terminals_as_pads

abdelazeem201_ASIC-Design-Roadmap/IC Compiler/01_design_planning.tcl

@@ -0,0 +1,126 @@
+# 01_design_planning.tcl
+set CHIP_LIB "CHIP_LIB"
+set TOP      "CHIP"
+set CREATE_CELL_FILE "../script/create_phy_cell.tcl"
+set TDF_FILE "../design_data/io.tdf"
+set POWER  "VDD"
+set GROUND "VSS"
+#======================================================================
+# Open Design
+#======================================================================
+#open_mw_lib $CHIP_LIB
+#open_mw_cel $TOP
+#======================================================================
+# Before reading io_constraints(*.TDF), you must create cell
+# Create I/O Cells======================================================================
+source $CREATE_CELL_FILE
+#======================================================================
+# Read a IO Constraint file
+#======================================================================
+set IO_SPACE 8.5 ; # 5~10
+read_pin_pad_physical_constraints $TDF_FILE
+#======================================================================
+# Initialize the Floorplan
+#======================================================================
+set CORE_PAD_SPACE 90 ;
+create_floorplan -core_aspect_ratio 1 -core_utilization 0.6 -flip_first_row -left_io2core $CORE_PAD_SPACE -right_io2core $CORE_PAD_SPACE -bottom_io2core $CORE_PAD_SPACE -top_io2core $CORE_PAD_SPACE
+#=====================================================================
+# Insert PAD Filler
+#=====================================================================
+insert_pad_filler -cell {PFILLER20 PFILLER10 PFILLER5 PFILLER1 PFILLER05 PFILLER0005} -overlap_cell {PFILLER0005} ; # overlap_cell means smallest filler cell
+#=====================================================================
+# Save Design
+#=====================================================================
+save_mw_cel $TOP
+save_mw_cel -as "init_floor_plan"
+#=====================================================================
+# Set Macro Placement Constraints
+# - Memory margin constraints
+#======================================================================
+#set_keepout_margin -all_macros -type hard -outer {20 20 20 20}
+#======================================================================
+# Set Routing Blockage
+#=====================================================================
+#create_route_guide -no_signal_layer {METAL5 METAL6} -coordinate {{20 20} {75 95}}
+#=====================================================================
+# Place Standard and Macro Cells
+# 1st Compile
+#=====================================================================
+set_host_options -max_cores 4
+create_fp_placement -timing_driven -effort high -num_cpus 4
+#set_dont_touch_placement [all_macro_cells]
+#=====================================================================
+# Connect P/G Nets
+#=====================================================================
+derive_pg_connection -power_net $POWER -ground_net $GROUND -power_pin $POWER -ground_pin $GROUND
+#=====================================================================
+# Set Power Network Constraints
+# set_fp_rail_constraints  # set rail synthesis constraints
+#       -add_layer             (add layer constraints) (strap)
+#       -set_ring              (set ring constraints)
+#       -set_global            (set global constraints)
+#======================================================================
+set H_LAYER M6
+set V_LAYER M5
+set STRAP_WIDTH 4
+ 
+set_fp_rail_constraints -add_layer -layer $H_LAYER \
+    -direction horizontal \
+    -max_strap 15 -min_strap 10 \
+    -max_width $STRAP_WIDTH -min_width $STRAP_WIDTH \
+    -spacing minimum
+ 
+set_fp_rail_constraints -add_layer -layer $V_LAYER \
+    -direction vertical \
+    -max_strap 15 -min_strap 10 \
+    -max_width $STRAP_WIDTH -min_width $STRAP_WIDTH \
+    -spacing minimum
+ 
+set_fp_rail_constraints -set_ring -nets \
+    [format  "%s %s %s %s %s %s %s %s" \
+    $POWER $GROUND $POWER $GROUND $POWER $GROUND $POWER $GROUND] \
+    -horizontal_ring_layer $H_LAYER \
+    -vertical_ring_layer $V_LAYER \
+    -ring_width 4 \
+    -ring_spacing 4 \
+    -ring_offset 4 \
+    -extend_strap core_ring
+ 
+set_fp_rail_constraints -set_global \
+    -no_routing_over_hard_macros \
+    -no_same_width_sizing \
+    -keep_ring_outside_core
+ 
+# For memory block
+#set_fp_block_ring_constraints -add -horizontal_layer H_LAYER \
+#   -horizontal_width 8 \
+#    -horizontal_offset 1 \
+#    -vertical_layer V_LAYER \
+#    -vertical_width 8 \
+#    -vertical_offset 1 \
+#    -block_type master  \
+#    -block {rom_128x12_t90} \
+#    -net  {VDD VSS}
+ 
+#======================================================================
+# Running Power Network Synthesis
+#       -voltage_supply : 1V for T90 ; 0.9V for T40
+#       -power_budget : unit:mW
+#======================================================================
+synthesize_fp_rail -nets [list $POWER $GROUND] \
+    -voltage_supply 0.9 \
+    -synthesize_power_plan \
+    -power_budget 30
+ 
+#======================================
+# Note :
+#     check IR drop map after this command
+#======================================================================
+# Commit Power Plan
+#======================================================================
+commit_fp_rail
+#======================================================================
+# Save Design
+#======================================================================
+save_mw_cel  -design [format  "%s%s" $TOP ".CEL;1"]
+save_mw_cel  -design [format  "%s%s" $TOP ".CEL;1"] -as "design_planning"

abdelazeem201_ASIC-Design-Roadmap/IC Compiler/02_preroute.tcl

@@ -0,0 +1,85 @@
+# 02_preroute.tcl
+set CHIP_LIB    "CHIP_LIB"
+set TOP         "CHIP"
+set SDC         "../design_data/CHIP.sdc"
+set RPT_PATH    "../rpt/"
+set PWR_NET_LYR [list M6 M5]
+set POWER  "VDD"
+set GROUND "VSS"
+#======================================================================
+# Connect I/O PAD to P/G Ring
+#======================================================================
+preroute_instances  -ignore_macros \
+                    -ignore_cover_cells \
+                -primary_routing_layer pin \
+                -extend_for_multiple_connections \
+                -extension_gap 16
+#======================================================================
+# Connect Block Ring to P/G Ring
+#======================================================================
+preroute_instances  -ignore_pads \
+            -ignore_cover_cells \
+            -primary_routing_layer pin
+ 
+#preroute_instances -ignore_pads -ignore_cover_cells \
+#                   -connect_instances specified \
+#                   -macros $MEM -skip_bottom_side \
+#                   -extension_gap 4
+ 
+#==========================================
+# Note :
+# if you meet Double Via problem ( double via < 90% )  # File -> Task -> All Task
+# cut_row -within {{1272.140 816.060} {1400.480 842.505}}
+# cut_row -within {{1272.375 776.450} {1400.365 805.365}}
+# cut_row -within {{183.110 797.725} {310.045 823.935}}
+# cut_row -within {{181.700 756.355} {310.160 785.970}}
+# create_power_straps -direction vertical -start_at 303.00 -nets {VDD VSS}  -layer M8 -width 4
+# create_power_straps -direction vertical -start_at 1275.00 -nets {VDD VSS} -layer M8 -width 4
+#======================================================================
+# Preroute Std Cell Rail
+#======================================================================
+#set_route_zrt_common_options -freeze_layer_by_layer_name {{AP true}}   ; # don't use layer AP (metal 10) to avoid DRC violations
+preroute_standard_cells -extend_for_multiple_connections \
+                        -extension_gap 16 -connect horizontal \
+                        -remove_floating_pieces \
+                        -do_not_route_over_macros \
+                        -fill_empty_rows \
+                        -port_filter_mode off \
+                        -cell_master_filter_mode off \
+                        -cell_instance_filter_mode off \
+                        -voltage_area_filter_mode off \
+                        -route_type {P/G Std. Cell Pin Conn}
+#======================================================================
+# Create placement blockage
+#======================================================================
+#create_placement_blockage -coordinate {0.0 1.1} -name haha0 -type hadr -no_snap
+#======================================================================
+# Set PNET and Re-Compile
+#   -complete : no std cell on power net
+#   -partial : partial std cells on power net
+#======================================================================
+set_pnet_options -complete $PWR_NET_LYR
+#set_pnet_options -partial $PWR_NET_LYR
+create_fp_placement -timing_driven -congestion_driven -incremental all
+derive_pg_connection -power_net $POWER -ground_net $GROUND -power_pin $POWER -ground_pin $GROUND
+add_tap_cell_array -master_cell_name {FILLTIE4_A9TR} -distance 20 -no_tap_cell_under_layers {M1 M2} ; # insert well tap for TN40G
+#=====================================================================
+# Check clock constraints before CTS
+#=====================================================================
+read_sdc -echo -version Latest $SDC
+report_clock > [format "%s%s%s" $RPT_PATH $TOP "_plan_clk.rpt"]
+report_clock -skew > [format "%s%s%s" $RPT_PATH $TOP "_plan_clk_skew.rpt"]
+#=====================================================================
+# Check timing: if(slack is large)  modify design planning
+#                 else keep going
+#=====================================================================
+set_zero_interconnect_delay_mode true
+report_timing > [format "%s%s%s" $RPT_PATH $TOP "_plan_timing.rpt" ]
+#set_ideal_network [get_ports se]
+report_constraint -all > [format "%s%s%s" $RPT_PATH $TOP "_plan_clk_con.rpt" ]
+set_zero_interconnect_delay_mode false
+#=====================================================================
+# Save Design
+#=====================================================================
+save_mw_cel -design [format "%s%s" $TOP ".CEL;1"]
+save_mw_cel -design [format "%s%s" $TOP ".CEL;1"] -as "preroute"

abdelazeem201_ASIC-Design-Roadmap/IC Compiler/create_phy_cell.tcl

@@ -0,0 +1,20 @@
+# create_phy_cell.tcl
+set CORE_POWER_LIST  [list core_vdd1 core_vdd2 core_vdd3 core_vdd4]
+set CORE_GROUND_LIST [list core_vss1 core_vss2 core_vss3 core_vss4]
+set PAD_POWER_LIST   [list io_vdd01 io_vdd02 io_vdd03 io_vdd04 io_vdd05 \
+io_vdd06 io_vdd07 io_vdd08 io_vdd09 io_vdd10 \
+io_vdd11 io_vdd12 io_vdd13 io_vdd14 io_vdd15 \
+io_vdd16 io_vdd17 io_vdd18 io_vdd19 ]
+set PAD_GROUND_LIST  [list io_vss01 io_vss02 io_vss03 io_vss04 io_vss05 \
+io_vss06 io_vss07 io_vss08 io_vss09 io_vss10 \
+io_vss11 io_vss12 io_vss13 io_vss14 io_vss15 \
+io_vss16 io_vss17 io_vss18 io_vss19 io_vss20 ]
+set CORNER_LIST      [list cornerUL cornerUR cornerLR cornerLL]
+set POC_LIST         [list io_vdd20]
+ 
+create_cell $CORE_POWER_LIST  PVDD1DGZ
+create_cell $CORE_GROUND_LIST PVSS1DGZ
+create_cell $PAD_POWER_LIST   PVDD2DGZ
+create_cell $PAD_GROUND_LIST  PVSS2DGZ
+create_cell $CORNER_LIST      PCORNER
+create_cell $POC_LIST         PVDD2POC

abdelazeem201_ASIC-Design-Roadmap/IC Compiler/io.tdf

@@ -0,0 +1,140 @@
+# io.tdf
+set_pad_physical_constraints -side 1 -pad_name cornerUL
+set_pad_physical_constraints -side 2 -pad_name cornerUR
+set_pad_physical_constraints -side 3 -pad_name cornerLR
+set_pad_physical_constraints -side 4 -pad_name cornerLL
+ 
+# io_vdd20 is Power-on Control Power Pad for I/O Power Supply ( PVDD2POC )
+# set IO_SPACE 8.5 ; # suggest 5~10
+ 
+set_pad_physical_constraints -side 1 -pad_name io_vdd20         -order 1      -min_left_iospace $IO_SPACE -min_right_iospace $IO_SPACE
+set_pad_physical_constraints -side 1 -pad_name ipad_F_opt_Im_12 -order 2      -min_left_iospace $IO_SPACE -min_right_iospace $IO_SPACE
+set_pad_physical_constraints -side 1 -pad_name ipad_F_opt_Im_11 -order 3      -min_left_iospace $IO_SPACE -min_right_iospace $IO_SPACE
+set_pad_physical_constraints -side 1 -pad_name ipad_F_opt_Im_10 -order 4      -min_left_iospace $IO_SPACE -min_right_iospace $IO_SPACE
+set_pad_physical_constraints -side 1 -pad_name ipad_F_opt_Im_9  -order 5      -min_left_iospace $IO_SPACE -min_right_iospace $IO_SPACE
+set_pad_physical_constraints -side 1 -pad_name ipad_F_opt_Im_8  -order 6      -min_left_iospace $IO_SPACE -min_right_iospace $IO_SPACE
+set_pad_physical_constraints -side 1 -pad_name io_vss20         -order 7      -min_left_iospace $IO_SPACE -min_right_iospace $IO_SPACE
+set_pad_physical_constraints -side 1 -pad_name ipad_F_opt_Im_7  -order 8      -min_left_iospace $IO_SPACE -min_right_iospace $IO_SPACE
+set_pad_physical_constraints -side 1 -pad_name ipad_F_opt_Im_6  -order 9      -min_left_iospace $IO_SPACE -min_right_iospace $IO_SPACE
+set_pad_physical_constraints -side 1 -pad_name ipad_F_opt_Im_5  -order 10     -min_left_iospace $IO_SPACE -min_right_iospace $IO_SPACE
+set_pad_physical_constraints -side 1 -pad_name ipad_F_opt_Im_4  -order 11     -min_left_iospace $IO_SPACE -min_right_iospace $IO_SPACE
+set_pad_physical_constraints -side 1 -pad_name ipad_F_opt_Im_2  -order 12     -min_left_iospace $IO_SPACE -min_right_iospace $IO_SPACE
+set_pad_physical_constraints -side 1 -pad_name ipad_F_opt_Im_3  -order 13     -min_left_iospace $IO_SPACE -min_right_iospace $IO_SPACE
+set_pad_physical_constraints -side 1 -pad_name io_vdd19         -order 14     -min_left_iospace $IO_SPACE -min_right_iospace $IO_SPACE
+set_pad_physical_constraints -side 1 -pad_name core_vdd1        -order 15     -min_left_iospace $IO_SPACE -min_right_iospace $IO_SPACE
+set_pad_physical_constraints -side 1 -pad_name core_vss1        -order 16     -min_left_iospace $IO_SPACE -min_right_iospace $IO_SPACE
+set_pad_physical_constraints -side 1 -pad_name ipad_F_opt_Im_1  -order 17     -min_left_iospace $IO_SPACE -min_right_iospace $IO_SPACE
+set_pad_physical_constraints -side 1 -pad_name io_vss19         -order 18     -min_left_iospace $IO_SPACE -min_right_iospace $IO_SPACE
+set_pad_physical_constraints -side 1 -pad_name ipad_F_opt_Im_0  -order 19     -min_left_iospace $IO_SPACE -min_right_iospace $IO_SPACE
+set_pad_physical_constraints -side 1 -pad_name ipad_F_opt_Re_12 -order 20     -min_left_iospace $IO_SPACE -min_right_iospace $IO_SPACE
+set_pad_physical_constraints -side 1 -pad_name ipad_F_opt_Re_11 -order 21     -min_left_iospace $IO_SPACE -min_right_iospace $IO_SPACE
+set_pad_physical_constraints -side 1 -pad_name ipad_F_opt_Re_10 -order 22     -min_left_iospace $IO_SPACE -min_right_iospace $IO_SPACE
+set_pad_physical_constraints -side 1 -pad_name ipad_F_opt_Re_9  -order 23     -min_left_iospace $IO_SPACE -min_right_iospace $IO_SPACE
+set_pad_physical_constraints -side 1 -pad_name io_vdd18         -order 24     -min_left_iospace $IO_SPACE -min_right_iospace $IO_SPACE
+set_pad_physical_constraints -side 1 -pad_name ipad_F_opt_Re_8  -order 25     -min_left_iospace $IO_SPACE -min_right_iospace $IO_SPACE
+set_pad_physical_constraints -side 1 -pad_name ipad_F_opt_Re_7  -order 26     -min_left_iospace $IO_SPACE -min_right_iospace $IO_SPACE
+set_pad_physical_constraints -side 1 -pad_name ipad_F_opt_Re_6  -order 27     -min_left_iospace $IO_SPACE -min_right_iospace $IO_SPACE
+set_pad_physical_constraints -side 1 -pad_name ipad_F_opt_Re_5  -order 28     -min_left_iospace $IO_SPACE -min_right_iospace $IO_SPACE
+set_pad_physical_constraints -side 1 -pad_name ipad_F_opt_Re_4  -order 29     -min_left_iospace $IO_SPACE -min_right_iospace $IO_SPACE
+set_pad_physical_constraints -side 1 -pad_name io_vss18         -order 30     -min_left_iospace $IO_SPACE -min_right_iospace $IO_SPACE
+#set_pad_physical_constraints -side 1 -pad_name iopad_98        -order 31     -min_left_iospace $IO_SPACE -min_right_iospace $IO_SPACE
+#set_pad_physical_constraints -side 1 -pad_name iopad_97        -order 32     -min_left_iospace $IO_SPACE -min_right_iospace $IO_SPACE 
+ 
+set_pad_physical_constraints -side 2 -pad_name io_vdd17         -order 1      -min_left_iospace $IO_SPACE -min_right_iospace $IO_SPACE
+set_pad_physical_constraints -side 2 -pad_name ipad_F_opt_Re_3  -order 2      -min_left_iospace $IO_SPACE -min_right_iospace $IO_SPACE
+set_pad_physical_constraints -side 2 -pad_name ipad_F_opt_Re_2  -order 3      -min_left_iospace $IO_SPACE -min_right_iospace $IO_SPACE
+set_pad_physical_constraints -side 2 -pad_name ipad_F_opt_Re_1  -order 4      -min_left_iospace $IO_SPACE -min_right_iospace $IO_SPACE
+set_pad_physical_constraints -side 2 -pad_name io_vss17         -order 5      -min_left_iospace $IO_SPACE -min_right_iospace $IO_SPACE
+set_pad_physical_constraints -side 2 -pad_name ipad_F_opt_Re_0  -order 6      -min_left_iospace $IO_SPACE -min_right_iospace $IO_SPACE
+set_pad_physical_constraints -side 2 -pad_name ipad_input_Valid -order 7      -min_left_iospace $IO_SPACE -min_right_iospace $IO_SPACE
+set_pad_physical_constraints -side 2 -pad_name ipad_Ns_1        -order 8      -min_left_iospace $IO_SPACE -min_right_iospace $IO_SPACE
+set_pad_physical_constraints -side 2 -pad_name ipad_Ns_0        -order 9      -min_left_iospace $IO_SPACE -min_right_iospace $IO_SPACE
+set_pad_physical_constraints -side 2 -pad_name io_vdd16         -order 10     -min_left_iospace $IO_SPACE -min_right_iospace $IO_SPACE
+set_pad_physical_constraints -side 2 -pad_name ipad_start       -order 11     -min_left_iospace $IO_SPACE -min_right_iospace $IO_SPACE
+set_pad_physical_constraints -side 2 -pad_name ipad_clk         -order 12     -min_left_iospace $IO_SPACE -min_right_iospace $IO_SPACE
+set_pad_physical_constraints -side 2 -pad_name ipad_rst_n       -order 13     -min_left_iospace $IO_SPACE -min_right_iospace $IO_SPACE
+set_pad_physical_constraints -side 2 -pad_name io_vss16         -order 14     -min_left_iospace $IO_SPACE -min_right_iospace $IO_SPACE
+set_pad_physical_constraints -side 2 -pad_name core_vdd2        -order 15     -min_left_iospace $IO_SPACE -min_right_iospace $IO_SPACE
+set_pad_physical_constraints -side 2 -pad_name core_vss2        -order 16     -min_left_iospace $IO_SPACE -min_right_iospace $IO_SPACE
+set_pad_physical_constraints -side 2 -pad_name ipad_se          -order 17     -min_left_iospace $IO_SPACE -min_right_iospace $IO_SPACE
+set_pad_physical_constraints -side 2 -pad_name io_vdd15         -order 18     -min_left_iospace $IO_SPACE -min_right_iospace $IO_SPACE
+set_pad_physical_constraints -side 2 -pad_name opad_F_bb_12     -order 19     -min_left_iospace $IO_SPACE -min_right_iospace $IO_SPACE
+set_pad_physical_constraints -side 2 -pad_name io_vss15         -order 20     -min_left_iospace $IO_SPACE -min_right_iospace $IO_SPACE
+set_pad_physical_constraints -side 2 -pad_name opad_F_bb_11     -order 21     -min_left_iospace $IO_SPACE -min_right_iospace $IO_SPACE
+set_pad_physical_constraints -side 2 -pad_name io_vdd14         -order 22     -min_left_iospace $IO_SPACE -min_right_iospace $IO_SPACE
+set_pad_physical_constraints -side 2 -pad_name opad_F_bb_10     -order 23     -min_left_iospace $IO_SPACE -min_right_iospace $IO_SPACE
+set_pad_physical_constraints -side 2 -pad_name opad_F_bb_9      -order 24     -min_left_iospace $IO_SPACE -min_right_iospace $IO_SPACE
+set_pad_physical_constraints -side 2 -pad_name io_vss14         -order 25     -min_left_iospace $IO_SPACE -min_right_iospace $IO_SPACE
+set_pad_physical_constraints -side 2 -pad_name opad_F_bb_8      -order 26     -min_left_iospace $IO_SPACE -min_right_iospace $IO_SPACE
+set_pad_physical_constraints -side 2 -pad_name io_vdd13         -order 27     -min_left_iospace $IO_SPACE -min_right_iospace $IO_SPACE
+set_pad_physical_constraints -side 2 -pad_name opad_F_bb_7      -order 28     -min_left_iospace $IO_SPACE -min_right_iospace $IO_SPACE
+set_pad_physical_constraints -side 2 -pad_name opad_F_bb_6      -order 29     -min_left_iospace $IO_SPACE -min_right_iospace $IO_SPACE
+set_pad_physical_constraints -side 2 -pad_name io_vss13         -order 30     -min_left_iospace $IO_SPACE -min_right_iospace $IO_SPACE
+#set_pad_physical_constraints -side 2 -pad_name iopad_66        -order 31     -min_left_iospace $IO_SPACE -min_right_iospace $IO_SPACE
+#set_pad_physical_constraints -side 2 -pad_name iopad_65        -order 32     -min_left_iospace $IO_SPACE -min_right_iospace $IO_SPACE
+ 
+set_pad_physical_constraints -side 3 -pad_name io_vss07         -order 1      -min_left_iospace $IO_SPACE -min_right_iospace $IO_SPACE
+set_pad_physical_constraints -side 3 -pad_name opad_F_rf_Im_3   -order 2      -min_left_iospace $IO_SPACE -min_right_iospace $IO_SPACE
+set_pad_physical_constraints -side 3 -pad_name opad_F_rf_Im_4   -order 3      -min_left_iospace $IO_SPACE -min_right_iospace $IO_SPACE
+set_pad_physical_constraints -side 3 -pad_name io_vdd07         -order 4      -min_left_iospace $IO_SPACE -min_right_iospace $IO_SPACE
+set_pad_physical_constraints -side 3 -pad_name opad_F_rf_Im_5   -order 5      -min_left_iospace $IO_SPACE -min_right_iospace $IO_SPACE
+set_pad_physical_constraints -side 3 -pad_name io_vss08         -order 6      -min_left_iospace $IO_SPACE -min_right_iospace $IO_SPACE
+set_pad_physical_constraints -side 3 -pad_name opad_F_rf_Im_6   -order 7      -min_left_iospace $IO_SPACE -min_right_iospace $IO_SPACE
+set_pad_physical_constraints -side 3 -pad_name opad_F_rf_Im_7   -order 8      -min_left_iospace $IO_SPACE -min_right_iospace $IO_SPACE
+set_pad_physical_constraints -side 3 -pad_name io_vdd08         -order 9      -min_left_iospace $IO_SPACE -min_right_iospace $IO_SPACE
+set_pad_physical_constraints -side 3 -pad_name opad_F_rf_Im_8   -order 10     -min_left_iospace $IO_SPACE -min_right_iospace $IO_SPACE
+set_pad_physical_constraints -side 3 -pad_name opad_F_rf_Im_9   -order 11     -min_left_iospace $IO_SPACE -min_right_iospace $IO_SPACE
+set_pad_physical_constraints -side 3 -pad_name io_vss09         -order 12     -min_left_iospace $IO_SPACE -min_right_iospace $IO_SPACE
+set_pad_physical_constraints -side 3 -pad_name opad_F_rf_Im_10  -order 13     -min_left_iospace $IO_SPACE -min_right_iospace $IO_SPACE
+set_pad_physical_constraints -side 3 -pad_name opad_F_rf_Im_11  -order 14     -min_left_iospace $IO_SPACE -min_right_iospace $IO_SPACE
+set_pad_physical_constraints -side 3 -pad_name io_vdd09         -order 15     -min_left_iospace $IO_SPACE -min_right_iospace $IO_SPACE
+set_pad_physical_constraints -side 3 -pad_name core_vdd3        -order 16     -min_left_iospace $IO_SPACE -min_right_iospace $IO_SPACE
+set_pad_physical_constraints -side 3 -pad_name core_vss3        -order 17     -min_left_iospace $IO_SPACE -min_right_iospace $IO_SPACE
+set_pad_physical_constraints -side 3 -pad_name io_vss10         -order 18     -min_left_iospace $IO_SPACE -min_right_iospace $IO_SPACE
+set_pad_physical_constraints -side 3 -pad_name opad_F_rf_Im_12  -order 19     -min_left_iospace $IO_SPACE -min_right_iospace $IO_SPACE
+set_pad_physical_constraints -side 3 -pad_name io_vdd10         -order 20     -min_left_iospace $IO_SPACE -min_right_iospace $IO_SPACE
+set_pad_physical_constraints -side 3 -pad_name opad_F_bb_Valid  -order 21     -min_left_iospace $IO_SPACE -min_right_iospace $IO_SPACE
+set_pad_physical_constraints -side 3 -pad_name opad_F_bb_0      -order 22     -min_left_iospace $IO_SPACE -min_right_iospace $IO_SPACE
+set_pad_physical_constraints -side 3 -pad_name io_vss11         -order 23     -min_left_iospace $IO_SPACE -min_right_iospace $IO_SPACE
+set_pad_physical_constraints -side 3 -pad_name opad_F_bb_1      -order 24     -min_left_iospace $IO_SPACE -min_right_iospace $IO_SPACE
+set_pad_physical_constraints -side 3 -pad_name opad_F_bb_2      -order 25     -min_left_iospace $IO_SPACE -min_right_iospace $IO_SPACE
+set_pad_physical_constraints -side 3 -pad_name io_vdd11         -order 26     -min_left_iospace $IO_SPACE -min_right_iospace $IO_SPACE
+set_pad_physical_constraints -side 3 -pad_name opad_F_bb_3      -order 27     -min_left_iospace $IO_SPACE -min_right_iospace $IO_SPACE
+set_pad_physical_constraints -side 3 -pad_name opad_F_bb_4      -order 28     -min_left_iospace $IO_SPACE -min_right_iospace $IO_SPACE
+set_pad_physical_constraints -side 3 -pad_name io_vss12         -order 29     -min_left_iospace $IO_SPACE -min_right_iospace $IO_SPACE
+set_pad_physical_constraints -side 3 -pad_name opad_F_bb_5      -order 30     -min_left_iospace $IO_SPACE -min_right_iospace $IO_SPACE
+set_pad_physical_constraints -side 3 -pad_name io_vdd12         -order 31     -min_left_iospace $IO_SPACE -min_right_iospace $IO_SPACE
+#set_pad_physical_constraints -side 3 -pad_name iopad_64        -order 32     -min_left_iospace $IO_SPACE -min_right_iospace $IO_SPACE
+ 
+set_pad_physical_constraints -side 4 -pad_name io_vss01         -order 1      -min_left_iospace $IO_SPACE -min_right_iospace $IO_SPACE
+set_pad_physical_constraints -side 4 -pad_name opad_F_rf_Valid  -order 2      -min_left_iospace $IO_SPACE -min_right_iospace $IO_SPACE
+set_pad_physical_constraints -side 4 -pad_name opad_F_rf_Re_0   -order 3      -min_left_iospace $IO_SPACE -min_right_iospace $IO_SPACE
+set_pad_physical_constraints -side 4 -pad_name io_vdd01         -order 4      -min_left_iospace $IO_SPACE -min_right_iospace $IO_SPACE
+set_pad_physical_constraints -side 4 -pad_name opad_F_rf_Re_1   -order 5      -min_left_iospace $IO_SPACE -min_right_iospace $IO_SPACE
+set_pad_physical_constraints -side 4 -pad_name io_vss02         -order 6      -min_left_iospace $IO_SPACE -min_right_iospace $IO_SPACE
+set_pad_physical_constraints -side 4 -pad_name opad_F_rf_Re_2   -order 7      -min_left_iospace $IO_SPACE -min_right_iospace $IO_SPACE
+set_pad_physical_constraints -side 4 -pad_name opad_F_rf_Re_3   -order 8      -min_left_iospace $IO_SPACE -min_right_iospace $IO_SPACE
+set_pad_physical_constraints -side 4 -pad_name io_vdd02         -order 9      -min_left_iospace $IO_SPACE -min_right_iospace $IO_SPACE
+set_pad_physical_constraints -side 4 -pad_name opad_F_rf_Re_4   -order 10     -min_left_iospace $IO_SPACE -min_right_iospace $IO_SPACE
+set_pad_physical_constraints -side 4 -pad_name opad_F_rf_Re_5   -order 11     -min_left_iospace $IO_SPACE -min_right_iospace $IO_SPACE
+set_pad_physical_constraints -side 4 -pad_name io_vss03         -order 12     -min_left_iospace $IO_SPACE -min_right_iospace $IO_SPACE
+set_pad_physical_constraints -side 4 -pad_name opad_F_rf_Re_6   -order 13     -min_left_iospace $IO_SPACE -min_right_iospace $IO_SPACE
+set_pad_physical_constraints -side 4 -pad_name opad_F_rf_Re_7   -order 14     -min_left_iospace $IO_SPACE -min_right_iospace $IO_SPACE
+set_pad_physical_constraints -side 4 -pad_name io_vdd03         -order 15     -min_left_iospace $IO_SPACE -min_right_iospace $IO_SPACE
+set_pad_physical_constraints -side 4 -pad_name core_vdd4        -order 16     -min_left_iospace $IO_SPACE -min_right_iospace $IO_SPACE
+set_pad_physical_constraints -side 4 -pad_name core_vss4        -order 17     -min_left_iospace $IO_SPACE -min_right_iospace $IO_SPACE
+set_pad_physical_constraints -side 4 -pad_name io_vss04         -order 18     -min_left_iospace $IO_SPACE -min_right_iospace $IO_SPACE
+set_pad_physical_constraints -side 4 -pad_name opad_F_rf_Re_8   -order 19     -min_left_iospace $IO_SPACE -min_right_iospace $IO_SPACE
+set_pad_physical_constraints -side 4 -pad_name io_vdd04         -order 20     -min_left_iospace $IO_SPACE -min_right_iospace $IO_SPACE
+set_pad_physical_constraints -side 4 -pad_name opad_F_rf_Re_9   -order 21     -min_left_iospace $IO_SPACE -min_right_iospace $IO_SPACE
+set_pad_physical_constraints -side 4 -pad_name opad_F_rf_Re_10  -order 22     -min_left_iospace $IO_SPACE -min_right_iospace $IO_SPACE
+set_pad_physical_constraints -side 4 -pad_name io_vss05         -order 23     -min_left_iospace $IO_SPACE -min_right_iospace $IO_SPACE
+set_pad_physical_constraints -side 4 -pad_name opad_F_rf_Re_11  -order 24     -min_left_iospace $IO_SPACE -min_right_iospace $IO_SPACE
+set_pad_physical_constraints -side 4 -pad_name opad_F_rf_Re_12  -order 25     -min_left_iospace $IO_SPACE -min_right_iospace $IO_SPACE
+set_pad_physical_constraints -side 4 -pad_name io_vdd05         -order 26     -min_left_iospace $IO_SPACE -min_right_iospace $IO_SPACE
+set_pad_physical_constraints -side 4 -pad_name opad_F_rf_Im_0   -order 27     -min_left_iospace $IO_SPACE -min_right_iospace $IO_SPACE
+set_pad_physical_constraints -side 4 -pad_name opad_F_rf_Im_1   -order 28     -min_left_iospace $IO_SPACE -min_right_iospace $IO_SPACE
+set_pad_physical_constraints -side 4 -pad_name io_vss06         -order 29     -min_left_iospace $IO_SPACE -min_right_iospace $IO_SPACE
+set_pad_physical_constraints -side 4 -pad_name opad_F_rf_Im_2   -order 30     -min_left_iospace $IO_SPACE -min_right_iospace $IO_SPACE
+set_pad_physical_constraints -side 4 -pad_name io_vdd06         -order 31     -min_left_iospace $IO_SPACE -min_right_iospace $IO_SPACE
+#set_pad_physical_constraints -side 4 -pad_name iopad_32        -order 32     -min_left_iospace $IO_SPACE -min_right_iospace $IO_SPACE

abdelazeem201_ASIC-Design-Roadmap/LEF2FRAM/Readme.md

@@ -0,0 +1,119 @@
+# LEF Layer to Technology File Layer Mapper
+
+This Perl script processes a technology file (.tf) and a Library Exchange Format (LEF) file to generate a mapping between the layers defined in these files.
+
+# Overview
+
+The script reads through the specified technology and LEF files, extracts layer information, and generates two output files:
+
+A log file documenting the processing steps and any issues encountered.
+A mapping file that correlates the layers in the LEF file with their corresponding layers in the technology file.
+
+# Features
+
+Automatic Layer Mapping: The script identifies and maps layers between the LEF and technology files based on predefined rules.
+Logging: Detailed logging of the processing steps, aiding in troubleshooting and validation.
+Configurable via Command Line Arguments: The input files are specified via command line arguments, allowing flexibility in usage.
+
+# Usage
+
+Command Line
+
+````````````````````````````````````````````````
+perl lef_layer_tf_number_map.pl Tech_file_name.tf Lef_file_name.lef
+````````````````````````````````````````````````
+
+* Tech_file_name.tf: The technology file containing layer definitions.
+* Lef_file_name.lef: The LEF file containing layer definitions.
+
+Output Files
+
+* Lef_file_name_lef_Tech_file_name_tf.map: A file containing the mapping between LEF layers and technology file layers.
+* Lef_file_name_lef_Tech_file_name_tf.log: A log file containing detailed logs of the processing steps.
+
+# Script Explanation
+## Argument Handling
+
+The script expects two arguments: the technology file and the LEF file. If the correct number of arguments is not provided, it displays a usage message and exits.
+
+## File Opening
+The script opens the technology file, LEF file, and two output files: one for logging and one for the mapping.
+
+## Processing the Technology File
+The script processes the technology file to extract layer information:
+
+Identifies layers, their numbers, and mask names.
+Stores the extracted information in hashes for later use.
+Processing the LEF File
+The script processes the LEF file to extract layer information and derive mask names based on the layer types:
+
+Uses predefined rules to derive mask names for various layer types.
+Maps these derived mask names to the corresponding layer numbers from the technology file.
+Generating the Mapping File
+The script generates the mapping file by printing the layer names and their corresponding numbers from both the LEF and technology files.
+
+## Logging and Helper Subroutines
+The script includes helper subroutines for logging and printing the map file.
+
+## Example
+To run the script with example files:
+``````````````````````````````````````````````
+perl lef_layer_tf_number_map.pl example_tech.tf example_lef.lef
+``````````````````````````````````````````````
+This will generate example_lef_lef_example_tech_tf.map and example_lef_lef_example_tech_tf.log.
+
+# LEF2FRAM
+
+1. **1. Preparing the Map File**
+
+Use the `lef_layer_tf_number_mapper.pl` script provided in the compressed package, and modify the first line to:
+
+``````````````````````````
+#!/usr/bin/perl -w
+``````````````````````````
+
+Change the file attributes to make it executable:
+
+``````````````````````````````````````
+chmod 755 lef_layer_tf_number_mapper.pl
+```````````````````````````````````````
+
+Prepare the technology file and the TECH LEF file. Note that the LEF file should be the process LEF file, not the LEF file generated by SRAM:
+
+* `scc013u_8lm_1tm_thick.lef
+* `smic13_hd_8lm_1tm_thick.tf
+
+Tip: From my observation, in the given SMIC13 standard cell library, the process file and TECH LEF file are the same across various cell libraries. Therefore, you can select the one under RVT. However, the process file and TECH LEF file themselves are divided into two types: with RDL and without RDL. I used the `diff` command to check and found that it seems to add an RDL layer.
+
+Place the above three files in the same directory, cd into that directory, and execute the following command:
+
+```````````````````````````````````````````````````````````````````````````````````
+./lef_layer_tf_number_mapper.pl smic13_hd_8lm_1tm_thick.tf scc013u_8lm_1tm_thick.lef
+````````````````````````````````````````````````````````````````````````````````````
+
+This will generate the map file from LEF to Milkyway.
+
+
+2. **Automatically Create LEF to Milkyway Frame View**
+
+In the current directory, create a `mw` directory and copy the `.lef`, `.tf`, and `.map` files mentioned above into this directory. Create a new `cell_lef` directory and copy the cell LEF files of the macros to be converted into this directory. Then, `cd` into the `mw` directory and open a terminal.
+
+# To start the Milkyway tool, please follow these steps:
+
+Open a terminal.
+
+Enter the full path to the Milkyway executable file. For example:
+
+
+``````````````````````````````````````````````````````````
+/eda/Synopsys/mw_2018.06/bin/linux64/Milkyway
+
+milkway
+```````````````````````````````````````````````````````````
+Replace `/eda/Synopsys/mw_2018.06/bin/linux64/Milkyway` with the actual full path to the Milkyway executable file on your system.
+
+1. Press Enter to execute the command.
+
+2. This should launch the Milkyway tool.
+
+

abdelazeem201_ASIC-Design-Roadmap/LEF2FRAM/lef_layer_tf_number_mapper.pl

@@ -0,0 +1,198 @@
+#!/depot/perl-5.003/bin/perl5.003 -w
+
+# Written by Ahmed Abdelazeem
+# March 11, 2024
+# Updated to cover more LEF cases
+# July 1, 2024
+# A Perl script processes a technology file (.tf) and an LEF (Library Exchange Format) file to generate a mapping between layers defined in these files.
+#
+#
+
+$EXPECTED_COMMAND_ARGS = 2;
+
+if ($#ARGV < $EXPECTED_COMMAND_ARGS -1 )
+        {
+        die "Usage: lef_layer_tf_number_map.pl Tech_file_name.tf Lef_file_name.lef\n";
+        }
+        else
+                {
+                $tech_file = $ARGV[0];
+                $lef_file = $ARGV[1];
+		$tmp_s1 = $ARGV[0];
+		$tmp_s1 =~ s/\.tf/_tf/;
+		$tmp_s2 = $ARGV[1];
+		$tmp_s2 =~ s/\.lef/_lef/;
+                $lef_tf_map_file = $tmp_s2."_".$tmp_s1.".map";
+                $lef_tf_log_file = $tmp_s2."_".$tmp_s1.".log";
+                }
+
+open tech_file or die "Can't open $tech_file\n";
+open lef_file or die "Can't open $lef_file\n";
+open lef_tf_log_file, ">$lef_tf_log_file" or die "Can't open $lef_tf_log_file\n";
+open lef_tf_map_file, ">$lef_tf_map_file" or die "Can't open $lef_tf_map_file\n";
+
+print_log( "\n*** Beginning to process $tech_file tech file***\n");
+$i=0;
+
+%tf_layerMaskNames = ();
+%tf_layerMaskLayerNumber = ();
+%tf_layerName = ();
+
+$processing_tf_layer = 0;
+$found_maskName = 0;
+$tf_masks = 0;
+while ($line = <tech_file>) 
+{
+	chop $line;
+	if ( $line =~ /^[lL][aA][yY][eE][rR][\s]+\"([\w\W]+)\"[\s]+\{.*$/ )
+	{
+	if ($processing_tf_layer ==0)
+		{
+		$processing_tf_layer = 1;
+		$tf_layer_name = $1;
+		print_log( "\nBeginning to process $tf_layer_name layer...\n");
+		}
+	}	
+	elsif ( $line =~ /^[\s]*\}.*$/) 
+		{
+		if ($processing_tf_layer ==1) 
+			{
+			if ($found_maskName == 1)
+				{
+				$tf_layerMaskNames{$tf_masks} = $tf_maskName;
+				$tf_layerMaskLayerNumber{$tf_maskName} = $tf_layerNumber;
+				$tf_layerName{$tf_maskName} = $tf_layer_name;
+
+				$tf_masks++;
+				$found_maskName =0;
+				}
+			print_log( "Completed the processing of $tf_layer_name layer.\n");
+			$processing_tf_layer = 0;
+			}
+		}
+	elsif ( $line =~ /^[\s]*layerNumber[\s]*\=[\s]*([\d]+).*$/) 
+		{
+		$tf_layerNumber = $1;
+		print_log( "Found the layerNumber $tf_layerNumber for the $tf_layer_name!\n");
+		}
+	elsif ( $line =~ /^[\s]*maskName[\s]*\=[\s]*\"([\w]+)\".*$/) 
+		{
+		$tf_maskName = $1;
+		$found_maskName = 1;
+		print_log( "Found the maskName $tf_maskName for the $tf_layer_name!\n");
+		}
+$i++;
+}
+
+#foreach $key (keys %tf_layerMaskNames)
+#	{
+#	print "tf_layerName=$tf_layerName{$tf_layerMaskNames{$key}}		";
+#	print "tf_mask_layerName=$tf_layerMaskNames{$key}		";
+#	print "tf_mask_layerNumber=$tf_layerMaskLayerNumber{$tf_layerMaskNames{$key}}\n";
+#	}
+
+print_log( "\n*** Beginning to process $lef_file LEF file***\n");
+
+%lef_layerDerivedMaskNames = ();
+%lef_layerDerivedMaskLayerNumber = ();
+%lef_layerName = ();
+
+$i=0;
+$lef_masks = 0;
+$processing_lef_layer = 0;
+$lef_prev_layerTYPE = "";
+$metal_index = 0;
+while ($line = <lef_file>) 
+{
+	chop $line;
+#	print "$line\n";
+#	print "$i th line:$line\n";      
+	if ( $line =~ /^LAYER[\s]+([\w]+)[\s]*$/ )
+	{
+	if ($processing_lef_layer ==0)
+		{
+		$processing_lef_layer = 1;
+		$lef_layer_name = $1;
+		print_log( "\nBeginning to process $lef_layer_name layer...\n");
+		}
+	}	
+	elsif ( $line =~ /^END[\s]+[\w]+[\s]*$/) 
+		{
+		if ($processing_lef_layer ==1) 
+			{
+			$lef_derivedmaskName = "";
+			if ( ($lef_layerTYPE eq "MASTERSLICE") && ($lef_masks == 0) )
+				{
+				$lef_derivedmaskName = "poly";
+				}
+			elsif ( ($lef_layerTYPE eq "CUT") && ($lef_prev_layerTYPE eq "MASTERSLICE") )
+				{
+				$lef_derivedmaskName = "polyCont";
+				}
+			elsif ( ($lef_layerTYPE eq "ROUTING") )
+				{
+				if ( $metal_index == 0) { $metal_index = 1; }
+				else { $metal_index++; }
+				$lef_derivedmaskName = "metal".$metal_index;
+				}
+			elsif ( ($lef_layerTYPE eq "CUT") && ($lef_prev_layerTYPE ne "MASTERSLICE"))
+				{
+#				print "lef_layerTYPE=$lef_layerTYPE;lef_masks=$lef_masks;lef_prev_layerTYPE=$lef_prev_layerTYPE\n";
+				$lef_derivedmaskName = "via".$metal_index;
+				}
+			elsif ( ($lef_layerTYPE eq "OVERLAP") )
+				{
+				print_log( "Skipping the OVERLAP Layer...\n");
+				}
+			else    { 
+#				print "lef_layerTYPE=$lef_layerTYPE;lef_masks=$lef_masks;lef_prev_layerTYPE=$lef_prev_layerTYPE\n";
+				die "Can not process due to issue...\n";
+				}
+
+			if ($lef_derivedmaskName ne "" )
+				{
+				$lef_derivedlayerNumber = $tf_layerMaskLayerNumber{$lef_derivedmaskName};
+
+				$lef_layerDerivedMaskNames{$lef_masks} = $lef_derivedmaskName;
+				$lef_layerDerivedMaskLayerNumber{$lef_derivedmaskName} = $lef_derivedlayerNumber;
+				$lef_layerName{$lef_derivedmaskName} = $lef_layer_name;
+				$lef_masks++;
+				}
+			print_log( "Completed the processing of $lef_layer_name layer.\n");
+			$processing_lef_layer = 0;
+			$lef_prev_layerTYPE = $lef_layerTYPE;
+			}
+		}
+	elsif ( $line =~ /^[\s]*TYPE[\s]+([\w]+)[\s]*\;.*$/) 
+		{
+		$lef_layerTYPE = $1;
+		print_log( "Found the TYPE $lef_layerTYPE for the $lef_layer_name!\n");
+		}
+$i++;
+}
+
+#foreach $key (keys %lef_layerDerivedMaskNames)
+#	{
+#	print "lef_layerName=$lef_layerName{$lef_layerDerivedMaskNames{$key}}		";
+#	print "lef_mask_layerName=$lef_layerDerivedMaskNames{$key}		";
+#	print "lef_mask_layerNumber=$lef_layerDerivedMaskLayerNumber{$lef_layerDerivedMaskNames{$key}}\n";
+#	}
+
+print_log( "\n*** Printing the map file between $lef_file and $tech_file ***\n");
+for ($j=0; $j < $lef_masks; $j++)
+	{
+	print_map("$lef_layerName{$lef_layerDerivedMaskNames{$j}}");
+	print_map(" $lef_layerDerivedMaskLayerNumber{$lef_layerDerivedMaskNames{$j}}\n");
+	}
+
+close lef_tf_map_file;
+
+sub print_log {
+	print "$_[0]";
+	print lef_tf_log_file "$_[0]";
+}
+
+sub print_map {
+	print "$_[0]";
+	print lef_tf_map_file "$_[0]";
+}

abdelazeem201_ASIC-Design-Roadmap/LEF2FRAM/lef_layer_tf_number_mapper.tcl

@@ -0,0 +1,185 @@
+#!/usr/bin/env wish
+
+# Written by Ahmed Abdelazeem
+# March 11, 2024
+# Updated to cover more LEF cases
+# July 1, 2024
+# A TCL script processes a technology file (.tf) and an LEF (Library Exchange Format) file to generate a mapping between layers defined in these files.
+
+set EXPECTED_COMMAND_ARGS 2
+
+if {[llength $argv] < $EXPECTED_COMMAND_ARGS} {
+    puts "Usage: lef_layer_tf_number_map.tcl Tech_file_name.tf Lef_file_name.lef"
+    exit 1
+} else {
+    set tech_file [lindex $argv 0]
+    set lef_file [lindex $argv 1]
+    set tmp_s1 [regsub {.tf} $tech_file {_tf}]
+    set tmp_s2 [regsub {.lef} $lef_file {_lef}]
+    set lef_tf_map_file "${tmp_s2}_${tmp_s1}.map"
+    set lef_tf_log_file "${tmp_s2}_${tmp_s1}.log"
+}
+
+set tech_file_id [open $tech_file r]
+if {$tech_file_id == ""} {
+    puts "Can't open $tech_file"
+    exit 1
+}
+
+set lef_file_id [open $lef_file r]
+if {$lef_file_id == ""} {
+    puts "Can't open $lef_file"
+    exit 1
+}
+
+set lef_tf_log_file_id [open $lef_tf_log_file w]
+if {$lef_tf_log_file_id == ""} {
+    puts "Can't open $lef_tf_log_file"
+    exit 1
+}
+
+set lef_tf_map_file_id [open $lef_tf_map_file w]
+if {$lef_tf_map_file_id == ""} {
+    puts "Can't open $lef_tf_map_file"
+    exit 1
+}
+
+proc print_log {message} {
+    puts $message
+    puts $::lef_tf_log_file_id $message
+}
+
+proc print_map {message} {
+    puts $message
+    puts $::lef_tf_map_file_id $message
+}
+
+print_log "\n*** Beginning to process $tech_file tech file***\n"
+
+set i 0
+array set tf_layerMaskNames {}
+array set tf_layerMaskLayerNumber {}
+array set tf_layerName {}
+
+set processing_tf_layer 0
+set found_maskName 0
+set tf_masks 0
+
+while {[gets $tech_file_id line] != -1} {
+    regsub -all {[\[\]]} $line {} line
+    regsub -all {\{\}} $line {} line
+    regsub -all {\[\]} $line {} line
+    regsub -all {\{\}} $line {} line
+    regsub -all {"} $line {} line
+    regsub -all {;} $line {} line
+    regsub -all {\;} $line {} line
+    regsub -all {[()]}} $line {} line
+
+    if {[regexp {^[lL][aA][yY][eE][rR][\s]+\"([\w\W]+)\"[\s]+\{.*$} $line match tf_layer_name]} {
+        if {$processing_tf_layer == 0} {
+            set processing_tf_layer 1
+            print_log "\nBeginning to process $tf_layer_name layer...\n"
+        }
+    } elseif {[regexp {^[\s]*\}.*$} $line]} {
+        if {$processing_tf_layer == 1} {
+            if {$found_maskName == 1} {
+                set tf_layerMaskNames($tf_masks) $tf_maskName
+                set tf_layerMaskLayerNumber($tf_maskName) $tf_layerNumber
+                set tf_layerName($tf_maskName) $tf_layer_name
+
+                incr tf_masks
+                set found_maskName 0
+            }
+            print_log "Completed the processing of $tf_layer_name layer.\n"
+            set processing_tf_layer 0
+        }
+    } elseif {[regexp {^[\s]*layerNumber[\s]*\=[\s]*([\d]+).*} $line match tf_layerNumber]} {
+        set tf_layerNumber [lindex $match 1]
+        print_log "Found the layerNumber $tf_layerNumber for the $tf_layer_name!\n"
+    } elseif {[regexp {^[\s]*maskName[\s]*\=[\s]*\"([\w]+)\".*} $line match tf_maskName]} {
+        set tf_maskName [lindex $match 1]
+        set found_maskName 1
+        print_log "Found the maskName $tf_maskName for the $tf_layer_name!\n"
+    }
+    incr i
+}
+
+print_log "\n*** Beginning to process $lef_file LEF file***\n"
+
+set lef_masks 0
+set processing_lef_layer 0
+set lef_prev_layerTYPE ""
+set metal_index 0
+
+while {[gets $lef_file_id line] != -1} {
+    regsub -all {[\[\]]} $line {} line
+    regsub -all {\{\}} $line {} line
+    regsub -all {\[\]} $line {} line
+    regsub -all {\{\}} $line {} line
+    regsub -all {"} $line {} line
+    regsub -all {;} $line {} line
+    regsub -all {\;} $line {} line
+    regsub -all {[()]}} $line {} line
+
+    if {[regexp {^LAYER[\s]+([\w]+)[\s]*$} $line match lef_layer_name]} {
+        if {$processing_lef_layer == 0} {
+            set processing_lef_layer 1
+            print_log "\nBeginning to process $lef_layer_name layer...\n"
+        }
+    } elseif {[regexp {^END[\s]+[\w]+[\s]*$} $line]} {
+        if {$processing_lef_layer == 1} {
+            set lef_derivedmaskName ""
+            if {($lef_layerTYPE eq "MASTERSLICE") && ($lef_masks == 0)} {
+                set lef_derivedmaskName "poly"
+            } elseif {($lef_layerTYPE eq "CUT") && ($lef_prev_layerTYPE eq "MASTERSLICE")} {
+                set lef_derivedmaskName "polyCont"
+            } elseif {($lef_layerTYPE eq "ROUTING")} {
+                if {$metal_index == 0} {incr metal_index}
+                else {incr metal_index}
+                set lef_derivedmaskName "metal$metal_index"
+            } elseif {($lef_layerTYPE eq "CUT") && ($lef_prev_layerTYPE ne "MASTERSLICE")} {
+                set lef_derivedmaskName "via$metal_index"
+            } elseif {($lef_layerTYPE eq "OVERLAP")} {
+                print_log "Skipping the OVERLAP Layer...\n"
+            } else {
+                print_log "Can not process due to issue...\n"
+                exit 1
+            }
+
+            if {$lef_derivedmaskName ne ""} {
+                set lef_derivedlayerNumber $tf_layerMaskLayerNumber($lef_derivedmaskName)
+
+                set lef_layerDerivedMaskNames($lef_masks) $lef_derivedmaskName
+                set lef_layerDerivedMaskNames($lef_masks) $lef_derivedmaskName
+                set lef_layerDerivedMaskLayerNumber($lef_derivedmaskName) $lef_derivedlayerNumber
+                set lef_layerName($lef_derivedmaskName) $lef_layer_name
+                incr lef_masks
+            }
+            print_log "Completed the processing of $lef_layer_name layer.\n"
+            set processing_lef_layer 0
+            set lef_prev_layerTYPE $lef_layerTYPE
+        }
+    } elseif {[regexp {^[\s]*TYPE[\s]+([\w]+)[\s]*\;.*$} $line match lef_layerTYPE]} {
+        set lef_layerTYPE [lindex $match 1]
+        print_log "Found the TYPE $lef_layerTYPE for the $lef_layer_name!\n"
+    }
+    incr i
+}
+
+print_log "\n*** Printing the map file between $lef_file and $tech_file ***\n"
+for {set j 0} {$j < $lef_masks} {incr j} {
+    print_map "$lef_layerName($lef_layerDerivedMaskNames($j))"
+    print_map " $lef_layerDerivedMaskLayerNumber($lef_layerDerivedMaskNames($j))\n"
+}
+
+close $lef_tf_map_file_id
+
+proc print_log {message} {
+    puts $message
+    puts $::lef_tf_log_file_id $message
+}
+
+proc print_map {message} {
+    puts $message
+    puts $::lef_tf_map_file_id $message
+}

abdelazeem201_ASIC-Design-Roadmap/LICENSE

@@ -0,0 +1,21 @@
+MIT License
+
+Copyright (c) 2021 Ahmed Abdelazeem
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.

abdelazeem201_ASIC-Design-Roadmap/Logo.pl

@@ -0,0 +1,87 @@
+/*
+
+*/
+
+let((win cv bmpfile bmpSize WORD Wnum number Grid Layer row column max_column
+	i dot x y signature offset width height pixel ImageSize )
+
+	win = hiGetCurrentWindow()
+	cv = getEditRep(win)
+
+	bmpfile = "/home/abdelazeem/project_map/proj_lyra/lyra_logo/907.bmp" ;;; Input BMP File
+	Layer = list("M3" "drawing")	;;; Output Layer
+	Grid = 0.3				;;; Rectangle Size
+	column = 0
+
+procedure(MessageForm(text)
+    prog( ()
+	hiDisplayAppDBox(
+		?name 'JWDBox_Message
+		?dboxBanner "Message!!"
+		?buttonLayout 'Close
+		?dboxText text
+	)
+    );prog
+);procedure
+
+;Read BMP file
+	if(InFile = infile(bmpfile) then
+		bmpSize = fileLength(bmpfile)
+		declare(WORD[bmpSize])
+		for(Wnum 0 bmpSize-1	WORD[Wnum] = charToInt(getc(InFile)) )
+		close(InFile)
+	else
+		MessageForm("Input file does not exist!")
+		return()
+	)
+
+	sprintf(signature "%02x%02x" WORD[0] WORD[1])
+	offset = (WORD[0x0d]<<24) + (WORD[0x0c]<<16) + (WORD[0x0b]<<8) + WORD[0x0a] 
+	width  = (WORD[0x15]<<24) + (WORD[0x14]<<16) + (WORD[0x13]<<8) + WORD[0x12]
+	height = (WORD[0x19]<<24) + (WORD[0x18]<<16) + (WORD[0x17]<<8) + WORD[0x16]
+	pixel  = (WORD[0x1d]<<8) + WORD[0x1c]
+	ImageSize = (WORD[0x25]<<24) + (WORD[0x24]<<16) + (WORD[0x23]<<8) + WORD[0x22]
+
+	printf("--- BMP2LAY Start --- %L\n" getCurrentTime())
+	printf("offset  : 0x%x \n" offset)
+	printf("width   : 0x%x \n" width)
+	printf("height  : 0x%x \n" height)
+	printf("ImgSize : 0x%x \n" ImageSize)
+
+;check bmp file
+	if(!equal(signature "424d") then
+		MessageForm("*ERROR* Standard Input is not a BMP file")
+		return()
+	)
+
+;check mono bmp file
+	if(!equal(pixel 0x01) then
+		MessageForm("*ERROR* only supports mono bmp files")
+		return()
+	)
+
+;BMP2LAY
+	max_column = ImageSize/height<<3
+	number = offset+ImageSize-1
+
+	for(Wnum offset number
+		row = fix((Wnum-offset)/(max_column>>3))
+		y = Grid*row
+
+		for(i 0 7
+			dot = bitfield1(WORD[Wnum] 7-i)		; bit<7> ~ bit<0>
+			x = Grid*column
+			if(zerop(dot) && column<width then
+				geSelectObject(dbCreateRect(cv Layer list(x:y x+Grid:y+Grid)))
+			)
+			column++
+		);for
+		if(equal(column max_column)	column=0)
+		Wnum++
+	);for
+
+	hiZoomIn(win list(-10:-10 x+10:y+10))
+	printf("--- BMP2LAY End ----- %L\nt\n" getCurrentTime())
+);let
+
+;-------------------------------------------------------

abdelazeem201_ASIC-Design-Roadmap/MY-Design/MY_DESIGN.v

@@ -0,0 +1,71 @@
+
+module MY_DESIGN ( Cin1, Cin2, Cout, data1, data2, sel, clk, out1, out2, out3);
+  input [4:0] Cin1, Cin2, data1, data2;
+  input sel, clk;
+  output [4:0] Cout, out1, out2, out3;
+  reg   [4:0] R1, R2, R3, R4, out1, out2, out3;
+  wire   [4:0] arth_o;
+
+  ARITH U1_ARITH ( .a(data1), .b(data2), .sel(sel), .out1(arth_o) );
+  COMBO U_COMBO ( .Cin1(Cin1), .Cin2(Cin2), .sel(sel), .Cout(Cout) );
+
+
+always @ (posedge clk)
+  begin
+    R1 <= arth_o;
+    R2 <= data1 & data2;
+    R3 <= data1 + data2;
+    R4 <= R2 + R3;
+  end
+
+always @ (out2, R1, R3, R4)
+  begin
+    out1 <= R1 + R3;
+    out2 <= R3 & R4;
+    out3 <= out2 - R3;
+  end
+
+endmodule
+
+
+
+
+
+module ARITH ( a, b, sel, out1 );
+  input [4:0] a, b;
+  input sel;
+  output [4:0] out1;
+  reg [4:0] out1;
+
+always @(sel, a, b)
+
+  begin
+    case({sel})
+        1'b0: out1 <= a + b;
+        1'b1: out1 <= a - b;
+    endcase
+  end
+
+
+
+endmodule
+
+
+
+
+module COMBO ( Cin1, Cin2, sel, Cout );
+  input [4:0] Cin1, Cin2;
+  input sel;
+  output [4:0] Cout;
+  reg [4:0] Cout;
+
+  wire   [4:0] arth_o;
+
+  ARITH U2_ARITH ( .a(Cin1), .b(Cin2), .sel(sel), .out1(arth_o) );
+
+always @ (Cin1, arth_o)
+  begin
+    Cout <= arth_o + Cin1;
+  end
+
+endmodule

abdelazeem201_ASIC-Design-Roadmap/MY-Design/My_Design.cons

@@ -0,0 +1,141 @@
+###################################
+#                                 #
+#   UNITS                         #
+#                                 #
+###################################
+
+# The unit of time in this library is 1ns 
+# The unit of capacitance in this library is 1pF 
+#
+
+
+###################################
+#                                 #
+#   CLEAN-UP                      #
+#                                 #
+###################################
+
+# Remove any existing constraints and attributes
+#
+reset_design
+
+
+###################################
+#                                 #
+#   CLOCK DEFINITION              #
+#                                 #
+###################################
+
+# A 333Mhz clock is a 3.0ns period:
+#
+create_clock -period 3.0 [get_ports clk]
+
+
+# The maximum clock source latency is 700ps or 0.7ns
+#
+set_clock_latency -source  -max 0.7 [get_clocks clk] 
+
+
+# The maximum clock network latency is 300ps or 0.3 ns:
+#
+set_clock_latency -max 0.3 [get_clocks clk]
+
+
+# The +/-30ps clock insertion delay variation to register clock pins results in 
+# a 60ps worst case skew or uncertainty, if you launch late (+30ps) and 
+# capture early (-30ps)r; Add 40ps due to jitter and 50ps for setup margin;
+# This equals 150ps or 0.15 ns of total uncertainty.
+#
+set_clock_uncertainty -setup 0.15 [get_clocks clk]
+
+
+# The maximum clock transition is 120ps or 0.12ns
+#
+set_clock_transition -max 0.12 [get_clocks clk]
+
+
+###################################
+#                                 #
+#   INPUT TIMING                  #
+#                                 #
+###################################
+
+# The maximum "input delay" (external) on ports data1 and data2 is: 
+# clock period - clock uncertainty - delay of S - register setup time = 
+#     3.0      -      0.15         -     2.2   -      0.2            = 0.45ns
+# 
+set_input_delay -max  0.45 -clock clk [get_ports data*]  
+
+
+# The latest arrival time at port sel is 1.4ns (absolute time). The total clock insertion delay or latency to the external 
+# registers is 700ps + 300ps or 1.0ns. Therefore, the relative input delay on the port is 1.4 -1.0 = 0.4ns
+#
+set_input_delay -max  0.4 -clock clk [get_ports sel]
+
+
+###################################
+#                                 #
+#   OUTPUT TIMING                 #
+#                                 #
+###################################
+
+# The output delay at port out1 is 420ps + 80ps = 500ps or 0.5ns
+#
+set_output_delay -max  0.5 -clock clk [get_ports out1]
+
+
+# The internal delay to out2 is 810ps. The external capturing clock edge happens 3ns after the launch edge, 
+# minus the uncertainty of 0.15ns, or 2.85ns after launch. To constrain the internal delay to 0.81ns the 
+# output delay must therefore be constrained to 2.85ns - 0.81ns = 2.04ns.
+#
+set_output_delay -max 2.04  -clock clk [get_ports out2]
+
+
+# The setup time requirement on port out3 is 400ps or 0.4ns with respect to the capturing register's clock. 
+# This is, by definition, the "set_output_delay" value
+#
+set_output_delay -max  0.4 -clock clk [get_ports out3] 
+
+
+###################################
+#                                 #
+#   COMBINATIONAL LOGIC TIMING    #
+#                                 #
+###################################
+
+# The maximum delay through the combinational logic is 2.45ns. This can be constrained by pretending that there are 
+# launching registers on the input ports Cin1 and Cin2 and capturing registers on the output port Cout, and applying 
+# corresponding input and output delays. The sum of the external input and output delay values must be equal to the 
+# clock period minus the clock uncertainty minus the maximum combo delay = 3ns - 0.15ns - 2.45ns = 0.4ns. 
+# This means that the input and output delay values can be 0.4 and 0.0, or 0.2 and 0.2, or 0.1 and 0.3, etc., respectively.
+#
+set_input_delay -max 0.3 -clock clk [get_ports Cin*]
+set_output_delay -max 0.1 -clock clk [get_ports Cout]
+
+ 
+###################################
+#                                 #
+#   ENVIRONMENTAL ATTRIBUTES      #
+#                                 #
+###################################
+
+
+# All input ports, except clk and Cin, are driven by bufbd1 buffers
+#
+set_driving_cell -max -lib_cell bufbd1 \
+ [remove_from_collection [all_inputs] [get_ports "clk Cin*"]]
+
+
+# Port Cin is a chip level input and has an input transition of 120ps or 0.12 ns
+#
+set_input_transition -max 0.12 [get_ports Cin*]
+
+
+# All outputs, except Cout, drive 2x bufbd7 loads
+#
+set_load -max [expr {2 * [load_of cb13fs120_tsmc_max/bufbd7/I]}] [get_ports out*]
+
+
+# Cout drives 25fF, or .025 pF
+#
+set_load -max 0.025 [get_ports Cout*]

abdelazeem201_ASIC-Design-Roadmap/PrimeTime/RUN.tcl

@@ -0,0 +1,38 @@
+# - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+# PrimeTime STA run script for ORCA
+# - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
+
+########################
+# Setup
+
+source ./common_setup.tcl
+source ./pt_setup.tcl
+
+# Allow source to use search_path
+set sh_source_uses_search_path true
+
+# Do not allow black boxes for unresolved references
+set link_create_black_boxes false
+
+
+########################
+# READ and LINK
+
+read_verilog orca_routed.v.gz
+link_design ORCA
+
+read_parasitics ../ref/design_data/ORCA.SPEF.gz
+
+########################
+# Apply constraints
+
+source -echo -verbose orca_pt_constraints.tcl
+report_analysis_coverage
+
+########################
+# Save session
+
+file delete -force orca_savesession
+save_session orca_savesession
+
+quit

abdelazeem201_ASIC-Design-Roadmap/PrimeTime/UsefulScripts/report_case_propagation.tcl

@@ -0,0 +1,118 @@
+# report_case_propagation.tcl - trace case analysis back to source(s)
+# abdelazeem@synopsys.com
+#
+# v1.0  05/25/2024  abdelazeem
+#  initial release
+# v1.01 05/31/2024  abdelazeem
+#  fix bug with parallel arcs between two pins
+
+proc report_case_propagation {args} {
+ parse_proc_arguments -args $args results
+
+ set objects {}
+ append_to_collection objects [get_pins -quiet $results(pins_ports)]
+ append_to_collection objects [get_ports -quiet $results(pins_ports)]
+
+ # make a list of startpoint contexts to queue up
+ # (I use a flat context list instead of succumbing to the lure of recursion...)
+ set queued_contexts {}
+ foreach_in_collection object $objects {
+  lappend queued_contexts [list $object 0]
+ }
+
+ array unset visited_from_pins
+ array unset visited_pairs
+ while {$queued_contexts ne {}} {
+
+  # pop next to_pin off list
+  set context [lindex $queued_contexts 0]
+  foreach {to_pin indent_level} $context {}
+  set queued_contexts [lrange $queued_contexts 1 end]
+  set to_pin_name [get_object_name $to_pin]
+
+  # get list of valid from_pins with case values
+  set valid_from_pins {}
+  if {[set user_case_value [get_attribute -quiet $to_pin user_case_value]] eq {}} {
+   foreach_in_collection arc [get_timing_arcs -quiet -to $to_pin] {
+    if {[set from_pin [filter_collection [get_attribute $arc from_pin] {defined(case_value)}]] ne {}} {
+     append_to_collection -unique valid_from_pins $from_pin
+    }
+   }
+  }
+
+  # from the valid from_pins, get list of the from_pins for all the
+  # unvisited backwards *arcs* ending at this pin
+  # (the visited_pairs() array contains all the backwards arcs we've been down before)
+  set unvisited_from_pins {}
+  foreach_in_collection from_pin $valid_from_pins {
+   set from_pin_name [get_object_name $from_pin]
+   if {![info exists visited_pairs([list $from_pin_name $to_pin_name])]} {
+    append_to_collection unvisited_from_pins $from_pin
+   }
+  }
+
+  # print information about this to_pin
+  switch [get_attribute $to_pin object_class] {
+   pin {
+    if {[set ref_info [get_object_name [get_lib_cells -quiet -of [get_cells -quiet -of $to_pin]]]] eq {}} {
+     set ref_info [get_attribute [get_cells -quiet -of $to_pin] ref_name]
+    }
+   }
+   port {set ref_info "[get_attribute $to_pin port_direction] port"}
+  }
+  if {[sizeof_collection $valid_from_pins] >= 1 && [sizeof_collection $unvisited_from_pins]==0} {
+   # in this branch, we arrived at this to_pin but all backwards arcs have previously been visited
+   set branch_info " (previously covered path)"
+  } elseif {[sizeof_collection $valid_from_pins] > 1} {
+   # multiple backwards arcs exist, so there are multiple branches to trace back
+   set branch_info " (branch [expr {1+[sizeof_collection $valid_from_pins]-[sizeof_collection $unvisited_from_pins]}] of [sizeof_collection $valid_from_pins] follows)"
+  } else {
+   # just a single unambiguous path to trace back
+   set branch_info {}
+  }
+  if {$user_case_value ne {}} {
+   set case_info "user-defined case=$user_case_value"
+  } else {
+   set case_info "case=[get_attribute -quiet $to_pin case_value]"
+  }
+  echo "[string repeat { } $indent_level][get_object_name $to_pin] ($ref_info) $case_info${branch_info}"
+
+  # restart loop with next to_pin context if there's nothing to trace back
+  # (nothing to queue up)
+  if {$unvisited_from_pins eq {}} {
+   continue
+  }
+
+  # first, grab the first from_pin on the list
+  set from_pin [index_collection $unvisited_from_pins 0]
+  set from_pin_name [get_object_name $from_pin]
+  set unvisited_from_pins [remove_from_collection $unvisited_from_pins $from_pin]
+
+  # if there are any additional remaining from_pins, queue *this* to_pin up again
+  # so that we can trace back those other branches too
+  if {$unvisited_from_pins ne {}} {
+   set queued_contexts [linsert $queued_contexts 0 [list $to_pin $indent_level]]
+  }
+
+  # now, push our first unvisited from_pin onto the list of to_pins to visit next
+  # (this moves us backwards down this path, and the fact that we push it last
+  # causes the depth-first backtrace)
+  if {[sizeof_collection $valid_from_pins] > 1} {
+   incr indent_level
+  }
+  set queued_contexts [linsert $queued_contexts 0 [list $from_pin $indent_level]]
+
+  # mark this arc as visited (so we never propagate past it in the future)
+  set visited_pairs([list $from_pin_name $to_pin_name]) 1
+ }
+
+ echo ""
+}
+
+define_proc_attributes report_case_propagation \
+ -info "trace case analysis back to source(s)" \
+ -define_args \
+ {
+  {pins_ports {pin(s)/port(s) where case value is present} pins_ports string required}
+ }
+

abdelazeem201_ASIC-Design-Roadmap/PrimeTime/common_setup.tcl

@@ -0,0 +1,86 @@
+##########################################################################################
+# common variables
+# Script: common_setup.tcl
+# Version: O-2018.06 (Oct. 3, 2022)
+# Copyright (C) 2022, 2024 abdelazeem.
+##########################################################################################
+
+set DESIGN_NAME                   "ORCA"  ;#  The name of the top-level design
+
+set DESIGN_REF_DATA_PATH          "../ref"  ;#  Absolute path prefix variable for library/design data.
+                                        #  Use this variable to prefix the common absolute path to 
+                                        #  the common variables defined below.
+                                        #  Absolute paths are mandatory for hierarchical RM flow.
+
+##########################################################################################
+# Library Setup Variables
+##########################################################################################
+
+# For the following variables, use a blank space to separate multiple entries
+# Example: set TARGET_LIBRARY_FILES "lib1.db lib2.db lib3.db"
+
+set ADDITIONAL_SEARCH_PATH        "$DESIGN_REF_DATA_PATH/design_data  $DESIGN_REF_DATA_PATH/libs  $DESIGN_REF_DATA_PATH/scripts  $DESIGN_REF_DATA_PATH/tcl_procs ./pt_scripts"   ; #  Additional search path to be added to the default search path
+
+set TARGET_LIBRARY_FILES          "sc_max.db" ;#  Target technology logical libraries
+
+
+set ADDITIONAL_LINK_LIB_FILES     "io_max.db \
+                                   special.db \
+                                   mem_max.db " ;#  Extra link logical libraries not included in TARGET_LIBRARY_FILES
+
+
+
+set MIN_LIBRARY_FILES             "";#  List of max min library pairs "max1 min1 max2 min2 max3 min3"...
+
+set MW_REFERENCE_LIB_DIRS         "" ;#  Milkyway reference libraries
+
+set MW_REFERENCE_CONTROL_FILE     ""  ;#  Reference Control file to define the MW ref libs
+
+set TECH_FILE                     "${DESIGN_REF_DATA_PATH}/libs/tech/cb13_6m.tf"  ;#  Milkyway technology file
+
+
+set MAP_FILE                      "${DESIGN_REF_DATA_PATH}/libs/tlup/cb13_6m.map"  ;#  Mapping file for TLUplus
+
+set TLUPLUS_MAX_FILE              "${DESIGN_REF_DATA_PATH}/libs/tlup/cb13_6m_max.tluplus"  ;#  Max TLUplus file
+
+set TLUPLUS_MIN_FILE              "${DESIGN_REF_DATA_PATH}/libs/tlup/cb13_6m_min.tluplus"  ;#  Min TLUplus file
+
+set MW_POWER_NET                  "VDD" ;#
+set MW_POWER_PORT                 "VDD" ;#
+set MW_GROUND_NET                 "VSS" ;#
+set MW_GROUND_PORT                "VSS" ;#
+
+set MIN_ROUTING_LAYER             ""   ;# Min routing layer
+set MAX_ROUTING_LAYER             "METAL2"   ;# Max routing layer
+
+
+##########################################################################################
+# Multi-Voltage Common Variables
+#
+# Define the following MV common variables for the RM scripts for multi-voltage flows.
+# Use as few or as many of the following definitions as needed by your design.
+##########################################################################################
+
+set PD1                          ""           ;# Name of power domain/voltage area  1
+set PD1_CELLS                    ""           ;# Instances to include in power domain/voltage area 1
+set VA1_COORDINATES              {}           ;# Coordinates for voltage area 1
+set MW_POWER_NET1                "VDD1"       ;# Power net for voltage area 1
+set MW_POWER_PORT1               "VDD"        ;# Power port for voltage area 1
+
+set PD2                          ""           ;# Name of power domain/voltage area  2
+set PD2_CELLS                    ""           ;# Instances to include in power domain/voltage area 2
+set VA2_COORDINATES              {}           ;# Coordinates for voltage area 2
+set MW_POWER_NET2                "VDD2"       ;# Power net for voltage area 2
+set MW_POWER_PORT2               "VDD"        ;# Power port for voltage area 2
+
+set PD3                          ""           ;# Name of power domain/voltage area  3
+set PD3_CELLS                    ""           ;# Instances to include in power domain/voltage area 3
+set VA3_COORDINATES              {}           ;# Coordinates for voltage area 3
+set MW_POWER_NET3                "VDD3"       ;# Power net for voltage area 3
+set MW_POWER_PORT3               "VDD"        ;# Power port for voltage area 3
+
+set PD4                          ""           ;# Name of power domain/voltage area  4
+set PD4_CELLS                    ""           ;# Instances to include in power domain/voltage area 4
+set VA4_COORDINATES              {}           ;# Coordinates for voltage area 4
+set MW_POWER_NET4                "VDD4"       ;# Power net for voltage area 4
+set MW_POWER_PORT4               "VDD"        ;# Power port for voltage area 4

abdelazeem201_ASIC-Design-Roadmap/PrimeTime/pt.tcl

@@ -0,0 +1,116 @@
+################################################################################
+start_profile
+set timing_update_status_level high
+
+
+################################################################################
+set sh_source_emits_line_numbers E
+set sh_continue_on_error true
+
+
+#################################################################################
+# PrimeTime Script
+# Script: pt.tcl
+# Version: O-2018.06-SP2 (September. 28, 2018)
+# Copyright (C) 2022-2024 abdelazeem.
+#################################################################################
+
+
+##################################################################
+#    Source common and pt_setup.tcl File                         #
+##################################################################
+
+# Allow source to use search_path
+set sh_source_uses_search_path true 
+source ./common_setup.tcl
+source ./pt_setup.tcl
+
+
+##################################################################
+#    Search Path, Library and Operating Condition Section        #
+##################################################################
+
+
+set report_default_significant_digits 3 ;
+set sh_source_uses_search_path true 
+set search_path " $search_path" ;
+
+
+##################################################################
+#    Netlist Reading Section                                     #
+##################################################################
+
+set link_path " $link_path"
+
+read_verilog $NETLIST_FILES
+
+current_design $DESIGN_NAME 
+link_design -verbose 
+
+##################################################################
+#    Back Annotation Section                                     #
+##################################################################
+
+read_parasitics  $PARASITIC_FILES 
+
+report_annotated_parasitics -check > $REPORTS_DIR/rap.report
+
+
+##################################################################
+#    Reading Constraints Section                                 #
+##################################################################
+if  {[info exists CONSTRAINT_FILES]} {
+        foreach constraint_file $CONSTRAINT_FILES {
+                if {[file extension $constraint_file] eq ".sdc"} {
+                        read_sdc -echo $constraint_file
+                } else {
+                        source -echo $constraint_file
+                }
+        }
+}
+
+
+##################################################################
+#    Clock Tree Synthesis Section                                #
+##################################################################
+
+set_propagated_clock [all_clocks] 
+
+
+##################################################################
+#    Update_timing and check_timing Section                      #
+##################################################################
+
+update_timing -full
+
+# Ensure design is properly constrained
+check_timing -verbose > $REPORTS_DIR/ct.report
+
+##################################################################
+#    Report_timing Section                                       #
+##################################################################
+# Report Timing
+report_timing -slack_lesser_than 0.0 -delay min_max -nosplit -input -net -sign 4 > $REPORTS_DIR/rt.report
+report_clock -skew -attribute > $REPORTS_DIR/rc.report 
+report_analysis_coverage > $REPORTS_DIR/rac.report
+
+
+#################################################################
+#    Save Session                                               #
+#################################################################
+
+
+
+
+
+
+
+
+
+
+##########################################################################
+stop_profile
+save_session my_savesession
+print_message_info
+exit
+##########################################################################

abdelazeem201_ASIC-Design-Roadmap/PrimeTime/pt_setup.tcl

@@ -0,0 +1,101 @@
+
+
+### pt_setup.tcl file              ###
+
+
+
+
+### Start of PrimeTime Runtime Variables ###
+
+
+##########################################################################################
+# PrimeTime Variables PrimeTime script
+# Script: pt_setup.tcl
+# Version: O-2018.06-SP2 (April. 28, 2024)
+# Copyright (C) 2022-2024 abdelazeem.
+##########################################################################################
+
+
+######################################
+# Report and Results directories
+######################################
+
+
+set REPORTS_DIR "reports"
+file mkdir $REPORTS_DIR
+
+
+######################################
+# Library & Design Setup
+######################################
+
+
+### Mode : Generic
+
+set search_path ". $ADDITIONAL_SEARCH_PATH $search_path"
+set target_library $TARGET_LIBRARY_FILES
+set link_path "* $target_library $ADDITIONAL_LINK_LIB_FILES"
+
+
+# Provide list of  Verilog netlist file. It can be compressed ---example "A.v B.v C.v"
+set NETLIST_FILES               "orca_routed.v.gz"
+
+# DESIGN_NAME will be checked for existence from common_setup.tcl
+if {[string length $DESIGN_NAME] > 0} {
+} else {
+set DESIGN_NAME                   ""  ;#  The name of the top-level design
+}
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+######################################
+# Back Annotation File Section
+######################################
+
+#PARASITIC Files --- example "top.sbpf A.sbpf" 
+#The path (instance name) and name of the parasitic file --- example "top.spef A.spef" 
+#Each PARASITIC_PATH entry corresponds to the related PARASITIC_FILE for the specific block"   
+#For a single toplevel PARASITIC file please use the toplevel design name in PARASITIC_PATHS variable."   
+set PARASITIC_PATHS	 "ORCA" 
+set PARASITIC_FILES	 "ORCA.SPEF.gz" 
+
+
+
+######################################
+# Constraint Section Setup
+######################################
+# Provide one or a list of constraint files.  for example "top.sdc" or "clock.sdc io.sdc te.sdc"
+set CONSTRAINT_FILES	 "var_Day1.tcl orca_pt_constraints.tcl"  
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+######################################
+# End
+######################################
+
+
+
+### End of PrimeTime Runtime Variables ###

abdelazeem201_ASIC-Design-Roadmap/README.md

@@ -0,0 +1,220 @@
+# 🧠 ASIC Design Roadmap
+
+> Empowering students worldwide with a complete roadmap to learn **Application Specific Integrated Circuit (ASIC)** Design — from logic to layout, RTL to GDSII.
+
+<div align="center">بِسْمِ اللهِ الرَّحْمنِ الرَّحِيم</div>
+<div align="center">“وَمَا أُوتِيتُمْ مِنَ الْعِلْمِ إِلَّا قَلِيلًا”</div>
+
+---
+
+The journey of designing an ASIC (Application Specific Integrated Circuit) is long and deeply technical — transforming an idea into silicon requires precision, planning, and patience. Despite the final chip being only a few nanometers in scale, the design process includes multiple sophisticated steps filled with engineering challenges and opportunities for learning.
+
+ASICs are purpose-built chips tailored for specific applications. Unlike general-purpose processors or FPGAs, they are optimized for power, performance, and area (PPA), making them ideal for mass production. Their circuits, built from permanent gates and flip-flops, are described using hardware description languages such as Verilog, SystemVerilog, or VHDL.
+
+> ✅ More power-efficient than FPGAs  
+> ✅ Capable of higher frequencies  
+> ✅ Ideal for high-volume production  
+> ⚠️ Not suitable for frequent upgrades  
+> ⚠️ Bugs after tape-out are costly
+
+![Complex ASIC Design](https://github.com/abdelazeem201/ASIC-Physical-Design-Roadmap/blob/main/Figures/Fig.%20Complex%20ASIC%20Design.jpeg)
+---
+
+# 📌 Why This Roadmap?
+Many students and entry-level engineers want to break into the world of IC design but are unsure where to begin or how to build strong fundamentals. When you search for resources online, the flood of random posts and YouTube videos can leave you even more lost and overwhelmed. That’s why I decided to build this open-source roadmap — to make the learning process smoother and more organized for anyone looking to enter the industry.
+
+# 🎯 Who Is This For?
+Whether you’re a student, fresh graduate, or an engineer transitioning into VLSI, this roadmap is tailored to help you navigate Physical Design — one of the most critical and challenging domains in ASIC development.
+
+# 🚀 What’s Inside?
+This roadmap is not just a list of tools or topics. It’s a carefully structured guide with:
+
+> * Step-by-step learning paths from basic concepts to industry-level knowledge
+> * Hands-on projects and scripts to give you practical experience
+> * Tips and insights from real-world Physical Design workflows
+> * Links to trusted resources — not just random Google or YouTube results
+
+
+---
+
+## 📘 Table of Contents
+
+- [Introduction](#introduction)
+- [Fundamentals](#fundamentals)
+- [ASIC Design Flow](#asic-design-flow)
+- [Awesome Digital IC Resources](#awesome-digital-ic-resources)
+- [Project Repositories and IPs](#project-repositories-and-ips)
+
+---
+
+## 🧾 Introduction
+
+The aim of this roadmap is to provide aspiring ASIC and Digital IC designers a clear path to follow — with carefully selected courses, resources, and projects that balance theory and practice. Whether you're a beginner or transitioning from FPGA/Embedded design, this roadmap is crafted to guide you through every phase of ASIC development.
+
+---
+
+## 🧱 Fundamentals
+
+### 1. **Digital Electronics & CMOS Basics**
+- [Digital Electronics (Playlist)](https://www.youtube.com/playlist?list=PLMSBalys69yzp1vrmnYAmpRFiptbuGuaj) 📽  
+  *Focus: Logic gates, FFs, CMOS inverter, MOSFET switching.*
+
+### 2. **Digital Logic Design / Frontend**
+- [Digital Design – CS221 by Dr. Waleed Youssef](https://youtube.com/playlist?list=PLoK2Lr1miEm8b6Vv5zAfsbMEPZ1C7fCQw) 📽  
+- [Verilog Modeling – Dr. Indranil Sen Gupta](https://www.youtube.com/playlist?list=PLJ5C_6qdAvBELELTSPgzYkQg3HgclQh-5) 📽  
+
+### 3. **Computer Architecture**
+- [Digital Design and Computer Architecture (YouTube)](https://www.youtube.com/playlist?list=PL5Q2soXY2Zi_FRrloMa2fUYWPGiZUBQo2) 📽
+
+### 4. **Digital IC Design (RTL to ASIC)**
+> Based on "CMOS VLSI Design" by Weste & Harris  
+- [Part 1](https://youtube.com/playlist?list=PLMSBalys69yzvAKErDt7tT7O-iIKPlOCP) 📽  
+- [Part 2](https://youtube.com/playlist?list=PLMSBalys69yxoIjeZ2Q3fxs69cGCU14B1) 📽  
+- [Part 3](https://youtube.com/playlist?list=PLMSBalys69yw1tSoF42QW9jbbC0-UeCAy) 📽  
+
+---
+
+## 🔧 ASIC Design Flow
+
+### Logic Synthesis & Timing Closure
+- [Advanced Logic Synthesis by Dhiraj Taneja](https://www.youtube.com/playlist?list=PLbMVogVj5nJQe0_9YJlN9S7ktkA8DI-fL) 📽  
+  *Includes Synopsys DC/PT Labs – skip first 12 videos if needed*
+
+### Physical Design
+- [Physical Design – Prof. Indranil Sengupta](https://www.youtube.com/playlist?list=PLU8VFS-HdvKtKswbcvvA8yVhzleTV7OE8) 📽  
+  *Covers Floorplanning, Placement, CTS, Routing, DRC/LVS*
+
+- [RTL to GDSII (by Adi Teman)](https://www.youtube.com/playlist?list=PLZU5hLL_713x0_AV_rVbay0pWmED7992G) 📽  
+  *Very recommended* ✅
+
+- [My Slideshare RTL2GDSII Notes](https://www.slideshare.net/AhmedAbdelazeem28/presentations) 📚
+
+---
+
+## 🌍 Awesome Digital IC Resources
+
+> Curated lists and tools for ASIC/VLSI/FPGA engineers
+
+| Name | Type | Description |
+|------|------|-------------|
+| [Awesome FPGA](https://github.com/Vitorian/awesome-fpga) | 📍⭐ | FPGA resources and boards |
+| [Awesome HDL](https://github.com/drom/awesome-hdl) | 📍⭐ | Hardware description languages |
+| [Awesome Open Source EDA](https://github.com/clin99/awesome-eda) | 📍 | Open-source EDA tools |
+| [Awesome Hardware Verification](https://github.com/ben-marshall/awesome-open-hardware-verification) | 📍 | Verification tools |
+| [Awesome HWD Tools](https://github.com/TM90/awesome-hwd-tools) | 📍 | Open-source IC design tools |
+| [Awesome Lattice FPGAs](https://github.com/kelu124/awesome-latticeFPGAs) | 📍 | Lattice FPGA board list |
+
+---
+
+## 📦 Project Repositories and IPs
+
+### Core IPs and Repos
+- [OpenCores](https://opencores.org/) ⭐ - IP Cores Archive  
+- [FreeCores](http://freecores.github.io/) 📍 - Legacy IPs from OpenCores  
+- [Basic Verilog Modules](https://github.com/pConst/basic_verilog) 📍 - Synthesizable Verilog modules  
+- [32 Mini Projects (Verilog)](https://github.com/sudhamshu091/32-Verilog-Mini-Projects) 📍👶
+
+### Communication Protocols
+- [Alex Forencich's IPs](http://alexforencich.com/wiki/en/verilog/start) - PCIe, Ethernet, I2C, UART and more
+
+
+### Information Technology
+
+#### RISC-V
+
+- [RISC-V Instruction Set Manual](https://github.com/riscv/riscv-isa-manual) - This repository contains the LaTeX source for the draft RISC-V Instruction Set Manual.
+
+- [RISC-V Exchange: Cores & SoCs](https://riscv.org/exchanges/cores-socs/) - A list of RICS-V cores and SoCs.
+- [PULP](https://github.com/pulp-platform/pulp) - Open source Parallel Ultra-Low-Power RISC-V core.
+- [openc910](https://github.com/T-head-Semi/openc910) 📍![stars](https://img.shields.io/github/stars/T-head-Semi/openc910) - OpenXuantie C910 Core.
+- [XiangShan](https://github.com/OpenXiangShan/XiangShan) 📍![stars](https://img.shields.io/github/stars/OpenXiangShan/XiangShan) - Open-source high-performance RISC-V processor.
+- [riscv-starship](https://github.com/riscv-zju/riscv-starship) 📍![stars](https://img.shields.io/github/stars/riscv-zju/riscv-starship) - Run rocket-chip on FPGA(Xilinx Virtex-7 VC707).
+- [Wujian100](https://github.com/T-head-Semi/wujian100_open) 📍![stars](https://img.shields.io/github/stars/T-head-Semi/wujian100_open) - A MCU base SoC.
+- [picorv32](https://github.com/YosysHQ/picorv32) 📍![stars](https://img.shields.io/github/stars/YosysHQ/picorv32) - A Size-Optimized RISC-V CPU.
+- [Hummingbirdv2 E203 Core and SoC](https://github.com/riscv-mcu/e203_hbirdv2) 📍![stars](https://img.shields.io/github/stars/riscv-mcu/e203_hbirdv2) [Docs](https://doc.nucleisys.com/hbirdv2/) - A Ultra-Low Power RISC-V Core.
+- [darkriscv](https://github.com/darklife/darkriscv) 📍![stars](https://img.shields.io/github/stars/darklife/darkriscv) - A proof of concept for the opensource RISC-V instruction set.
+- [CVA6 RISC-V CPU](https://github.com/openhwgroup/cva6) 📍![stars](https://img.shields.io/github/stars/openhwgroup/cva6) - An application class 6-stage RISC-V CPU capable of booting Linux.
+- [VexRiscv](https://github.com/SpinalHDL/VexRiscv) 📍![stars](https://img.shields.io/github/stars/SpinalHDL/VexRiscv) - A FPGA friendly 32 bit RISC-V CPU implementation.
+
+#### Others
+
+- [zipcpu](https://github.com/ZipCPU/zipcpu) ⭐📍![stars](https://img.shields.io/github/stars/ZipCPU/zipcpu) - with detailed comments.
+- [openmsp430](https://opencores.org/projects/openmsp430) - The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog.
+- [Nyuzi Processor](https://github.com/jbush001/NyuziProcessor) 📍![stars](https://img.shields.io/github/stars/jbush001/NyuziProcessor) - GPGPU microprocessor architecture.
+
+## Tutorials and Courses 💬[Intro](./Tutorials%20and%20Courses/README.md)
+
+- [zipcpu](http://zipcpu.com/tutorial/) 👶 - Verilog, Formal Verification and Verilator Beginner's Tutorial
+- [WORLD OF ASIC](http://asic-world.com/) ⭐ - A great source of detailed VLSI tutorials and examples.
+
+### HDL
+
+- More information about hardware description language on [Awesome HDL](https://github.com/drom/awesome-hdl)
+
+#### Verilog Grammar
+
+- [Verilog TUTORIAL for beginners](http://www.referencedesigner.com/tutorials/verilog/verilog_01.php) 👶 - A tutorial based upon free Icarus Verilog compiler.
+- [ChipVerify: Verilog Tutorial](https://www.chipverify.com/verilog/verilog-tutorial) - A guide for someone new to Verilog.
+- [Verilog/SystemVerilog Guide](https://github.com/mikeroyal/Verilog-SystemVerilog-Guide) 📍![stars](https://img.shields.io/github/stars/mikeroyal/Verilog-SystemVerilog-Guide) - A guide covering Verilog & SystemVerilog.
+
+
+#### VHDL Grammar
+
+- [VHDL Guide](https://github.com/mikeroyal/VHDL-Guide) 📍![stars](https://img.shields.io/github/stars/mikeroyal/VHDL-Guide) - A guide covering VHDL.
+
+
+### Verification
+
+- [Verification Academy](https://verificationacademy.com/) - The most comprehensive resource for verification training.
+- [Verification Guide](https://www.verificationguide.com/p/home.html) - Tutorials with links to example codes on EDA Playground.
+- [Doulos](https://www.doulos.com) - Global training solutions for engineers creating the world's electronics products.
+- [testbench](http://www.testbench.in/) - Some training articals for systemverilog.
+- [ClueLogic](http://cluelogic.com) - Providing the clues to solve your verification problems.
+- [ChipVerify](https://www.chipverify.com/) - A simple and complete set of verilog/System Verilog/UVM tutorials.
+
+### Build a CPU
+
+- [RISC-V Guide](https://github.com/mikeroyal/RISC-V-Guide) 📍![stars](https://img.shields.io/github/stars/mikeroyal/RISC-V-Guide) - A guide covering the RISC-V Architecture.
+- [ARM Guide](https://github.com/mikeroyal/ARM-Guide) 📍![stars](https://img.shields.io/github/stars/mikeroyal/ARM-Guide) - A guide covering ARM architecture.
+- [nand2tetris](https://www.nand2tetris.org/) - Build an advanced computer from nand gate.
+- [Building a RISC-V CPU Core - edX](https://www.edx.org/course/building-a-risc-v-cpu-core) 📽 - Build a RISC-V cpu core. No prior knowledge of digital logic design is required.
+- [Build a Modern Computer from First Principles: From Nand to Tetris - coursera](https://www.coursera.org/learn/build-a-computer "依据基本原理构建现代计算机：从与非门到俄罗斯方块（基于项目的课程）") 📽 - Build a modern computer system.
+
+### FPGA
+
+- [FPGA Tutorial](https://github.com/LeiWang1999/FPGA) 
+- [Complex Programmable Logic Device (CPLD) Guide](https://github.com/mikeroyal/CPLD-Guide) 📍![stars](https://img.shields.io/github/stars/mikeroyal/CPLD-Guide) - A guide covering CPLD.
+
+## Tools
+
+- [EDA Playground](https://www.edaplayground.com/) - Edit, save, simulate, synthesize SystemVerilog, Verilog, VHDL and other HDLs from your web browser.
+- [tree-core-ide](https://github.com/microdynamics-cpu/tree-core-ide)  📍![stars](https://img.shields.io/github/stars/microdynamics-cpu/tree-core-ide)- A VSCode-based HDL extension.
+- [WaveDrom](https://wavedrom.com/) - Digital Timing Diagram everywhere
+- [Icarus Verilog](http://iverilog.icarus.com/) 📍[Github](https://github.com/steveicarus/iverilog)![stars](https://img.shields.io/github/stars/steveicarus/iverilog) - A Verilog simulation and synthesis tool.
+- [GTKWave](http://gtkwave.sourceforge.net/) - GTKWave is a fully featured GTK+ based wave viewer.
+- [OpenROAD](https://theopenroadproject.org/) 💬[Doc](https://openroad.readthedocs.io/en/latest/main/README.html) 📍[Github](https://github.com/The-OpenROAD-Project/OpenROAD)![stars](https://img.shields.io/github/stars/The-OpenROAD-Project/OpenROAD) - An RTL-to-GDS Flow
+- More information about hardware dv tools on [Awesome Open Hardware Verification - Tools](https://github.com/ben-marshall/awesome-open-hardware-verification#Tools) and [Awesome HWD Tools](https://github.com/TM90/awesome-hwd-tools)
+
+
+
+## Online Judge Platforms
+
+- [HDL bits](https://hdlbits.01xz.net/wiki/Main_Page) - A collection of small circuit design exercises for practicing digital hardware design using Verilog Hardware Description Language (HDL).
+- [nowcoder - Verilog Part](https://www.nowcoder.com/exam/oj?page=1&tab=Verilog%E7%AF%87&topicId=301) - A verilog oj platform.
+---
+
+## 🧠 Final Thoughts
+
+🔹 Start slow, stay consistent.  
+🔹 Simulate everything before synthesizing.  
+🔹 Join VLSI communities and open-source projects.  
+🔹 Learn by doing – replicate designs, break them, and fix them.  
+
+If this roadmap helped you, consider sharing it with others or contributing back to the repo!  
+📬 For inquiries or collaborations: [a.abdelazeem201@gmail.com](mailto:a.abdelazeem201@gmail.com)
+
+---
+
+> _“Whoever treads a path in search of knowledge, Allah will make easy for him the path to Paradise.” – Prophet Muhammad ﷺ_
+
+

abdelazeem201_ASIC-Design-Roadmap/cmsdk/blk_mem_zed.v

@@ -0,0 +1,184 @@
+/*******************************************************************************
+*     This file is owned and controlled by Xilinx and must be used solely      *
+*     for design, simulation, implementation and creation of design files      *
+*     limited to Xilinx devices or technologies. Use with non-Xilinx           *
+*     devices or technologies is expressly prohibited and immediately          *
+*     terminates your license.                                                 *
+*                                                                              *
+*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY     *
+*     FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES.  BY     *
+*     PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE              *
+*     IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS       *
+*     MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY       *
+*     CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY        *
+*     RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY        *
+*     DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE    *
+*     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR           *
+*     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF          *
+*     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A    *
+*     PARTICULAR PURPOSE.                                                      *
+*                                                                              *
+*     Xilinx products are not intended for use in life support appliances,     *
+*     devices, or systems.  Use in such applications are expressly             *
+*     prohibited.                                                              *
+*                                                                              *
+*     (c) Copyright 1995-2023 Xilinx, Inc.                                     *
+*     All rights reserved.                                                     *
+*******************************************************************************/
+// You must compile the wrapper file blk_mem_zed.v when simulating
+// the core, blk_mem_zed. When compiling the wrapper file, be sure to
+// reference the XilinxCoreLib Verilog simulation library. For detailed
+// instructions, please refer to the "CORE Generator Help".
+
+// The synthesis directives "translate_off/translate_on" specified below are
+// supported by Xilinx, Mentor Graphics and Synplicity synthesis
+// tools. Ensure they are correct for your synthesis tool(s).
+
+`timescale 1ns/1ps
+
+module blk_mem_zed #(
+  parameter filename = "mem0.mif")
+  (
+  clka,
+  ena,
+  wea,
+  addra,
+  dina,
+  douta
+);
+
+input clka;
+input ena;
+input [0 : 0] wea;
+input [13 : 0] addra;
+input [7 : 0] dina;
+output [7 : 0] douta;
+
+// synthesis translate_off
+
+  BLK_MEM_GEN_V7_1 #(
+    .C_ADDRA_WIDTH(14),
+    .C_ADDRB_WIDTH(14),
+    .C_ALGORITHM(1),
+    .C_AXI_ID_WIDTH(4),
+    .C_AXI_SLAVE_TYPE(0),
+    .C_AXI_TYPE(1),
+    .C_BYTE_SIZE(9),
+    .C_COMMON_CLK(0),
+    .C_DEFAULT_DATA(""),
+    .C_DISABLE_WARN_BHV_COLL(0),
+    .C_DISABLE_WARN_BHV_RANGE(0),
+    .C_ENABLE_32BIT_ADDRESS(0),
+    .C_FAMILY("zynq"),
+    .C_HAS_AXI_ID(0),
+    .C_HAS_ENA(1),
+    .C_HAS_ENB(0),
+    .C_HAS_INJECTERR(0),
+    .C_HAS_MEM_OUTPUT_REGS_A(0),
+    .C_HAS_MEM_OUTPUT_REGS_B(0),
+    .C_HAS_MUX_OUTPUT_REGS_A(0),
+    .C_HAS_MUX_OUTPUT_REGS_B(0),
+    .C_HAS_REGCEA(0),
+    .C_HAS_REGCEB(0),
+    .C_HAS_RSTA(0),
+    .C_HAS_RSTB(0),
+    .C_HAS_SOFTECC_INPUT_REGS_A(0),
+    .C_HAS_SOFTECC_OUTPUT_REGS_B(0),
+    .C_INIT_FILE_NAME(filename),
+    //.C_INIT_FILE_NAME(""),
+    .C_INITA_VAL(""),
+    .C_INITB_VAL(""),
+    .C_INTERFACE_TYPE(0),
+    .C_LOAD_INIT_FILE(1),
+    //.C_LOAD_INIT_FILE(0),
+    .C_MEM_TYPE(0),
+    .C_MUX_PIPELINE_STAGES(0),
+    .C_PRIM_TYPE(1),
+    .C_READ_DEPTH_A(16384),
+    .C_READ_DEPTH_B(16384),
+    .C_READ_WIDTH_A(8),
+    .C_READ_WIDTH_B(8),
+    .C_RST_PRIORITY_A("CE"),
+    .C_RST_PRIORITY_B("CE"),
+    .C_RST_TYPE("SYNC"),
+    .C_RSTRAM_A(0),
+    .C_RSTRAM_B(0),
+    .C_SIM_COLLISION_CHECK("ALL"),
+    .C_USE_BYTE_WEA(0),
+    .C_USE_BYTE_WEB(0),
+    .C_USE_DEFAULT_DATA(0),
+    .C_USE_ECC(0),
+    .C_USE_SOFTECC(0),
+    .C_WEA_WIDTH(1),
+    .C_WEB_WIDTH(1),
+    .C_WRITE_DEPTH_A(16384),
+    .C_WRITE_DEPTH_B(16384),
+    .C_WRITE_MODE_A("READ_FIRST"),
+    .C_WRITE_MODE_B("WRITE_FIRST"),
+    .C_WRITE_WIDTH_A(8),
+    .C_WRITE_WIDTH_B(8),
+    .C_XDEVICEFAMILY("zynq")
+  )
+  inst (
+    .CLKA(clka),
+    .ENA(ena),
+    .WEA(wea),
+    .ADDRA(addra),
+    .DINA(dina),
+    .DOUTA(douta),
+    .RSTA(),
+    .REGCEA(),
+    .CLKB(),
+    .RSTB(),
+    .ENB(),
+    .REGCEB(),
+    .WEB(),
+    .ADDRB(),
+    .DINB(),
+    .DOUTB(),
+    .INJECTSBITERR(),
+    .INJECTDBITERR(),
+    .SBITERR(),
+    .DBITERR(),
+    .RDADDRECC(),
+    .S_ACLK(),
+    .S_ARESETN(),
+    .S_AXI_AWID(),
+    .S_AXI_AWADDR(),
+    .S_AXI_AWLEN(),
+    .S_AXI_AWSIZE(),
+    .S_AXI_AWBURST(),
+    .S_AXI_AWVALID(),
+    .S_AXI_AWREADY(),
+    .S_AXI_WDATA(),
+    .S_AXI_WSTRB(),
+    .S_AXI_WLAST(),
+    .S_AXI_WVALID(),
+    .S_AXI_WREADY(),
+    .S_AXI_BID(),
+    .S_AXI_BRESP(),
+    .S_AXI_BVALID(),
+    .S_AXI_BREADY(),
+    .S_AXI_ARID(),
+    .S_AXI_ARADDR(),
+    .S_AXI_ARLEN(),
+    .S_AXI_ARSIZE(),
+    .S_AXI_ARBURST(),
+    .S_AXI_ARVALID(),
+    .S_AXI_ARREADY(),
+    .S_AXI_RID(),
+    .S_AXI_RDATA(),
+    .S_AXI_RRESP(),
+    .S_AXI_RLAST(),
+    .S_AXI_RVALID(),
+    .S_AXI_RREADY(),
+    .S_AXI_INJECTSBITERR(),
+    .S_AXI_INJECTDBITERR(),
+    .S_AXI_SBITERR(),
+    .S_AXI_DBITERR(),
+    .S_AXI_RDADDRECC()
+  );
+
+// synthesis translate_on
+
+endmodule

abdelazeem201_ASIC-Design-Roadmap/cmsdk/cmsdk_mcu_defs.v

@@ -0,0 +1,61 @@
+//------------------------------------------------------------------------------
+// The confidential and proprietary information contained in this file may
+// only be used by a person authorised under and to the extent permitted
+// by a subsisting licensing agreement from ARM Limited or its affiliates.
+//
+//            (C) COPYRIGHT 2010-2015 ARM Limited or its affiliates.
+//                ALL RIGHTS RESERVED
+//
+// This entire notice must be reproduced on all copies of this file
+// and copies of this file may only be made by a person if such person is
+// permitted to do so under the terms of a subsisting license agreement
+// from ARM Limited or its affiliates.
+//
+//  Version and Release Control Information:
+//
+//  File Revision       : $Revision: 368442 $
+//  File Date           : $Date: 2017-07-25 15:07:59 +0100 (Tue, 25 Jul 2017) $
+//
+//  Release Information : Cortex-M0 DesignStart-r2p0-00rel0
+//
+//------------------------------------------------------------------------------
+// Verilog-2001 (IEEE Std 1364-2001)
+//------------------------------------------------------------------------------
+//
+//-----------------------------------------------------------------------------
+// Abstract : System configurations for Cortex-M0 example system
+//-----------------------------------------------------------------------------
+
+
+// ============= MCU System options ===========
+
+//------------------------------------------------------------------------------
+// Option for debug protocol
+// It can either be SWD (Serial Wire Debug protocol) or JTAG
+// These options specified here cannot be controlled purely by parameters
+// due to impact on I/O ports
+//
+//`define ARM_CMSDK_INCLUDE_JTAG
+
+//------------------------------------------------------------------------------
+// Memory types
+//------------------------------------------------------------------------------
+
+//`include "cmsdk_ahb_memory_models_defs.v"
+
+// Memory types used in the Example system
+
+// Memory wait state parameters - used by behaviorial model if applicable*/
+   // Boot ROM non-sequential and sequential waitstate
+`define ARM_CMSDK_BOOT_MEM_WS_N   0
+`define ARM_CMSDK_BOOT_MEM_WS_S   0
+
+   // ROM non-sequential and sequential waitstate
+`define ARM_CMSDK_ROM_MEM_WS_N    0
+`define ARM_CMSDK_ROM_MEM_WS_S    0
+
+   // RAM non-sequential and sequential waitstate
+`define ARM_CMSDK_RAM_MEM_WS_N    0
+`define ARM_CMSDK_RAM_MEM_WS_S    0
+
+

abdelazeem201_ASIC-Design-Roadmap/cmsdk/cmsdk_mcu_pin_mux.v

@@ -0,0 +1,213 @@
+//------------------------------------------------------------------------------
+// The confidential and proprietary information contained in this file may
+// only be used by a person authorised under and to the extent permitted
+// by a subsisting licensing agreement from ARM Limited or its affiliates.
+//
+//            (C) COPYRIGHT 2010-2015 ARM Limited or its affiliates.
+//                ALL RIGHTS RESERVED
+//
+// This entire notice must be reproduced on all copies of this file
+// and copies of this file may only be made by a person if such person is
+// permitted to do so under the terms of a subsisting license agreement
+// from ARM Limited or its affiliates.
+//
+//  Version and Release Control Information:
+//
+//  File Revision       : $Revision: 368442 $
+//  File Date           : $Date: 2017-07-25 15:07:59 +0100 (Tue, 25 Jul 2017) $
+//
+//  Release Information : Cortex-M0 DesignStart-r2p0-00rel0
+//
+//------------------------------------------------------------------------------
+// Verilog-2001 (IEEE Std 1364-2001)
+//------------------------------------------------------------------------------
+//
+//-----------------------------------------------------------------------------
+// Abstract : Pin multiplexing control for example Cortex-M0/Cortex-M0+
+//            microcontroller
+//-----------------------------------------------------------------------------
+//
+module cmsdk_mcu_pin_mux (
+  //-------------------------------------------
+  // I/O ports
+  //-------------------------------------------
+
+    // UART
+    output wire             uart0_rxd,
+    input  wire             uart0_txd,
+    input  wire             uart0_txen,
+    output wire             uart1_rxd,
+    input  wire             uart1_txd,
+    input  wire             uart1_txen,
+    output wire             uart2_rxd,
+    input  wire             uart2_txd,
+    input  wire             uart2_txen,
+
+    // Timer
+    output wire             timer0_extin,
+    output wire             timer1_extin,
+
+    // IO Ports
+    output wire  [15:0]     p0_in,
+    input  wire  [15:0]     p0_out,
+    input  wire  [15:0]     p0_outen,
+    input  wire  [15:0]     p0_altfunc,
+
+    output wire  [15:0]     p1_in,
+    input  wire  [15:0]     p1_out,
+    input  wire  [15:0]     p1_outen,
+    input  wire  [15:0]     p1_altfunc,
+
+    // Processor debug interface
+    output wire             i_trst_n,
+    output wire             i_swditms,
+    output wire             i_swclktck,
+    output wire             i_tdi,
+    input  wire             i_tdo,
+    input  wire             i_tdoen_n,
+    input  wire             i_swdo,
+    input  wire             i_swdoen,
+
+    // IO pads
+    inout  wire   [15:0]    P0,
+    inout  wire   [15:0]    P1,
+
+    input  wire             nTRST, // Not needed if serial-wire debug is used
+    input  wire             TDI,   // Not needed if serial-wire debug is used
+    inout  wire             SWDIOTMS,
+    input  wire             SWCLKTCK,
+    output wire             TDO);   // Not needed if serial-wire debug is used
+
+  //-------------------------------------------
+  // Internal wires
+  //-------------------------------------------
+  wire      [15:0]     p0_out_mux;
+  wire      [15:0]     p1_out_mux;
+
+  wire      [15:0]     p0_out_en_mux;
+  wire      [15:0]     p1_out_en_mux;
+
+  //-------------------------------------------
+  // Beginning of main code
+  //-------------------------------------------
+  // inputs
+  assign    uart0_rxd    = p1_in[0];
+  assign    uart1_rxd    = p1_in[2];
+  assign    uart2_rxd    = p1_in[4];
+  assign    timer0_extin = p1_in[8];
+  assign    timer1_extin = p1_in[9];
+
+  assign    p0_in        = P0;
+  assign    p1_in        = P1;
+
+  // Output function mux
+  assign    p0_out_mux    = p0_out; // No function muxing for Port 0
+
+  assign    p1_out_mux[0] =                               p1_out[0];
+  assign    p1_out_mux[1] = (p1_altfunc[1]) ? uart0_txd : p1_out[1];
+  assign    p1_out_mux[2] =                               p1_out[2];
+  assign    p1_out_mux[3] = (p1_altfunc[3]) ? uart1_txd : p1_out[3];
+  assign    p1_out_mux[4] =                               p1_out[4];
+  assign    p1_out_mux[5] = (p1_altfunc[5]) ? uart2_txd : p1_out[5];
+  assign    p1_out_mux[15:6] = p1_out[15:6];
+
+  // Output enable mux
+  assign    p0_out_en_mux   = p0_outen; // No function muxing for Port 0
+
+  assign    p1_out_en_mux[0] =                                p1_outen[0];
+  assign    p1_out_en_mux[1] = (p1_altfunc[1]) ? uart0_txen : p1_outen[1];
+  assign    p1_out_en_mux[2] =                                p1_outen[2];
+  assign    p1_out_en_mux[3] = (p1_altfunc[3]) ? uart1_txen : p1_outen[3];
+  assign    p1_out_en_mux[4] =                                p1_outen[4];
+  assign    p1_out_en_mux[5] = (p1_altfunc[5]) ? uart2_txen : p1_outen[5];
+  assign    p1_out_en_mux[15:6] = p1_outen[15:6];
+
+  // Output tristate
+  assign    P0[ 0] = p0_out_en_mux[ 0] ? p0_out_mux[ 0] : 1'bz;
+  assign    P0[ 1] = p0_out_en_mux[ 1] ? p0_out_mux[ 1] : 1'bz;
+  assign    P0[ 2] = p0_out_en_mux[ 2] ? p0_out_mux[ 2] : 1'bz;
+  assign    P0[ 3] = p0_out_en_mux[ 3] ? p0_out_mux[ 3] : 1'bz;
+  assign    P0[ 4] = p0_out_en_mux[ 4] ? p0_out_mux[ 4] : 1'bz;
+  assign    P0[ 5] = p0_out_en_mux[ 5] ? p0_out_mux[ 5] : 1'bz;
+  assign    P0[ 6] = p0_out_en_mux[ 6] ? p0_out_mux[ 6] : 1'bz;
+  assign    P0[ 7] = p0_out_en_mux[ 7] ? p0_out_mux[ 7] : 1'bz;
+  assign    P0[ 8] = p0_out_en_mux[ 8] ? p0_out_mux[ 8] : 1'bz;
+  assign    P0[ 9] = p0_out_en_mux[ 9] ? p0_out_mux[ 9] : 1'bz;
+  assign    P0[10] = p0_out_en_mux[10] ? p0_out_mux[10] : 1'bz;
+  assign    P0[11] = p0_out_en_mux[11] ? p0_out_mux[11] : 1'bz;
+  assign    P0[12] = p0_out_en_mux[12] ? p0_out_mux[12] : 1'bz;
+  assign    P0[13] = p0_out_en_mux[13] ? p0_out_mux[13] : 1'bz;
+  assign    P0[14] = p0_out_en_mux[14] ? p0_out_mux[14] : 1'bz;
+  assign    P0[15] = p0_out_en_mux[15] ? p0_out_mux[15] : 1'bz;
+
+  assign    P1[ 0] = p1_out_en_mux[ 0] ? p1_out_mux[ 0] : 1'bz;
+  assign    P1[ 1] = p1_out_en_mux[ 1] ? p1_out_mux[1] : 1'bz;
+  assign    P1[ 2] = p1_out_en_mux[ 2] ? p1_out_mux[ 2] : 1'bz;
+  assign    P1[ 3] = p1_out_en_mux[ 3] ? p1_out_mux[ 3] : 1'bz;
+  assign    P1[ 4] = p1_out_en_mux[ 4] ? p1_out_mux[ 4] : 1'bz;
+  assign    P1[ 5] = p1_out_en_mux[ 5] ? p1_out_mux[ 5] : 1'bz;
+  assign    P1[ 6] = p1_out_en_mux[ 6] ? p1_out_mux[ 6] : 1'bz;
+  assign    P1[ 7] = p1_out_en_mux[ 7] ? p1_out_mux[ 7] : 1'bz;
+  assign    P1[ 8] = p1_out_en_mux[ 8] ? p1_out_mux[ 8] : 1'bz;
+  assign    P1[ 9] = p1_out_en_mux[ 9] ? p1_out_mux[ 9] : 1'bz;
+  assign    P1[10] = p1_out_en_mux[10] ? p1_out_mux[10] : 1'bz;
+  assign    P1[11] = p1_out_en_mux[11] ? p1_out_mux[11] : 1'bz;
+  assign    P1[12] = p1_out_en_mux[12] ? p1_out_mux[12] : 1'bz;
+  assign    P1[13] = p1_out_en_mux[13] ? p1_out_mux[13] : 1'bz;
+  assign    P1[14] = p1_out_en_mux[14] ? p1_out_mux[14] : 1'bz;
+  assign    P1[15] = p1_out_en_mux[15] ? p1_out_mux[15] : 1'bz;
+
+// synopsys translate_off
+
+  // Pullup
+  pullup(P0[ 0]);
+  pullup(P0[ 1]);
+  pullup(P0[ 2]);
+  pullup(P0[ 3]);
+  pullup(P0[ 4]);
+  pullup(P0[ 5]);
+  pullup(P0[ 6]);
+  pullup(P0[ 7]);
+  pullup(P0[ 8]);
+  pullup(P0[ 9]);
+  pullup(P0[10]);
+  pullup(P0[11]);
+  pullup(P0[12]);
+  pullup(P0[13]);
+  pullup(P0[14]);
+  pullup(P0[15]);
+
+  pullup(P1[ 0]);
+  pullup(P1[ 1]);
+  pullup(P1[ 2]);
+  pullup(P1[ 3]);
+  pullup(P1[ 4]);
+  pullup(P1[ 5]);
+  pullup(P1[ 6]);
+  pullup(P1[ 7]);
+  pullup(P1[ 8]);
+  pullup(P1[ 9]);
+  pullup(P1[10]);
+  pullup(P1[11]);
+  pullup(P1[12]);
+  pullup(P1[13]);
+  pullup(P1[14]);
+  pullup(P1[15]);
+
+// synopsys translate_on
+
+  //-------------------------------------------
+  // Debug connections
+  //-------------------------------------------
+
+  assign    i_trst_n     = nTRST;
+  assign    i_tdi        = TDI;
+  assign    i_swclktck   = SWCLKTCK;
+  assign    i_swditms    = SWDIOTMS;
+
+  // Tristate buffers for debug output signals
+ // bufif1 (SWDIOTMS, i_swdo, i_swdoen);
+assign   SWDIOTMS = i_swdoen ? i_swdo : 1'bz;
+  bufif0 (TDO,      i_tdo,  i_tdoen_n);
+
+  endmodule

abdelazeem201_ASIC-Design-Roadmap/cmsdk/cmsdk_mcu_system_zed.v

@@ -0,0 +1,863 @@
+//------------------------------------------------------------------------------
+// The confidential and proprietary information contained in this file may
+// only be used by a person authorised under and to the extent permitted
+// by a subsisting licensing agreement from ARM Limited or its affiliates.
+//
+//            (C) COPYRIGHT 2010-2017 ARM Limited or its affiliates.
+//                ALL RIGHTS RESERVED
+//
+// This entire notice must be reproduced on all copies of this file
+// and copies of this file may only be made by a person if such person is
+// permitted to do so under the terms of a subsisting license agreement
+// from ARM Limited or its affiliates.
+//
+//  Version and Release Control Information:
+//
+//  File Revision       : $Revision: 368442 $
+//  File Date           : $Date: 2017-07-25 15:07:59 +0100 (Tue, 25 Jul 2017) $
+//
+//  Release Information : Cortex-M0 DesignStart-r2p0-00rel0
+//
+//------------------------------------------------------------------------------
+// Verilog-2001 (IEEE Std 1364-2001)
+//------------------------------------------------------------------------------
+//
+//-----------------------------------------------------------------------------
+// Abstract : System level design for the example Cortex-M0 system
+//-----------------------------------------------------------------------------
+// Cortex-M0 DesignStart Eval
+//
+// Supports mostly 'standard' CMDSK configuration, or an FPGA version
+// which includes additional peripherals as determined by 
+// ARM_DESIGNSTART_FPGA.
+
+// The RTL configuration differs with respect to the base BP210 version in
+// UART configuration and interrupt assignments
+
+`include "cmsdk_mcu_defs.v"
+
+module cmsdk_mcu_system #(
+  parameter BASEADDR_GPIO0  = 32'h4001_0000, // GPIO0 peripheral base address
+  parameter BASEADDR_GPIO1  = 32'h4001_1000, // GPIO1 peripheral base address
+  parameter BE              = 0,   // 1: Big endian 0: little endian
+  parameter BKPT            = 4,   // Number of breakpoint comparators
+  parameter DBG             = 1,   // Debug configuration
+  parameter NUMIRQ          = 32,  // NUM of IRQ
+  parameter SMUL            = 0,   // Multiplier configuration
+  parameter SYST            = 1,   // SysTick
+  parameter WIC             = 0,   // Wake-up interrupt controller support
+  parameter WICLINES        = 34,  // Supported WIC lines
+  parameter WPT             = 2,   // Number of DWT comparators
+
+  // Location of the System ROM Table.
+  parameter BASEADDR_SYSROMTABLE = 32'hF000_0000
+
+ )
+ (
+  input  wire               FCLK,             // Free running clock
+  input  wire               HCLK,             // AHB clock(from PMU)
+  input  wire               DCLK,             // Debug system clock (from PMU)
+  input  wire               SCLK,             // System clock
+  input  wire               HRESETn,          // AHB and System reset
+  input  wire               PORESETn,         // Power on reset
+  input  wire               DBGRESETn,        // Debug reset
+  input  wire               PCLK,             // Peripheral clock
+  input  wire               PCLKG,            // Gated Peripheral bus clock
+  input  wire               PRESETn,          // Peripheral system and APB reset
+  input  wire               PCLKEN,           // Clock divide control for AHB to APB bridge
+
+`ifdef ARM_DESIGNSTART_FPGA
+  input  wire               zbt_boot_ctrl,    // FPGA Only: Set to 1 to boot from ZBT SRAM
+`endif
+  output wire  [31:0]       HADDR,            // AHB to memory blocks - address
+  output wire   [1:0]       HTRANS,           // AHB to memory blocks - transfer ctrl
+  output wire   [2:0]       HSIZE,            // AHB to memory blocks - transfer size
+  output wire               HWRITE,           // AHB to memory blocks - write ctrl
+  output wire  [31:0]       HWDATA,           // AHB to memory blocks - write data
+  output wire               HREADY,           // AHB to memory blocks - AHB ready
+
+  output wire               flash_hsel,       // AHB to flash memory - select
+  input  wire               flash_hreadyout,  // AHB from flash blocks - ready
+  input  wire  [31:0]       flash_hrdata,     // AHB from flash blocks - read data
+  input  wire               flash_hresp,      // AHB from flash blocks - response
+
+  output wire               sram_hsel,        // AHB to SRAM - select
+  input  wire               sram_hreadyout,   // AHB from SRAM - ready
+  input  wire  [31:0]       sram_hrdata,      // AHB from SRAM - read data
+  input  wire               sram_hresp,       // AHB from SRAM - response
+
+                                              // Optional : only if BOOT_MEM_TYPE!=0
+  output wire               boot_hsel,        // AHB to boot loader - select
+  input  wire               boot_hreadyout,   // AHB from boot loader - ready
+  input  wire  [31:0]       boot_hrdata,      // AHB from boot loader - read data
+  input  wire               boot_hresp,       // AHB from boot loader - response
+
+  output wire               APBACTIVE,        // APB bus active (for clock gating of PCLKG)
+  output wire               SLEEPING,         // Processor status - sleeping
+  output wire               SLEEPDEEP,        // Processor status - deep sleep
+  output wire               SYSRESETREQ,      // Processor control - system reset request
+  output wire               WDOGRESETREQ,     // Watchdog reset request
+  output wire               LOCKUP,           // Processor status - Locked up
+  output wire               LOCKUPRESET,      // System Controller cfg - reset if lockup
+  output wire               PMUENABLE,        // System Controller cfg - Enable PMU
+
+  input  wire               nTRST,            // JTAG - Test reset (active low)
+  input  wire               SWDITMS,          // JTAG/SWD - TMS / SWD data input
+  input  wire               SWCLKTCK,         // JTAG/SWD - TCK / SWCLK
+  input  wire               TDI,              // JTAG - Test data in
+  output wire               TDO,              // JTAG - Test data out
+  output wire               nTDOEN,           // JTAG - Test data out enable (active low)
+  output wire               SWDO,             // SWD - SWD data output
+  output wire               SWDOEN,           // SWD - SWD data output enable
+  
+  input  wire               uart0_rxd,        // Uart 0 receive data
+  output wire               uart0_txd,        // Uart 0 transmit data
+  output wire               uart0_txen,       // Uart 0 transmit data enable
+  input  wire               uart1_rxd,        // Uart 1 receive data
+  output wire               uart1_txd,        // Uart 1 transmit data
+  output wire               uart1_txen,       // Uart 1 transmit data enable
+  input  wire               uart2_rxd,        // Uart 2 receive data
+  output wire               uart2_txd,        // Uart 2 transmit data
+  output wire               uart2_txen,       // Uart 2 transmit data enable
+
+  input  wire               timer0_extin,     // Timer 0 external input
+  input  wire               timer1_extin,     // Timer 1 external input
+
+  input  wire  [15:0]       p0_in,            // GPIO 0 inputs
+  output wire  [15:0]       p0_out,           // GPIO 0 outputs
+  output wire  [15:0]       p0_outen,         // GPIO 0 output enables
+  output wire  [15:0]       p0_altfunc,       // GPIO 0 alternate function (pin mux)
+  input  wire  [15:0]       p1_in,            // GPIO 1 inputs
+  output wire  [15:0]       p1_out,           // GPIO 1 outputs
+  output wire  [15:0]       p1_outen,         // GPIO 1 output enables
+  output wire  [15:0]       p1_altfunc,       // GPIO 1 alternate function (pin mux)
+
+`ifdef ARM_DESIGNSTART_FPGA
+  input  wire               spi_interrupt,    // FPGA Only: V2M-MPS2 SPI interrupt
+  input  wire               i2s_interrupt,    // FPGA Only: V2M-MPS2 I2S interrupt
+  input  wire               eth_interrupt,    // FPGA Only: V2M-MPS2 Ethernet interrupt
+  input  wire               ts_interrupt,     // FPGA Only: V2M-MPS2 Touch screen interrupt
+  input  wire               gpio2_interrupt,  // FPGA Only: V2M-MPS2 GPIO 2
+  input  wire               gpio3_interrupt,  // FPGA Only: V2M-MPS2 GPIO 3
+`endif
+  input  wire               DFTSE);           // dummy scan enable port for synthesis
+
+  // -------------------------------
+  // Internal signals
+  // -------------------------------
+  wire              HCLKSYS;        // System AHB clock
+
+  // System bus from processor
+  wire     [31:0]   cm0_haddr;
+  wire     [1:0]    cm0_htrans;
+  wire     [2:0]    cm0_hsize;
+  wire     [2:0]    cm0_hburst;
+  wire     [3:0]    cm0_hprot;
+  wire              cm0_hmaster;
+  wire              cm0_hmastlock;
+  wire              cm0_hwrite;
+  wire     [31:0]   cm0_hwdata;
+  wire     [31:0]   cm0_hrdata;
+  wire              cm0_hready;
+  wire              cm0_hresp;
+
+  // Bit band wrapper bus between CPU and the reset of the system
+  wire     [31:0]   cm_haddr;
+  wire     [1:0]    cm_htrans;
+  wire     [2:0]    cm_hsize;
+  wire     [2:0]    cm_hburst;
+  wire     [3:0]    cm_hprot;
+  wire              cm_hmastlock;
+  wire              cm_hmaster;
+  wire              cm_hwrite;
+  wire     [31:0]   cm_hwdata;
+  wire     [31:0]   cm_hrdata;
+  wire              cm_hready;
+  wire              cm_hreadyout;
+  wire              cm_hresp;
+
+  // System bus
+  wire              sys_hselm;  // Note: the sys_hselm signal is for protocol checking only.
+  wire     [31:0]   sys_haddr;
+  wire     [1:0]    sys_htrans;
+  wire     [2:0]    sys_hsize;
+  wire     [2:0]    sys_hburst;
+  wire     [3:0]    sys_hprot;
+  wire              sys_hmaster;
+  wire              sys_hmastlock;
+  wire              sys_hwrite;
+  wire     [31:0]   sys_hwdata;
+  wire     [31:0]   sys_hrdata;
+  wire              sys_hready;
+  wire              sys_hreadyout;
+  wire              sys_hresp;
+
+  wire              defslv_hsel;   // AHB default slave signals
+  wire              defslv_hreadyout;
+  wire     [31:0]   defslv_hrdata;
+  wire              defslv_hresp;
+
+  wire              apbsys_hsel;  // APB subsystem AHB interface signals
+  wire              apbsys_hreadyout;
+  wire     [31:0]   apbsys_hrdata;
+  wire              apbsys_hresp;
+
+  wire              gpio0_hsel;   // AHB GPIO bus interface signals
+  wire              gpio0_hreadyout;
+  wire     [31:0]   gpio0_hrdata;
+  wire              gpio0_hresp;
+
+  wire              gpio1_hsel;   // AHB GPIO bus interface signals
+  wire              gpio1_hreadyout;
+  wire     [31:0]   gpio1_hrdata;
+  wire              gpio1_hresp;
+
+  wire              sysctrl_hsel;  // System control bus interface signals
+  wire              sysctrl_hreadyout;
+  wire     [31:0]   sysctrl_hrdata;
+  wire              sysctrl_hresp;
+
+  // MTB (Only available to the Cortex-M0+)
+  wire              HSELMTB;
+  wire              HREADYOUTMTB;
+  wire     [31:0]   HRDATAMTB;
+  wire              HRESPMTB;
+  wire              HSELSFR;
+  wire              HSELRAM;
+
+  // System ROM Table
+  wire              sysrom_hsel;      // AHB to System ROM Table - select
+  wire              sysrom_hreadyout; // AHB from System ROM Table - ready
+  wire     [31:0]   sysrom_hrdata;    // AHB from System ROM Table - read data
+  wire              sysrom_hresp;     // AHB from System ROM Table - response
+
+  wire [1:0]        sys_hmaster_i;
+
+  // APB expansion port signals
+  wire     [11:0]   exp_paddr;
+  wire     [31:0]   exp_pwdata;
+  wire              exp_pwrite;
+  wire              exp_penable;
+
+  wire     [33:0]   WICSENSE;
+  wire CDBGPWRUPREQ;
+  wire              remap_ctrl;
+
+  // Interrupt request
+  wire     [31:0]   intisr_cm0;
+  wire              intnmi_cm0;
+  wire     [15:0]   gpio0_intr;
+  wire              gpio0_combintr;
+  wire              gpio1_combintr;
+  wire     [31:0]   apbsubsys_interrupt;
+  wire              watchdog_interrupt;
+
+     // I/O Port
+  wire              IOMATCH;
+  wire     [31:0]   IORDATA;
+  wire              IOTRANS;
+  wire              IOWRITE;
+  wire     [31:0]   IOCHECK;
+  wire     [31:0]   IOADDR;
+  wire     [ 1:0]   IOSIZE;
+  wire              IOMASTER;
+  wire              IOPRIV;
+  wire     [31:0]   IOWDATA;
+
+  // event signals
+  wire              TXEV;
+  wire              RXEV;
+
+  // SysTick timer signals
+  wire              STCLKEN;
+  wire     [25:0]   STCALIB;
+
+  // Processor debug signals
+  wire              DBGRESTART;
+  wire              DBGRESTARTED;
+  wire              EDBGRQ;
+
+  // Processor status
+  wire              HALTED;
+  wire              SPECHTRANS;
+  wire              CODENSEQ;
+  wire              SHAREABLE;
+
+// Only used in FPGA configuration, tie-off in RTL version
+`ifndef ARM_DESIGNSTART_FPGA
+  wire       spi_interrupt   = 1'b0;
+  wire       i2s_interrupt   = 1'b0;
+  wire       eth_interrupt   = 1'b0;
+  wire       ts_interrupt    = 1'b0;
+  wire       gpio2_interrupt = 1'b0;
+  wire       gpio3_interrupt = 1'b0;
+`endif
+    
+  assign   HCLKSYS  = HCLK;
+
+
+//instantiate the DesignStart Cortex M0 Integration Layer
+CORTEXM0INTEGRATION
+u_cortexm0integration
+(
+  // CLOCK AND RESETS
+  .FCLK          (FCLK),
+  .SCLK          (SCLK),
+  .HCLK          (HCLK),
+  .DCLK          (DCLK),
+  .PORESETn      (PORESETn),
+  .DBGRESETn     (DBGRESETn),
+  .HRESETn       (HRESETn),
+  .SWCLKTCK      (SWCLKTCK),
+  .nTRST         (nTRST),
+
+  // AHB-LITE MASTER PORT
+  .HADDR         (cm0_haddr),
+  .HBURST        (cm0_hburst),
+  .HMASTLOCK     (cm0_hmastlock),
+  .HPROT         (cm0_hprot),
+  .HSIZE         (cm0_hsize),
+  .HTRANS        (cm0_htrans),
+  .HWDATA        (cm0_hwdata),
+  .HWRITE        (cm0_hwrite),
+  .HRDATA        (cm0_hrdata),
+  .HREADY        (cm0_hready),
+  .HRESP         (cm0_hresp),
+  .HMASTER       (),
+
+  // CODE SEQUENTIALITY AND SPECULATION
+  .CODENSEQ      (CODENSEQ),
+  .CODEHINTDE    (),
+  .SPECHTRANS    (),
+
+  // DEBUG
+  .SWDITMS       (SWDITMS),
+  .TDI           (1'b0),
+  .SWDO          (SWDO),
+  .SWDOEN        (SWDOEN),
+  .TDO           (TDO),
+  .nTDOEN        (nTDOEN),
+  .DBGRESTART    (1'b0),
+  .DBGRESTARTED  (DBGRESTARTED),
+  .EDBGRQ        (1'b0),
+  .HALTED        (HALTED),
+
+  // MISC
+  .NMI            (1'b0),        // Non-maskable interrupt input
+  .IRQ            (32'h00000000),        // Interrupt request inputs
+  .TXEV           (TXEV),              // Event output (SEV executed)
+  .RXEV           (1'b0),              // Event input
+  .LOCKUP         (LOCKUP),            // Core is locked-up
+  .SYSRESETREQ    (SYSRESETREQ),       // System reset request
+  .STCALIB        (STCALIB),           // SysTick calibration register value
+  .STCLKEN        (STCLKEN),           // SysTick SCLK clock enable
+  .IRQLATENCY     (8'h00),
+  .ECOREVNUM      (28'haa),
+
+  // POWER MANAGEMENT
+  .GATEHCLK      (),
+  .SLEEPING      (SLEEPING),           // Core and NVIC sleeping
+  .SLEEPDEEP     (SLEEPDEEP),
+  .WAKEUP        (),
+  .WICSENSE      (WICSENSE),
+  .SLEEPHOLDREQn (1'b1),
+  .SLEEPHOLDACKn (),
+  .WICENREQ      (1'b0),
+  .WICENACK      (),
+  .CDBGPWRUPREQ  (CDBGPWRUPREQ),
+  .CDBGPWRUPACK  (CDBGPWRUPREQ),
+
+  // SCAN IO
+  .SE            (1'b1),
+  .RSTBYPASS     (1'b0)
+);
+
+// Force connect some signals to 0 or 1
+   assign        cm0_hmaster  = 1'b0;
+
+
+  // Unused debug feature
+  assign   DBGRESTART = 1'b0; // multi-core synchronous restart from halt
+  assign   EDBGRQ     = 1'b0; // multi-core synchronous halt request
+
+  assign   RXEV = 1'b0;
+
+  // No MTB in Cortex-M0
+  assign   HRDATAMTB    = {32{1'b0}};
+  assign   HREADYOUTMTB = 1'b0;
+  assign   HRESPMTB     = 1'b0;
+
+  // -------------------------------
+  // AHB system
+  // -------------------------------
+
+  // No bitband wrapper, direct signal connections
+  assign   cm_haddr[31:0]  = cm0_haddr[31:0];
+  assign   cm_htrans[1:0]  = cm0_htrans[1:0];
+  assign   cm_hsize[2:0]   = cm0_hsize[2:0];
+  assign   cm_hburst[2:0]  = cm0_hburst[2:0];
+  assign   cm_hprot[3:0]   = cm0_hprot[3:0];
+  assign   cm_hmaster      = cm0_hmaster;
+  assign   cm_hmastlock    = cm0_hmastlock;
+  assign   cm_hwrite       = cm0_hwrite;
+  assign   cm_hwdata[31:0] = cm0_hwdata[31:0];
+  assign   cm_hready       = cm0_hready;
+  assign   cm0_hrdata[31:0]= cm_hrdata[31:0];
+  assign   cm0_hready      = cm_hreadyout;
+  assign   cm0_hresp       = cm_hresp;
+
+  // No DMA controller - no need to have master multiplexer
+  // direct connection from cpu to system bus if DMA is not presented
+  assign   sys_haddr[31:0] = cm_haddr[31:0];
+  assign   sys_htrans[1:0] = cm_htrans[1:0];
+  assign   sys_hsize[2:0]  = cm_hsize[2:0];
+  assign   sys_hburst[2:0] = cm_hburst[2:0];
+  assign   sys_hprot[3:0]  = cm_hprot[3:0];
+  assign   sys_hmaster     = cm_hmaster;
+  assign   sys_hmastlock   = cm_hmastlock;
+  assign   sys_hwrite      = cm_hwrite;
+  assign   sys_hwdata[31:0]= cm_hwdata[31:0];
+  assign   sys_hready      = cm_hready;
+  assign   cm_hrdata[31:0] = sys_hrdata[31:0];
+  assign   cm_hreadyout    = sys_hreadyout;
+  assign   cm_hresp        = sys_hresp;
+  assign   sys_hmaster_i   = 2'b00;
+
+  // AHB address decode
+  cmsdk_mcu_addr_decode #(
+     .BASEADDR_GPIO0       (BASEADDR_GPIO0),
+     .BASEADDR_GPIO1       (BASEADDR_GPIO1),
+     .BOOT_LOADER_PRESENT  (1'b0),
+     .BASEADDR_SYSROMTABLE (BASEADDR_SYSROMTABLE)
+    )
+    u_addr_decode (
+    // System Address
+    .haddr         (sys_haddr),
+    .remap_ctrl    (remap_ctrl),
+`ifdef ARM_DESIGNSTART_FPGA
+    .zbt_boot_ctrl (zbt_boot_ctrl),
+`endif
+    .boot_hsel     (boot_hsel),
+    .flash_hsel    (flash_hsel),
+    .sram_hsel     (sram_hsel),
+    .apbsys_hsel   (apbsys_hsel),
+    .gpio0_hsel    (gpio0_hsel),
+    .gpio1_hsel    (gpio1_hsel),
+    .sysctrl_hsel  (sysctrl_hsel),
+    .sysrom_hsel   (sysrom_hsel),
+    .defslv_hsel   (defslv_hsel),
+    .hselmtb       (HSELMTB),
+    .hselram       (HSELRAM),
+    .hselsfr       (HSELSFR)
+  );
+
+
+  // AHB slave multiplexer
+  cmsdk_ahb_slave_mux #(
+    .PORT0_ENABLE  (1),
+    .PORT1_ENABLE  (1),
+    .PORT2_ENABLE  (0),
+    .PORT3_ENABLE  (1),
+    .PORT4_ENABLE  (1),
+    .PORT5_ENABLE  (1),
+    .PORT6_ENABLE  (1),
+    .PORT7_ENABLE  (1),
+    .PORT8_ENABLE  (1),
+    .PORT9_ENABLE  (0),
+    .DW            (32)
+    )
+    u_ahb_slave_mux_sys_bus (
+    .HCLK         (HCLKSYS),
+    .HRESETn      (HRESETn),
+    .HREADY       (sys_hready),
+    .HSEL0        (flash_hsel),      // Input Port 0
+    .HREADYOUT0   (flash_hreadyout),
+    .HRESP0       (flash_hresp),
+    .HRDATA0      (flash_hrdata),
+    .HSEL1        (sram_hsel),       // Input Port 1
+    .HREADYOUT1   (sram_hreadyout),
+    .HRESP1       (sram_hresp),
+    .HRDATA1      (sram_hrdata),
+    .HSEL2        (boot_hsel),       // Input Port 2
+    .HREADYOUT2   (boot_hreadyout),
+    .HRESP2       (boot_hresp),
+    .HRDATA2      (boot_hrdata),
+    .HSEL3        (defslv_hsel),     // Input Port 3
+    .HREADYOUT3   (defslv_hreadyout),
+    .HRESP3       (defslv_hresp),
+    .HRDATA3      (defslv_hrdata),
+    .HSEL4        (apbsys_hsel),     // Input Port 4
+    .HREADYOUT4   (apbsys_hreadyout),
+    .HRESP4       (apbsys_hresp),
+    .HRDATA4      (apbsys_hrdata),
+    .HSEL5        (gpio0_hsel),      // Input Port 5
+    .HREADYOUT5   (gpio0_hreadyout),
+    .HRESP5       (gpio0_hresp),
+    .HRDATA5      (gpio0_hrdata),
+    .HSEL6        (gpio1_hsel),      // Input Port 6
+    .HREADYOUT6   (gpio1_hreadyout),
+    .HRESP6       (gpio1_hresp),
+    .HRDATA6      (gpio1_hrdata),
+    .HSEL7        (sysctrl_hsel),    // Input Port 7
+    .HREADYOUT7   (sysctrl_hreadyout),
+    .HRESP7       (sysctrl_hresp),
+    .HRDATA7      (sysctrl_hrdata),
+    .HSEL8        (sysrom_hsel),     // Input Port 8
+    .HREADYOUT8   (sysrom_hreadyout),
+    .HRESP8       (sysrom_hresp),
+    .HRDATA8      (sysrom_hrdata),
+    .HSEL9        (HSELMTB),         // Input Port 9
+    .HREADYOUT9   (HREADYOUTMTB),
+    .HRESP9       (HRESPMTB),
+    .HRDATA9      (HRDATAMTB),
+
+    .HREADYOUT    (sys_hreadyout),   // Outputs
+    .HRESP        (sys_hresp),
+    .HRDATA       (sys_hrdata)
+  );
+
+  // Default slave
+  cmsdk_ahb_default_slave u_ahb_default_slave_1 (
+    .HCLK         (HCLKSYS),
+    .HRESETn      (HRESETn),
+    .HSEL         (defslv_hsel),
+    .HTRANS       (sys_htrans),
+    .HREADY       (sys_hready),
+    .HREADYOUT    (defslv_hreadyout),
+    .HRESP        (defslv_hresp)
+  );
+
+  assign   defslv_hrdata = 32'h00000000; // Default slave do not have read data
+
+
+  // -------------------------------
+  // System ROM Table
+  // -------------------------------
+  cmsdk_ahb_cs_rom_table
+   #(//.JEPID                             (),
+     //.JEPCONTINUATION                   (),
+     //.PARTNUMBER                        (),
+     //.REVISION                          (),
+     .BASE              (BASEADDR_SYSROMTABLE),
+     // Entry 0 = Cortex-M0+ Processor
+     .ENTRY0BASEADDR    (32'hE00FF000),
+     .ENTRY0PRESENT     (1'b1),
+     // Entry 1 = CoreSight MTB-M0+
+     .ENTRY1BASEADDR    (32'hF0200000),
+     .ENTRY1PRESENT     (0))
+    u_system_rom_table
+    (//Outputs
+     .HRDATA                            (sysrom_hrdata[31:0]),
+     .HREADYOUT                         (sysrom_hreadyout),
+     .HRESP                             (sysrom_hresp),
+     //Inputs
+     .HCLK                              (HCLKSYS),
+     .HSEL                              (sysrom_hsel),
+     .HADDR                             (sys_haddr[31:0]),
+     .HBURST                            (sys_hburst[2:0]),
+     .HMASTLOCK                         (sys_hmastlock),
+     .HPROT                             (sys_hprot[3:0]),
+     .HSIZE                             (sys_hsize[2:0]),
+     .HTRANS                            (sys_htrans[1:0]),
+     .HWDATA                            (sys_hwdata[31:0]),
+     .HWRITE                            (sys_hwrite),
+     .HREADY                            (sys_hready),
+     .ECOREVNUM                         (4'h0));
+
+  // -------------------------------
+  // Peripherals
+  // -------------------------------
+
+  cmsdk_mcu_sysctrl #(.BE (BE))
+    u_cmsdk_mcu_sysctrl
+  (
+   // AHB Inputs
+    .HCLK         (HCLKSYS),
+    .HRESETn      (HRESETn),
+    .FCLK         (FCLK),
+    .PORESETn     (PORESETn),
+    .HSEL         (sysctrl_hsel),
+    .HREADY       (sys_hready),
+    .HTRANS       (sys_htrans),
+    .HSIZE        (sys_hsize),
+    .HWRITE       (sys_hwrite),
+    .HADDR        (sys_haddr[11:0]),
+    .HWDATA       (sys_hwdata),
+   // AHB Outputs
+    .HREADYOUT    (sysctrl_hreadyout),
+    .HRESP        (sysctrl_hresp),
+    .HRDATA       (sysctrl_hrdata),
+   // Reset information
+    .SYSRESETREQ  (SYSRESETREQ),
+    .WDOGRESETREQ (WDOGRESETREQ),
+    .LOCKUP       (LOCKUP),
+    // Engineering-change-order revision bits
+    .ECOREVNUM    (4'h0),
+   // System control signals
+    .REMAP        (remap_ctrl),
+    .PMUENABLE    (PMUENABLE),
+    .LOCKUPRESET  (LOCKUPRESET)
+   );
+
+
+  // GPIO is driven from the AHB
+  cmsdk_ahb_gpio #(
+    .ALTERNATE_FUNC_MASK     (16'h0000), // No pin muxing for Port #0
+    .ALTERNATE_FUNC_DEFAULT  (16'h0000), // All pins default to GPIO
+    .BE                      (BE)
+    )
+    u_ahb_gpio_0  (
+   // AHB Inputs
+    .HCLK         (HCLKSYS),
+    .HRESETn      (HRESETn),
+    .FCLK         (FCLK),
+    .HSEL         (gpio0_hsel),
+    .HREADY       (sys_hready),
+    .HTRANS       (sys_htrans),
+    .HSIZE        (sys_hsize),
+    .HWRITE       (sys_hwrite),
+    .HADDR        (sys_haddr[11:0]),
+    .HWDATA       (sys_hwdata),
+   // AHB Outputs
+    .HREADYOUT    (gpio0_hreadyout),
+    .HRESP        (gpio0_hresp),
+    .HRDATA       (gpio0_hrdata),
+
+    .ECOREVNUM    (4'h0),// Engineering-change-order revision bits
+
+    .PORTIN       (p0_in),   // GPIO Interface inputs
+    .PORTOUT      (p0_out),  // GPIO Interface outputs
+    .PORTEN       (p0_outen),
+    .PORTFUNC     (p0_altfunc), // Alternate function control
+
+    .GPIOINT      (gpio0_intr[15:0]),  // Interrupt outputs
+    .COMBINT      (gpio0_combintr)
+  );
+
+
+  cmsdk_ahb_gpio #(
+    .ALTERNATE_FUNC_MASK     (16'h002A), // pin muxing for Port #1
+    .ALTERNATE_FUNC_DEFAULT  (16'h0000), // All pins default to GPIO
+    .BE                      (BE)
+    )
+    u_ahb_gpio_1  (
+   // AHB Inputs
+    .HCLK         (HCLKSYS),
+    .HRESETn      (HRESETn),
+    .FCLK         (FCLK),
+    .HSEL         (gpio1_hsel),
+    .HREADY       (sys_hready),
+    .HTRANS       (sys_htrans),
+    .HSIZE        (sys_hsize),
+    .HWRITE       (sys_hwrite),
+    .HADDR        (sys_haddr[11:0]),
+    .HWDATA       (sys_hwdata),
+   // AHB Outputs
+    .HREADYOUT    (gpio1_hreadyout),
+    .HRESP        (gpio1_hresp),
+    .HRDATA       (gpio1_hrdata),
+
+    .ECOREVNUM    (4'h0),// Engineering-change-order revision bits
+
+    .PORTIN       (p1_in),   // GPIO Interface inputs
+    .PORTOUT      (p1_out),  // GPIO Interface outputs
+    .PORTEN       (p1_outen),
+    .PORTFUNC     (p1_altfunc), // Alternate function control
+
+    .GPIOINT      (),  // Interrupt outputs
+    .COMBINT      (gpio1_combintr)
+  );
+
+  assign IOMATCH = 1'b0;
+  assign IORDATA = {32{(1'b0)}};
+
+  // APB subsystem for timers, UARTs
+  cmsdk_apb_subsystem #(
+    .APB_EXT_PORT12_ENABLE   (0),
+    .APB_EXT_PORT13_ENABLE   (0),
+    .APB_EXT_PORT14_ENABLE   (0),
+    .APB_EXT_PORT15_ENABLE   (0),
+    .INCLUDE_IRQ_SYNCHRONIZER(0),
+    .INCLUDE_APB_TEST_SLAVE  (0),
+    .INCLUDE_APB_TIMER0      (0),  // Include simple timer #0
+    .INCLUDE_APB_TIMER1      (0),  // Include simple timer #1
+    .INCLUDE_APB_DUALTIMER0  (0),  // Include dual timer module
+    .INCLUDE_APB_UART0       (1),  // Include simple UART #0
+    .INCLUDE_APB_UART1       (0),  // Include simple UART #1
+    .INCLUDE_APB_UART2       (0),  // Include simple UART #2.
+    .INCLUDE_APB_WATCHDOG    (0),  // Include APB watchdog module
+    .BE                      (BE)
+     )
+  u_apb_subsystem(
+
+  // AHB interface for AHB to APB bridge
+    .HCLK          (HCLKSYS),
+    .HRESETn       (HRESETn),
+
+    .HSEL          (apbsys_hsel),
+    .HADDR         (sys_haddr[15:0]),
+    .HTRANS        (sys_htrans[1:0]),
+    .HWRITE        (sys_hwrite),
+    .HSIZE         (sys_hsize),
+    .HPROT         (sys_hprot),
+    .HREADY        (sys_hready),
+    .HWDATA        (sys_hwdata[31:0]),
+
+    .HREADYOUT     (apbsys_hreadyout),
+    .HRDATA        (apbsys_hrdata),
+    .HRESP         (apbsys_hresp),
+
+  // APB clock and reset
+    .PCLK          (PCLK),
+    .PCLKG         (PCLKG),
+    .PCLKEN        (PCLKEN),
+    .PRESETn       (PRESETn),
+
+  // APB extension ports
+    .PADDR         (exp_paddr[11:0]),
+    .PWRITE        (exp_pwrite),
+    .PWDATA        (exp_pwdata[31:0]),
+    .PENABLE       (exp_penable),
+
+    .ext12_psel    (),
+    .ext13_psel    (),
+    .ext14_psel    (),
+    .ext15_psel    (),
+
+  // Input from APB devices on APB expansion ports
+    .ext12_prdata  (32'h00000000),
+    .ext12_pready  (1'b1),
+    .ext12_pslverr (1'b0),
+
+    .ext13_prdata  (32'h00000000),
+    .ext13_pready  (1'b1),
+    .ext13_pslverr (1'b0),
+
+    .ext14_prdata  (32'h00000000),
+    .ext14_pready  (1'b1),
+    .ext14_pslverr (1'b0),
+
+    .ext15_prdata  (32'h00000000),
+    .ext15_pready  (1'b1),
+    .ext15_pslverr (1'b0),
+
+    .APBACTIVE     (APBACTIVE),  // Status Output for clock gating
+
+  // Peripherals
+    // UART
+    .uart0_rxd     (uart0_rxd),
+    .uart0_txd     (uart0_txd),
+    .uart0_txen    (uart0_txen),
+
+    .uart1_rxd     (uart1_rxd),
+    .uart1_txd     (uart1_txd),
+    .uart1_txen    (uart1_txen),
+
+    .uart2_rxd     (uart2_rxd),
+    .uart2_txd     (uart2_txd),
+    .uart2_txen    (uart2_txen),
+
+    // Timer
+    .timer0_extin  (timer0_extin),
+    .timer1_extin  (timer1_extin),
+
+  // Interrupt outputs
+    .apbsubsys_interrupt (apbsubsys_interrupt),
+    .watchdog_interrupt  (watchdog_interrupt),
+   // reset output
+    .watchdog_reset      (WDOGRESETREQ)
+  );
+
+  // Connect system bus to external
+  assign   HADDR  = sys_haddr;
+  assign   HTRANS = sys_htrans;
+  assign   HSIZE  = sys_hsize;
+  assign   HWRITE = sys_hwrite;
+  assign   HWDATA = sys_hwdata;
+  assign   HREADY = sys_hready;
+
+  // -------------------------------
+  // Interrupt assignment
+  // -------------------------------
+  // Changed from CMSDK:
+  // IRQ[12] is used as combined UART overflow interrupt
+  
+  assign intnmi_cm0        = watchdog_interrupt;
+  assign intisr_cm0[ 5: 0] = apbsubsys_interrupt[ 5: 0];
+  assign intisr_cm0[ 6]    = apbsubsys_interrupt[ 6]   | gpio0_combintr | gpio2_interrupt;
+  assign intisr_cm0[ 7]    = apbsubsys_interrupt[ 7]   | gpio1_combintr | gpio3_interrupt;
+  assign intisr_cm0[10: 8] = apbsubsys_interrupt[10: 8];
+  assign intisr_cm0[11]    = apbsubsys_interrupt[11]   | spi_interrupt; 
+  assign intisr_cm0[12]    = |apbsubsys_interrupt[14: 12]; // UART Overflow interrupts
+  assign intisr_cm0[13]    = eth_interrupt;                // V2M-MPS2 Ethernet
+  assign intisr_cm0[14]    = i2s_interrupt;                // V2M-MPS2 Ethernet
+  assign intisr_cm0[15]    = apbsubsys_interrupt[15]   | ts_interrupt; // Also DMA if integrated
+  assign intisr_cm0[31:16] = apbsubsys_interrupt[31:16]| gpio0_intr;
+
+  // -------------------------------
+  // SysTick signals
+  // -------------------------------
+  cmsdk_mcu_stclkctrl
+   #(.DIV_RATIO (18'd01000))
+   u_cmsdk_mcu_stclkctrl (
+    .FCLK      (FCLK),
+    .SYSRESETn (HRESETn),
+
+    .STCLKEN   (STCLKEN),
+    .STCALIB   (STCALIB)
+    );
+
+ // --------------------------------------------------------------------------------
+ // Verification components
+ // --------------------------------------------------------------------------------
+`ifdef ARM_AHB_ASSERT_ON
+  // AHB protocol checker for process bus
+  AhbLitePC #(
+      .ADDR_WIDTH                           (32),
+      .DATA_WIDTH                           (32),
+      .BIG_ENDIAN                           (BE),
+      .MASTER_TO_INTERCONNECT               ( 1),
+      .EARLY_BURST_TERMINATION              ( 0),
+      // Property type (0=prove, 1=assume, 2=ignore)
+      .MASTER_REQUIREMENT_PROPTYPE          ( 0),
+      .MASTER_RECOMMENDATION_PROPTYPE       ( 0),
+      .MASTER_XCHECK_PROPTYPE               ( 0),
+      .SLAVE_REQUIREMENT_PROPTYPE           ( 0),
+      .SLAVE_RECOMMENDATION_PROPTYPE        ( 0),
+      .SLAVE_XCHECK_PROPTYPE                ( 0),
+      .INTERCONNECT_REQUIREMENT_PROPTYPE    ( 0),
+      .INTERCONNECT_RECOMMENDATION_PROPTYPE ( 0),
+      .INTERCONNECT_XCHECK_PROPTYPE         ( 0)
+   ) u_AhbLitePC_processor
+  (
+   // clock
+   .HCLK         (HCLKSYS),
+
+   // active low reset
+   .HRESETn      (HRESETn),
+
+   // Main Master signals
+   .HADDR        (cm0_haddr),
+   .HTRANS       (cm0_htrans),
+   .HWRITE       (cm0_hwrite),
+   .HSIZE        (cm0_hsize),
+   .HBURST       (cm0_hburst),
+   .HPROT        (cm0_hprot),
+   .HWDATA       (cm0_hwdata),
+
+   // Main Decoder signals
+   .HSELx        (1'bx), // Ignored for this instance
+
+   // Main Slave signals
+   .HRDATA       (cm0_hrdata),
+   .HREADY       (cm0_hready),
+   .HREADYOUT    (1'bx),  // Ignored for this instance
+   .HRESP        (cm0_hresp),
+
+   // HMASTER, // NOTE: not used
+
+   .HMASTLOCK    (cm0_hmastlock)
+   );
+`endif
+
+endmodule

abdelazeem201_ASIC-Design-Roadmap/cmsdk/fpga_ram_top.v

@@ -0,0 +1,66 @@
+//-----------------------------------------------------------------------------
+//  Abstract : FPGA BlockRam/OnChip RAM
+// ----------------------------------------------------------------------------
+
+module fpga_ram_top #(
+// --------------------------------------------------------------------------
+// Parameter Declarations
+// --------------------------------------------------------------------------
+  parameter AW = 16,
+  parameter filename = ""
+)
+ (
+  // Inputs
+  input  wire          CLK,
+  input  wire [AW-1:2] ADDR,
+  input  wire [31:0]   WDATA,
+  input  wire [3:0]    WREN,
+  input  wire          CS,
+
+  // Outputs
+  output wire [31:0]   RDATA
+ );
+
+blk_mem_zed //#(
+  //.filename("mem0.coe"))
+  blk_mem0 
+  (
+  .clka (CLK),
+  .ena  (CS),
+  .wea  (WREN[0]),
+  .addra(ADDR[15:2]),
+  .dina (WDATA[7:0]),
+  .douta(RDATA[7:0])
+);
+blk_mem_zed// #(
+ // .filename("mem1.coe"))
+  blk_mem1 (
+  .clka (CLK),
+  .ena  (CS),
+  .wea  (WREN[1]),
+  .addra(ADDR[15:2]),
+  .dina (WDATA[15:8]),
+  .douta(RDATA[15:8])
+);
+blk_mem_zed //#(
+ // .filename("mem2.coe"))
+  blk_mem2 (
+  .clka (CLK),
+  .ena  (CS),
+  .wea  (WREN[2]),
+  .addra(ADDR[15:2]),
+  .dina (WDATA[23:16]),
+  .douta(RDATA[23:16])
+);
+blk_mem_zed //#(
+  //.filename("mem3.coe"))
+  blk_mem3 (
+  .clka (CLK),
+  .ena  (CS),
+  .wea  (WREN[3]),
+  .addra(ADDR[15:2]),
+  .dina (WDATA[31:24]),
+  .douta(RDATA[31:24])
+);
+
+endmodule

abdelazeem201_ASIC-Design-Roadmap/cmsdk/fpga_rom_top.v

@@ -0,0 +1,70 @@
+//-----------------------------------------------------------------------------
+//  Abstract : FPGA BlockRam/OnChip ROM
+// ----------------------------------------------------------------------------
+
+module fpga_rom_top #(
+// --------------------------------------------------------------------------
+// Parameter Declarations
+// --------------------------------------------------------------------------
+  parameter AW = 16,
+  parameter filename = "image.hex"
+)
+ (
+  // Inputs
+  input  wire          CLK,
+  input  wire [AW-1:2] ADDR,
+  input  wire [31:0]   WDATA,
+  input  wire [3:0]    WREN,
+  input  wire          CS,
+
+  // Outputs
+  output wire [31:0]   RDATA
+ );
+
+blk_mem_zed 
+#(
+  .filename("mem0.mif"))
+  blk_mem0 
+  (
+  .clka (CLK),
+  .ena  (1'b1),
+  .wea  (WREN[0]),
+  .addra(ADDR[15:2]),
+  .dina (WDATA[7:0]),
+  .douta(RDATA[7:0])
+);
+blk_mem_zed 
+#(
+  .filename("mem1.mif"))
+  blk_mem1 (
+  .clka (CLK),
+  .ena  (1'b1),
+  .wea  (WREN[1]),
+  .addra(ADDR[15:2]),
+  .dina (WDATA[15:8]),
+  .douta(RDATA[15:8])
+);
+blk_mem_zed 
+#(
+  .filename("mem2.mif"))
+  blk_mem2 (
+  .clka (CLK),
+  .ena  (1'b1),
+  .wea  (WREN[2]),
+  .addra(ADDR[15:2]),
+  .dina (WDATA[23:16]),
+  .douta(RDATA[23:16])
+);
+blk_mem_zed 
+#(
+  .filename("mem3.mif"))
+  blk_mem3 (
+  .clka (CLK),
+  .ena  (1'b1),
+  .wea  (WREN[3]),
+  .addra(ADDR[15:2]),
+  .dina (WDATA[31:24]),
+  .douta(RDATA[31:24])
+);
+
+endmodule

abdelazeem201_ASIC-Design-Roadmap/cmsdk/led_1second.v

@@ -0,0 +1,108 @@
+// 1second_test 
+`timescale 1 ns / 1 ns
+
+module led_1second(
+             clk,
+             reset,
+             led_a
+             );
+input  clk;
+input  reset;
+output led_a;   
+
+reg reg_led_a;
+
+
+reg reg_1s_flag;
+reg reg_ms_flag;
+reg reg_us_flag;
+//reg reg_1m_flag;
+//reg [5:0] reg_s_count;
+reg [9:0] reg_ms_count;
+reg [9:0] reg_us_count;
+reg [5:0] reg_clk_count;
+
+//��������������������������������������������begin ���´���Ĺ��ܣ�ʵ��1���Ӽ�����������һ��һ���ӱ�־��������������������������������
+
+//clk�����������Ƶ�50 ��ʱ�ӣ�50MHZ��ʱ�ӣ�������20ns��ʱ���㣬Ҳ����1000ms = 1΢��
+always @(posedge clk or negedge reset)
+begin
+  if (~reset)
+     reg_clk_count <= 6'b00000;
+  else  if( reg_clk_count == 49) reg_clk_count <= 6'b00000;
+  else  reg_clk_count <= reg_clk_count + 1;
+end
+
+//����1us��־ reg_us_flag
+always @(posedge clk or negedge reset)
+begin
+  if (~reset)
+     reg_us_flag <= 0;
+  else  if( reg_clk_count == 49) reg_us_flag <= 1;
+  else  reg_us_flag <= 0;
+end
+//us �����������Ƶ�1000us ʱ���㣬Ҳ����1����
+always @(posedge clk or negedge reset)
+begin
+  if (~reset)
+     reg_us_count <= 0;
+  else  if( reg_us_count == 999) reg_us_count <= 10'h000;
+  else  if( reg_us_flag) reg_us_count <= reg_us_count + 1;
+end
+
+//����1ms��־ reg_ms_flag
+always @(posedge clk or negedge reset)
+begin
+  if (~reset)
+     reg_ms_flag <= 0;
+  else  if( reg_us_count == 999) reg_ms_flag <= 1;
+  else  reg_ms_flag <= 0;
+end
+//ms �����������Ƶ�1000ms ʱ���㣬Ҳ����1����
+always @(posedge clk or negedge reset)
+begin
+  if (~reset)
+     reg_ms_count <= 0;
+  else  if( reg_ms_count == 999) reg_ms_count <= 10'h000;
+  else  if( reg_ms_flag) reg_ms_count <= reg_ms_count + 1;
+end
+
+//����1s ��־reg_1s_flag
+always @(posedge clk or negedge reset)
+begin
+  if (~reset)
+     reg_1s_flag <= 0;
+  else  if( reg_ms_count == 999) reg_1s_flag <= 1;
+  else  reg_1s_flag <= 0;
+end
+
+
+always @(posedge clk or negedge reset)
+begin
+  if (~reset)
+     reg_led_a <= 0;
+  else  if( reg_1s_flag == 1) reg_led_a <= ~reg_led_a;
+  else  reg_led_a <= reg_led_a;
+end
+
+assign led_a = reg_led_a ;
+
+
+endmodule
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

abdelazeem201_ASIC-Design-Roadmap/cmsdk/tb_cmsdk_mcu_zed.v

@@ -0,0 +1,161 @@
+//------------------------------------------------------------------------------
+// The confidential and proprietary information contained in this file may
+// only be used by a person authorised under and to the extent permitted
+// by a subsisting licensing agreement from ARM Limited or its affiliates.
+//
+//            (C) COPYRIGHT 2010-2015 ARM Limited or its affiliates.
+//                ALL RIGHTS RESERVED
+//
+// This entire notice must be reproduced on all copies of this file
+// and copies of this file may only be made by a person if such person is
+// permitted to do so under the terms of a subsisting license agreement
+// from ARM Limited or its affiliates.
+//
+//  Version and Release Control Information:
+//
+//  File Revision       : $Revision: 368442 $
+//  File Date           : $Date: 2017-07-25 15:07:59 +0100 (Tue, 25 Jul 2017) $
+//
+//  Release Information : Cortex-M0 DesignStart-r2p0-00rel0
+//
+//------------------------------------------------------------------------------
+// Verilog-2001 (IEEE Std 1364-2001)
+//------------------------------------------------------------------------------
+//
+//-----------------------------------------------------------------------------
+// Abstract : Testbench for the Cortex-M0 example system
+//-----------------------------------------------------------------------------
+//
+`timescale 1ns/1ps
+`include "cmsdk_mcu_defs.v"
+
+module tb_cmsdk_mcu_zed;
+
+  reg        XTAL1;   // crystal pin 1
+  wire        XTAL2;   // crystal pin 2
+  reg        NRST;    // active low reset
+
+  wire [15:0] P0;      // Port 0
+  wire [15:0] P1;      // Port 1
+
+
+  //Debug tester signals
+  wire        nTRST;
+  wire        TDI;
+  wire        SWDIOTMS;
+  wire        SWCLKTCK;
+  wire        TDO;
+
+  wire        PCLK;          // Clock for UART capture device
+  wire [5:0]  debug_command; // used to drive debug tester
+  wire        debug_running; // indicate debug test is running
+  wire        debug_err;     // indicate debug test has error
+
+  wire        debug_test_en; // To enable the debug tester connection to MCU GPIO P0
+                             // This signal is controlled by software,
+                             // Use "UartPutc((char) 0x1B)" to send ESCAPE code to start
+                             // the command, use "UartPutc((char) 0x11)" to send debug test
+                             // enable command, use "UartPutc((char) 0x12)" to send debug test
+                             // disable command. Refer to tb_uart_capture.v file for detail
+
+  parameter BE              = 0;   // Big or little endian
+
+  parameter BKPT            = 4;   // Number of breakpoint comparators
+  parameter DBG             = 1;   // Debug configuration
+  parameter NUMIRQ          = 32;  // NUM of IRQ
+  parameter SMUL            = 0;   // Multiplier configuration
+  parameter SYST            = 1;   // SysTick
+  parameter WIC             = 1;   // Wake-up interrupt controller support
+  parameter WICLINES        = 34;  // Supported WIC lines
+  parameter WPT             = 2;   // Number of DWT comparators
+
+ // --------------------------------------------------------------------------------
+ // Cortex-M0/Cortex-M0+ Microcontroller
+ // --------------------------------------------------------------------------------
+          wire uart0_txd    ;
+ // cmsdk_mcu
+  cmsdk_mcu_zed
+   #(.BE               (BE),
+     .BKPT             (BKPT),          // Number of breakpoint comparators
+     .DBG              (DBG),           // Debug configuration
+     .NUMIRQ           (NUMIRQ),        // NUMIRQ
+     .SMUL             (SMUL),          // Multiplier configuration
+     .SYST             (SYST),          // SysTick
+     .WIC              (WIC),           // Wake-up interrupt controller support
+     .WICLINES         (WICLINES),      // Supported WIC lines
+     .WPT              (WPT)            // Number of DWT comparators
+   )
+   u_cmsdk_mcu_zed (
+  .XTAL1      (XTAL1),  // input
+ // .i_clk      (XTAL1), 
+ // .XTAL2      (XTAL2),  // output
+  .RST       (NRST),   // active low reset
+  .uartf_TXD (uart0_txd),
+  .o_led (),
+  //.P0_O         (),
+  //.P1         (P1),
+ // .nTRST      (nTRST),  // Not needed if serial-wire debug is used
+  //.TDI        (TDI),    // Not needed if serial-wire debug is used
+  //.TDO        (TDO),    // Not needed if serial-wire debug is used
+  .SWDIOTMS   (SWDIOTMS),
+  .SWCLKTCK   (SWCLKTCK)
+  );
+
+ // --------------------------------------------------------------------------------
+ // Source for clock and reset
+ // --------------------------------------------------------------------------------
+//  cmsdk_clkreset u_cmsdk_clkreset(
+//  .CLK  (XTAL1),
+//  .NRST (NRST)
+//  );
+always #10 XTAL1 =~ XTAL1;
+ // --------------------------------------------------------------------------------
+ // UART output capture
+ // --------------------------------------------------------------------------------
+  assign PCLK = XTAL1;
+
+  cmsdk_uart_capture   u_cmsdk_uart_capture(
+    .RESETn               (~NRST),
+    .CLK                  (PCLK),
+    .RXD                  (uart0_txd), // UART 0 used for StdOut
+    .DEBUG_TESTER_ENABLE  (debug_test_en),
+    .SIMULATIONEND        (),      // This signal set to 1 at the end of simulation.
+    .AUXCTRL              ()
+  );
+
+  // UART connection cross over for UART test
+  assign P1[2] = P1[5];  // UART 1 RXD = UART 2 TXD
+  assign P1[4] = P1[3];  // UART 2 RXD = UART 1 TXD
+
+ // --------------------------------------------------------------------------------
+ // Debug tester connection -
+ // --------------------------------------------------------------------------------
+
+ // No debug connection for Cortex-M0 DesignStart
+ assign nTRST    = NRST;
+ assign TDI      = 1'b1;
+ assign SWDIOTMS = 1'b1;
+ assign SWCLKTCK = 1'b1;
+
+ bufif1 (P0[31-16], debug_running, debug_test_en);
+ bufif1 (P0[30-16], debug_err, debug_test_en);
+
+ pullup (debug_running);
+ pullup (debug_err);
+
+ // --------------------------------------------------------------------------------
+ // Misc
+ // --------------------------------------------------------------------------------
+
+  // Format for time reporting
+  initial    $timeformat(-9, 0, " ns", 0);
+  initial  
+  begin 
+  	XTAL1 = 0;
+    NRST = 1;
+    #1000;
+    NRST = 0;
+ 
+    #100000;
+  end
+endmodule

abdelazeem201_ASIC-Design-Roadmap/good online sites and books for learning ASIC Design/README

@@ -0,0 +1 @@
+

abdelazeem201_ASIC-Design-Roadmap/lef_layer_tf_number_mapper.pl

@@ -0,0 +1,198 @@
+#!/depot/perl-5.003/bin/perl5.003 -w
+
+# Written by Ahmed Abdelazeem
+# March 11, 2024
+# Updated to cover more LEF cases
+# July 1, 2024
+# A Perl script processes a technology file (.tf) and an LEF (Library Exchange Format) file to generate a mapping between layers defined in these files.
+#
+#
+
+$EXPECTED_COMMAND_ARGS = 2;
+
+if ($#ARGV < $EXPECTED_COMMAND_ARGS -1 )
+        {
+        die "Usage: lef_layer_tf_number_map.pl Tech_file_name.tf Lef_file_name.lef\n";
+        }
+        else
+                {
+                $tech_file = $ARGV[0];
+                $lef_file = $ARGV[1];
+		$tmp_s1 = $ARGV[0];
+		$tmp_s1 =~ s/\.tf/_tf/;
+		$tmp_s2 = $ARGV[1];
+		$tmp_s2 =~ s/\.lef/_lef/;
+                $lef_tf_map_file = $tmp_s2."_".$tmp_s1.".map";
+                $lef_tf_log_file = $tmp_s2."_".$tmp_s1.".log";
+                }
+
+open tech_file or die "Can't open $tech_file\n";
+open lef_file or die "Can't open $lef_file\n";
+open lef_tf_log_file, ">$lef_tf_log_file" or die "Can't open $lef_tf_log_file\n";
+open lef_tf_map_file, ">$lef_tf_map_file" or die "Can't open $lef_tf_map_file\n";
+
+print_log( "\n*** Beginning to process $tech_file tech file***\n");
+$i=0;
+
+%tf_layerMaskNames = ();
+%tf_layerMaskLayerNumber = ();
+%tf_layerName = ();
+
+$processing_tf_layer = 0;
+$found_maskName = 0;
+$tf_masks = 0;
+while ($line = <tech_file>) 
+{
+	chop $line;
+	if ( $line =~ /^[lL][aA][yY][eE][rR][\s]+\"([\w\W]+)\"[\s]+\{.*$/ )
+	{
+	if ($processing_tf_layer ==0)
+		{
+		$processing_tf_layer = 1;
+		$tf_layer_name = $1;
+		print_log( "\nBeginning to process $tf_layer_name layer...\n");
+		}
+	}	
+	elsif ( $line =~ /^[\s]*\}.*$/) 
+		{
+		if ($processing_tf_layer ==1) 
+			{
+			if ($found_maskName == 1)
+				{
+				$tf_layerMaskNames{$tf_masks} = $tf_maskName;
+				$tf_layerMaskLayerNumber{$tf_maskName} = $tf_layerNumber;
+				$tf_layerName{$tf_maskName} = $tf_layer_name;
+
+				$tf_masks++;
+				$found_maskName =0;
+				}
+			print_log( "Completed the processing of $tf_layer_name layer.\n");
+			$processing_tf_layer = 0;
+			}
+		}
+	elsif ( $line =~ /^[\s]*layerNumber[\s]*\=[\s]*([\d]+).*$/) 
+		{
+		$tf_layerNumber = $1;
+		print_log( "Found the layerNumber $tf_layerNumber for the $tf_layer_name!\n");
+		}
+	elsif ( $line =~ /^[\s]*maskName[\s]*\=[\s]*\"([\w]+)\".*$/) 
+		{
+		$tf_maskName = $1;
+		$found_maskName = 1;
+		print_log( "Found the maskName $tf_maskName for the $tf_layer_name!\n");
+		}
+$i++;
+}
+
+#foreach $key (keys %tf_layerMaskNames)
+#	{
+#	print "tf_layerName=$tf_layerName{$tf_layerMaskNames{$key}}		";
+#	print "tf_mask_layerName=$tf_layerMaskNames{$key}		";
+#	print "tf_mask_layerNumber=$tf_layerMaskLayerNumber{$tf_layerMaskNames{$key}}\n";
+#	}
+
+print_log( "\n*** Beginning to process $lef_file LEF file***\n");
+
+%lef_layerDerivedMaskNames = ();
+%lef_layerDerivedMaskLayerNumber = ();
+%lef_layerName = ();
+
+$i=0;
+$lef_masks = 0;
+$processing_lef_layer = 0;
+$lef_prev_layerTYPE = "";
+$metal_index = 0;
+while ($line = <lef_file>) 
+{
+	chop $line;
+#	print "$line\n";
+#	print "$i th line:$line\n";      
+	if ( $line =~ /^LAYER[\s]+([\w]+)[\s]*$/ )
+	{
+	if ($processing_lef_layer ==0)
+		{
+		$processing_lef_layer = 1;
+		$lef_layer_name = $1;
+		print_log( "\nBeginning to process $lef_layer_name layer...\n");
+		}
+	}	
+	elsif ( $line =~ /^END[\s]+[\w]+[\s]*$/) 
+		{
+		if ($processing_lef_layer ==1) 
+			{
+			$lef_derivedmaskName = "";
+			if ( ($lef_layerTYPE eq "MASTERSLICE") && ($lef_masks == 0) )
+				{
+				$lef_derivedmaskName = "poly";
+				}
+			elsif ( ($lef_layerTYPE eq "CUT") && ($lef_prev_layerTYPE eq "MASTERSLICE") )
+				{
+				$lef_derivedmaskName = "polyCont";
+				}
+			elsif ( ($lef_layerTYPE eq "ROUTING") )
+				{
+				if ( $metal_index == 0) { $metal_index = 1; }
+				else { $metal_index++; }
+				$lef_derivedmaskName = "metal".$metal_index;
+				}
+			elsif ( ($lef_layerTYPE eq "CUT") && ($lef_prev_layerTYPE ne "MASTERSLICE"))
+				{
+#				print "lef_layerTYPE=$lef_layerTYPE;lef_masks=$lef_masks;lef_prev_layerTYPE=$lef_prev_layerTYPE\n";
+				$lef_derivedmaskName = "via".$metal_index;
+				}
+			elsif ( ($lef_layerTYPE eq "OVERLAP") )
+				{
+				print_log( "Skipping the OVERLAP Layer...\n");
+				}
+			else    { 
+#				print "lef_layerTYPE=$lef_layerTYPE;lef_masks=$lef_masks;lef_prev_layerTYPE=$lef_prev_layerTYPE\n";
+				die "Can not process due to issue...\n";
+				}
+
+			if ($lef_derivedmaskName ne "" )
+				{
+				$lef_derivedlayerNumber = $tf_layerMaskLayerNumber{$lef_derivedmaskName};
+
+				$lef_layerDerivedMaskNames{$lef_masks} = $lef_derivedmaskName;
+				$lef_layerDerivedMaskLayerNumber{$lef_derivedmaskName} = $lef_derivedlayerNumber;
+				$lef_layerName{$lef_derivedmaskName} = $lef_layer_name;
+				$lef_masks++;
+				}
+			print_log( "Completed the processing of $lef_layer_name layer.\n");
+			$processing_lef_layer = 0;
+			$lef_prev_layerTYPE = $lef_layerTYPE;
+			}
+		}
+	elsif ( $line =~ /^[\s]*TYPE[\s]+([\w]+)[\s]*\;.*$/) 
+		{
+		$lef_layerTYPE = $1;
+		print_log( "Found the TYPE $lef_layerTYPE for the $lef_layer_name!\n");
+		}
+$i++;
+}
+
+#foreach $key (keys %lef_layerDerivedMaskNames)
+#	{
+#	print "lef_layerName=$lef_layerName{$lef_layerDerivedMaskNames{$key}}		";
+#	print "lef_mask_layerName=$lef_layerDerivedMaskNames{$key}		";
+#	print "lef_mask_layerNumber=$lef_layerDerivedMaskLayerNumber{$lef_layerDerivedMaskNames{$key}}\n";
+#	}
+
+print_log( "\n*** Printing the map file between $lef_file and $tech_file ***\n");
+for ($j=0; $j < $lef_masks; $j++)
+	{
+	print_map("$lef_layerName{$lef_layerDerivedMaskNames{$j}}");
+	print_map(" $lef_layerDerivedMaskLayerNumber{$lef_layerDerivedMaskNames{$j}}\n");
+	}
+
+close lef_tf_map_file;
+
+sub print_log {
+	print "$_[0]";
+	print lef_tf_log_file "$_[0]";
+}
+
+sub print_map {
+	print "$_[0]";
+	print lef_tf_map_file "$_[0]";
+}

abdelazeem201_ASIC-Design-Roadmap/low_power.upf

@@ -0,0 +1,68 @@
+#Scope: RISC_CORE_1
+
+#Domain: TOP
+create_power_domain TOP
+
+create_supply_net VDDH -domain TOP
+create_supply_port VDDH -domain TOP -direction in
+
+create_supply_net VDDL -domain TOP
+create_supply_port VDDL -domain TOP -direction in
+connect_supply_net VDDL -ports {VDDL}
+
+create_supply_net VSS -domain TOP
+create_supply_port VSS -domain TOP -direction in
+connect_supply_net VSS -ports {VSS}
+
+set_domain_supply_net TOP -primary_power_net VDDH -primary_ground_net VSS
+
+
+add_port_state VSS -state {state1 0.000000}
+add_port_state VDDL -state {state1 0.800000}
+add_port_state VDDH -state {state1 1.200000}
+
+
+#Domain: PD2
+create_power_domain PD2 \
+         -elements {I_DATA_PATH I_CONTROL I_STACK_TOP I_REG_FILE I_PRGRM_CNT_TOP I_INSTRN_LAT}
+create_supply_net VDDL -domain PD2 -reuse
+create_supply_net VSS -domain PD2 -reuse
+set_domain_supply_net PD2 -primary_power_net VDDL -primary_ground_net VSS
+
+add_port_state VSS \
+         -state {state1 0.000000}
+
+#Scope: I_ALU
+
+#Domain: PD1
+create_power_domain PD1 -scope I_ALU \
+         -elements {I_ALU}
+
+
+create_supply_port VSS -domain I_ALU/PD1 -direction in
+create_supply_net VSS -domain I_ALU/PD1
+connect_supply_net I_ALU/VSS -ports {I_ALU/VSS}
+
+create_supply_port PD1_VDD -domain I_ALU/PD1 -direction in
+create_supply_net PD1_VDD -domain I_ALU/PD1
+connect_supply_net I_ALU/PD1_VDD -ports {I_ALU/PD1_VDD}
+
+set_domain_supply_net I_ALU/PD1 -primary_power_net I_ALU/PD1_VDD -primary_ground_net I_ALU/VSS
+
+
+
+add_port_state I_ALU/VSS -state {state1 0.000000}
+add_port_state I_ALU/PD1_VDD -state {state1 1.200000}
+
+
+
+
+connect_supply_net VDDH -ports {VDDH I_ALU/PD1_VDD}
+connect_supply_net VSS -ports {I_ALU/VSS}
+
+
+set_level_shifter shift_up -domain {PD2} -applies_to both -location automatic -rule both
+set_level_shifter shift_up -domain {I_ALU/PD1} -applies_to both -location automatic -rule both
+
+
+

abdelazeem201_ASIC-Design-Roadmap/memories/cmsdk_ahb_ram.v

@@ -0,0 +1,342 @@
+//-----------------------------------------------------------------------------
+// The confidential and proprietary information contained in this file may
+// only be used by a person authorised under and to the extent permitted
+// by a subsisting licensing agreement from ARM Limited.
+//
+//            (C) COPYRIGHT 2010-2013 ARM Limited.
+//                ALL RIGHTS RESERVED
+//
+// This entire notice must be reproduced on all copies of this file
+// and copies of this file may only be made by a person if such person is
+// permitted to do so under the terms of a subsisting license agreement
+// from ARM Limited.
+//
+//      SVN Information
+//
+//      Checked In          : $Date: 2013-04-10 15:27:13 +0100 (Wed, 10 Apr 2013) $
+//
+//      Revision            : $Revision: 243506 $
+//
+//      Release Information : Cortex-M System Design Kit-r1p0-00rel0
+//
+//-----------------------------------------------------------------------------
+//-----------------------------------------------------------------------------
+// Abstract : Simple AHB RAM model wrapper
+//-----------------------------------------------------------------------------
+// This RAM wrapper allows various types of RAM to be instantiated by
+// simply changing MEM_TYPE parameter.
+//
+// Select one of the following
+//
+// MEM_TYPE = 0 : AHB_ROM_NONE
+// - Memory not present
+//
+// MEM_TYPE = 1 : AHB_RAM_BEH_MODEL
+// - Simple behavioral model (default)
+//
+// MEM_TYPE = 2 : AHB_RAM_FPGA_SRAM_MODEL
+// - behavioral model of simple ASIC/FPGA SRAM model with AHB wrapper
+//
+// MEM_TYPE = 3 : AHB_RAM_EXT_SRAM16_MODEL
+// - behavioral model of simple 16-bit external SRAM model with external memory interface
+//
+// MEM_TYPE = 4 : AHB_RAM_EXT_SRAM8_MODEL
+// - behavioral model of simple 8-bit external SRAM model with external memory interface
+//
+`include "cmsdk_ahb_memory_models_defs.v"
+
+module cmsdk_ahb_ram #(
+  parameter MEM_TYPE = 2, // Memory Type : Default to behavioral memory
+  parameter AW       = 16,// Address width
+  parameter filename = "",
+  parameter WS_N     = 0, // First access wait state
+  parameter WS_S     = 0  // Subsequent access wait state
+ )
+ (
+  input  wire          HCLK,    // Clock
+  input  wire          HRESETn, // Reset
+  // AHB inputs
+  input  wire          HSEL,    // Device select
+  input  wire [AW-1:0] HADDR,   // Address
+  input  wire [1:0]    HTRANS,  // Transfer control
+  input  wire [2:0]    HSIZE,   // Transfer size
+  input  wire          HWRITE,  // Write control
+  input  wire [31:0]   HWDATA,  // Write data
+  input  wire          HREADY,  // Transfer phase done
+  // AHB Outputs
+  output wire          HREADYOUT, // Device ready
+  output wire [31:0]   HRDATA,  // Read data output
+  output wire          HRESP);  // Device response (always OKAY)
+  
+//  parameter MEM_TYPE = 2;
+  //----------------------------------------------------------------
+  // AHB_RAM_NONE : Memory not present
+/*
+  generate if (MEM_TYPE == `AHB_RAM_NONE) begin
+    assign HREADYOUT = 1'b1;
+    assign HRDATA    = {32{1'b0}};
+    assign HRESP     = 1'b0;
+  end endgenerate
+
+  //----------------------------------------------------------------
+  // AHB_RAM_BEH_MODEL : Simple behavioral model (default)
+
+  generate if (MEM_TYPE == `AHB_RAM_BEH_MODEL) begin
+  // Behavioral SRAM model
+  cmsdk_ahb_ram_beh
+  #(.AW(AW),
+    .filename(filename),
+    .WS_N(WS_N),
+    .WS_S(WS_S)
+    )
+  u_ahb_ram_beh (
+    .HCLK       (HCLK),
+    .HRESETn    (HRESETn),
+    .HSEL       (HSEL),  // AHB inputs
+    .HADDR      (HADDR),
+    .HTRANS     (HTRANS),
+    .HSIZE      (HSIZE),
+    .HWRITE     (HWRITE),
+    .HWDATA     (HWDATA),
+    .HREADY     (HREADY),
+
+    .HREADYOUT  (HREADYOUT), // Outputs
+    .HRDATA     (HRDATA),
+    .HRESP      (HRESP)
+  );
+  end endgenerate
+*/
+  //----------------------------------------------------------------
+  // AHB_RAM_FPGA_SRAM_MODEL :
+  //    behavioral model of simple ASIC/FPGA SRAM model with AHB wrapper
+
+  //generate if (MEM_TYPE == `AHB_RAM_FPGA_SRAM_MODEL) begin
+  // wires for SRAM interface
+  wire  [AW-3:0] SRAMADDR;
+  wire    [31:0] SRAMWDATA;
+  wire    [31:0] SRAMRDATA;
+  wire     [3:0] SRAMWEN;
+  wire           SRAMCS;
+
+  // AHB to SRAM bridge
+  cmsdk_ahb_to_sram #(.AW(AW)) u_ahb_to_sram
+  (
+    // AHB Inputs
+    .HCLK       (HCLK),
+    .HRESETn    (HRESETn),
+    .HSEL       (HSEL),  // AHB inputs
+    .HADDR      (HADDR),
+    .HTRANS     (HTRANS),
+    .HSIZE      (HSIZE),
+    .HWRITE     (HWRITE),
+    .HWDATA     (HWDATA),
+    .HREADY     (HREADY),
+
+    // AHB Outputs
+    .HREADYOUT  (HREADYOUT), // Outputs
+    .HRDATA     (HRDATA),
+    .HRESP      (HRESP),
+
+   // SRAM input
+    .SRAMRDATA  (SRAMRDATA),
+   // SRAM Outputs
+    .SRAMADDR   (SRAMADDR),
+    .SRAMWDATA  (SRAMWDATA),
+    .SRAMWEN    (SRAMWEN),
+    .SRAMCS     (SRAMCS)
+   );
+
+  // SRAM model
+ // cmsdk_fpga_sram #(.AW(AW)) u_fpga_sram
+  fpga_ram_top #(.AW(AW)) fpga_ram_top
+   (
+   // SRAM Inputs
+    .CLK        (HCLK),
+    .ADDR       (SRAMADDR),
+    .WDATA      (SRAMWDATA),
+    .WREN       (SRAMWEN),
+    .CS         (SRAMCS),
+   // SRAM Outputs
+    .RDATA      (SRAMRDATA)
+   );
+//  end endgenerate
+
+  //----------------------------------------------------------------
+  // AHB_RAM_EXT_SRAM16_MODEL :
+  //    behavioral model of 16-bit external SRAM with AHB to external RAM interface
+  //
+  //    Note    : for benchmarking using 16-bit external asynchronous SRAM.
+  //              In real application the 16-bit external SRAM will be off chip
+  //
+/*
+  generate if (MEM_TYPE == `AHB_RAM_EXT_SRAM16_MODEL) begin
+  // wires for external SRAM interface
+  wire    [AW-1:0]  EMIADDR;  // External memory interface address
+  wire    [15:0]  EMIDATA;  // External memory interface data (bi-directional)
+  wire    [15:0]  EMIDATAIN;
+  wire    [15:0]  EMIDATAOUT;
+  wire            EMIDATAOEn;
+  wire            EMIWEn;   // Write enable (active low)
+  wire            EMIOEn;   // Output enable (active low)
+  wire            EMICEn;   // Chip enable (active low)
+  wire            EMILBn;   // Lower byte strobe (active low)
+  wire            EMIUBn;   // Upper byte strobe (active low)
+
+  wire    [2:0]   CFGREADCYCLE;
+  wire    [2:0]   CFGWRITECYCLE;
+  wire    [2:0]   CFGTURNAROUNDCYCLE;
+  wire            CFGSIZE;
+
+  assign  CFGSIZE            = 1'b1; // 16-bit
+  assign  CFGREADCYCLE       = WS_N;
+  assign  CFGWRITECYCLE      = WS_N;
+  assign  CFGTURNAROUNDCYCLE = WS_N;
+
+  // interface to external SRAM
+  cmsdk_ahb_to_extmem16
+    #(.AW (AW))
+    u_ahb_to_extmem16 (
+    .HCLK         (HCLK),
+    .HRESETn      (HRESETn),
+
+    .HSEL         (HSEL),       // AHB inputs
+    .HADDR        (HADDR[AW-1:0]),
+    .HTRANS       (HTRANS),
+    .HSIZE        (HSIZE),
+    .HWRITE       (HWRITE),
+    .HWDATA       (HWDATA),
+    .HREADY       (HREADY),
+
+    .HREADYOUT    (HREADYOUT), // AHB Outputs
+    .HRDATA       (HRDATA),
+    .HRESP        (HRESP),
+
+     // Configuration signals
+    .CFGREADCYCLE      (CFGREADCYCLE),   // Read cycle
+    .CFGWRITECYCLE     (CFGWRITECYCLE),  // Write cycle
+    .CFGTURNAROUNDCYCLE(CFGTURNAROUNDCYCLE),  // Turn around cycle
+    .CFGSIZE           (CFGSIZE),     // Size (0 = 8-bit, 1 = 16-bit)
+
+     // External memory
+    .DATAIN       (EMIDATAIN),      // data input
+
+    .ADDR         (EMIADDR[AW-1:0]),        // address output
+    .DATAOUT      (EMIDATAOUT),     // data output
+    .DATAOEn      (EMIDATAOEn),     // output enable (active low)
+    .WEn          (EMIWEn),         // write control (active low)
+    .OEn          (EMIOEn),         // read control  (active low)
+    .CEn          (EMICEn),         // Chip Enable   (active low)
+    .LBn          (EMILBn),         // Lower Byte    (active low)
+    .UBn          (EMIUBn)          // Upper Byte    (active low)
+  );
+
+  // Tristate buffer for data
+  assign EMIDATAIN = EMIDATA;
+  assign EMIDATA   = (EMIDATAOEn==1'b0) ? EMIDATAOUT : {16{1'bz}};
+
+  // 16-bit SRAM model
+  cmsdk_sram256x16
+    #(.AW(AW))
+    u_sram256x16 (
+    .Address  (EMIADDR[AW-1:0]),
+    .DataIO   (EMIDATA),
+    .WEn      (EMIWEn),
+    .OEn      (EMIOEn),
+    .CEn      (EMICEn),
+    .LBn      (EMILBn),
+    .UBn      (EMIUBn)
+    );
+
+  end endgenerate
+
+  //----------------------------------------------------------------
+  // AHB_RAM_EXT_SRAM8_MODEL :
+  //    behavioral model of 8-bit external SRAM with AHB to external RAM interface
+  //
+  //    Note    : for benchmarking using 8-bit external asynchronous SRAM.
+  //              In real application the 8-bit external SRAM will be off chip
+  //
+
+  generate if (MEM_TYPE == `AHB_RAM_EXT_SRAM8_MODEL) begin
+  // wires for external SRAM interface
+  wire    [AW-1:0]  EMIADDR;  // External memory interface address
+  wire    [15:0]  EMIDATA;  // External memory interface data (bi-directional)
+  wire    [15:0]  EMIDATAIN;
+  wire    [15:0]  EMIDATAOUT;
+  wire            EMIDATAOEn;
+  wire            EMIWEn;   // Write enable (active low)
+  wire            EMIOEn;   // Output enable (active low)
+  wire            EMICEn;   // Chip enable (active low)
+  wire            EMILBn;   // Lower byte strobe (active low)
+  wire            EMIUBn;   // Upper byte strobe (active low)
+
+  wire    [2:0]   CFGREADCYCLE;
+  wire    [2:0]   CFGWRITECYCLE;
+  wire    [2:0]   CFGTURNAROUNDCYCLE;
+  wire            CFGSIZE;
+
+  assign  CFGSIZE            = 1'b0; // 8-bit
+  assign  CFGREADCYCLE       = WS_N;
+  assign  CFGWRITECYCLE      = WS_N;
+  assign  CFGTURNAROUNDCYCLE = WS_N;
+
+  // interface to external SRAM
+  cmsdk_ahb_to_extmem16
+    #(.AW (AW))
+    u_ahb_to_extmem16 (
+    .HCLK         (HCLK),
+    .HRESETn      (HRESETn),
+
+    .HSEL         (HSEL),       // AHB inputs
+    .HADDR        (HADDR[AW-1:0]),
+    .HTRANS       (HTRANS),
+    .HSIZE        (HSIZE),
+    .HWRITE       (HWRITE),
+    .HWDATA       (HWDATA),
+    .HREADY       (HREADY),
+
+    .HREADYOUT    (HREADYOUT), // AHB Outputs
+    .HRDATA       (HRDATA),
+    .HRESP        (HRESP),
+
+     // Configuration signals
+    .CFGREADCYCLE      (CFGREADCYCLE),   // Read cycle
+    .CFGWRITECYCLE     (CFGWRITECYCLE),  // Write cycle
+    .CFGTURNAROUNDCYCLE(CFGTURNAROUNDCYCLE),  // Turn around cycle
+    .CFGSIZE           (CFGSIZE),     // Size (0 = 8-bit, 1 = 16-bit)
+
+     // External memory
+    .DATAIN       (EMIDATAIN),      // data input
+
+    .ADDR         (EMIADDR[AW-1:0]),// address output
+    .DATAOUT      (EMIDATAOUT),     // data output
+    .DATAOEn      (EMIDATAOEn),     // output enable (active low)
+    .WEn          (EMIWEn),         // write control (active low)
+    .OEn          (EMIOEn),         // read control  (active low)
+    .CEn          (EMICEn),         // Chip Enable   (active low)
+    .LBn          (EMILBn),         // Lower Byte    (active low)
+    .UBn          (EMIUBn)          // Upper Byte    (active low)
+  );
+
+  // Tristate buffer for data 
+  assign EMIDATAIN = {8'h00, EMIDATA[7:0]};
+  assign EMIDATA   = (EMIDATAOEn==1'b0) ? EMIDATAOUT : {16{1'bz}};
+
+  // 8-bit SRAM model
+  cmsdk_sram256x8
+    #(.AW(AW))
+    u_sram256x8 (
+    .Address  (EMIADDR[AW-1:0]),
+    .DataIO   (EMIDATA[7:0]),
+    .WEn      (EMIWEn),
+    .OEn      (EMIOEn),
+    .CEn      (EMICEn)
+    );
+
+  end endgenerate
+*/
+  //----------------------------------------------------------------
+
+
+endmodule
+

abdelazeem201_ASIC-Design-Roadmap/memories/cmsdk_ahb_rom.v

@@ -0,0 +1,324 @@
+//-----------------------------------------------------------------------------
+// The confidential and proprietary information contained in this file may
+// only be used by a person authorised under and to the extent permitted
+// by a subsisting licensing agreement from ARM Limited.
+//
+//            (C) COPYRIGHT 2010-2013 ARM Limited.
+//                ALL RIGHTS RESERVED
+//
+// This entire notice must be reproduced on all copies of this file
+// and copies of this file may only be made by a person if such person is
+// permitted to do so under the terms of a subsisting license agreement
+// from ARM Limited.
+//
+//      SVN Information
+//
+//      Checked In          : $Date: 2013-03-22 11:05:41 +0000 (Fri, 22 Mar 2013) $
+//
+//      Revision            : $Revision: 242013 $
+//
+//      Release Information : Cortex-M System Design Kit-r1p0-00rel0
+//
+//-----------------------------------------------------------------------------
+//-----------------------------------------------------------------------------
+// Abstract : Simple AHB ROM model wrapper
+//-----------------------------------------------------------------------------
+// This ROM wrapper allows various types of memory to be instantiated by
+// simply changing MEM_TYPE parameter.
+//
+// Select one of the following
+//
+// MEM_TYPE = 0 : AHB_ROM_NONE
+// - Memory not present
+//
+// MEM_TYPE = 1 : AHB_ROM_BEH_MODEL
+// - Simple behavioral model (default)
+//
+// MEM_TYPE = 2 : AHB_ROM_FPGA_SRAM_MODEL
+// - behavioral model of simple ASIC/FPGA ROM/SRAM model with wrapper
+//
+// MEM_TYPE = 3 : AHB_ROM_FLASH32_MODEL
+// - 32-bit flash model
+//
+// MEM_TYPE = 4 : AHB_ROM_FLASH16_MODEL
+// - 16-bit flash model
+//
+
+`include "cmsdk_ahb_memory_models_defs.v"
+//`define MEM_TYPE  2 
+module cmsdk_ahb_rom #(
+// --------------------------------------------------------------------------
+// Parameter Declarations
+// --------------------------------------------------------------------------
+ //parameter MEM_TYPE = 1,   // Memory Type : Default to behavioral memory
+  parameter MEM_TYPE = 2,   // Memory Type : Default to behavioral memory
+ parameter AW       = 16,  // Address width
+ parameter filename = "",
+ parameter WS_N     = 0,   // First access wait state
+ parameter WS_S     = 0,   // Subsequent access wait state
+ parameter BE       = 0    // Big endian
+ )
+ (
+  input  wire          HCLK,    // Clock
+  input  wire          HRESETn, // Reset
+  input  wire          HSEL,    // Device select
+  input  wire [AW-1:0] HADDR,   // Address
+  input  wire [1:0]    HTRANS,  // Transfer control
+  input  wire [2:0]    HSIZE,   // Transfer size
+  input  wire          HWRITE,  // Write control
+  input  wire [31:0]   HWDATA,  // Write data
+  input  wire          HREADY,  // Transfer phase done
+
+  output wire          HREADYOUT, // Device ready
+  output wire [31:0]   HRDATA,  // Read data output
+  output wire          HRESP    // Device response (always OKAY)
+  );
+
+  //----------------------------------------------------------------
+  // AHB_ROM_NONE : Memory not present
+
+  generate if (MEM_TYPE == `AHB_ROM_NONE) begin
+    assign HREADYOUT = 1'b1;
+    assign HRDATA    = {32{1'b0}};
+    assign HRESP     = 1'b0;
+  end endgenerate
+
+  //----------------------------------------------------------------
+  // AHB_ROM_BEH_MODEL : Simple behavioral model (default)
+/*
+  generate if (MEM_TYPE == `AHB_ROM_BEH_MODEL) begin
+    // Behavioral memory model
+  cmsdk_ahb_ram_beh
+  #(.AW(AW),
+    .filename(filename),
+    .WS_N(WS_N),
+    .WS_S(WS_S)
+    )
+  u_ahb_ram_beh (
+    .HCLK       (HCLK),
+    .HRESETn    (HRESETn),
+    .HSEL       (HSEL),  // AHB inputs
+    .HADDR      (HADDR),
+    .HTRANS     (HTRANS),
+    .HSIZE      (HSIZE),
+    .HWRITE     (1'b0), // write disabled
+    .HWDATA     (32'h00000000),
+    .HREADY     (HREADY),
+
+    .HREADYOUT  (HREADYOUT), // Outputs
+    .HRDATA     (HRDATA),
+    .HRESP      (HRESP)
+  );
+  end endgenerate
+*/
+  //----------------------------------------------------------------
+  // AHB_ROM_FPGA_SRAM_MODEL :
+  //    behavioral model of simple ASIC/FPGA ROM/SRAM model with wrapper
+
+ // generate if (MEM_TYPE == `AHB_ROM_FPGA_SRAM_MODEL) begin
+  // wires for ROM/SRAM interface
+  wire  [AW-3:0] SRAMADDR;
+  wire    [31:0] SRAMWDATA;
+  wire    [31:0] SRAMRDATA;
+  wire     [3:0] SRAMWEN;
+  wire           SRAMCS;
+
+  // AHB to SRAM bridge
+  cmsdk_ahb_to_sram
+    #(.AW(AW)
+   ) u_ahb_to_sram
+  (
+    // AHB Inputs
+    .HCLK       (HCLK),
+    .HRESETn    (HRESETn),
+    .HSEL       (HSEL),  // AHB inputs
+    .HADDR      (HADDR),
+    .HTRANS     (HTRANS),
+    .HSIZE      (HSIZE),
+    .HWRITE     (HWRITE),
+    .HWDATA     (HWDATA),
+    .HREADY     (HREADY),
+
+    // AHB Outputs
+    .HREADYOUT  (HREADYOUT), // Outputs
+    .HRDATA     (HRDATA),
+    .HRESP      (HRESP),
+
+   // SRAM input
+    .SRAMRDATA  (SRAMRDATA),
+   // SRAM Outputs
+    .SRAMADDR   (SRAMADDR),
+    .SRAMWDATA  (SRAMWDATA),
+    .SRAMWEN    (SRAMWEN),
+    .SRAMCS     (SRAMCS)
+   );
+
+  // RAM model
+//  cmsdk_fpga_rom #(.AW(AW), .filename(filename)) u_fpga_rom
+  fpga_rom_top #(.AW(AW), .filename(filename))  fpga_rom_top
+   (
+   // SRAM Inputs
+    .CLK        (HCLK),
+    .ADDR       (SRAMADDR),
+    .WDATA      (SRAMWDATA),
+    .WREN       (SRAMWEN),
+    .CS         (SRAMCS),
+   // SRAM Outputs
+    .RDATA      (SRAMRDATA)
+   );
+//  end endgenerate
+
+/*
+  //----------------------------------------------------------------
+  // AHB_ROM_FLASH32_MODEL : 32-bit flash model (no pre-fetcher)
+
+  generate if (MEM_TYPE == `AHB_ROM_FLASH32_MODEL) begin
+  // wires for Flash interface
+  wire  [AW-3:0] FLASHADDR;
+  wire    [31:0] FLASHRDATA;
+
+  // flash memory wrapper
+  cmsdk_ahb_to_flash32
+   #(
+   .AW (AW),
+   .WS (WS_N)
+    ) u_ahb_to_flash32 (
+    .HCLK         (HCLK),
+    .HRESETn      (HRESETn),
+    .HSEL         (HSEL),  // AHB inputs
+    .HADDR        (HADDR),
+    .HTRANS       (HTRANS),
+    .HPROT        (4'h8), // Always cacheable
+    .HSIZE        (HSIZE),
+    .HWRITE       (HWRITE),
+    .HWDATA       (32'h00000000), // not used
+    .HREADY       (HREADY),
+
+    .HREADYOUT    (HREADYOUT), // Outputs
+    .HRDATA       (HRDATA),
+    .HRESP        (HRESP),
+
+    .FLASHADDR    (FLASHADDR),
+    .FLASHRDATA   (FLASHRDATA)
+  );
+
+  // 32-bit flash
+  cmsdk_flash_rom32
+    #(
+   .AW (AW),
+   .WS (WS_N),
+   .filename (filename)
+    ) u_flash_rom32(
+    .rst_n        (HRESETn),    // for emulation of timing
+    .clk          (HCLK),       // for emulation of timing
+    .addr         (FLASHADDR),  // address
+    .rdata        (FLASHRDATA)  // data
+    );
+
+  end endgenerate
+
+  //----------------------------------------------------------------
+  // AHB_ROM_FLASH16_MODEL : 16-bit flash model (no pre-fetcher)
+
+  generate if (MEM_TYPE == `AHB_ROM_FLASH16_MODEL) begin
+  // wires for Flash interface
+  wire  [AW-2:0] FLASHADDR;
+  wire    [15:0] FLASHRDATA;
+
+  wire    [AW-1:0] MHADDR;
+  wire    [1:0]    MHTRANS;
+  wire    [3:0]    MHPROT;
+  wire    [2:0]    MHSIZE;
+  wire             MHWRITE;
+  wire    [15:0]   MHRDATA;
+  wire             MHREADY;
+  wire             MHRESP;
+
+  // Down sizer for 16-bit memory
+  cm0p_32to16_dnsize   #(
+   .AW (AW)
+    ) u_cm0p_32to16_dnsize (
+    .HCLK         (HCLK),
+    .HRESETn      (HRESETn),
+
+    // Inputs
+    .SHADDR       (HADDR),
+    .SHTRANS      (HTRANS),
+    .SHPROT       (4'h8),
+    .SHBURST      (3'h0),
+    .SHMASTLOCK   (1'b0),
+    .SHSIZE       (HSIZE),
+    .SHWRITE      (HWRITE),
+    .SHWDATA      (HWDATA),
+    .SHREADY      (HREADY),
+    .SHSEL        (HSEL),
+
+    .SHMASTER     (1'b0),
+
+    // Outputs
+    .SHREADYOUT   (HREADYOUT),
+    .SHRDATA      (HRDATA),
+    .SHRESP       (HRESP),
+
+    .MHADDR       (MHADDR),
+    .MHTRANS      (MHTRANS),
+    .MHPROT       (MHPROT),
+    .MHBURST      (), // not used
+    .MHMASTLOCK   (), // not used
+    .MHSIZE       (MHSIZE),
+    .MHWRITE      (MHWRITE),
+    .MHWDATA      (), // not used
+
+
+    .MHMASTER     (), // not used
+
+    // Inputs
+    .MHREADY      (MHREADY),
+    .MHRDATA      (MHRDATA),
+    .MHRESP       (MHRESP));
+
+  // flash memory wrapper
+  cmsdk_ahb_to_flash16
+   #(
+   .AW (AW),
+   .WS (WS_N)
+    ) u_ahb_to_flash16 (
+    .HCLK         (HCLK),
+    .HRESETn      (HRESETn),
+    // AHB inputs
+    .HSEL         (1'b1),
+    .HADDR        (MHADDR),
+    .HTRANS       (MHTRANS),
+    .HPROT        (MHPROT), // Always cacheable
+    .HSIZE        (MHSIZE),
+    .HWRITE       (MHWRITE),
+    .HWDATA       (16'h0000), // not used
+    .HREADY       (MHREADY),
+
+    .HREADYOUT    (MHREADY), // Outputs
+    .HRDATA       (MHRDATA),
+    .HRESP        (MHRESP),
+
+    .FLASHADDR    (FLASHADDR),
+    .FLASHRDATA   (FLASHRDATA)
+  );
+
+  // 16-bit flash
+  cmsdk_flash_rom16
+    #(
+   .AW (AW),
+   .WS (WS_N),
+   .filename (filename)
+    ) u_flash_rom16(
+    .rst_n        (HRESETn),    // for emulation of timing
+    .clk          (HCLK),       // for emulation of timing
+    .addr         (FLASHADDR),  // address
+    .rdata        (FLASHRDATA)  // data
+    );
+
+  end endgenerate
+*/
+  //----------------------------------------------------------------
+
+endmodule
+

abdelazeem201_ASIC-Design-Roadmap/mentor_scripts/0_import.tcl

@@ -0,0 +1,846 @@
+#####################################################
+## Copyright Mentor, A Siemens Business            ##
+## All Rights Reserved                             ##
+##                                                 ##
+## THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY ##
+## INFORMATION WHICH ARE THE PROPERTY OF MENTOR    ##
+## GRAPHICS CORPORATION OR ITS LICENSORS AND IS    ##
+## SUBJECT TO LICENSE TERMS.                       ##
+#####################################################
+puts "
+#####################################################
+## Nitro Reference Flow : Import Stage             ##
+##                                                 ##
+## Imports technology & design info to prepare     ##
+## design for NRF place and route.                 ##
+#####################################################
+"
+fk_msg -set_prompt NRF
+#config_units -value_type distance -units micro
+config_shell -echo_script false
+
+# ==============
+# Read libraries and variables
+# ==============
+if { [info exists MGC_tanner_flow] && $MGC_tanner_flow eq "true"} {
+    fk_msg -type info "Running Nitro-AMS : Import Stage" 
+} else {
+    source import_variables.tcl  
+}
+
+set tmpdir [file dirname $sierra_tcl_dir]
+set nrf_dir ${tmpdir}/ref_flows/tcl
+
+if { [info exists MGC_nrf_custom_scripts_dir] && $MGC_nrf_custom_scripts_dir != "" && [file exists $MGC_nrf_custom_scripts_dir/scr/kit_utils.tcl] } {
+    fk_msg "Sourcing custom NRF script $MGC_nrf_custom_scripts_dir/scr/kit_utils.tcl"
+    source $MGC_nrf_custom_scripts_dir/scr/kit_utils.tcl
+} else {
+    fk_msg "Sourcing standard NRF script $nrf_dir/scr/kit_utils.tcl"
+    source $nrf_dir/scr/kit_utils.tcl
+}
+
+set MGC_flowStage import
+
+load_utils -name nrf_utils 
+load_utils -name save_nrf_import_vars -force
+
+## make sure that user input is valid for all stages
+set num_errors [nrf_utils::check_import_variables]
+if { $num_errors > 0 } {
+    fk_msg -type error "Please fix all errors to continue execution"
+    return -code error
+}
+
+nrf_utils::save_nrf_import_vars
+
+# ==========
+# Multi CPUs
+# ==========
+config_application -cpus $MGC_cpus
+config_timing -cpus $MGC_cpus
+
+# If resuming import after manual floorplanning, skip to post-floorplan for resuming execution
+
+if { ![info exists MGC_resume_import] || !$MGC_resume_import } {
+
+# Read in technology libraries if no library DB exists, else read library DB
+
+if {$MGC_libDbPath =="" || ![file exists $MGC_libDbPath]} {
+    fk_msg "MGC_libDbPath : $MGC_libDbPath doesn't exist, Running library setup part of import stage and generate libs.db" 
+
+    # Source the rules.tcl file if provided
+    if {$MGC_tech_rules !="" && [file exists $MGC_tech_rules]} {
+        fk_msg "Reading TECHNO RULES File"
+        source $MGC_tech_rules
+    } else {
+        fk_msg "Since TECHNO RULE File is not provided or does not exist, technology rules must come from tech lef"
+    } 
+    # Source the vias.tcl file if provided 
+    if {$MGC_tech_vias !="" && [file exists $MGC_tech_vias]} {
+        source $MGC_tech_vias
+    }
+    # Source the dfm_vias.tcl file if provided
+    if {$MGC_tech_dfm_vias !="" && [file exists $MGC_tech_dfm_vias]} {
+        source $MGC_tech_dfm_vias
+    }
+
+    # Tech lef is used instead of rules.tcl for technologies 40nm and above
+    if {$MGC_physical_library_tech !="" && [file exists $MGC_physical_library_tech]} {
+        fk_msg "Reading TECH LEF File"
+        read_lef -file $MGC_physical_library_tech
+    }
+
+    if {$MGC_physical_libraries !=""} {
+	fk_msg "Reading Cell LEF Files"
+	read_lef -files "$MGC_physical_libraries"
+    }
+
+    # Read the ptf files
+    foreach parasiticsCorner [array name MGC_parasitic_library] {
+        fk_msg "Load $parasiticsCorner technology .PTF"
+        read_lib $MGC_parasitic_library($parasiticsCorner) -layer_map_file $MGC_itf_to_lef_layer_map -name_prefix $parasiticsCorner
+    }
+
+    # Read the lib files
+    foreach lib_corner [array name MGC_timing_library] {
+        read_library -skip_ccs $MGC_skip_ccs -files $MGC_timing_library($lib_corner) -name_prefix $lib_corner
+    }
+
+    # Perform preprocess lib : it has internal check for node won't do any pre-processing for node > 20
+    if { [info exists MGC_tanner_flow] && $MGC_tanner_flow eq "true"} {
+        #continue 
+    } else {
+        preprocess_library -categories auto 
+    }
+
+    # ====================
+    # Save intermediate db
+    # ====================
+
+    if {$MGC_split_db} {
+        write_db -data lib -file dbs/libs.db
+    } else {
+        write_db -data all -file dbs/import_libs.db
+    }
+} else {
+    fk_msg "Reading Library Database : $MGC_libDbPath : skipping lib gen step"
+    if { [file isfile $MGC_libDbPath] } {
+        # Old DB -- Convert to 2.5
+        load_utils -name db_utils
+        util::update_lib_db -lib_db $MGC_libDbPath
+    } else {
+        read_db -file $MGC_libDbPath
+    }
+    file mkdir dbs
+    if {![file exists dbs/libs.db]} {
+        fk_msg "Creating link dbs/libs.db : $MGC_libDbPath"
+        file link -symbolic dbs/libs.db $MGC_libDbPath
+    } else { 
+        fk_msg -type warning "dbs/libs.db path already exists, make sure MGC_libDbPath is pointing to the same file. All following flow step will use dbs/lib.db"
+    }
+}
+
+set_analysis_corner fast -enable false
+set_analysis_corner slow -enable false
+foreach corner $MGC_corners {
+    set_analysis_corner -corner $corner \
+       			-enable true \
+       			-setup true \
+       			-hold true \
+       			-crpr setup_hold \
+       			-library [get_objects electrical_lib *$MGC_CornerTiming($corner)*] \
+       			-process [get_libs -type process -filter file=="[string trim $MGC_parasitic_library($MGC_CornerParasitic($corner))]"] \
+       			-rc_temp $MGC_CornerTemperature($corner)
+}
+
+report_analysis_corner
+
+# ==============
+# Import netlist
+# ==============
+fk_msg "Reading netlist $MGC_importVerilogNetlist"
+# to handle correctly tie-up/tie-low connections in a multi-supply design
+#TODO: workaround till conver_supply_nets_to_pg is true default
+config_default_value -command read_verilog -argument convert_supply_nets_to_pg -value true
+if {[info exists MGC_mxdb_flow] && $MGC_mxdb_flow } {
+    if {[info exists MGC_mxdb_path] && $MGC_mxdb_path !=""} {
+        #read_mxdb -skip { def directives library netlist scandef SDC } -file $MGC_mxdb_path
+        read_mxdb -skip { library SDC } -file $MGC_mxdb_path
+    } else { 
+        fk_msg -type error "MGC_mxdb_flow is set to true : Provide valid path to mxdb by setting MGC_mxdb_path or set MGC_mxdb_flow to false" 
+    }
+} else {
+    read_verilog $MGC_importVerilogNetlist
+}
+
+if { [info exists MGC_topDesign] && $MGC_topDesign != "" } {
+    current_design $MGC_topDesign
+}
+
+# ============
+# Avoid assign
+# ============
+config_optimize -dont_create_assign
+
+# ==========
+# Enable ccs
+# ==========
+
+if {!$MGC_skip_ccs} {
+    fk_msg "Info: Setting delay model to current"
+    set_delay_model -base_model current
+} else {
+    fk_msg "Info: Setting delay model to voltage"
+    set_delay_model -base_model voltage
+}
+report_delay_model
+
+# ===========================
+# Define implementation modes
+# ===========================
+foreach mode $MGC_modes {
+    define_design_mode $mode
+}
+foreach mode $MGC_modes {
+    set_design_mode $mode -enable true -corners $MGC_cornersPerMode($mode)
+}
+
+set_design_mode default -enable false
+report_design_mode
+
+# =============
+# Read def file
+# ============
+
+if { [info exists MGC_floorLoadDefFile] && $MGC_floorLoadDefFile != "" } {
+    read_def -skip {regions} $MGC_floorLoadDefFile
+}
+
+if { [info exists MGC_nrf_floorplanning] && $MGC_nrf_floorplanning eq "auto"} {
+    if { [info exists MGC_nrf_custom_scripts_dir] && $MGC_nrf_custom_scripts_dir != "" && [file exists $MGC_nrf_custom_scripts_dir/scr/floorplan.tcl] } {
+        fk_msg "Sourcing custom NRF script $MGC_nrf_custom_scripts_dir/scr/floorplan.tcl\n"
+        source $MGC_nrf_custom_scripts_dir/scr/floorplan.tcl
+    } else {
+        fk_msg "Sourcing standard NRF script $nrf_dir/scr/floorplan.tcl\n"
+        source $nrf_dir/scr/floorplan.tcl
+    }
+} elseif { $MGC_nrf_floorplanning eq "manual" } {
+    fk_msg "###############################################################"
+    fk_msg "#  NRF Import suspended for manual floorplanning.             #"
+    fk_msg "#  Perform floorplanning as desired.  When complete, execute: #"
+    fk_msg "#      resume_nrf_import                                      #"
+    fk_msg "#  to resume NRF import flow.                                 #"
+    fk_msg "###############################################################\n"
+    return
+} elseif { $MGC_nrf_floorplanning eq "none" } {
+    fk_msg "Skipping NRF floorplanning.\n"
+} else {
+    fk_msg -type warning "MGC_nrf_floorplanning setting $MGC_nrf_floorplanning is invalid.  Valid values: auto | manual | none.  Skipping NRF floorplanning.\n"
+}
+
+} ;  # If manually floorplanning, we will resume import execution here
+
+# Read additional floorplan script if provided
+
+if {[info exists MGC_floorplan_tcl_file] && $MGC_floorplan_tcl_file != ""} {
+    if { [file exists $MGC_floorplan_tcl_file] } {
+        fk_msg "Sourcing floorplan Tcl file $MGC_floorplan_tcl_file"
+        source $MGC_floorplan_tcl_file
+    } elseif { [info exists MGC_nrf_custom_scripts_dir] && $MGC_nrf_custom_scripts_dir != "" && [file exists $MGC_nrf_custom_scripts_dir/$MGC_floorplan_tcl_file] } {
+        fk_msg "Sourcing floorplan Tcl file $MGC_nrf_custom_scripts_dir/$MGC_floorplan_tcl_file"
+        source $MGC_nrf_custom_scripts_dir/$MGC_floorplan_tcl_file
+    } else {
+        fk_msg -type warning "Could not find file $MGC_floorplan_tcl_file.  Check MGC_floorplan_tcl_file setting."
+    }
+}
+
+# Read scan DEF file if provided
+
+if {[info exists MGC_scan_def_file] && [string trim $MGC_scan_def_file] !=""} {
+    if {[info exists MGC_mxdb_flow] && $MGC_mxdb_flow } {
+        fk_msg -type info "Scan DEF is already loaded from mxdb"
+    } else {
+        read_def -sections {scan_chains} -skip {} -file $MGC_scan_def_file
+    }
+}
+
+# =================================
+# Check design for unresolved cells
+# =================================
+check_design -check cells
+set unresolved_cells [get_cells -of_objects [get_objects -type error -filter @name==unresolved]]
+if {[llength $unresolved_cells] > 0} {
+  fk_msg -type error "Design has [llength $unresolved_cells] unresolved cells that must be fixed before proceeding."
+  foreach c $unresolved_cells {
+    puts "\t$c of cell type [get_lib_cell -of $c]"
+  }
+  exit -1
+}
+
+# =======================
+# Check for top partition
+# =======================
+
+if {[llength [get_top_partition]] == 0} {
+  fk_msg -type error "No partition has been created.  Check floorplan and/or input DEF file.\n"
+  exit -1
+}
+
+# ================
+# Check and Re-create tracks
+# ================
+set node [get_config -name process -param node]
+if {$node > 22 || $node=="unknown"} {
+    ## Create tracks for nodes above 22nm. 
+    fk_msg "Creating new tracks on all layers"
+    remove_objects -objects [get_objects -type track]
+    create_tracks
+} else { 
+    check_floorplan -check no_tracks
+    set track_errs [get_objects -type error -filter (@category==floorplan)&&(@name==no_tracks)]
+    if {[llength $track_errs] } {
+        fk_msg -type error "No preferred direction routing tracks on the layers: [get_objects -type layer -of_objects $track_errs]"
+        fk_msg  "Review and create tracks on missing layers : using command create_tracks" 
+        return -code error
+    }
+}
+# Control generated vias based on user setting or node
+if { [info exists MGC_disable_SDA_vias_creation] && $MGC_disable_SDA_vias_creation } {
+    config_lib_vias -use_generated false -create false -select true -use_asymmetrical true -use_4cut true
+} elseif {$node > 28 || $node=="unknown"} {
+    config_lib_vias -use_generated true -create true -select true -use_asymmetrical true -use_4cut true
+} else {
+    config_lib_vias -use_generate false
+}
+
+# Merge net shapes to avoid having false LVS violations
+config_lvs -merge_ports true
+
+# =======================
+# Read design constraints
+# =======================
+config_units -value_type time -units nano
+fk_msg "Reading constraints"
+
+foreach mode $MGC_modes {
+      fk_msg "Loading ${mode} Constraints"
+      fk_msg "PT file path $MGC_importConstraintsFile($mode)"
+      if {[file extension $MGC_importConstraintsFile($mode)] == ".mxdb" } {
+         fk_msg  "Reading Constraints from MXDB for Mode $mode"
+         read_mxdb -skip { def directives library netlist scandef } -file $MGC_importConstraintsFile($mode) -nitro_mode $mode
+      } else {
+          read_constraints \
+           -modes $mode \
+           -file $MGC_importConstraintsFile($mode) \
+           -clock_suffix _${mode}
+      }
+}
+
+# If no power domains yet exist, read UPF or create default power domain
+
+# check for propagated clocks
+nrf_utils::check_for_propagated_clocks
+
+set re_write_lib false
+
+if { [llength [get_objects -type power_domain]] == 0 } {
+  if {$MGC_MultiVoltage} {
+      fk_msg -type info "Design is multivoltage; setting up MV environment."
+      if {[info exists MGC_UPF_File] && $MGC_UPF_File != ""} {
+          source $MGC_UPF_File 
+      } else {
+          fk_msg -type error "No UPF file found for MV setup." 
+      }
+      if {[info exists MGC_additional_MV_Setup_File] && $MGC_additional_MV_Setup_File != ""} {
+         source $MGC_additional_MV_Setup_File
+      }
+
+      config_mv -name enable_pgsite_mode -value false      
+      config_mv -name const_net_tie_to_related_supply -value true      
+      enable_mv
+      check_mv
+
+# Re-save libs in case lib cell updates were made in UPF
+      set re_write_lib true
+  } elseif {[info exists MGC_UPF_File] && $MGC_UPF_File != ""} {
+      fk_msg -type info "Design is not MV, but reading UPF file for power intent."
+      source $MGC_UPF_File
+
+# Re-save libs in case lib cell updates were made in UPF
+      set re_write_lib true
+  } else {
+      if {$MGC_primary_power_net == "" || $MGC_primary_ground_net == ""} {
+        puts ""
+        fk_msg -type error "Variables MGC_primary_power_net & MGC_primary_ground_net must be defined in import_variables.tcl.\n"
+        exit -1
+      }
+      fk_msg -type info "Creating default power domain to identify primary power and ground supplies."
+      create_power_domain -domain DEFAULT_PD
+      create_supply_net $MGC_primary_power_net -domain DEFAULT_PD  -power_net true
+      create_supply_net $MGC_primary_ground_net -domain DEFAULT_PD   -power_net false
+      set_domain_supply_net -domain DEFAULT_PD -primary_power_net $MGC_primary_power_net -primary_ground_net $MGC_primary_ground_net
+  } 
+}
+
+if {[lpp::create_cell_edge_constraints]} {
+  set re_write_lib true
+}
+
+set pgb_lcells [prepare_cell_pg_blockages]
+if {[llength $pgb_lcells]} {
+  set re_write_lib true
+}
+
+# =======
+# Save DB
+# =======
+if {$MGC_split_db} {
+    if {$re_write_lib} {
+        write_db -data lib -file dbs/libs.db
+    }
+    write_db -data design -file dbs/import.db
+} else {
+    write_db -data all -file dbs/import.db
+}
+
+# =======
+# RUN Import design checks 
+# =======
+if { [info exists MGC_nrf_custom_scripts_dir] && $MGC_nrf_custom_scripts_dir != "" && [file exists $MGC_nrf_custom_scripts_dir/scr/import_checks.tcl] } {
+    fk_msg "Sourcing custom NRF script $MGC_nrf_custom_scripts_dir/scr/import_checks.tcl"
+    source $MGC_nrf_custom_scripts_dir/scr/import_checks.tcl
+} else {
+    fk_msg "Sourcing standard NRF script $nrf_dir/scr/import_checks.tcl"
+    source $nrf_dir/scr/import_checks.tcl
+}
+report_messages
+
+#if { [info exists MGC_no_exit] && $MGC_no_exit } { 
+#    #continue 
+#} else {
+#    exit
+#}
+
+#####################################################
+## Copyright Mentor, A Siemens Business            ##
+## All Rights Reserved                             ##
+##                                                 ##
+## THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY ##
+## INFORMATION WHICH ARE THE PROPERTY OF MENTOR    ##
+## GRAPHICS CORPORATION OR ITS LICENSORS AND IS    ##
+## SUBJECT TO LICENSE TERMS.                       ##
+#####################################################
+puts "
+#####################################################
+## Nitro Reference Flow : Import Stage             ##
+##                                                 ##
+## Imports technology & design info to prepare     ##
+## design for NRF place and route.                 ##
+#####################################################
+"
+fk_msg -set_prompt NRF
+#config_units -value_type distance -units micro
+config_shell -echo_script false
+
+# ==============
+# Read libraries and variables
+# ==============
+if { [info exists MGC_tanner_flow] && $MGC_tanner_flow eq "true"} {
+    fk_msg -type info "Running Nitro-AMS : Import Stage" 
+} else {
+    source import_variables.tcl  
+}
+
+set tmpdir [file dirname $sierra_tcl_dir]
+set nrf_dir ${tmpdir}/ref_flows/tcl
+
+if { [info exists MGC_nrf_custom_scripts_dir] && $MGC_nrf_custom_scripts_dir != "" && [file exists $MGC_nrf_custom_scripts_dir/scr/kit_utils.tcl] } {
+    fk_msg "Sourcing custom NRF script $MGC_nrf_custom_scripts_dir/scr/kit_utils.tcl"
+    source $MGC_nrf_custom_scripts_dir/scr/kit_utils.tcl
+} else {
+    fk_msg "Sourcing standard NRF script $nrf_dir/scr/kit_utils.tcl"
+    source $nrf_dir/scr/kit_utils.tcl
+}
+
+set MGC_flowStage import
+
+load_utils -name nrf_utils 
+load_utils -name save_nrf_import_vars -force
+
+## make sure that user input is valid for all stages
+set num_errors [nrf_utils::check_import_variables]
+if { $num_errors > 0 } {
+    fk_msg -type error "Please fix all errors to continue execution"
+    return -code error
+}
+
+nrf_utils::save_nrf_import_vars
+
+# ==========
+# Multi CPUs
+# ==========
+config_application -cpus $MGC_cpus
+config_timing -cpus $MGC_cpus
+
+# If resuming import after manual floorplanning, skip to post-floorplan for resuming execution
+
+if { ![info exists MGC_resume_import] || !$MGC_resume_import } {
+
+# Read in technology libraries if no library DB exists, else read library DB
+
+if {$MGC_libDbPath =="" || ![file exists $MGC_libDbPath]} {
+    fk_msg "MGC_libDbPath : $MGC_libDbPath doesn't exist, Running library setup part of import stage and generate libs.db" 
+
+    # Source the rules.tcl file if provided
+    if {$MGC_tech_rules !="" && [file exists $MGC_tech_rules]} {
+        fk_msg "Reading TECHNO RULES File"
+        source $MGC_tech_rules
+    } else {
+        fk_msg "Since TECHNO RULE File is not provided or does not exist, technology rules must come from tech lef"
+    } 
+    # Source the vias.tcl file if provided 
+    if {$MGC_tech_vias !="" && [file exists $MGC_tech_vias]} {
+        source $MGC_tech_vias
+    }
+    # Source the dfm_vias.tcl file if provided
+    if {$MGC_tech_dfm_vias !="" && [file exists $MGC_tech_dfm_vias]} {
+        source $MGC_tech_dfm_vias
+    }
+
+    # Tech lef is used instead of rules.tcl for technologies 40nm and above
+    if {$MGC_physical_library_tech !="" && [file exists $MGC_physical_library_tech]} {
+        fk_msg "Reading TECH LEF File"
+        read_lef -file $MGC_physical_library_tech
+    }
+
+    if {$MGC_physical_libraries !=""} {
+	fk_msg "Reading Cell LEF Files"
+	read_lef -files "$MGC_physical_libraries"
+    }
+
+    # Read the ptf files
+    foreach parasiticsCorner [array name MGC_parasitic_library] {
+        fk_msg "Load $parasiticsCorner technology .PTF"
+        read_lib $MGC_parasitic_library($parasiticsCorner) -layer_map_file $MGC_itf_to_lef_layer_map -name_prefix $parasiticsCorner
+    }
+
+    # Read the lib files
+    foreach lib_corner [array name MGC_timing_library] {
+        read_library -skip_ccs $MGC_skip_ccs -files $MGC_timing_library($lib_corner) -name_prefix $lib_corner
+    }
+
+    # Perform preprocess lib : it has internal check for node won't do any pre-processing for node > 20
+    if { [info exists MGC_tanner_flow] && $MGC_tanner_flow eq "true"} {
+        #continue 
+    } else {
+        preprocess_library -categories auto 
+    }
+
+    # ====================
+    # Save intermediate db
+    # ====================
+
+    if {$MGC_split_db} {
+        write_db -data lib -file dbs/libs.db
+    } else {
+        write_db -data all -file dbs/import_libs.db
+    }
+} else {
+    fk_msg "Reading Library Database : $MGC_libDbPath : skipping lib gen step"
+    if { [file isfile $MGC_libDbPath] } {
+        # Old DB -- Convert to 2.5
+        load_utils -name db_utils
+        util::update_lib_db -lib_db $MGC_libDbPath
+    } else {
+        read_db -file $MGC_libDbPath
+    }
+    file mkdir dbs
+    if {![file exists dbs/libs.db]} {
+        fk_msg "Creating link dbs/libs.db : $MGC_libDbPath"
+        file link -symbolic dbs/libs.db $MGC_libDbPath
+    } else { 
+        fk_msg -type warning "dbs/libs.db path already exists, make sure MGC_libDbPath is pointing to the same file. All following flow step will use dbs/lib.db"
+    }
+}
+
+set_analysis_corner fast -enable false
+set_analysis_corner slow -enable false
+foreach corner $MGC_corners {
+    set_analysis_corner -corner $corner \
+       			-enable true \
+       			-setup true \
+       			-hold true \
+       			-crpr setup_hold \
+       			-library [get_objects electrical_lib *$MGC_CornerTiming($corner)*] \
+       			-process [get_libs -type process -filter file=="[string trim $MGC_parasitic_library($MGC_CornerParasitic($corner))]"] \
+       			-rc_temp $MGC_CornerTemperature($corner)
+}
+
+report_analysis_corner
+
+# ==============
+# Import netlist
+# ==============
+fk_msg "Reading netlist $MGC_importVerilogNetlist"
+# to handle correctly tie-up/tie-low connections in a multi-supply design
+#TODO: workaround till conver_supply_nets_to_pg is true default
+config_default_value -command read_verilog -argument convert_supply_nets_to_pg -value true
+if {[info exists MGC_mxdb_flow] && $MGC_mxdb_flow } {
+    if {[info exists MGC_mxdb_path] && $MGC_mxdb_path !=""} {
+        #read_mxdb -skip { def directives library netlist scandef SDC } -file $MGC_mxdb_path
+        read_mxdb -skip { library SDC } -file $MGC_mxdb_path
+    } else { 
+        fk_msg -type error "MGC_mxdb_flow is set to true : Provide valid path to mxdb by setting MGC_mxdb_path or set MGC_mxdb_flow to false" 
+    }
+} else {
+    read_verilog $MGC_importVerilogNetlist
+}
+
+if { [info exists MGC_topDesign] && $MGC_topDesign != "" } {
+    current_design $MGC_topDesign
+}
+
+# ============
+# Avoid assign
+# ============
+config_optimize -dont_create_assign
+
+# ==========
+# Enable ccs
+# ==========
+
+if {!$MGC_skip_ccs} {
+    fk_msg "Info: Setting delay model to current"
+    set_delay_model -base_model current
+} else {
+    fk_msg "Info: Setting delay model to voltage"
+    set_delay_model -base_model voltage
+}
+report_delay_model
+
+# ===========================
+# Define implementation modes
+# ===========================
+foreach mode $MGC_modes {
+    define_design_mode $mode
+}
+foreach mode $MGC_modes {
+    set_design_mode $mode -enable true -corners $MGC_cornersPerMode($mode)
+}
+
+set_design_mode default -enable false
+report_design_mode
+
+# =============
+# Read def file
+# ============
+
+if { [info exists MGC_floorLoadDefFile] && $MGC_floorLoadDefFile != "" } {
+    read_def -skip {regions} $MGC_floorLoadDefFile
+}
+
+if { [info exists MGC_nrf_floorplanning] && $MGC_nrf_floorplanning eq "auto"} {
+    if { [info exists MGC_nrf_custom_scripts_dir] && $MGC_nrf_custom_scripts_dir != "" && [file exists $MGC_nrf_custom_scripts_dir/scr/floorplan.tcl] } {
+        fk_msg "Sourcing custom NRF script $MGC_nrf_custom_scripts_dir/scr/floorplan.tcl\n"
+        source $MGC_nrf_custom_scripts_dir/scr/floorplan.tcl
+    } else {
+        fk_msg "Sourcing standard NRF script $nrf_dir/scr/floorplan.tcl\n"
+        source $nrf_dir/scr/floorplan.tcl
+    }
+} elseif { $MGC_nrf_floorplanning eq "manual" } {
+    fk_msg "###############################################################"
+    fk_msg "#  NRF Import suspended for manual floorplanning.             #"
+    fk_msg "#  Perform floorplanning as desired.  When complete, execute: #"
+    fk_msg "#      resume_nrf_import                                      #"
+    fk_msg "#  to resume NRF import flow.                                 #"
+    fk_msg "###############################################################\n"
+    return
+} elseif { $MGC_nrf_floorplanning eq "none" } {
+    fk_msg "Skipping NRF floorplanning.\n"
+} else {
+    fk_msg -type warning "MGC_nrf_floorplanning setting $MGC_nrf_floorplanning is invalid.  Valid values: auto | manual | none.  Skipping NRF floorplanning.\n"
+}
+
+} ;  # If manually floorplanning, we will resume import execution here
+
+# Read additional floorplan script if provided
+
+if {[info exists MGC_floorplan_tcl_file] && $MGC_floorplan_tcl_file != ""} {
+    if { [file exists $MGC_floorplan_tcl_file] } {
+        fk_msg "Sourcing floorplan Tcl file $MGC_floorplan_tcl_file"
+        source $MGC_floorplan_tcl_file
+    } elseif { [info exists MGC_nrf_custom_scripts_dir] && $MGC_nrf_custom_scripts_dir != "" && [file exists $MGC_nrf_custom_scripts_dir/$MGC_floorplan_tcl_file] } {
+        fk_msg "Sourcing floorplan Tcl file $MGC_nrf_custom_scripts_dir/$MGC_floorplan_tcl_file"
+        source $MGC_nrf_custom_scripts_dir/$MGC_floorplan_tcl_file
+    } else {
+        fk_msg -type warning "Could not find file $MGC_floorplan_tcl_file.  Check MGC_floorplan_tcl_file setting."
+    }
+}
+
+# Read scan DEF file if provided
+
+if {[info exists MGC_scan_def_file] && [string trim $MGC_scan_def_file] !=""} {
+    if {[info exists MGC_mxdb_flow] && $MGC_mxdb_flow } {
+        fk_msg -type info "Scan DEF is already loaded from mxdb"
+    } else {
+        read_def -sections {scan_chains} -skip {} -file $MGC_scan_def_file
+    }
+}
+
+# =================================
+# Check design for unresolved cells
+# =================================
+check_design -check cells
+set unresolved_cells [get_cells -of_objects [get_objects -type error -filter @name==unresolved]]
+if {[llength $unresolved_cells] > 0} {
+  fk_msg -type error "Design has [llength $unresolved_cells] unresolved cells that must be fixed before proceeding."
+  foreach c $unresolved_cells {
+    puts "\t$c of cell type [get_lib_cell -of $c]"
+  }
+  exit -1
+}
+
+# =======================
+# Check for top partition
+# =======================
+
+if {[llength [get_top_partition]] == 0} {
+  fk_msg -type error "No partition has been created.  Check floorplan and/or input DEF file.\n"
+  exit -1
+}
+
+# ================
+# Check and Re-create tracks
+# ================
+set node [get_config -name process -param node]
+if {$node > 22 || $node=="unknown"} {
+    ## Create tracks for nodes above 22nm. 
+    fk_msg "Creating new tracks on all layers"
+    remove_objects -objects [get_objects -type track]
+    create_tracks
+} else { 
+    check_floorplan -check no_tracks
+    set track_errs [get_objects -type error -filter (@category==floorplan)&&(@name==no_tracks)]
+    if {[llength $track_errs] } {
+        fk_msg -type error "No preferred direction routing tracks on the layers: [get_objects -type layer -of_objects $track_errs]"
+        fk_msg  "Review and create tracks on missing layers : using command create_tracks" 
+        return -code error
+    }
+}
+# Control generated vias based on user setting or node
+if { [info exists MGC_disable_SDA_vias_creation] && $MGC_disable_SDA_vias_creation } {
+    config_lib_vias -use_generated false -create false -select true -use_asymmetrical true -use_4cut true
+} elseif {$node > 28 || $node=="unknown"} {
+    config_lib_vias -use_generated true -create true -select true -use_asymmetrical true -use_4cut true
+} else {
+    config_lib_vias -use_generate false
+}
+
+# Merge net shapes to avoid having false LVS violations
+config_lvs -merge_ports true
+
+# =======================
+# Read design constraints
+# =======================
+config_units -value_type time -units nano
+fk_msg "Reading constraints"
+
+foreach mode $MGC_modes {
+      fk_msg "Loading ${mode} Constraints"
+      fk_msg "PT file path $MGC_importConstraintsFile($mode)"
+      if {[file extension $MGC_importConstraintsFile($mode)] == ".mxdb" } {
+         fk_msg  "Reading Constraints from MXDB for Mode $mode"
+         read_mxdb -skip { def directives library netlist scandef } -file $MGC_importConstraintsFile($mode) -nitro_mode $mode
+      } else {
+          read_constraints \
+           -modes $mode \
+           -file $MGC_importConstraintsFile($mode) \
+           -clock_suffix _${mode}
+      }
+}
+
+# If no power domains yet exist, read UPF or create default power domain
+
+# check for propagated clocks
+nrf_utils::check_for_propagated_clocks
+
+set re_write_lib false
+
+if { [llength [get_objects -type power_domain]] == 0 } {
+  if {$MGC_MultiVoltage} {
+      fk_msg -type info "Design is multivoltage; setting up MV environment."
+      if {[info exists MGC_UPF_File] && $MGC_UPF_File != ""} {
+          source $MGC_UPF_File 
+      } else {
+          fk_msg -type error "No UPF file found for MV setup." 
+      }
+      if {[info exists MGC_additional_MV_Setup_File] && $MGC_additional_MV_Setup_File != ""} {
+         source $MGC_additional_MV_Setup_File
+      }
+
+      config_mv -name enable_pgsite_mode -value false      
+      config_mv -name const_net_tie_to_related_supply -value true      
+      enable_mv
+      check_mv
+
+# Re-save libs in case lib cell updates were made in UPF
+      set re_write_lib true
+  } elseif {[info exists MGC_UPF_File] && $MGC_UPF_File != ""} {
+      fk_msg -type info "Design is not MV, but reading UPF file for power intent."
+      source $MGC_UPF_File
+
+# Re-save libs in case lib cell updates were made in UPF
+      set re_write_lib true
+  } else {
+      if {$MGC_primary_power_net == "" || $MGC_primary_ground_net == ""} {
+        puts ""
+        fk_msg -type error "Variables MGC_primary_power_net & MGC_primary_ground_net must be defined in import_variables.tcl.\n"
+        exit -1
+      }
+      fk_msg -type info "Creating default power domain to identify primary power and ground supplies."
+      create_power_domain -domain DEFAULT_PD
+      create_supply_net $MGC_primary_power_net -domain DEFAULT_PD  -power_net true
+      create_supply_net $MGC_primary_ground_net -domain DEFAULT_PD   -power_net false
+      set_domain_supply_net -domain DEFAULT_PD -primary_power_net $MGC_primary_power_net -primary_ground_net $MGC_primary_ground_net
+  } 
+}
+
+if {[lpp::create_cell_edge_constraints]} {
+  set re_write_lib true
+}
+
+set pgb_lcells [prepare_cell_pg_blockages]
+if {[llength $pgb_lcells]} {
+  set re_write_lib true
+}
+
+# =======
+# Save DB
+# =======
+if {$MGC_split_db} {
+    if {$re_write_lib} {
+        write_db -data lib -file dbs/libs.db
+    }
+    write_db -data design -file dbs/import.db
+} else {
+    write_db -data all -file dbs/import.db
+}
+
+# =======
+# RUN Import design checks 
+# =======
+if { [info exists MGC_nrf_custom_scripts_dir] && $MGC_nrf_custom_scripts_dir != "" && [file exists $MGC_nrf_custom_scripts_dir/scr/import_checks.tcl] } {
+    fk_msg "Sourcing custom NRF script $MGC_nrf_custom_scripts_dir/scr/import_checks.tcl"
+    source $MGC_nrf_custom_scripts_dir/scr/import_checks.tcl
+} else {
+    fk_msg "Sourcing standard NRF script $nrf_dir/scr/import_checks.tcl"
+    source $nrf_dir/scr/import_checks.tcl
+}
+report_messages
+
+#if { [info exists MGC_no_exit] && $MGC_no_exit } { 
+#    #continue 
+#} else {
+#    exit
+#}
+

abdelazeem201_ASIC-Design-Roadmap/mentor_scripts/1_place.tcl

@@ -0,0 +1,228 @@
+#####################################################
+## Copyright Mentor, A Siemens Business            ##
+## All Rights Reserved                             ##
+##                                                 ##
+## THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY ##
+## INFORMATION WHICH ARE THE PROPERTY OF MENTOR    ##
+## GRAPHICS CORPORATION OR ITS LICENSORS AND IS    ##
+## SUBJECT TO LICENSE TERMS.                       ##
+#####################################################
+puts "
+#####################################################
+## Nitro Reference Flow : Place Stage              ##
+##                                                 ##
+## Loads design from import stage, prepares for    ##
+## and then runs run_place_timing                  ##
+#####################################################
+"
+set MGC_flowStage place 
+fk_msg -set_prompt NRF
+
+###Setting design and technology variables
+source flow_variables.tcl 
+source scr/kit_utils.tcl
+load_utils -name nrf_utils 
+load_utils -name save_vars
+load_utils -name db_utils
+
+config_application -cpus $MGC_cpus
+config_timing -cpus $MGC_cpus
+
+# Read db
+if {![string length [get_top_partition]]} {
+    if { [file exists dbs/libs.db] } {
+	## split_db is true
+        if { [file isfile dbs/libs.db] } {
+            # Old DB -- Convert to 2.5
+            util::update_split_db -lib_db dbs/libs.db -design_db dbs/import.db
+        } else {
+            read_db -file dbs/libs.db
+            read_db -file dbs/import.db
+        }
+        config_default_value -command write_db -argument data -value design
+    } else {
+        if { [file isfile dbs/import.db] } {
+            # Old DB -- Convert to 2.5
+            util::update_full_db -design_db dbs/import.db
+        } else {
+            read_db -file dbs/import.db
+        }
+    }
+}
+
+#Source Custom NDR file before checks
+if { [info exist MGC_customNdrFile] && $MGC_customNdrFile != "" } {
+    fk_msg -type info "Using Custom NDR File : $MGC_customNdrFile. Please ensure to include set_cts_routing_rule as well in the file."
+    source $MGC_customNdrFile
+    }
+
+
+## make sure that user input is valid for all stages
+set num_errors 0
+incr num_errors [nrf_utils::check_flow_variables $MGC_flowStage]
+if { $num_errors > 0 } {
+    fk_msg -type error "Please fix all errors to continue execution"
+    return -code error
+}
+util::save_vars
+
+# ===========================================================================================
+# START of PLACE STAGE
+# ==========================================================================================
+check_design 
+config_shell -echo_script true
+
+# Target Scenario Management : saving curent scenarios, enabling modes and corners for a stage
+nrf_utils::save_scenarios
+nrf_utils::configure_scenarios $MGC_flowStage
+nrf_utils::check_for_propagated_clocks
+
+# For now only set power corner if user defined
+if { $MGC_powerCorner != "" } {
+    config_nitro_flow -name power_corner -value $MGC_powerCorner
+}
+
+# Target Library Management: preparing and setting dont use cell list : # This Proc is in scr/kit_utils.tcl
+nrf_utils::configure_target_libs $MGC_flowStage
+
+# Set routing layers:
+if { ![nrf_utils::configure_routing_layers] } {
+    return -code error
+}
+
+lpp::create_cell_edge_constraints
+
+# Generic configs:
+set_crpr_spec -method margin_based
+config_default -command compile_scan -argument cross_chain_optimization -value false
+config_place_detail -name min_filler_space -value $MGC_min_filler_space
+
+# Use this file to source the needed files to set OCV derates. Can be either "regular OCV" or "AOCV" 
+# In case of POCV we recommend to use it starting from POST-CTS stage 
+source scr/ocv.tcl
+if {$MGC_OCV == "aocv"} {
+    fk_msg "Enabling AOCV; please make sure you sourced appropraite AOCV files/settings using src/ocv.tcl"
+    config_timing -advanced_ocv true
+}
+## get_config_value is proc in scr/kit_utils.tcl
+if {[get_config_value config_timing parametric_ocv]} { 
+    fk_msg -type info "POCV is enabled in import database. Enabling graph based CRPR which is needed for POCV. Pleaase ensure POCV setup is done properly." 
+    set_crpr_spec -method graph_based
+}
+
+# Prepare path groups
+nrf_utils::configure_path_groups
+
+### Avoid assign
+config_optimize -dont_create_assign
+
+#############################################################
+### Apply NDR to clock nets for congestion estimation
+### Priority: 1) MGC_customNdrFile; 2) MGC_CLOCK_NDR_NAME 3) Default, MGC_NdrSpaceMultiplier & MGC_NdrWidthMultiplier
+###   MGC_NdrWidthMultiplier and MGC_NdrSpaceMultiplier are prefered way of defining clock NDR
+###   If MGC_CLOCK_NDR_NAME is set : NDR with this name must exist 
+###   NDR setup uses layers: MGC_CtsBottomPreferredLayer, MGC_CtsTopPreferredLayer, and $MGC_MaxRouteLayer
+###   and special vias: MGC_clock_route_ndr_vias 
+###   Shielding is controlled by MGC_applyShield, and it uses MGC_clock_shield_net
+if { $MGC_customNdrFile == "" } {
+    fk_msg -type info "Deriving Clock NDR from technology."
+    if { ![nrf_utils::setup_clock_ndr_and_shield] } {
+	 return -code error
+    }
+}
+
+set_rcd_models -stage pre_cts
+# Source Timer & Extractor configs
+source scr/config.tcl
+
+config_optimize -allow_reroute true -nondef_rule "" 
+config_timing -disable_clock_gating_checks false
+
+if {$MGC_place_high_effort_congestion} {
+    config_place_timing -name congestion_effort -value high
+}
+
+# Clock offset optimization
+if { [info exists MGC_activeCorners(place:hold)] && $MGC_activeCorners(place:hold) != "" } {
+    config_clockdata_optimize -name hold_corners -value $MGC_activeCorners(place:hold)
+}
+
+# WARNING!: Following flow config are not stored in the DB" #
+config_flows -preserve_rcd true
+
+### Max Length Constraint to be honored during optimization
+set_max_length -length_threshold $MGC_maxLengthParam 
+fk_msg "Max Length Set to [report_max_length]"
+
+# constrain the clock maximum transition for better SI results later
+nrf_utils::set_clock_based_max_transition
+
+### Define Low power effort OPT effort for RPT
+if { $MGC_powerEffort != "none" } {
+    config_place_timing -name low_power_effort -value $MGC_powerEffort 
+    if { $MGC_saifFile == "" } {
+        fk_msg -type warning "Please provide SAIF file when running low power flow. Power analysis will be inaccurate otherwise."
+    } else {
+        read_saif -file $MGC_saifFile 
+        #TODO: Check how to find saif annotation : add it in checks
+    }   
+    ## create leakage groups and enable optimization leakage control
+    set num_groups [ipo_vt_expert -create]
+    if { $num_groups >= 2 } {
+        config_nitro_flow -name enable_leakage_control -value true
+    }
+}
+
+### Set buffer and inverter lists for more accurately estimation of the clock offset step
+nrf_utils::configure_cts_engine $MGC_flowStage
+
+# constrain the clock ideal transition for better timing convergence
+nrf_utils::check_ideal_clock_transitions
+
+nrf_utils::report_timer_configs 
+# ===========================================================================================
+# RUN_PLACE_TIMING 
+# ===========================================================================================
+if { [file exists nrf_customization.tcl] } {
+    source nrf_customization.tcl
+}
+
+## Remove assign
+if {$MGC_fix_assigns } {
+    ipo_sweep_assigns -place_cell false -message verbose
+}
+
+## Enable N2N synthesis : Remapping in 0RC mode
+if {$MGC_high_effort_remap} {
+    run_0rc_remap
+    config_place_timing -name enable_remap_optimization -value true
+}
+
+run_place_timing -effort $MGC_flow_effort  -skip_precondition $MGC_skip_precondition -messages verbose 
+
+# Optional additional optimizations to improve timing closure
+if { $MGC_enable_pre_cts_incr } {
+    source scr/pre_cts_incr.tcl
+}
+# ===========================================================================================
+# END of PLACE STAGE
+# ===========================================================================================
+if { [file exists dbs/libs.db] } {
+    ## split_db is true
+    write_db -data design -file dbs/place.db
+} else {
+    write_db -data all -file dbs/place.db
+}
+if { $MGC_powerEffort != "none" && $MGC_saifFile != "" } {
+    ## Getting one mode to write saif 
+    set saifMode [nrf_get_saif_mode $MGC_powerCorner]
+    write_saif dbs/place.saif.gz -mode $saifMode
+}
+nrf_utils::write_reports $MGC_flowStage reports 100
+
+#if { [info exists MGC_no_exit] && $MGC_no_exit eq "true" } { 
+#    #continue
+#} else {
+#    exit
+#}
+

abdelazeem201_ASIC-Design-Roadmap/mentor_scripts/2_clock.tcl

@@ -0,0 +1,233 @@
+#####################################################
+## Copyright Mentor, A Siemens Business            ##
+## All Rights Reserved                             ##
+##                                                 ##
+## THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY ##
+## INFORMATION WHICH ARE THE PROPERTY OF MENTOR    ##
+## GRAPHICS CORPORATION OR ITS LICENSORS AND IS    ##
+## SUBJECT TO LICENSE TERMS.                       ##
+#####################################################
+puts "
+#####################################################
+## Nitro Reference Flow : Clock Stage              ##
+##                                                 ##
+## Loads design from place stage, prepares for     ##
+## and then runs run_clock_timing                  ##
+#####################################################
+"
+
+set MGC_flowStage clock
+fk_msg -set_prompt NRF
+
+###Setting design and technology variables
+source flow_variables.tcl
+source scr/kit_utils.tcl
+load_utils -name nrf_utils 
+load_utils -name save_vars
+load_utils -name db_utils
+
+config_application -cpus $MGC_cpus
+config_timing -cpus $MGC_cpus
+
+# Read db
+if {![string length [get_top_partition]]} {
+    if { [file exists dbs/libs.db] } {
+	## split_db is true
+        if { [file isfile dbs/libs.db] } {
+            util::update_split_db -lib_db dbs/libs.db -design_db dbs/place.db
+        } else {
+            read_db -file dbs/libs.db
+            read_db -file dbs/place.db
+        }
+        config_default_value -command write_db -argument data -value design
+    } else {
+        if { [file isfile dbs/place.db] } {
+            util::update_full_db -design_db dbs/place.db
+        } else {
+            read_db -file dbs/place.db
+        }
+    }
+}
+set num_errors [nrf_utils::check_flow_variables $MGC_flowStage]
+if { $num_errors > 0 } {
+    fk_msg -type error "Please fix all errors to continue execution"
+    return -code error
+}
+util::save_vars
+
+# ===========================================================================================
+# START of CLOCK STAGE
+# ==========================================================================================
+check_design 
+config_shell -echo_script true
+
+# ===========================================================================================
+# Default settings
+# ===========================================================================================
+# Objective for automated CTS repeater selection
+set MGC_cts_repeater_pruning_objective delay ; # Valid values: area delay driver_res input_cap leakage total_power
+
+# CG Pruning settings
+set MGC_ck_cg_apply_pruning true
+
+# Usage of dont_use cells for GC Optimization
+set MGC_ck_cg_use_dont_use false
+
+# CTS engine tuning
+set cts_partition_skew_threshold 0.50
+set cts_compile_local_refine_skew_factor 0.30
+set cts_intrinsic_repeater_delay_new true
+
+# ===========================================================================================
+# TECHNO / LIB 
+# ===========================================================================================
+
+# Don't let the tool use its own generated vias 
+# Generated vias rules are provided
+set node [get_config -name process -param node]
+if {$node > 28 || $node=="unknown"} {
+    config_lib_vias -use_generated  true -create true -select true -use_asymmetrical true -use_4cut true
+} else {
+    config_lib_vias -use_generate false
+}
+
+# ===========================================================================================
+# GENERIC  
+# ===========================================================================================
+
+config_name_rule -cell CLOCK -net CLOCK
+config_timing -use_annotated_cts_offsets false
+
+# ===========================================================================================
+# GR 
+# ===========================================================================================
+config_route_global -category user_defined
+fk_msg "Applying NRF non-default GR settings"
+config_route_global -name gr_full_timing_update_thresh -value 0.0
+
+# ===========================================================================================
+# TIMING CONSTRAINTS - MCMM
+# ===========================================================================================
+if {[file exists scr/reload_constraints_${MGC_flowStage}.tcl]} {
+    source scr/reload_constraints_${MGC_flowStage}.tcl
+}
+nrf_utils::configure_scenarios $MGC_flowStage
+nrf_utils::configure_target_libs $MGC_flowStage
+
+# Set routing layers:
+if { ![nrf_utils::configure_routing_layers] } {
+    return -code error
+}
+
+lpp::create_cell_edge_constraints
+
+#constraining clock transition for SI
+nrf_utils::set_clock_based_max_transition
+
+# Force tight max_transition constraint on macros' data pins
+if { $MGC_max_trans_on_macro_pins_value != 0 } {
+    foreach pin [ get_pins -of_objects [ get_cells -filter is_macro ] -filter direction==in&&!@is_clock_pin ] {
+        set_max_transition $MGC_max_trans_on_macro_pins_value [ get_pins $pin ]
+    }
+}
+
+# ===========================================================================================
+# OCV - CRPR 
+# ===========================================================================================
+# Use this file to source the needed files to set OCV derates. Can be either "regular OCV" or "AOCV" or "POCV" 
+source scr/ocv.tcl
+if {$MGC_OCV == "aocv"} {
+    fk_msg "Enabling AOCV; please make sure you sourced appropraite AOCV files/settings using src/ocv.tcl"
+    config_timing -advanced_ocv true
+}
+if {$MGC_OCV== "pocv"} {
+    fk_msg "Enabling POCV; please make  sure you sourced appropraite POCV files/settings using scr/ocv.tcl"
+    config_timing -parametric_ocv true
+    config_report_timing -add_columns variation
+}
+set_crpr_spec -method graph_based
+set_crpr_spec -crpr_threshold $MGC_crpr_threshold
+source scr/config.tcl
+
+# ===========================================================================================
+# HOLD 
+# ===========================================================================================
+set_property -name is_dont_use -value true -objects [get_lib_cells $MGC_DLY_cells]
+config_flows -hold_opt_cell_list [ get_lib_cells $MGC_DLY_cells ]
+
+# ===========================================================================================
+# MV - POWER 
+# ===========================================================================================
+if { $MGC_powerEffort != "none" && $MGC_saifFile != "" } {
+    read_saif -file dbs/place.saif.gz
+} 
+## Define Low power effort OPT effort for RCT
+if { $MGC_powerEffort != "none"} {
+    config_clock_timing -name low_power_effort -value $MGC_powerEffort
+}
+if { $MGC_powerCorner != {} } { 
+    config_clock_timing -name dont_prune_corners -value $MGC_powerCorner
+}
+
+# ===========================================================================================
+# CTS
+# ===========================================================================================
+nrf_utils::configure_cts_engine $MGC_flowStage
+
+config_clock_timing -name refine_cts -value $MGC_clock_refine_cts
+fk_msg "Cleaning up NRF-generated pre-existing NDR/Shield rules on clock nets before CTS Buffering. Custom rules, if any,  are kept."
+set candidate_nets [filter_collection [collect_clock_nets] -expression "@nondefault_rule~=MGC_CLK_NDR_*"]
+if {[sizeof_collection $candidate_nets] > 0} {
+	set_property -name nondefault_rule -value "" -object $candidate_nets
+	set_property -name shield_rule -value "" -object $candidate_nets
+}
+
+nrf_utils::report_timer_configs 
+
+# ===========================================================================================
+# RUN_CLOCK_TIMING 
+# ===========================================================================================
+config_clock_timing -name preserve_rcd_models -value true
+config_clock_timing -name enable_optimize_clock_tree -value $MGC_enable_clock_data_opt
+# Preserving CTS Reference corner from Pruning
+set current_excluded_corners_for_pruning [config_clock_timing -name dont_prune_corners]
+config_clock_timing -name dont_prune_corners -value [add_to_collection -unique true -object [get_corners $current_excluded_corners_for_pruning] -add [get_corners $::MGC_activeCorners(clock:ref)]]
+
+###Max length constraint for optimization
+config_optimize -buffer_removal_max_length_limit $MGC_maxLengthParam
+
+if { [file exists nrf_customization.tcl] } {
+    source nrf_customization.tcl
+}
+
+run_clock_timing -cpus $MGC_cpus
+
+## Insert tie-cells
+if {$MGC_tie_low_cell ne "" && $MGC_tie_high_cell ne ""} {
+    nrf_utils::insert_tie_cells
+    fk_msg -type info "Running tie cells insertion."
+} else {
+    fk_msg -type info "Skipping tie cells insertion."
+}
+# ===========================================================================================
+# END of CLOCK STAGE
+# ===========================================================================================
+if { [file exists dbs/libs.db] } {
+    ## split_db is true
+    write_db -data design -file dbs/clock.db
+} else {
+    write_db -data all -file dbs/clock.db
+}
+if { $MGC_powerEffort != "none" && $MGC_saifFile != "" } {
+    ## Getting one mode to write saif 
+    set saifMode [nrf_get_saif_mode $MGC_powerCorner]
+    write_saif dbs/clock.saif.gz -mode $saifMode
+}
+nrf_utils::write_reports $MGC_flowStage reports 100
+
+#if { [info exists MGC_no_exit] && $MGC_no_exit eq "true" } { 
+#    #continue
+#} else {
+#    exit
+#}
+

abdelazeem201_ASIC-Design-Roadmap/mentor_scripts/3_route.tcl

@@ -0,0 +1,167 @@
+# ==================================================================
+#  NITRO  KIT
+#  Task : routing
+#  Description: track/detail routing and final timing driven routing
+# ==================================================================
+puts "
+#####################################################
+## Nitro Reference Flow : Route Stage              ##
+##                                                 ##
+## Loads design from clock stage, prepares for     ##
+## and then runs run_route_timing                  ##
+#####################################################
+"
+
+set MGC_flowStage route
+fk_msg -set_prompt NRF
+
+###Setting design and technology variables
+source flow_variables.tcl
+source scr/kit_utils.tcl
+load_utils -name nrf_utils 
+load_utils -name save_vars
+load_utils -name db_utils
+
+config_application -cpus $MGC_cpus
+config_timing -cpus $MGC_cpus
+
+# Read db
+if {![string length [get_top_partition]]} {
+    if { [file exists dbs/libs.db] } {
+	# Split db is used
+        if { [file isfile dbs/libs.db] } {
+            # Old DB -- Convert to 2.5
+            util::update_split_db -lib_db dbs/libs.db -design_db dbs/clock.db
+        } else {
+            read_db -file  dbs/libs.db
+            read_db -file  dbs/clock.db
+        }
+        config_default_value -command write_db -argument data -value design
+    } else {
+        if { [file isfile dbs/clock.db] } {
+            # Old DB -- Convert to 2.5
+            util::update_full_db -design_db dbs/clock.db
+        } else {
+            read_db -file dbs/clock.db
+        }
+    }
+}
+
+set num_errors [nrf_utils::check_flow_variables $MGC_flowStage]
+if { $num_errors > 0 } {
+    fk_msg -type error "Please fix all errors to continue execution"
+    return -code error
+}
+util::save_vars
+
+# ===========================================================================================
+# START of ROUTE STAGE
+# ==========================================================================================
+check_design 
+
+config_shell -echo_script true
+set MGC_rrt_opt true
+
+# Don't let the tool use its own generated vias 
+# Generated vias rules are provided
+set node [get_config -name process -param node]
+if {$node > 28 || $node=="unknown"} {
+    config_lib_vias -use_generated  true -create true -select true -use_asymmetrical true -use_4cut true
+} else {
+    config_lib_vias -use_generate false
+}
+
+lpp::create_cell_edge_constraints
+
+if { $MGC_powerEffort != "none" && $MGC_saifFile != "" } {
+    read_saif -file dbs/clock.saif.gz
+} 
+
+# Target Scenario Management : enabling modes and corners 
+# This Proc is in scr/kit_utils.tcl
+nrf_utils::configure_scenarios $MGC_flowStage
+# Target Library Management: preparing and setting dont use cell list
+# This Proc is in scr/kit_utils.tcl
+if {$MGC_rrt_opt} {
+    nrf_utils::configure_target_libs $MGC_flowStage
+}
+
+# Generic configs:
+config_timing -disable_clock_gating_checks false
+set_crpr_spec -method graph_based
+
+# Routing flow will set 2 rcd models internally: Postcts at first & then post_route after track routing
+# All user specified engine settings will be honored 
+config_flows -preserve_rcd false
+source scr/config.tcl
+
+config_route_timing -reset_all 
+
+# Enable DFM optimization by replacing DFM vias
+if {$MGC_replace_dfm} {
+    config_route_timing -name dvia_mode -value dfm
+}
+
+## Define Low power effort OPT effort for RRT
+if { $MGC_powerEffort != "none"} {
+    config_route_timing -name low_power_effort -value $MGC_powerEffort
+}
+
+## check if design is legal, if not - error
+if { [config_place_detail -name follow_drc_for] == {} } {
+    config_place_detail -name follow_drc_for -reset
+    set illegal_cells [get_illegal_cells]
+    if { [llength $illegal_cells] } {
+	fk_msg -type warning  "Flow was run with suppressed pre_route checks during legalization. As a result [llength $illegal_cells] cells are illegal."
+	#return -code error "Stop the flow due to illegal cells"
+    }
+}
+
+# ===========================================================================================
+# RUN_ROUTE_TIMING 
+# ===========================================================================================
+
+if { [file exists nrf_customization.tcl] } {
+    source nrf_customization.tcl
+}
+
+if {$MGC_rrt_opt} {
+    # configs for extraction in DR
+    config_extraction -use_thickness_variation false
+    config_extraction -use_thickness_variation_for_cap false
+    config_extraction -use_thickness_variation_for_res true
+    # CRPR
+    set_crpr_spec -crpr_threshold $MGC_crpr_threshold
+    set_crpr_spec -method graph_based
+    set_crpr_spec -transition same_transition
+    ### Max Length Constraint to be honored during optimization
+    fk_msg "Max Length Constraint"
+    set_max_length -length_threshold $MGC_maxLengthParam 
+    fk_msg "Max Length Set to [report_max_length]"
+    fk_msg "Running RRT with Interleave Optimization"
+    run_route_timing -mode interleave_opt -cpus $MGC_cpus -messages verbose
+} else {
+    run_route_timing -cpus $MGC_cpus -messages verbose
+}
+# ===========================================================================================
+# END of ROUTE STAGE
+# ===========================================================================================
+if { [file exists dbs/libs.db] } {
+    ## split_db is true
+    write_db -data design -file dbs/route.db
+} else {
+    write_db -data all -file dbs/route.db
+}
+if { $MGC_powerEffort != "none" && $MGC_saifFile != "" } {
+    ## Getting one mode to write saif 
+    set saifMode [nrf_get_saif_mode $MGC_powerCorner]
+    write_saif dbs/route.saif.gz -mode $saifMode
+}
+nrf_utils::write_reports $MGC_flowStage reports 100
+
+#if { [info exists MGC_no_exit] && $MGC_no_exit eq "true" } { 
+#    #continue
+#} else {
+#    exit
+#}
+

abdelazeem201_ASIC-Design-Roadmap/mentor_scripts/4_export.tcl

@@ -0,0 +1,246 @@
+######################################################
+### Copyright Mentor, A Siemens Business            ##
+### All Rights Reserved                             ##
+###                                                 ##
+### THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY ##
+### INFORMATION WHICH ARE THE PROPERTY OF MENTOR    ##
+### GRAPHICS CORPORATION OR ITS LICENSORS AND IS    ##
+### SUBJECT TO LICENSE TERMS.                       ##
+######################################################
+puts "
+######################################################
+#  Export Flow                                       #
+#                                                    #
+#  Fix process antennas, add fillers & metal fill    #
+#  Output design data.                               #
+#  Control vars defined in flow_variables.tcl        #
+#                                                    #
+######################################################
+"
+
+config_shell -echo_script false
+fk_msg -set_prompt NRF
+
+###Sourcing design and technology variables
+source flow_variables.tcl
+source scr/kit_utils.tcl
+load_utils -name nrf_utils 
+load_utils -name save_vars
+load_utils -name db_utils
+
+set MGC_flowStage export
+
+# Read DB
+if {![string length [get_top_partition]]} {
+    if { [file exists dbs/libs.db] } {
+	# Split db is used
+        if { [file isfile dbs/libs.db] } {
+            # Old DB -- Convert to 2.5
+            util::update_split_db -lib_db dbs/libs.db -design_db dbs/route.db
+        } else {
+	    read_db -file dbs/libs.db
+	    read_db -file dbs/route.db
+        }
+	config_default_value -command write_db -argument data -value design
+    } else {
+        if { [file isfile dbs/route.db] } {
+            # Old DB -- Convert to 2.5
+            util::update_full_db -design_db dbs/route.db
+        } else {
+	    read_db -file dbs/route.db
+        }
+    }
+}
+
+set num_errors [nrf_utils::check_flow_variables $MGC_flowStage]
+if { $num_errors > 0 } {
+    fk_msg -type error "Please fix all errors to continue execution"
+    return -code error
+}
+util::save_vars
+
+lpp::create_cell_edge_constraints
+
+## Fix Antenna
+set MGC_fix_antenna true             ; # Mandatory to review : true|false
+
+if { [file exists nrf_customization.tcl] } {
+    source nrf_customization.tcl
+}
+
+if {$MGC_fix_antenna eq true} {
+    check_antenna -cpus $MGC_cpus
+    fix_antenna -method jumper -cpus $MGC_cpus
+
+    if {$MGC_fix_antenna_use_diodes eq true} {
+	if {$MGC_fix_antenna_diodes != ""} {
+	    config_antenna -diodes $MGC_fix_antenna_diodes
+	}
+	fix_antenna -method diode -finish all
+    }
+}
+
+## Check if design is DRC clean before starting chip finishing
+set MGC_num_drc_errors_threshold 100    ; # If number of DRC errors exceeds this threshold the chip finishing steps will not be performed
+check_drc
+set num0 [llength [get_objects -type error -filter @category==drc -quiet true]]
+set skip_chip_finishing false
+if { $num0 > $MGC_num_drc_errors_threshold } {
+    fk_msg -type info "Number of DRC (including antenna) errors is too high ($num0 > $MGC_num_drc_errors_threshold). Chip finishing steps will be skipped \n"
+    set skip_chip_finishing true
+}
+
+## Place Filler
+set MGC_insert_filler_cells true     ; # true|false
+
+if { $skip_chip_finishing == false && $MGC_insert_filler_cells eq true} {
+    # only needed for advanced nodes 
+    #config_place_detail -name honor_lib_cell_edge_spacing -value true
+    set_property -objects [get_lib_cells -filter @is_filler] -name is_dont_use -value true
+    if {[llength $MGC_filler_lib_cells] == 0} {
+        set lc_list [get_lib_cells -filter @is_filler]
+        if {[llength $lc_list] == 0} {
+	    fk_msg -type error "Could not find any lib cells marked as filler cells.  No fillers inserted.\n"
+        } else {
+            set_property -objects $lc_list -name is_dont_use -value false
+	    fk_msg -type info "Placing filler cells using all lib cells marked as fillers: $lc_list\n"
+	    place_filler_cells -cpus $MGC_cpus -lib_cells $lc_list -respect_blockages $MGC_filler_respect_blockages
+        }
+    } elseif {[llength $MGC_filler_lib_cells] == 1} {
+        set lc_list [get_lib_cells -filter @is_filler -pattern $MGC_filler_lib_cells]
+        if {[llength $lc_list] == 0} {
+	    fk_msg -type error "Could not find any filler lib cells matching pattern $MGC_filler_lib_cells.  No fillers inserted.\n"
+        } else {
+	    set_property -objects $lc_list -name is_dont_use -value false
+	    fk_msg -type info "Placing filler cells using lib cells: $lc_list\n"
+	    place_filler_cells -cpus $MGC_cpus -lib_cells $lc_list -respect_blockages $MGC_filler_respect_blockages
+        }
+    } else {
+        set lc_string [join $MGC_filler_lib_cells]
+        set tempvar ""
+        if {[string is integer -strict [lindex $lc_string 1]]} {
+            for {set x 0} {$x < [llength $lc_string]} {incr x 2} {
+              set fcpattern [lindex $lc_string $x]
+              set fcpercent [lindex $lc_string $x+1]
+              lappend tempvar "$fcpattern $fcpercent"
+            }
+            set MGC_filler_lib_cells $tempvar
+	    # Place filler cells by using the percentage-based algorithm
+	    set fill_groups {}
+	    foreach filler_group $MGC_filler_lib_cells {
+	        set filler_libcells [lindex $filler_group 0]
+	        set filler_percentage [lindex $filler_group 1]
+	        set filler_groupname [regsub -all {[*?]} $filler_libcells ""]
+	        set_property -objects [get_lib_cells -filter is_filler -pattern $filler_libcells] -name is_dont_use -value false
+	        create_filler_set -name FS_$filler_groupname -lib_cells [get_lib_cells -filter is_filler -pattern $filler_libcells]
+	        lappend fill_groups FS_$filler_groupname $filler_percentage
+	    }
+            fk_msg -type info "Placing filler cells using filler sets."
+            report_filler_sets
+            puts "Filler set percentages:"
+            for {set x 0} {$x < [llength $fill_groups]} {incr x 2} {
+                puts "\t[lindex $fill_groups $x] = [lindex $fill_groups $x+1]%"
+            }
+            puts ""
+	    place_filler_cells -filler_set_prefix true -filler_set_percentages $fill_groups -cpus $MGC_cpus -respect_blockages $MGC_filler_respect_blockages
+        } else {
+            set lc_list [get_lib_cells -filter @is_filler -pattern $MGC_filler_lib_cells]
+            if {[llength $lc_list] == 0} {
+                fk_msg -type error "Could not find any filler lib cells matching pattern $MGC_filler_lib_cells.  No fillers inserted.\n"
+            } else {
+                set_property -objects $lc_list -name is_dont_use -value false
+                fk_msg -type info "Placing filler cells using lib cells: $lc_list\n"
+                place_filler_cells -cpus $MGC_cpus -lib_cells $lc_list -respect_blockages $MGC_filler_respect_blockages
+            }
+        }
+    }
+    
+    ## Check for unfilled gaps.  
+    ## This has a dependency on how fill was inserted under blockages.
+    fk_msg -type info "Checking for unfilled gaps after filler cell insertion"
+    if { $MGC_filler_respect_blockages == "hard" } {
+            check_unfilled_gaps -include_gaps_under_blockage false
+       } elseif { $MGC_filler_respect_blockages == "all" } {
+            check_unfilled_gaps -include_gaps_under_blockage false
+       } elseif { $MGC_filler_respect_blockages == "none" } {
+            check_unfilled_gaps -include_gaps_under_blockage true
+       }
+         
+    ## Check for any new DRC issues and fix them
+    check_drc
+    set num1 [llength [get_objects -type error -filter @category==drc]]
+    if { $num1 } {
+	if { $num1 > $num0 } {
+	    fk_msg -type info "Number of DRC errors increased after filler cell insertion ($num1 > $num0). Running DRC clean-up \n"
+	} else {
+	    fk_msg -type info "Running DRC clean-up for remaining $num1 errors.\n"
+	}
+	clean_drc
+	run_route_timing -mode repair -cpus $MGC_cpus -user_params "-drc_effort high -drc_accept number -dp_local_effort high"
+	check_drc
+	set num2 [llength [get_objects -type error -filter @category==drc]]
+	if { $num2 } {
+	    fk_msg -type info "$num2 DRC errors remain.\n"
+	}
+    }
+}
+## Insert Metal Fill
+if { $skip_chip_finishing == false && $MGC_skip_metal_fill == false} {
+     fk_msg -type info "Inserting metal fill"
+     insert_metal_fill
+}
+
+## Write out data
+set design [current_design]
+set dataDir output
+
+if { [info exists MGC_tanner_flow] && $MGC_tanner_flow eq "true"} {
+    # Write output data to EXPORT directory
+    write_verilog -file results/[current_design].v -bus_aware true
+    write_def -skip regions -all_vias -db_units 1000 -file results/routed.def -prefix_special_characters false
+    set corners [get_corners -filter enable]
+    set modes [get_modes -filter enable]
+    foreach_in_collection el $corners {
+	foreach el1 $modes {
+	    write_sdf -corner $el -mode $el1 -file ./results/SDF_[current_design]_${el}_${el1}.sdf -skip_backslash true
+	}
+    }
+    # Exporting SPEF
+    foreach el $corners {
+	write_spef -corner $el  -file ./results/SPEF_[current_design]_${el}.spef -coupling
+    }
+} else {
+    write_verilog -file $dataDir/${design}.v.gz
+    write_def -file $dataDir/${design}.def.gz
+    write_lef -file $dataDir/${design}.lef.gz -lib_cells [get_lib_cells -of_objects [get_top_partition]]
+}
+
+# Export GDS
+#we might need resolution 5.0:
+#config_write_stream -resolution 5.0
+if { $MGC_gds_layer_map_file != "" } {
+    source $MGC_gds_layer_map_file
+    write_stream -format gds -file $dataDir/${design}.gds
+} elseif { $MGC_gds_layer_map_file == "" } {
+    fk_msg -type warning "No GDS layer-map file specified in flow variable MGC_gds_layer_map_file.  GDS will not be written"
+} 
+
+# Save db
+if { [file exists dbs/libs.db] } {
+    ## split_db is true
+    write_db -data design -file dbs/export.db
+} else {
+    write_db -data all -file dbs/export.db
+}
+nrf_utils::write_reports $MGC_flowStage reports 100
+
+# Propagate power and grounds and output power netlist
+
+if { [info exists MGC_no_exit] && $MGC_no_exit eq "true" } {
+    fk_msg -type info "Because Nitro is not being exited, supply nets are not propagated and power netlist is not output by default.\n"
+} else {
+    propagate_power_and_ground_nets
+    write_verilog -file $dataDir/${design}.power.v.gz -power true -well_connections true
+#    exit
+}
+

abdelazeem201_ASIC-Design-Roadmap/mentor_scripts/createpathgroup.tcl

@@ -0,0 +1,9 @@
+set unq_input_list [all_inputs]
+foreach_in_collection unq_clock_element [all_clocks] {
+     set unq_clock_name [get_port  $unq_clock_element]
+     set unq_input_list [remove_from_collection $unq_input_list $unq_clock_name]
+}
+group_path -name f2f -from [all_registers]  -to [all_registers] -critical_range 0.7
+group_path -name i2f -from $unq_input_list -to [all_registers] -critical_range 0.7
+group_path -name f2o -from [all_registers]  -to [all_outputs]   -critical_range 0.7
+group_path -name i2o -from $unq_input_list -to [all_outputs]   -critical_range 0.7