Commit ·
123e810
1
Parent(s): 9d34554
Add 511-case data manifest (testbench_verilator, issues, snapshots) (#2)
Browse files- Add 511-case data manifest (testbench_verilator, issues, snapshots) (248e679d788789360adf7fdbaa7078e9742c333b)
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This view is limited to 50 files because it contains too many changes. See raw diff
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.gitattributes
CHANGED
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@@ -58,3 +58,741 @@ saved_model/**/* filter=lfs diff=lfs merge=lfs -text
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# Video files - compressed
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| 58 |
# Video files - compressed
|
| 59 |
*.mp4 filter=lfs diff=lfs merge=lfs -text
|
| 60 |
*.webm filter=lfs diff=lfs merge=lfs -text
|
| 61 |
+
snapshots/MiSTer-devel_Arcade-Robotron_MiSTer_pr25/releases/Arcade-Robotron_20210103.rbf filter=lfs diff=lfs merge=lfs -text
|
| 62 |
+
snapshots/MiSTer-devel_Arcade-Robotron_MiSTer_pr25/releases/Arcade-Robotron_20200220.rbf filter=lfs diff=lfs merge=lfs -text
|
| 63 |
+
snapshots/MiSTer-devel_Arcade-Robotron_MiSTer_pr25/releases/Arcade-Robotron_20181215.rbf filter=lfs diff=lfs merge=lfs -text
|
| 64 |
+
snapshots/MiSTer-devel_Arcade-Robotron_MiSTer_pr25/releases/Arcade-Robotron_20191218.rbf filter=lfs diff=lfs merge=lfs -text
|
| 65 |
+
snapshots/MiSTer-devel_Arcade-Robotron_MiSTer_pr25/releases/Arcade-Robotron_20200304.rbf filter=lfs diff=lfs merge=lfs -text
|
| 66 |
+
snapshots/MiSTer-devel_Arcade-Robotron_MiSTer_pr25/releases/Arcade-Robotron_20210420.rbf filter=lfs diff=lfs merge=lfs -text
|
| 67 |
+
snapshots/MiSTer-devel_Arcade-Robotron_MiSTer_pr25/releases/Arcade-Robotron_20210315.rbf filter=lfs diff=lfs merge=lfs -text
|
| 68 |
+
snapshots/MiSTer-devel_Arcade-Robotron_MiSTer_pr25/releases/Arcade-Robotron_20200316.rbf filter=lfs diff=lfs merge=lfs -text
|
| 69 |
+
snapshots/MiSTer-devel_Arcade-Robotron_MiSTer_pr25/releases/Arcade-Robotron_20200219.rbf filter=lfs diff=lfs merge=lfs -text
|
| 70 |
+
snapshots/MiSTer-devel_Arcade-Robotron_MiSTer_pr25/releases/Arcade-Robotron_20210415.rbf filter=lfs diff=lfs merge=lfs -text
|
| 71 |
+
snapshots/lowRISC_ibex_pr2261/vendor/riscv-tests/debug/bin/RTOSDemo64.axf filter=lfs diff=lfs merge=lfs -text
|
| 72 |
+
snapshots/lowRISC_ibex_pr2261/vendor/riscv-tests/debug/bin/RTOSDemo32.axf filter=lfs diff=lfs merge=lfs -text
|
| 73 |
+
snapshots/lowRISC_ibex_pr2261/vendor/riscv-isa-sim/tests/mseccfg/gengen_tool/gengen filter=lfs diff=lfs merge=lfs -text
|
| 74 |
+
snapshots/chipsalliance_adams-bridge_pr66/docs/Side-Channel[[:space:]]Countermeasures[[:space:]]for[[:space:]]Adam’s[[:space:]]Bridge[[:space:]]Accelerator.docx filter=lfs diff=lfs merge=lfs -text
|
| 75 |
+
snapshots/chipsalliance_adams-bridge_pr66/docs/Adams[[:space:]]bridge_HardwareSpecs.docx filter=lfs diff=lfs merge=lfs -text
|
| 76 |
+
snapshots/FPGA-MAFIA_fpga_mafia_pr451/FPGA/SDRAM_RTL_Test/DE10_LITE_SDRAM_RTL_Test.sof filter=lfs diff=lfs merge=lfs -text
|
| 77 |
+
snapshots/FPGA-MAFIA_fpga_mafia_pr451/FPGA/SDRAM_RTL_Test/DE10_LITE_SDRAM_RTL_Test.pof filter=lfs diff=lfs merge=lfs -text
|
| 78 |
+
snapshots/FPGA-MAFIA_fpga_mafia_pr451/FPGA/SDRAM_RTL_Test/demo_batch/DE10_LITE_SDRAM_RTL_Test.sof filter=lfs diff=lfs merge=lfs -text
|
| 79 |
+
snapshots/jotego_jtcores_pr1242/doc/mame.xml filter=lfs diff=lfs merge=lfs -text
|
| 80 |
+
snapshots/jotego_jtcores_pr1242/cores/pinpon/doc/Konami's[[:space:]]Ping[[:space:]]Pong[[:space:]]Report.pdf filter=lfs diff=lfs merge=lfs -text
|
| 81 |
+
snapshots/jotego_jtcores_pr1242/cores/contra/doc/007121.pdf filter=lfs diff=lfs merge=lfs -text
|
| 82 |
+
snapshots/jotego_jtcores_pr1242/cores/s16b/doc/315-5195_schematics.pdf filter=lfs diff=lfs merge=lfs -text
|
| 83 |
+
snapshots/jotego_jtcores_pr1242/cores/flstory/doc/msm5232.ods filter=lfs diff=lfs merge=lfs -text
|
| 84 |
+
snapshots/jotego_jtcores_pr1242/cores/aliens/doc/051960_schematics.pdf filter=lfs diff=lfs merge=lfs -text
|
| 85 |
+
snapshots/jotego_jtcores_pr1242/cores/aliens/doc/k052109_schematics.pdf filter=lfs diff=lfs merge=lfs -text
|
| 86 |
+
snapshots/jotego_jtcores_pr1242/cores/aliens/doc/051937_schematics.pdf filter=lfs diff=lfs merge=lfs -text
|
| 87 |
+
snapshots/jotego_jtcores_pr1242/cores/aliens/doc/k051962_schematics.pdf filter=lfs diff=lfs merge=lfs -text
|
| 88 |
+
snapshots/jotego_jtcores_pr1242/cores/aliens/doc/052591/k052591_schematics.pdf filter=lfs diff=lfs merge=lfs -text
|
| 89 |
+
snapshots/jotego_jtcores_pr1242/cores/s18/custom/shdancer/epr-12773b.a5 filter=lfs diff=lfs merge=lfs -text
|
| 90 |
+
snapshots/jotego_jtcores_pr1242/cores/s18/custom/shdancer/epr-12723.a8 filter=lfs diff=lfs merge=lfs -text
|
| 91 |
+
snapshots/jotego_jtcores_pr1242/cores/s18/custom/shdancer/mpr-12715.b4 filter=lfs diff=lfs merge=lfs -text
|
| 92 |
+
snapshots/jotego_jtcores_pr1242/cores/s18/custom/shdancer/mpr-12725.a10 filter=lfs diff=lfs merge=lfs -text
|
| 93 |
+
snapshots/jotego_jtcores_pr1242/cores/s18/custom/shdancer/epr-12987.a4 filter=lfs diff=lfs merge=lfs -text
|
| 94 |
+
snapshots/jotego_jtcores_pr1242/cores/s18/custom/shdancer/mpr-12717.b9 filter=lfs diff=lfs merge=lfs -text
|
| 95 |
+
snapshots/jotego_jtcores_pr1242/cores/s18/custom/shdancer/epr-12774b.a6 filter=lfs diff=lfs merge=lfs -text
|
| 96 |
+
snapshots/jotego_jtcores_pr1242/cores/s18/custom/shdancer/mpr-12714.b3 filter=lfs diff=lfs merge=lfs -text
|
| 97 |
+
snapshots/jotego_jtcores_pr1242/cores/s18/custom/shdancer/mpr-12724.a9 filter=lfs diff=lfs merge=lfs -text
|
| 98 |
+
snapshots/jotego_jtcores_pr1242/cores/s18/custom/shdancer/mpr-12713.b2 filter=lfs diff=lfs merge=lfs -text
|
| 99 |
+
snapshots/jotego_jtcores_pr1242/cores/s18/custom/shdancer/mpr-12726.a11 filter=lfs diff=lfs merge=lfs -text
|
| 100 |
+
snapshots/jotego_jtcores_pr1242/cores/s18/custom/shdancer/mpr-12719.b11 filter=lfs diff=lfs merge=lfs -text
|
| 101 |
+
snapshots/jotego_jtcores_pr1242/cores/s18/custom/shdancer/epr-12716.b8 filter=lfs diff=lfs merge=lfs -text
|
| 102 |
+
snapshots/jotego_jtcores_pr1242/cores/s18/custom/shdancer/mpr-12712.b1 filter=lfs diff=lfs merge=lfs -text
|
| 103 |
+
snapshots/jotego_jtcores_pr1242/cores/s18/custom/shdancer/mpr-12718.b10 filter=lfs diff=lfs merge=lfs -text
|
| 104 |
+
snapshots/jotego_jtcores_pr1242/cores/s18/custom/shdancer/shdancer1/epr-12771b.a5 filter=lfs diff=lfs merge=lfs -text
|
| 105 |
+
snapshots/jotego_jtcores_pr1242/cores/s18/custom/shdancer/shdancer1/epr-12720.a4 filter=lfs diff=lfs merge=lfs -text
|
| 106 |
+
snapshots/jotego_jtcores_pr1242/cores/s18/custom/shdancer/shdancer1/epr-12772b.a6 filter=lfs diff=lfs merge=lfs -text
|
| 107 |
+
snapshots/jotego_jtcores_pr1242/cores/s18/custom/shdancer/shdancbl/ic3 filter=lfs diff=lfs merge=lfs -text
|
| 108 |
+
snapshots/jotego_jtcores_pr1242/cores/s18/custom/shdancer/shdancbl/ic16 filter=lfs diff=lfs merge=lfs -text
|
| 109 |
+
snapshots/jotego_jtcores_pr1242/cores/s18/custom/shdancer/shdancbl/ic2 filter=lfs diff=lfs merge=lfs -text
|
| 110 |
+
snapshots/jotego_jtcores_pr1242/cores/s18/custom/shdancer/shdancbl/ic17 filter=lfs diff=lfs merge=lfs -text
|
| 111 |
+
snapshots/jotego_jtcores_pr1242/cores/s18/custom/shdancer/shdancbl/ic18 filter=lfs diff=lfs merge=lfs -text
|
| 112 |
+
snapshots/jotego_jtcores_pr1242/cores/s18/custom/shdancer/shdancbl/ic4 filter=lfs diff=lfs merge=lfs -text
|
| 113 |
+
snapshots/jotego_jtcores_pr1242/cores/s18/custom/shdancer/shdancerj/epr-12721b.a5 filter=lfs diff=lfs merge=lfs -text
|
| 114 |
+
snapshots/jotego_jtcores_pr1242/cores/s18/custom/shdancer/shdancerj/epr-12722b.a6 filter=lfs diff=lfs merge=lfs -text
|
| 115 |
+
snapshots/jotego_jtcores_pr1242/cores/riders/ver/glfgreat/z-tilemap filter=lfs diff=lfs merge=lfs -text
|
| 116 |
+
snapshots/jotego_jtcores_pr1242/cores/riders/ver/glfgreat/z-tiles filter=lfs diff=lfs merge=lfs -text
|
| 117 |
+
snapshots/jotego_jtcores_pr1242/cores/simson/doc/053251.pdf filter=lfs diff=lfs merge=lfs -text
|
| 118 |
+
snapshots/jotego_jtcores_pr1242/cores/simson/doc/k053260_schematics.PDF filter=lfs diff=lfs merge=lfs -text
|
| 119 |
+
snapshots/jotego_jtcores_pr1242/modules/jtframe/doc/T48[[:space:]]Integration[[:space:]]Manual.pdf filter=lfs diff=lfs merge=lfs -text
|
| 120 |
+
snapshots/jotego_jtcores_pr1242/modules/jtframe/doc/93c06.pdf filter=lfs diff=lfs merge=lfs -text
|
| 121 |
+
snapshots/jotego_jtcores_pr1242/modules/jtframe/asm/z80/tiny_basic_instructions.pdf filter=lfs diff=lfs merge=lfs -text
|
| 122 |
+
snapshots/jotego_jtcores_pr1169/doc/mame.xml filter=lfs diff=lfs merge=lfs -text
|
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snapshots/Multimedia-Processing_Digital-Logic-Design_pr62/VHDL[[:space:]]Digital[[:space:]]Logic[[:space:]]Design[[:space:]]Practice/CH7/clock.snf filter=lfs diff=lfs merge=lfs -text
|
| 769 |
+
snapshots/Multimedia-Processing_Digital-Logic-Design_pr62/VHDL[[:space:]]Digital[[:space:]]Logic[[:space:]]Design[[:space:]]Practice/CH5/bin_to_bcd_8bit_1.cnf filter=lfs diff=lfs merge=lfs -text
|
| 770 |
+
snapshots/Multimedia-Processing_Digital-Logic-Design_pr62/VHDL[[:space:]]Digital[[:space:]]Logic[[:space:]]Design[[:space:]]Practice/CH5/demux_1x16_1.cnf filter=lfs diff=lfs merge=lfs -text
|
| 771 |
+
snapshots/Multimedia-Processing_Digital-Logic-Design_pr62/VHDL[[:space:]]Digital[[:space:]]Logic[[:space:]]Design[[:space:]]Practice/CH5/bin_to_bcd_8bit.snf filter=lfs diff=lfs merge=lfs -text
|
| 772 |
+
snapshots/Multimedia-Processing_Digital-Logic-Design_pr62/VHDL[[:space:]]Digital[[:space:]]Logic[[:space:]]Design[[:space:]]Practice/CH5/bin_to_bcd_8bit.cnf filter=lfs diff=lfs merge=lfs -text
|
| 773 |
+
snapshots/bespoke-silicon-group_basejump_stl_pr737/docs/BaseJump_STL_DAC_2018_Camera_Ready.pdf filter=lfs diff=lfs merge=lfs -text
|
| 774 |
+
snapshots/chipsalliance_Cores-VeeR-EL2_pr363/docs/RISC-V_VeeR_EL2_PRM.pdf filter=lfs diff=lfs merge=lfs -text
|
| 775 |
+
snapshots/bespoke-silicon-group_basejump_stl_pr737/bsg_legacy/bsg_tag/config_net/docs/20130219.pdf filter=lfs diff=lfs merge=lfs -text
|
| 776 |
+
snapshots/MiSTer-devel_ao486_MiSTer_pr185/releases/ao486_20200822.rbf filter=lfs diff=lfs merge=lfs -text
|
| 777 |
+
snapshots/MiSTer-devel_ao486_MiSTer_pr185/releases/ao486_20210103.rbf filter=lfs diff=lfs merge=lfs -text
|
| 778 |
+
snapshots/MiSTer-devel_ao486_MiSTer_pr185/releases/ao486_20190719.rbf filter=lfs diff=lfs merge=lfs -text
|
| 779 |
+
snapshots/MiSTer-devel_ao486_MiSTer_pr185/releases/ao486_20200421.rbf filter=lfs diff=lfs merge=lfs -text
|
| 780 |
+
snapshots/MiSTer-devel_ao486_MiSTer_pr185/releases/ao486_20201106.rbf filter=lfs diff=lfs merge=lfs -text
|
| 781 |
+
snapshots/MiSTer-devel_ao486_MiSTer_pr185/releases/ao486_20170818.rbf filter=lfs diff=lfs merge=lfs -text
|
| 782 |
+
snapshots/MiSTer-devel_ao486_MiSTer_pr185/releases/ao486_20230816.rbf filter=lfs diff=lfs merge=lfs -text
|
| 783 |
+
snapshots/MiSTer-devel_ao486_MiSTer_pr185/releases/ao486_20180101.rbf filter=lfs diff=lfs merge=lfs -text
|
| 784 |
+
snapshots/MiSTer-devel_ao486_MiSTer_pr185/releases/ao486_20210329.rbf filter=lfs diff=lfs merge=lfs -text
|
| 785 |
+
snapshots/MiSTer-devel_ao486_MiSTer_pr185/releases/ao486_20200814.rbf filter=lfs diff=lfs merge=lfs -text
|
| 786 |
+
snapshots/MiSTer-devel_ao486_MiSTer_pr185/releases/ao486_20201101.rbf filter=lfs diff=lfs merge=lfs -text
|
| 787 |
+
snapshots/MiSTer-devel_ao486_MiSTer_pr185/releases/ao486_20180304.rbf filter=lfs diff=lfs merge=lfs -text
|
| 788 |
+
snapshots/MiSTer-devel_ao486_MiSTer_pr185/releases/ao486_20200510.rbf filter=lfs diff=lfs merge=lfs -text
|
| 789 |
+
snapshots/MiSTer-devel_ao486_MiSTer_pr185/releases/ao486_20210117.rbf filter=lfs diff=lfs merge=lfs -text
|
| 790 |
+
snapshots/MiSTer-devel_ao486_MiSTer_pr185/releases/ao486_20220301.rbf filter=lfs diff=lfs merge=lfs -text
|
| 791 |
+
snapshots/MiSTer-devel_ao486_MiSTer_pr185/releases/ao486_20180426.rbf filter=lfs diff=lfs merge=lfs -text
|
| 792 |
+
snapshots/MiSTer-devel_ao486_MiSTer_pr185/releases/ao486_20200816.rbf filter=lfs diff=lfs merge=lfs -text
|
| 793 |
+
snapshots/MiSTer-devel_ao486_MiSTer_pr185/releases/ao486_20180407.rbf filter=lfs diff=lfs merge=lfs -text
|
| 794 |
+
snapshots/jotego_jtcores_pr1108/doc/dd2/Double[[:space:]]Dragon[[:space:]]2[[:space:]]pcb.m4a filter=lfs diff=lfs merge=lfs -text
|
| 795 |
+
snapshots/FPGA-MAFIA_fpga_mafia_pr479/FPGA/SDRAM_RTL_Test/DE10_LITE_SDRAM_RTL_Test.sof filter=lfs diff=lfs merge=lfs -text
|
| 796 |
+
snapshots/FPGA-MAFIA_fpga_mafia_pr479/FPGA/SDRAM_RTL_Test/DE10_LITE_SDRAM_RTL_Test.pof filter=lfs diff=lfs merge=lfs -text
|
| 797 |
+
snapshots/FPGA-MAFIA_fpga_mafia_pr479/FPGA/SDRAM_RTL_Test/demo_batch/DE10_LITE_SDRAM_RTL_Test.sof filter=lfs diff=lfs merge=lfs -text
|
| 798 |
+
snapshots/jotego_jtcores_pr960/cores/s16b/doc/315-5195_schematics.pdf filter=lfs diff=lfs merge=lfs -text
|
DATA_MANIFEST.md
ADDED
|
@@ -0,0 +1,13 @@
|
|
|
|
|
|
|
|
|
|
|
|
|
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|
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|
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|
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|
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|
|
|
|
|
|
|
|
| 1 |
+
# Phoenix-Bench — 511-case benchmark data
|
| 2 |
+
|
| 3 |
+
Each case provides four aligned artifacts under a common root:
|
| 4 |
+
testbench/<case>/ verilator differential testbench (run via run_once.sh / run_verilator.sh)
|
| 5 |
+
snapshots/<case>/ pre-PR repository snapshot (RTL sources)
|
| 6 |
+
patches/<case>.patch the fix; testbench reverse-applies for buggy, applies for fixed
|
| 7 |
+
issues/<case> issue description
|
| 8 |
+
testbench/_* shared run helpers (sourced by per-case scripts)
|
| 9 |
+
|
| 10 |
+
Counts: testbench=511 snapshots=511 patches=511 issues=511
|
| 11 |
+
|
| 12 |
+
Toolchain: set $OSS_CAD_SUITE (or have verilator/surelog on PATH). No absolute machine paths.
|
| 13 |
+
Excluded: .git, verilator obj_dir/build artifacts, surelog parse caches, broken symlinks.
|
issues/AUCOHL_Lighter_pr16
ADDED
|
@@ -0,0 +1,51 @@
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
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|
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|
|
|
|
|
|
|
|
|
|
|
| 1 |
+
Minimal fail-to-pass extraction for AUCOHL/Lighter PR 16, "bug fix in FF
|
| 2 |
+
Mapping cells".
|
| 3 |
+
|
| 4 |
+
The reduced snapshot models the sky130 `\$dffe` mapping cell. The buggy
|
| 5 |
+
mapping feeds `EN` directly into the clock-gate cell and ignores
|
| 6 |
+
`EN_POLARITY`, so an active-low enable does not capture data. The patch adds
|
| 7 |
+
the polarity-adjusted gate enable used by the real PR. The Verilator
|
| 8 |
+
testbench drives an active-low enable and checks capture/hold behavior.
|
| 9 |
+
|
| 10 |
+
## PR Content from GitHub
|
| 11 |
+
|
| 12 |
+
# Pull Request Summary
|
| 13 |
+
|
| 14 |
+
**PR Title:** bug fix in FF Mapping cells
|
| 15 |
+
|
| 16 |
+
**PR Number:** #16
|
| 17 |
+
|
| 18 |
+
**Status:** Merged (Sep 28, 2023)
|
| 19 |
+
|
| 20 |
+
---
|
| 21 |
+
|
| 22 |
+
## PR Description
|
| 23 |
+
|
| 24 |
+
**Signed by:** Youssef Kandil
|
| 25 |
+
|
| 26 |
+
**Contributor:** @dineshannayya
|
| 27 |
+
|
| 28 |
+
**Context:**
|
| 29 |
+
The clock gating functionality of $SDFFE cells was causing validation failures. The issue stemmed from forced positive signaling of clock and enable signals.
|
| 30 |
+
|
| 31 |
+
**Changes:**
|
| 32 |
+
The fix implements polarity checking for both "clock" and "enable" signals, adjusting their signs accordingly. This resolves issue #2.
|
| 33 |
+
|
| 34 |
+
**Mentions:** @dineshannayya, @shalan
|
| 35 |
+
|
| 36 |
+
---
|
| 37 |
+
|
| 38 |
+
## Linked Issue
|
| 39 |
+
|
| 40 |
+
**Title:** SDFFE mapping crashes validation
|
| 41 |
+
|
| 42 |
+
This PR successfully merged after closing the referenced issue.
|
| 43 |
+
|
| 44 |
+
---
|
| 45 |
+
|
| 46 |
+
## Participants
|
| 47 |
+
|
| 48 |
+
- @kanndil (merged the PR)
|
| 49 |
+
- @dineshannayya (contributor)
|
| 50 |
+
|
| 51 |
+
No formal reviews were recorded, and no labels, assignees, or milestone were set for this pull request.
|
issues/AsFigo_pyslint_pr138
ADDED
|
@@ -0,0 +1,33 @@
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
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|
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|
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|
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|
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|
|
|
|
|
|
| 1 |
+
# SVA: expect construct usage - compatibility issue
|
| 2 |
+
|
| 3 |
+
- Source URL: https://github.com/AsFigo/pyslint/issues/136
|
| 4 |
+
|
| 5 |
+
https://verificationacademy.com/forums/systemverilog/expect-assertion#answer-117075
|
| 6 |
+
|
| 7 |
+
```verilog
|
| 8 |
+
module test;
|
| 9 |
+
|
| 10 |
+
bit req1,req2;
|
| 11 |
+
bit clk;
|
| 12 |
+
|
| 13 |
+
always #5 clk=~clk;
|
| 14 |
+
|
| 15 |
+
|
| 16 |
+
initial begin
|
| 17 |
+
#100;
|
| 18 |
+
expect(@(posedge clk) req1 ##2 req2) else $error ("expect failure");
|
| 19 |
+
$display("DONE");
|
| 20 |
+
end
|
| 21 |
+
|
| 22 |
+
initial
|
| 23 |
+
begin
|
| 24 |
+
repeat(10)
|
| 25 |
+
begin
|
| 26 |
+
req1=$urandom;
|
| 27 |
+
req2=$urandom;
|
| 28 |
+
#12;
|
| 29 |
+
end
|
| 30 |
+
$finish;
|
| 31 |
+
end
|
| 32 |
+
endmodule
|
| 33 |
+
```
|
issues/AsFigo_pyslint_pr140
ADDED
|
@@ -0,0 +1,37 @@
|
|
|
|
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|
|
|
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|
|
|
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|
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|
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|
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|
|
|
|
|
| 1 |
+
# SV: post/pre randomize return value check - COMPAT issue
|
| 2 |
+
|
| 3 |
+
- Source URL: https://github.com/AsFigo/pyslint/issues/139
|
| 4 |
+
|
| 5 |
+
```verilog
|
| 6 |
+
class gen_c;
|
| 7 |
+
rand bit b;
|
| 8 |
+
|
| 9 |
+
function pre_randomize();
|
| 10 |
+
endfunction
|
| 11 |
+
|
| 12 |
+
function post_randomize();
|
| 13 |
+
endfunction
|
| 14 |
+
endclass : gen_c
|
| 15 |
+
```
|
| 16 |
+
|
| 17 |
+
Above code works fine in one but not in all others.
|
| 18 |
+
|
| 19 |
+
## PR Content from GitHub
|
| 20 |
+
|
| 21 |
+
# Pull Request #140 Summary
|
| 22 |
+
|
| 23 |
+
**PR Title:** Added rule to address issue 139
|
| 24 |
+
|
| 25 |
+
**PR Description Body:**
|
| 26 |
+
The page does not display a full description body beyond the title. The only substantive comment is: "Fixes #139"
|
| 27 |
+
|
| 28 |
+
**PR Comments:**
|
| 29 |
+
- **Author: svenka3** - "Fixes #139"
|
| 30 |
+
|
| 31 |
+
**Linked Issue #139:**
|
| 32 |
+
**Title:** "SV: post/pre randomize return value check - COMPAT issue"
|
| 33 |
+
|
| 34 |
+
**Issue Body:**
|
| 35 |
+
Not provided in the extracted content.
|
| 36 |
+
|
| 37 |
+
**Status:** This PR was merged by svenka3 on November 29, 2023, into the main branch from the i139 branch.
|
issues/AsFigo_pyslint_pr149
ADDED
|
@@ -0,0 +1,56 @@
|
|
|
|
|
|
|
|
|
|
|
|
|
|
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|
| 1 |
+
# DPI - checks needed inside interface context
|
| 2 |
+
|
| 3 |
+
- Source URL: https://github.com/AsFigo/pyslint/issues/147
|
| 4 |
+
|
| 5 |
+
DPI checks to be added for interface context.
|
| 6 |
+
|
| 7 |
+
```verilog
|
| 8 |
+
interface af_sv_if;
|
| 9 |
+
import "DPI" function int c_sum();
|
| 10 |
+
endinterface : af_sv_if
|
| 11 |
+
```
|
| 12 |
+
|
| 13 |
+
## PR Content from GitHub
|
| 14 |
+
|
| 15 |
+
# Pull Request Summary
|
| 16 |
+
|
| 17 |
+
**PR Title:** DPI enhancements
|
| 18 |
+
|
| 19 |
+
**PR Number:** #149
|
| 20 |
+
|
| 21 |
+
**Status:** Merged
|
| 22 |
+
|
| 23 |
+
**Author:** svenka3
|
| 24 |
+
|
| 25 |
+
**Merge Date:** December 1, 2023
|
| 26 |
+
|
| 27 |
+
---
|
| 28 |
+
|
| 29 |
+
## PR Description
|
| 30 |
+
|
| 31 |
+
The pull request description is minimal. The author only states: "Fixes #147 and #148"
|
| 32 |
+
|
| 33 |
+
---
|
| 34 |
+
|
| 35 |
+
## Commits
|
| 36 |
+
|
| 37 |
+
Two commits were included:
|
| 38 |
+
1. "Fixes Issue #147" (commit f340d60)
|
| 39 |
+
2. "Support for DPI inside PKG is added" (commit e15120a)
|
| 40 |
+
|
| 41 |
+
---
|
| 42 |
+
|
| 43 |
+
## Comments
|
| 44 |
+
|
| 45 |
+
**svenka3** commented on December 1, 2023:
|
| 46 |
+
"Fixes #147 and #148"
|
| 47 |
+
|
| 48 |
+
---
|
| 49 |
+
|
| 50 |
+
## Linked Issues
|
| 51 |
+
|
| 52 |
+
This PR references two issues:
|
| 53 |
+
- **Issue #147:** "DPI - checks needed inside interface context"
|
| 54 |
+
- **Issue #148:** "DPI - checks need to be performed for package scoped DPI methods"
|
| 55 |
+
|
| 56 |
+
The pull request successfully closed Issue #147. Issue #148 was also referenced and addressed through the implementation of DPI (Direct Programming Interface) support within package scoping contexts.
|
issues/AsFigo_pyslint_pr164
ADDED
|
@@ -0,0 +1,26 @@
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
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|
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|
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|
|
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|
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|
|
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|
|
|
|
|
|
|
|
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|
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|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| 1 |
+
# Avoid begin..end around timing control
|
| 2 |
+
|
| 3 |
+
- Source URL: https://github.com/AsFigo/pyslint/issues/161
|
| 4 |
+
|
| 5 |
+
https://verificationacademy.com/forums/systemverilog/memory-read-showing-xxx-values-apb-verification#reply-117165
|
| 6 |
+
|
| 7 |
+
```verilog
|
| 8 |
+
task Write();
|
| 9 |
+
begin
|
| 10 |
+
@(negedge pclk) begin
|
| 11 |
+
psel = 1;
|
| 12 |
+
penb = 0;
|
| 13 |
+
for (int i = 0; i < 64; i=i+1) begin
|
| 14 |
+
@(negedge pclk) begin
|
| 15 |
+
penb = 1 ;
|
| 16 |
+
pwrite = 1;
|
| 17 |
+
paddr = i;
|
| 18 |
+
pwdata = i;
|
| 19 |
+
$display("PADDR %h, PWDATA %h ",paddr,pwdata);
|
| 20 |
+
end
|
| 21 |
+
end
|
| 22 |
+
end
|
| 23 |
+
end
|
| 24 |
+
endtask
|
| 25 |
+
|
| 26 |
+
```
|
issues/AsFigo_pyslint_pr166
ADDED
|
@@ -0,0 +1,42 @@
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| 1 |
+
# VLT: no clocking blocks in interface
|
| 2 |
+
|
| 3 |
+
- Source URL: https://github.com/AsFigo/pyslint/issues/165
|
| 4 |
+
|
| 5 |
+
Verilator does not support clocking block based driving (as of today). Add a rule to check.
|
| 6 |
+
|
| 7 |
+
## PR Content from GitHub
|
| 8 |
+
|
| 9 |
+
# PR Summary
|
| 10 |
+
|
| 11 |
+
**PR Title:** Added rule for CB check for Verilator issue 165
|
| 12 |
+
|
| 13 |
+
**PR Number:** #166
|
| 14 |
+
|
| 15 |
+
**Status:** Merged
|
| 16 |
+
|
| 17 |
+
**Author:** svenka3
|
| 18 |
+
|
| 19 |
+
**Merge Date:** December 6, 2023
|
| 20 |
+
|
| 21 |
+
---
|
| 22 |
+
|
| 23 |
+
## PR Description Body
|
| 24 |
+
|
| 25 |
+
The PR description was not fully visible in the provided content. Only a reference appears:
|
| 26 |
+
|
| 27 |
+
**Comment by svenka3:**
|
| 28 |
+
"Fixes #165"
|
| 29 |
+
|
| 30 |
+
---
|
| 31 |
+
|
| 32 |
+
## Linked Issue
|
| 33 |
+
|
| 34 |
+
**Issue #165 Title:** VLT: no clocking blocks in interface
|
| 35 |
+
|
| 36 |
+
The issue details were not included in the available content, but the PR was designed to address this specific Verilator-related constraint.
|
| 37 |
+
|
| 38 |
+
---
|
| 39 |
+
|
| 40 |
+
## Additional Context
|
| 41 |
+
|
| 42 |
+
The pull request contained 1 commit (ea905ff) that was merged into the main branch. The change implements a rule to check for clocking blocks within interfaces, addressing a Verilator linting requirement.
|
issues/AsFigo_pyslint_pr167
ADDED
|
@@ -0,0 +1,58 @@
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| 1 |
+
# Avoid begin..end around task/function
|
| 2 |
+
|
| 3 |
+
- Source URL: https://github.com/AsFigo/pyslint/issues/160
|
| 4 |
+
|
| 5 |
+
```verilog
|
| 6 |
+
|
| 7 |
+
task Write();
|
| 8 |
+
begin
|
| 9 |
+
|
| 10 |
+
$display("PADDR %h, PWDATA %h ",paddr,pwdata);
|
| 11 |
+
|
| 12 |
+
end
|
| 13 |
+
|
| 14 |
+
endtask
|
| 15 |
+
```
|
| 16 |
+
|
| 17 |
+
## PR Content from GitHub
|
| 18 |
+
|
| 19 |
+
# GitHub Pull Request Summary
|
| 20 |
+
|
| 21 |
+
**PR Title:** Support for issue 160 added
|
| 22 |
+
|
| 23 |
+
**PR Number:** #167
|
| 24 |
+
|
| 25 |
+
**Author:** svenka3
|
| 26 |
+
|
| 27 |
+
**Status:** Merged (Dec 6, 2023)
|
| 28 |
+
|
| 29 |
+
---
|
| 30 |
+
|
| 31 |
+
## PR Description Body
|
| 32 |
+
|
| 33 |
+
The PR description body is not fully visible in the provided content. Only a comment referencing the issue is shown.
|
| 34 |
+
|
| 35 |
+
---
|
| 36 |
+
|
| 37 |
+
## PR Comments
|
| 38 |
+
|
| 39 |
+
**@svenka3** (Dec 6, 2023):
|
| 40 |
+
"Fixes #160"
|
| 41 |
+
|
| 42 |
+
---
|
| 43 |
+
|
| 44 |
+
## Linked Issue
|
| 45 |
+
|
| 46 |
+
**Issue #160 Title:** "Avoid begin..end around task/function"
|
| 47 |
+
|
| 48 |
+
**Issue Body:** Not provided in the source material.
|
| 49 |
+
|
| 50 |
+
---
|
| 51 |
+
|
| 52 |
+
## Additional Details
|
| 53 |
+
|
| 54 |
+
- **Commits:** 1 commit (18608ad)
|
| 55 |
+
- **Merged into:** main branch
|
| 56 |
+
- **Source branch:** i160
|
| 57 |
+
- **Reviews:** None
|
| 58 |
+
- **Assignees:** None
|
issues/AsFigo_pyslint_pr169
ADDED
|
@@ -0,0 +1,24 @@
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| 1 |
+
# COMPAT rule - function with ref arg shall be automatic
|
| 2 |
+
|
| 3 |
+
- Source URL: https://github.com/AsFigo/pyslint/issues/159
|
| 4 |
+
|
| 5 |
+
Add a new rule to check that functions with ref arguments are declared automatic.
|
| 6 |
+
|
| 7 |
+
```verilog
|
| 8 |
+
module x;
|
| 9 |
+
integer x1;
|
| 10 |
+
function func (ref integer a[]);
|
| 11 |
+
$display ("%p", a);
|
| 12 |
+
endfunction
|
| 13 |
+
|
| 14 |
+
initial begin
|
| 15 |
+
integer a [];
|
| 16 |
+
a = {1,2,3,4,5};
|
| 17 |
+
x1=func(a);
|
| 18 |
+
end
|
| 19 |
+
endmodule
|
| 20 |
+
```
|
| 21 |
+
|
| 22 |
+
```log
|
| 23 |
+
reference argument is illegal inside static task-function declaration.
|
| 24 |
+
```
|
issues/AsFigo_pyslint_pr175
ADDED
|
@@ -0,0 +1,57 @@
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| 1 |
+
# COMPAT SVA missing ;
|
| 2 |
+
|
| 3 |
+
- Source URL: https://github.com/AsFigo/pyslint/issues/174
|
| 4 |
+
|
| 5 |
+
```verilog
|
| 6 |
+
module m;
|
| 7 |
+
bit clk, a, b;
|
| 8 |
+
|
| 9 |
+
property p_ex;
|
| 10 |
+
@(posedge clk) a |=> b
|
| 11 |
+
endproperty : p_ex
|
| 12 |
+
|
| 13 |
+
endmodule : m
|
| 14 |
+
```
|
| 15 |
+
|
| 16 |
+
## PR Content from GitHub
|
| 17 |
+
|
| 18 |
+
# GitHub Pull Request Summary
|
| 19 |
+
|
| 20 |
+
**PR Title:** Added rule 174 - COMPAT
|
| 21 |
+
|
| 22 |
+
**PR Number:** #175
|
| 23 |
+
|
| 24 |
+
**Status:** Merged
|
| 25 |
+
|
| 26 |
+
**Author:** svenka3
|
| 27 |
+
|
| 28 |
+
**Merge Date:** December 8, 2023
|
| 29 |
+
|
| 30 |
+
---
|
| 31 |
+
|
| 32 |
+
## PR Description
|
| 33 |
+
The PR description body is not explicitly shown in the provided content beyond the title.
|
| 34 |
+
|
| 35 |
+
## Comments
|
| 36 |
+
|
| 37 |
+
**svenka3** commented:
|
| 38 |
+
> "Fixes #174"
|
| 39 |
+
|
| 40 |
+
This brief comment references the linked issue.
|
| 41 |
+
|
| 42 |
+
---
|
| 43 |
+
|
| 44 |
+
## Linked Issue
|
| 45 |
+
|
| 46 |
+
**Issue #174 Title:** "COMPAT SVA missing ;"
|
| 47 |
+
|
| 48 |
+
The issue title indicates this PR addresses a missing semicolon issue related to COMPAT SVA functionality.
|
| 49 |
+
|
| 50 |
+
---
|
| 51 |
+
|
| 52 |
+
## Additional Details
|
| 53 |
+
|
| 54 |
+
- **Commits:** 1 commit merged (09108a8)
|
| 55 |
+
- **Branch:** Merged from `i174` into `main`
|
| 56 |
+
- **Reviewers:** None listed
|
| 57 |
+
- **Assignees:** None listed
|
issues/AsFigo_pyslint_pr180
ADDED
|
@@ -0,0 +1,59 @@
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| 1 |
+
# COMPAT - class parameter default value missing check
|
| 2 |
+
|
| 3 |
+
- Source URL: https://github.com/AsFigo/pyslint/issues/178
|
| 4 |
+
|
| 5 |
+
```verilog
|
| 6 |
+
|
| 7 |
+
class abstract_ifc #(int cwidth=1, int awidth=2, int dwidth);
|
| 8 |
+
|
| 9 |
+
endclass
|
| 10 |
+
|
| 11 |
+
```
|
| 12 |
+
|
| 13 |
+
LOG
|
| 14 |
+
```log
|
| 15 |
+
Omitting the assignment to constant_param_expression in a param_assignment in a parameter_port_list currently is not supported.
|
| 16 |
+
```
|
| 17 |
+
|
| 18 |
+
## PR Content from GitHub
|
| 19 |
+
|
| 20 |
+
# GitHub Pull Request Summary
|
| 21 |
+
|
| 22 |
+
**PR Title:** Added new rule for #178
|
| 23 |
+
|
| 24 |
+
**PR Number:** #180
|
| 25 |
+
|
| 26 |
+
**Status:** Merged
|
| 27 |
+
|
| 28 |
+
**Author:** svenka3
|
| 29 |
+
|
| 30 |
+
**Merge Date:** December 29, 2023
|
| 31 |
+
|
| 32 |
+
---
|
| 33 |
+
|
| 34 |
+
## PR Description
|
| 35 |
+
The pull request body is not fully visible in the provided content, but the commit message indicates: "Added new rule for #178"
|
| 36 |
+
|
| 37 |
+
---
|
| 38 |
+
|
| 39 |
+
## Comments
|
| 40 |
+
|
| 41 |
+
**svenka3** (Dec 29, 2023):
|
| 42 |
+
"Fixes #178"
|
| 43 |
+
|
| 44 |
+
---
|
| 45 |
+
|
| 46 |
+
## Linked Issue
|
| 47 |
+
|
| 48 |
+
**Issue #178 Title:** COMPAT - class parameter default value missing check
|
| 49 |
+
|
| 50 |
+
**Issue Description:** Not provided in the extracted content.
|
| 51 |
+
|
| 52 |
+
---
|
| 53 |
+
|
| 54 |
+
## Additional Context
|
| 55 |
+
|
| 56 |
+
- **Commits:** 1 commit included
|
| 57 |
+
- **Commit Hash:** ee7ed6e
|
| 58 |
+
- **Branch:** Merged from `i178` into `main`
|
| 59 |
+
- **Merge Commit:** c55f299
|
issues/AsFigo_pyslint_pr185
ADDED
|
@@ -0,0 +1,31 @@
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| 1 |
+
# CNST - add new rule
|
| 2 |
+
|
| 3 |
+
- Source URL: https://github.com/AsFigo/pyslint/issues/184
|
| 4 |
+
|
| 5 |
+
```verilog
|
| 6 |
+
class bli_c;
|
| 7 |
+
bit foo_sel;
|
| 8 |
+
|
| 9 |
+
rand int foo;
|
| 10 |
+
|
| 11 |
+
constraint cst_1 {
|
| 12 |
+
foo == (foo_sel) ? 5 :6;
|
| 13 |
+
}
|
| 14 |
+
|
| 15 |
+
function void post_randomize();
|
| 16 |
+
$display ("%p", this);
|
| 17 |
+
endfunction
|
| 18 |
+
endclass
|
| 19 |
+
|
| 20 |
+
module m;
|
| 21 |
+
bli_c u_bli_c_0;
|
| 22 |
+
|
| 23 |
+
initial begin
|
| 24 |
+
u_bli_c_0 = new();
|
| 25 |
+
repeat (5) u_bli_c_0.randomize();
|
| 26 |
+
#10;
|
| 27 |
+
$finish (2);
|
| 28 |
+
end
|
| 29 |
+
endmodule
|
| 30 |
+
```
|
| 31 |
+
https://www.linkedin.com/posts/avidan-efody_appleabrdv-servingthenextbug-systemverilog-activity-7152673318020562944-tI2M?utm_source=share&utm_medium=member_desktop
|
issues/AsFigo_pyslint_pr56
ADDED
|
@@ -0,0 +1,36 @@
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| 1 |
+
# REUSE_NO_TDEF_IN_MOD - check for typedef inside module
|
| 2 |
+
|
| 3 |
+
- Source URL: https://github.com/AsFigo/pyslint/issues/55
|
| 4 |
+
|
| 5 |
+
**Is your feature request related to a new rule? Please describe.**
|
| 6 |
+
Any typedef inside module scope would lead to reuse issues. Example:
|
| 7 |
+
|
| 8 |
+
https://www.linkedin.com/posts/petermonsson_verification-systemverilog-verilog-activity-7114149452868632576-EbPn
|
| 9 |
+
|
| 10 |
+
**Describe the solution you'd like**
|
| 11 |
+
Add a check to detect such declarations and suggest using package instead.
|
| 12 |
+
|
| 13 |
+
## PR Content from GitHub
|
| 14 |
+
|
| 15 |
+
# Pull Request #56 Summary
|
| 16 |
+
|
| 17 |
+
**PR Title:** "Added new rule to address issue #55 and a test"
|
| 18 |
+
|
| 19 |
+
**PR Description Body:** Not provided in the page content.
|
| 20 |
+
|
| 21 |
+
**PR Comments:**
|
| 22 |
+
|
| 23 |
+
- **@svenka3** (Collaborator): "Fixes #55"
|
| 24 |
+
|
| 25 |
+
**Linked Issue:**
|
| 26 |
+
|
| 27 |
+
- **Issue #55 Title:** "REUSE_NO_TDEF_IN_MOD - check for typedef inside module"
|
| 28 |
+
- **Issue #55 Body:** Not provided in the page content.
|
| 29 |
+
|
| 30 |
+
**Additional Details:**
|
| 31 |
+
- Status: Merged on October 1, 2023
|
| 32 |
+
- Merged by: @svenka3
|
| 33 |
+
- Source branch: rtl_tdep_oct1
|
| 34 |
+
- Target branch: main
|
| 35 |
+
- Commits: 1 commit (1c588dd)
|
| 36 |
+
- The branch was deleted on December 2, 2023
|
issues/FPGA-MAFIA_fpga_mafia_pr428
ADDED
|
@@ -0,0 +1,29 @@
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| 1 |
+
# change csr names and design to fit the spec
|
| 2 |
+
|
| 3 |
+
- Source URL: https://github.com/FPGA-MAFIA/fpga_mafia/issues/421
|
| 4 |
+
|
| 5 |
+
make changes both to core_rrv and rv32i_ref
|
| 6 |
+
|
| 7 |
+
PR Title: add cycle and instret User mode csr's
|
| 8 |
+
PR Number: #428
|
| 9 |
+
Status: Merged
|
| 10 |
+
Author: roman012285
|
| 11 |
+
Merge Details: Merged on January 14, 2024, from branch core_rrv into main
|
| 12 |
+
|
| 13 |
+
Description:
|
| 14 |
+
No description was provided by the contributor.
|
| 15 |
+
|
| 16 |
+
Comments:
|
| 17 |
+
roman012285 (Collaborator) - January 14, 2024:
|
| 18 |
+
No substantive comment; the PR was opened without explanation.
|
| 19 |
+
|
| 20 |
+
Linked Issue:
|
| 21 |
+
Issue #421: "change csr names and design to fit the spec"
|
| 22 |
+
This pull request was flagged as potentially closing this issue.
|
| 23 |
+
|
| 24 |
+
Metadata:
|
| 25 |
+
- Commits: 2 commits
|
| 26 |
+
- Milestone: MAFIA 0.1 (later modified to include MAFIA 1.0)
|
| 27 |
+
- Participants: roman012285, amichai-bd
|
| 28 |
+
- Reviews: None documented
|
| 29 |
+
- Assignees: None
|
issues/FPGA-MAFIA_fpga_mafia_pr429
ADDED
|
@@ -0,0 +1,34 @@
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| 1 |
+
# sc_core - screen is broken, and there is no reference model in TB
|
| 2 |
+
|
| 3 |
+
- Source URL: https://github.com/FPGA-MAFIA/fpga_mafia/issues/423
|
| 4 |
+
|
| 5 |
+
2 things to fix:
|
| 6 |
+
1) add a reference model and EOT check to make sure IP is running correctly
|
| 7 |
+
2) Make sure the display works. (have a dedicated memory region for VGA space)
|
| 8 |
+
|
| 9 |
+
PR Title: integrate ref model to sc_core_tb and regress level 0
|
| 10 |
+
Status: Merged on January 14, 2024
|
| 11 |
+
|
| 12 |
+
Description:
|
| 13 |
+
Roman012285 implemented the following changes:
|
| 14 |
+
1. Added a reference model to sc_core_tb
|
| 15 |
+
2. Introduced test cases including bubblesort
|
| 16 |
+
3. Integrated rv32i_level0 into sc_core (modifying the mafia_sanity SC_CORE configuration)
|
| 17 |
+
4. Did not yet work on VGA functionality
|
| 18 |
+
|
| 19 |
+
The author noted that verification requires adding "+4" to an addition operation; "+1" causes timeouts.
|
| 20 |
+
|
| 21 |
+
Key Discussion:
|
| 22 |
+
Roman asked about releasing sc_core's data memory at line 124 in sc_core.tb.sv.
|
| 23 |
+
|
| 24 |
+
Amichai-bd responded: "The use of 'Force' is to force the priority to the assignment in the TB over the RTL... I think that in the case of the '$readmemh' its getting priority without the use of 'force'."
|
| 25 |
+
|
| 26 |
+
He explained that using "$readmemh" for both DMem and NextDMem ensures data memory initialization without explicit release statements.
|
| 27 |
+
|
| 28 |
+
Metadata:
|
| 29 |
+
- Author: roman012285
|
| 30 |
+
- Reviewer/Approver: amichai-bd
|
| 31 |
+
- Assignee: roman012285
|
| 32 |
+
- Labels: RV32I_REF, SC_CORE
|
| 33 |
+
- Milestone: MAFIA 0.1
|
| 34 |
+
- Linked Issue: #423 (sc_core screen broken, no reference model in TB)
|
issues/FPGA-MAFIA_fpga_mafia_pr449
ADDED
|
@@ -0,0 +1,58 @@
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|
| 1 |
+
# Remove the Parameter override from the build.
|
| 2 |
+
|
| 3 |
+
- Source URL: https://github.com/FPGA-MAFIA/fpga_mafia/issues/441
|
| 4 |
+
|
| 5 |
+
https://github.com/FPGA-MAFIA/fpga_mafia/blob/931deaa13c92a1fe5d29dee95ba23c76531a68f2/build.py#L241C16-L241C16
|
| 6 |
+
|
| 7 |
+
I think there is room for creating a script that can override the parameter value by name - both in source (AKA rtl) and in verif
|
| 8 |
+
|
| 9 |
+
The way it should work is as following:
|
| 10 |
+
In the cfg file add a field that is called "parameter_override"
|
| 11 |
+
``` json
|
| 12 |
+
{
|
| 13 |
+
"I_MEM_OFFSET": 0,
|
| 14 |
+
"I_MEM_LENGTH": 65536,
|
| 15 |
+
"D_MEM_OFFSET": 65536,
|
| 16 |
+
"D_MEM_LENGTH": 61440,
|
| 17 |
+
"crt0_file" : "crt0_mini_rv32e.S",
|
| 18 |
+
"rv32_gcc" : "rv32e -mabi=ilp32e",
|
| 19 |
+
"name" : "rv32e",
|
| 20 |
+
"rtl_parameter_override" : {
|
| 21 |
+
"RF_NUM_MSB" : 31,
|
| 22 |
+
"RF_NUM_LSB" : 0,
|
| 23 |
+
"OTHER_EXAMPLE" : 31
|
| 24 |
+
},
|
| 25 |
+
"verif_pkg_parameter_override" : {
|
| 26 |
+
"TIMEOUT" : 1000000,
|
| 27 |
+
"OTHER_EXAMPLE" : 65403540
|
| 28 |
+
}
|
| 29 |
+
}
|
| 30 |
+
```
|
| 31 |
+
|
| 32 |
+
Then in the "build" call a new script that you need to create that accepts the list of parameters you need to change.
|
| 33 |
+
Make sure use correct regular expression so it overrides only the "parameter <name> = value" instances
|
| 34 |
+
|
| 35 |
+
The scipt will search, find and replace the values that are mentioned in the cfg json file.
|
| 36 |
+
The scipt will also log the info by printing to the screen what he found, where, and what he has changed.
|
| 37 |
+
|
| 38 |
+
During the find replace - add a comment in the line of parameter
|
| 39 |
+
Example:
|
| 40 |
+
```systemverilog
|
| 41 |
+
parameter EXAMPLE = 15; // Note: This line was inserted using parameter override script
|
| 42 |
+
```
|
| 43 |
+
|
| 44 |
+
*Note:*
|
| 45 |
+
This Parameter change will actually change the value of the RTL!!
|
| 46 |
+
This is fine - as long as we test correctly the different parameter variations in the workflow.
|
| 47 |
+
|
| 48 |
+
This is not the best solution because this may cause many redundant commit changes in the git. (the Change in Value is tracked in the git add/commit flow)
|
| 49 |
+
But i think for us - this is a good solution.
|
| 50 |
+
(We are not really expected to manually change the RTL parameters very often. but we want to make sure they are correct)
|
| 51 |
+
|
| 52 |
+
|
| 53 |
+
I will note that the alternative is override the parameter value in the command line (simular to what i just added) but i have some trouble with overriding specific values in the param_pkg.
|
| 54 |
+
Another good alternative is to pass the parameter in the instance of each module -> but this also can get annoying.
|
| 55 |
+
I think will need to this to the most common parameter overrides so we can simply intergrade different version of the same module in the same system. (similar to what we did with the RF_NUM_MSB which is getting override in the module instance)
|
| 56 |
+
|
| 57 |
+
I think you can do this fairly simple
|
| 58 |
+
Let me know if you have any questions
|
issues/FPGA-MAFIA_fpga_mafia_pr451
ADDED
|
@@ -0,0 +1,58 @@
|
|
|
|
|
|
|
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|
|
|
|
|
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|
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|
|
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|
|
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|
|
|
|
|
|
| 1 |
+
# Remove the Parameter override from the build.
|
| 2 |
+
|
| 3 |
+
- Source URL: https://github.com/FPGA-MAFIA/fpga_mafia/issues/441
|
| 4 |
+
|
| 5 |
+
https://github.com/FPGA-MAFIA/fpga_mafia/blob/931deaa13c92a1fe5d29dee95ba23c76531a68f2/build.py#L241C16-L241C16
|
| 6 |
+
|
| 7 |
+
I think there is room for creating a script that can override the parameter value by name - both in source (AKA rtl) and in verif
|
| 8 |
+
|
| 9 |
+
The way it should work is as following:
|
| 10 |
+
In the cfg file add a field that is called "parameter_override"
|
| 11 |
+
``` json
|
| 12 |
+
{
|
| 13 |
+
"I_MEM_OFFSET": 0,
|
| 14 |
+
"I_MEM_LENGTH": 65536,
|
| 15 |
+
"D_MEM_OFFSET": 65536,
|
| 16 |
+
"D_MEM_LENGTH": 61440,
|
| 17 |
+
"crt0_file" : "crt0_mini_rv32e.S",
|
| 18 |
+
"rv32_gcc" : "rv32e -mabi=ilp32e",
|
| 19 |
+
"name" : "rv32e",
|
| 20 |
+
"rtl_parameter_override" : {
|
| 21 |
+
"RF_NUM_MSB" : 31,
|
| 22 |
+
"RF_NUM_LSB" : 0,
|
| 23 |
+
"OTHER_EXAMPLE" : 31
|
| 24 |
+
},
|
| 25 |
+
"verif_pkg_parameter_override" : {
|
| 26 |
+
"TIMEOUT" : 1000000,
|
| 27 |
+
"OTHER_EXAMPLE" : 65403540
|
| 28 |
+
}
|
| 29 |
+
}
|
| 30 |
+
```
|
| 31 |
+
|
| 32 |
+
Then in the "build" call a new script that you need to create that accepts the list of parameters you need to change.
|
| 33 |
+
Make sure use correct regular expression so it overrides only the "parameter <name> = value" instances
|
| 34 |
+
|
| 35 |
+
The scipt will search, find and replace the values that are mentioned in the cfg json file.
|
| 36 |
+
The scipt will also log the info by printing to the screen what he found, where, and what he has changed.
|
| 37 |
+
|
| 38 |
+
During the find replace - add a comment in the line of parameter
|
| 39 |
+
Example:
|
| 40 |
+
```systemverilog
|
| 41 |
+
parameter EXAMPLE = 15; // Note: This line was inserted using parameter override script
|
| 42 |
+
```
|
| 43 |
+
|
| 44 |
+
*Note:*
|
| 45 |
+
This Parameter change will actually change the value of the RTL!!
|
| 46 |
+
This is fine - as long as we test correctly the different parameter variations in the workflow.
|
| 47 |
+
|
| 48 |
+
This is not the best solution because this may cause many redundant commit changes in the git. (the Change in Value is tracked in the git add/commit flow)
|
| 49 |
+
But i think for us - this is a good solution.
|
| 50 |
+
(We are not really expected to manually change the RTL parameters very often. but we want to make sure they are correct)
|
| 51 |
+
|
| 52 |
+
|
| 53 |
+
I will note that the alternative is override the parameter value in the command line (simular to what i just added) but i have some trouble with overriding specific values in the param_pkg.
|
| 54 |
+
Another good alternative is to pass the parameter in the instance of each module -> but this also can get annoying.
|
| 55 |
+
I think will need to this to the most common parameter overrides so we can simply intergrade different version of the same module in the same system. (similar to what we did with the RF_NUM_MSB which is getting override in the module instance)
|
| 56 |
+
|
| 57 |
+
I think you can do this fairly simple
|
| 58 |
+
Let me know if you have any questions
|
issues/FPGA-MAFIA_fpga_mafia_pr452
ADDED
|
@@ -0,0 +1,35 @@
|
|
|
|
|
|
|
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|
|
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|
|
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|
| 1 |
+
# change the directory structure in the verification
|
| 2 |
+
|
| 3 |
+
- Source URL: https://github.com/FPGA-MAFIA/fpga_mafia/issues/442
|
| 4 |
+
|
| 5 |
+
The directory structure in the verification is a little strange and i think it can be improved.
|
| 6 |
+
|
| 7 |
+
The idea is that we will have the same main directory as the RTL.
|
| 8 |
+
Meaning the content of the "verif/cache" should be moved into mem_ss
|
| 9 |
+
and the content of "verif/router" should be moved into fabric.
|
| 10 |
+
|
| 11 |
+
Then the list.f file should be merged into a single file - but keep many different "_tb" files that can be used using the "-top" option in the compilation command.
|
| 12 |
+
|
| 13 |
+
This change will need carful merging in the list.f files, in the include and functions, and the workflow sanity command ext
|
| 14 |
+
|
| 15 |
+
PR Title: Move the verif files around to have less DUT and use the -top flag to…
|
| 16 |
+
PR Number: #452
|
| 17 |
+
Status: Merged
|
| 18 |
+
Author: amichai-bd
|
| 19 |
+
Reviewer/Merger: roman012285
|
| 20 |
+
Date Merged: January 19, 2024
|
| 21 |
+
|
| 22 |
+
Description:
|
| 23 |
+
The PR reorganizes verification files to reduce Device Under Test (DUT) instances and implements the -top flag for proper subIP execution, addressing issue #442 regarding directory structure changes in verification.
|
| 24 |
+
|
| 25 |
+
Key Comments:
|
| 26 |
+
amichai-bd (Jan 20-21): Explained that a pycache file was inadvertently committed during the reorganization. This Python-generated file was created when importing local scripts in mem_ss_pp.py. To prevent future generation, the contributor added sys.dont_write_bytecode = True before the import statement and subsequently suggested consolidating the separate ref_orderer.py file directly into the main script.
|
| 27 |
+
|
| 28 |
+
roman012285: Acknowledged understanding the rationale behind the solution and noted some errors in gui_build.py that were outside the scope of immediate fixes.
|
| 29 |
+
|
| 30 |
+
Commits:
|
| 31 |
+
Two commits were merged:
|
| 32 |
+
1. Primary restructuring commit (b72c071)
|
| 33 |
+
2. Flow name fix commit (d940f1e)
|
| 34 |
+
|
| 35 |
+
The branch was subsequently deleted on March 1, 2024.
|
issues/FPGA-MAFIA_fpga_mafia_pr465
ADDED
|
@@ -0,0 +1,25 @@
|
|
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|
|
|
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|
| 1 |
+
# add HW interrupt support to core_rrv
|
| 2 |
+
|
| 3 |
+
- Source URL: https://github.com/FPGA-MAFIA/fpga_mafia/issues/437
|
| 4 |
+
|
| 5 |
+
The interrupt will start when one of the counters will reach a predefined value.
|
| 6 |
+
|
| 7 |
+
PR Title: fix issues we talked about csr
|
| 8 |
+
|
| 9 |
+
Description:
|
| 10 |
+
The contributor implemented an initial version that executes instructions once the timer interrupt is triggered. This approach ensures interrupts are processed when NOPs are absent, preventing loops. The implementation was tested with multiple timers using the comparison method for valid instructions. All relevant CSR updates are handled in the CSR module rather than software.
|
| 11 |
+
|
| 12 |
+
Commits (4):
|
| 13 |
+
1. Remove CSR check in ctrl and pass to CSR unit
|
| 14 |
+
2. Merge branch 'main' into core_rrv
|
| 15 |
+
3. Fix merge conflict issues
|
| 16 |
+
4. Fix timer interrupt handler
|
| 17 |
+
|
| 18 |
+
Comments:
|
| 19 |
+
roman012285 (Collaborator): "I chose to implement our initial version and execute the instruction once the timer interrupt is triggered... All the updated of relevant csrs are handled in CSR module and not in the software."
|
| 20 |
+
|
| 21 |
+
amichai-bd (Reviewer/Merger): "Great job!"
|
| 22 |
+
|
| 23 |
+
Linked Issue: #437 - "add HW interrupt support to core_rrv"
|
| 24 |
+
|
| 25 |
+
Status: Merged by amichai-bd on February 2, 2024
|
issues/FPGA-MAFIA_fpga_mafia_pr473
ADDED
|
@@ -0,0 +1,20 @@
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
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|
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|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
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|
|
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|
|
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|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| 1 |
+
# Disable correctly the interrupts & restore correctly the enable bits
|
| 2 |
+
|
| 3 |
+
- Source URL: https://github.com/FPGA-MAFIA/fpga_mafia/issues/471
|
| 4 |
+
|
| 5 |
+
|
| 6 |
+
This is wrong - after mret we dont need to enable the "csr_mie" this way.. we need to restore the mstatus correctly!
|
| 7 |
+
|
| 8 |
+
|
| 9 |
+
This is also wrong - don't need to change the csr_mie - only the disable the mstatus
|
| 10 |
+
|
| 11 |
+
Please read carefully again:
|
| 12 |
+
## Timer Interrupt Handling
|
| 13 |
+
When a timer interrupt is taken, you correctly set the mcause with the MSB set to '1' indicating an interrupt, and the cause code for a timer interrupt (0x7).
|
| 14 |
+
However, your handling of mie (Machine Interrupt Enable) and mstatus might not accurately reflect the typical behavior expected upon an interrupt.
|
| 15 |
+
Disabling interrupts by setting mie might not be necessary here; instead, interrupts are usually disabled by clearing the MIE bit in the mstatus register, not by directly manipulating mie.
|
| 16 |
+
The update to mstatus seems to intend to manipulate interrupt enable bits directly. Typically, upon taking an interrupt, the hardware would clear the MIE bit in mstatus, saving the previous state in MPIE, and update MPP if needed. Your comment regarding setting mstatus[7] equal to mstatus[3] seems to misunderstand the mstatus register's bit fields.
|
| 17 |
+
## Return from Interrupt (MRET)
|
| 18 |
+
Upon executing MRET, the typical behavior is to restore the previous interrupt enable state by copying MPIE to MIE in mstatus, not by directly setting mie. Your code seems to directly enable interrupts by setting mie and mstatus which might not correctly restore the previous state.
|
| 19 |
+
The mstatus update to 0x8 directly seems incorrect. The MRET instruction itself should handle the restoration of mstatus fields, specifically MIE and MPIE, based on their pre-interrupt values.
|
| 20 |
+
Clearing mip directly on MRET might not be necessary or correct, as mip reflects pending interrupts and is typically managed by acknowledging the interrupt source (like writing to a timer register to clear the timer interrupt).
|
issues/FPGA-MAFIA_fpga_mafia_pr479
ADDED
|
@@ -0,0 +1,37 @@
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
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|
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|
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|
|
|
|
|
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|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
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|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| 1 |
+
# core_rrv - create a dedicated test for the timer interrupt during a illegal instruction trap
|
| 2 |
+
|
| 3 |
+
- Source URL: https://github.com/FPGA-MAFIA/fpga_mafia/issues/477
|
| 4 |
+
|
| 5 |
+
Create a test that has both "illegal instruction trap" and "timer interrupts".
|
| 6 |
+
|
| 7 |
+
I am hoping to see hit this case:
|
| 8 |
+
|
| 9 |
+
- illegal instruction trap exception handler is in progress (MIE set to 0 by HW)
|
| 10 |
+
- Timer interrupt time condition met -> but MIE is 0, so no exception is taken yet
|
| 11 |
+
- illegal instruction handler return with MRET (MIE back to 1)
|
| 12 |
+
- Timer interrupt condition is still set so the timer interrupt exception handler takes place
|
| 13 |
+
- We return from the timer interrupts and continue execution
|
| 14 |
+
|
| 15 |
+
PR Title: add test timer exception after illegal instruction trap + debug csr's
|
| 16 |
+
Status: Merged on Feb 14, 2024
|
| 17 |
+
|
| 18 |
+
Description: No description was provided in the pull request.
|
| 19 |
+
|
| 20 |
+
Commits (7 total):
|
| 21 |
+
1. "add clear and set csr macros"
|
| 22 |
+
2. "add debud csrs. dpc, dcsr, dscratch0, dscratch1"
|
| 23 |
+
3. "add test for checking alive illegal before timer interrupt"
|
| 24 |
+
4. "disable mie to avoid timer exception while printing. may cause misses"
|
| 25 |
+
5. "Merge branch 'main' into core_rrv"
|
| 26 |
+
6. "modify regrees file"
|
| 27 |
+
7. "add debug csrs, custom_mtime, custom_mtimecmp and custom_lfsr"
|
| 28 |
+
|
| 29 |
+
Review Comments:
|
| 30 |
+
amichai-bd (reviewer/approver):
|
| 31 |
+
- Regarding cycle/instret counter synchronization: "The plan is to artificially match the ref model performance IPC with the DUT performance so the 2 tests can be compared correctly."
|
| 32 |
+
- On LFSR updates: Expected hardware LFSR updates "only when there is a read/write from the LFSR CSR" by moving logic into read/write cases
|
| 33 |
+
|
| 34 |
+
roman012285 (author) response to LFSR comment: Indicated the fix hadn't been implemented yet ("עוד לא הגעתי לזה")
|
| 35 |
+
|
| 36 |
+
Linked Issue:
|
| 37 |
+
Issue #477: "create a dedicated test for the timer interrupt during a illegal instruction trap"
|
issues/FPGA-MAFIA_fpga_mafia_pr495
ADDED
|
@@ -0,0 +1,25 @@
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| 1 |
+
# rvc_sample_csr - this is not a name we should use for the specific csr read of 0xb00 and 0xb02
|
| 2 |
+
|
| 3 |
+
- Source URL: https://github.com/FPGA-MAFIA/fpga_mafia/issues/489
|
| 4 |
+
|
| 5 |
+
Acording to the spec - done we have a "correct" name for the mcycle and instret?
|
| 6 |
+
Please revisit this and fix the name, the way we use it, where we use it, etc..
|
| 7 |
+
|
| 8 |
+
|
| 9 |
+
PR Title: refactor lfsr read condition and address of time and instret csr's
|
| 10 |
+
|
| 11 |
+
Description: No description provided.
|
| 12 |
+
|
| 13 |
+
Commits:
|
| 14 |
+
1. "refactor CSR address from machine to user mode"
|
| 15 |
+
2. "refactor - lfsr read condition"
|
| 16 |
+
3. Merge branch 'main' into core_rrv
|
| 17 |
+
|
| 18 |
+
Linked Issue: #489 - "rvc_sample_csr - this is not a name we should use for the specific csr read of 0xb00 and 0xb02"
|
| 19 |
+
|
| 20 |
+
Comments:
|
| 21 |
+
amichai-bd (Reviewer): "Still this function name makes no sense to me.. 'rvc_sample_csr' -> what is this function actually do? I feel like I'm missing something here"
|
| 22 |
+
|
| 23 |
+
roman012285 (Author): "we read the clycle and instret in alive_ipc test and calculates ipc"
|
| 24 |
+
|
| 25 |
+
Status: Merged by roman012285 on Feb 20, 2024
|
issues/FPGA-MAFIA_fpga_mafia_pr499
ADDED
|
@@ -0,0 +1,28 @@
|
|
|
|
|
|
|
|
|
|
|
|
|
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|
|
|
|
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|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| 1 |
+
# remove nop from mini_core rv32e/i configuration fails to pass sanity test
|
| 2 |
+
|
| 3 |
+
- Source URL: https://github.com/FPGA-MAFIA/fpga_mafia/issues/497
|
| 4 |
+
|
| 5 |
+
`python build.py -dut 'mini_core' -regress rv32i_level0 -app -hw -sim -keep_going`
|
| 6 |
+
./build.py -cfg mini_rv32i -dut mini_core -test basic -app -hw -sim -clean
|
| 7 |
+
|
| 8 |
+
when nothing written after `ebreak` it causes that fail
|
| 9 |
+
|
| 10 |
+
PR Title: fix ref_model didnt stop after ebreak
|
| 11 |
+
Status: Merged
|
| 12 |
+
Author: roman012285
|
| 13 |
+
Branch: core_rrv → main (merged Feb 21, 2024)
|
| 14 |
+
|
| 15 |
+
Description:
|
| 16 |
+
No description was provided for this pull request.
|
| 17 |
+
|
| 18 |
+
Commits:
|
| 19 |
+
1. "fix ref_model didnt stopped after ebreak" (2abdd32)
|
| 20 |
+
2. "remove nop" (8e0c07f)
|
| 21 |
+
|
| 22 |
+
Comments:
|
| 23 |
+
roman012285 changed the PR title from "dix ref_model didnt stop after ebreak" to the corrected version.
|
| 24 |
+
|
| 25 |
+
Linked Issue:
|
| 26 |
+
#497: "remove nop from mini_core rv32e/i configuration fails to pass sanity test"
|
| 27 |
+
|
| 28 |
+
This PR appears to address a bug where a reference model wasn't properly terminating after an "ebreak" instruction, with changes involving the removal of a no-operation instruction from a RISC-V core configuration.
|
issues/FPGA-MAFIA_fpga_mafia_pr548
ADDED
|
@@ -0,0 +1,27 @@
|
|
|
|
|
|
|
|
|
|
|
|
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|
|
|
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|
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|
|
|
|
|
| 1 |
+
# Add a-j to print function in vga lib
|
| 2 |
+
|
| 3 |
+
- Source URL: https://github.com/FPGA-MAFIA/fpga_mafia/issues/531
|
| 4 |
+
|
| 5 |
+
PR Title: charcters a-k and more
|
| 6 |
+
Status: Merged
|
| 7 |
+
Author: jacobavitan837
|
| 8 |
+
Merge Details: Merged 2 commits from jacob_branch into main on March 11, 2024 by roman012285
|
| 9 |
+
|
| 10 |
+
Description:
|
| 11 |
+
The PR extends the graphic VGA library with additional character support (letters a through k and beyond).
|
| 12 |
+
|
| 13 |
+
Key Comments:
|
| 14 |
+
jacobavitan837's Request: "please review and approve"
|
| 15 |
+
|
| 16 |
+
NoamRahat's Review Feedback:
|
| 17 |
+
Suggested adhering to standard coding conventions by writing preprocessor directives in uppercase, noting: "I think it would be a good idea to stick to common convention..."
|
| 18 |
+
|
| 19 |
+
roman012285's Response:
|
| 20 |
+
Agreed with the styling feedback, recommending consistency with existing patterns where "every thing is written in big letters except the letter itself" (e.g., A_TOP format).
|
| 21 |
+
|
| 22 |
+
NoamRahat's Clarification:
|
| 23 |
+
Proposed examples like changing Slash_TOP to SLASH_TOP and a_TOP to SMALL_A_TOP for consistency.
|
| 24 |
+
|
| 25 |
+
Linked Issues:
|
| 26 |
+
- Issue #531: "Add a-j to print function in vga lib"
|
| 27 |
+
- Issue #545: "add the rest characters to print function in vga lib"
|
issues/FPGA-MAFIA_fpga_mafia_pr559
ADDED
|
@@ -0,0 +1,32 @@
|
|
|
|
|
|
|
|
|
|
|
|
|
|
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|
| 1 |
+
# rrv_core - Add a assertion for illegal memory access region.
|
| 2 |
+
|
| 3 |
+
- Source URL: https://github.com/FPGA-MAFIA/fpga_mafia/issues/498
|
| 4 |
+
|
| 5 |
+
We should add an assertion making sure that if we have a load/store its for a d_mem/cr/vga region..
|
| 6 |
+
(this would ease debugging when the SW tries to access the wrong memory space completely.. )
|
| 7 |
+
|
| 8 |
+
PR Title: add assertion when accessing address out of range
|
| 9 |
+
PR Number: #559
|
| 10 |
+
Status: Merged
|
| 11 |
+
Author: roman012285
|
| 12 |
+
Reviewer/Merger: amichai-bd
|
| 13 |
+
Merge Date: March 13, 2024
|
| 14 |
+
|
| 15 |
+
Description:
|
| 16 |
+
No formal description was provided by the author.
|
| 17 |
+
|
| 18 |
+
Key Comments:
|
| 19 |
+
amichai-bd's Initial Review Questions:
|
| 20 |
+
- Questioned why a SIM_ONLY definition was commented out in the test file list
|
| 21 |
+
- Noted that a preprocessor directive should use ifdef instead of ifndef for the memory access assertion section
|
| 22 |
+
|
| 23 |
+
roman012285's Responses:
|
| 24 |
+
The author acknowledged making changes immediately after pushing and committed to fixing the preprocessor directive, stating: "I changed it right after I made push, I will commit it when i will be near computer. I must change ifndef to ifdef also"
|
| 25 |
+
|
| 26 |
+
After implementing corrections, roman012285 requested: "fixed - Please review the changes"
|
| 27 |
+
|
| 28 |
+
Final Approval:
|
| 29 |
+
amichai-bd approved the revised implementation and merged the pull request.
|
| 30 |
+
|
| 31 |
+
Related Issue:
|
| 32 |
+
This PR links to and likely closes issue #498: "rrv_core - Add a assertion for illegal memory access region"
|
issues/FPGA-MAFIA_fpga_mafia_pr638
ADDED
|
@@ -0,0 +1,40 @@
|
|
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|
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|
| 1 |
+
# writing MC (memory controller) for communication between host and SDRAM
|
| 2 |
+
|
| 3 |
+
- Source URL: https://github.com/FPGA-MAFIA/fpga_mafia/issues/611
|
| 4 |
+
|
| 5 |
+
** Goal
|
| 6 |
+
- Create communication interface between host computer and SDRAM
|
| 7 |
+
|
| 8 |
+
** requirements
|
| 9 |
+
- The controller will receive 128bit data (cache line) and transfer it to SDRAM at 16bit granularity.
|
| 10 |
+
- The communication is bi-directional
|
| 11 |
+
- The unit will take care of forwarding in case of RAW (read after write) that causes data hazard
|
| 12 |
+
- The protocol designed to work with DE10-lite SDRAM
|
| 13 |
+
- Support bursts
|
| 14 |
+
**Further specifications will be added in the future**
|
| 15 |
+
|
| 16 |
+
PR Title: Sdram controler for read/write 8 length bursts
|
| 17 |
+
|
| 18 |
+
Description:
|
| 19 |
+
The contributor submitted an FPGA design for an SDRAM controller supporting burst operations. Key details include:
|
| 20 |
+
- Controller Location: source/mem_ss/sdram_ctrl_bursts
|
| 21 |
+
- FPGA Design Location: /FPGA/sdram_full
|
| 22 |
+
|
| 23 |
+
The author noted temporary additions would be removed once the complete memory subsystem is functional, including some FPGA folders and .vh files within source/mem_ss.
|
| 24 |
+
|
| 25 |
+
Demonstration:
|
| 26 |
+
The PR included three test case examples showing write/read functionality:
|
| 27 |
+
- Writing to random address 0x0018
|
| 28 |
+
- Reading from that address
|
| 29 |
+
- Screenshots displaying read/write data and address values during operation
|
| 30 |
+
|
| 31 |
+
Commits:
|
| 32 |
+
The PR merged 11 commits (May 1-9, 2024), including:
|
| 33 |
+
- Controller implementation for burst operations
|
| 34 |
+
- FPGA test directory additions
|
| 35 |
+
- FSM implementations for random burst testing across addresses/banks
|
| 36 |
+
- Debugging fixes and refresh logic enhancements
|
| 37 |
+
|
| 38 |
+
Status: Merged on May 10, 2024 by roman012285
|
| 39 |
+
Assigned to: amichai-bd
|
| 40 |
+
Related Issue: #611 - "writing MC (memory controller) for communication between host and SDRAM"
|
issues/FPGA-MAFIA_fpga_mafia_pr646
ADDED
|
@@ -0,0 +1,34 @@
|
|
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|
| 1 |
+
# add M extension to big_core
|
| 2 |
+
|
| 3 |
+
- Source URL: https://github.com/FPGA-MAFIA/fpga_mafia/issues/648
|
| 4 |
+
|
| 5 |
+
- implement multiplication in HW in straight forward manner. We do that because FPGA has dedicated multipliers
|
| 6 |
+
- implement division as exception trap
|
| 7 |
+
|
| 8 |
+
PR Title: add m_extension support
|
| 9 |
+
Status: Merged
|
| 10 |
+
Merged by: amichai-bd on May 21, 2024
|
| 11 |
+
Source Branch: big_core_RV32IM → main
|
| 12 |
+
Commits: 4
|
| 13 |
+
|
| 14 |
+
Description:
|
| 15 |
+
The contributor successfully implemented RISC-V M extension (multiplication/division) support for the big_core processor. The implementation uses trap-based division handling and includes custom CSR functionality for storing the stack pointer.
|
| 16 |
+
|
| 17 |
+
Test Command:
|
| 18 |
+
./build.py -dut big_core -test m_extension -app -cfg big_core_rv32im -hw -sim
|
| 19 |
+
|
| 20 |
+
Results demonstrated: Division, unsigned division, remainder, and unsigned remainder operations with test case 34÷4, plus negative number handling and overflow/division-by-zero edge cases.
|
| 21 |
+
|
| 22 |
+
Key Comments:
|
| 23 |
+
roman012285 (Author):
|
| 24 |
+
- "it took allot of time to understand the pointers and debug every thing"
|
| 25 |
+
- Acknowledged performance concerns with naive division algorithm
|
| 26 |
+
- Noted potential stability issues with large unsigned number division and memory safety during interrupt handling
|
| 27 |
+
|
| 28 |
+
amichai-bd (Reviewer):
|
| 29 |
+
- Flagged inefficient division algorithms with comments: "Wow - this is why it takes so long! please change to a better algorithm"
|
| 30 |
+
- Requested terminology clarification (pointer vs. address; register file pointer vs. address)
|
| 31 |
+
- Confirmed test was included: "BIG_CORE -cfg big_core_rv32im with reference model"
|
| 32 |
+
|
| 33 |
+
Linked Issue:
|
| 34 |
+
#648: add M extension to big_core - marked for closure
|
issues/FPGA-MAFIA_fpga_mafia_pr655
ADDED
|
@@ -0,0 +1,30 @@
|
|
|
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|
|
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|
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|
|
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|
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|
|
|
|
| 1 |
+
# Cache - support partiol read/write (byte enable)
|
| 2 |
+
|
| 3 |
+
- Source URL: https://github.com/FPGA-MAFIA/fpga_mafia/issues/583
|
| 4 |
+
|
| 5 |
+
Cache - support partial read/write (byte enable)
|
| 6 |
+
LHU, LBU, LW,LH,LB SW,SH,SB
|
| 7 |
+
Also, support signed and unsigned extends for the memory load request.
|
| 8 |
+
|
| 9 |
+
PR Title: modify chach_tasks.vh to support random partial reads and writes
|
| 10 |
+
PR Number: #655
|
| 11 |
+
Status: Merged
|
| 12 |
+
Repository: FPGA-MAFIA/fpga_mafia
|
| 13 |
+
|
| 14 |
+
Description:
|
| 15 |
+
No formal description was provided by the author.
|
| 16 |
+
|
| 17 |
+
Comments:
|
| 18 |
+
amichai-bd (May 28, 2024):
|
| 19 |
+
"Small refactor into a single 'Case'"
|
| 20 |
+
The reviewer noted a code consolidation effort with an accompanying image reference.
|
| 21 |
+
|
| 22 |
+
amichai-bd (May 28, 2024):
|
| 23 |
+
"I will also note that the verification env for this Cache is not really good.. It takes a long time to build and simulate - i suspect its due to something wring we did here.. Also a lot of code is duplicated - we should be able to use parameters to have different flavors of similar tasks."
|
| 24 |
+
The reviewer raised concerns about verification environment performance and code duplication, suggesting future refactoring opportunities.
|
| 25 |
+
|
| 26 |
+
Linked Issue:
|
| 27 |
+
#583 - "Cache - support partiol read/write (byte enable)" (Closed by this PR)
|
| 28 |
+
|
| 29 |
+
Commits Overview:
|
| 30 |
+
13 commits were merged, including initial test additions, byte offset support for D_CACHE, partial read/write handling, and byte enable offset fixes across fill requests.
|
issues/FPGA-MAFIA_fpga_mafia_pr680
ADDED
|
@@ -0,0 +1,23 @@
|
|
|
|
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|
|
|
|
|
|
|
| 1 |
+
# Refactor the CR memory space
|
| 2 |
+
|
| 3 |
+
- Source URL: https://github.com/FPGA-MAFIA/fpga_mafia/issues/679
|
| 4 |
+
|
| 5 |
+
## Issue Title
|
| 6 |
+
Refactor the CR memory space
|
| 7 |
+
|
| 8 |
+
## Issue Description
|
| 9 |
+
Create a simple struct for the all CR! This shold solve the error in the readafter write issue we have.
|
| 10 |
+
|
| 11 |
+
(The issue proposes organizing the Control Register (CR) memory space using a structured data type to address read-after-write synchronization problems in the FPGA-MAFIA project.)
|
| 12 |
+
|
| 13 |
+
## Issue Comments
|
| 14 |
+
None.
|
| 15 |
+
|
| 16 |
+
## Issue Metadata
|
| 17 |
+
- Status: Closed (linked to PR #680)
|
| 18 |
+
- Assignee: amichai-bd
|
| 19 |
+
- Labels: RTL design, build & env
|
| 20 |
+
- Created: June 16, 2024
|
| 21 |
+
|
| 22 |
+
## Linked Issues / PRs
|
| 23 |
+
- PR #680 — the resolution implementation
|
issues/HiSA-Team_Simply-V_pr102
ADDED
|
@@ -0,0 +1,27 @@
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
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|
|
|
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|
|
|
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|
|
|
|
|
|
|
|
|
|
|
| 1 |
+
# [bugfix/sync_pbus_interrupts] Add synchronizers for PBUS interrupts
|
| 2 |
+
|
| 3 |
+
- Source URL: https://github.com/HiSA-Team/Simply-V/issues/101
|
| 4 |
+
|
| 5 |
+
## Issue Title
|
| 6 |
+
[bugfix/sync_pbus_interrupts] Add synchronizers for PBUS interrupts
|
| 7 |
+
|
| 8 |
+
## Issue Description
|
| 9 |
+
During CDC (#91) we forgot to re-synchronize PBUS outgoing interrupts to the MAIN_CLOCK_DOMAIN.
|
| 10 |
+
|
| 11 |
+
This could be fixed by adding a NUM_IRQ-wide xpm_cdc_async_rst in pbus between int_o and each peripheral interrupt, instead of just assigning them as in the prior implementation.
|
| 12 |
+
|
| 13 |
+
Additionally, here we could also fix unassigned int_o bits.
|
| 14 |
+
|
| 15 |
+
## Issue Comments
|
| 16 |
+
None visible.
|
| 17 |
+
|
| 18 |
+
## Issue Metadata
|
| 19 |
+
- Status: Closed (via PR #102)
|
| 20 |
+
- Assignee: DOTTORM5
|
| 21 |
+
- Milestone: MCU release
|
| 22 |
+
- Author: MaistoV
|
| 23 |
+
- Date Opened: April 8, 2025
|
| 24 |
+
|
| 25 |
+
## Linked Issues / PRs
|
| 26 |
+
- PR #102 — fix
|
| 27 |
+
- Refers back to #91 (prior CDC work)
|
issues/HiSA-Team_Simply-V_pr108
ADDED
|
@@ -0,0 +1,22 @@
|
|
|
|
|
|
|
|
|
|
|
|
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|
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|
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|
|
|
|
|
| 1 |
+
# [feature/rv64/rtl] RV64: RTL & IPs adjustments
|
| 2 |
+
|
| 3 |
+
- Source URL: https://github.com/HiSA-Team/Simply-V/issues/86
|
| 4 |
+
|
| 5 |
+
**UninaSoC RTL**
|
| 6 |
+
|
| 7 |
+
- [x] header files (`svh`) for protocols can work with adjusting the DATA_WIDTH, STRB and ID. To do so, let's remove parameters (as they are not used) and move to parametric macros and declarations (including ports)
|
| 8 |
+
- [x] Update files in `rtl` to support new `svh` macros
|
| 9 |
+
- [x] Update `.svinc` file generation
|
| 10 |
+
- [x] uninasoc.sv should be independent from XLEN, however all hardcoded references to 32 bits must be removed (if any).
|
| 11 |
+
- [x] Clock_converters and Dwidth_converters: DDR4
|
| 12 |
+
- [x] Clock_converters and Dwidth_converters: PBUS
|
| 13 |
+
- [x] Clock_converters and Dwidth_converters: Sys Master
|
| 14 |
+
- [x] Clock_converters and Dwidth_converters: PLIC
|
| 15 |
+
- [x] Regarding the socket, the idea is to assume a user will always use a 64-bits CPU if XLEN=64; therefore a simple assert will do the job, stopping the build if the core selector is incompatible with the XLEN. **Note** in #83 core and xlen compatibility will be checked as well
|
| 16 |
+
|
| 17 |
+
**UninaSoC IPS**
|
| 18 |
+
|
| 19 |
+
- [x] Update files in `rtl` to support new `svh` macros
|
| 20 |
+
- [x] The IP config files should take into account the change of data width and address width. (e.g. block mem generator).
|
| 21 |
+
- [x] Custom IPS will be independent from the config flow. For now, all peripherals on the pbus will be at 32, and only the PLIC might change between 32 and 64.
|
| 22 |
+
- [x] Add PLIC new Target (for socket S-mode) -> Moved to #107
|
issues/HiSA-Team_Simply-V_pr118
ADDED
|
@@ -0,0 +1,36 @@
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
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|
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|
|
|
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|
|
|
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|
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|
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|
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|
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|
|
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|
|
|
|
|
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|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| 1 |
+
# [Submission] <hidden> 2025
|
| 2 |
+
|
| 3 |
+
- Source URL: https://github.com/HiSA-Team/Simply-V/issues/65
|
| 4 |
+
|
| 5 |
+
## Issue Title
|
| 6 |
+
[Submission] <hidden> 2025
|
| 7 |
+
|
| 8 |
+
## Issue Description
|
| 9 |
+
This issue tracks all the technical tasks for the <hidden> submission.
|
| 10 |
+
|
| 11 |
+
Paper evaluation tasks:
|
| 12 |
+
- CPU Benchmark (tacle-bench)
|
| 13 |
+
- HLS integration
|
| 14 |
+
- HLS peripheral iterative fast-prototyping
|
| 15 |
+
- HLS experiments embedded
|
| 16 |
+
- HLS experiments HPC
|
| 17 |
+
- HLS experiments on HBUS
|
| 18 |
+
- RV64: CVA6 tacle-bench on BRAM (embedded)
|
| 19 |
+
- RV64: CVA6 tacle-bench on BRAM (hpc)
|
| 20 |
+
- RV64: CVA6 tacle-bench on DDR (hpc)
|
| 21 |
+
- RVV (tracked in #119)
|
| 22 |
+
- Veer Core (tracked in #67)
|
| 23 |
+
|
| 24 |
+
The checklist shows 7 of 7 items completed. Issue linked to pull request #118.
|
| 25 |
+
|
| 26 |
+
## Issue Comments
|
| 27 |
+
None visible.
|
| 28 |
+
|
| 29 |
+
## Issue Metadata
|
| 30 |
+
- Status: Closed
|
| 31 |
+
- Assignee: MaistoV
|
| 32 |
+
|
| 33 |
+
## Linked Issues / PRs
|
| 34 |
+
- PR #118 — submission tracker resolution
|
| 35 |
+
- #119: feature request for PULP Ara RVV support
|
| 36 |
+
- #67: feature request for VeerWolf core integration
|
issues/HiSA-Team_Simply-V_pr129
ADDED
|
@@ -0,0 +1,30 @@
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| 1 |
+
# [feature/rv64/cv64a6] RV64: Integrate CV64A6
|
| 2 |
+
|
| 3 |
+
- Source URL: https://github.com/HiSA-Team/Simply-V/issues/82
|
| 4 |
+
|
| 5 |
+
Integrating CV64A6
|
| 6 |
+
|
| 7 |
+
**Generic**
|
| 8 |
+
- [x] Rebase on Main
|
| 9 |
+
- [x] Restore HBUS behaviour and revert openocd
|
| 10 |
+
|
| 11 |
+
**Hardware**
|
| 12 |
+
- [x] Integrate CV64A6 in the socket
|
| 13 |
+
- [x] Integrate JTAG2AXI DWIDTH converter
|
| 14 |
+
- [x] Fix RTL: peripheral crossbar generation
|
| 15 |
+
- [x] Fix linker script generation: stack alignment
|
| 16 |
+
- [x] Add patching in OpenHW fetch sources script
|
| 17 |
+
- [x] Stabilize 64-bits toolchain
|
| 18 |
+
- [x] Integrate 64-bits debugging
|
| 19 |
+
- [x] Add our configs into Assets with symbolic linking
|
| 20 |
+
- [x] Connect Interrupts
|
| 21 |
+
|
| 22 |
+
**Software**
|
| 23 |
+
- [x] Update tinyIO to be compiled at 64 bits
|
| 24 |
+
- [x] Test Software : Blinky
|
| 25 |
+
- [x] Test Software : Echo
|
| 26 |
+
- [x] Test Software: Hello World
|
| 27 |
+
- [x] Test Software: Interrupts
|
| 28 |
+
- [x] Prototype bootrom
|
| 29 |
+
|
| 30 |
+
> BUG: OpenHW CVA6 v0.5.1 with C-ext enabled can't run code without C-ext
|
issues/HiSA-Team_Simply-V_pr147
ADDED
|
@@ -0,0 +1,27 @@
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| 1 |
+
# [feature/rv64/microblazev] Integrate RV64 version of Microblaze-V
|
| 2 |
+
|
| 3 |
+
- Source URL: https://github.com/HiSA-Team/Simply-V/issues/114
|
| 4 |
+
|
| 5 |
+
## Issue Title
|
| 6 |
+
[feature/rv64/microblazev] Integrate RV64 version of Microblaze-V
|
| 7 |
+
|
| 8 |
+
## Issue Description
|
| 9 |
+
Assigned to Salvatore Santoro.
|
| 10 |
+
|
| 11 |
+
Add microblaze_riscv_rv64 Xilinx IP (UG1629).
|
| 12 |
+
|
| 13 |
+
W.r.t. microblaze_riscv IP, the only parameters to change are:
|
| 14 |
+
1. CONFIG.C_DATA_SIZE = 64
|
| 15 |
+
2. CONFIG.C_ADDR_SIZE — supported values: 32, 36, 40, 44, 48, 52, 56, 64
|
| 16 |
+
|
| 17 |
+
Note that when enabling RV64 (rather than RV32), all the interfaces remain 32-bits wide, therefore a couple of dwidth adapters should do the trick.
|
| 18 |
+
|
| 19 |
+
## Issue Comments
|
| 20 |
+
None visible.
|
| 21 |
+
|
| 22 |
+
## Issue Metadata
|
| 23 |
+
- Status: Closed (linked to PR #147)
|
| 24 |
+
- Assignee: MaistoV
|
| 25 |
+
|
| 26 |
+
## Linked Issues / PRs
|
| 27 |
+
- PR #147 — implements this feature
|
issues/HiSA-Team_Simply-V_pr166
ADDED
|
@@ -0,0 +1,24 @@
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
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|
|
|
|
|
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|
|
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|
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|
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|
|
|
|
|
|
|
|
|
|
|
|
|
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|
|
|
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|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| 1 |
+
# [feature/rvv/ara] Integrate PULP Ara for RVV support
|
| 2 |
+
|
| 3 |
+
- Source URL: https://github.com/HiSA-Team/Simply-V/issues/119
|
| 4 |
+
|
| 5 |
+
## Issue Title
|
| 6 |
+
[feature/rvv/ara] Integrate PULP Ara for RVV support
|
| 7 |
+
|
| 8 |
+
## Issue Description
|
| 9 |
+
- Need finalized CVA6 support
|
| 10 |
+
- Integrate CVA6 + Ara as a single custom IP (different than standalone cv64a6)
|
| 11 |
+
- Use Ara 2-lanes, matching CVA6 data width, e.g. 64-bits
|
| 12 |
+
|
| 13 |
+
TODO (move to another issue):
|
| 14 |
+
- Ara 4- and 8-lanes: Attach Ara AXI master to HBUS
|
| 15 |
+
|
| 16 |
+
## Issue Comments
|
| 17 |
+
None visible.
|
| 18 |
+
|
| 19 |
+
## Issue Metadata
|
| 20 |
+
- Status: Closed (with associated PR #166)
|
| 21 |
+
- Assignee: MaistoV
|
| 22 |
+
|
| 23 |
+
## Linked Issues / PRs
|
| 24 |
+
- PR #166 — addresses this feature request
|
issues/HiSA-Team_Simply-V_pr184
ADDED
|
@@ -0,0 +1,27 @@
|
|
|
|
|
|
|
|
|
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|
|
|
|
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|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| 1 |
+
# [feature/axi_cdma/basic][student] Basic AXI CDMA integration
|
| 2 |
+
|
| 3 |
+
- Source URL: https://github.com/HiSA-Team/Simply-V/issues/162
|
| 4 |
+
|
| 5 |
+
## Issue Title
|
| 6 |
+
[feature/axi_cdma/basic][student] Basic AXI CDMA integration
|
| 7 |
+
|
| 8 |
+
## Issue Description
|
| 9 |
+
Assigned to Michele Giugliano.
|
| 10 |
+
|
| 11 |
+
Integration design diagram is attached. See parent issue #153 for further details.
|
| 12 |
+
|
| 13 |
+
The submission represents a student-led feature development task related to AXI CDMA (Advanced eXtensible Interface Central Direct Memory Access) integration. It indicates a hierarchical issue structure with parent issue #153 containing broader requirements.
|
| 14 |
+
|
| 15 |
+
## Issue Comments
|
| 16 |
+
None visible.
|
| 17 |
+
|
| 18 |
+
## Issue Metadata
|
| 19 |
+
- Status: Closed (merged via PR #184)
|
| 20 |
+
- Assignee: MaistoV
|
| 21 |
+
- Labels: None
|
| 22 |
+
- Type: None
|
| 23 |
+
- Project / milestone: None
|
| 24 |
+
|
| 25 |
+
## Linked Issues / PRs
|
| 26 |
+
- PR #184 — implementation
|
| 27 |
+
- Parent issue: #153
|
issues/HiSA-Team_Simply-V_pr48
ADDED
|
@@ -0,0 +1,26 @@
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
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|
|
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|
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|
|
|
|
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|
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|
|
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|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| 1 |
+
# [feature/debug_module] Integrate RISC-V debug module
|
| 2 |
+
|
| 3 |
+
- Source URL: https://github.com/HiSA-Team/Simply-V/issues/22
|
| 4 |
+
|
| 5 |
+
## Issue Title
|
| 6 |
+
[feature/debug_module] Integrate RISC-V debug module
|
| 7 |
+
|
| 8 |
+
## Issue Description
|
| 9 |
+
Add RISC-V debug module (https://github.com/pulp-platform/riscv-dbg/tree/v0.8.1) and expose it on Xilinx scanchain to make it visible to hw_server.
|
| 10 |
+
|
| 11 |
+
Tentatively try to integrate it with jtag-ext-bscan.vhdl (https://github.com/eugene-tarassov/vivado-risc-v/blob/master/vhdl-wrapper/src/net/largest/riscv/vhdl/jtag-ext-bscan.vhdl).
|
| 12 |
+
|
| 13 |
+
Most likely there are going to be compatibility issues with JTAG, BSCAN and hw_server.
|
| 14 |
+
|
| 15 |
+
Alternatively, just fall-back to PULP BSCAN tap (https://github.com/pulp-platform/riscv-dbg/blob/master/src/dmi_bscane_tap.sv) and OpenOCD. In this case, the issue would be the OpenOCD config file for Nexys and Alveo.
|
| 16 |
+
|
| 17 |
+
## Issue Comments
|
| 18 |
+
No comments are present on this issue.
|
| 19 |
+
|
| 20 |
+
## Issue Metadata
|
| 21 |
+
- Status: Closed
|
| 22 |
+
- Assignee: MaistoV
|
| 23 |
+
- Milestone: MCU release
|
| 24 |
+
|
| 25 |
+
## Linked Issues / PRs
|
| 26 |
+
- PR #48 — associated pull request (closed)
|
issues/HiSA-Team_Simply-V_pr52
ADDED
|
@@ -0,0 +1,20 @@
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
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|
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|
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|
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|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| 1 |
+
# [feature/core_selection] Add core selection to Make flow
|
| 2 |
+
|
| 3 |
+
- Source URL: https://github.com/HiSA-Team/Simply-V/issues/20
|
| 4 |
+
|
| 5 |
+
## Issue Title
|
| 6 |
+
[feature/core_selection] Add core selection to Make flow
|
| 7 |
+
|
| 8 |
+
## Issue Description
|
| 9 |
+
Add core selection to Make flow for RVM socket CORE_SELECTION parameter.
|
| 10 |
+
|
| 11 |
+
## Issue Comments
|
| 12 |
+
None visible.
|
| 13 |
+
|
| 14 |
+
## Issue Metadata
|
| 15 |
+
- Status: Closed
|
| 16 |
+
- Assignee: MaistoV
|
| 17 |
+
- Milestone: MCU release
|
| 18 |
+
|
| 19 |
+
## Linked Issues / PRs
|
| 20 |
+
- PR #52 — implementation (closed)
|
issues/HiSA-Team_Simply-V_pr68
ADDED
|
@@ -0,0 +1,20 @@
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| 1 |
+
# [debug/plic] Fix PLIC integration
|
| 2 |
+
|
| 3 |
+
- Source URL: https://github.com/HiSA-Team/Simply-V/issues/50
|
| 4 |
+
|
| 5 |
+
## Issue Title
|
| 6 |
+
[debug/plic] Fix PLIC integration
|
| 7 |
+
|
| 8 |
+
## Issue Description
|
| 9 |
+
No description provided.
|
| 10 |
+
|
| 11 |
+
## Issue Comments
|
| 12 |
+
None visible.
|
| 13 |
+
|
| 14 |
+
## Issue Metadata
|
| 15 |
+
- Status: Closed
|
| 16 |
+
- Assignee: Granp4sso
|
| 17 |
+
- Milestone: MCU release
|
| 18 |
+
|
| 19 |
+
## Linked Issues / PRs
|
| 20 |
+
- PR #68 — closing PR
|
issues/HiSA-Team_Simply-V_pr92
ADDED
|
@@ -0,0 +1,24 @@
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| 1 |
+
# [feature/cores/ibex] Integrate Ibex core as custom IP
|
| 2 |
+
|
| 3 |
+
- Source URL: https://github.com/HiSA-Team/Simply-V/issues/66
|
| 4 |
+
|
| 5 |
+
## Issue Title
|
| 6 |
+
[feature/cores/ibex] Integrate Ibex core as custom IP
|
| 7 |
+
|
| 8 |
+
## Issue Description
|
| 9 |
+
From https://github.com/lowRISC/ibex.
|
| 10 |
+
|
| 11 |
+
Issues:
|
| 12 |
+
- which release?
|
| 13 |
+
- which DTM to use? from PULP or ibex-demo-system?
|
| 14 |
+
|
| 15 |
+
## Issue Comments
|
| 16 |
+
None visible.
|
| 17 |
+
|
| 18 |
+
## Issue Metadata
|
| 19 |
+
- Status: Closed (via PR #92)
|
| 20 |
+
- Opened by: MaistoV on March 11, 2025
|
| 21 |
+
- Assignees: Granp4sso, MaistoV
|
| 22 |
+
|
| 23 |
+
## Linked Issues / PRs
|
| 24 |
+
- PR #92 — appears to be the resolution implementation
|
issues/IEEE-UCF_Gaming-CPU-Project_pr42
ADDED
|
@@ -0,0 +1,22 @@
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| 1 |
+
# Subsystem: Design RAM Handler
|
| 2 |
+
|
| 3 |
+
- Source URL: https://github.com/IEEE-UCF/Gaming-CPU-Project/issues/27
|
| 4 |
+
|
| 5 |
+
**Purpose:** Orchestrate Double Data Rate (DDR) interactions between RAM and CPU system, including booting from ROM and connecting to AXI
|
| 6 |
+
|
| 7 |
+
**Main File(s)**
|
| 8 |
+
|
| 9 |
+
- [SRAM Dualport](https://github.com/IEEE-UCF/Gaming-CPU-Project/blob/main/rtl/mem/sram_dualport.sv)
|
| 10 |
+
- [Boot ROM](https://github.com/IEEE-UCF/Gaming-CPU-Project/blob/main/rtl/mem/bootrom.sv)
|
| 11 |
+
- [DMA](https://github.com/IEEE-UCF/Gaming-CPU-Project/blob/main/rtl/subsys/dma_subsys.sv)
|
| 12 |
+
|
| 13 |
+
**Sub-Files**
|
| 14 |
+
- [MIG AXI Wrapper](https://github.com/IEEE-UCF/Gaming-CPU-Project/blob/main/rtl/mem/ddr/mig_axi_wrap.sv)
|
| 15 |
+
- [MIG Calibration Status](https://github.com/IEEE-UCF/Gaming-CPU-Project/blob/main/rtl/mem/ddr/calib_status_sync.sv)
|
| 16 |
+
|
| 17 |
+
**Related Sub-Issues (Dependencies)**
|
| 18 |
+
Bus: #6
|
| 19 |
+
Input-Output: #26
|
| 20 |
+
|
| 21 |
+
**Co-Lead**
|
| 22 |
+
Evan Eichholz
|
issues/KestrelComputer_polaris_pr21
ADDED
|
@@ -0,0 +1,21 @@
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| 1 |
+
Datasheet assumes the user knows how to instantiate the processor in Verilog. And they probably do. However, in the interests of professionalism, I'd like to see an example Verilog application of the processor included in the data sheet showing how it's typically used.
|
| 2 |
+
|
| 3 |
+
|
| 4 |
+
Simple RAM memory; 4KB ought to be way more than enough for our needs (512 x 64b).
|
| 5 |
+
|
| 6 |
+
Simple ROM memory; 4KB ought to be plenty (1024 x 32b)
|
| 7 |
+
|
| 8 |
+
Simple console I/O port.
|
| 9 |
+
|
| 10 |
+
Character output port (prints character to screen)
|
| 11 |
+
|
| 12 |
+
Bit that exits the simulation.
|
| 13 |
+
|
| 14 |
+
Custom CSR registers to demo the C-port?
|
| 15 |
+
|
| 16 |
+
Simple address decoder.
|
| 17 |
+
|
| 18 |
+
A simple hello-world type application that prints to the screen and exits the simulation.
|
| 19 |
+
|
| 20 |
+
Memory bus bridge
|
| 21 |
+
|
issues/KestrelComputer_polaris_pr22
ADDED
|
@@ -0,0 +1,32 @@
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| 1 |
+
# Support SLT/SLTU instructions
|
| 2 |
+
|
| 3 |
+
- Source URL: https://github.com/KestrelComputer/polaris/pull/22
|
| 4 |
+
|
| 5 |
+
The SLT and SLTU instructions are decoded. However, the driver signals are never propagated to the ALU. Moreover, I don't think the ALU itself has SLT/SLTU functionality baked into it just yet.
|
| 6 |
+
|
| 7 |
+
Write bench tests to check for this condition.
|
| 8 |
+
|
| 9 |
+
Confirm malignant behavior with bench tests.
|
| 10 |
+
|
| 11 |
+
Propagate ltu_en from sequencer to ALU.
|
| 12 |
+
|
| 13 |
+
Propagate lts_en from sequencer to ALU.
|
| 14 |
+
|
| 15 |
+
Implement magnitude comparison logic in ALU. Probably borrow/re-use same logic as BLT and BLTU instructions.
|
| 16 |
+
|
| 17 |
+
## Fetched Issue/PR Details
|
| 18 |
+
|
| 19 |
+
Title: Support SLT/SLTU instructions.
|
| 20 |
+
|
| 21 |
+
Description: The pull request restores previously missing SLT/SLTU instructions. According to the contributor: "These instructions were previously missing. They're back!"
|
| 22 |
+
|
| 23 |
+
Status: Merged
|
| 24 |
+
Author: sam-falvo
|
| 25 |
+
Merge Date: November 26, 2016
|
| 26 |
+
Repository: KestrelComputer/polaris
|
| 27 |
+
Branch: master
|
| 28 |
+
|
| 29 |
+
Comments:
|
| 30 |
+
- sam-falvo (Nov 26, 2016): Indicated that this PR resolves issue #18 in the KestrelComputer/polaris repository.
|
| 31 |
+
|
| 32 |
+
Linked Issues: Closes issue #18 (the original local description above appears to capture the body of that referenced issue: missing propagation of SLT/SLTU driver signals into the ALU and missing magnitude-comparison logic in the ALU).
|
issues/Lampro-Mellon_LM-RISCV-DV_pr81
ADDED
|
@@ -0,0 +1,20 @@
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| 1 |
+
# Enable Verilator in the RTL Simulation Flow for SweRV integration
|
| 2 |
+
|
| 3 |
+
- Source URL: https://github.com/Lampro-Mellon/LM-RISCV-DV/issues/69
|
| 4 |
+
|
| 5 |
+
|
| 6 |
+
## Fetched Issue/PR Details
|
| 7 |
+
|
| 8 |
+
Title: Enable Verilator in the RTL Simulation Flow for SweRV integration (#69)
|
| 9 |
+
|
| 10 |
+
Description: No description was provided in the original issue.
|
| 11 |
+
|
| 12 |
+
Status: Closed (resolved via PR #81)
|
| 13 |
+
Assignee: amnafayyaz28
|
| 14 |
+
Label: enhancement
|
| 15 |
+
Reporter: haroon-shafique
|
| 16 |
+
Opened: January 7, 2021
|
| 17 |
+
|
| 18 |
+
Comments: No comments, reactions, or additional context were visible on the page.
|
| 19 |
+
|
| 20 |
+
Linked Issues: Resolving PR #81. The issue requests integration of Verilator (an open-source RTL simulator) into the RTL simulation workflow for SweRV core integration within the LM-RISCV-DV project.
|
issues/MPSU_APS_pr98
ADDED
|
@@ -0,0 +1,51 @@
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| 1 |
+
# 6 лабораторная
|
| 2 |
+
|
| 3 |
+
- Source URL: https://github.com/MPSU/APS/issues/94
|
| 4 |
+
|
| 5 |
+
Не указано, что для работы симуляции память должна называться "ram", иначе выдаст ошибку.
|
| 6 |
+
|
| 7 |
+
---
|
| 8 |
+
|
| 9 |
+
## Pull Request
|
| 10 |
+
|
| 11 |
+
**PR Title:** WIP: APS cumulative update
|
| 12 |
+
|
| 13 |
+
**PR Number:** #98
|
| 14 |
+
|
| 15 |
+
**Status:** Merged on September 2, 2024
|
| 16 |
+
|
| 17 |
+
**Author:** HepoH3
|
| 18 |
+
|
| 19 |
+
### Description
|
| 20 |
+
|
| 21 |
+
No description provided by the author.
|
| 22 |
+
|
| 23 |
+
### Commits (16 total)
|
| 24 |
+
|
| 25 |
+
The pull request contains 16 commits including:
|
| 26 |
+
- Updates to FPGA documentation
|
| 27 |
+
- Reorganization of sequential logic content into separate documentation
|
| 28 |
+
- Image corrections and formatting fixes
|
| 29 |
+
- Vivado Basics section refactoring
|
| 30 |
+
- Project creation guide updates with images
|
| 31 |
+
- Link corrections across multiple sections (RTL analysis, bug hunting)
|
| 32 |
+
- FPGA firmware guide refactoring
|
| 33 |
+
- Mass updates and figure restorations
|
| 34 |
+
|
| 35 |
+
### Linked Issue
|
| 36 |
+
|
| 37 |
+
**Issue #94:** "6 лабораторная" (6th Laboratory)
|
| 38 |
+
|
| 39 |
+
### Activity
|
| 40 |
+
|
| 41 |
+
- Initial commit: August 23, 2024
|
| 42 |
+
- Marked ready for review: September 2, 2024
|
| 43 |
+
- Merged: September 2, 2024
|
| 44 |
+
- Branch deleted: September 2, 2024 (cumulative_update branch)
|
| 45 |
+
|
| 46 |
+
### Additional Details
|
| 47 |
+
|
| 48 |
+
- Reviewers: None recorded
|
| 49 |
+
- Assignees: None
|
| 50 |
+
- Labels: None
|
| 51 |
+
- Milestone: None
|
issues/MiSTer-devel_Arcade-Robotron_MiSTer_pr25
ADDED
|
@@ -0,0 +1,24 @@
|
|
|
|
|
|
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|
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|
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|
|
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# Core is outputting at 296 x 243...
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- Source URL: https://github.com/MiSTer-devel/Arcade-Robotron_MiSTer/issues/24
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...instead of 292 x 240 and as such doesn't seem to want to scale to 720p.
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## Fetched Issue/PR Details
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Title: Core is outputting at 296 x 243... (#24)
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Description: The core outputs a resolution of 296 x 243 pixels instead of the expected 292 x 240, which prevents proper scaling to 720p.
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Repository: MiSTer-devel/Arcade-Robotron_MiSTer
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Author: dazzer69
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Opened: September 27, 2021
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Status: Closed (linked to PR #25)
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Additional Details:
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- No assignees or labels
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- No open branches or pull requests associated
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Comments: No comments visible.
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Linked Issues: Resolving PR #25.
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issues/MiSTer-devel_C64_MiSTer_pr142
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# Arctic Shipwreck crashes on start
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- Source URL: https://github.com/MiSTer-devel/C64_MiSTer/issues/107
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TOSEC — Commodore C64 - Games - [D64]: Arctic Shipwreck (1983)(Commodore).d64
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crc=684e5568 md5=aa9d3ed98bf0fe0b459626a1ff02bad1 sha1=a2139a5df6d949a4c402b726bd9f8bf11007a222
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This game crashes on start, attempting to render its 3D ice floe. It also fails to play the music melody on title screen. Core settings set to PAL machine with standard KERNAL.
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For comparison, the same disk file works properly in VICE emulator.
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## Fetched Issue/PR Details
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Title: Arctic Shipwreck crashes on start (#107)
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Description: The user reports that the game Arctic Shipwreck (1983) for Commodore 64 crashes when attempting to render its 3D ice floe at startup. Additionally, the title screen music fails to play. The core is configured for PAL machine with standard KERNAL. The same disk file functions properly in VICE emulator, indicating an emulation-specific compatibility issue rather than a corrupted ROM.
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Game Details:
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- Source: TOSEC - Commodore C64 - Games - [D64]
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- File: Arctic Shipwreck (1983)(Commodore).d64
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- Checksums: CRC=684e5568, MD5=aa9d3ed98bf0fe0b459626a1ff02bad1, SHA1=a2139a5df6d949a4c402b726bd9f8bf11007a222
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Status: Closed via pull request #142.
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Comments: No comments were present on the page.
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Linked Issues: Resolving PR #142.
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issues/MiSTer-devel_Gameboy_MiSTer_pr216
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# Perfect Dark (GBC) - No PCM Sound
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- Source URL: https://github.com/MiSTer-devel/Gameboy_MiSTer/issues/87
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In the GBC game Perfect Dark the PCM sound (which plays a relatively big part in this game) does not work.
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Steps to reproduce: press start a few times once the game boots in order to select a new game and have the game automatically create a name for your save file. After the name entry screen, an intro dialog screen will appear. This dialog should be fully voiced via PCM samples, but instead there's silence. Same goes for all the gunshots, footsteps, and various grunts/yells the characters make throughout the game.
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Example video with the PCM samples in the intro playing correctly; relevant section starts at about 54sec: https://youtu.be/xeLNNsVPSCA?t=54
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## Fetched Issue/PR Details
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Title: Perfect Dark (GBC) - No PCM Sound (#87)
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Repository: MiSTer-devel/Gameboy_MiSTer
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Description: The reporter identified that PCM sound functionality is non-functional in the Game Boy Color version of Perfect Dark. They noted: "the PCM sound (which plays a relatively big part in this game) does not work."
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Steps to Reproduce: Start the game, press start multiple times to initiate a new save file with auto-generated naming, then proceed through the name entry screen to reach an intro dialog sequence that should feature voice acting via PCM samples.
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Affected Audio Elements:
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- Intro dialog voice acting
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- Gunshot sound effects
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- Footstep sounds
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- Character vocalizations (grunts/yells)
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Reference Material: A YouTube link demonstrates the PCM samples functioning correctly, with the relevant audio sequence beginning around the 54-second mark.
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Status: Closed (resolved via PR #216)
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Label: bug
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Opened: June 24, 2020
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Linked Issues: Resolving PR #216.
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issues/MiSTer-devel_Gameboy_MiSTer_pr24
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# SRAM management
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- Source URL: https://github.com/MiSTer-devel/Gameboy_MiSTer/issues/13
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Is it possible to import/export SRAM data?
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## Fetched Issue/PR Details
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Title: SRAM management (#13)
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Description: "Is it possible to import/export SRAM data?"
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Author: catskull
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Date Opened: December 1, 2018
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Status: Closed
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Related pull request: #24 (closed)
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Comments: No comments visible on the page.
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Linked Issues: Resolving PR #24. The issue raises a question about whether the Gameboy_MiSTer project supports functionality for importing and exporting SRAM (Static RAM) data, which typically stores game save files.
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