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snapshots/alexforencich_verilog-pcie_pr20/example/AU250/fpga/README.md

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+# Verilog PCIe Alveo U250 Example Design
+
+## Introduction
+
+This example design targets the Xilinx Alveo U250 FPGA board.
+
+The design implements the PCIe AXI lite master module, the PCIe AXI master module, and the PCIe DMA module.  A very simple Linux driver is included to test the FPGA design.
+
+*  FPGA: xcu250-figd2104-2-e
+
+## How to build
+
+Run `make` to build.  Ensure that the Xilinx Vivado components are in PATH.
+
+Run `make` to build the driver.  Ensure the headers for the running kernel are installed, otherwise the driver cannot be compiled.
+
+## How to test
+
+Run `make program` to program the Alveo U250 board with Vivado.  Then load the driver with `insmod example.ko`.  Check dmesg for the output.

snapshots/alexforencich_verilog-pcie_pr20/example/AU250/fpga/common/vivado.mk

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+###################################################################
+# 
+# Xilinx Vivado FPGA Makefile
+# 
+# Copyright (c) 2016 Alex Forencich
+# 
+###################################################################
+# 
+# Parameters:
+# FPGA_TOP - Top module name
+# FPGA_FAMILY - FPGA family (e.g. VirtexUltrascale)
+# FPGA_DEVICE - FPGA device (e.g. xcvu095-ffva2104-2-e)
+# SYN_FILES - space-separated list of source files
+# INC_FILES - space-separated list of include files
+# XDC_FILES - space-separated list of timing constraint files
+# XCI_FILES - space-separated list of IP XCI files
+# 
+# Example:
+# 
+# FPGA_TOP = fpga
+# FPGA_FAMILY = VirtexUltrascale
+# FPGA_DEVICE = xcvu095-ffva2104-2-e
+# SYN_FILES = rtl/fpga.v
+# XDC_FILES = fpga.xdc
+# XCI_FILES = ip/pcspma.xci
+# include ../common/vivado.mk
+# 
+###################################################################
+
+# phony targets
+.PHONY: fpga vivado tmpclean clean distclean
+
+# prevent make from deleting intermediate files and reports
+.PRECIOUS: %.xpr %.bit %.mcs %.prm
+.SECONDARY:
+
+CONFIG ?= config.mk
+-include ../$(CONFIG)
+
+SYN_FILES_REL = $(patsubst %, ../%, $(filter-out /% ./%,$(SYN_FILES))) $(filter /% ./%,$(SYN_FILES))
+INC_FILES_REL = $(patsubst %, ../%, $(filter-out /% ./%,$(INC_FILES))) $(filter /% ./%,$(INC_FILES))
+XCI_FILES_REL = $(patsubst %, ../%, $(filter-out /% ./%,$(XCI_FILES))) $(filter /% ./%,$(XCI_FILES))
+IP_TCL_FILES_REL = $(patsubst %, ../%, $(filter-out /% ./%,$(IP_TCL_FILES))) $(filter /% ./%,$(IP_TCL_FILES))
+CONFIG_TCL_FILES_REL = $(patsubst %, ../%, $(filter-out /% ./%,$(CONFIG_TCL_FILES))) $(filter /% ./%,$(CONFIG_TCL_FILES))
+
+ifdef XDC_FILES
+  XDC_FILES_REL = $(patsubst %, ../%, $(filter-out /% ./%,$(XDC_FILES))) $(filter /% ./%,$(XDC_FILES))
+else
+  XDC_FILES_REL = $(FPGA_TOP).xdc
+endif
+
+###################################################################
+# Main Targets
+#
+# all: build everything
+# clean: remove output files and project files
+###################################################################
+
+all: fpga
+
+fpga: $(FPGA_TOP).bit
+
+vivado: $(FPGA_TOP).xpr
+	vivado $(FPGA_TOP).xpr
+
+tmpclean::
+	-rm -rf *.log *.jou *.cache *.gen *.hbs *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v
+	-rm -rf create_project.tcl update_config.tcl run_synth.tcl run_impl.tcl generate_bit.tcl
+
+clean:: tmpclean
+	-rm -rf *.bit program.tcl generate_mcs.tcl *.mcs *.prm flash.tcl
+
+distclean:: clean
+	-rm -rf rev
+
+###################################################################
+# Target implementations
+###################################################################
+
+# Vivado project file
+create_project.tcl: Makefile $(XCI_FILES_REL) $(IP_TCL_FILES_REL)
+	rm -rf defines.v
+	touch defines.v
+	for x in $(DEFS); do echo '`define' $$x >> defines.v; done
+	echo "create_project -force -part $(FPGA_PART) $(FPGA_TOP)" > $@
+	echo "add_files -fileset sources_1 defines.v $(SYN_FILES_REL)" >> $@
+	echo "add_files -fileset constrs_1 $(XDC_FILES_REL)" >> $@
+	for x in $(XCI_FILES_REL); do echo "import_ip $$x" >> $@; done
+	for x in $(IP_TCL_FILES_REL); do echo "source $$x" >> $@; done
+	for x in $(CONFIG_TCL_FILES_REL); do echo "source $$x" >> $@; done
+
+update_config.tcl: $(CONFIG_TCL_FILES_REL)
+	echo "open_project -quiet $(FPGA_TOP).xpr" > $@
+	for x in $(CONFIG_TCL_FILES_REL); do echo "source $$x" >> $@; done
+
+$(FPGA_TOP).xpr: create_project.tcl update_config.tcl
+	vivado -nojournal -nolog -mode batch $(foreach x,$?,-source $x)
+
+# synthesis run
+%.runs/synth_1/%.dcp: %.xpr $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL) $(CONFIG_TCL_FILES_REL)
+	echo "open_project $*.xpr" > run_synth.tcl
+	echo "reset_run synth_1" >> run_synth.tcl
+	echo "launch_runs -jobs 4 synth_1" >> run_synth.tcl
+	echo "wait_on_run synth_1" >> run_synth.tcl
+	vivado -nojournal -nolog -mode batch -source run_synth.tcl
+
+# implementation run
+%.runs/impl_1/%_routed.dcp: %.runs/synth_1/%.dcp
+	echo "open_project $*.xpr" > run_impl.tcl
+	echo "reset_run impl_1" >> run_impl.tcl
+	echo "launch_runs -jobs 4 impl_1" >> run_impl.tcl
+	echo "wait_on_run impl_1" >> run_impl.tcl
+	vivado -nojournal -nolog -mode batch -source run_impl.tcl
+
+# bit file
+%.bit: %.runs/impl_1/%_routed.dcp
+	echo "open_project $*.xpr" > generate_bit.tcl
+	echo "open_run impl_1" >> generate_bit.tcl
+	echo "write_bitstream -force $*.bit" >> generate_bit.tcl
+	vivado -nojournal -nolog -mode batch -source generate_bit.tcl
+	mkdir -p rev
+	EXT=bit; COUNT=100; \
+	while [ -e rev/$*_rev$$COUNT.$$EXT ]; \
+	do COUNT=$$((COUNT+1)); done; \
+	cp $@ rev/$*_rev$$COUNT.$$EXT; \
+	echo "Output: rev/$*_rev$$COUNT.$$EXT";

snapshots/alexforencich_verilog-pcie_pr20/example/AU250/fpga/fpga.xdc

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+# XDC constraints for the Xilinx Alveo U250 board
+# part: xcu250-figd2104-2-e
+
+# General configuration
+set_property CFGBVS GND                                [current_design]
+set_property CONFIG_VOLTAGE 1.8                        [current_design]
+set_property BITSTREAM.GENERAL.COMPRESS true           [current_design]
+set_property BITSTREAM.CONFIG.CONFIGFALLBACK ENABLE    [current_design]
+set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN DISABLE [current_design]
+set_property BITSTREAM.CONFIG.CONFIGRATE 63.8          [current_design]
+set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES       [current_design]
+set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4           [current_design]
+set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES        [current_design]
+set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP         [current_design]
+
+set_operating_conditions -design_power_budget 160
+
+# System clocks
+# 300 MHz (DDR 0)
+#set_property -dict {LOC AY37 IOSTANDARD LVDS} [get_ports clk_300mhz_0_p]
+#set_property -dict {LOC AY38 IOSTANDARD LVDS} [get_ports clk_300mhz_0_n]
+#create_clock -period 3.333 -name clk_300mhz_0 [get_ports clk_300mhz_0_p]
+
+# 300 MHz (DDR 1)
+#set_property -dict {LOC AW20 IOSTANDARD LVDS} [get_ports clk_300mhz_1_p]
+#set_property -dict {LOC AW19 IOSTANDARD LVDS} [get_ports clk_300mhz_1_n]
+#create_clock -period 3.333 -name clk_300mhz_1 [get_ports clk_300mhz_1_p]
+
+# 300 MHz (DDR 2)
+#set_property -dict {LOC F32  IOSTANDARD LVDS} [get_ports clk_300mhz_2_p]
+#set_property -dict {LOC E32  IOSTANDARD LVDS} [get_ports clk_300mhz_2_n]
+#create_clock -period 3.333 -name clk_300mhz_2 [get_ports clk_300mhz_2_p]
+
+# 300 MHz (DDR 3)
+#set_property -dict {LOC J16  IOSTANDARD LVDS} [get_ports clk_300mhz_3_p]
+#set_property -dict {LOC H16  IOSTANDARD LVDS} [get_ports clk_300mhz_3_n]
+#create_clock -period 3.333 -name clk_300mhz_3 [get_ports clk_300mhz_3_p]
+
+# SI570 user clock
+#set_property -dict {LOC AU19 IOSTANDARD LVDS} [get_ports clk_user_p]
+#set_property -dict {LOC AV19 IOSTANDARD LVDS} [get_ports clk_user_n]
+#create_clock -period 6.400 -name clk_user [get_ports clk_user_p]
+
+# LEDs
+set_property -dict {LOC BC21 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[0]}]
+set_property -dict {LOC BB21 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[1]}]
+set_property -dict {LOC BA20 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[2]}]
+
+set_false_path -to [get_ports {led[*]}]
+set_output_delay 0 [get_ports {led[*]}]
+
+# Reset button
+#set_property -dict {LOC AL20 IOSTANDARD LVCMOS12} [get_ports reset]
+
+#set_false_path -from [get_ports {reset}]
+#set_input_delay 0 [get_ports {reset}]
+
+# DIP switches
+set_property -dict {LOC AN22 IOSTANDARD LVCMOS12} [get_ports {sw[0]}]
+set_property -dict {LOC AM19 IOSTANDARD LVCMOS12} [get_ports {sw[1]}]
+set_property -dict {LOC AL19 IOSTANDARD LVCMOS12} [get_ports {sw[2]}]
+set_property -dict {LOC AP20 IOSTANDARD LVCMOS12} [get_ports {sw[3]}]
+
+set_false_path -from [get_ports {sw[*]}]
+set_input_delay 0 [get_ports {sw[*]}]
+
+# UART
+#set_property -dict {LOC BF18 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports uart_txd]
+#set_property -dict {LOC BB20 IOSTANDARD LVCMOS12} [get_ports uart_rxd]
+
+#set_false_path -to [get_ports {uart_txd}]
+#set_output_delay 0 [get_ports {uart_txd}]
+#set_false_path -from [get_ports {uart_rxd}]
+#set_input_delay 0 [get_ports {uart_rxd}]
+
+# BMC
+#set_property -dict {LOC AR20 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 4} [get_ports {msp_gpio[0]}]
+#set_property -dict {LOC AM20 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 4} [get_ports {msp_gpio[1]}]
+#set_property -dict {LOC AM21 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 4} [get_ports {msp_gpio[2]}]
+#set_property -dict {LOC AN21 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 4} [get_ports {msp_gpio[3]}]
+#set_property -dict {LOC BB19 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 4} [get_ports {msp_uart_txd}]
+#set_property -dict {LOC BA19 IOSTANDARD LVCMOS12} [get_ports {msp_uart_rxd}]
+
+#set_false_path -to [get_ports {msp_uart_txd}]
+#set_output_delay 0 [get_ports {msp_uart_txd}]
+#set_false_path -from [get_ports {msp_gpio[*] msp_uart_rxd}]
+#set_input_delay 0 [get_ports {msp_gpio[*] msp_uart_rxd}]
+
+# QSFP28 Interfaces
+#set_property -dict {LOC N4  } [get_ports qsfp0_rx1_p] ;# MGTYRXP0_231 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11
+#set_property -dict {LOC N3  } [get_ports qsfp0_rx1_n] ;# MGTYRXN0_231 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11
+#set_property -dict {LOC N9  } [get_ports qsfp0_tx1_p] ;# MGTYTXP0_231 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11
+#set_property -dict {LOC N8  } [get_ports qsfp0_tx1_n] ;# MGTYTXN0_231 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11
+#set_property -dict {LOC M2  } [get_ports qsfp0_rx2_p] ;# MGTYRXP1_231 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11
+#set_property -dict {LOC M1  } [get_ports qsfp0_rx2_n] ;# MGTYRXN1_231 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11
+#set_property -dict {LOC M7  } [get_ports qsfp0_tx2_p] ;# MGTYTXP1_231 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11
+#set_property -dict {LOC M6  } [get_ports qsfp0_tx2_n] ;# MGTYTXN1_231 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11
+#set_property -dict {LOC L4  } [get_ports qsfp0_rx3_p] ;# MGTYRXP2_231 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11
+#set_property -dict {LOC L3  } [get_ports qsfp0_rx3_n] ;# MGTYRXN2_231 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11
+#set_property -dict {LOC L9  } [get_ports qsfp0_tx3_p] ;# MGTYTXP2_231 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11
+#set_property -dict {LOC L8  } [get_ports qsfp0_tx3_n] ;# MGTYTXN2_231 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11
+#set_property -dict {LOC K2  } [get_ports qsfp0_rx4_p] ;# MGTYRXP3_231 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11
+#set_property -dict {LOC K1  } [get_ports qsfp0_rx4_n] ;# MGTYRXN3_231 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11
+#set_property -dict {LOC K7  } [get_ports qsfp0_tx4_p] ;# MGTYTXP3_231 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11
+#set_property -dict {LOC K6  } [get_ports qsfp0_tx4_n] ;# MGTYTXN3_231 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11
+#set_property -dict {LOC M11 } [get_ports qsfp0_mgt_refclk_0_p] ;# MGTREFCLK0P_231 from U14.4 via U43.13
+#set_property -dict {LOC M10 } [get_ports qsfp0_mgt_refclk_0_n] ;# MGTREFCLK0N_231 from U14.5 via U43.14
+#set_property -dict {LOC K11 } [get_ports qsfp0_mgt_refclk_1_p] ;# MGTREFCLK1P_231 from U9.18
+#set_property -dict {LOC K10 } [get_ports qsfp0_mgt_refclk_1_n] ;# MGTREFCLK1N_231 from U9.17
+#set_property -dict {LOC BE16 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports qsfp0_modsell]
+#set_property -dict {LOC BE17 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports qsfp0_resetl]
+#set_property -dict {LOC BE20 IOSTANDARD LVCMOS12 PULLUP true} [get_ports qsfp0_modprsl]
+#set_property -dict {LOC BE21 IOSTANDARD LVCMOS12 PULLUP true} [get_ports qsfp0_intl]
+#set_property -dict {LOC BD18 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports qsfp0_lpmode]
+#set_property -dict {LOC AT22 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports qsfp0_refclk_reset]
+#set_property -dict {LOC AT20 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {qsfp0_fs[0]}]
+#set_property -dict {LOC AU22 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {qsfp0_fs[1]}]
+
+# 156.25 MHz MGT reference clock (from SI570)
+#create_clock -period 6.400 -name qsfp0_mgt_refclk_0 [get_ports qsfp0_mgt_refclk_0_p]
+
+# 156.25 MHz MGT reference clock (from SI5335, FS = 0b01)
+#create_clock -period 6.400 -name qsfp0_mgt_refclk_1 [get_ports qsfp0_mgt_refclk_1_p]
+
+# 161.1328125 MHz MGT reference clock (from SI5335, FS = 0b10)
+#create_clock -period 6.206 -name qsfp0_mgt_refclk_1 [get_ports qsfp0_mgt_refclk_1_p]
+
+#set_false_path -to [get_ports {qsfp0_modsell qsfp0_resetl qsfp0_lpmode qsfp0_refclk_reset qsfp0_fs[*]}]
+#set_output_delay 0 [get_ports {qsfp0_modsell qsfp0_resetl qsfp0_lpmode qsfp0_refclk_reset qsfp0_fs[*]}]
+#set_false_path -from [get_ports {qsfp0_modprsl qsfp0_intl}]
+#set_input_delay 0 [get_ports {qsfp0_modprsl qsfp0_intl}]
+
+#set_property -dict {LOC U4  } [get_ports qsfp1_rx1_p] ;# MGTYRXP0_230 GTYE4_CHANNEL_X1Y40 / GTYE4_COMMON_X1Y10
+#set_property -dict {LOC U3  } [get_ports qsfp1_rx1_n] ;# MGTYRXN0_230 GTYE4_CHANNEL_X1Y40 / GTYE4_COMMON_X1Y10
+#set_property -dict {LOC U9  } [get_ports qsfp1_tx1_p] ;# MGTYTXP0_230 GTYE4_CHANNEL_X1Y40 / GTYE4_COMMON_X1Y10
+#set_property -dict {LOC U8  } [get_ports qsfp1_tx1_n] ;# MGTYTXN0_230 GTYE4_CHANNEL_X1Y40 / GTYE4_COMMON_X1Y10
+#set_property -dict {LOC T2  } [get_ports qsfp1_rx2_p] ;# MGTYRXP1_230 GTYE4_CHANNEL_X1Y41 / GTYE4_COMMON_X1Y10
+#set_property -dict {LOC T1  } [get_ports qsfp1_rx2_n] ;# MGTYRXN1_230 GTYE4_CHANNEL_X1Y41 / GTYE4_COMMON_X1Y10
+#set_property -dict {LOC T7  } [get_ports qsfp1_tx2_p] ;# MGTYTXP1_230 GTYE4_CHANNEL_X1Y41 / GTYE4_COMMON_X1Y10
+#set_property -dict {LOC T6  } [get_ports qsfp1_tx2_n] ;# MGTYTXN1_230 GTYE4_CHANNEL_X1Y41 / GTYE4_COMMON_X1Y10
+#set_property -dict {LOC R4  } [get_ports qsfp1_rx3_p] ;# MGTYRXP2_230 GTYE4_CHANNEL_X1Y42 / GTYE4_COMMON_X1Y10
+#set_property -dict {LOC R3  } [get_ports qsfp1_rx3_n] ;# MGTYRXN2_230 GTYE4_CHANNEL_X1Y42 / GTYE4_COMMON_X1Y10
+#set_property -dict {LOC R9  } [get_ports qsfp1_tx3_p] ;# MGTYTXP2_230 GTYE4_CHANNEL_X1Y42 / GTYE4_COMMON_X1Y10
+#set_property -dict {LOC R8  } [get_ports qsfp1_tx3_n] ;# MGTYTXN2_230 GTYE4_CHANNEL_X1Y42 / GTYE4_COMMON_X1Y10
+#set_property -dict {LOC P2  } [get_ports qsfp1_rx4_p] ;# MGTYRXP3_230 GTYE4_CHANNEL_X1Y43 / GTYE4_COMMON_X1Y10
+#set_property -dict {LOC P1  } [get_ports qsfp1_rx4_n] ;# MGTYRXN3_230 GTYE4_CHANNEL_X1Y43 / GTYE4_COMMON_X1Y10
+#set_property -dict {LOC P7  } [get_ports qsfp1_tx4_p] ;# MGTYTXP3_230 GTYE4_CHANNEL_X1Y43 / GTYE4_COMMON_X1Y10
+#set_property -dict {LOC P6  } [get_ports qsfp1_tx4_n] ;# MGTYTXN3_230 GTYE4_CHANNEL_X1Y43 / GTYE4_COMMON_X1Y10
+#set_property -dict {LOC T11 } [get_ports qsfp1_mgt_refclk_0_p] ;# MGTREFCLK0P_230 from U14.4 via U43.15
+#set_property -dict {LOC T10 } [get_ports qsfp1_mgt_refclk_0_n] ;# MGTREFCLK0N_230 from U14.5 via U43.16
+#set_property -dict {LOC P11 } [get_ports qsfp1_mgt_refclk_1_p] ;# MGTREFCLK1P_230 from U12.18
+#set_property -dict {LOC P10 } [get_ports qsfp1_mgt_refclk_1_n] ;# MGTREFCLK1N_230 from U12.17
+#set_property -dict {LOC AY20 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports qsfp1_modsell]
+#set_property -dict {LOC BC18 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports qsfp1_resetl]
+#set_property -dict {LOC BC19 IOSTANDARD LVCMOS12 PULLUP true} [get_ports qsfp1_modprsl]
+#set_property -dict {LOC AV21 IOSTANDARD LVCMOS12 PULLUP true} [get_ports qsfp1_intl]
+#set_property -dict {LOC AV22 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports qsfp1_lpmode]
+#set_property -dict {LOC AR21 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports qsfp1_refclk_reset]
+#set_property -dict {LOC AR22 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {qsfp1_fs[0]}]
+#set_property -dict {LOC AU20 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {qsfp1_fs[1]}]
+
+# 156.25 MHz MGT reference clock (from SI570)
+#create_clock -period 6.400 -name qsfp1_mgt_refclk_0 [get_ports qsfp1_mgt_refclk_0_p]
+
+# 156.25 MHz MGT reference clock (from SI5335, FS = 0b01)
+#create_clock -period 6.400 -name qsfp1_mgt_refclk_1 [get_ports qsfp1_mgt_refclk_1_p]
+
+# 161.1328125 MHz MGT reference clock (from SI5335, FS = 0b10)
+#create_clock -period 6.206 -name qsfp1_mgt_refclk_1 [get_ports qsfp1_mgt_refclk_1_p]
+
+#set_false_path -to [get_ports {qsfp1_modsell qsfp1_resetl qsfp1_lpmode qsfp1_refclk_reset qsfp1_fs[*]}]
+#set_output_delay 0 [get_ports {qsfp1_modsell qsfp1_resetl qsfp1_lpmode qsfp1_refclk_reset qsfp1_fs[*]}]
+#set_false_path -from [get_ports {qsfp1_modprsl qsfp1_intl}]
+#set_input_delay 0 [get_ports {qsfp1_modprsl qsfp1_intl}]
+
+# I2C interface
+#set_property -dict {LOC BF19 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports i2c_mux_reset]
+#set_property -dict {LOC BF20 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports i2c_scl]
+#set_property -dict {LOC BF17 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports i2c_sda]
+
+#set_false_path -to [get_ports {i2c_sda i2c_scl}]
+#set_output_delay 0 [get_ports {i2c_sda i2c_scl}]
+#set_false_path -from [get_ports {i2c_sda i2c_scl}]
+#set_input_delay 0 [get_ports {i2c_sda i2c_scl}]
+
+# PCIe Interface
+set_property -dict {LOC AF2  } [get_ports {pcie_rx_p[0]}]  ;# MGTYRXP3_227 GTYE4_CHANNEL_X1Y31 / GTYE4_COMMON_X1Y7
+set_property -dict {LOC AF1  } [get_ports {pcie_rx_n[0]}]  ;# MGTYRXN3_227 GTYE4_CHANNEL_X1Y31 / GTYE4_COMMON_X1Y7
+set_property -dict {LOC AF7  } [get_ports {pcie_tx_p[0]}]  ;# MGTYTXP3_227 GTYE4_CHANNEL_X1Y31 / GTYE4_COMMON_X1Y7
+set_property -dict {LOC AF6  } [get_ports {pcie_tx_n[0]}]  ;# MGTYTXN3_227 GTYE4_CHANNEL_X1Y31 / GTYE4_COMMON_X1Y7
+set_property -dict {LOC AG4  } [get_ports {pcie_rx_p[1]}]  ;# MGTYRXP2_227 GTYE4_CHANNEL_X1Y30 / GTYE4_COMMON_X1Y7
+set_property -dict {LOC AG3  } [get_ports {pcie_rx_n[1]}]  ;# MGTYRXN2_227 GTYE4_CHANNEL_X1Y30 / GTYE4_COMMON_X1Y7
+set_property -dict {LOC AG9  } [get_ports {pcie_tx_p[1]}]  ;# MGTYTXP2_227 GTYE4_CHANNEL_X1Y30 / GTYE4_COMMON_X1Y7
+set_property -dict {LOC AG8  } [get_ports {pcie_tx_n[1]}]  ;# MGTYTXN2_227 GTYE4_CHANNEL_X1Y30 / GTYE4_COMMON_X1Y7
+set_property -dict {LOC AH2  } [get_ports {pcie_rx_p[2]}]  ;# MGTYRXP1_227 GTYE4_CHANNEL_X1Y29 / GTYE4_COMMON_X1Y7
+set_property -dict {LOC AH1  } [get_ports {pcie_rx_n[2]}]  ;# MGTYRXN1_227 GTYE4_CHANNEL_X1Y29 / GTYE4_COMMON_X1Y7
+set_property -dict {LOC AH7  } [get_ports {pcie_tx_p[2]}]  ;# MGTYTXP1_227 GTYE4_CHANNEL_X1Y29 / GTYE4_COMMON_X1Y7
+set_property -dict {LOC AH6  } [get_ports {pcie_tx_n[2]}]  ;# MGTYTXN1_227 GTYE4_CHANNEL_X1Y29 / GTYE4_COMMON_X1Y7
+set_property -dict {LOC AJ4  } [get_ports {pcie_rx_p[3]}]  ;# MGTYRXP0_227 GTYE4_CHANNEL_X1Y28 / GTYE4_COMMON_X1Y7
+set_property -dict {LOC AJ3  } [get_ports {pcie_rx_n[3]}]  ;# MGTYRXN0_227 GTYE4_CHANNEL_X1Y28 / GTYE4_COMMON_X1Y7
+set_property -dict {LOC AJ9  } [get_ports {pcie_tx_p[3]}]  ;# MGTYTXP0_227 GTYE4_CHANNEL_X1Y28 / GTYE4_COMMON_X1Y7
+set_property -dict {LOC AJ8  } [get_ports {pcie_tx_n[3]}]  ;# MGTYTXN0_227 GTYE4_CHANNEL_X1Y28 / GTYE4_COMMON_X1Y7
+set_property -dict {LOC AK2  } [get_ports {pcie_rx_p[4]}]  ;# MGTYRXP3_226 GTYE4_CHANNEL_X1Y27 / GTYE4_COMMON_X1Y6
+set_property -dict {LOC AK1  } [get_ports {pcie_rx_n[4]}]  ;# MGTYRXN3_226 GTYE4_CHANNEL_X1Y27 / GTYE4_COMMON_X1Y6
+set_property -dict {LOC AK7  } [get_ports {pcie_tx_p[4]}]  ;# MGTYTXP3_226 GTYE4_CHANNEL_X1Y27 / GTYE4_COMMON_X1Y6
+set_property -dict {LOC AK6  } [get_ports {pcie_tx_n[4]}]  ;# MGTYTXN3_226 GTYE4_CHANNEL_X1Y27 / GTYE4_COMMON_X1Y6
+set_property -dict {LOC AL4  } [get_ports {pcie_rx_p[5]}]  ;# MGTYRXP2_226 GTYE4_CHANNEL_X1Y26 / GTYE4_COMMON_X1Y6
+set_property -dict {LOC AL3  } [get_ports {pcie_rx_n[5]}]  ;# MGTYRXN2_226 GTYE4_CHANNEL_X1Y26 / GTYE4_COMMON_X1Y6
+set_property -dict {LOC AL9  } [get_ports {pcie_tx_p[5]}]  ;# MGTYTXP2_226 GTYE4_CHANNEL_X1Y26 / GTYE4_COMMON_X1Y6
+set_property -dict {LOC AL8  } [get_ports {pcie_tx_n[5]}]  ;# MGTYTXN2_226 GTYE4_CHANNEL_X1Y26 / GTYE4_COMMON_X1Y6
+set_property -dict {LOC AM2  } [get_ports {pcie_rx_p[6]}]  ;# MGTYRXP1_226 GTYE4_CHANNEL_X1Y25 / GTYE4_COMMON_X1Y6
+set_property -dict {LOC AM1  } [get_ports {pcie_rx_n[6]}]  ;# MGTYRXN1_226 GTYE4_CHANNEL_X1Y25 / GTYE4_COMMON_X1Y6
+set_property -dict {LOC AM7  } [get_ports {pcie_tx_p[6]}]  ;# MGTYTXP1_226 GTYE4_CHANNEL_X1Y25 / GTYE4_COMMON_X1Y6
+set_property -dict {LOC AM6  } [get_ports {pcie_tx_n[6]}]  ;# MGTYTXN1_226 GTYE4_CHANNEL_X1Y25 / GTYE4_COMMON_X1Y6
+set_property -dict {LOC AN4  } [get_ports {pcie_rx_p[7]}]  ;# MGTYRXP0_226 GTYE4_CHANNEL_X1Y24 / GTYE4_COMMON_X1Y6
+set_property -dict {LOC AN3  } [get_ports {pcie_rx_n[7]}]  ;# MGTYRXN0_226 GTYE4_CHANNEL_X1Y24 / GTYE4_COMMON_X1Y6
+set_property -dict {LOC AN9  } [get_ports {pcie_tx_p[7]}]  ;# MGTYTXP0_226 GTYE4_CHANNEL_X1Y24 / GTYE4_COMMON_X1Y6
+set_property -dict {LOC AN8  } [get_ports {pcie_tx_n[7]}]  ;# MGTYTXN0_226 GTYE4_CHANNEL_X1Y24 / GTYE4_COMMON_X1Y6
+set_property -dict {LOC AP2  } [get_ports {pcie_rx_p[8]}]  ;# MGTYRXP3_225 GTYE4_CHANNEL_X1Y23 / GTYE4_COMMON_X1Y5
+set_property -dict {LOC AP1  } [get_ports {pcie_rx_n[8]}]  ;# MGTYRXN3_225 GTYE4_CHANNEL_X1Y23 / GTYE4_COMMON_X1Y5
+set_property -dict {LOC AP7  } [get_ports {pcie_tx_p[8]}]  ;# MGTYTXP3_225 GTYE4_CHANNEL_X1Y23 / GTYE4_COMMON_X1Y5
+set_property -dict {LOC AP6  } [get_ports {pcie_tx_n[8]}]  ;# MGTYTXN3_225 GTYE4_CHANNEL_X1Y23 / GTYE4_COMMON_X1Y5
+set_property -dict {LOC AR4  } [get_ports {pcie_rx_p[9]}]  ;# MGTYRXP2_225 GTYE4_CHANNEL_X1Y22 / GTYE4_COMMON_X1Y5
+set_property -dict {LOC AR3  } [get_ports {pcie_rx_n[9]}]  ;# MGTYRXN2_225 GTYE4_CHANNEL_X1Y22 / GTYE4_COMMON_X1Y5
+set_property -dict {LOC AR9  } [get_ports {pcie_tx_p[9]}]  ;# MGTYTXP2_225 GTYE4_CHANNEL_X1Y22 / GTYE4_COMMON_X1Y5
+set_property -dict {LOC AR8  } [get_ports {pcie_tx_n[9]}]  ;# MGTYTXN2_225 GTYE4_CHANNEL_X1Y22 / GTYE4_COMMON_X1Y5
+set_property -dict {LOC AT2  } [get_ports {pcie_rx_p[10]}] ;# MGTYRXP1_225 GTYE4_CHANNEL_X1Y21 / GTYE4_COMMON_X1Y5
+set_property -dict {LOC AT1  } [get_ports {pcie_rx_n[10]}] ;# MGTYRXN1_225 GTYE4_CHANNEL_X1Y21 / GTYE4_COMMON_X1Y5
+set_property -dict {LOC AT7  } [get_ports {pcie_tx_p[10]}] ;# MGTYTXP1_225 GTYE4_CHANNEL_X1Y21 / GTYE4_COMMON_X1Y5
+set_property -dict {LOC AT6  } [get_ports {pcie_tx_n[10]}] ;# MGTYTXN1_225 GTYE4_CHANNEL_X1Y21 / GTYE4_COMMON_X1Y5
+set_property -dict {LOC AU4  } [get_ports {pcie_rx_p[11]}] ;# MGTYRXP0_225 GTYE4_CHANNEL_X1Y20 / GTYE4_COMMON_X1Y5
+set_property -dict {LOC AU3  } [get_ports {pcie_rx_n[11]}] ;# MGTYRXN0_225 GTYE4_CHANNEL_X1Y20 / GTYE4_COMMON_X1Y5
+set_property -dict {LOC AU9  } [get_ports {pcie_tx_p[11]}] ;# MGTYTXP0_225 GTYE4_CHANNEL_X1Y20 / GTYE4_COMMON_X1Y5
+set_property -dict {LOC AU8  } [get_ports {pcie_tx_n[11]}] ;# MGTYTXN0_225 GTYE4_CHANNEL_X1Y20 / GTYE4_COMMON_X1Y5
+set_property -dict {LOC AV2  } [get_ports {pcie_rx_p[12]}] ;# MGTYRXP3_224 GTYE4_CHANNEL_X1Y19 / GTYE4_COMMON_X1Y4
+set_property -dict {LOC AV1  } [get_ports {pcie_rx_n[12]}] ;# MGTYRXN3_224 GTYE4_CHANNEL_X1Y19 / GTYE4_COMMON_X1Y4
+set_property -dict {LOC AV7  } [get_ports {pcie_tx_p[12]}] ;# MGTYTXP3_224 GTYE4_CHANNEL_X1Y19 / GTYE4_COMMON_X1Y4
+set_property -dict {LOC AV6  } [get_ports {pcie_tx_n[12]}] ;# MGTYTXN3_224 GTYE4_CHANNEL_X1Y19 / GTYE4_COMMON_X1Y4
+set_property -dict {LOC AW4  } [get_ports {pcie_rx_p[13]}] ;# MGTYRXP2_224 GTYE4_CHANNEL_X1Y18 / GTYE4_COMMON_X1Y4
+set_property -dict {LOC AW3  } [get_ports {pcie_rx_n[13]}] ;# MGTYRXN2_224 GTYE4_CHANNEL_X1Y18 / GTYE4_COMMON_X1Y4
+set_property -dict {LOC BB5  } [get_ports {pcie_tx_p[13]}] ;# MGTYTXP2_224 GTYE4_CHANNEL_X1Y18 / GTYE4_COMMON_X1Y4
+set_property -dict {LOC BB4  } [get_ports {pcie_tx_n[13]}] ;# MGTYTXN2_224 GTYE4_CHANNEL_X1Y18 / GTYE4_COMMON_X1Y4
+set_property -dict {LOC BA2  } [get_ports {pcie_rx_p[14]}] ;# MGTYRXP1_224 GTYE4_CHANNEL_X1Y17 / GTYE4_COMMON_X1Y4
+set_property -dict {LOC BA1  } [get_ports {pcie_rx_n[14]}] ;# MGTYRXN1_224 GTYE4_CHANNEL_X1Y17 / GTYE4_COMMON_X1Y4
+set_property -dict {LOC BD5  } [get_ports {pcie_tx_p[14]}] ;# MGTYTXP1_224 GTYE4_CHANNEL_X1Y17 / GTYE4_COMMON_X1Y4
+set_property -dict {LOC BD4  } [get_ports {pcie_tx_n[14]}] ;# MGTYTXN1_224 GTYE4_CHANNEL_X1Y17 / GTYE4_COMMON_X1Y4
+set_property -dict {LOC BC2  } [get_ports {pcie_rx_p[15]}] ;# MGTYRXP0_224 GTYE4_CHANNEL_X1Y16 / GTYE4_COMMON_X1Y4
+set_property -dict {LOC BC1  } [get_ports {pcie_rx_n[15]}] ;# MGTYRXN0_224 GTYE4_CHANNEL_X1Y16 / GTYE4_COMMON_X1Y4
+set_property -dict {LOC BF5  } [get_ports {pcie_tx_p[15]}] ;# MGTYTXP0_224 GTYE4_CHANNEL_X1Y16 / GTYE4_COMMON_X1Y4
+set_property -dict {LOC BF4  } [get_ports {pcie_tx_n[15]}] ;# MGTYTXN0_224 GTYE4_CHANNEL_X1Y16 / GTYE4_COMMON_X1Y4
+set_property -dict {LOC AM11 } [get_ports pcie_refclk_p] ;# MGTREFCLK0P_226
+set_property -dict {LOC AM10 } [get_ports pcie_refclk_n] ;# MGTREFCLK0N_226
+set_property -dict {LOC BD21 IOSTANDARD LVCMOS12 PULLUP true} [get_ports pcie_reset_n]
+
+# 100 MHz MGT reference clock
+create_clock -period 10 -name pcie_mgt_refclk_1 [get_ports pcie_refclk_p]
+
+set_false_path -from [get_ports {pcie_reset_n}]
+set_input_delay 0 [get_ports {pcie_reset_n}]

snapshots/alexforencich_verilog-pcie_pr20/example/AU250/fpga/fpga/Makefile

@@ -0,0 +1,94 @@
+
+# FPGA settings
+FPGA_PART = xcu250-figd2104-2-e
+FPGA_TOP = fpga
+FPGA_ARCH = virtexuplus
+
+# Files for synthesis
+SYN_FILES = rtl/fpga.v
+SYN_FILES += rtl/fpga_core.v
+SYN_FILES += rtl/debounce_switch.v
+SYN_FILES += rtl/sync_reset.v
+SYN_FILES += rtl/sync_signal.v
+SYN_FILES += rtl/common/example_core_pcie_us.v
+SYN_FILES += rtl/common/example_core_pcie.v
+SYN_FILES += rtl/common/example_core.v
+SYN_FILES += rtl/common/axi_ram.v
+SYN_FILES += lib/pcie/rtl/pcie_us_if.v
+SYN_FILES += lib/pcie/rtl/pcie_us_if_rc.v
+SYN_FILES += lib/pcie/rtl/pcie_us_if_rq.v
+SYN_FILES += lib/pcie/rtl/pcie_us_if_cq.v
+SYN_FILES += lib/pcie/rtl/pcie_us_if_cc.v
+SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v
+SYN_FILES += lib/pcie/rtl/pcie_us_msi.v
+SYN_FILES += lib/pcie/rtl/pcie_axil_master.v
+SYN_FILES += lib/pcie/rtl/pcie_axi_master.v
+SYN_FILES += lib/pcie/rtl/pcie_axi_master_rd.v
+SYN_FILES += lib/pcie/rtl/pcie_axi_master_wr.v
+SYN_FILES += lib/pcie/rtl/pcie_tlp_demux_bar.v
+SYN_FILES += lib/pcie/rtl/pcie_tlp_demux.v
+SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v
+SYN_FILES += lib/pcie/rtl/dma_if_pcie.v
+SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v
+SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v
+SYN_FILES += lib/pcie/rtl/dma_psdpram.v
+SYN_FILES += lib/pcie/rtl/arbiter.v
+SYN_FILES += lib/pcie/rtl/priority_encoder.v
+SYN_FILES += lib/pcie/rtl/pulse_merge.v
+
+# XDC files
+XDC_FILES = fpga.xdc
+
+# IP
+IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl
+
+include ../common/vivado.mk
+
+program: $(FPGA_TOP).bit
+	echo "open_hw" > program.tcl
+	echo "connect_hw_server" >> program.tcl
+	echo "open_hw_target" >> program.tcl
+	echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
+	echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
+	echo "set_property PROGRAM.FILE {$(FPGA_TOP).bit} [current_hw_device]" >> program.tcl
+	echo "program_hw_devices [current_hw_device]" >> program.tcl
+	echo "exit" >> program.tcl
+	vivado -nojournal -nolog -mode batch -source program.tcl
+
+%.mcs %.prm: %.bit
+	echo "write_cfgmem -force -format mcs -size 128 -interface SPIx4 -loadbit {up 0x01002000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl
+	echo "exit" >> generate_mcs.tcl
+	vivado -nojournal -nolog -mode batch -source generate_mcs.tcl
+	mkdir -p rev
+	COUNT=100; \
+	while [ -e rev/$*_rev$$COUNT.bit ]; \
+	do COUNT=$$((COUNT+1)); done; \
+	COUNT=$$((COUNT-1)); \
+	for x in .mcs .prm; \
+	do cp $*$$x rev/$*_rev$$COUNT$$x; \
+	echo "Output: rev/$*_rev$$COUNT$$x"; done;
+
+flash: $(FPGA_TOP).mcs $(FPGA_TOP).prm
+	echo "open_hw" > flash.tcl
+	echo "connect_hw_server" >> flash.tcl
+	echo "open_hw_target" >> flash.tcl
+	echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash.tcl
+	echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash.tcl
+	echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {mt25qu01g-spi-x1_x2_x4}] 0]" >> flash.tcl
+	echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash.tcl
+	echo "set_property PROGRAM.FILES [list \"$(FPGA_TOP).mcs\"] [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.PRM_FILES [list \"$(FPGA_TOP).prm\"] [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash.tcl
+	echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash.tcl
+	echo "program_hw_devices [current_hw_device]" >> flash.tcl
+	echo "refresh_hw_device [current_hw_device]" >> flash.tcl
+	echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash.tcl
+	echo "boot_hw_device [current_hw_device]" >> flash.tcl
+	echo "exit" >> flash.tcl
+	vivado -nojournal -nolog -mode batch -source flash.tcl
+

snapshots/alexforencich_verilog-pcie_pr20/example/AU250/fpga/ip/pcie4_uscale_plus_0.tcl

@@ -0,0 +1,28 @@
+
+create_ip -name pcie4_uscale_plus -vendor xilinx.com -library ip -module_name pcie4_uscale_plus_0
+
+set_property -dict [list \
+    CONFIG.PL_LINK_CAP_MAX_LINK_SPEED {8.0_GT/s} \
+    CONFIG.PL_LINK_CAP_MAX_LINK_WIDTH {X16} \
+    CONFIG.AXISTEN_IF_EXT_512_RQ_STRADDLE {false} \
+    CONFIG.axisten_if_enable_client_tag {true} \
+    CONFIG.axisten_if_width {512_bit} \
+    CONFIG.axisten_freq {250} \
+    CONFIG.PF0_CLASS_CODE {058000} \
+    CONFIG.PF0_DEVICE_ID {0001} \
+    CONFIG.PF0_MSI_CAP_MULTIMSGCAP {32_vectors} \
+    CONFIG.PF0_SUBSYSTEM_ID {90fa} \
+    CONFIG.PF0_SUBSYSTEM_VENDOR_ID {10ee} \
+    CONFIG.pf0_bar0_64bit {true} \
+    CONFIG.pf0_bar0_prefetchable {true} \
+    CONFIG.pf0_bar0_scale {Megabytes} \
+    CONFIG.pf0_bar0_size {16} \
+    CONFIG.pf0_bar2_64bit {true} \
+    CONFIG.pf0_bar2_prefetchable {true} \
+    CONFIG.pf0_bar2_enabled {true} \
+    CONFIG.pf0_bar2_type {Memory} \
+    CONFIG.pf0_bar2_scale {Megabytes} \
+    CONFIG.pf0_bar2_size {16} \
+    CONFIG.vendor_id {1234} \
+    CONFIG.en_msi_per_vec_masking {true} \
+] [get_ips pcie4_uscale_plus_0]

snapshots/alexforencich_verilog-pcie_pr20/example/AU250/fpga/rtl/debounce_switch.v

@@ -0,0 +1,93 @@
+/*
+
+Copyright (c) 2014-2018 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog-2001
+
+`resetall
+`timescale 1 ns / 1 ps
+`default_nettype none
+
+/*
+ * Synchronizes switch and button inputs with a slow sampled shift register
+ */
+module debounce_switch  #(
+    parameter WIDTH=1, // width of the input and output signals
+    parameter N=3, // length of shift register
+    parameter RATE=125000 // clock division factor
+)(
+    input wire clk,
+    input wire rst,
+    input wire [WIDTH-1:0] in,
+    output wire [WIDTH-1:0] out
+);
+
+reg [23:0] cnt_reg = 24'd0;
+
+reg [N-1:0] debounce_reg[WIDTH-1:0];
+
+reg [WIDTH-1:0] state;
+
+/*
+ * The synchronized output is the state register
+ */
+assign out = state;
+
+integer k;
+
+always @(posedge clk or posedge rst) begin
+    if (rst) begin
+        cnt_reg <= 0;
+        state <= 0;
+        
+        for (k = 0; k < WIDTH; k = k + 1) begin
+            debounce_reg[k] <= 0;
+        end
+    end else begin
+        if (cnt_reg < RATE) begin
+            cnt_reg <= cnt_reg + 24'd1;
+        end else begin
+            cnt_reg <= 24'd0;
+        end
+        
+        if (cnt_reg == 24'd0) begin
+            for (k = 0; k < WIDTH; k = k + 1) begin
+                debounce_reg[k] <= {debounce_reg[k][N-2:0], in[k]};
+            end
+        end
+        
+        for (k = 0; k < WIDTH; k = k + 1) begin
+            if (|debounce_reg[k] == 0) begin
+                state[k] <= 0;
+            end else if (&debounce_reg[k] == 1) begin
+                state[k] <= 1;
+            end else begin
+                state[k] <= state[k];
+            end
+        end
+    end
+end
+
+endmodule
+
+`resetall

snapshots/alexforencich_verilog-pcie_pr20/example/AU250/fpga/rtl/fpga.v

@@ -0,0 +1,463 @@
+/*
+
+Copyright (c) 2018 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog 2001
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * FPGA top-level module
+ */
+module fpga (
+    /*
+     * GPIO
+     */
+    input  wire [3:0]  sw,
+    output wire [2:0]  led,
+
+    /*
+     * PCI express
+     */
+    input  wire [15:0] pcie_rx_p,
+    input  wire [15:0] pcie_rx_n,
+    output wire [15:0] pcie_tx_p,
+    output wire [15:0] pcie_tx_n,
+    input  wire        pcie_refclk_p,
+    input  wire        pcie_refclk_n,
+    input  wire        pcie_reset_n
+);
+
+parameter AXIS_PCIE_DATA_WIDTH = 512;
+parameter AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32);
+parameter AXIS_PCIE_RC_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 75 : 161;
+parameter AXIS_PCIE_RQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 60 : 137;
+parameter AXIS_PCIE_CQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 85 : 183;
+parameter AXIS_PCIE_CC_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 33 : 81;
+
+parameter RQ_SEQ_NUM_WIDTH = AXIS_PCIE_RQ_USER_WIDTH == 60 ? 4 : 6;
+parameter RQ_SEQ_NUM_ENABLE = 1;
+
+parameter PCIE_TAG_COUNT = 64;
+parameter BAR0_APERTURE = 24;
+parameter BAR2_APERTURE = 24;
+
+// Clock and reset
+wire pcie_user_clk;
+wire pcie_user_reset;
+
+// GPIO
+wire [3:0] sw_int;
+
+debounce_switch #(
+    .WIDTH(4),
+    .N(4),
+    .RATE(250000)
+)
+debounce_switch_inst (
+    .clk(pcie_user_clk),
+    .rst(pcie_user_reset),
+    .in({sw}),
+    .out({sw_int})
+);
+
+// PCIe
+wire pcie_sys_clk;
+wire pcie_sys_clk_gt;
+
+IBUFDS_GTE4 #(
+    .REFCLK_HROW_CK_SEL(2'b00)
+)
+ibufds_gte4_pcie_mgt_refclk_inst (
+    .I             (pcie_refclk_p),
+    .IB            (pcie_refclk_n),
+    .CEB           (1'b0),
+    .O             (pcie_sys_clk_gt),
+    .ODIV2         (pcie_sys_clk)
+);
+
+wire [AXIS_PCIE_DATA_WIDTH-1:0]    axis_rq_tdata;
+wire [AXIS_PCIE_KEEP_WIDTH-1:0]    axis_rq_tkeep;
+wire                               axis_rq_tlast;
+wire                               axis_rq_tready;
+wire [AXIS_PCIE_RQ_USER_WIDTH-1:0] axis_rq_tuser;
+wire                               axis_rq_tvalid;
+
+wire [AXIS_PCIE_DATA_WIDTH-1:0]    axis_rc_tdata;
+wire [AXIS_PCIE_KEEP_WIDTH-1:0]    axis_rc_tkeep;
+wire                               axis_rc_tlast;
+wire                               axis_rc_tready;
+wire [AXIS_PCIE_RC_USER_WIDTH-1:0] axis_rc_tuser;
+wire                               axis_rc_tvalid;
+
+wire [AXIS_PCIE_DATA_WIDTH-1:0]    axis_cq_tdata;
+wire [AXIS_PCIE_KEEP_WIDTH-1:0]    axis_cq_tkeep;
+wire                               axis_cq_tlast;
+wire                               axis_cq_tready;
+wire [AXIS_PCIE_CQ_USER_WIDTH-1:0] axis_cq_tuser;
+wire                               axis_cq_tvalid;
+
+wire [AXIS_PCIE_DATA_WIDTH-1:0]    axis_cc_tdata;
+wire [AXIS_PCIE_KEEP_WIDTH-1:0]    axis_cc_tkeep;
+wire                               axis_cc_tlast;
+wire                               axis_cc_tready;
+wire [AXIS_PCIE_CC_USER_WIDTH-1:0] axis_cc_tuser;
+wire                               axis_cc_tvalid;
+
+wire [RQ_SEQ_NUM_WIDTH-1:0]        pcie_rq_seq_num0;
+wire                               pcie_rq_seq_num_vld0;
+wire [RQ_SEQ_NUM_WIDTH-1:0]        pcie_rq_seq_num1;
+wire                               pcie_rq_seq_num_vld1;
+
+// ila_0 rq_ila (
+//     .clk(pcie_user_clk),
+//     .probe0(axis_rq_tdata),
+//     .probe1(axis_rq_tkeep),
+//     .probe2(axis_rq_tlast),
+//     .probe3(axis_rq_tready),
+//     .probe4(axis_rq_tuser),
+//     .probe5(axis_rq_tvalid)
+// );
+
+// ila_0 rc_ila (
+//     .clk(pcie_user_clk),
+//     .probe0(axis_rc_tdata),
+//     .probe1(axis_rc_tkeep),
+//     .probe2(axis_rc_tlast),
+//     .probe3(axis_rc_tready),
+//     .probe4(axis_rc_tuser),
+//     .probe5(axis_rc_tvalid)
+// );
+
+wire [2:0] cfg_max_payload;
+wire [2:0] cfg_max_read_req;
+
+wire [9:0]  cfg_mgmt_addr;
+wire [7:0]  cfg_mgmt_function_number;
+wire        cfg_mgmt_write;
+wire [31:0] cfg_mgmt_write_data;
+wire [3:0]  cfg_mgmt_byte_enable;
+wire        cfg_mgmt_read;
+wire [31:0] cfg_mgmt_read_data;
+wire        cfg_mgmt_read_write_done;
+
+wire [7:0]  cfg_fc_ph;
+wire [11:0] cfg_fc_pd;
+wire [7:0]  cfg_fc_nph;
+wire [11:0] cfg_fc_npd;
+wire [7:0]  cfg_fc_cplh;
+wire [11:0] cfg_fc_cpld;
+wire [2:0]  cfg_fc_sel;
+
+wire [3:0]  cfg_interrupt_msi_enable;
+wire [11:0] cfg_interrupt_msi_mmenable;
+wire        cfg_interrupt_msi_mask_update;
+wire [31:0] cfg_interrupt_msi_data;
+wire [3:0]  cfg_interrupt_msi_select;
+wire [31:0] cfg_interrupt_msi_int;
+wire [31:0] cfg_interrupt_msi_pending_status;
+wire        cfg_interrupt_msi_pending_status_data_enable;
+wire [3:0]  cfg_interrupt_msi_pending_status_function_num;
+wire        cfg_interrupt_msi_sent;
+wire        cfg_interrupt_msi_fail;
+wire [2:0]  cfg_interrupt_msi_attr;
+wire        cfg_interrupt_msi_tph_present;
+wire [1:0]  cfg_interrupt_msi_tph_type;
+wire [8:0]  cfg_interrupt_msi_tph_st_tag;
+wire [3:0]  cfg_interrupt_msi_function_number;
+
+wire status_error_cor;
+wire status_error_uncor;
+
+pcie4_uscale_plus_0
+pcie4_uscale_plus_inst (
+    .pci_exp_txn(pcie_tx_n),
+    .pci_exp_txp(pcie_tx_p),
+    .pci_exp_rxn(pcie_rx_n),
+    .pci_exp_rxp(pcie_rx_p),
+    .user_clk(pcie_user_clk),
+    .user_reset(pcie_user_reset),
+    .user_lnk_up(),
+
+    .s_axis_rq_tdata(axis_rq_tdata),
+    .s_axis_rq_tkeep(axis_rq_tkeep),
+    .s_axis_rq_tlast(axis_rq_tlast),
+    .s_axis_rq_tready(axis_rq_tready),
+    .s_axis_rq_tuser(axis_rq_tuser),
+    .s_axis_rq_tvalid(axis_rq_tvalid),
+
+    .m_axis_rc_tdata(axis_rc_tdata),
+    .m_axis_rc_tkeep(axis_rc_tkeep),
+    .m_axis_rc_tlast(axis_rc_tlast),
+    .m_axis_rc_tready(axis_rc_tready),
+    .m_axis_rc_tuser(axis_rc_tuser),
+    .m_axis_rc_tvalid(axis_rc_tvalid),
+
+    .m_axis_cq_tdata(axis_cq_tdata),
+    .m_axis_cq_tkeep(axis_cq_tkeep),
+    .m_axis_cq_tlast(axis_cq_tlast),
+    .m_axis_cq_tready(axis_cq_tready),
+    .m_axis_cq_tuser(axis_cq_tuser),
+    .m_axis_cq_tvalid(axis_cq_tvalid),
+
+    .s_axis_cc_tdata(axis_cc_tdata),
+    .s_axis_cc_tkeep(axis_cc_tkeep),
+    .s_axis_cc_tlast(axis_cc_tlast),
+    .s_axis_cc_tready(axis_cc_tready),
+    .s_axis_cc_tuser(axis_cc_tuser),
+    .s_axis_cc_tvalid(axis_cc_tvalid),
+
+    .pcie_rq_seq_num0(pcie_rq_seq_num0),
+    .pcie_rq_seq_num_vld0(pcie_rq_seq_num_vld0),
+    .pcie_rq_seq_num1(pcie_rq_seq_num1),
+    .pcie_rq_seq_num_vld1(pcie_rq_seq_num_vld1),
+    .pcie_rq_tag0(),
+    .pcie_rq_tag1(),
+    .pcie_rq_tag_av(),
+    .pcie_rq_tag_vld0(),
+    .pcie_rq_tag_vld1(),
+
+    .pcie_tfc_nph_av(),
+    .pcie_tfc_npd_av(),
+
+    .pcie_cq_np_req(1'b1),
+    .pcie_cq_np_req_count(),
+
+    .cfg_phy_link_down(),
+    .cfg_phy_link_status(),
+    .cfg_negotiated_width(),
+    .cfg_current_speed(),
+    .cfg_max_payload(cfg_max_payload),
+    .cfg_max_read_req(cfg_max_read_req),
+    .cfg_function_status(),
+    .cfg_function_power_state(),
+    .cfg_vf_status(),
+    .cfg_vf_power_state(),
+    .cfg_link_power_state(),
+
+    .cfg_mgmt_addr(cfg_mgmt_addr),
+    .cfg_mgmt_function_number(cfg_mgmt_function_number),
+    .cfg_mgmt_write(cfg_mgmt_write),
+    .cfg_mgmt_write_data(cfg_mgmt_write_data),
+    .cfg_mgmt_byte_enable(cfg_mgmt_byte_enable),
+    .cfg_mgmt_read(cfg_mgmt_read),
+    .cfg_mgmt_read_data(cfg_mgmt_read_data),
+    .cfg_mgmt_read_write_done(cfg_mgmt_read_write_done),
+    .cfg_mgmt_debug_access(1'b0),
+
+    .cfg_err_cor_out(),
+    .cfg_err_nonfatal_out(),
+    .cfg_err_fatal_out(),
+    .cfg_local_error_valid(),
+    .cfg_local_error_out(),
+    .cfg_ltssm_state(),
+    .cfg_rx_pm_state(),
+    .cfg_tx_pm_state(),
+    .cfg_rcb_status(),
+    .cfg_obff_enable(),
+    .cfg_pl_status_change(),
+    .cfg_tph_requester_enable(),
+    .cfg_tph_st_mode(),
+    .cfg_vf_tph_requester_enable(),
+    .cfg_vf_tph_st_mode(),
+
+    .cfg_msg_received(),
+    .cfg_msg_received_data(),
+    .cfg_msg_received_type(),
+    .cfg_msg_transmit(1'b0),
+    .cfg_msg_transmit_type(3'd0),
+    .cfg_msg_transmit_data(32'd0),
+    .cfg_msg_transmit_done(),
+
+    .cfg_fc_ph(cfg_fc_ph),
+    .cfg_fc_pd(cfg_fc_pd),
+    .cfg_fc_nph(cfg_fc_nph),
+    .cfg_fc_npd(cfg_fc_npd),
+    .cfg_fc_cplh(cfg_fc_cplh),
+    .cfg_fc_cpld(cfg_fc_cpld),
+    .cfg_fc_sel(cfg_fc_sel),
+
+    .cfg_dsn(64'd0),
+
+    .cfg_bus_number(),
+
+    .cfg_power_state_change_ack(1'b1),
+    .cfg_power_state_change_interrupt(),
+
+    .cfg_err_cor_in(status_error_cor),
+    .cfg_err_uncor_in(status_error_uncor),
+    .cfg_flr_in_process(),
+    .cfg_flr_done(4'd0),
+    .cfg_vf_flr_in_process(),
+    .cfg_vf_flr_func_num(8'd0),
+    .cfg_vf_flr_done(8'd0),
+
+    .cfg_link_training_enable(1'b1),
+
+    .cfg_interrupt_int(4'd0),
+    .cfg_interrupt_pending(4'd0),
+    .cfg_interrupt_sent(),
+    .cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
+    .cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
+    .cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
+    .cfg_interrupt_msi_data(cfg_interrupt_msi_data),
+    .cfg_interrupt_msi_select(cfg_interrupt_msi_select),
+    .cfg_interrupt_msi_int(cfg_interrupt_msi_int),
+    .cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
+    .cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
+    .cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
+    .cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
+    .cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
+    .cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
+    .cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
+    .cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
+    .cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
+    .cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
+
+    .cfg_pm_aspm_l1_entry_reject(1'b0),
+    .cfg_pm_aspm_tx_l0s_entry_disable(1'b0),
+
+    .cfg_hot_reset_out(),
+
+    .cfg_config_space_enable(1'b1),
+    .cfg_req_pm_transition_l23_ready(1'b0),
+    .cfg_hot_reset_in(1'b0),
+
+    .cfg_ds_port_number(8'd0),
+    .cfg_ds_bus_number(8'd0),
+    .cfg_ds_device_number(5'd0),
+
+    .sys_clk(pcie_sys_clk),
+    .sys_clk_gt(pcie_sys_clk_gt),
+    .sys_reset(pcie_reset_n),
+
+    .phy_rdy_out()
+);
+
+fpga_core #(
+    .AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
+    .AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
+    .AXIS_PCIE_RC_USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH),
+    .AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH),
+    .AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH),
+    .AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH),
+    .RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH),
+    .RQ_SEQ_NUM_ENABLE(RQ_SEQ_NUM_ENABLE),
+    .PCIE_TAG_COUNT(PCIE_TAG_COUNT),
+    .BAR0_APERTURE(BAR0_APERTURE),
+    .BAR2_APERTURE(BAR2_APERTURE)
+)
+core_inst (
+    /*
+     * Clock: 250 MHz
+     * Synchronous reset
+     */
+    .clk(pcie_user_clk),
+    .rst(pcie_user_reset),
+    /*
+     * GPIO
+     */
+    .sw(sw_int),
+    .led(led),
+    /*
+     * PCIe
+     */
+    .m_axis_rq_tdata(axis_rq_tdata),
+    .m_axis_rq_tkeep(axis_rq_tkeep),
+    .m_axis_rq_tlast(axis_rq_tlast),
+    .m_axis_rq_tready(axis_rq_tready),
+    .m_axis_rq_tuser(axis_rq_tuser),
+    .m_axis_rq_tvalid(axis_rq_tvalid),
+
+    .s_axis_rc_tdata(axis_rc_tdata),
+    .s_axis_rc_tkeep(axis_rc_tkeep),
+    .s_axis_rc_tlast(axis_rc_tlast),
+    .s_axis_rc_tready(axis_rc_tready),
+    .s_axis_rc_tuser(axis_rc_tuser),
+    .s_axis_rc_tvalid(axis_rc_tvalid),
+
+    .s_axis_cq_tdata(axis_cq_tdata),
+    .s_axis_cq_tkeep(axis_cq_tkeep),
+    .s_axis_cq_tlast(axis_cq_tlast),
+    .s_axis_cq_tready(axis_cq_tready),
+    .s_axis_cq_tuser(axis_cq_tuser),
+    .s_axis_cq_tvalid(axis_cq_tvalid),
+
+    .m_axis_cc_tdata(axis_cc_tdata),
+    .m_axis_cc_tkeep(axis_cc_tkeep),
+    .m_axis_cc_tlast(axis_cc_tlast),
+    .m_axis_cc_tready(axis_cc_tready),
+    .m_axis_cc_tuser(axis_cc_tuser),
+    .m_axis_cc_tvalid(axis_cc_tvalid),
+
+    .s_axis_rq_seq_num_0(pcie_rq_seq_num0),
+    .s_axis_rq_seq_num_valid_0(pcie_rq_seq_num_vld0),
+    .s_axis_rq_seq_num_1(pcie_rq_seq_num1),
+    .s_axis_rq_seq_num_valid_1(pcie_rq_seq_num_vld1),
+
+    .cfg_max_payload(cfg_max_payload),
+    .cfg_max_read_req(cfg_max_read_req),
+    
+    .cfg_mgmt_addr(cfg_mgmt_addr),
+    .cfg_mgmt_function_number(cfg_mgmt_function_number),
+    .cfg_mgmt_write(cfg_mgmt_write),
+    .cfg_mgmt_write_data(cfg_mgmt_write_data),
+    .cfg_mgmt_byte_enable(cfg_mgmt_byte_enable),
+    .cfg_mgmt_read(cfg_mgmt_read),
+    .cfg_mgmt_read_data(cfg_mgmt_read_data),
+    .cfg_mgmt_read_write_done(cfg_mgmt_read_write_done),
+
+    .cfg_fc_ph(cfg_fc_ph),
+    .cfg_fc_pd(cfg_fc_pd),
+    .cfg_fc_nph(cfg_fc_nph),
+    .cfg_fc_npd(cfg_fc_npd),
+    .cfg_fc_cplh(cfg_fc_cplh),
+    .cfg_fc_cpld(cfg_fc_cpld),
+    .cfg_fc_sel(cfg_fc_sel),
+
+    .cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
+    .cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
+    .cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
+    .cfg_interrupt_msi_data(cfg_interrupt_msi_data),
+    .cfg_interrupt_msi_select(cfg_interrupt_msi_select),
+    .cfg_interrupt_msi_int(cfg_interrupt_msi_int),
+    .cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
+    .cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
+    .cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
+    .cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
+    .cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
+    .cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
+    .cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
+    .cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
+    .cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
+    .cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
+
+    .status_error_cor(status_error_cor),
+    .status_error_uncor(status_error_uncor)
+);
+
+endmodule
+
+`resetall

snapshots/alexforencich_verilog-pcie_pr20/example/AU250/fpga/rtl/fpga_core.v

@@ -0,0 +1,271 @@
+/*
+
+Copyright (c) 2018 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog 2001
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * FPGA core logic
+ */
+module fpga_core #
+(
+    parameter AXIS_PCIE_DATA_WIDTH = 512,
+    parameter AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32),
+    parameter AXIS_PCIE_RC_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 75 : 161,
+    parameter AXIS_PCIE_RQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 60 : 137,
+    parameter AXIS_PCIE_CQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 85 : 183,
+    parameter AXIS_PCIE_CC_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 33 : 81,
+    parameter RQ_SEQ_NUM_WIDTH = AXIS_PCIE_RQ_USER_WIDTH == 60 ? 4 : 6,
+    parameter RQ_SEQ_NUM_ENABLE = 1,
+    parameter PCIE_TAG_COUNT = 64,
+    parameter BAR0_APERTURE = 24,
+    parameter BAR2_APERTURE = 24
+)
+(
+    /*
+     * Clock: 250 MHz
+     * Synchronous reset
+     */
+    input  wire                               clk,
+    input  wire                               rst,
+
+    /*
+     * GPIO
+     */
+    input  wire [3:0]                         sw,
+    output wire [2:0]                         led,
+
+    /*
+     * PCIe
+     */
+    output wire [AXIS_PCIE_DATA_WIDTH-1:0]    m_axis_rq_tdata,
+    output wire [AXIS_PCIE_KEEP_WIDTH-1:0]    m_axis_rq_tkeep,
+    output wire                               m_axis_rq_tlast,
+    input  wire                               m_axis_rq_tready,
+    output wire [AXIS_PCIE_RQ_USER_WIDTH-1:0] m_axis_rq_tuser,
+    output wire                               m_axis_rq_tvalid,
+
+    input  wire [AXIS_PCIE_DATA_WIDTH-1:0]    s_axis_rc_tdata,
+    input  wire [AXIS_PCIE_KEEP_WIDTH-1:0]    s_axis_rc_tkeep,
+    input  wire                               s_axis_rc_tlast,
+    output wire                               s_axis_rc_tready,
+    input  wire [AXIS_PCIE_RC_USER_WIDTH-1:0] s_axis_rc_tuser,
+    input  wire                               s_axis_rc_tvalid,
+
+    input  wire [AXIS_PCIE_DATA_WIDTH-1:0]    s_axis_cq_tdata,
+    input  wire [AXIS_PCIE_KEEP_WIDTH-1:0]    s_axis_cq_tkeep,
+    input  wire                               s_axis_cq_tlast,
+    output wire                               s_axis_cq_tready,
+    input  wire [AXIS_PCIE_CQ_USER_WIDTH-1:0] s_axis_cq_tuser,
+    input  wire                               s_axis_cq_tvalid,
+
+    output wire [AXIS_PCIE_DATA_WIDTH-1:0]    m_axis_cc_tdata,
+    output wire [AXIS_PCIE_KEEP_WIDTH-1:0]    m_axis_cc_tkeep,
+    output wire                               m_axis_cc_tlast,
+    input  wire                               m_axis_cc_tready,
+    output wire [AXIS_PCIE_CC_USER_WIDTH-1:0] m_axis_cc_tuser,
+    output wire                               m_axis_cc_tvalid,
+
+    input  wire [RQ_SEQ_NUM_WIDTH-1:0]        s_axis_rq_seq_num_0,
+    input  wire                               s_axis_rq_seq_num_valid_0,
+    input  wire [RQ_SEQ_NUM_WIDTH-1:0]        s_axis_rq_seq_num_1,
+    input  wire                               s_axis_rq_seq_num_valid_1,
+
+    input  wire [2:0]                         cfg_max_payload,
+    input  wire [2:0]                         cfg_max_read_req,
+
+    output wire [9:0]                         cfg_mgmt_addr,
+    output wire [7:0]                         cfg_mgmt_function_number,
+    output wire                               cfg_mgmt_write,
+    output wire [31:0]                        cfg_mgmt_write_data,
+    output wire [3:0]                         cfg_mgmt_byte_enable,
+    output wire                               cfg_mgmt_read,
+    input  wire [31:0]                        cfg_mgmt_read_data,
+    input  wire                               cfg_mgmt_read_write_done,
+
+    input  wire [7:0]                         cfg_fc_ph,
+    input  wire [11:0]                        cfg_fc_pd,
+    input  wire [7:0]                         cfg_fc_nph,
+    input  wire [11:0]                        cfg_fc_npd,
+    input  wire [7:0]                         cfg_fc_cplh,
+    input  wire [11:0]                        cfg_fc_cpld,
+    output wire [2:0]                         cfg_fc_sel,
+
+    input  wire [3:0]                         cfg_interrupt_msi_enable,
+    input  wire [11:0]                        cfg_interrupt_msi_mmenable,
+    input  wire                               cfg_interrupt_msi_mask_update,
+    input  wire [31:0]                        cfg_interrupt_msi_data,
+    output wire [3:0]                         cfg_interrupt_msi_select,
+    output wire [31:0]                        cfg_interrupt_msi_int,
+    output wire [31:0]                        cfg_interrupt_msi_pending_status,
+    output wire                               cfg_interrupt_msi_pending_status_data_enable,
+    output wire [3:0]                         cfg_interrupt_msi_pending_status_function_num,
+    input  wire                               cfg_interrupt_msi_sent,
+    input  wire                               cfg_interrupt_msi_fail,
+    output wire [2:0]                         cfg_interrupt_msi_attr,
+    output wire                               cfg_interrupt_msi_tph_present,
+    output wire [1:0]                         cfg_interrupt_msi_tph_type,
+    output wire [8:0]                         cfg_interrupt_msi_tph_st_tag,
+    output wire [3:0]                         cfg_interrupt_msi_function_number,
+
+    output wire                               status_error_cor,
+    output wire                               status_error_uncor
+);
+
+assign led = 3'd0;
+
+example_core_pcie_us #(
+    .AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
+    .AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
+    .AXIS_PCIE_RC_USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH),
+    .AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH),
+    .AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH),
+    .AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH),
+    .RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH),
+    .RQ_SEQ_NUM_ENABLE(RQ_SEQ_NUM_ENABLE),
+    .PCIE_TAG_COUNT(PCIE_TAG_COUNT),
+    .READ_OP_TABLE_SIZE(PCIE_TAG_COUNT),
+    .READ_TX_LIMIT(2**(RQ_SEQ_NUM_WIDTH-1)),
+    .READ_TX_FC_ENABLE(1),
+    .WRITE_OP_TABLE_SIZE(2**(RQ_SEQ_NUM_WIDTH-1)),
+    .WRITE_TX_LIMIT(2**(RQ_SEQ_NUM_WIDTH-1)),
+    .WRITE_TX_FC_ENABLE(1),
+    .BAR0_APERTURE(BAR0_APERTURE),
+    .BAR2_APERTURE(BAR2_APERTURE)
+)
+example_core_pcie_us_inst (
+    .clk(clk),
+    .rst(rst),
+
+    /*
+     * AXI input (RC)
+     */
+    .s_axis_rc_tdata(s_axis_rc_tdata),
+    .s_axis_rc_tkeep(s_axis_rc_tkeep),
+    .s_axis_rc_tvalid(s_axis_rc_tvalid),
+    .s_axis_rc_tready(s_axis_rc_tready),
+    .s_axis_rc_tlast(s_axis_rc_tlast),
+    .s_axis_rc_tuser(s_axis_rc_tuser),
+
+    /*
+     * AXI output (RQ)
+     */
+    .m_axis_rq_tdata(m_axis_rq_tdata),
+    .m_axis_rq_tkeep(m_axis_rq_tkeep),
+    .m_axis_rq_tvalid(m_axis_rq_tvalid),
+    .m_axis_rq_tready(m_axis_rq_tready),
+    .m_axis_rq_tlast(m_axis_rq_tlast),
+    .m_axis_rq_tuser(m_axis_rq_tuser),
+
+    /*
+     * AXI input (CQ)
+     */
+    .s_axis_cq_tdata(s_axis_cq_tdata),
+    .s_axis_cq_tkeep(s_axis_cq_tkeep),
+    .s_axis_cq_tvalid(s_axis_cq_tvalid),
+    .s_axis_cq_tready(s_axis_cq_tready),
+    .s_axis_cq_tlast(s_axis_cq_tlast),
+    .s_axis_cq_tuser(s_axis_cq_tuser),
+
+    /*
+     * AXI output (CC)
+     */
+    .m_axis_cc_tdata(m_axis_cc_tdata),
+    .m_axis_cc_tkeep(m_axis_cc_tkeep),
+    .m_axis_cc_tvalid(m_axis_cc_tvalid),
+    .m_axis_cc_tready(m_axis_cc_tready),
+    .m_axis_cc_tlast(m_axis_cc_tlast),
+    .m_axis_cc_tuser(m_axis_cc_tuser),
+
+    /*
+     * Transmit sequence number input
+     */
+    .s_axis_rq_seq_num_0(s_axis_rq_seq_num_0),
+    .s_axis_rq_seq_num_valid_0(s_axis_rq_seq_num_valid_0),
+    .s_axis_rq_seq_num_1(s_axis_rq_seq_num_1),
+    .s_axis_rq_seq_num_valid_1(s_axis_rq_seq_num_valid_1),
+
+    /*
+     * Flow control
+     */
+    .cfg_fc_ph(cfg_fc_ph),
+    .cfg_fc_pd(cfg_fc_pd),
+    .cfg_fc_nph(cfg_fc_nph),
+    .cfg_fc_npd(cfg_fc_npd),
+    .cfg_fc_cplh(cfg_fc_cplh),
+    .cfg_fc_cpld(cfg_fc_cpld),
+    .cfg_fc_sel(cfg_fc_sel),
+
+    /*
+     * Configuration interface
+     */
+    .cfg_mgmt_addr(cfg_mgmt_addr),
+    .cfg_mgmt_function_number(cfg_mgmt_function_number),
+    .cfg_mgmt_write(cfg_mgmt_write),
+    .cfg_mgmt_write_data(cfg_mgmt_write_data),
+    .cfg_mgmt_byte_enable(cfg_mgmt_byte_enable),
+    .cfg_mgmt_read(cfg_mgmt_read),
+    .cfg_mgmt_read_data(cfg_mgmt_read_data),
+    .cfg_mgmt_read_write_done(cfg_mgmt_read_write_done),
+
+    /*
+     * Interrupt interface
+     */
+    .cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
+    .cfg_interrupt_msi_vf_enable(8'd0),
+    .cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
+    .cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
+    .cfg_interrupt_msi_data(cfg_interrupt_msi_data),
+    .cfg_interrupt_msi_select(cfg_interrupt_msi_select),
+    .cfg_interrupt_msi_int(cfg_interrupt_msi_int),
+    .cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
+    .cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
+    .cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
+    .cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
+    .cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
+    .cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
+    .cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
+    .cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
+    .cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
+    .cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
+
+    /*
+     * Configuration
+     */
+    .cfg_max_read_req(cfg_max_read_req),
+    .cfg_max_payload(cfg_max_payload),
+
+    /*
+     * Status
+     */
+    .status_error_cor(status_error_cor),
+    .status_error_uncor(status_error_uncor)
+);
+
+endmodule
+
+`resetall

snapshots/alexforencich_verilog-pcie_pr20/example/AU250/fpga/rtl/sync_reset.v

@@ -0,0 +1,56 @@
+/*
+
+Copyright (c) 2014-2018 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog-2001
+
+`resetall
+`timescale 1 ns / 1 ps
+`default_nettype none
+
+/*
+ * Synchronizes an active-high asynchronous reset signal to a given clock by
+ * using a pipeline of N registers.
+ */
+module sync_reset #(
+    parameter N=2 // depth of synchronizer
+)(
+    input wire clk,
+    input wire rst,
+    output wire sync_reset_out
+);
+
+reg [N-1:0] sync_reg = {N{1'b1}};
+
+assign sync_reset_out = sync_reg[N-1];
+
+always @(posedge clk or posedge rst) begin
+    if (rst)
+        sync_reg <= {N{1'b1}};
+    else
+        sync_reg <= {sync_reg[N-2:0], 1'b0};
+end
+
+endmodule
+
+`resetall

snapshots/alexforencich_verilog-pcie_pr20/example/AU250/fpga/rtl/sync_signal.v

@@ -0,0 +1,62 @@
+/*
+
+Copyright (c) 2014-2018 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog-2001
+
+`resetall
+`timescale 1 ns / 1 ps
+`default_nettype none
+
+/*
+ * Synchronizes an asyncronous signal to a given clock by using a pipeline of
+ * two registers.
+ */
+module sync_signal #(
+    parameter WIDTH=1, // width of the input and output signals
+    parameter N=2 // depth of synchronizer
+)(
+    input wire clk,
+    input wire [WIDTH-1:0] in,
+    output wire [WIDTH-1:0] out
+);
+
+reg [WIDTH-1:0] sync_reg[N-1:0];
+
+/*
+ * The synchronized output is the last register in the pipeline.
+ */
+assign out = sync_reg[N-1];
+
+integer k;
+
+always @(posedge clk) begin
+    sync_reg[0] <= in;
+    for (k = 1; k < N; k = k + 1) begin
+        sync_reg[k] <= sync_reg[k-1];
+    end
+end
+
+endmodule
+
+`resetall

snapshots/alexforencich_verilog-pcie_pr20/example/AU250/fpga_axi/Makefile

@@ -0,0 +1,25 @@
+# Targets
+TARGETS:=
+
+# Subdirectories
+SUBDIRS = fpga
+SUBDIRS_CLEAN = $(patsubst %,%.clean,$(SUBDIRS))
+
+# Rules
+.PHONY: all
+all: $(SUBDIRS) $(TARGETS)
+
+.PHONY: $(SUBDIRS)
+$(SUBDIRS):
+	cd $@ && $(MAKE)
+
+.PHONY: $(SUBDIRS_CLEAN)
+$(SUBDIRS_CLEAN):
+	cd $(@:.clean=) && $(MAKE) clean
+
+.PHONY: clean
+clean: $(SUBDIRS_CLEAN)
+	-rm -rf $(TARGETS)
+
+program:
+	#djtgcfg prog -d Atlys --index 0 --file fpga/fpga.bit

snapshots/alexforencich_verilog-pcie_pr20/example/AU250/fpga_axi/README.md

@@ -0,0 +1,26 @@
+# Verilog PCIe Alveo U250 Example Design
+
+## Introduction
+
+This example design targets the Xilinx Alveo U250 FPGA board.
+
+The design implements the PCIe AXI lite master module, the PCIe AXI master
+module, and the PCIe AXI DMA module.  A very simple Linux driver is included
+to test the FPGA design.
+
+FPGA: xcu250-figd2104-2-e
+
+## How to build
+
+Run make to build.  Ensure that the Xilinx Vivado toolchain components are
+in PATH.
+
+Run make to build the driver.  Ensure the headers for the running kernel are
+installed, otherwise the driver cannot be compiled.
+
+## How to test
+
+Run make program to program the Alveo U250 board with Vivado.  Then load the
+driver with insmod example.ko.  Check dmesg for the output.
+
+

snapshots/alexforencich_verilog-pcie_pr20/example/AU250/fpga_axi/common/vivado.mk

@@ -0,0 +1,126 @@
+###################################################################
+# 
+# Xilinx Vivado FPGA Makefile
+# 
+# Copyright (c) 2016 Alex Forencich
+# 
+###################################################################
+# 
+# Parameters:
+# FPGA_TOP - Top module name
+# FPGA_FAMILY - FPGA family (e.g. VirtexUltrascale)
+# FPGA_DEVICE - FPGA device (e.g. xcvu095-ffva2104-2-e)
+# SYN_FILES - space-separated list of source files
+# INC_FILES - space-separated list of include files
+# XDC_FILES - space-separated list of timing constraint files
+# XCI_FILES - space-separated list of IP XCI files
+# 
+# Example:
+# 
+# FPGA_TOP = fpga
+# FPGA_FAMILY = VirtexUltrascale
+# FPGA_DEVICE = xcvu095-ffva2104-2-e
+# SYN_FILES = rtl/fpga.v
+# XDC_FILES = fpga.xdc
+# XCI_FILES = ip/pcspma.xci
+# include ../common/vivado.mk
+# 
+###################################################################
+
+# phony targets
+.PHONY: fpga vivado tmpclean clean distclean
+
+# prevent make from deleting intermediate files and reports
+.PRECIOUS: %.xpr %.bit %.mcs %.prm
+.SECONDARY:
+
+CONFIG ?= config.mk
+-include ../$(CONFIG)
+
+SYN_FILES_REL = $(patsubst %, ../%, $(filter-out /% ./%,$(SYN_FILES))) $(filter /% ./%,$(SYN_FILES))
+INC_FILES_REL = $(patsubst %, ../%, $(filter-out /% ./%,$(INC_FILES))) $(filter /% ./%,$(INC_FILES))
+XCI_FILES_REL = $(patsubst %, ../%, $(filter-out /% ./%,$(XCI_FILES))) $(filter /% ./%,$(XCI_FILES))
+IP_TCL_FILES_REL = $(patsubst %, ../%, $(filter-out /% ./%,$(IP_TCL_FILES))) $(filter /% ./%,$(IP_TCL_FILES))
+CONFIG_TCL_FILES_REL = $(patsubst %, ../%, $(filter-out /% ./%,$(CONFIG_TCL_FILES))) $(filter /% ./%,$(CONFIG_TCL_FILES))
+
+ifdef XDC_FILES
+  XDC_FILES_REL = $(patsubst %, ../%, $(filter-out /% ./%,$(XDC_FILES))) $(filter /% ./%,$(XDC_FILES))
+else
+  XDC_FILES_REL = $(FPGA_TOP).xdc
+endif
+
+###################################################################
+# Main Targets
+#
+# all: build everything
+# clean: remove output files and project files
+###################################################################
+
+all: fpga
+
+fpga: $(FPGA_TOP).bit
+
+vivado: $(FPGA_TOP).xpr
+	vivado $(FPGA_TOP).xpr
+
+tmpclean::
+	-rm -rf *.log *.jou *.cache *.gen *.hbs *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v
+	-rm -rf create_project.tcl update_config.tcl run_synth.tcl run_impl.tcl generate_bit.tcl
+
+clean:: tmpclean
+	-rm -rf *.bit program.tcl generate_mcs.tcl *.mcs *.prm flash.tcl
+
+distclean:: clean
+	-rm -rf rev
+
+###################################################################
+# Target implementations
+###################################################################
+
+# Vivado project file
+create_project.tcl: Makefile $(XCI_FILES_REL) $(IP_TCL_FILES_REL)
+	rm -rf defines.v
+	touch defines.v
+	for x in $(DEFS); do echo '`define' $$x >> defines.v; done
+	echo "create_project -force -part $(FPGA_PART) $(FPGA_TOP)" > $@
+	echo "add_files -fileset sources_1 defines.v $(SYN_FILES_REL)" >> $@
+	echo "add_files -fileset constrs_1 $(XDC_FILES_REL)" >> $@
+	for x in $(XCI_FILES_REL); do echo "import_ip $$x" >> $@; done
+	for x in $(IP_TCL_FILES_REL); do echo "source $$x" >> $@; done
+	for x in $(CONFIG_TCL_FILES_REL); do echo "source $$x" >> $@; done
+
+update_config.tcl: $(CONFIG_TCL_FILES_REL)
+	echo "open_project -quiet $(FPGA_TOP).xpr" > $@
+	for x in $(CONFIG_TCL_FILES_REL); do echo "source $$x" >> $@; done
+
+$(FPGA_TOP).xpr: create_project.tcl update_config.tcl
+	vivado -nojournal -nolog -mode batch $(foreach x,$?,-source $x)
+
+# synthesis run
+%.runs/synth_1/%.dcp: %.xpr $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL) $(CONFIG_TCL_FILES_REL)
+	echo "open_project $*.xpr" > run_synth.tcl
+	echo "reset_run synth_1" >> run_synth.tcl
+	echo "launch_runs -jobs 4 synth_1" >> run_synth.tcl
+	echo "wait_on_run synth_1" >> run_synth.tcl
+	vivado -nojournal -nolog -mode batch -source run_synth.tcl
+
+# implementation run
+%.runs/impl_1/%_routed.dcp: %.runs/synth_1/%.dcp
+	echo "open_project $*.xpr" > run_impl.tcl
+	echo "reset_run impl_1" >> run_impl.tcl
+	echo "launch_runs -jobs 4 impl_1" >> run_impl.tcl
+	echo "wait_on_run impl_1" >> run_impl.tcl
+	vivado -nojournal -nolog -mode batch -source run_impl.tcl
+
+# bit file
+%.bit: %.runs/impl_1/%_routed.dcp
+	echo "open_project $*.xpr" > generate_bit.tcl
+	echo "open_run impl_1" >> generate_bit.tcl
+	echo "write_bitstream -force $*.bit" >> generate_bit.tcl
+	vivado -nojournal -nolog -mode batch -source generate_bit.tcl
+	mkdir -p rev
+	EXT=bit; COUNT=100; \
+	while [ -e rev/$*_rev$$COUNT.$$EXT ]; \
+	do COUNT=$$((COUNT+1)); done; \
+	cp $@ rev/$*_rev$$COUNT.$$EXT; \
+	echo "Output: rev/$*_rev$$COUNT.$$EXT";

snapshots/alexforencich_verilog-pcie_pr20/example/AU250/fpga_axi/fpga.xdc

@@ -0,0 +1,259 @@
+# XDC constraints for the Xilinx Alveo U250 board
+# part: xcu250-figd2104-2-e
+
+# General configuration
+set_property CFGBVS GND                                [current_design]
+set_property CONFIG_VOLTAGE 1.8                        [current_design]
+set_property BITSTREAM.GENERAL.COMPRESS true           [current_design]
+set_property BITSTREAM.CONFIG.CONFIGFALLBACK ENABLE    [current_design]
+set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN DISABLE [current_design]
+set_property BITSTREAM.CONFIG.CONFIGRATE 63.8          [current_design]
+set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES       [current_design]
+set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4           [current_design]
+set_property BITSTREAM.CONFIG.SPI_FALL_EDGE YES        [current_design]
+set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP         [current_design]
+
+set_operating_conditions -design_power_budget 160
+
+# System clocks
+# 300 MHz (DDR 0)
+#set_property -dict {LOC AY37 IOSTANDARD LVDS} [get_ports clk_300mhz_0_p]
+#set_property -dict {LOC AY38 IOSTANDARD LVDS} [get_ports clk_300mhz_0_n]
+#create_clock -period 3.333 -name clk_300mhz_0 [get_ports clk_300mhz_0_p]
+
+# 300 MHz (DDR 1)
+#set_property -dict {LOC AW20 IOSTANDARD LVDS} [get_ports clk_300mhz_1_p]
+#set_property -dict {LOC AW19 IOSTANDARD LVDS} [get_ports clk_300mhz_1_n]
+#create_clock -period 3.333 -name clk_300mhz_1 [get_ports clk_300mhz_1_p]
+
+# 300 MHz (DDR 2)
+#set_property -dict {LOC F32  IOSTANDARD LVDS} [get_ports clk_300mhz_2_p]
+#set_property -dict {LOC E32  IOSTANDARD LVDS} [get_ports clk_300mhz_2_n]
+#create_clock -period 3.333 -name clk_300mhz_2 [get_ports clk_300mhz_2_p]
+
+# 300 MHz (DDR 3)
+#set_property -dict {LOC J16  IOSTANDARD LVDS} [get_ports clk_300mhz_3_p]
+#set_property -dict {LOC H16  IOSTANDARD LVDS} [get_ports clk_300mhz_3_n]
+#create_clock -period 3.333 -name clk_300mhz_3 [get_ports clk_300mhz_3_p]
+
+# SI570 user clock
+#set_property -dict {LOC AU19 IOSTANDARD LVDS} [get_ports clk_user_p]
+#set_property -dict {LOC AV19 IOSTANDARD LVDS} [get_ports clk_user_n]
+#create_clock -period 6.400 -name clk_user [get_ports clk_user_p]
+
+# LEDs
+set_property -dict {LOC BC21 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[0]}]
+set_property -dict {LOC BB21 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[1]}]
+set_property -dict {LOC BA20 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {led[2]}]
+
+set_false_path -to [get_ports {led[*]}]
+set_output_delay 0 [get_ports {led[*]}]
+
+# Reset button
+#set_property -dict {LOC AL20 IOSTANDARD LVCMOS12} [get_ports reset]
+
+#set_false_path -from [get_ports {reset}]
+#set_input_delay 0 [get_ports {reset}]
+
+# DIP switches
+set_property -dict {LOC AN22 IOSTANDARD LVCMOS12} [get_ports {sw[0]}]
+set_property -dict {LOC AM19 IOSTANDARD LVCMOS12} [get_ports {sw[1]}]
+set_property -dict {LOC AL19 IOSTANDARD LVCMOS12} [get_ports {sw[2]}]
+set_property -dict {LOC AP20 IOSTANDARD LVCMOS12} [get_ports {sw[3]}]
+
+set_false_path -from [get_ports {sw[*]}]
+set_input_delay 0 [get_ports {sw[*]}]
+
+# UART
+#set_property -dict {LOC BF18 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports uart_txd]
+#set_property -dict {LOC BB20 IOSTANDARD LVCMOS12} [get_ports uart_rxd]
+
+#set_false_path -to [get_ports {uart_txd}]
+#set_output_delay 0 [get_ports {uart_txd}]
+#set_false_path -from [get_ports {uart_rxd}]
+#set_input_delay 0 [get_ports {uart_rxd}]
+
+# BMC
+#set_property -dict {LOC AR20 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 4} [get_ports {msp_gpio[0]}]
+#set_property -dict {LOC AM20 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 4} [get_ports {msp_gpio[1]}]
+#set_property -dict {LOC AM21 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 4} [get_ports {msp_gpio[2]}]
+#set_property -dict {LOC AN21 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 4} [get_ports {msp_gpio[3]}]
+#set_property -dict {LOC BB19 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 4} [get_ports {msp_uart_txd}]
+#set_property -dict {LOC BA19 IOSTANDARD LVCMOS12} [get_ports {msp_uart_rxd}]
+
+#set_false_path -to [get_ports {msp_uart_txd}]
+#set_output_delay 0 [get_ports {msp_uart_txd}]
+#set_false_path -from [get_ports {msp_gpio[*] msp_uart_rxd}]
+#set_input_delay 0 [get_ports {msp_gpio[*] msp_uart_rxd}]
+
+# QSFP28 Interfaces
+#set_property -dict {LOC N4  } [get_ports qsfp0_rx1_p] ;# MGTYRXP0_231 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11
+#set_property -dict {LOC N3  } [get_ports qsfp0_rx1_n] ;# MGTYRXN0_231 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11
+#set_property -dict {LOC N9  } [get_ports qsfp0_tx1_p] ;# MGTYTXP0_231 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11
+#set_property -dict {LOC N8  } [get_ports qsfp0_tx1_n] ;# MGTYTXN0_231 GTYE4_CHANNEL_X1Y44 / GTYE4_COMMON_X1Y11
+#set_property -dict {LOC M2  } [get_ports qsfp0_rx2_p] ;# MGTYRXP1_231 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11
+#set_property -dict {LOC M1  } [get_ports qsfp0_rx2_n] ;# MGTYRXN1_231 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11
+#set_property -dict {LOC M7  } [get_ports qsfp0_tx2_p] ;# MGTYTXP1_231 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11
+#set_property -dict {LOC M6  } [get_ports qsfp0_tx2_n] ;# MGTYTXN1_231 GTYE4_CHANNEL_X1Y45 / GTYE4_COMMON_X1Y11
+#set_property -dict {LOC L4  } [get_ports qsfp0_rx3_p] ;# MGTYRXP2_231 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11
+#set_property -dict {LOC L3  } [get_ports qsfp0_rx3_n] ;# MGTYRXN2_231 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11
+#set_property -dict {LOC L9  } [get_ports qsfp0_tx3_p] ;# MGTYTXP2_231 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11
+#set_property -dict {LOC L8  } [get_ports qsfp0_tx3_n] ;# MGTYTXN2_231 GTYE4_CHANNEL_X1Y46 / GTYE4_COMMON_X1Y11
+#set_property -dict {LOC K2  } [get_ports qsfp0_rx4_p] ;# MGTYRXP3_231 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11
+#set_property -dict {LOC K1  } [get_ports qsfp0_rx4_n] ;# MGTYRXN3_231 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11
+#set_property -dict {LOC K7  } [get_ports qsfp0_tx4_p] ;# MGTYTXP3_231 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11
+#set_property -dict {LOC K6  } [get_ports qsfp0_tx4_n] ;# MGTYTXN3_231 GTYE4_CHANNEL_X1Y47 / GTYE4_COMMON_X1Y11
+#set_property -dict {LOC M11 } [get_ports qsfp0_mgt_refclk_0_p] ;# MGTREFCLK0P_231 from U14.4 via U43.13
+#set_property -dict {LOC M10 } [get_ports qsfp0_mgt_refclk_0_n] ;# MGTREFCLK0N_231 from U14.5 via U43.14
+#set_property -dict {LOC K11 } [get_ports qsfp0_mgt_refclk_1_p] ;# MGTREFCLK1P_231 from U9.18
+#set_property -dict {LOC K10 } [get_ports qsfp0_mgt_refclk_1_n] ;# MGTREFCLK1N_231 from U9.17
+#set_property -dict {LOC BE16 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports qsfp0_modsell]
+#set_property -dict {LOC BE17 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports qsfp0_resetl]
+#set_property -dict {LOC BE20 IOSTANDARD LVCMOS12 PULLUP true} [get_ports qsfp0_modprsl]
+#set_property -dict {LOC BE21 IOSTANDARD LVCMOS12 PULLUP true} [get_ports qsfp0_intl]
+#set_property -dict {LOC BD18 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports qsfp0_lpmode]
+#set_property -dict {LOC AT22 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports qsfp0_refclk_reset]
+#set_property -dict {LOC AT20 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {qsfp0_fs[0]}]
+#set_property -dict {LOC AU22 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {qsfp0_fs[1]}]
+
+# 156.25 MHz MGT reference clock (from SI570)
+#create_clock -period 6.400 -name qsfp0_mgt_refclk_0 [get_ports qsfp0_mgt_refclk_0_p]
+
+# 156.25 MHz MGT reference clock (from SI5335, FS = 0b01)
+#create_clock -period 6.400 -name qsfp0_mgt_refclk_1 [get_ports qsfp0_mgt_refclk_1_p]
+
+# 161.1328125 MHz MGT reference clock (from SI5335, FS = 0b10)
+#create_clock -period 6.206 -name qsfp0_mgt_refclk_1 [get_ports qsfp0_mgt_refclk_1_p]
+
+#set_false_path -to [get_ports {qsfp0_modsell qsfp0_resetl qsfp0_lpmode qsfp0_refclk_reset qsfp0_fs[*]}]
+#set_output_delay 0 [get_ports {qsfp0_modsell qsfp0_resetl qsfp0_lpmode qsfp0_refclk_reset qsfp0_fs[*]}]
+#set_false_path -from [get_ports {qsfp0_modprsl qsfp0_intl}]
+#set_input_delay 0 [get_ports {qsfp0_modprsl qsfp0_intl}]
+
+#set_property -dict {LOC U4  } [get_ports qsfp1_rx1_p] ;# MGTYRXP0_230 GTYE4_CHANNEL_X1Y40 / GTYE4_COMMON_X1Y10
+#set_property -dict {LOC U3  } [get_ports qsfp1_rx1_n] ;# MGTYRXN0_230 GTYE4_CHANNEL_X1Y40 / GTYE4_COMMON_X1Y10
+#set_property -dict {LOC U9  } [get_ports qsfp1_tx1_p] ;# MGTYTXP0_230 GTYE4_CHANNEL_X1Y40 / GTYE4_COMMON_X1Y10
+#set_property -dict {LOC U8  } [get_ports qsfp1_tx1_n] ;# MGTYTXN0_230 GTYE4_CHANNEL_X1Y40 / GTYE4_COMMON_X1Y10
+#set_property -dict {LOC T2  } [get_ports qsfp1_rx2_p] ;# MGTYRXP1_230 GTYE4_CHANNEL_X1Y41 / GTYE4_COMMON_X1Y10
+#set_property -dict {LOC T1  } [get_ports qsfp1_rx2_n] ;# MGTYRXN1_230 GTYE4_CHANNEL_X1Y41 / GTYE4_COMMON_X1Y10
+#set_property -dict {LOC T7  } [get_ports qsfp1_tx2_p] ;# MGTYTXP1_230 GTYE4_CHANNEL_X1Y41 / GTYE4_COMMON_X1Y10
+#set_property -dict {LOC T6  } [get_ports qsfp1_tx2_n] ;# MGTYTXN1_230 GTYE4_CHANNEL_X1Y41 / GTYE4_COMMON_X1Y10
+#set_property -dict {LOC R4  } [get_ports qsfp1_rx3_p] ;# MGTYRXP2_230 GTYE4_CHANNEL_X1Y42 / GTYE4_COMMON_X1Y10
+#set_property -dict {LOC R3  } [get_ports qsfp1_rx3_n] ;# MGTYRXN2_230 GTYE4_CHANNEL_X1Y42 / GTYE4_COMMON_X1Y10
+#set_property -dict {LOC R9  } [get_ports qsfp1_tx3_p] ;# MGTYTXP2_230 GTYE4_CHANNEL_X1Y42 / GTYE4_COMMON_X1Y10
+#set_property -dict {LOC R8  } [get_ports qsfp1_tx3_n] ;# MGTYTXN2_230 GTYE4_CHANNEL_X1Y42 / GTYE4_COMMON_X1Y10
+#set_property -dict {LOC P2  } [get_ports qsfp1_rx4_p] ;# MGTYRXP3_230 GTYE4_CHANNEL_X1Y43 / GTYE4_COMMON_X1Y10
+#set_property -dict {LOC P1  } [get_ports qsfp1_rx4_n] ;# MGTYRXN3_230 GTYE4_CHANNEL_X1Y43 / GTYE4_COMMON_X1Y10
+#set_property -dict {LOC P7  } [get_ports qsfp1_tx4_p] ;# MGTYTXP3_230 GTYE4_CHANNEL_X1Y43 / GTYE4_COMMON_X1Y10
+#set_property -dict {LOC P6  } [get_ports qsfp1_tx4_n] ;# MGTYTXN3_230 GTYE4_CHANNEL_X1Y43 / GTYE4_COMMON_X1Y10
+#set_property -dict {LOC T11 } [get_ports qsfp1_mgt_refclk_0_p] ;# MGTREFCLK0P_230 from U14.4 via U43.15
+#set_property -dict {LOC T10 } [get_ports qsfp1_mgt_refclk_0_n] ;# MGTREFCLK0N_230 from U14.5 via U43.16
+#set_property -dict {LOC P11 } [get_ports qsfp1_mgt_refclk_1_p] ;# MGTREFCLK1P_230 from U12.18
+#set_property -dict {LOC P10 } [get_ports qsfp1_mgt_refclk_1_n] ;# MGTREFCLK1N_230 from U12.17
+#set_property -dict {LOC AY20 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports qsfp1_modsell]
+#set_property -dict {LOC BC18 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports qsfp1_resetl]
+#set_property -dict {LOC BC19 IOSTANDARD LVCMOS12 PULLUP true} [get_ports qsfp1_modprsl]
+#set_property -dict {LOC AV21 IOSTANDARD LVCMOS12 PULLUP true} [get_ports qsfp1_intl]
+#set_property -dict {LOC AV22 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports qsfp1_lpmode]
+#set_property -dict {LOC AR21 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports qsfp1_refclk_reset]
+#set_property -dict {LOC AR22 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {qsfp1_fs[0]}]
+#set_property -dict {LOC AU20 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports {qsfp1_fs[1]}]
+
+# 156.25 MHz MGT reference clock (from SI570)
+#create_clock -period 6.400 -name qsfp1_mgt_refclk_0 [get_ports qsfp1_mgt_refclk_0_p]
+
+# 156.25 MHz MGT reference clock (from SI5335, FS = 0b01)
+#create_clock -period 6.400 -name qsfp1_mgt_refclk_1 [get_ports qsfp1_mgt_refclk_1_p]
+
+# 161.1328125 MHz MGT reference clock (from SI5335, FS = 0b10)
+#create_clock -period 6.206 -name qsfp1_mgt_refclk_1 [get_ports qsfp1_mgt_refclk_1_p]
+
+#set_false_path -to [get_ports {qsfp1_modsell qsfp1_resetl qsfp1_lpmode qsfp1_refclk_reset qsfp1_fs[*]}]
+#set_output_delay 0 [get_ports {qsfp1_modsell qsfp1_resetl qsfp1_lpmode qsfp1_refclk_reset qsfp1_fs[*]}]
+#set_false_path -from [get_ports {qsfp1_modprsl qsfp1_intl}]
+#set_input_delay 0 [get_ports {qsfp1_modprsl qsfp1_intl}]
+
+# I2C interface
+#set_property -dict {LOC BF19 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports i2c_mux_reset]
+#set_property -dict {LOC BF20 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports i2c_scl]
+#set_property -dict {LOC BF17 IOSTANDARD LVCMOS12 SLEW SLOW DRIVE 8} [get_ports i2c_sda]
+
+#set_false_path -to [get_ports {i2c_sda i2c_scl}]
+#set_output_delay 0 [get_ports {i2c_sda i2c_scl}]
+#set_false_path -from [get_ports {i2c_sda i2c_scl}]
+#set_input_delay 0 [get_ports {i2c_sda i2c_scl}]
+
+# PCIe Interface
+set_property -dict {LOC AF2  } [get_ports {pcie_rx_p[0]}]  ;# MGTYRXP3_227 GTYE4_CHANNEL_X1Y31 / GTYE4_COMMON_X1Y7
+set_property -dict {LOC AF1  } [get_ports {pcie_rx_n[0]}]  ;# MGTYRXN3_227 GTYE4_CHANNEL_X1Y31 / GTYE4_COMMON_X1Y7
+set_property -dict {LOC AF7  } [get_ports {pcie_tx_p[0]}]  ;# MGTYTXP3_227 GTYE4_CHANNEL_X1Y31 / GTYE4_COMMON_X1Y7
+set_property -dict {LOC AF6  } [get_ports {pcie_tx_n[0]}]  ;# MGTYTXN3_227 GTYE4_CHANNEL_X1Y31 / GTYE4_COMMON_X1Y7
+set_property -dict {LOC AG4  } [get_ports {pcie_rx_p[1]}]  ;# MGTYRXP2_227 GTYE4_CHANNEL_X1Y30 / GTYE4_COMMON_X1Y7
+set_property -dict {LOC AG3  } [get_ports {pcie_rx_n[1]}]  ;# MGTYRXN2_227 GTYE4_CHANNEL_X1Y30 / GTYE4_COMMON_X1Y7
+set_property -dict {LOC AG9  } [get_ports {pcie_tx_p[1]}]  ;# MGTYTXP2_227 GTYE4_CHANNEL_X1Y30 / GTYE4_COMMON_X1Y7
+set_property -dict {LOC AG8  } [get_ports {pcie_tx_n[1]}]  ;# MGTYTXN2_227 GTYE4_CHANNEL_X1Y30 / GTYE4_COMMON_X1Y7
+set_property -dict {LOC AH2  } [get_ports {pcie_rx_p[2]}]  ;# MGTYRXP1_227 GTYE4_CHANNEL_X1Y29 / GTYE4_COMMON_X1Y7
+set_property -dict {LOC AH1  } [get_ports {pcie_rx_n[2]}]  ;# MGTYRXN1_227 GTYE4_CHANNEL_X1Y29 / GTYE4_COMMON_X1Y7
+set_property -dict {LOC AH7  } [get_ports {pcie_tx_p[2]}]  ;# MGTYTXP1_227 GTYE4_CHANNEL_X1Y29 / GTYE4_COMMON_X1Y7
+set_property -dict {LOC AH6  } [get_ports {pcie_tx_n[2]}]  ;# MGTYTXN1_227 GTYE4_CHANNEL_X1Y29 / GTYE4_COMMON_X1Y7
+set_property -dict {LOC AJ4  } [get_ports {pcie_rx_p[3]}]  ;# MGTYRXP0_227 GTYE4_CHANNEL_X1Y28 / GTYE4_COMMON_X1Y7
+set_property -dict {LOC AJ3  } [get_ports {pcie_rx_n[3]}]  ;# MGTYRXN0_227 GTYE4_CHANNEL_X1Y28 / GTYE4_COMMON_X1Y7
+set_property -dict {LOC AJ9  } [get_ports {pcie_tx_p[3]}]  ;# MGTYTXP0_227 GTYE4_CHANNEL_X1Y28 / GTYE4_COMMON_X1Y7
+set_property -dict {LOC AJ8  } [get_ports {pcie_tx_n[3]}]  ;# MGTYTXN0_227 GTYE4_CHANNEL_X1Y28 / GTYE4_COMMON_X1Y7
+set_property -dict {LOC AK2  } [get_ports {pcie_rx_p[4]}]  ;# MGTYRXP3_226 GTYE4_CHANNEL_X1Y27 / GTYE4_COMMON_X1Y6
+set_property -dict {LOC AK1  } [get_ports {pcie_rx_n[4]}]  ;# MGTYRXN3_226 GTYE4_CHANNEL_X1Y27 / GTYE4_COMMON_X1Y6
+set_property -dict {LOC AK7  } [get_ports {pcie_tx_p[4]}]  ;# MGTYTXP3_226 GTYE4_CHANNEL_X1Y27 / GTYE4_COMMON_X1Y6
+set_property -dict {LOC AK6  } [get_ports {pcie_tx_n[4]}]  ;# MGTYTXN3_226 GTYE4_CHANNEL_X1Y27 / GTYE4_COMMON_X1Y6
+set_property -dict {LOC AL4  } [get_ports {pcie_rx_p[5]}]  ;# MGTYRXP2_226 GTYE4_CHANNEL_X1Y26 / GTYE4_COMMON_X1Y6
+set_property -dict {LOC AL3  } [get_ports {pcie_rx_n[5]}]  ;# MGTYRXN2_226 GTYE4_CHANNEL_X1Y26 / GTYE4_COMMON_X1Y6
+set_property -dict {LOC AL9  } [get_ports {pcie_tx_p[5]}]  ;# MGTYTXP2_226 GTYE4_CHANNEL_X1Y26 / GTYE4_COMMON_X1Y6
+set_property -dict {LOC AL8  } [get_ports {pcie_tx_n[5]}]  ;# MGTYTXN2_226 GTYE4_CHANNEL_X1Y26 / GTYE4_COMMON_X1Y6
+set_property -dict {LOC AM2  } [get_ports {pcie_rx_p[6]}]  ;# MGTYRXP1_226 GTYE4_CHANNEL_X1Y25 / GTYE4_COMMON_X1Y6
+set_property -dict {LOC AM1  } [get_ports {pcie_rx_n[6]}]  ;# MGTYRXN1_226 GTYE4_CHANNEL_X1Y25 / GTYE4_COMMON_X1Y6
+set_property -dict {LOC AM7  } [get_ports {pcie_tx_p[6]}]  ;# MGTYTXP1_226 GTYE4_CHANNEL_X1Y25 / GTYE4_COMMON_X1Y6
+set_property -dict {LOC AM6  } [get_ports {pcie_tx_n[6]}]  ;# MGTYTXN1_226 GTYE4_CHANNEL_X1Y25 / GTYE4_COMMON_X1Y6
+set_property -dict {LOC AN4  } [get_ports {pcie_rx_p[7]}]  ;# MGTYRXP0_226 GTYE4_CHANNEL_X1Y24 / GTYE4_COMMON_X1Y6
+set_property -dict {LOC AN3  } [get_ports {pcie_rx_n[7]}]  ;# MGTYRXN0_226 GTYE4_CHANNEL_X1Y24 / GTYE4_COMMON_X1Y6
+set_property -dict {LOC AN9  } [get_ports {pcie_tx_p[7]}]  ;# MGTYTXP0_226 GTYE4_CHANNEL_X1Y24 / GTYE4_COMMON_X1Y6
+set_property -dict {LOC AN8  } [get_ports {pcie_tx_n[7]}]  ;# MGTYTXN0_226 GTYE4_CHANNEL_X1Y24 / GTYE4_COMMON_X1Y6
+set_property -dict {LOC AP2  } [get_ports {pcie_rx_p[8]}]  ;# MGTYRXP3_225 GTYE4_CHANNEL_X1Y23 / GTYE4_COMMON_X1Y5
+set_property -dict {LOC AP1  } [get_ports {pcie_rx_n[8]}]  ;# MGTYRXN3_225 GTYE4_CHANNEL_X1Y23 / GTYE4_COMMON_X1Y5
+set_property -dict {LOC AP7  } [get_ports {pcie_tx_p[8]}]  ;# MGTYTXP3_225 GTYE4_CHANNEL_X1Y23 / GTYE4_COMMON_X1Y5
+set_property -dict {LOC AP6  } [get_ports {pcie_tx_n[8]}]  ;# MGTYTXN3_225 GTYE4_CHANNEL_X1Y23 / GTYE4_COMMON_X1Y5
+set_property -dict {LOC AR4  } [get_ports {pcie_rx_p[9]}]  ;# MGTYRXP2_225 GTYE4_CHANNEL_X1Y22 / GTYE4_COMMON_X1Y5
+set_property -dict {LOC AR3  } [get_ports {pcie_rx_n[9]}]  ;# MGTYRXN2_225 GTYE4_CHANNEL_X1Y22 / GTYE4_COMMON_X1Y5
+set_property -dict {LOC AR9  } [get_ports {pcie_tx_p[9]}]  ;# MGTYTXP2_225 GTYE4_CHANNEL_X1Y22 / GTYE4_COMMON_X1Y5
+set_property -dict {LOC AR8  } [get_ports {pcie_tx_n[9]}]  ;# MGTYTXN2_225 GTYE4_CHANNEL_X1Y22 / GTYE4_COMMON_X1Y5
+set_property -dict {LOC AT2  } [get_ports {pcie_rx_p[10]}] ;# MGTYRXP1_225 GTYE4_CHANNEL_X1Y21 / GTYE4_COMMON_X1Y5
+set_property -dict {LOC AT1  } [get_ports {pcie_rx_n[10]}] ;# MGTYRXN1_225 GTYE4_CHANNEL_X1Y21 / GTYE4_COMMON_X1Y5
+set_property -dict {LOC AT7  } [get_ports {pcie_tx_p[10]}] ;# MGTYTXP1_225 GTYE4_CHANNEL_X1Y21 / GTYE4_COMMON_X1Y5
+set_property -dict {LOC AT6  } [get_ports {pcie_tx_n[10]}] ;# MGTYTXN1_225 GTYE4_CHANNEL_X1Y21 / GTYE4_COMMON_X1Y5
+set_property -dict {LOC AU4  } [get_ports {pcie_rx_p[11]}] ;# MGTYRXP0_225 GTYE4_CHANNEL_X1Y20 / GTYE4_COMMON_X1Y5
+set_property -dict {LOC AU3  } [get_ports {pcie_rx_n[11]}] ;# MGTYRXN0_225 GTYE4_CHANNEL_X1Y20 / GTYE4_COMMON_X1Y5
+set_property -dict {LOC AU9  } [get_ports {pcie_tx_p[11]}] ;# MGTYTXP0_225 GTYE4_CHANNEL_X1Y20 / GTYE4_COMMON_X1Y5
+set_property -dict {LOC AU8  } [get_ports {pcie_tx_n[11]}] ;# MGTYTXN0_225 GTYE4_CHANNEL_X1Y20 / GTYE4_COMMON_X1Y5
+set_property -dict {LOC AV2  } [get_ports {pcie_rx_p[12]}] ;# MGTYRXP3_224 GTYE4_CHANNEL_X1Y19 / GTYE4_COMMON_X1Y4
+set_property -dict {LOC AV1  } [get_ports {pcie_rx_n[12]}] ;# MGTYRXN3_224 GTYE4_CHANNEL_X1Y19 / GTYE4_COMMON_X1Y4
+set_property -dict {LOC AV7  } [get_ports {pcie_tx_p[12]}] ;# MGTYTXP3_224 GTYE4_CHANNEL_X1Y19 / GTYE4_COMMON_X1Y4
+set_property -dict {LOC AV6  } [get_ports {pcie_tx_n[12]}] ;# MGTYTXN3_224 GTYE4_CHANNEL_X1Y19 / GTYE4_COMMON_X1Y4
+set_property -dict {LOC AW4  } [get_ports {pcie_rx_p[13]}] ;# MGTYRXP2_224 GTYE4_CHANNEL_X1Y18 / GTYE4_COMMON_X1Y4
+set_property -dict {LOC AW3  } [get_ports {pcie_rx_n[13]}] ;# MGTYRXN2_224 GTYE4_CHANNEL_X1Y18 / GTYE4_COMMON_X1Y4
+set_property -dict {LOC BB5  } [get_ports {pcie_tx_p[13]}] ;# MGTYTXP2_224 GTYE4_CHANNEL_X1Y18 / GTYE4_COMMON_X1Y4
+set_property -dict {LOC BB4  } [get_ports {pcie_tx_n[13]}] ;# MGTYTXN2_224 GTYE4_CHANNEL_X1Y18 / GTYE4_COMMON_X1Y4
+set_property -dict {LOC BA2  } [get_ports {pcie_rx_p[14]}] ;# MGTYRXP1_224 GTYE4_CHANNEL_X1Y17 / GTYE4_COMMON_X1Y4
+set_property -dict {LOC BA1  } [get_ports {pcie_rx_n[14]}] ;# MGTYRXN1_224 GTYE4_CHANNEL_X1Y17 / GTYE4_COMMON_X1Y4
+set_property -dict {LOC BD5  } [get_ports {pcie_tx_p[14]}] ;# MGTYTXP1_224 GTYE4_CHANNEL_X1Y17 / GTYE4_COMMON_X1Y4
+set_property -dict {LOC BD4  } [get_ports {pcie_tx_n[14]}] ;# MGTYTXN1_224 GTYE4_CHANNEL_X1Y17 / GTYE4_COMMON_X1Y4
+set_property -dict {LOC BC2  } [get_ports {pcie_rx_p[15]}] ;# MGTYRXP0_224 GTYE4_CHANNEL_X1Y16 / GTYE4_COMMON_X1Y4
+set_property -dict {LOC BC1  } [get_ports {pcie_rx_n[15]}] ;# MGTYRXN0_224 GTYE4_CHANNEL_X1Y16 / GTYE4_COMMON_X1Y4
+set_property -dict {LOC BF5  } [get_ports {pcie_tx_p[15]}] ;# MGTYTXP0_224 GTYE4_CHANNEL_X1Y16 / GTYE4_COMMON_X1Y4
+set_property -dict {LOC BF4  } [get_ports {pcie_tx_n[15]}] ;# MGTYTXN0_224 GTYE4_CHANNEL_X1Y16 / GTYE4_COMMON_X1Y4
+set_property -dict {LOC AM11 } [get_ports pcie_refclk_p] ;# MGTREFCLK0P_226
+set_property -dict {LOC AM10 } [get_ports pcie_refclk_n] ;# MGTREFCLK0N_226
+set_property -dict {LOC BD21 IOSTANDARD LVCMOS12 PULLUP true} [get_ports pcie_reset_n]
+
+# 100 MHz MGT reference clock
+create_clock -period 10 -name pcie_mgt_refclk_1 [get_ports pcie_refclk_p]
+
+set_false_path -from [get_ports {pcie_reset_n}]
+set_input_delay 0 [get_ports {pcie_reset_n}]

snapshots/alexforencich_verilog-pcie_pr20/example/AU250/fpga_axi/fpga/Makefile

@@ -0,0 +1,85 @@
+
+# FPGA settings
+FPGA_PART = xcu250-figd2104-2-e
+FPGA_TOP = fpga
+FPGA_ARCH = virtexuplus
+
+# Files for synthesis
+SYN_FILES = rtl/fpga.v
+SYN_FILES += rtl/fpga_core.v
+SYN_FILES += rtl/debounce_switch.v
+SYN_FILES += rtl/sync_reset.v
+SYN_FILES += rtl/sync_signal.v
+SYN_FILES += rtl/axi_ram.v
+SYN_FILES += rtl/axis_register.v
+SYN_FILES += lib/pcie/rtl/axis_arb_mux.v
+SYN_FILES += lib/pcie/rtl/pcie_us_axil_master.v
+SYN_FILES += lib/pcie/rtl/pcie_us_axi_dma.v
+SYN_FILES += lib/pcie/rtl/pcie_us_axi_dma_rd.v
+SYN_FILES += lib/pcie/rtl/pcie_us_axi_dma_wr.v
+SYN_FILES += lib/pcie/rtl/pcie_us_axi_master.v
+SYN_FILES += lib/pcie/rtl/pcie_us_axi_master_rd.v
+SYN_FILES += lib/pcie/rtl/pcie_us_axi_master_wr.v
+SYN_FILES += lib/pcie/rtl/pcie_us_axis_cq_demux.v
+SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v
+SYN_FILES += lib/pcie/rtl/pcie_us_msi.v
+SYN_FILES += lib/pcie/rtl/arbiter.v
+SYN_FILES += lib/pcie/rtl/priority_encoder.v
+SYN_FILES += lib/pcie/rtl/pulse_merge.v
+
+# XDC files
+XDC_FILES = fpga.xdc
+
+# IP
+IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl
+
+include ../common/vivado.mk
+
+program: $(FPGA_TOP).bit
+	echo "open_hw" > program.tcl
+	echo "connect_hw_server" >> program.tcl
+	echo "open_hw_target" >> program.tcl
+	echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
+	echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
+	echo "set_property PROGRAM.FILE {$(FPGA_TOP).bit} [current_hw_device]" >> program.tcl
+	echo "program_hw_devices [current_hw_device]" >> program.tcl
+	echo "exit" >> program.tcl
+	vivado -nojournal -nolog -mode batch -source program.tcl
+
+%.mcs %.prm: %.bit
+	echo "write_cfgmem -force -format mcs -size 128 -interface SPIx4 -loadbit {up 0x01002000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl
+	echo "exit" >> generate_mcs.tcl
+	vivado -nojournal -nolog -mode batch -source generate_mcs.tcl
+	mkdir -p rev
+	COUNT=100; \
+	while [ -e rev/$*_rev$$COUNT.bit ]; \
+	do COUNT=$$((COUNT+1)); done; \
+	COUNT=$$((COUNT-1)); \
+	for x in .mcs .prm; \
+	do cp $*$$x rev/$*_rev$$COUNT$$x; \
+	echo "Output: rev/$*_rev$$COUNT$$x"; done;
+
+flash: $(FPGA_TOP).mcs $(FPGA_TOP).prm
+	echo "open_hw" > flash.tcl
+	echo "connect_hw_server" >> flash.tcl
+	echo "open_hw_target" >> flash.tcl
+	echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash.tcl
+	echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash.tcl
+	echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {mt25qu01g-spi-x1_x2_x4}] 0]" >> flash.tcl
+	echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash.tcl
+	echo "set_property PROGRAM.FILES [list \"$(FPGA_TOP).mcs\"] [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.PRM_FILES [list \"$(FPGA_TOP).prm\"] [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash.tcl
+	echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash.tcl
+	echo "program_hw_devices [current_hw_device]" >> flash.tcl
+	echo "refresh_hw_device [current_hw_device]" >> flash.tcl
+	echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash.tcl
+	echo "boot_hw_device [current_hw_device]" >> flash.tcl
+	echo "exit" >> flash.tcl
+	vivado -nojournal -nolog -mode batch -source flash.tcl
+

snapshots/alexforencich_verilog-pcie_pr20/example/AU250/fpga_axi/ip/pcie4_uscale_plus_0.tcl

@@ -0,0 +1,28 @@
+
+create_ip -name pcie4_uscale_plus -vendor xilinx.com -library ip -module_name pcie4_uscale_plus_0
+
+set_property -dict [list \
+    CONFIG.PL_LINK_CAP_MAX_LINK_SPEED {8.0_GT/s} \
+    CONFIG.PL_LINK_CAP_MAX_LINK_WIDTH {X16} \
+    CONFIG.AXISTEN_IF_EXT_512_RQ_STRADDLE {false} \
+    CONFIG.axisten_if_enable_client_tag {true} \
+    CONFIG.axisten_if_width {512_bit} \
+    CONFIG.axisten_freq {250} \
+    CONFIG.PF0_CLASS_CODE {058000} \
+    CONFIG.PF0_DEVICE_ID {0001} \
+    CONFIG.PF0_MSI_CAP_MULTIMSGCAP {32_vectors} \
+    CONFIG.PF0_SUBSYSTEM_ID {90fa} \
+    CONFIG.PF0_SUBSYSTEM_VENDOR_ID {10ee} \
+    CONFIG.pf0_bar0_64bit {true} \
+    CONFIG.pf0_bar0_prefetchable {true} \
+    CONFIG.pf0_bar0_scale {Megabytes} \
+    CONFIG.pf0_bar0_size {16} \
+    CONFIG.pf0_bar2_64bit {true} \
+    CONFIG.pf0_bar2_prefetchable {true} \
+    CONFIG.pf0_bar2_enabled {true} \
+    CONFIG.pf0_bar2_type {Memory} \
+    CONFIG.pf0_bar2_scale {Megabytes} \
+    CONFIG.pf0_bar2_size {16} \
+    CONFIG.vendor_id {1234} \
+    CONFIG.en_msi_per_vec_masking {true} \
+] [get_ips pcie4_uscale_plus_0]

snapshots/alexforencich_verilog-pcie_pr20/example/AU250/fpga_axi/rtl/axi_ram.v

@@ -0,0 +1,369 @@
+/*
+
+Copyright (c) 2018 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog 2001
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * AXI4 RAM
+ */
+module axi_ram #
+(
+    parameter DATA_WIDTH = 32,  // width of data bus in bits
+    parameter ADDR_WIDTH = 16,  // width of address bus in bits
+    parameter STRB_WIDTH = (DATA_WIDTH/8),
+    parameter ID_WIDTH = 8,
+    parameter PIPELINE_OUTPUT = 0
+)
+(
+    input  wire                   clk,
+    input  wire                   rst,
+
+    input  wire [ID_WIDTH-1:0]    s_axi_awid,
+    input  wire [ADDR_WIDTH-1:0]  s_axi_awaddr,
+    input  wire [7:0]             s_axi_awlen,
+    input  wire [2:0]             s_axi_awsize,
+    input  wire [1:0]             s_axi_awburst,
+    input  wire                   s_axi_awlock,
+    input  wire [3:0]             s_axi_awcache,
+    input  wire [2:0]             s_axi_awprot,
+    input  wire                   s_axi_awvalid,
+    output wire                   s_axi_awready,
+    input  wire [DATA_WIDTH-1:0]  s_axi_wdata,
+    input  wire [STRB_WIDTH-1:0]  s_axi_wstrb,
+    input  wire                   s_axi_wlast,
+    input  wire                   s_axi_wvalid,
+    output wire                   s_axi_wready,
+    output wire [ID_WIDTH-1:0]    s_axi_bid,
+    output wire [1:0]             s_axi_bresp,
+    output wire                   s_axi_bvalid,
+    input  wire                   s_axi_bready,
+    input  wire [ID_WIDTH-1:0]    s_axi_arid,
+    input  wire [ADDR_WIDTH-1:0]  s_axi_araddr,
+    input  wire [7:0]             s_axi_arlen,
+    input  wire [2:0]             s_axi_arsize,
+    input  wire [1:0]             s_axi_arburst,
+    input  wire                   s_axi_arlock,
+    input  wire [3:0]             s_axi_arcache,
+    input  wire [2:0]             s_axi_arprot,
+    input  wire                   s_axi_arvalid,
+    output wire                   s_axi_arready,
+    output wire [ID_WIDTH-1:0]    s_axi_rid,
+    output wire [DATA_WIDTH-1:0]  s_axi_rdata,
+    output wire [1:0]             s_axi_rresp,
+    output wire                   s_axi_rlast,
+    output wire                   s_axi_rvalid,
+    input  wire                   s_axi_rready
+);
+
+parameter VALID_ADDR_WIDTH = ADDR_WIDTH - $clog2(STRB_WIDTH);
+parameter WORD_WIDTH = STRB_WIDTH;
+parameter WORD_SIZE = DATA_WIDTH/WORD_WIDTH;
+
+// bus width assertions
+initial begin
+    if (WORD_SIZE * STRB_WIDTH != DATA_WIDTH) begin
+        $error("Error: AXI data width not evenly divisble");
+        $finish;
+    end
+
+    if (2**$clog2(WORD_WIDTH) != WORD_WIDTH) begin
+        $error("Error: AXI word width must be even power of two");
+        $finish;
+    end
+end
+
+localparam [0:0]
+    READ_STATE_IDLE = 1'd0,
+    READ_STATE_BURST = 1'd1;
+
+reg [0:0] read_state_reg = READ_STATE_IDLE, read_state_next;
+
+localparam [1:0]
+    WRITE_STATE_IDLE = 2'd0,
+    WRITE_STATE_BURST = 2'd1,
+    WRITE_STATE_RESP = 2'd2;
+
+reg [1:0] write_state_reg = WRITE_STATE_IDLE, write_state_next;
+
+reg mem_wr_en;
+reg mem_rd_en;
+
+reg [ID_WIDTH-1:0] read_id_reg = {ID_WIDTH{1'b0}}, read_id_next;
+reg [ADDR_WIDTH-1:0] read_addr_reg = {ADDR_WIDTH{1'b0}}, read_addr_next;
+reg [7:0] read_count_reg = 8'd0, read_count_next;
+reg [2:0] read_size_reg = 3'd0, read_size_next;
+reg [1:0] read_burst_reg = 2'd0, read_burst_next;
+reg [ID_WIDTH-1:0] write_id_reg = {ID_WIDTH{1'b0}}, write_id_next;
+reg [ADDR_WIDTH-1:0] write_addr_reg = {ADDR_WIDTH{1'b0}}, write_addr_next;
+reg [7:0] write_count_reg = 8'd0, write_count_next;
+reg [2:0] write_size_reg = 3'd0, write_size_next;
+reg [1:0] write_burst_reg = 2'd0, write_burst_next;
+
+reg s_axi_awready_reg = 1'b0, s_axi_awready_next;
+reg s_axi_wready_reg = 1'b0, s_axi_wready_next;
+reg [ID_WIDTH-1:0] s_axi_bid_reg = {ID_WIDTH{1'b0}}, s_axi_bid_next;
+reg s_axi_bvalid_reg = 1'b0, s_axi_bvalid_next;
+reg s_axi_arready_reg = 1'b0, s_axi_arready_next;
+reg [ID_WIDTH-1:0] s_axi_rid_reg = {ID_WIDTH{1'b0}}, s_axi_rid_next;
+reg [DATA_WIDTH-1:0] s_axi_rdata_reg = {DATA_WIDTH{1'b0}}, s_axi_rdata_next;
+reg s_axi_rlast_reg = 1'b0, s_axi_rlast_next;
+reg s_axi_rvalid_reg = 1'b0, s_axi_rvalid_next;
+reg [ID_WIDTH-1:0] s_axi_rid_pipe_reg = {ID_WIDTH{1'b0}};
+reg [DATA_WIDTH-1:0] s_axi_rdata_pipe_reg = {DATA_WIDTH{1'b0}};
+reg s_axi_rlast_pipe_reg = 1'b0;
+reg s_axi_rvalid_pipe_reg = 1'b0;
+
+// (* RAM_STYLE="BLOCK" *)
+reg [DATA_WIDTH-1:0] mem[(2**VALID_ADDR_WIDTH)-1:0];
+
+wire [VALID_ADDR_WIDTH-1:0] s_axi_awaddr_valid = s_axi_awaddr >> (ADDR_WIDTH - VALID_ADDR_WIDTH);
+wire [VALID_ADDR_WIDTH-1:0] s_axi_araddr_valid = s_axi_araddr >> (ADDR_WIDTH - VALID_ADDR_WIDTH);
+wire [VALID_ADDR_WIDTH-1:0] read_addr_valid = read_addr_reg >> (ADDR_WIDTH - VALID_ADDR_WIDTH);
+wire [VALID_ADDR_WIDTH-1:0] write_addr_valid = write_addr_reg >> (ADDR_WIDTH - VALID_ADDR_WIDTH);
+
+assign s_axi_awready = s_axi_awready_reg;
+assign s_axi_wready = s_axi_wready_reg;
+assign s_axi_bid = s_axi_bid_reg;
+assign s_axi_bresp = 2'b00;
+assign s_axi_bvalid = s_axi_bvalid_reg;
+assign s_axi_arready = s_axi_arready_reg;
+assign s_axi_rid = PIPELINE_OUTPUT ? s_axi_rid_pipe_reg : s_axi_rid_reg;
+assign s_axi_rdata = PIPELINE_OUTPUT ? s_axi_rdata_pipe_reg : s_axi_rdata_reg;
+assign s_axi_rresp = 2'b00;
+assign s_axi_rlast = PIPELINE_OUTPUT ? s_axi_rlast_pipe_reg : s_axi_rlast_reg;
+assign s_axi_rvalid = PIPELINE_OUTPUT ? s_axi_rvalid_pipe_reg : s_axi_rvalid_reg;
+
+integer i, j;
+
+initial begin
+    // two nested loops for smaller number of iterations per loop
+    // workaround for synthesizer complaints about large loop counts
+    for (i = 0; i < 2**ADDR_WIDTH; i = i + 2**(ADDR_WIDTH/2)) begin
+        for (j = i; j < i + 2**(ADDR_WIDTH/2); j = j + 1) begin
+            mem[j] = 0;
+        end
+    end
+end
+
+always @* begin
+    write_state_next = WRITE_STATE_IDLE;
+
+    mem_wr_en = 1'b0;
+
+    write_id_next = write_id_reg;
+    write_addr_next = write_addr_reg;
+    write_count_next = write_count_reg;
+    write_size_next = write_size_reg;
+    write_burst_next = write_burst_reg;
+
+    s_axi_awready_next = 1'b0;
+    s_axi_wready_next = 1'b0;
+    s_axi_bid_next = s_axi_bid_reg;
+    s_axi_bvalid_next = s_axi_bvalid_reg && !s_axi_bready;
+
+    case (write_state_reg)
+        WRITE_STATE_IDLE: begin
+            s_axi_awready_next = 1'b1;
+
+            if (s_axi_awready && s_axi_awvalid) begin
+                write_id_next = s_axi_awid;
+                write_addr_next = s_axi_awaddr;
+                write_count_next = s_axi_awlen;
+                write_size_next = s_axi_awsize < $clog2(STRB_WIDTH) ? s_axi_awsize : $clog2(STRB_WIDTH);
+                write_burst_next = s_axi_awburst;
+
+                s_axi_awready_next = 1'b0;
+                s_axi_wready_next = 1'b1;
+                write_state_next = WRITE_STATE_BURST;
+            end else begin
+                write_state_next = WRITE_STATE_IDLE;
+            end
+        end
+        WRITE_STATE_BURST: begin
+            s_axi_wready_next = 1'b1;
+
+            if (s_axi_wready && s_axi_wvalid) begin
+                mem_wr_en = 1'b1;
+                if (write_burst_reg != 2'b00) begin
+                    write_addr_next = write_addr_reg + (1 << write_size_reg);
+                end
+                write_count_next = write_count_reg - 1;
+                if (write_count_reg > 0) begin
+                    write_state_next = WRITE_STATE_BURST;
+                end else begin
+                    s_axi_wready_next = 1'b0;
+                    if (s_axi_bready || !s_axi_bvalid) begin
+                        s_axi_bid_next = write_id_reg;
+                        s_axi_bvalid_next = 1'b1;
+                        s_axi_awready_next = 1'b1;
+                        write_state_next = WRITE_STATE_IDLE;
+                    end else begin
+                        write_state_next = WRITE_STATE_RESP;
+                    end
+                end
+            end else begin
+                write_state_next = WRITE_STATE_BURST;
+            end
+        end
+        WRITE_STATE_RESP: begin
+            if (s_axi_bready || !s_axi_bvalid) begin
+                s_axi_bid_next = write_id_reg;
+                s_axi_bvalid_next = 1'b1;
+                s_axi_awready_next = 1'b1;
+                write_state_next = WRITE_STATE_IDLE;
+            end else begin
+                write_state_next = WRITE_STATE_RESP;
+            end
+        end
+    endcase
+end
+
+always @(posedge clk) begin
+    if (rst) begin
+        write_state_reg <= WRITE_STATE_IDLE;
+        s_axi_awready_reg <= 1'b0;
+        s_axi_wready_reg <= 1'b0;
+        s_axi_bvalid_reg <= 1'b0;
+    end else begin
+        write_state_reg <= write_state_next;
+        s_axi_awready_reg <= s_axi_awready_next;
+        s_axi_wready_reg <= s_axi_wready_next;
+        s_axi_bvalid_reg <= s_axi_bvalid_next;
+    end
+
+    write_id_reg <= write_id_next;
+    write_addr_reg <= write_addr_next;
+    write_count_reg <= write_count_next;
+    write_size_reg <= write_size_next;
+    write_burst_reg <= write_burst_next;
+
+    s_axi_bid_reg <= s_axi_bid_next;
+
+    for (i = 0; i < WORD_WIDTH; i = i + 1) begin
+        if (mem_wr_en & s_axi_wstrb[i]) begin
+            mem[write_addr_valid][WORD_SIZE*i +: WORD_SIZE] <= s_axi_wdata[WORD_SIZE*i +: WORD_SIZE];
+        end
+    end
+end
+
+always @* begin
+    read_state_next = READ_STATE_IDLE;
+
+    mem_rd_en = 1'b0;
+
+    s_axi_rid_next = s_axi_rid_reg;
+    s_axi_rlast_next = s_axi_rlast_reg;
+    s_axi_rvalid_next = s_axi_rvalid_reg && !(s_axi_rready || (PIPELINE_OUTPUT && !s_axi_rvalid_pipe_reg));
+
+    read_id_next = read_id_reg;
+    read_addr_next = read_addr_reg;
+    read_count_next = read_count_reg;
+    read_size_next = read_size_reg;
+    read_burst_next = read_burst_reg;
+
+    s_axi_arready_next = 1'b0;
+
+    case (read_state_reg)
+        READ_STATE_IDLE: begin
+            s_axi_arready_next = 1'b1;
+
+            if (s_axi_arready && s_axi_arvalid) begin
+                read_id_next = s_axi_arid;
+                read_addr_next = s_axi_araddr;
+                read_count_next = s_axi_arlen;
+                read_size_next = s_axi_arsize < $clog2(STRB_WIDTH) ? s_axi_arsize : $clog2(STRB_WIDTH);
+                read_burst_next = s_axi_arburst;
+
+                s_axi_arready_next = 1'b0;
+                read_state_next = READ_STATE_BURST;
+            end else begin
+                read_state_next = READ_STATE_IDLE;
+            end
+        end
+        READ_STATE_BURST: begin
+            if (s_axi_rready || (PIPELINE_OUTPUT && !s_axi_rvalid_pipe_reg) || !s_axi_rvalid_reg) begin
+                mem_rd_en = 1'b1;
+                s_axi_rvalid_next = 1'b1;
+                s_axi_rid_next = read_id_reg;
+                s_axi_rlast_next = read_count_reg == 0;
+                if (read_burst_reg != 2'b00) begin
+                    read_addr_next = read_addr_reg + (1 << read_size_reg);
+                end
+                read_count_next = read_count_reg - 1;
+                if (read_count_reg > 0) begin
+                    read_state_next = READ_STATE_BURST;
+                end else begin
+                    s_axi_arready_next = 1'b1;
+                    read_state_next = READ_STATE_IDLE;
+                end
+            end else begin
+                read_state_next = READ_STATE_BURST;
+            end
+        end
+    endcase
+end
+
+always @(posedge clk) begin
+    if (rst) begin
+        read_state_reg <= READ_STATE_IDLE;
+        s_axi_arready_reg <= 1'b0;
+        s_axi_rvalid_reg <= 1'b0;
+        s_axi_rvalid_pipe_reg <= 1'b0;
+    end else begin
+        read_state_reg <= read_state_next;
+        s_axi_arready_reg <= s_axi_arready_next;
+        s_axi_rvalid_reg <= s_axi_rvalid_next;
+
+        if (!s_axi_rvalid_pipe_reg || s_axi_rready) begin
+            s_axi_rvalid_pipe_reg <= s_axi_rvalid_reg;
+        end
+    end
+
+    read_id_reg <= read_id_next;
+    read_addr_reg <= read_addr_next;
+    read_count_reg <= read_count_next;
+    read_size_reg <= read_size_next;
+    read_burst_reg <= read_burst_next;
+
+    s_axi_rid_reg <= s_axi_rid_next;
+    s_axi_rlast_reg <= s_axi_rlast_next;
+
+    if (mem_rd_en) begin
+        s_axi_rdata_reg <= mem[read_addr_valid];
+    end
+
+    if (!s_axi_rvalid_pipe_reg || s_axi_rready) begin
+        s_axi_rid_pipe_reg <= s_axi_rid_reg;
+        s_axi_rdata_pipe_reg <= s_axi_rdata_reg;
+        s_axi_rlast_pipe_reg <= s_axi_rlast_reg;
+    end
+end
+
+endmodule
+
+`resetall

snapshots/alexforencich_verilog-pcie_pr20/example/AU250/fpga_axi/rtl/axis_register.v

@@ -0,0 +1,268 @@
+/*
+
+Copyright (c) 2014-2018 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog 2001
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * AXI4-Stream register
+ */
+module axis_register #
+(
+    parameter DATA_WIDTH = 8,
+    parameter KEEP_ENABLE = (DATA_WIDTH>8),
+    parameter KEEP_WIDTH = (DATA_WIDTH/8),
+    parameter LAST_ENABLE = 1,
+    parameter ID_ENABLE = 0,
+    parameter ID_WIDTH = 8,
+    parameter DEST_ENABLE = 0,
+    parameter DEST_WIDTH = 8,
+    parameter USER_ENABLE = 1,
+    parameter USER_WIDTH = 1,
+    parameter REG_TYPE = 2
+)
+(
+    input  wire                   clk,
+    input  wire                   rst,
+
+    /*
+     * AXI Stream input
+     */
+    input  wire [DATA_WIDTH-1:0]  s_axis_tdata,
+    input  wire [KEEP_WIDTH-1:0]  s_axis_tkeep,
+    input  wire                   s_axis_tvalid,
+    output wire                   s_axis_tready,
+    input  wire                   s_axis_tlast,
+    input  wire [ID_WIDTH-1:0]    s_axis_tid,
+    input  wire [DEST_WIDTH-1:0]  s_axis_tdest,
+    input  wire [USER_WIDTH-1:0]  s_axis_tuser,
+
+    /*
+     * AXI Stream output
+     */
+    output wire [DATA_WIDTH-1:0]  m_axis_tdata,
+    output wire [KEEP_WIDTH-1:0]  m_axis_tkeep,
+    output wire                   m_axis_tvalid,
+    input  wire                   m_axis_tready,
+    output wire                   m_axis_tlast,
+    output wire [ID_WIDTH-1:0]    m_axis_tid,
+    output wire [DEST_WIDTH-1:0]  m_axis_tdest,
+    output wire [USER_WIDTH-1:0]  m_axis_tuser
+);
+
+generate
+
+if (REG_TYPE > 1) begin
+    // skid buffer, no bubble cycles
+
+    // datapath registers
+    reg                  s_axis_tready_reg = 1'b0;
+
+    reg [DATA_WIDTH-1:0] m_axis_tdata_reg  = {DATA_WIDTH{1'b0}};
+    reg [KEEP_WIDTH-1:0] m_axis_tkeep_reg  = {KEEP_WIDTH{1'b0}};
+    reg                  m_axis_tvalid_reg = 1'b0, m_axis_tvalid_next;
+    reg                  m_axis_tlast_reg  = 1'b0;
+    reg [ID_WIDTH-1:0]   m_axis_tid_reg    = {ID_WIDTH{1'b0}};
+    reg [DEST_WIDTH-1:0] m_axis_tdest_reg  = {DEST_WIDTH{1'b0}};
+    reg [USER_WIDTH-1:0] m_axis_tuser_reg  = {USER_WIDTH{1'b0}};
+
+    reg [DATA_WIDTH-1:0] temp_m_axis_tdata_reg  = {DATA_WIDTH{1'b0}};
+    reg [KEEP_WIDTH-1:0] temp_m_axis_tkeep_reg  = {KEEP_WIDTH{1'b0}};
+    reg                  temp_m_axis_tvalid_reg = 1'b0, temp_m_axis_tvalid_next;
+    reg                  temp_m_axis_tlast_reg  = 1'b0;
+    reg [ID_WIDTH-1:0]   temp_m_axis_tid_reg    = {ID_WIDTH{1'b0}};
+    reg [DEST_WIDTH-1:0] temp_m_axis_tdest_reg  = {DEST_WIDTH{1'b0}};
+    reg [USER_WIDTH-1:0] temp_m_axis_tuser_reg  = {USER_WIDTH{1'b0}};
+
+    // datapath control
+    reg store_axis_input_to_output;
+    reg store_axis_input_to_temp;
+    reg store_axis_temp_to_output;
+
+    assign s_axis_tready = s_axis_tready_reg;
+
+    assign m_axis_tdata  = m_axis_tdata_reg;
+    assign m_axis_tkeep  = KEEP_ENABLE ? m_axis_tkeep_reg : {KEEP_WIDTH{1'b1}};
+    assign m_axis_tvalid = m_axis_tvalid_reg;
+    assign m_axis_tlast  = LAST_ENABLE ? m_axis_tlast_reg : 1'b1;
+    assign m_axis_tid    = ID_ENABLE   ? m_axis_tid_reg   : {ID_WIDTH{1'b0}};
+    assign m_axis_tdest  = DEST_ENABLE ? m_axis_tdest_reg : {DEST_WIDTH{1'b0}};
+    assign m_axis_tuser  = USER_ENABLE ? m_axis_tuser_reg : {USER_WIDTH{1'b0}};
+
+    // enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
+    wire s_axis_tready_early = m_axis_tready || (!temp_m_axis_tvalid_reg && (!m_axis_tvalid_reg || !s_axis_tvalid));
+
+    always @* begin
+        // transfer sink ready state to source
+        m_axis_tvalid_next = m_axis_tvalid_reg;
+        temp_m_axis_tvalid_next = temp_m_axis_tvalid_reg;
+
+        store_axis_input_to_output = 1'b0;
+        store_axis_input_to_temp = 1'b0;
+        store_axis_temp_to_output = 1'b0;
+
+        if (s_axis_tready_reg) begin
+            // input is ready
+            if (m_axis_tready || !m_axis_tvalid_reg) begin
+                // output is ready or currently not valid, transfer data to output
+                m_axis_tvalid_next = s_axis_tvalid;
+                store_axis_input_to_output = 1'b1;
+            end else begin
+                // output is not ready, store input in temp
+                temp_m_axis_tvalid_next = s_axis_tvalid;
+                store_axis_input_to_temp = 1'b1;
+            end
+        end else if (m_axis_tready) begin
+            // input is not ready, but output is ready
+            m_axis_tvalid_next = temp_m_axis_tvalid_reg;
+            temp_m_axis_tvalid_next = 1'b0;
+            store_axis_temp_to_output = 1'b1;
+        end
+    end
+
+    always @(posedge clk) begin
+        if (rst) begin
+            s_axis_tready_reg <= 1'b0;
+            m_axis_tvalid_reg <= 1'b0;
+            temp_m_axis_tvalid_reg <= 1'b0;
+        end else begin
+            s_axis_tready_reg <= s_axis_tready_early;
+            m_axis_tvalid_reg <= m_axis_tvalid_next;
+            temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
+        end
+
+        // datapath
+        if (store_axis_input_to_output) begin
+            m_axis_tdata_reg <= s_axis_tdata;
+            m_axis_tkeep_reg <= s_axis_tkeep;
+            m_axis_tlast_reg <= s_axis_tlast;
+            m_axis_tid_reg   <= s_axis_tid;
+            m_axis_tdest_reg <= s_axis_tdest;
+            m_axis_tuser_reg <= s_axis_tuser;
+        end else if (store_axis_temp_to_output) begin
+            m_axis_tdata_reg <= temp_m_axis_tdata_reg;
+            m_axis_tkeep_reg <= temp_m_axis_tkeep_reg;
+            m_axis_tlast_reg <= temp_m_axis_tlast_reg;
+            m_axis_tid_reg   <= temp_m_axis_tid_reg;
+            m_axis_tdest_reg <= temp_m_axis_tdest_reg;
+            m_axis_tuser_reg <= temp_m_axis_tuser_reg;
+        end
+
+        if (store_axis_input_to_temp) begin
+            temp_m_axis_tdata_reg <= s_axis_tdata;
+            temp_m_axis_tkeep_reg <= s_axis_tkeep;
+            temp_m_axis_tlast_reg <= s_axis_tlast;
+            temp_m_axis_tid_reg   <= s_axis_tid;
+            temp_m_axis_tdest_reg <= s_axis_tdest;
+            temp_m_axis_tuser_reg <= s_axis_tuser;
+        end
+    end
+
+end else if (REG_TYPE == 1) begin
+    // simple register, inserts bubble cycles
+
+    // datapath registers
+    reg                  s_axis_tready_reg = 1'b0;
+
+    reg [DATA_WIDTH-1:0] m_axis_tdata_reg  = {DATA_WIDTH{1'b0}};
+    reg [KEEP_WIDTH-1:0] m_axis_tkeep_reg  = {KEEP_WIDTH{1'b0}};
+    reg                  m_axis_tvalid_reg = 1'b0, m_axis_tvalid_next;
+    reg                  m_axis_tlast_reg  = 1'b0;
+    reg [ID_WIDTH-1:0]   m_axis_tid_reg    = {ID_WIDTH{1'b0}};
+    reg [DEST_WIDTH-1:0] m_axis_tdest_reg  = {DEST_WIDTH{1'b0}};
+    reg [USER_WIDTH-1:0] m_axis_tuser_reg  = {USER_WIDTH{1'b0}};
+
+    // datapath control
+    reg store_axis_input_to_output;
+
+    assign s_axis_tready = s_axis_tready_reg;
+
+    assign m_axis_tdata  = m_axis_tdata_reg;
+    assign m_axis_tkeep  = KEEP_ENABLE ? m_axis_tkeep_reg : {KEEP_WIDTH{1'b1}};
+    assign m_axis_tvalid = m_axis_tvalid_reg;
+    assign m_axis_tlast  = LAST_ENABLE ? m_axis_tlast_reg : 1'b1;
+    assign m_axis_tid    = ID_ENABLE   ? m_axis_tid_reg   : {ID_WIDTH{1'b0}};
+    assign m_axis_tdest  = DEST_ENABLE ? m_axis_tdest_reg : {DEST_WIDTH{1'b0}};
+    assign m_axis_tuser  = USER_ENABLE ? m_axis_tuser_reg : {USER_WIDTH{1'b0}};
+
+    // enable ready input next cycle if output buffer will be empty
+    wire s_axis_tready_early = !m_axis_tvalid_next;
+
+    always @* begin
+        // transfer sink ready state to source
+        m_axis_tvalid_next = m_axis_tvalid_reg;
+
+        store_axis_input_to_output = 1'b0;
+
+        if (s_axis_tready_reg) begin
+            m_axis_tvalid_next = s_axis_tvalid;
+            store_axis_input_to_output = 1'b1;
+        end else if (m_axis_tready) begin
+            m_axis_tvalid_next = 1'b0;
+        end
+    end
+
+    always @(posedge clk) begin
+        if (rst) begin
+            s_axis_tready_reg <= 1'b0;
+            m_axis_tvalid_reg <= 1'b0;
+        end else begin
+            s_axis_tready_reg <= s_axis_tready_early;
+            m_axis_tvalid_reg <= m_axis_tvalid_next;
+        end
+
+        // datapath
+        if (store_axis_input_to_output) begin
+            m_axis_tdata_reg <= s_axis_tdata;
+            m_axis_tkeep_reg <= s_axis_tkeep;
+            m_axis_tlast_reg <= s_axis_tlast;
+            m_axis_tid_reg   <= s_axis_tid;
+            m_axis_tdest_reg <= s_axis_tdest;
+            m_axis_tuser_reg <= s_axis_tuser;
+        end
+    end
+
+end else begin
+    // bypass
+
+    assign m_axis_tdata  = s_axis_tdata;
+    assign m_axis_tkeep  = KEEP_ENABLE ? s_axis_tkeep : {KEEP_WIDTH{1'b1}};
+    assign m_axis_tvalid = s_axis_tvalid;
+    assign m_axis_tlast  = LAST_ENABLE ? s_axis_tlast : 1'b1;
+    assign m_axis_tid    = ID_ENABLE   ? s_axis_tid   : {ID_WIDTH{1'b0}};
+    assign m_axis_tdest  = DEST_ENABLE ? s_axis_tdest : {DEST_WIDTH{1'b0}};
+    assign m_axis_tuser  = USER_ENABLE ? s_axis_tuser : {USER_WIDTH{1'b0}};
+
+    assign s_axis_tready = m_axis_tready;
+
+end
+
+endgenerate
+
+endmodule
+
+`resetall

snapshots/alexforencich_verilog-pcie_pr20/example/AU250/fpga_axi/rtl/debounce_switch.v

@@ -0,0 +1,93 @@
+/*
+
+Copyright (c) 2014-2018 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog-2001
+
+`resetall
+`timescale 1 ns / 1 ps
+`default_nettype none
+
+/*
+ * Synchronizes switch and button inputs with a slow sampled shift register
+ */
+module debounce_switch  #(
+    parameter WIDTH=1, // width of the input and output signals
+    parameter N=3, // length of shift register
+    parameter RATE=125000 // clock division factor
+)(
+    input wire clk,
+    input wire rst,
+    input wire [WIDTH-1:0] in,
+    output wire [WIDTH-1:0] out
+);
+
+reg [23:0] cnt_reg = 24'd0;
+
+reg [N-1:0] debounce_reg[WIDTH-1:0];
+
+reg [WIDTH-1:0] state;
+
+/*
+ * The synchronized output is the state register
+ */
+assign out = state;
+
+integer k;
+
+always @(posedge clk or posedge rst) begin
+    if (rst) begin
+        cnt_reg <= 0;
+        state <= 0;
+        
+        for (k = 0; k < WIDTH; k = k + 1) begin
+            debounce_reg[k] <= 0;
+        end
+    end else begin
+        if (cnt_reg < RATE) begin
+            cnt_reg <= cnt_reg + 24'd1;
+        end else begin
+            cnt_reg <= 24'd0;
+        end
+        
+        if (cnt_reg == 24'd0) begin
+            for (k = 0; k < WIDTH; k = k + 1) begin
+                debounce_reg[k] <= {debounce_reg[k][N-2:0], in[k]};
+            end
+        end
+        
+        for (k = 0; k < WIDTH; k = k + 1) begin
+            if (|debounce_reg[k] == 0) begin
+                state[k] <= 0;
+            end else if (&debounce_reg[k] == 1) begin
+                state[k] <= 1;
+            end else begin
+                state[k] <= state[k];
+            end
+        end
+    end
+end
+
+endmodule
+
+`resetall

snapshots/alexforencich_verilog-pcie_pr20/example/AU250/fpga_axi/rtl/fpga.v

@@ -0,0 +1,428 @@
+/*
+
+Copyright (c) 2018 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog 2001
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * FPGA top-level module
+ */
+module fpga (
+    /*
+     * GPIO
+     */
+    input  wire [3:0]  sw,
+    output wire [2:0]  led,
+
+    /*
+     * PCI express
+     */
+    input  wire [15:0] pcie_rx_p,
+    input  wire [15:0] pcie_rx_n,
+    output wire [15:0] pcie_tx_p,
+    output wire [15:0] pcie_tx_n,
+    input  wire        pcie_refclk_p,
+    input  wire        pcie_refclk_n,
+    input  wire        pcie_reset_n
+);
+
+parameter AXIS_PCIE_DATA_WIDTH = 512;
+parameter AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32);
+parameter AXIS_PCIE_RC_USER_WIDTH = 161;
+parameter AXIS_PCIE_RQ_USER_WIDTH = 137;
+parameter AXIS_PCIE_CQ_USER_WIDTH = 183;
+parameter AXIS_PCIE_CC_USER_WIDTH = 81;
+
+// Clock and reset
+wire pcie_user_clk;
+wire pcie_user_reset;
+
+// GPIO
+wire [3:0] sw_int;
+
+debounce_switch #(
+    .WIDTH(4),
+    .N(4),
+    .RATE(250000)
+)
+debounce_switch_inst (
+    .clk(pcie_user_clk),
+    .rst(pcie_user_reset),
+    .in({sw}),
+    .out({sw_int})
+);
+
+// PCIe
+wire pcie_sys_clk;
+wire pcie_sys_clk_gt;
+
+IBUFDS_GTE4 #(
+    .REFCLK_HROW_CK_SEL(2'b00)
+)
+ibufds_gte4_pcie_mgt_refclk_inst (
+    .I             (pcie_refclk_p),
+    .IB            (pcie_refclk_n),
+    .CEB           (1'b0),
+    .O             (pcie_sys_clk_gt),
+    .ODIV2         (pcie_sys_clk)
+);
+
+wire [AXIS_PCIE_DATA_WIDTH-1:0]    axis_rq_tdata;
+wire [AXIS_PCIE_KEEP_WIDTH-1:0]    axis_rq_tkeep;
+wire                               axis_rq_tlast;
+wire                               axis_rq_tready;
+wire [AXIS_PCIE_RQ_USER_WIDTH-1:0] axis_rq_tuser;
+wire                               axis_rq_tvalid;
+
+wire [AXIS_PCIE_DATA_WIDTH-1:0]    axis_rc_tdata;
+wire [AXIS_PCIE_KEEP_WIDTH-1:0]    axis_rc_tkeep;
+wire                               axis_rc_tlast;
+wire                               axis_rc_tready;
+wire [AXIS_PCIE_RC_USER_WIDTH-1:0] axis_rc_tuser;
+wire                               axis_rc_tvalid;
+
+wire [AXIS_PCIE_DATA_WIDTH-1:0]    axis_cq_tdata;
+wire [AXIS_PCIE_KEEP_WIDTH-1:0]    axis_cq_tkeep;
+wire                               axis_cq_tlast;
+wire                               axis_cq_tready;
+wire [AXIS_PCIE_CQ_USER_WIDTH-1:0] axis_cq_tuser;
+wire                               axis_cq_tvalid;
+
+wire [AXIS_PCIE_DATA_WIDTH-1:0]    axis_cc_tdata;
+wire [AXIS_PCIE_KEEP_WIDTH-1:0]    axis_cc_tkeep;
+wire                               axis_cc_tlast;
+wire                               axis_cc_tready;
+wire [AXIS_PCIE_CC_USER_WIDTH-1:0] axis_cc_tuser;
+wire                               axis_cc_tvalid;
+
+// ila_0 rq_ila (
+//     .clk(pcie_user_clk),
+//     .probe0(axis_rq_tdata),
+//     .probe1(axis_rq_tkeep),
+//     .probe2(axis_rq_tlast),
+//     .probe3(axis_rq_tready),
+//     .probe4(axis_rq_tuser),
+//     .probe5(axis_rq_tvalid)
+// );
+
+// ila_0 rc_ila (
+//     .clk(pcie_user_clk),
+//     .probe0(axis_rc_tdata),
+//     .probe1(axis_rc_tkeep),
+//     .probe2(axis_rc_tlast),
+//     .probe3(axis_rc_tready),
+//     .probe4(axis_rc_tuser),
+//     .probe5(axis_rc_tvalid)
+// );
+
+wire [2:0] cfg_max_payload;
+wire [2:0] cfg_max_read_req;
+
+wire [9:0]  cfg_mgmt_addr;
+wire [7:0]  cfg_mgmt_function_number;
+wire        cfg_mgmt_write;
+wire [31:0] cfg_mgmt_write_data;
+wire [3:0]  cfg_mgmt_byte_enable;
+wire        cfg_mgmt_read;
+wire [31:0] cfg_mgmt_read_data;
+wire        cfg_mgmt_read_write_done;
+
+wire [3:0]  cfg_interrupt_msi_enable;
+wire [11:0] cfg_interrupt_msi_mmenable;
+wire        cfg_interrupt_msi_mask_update;
+wire [31:0] cfg_interrupt_msi_data;
+wire [3:0]  cfg_interrupt_msi_select;
+wire [31:0] cfg_interrupt_msi_int;
+wire [31:0] cfg_interrupt_msi_pending_status;
+wire        cfg_interrupt_msi_pending_status_data_enable;
+wire [3:0]  cfg_interrupt_msi_pending_status_function_num;
+wire        cfg_interrupt_msi_sent;
+wire        cfg_interrupt_msi_fail;
+wire [2:0]  cfg_interrupt_msi_attr;
+wire        cfg_interrupt_msi_tph_present;
+wire [1:0]  cfg_interrupt_msi_tph_type;
+wire [8:0]  cfg_interrupt_msi_tph_st_tag;
+wire [3:0]  cfg_interrupt_msi_function_number;
+
+wire status_error_cor;
+wire status_error_uncor;
+
+pcie4_uscale_plus_0
+pcie4_uscale_plus_inst (
+    .pci_exp_txn(pcie_tx_n),
+    .pci_exp_txp(pcie_tx_p),
+    .pci_exp_rxn(pcie_rx_n),
+    .pci_exp_rxp(pcie_rx_p),
+    .user_clk(pcie_user_clk),
+    .user_reset(pcie_user_reset),
+    .user_lnk_up(),
+
+    .s_axis_rq_tdata(axis_rq_tdata),
+    .s_axis_rq_tkeep(axis_rq_tkeep),
+    .s_axis_rq_tlast(axis_rq_tlast),
+    .s_axis_rq_tready(axis_rq_tready),
+    .s_axis_rq_tuser(axis_rq_tuser),
+    .s_axis_rq_tvalid(axis_rq_tvalid),
+
+    .m_axis_rc_tdata(axis_rc_tdata),
+    .m_axis_rc_tkeep(axis_rc_tkeep),
+    .m_axis_rc_tlast(axis_rc_tlast),
+    .m_axis_rc_tready(axis_rc_tready),
+    .m_axis_rc_tuser(axis_rc_tuser),
+    .m_axis_rc_tvalid(axis_rc_tvalid),
+
+    .m_axis_cq_tdata(axis_cq_tdata),
+    .m_axis_cq_tkeep(axis_cq_tkeep),
+    .m_axis_cq_tlast(axis_cq_tlast),
+    .m_axis_cq_tready(axis_cq_tready),
+    .m_axis_cq_tuser(axis_cq_tuser),
+    .m_axis_cq_tvalid(axis_cq_tvalid),
+
+    .s_axis_cc_tdata(axis_cc_tdata),
+    .s_axis_cc_tkeep(axis_cc_tkeep),
+    .s_axis_cc_tlast(axis_cc_tlast),
+    .s_axis_cc_tready(axis_cc_tready),
+    .s_axis_cc_tuser(axis_cc_tuser),
+    .s_axis_cc_tvalid(axis_cc_tvalid),
+
+    .pcie_rq_seq_num0(),
+    .pcie_rq_seq_num_vld0(),
+    .pcie_rq_seq_num1(),
+    .pcie_rq_seq_num_vld1(),
+    .pcie_rq_tag0(),
+    .pcie_rq_tag1(),
+    .pcie_rq_tag_av(),
+    .pcie_rq_tag_vld0(),
+    .pcie_rq_tag_vld1(),
+
+    .pcie_tfc_nph_av(),
+    .pcie_tfc_npd_av(),
+
+    .pcie_cq_np_req(1'b1),
+    .pcie_cq_np_req_count(),
+
+    .cfg_phy_link_down(),
+    .cfg_phy_link_status(),
+    .cfg_negotiated_width(),
+    .cfg_current_speed(),
+    .cfg_max_payload(cfg_max_payload),
+    .cfg_max_read_req(cfg_max_read_req),
+    .cfg_function_status(),
+    .cfg_function_power_state(),
+    .cfg_vf_status(),
+    .cfg_vf_power_state(),
+    .cfg_link_power_state(),
+
+    .cfg_mgmt_addr(cfg_mgmt_addr),
+    .cfg_mgmt_function_number(cfg_mgmt_function_number),
+    .cfg_mgmt_write(cfg_mgmt_write),
+    .cfg_mgmt_write_data(cfg_mgmt_write_data),
+    .cfg_mgmt_byte_enable(cfg_mgmt_byte_enable),
+    .cfg_mgmt_read(cfg_mgmt_read),
+    .cfg_mgmt_read_data(cfg_mgmt_read_data),
+    .cfg_mgmt_read_write_done(cfg_mgmt_read_write_done),
+    .cfg_mgmt_debug_access(1'b0),
+
+    .cfg_err_cor_out(),
+    .cfg_err_nonfatal_out(),
+    .cfg_err_fatal_out(),
+    .cfg_local_error_valid(),
+    .cfg_local_error_out(),
+    .cfg_ltssm_state(),
+    .cfg_rx_pm_state(),
+    .cfg_tx_pm_state(),
+    .cfg_rcb_status(),
+    .cfg_obff_enable(),
+    .cfg_pl_status_change(),
+    .cfg_tph_requester_enable(),
+    .cfg_tph_st_mode(),
+    .cfg_vf_tph_requester_enable(),
+    .cfg_vf_tph_st_mode(),
+
+    .cfg_msg_received(),
+    .cfg_msg_received_data(),
+    .cfg_msg_received_type(),
+    .cfg_msg_transmit(1'b0),
+    .cfg_msg_transmit_type(3'd0),
+    .cfg_msg_transmit_data(32'd0),
+    .cfg_msg_transmit_done(),
+
+    .cfg_fc_ph(),
+    .cfg_fc_pd(),
+    .cfg_fc_nph(),
+    .cfg_fc_npd(),
+    .cfg_fc_cplh(),
+    .cfg_fc_cpld(),
+    .cfg_fc_sel(3'd0),
+
+    .cfg_dsn(64'd0),
+
+    .cfg_bus_number(),
+
+    .cfg_power_state_change_ack(1'b1),
+    .cfg_power_state_change_interrupt(),
+
+    .cfg_err_cor_in(status_error_cor),
+    .cfg_err_uncor_in(status_error_uncor),
+    .cfg_flr_in_process(),
+    .cfg_flr_done(4'd0),
+    .cfg_vf_flr_in_process(),
+    .cfg_vf_flr_func_num(8'd0),
+    .cfg_vf_flr_done(8'd0),
+
+    .cfg_link_training_enable(1'b1),
+
+    .cfg_interrupt_int(4'd0),
+    .cfg_interrupt_pending(4'd0),
+    .cfg_interrupt_sent(),
+    .cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
+    .cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
+    .cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
+    .cfg_interrupt_msi_data(cfg_interrupt_msi_data),
+    .cfg_interrupt_msi_select(cfg_interrupt_msi_select),
+    .cfg_interrupt_msi_int(cfg_interrupt_msi_int),
+    .cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
+    .cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
+    .cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
+    .cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
+    .cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
+    .cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
+    .cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
+    .cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
+    .cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
+    .cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
+
+    .cfg_pm_aspm_l1_entry_reject(1'b0),
+    .cfg_pm_aspm_tx_l0s_entry_disable(1'b0),
+
+    .cfg_hot_reset_out(),
+
+    .cfg_config_space_enable(1'b1),
+    .cfg_req_pm_transition_l23_ready(1'b0),
+    .cfg_hot_reset_in(1'b0),
+
+    .cfg_ds_port_number(8'd0),
+    .cfg_ds_bus_number(8'd0),
+    .cfg_ds_device_number(5'd0),
+    //.cfg_ds_function_number(3'd0),
+
+    //.cfg_subsys_vend_id(16'h1234),
+
+    .sys_clk(pcie_sys_clk),
+    .sys_clk_gt(pcie_sys_clk_gt),
+    .sys_reset(pcie_reset_n),
+
+    .phy_rdy_out()
+);
+
+fpga_core #(
+    .AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
+    .AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
+    .AXIS_PCIE_RC_USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH),
+    .AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH),
+    .AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH),
+    .AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH)
+)
+core_inst (
+    /*
+     * Clock: 250 MHz
+     * Synchronous reset
+     */
+    .clk(pcie_user_clk),
+    .rst(pcie_user_reset),
+    /*
+     * GPIO
+     */
+    .sw(sw_int),
+    .led(led),
+    /*
+     * PCIe
+     */
+    .m_axis_rq_tdata(axis_rq_tdata),
+    .m_axis_rq_tkeep(axis_rq_tkeep),
+    .m_axis_rq_tlast(axis_rq_tlast),
+    .m_axis_rq_tready(axis_rq_tready),
+    .m_axis_rq_tuser(axis_rq_tuser),
+    .m_axis_rq_tvalid(axis_rq_tvalid),
+
+    .s_axis_rc_tdata(axis_rc_tdata),
+    .s_axis_rc_tkeep(axis_rc_tkeep),
+    .s_axis_rc_tlast(axis_rc_tlast),
+    .s_axis_rc_tready(axis_rc_tready),
+    .s_axis_rc_tuser(axis_rc_tuser),
+    .s_axis_rc_tvalid(axis_rc_tvalid),
+
+    .s_axis_cq_tdata(axis_cq_tdata),
+    .s_axis_cq_tkeep(axis_cq_tkeep),
+    .s_axis_cq_tlast(axis_cq_tlast),
+    .s_axis_cq_tready(axis_cq_tready),
+    .s_axis_cq_tuser(axis_cq_tuser),
+    .s_axis_cq_tvalid(axis_cq_tvalid),
+
+    .m_axis_cc_tdata(axis_cc_tdata),
+    .m_axis_cc_tkeep(axis_cc_tkeep),
+    .m_axis_cc_tlast(axis_cc_tlast),
+    .m_axis_cc_tready(axis_cc_tready),
+    .m_axis_cc_tuser(axis_cc_tuser),
+    .m_axis_cc_tvalid(axis_cc_tvalid),
+
+    .cfg_max_payload(cfg_max_payload),
+    .cfg_max_read_req(cfg_max_read_req),
+    
+    .cfg_mgmt_addr(cfg_mgmt_addr),
+    .cfg_mgmt_function_number(cfg_mgmt_function_number),
+    .cfg_mgmt_write(cfg_mgmt_write),
+    .cfg_mgmt_write_data(cfg_mgmt_write_data),
+    .cfg_mgmt_byte_enable(cfg_mgmt_byte_enable),
+    .cfg_mgmt_read(cfg_mgmt_read),
+    .cfg_mgmt_read_data(cfg_mgmt_read_data),
+    .cfg_mgmt_read_write_done(cfg_mgmt_read_write_done),
+
+    .cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
+    .cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
+    .cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
+    .cfg_interrupt_msi_data(cfg_interrupt_msi_data),
+    .cfg_interrupt_msi_select(cfg_interrupt_msi_select),
+    .cfg_interrupt_msi_int(cfg_interrupt_msi_int),
+    .cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
+    .cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
+    .cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
+    .cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
+    .cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
+    .cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
+    .cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
+    .cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
+    .cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
+    .cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
+
+    .status_error_cor(status_error_cor),
+    .status_error_uncor(status_error_uncor)
+);
+
+endmodule
+
+`resetall

snapshots/alexforencich_verilog-pcie_pr20/example/AU250/fpga_axi/rtl/fpga_core.v

@@ -0,0 +1,1123 @@
+/*
+
+Copyright (c) 2018 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog 2001
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * FPGA core logic
+ */
+module fpga_core #
+(
+    parameter AXIS_PCIE_DATA_WIDTH = 512,
+    parameter AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32),
+    parameter AXIS_PCIE_RC_USER_WIDTH = 161,
+    parameter AXIS_PCIE_RQ_USER_WIDTH = 137,
+    parameter AXIS_PCIE_CQ_USER_WIDTH = 183,
+    parameter AXIS_PCIE_CC_USER_WIDTH = 81
+)
+(
+    /*
+     * Clock: 250 MHz
+     * Synchronous reset
+     */
+    input  wire                               clk,
+    input  wire                               rst,
+
+    /*
+     * GPIO
+     */
+    input  wire [3:0]                         sw,
+    output wire [2:0]                         led,
+
+    /*
+     * PCIe
+     */
+    output wire [AXIS_PCIE_DATA_WIDTH-1:0]    m_axis_rq_tdata,
+    output wire [AXIS_PCIE_KEEP_WIDTH-1:0]    m_axis_rq_tkeep,
+    output wire                               m_axis_rq_tlast,
+    input  wire                               m_axis_rq_tready,
+    output wire [AXIS_PCIE_RQ_USER_WIDTH-1:0] m_axis_rq_tuser,
+    output wire                               m_axis_rq_tvalid,
+
+    input  wire [AXIS_PCIE_DATA_WIDTH-1:0]    s_axis_rc_tdata,
+    input  wire [AXIS_PCIE_KEEP_WIDTH-1:0]    s_axis_rc_tkeep,
+    input  wire                               s_axis_rc_tlast,
+    output wire                               s_axis_rc_tready,
+    input  wire [AXIS_PCIE_RC_USER_WIDTH-1:0] s_axis_rc_tuser,
+    input  wire                               s_axis_rc_tvalid,
+
+    input  wire [AXIS_PCIE_DATA_WIDTH-1:0]    s_axis_cq_tdata,
+    input  wire [AXIS_PCIE_KEEP_WIDTH-1:0]    s_axis_cq_tkeep,
+    input  wire                               s_axis_cq_tlast,
+    output wire                               s_axis_cq_tready,
+    input  wire [AXIS_PCIE_CQ_USER_WIDTH-1:0] s_axis_cq_tuser,
+    input  wire                               s_axis_cq_tvalid,
+
+    output wire [AXIS_PCIE_DATA_WIDTH-1:0]    m_axis_cc_tdata,
+    output wire [AXIS_PCIE_KEEP_WIDTH-1:0]    m_axis_cc_tkeep,
+    output wire                               m_axis_cc_tlast,
+    input  wire                               m_axis_cc_tready,
+    output wire [AXIS_PCIE_CC_USER_WIDTH-1:0] m_axis_cc_tuser,
+    output wire                               m_axis_cc_tvalid,
+
+    input  wire [2:0]                         cfg_max_payload,
+    input  wire [2:0]                         cfg_max_read_req,
+
+    output wire [9:0]                         cfg_mgmt_addr,
+    output wire [7:0]                         cfg_mgmt_function_number,
+    output wire                               cfg_mgmt_write,
+    output wire [31:0]                        cfg_mgmt_write_data,
+    output wire [3:0]                         cfg_mgmt_byte_enable,
+    output wire                               cfg_mgmt_read,
+    input  wire [31:0]                        cfg_mgmt_read_data,
+    input  wire                               cfg_mgmt_read_write_done,
+
+    input  wire [3:0]                         cfg_interrupt_msi_enable,
+    input  wire [11:0]                        cfg_interrupt_msi_mmenable,
+    input  wire                               cfg_interrupt_msi_mask_update,
+    input  wire [31:0]                        cfg_interrupt_msi_data,
+    output wire [3:0]                         cfg_interrupt_msi_select,
+    output wire [31:0]                        cfg_interrupt_msi_int,
+    output wire [31:0]                        cfg_interrupt_msi_pending_status,
+    output wire                               cfg_interrupt_msi_pending_status_data_enable,
+    output wire [3:0]                         cfg_interrupt_msi_pending_status_function_num,
+    input  wire                               cfg_interrupt_msi_sent,
+    input  wire                               cfg_interrupt_msi_fail,
+    output wire [2:0]                         cfg_interrupt_msi_attr,
+    output wire                               cfg_interrupt_msi_tph_present,
+    output wire [1:0]                         cfg_interrupt_msi_tph_type,
+    output wire [8:0]                         cfg_interrupt_msi_tph_st_tag,
+    output wire [3:0]                         cfg_interrupt_msi_function_number,
+
+    output wire                               status_error_cor,
+    output wire                               status_error_uncor
+);
+
+parameter PCIE_ADDR_WIDTH = 64;
+
+parameter AXIL_DATA_WIDTH = 32;
+parameter AXIL_STRB_WIDTH = (AXIL_DATA_WIDTH/8);
+parameter AXIL_ADDR_WIDTH = 32;
+
+parameter AXI_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH;
+parameter AXI_STRB_WIDTH = (AXI_DATA_WIDTH/8);
+parameter AXI_ADDR_WIDTH = 32;
+parameter AXI_ID_WIDTH = 8;
+
+parameter DMA_TAG_WIDTH = 8;
+
+// Completer mux/demux
+wire [AXIS_PCIE_DATA_WIDTH-1:0]    axis_cq_tdata_bar_0;
+wire [AXIS_PCIE_KEEP_WIDTH-1:0]    axis_cq_tkeep_bar_0;
+wire                               axis_cq_tvalid_bar_0;
+wire                               axis_cq_tready_bar_0;
+wire                               axis_cq_tlast_bar_0;
+wire [AXIS_PCIE_CQ_USER_WIDTH-1:0] axis_cq_tuser_bar_0;
+
+wire [AXIS_PCIE_DATA_WIDTH-1:0]    axis_cc_tdata_bar_0;
+wire [AXIS_PCIE_KEEP_WIDTH-1:0]    axis_cc_tkeep_bar_0;
+wire                               axis_cc_tvalid_bar_0;
+wire                               axis_cc_tready_bar_0;
+wire                               axis_cc_tlast_bar_0;
+wire [AXIS_PCIE_CC_USER_WIDTH-1:0] axis_cc_tuser_bar_0;
+
+wire [AXIS_PCIE_DATA_WIDTH-1:0]    axis_cq_tdata_bar_2;
+wire [AXIS_PCIE_KEEP_WIDTH-1:0]    axis_cq_tkeep_bar_2;
+wire                               axis_cq_tvalid_bar_2;
+wire                               axis_cq_tready_bar_2;
+wire                               axis_cq_tlast_bar_2;
+wire [AXIS_PCIE_CQ_USER_WIDTH-1:0] axis_cq_tuser_bar_2;
+
+wire [AXIS_PCIE_DATA_WIDTH-1:0]    axis_cc_tdata_bar_2;
+wire [AXIS_PCIE_KEEP_WIDTH-1:0]    axis_cc_tkeep_bar_2;
+wire                               axis_cc_tvalid_bar_2;
+wire                               axis_cc_tready_bar_2;
+wire                               axis_cc_tlast_bar_2;
+wire [AXIS_PCIE_CC_USER_WIDTH-1:0] axis_cc_tuser_bar_2;
+
+wire [2:0] bar_id;
+wire [1:0] select;
+
+pcie_us_axis_cq_demux #(
+    .M_COUNT(2),
+    .AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
+    .AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
+    .AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH)
+)
+cq_demux_inst (
+    .clk(clk),
+    .rst(rst),
+
+    /*
+     * AXI input (CQ)
+     */
+    .s_axis_cq_tdata(s_axis_cq_tdata),
+    .s_axis_cq_tkeep(s_axis_cq_tkeep),
+    .s_axis_cq_tvalid(s_axis_cq_tvalid),
+    .s_axis_cq_tready(s_axis_cq_tready),
+    .s_axis_cq_tlast(s_axis_cq_tlast),
+    .s_axis_cq_tuser(s_axis_cq_tuser),
+
+    /*
+     * AXI output (CQ)
+     */
+    .m_axis_cq_tdata({axis_cq_tdata_bar_2, axis_cq_tdata_bar_0}),
+    .m_axis_cq_tkeep({axis_cq_tkeep_bar_2, axis_cq_tkeep_bar_0}),
+    .m_axis_cq_tvalid({axis_cq_tvalid_bar_2, axis_cq_tvalid_bar_0}),
+    .m_axis_cq_tready({axis_cq_tready_bar_2, axis_cq_tready_bar_0}),
+    .m_axis_cq_tlast({axis_cq_tlast_bar_2, axis_cq_tlast_bar_0}),
+    .m_axis_cq_tuser({axis_cq_tuser_bar_2, axis_cq_tuser_bar_0}),
+
+    /*
+     * Fields
+     */
+    .req_type(),
+    .target_function(),
+    .bar_id(bar_id),
+    .msg_code(),
+    .msg_routing(),
+
+    /*
+     * Control
+     */
+    .enable(1),
+    .drop(0),
+    .select(select)
+);
+
+assign select[1] = bar_id == 3'd2;
+assign select[0] = bar_id == 3'd0;
+
+axis_arb_mux #(
+    .S_COUNT(2),
+    .DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
+    .KEEP_ENABLE(1),
+    .KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
+    .ID_ENABLE(0),
+    .DEST_ENABLE(0),
+    .USER_ENABLE(1),
+    .USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH)
+)
+cc_mux_inst (
+    .clk(clk),
+    .rst(rst),
+
+    /*
+     * AXI inputs
+     */
+    .s_axis_tdata({axis_cc_tdata_bar_2, axis_cc_tdata_bar_0}),
+    .s_axis_tkeep({axis_cc_tkeep_bar_2, axis_cc_tkeep_bar_0}),
+    .s_axis_tvalid({axis_cc_tvalid_bar_2, axis_cc_tvalid_bar_0}),
+    .s_axis_tready({axis_cc_tready_bar_2, axis_cc_tready_bar_0}),
+    .s_axis_tlast({axis_cc_tlast_bar_2, axis_cc_tlast_bar_0}),
+    .s_axis_tid(0),
+    .s_axis_tdest(0),
+    .s_axis_tuser({axis_cc_tuser_bar_2, axis_cc_tuser_bar_0}),
+
+    /*
+     * AXI output
+     */
+    .m_axis_tdata(m_axis_cc_tdata),
+    .m_axis_tkeep(m_axis_cc_tkeep),
+    .m_axis_tvalid(m_axis_cc_tvalid),
+    .m_axis_tready(m_axis_cc_tready),
+    .m_axis_tlast(m_axis_cc_tlast),
+    .m_axis_tid(),
+    .m_axis_tdest(),
+    .m_axis_tuser(m_axis_cc_tuser)
+);
+
+wire [AXIL_ADDR_WIDTH-1:0] axil_ctrl_awaddr;
+wire [2:0]                 axil_ctrl_awprot;
+wire                       axil_ctrl_awvalid;
+wire                       axil_ctrl_awready;
+wire [AXIL_DATA_WIDTH-1:0] axil_ctrl_wdata;
+wire [AXIL_STRB_WIDTH-1:0] axil_ctrl_wstrb;
+wire                       axil_ctrl_wvalid;
+wire                       axil_ctrl_wready;
+wire [1:0]                 axil_ctrl_bresp;
+wire                       axil_ctrl_bvalid;
+wire                       axil_ctrl_bready;
+wire [AXIL_ADDR_WIDTH-1:0] axil_ctrl_araddr;
+wire [2:0]                 axil_ctrl_arprot;
+wire                       axil_ctrl_arvalid;
+wire                       axil_ctrl_arready;
+wire [AXIL_DATA_WIDTH-1:0] axil_ctrl_rdata;
+wire [1:0]                 axil_ctrl_rresp;
+wire                       axil_ctrl_rvalid;
+wire                       axil_ctrl_rready;
+
+wire [AXI_ID_WIDTH-1:0]    axi_awid;
+wire [AXI_ADDR_WIDTH-1:0]  axi_awaddr;
+wire [7:0]                 axi_awlen;
+wire [2:0]                 axi_awsize;
+wire [1:0]                 axi_awburst;
+wire                       axi_awlock;
+wire [3:0]                 axi_awcache;
+wire [2:0]                 axi_awprot;
+wire                       axi_awvalid;
+wire                       axi_awready;
+wire [AXI_DATA_WIDTH-1:0]  axi_wdata;
+wire [AXI_STRB_WIDTH-1:0]  axi_wstrb;
+wire                       axi_wlast;
+wire                       axi_wvalid;
+wire                       axi_wready;
+wire [AXI_ID_WIDTH-1:0]    axi_bid;
+wire [1:0]                 axi_bresp;
+wire                       axi_bvalid;
+wire                       axi_bready;
+wire [AXI_ID_WIDTH-1:0]    axi_arid;
+wire [AXI_ADDR_WIDTH-1:0]  axi_araddr;
+wire [7:0]                 axi_arlen;
+wire [2:0]                 axi_arsize;
+wire [1:0]                 axi_arburst;
+wire                       axi_arlock;
+wire [3:0]                 axi_arcache;
+wire [2:0]                 axi_arprot;
+wire                       axi_arvalid;
+wire                       axi_arready;
+wire [AXI_ID_WIDTH-1:0]    axi_rid;
+wire [AXI_DATA_WIDTH-1:0]  axi_rdata;
+wire [1:0]                 axi_rresp;
+wire                       axi_rlast;
+wire                       axi_rvalid;
+wire                       axi_rready;
+
+wire [AXI_ID_WIDTH-1:0]    axi_dma_awid;
+wire [AXI_ADDR_WIDTH-1:0]  axi_dma_awaddr;
+wire [7:0]                 axi_dma_awlen;
+wire [2:0]                 axi_dma_awsize;
+wire [1:0]                 axi_dma_awburst;
+wire                       axi_dma_awlock;
+wire [3:0]                 axi_dma_awcache;
+wire [2:0]                 axi_dma_awprot;
+wire                       axi_dma_awvalid;
+wire                       axi_dma_awready;
+wire [AXI_DATA_WIDTH-1:0]  axi_dma_wdata;
+wire [AXI_STRB_WIDTH-1:0]  axi_dma_wstrb;
+wire                       axi_dma_wlast;
+wire                       axi_dma_wvalid;
+wire                       axi_dma_wready;
+wire [AXI_ID_WIDTH-1:0]    axi_dma_bid;
+wire [1:0]                 axi_dma_bresp;
+wire                       axi_dma_bvalid;
+wire                       axi_dma_bready;
+wire [AXI_ID_WIDTH-1:0]    axi_dma_arid;
+wire [AXI_ADDR_WIDTH-1:0]  axi_dma_araddr;
+wire [7:0]                 axi_dma_arlen;
+wire [2:0]                 axi_dma_arsize;
+wire [1:0]                 axi_dma_arburst;
+wire                       axi_dma_arlock;
+wire [3:0]                 axi_dma_arcache;
+wire [2:0]                 axi_dma_arprot;
+wire                       axi_dma_arvalid;
+wire                       axi_dma_arready;
+wire [AXI_ID_WIDTH-1:0]    axi_dma_rid;
+wire [AXI_DATA_WIDTH-1:0]  axi_dma_rdata;
+wire [1:0]                 axi_dma_rresp;
+wire                       axi_dma_rlast;
+wire                       axi_dma_rvalid;
+wire                       axi_dma_rready;
+
+// PCIe DMA control
+wire [PCIE_ADDR_WIDTH-1:0] pcie_dma_read_desc_pcie_addr;
+wire [AXI_ADDR_WIDTH-1:0]  pcie_dma_read_desc_axi_addr;
+wire [15:0]                pcie_dma_read_desc_len;
+wire [DMA_TAG_WIDTH-1:0]   pcie_dma_read_desc_tag;
+wire                       pcie_dma_read_desc_valid;
+wire                       pcie_dma_read_desc_ready;
+
+wire [DMA_TAG_WIDTH-1:0]   pcie_dma_read_desc_status_tag;
+wire [3:0]                 pcie_dma_read_desc_status_error;
+wire                       pcie_dma_read_desc_status_valid;
+
+wire [PCIE_ADDR_WIDTH-1:0] pcie_dma_write_desc_pcie_addr;
+wire [AXI_ADDR_WIDTH-1:0]  pcie_dma_write_desc_axi_addr;
+wire [15:0]                pcie_dma_write_desc_len;
+wire [DMA_TAG_WIDTH-1:0]   pcie_dma_write_desc_tag;
+wire                       pcie_dma_write_desc_valid;
+wire                       pcie_dma_write_desc_ready;
+
+wire [DMA_TAG_WIDTH-1:0]   pcie_dma_write_desc_status_tag;
+wire [3:0]                 pcie_dma_write_desc_status_error;
+wire                       pcie_dma_write_desc_status_valid;
+
+wire                       pcie_dma_enable;
+
+// Error handling
+wire [2:0] status_error_uncor_int;
+wire [2:0] status_error_cor_int;
+
+wire [31:0] msi_irq;
+
+wire ext_tag_enable;
+
+// control registers
+reg axil_ctrl_awready_reg = 1'b0, axil_ctrl_awready_next;
+reg axil_ctrl_wready_reg = 1'b0, axil_ctrl_wready_next;
+reg [1:0] axil_ctrl_bresp_reg = 2'b00, axil_ctrl_bresp_next;
+reg axil_ctrl_bvalid_reg = 1'b0, axil_ctrl_bvalid_next;
+reg axil_ctrl_arready_reg = 1'b0, axil_ctrl_arready_next;
+reg [AXIL_DATA_WIDTH-1:0] axil_ctrl_rdata_reg = {AXIL_DATA_WIDTH{1'b0}}, axil_ctrl_rdata_next;
+reg [1:0] axil_ctrl_rresp_reg = 2'b00, axil_ctrl_rresp_next;
+reg axil_ctrl_rvalid_reg = 1'b0, axil_ctrl_rvalid_next;
+
+reg [PCIE_ADDR_WIDTH-1:0] pcie_dma_read_desc_pcie_addr_reg = 0, pcie_dma_read_desc_pcie_addr_next;
+reg [AXI_ADDR_WIDTH-1:0] pcie_dma_read_desc_axi_addr_reg = 0, pcie_dma_read_desc_axi_addr_next;
+reg [15:0] pcie_dma_read_desc_len_reg = 0, pcie_dma_read_desc_len_next;
+reg [DMA_TAG_WIDTH-1:0] pcie_dma_read_desc_tag_reg = 0, pcie_dma_read_desc_tag_next;
+reg pcie_dma_read_desc_valid_reg = 0, pcie_dma_read_desc_valid_next;
+
+reg [DMA_TAG_WIDTH-1:0] pcie_dma_read_desc_status_tag_reg = 0, pcie_dma_read_desc_status_tag_next;
+reg [31:0] pcie_dma_read_desc_status_error_reg = 0, pcie_dma_read_desc_status_error_next;
+reg pcie_dma_read_desc_status_valid_reg = 0, pcie_dma_read_desc_status_valid_next;
+
+reg [PCIE_ADDR_WIDTH-1:0] pcie_dma_write_desc_pcie_addr_reg = 0, pcie_dma_write_desc_pcie_addr_next;
+reg [AXI_ADDR_WIDTH-1:0] pcie_dma_write_desc_axi_addr_reg = 0, pcie_dma_write_desc_axi_addr_next;
+reg [15:0] pcie_dma_write_desc_len_reg = 0, pcie_dma_write_desc_len_next;
+reg [DMA_TAG_WIDTH-1:0] pcie_dma_write_desc_tag_reg = 0, pcie_dma_write_desc_tag_next;
+reg pcie_dma_write_desc_valid_reg = 0, pcie_dma_write_desc_valid_next;
+
+reg [DMA_TAG_WIDTH-1:0] pcie_dma_write_desc_status_tag_reg = 0, pcie_dma_write_desc_status_tag_next;
+reg [31:0] pcie_dma_write_desc_status_error_reg = 0, pcie_dma_write_desc_status_error_next;
+reg pcie_dma_write_desc_status_valid_reg = 0, pcie_dma_write_desc_status_valid_next;
+
+reg pcie_dma_enable_reg = 0, pcie_dma_enable_next;
+
+reg [31:0] pcie_rq_count_reg = 0;
+reg [31:0] pcie_rc_count_reg = 0;
+reg [31:0] pcie_cq_count_reg = 0;
+reg [31:0] pcie_cc_count_reg = 0;
+
+assign axil_ctrl_awready = axil_ctrl_awready_reg;
+assign axil_ctrl_wready = axil_ctrl_wready_reg;
+assign axil_ctrl_bresp = axil_ctrl_bresp_reg;
+assign axil_ctrl_bvalid = axil_ctrl_bvalid_reg;
+assign axil_ctrl_arready = axil_ctrl_arready_reg;
+assign axil_ctrl_rdata = axil_ctrl_rdata_reg;
+assign axil_ctrl_rresp = axil_ctrl_rresp_reg;
+assign axil_ctrl_rvalid = axil_ctrl_rvalid_reg;
+
+assign pcie_dma_read_desc_pcie_addr = pcie_dma_read_desc_pcie_addr_reg;
+assign pcie_dma_read_desc_axi_addr = pcie_dma_read_desc_axi_addr_reg;
+assign pcie_dma_read_desc_len = pcie_dma_read_desc_len_reg;
+assign pcie_dma_read_desc_tag = pcie_dma_read_desc_tag_reg;
+assign pcie_dma_read_desc_valid = pcie_dma_read_desc_valid_reg;
+assign pcie_dma_write_desc_pcie_addr = pcie_dma_write_desc_pcie_addr_reg;
+assign pcie_dma_write_desc_axi_addr = pcie_dma_write_desc_axi_addr_reg;
+assign pcie_dma_write_desc_len = pcie_dma_write_desc_len_reg;
+assign pcie_dma_write_desc_tag = pcie_dma_write_desc_tag_reg;
+assign pcie_dma_write_desc_valid = pcie_dma_write_desc_valid_reg;
+assign pcie_dma_enable = pcie_dma_enable_reg;
+
+assign msi_irq[0] = pcie_dma_read_desc_status_valid || pcie_dma_write_desc_status_valid;
+assign msi_irq[31:1] = 0;
+
+always @* begin
+    axil_ctrl_awready_next = 1'b0;
+    axil_ctrl_wready_next = 1'b0;
+    axil_ctrl_bresp_next = 2'b00;
+    axil_ctrl_bvalid_next = axil_ctrl_bvalid_reg && !axil_ctrl_bready;
+    axil_ctrl_arready_next = 1'b0;
+    axil_ctrl_rdata_next = {AXIL_DATA_WIDTH{1'b0}};
+    axil_ctrl_rresp_next = 2'b00;
+    axil_ctrl_rvalid_next = axil_ctrl_rvalid_reg && !axil_ctrl_rready;
+
+    pcie_dma_read_desc_pcie_addr_next = pcie_dma_read_desc_pcie_addr_reg;
+    pcie_dma_read_desc_axi_addr_next = pcie_dma_read_desc_axi_addr_reg;
+    pcie_dma_read_desc_len_next = pcie_dma_read_desc_len_reg;
+    pcie_dma_read_desc_tag_next = pcie_dma_read_desc_tag_reg;
+    pcie_dma_read_desc_valid_next = pcie_dma_read_desc_valid_reg && !pcie_dma_read_desc_ready;
+
+    pcie_dma_read_desc_status_tag_next = pcie_dma_read_desc_status_tag_reg;
+    pcie_dma_read_desc_status_error_next = pcie_dma_read_desc_status_error_reg;
+    pcie_dma_read_desc_status_valid_next = pcie_dma_read_desc_status_valid_reg;
+
+    pcie_dma_write_desc_pcie_addr_next = pcie_dma_write_desc_pcie_addr_reg;
+    pcie_dma_write_desc_axi_addr_next = pcie_dma_write_desc_axi_addr_reg;
+    pcie_dma_write_desc_len_next = pcie_dma_write_desc_len_reg;
+    pcie_dma_write_desc_tag_next = pcie_dma_write_desc_tag_reg;
+    pcie_dma_write_desc_valid_next = pcie_dma_write_desc_valid_reg && !pcie_dma_read_desc_ready;
+
+    pcie_dma_write_desc_status_tag_next = pcie_dma_write_desc_status_tag_reg;
+    pcie_dma_write_desc_status_error_next = pcie_dma_write_desc_status_error_reg;
+    pcie_dma_write_desc_status_valid_next = pcie_dma_write_desc_status_valid_reg;
+
+    pcie_dma_enable_next = pcie_dma_enable_reg;
+
+    if (axil_ctrl_awvalid && axil_ctrl_wvalid && !axil_ctrl_bvalid) begin
+        // write operation
+        axil_ctrl_awready_next = 1'b1;
+        axil_ctrl_wready_next = 1'b1;
+        axil_ctrl_bresp_next = 2'b00;
+        axil_ctrl_bvalid_next = 1'b1;
+
+        case ({axil_ctrl_awaddr[15:2], 2'b00})
+            16'h0000: pcie_dma_enable_next = axil_ctrl_wdata;
+            16'h0100: pcie_dma_read_desc_pcie_addr_next[31:0] = axil_ctrl_wdata;
+            16'h0104: pcie_dma_read_desc_pcie_addr_next[63:32] = axil_ctrl_wdata;
+            16'h0108: pcie_dma_read_desc_axi_addr_next[31:0] = axil_ctrl_wdata;
+            //16'h010C: pcie_dma_read_desc_axi_addr_next[63:32] = axil_ctrl_wdata;
+            16'h0110: pcie_dma_read_desc_len_next = axil_ctrl_wdata;
+            16'h0114: begin
+                pcie_dma_read_desc_tag_next = axil_ctrl_wdata;
+                pcie_dma_read_desc_valid_next = 1'b1;
+            end
+            16'h0200: pcie_dma_write_desc_pcie_addr_next[31:0] = axil_ctrl_wdata;
+            16'h0204: pcie_dma_write_desc_pcie_addr_next[63:32] = axil_ctrl_wdata;
+            16'h0208: pcie_dma_write_desc_axi_addr_next[31:0] = axil_ctrl_wdata;
+            //16'h020C: pcie_dma_write_desc_axi_addr_next[63:32] = axil_ctrl_wdata;
+            16'h0210: pcie_dma_write_desc_len_next = axil_ctrl_wdata;
+            16'h0214: begin
+                pcie_dma_write_desc_tag_next = axil_ctrl_wdata;
+                pcie_dma_write_desc_valid_next = 1'b1;
+            end
+        endcase
+    end
+
+    if (axil_ctrl_arvalid && !axil_ctrl_rvalid) begin
+        // read operation
+        axil_ctrl_arready_next = 1'b1;
+        axil_ctrl_rresp_next = 2'b00;
+        axil_ctrl_rvalid_next = 1'b1;
+
+        case ({axil_ctrl_araddr[15:2], 2'b00})
+            16'h0000: axil_ctrl_rdata_next = pcie_dma_enable_reg;
+            16'h0118: begin
+                axil_ctrl_rdata_next[7:0] = pcie_dma_read_desc_status_tag_reg;
+                axil_ctrl_rdata_next[15:8] = pcie_dma_read_desc_status_error_reg;
+                axil_ctrl_rdata_next[31] = pcie_dma_read_desc_status_valid_reg;
+                pcie_dma_read_desc_status_valid_next = 1'b0;
+            end
+            16'h0218: begin
+                axil_ctrl_rdata_next[7:0] = pcie_dma_write_desc_status_tag_reg;
+                axil_ctrl_rdata_next[15:8] = pcie_dma_write_desc_status_error_reg;
+                axil_ctrl_rdata_next[31] = pcie_dma_write_desc_status_valid_reg;
+                pcie_dma_write_desc_status_valid_next = 1'b0;
+            end
+            16'h0400: axil_ctrl_rdata_next = pcie_rq_count_reg;
+            16'h0404: axil_ctrl_rdata_next = pcie_rc_count_reg;
+            16'h0408: axil_ctrl_rdata_next = pcie_cq_count_reg;
+            16'h040C: axil_ctrl_rdata_next = pcie_cc_count_reg;
+        endcase
+    end
+
+    if (pcie_dma_read_desc_status_valid) begin
+        pcie_dma_read_desc_status_tag_next = pcie_dma_read_desc_status_tag;
+        pcie_dma_read_desc_status_error_next = pcie_dma_read_desc_status_error;
+        pcie_dma_read_desc_status_valid_next = pcie_dma_read_desc_status_valid;
+    end
+
+    if (pcie_dma_write_desc_status_valid) begin
+        pcie_dma_write_desc_status_tag_next = pcie_dma_write_desc_status_tag;
+        pcie_dma_write_desc_status_error_next = pcie_dma_write_desc_status_error;
+        pcie_dma_write_desc_status_valid_next = pcie_dma_write_desc_status_valid;
+    end
+end
+
+always @(posedge clk) begin
+    axil_ctrl_awready_reg <= axil_ctrl_awready_next;
+    axil_ctrl_wready_reg <= axil_ctrl_wready_next;
+    axil_ctrl_bresp_reg <= axil_ctrl_bresp_next;
+    axil_ctrl_bvalid_reg <= axil_ctrl_bvalid_next;
+    axil_ctrl_arready_reg <= axil_ctrl_arready_next;
+    axil_ctrl_rdata_reg <= axil_ctrl_rdata_next;
+    axil_ctrl_rresp_reg <= axil_ctrl_rresp_next;
+    axil_ctrl_rvalid_reg <= axil_ctrl_rvalid_next;
+
+    pcie_dma_read_desc_pcie_addr_reg <= pcie_dma_read_desc_pcie_addr_next;
+    pcie_dma_read_desc_axi_addr_reg <= pcie_dma_read_desc_axi_addr_next;
+    pcie_dma_read_desc_len_reg <= pcie_dma_read_desc_len_next;
+    pcie_dma_read_desc_tag_reg <= pcie_dma_read_desc_tag_next;
+    pcie_dma_read_desc_valid_reg <= pcie_dma_read_desc_valid_next;
+
+    pcie_dma_read_desc_status_tag_reg <= pcie_dma_read_desc_status_tag_next;
+    pcie_dma_read_desc_status_error_reg <= pcie_dma_read_desc_status_error_next;
+    pcie_dma_read_desc_status_valid_reg <= pcie_dma_read_desc_status_valid_next;
+
+    pcie_dma_write_desc_pcie_addr_reg <= pcie_dma_write_desc_pcie_addr_next;
+    pcie_dma_write_desc_axi_addr_reg <= pcie_dma_write_desc_axi_addr_next;
+    pcie_dma_write_desc_len_reg <= pcie_dma_write_desc_len_next;
+    pcie_dma_write_desc_tag_reg <= pcie_dma_write_desc_tag_next;
+    pcie_dma_write_desc_valid_reg <= pcie_dma_write_desc_valid_next;
+
+    pcie_dma_write_desc_status_tag_reg <= pcie_dma_write_desc_status_tag_next;
+    pcie_dma_write_desc_status_error_reg <= pcie_dma_write_desc_status_error_next;
+    pcie_dma_write_desc_status_valid_reg <= pcie_dma_write_desc_status_valid_next;
+
+    pcie_dma_enable_reg <= pcie_dma_enable_next;
+
+    if (m_axis_rq_tready && m_axis_rq_tvalid && m_axis_rq_tlast) begin
+        pcie_rq_count_reg <= pcie_rq_count_reg + 1;
+    end
+
+    if (s_axis_rc_tready && s_axis_rc_tvalid && s_axis_rc_tlast) begin
+        pcie_rc_count_reg <= pcie_rc_count_reg + 1;
+    end
+
+    if (s_axis_cq_tready && s_axis_cq_tvalid && s_axis_cq_tlast) begin
+        pcie_cq_count_reg <= pcie_cq_count_reg + 1;
+    end
+
+    if (m_axis_cc_tready && m_axis_cc_tvalid && m_axis_cc_tlast) begin
+        pcie_cc_count_reg <= pcie_cc_count_reg + 1;
+    end
+
+    if (rst) begin
+        axil_ctrl_awready_reg <= 1'b0;
+        axil_ctrl_wready_reg <= 1'b0;
+        axil_ctrl_bvalid_reg <= 1'b0;
+        axil_ctrl_arready_reg <= 1'b0;
+        axil_ctrl_rvalid_reg <= 1'b0;
+
+        pcie_dma_read_desc_valid_reg <= 1'b0;
+        pcie_dma_read_desc_status_valid_reg <= 1'b0;
+        pcie_dma_write_desc_valid_reg <= 1'b0;
+        pcie_dma_write_desc_status_valid_reg <= 1'b0;
+        pcie_dma_enable_reg <= 1'b0;
+
+        pcie_rq_count_reg <= 0;
+        pcie_rc_count_reg <= 0;
+        pcie_cq_count_reg <= 0;
+        pcie_cc_count_reg <= 0;
+    end
+end
+
+assign led = 3'd0;
+
+pcie_us_cfg #(
+    .PF_COUNT(1),
+    .VF_COUNT(0),
+    .VF_OFFSET(4),
+    .PCIE_CAP_OFFSET(12'h070)
+)
+pcie_us_cfg_inst (
+    .clk(clk),
+    .rst(rst),
+
+    /*
+     * Configuration outputs
+     */
+    .ext_tag_enable(ext_tag_enable),
+    .max_read_request_size(),
+    .max_payload_size(),
+
+    /*
+     * Interface to Ultrascale PCIe IP core
+     */
+    .cfg_mgmt_addr(cfg_mgmt_addr),
+    .cfg_mgmt_function_number(cfg_mgmt_function_number),
+    .cfg_mgmt_write(cfg_mgmt_write),
+    .cfg_mgmt_write_data(cfg_mgmt_write_data),
+    .cfg_mgmt_byte_enable(cfg_mgmt_byte_enable),
+    .cfg_mgmt_read(cfg_mgmt_read),
+    .cfg_mgmt_read_data(cfg_mgmt_read_data),
+    .cfg_mgmt_read_write_done(cfg_mgmt_read_write_done)
+);
+
+pcie_us_axil_master #(
+    .AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
+    .AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
+    .AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH),
+    .AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH),
+    .AXI_DATA_WIDTH(AXIL_DATA_WIDTH),
+    .AXI_ADDR_WIDTH(AXIL_ADDR_WIDTH),
+    .ENABLE_PARITY(0)
+)
+pcie_us_axil_master_inst (
+    .clk(clk),
+    .rst(rst),
+
+    /*
+     * AXI input (CQ)
+     */
+    .s_axis_cq_tdata(axis_cq_tdata_bar_0),
+    .s_axis_cq_tkeep(axis_cq_tkeep_bar_0),
+    .s_axis_cq_tvalid(axis_cq_tvalid_bar_0),
+    .s_axis_cq_tready(axis_cq_tready_bar_0),
+    .s_axis_cq_tlast(axis_cq_tlast_bar_0),
+    .s_axis_cq_tuser(axis_cq_tuser_bar_0),
+
+    /*
+     * AXI input (CC)
+     */
+    .m_axis_cc_tdata(axis_cc_tdata_bar_0),
+    .m_axis_cc_tkeep(axis_cc_tkeep_bar_0),
+    .m_axis_cc_tvalid(axis_cc_tvalid_bar_0),
+    .m_axis_cc_tready(axis_cc_tready_bar_0),
+    .m_axis_cc_tlast(axis_cc_tlast_bar_0),
+    .m_axis_cc_tuser(axis_cc_tuser_bar_0),
+
+    /*
+     * AXI Lite Master output
+     */
+    .m_axil_awaddr(axil_ctrl_awaddr),
+    .m_axil_awprot(axil_ctrl_awprot),
+    .m_axil_awvalid(axil_ctrl_awvalid),
+    .m_axil_awready(axil_ctrl_awready),
+    .m_axil_wdata(axil_ctrl_wdata),
+    .m_axil_wstrb(axil_ctrl_wstrb),
+    .m_axil_wvalid(axil_ctrl_wvalid),
+    .m_axil_wready(axil_ctrl_wready),
+    .m_axil_bresp(axil_ctrl_bresp),
+    .m_axil_bvalid(axil_ctrl_bvalid),
+    .m_axil_bready(axil_ctrl_bready),
+    .m_axil_araddr(axil_ctrl_araddr),
+    .m_axil_arprot(axil_ctrl_arprot),
+    .m_axil_arvalid(axil_ctrl_arvalid),
+    .m_axil_arready(axil_ctrl_arready),
+    .m_axil_rdata(axil_ctrl_rdata),
+    .m_axil_rresp(axil_ctrl_rresp),
+    .m_axil_rvalid(axil_ctrl_rvalid),
+    .m_axil_rready(axil_ctrl_rready),
+
+    /*
+     * Configuration
+     */
+    .completer_id({8'd0, 5'd0, 3'd0}),
+    .completer_id_enable(1'b0),
+
+    /*
+     * Status
+     */
+    .status_error_cor(status_error_cor_int[0]),
+    .status_error_uncor(status_error_uncor_int[0])
+);
+
+pcie_us_axi_master #(
+    .AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
+    .AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
+    .AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH),
+    .AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH),
+    .AXI_DATA_WIDTH(AXI_DATA_WIDTH),
+    .AXI_ADDR_WIDTH(AXI_ADDR_WIDTH),
+    .AXI_STRB_WIDTH(AXI_STRB_WIDTH),
+    .AXI_ID_WIDTH(AXI_ID_WIDTH)
+)
+pcie_us_axi_master_inst (
+    .clk(clk),
+    .rst(rst),
+
+    /*
+     * AXI input (CQ)
+     */
+    .s_axis_cq_tdata(axis_cq_tdata_bar_2),
+    .s_axis_cq_tkeep(axis_cq_tkeep_bar_2),
+    .s_axis_cq_tvalid(axis_cq_tvalid_bar_2),
+    .s_axis_cq_tready(axis_cq_tready_bar_2),
+    .s_axis_cq_tlast(axis_cq_tlast_bar_2),
+    .s_axis_cq_tuser(axis_cq_tuser_bar_2),
+
+    /*
+     * AXI output (CC)
+     */
+    .m_axis_cc_tdata(axis_cc_tdata_bar_2),
+    .m_axis_cc_tkeep(axis_cc_tkeep_bar_2),
+    .m_axis_cc_tvalid(axis_cc_tvalid_bar_2),
+    .m_axis_cc_tready(axis_cc_tready_bar_2),
+    .m_axis_cc_tlast(axis_cc_tlast_bar_2),
+    .m_axis_cc_tuser(axis_cc_tuser_bar_2),
+
+    /*
+     * AXI Master output
+     */
+    .m_axi_awid(axi_awid),
+    .m_axi_awaddr(axi_awaddr),
+    .m_axi_awlen(axi_awlen),
+    .m_axi_awsize(axi_awsize),
+    .m_axi_awburst(axi_awburst),
+    .m_axi_awlock(axi_awlock),
+    .m_axi_awcache(axi_awcache),
+    .m_axi_awprot(axi_awprot),
+    .m_axi_awvalid(axi_awvalid),
+    .m_axi_awready(axi_awready),
+    .m_axi_wdata(axi_wdata),
+    .m_axi_wstrb(axi_wstrb),
+    .m_axi_wlast(axi_wlast),
+    .m_axi_wvalid(axi_wvalid),
+    .m_axi_wready(axi_wready),
+    .m_axi_bid(axi_bid),
+    .m_axi_bresp(axi_bresp),
+    .m_axi_bvalid(axi_bvalid),
+    .m_axi_bready(axi_bready),
+    .m_axi_arid(axi_arid),
+    .m_axi_araddr(axi_araddr),
+    .m_axi_arlen(axi_arlen),
+    .m_axi_arsize(axi_arsize),
+    .m_axi_arburst(axi_arburst),
+    .m_axi_arlock(axi_arlock),
+    .m_axi_arcache(axi_arcache),
+    .m_axi_arprot(axi_arprot),
+    .m_axi_arvalid(axi_arvalid),
+    .m_axi_arready(axi_arready),
+    .m_axi_rid(axi_rid),
+    .m_axi_rdata(axi_rdata),
+    .m_axi_rresp(axi_rresp),
+    .m_axi_rlast(axi_rlast),
+    .m_axi_rvalid(axi_rvalid),
+    .m_axi_rready(axi_rready),
+
+    /*
+     * Configuration
+     */
+    .completer_id({8'd0, 5'd0, 3'd1}),
+    .completer_id_enable(1'b0),
+    .max_payload_size(cfg_max_payload),
+
+    /*
+     * Status
+     */
+    .status_error_cor(status_error_cor_int[1]),
+    .status_error_uncor(status_error_uncor_int[1])
+);
+
+axi_ram #(
+    .DATA_WIDTH(AXI_DATA_WIDTH),
+    .ADDR_WIDTH(16),
+    .ID_WIDTH(AXI_ID_WIDTH),
+    .PIPELINE_OUTPUT(1)
+)
+axi_ram_inst (
+    .clk(clk),
+    .rst(rst),
+    .s_axi_awid(axi_awid),
+    .s_axi_awaddr(axi_awaddr),
+    .s_axi_awlen(axi_awlen),
+    .s_axi_awsize(axi_awsize),
+    .s_axi_awburst(axi_awburst),
+    .s_axi_awlock(axi_awlock),
+    .s_axi_awcache(axi_awcache),
+    .s_axi_awprot(axi_awprot),
+    .s_axi_awvalid(axi_awvalid),
+    .s_axi_awready(axi_awready),
+    .s_axi_wdata(axi_wdata),
+    .s_axi_wstrb(axi_wstrb),
+    .s_axi_wlast(axi_wlast),
+    .s_axi_wvalid(axi_wvalid),
+    .s_axi_wready(axi_wready),
+    .s_axi_bid(axi_bid),
+    .s_axi_bresp(axi_bresp),
+    .s_axi_bvalid(axi_bvalid),
+    .s_axi_bready(axi_bready),
+    .s_axi_arid(axi_arid),
+    .s_axi_araddr(axi_araddr),
+    .s_axi_arlen(axi_arlen),
+    .s_axi_arsize(axi_arsize),
+    .s_axi_arburst(axi_arburst),
+    .s_axi_arlock(axi_arlock),
+    .s_axi_arcache(axi_arcache),
+    .s_axi_arprot(axi_arprot),
+    .s_axi_arvalid(axi_arvalid),
+    .s_axi_arready(axi_arready),
+    .s_axi_rid(axi_rid),
+    .s_axi_rdata(axi_rdata),
+    .s_axi_rresp(axi_rresp),
+    .s_axi_rlast(axi_rlast),
+    .s_axi_rvalid(axi_rvalid),
+    .s_axi_rready(axi_rready)
+);
+
+wire [AXIS_PCIE_DATA_WIDTH-1:0]    axis_rc_tdata_r;
+wire [AXIS_PCIE_KEEP_WIDTH-1:0]    axis_rc_tkeep_r;
+wire                               axis_rc_tlast_r;
+wire                               axis_rc_tready_r;
+wire [AXIS_PCIE_RC_USER_WIDTH-1:0] axis_rc_tuser_r;
+wire                               axis_rc_tvalid_r;
+
+axis_register #(
+    .DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
+    .KEEP_ENABLE(1),
+    .KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
+    .LAST_ENABLE(1),
+    .ID_ENABLE(0),
+    .DEST_ENABLE(0),
+    .USER_ENABLE(1),
+    .USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH)
+)
+rc_reg (
+    .clk(clk),
+    .rst(rst),
+
+    /*
+     * AXI input
+     */
+    .s_axis_tdata(s_axis_rc_tdata),
+    .s_axis_tkeep(s_axis_rc_tkeep),
+    .s_axis_tvalid(s_axis_rc_tvalid),
+    .s_axis_tready(s_axis_rc_tready),
+    .s_axis_tlast(s_axis_rc_tlast),
+    .s_axis_tid(0),
+    .s_axis_tdest(0),
+    .s_axis_tuser(s_axis_rc_tuser),
+
+    /*
+     * AXI output
+     */
+    .m_axis_tdata(axis_rc_tdata_r),
+    .m_axis_tkeep(axis_rc_tkeep_r),
+    .m_axis_tvalid(axis_rc_tvalid_r),
+    .m_axis_tready(axis_rc_tready_r),
+    .m_axis_tlast(axis_rc_tlast_r),
+    .m_axis_tid(),
+    .m_axis_tdest(),
+    .m_axis_tuser(axis_rc_tuser_r)
+);
+
+pcie_us_axi_dma #(
+    .AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
+    .AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
+    .AXIS_PCIE_RC_USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH),
+    .AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH),
+    .AXI_DATA_WIDTH(AXI_DATA_WIDTH),
+    .AXI_ADDR_WIDTH(AXI_ADDR_WIDTH),
+    .AXI_STRB_WIDTH(AXI_STRB_WIDTH),
+    .AXI_ID_WIDTH(AXI_ID_WIDTH),
+    .AXI_MAX_BURST_LEN(256),
+    .PCIE_ADDR_WIDTH(PCIE_ADDR_WIDTH),
+    .PCIE_TAG_COUNT(256),
+    .LEN_WIDTH(16),
+    .TAG_WIDTH(DMA_TAG_WIDTH)
+)
+pcie_us_axi_dma_inst (
+    .clk(clk),
+    .rst(rst),
+
+    /*
+     * AXI input (RC)
+     */
+    .s_axis_rc_tdata(axis_rc_tdata_r),
+    .s_axis_rc_tkeep(axis_rc_tkeep_r),
+    .s_axis_rc_tvalid(axis_rc_tvalid_r),
+    .s_axis_rc_tready(axis_rc_tready_r),
+    .s_axis_rc_tlast(axis_rc_tlast_r),
+    .s_axis_rc_tuser(axis_rc_tuser_r),
+
+    /*
+     * AXI output (RQ)
+     */
+    .m_axis_rq_tdata(m_axis_rq_tdata),
+    .m_axis_rq_tkeep(m_axis_rq_tkeep),
+    .m_axis_rq_tvalid(m_axis_rq_tvalid),
+    .m_axis_rq_tready(m_axis_rq_tready),
+    .m_axis_rq_tlast(m_axis_rq_tlast),
+    .m_axis_rq_tuser(m_axis_rq_tuser),
+
+    /*
+     * AXI read descriptor input
+     */
+    .s_axis_read_desc_pcie_addr(pcie_dma_read_desc_pcie_addr),
+    .s_axis_read_desc_axi_addr(pcie_dma_read_desc_axi_addr),
+    .s_axis_read_desc_len(pcie_dma_read_desc_len),
+    .s_axis_read_desc_tag(pcie_dma_read_desc_tag),
+    .s_axis_read_desc_valid(pcie_dma_read_desc_valid),
+    .s_axis_read_desc_ready(pcie_dma_read_desc_ready),
+
+    /*
+     * AXI read descriptor status output
+     */
+    .m_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag),
+    .m_axis_read_desc_status_error(pcie_dma_read_desc_status_error),
+    .m_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid),
+
+    /*
+     * AXI write descriptor input
+     */
+    .s_axis_write_desc_pcie_addr(pcie_dma_write_desc_pcie_addr),
+    .s_axis_write_desc_axi_addr(pcie_dma_write_desc_axi_addr),
+    .s_axis_write_desc_len(pcie_dma_write_desc_len),
+    .s_axis_write_desc_tag(pcie_dma_write_desc_tag),
+    .s_axis_write_desc_valid(pcie_dma_write_desc_valid),
+    .s_axis_write_desc_ready(pcie_dma_write_desc_ready),
+
+    /*
+     * AXI write descriptor status output
+     */
+    .m_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag),
+    .m_axis_write_desc_status_error(pcie_dma_write_desc_status_error),
+    .m_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid),
+
+    /*
+     * AXI Master output
+     */
+    .m_axi_awid(axi_dma_awid),
+    .m_axi_awaddr(axi_dma_awaddr),
+    .m_axi_awlen(axi_dma_awlen),
+    .m_axi_awsize(axi_dma_awsize),
+    .m_axi_awburst(axi_dma_awburst),
+    .m_axi_awlock(axi_dma_awlock),
+    .m_axi_awcache(axi_dma_awcache),
+    .m_axi_awprot(axi_dma_awprot),
+    .m_axi_awvalid(axi_dma_awvalid),
+    .m_axi_awready(axi_dma_awready),
+    .m_axi_wdata(axi_dma_wdata),
+    .m_axi_wstrb(axi_dma_wstrb),
+    .m_axi_wlast(axi_dma_wlast),
+    .m_axi_wvalid(axi_dma_wvalid),
+    .m_axi_wready(axi_dma_wready),
+    .m_axi_bid(axi_dma_bid),
+    .m_axi_bresp(axi_dma_bresp),
+    .m_axi_bvalid(axi_dma_bvalid),
+    .m_axi_bready(axi_dma_bready),
+    .m_axi_arid(axi_dma_arid),
+    .m_axi_araddr(axi_dma_araddr),
+    .m_axi_arlen(axi_dma_arlen),
+    .m_axi_arsize(axi_dma_arsize),
+    .m_axi_arburst(axi_dma_arburst),
+    .m_axi_arlock(axi_dma_arlock),
+    .m_axi_arcache(axi_dma_arcache),
+    .m_axi_arprot(axi_dma_arprot),
+    .m_axi_arvalid(axi_dma_arvalid),
+    .m_axi_arready(axi_dma_arready),
+    .m_axi_rid(axi_dma_rid),
+    .m_axi_rdata(axi_dma_rdata),
+    .m_axi_rresp(axi_dma_rresp),
+    .m_axi_rlast(axi_dma_rlast),
+    .m_axi_rvalid(axi_dma_rvalid),
+    .m_axi_rready(axi_dma_rready),
+
+    /*
+     * Configuration
+     */
+    .read_enable(pcie_dma_enable),
+    .write_enable(pcie_dma_enable),
+    .ext_tag_enable(ext_tag_enable),
+    .requester_id({8'd0, 5'd0, 3'd0}),
+    .requester_id_enable(1'b0),
+    .max_read_request_size(cfg_max_read_req),
+    .max_payload_size(cfg_max_payload),
+
+    /*
+     * Status
+     */
+    .status_error_cor(status_error_cor_int[2]),
+    .status_error_uncor(status_error_uncor_int[2])
+);
+
+axi_ram #(
+    .DATA_WIDTH(AXI_DATA_WIDTH),
+    .ADDR_WIDTH(16),
+    .ID_WIDTH(AXI_ID_WIDTH),
+    .PIPELINE_OUTPUT(1)
+)
+axi_dma_ram_inst (
+    .clk(clk),
+    .rst(rst),
+    .s_axi_awid(axi_dma_awid),
+    .s_axi_awaddr(axi_dma_awaddr),
+    .s_axi_awlen(axi_dma_awlen),
+    .s_axi_awsize(axi_dma_awsize),
+    .s_axi_awburst(axi_dma_awburst),
+    .s_axi_awlock(axi_dma_awlock),
+    .s_axi_awcache(axi_dma_awcache),
+    .s_axi_awprot(axi_dma_awprot),
+    .s_axi_awvalid(axi_dma_awvalid),
+    .s_axi_awready(axi_dma_awready),
+    .s_axi_wdata(axi_dma_wdata),
+    .s_axi_wstrb(axi_dma_wstrb),
+    .s_axi_wlast(axi_dma_wlast),
+    .s_axi_wvalid(axi_dma_wvalid),
+    .s_axi_wready(axi_dma_wready),
+    .s_axi_bid(axi_dma_bid),
+    .s_axi_bresp(axi_dma_bresp),
+    .s_axi_bvalid(axi_dma_bvalid),
+    .s_axi_bready(axi_dma_bready),
+    .s_axi_arid(axi_dma_arid),
+    .s_axi_araddr(axi_dma_araddr),
+    .s_axi_arlen(axi_dma_arlen),
+    .s_axi_arsize(axi_dma_arsize),
+    .s_axi_arburst(axi_dma_arburst),
+    .s_axi_arlock(axi_dma_arlock),
+    .s_axi_arcache(axi_dma_arcache),
+    .s_axi_arprot(axi_dma_arprot),
+    .s_axi_arvalid(axi_dma_arvalid),
+    .s_axi_arready(axi_dma_arready),
+    .s_axi_rid(axi_dma_rid),
+    .s_axi_rdata(axi_dma_rdata),
+    .s_axi_rresp(axi_dma_rresp),
+    .s_axi_rlast(axi_dma_rlast),
+    .s_axi_rvalid(axi_dma_rvalid),
+    .s_axi_rready(axi_dma_rready)
+);
+
+pulse_merge #(
+    .INPUT_WIDTH(3),
+    .COUNT_WIDTH(4)
+)
+status_error_cor_pm_inst (
+    .clk(clk),
+    .rst(rst),
+
+    .pulse_in(status_error_cor_int),
+    .count_out(),
+    .pulse_out(status_error_cor)
+);
+
+pulse_merge #(
+    .INPUT_WIDTH(3),
+    .COUNT_WIDTH(4)
+)
+status_error_uncor_pm_inst (
+    .clk(clk),
+    .rst(rst),
+
+    .pulse_in(status_error_uncor_int),
+    .count_out(),
+    .pulse_out(status_error_uncor)
+);
+
+pcie_us_msi #(
+    .MSI_COUNT(32)
+)
+pcie_us_msi_inst (
+    .clk(clk),
+    .rst(rst),
+
+    .msi_irq(msi_irq),
+
+    .cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
+    .cfg_interrupt_msi_vf_enable(0),
+    .cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
+    .cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
+    .cfg_interrupt_msi_data(cfg_interrupt_msi_data),
+    .cfg_interrupt_msi_select(cfg_interrupt_msi_select),
+    .cfg_interrupt_msi_int(cfg_interrupt_msi_int),
+    .cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
+    .cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
+    .cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
+    .cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
+    .cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
+    .cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
+    .cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
+    .cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
+    .cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
+    .cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number)
+);
+
+endmodule
+
+`resetall

snapshots/alexforencich_verilog-pcie_pr20/example/AU250/fpga_axi/rtl/sync_reset.v

@@ -0,0 +1,56 @@
+/*
+
+Copyright (c) 2014-2018 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog-2001
+
+`resetall
+`timescale 1 ns / 1 ps
+`default_nettype none
+
+/*
+ * Synchronizes an active-high asynchronous reset signal to a given clock by
+ * using a pipeline of N registers.
+ */
+module sync_reset #(
+    parameter N=2 // depth of synchronizer
+)(
+    input wire clk,
+    input wire rst,
+    output wire sync_reset_out
+);
+
+reg [N-1:0] sync_reg = {N{1'b1}};
+
+assign sync_reset_out = sync_reg[N-1];
+
+always @(posedge clk or posedge rst) begin
+    if (rst)
+        sync_reg <= {N{1'b1}};
+    else
+        sync_reg <= {sync_reg[N-2:0], 1'b0};
+end
+
+endmodule
+
+`resetall

snapshots/alexforencich_verilog-pcie_pr20/example/AU250/fpga_axi/rtl/sync_signal.v

@@ -0,0 +1,62 @@
+/*
+
+Copyright (c) 2014-2018 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog-2001
+
+`resetall
+`timescale 1 ns / 1 ps
+`default_nettype none
+
+/*
+ * Synchronizes an asyncronous signal to a given clock by using a pipeline of
+ * two registers.
+ */
+module sync_signal #(
+    parameter WIDTH=1, // width of the input and output signals
+    parameter N=2 // depth of synchronizer
+)(
+    input wire clk,
+    input wire [WIDTH-1:0] in,
+    output wire [WIDTH-1:0] out
+);
+
+reg [WIDTH-1:0] sync_reg[N-1:0];
+
+/*
+ * The synchronized output is the last register in the pipeline.
+ */
+assign out = sync_reg[N-1];
+
+integer k;
+
+always @(posedge clk) begin
+    sync_reg[0] <= in;
+    for (k = 1; k < N; k = k + 1) begin
+        sync_reg[k] <= sync_reg[k-1];
+    end
+end
+
+endmodule
+
+`resetall

snapshots/alexforencich_verilog-pcie_pr20/example/AU250/fpga_axi/tb/fpga_core/Makefile

@@ -0,0 +1,102 @@
+# Copyright (c) 2020 Alex Forencich
+#
+# Permission is hereby granted, free of charge, to any person obtaining a copy
+# of this software and associated documentation files (the "Software"), to deal
+# in the Software without restriction, including without limitation the rights
+# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+# copies of the Software, and to permit persons to whom the Software is
+# furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+# THE SOFTWARE.
+
+TOPLEVEL_LANG = verilog
+
+SIM ?= icarus
+WAVES ?= 0
+
+COCOTB_HDL_TIMEUNIT = 1ns
+COCOTB_HDL_TIMEPRECISION = 1ps
+
+DUT      = fpga_core
+TOPLEVEL = $(DUT)
+MODULE   = test_$(DUT)
+VERILOG_SOURCES += ../../rtl/$(DUT).v
+VERILOG_SOURCES += ../../rtl/axi_ram.v
+VERILOG_SOURCES += ../../rtl/axis_register.v
+VERILOG_SOURCES += ../../lib/pcie/rtl/axis_arb_mux.v
+VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_axil_master.v
+VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_axi_dma.v
+VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_axi_dma_rd.v
+VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_axi_dma_wr.v
+VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_axi_master.v
+VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_axi_master_rd.v
+VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_axi_master_wr.v
+VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_axis_cq_demux.v
+VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_cfg.v
+VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_msi.v
+VERILOG_SOURCES += ../../lib/pcie/rtl/arbiter.v
+VERILOG_SOURCES += ../../lib/pcie/rtl/priority_encoder.v
+VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v
+
+# module parameters
+export PARAM_AXIS_PCIE_DATA_WIDTH ?= 512
+export PARAM_AXIS_PCIE_KEEP_WIDTH ?= $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 )
+export PARAM_AXIS_PCIE_RQ_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),62,137)
+export PARAM_AXIS_PCIE_RC_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),75,161)
+export PARAM_AXIS_PCIE_CQ_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),88,183)
+export PARAM_AXIS_PCIE_CC_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),33,81)
+export PARAM_RQ_SEQ_NUM_WIDTH ?= 6
+
+ifeq ($(SIM), icarus)
+	PLUSARGS += -fst
+
+	COMPILE_ARGS += -P $(TOPLEVEL).AXIS_PCIE_DATA_WIDTH=$(PARAM_AXIS_PCIE_DATA_WIDTH)
+	COMPILE_ARGS += -P $(TOPLEVEL).AXIS_PCIE_KEEP_WIDTH=$(PARAM_AXIS_PCIE_KEEP_WIDTH)
+	COMPILE_ARGS += -P $(TOPLEVEL).AXIS_PCIE_RQ_USER_WIDTH=$(PARAM_AXIS_PCIE_RQ_USER_WIDTH)
+	COMPILE_ARGS += -P $(TOPLEVEL).AXIS_PCIE_RC_USER_WIDTH=$(PARAM_AXIS_PCIE_RC_USER_WIDTH)
+	COMPILE_ARGS += -P $(TOPLEVEL).AXIS_PCIE_CQ_USER_WIDTH=$(PARAM_AXIS_PCIE_CQ_USER_WIDTH)
+	COMPILE_ARGS += -P $(TOPLEVEL).AXIS_PCIE_CC_USER_WIDTH=$(PARAM_AXIS_PCIE_CC_USER_WIDTH)
+	COMPILE_ARGS += -P $(TOPLEVEL).RQ_SEQ_NUM_WIDTH=$(PARAM_RQ_SEQ_NUM_WIDTH)
+
+	ifeq ($(WAVES), 1)
+		VERILOG_SOURCES += iverilog_dump.v
+		COMPILE_ARGS += -s iverilog_dump
+	endif
+else ifeq ($(SIM), verilator)
+	COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH
+
+	COMPILE_ARGS += -GAXIS_PCIE_DATA_WIDTH=$(PARAM_AXIS_PCIE_DATA_WIDTH)
+	COMPILE_ARGS += -GAXIS_PCIE_KEEP_WIDTH=$(PARAM_AXIS_PCIE_KEEP_WIDTH)
+	COMPILE_ARGS += -GAXIS_PCIE_RQ_USER_WIDTH=$(PARAM_AXIS_PCIE_RQ_USER_WIDTH)
+	COMPILE_ARGS += -GAXIS_PCIE_RC_USER_WIDTH=$(PARAM_AXIS_PCIE_RC_USER_WIDTH)
+	COMPILE_ARGS += -GAXIS_PCIE_CQ_USER_WIDTH=$(PARAM_AXIS_PCIE_CQ_USER_WIDTH)
+	COMPILE_ARGS += -GAXIS_PCIE_CC_USER_WIDTH=$(PARAM_AXIS_PCIE_CC_USER_WIDTH)
+	COMPILE_ARGS += -GRQ_SEQ_NUM_WIDTH=$(PARAM_RQ_SEQ_NUM_WIDTH)
+
+	ifeq ($(WAVES), 1)
+		COMPILE_ARGS += --trace-fst
+	endif
+endif
+
+include $(shell cocotb-config --makefiles)/Makefile.sim
+
+iverilog_dump.v:
+	echo 'module iverilog_dump();' > $@
+	echo 'initial begin' >> $@
+	echo '    $$dumpfile("$(TOPLEVEL).fst");' >> $@
+	echo '    $$dumpvars(0, $(TOPLEVEL));' >> $@
+	echo 'end' >> $@
+	echo 'endmodule' >> $@
+
+clean::
+	@rm -rf iverilog_dump.v
+	@rm -rf dump.fst $(TOPLEVEL).fst

snapshots/alexforencich_verilog-pcie_pr20/example/AU250/fpga_axi/tb/fpga_core/test_fpga_core.py

@@ -0,0 +1,376 @@
+"""
+
+Copyright (c) 2020 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+"""
+
+import logging
+import os
+
+import cocotb_test.simulator
+
+import cocotb
+from cocotb.log import SimLog
+from cocotb.triggers import RisingEdge, FallingEdge, Timer
+
+from cocotbext.axi import AxiStreamBus
+from cocotbext.pcie.core import RootComplex
+from cocotbext.pcie.xilinx.us import UltraScalePlusPcieDevice
+from cocotbext.axi.utils import hexdump_str
+
+
+class TB(object):
+    def __init__(self, dut):
+        self.dut = dut
+
+        self.log = SimLog("cocotb.tb")
+        self.log.setLevel(logging.DEBUG)
+
+        # PCIe
+        self.rc = RootComplex()
+
+        self.dev = UltraScalePlusPcieDevice(
+            # configuration options
+            pcie_generation=3,
+            pcie_link_width=16,
+            user_clk_frequency=250e6,
+            alignment="dword",
+            cq_cc_straddle=False,
+            rq_rc_straddle=False,
+            rc_4tlp_straddle=False,
+            enable_pf1=False,
+            enable_client_tag=True,
+            enable_extended_tag=True,
+            enable_parity=False,
+            enable_rx_msg_interface=False,
+            enable_sriov=False,
+            enable_extended_configuration=False,
+
+            enable_pf0_msi=True,
+            enable_pf1_msi=False,
+
+            # signals
+            # Clock and Reset Interface
+            user_clk=dut.clk,
+            user_reset=dut.rst,
+            # user_lnk_up
+            # sys_clk
+            # sys_clk_gt
+            # sys_reset
+            # phy_rdy_out
+
+            # Requester reQuest Interface
+            rq_bus=AxiStreamBus.from_prefix(dut, "m_axis_rq"),
+            # pcie_rq_seq_num0=dut.s_axis_rq_seq_num_0,
+            # pcie_rq_seq_num_vld0=dut.s_axis_rq_seq_num_valid_0,
+            # pcie_rq_seq_num1=dut.s_axis_rq_seq_num_1,
+            # pcie_rq_seq_num_vld1=dut.s_axis_rq_seq_num_valid_1,
+            # pcie_rq_tag0
+            # pcie_rq_tag1
+            # pcie_rq_tag_av
+            # pcie_rq_tag_vld0
+            # pcie_rq_tag_vld1
+
+            # Requester Completion Interface
+            rc_bus=AxiStreamBus.from_prefix(dut, "s_axis_rc"),
+
+            # Completer reQuest Interface
+            cq_bus=AxiStreamBus.from_prefix(dut, "s_axis_cq"),
+            # pcie_cq_np_req
+            # pcie_cq_np_req_count
+
+            # Completer Completion Interface
+            cc_bus=AxiStreamBus.from_prefix(dut, "m_axis_cc"),
+
+            # Transmit Flow Control Interface
+            # pcie_tfc_nph_av=dut.pcie_tfc_nph_av,
+            # pcie_tfc_npd_av=dut.pcie_tfc_npd_av,
+
+            # Configuration Management Interface
+            cfg_mgmt_addr=dut.cfg_mgmt_addr,
+            cfg_mgmt_function_number=dut.cfg_mgmt_function_number,
+            cfg_mgmt_write=dut.cfg_mgmt_write,
+            cfg_mgmt_write_data=dut.cfg_mgmt_write_data,
+            cfg_mgmt_byte_enable=dut.cfg_mgmt_byte_enable,
+            cfg_mgmt_read=dut.cfg_mgmt_read,
+            cfg_mgmt_read_data=dut.cfg_mgmt_read_data,
+            cfg_mgmt_read_write_done=dut.cfg_mgmt_read_write_done,
+            # cfg_mgmt_debug_access
+
+            # Configuration Status Interface
+            # cfg_phy_link_down
+            # cfg_phy_link_status
+            # cfg_negotiated_width
+            # cfg_current_speed
+            cfg_max_payload=dut.cfg_max_payload,
+            cfg_max_read_req=dut.cfg_max_read_req,
+            # cfg_function_status
+            # cfg_vf_status
+            # cfg_function_power_state
+            # cfg_vf_power_state
+            # cfg_link_power_state
+            # cfg_err_cor_out
+            # cfg_err_nonfatal_out
+            # cfg_err_fatal_out
+            # cfg_local_error_out
+            # cfg_local_error_valid
+            # cfg_rx_pm_state
+            # cfg_tx_pm_state
+            # cfg_ltssm_state
+            # cfg_rcb_status
+            # cfg_obff_enable
+            # cfg_pl_status_change
+            # cfg_tph_requester_enable
+            # cfg_tph_st_mode
+            # cfg_vf_tph_requester_enable
+            # cfg_vf_tph_st_mode
+
+            # Configuration Received Message Interface
+            # cfg_msg_received
+            # cfg_msg_received_data
+            # cfg_msg_received_type
+
+            # Configuration Transmit Message Interface
+            # cfg_msg_transmit
+            # cfg_msg_transmit_type
+            # cfg_msg_transmit_data
+            # cfg_msg_transmit_done
+
+            # Configuration Flow Control Interface
+            # cfg_fc_ph=dut.cfg_fc_ph,
+            # cfg_fc_pd=dut.cfg_fc_pd,
+            # cfg_fc_nph=dut.cfg_fc_nph,
+            # cfg_fc_npd=dut.cfg_fc_npd,
+            # cfg_fc_cplh=dut.cfg_fc_cplh,
+            # cfg_fc_cpld=dut.cfg_fc_cpld,
+            # cfg_fc_sel=dut.cfg_fc_sel,
+
+            # Configuration Control Interface
+            # cfg_hot_reset_in
+            # cfg_hot_reset_out
+            # cfg_config_space_enable
+            # cfg_dsn
+            # cfg_bus_number
+            # cfg_ds_port_number
+            # cfg_ds_bus_number
+            # cfg_ds_device_number
+            # cfg_ds_function_number
+            # cfg_power_state_change_ack
+            # cfg_power_state_change_interrupt
+            cfg_err_cor_in=dut.status_error_cor,
+            cfg_err_uncor_in=dut.status_error_uncor,
+            # cfg_flr_in_process
+            # cfg_flr_done
+            # cfg_vf_flr_in_process
+            # cfg_vf_flr_func_num
+            # cfg_vf_flr_done
+            # cfg_pm_aspm_l1_entry_reject
+            # cfg_pm_aspm_tx_l0s_entry_disable
+            # cfg_req_pm_transition_l23_ready
+            # cfg_link_training_enable
+
+            # Configuration Interrupt Controller Interface
+            # cfg_interrupt_int
+            # cfg_interrupt_sent
+            # cfg_interrupt_pending
+            cfg_interrupt_msi_enable=dut.cfg_interrupt_msi_enable,
+            cfg_interrupt_msi_mmenable=dut.cfg_interrupt_msi_mmenable,
+            cfg_interrupt_msi_mask_update=dut.cfg_interrupt_msi_mask_update,
+            cfg_interrupt_msi_data=dut.cfg_interrupt_msi_data,
+            # cfg_interrupt_msi_select=dut.cfg_interrupt_msi_select,
+            cfg_interrupt_msi_int=dut.cfg_interrupt_msi_int,
+            cfg_interrupt_msi_pending_status=dut.cfg_interrupt_msi_pending_status,
+            cfg_interrupt_msi_pending_status_data_enable=dut.cfg_interrupt_msi_pending_status_data_enable,
+            # cfg_interrupt_msi_pending_status_function_num=dut.cfg_interrupt_msi_pending_status_function_num,
+            cfg_interrupt_msi_sent=dut.cfg_interrupt_msi_sent,
+            cfg_interrupt_msi_fail=dut.cfg_interrupt_msi_fail,
+            # cfg_interrupt_msix_enable
+            # cfg_interrupt_msix_mask
+            # cfg_interrupt_msix_vf_enable
+            # cfg_interrupt_msix_vf_mask
+            # cfg_interrupt_msix_address
+            # cfg_interrupt_msix_data
+            # cfg_interrupt_msix_int
+            # cfg_interrupt_msix_vec_pending
+            # cfg_interrupt_msix_vec_pending_status
+            cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr,
+            cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present,
+            cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type,
+            # cfg_interrupt_msi_tph_st_tag=dut.cfg_interrupt_msi_tph_st_tag,
+            # cfg_interrupt_msi_function_number=dut.cfg_interrupt_msi_function_number,
+
+            # Configuration Extend Interface
+            # cfg_ext_read_received
+            # cfg_ext_write_received
+            # cfg_ext_register_number
+            # cfg_ext_function_number
+            # cfg_ext_write_data
+            # cfg_ext_write_byte_enable
+            # cfg_ext_read_data
+            # cfg_ext_read_data_valid
+        )
+
+        # self.dev.log.setLevel(logging.DEBUG)
+
+        self.rc.make_port().connect(self.dev)
+
+        self.dev.functions[0].msi_multiple_message_capable = 5
+
+        self.dev.functions[0].configure_bar(0, 2**22)
+        self.dev.functions[0].configure_bar(2, 2**22)
+
+        dut.sw.setimmediatevalue(0)
+
+    async def init(self):
+
+        await FallingEdge(self.dut.rst)
+        await Timer(100, 'ns')
+
+        await self.rc.enumerate(enable_bus_mastering=True, configure_msi=True)
+
+
+@cocotb.test()
+async def run_test(dut):
+
+    tb = TB(dut)
+
+    await tb.init()
+
+    mem = tb.rc.mem_pool.alloc_region(16*1024*1024)
+    mem_base = mem.get_absolute_address(0)
+
+    dev_pf0_bar0 = tb.rc.tree[0][0].bar_window[0]
+    dev_pf0_bar2 = tb.rc.tree[0][0].bar_window[2]
+
+    tb.log.info("Test memory write to BAR 2")
+
+    test_data = b'\x11\x22\x33\x44'
+    await dev_pf0_bar2.write(0, test_data)
+
+    await Timer(100, 'ns')
+
+    tb.log.info("Test memory read from BAR 2")
+
+    val = await dev_pf0_bar2.read(0, len(test_data), timeout=1000)
+    tb.log.info("Read data: %s", val)
+    assert val == test_data
+
+    tb.log.info("Test DMA")
+
+    # write packet data
+    mem[0:1024] = bytearray([x % 256 for x in range(1024)])
+
+    # enable DMA
+    await dev_pf0_bar0.write_dword(0x000000, 1)
+
+    # write pcie read descriptor
+    await dev_pf0_bar0.write_dword(0x000100, (mem_base+0x0000) & 0xffffffff)
+    await dev_pf0_bar0.write_dword(0x000104, (mem_base+0x0000 >> 32) & 0xffffffff)
+    await dev_pf0_bar0.write_dword(0x000108, 0x100)
+    await dev_pf0_bar0.write_dword(0x000110, 0x400)
+    await dev_pf0_bar0.write_dword(0x000114, 0xAA)
+
+    await Timer(2000, 'ns')
+
+    # read status
+    val = await dev_pf0_bar0.read_dword(0x000118)
+    tb.log.info("Status: 0x%x", val)
+    assert val == 0x800000AA
+
+    # write pcie write descriptor
+    await dev_pf0_bar0.write_dword(0x000200, (mem_base+0x1000) & 0xffffffff)
+    await dev_pf0_bar0.write_dword(0x000204, (mem_base+0x1000 >> 32) & 0xffffffff)
+    await dev_pf0_bar0.write_dword(0x000208, 0x100)
+    await dev_pf0_bar0.write_dword(0x000210, 0x400)
+    await dev_pf0_bar0.write_dword(0x000214, 0x55)
+
+    await Timer(2000, 'ns')
+
+    # read status
+    val = await dev_pf0_bar0.read_dword(0x000218)
+    tb.log.info("Status: 0x%x", val)
+    assert val == 0x80000055
+
+    tb.log.info("%s", mem.hexdump_str(0x1000, 64))
+
+    assert mem[0:1024] == mem[0x1000:0x1000+1024]
+
+    await RisingEdge(dut.clk)
+    await RisingEdge(dut.clk)
+
+
+# cocotb-test
+
+tests_dir = os.path.dirname(__file__)
+rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
+lib_dir = os.path.abspath(os.path.join(rtl_dir, '..', 'lib'))
+pcie_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'pcie', 'rtl'))
+
+
+def test_fpga_core(request):
+    dut = "fpga_core"
+    module = os.path.splitext(os.path.basename(__file__))[0]
+    toplevel = dut
+
+    verilog_sources = [
+        os.path.join(rtl_dir, f"{dut}.v"),
+        os.path.join(rtl_dir, "axi_ram.v"),
+        os.path.join(rtl_dir, "axis_register.v"),
+        os.path.join(pcie_rtl_dir, "axis_arb_mux.v"),
+        os.path.join(pcie_rtl_dir, "pcie_us_axil_master.v"),
+        os.path.join(pcie_rtl_dir, "pcie_us_axi_dma.v"),
+        os.path.join(pcie_rtl_dir, "pcie_us_axi_dma_rd.v"),
+        os.path.join(pcie_rtl_dir, "pcie_us_axi_dma_wr.v"),
+        os.path.join(pcie_rtl_dir, "pcie_us_axi_master.v"),
+        os.path.join(pcie_rtl_dir, "pcie_us_axi_master_rd.v"),
+        os.path.join(pcie_rtl_dir, "pcie_us_axi_master_wr.v"),
+        os.path.join(pcie_rtl_dir, "pcie_us_axis_cq_demux.v"),
+        os.path.join(pcie_rtl_dir, "pcie_us_cfg.v"),
+        os.path.join(pcie_rtl_dir, "pcie_us_msi.v"),
+        os.path.join(pcie_rtl_dir, "arbiter.v"),
+        os.path.join(pcie_rtl_dir, "priority_encoder.v"),
+        os.path.join(pcie_rtl_dir, "pulse_merge.v"),
+    ]
+
+    parameters = {}
+
+    parameters['AXIS_PCIE_DATA_WIDTH'] = 512
+    parameters['AXIS_PCIE_KEEP_WIDTH'] = parameters['AXIS_PCIE_DATA_WIDTH'] // 32
+    parameters['AXIS_PCIE_RQ_USER_WIDTH'] = 62 if parameters['AXIS_PCIE_DATA_WIDTH'] < 512 else 137
+    parameters['AXIS_PCIE_RC_USER_WIDTH'] = 75 if parameters['AXIS_PCIE_DATA_WIDTH'] < 512 else 161
+    parameters['AXIS_PCIE_CQ_USER_WIDTH'] = 88 if parameters['AXIS_PCIE_DATA_WIDTH'] < 512 else 183
+    parameters['AXIS_PCIE_CC_USER_WIDTH'] = 33 if parameters['AXIS_PCIE_DATA_WIDTH'] < 512 else 81
+    parameters['RQ_SEQ_NUM_WIDTH'] = 6
+
+    extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
+
+    sim_build = os.path.join(tests_dir, "sim_build",
+        request.node.name.replace('[', '-').replace(']', ''))
+
+    cocotb_test.simulator.run(
+        python_search=[tests_dir],
+        verilog_sources=verilog_sources,
+        toplevel=toplevel,
+        module=module,
+        parameters=parameters,
+        sim_build=sim_build,
+        extra_env=extra_env,
+    )

snapshots/alexforencich_verilog-pcie_pr20/example/AU50/fpga/README.md

@@ -0,0 +1,19 @@
+# Verilog PCIe Alveo U50 Example Design
+
+## Introduction
+
+This example design targets the Xilinx Alveo U50 FPGA board.
+
+The design implements the PCIe AXI lite master module, the PCIe AXI master module, and the PCIe DMA module.  A very simple Linux driver is included to test the FPGA design.
+
+*  FPGA: xcu50-fsvh2104-2-e
+
+## How to build
+
+Run `make` to build.  Ensure that the Xilinx Vivado components are in PATH.
+
+Run `make` to build the driver.  Ensure the headers for the running kernel are installed, otherwise the driver cannot be compiled.
+
+## How to test
+
+Run `make program` to program the Alveo U50 board with Vivado.  Then load the driver with `insmod example.ko`.  Check dmesg for the output.

snapshots/alexforencich_verilog-pcie_pr20/example/AU50/fpga/common/vivado.mk

@@ -0,0 +1,126 @@
+###################################################################
+# 
+# Xilinx Vivado FPGA Makefile
+# 
+# Copyright (c) 2016 Alex Forencich
+# 
+###################################################################
+# 
+# Parameters:
+# FPGA_TOP - Top module name
+# FPGA_FAMILY - FPGA family (e.g. VirtexUltrascale)
+# FPGA_DEVICE - FPGA device (e.g. xcvu095-ffva2104-2-e)
+# SYN_FILES - space-separated list of source files
+# INC_FILES - space-separated list of include files
+# XDC_FILES - space-separated list of timing constraint files
+# XCI_FILES - space-separated list of IP XCI files
+# 
+# Example:
+# 
+# FPGA_TOP = fpga
+# FPGA_FAMILY = VirtexUltrascale
+# FPGA_DEVICE = xcvu095-ffva2104-2-e
+# SYN_FILES = rtl/fpga.v
+# XDC_FILES = fpga.xdc
+# XCI_FILES = ip/pcspma.xci
+# include ../common/vivado.mk
+# 
+###################################################################
+
+# phony targets
+.PHONY: fpga vivado tmpclean clean distclean
+
+# prevent make from deleting intermediate files and reports
+.PRECIOUS: %.xpr %.bit %.mcs %.prm
+.SECONDARY:
+
+CONFIG ?= config.mk
+-include ../$(CONFIG)
+
+SYN_FILES_REL = $(patsubst %, ../%, $(filter-out /% ./%,$(SYN_FILES))) $(filter /% ./%,$(SYN_FILES))
+INC_FILES_REL = $(patsubst %, ../%, $(filter-out /% ./%,$(INC_FILES))) $(filter /% ./%,$(INC_FILES))
+XCI_FILES_REL = $(patsubst %, ../%, $(filter-out /% ./%,$(XCI_FILES))) $(filter /% ./%,$(XCI_FILES))
+IP_TCL_FILES_REL = $(patsubst %, ../%, $(filter-out /% ./%,$(IP_TCL_FILES))) $(filter /% ./%,$(IP_TCL_FILES))
+CONFIG_TCL_FILES_REL = $(patsubst %, ../%, $(filter-out /% ./%,$(CONFIG_TCL_FILES))) $(filter /% ./%,$(CONFIG_TCL_FILES))
+
+ifdef XDC_FILES
+  XDC_FILES_REL = $(patsubst %, ../%, $(filter-out /% ./%,$(XDC_FILES))) $(filter /% ./%,$(XDC_FILES))
+else
+  XDC_FILES_REL = $(FPGA_TOP).xdc
+endif
+
+###################################################################
+# Main Targets
+#
+# all: build everything
+# clean: remove output files and project files
+###################################################################
+
+all: fpga
+
+fpga: $(FPGA_TOP).bit
+
+vivado: $(FPGA_TOP).xpr
+	vivado $(FPGA_TOP).xpr
+
+tmpclean::
+	-rm -rf *.log *.jou *.cache *.gen *.hbs *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v
+	-rm -rf create_project.tcl update_config.tcl run_synth.tcl run_impl.tcl generate_bit.tcl
+
+clean:: tmpclean
+	-rm -rf *.bit program.tcl generate_mcs.tcl *.mcs *.prm flash.tcl
+
+distclean:: clean
+	-rm -rf rev
+
+###################################################################
+# Target implementations
+###################################################################
+
+# Vivado project file
+create_project.tcl: Makefile $(XCI_FILES_REL) $(IP_TCL_FILES_REL)
+	rm -rf defines.v
+	touch defines.v
+	for x in $(DEFS); do echo '`define' $$x >> defines.v; done
+	echo "create_project -force -part $(FPGA_PART) $(FPGA_TOP)" > $@
+	echo "add_files -fileset sources_1 defines.v $(SYN_FILES_REL)" >> $@
+	echo "add_files -fileset constrs_1 $(XDC_FILES_REL)" >> $@
+	for x in $(XCI_FILES_REL); do echo "import_ip $$x" >> $@; done
+	for x in $(IP_TCL_FILES_REL); do echo "source $$x" >> $@; done
+	for x in $(CONFIG_TCL_FILES_REL); do echo "source $$x" >> $@; done
+
+update_config.tcl: $(CONFIG_TCL_FILES_REL)
+	echo "open_project -quiet $(FPGA_TOP).xpr" > $@
+	for x in $(CONFIG_TCL_FILES_REL); do echo "source $$x" >> $@; done
+
+$(FPGA_TOP).xpr: create_project.tcl update_config.tcl
+	vivado -nojournal -nolog -mode batch $(foreach x,$?,-source $x)
+
+# synthesis run
+%.runs/synth_1/%.dcp: %.xpr $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL) $(CONFIG_TCL_FILES_REL)
+	echo "open_project $*.xpr" > run_synth.tcl
+	echo "reset_run synth_1" >> run_synth.tcl
+	echo "launch_runs -jobs 4 synth_1" >> run_synth.tcl
+	echo "wait_on_run synth_1" >> run_synth.tcl
+	vivado -nojournal -nolog -mode batch -source run_synth.tcl
+
+# implementation run
+%.runs/impl_1/%_routed.dcp: %.runs/synth_1/%.dcp
+	echo "open_project $*.xpr" > run_impl.tcl
+	echo "reset_run impl_1" >> run_impl.tcl
+	echo "launch_runs -jobs 4 impl_1" >> run_impl.tcl
+	echo "wait_on_run impl_1" >> run_impl.tcl
+	vivado -nojournal -nolog -mode batch -source run_impl.tcl
+
+# bit file
+%.bit: %.runs/impl_1/%_routed.dcp
+	echo "open_project $*.xpr" > generate_bit.tcl
+	echo "open_run impl_1" >> generate_bit.tcl
+	echo "write_bitstream -force $*.bit" >> generate_bit.tcl
+	vivado -nojournal -nolog -mode batch -source generate_bit.tcl
+	mkdir -p rev
+	EXT=bit; COUNT=100; \
+	while [ -e rev/$*_rev$$COUNT.$$EXT ]; \
+	do COUNT=$$((COUNT+1)); done; \
+	cp $@ rev/$*_rev$$COUNT.$$EXT; \
+	echo "Output: rev/$*_rev$$COUNT.$$EXT";

snapshots/alexforencich_verilog-pcie_pr20/example/AU50/fpga/fpga/Makefile

@@ -0,0 +1,93 @@
+
+# FPGA settings
+FPGA_PART = xcu50-fsvh2104-2-e
+FPGA_TOP = fpga
+FPGA_ARCH = virtexuplus
+
+# Files for synthesis
+SYN_FILES = rtl/fpga.v
+SYN_FILES += rtl/fpga_core.v
+SYN_FILES += rtl/sync_reset.v
+SYN_FILES += rtl/sync_signal.v
+SYN_FILES += rtl/common/example_core_pcie_us.v
+SYN_FILES += rtl/common/example_core_pcie.v
+SYN_FILES += rtl/common/example_core.v
+SYN_FILES += rtl/common/axi_ram.v
+SYN_FILES += lib/pcie/rtl/pcie_us_if.v
+SYN_FILES += lib/pcie/rtl/pcie_us_if_rc.v
+SYN_FILES += lib/pcie/rtl/pcie_us_if_rq.v
+SYN_FILES += lib/pcie/rtl/pcie_us_if_cq.v
+SYN_FILES += lib/pcie/rtl/pcie_us_if_cc.v
+SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v
+SYN_FILES += lib/pcie/rtl/pcie_us_msi.v
+SYN_FILES += lib/pcie/rtl/pcie_axil_master.v
+SYN_FILES += lib/pcie/rtl/pcie_axi_master.v
+SYN_FILES += lib/pcie/rtl/pcie_axi_master_rd.v
+SYN_FILES += lib/pcie/rtl/pcie_axi_master_wr.v
+SYN_FILES += lib/pcie/rtl/pcie_tlp_demux_bar.v
+SYN_FILES += lib/pcie/rtl/pcie_tlp_demux.v
+SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v
+SYN_FILES += lib/pcie/rtl/dma_if_pcie.v
+SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v
+SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v
+SYN_FILES += lib/pcie/rtl/dma_psdpram.v
+SYN_FILES += lib/pcie/rtl/arbiter.v
+SYN_FILES += lib/pcie/rtl/priority_encoder.v
+SYN_FILES += lib/pcie/rtl/pulse_merge.v
+
+# XDC files
+XDC_FILES = fpga.xdc
+
+# IP
+IP_TCL_FILES = ip/pcie4c_uscale_plus_0.tcl
+
+include ../common/vivado.mk
+
+program: $(FPGA_TOP).bit
+	echo "open_hw" > program.tcl
+	echo "connect_hw_server" >> program.tcl
+	echo "open_hw_target" >> program.tcl
+	echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
+	echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
+	echo "set_property PROGRAM.FILE {$(FPGA_TOP).bit} [current_hw_device]" >> program.tcl
+	echo "program_hw_devices [current_hw_device]" >> program.tcl
+	echo "exit" >> program.tcl
+	vivado -nojournal -nolog -mode batch -source program.tcl
+
+%.mcs %.prm: %.bit
+	echo "write_cfgmem -force -format mcs -size 128 -interface SPIx4 -loadbit {up 0x01002000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl
+	echo "exit" >> generate_mcs.tcl
+	vivado -nojournal -nolog -mode batch -source generate_mcs.tcl
+	mkdir -p rev
+	COUNT=100; \
+	while [ -e rev/$*_rev$$COUNT.bit ]; \
+	do COUNT=$$((COUNT+1)); done; \
+	COUNT=$$((COUNT-1)); \
+	for x in .mcs .prm; \
+	do cp $*$$x rev/$*_rev$$COUNT$$x; \
+	echo "Output: rev/$*_rev$$COUNT$$x"; done;
+
+flash: $(FPGA_TOP).mcs $(FPGA_TOP).prm
+	echo "open_hw" > flash.tcl
+	echo "connect_hw_server" >> flash.tcl
+	echo "open_hw_target" >> flash.tcl
+	echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash.tcl
+	echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash.tcl
+	echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {mt25qu01g-spi-x1_x2_x4}] 0]" >> flash.tcl
+	echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash.tcl
+	echo "set_property PROGRAM.FILES [list \"$(FPGA_TOP).mcs\"] [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.PRM_FILES [list \"$(FPGA_TOP).prm\"] [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash.tcl
+	echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash.tcl
+	echo "program_hw_devices [current_hw_device]" >> flash.tcl
+	echo "refresh_hw_device [current_hw_device]" >> flash.tcl
+	echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash.tcl
+	echo "boot_hw_device [current_hw_device]" >> flash.tcl
+	echo "exit" >> flash.tcl
+	vivado -nojournal -nolog -mode batch -source flash.tcl
+

snapshots/alexforencich_verilog-pcie_pr20/example/AU50/fpga/ip/pcie4c_uscale_plus_0.tcl

@@ -0,0 +1,28 @@
+
+create_ip -name pcie4c_uscale_plus -vendor xilinx.com -library ip -module_name pcie4c_uscale_plus_0
+
+set_property -dict [list \
+    CONFIG.PL_LINK_CAP_MAX_LINK_SPEED {8.0_GT/s} \
+    CONFIG.PL_LINK_CAP_MAX_LINK_WIDTH {X16} \
+    CONFIG.AXISTEN_IF_EXT_512_RQ_STRADDLE {false} \
+    CONFIG.axisten_if_enable_client_tag {true} \
+    CONFIG.axisten_if_width {512_bit} \
+    CONFIG.axisten_freq {250} \
+    CONFIG.PF0_CLASS_CODE {058000} \
+    CONFIG.PF0_DEVICE_ID {0001} \
+    CONFIG.PF0_MSI_CAP_MULTIMSGCAP {32_vectors} \
+    CONFIG.PF0_SUBSYSTEM_ID {9032} \
+    CONFIG.PF0_SUBSYSTEM_VENDOR_ID {10ee} \
+    CONFIG.pf0_bar0_64bit {true} \
+    CONFIG.pf0_bar0_prefetchable {true} \
+    CONFIG.pf0_bar0_scale {Megabytes} \
+    CONFIG.pf0_bar0_size {16} \
+    CONFIG.pf0_bar2_64bit {true} \
+    CONFIG.pf0_bar2_prefetchable {true} \
+    CONFIG.pf0_bar2_enabled {true} \
+    CONFIG.pf0_bar2_type {Memory} \
+    CONFIG.pf0_bar2_scale {Megabytes} \
+    CONFIG.pf0_bar2_size {16} \
+    CONFIG.vendor_id {1234} \
+    CONFIG.en_msi_per_vec_masking {true} \
+] [get_ips pcie4c_uscale_plus_0]

snapshots/alexforencich_verilog-pcie_pr20/example/AU50/fpga/rtl/fpga.v

@@ -0,0 +1,454 @@
+/*
+
+Copyright (c) 2020 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog 2001
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * FPGA top-level module
+ */
+module fpga (
+    /*
+     * GPIO
+     */
+    output wire        qsfp_led_act,
+    output wire        qsfp_led_stat_g,
+    output wire        qsfp_led_stat_y,
+    output wire        hbm_cattrip,
+
+    /*
+     * PCI express
+     */
+    input  wire [15:0] pcie_rx_p,
+    input  wire [15:0] pcie_rx_n,
+    output wire [15:0] pcie_tx_p,
+    output wire [15:0] pcie_tx_n,
+    input  wire        pcie_refclk_1_p,
+    input  wire        pcie_refclk_1_n,
+    input  wire        pcie_reset_n
+);
+
+parameter AXIS_PCIE_DATA_WIDTH = 512;
+parameter AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32);
+parameter AXIS_PCIE_RC_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 75 : 161;
+parameter AXIS_PCIE_RQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 60 : 137;
+parameter AXIS_PCIE_CQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 85 : 183;
+parameter AXIS_PCIE_CC_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 33 : 81;
+
+parameter RQ_SEQ_NUM_WIDTH = AXIS_PCIE_RQ_USER_WIDTH == 60 ? 4 : 6;
+parameter RQ_SEQ_NUM_ENABLE = 1;
+
+parameter PCIE_TAG_COUNT = 64;
+parameter BAR0_APERTURE = 24;
+parameter BAR2_APERTURE = 24;
+
+// Clock and reset
+wire pcie_user_clk;
+wire pcie_user_reset;
+
+// GPIO
+assign hbm_cattrip = 1'b0;
+
+// PCIe
+wire pcie_sys_clk;
+wire pcie_sys_clk_gt;
+
+IBUFDS_GTE4 #(
+    .REFCLK_HROW_CK_SEL(2'b00)
+)
+ibufds_gte4_pcie_mgt_refclk_inst (
+    .I             (pcie_refclk_1_p),
+    .IB            (pcie_refclk_1_n),
+    .CEB           (1'b0),
+    .O             (pcie_sys_clk_gt),
+    .ODIV2         (pcie_sys_clk)
+);
+
+wire [AXIS_PCIE_DATA_WIDTH-1:0]    axis_rq_tdata;
+wire [AXIS_PCIE_KEEP_WIDTH-1:0]    axis_rq_tkeep;
+wire                               axis_rq_tlast;
+wire                               axis_rq_tready;
+wire [AXIS_PCIE_RQ_USER_WIDTH-1:0] axis_rq_tuser;
+wire                               axis_rq_tvalid;
+
+wire [AXIS_PCIE_DATA_WIDTH-1:0]    axis_rc_tdata;
+wire [AXIS_PCIE_KEEP_WIDTH-1:0]    axis_rc_tkeep;
+wire                               axis_rc_tlast;
+wire                               axis_rc_tready;
+wire [AXIS_PCIE_RC_USER_WIDTH-1:0] axis_rc_tuser;
+wire                               axis_rc_tvalid;
+
+wire [AXIS_PCIE_DATA_WIDTH-1:0]    axis_cq_tdata;
+wire [AXIS_PCIE_KEEP_WIDTH-1:0]    axis_cq_tkeep;
+wire                               axis_cq_tlast;
+wire                               axis_cq_tready;
+wire [AXIS_PCIE_CQ_USER_WIDTH-1:0] axis_cq_tuser;
+wire                               axis_cq_tvalid;
+
+wire [AXIS_PCIE_DATA_WIDTH-1:0]    axis_cc_tdata;
+wire [AXIS_PCIE_KEEP_WIDTH-1:0]    axis_cc_tkeep;
+wire                               axis_cc_tlast;
+wire                               axis_cc_tready;
+wire [AXIS_PCIE_CC_USER_WIDTH-1:0] axis_cc_tuser;
+wire                               axis_cc_tvalid;
+
+wire [RQ_SEQ_NUM_WIDTH-1:0]        pcie_rq_seq_num0;
+wire                               pcie_rq_seq_num_vld0;
+wire [RQ_SEQ_NUM_WIDTH-1:0]        pcie_rq_seq_num1;
+wire                               pcie_rq_seq_num_vld1;
+
+// ila_0 rq_ila (
+//     .clk(pcie_user_clk),
+//     .probe0(axis_rq_tdata),
+//     .probe1(axis_rq_tkeep),
+//     .probe2(axis_rq_tlast),
+//     .probe3(axis_rq_tready),
+//     .probe4(axis_rq_tuser),
+//     .probe5(axis_rq_tvalid)
+// );
+
+// ila_0 rc_ila (
+//     .clk(pcie_user_clk),
+//     .probe0(axis_rc_tdata),
+//     .probe1(axis_rc_tkeep),
+//     .probe2(axis_rc_tlast),
+//     .probe3(axis_rc_tready),
+//     .probe4(axis_rc_tuser),
+//     .probe5(axis_rc_tvalid)
+// );
+
+wire [2:0] cfg_max_payload;
+wire [2:0] cfg_max_read_req;
+
+wire [9:0]  cfg_mgmt_addr;
+wire [7:0]  cfg_mgmt_function_number;
+wire        cfg_mgmt_write;
+wire [31:0] cfg_mgmt_write_data;
+wire [3:0]  cfg_mgmt_byte_enable;
+wire        cfg_mgmt_read;
+wire [31:0] cfg_mgmt_read_data;
+wire        cfg_mgmt_read_write_done;
+
+wire [7:0]  cfg_fc_ph;
+wire [11:0] cfg_fc_pd;
+wire [7:0]  cfg_fc_nph;
+wire [11:0] cfg_fc_npd;
+wire [7:0]  cfg_fc_cplh;
+wire [11:0] cfg_fc_cpld;
+wire [2:0]  cfg_fc_sel;
+
+wire [3:0]  cfg_interrupt_msi_enable;
+wire [11:0] cfg_interrupt_msi_mmenable;
+wire        cfg_interrupt_msi_mask_update;
+wire [31:0] cfg_interrupt_msi_data;
+wire [3:0]  cfg_interrupt_msi_select;
+wire [31:0] cfg_interrupt_msi_int;
+wire [31:0] cfg_interrupt_msi_pending_status;
+wire        cfg_interrupt_msi_pending_status_data_enable;
+wire [3:0]  cfg_interrupt_msi_pending_status_function_num;
+wire        cfg_interrupt_msi_sent;
+wire        cfg_interrupt_msi_fail;
+wire [2:0]  cfg_interrupt_msi_attr;
+wire        cfg_interrupt_msi_tph_present;
+wire [1:0]  cfg_interrupt_msi_tph_type;
+wire [8:0]  cfg_interrupt_msi_tph_st_tag;
+wire [3:0]  cfg_interrupt_msi_function_number;
+
+wire status_error_cor;
+wire status_error_uncor;
+
+pcie4c_uscale_plus_0
+pcie4c_uscale_plus_inst (
+    .pci_exp_txn(pcie_tx_n),
+    .pci_exp_txp(pcie_tx_p),
+    .pci_exp_rxn(pcie_rx_n),
+    .pci_exp_rxp(pcie_rx_p),
+    .user_clk(pcie_user_clk),
+    .user_reset(pcie_user_reset),
+    .user_lnk_up(),
+
+    .s_axis_rq_tdata(axis_rq_tdata),
+    .s_axis_rq_tkeep(axis_rq_tkeep),
+    .s_axis_rq_tlast(axis_rq_tlast),
+    .s_axis_rq_tready(axis_rq_tready),
+    .s_axis_rq_tuser(axis_rq_tuser),
+    .s_axis_rq_tvalid(axis_rq_tvalid),
+
+    .m_axis_rc_tdata(axis_rc_tdata),
+    .m_axis_rc_tkeep(axis_rc_tkeep),
+    .m_axis_rc_tlast(axis_rc_tlast),
+    .m_axis_rc_tready(axis_rc_tready),
+    .m_axis_rc_tuser(axis_rc_tuser),
+    .m_axis_rc_tvalid(axis_rc_tvalid),
+
+    .m_axis_cq_tdata(axis_cq_tdata),
+    .m_axis_cq_tkeep(axis_cq_tkeep),
+    .m_axis_cq_tlast(axis_cq_tlast),
+    .m_axis_cq_tready(axis_cq_tready),
+    .m_axis_cq_tuser(axis_cq_tuser),
+    .m_axis_cq_tvalid(axis_cq_tvalid),
+
+    .s_axis_cc_tdata(axis_cc_tdata),
+    .s_axis_cc_tkeep(axis_cc_tkeep),
+    .s_axis_cc_tlast(axis_cc_tlast),
+    .s_axis_cc_tready(axis_cc_tready),
+    .s_axis_cc_tuser(axis_cc_tuser),
+    .s_axis_cc_tvalid(axis_cc_tvalid),
+
+    .pcie_rq_seq_num0(pcie_rq_seq_num0),
+    .pcie_rq_seq_num_vld0(pcie_rq_seq_num_vld0),
+    .pcie_rq_seq_num1(pcie_rq_seq_num1),
+    .pcie_rq_seq_num_vld1(pcie_rq_seq_num_vld1),
+    .pcie_rq_tag0(),
+    .pcie_rq_tag1(),
+    .pcie_rq_tag_av(),
+    .pcie_rq_tag_vld0(),
+    .pcie_rq_tag_vld1(),
+
+    .pcie_tfc_nph_av(),
+    .pcie_tfc_npd_av(),
+
+    .pcie_cq_np_req(1'b1),
+    .pcie_cq_np_req_count(),
+
+    .cfg_phy_link_down(),
+    .cfg_phy_link_status(),
+    .cfg_negotiated_width(),
+    .cfg_current_speed(),
+    .cfg_max_payload(cfg_max_payload),
+    .cfg_max_read_req(cfg_max_read_req),
+    .cfg_function_status(),
+    .cfg_function_power_state(),
+    .cfg_vf_status(),
+    .cfg_vf_power_state(),
+    .cfg_link_power_state(),
+
+    .cfg_mgmt_addr(cfg_mgmt_addr),
+    .cfg_mgmt_function_number(cfg_mgmt_function_number),
+    .cfg_mgmt_write(cfg_mgmt_write),
+    .cfg_mgmt_write_data(cfg_mgmt_write_data),
+    .cfg_mgmt_byte_enable(cfg_mgmt_byte_enable),
+    .cfg_mgmt_read(cfg_mgmt_read),
+    .cfg_mgmt_read_data(cfg_mgmt_read_data),
+    .cfg_mgmt_read_write_done(cfg_mgmt_read_write_done),
+    .cfg_mgmt_debug_access(1'b0),
+
+    .cfg_err_cor_out(),
+    .cfg_err_nonfatal_out(),
+    .cfg_err_fatal_out(),
+    .cfg_local_error_valid(),
+    .cfg_local_error_out(),
+    .cfg_ltssm_state(),
+    .cfg_rx_pm_state(),
+    .cfg_tx_pm_state(),
+    .cfg_rcb_status(),
+    .cfg_obff_enable(),
+    .cfg_pl_status_change(),
+    .cfg_tph_requester_enable(),
+    .cfg_tph_st_mode(),
+    .cfg_vf_tph_requester_enable(),
+    .cfg_vf_tph_st_mode(),
+
+    .cfg_msg_received(),
+    .cfg_msg_received_data(),
+    .cfg_msg_received_type(),
+    .cfg_msg_transmit(1'b0),
+    .cfg_msg_transmit_type(3'd0),
+    .cfg_msg_transmit_data(32'd0),
+    .cfg_msg_transmit_done(),
+
+    .cfg_fc_ph(cfg_fc_ph),
+    .cfg_fc_pd(cfg_fc_pd),
+    .cfg_fc_nph(cfg_fc_nph),
+    .cfg_fc_npd(cfg_fc_npd),
+    .cfg_fc_cplh(cfg_fc_cplh),
+    .cfg_fc_cpld(cfg_fc_cpld),
+    .cfg_fc_sel(cfg_fc_sel),
+
+    .cfg_dsn(64'd0),
+
+    .cfg_bus_number(),
+
+    .cfg_power_state_change_ack(1'b1),
+    .cfg_power_state_change_interrupt(),
+
+    .cfg_err_cor_in(status_error_cor),
+    .cfg_err_uncor_in(status_error_uncor),
+    .cfg_flr_in_process(),
+    .cfg_flr_done(4'd0),
+    .cfg_vf_flr_in_process(),
+    .cfg_vf_flr_func_num(8'd0),
+    .cfg_vf_flr_done(8'd0),
+
+    .cfg_link_training_enable(1'b1),
+
+    .cfg_interrupt_int(4'd0),
+    .cfg_interrupt_pending(4'd0),
+    .cfg_interrupt_sent(),
+    .cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
+    .cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
+    .cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
+    .cfg_interrupt_msi_data(cfg_interrupt_msi_data),
+    .cfg_interrupt_msi_select(cfg_interrupt_msi_select),
+    .cfg_interrupt_msi_int(cfg_interrupt_msi_int),
+    .cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
+    .cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
+    .cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
+    .cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
+    .cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
+    .cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
+    .cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
+    .cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
+    .cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
+    .cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
+
+    .cfg_pm_aspm_l1_entry_reject(1'b0),
+    .cfg_pm_aspm_tx_l0s_entry_disable(1'b0),
+
+    .cfg_hot_reset_out(),
+
+    .cfg_config_space_enable(1'b1),
+    .cfg_req_pm_transition_l23_ready(1'b0),
+    .cfg_hot_reset_in(1'b0),
+
+    .cfg_ds_port_number(8'd0),
+    .cfg_ds_bus_number(8'd0),
+    .cfg_ds_device_number(5'd0),
+
+    .sys_clk(pcie_sys_clk),
+    .sys_clk_gt(pcie_sys_clk_gt),
+    .sys_reset(pcie_reset_n),
+
+    .phy_rdy_out()
+);
+
+fpga_core #(
+    .AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
+    .AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
+    .AXIS_PCIE_RC_USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH),
+    .AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH),
+    .AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH),
+    .AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH),
+    .RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH),
+    .RQ_SEQ_NUM_ENABLE(RQ_SEQ_NUM_ENABLE),
+    .PCIE_TAG_COUNT(PCIE_TAG_COUNT),
+    .BAR0_APERTURE(BAR0_APERTURE),
+    .BAR2_APERTURE(BAR2_APERTURE)
+)
+core_inst (
+    /*
+     * Clock: 250 MHz
+     * Synchronous reset
+     */
+    .clk(pcie_user_clk),
+    .rst(pcie_user_reset),
+    /*
+     * GPIO
+     */
+    .qsfp_led_act(qsfp_led_act),
+    .qsfp_led_stat_g(qsfp_led_stat_g),
+    .qsfp_led_stat_y(qsfp_led_stat_y),
+    /*
+     * PCIe
+     */
+    .m_axis_rq_tdata(axis_rq_tdata),
+    .m_axis_rq_tkeep(axis_rq_tkeep),
+    .m_axis_rq_tlast(axis_rq_tlast),
+    .m_axis_rq_tready(axis_rq_tready),
+    .m_axis_rq_tuser(axis_rq_tuser),
+    .m_axis_rq_tvalid(axis_rq_tvalid),
+
+    .s_axis_rc_tdata(axis_rc_tdata),
+    .s_axis_rc_tkeep(axis_rc_tkeep),
+    .s_axis_rc_tlast(axis_rc_tlast),
+    .s_axis_rc_tready(axis_rc_tready),
+    .s_axis_rc_tuser(axis_rc_tuser),
+    .s_axis_rc_tvalid(axis_rc_tvalid),
+
+    .s_axis_cq_tdata(axis_cq_tdata),
+    .s_axis_cq_tkeep(axis_cq_tkeep),
+    .s_axis_cq_tlast(axis_cq_tlast),
+    .s_axis_cq_tready(axis_cq_tready),
+    .s_axis_cq_tuser(axis_cq_tuser),
+    .s_axis_cq_tvalid(axis_cq_tvalid),
+
+    .m_axis_cc_tdata(axis_cc_tdata),
+    .m_axis_cc_tkeep(axis_cc_tkeep),
+    .m_axis_cc_tlast(axis_cc_tlast),
+    .m_axis_cc_tready(axis_cc_tready),
+    .m_axis_cc_tuser(axis_cc_tuser),
+    .m_axis_cc_tvalid(axis_cc_tvalid),
+
+    .s_axis_rq_seq_num_0(pcie_rq_seq_num0),
+    .s_axis_rq_seq_num_valid_0(pcie_rq_seq_num_vld0),
+    .s_axis_rq_seq_num_1(pcie_rq_seq_num1),
+    .s_axis_rq_seq_num_valid_1(pcie_rq_seq_num_vld1),
+
+    .cfg_max_payload(cfg_max_payload),
+    .cfg_max_read_req(cfg_max_read_req),
+    
+    .cfg_mgmt_addr(cfg_mgmt_addr),
+    .cfg_mgmt_function_number(cfg_mgmt_function_number),
+    .cfg_mgmt_write(cfg_mgmt_write),
+    .cfg_mgmt_write_data(cfg_mgmt_write_data),
+    .cfg_mgmt_byte_enable(cfg_mgmt_byte_enable),
+    .cfg_mgmt_read(cfg_mgmt_read),
+    .cfg_mgmt_read_data(cfg_mgmt_read_data),
+    .cfg_mgmt_read_write_done(cfg_mgmt_read_write_done),
+
+    .cfg_fc_ph(cfg_fc_ph),
+    .cfg_fc_pd(cfg_fc_pd),
+    .cfg_fc_nph(cfg_fc_nph),
+    .cfg_fc_npd(cfg_fc_npd),
+    .cfg_fc_cplh(cfg_fc_cplh),
+    .cfg_fc_cpld(cfg_fc_cpld),
+    .cfg_fc_sel(cfg_fc_sel),
+
+    .cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
+    .cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
+    .cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
+    .cfg_interrupt_msi_data(cfg_interrupt_msi_data),
+    .cfg_interrupt_msi_select(cfg_interrupt_msi_select),
+    .cfg_interrupt_msi_int(cfg_interrupt_msi_int),
+    .cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
+    .cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
+    .cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
+    .cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
+    .cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
+    .cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
+    .cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
+    .cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
+    .cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
+    .cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
+
+    .status_error_cor(status_error_cor),
+    .status_error_uncor(status_error_uncor)
+);
+
+endmodule
+
+`resetall

snapshots/alexforencich_verilog-pcie_pr20/example/AU50/fpga/rtl/fpga_core.v

@@ -0,0 +1,274 @@
+/*
+
+Copyright (c) 2020 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog 2001
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * FPGA core logic
+ */
+module fpga_core #
+(
+    parameter AXIS_PCIE_DATA_WIDTH = 512,
+    parameter AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32),
+    parameter AXIS_PCIE_RC_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 75 : 161,
+    parameter AXIS_PCIE_RQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 60 : 137,
+    parameter AXIS_PCIE_CQ_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 85 : 183,
+    parameter AXIS_PCIE_CC_USER_WIDTH = AXIS_PCIE_DATA_WIDTH < 512 ? 33 : 81,
+    parameter RQ_SEQ_NUM_WIDTH = AXIS_PCIE_RQ_USER_WIDTH == 60 ? 4 : 6,
+    parameter RQ_SEQ_NUM_ENABLE = 1,
+    parameter PCIE_TAG_COUNT = 64,
+    parameter BAR0_APERTURE = 24,
+    parameter BAR2_APERTURE = 24
+)
+(
+    /*
+     * Clock: 250 MHz
+     * Synchronous reset
+     */
+    input  wire                               clk,
+    input  wire                               rst,
+
+    /*
+     * GPIO
+     */
+    output wire                               qsfp_led_act,
+    output wire                               qsfp_led_stat_g,
+    output wire                               qsfp_led_stat_y,
+
+    /*
+     * PCIe
+     */
+    output wire [AXIS_PCIE_DATA_WIDTH-1:0]    m_axis_rq_tdata,
+    output wire [AXIS_PCIE_KEEP_WIDTH-1:0]    m_axis_rq_tkeep,
+    output wire                               m_axis_rq_tlast,
+    input  wire                               m_axis_rq_tready,
+    output wire [AXIS_PCIE_RQ_USER_WIDTH-1:0] m_axis_rq_tuser,
+    output wire                               m_axis_rq_tvalid,
+
+    input  wire [AXIS_PCIE_DATA_WIDTH-1:0]    s_axis_rc_tdata,
+    input  wire [AXIS_PCIE_KEEP_WIDTH-1:0]    s_axis_rc_tkeep,
+    input  wire                               s_axis_rc_tlast,
+    output wire                               s_axis_rc_tready,
+    input  wire [AXIS_PCIE_RC_USER_WIDTH-1:0] s_axis_rc_tuser,
+    input  wire                               s_axis_rc_tvalid,
+
+    input  wire [AXIS_PCIE_DATA_WIDTH-1:0]    s_axis_cq_tdata,
+    input  wire [AXIS_PCIE_KEEP_WIDTH-1:0]    s_axis_cq_tkeep,
+    input  wire                               s_axis_cq_tlast,
+    output wire                               s_axis_cq_tready,
+    input  wire [AXIS_PCIE_CQ_USER_WIDTH-1:0] s_axis_cq_tuser,
+    input  wire                               s_axis_cq_tvalid,
+
+    output wire [AXIS_PCIE_DATA_WIDTH-1:0]    m_axis_cc_tdata,
+    output wire [AXIS_PCIE_KEEP_WIDTH-1:0]    m_axis_cc_tkeep,
+    output wire                               m_axis_cc_tlast,
+    input  wire                               m_axis_cc_tready,
+    output wire [AXIS_PCIE_CC_USER_WIDTH-1:0] m_axis_cc_tuser,
+    output wire                               m_axis_cc_tvalid,
+
+    input  wire [RQ_SEQ_NUM_WIDTH-1:0]        s_axis_rq_seq_num_0,
+    input  wire                               s_axis_rq_seq_num_valid_0,
+    input  wire [RQ_SEQ_NUM_WIDTH-1:0]        s_axis_rq_seq_num_1,
+    input  wire                               s_axis_rq_seq_num_valid_1,
+
+    input  wire [2:0]                         cfg_max_payload,
+    input  wire [2:0]                         cfg_max_read_req,
+
+    output wire [9:0]                         cfg_mgmt_addr,
+    output wire [7:0]                         cfg_mgmt_function_number,
+    output wire                               cfg_mgmt_write,
+    output wire [31:0]                        cfg_mgmt_write_data,
+    output wire [3:0]                         cfg_mgmt_byte_enable,
+    output wire                               cfg_mgmt_read,
+    input  wire [31:0]                        cfg_mgmt_read_data,
+    input  wire                               cfg_mgmt_read_write_done,
+
+    input  wire [7:0]                         cfg_fc_ph,
+    input  wire [11:0]                        cfg_fc_pd,
+    input  wire [7:0]                         cfg_fc_nph,
+    input  wire [11:0]                        cfg_fc_npd,
+    input  wire [7:0]                         cfg_fc_cplh,
+    input  wire [11:0]                        cfg_fc_cpld,
+    output wire [2:0]                         cfg_fc_sel,
+
+    input  wire [3:0]                         cfg_interrupt_msi_enable,
+    input  wire [11:0]                        cfg_interrupt_msi_mmenable,
+    input  wire                               cfg_interrupt_msi_mask_update,
+    input  wire [31:0]                        cfg_interrupt_msi_data,
+    output wire [3:0]                         cfg_interrupt_msi_select,
+    output wire [31:0]                        cfg_interrupt_msi_int,
+    output wire [31:0]                        cfg_interrupt_msi_pending_status,
+    output wire                               cfg_interrupt_msi_pending_status_data_enable,
+    output wire [3:0]                         cfg_interrupt_msi_pending_status_function_num,
+    input  wire                               cfg_interrupt_msi_sent,
+    input  wire                               cfg_interrupt_msi_fail,
+    output wire [2:0]                         cfg_interrupt_msi_attr,
+    output wire                               cfg_interrupt_msi_tph_present,
+    output wire [1:0]                         cfg_interrupt_msi_tph_type,
+    output wire [8:0]                         cfg_interrupt_msi_tph_st_tag,
+    output wire [3:0]                         cfg_interrupt_msi_function_number,
+
+    output wire                               status_error_cor,
+    output wire                               status_error_uncor
+);
+
+assign qsfp_led_act = 1'b0;
+assign qsfp_led_stat_g = 1'b0;
+assign qsfp_led_stat_y = 1'b0;
+
+example_core_pcie_us #(
+    .AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
+    .AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
+    .AXIS_PCIE_RC_USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH),
+    .AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH),
+    .AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH),
+    .AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH),
+    .RQ_SEQ_NUM_WIDTH(RQ_SEQ_NUM_WIDTH),
+    .RQ_SEQ_NUM_ENABLE(RQ_SEQ_NUM_ENABLE),
+    .PCIE_TAG_COUNT(PCIE_TAG_COUNT),
+    .READ_OP_TABLE_SIZE(PCIE_TAG_COUNT),
+    .READ_TX_LIMIT(2**(RQ_SEQ_NUM_WIDTH-1)),
+    .READ_TX_FC_ENABLE(1),
+    .WRITE_OP_TABLE_SIZE(2**(RQ_SEQ_NUM_WIDTH-1)),
+    .WRITE_TX_LIMIT(2**(RQ_SEQ_NUM_WIDTH-1)),
+    .WRITE_TX_FC_ENABLE(1),
+    .BAR0_APERTURE(BAR0_APERTURE),
+    .BAR2_APERTURE(BAR2_APERTURE)
+)
+example_core_pcie_us_inst (
+    .clk(clk),
+    .rst(rst),
+
+    /*
+     * AXI input (RC)
+     */
+    .s_axis_rc_tdata(s_axis_rc_tdata),
+    .s_axis_rc_tkeep(s_axis_rc_tkeep),
+    .s_axis_rc_tvalid(s_axis_rc_tvalid),
+    .s_axis_rc_tready(s_axis_rc_tready),
+    .s_axis_rc_tlast(s_axis_rc_tlast),
+    .s_axis_rc_tuser(s_axis_rc_tuser),
+
+    /*
+     * AXI output (RQ)
+     */
+    .m_axis_rq_tdata(m_axis_rq_tdata),
+    .m_axis_rq_tkeep(m_axis_rq_tkeep),
+    .m_axis_rq_tvalid(m_axis_rq_tvalid),
+    .m_axis_rq_tready(m_axis_rq_tready),
+    .m_axis_rq_tlast(m_axis_rq_tlast),
+    .m_axis_rq_tuser(m_axis_rq_tuser),
+
+    /*
+     * AXI input (CQ)
+     */
+    .s_axis_cq_tdata(s_axis_cq_tdata),
+    .s_axis_cq_tkeep(s_axis_cq_tkeep),
+    .s_axis_cq_tvalid(s_axis_cq_tvalid),
+    .s_axis_cq_tready(s_axis_cq_tready),
+    .s_axis_cq_tlast(s_axis_cq_tlast),
+    .s_axis_cq_tuser(s_axis_cq_tuser),
+
+    /*
+     * AXI output (CC)
+     */
+    .m_axis_cc_tdata(m_axis_cc_tdata),
+    .m_axis_cc_tkeep(m_axis_cc_tkeep),
+    .m_axis_cc_tvalid(m_axis_cc_tvalid),
+    .m_axis_cc_tready(m_axis_cc_tready),
+    .m_axis_cc_tlast(m_axis_cc_tlast),
+    .m_axis_cc_tuser(m_axis_cc_tuser),
+
+    /*
+     * Transmit sequence number input
+     */
+    .s_axis_rq_seq_num_0(s_axis_rq_seq_num_0),
+    .s_axis_rq_seq_num_valid_0(s_axis_rq_seq_num_valid_0),
+    .s_axis_rq_seq_num_1(s_axis_rq_seq_num_1),
+    .s_axis_rq_seq_num_valid_1(s_axis_rq_seq_num_valid_1),
+
+    /*
+     * Flow control
+     */
+    .cfg_fc_ph(cfg_fc_ph),
+    .cfg_fc_pd(cfg_fc_pd),
+    .cfg_fc_nph(cfg_fc_nph),
+    .cfg_fc_npd(cfg_fc_npd),
+    .cfg_fc_cplh(cfg_fc_cplh),
+    .cfg_fc_cpld(cfg_fc_cpld),
+    .cfg_fc_sel(cfg_fc_sel),
+
+    /*
+     * Configuration interface
+     */
+    .cfg_mgmt_addr(cfg_mgmt_addr),
+    .cfg_mgmt_function_number(cfg_mgmt_function_number),
+    .cfg_mgmt_write(cfg_mgmt_write),
+    .cfg_mgmt_write_data(cfg_mgmt_write_data),
+    .cfg_mgmt_byte_enable(cfg_mgmt_byte_enable),
+    .cfg_mgmt_read(cfg_mgmt_read),
+    .cfg_mgmt_read_data(cfg_mgmt_read_data),
+    .cfg_mgmt_read_write_done(cfg_mgmt_read_write_done),
+
+    /*
+     * Interrupt interface
+     */
+    .cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
+    .cfg_interrupt_msi_vf_enable(8'd0),
+    .cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
+    .cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
+    .cfg_interrupt_msi_data(cfg_interrupt_msi_data),
+    .cfg_interrupt_msi_select(cfg_interrupt_msi_select),
+    .cfg_interrupt_msi_int(cfg_interrupt_msi_int),
+    .cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
+    .cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
+    .cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
+    .cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
+    .cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
+    .cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
+    .cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
+    .cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
+    .cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
+    .cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
+
+    /*
+     * Configuration
+     */
+    .cfg_max_read_req(cfg_max_read_req),
+    .cfg_max_payload(cfg_max_payload),
+
+    /*
+     * Status
+     */
+    .status_error_cor(status_error_cor),
+    .status_error_uncor(status_error_uncor)
+);
+
+endmodule
+
+`resetall

snapshots/alexforencich_verilog-pcie_pr20/example/AU50/fpga/rtl/sync_reset.v

@@ -0,0 +1,56 @@
+/*
+
+Copyright (c) 2014-2018 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog-2001
+
+`resetall
+`timescale 1 ns / 1 ps
+`default_nettype none
+
+/*
+ * Synchronizes an active-high asynchronous reset signal to a given clock by
+ * using a pipeline of N registers.
+ */
+module sync_reset #(
+    parameter N=2 // depth of synchronizer
+)(
+    input wire clk,
+    input wire rst,
+    output wire sync_reset_out
+);
+
+reg [N-1:0] sync_reg = {N{1'b1}};
+
+assign sync_reset_out = sync_reg[N-1];
+
+always @(posedge clk or posedge rst) begin
+    if (rst)
+        sync_reg <= {N{1'b1}};
+    else
+        sync_reg <= {sync_reg[N-2:0], 1'b0};
+end
+
+endmodule
+
+`resetall

snapshots/alexforencich_verilog-pcie_pr20/example/AU50/fpga/rtl/sync_signal.v

@@ -0,0 +1,62 @@
+/*
+
+Copyright (c) 2014-2018 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog-2001
+
+`resetall
+`timescale 1 ns / 1 ps
+`default_nettype none
+
+/*
+ * Synchronizes an asyncronous signal to a given clock by using a pipeline of
+ * two registers.
+ */
+module sync_signal #(
+    parameter WIDTH=1, // width of the input and output signals
+    parameter N=2 // depth of synchronizer
+)(
+    input wire clk,
+    input wire [WIDTH-1:0] in,
+    output wire [WIDTH-1:0] out
+);
+
+reg [WIDTH-1:0] sync_reg[N-1:0];
+
+/*
+ * The synchronized output is the last register in the pipeline.
+ */
+assign out = sync_reg[N-1];
+
+integer k;
+
+always @(posedge clk) begin
+    sync_reg[0] <= in;
+    for (k = 1; k < N; k = k + 1) begin
+        sync_reg[k] <= sync_reg[k-1];
+    end
+end
+
+endmodule
+
+`resetall

snapshots/alexforencich_verilog-pcie_pr20/example/AU50/fpga/tb/fpga_core/Makefile

@@ -0,0 +1,123 @@
+# Copyright (c) 2020 Alex Forencich
+#
+# Permission is hereby granted, free of charge, to any person obtaining a copy
+# of this software and associated documentation files (the "Software"), to deal
+# in the Software without restriction, including without limitation the rights
+# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+# copies of the Software, and to permit persons to whom the Software is
+# furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+# THE SOFTWARE.
+
+TOPLEVEL_LANG = verilog
+
+SIM ?= icarus
+WAVES ?= 0
+
+COCOTB_HDL_TIMEUNIT = 1ns
+COCOTB_HDL_TIMEPRECISION = 1ps
+
+DUT      = fpga_core
+TOPLEVEL = $(DUT)
+MODULE   = test_$(DUT)
+VERILOG_SOURCES += ../../rtl/$(DUT).v
+VERILOG_SOURCES += ../../rtl/common/example_core_pcie_us.v
+VERILOG_SOURCES += ../../rtl/common/example_core_pcie.v
+VERILOG_SOURCES += ../../rtl/common/example_core.v
+VERILOG_SOURCES += ../../rtl/common/axi_ram.v
+VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if.v
+VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_rc.v
+VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_rq.v
+VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cq.v
+VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_if_cc.v
+VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_cfg.v
+VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_msi.v
+VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axil_master.v
+VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axi_master.v
+VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axi_master_rd.v
+VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_axi_master_wr.v
+VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux_bar.v
+VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_demux.v
+VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_tlp_mux.v
+VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie.v
+VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_rd.v
+VERILOG_SOURCES += ../../lib/pcie/rtl/dma_if_pcie_wr.v
+VERILOG_SOURCES += ../../lib/pcie/rtl/dma_psdpram.v
+VERILOG_SOURCES += ../../lib/pcie/rtl/arbiter.v
+VERILOG_SOURCES += ../../lib/pcie/rtl/priority_encoder.v
+VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v
+
+# module parameters
+export PARAM_AXIS_PCIE_DATA_WIDTH ?= 512
+export PARAM_AXIS_PCIE_KEEP_WIDTH ?= $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 )
+export PARAM_AXIS_PCIE_RQ_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),62,137)
+export PARAM_AXIS_PCIE_RC_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),75,161)
+export PARAM_AXIS_PCIE_CQ_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),88,183)
+export PARAM_AXIS_PCIE_CC_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),33,81)
+export PARAM_RQ_SEQ_NUM_WIDTH ?= 6
+export PARAM_RQ_SEQ_NUM_ENABLE ?= 1
+export PARAM_PCIE_TAG_COUNT ?= 64
+export PARAM_BAR0_APERTURE ?= 24
+export PARAM_BAR2_APERTURE ?= 24
+
+ifeq ($(SIM), icarus)
+	PLUSARGS += -fst
+
+	COMPILE_ARGS += -P $(TOPLEVEL).AXIS_PCIE_DATA_WIDTH=$(PARAM_AXIS_PCIE_DATA_WIDTH)
+	COMPILE_ARGS += -P $(TOPLEVEL).AXIS_PCIE_KEEP_WIDTH=$(PARAM_AXIS_PCIE_KEEP_WIDTH)
+	COMPILE_ARGS += -P $(TOPLEVEL).AXIS_PCIE_RQ_USER_WIDTH=$(PARAM_AXIS_PCIE_RQ_USER_WIDTH)
+	COMPILE_ARGS += -P $(TOPLEVEL).AXIS_PCIE_RC_USER_WIDTH=$(PARAM_AXIS_PCIE_RC_USER_WIDTH)
+	COMPILE_ARGS += -P $(TOPLEVEL).AXIS_PCIE_CQ_USER_WIDTH=$(PARAM_AXIS_PCIE_CQ_USER_WIDTH)
+	COMPILE_ARGS += -P $(TOPLEVEL).AXIS_PCIE_CC_USER_WIDTH=$(PARAM_AXIS_PCIE_CC_USER_WIDTH)
+	COMPILE_ARGS += -P $(TOPLEVEL).RQ_SEQ_NUM_WIDTH=$(PARAM_RQ_SEQ_NUM_WIDTH)
+	COMPILE_ARGS += -P $(TOPLEVEL).RQ_SEQ_NUM_ENABLE=$(PARAM_RQ_SEQ_NUM_ENABLE)
+	COMPILE_ARGS += -P $(TOPLEVEL).PCIE_TAG_COUNT=$(PARAM_PCIE_TAG_COUNT)
+	COMPILE_ARGS += -P $(TOPLEVEL).BAR0_APERTURE=$(PARAM_BAR0_APERTURE)
+	COMPILE_ARGS += -P $(TOPLEVEL).BAR2_APERTURE=$(PARAM_BAR2_APERTURE)
+
+	ifeq ($(WAVES), 1)
+		VERILOG_SOURCES += iverilog_dump.v
+		COMPILE_ARGS += -s iverilog_dump
+	endif
+else ifeq ($(SIM), verilator)
+	COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH
+
+	COMPILE_ARGS += -GAXIS_PCIE_DATA_WIDTH=$(PARAM_AXIS_PCIE_DATA_WIDTH)
+	COMPILE_ARGS += -GAXIS_PCIE_KEEP_WIDTH=$(PARAM_AXIS_PCIE_KEEP_WIDTH)
+	COMPILE_ARGS += -GAXIS_PCIE_RQ_USER_WIDTH=$(PARAM_AXIS_PCIE_RQ_USER_WIDTH)
+	COMPILE_ARGS += -GAXIS_PCIE_RC_USER_WIDTH=$(PARAM_AXIS_PCIE_RC_USER_WIDTH)
+	COMPILE_ARGS += -GAXIS_PCIE_CQ_USER_WIDTH=$(PARAM_AXIS_PCIE_CQ_USER_WIDTH)
+	COMPILE_ARGS += -GAXIS_PCIE_CC_USER_WIDTH=$(PARAM_AXIS_PCIE_CC_USER_WIDTH)
+	COMPILE_ARGS += -GRQ_SEQ_NUM_WIDTH=$(PARAM_RQ_SEQ_NUM_WIDTH)
+	COMPILE_ARGS += -GRQ_SEQ_NUM_ENABLE=$(PARAM_RQ_SEQ_NUM_ENABLE)
+	COMPILE_ARGS += -GPCIE_TAG_COUNT=$(PARAM_PCIE_TAG_COUNT)
+	COMPILE_ARGS += -GBAR0_APERTURE=$(PARAM_BAR0_APERTURE)
+	COMPILE_ARGS += -GBAR2_APERTURE=$(PARAM_BAR2_APERTURE)
+
+	ifeq ($(WAVES), 1)
+		COMPILE_ARGS += --trace-fst
+	endif
+endif
+
+include $(shell cocotb-config --makefiles)/Makefile.sim
+
+iverilog_dump.v:
+	echo 'module iverilog_dump();' > $@
+	echo 'initial begin' >> $@
+	echo '    $$dumpfile("$(TOPLEVEL).fst");' >> $@
+	echo '    $$dumpvars(0, $(TOPLEVEL));' >> $@
+	echo 'end' >> $@
+	echo 'endmodule' >> $@
+
+clean::
+	@rm -rf iverilog_dump.v
+	@rm -rf dump.fst $(TOPLEVEL).fst

snapshots/alexforencich_verilog-pcie_pr20/example/AU50/fpga/tb/fpga_core/test_fpga_core.py

@@ -0,0 +1,472 @@
+"""
+
+Copyright (c) 2020 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+"""
+
+import logging
+import os
+
+import cocotb_test.simulator
+
+import cocotb
+from cocotb.log import SimLog
+from cocotb.triggers import RisingEdge, FallingEdge, Timer
+
+from cocotbext.axi import AxiStreamBus
+from cocotbext.pcie.core import RootComplex
+from cocotbext.pcie.xilinx.us import UltraScalePlusPcieDevice
+
+
+class TB(object):
+    def __init__(self, dut):
+        self.dut = dut
+
+        self.log = SimLog("cocotb.tb")
+        self.log.setLevel(logging.DEBUG)
+
+        # PCIe
+        self.rc = RootComplex()
+
+        self.dev = UltraScalePlusPcieDevice(
+            # configuration options
+            pcie_generation=3,
+            pcie_link_width=16,
+            user_clk_frequency=250e6,
+            alignment="dword",
+            cq_cc_straddle=False,
+            rq_rc_straddle=False,
+            rc_4tlp_straddle=False,
+            enable_pf1=False,
+            enable_client_tag=True,
+            enable_extended_tag=True,
+            enable_parity=False,
+            enable_rx_msg_interface=False,
+            enable_sriov=False,
+            enable_extended_configuration=False,
+
+            enable_pf0_msi=True,
+            enable_pf1_msi=False,
+
+            # signals
+            # Clock and Reset Interface
+            user_clk=dut.clk,
+            user_reset=dut.rst,
+            # user_lnk_up
+            # sys_clk
+            # sys_clk_gt
+            # sys_reset
+            # phy_rdy_out
+
+            # Requester reQuest Interface
+            rq_bus=AxiStreamBus.from_prefix(dut, "m_axis_rq"),
+            pcie_rq_seq_num0=dut.s_axis_rq_seq_num_0,
+            pcie_rq_seq_num_vld0=dut.s_axis_rq_seq_num_valid_0,
+            pcie_rq_seq_num1=dut.s_axis_rq_seq_num_1,
+            pcie_rq_seq_num_vld1=dut.s_axis_rq_seq_num_valid_1,
+            # pcie_rq_tag0
+            # pcie_rq_tag1
+            # pcie_rq_tag_av
+            # pcie_rq_tag_vld0
+            # pcie_rq_tag_vld1
+
+            # Requester Completion Interface
+            rc_bus=AxiStreamBus.from_prefix(dut, "s_axis_rc"),
+
+            # Completer reQuest Interface
+            cq_bus=AxiStreamBus.from_prefix(dut, "s_axis_cq"),
+            # pcie_cq_np_req
+            # pcie_cq_np_req_count
+
+            # Completer Completion Interface
+            cc_bus=AxiStreamBus.from_prefix(dut, "m_axis_cc"),
+
+            # Transmit Flow Control Interface
+            # pcie_tfc_nph_av=dut.pcie_tfc_nph_av,
+            # pcie_tfc_npd_av=dut.pcie_tfc_npd_av,
+
+            # Configuration Management Interface
+            cfg_mgmt_addr=dut.cfg_mgmt_addr,
+            cfg_mgmt_function_number=dut.cfg_mgmt_function_number,
+            cfg_mgmt_write=dut.cfg_mgmt_write,
+            cfg_mgmt_write_data=dut.cfg_mgmt_write_data,
+            cfg_mgmt_byte_enable=dut.cfg_mgmt_byte_enable,
+            cfg_mgmt_read=dut.cfg_mgmt_read,
+            cfg_mgmt_read_data=dut.cfg_mgmt_read_data,
+            cfg_mgmt_read_write_done=dut.cfg_mgmt_read_write_done,
+            # cfg_mgmt_debug_access
+
+            # Configuration Status Interface
+            # cfg_phy_link_down
+            # cfg_phy_link_status
+            # cfg_negotiated_width
+            # cfg_current_speed
+            cfg_max_payload=dut.cfg_max_payload,
+            cfg_max_read_req=dut.cfg_max_read_req,
+            # cfg_function_status
+            # cfg_vf_status
+            # cfg_function_power_state
+            # cfg_vf_power_state
+            # cfg_link_power_state
+            # cfg_err_cor_out
+            # cfg_err_nonfatal_out
+            # cfg_err_fatal_out
+            # cfg_local_error_out
+            # cfg_local_error_valid
+            # cfg_rx_pm_state
+            # cfg_tx_pm_state
+            # cfg_ltssm_state
+            # cfg_rcb_status
+            # cfg_obff_enable
+            # cfg_pl_status_change
+            # cfg_tph_requester_enable
+            # cfg_tph_st_mode
+            # cfg_vf_tph_requester_enable
+            # cfg_vf_tph_st_mode
+
+            # Configuration Received Message Interface
+            # cfg_msg_received
+            # cfg_msg_received_data
+            # cfg_msg_received_type
+
+            # Configuration Transmit Message Interface
+            # cfg_msg_transmit
+            # cfg_msg_transmit_type
+            # cfg_msg_transmit_data
+            # cfg_msg_transmit_done
+
+            # Configuration Flow Control Interface
+            cfg_fc_ph=dut.cfg_fc_ph,
+            cfg_fc_pd=dut.cfg_fc_pd,
+            cfg_fc_nph=dut.cfg_fc_nph,
+            cfg_fc_npd=dut.cfg_fc_npd,
+            cfg_fc_cplh=dut.cfg_fc_cplh,
+            cfg_fc_cpld=dut.cfg_fc_cpld,
+            cfg_fc_sel=dut.cfg_fc_sel,
+
+            # Configuration Control Interface
+            # cfg_hot_reset_in
+            # cfg_hot_reset_out
+            # cfg_config_space_enable
+            # cfg_dsn
+            # cfg_bus_number
+            # cfg_ds_port_number
+            # cfg_ds_bus_number
+            # cfg_ds_device_number
+            # cfg_ds_function_number
+            # cfg_power_state_change_ack
+            # cfg_power_state_change_interrupt
+            cfg_err_cor_in=dut.status_error_cor,
+            cfg_err_uncor_in=dut.status_error_uncor,
+            # cfg_flr_in_process
+            # cfg_flr_done
+            # cfg_vf_flr_in_process
+            # cfg_vf_flr_func_num
+            # cfg_vf_flr_done
+            # cfg_pm_aspm_l1_entry_reject
+            # cfg_pm_aspm_tx_l0s_entry_disable
+            # cfg_req_pm_transition_l23_ready
+            # cfg_link_training_enable
+
+            # Configuration Interrupt Controller Interface
+            # cfg_interrupt_int
+            # cfg_interrupt_sent
+            # cfg_interrupt_pending
+            cfg_interrupt_msi_enable=dut.cfg_interrupt_msi_enable,
+            cfg_interrupt_msi_mmenable=dut.cfg_interrupt_msi_mmenable,
+            cfg_interrupt_msi_mask_update=dut.cfg_interrupt_msi_mask_update,
+            cfg_interrupt_msi_data=dut.cfg_interrupt_msi_data,
+            # cfg_interrupt_msi_select=dut.cfg_interrupt_msi_select,
+            cfg_interrupt_msi_int=dut.cfg_interrupt_msi_int,
+            cfg_interrupt_msi_pending_status=dut.cfg_interrupt_msi_pending_status,
+            cfg_interrupt_msi_pending_status_data_enable=dut.cfg_interrupt_msi_pending_status_data_enable,
+            # cfg_interrupt_msi_pending_status_function_num=dut.cfg_interrupt_msi_pending_status_function_num,
+            cfg_interrupt_msi_sent=dut.cfg_interrupt_msi_sent,
+            cfg_interrupt_msi_fail=dut.cfg_interrupt_msi_fail,
+            # cfg_interrupt_msix_enable
+            # cfg_interrupt_msix_mask
+            # cfg_interrupt_msix_vf_enable
+            # cfg_interrupt_msix_vf_mask
+            # cfg_interrupt_msix_address
+            # cfg_interrupt_msix_data
+            # cfg_interrupt_msix_int
+            # cfg_interrupt_msix_vec_pending
+            # cfg_interrupt_msix_vec_pending_status
+            cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr,
+            cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present,
+            cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type,
+            # cfg_interrupt_msi_tph_st_tag=dut.cfg_interrupt_msi_tph_st_tag,
+            # cfg_interrupt_msi_function_number=dut.cfg_interrupt_msi_function_number,
+
+            # Configuration Extend Interface
+            # cfg_ext_read_received
+            # cfg_ext_write_received
+            # cfg_ext_register_number
+            # cfg_ext_function_number
+            # cfg_ext_write_data
+            # cfg_ext_write_byte_enable
+            # cfg_ext_read_data
+            # cfg_ext_read_data_valid
+        )
+
+        # self.dev.log.setLevel(logging.DEBUG)
+
+        self.rc.make_port().connect(self.dev)
+
+        self.dev.functions[0].msi_multiple_message_capable = 5
+
+        self.dev.functions[0].configure_bar(0, 2**len(dut.example_core_pcie_us_inst.core_pcie_inst.axil_ctrl_awaddr))
+        self.dev.functions[0].configure_bar(2, 2**len(dut.example_core_pcie_us_inst.core_pcie_inst.axi_ram_awaddr))
+
+    async def init(self):
+
+        await FallingEdge(self.dut.rst)
+        await Timer(100, 'ns')
+
+        await self.rc.enumerate(enable_bus_mastering=True, configure_msi=True)
+
+
+@cocotb.test()
+async def run_test(dut):
+
+    tb = TB(dut)
+
+    await tb.init()
+
+    mem = tb.rc.mem_pool.alloc_region(16*1024*1024)
+    mem_base = mem.get_absolute_address(0)
+
+    dev_pf0_bar0 = tb.rc.tree[0][0].bar_window[0]
+    dev_pf0_bar2 = tb.rc.tree[0][0].bar_window[2]
+
+    tb.log.info("Test memory write to BAR 2")
+
+    test_data = b'\x11\x22\x33\x44'
+    await dev_pf0_bar2.write(0, test_data)
+
+    await Timer(100, 'ns')
+
+    tb.log.info("Test memory read from BAR 2")
+
+    val = await dev_pf0_bar2.read(0, len(test_data), timeout=1000)
+    tb.log.info("Read data: %s", val)
+    assert val == test_data
+
+    tb.log.info("Test DMA")
+
+    # write packet data
+    mem[0:1024] = bytearray([x % 256 for x in range(1024)])
+
+    # enable DMA
+    await dev_pf0_bar0.write_dword(0x000000, 1)
+
+    # write pcie read descriptor
+    await dev_pf0_bar0.write_dword(0x000100, (mem_base+0x0000) & 0xffffffff)
+    await dev_pf0_bar0.write_dword(0x000104, (mem_base+0x0000 >> 32) & 0xffffffff)
+    await dev_pf0_bar0.write_dword(0x000108, 0x100)
+    await dev_pf0_bar0.write_dword(0x000110, 0x400)
+    await dev_pf0_bar0.write_dword(0x000114, 0xAA)
+
+    await Timer(2000, 'ns')
+
+    # read status
+    val = await dev_pf0_bar0.read_dword(0x000118)
+    tb.log.info("Status: 0x%x", val)
+    assert val == 0x800000AA
+
+    # write pcie write descriptor
+    await dev_pf0_bar0.write_dword(0x000200, (mem_base+0x1000) & 0xffffffff)
+    await dev_pf0_bar0.write_dword(0x000204, (mem_base+0x1000 >> 32) & 0xffffffff)
+    await dev_pf0_bar0.write_dword(0x000208, 0x100)
+    await dev_pf0_bar0.write_dword(0x000210, 0x400)
+    await dev_pf0_bar0.write_dword(0x000214, 0x55)
+
+    await Timer(2000, 'ns')
+
+    # read status
+    val = await dev_pf0_bar0.read_dword(0x000218)
+    tb.log.info("Status: 0x%x", val)
+    assert val == 0x80000055
+
+    tb.log.info("%s", mem.hexdump_str(0x1000, 64))
+
+    assert mem[0:1024] == mem[0x1000:0x1000+1024]
+
+    tb.log.info("Test DMA block operations")
+
+    # write packet data
+    mem[0:1024] = bytearray([x % 256 for x in range(1024)])
+
+    # enable DMA
+    await dev_pf0_bar0.write_dword(0x000000, 1)
+    # disable interrupts
+    await dev_pf0_bar0.write_dword(0x000008, 0)
+
+    # configure operation (read)
+    # DMA base address
+    await dev_pf0_bar0.write_dword(0x001080, (mem_base+0x0000) & 0xffffffff)
+    await dev_pf0_bar0.write_dword(0x001084, (mem_base+0x0000 >> 32) & 0xffffffff)
+    # DMA offset address
+    await dev_pf0_bar0.write_dword(0x001088, 0)
+    await dev_pf0_bar0.write_dword(0x00108c, 0)
+    # DMA offset mask
+    await dev_pf0_bar0.write_dword(0x001090, 0x000003ff)
+    await dev_pf0_bar0.write_dword(0x001094, 0)
+    # DMA stride
+    await dev_pf0_bar0.write_dword(0x001098, 256)
+    await dev_pf0_bar0.write_dword(0x00109c, 0)
+    # RAM base address
+    await dev_pf0_bar0.write_dword(0x0010c0, 0)
+    await dev_pf0_bar0.write_dword(0x0010c4, 0)
+    # RAM offset address
+    await dev_pf0_bar0.write_dword(0x0010c8, 0)
+    await dev_pf0_bar0.write_dword(0x0010cc, 0)
+    # RAM offset mask
+    await dev_pf0_bar0.write_dword(0x0010d0, 0x000003ff)
+    await dev_pf0_bar0.write_dword(0x0010d4, 0)
+    # RAM stride
+    await dev_pf0_bar0.write_dword(0x0010d8, 256)
+    await dev_pf0_bar0.write_dword(0x0010dc, 0)
+    # clear cycle count
+    await dev_pf0_bar0.write_dword(0x001008, 0)
+    await dev_pf0_bar0.write_dword(0x00100c, 0)
+    # block length
+    await dev_pf0_bar0.write_dword(0x001010, 256)
+    # block count
+    await dev_pf0_bar0.write_dword(0x001018, 32)
+    await dev_pf0_bar0.write_dword(0x00101c, 0)
+    # start
+    await dev_pf0_bar0.write_dword(0x001000, 1)
+
+    await Timer(2000, 'ns')
+
+    # configure operation (write)
+    # DMA base address
+    await dev_pf0_bar0.write_dword(0x001180, (mem_base+0x0000) & 0xffffffff)
+    await dev_pf0_bar0.write_dword(0x001184, (mem_base+0x0000 >> 32) & 0xffffffff)
+    # DMA offset address
+    await dev_pf0_bar0.write_dword(0x001188, 0)
+    await dev_pf0_bar0.write_dword(0x00118c, 0)
+    # DMA offset mask
+    await dev_pf0_bar0.write_dword(0x001190, 0x000003ff)
+    await dev_pf0_bar0.write_dword(0x001194, 0)
+    # DMA stride
+    await dev_pf0_bar0.write_dword(0x001198, 256)
+    await dev_pf0_bar0.write_dword(0x00119c, 0)
+    # RAM base address
+    await dev_pf0_bar0.write_dword(0x0011c0, 0)
+    await dev_pf0_bar0.write_dword(0x0011c4, 0)
+    # RAM offset address
+    await dev_pf0_bar0.write_dword(0x0011c8, 0)
+    await dev_pf0_bar0.write_dword(0x0011cc, 0)
+    # RAM offset mask
+    await dev_pf0_bar0.write_dword(0x0011d0, 0x000003ff)
+    await dev_pf0_bar0.write_dword(0x0011d4, 0)
+    # RAM stride
+    await dev_pf0_bar0.write_dword(0x0011d8, 256)
+    await dev_pf0_bar0.write_dword(0x0011dc, 0)
+    # clear cycle count
+    await dev_pf0_bar0.write_dword(0x001108, 0)
+    await dev_pf0_bar0.write_dword(0x00110c, 0)
+    # block length
+    await dev_pf0_bar0.write_dword(0x001110, 256)
+    # block count
+    await dev_pf0_bar0.write_dword(0x001118, 32)
+    await dev_pf0_bar0.write_dword(0x00111c, 0)
+    # start
+    await dev_pf0_bar0.write_dword(0x001100, 1)
+
+    await Timer(2000, 'ns')
+
+    await RisingEdge(dut.clk)
+    await RisingEdge(dut.clk)
+
+
+# cocotb-test
+
+tests_dir = os.path.dirname(__file__)
+rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
+lib_dir = os.path.abspath(os.path.join(rtl_dir, '..', 'lib'))
+pcie_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'pcie', 'rtl'))
+
+
+def test_fpga_core(request):
+    dut = "fpga_core"
+    module = os.path.splitext(os.path.basename(__file__))[0]
+    toplevel = dut
+
+    verilog_sources = [
+        os.path.join(rtl_dir, f"{dut}.v"),
+        os.path.join(rtl_dir, "common", "example_core_pcie_us.v"),
+        os.path.join(rtl_dir, "common", "example_core_pcie.v"),
+        os.path.join(rtl_dir, "common", "example_core.v"),
+        os.path.join(rtl_dir, "common", "axi_ram.v"),
+        os.path.join(pcie_rtl_dir, "pcie_us_if.v"),
+        os.path.join(pcie_rtl_dir, "pcie_us_if_rc.v"),
+        os.path.join(pcie_rtl_dir, "pcie_us_if_rq.v"),
+        os.path.join(pcie_rtl_dir, "pcie_us_if_cq.v"),
+        os.path.join(pcie_rtl_dir, "pcie_us_if_cc.v"),
+        os.path.join(pcie_rtl_dir, "pcie_us_cfg.v"),
+        os.path.join(pcie_rtl_dir, "pcie_us_msi.v"),
+        os.path.join(pcie_rtl_dir, "pcie_axil_master.v"),
+        os.path.join(pcie_rtl_dir, "pcie_axi_master.v"),
+        os.path.join(pcie_rtl_dir, "pcie_axi_master_rd.v"),
+        os.path.join(pcie_rtl_dir, "pcie_axi_master_wr.v"),
+        os.path.join(pcie_rtl_dir, "pcie_tlp_demux_bar.v"),
+        os.path.join(pcie_rtl_dir, "pcie_tlp_demux.v"),
+        os.path.join(pcie_rtl_dir, "pcie_tlp_mux.v"),
+        os.path.join(pcie_rtl_dir, "dma_if_pcie.v"),
+        os.path.join(pcie_rtl_dir, "dma_if_pcie_rd.v"),
+        os.path.join(pcie_rtl_dir, "dma_if_pcie_wr.v"),
+        os.path.join(pcie_rtl_dir, "dma_psdpram.v"),
+        os.path.join(pcie_rtl_dir, "arbiter.v"),
+        os.path.join(pcie_rtl_dir, "priority_encoder.v"),
+        os.path.join(pcie_rtl_dir, "pulse_merge.v"),
+    ]
+
+    parameters = {}
+
+    parameters['AXIS_PCIE_DATA_WIDTH'] = 512
+    parameters['AXIS_PCIE_KEEP_WIDTH'] = parameters['AXIS_PCIE_DATA_WIDTH'] // 32
+    parameters['AXIS_PCIE_RQ_USER_WIDTH'] = 62 if parameters['AXIS_PCIE_DATA_WIDTH'] < 512 else 137
+    parameters['AXIS_PCIE_RC_USER_WIDTH'] = 75 if parameters['AXIS_PCIE_DATA_WIDTH'] < 512 else 161
+    parameters['AXIS_PCIE_CQ_USER_WIDTH'] = 88 if parameters['AXIS_PCIE_DATA_WIDTH'] < 512 else 183
+    parameters['AXIS_PCIE_CC_USER_WIDTH'] = 33 if parameters['AXIS_PCIE_DATA_WIDTH'] < 512 else 81
+    parameters['RQ_SEQ_NUM_WIDTH'] = 6
+    parameters['RQ_SEQ_NUM_ENABLE'] = 1
+    parameters['PCIE_TAG_COUNT'] = 64
+    parameters['BAR0_APERTURE'] = 24
+    parameters['BAR2_APERTURE'] = 24
+
+    extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
+
+    sim_build = os.path.join(tests_dir, "sim_build",
+        request.node.name.replace('[', '-').replace(']', ''))
+
+    cocotb_test.simulator.run(
+        python_search=[tests_dir],
+        verilog_sources=verilog_sources,
+        toplevel=toplevel,
+        module=module,
+        parameters=parameters,
+        sim_build=sim_build,
+        extra_env=extra_env,
+    )

snapshots/alexforencich_verilog-pcie_pr20/example/AU50/fpga_axi/common/vivado.mk

@@ -0,0 +1,126 @@
+###################################################################
+# 
+# Xilinx Vivado FPGA Makefile
+# 
+# Copyright (c) 2016 Alex Forencich
+# 
+###################################################################
+# 
+# Parameters:
+# FPGA_TOP - Top module name
+# FPGA_FAMILY - FPGA family (e.g. VirtexUltrascale)
+# FPGA_DEVICE - FPGA device (e.g. xcvu095-ffva2104-2-e)
+# SYN_FILES - space-separated list of source files
+# INC_FILES - space-separated list of include files
+# XDC_FILES - space-separated list of timing constraint files
+# XCI_FILES - space-separated list of IP XCI files
+# 
+# Example:
+# 
+# FPGA_TOP = fpga
+# FPGA_FAMILY = VirtexUltrascale
+# FPGA_DEVICE = xcvu095-ffva2104-2-e
+# SYN_FILES = rtl/fpga.v
+# XDC_FILES = fpga.xdc
+# XCI_FILES = ip/pcspma.xci
+# include ../common/vivado.mk
+# 
+###################################################################
+
+# phony targets
+.PHONY: fpga vivado tmpclean clean distclean
+
+# prevent make from deleting intermediate files and reports
+.PRECIOUS: %.xpr %.bit %.mcs %.prm
+.SECONDARY:
+
+CONFIG ?= config.mk
+-include ../$(CONFIG)
+
+SYN_FILES_REL = $(patsubst %, ../%, $(filter-out /% ./%,$(SYN_FILES))) $(filter /% ./%,$(SYN_FILES))
+INC_FILES_REL = $(patsubst %, ../%, $(filter-out /% ./%,$(INC_FILES))) $(filter /% ./%,$(INC_FILES))
+XCI_FILES_REL = $(patsubst %, ../%, $(filter-out /% ./%,$(XCI_FILES))) $(filter /% ./%,$(XCI_FILES))
+IP_TCL_FILES_REL = $(patsubst %, ../%, $(filter-out /% ./%,$(IP_TCL_FILES))) $(filter /% ./%,$(IP_TCL_FILES))
+CONFIG_TCL_FILES_REL = $(patsubst %, ../%, $(filter-out /% ./%,$(CONFIG_TCL_FILES))) $(filter /% ./%,$(CONFIG_TCL_FILES))
+
+ifdef XDC_FILES
+  XDC_FILES_REL = $(patsubst %, ../%, $(filter-out /% ./%,$(XDC_FILES))) $(filter /% ./%,$(XDC_FILES))
+else
+  XDC_FILES_REL = $(FPGA_TOP).xdc
+endif
+
+###################################################################
+# Main Targets
+#
+# all: build everything
+# clean: remove output files and project files
+###################################################################
+
+all: fpga
+
+fpga: $(FPGA_TOP).bit
+
+vivado: $(FPGA_TOP).xpr
+	vivado $(FPGA_TOP).xpr
+
+tmpclean::
+	-rm -rf *.log *.jou *.cache *.gen *.hbs *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v
+	-rm -rf create_project.tcl update_config.tcl run_synth.tcl run_impl.tcl generate_bit.tcl
+
+clean:: tmpclean
+	-rm -rf *.bit program.tcl generate_mcs.tcl *.mcs *.prm flash.tcl
+
+distclean:: clean
+	-rm -rf rev
+
+###################################################################
+# Target implementations
+###################################################################
+
+# Vivado project file
+create_project.tcl: Makefile $(XCI_FILES_REL) $(IP_TCL_FILES_REL)
+	rm -rf defines.v
+	touch defines.v
+	for x in $(DEFS); do echo '`define' $$x >> defines.v; done
+	echo "create_project -force -part $(FPGA_PART) $(FPGA_TOP)" > $@
+	echo "add_files -fileset sources_1 defines.v $(SYN_FILES_REL)" >> $@
+	echo "add_files -fileset constrs_1 $(XDC_FILES_REL)" >> $@
+	for x in $(XCI_FILES_REL); do echo "import_ip $$x" >> $@; done
+	for x in $(IP_TCL_FILES_REL); do echo "source $$x" >> $@; done
+	for x in $(CONFIG_TCL_FILES_REL); do echo "source $$x" >> $@; done
+
+update_config.tcl: $(CONFIG_TCL_FILES_REL)
+	echo "open_project -quiet $(FPGA_TOP).xpr" > $@
+	for x in $(CONFIG_TCL_FILES_REL); do echo "source $$x" >> $@; done
+
+$(FPGA_TOP).xpr: create_project.tcl update_config.tcl
+	vivado -nojournal -nolog -mode batch $(foreach x,$?,-source $x)
+
+# synthesis run
+%.runs/synth_1/%.dcp: %.xpr $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL) $(CONFIG_TCL_FILES_REL)
+	echo "open_project $*.xpr" > run_synth.tcl
+	echo "reset_run synth_1" >> run_synth.tcl
+	echo "launch_runs -jobs 4 synth_1" >> run_synth.tcl
+	echo "wait_on_run synth_1" >> run_synth.tcl
+	vivado -nojournal -nolog -mode batch -source run_synth.tcl
+
+# implementation run
+%.runs/impl_1/%_routed.dcp: %.runs/synth_1/%.dcp
+	echo "open_project $*.xpr" > run_impl.tcl
+	echo "reset_run impl_1" >> run_impl.tcl
+	echo "launch_runs -jobs 4 impl_1" >> run_impl.tcl
+	echo "wait_on_run impl_1" >> run_impl.tcl
+	vivado -nojournal -nolog -mode batch -source run_impl.tcl
+
+# bit file
+%.bit: %.runs/impl_1/%_routed.dcp
+	echo "open_project $*.xpr" > generate_bit.tcl
+	echo "open_run impl_1" >> generate_bit.tcl
+	echo "write_bitstream -force $*.bit" >> generate_bit.tcl
+	vivado -nojournal -nolog -mode batch -source generate_bit.tcl
+	mkdir -p rev
+	EXT=bit; COUNT=100; \
+	while [ -e rev/$*_rev$$COUNT.$$EXT ]; \
+	do COUNT=$$((COUNT+1)); done; \
+	cp $@ rev/$*_rev$$COUNT.$$EXT; \
+	echo "Output: rev/$*_rev$$COUNT.$$EXT";

snapshots/alexforencich_verilog-pcie_pr20/example/AU50/fpga_axi/fpga/Makefile

@@ -0,0 +1,84 @@
+
+# FPGA settings
+FPGA_PART = xcu50-fsvh2104-2-e
+FPGA_TOP = fpga
+FPGA_ARCH = virtexuplus
+
+# Files for synthesis
+SYN_FILES = rtl/fpga.v
+SYN_FILES += rtl/fpga_core.v
+SYN_FILES += rtl/sync_reset.v
+SYN_FILES += rtl/sync_signal.v
+SYN_FILES += rtl/axi_ram.v
+SYN_FILES += rtl/axis_register.v
+SYN_FILES += lib/pcie/rtl/axis_arb_mux.v
+SYN_FILES += lib/pcie/rtl/pcie_us_axil_master.v
+SYN_FILES += lib/pcie/rtl/pcie_us_axi_dma.v
+SYN_FILES += lib/pcie/rtl/pcie_us_axi_dma_rd.v
+SYN_FILES += lib/pcie/rtl/pcie_us_axi_dma_wr.v
+SYN_FILES += lib/pcie/rtl/pcie_us_axi_master.v
+SYN_FILES += lib/pcie/rtl/pcie_us_axi_master_rd.v
+SYN_FILES += lib/pcie/rtl/pcie_us_axi_master_wr.v
+SYN_FILES += lib/pcie/rtl/pcie_us_axis_cq_demux.v
+SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v
+SYN_FILES += lib/pcie/rtl/pcie_us_msi.v
+SYN_FILES += lib/pcie/rtl/arbiter.v
+SYN_FILES += lib/pcie/rtl/priority_encoder.v
+SYN_FILES += lib/pcie/rtl/pulse_merge.v
+
+# XDC files
+XDC_FILES = fpga.xdc
+
+# IP
+IP_TCL_FILES = ip/pcie4c_uscale_plus_0.tcl
+
+include ../common/vivado.mk
+
+program: $(FPGA_TOP).bit
+	echo "open_hw" > program.tcl
+	echo "connect_hw_server" >> program.tcl
+	echo "open_hw_target" >> program.tcl
+	echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
+	echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
+	echo "set_property PROGRAM.FILE {$(FPGA_TOP).bit} [current_hw_device]" >> program.tcl
+	echo "program_hw_devices [current_hw_device]" >> program.tcl
+	echo "exit" >> program.tcl
+	vivado -nojournal -nolog -mode batch -source program.tcl
+
+%.mcs %.prm: %.bit
+	echo "write_cfgmem -force -format mcs -size 128 -interface SPIx4 -loadbit {up 0x01002000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl
+	echo "exit" >> generate_mcs.tcl
+	vivado -nojournal -nolog -mode batch -source generate_mcs.tcl
+	mkdir -p rev
+	COUNT=100; \
+	while [ -e rev/$*_rev$$COUNT.bit ]; \
+	do COUNT=$$((COUNT+1)); done; \
+	COUNT=$$((COUNT-1)); \
+	for x in .mcs .prm; \
+	do cp $*$$x rev/$*_rev$$COUNT$$x; \
+	echo "Output: rev/$*_rev$$COUNT$$x"; done;
+
+flash: $(FPGA_TOP).mcs $(FPGA_TOP).prm
+	echo "open_hw" > flash.tcl
+	echo "connect_hw_server" >> flash.tcl
+	echo "open_hw_target" >> flash.tcl
+	echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash.tcl
+	echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash.tcl
+	echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {mt25qu01g-spi-x1_x2_x4}] 0]" >> flash.tcl
+	echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash.tcl
+	echo "set_property PROGRAM.FILES [list \"$(FPGA_TOP).mcs\"] [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.PRM_FILES [list \"$(FPGA_TOP).prm\"] [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash.tcl
+	echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash.tcl
+	echo "program_hw_devices [current_hw_device]" >> flash.tcl
+	echo "refresh_hw_device [current_hw_device]" >> flash.tcl
+	echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash.tcl
+	echo "boot_hw_device [current_hw_device]" >> flash.tcl
+	echo "exit" >> flash.tcl
+	vivado -nojournal -nolog -mode batch -source flash.tcl
+

snapshots/alexforencich_verilog-pcie_pr20/example/AU50/fpga_axi/ip/pcie4c_uscale_plus_0.tcl

@@ -0,0 +1,28 @@
+
+create_ip -name pcie4c_uscale_plus -vendor xilinx.com -library ip -module_name pcie4c_uscale_plus_0
+
+set_property -dict [list \
+    CONFIG.PL_LINK_CAP_MAX_LINK_SPEED {8.0_GT/s} \
+    CONFIG.PL_LINK_CAP_MAX_LINK_WIDTH {X16} \
+    CONFIG.AXISTEN_IF_EXT_512_RQ_STRADDLE {false} \
+    CONFIG.axisten_if_enable_client_tag {true} \
+    CONFIG.axisten_if_width {512_bit} \
+    CONFIG.axisten_freq {250} \
+    CONFIG.PF0_CLASS_CODE {058000} \
+    CONFIG.PF0_DEVICE_ID {0001} \
+    CONFIG.PF0_MSI_CAP_MULTIMSGCAP {32_vectors} \
+    CONFIG.PF0_SUBSYSTEM_ID {9032} \
+    CONFIG.PF0_SUBSYSTEM_VENDOR_ID {10ee} \
+    CONFIG.pf0_bar0_64bit {true} \
+    CONFIG.pf0_bar0_prefetchable {true} \
+    CONFIG.pf0_bar0_scale {Megabytes} \
+    CONFIG.pf0_bar0_size {16} \
+    CONFIG.pf0_bar2_64bit {true} \
+    CONFIG.pf0_bar2_prefetchable {true} \
+    CONFIG.pf0_bar2_enabled {true} \
+    CONFIG.pf0_bar2_type {Memory} \
+    CONFIG.pf0_bar2_scale {Megabytes} \
+    CONFIG.pf0_bar2_size {16} \
+    CONFIG.vendor_id {1234} \
+    CONFIG.en_msi_per_vec_masking {true} \
+] [get_ips pcie4c_uscale_plus_0]

snapshots/alexforencich_verilog-pcie_pr20/example/AU50/fpga_axi/rtl/axi_ram.v

@@ -0,0 +1,369 @@
+/*
+
+Copyright (c) 2018 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog 2001
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * AXI4 RAM
+ */
+module axi_ram #
+(
+    parameter DATA_WIDTH = 32,  // width of data bus in bits
+    parameter ADDR_WIDTH = 16,  // width of address bus in bits
+    parameter STRB_WIDTH = (DATA_WIDTH/8),
+    parameter ID_WIDTH = 8,
+    parameter PIPELINE_OUTPUT = 0
+)
+(
+    input  wire                   clk,
+    input  wire                   rst,
+
+    input  wire [ID_WIDTH-1:0]    s_axi_awid,
+    input  wire [ADDR_WIDTH-1:0]  s_axi_awaddr,
+    input  wire [7:0]             s_axi_awlen,
+    input  wire [2:0]             s_axi_awsize,
+    input  wire [1:0]             s_axi_awburst,
+    input  wire                   s_axi_awlock,
+    input  wire [3:0]             s_axi_awcache,
+    input  wire [2:0]             s_axi_awprot,
+    input  wire                   s_axi_awvalid,
+    output wire                   s_axi_awready,
+    input  wire [DATA_WIDTH-1:0]  s_axi_wdata,
+    input  wire [STRB_WIDTH-1:0]  s_axi_wstrb,
+    input  wire                   s_axi_wlast,
+    input  wire                   s_axi_wvalid,
+    output wire                   s_axi_wready,
+    output wire [ID_WIDTH-1:0]    s_axi_bid,
+    output wire [1:0]             s_axi_bresp,
+    output wire                   s_axi_bvalid,
+    input  wire                   s_axi_bready,
+    input  wire [ID_WIDTH-1:0]    s_axi_arid,
+    input  wire [ADDR_WIDTH-1:0]  s_axi_araddr,
+    input  wire [7:0]             s_axi_arlen,
+    input  wire [2:0]             s_axi_arsize,
+    input  wire [1:0]             s_axi_arburst,
+    input  wire                   s_axi_arlock,
+    input  wire [3:0]             s_axi_arcache,
+    input  wire [2:0]             s_axi_arprot,
+    input  wire                   s_axi_arvalid,
+    output wire                   s_axi_arready,
+    output wire [ID_WIDTH-1:0]    s_axi_rid,
+    output wire [DATA_WIDTH-1:0]  s_axi_rdata,
+    output wire [1:0]             s_axi_rresp,
+    output wire                   s_axi_rlast,
+    output wire                   s_axi_rvalid,
+    input  wire                   s_axi_rready
+);
+
+parameter VALID_ADDR_WIDTH = ADDR_WIDTH - $clog2(STRB_WIDTH);
+parameter WORD_WIDTH = STRB_WIDTH;
+parameter WORD_SIZE = DATA_WIDTH/WORD_WIDTH;
+
+// bus width assertions
+initial begin
+    if (WORD_SIZE * STRB_WIDTH != DATA_WIDTH) begin
+        $error("Error: AXI data width not evenly divisble");
+        $finish;
+    end
+
+    if (2**$clog2(WORD_WIDTH) != WORD_WIDTH) begin
+        $error("Error: AXI word width must be even power of two");
+        $finish;
+    end
+end
+
+localparam [0:0]
+    READ_STATE_IDLE = 1'd0,
+    READ_STATE_BURST = 1'd1;
+
+reg [0:0] read_state_reg = READ_STATE_IDLE, read_state_next;
+
+localparam [1:0]
+    WRITE_STATE_IDLE = 2'd0,
+    WRITE_STATE_BURST = 2'd1,
+    WRITE_STATE_RESP = 2'd2;
+
+reg [1:0] write_state_reg = WRITE_STATE_IDLE, write_state_next;
+
+reg mem_wr_en;
+reg mem_rd_en;
+
+reg [ID_WIDTH-1:0] read_id_reg = {ID_WIDTH{1'b0}}, read_id_next;
+reg [ADDR_WIDTH-1:0] read_addr_reg = {ADDR_WIDTH{1'b0}}, read_addr_next;
+reg [7:0] read_count_reg = 8'd0, read_count_next;
+reg [2:0] read_size_reg = 3'd0, read_size_next;
+reg [1:0] read_burst_reg = 2'd0, read_burst_next;
+reg [ID_WIDTH-1:0] write_id_reg = {ID_WIDTH{1'b0}}, write_id_next;
+reg [ADDR_WIDTH-1:0] write_addr_reg = {ADDR_WIDTH{1'b0}}, write_addr_next;
+reg [7:0] write_count_reg = 8'd0, write_count_next;
+reg [2:0] write_size_reg = 3'd0, write_size_next;
+reg [1:0] write_burst_reg = 2'd0, write_burst_next;
+
+reg s_axi_awready_reg = 1'b0, s_axi_awready_next;
+reg s_axi_wready_reg = 1'b0, s_axi_wready_next;
+reg [ID_WIDTH-1:0] s_axi_bid_reg = {ID_WIDTH{1'b0}}, s_axi_bid_next;
+reg s_axi_bvalid_reg = 1'b0, s_axi_bvalid_next;
+reg s_axi_arready_reg = 1'b0, s_axi_arready_next;
+reg [ID_WIDTH-1:0] s_axi_rid_reg = {ID_WIDTH{1'b0}}, s_axi_rid_next;
+reg [DATA_WIDTH-1:0] s_axi_rdata_reg = {DATA_WIDTH{1'b0}}, s_axi_rdata_next;
+reg s_axi_rlast_reg = 1'b0, s_axi_rlast_next;
+reg s_axi_rvalid_reg = 1'b0, s_axi_rvalid_next;
+reg [ID_WIDTH-1:0] s_axi_rid_pipe_reg = {ID_WIDTH{1'b0}};
+reg [DATA_WIDTH-1:0] s_axi_rdata_pipe_reg = {DATA_WIDTH{1'b0}};
+reg s_axi_rlast_pipe_reg = 1'b0;
+reg s_axi_rvalid_pipe_reg = 1'b0;
+
+// (* RAM_STYLE="BLOCK" *)
+reg [DATA_WIDTH-1:0] mem[(2**VALID_ADDR_WIDTH)-1:0];
+
+wire [VALID_ADDR_WIDTH-1:0] s_axi_awaddr_valid = s_axi_awaddr >> (ADDR_WIDTH - VALID_ADDR_WIDTH);
+wire [VALID_ADDR_WIDTH-1:0] s_axi_araddr_valid = s_axi_araddr >> (ADDR_WIDTH - VALID_ADDR_WIDTH);
+wire [VALID_ADDR_WIDTH-1:0] read_addr_valid = read_addr_reg >> (ADDR_WIDTH - VALID_ADDR_WIDTH);
+wire [VALID_ADDR_WIDTH-1:0] write_addr_valid = write_addr_reg >> (ADDR_WIDTH - VALID_ADDR_WIDTH);
+
+assign s_axi_awready = s_axi_awready_reg;
+assign s_axi_wready = s_axi_wready_reg;
+assign s_axi_bid = s_axi_bid_reg;
+assign s_axi_bresp = 2'b00;
+assign s_axi_bvalid = s_axi_bvalid_reg;
+assign s_axi_arready = s_axi_arready_reg;
+assign s_axi_rid = PIPELINE_OUTPUT ? s_axi_rid_pipe_reg : s_axi_rid_reg;
+assign s_axi_rdata = PIPELINE_OUTPUT ? s_axi_rdata_pipe_reg : s_axi_rdata_reg;
+assign s_axi_rresp = 2'b00;
+assign s_axi_rlast = PIPELINE_OUTPUT ? s_axi_rlast_pipe_reg : s_axi_rlast_reg;
+assign s_axi_rvalid = PIPELINE_OUTPUT ? s_axi_rvalid_pipe_reg : s_axi_rvalid_reg;
+
+integer i, j;
+
+initial begin
+    // two nested loops for smaller number of iterations per loop
+    // workaround for synthesizer complaints about large loop counts
+    for (i = 0; i < 2**ADDR_WIDTH; i = i + 2**(ADDR_WIDTH/2)) begin
+        for (j = i; j < i + 2**(ADDR_WIDTH/2); j = j + 1) begin
+            mem[j] = 0;
+        end
+    end
+end
+
+always @* begin
+    write_state_next = WRITE_STATE_IDLE;
+
+    mem_wr_en = 1'b0;
+
+    write_id_next = write_id_reg;
+    write_addr_next = write_addr_reg;
+    write_count_next = write_count_reg;
+    write_size_next = write_size_reg;
+    write_burst_next = write_burst_reg;
+
+    s_axi_awready_next = 1'b0;
+    s_axi_wready_next = 1'b0;
+    s_axi_bid_next = s_axi_bid_reg;
+    s_axi_bvalid_next = s_axi_bvalid_reg && !s_axi_bready;
+
+    case (write_state_reg)
+        WRITE_STATE_IDLE: begin
+            s_axi_awready_next = 1'b1;
+
+            if (s_axi_awready && s_axi_awvalid) begin
+                write_id_next = s_axi_awid;
+                write_addr_next = s_axi_awaddr;
+                write_count_next = s_axi_awlen;
+                write_size_next = s_axi_awsize < $clog2(STRB_WIDTH) ? s_axi_awsize : $clog2(STRB_WIDTH);
+                write_burst_next = s_axi_awburst;
+
+                s_axi_awready_next = 1'b0;
+                s_axi_wready_next = 1'b1;
+                write_state_next = WRITE_STATE_BURST;
+            end else begin
+                write_state_next = WRITE_STATE_IDLE;
+            end
+        end
+        WRITE_STATE_BURST: begin
+            s_axi_wready_next = 1'b1;
+
+            if (s_axi_wready && s_axi_wvalid) begin
+                mem_wr_en = 1'b1;
+                if (write_burst_reg != 2'b00) begin
+                    write_addr_next = write_addr_reg + (1 << write_size_reg);
+                end
+                write_count_next = write_count_reg - 1;
+                if (write_count_reg > 0) begin
+                    write_state_next = WRITE_STATE_BURST;
+                end else begin
+                    s_axi_wready_next = 1'b0;
+                    if (s_axi_bready || !s_axi_bvalid) begin
+                        s_axi_bid_next = write_id_reg;
+                        s_axi_bvalid_next = 1'b1;
+                        s_axi_awready_next = 1'b1;
+                        write_state_next = WRITE_STATE_IDLE;
+                    end else begin
+                        write_state_next = WRITE_STATE_RESP;
+                    end
+                end
+            end else begin
+                write_state_next = WRITE_STATE_BURST;
+            end
+        end
+        WRITE_STATE_RESP: begin
+            if (s_axi_bready || !s_axi_bvalid) begin
+                s_axi_bid_next = write_id_reg;
+                s_axi_bvalid_next = 1'b1;
+                s_axi_awready_next = 1'b1;
+                write_state_next = WRITE_STATE_IDLE;
+            end else begin
+                write_state_next = WRITE_STATE_RESP;
+            end
+        end
+    endcase
+end
+
+always @(posedge clk) begin
+    if (rst) begin
+        write_state_reg <= WRITE_STATE_IDLE;
+        s_axi_awready_reg <= 1'b0;
+        s_axi_wready_reg <= 1'b0;
+        s_axi_bvalid_reg <= 1'b0;
+    end else begin
+        write_state_reg <= write_state_next;
+        s_axi_awready_reg <= s_axi_awready_next;
+        s_axi_wready_reg <= s_axi_wready_next;
+        s_axi_bvalid_reg <= s_axi_bvalid_next;
+    end
+
+    write_id_reg <= write_id_next;
+    write_addr_reg <= write_addr_next;
+    write_count_reg <= write_count_next;
+    write_size_reg <= write_size_next;
+    write_burst_reg <= write_burst_next;
+
+    s_axi_bid_reg <= s_axi_bid_next;
+
+    for (i = 0; i < WORD_WIDTH; i = i + 1) begin
+        if (mem_wr_en & s_axi_wstrb[i]) begin
+            mem[write_addr_valid][WORD_SIZE*i +: WORD_SIZE] <= s_axi_wdata[WORD_SIZE*i +: WORD_SIZE];
+        end
+    end
+end
+
+always @* begin
+    read_state_next = READ_STATE_IDLE;
+
+    mem_rd_en = 1'b0;
+
+    s_axi_rid_next = s_axi_rid_reg;
+    s_axi_rlast_next = s_axi_rlast_reg;
+    s_axi_rvalid_next = s_axi_rvalid_reg && !(s_axi_rready || (PIPELINE_OUTPUT && !s_axi_rvalid_pipe_reg));
+
+    read_id_next = read_id_reg;
+    read_addr_next = read_addr_reg;
+    read_count_next = read_count_reg;
+    read_size_next = read_size_reg;
+    read_burst_next = read_burst_reg;
+
+    s_axi_arready_next = 1'b0;
+
+    case (read_state_reg)
+        READ_STATE_IDLE: begin
+            s_axi_arready_next = 1'b1;
+
+            if (s_axi_arready && s_axi_arvalid) begin
+                read_id_next = s_axi_arid;
+                read_addr_next = s_axi_araddr;
+                read_count_next = s_axi_arlen;
+                read_size_next = s_axi_arsize < $clog2(STRB_WIDTH) ? s_axi_arsize : $clog2(STRB_WIDTH);
+                read_burst_next = s_axi_arburst;
+
+                s_axi_arready_next = 1'b0;
+                read_state_next = READ_STATE_BURST;
+            end else begin
+                read_state_next = READ_STATE_IDLE;
+            end
+        end
+        READ_STATE_BURST: begin
+            if (s_axi_rready || (PIPELINE_OUTPUT && !s_axi_rvalid_pipe_reg) || !s_axi_rvalid_reg) begin
+                mem_rd_en = 1'b1;
+                s_axi_rvalid_next = 1'b1;
+                s_axi_rid_next = read_id_reg;
+                s_axi_rlast_next = read_count_reg == 0;
+                if (read_burst_reg != 2'b00) begin
+                    read_addr_next = read_addr_reg + (1 << read_size_reg);
+                end
+                read_count_next = read_count_reg - 1;
+                if (read_count_reg > 0) begin
+                    read_state_next = READ_STATE_BURST;
+                end else begin
+                    s_axi_arready_next = 1'b1;
+                    read_state_next = READ_STATE_IDLE;
+                end
+            end else begin
+                read_state_next = READ_STATE_BURST;
+            end
+        end
+    endcase
+end
+
+always @(posedge clk) begin
+    if (rst) begin
+        read_state_reg <= READ_STATE_IDLE;
+        s_axi_arready_reg <= 1'b0;
+        s_axi_rvalid_reg <= 1'b0;
+        s_axi_rvalid_pipe_reg <= 1'b0;
+    end else begin
+        read_state_reg <= read_state_next;
+        s_axi_arready_reg <= s_axi_arready_next;
+        s_axi_rvalid_reg <= s_axi_rvalid_next;
+
+        if (!s_axi_rvalid_pipe_reg || s_axi_rready) begin
+            s_axi_rvalid_pipe_reg <= s_axi_rvalid_reg;
+        end
+    end
+
+    read_id_reg <= read_id_next;
+    read_addr_reg <= read_addr_next;
+    read_count_reg <= read_count_next;
+    read_size_reg <= read_size_next;
+    read_burst_reg <= read_burst_next;
+
+    s_axi_rid_reg <= s_axi_rid_next;
+    s_axi_rlast_reg <= s_axi_rlast_next;
+
+    if (mem_rd_en) begin
+        s_axi_rdata_reg <= mem[read_addr_valid];
+    end
+
+    if (!s_axi_rvalid_pipe_reg || s_axi_rready) begin
+        s_axi_rid_pipe_reg <= s_axi_rid_reg;
+        s_axi_rdata_pipe_reg <= s_axi_rdata_reg;
+        s_axi_rlast_pipe_reg <= s_axi_rlast_reg;
+    end
+end
+
+endmodule
+
+`resetall

snapshots/alexforencich_verilog-pcie_pr20/example/AU50/fpga_axi/rtl/axis_register.v

@@ -0,0 +1,268 @@
+/*
+
+Copyright (c) 2014-2018 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog 2001
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * AXI4-Stream register
+ */
+module axis_register #
+(
+    parameter DATA_WIDTH = 8,
+    parameter KEEP_ENABLE = (DATA_WIDTH>8),
+    parameter KEEP_WIDTH = (DATA_WIDTH/8),
+    parameter LAST_ENABLE = 1,
+    parameter ID_ENABLE = 0,
+    parameter ID_WIDTH = 8,
+    parameter DEST_ENABLE = 0,
+    parameter DEST_WIDTH = 8,
+    parameter USER_ENABLE = 1,
+    parameter USER_WIDTH = 1,
+    parameter REG_TYPE = 2
+)
+(
+    input  wire                   clk,
+    input  wire                   rst,
+
+    /*
+     * AXI Stream input
+     */
+    input  wire [DATA_WIDTH-1:0]  s_axis_tdata,
+    input  wire [KEEP_WIDTH-1:0]  s_axis_tkeep,
+    input  wire                   s_axis_tvalid,
+    output wire                   s_axis_tready,
+    input  wire                   s_axis_tlast,
+    input  wire [ID_WIDTH-1:0]    s_axis_tid,
+    input  wire [DEST_WIDTH-1:0]  s_axis_tdest,
+    input  wire [USER_WIDTH-1:0]  s_axis_tuser,
+
+    /*
+     * AXI Stream output
+     */
+    output wire [DATA_WIDTH-1:0]  m_axis_tdata,
+    output wire [KEEP_WIDTH-1:0]  m_axis_tkeep,
+    output wire                   m_axis_tvalid,
+    input  wire                   m_axis_tready,
+    output wire                   m_axis_tlast,
+    output wire [ID_WIDTH-1:0]    m_axis_tid,
+    output wire [DEST_WIDTH-1:0]  m_axis_tdest,
+    output wire [USER_WIDTH-1:0]  m_axis_tuser
+);
+
+generate
+
+if (REG_TYPE > 1) begin
+    // skid buffer, no bubble cycles
+
+    // datapath registers
+    reg                  s_axis_tready_reg = 1'b0;
+
+    reg [DATA_WIDTH-1:0] m_axis_tdata_reg  = {DATA_WIDTH{1'b0}};
+    reg [KEEP_WIDTH-1:0] m_axis_tkeep_reg  = {KEEP_WIDTH{1'b0}};
+    reg                  m_axis_tvalid_reg = 1'b0, m_axis_tvalid_next;
+    reg                  m_axis_tlast_reg  = 1'b0;
+    reg [ID_WIDTH-1:0]   m_axis_tid_reg    = {ID_WIDTH{1'b0}};
+    reg [DEST_WIDTH-1:0] m_axis_tdest_reg  = {DEST_WIDTH{1'b0}};
+    reg [USER_WIDTH-1:0] m_axis_tuser_reg  = {USER_WIDTH{1'b0}};
+
+    reg [DATA_WIDTH-1:0] temp_m_axis_tdata_reg  = {DATA_WIDTH{1'b0}};
+    reg [KEEP_WIDTH-1:0] temp_m_axis_tkeep_reg  = {KEEP_WIDTH{1'b0}};
+    reg                  temp_m_axis_tvalid_reg = 1'b0, temp_m_axis_tvalid_next;
+    reg                  temp_m_axis_tlast_reg  = 1'b0;
+    reg [ID_WIDTH-1:0]   temp_m_axis_tid_reg    = {ID_WIDTH{1'b0}};
+    reg [DEST_WIDTH-1:0] temp_m_axis_tdest_reg  = {DEST_WIDTH{1'b0}};
+    reg [USER_WIDTH-1:0] temp_m_axis_tuser_reg  = {USER_WIDTH{1'b0}};
+
+    // datapath control
+    reg store_axis_input_to_output;
+    reg store_axis_input_to_temp;
+    reg store_axis_temp_to_output;
+
+    assign s_axis_tready = s_axis_tready_reg;
+
+    assign m_axis_tdata  = m_axis_tdata_reg;
+    assign m_axis_tkeep  = KEEP_ENABLE ? m_axis_tkeep_reg : {KEEP_WIDTH{1'b1}};
+    assign m_axis_tvalid = m_axis_tvalid_reg;
+    assign m_axis_tlast  = LAST_ENABLE ? m_axis_tlast_reg : 1'b1;
+    assign m_axis_tid    = ID_ENABLE   ? m_axis_tid_reg   : {ID_WIDTH{1'b0}};
+    assign m_axis_tdest  = DEST_ENABLE ? m_axis_tdest_reg : {DEST_WIDTH{1'b0}};
+    assign m_axis_tuser  = USER_ENABLE ? m_axis_tuser_reg : {USER_WIDTH{1'b0}};
+
+    // enable ready input next cycle if output is ready or the temp reg will not be filled on the next cycle (output reg empty or no input)
+    wire s_axis_tready_early = m_axis_tready || (!temp_m_axis_tvalid_reg && (!m_axis_tvalid_reg || !s_axis_tvalid));
+
+    always @* begin
+        // transfer sink ready state to source
+        m_axis_tvalid_next = m_axis_tvalid_reg;
+        temp_m_axis_tvalid_next = temp_m_axis_tvalid_reg;
+
+        store_axis_input_to_output = 1'b0;
+        store_axis_input_to_temp = 1'b0;
+        store_axis_temp_to_output = 1'b0;
+
+        if (s_axis_tready_reg) begin
+            // input is ready
+            if (m_axis_tready || !m_axis_tvalid_reg) begin
+                // output is ready or currently not valid, transfer data to output
+                m_axis_tvalid_next = s_axis_tvalid;
+                store_axis_input_to_output = 1'b1;
+            end else begin
+                // output is not ready, store input in temp
+                temp_m_axis_tvalid_next = s_axis_tvalid;
+                store_axis_input_to_temp = 1'b1;
+            end
+        end else if (m_axis_tready) begin
+            // input is not ready, but output is ready
+            m_axis_tvalid_next = temp_m_axis_tvalid_reg;
+            temp_m_axis_tvalid_next = 1'b0;
+            store_axis_temp_to_output = 1'b1;
+        end
+    end
+
+    always @(posedge clk) begin
+        if (rst) begin
+            s_axis_tready_reg <= 1'b0;
+            m_axis_tvalid_reg <= 1'b0;
+            temp_m_axis_tvalid_reg <= 1'b0;
+        end else begin
+            s_axis_tready_reg <= s_axis_tready_early;
+            m_axis_tvalid_reg <= m_axis_tvalid_next;
+            temp_m_axis_tvalid_reg <= temp_m_axis_tvalid_next;
+        end
+
+        // datapath
+        if (store_axis_input_to_output) begin
+            m_axis_tdata_reg <= s_axis_tdata;
+            m_axis_tkeep_reg <= s_axis_tkeep;
+            m_axis_tlast_reg <= s_axis_tlast;
+            m_axis_tid_reg   <= s_axis_tid;
+            m_axis_tdest_reg <= s_axis_tdest;
+            m_axis_tuser_reg <= s_axis_tuser;
+        end else if (store_axis_temp_to_output) begin
+            m_axis_tdata_reg <= temp_m_axis_tdata_reg;
+            m_axis_tkeep_reg <= temp_m_axis_tkeep_reg;
+            m_axis_tlast_reg <= temp_m_axis_tlast_reg;
+            m_axis_tid_reg   <= temp_m_axis_tid_reg;
+            m_axis_tdest_reg <= temp_m_axis_tdest_reg;
+            m_axis_tuser_reg <= temp_m_axis_tuser_reg;
+        end
+
+        if (store_axis_input_to_temp) begin
+            temp_m_axis_tdata_reg <= s_axis_tdata;
+            temp_m_axis_tkeep_reg <= s_axis_tkeep;
+            temp_m_axis_tlast_reg <= s_axis_tlast;
+            temp_m_axis_tid_reg   <= s_axis_tid;
+            temp_m_axis_tdest_reg <= s_axis_tdest;
+            temp_m_axis_tuser_reg <= s_axis_tuser;
+        end
+    end
+
+end else if (REG_TYPE == 1) begin
+    // simple register, inserts bubble cycles
+
+    // datapath registers
+    reg                  s_axis_tready_reg = 1'b0;
+
+    reg [DATA_WIDTH-1:0] m_axis_tdata_reg  = {DATA_WIDTH{1'b0}};
+    reg [KEEP_WIDTH-1:0] m_axis_tkeep_reg  = {KEEP_WIDTH{1'b0}};
+    reg                  m_axis_tvalid_reg = 1'b0, m_axis_tvalid_next;
+    reg                  m_axis_tlast_reg  = 1'b0;
+    reg [ID_WIDTH-1:0]   m_axis_tid_reg    = {ID_WIDTH{1'b0}};
+    reg [DEST_WIDTH-1:0] m_axis_tdest_reg  = {DEST_WIDTH{1'b0}};
+    reg [USER_WIDTH-1:0] m_axis_tuser_reg  = {USER_WIDTH{1'b0}};
+
+    // datapath control
+    reg store_axis_input_to_output;
+
+    assign s_axis_tready = s_axis_tready_reg;
+
+    assign m_axis_tdata  = m_axis_tdata_reg;
+    assign m_axis_tkeep  = KEEP_ENABLE ? m_axis_tkeep_reg : {KEEP_WIDTH{1'b1}};
+    assign m_axis_tvalid = m_axis_tvalid_reg;
+    assign m_axis_tlast  = LAST_ENABLE ? m_axis_tlast_reg : 1'b1;
+    assign m_axis_tid    = ID_ENABLE   ? m_axis_tid_reg   : {ID_WIDTH{1'b0}};
+    assign m_axis_tdest  = DEST_ENABLE ? m_axis_tdest_reg : {DEST_WIDTH{1'b0}};
+    assign m_axis_tuser  = USER_ENABLE ? m_axis_tuser_reg : {USER_WIDTH{1'b0}};
+
+    // enable ready input next cycle if output buffer will be empty
+    wire s_axis_tready_early = !m_axis_tvalid_next;
+
+    always @* begin
+        // transfer sink ready state to source
+        m_axis_tvalid_next = m_axis_tvalid_reg;
+
+        store_axis_input_to_output = 1'b0;
+
+        if (s_axis_tready_reg) begin
+            m_axis_tvalid_next = s_axis_tvalid;
+            store_axis_input_to_output = 1'b1;
+        end else if (m_axis_tready) begin
+            m_axis_tvalid_next = 1'b0;
+        end
+    end
+
+    always @(posedge clk) begin
+        if (rst) begin
+            s_axis_tready_reg <= 1'b0;
+            m_axis_tvalid_reg <= 1'b0;
+        end else begin
+            s_axis_tready_reg <= s_axis_tready_early;
+            m_axis_tvalid_reg <= m_axis_tvalid_next;
+        end
+
+        // datapath
+        if (store_axis_input_to_output) begin
+            m_axis_tdata_reg <= s_axis_tdata;
+            m_axis_tkeep_reg <= s_axis_tkeep;
+            m_axis_tlast_reg <= s_axis_tlast;
+            m_axis_tid_reg   <= s_axis_tid;
+            m_axis_tdest_reg <= s_axis_tdest;
+            m_axis_tuser_reg <= s_axis_tuser;
+        end
+    end
+
+end else begin
+    // bypass
+
+    assign m_axis_tdata  = s_axis_tdata;
+    assign m_axis_tkeep  = KEEP_ENABLE ? s_axis_tkeep : {KEEP_WIDTH{1'b1}};
+    assign m_axis_tvalid = s_axis_tvalid;
+    assign m_axis_tlast  = LAST_ENABLE ? s_axis_tlast : 1'b1;
+    assign m_axis_tid    = ID_ENABLE   ? s_axis_tid   : {ID_WIDTH{1'b0}};
+    assign m_axis_tdest  = DEST_ENABLE ? s_axis_tdest : {DEST_WIDTH{1'b0}};
+    assign m_axis_tuser  = USER_ENABLE ? s_axis_tuser : {USER_WIDTH{1'b0}};
+
+    assign s_axis_tready = m_axis_tready;
+
+end
+
+endgenerate
+
+endmodule
+
+`resetall

snapshots/alexforencich_verilog-pcie_pr20/example/AU50/fpga_axi/rtl/fpga.v

@@ -0,0 +1,416 @@
+/*
+
+Copyright (c) 2020 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog 2001
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * FPGA top-level module
+ */
+module fpga (
+    /*
+     * GPIO
+     */
+    output wire        qsfp_led_act,
+    output wire        qsfp_led_stat_g,
+    output wire        qsfp_led_stat_y,
+    output wire        hbm_cattrip,
+
+    /*
+     * PCI express
+     */
+    input  wire [15:0] pcie_rx_p,
+    input  wire [15:0] pcie_rx_n,
+    output wire [15:0] pcie_tx_p,
+    output wire [15:0] pcie_tx_n,
+    input  wire        pcie_refclk_1_p,
+    input  wire        pcie_refclk_1_n,
+    input  wire        pcie_reset_n
+);
+
+parameter AXIS_PCIE_DATA_WIDTH = 512;
+parameter AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32);
+parameter AXIS_PCIE_RC_USER_WIDTH = 161;
+parameter AXIS_PCIE_RQ_USER_WIDTH = 137;
+parameter AXIS_PCIE_CQ_USER_WIDTH = 183;
+parameter AXIS_PCIE_CC_USER_WIDTH = 81;
+
+// Clock and reset
+wire pcie_user_clk;
+wire pcie_user_reset;
+
+// GPIO
+assign hbm_cattrip = 1'b0;
+
+// PCIe
+wire pcie_sys_clk;
+wire pcie_sys_clk_gt;
+
+IBUFDS_GTE4 #(
+    .REFCLK_HROW_CK_SEL(2'b00)
+)
+ibufds_gte4_pcie_mgt_refclk_inst (
+    .I             (pcie_refclk_1_p),
+    .IB            (pcie_refclk_1_n),
+    .CEB           (1'b0),
+    .O             (pcie_sys_clk_gt),
+    .ODIV2         (pcie_sys_clk)
+);
+
+wire [AXIS_PCIE_DATA_WIDTH-1:0]    axis_rq_tdata;
+wire [AXIS_PCIE_KEEP_WIDTH-1:0]    axis_rq_tkeep;
+wire                               axis_rq_tlast;
+wire                               axis_rq_tready;
+wire [AXIS_PCIE_RQ_USER_WIDTH-1:0] axis_rq_tuser;
+wire                               axis_rq_tvalid;
+
+wire [AXIS_PCIE_DATA_WIDTH-1:0]    axis_rc_tdata;
+wire [AXIS_PCIE_KEEP_WIDTH-1:0]    axis_rc_tkeep;
+wire                               axis_rc_tlast;
+wire                               axis_rc_tready;
+wire [AXIS_PCIE_RC_USER_WIDTH-1:0] axis_rc_tuser;
+wire                               axis_rc_tvalid;
+
+wire [AXIS_PCIE_DATA_WIDTH-1:0]    axis_cq_tdata;
+wire [AXIS_PCIE_KEEP_WIDTH-1:0]    axis_cq_tkeep;
+wire                               axis_cq_tlast;
+wire                               axis_cq_tready;
+wire [AXIS_PCIE_CQ_USER_WIDTH-1:0] axis_cq_tuser;
+wire                               axis_cq_tvalid;
+
+wire [AXIS_PCIE_DATA_WIDTH-1:0]    axis_cc_tdata;
+wire [AXIS_PCIE_KEEP_WIDTH-1:0]    axis_cc_tkeep;
+wire                               axis_cc_tlast;
+wire                               axis_cc_tready;
+wire [AXIS_PCIE_CC_USER_WIDTH-1:0] axis_cc_tuser;
+wire                               axis_cc_tvalid;
+
+// ila_0 rq_ila (
+//     .clk(pcie_user_clk),
+//     .probe0(axis_rq_tdata),
+//     .probe1(axis_rq_tkeep),
+//     .probe2(axis_rq_tlast),
+//     .probe3(axis_rq_tready),
+//     .probe4(axis_rq_tuser),
+//     .probe5(axis_rq_tvalid)
+// );
+
+// ila_0 rc_ila (
+//     .clk(pcie_user_clk),
+//     .probe0(axis_rc_tdata),
+//     .probe1(axis_rc_tkeep),
+//     .probe2(axis_rc_tlast),
+//     .probe3(axis_rc_tready),
+//     .probe4(axis_rc_tuser),
+//     .probe5(axis_rc_tvalid)
+// );
+
+wire [2:0] cfg_max_payload;
+wire [2:0] cfg_max_read_req;
+
+wire [9:0]  cfg_mgmt_addr;
+wire [7:0]  cfg_mgmt_function_number;
+wire        cfg_mgmt_write;
+wire [31:0] cfg_mgmt_write_data;
+wire [3:0]  cfg_mgmt_byte_enable;
+wire        cfg_mgmt_read;
+wire [31:0] cfg_mgmt_read_data;
+wire        cfg_mgmt_read_write_done;
+
+wire [3:0]  cfg_interrupt_msi_enable;
+wire [11:0] cfg_interrupt_msi_mmenable;
+wire        cfg_interrupt_msi_mask_update;
+wire [31:0] cfg_interrupt_msi_data;
+wire [3:0]  cfg_interrupt_msi_select;
+wire [31:0] cfg_interrupt_msi_int;
+wire [31:0] cfg_interrupt_msi_pending_status;
+wire        cfg_interrupt_msi_pending_status_data_enable;
+wire [3:0]  cfg_interrupt_msi_pending_status_function_num;
+wire        cfg_interrupt_msi_sent;
+wire        cfg_interrupt_msi_fail;
+wire [2:0]  cfg_interrupt_msi_attr;
+wire        cfg_interrupt_msi_tph_present;
+wire [1:0]  cfg_interrupt_msi_tph_type;
+wire [8:0]  cfg_interrupt_msi_tph_st_tag;
+wire [3:0]  cfg_interrupt_msi_function_number;
+
+wire status_error_cor;
+wire status_error_uncor;
+
+pcie4c_uscale_plus_0
+pcie4c_uscale_plus_inst (
+    .pci_exp_txn(pcie_tx_n),
+    .pci_exp_txp(pcie_tx_p),
+    .pci_exp_rxn(pcie_rx_n),
+    .pci_exp_rxp(pcie_rx_p),
+    .user_clk(pcie_user_clk),
+    .user_reset(pcie_user_reset),
+    .user_lnk_up(),
+
+    .s_axis_rq_tdata(axis_rq_tdata),
+    .s_axis_rq_tkeep(axis_rq_tkeep),
+    .s_axis_rq_tlast(axis_rq_tlast),
+    .s_axis_rq_tready(axis_rq_tready),
+    .s_axis_rq_tuser(axis_rq_tuser),
+    .s_axis_rq_tvalid(axis_rq_tvalid),
+
+    .m_axis_rc_tdata(axis_rc_tdata),
+    .m_axis_rc_tkeep(axis_rc_tkeep),
+    .m_axis_rc_tlast(axis_rc_tlast),
+    .m_axis_rc_tready(axis_rc_tready),
+    .m_axis_rc_tuser(axis_rc_tuser),
+    .m_axis_rc_tvalid(axis_rc_tvalid),
+
+    .m_axis_cq_tdata(axis_cq_tdata),
+    .m_axis_cq_tkeep(axis_cq_tkeep),
+    .m_axis_cq_tlast(axis_cq_tlast),
+    .m_axis_cq_tready(axis_cq_tready),
+    .m_axis_cq_tuser(axis_cq_tuser),
+    .m_axis_cq_tvalid(axis_cq_tvalid),
+
+    .s_axis_cc_tdata(axis_cc_tdata),
+    .s_axis_cc_tkeep(axis_cc_tkeep),
+    .s_axis_cc_tlast(axis_cc_tlast),
+    .s_axis_cc_tready(axis_cc_tready),
+    .s_axis_cc_tuser(axis_cc_tuser),
+    .s_axis_cc_tvalid(axis_cc_tvalid),
+
+    .pcie_rq_seq_num0(),
+    .pcie_rq_seq_num_vld0(),
+    .pcie_rq_seq_num1(),
+    .pcie_rq_seq_num_vld1(),
+    .pcie_rq_tag0(),
+    .pcie_rq_tag1(),
+    .pcie_rq_tag_av(),
+    .pcie_rq_tag_vld0(),
+    .pcie_rq_tag_vld1(),
+
+    .pcie_tfc_nph_av(),
+    .pcie_tfc_npd_av(),
+
+    .pcie_cq_np_req(1'b1),
+    .pcie_cq_np_req_count(),
+
+    .cfg_phy_link_down(),
+    .cfg_phy_link_status(),
+    .cfg_negotiated_width(),
+    .cfg_current_speed(),
+    .cfg_max_payload(cfg_max_payload),
+    .cfg_max_read_req(cfg_max_read_req),
+    .cfg_function_status(),
+    .cfg_function_power_state(),
+    .cfg_vf_status(),
+    .cfg_vf_power_state(),
+    .cfg_link_power_state(),
+
+    .cfg_mgmt_addr(cfg_mgmt_addr),
+    .cfg_mgmt_function_number(cfg_mgmt_function_number),
+    .cfg_mgmt_write(cfg_mgmt_write),
+    .cfg_mgmt_write_data(cfg_mgmt_write_data),
+    .cfg_mgmt_byte_enable(cfg_mgmt_byte_enable),
+    .cfg_mgmt_read(cfg_mgmt_read),
+    .cfg_mgmt_read_data(cfg_mgmt_read_data),
+    .cfg_mgmt_read_write_done(cfg_mgmt_read_write_done),
+    .cfg_mgmt_debug_access(1'b0),
+
+    .cfg_err_cor_out(),
+    .cfg_err_nonfatal_out(),
+    .cfg_err_fatal_out(),
+    .cfg_local_error_valid(),
+    .cfg_local_error_out(),
+    .cfg_ltssm_state(),
+    .cfg_rx_pm_state(),
+    .cfg_tx_pm_state(),
+    .cfg_rcb_status(),
+    .cfg_obff_enable(),
+    .cfg_pl_status_change(),
+    .cfg_tph_requester_enable(),
+    .cfg_tph_st_mode(),
+    .cfg_vf_tph_requester_enable(),
+    .cfg_vf_tph_st_mode(),
+
+    .cfg_msg_received(),
+    .cfg_msg_received_data(),
+    .cfg_msg_received_type(),
+    .cfg_msg_transmit(1'b0),
+    .cfg_msg_transmit_type(3'd0),
+    .cfg_msg_transmit_data(32'd0),
+    .cfg_msg_transmit_done(),
+
+    .cfg_fc_ph(),
+    .cfg_fc_pd(),
+    .cfg_fc_nph(),
+    .cfg_fc_npd(),
+    .cfg_fc_cplh(),
+    .cfg_fc_cpld(),
+    .cfg_fc_sel(3'd0),
+
+    .cfg_dsn(64'd0),
+
+    .cfg_bus_number(),
+
+    .cfg_power_state_change_ack(1'b1),
+    .cfg_power_state_change_interrupt(),
+
+    .cfg_err_cor_in(status_error_cor),
+    .cfg_err_uncor_in(status_error_uncor),
+    .cfg_flr_in_process(),
+    .cfg_flr_done(4'd0),
+    .cfg_vf_flr_in_process(),
+    .cfg_vf_flr_func_num(8'd0),
+    .cfg_vf_flr_done(8'd0),
+
+    .cfg_link_training_enable(1'b1),
+
+    .cfg_interrupt_int(4'd0),
+    .cfg_interrupt_pending(4'd0),
+    .cfg_interrupt_sent(),
+    .cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
+    .cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
+    .cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
+    .cfg_interrupt_msi_data(cfg_interrupt_msi_data),
+    .cfg_interrupt_msi_select(cfg_interrupt_msi_select),
+    .cfg_interrupt_msi_int(cfg_interrupt_msi_int),
+    .cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
+    .cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
+    .cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
+    .cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
+    .cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
+    .cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
+    .cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
+    .cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
+    .cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
+    .cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
+
+    .cfg_pm_aspm_l1_entry_reject(1'b0),
+    .cfg_pm_aspm_tx_l0s_entry_disable(1'b0),
+
+    .cfg_hot_reset_out(),
+
+    .cfg_config_space_enable(1'b1),
+    .cfg_req_pm_transition_l23_ready(1'b0),
+    .cfg_hot_reset_in(1'b0),
+
+    .cfg_ds_port_number(8'd0),
+    .cfg_ds_bus_number(8'd0),
+    .cfg_ds_device_number(5'd0),
+
+    .sys_clk(pcie_sys_clk),
+    .sys_clk_gt(pcie_sys_clk_gt),
+    .sys_reset(pcie_reset_n),
+
+    .phy_rdy_out()
+);
+
+fpga_core #(
+    .AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
+    .AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
+    .AXIS_PCIE_RC_USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH),
+    .AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH),
+    .AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH),
+    .AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH)
+)
+core_inst (
+    /*
+     * Clock: 250 MHz
+     * Synchronous reset
+     */
+    .clk(pcie_user_clk),
+    .rst(pcie_user_reset),
+    /*
+     * GPIO
+     */
+    .qsfp_led_act(qsfp_led_act),
+    .qsfp_led_stat_g(qsfp_led_stat_g),
+    .qsfp_led_stat_y(qsfp_led_stat_y),
+    /*
+     * PCIe
+     */
+    .m_axis_rq_tdata(axis_rq_tdata),
+    .m_axis_rq_tkeep(axis_rq_tkeep),
+    .m_axis_rq_tlast(axis_rq_tlast),
+    .m_axis_rq_tready(axis_rq_tready),
+    .m_axis_rq_tuser(axis_rq_tuser),
+    .m_axis_rq_tvalid(axis_rq_tvalid),
+
+    .s_axis_rc_tdata(axis_rc_tdata),
+    .s_axis_rc_tkeep(axis_rc_tkeep),
+    .s_axis_rc_tlast(axis_rc_tlast),
+    .s_axis_rc_tready(axis_rc_tready),
+    .s_axis_rc_tuser(axis_rc_tuser),
+    .s_axis_rc_tvalid(axis_rc_tvalid),
+
+    .s_axis_cq_tdata(axis_cq_tdata),
+    .s_axis_cq_tkeep(axis_cq_tkeep),
+    .s_axis_cq_tlast(axis_cq_tlast),
+    .s_axis_cq_tready(axis_cq_tready),
+    .s_axis_cq_tuser(axis_cq_tuser),
+    .s_axis_cq_tvalid(axis_cq_tvalid),
+
+    .m_axis_cc_tdata(axis_cc_tdata),
+    .m_axis_cc_tkeep(axis_cc_tkeep),
+    .m_axis_cc_tlast(axis_cc_tlast),
+    .m_axis_cc_tready(axis_cc_tready),
+    .m_axis_cc_tuser(axis_cc_tuser),
+    .m_axis_cc_tvalid(axis_cc_tvalid),
+
+    .cfg_max_payload(cfg_max_payload),
+    .cfg_max_read_req(cfg_max_read_req),
+    
+    .cfg_mgmt_addr(cfg_mgmt_addr),
+    .cfg_mgmt_function_number(cfg_mgmt_function_number),
+    .cfg_mgmt_write(cfg_mgmt_write),
+    .cfg_mgmt_write_data(cfg_mgmt_write_data),
+    .cfg_mgmt_byte_enable(cfg_mgmt_byte_enable),
+    .cfg_mgmt_read(cfg_mgmt_read),
+    .cfg_mgmt_read_data(cfg_mgmt_read_data),
+    .cfg_mgmt_read_write_done(cfg_mgmt_read_write_done),
+
+    .cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
+    .cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
+    .cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
+    .cfg_interrupt_msi_data(cfg_interrupt_msi_data),
+    .cfg_interrupt_msi_select(cfg_interrupt_msi_select),
+    .cfg_interrupt_msi_int(cfg_interrupt_msi_int),
+    .cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
+    .cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
+    .cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
+    .cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
+    .cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
+    .cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
+    .cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
+    .cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
+    .cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
+    .cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number),
+
+    .status_error_cor(status_error_cor),
+    .status_error_uncor(status_error_uncor)
+);
+
+endmodule
+
+`resetall

snapshots/alexforencich_verilog-pcie_pr20/example/AU50/fpga_axi/rtl/fpga_core.v

@@ -0,0 +1,1126 @@
+/*
+
+Copyright (c) 2020 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog 2001
+
+`resetall
+`timescale 1ns / 1ps
+`default_nettype none
+
+/*
+ * FPGA core logic
+ */
+module fpga_core #
+(
+    parameter AXIS_PCIE_DATA_WIDTH = 512,
+    parameter AXIS_PCIE_KEEP_WIDTH = (AXIS_PCIE_DATA_WIDTH/32),
+    parameter AXIS_PCIE_RC_USER_WIDTH = 161,
+    parameter AXIS_PCIE_RQ_USER_WIDTH = 137,
+    parameter AXIS_PCIE_CQ_USER_WIDTH = 183,
+    parameter AXIS_PCIE_CC_USER_WIDTH = 81
+)
+(
+    /*
+     * Clock: 250 MHz
+     * Synchronous reset
+     */
+    input  wire                               clk,
+    input  wire                               rst,
+
+    /*
+     * GPIO
+     */
+    output wire                               qsfp_led_act,
+    output wire                               qsfp_led_stat_g,
+    output wire                               qsfp_led_stat_y,
+
+    /*
+     * PCIe
+     */
+    output wire [AXIS_PCIE_DATA_WIDTH-1:0]    m_axis_rq_tdata,
+    output wire [AXIS_PCIE_KEEP_WIDTH-1:0]    m_axis_rq_tkeep,
+    output wire                               m_axis_rq_tlast,
+    input  wire                               m_axis_rq_tready,
+    output wire [AXIS_PCIE_RQ_USER_WIDTH-1:0] m_axis_rq_tuser,
+    output wire                               m_axis_rq_tvalid,
+
+    input  wire [AXIS_PCIE_DATA_WIDTH-1:0]    s_axis_rc_tdata,
+    input  wire [AXIS_PCIE_KEEP_WIDTH-1:0]    s_axis_rc_tkeep,
+    input  wire                               s_axis_rc_tlast,
+    output wire                               s_axis_rc_tready,
+    input  wire [AXIS_PCIE_RC_USER_WIDTH-1:0] s_axis_rc_tuser,
+    input  wire                               s_axis_rc_tvalid,
+
+    input  wire [AXIS_PCIE_DATA_WIDTH-1:0]    s_axis_cq_tdata,
+    input  wire [AXIS_PCIE_KEEP_WIDTH-1:0]    s_axis_cq_tkeep,
+    input  wire                               s_axis_cq_tlast,
+    output wire                               s_axis_cq_tready,
+    input  wire [AXIS_PCIE_CQ_USER_WIDTH-1:0] s_axis_cq_tuser,
+    input  wire                               s_axis_cq_tvalid,
+
+    output wire [AXIS_PCIE_DATA_WIDTH-1:0]    m_axis_cc_tdata,
+    output wire [AXIS_PCIE_KEEP_WIDTH-1:0]    m_axis_cc_tkeep,
+    output wire                               m_axis_cc_tlast,
+    input  wire                               m_axis_cc_tready,
+    output wire [AXIS_PCIE_CC_USER_WIDTH-1:0] m_axis_cc_tuser,
+    output wire                               m_axis_cc_tvalid,
+
+    input  wire [2:0]                         cfg_max_payload,
+    input  wire [2:0]                         cfg_max_read_req,
+
+    output wire [9:0]                         cfg_mgmt_addr,
+    output wire [7:0]                         cfg_mgmt_function_number,
+    output wire                               cfg_mgmt_write,
+    output wire [31:0]                        cfg_mgmt_write_data,
+    output wire [3:0]                         cfg_mgmt_byte_enable,
+    output wire                               cfg_mgmt_read,
+    input  wire [31:0]                        cfg_mgmt_read_data,
+    input  wire                               cfg_mgmt_read_write_done,
+
+    input  wire [3:0]                         cfg_interrupt_msi_enable,
+    input  wire [11:0]                        cfg_interrupt_msi_mmenable,
+    input  wire                               cfg_interrupt_msi_mask_update,
+    input  wire [31:0]                        cfg_interrupt_msi_data,
+    output wire [3:0]                         cfg_interrupt_msi_select,
+    output wire [31:0]                        cfg_interrupt_msi_int,
+    output wire [31:0]                        cfg_interrupt_msi_pending_status,
+    output wire                               cfg_interrupt_msi_pending_status_data_enable,
+    output wire [3:0]                         cfg_interrupt_msi_pending_status_function_num,
+    input  wire                               cfg_interrupt_msi_sent,
+    input  wire                               cfg_interrupt_msi_fail,
+    output wire [2:0]                         cfg_interrupt_msi_attr,
+    output wire                               cfg_interrupt_msi_tph_present,
+    output wire [1:0]                         cfg_interrupt_msi_tph_type,
+    output wire [8:0]                         cfg_interrupt_msi_tph_st_tag,
+    output wire [3:0]                         cfg_interrupt_msi_function_number,
+
+    output wire                               status_error_cor,
+    output wire                               status_error_uncor
+);
+
+parameter PCIE_ADDR_WIDTH = 64;
+
+parameter AXIL_DATA_WIDTH = 32;
+parameter AXIL_STRB_WIDTH = (AXIL_DATA_WIDTH/8);
+parameter AXIL_ADDR_WIDTH = 32;
+
+parameter AXI_DATA_WIDTH = AXIS_PCIE_DATA_WIDTH;
+parameter AXI_STRB_WIDTH = (AXI_DATA_WIDTH/8);
+parameter AXI_ADDR_WIDTH = 32;
+parameter AXI_ID_WIDTH = 8;
+
+parameter DMA_TAG_WIDTH = 8;
+
+// Completer mux/demux
+wire [AXIS_PCIE_DATA_WIDTH-1:0]    axis_cq_tdata_bar_0;
+wire [AXIS_PCIE_KEEP_WIDTH-1:0]    axis_cq_tkeep_bar_0;
+wire                               axis_cq_tvalid_bar_0;
+wire                               axis_cq_tready_bar_0;
+wire                               axis_cq_tlast_bar_0;
+wire [AXIS_PCIE_CQ_USER_WIDTH-1:0] axis_cq_tuser_bar_0;
+
+wire [AXIS_PCIE_DATA_WIDTH-1:0]    axis_cc_tdata_bar_0;
+wire [AXIS_PCIE_KEEP_WIDTH-1:0]    axis_cc_tkeep_bar_0;
+wire                               axis_cc_tvalid_bar_0;
+wire                               axis_cc_tready_bar_0;
+wire                               axis_cc_tlast_bar_0;
+wire [AXIS_PCIE_CC_USER_WIDTH-1:0] axis_cc_tuser_bar_0;
+
+wire [AXIS_PCIE_DATA_WIDTH-1:0]    axis_cq_tdata_bar_2;
+wire [AXIS_PCIE_KEEP_WIDTH-1:0]    axis_cq_tkeep_bar_2;
+wire                               axis_cq_tvalid_bar_2;
+wire                               axis_cq_tready_bar_2;
+wire                               axis_cq_tlast_bar_2;
+wire [AXIS_PCIE_CQ_USER_WIDTH-1:0] axis_cq_tuser_bar_2;
+
+wire [AXIS_PCIE_DATA_WIDTH-1:0]    axis_cc_tdata_bar_2;
+wire [AXIS_PCIE_KEEP_WIDTH-1:0]    axis_cc_tkeep_bar_2;
+wire                               axis_cc_tvalid_bar_2;
+wire                               axis_cc_tready_bar_2;
+wire                               axis_cc_tlast_bar_2;
+wire [AXIS_PCIE_CC_USER_WIDTH-1:0] axis_cc_tuser_bar_2;
+
+wire [2:0] bar_id;
+wire [1:0] select;
+
+pcie_us_axis_cq_demux #(
+    .M_COUNT(2),
+    .AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
+    .AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
+    .AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH)
+)
+cq_demux_inst (
+    .clk(clk),
+    .rst(rst),
+
+    /*
+     * AXI input (CQ)
+     */
+    .s_axis_cq_tdata(s_axis_cq_tdata),
+    .s_axis_cq_tkeep(s_axis_cq_tkeep),
+    .s_axis_cq_tvalid(s_axis_cq_tvalid),
+    .s_axis_cq_tready(s_axis_cq_tready),
+    .s_axis_cq_tlast(s_axis_cq_tlast),
+    .s_axis_cq_tuser(s_axis_cq_tuser),
+
+    /*
+     * AXI output (CQ)
+     */
+    .m_axis_cq_tdata({axis_cq_tdata_bar_2, axis_cq_tdata_bar_0}),
+    .m_axis_cq_tkeep({axis_cq_tkeep_bar_2, axis_cq_tkeep_bar_0}),
+    .m_axis_cq_tvalid({axis_cq_tvalid_bar_2, axis_cq_tvalid_bar_0}),
+    .m_axis_cq_tready({axis_cq_tready_bar_2, axis_cq_tready_bar_0}),
+    .m_axis_cq_tlast({axis_cq_tlast_bar_2, axis_cq_tlast_bar_0}),
+    .m_axis_cq_tuser({axis_cq_tuser_bar_2, axis_cq_tuser_bar_0}),
+
+    /*
+     * Fields
+     */
+    .req_type(),
+    .target_function(),
+    .bar_id(bar_id),
+    .msg_code(),
+    .msg_routing(),
+
+    /*
+     * Control
+     */
+    .enable(1),
+    .drop(0),
+    .select(select)
+);
+
+assign select[1] = bar_id == 3'd2;
+assign select[0] = bar_id == 3'd0;
+
+axis_arb_mux #(
+    .S_COUNT(2),
+    .DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
+    .KEEP_ENABLE(1),
+    .KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
+    .ID_ENABLE(0),
+    .DEST_ENABLE(0),
+    .USER_ENABLE(1),
+    .USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH)
+)
+cc_mux_inst (
+    .clk(clk),
+    .rst(rst),
+
+    /*
+     * AXI inputs
+     */
+    .s_axis_tdata({axis_cc_tdata_bar_2, axis_cc_tdata_bar_0}),
+    .s_axis_tkeep({axis_cc_tkeep_bar_2, axis_cc_tkeep_bar_0}),
+    .s_axis_tvalid({axis_cc_tvalid_bar_2, axis_cc_tvalid_bar_0}),
+    .s_axis_tready({axis_cc_tready_bar_2, axis_cc_tready_bar_0}),
+    .s_axis_tlast({axis_cc_tlast_bar_2, axis_cc_tlast_bar_0}),
+    .s_axis_tid(0),
+    .s_axis_tdest(0),
+    .s_axis_tuser({axis_cc_tuser_bar_2, axis_cc_tuser_bar_0}),
+
+    /*
+     * AXI output
+     */
+    .m_axis_tdata(m_axis_cc_tdata),
+    .m_axis_tkeep(m_axis_cc_tkeep),
+    .m_axis_tvalid(m_axis_cc_tvalid),
+    .m_axis_tready(m_axis_cc_tready),
+    .m_axis_tlast(m_axis_cc_tlast),
+    .m_axis_tid(),
+    .m_axis_tdest(),
+    .m_axis_tuser(m_axis_cc_tuser)
+);
+
+wire [AXIL_ADDR_WIDTH-1:0] axil_ctrl_awaddr;
+wire [2:0]                 axil_ctrl_awprot;
+wire                       axil_ctrl_awvalid;
+wire                       axil_ctrl_awready;
+wire [AXIL_DATA_WIDTH-1:0] axil_ctrl_wdata;
+wire [AXIL_STRB_WIDTH-1:0] axil_ctrl_wstrb;
+wire                       axil_ctrl_wvalid;
+wire                       axil_ctrl_wready;
+wire [1:0]                 axil_ctrl_bresp;
+wire                       axil_ctrl_bvalid;
+wire                       axil_ctrl_bready;
+wire [AXIL_ADDR_WIDTH-1:0] axil_ctrl_araddr;
+wire [2:0]                 axil_ctrl_arprot;
+wire                       axil_ctrl_arvalid;
+wire                       axil_ctrl_arready;
+wire [AXIL_DATA_WIDTH-1:0] axil_ctrl_rdata;
+wire [1:0]                 axil_ctrl_rresp;
+wire                       axil_ctrl_rvalid;
+wire                       axil_ctrl_rready;
+
+wire [AXI_ID_WIDTH-1:0]    axi_awid;
+wire [AXI_ADDR_WIDTH-1:0]  axi_awaddr;
+wire [7:0]                 axi_awlen;
+wire [2:0]                 axi_awsize;
+wire [1:0]                 axi_awburst;
+wire                       axi_awlock;
+wire [3:0]                 axi_awcache;
+wire [2:0]                 axi_awprot;
+wire                       axi_awvalid;
+wire                       axi_awready;
+wire [AXI_DATA_WIDTH-1:0]  axi_wdata;
+wire [AXI_STRB_WIDTH-1:0]  axi_wstrb;
+wire                       axi_wlast;
+wire                       axi_wvalid;
+wire                       axi_wready;
+wire [AXI_ID_WIDTH-1:0]    axi_bid;
+wire [1:0]                 axi_bresp;
+wire                       axi_bvalid;
+wire                       axi_bready;
+wire [AXI_ID_WIDTH-1:0]    axi_arid;
+wire [AXI_ADDR_WIDTH-1:0]  axi_araddr;
+wire [7:0]                 axi_arlen;
+wire [2:0]                 axi_arsize;
+wire [1:0]                 axi_arburst;
+wire                       axi_arlock;
+wire [3:0]                 axi_arcache;
+wire [2:0]                 axi_arprot;
+wire                       axi_arvalid;
+wire                       axi_arready;
+wire [AXI_ID_WIDTH-1:0]    axi_rid;
+wire [AXI_DATA_WIDTH-1:0]  axi_rdata;
+wire [1:0]                 axi_rresp;
+wire                       axi_rlast;
+wire                       axi_rvalid;
+wire                       axi_rready;
+
+wire [AXI_ID_WIDTH-1:0]    axi_dma_awid;
+wire [AXI_ADDR_WIDTH-1:0]  axi_dma_awaddr;
+wire [7:0]                 axi_dma_awlen;
+wire [2:0]                 axi_dma_awsize;
+wire [1:0]                 axi_dma_awburst;
+wire                       axi_dma_awlock;
+wire [3:0]                 axi_dma_awcache;
+wire [2:0]                 axi_dma_awprot;
+wire                       axi_dma_awvalid;
+wire                       axi_dma_awready;
+wire [AXI_DATA_WIDTH-1:0]  axi_dma_wdata;
+wire [AXI_STRB_WIDTH-1:0]  axi_dma_wstrb;
+wire                       axi_dma_wlast;
+wire                       axi_dma_wvalid;
+wire                       axi_dma_wready;
+wire [AXI_ID_WIDTH-1:0]    axi_dma_bid;
+wire [1:0]                 axi_dma_bresp;
+wire                       axi_dma_bvalid;
+wire                       axi_dma_bready;
+wire [AXI_ID_WIDTH-1:0]    axi_dma_arid;
+wire [AXI_ADDR_WIDTH-1:0]  axi_dma_araddr;
+wire [7:0]                 axi_dma_arlen;
+wire [2:0]                 axi_dma_arsize;
+wire [1:0]                 axi_dma_arburst;
+wire                       axi_dma_arlock;
+wire [3:0]                 axi_dma_arcache;
+wire [2:0]                 axi_dma_arprot;
+wire                       axi_dma_arvalid;
+wire                       axi_dma_arready;
+wire [AXI_ID_WIDTH-1:0]    axi_dma_rid;
+wire [AXI_DATA_WIDTH-1:0]  axi_dma_rdata;
+wire [1:0]                 axi_dma_rresp;
+wire                       axi_dma_rlast;
+wire                       axi_dma_rvalid;
+wire                       axi_dma_rready;
+
+// PCIe DMA control
+wire [PCIE_ADDR_WIDTH-1:0] pcie_dma_read_desc_pcie_addr;
+wire [AXI_ADDR_WIDTH-1:0]  pcie_dma_read_desc_axi_addr;
+wire [15:0]                pcie_dma_read_desc_len;
+wire [DMA_TAG_WIDTH-1:0]   pcie_dma_read_desc_tag;
+wire                       pcie_dma_read_desc_valid;
+wire                       pcie_dma_read_desc_ready;
+
+wire [DMA_TAG_WIDTH-1:0]   pcie_dma_read_desc_status_tag;
+wire [3:0]                 pcie_dma_read_desc_status_error;
+wire                       pcie_dma_read_desc_status_valid;
+
+wire [PCIE_ADDR_WIDTH-1:0] pcie_dma_write_desc_pcie_addr;
+wire [AXI_ADDR_WIDTH-1:0]  pcie_dma_write_desc_axi_addr;
+wire [15:0]                pcie_dma_write_desc_len;
+wire [DMA_TAG_WIDTH-1:0]   pcie_dma_write_desc_tag;
+wire                       pcie_dma_write_desc_valid;
+wire                       pcie_dma_write_desc_ready;
+
+wire [DMA_TAG_WIDTH-1:0]   pcie_dma_write_desc_status_tag;
+wire [3:0]                 pcie_dma_write_desc_status_error;
+wire                       pcie_dma_write_desc_status_valid;
+
+wire                       pcie_dma_enable;
+
+// Error handling
+wire [2:0] status_error_uncor_int;
+wire [2:0] status_error_cor_int;
+
+wire [31:0] msi_irq;
+
+wire ext_tag_enable;
+
+// control registers
+reg axil_ctrl_awready_reg = 1'b0, axil_ctrl_awready_next;
+reg axil_ctrl_wready_reg = 1'b0, axil_ctrl_wready_next;
+reg [1:0] axil_ctrl_bresp_reg = 2'b00, axil_ctrl_bresp_next;
+reg axil_ctrl_bvalid_reg = 1'b0, axil_ctrl_bvalid_next;
+reg axil_ctrl_arready_reg = 1'b0, axil_ctrl_arready_next;
+reg [AXIL_DATA_WIDTH-1:0] axil_ctrl_rdata_reg = {AXIL_DATA_WIDTH{1'b0}}, axil_ctrl_rdata_next;
+reg [1:0] axil_ctrl_rresp_reg = 2'b00, axil_ctrl_rresp_next;
+reg axil_ctrl_rvalid_reg = 1'b0, axil_ctrl_rvalid_next;
+
+reg [PCIE_ADDR_WIDTH-1:0] pcie_dma_read_desc_pcie_addr_reg = 0, pcie_dma_read_desc_pcie_addr_next;
+reg [AXI_ADDR_WIDTH-1:0] pcie_dma_read_desc_axi_addr_reg = 0, pcie_dma_read_desc_axi_addr_next;
+reg [15:0] pcie_dma_read_desc_len_reg = 0, pcie_dma_read_desc_len_next;
+reg [DMA_TAG_WIDTH-1:0] pcie_dma_read_desc_tag_reg = 0, pcie_dma_read_desc_tag_next;
+reg pcie_dma_read_desc_valid_reg = 0, pcie_dma_read_desc_valid_next;
+
+reg [DMA_TAG_WIDTH-1:0] pcie_dma_read_desc_status_tag_reg = 0, pcie_dma_read_desc_status_tag_next;
+reg [31:0] pcie_dma_read_desc_status_error_reg = 0, pcie_dma_read_desc_status_error_next;
+reg pcie_dma_read_desc_status_valid_reg = 0, pcie_dma_read_desc_status_valid_next;
+
+reg [PCIE_ADDR_WIDTH-1:0] pcie_dma_write_desc_pcie_addr_reg = 0, pcie_dma_write_desc_pcie_addr_next;
+reg [AXI_ADDR_WIDTH-1:0] pcie_dma_write_desc_axi_addr_reg = 0, pcie_dma_write_desc_axi_addr_next;
+reg [15:0] pcie_dma_write_desc_len_reg = 0, pcie_dma_write_desc_len_next;
+reg [DMA_TAG_WIDTH-1:0] pcie_dma_write_desc_tag_reg = 0, pcie_dma_write_desc_tag_next;
+reg pcie_dma_write_desc_valid_reg = 0, pcie_dma_write_desc_valid_next;
+
+reg [DMA_TAG_WIDTH-1:0] pcie_dma_write_desc_status_tag_reg = 0, pcie_dma_write_desc_status_tag_next;
+reg [31:0] pcie_dma_write_desc_status_error_reg = 0, pcie_dma_write_desc_status_error_next;
+reg pcie_dma_write_desc_status_valid_reg = 0, pcie_dma_write_desc_status_valid_next;
+
+reg pcie_dma_enable_reg = 0, pcie_dma_enable_next;
+
+reg [31:0] pcie_rq_count_reg = 0;
+reg [31:0] pcie_rc_count_reg = 0;
+reg [31:0] pcie_cq_count_reg = 0;
+reg [31:0] pcie_cc_count_reg = 0;
+
+assign axil_ctrl_awready = axil_ctrl_awready_reg;
+assign axil_ctrl_wready = axil_ctrl_wready_reg;
+assign axil_ctrl_bresp = axil_ctrl_bresp_reg;
+assign axil_ctrl_bvalid = axil_ctrl_bvalid_reg;
+assign axil_ctrl_arready = axil_ctrl_arready_reg;
+assign axil_ctrl_rdata = axil_ctrl_rdata_reg;
+assign axil_ctrl_rresp = axil_ctrl_rresp_reg;
+assign axil_ctrl_rvalid = axil_ctrl_rvalid_reg;
+
+assign pcie_dma_read_desc_pcie_addr = pcie_dma_read_desc_pcie_addr_reg;
+assign pcie_dma_read_desc_axi_addr = pcie_dma_read_desc_axi_addr_reg;
+assign pcie_dma_read_desc_len = pcie_dma_read_desc_len_reg;
+assign pcie_dma_read_desc_tag = pcie_dma_read_desc_tag_reg;
+assign pcie_dma_read_desc_valid = pcie_dma_read_desc_valid_reg;
+assign pcie_dma_write_desc_pcie_addr = pcie_dma_write_desc_pcie_addr_reg;
+assign pcie_dma_write_desc_axi_addr = pcie_dma_write_desc_axi_addr_reg;
+assign pcie_dma_write_desc_len = pcie_dma_write_desc_len_reg;
+assign pcie_dma_write_desc_tag = pcie_dma_write_desc_tag_reg;
+assign pcie_dma_write_desc_valid = pcie_dma_write_desc_valid_reg;
+assign pcie_dma_enable = pcie_dma_enable_reg;
+
+assign msi_irq[0] = pcie_dma_read_desc_status_valid || pcie_dma_write_desc_status_valid;
+assign msi_irq[31:1] = 0;
+
+always @* begin
+    axil_ctrl_awready_next = 1'b0;
+    axil_ctrl_wready_next = 1'b0;
+    axil_ctrl_bresp_next = 2'b00;
+    axil_ctrl_bvalid_next = axil_ctrl_bvalid_reg && !axil_ctrl_bready;
+    axil_ctrl_arready_next = 1'b0;
+    axil_ctrl_rdata_next = {AXIL_DATA_WIDTH{1'b0}};
+    axil_ctrl_rresp_next = 2'b00;
+    axil_ctrl_rvalid_next = axil_ctrl_rvalid_reg && !axil_ctrl_rready;
+
+    pcie_dma_read_desc_pcie_addr_next = pcie_dma_read_desc_pcie_addr_reg;
+    pcie_dma_read_desc_axi_addr_next = pcie_dma_read_desc_axi_addr_reg;
+    pcie_dma_read_desc_len_next = pcie_dma_read_desc_len_reg;
+    pcie_dma_read_desc_tag_next = pcie_dma_read_desc_tag_reg;
+    pcie_dma_read_desc_valid_next = pcie_dma_read_desc_valid_reg && !pcie_dma_read_desc_ready;
+
+    pcie_dma_read_desc_status_tag_next = pcie_dma_read_desc_status_tag_reg;
+    pcie_dma_read_desc_status_error_next = pcie_dma_read_desc_status_error_reg;
+    pcie_dma_read_desc_status_valid_next = pcie_dma_read_desc_status_valid_reg;
+
+    pcie_dma_write_desc_pcie_addr_next = pcie_dma_write_desc_pcie_addr_reg;
+    pcie_dma_write_desc_axi_addr_next = pcie_dma_write_desc_axi_addr_reg;
+    pcie_dma_write_desc_len_next = pcie_dma_write_desc_len_reg;
+    pcie_dma_write_desc_tag_next = pcie_dma_write_desc_tag_reg;
+    pcie_dma_write_desc_valid_next = pcie_dma_write_desc_valid_reg && !pcie_dma_read_desc_ready;
+
+    pcie_dma_write_desc_status_tag_next = pcie_dma_write_desc_status_tag_reg;
+    pcie_dma_write_desc_status_error_next = pcie_dma_write_desc_status_error_reg;
+    pcie_dma_write_desc_status_valid_next = pcie_dma_write_desc_status_valid_reg;
+
+    pcie_dma_enable_next = pcie_dma_enable_reg;
+
+    if (axil_ctrl_awvalid && axil_ctrl_wvalid && !axil_ctrl_bvalid) begin
+        // write operation
+        axil_ctrl_awready_next = 1'b1;
+        axil_ctrl_wready_next = 1'b1;
+        axil_ctrl_bresp_next = 2'b00;
+        axil_ctrl_bvalid_next = 1'b1;
+
+        case ({axil_ctrl_awaddr[15:2], 2'b00})
+            16'h0000: pcie_dma_enable_next = axil_ctrl_wdata;
+            16'h0100: pcie_dma_read_desc_pcie_addr_next[31:0] = axil_ctrl_wdata;
+            16'h0104: pcie_dma_read_desc_pcie_addr_next[63:32] = axil_ctrl_wdata;
+            16'h0108: pcie_dma_read_desc_axi_addr_next[31:0] = axil_ctrl_wdata;
+            //16'h010C: pcie_dma_read_desc_axi_addr_next[63:32] = axil_ctrl_wdata;
+            16'h0110: pcie_dma_read_desc_len_next = axil_ctrl_wdata;
+            16'h0114: begin
+                pcie_dma_read_desc_tag_next = axil_ctrl_wdata;
+                pcie_dma_read_desc_valid_next = 1'b1;
+            end
+            16'h0200: pcie_dma_write_desc_pcie_addr_next[31:0] = axil_ctrl_wdata;
+            16'h0204: pcie_dma_write_desc_pcie_addr_next[63:32] = axil_ctrl_wdata;
+            16'h0208: pcie_dma_write_desc_axi_addr_next[31:0] = axil_ctrl_wdata;
+            //16'h020C: pcie_dma_write_desc_axi_addr_next[63:32] = axil_ctrl_wdata;
+            16'h0210: pcie_dma_write_desc_len_next = axil_ctrl_wdata;
+            16'h0214: begin
+                pcie_dma_write_desc_tag_next = axil_ctrl_wdata;
+                pcie_dma_write_desc_valid_next = 1'b1;
+            end
+        endcase
+    end
+
+    if (axil_ctrl_arvalid && !axil_ctrl_rvalid) begin
+        // read operation
+        axil_ctrl_arready_next = 1'b1;
+        axil_ctrl_rresp_next = 2'b00;
+        axil_ctrl_rvalid_next = 1'b1;
+
+        case ({axil_ctrl_araddr[15:2], 2'b00})
+            16'h0000: axil_ctrl_rdata_next = pcie_dma_enable_reg;
+            16'h0118: begin
+                axil_ctrl_rdata_next[7:0] = pcie_dma_read_desc_status_tag_reg;
+                axil_ctrl_rdata_next[15:8] = pcie_dma_read_desc_status_error_reg;
+                axil_ctrl_rdata_next[31] = pcie_dma_read_desc_status_valid_reg;
+                pcie_dma_read_desc_status_valid_next = 1'b0;
+            end
+            16'h0218: begin
+                axil_ctrl_rdata_next[7:0] = pcie_dma_write_desc_status_tag_reg;
+                axil_ctrl_rdata_next[15:8] = pcie_dma_write_desc_status_error_reg;
+                axil_ctrl_rdata_next[31] = pcie_dma_write_desc_status_valid_reg;
+                pcie_dma_write_desc_status_valid_next = 1'b0;
+            end
+            16'h0400: axil_ctrl_rdata_next = pcie_rq_count_reg;
+            16'h0404: axil_ctrl_rdata_next = pcie_rc_count_reg;
+            16'h0408: axil_ctrl_rdata_next = pcie_cq_count_reg;
+            16'h040C: axil_ctrl_rdata_next = pcie_cc_count_reg;
+        endcase
+    end
+
+    if (pcie_dma_read_desc_status_valid) begin
+        pcie_dma_read_desc_status_tag_next = pcie_dma_read_desc_status_tag;
+        pcie_dma_read_desc_status_error_next = pcie_dma_read_desc_status_error;
+        pcie_dma_read_desc_status_valid_next = pcie_dma_read_desc_status_valid;
+    end
+
+    if (pcie_dma_write_desc_status_valid) begin
+        pcie_dma_write_desc_status_tag_next = pcie_dma_write_desc_status_tag;
+        pcie_dma_write_desc_status_error_next = pcie_dma_write_desc_status_error;
+        pcie_dma_write_desc_status_valid_next = pcie_dma_write_desc_status_valid;
+    end
+end
+
+always @(posedge clk) begin
+    axil_ctrl_awready_reg <= axil_ctrl_awready_next;
+    axil_ctrl_wready_reg <= axil_ctrl_wready_next;
+    axil_ctrl_bresp_reg <= axil_ctrl_bresp_next;
+    axil_ctrl_bvalid_reg <= axil_ctrl_bvalid_next;
+    axil_ctrl_arready_reg <= axil_ctrl_arready_next;
+    axil_ctrl_rdata_reg <= axil_ctrl_rdata_next;
+    axil_ctrl_rresp_reg <= axil_ctrl_rresp_next;
+    axil_ctrl_rvalid_reg <= axil_ctrl_rvalid_next;
+
+    pcie_dma_read_desc_pcie_addr_reg <= pcie_dma_read_desc_pcie_addr_next;
+    pcie_dma_read_desc_axi_addr_reg <= pcie_dma_read_desc_axi_addr_next;
+    pcie_dma_read_desc_len_reg <= pcie_dma_read_desc_len_next;
+    pcie_dma_read_desc_tag_reg <= pcie_dma_read_desc_tag_next;
+    pcie_dma_read_desc_valid_reg <= pcie_dma_read_desc_valid_next;
+
+    pcie_dma_read_desc_status_tag_reg <= pcie_dma_read_desc_status_tag_next;
+    pcie_dma_read_desc_status_error_reg <= pcie_dma_read_desc_status_error_next;
+    pcie_dma_read_desc_status_valid_reg <= pcie_dma_read_desc_status_valid_next;
+
+    pcie_dma_write_desc_pcie_addr_reg <= pcie_dma_write_desc_pcie_addr_next;
+    pcie_dma_write_desc_axi_addr_reg <= pcie_dma_write_desc_axi_addr_next;
+    pcie_dma_write_desc_len_reg <= pcie_dma_write_desc_len_next;
+    pcie_dma_write_desc_tag_reg <= pcie_dma_write_desc_tag_next;
+    pcie_dma_write_desc_valid_reg <= pcie_dma_write_desc_valid_next;
+
+    pcie_dma_write_desc_status_tag_reg <= pcie_dma_write_desc_status_tag_next;
+    pcie_dma_write_desc_status_error_reg <= pcie_dma_write_desc_status_error_next;
+    pcie_dma_write_desc_status_valid_reg <= pcie_dma_write_desc_status_valid_next;
+
+    pcie_dma_enable_reg <= pcie_dma_enable_next;
+
+    if (m_axis_rq_tready && m_axis_rq_tvalid && m_axis_rq_tlast) begin
+        pcie_rq_count_reg <= pcie_rq_count_reg + 1;
+    end
+
+    if (s_axis_rc_tready && s_axis_rc_tvalid && s_axis_rc_tlast) begin
+        pcie_rc_count_reg <= pcie_rc_count_reg + 1;
+    end
+
+    if (s_axis_cq_tready && s_axis_cq_tvalid && s_axis_cq_tlast) begin
+        pcie_cq_count_reg <= pcie_cq_count_reg + 1;
+    end
+
+    if (m_axis_cc_tready && m_axis_cc_tvalid && m_axis_cc_tlast) begin
+        pcie_cc_count_reg <= pcie_cc_count_reg + 1;
+    end
+
+    if (rst) begin
+        axil_ctrl_awready_reg <= 1'b0;
+        axil_ctrl_wready_reg <= 1'b0;
+        axil_ctrl_bvalid_reg <= 1'b0;
+        axil_ctrl_arready_reg <= 1'b0;
+        axil_ctrl_rvalid_reg <= 1'b0;
+
+        pcie_dma_read_desc_valid_reg <= 1'b0;
+        pcie_dma_read_desc_status_valid_reg <= 1'b0;
+        pcie_dma_write_desc_valid_reg <= 1'b0;
+        pcie_dma_write_desc_status_valid_reg <= 1'b0;
+        pcie_dma_enable_reg <= 1'b0;
+
+        pcie_rq_count_reg <= 0;
+        pcie_rc_count_reg <= 0;
+        pcie_cq_count_reg <= 0;
+        pcie_cc_count_reg <= 0;
+    end
+end
+
+assign qsfp_led_act = 1'b0;
+assign qsfp_led_stat_g = 1'b0;
+assign qsfp_led_stat_y = 1'b0;
+
+pcie_us_cfg #(
+    .PF_COUNT(1),
+    .VF_COUNT(0),
+    .VF_OFFSET(4),
+    .PCIE_CAP_OFFSET(12'h070)
+)
+pcie_us_cfg_inst (
+    .clk(clk),
+    .rst(rst),
+
+    /*
+     * Configuration outputs
+     */
+    .ext_tag_enable(ext_tag_enable),
+    .max_read_request_size(),
+    .max_payload_size(),
+
+    /*
+     * Interface to Ultrascale PCIe IP core
+     */
+    .cfg_mgmt_addr(cfg_mgmt_addr),
+    .cfg_mgmt_function_number(cfg_mgmt_function_number),
+    .cfg_mgmt_write(cfg_mgmt_write),
+    .cfg_mgmt_write_data(cfg_mgmt_write_data),
+    .cfg_mgmt_byte_enable(cfg_mgmt_byte_enable),
+    .cfg_mgmt_read(cfg_mgmt_read),
+    .cfg_mgmt_read_data(cfg_mgmt_read_data),
+    .cfg_mgmt_read_write_done(cfg_mgmt_read_write_done)
+);
+
+pcie_us_axil_master #(
+    .AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
+    .AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
+    .AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH),
+    .AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH),
+    .AXI_DATA_WIDTH(AXIL_DATA_WIDTH),
+    .AXI_ADDR_WIDTH(AXIL_ADDR_WIDTH),
+    .ENABLE_PARITY(0)
+)
+pcie_us_axil_master_inst (
+    .clk(clk),
+    .rst(rst),
+
+    /*
+     * AXI input (CQ)
+     */
+    .s_axis_cq_tdata(axis_cq_tdata_bar_0),
+    .s_axis_cq_tkeep(axis_cq_tkeep_bar_0),
+    .s_axis_cq_tvalid(axis_cq_tvalid_bar_0),
+    .s_axis_cq_tready(axis_cq_tready_bar_0),
+    .s_axis_cq_tlast(axis_cq_tlast_bar_0),
+    .s_axis_cq_tuser(axis_cq_tuser_bar_0),
+
+    /*
+     * AXI input (CC)
+     */
+    .m_axis_cc_tdata(axis_cc_tdata_bar_0),
+    .m_axis_cc_tkeep(axis_cc_tkeep_bar_0),
+    .m_axis_cc_tvalid(axis_cc_tvalid_bar_0),
+    .m_axis_cc_tready(axis_cc_tready_bar_0),
+    .m_axis_cc_tlast(axis_cc_tlast_bar_0),
+    .m_axis_cc_tuser(axis_cc_tuser_bar_0),
+
+    /*
+     * AXI Lite Master output
+     */
+    .m_axil_awaddr(axil_ctrl_awaddr),
+    .m_axil_awprot(axil_ctrl_awprot),
+    .m_axil_awvalid(axil_ctrl_awvalid),
+    .m_axil_awready(axil_ctrl_awready),
+    .m_axil_wdata(axil_ctrl_wdata),
+    .m_axil_wstrb(axil_ctrl_wstrb),
+    .m_axil_wvalid(axil_ctrl_wvalid),
+    .m_axil_wready(axil_ctrl_wready),
+    .m_axil_bresp(axil_ctrl_bresp),
+    .m_axil_bvalid(axil_ctrl_bvalid),
+    .m_axil_bready(axil_ctrl_bready),
+    .m_axil_araddr(axil_ctrl_araddr),
+    .m_axil_arprot(axil_ctrl_arprot),
+    .m_axil_arvalid(axil_ctrl_arvalid),
+    .m_axil_arready(axil_ctrl_arready),
+    .m_axil_rdata(axil_ctrl_rdata),
+    .m_axil_rresp(axil_ctrl_rresp),
+    .m_axil_rvalid(axil_ctrl_rvalid),
+    .m_axil_rready(axil_ctrl_rready),
+
+    /*
+     * Configuration
+     */
+    .completer_id({8'd0, 5'd0, 3'd0}),
+    .completer_id_enable(1'b0),
+
+    /*
+     * Status
+     */
+    .status_error_cor(status_error_cor_int[0]),
+    .status_error_uncor(status_error_uncor_int[0])
+);
+
+pcie_us_axi_master #(
+    .AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
+    .AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
+    .AXIS_PCIE_CQ_USER_WIDTH(AXIS_PCIE_CQ_USER_WIDTH),
+    .AXIS_PCIE_CC_USER_WIDTH(AXIS_PCIE_CC_USER_WIDTH),
+    .AXI_DATA_WIDTH(AXI_DATA_WIDTH),
+    .AXI_ADDR_WIDTH(AXI_ADDR_WIDTH),
+    .AXI_STRB_WIDTH(AXI_STRB_WIDTH),
+    .AXI_ID_WIDTH(AXI_ID_WIDTH)
+)
+pcie_us_axi_master_inst (
+    .clk(clk),
+    .rst(rst),
+
+    /*
+     * AXI input (CQ)
+     */
+    .s_axis_cq_tdata(axis_cq_tdata_bar_2),
+    .s_axis_cq_tkeep(axis_cq_tkeep_bar_2),
+    .s_axis_cq_tvalid(axis_cq_tvalid_bar_2),
+    .s_axis_cq_tready(axis_cq_tready_bar_2),
+    .s_axis_cq_tlast(axis_cq_tlast_bar_2),
+    .s_axis_cq_tuser(axis_cq_tuser_bar_2),
+
+    /*
+     * AXI output (CC)
+     */
+    .m_axis_cc_tdata(axis_cc_tdata_bar_2),
+    .m_axis_cc_tkeep(axis_cc_tkeep_bar_2),
+    .m_axis_cc_tvalid(axis_cc_tvalid_bar_2),
+    .m_axis_cc_tready(axis_cc_tready_bar_2),
+    .m_axis_cc_tlast(axis_cc_tlast_bar_2),
+    .m_axis_cc_tuser(axis_cc_tuser_bar_2),
+
+    /*
+     * AXI Master output
+     */
+    .m_axi_awid(axi_awid),
+    .m_axi_awaddr(axi_awaddr),
+    .m_axi_awlen(axi_awlen),
+    .m_axi_awsize(axi_awsize),
+    .m_axi_awburst(axi_awburst),
+    .m_axi_awlock(axi_awlock),
+    .m_axi_awcache(axi_awcache),
+    .m_axi_awprot(axi_awprot),
+    .m_axi_awvalid(axi_awvalid),
+    .m_axi_awready(axi_awready),
+    .m_axi_wdata(axi_wdata),
+    .m_axi_wstrb(axi_wstrb),
+    .m_axi_wlast(axi_wlast),
+    .m_axi_wvalid(axi_wvalid),
+    .m_axi_wready(axi_wready),
+    .m_axi_bid(axi_bid),
+    .m_axi_bresp(axi_bresp),
+    .m_axi_bvalid(axi_bvalid),
+    .m_axi_bready(axi_bready),
+    .m_axi_arid(axi_arid),
+    .m_axi_araddr(axi_araddr),
+    .m_axi_arlen(axi_arlen),
+    .m_axi_arsize(axi_arsize),
+    .m_axi_arburst(axi_arburst),
+    .m_axi_arlock(axi_arlock),
+    .m_axi_arcache(axi_arcache),
+    .m_axi_arprot(axi_arprot),
+    .m_axi_arvalid(axi_arvalid),
+    .m_axi_arready(axi_arready),
+    .m_axi_rid(axi_rid),
+    .m_axi_rdata(axi_rdata),
+    .m_axi_rresp(axi_rresp),
+    .m_axi_rlast(axi_rlast),
+    .m_axi_rvalid(axi_rvalid),
+    .m_axi_rready(axi_rready),
+
+    /*
+     * Configuration
+     */
+    .completer_id({8'd0, 5'd0, 3'd1}),
+    .completer_id_enable(1'b0),
+    .max_payload_size(cfg_max_payload),
+
+    /*
+     * Status
+     */
+    .status_error_cor(status_error_cor_int[1]),
+    .status_error_uncor(status_error_uncor_int[1])
+);
+
+axi_ram #(
+    .DATA_WIDTH(AXI_DATA_WIDTH),
+    .ADDR_WIDTH(16),
+    .ID_WIDTH(AXI_ID_WIDTH),
+    .PIPELINE_OUTPUT(1)
+)
+axi_ram_inst (
+    .clk(clk),
+    .rst(rst),
+    .s_axi_awid(axi_awid),
+    .s_axi_awaddr(axi_awaddr),
+    .s_axi_awlen(axi_awlen),
+    .s_axi_awsize(axi_awsize),
+    .s_axi_awburst(axi_awburst),
+    .s_axi_awlock(axi_awlock),
+    .s_axi_awcache(axi_awcache),
+    .s_axi_awprot(axi_awprot),
+    .s_axi_awvalid(axi_awvalid),
+    .s_axi_awready(axi_awready),
+    .s_axi_wdata(axi_wdata),
+    .s_axi_wstrb(axi_wstrb),
+    .s_axi_wlast(axi_wlast),
+    .s_axi_wvalid(axi_wvalid),
+    .s_axi_wready(axi_wready),
+    .s_axi_bid(axi_bid),
+    .s_axi_bresp(axi_bresp),
+    .s_axi_bvalid(axi_bvalid),
+    .s_axi_bready(axi_bready),
+    .s_axi_arid(axi_arid),
+    .s_axi_araddr(axi_araddr),
+    .s_axi_arlen(axi_arlen),
+    .s_axi_arsize(axi_arsize),
+    .s_axi_arburst(axi_arburst),
+    .s_axi_arlock(axi_arlock),
+    .s_axi_arcache(axi_arcache),
+    .s_axi_arprot(axi_arprot),
+    .s_axi_arvalid(axi_arvalid),
+    .s_axi_arready(axi_arready),
+    .s_axi_rid(axi_rid),
+    .s_axi_rdata(axi_rdata),
+    .s_axi_rresp(axi_rresp),
+    .s_axi_rlast(axi_rlast),
+    .s_axi_rvalid(axi_rvalid),
+    .s_axi_rready(axi_rready)
+);
+
+wire [AXIS_PCIE_DATA_WIDTH-1:0]    axis_rc_tdata_r;
+wire [AXIS_PCIE_KEEP_WIDTH-1:0]    axis_rc_tkeep_r;
+wire                               axis_rc_tlast_r;
+wire                               axis_rc_tready_r;
+wire [AXIS_PCIE_RC_USER_WIDTH-1:0] axis_rc_tuser_r;
+wire                               axis_rc_tvalid_r;
+
+axis_register #(
+    .DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
+    .KEEP_ENABLE(1),
+    .KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
+    .LAST_ENABLE(1),
+    .ID_ENABLE(0),
+    .DEST_ENABLE(0),
+    .USER_ENABLE(1),
+    .USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH)
+)
+rc_reg (
+    .clk(clk),
+    .rst(rst),
+
+    /*
+     * AXI input
+     */
+    .s_axis_tdata(s_axis_rc_tdata),
+    .s_axis_tkeep(s_axis_rc_tkeep),
+    .s_axis_tvalid(s_axis_rc_tvalid),
+    .s_axis_tready(s_axis_rc_tready),
+    .s_axis_tlast(s_axis_rc_tlast),
+    .s_axis_tid(0),
+    .s_axis_tdest(0),
+    .s_axis_tuser(s_axis_rc_tuser),
+
+    /*
+     * AXI output
+     */
+    .m_axis_tdata(axis_rc_tdata_r),
+    .m_axis_tkeep(axis_rc_tkeep_r),
+    .m_axis_tvalid(axis_rc_tvalid_r),
+    .m_axis_tready(axis_rc_tready_r),
+    .m_axis_tlast(axis_rc_tlast_r),
+    .m_axis_tid(),
+    .m_axis_tdest(),
+    .m_axis_tuser(axis_rc_tuser_r)
+);
+
+pcie_us_axi_dma #(
+    .AXIS_PCIE_DATA_WIDTH(AXIS_PCIE_DATA_WIDTH),
+    .AXIS_PCIE_KEEP_WIDTH(AXIS_PCIE_KEEP_WIDTH),
+    .AXIS_PCIE_RC_USER_WIDTH(AXIS_PCIE_RC_USER_WIDTH),
+    .AXIS_PCIE_RQ_USER_WIDTH(AXIS_PCIE_RQ_USER_WIDTH),
+    .AXI_DATA_WIDTH(AXI_DATA_WIDTH),
+    .AXI_ADDR_WIDTH(AXI_ADDR_WIDTH),
+    .AXI_STRB_WIDTH(AXI_STRB_WIDTH),
+    .AXI_ID_WIDTH(AXI_ID_WIDTH),
+    .AXI_MAX_BURST_LEN(256),
+    .PCIE_ADDR_WIDTH(PCIE_ADDR_WIDTH),
+    .PCIE_TAG_COUNT(256),
+    .LEN_WIDTH(16),
+    .TAG_WIDTH(DMA_TAG_WIDTH)
+)
+pcie_us_axi_dma_inst (
+    .clk(clk),
+    .rst(rst),
+
+    /*
+     * AXI input (RC)
+     */
+    .s_axis_rc_tdata(axis_rc_tdata_r),
+    .s_axis_rc_tkeep(axis_rc_tkeep_r),
+    .s_axis_rc_tvalid(axis_rc_tvalid_r),
+    .s_axis_rc_tready(axis_rc_tready_r),
+    .s_axis_rc_tlast(axis_rc_tlast_r),
+    .s_axis_rc_tuser(axis_rc_tuser_r),
+
+    /*
+     * AXI output (RQ)
+     */
+    .m_axis_rq_tdata(m_axis_rq_tdata),
+    .m_axis_rq_tkeep(m_axis_rq_tkeep),
+    .m_axis_rq_tvalid(m_axis_rq_tvalid),
+    .m_axis_rq_tready(m_axis_rq_tready),
+    .m_axis_rq_tlast(m_axis_rq_tlast),
+    .m_axis_rq_tuser(m_axis_rq_tuser),
+
+    /*
+     * AXI read descriptor input
+     */
+    .s_axis_read_desc_pcie_addr(pcie_dma_read_desc_pcie_addr),
+    .s_axis_read_desc_axi_addr(pcie_dma_read_desc_axi_addr),
+    .s_axis_read_desc_len(pcie_dma_read_desc_len),
+    .s_axis_read_desc_tag(pcie_dma_read_desc_tag),
+    .s_axis_read_desc_valid(pcie_dma_read_desc_valid),
+    .s_axis_read_desc_ready(pcie_dma_read_desc_ready),
+
+    /*
+     * AXI read descriptor status output
+     */
+    .m_axis_read_desc_status_tag(pcie_dma_read_desc_status_tag),
+    .m_axis_read_desc_status_error(pcie_dma_read_desc_status_error),
+    .m_axis_read_desc_status_valid(pcie_dma_read_desc_status_valid),
+
+    /*
+     * AXI write descriptor input
+     */
+    .s_axis_write_desc_pcie_addr(pcie_dma_write_desc_pcie_addr),
+    .s_axis_write_desc_axi_addr(pcie_dma_write_desc_axi_addr),
+    .s_axis_write_desc_len(pcie_dma_write_desc_len),
+    .s_axis_write_desc_tag(pcie_dma_write_desc_tag),
+    .s_axis_write_desc_valid(pcie_dma_write_desc_valid),
+    .s_axis_write_desc_ready(pcie_dma_write_desc_ready),
+
+    /*
+     * AXI write descriptor status output
+     */
+    .m_axis_write_desc_status_tag(pcie_dma_write_desc_status_tag),
+    .m_axis_write_desc_status_error(pcie_dma_write_desc_status_error),
+    .m_axis_write_desc_status_valid(pcie_dma_write_desc_status_valid),
+
+    /*
+     * AXI Master output
+     */
+    .m_axi_awid(axi_dma_awid),
+    .m_axi_awaddr(axi_dma_awaddr),
+    .m_axi_awlen(axi_dma_awlen),
+    .m_axi_awsize(axi_dma_awsize),
+    .m_axi_awburst(axi_dma_awburst),
+    .m_axi_awlock(axi_dma_awlock),
+    .m_axi_awcache(axi_dma_awcache),
+    .m_axi_awprot(axi_dma_awprot),
+    .m_axi_awvalid(axi_dma_awvalid),
+    .m_axi_awready(axi_dma_awready),
+    .m_axi_wdata(axi_dma_wdata),
+    .m_axi_wstrb(axi_dma_wstrb),
+    .m_axi_wlast(axi_dma_wlast),
+    .m_axi_wvalid(axi_dma_wvalid),
+    .m_axi_wready(axi_dma_wready),
+    .m_axi_bid(axi_dma_bid),
+    .m_axi_bresp(axi_dma_bresp),
+    .m_axi_bvalid(axi_dma_bvalid),
+    .m_axi_bready(axi_dma_bready),
+    .m_axi_arid(axi_dma_arid),
+    .m_axi_araddr(axi_dma_araddr),
+    .m_axi_arlen(axi_dma_arlen),
+    .m_axi_arsize(axi_dma_arsize),
+    .m_axi_arburst(axi_dma_arburst),
+    .m_axi_arlock(axi_dma_arlock),
+    .m_axi_arcache(axi_dma_arcache),
+    .m_axi_arprot(axi_dma_arprot),
+    .m_axi_arvalid(axi_dma_arvalid),
+    .m_axi_arready(axi_dma_arready),
+    .m_axi_rid(axi_dma_rid),
+    .m_axi_rdata(axi_dma_rdata),
+    .m_axi_rresp(axi_dma_rresp),
+    .m_axi_rlast(axi_dma_rlast),
+    .m_axi_rvalid(axi_dma_rvalid),
+    .m_axi_rready(axi_dma_rready),
+
+    /*
+     * Configuration
+     */
+    .read_enable(pcie_dma_enable),
+    .write_enable(pcie_dma_enable),
+    .ext_tag_enable(ext_tag_enable),
+    .requester_id({8'd0, 5'd0, 3'd0}),
+    .requester_id_enable(1'b0),
+    .max_read_request_size(cfg_max_read_req),
+    .max_payload_size(cfg_max_payload),
+
+    /*
+     * Status
+     */
+    .status_error_cor(status_error_cor_int[2]),
+    .status_error_uncor(status_error_uncor_int[2])
+);
+
+axi_ram #(
+    .DATA_WIDTH(AXI_DATA_WIDTH),
+    .ADDR_WIDTH(16),
+    .ID_WIDTH(AXI_ID_WIDTH),
+    .PIPELINE_OUTPUT(1)
+)
+axi_dma_ram_inst (
+    .clk(clk),
+    .rst(rst),
+    .s_axi_awid(axi_dma_awid),
+    .s_axi_awaddr(axi_dma_awaddr),
+    .s_axi_awlen(axi_dma_awlen),
+    .s_axi_awsize(axi_dma_awsize),
+    .s_axi_awburst(axi_dma_awburst),
+    .s_axi_awlock(axi_dma_awlock),
+    .s_axi_awcache(axi_dma_awcache),
+    .s_axi_awprot(axi_dma_awprot),
+    .s_axi_awvalid(axi_dma_awvalid),
+    .s_axi_awready(axi_dma_awready),
+    .s_axi_wdata(axi_dma_wdata),
+    .s_axi_wstrb(axi_dma_wstrb),
+    .s_axi_wlast(axi_dma_wlast),
+    .s_axi_wvalid(axi_dma_wvalid),
+    .s_axi_wready(axi_dma_wready),
+    .s_axi_bid(axi_dma_bid),
+    .s_axi_bresp(axi_dma_bresp),
+    .s_axi_bvalid(axi_dma_bvalid),
+    .s_axi_bready(axi_dma_bready),
+    .s_axi_arid(axi_dma_arid),
+    .s_axi_araddr(axi_dma_araddr),
+    .s_axi_arlen(axi_dma_arlen),
+    .s_axi_arsize(axi_dma_arsize),
+    .s_axi_arburst(axi_dma_arburst),
+    .s_axi_arlock(axi_dma_arlock),
+    .s_axi_arcache(axi_dma_arcache),
+    .s_axi_arprot(axi_dma_arprot),
+    .s_axi_arvalid(axi_dma_arvalid),
+    .s_axi_arready(axi_dma_arready),
+    .s_axi_rid(axi_dma_rid),
+    .s_axi_rdata(axi_dma_rdata),
+    .s_axi_rresp(axi_dma_rresp),
+    .s_axi_rlast(axi_dma_rlast),
+    .s_axi_rvalid(axi_dma_rvalid),
+    .s_axi_rready(axi_dma_rready)
+);
+
+pulse_merge #(
+    .INPUT_WIDTH(3),
+    .COUNT_WIDTH(4)
+)
+status_error_cor_pm_inst (
+    .clk(clk),
+    .rst(rst),
+
+    .pulse_in(status_error_cor_int),
+    .count_out(),
+    .pulse_out(status_error_cor)
+);
+
+pulse_merge #(
+    .INPUT_WIDTH(3),
+    .COUNT_WIDTH(4)
+)
+status_error_uncor_pm_inst (
+    .clk(clk),
+    .rst(rst),
+
+    .pulse_in(status_error_uncor_int),
+    .count_out(),
+    .pulse_out(status_error_uncor)
+);
+
+pcie_us_msi #(
+    .MSI_COUNT(32)
+)
+pcie_us_msi_inst (
+    .clk(clk),
+    .rst(rst),
+
+    .msi_irq(msi_irq),
+
+    .cfg_interrupt_msi_enable(cfg_interrupt_msi_enable),
+    .cfg_interrupt_msi_vf_enable(0),
+    .cfg_interrupt_msi_mmenable(cfg_interrupt_msi_mmenable),
+    .cfg_interrupt_msi_mask_update(cfg_interrupt_msi_mask_update),
+    .cfg_interrupt_msi_data(cfg_interrupt_msi_data),
+    .cfg_interrupt_msi_select(cfg_interrupt_msi_select),
+    .cfg_interrupt_msi_int(cfg_interrupt_msi_int),
+    .cfg_interrupt_msi_pending_status(cfg_interrupt_msi_pending_status),
+    .cfg_interrupt_msi_pending_status_data_enable(cfg_interrupt_msi_pending_status_data_enable),
+    .cfg_interrupt_msi_pending_status_function_num(cfg_interrupt_msi_pending_status_function_num),
+    .cfg_interrupt_msi_sent(cfg_interrupt_msi_sent),
+    .cfg_interrupt_msi_fail(cfg_interrupt_msi_fail),
+    .cfg_interrupt_msi_attr(cfg_interrupt_msi_attr),
+    .cfg_interrupt_msi_tph_present(cfg_interrupt_msi_tph_present),
+    .cfg_interrupt_msi_tph_type(cfg_interrupt_msi_tph_type),
+    .cfg_interrupt_msi_tph_st_tag(cfg_interrupt_msi_tph_st_tag),
+    .cfg_interrupt_msi_function_number(cfg_interrupt_msi_function_number)
+);
+
+endmodule
+
+`resetall

snapshots/alexforencich_verilog-pcie_pr20/example/AU50/fpga_axi/rtl/sync_reset.v

@@ -0,0 +1,56 @@
+/*
+
+Copyright (c) 2014-2018 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog-2001
+
+`resetall
+`timescale 1 ns / 1 ps
+`default_nettype none
+
+/*
+ * Synchronizes an active-high asynchronous reset signal to a given clock by
+ * using a pipeline of N registers.
+ */
+module sync_reset #(
+    parameter N=2 // depth of synchronizer
+)(
+    input wire clk,
+    input wire rst,
+    output wire sync_reset_out
+);
+
+reg [N-1:0] sync_reg = {N{1'b1}};
+
+assign sync_reset_out = sync_reg[N-1];
+
+always @(posedge clk or posedge rst) begin
+    if (rst)
+        sync_reg <= {N{1'b1}};
+    else
+        sync_reg <= {sync_reg[N-2:0], 1'b0};
+end
+
+endmodule
+
+`resetall

snapshots/alexforencich_verilog-pcie_pr20/example/AU50/fpga_axi/rtl/sync_signal.v

@@ -0,0 +1,62 @@
+/*
+
+Copyright (c) 2014-2018 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+*/
+
+// Language: Verilog-2001
+
+`resetall
+`timescale 1 ns / 1 ps
+`default_nettype none
+
+/*
+ * Synchronizes an asyncronous signal to a given clock by using a pipeline of
+ * two registers.
+ */
+module sync_signal #(
+    parameter WIDTH=1, // width of the input and output signals
+    parameter N=2 // depth of synchronizer
+)(
+    input wire clk,
+    input wire [WIDTH-1:0] in,
+    output wire [WIDTH-1:0] out
+);
+
+reg [WIDTH-1:0] sync_reg[N-1:0];
+
+/*
+ * The synchronized output is the last register in the pipeline.
+ */
+assign out = sync_reg[N-1];
+
+integer k;
+
+always @(posedge clk) begin
+    sync_reg[0] <= in;
+    for (k = 1; k < N; k = k + 1) begin
+        sync_reg[k] <= sync_reg[k-1];
+    end
+end
+
+endmodule
+
+`resetall

snapshots/alexforencich_verilog-pcie_pr20/example/AU50/fpga_axi/tb/fpga_core/Makefile

@@ -0,0 +1,102 @@
+# Copyright (c) 2020 Alex Forencich
+#
+# Permission is hereby granted, free of charge, to any person obtaining a copy
+# of this software and associated documentation files (the "Software"), to deal
+# in the Software without restriction, including without limitation the rights
+# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+# copies of the Software, and to permit persons to whom the Software is
+# furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+# THE SOFTWARE.
+
+TOPLEVEL_LANG = verilog
+
+SIM ?= icarus
+WAVES ?= 0
+
+COCOTB_HDL_TIMEUNIT = 1ns
+COCOTB_HDL_TIMEPRECISION = 1ps
+
+DUT      = fpga_core
+TOPLEVEL = $(DUT)
+MODULE   = test_$(DUT)
+VERILOG_SOURCES += ../../rtl/$(DUT).v
+VERILOG_SOURCES += ../../rtl/axi_ram.v
+VERILOG_SOURCES += ../../rtl/axis_register.v
+VERILOG_SOURCES += ../../lib/pcie/rtl/axis_arb_mux.v
+VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_axil_master.v
+VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_axi_dma.v
+VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_axi_dma_rd.v
+VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_axi_dma_wr.v
+VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_axi_master.v
+VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_axi_master_rd.v
+VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_axi_master_wr.v
+VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_axis_cq_demux.v
+VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_cfg.v
+VERILOG_SOURCES += ../../lib/pcie/rtl/pcie_us_msi.v
+VERILOG_SOURCES += ../../lib/pcie/rtl/arbiter.v
+VERILOG_SOURCES += ../../lib/pcie/rtl/priority_encoder.v
+VERILOG_SOURCES += ../../lib/pcie/rtl/pulse_merge.v
+
+# module parameters
+export PARAM_AXIS_PCIE_DATA_WIDTH ?= 512
+export PARAM_AXIS_PCIE_KEEP_WIDTH ?= $(shell expr $(PARAM_AXIS_PCIE_DATA_WIDTH) / 32 )
+export PARAM_AXIS_PCIE_RQ_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),62,137)
+export PARAM_AXIS_PCIE_RC_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),75,161)
+export PARAM_AXIS_PCIE_CQ_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),88,183)
+export PARAM_AXIS_PCIE_CC_USER_WIDTH ?= $(if $(filter-out 512,$(PARAM_AXIS_PCIE_DATA_WIDTH)),33,81)
+export PARAM_RQ_SEQ_NUM_WIDTH ?= 6
+
+ifeq ($(SIM), icarus)
+	PLUSARGS += -fst
+
+	COMPILE_ARGS += -P $(TOPLEVEL).AXIS_PCIE_DATA_WIDTH=$(PARAM_AXIS_PCIE_DATA_WIDTH)
+	COMPILE_ARGS += -P $(TOPLEVEL).AXIS_PCIE_KEEP_WIDTH=$(PARAM_AXIS_PCIE_KEEP_WIDTH)
+	COMPILE_ARGS += -P $(TOPLEVEL).AXIS_PCIE_RQ_USER_WIDTH=$(PARAM_AXIS_PCIE_RQ_USER_WIDTH)
+	COMPILE_ARGS += -P $(TOPLEVEL).AXIS_PCIE_RC_USER_WIDTH=$(PARAM_AXIS_PCIE_RC_USER_WIDTH)
+	COMPILE_ARGS += -P $(TOPLEVEL).AXIS_PCIE_CQ_USER_WIDTH=$(PARAM_AXIS_PCIE_CQ_USER_WIDTH)
+	COMPILE_ARGS += -P $(TOPLEVEL).AXIS_PCIE_CC_USER_WIDTH=$(PARAM_AXIS_PCIE_CC_USER_WIDTH)
+	COMPILE_ARGS += -P $(TOPLEVEL).RQ_SEQ_NUM_WIDTH=$(PARAM_RQ_SEQ_NUM_WIDTH)
+
+	ifeq ($(WAVES), 1)
+		VERILOG_SOURCES += iverilog_dump.v
+		COMPILE_ARGS += -s iverilog_dump
+	endif
+else ifeq ($(SIM), verilator)
+	COMPILE_ARGS += -Wno-SELRANGE -Wno-WIDTH
+
+	COMPILE_ARGS += -GAXIS_PCIE_DATA_WIDTH=$(PARAM_AXIS_PCIE_DATA_WIDTH)
+	COMPILE_ARGS += -GAXIS_PCIE_KEEP_WIDTH=$(PARAM_AXIS_PCIE_KEEP_WIDTH)
+	COMPILE_ARGS += -GAXIS_PCIE_RQ_USER_WIDTH=$(PARAM_AXIS_PCIE_RQ_USER_WIDTH)
+	COMPILE_ARGS += -GAXIS_PCIE_RC_USER_WIDTH=$(PARAM_AXIS_PCIE_RC_USER_WIDTH)
+	COMPILE_ARGS += -GAXIS_PCIE_CQ_USER_WIDTH=$(PARAM_AXIS_PCIE_CQ_USER_WIDTH)
+	COMPILE_ARGS += -GAXIS_PCIE_CC_USER_WIDTH=$(PARAM_AXIS_PCIE_CC_USER_WIDTH)
+	COMPILE_ARGS += -GRQ_SEQ_NUM_WIDTH=$(PARAM_RQ_SEQ_NUM_WIDTH)
+
+	ifeq ($(WAVES), 1)
+		COMPILE_ARGS += --trace-fst
+	endif
+endif
+
+include $(shell cocotb-config --makefiles)/Makefile.sim
+
+iverilog_dump.v:
+	echo 'module iverilog_dump();' > $@
+	echo 'initial begin' >> $@
+	echo '    $$dumpfile("$(TOPLEVEL).fst");' >> $@
+	echo '    $$dumpvars(0, $(TOPLEVEL));' >> $@
+	echo 'end' >> $@
+	echo 'endmodule' >> $@
+
+clean::
+	@rm -rf iverilog_dump.v
+	@rm -rf dump.fst $(TOPLEVEL).fst

snapshots/alexforencich_verilog-pcie_pr20/example/AU50/fpga_axi/tb/fpga_core/test_fpga_core.py

@@ -0,0 +1,374 @@
+"""
+
+Copyright (c) 2020 Alex Forencich
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in
+all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+THE SOFTWARE.
+
+"""
+
+import logging
+import os
+
+import cocotb_test.simulator
+
+import cocotb
+from cocotb.log import SimLog
+from cocotb.triggers import RisingEdge, FallingEdge, Timer
+
+from cocotbext.axi import AxiStreamBus
+from cocotbext.pcie.core import RootComplex
+from cocotbext.pcie.xilinx.us import UltraScalePlusPcieDevice
+from cocotbext.axi.utils import hexdump_str
+
+
+class TB(object):
+    def __init__(self, dut):
+        self.dut = dut
+
+        self.log = SimLog("cocotb.tb")
+        self.log.setLevel(logging.DEBUG)
+
+        # PCIe
+        self.rc = RootComplex()
+
+        self.dev = UltraScalePlusPcieDevice(
+            # configuration options
+            pcie_generation=3,
+            pcie_link_width=16,
+            user_clk_frequency=250e6,
+            alignment="dword",
+            cq_cc_straddle=False,
+            rq_rc_straddle=False,
+            rc_4tlp_straddle=False,
+            enable_pf1=False,
+            enable_client_tag=True,
+            enable_extended_tag=True,
+            enable_parity=False,
+            enable_rx_msg_interface=False,
+            enable_sriov=False,
+            enable_extended_configuration=False,
+
+            enable_pf0_msi=True,
+            enable_pf1_msi=False,
+
+            # signals
+            # Clock and Reset Interface
+            user_clk=dut.clk,
+            user_reset=dut.rst,
+            # user_lnk_up
+            # sys_clk
+            # sys_clk_gt
+            # sys_reset
+            # phy_rdy_out
+
+            # Requester reQuest Interface
+            rq_bus=AxiStreamBus.from_prefix(dut, "m_axis_rq"),
+            # pcie_rq_seq_num0=dut.s_axis_rq_seq_num_0,
+            # pcie_rq_seq_num_vld0=dut.s_axis_rq_seq_num_valid_0,
+            # pcie_rq_seq_num1=dut.s_axis_rq_seq_num_1,
+            # pcie_rq_seq_num_vld1=dut.s_axis_rq_seq_num_valid_1,
+            # pcie_rq_tag0
+            # pcie_rq_tag1
+            # pcie_rq_tag_av
+            # pcie_rq_tag_vld0
+            # pcie_rq_tag_vld1
+
+            # Requester Completion Interface
+            rc_bus=AxiStreamBus.from_prefix(dut, "s_axis_rc"),
+
+            # Completer reQuest Interface
+            cq_bus=AxiStreamBus.from_prefix(dut, "s_axis_cq"),
+            # pcie_cq_np_req
+            # pcie_cq_np_req_count
+
+            # Completer Completion Interface
+            cc_bus=AxiStreamBus.from_prefix(dut, "m_axis_cc"),
+
+            # Transmit Flow Control Interface
+            # pcie_tfc_nph_av=dut.pcie_tfc_nph_av,
+            # pcie_tfc_npd_av=dut.pcie_tfc_npd_av,
+
+            # Configuration Management Interface
+            cfg_mgmt_addr=dut.cfg_mgmt_addr,
+            cfg_mgmt_function_number=dut.cfg_mgmt_function_number,
+            cfg_mgmt_write=dut.cfg_mgmt_write,
+            cfg_mgmt_write_data=dut.cfg_mgmt_write_data,
+            cfg_mgmt_byte_enable=dut.cfg_mgmt_byte_enable,
+            cfg_mgmt_read=dut.cfg_mgmt_read,
+            cfg_mgmt_read_data=dut.cfg_mgmt_read_data,
+            cfg_mgmt_read_write_done=dut.cfg_mgmt_read_write_done,
+            # cfg_mgmt_debug_access
+
+            # Configuration Status Interface
+            # cfg_phy_link_down
+            # cfg_phy_link_status
+            # cfg_negotiated_width
+            # cfg_current_speed
+            cfg_max_payload=dut.cfg_max_payload,
+            cfg_max_read_req=dut.cfg_max_read_req,
+            # cfg_function_status
+            # cfg_vf_status
+            # cfg_function_power_state
+            # cfg_vf_power_state
+            # cfg_link_power_state
+            # cfg_err_cor_out
+            # cfg_err_nonfatal_out
+            # cfg_err_fatal_out
+            # cfg_local_error_out
+            # cfg_local_error_valid
+            # cfg_rx_pm_state
+            # cfg_tx_pm_state
+            # cfg_ltssm_state
+            # cfg_rcb_status
+            # cfg_obff_enable
+            # cfg_pl_status_change
+            # cfg_tph_requester_enable
+            # cfg_tph_st_mode
+            # cfg_vf_tph_requester_enable
+            # cfg_vf_tph_st_mode
+
+            # Configuration Received Message Interface
+            # cfg_msg_received
+            # cfg_msg_received_data
+            # cfg_msg_received_type
+
+            # Configuration Transmit Message Interface
+            # cfg_msg_transmit
+            # cfg_msg_transmit_type
+            # cfg_msg_transmit_data
+            # cfg_msg_transmit_done
+
+            # Configuration Flow Control Interface
+            # cfg_fc_ph=dut.cfg_fc_ph,
+            # cfg_fc_pd=dut.cfg_fc_pd,
+            # cfg_fc_nph=dut.cfg_fc_nph,
+            # cfg_fc_npd=dut.cfg_fc_npd,
+            # cfg_fc_cplh=dut.cfg_fc_cplh,
+            # cfg_fc_cpld=dut.cfg_fc_cpld,
+            # cfg_fc_sel=dut.cfg_fc_sel,
+
+            # Configuration Control Interface
+            # cfg_hot_reset_in
+            # cfg_hot_reset_out
+            # cfg_config_space_enable
+            # cfg_dsn
+            # cfg_bus_number
+            # cfg_ds_port_number
+            # cfg_ds_bus_number
+            # cfg_ds_device_number
+            # cfg_ds_function_number
+            # cfg_power_state_change_ack
+            # cfg_power_state_change_interrupt
+            cfg_err_cor_in=dut.status_error_cor,
+            cfg_err_uncor_in=dut.status_error_uncor,
+            # cfg_flr_in_process
+            # cfg_flr_done
+            # cfg_vf_flr_in_process
+            # cfg_vf_flr_func_num
+            # cfg_vf_flr_done
+            # cfg_pm_aspm_l1_entry_reject
+            # cfg_pm_aspm_tx_l0s_entry_disable
+            # cfg_req_pm_transition_l23_ready
+            # cfg_link_training_enable
+
+            # Configuration Interrupt Controller Interface
+            # cfg_interrupt_int
+            # cfg_interrupt_sent
+            # cfg_interrupt_pending
+            cfg_interrupt_msi_enable=dut.cfg_interrupt_msi_enable,
+            cfg_interrupt_msi_mmenable=dut.cfg_interrupt_msi_mmenable,
+            cfg_interrupt_msi_mask_update=dut.cfg_interrupt_msi_mask_update,
+            cfg_interrupt_msi_data=dut.cfg_interrupt_msi_data,
+            # cfg_interrupt_msi_select=dut.cfg_interrupt_msi_select,
+            cfg_interrupt_msi_int=dut.cfg_interrupt_msi_int,
+            cfg_interrupt_msi_pending_status=dut.cfg_interrupt_msi_pending_status,
+            cfg_interrupt_msi_pending_status_data_enable=dut.cfg_interrupt_msi_pending_status_data_enable,
+            # cfg_interrupt_msi_pending_status_function_num=dut.cfg_interrupt_msi_pending_status_function_num,
+            cfg_interrupt_msi_sent=dut.cfg_interrupt_msi_sent,
+            cfg_interrupt_msi_fail=dut.cfg_interrupt_msi_fail,
+            # cfg_interrupt_msix_enable
+            # cfg_interrupt_msix_mask
+            # cfg_interrupt_msix_vf_enable
+            # cfg_interrupt_msix_vf_mask
+            # cfg_interrupt_msix_address
+            # cfg_interrupt_msix_data
+            # cfg_interrupt_msix_int
+            # cfg_interrupt_msix_vec_pending
+            # cfg_interrupt_msix_vec_pending_status
+            cfg_interrupt_msi_attr=dut.cfg_interrupt_msi_attr,
+            cfg_interrupt_msi_tph_present=dut.cfg_interrupt_msi_tph_present,
+            cfg_interrupt_msi_tph_type=dut.cfg_interrupt_msi_tph_type,
+            # cfg_interrupt_msi_tph_st_tag=dut.cfg_interrupt_msi_tph_st_tag,
+            # cfg_interrupt_msi_function_number=dut.cfg_interrupt_msi_function_number,
+
+            # Configuration Extend Interface
+            # cfg_ext_read_received
+            # cfg_ext_write_received
+            # cfg_ext_register_number
+            # cfg_ext_function_number
+            # cfg_ext_write_data
+            # cfg_ext_write_byte_enable
+            # cfg_ext_read_data
+            # cfg_ext_read_data_valid
+        )
+
+        # self.dev.log.setLevel(logging.DEBUG)
+
+        self.rc.make_port().connect(self.dev)
+
+        self.dev.functions[0].msi_multiple_message_capable = 5
+
+        self.dev.functions[0].configure_bar(0, 2**22)
+        self.dev.functions[0].configure_bar(2, 2**22)
+
+    async def init(self):
+
+        await FallingEdge(self.dut.rst)
+        await Timer(100, 'ns')
+
+        await self.rc.enumerate(enable_bus_mastering=True, configure_msi=True)
+
+
+@cocotb.test()
+async def run_test(dut):
+
+    tb = TB(dut)
+
+    await tb.init()
+
+    mem = tb.rc.mem_pool.alloc_region(16*1024*1024)
+    mem_base = mem.get_absolute_address(0)
+
+    dev_pf0_bar0 = tb.rc.tree[0][0].bar_window[0]
+    dev_pf0_bar2 = tb.rc.tree[0][0].bar_window[2]
+
+    tb.log.info("Test memory write to BAR 2")
+
+    test_data = b'\x11\x22\x33\x44'
+    await dev_pf0_bar2.write(0, test_data)
+
+    await Timer(100, 'ns')
+
+    tb.log.info("Test memory read from BAR 2")
+
+    val = await dev_pf0_bar2.read(0, len(test_data), timeout=1000)
+    tb.log.info("Read data: %s", val)
+    assert val == test_data
+
+    tb.log.info("Test DMA")
+
+    # write packet data
+    mem[0:1024] = bytearray([x % 256 for x in range(1024)])
+
+    # enable DMA
+    await dev_pf0_bar0.write_dword(0x000000, 1)
+
+    # write pcie read descriptor
+    await dev_pf0_bar0.write_dword(0x000100, (mem_base+0x0000) & 0xffffffff)
+    await dev_pf0_bar0.write_dword(0x000104, (mem_base+0x0000 >> 32) & 0xffffffff)
+    await dev_pf0_bar0.write_dword(0x000108, 0x100)
+    await dev_pf0_bar0.write_dword(0x000110, 0x400)
+    await dev_pf0_bar0.write_dword(0x000114, 0xAA)
+
+    await Timer(2000, 'ns')
+
+    # read status
+    val = await dev_pf0_bar0.read_dword(0x000118)
+    tb.log.info("Status: 0x%x", val)
+    assert val == 0x800000AA
+
+    # write pcie write descriptor
+    await dev_pf0_bar0.write_dword(0x000200, (mem_base+0x1000) & 0xffffffff)
+    await dev_pf0_bar0.write_dword(0x000204, (mem_base+0x1000 >> 32) & 0xffffffff)
+    await dev_pf0_bar0.write_dword(0x000208, 0x100)
+    await dev_pf0_bar0.write_dword(0x000210, 0x400)
+    await dev_pf0_bar0.write_dword(0x000214, 0x55)
+
+    await Timer(2000, 'ns')
+
+    # read status
+    val = await dev_pf0_bar0.read_dword(0x000218)
+    tb.log.info("Status: 0x%x", val)
+    assert val == 0x80000055
+
+    tb.log.info("%s", mem.hexdump_str(0x1000, 64))
+
+    assert mem[0:1024] == mem[0x1000:0x1000+1024]
+
+    await RisingEdge(dut.clk)
+    await RisingEdge(dut.clk)
+
+
+# cocotb-test
+
+tests_dir = os.path.dirname(__file__)
+rtl_dir = os.path.abspath(os.path.join(tests_dir, '..', '..', 'rtl'))
+lib_dir = os.path.abspath(os.path.join(rtl_dir, '..', 'lib'))
+pcie_rtl_dir = os.path.abspath(os.path.join(lib_dir, 'pcie', 'rtl'))
+
+
+def test_fpga_core(request):
+    dut = "fpga_core"
+    module = os.path.splitext(os.path.basename(__file__))[0]
+    toplevel = dut
+
+    verilog_sources = [
+        os.path.join(rtl_dir, f"{dut}.v"),
+        os.path.join(rtl_dir, "axi_ram.v"),
+        os.path.join(rtl_dir, "axis_register.v"),
+        os.path.join(pcie_rtl_dir, "axis_arb_mux.v"),
+        os.path.join(pcie_rtl_dir, "pcie_us_axil_master.v"),
+        os.path.join(pcie_rtl_dir, "pcie_us_axi_dma.v"),
+        os.path.join(pcie_rtl_dir, "pcie_us_axi_dma_rd.v"),
+        os.path.join(pcie_rtl_dir, "pcie_us_axi_dma_wr.v"),
+        os.path.join(pcie_rtl_dir, "pcie_us_axi_master.v"),
+        os.path.join(pcie_rtl_dir, "pcie_us_axi_master_rd.v"),
+        os.path.join(pcie_rtl_dir, "pcie_us_axi_master_wr.v"),
+        os.path.join(pcie_rtl_dir, "pcie_us_axis_cq_demux.v"),
+        os.path.join(pcie_rtl_dir, "pcie_us_cfg.v"),
+        os.path.join(pcie_rtl_dir, "pcie_us_msi.v"),
+        os.path.join(pcie_rtl_dir, "arbiter.v"),
+        os.path.join(pcie_rtl_dir, "priority_encoder.v"),
+        os.path.join(pcie_rtl_dir, "pulse_merge.v"),
+    ]
+
+    parameters = {}
+
+    parameters['AXIS_PCIE_DATA_WIDTH'] = 512
+    parameters['AXIS_PCIE_KEEP_WIDTH'] = parameters['AXIS_PCIE_DATA_WIDTH'] // 32
+    parameters['AXIS_PCIE_RQ_USER_WIDTH'] = 62 if parameters['AXIS_PCIE_DATA_WIDTH'] < 512 else 137
+    parameters['AXIS_PCIE_RC_USER_WIDTH'] = 75 if parameters['AXIS_PCIE_DATA_WIDTH'] < 512 else 161
+    parameters['AXIS_PCIE_CQ_USER_WIDTH'] = 88 if parameters['AXIS_PCIE_DATA_WIDTH'] < 512 else 183
+    parameters['AXIS_PCIE_CC_USER_WIDTH'] = 33 if parameters['AXIS_PCIE_DATA_WIDTH'] < 512 else 81
+    parameters['RQ_SEQ_NUM_WIDTH'] = 6
+
+    extra_env = {f'PARAM_{k}': str(v) for k, v in parameters.items()}
+
+    sim_build = os.path.join(tests_dir, "sim_build",
+        request.node.name.replace('[', '-').replace(']', ''))
+
+    cocotb_test.simulator.run(
+        python_search=[tests_dir],
+        verilog_sources=verilog_sources,
+        toplevel=toplevel,
+        module=module,
+        parameters=parameters,
+        sim_build=sim_build,
+        extra_env=extra_env,
+    )

snapshots/alexforencich_verilog-pcie_pr20/example/ExaNIC_X25/fpga/README.md

@@ -0,0 +1,19 @@
+# Verilog PCIe ExaNIC X25 Example Design
+
+## Introduction
+
+This example design targets the Exablaze ExaNIC X25 FPGA board.
+
+The design implements the PCIe AXI lite master module, the PCIe AXI master module, and the PCIe DMA module.  A very simple Linux driver is included to test the FPGA design.
+
+*  FPGA: xcku3p-ffvb676-2-e
+
+## How to build
+
+Run `make` to build.  Ensure that the Xilinx Vivado components are in PATH.
+
+Run `make` to build the driver.  Ensure the headers for the running kernel are installed, otherwise the driver cannot be compiled.
+
+## How to test
+
+Run `make program` to program the ExaNIC X25 board with Vivado.  Then load the driver with `insmod example.ko`.  Check dmesg for the output.

snapshots/alexforencich_verilog-pcie_pr20/example/ExaNIC_X25/fpga/common/vivado.mk

@@ -0,0 +1,126 @@
+###################################################################
+# 
+# Xilinx Vivado FPGA Makefile
+# 
+# Copyright (c) 2016 Alex Forencich
+# 
+###################################################################
+# 
+# Parameters:
+# FPGA_TOP - Top module name
+# FPGA_FAMILY - FPGA family (e.g. VirtexUltrascale)
+# FPGA_DEVICE - FPGA device (e.g. xcvu095-ffva2104-2-e)
+# SYN_FILES - space-separated list of source files
+# INC_FILES - space-separated list of include files
+# XDC_FILES - space-separated list of timing constraint files
+# XCI_FILES - space-separated list of IP XCI files
+# 
+# Example:
+# 
+# FPGA_TOP = fpga
+# FPGA_FAMILY = VirtexUltrascale
+# FPGA_DEVICE = xcvu095-ffva2104-2-e
+# SYN_FILES = rtl/fpga.v
+# XDC_FILES = fpga.xdc
+# XCI_FILES = ip/pcspma.xci
+# include ../common/vivado.mk
+# 
+###################################################################
+
+# phony targets
+.PHONY: fpga vivado tmpclean clean distclean
+
+# prevent make from deleting intermediate files and reports
+.PRECIOUS: %.xpr %.bit %.mcs %.prm
+.SECONDARY:
+
+CONFIG ?= config.mk
+-include ../$(CONFIG)
+
+SYN_FILES_REL = $(patsubst %, ../%, $(filter-out /% ./%,$(SYN_FILES))) $(filter /% ./%,$(SYN_FILES))
+INC_FILES_REL = $(patsubst %, ../%, $(filter-out /% ./%,$(INC_FILES))) $(filter /% ./%,$(INC_FILES))
+XCI_FILES_REL = $(patsubst %, ../%, $(filter-out /% ./%,$(XCI_FILES))) $(filter /% ./%,$(XCI_FILES))
+IP_TCL_FILES_REL = $(patsubst %, ../%, $(filter-out /% ./%,$(IP_TCL_FILES))) $(filter /% ./%,$(IP_TCL_FILES))
+CONFIG_TCL_FILES_REL = $(patsubst %, ../%, $(filter-out /% ./%,$(CONFIG_TCL_FILES))) $(filter /% ./%,$(CONFIG_TCL_FILES))
+
+ifdef XDC_FILES
+  XDC_FILES_REL = $(patsubst %, ../%, $(filter-out /% ./%,$(XDC_FILES))) $(filter /% ./%,$(XDC_FILES))
+else
+  XDC_FILES_REL = $(FPGA_TOP).xdc
+endif
+
+###################################################################
+# Main Targets
+#
+# all: build everything
+# clean: remove output files and project files
+###################################################################
+
+all: fpga
+
+fpga: $(FPGA_TOP).bit
+
+vivado: $(FPGA_TOP).xpr
+	vivado $(FPGA_TOP).xpr
+
+tmpclean::
+	-rm -rf *.log *.jou *.cache *.gen *.hbs *.hw *.ip_user_files *.runs *.xpr *.html *.xml *.sim *.srcs *.str .Xil defines.v
+	-rm -rf create_project.tcl update_config.tcl run_synth.tcl run_impl.tcl generate_bit.tcl
+
+clean:: tmpclean
+	-rm -rf *.bit program.tcl generate_mcs.tcl *.mcs *.prm flash.tcl
+
+distclean:: clean
+	-rm -rf rev
+
+###################################################################
+# Target implementations
+###################################################################
+
+# Vivado project file
+create_project.tcl: Makefile $(XCI_FILES_REL) $(IP_TCL_FILES_REL)
+	rm -rf defines.v
+	touch defines.v
+	for x in $(DEFS); do echo '`define' $$x >> defines.v; done
+	echo "create_project -force -part $(FPGA_PART) $(FPGA_TOP)" > $@
+	echo "add_files -fileset sources_1 defines.v $(SYN_FILES_REL)" >> $@
+	echo "add_files -fileset constrs_1 $(XDC_FILES_REL)" >> $@
+	for x in $(XCI_FILES_REL); do echo "import_ip $$x" >> $@; done
+	for x in $(IP_TCL_FILES_REL); do echo "source $$x" >> $@; done
+	for x in $(CONFIG_TCL_FILES_REL); do echo "source $$x" >> $@; done
+
+update_config.tcl: $(CONFIG_TCL_FILES_REL)
+	echo "open_project -quiet $(FPGA_TOP).xpr" > $@
+	for x in $(CONFIG_TCL_FILES_REL); do echo "source $$x" >> $@; done
+
+$(FPGA_TOP).xpr: create_project.tcl update_config.tcl
+	vivado -nojournal -nolog -mode batch $(foreach x,$?,-source $x)
+
+# synthesis run
+%.runs/synth_1/%.dcp: %.xpr $(SYN_FILES_REL) $(INC_FILES_REL) $(XDC_FILES_REL) $(CONFIG_TCL_FILES_REL)
+	echo "open_project $*.xpr" > run_synth.tcl
+	echo "reset_run synth_1" >> run_synth.tcl
+	echo "launch_runs -jobs 4 synth_1" >> run_synth.tcl
+	echo "wait_on_run synth_1" >> run_synth.tcl
+	vivado -nojournal -nolog -mode batch -source run_synth.tcl
+
+# implementation run
+%.runs/impl_1/%_routed.dcp: %.runs/synth_1/%.dcp
+	echo "open_project $*.xpr" > run_impl.tcl
+	echo "reset_run impl_1" >> run_impl.tcl
+	echo "launch_runs -jobs 4 impl_1" >> run_impl.tcl
+	echo "wait_on_run impl_1" >> run_impl.tcl
+	vivado -nojournal -nolog -mode batch -source run_impl.tcl
+
+# bit file
+%.bit: %.runs/impl_1/%_routed.dcp
+	echo "open_project $*.xpr" > generate_bit.tcl
+	echo "open_run impl_1" >> generate_bit.tcl
+	echo "write_bitstream -force $*.bit" >> generate_bit.tcl
+	vivado -nojournal -nolog -mode batch -source generate_bit.tcl
+	mkdir -p rev
+	EXT=bit; COUNT=100; \
+	while [ -e rev/$*_rev$$COUNT.$$EXT ]; \
+	do COUNT=$$((COUNT+1)); done; \
+	cp $@ rev/$*_rev$$COUNT.$$EXT; \
+	echo "Output: rev/$*_rev$$COUNT.$$EXT";

snapshots/alexforencich_verilog-pcie_pr20/example/ExaNIC_X25/fpga/fpga.xdc

@@ -0,0 +1,187 @@
+# XDC constraints for the ExaNIC X25
+# part: xcku3p-ffvb676-2-e
+
+# General configuration
+set_property CFGBVS GND                                      [current_design]
+set_property CONFIG_VOLTAGE 1.8                              [current_design]
+set_property BITSTREAM.GENERAL.COMPRESS true                 [current_design]
+set_property BITSTREAM.CONFIG.UNUSEDPIN Pullup               [current_design]
+set_property BITSTREAM.CONFIG.CONFIGRATE 31.9                [current_design]
+set_property BITSTREAM.CONFIG.BPI_PAGE_SIZE 8                [current_design]
+set_property BITSTREAM.CONFIG.BPI_1ST_READ_CYCLE 4           [current_design]
+set_property CONFIG_MODE BPI16                               [current_design]
+set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN Enable        [current_design]
+
+# 10 MHz TXCO
+#set_property -dict {LOC D14  IOSTANDARD LVCMOS33} [get_ports clk_10mhz]
+#create_clock -period 100 -name clk_100mhz [get_ports clk_10mhz]
+
+# LEDs
+set_property -dict {LOC J12 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports {sfp_1_led[0]}]
+set_property -dict {LOC H12 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports {sfp_1_led[1]}]
+set_property -dict {LOC J13 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports {sfp_2_led[0]}]
+set_property -dict {LOC H13 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports {sfp_2_led[1]}]
+set_property -dict {LOC J14 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports {sma_led[0]}]
+set_property -dict {LOC G12 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports {sma_led[1]}]
+
+set_false_path -to [get_ports {sfp_1_led[*] sfp_2_led[*] sma_led[*]}]
+set_output_delay 0 [get_ports {sfp_1_led[*] sfp_2_led[*] sma_led[*]}]
+
+# GPIO
+#set_property -dict {LOC F9   IOSTANDARD LVCMOS18} [get_ports gpio[0]]
+#set_property -dict {LOC F10  IOSTANDARD LVCMOS18} [get_ports gpio[1]]
+#set_property -dict {LOC G9   IOSTANDARD LVCMOS18} [get_ports gpio[2]]
+#set_property -dict {LOC G10  IOSTANDARD LVCMOS18} [get_ports gpio[3]]
+
+# SMA
+#set_property -dict {LOC A14  IOSTANDARD LVCMOS33} [get_ports sma_in]
+#set_property -dict {LOC A12  IOSTANDARD LVCMOS33 SLEW FAST DRIVE 12} [get_ports sma_out]
+#set_property -dict {LOC A13  IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports sma_out_en]
+#set_property -dict {LOC B12  IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports sma_term_en]
+
+#set_false_path -to [get_ports {sma_out sma_term sma_term_en}]
+#set_output_delay 0 [get_ports {sma_out sma_term sma_term_en}]
+#set_false_path -from [get_ports {sma_in}]
+#set_input_delay 0 [get_ports {sma_in}]
+
+# Config
+#set_property -dict {LOC C14  IOSTANDARD LVCMOS33} [get_ports ddr_npres]
+
+# SFP28 Interfaces
+#set_property -dict {LOC D2  } [get_ports sfp_1_rx_p] ;# MGTYRXP0_227 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3
+#set_property -dict {LOC D1  } [get_ports sfp_1_rx_n] ;# MGTYRXN0_227 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3
+#set_property -dict {LOC A4  } [get_ports sfp_2_rx_p] ;# MGTYRXP3_227 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3
+#set_property -dict {LOC A3  } [get_ports sfp_2_rx_n] ;# MGTYRXN3_227 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3
+#set_property -dict {LOC F7  } [get_ports sfp_1_tx_p] ;# MGTYTXP0_227 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3
+#set_property -dict {LOC F6  } [get_ports sfp_1_tx_n] ;# MGTYTXN0_227 GTYE4_CHANNEL_X0Y12 / GTYE4_COMMON_X0Y3
+#set_property -dict {LOC B7  } [get_ports sfp_2_tx_p] ;# MGTYTXP3_227 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3
+#set_property -dict {LOC B6  } [get_ports sfp_2_tx_n] ;# MGTYTXN3_227 GTYE4_CHANNEL_X0Y15 / GTYE4_COMMON_X0Y3
+#set_property -dict {LOC K7  } [get_ports sfp_mgt_refclk_p] ;# MGTREFCLK0P_227 from X2
+#set_property -dict {LOC K6  } [get_ports sfp_mgt_refclk_n] ;# MGTREFCLK0N_227 from X2
+#set_property -dict {LOC AC17 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports sfp_1_tx_disable]
+#set_property -dict {LOC AA17 IOSTANDARD LVCMOS18 SLEW SLOW DRIVE 12} [get_ports sfp_2_tx_disable]
+#set_property -dict {LOC F12  IOSTANDARD LVCMOS33 PULLUP true} [get_ports sfp_1_npres]
+#set_property -dict {LOC F14  IOSTANDARD LVCMOS33 PULLUP true} [get_ports sfp_2_npres]
+#set_property -dict {LOC AC16 IOSTANDARD LVCMOS18 PULLUP true} [get_ports sfp_1_los]
+#set_property -dict {LOC Y17  IOSTANDARD LVCMOS18 PULLUP true} [get_ports sfp_2_los]
+#set_property -dict {LOC G14  IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports sfp_1_rs]
+#set_property -dict {LOC H14  IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12} [get_ports sfp_2_rs]
+#set_property -dict {LOC A10  IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12 PULLUP true} [get_ports sfp_i2c_scl]
+#set_property -dict {LOC C11  IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12 PULLUP true} [get_ports sfp_1_i2c_sda]
+#set_property -dict {LOC B11  IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12 PULLUP true} [get_ports sfp_2_i2c_sda]
+
+# 161.1328125 MHz MGT reference clock
+#create_clock -period 6.206 -name sfp_mgt_refclk [get_ports sfp_mgt_refclk_p]
+
+#set_false_path -to [get_ports {sfp_1_tx_disable sfp_2_tx_disable sfp_1_rs sfp_2_rs}]
+#set_output_delay 0 [get_ports {sfp_1_tx_disable sfp_2_tx_disable sfp_1_rs sfp_2_rs}]
+#set_false_path -from [get_ports {sfp_1_npres sfp_2_npres sfp_1_los sfp_2_los}]
+#set_input_delay 0 [get_ports {sfp_1_npres sfp_2_npres sfp_1_los sfp_2_los}]
+
+#set_false_path -to [get_ports {sfp_1_i2c_sda sfp_2_i2c_sda sfp_i2c_scl}]
+#set_output_delay 0 [get_ports {sfp_1_i2c_sda sfp_2_i2c_sda sfp_i2c_scl}]
+#set_false_path -from [get_ports {sfp_1_i2c_sda sfp_2_i2c_sda sfp_i2c_scl}]
+#set_input_delay 0 [get_ports {sfp_1_i2c_sda sfp_2_i2c_sda sfp_i2c_scl}]
+
+# I2C interface
+#set_property -dict {LOC B9 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12 PULLUP true} [get_ports eeprom_i2c_scl]
+#set_property -dict {LOC A9 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 12 PULLUP true} [get_ports eeprom_i2c_sda]
+
+#set_false_path -to [get_ports {eeprom_i2c_sda eeprom_i2c_scl}]
+#set_output_delay 0 [get_ports {eeprom_i2c_sda eeprom_i2c_scl}]
+#set_false_path -from [get_ports {eeprom_i2c_sda eeprom_i2c_scl}]
+#set_input_delay 0 [get_ports {eeprom_i2c_sda eeprom_i2c_scl}]
+
+# PCIe Interface
+set_property -dict {LOC P2  } [get_ports {pcie_rx_p[0]}] ;# MGTYRXP3_225 GTYE4_CHANNEL_X0Y7 / GTYE4_COMMON_X0Y1
+set_property -dict {LOC P1  } [get_ports {pcie_rx_n[0]}] ;# MGTYRXN3_225 GTYE4_CHANNEL_X0Y7 / GTYE4_COMMON_X0Y1
+set_property -dict {LOC R5  } [get_ports {pcie_tx_p[0]}] ;# MGTYTXP3_225 GTYE4_CHANNEL_X0Y7 / GTYE4_COMMON_X0Y1
+set_property -dict {LOC R4  } [get_ports {pcie_tx_n[0]}] ;# MGTYTXN3_225 GTYE4_CHANNEL_X0Y7 / GTYE4_COMMON_X0Y1
+set_property -dict {LOC T2  } [get_ports {pcie_rx_p[1]}] ;# MGTYRXP2_225 GTYE4_CHANNEL_X0Y6 / GTYE4_COMMON_X0Y1
+set_property -dict {LOC T1  } [get_ports {pcie_rx_n[1]}] ;# MGTYRXN2_225 GTYE4_CHANNEL_X0Y6 / GTYE4_COMMON_X0Y1
+set_property -dict {LOC U5  } [get_ports {pcie_tx_p[1]}] ;# MGTYTXP2_225 GTYE4_CHANNEL_X0Y6 / GTYE4_COMMON_X0Y1
+set_property -dict {LOC U4  } [get_ports {pcie_tx_n[1]}] ;# MGTYTXN2_225 GTYE4_CHANNEL_X0Y6 / GTYE4_COMMON_X0Y1
+set_property -dict {LOC V2  } [get_ports {pcie_rx_p[2]}] ;# MGTYRXP1_225 GTYE4_CHANNEL_X0Y5 / GTYE4_COMMON_X0Y1
+set_property -dict {LOC V1  } [get_ports {pcie_rx_n[2]}] ;# MGTYRXN1_225 GTYE4_CHANNEL_X0Y5 / GTYE4_COMMON_X0Y1
+set_property -dict {LOC W5  } [get_ports {pcie_tx_p[2]}] ;# MGTYTXP1_225 GTYE4_CHANNEL_X0Y5 / GTYE4_COMMON_X0Y1
+set_property -dict {LOC W4  } [get_ports {pcie_tx_n[2]}] ;# MGTYTXN1_225 GTYE4_CHANNEL_X0Y5 / GTYE4_COMMON_X0Y1
+set_property -dict {LOC Y2  } [get_ports {pcie_rx_p[3]}] ;# MGTYRXP0_225 GTYE4_CHANNEL_X0Y4 / GTYE4_COMMON_X0Y1
+set_property -dict {LOC Y1  } [get_ports {pcie_rx_n[3]}] ;# MGTYRXN0_225 GTYE4_CHANNEL_X0Y4 / GTYE4_COMMON_X0Y1
+set_property -dict {LOC AA5 } [get_ports {pcie_tx_p[3]}] ;# MGTYTXP0_225 GTYE4_CHANNEL_X0Y4 / GTYE4_COMMON_X0Y1
+set_property -dict {LOC AA4 } [get_ports {pcie_tx_n[3]}] ;# MGTYTXN0_225 GTYE4_CHANNEL_X0Y4 / GTYE4_COMMON_X0Y1
+set_property -dict {LOC AB2 } [get_ports {pcie_rx_p[4]}] ;# MGTYRXP3_224 GTYE4_CHANNEL_X0Y3 / GTYE4_COMMON_X0Y0
+set_property -dict {LOC AB1 } [get_ports {pcie_rx_n[4]}] ;# MGTYRXN3_224 GTYE4_CHANNEL_X0Y3 / GTYE4_COMMON_X0Y0
+set_property -dict {LOC AC5 } [get_ports {pcie_tx_p[4]}] ;# MGTYTXP3_224 GTYE4_CHANNEL_X0Y3 / GTYE4_COMMON_X0Y0
+set_property -dict {LOC AC4 } [get_ports {pcie_tx_n[4]}] ;# MGTYTXN3_224 GTYE4_CHANNEL_X0Y3 / GTYE4_COMMON_X0Y0
+set_property -dict {LOC AD2 } [get_ports {pcie_rx_p[5]}] ;# MGTYRXP2_224 GTYE4_CHANNEL_X0Y2 / GTYE4_COMMON_X0Y0
+set_property -dict {LOC AD1 } [get_ports {pcie_rx_n[5]}] ;# MGTYRXN2_224 GTYE4_CHANNEL_X0Y2 / GTYE4_COMMON_X0Y0
+set_property -dict {LOC AD7 } [get_ports {pcie_tx_p[5]}] ;# MGTYTXP2_224 GTYE4_CHANNEL_X0Y2 / GTYE4_COMMON_X0Y0
+set_property -dict {LOC AD6 } [get_ports {pcie_tx_n[5]}] ;# MGTYTXN2_224 GTYE4_CHANNEL_X0Y2 / GTYE4_COMMON_X0Y0
+set_property -dict {LOC AE4 } [get_ports {pcie_rx_p[6]}] ;# MGTYRXP1_224 GTYE4_CHANNEL_X0Y1 / GTYE4_COMMON_X0Y0
+set_property -dict {LOC AE3 } [get_ports {pcie_rx_n[6]}] ;# MGTYRXN1_224 GTYE4_CHANNEL_X0Y1 / GTYE4_COMMON_X0Y0
+set_property -dict {LOC AE9 } [get_ports {pcie_tx_p[6]}] ;# MGTYTXP1_224 GTYE4_CHANNEL_X0Y1 / GTYE4_COMMON_X0Y0
+set_property -dict {LOC AE8 } [get_ports {pcie_tx_n[6]}] ;# MGTYTXN1_224 GTYE4_CHANNEL_X0Y1 / GTYE4_COMMON_X0Y0
+set_property -dict {LOC AF2 } [get_ports {pcie_rx_p[7]}] ;# MGTYRXP0_224 GTYE4_CHANNEL_X0Y0 / GTYE4_COMMON_X0Y0
+set_property -dict {LOC AF1 } [get_ports {pcie_rx_n[7]}] ;# MGTYRXN0_224 GTYE4_CHANNEL_X0Y0 / GTYE4_COMMON_X0Y0
+set_property -dict {LOC AF7 } [get_ports {pcie_tx_p[7]}] ;# MGTYTXP0_224 GTYE4_CHANNEL_X0Y0 / GTYE4_COMMON_X0Y0
+set_property -dict {LOC AF6 } [get_ports {pcie_tx_n[7]}] ;# MGTYTXN0_224 GTYE4_CHANNEL_X0Y0 / GTYE4_COMMON_X0Y0
+set_property -dict {LOC V7  } [get_ports pcie_refclk_p] ;# MGTREFCLK0P_225
+set_property -dict {LOC V6  } [get_ports pcie_refclk_n] ;# MGTREFCLK0N_225
+set_property -dict {LOC T19 IOSTANDARD LVCMOS18 PULLUP true} [get_ports pcie_reset_n]
+
+set_false_path -from [get_ports {pcie_reset_n}]
+set_input_delay 0 [get_ports {pcie_reset_n}]
+
+# 100 MHz MGT reference clock
+create_clock -period 10 -name pcie_mgt_refclk [get_ports pcie_refclk_p]
+
+# BPI flash
+#set_property -dict {LOC AF20 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[0]}]
+#set_property -dict {LOC AE18 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[1]}]
+#set_property -dict {LOC AF19 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[2]}]
+#set_property -dict {LOC AF17 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[3]}]
+#set_property -dict {LOC AB19 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[4]}]
+#set_property -dict {LOC AD19 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[5]}]
+#set_property -dict {LOC AB17 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[6]}]
+#set_property -dict {LOC AE17 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[7]}]
+#set_property -dict {LOC AD16 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[8]}]
+#set_property -dict {LOC AE16 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[9]}]
+#set_property -dict {LOC AD18 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[10]}]
+#set_property -dict {LOC AC21 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[11]}]
+#set_property -dict {LOC AE22 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[12]}]
+#set_property -dict {LOC AF22 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[13]}]
+#set_property -dict {LOC AF25 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[14]}]
+#set_property -dict {LOC AF24 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_dq[15]}]
+#set_property -dict {LOC AE20 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[0]}]
+#set_property -dict {LOC AE26 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[1]}]
+#set_property -dict {LOC AD24 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[2]}]
+#set_property -dict {LOC AC23 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[3]}]
+#set_property -dict {LOC AE23 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[4]}]
+#set_property -dict {LOC AD20 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[5]}]
+#set_property -dict {LOC AC24 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[6]}]
+#set_property -dict {LOC AC22 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[7]}]
+#set_property -dict {LOC AD23 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[8]}]
+#set_property -dict {LOC AD21 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[9]}]
+#set_property -dict {LOC AB22 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[10]}]
+#set_property -dict {LOC AA22 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[11]}]
+#set_property -dict {LOC AE25 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[12]}]
+#set_property -dict {LOC AD26 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[13]}]
+#set_property -dict {LOC AB25 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[14]}]
+#set_property -dict {LOC AB26 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[15]}]
+#set_property -dict {LOC AD25 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[16]}]
+#set_property -dict {LOC AC26 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[17]}]
+#set_property -dict {LOC AB21 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[18]}]
+#set_property -dict {LOC AB24 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[19]}]
+#set_property -dict {LOC Y18  IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[20]}]
+#set_property -dict {LOC AA20 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[21]}]
+#set_property -dict {LOC AC19 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_addr[22]}]
+#set_property -dict {LOC Y20  IOSTANDARD LVCMOS18 PULLUP true} [get_ports {flash_region}]
+#set_property -dict {LOC AF18 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_ce_n}]
+#set_property -dict {LOC Y21  IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_oe_n}]
+#set_property -dict {LOC AB20 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_we_n}]
+#set_property -dict {LOC AF23 IOSTANDARD LVCMOS18 DRIVE 12} [get_ports {flash_adv_n}]
+
+#set_false_path -to [get_ports {flash_dq[*] flash_addr[*] flash_region flash_ce_n flash_oe_n flash_we_n flash_adv_n}]
+#set_output_delay 0 [get_ports {flash_dq[*] flash_addr[*] flash_region flash_ce_n flash_oe_n flash_we_n flash_adv_n}]
+#set_false_path -from [get_ports {flash_dq[*]}]
+#set_input_delay 0 [get_ports {flash_dq[*]}]

snapshots/alexforencich_verilog-pcie_pr20/example/ExaNIC_X25/fpga/fpga/Makefile

@@ -0,0 +1,95 @@
+
+# FPGA settings
+FPGA_PART = xcku3p-ffvb676-2-e
+FPGA_TOP = fpga
+FPGA_ARCH = kintexuplus
+
+# Files for synthesis
+SYN_FILES = rtl/fpga.v
+SYN_FILES += rtl/fpga_core.v
+SYN_FILES += rtl/debounce_switch.v
+SYN_FILES += rtl/sync_reset.v
+SYN_FILES += rtl/sync_signal.v
+SYN_FILES += rtl/common/example_core_pcie_us.v
+SYN_FILES += rtl/common/example_core_pcie.v
+SYN_FILES += rtl/common/example_core.v
+SYN_FILES += rtl/common/axi_ram.v
+SYN_FILES += lib/pcie/rtl/pcie_us_if.v
+SYN_FILES += lib/pcie/rtl/pcie_us_if_rc.v
+SYN_FILES += lib/pcie/rtl/pcie_us_if_rq.v
+SYN_FILES += lib/pcie/rtl/pcie_us_if_cq.v
+SYN_FILES += lib/pcie/rtl/pcie_us_if_cc.v
+SYN_FILES += lib/pcie/rtl/pcie_us_cfg.v
+SYN_FILES += lib/pcie/rtl/pcie_us_msi.v
+SYN_FILES += lib/pcie/rtl/pcie_axil_master.v
+SYN_FILES += lib/pcie/rtl/pcie_axi_master.v
+SYN_FILES += lib/pcie/rtl/pcie_axi_master_rd.v
+SYN_FILES += lib/pcie/rtl/pcie_axi_master_wr.v
+SYN_FILES += lib/pcie/rtl/pcie_tlp_demux_bar.v
+SYN_FILES += lib/pcie/rtl/pcie_tlp_demux.v
+SYN_FILES += lib/pcie/rtl/pcie_tlp_mux.v
+SYN_FILES += lib/pcie/rtl/dma_if_pcie.v
+SYN_FILES += lib/pcie/rtl/dma_if_pcie_rd.v
+SYN_FILES += lib/pcie/rtl/dma_if_pcie_wr.v
+SYN_FILES += lib/pcie/rtl/dma_psdpram.v
+SYN_FILES += lib/pcie/rtl/arbiter.v
+SYN_FILES += lib/pcie/rtl/priority_encoder.v
+SYN_FILES += lib/pcie/rtl/pulse_merge.v
+
+# XDC files
+XDC_FILES = fpga.xdc
+
+# IP
+IP_TCL_FILES = ip/pcie4_uscale_plus_0.tcl
+
+include ../common/vivado.mk
+
+program: $(FPGA_TOP).bit
+	echo "open_hw" > program.tcl
+	echo "connect_hw_server" >> program.tcl
+	echo "open_hw_target" >> program.tcl
+	echo "current_hw_device [lindex [get_hw_devices] 0]" >> program.tcl
+	echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> program.tcl
+	echo "set_property PROGRAM.FILE {$(FPGA_TOP).bit} [current_hw_device]" >> program.tcl
+	echo "program_hw_devices [current_hw_device]" >> program.tcl
+	echo "exit" >> program.tcl
+	vivado -nojournal -nolog -mode batch -source program.tcl
+
+%.mcs %.prm: %.bit
+	echo "write_cfgmem -force -format mcs -size 32 -interface BPIx16 -loadbit {up 0x00800000 $*.bit} -checksum -file $*.mcs" > generate_mcs.tcl
+	echo "exit" >> generate_mcs.tcl
+	vivado -nojournal -nolog -mode batch -source generate_mcs.tcl
+	mkdir -p rev
+	COUNT=100; \
+	while [ -e rev/$*_rev$$COUNT.bit ]; \
+	do COUNT=$$((COUNT+1)); done; \
+	COUNT=$$((COUNT-1)); \
+	for x in .mcs .prm; \
+	do cp $*$$x rev/$*_rev$$COUNT$$x; \
+	echo "Output: rev/$*_rev$$COUNT$$x"; done;
+
+flash: $(FPGA_TOP).mcs $(FPGA_TOP).prm
+	echo "open_hw" > flash.tcl
+	echo "connect_hw_server" >> flash.tcl
+	echo "open_hw_target" >> flash.tcl
+	echo "current_hw_device [lindex [get_hw_devices] 0]" >> flash.tcl
+	echo "refresh_hw_device -update_hw_probes false [current_hw_device]" >> flash.tcl
+	echo "create_hw_cfgmem -hw_device [current_hw_device] [lindex [get_cfgmem_parts {s29gl256p-bpi-x16}] 0]" >> flash.tcl
+	echo "current_hw_cfgmem -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM [current_hw_device]]" >> flash.tcl
+	echo "set_property PROGRAM.FILES [list \"$(FPGA_TOP).mcs\"] [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.PRM_FILES [list \"$(FPGA_TOP).prm\"] [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.ERASE 1 [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.ADDRESS_RANGE {use_file} [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.BPI_RS_PINS {24:23} [current_hw_cfgmem]" >> flash.tcl
+	echo "set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [current_hw_cfgmem]" >> flash.tcl
+	echo "create_hw_bitstream -hw_device [current_hw_device] [get_property PROGRAM.HW_CFGMEM_BITFILE [current_hw_device]]" >> flash.tcl
+	echo "program_hw_devices [current_hw_device]" >> flash.tcl
+	echo "refresh_hw_device [current_hw_device]" >> flash.tcl
+	echo "program_hw_cfgmem -hw_cfgmem [current_hw_cfgmem]" >> flash.tcl
+	echo "boot_hw_device [current_hw_device]" >> flash.tcl
+	echo "exit" >> flash.tcl
+	vivado -nojournal -nolog -mode batch -source flash.tcl
+