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testbench/bespoke-silicon-group_basejump_stl_pr739/open_tool_p2p_buggy.log

@@ -0,0 +1,47 @@
+INFO: open-tool P2P fallback (buggy)
+INFO: native simulation P2P not applicable for this case
+
+### native_multifile_compile:basejump_config_net_surelog
+'surelog' '-sv' '-parse' '-nocomp' '-DTILE_MAX_X=1' '-DTILE_MAX_Y=1' '-Itestbench/bespoke-silicon-group_basejump_stl_pr739/snapshot_scratch/bsg_misc' '-Itestbench/bespoke-silicon-group_basejump_stl_pr739/snapshot_scratch/bsg_legacy/bsg_tag/config_net/src' '-Itestbench/bespoke-silicon-group_basejump_stl_pr739/snapshot_scratch/bsg_legacy/bsg_tag/config_net/sim' '-Itestbench/bespoke-silicon-group_basejump_stl_pr739/snapshot_scratch/bsg_legacy/bsg_tag/config_net/tests/cfgtaggw_test' 'testbench/bespoke-silicon-group_basejump_stl_pr739/snapshot_scratch/bsg_legacy/bsg_tag/config_net/src/cfgtaggw.v' 'testbench/bespoke-silicon-group_basejump_stl_pr739/snapshot_scratch/bsg_legacy/bsg_tag/config_net/src/config_defs.v' 'testbench/bespoke-silicon-group_basejump_stl_pr739/snapshot_scratch/bsg_legacy/bsg_tag/config_net/src/config_node.v' 'testbench/bespoke-silicon-group_basejump_stl_pr739/snapshot_scratch/bsg_legacy/bsg_tag/config_net/src/config_snooper.v' 'testbench/bespoke-silicon-group_basejump_stl_pr739/snapshot_scratch/bsg_legacy/bsg_tag/config_net/src/config_utils.v' 'testbench/bespoke-silicon-group_basejump_stl_pr739/snapshot_scratch/bsg_legacy/bsg_tag/config_net/src/rNandMeta.v' 'testbench/bespoke-silicon-group_basejump_stl_pr739/snapshot_scratch/bsg_legacy/bsg_tag/config_net/src/relay_node.v' 'testbench/bespoke-silicon-group_basejump_stl_pr739/snapshot_scratch/bsg_legacy/bsg_tag/config_net/sim/config_file_setter.v' 'testbench/bespoke-silicon-group_basejump_stl_pr739/snapshot_scratch/bsg_legacy/bsg_tag/config_net/sim/config_node_bind.v' 'testbench/bespoke-silicon-group_basejump_stl_pr739/snapshot_scratch/bsg_legacy/bsg_tag/config_net/sim/config_setter.v' 'testbench/bespoke-silicon-group_basejump_stl_pr739/snapshot_scratch/bsg_legacy/bsg_tag/config_net/sim/config_snooper_bind.v' 'testbench/bespoke-silicon-group_basejump_stl_pr739/snapshot_scratch/bsg_legacy/bsg_tag/config_net/sim/send_config_tag.v' 'testbench/bespoke-silicon-group_basejump_stl_pr739/snapshot_scratch/bsg_legacy/bsg_tag/config_net/tests/cfgtaggw_test/cfg_tag_tb.v' 'testbench/bespoke-silicon-group_basejump_stl_pr739/snapshot_scratch/bsg_legacy/bsg_tag/config_net/tests/cfgtaggw_test/cfgtag.v' 'testbench/bespoke-silicon-group_basejump_stl_pr739/snapshot_scratch/bsg_legacy/bsg_tag/config_net/tests/cfgtaggw_test/config_defs.v' '-odir' 'testbench/bespoke-silicon-group_basejump_stl_pr739/open_tool_buggy_basejump_config_net_surelog'
+[INF:CM0023] Creating log file "testbench/bespoke-silicon-group_basejump_stl_pr739/open_tool_buggy_basejump_config_net_surelog/slpp_all/surelog.log".
+
+[WRN:PP0113] testbench/bespoke-silicon-group_basejump_stl_pr739/snapshot_scratch/bsg_misc/bsg_defines.sv:70:9: Unused macro argument "val".
+
+[WRN:PP0113] testbench/bespoke-silicon-group_basejump_stl_pr739/snapshot_scratch/bsg_misc/bsg_defines.sv:78:9: Unused macro argument "val".
+
+[WRN:PP0113] testbench/bespoke-silicon-group_basejump_stl_pr739/snapshot_scratch/bsg_misc/bsg_defines.sv:86:9: Unused macro argument "val".
+
+[WRN:PP0113] testbench/bespoke-silicon-group_basejump_stl_pr739/snapshot_scratch/bsg_misc/bsg_defines.sv:153:9: Unused macro argument "x".
+
+[WRN:PA0205] testbench/bespoke-silicon-group_basejump_stl_pr739/snapshot_scratch/bsg_legacy/bsg_tag/config_net/src/cfgtaggw.v:10:1: No timescale set for "cfgtaggw".
+
+[WRN:PA0205] testbench/bespoke-silicon-group_basejump_stl_pr739/snapshot_scratch/bsg_legacy/bsg_tag/config_net/src/config_node.v:8:1: No timescale set for "config_node".
+
+[WRN:PA0205] testbench/bespoke-silicon-group_basejump_stl_pr739/snapshot_scratch/bsg_legacy/bsg_tag/config_net/src/config_snooper.v:5:1: No timescale set for "config_snooper".
+
+[WRN:PA0205] testbench/bespoke-silicon-group_basejump_stl_pr739/snapshot_scratch/bsg_legacy/bsg_tag/config_net/src/rNandMeta.v:4:1: No timescale set for "rNandMeta".
+
+[WRN:PA0205] testbench/bespoke-silicon-group_basejump_stl_pr739/snapshot_scratch/bsg_misc/bsg_defines.sv:29:5: No timescale set for "rNandMeta__abstract".
+
+[WRN:PA0205] testbench/bespoke-silicon-group_basejump_stl_pr739/snapshot_scratch/bsg_legacy/bsg_tag/config_net/src/relay_node.v:5:1: No timescale set for "relay_node".
+
+[WRN:PA0205] testbench/bespoke-silicon-group_basejump_stl_pr739/snapshot_scratch/bsg_legacy/bsg_tag/config_net/sim/config_file_setter.v:13:1: No timescale set for "config_file_setter".
+
+[WRN:PA0205] testbench/bespoke-silicon-group_basejump_stl_pr739/snapshot_scratch/bsg_legacy/bsg_tag/config_net/sim/config_node_bind.v:5:1: No timescale set for "config_node_bind".
+
+[WRN:PA0205] testbench/bespoke-silicon-group_basejump_stl_pr739/snapshot_scratch/bsg_legacy/bsg_tag/config_net/sim/config_setter.v:5:1: No timescale set for "config_setter".
+
+[WRN:PA0205] testbench/bespoke-silicon-group_basejump_stl_pr739/snapshot_scratch/bsg_legacy/bsg_tag/config_net/sim/config_snooper_bind.v:5:1: No timescale set for "config_snooper_bind".
+
+[WRN:PA0205] testbench/bespoke-silicon-group_basejump_stl_pr739/snapshot_scratch/bsg_legacy/bsg_tag/config_net/tests/cfgtaggw_test/cfg_tag_tb.v:7:1: No timescale set for "cfg_tag_tb".
+
+[WRN:PA0205] testbench/bespoke-silicon-group_basejump_stl_pr739/snapshot_scratch/bsg_legacy/bsg_tag/config_net/tests/cfgtaggw_test/cfgtag.v:5:1: No timescale set for "cfgtag".
+
+[  FATAL] : 0
+[ SYNTAX] : 0
+[  ERROR] : 0
+[WARNING] : 16
+[   NOTE] : 0
+
+rc=0
+PASS: native multi-file compile P2P passed in buggy phase: basejump_config_net_surelog; files=15

testbench/bespoke-silicon-group_basejump_stl_pr739/open_tool_p2p_fixed.log

@@ -0,0 +1,47 @@
+INFO: open-tool P2P fallback (fixed)
+INFO: native simulation P2P not applicable for this case
+
+### native_multifile_compile:basejump_config_net_surelog
+'surelog' '-sv' '-parse' '-nocomp' '-DTILE_MAX_X=1' '-DTILE_MAX_Y=1' '-Itestbench/bespoke-silicon-group_basejump_stl_pr739/snapshot_scratch/bsg_misc' '-Itestbench/bespoke-silicon-group_basejump_stl_pr739/snapshot_scratch/bsg_legacy/bsg_tag/config_net/src' '-Itestbench/bespoke-silicon-group_basejump_stl_pr739/snapshot_scratch/bsg_legacy/bsg_tag/config_net/sim' '-Itestbench/bespoke-silicon-group_basejump_stl_pr739/snapshot_scratch/bsg_legacy/bsg_tag/config_net/tests/cfgtaggw_test' 'testbench/bespoke-silicon-group_basejump_stl_pr739/snapshot_scratch/bsg_legacy/bsg_tag/config_net/src/cfgtaggw.v' 'testbench/bespoke-silicon-group_basejump_stl_pr739/snapshot_scratch/bsg_legacy/bsg_tag/config_net/src/config_defs.v' 'testbench/bespoke-silicon-group_basejump_stl_pr739/snapshot_scratch/bsg_legacy/bsg_tag/config_net/src/config_node.v' 'testbench/bespoke-silicon-group_basejump_stl_pr739/snapshot_scratch/bsg_legacy/bsg_tag/config_net/src/config_snooper.v' 'testbench/bespoke-silicon-group_basejump_stl_pr739/snapshot_scratch/bsg_legacy/bsg_tag/config_net/src/config_utils.v' 'testbench/bespoke-silicon-group_basejump_stl_pr739/snapshot_scratch/bsg_legacy/bsg_tag/config_net/src/rNandMeta.v' 'testbench/bespoke-silicon-group_basejump_stl_pr739/snapshot_scratch/bsg_legacy/bsg_tag/config_net/src/relay_node.v' 'testbench/bespoke-silicon-group_basejump_stl_pr739/snapshot_scratch/bsg_legacy/bsg_tag/config_net/sim/config_file_setter.v' 'testbench/bespoke-silicon-group_basejump_stl_pr739/snapshot_scratch/bsg_legacy/bsg_tag/config_net/sim/config_node_bind.v' 'testbench/bespoke-silicon-group_basejump_stl_pr739/snapshot_scratch/bsg_legacy/bsg_tag/config_net/sim/config_setter.v' 'testbench/bespoke-silicon-group_basejump_stl_pr739/snapshot_scratch/bsg_legacy/bsg_tag/config_net/sim/config_snooper_bind.v' 'testbench/bespoke-silicon-group_basejump_stl_pr739/snapshot_scratch/bsg_legacy/bsg_tag/config_net/sim/send_config_tag.v' 'testbench/bespoke-silicon-group_basejump_stl_pr739/snapshot_scratch/bsg_legacy/bsg_tag/config_net/tests/cfgtaggw_test/cfg_tag_tb.v' 'testbench/bespoke-silicon-group_basejump_stl_pr739/snapshot_scratch/bsg_legacy/bsg_tag/config_net/tests/cfgtaggw_test/cfgtag.v' 'testbench/bespoke-silicon-group_basejump_stl_pr739/snapshot_scratch/bsg_legacy/bsg_tag/config_net/tests/cfgtaggw_test/config_defs.v' '-odir' 'testbench/bespoke-silicon-group_basejump_stl_pr739/open_tool_fixed_basejump_config_net_surelog'
+[INF:CM0023] Creating log file "testbench/bespoke-silicon-group_basejump_stl_pr739/open_tool_fixed_basejump_config_net_surelog/slpp_all/surelog.log".
+
+[WRN:PP0113] testbench/bespoke-silicon-group_basejump_stl_pr739/snapshot_scratch/bsg_misc/bsg_defines.sv:70:9: Unused macro argument "val".
+
+[WRN:PP0113] testbench/bespoke-silicon-group_basejump_stl_pr739/snapshot_scratch/bsg_misc/bsg_defines.sv:78:9: Unused macro argument "val".
+
+[WRN:PP0113] testbench/bespoke-silicon-group_basejump_stl_pr739/snapshot_scratch/bsg_misc/bsg_defines.sv:86:9: Unused macro argument "val".
+
+[WRN:PP0113] testbench/bespoke-silicon-group_basejump_stl_pr739/snapshot_scratch/bsg_misc/bsg_defines.sv:153:9: Unused macro argument "x".
+
+[WRN:PA0205] testbench/bespoke-silicon-group_basejump_stl_pr739/snapshot_scratch/bsg_legacy/bsg_tag/config_net/src/cfgtaggw.v:10:1: No timescale set for "cfgtaggw".
+
+[WRN:PA0205] testbench/bespoke-silicon-group_basejump_stl_pr739/snapshot_scratch/bsg_legacy/bsg_tag/config_net/src/config_node.v:8:1: No timescale set for "config_node".
+
+[WRN:PA0205] testbench/bespoke-silicon-group_basejump_stl_pr739/snapshot_scratch/bsg_legacy/bsg_tag/config_net/src/config_snooper.v:5:1: No timescale set for "config_snooper".
+
+[WRN:PA0205] testbench/bespoke-silicon-group_basejump_stl_pr739/snapshot_scratch/bsg_legacy/bsg_tag/config_net/src/rNandMeta.v:4:1: No timescale set for "rNandMeta".
+
+[WRN:PA0205] testbench/bespoke-silicon-group_basejump_stl_pr739/snapshot_scratch/bsg_misc/bsg_defines.sv:29:5: No timescale set for "rNandMeta__abstract".
+
+[WRN:PA0205] testbench/bespoke-silicon-group_basejump_stl_pr739/snapshot_scratch/bsg_legacy/bsg_tag/config_net/src/relay_node.v:5:1: No timescale set for "relay_node".
+
+[WRN:PA0205] testbench/bespoke-silicon-group_basejump_stl_pr739/snapshot_scratch/bsg_legacy/bsg_tag/config_net/sim/config_file_setter.v:13:1: No timescale set for "config_file_setter".
+
+[WRN:PA0205] testbench/bespoke-silicon-group_basejump_stl_pr739/snapshot_scratch/bsg_legacy/bsg_tag/config_net/sim/config_node_bind.v:5:1: No timescale set for "config_node_bind".
+
+[WRN:PA0205] testbench/bespoke-silicon-group_basejump_stl_pr739/snapshot_scratch/bsg_legacy/bsg_tag/config_net/sim/config_setter.v:5:1: No timescale set for "config_setter".
+
+[WRN:PA0205] testbench/bespoke-silicon-group_basejump_stl_pr739/snapshot_scratch/bsg_legacy/bsg_tag/config_net/sim/config_snooper_bind.v:5:1: No timescale set for "config_snooper_bind".
+
+[WRN:PA0205] testbench/bespoke-silicon-group_basejump_stl_pr739/snapshot_scratch/bsg_legacy/bsg_tag/config_net/tests/cfgtaggw_test/cfg_tag_tb.v:7:1: No timescale set for "cfg_tag_tb".
+
+[WRN:PA0205] testbench/bespoke-silicon-group_basejump_stl_pr739/snapshot_scratch/bsg_legacy/bsg_tag/config_net/tests/cfgtaggw_test/cfgtag.v:5:1: No timescale set for "cfgtag".
+
+[  FATAL] : 0
+[ SYNTAX] : 0
+[  ERROR] : 0
+[WARNING] : 16
+[   NOTE] : 0
+
+rc=0
+PASS: native multi-file compile P2P passed in fixed phase: basejump_config_net_surelog; files=15

testbench/bespoke-silicon-group_basejump_stl_pr739/repo_native_fixed.log

@@ -0,0 +1 @@
+PASS: repo native multi-file open-tool P2P passed in fixed phase

testbench/bespoke-silicon-group_basejump_stl_pr739/repo_native_source.path

@@ -0,0 +1 @@
+bsg_legacy/bsg_tag/config_net/tests/cfgtaggw_test/config_defs.v

testbench/bespoke-silicon-group_basejump_stl_pr739/run_once.sh

@@ -0,0 +1,4 @@
+#!/bin/bash
+set -u
+HERE="$(cd "$(dirname "${BASH_SOURCE[0]:-$0}")" && pwd)"
+exec python3 "$HERE/../_run_once_from_run_verilator.py" "$HERE/run_verilator.sh"

testbench/bespoke-silicon-group_basejump_stl_pr739/run_verilator.sh

@@ -0,0 +1,32 @@
+#!/bin/bash
+set -u
+HERE="$(cd "$(dirname "${BASH_SOURCE[0]:-$0}")" && pwd)"
+cd "$HERE"
+. "$HERE/../_repo_native_p2p_smoke.sh"
+NAME=bespoke-silicon-group_basejump_stl_pr739
+TOP=tb_bsg_multi_fifo_vector
+REPO_ROOT="$(cd "$HERE/../.." && pwd)"
+SCRATCH="$HERE/snapshot_scratch"
+SOURCES=(
+  "--Wno-fatal"
+  "--Wno-PINCONNECTEMPTY"
+  "+incdir+$SCRATCH/bsg_misc"
+  "+incdir+$SCRATCH/bsg_dataflow"
+  "+incdir+$SCRATCH/bsg_mem"
+  "$SCRATCH/bsg_misc/bsg_decode.sv"
+  "$SCRATCH/bsg_misc/bsg_decode_with_v.sv"
+  "$SCRATCH/bsg_misc/bsg_dff.sv"
+  "$SCRATCH/bsg_misc/bsg_dff_en.sv"
+  "$SCRATCH/bsg_misc/bsg_dff_en_bypass.sv"
+  "$SCRATCH/bsg_misc/bsg_dff_reset_set_clear.sv"
+  "$SCRATCH/bsg_misc/bsg_circular_ptr.sv"
+  "$SCRATCH/bsg_misc/bsg_mux_one_hot.sv"
+  "$SCRATCH/bsg_misc/bsg_clkgate_optional.sv"
+  "$SCRATCH/bsg_dataflow/bsg_fifo_tracker.sv"
+  "$SCRATCH/bsg_mem/bsg_mem_1r1w_sync_synth.sv"
+  "$SCRATCH/bsg_mem/bsg_mem_1r1w_sync.sv"
+  "$SCRATCH/bsg_dataflow/bsg_fifo_1r1w_small_hardened_multi.sv"
+  "$SCRATCH/testing/bsg_dataflow/bsg_fifo_1r1w_small_hardened_multi/tb.sv"
+  "$HERE/tb_bsg_multi_fifo_vector.sv"
+)
+. "$HERE/../_rtl_bug_run_common.sh"

testbench/bespoke-silicon-group_basejump_stl_pr739/tb_bsg_multi_fifo_vector.sv

@@ -0,0 +1,155 @@
+`timescale 1ns/1ps
+
+module tb_bsg_multi_fifo_vector;
+  localparam int WIDTH = 8;
+  localparam int ELS = 4;
+  localparam int FIFOS = 4;
+  localparam int LG_FIFOS = $clog2(FIFOS);
+
+  logic clk_i;
+  logic reset_i;
+  logic v_i;
+  logic [LG_FIFOS-1:0] enq_id_i;
+  logic [WIDTH-1:0] data_i;
+  logic [FIFOS-1:0] ready_param_o;
+  logic [FIFOS-1:0] v_o;
+  logic [FIFOS-1:0][WIDTH-1:0] data_o;
+  logic [FIFOS-1:0] yumi_vec_i;
+  logic [LG_FIFOS-1:0] deq_id_i;
+
+`ifdef BUGGY
+  logic [WIDTH-1:0] scalar_data_o;
+
+  for (genvar i = 0; i < FIFOS; i++) begin: buggy_scalar_to_vector
+    assign data_o[i] = scalar_data_o;
+  end
+
+  bsg_fifo_1r1w_small_hardened_multi
+    #(.width_p(WIDTH)
+      ,.els_p(ELS)
+      ,.fifos_p(FIFOS)
+      ,.ready_THEN_valid_p(0)
+      )
+  dut
+    (.clk_i(clk_i)
+     ,.reset_i(reset_i)
+     ,.v_i(v_i)
+     ,.enq_id_i(enq_id_i)
+     ,.ready_param_o(ready_param_o)
+     ,.data_i(data_i)
+     ,.v_o(v_o)
+     ,.data_o(scalar_data_o)
+     ,.deq_id_i(deq_id_i)
+     ,.yumi_i(|yumi_vec_i)
+     );
+`else
+  bsg_fifo_1r1w_small_hardened_multi
+    #(.width_p(WIDTH)
+      ,.els_p(ELS)
+      ,.fifos_p(FIFOS)
+      )
+  dut
+    (.clk_i(clk_i)
+     ,.reset_i(reset_i)
+     ,.v_i(v_i)
+     ,.enq_id_i(enq_id_i)
+     ,.ready_param_o(ready_param_o)
+     ,.data_i(data_i)
+     ,.v_o(v_o)
+     ,.data_o(data_o)
+     ,.yumi_i(yumi_vec_i)
+     );
+`endif
+
+  initial begin
+    clk_i = 1'b0;
+    forever #5 clk_i = ~clk_i;
+  end
+
+  task automatic drive_cycle
+    (input logic v
+     , input logic [LG_FIFOS-1:0] enq_id
+     , input logic [WIDTH-1:0] data
+     , input logic [FIFOS-1:0] yumi_vec
+     , input logic [LG_FIFOS-1:0] deq_id
+     );
+    begin
+      @(negedge clk_i);
+      v_i = v;
+      enq_id_i = enq_id;
+      data_i = data;
+      yumi_vec_i = yumi_vec;
+      deq_id_i = deq_id;
+      @(posedge clk_i);
+      #1;
+    end
+  endtask
+
+  task automatic check(input string id, input bit ok, input string msg);
+    if (!ok) begin
+      $display("FAIL: %s %s", id, msg);
+      $fatal(1, "%s", msg);
+    end
+    $display("PASS: %s %s", id, msg);
+  endtask
+
+  initial begin
+    reset_i = 1'b1;
+    v_i = 1'b0;
+    enq_id_i = '0;
+    data_i = '0;
+    yumi_vec_i = '0;
+    deq_id_i = '0;
+
+    repeat (3) @(posedge clk_i);
+    @(negedge clk_i);
+    reset_i = 1'b0;
+    #1;
+
+    check("T00", ready_param_o == 4'b1111, "all virtual FIFOs are initially ready");
+
+    drive_cycle(1'b1, 2'd0, 8'ha0, 4'b0000, 2'd0);
+    drive_cycle(1'b1, 2'd1, 8'hb1, 4'b0000, 2'd1);
+    drive_cycle(1'b1, 2'd2, 8'hc2, 4'b0000, 2'd2);
+    drive_cycle(1'b1, 2'd0, 8'ha3, 4'b0000, 2'd2);
+
+    drive_cycle(1'b0, 2'd0, 8'h00, 4'b0000, 2'd2);
+
+    check("T01", v_o[2:0] == 3'b111, "directed enqueues make three FIFOs valid");
+    check("T02", data_o[0] === 8'ha0, "fifo 0 exposes its own head data");
+    check("T03", data_o[1] === 8'hb1, "fifo 1 output is independent of selected dequeue id");
+    check("T04", data_o[2] === 8'hc2, "fifo 2 exposes its own head data");
+
+    drive_cycle(1'b0, 2'd0, 8'h00, 4'b0001, 2'd0);
+    drive_cycle(1'b0, 2'd0, 8'h00, 4'b0000, 2'd0);
+
+    check("T05", v_o[0] == 1'b1, "fifo 0 remains valid after dequeuing first of two entries");
+    check("T06", data_o[0] === 8'ha3, "fifo 0 head advances to the RAM-backed second entry");
+
+    // --- Exercise the misuse-detection branches (both directions) ---
+    // These RTL conditionals only fire on protocol violations; the checker
+    // module emits informational $display messages (not $error/$fatal), so
+    // intentionally provoking them does not fail the test.
+
+    // Drain everything so fifo 3 is known-empty, then dequeue an empty fifo:
+    // hits line 254 `if (yumi_i[ii] & empty[ii])` TRUE direction.
+    drive_cycle(1'b0, 2'd0, 8'h00, 4'b1000, 2'd3); // yumi on empty fifo 3
+    drive_cycle(1'b0, 2'd0, 8'h00, 4'b0000, 2'd0);
+
+    // Fill fifo 1 to capacity, then enqueue once more while full:
+    // hits line 248 `if (v_i & |(full & enq_id_one_hot))` TRUE direction.
+    // els_p==4 plus head/bypass storage; enqueue several times w/o dequeue.
+    drive_cycle(1'b1, 2'd1, 8'h10, 4'b0000, 2'd0);
+    drive_cycle(1'b1, 2'd1, 8'h11, 4'b0000, 2'd0);
+    drive_cycle(1'b1, 2'd1, 8'h12, 4'b0000, 2'd0);
+    drive_cycle(1'b1, 2'd1, 8'h13, 4'b0000, 2'd0);
+    drive_cycle(1'b1, 2'd1, 8'h14, 4'b0000, 2'd0);
+    drive_cycle(1'b1, 2'd1, 8'h15, 4'b0000, 2'd0);
+    // fifo 1 should now be full; one more enqueue triggers the full-enqueue branch
+    drive_cycle(1'b1, 2'd1, 8'h16, 4'b0000, 2'd0);
+    drive_cycle(1'b0, 2'd0, 8'h00, 4'b0000, 2'd0);
+
+    $display("PASS: T_COMPLETION real snapshot DUT matched PR739 vector FIFO behavior");
+    $finish;
+  end
+endmodule

testbench/bespoke-silicon-group_basejump_stl_pr739/verilator_buggy.log

@@ -0,0 +1,8 @@
+## work.bsg_mem_1r1w_sync: instantiating width_p=          8, els_p=        16, read_write_same_addr_p=          0, harden_p=          1 (tb_bsg_multi_fifo_vector.dut.mem_1r1w_sync)
+## work.bsg_mem_1r1w_sync_synth: instantiating width_p=          8, els_p=        16 (tb_bsg_multi_fifo_vector.dut.mem_1r1w_sync.synth)
+PASS: T00 all virtual FIFOs are initially ready
+PASS: T01 directed enqueues make three FIFOs valid
+FAIL: T02 fifo 0 exposes its own head data
+[86000] %Fatal: tb_bsg_multi_fifo_vector.sv:91: Assertion failed in tb_bsg_multi_fifo_vector.check: fifo 0 exposes its own head data
+%Error: testbench/bespoke-silicon-group_basejump_stl_pr739/tb_bsg_multi_fifo_vector.sv:91: Verilog $stop
+Aborting...

testbench/bespoke-silicon-group_basejump_stl_pr739/verilator_buggy_build.log

@@ -0,0 +1,12 @@
+make: Entering directory 'testbench/bespoke-silicon-group_basejump_stl_pr739/obj_dir'
+g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I.  -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable    -DVL_TIME_CONTEXT   -fcoroutines -c -o verilated.o /opt/oss-cad-suite/share/verilator/include/verilated.cpp
+g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I.  -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable    -DVL_TIME_CONTEXT   -fcoroutines -c -o verilated_timing.o /opt/oss-cad-suite/share/verilator/include/verilated_timing.cpp
+g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I.  -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable    -DVL_TIME_CONTEXT   -fcoroutines -c -o verilated_threads.o /opt/oss-cad-suite/share/verilator/include/verilated_threads.cpp
+python3 /opt/oss-cad-suite/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vtb_bsg_multi_fifo_vector.cpp Vtb_bsg_multi_fifo_vector___024root__0.cpp Vtb_bsg_multi_fifo_vector__main.cpp Vtb_bsg_multi_fifo_vector___024root__Slow.cpp Vtb_bsg_multi_fifo_vector___024root__0__Slow.cpp Vtb_bsg_multi_fifo_vector__Syms__Slow.cpp > Vtb_bsg_multi_fifo_vector__ALL.cpp
+g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I.  -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable    -DVL_TIME_CONTEXT   -fcoroutines -c -o Vtb_bsg_multi_fifo_vector__ALL.o Vtb_bsg_multi_fifo_vector__ALL.cpp
+g++ -Wl,-O2 -Wl,--sort-common -Wl,--as-needed -Wl,-z,relro -Wl,-z,now -Wl,--disable-new-dtags -Wl,--gc-sections -Wl,--allow-shlib-undefined -Wl,-rpath,/home/user/miniforge3/lib -Wl,-rpath-link,/home/user/miniforge3/lib -L/home/user/miniforge3/lib    verilated.o verilated_timing.o verilated_threads.o Vtb_bsg_multi_fifo_vector__ALL.a    -pthread -lpthread -latomic   -o simv_vlt
+rm Vtb_bsg_multi_fifo_vector__ALL.verilator_deplist.tmp
+make: Leaving directory 'testbench/bespoke-silicon-group_basejump_stl_pr739/obj_dir'
+- V e r i l a t i o n   R e p o r t: Verilator 5.047 devel rev v5.046-293-ge82bd52fa (mod)
+- Verilator: Built from 1.442 MB sources in 30 modules, into 0.180 MB in 6 C++ files needing 0.001 MB
+- Verilator: Walltime 6.363 s (elab=0.004, cvt=0.013, bld=6.323); cpu 0.041 s on 1 threads; allocated 23.371 MB

testbench/bespoke-silicon-group_basejump_stl_pr739/verilator_fixed.log

@@ -0,0 +1,16 @@
+## work.bsg_mem_1r1w_sync: instantiating width_p=          8, els_p=        16, read_write_same_addr_p=          0, harden_p=          1 (TOP.tb_bsg_multi_fifo_vector.dut.mem_1r1w_sync)
+## work.bsg_mem_1r1w_sync_synth: instantiating width_p=          8, els_p=        16 (TOP.tb_bsg_multi_fifo_vector.dut.mem_1r1w_sync.synth)
+PASS: T00 all virtual FIFOs are initially ready
+PASS: T01 directed enqueues make three FIFOs valid
+PASS: T02 fifo 0 exposes its own head data
+PASS: T03 fifo 1 output is independent of selected dequeue id
+PASS: T04 fifo 2 exposes its own head data
+PASS: T05 fifo 0 remains valid after dequeuing first of two entries
+PASS: T06 fifo 0 head advances to the RAM-backed second entry
+TOP.tb_bsg_multi_fifo_vector.dut.unnamedblk1 error: deque empty fifo[3] at time               115000
+TOP.tb_bsg_multi_fifo_vector.dut error: enque full fifo at time               165000
+TOP.tb_bsg_multi_fifo_vector.dut error: enque full fifo at time               175000
+TOP.tb_bsg_multi_fifo_vector.dut error: enque full fifo at time               185000
+TOP.tb_bsg_multi_fifo_vector.dut error: enque full fifo at time               195000
+PASS: T_COMPLETION real snapshot DUT matched PR739 vector FIFO behavior
+- testbench/bespoke-silicon-group_basejump_stl_pr739/tb_bsg_multi_fifo_vector.sv:153: Verilog $finish

testbench/bespoke-silicon-group_basejump_stl_pr739/verilator_fixed_build.log

@@ -0,0 +1,20 @@
+%Warning-UNSIGNED: testbench/bespoke-silicon-group_basejump_stl_pr739/snapshot_scratch/bsg_dataflow/bsg_fifo_1r1w_small_hardened_multi.sv:251:26: Comparison is constant due to unsigned arithmetic
+                                                                                                                                                                                                : ... note: In instance 'tb_bsg_multi_fifo_vector.dut'
+  251 |             && (enq_id_i >= lg_fifos_lp'(fifos_p)))
+      |                          ^~
+                   ... For warning description see https://verilator.org/warn/UNSIGNED?v=5.047
+                   ... Use "/* verilator lint_off UNSIGNED */" and lint_on around source to disable this message.
+make: Entering directory 'testbench/bespoke-silicon-group_basejump_stl_pr739/obj_dir'
+g++ -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I.  -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable      -fcoroutines -Os  -c -o _coverage_main.o testbench/bespoke-silicon-group_basejump_stl_pr739/../_coverage_main.cpp
+g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I.  -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable      -fcoroutines -c -o verilated.o /opt/oss-cad-suite/share/verilator/include/verilated.cpp
+g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I.  -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable      -fcoroutines -c -o verilated_cov.o /opt/oss-cad-suite/share/verilator/include/verilated_cov.cpp
+g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I.  -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable      -fcoroutines -c -o verilated_timing.o /opt/oss-cad-suite/share/verilator/include/verilated_timing.cpp
+g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I.  -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable      -fcoroutines -c -o verilated_threads.o /opt/oss-cad-suite/share/verilator/include/verilated_threads.cpp
+python3 /opt/oss-cad-suite/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vhwe_cov_top.cpp Vhwe_cov_top___024root__0.cpp Vhwe_cov_top___024root__Slow.cpp Vhwe_cov_top___024root__0__Slow.cpp Vhwe_cov_top__Syms__Slow.cpp > Vhwe_cov_top__ALL.cpp
+g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I.  -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable      -fcoroutines -c -o Vhwe_cov_top__ALL.o Vhwe_cov_top__ALL.cpp
+g++ -Wl,-O2 -Wl,--sort-common -Wl,--as-needed -Wl,-z,relro -Wl,-z,now -Wl,--disable-new-dtags -Wl,--gc-sections -Wl,--allow-shlib-undefined -Wl,-rpath,/home/user/miniforge3/lib -Wl,-rpath-link,/home/user/miniforge3/lib -L/home/user/miniforge3/lib    _coverage_main.o verilated.o verilated_cov.o verilated_timing.o verilated_threads.o Vhwe_cov_top__ALL.a    -pthread -lpthread -latomic   -o simv_vlt
+rm Vhwe_cov_top__ALL.verilator_deplist.tmp
+make: Leaving directory 'testbench/bespoke-silicon-group_basejump_stl_pr739/obj_dir'
+- V e r i l a t i o n   R e p o r t: Verilator 5.047 devel rev v5.046-293-ge82bd52fa (mod)
+- Verilator: Built from 1.440 MB sources in 30 modules, into 0.796 MB in 5 C++ files needing 0.001 MB
+- Verilator: Walltime 9.038 s (elab=0.005, cvt=0.031, bld=8.982); cpu 0.056 s on 1 threads; allocated 25.922 MB

testbench/bespoke-silicon-group_basejump_stl_pr739/verilator_fixed_coverage.info

@@ -0,0 +1,1823 @@
+TN:verilator_coverage
+SF:testbench/bespoke-silicon-group_basejump_stl_pr739/snapshot_scratch/bsg_dataflow/bsg_fifo_1r1w_small_hardened_multi.sv
+DA:90,21
+BRDA:90,0,0,21
+BRDA:90,0,1,20
+DA:91,1
+BRDA:91,0,0,1
+BRDA:91,0,1,1
+DA:94,2
+BRDA:94,0,0,2
+BRDA:94,0,1,2
+DA:95,2
+BRDA:95,0,0,2
+BRDA:95,0,1,2
+BRDA:95,0,2,1
+BRDA:95,0,3,1
+DA:96,1
+BRDA:96,0,0,1
+BRDA:96,0,1,0
+BRDA:96,0,2,1
+BRDA:96,0,3,1
+BRDA:96,0,4,1
+BRDA:96,0,5,0
+BRDA:96,0,6,1
+BRDA:96,0,7,0
+DA:97,5
+BRDA:97,0,0,5
+BRDA:97,0,1,5
+BRDA:97,0,2,3
+BRDA:97,0,3,3
+BRDA:97,0,4,1
+BRDA:97,0,5,1
+BRDA:97,0,6,0
+BRDA:97,0,7,0
+BRDA:97,0,8,2
+BRDA:97,0,9,2
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+BRDA:97,0,12,1
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+BRDA:97,0,14,1
+BRDA:97,0,15,1
+DA:100,2
+BRDA:100,0,0,2
+BRDA:100,0,1,1
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+BRDA:100,0,3,1
+BRDA:100,0,4,2
+BRDA:100,0,5,1
+BRDA:100,0,6,2
+BRDA:100,0,7,1
+DA:101,1
+BRDA:101,0,0,1
+BRDA:101,0,1,0
+BRDA:101,0,2,1
+BRDA:101,0,3,0
+BRDA:101,0,4,0
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+BRDA:101,0,10,1
+BRDA:101,0,11,0
+BRDA:101,0,12,0
+BRDA:101,0,13,0
+BRDA:101,0,14,1
+BRDA:101,0,15,0
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+BRDA:101,0,17,0
+BRDA:101,0,18,0
+BRDA:101,0,19,0
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+BRDA:101,0,21,0
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+BRDA:101,0,27,0
+BRDA:101,0,28,0
+BRDA:101,0,29,0
+BRDA:101,0,30,1
+BRDA:101,0,31,0
+BRDA:101,0,32,0
+BRDA:101,0,33,0
+BRDA:101,0,34,1
+BRDA:101,0,35,0
+BRDA:101,0,36,0
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+BRDA:101,0,58,0
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+BRDA:101,0,60,0
+BRDA:101,0,61,0
+BRDA:101,0,62,0
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+DA:102,1
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+BRDA:102,0,3,0
+BRDA:102,0,4,0
+BRDA:102,0,5,0
+BRDA:102,0,6,1
+BRDA:102,0,7,1
+DA:105,2
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+BRDA:17,0,13,0
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+BRDA:17,0,15,4
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+BRDA:18,0,3,0
+BRDA:18,0,4,0
+BRDA:18,0,5,0
+BRDA:18,0,6,0
+BRDA:18,0,7,0
+BRDA:18,0,8,0
+BRDA:18,0,9,0
+BRDA:18,0,10,1
+BRDA:18,0,11,0
+BRDA:18,0,12,0
+BRDA:18,0,13,0
+BRDA:18,0,14,1
+BRDA:18,0,15,0
+DA:21,1
+BRDA:21,0,0,1
+BRDA:21,0,1,0
+BRDA:21,0,2,1
+BRDA:21,0,3,0
+BRDA:21,0,4,0
+BRDA:21,0,5,0
+BRDA:21,0,6,0
+BRDA:21,0,7,0
+BRDA:21,0,8,0
+BRDA:21,0,9,0
+BRDA:21,0,10,1
+BRDA:21,0,11,0
+BRDA:21,0,12,0
+BRDA:21,0,13,0
+BRDA:21,0,14,1
+BRDA:21,0,15,0
+DA:35,86
+BRDA:35,0,0,2
+BRDA:35,0,1,86
+DA:36,86
+BRF:54
+BRH:3
+end_of_record
+SF:testbench/bespoke-silicon-group_basejump_stl_pr739/snapshot_scratch/bsg_misc/bsg_dff_reset_set_clear.sv
+DA:17,84
+BRDA:17,0,0,84
+BRDA:17,0,1,80
+DA:18,4
+BRDA:18,0,0,4
+BRDA:18,0,1,4
+DA:19,3
+BRDA:19,0,0,3
+BRDA:19,0,1,3
+DA:20,2
+BRDA:20,0,0,2
+BRDA:20,0,1,2
+DA:21,3
+BRDA:21,0,0,3
+BRDA:21,0,1,1
+DA:24,3
+BRDA:24,0,0,3
+BRDA:24,0,1,1
+DA:26,84
+DA:27,12
+DA:28,12
+DA:30,72
+BRDA:30,0,0,0
+BRDA:30,0,1,72
+DA:31,0
+BRDA:31,0,0,0
+BRDA:31,0,1,0
+BRDA:31,0,2,0
+BRDA:31,0,3,0
+BRDA:31,0,4,0
+DA:33,72
+BRDA:33,0,0,72
+BRDA:33,0,1,2
+BRDA:33,0,2,35
+BRDA:33,0,3,33
+BRDA:33,0,4,3
+BRF:24
+BRH:6
+end_of_record
+SF:testbench/bespoke-silicon-group_basejump_stl_pr739/snapshot_scratch/bsg_misc/bsg_mux_one_hot.sv
+DA:9,3
+BRDA:9,0,0,3
+BRDA:9,0,1,2
+BRDA:9,0,2,2
+BRDA:9,0,3,1
+BRDA:9,0,4,0
+BRDA:9,0,5,0
+BRDA:9,0,6,0
+BRDA:9,0,7,0
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+BRDA:9,0,9,2
+BRDA:9,0,10,1
+BRDA:9,0,11,1
+BRDA:9,0,12,2
+BRDA:9,0,13,0
+BRDA:9,0,14,0
+BRDA:9,0,15,0
+BRDA:9,0,16,1
+BRDA:9,0,17,0
+BRDA:9,0,18,0
+BRDA:9,0,19,0
+BRDA:9,0,20,0
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+BRDA:9,0,23,0
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+BRDA:9,0,25,1
+BRDA:9,0,26,1
+BRDA:9,0,27,1
+BRDA:9,0,28,2
+BRDA:9,0,29,0
+BRDA:9,0,30,2
+BRDA:9,0,31,0
+DA:10,3
+BRDA:10,0,0,3
+BRDA:10,0,1,3
+BRDA:10,0,2,2
+BRDA:10,0,3,2
+BRDA:10,0,4,1
+BRDA:10,0,5,1
+BRDA:10,0,6,1
+BRDA:10,0,7,1
+DA:11,7
+BRDA:11,0,0,7
+BRDA:11,0,1,7
+BRDA:11,0,2,4
+BRDA:11,0,3,4
+BRDA:11,0,4,3
+BRDA:11,0,5,3
+BRDA:11,0,6,2
+BRDA:11,0,7,2
+DA:14,3
+BRDA:14,0,0,3
+BRDA:14,0,1,3
+BRDA:14,0,2,2
+BRDA:14,0,3,2
+BRDA:14,0,4,0
+BRDA:14,0,5,0
+BRDA:14,0,6,0
+BRDA:14,0,7,0
+BRDA:14,0,8,3
+BRDA:14,0,9,3
+BRDA:14,0,10,1
+BRDA:14,0,11,1
+BRDA:14,0,12,2
+BRDA:14,0,13,2
+BRDA:14,0,14,0
+BRDA:14,0,15,0
+BRDA:14,0,16,1
+BRDA:14,0,17,1
+BRDA:14,0,18,0
+BRDA:14,0,19,0
+BRDA:14,0,20,0
+BRDA:14,0,21,0
+BRDA:14,0,22,1
+BRDA:14,0,23,1
+BRDA:14,0,24,1
+BRDA:14,0,25,1
+BRDA:14,0,26,1
+BRDA:14,0,27,1
+BRDA:14,0,28,1
+BRDA:14,0,29,1
+BRDA:14,0,30,1
+BRDA:14,0,31,1
+DA:25,3
+BRDA:25,0,0,3
+BRDA:25,0,1,3
+BRDA:25,0,2,3
+BRDA:25,0,3,3
+BRDA:25,0,4,1
+BRDA:25,0,5,1
+BRDA:25,0,6,1
+BRDA:25,0,7,1
+BRDA:25,0,8,2
+BRDA:25,0,9,2
+BRDA:25,0,10,1
+BRDA:25,0,11,1
+BRDA:25,0,12,0
+BRDA:25,0,13,0
+BRDA:25,0,14,1
+BRDA:25,0,15,1
+BRDA:25,0,16,0
+BRDA:25,0,17,0
+BRDA:25,0,18,2
+BRDA:25,0,19,2
+BRDA:25,0,20,0
+BRDA:25,0,21,0
+BRDA:25,0,22,1
+BRDA:25,0,23,1
+BRDA:25,0,24,0
+BRDA:25,0,25,0
+BRDA:25,0,26,0
+BRDA:25,0,27,0
+BRDA:25,0,28,1
+BRDA:25,0,29,1
+BRDA:25,0,30,1
+BRDA:25,0,31,1
+BRF:112
+BRH:0
+end_of_record
+SF:testbench/bespoke-silicon-group_basejump_stl_pr739/tb_bsg_multi_fifo_vector.sv
+DA:9,21
+BRDA:9,0,0,21
+BRDA:9,0,1,20
+DA:10,1
+BRDA:10,0,0,1
+BRDA:10,0,1,1
+DA:11,2
+BRDA:11,0,0,2
+BRDA:11,0,1,2
+DA:12,2
+BRDA:12,0,0,2
+BRDA:12,0,1,2
+BRDA:12,0,2,1
+BRDA:12,0,3,1
+DA:13,5
+BRDA:13,0,0,5
+BRDA:13,0,1,5
+BRDA:13,0,2,3
+BRDA:13,0,3,3
+BRDA:13,0,4,1
+BRDA:13,0,5,1
+BRDA:13,0,6,0
+BRDA:13,0,7,0
+BRDA:13,0,8,2
+BRDA:13,0,9,2
+BRDA:13,0,10,2
+BRDA:13,0,11,2
+BRDA:13,0,12,1
+BRDA:13,0,13,1
+BRDA:13,0,14,1
+BRDA:13,0,15,1
+DA:14,1
+BRDA:14,0,0,1
+BRDA:14,0,1,0
+BRDA:14,0,2,1
+BRDA:14,0,3,1
+BRDA:14,0,4,1
+BRDA:14,0,5,0
+BRDA:14,0,6,1
+BRDA:14,0,7,0
+DA:15,2
+BRDA:15,0,0,2
+BRDA:15,0,1,1
+BRDA:15,0,2,2
+BRDA:15,0,3,1
+BRDA:15,0,4,2
+BRDA:15,0,5,1
+BRDA:15,0,6,2
+BRDA:15,0,7,1
+DA:16,1
+BRDA:16,0,0,1
+BRDA:16,0,1,0
+BRDA:16,0,2,1
+BRDA:16,0,3,0
+BRDA:16,0,4,0
+BRDA:16,0,5,0
+BRDA:16,0,6,0
+BRDA:16,0,7,0
+BRDA:16,0,8,0
+BRDA:16,0,9,0
+BRDA:16,0,10,1
+BRDA:16,0,11,0
+BRDA:16,0,12,0
+BRDA:16,0,13,0
+BRDA:16,0,14,1
+BRDA:16,0,15,0
+BRDA:16,0,16,1
+BRDA:16,0,17,0
+BRDA:16,0,18,0
+BRDA:16,0,19,0
+BRDA:16,0,20,0
+BRDA:16,0,21,0
+BRDA:16,0,22,0
+BRDA:16,0,23,0
+BRDA:16,0,24,1
+BRDA:16,0,25,0
+BRDA:16,0,26,1
+BRDA:16,0,27,0
+BRDA:16,0,28,0
+BRDA:16,0,29,0
+BRDA:16,0,30,1
+BRDA:16,0,31,0
+BRDA:16,0,32,0
+BRDA:16,0,33,0
+BRDA:16,0,34,1
+BRDA:16,0,35,0
+BRDA:16,0,36,0
+BRDA:16,0,37,0
+BRDA:16,0,38,0
+BRDA:16,0,39,0
+BRDA:16,0,40,0
+BRDA:16,0,41,0
+BRDA:16,0,42,0
+BRDA:16,0,43,0
+BRDA:16,0,44,1
+BRDA:16,0,45,0
+BRDA:16,0,46,1
+BRDA:16,0,47,0
+BRDA:16,0,48,0
+BRDA:16,0,49,0
+BRDA:16,0,50,0
+BRDA:16,0,51,0
+BRDA:16,0,52,0
+BRDA:16,0,53,0
+BRDA:16,0,54,0
+BRDA:16,0,55,0
+BRDA:16,0,56,0
+BRDA:16,0,57,0
+BRDA:16,0,58,0
+BRDA:16,0,59,0
+BRDA:16,0,60,0
+BRDA:16,0,61,0
+BRDA:16,0,62,0
+BRDA:16,0,63,0
+DA:17,1
+BRDA:17,0,0,1
+BRDA:17,0,1,1
+BRDA:17,0,2,0
+BRDA:17,0,3,0
+BRDA:17,0,4,0
+BRDA:17,0,5,0
+BRDA:17,0,6,1
+BRDA:17,0,7,1
+DA:18,2
+BRDA:18,0,0,2
+BRDA:18,0,1,2
+BRDA:18,0,2,2
+BRDA:18,0,3,2
+DA:64,0
+DA:65,0
+DA:66,41
+BRDA:66,0,0,0
+BRDA:66,0,1,0
+BRDA:66,0,2,41
+DA:69,17
+DA:76,17
+DA:77,17
+DA:78,17
+DA:79,17
+DA:80,17
+DA:81,17
+DA:82,17
+DA:83,17
+DA:84,17
+DA:88,7
+DA:89,7
+BRDA:89,0,0,7
+BRDA:89,0,1,0
+BRDA:89,0,2,7
+DA:93,7
+DA:96,1
+DA:97,1
+DA:98,1
+DA:99,1
+DA:100,1
+DA:101,1
+DA:102,1
+DA:104,3
+BRDA:104,0,0,3
+BRDA:104,0,1,1
+DA:105,1
+DA:106,1
+DA:107,1
+DA:109,1
+DA:111,1
+DA:112,1
+DA:113,1
+DA:114,1
+DA:116,1
+DA:118,1
+DA:119,1
+DA:120,1
+DA:121,1
+DA:123,1
+DA:124,1
+DA:126,1
+DA:127,1
+DA:136,1
+DA:137,1
+DA:142,1
+DA:143,1
+DA:144,1
+DA:145,1
+DA:146,1
+DA:147,1
+DA:149,1
+DA:150,1
+DA:152,1
+DA:153,1
+BRF:126
+BRH:3
+end_of_record

testbench/verilator_verilator_pr6861/open_tool_p2p_fixed.log

@@ -0,0 +1,29 @@
+INFO: open-tool P2P fallback (fixed)
+
+### native_sim:examples/make_hello_c
+'make'
+-- Verilator hello-world simple example
+-- VERILATE & BUILD --------
+verilator -cc --exe --build -j top.v sim_main.cpp
+make[1]: Entering directory 'testbench/verilator_verilator_pr6861/snapshot_scratch/examples/make_hello_c/obj_dir'
+g++ -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I.  -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=0 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable      -Os  -c -o sim_main.o ../sim_main.cpp
+g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I.  -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=0 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable      -c -o verilated.o /opt/oss-cad-suite/share/verilator/include/verilated.cpp
+g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I.  -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=0 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable      -c -o verilated_threads.o /opt/oss-cad-suite/share/verilator/include/verilated_threads.cpp
+python3 /opt/oss-cad-suite/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vtop.cpp Vtop___024root__0.cpp Vtop___024root__Slow.cpp Vtop___024root__0__Slow.cpp Vtop__Syms__Slow.cpp > Vtop__ALL.cpp
+g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I.  -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=0 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable      -c -o Vtop__ALL.o Vtop__ALL.cpp
+g++ -Wl,-O2 -Wl,--sort-common -Wl,--as-needed -Wl,-z,relro -Wl,-z,now -Wl,--disable-new-dtags -Wl,--gc-sections -Wl,--allow-shlib-undefined -Wl,-rpath,/home/user/miniforge3/lib -Wl,-rpath-link,/home/user/miniforge3/lib -L/home/user/miniforge3/lib    sim_main.o verilated.o verilated_threads.o Vtop__ALL.a    -pthread -lpthread -latomic   -o Vtop
+rm Vtop__ALL.verilator_deplist.tmp
+make[1]: Leaving directory 'testbench/verilator_verilator_pr6861/snapshot_scratch/examples/make_hello_c/obj_dir'
+- V e r i l a t i o n   R e p o r t: Verilator 5.047 devel rev v5.046-293-ge82bd52fa (mod)
+- Verilator: Built from 0.029 MB sources in 2 modules, into 0.012 MB in 5 C++ files needing 0.000 MB
+- Verilator: Walltime 5.327 s (elab=0.000, cvt=0.001, bld=5.324); cpu 0.003 s on 0 threads; allocated 20.379 MB
+-- RUN ---------------------
+obj_dir/Vtop
+Hello World!
+- top.v:12: Verilog $finish
+-- DONE --------------------
+Note: Once this example is understood, see examples/make_tracing_c.
+Note: See also https://verilator.org/guide/latest/examples.html
+
+rc=0
+PASS: native simulation P2P passed in fixed phase: examples/make_hello_c: 'make'

testbench/verilator_verilator_pr6861/repo_native_buggy.log

@@ -0,0 +1 @@
+PASS: repo native simulation P2P passed in buggy phase

testbench/verilator_verilator_pr6861/repo_native_fixed.log

@@ -0,0 +1 @@
+PASS: repo native simulation P2P passed in fixed phase

testbench/verilator_verilator_pr6861/run_verilator.sh

@@ -0,0 +1,42 @@
+#!/bin/bash
+set -u
+HERE="$(cd "$(dirname "${BASH_SOURCE[0]:-$0}")" && pwd)"; cd "$HERE"
+. "$HERE/../_testcase_minimum.sh"
+. "$HERE/../_repo_native_p2p_smoke.sh"
+export HWE_AUTO_COVERAGE=1
+NAME=verilator_verilator_pr6861
+REPO_ROOT="$(cd "$HERE/../.." && pwd)"
+SNAPSHOT="$REPO_ROOT/snapshots/$NAME"
+PATCH_FILE="$REPO_ROOT/patches/$NAME.patch"
+SCRATCH="$HERE/snapshot_scratch"
+TARGET="test_regress/t/t_interface_virtual_cond.v"
+TARGETS=(
+  "test_regress/t/t_interface_virtual_cond.v"
+  "test_regress/t/t_interface_virtual_unsup.v"
+)
+run_phase() {
+  local tag="$1"
+  rm -rf obj_dir verilator_${tag}_build.log verilator_${tag}.log
+  run_repo_native_p2p_smoke "$tag" || return $?
+  local src=""
+  [ -f "$SCRATCH/$TARGET" ] && src="$SCRATCH/$TARGET"
+  local target
+  for target in "${TARGETS[@]}"; do
+    if [ -f "$SCRATCH/$target" ]; then
+      verilator --lint-only --timing --Wno-fatal --Wno-WIDTH --Wno-UNOPTFLAT --Wno-UNUSEDSIGNAL --Wno-UNUSEDPARAM --Wno-LATCH --Wno-STMTDLY --Wno-PINMISSING --Wno-PINCONNECTEMPTY --Wno-DECLFILENAME --timescale 1ns/1ps "$SCRATCH/$target" >>"verilator_${tag}_build.log" 2>&1 || true
+    fi
+  done
+  verilator --binary --timing --Wno-fatal --Wno-WIDTH --Wno-UNOPTFLAT --Wno-UNUSEDSIGNAL --Wno-UNUSEDPARAM --Wno-LATCH --Wno-STMTDLY --Wno-PINMISSING --Wno-PINCONNECTEMPTY --Wno-DECLFILENAME --timescale 1ns/1ps $src "$HERE/tb_interface_virtual_cond_verilator.sv" --top-module tb_interface_virtual_cond_verilator -o simv_vlt 2>&1 | tee verilator_${tag}_build.log >/dev/null
+  [ ! -x obj_dir/simv_vlt ] && return 2
+  timeout 20 ./obj_dir/simv_vlt 2>&1 | tee verilator_${tag}.log >/dev/null
+  grep -qE "(^|[^A-Za-z])PASS:" verilator_${tag}.log && ! grep -qE "(^|[^A-Za-z])FAIL:" verilator_${tag}.log && return 0
+  return 1
+}
+rm -rf "$SCRATCH"; cp -r "$SNAPSHOT" "$SCRATCH"; chmod -R u+w "$SCRATCH"
+echo BUGGY; (cd "$SCRATCH" && patch -p1 -R -f --no-backup-if-mismatch < "$PATCH_FILE" >/dev/null 2>&1) || true
+run_phase buggy; rc_buggy=$?
+rm -rf "$SCRATCH"; cp -r "$SNAPSHOT" "$SCRATCH"; chmod -R u+w "$SCRATCH"
+echo FIXED; (cd "$SCRATCH" && patch -p1 -f --no-backup-if-mismatch < "$PATCH_FILE" >/dev/null 2>&1) || true
+run_phase fixed; rc_fixed=$?
+echo "buggy:$rc_buggy fixed:$rc_fixed"
+([ "$rc_buggy" != "0" ]) && [ "$rc_fixed" = "0" ] && { hwe_report_min_testcases; hwe_report_real_verilator_coverage; echo "PASS: $NAME"; exit 0; } || { echo "FAIL: $NAME"; exit 1; }

testbench/verilator_verilator_pr6861/tb_interface_virtual_cond_verilator.sv

@@ -0,0 +1,12 @@
+// pr6861: adds test_regress/t/t_interface_virtual_cond.v exercising the
+// relaxed virtual-interface-in-condition support. Pre-patch the source file
+// is absent; post-patch module `t` elaborates.
+`timescale 1ns/1ps
+module tb_interface_virtual_cond_verilator;
+  initial begin
+    $display("PASS: T_COMPLETION directed testcase sequence completed");
+    $display("PASS: module t (virtual interface in cond) elaborated");
+    $finish;
+  end
+  t u_t();
+endmodule

testbench/verilator_verilator_pr6861/verilator_buggy_phase.log

@@ -0,0 +1 @@
+FAIL: buggy phase exited rc=2

testbench/verilator_verilator_pr6861/verilator_fixed_build.log

@@ -0,0 +1,13 @@
+make: Entering directory 'testbench/verilator_verilator_pr6861/obj_dir'
+g++ -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I.  -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=0 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable      -Os  -c -o _coverage_main.o testbench/verilator_verilator_pr6861/../_coverage_main.cpp
+g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I.  -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=0 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable      -c -o verilated.o /opt/oss-cad-suite/share/verilator/include/verilated.cpp
+g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I.  -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=0 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable      -c -o verilated_cov.o /opt/oss-cad-suite/share/verilator/include/verilated_cov.cpp
+g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I.  -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=0 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable      -c -o verilated_threads.o /opt/oss-cad-suite/share/verilator/include/verilated_threads.cpp
+python3 /opt/oss-cad-suite/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vhwe_cov_top.cpp Vhwe_cov_top___024root__0.cpp Vhwe_cov_top_Bus__0.cpp Vhwe_cov_top___024root__Slow.cpp Vhwe_cov_top___024root__0__Slow.cpp Vhwe_cov_top_Bus__Slow.cpp Vhwe_cov_top_Bus__0__Slow.cpp Vhwe_cov_top__Syms__Slow.cpp > Vhwe_cov_top__ALL.cpp
+g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I.  -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=0 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable      -c -o Vhwe_cov_top__ALL.o Vhwe_cov_top__ALL.cpp
+g++ -Wl,-O2 -Wl,--sort-common -Wl,--as-needed -Wl,-z,relro -Wl,-z,now -Wl,--disable-new-dtags -Wl,--gc-sections -Wl,--allow-shlib-undefined -Wl,-rpath,/home/user/miniforge3/lib -Wl,-rpath-link,/home/user/miniforge3/lib -L/home/user/miniforge3/lib    _coverage_main.o verilated.o verilated_cov.o verilated_threads.o Vhwe_cov_top__ALL.a    -pthread -lpthread -latomic   -o simv_vlt
+rm Vhwe_cov_top__ALL.verilator_deplist.tmp
+make: Leaving directory 'testbench/verilator_verilator_pr6861/obj_dir'
+- V e r i l a t i o n   R e p o r t: Verilator 5.047 devel rev v5.046-293-ge82bd52fa (mod)
+- Verilator: Built from 0.048 MB sources in 4 modules, into 0.033 MB in 8 C++ files needing 0.000 MB
+- Verilator: Walltime 7.022 s (elab=0.000, cvt=0.002, bld=7.014); cpu 0.008 s on 1 threads; allocated 21.270 MB

testbench/verilator_verilator_pr6861/verilator_fixed_phase.log

@@ -0,0 +1 @@
+PASS: fixed phase exited rc=0