Add files using upload-large-folder tool

snapshots/chipsalliance_adams-bridge_pr66/src/norm_check/config/compile.yml

@@ -0,0 +1,49 @@
+# Copyright (C) Microsoft Corporation. All rights reserved.
+
+# Go here for details on compile.yml syntax:
+# https://dev.azure.com/ms-tsd/Ether/_git/sim-tools?path=%2FSourceFileSpec.docx&version=GBmaster
+
+---
+provides: [norm_check_pkg]
+schema_version: 2.4.0
+requires: []
+targets:
+  rtl:
+    directories: [$COMPILE_ROOT/rtl]
+    files:
+      - $COMPILE_ROOT/rtl/norm_check_defines_pkg.sv
+  tb:
+    directories: [$COMPILE_ROOT/rtl]
+    files:
+      - $COMPILE_ROOT/rtl/norm_check_defines_pkg.sv
+---
+provides: [norm_check]
+schema_version: 2.4.0
+requires:
+  - norm_check_pkg
+  - mldsa_defines
+targets:
+  rtl:
+    directories: [$COMPILE_ROOT/rtl]
+    files:
+      - $COMPILE_ROOT/rtl/norm_check.sv
+      - $COMPILE_ROOT/rtl/norm_check_ctrl.sv
+      - $COMPILE_ROOT/rtl/norm_check_top.sv
+    tops: [norm_check]
+  rtl_lint:
+    directories: []
+    waiver_files:
+      - $MSFT_REPO_ROOT/src/norm_check/config/design_lint/norm_check/sglint_waivers
+---
+provides: [norm_check_tb]
+schema_version: 2.4.0
+requires: 
+  - norm_check
+  - norm_check_pkg
+  - mldsa_defines
+targets:
+  rtl:
+    directories: [$COMPILE_ROOT/tb]
+    files:
+      - $COMPILE_ROOT/tb/norm_check_tb.sv
+    tops: [norm_check_tb]

snapshots/chipsalliance_adams-bridge_pr66/src/norm_check/config/norm_check.vf

@@ -0,0 +1,9 @@
++incdir+${ADAMSBRIDGE_ROOT}/src/norm_check/rtl
++incdir+${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl
+${ADAMSBRIDGE_ROOT}/src/norm_check/rtl/norm_check_defines_pkg.sv
+${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_config_defines.svh
+${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_params_pkg.sv
+${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_reg_pkg.sv
+${ADAMSBRIDGE_ROOT}/src/norm_check/rtl/norm_check.sv
+${ADAMSBRIDGE_ROOT}/src/norm_check/rtl/norm_check_ctrl.sv
+${ADAMSBRIDGE_ROOT}/src/norm_check/rtl/norm_check_top.sv

snapshots/chipsalliance_adams-bridge_pr66/src/norm_check/config/norm_check_pkg.vf

@@ -0,0 +1,3 @@
++incdir+${ADAMSBRIDGE_ROOT}/src/norm_check/rtl
+${ADAMSBRIDGE_ROOT}/src/norm_check/rtl/norm_check_defines_pkg.sv
+${ADAMSBRIDGE_ROOT}/src/norm_check/rtl/norm_check_defines_pkg.sv

snapshots/chipsalliance_adams-bridge_pr66/src/norm_check/config/norm_check_tb.vf

@@ -0,0 +1,11 @@
++incdir+${ADAMSBRIDGE_ROOT}/src/norm_check/rtl
++incdir+${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl
++incdir+${ADAMSBRIDGE_ROOT}/src/norm_check/tb
+${ADAMSBRIDGE_ROOT}/src/norm_check/rtl/norm_check_defines_pkg.sv
+${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_config_defines.svh
+${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_params_pkg.sv
+${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_reg_pkg.sv
+${ADAMSBRIDGE_ROOT}/src/norm_check/rtl/norm_check.sv
+${ADAMSBRIDGE_ROOT}/src/norm_check/rtl/norm_check_ctrl.sv
+${ADAMSBRIDGE_ROOT}/src/norm_check/rtl/norm_check_top.sv
+${ADAMSBRIDGE_ROOT}/src/norm_check/tb/norm_check_tb.sv

snapshots/chipsalliance_adams-bridge_pr66/src/norm_check/rtl/norm_check.sv

@@ -0,0 +1,53 @@
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//======================================================================
+//
+// norm_check.sv
+// --------
+// Performs: invalid = (coeff > bound) && (coeff < q-bound)
+
+module norm_check
+    import norm_check_defines_pkg::*;
+    import mldsa_params_pkg::*;
+    #(
+        parameter MLDSA_Q = 8380417,
+        parameter GAMMA1 = 2**19,
+        // parameter MLDSA_GAMMA2 = (MLDSA_Q-1)/32,
+        parameter BETA = 120,
+        parameter GAMMA1_MINUS_BETA = GAMMA1 - BETA,
+        parameter GAMMA2_MINUS_BETA = MLDSA_GAMMA2 - BETA
+    )
+    (
+        input wire enable,
+        input chk_norm_mode_t mode,
+        input wire [REG_SIZE-2:0] opa_i,
+        output logic invalid
+    );
+
+    logic [REG_SIZE-2:0] bound;
+    logic [REG_SIZE-2:0] q_minus_bound;
+
+    always_comb begin
+        case(mode)
+            z_bound:    bound = GAMMA1_MINUS_BETA;
+            r0_bound:   bound = GAMMA2_MINUS_BETA;
+            ct0_bound:  bound = MLDSA_GAMMA2;
+            default:    bound = 'h0;
+        endcase
+
+        q_minus_bound = MLDSA_Q - bound;
+    end
+
+    always_comb invalid = enable & (opa_i >= bound) & (opa_i <= q_minus_bound);
+endmodule

snapshots/chipsalliance_adams-bridge_pr66/src/norm_check/rtl/norm_check_ctrl.sv

@@ -0,0 +1,159 @@
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//======================================================================
+//
+// norm_check_ctrl.sv
+// --------
+// Manages memory accesses for check norm module. Two reads are done
+// to perform 8 coeff checks per cycle. First port reads 0, 2, 4, etc, while second
+// port reads 1, 3, 5, etc
+// Assumes that one enable triggers check for all polynomials of chosen vector and 
+// assumes all polynomials of the vector are stored in continuous addr space in memory
+
+module norm_check_ctrl
+    import mldsa_params_pkg::*;
+    import norm_check_defines_pkg::*;
+    #(
+        parameter MLDSA_N = 256,
+        parameter MLDSA_L = 7,
+        parameter MLDSA_K = 8
+    )
+    (
+        input wire clk,
+        input wire reset_n,
+        input wire zeroize,
+
+        input wire norm_check_enable,
+        input chk_norm_mode_t mode,
+
+        input wire [5:0] randomness,
+
+        input wire [MLDSA_MEM_ADDR_WIDTH-1:0] mem_base_addr,
+        output mem_if_t mem_rd_req,
+        output logic check_enable,
+        output logic norm_check_done
+    );
+
+    
+    chk_read_state_e read_fsm_state_ps, read_fsm_state_ns;
+    logic [MLDSA_MEM_ADDR_WIDTH-1:0] mem_rd_addr, locked_based_addr;
+
+    //Flags
+    logic incr_rd_addr;
+    logic last_poly_last_addr;
+    logic norm_check_busy;
+
+    logic [4:0] latched_out_randomness;
+    logic latched_in_randomness;
+    logic [4:0] increment_addr;
+    logic [6:0] neutral_cnt;
+
+    always_ff @(posedge clk or negedge reset_n) begin
+        if (!reset_n) begin
+            latched_out_randomness  <= 'h0;
+            latched_in_randomness   <= 'h0;
+            increment_addr          <= 'h0;
+            mem_rd_addr             <= 'h0;
+            neutral_cnt             <= 'h0;
+            locked_based_addr       <= 'h0;
+        end
+        else if (zeroize) begin
+            latched_out_randomness  <= 'h0;
+            latched_in_randomness   <= 'h0;
+            increment_addr          <= 'h0;
+            mem_rd_addr             <= 'h0;
+            neutral_cnt             <= 'h0;
+            locked_based_addr       <= 'h0;
+        end
+        else begin
+            if (norm_check_enable) begin
+                latched_out_randomness  <= randomness[5:1];
+                latched_in_randomness   <= randomness[0];
+                increment_addr          <= randomness[5:1];
+                mem_rd_addr             <= {{(MLDSA_MEM_ADDR_WIDTH-6){1'b0}}, randomness};
+                neutral_cnt             <= 'h0;
+                locked_based_addr       <=  mem_base_addr;
+            end
+            else if (incr_rd_addr) begin
+                latched_in_randomness   <= latched_in_randomness;
+                latched_out_randomness  <= latched_out_randomness;
+                increment_addr          <= increment_addr;
+                mem_rd_addr             <= {mem_rd_addr[MLDSA_MEM_ADDR_WIDTH-1:6], increment_addr, latched_in_randomness};
+                neutral_cnt             <= neutral_cnt + 'h1;
+            end
+            else if (~incr_rd_addr) begin
+                latched_in_randomness   <= randomness[0];
+                latched_out_randomness  <= latched_out_randomness;
+                increment_addr          <= increment_addr + 'h1;
+                mem_rd_addr             <= {mem_rd_addr[MLDSA_MEM_ADDR_WIDTH-1:1], ~latched_in_randomness};
+                neutral_cnt             <= neutral_cnt + 'h1;
+            end
+        end
+    end
+
+    //Addr assignment
+    always_comb begin
+        mem_rd_req.addr = mem_rd_addr+locked_based_addr;
+
+        mem_rd_req.rd_wr_en = ((read_fsm_state_ps == CHK_RD_MEM) | (read_fsm_state_ps == CHK_WAIT)) ? RW_READ : RW_IDLE;
+    end
+
+    //Last addr flag
+    always_comb last_poly_last_addr = (neutral_cnt == ((MLDSA_N/4))-1);
+
+    //Ctrl flags
+    always_comb begin
+        norm_check_busy = (read_fsm_state_ps != CHK_IDLE);
+    end
+
+    //FSM
+    always_ff @(posedge clk or negedge reset_n) begin
+        if (!reset_n)
+            read_fsm_state_ps <= CHK_IDLE;
+        else if (zeroize)
+            read_fsm_state_ps <= CHK_IDLE;
+        else
+            read_fsm_state_ps <= read_fsm_state_ns;
+    end
+
+    always_comb begin
+        read_fsm_state_ns = read_fsm_state_ps;
+        incr_rd_addr = 'b0;
+        norm_check_done = 0;
+
+        case(read_fsm_state_ps)
+            CHK_IDLE: begin
+                read_fsm_state_ns = norm_check_enable ? CHK_RD_MEM : CHK_IDLE;
+            end
+            CHK_RD_MEM: begin
+                read_fsm_state_ns = last_poly_last_addr ? CHK_DONE : CHK_WAIT;
+                incr_rd_addr = 'b0;
+            end
+            CHK_WAIT: begin
+                read_fsm_state_ns = last_poly_last_addr ? CHK_DONE : CHK_RD_MEM;
+                incr_rd_addr = 'b1;
+            end
+            CHK_DONE: begin
+                read_fsm_state_ns = CHK_IDLE;
+                norm_check_done = 'b1;
+            end
+            default begin
+                read_fsm_state_ns = CHK_IDLE;
+            end
+        endcase
+    end
+
+    always_comb check_enable = (read_fsm_state_ps == CHK_RD_MEM) | (read_fsm_state_ps == CHK_WAIT);
+
+endmodule

snapshots/chipsalliance_adams-bridge_pr66/src/norm_check/rtl/norm_check_defines_pkg.sv

@@ -0,0 +1,34 @@
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//======================================================================
+//
+// norm_check_defines_pkg.sv
+// --------
+// Validity norm check parameters for the digital signature algorithm (DSA).
+//
+//
+//======================================================================
+
+`ifndef ABR_NORM_CHECK_DEFINES
+`define ABR_NORM_CHECK_DEFINES
+
+package norm_check_defines_pkg;
+
+    parameter z_bound = 2'h0, r0_bound = 2'h1, ct0_bound = 2'h2;
+    typedef logic [1:0] chk_norm_mode_t;
+
+    typedef enum logic [1:0] {CHK_IDLE, CHK_RD_MEM, CHK_WAIT, CHK_DONE} chk_read_state_e;
+endpackage
+
+`endif

snapshots/chipsalliance_adams-bridge_pr66/src/norm_check/rtl/norm_check_top.sv

@@ -0,0 +1,135 @@
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//======================================================================
+//
+// norm_check_top.sv
+// --------
+// Performs the 3 validity checks (z, r0, ct0) needed for signing algorithm based on mode selection
+// Generates one final invalid bit that is accumulated across all polynomials of the chosen vector
+// Since this module only has to read from memory, two addresses are read per cycle to increase bandwidth
+// and reduce latency, i.e. 8 coeffs are processed per cycle, and 8 check units are instantiated
+
+// Once the norm_check_done is asserted, the invalid flag needs to be latched at the top level
+// for future use in signing algo. Assuming it takes 1 cycle to latch the value, ready is asserted 1 cycle later
+// to let HLC know that norm_check operation is done for that vector and next one can be queued
+// TODO: see if this needs any changes
+
+// TODO: embed z and r0 checks in decompose?
+// TODO: need a restart input (other than zeroize)
+
+module norm_check_top
+    import mldsa_params_pkg::*;
+    import norm_check_defines_pkg::*;
+    #(
+        parameter MLDSA_N = 256
+    )
+    (
+        input wire clk,
+        input wire reset_n,
+        input wire zeroize,
+
+        input wire norm_check_enable,
+        input chk_norm_mode_t mode,
+
+        input wire shuffling_enable,
+        input wire [5:0] randomness,
+
+        input wire [MLDSA_MEM_ADDR_WIDTH-1:0] mem_base_addr,
+        output mem_if_t mem_rd_req,
+        input [4*REG_SIZE-1:0] mem_rd_data,
+        output logic invalid,
+        output logic norm_check_ready,
+        output logic norm_check_done
+    );
+
+    logic [3:0] check_a_invalid;
+    logic check_enable, check_enable_reg;
+    logic norm_check_done_int;
+    logic latched_shuffling_enable;
+    logic randomness_enable;
+    logic [5:0] controller_randomness;
+
+    
+    assign randomness_enable = latched_shuffling_enable | shuffling_enable;
+    assign controller_randomness = randomness_enable ? randomness: '0;
+
+    generate 
+        for (genvar i = 0; i < 4; i++) begin
+            norm_check check_inst (
+                .enable(check_enable_reg),
+                .mode(mode),
+                .opa_i(mem_rd_data[(REG_SIZE-2)+(i*REG_SIZE):i*REG_SIZE]),
+                .invalid(check_a_invalid[i])
+            );
+        end
+    endgenerate
+
+    always_ff @(posedge clk or negedge reset_n) begin
+        if (!reset_n)
+            norm_check_done <= 'b0;
+        else if (zeroize)
+            norm_check_done <= 'b0;
+        else
+            norm_check_done <= norm_check_done_int;
+    end
+
+    always_ff @(posedge clk or negedge reset_n) begin
+        if  (!reset_n) 
+            invalid <= 'b0;
+        else if (zeroize | norm_check_done) 
+            invalid <= 'b0;
+        else 
+            invalid <= invalid | (|check_a_invalid);// |  (|check_b_invalid);
+    end
+
+    //Delay flops
+    //Give one cycle for HLC to capture invalid flag
+    always_ff @(posedge clk or negedge reset_n) begin
+        if (!reset_n)  begin
+            norm_check_ready         <= 'b0;
+            check_enable_reg         <= 'b0;
+            latched_shuffling_enable <= 'b0;
+        end
+        else if (zeroize)  begin
+            norm_check_ready         <= 'b0;
+            check_enable_reg         <= 'b0;
+            latched_shuffling_enable <= 'b0;
+        end
+        else  begin
+            norm_check_ready         <= norm_check_done;
+            check_enable_reg         <= check_enable;
+            if (norm_check_enable)
+                latched_shuffling_enable <= shuffling_enable;
+            else if  (norm_check_done)
+                latched_shuffling_enable <= 'b0;
+        end
+
+    end
+
+    norm_check_ctrl
+    norm_check_ctrl_inst (
+        .clk(clk),
+        .reset_n(reset_n),
+        .zeroize(zeroize),
+        .norm_check_enable(norm_check_enable),
+        .randomness(controller_randomness),
+        .mode(mode),
+        .mem_base_addr(mem_base_addr),
+        .mem_rd_req(mem_rd_req),
+        .norm_check_done(norm_check_done_int),
+        .check_enable(check_enable)
+    );
+
+
+endmodule

snapshots/chipsalliance_adams-bridge_pr66/src/norm_check/stimulus/tests/directed/norm_check_normal_test.yml

@@ -0,0 +1,21 @@
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+---
+# plusargs:
+#   - +ECC_TEST_VECTOR_FILE='${CALIPTRA_ROOT}/src/ecc/tb/test_vectors/ecc_drbg_mbedtls.hex'
+#   - +ECC_TEST='ECC_normal_test'
+
+testname: norm_check_normal_test
+seed: 1

snapshots/chipsalliance_adams-bridge_pr66/src/norm_check/tb/norm_check_tb.sv

@@ -0,0 +1,482 @@
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+//======================================================================
+//
+// norm_check_tb.sv
+// --------
+// 
+//
+//
+//======================================================================
+
+`default_nettype none
+
+module norm_check_tb
+  import mldsa_params_pkg::*;
+    import norm_check_defines_pkg::*;
+#(
+    parameter NUM_WR = 4,
+    parameter NUM_RD = 4,
+    parameter BUFFER_DATA_W = 8
+)
+();
+
+parameter CLK_HALF_PERIOD = 5;
+parameter CLK_PERIOD      = 2 * CLK_HALF_PERIOD;
+
+parameter MLDSA_Q = 8380417;
+parameter MLDSA_ETA = 2;
+parameter MLDSA_TAU = 60;
+parameter MLDSA_GAMMA1 = 2**19;
+parameter MLDSA_GAMMA2 = (MLDSA_Q -1)/32;
+parameter MLDSA_BETA = MLDSA_TAU * MLDSA_ETA;
+
+parameter Z_BOUND = MLDSA_GAMMA1 - MLDSA_BETA;
+parameter R0_BOUND = MLDSA_GAMMA2 - MLDSA_BETA;
+parameter CT0_BOUND = MLDSA_GAMMA2;
+
+//----------------------------------------------------------------
+// Register and Wire declarations.
+//----------------------------------------------------------------
+reg           clk_tb;
+reg           reset_n_tb;
+reg           zeroize_tb;
+reg           en_tb;
+reg           shuffling_enable_tb;
+reg           [5:0] randomness_tb;
+reg [MLDSA_MEM_ADDR_WIDTH-1:0] src_base_tb;
+wire invalid_tb;
+wire norm_check_done_tb;
+chk_norm_mode_t mode_tb;
+
+parameter NUM_OF_COEFF = 256 * 7; // Adjust as per your design
+parameter NUM_OF_MEM_WORDS = NUM_OF_COEFF / 4;
+reg [3:0][REG_SIZE-1:0] input_mem [0:NUM_OF_MEM_WORDS-1];
+
+mem_if_t mem_rd_req_tb;
+reg [3:0][REG_SIZE-1:0] mem_rd_data_tb;
+
+int mem_word_index;
+
+generate
+    genvar k;
+    for (k = 0; k < 4; k = k +1) begin : mem_blocks
+        normcheck_dual_port_memory #(
+            .ADDR_WIDTH(MLDSA_MEM_ADDR_WIDTH),
+            .DATA_WIDTH(REG_SIZE),
+            .DEPTH(NUM_OF_MEM_WORDS)
+        )
+        input_memory (
+            .clk(clk_tb),
+            .addr_a(mem_rd_req_tb.addr),
+            .data_in_a(24'h0),
+            .we_a(1'b0),
+            .data_out_a(mem_rd_data_tb[k]),
+            .addr_b('0), // Unused
+            .data_in_b(24'h0),
+            .we_b(1'b0),
+            .data_out_b()
+        );
+    end
+endgenerate
+
+norm_check_top dut(
+    .clk(clk_tb),
+    .reset_n(reset_n_tb),
+    .zeroize(zeroize_tb),
+    .norm_check_enable(en_tb),
+    .shuffling_enable(shuffling_enable_tb),
+    .randomness(randomness_tb),
+    .mode(mode_tb),
+    .mem_base_addr(src_base_tb),
+    .mem_rd_req(mem_rd_req_tb),
+    .mem_rd_data(mem_rd_data_tb),
+    .invalid(invalid_tb),
+    .norm_check_ready(),
+    .norm_check_done(norm_check_done_tb)
+);
+
+//----------------------------------------------------------------
+// clk_gen
+//----------------------------------------------------------------
+always
+begin : clk_gen
+  #CLK_HALF_PERIOD;
+  clk_tb = !clk_tb;
+end // clk_gen
+
+task init_sim;
+    begin
+        $display("Start of init\n");
+        clk_tb = 0;
+        reset_n_tb = 0;
+        zeroize_tb = 0;
+        en_tb = 0;
+        src_base_tb = 'h0;
+        shuffling_enable_tb = '0;
+    end
+endtask
+
+//----------------------------------------------------------------
+// reset_dut()
+//----------------------------------------------------------------
+task reset_dut;
+    begin
+      $display("*** Toggle reset.");
+      reset_n_tb = 0;
+
+      #(2 * CLK_PERIOD);
+      reset_n_tb = 1;
+      #(2 * CLK_PERIOD);
+
+      $display("End of reset");
+    end
+endtask // reset_dut
+
+task overwrite_memory_content(input reg [MLDSA_MEM_ADDR_WIDTH-1:0] src_base_addr);
+    int i;
+    for (i = 0; i < 64; i = i + 1) begin
+        mem_blocks[0].input_memory.mem[i+src_base_addr] = input_mem[i][0];
+        mem_blocks[1].input_memory.mem[i+src_base_addr] = input_mem[i][1];
+        mem_blocks[2].input_memory.mem[i+src_base_addr] = input_mem[i][2];
+        mem_blocks[3].input_memory.mem[i+src_base_addr] = input_mem[i][3];
+    end
+endtask
+
+task z_bound_norm_check_test;
+  // Z_BOUND Test
+  $display("Z bound mode\n");
+  mode_tb = z_bound;
+  src_base_tb = 'h0;
+
+  mem_word_index = 0;
+  for (int i = 0; i < 64; i++) begin
+    input_mem[mem_word_index][0] = REG_SIZE'($urandom_range(0,Z_BOUND-1));
+    input_mem[mem_word_index][1] = REG_SIZE'($urandom_range(MLDSA_Q-Z_BOUND, MLDSA_Q-1));
+    input_mem[mem_word_index][2] = REG_SIZE'($urandom_range(0,Z_BOUND));
+    input_mem[mem_word_index][3] = REG_SIZE'($urandom_range(0,Z_BOUND));
+    mem_word_index = mem_word_index + 1;
+  end
+  overwrite_memory_content(src_base_tb);
+  @(negedge clk_tb);
+  en_tb = 1'b1;
+  @(posedge clk_tb);
+  @(negedge clk_tb);
+  en_tb = 1'b0;
+
+  repeat (2) @(posedge clk_tb);
+
+  wait (norm_check_done_tb);
+  if (invalid_tb) $error("Expected z check to be valid, received invalid\n");
+  else $display("Norm check for z is successful\n");
+endtask
+
+task r0_bound_norm_check_test;
+  //R0_BOUND Test
+  $display("r0 bound mode\n");
+  mode_tb = r0_bound;
+  src_base_tb = 'h40;
+
+  mem_word_index = 0;
+  for (int i = 0; i < 64; i++) begin
+    input_mem[mem_word_index][0] = REG_SIZE'($urandom_range(MLDSA_Q-R0_BOUND, MLDSA_Q-1));
+    input_mem[mem_word_index][1] = REG_SIZE'($urandom_range(MLDSA_Q-R0_BOUND, MLDSA_Q-1));
+    input_mem[mem_word_index][2] = REG_SIZE'($urandom_range(MLDSA_Q-R0_BOUND, MLDSA_Q-1));
+    input_mem[mem_word_index][3] = REG_SIZE'($urandom_range(MLDSA_Q-R0_BOUND, MLDSA_Q-1));
+    mem_word_index = mem_word_index + 1;
+  end
+  overwrite_memory_content(src_base_tb);
+  @(negedge clk_tb);
+  en_tb = 1'b1;
+  @(posedge clk_tb);
+  @(negedge clk_tb);
+  en_tb = 1'b0;
+  repeat (2) @(posedge clk_tb);
+
+  wait (norm_check_done_tb);
+  if (invalid_tb) $error("Expected r0 check to be valid, received invalid\n");
+  else $display("Norm check for r0 is successful\n");
+
+endtask
+
+task ct0_bound_norm_check_test;
+  // CT0_BOUND Test
+  $display("ct0 bound mode\n");
+  mode_tb = ct0_bound;
+  src_base_tb = 'h80;
+
+  mem_word_index = '0;
+  for (int i = 0; i < 64; i++) begin
+    input_mem[mem_word_index][0] = REG_SIZE'($urandom_range(0,CT0_BOUND-1));
+    input_mem[mem_word_index][1] = REG_SIZE'($urandom_range(0,CT0_BOUND-1));
+    input_mem[mem_word_index][2] = REG_SIZE'($urandom_range(0,CT0_BOUND-1));
+    input_mem[mem_word_index][3] = REG_SIZE'($urandom_range(0,CT0_BOUND-1));
+    mem_word_index = mem_word_index + 1;
+  end
+  overwrite_memory_content(src_base_tb);
+  @(negedge clk_tb);
+  en_tb = 1'b1;
+  @(posedge clk_tb);
+  @(negedge clk_tb);
+  en_tb = 1'b0;
+  repeat (2) @(posedge clk_tb);
+
+  wait (norm_check_done_tb);
+  if (invalid_tb) $error("Expected r0 check to be valid, received invalid\n");
+  else $display("Norm check for r0 is successful\n");
+
+endtask
+
+task rejected_ct0_bound_norm_check_test;
+  // Rejected Test
+  $display("Rejected test for ct0 bound mode\n");
+  mode_tb = ct0_bound;
+  src_base_tb = 'hC0;
+
+  mem_word_index = 0;
+  for (int poly = 0; poly < 8; poly++) begin
+      $display("Starting poly %0d", poly);
+      for (int i = 0; i < 32; i++) begin
+          input_mem[mem_word_index][0] = REG_SIZE'($urandom_range(0,CT0_BOUND-1));
+          input_mem[mem_word_index][1] = REG_SIZE'($urandom_range(0,CT0_BOUND-1));
+          input_mem[mem_word_index][2] = REG_SIZE'($urandom_range(0,CT0_BOUND-1));
+          input_mem[mem_word_index][3] = REG_SIZE'($urandom_range(CT0_BOUND,MLDSA_Q-1));
+          mem_word_index = mem_word_index + 1;
+      end
+  end
+  overwrite_memory_content(src_base_tb);
+  @(negedge clk_tb);
+  en_tb = 1'b1;
+  @(posedge clk_tb);
+  @(negedge clk_tb);
+  en_tb = 1'b0;
+  repeat (2) @(posedge clk_tb);
+
+  @(posedge clk_tb);
+  wait (norm_check_done_tb);
+  if (invalid_tb) $display("Norm check for ct0 is rejected as expected\n");
+  else $error("Expected ct0 check to be invalid, received valid\n");
+
+endtask
+
+task rejected_z_bound_norm_check_test;
+  // Z_BOUND Test
+  $display("Z bound mode\n");
+  mode_tb = z_bound;
+  src_base_tb = 'h0;
+
+  mem_word_index = 0;
+  for (int i = 0; i < 64; i++) begin
+    input_mem[mem_word_index][0] = REG_SIZE'($urandom_range(0,Z_BOUND-1));
+    input_mem[mem_word_index][1] = REG_SIZE'($urandom_range(MLDSA_Q-Z_BOUND, MLDSA_Q-1));
+    input_mem[mem_word_index][2] = REG_SIZE'($urandom_range(0,Z_BOUND));
+    if (i==63) begin
+      input_mem[mem_word_index][3] = REG_SIZE'($urandom_range(Z_BOUND,MLDSA_Q-Z_BOUND));
+    end 
+    else begin
+      input_mem[mem_word_index][3] = REG_SIZE'($urandom_range(0,Z_BOUND));
+    end
+    mem_word_index = mem_word_index + 1;
+  end
+  overwrite_memory_content(src_base_tb);
+  @(negedge clk_tb);
+  en_tb = 1'b1;
+  @(posedge clk_tb);
+  @(negedge clk_tb);
+  en_tb = 1'b0;
+
+  repeat (2) @(posedge clk_tb);
+
+  wait (norm_check_done_tb);
+  if (invalid_tb) $display("Norm check for z is rejected as expected\n");
+  else $error("Expected z check to be invalid, received valid\n");
+endtask
+
+task rejected_r0_bound_norm_check_test;
+  //R0_BOUND Test
+  $display("r0 bound mode\n");
+  mode_tb = r0_bound;
+  src_base_tb = 'h40;
+
+  mem_word_index = 0;
+  for (int i = 0; i < 64; i++) begin
+    if (i==0)
+      input_mem[mem_word_index][0] = REG_SIZE'($urandom_range(0, MLDSA_Q-R0_BOUND-1));
+    else
+      input_mem[mem_word_index][0] = REG_SIZE'($urandom_range(MLDSA_Q-R0_BOUND, MLDSA_Q-1));
+    input_mem[mem_word_index][1] = REG_SIZE'($urandom_range(MLDSA_Q-R0_BOUND, MLDSA_Q-1));
+    input_mem[mem_word_index][2] = REG_SIZE'($urandom_range(MLDSA_Q-R0_BOUND, MLDSA_Q-1));
+    input_mem[mem_word_index][3] = REG_SIZE'($urandom_range(MLDSA_Q-R0_BOUND, MLDSA_Q-1));
+    mem_word_index = mem_word_index + 1;
+  end
+  overwrite_memory_content(src_base_tb);
+  @(negedge clk_tb);
+  en_tb = 1'b1;
+  @(posedge clk_tb);
+  @(negedge clk_tb);
+  en_tb = 1'b0;
+  repeat (2) @(posedge clk_tb);
+
+  wait (norm_check_done_tb);
+  if (invalid_tb) $display("Norm check for r0 is rejected as expected\n");
+  else $error("Expected r0 check to be invalid, received valid\n");
+
+endtask
+
+task randomized_rejected_r0_bound_norm_check_test;
+  //R0_BOUND Test
+  int inner_index;
+  mode_tb = r0_bound;
+  src_base_tb = $urandom_range(0, 127);
+  repeat (3) @(posedge clk_tb);
+
+  mem_word_index = 0;
+  for (int i = 0; i < 64; i++) begin
+    input_mem[mem_word_index][0] = REG_SIZE'($urandom_range(MLDSA_Q-R0_BOUND, MLDSA_Q-1));
+    input_mem[mem_word_index][1] = REG_SIZE'($urandom_range(MLDSA_Q-R0_BOUND, MLDSA_Q-1));
+    input_mem[mem_word_index][2] = REG_SIZE'($urandom_range(MLDSA_Q-R0_BOUND, MLDSA_Q-1));
+    input_mem[mem_word_index][3] = REG_SIZE'($urandom_range(MLDSA_Q-R0_BOUND, MLDSA_Q-1));
+    mem_word_index = mem_word_index + 1;
+  end
+  mem_word_index = $urandom_range(0, 63);
+  inner_index = $urandom_range(0, 3);
+  input_mem[mem_word_index][inner_index] = REG_SIZE'($urandom_range(R0_BOUND, MLDSA_Q-R0_BOUND-1));
+
+  overwrite_memory_content(src_base_tb);
+  @(negedge clk_tb);
+  en_tb = 1'b1;
+  @(posedge clk_tb);
+  @(negedge clk_tb);
+  en_tb = 1'b0;
+  repeat (2) @(posedge clk_tb);
+
+  wait (norm_check_done_tb);
+  if (!invalid_tb) begin
+    $display("The incorrect range (%x) is inserted in %d and %d\n",input_mem[mem_word_index][inner_index], mem_word_index, inner_index );
+    $error("Expected r0 check to be invalid, received valid at %t\n", $time);
+  end
+
+endtask
+
+task randomized_ct0_bound_norm_check_test;
+  // CT0_BOUND Test
+  mode_tb = ct0_bound;
+  src_base_tb = $urandom_range(0, 127);
+  repeat (3) @(posedge clk_tb);
+
+  mem_word_index = '0;
+  for (int i = 0; i < 64; i++) begin
+    input_mem[mem_word_index][0] = REG_SIZE'($urandom_range(0,CT0_BOUND-1));
+    input_mem[mem_word_index][1] = REG_SIZE'($urandom_range(0,CT0_BOUND-1));
+    input_mem[mem_word_index][2] = REG_SIZE'($urandom_range(0,CT0_BOUND-1));
+    input_mem[mem_word_index][3] = REG_SIZE'($urandom_range(0,CT0_BOUND-1));
+    mem_word_index = mem_word_index + 1;
+  end
+  overwrite_memory_content(src_base_tb);
+  @(negedge clk_tb);
+  en_tb = 1'b1;
+  @(posedge clk_tb);
+  @(negedge clk_tb);
+  en_tb = 1'b0;
+  repeat (2) @(posedge clk_tb);
+
+  wait (norm_check_done_tb);
+  if (invalid_tb) $error("Expected r0 check to be valid, received invalid\n");
+
+endtask
+
+task norm_check_test;
+    $display("Starting check norm ctrl test\n");
+    z_bound_norm_check_test();
+    repeat (2) @(posedge clk_tb);
+    r0_bound_norm_check_test();
+    repeat (2) @(posedge clk_tb);
+    ct0_bound_norm_check_test();
+    repeat (2) @(posedge clk_tb);
+    rejected_ct0_bound_norm_check_test();
+    repeat (2) @(posedge clk_tb);
+    rejected_z_bound_norm_check_test();
+    repeat (2) @(posedge clk_tb);
+    rejected_r0_bound_norm_check_test();
+    repeat (10000) randomized_rejected_r0_bound_norm_check_test();
+    repeat (10000) randomized_ct0_bound_norm_check_test();
+    $display("Ctrl test done\n");
+endtask
+
+initial begin
+  fork
+    begin
+      init_sim();
+      reset_dut();
+      shuffling_enable_tb = '0;
+      norm_check_test();
+      shuffling_enable_tb = '1;
+      norm_check_test();
+    end
+    begin
+      while(1) begin
+        @(posedge clk_tb);
+        randomness_tb =  $urandom_range(0,64);
+      end
+    end
+  join_any
+    $finish;
+end
+
+endmodule
+
+// Memory module definition (normcheck_dual_port_memory)
+module normcheck_dual_port_memory
+#(
+    parameter ADDR_WIDTH = 15,
+    parameter DATA_WIDTH = 32,
+    parameter DEPTH = 256
+)
+(
+    input wire clk,
+    
+    // Port A
+    input wire [ADDR_WIDTH-1:0] addr_a,
+    input wire [DATA_WIDTH-1:0] data_in_a,
+    input wire we_a,  // Write enable for port A
+    output reg [DATA_WIDTH-1:0] data_out_a,
+
+    // Port B (Unused in this testbench)
+    input wire [ADDR_WIDTH-1:0] addr_b,
+    input wire [DATA_WIDTH-1:0] data_in_b,
+    input wire we_b,  // Write enable for port B
+    output reg [DATA_WIDTH-1:0] data_out_b
+);
+
+    // Memory array
+    reg [DATA_WIDTH-1:0] mem [0:DEPTH-1];
+
+    // Port A logic
+    always @(posedge clk) begin
+        if (we_a) begin
+            mem[addr_a] <= data_in_a;
+        end
+        data_out_a <= mem[addr_a];
+    end
+
+    // Port B logic (Unused)
+    always @(posedge clk) begin
+        if (we_b) begin
+            mem[addr_b] <= data_in_b;
+        end
+        data_out_b <= mem[addr_b];
+    end
+
+endmodule

snapshots/chipsalliance_adams-bridge_pr66/src/rej_sampler/stimulus/tests/directed/rej_rand_test.yml

@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+---
+testname: rej_rand_test
+seed: 1 #${PLAYBOOK_RANDOM_SEED}

snapshots/chipsalliance_adams-bridge_pr66/src/rej_sampler/tb/rej_sampler.py

@@ -0,0 +1,106 @@
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+import sys
+import os
+import binascii
+from hashlib import shake_128, shake_256
+
+DILITHIUM_Q = 8380417 # 2**23 - 2**13 + 1
+DILITHIUM_N = 256
+DILITHIUM_LOGN = 8
+DILITHIUM_ROOT_OF_UNITY = 1753
+
+## Category 5 parameters:
+DILITHIUM_ETA = 2
+DILITHIUM_ETA_BOUND = 15
+DILITHIUM_TAU = 60
+DILITHIUM_GAMMA1 = 2**19
+
+
+class Shake():
+    def __init__(self, algorithm, block_length):
+        self.algorithm    = algorithm
+        self.block_length = block_length
+        self.read_blocks  = 0
+        self.read_data    = b""
+        
+    def absorb(self, input_bytes):
+        self.read_blocks  = 0
+        self.read_data    = b""
+        self.xof = self.algorithm(input_bytes)
+        
+    def digest(self, input_bytes, length):
+        return self.algorithm(input_bytes).digest(length)
+        
+    def get_n_blocks(self, n):
+        byte_count = self.block_length * (self.read_blocks + n)
+        xof_data   = self.xof.digest(byte_count)
+        self.read_blocks += n
+        self.read_data = xof_data[-self.block_length*n:]
+    
+    def read(self, n):
+        if n > len(self.read_data):
+            self.get_n_blocks(5*n)
+        send = self.read_data[:n]
+        self.read_data = self.read_data[n:]
+        return send
+
+Shake128 = Shake(shake_128, 168)
+Shake256 = Shake(shake_256, 136)
+
+def rejection_q(seed):
+    global DILITHIUM_Q
+    global DILITHIUM_N
+    global buff_arr
+
+    def rejection_sample(xof):
+        global buff_arr
+        while True:    
+            if (len(buff_arr) == 0):
+                log_file.write("squeezing\n")
+                buff_bytes = xof.read(168)
+                buff_arr = bytearray(buff_bytes)
+                buff_int = int.from_bytes(buff_bytes, "little")
+                input_vectors.write(f"{buff_int:0336x}")
+            j_bytes = buff_arr[0:3]
+            for i in range (3):
+                buff_arr.pop(0)
+            j = int.from_bytes(j_bytes, "little")
+            j &= 0x7FFFFF
+            if j < DILITHIUM_Q:
+                log_file.write("ack: " + f"{j:06x}" + "\n")
+                return j
+            log_file.write("rej: " + f"{j:06x}" + "\n")
+
+    # Initialise the XOF
+    Shake128.absorb(seed)
+    buff_arr = bytearray()
+    coeffs = [rejection_sample(Shake128) for _ in range(DILITHIUM_N)]
+    input_vectors.write("\n")
+    log_file.write("\n")
+    return coeffs
+
+#open the input vector file for reading
+input_seeds = open("input_seeds.txt", "r")
+input_vectors = open("input_vectors.txt", "w")
+exp_results = open("exp_results.txt", "w")
+log_file = open("rej_sampler.log", "w")
+Lines = input_seeds.readlines()
+
+for line in Lines:
+    Coeffs = rejection_q( bytes(line.strip(),'utf-8') )
+    for coeff in Coeffs:
+        exp_results.write(f"{coeff:06x}"+" ")
+    exp_results.write("\n")

snapshots/chipsalliance_adams-bridge_pr66/src/rej_sampler/tb/rej_sampler_tb.sv

@@ -0,0 +1,439 @@
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+//======================================================================
+//
+// rej_sampler_tb.sv
+// --------
+//
+//======================================================================
+
+import "DPI-C" function string getenv(input string env_name);
+
+module rej_sampler_tb
+  import mldsa_sampler_pkg::*;
+  import mldsa_params_pkg::*;
+(
+`ifdef VERILATOR
+  input bit clk_tb
+`endif
+  );
+
+  parameter REJ_NUM_SAMPLERS = 5;
+  parameter REJ_SAMPLE_W     = 24;
+  parameter REJ_VLD_SAMPLES  = 4;
+  parameter PISO_BUFFER_W    = 1440;
+  parameter PISO_INPUT_RATE  = 1344;
+  parameter PISO_OUTPUT_RATE = 120;
+  parameter MLDSA_Q = 8380417;
+  parameter MLDSA_Q_WIDTH = $clog2(MLDSA_Q) + 1;
+  parameter MLDSA_N = 256;
+
+
+  `ifndef VERILATOR
+  int MAX_CYCLES;
+  int VEC_CNT;
+
+  initial begin
+    // To use this from the command line, add "+MAX_CYCLES=<value>"
+    // to override the sim timeout
+    if ($value$plusargs("MAX_CYCLES=%d", MAX_CYCLES)) begin
+      $info("Received argument +MAX_CYCLES, with value %d", MAX_CYCLES);
+    end else begin
+      MAX_CYCLES = 20_0000;
+      $info("No argument provided for MAX_CYCLES, defaulting to %d", MAX_CYCLES);
+    end
+    if ($value$plusargs("VEC_CNT=%d", VEC_CNT)) begin
+      $info("Received argument +VEC_CNT, with value %d", VEC_CNT);
+    end else begin
+      VEC_CNT = 10;
+      $info("No argument provided for VEC_CNT, defaulting to %d", VEC_CNT);
+    end
+  end
+  `else
+  parameter MAX_CYCLES = 20_0000;
+  `endif
+
+  parameter DEBUG = 0;
+
+  parameter CLK_HALF_PERIOD = 5;
+
+  //input data to piso
+  logic                                          data_valid_i;
+  logic                                          data_hold_o;
+  logic [PISO_INPUT_RATE-1:0]                    data_i;
+
+  //input data
+  logic                                          piso_valid;
+  logic                                          piso_hold;
+  logic [REJ_NUM_SAMPLERS-1:0][REJ_SAMPLE_W-1:0] piso_data;
+
+  //output data
+  logic                                         data_valid_o;
+  logic [REJ_VLD_SAMPLES-1:0][MLDSA_Q_WIDTH-1:0] data_o;
+
+  logic zeroize;
+
+  //----------------------------------------------------------------
+  // Register and Wire declarations.
+  //----------------------------------------------------------------
+  reg [31 : 0] cycle_ctr;
+  reg [31 : 0] error_ctr;
+  reg [31 : 0] vld_coeff_ctr;
+  reg [31 : 0] tc_ctr;
+
+`ifndef VERILATOR
+  reg clk_tb;
+`endif
+  reg clk_i;
+  reg reset_n_tb;
+  reg rst_ni;
+  reg [31 : 0] read_data;
+
+  assign clk_i = clk_tb;
+  assign rst_ni = reset_n_tb;
+
+  logic [MLDSA_Q_WIDTH-1:0] exp_result;
+  logic [MLDSA_Q_WIDTH-1:0] expected_results[$];  // queue of results
+
+  string seed_filename, vector_filename, exp_res_filename;
+  assign exp_res_filename = "exp_results.txt";
+  assign seed_filename = "input_seeds.txt";
+  assign vector_filename = "input_vectors.txt";
+
+  int fd_r_exp;
+
+  //----------------------------------------------------------------
+  // Device Under Test.
+  //----------------------------------------------------------------
+  abr_piso #(
+    .PISO_BUFFER_W(PISO_BUFFER_W),
+    .PISO_INPUT_RATE(PISO_INPUT_RATE),
+    .PISO_OUTPUT_RATE(PISO_OUTPUT_RATE)
+ ) piso_i (
+ .clk(clk_i),
+ .rst_b(rst_ni),
+ .zeroize(zeroize),
+ .valid_i(data_valid_i),
+ .hold_o(data_hold_o),
+ .data_i(data_i),
+ .valid_o(piso_valid),
+ .hold_i(piso_hold),
+ .data_o(piso_data)
+ );
+
+  rej_sampler_ctrl#(
+    .REJ_NUM_SAMPLERS(REJ_NUM_SAMPLERS),
+    .REJ_SAMPLE_W(REJ_SAMPLE_W),
+    .REJ_VLD_SAMPLES(REJ_VLD_SAMPLES),
+    .REJ_VALUE(MLDSA_Q)
+  ) dut (
+  .clk(clk_i),
+  .rst_b(rst_ni),
+  .zeroize(zeroize), 
+  //input data
+  .data_valid_i(piso_valid),
+  .data_hold_o(piso_hold),
+  .data_i(piso_data),
+
+  //output data
+  .data_valid_o(data_valid_o),
+  .data_o(data_o)
+  );
+
+  //----------------------------------------------------------------
+  // clk_gen
+  //
+  // Clock generator process.
+  //----------------------------------------------------------------
+`ifndef VERILATOR
+  always
+    begin : clk_gen
+      #CLK_HALF_PERIOD
+      clk_tb = !clk_tb;
+    end // clk_gen
+`endif
+
+  //----------------------------------------------------------------
+  // sys_monitor
+  //
+  // Generates a cycle counter and displays information about
+  // the dut as needed.
+  //----------------------------------------------------------------
+  always @(posedge clk_tb) begin : sys_monitor
+      cycle_ctr = (!reset_n_tb) ? 32'h0 : cycle_ctr + 1;
+
+      // Test timeout monitor
+      if(cycle_ctr == MAX_CYCLES) begin
+        $error("Hit max cycle count (%0d) .. stopping",cycle_ctr);
+        $finish;
+      end
+    end
+
+  //----------------------------------------------------------------
+  // reset_dut()
+  //
+  // Toggles reset to force the DUT into a well defined state.
+  //----------------------------------------------------------------
+  task reset_dut;
+    begin
+      $display("*** Toggle reset.");
+      reset_n_tb = 0;
+
+      repeat (2) @(posedge clk_tb);
+      reset_n_tb = 1;
+
+      repeat (2) @(posedge clk_tb);
+
+      $display("");
+    end
+  endtask // reset_dut
+
+  //----------------------------------------------------------------
+  // init_sim()
+  //
+  // Initialize all counters and testbed functionality as well
+  // as setting the DUT inputs to defined values.
+  //----------------------------------------------------------------
+  task init_sim;
+    begin
+      error_ctr     = '0;
+      tc_ctr        = '0;
+      vld_coeff_ctr = '0;
+`ifndef VERILATOR
+      clk_tb        = 0;
+`endif
+      reset_n_tb    = 0;
+
+      zeroize       = 0;
+      data_valid_i  = '0;
+      data_i        = '0;
+
+    end
+  endtask // init_dut
+
+  //----------------------------------------------------------------
+  // display_test_result()
+  //
+  // Display the accumulated test results.
+  //----------------------------------------------------------------
+  task display_test_result;
+    begin
+      if (error_ctr == 0)
+        begin
+          $display("*** All %02d test cases completed successfully.", tc_ctr);
+          $display("* TESTCASE PASSED");
+        end
+      else
+        begin
+          $display("*** %02d test cases completed.", tc_ctr);
+          $display("*** %02d errors detected during testing.", error_ctr);
+          $display("* TESTCASE FAILED");
+        end
+    end
+  endtask // display_test_result
+
+  //----------------------------------------------------------------
+  // Scoreboard 
+  //----------------------------------------------------------------
+  initial begin
+    forever begin
+      @(posedge clk_tb)
+      if (data_valid_o) begin
+        if (expected_results.size() >= 4) begin
+          for (int i = 0; i < REJ_VLD_SAMPLES; i++) begin
+            vld_coeff_ctr += 1; //increment vld coeff ctr
+            if (expected_results[0] != data_o[i]) begin
+              //ERROR
+              $display("[%t] Expected results mismatch for output index %d", $time, i);
+              $display("[%t] Actual:   %x", $time,data_o[i]);
+              $display("[%t] Expected: %x", $time,expected_results[0]);
+              error_ctr += 1;
+            end
+            expected_results.pop_front();
+          end
+        end else begin
+          //ERROR
+          $display("[%t] Not enough valid samples in the queue", $time);
+          error_ctr += 1;
+        end
+      end
+    end
+
+  end
+
+  initial begin
+    forever begin
+      @(posedge clk_tb)
+      if (vld_coeff_ctr == 256) begin
+        zeroize <= 1;
+        @(posedge clk_tb)
+        zeroize <= 0;
+      end
+    end
+  end
+
+  initial begin
+    forever begin
+      @(posedge zeroize)
+          vld_coeff_ctr = '0;
+          expected_results = {};
+    end
+  end
+
+  //----------------------------------------------------------------
+  // write_single_msg()
+  //
+  // Write the given msg to the DUT using the DUT interface.
+  //----------------------------------------------------------------
+  task write_single_msg(logic [PISO_INPUT_RATE-1:0] rand_samples);
+    begin
+      data_valid_i <= 1;
+      data_i       <= rand_samples;
+
+      //don't like this, but solves the timing issue
+      @(posedge clk_tb);
+      //Make sure no hold
+      //drop this transaction if zeroize is set
+      while ((data_hold_o == 1) & (zeroize == 0)) @(posedge clk_tb);
+
+      //@(posedge clk_tb);
+      data_valid_i <= 0;
+      data_i       <= 'x;
+
+    end
+  endtask // write_single_msg
+
+  //----------------------------------------------------------------
+  // gen_rand_test_vectors()
+  //----------------------------------------------------------------
+  task gen_rand_test_vectors;
+    int fd_w;
+
+    fd_w = $fopen(seed_filename, "a");
+    if (fd_w == 0) $error("Cannot open file %s for writing", seed_filename);
+    
+    for (int i = 0; i < VEC_CNT; i++) begin
+      //Write random_ eeds
+      $fwrite(fd_w, "%0d \n", $urandom());
+    end
+    $fclose(fd_w);
+    //generate input vectors and expected results
+    $system($sformatf("python rej_sampler.py"));
+
+
+    //open expected results files
+    fd_r_exp = $fopen(exp_res_filename, "r");
+    if (fd_r_exp == 0) begin
+      $error("Cannot open file %s for reading", exp_res_filename);
+      error_ctr++;
+    end
+
+  endtask
+
+
+  //----------------------------------------------------------------
+  // run_rand_test()
+  //----------------------------------------------------------------
+  parameter PISO_INPUT_CHARS = PISO_INPUT_RATE/4;
+  parameter PISO_INPUT_DWORDS = PISO_INPUT_RATE/32;
+  task run_rand_test;
+    int fd_r_inp;
+    string line_read;
+    string line_substr;
+    int num_states;
+    logic [PISO_INPUT_DWORDS-1:0][31:0] test_data;
+
+    //open input vectors
+    fd_r_inp = $fopen(vector_filename, "r");
+    if (fd_r_inp == 0) begin
+      $error("Cannot open file %s for reading", vector_filename);
+      error_ctr++;
+    end
+
+    //open expected results files
+    fd_r_exp = $fopen(exp_res_filename, "r");
+    if (fd_r_exp == 0) begin
+      $error("Cannot open file %s for reading", exp_res_filename);
+      error_ctr++;
+    end
+
+    for (int iter = 0; iter < VEC_CNT; iter++) begin
+      //get the next exp result
+      if (!($fgets(line_read, fd_r_exp))) begin
+        $error("Failed to read a new line");
+        error_ctr++;
+      end
+      for (int res = 0; res < MLDSA_N; res++) begin
+        exp_result = line_read.substr(res*7, res*7 + 7-2).atohex();
+        expected_results.push_back(exp_result);
+      end
+
+      //get the next input vector
+      if (!($fgets(line_read, fd_r_inp))) begin
+        $error("Failed to read a new line");
+        error_ctr++;
+      end
+
+      num_states = (line_read.len()/PISO_INPUT_CHARS);
+      //$display("Vector Length: %d", line_read.len());
+      //$display("Number of states: %d", num_states);
+      for (int state = 0; state < num_states; state++) begin
+          line_substr = line_read.substr(state*PISO_INPUT_CHARS , (state*PISO_INPUT_CHARS)+PISO_INPUT_CHARS-1);
+          //$display("State: %s", line_substr);
+          for (int dword = 0; dword < PISO_INPUT_DWORDS; dword++) begin
+            test_data[dword] = line_substr.substr((PISO_INPUT_CHARS - dword*8 - 8), (PISO_INPUT_CHARS - dword*8 - 1)).atohex();
+            //$display("Dword: %d - %h", dword, test_data[dword]);
+          end
+          write_single_msg(test_data);
+      end
+
+      wait (zeroize == 1);
+      wait (zeroize == 0);
+
+      tc_ctr++;
+
+    end
+
+    $fclose(fd_r_inp);
+
+  endtask // run_hw_if_test
+
+  //----------------------------------------------------------------
+  // The main test functionality.
+  //----------------------------------------------------------------
+
+  initial
+    begin : main
+      $write("PLAYBOOK_RANDOM_SEED = %s\n", getenv("PLAYBOOK_RANDOM_SEED"));
+      $display("   -- Testbench for REJ_SAMPLER started --");
+
+      init_sim();
+      reset_dut();
+
+      gen_rand_test_vectors();
+      run_rand_test();
+
+      @(posedge clk_tb);
+      display_test_result();
+
+      $display("   -- Testbench for REJ_SAMPLER done. --");
+      $finish;
+    end // main
+
+endmodule // rej_sampler_tb
+
+//======================================================================
+// EOF rej_sampler_tb.sv
+//======================================================================

snapshots/chipsalliance_adams-bridge_pr66/src/sk_encode/config/compile.yml

@@ -0,0 +1,37 @@
+# Copyright (C) Microsoft Corporation. All rights reserved.
+
+# Go here for details on compile.yml syntax:
+# https://dev.azure.com/ms-tsd/Ether/_git/sim-tools?path=%2FSourceFileSpec.docx&version=GBmaster
+
+---
+provides: [skencode]
+schema_version: 2.4.0
+requires:
+  - mldsa_defines
+  - skdecode_pkg
+  - abr_libs
+targets:
+  rtl:
+    directories: [$COMPILE_ROOT/rtl]
+    files:
+      - $COMPILE_ROOT/rtl/skencode.sv
+      
+    tops: [skencode]
+  rtl_lint:
+    directories: []
+    waiver_files:
+      - $MSFT_REPO_ROOT/src/sk_decode/config/design_lint/skencode/sglint_waivers
+---
+provides: [skencode_tb]
+schema_version: 2.4.0
+requires:
+  - skencode
+  - skdecode_pkg
+targets:
+  rtl:
+    directories: [$COMPILE_ROOT/tb]
+    files:
+      - $COMPILE_ROOT/tb/skencode_tb.sv
+    tops: [skencode_tb]
+  sim:
+    pre_exec: 'echo "[PRE-EXEC] Copying s1 bytes hex to $PWD" && cp $COMPILE_ROOT/tb/pack_eta.py .'

snapshots/chipsalliance_adams-bridge_pr66/src/sk_encode/config/skencode.vf

@@ -0,0 +1,36 @@
++incdir+${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl
++incdir+${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl
++incdir+${ADAMSBRIDGE_ROOT}/src/sk_decode/rtl
++incdir+${ADAMSBRIDGE_ROOT}/src/sk_encode/rtl
+${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_config_defines.svh
+${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_params_pkg.sv
+${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_reg_pkg.sv
+${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_sva.svh
+${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_macros.svh
+${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_ram.sv
+${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_be_ram.sv
+${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_512x4_ram.sv
+${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ram_regout.sv
+${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_icg.sv
+${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_2ff_sync.sv
+${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_piso_4.sv
+${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_piso.sv
+${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_sample_buffer.sv
+${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ahb_defines_pkg.sv
+${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ahb_slv_sif.sv
+${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_AND.sv
+${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_delay_masked_shares.sv
+${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_add_sub_mod_Boolean.sv
+${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_MUX.sv
+${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Boolean_sub.sv
+${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_full_adder.sv
+${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_A2B_conv.sv
+${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Boolean_adder.sv
+${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_B2A_conv.sv
+${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_mult.sv
+${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_mult_two_share.sv
+${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_adder.sv
+${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_add_sub_mod.sv
+${ADAMSBRIDGE_ROOT}/src/sk_decode/rtl/skdecode_defines_pkg.sv
+${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Arith_adder.sv
+${ADAMSBRIDGE_ROOT}/src/sk_encode/rtl/skencode.sv

snapshots/chipsalliance_adams-bridge_pr66/src/sk_encode/config/skencode_tb.vf

@@ -0,0 +1,38 @@
++incdir+${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl
++incdir+${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl
++incdir+${ADAMSBRIDGE_ROOT}/src/sk_decode/rtl
++incdir+${ADAMSBRIDGE_ROOT}/src/sk_encode/rtl
++incdir+${ADAMSBRIDGE_ROOT}/src/sk_encode/tb
+${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_config_defines.svh
+${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_params_pkg.sv
+${ADAMSBRIDGE_ROOT}/src/mldsa_top/rtl/mldsa_reg_pkg.sv
+${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_sva.svh
+${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_macros.svh
+${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_ram.sv
+${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_be_ram.sv
+${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_1r1w_512x4_ram.sv
+${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ram_regout.sv
+${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_icg.sv
+${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_2ff_sync.sv
+${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_piso_4.sv
+${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_piso.sv
+${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_sample_buffer.sv
+${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ahb_defines_pkg.sv
+${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_ahb_slv_sif.sv
+${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_AND.sv
+${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_delay_masked_shares.sv
+${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_add_sub_mod_Boolean.sv
+${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_MUX.sv
+${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Boolean_sub.sv
+${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_full_adder.sv
+${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_A2B_conv.sv
+${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Boolean_adder.sv
+${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_B2A_conv.sv
+${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_mult.sv
+${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_mult_two_share.sv
+${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_adder.sv
+${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_add_sub_mod.sv
+${ADAMSBRIDGE_ROOT}/src/sk_decode/rtl/skdecode_defines_pkg.sv
+${ADAMSBRIDGE_ROOT}/src/abr_libs/rtl/abr_masked_N_bit_Arith_adder.sv
+${ADAMSBRIDGE_ROOT}/src/sk_encode/rtl/skencode.sv
+${ADAMSBRIDGE_ROOT}/src/sk_encode/tb/skencode_tb.sv

snapshots/chipsalliance_adams-bridge_pr66/src/sk_encode/rtl/skencode.sv

@@ -0,0 +1,400 @@
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//======================================================================
+//
+// skencode.sv
+// --------
+// The skencode module performs the encoding of secret key components into a packed format. 
+// This module supports the MLDSA scheme, encoding sk inputs into s1, s2 polynomials. 
+// The output coefficients are packed into 24-bit format.
+// The design supports dual memory writes per cycle, processing 8 values per cycle for s1 and s2 encoding. 
+// The module operates under the control of a single enable pulse, triggering the encoding process for all polynomials. 
+// Upon completion, control is transferred back to the host. If any invalid input is detected, the module raises 
+// an error flag, halting the operation. Error handling and notifications are left to the host's implementation. 
+// 8 instances of the s1s2 encoder can operate simultaneously, each handling 24 bits of data per cycle.
+//
+//======================================================================
+
+module skencode
+    import mldsa_params_pkg::*;
+    import skdecode_defines_pkg::*;
+    #(
+        parameter MEM_ADDR_WIDTH = 15,
+        parameter MLDSA_Q = 23'd8380417,
+        parameter MLDSA_L = 'h7,
+        parameter MLDSA_K = 'h8,
+        parameter MLDSA_N = 'd256,
+        parameter REG_SIZE = 24,
+        parameter AHB_DATA_WIDTH = 32
+    )
+    (
+        input wire clk,
+        input wire reset_n,
+        input wire zeroize,
+        
+        input wire skencode_enable,
+        input wire [MEM_ADDR_WIDTH-1:0] dest_base_addr,
+        input wire [MEM_ADDR_WIDTH-1:0] src_base_addr,
+        input wire  [3:0][REG_SIZE-1:0] mem_a_rd_data,
+        input wire  [3:0][REG_SIZE-1:0] mem_b_rd_data,
+
+        output mem_if_t keymem_a_wr_req,
+        output mem_if_t mem_a_rd_req,
+        output mem_if_t mem_b_rd_req,
+        output logic [AHB_DATA_WIDTH-1:0] keymem_a_wr_data,
+
+        output logic skencode_error,
+        output logic skencode_done
+    );
+
+    localparam THE_LAST_ADDR = ((MLDSA_K * MLDSA_N)/4)+((MLDSA_L * MLDSA_N)/4)-1;
+    localparam THE_LAST_API = ((MLDSA_K +MLDSA_L)*MLDSA_N*3)/32;
+
+    // Main State Machine States
+    // TODO: Define the state names in a pakcage.
+    localparam  IDLE                    = 3'b000,
+                READ                    = 3'b001,
+                READ_and_ENC            = 3'b010,
+                READ_ENC_and_CONSUME    = 3'b011,
+                ENC_and_CONSUME         = 3'b100,
+                CONSUME                 = 3'b101,
+                CONSUME_LAST            = 3'b110,
+                DONE                    = 3'b111;
+    
+    // Main State Machine States
+    localparam  WAIT_BUFFER             = 3'b001,
+                WRITE                   = 3'b010,
+                STALL                   = 3'b011,
+                GET_LAST                = 3'b100;
+
+    
+    logic [2:0] main_state, next_main_state, write_state, next_write_state;
+    logic error_flag, asserted_error_flag;
+    logic [7:0][2:0] encoded_coeffs;
+    logic [7:0] encoding_error;
+    logic [23:0] one_encoding_string;
+    logic [95:0] buffer;
+    logic [1:0] producer_selector, consumer_selector;
+    logic write_buffer;
+    logic [31:0] num_mem_operands, num_api_operands;   // encoded each four coeff will increment these by one
+    logic [MEM_ADDR_WIDTH-1:0] locked_dest_addr, locked_src_addr; // this ensures that addresses are captured when the block is enabled
+
+    assign one_encoding_string = {encoded_coeffs[7],encoded_coeffs[6],encoded_coeffs[5],encoded_coeffs[4],
+                                    encoded_coeffs[3],encoded_coeffs[2],encoded_coeffs[1],encoded_coeffs[0]};
+
+    //FIXME enable this later?
+    assign error_flag = 0;//encoding_error[0] | encoding_error[1] | encoding_error[2] | encoding_error[3] |
+                        //encoding_error[4] | encoding_error[5] | encoding_error[6] | encoding_error[7];
+    
+    
+    // State Machine: Updates main_state and write_state based on current conditions and next states.
+    always_ff @(posedge clk or negedge reset_n) begin
+        if (!reset_n) begin
+            main_state  <= IDLE;
+            write_state <= IDLE;
+        end
+        else if (zeroize) begin
+            main_state  <= IDLE;
+            write_state <= IDLE;
+        end
+        else begin
+            if (skencode_error) begin
+                main_state     <= IDLE;
+                write_state    <= IDLE;
+            end
+            else begin
+                main_state     <= next_main_state;
+                write_state    <= next_write_state;
+            end
+        end
+    end
+
+    // Determines next state for main_state based on current main_state and conditions.
+    always_comb begin
+        case (main_state)
+            IDLE: begin
+                if (skencode_enable)
+                    next_main_state = READ;
+                else
+                    next_main_state = IDLE;
+            end
+            READ: begin
+                next_main_state = READ_and_ENC;
+            end
+            READ_and_ENC: begin
+                next_main_state = READ_ENC_and_CONSUME;
+            end
+            READ_ENC_and_CONSUME: begin
+                if ((num_mem_operands+1) == THE_LAST_ADDR) begin
+                    next_main_state = ENC_and_CONSUME;
+                end
+                else begin
+                    next_main_state = READ_ENC_and_CONSUME;
+                end
+            end
+            ENC_and_CONSUME: begin
+                next_main_state = CONSUME;
+            end
+            CONSUME: begin
+                next_main_state = CONSUME_LAST;
+            end
+            CONSUME_LAST: begin
+                next_main_state = DONE;
+            end
+            DONE: begin
+                next_main_state = IDLE;
+            end
+            default: begin
+                next_main_state = IDLE;
+            end
+        endcase
+    end
+
+    // Determines next state for write_state based on current write_state and conditions.
+    always_comb begin
+        case (write_state)
+            IDLE: begin
+                if (main_state == READ_ENC_and_CONSUME)
+                    next_write_state    = WAIT_BUFFER;
+                else
+                    next_write_state    = IDLE;
+            end
+            WAIT_BUFFER: begin
+                if (producer_selector == 'h1)
+                    next_write_state    = WRITE;
+                else
+                    next_write_state    = WAIT_BUFFER;
+            end
+            WRITE: begin
+                if (consumer_selector == 'h1)
+                    next_write_state    = STALL;
+                else
+                    next_write_state    = WRITE;
+            end
+            STALL: begin
+                if (num_api_operands == THE_LAST_API) begin
+                    next_write_state = GET_LAST;
+                end
+                else begin
+                    next_write_state = WAIT_BUFFER;
+                end
+            end
+            GET_LAST: begin
+                next_write_state    = DONE;
+            end
+            DONE: begin
+                next_write_state    = IDLE;
+            end
+            default: begin
+                next_write_state    = IDLE;
+            end
+        endcase
+    end
+
+    // Write request generation
+    always_ff @(posedge clk or negedge reset_n) begin
+        if (!reset_n) begin
+            keymem_a_wr_req     <= '{rd_wr_en: RW_IDLE, addr: '0};
+            num_api_operands    <= 'h0;
+            consumer_selector   <= 'h0;
+        end
+        else if (zeroize) begin
+            keymem_a_wr_req <= '{rd_wr_en: RW_IDLE, addr: '0};
+            num_api_operands    <= 'h0;
+            consumer_selector   <= 'h0;
+        end
+        else begin
+            if (write_state == WRITE)
+                consumer_selector   <= consumer_selector + 'h1;
+            else
+                consumer_selector   <= 'h0;
+
+            if (write_state == IDLE ) begin
+                num_api_operands    <= 'h0;
+            end
+            else if (write_state == WRITE || (write_state == WAIT_BUFFER && producer_selector == 'h1)) begin
+                num_api_operands    <= num_api_operands +'h1;
+            end
+
+            if (write_state == WRITE || (write_state == WAIT_BUFFER && producer_selector == 'h1)) begin
+                keymem_a_wr_req <= '{rd_wr_en: RW_WRITE, addr: locked_dest_addr + num_api_operands};
+            end
+            else begin
+                keymem_a_wr_req <= '{rd_wr_en: RW_IDLE, addr: '0};
+            end
+        end
+    end
+
+    // Controls and updates the state of various internal signals and registers based on the state machine and input signals.
+    // Resets or initializes all signals execpt for the write operation related logics.
+    // Locks destination and source addresses when skencode_enable is active.
+    // Manages write_buffer and producer_selector based on the main state machine.
+    // Issues read requests to memory and increments num_mem_operands during appropriate states.
+    // Signals completion (skencode_done) and checks for errors (skencode_error) based on operation progress.
+    always_ff @(posedge clk or negedge reset_n) begin
+        if (!reset_n) begin
+            write_buffer        <= 'h0;
+            producer_selector   <= 'h0;
+            num_mem_operands    <= 'h0;
+            locked_dest_addr    <= 'h0;
+            locked_src_addr     <= 'h0;
+            skencode_done       <= 'h0;
+            skencode_error      <= 'h0;
+            mem_a_rd_req        <= '{rd_wr_en: RW_IDLE, addr: '0};
+            mem_b_rd_req        <= '{rd_wr_en: RW_IDLE, addr: '0};
+        end
+        else if (zeroize) begin
+            write_buffer        <= 'h0;
+            producer_selector   <= 'h0;
+            num_mem_operands    <= 'h0;
+            locked_dest_addr    <= 'h0;
+            locked_src_addr     <= 'h0;
+            skencode_done       <= 'h0;
+            skencode_error      <= 'h0;
+            mem_a_rd_req        <= '{rd_wr_en: RW_IDLE, addr: '0};
+            mem_b_rd_req        <= '{rd_wr_en: RW_IDLE, addr: '0};
+        end
+        else begin
+            if (skencode_enable) begin
+                locked_dest_addr    <= dest_base_addr;
+                locked_src_addr     <= src_base_addr;
+            end
+
+            if (main_state == READ_and_ENC || main_state == READ_ENC_and_CONSUME || main_state == ENC_and_CONSUME) begin
+                write_buffer        <= 'h1;                
+            end
+            else begin
+                write_buffer        <= 'h0;
+            end
+
+            if (main_state == READ_ENC_and_CONSUME || main_state == ENC_and_CONSUME)
+                producer_selector   <= producer_selector + 1'b1;
+            else
+                producer_selector   <= 'h0;
+
+            if (main_state == READ || main_state == READ_and_ENC || main_state == READ_ENC_and_CONSUME) begin
+                mem_a_rd_req        <= '{rd_wr_en: RW_READ, addr: locked_src_addr + num_mem_operands};
+                mem_b_rd_req        <= '{rd_wr_en: RW_READ, addr: locked_src_addr + num_mem_operands + 1};
+                num_mem_operands    <= num_mem_operands +2'h2;
+            end
+            else begin
+                mem_a_rd_req        <= '{rd_wr_en: RW_IDLE, addr: '0};
+                mem_b_rd_req        <= '{rd_wr_en: RW_IDLE, addr: '0};
+                num_mem_operands    <= 'h0;
+            end
+
+            if (main_state == DONE) begin
+                skencode_done      <= 'h1;
+            end
+            else begin
+                skencode_done      <= 'h0;
+            end
+
+            if (skencode_error == 1'b0 && main_state != IDLE)
+                skencode_error <= error_flag;
+        end
+    end
+    
+    // Manages the 96-bit buffer register based on the write_buffer signal and producer_selector state.
+    // Accumulates 24-bit encoded strings into the 96-bit buffer, preparing data for further processing or output.
+    always_ff @(posedge clk or negedge reset_n) begin
+        if (!reset_n) begin
+            buffer  <= 'h0;
+        end
+        else if (zeroize) begin
+            buffer  <= 'h0;
+        end
+        else begin
+            if (write_buffer) begin
+                if (producer_selector == 2'h0)
+                    buffer[23:0]  <= one_encoding_string;
+                else if (producer_selector == 2'h1)
+                    buffer[47:24] <= one_encoding_string;
+                else if (producer_selector == 2'h2)
+                    buffer[71:48] <= one_encoding_string;
+                else
+                    buffer[95:72] <= one_encoding_string;
+            end
+        end
+    end
+
+    // Assigns the appropriate 32-bit portion of the buffer to keymem_a_wr_data based on consumer_selector.
+    always_comb begin : API_org
+        case(consumer_selector)
+            2'h0: keymem_a_wr_data = buffer[31:0];
+            2'h1: keymem_a_wr_data = buffer[63:32];
+            2'h2: keymem_a_wr_data = buffer[95:64];
+            2'h3: keymem_a_wr_data = 'h0; // Ignored case
+        endcase
+    end : API_org
+
+    always_comb begin : encoding
+        for (int i = 0; i < 4; i++) begin
+            unique case(mem_a_rd_data[i])
+                'h0: begin
+                    encoded_coeffs[i] = 'h2;
+                    encoding_error[i] = 'h0;
+                end
+                'h1: begin
+                    encoded_coeffs[i] = 'h1;
+                    encoding_error[i] = 'h0;
+                end
+                'h2: begin
+                    encoded_coeffs[i] = 'h0;
+                    encoding_error[i] = 'h0;
+                end
+                MLDSA_Q-1: begin
+                    encoded_coeffs[i] = 'h3;
+                    encoding_error[i] = 'h0;
+                end
+                MLDSA_Q-2: begin
+                    encoded_coeffs[i] = 'h4;
+                    encoding_error[i] = 'h0;
+                end
+                default: begin
+                    encoded_coeffs[i] = 'h0;
+                    encoding_error[i] = 'h1;
+                end
+            endcase
+            unique case(mem_b_rd_data[i])
+                'h0: begin
+                    encoded_coeffs[i+4] = 'h2;
+                    encoding_error[i+4] = 'h0;
+                end
+                'h1: begin
+                    encoded_coeffs[i+4] = 'h1;
+                    encoding_error[i+4] = 'h0;
+                end
+                'h2: begin
+                    encoded_coeffs[i+4] = 'h0;
+                    encoding_error[i+4] = 'h0;
+                end
+                MLDSA_Q-1: begin
+                    encoded_coeffs[i+4] = 'h3;
+                    encoding_error[i+4] = 'h0;
+                end
+                MLDSA_Q-2: begin
+                    encoded_coeffs[i+4] = 'h4;
+                    encoding_error[i+4] = 'h0;
+                end
+                default: begin
+                    encoded_coeffs[i+4] = 'h0;
+                    encoding_error[i+4] = 'h1;
+                end
+            endcase
+        end
+    end : encoding
+    
+
+endmodule

snapshots/chipsalliance_adams-bridge_pr66/src/sk_encode/tb/pack_eta.py

@@ -0,0 +1,86 @@
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+import random
+
+# Constants
+Q = 8380417
+VALID_COEFFICIENTS = [Q - 2, Q - 1, 0, 1, 2]
+INVALID_COEFFICIENTS = [Q + 1, -1, Q + 2, 123456]  # Example invalid values
+K = 8
+L = 7
+N = 256
+TOTAL_COEFFICIENTS = (K + L) * N
+
+def map_coefficient(coef):
+    """Map the input coefficient to the corresponding 3-bit value."""
+    mapping = {
+        Q - 2: 4,
+        Q - 1: 3,
+        0: 2,
+        1: 1,
+        2: 0
+    }
+    return mapping.get(coef, None)
+
+def generate_random_coefficients(num_coeffs, include_invalid=False):
+    """Generate a list of random coefficients, including invalid ones if specified."""
+    coefficients = []
+    for _ in range(num_coeffs):
+        if include_invalid and random.random() < 0.2:
+            # 20% chance to pick an invalid coefficient
+            coefficients.append(random.choice(INVALID_COEFFICIENTS))
+        else:
+            # 80% chance to pick a valid coefficient
+            coefficients.append(random.choice(VALID_COEFFICIENTS))
+    return coefficients
+
+def generate_files(input_coefficients, input_file, output_file):
+    """Generate files for the input coefficients and their expected outputs."""
+    output_lines = []
+
+    # Write input coefficients to input file
+    with open(input_file, 'w') as f_input:
+        for coef in input_coefficients:
+            f_input.write(f"{coef:X}\n")
+
+    # Process coefficients for expected output
+    for i in range(0, len(input_coefficients), 32):
+        current_line = 0
+        for j in range(32):
+            if i + j < len(input_coefficients):
+                coef = input_coefficients[i + j]
+                mapped_value = map_coefficient(coef)
+                if mapped_value is not None:
+                    # Shift the current line to the right by 3 and add the mapped value to the left
+                    current_line = (mapped_value << (j * 3)) | current_line
+        
+        if current_line is not None:
+            # Convert the line to a 96-bit hex string
+            final_hex = f"{current_line:024X}"
+            # Add the line to output lines
+            output_lines.append(final_hex)
+
+    # Write expected output lines to the output file
+    with open(output_file, 'w') as f_output:
+        for line in output_lines:
+            f_output.write(f"{line}\n")
+
+# Generate normal and error test vectors
+normal_coefficients = generate_random_coefficients(TOTAL_COEFFICIENTS)
+error_coefficients = generate_random_coefficients(TOTAL_COEFFICIENTS, include_invalid=True)
+
+# Output the files with specified names
+generate_files(normal_coefficients, 'input_sk.hex', 'output_encoded_sk.hex')
+generate_files(error_coefficients, 'error_input_sk.hex', 'error_output_encoded_sk.hex')

snapshots/chipsalliance_adams-bridge_pr66/src/sk_encode/tb/skencode_tb.sv

@@ -0,0 +1,382 @@
+// SPDX-License-Identifier: Apache-2.0
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+// http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+//======================================================================
+//
+// skencode_tb.sv
+// ---------------
+// Testbench for skencode module
+//======================================================================
+
+`default_nettype none
+
+module skencode_tb
+    import mldsa_params_pkg::*;
+    import skdecode_defines_pkg::*;
+#(
+    parameter REG_SIZE = 24,
+    parameter MEM_ADDR_WIDTH = MLDSA_MEM_ADDR_WIDTH,
+    parameter MLDSA_Q = 23'd8380417,
+    parameter AHB_DATA_WIDTH = 32,
+    parameter MLDSA_L = 'h7,
+    parameter MLDSA_K = 'h8
+)
+();
+localparam NUM_OF_COEFF = MLDSA_N * (MLDSA_L + MLDSA_K);
+parameter CLK_HALF_PERIOD = 5;
+parameter CLK_PERIOD = 2 * CLK_HALF_PERIOD;
+
+//----------------------------------------------------------------
+// Register and Wire declarations.
+//----------------------------------------------------------------
+reg clk_tb;
+reg reset_n_tb;
+reg zeroize_tb;
+reg skencode_enable_tb;
+reg [MEM_ADDR_WIDTH-1:0] src_base_addr_tb;
+reg [MEM_ADDR_WIDTH-1:0] dest_base_addr_tb;
+wire [3:0][REG_SIZE-1:0] mem_a_rd_data_tb;
+wire [3:0][REG_SIZE-1:0] mem_b_rd_data_tb;
+wire skencode_done_tb;
+mem_if_t mem_a_rd_req_tb;
+mem_if_t mem_b_rd_req_tb;
+wire [AHB_DATA_WIDTH-1:0] keymem_a_wr_data_tb;
+mem_if_t keymem_a_wr_req_tb;
+wire skencode_error_tb;
+
+reg [23:0] input_mem [0:NUM_OF_COEFF-1];
+reg [AHB_DATA_WIDTH*3-1:0] expected_output_mem [0:NUM_OF_COEFF/32-1];
+reg [AHB_DATA_WIDTH*3-1:0] actual_output_mem [0:NUM_OF_COEFF/32-1];
+
+skencode #(
+    .MEM_ADDR_WIDTH(MEM_ADDR_WIDTH),
+    .MLDSA_Q(MLDSA_Q),
+    .REG_SIZE(REG_SIZE),
+    .AHB_DATA_WIDTH(AHB_DATA_WIDTH)
+) dut (
+    .clk(clk_tb),
+    .reset_n(reset_n_tb),
+    .zeroize(zeroize_tb),
+    .skencode_enable(skencode_enable_tb),
+    .src_base_addr(src_base_addr_tb),
+    .dest_base_addr(dest_base_addr_tb),
+    .mem_a_rd_req(mem_a_rd_req_tb),
+    .mem_b_rd_req(mem_b_rd_req_tb),
+    .mem_a_rd_data(mem_a_rd_data_tb),
+    .mem_b_rd_data(mem_b_rd_data_tb),
+    .keymem_a_wr_req(keymem_a_wr_req_tb),
+    .keymem_a_wr_data(keymem_a_wr_data_tb),
+    .skencode_done(skencode_done_tb),
+    .skencode_error(skencode_error_tb)
+);
+
+wire [AHB_DATA_WIDTH-1:0] dummy_mem_out0, dummy_mem_out1;
+
+genvar k;
+generate
+    for (k = 0; k < 4; k = k +1) begin : mem_blocks
+        dual_port_memory #(
+            .ADDR_WIDTH(MEM_ADDR_WIDTH),
+            .DATA_WIDTH(REG_SIZE),
+            .DEPTH(NUM_OF_COEFF)
+        )
+        input_memory (
+            .clk(clk_tb),
+            .addr_a(mem_a_rd_req_tb.addr),
+            .data_in_a(24'h0),
+            .we_a(1'b0),
+            .data_out_a(mem_a_rd_data_tb[k]),
+            .addr_b(mem_b_rd_req_tb.addr),
+            .data_in_b(24'h0),
+            .we_b(1'b0),
+            .data_out_b(mem_b_rd_data_tb[k])
+        );
+    end : mem_blocks
+endgenerate
+
+dual_port_memory #(
+            .ADDR_WIDTH(MEM_ADDR_WIDTH),
+            .DATA_WIDTH(AHB_DATA_WIDTH),
+            .DEPTH(NUM_OF_COEFF)
+        )
+        output_memory (
+            .clk(clk_tb),
+            .addr_a(keymem_a_wr_req_tb.addr),
+            .data_in_a(keymem_a_wr_data_tb),
+            .we_a((keymem_a_wr_req_tb.rd_wr_en == RW_WRITE)),
+            .data_out_a(dummy_mem_out0),
+            .addr_b(15'b0),
+            .data_in_b(32'b0),
+            .we_b(1'b0),
+            .data_out_b(dummy_mem_out1)
+        );
+
+//----------------------------------------------------------------
+// clk_gen
+//
+// Always running clock generator process.
+//----------------------------------------------------------------
+always
+begin : clk_gen
+  #CLK_HALF_PERIOD;
+  clk_tb = !clk_tb;
+end // clk_gen
+
+task init_sim;
+    begin
+        $display("Start of init\n");
+        clk_tb = 0;
+        reset_n_tb = 0;
+        zeroize_tb = 0;
+        skencode_enable_tb = 0;
+        src_base_addr_tb = 0;
+        dest_base_addr_tb = 0;
+    end
+endtask
+
+//----------------------------------------------------------------
+// reset_dut()
+//
+// Toggle reset to put the DUT into a well known state.
+//----------------------------------------------------------------
+task reset_dut;
+    begin
+      $display("*** Toggle reset.");
+      reset_n_tb = 0;
+      #(3 * CLK_PERIOD);
+      reset_n_tb = 1;
+      $display("End of reset");
+    end
+endtask // reset_dut
+
+task overwrite_memory_content(reg [MEM_ADDR_WIDTH-1:0] src_base_addr);
+    int i, j;
+
+    // Overwrite input memory with the values from input_mem
+    for (i = 0; i < (NUM_OF_COEFF/4); i = i + 1) begin
+        mem_blocks[0].input_memory.mem[i+src_base_addr] = input_mem[4*i + 0];
+        mem_blocks[1].input_memory.mem[i+src_base_addr] = input_mem[4*i + 1];
+        mem_blocks[2].input_memory.mem[i+src_base_addr] = input_mem[4*i + 2];
+        mem_blocks[3].input_memory.mem[i+src_base_addr] = input_mem[4*i + 3];
+    end
+endtask
+
+task read_memory_content(input reg [MEM_ADDR_WIDTH-1:0] dest_base_addr);
+    int i, j;
+    // Read output memory into the actual_output_mem array
+    for (i = 0; i < (NUM_OF_COEFF)/32; i = i + 1) begin
+        actual_output_mem[i][31:0] = output_memory.mem[3*i+0+dest_base_addr];
+        actual_output_mem[i][63:32] = output_memory.mem[3*i+1+dest_base_addr];
+        actual_output_mem[i][95:64] = output_memory.mem[3*i+2+dest_base_addr];
+    end
+endtask
+
+task read_test_vectors(input reg [MEM_ADDR_WIDTH-1:0] src_base_addr);
+    string input_file = "input_sk.hex";
+    string output_file = "output_encoded_sk.hex";
+    integer file, ret;
+    int i;
+    string line;
+
+    // Read input file
+    file = $fopen(input_file, "r");
+    if (file == 0) $error("Cannot open %s for reading\n", input_file);
+    i = 0;
+    while (!$feof(file)) begin
+        if($fgets(line,file)) begin
+            ret = $sscanf(line, "%h", input_mem[i]);
+            i = i + 1;
+        end
+    end
+    $fclose(file);
+    overwrite_memory_content(src_base_addr);
+
+    // Read expected output file
+    file = $fopen(output_file, "r");
+    if (file == 0) $error("Cannot open %s for reading\n", output_file);
+    i = 0;
+    while (!$feof(file)) begin
+        if($fgets(line,file)) begin
+            ret = $sscanf(line, "%h", expected_output_mem[i]);
+            i = i + 1;
+        end
+    end
+    $fclose(file);
+endtask
+
+
+task read_error_test_vectors(input reg [MEM_ADDR_WIDTH-1:0] src_base_addr);
+    string input_file = "error_input_sk.hex";
+    string output_file = "error_output_encoded_sk.hex";
+    integer file, ret;
+    int i;
+    string line;
+
+    // Read input file
+    file = $fopen(input_file, "r");
+    if (file == 0) $error("Cannot open %s for reading\n", input_file);
+    i = 0;
+    while (!$feof(file)) begin
+        if($fgets(line,file)) begin
+            ret = $sscanf(line, "%h", input_mem[i]);
+            i = i + 1;
+        end
+    end
+    $fclose(file);
+    overwrite_memory_content(src_base_addr);
+
+    // Read expected output file
+    file = $fopen(output_file, "r");
+    if (file == 0) $error("Cannot open %s for reading\n", output_file);
+    i = 0;
+    while (!$feof(file)) begin
+        if($fgets(line,file)) begin
+            ret = $sscanf(line, "%h", expected_output_mem[i]);
+            i = i + 1;
+        end
+    end
+    $fclose(file);
+endtask
+
+task skencode_test(input reg [MEM_ADDR_WIDTH-1:0] dest_base_addr, input reg [MEM_ADDR_WIDTH-1:0] src_base_addr);
+    int i, j;
+    $display("Starting skencode test\n");
+    read_test_vectors(src_base_addr);
+    @(posedge clk_tb);
+    skencode_enable_tb = 1;
+    src_base_addr_tb = src_base_addr;
+    dest_base_addr_tb = dest_base_addr;
+    @(posedge clk_tb);
+    skencode_enable_tb = 0;
+    src_base_addr_tb = 0;
+    dest_base_addr_tb = 0;
+
+    $display("Waiting for skencode to complete\n");
+    wait (skencode_done_tb);
+    read_memory_content(dest_base_addr);
+
+    $display("Checking output data\n");
+    for (i = 0; i < NUM_OF_COEFF; i = i + 1) begin
+        if (actual_output_mem[i] !== expected_output_mem[i]) begin
+            $display("Error: Output mismatch at index %0d. Expected: %h, Got: %h", i, expected_output_mem[i], actual_output_mem[i]);
+        end
+    end
+    $display("Test completed\n");
+endtask
+
+
+task skencode_error_test(input reg [MEM_ADDR_WIDTH-1:0] dest_base_addr, input reg [MEM_ADDR_WIDTH-1:0] src_base_addr);
+    int i, j;
+    $display("Starting skencode error test\n");
+    read_error_test_vectors(src_base_addr);
+    @(posedge clk_tb);
+    skencode_enable_tb = 1;
+    src_base_addr_tb = src_base_addr;
+    dest_base_addr_tb = dest_base_addr;
+    @(posedge clk_tb);
+    skencode_enable_tb = 0;
+    src_base_addr_tb = 0;
+    dest_base_addr_tb = 0;
+
+    $display("Waiting for skencode to complete\n");
+    wait (skencode_done_tb | skencode_error_tb);
+    if (skencode_done_tb) begin
+        $display("Error: Error flag should have been asserted...");
+    end
+    else begin
+        @(posedge clk_tb);
+        zeroize_tb = 1;
+        @(posedge clk_tb);
+        zeroize_tb = 0;
+        repeat(3) @(posedge clk_tb);
+        $display("Starting skencode test again\n");
+        read_test_vectors(src_base_addr);
+        @(posedge clk_tb);
+        skencode_enable_tb = 1;
+        src_base_addr_tb = src_base_addr;
+        dest_base_addr_tb = dest_base_addr;
+        @(posedge clk_tb);
+        skencode_enable_tb = 0;
+        src_base_addr_tb = 0;
+        dest_base_addr_tb = 0;
+
+        $display("Waiting for skencode to complete\n");
+        wait (skencode_done_tb);
+        read_memory_content(dest_base_addr);
+
+        $display("Checking output data\n");
+        for (i = 0; i < NUM_OF_COEFF; i = i + 1) begin
+            if (actual_output_mem[i] !== expected_output_mem[i]) begin
+                $display("Error: Output mismatch at index %0d. Expected: %h, Got: %h", i, expected_output_mem[i], actual_output_mem[i]);
+            end
+        end
+        $display("Test completed\n");
+    end
+endtask
+
+initial begin
+    $system($sformatf("python3 pack_eta.py"));
+    init_sim();
+    reset_dut();
+    $display("Reading test vectors from hex files\n");
+    skencode_test('h0, 'h0);
+    skencode_test('h40, 'h20);
+    skencode_error_test('h0, 'h0);
+    $finish;
+end
+
+endmodule
+
+module dual_port_memory
+#(
+    parameter ADDR_WIDTH = 15,
+    parameter DATA_WIDTH = 32,
+    parameter DEPTH = 256
+)
+(
+    input wire clk,
+    
+    // Port A
+    input wire [ADDR_WIDTH-1:0] addr_a,
+    input wire [DATA_WIDTH-1:0] data_in_a,
+    input wire we_a,  // Write enable for port A
+    output reg [DATA_WIDTH-1:0] data_out_a,
+
+    // Port B
+    input wire [ADDR_WIDTH-1:0] addr_b,
+    input wire [DATA_WIDTH-1:0] data_in_b,
+    input wire we_b,  // Write enable for port B
+    output reg [DATA_WIDTH-1:0] data_out_b
+);
+
+    // Memory array
+    reg [DATA_WIDTH-1:0] mem [0:DEPTH-1];
+
+    // Port A logic
+    always @(posedge clk) begin
+        if (we_a) begin
+            mem[addr_a] <= data_in_a;
+        end
+        data_out_a <= mem[addr_a];
+    end
+
+    // Port B logic
+    always @(posedge clk) begin
+        if (we_b) begin
+            mem[addr_b] <= data_in_b;
+        end
+        data_out_b <= mem[addr_b];
+    end
+
+endmodule