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testbench/AsFigo_pyslint_pr166/open_tool_p2p_buggy.log

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+INFO: open-tool P2P fallback (buggy)
+INFO: native simulation P2P not applicable for this case
+
+### native_multifile_compile:pyslint_positive_sv_suite
+'surelog' '-sv' '-parse' '-nocomp' '-Itestbench/AsFigo_pyslint_pr166/snapshot_scratch' '-Itestbench/AsFigo_pyslint_pr166/snapshot_scratch/sv_tests' 'testbench/AsFigo_pyslint_pr166/snapshot_scratch/sv_tests/test_sv_naming_01_p.sv' 'testbench/AsFigo_pyslint_pr166/snapshot_scratch/sv_tests/test_sv_naming_03_p.sv' 'testbench/AsFigo_pyslint_pr166/snapshot_scratch/sv_tests/test_sv_qual_1_p.sv' 'testbench/AsFigo_pyslint_pr166/snapshot_scratch/sv_tests/test_sv_qual_2_p.sv' 'testbench/AsFigo_pyslint_pr166/snapshot_scratch/sv_tests/test_sv_sva_degen_p.sv' '-odir' 'testbench/AsFigo_pyslint_pr166/open_tool_buggy_pyslint_positive_sv_suite'
+[INF:CM0023] Creating log file "testbench/AsFigo_pyslint_pr166/open_tool_buggy_pyslint_positive_sv_suite/slpp_all/surelog.log".
+
+[WRN:PA0205] testbench/AsFigo_pyslint_pr166/snapshot_scratch/sv_tests/test_sv_naming_01_p.sv:7:1: No timescale set for "af_sv_if".
+
+[WRN:PA0205] testbench/AsFigo_pyslint_pr166/snapshot_scratch/sv_tests/test_sv_qual_1_p.sv:8:1: No timescale set for "sv_qual".
+
+[  FATAL] : 0
+[ SYNTAX] : 0
+[  ERROR] : 0
+[WARNING] : 2
+[   NOTE] : 0
+
+rc=0
+PASS: native multi-file compile P2P passed in buggy phase: pyslint_positive_sv_suite; files=5

testbench/AsFigo_pyslint_pr166/open_tool_p2p_fixed.log

@@ -0,0 +1,19 @@
+INFO: open-tool P2P fallback (fixed)
+INFO: native simulation P2P not applicable for this case
+
+### native_multifile_compile:pyslint_positive_sv_suite
+'surelog' '-sv' '-parse' '-nocomp' '-Itestbench/AsFigo_pyslint_pr166/snapshot_scratch' '-Itestbench/AsFigo_pyslint_pr166/snapshot_scratch/sv_tests' 'testbench/AsFigo_pyslint_pr166/snapshot_scratch/sv_tests/test_sv_naming_01_p.sv' 'testbench/AsFigo_pyslint_pr166/snapshot_scratch/sv_tests/test_sv_naming_03_p.sv' 'testbench/AsFigo_pyslint_pr166/snapshot_scratch/sv_tests/test_sv_qual_1_p.sv' 'testbench/AsFigo_pyslint_pr166/snapshot_scratch/sv_tests/test_sv_qual_2_p.sv' 'testbench/AsFigo_pyslint_pr166/snapshot_scratch/sv_tests/test_sv_sva_degen_p.sv' '-odir' 'testbench/AsFigo_pyslint_pr166/open_tool_fixed_pyslint_positive_sv_suite'
+[INF:CM0023] Creating log file "testbench/AsFigo_pyslint_pr166/open_tool_fixed_pyslint_positive_sv_suite/slpp_all/surelog.log".
+
+[WRN:PA0205] testbench/AsFigo_pyslint_pr166/snapshot_scratch/sv_tests/test_sv_naming_01_p.sv:7:1: No timescale set for "af_sv_if".
+
+[WRN:PA0205] testbench/AsFigo_pyslint_pr166/snapshot_scratch/sv_tests/test_sv_qual_1_p.sv:8:1: No timescale set for "sv_qual".
+
+[  FATAL] : 0
+[ SYNTAX] : 0
+[  ERROR] : 0
+[WARNING] : 2
+[   NOTE] : 0
+
+rc=0
+PASS: native multi-file compile P2P passed in fixed phase: pyslint_positive_sv_suite; files=5

testbench/AsFigo_pyslint_pr166/repo_native_buggy.log

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+PASS: repo native multi-file open-tool P2P passed in buggy phase

testbench/AsFigo_pyslint_pr166/repo_native_fixed.log

@@ -0,0 +1 @@
+PASS: repo native multi-file open-tool P2P passed in fixed phase

testbench/AsFigo_pyslint_pr166/repo_native_source.path

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+sv_tests/test_issue_106_f.sv

testbench/AsFigo_pyslint_pr166/run_once.sh

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+#!/bin/bash
+set -u
+HERE="$(cd "$(dirname "${BASH_SOURCE[0]:-$0}")" && pwd)"
+exec python3 "$HERE/../_run_once_from_run_verilator.py" "$HERE/run_verilator.sh"

testbench/AsFigo_pyslint_pr166/run_verilator.sh

@@ -0,0 +1,35 @@
+#!/bin/bash
+set -u
+HERE="$(cd "$(dirname "${BASH_SOURCE[0]:-$0}")" && pwd)"; cd "$HERE"
+. "$HERE/../_testcase_minimum.sh"
+. "$HERE/../_repo_native_p2p_smoke.sh"
+export HWE_AUTO_COVERAGE=1
+NAME=AsFigo_pyslint_pr166
+REPO_ROOT="$(cd "$HERE/../.." && pwd)"
+SNAPSHOT="$REPO_ROOT/snapshots/$NAME"
+PATCH_FILE="$REPO_ROOT/patches/$NAME.patch"
+SCRATCH="$HERE/snapshot_scratch"
+TARGET="sv_tests/test_issue_165_p.sv"
+# Also records the failing clocking-block variant as a patch target.  It is not
+# compiled with the passing variant because both files declare af_sv_if.
+PATCH_TARGET_EVIDENCE="sv_tests/test_issue_165_f.sv sv_tests/test_issue_165_p.sv"
+run_phase() {
+  local tag="$1"
+  rm -rf obj_dir verilator_${tag}_build.log verilator_${tag}.log
+  run_repo_native_p2p_smoke "$tag" || return $?
+  local src=""
+  [ -f "$SCRATCH/$TARGET" ] && src="$SCRATCH/$TARGET"
+  verilator --binary --timing --Wno-fatal --Wno-WIDTH --Wno-UNOPTFLAT --Wno-UNUSEDSIGNAL --Wno-UNUSEDPARAM --Wno-LATCH --Wno-STMTDLY --Wno-PINMISSING --Wno-PINCONNECTEMPTY --Wno-DECLFILENAME --timescale 1ns/1ps $src "$HERE/tb_af_sv_if_verilator.sv" --top-module tb_af_sv_if_verilator -o simv_vlt 2>&1 | tee verilator_${tag}_build.log >/dev/null
+  [ ! -x obj_dir/simv_vlt ] && return 2
+  timeout 20 ./obj_dir/simv_vlt 2>&1 | tee verilator_${tag}.log >/dev/null
+  grep -qE "(^|[^A-Za-z])PASS:" verilator_${tag}.log && ! grep -qE "(^|[^A-Za-z])FAIL:" verilator_${tag}.log && return 0
+  return 1
+}
+rm -rf "$SCRATCH"; cp -r "$SNAPSHOT" "$SCRATCH"; chmod -R u+w "$SCRATCH"
+echo BUGGY; (cd "$SCRATCH" && patch -p1 -R -f --no-backup-if-mismatch < "$PATCH_FILE" >/dev/null 2>&1) || true
+run_phase buggy; rc_buggy=$?
+rm -rf "$SCRATCH"; cp -r "$SNAPSHOT" "$SCRATCH"; chmod -R u+w "$SCRATCH"
+echo FIXED; (cd "$SCRATCH" && patch -p1 -f --no-backup-if-mismatch < "$PATCH_FILE" >/dev/null 2>&1) || true
+run_phase fixed; rc_fixed=$?
+echo "buggy:$rc_buggy fixed:$rc_fixed"
+([ "$rc_buggy" != "0" ]) && [ "$rc_fixed" = "0" ] && { hwe_report_min_testcases; hwe_report_real_verilator_coverage; echo "PASS: $NAME"; exit 0; } || { echo "FAIL: $NAME"; exit 1; }

testbench/AsFigo_pyslint_pr166/tb_af_sv_if_verilator.sv

@@ -0,0 +1,24 @@
+// pr166: adds sv_tests/test_issue_165_p.sv defining interface `af_sv_if`
+// (Verilator-friendly variant that guards out the clocking block via
+// `VERILATOR). Pre-patch the file is missing and elaboration fails; post-patch
+// the TB instantiates the interface and drives bit_a / clk.
+`timescale 1ns/1ps
+module tb_af_sv_if_verilator;
+  af_sv_if dut();
+
+  initial begin
+    dut.clk = 0;
+    dut.bit_a = 0;
+    #1;
+    dut.bit_a = 1;
+    dut.clk = 1;
+    #1;
+    if (dut.bit_a === 1'b1 && dut.clk === 1'b1)
+      $display("PASS: af_sv_if interface accessible and drivable");
+    else
+      $display("FAIL: bit_a=%0b clk=%0b", dut.bit_a, dut.clk);
+    $finish;
+  end
+
+  initial begin #1000; $display("FAIL: timeout"); $finish; end
+endmodule

testbench/AsFigo_pyslint_pr166/verilator_buggy_build.log

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+%Error: testbench/AsFigo_pyslint_pr166/tb_af_sv_if_verilator.sv:10:5: Dotted reference to instance that refers to missing module/interface: 'af_sv_if'
+   10 |     dut.clk = 0;
+      |     ^~~
+        ... See the manual at https://verilator.org/verilator_doc.html?v=5.047 for more assistance.
+%Error: testbench/AsFigo_pyslint_pr166/tb_af_sv_if_verilator.sv:10:9: Can't find definition of 'clk' in dotted variable/method: 'dut.clk'
+   10 |     dut.clk = 0;
+      |         ^~~
+%Error: testbench/AsFigo_pyslint_pr166/tb_af_sv_if_verilator.sv:11:5: Dotted reference to instance that refers to missing module/interface: 'af_sv_if'
+   11 |     dut.bit_a = 0;
+      |     ^~~
+%Error: testbench/AsFigo_pyslint_pr166/tb_af_sv_if_verilator.sv:11:9: Can't find definition of 'bit_a' in dotted variable/method: 'dut.bit_a'
+   11 |     dut.bit_a = 0;
+      |         ^~~~~
+%Error: testbench/AsFigo_pyslint_pr166/tb_af_sv_if_verilator.sv:13:5: Dotted reference to instance that refers to missing module/interface: 'af_sv_if'
+   13 |     dut.bit_a = 1;
+      |     ^~~
+%Error: testbench/AsFigo_pyslint_pr166/tb_af_sv_if_verilator.sv:13:9: Can't find definition of 'bit_a' in dotted variable/method: 'dut.bit_a'
+   13 |     dut.bit_a = 1;
+      |         ^~~~~
+%Error: testbench/AsFigo_pyslint_pr166/tb_af_sv_if_verilator.sv:14:5: Dotted reference to instance that refers to missing module/interface: 'af_sv_if'
+   14 |     dut.clk = 1;
+      |     ^~~
+%Error: testbench/AsFigo_pyslint_pr166/tb_af_sv_if_verilator.sv:14:9: Can't find definition of 'clk' in dotted variable/method: 'dut.clk'
+   14 |     dut.clk = 1;
+      |         ^~~
+%Error: testbench/AsFigo_pyslint_pr166/tb_af_sv_if_verilator.sv:16:9: Dotted reference to instance that refers to missing module/interface: 'af_sv_if'
+   16 |     if (dut.bit_a === 1'b1 && dut.clk === 1'b1)
+      |         ^~~
+%Error: testbench/AsFigo_pyslint_pr166/tb_af_sv_if_verilator.sv:16:13: Can't find definition of 'bit_a' in dotted variable/method: 'dut.bit_a'
+   16 |     if (dut.bit_a === 1'b1 && dut.clk === 1'b1)
+      |             ^~~~~
+%Error: testbench/AsFigo_pyslint_pr166/tb_af_sv_if_verilator.sv:16:31: Dotted reference to instance that refers to missing module/interface: 'af_sv_if'
+   16 |     if (dut.bit_a === 1'b1 && dut.clk === 1'b1)
+      |                               ^~~
+%Error: testbench/AsFigo_pyslint_pr166/tb_af_sv_if_verilator.sv:16:35: Can't find definition of 'clk' in dotted variable/method: 'dut.clk'
+   16 |     if (dut.bit_a === 1'b1 && dut.clk === 1'b1)
+      |                                   ^~~
+%Error: testbench/AsFigo_pyslint_pr166/tb_af_sv_if_verilator.sv:19:43: Dotted reference to instance that refers to missing module/interface: 'af_sv_if'
+   19 |       $display("FAIL: bit_a=%0b clk=%0b", dut.bit_a, dut.clk);
+      |                                           ^~~
+%Error: testbench/AsFigo_pyslint_pr166/tb_af_sv_if_verilator.sv:19:47: Can't find definition of 'bit_a' in dotted variable/method: 'dut.bit_a'
+   19 |       $display("FAIL: bit_a=%0b clk=%0b", dut.bit_a, dut.clk);
+      |                                               ^~~~~
+%Error: testbench/AsFigo_pyslint_pr166/tb_af_sv_if_verilator.sv:19:54: Dotted reference to instance that refers to missing module/interface: 'af_sv_if'
+   19 |       $display("FAIL: bit_a=%0b clk=%0b", dut.bit_a, dut.clk);
+      |                                                      ^~~
+%Error: testbench/AsFigo_pyslint_pr166/tb_af_sv_if_verilator.sv:19:58: Can't find definition of 'clk' in dotted variable/method: 'dut.clk'
+   19 |       $display("FAIL: bit_a=%0b clk=%0b", dut.bit_a, dut.clk);
+      |                                                          ^~~
+%Error: Exiting due to 16 error(s)
+HWE_AUTO_COVERAGE: retrying with --coverage-line
+%Error: testbench/AsFigo_pyslint_pr166/tb_af_sv_if_verilator.sv:10:5: Dotted reference to instance that refers to missing module/interface: 'af_sv_if'
+   10 |     dut.clk = 0;
+      |     ^~~
+        ... See the manual at https://verilator.org/verilator_doc.html?v=5.047 for more assistance.
+%Error: testbench/AsFigo_pyslint_pr166/tb_af_sv_if_verilator.sv:10:9: Can't find definition of 'clk' in dotted variable/method: 'dut.clk'
+   10 |     dut.clk = 0;
+      |         ^~~
+%Error: testbench/AsFigo_pyslint_pr166/tb_af_sv_if_verilator.sv:11:5: Dotted reference to instance that refers to missing module/interface: 'af_sv_if'
+   11 |     dut.bit_a = 0;
+      |     ^~~
+%Error: testbench/AsFigo_pyslint_pr166/tb_af_sv_if_verilator.sv:11:9: Can't find definition of 'bit_a' in dotted variable/method: 'dut.bit_a'
+   11 |     dut.bit_a = 0;
+      |         ^~~~~
+%Error: testbench/AsFigo_pyslint_pr166/tb_af_sv_if_verilator.sv:13:5: Dotted reference to instance that refers to missing module/interface: 'af_sv_if'
+   13 |     dut.bit_a = 1;
+      |     ^~~
+%Error: testbench/AsFigo_pyslint_pr166/tb_af_sv_if_verilator.sv:13:9: Can't find definition of 'bit_a' in dotted variable/method: 'dut.bit_a'
+   13 |     dut.bit_a = 1;
+      |         ^~~~~
+%Error: testbench/AsFigo_pyslint_pr166/tb_af_sv_if_verilator.sv:14:5: Dotted reference to instance that refers to missing module/interface: 'af_sv_if'
+   14 |     dut.clk = 1;
+      |     ^~~
+%Error: testbench/AsFigo_pyslint_pr166/tb_af_sv_if_verilator.sv:14:9: Can't find definition of 'clk' in dotted variable/method: 'dut.clk'
+   14 |     dut.clk = 1;
+      |         ^~~
+%Error: testbench/AsFigo_pyslint_pr166/tb_af_sv_if_verilator.sv:16:9: Dotted reference to instance that refers to missing module/interface: 'af_sv_if'
+   16 |     if (dut.bit_a === 1'b1 && dut.clk === 1'b1)
+      |         ^~~
+%Error: testbench/AsFigo_pyslint_pr166/tb_af_sv_if_verilator.sv:16:13: Can't find definition of 'bit_a' in dotted variable/method: 'dut.bit_a'
+   16 |     if (dut.bit_a === 1'b1 && dut.clk === 1'b1)
+      |             ^~~~~
+%Error: testbench/AsFigo_pyslint_pr166/tb_af_sv_if_verilator.sv:16:31: Dotted reference to instance that refers to missing module/interface: 'af_sv_if'
+   16 |     if (dut.bit_a === 1'b1 && dut.clk === 1'b1)
+      |                               ^~~
+%Error: testbench/AsFigo_pyslint_pr166/tb_af_sv_if_verilator.sv:16:35: Can't find definition of 'clk' in dotted variable/method: 'dut.clk'
+   16 |     if (dut.bit_a === 1'b1 && dut.clk === 1'b1)
+      |                                   ^~~
+%Error: testbench/AsFigo_pyslint_pr166/tb_af_sv_if_verilator.sv:19:43: Dotted reference to instance that refers to missing module/interface: 'af_sv_if'
+   19 |       $display("FAIL: bit_a=%0b clk=%0b", dut.bit_a, dut.clk);
+      |                                           ^~~
+%Error: testbench/AsFigo_pyslint_pr166/tb_af_sv_if_verilator.sv:19:47: Can't find definition of 'bit_a' in dotted variable/method: 'dut.bit_a'
+   19 |       $display("FAIL: bit_a=%0b clk=%0b", dut.bit_a, dut.clk);
+      |                                               ^~~~~
+%Error: testbench/AsFigo_pyslint_pr166/tb_af_sv_if_verilator.sv:19:54: Dotted reference to instance that refers to missing module/interface: 'af_sv_if'
+   19 |       $display("FAIL: bit_a=%0b clk=%0b", dut.bit_a, dut.clk);
+      |                                                      ^~~
+%Error: testbench/AsFigo_pyslint_pr166/tb_af_sv_if_verilator.sv:19:58: Can't find definition of 'clk' in dotted variable/method: 'dut.clk'
+   19 |       $display("FAIL: bit_a=%0b clk=%0b", dut.bit_a, dut.clk);
+      |                                                          ^~~
+%Error: Exiting due to 16 error(s)

testbench/AsFigo_pyslint_pr166/verilator_fixed.log

@@ -0,0 +1,2 @@
+PASS: af_sv_if interface accessible and drivable
+- testbench/AsFigo_pyslint_pr166/tb_af_sv_if_verilator.sv:20: Verilog $finish

testbench/AsFigo_pyslint_pr166/verilator_fixed_build.log

@@ -0,0 +1,18 @@
+%Warning-DEFOVERRIDE: testbench/AsFigo_pyslint_pr166/snapshot_scratch/sv_tests/test_issue_165_p.sv:8:1: Overriding define: 'VERILATOR' with value: '' to existing command line define value: '1'
+                      ... Location of previous definition, with value: '1'
+                      ... For warning description see https://verilator.org/warn/DEFOVERRIDE?v=5.047
+                      ... Use "/* verilator lint_off DEFOVERRIDE */" and lint_on around source to disable this message.
+make: Entering directory 'testbench/AsFigo_pyslint_pr166/obj_dir'
+g++ -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I.  -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable      -fcoroutines -Os  -c -o _coverage_main.o testbench/AsFigo_pyslint_pr166/../_coverage_main.cpp
+g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I.  -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable      -fcoroutines -c -o verilated.o /opt/oss-cad-suite/share/verilator/include/verilated.cpp
+g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I.  -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable      -fcoroutines -c -o verilated_cov.o /opt/oss-cad-suite/share/verilator/include/verilated_cov.cpp
+g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I.  -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable      -fcoroutines -c -o verilated_timing.o /opt/oss-cad-suite/share/verilator/include/verilated_timing.cpp
+g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I.  -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable      -fcoroutines -c -o verilated_threads.o /opt/oss-cad-suite/share/verilator/include/verilated_threads.cpp
+python3 /opt/oss-cad-suite/share/verilator/bin/verilator_includer -DVL_INCLUDE_OPT=include Vhwe_cov_top.cpp Vhwe_cov_top___024root__0.cpp Vhwe_cov_top_af_sv_if__0.cpp Vhwe_cov_top___024root__Slow.cpp Vhwe_cov_top___024root__0__Slow.cpp Vhwe_cov_top_af_sv_if__Slow.cpp Vhwe_cov_top_af_sv_if__0__Slow.cpp Vhwe_cov_top__Syms__Slow.cpp > Vhwe_cov_top__ALL.cpp
+g++ -Os -fvisibility-inlines-hidden -std=c++17 -fmessage-length=0 -march=nocona -mtune=haswell -ftree-vectorize -fPIC -fstack-protector-strong -fno-plt -O2 -ffunction-sections -pipe -isystem /home/user/miniforge3/include -DNDEBUG -D_FORTIFY_SOURCE=2 -O2 -isystem /home/user/miniforge3/include -I.  -MMD -I/opt/oss-cad-suite/share/verilator/include -I/opt/oss-cad-suite/share/verilator/include/vltstd -DVERILATOR=1 -DVM_COVERAGE=1 -DVM_SC=0 -DVM_TIMING=1 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-int-in-bool-context -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable      -fcoroutines -c -o Vhwe_cov_top__ALL.o Vhwe_cov_top__ALL.cpp
+g++ -Wl,-O2 -Wl,--sort-common -Wl,--as-needed -Wl,-z,relro -Wl,-z,now -Wl,--disable-new-dtags -Wl,--gc-sections -Wl,--allow-shlib-undefined -Wl,-rpath,/home/user/miniforge3/lib -Wl,-rpath-link,/home/user/miniforge3/lib -L/home/user/miniforge3/lib    _coverage_main.o verilated.o verilated_cov.o verilated_timing.o verilated_threads.o Vhwe_cov_top__ALL.a    -pthread -lpthread -latomic   -o simv_vlt
+rm Vhwe_cov_top__ALL.verilator_deplist.tmp
+make: Leaving directory 'testbench/AsFigo_pyslint_pr166/obj_dir'
+- V e r i l a t i o n   R e p o r t: Verilator 5.047 devel rev v5.046-293-ge82bd52fa (mod)
+- Verilator: Built from 0.047 MB sources in 3 modules, into 0.041 MB in 8 C++ files needing 0.000 MB
+- Verilator: Walltime 7.819 s (elab=0.001, cvt=0.005, bld=7.808); cpu 0.011 s on 1 threads; allocated 20.398 MB

testbench/jotego_jtcores_pr1111/open_tool_p2p_buggy.log

@@ -0,0 +1,9 @@
+INFO: open-tool P2P fallback (buggy)
+
+### native_sim:modules/jtframe/ver/cen
+'sh' '-c' 'PATH=.:$PATH bash sim.sh'
+LXT info: dumpfile test.lxt opened for output.
+test.v:45: $finish called at 2000000 (1ps)
+
+rc=0
+PASS: native simulation P2P passed in buggy phase: modules/jtframe/ver/cen: 'sh' '-c' 'PATH=.:$PATH bash sim.sh'

testbench/jotego_jtcores_pr1111/repo_native_source.path

@@ -0,0 +1 @@
+cores/twin16/ver/models/test/twin16_main_tb.v

testbench/jotego_jtcores_pr1111/run_once.sh

@@ -0,0 +1,4 @@
+#!/bin/bash
+set -u
+HERE="$(cd "$(dirname "${BASH_SOURCE[0]:-$0}")" && pwd)"
+exec python3 "$HERE/../_run_once_from_run_verilator.py" "$HERE/run_verilator.sh"

testbench/jotego_jtcores_pr1111/tb_credits_sync_delay.sv

@@ -0,0 +1,71 @@
+module tb_credits_sync_delay;
+    logic clk;
+    logic rst_n;
+    logic hs;
+    logic vs;
+    logic hb;
+    logic vb;
+    logic hs_out;
+    logic vs_out;
+    logic hb_out;
+    logic vb_out;
+    int errors;
+
+    credits_sync_delay_model dut (
+        .clk_i(clk),
+        .rst_ni(rst_n),
+        .hs_i(hs),
+        .vs_i(vs),
+        .hb_i(hb),
+        .vb_i(vb),
+        .hs_o(hs_out),
+        .vs_o(vs_out),
+        .hb_o(hb_out),
+        .vb_o(vb_out)
+    );
+
+    initial clk = 1'b0;
+    always #5 clk = ~clk;
+
+    task automatic check_case(input int id, input bit ok, input string msg);
+        if (ok) $display("PASS: CASE %0d: %s", id, msg);
+        else begin
+            $display("FAIL: CASE %0d: %s", id, msg);
+            errors++;
+        end
+    endtask
+
+    initial begin
+        errors = 0;
+        rst_n = 1'b0;
+        hs = 1'b0;
+        vs = 1'b0;
+        hb = 1'b0;
+        vb = 1'b0;
+        repeat (2) @(posedge clk);
+        rst_n = 1'b1;
+        @(posedge clk);
+        #1;
+
+        hs = 1'b1;
+        #1;
+        check_case(1, hs_out == 1'b0, "credit HS output is delayed by video clock");
+
+        vs = 1'b1;
+        #1;
+        check_case(2, vs_out == 1'b0, "credit VS output is delayed by video clock");
+
+        @(posedge clk);
+        #1;
+        hs = 1'b0;
+        #1;
+        check_case(3, hs_out == 1'b1, "credit HS falling edge is delayed by video clock");
+
+        vs = 1'b0;
+        #1;
+        check_case(4, vs_out == 1'b1, "credit VS falling edge is delayed by video clock");
+
+        if (errors) $fatal(1, "FAIL: credit sync delay missed %0d sync edges", errors);
+        $finish;
+    end
+endmodule

testbench/jotego_jtcores_pr1111/verilator_buggy.log

@@ -0,0 +1 @@
+FAIL: jotego_jtcores_pr1111 buggy state failed as expected

testbench/jotego_jtcores_pr1111/verilator_buggy_build.log

@@ -0,0 +1,30 @@
+%Error-PINNOTFOUND: testbench/jotego_jtcores_pr1111/tb_jtframe_credits_sync.sv:26:10: Pin not found: 'HS'
+                                                                                                                                    : ... Suggested alternative: 'HB'
+   26 |         .HS(hs),
+      |          ^~
+                                                                                                                                    : ... Location of instance's module declaration
+   21 | module jtframe_credits #(
+      |        ^~~~~~~~~~~~~~~
+                    ... For error description see https://verilator.org/warn/PINNOTFOUND?v=5.047
+%Error-PINNOTFOUND: testbench/jotego_jtcores_pr1111/tb_jtframe_credits_sync.sv:27:10: Pin not found: 'VS'
+                                                                                                                                    : ... Suggested alternative: 'VB'
+   27 |         .VS(vs),
+      |          ^~
+                                                                                                                                    : ... Location of instance's module declaration
+   21 | module jtframe_credits #(
+      |        ^~~~~~~~~~~~~~~
+%Error-PINNOTFOUND: testbench/jotego_jtcores_pr1111/tb_jtframe_credits_sync.sv:40:10: Pin not found: 'HS_out'
+                                                                                                                                    : ... Suggested alternative: 'HB_out'
+   40 |         .HS_out(hs_out),
+      |          ^~~~~~
+                                                                                                                                    : ... Location of instance's module declaration
+   21 | module jtframe_credits #(
+      |        ^~~~~~~~~~~~~~~
+%Error-PINNOTFOUND: testbench/jotego_jtcores_pr1111/tb_jtframe_credits_sync.sv:41:10: Pin not found: 'VS_out'
+                                                                                                                                    : ... Suggested alternative: 'VB_out'
+   41 |         .VS_out(vs_out),
+      |          ^~~~~~
+                                                                                                                                    : ... Location of instance's module declaration
+   21 | module jtframe_credits #(
+      |        ^~~~~~~~~~~~~~~
+%Error: Exiting due to 4 error(s)

testbench/jotego_jtcores_pr1111/verilator_fixed.log

@@ -0,0 +1,7 @@
+PASS: CASE 1: credits starts with all sync outputs low
+PASS: CASE 2: credits sync outputs are registered before the pixel tick
+PASS: CASE 3: credits delays HB/VB/HS/VS together by one pixel clock
+PASS: CASE 4: credits keeps prior HS/VS until the next pixel tick
+PASS: CASE 5: credits propagates HS/VS falling edges with the same delay
+PASS: jtframe_credits registers HS/VS with credits video path
+- testbench/jotego_jtcores_pr1111/tb_jtframe_credits_sync.sv:105: Verilog $finish

testbench/jotego_jtcores_pr1111/verilator_fixed_coverage.info

@@ -0,0 +1,1004 @@
+TN:verilator_coverage
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testbench/jotego_jtcores_pr1111/verilator_fixed_patch_hdl_lint.log

@@ -0,0 +1,3 @@
+- V e r i l a t i o n   R e p o r t: Verilator 5.047 devel rev v5.046-293-ge82bd52fa (mod)
+- Verilator: Built from 0.394 MB sources in 31 modules, into 0.033 MB in 3 C++ files needing 0.000 MB
+- Verilator: Walltime 0.019 s (elab=0.003, cvt=0.004, bld=0.000); cpu 0.019 s on 1 threads; allocated 23.633 MB