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snapshots/chipsalliance_adams-bridge_pr66/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvmf/default_clk_gen.sv

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+//
+// File: default_clk_gen.sv
+//
+// Generated from Mentor VIP Configurator (20220406)
+// Generated using Mentor VIP Library ( 2022.2 : 04/20/2022:16:06 )
+//
+module default_clk_gen
+(
+    output reg  CLK
+);
+    
+    timeunit 1ns;
+    timeprecision 1ns;
+    
+    initial
+    begin
+        CLK = 0;
+        forever
+        begin
+            #1 CLK = ~CLK;
+        end
+    end
+    
+
+endmodule: default_clk_gen

snapshots/chipsalliance_adams-bridge_pr66/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvmf/default_reset_gen.sv

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+//
+// File: default_reset_gen.sv
+//
+// Generated from Mentor VIP Configurator (20220406)
+// Generated using Mentor VIP Library ( 2022.2 : 04/20/2022:16:06 )
+//
+module default_reset_gen
+(
+    output reg  RESET,
+    input  reg  CLK_IN
+);
+    
+    initial
+    begin
+        RESET = 1;
+        
+        RESET = ~RESET;
+        
+        repeat ( 2 )
+        begin
+            @(posedge CLK_IN);
+        end
+        
+        RESET = ~RESET;
+    end
+    
+
+endmodule: default_reset_gen

snapshots/chipsalliance_adams-bridge_pr66/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvmf/hdl_qvip_ahb_lite_slave.sv

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+//
+// File: hdl_qvip_ahb_lite_slave.sv
+//
+// Generated from Mentor VIP Configurator (20220406)
+// Generated using Mentor VIP Library ( 2022.2 : 04/20/2022:16:06 )
+//
+//Time resolution of '1ns' will be used (See Makefiles and scripts)
+module hdl_qvip_ahb_lite_slave;
+    parameter  UNIQUE_ID = "";
+    parameter  AHB_LITE_SLAVE_0_ACTIVE = 1;
+    parameter  EXT_CLK_RESET = 0;
+    import uvm_pkg::*;
+    import qvip_ahb_lite_slave_params_pkg::*;
+    wire                                                                                                                                                                         default_clk_gen_CLK;
+    wire                                                                                                                                                                         default_reset_gen_RESET;
+    wire [(ahb_lite_slave_0_params::AHB_ADDRESS_WIDTH-1):0]                                                                                                                      ahb_lite_slave_0_HADDR;
+    wire [1:0]                                                                                                                                                                   ahb_lite_slave_0_HTRANS;
+    wire                                                                                                                                                                         ahb_lite_slave_0_HWRITE;
+    wire [2:0]                                                                                                                                                                   ahb_lite_slave_0_HSIZE;
+    wire [(ahb_lite_slave_0_params::AHB_WDATA_WIDTH-1):0]                                                                                                                        ahb_lite_slave_0_HWDATA;
+    wire [2:0]                                                                                                                                                                   ahb_lite_slave_0_HBURST;
+    wire [6:0]                                                                                                                                                                   ahb_lite_slave_0_HPROT;
+    wire                                                                                                                                                                         ahb_lite_slave_0_HMASTLOCK;
+    wire                                                                                                                                                                         ahb_lite_slave_0_HREADYOUT;
+    wire [(ahb_lite_slave_0_params::AHB_RDATA_WIDTH-1):0]                                                                                                                        ahb_lite_slave_0_HRDATA;
+    wire                                                                                                                                                                         ahb_lite_slave_0_HREADY;
+    wire                                                                                                                                                                         ahb_lite_slave_0_HRESP;
+    wire                                                                                                                                                                         ahb_lite_slave_0_HSEL;
+    wire                                                                                                                                                                         ahb_lite_slave_0_HNONSEC;
+    wire [63:0]                                                                                                                                                                  ahb_lite_slave_0_HAUSER;
+    wire [63:0]                                                                                                                                                                  ahb_lite_slave_0_HWUSER;
+    wire [63:0]                                                                                                                                                                  ahb_lite_slave_0_HRUSER;
+    wire [15:0]                                                                                                                                                                  ahb_lite_slave_0_mult_HSEL;
+    wire                                                                                                                                                                         ahb_lite_slave_0_HEXCL;
+    wire [15:0]                                                                                                                                                                  ahb_lite_slave_0_HMASTER;
+    wire                                                                                                                                                                         ahb_lite_slave_0_HEXOKAY;
+    
+    mgc_ahb #(.AHB_NUM_MASTERS(ahb_lite_slave_0_params::AHB_NUM_MASTERS),.AHB_NUM_MASTER_BITS(ahb_lite_slave_0_params::AHB_NUM_MASTER_BITS),.AHB_NUM_SLAVES(ahb_lite_slave_0_params::AHB_NUM_SLAVES),.AHB_ADDRESS_WIDTH(ahb_lite_slave_0_params::AHB_ADDRESS_WIDTH),.AHB_WDATA_WIDTH(ahb_lite_slave_0_params::AHB_WDATA_WIDTH),.AHB_RDATA_WIDTH(ahb_lite_slave_0_params::AHB_RDATA_WIDTH))ahb_lite_slave_0_bfm(.iHCLK(default_clk_gen_CLK),.iHRESETn(default_reset_gen_RESET));
+    
+    
+    initial
+    begin
+        uvm_config_db #(ahb_lite_slave_0_bfm_t)::set(null,"UVMF_VIRTUAL_INTERFACES",{UNIQUE_ID,"ahb_lite_slave_0"},ahb_lite_slave_0_bfm);
+    end
+    generate
+        if ( EXT_CLK_RESET == 0 )
+        begin: generate_internal_clk_rst
+            default_clk_gen default_clk_gen
+            (
+                .CLK(default_clk_gen_CLK)
+            );
+            default_reset_gen default_reset_gen
+            (
+                .RESET(default_reset_gen_RESET),
+                .CLK_IN(default_clk_gen_CLK)
+            );
+        end
+    endgenerate
+    generate
+        if ( AHB_LITE_SLAVE_0_ACTIVE )
+        begin: generate_active_ahb_lite_slave_0
+            ahb_lite_slave 
+            #(
+                .NUM_MASTERS(ahb_lite_slave_0_params::AHB_NUM_MASTERS),
+                .NUM_MASTER_BITS(ahb_lite_slave_0_params::AHB_NUM_MASTER_BITS),
+                .NUM_SLAVES(ahb_lite_slave_0_params::AHB_NUM_SLAVES),
+                .ADDR_WIDTH(ahb_lite_slave_0_params::AHB_ADDRESS_WIDTH),
+                .WDATA_WIDTH(ahb_lite_slave_0_params::AHB_WDATA_WIDTH),
+                .RDATA_WIDTH(ahb_lite_slave_0_params::AHB_RDATA_WIDTH),
+                .SLAVE_INDEX(0)
+            )
+            ahb_lite_slave_0
+            (
+                .ahb_if(ahb_lite_slave_0_bfm),
+                .HADDR(ahb_lite_slave_0_HADDR),
+                .HTRANS(ahb_lite_slave_0_HTRANS),
+                .HWRITE(ahb_lite_slave_0_HWRITE),
+                .HSIZE(ahb_lite_slave_0_HSIZE),
+                .HWDATA(ahb_lite_slave_0_HWDATA),
+                .HBURST(ahb_lite_slave_0_HBURST),
+                .HPROT(ahb_lite_slave_0_HPROT),
+                .HMASTLOCK(ahb_lite_slave_0_HMASTLOCK),
+                .HREADYOUT(ahb_lite_slave_0_HREADYOUT),
+                .HRDATA(ahb_lite_slave_0_HRDATA),
+                .HREADY(ahb_lite_slave_0_HREADY),
+                .HRESP(ahb_lite_slave_0_HRESP),
+                .HSEL(ahb_lite_slave_0_HSEL),
+                .HNONSEC(ahb_lite_slave_0_HNONSEC),
+                .HAUSER(ahb_lite_slave_0_HAUSER),
+                .HWUSER(ahb_lite_slave_0_HWUSER),
+                .HRUSER(ahb_lite_slave_0_HRUSER),
+                .mult_HSEL(ahb_lite_slave_0_mult_HSEL),
+                .HEXCL(ahb_lite_slave_0_HEXCL),
+                .HMASTER(ahb_lite_slave_0_HMASTER),
+                .HEXOKAY(ahb_lite_slave_0_HEXOKAY)
+            );
+        end
+        else
+        begin: generate_passive_ahb_lite_slave_0_monitor
+            logic [(ahb_lite_slave_0_params::AHB_RDATA_WIDTH-1):0] unpacked_HRDATA   [ahb_lite_slave_0_params::AHB_NUM_SLAVES];
+            logic                                                  unpacked_HREADY   [ahb_lite_slave_0_params::AHB_NUM_SLAVES];
+            logic                                                  unpacked_HRESP    [ahb_lite_slave_0_params::AHB_NUM_SLAVES];
+            logic                                                  unpacked_HSEL     [ahb_lite_slave_0_params::AHB_NUM_SLAVES];
+            logic [15:0]                                           unpacked_mult_HSEL[ahb_lite_slave_0_params::AHB_NUM_SLAVES];
+            logic                                                  unpacked_HEXOKAY  [ahb_lite_slave_0_params::AHB_NUM_SLAVES];
+            assign unpacked_HRDATA   [0] = ahb_lite_slave_0_HRDATA;
+            assign unpacked_HREADY   [0] = ahb_lite_slave_0_HREADY;
+            assign unpacked_HRESP    [0] = ahb_lite_slave_0_HRESP;
+            assign unpacked_HSEL     [0] = ahb_lite_slave_0_HSEL;
+            assign unpacked_mult_HSEL[0] = ahb_lite_slave_0_mult_HSEL;
+            assign unpacked_HEXOKAY  [0] = ahb_lite_slave_0_HEXOKAY;
+            ahb_lite_monitor 
+            #(
+                .NUM_MASTERS(ahb_lite_slave_0_params::AHB_NUM_MASTERS),
+                .NUM_MASTER_BITS(ahb_lite_slave_0_params::AHB_NUM_MASTER_BITS),
+                .NUM_SLAVES(ahb_lite_slave_0_params::AHB_NUM_SLAVES),
+                .ADDR_WIDTH(ahb_lite_slave_0_params::AHB_ADDRESS_WIDTH),
+                .WDATA_WIDTH(ahb_lite_slave_0_params::AHB_WDATA_WIDTH),
+                .RDATA_WIDTH(ahb_lite_slave_0_params::AHB_RDATA_WIDTH)
+            )
+            ahb_lite_slave_0
+            (
+                .ahb_if(ahb_lite_slave_0_bfm),
+                .HADDR(ahb_lite_slave_0_HADDR),
+                .HTRANS(ahb_lite_slave_0_HTRANS),
+                .HWRITE(ahb_lite_slave_0_HWRITE),
+                .HSIZE(ahb_lite_slave_0_HSIZE),
+                .HWDATA(ahb_lite_slave_0_HWDATA),
+                .HBURST(ahb_lite_slave_0_HBURST),
+                .HPROT(ahb_lite_slave_0_HPROT),
+                .HMASTLOCK(ahb_lite_slave_0_HMASTLOCK),
+//                .HREADYOUT(ahb_lite_slave_0_HREADYOUT),
+                .HRDATA(unpacked_HRDATA),
+                .HREADY(unpacked_HREADY),
+                .HRESP(unpacked_HRESP),
+                .HSEL(unpacked_HSEL),
+                .HNONSEC(ahb_lite_slave_0_HNONSEC),
+                .HAUSER(ahb_lite_slave_0_HAUSER),
+                .HWUSER(ahb_lite_slave_0_HWUSER),
+                .HRUSER(ahb_lite_slave_0_HRUSER),
+                .mult_HSEL(unpacked_mult_HSEL),
+                .HEXCL(ahb_lite_slave_0_HEXCL),
+                .HMASTER(ahb_lite_slave_0_HMASTER),
+                .HEXOKAY(unpacked_HEXOKAY)
+            );
+        end
+    endgenerate
+
+endmodule: hdl_qvip_ahb_lite_slave

snapshots/chipsalliance_adams-bridge_pr66/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvmf/qvip_ahb_lite_slave_env_configuration.svh

@@ -0,0 +1,76 @@
+//
+// File: qvip_ahb_lite_slave_env_configuration.svh
+//
+// Generated from Mentor VIP Configurator (20220406)
+// Generated using Mentor VIP Library ( 2022.2 : 04/20/2022:16:06 )
+//
+class qvip_ahb_lite_slave_env_configuration extends uvmf_environment_configuration_base;
+    `uvm_object_utils(qvip_ahb_lite_slave_env_configuration)
+    // Handles for vip config for each of the QVIP instances
+    
+    ahb_lite_slave_0_cfg_t ahb_lite_slave_0_cfg;
+    // Handles for address maps
+    
+    address_map MBOX;
+    
+    function new
+    (
+        string name = "qvip_ahb_lite_slave_env_configuration"
+    );
+        super.new(name);
+        ahb_lite_slave_0_cfg = ahb_lite_slave_0_cfg_t::type_id::create("ahb_lite_slave_0_cfg");
+    endfunction
+    
+    virtual function string convert2string;
+        return {"qvip_ahb_lite_slave_env_configuration:",ahb_lite_slave_0_cfg.convert2string()};
+    endfunction: convert2string
+    
+    extern function void initialize
+    (
+        uvmf_sim_level_t sim_level,
+        string environment_path,
+        string interface_names[],
+        uvm_reg_block register_model = null,
+        uvmf_active_passive_t interface_activity[] = {}
+    );
+    
+endclass: qvip_ahb_lite_slave_env_configuration
+
+function void qvip_ahb_lite_slave_env_configuration::initialize
+(
+    uvmf_sim_level_t sim_level,
+    string environment_path,
+    string interface_names[],
+    uvm_reg_block register_model = null,
+    uvmf_active_passive_t interface_activity[] = {}
+);
+    super.initialize(sim_level, environment_path, interface_names, register_model, interface_activity);
+    
+    if ( !uvm_config_db #(ahb_lite_slave_0_bfm_t)::get( null, "UVMF_VIRTUAL_INTERFACES", interface_names[0], ahb_lite_slave_0_cfg.m_bfm ) )
+    begin
+        `uvm_fatal("Config Error", $sformatf("uvm_config_db #(ahb_lite_slave_0_bfm_t)::get() cannot find bfm vif handle for agent with interface_name '%s'", interface_names[0]))
+    end
+    
+    begin
+        addr_map_entry_s addr_map_entries[] = new [3];
+        addr_map_entries = '{
+            '{MAP_NORMAL,"MEM",0,MAP_NS,4'h0,64'h30000000,64'h20000,MEM_NORMAL,MAP_NORM_SEC_DATA},
+            '{MAP_NORMAL,"CSR",1,MAP_NS,4'h0,64'h30020000,64'h10000,MEM_NORMAL,MAP_NORM_SEC_DATA},
+            '{MAP_NORMAL,"REG",2,MAP_NS,4'h0,64'h30030000,64'h10000,MEM_NORMAL,MAP_NORM_SEC_DATA}};
+        MBOX = address_map::type_id::create("MBOX_addr_map");
+        MBOX.addr_mask = 64'hFFF;
+        MBOX.set( addr_map_entries );
+    end
+    
+    ahb_lite_slave_0_config_policy::configure(ahb_lite_slave_0_cfg, MBOX);
+    if ( interface_activity.size() > 0 )
+    begin
+        case ( interface_activity[0] )
+            ACTIVE :
+                ahb_lite_slave_0_cfg.agent_cfg.is_active = 1;
+            PASSIVE :
+                ahb_lite_slave_0_cfg.agent_cfg.is_active = 0;
+        endcase
+    end
+endfunction: initialize
+

snapshots/chipsalliance_adams-bridge_pr66/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvmf/qvip_ahb_lite_slave_environment.svh

@@ -0,0 +1,51 @@
+//
+// File: qvip_ahb_lite_slave_environment.svh
+//
+// Generated from Mentor VIP Configurator (20220406)
+// Generated using Mentor VIP Library ( 2022.2 : 04/20/2022:16:06 )
+//
+`include "uvm_macros.svh"
+class qvip_ahb_lite_slave_environment
+#(
+    string UNIQUE_ID = ""
+) extends uvmf_environment_base #(.CONFIG_T(qvip_ahb_lite_slave_env_configuration));
+    `uvm_component_param_utils(qvip_ahb_lite_slave_environment #(UNIQUE_ID))
+    // Agent handles
+    
+    ahb_lite_slave_0_agent_t ahb_lite_slave_0;
+    function new
+    (
+        string name = "qvip_ahb_lite_slave_environment",
+        uvm_component parent = null
+    );
+        super.new(name, parent);
+    endfunction
+    
+    extern function void build_phase
+    (
+        uvm_phase phase
+    );
+    
+    extern function void connect_phase
+    (
+        uvm_phase phase
+    );
+    
+endclass: qvip_ahb_lite_slave_environment
+
+function void qvip_ahb_lite_slave_environment::build_phase
+(
+    uvm_phase phase
+);
+    ahb_lite_slave_0 = ahb_lite_slave_0_agent_t::type_id::create("ahb_lite_slave_0", this );
+    ahb_lite_slave_0.set_mvc_config(configuration.ahb_lite_slave_0_cfg);
+    
+endfunction: build_phase
+
+function void qvip_ahb_lite_slave_environment::connect_phase
+(
+    uvm_phase phase
+);
+    uvm_config_db #(mvc_sequencer)::set(null,UVMF_SEQUENCERS,{UNIQUE_ID,"ahb_lite_slave_0"},ahb_lite_slave_0.m_sequencer);
+endfunction: connect_phase
+

snapshots/chipsalliance_adams-bridge_pr66/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvmf/qvip_ahb_lite_slave_pkg.sv

@@ -0,0 +1,31 @@
+//
+// File: qvip_ahb_lite_slave_pkg.sv
+//
+// Generated from Mentor VIP Configurator (20220406)
+// Generated using Mentor VIP Library ( 2022.2 : 04/20/2022:16:06 )
+//
+// ## The following code is used to add this qvip_configurator generated output into an
+// ## encapsulating UVMF Generated environment.  The addQvipSubEnv function is added to 
+// ## the python configuration file used by the UVMF environment generator.
+// env.addQvipSubEnv('sub_env_instance_name', 'qvip_ahb_lite_slave', ['ahb_lite_slave_0'])
+//
+// ## The following code is used to add this qvip_configurator generated output into an
+// ## encapsulating UVMF Generated test bench.  The addQvipBfm function is added to 
+// ## the python configuration file used by the UVMF bench generator.
+// ben.addQvipBfm('ahb_lite_slave_0', 'qvip_ahb_lite_slave', 'ACTIVE')
+package qvip_ahb_lite_slave_pkg;
+    import uvm_pkg::*;
+    
+    `include "uvm_macros.svh"
+    
+    import addr_map_pkg::*;
+    
+    import uvmf_base_pkg::*;
+    import qvip_ahb_lite_slave_params_pkg::*;
+    import mvc_pkg::*;
+    import mgc_ahb_seq_pkg::*;
+    import mgc_ahb_v2_0_pkg::*;
+    
+    `include "qvip_ahb_lite_slave_env_configuration.svh"
+    `include "qvip_ahb_lite_slave_environment.svh"
+endpackage: qvip_ahb_lite_slave_pkg

snapshots/chipsalliance_adams-bridge_pr66/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvmf/qvip_ahb_lite_slave_subenv_config.yaml

@@ -0,0 +1,14 @@
+## To instantiate this subenv in a higher level, use this structure:
+##  qvip_subenvs :
+##    - { name: "<instance_name_of_subenv>", type: "qvip_ahb_lite_slave" }
+uvmf:
+  qvip_library:
+    version: '2022.2'
+    date: '04/20/2022:16:06'
+  qvip_environments:
+     "qvip_ahb_lite_slave":
+        agents:
+          - name: 'ahb_lite_slave_0'
+            imports:
+              - "mvc_pkg"
+              - "mgc_ahb_v2_0_pkg"

snapshots/chipsalliance_adams-bridge_pr66/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvmf_tb/Makefile

@@ -0,0 +1,57 @@
+####################
+# Common Setup.
+
+INCDIRS = +incdir+${QUESTA_MVC_HOME}/questa_mvc_src/sv \
+          +incdir+${UVMF_HOME}/uvmf_base_pkg \
+          +incdir+../config_policies
+
+HVL_SV_SOURCE = ../uvmf/hvl_qvip_ahb_lite_slave.sv
+HDL_SV_SOURCE = ../uvmf/hdl_qvip_ahb_lite_slave.sv
+
+UVM_OPTIONS = +UVM_TESTNAME=qvip_ahb_lite_slave_test_base +SEQ=qvip_ahb_lite_slave_example_vseq
+
+export QVIP_AHB_LITE_SLAVE_DIR_NAME ?= $(shell pwd)/../uvmf
+
+####################
+# Questa support.
+
+all: work sv opt sim
+
+sv: hvl_sv hdl_sv
+
+work:
+	vlib work
+
+hvl_sv:
+	vlog -f qvip_ahb_lite_slave_test_filelist.f $(INCDIRS) $(HVL_SV_SOURCE)
+
+hdl_sv:
+	vlog -f qvip_ahb_lite_slave_test_filelist.f $(INCDIRS) $(HDL_SV_SOURCE)
+
+opt:
+	vopt hdl_qvip_ahb_lite_slave hvl_qvip_ahb_lite_slave -o top_opt
+
+vis_opt:
+	vopt hdl_qvip_ahb_lite_slave hvl_qvip_ahb_lite_slave -o top_opt -debug -designfile design.bin
+
+sim:
+	vsim -mvchome ${QUESTA_MVC_HOME} top_opt $(UVM_OPTIONS) +nowarnTSCALE -t 1ns -c -do "run -all; quit"
+
+vis_sim:
+	vsim -mvchome ${QUESTA_MVC_HOME} top_opt $(UVM_OPTIONS) +nowarnTSCALE -t 1ns -c -do "run -all; quit" -qwavedb=+signal+transaction+class+uvm_schematic
+	visualizer -designfile design.bin -wavefile qwave.db
+
+vis_int: work sv vis_opt
+	vsim -mvchome ${QUESTA_MVC_HOME} top_opt $(UVM_OPTIONS) +nowarnTSCALE -t 1ns -visualizer=design.bin -qwavedb=+signal+transaction+class+uvm_schematic
+
+gui:
+	vsim -mvchome ${QUESTA_MVC_HOME} top_opt $(UVM_OPTIONS) +nowarnTSCALE -t 1ns
+
+####################
+# Cleanup.
+
+clean:
+	rm -rf work transcript vsim.wlf
+
+.PHONY: all sv hvl_sv hdl_sv opt sim gui
+.PHONY: vis vis_opt vis_sim vis_int

snapshots/chipsalliance_adams-bridge_pr66/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvmf_tb/qrun_32.f

@@ -0,0 +1,15 @@
+export QVIP_AHB_LITE_SLAVE_DIR_NAME=$(pwd)/../uvmf
+
+qrun -f qvip_ahb_lite_slave_test_filelist.f \
++incdir+${QUESTA_MVC_HOME}/questa_mvc_src/sv \
+../uvmf/hdl_qvip_ahb_lite_slave.sv \
+../uvmf/hvl_qvip_ahb_lite_slave.sv \
+-debug \
+-designfile design.bin \
+-c \
+-mvchome ${QUESTA_MVC_HOME} \
++nowarnTSCALE -t 1ns \
+-do "run -all; quit" \
++UVM_TESTNAME=qvip_ahb_lite_slave_test_base \
++SEQ=qvip_ahb_lite_slave_example_vseq \
+-qwavedb=+signal+transaction+class+uvm_schematic

snapshots/chipsalliance_adams-bridge_pr66/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvmf_tb/qrun_64.f

@@ -0,0 +1,16 @@
+export QVIP_AHB_LITE_SLAVE_DIR_NAME=$(pwd)/../uvmf
+
+qrun -f qvip_ahb_lite_slave_test_filelist.f \
++incdir+${QUESTA_MVC_HOME}/questa_mvc_src/sv \
+../uvmf/hdl_qvip_ahb_lite_slave.sv \
+../uvmf/hvl_qvip_ahb_lite_slave.sv \
+-64 \
+-debug \
+-designfile design.bin \
+-c \
+-mvchome ${QUESTA_MVC_HOME} \
++nowarnTSCALE -t 1ns \
+-do "run -all; quit" \
++UVM_TESTNAME=qvip_ahb_lite_slave_test_base \
++SEQ=qvip_ahb_lite_slave_example_vseq \
+-qwavedb=+signal+transaction+class+uvm_schematic

snapshots/chipsalliance_adams-bridge_pr66/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvmf_tb/questa_run_32

@@ -0,0 +1,13 @@
+export QVIP_AHB_LITE_SLAVE_DIR_NAME=$(pwd)/../uvmf
+
+echo "Setting up work directory"
+vlib work
+
+vlog -f qvip_ahb_lite_slave_test_filelist.f +incdir+${QUESTA_MVC_HOME}/questa_mvc_src/sv \
+    ../uvmf/hdl_qvip_ahb_lite_slave.sv \
+    ../uvmf/hvl_qvip_ahb_lite_slave.sv 
+echo "Optimisation step"
+vopt -o top_opt hdl_qvip_ahb_lite_slave hvl_qvip_ahb_lite_slave -debug -designfile design.bin
+
+echo "Running test"
+vsim -c -mvchome ${QUESTA_MVC_HOME} top_opt +nowarnTSCALE -t 1ns -do "run -all; quit" +UVM_TESTNAME=qvip_ahb_lite_slave_test_base +SEQ=qvip_ahb_lite_slave_example_vseq -qwavedb=+signal+transaction+class+uvm_schematic

snapshots/chipsalliance_adams-bridge_pr66/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvmf_tb/questa_run_64

@@ -0,0 +1,13 @@
+export QVIP_AHB_LITE_SLAVE_DIR_NAME=$(pwd)/../uvmf
+
+echo "Setting up work directory"
+vlib work
+
+vlog -f qvip_ahb_lite_slave_test_filelist.f +incdir+${QUESTA_MVC_HOME}/questa_mvc_src/sv \
+    ../uvmf/hdl_qvip_ahb_lite_slave.sv \
+    ../uvmf/hvl_qvip_ahb_lite_slave.sv 
+echo "Optimisation step"
+vopt -64 -o top_opt hdl_qvip_ahb_lite_slave hvl_qvip_ahb_lite_slave -debug -designfile design.bin
+
+echo "Running test"
+vsim -c -64 -mvchome ${QUESTA_MVC_HOME} top_opt +nowarnTSCALE -t 1ns -do "run -all; quit" +UVM_TESTNAME=qvip_ahb_lite_slave_test_base +SEQ=qvip_ahb_lite_slave_example_vseq -qwavedb=+signal+transaction+class+uvm_schematic

snapshots/chipsalliance_adams-bridge_pr66/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvmf_tb/qvip_ahb_lite_slave_example_vseq.svh

@@ -0,0 +1,33 @@
+//
+// File: qvip_ahb_lite_slave_example_vseq.svh
+//
+// Generated from Mentor VIP Configurator (20220406)
+// Generated using Mentor VIP Library ( 2022.2 : 04/20/2022:16:06 )
+//
+// The purpose of this example virtual sequence is to show how the default or selected sequences for 
+// each QVIP can be run. The sequences are run in series in an arbitary order. 
+class qvip_ahb_lite_slave_example_vseq extends qvip_ahb_lite_slave_vseq_base;
+    `uvm_object_utils(qvip_ahb_lite_slave_example_vseq)
+    function new
+    (
+        string name = "qvip_ahb_lite_slave_example_vseq"
+    );
+        super.new(name);
+    endfunction
+    
+    extern task body;
+    
+endclass: qvip_ahb_lite_slave_example_vseq
+
+task qvip_ahb_lite_slave_example_vseq::body;
+    ahb_single_wr_deparam_seq ahb_lite_slave_0_seq_0 = ahb_single_wr_deparam_seq::type_id::create("ahb_single_wr_deparam_seq");
+    ahb_single_rd_deparam_seq ahb_lite_slave_0_seq_1 = ahb_single_rd_deparam_seq::type_id::create("ahb_single_rd_deparam_seq");
+    
+    // Sequences run in the following order
+    
+    begin
+        ahb_lite_slave_0_seq_0.start(ahb_lite_slave_0_sqr);
+        ahb_lite_slave_0_seq_1.start(ahb_lite_slave_0_sqr);
+    end
+endtask: body
+

snapshots/chipsalliance_adams-bridge_pr66/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvmf_tb/qvip_ahb_lite_slave_test_base.svh

@@ -0,0 +1,73 @@
+//
+// File: qvip_ahb_lite_slave_test_base.svh
+//
+// Generated from Mentor VIP Configurator (20220406)
+// Generated using Mentor VIP Library ( 2022.2 : 04/20/2022:16:06 )
+//
+class qvip_ahb_lite_slave_test_base extends uvmf_test_base #(.CONFIG_T(qvip_ahb_lite_slave_env_configuration),.ENV_T(qvip_ahb_lite_slave_environment),.TOP_LEVEL_SEQ_T(qvip_ahb_lite_slave_vseq_base));
+    `uvm_component_utils(qvip_ahb_lite_slave_test_base)
+    function new
+    (
+        string name = "qvip_ahb_lite_slave_test_base_test_base",
+        uvm_component parent = null
+    );
+        super.new(name, parent);
+    endfunction
+    
+    extern function void build_phase
+    (
+        uvm_phase phase
+    );
+    
+    extern task run_phase
+    (
+        uvm_phase phase
+    );
+    
+endclass: qvip_ahb_lite_slave_test_base
+
+function void qvip_ahb_lite_slave_test_base::build_phase
+(
+    uvm_phase phase
+);
+    string interface_names[] = { "ahb_lite_slave_0" };
+    super.build_phase( phase );
+    configuration.initialize( BLOCK, "uvm_test_top.qvip_ahb_lite_slave", interface_names );
+endfunction: build_phase
+
+task qvip_ahb_lite_slave_test_base::run_phase
+(
+    uvm_phase phase
+);
+    string sequence_name;
+    qvip_ahb_lite_slave_vseq_base vseq;
+    uvm_object obj;
+    uvm_cmdline_processor clp;
+    uvm_factory factory;
+    clp = uvm_cmdline_processor::get_inst();
+    factory = uvm_factory::get();
+    if ( clp.get_arg_value("+SEQ=", sequence_name) == 0 )
+    begin
+        `uvm_fatal(get_type_name(), "You must specify a virtual sequence to run using the +SEQ plusarg")
+    end
+    obj = factory.create_object_by_name(sequence_name);
+    if ( obj == null )
+    begin
+        factory.print();
+        `uvm_fatal(get_type_name(), {"Virtual sequence '",sequence_name,"' not found in factory"})
+    end
+    
+    if ( !$cast(vseq, obj) )
+    begin
+        factory.print();
+        `uvm_fatal(get_type_name(), {"Virtual sequence '",sequence_name,"' is not derived from qvip_ahb_lite_slave_vseq_base"})
+    end
+    
+    //The sequence is OK to run
+    `uvm_info(get_type_name(), {"Running virtual sequence '",sequence_name,"'"}, UVM_LOW)
+    
+    phase.raise_objection(this);
+    vseq.start(null);
+    phase.drop_objection(this);
+endtask: run_phase
+

snapshots/chipsalliance_adams-bridge_pr66/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvmf_tb/qvip_ahb_lite_slave_test_filelist.f

@@ -0,0 +1,17 @@
+$QUESTA_MVC_HOME/include/questa_mvc_svapi.sv
++define+MAP_PROT_ATTR $QUESTA_MVC_HOME/questa_mvc_src/sv/mvc_pkg.sv
++incdir+$UVMF_HOME/common/fli_pkg
+$UVMF_HOME/common/fli_pkg/fli_pkg.sv
++incdir+$UVMF_HOME/uvmf_base_pkg
+$UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg_hdl.sv
+$UVMF_HOME/uvmf_base_pkg/uvmf_base_pkg.sv
++incdir+$QUESTA_MVC_HOME/questa_mvc_src/sv/ahb $QUESTA_MVC_HOME/questa_mvc_src/sv/ahb/mgc_ahb_v2_0_pkg.sv
++incdir+$QVIP_AHB_LITE_SLAVE_DIR_NAME
++incdir+$QVIP_AHB_LITE_SLAVE_DIR_NAME/../config_policies
+$QVIP_AHB_LITE_SLAVE_DIR_NAME/../config_policies/qvip_ahb_lite_slave_params_pkg.sv
+$QVIP_AHB_LITE_SLAVE_DIR_NAME/qvip_ahb_lite_slave_pkg.sv
+$QVIP_AHB_LITE_SLAVE_DIR_NAME/../uvmf_tb/qvip_ahb_lite_slave_test_pkg.sv
++incdir+$QUESTA_MVC_HOME/questa_mvc_src/sv/ahb/modules $QUESTA_MVC_HOME/questa_mvc_src/sv/ahb/modules/ahb_lite_slave.sv
++incdir+$QUESTA_MVC_HOME/questa_mvc_src/sv/ahb/modules $QUESTA_MVC_HOME/questa_mvc_src/sv/ahb/modules/ahb_lite_monitor.sv
+$QVIP_AHB_LITE_SLAVE_DIR_NAME/default_clk_gen.sv
+$QVIP_AHB_LITE_SLAVE_DIR_NAME/default_reset_gen.sv

snapshots/chipsalliance_adams-bridge_pr66/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvmf_tb/qvip_ahb_lite_slave_test_pkg.sv

@@ -0,0 +1,34 @@
+//
+// File: qvip_ahb_lite_slave_test_pkg.sv
+//
+// Generated from Mentor VIP Configurator (20220406)
+// Generated using Mentor VIP Library ( 2022.2 : 04/20/2022:16:06 )
+//
+// ## The following code is used to add this qvip_configurator generated output into an
+// ## encapsulating UVMF Generated environment.  The addQvipSubEnv function is added to 
+// ## the python configuration file used by the UVMF environment generator.
+// env.addQvipSubEnv('sub_env_instance_name', 'qvip_ahb_lite_slave', ['ahb_lite_slave_0'])
+//
+// ## The following code is used to add this qvip_configurator generated output into an
+// ## encapsulating UVMF Generated test bench.  The addQvipBfm function is added to 
+// ## the python configuration file used by the UVMF bench generator.
+// ben.addQvipBfm('ahb_lite_slave_0', 'qvip_ahb_lite_slave', 'ACTIVE')
+package qvip_ahb_lite_slave_test_pkg;
+    import uvm_pkg::*;
+    
+    `include "uvm_macros.svh"
+    
+    import addr_map_pkg::*;
+    
+    import uvmf_base_pkg::*;
+    import qvip_ahb_lite_slave_params_pkg::*;
+    import mvc_pkg::*;
+    import mgc_ahb_seq_pkg::*;
+    import mgc_ahb_v2_0_pkg::*;
+    import qvip_ahb_lite_slave_pkg::*;
+    
+    `include "qvip_ahb_lite_slave_vseq_base.svh"
+    `include "qvip_ahb_lite_slave_test_base.svh"
+    `include "qvip_ahb_lite_slave_example_vseq.svh"
+    
+endpackage: qvip_ahb_lite_slave_test_pkg

snapshots/chipsalliance_adams-bridge_pr66/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvmf_tb/qvip_ahb_lite_slave_vseq_base.svh

@@ -0,0 +1,29 @@
+//
+// File: qvip_ahb_lite_slave_vseq_base.svh
+//
+// Generated from Mentor VIP Configurator (20220406)
+// Generated using Mentor VIP Library ( 2022.2 : 04/20/2022:16:06 )
+//
+class qvip_ahb_lite_slave_vseq_base extends uvm_sequence;
+    `uvm_object_utils(qvip_ahb_lite_slave_vseq_base)
+    // Handles for each of the target (QVIP) sequencers
+    
+    mvc_sequencer ahb_lite_slave_0_sqr;
+    function new
+    (
+        string name = "qvip_ahb_lite_slave_vseq_base"
+    );
+        super.new(name);
+        if ( !uvm_config_db #(mvc_sequencer)::get(null,UVMF_SEQUENCERS,"ahb_lite_slave_0", ahb_lite_slave_0_sqr) )
+        begin
+            `uvm_error("Config Error" , "uvm_config_db #( mvc_sequencer )::get cannot find resource 'ahb_lite_slave_0'" )
+        end
+    endfunction
+    
+    extern task body;
+    
+endclass: qvip_ahb_lite_slave_vseq_base
+
+task qvip_ahb_lite_slave_vseq_base::body;
+endtask: body
+

snapshots/chipsalliance_adams-bridge_pr66/src/abr_libs/uvmf/qvip_ahb_lite_slave_dir/uvmf_tb/test_packages.svh

@@ -0,0 +1,10 @@
+//
+// File: test_packages.svh
+//
+// Generated from Mentor VIP Configurator (20220406)
+// Generated using Mentor VIP Library ( 2022.2 : 04/20/2022:16:06 )
+//
+
+import qvip_ahb_lite_slave_test_pkg::*;
+
+// Add other packages here as required

snapshots/chipsalliance_adams-bridge_pr66/src/sigdecode_h/config/compile.yml

@@ -0,0 +1,48 @@
+# Copyright (C) Microsoft Corporation. All rights reserved.
+
+# Go here for details on compile.yml syntax:
+# https://dev.azure.com/ms-tsd/Ether/_git/sim-tools?path=%2FSourceFileSpec.docx&version=GBmaster
+
+---
+provides: [sigdecode_h_pkg]
+schema_version: 2.4.0
+requires: []
+targets:
+  rtl:
+    directories: [$COMPILE_ROOT/rtl]
+    files:
+      - $COMPILE_ROOT/rtl/sigdecode_h_defines_pkg.sv
+---
+provides: [sigdecode_h]
+schema_version: 2.4.0
+requires:
+  - mldsa_defines
+  - abr_libs
+  - sigdecode_h_pkg
+targets:
+  rtl:
+    directories: [$COMPILE_ROOT/rtl]
+    files:
+      - $COMPILE_ROOT/rtl/sigdecode_h.sv
+      - $COMPILE_ROOT/rtl/sigdecode_h_ctrl.sv
+      
+    tops: [sigdecode_h]
+  rtl_lint:
+    directories: []
+    waiver_files:
+      - $MSFT_REPO_ROOT/src/sigdecode_h/config/design_lint/sigdecode_h/sglint_waivers
+---
+provides: [sigdecode_h_tb]  
+schema_version: 2.4.0
+requires: 
+  - sigdecode_h
+  - sigdecode_h_pkg
+targets:
+  rtl:
+    directories: [$COMPILE_ROOT/tb]
+    files:
+      - $COMPILE_ROOT/tb/sigdecode_h_tb.sv
+    tops: [sigdecode_h_tb]
+  # sim:
+  #   pre_exec: 'echo "[PRE-EXEC] Copying r hex to $PWD" && cp $COMPILE_ROOT/tb/r.hex . && cp $COMPILE_ROOT/tb/z.hex .'
+

snapshots/chipsalliance_adams-bridge_pr66/src/sigdecode_h/config/sigdecode_h_pkg.vf

@@ -0,0 +1,2 @@
++incdir+${ADAMSBRIDGE_ROOT}/src/sigdecode_h/rtl
+${ADAMSBRIDGE_ROOT}/src/sigdecode_h/rtl/sigdecode_h_defines_pkg.sv