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snapshots/pulp-platform_common_cells_pr280/.gitlab-ci.yml

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+# Copyright 2023 ETH Zurich and University of Bologna.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+# Author: Nils Wistoff <nwistoff@iis.ee.ethz.ch>
+
+variables:
+  VSIM: questa-2022.3 vsim -64
+  VLIB: questa-2022.3 vlib
+  VMAP: questa-2022.3 vmap
+  VCOM: questa-2022.3 vcom -64
+  VLOG: questa-2022.3 vlog -64
+  VOPT: questa-2022.3 vopt -64
+
+stages:
+  - test
+
+.test-tpl:
+  stage: test
+  needs:
+  variables:
+    TOPLEVEL: ""
+    PARAM1: ""
+    PARAM2: ""
+  timeout: 10min
+  script:
+    - bender checkout
+    - bender script vsim -t test > compile.tcl
+    - $VSIM -c -quiet -do 'source compile.tcl; quit'
+    - $VSIM -c $TOPLEVEL -voptargs="-timescale 1ns/100ps" -do "run -all" $PARAM1 $PARAM2
+    - (! grep -n "Error:" transcript)
+
+tests:
+  extends: .test-tpl
+  parallel:
+    matrix:
+      - TOPLEVEL:
+          - addr_decode_tb
+          - cb_filter_tb
+          # - cdc_fifo_clearable_tb
+          - clk_int_div_tb
+          - clk_int_div_static_tb
+          - clk_mux_glitch_free_tb
+          - id_queue_tb
+          - isochronous_crossing_tb
+          - passthrough_stream_fifo_tb
+          - popcount_tb
+          - rr_arb_tree_tb
+          - stream_omega_net_tb
+          - stream_register_tb
+          - stream_to_mem_tb
+          - stream_xbar_tb
+          - sub_per_hash_tb
+          - lossy_valid_to_stream_tb
+      - TOPLEVEL: graycode_tb
+        PARAM1: [-GN=1, -GN=2, -GN=3, -GN=4, -GN=8, -GN=16]
+      - TOPLEVEL: fifo_tb
+        PARAM1: [-GDEPTH=1, -GDEPTH=13, -GDEPTH=32 -GFALL_THROUGH=1]
+      # - TOPLEVEL: [cdc_2phase_tb, cdc_2phase_clearable_tb]
+      #   PARAM1: -GUNTIL=1000000
+      # - TOPLEVEL: cdc_fifo_tb
+      #   PARAM1: [-GDEPTH=1, -GDEPTH=2, -GDEPTH=3, -GDEPTH=4, -GDEPTH=5]
+      #   PARAM2: [-GGRAY=0, -GGRAY=1]

snapshots/pulp-platform_common_cells_pr280/Bender.yml

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+package:
+  name: common_cells
+  authors:
+    - "Florian Zaruba <zarubaf@iis.ee.ethz.ch>"
+    - "Fabian Schuiki <fschuiki@iis.ee.ethz.ch>"
+    - "Michael Schaffner <schaffner@iis.ee.ethz.ch>"
+    - "Andreas Kurth <akurth@iis.ee.ethz.ch>"
+    - "Manuel Eggimann <meggimann@iis.ee.ethz.ch>"
+    - "Stefan Mach <smach@iis.ee.ethz.ch>"
+    - "Wolfgang Roenninger <wroennin@student.ethz.ch>"
+    - "Thomas Benz <tbenz@iis.ee.ethz.ch>"
+
+dependencies:
+  common_verification: { git: "https://github.com/pulp-platform/common_verification.git", version: 0.2.0 }
+  tech_cells_generic: { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.11 }
+
+export_include_dirs:
+  - include
+
+sources:
+  # Source files grouped in levels. Files in level 0 have no dependencies on files in this package.
+  # Files in level 1 only depend on files in level 0, files in level 2 on files in levels 1 and 0,
+  # etc. Files within a level are ordered alphabetically.
+
+  # Level 0
+  - src/binary_to_gray.sv
+
+  - target: not(all(xilinx,vivado_ipx))
+    files:
+      - src/cb_filter_pkg.sv
+      - src/cc_onehot.sv
+      - src/cdc_reset_ctrlr_pkg.sv
+      - src/cf_math_pkg.sv
+      - src/clk_int_div.sv
+      - src/credit_counter.sv
+      - src/delta_counter.sv
+      - src/ecc_pkg.sv
+      - src/edge_propagator_tx.sv
+      - src/exp_backoff.sv
+      - src/fifo_v3.sv
+      - src/gray_to_binary.sv
+      - src/heaviside.sv
+      - src/isochronous_4phase_handshake.sv
+      - src/isochronous_spill_register.sv
+      - src/lfsr.sv
+      - src/lfsr_16bit.sv
+      - src/lfsr_8bit.sv
+      - src/lossy_valid_to_stream.sv
+      - src/mv_filter.sv
+      - src/onehot_to_bin.sv
+      - src/plru_tree.sv
+      - src/passthrough_stream_fifo.sv
+      - src/popcount.sv
+      - src/ring_buffer.sv
+      - src/rr_arb_tree.sv
+      - src/rstgen_bypass.sv
+      - src/serial_deglitch.sv
+      - src/shift_reg.sv
+      - src/shift_reg_gated.sv
+      - src/spill_register_flushable.sv
+      - src/stream_demux.sv
+      - src/stream_filter.sv
+      - src/stream_fork.sv
+      - src/stream_intf.sv
+      - src/stream_join_dynamic.sv
+      - src/stream_mux.sv
+      - src/stream_throttle.sv
+      - src/sub_per_hash.sv
+      - src/sync.sv
+      - src/sync_wedge.sv
+      - src/unread.sv
+      - src/read.sv
+      # Level 1
+      - src/addr_decode_dync.sv
+      - src/boxcar.sv
+      - src/cdc_2phase.sv
+      - src/cdc_4phase.sv
+      - src/clk_int_div_static.sv
+      - src/trip_counter.sv
+      # Level 2
+      - src/addr_decode.sv
+      - src/addr_decode_napot.sv
+      - src/multiaddr_decode.sv
+  - target: not(all(xilinx,vivado_ipx))
+    files:
+      - src/cb_filter.sv
+      - src/cdc_fifo_2phase.sv
+      - src/clk_mux_glitch_free.sv
+      - src/counter.sv
+      - src/ecc_decode.sv
+      - src/ecc_encode.sv
+      - src/edge_detect.sv
+      - src/lzc.sv
+      - src/max_counter.sv
+      - src/rstgen.sv
+      - src/spill_register.sv
+      - src/stream_delay.sv
+      - src/stream_fifo.sv
+      - src/stream_fork_dynamic.sv
+      - src/stream_join.sv
+      # Level 2
+      - src/cdc_reset_ctrlr.sv
+      - src/cdc_fifo_gray.sv
+      - src/fall_through_register.sv
+      - src/id_queue.sv
+      - src/stream_to_mem.sv
+      - src/stream_arbiter_flushable.sv
+      - src/stream_fifo_optimal_wrap.sv
+      - src/stream_register.sv
+      - src/stream_xbar.sv
+      # Level 3
+      - src/cdc_fifo_gray_clearable.sv
+      - src/cdc_2phase_clearable.sv
+      - src/mem_to_banks_detailed.sv
+      - src/stream_arbiter.sv
+      - src/stream_omega_net.sv
+      # Level 4
+      - src/mem_to_banks.sv
+
+  - target: all(simulation, not(verilator))
+    files:
+      - src/deprecated/sram.sv
+
+  - target: test
+    files:
+      # Level 0
+      - test/addr_decode_tb.sv
+      - test/cb_filter_tb.sv
+      - test/cdc_2phase_tb.sv
+      - test/cdc_2phase_clearable_tb.sv
+      - test/cdc_fifo_tb.sv
+      - test/cdc_fifo_clearable_tb.sv
+      - test/fifo_tb.sv
+      - test/graycode_tb.sv
+      - test/id_queue_tb.sv
+      - test/passthrough_stream_fifo_tb.sv
+      - test/popcount_tb.sv
+      - test/rr_arb_tree_tb.sv
+      - test/stream_test.sv
+      - test/stream_register_tb.sv
+      - test/stream_to_mem_tb.sv
+      - test/sub_per_hash_tb.sv
+      # Level 1
+      - test/isochronous_crossing_tb.sv
+      - test/stream_omega_net_tb.sv
+      - test/stream_xbar_tb.sv
+      - test/clk_int_div_tb.sv
+      - test/clk_int_div_static_tb.sv
+      - test/clk_mux_glitch_free_tb.sv
+      - test/lossy_valid_to_stream_tb.sv
+
+
+  - target: synth_test
+    files:
+      # Level 0
+      - test/cdc_2phase_synth.sv
+      - test/id_queue_synth.sv
+      - test/stream_arbiter_synth.sv
+      - test/ecc_synth.sv
+      # Level 1
+      - test/synth_bench.sv
+
+  # Deprecated modules
+  # Level 0
+  - src/deprecated/clock_divider_counter.sv
+  - src/deprecated/clk_div.sv
+  - src/deprecated/find_first_one.sv
+  - src/deprecated/generic_LFSR_8bit.sv
+  - src/deprecated/generic_fifo.sv
+  - src/deprecated/prioarbiter.sv
+  - src/deprecated/pulp_sync.sv
+  - src/deprecated/pulp_sync_wedge.sv
+  - src/deprecated/rrarbiter.sv
+  # Level 1
+  - src/deprecated/clock_divider.sv
+  - src/deprecated/fifo_v2.sv
+  # Level 2
+  - src/deprecated/fifo_v1.sv
+
+  # Depend on deprecated modules
+  - src/edge_propagator_ack.sv
+  - src/edge_propagator.sv
+  - src/edge_propagator_rx.sv

snapshots/pulp-platform_common_cells_pr280/CHANGELOG.md

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+# Changelog
+All notable changes to this project will be documented in this file.
+
+The format is based on [Keep a Changelog](http://keepachangelog.com/en/1.0.0/)
+and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0.html).
+
+## 1.39.0 - 2025-11-20
+### Added
+- `boxcar`: Add boxcar function to compose bit masks
+- `heaviside`: Add Heaviside function to compose bit masks
+- `ring_buffer`: Add ring buffer with sequential write and random reads
+- `trip_counter`: Add counter with 'trip' output when reaching threshold value
+
+### Changed
+- `cb_filter`, `id_queue`, `lzc`, `rr_arb_tree`: Speed up Verilator simulation
+- `cdc_fifo_gray*`, `isochronous_spill_register`: Change flip-flops without to flip-flops with reset
+- `isochronous_spill_register`: Remove unnecessary data stability assertions
+- `addr_decode*`: Change assumed integer index to arbitrary type (default remains integer)
+
+### Fixed
+- `id_queue`: Fix struct access
+- `cdc_fifo_gray*`: Fix Spyglass linting edge case
+- `lzc`: Fix assertion for degenerate case `WIDTH == 0`
+- Fix Verilator compilation by adding guard statements
+
+## 1.38.0 - 2025-02-28
+### Changed
+- Assertions no longer disabled for Verilator. Define `ASSERTS_OFF` to disable.
+- Define `ASSERTS_OVERRIDE_ON` to override any defines that turn assertions off otherwise.
+- `id_queue`: Parametrize number of compare ports.
+- `assertions.svh`: Add optional argument to assertion macros to display custom error message.
+- `stream_to_mem`: Disable assertions during reset.
+- `addr_decode_dync`, `cdc_fifo_gray_clearable`, `multiaddr_decode`, `spill_register_flushable`: Promote `$warning` to `$error`.
+- `rr_arb_tree`, `stream_omega_net`, `stream_xbar`: Remove default assertion disable.
+
+### Fixed
+- `delta_counter`: Fix inverted reset.
+- `stream_join_dynamic`: Handshake only selected streams.
+- Various tool compatibility improvements.
+
+## 1.37.0 - 2024-07-18
+### Added
+- `credit_counter`: Add up/down counter for credit.
+
+### Fixed
+- `mem_to_banks_detailed`: Ensure no spurious response after full dead write.
+
+## 1.36.0 - 2024-07-08
+### Fixed
+- `registers`: Fix else statement in FFARNC macro.
+- `stream_arbiter_flushable`: Do not lock priority arbiter.
+
+## 1.35.0 - 2024-04-22
+### Changed
+- `id_queue`: Add parameter to cut a critical path.
+
+## 1.34.0 - 2024-04-09
+### Changed
+- `stream_xbar`: Add payload assertion stability mask.
+
+## 1.33.1 - 2024-03-16
+### Fixed
+- `stream_omega_net`: Fix assertion.
+- Revert gitlab-ci trigger condition to `pull_request`.
+
+## 1.33.0 - 2024-03-07
+### Added
+- Add `passthrough_stream_fifo`: Stream FIFO which does not cut the timing path, this allows it to do a simultaneous push and pop when full.
+- Registers: Add FFARNC macro: Flip-Flop with asynchronous active-low reset and synchronous clear.
+
+### Changed
+- Enable assertions in verilator.
+- Change `pragma translate_off` statements to ```ifndef SYNTHESIS`` according to IEEE 1364.1-2005 spec 6.3.2.
+- `plru_tree`: Add assertion that output is onehot.
+- Update CI trigger condition.
+
+### Fixed
+- `onehot_to_bin`: Fix width mismatch in assignment.
+- `plru_tree`: Improve tool compatibility.
+- `stream_xbar`: Fix masked assertion.
+
+## 1.32.0 - 2023-09-26
+### Added
+- Add `stream_join_dynamic`: `stream_join` with a dynamically configurable subset selection.
+- Add `multiaddr_decode`: Address map decoder using NAPOT regions and allowing for multiple address inputs.
+- Add `addr_decode_dync`: `addr_decode` with support for dynamic online configuration.
+
+### Changed
+- `mem_to_banks`: Change default value for `NumBanks` from `0` to `1` to avoid division by zero.
+
+## 1.31.1 - 2023-08-09
+### Fixed
+- `mem_to_banks`: Keep defaut values for localparams
+
+## 1.31.0 - 2023-08-08
+### Added
+- Add `mem_to_banks_detailed`: `mem_to_banks` with detailed response signals
+
+### Fixed
+- `unread`: Add dummy signal assignment when targeting Vivado to avoid blackbox inference
+
+## 1.30.0 - 2023-06-09
+### Added
+- Add `lossy_valid_to_stream`: A converter between valid-only protocols and ready-valid where the latest transaction overwrites the most recently queue one.
+- Add `clk_int_div_static`: A wrapper for `clk_int_div` for static clock division.
+
+### Changed
+- `popcount`: Refactor and support all input widths.
+- `clk_int_div`: Support clock output during reset.
+- `stream_delay`: Support larger counts.
+
+### Fixed
+- `clk_int_div`: Fix possible deadlock and avoid hold issues.
+
+## 1.29.0 - 2023-04-14
+### Added
+- Add `shift_reg_gated`: Shift register with ICG for arbitrary types.
+
+### Changed
+- CI: Run testbenches in `test/` on internal gitlab mirror.
+- `fifo_tb`: Add test for DEPTH not power of two.
+
+### Fixed
+- `clk_int_div`: Allow configuration while clock is disabled.
+- `mem_to_banks`: Cut possible timing loop for HideStrb feature.
+- Improved tool compatibility (Verilator, Questasim, Synopsys).
+
+## 1.28.0 - 2022-12-15
+### Added
+- Add `clk_mux_glitch_free`: A glitch-free clock multiplexer.
+
+## 1.27.1 - 2022-12-06
+### Fixed
+- `fall_through_register`: Remove superfluous `$size()` call for tool compatibility
+
+## 1.27.0 - 2022-12-01
+### Added
+- Add `mem_to_banks`: split memory access over multiple parallel banks. Moved from the `AXI4+ATOP`
+  [`axi_to_mem`](https://github.com/pulp-platform/axi/blob/2f395b176bee1c769c80f060a4345fda965bb04b/src/axi_to_mem.sv#L563) module.
+- Add `read`: dummy module that prevents a signal from being removed during synthesis
+
+### Changed
+- `stream_fifo_optimal_wrap`: Remove asserts
+- `fall_through_register`: Update fifo to `fifo_v3`
+
+### Fixed
+- FuseSoC: Add `assertions.svh`
+
+## 1.26.0 - 2022-08-26
+### Added
+- Add `stream_throttle`: restricts the number of outstanding transfers in a stream.
+
+### Changed
+- Allow out-of-bounds (i.e. `'0`) top end address in addr_map of `addr_decode` module for end of address space.
+- Update CI.
+
+## 1.25.0 - 2022-08-10
+### Added
+- Add `addr_decode_napot`: variant of `addr_decode` which uses a base address and mask instead of a start and end address.
+- Add `stream_fifo_optimal_wrap`: instantiates a more optimal `spill_register` instead of a `stream_fifo` for `depth == 2`.
+
+### Changed
+- Make `stream_register` truly stream by replacing internal FIFO with FFs.
+- Avoid using `$bits()` call in `id_queue`'s parameters.
+- Remove `cb_filter` and `cb_filter_pkg` from from Vivado IP packager project sources due to compatibility issues.
+- Use `tc_clk_mux` as glitch-free muxes in `rstgen_bypass` to avoid combinational glitches.
+- Avoid program blocks in testbenches for simulator compatibility.
+
+### Fixed
+- Update `src_files.yml` and `common_cells.core`
+
+## 1.24.1 - 2022-04-13
+### Fixed
+- Fix typos in `Bender.yml` and `src_files.yml`
+
+## 1.24.0 - 2022-03-31
+### Added
+- Add `edge_propagator_ack`: Edge/pulse propagator with sender-synchronous receive-acknowledge
+  output.  `edge_propagator` is now implemented by instantiating `edge_propagator_ack`.
+- Add `4phase_cdc`: A 4 phase handshaking CDC that allows glitch-free resetting (used internally in the new clearable CDC IPs).
+- Add one-sided clearable and/or async resettable flavors of 2phase CDC (`cdc_2phase_clearable`) and gray-counting FIFO CDCs (`cdc_fifo_gray_clearable`).
+- Add reset CDC controller `cdc_reset_ctrl` that supports reset/synchronous clear sequencing across clock domain crossings (used internally in clearable CDC IPs).
+- Add `clk_int_div` arbitrary integer clock divider with *at-runtime*
+  configurable divider selection and glitch-free, 50%duty cycle output clock.
+- Add an assertion to the `lzc` to verify parameters.
+
+### Fixed
+- Correct reset polarity in assertions in `isochronous_4phase_handshake` and `isochronous_spill_register`
+- Fix compatibility of `sub_per_hash` constructs with Verilator
+
+### Changed
+- Add `dont_touch` and `async_reg` attribute to FFs in `sync` cell.
+- Improved reset behavior documentation (in module header) of existing CDC IPs.
+- Deprecated flawed `clk_div` module and add elaboration warning message that
+  will be shown for existing designs (can be disabled with optional
+  instantiation parameter).
+- Add optional `Seed` parameter to `stream_delay` module
+- Update `tech_cells_generic` to `0.2.9`
+
+## 1.23.0 - 2021-09-05
+### Added
+- Add `cc_onehot`
+- `isochronous_4phase_handshake`: Isochronous clock domain crossing cutting all paths using a 4-phase handshake.
+- Changed `isochronous_spill_register_tb` to `isochronous_crossing_tb` also covering the `isochronous_4phase_handshake`
+  module.
+- Make reset value of `sync` module parameterizable.
+
+### Changed
+- `id_queue`: Allow simultaneous input and output requests in `FULL_BW` mode
+
+## 1.22.1 - 2021-06-14
+### Fixed
+- Remove breaking change of `spill_register`
+
+## 1.22.0 - 2021-06-09
+### Added
+- Add `spill_register_flushable`
+
+### Changed
+- `registers.svh`: Merge explicit and implicit register variants into `` `FF `` and `` `FFL `` macros
+- `rr_arb_tree`: Allow flushing locked decision
+- Improved `verific` compatibility
+
+## 1.21.0 - 2021-01-28
+### Changed
+- Remove `timeprecision/timeunit` arguments
+- Update `common_verification` to `0.2.0`
+- Update `tech_cells_generic` to `0.2.3`
+
+## 1.20.1 - 2021-01-21
+### Changed
+- `id_queue`: Replace default or reset value of signals that were assigned `'x` with `'0`.
+- `id_queue`: Use `cf_math_pkg::idx_width()` for computation of localparams.
+
+### Fixed
+- Add `XSIM` define guard for statements incompatible with `xsim`.
+
+## 1.20.0 - 2020-11-04
+### Added
+- assertions: Assertion include header with macros (from lowrisc)
+
+### Changed
+- `sram.sv`: Deprecated as it has been moved to `tech_cells_generic`
+
+### Fixed
+- `stream_register`: Fix `DATA_WIDTH` of instantiated FIFO.
+- `stream_xbar`: Add missing argument in assertion error string.
+- Lint style fixes
+- `stream_omega`: Fix parse issue with verible.
+- `src_files.yml`: Fix compile order and missing modules.
+
+## 1.19.0 - 2020-05-25
+### Added
+- stream_to_mem: Allows to use memories with flow control (req/gnt) for requests but
+  without flow control for output data to be used in streams.
+- isochronous_spill_register: Isochronous clock domain crossing cutting all paths.
+- `rr_arb_tree_tb`: Systemverilog testbench for `rr_arb_tree`, which checks for fair throughput.
+- `cf_math_pkg::idx_width`: Constant function for defining the binary representation width
+  of an index signal.
+
+### Changed
+- `addr_decode`: Use `cf_math_pkg::idx_width` for computing the index width, inline documentation.
+- `lzc`: Use `cf_math_pkg::idx_width` for computing the index width, inline documentation.
+- `Bender`: Change levels of modules affected by depending on `cf_math_pkg::idx_width()`.
+- `stream_xbar`: Fully connected stream bassed interconnect with variable number of inputs and outputs.
+- `stream_xbar`: Fully connected stream-bassed interconnect with a variable number of inputs and outputs.
+- `stream_omega_net`: Stream-based network implementing an omega topology. Variable number of inputs,
+  outputs and radix. Topology is isomorphic to a butterfly network.
+
+### Fixed
+- Improve tool compatibility.
+- `rr_arb_tree`: Properly degenerate `rr_i` and `idx_o` signals.
+- `rr_arb_tree`: Add parameter `FairArb` to distribute throughput of input requests evenly when
+  not all inputs have requests active.
+- `stream_demux`: Properly degenerate `inp_sel_i` signal.
+
+## 1.18.0 - 2020-04-15
+### Added
+- stream_fork_dynamic: Wrapper around `stream_fork` for partial forking.
+- stream_join: Join multiple Ready/Valid handshakes to one common handshake.
+- SECDED (Single Error Correction, Double Error Detection) encoder and decoder
+- SECDED Verilator-based testbench
+- Travis build for SECDED module
+
+## 1.17.0 - 2020-04-09
+### Added
+- stream_fifo: Ready/Valid handshake wrapper around `fifo_v3`
+
+## 1.16.4 - 2020-03-02
+### Fixed
+- id_queue: Fix generation of `head_tail_q` registers
+
+## 1.16.3 - 2020-02-11
+### Fixed
+- Handle degenerated `addr_decode` with `NoIndices == 1`, change default parameters to `32'd0`
+
+## 1.16.2 - 2020-02-04
+### Fixed
+- Fix author section in Bender.yml
+
+## 1.16.1 - 2020-02-03
+### Fixed
+- `rr_arb_tree`: Add guard SVA statement for Verilator
+- Added missing sources in `Bender.yml` and `src_files.yml`
+
+## 1.16.0 - 2020-01-13
+### Fixed
+- Handle degenerated `onehot_to_bin` with `ONEHOT_WIDTH == 1`
+- Handle degenerated `id_queue` with `CAPACITY == 1` or `HT_CAPACITY == 1`
+- Fix `cdc_fifo_gray` to be a safe clock domain crossing (CDC)
+
+## 1.15.0 - 2019-12-09
+### Added
+- Added address map decoder module
+
+### Fixed
+- Handle degenerated `lzc` with `WIDTH == 1`
+
+## 1.14.0 - 2019-10-08
+
+### Added
+- Added spubstitution-permutation hash function module
+- Added couning-bloom-filter module
+- `spill_register`: Added Bypass parameter
+- `counter`: Added sticky overflow
+- Added counter with variable delta
+- Added counter that tracks its maximum value
+
+### Changed
+- Added formal testbench for `fifo` and `fall_through_regsiter`
+
+## 1.13.1 - 2019-06-01
+
+### Changed
+
+- Fix path in `src_files.yml` for `stream_arbiter` and `stream_arbiter_flushable`
+
+## 1.13.0 - 2019-05-29
+
+### Added
+
+- Added exponential backoff window module
+- Added parametric Galois LFSR module with optional whitening feature
+- Added `cf_math_pkg`: Constant Function implementations of mathematical functions for HDL elaboration
+
+### Changed
+- Parametric payload data type for `rr_arb_tree`
+
+### Deprecated
+- The following arbiter implementations are deprecated and superseded by `rr_arb_tree`:
+- Priority arbiter `prioarbiter`
+- Round-robin arbiter `rrarbiter`
+
+### Fixed
+
+## 1.12.0 - 2019-04-09
+
+### Added
+- Add priority arbiter
+- Add Pseudo Least Recently Used tree
+- Add round robin arbiter mux tree
+
+### Changed
+- Add selectable arbiter implementation for `stream_arbiter` and `stream_arbiter_flushable`. One can choose between priority (`prio`) and round-robin arbitration (`rr`).
+- Add `$onehot0` assertion in one-hot to bin
+- Rework `rrarbiter` unit (uses `rr_arb_tree` implementation underneath)
+
+## 1.11.0 - 2019-03-20
+
+### Added
+- Add stream fork
+- Add fall-through register
+- Add stream filter
+- Add ID queue
+
+### Changed
+- `sync_wedge` use existing synchronizer. This defines a single place where a tech-specific synchronizer can be defined.
+
+### Fixed
+- Fix FIFO push and pop signals in `stream_register` to observe interface prerequisites.
+- In `fifo_v3`, fix data output when pushing into empty fall-through FIFO. Previously, the data
+  output of an empty fall-through FIFO with data at its input (and `push_i=1`) depended on
+  `pop_i`: When `pop_i=0`, old, invalid data were visible at the output (even though `empty_o=0`,
+  indicating that the data output is valid). Only when `pop_i=1`, the data from the input fell
+  through. One consequence of this bug was that `data_o` of the `fall_through_register` could change
+  while `valid_o=1`, violating the basic stream specification.
+
+## 1.10.0 - 2018-12-18
+
+### Added
+- Add `fifo_v3` with generic fill count
+- Add 16 bit LFSR
+- Add stream delayer
+- Add stream arbiter
+- Add register macros for RTL
+- Add shift register
+
+### Changed
+- Make number of registers of `rstgen_bypass` a parameter.
+
+### Fixed
+- Fix `valid_i` and `grant_i` guarantees in `generic_fifo` for backward compatibility.
+- LZC: Synthesis of streaming operators in ternary operators
+- Add missing entry for `popcount` to `Bender.yml`.
+- Add default values for parameters to improve compatibility with Synopsys DC and Vivado.
+
+## 1.9.0 - 2018-11-02
+
+### Added
+- Add popcount circuit `popcount`
+
+## 1.8.0 - 2018-10-15
+
+### Added
+- Add lock feature to the rrarbiter. This prevents the arbiter to change the decision when we have pending requests that remain unaknowledged for several cycles.
+- Add deglitching circuit
+- Add generic clock divider
+- Add edge detecter as alias to sync_wedge (name is more expressive)
+- Add generic counter
+- Add moving deglitcher
+
+## 1.7.6 - 2018-09-27
+
+### Added
+- Add reset synchronizer with explicit reset bypass in testmode
+
+## 1.7.5 - 2018-09-06
+### Fixed
+- Fix incompatibility with verilator
+- Fix dependency to open-source repo
+
+## 1.7.4 - 2018-09-06
+- Fix assertions in `fifo_v2` (write on full / read on empty did not trigger properly)
+
+## 1.7.3 - 2018-08-27
+### Fixed
+- Use proper `fifo_v2` in `generic_fifo` module.
+
+## 1.7.2 - 2018-08-27
+### Added
+- Almost full/empty flags to FIFO, as `fifo_v2`.
+
+### Changed
+- FIFO moved to `fifo_v1` and instantiates `fifo_v2`.
+
+## 1.7.1 - 2018-08-27
+### Fixed
+- Revert breaking changes to `fifo`.
+
+## 1.7.0 - 2018-08-24
+### Added
+- Add stream register (`stream_register`).
+- Add stream multiplexer and demultiplexer (`stream_mux`, `stream_demux`).
+- Add round robin arbiter (`rrarbiter`).
+- Add leading zero counter (`lzc`).
+
+### Changed
+- Deprecate `find_first_one` in favor of `lzc`.
+
+## 1.6.0 - 2018-04-03
+### Added
+- Add binary to Gray code converter.
+- Add Gray code to binary converter.
+- Add Gray code testbench.
+- Add CDC FIFO based on Gray counters. This is a faster alternative to the 2-phase FIFO which also works if a domain's clock has stopped.
+
+### Changed
+- Rename `cdc_fifo` to `cdc_fifo_2phase`.
+- Adjust CDC FIFO testbench to cover both implementations.
+
+## 1.5.4 - 2018-03-31
+### Changed
+- Replace explicit clock gate in `fifo` with implicit one.
+
+## 1.5.3 - 2018-03-16
+### Changed
+- Remove duplicate deprecated modules.
+
+## 1.5.2 - 2018-03-16
+### Changed
+- Remove deprecated `rstgen` and fix interface.
+
+## 1.5.1 - 2018-03-16
+### Changed
+- Remove deprecated `onehot_to_bin`.
+
+## 1.5.0 - 2018-03-14
+### Added
+- Add behavioural SRAM model
+
+## 1.4.0 - 2018-03-14
+### Added
+- Clock domain crossing FIFO
+
+### Changed
+- Re-name new sync modules to resolve namespace collisions
+
+## 1.3.0 - 2018-03-12
+### Added
+- 2-phase clock domain crossing
+- Add old common cells as deprecated legacy modules
+
+## 1.2.3 - 2018-03-09
+### Added
+- Backwards compatibility wrapper for `generic_LFSR_8bit`
+
+## 1.2.2 - 2018-03-09
+### Added
+- Backwards compatibility wrapper for `generic_fifo`
+
+## 1.2.1 - 2018-03-09
+### Fixed
+- Fix an issue in the spill register which causes transactions to be lost
+
+## 1.2.0 - 2018-03-09
+### Added
+- Add spill register
+
+## 1.1.0 - 2018-03-06
+### Added
+- Find first zero
+
+## 1.0.0 - 2018-03-02
+### Added
+- Re-implementation of the generic FIFO supporting all kinds of use-cases
+- Testbench for FIFO
+
+### Changed
+- Re-formatting and artistic code clean-up
+
+## 0.1.0 - 2018-02-23
+### Added
+- Fork of PULP common cells repository

snapshots/pulp-platform_common_cells_pr280/Makefile

@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: Apache-2.0
+
+VERILATOR ?= verilator
+
+all: ecc_encode ecc_decode
+
+ecc_%: test/ecc/ecc_%.cpp test/ecc/ecc.cpp src/ecc_pkg.sv src/ecc_%.sv
+	$(VERILATOR) --cc $^ --top-module $@ --trace --exe
+	cd obj_dir && make -f V$@.mk > /dev/zero

snapshots/pulp-platform_common_cells_pr280/README.md

@@ -0,0 +1,209 @@
+[![Build Status](https://github.com/pulp-platform/common_cells/actions/workflows/ci.yml/badge.svg?branch=master)](https://github.com/pulp-platform/common_cells/actions/workflows/ci.yml?query=branch%3Amaster)
+[![GitHub tag (latest SemVer)](https://img.shields.io/github/v/tag/pulp-platform/common_cells?color=blue&label=current&sort=semver)](CHANGELOG.md)
+[![SHL-0.51 license](https://img.shields.io/badge/license-SHL--0.51-green)](LICENSE)
+
+# Common Cells Repository
+
+Maintainer: Philippe Sauter <phsauter@iis.ee.ethz.ch>
+
+This repository contains commonly used cells and headers for use in various projects.
+
+## Cell Contents
+
+This repository currently contains the following cells, ordered by categories.
+Please note that cells with status *deprecated* are not to be used for new designs and only serve to provide compatibility with old code.
+
+### Clocks and Resets
+
+| Name                                                               | Description                                                                           | Status       | Superseded By                       |
+|--------------------------------------------------------------------|---------------------------------------------------------------------------------------|--------------|-------------------------------------|
+| [`clk_int_div`](src/clk_int_div.sv)                                | Arbitrary integer clock divider with config interface and 50% output clock duty cycle | active       |                                     |
+| [`clk_int_div_static`](src/clk_int_div_static.sv)                  | A convenience wrapper around `clk_int_div` with static division factor.               | active       |                                     |
+| [`clk_div`](src/deprecated/clk_div.sv)                             | Clock divider with integer divisor                                                    | *deprecated* | [`clk_int_div`](src/clk_int_div.sv) |
+| [`clock_divider`](src/deprecated/clock_divider.sv)                 | Clock divider with configuration registers                                            | *deprecated* | [`clk_int_div`](src/clk_int_div.sv) |
+| [`clock_divider_counter`](src/deprecated/clock_divider_counter.sv) | Clock divider using a counter                                                         | *deprecated* | [`clk_int_div`](src/clk_int_div.sv) |
+| [`rstgen`](src/rstgen.sv)                                          | Reset synchronizer                                                                    | active       |                                     |
+| [`rstgen_bypass`](src/rstgen_bypass.sv)                            | Reset synchronizer with dedicated test reset bypass                                   | active       |                                     |
+
+### Clock Domains and Asynchronous Crossings
+
+| Name                                                                  | Description                                                                                   | Status       | Superseded By                     |
+|-----------------------------------------------------------------------|-----------------------------------------------------------------------------------------------|--------------|-----------------------------------|
+| [`cdc_4phase`](src/cdc_4phase.sv)                                     | Clock domain crossing using 4-phase handshake, with ready/valid interface                     | active       |                                   |
+| [`cdc_2phase`](src/cdc_2phase.sv)                                     | Clock domain crossing using two-phase handshake, with ready/valid interface                   | active       |                                   |
+| [`cdc_2phase_clearable`](src/cdc_2phase_clearable.sv)                 | Identical to `cdc_2phase` but supports one-sided async/sync resetting of either src or dst    | active       |                                   |
+| [`cdc_fifo_2phase`](src/cdc_fifo_2phase.sv)                           | Clock domain crossing FIFO using two-phase handshake, with ready/valid interface              | active       |                                   |
+| [`cdc_fifo_gray`](src/cdc_fifo_gray.sv)                               | Clock domain crossing FIFO using a gray-counter, with ready/valid interface                   | active       |                                   |
+| [`cdc_fifo_gray_clearable`](src/cdc_fifo_gray_clearable.sv)           | Identical to `cdc_fifo_gray` but supports one-sided async/sync resetting of either src or dst | active       |                                   |
+| [`cdc_reset_ctrlr`](src/cdc_reset_ctrlr.sv)                           | Lock-step reset sequencer accross clock domains (internally used by clearable CDCs)           | active       |                                   |
+| [`clk_mux_glitch_free`](src/clk_mux_glitch_free.sv)                   | A glitch-free clock multiplexer with parametrizeable number of inputs.                        | active       |                                   |
+| [`edge_detect`](src/edge_detect.sv)                                   | Rising/falling edge detector                                                                  | active       |                                   |
+| [`edge_propagator`](src/edge_propagator.sv)                           | Propagates a single-cycle pulse across an asynchronous clock domain crossing                  | active       |                                   |
+| [`edge_propagator_ack`](src/edge_propagator_ack.sv)                   | `edge_propagator` with sender-synchronous acknowledge pin (flags received pulse)              | active       |                                   |
+| [`edge_propagator_rx`](src/edge_propagator_rx.sv)                     | Receive slice of `edge_propagator`, requires only the receiver clock                          | active       |                                   |
+| [`edge_propagator_tx`](src/edge_propagator_tx.sv)                     | Transmit slice of `edge_propagator`, requires only the sender clock                           | active       |                                   |
+| [`isochronous_spill_register`](src/isochronous_spill_register.sv)     | Isochronous clock domain crossing and full handshake (like `spill_register`)                  | active       |                                   |
+| [`isochronous_4phase_handshake`](src/isochronous_4phase_handshake.sv) | Isochronous four-phase handshake.                                                             | active       |                                   |
+| [`pulp_sync`](src/deprecated/pulp_sync.sv)                            | Serial line synchronizer                                                                      | *deprecated* | [`sync`](src/sync.sv)             |
+| [`pulp_sync_wedge`](src/deprecated/pulp_sync_wedge.sv)                | Serial line synchronizer with edge detector                                                   | *deprecated* | [`sync_wedge`](src/sync_wedge.sv) |
+| [`serial_deglitch`](src/serial_deglitch.sv)                           | Serial line deglitcher                                                                        | active       |                                   |
+| [`sync`](src/sync.sv)                                                 | Serial line synchronizer                                                                      | active       |                                   |
+| [`sync_wedge`](src/sync_wedge.sv)                                     | Serial line synchronizer with edge detector                                                   | active       |                                   |
+
+### Counters and Shift Registers
+
+| Name                                                       | Description                                                         | Status       | Superseded By                   |
+| ---------------------------------------------------------- | ------------------------------------------------------------------- | ------------ | ------------------------------- |
+| [`counter`](src/counter.sv)                                | Generic up/down counter with overflow detection                     | active       |                                 |
+| [`credit_counter`](src/credit_counter.sv)                  | Up/down counter for credit                                          | active       |                                 |
+| [`delta_counter`](src/delta_counter.sv)                    | Up/down counter with variable delta and overflow detection          | active       |                                 |
+| [`generic_LFSR_8bit`](src/deprecated/generic_LFSR_8bit.sv) | 8-bit linear feedback shift register (LFSR)                         | *deprecated* | [`lfsr_8bit`](src/lfsr_8bit.sv) |
+| [`lfsr_8bit`](src/lfsr_8bit.sv)                            | 8-bit linear feedback shift register (LFSR)                         | active       |                                 |
+| [`lfsr_16bit`](src/lfsr_16bit.sv)                          | 16-bit linear feedback shift register (LFSR)                        | active       |                                 |
+| [`lfsr`](src/lfsr.sv)                                      | 4...64-bit parametric Galois LFSR with optional whitening feature   | active       |                                 |
+| [`max_counter`](src/max_counter.sv)                        | Up/down counter with variable delta that tracks its maximum value   | active       |                                 |
+| [`mv_filter`](src/mv_filter.sv)                            | **ZARUBAF ADD DESCRIPTION**                                         | active       |                                 |
+| [`trip_counter`](src/trip_counter.sv)                      | Counter that resets automatically when it reaches a specified bound | active       |                                 |
+
+### Data Path Elements
+
+| Name                                                           | Description                                                                                               | Status       | Superseded By                       |
+|----------------------------------------------------------------|-----------------------------------------------------------------------------------------------------------|--------------|-------------------------------------|
+| [`addr_decode`](src/addr_decode.sv)                            | Address map decoder                                                                                       | active       |                                     |
+| [`addr_decode_dync`](src/addr_decode_dync.sv)                  | Address map decoder extended to support dynamic online configuration                                      | active       |                                     |
+| [`addr_decode_napot`](src/addr_decode_napot.sv)                | Address map decoder using naturally-aligned power of two (NAPOT) regions                                  | active       |                                     |
+| [`multiaddr_decode`](src/multiaddr_decode.sv)                  | Address map decoder using NAPOT regions and allowing for multiple address inputs                          | active       |                                     |
+| [`ecc_decode`](src/ecc_decode.sv)                              | SECDED Decoder (Single Error Correction, Double Error Detection)                                          | active       |                                     |
+| [`ecc_encode`](src/ecc_encode.sv)                              | SECDED Encoder (Single Error Correction, Double Error Detection)                                          | active       |                                     |
+| [`binary_to_gray`](src/binary_to_gray.sv)                      | Binary to gray code converter                                                                             | active       |                                     |
+| [`find_first_one`](src/deprecated/find_first_one.sv)           | Leading-one finder / leading-zero counter                                                                 | *deprecated* | [`lzc`](src/lzc.sv)                 |
+| [`gray_to_binary`](src/gray_to_binary.sv)                      | Gray code to binary converter                                                                             | active       |                                     |
+| [`lzc`](src/lzc.sv)                                            | Leading/trailing-zero counter                                                                             | active       |                                     |
+| [`onehot_to_bin`](src/onehot_to_bin.sv)                        | One-hot to binary converter                                                                               | active       |                                     |
+| [`shift_reg`](src/shift_reg.sv)                                | Shift register for arbitrary types                                                                        | active       |                                     |
+| [`shift_reg_gated`](src/shift_reg_gated.sv)                    | Shift register with ICG for arbitrary types                                                               | active       |                                     |
+| [`rr_arb_tree`](src/rr_arb_tree.sv)                            | Round-robin arbiter for req/gnt and vld/rdy interfaces with optional priority                             | active       |                                     |
+| [`rrarbiter`](src/deprecated/rrarbiter.sv)                     | Round-robin arbiter for req/ack interface with look-ahead                                                 | *deprecated* | [`rr_arb_tree`](src/rr_arb_tree.sv) |
+| [`prioarbiter`](src/deprecated/prioarbiter.sv)                 | Priority arbiter arbiter for req/ack interface with look-ahead                                            | *deprecated* | [`rr_arb_tree`](src/rr_arb_tree.sv) |
+| [`fall_through_register`](src/fall_through_register.sv)        | Fall-through register with ready/valid interface                                                          | active       |                                     |
+| [`spill_register_flushable`](src/spill_register_flushable.sv)  | Register with ready/valid interface to cut all combinational interface paths and additional flush signal. | active       |                                     |
+| [`spill_register`](src/spill_register.sv)                      | Register with ready/valid interface to cut all combinational interface paths                              | active       |                                     |
+| [`stream_arbiter`](src/stream_arbiter.sv)                      | Round-robin arbiter for ready/valid stream interface                                                      | active       |                                     |
+| [`stream_arbiter_flushable`](src/stream_arbiter_flushable.sv)  | Round-robin arbiter for ready/valid stream interface and flush functionality                              | active       |                                     |
+| [`stream_demux`](src/stream_demux.sv)                          | Ready/valid interface demultiplexer                                                                       | active       |                                     |
+| [`lossy_valid_to_stream`](src/lossy_valid_to_stream.sv)        | Convert Valid-only to ready/valid by updating in-flight transaction                                       | active       |                                     |
+| [`stream_join`](src/stream_join.sv)                            | Ready/valid handshake join multiple to one common                                                         | active       |                                     |
+| [`stream_join_dynamic`](src/stream_join_dynamic.sv)            | Ready/valid handshake join multiple to one common, dynamically configurable subset selection              | active       |                                     |
+| [`stream_mux`](src/stream_mux.sv)                              | Ready/valid interface multiplexer                                                                         | active       |                                     |
+| [`stream_register`](src/stream_register.sv)                    | Register with ready/valid interface                                                                       | active       |                                     |
+| [`stream_fork`](src/stream_fork.sv)                            | Ready/valid fork                                                                                          | active       |                                     |
+| [`stream_fork_dynamic`](src/stream_fork_dynamic.sv)            | Ready/valid fork, with selection mask for partial forking                                                 | active       |                                     |
+| [`stream_filter`](src/stream_filter.sv)                        | Ready/valid filter                                                                                        | active       |                                     |
+| [`stream_delay`](src/stream_delay.sv)                          | Randomize or delay ready/valid interface                                                                  | active       |                                     |
+| [`stream_to_mem`](src/stream_to_mem.sv)                        | Use memories without flow control for output data in streams.                                             | active       |                                     |
+| [`stream_xbar`](src/stream_xbar.sv)                            | Fully connected crossbar with ready/valid interface.                                                      | active       |                                     |
+| [`stream_omega_net`](src/stream_omega_net.sv)                  | One-way stream omega-net with ready/valid interface. Isomorphic to a butterfly.                           | active       |                                     |
+| [`stream_throttle`](src/stream_throttle.sv)                    | Restrict the number of outstanding transfers in a stream.                                                 | active       |                                     |
+| [`sub_per_hash`](src/sub_per_hash.sv)                          | Substitution-permutation hash function                                                                    | active       |                                     |
+| [`popcount`](src/popcount.sv)                                  | Combinatorial popcount (hamming weight)                                                                   | active       |                                     |
+| [`mem_to_banks_detailed`](src/mem_to_banks_detailed.sv)        | Split memory access over multiple parallel banks with detailed response signals                           | active       |                                     |
+| [`mem_to_banks`](src/mem_to_banks.sv)                          | Split memory access over multiple parallel banks                                                          | active       |                                     |
+| [`heaviside`](src/heaviside.sv)                                | Generates a mask obtained by applying the Heaviside step function                                         | active       |                                     |
+| [`boxcar`](src/boxcar.sv)                                      | Generates a mask obtained by applying a boxcar function                                                   | active       |                                     |
+
+### Data Structures
+
+| Name                                                             | Description                                                                 | Status       | Superseded By                                                                                   |
+| ---------------------------------------------------------------- | --------------------------------------------------------------------------- | ------------ | ----------------------------------------------------------------------------------------------- |
+| [`cb_filter`](src/cb_filter.sv)                                  | Counting-Bloom-Filter with combinational lookup                             | active       |                                                                                                 |
+| [`fifo`](src/deprecated/fifo_v1.sv)                              | FIFO register with upper threshold                                          | *deprecated* | [`fifo_v3`](src/fifo_v3.sv)                                                                     |
+| [`fifo_v2`](src/deprecated/fifo_v2.sv)                           | FIFO register with upper and lower threshold                                | *deprecated* | [`fifo_v3`](src/fifo_v3.sv)                                                                     |
+| [`fifo_v3`](src/fifo_v3.sv)                                      | FIFO register with generic fill counts                                      | active       |                                                                                                 |
+| [`passthrough_stream_fifo`](src/passthrough_stream_fifo.sv)      | FIFO register with ready/valid interface and same-cycle push/pop when full  | active       |                                                                                                 |
+| [`ring_buffer`](src/ring_buffer.sv)                              | Ring buffer with sequential write and random-access read interfaces         | active       |                                                                                                 |
+| [`stream_fifo`](src/stream_fifo.sv)                              | FIFO register with ready/valid interface                                    | active       |                                                                                                 |
+| [`stream_fifo_optimal_wrap`](src/stream_fifo_optimal_wrap.sv)    | Wrapper that optimally selects either a spill register or a FIFO            | active       |                                                                                                 |
+| [`generic_fifo`](src/deprecated/generic_fifo.sv)                 | FIFO register without thresholds                                            | *deprecated* | [`fifo_v3`](src/fifo_v3.sv)                                                                     |
+| [`generic_fifo_adv`](src/deprecated/generic_fifo_adv.sv)         | FIFO register without thresholds                                            | *deprecated* | [`fifo_v3`](src/fifo_v3.sv)                                                                     |
+| [`sram`](src/deprecated/sram.sv)                                 | SRAM behavioral model                                                       | *deprecated* | [`tc_sram`](https://github.com/pulp-platform/tech_cells_generic/blob/master/src/rtl/tc_sram.sv) |
+| [`plru_tree`](src/plru_tree.sv)                                  | Pseudo least recently used tree                                             | active       |                                                                                                 |
+| [`unread`](src/unread.sv)                                        | Empty module to sink unconnected outputs into                               | active       |                                                                                                 |
+| [`read`](src/read.sv)                                            | Dummy module that prevents a signal from being removed during synthesis     | active       |                                                                                                 |
+
+## Header Contents
+
+This repository currently contains the following header files.
+
+### RTL Register Macros
+
+The header file [`registers.svh`](include/common_cells/registers.svh) contains macros that expand to descriptions of registers.
+To avoid misuse of `always_ff` blocks, only the following macros shall be used to describe sequential behavior.
+The use of linter rules that flag explicit uses of `always_ff` in source code is encouraged.
+
+|    Macro     |                             Arguments                             |                                Description                                |
+| ------------ | ----------------------------------------------------------------- | ------------------------------------------------------------------------- |
+| <code>`FF</code>     | `q_sig`, `d_sig`, `rst_val`, (`clk_sig`, `arstn_sig`)             | Flip-flop with asynchronous active-low reset                              |
+| <code>`FFAR</code>   | `q_sig`, `d_sig`, `rst_val`, `clk_sig`, `arst_sig`                | Flip-flop with asynchronous active-high reset                             |
+| <code>`FFARN</code>  | `q_sig`, `d_sig`, `rst_val`, `clk_sig`, `arstn_sig`               | *deprecated* Flip-flop with asynchronous active-low reset                 |
+| <code>`FFSR</code>   | `q_sig`, `d_sig`, `rst_val`, `clk_sig`, `rst_sig`                 | Flip-flop with synchronous active-high reset                              |
+| <code>`FFSRN</code>  | `q_sig`, `d_sig`, `rst_val`, `clk_sig`, `rstn_sig`                | Flip-flop with synchronous active-low reset                               |
+| <code>`FFNR</code>   | `q_sig`, `d_sig`, `clk_sig`                                       | Flip-flop without reset                                                   |
+|              |                                                                   |                                                                           |
+| <code>`FFL</code>    | `q_sig`, `d_sig`, `load_ena`, `rst_val`, (`clk_sig`, `arstn_sig`) | Flip-flop with load-enable and asynchronous active-low reset              |
+| <code>`FFLAR</code>  | `q_sig`, `d_sig`, `load_ena`, `rst_val`, `clk_sig`, `arst_sig`    | Flip-flop with load-enable and asynchronous active-high reset             |
+| <code>`FFLARN</code> | `q_sig`, `d_sig`, `load_ena`, `rst_val`, `clk_sig`, `arstn_sig`   | *deprecated* Flip-flop with load-enable and asynchronous active-low reset |
+| <code>`FFLSR</code>  | `q_sig`, `d_sig`, `load_ena`, `rst_val`, `clk_sig`, `rst_sig`     | Flip-flop with load-enable and synchronous active-high reset              |
+| <code>`FFLSRN</code> | `q_sig`, `d_sig`, `load_ena`, `rst_val`, `clk_sig`, `rstn_sig`    | Flip-flop with load-enable and synchronous active-low reset               |
+| <code>`FFLNR</code>  | `q_sig`, `d_sig`, `load_ena`, `clk_sig`                           | Flip-flop with load-enable without reset                                  |
+- *The name of the clock and reset signals for implicit variants is `clk_i` and `rst_ni`, respectively.*
+- *Argument suffix `_sig` indicates signal names for present and next state as well as clocks and resets.*
+- *Argument `rst_val` specifies the value literal to be assigned upon reset.*
+- *Argument `load_ena` specifies the boolean expression that forms the load enable of the register.*
+
+### SystemVerilog Assertion Macros
+
+The header file [`assertions.svh`](include/common_cells/assertions.svh) contains macros that expand to assertion blocks.
+These macros should recduce the effort in writing many assertions and make it
+easier to use them. They are similar to but incompatible with the macros used by [lowrisc](https://github.com/lowRISC/opentitan/blob/master/hw/ip/prim/rtl/prim_assert.sv).
+
+#### Simple Assertion and Cover Macros
+| Macro              | Arguments                                        | Description                                                                |
+| ------------------ | ------------------------------------------------ | -------------------------------------------------------------------------- |
+| <code>`ASSERT_I</code>     | `__name`, `__prop`, (`__desc`)                   | Immediate assertion                                                        |
+| <code>`ASSERT_INIT</code>  | `__name`, `__prop`, (`__desc`)                   | Assertion in initial block. Can be used for things like parameter checking |
+| <code>`ASSERT_FINAL</code> | `__name`, `__prop`, (`__desc`)                   | Assertion in final block                                                   |
+| <code>`ASSERT</code>       | `__name`, `__prop`, (`__clk`, `__rst`, `__desc`) | Assert a concurrent property directly                                      |
+| <code>`ASSERT_NEVER</code> | `__name`, `__prop`, (`__clk`, `__rst`, `__desc`) | Assert a concurrent property NEVER happens                                 |
+| <code>`ASSERT_KNOWN</code> | `__name`, `__sig`, (`__clk`, `__rst`, `__desc`)  | Concurrent clocked assertion with custom error message                     |
+| <code>`COVER</code>        | `__name`, `__prop`, (`__clk`, `__rst`)           | Cover a concurrent property                                                |
+- *The name of the clock and reset signals for implicit variants is `clk_i` and `rst_ni`, respectively.*
+- *`__desc` is an optional string argument describing the failure causing the assertion to be violated that is embedded into the error report and defaults to `""`.*
+
+#### Complex Assertion Macros
+| Macro                 | Arguments                                                                           | Description                                                                                                |
+| --------------------- | ----------------------------------------------------------------------------------- | ---------------------------------------------------------------------------------------------------------- |
+| <code>`ASSERT_PULSE</code>    | `__name`, `__sig`, (`__clk`, `__rst`, `__desc`)                                     | Assert that signal is an active-high pulse with pulse length of 1 clock cycle                              |
+| <code>`ASSERT_IF</code>       | `__name`, `__prop`, `__enable`, (`__clk`, `__rst`, `__desc`)                        | Assert that a property is true only when an enable signal is set                                           |
+| <code>`ASSERT_KNOWN_IF</code> | `__name`, `__sig`, `__enable`, (`__clk`, `__rst`, `__desc`)                         | Assert that signal has a known value (each bit is either '0' or '1') after reset if enable is set          |
+| <code>`ASSERT_STABLE</code>   | `__name`, `__valid`, `__ready`, `__data`, `__enable`, (`__clk`, `__rst`, `__desc`)  | Assert that the data on a ready-valid interface is kept stable after valid is asserted, until ready is too |
+- *The name of the clock and reset signals for implicit variants is `clk_i` and `rst_ni`, respectively.*
+- *`__desc` is an optional string argument describing the failure causing the assertion to be violated that is embedded into the error report and defaults to `""`.*
+
+#### Assumption Macros
+
+| Macro          | Arguments                                        | Description                  |
+| -------------- | ------------------------------------------------ | ---------------------------- |
+| <code>`ASSUME</code>   | `__name`, `__prop`, (`__clk`, `__rst`, `__desc`) | Assume a concurrent property |
+| <code>`ASSUME_I</code> | `__name`, `__prop`, (`__desc`)                   | Assume an immediate property |
+- *The name of the clock and reset signals for implicit variants is `clk_i` and `rst_ni`, respectively.*
+- *`__desc` is an optional string argument describing the failure causing the assertion to be violated that is embedded into the error report and defaults to `""`.*
+
+#### Formal Verification Macros
+
+| Macro              | Arguments                                        | Description                                                  |
+| ------------------ | ------------------------------------------------ | ------------------------------------------------------------ |
+| <code>`ASSUME_FPV</code>   | `__name`, `__prop`, (`__clk`, `__rst`, `__desc`) | Assume a concurrent property during formal verification only |
+| <code>`ASSUME_I_FPV</code> | `__name`, `__prop`, (`__desc`)                   | Assume a concurrent property during formal verification only |
+| <code>`COVER_FPV</code>    | `__name`, `__prop`, (`__clk`, `__rst`)           | Cover a concurrent property during formal verification       |
+- *The name of the clock and reset signals for implicit variants is `clk_i` and `rst_ni`, respectively.*
+- *`__desc` is an optional string argument describing the failure causing the assertion to be violated that is embedded into the error report and defaults to `""`.*

snapshots/pulp-platform_riscv-dbg_pr53/debug_rom/.gitignore

@@ -0,0 +1,3 @@
+*.bin
+*.elf
+debug_rom.img

snapshots/pulp-platform_riscv-dbg_pr53/debug_rom/Makefile

@@ -0,0 +1,28 @@
+# See LICENSE.SiFive for license details
+
+debug_rom = debug_rom.sv
+
+GCC?=riscv64-unknown-elf-gcc
+OBJCOPY?=riscv64-unknown-elf-objcopy
+OBJDUMP?=riscv64-unknown-elf-objdump
+PYTHON?=python
+
+all: $(debug_rom)
+
+%.sv: %.img
+	$(PYTHON) gen_rom.py $<
+
+%.img: %.bin
+	dd if=$< of=$@ bs=256 count=1
+
+%.bin: %.elf
+	$(OBJCOPY) -O binary $< $@
+
+%.elf: %.S link.ld
+	$(GCC) -I$(RISCV)/include -Tlink.ld $< -nostdlib -fPIC -static -Wl,--no-gc-sections -o $@
+
+%.dump: %.elf
+	$(OBJDUMP) -d $< --disassemble-all --disassemble-zeroes --section=.text --section=.text.startup --section=.text.init --section=.data  > $@
+
+clean:
+	rm -f *.img *.dump *.bin *.sv

snapshots/pulp-platform_riscv-dbg_pr53/debug_rom/debug_rom.S

@@ -0,0 +1,100 @@
+// See LICENSE.SiFive for license details.
+
+#include "encoding.h"
+
+// These are implementation-specific addresses in the Debug Module
+#define HALTED    0x100
+#define GOING     0x104
+#define RESUMING  0x108
+#define EXCEPTION 0x10C
+
+// Region of memory where each hart has 1
+// byte to read.
+#define FLAGS 0x400
+#define FLAG_GO     0
+#define FLAG_RESUME 1
+
+        .option norvc
+        .global entry
+        .global exception
+
+        // Entry location on ebreak, Halt, or Breakpoint
+        // It is the same for all harts. They branch when
+        // their GO or RESUME bit is set.
+
+entry:
+       jal zero, _entry
+resume:
+       jal zero, _resume
+exception:
+       jal zero, _exception
+
+
+
+_entry:
+        // This fence is required because the execution may have written something
+        // into the Abstract Data or Program Buffer registers.
+        fence
+        csrw CSR_DSCRATCH0, s0       // Save s0 to allow signaling MHARTID
+        csrw CSR_DSCRATCH1, a0       // Save a0 to allow loading arbitrary DM base
+        auipc a0, 0                  // Get PC
+        srli a0, a0, 12              // And throw away lower 12 bits to get the DM base
+        slli a0, a0, 12
+
+        // We continue to let the hart know that we are halted in order that
+        // a DM which was reset is still made aware that a hart is halted.
+        // We keep checking both whether there is something the debugger wants
+        // us to do, or whether we should resume.
+entry_loop:
+        csrr s0, CSR_MHARTID
+        sw   s0, HALTED(a0)
+        add  s0, s0, a0
+        lbu  s0, FLAGS(s0) // 1 byte flag per hart. Only one hart advances here.
+        andi s0, s0, (1 << FLAG_GO)
+        bnez s0, going
+        csrr s0, CSR_MHARTID
+        add  s0, s0, a0
+        lbu  s0, FLAGS(s0) // multiple harts can resume  here
+        andi s0, s0, (1 << FLAG_RESUME)
+        bnez s0, resume
+        jal  zero, entry_loop
+
+_exception:
+        // We can only get here due to an exception while in debug mode. Hence,
+        // we do not need to save a0 to a scratch register as it has already
+        // been saved on debug entry.
+        auipc a0, 0                  // Get POC
+        srli a0, a0, 12              // And throw away lower 12 bits to get the DM base
+        slli a0, a0, 12
+        sw   zero, EXCEPTION(a0)     // Let debug module know you got an exception.
+        // It is safe to always restore the scratch registers here as they must
+        // have been saved on debug entry. Restoring them here avoids issues
+        // with registers being overwritten by exceptions occuring during
+        // program buffer execution.
+        csrr s0, CSR_DSCRATCH0       // Restore s0 here
+        csrr a0, CSR_DSCRATCH1       // Restore a0 here
+        ebreak
+
+going:
+        sw zero, GOING(a0)          // When debug module sees this write, the GO flag is reset.
+        csrr s0, CSR_DSCRATCH0      // Restore s0 here
+        csrr a0, CSR_DSCRATCH1      // Restore a0 here
+        jal zero, whereto
+_resume:
+        csrr s0, CSR_MHARTID
+        sw   s0, RESUMING(a0)   // When Debug Module sees this write, the RESUME flag is reset.
+        csrr s0, CSR_DSCRATCH0  // Restore s0 here
+        csrr a0, CSR_DSCRATCH1  // Restore a0 here
+        dret
+
+        // END OF ACTUAL "ROM" CONTENTS. BELOW IS JUST FOR LINKER SCRIPT.
+
+.section .whereto
+whereto:
+        nop
+        // Variable "ROM" This is : jal x0 abstract, jal x0 program_buffer,
+        //                or jal x0 resume, as desired.
+        //                Debug Module state machine tracks what is 'desired'.
+        //                We don't need/want to use jalr here because all of the
+        //                Variable ROM contents are set by
+        //                Debug Module before setting the OK_GO byte.

snapshots/pulp-platform_riscv-dbg_pr53/debug_rom/debug_rom.h

@@ -0,0 +1,44 @@
+// Auto-generated code
+
+const int reset_vec_size = 38;
+
+uint32_t reset_vec[reset_vec_size] = {
+    0x00c0006f,
+    0x07c0006f,
+    0x04c0006f,
+    0x0ff0000f,
+    0x7b241073,
+    0x7b351073,
+    0x00000517,
+    0x00c55513,
+    0x00c51513,
+    0xf1402473,
+    0x10852023,
+    0x00a40433,
+    0x40044403,
+    0x00147413,
+    0x02041c63,
+    0xf1402473,
+    0x00a40433,
+    0x40044403,
+    0x00247413,
+    0xfa041ce3,
+    0xfd5ff06f,
+    0x00000517,
+    0x00c55513,
+    0x00c51513,
+    0x10052623,
+    0x7b202473,
+    0x7b302573,
+    0x00100073,
+    0x10052223,
+    0x7b202473,
+    0x7b302573,
+    0xa85ff06f,
+    0xf1402473,
+    0x10852423,
+    0x7b202473,
+    0x7b302573,
+    0x7b200073,
+    0x00000000
+};

snapshots/pulp-platform_riscv-dbg_pr53/debug_rom/debug_rom.sv

@@ -0,0 +1,65 @@
+/* Copyright 2018 ETH Zurich and University of Bologna.
+ * Copyright and related rights are licensed under the Solderpad Hardware
+ * License, Version 0.51 (the "License"); you may not use this file except in
+ * compliance with the License.  You may obtain a copy of the License at
+ * http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
+ * or agreed to in writing, software, hardware and materials distributed under
+ * this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
+ * CONDITIONS OF ANY KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations under the License.
+ *
+ * File: $filename.v
+ *
+ * Description: Auto-generated bootrom
+ */
+
+// Auto-generated code
+module debug_rom (
+  input  logic         clk_i,
+  input  logic         req_i,
+  input  logic [63:0]  addr_i,
+  output logic [63:0]  rdata_o
+);
+
+  localparam int unsigned RomSize = 19;
+
+  const logic [RomSize-1:0][63:0] mem = {
+    64'h00000000_7b200073,
+    64'h7b302573_7b202473,
+    64'h10852423_f1402473,
+    64'ha85ff06f_7b302573,
+    64'h7b202473_10052223,
+    64'h00100073_7b302573,
+    64'h7b202473_10052623,
+    64'h00c51513_00c55513,
+    64'h00000517_fd5ff06f,
+    64'hfa041ce3_00247413,
+    64'h40044403_00a40433,
+    64'hf1402473_02041c63,
+    64'h00147413_40044403,
+    64'h00a40433_10852023,
+    64'hf1402473_00c51513,
+    64'h00c55513_00000517,
+    64'h7b351073_7b241073,
+    64'h0ff0000f_04c0006f,
+    64'h07c0006f_00c0006f
+  };
+
+  logic [$clog2(RomSize)-1:0] addr_q;
+
+  always_ff @(posedge clk_i) begin
+    if (req_i) begin
+      addr_q <= addr_i[$clog2(RomSize)-1+3:3];
+    end
+  end
+
+  // this prevents spurious Xes from propagating into
+  // the speculative fetch stage of the core
+  always_comb begin : p_outmux
+    rdata_o = '0;
+    if (addr_q < $clog2(RomSize)'(RomSize)) begin
+        rdata_o = mem[addr_q];
+    end
+  end
+
+endmodule

snapshots/pulp-platform_riscv-dbg_pr53/debug_rom/gen_rom.py

@@ -0,0 +1,134 @@
+#!/usr/bin/env python3
+
+from string import Template
+import argparse
+import os.path
+import sys
+import binascii
+
+
+parser = argparse.ArgumentParser(description='Convert binary file to verilog rom')
+parser.add_argument('filename', metavar='filename', nargs=1,
+                   help='filename of input binary')
+
+args = parser.parse_args()
+file = args.filename[0];
+
+# check that file exists
+if not os.path.isfile(file):
+    print("File {} does not exist.".format(filename))
+    sys.exit(1)
+
+filename = os.path.splitext(file)[0]
+
+license = """\
+/* Copyright 2018 ETH Zurich and University of Bologna.
+ * Copyright and related rights are licensed under the Solderpad Hardware
+ * License, Version 0.51 (the "License"); you may not use this file except in
+ * compliance with the License.  You may obtain a copy of the License at
+ * http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
+ * or agreed to in writing, software, hardware and materials distributed under
+ * this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
+ * CONDITIONS OF ANY KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations under the License.
+ *
+ * File: $filename.v
+ *
+ * Description: Auto-generated bootrom
+ */
+
+// Auto-generated code
+"""
+
+module = """\
+module $filename (
+  input  logic         clk_i,
+  input  logic         req_i,
+  input  logic [63:0]  addr_i,
+  output logic [63:0]  rdata_o
+);
+
+  localparam int unsigned RomSize = $size;
+
+  const logic [RomSize-1:0][63:0] mem = {
+$content
+  };
+
+  logic [$$clog2(RomSize)-1:0] addr_q;
+
+  always_ff @(posedge clk_i) begin
+    if (req_i) begin
+      addr_q <= addr_i[$$clog2(RomSize)-1+3:3];
+    end
+  end
+
+  // this prevents spurious Xes from propagating into
+  // the speculative fetch stage of the core
+  always_comb begin : p_outmux
+    rdata_o = '0;
+    if (addr_q < $$clog2(RomSize)'(RomSize)) begin
+        rdata_o = mem[addr_q];
+    end
+  end
+
+endmodule
+"""
+
+c_var = """\
+// Auto-generated code
+
+const int reset_vec_size = $size;
+
+uint32_t reset_vec[reset_vec_size] = {
+$content
+};
+"""
+
+def read_bin():
+
+    with open(filename + ".img", 'rb') as f:
+        rom = binascii.hexlify(f.read())
+        rom = map(''.join, zip(rom[::2], rom[1::2]))
+
+
+    # align to 64 bit
+    align = (int((len(rom) + 7) / 8 )) * 8;
+
+    for i in range(len(rom), align):
+        rom.append("00")
+
+    return rom
+
+rom = read_bin()
+
+""" Generate C header file for simulator
+"""
+with open(filename + ".h", "w") as f:
+    rom_str = ""
+    # process in junks of 32 bit (4 byte)
+    for i in range(0, int(len(rom)/4)):
+        rom_str += "    0x" + "".join(rom[i*4:i*4+4][::-1]) + ",\n"
+
+    # remove the trailing comma
+    rom_str = rom_str[:-2]
+
+    s = Template(c_var)
+    f.write(s.substitute(filename=filename, size=int(len(rom)/4), content=rom_str))
+
+    f.close()
+
+""" Generate SystemVerilog bootcode for FPGA and ASIC
+"""
+with open(filename + ".sv", "w") as f:
+    rom_str = ""
+    # process in junks of 64 bit (8 byte)
+    for i in reversed(range(int(len(rom)/8))):
+        rom_str += "    64'h" + "".join(rom[i*8+4:i*8+8][::-1]) + "_" + "".join(rom[i*8:i*8+4][::-1]) + ",\n"
+
+    # remove the trailing comma
+    rom_str = rom_str[:-2]
+
+    f.write(license)
+    s = Template(module)
+    f.write(s.substitute(filename=filename, size=int(len(rom)/8), content=rom_str))
+

snapshots/pulp-platform_riscv-dbg_pr53/debug_rom/link.ld

@@ -0,0 +1,16 @@
+/* See LICENSE.SiFive for license details. */
+OUTPUT_ARCH( "riscv" )
+ENTRY( entry )
+SECTIONS
+{
+    .whereto 0x300 :
+    {
+        *(.whereto)
+    }   
+    . = 0x800;
+    .text :
+    {
+        *(.text)
+    }
+    _end = .;
+}

snapshots/pulp-platform_riscv-dbg_pr53/src/dm_csrs.sv

@@ -0,0 +1,647 @@
+/* Copyright 2018 ETH Zurich and University of Bologna.
+ * Copyright and related rights are licensed under the Solderpad Hardware
+ * License, Version 0.51 (the “License”); you may not use this file except in
+ * compliance with the License.  You may obtain a copy of the License at
+ * http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
+ * or agreed to in writing, software, hardware and materials distributed under
+ * this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR
+ * CONDITIONS OF ANY KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations under the License.
+ *
+ * File:  dm_csrs.sv
+ * Author: Florian Zaruba <zarubaf@iis.ee.ethz.ch>
+ * Date:   30.6.2018
+ *
+ * Description: Debug CSRs. Communication over Debug Transport Module (DTM)
+ */
+
+module dm_csrs #(
+  parameter int unsigned        NrHarts          = 1,
+  parameter int unsigned        BusWidth         = 32,
+  parameter logic [NrHarts-1:0] SelectableHarts  = {NrHarts{1'b1}}
+) (
+  input  logic                              clk_i,           // Clock
+  input  logic                              rst_ni,          // Asynchronous reset active low
+  input  logic                              testmode_i,
+  input  logic                              dmi_rst_ni,      // Debug Module Intf reset active-low
+  input  logic                              dmi_req_valid_i,
+  output logic                              dmi_req_ready_o,
+  input  dm::dmi_req_t                      dmi_req_i,
+  // every request needs a response one cycle later
+  output logic                              dmi_resp_valid_o,
+  input  logic                              dmi_resp_ready_i,
+  output dm::dmi_resp_t                     dmi_resp_o,
+  // global ctrl
+  output logic                              ndmreset_o,      // non-debug module reset active-high
+  output logic                              dmactive_o,      // 1 -> debug-module is active,
+                                                             // 0 -> synchronous re-set
+  // hart status
+  input  dm::hartinfo_t [NrHarts-1:0]       hartinfo_i,      // static hartinfo
+  input  logic [NrHarts-1:0]                halted_i,        // hart is halted
+  input  logic [NrHarts-1:0]                unavailable_i,   // e.g.: powered down
+  input  logic [NrHarts-1:0]                resumeack_i,     // hart acknowledged resume request
+  // hart control
+  output logic [19:0]                       hartsel_o,       // hartselect to ctrl module
+  output logic [NrHarts-1:0]                haltreq_o,       // request to halt a hart
+  output logic [NrHarts-1:0]                resumereq_o,     // request hart to resume
+  output logic                              clear_resumeack_o,
+
+  output logic                              cmd_valid_o,       // debugger writing to cmd field
+  output dm::command_t                      cmd_o,             // abstract command
+  input  logic                              cmderror_valid_i,  // an error occurred
+  input  dm::cmderr_e                       cmderror_i,        // this error occurred
+  input  logic                              cmdbusy_i,         // cmd is currently busy executing
+
+  output logic [dm::ProgBufSize-1:0][31:0]  progbuf_o, // to system bus
+  output logic [dm::DataCount-1:0][31:0]    data_o,
+
+  input  logic [dm::DataCount-1:0][31:0]    data_i,
+  input  logic                              data_valid_i,
+  // system bus access module (SBA)
+  output logic [BusWidth-1:0]               sbaddress_o,
+  input  logic [BusWidth-1:0]               sbaddress_i,
+  output logic                              sbaddress_write_valid_o,
+  // control signals in
+  output logic                              sbreadonaddr_o,
+  output logic                              sbautoincrement_o,
+  output logic [2:0]                        sbaccess_o,
+  // data out
+  output logic                              sbreadondata_o,
+  output logic [BusWidth-1:0]               sbdata_o,
+  output logic                              sbdata_read_valid_o,
+  output logic                              sbdata_write_valid_o,
+  // read data in
+  input  logic [BusWidth-1:0]               sbdata_i,
+  input  logic                              sbdata_valid_i,
+  // control signals
+  input  logic                              sbbusy_i,
+  input  logic                              sberror_valid_i, // bus error occurred
+  input  logic [2:0]                        sberror_i // bus error occurred
+);
+  // the amount of bits we need to represent all harts
+  localparam int unsigned HartSelLen = (NrHarts == 1) ? 1 : $clog2(NrHarts);
+  localparam int unsigned NrHartsAligned = 2**HartSelLen;
+
+  dm::dtm_op_e dtm_op;
+  assign dtm_op = dm::dtm_op_e'(dmi_req_i.op);
+
+  logic        resp_queue_full;
+  logic        resp_queue_empty;
+  logic        resp_queue_push;
+  logic        resp_queue_pop;
+  logic [31:0] resp_queue_data;
+
+  localparam dm::dm_csr_e DataEnd = dm::dm_csr_e'(dm::Data0 + {4'b0, dm::DataCount} - 8'h01);
+  localparam dm::dm_csr_e ProgBufEnd = dm::dm_csr_e'(dm::ProgBuf0 + {4'b0, dm::ProgBufSize} - 8'h01);
+
+  logic [31:0] haltsum0, haltsum1, haltsum2, haltsum3;
+  logic [((NrHarts-1)/2**5 + 1) * 32 - 1 : 0] halted;
+  logic [(NrHarts-1)/2**5:0][31:0] halted_reshaped0;
+  logic [NrHarts/2**10:0][31:0] halted_reshaped1;
+  logic [NrHarts/2**15:0][31:0] halted_reshaped2;
+  logic [(NrHarts/2**10+1)*32-1:0] halted_flat1;
+  logic [(NrHarts/2**15+1)*32-1:0] halted_flat2;
+  logic [32-1:0] halted_flat3;
+
+  // haltsum0
+  logic [14:0] hartsel_idx0;
+  always_comb begin : p_haltsum0
+    halted              = '0;
+    haltsum0            = '0;
+    hartsel_idx0        = hartsel_o[19:5];
+    halted[NrHarts-1:0] = halted_i;
+    halted_reshaped0    = halted;
+    if (hartsel_idx0 < 15'((NrHarts-1)/2**5+1)) begin
+      haltsum0 = halted_reshaped0[hartsel_idx0];
+    end
+  end
+
+  // haltsum1
+  logic [9:0] hartsel_idx1;
+  always_comb begin : p_reduction1
+    halted_flat1 = '0;
+    haltsum1     = '0;
+    hartsel_idx1 = hartsel_o[19:10];
+
+    for (int unsigned k = 0; k < NrHarts/2**5+1; k++) begin
+      halted_flat1[k] = |halted_reshaped0[k];
+    end
+    halted_reshaped1 = halted_flat1;
+
+    if (hartsel_idx1 < 10'((NrHarts/2**10+1))) begin
+      haltsum1 = halted_reshaped1[hartsel_idx1];
+    end
+  end
+
+  // haltsum2
+  logic [4:0] hartsel_idx2;
+  always_comb begin : p_reduction2
+    halted_flat2 = '0;
+    haltsum2     = '0;
+    hartsel_idx2 = hartsel_o[19:15];
+
+    for (int unsigned k = 0; k < NrHarts/2**10+1; k++) begin
+      halted_flat2[k] = |halted_reshaped1[k];
+    end
+    halted_reshaped2 = halted_flat2;
+
+    if (hartsel_idx2 < 5'((NrHarts/2**15+1))) begin
+      haltsum2         = halted_reshaped2[hartsel_idx2];
+    end
+  end
+
+  // haltsum3
+  always_comb begin : p_reduction3
+    halted_flat3 = '0;
+    for (int unsigned k = 0; k < NrHarts/2**15+1; k++) begin
+      halted_flat3[k] = |halted_reshaped2[k];
+    end
+    haltsum3 = halted_flat3;
+  end
+
+
+  dm::dmstatus_t      dmstatus;
+  dm::dmcontrol_t     dmcontrol_d, dmcontrol_q;
+  dm::abstractcs_t    abstractcs;
+  dm::cmderr_e        cmderr_d, cmderr_q;
+  dm::command_t       command_d, command_q;
+  logic               cmd_valid_d, cmd_valid_q;
+  dm::abstractauto_t  abstractauto_d, abstractauto_q;
+  dm::sbcs_t          sbcs_d, sbcs_q;
+  logic [63:0]        sbaddr_d, sbaddr_q;
+  logic [63:0]        sbdata_d, sbdata_q;
+
+  logic [NrHarts-1:0] havereset_d, havereset_q;
+  // program buffer
+  logic [dm::ProgBufSize-1:0][31:0] progbuf_d, progbuf_q;
+  logic [dm::DataCount-1:0][31:0] data_d, data_q;
+
+  logic [HartSelLen-1:0] selected_hart;
+
+  // a successful response returns zero
+  assign dmi_resp_o.resp = dm::DTM_SUCCESS;
+  assign dmi_resp_valid_o     = ~resp_queue_empty;
+  assign dmi_req_ready_o      = ~resp_queue_full;
+  assign resp_queue_push      = dmi_req_valid_i & dmi_req_ready_o;
+  // SBA
+  assign sbautoincrement_o = sbcs_q.sbautoincrement;
+  assign sbreadonaddr_o    = sbcs_q.sbreadonaddr;
+  assign sbreadondata_o    = sbcs_q.sbreadondata;
+  assign sbaccess_o        = sbcs_q.sbaccess;
+  assign sbdata_o          = sbdata_q[BusWidth-1:0];
+  assign sbaddress_o       = sbaddr_q[BusWidth-1:0];
+
+  assign hartsel_o         = {dmcontrol_q.hartselhi, dmcontrol_q.hartsello};
+
+  // needed to avoid lint warnings
+  logic [NrHartsAligned-1:0] havereset_d_aligned, havereset_q_aligned,
+                             resumeack_aligned, unavailable_aligned,
+                             halted_aligned;
+  assign resumeack_aligned   = NrHartsAligned'(resumeack_i);
+  assign unavailable_aligned = NrHartsAligned'(unavailable_i);
+  assign halted_aligned      = NrHartsAligned'(halted_i);
+
+  assign havereset_d         = NrHarts'(havereset_d_aligned);
+  assign havereset_q_aligned = NrHartsAligned'(havereset_q);
+
+  dm::hartinfo_t [NrHartsAligned-1:0] hartinfo_aligned;
+  always_comb begin : p_hartinfo_align
+    hartinfo_aligned = '0;
+    hartinfo_aligned[NrHarts-1:0] = hartinfo_i;
+  end
+
+  // helper variables
+  dm::sbcs_t sbcs;
+  dm::dmcontrol_t dmcontrol;
+  dm::abstractcs_t a_abstractcs;
+  logic [4:0] autoexecdata_idx;
+  always_comb begin : csr_read_write
+    // --------------------
+    // Static Values (R/O)
+    // --------------------
+    // dmstatus
+    dmstatus    = '0;
+    dmstatus.version = dm::DbgVersion013;
+    // no authentication implemented
+    dmstatus.authenticated = 1'b1;
+    // we do not support halt-on-reset sequence
+    dmstatus.hasresethaltreq = 1'b0;
+    // TODO(zarubaf) things need to change here if we implement the array mask
+    dmstatus.allhavereset = havereset_q_aligned[selected_hart];
+    dmstatus.anyhavereset = havereset_q_aligned[selected_hart];
+
+    dmstatus.allresumeack = resumeack_aligned[selected_hart];
+    dmstatus.anyresumeack = resumeack_aligned[selected_hart];
+
+    dmstatus.allunavail   = unavailable_aligned[selected_hart];
+    dmstatus.anyunavail   = unavailable_aligned[selected_hart];
+
+    // as soon as we are out of the legal Hart region tell the debugger
+    // that there are only non-existent harts
+    dmstatus.allnonexistent = logic'(32'(hartsel_o) > (NrHarts - 1));
+    dmstatus.anynonexistent = logic'(32'(hartsel_o) > (NrHarts - 1));
+
+    // We are not allowed to be in multiple states at once. This is a to
+    // make the running/halted and unavailable states exclusive.
+    dmstatus.allhalted    = halted_aligned[selected_hart] & ~unavailable_aligned[selected_hart];
+    dmstatus.anyhalted    = halted_aligned[selected_hart] & ~unavailable_aligned[selected_hart];
+
+    dmstatus.allrunning   = ~halted_aligned[selected_hart] & ~unavailable_aligned[selected_hart];
+    dmstatus.anyrunning   = ~halted_aligned[selected_hart] & ~unavailable_aligned[selected_hart];
+
+    // abstractcs
+    abstractcs = '0;
+    abstractcs.datacount = dm::DataCount;
+    abstractcs.progbufsize = dm::ProgBufSize;
+    abstractcs.busy = cmdbusy_i;
+    abstractcs.cmderr = cmderr_q;
+
+    // abstractautoexec
+    abstractauto_d = abstractauto_q;
+    abstractauto_d.zero0 = '0;
+
+    // default assignments
+    havereset_d_aligned = NrHartsAligned'(havereset_q);
+    dmcontrol_d         = dmcontrol_q;
+    cmderr_d            = cmderr_q;
+    command_d           = command_q;
+    progbuf_d           = progbuf_q;
+    data_d              = data_q;
+    sbcs_d              = sbcs_q;
+    sbaddr_d            = 64'(sbaddress_i);
+    sbdata_d            = sbdata_q;
+
+    resp_queue_data         = 32'b0;
+    cmd_valid_d             = 1'b0;
+    sbaddress_write_valid_o = 1'b0;
+    sbdata_read_valid_o     = 1'b0;
+    sbdata_write_valid_o    = 1'b0;
+    clear_resumeack_o       = 1'b0;
+
+    // helper variables
+    sbcs         = '0;
+    dmcontrol    = '0;
+    a_abstractcs = '0;
+
+    autoexecdata_idx    = dmi_req_i.addr[4:0] - 5'(dm::Data0);
+
+    // localparam int unsigned DataCountAlign = $clog2(dm::DataCount);
+    // reads
+    if (dmi_req_ready_o && dmi_req_valid_i && dtm_op == dm::DTM_READ) begin
+      unique case ({1'b0, dmi_req_i.addr}) inside
+        [(dm::Data0):DataEnd]: begin
+          // logic [$clog2(dm::DataCount)-1:0] resp_queue_idx;
+          // resp_queue_idx = dmi_req_i.addr[4:0] - int'(dm::Data0);
+          resp_queue_data = data_q[$clog2(dm::DataCount)'(autoexecdata_idx)];
+          if (!cmdbusy_i) begin
+            // check whether we need to re-execute the command (just give a cmd_valid)
+            if (autoexecdata_idx < $bits(abstractauto_q.autoexecdata)) begin
+              cmd_valid_d = abstractauto_q.autoexecdata[autoexecdata_idx];
+            end
+          end
+        end
+        dm::DMControl:    resp_queue_data = dmcontrol_q;
+        dm::DMStatus:     resp_queue_data = dmstatus;
+        dm::Hartinfo:     resp_queue_data = hartinfo_aligned[selected_hart];
+        dm::AbstractCS:   resp_queue_data = abstractcs;
+        dm::AbstractAuto: resp_queue_data = abstractauto_q;
+        // command is read-only
+        dm::Command:    resp_queue_data = '0;
+        [(dm::ProgBuf0):ProgBufEnd]: begin
+          resp_queue_data = progbuf_q[dmi_req_i.addr[$clog2(dm::ProgBufSize)-1:0]];
+          if (!cmdbusy_i) begin
+            // check whether we need to re-execute the command (just give a cmd_valid)
+            // range of autoexecprogbuf is 31:16
+            cmd_valid_d = abstractauto_q.autoexecprogbuf[{1'b1, dmi_req_i.addr[3:0]}];
+          end
+        end
+        dm::HaltSum0: resp_queue_data = haltsum0;
+        dm::HaltSum1: resp_queue_data = haltsum1;
+        dm::HaltSum2: resp_queue_data = haltsum2;
+        dm::HaltSum3: resp_queue_data = haltsum3;
+        dm::SBCS: begin
+          resp_queue_data = sbcs_q;
+        end
+        dm::SBAddress0: begin
+          // access while the SBA was busy
+          if (sbbusy_i) begin
+            sbcs_d.sbbusyerror = 1'b1;
+          end else begin
+            resp_queue_data = sbaddr_q[31:0];
+          end
+        end
+        dm::SBAddress1: begin
+          // access while the SBA was busy
+          if (sbbusy_i) begin
+            sbcs_d.sbbusyerror = 1'b1;
+          end else begin
+            resp_queue_data = sbaddr_q[63:32];
+          end
+        end
+        dm::SBData0: begin
+          // access while the SBA was busy
+          if (sbbusy_i) begin
+            sbcs_d.sbbusyerror = 1'b1;
+          end else begin
+            sbdata_read_valid_o = (sbcs_q.sberror == '0);
+            resp_queue_data = sbdata_q[31:0];
+          end
+        end
+        dm::SBData1: begin
+          // access while the SBA was busy
+          if (sbbusy_i) begin
+            sbcs_d.sbbusyerror = 1'b1;
+          end else begin
+            resp_queue_data = sbdata_q[63:32];
+          end
+        end
+        default:;
+      endcase
+    end
+
+    // write
+    if (dmi_req_ready_o && dmi_req_valid_i && dtm_op == dm::DTM_WRITE) begin
+      unique case (dm::dm_csr_e'({1'b0, dmi_req_i.addr})) inside
+        [(dm::Data0):DataEnd]: begin
+          // attempts to write them while busy is set does not change their value
+          if (!cmdbusy_i && dm::DataCount > 0) begin
+            data_d[dmi_req_i.addr[$clog2(dm::DataCount)-1:0]] = dmi_req_i.data;
+            // check whether we need to re-execute the command (just give a cmd_valid)
+            if (autoexecdata_idx < $bits(abstractauto_q.autoexecdata)) begin
+              cmd_valid_d = abstractauto_q.autoexecdata[autoexecdata_idx];
+            end
+          end
+        end
+        dm::DMControl: begin
+          dmcontrol = dm::dmcontrol_t'(dmi_req_i.data);
+          // clear the havreset of the selected hart
+          if (dmcontrol.ackhavereset) begin
+            havereset_d_aligned[selected_hart] = 1'b0;
+          end
+          dmcontrol_d = dmi_req_i.data;
+        end
+        dm::DMStatus:; // write are ignored to R/O register
+        dm::Hartinfo:; // hartinfo is R/O
+        // only command error is write-able
+        dm::AbstractCS: begin // W1C
+          // Gets set if an abstract command fails. The bits in this
+          // field remain set until they are cleared by writing 1 to
+          // them. No abstract command is started until the value is
+          // reset to 0.
+          a_abstractcs = dm::abstractcs_t'(dmi_req_i.data);
+          // reads during abstract command execution are not allowed
+          if (!cmdbusy_i) begin
+            cmderr_d = dm::cmderr_e'(~a_abstractcs.cmderr & cmderr_q);
+          end else if (cmderr_q == dm::CmdErrNone) begin
+            cmderr_d = dm::CmdErrBusy;
+          end
+        end
+        dm::Command: begin
+          // writes are ignored if a command is already busy
+          if (!cmdbusy_i) begin
+            cmd_valid_d = 1'b1;
+            command_d = dm::command_t'(dmi_req_i.data);
+          // if there was an attempted to write during a busy execution
+          // and the cmderror field is zero set the busy error
+          end else if (cmderr_q == dm::CmdErrNone) begin
+            cmderr_d = dm::CmdErrBusy;
+          end
+        end
+        dm::AbstractAuto: begin
+          // this field can only be written legally when there is no command executing
+          if (!cmdbusy_i) begin
+            abstractauto_d                 = 32'b0;
+            abstractauto_d.autoexecdata    = 12'(dmi_req_i.data[dm::DataCount-1:0]);
+            abstractauto_d.autoexecprogbuf = 16'(dmi_req_i.data[dm::ProgBufSize-1+16:16]);
+          end else if (cmderr_q == dm::CmdErrNone) begin
+            cmderr_d = dm::CmdErrBusy;
+          end
+        end
+        [(dm::ProgBuf0):ProgBufEnd]: begin
+          // attempts to write them while busy is set does not change their value
+          if (!cmdbusy_i) begin
+            progbuf_d[dmi_req_i.addr[$clog2(dm::ProgBufSize)-1:0]] = dmi_req_i.data;
+            // check whether we need to re-execute the command (just give a cmd_valid)
+            // this should probably throw an error if executed during another command
+            // was busy
+            // range of autoexecprogbuf is 31:16
+            cmd_valid_d = abstractauto_q.autoexecprogbuf[{1'b1, dmi_req_i.addr[3:0]}];
+          end
+        end
+        dm::SBCS: begin
+          // access while the SBA was busy
+          if (sbbusy_i) begin
+            sbcs_d.sbbusyerror = 1'b1;
+          end else begin
+            sbcs = dm::sbcs_t'(dmi_req_i.data);
+            sbcs_d = sbcs;
+            // R/W1C
+            sbcs_d.sbbusyerror = sbcs_q.sbbusyerror & (~sbcs.sbbusyerror);
+            sbcs_d.sberror     = sbcs_q.sberror     & (~sbcs.sberror);
+          end
+        end
+        dm::SBAddress0: begin
+          // access while the SBA was busy
+          if (sbbusy_i) begin
+            sbcs_d.sbbusyerror = 1'b1;
+          end else begin
+            sbaddr_d[31:0] = dmi_req_i.data;
+            sbaddress_write_valid_o = (sbcs_q.sberror == '0);
+          end
+        end
+        dm::SBAddress1: begin
+          // access while the SBA was busy
+          if (sbbusy_i) begin
+            sbcs_d.sbbusyerror = 1'b1;
+          end else begin
+            sbaddr_d[63:32] = dmi_req_i.data;
+          end
+        end
+        dm::SBData0: begin
+          // access while the SBA was busy
+          if (sbbusy_i) begin
+           sbcs_d.sbbusyerror = 1'b1;
+          end else begin
+            sbdata_d[31:0] = dmi_req_i.data;
+            sbdata_write_valid_o = (sbcs_q.sberror == '0);
+          end
+        end
+        dm::SBData1: begin
+          // access while the SBA was busy
+          if (sbbusy_i) begin
+           sbcs_d.sbbusyerror = 1'b1;
+          end else begin
+            sbdata_d[63:32] = dmi_req_i.data;
+          end
+        end
+        default:;
+      endcase
+    end
+    // hart threw a command error and has precedence over bus writes
+    if (cmderror_valid_i) begin
+      cmderr_d = cmderror_i;
+    end
+
+    // update data registers
+    if (data_valid_i) begin
+      data_d = data_i;
+    end
+
+    // set the havereset flag when we did a ndmreset
+    if (ndmreset_o) begin
+      havereset_d_aligned[NrHarts-1:0] = '1;
+    end
+    // -------------
+    // System Bus
+    // -------------
+    // set bus error
+    if (sberror_valid_i) begin
+      sbcs_d.sberror = sberror_i;
+    end
+    // update read data
+    if (sbdata_valid_i) begin
+      sbdata_d = 64'(sbdata_i);
+    end
+
+    // dmcontrol
+    // TODO(zarubaf) we currently do not implement the hartarry mask
+    dmcontrol_d.hasel           = 1'b0;
+    // we do not support resetting an individual hart
+    dmcontrol_d.hartreset       = 1'b0;
+    dmcontrol_d.setresethaltreq = 1'b0;
+    dmcontrol_d.clrresethaltreq = 1'b0;
+    dmcontrol_d.zero1           = '0;
+    dmcontrol_d.zero0           = '0;
+    // Non-writeable, clear only
+    dmcontrol_d.ackhavereset    = 1'b0;
+    if (!dmcontrol_q.resumereq && dmcontrol_d.resumereq) begin
+      clear_resumeack_o = 1'b1;
+    end
+    if (dmcontrol_q.resumereq && resumeack_i) begin
+      dmcontrol_d.resumereq = 1'b0;
+    end
+    // static values for dcsr
+    sbcs_d.sbversion            = 3'b1;
+    sbcs_d.sbbusy               = sbbusy_i;
+    sbcs_d.sbasize              = $bits(sbcs_d.sbasize)'(BusWidth);
+    sbcs_d.sbaccess128          = 1'b0;
+    sbcs_d.sbaccess64           = logic'(BusWidth == 32'd64);
+    sbcs_d.sbaccess32           = logic'(BusWidth == 32'd32);
+    sbcs_d.sbaccess16           = 1'b0;
+    sbcs_d.sbaccess8            = 1'b0;
+    sbcs_d.sbaccess             = (BusWidth == 32'd64) ? 3'd3 : 3'd2;
+  end
+
+  // output multiplexer
+  always_comb begin : p_outmux
+    selected_hart = hartsel_o[HartSelLen-1:0];
+    // default assignment
+    haltreq_o = '0;
+    resumereq_o = '0;
+    if (selected_hart < (HartSelLen+1)'(NrHarts)) begin
+      haltreq_o[selected_hart]   = dmcontrol_q.haltreq;
+      resumereq_o[selected_hart] = dmcontrol_q.resumereq;
+    end
+  end
+
+  assign dmactive_o  = dmcontrol_q.dmactive;
+  assign cmd_o       = command_q;
+  assign cmd_valid_o = cmd_valid_q;
+  assign progbuf_o   = progbuf_q;
+  assign data_o      = data_q;
+
+  assign resp_queue_pop = dmi_resp_ready_i & ~resp_queue_empty;
+
+  assign ndmreset_o = dmcontrol_q.ndmreset;
+
+  // response FIFO
+  fifo_v2 #(
+    .dtype            ( logic [31:0]         ),
+    .DEPTH            ( 2                    )
+  ) i_fifo (
+    .clk_i            ( clk_i                ),
+    .rst_ni           ( dmi_rst_ni           ), // reset only when system is re-set
+    .flush_i          ( 1'b0                 ), // we do not need to flush this queue
+    .testmode_i       ( testmode_i           ),
+    .full_o           ( resp_queue_full      ),
+    .empty_o          ( resp_queue_empty     ),
+    .alm_full_o       (                      ),
+    .alm_empty_o      (                      ),
+    .data_i           ( resp_queue_data      ),
+    .push_i           ( resp_queue_push      ),
+    .data_o           ( dmi_resp_o.data      ),
+    .pop_i            ( resp_queue_pop       )
+  );
+
+  always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs
+    // PoR
+    if (!rst_ni) begin
+      dmcontrol_q    <= '0;
+      // this is the only write-able bit during reset
+      cmderr_q       <= dm::CmdErrNone;
+      command_q      <= '0;
+      abstractauto_q <= '0;
+      progbuf_q      <= '0;
+      data_q         <= '0;
+      sbcs_q         <= '0;
+      sbaddr_q       <= '0;
+      sbdata_q       <= '0;
+      havereset_q    <= '1;
+    end else begin
+      havereset_q    <= SelectableHarts & havereset_d;
+      // synchronous re-set of debug module, active-low, except for dmactive
+      if (!dmcontrol_q.dmactive) begin
+        dmcontrol_q.haltreq          <= '0;
+        dmcontrol_q.resumereq        <= '0;
+        dmcontrol_q.hartreset        <= '0;
+        dmcontrol_q.ackhavereset     <= '0;
+        dmcontrol_q.zero1            <= '0;
+        dmcontrol_q.hasel            <= '0;
+        dmcontrol_q.hartsello        <= '0;
+        dmcontrol_q.hartselhi        <= '0;
+        dmcontrol_q.zero0            <= '0;
+        dmcontrol_q.setresethaltreq  <= '0;
+        dmcontrol_q.clrresethaltreq  <= '0;
+        dmcontrol_q.ndmreset         <= '0;
+        // this is the only write-able bit during reset
+        dmcontrol_q.dmactive         <= dmcontrol_d.dmactive;
+        cmderr_q                     <= dm::CmdErrNone;
+        command_q                    <= '0;
+        cmd_valid_q                  <= '0;
+        abstractauto_q               <= '0;
+        progbuf_q                    <= '0;
+        data_q                       <= '0;
+        sbcs_q                       <= '0;
+        sbaddr_q                     <= '0;
+        sbdata_q                     <= '0;
+      end else begin
+        dmcontrol_q                  <= dmcontrol_d;
+        cmderr_q                     <= cmderr_d;
+        command_q                    <= command_d;
+        cmd_valid_q                  <= cmd_valid_d;
+        abstractauto_q               <= abstractauto_d;
+        progbuf_q                    <= progbuf_d;
+        data_q                       <= data_d;
+        sbcs_q                       <= sbcs_d;
+        sbaddr_q                     <= sbaddr_d;
+        sbdata_q                     <= sbdata_d;
+      end
+    end
+  end
+
+  ///////////////////////////////////////////////////////
+  // assertions
+  ///////////////////////////////////////////////////////
+
+  //pragma translate_off
+  `ifndef VERILATOR
+  haltsum: assert property (
+      @(posedge clk_i) disable iff (!rst_ni)
+          (dmi_req_ready_o && dmi_req_valid_i && dtm_op == dm::DTM_READ) |->
+              !({1'b0, dmi_req_i.addr} inside
+                  {dm::HaltSum0, dm::HaltSum1, dm::HaltSum2, dm::HaltSum3}))
+      else $warning("Haltsums have not been properly tested yet.");
+  `endif
+  //pragma translate_on
+
+endmodule : dm_csrs

snapshots/pulp-platform_riscv-dbg_pr53/src/dm_mem.sv

@@ -0,0 +1,497 @@
+/* Copyright 2018 ETH Zurich and University of Bologna.
+* Copyright and related rights are licensed under the Solderpad Hardware
+* License, Version 0.51 (the “License”); you may not use this file except in
+* compliance with the License.  You may obtain a copy of the License at
+* http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
+* or agreed to in writing, software, hardware and materials distributed under
+* this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR
+* CONDITIONS OF ANY KIND, either express or implied. See the License for the
+* specific language governing permissions and limitations under the License.
+*
+* File:   dm_mem.sv
+* Author: Florian Zaruba <zarubaf@iis.ee.ethz.ch>
+* Date:   11.7.2018
+*
+* Description: Memory module for execution-based debug clients
+*
+*/
+
+module dm_mem #(
+  parameter int unsigned        NrHarts          =  1,
+  parameter int unsigned        BusWidth         = 32,
+  parameter logic [NrHarts-1:0] SelectableHarts  = {NrHarts{1'b1}}
+) (
+  input  logic                             clk_i,       // Clock
+  input  logic                             rst_ni,      // debug module reset
+
+  output logic [NrHarts-1:0]               debug_req_o,
+  input  logic [19:0]                      hartsel_i,
+  // from Ctrl and Status register
+  input  logic [NrHarts-1:0]               haltreq_i,
+  input  logic [NrHarts-1:0]               resumereq_i,
+  input  logic                             clear_resumeack_i,
+
+  // state bits
+  output logic [NrHarts-1:0]               halted_o,    // hart acknowledge halt
+  output logic [NrHarts-1:0]               resuming_o,  // hart is resuming
+
+  input  logic [dm::ProgBufSize-1:0][31:0] progbuf_i,    // program buffer to expose
+
+  input  logic [dm::DataCount-1:0][31:0]   data_i,       // data in
+  output logic [dm::DataCount-1:0][31:0]   data_o,       // data out
+  output logic                             data_valid_o, // data out is valid
+  // abstract command interface
+  input  logic                             cmd_valid_i,
+  input  dm::command_t                     cmd_i,
+  output logic                             cmderror_valid_o,
+  output dm::cmderr_e                      cmderror_o,
+  output logic                             cmdbusy_o,
+  // data interface
+
+  // SRAM interface
+  input  logic                             req_i,
+  input  logic                             we_i,
+  input  logic [BusWidth-1:0]              addr_i,
+  input  logic [BusWidth-1:0]              wdata_i,
+  input  logic [BusWidth/8-1:0]            be_i,
+  output logic [BusWidth-1:0]              rdata_o
+);
+  localparam int unsigned DbgAddressBits = 12;
+  localparam int unsigned HartSelLen     = (NrHarts == 1) ? 1 : $clog2(NrHarts);
+  localparam int unsigned NrHartsAligned = 2**HartSelLen;
+  localparam int unsigned MaxAar         = (BusWidth == 64) ? 4 : 3;
+
+  localparam logic [DbgAddressBits-1:0] DataBaseAddr        = (dm::DataAddr);
+  localparam logic [DbgAddressBits-1:0] DataEndAddr         = (dm::DataAddr + 4*dm::DataCount - 1);
+  localparam logic [DbgAddressBits-1:0] ProgBufBaseAddr     = (dm::DataAddr - 4*dm::ProgBufSize);
+  localparam logic [DbgAddressBits-1:0] ProgBufEndAddr      = (dm::DataAddr - 1);
+  localparam logic [DbgAddressBits-1:0] AbstractCmdBaseAddr = (ProgBufBaseAddr - 4*10);
+  localparam logic [DbgAddressBits-1:0] AbstractCmdEndAddr  = (ProgBufBaseAddr - 1);
+
+  localparam logic [DbgAddressBits-1:0] WhereToAddr   = 'h300;
+  localparam logic [DbgAddressBits-1:0] FlagsBaseAddr = 'h400;
+  localparam logic [DbgAddressBits-1:0] FlagsEndAddr  = 'h7FF;
+
+  localparam logic [DbgAddressBits-1:0] HaltedAddr    = 'h100;
+  localparam logic [DbgAddressBits-1:0] GoingAddr     = 'h104;
+  localparam logic [DbgAddressBits-1:0] ResumingAddr  = 'h108;
+  localparam logic [DbgAddressBits-1:0] ExceptionAddr = 'h10C;
+
+  logic [dm::ProgBufSize/2-1:0][63:0]   progbuf;
+  logic [7:0][63:0]   abstract_cmd;
+  logic [NrHarts-1:0] halted_d, halted_q;
+  logic [NrHarts-1:0] resuming_d, resuming_q;
+  logic               resume, go, going;
+
+  logic exception;
+  logic unsupported_command;
+
+  logic [63:0] rom_rdata;
+  logic [63:0] rdata_d, rdata_q;
+  logic        word_enable32_q;
+
+  // this is needed to avoid lint warnings related to array indexing
+  // resize hartsel to valid range
+  logic [HartSelLen-1:0] hartsel, wdata_hartsel;
+
+  assign hartsel       = hartsel_i[HartSelLen-1:0];
+  assign wdata_hartsel = wdata_i[HartSelLen-1:0];
+
+  logic [NrHartsAligned-1:0] resumereq_aligned, haltreq_aligned,
+                             halted_d_aligned, halted_q_aligned,
+                             halted_aligned, resumereq_wdata_aligned,
+                             resuming_d_aligned, resuming_q_aligned;
+
+  assign resumereq_aligned       = NrHartsAligned'(resumereq_i);
+  assign haltreq_aligned         = NrHartsAligned'(haltreq_i);
+  assign resumereq_wdata_aligned = NrHartsAligned'(resumereq_i);
+
+  assign halted_q_aligned        = NrHartsAligned'(halted_q);
+  assign halted_d                = NrHarts'(halted_d_aligned);
+  assign resuming_q_aligned      = NrHartsAligned'(resuming_q);
+  assign resuming_d              = NrHarts'(resuming_d_aligned);
+
+  // distinguish whether we need to forward data from the ROM or the FSM
+  // latch the address for this
+  logic fwd_rom_d, fwd_rom_q;
+  dm::ac_ar_cmd_t ac_ar;
+
+  // Abstract Command Access Register
+  assign ac_ar       = dm::ac_ar_cmd_t'(cmd_i.control);
+  assign debug_req_o = haltreq_i;
+  assign halted_o    = halted_q;
+  assign resuming_o  = resuming_q;
+
+  // reshape progbuf
+  assign progbuf = progbuf_i;
+
+  typedef enum logic [1:0] { Idle, Go, Resume, CmdExecuting } state_e;
+  state_e state_d, state_q;
+
+  // hart ctrl queue
+  always_comb begin : p_hart_ctrl_queue
+    cmderror_valid_o = 1'b0;
+    cmderror_o       = dm::CmdErrNone;
+    state_d          = state_q;
+    go               = 1'b0;
+    resume           = 1'b0;
+    cmdbusy_o        = 1'b1;
+
+    unique case (state_q)
+      Idle: begin
+        cmdbusy_o = 1'b0;
+        if (cmd_valid_i && halted_q_aligned[hartsel] && !unsupported_command) begin
+          // give the go signal
+          state_d = Go;
+        end else if (cmd_valid_i) begin
+          // hart must be halted for all requests
+          cmderror_valid_o = 1'b1;
+          cmderror_o = dm::CmdErrorHaltResume;
+        end
+        // CSRs want to resume, the request is ignored when the hart is
+        // requested to halt or it didn't clear the resuming_q bit before
+        if (resumereq_aligned[hartsel] && !resuming_q_aligned[hartsel] &&
+            !haltreq_aligned[hartsel] && halted_q_aligned[hartsel]) begin
+          state_d = Resume;
+        end
+      end
+
+      Go: begin
+        // we are already busy here since we scheduled the execution of a program
+        cmdbusy_o = 1'b1;
+        go        = 1'b1;
+        // the thread is now executing the command, track its state
+        if (going) begin
+            state_d = CmdExecuting;
+        end
+      end
+
+      Resume: begin
+        cmdbusy_o = 1'b1;
+        resume = 1'b1;
+        if (resuming_q_aligned[hartsel]) begin
+          state_d = Idle;
+        end
+      end
+
+      CmdExecuting: begin
+        cmdbusy_o = 1'b1;
+        go        = 1'b0;
+        // wait until the hart has halted again
+        if (halted_aligned[hartsel]) begin
+          state_d = Idle;
+        end
+      end
+
+      default: ;
+    endcase
+
+    // only signal once that cmd is unsupported so that we can clear cmderr
+    // in subsequent writes to abstractcs
+    if (unsupported_command && cmd_valid_i) begin
+      cmderror_valid_o = 1'b1;
+      cmderror_o = dm::CmdErrNotSupported;
+    end
+
+    if (exception) begin
+      cmderror_valid_o = 1'b1;
+      cmderror_o = dm::CmdErrorException;
+    end
+  end
+
+  // word mux for 32bit and 64bit buses
+  logic [63:0] word_mux;
+  assign word_mux = (fwd_rom_q) ? rom_rdata : rdata_q;
+
+  if (BusWidth == 64) begin : gen_word_mux64
+    assign rdata_o = word_mux;
+  end else begin : gen_word_mux32
+    assign rdata_o = (word_enable32_q) ? word_mux[32 +: 32] : word_mux[0 +: 32];
+  end
+
+  // read/write logic
+  logic [63:0] data_bits;
+  logic [7:0][7:0] rdata;
+  always_comb begin : p_rw_logic
+
+    halted_d_aligned   = NrHartsAligned'(halted_q);
+    resuming_d_aligned = NrHartsAligned'(resuming_q);
+    rdata_d        = rdata_q;
+    // convert the data in bits representation
+    data_bits      = data_i;
+    rdata          = '0;
+
+    // write data in csr register
+    data_valid_o   = 1'b0;
+    exception      = 1'b0;
+    halted_aligned     = '0;
+    going          = 1'b0;
+
+    // The resume ack signal is lowered when the resume request is deasserted
+    if (clear_resumeack_i) begin
+      resuming_d_aligned[hartsel] = 1'b0;
+    end
+    // we've got a new request
+    if (req_i) begin
+      // this is a write
+      if (we_i) begin
+        unique case (addr_i[DbgAddressBits-1:0]) inside
+          HaltedAddr: begin
+            halted_aligned[wdata_hartsel] = 1'b1;
+            halted_d_aligned[wdata_hartsel] = 1'b1;
+          end
+          GoingAddr: begin
+            going = 1'b1;
+          end
+          ResumingAddr: begin
+            // clear the halted flag as the hart resumed execution
+            halted_d_aligned[wdata_hartsel] = 1'b0;
+            // set the resuming flag which needs to be cleared by the debugger
+            resuming_d_aligned[wdata_hartsel] = 1'b1;
+          end
+          // an exception occurred during execution
+          ExceptionAddr: exception = 1'b1;
+          // core can write data registers
+          [DataBaseAddr:DataEndAddr]: begin
+            data_valid_o = 1'b1;
+            for (int i = 0; i < $bits(be_i); i++) begin
+              if (be_i[i]) begin
+                data_bits[i*8+:8] = wdata_i[i*8+:8];
+              end
+            end
+          end
+          default ;
+        endcase
+
+      // this is a read
+      end else begin
+        unique case (addr_i[DbgAddressBits-1:0]) inside
+          // variable ROM content
+          WhereToAddr: begin
+            // variable jump to abstract cmd, program_buffer or resume
+            if (resumereq_wdata_aligned[wdata_hartsel]) begin
+              rdata_d = {32'b0, dm::jal('0, 21'(dm::ResumeAddress[11:0])-21'(WhereToAddr))};
+            end
+
+            // there is a command active so jump there
+            if (cmdbusy_o) begin
+              // transfer not set is shortcut to the program buffer if postexec is set
+              // keep this statement narrow to not catch invalid commands
+              if (cmd_i.cmdtype == dm::AccessRegister &&
+                  !ac_ar.transfer && ac_ar.postexec) begin
+                rdata_d = {32'b0, dm::jal('0, 21'(ProgBufBaseAddr)-21'(WhereToAddr))};
+              // this is a legit abstract cmd -> execute it
+              end else begin
+                rdata_d = {32'b0, dm::jal('0, 21'(AbstractCmdBaseAddr)-21'(WhereToAddr))};
+              end
+            end
+          end
+
+          [DataBaseAddr:DataEndAddr]: begin
+            rdata_d = {
+                      data_i[$clog2(dm::ProgBufSize)'(addr_i[DbgAddressBits-1:3] -
+                          DataBaseAddr[DbgAddressBits-1:3] + 1'b1)],
+                      data_i[$clog2(dm::ProgBufSize)'(addr_i[DbgAddressBits-1:3] -
+                          DataBaseAddr[DbgAddressBits-1:3])]
+                      };
+          end
+
+          [ProgBufBaseAddr:ProgBufEndAddr]: begin
+            rdata_d = progbuf[$clog2(dm::ProgBufSize)'(addr_i[DbgAddressBits-1:3] -
+                          ProgBufBaseAddr[DbgAddressBits-1:3])];
+          end
+
+          // two slots for abstract command
+          [AbstractCmdBaseAddr:AbstractCmdEndAddr]: begin
+            // return the correct address index
+            rdata_d = abstract_cmd[3'(addr_i[DbgAddressBits-1:3] -
+                           AbstractCmdBaseAddr[DbgAddressBits-1:3])];
+          end
+          // harts are polling for flags here
+          [FlagsBaseAddr:FlagsEndAddr]: begin
+            // release the corresponding hart
+            if (({addr_i[DbgAddressBits-1:3], 3'b0} - FlagsBaseAddr[DbgAddressBits-1:0]) ==
+              (DbgAddressBits'(hartsel) & {{(DbgAddressBits-3){1'b1}}, 3'b0})) begin
+              rdata[DbgAddressBits'(hartsel) & DbgAddressBits'(3'b111)] = {6'b0, resume, go};
+            end
+            rdata_d = rdata;
+          end
+          default: ;
+        endcase
+      end
+    end
+
+    data_o = data_bits;
+  end
+
+  always_comb begin : p_abstract_cmd_rom
+    // this abstract command is currently unsupported
+    unsupported_command = 1'b0;
+    // default memory
+    // if ac_ar.transfer is not set then we can take a shortcut to the program buffer
+    abstract_cmd[0][31:0]  = dm::illegal();
+    // load debug module base address into a0, this is shared among all commands
+    abstract_cmd[0][63:32] = dm::auipc(5'd10, '0);
+    abstract_cmd[1][31:0]  = dm::srli(5'd10, 5'd10, 6'd12); // clr lowest 12b -> DM base offset
+    abstract_cmd[1][63:32] = dm::slli(5'd10, 5'd10, 6'd12);
+    abstract_cmd[2][31:0]  = dm::nop();
+    abstract_cmd[2][63:32] = dm::nop();
+    abstract_cmd[3][31:0]  = dm::nop();
+    abstract_cmd[3][63:32] = dm::nop();
+    abstract_cmd[4][31:0]  = dm::csrr(dm::CSR_DSCRATCH1, 5'd10);
+    abstract_cmd[4][63:32] = dm::ebreak();
+    abstract_cmd[7:5]      = '0;
+
+    // this depends on the command being executed
+    unique case (cmd_i.cmdtype)
+      // --------------------
+      // Access Register
+      // --------------------
+      dm::AccessRegister: begin
+        if (32'(ac_ar.aarsize) < MaxAar && ac_ar.transfer && ac_ar.write) begin
+          // store a0 in dscratch1
+          abstract_cmd[0][31:0] = dm::csrw(dm::CSR_DSCRATCH1, 5'd10);
+          // this range is reserved
+          if (ac_ar.regno[15:14] != '0) begin
+            abstract_cmd[0][31:0] = dm::ebreak(); // we leave asap
+            unsupported_command = 1'b1;
+          // A0 access needs to be handled separately, as we use A0 to load
+          // the DM address offset need to access DSCRATCH1 in this case
+          end else if (ac_ar.regno[12] && (!ac_ar.regno[5]) &&
+                      (ac_ar.regno[4:0] == 5'd10)) begin
+            // store s0 in dscratch
+            abstract_cmd[2][31:0]  = dm::csrw(dm::CSR_DSCRATCH0, 5'd8);
+            // load from data register
+            abstract_cmd[2][63:32] = dm::load(ac_ar.aarsize, 5'd8, 5'd10, dm::DataAddr);
+            // and store it in the corresponding CSR
+            abstract_cmd[3][31:0]  = dm::csrw(dm::CSR_DSCRATCH1, 5'd8);
+            // restore s0 again from dscratch
+            abstract_cmd[3][63:32] = dm::csrr(dm::CSR_DSCRATCH0, 5'd8);
+          // GPR/FPR access
+          end else if (ac_ar.regno[12]) begin
+            // determine whether we want to access the floating point register or not
+            if (ac_ar.regno[5]) begin
+              abstract_cmd[2][31:0] =
+                  dm::float_load(ac_ar.aarsize, ac_ar.regno[4:0], 5'd10, dm::DataAddr);
+            end else begin
+              abstract_cmd[2][31:0] =
+                  dm::load(ac_ar.aarsize, ac_ar.regno[4:0], 5'd10, dm::DataAddr);
+            end
+          // CSR access
+          end else begin
+            // data register to CSR
+            // store s0 in dscratch
+            abstract_cmd[2][31:0]  = dm::csrw(dm::CSR_DSCRATCH0, 5'd8);
+            // load from data register
+            abstract_cmd[2][63:32] = dm::load(ac_ar.aarsize, 5'd8, 5'd10, dm::DataAddr);
+            // and store it in the corresponding CSR
+            abstract_cmd[3][31:0]  = dm::csrw(dm::csr_reg_t'(ac_ar.regno[11:0]), 5'd8);
+            // restore s0 again from dscratch
+            abstract_cmd[3][63:32] = dm::csrr(dm::CSR_DSCRATCH0, 5'd8);
+          end
+        end else if (32'(ac_ar.aarsize) < MaxAar && ac_ar.transfer && !ac_ar.write) begin
+          // store a0 in dscratch1
+          abstract_cmd[0][31:0]  = dm::csrw(dm::CSR_DSCRATCH1, 5'd10);
+          // this range is reserved
+          if (ac_ar.regno[15:14] != '0) begin
+              abstract_cmd[0][31:0] = dm::ebreak(); // we leave asap
+              unsupported_command = 1'b1;
+          // A0 access needs to be handled separately, as we use A0 to load
+          // the DM address offset need to access DSCRATCH1 in this case
+          end else if (ac_ar.regno[12] && (!ac_ar.regno[5]) &&
+                      (ac_ar.regno[4:0] == 5'd10)) begin
+            // store s0 in dscratch
+            abstract_cmd[2][31:0]  = dm::csrw(dm::CSR_DSCRATCH0, 5'd8);
+            // read value from CSR into s0
+            abstract_cmd[2][63:32] = dm::csrr(dm::CSR_DSCRATCH1, 5'd8);
+            // and store s0 into data section
+            abstract_cmd[3][31:0]  = dm::store(ac_ar.aarsize, 5'd8, 5'd10, dm::DataAddr);
+            // restore s0 again from dscratch
+            abstract_cmd[3][63:32] = dm::csrr(dm::CSR_DSCRATCH0, 5'd8);
+          // GPR/FPR access
+          end else if (ac_ar.regno[12]) begin
+            // determine whether we want to access the floating point register or not
+            if (ac_ar.regno[5]) begin
+              abstract_cmd[2][31:0] =
+                  dm::float_store(ac_ar.aarsize, ac_ar.regno[4:0], 5'd10, dm::DataAddr);
+            end else begin
+              abstract_cmd[2][31:0] =
+                  dm::store(ac_ar.aarsize, ac_ar.regno[4:0], 5'd10, dm::DataAddr);
+            end
+          // CSR access
+          end else begin
+            // CSR register to data
+            // store s0 in dscratch
+            abstract_cmd[2][31:0]  = dm::csrw(dm::CSR_DSCRATCH0, 5'd8);
+            // read value from CSR into s0
+            abstract_cmd[2][63:32] = dm::csrr(dm::csr_reg_t'(ac_ar.regno[11:0]), 5'd8);
+            // and store s0 into data section
+            abstract_cmd[3][31:0]  = dm::store(ac_ar.aarsize, 5'd8, 5'd10, dm::DataAddr);
+            // restore s0 again from dscratch
+            abstract_cmd[3][63:32] = dm::csrr(dm::CSR_DSCRATCH0, 5'd8);
+          end
+        end else if (32'(ac_ar.aarsize) >= MaxAar || ac_ar.aarpostincrement == 1'b1) begin
+          // this should happend when e.g. ac_ar.aarsize >= MaxAar
+          // Openocd will try to do an access with aarsize=64 bits
+          // first before falling back to 32 bits.
+          abstract_cmd[0][31:0] = dm::ebreak(); // we leave asap
+          unsupported_command = 1'b1;
+        end
+
+        // Check whether we need to execute the program buffer. When we
+        // get an unsupported command we really should abort instead of
+        // still trying to execute the program buffer, makes it easier
+        // for the debugger to recover
+        if (ac_ar.postexec && !unsupported_command) begin
+          // issue a nop, we will automatically run into the program buffer
+          abstract_cmd[4][63:32] = dm::nop();
+        end
+      end
+      // not supported at the moment
+      // dm::QuickAccess:;
+      // dm::AccessMemory:;
+      default: begin
+        abstract_cmd[0][31:0] = dm::ebreak();
+        unsupported_command = 1'b1;
+      end
+    endcase
+  end
+
+  logic [63:0] rom_addr;
+  assign rom_addr = 64'(addr_i);
+  debug_rom i_debug_rom (
+    .clk_i,
+    .req_i,
+    .addr_i  ( rom_addr  ),
+    .rdata_o ( rom_rdata )
+  );
+
+  // ROM starts at the HaltAddress of the core e.g.: it immediately jumps to
+  // the ROM base address
+  assign fwd_rom_d = logic'(addr_i[DbgAddressBits-1:0] >= dm::HaltAddress[DbgAddressBits-1:0]);
+
+  always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs
+    if (!rst_ni) begin
+      fwd_rom_q       <= 1'b0;
+      rdata_q         <= '0;
+      state_q         <= Idle;
+      word_enable32_q <= 1'b0;
+    end else begin
+      fwd_rom_q       <= fwd_rom_d;
+      rdata_q         <= rdata_d;
+      state_q         <= state_d;
+      word_enable32_q <= addr_i[2];
+    end
+  end
+
+  always_ff @(posedge clk_i or negedge rst_ni) begin
+    if (!rst_ni) begin
+      halted_q   <= 1'b0;
+      resuming_q <= 1'b0;
+    end else begin
+      halted_q   <= SelectableHarts & halted_d;
+      resuming_q <= SelectableHarts & resuming_d;
+    end
+  end
+
+endmodule : dm_mem

snapshots/pulp-platform_riscv-dbg_pr53/src/dm_pkg.sv

@@ -0,0 +1,414 @@
+/* Copyright 2018 ETH Zurich and University of Bologna.
+ * Copyright and related rights are licensed under the Solderpad Hardware
+ * License, Version 0.51 (the “License”); you may not use this file except in
+ * compliance with the License.  You may obtain a copy of the License at
+ * http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
+ * or agreed to in writing, software, hardware and materials distributed under
+ * this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR
+ * CONDITIONS OF ANY KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations under the License.
+ *
+ * File:   dm_pkg.sv
+ * Author: Florian Zaruba <zarubaf@iis.ee.ethz.ch>
+ * Date:   30.6.2018
+ *
+ * Description: Debug-module package, contains common system definitions.
+ *
+ */
+
+package dm;
+  localparam logic [3:0] DbgVersion013 = 4'h2;
+  // size of program buffer in junks of 32-bit words
+  localparam logic [4:0] ProgBufSize   = 5'h8;
+
+  // amount of data count registers implemented
+  localparam logic [3:0] DataCount     = 4'h2;
+
+  // address to which a hart should jump when it was requested to halt
+  localparam logic [63:0] HaltAddress = 64'h800;
+  localparam logic [63:0] ResumeAddress = HaltAddress + 4;
+  localparam logic [63:0] ExceptionAddress = HaltAddress + 8;
+
+  // address where data0-15 is shadowed or if shadowed in a CSR
+  // address of the first CSR used for shadowing the data
+  localparam logic [11:0] DataAddr = 12'h380; // we are aligned with Rocket here
+
+  // debug registers
+  typedef enum logic [7:0] {
+    Data0        = 8'h04,
+    Data1        = 8'h05,
+    Data2        = 8'h06,
+    Data3        = 8'h07,
+    Data4        = 8'h08,
+    Data5        = 8'h09,
+    Data6        = 8'h0A,
+    Data7        = 8'h0B,
+    Data8        = 8'h0C,
+    Data9        = 8'h0D,
+    Data10       = 8'h0E,
+    Data11       = 8'h0F,
+    DMControl    = 8'h10,
+    DMStatus     = 8'h11, // r/o
+    Hartinfo     = 8'h12,
+    HaltSum1     = 8'h13,
+    HAWindowSel  = 8'h14,
+    HAWindow     = 8'h15,
+    AbstractCS   = 8'h16,
+    Command      = 8'h17,
+    AbstractAuto = 8'h18,
+    DevTreeAddr0 = 8'h19,
+    DevTreeAddr1 = 8'h1A,
+    DevTreeAddr2 = 8'h1B,
+    DevTreeAddr3 = 8'h1C,
+    NextDM       = 8'h1D,
+    ProgBuf0     = 8'h20,
+    ProgBuf15    = 8'h2F,
+    AuthData     = 8'h30,
+    HaltSum2     = 8'h34,
+    HaltSum3     = 8'h35,
+    SBAddress3   = 8'h37,
+    SBCS         = 8'h38,
+    SBAddress0   = 8'h39,
+    SBAddress1   = 8'h3A,
+    SBAddress2   = 8'h3B,
+    SBData0      = 8'h3C,
+    SBData1      = 8'h3D,
+    SBData2      = 8'h3E,
+    SBData3      = 8'h3F,
+    HaltSum0     = 8'h40
+  } dm_csr_e;
+
+  // debug causes
+  localparam logic [2:0] CauseBreakpoint = 3'h1;
+  localparam logic [2:0] CauseTrigger    = 3'h2;
+  localparam logic [2:0] CauseRequest    = 3'h3;
+  localparam logic [2:0] CauseSingleStep = 3'h4;
+
+  typedef struct packed {
+    logic [31:23] zero1;
+    logic         impebreak;
+    logic [21:20] zero0;
+    logic         allhavereset;
+    logic         anyhavereset;
+    logic         allresumeack;
+    logic         anyresumeack;
+    logic         allnonexistent;
+    logic         anynonexistent;
+    logic         allunavail;
+    logic         anyunavail;
+    logic         allrunning;
+    logic         anyrunning;
+    logic         allhalted;
+    logic         anyhalted;
+    logic         authenticated;
+    logic         authbusy;
+    logic         hasresethaltreq;
+    logic         devtreevalid;
+    logic [3:0]   version;
+  } dmstatus_t;
+
+  typedef struct packed {
+    logic         haltreq;
+    logic         resumereq;
+    logic         hartreset;
+    logic         ackhavereset;
+    logic         zero1;
+    logic         hasel;
+    logic [25:16] hartsello;
+    logic [15:6]  hartselhi;
+    logic [5:4]   zero0;
+    logic         setresethaltreq;
+    logic         clrresethaltreq;
+    logic         ndmreset;
+    logic         dmactive;
+  } dmcontrol_t;
+
+  typedef struct packed {
+    logic [31:24] zero1;
+    logic [23:20] nscratch;
+    logic [19:17] zero0;
+    logic         dataaccess;
+    logic [15:12] datasize;
+    logic [11:0]  dataaddr;
+  } hartinfo_t;
+
+  typedef enum logic [2:0] {
+    CmdErrNone, CmdErrBusy, CmdErrNotSupported,
+    CmdErrorException, CmdErrorHaltResume,
+    CmdErrorBus, CmdErrorOther = 7
+  } cmderr_e;
+
+  typedef struct packed {
+    logic [31:29] zero3;
+    logic [28:24] progbufsize;
+    logic [23:13] zero2;
+    logic         busy;
+    logic         zero1;
+    cmderr_e      cmderr;
+    logic [7:4]   zero0;
+    logic [3:0]   datacount;
+  } abstractcs_t;
+
+  typedef enum logic [7:0] {
+    AccessRegister = 8'h0,
+    QuickAccess    = 8'h1,
+    AccessMemory   = 8'h2
+  } cmd_e;
+
+  typedef struct packed {
+    cmd_e        cmdtype;
+    logic [23:0] control;
+  } command_t;
+
+  typedef struct packed {
+    logic [31:16] autoexecprogbuf;
+    logic [15:12] zero0;
+    logic [11:0]  autoexecdata;
+  } abstractauto_t;
+
+  typedef struct packed {
+    logic         zero1;
+    logic [22:20] aarsize;
+    logic         aarpostincrement;
+    logic         postexec;
+    logic         transfer;
+    logic         write;
+    logic [15:0]  regno;
+  } ac_ar_cmd_t;
+
+  // DTM
+  typedef enum logic [1:0] {
+    DTM_NOP   = 2'h0,
+    DTM_READ  = 2'h1,
+    DTM_WRITE = 2'h2
+  } dtm_op_e;
+
+  typedef struct packed {
+    logic [31:29] sbversion;
+    logic [28:23] zero0;
+    logic         sbbusyerror;
+    logic         sbbusy;
+    logic         sbreadonaddr;
+    logic [19:17] sbaccess;
+    logic         sbautoincrement;
+    logic         sbreadondata;
+    logic [14:12] sberror;
+    logic [11:5]  sbasize;
+    logic         sbaccess128;
+    logic         sbaccess64;
+    logic         sbaccess32;
+    logic         sbaccess16;
+    logic         sbaccess8;
+  } sbcs_t;
+
+  localparam logic[1:0] DTM_SUCCESS = 2'h0;
+
+  typedef struct packed {
+    logic [6:0]  addr;
+    dtm_op_e     op;
+    logic [31:0] data;
+  } dmi_req_t;
+
+  typedef struct packed  {
+    logic [31:0] data;
+    logic [1:0]  resp;
+  } dmi_resp_t;
+
+  // privilege levels
+  typedef enum logic[1:0] {
+    PRIV_LVL_M = 2'b11,
+    PRIV_LVL_S = 2'b01,
+    PRIV_LVL_U = 2'b00
+  } priv_lvl_t;
+
+  // debugregs in core
+  typedef struct packed {
+    logic [31:28]     xdebugver;
+    logic [27:16]     zero2;
+    logic             ebreakm;
+    logic             zero1;
+    logic             ebreaks;
+    logic             ebreaku;
+    logic             stepie;
+    logic             stopcount;
+    logic             stoptime;
+    logic [8:6]       cause;
+    logic             zero0;
+    logic             mprven;
+    logic             nmip;
+    logic             step;
+    priv_lvl_t        prv;
+  } dcsr_t;
+
+  // CSRs
+  typedef enum logic [11:0] {
+    // Floating-Point CSRs
+    CSR_FFLAGS         = 12'h001,
+    CSR_FRM            = 12'h002,
+    CSR_FCSR           = 12'h003,
+    CSR_FTRAN          = 12'h800,
+    // Supervisor Mode CSRs
+    CSR_SSTATUS        = 12'h100,
+    CSR_SIE            = 12'h104,
+    CSR_STVEC          = 12'h105,
+    CSR_SCOUNTEREN     = 12'h106,
+    CSR_SSCRATCH       = 12'h140,
+    CSR_SEPC           = 12'h141,
+    CSR_SCAUSE         = 12'h142,
+    CSR_STVAL          = 12'h143,
+    CSR_SIP            = 12'h144,
+    CSR_SATP           = 12'h180,
+    // Machine Mode CSRs
+    CSR_MSTATUS        = 12'h300,
+    CSR_MISA           = 12'h301,
+    CSR_MEDELEG        = 12'h302,
+    CSR_MIDELEG        = 12'h303,
+    CSR_MIE            = 12'h304,
+    CSR_MTVEC          = 12'h305,
+    CSR_MCOUNTEREN     = 12'h306,
+    CSR_MSCRATCH       = 12'h340,
+    CSR_MEPC           = 12'h341,
+    CSR_MCAUSE         = 12'h342,
+    CSR_MTVAL          = 12'h343,
+    CSR_MIP            = 12'h344,
+    CSR_PMPCFG0        = 12'h3A0,
+    CSR_PMPADDR0       = 12'h3B0,
+    CSR_MVENDORID      = 12'hF11,
+    CSR_MARCHID        = 12'hF12,
+    CSR_MIMPID         = 12'hF13,
+    CSR_MHARTID        = 12'hF14,
+    CSR_MCYCLE         = 12'hB00,
+    CSR_MINSTRET       = 12'hB02,
+    CSR_DCACHE         = 12'h701,
+    CSR_ICACHE         = 12'h700,
+
+    CSR_TSELECT        = 12'h7A0,
+    CSR_TDATA1         = 12'h7A1,
+    CSR_TDATA2         = 12'h7A2,
+    CSR_TDATA3         = 12'h7A3,
+    CSR_TINFO          = 12'h7A4,
+
+    // Debug CSR
+    CSR_DCSR           = 12'h7b0,
+    CSR_DPC            = 12'h7b1,
+    CSR_DSCRATCH0      = 12'h7b2, // optional
+    CSR_DSCRATCH1      = 12'h7b3, // optional
+
+    // Counters and Timers
+    CSR_CYCLE          = 12'hC00,
+    CSR_TIME           = 12'hC01,
+    CSR_INSTRET        = 12'hC02
+  } csr_reg_t;
+
+
+  // Instruction Generation Helpers
+  function automatic logic [31:0] jal (logic [4:0]  rd,
+                                       logic [20:0] imm);
+    // OpCode Jal
+    return {imm[20], imm[10:1], imm[11], imm[19:12], rd, 7'h6f};
+  endfunction
+
+  function automatic logic [31:0] jalr (logic [4:0]  rd,
+                                        logic [4:0]  rs1,
+                                        logic [11:0] offset);
+    // OpCode Jal
+    return {offset[11:0], rs1, 3'b0, rd, 7'h67};
+  endfunction
+
+  function automatic logic [31:0] andi (logic [4:0]  rd,
+                                        logic [4:0]  rs1,
+                                        logic [11:0] imm);
+    // OpCode andi
+    return {imm[11:0], rs1, 3'h7, rd, 7'h13};
+  endfunction
+
+  function automatic logic [31:0] slli (logic [4:0] rd,
+                                        logic [4:0] rs1,
+                                        logic [5:0] shamt);
+    // OpCode slli
+    return {6'b0, shamt[5:0], rs1, 3'h1, rd, 7'h13};
+  endfunction
+
+  function automatic logic [31:0] srli (logic [4:0] rd,
+                                        logic [4:0] rs1,
+                                        logic [5:0] shamt);
+    // OpCode srli
+    return {6'b0, shamt[5:0], rs1, 3'h5, rd, 7'h13};
+  endfunction
+
+  function automatic logic [31:0] load (logic [2:0]  size,
+                                        logic [4:0]  dest,
+                                        logic [4:0]  base,
+                                        logic [11:0] offset);
+    // OpCode Load
+    return {offset[11:0], base, size, dest, 7'h03};
+  endfunction
+
+  function automatic logic [31:0] auipc (logic [4:0]  rd,
+                                         logic [20:0] imm);
+    // OpCode Auipc
+    return {imm[20], imm[10:1], imm[11], imm[19:12], rd, 7'h17};
+  endfunction
+
+  function automatic logic [31:0] store (logic [2:0]  size,
+                                         logic [4:0]  src,
+                                         logic [4:0]  base,
+                                         logic [11:0] offset);
+    // OpCode Store
+    return {offset[11:5], src, base, size, offset[4:0], 7'h23};
+  endfunction
+
+  function automatic logic [31:0] float_load (logic [2:0]  size,
+                                              logic [4:0]  dest,
+                                              logic [4:0]  base,
+                                              logic [11:0] offset);
+    // OpCode Load
+    return {offset[11:0], base, size, dest, 7'b00_001_11};
+  endfunction
+
+  function automatic logic [31:0] float_store (logic [2:0]  size,
+                                               logic [4:0]  src,
+                                               logic [4:0]  base,
+                                               logic [11:0] offset);
+    // OpCode Store
+    return {offset[11:5], src, base, size, offset[4:0], 7'b01_001_11};
+  endfunction
+
+  function automatic logic [31:0] csrw (csr_reg_t   csr,
+                                        logic [4:0] rs1);
+    // CSRRW, rd, OpCode System
+    return {csr, rs1, 3'h1, 5'h0, 7'h73};
+  endfunction
+
+  function automatic logic [31:0] csrr (csr_reg_t   csr,
+                                        logic [4:0] dest);
+    // rs1, CSRRS, rd, OpCode System
+    return {csr, 5'h0, 3'h2, dest, 7'h73};
+  endfunction
+
+  function automatic logic [31:0] branch(logic [4:0]  src2,
+                                         logic [4:0]  src1,
+                                         logic [2:0]  funct3,
+                                         logic [11:0] offset);
+    // OpCode Branch
+    return {offset[11], offset[9:4], src2, src1, funct3,
+        offset[3:0], offset[10], 7'b11_000_11};
+  endfunction
+
+  function automatic logic [31:0] ebreak ();
+    return 32'h00100073;
+  endfunction
+
+  function automatic logic [31:0] wfi ();
+    return 32'h10500073;
+  endfunction
+
+  function automatic logic [31:0] nop ();
+    return 32'h00000013;
+  endfunction
+
+  function automatic logic [31:0] illegal ();
+    return 32'h00000000;
+  endfunction
+
+endpackage : dm

snapshots/pulp-platform_riscv-dbg_pr53/src/dm_sba.sv

@@ -0,0 +1,172 @@
+/* Copyright 2018 ETH Zurich and University of Bologna.
+* Copyright and related rights are licensed under the Solderpad Hardware
+* License, Version 0.51 (the “License”); you may not use this file except in
+* compliance with the License.  You may obtain a copy of the License at
+* http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
+* or agreed to in writing, software, hardware and materials distributed under
+* this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR
+* CONDITIONS OF ANY KIND, either express or implied. See the License for the
+* specific language governing permissions and limitations under the License.
+*
+* File:   dm_sba.sv
+* Author: Florian Zaruba <zarubaf@iis.ee.ethz.ch>
+* Date:   1.8.2018
+*
+* Description: System Bus Access Module
+*
+*/
+module dm_sba #(
+  parameter int unsigned BusWidth = 32
+) (
+  input  logic                   clk_i,       // Clock
+  input  logic                   rst_ni,
+  input  logic                   dmactive_i,  // synchronous reset active low
+
+  output logic                   master_req_o,
+  output logic [BusWidth-1:0]    master_add_o,
+  output logic                   master_we_o,
+  output logic [BusWidth-1:0]    master_wdata_o,
+  output logic [BusWidth/8-1:0]  master_be_o,
+  input  logic                   master_gnt_i,
+  input  logic                   master_r_valid_i,
+  input  logic [BusWidth-1:0]    master_r_rdata_i,
+
+  input  logic [BusWidth-1:0]    sbaddress_i,
+  input  logic                   sbaddress_write_valid_i,
+  // control signals in
+  input  logic                   sbreadonaddr_i,
+  output logic [BusWidth-1:0]    sbaddress_o,
+  input  logic                   sbautoincrement_i,
+  input  logic [2:0]             sbaccess_i,
+  // data in
+  input  logic                   sbreadondata_i,
+  input  logic [BusWidth-1:0]    sbdata_i,
+  input  logic                   sbdata_read_valid_i,
+  input  logic                   sbdata_write_valid_i,
+  // read data out
+  output logic [BusWidth-1:0]    sbdata_o,
+  output logic                   sbdata_valid_o,
+  // control signals
+  output logic                   sbbusy_o,
+  output logic                   sberror_valid_o, // bus error occurred
+  output logic [2:0]             sberror_o // bus error occurred
+);
+
+  typedef enum logic [2:0] { Idle, Read, Write, WaitRead, WaitWrite } state_e;
+  state_e state_d, state_q;
+
+  logic [BusWidth-1:0]           address;
+  logic                          req;
+  logic                          gnt;
+  logic                          we;
+  logic [BusWidth/8-1:0]         be;
+  logic [$clog2(BusWidth/8)-1:0] be_idx;
+
+  assign sbbusy_o = logic'(state_q != Idle);
+
+  always_comb begin : p_fsm
+    req     = 1'b0;
+    address = sbaddress_i;
+    we      = 1'b0;
+    be      = '0;
+    be_idx  = sbaddress_i[$clog2(BusWidth/8)-1:0];
+
+    sberror_o       = '0;
+    sberror_valid_o = 1'b0;
+    sbaddress_o     = sbaddress_i;
+
+    state_d = state_q;
+
+    unique case (state_q)
+      Idle: begin
+        // debugger requested a read
+        if (sbaddress_write_valid_i && sbreadonaddr_i)  state_d = Read;
+        // debugger requested a write
+        if (sbdata_write_valid_i) state_d = Write;
+        // perform another read
+        if (sbdata_read_valid_i && sbreadondata_i) state_d = Read;
+      end
+
+      Read: begin
+        req = 1'b1;
+        if (gnt) state_d = WaitRead;
+      end
+
+      Write: begin
+        req = 1'b1;
+        we  = 1'b1;
+        // generate byte enable mask
+        unique case (sbaccess_i)
+          3'b000: begin
+            be[be_idx] = '1;
+          end
+          3'b001: begin
+            be[int'({be_idx[$high(be_idx):1], 1'b0}) +: 2] = '1;
+          end
+          3'b010: begin
+            if (BusWidth == 32'd64) be[int'({be_idx[$high(be_idx)], 2'b0}) +: 4] = '1;
+            else                    be = '1;
+          end
+          3'b011: be = '1;
+          default: ;
+        endcase
+        if (gnt) state_d = WaitWrite;
+      end
+
+      WaitRead: begin
+        if (sbdata_valid_o) begin
+          state_d = Idle;
+          // auto-increment address
+          if (sbautoincrement_i) sbaddress_o = sbaddress_i + (32'b1 << sbaccess_i);
+        end
+      end
+
+      WaitWrite: begin
+        if (sbdata_valid_o) begin
+          state_d = Idle;
+          // auto-increment address
+          if (sbautoincrement_i) sbaddress_o = sbaddress_i + (32'b1 << sbaccess_i);
+        end
+      end
+
+      default: state_d = Idle; // catch parasitic state
+    endcase
+
+    // handle error case
+    if (sbaccess_i > 3 && state_q != Idle) begin
+      req             = 1'b0;
+      state_d         = Idle;
+      sberror_valid_o = 1'b1;
+      sberror_o       = 3'd3;
+    end
+    // further error handling should go here ...
+  end
+
+  always_ff @(posedge clk_i or negedge rst_ni) begin : p_regs
+    if (!rst_ni) begin
+      state_q <= Idle;
+    end else begin
+      state_q <= state_d;
+    end
+  end
+
+  assign master_req_o    = req;
+  assign master_add_o    = address[BusWidth-1:0];
+  assign master_we_o     = we;
+  assign master_wdata_o  = sbdata_i[BusWidth-1:0];
+  assign master_be_o     = be[BusWidth/8-1:0];
+  assign gnt             = master_gnt_i;
+  assign sbdata_valid_o  = master_r_valid_i;
+  assign sbdata_o        = master_r_rdata_i[BusWidth-1:0];
+
+
+  //pragma translate_off
+  `ifndef VERILATOR
+    // maybe bump severity to $error if not handled at runtime
+    dm_sba_access_size: assert property(@(posedge clk_i) disable iff (dmactive_i !== 1'b0)
+        (state_d != Idle) |-> (sbaccess_i < 4))
+            else $warning ("accesses > 8 byte not supported at the moment");
+  `endif
+  //pragma translate_on
+
+endmodule : dm_sba

snapshots/pulp-platform_riscv-dbg_pr53/src/dm_top.sv

@@ -0,0 +1,222 @@
+/* Copyright 2018 ETH Zurich and University of Bologna.
+* Copyright and related rights are licensed under the Solderpad Hardware
+* License, Version 0.51 (the “License”); you may not use this file except in
+* compliance with the License.  You may obtain a copy of the License at
+* http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
+* or agreed to in writing, software, hardware and materials distributed under
+* this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR
+* CONDITIONS OF ANY KIND, either express or implied. See the License for the
+* specific language governing permissions and limitations under the License.
+*
+* File:   dm_top.sv
+* Author: Florian Zaruba <zarubaf@iis.ee.ethz.ch>
+* Date:   30.6.2018
+*
+* Description: Top-level of debug module (DM). This is an AXI-Slave.
+*              DTM protocol is equal to SiFives debug protocol to leverage
+*              SW infrastructure re-use. As of version 0.13
+*/
+
+module dm_top #(
+  parameter int unsigned        NrHarts          = 1,
+  parameter int unsigned        BusWidth         = 32,
+  // Bitmask to select physically available harts for systems
+  // that don't use hart numbers in a contiguous fashion.
+  parameter logic [NrHarts-1:0] SelectableHarts  = {NrHarts{1'b1}}
+) (
+  input  logic                  clk_i,       // clock
+  input  logic                  rst_ni,      // asynchronous reset active low, connect PoR here, not the system reset
+  input  logic                  testmode_i,
+  output logic                  ndmreset_o,  // non-debug module reset
+  output logic                  dmactive_o,  // debug module is active
+  output logic [NrHarts-1:0]    debug_req_o, // async debug request
+  input  logic [NrHarts-1:0]    unavailable_i, // communicate whether the hart is unavailable (e.g.: power down)
+  dm::hartinfo_t [NrHarts-1:0]  hartinfo_i,
+
+  input  logic                  slave_req_i,
+  input  logic                  slave_we_i,
+  input  logic [BusWidth-1:0]   slave_addr_i,
+  input  logic [BusWidth/8-1:0] slave_be_i,
+  input  logic [BusWidth-1:0]   slave_wdata_i,
+  output logic [BusWidth-1:0]   slave_rdata_o,
+
+  output logic                  master_req_o,
+  output logic [BusWidth-1:0]   master_add_o,
+  output logic                  master_we_o,
+  output logic [BusWidth-1:0]   master_wdata_o,
+  output logic [BusWidth/8-1:0] master_be_o,
+  input  logic                  master_gnt_i,
+  input  logic                  master_r_valid_i,
+  input  logic [BusWidth-1:0]   master_r_rdata_i,
+
+  // Connection to DTM - compatible to RocketChip Debug Module
+  input  logic                  dmi_rst_ni,
+  input  logic                  dmi_req_valid_i,
+  output logic                  dmi_req_ready_o,
+  input  dm::dmi_req_t          dmi_req_i,
+
+  output logic                  dmi_resp_valid_o,
+  input  logic                  dmi_resp_ready_i,
+  output dm::dmi_resp_t         dmi_resp_o
+);
+
+  // Debug CSRs
+  logic [NrHarts-1:0]               halted;
+  // logic [NrHarts-1:0]               running;
+  logic [NrHarts-1:0]               resumeack;
+  logic [NrHarts-1:0]               haltreq;
+  logic [NrHarts-1:0]               resumereq;
+  logic                             clear_resumeack;
+  logic                             cmd_valid;
+  dm::command_t                     cmd;
+
+  logic                             cmderror_valid;
+  dm::cmderr_e                      cmderror;
+  logic                             cmdbusy;
+  logic [dm::ProgBufSize-1:0][31:0] progbuf;
+  logic [dm::DataCount-1:0][31:0]   data_csrs_mem;
+  logic [dm::DataCount-1:0][31:0]   data_mem_csrs;
+  logic                             data_valid;
+  logic [19:0]                      hartsel;
+  // System Bus Access Module
+  logic [BusWidth-1:0]              sbaddress_csrs_sba;
+  logic [BusWidth-1:0]              sbaddress_sba_csrs;
+  logic                             sbaddress_write_valid;
+  logic                             sbreadonaddr;
+  logic                             sbautoincrement;
+  logic [2:0]                       sbaccess;
+  logic                             sbreadondata;
+  logic [BusWidth-1:0]              sbdata_write;
+  logic                             sbdata_read_valid;
+  logic                             sbdata_write_valid;
+  logic [BusWidth-1:0]              sbdata_read;
+  logic                             sbdata_valid;
+  logic                             sbbusy;
+  logic                             sberror_valid;
+  logic [2:0]                       sberror;
+
+
+  dm_csrs #(
+    .NrHarts(NrHarts),
+    .BusWidth(BusWidth),
+    .SelectableHarts(SelectableHarts)
+  ) i_dm_csrs (
+    .clk_i,
+    .rst_ni,
+    .testmode_i,
+    .dmi_rst_ni,
+    .dmi_req_valid_i,
+    .dmi_req_ready_o,
+    .dmi_req_i,
+    .dmi_resp_valid_o,
+    .dmi_resp_ready_i,
+    .dmi_resp_o,
+    .ndmreset_o,
+    .dmactive_o,
+    .hartsel_o               ( hartsel               ),
+    .hartinfo_i,
+    .halted_i                ( halted                ),
+    .unavailable_i,
+    .resumeack_i             ( resumeack             ),
+    .haltreq_o               ( haltreq               ),
+    .resumereq_o             ( resumereq             ),
+    .clear_resumeack_o       ( clear_resumeack       ),
+    .cmd_valid_o             ( cmd_valid             ),
+    .cmd_o                   ( cmd                   ),
+    .cmderror_valid_i        ( cmderror_valid        ),
+    .cmderror_i              ( cmderror              ),
+    .cmdbusy_i               ( cmdbusy               ),
+    .progbuf_o               ( progbuf               ),
+    .data_i                  ( data_mem_csrs         ),
+    .data_valid_i            ( data_valid            ),
+    .data_o                  ( data_csrs_mem         ),
+    .sbaddress_o             ( sbaddress_csrs_sba    ),
+    .sbaddress_i             ( sbaddress_sba_csrs    ),
+    .sbaddress_write_valid_o ( sbaddress_write_valid ),
+    .sbreadonaddr_o          ( sbreadonaddr          ),
+    .sbautoincrement_o       ( sbautoincrement       ),
+    .sbaccess_o              ( sbaccess              ),
+    .sbreadondata_o          ( sbreadondata          ),
+    .sbdata_o                ( sbdata_write          ),
+    .sbdata_read_valid_o     ( sbdata_read_valid     ),
+    .sbdata_write_valid_o    ( sbdata_write_valid    ),
+    .sbdata_i                ( sbdata_read           ),
+    .sbdata_valid_i          ( sbdata_valid          ),
+    .sbbusy_i                ( sbbusy                ),
+    .sberror_valid_i         ( sberror_valid         ),
+    .sberror_i               ( sberror               )
+  );
+
+  dm_sba #(
+    .BusWidth(BusWidth)
+  ) i_dm_sba (
+    .clk_i,
+    .rst_ni,
+    .dmactive_i              ( dmactive_o            ),
+
+    .master_req_o,
+    .master_add_o,
+    .master_we_o,
+    .master_wdata_o,
+    .master_be_o,
+    .master_gnt_i,
+    .master_r_valid_i,
+    .master_r_rdata_i,
+
+    .sbaddress_i             ( sbaddress_csrs_sba    ),
+    .sbaddress_o             ( sbaddress_sba_csrs    ),
+    .sbaddress_write_valid_i ( sbaddress_write_valid ),
+    .sbreadonaddr_i          ( sbreadonaddr          ),
+    .sbautoincrement_i       ( sbautoincrement       ),
+    .sbaccess_i              ( sbaccess              ),
+    .sbreadondata_i          ( sbreadondata          ),
+    .sbdata_i                ( sbdata_write          ),
+    .sbdata_read_valid_i     ( sbdata_read_valid     ),
+    .sbdata_write_valid_i    ( sbdata_write_valid    ),
+    .sbdata_o                ( sbdata_read           ),
+    .sbdata_valid_o          ( sbdata_valid          ),
+    .sbbusy_o                ( sbbusy                ),
+    .sberror_valid_o         ( sberror_valid         ),
+    .sberror_o               ( sberror               )
+  );
+
+  dm_mem #(
+    .NrHarts(NrHarts),
+    .BusWidth(BusWidth),
+    .SelectableHarts(SelectableHarts)
+  ) i_dm_mem (
+    .clk_i,
+    .rst_ni,
+    .debug_req_o,
+    .hartsel_i               ( hartsel               ),
+    .haltreq_i               ( haltreq               ),
+    .resumereq_i             ( resumereq             ),
+    .clear_resumeack_i       ( clear_resumeack       ),
+    .halted_o                ( halted                ),
+    .resuming_o              ( resumeack             ),
+    .cmd_valid_i             ( cmd_valid             ),
+    .cmd_i                   ( cmd                   ),
+    .cmderror_valid_o        ( cmderror_valid        ),
+    .cmderror_o              ( cmderror              ),
+    .cmdbusy_o               ( cmdbusy               ),
+    .progbuf_i               ( progbuf               ),
+    .data_i                  ( data_csrs_mem         ),
+    .data_o                  ( data_mem_csrs         ),
+    .data_valid_o            ( data_valid            ),
+    .req_i                   ( slave_req_i           ),
+    .we_i                    ( slave_we_i            ),
+    .addr_i                  ( slave_addr_i          ),
+    .wdata_i                 ( slave_wdata_i         ),
+    .be_i                    ( slave_be_i            ),
+    .rdata_o                 ( slave_rdata_o         )
+  );
+
+
+`ifndef VERILATOR
+  initial begin
+    assert (BusWidth == 32 || BusWidth == 64)
+        else $fatal(1, "DM needs a bus width of either 32 or 64 bits");
+  end
+`endif
+
+endmodule : dm_top

snapshots/pulp-platform_riscv-dbg_pr53/src/dmi_cdc.sv

@@ -0,0 +1,73 @@
+/* Copyright 2018 ETH Zurich and University of Bologna.
+* Copyright and related rights are licensed under the Solderpad Hardware
+* License, Version 0.51 (the “License”); you may not use this file except in
+* compliance with the License.  You may obtain a copy of the License at
+* http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
+* or agreed to in writing, software, hardware and materials distributed under
+* this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR
+* CONDITIONS OF ANY KIND, either express or implied. See the License for the
+* specific language governing permissions and limitations under the License.
+*
+* File:   axi_riscv_debug_module.sv
+* Author: Andreas Traber <atraber@iis.ee.ethz.ch>
+* Author: Florian Zaruba <zarubaf@iis.ee.ethz.ch>
+*
+* Description: Clock domain crossings for JTAG to DMI very heavily based
+*              on previous work by Andreas Traber for the PULP project.
+*              This is mainly a wrapper around the existing CDCs.
+*/
+module dmi_cdc (
+  // JTAG side (master side)
+  input  logic             tck_i,
+  input  logic             trst_ni,
+
+  input  dm::dmi_req_t     jtag_dmi_req_i,
+  output logic             jtag_dmi_ready_o,
+  input  logic             jtag_dmi_valid_i,
+
+  output dm::dmi_resp_t    jtag_dmi_resp_o,
+  output logic             jtag_dmi_valid_o,
+  input  logic             jtag_dmi_ready_i,
+
+  // core side (slave side)
+  input  logic             clk_i,
+  input  logic             rst_ni,
+
+  output dm::dmi_req_t     core_dmi_req_o,
+  output logic             core_dmi_valid_o,
+  input  logic             core_dmi_ready_i,
+
+  input dm::dmi_resp_t     core_dmi_resp_i,
+  output logic             core_dmi_ready_o,
+  input  logic             core_dmi_valid_i
+);
+
+  cdc_2phase #(.T(dm::dmi_req_t)) i_cdc_req (
+    .src_rst_ni  ( trst_ni          ),
+    .src_clk_i   ( tck_i            ),
+    .src_data_i  ( jtag_dmi_req_i   ),
+    .src_valid_i ( jtag_dmi_valid_i ),
+    .src_ready_o ( jtag_dmi_ready_o ),
+
+    .dst_rst_ni  ( rst_ni           ),
+    .dst_clk_i   ( clk_i            ),
+    .dst_data_o  ( core_dmi_req_o   ),
+    .dst_valid_o ( core_dmi_valid_o ),
+    .dst_ready_i ( core_dmi_ready_i )
+  );
+
+  cdc_2phase #(.T(dm::dmi_resp_t)) i_cdc_resp (
+    .src_rst_ni  ( rst_ni           ),
+    .src_clk_i   ( clk_i            ),
+    .src_data_i  ( core_dmi_resp_i  ),
+    .src_valid_i ( core_dmi_valid_i ),
+    .src_ready_o ( core_dmi_ready_o ),
+
+    .dst_rst_ni  ( trst_ni          ),
+    .dst_clk_i   ( tck_i            ),
+    .dst_data_o  ( jtag_dmi_resp_o  ),
+    .dst_valid_o ( jtag_dmi_valid_o ),
+    .dst_ready_i ( jtag_dmi_ready_i )
+  );
+
+endmodule : dmi_cdc

snapshots/pulp-platform_riscv-dbg_pr53/src/dmi_jtag.sv

@@ -0,0 +1,264 @@
+/* Copyright 2018 ETH Zurich and University of Bologna.
+* Copyright and related rights are licensed under the Solderpad Hardware
+* License, Version 0.51 (the “License”); you may not use this file except in
+* compliance with the License.  You may obtain a copy of the License at
+* http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
+* or agreed to in writing, software, hardware and materials distributed under
+* this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR
+* CONDITIONS OF ANY KIND, either express or implied. See the License for the
+* specific language governing permissions and limitations under the License.
+*
+* File:   axi_riscv_debug_module.sv
+* Author: Florian Zaruba <zarubaf@iis.ee.ethz.ch>
+* Date:   19.7.2018
+*
+* Description: JTAG DMI (debug module interface)
+*
+*/
+
+module dmi_jtag #(
+  parameter logic [31:0] IdcodeValue = 32'h00000001
+) (
+  input  logic         clk_i,      // DMI Clock
+  input  logic         rst_ni,     // Asynchronous reset active low
+  input  logic         testmode_i,
+
+  output logic         dmi_rst_no, // hard reset
+  output dm::dmi_req_t dmi_req_o,
+  output logic         dmi_req_valid_o,
+  input  logic         dmi_req_ready_i,
+
+  input dm::dmi_resp_t dmi_resp_i,
+  output logic         dmi_resp_ready_o,
+  input  logic         dmi_resp_valid_i,
+
+  input  logic         tck_i,    // JTAG test clock pad
+  input  logic         tms_i,    // JTAG test mode select pad
+  input  logic         trst_ni,  // JTAG test reset pad
+  input  logic         td_i,     // JTAG test data input pad
+  output logic         td_o,     // JTAG test data output pad
+  output logic         tdo_oe_o  // Data out output enable
+);
+  assign       dmi_rst_no = rst_ni;
+
+  logic        test_logic_reset;
+  logic        shift_dr;
+  logic        update_dr;
+  logic        capture_dr;
+  logic        dmi_access;
+  logic        dtmcs_select;
+  logic        dmi_reset;
+  logic        dmi_tdi;
+  logic        dmi_tdo;
+
+  dm::dmi_req_t  dmi_req;
+  logic          dmi_req_ready;
+  logic          dmi_req_valid;
+
+  dm::dmi_resp_t dmi_resp;
+  logic          dmi_resp_valid;
+  logic          dmi_resp_ready;
+
+  typedef struct packed {
+    logic [6:0]  address;
+    logic [31:0] data;
+    logic [1:0]  op;
+  } dmi_t;
+
+  typedef enum logic [1:0] {
+    DMINoError = 2'h0, DMIReservedError = 2'h1,
+    DMIOPFailed = 2'h2, DMIBusy = 2'h3
+  } dmi_error_e;
+
+  typedef enum logic [2:0] { Idle, Read, WaitReadValid, Write, WaitWriteValid } state_e;
+  state_e state_d, state_q;
+
+  logic [$bits(dmi_t)-1:0] dr_d, dr_q;
+  logic [6:0] address_d, address_q;
+  logic [31:0] data_d, data_q;
+
+  dmi_t  dmi;
+  assign dmi          = dmi_t'(dr_q);
+  assign dmi_req.addr = address_q;
+  assign dmi_req.data = data_q;
+  assign dmi_req.op   = (state_q == Write) ? dm::DTM_WRITE : dm::DTM_READ;
+  // we'will always be ready to accept the data we requested
+  assign dmi_resp_ready = 1'b1;
+
+  logic error_dmi_busy;
+  dmi_error_e error_d, error_q;
+
+  always_comb begin : p_fsm
+    error_dmi_busy = 1'b0;
+    // default assignments
+    state_d   = state_q;
+    address_d = address_q;
+    data_d    = data_q;
+    error_d   = error_q;
+
+    dmi_req_valid = 1'b0;
+
+    unique case (state_q)
+      Idle: begin
+        // make sure that no error is sticky
+        if (dmi_access && update_dr && (error_q == DMINoError)) begin
+          // save address and value
+          address_d = dmi.address;
+          data_d = dmi.data;
+          if (dm::dtm_op_e'(dmi.op) == dm::DTM_READ) begin
+            state_d = Read;
+          end else if (dm::dtm_op_e'(dmi.op) == dm::DTM_WRITE) begin
+            state_d = Write;
+          end
+          // else this is a nop and we can stay here
+        end
+      end
+
+      Read: begin
+        dmi_req_valid = 1'b1;
+        if (dmi_req_ready) begin
+          state_d = WaitReadValid;
+        end
+      end
+
+      WaitReadValid: begin
+        // load data into register and shift out
+        if (dmi_resp_valid) begin
+          data_d = dmi_resp.data;
+          state_d = Idle;
+        end
+      end
+
+      Write: begin
+        dmi_req_valid = 1'b1;
+        // got a valid answer go back to idle
+        if (dmi_req_ready) begin
+          state_d = Idle;
+        end
+      end
+
+      default: begin
+        // just wait for idle here
+        if (dmi_resp_valid) begin
+          state_d = Idle;
+        end
+      end
+    endcase
+
+    // update_dr means we got another request but we didn't finish
+    // the one in progress, this state is sticky
+    if (update_dr && state_q != Idle) begin
+      error_dmi_busy = 1'b1;
+    end
+
+    // if capture_dr goes high while we are in the read state
+    // or in the corresponding wait state we are not giving back a valid word
+    // -> throw an error
+    if (capture_dr && state_q inside {Read, WaitReadValid}) begin
+      error_dmi_busy = 1'b1;
+    end
+
+    if (error_dmi_busy) begin
+      error_d = DMIBusy;
+    end
+    // clear sticky error flag
+    if (dmi_reset && dtmcs_select) begin
+      error_d = DMINoError;
+    end
+  end
+
+  // shift register
+  assign dmi_tdo = dr_q[0];
+
+  always_comb begin : p_shift
+    dr_d    = dr_q;
+
+    if (capture_dr) begin
+      if (dmi_access) begin
+        if (error_q == DMINoError && !error_dmi_busy) begin
+          dr_d = {address_q, data_q, DMINoError};
+        // DMI was busy, report an error
+        end else if (error_q == DMIBusy || error_dmi_busy) begin
+          dr_d = {address_q, data_q, DMIBusy};
+        end
+      end
+    end
+
+    if (shift_dr) begin
+      if (dmi_access) begin
+        dr_d = {dmi_tdi, dr_q[$bits(dr_q)-1:1]};
+      end
+    end
+
+    if (test_logic_reset) begin
+      dr_d = '0;
+    end
+  end
+
+  always_ff @(posedge tck_i or negedge trst_ni) begin : p_regs
+    if (!trst_ni) begin
+      dr_q      <= '0;
+      state_q   <= Idle;
+      address_q <= '0;
+      data_q    <= '0;
+      error_q   <= DMINoError;
+    end else begin
+      dr_q      <= dr_d;
+      state_q   <= state_d;
+      address_q <= address_d;
+      data_q    <= data_d;
+      error_q   <= error_d;
+    end
+  end
+
+  // ---------
+  // TAP
+  // ---------
+  dmi_jtag_tap #(
+    .IrLength (5),
+    .IdcodeValue(IdcodeValue)
+  ) i_dmi_jtag_tap (
+    .tck_i,
+    .tms_i,
+    .trst_ni,
+    .td_i,
+    .td_o,
+    .tdo_oe_o,
+    .testmode_i,
+    .test_logic_reset_o ( test_logic_reset ),
+    .shift_dr_o         ( shift_dr         ),
+    .update_dr_o        ( update_dr        ),
+    .capture_dr_o       ( capture_dr       ),
+    .dmi_access_o       ( dmi_access       ),
+    .dtmcs_select_o     ( dtmcs_select     ),
+    .dmi_reset_o        ( dmi_reset        ),
+    .dmi_error_i        ( error_q          ),
+    .dmi_tdi_o          ( dmi_tdi          ),
+    .dmi_tdo_i          ( dmi_tdo          )
+  );
+
+  // ---------
+  // CDC
+  // ---------
+  dmi_cdc i_dmi_cdc (
+    // JTAG side (master side)
+    .tck_i,
+    .trst_ni,
+    .jtag_dmi_req_i    ( dmi_req          ),
+    .jtag_dmi_ready_o  ( dmi_req_ready    ),
+    .jtag_dmi_valid_i  ( dmi_req_valid    ),
+    .jtag_dmi_resp_o   ( dmi_resp         ),
+    .jtag_dmi_valid_o  ( dmi_resp_valid   ),
+    .jtag_dmi_ready_i  ( dmi_resp_ready   ),
+    // core side
+    .clk_i,
+    .rst_ni,
+    .core_dmi_req_o    ( dmi_req_o        ),
+    .core_dmi_valid_o  ( dmi_req_valid_o  ),
+    .core_dmi_ready_i  ( dmi_req_ready_i  ),
+    .core_dmi_resp_i   ( dmi_resp_i       ),
+    .core_dmi_ready_o  ( dmi_resp_ready_o ),
+    .core_dmi_valid_i  ( dmi_resp_valid_i )
+  );
+
+endmodule : dmi_jtag

snapshots/pulp-platform_riscv-dbg_pr53/src/dmi_jtag_tap.sv

@@ -0,0 +1,349 @@
+/* Copyright 2018 ETH Zurich and University of Bologna.
+ * Copyright and related rights are licensed under the Solderpad Hardware
+ * License, Version 0.51 (the “License”); you may not use this file except in
+ * compliance with the License.  You may obtain a copy of the License at
+ * http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
+ * or agreed to in writing, software, hardware and materials distributed under
+ * this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR
+ * CONDITIONS OF ANY KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations under the License.
+ *
+ * File:   dmi_jtag_tap.sv
+ * Author: Florian Zaruba <zarubaf@iis.ee.ethz.ch>
+ * Date:   19.7.2018
+ *
+ * Description: JTAG TAP for DMI (according to debug spec 0.13)
+ *
+ */
+
+module dmi_jtag_tap #(
+  parameter int unsigned IrLength = 5,
+  // JTAG IDCODE Value
+  parameter logic [31:0] IdcodeValue = 32'h00000001
+  // xxxx             version
+  // xxxxxxxxxxxxxxxx part number
+  // xxxxxxxxxxx      manufacturer id
+  // 1                required by standard
+) (
+  input  logic        tck_i,    // JTAG test clock pad
+  input  logic        tms_i,    // JTAG test mode select pad
+  input  logic        trst_ni,  // JTAG test reset pad
+  input  logic        td_i,     // JTAG test data input pad
+  output logic        td_o,     // JTAG test data output pad
+  output logic        tdo_oe_o, // Data out output enable
+  input  logic        testmode_i,
+  output logic        test_logic_reset_o,
+  output logic        shift_dr_o,
+  output logic        update_dr_o,
+  output logic        capture_dr_o,
+
+  // we want to access DMI register
+  output logic        dmi_access_o,
+  // JTAG is interested in writing the DTM CSR register
+  output logic        dtmcs_select_o,
+  // clear error state
+  output logic        dmi_reset_o,
+  input  logic [1:0]  dmi_error_i,
+  // test data to submodule
+  output logic        dmi_tdi_o,
+  // test data in from submodule
+  input  logic        dmi_tdo_i
+);
+
+  // to submodule
+  assign dmi_tdi_o = td_i;
+
+  typedef enum logic [3:0] {
+    TestLogicReset, RunTestIdle, SelectDrScan,
+    CaptureDr, ShiftDr, Exit1Dr, PauseDr, Exit2Dr,
+    UpdateDr, SelectIrScan, CaptureIr, ShiftIr,
+    Exit1Ir, PauseIr, Exit2Ir, UpdateIr
+  } tap_state_e;
+
+  tap_state_e tap_state_q, tap_state_d;
+
+  typedef enum logic [IrLength-1:0] {
+    BYPASS0   = 'h0,
+    IDCODE    = 'h1,
+    DTMCSR    = 'h10,
+    DMIACCESS = 'h11,
+    BYPASS1   = 'h1f
+  } ir_reg_e;
+
+  typedef struct packed {
+    logic [31:18] zero1;
+    logic         dmihardreset;
+    logic         dmireset;
+    logic         zero0;
+    logic [14:12] idle;
+    logic [11:10] dmistat;
+    logic [9:4]   abits;
+    logic [3:0]   version;
+  } dtmcs_t;
+
+  // ----------------
+  // IR logic
+  // ----------------
+
+  // shift register
+  logic [IrLength-1:0]  jtag_ir_shift_d, jtag_ir_shift_q;
+  // IR register -> this gets captured from shift register upon update_ir
+  ir_reg_e              jtag_ir_d, jtag_ir_q;
+  logic capture_ir, shift_ir, update_ir; // pause_ir
+
+  always_comb begin : p_jtag
+    jtag_ir_shift_d = jtag_ir_shift_q;
+    jtag_ir_d       = jtag_ir_q;
+
+    // IR shift register
+    if (shift_ir) begin
+      jtag_ir_shift_d = {td_i, jtag_ir_shift_q[IrLength-1:1]};
+    end
+
+    // capture IR register
+    if (capture_ir) begin
+      jtag_ir_shift_d =  IrLength'(4'b0101);
+    end
+
+    // update IR register
+    if (update_ir) begin
+      jtag_ir_d = ir_reg_e'(jtag_ir_shift_q);
+    end
+
+    // synchronous test-logic reset
+    if (test_logic_reset_o) begin
+      jtag_ir_shift_d = '0;
+      jtag_ir_d       = IDCODE;
+    end
+  end
+
+  always_ff @(posedge tck_i, negedge trst_ni) begin : p_jtag_ir_reg
+    if (!trst_ni) begin
+      jtag_ir_shift_q <= '0;
+      jtag_ir_q       <= IDCODE;
+    end else begin
+      jtag_ir_shift_q <= jtag_ir_shift_d;
+      jtag_ir_q       <= jtag_ir_d;
+    end
+  end
+
+  // ----------------
+  // TAP DR Regs
+  // ----------------
+  // - Bypass
+  // - IDCODE
+  // - DTM CS
+  logic [31:0] idcode_d, idcode_q;
+  logic        idcode_select;
+  logic        bypass_select;
+  dtmcs_t      dtmcs_d, dtmcs_q;
+  logic        bypass_d, bypass_q;  // this is a 1-bit register
+
+  assign dmi_reset_o = dtmcs_q.dmireset;
+
+  always_comb begin
+    idcode_d = idcode_q;
+    bypass_d = bypass_q;
+    dtmcs_d  = dtmcs_q;
+
+    if (capture_dr_o) begin
+      if (idcode_select) idcode_d = IdcodeValue;
+      if (bypass_select) bypass_d = 1'b0;
+      if (dtmcs_select_o) begin
+        dtmcs_d  = '{
+                      zero1        : '0,
+                      dmihardreset : 1'b0,
+                      dmireset     : 1'b0,
+                      zero0        : '0,
+                      idle         : 3'd1, // 1: Enter Run-Test/Idle and leave it immediately
+                      dmistat      : dmi_error_i, // 0: No error, 1: Op failed, 2: too fast
+                      abits        : 6'd7, // The size of address in dmi
+                      version      : 4'd1  // Version described in spec version 0.13 (and later?)
+                    };
+      end
+    end
+
+    if (shift_dr_o) begin
+      if (idcode_select)  idcode_d = {td_i, 31'(idcode_q >> 1)};
+      if (bypass_select)  bypass_d = td_i;
+      if (dtmcs_select_o) dtmcs_d  = {td_i, 31'(dtmcs_q >> 1)};
+    end
+
+    if (test_logic_reset_o) begin
+      idcode_d = IdcodeValue;
+      bypass_d = 1'b0;
+    end
+  end
+
+  // ----------------
+  // Data reg select
+  // ----------------
+  always_comb begin : p_data_reg_sel
+    dmi_access_o   = 1'b0;
+    dtmcs_select_o = 1'b0;
+    idcode_select  = 1'b0;
+    bypass_select  = 1'b0;
+    unique case (jtag_ir_q)
+      BYPASS0:   bypass_select  = 1'b1;
+      IDCODE:    idcode_select  = 1'b1;
+      DTMCSR:    dtmcs_select_o = 1'b1;
+      DMIACCESS: dmi_access_o   = 1'b1;
+      BYPASS1:   bypass_select  = 1'b1;
+      default:   bypass_select  = 1'b1;
+    endcase
+  end
+
+  // ----------------
+  // Output select
+  // ----------------
+  logic tdo_mux;
+
+  always_comb begin : p_out_sel
+    // we are shifting out the IR register
+    if (shift_ir) begin
+      tdo_mux = jtag_ir_shift_q[0];
+    // here we are shifting the DR register
+    end else begin
+      unique case (jtag_ir_q)
+        IDCODE:         tdo_mux = idcode_q[0];     // Reading ID code
+        DTMCSR:         tdo_mux = dtmcs_q.version[0];
+        DMIACCESS:      tdo_mux = dmi_tdo_i;       // Read from DMI TDO
+        default:        tdo_mux = bypass_q;      // BYPASS instruction
+      endcase
+    end
+  end
+
+  // ----------------
+  // DFT
+  // ----------------
+  logic tck_n, tck_ni;
+
+  cluster_clock_inverter i_tck_inv (
+    .clk_i ( tck_i  ),
+    .clk_o ( tck_ni )
+  );
+
+  pulp_clock_mux2 i_dft_tck_mux (
+    .clk0_i    ( tck_ni     ),
+    .clk1_i    ( tck_i      ), // bypass the inverted clock for testing
+    .clk_sel_i ( testmode_i ),
+    .clk_o     ( tck_n      )
+  );
+
+  // TDO changes state at negative edge of TCK
+  always_ff @(posedge tck_n, negedge trst_ni) begin : p_tdo_regs
+    if (!trst_ni) begin
+      td_o     <= 1'b0;
+      tdo_oe_o <= 1'b0;
+    end else begin
+      td_o     <= tdo_mux;
+      tdo_oe_o <= (shift_ir | shift_dr_o);
+    end
+  end
+  // ----------------
+  // TAP FSM
+  // ----------------
+  // Determination of next state; purely combinatorial
+  always_comb begin : p_tap_fsm
+
+    test_logic_reset_o = 1'b0;
+
+    capture_dr_o       = 1'b0;
+    shift_dr_o         = 1'b0;
+    update_dr_o        = 1'b0;
+
+    capture_ir         = 1'b0;
+    shift_ir           = 1'b0;
+    // pause_ir           = 1'b0; unused
+    update_ir          = 1'b0;
+
+    unique case (tap_state_q)
+      TestLogicReset: begin
+        tap_state_d = (tms_i) ? TestLogicReset : RunTestIdle;
+        test_logic_reset_o = 1'b1;
+      end
+      RunTestIdle: begin
+        tap_state_d = (tms_i) ? SelectDrScan : RunTestIdle;
+      end
+      // DR Path
+      SelectDrScan: begin
+        tap_state_d = (tms_i) ? SelectIrScan : CaptureDr;
+      end
+      CaptureDr: begin
+        capture_dr_o = 1'b1;
+        tap_state_d = (tms_i) ? Exit1Dr : ShiftDr;
+      end
+      ShiftDr: begin
+        shift_dr_o = 1'b1;
+        tap_state_d = (tms_i) ? Exit1Dr : ShiftDr;
+      end
+      Exit1Dr: begin
+        tap_state_d = (tms_i) ? UpdateDr : PauseDr;
+      end
+      PauseDr: begin
+        tap_state_d = (tms_i) ? Exit2Dr : PauseDr;
+      end
+      Exit2Dr: begin
+        tap_state_d = (tms_i) ? UpdateDr : ShiftDr;
+      end
+      UpdateDr: begin
+        update_dr_o = 1'b1;
+        tap_state_d = (tms_i) ? SelectDrScan : RunTestIdle;
+      end
+      // IR Path
+      SelectIrScan: begin
+        tap_state_d = (tms_i) ? TestLogicReset : CaptureIr;
+      end
+      // In this controller state, the shift register bank in the
+      // Instruction Register parallel loads a pattern of fixed values on
+      // the rising edge of TCK. The last two significant bits must always
+      // be "01".
+      CaptureIr: begin
+        capture_ir = 1'b1;
+        tap_state_d = (tms_i) ? Exit1Ir : ShiftIr;
+      end
+      // In this controller state, the instruction register gets connected
+      // between TDI and TDO, and the captured pattern gets shifted on
+      // each rising edge of TCK. The instruction available on the TDI
+      // pin is also shifted in to the instruction register.
+      ShiftIr: begin
+        shift_ir = 1'b1;
+        tap_state_d = (tms_i) ? Exit1Ir : ShiftIr;
+      end
+      Exit1Ir: begin
+        tap_state_d = (tms_i) ? UpdateIr : PauseIr;
+      end
+      PauseIr: begin
+        // pause_ir = 1'b1; // unused
+        tap_state_d = (tms_i) ? Exit2Ir : PauseIr;
+      end
+      Exit2Ir: begin
+        tap_state_d = (tms_i) ? UpdateIr : ShiftIr;
+      end
+      // In this controller state, the instruction in the instruction
+      // shift register is latched to the latch bank of the Instruction
+      // Register on every falling edge of TCK. This instruction becomes
+      // the current instruction once it is latched.
+      UpdateIr: begin
+        update_ir = 1'b1;
+        tap_state_d = (tms_i) ? SelectDrScan : RunTestIdle;
+      end
+      default: ; // can't actually happen since case is full
+    endcase
+  end
+
+  always_ff @(posedge tck_i or negedge trst_ni) begin : p_regs
+    if (!trst_ni) begin
+      tap_state_q <= RunTestIdle;
+      idcode_q    <= IdcodeValue;
+      bypass_q    <= 1'b0;
+      dtmcs_q     <= '0;
+    end else begin
+      tap_state_q <= tap_state_d;
+      idcode_q    <= idcode_d;
+      bypass_q    <= bypass_d;
+      dtmcs_q     <= dtmcs_d;
+    end
+  end
+
+endmodule : dmi_jtag_tap