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snapshots/jotego_jtcores_pr1100/cores/biocom/cfg/files.yaml

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+biocom:
+  - get:
+    - jtbiocom_colmix.v
+    - jtbiocom_game.v
+    - jtbiocom_main.v
+    - jtbiocom_mcu.v
+    - jtbiocom_video.v
+    - jtbiocom_sound.v
+tora:
+  - get:
+    - jttora_obj.v
+    - jttora_objdata.v
+gng:
+  - get:
+    - jtgng_video.yaml
+    - jtgng_dual_ram.v
+jtframe:
+  - from: clocking
+    get:
+      - jtframe_cen48.v
+      - jtframe_cen24.v
+  - from: cpu
+    get:
+      - jtframe_z80.yaml
+      - jtframe_m68k.yaml
+      - jtframe_8751.yaml
+  - from: ram
+    get:
+      - jtframe_ram.v
+      - jtframe_dual_ram.v
+      - jtframe_dual_ram16.v
+  - from: video
+    get:
+      - jtframe_blank.v
+      - jtframe_obj.yaml
+jt51:
+jt12:
+  - get:
+    - jt49.yaml
+    - jt12_rst.v

snapshots/jotego_jtcores_pr1100/cores/biocom/cfg/macros.def

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+CORENAME=JTBIOCOM
+
+JTFRAME_STEREO
+
+JTFRAME_CLK24
+JTFRAME_PXLCLK=6
+
+JTFRAME_COLORW=5
+JTFRAME_WIDTH=256
+JTFRAME_HEIGHT=224
+JTFRAME_CREDITS_PAGES=1
+
+# SDRAM
+JTFRAME_BA1_START =0x040000
+FIX_START=0x80000
+
+JTFRAME_BA2_START =0x088000
+
+JTFRAME_BA3_START =0x0C8000
+OBJ_START=0xD0000
+
+JTFRAME_PROM_START=0x110000
+
+[mist|sidi]
+#The logo doesn't fit in small devices
+JTFRAME_OSD_NOLOGO
+-JTFRAME_CREDITS
+
+[mister]
+JTFRAME_ARX=5
+JTFRAME_ARY=4

snapshots/jotego_jtcores_pr1100/cores/biocom/cfg/mame2mra.toml

@@ -0,0 +1,45 @@
+[global]
+author=["jotego"]
+
+[parse]
+sourcefile=[ "bionicc.cpp" ]
+# skip.Setnames=["bioniccbl2"]
+
+[Audio]
+volume = [
+    { machine="bionicc", value=0x40 },
+    ]
+    
+[buttons]
+names=[
+    { names="Shoot,Arm" }
+]
+
+[dipsw]
+rename=[
+    { name="Bonus Life", to="Bonus" },
+]
+
+[ROM]
+regions=[
+    { name="maincpu", width=16, reverse=true },
+    # gfx2 = scroll 2
+    { name="gfx2", width=16, reverse=true, start="JTFRAME_BA1_START", no_offset=true },
+    { name="gfx1", start="FIX_START", reverse=true },
+    { name="gfx3", width=16, sequence=[4,0,5,1,6,2,7,3], start="JTFRAME_BA2_START" },
+    { name="audiocpu", no_offset=true, start="JTFRAME_BA3_START" },
+    { name="spritegen", width=32, reverse=true, no_offset=true },
+    { name="mcu", start="JTFRAME_PROM_START" },
+]
+
+patches=[
+    { setname="topsecrt2", offset=4, data="00 00 a8 42" }, # skip initial test
+    { setname="topsecrt",  offset=4, data="00 00 90 42" }, # skip initial test
+]
+
+order=[ "maincpu",
+    "gfx2", "gfx1",
+    "gfx3",
+    "audiocpu", "spritegen",
+    "mcu","proms"
+]

snapshots/jotego_jtcores_pr1100/cores/biocom/cfg/mem.yaml

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+params:
+  - { name: FIX_OFFSET, value: "(`FIX_START-`JTFRAME_BA1_START)>>1" }
+  - { name: OBJ_OFFSET, value: "(`OBJ_START-`JTFRAME_BA3_START)>>1" }
+clocks:
+  clk48:
+    - freq: 8000000
+      outputs:
+        - video_cen8
+        - nc_cen4
+    - freq: 3579545
+      outputs:
+        - cen_fm
+        - cen_fm2
+  clk24:
+    - freq: 3000000
+      outputs:
+        - cen3
+        - mcu_cen
+audio:
+  rsum: 27k
+  channels:
+    - { name: fm, module: jt51, rsum: 27k, rc: [{r: 1rout, c: 3.3n }]}
+download:
+  post_addr: true
+sdram:
+  banks:
+    - buses:
+      - name: main
+        addr_width: 18
+        data_width: 16
+    - buses:
+      - name: scr2
+        addr_width: 16
+        data_width: 16
+        cs: LVBL
+      - name: char
+        addr_width: 14
+        data_width: 16
+        offset: FIX_OFFSET
+        cs: LVBL
+    - buses:
+      - name: scr1
+        addr_width: 18
+        data_width: 16
+        cs: LVBL
+    - buses:
+      - name: snd
+        addr_width: 15
+        data_width: 8
+      - name: obj
+        addr_width: 18
+        data_width: 32
+        offset: OBJ_OFFSET

snapshots/jotego_jtcores_pr1100/cores/biocom/cfg/msg

@@ -0,0 +1,25 @@
+        BIONIC COMMANDO
+        CLONE FOR FPGA
+    BROUGHT TO YOU BY JOTEGO.   
+  http://patreon.com/jotego
+
+        Thanks to
+
+  SCRALINGS   SUVERMAN
+
+FREDERIC MAHE  JO TOMIYORI
+BRIAN SALLEE   PHILLIP MCMAHON
+DUSTIN HUBBARD DANIEL BAUZA
+
+  Andrew Moore   Andyways
+  Don Gafford    J. Slowfret
+  Kyle Good      Leslie Law
+  M. Astudillo   Mary Marshall
+  Matthew Young  Oliver Jaksch
+  Blackstar      Oscar Laguna
+  Roman Buser    Ryan Fig
+  Steve Suavek   Steve Wilson
+  Toby Boreham   Xzarian
+  Xzarian        Sembiance
+victor Gomariz  Ultrarobotninja
+       WILLIAM CLEMENS          

snapshots/jotego_jtcores_pr1100/cores/biocom/doc/bionicc.cpp

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+// license:BSD-3-Clause
+// copyright-holders:Phil Stroffolino, Paul Leaman, Dirk Best
+// thanks-to: Steven Frew (the author of Slutte)
+/***************************************************************************
+
+    Bionic Commando
+
+    © 1987 Capcom
+
+    Hardware:
+
+        Main CPU board: 86612-A-2
+    Graphics ROM board: 86612-B-2
+     Program ROM board: 86612-C-2
+
+      Main CPU: 68000CP10        @ 24MHz / 2 = 12MHz
+     Sound CPU: Z80A             @ 14.31818 / 4 = 3.579545MHz
+           MCU: Intel C8751H-88  @ 24MHz / 4 = 6MHz
+    Sound Chip: YM2151 & YM3012
+           OSC: 24.000 MHz (on the 86612-B-2 PCB)
+        Custom: CAPCOM DL-010D-103 (on the 86612-B-2 PCB)
+
+    Video timings:
+
+    Horizontal scan rate: 15.606kHz
+    Vertical scan rate: 60.024Hz
+
+    pixel clock:         6.000MHz, 166ns per pixel
+
+    htotal:             64.076us, 386 pixels
+    hsync:               5.312us,  32 pixels
+    back porch + sync:  15.106us,  91 pixels
+    active video:       42.662us, 257 pixels (first pixel is repeated?)
+    front porch:         6.308us,  38 pixels
+
+    vtotal:             16.660ms, 260 lines
+    vsync:             256.304us,   4 lines
+    back porch + sync:   1.282ms,  20 lines
+    active video:       14.353ms, 224 lines
+    front porch:         1.025ms,  16 lines
+
+    Clocks verified on 86612-A-2 and 86612-B-2 boards, serial no. 39646
+    ("Bionic Commando", US region) by scope measurement at clock pins.
+    Timings verified at SYNC pin and BLUE pin (jamma edge),
+    using an Agilent DSO9404A scope and two N2873A 500MHz probes
+
+    BTANB [MT00209] (verified on real PCB):
+    - misplaced sprites (see beginning of level 1 or 2 for example)
+    - sprite / sprite priority (see level 2 the reflectors)
+    - sprite / background priority (see level 1: birds walk through
+      branches of different trees)
+    - see the beginning of level 3: background screwed
+    - gray tiles around the title in Top Secret
+
+    Notes:
+    - Protection MCU is labelled "TS" without a number and without a coloured.
+      Maybe its code is not region dependant.
+    - The MCU rom contains the string
+      "<for dealer-location test & USA show. 87/03/10 >"
+      which indicates it could be from an earlier version, especially with it
+      coming from a 'Top Secret' bootleg with identical program but unprotected
+      MCU, however f1dream has a similar string, and is verified as being from
+      a production board.
+    - Euro rom labels (IE: "TSE") had a blue stripe, while those labeled
+      as USA (TSU) had an red stripe on the sticker. The intermixing
+      of TSE and TSU roms in the parent set is correct and verified.
+    - Euro set simply states the game cannot be operated in Japan.
+    - IRQ 4 is control related. On each interrupt, it reads 0xFE4000
+      (coin/start), shift the bits around and move the resulting byte into a
+      dword RAM location. The dword RAM location is rotated by 8 bits each time
+      this happens. This is probably done to be pedantic about coin insertions
+      (might be protection related).
+
+    TODO:
+    - Firing IRQ4 at line 16 causes the game to often miss coin inserts. Set
+      to 128 currently to compensate.
+    - The game doesn't set the coin lockout in service mode, so the coin inputs
+      can't be tested there if you uncomment and enable it.
+
+***************************************************************************/
+
+#include "emu.h"
+
+#include "cpu/m68000/m68000.h"
+#include "cpu/mcs51/mcs51.h"
+#include "cpu/z80/z80.h"
+#include "machine/timer.h"
+#include "video/bufsprite.h"
+#include "tigeroad_spr.h"
+#include "sound/ymopm.h"
+#include "emupal.h"
+#include "screen.h"
+#include "speaker.h"
+#include "tilemap.h"
+
+
+//**************************************************************************
+//  TYPE DEFINITIONS
+//**************************************************************************
+
+class bionicc_state : public driver_device
+{
+public:
+	bionicc_state(const machine_config &mconfig, device_type type, const char *tag) :
+		driver_device(mconfig, type, tag),
+		m_maincpu(*this, "maincpu"),
+		m_audiocpu(*this, "audiocpu"),
+		m_mcu(*this, "mcu"),
+		m_gfxdecode(*this, "gfxdecode"),
+		m_palette(*this, "palette"),
+		m_spritegen(*this, "spritegen"),
+		m_spriteram(*this, "spriteram") ,
+		m_txvideoram(*this, "txvideoram"),
+		m_fgvideoram(*this, "fgvideoram"),
+		m_bgvideoram(*this, "bgvideoram"),
+		m_mcu_p3(0xff)
+	{ }
+
+	void bionicc(machine_config &config);
+
+protected:
+	virtual void machine_start() override;
+	virtual void machine_reset() override;
+	virtual void video_start() override;
+
+private:
+	required_device<cpu_device> m_maincpu;
+	required_device<cpu_device> m_audiocpu;
+	required_device<i8751_device> m_mcu;
+	required_device<gfxdecode_device> m_gfxdecode;
+	required_device<palette_device> m_palette;
+	required_device<tigeroad_spr_device> m_spritegen;
+	required_device<buffered_spriteram16_device> m_spriteram;
+
+	required_shared_ptr<uint16_t> m_txvideoram;
+	required_shared_ptr<uint16_t> m_fgvideoram;
+	required_shared_ptr<uint16_t> m_bgvideoram;
+
+	void main_map(address_map &map);
+	void sound_map(address_map &map);
+	void mcu_io(address_map &map);
+
+	void output_w(u8 data);
+
+	// video
+	TILE_GET_INFO_MEMBER(get_bg_tile_info);
+	TILE_GET_INFO_MEMBER(get_fg_tile_info);
+	TILE_GET_INFO_MEMBER(get_tx_tile_info);
+	static rgb_t RRRRGGGGBBBBIIII(uint32_t raw);
+	uint32_t screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
+	TIMER_DEVICE_CALLBACK_MEMBER(scanline);
+
+	void bgvideoram_w(offs_t offset, u16 data, u16 mem_mask = ~0);
+	void fgvideoram_w(offs_t offset, u16 data, u16 mem_mask = ~0);
+	void txvideoram_w(offs_t offset, u16 data, u16 mem_mask = ~0);
+	void scroll_w(offs_t offset, u16 data, u16 mem_mask = ~0);
+
+	tilemap_t   *m_tx_tilemap = nullptr;
+	tilemap_t   *m_bg_tilemap = nullptr;
+	tilemap_t   *m_fg_tilemap = nullptr;
+	uint16_t    m_scroll[4]{};
+
+	// audio
+	void audiocpu_nmi_w(u8 data);
+
+	// protection mcu
+	u8 m_audiocpu_to_mcu = 0; // ls374 at 4a
+	u8 m_mcu_to_audiocpu = 0; // ls374 at 5a
+	u8 m_mcu_p1 = 0;
+	u8 m_mcu_p3;
+
+	void dmaon_w(u16 data);
+	u8 mcu_dma_r(offs_t offset);
+	void mcu_dma_w(offs_t offset, u8 data);
+	void mcu_p3_w(u8 data);
+};
+
+
+//**************************************************************************
+//  ADDRESS MAPS
+//**************************************************************************
+
+void bionicc_state::main_map(address_map &map)
+{
+	map.global_mask(0xfffff);
+	map(0x00000, 0x3ffff).rom();
+	map(0xe0000, 0xe07ff).ram(); /* RAM? */
+	map(0xe0800, 0xe0cff).ram().share("spriteram");
+	map(0xe0d00, 0xe3fff).ram();              /* RAM? */
+	map(0xe4000, 0xe4000).mirror(0x3ffc).w(FUNC(bionicc_state::output_w));
+	map(0xe4000, 0xe4001).mirror(0x3ffc).portr("INPUTS");
+	map(0xe4002, 0xe4002).mirror(0x3ffc).w(FUNC(bionicc_state::audiocpu_nmi_w));
+	map(0xe4002, 0xe4003).mirror(0x3ffc).portr("DSW");
+	map(0xe8010, 0xe8017).w(FUNC(bionicc_state::scroll_w));
+	map(0xe8018, 0xe8019).nopw(); // vblank irq ack?
+	map(0xe801a, 0xe801b).w(FUNC(bionicc_state::dmaon_w));
+	map(0xec000, 0xecfff).mirror(0x3000).ram().w(FUNC(bionicc_state::txvideoram_w)).share("txvideoram");
+	map(0xf0000, 0xf3fff).ram().w(FUNC(bionicc_state::fgvideoram_w)).share("fgvideoram");
+	map(0xf4000, 0xf7fff).ram().w(FUNC(bionicc_state::bgvideoram_w)).share("bgvideoram");
+	map(0xf8000, 0xf87ff).ram().w(m_palette, FUNC(palette_device::write16)).share("palette");
+	map(0xfc000, 0xfffff).ram(); // WRAM
+}
+
+void bionicc_state::sound_map(address_map &map)
+{
+	map(0x0000, 0x7fff).rom();
+	map(0x8000, 0x8001).rw("ymsnd", FUNC(ym2151_device::read), FUNC(ym2151_device::write));
+	map(0xa000, 0xa000).lrw8(NAME([this]() { return m_mcu_to_audiocpu; }), NAME([this](u8 data) { m_audiocpu_to_mcu = data; }));
+	map(0xc000, 0xc7ff).ram();
+}
+
+void bionicc_state::mcu_io(address_map &map)
+{
+	map.global_mask(0x7ff);
+	map(0x000, 0x7ff).rw(FUNC(bionicc_state::mcu_dma_r), FUNC(bionicc_state::mcu_dma_w));
+}
+
+
+//**************************************************************************
+//  INPUT PORT DEFINITIONS
+//**************************************************************************
+
+static INPUT_PORTS_START( bionicc )
+	PORT_START("INPUTS")
+	PORT_BIT(0x0001, IP_ACTIVE_LOW, IPT_BUTTON2)        PORT_COCKTAIL
+	PORT_BIT(0x0002, IP_ACTIVE_LOW, IPT_BUTTON1)        PORT_COCKTAIL
+	PORT_BIT(0x0004, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT) PORT_COCKTAIL PORT_8WAY
+	PORT_BIT(0x0008, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT)  PORT_COCKTAIL PORT_8WAY
+	PORT_BIT(0x0010, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN)  PORT_COCKTAIL PORT_8WAY
+	PORT_BIT(0x0020, IP_ACTIVE_LOW, IPT_JOYSTICK_UP)    PORT_COCKTAIL PORT_8WAY
+	PORT_BIT(0x0040, IP_ACTIVE_LOW, IPT_BUTTON2)
+	PORT_BIT(0x0080, IP_ACTIVE_LOW, IPT_BUTTON1)
+	PORT_BIT(0x0100, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT) PORT_8WAY
+	PORT_BIT(0x0200, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT)  PORT_8WAY
+	PORT_BIT(0x0400, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN)  PORT_8WAY
+	PORT_BIT(0x0800, IP_ACTIVE_LOW, IPT_JOYSTICK_UP)    PORT_8WAY
+	PORT_BIT(0x1000, IP_ACTIVE_LOW, IPT_START2)
+	PORT_BIT(0x2000, IP_ACTIVE_LOW, IPT_START1)
+	PORT_BIT(0x4000, IP_ACTIVE_LOW, IPT_COIN2)
+	PORT_BIT(0x8000, IP_ACTIVE_LOW, IPT_COIN1)
+
+	PORT_START("DSW")
+	PORT_DIPNAME( 0x0007, 0x0007, DEF_STR( Coin_A ) )       PORT_DIPLOCATION("SWB:1,2,3")
+	PORT_DIPSETTING(      0x0000, DEF_STR( 4C_1C ) )
+	PORT_DIPSETTING(      0x0001, DEF_STR( 3C_1C ) )
+	PORT_DIPSETTING(      0x0002, DEF_STR( 2C_1C ) )
+	PORT_DIPSETTING(      0x0007, DEF_STR( 1C_1C ) )
+	PORT_DIPSETTING(      0x0006, DEF_STR( 1C_2C ) )
+	PORT_DIPSETTING(      0x0005, DEF_STR( 1C_3C ) )
+	PORT_DIPSETTING(      0x0004, DEF_STR( 1C_4C ) )
+	PORT_DIPSETTING(      0x0003, DEF_STR( 1C_6C ) )
+	PORT_DIPNAME( 0x0038, 0x0038, DEF_STR( Coin_B ) )       PORT_DIPLOCATION("SWB:4,5,6")
+	PORT_DIPSETTING(      0x0000, DEF_STR( 4C_1C ) )
+	PORT_DIPSETTING(      0x0008, DEF_STR( 3C_1C ) )
+	PORT_DIPSETTING(      0x0010, DEF_STR( 2C_1C ) )
+	PORT_DIPSETTING(      0x0038, DEF_STR( 1C_1C ) )
+	PORT_DIPSETTING(      0x0030, DEF_STR( 1C_2C ) )
+	PORT_DIPSETTING(      0x0028, DEF_STR( 1C_3C ) )
+	PORT_DIPSETTING(      0x0020, DEF_STR( 1C_4C ) )
+	PORT_DIPSETTING(      0x0018, DEF_STR( 1C_6C ) )
+	PORT_SERVICE_DIPLOC(  0x0040, IP_ACTIVE_LOW, "SWB:7" )
+	PORT_DIPNAME( 0x0080, 0x0080, DEF_STR( Flip_Screen ) )  PORT_DIPLOCATION("SWB:8")
+	PORT_DIPSETTING(      0x0080, DEF_STR( Off ) )
+	PORT_DIPSETTING(      0x0000, DEF_STR( On ) )
+	PORT_DIPNAME( 0x0300, 0x0300, DEF_STR( Lives ) )        PORT_DIPLOCATION("SWA:1,2")
+	PORT_DIPSETTING(      0x0300, "3" )
+	PORT_DIPSETTING(      0x0200, "4" )
+	PORT_DIPSETTING(      0x0100, "5" )
+	PORT_DIPSETTING(      0x0000, "7" )
+	PORT_DIPNAME( 0x0400, 0x0400, DEF_STR( Cabinet ) )      PORT_DIPLOCATION("SWA:3")
+	PORT_DIPSETTING(      0x0400, DEF_STR( Upright ) )
+	PORT_DIPSETTING(      0x0000, DEF_STR( Cocktail ) )
+	PORT_DIPNAME( 0x1800, 0x1800, DEF_STR( Bonus_Life ) )   PORT_DIPLOCATION("SWA:4,5")   /* table at 0x00483a */
+	PORT_DIPSETTING(      0x1800, "20k 40k 100k 60k+" )
+	PORT_DIPSETTING(      0x1000, "30k 50k 120k 70k+" )
+	PORT_DIPSETTING(      0x0800, "20k 60k")
+	PORT_DIPSETTING(      0x0000, "30k 70k" )
+	PORT_DIPNAME( 0x6000, 0x4000, DEF_STR( Difficulty ) )   PORT_DIPLOCATION("SWA:6,7")
+	PORT_DIPSETTING(      0x4000, DEF_STR( Easy ) )
+	PORT_DIPSETTING(      0x6000, DEF_STR( Medium ) )
+	PORT_DIPSETTING(      0x2000, DEF_STR( Hard ) )
+	PORT_DIPSETTING(      0x0000, DEF_STR( Hardest ) )
+	PORT_DIPNAME( 0x8000, 0x8000, "Freeze" )                PORT_DIPLOCATION("SWA:8")     /* Listed as "Unused" */
+	PORT_DIPSETTING(      0x8000, DEF_STR( Off ) )
+	PORT_DIPSETTING(      0x0000, DEF_STR( On ) )
+INPUT_PORTS_END
+
+
+//**************************************************************************
+//  PALETTE
+//**************************************************************************
+
+rgb_t bionicc_state::RRRRGGGGBBBBIIII(uint32_t raw)
+{
+	uint8_t bright = (raw & 0x0f);
+
+	uint8_t r = ((raw >> 12) & 0x0f) * 0x11;
+	uint8_t g = ((raw >>  8) & 0x0f) * 0x11;
+	uint8_t b = ((raw >>  4) & 0x0f) * 0x11;
+
+	if ((bright & 0x08) == 0)
+	{
+		r = r * (0x07 + bright) / 0x0e;
+		g = g * (0x07 + bright) / 0x0e;
+		b = b * (0x07 + bright) / 0x0e;
+	}
+
+	return rgb_t(r, g, b);
+}
+
+
+//**************************************************************************
+//  VIDEO EMULATION
+//**************************************************************************
+
+/*
+
+    This board handles tile/tile and tile/sprite priority with a PROM. Its
+    working is complicated and hardcoded in the driver.
+
+    The PROM is a 256x4 chip, with address inputs wired as follows:
+
+    A0 bg opaque
+    A1 \
+    A2 |  fg pen
+    A3 |
+    A4 /
+    A5 fg has priority over sprites (bit 5 of tile attribute)
+    A6 fg has not priority over bg (bits 6 & 7 of tile attribute both set)
+    A7 sprite opaque
+
+    The output selects the active layer, it can be:
+    0  bg
+    1  fg
+    2  sprite
+
+*/
+
+void bionicc_state::bgvideoram_w(offs_t offset, u16 data, u16 mem_mask)
+{
+	COMBINE_DATA(&m_bgvideoram[offset]);
+	m_bg_tilemap->mark_tile_dirty(offset / 2);
+}
+
+void bionicc_state::fgvideoram_w(offs_t offset, u16 data, u16 mem_mask)
+{
+	COMBINE_DATA(&m_fgvideoram[offset]);
+	m_fg_tilemap->mark_tile_dirty(offset / 2);
+}
+
+void bionicc_state::txvideoram_w(offs_t offset, u16 data, u16 mem_mask)
+{
+	COMBINE_DATA(&m_txvideoram[offset]);
+	m_tx_tilemap->mark_tile_dirty(offset & 0x3ff);
+}
+
+void bionicc_state::scroll_w(offs_t offset, u16 data, u16 mem_mask)
+{
+	data = COMBINE_DATA(&m_scroll[offset]);
+
+	switch (offset)
+	{
+		case 0:
+			m_fg_tilemap->set_scrollx(0, data);
+			break;
+		case 1:
+			m_fg_tilemap->set_scrolly(0, data);
+			break;
+		case 2:
+			m_bg_tilemap->set_scrollx(0, data);
+			break;
+		case 3:
+			m_bg_tilemap->set_scrolly(0, data);
+			break;
+	}
+}
+
+u32 bionicc_state::screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect)
+{
+	bitmap.fill(m_palette->black_pen(), cliprect);
+
+	m_fg_tilemap->draw(screen, bitmap, cliprect, 1 | TILEMAP_DRAW_LAYER1, 0);   /* nothing in FRONT */
+	m_bg_tilemap->draw(screen, bitmap, cliprect, 0, 0);
+	m_fg_tilemap->draw(screen, bitmap, cliprect, 0 | TILEMAP_DRAW_LAYER1, 0);
+	m_spritegen->draw_sprites(bitmap, cliprect, m_spriteram->buffer(), m_spriteram->bytes(), flip_screen(), false);
+	m_fg_tilemap->draw(screen, bitmap, cliprect, 0 | TILEMAP_DRAW_LAYER0, 0);
+
+	// text layer last
+	m_tx_tilemap->draw(screen, bitmap, cliprect, 0, 0);
+
+	return 0;
+}
+
+void bionicc_state::video_start()
+{
+	m_tx_tilemap = &machine().tilemap().create(*m_gfxdecode, tilemap_get_info_delegate(*this, FUNC(bionicc_state::get_tx_tile_info)), TILEMAP_SCAN_ROWS,  8,  8, 32, 32);
+	m_fg_tilemap = &machine().tilemap().create(*m_gfxdecode, tilemap_get_info_delegate(*this, FUNC(bionicc_state::get_fg_tile_info)), TILEMAP_SCAN_ROWS, 16, 16, 64, 64);
+	m_bg_tilemap = &machine().tilemap().create(*m_gfxdecode, tilemap_get_info_delegate(*this, FUNC(bionicc_state::get_bg_tile_info)), TILEMAP_SCAN_ROWS,  8,  8, 64, 64);
+
+	m_tx_tilemap->set_transparent_pen(3);
+	m_fg_tilemap->set_transmask(0, 0xffff, 0x8000); /* split type 0 is completely transparent in front half */
+	m_fg_tilemap->set_transmask(1, 0xffc1, 0x803e); /* split type 1 has pens 1-5 opaque in front half */
+	m_bg_tilemap->set_transparent_pen(15);
+
+	m_tx_tilemap->set_scrolldx(128, 128);
+	m_tx_tilemap->set_scrolldy(  6,   6);
+	m_bg_tilemap->set_scrolldx(128, 128);
+	m_bg_tilemap->set_scrolldy(  6,   6);
+	m_fg_tilemap->set_scrolldx(128, 128);
+	m_fg_tilemap->set_scrolldy(  6,   6);
+}
+
+
+//**************************************************************************
+//  DRAWGFX LAYOUTS
+//**************************************************************************
+
+static const gfx_layout vramlayout=
+{
+	8,8,    /* 8*8 characters */
+	RGN_FRAC(1,1),   /* 1024 character */
+	2,      /* 2 bitplanes */
+	{ 4,0 },
+	{ STEP4(0,1), STEP4(4*2,1) },
+	{ STEP8(0,4*2*2) },
+	128   /* every character takes 128 consecutive bytes */
+};
+
+static const gfx_layout scroll2layout=
+{
+	8,8,    /* 8*8 tiles */
+	RGN_FRAC(1,2),   /* 2048 tiles */
+	4,      /* 4 bits per pixel */
+	{ RGN_FRAC(1,2)+4,RGN_FRAC(1,2),4,0 },
+	{ STEP4(0,1), STEP4(4*2,1) },
+	{ STEP8(0,4*2*2) },
+	128   /* every tile takes 128 consecutive bytes */
+};
+
+static const gfx_layout scroll1layout=
+{
+	16,16,  /* 16*16 tiles */
+	RGN_FRAC(1,2),   /* 2048 tiles */
+	4,      /* 4 bits per pixel */
+	{ RGN_FRAC(1,2)+4,RGN_FRAC(1,2),4,0 },
+	{ STEP4(0,1), STEP4(4*2,1), STEP4(4*2*2*16,1), STEP4(4*2*2*16+4*2,1) },
+	{ STEP16(0,4*2*2) },
+	512   /* each tile takes 512 consecutive bytes */
+};
+
+static GFXDECODE_START( gfx_bionicc )
+	GFXDECODE_ENTRY( "gfx1", 0, vramlayout,    768, 64 )    /* colors 768-1023 */
+	GFXDECODE_ENTRY( "gfx2", 0, scroll2layout,   0,  8 )    /* colors   0- 127 */
+	GFXDECODE_ENTRY( "gfx3", 0, scroll1layout, 256,  4 )    /* colors 256- 319 */
+GFXDECODE_END
+
+TILE_GET_INFO_MEMBER(bionicc_state::get_tx_tile_info)
+{
+	// 76------  tile code high bits
+	// --543210  color
+
+	int attr = m_txvideoram[tile_index + 0x400];
+	int code = m_txvideoram[tile_index] & 0xff;
+
+	tileinfo.set(0, ((attr & 0xc0) << 2) | code, attr & 0x3f, 0);
+}
+
+TILE_GET_INFO_MEMBER(bionicc_state::get_fg_tile_info)
+{
+	// 7-------  tile flip x
+	// -6------  tile flip y
+	// --5-----  layer
+	// ---43---  color
+	// -----210  tile code high bits
+
+	int attr = m_fgvideoram[2 * tile_index + 1];
+	int code = m_fgvideoram[2 * tile_index] & 0xff;
+	int flag = 0;
+
+	if ((attr & 0xc0) == 0xc0)
+	{
+		// drawn to the background if both flip bits are set
+		tileinfo.category = 1;
+		tileinfo.group = 0;
+	}
+	else
+	{
+		tileinfo.category = 0;
+		tileinfo.group = (attr & 0x20) >> 5;
+		flag = TILE_FLIPXY((attr & 0xc0) >> 6);
+	}
+
+	tileinfo.set(2, ((attr & 0x07) << 8) | code, (attr & 0x18) >> 3, flag);
+}
+
+TILE_GET_INFO_MEMBER(bionicc_state::get_bg_tile_info)
+{
+	// 7-------  tile flip x
+	// -6------  tile flip y
+	// --543---  color
+	// -----210  tile code high bits
+
+	int attr = m_bgvideoram[2 * tile_index + 1];
+	int code = m_bgvideoram[2 * tile_index] & 0xff;
+	int flag = TILE_FLIPXY((attr & 0xc0) >> 6);
+
+	tileinfo.set(1, ((attr & 0x07) << 8) | code, (attr & 0x38) >> 3, flag);
+}
+
+
+//**************************************************************************
+//  PROTECTION MCU
+//**************************************************************************
+
+u8 bionicc_state::mcu_dma_r(offs_t offset)
+{
+	u8 data = 0xff;
+
+	if (BIT(m_mcu_p3, 5) == 0)
+	{
+		// various address bits are pulled high because the mcu doesn't drive them
+		// the 3 upper address bits (p2.0, p2.1, p2.2) are connected to a14 to a16
+		offs_t address = 0xe3e01 | ((offset & 0x700) << 6) | ((offset & 0xff) << 1);
+		data = m_maincpu->space(AS_PROGRAM).read_byte(address);
+	}
+
+	return data;
+}
+
+void bionicc_state::mcu_dma_w(offs_t offset, u8 data)
+{
+	if (BIT(m_mcu_p3, 5) == 0)
+	{
+		offs_t address = 0xe3e01 | ((offset & 0x700) << 6) | ((offset & 0xff) << 1);
+		m_maincpu->space(AS_PROGRAM).write_byte(address, data);
+	}
+}
+
+void bionicc_state::mcu_p3_w(u8 data)
+{
+	// 7-------  read strobe
+	// -6------  write strobe
+	// --5-----  dma
+	// ---4----  int1 ack
+	// ----3---  int1
+	// -----2--  int0
+	// ------1-  int0 flip-flop preset
+	// -------0  int0 ack
+
+	if (BIT(m_mcu_p3, 0) == 1 && BIT(data, 0) == 0)
+	{
+		m_mcu->set_input_line(MCS51_INT0_LINE, CLEAR_LINE);
+		m_maincpu->resume(SUSPEND_REASON_HALT);
+	}
+
+	if (BIT(m_mcu_p3, 4) == 1 && BIT(data, 4) == 0)
+		m_mcu->set_input_line(MCS51_INT1_LINE, CLEAR_LINE);
+
+	if (BIT(m_mcu_p3, 6) == 1 && BIT(data, 6) == 0)
+		m_mcu_to_audiocpu = m_mcu_p1;
+
+	m_mcu_p3 = data;
+}
+
+void bionicc_state::dmaon_w(u16 data)
+{
+	m_mcu->set_input_line(MCS51_INT0_LINE, ASSERT_LINE);
+	m_maincpu->suspend(SUSPEND_REASON_HALT, true);
+}
+
+
+//**************************************************************************
+//  AUDIO
+//**************************************************************************
+
+void bionicc_state::audiocpu_nmi_w(u8 data)
+{
+	m_audiocpu->pulse_input_line(INPUT_LINE_NMI, attotime::zero);
+}
+
+
+//**************************************************************************
+//  MACHINE EMULATION
+//**************************************************************************
+
+void bionicc_state::output_w(u8 data)
+{
+	// 7-------  coin counter 1
+	// -6------  coin counter 2
+	// --5-----  coin lockout 1
+	// ---4----  coin lockout 2
+	// ----321-  unused
+	// -------0  flip screen
+
+	flip_screen_set(BIT(data, 0));
+
+	// commented out, else you can't test the coin inputs in service mode
+//  machine().bookkeeping().coin_lockout_w(1, BIT(~data, 4));
+//  machine().bookkeeping().coin_lockout_w(0, BIT(~data, 5));
+	machine().bookkeeping().coin_counter_w(1, BIT(data, 6));
+	machine().bookkeeping().coin_counter_w(0, BIT(data, 7));
+}
+
+TIMER_DEVICE_CALLBACK_MEMBER(bionicc_state::scanline)
+{
+	// vblank-out irq - drives the game (V256)
+	if (param == 256)
+		m_maincpu->set_input_line(2, HOLD_LINE);
+
+	// vblank-in irq - processes inputs (!LVBL)
+	// should be 16? but then often loses coin inserts
+	if (param == 128)
+		m_maincpu->set_input_line(4, HOLD_LINE);
+}
+
+void bionicc_state::machine_start()
+{
+	save_item(NAME(m_scroll));
+	save_item(NAME(m_audiocpu_to_mcu));
+	save_item(NAME(m_mcu_to_audiocpu));
+	save_item(NAME(m_mcu_p1));
+	save_item(NAME(m_mcu_p3));
+}
+
+void bionicc_state::machine_reset()
+{
+	m_scroll[0] = 0;
+	m_scroll[1] = 0;
+	m_scroll[2] = 0;
+	m_scroll[3] = 0;
+}
+
+
+//**************************************************************************
+//  MACHINE DEFINITIONS
+//**************************************************************************
+
+void bionicc_state::bionicc(machine_config &config)
+{
+	// Main CPU 68000CP10 @ 12 MHz
+	M68000(config, m_maincpu, 24_MHz_XTAL / 2);
+	m_maincpu->set_addrmap(AS_PROGRAM, &bionicc_state::main_map);
+
+	TIMER(config, "scantimer").configure_scanline(FUNC(bionicc_state::scanline), "screen", 0, 1);
+
+	// Audio CPU Z80 @ 3.579545 MHz (EXO3 C,B=GND, A=5V ==> Divisor 2^2)
+	Z80(config, m_audiocpu, 14.318181_MHz_XTAL / 4);
+	m_audiocpu->set_addrmap(AS_PROGRAM, &bionicc_state::sound_map);
+
+	// Protection MCU Intel C8751H-88 @ 6 MHz
+	I8751(config, m_mcu, 24_MHz_XTAL / 4);
+	m_mcu->set_addrmap(AS_IO, &bionicc_state::mcu_io);
+	m_mcu->port_in_cb<1>().set([this](){ return m_audiocpu_to_mcu; });
+	m_mcu->port_out_cb<1>().set([this](u8 data){ m_mcu_p1 = data; });
+	m_mcu->port_out_cb<3>().set(FUNC(bionicc_state::mcu_p3_w));
+
+	// video hardware
+	screen_device &screen(SCREEN(config, "screen", SCREEN_TYPE_RASTER));
+	screen.set_raw(24_MHz_XTAL / 4, 384, 128, 0, 262, 22, 246); // hsync is 50..77, vsync is 257..259
+	screen.set_screen_update(FUNC(bionicc_state::screen_update));
+	screen.screen_vblank().set(m_spriteram, FUNC(buffered_spriteram16_device::vblank_copy_rising));
+	screen.set_palette(m_palette);
+
+	GFXDECODE(config, m_gfxdecode, m_palette, gfx_bionicc);
+
+	TIGEROAD_SPRITE(config, m_spritegen, 0);
+	m_spritegen->set_palette(m_palette);
+	m_spritegen->set_color_base(512);    /* colors 512- 767 */
+
+	PALETTE(config, m_palette).set_format(2, &bionicc_state::RRRRGGGGBBBBIIII, 1024);
+
+	BUFFERED_SPRITERAM16(config, m_spriteram);
+
+	SPEAKER(config, "mono").front_center();
+
+	YM2151(config, "ymsnd", 14.318181_MHz_XTAL / 4).add_route(0, "mono", 0.60).add_route(1, "mono", 0.60);
+}
+
+
+//**************************************************************************
+//  ROM DEFINITIONS
+//**************************************************************************
+
+ROM_START( bionicc ) /* "Not for use in Japan" */
+	ROM_REGION( 0x40000, "maincpu", 0 )      /* 68000 code */
+	ROM_LOAD16_BYTE( "tse_02.1a",  0x00000, 0x10000, CRC(e4aeefaa) SHA1(77b6a2d4337bf350239abb50013d030d7c5c8640) ) /* 68000 code */
+	ROM_LOAD16_BYTE( "tse_04.1b",  0x00001, 0x10000, CRC(d0c8ec75) SHA1(04138c75ca3939604100b7e9fb451f7fceee67ca) ) /* 68000 code */
+	ROM_LOAD16_BYTE( "tse_03.2a",  0x20000, 0x10000, CRC(b2ac0a45) SHA1(d0933e74870efa9ea703251b30a56ef706ac24fe) ) /* 68000 code */
+	ROM_LOAD16_BYTE( "tse_05.2b",  0x20001, 0x10000, CRC(a79cb406) SHA1(50eada2f3e80c28dcb5529890d9b279c73f0115a) ) /* 68000 code */
+
+	ROM_REGION( 0x10000, "audiocpu", 0 )
+	ROM_LOAD( "ts_01b.4e",  0x00000, 0x8000, CRC(a9a6cafa) SHA1(55e0a0e6ca11e8e73339d5b4604e130031211291) )
+
+	ROM_REGION( 0x1000, "mcu", 0 )  /* i8751 microcontroller */
+	ROM_LOAD( "ts.2f",     0x0000, 0x1000, CRC(3ed7f0be) SHA1(db9e972065c8e60b5d74762dc3424271ea9524cb) )  /* from 'topsecrt' bootleg, but appears to be original */
+
+	ROM_REGION( 0x08000, "gfx1", 0 )
+	ROM_LOAD( "tsu_08.8l",   0x00000, 0x8000, CRC(9bf0b7a2) SHA1(1361335c3c2c8a9c6a7d99566048d8aac99e7c8f) )    /* VIDEORAM (text layer) tiles */
+
+	ROM_REGION( 0x10000, "gfx2", 0 )
+	ROM_LOAD( "tsu_07.5l",   0x00000, 0x8000, CRC(9469efa4) SHA1(53c70361e8d9e54825f61b87a10df42438aaf5b0) )    /* SCROLL2 Layer Tiles */
+	ROM_LOAD( "tsu_06.4l",   0x08000, 0x8000, CRC(40bf0eb4) SHA1(fcb186c31747e2c9872de01e34b3e713dc74df82) )
+
+	ROM_REGION( 0x40000, "gfx3", 0 )
+	ROM_LOAD( "ts_12.17f",    0x00000, 0x8000, CRC(e4b4619e) SHA1(3bec8399ffb28fd50ce6ae88d90b091eadf8bda1) )   /* SCROLL1 Layer Tiles */
+	ROM_LOAD( "ts_11.15f",    0x08000, 0x8000, CRC(ab30237a) SHA1(ea6c07df992ba48f9eca7daa4ea775faa94358d2) )
+	ROM_LOAD( "ts_17.17g",    0x10000, 0x8000, CRC(deb657e4) SHA1(b36b468f9bbb7a4937286230d3f6caa14c61d4dd) )
+	ROM_LOAD( "ts_16.15g",    0x18000, 0x8000, CRC(d363b5f9) SHA1(1dd3991d99db2d6bcbdb12879ba50a01fef95004) )
+	ROM_LOAD( "ts_13.18f",    0x20000, 0x8000, CRC(a8f5a004) SHA1(36ab0cb8ec9ce0519876f7461ccc5020c9c5b597) )
+	ROM_LOAD( "ts_18.18g",    0x28000, 0x8000, CRC(3b36948c) SHA1(d85fcc0265ba1729c587b046cc5a7ba6f25363dd) )
+	ROM_LOAD( "ts_23.18j",    0x30000, 0x8000, CRC(bbfbe58a) SHA1(9b1d5672b6f3c5c0952f8dcd0da71acc68a97a5e) )
+	ROM_LOAD( "ts_24.18k",    0x38000, 0x8000, CRC(f156e564) SHA1(a6cad05bcc6d9ded6294f9b5aa856d05641aed02) )
+
+	ROM_REGION( 0x40000, "spritegen", 0 )
+	ROM_LOAD32_BYTE( "tse_10.13f",   0x00003, 0x8000, CRC(d28eeacc) SHA1(8b4a655a48da276b07f3464c65743b13cec52bcb) )   /* Sprites */
+	ROM_LOAD32_BYTE( "tsu_09.11f",   0x20003, 0x8000, CRC(6a049292) SHA1(525c862061f426d679b539b6926af4c9f14b47b5) )
+	ROM_LOAD32_BYTE( "tse_15.13g",   0x00002, 0x8000, CRC(9b5593c0) SHA1(73c0acbb01fe69c2bd29dea11b6a223c8efb54a0) )
+	ROM_LOAD32_BYTE( "tsu_14.11g",   0x20002, 0x8000, CRC(46b2ad83) SHA1(21ebd5691a544323fdfcf330b9a37bbe0428e3e3) )
+	ROM_LOAD32_BYTE( "tse_20.13j",   0x00001, 0x8000, CRC(b03db778) SHA1(f72a93e73196c800c1893fd3b523394d702547dd) )
+	ROM_LOAD32_BYTE( "tsu_19.11j",   0x20001, 0x8000, CRC(b5c82722) SHA1(969f9159f7d59e4e4c9ef9ddbdc27cbfa531eabf) )
+	ROM_LOAD32_BYTE( "tse_22.17j",   0x00000, 0x8000, CRC(d4dedeb3) SHA1(e121057bb541f3f5c755963ca22832c3fe2637c0) )
+	ROM_LOAD32_BYTE( "tsu_21.15j",   0x20000, 0x8000, CRC(98777006) SHA1(bcc2058b639e9b71d16af05f63df298bcce91fdc) )
+
+	ROM_REGION( 0x0100, "proms", 0 )
+	ROM_LOAD( "63s141.18f",   0x0000, 0x0100, CRC(b58d0023) SHA1(e8a4a2e2951bf73b3d9eed6957e9ee1e61c9c58a) )    /* priority (not used), Labeled "TSB" */
+ROM_END
+
+ROM_START( bionicc1 ) /* "Not for use outside of USA or Canada" revision B */
+	ROM_REGION( 0x40000, "maincpu", 0 )      /* 68000 code */
+	ROM_LOAD16_BYTE( "tsu_02b.1a",  0x00000, 0x10000, CRC(cf965a0a) SHA1(ab88742a3225a0b82ee2dfef6ed0058d3e11c38c) ) /* 68000 code */
+	ROM_LOAD16_BYTE( "tsu_04b.1b",  0x00001, 0x10000, CRC(c9884bfb) SHA1(7d10cedff0a62847f8deb61a9611cc6661efb037) ) /* 68000 code */
+	ROM_LOAD16_BYTE( "tsu_03b.2a",  0x20000, 0x10000, CRC(4e157ae2) SHA1(cc02931376d22a7fcfc320e6fd4129e03a461a49) ) /* 68000 code */
+	ROM_LOAD16_BYTE( "tsu_05b.2b",  0x20001, 0x10000, CRC(e66ca0f9) SHA1(a503badf2fed38786d38c313d1dc315f3175d6de) ) /* 68000 code */
+
+	ROM_REGION( 0x10000, "audiocpu", 0 )
+	ROM_LOAD( "ts_01b.4e",  0x00000, 0x8000, CRC(a9a6cafa) SHA1(55e0a0e6ca11e8e73339d5b4604e130031211291) )
+
+	ROM_REGION( 0x1000, "mcu", 0 )  /* i8751 microcontroller */
+	ROM_LOAD( "ts.2f",     0x0000, 0x1000, CRC(3ed7f0be) SHA1(db9e972065c8e60b5d74762dc3424271ea9524cb) )  /* from 'topsecrt' bootleg, but appears to be original */
+
+	ROM_REGION( 0x08000, "gfx1", 0 )
+	ROM_LOAD( "tsu_08.8l",   0x00000, 0x8000, CRC(9bf0b7a2) SHA1(1361335c3c2c8a9c6a7d99566048d8aac99e7c8f) )    /* VIDEORAM (text layer) tiles */
+
+	ROM_REGION( 0x10000, "gfx2", 0 )
+	ROM_LOAD( "tsu_07.5l",   0x00000, 0x8000, CRC(9469efa4) SHA1(53c70361e8d9e54825f61b87a10df42438aaf5b0) )    /* SCROLL2 Layer Tiles */
+	ROM_LOAD( "tsu_06.4l",   0x08000, 0x8000, CRC(40bf0eb4) SHA1(fcb186c31747e2c9872de01e34b3e713dc74df82) )
+
+	ROM_REGION( 0x40000, "gfx3", 0 )
+	ROM_LOAD( "ts_12.17f",    0x00000, 0x8000, CRC(e4b4619e) SHA1(3bec8399ffb28fd50ce6ae88d90b091eadf8bda1) )   /* SCROLL1 Layer Tiles */
+	ROM_LOAD( "ts_11.15f",    0x08000, 0x8000, CRC(ab30237a) SHA1(ea6c07df992ba48f9eca7daa4ea775faa94358d2) )
+	ROM_LOAD( "ts_17.17g",    0x10000, 0x8000, CRC(deb657e4) SHA1(b36b468f9bbb7a4937286230d3f6caa14c61d4dd) )
+	ROM_LOAD( "ts_16.15g",    0x18000, 0x8000, CRC(d363b5f9) SHA1(1dd3991d99db2d6bcbdb12879ba50a01fef95004) )
+	ROM_LOAD( "ts_13.18f",    0x20000, 0x8000, CRC(a8f5a004) SHA1(36ab0cb8ec9ce0519876f7461ccc5020c9c5b597) )
+	ROM_LOAD( "ts_18.18g",    0x28000, 0x8000, CRC(3b36948c) SHA1(d85fcc0265ba1729c587b046cc5a7ba6f25363dd) )
+	ROM_LOAD( "ts_23.18j",    0x30000, 0x8000, CRC(bbfbe58a) SHA1(9b1d5672b6f3c5c0952f8dcd0da71acc68a97a5e) )
+	ROM_LOAD( "ts_24.18k",    0x38000, 0x8000, CRC(f156e564) SHA1(a6cad05bcc6d9ded6294f9b5aa856d05641aed02) )
+
+	ROM_REGION( 0x40000, "spritegen", 0 )
+	ROM_LOAD32_BYTE( "tsu_10.13f",   0x00003, 0x8000, CRC(f1180d02) SHA1(312626af48235a1f726ab596f296ef4739785ca0) )   /* Sprites */
+	ROM_LOAD32_BYTE( "tsu_09.11f",   0x20003, 0x8000, CRC(6a049292) SHA1(525c862061f426d679b539b6926af4c9f14b47b5) )
+	ROM_LOAD32_BYTE( "tsu_15.13g",   0x00002, 0x8000, CRC(ea912701) SHA1(106336c63a1c8a0b13236268bc533a8263285cad) )
+	ROM_LOAD32_BYTE( "tsu_14.11g",   0x20002, 0x8000, CRC(46b2ad83) SHA1(21ebd5691a544323fdfcf330b9a37bbe0428e3e3) )
+	ROM_LOAD32_BYTE( "tsu_20.13j",   0x00001, 0x8000, CRC(17857ad2) SHA1(9f45cea6e9ce82bfc9ee6896a30257d20fb38bca) )
+	ROM_LOAD32_BYTE( "tsu_19.11j",   0x20001, 0x8000, CRC(b5c82722) SHA1(969f9159f7d59e4e4c9ef9ddbdc27cbfa531eabf) )
+	ROM_LOAD32_BYTE( "tsu_22.17j",   0x00000, 0x8000, CRC(5ee1ae6a) SHA1(76ca53d847c940c4176d79ba49b0c10efd6342e8) )
+	ROM_LOAD32_BYTE( "tsu_21.15j",   0x20000, 0x8000, CRC(98777006) SHA1(bcc2058b639e9b71d16af05f63df298bcce91fdc) )
+
+	ROM_REGION( 0x0100, "proms", 0 )
+	ROM_LOAD( "63s141.18f",   0x0000, 0x0100, CRC(b58d0023) SHA1(e8a4a2e2951bf73b3d9eed6957e9ee1e61c9c58a) )    /* priority (not used), Labeled "TSB" */
+ROM_END
+
+ROM_START( bionicc2 ) /* "Not for use outside of USA or Canada" 1st release */
+	ROM_REGION( 0x40000, "maincpu", 0 )      /* 68000 code */
+	ROM_LOAD16_BYTE( "tsu_02.1a",  0x00000, 0x10000, CRC(f2528f08) SHA1(04c793837c86d83312fd44b46a6a94378c90113b) ) /* 68000 code */
+	ROM_LOAD16_BYTE( "tsu_04.1b",  0x00001, 0x10000, CRC(38b1c7e4) SHA1(14bf743726c214bd00177e7b410c272dd7ab3d3f) ) /* 68000 code */
+	ROM_LOAD16_BYTE( "tsu_03.2a",  0x20000, 0x10000, CRC(72c3b76f) SHA1(f7f71eae7617e3348b727775088b496e86d51e38) ) /* 68000 code */
+	ROM_LOAD16_BYTE( "tsu_05.2b",  0x20001, 0x10000, CRC(70621f83) SHA1(0a77c2827a5c50457d90ccc62e463508d83d2f20) ) /* 68000 code */
+
+	ROM_REGION( 0x10000, "audiocpu", 0 )
+	ROM_LOAD( "ts_01b.4e",  0x00000, 0x8000, CRC(a9a6cafa) SHA1(55e0a0e6ca11e8e73339d5b4604e130031211291) )
+
+	ROM_REGION( 0x1000, "mcu", 0 )  /* i8751 microcontroller */
+	ROM_LOAD( "ts.2f",     0x0000, 0x1000, CRC(3ed7f0be) SHA1(db9e972065c8e60b5d74762dc3424271ea9524cb) )  /* from 'topsecrt' bootleg, but appears to be original */
+
+	ROM_REGION( 0x08000, "gfx1", 0 )
+	ROM_LOAD( "tsu_08.8l",   0x00000, 0x8000, CRC(9bf0b7a2) SHA1(1361335c3c2c8a9c6a7d99566048d8aac99e7c8f) )    /* VIDEORAM (text layer) tiles */
+
+	ROM_REGION( 0x10000, "gfx2", 0 )
+	ROM_LOAD( "tsu_07.5l",   0x00000, 0x8000, CRC(9469efa4) SHA1(53c70361e8d9e54825f61b87a10df42438aaf5b0) )    /* SCROLL2 Layer Tiles */
+	ROM_LOAD( "tsu_06.4l",   0x08000, 0x8000, CRC(40bf0eb4) SHA1(fcb186c31747e2c9872de01e34b3e713dc74df82) )
+
+	ROM_REGION( 0x40000, "gfx3", 0 )
+	ROM_LOAD( "ts_12.17f",    0x00000, 0x8000, CRC(e4b4619e) SHA1(3bec8399ffb28fd50ce6ae88d90b091eadf8bda1) )   /* SCROLL1 Layer Tiles */
+	ROM_LOAD( "ts_11.15f",    0x08000, 0x8000, CRC(ab30237a) SHA1(ea6c07df992ba48f9eca7daa4ea775faa94358d2) )
+	ROM_LOAD( "ts_17.17g",    0x10000, 0x8000, CRC(deb657e4) SHA1(b36b468f9bbb7a4937286230d3f6caa14c61d4dd) )
+	ROM_LOAD( "ts_16.15g",    0x18000, 0x8000, CRC(d363b5f9) SHA1(1dd3991d99db2d6bcbdb12879ba50a01fef95004) )
+	ROM_LOAD( "ts_13.18f",    0x20000, 0x8000, CRC(a8f5a004) SHA1(36ab0cb8ec9ce0519876f7461ccc5020c9c5b597) )
+	ROM_LOAD( "ts_18.18g",    0x28000, 0x8000, CRC(3b36948c) SHA1(d85fcc0265ba1729c587b046cc5a7ba6f25363dd) )
+	ROM_LOAD( "ts_23.18j",    0x30000, 0x8000, CRC(bbfbe58a) SHA1(9b1d5672b6f3c5c0952f8dcd0da71acc68a97a5e) )
+	ROM_LOAD( "ts_24.18k",    0x38000, 0x8000, CRC(f156e564) SHA1(a6cad05bcc6d9ded6294f9b5aa856d05641aed02) )
+
+	ROM_REGION( 0x40000, "spritegen", 0 )
+	ROM_LOAD32_BYTE( "tsu_10.13f",   0x00003, 0x8000, CRC(f1180d02) SHA1(312626af48235a1f726ab596f296ef4739785ca0) )   /* Sprites */
+	ROM_LOAD32_BYTE( "tsu_09.11f",   0x20003, 0x8000, CRC(6a049292) SHA1(525c862061f426d679b539b6926af4c9f14b47b5) )
+	ROM_LOAD32_BYTE( "tsu_15.13g",   0x00002, 0x8000, CRC(ea912701) SHA1(106336c63a1c8a0b13236268bc533a8263285cad) )
+	ROM_LOAD32_BYTE( "tsu_14.11g",   0x20002, 0x8000, CRC(46b2ad83) SHA1(21ebd5691a544323fdfcf330b9a37bbe0428e3e3) )
+	ROM_LOAD32_BYTE( "tsu_20.13j",   0x00001, 0x8000, CRC(17857ad2) SHA1(9f45cea6e9ce82bfc9ee6896a30257d20fb38bca) )
+	ROM_LOAD32_BYTE( "tsu_19.11j",   0x20001, 0x8000, CRC(b5c82722) SHA1(969f9159f7d59e4e4c9ef9ddbdc27cbfa531eabf) )
+	ROM_LOAD32_BYTE( "tsu_22.17j",   0x00000, 0x8000, CRC(5ee1ae6a) SHA1(76ca53d847c940c4176d79ba49b0c10efd6342e8) )
+	ROM_LOAD32_BYTE( "tsu_21.15j",   0x20000, 0x8000, CRC(98777006) SHA1(bcc2058b639e9b71d16af05f63df298bcce91fdc) )
+
+	ROM_REGION( 0x0100, "proms", 0 )
+	ROM_LOAD( "63s141.18f",   0x0000, 0x0100, CRC(b58d0023) SHA1(e8a4a2e2951bf73b3d9eed6957e9ee1e61c9c58a) )    /* priority (not used), Labeled "TSB" */
+ROM_END
+
+ROM_START( topsecrt2 ) /* "Not for use in any other country but Japan" */
+	ROM_REGION( 0x40000, "maincpu", 0 )      /* 68000 code */
+	ROM_LOAD16_BYTE( "ts_02b.1a",  0x00000, 0x10000, CRC(0b84497f) SHA1(f7e9412d37a1e4b7a437d3f7bc5dc448c8a22079) ) /* 68000 code */
+	ROM_LOAD16_BYTE( "ts_04b.1b",  0x00001, 0x10000, CRC(9ab6de8d) SHA1(04445bc183364ebb6a8833a147b694234b509634) ) /* 68000 code */
+	ROM_LOAD16_BYTE( "ts_03b.2a",  0x20000, 0x10000, CRC(1b3f8a82) SHA1(2f9cad83b7bd10617bbd5172a1d31f41b194d3ac) ) /* 68000 code */
+	ROM_LOAD16_BYTE( "ts_05b.2b",  0x20001, 0x10000, CRC(962a89d8) SHA1(4aa5b0fd68a59ff74716253b0ba4c1933e92855b) ) /* 68000 code */
+
+	ROM_REGION( 0x10000, "audiocpu", 0 )
+	ROM_LOAD( "ts_01b.4e",  0x00000, 0x8000, CRC(a9a6cafa) SHA1(55e0a0e6ca11e8e73339d5b4604e130031211291) )
+
+	ROM_REGION( 0x1000, "mcu", 0 )  /* i8751 microcontroller */
+	ROM_LOAD( "ts.2f",     0x0000, 0x1000, CRC(3ed7f0be) SHA1(db9e972065c8e60b5d74762dc3424271ea9524cb) )  /* from 'topsecrt' bootleg, but appears to be original */
+
+	ROM_REGION( 0x08000, "gfx1", 0 )
+	ROM_LOAD( "ts_08.8l",    0x00000, 0x8000, CRC(96ad379e) SHA1(accd3a560b259c186bc28cdc004ed8de0b12f9d5) )    /* VIDEORAM (text layer) tiles */
+
+	ROM_REGION( 0x10000, "gfx2", 0 )
+	ROM_LOAD( "ts_07.5l",    0x00000, 0x8000, CRC(25cdf8b2) SHA1(316f6acc46878682dabeab12722e6a64504d23bd) )    /* SCROLL2 Layer Tiles */
+	ROM_LOAD( "ts_06.4l",    0x08000, 0x8000, CRC(314fb12d) SHA1(dab0519a49b64fe7a837b3c6383f6147e1ab6ffd) )
+
+	ROM_REGION( 0x40000, "gfx3", 0 )
+	ROM_LOAD( "ts_12.17f",    0x00000, 0x8000, CRC(e4b4619e) SHA1(3bec8399ffb28fd50ce6ae88d90b091eadf8bda1) )   /* SCROLL1 Layer Tiles */
+	ROM_LOAD( "ts_11.15f",    0x08000, 0x8000, CRC(ab30237a) SHA1(ea6c07df992ba48f9eca7daa4ea775faa94358d2) )
+	ROM_LOAD( "ts_17.17g",    0x10000, 0x8000, CRC(deb657e4) SHA1(b36b468f9bbb7a4937286230d3f6caa14c61d4dd) )
+	ROM_LOAD( "ts_16.15g",    0x18000, 0x8000, CRC(d363b5f9) SHA1(1dd3991d99db2d6bcbdb12879ba50a01fef95004) )
+	ROM_LOAD( "ts_13.18f",    0x20000, 0x8000, CRC(a8f5a004) SHA1(36ab0cb8ec9ce0519876f7461ccc5020c9c5b597) )
+	ROM_LOAD( "ts_18.18g",    0x28000, 0x8000, CRC(3b36948c) SHA1(d85fcc0265ba1729c587b046cc5a7ba6f25363dd) )
+	ROM_LOAD( "ts_23.18j",    0x30000, 0x8000, CRC(bbfbe58a) SHA1(9b1d5672b6f3c5c0952f8dcd0da71acc68a97a5e) )
+	ROM_LOAD( "ts_24.18k",    0x38000, 0x8000, CRC(f156e564) SHA1(a6cad05bcc6d9ded6294f9b5aa856d05641aed02) )
+
+	ROM_REGION( 0x40000, "spritegen", 0 )
+	ROM_LOAD32_BYTE( "ts_10.13f",    0x00003, 0x8000, CRC(c3587d05) SHA1(ad0898a5d4cf110783ef092bf8e65b6ef31a8ae0) )   /* Sprites */
+	ROM_LOAD32_BYTE( "ts_09.11f",    0x20003, 0x8000, CRC(6b63eef2) SHA1(5d1580db7f49c5994c2a08a36c2d05f3e246930d) )
+	ROM_LOAD32_BYTE( "ts_15.13g",    0x00002, 0x8000, CRC(db8cebb0) SHA1(1cc9eac14851cde95fb2d69d6f5ffb08bc9c0d93) )
+	ROM_LOAD32_BYTE( "ts_14.11g",    0x20002, 0x8000, CRC(e2e41abf) SHA1(d002d0d8fdbb9ec3e2eac218f6338f733953ca82) )
+	ROM_LOAD32_BYTE( "ts_20.13j",    0x00001, 0x8000, CRC(bfd1a695) SHA1(bf93486b96bfa1a1d5015189043b07e6130e6df1) )
+	ROM_LOAD32_BYTE( "ts_19.11j",    0x20001, 0x8000, CRC(928b669e) SHA1(98ea9d23a46b0700490fd2fa7ab4fb0988dd5ca6) )
+	ROM_LOAD32_BYTE( "ts_22.17j",    0x00000, 0x8000, CRC(3fe05d9a) SHA1(32e28ef03fb82785019d1ae8b3859215b5368c2b) )
+	ROM_LOAD32_BYTE( "ts_21.15j",    0x20000, 0x8000, CRC(27a9bb7c) SHA1(bb60332c0ecde4d7797960dec39c1079498175c3) )
+
+	ROM_REGION( 0x0100, "proms", 0 )
+	ROM_LOAD( "63s141.18f",   0x0000, 0x0100, CRC(b58d0023) SHA1(e8a4a2e2951bf73b3d9eed6957e9ee1e61c9c58a) )    /* priority (not used), Labeled "TSB" */
+ROM_END
+
+ROM_START( topsecrt ) /* "Not for use in any other country but Japan" */
+	ROM_REGION( 0x40000, "maincpu", 0 )      /* 68000 code */
+	ROM_LOAD16_BYTE( "ts_02.1a",  0x00000, 0x10000, CRC(b2fe1ddb) SHA1(892f19124993add96edabdba3aafeecc6668c5d9) ) /* 68000 code */
+	ROM_LOAD16_BYTE( "ts_04.1b",  0x00001, 0x10000, CRC(427a003d) SHA1(5a379fe2942e5565810939d5eb843003226222cc) ) /* 68000 code */
+	ROM_LOAD16_BYTE( "ts_03.2a",  0x20000, 0x10000, CRC(27f04bb6) SHA1(41d17b84b34dc8b2e5dfa67794a8df3e898b740b) ) /* 68000 code */
+	ROM_LOAD16_BYTE( "ts_05.2b",  0x20001, 0x10000, CRC(c01547b1) SHA1(563bf6be4f10f5e6eb5b562266accf168f62bf30) ) /* 68000 code */
+
+	ROM_REGION( 0x10000, "audiocpu", 0 )
+	ROM_LOAD( "ts_01.4e",    0x00000, 0x8000, CRC(8ea07917) SHA1(e9ace70d89482fc3669860450a41aacacbee9083) )
+
+	ROM_REGION( 0x1000, "mcu", 0 )  /* i8751 microcontroller */
+	ROM_LOAD( "ts.2f",     0x0000, 0x1000, CRC(3ed7f0be) SHA1(db9e972065c8e60b5d74762dc3424271ea9524cb) )  /* from 'topsecrt' bootleg, but appears to be original */
+
+	ROM_REGION( 0x08000, "gfx1", 0 )
+	ROM_LOAD( "ts_08.8l",    0x00000, 0x8000, CRC(96ad379e) SHA1(accd3a560b259c186bc28cdc004ed8de0b12f9d5) )    /* VIDEORAM (text layer) tiles */
+
+	ROM_REGION( 0x10000, "gfx2", 0 )
+	ROM_LOAD( "ts_07.5l",    0x00000, 0x8000, CRC(25cdf8b2) SHA1(316f6acc46878682dabeab12722e6a64504d23bd) )    /* SCROLL2 Layer Tiles */
+	ROM_LOAD( "ts_06.4l",    0x08000, 0x8000, CRC(314fb12d) SHA1(dab0519a49b64fe7a837b3c6383f6147e1ab6ffd) )
+
+	ROM_REGION( 0x40000, "gfx3", 0 )
+	ROM_LOAD( "ts_12.17f",    0x00000, 0x8000, CRC(e4b4619e) SHA1(3bec8399ffb28fd50ce6ae88d90b091eadf8bda1) )   /* SCROLL1 Layer Tiles */
+	ROM_LOAD( "ts_11.15f",    0x08000, 0x8000, CRC(ab30237a) SHA1(ea6c07df992ba48f9eca7daa4ea775faa94358d2) )
+	ROM_LOAD( "ts_17.17g",    0x10000, 0x8000, CRC(deb657e4) SHA1(b36b468f9bbb7a4937286230d3f6caa14c61d4dd) )
+	ROM_LOAD( "ts_16.15g",    0x18000, 0x8000, CRC(d363b5f9) SHA1(1dd3991d99db2d6bcbdb12879ba50a01fef95004) )
+	ROM_LOAD( "ts_13.18f",    0x20000, 0x8000, CRC(a8f5a004) SHA1(36ab0cb8ec9ce0519876f7461ccc5020c9c5b597) )
+	ROM_LOAD( "ts_18.18g",    0x28000, 0x8000, CRC(3b36948c) SHA1(d85fcc0265ba1729c587b046cc5a7ba6f25363dd) )
+	ROM_LOAD( "ts_23.18j",    0x30000, 0x8000, CRC(bbfbe58a) SHA1(9b1d5672b6f3c5c0952f8dcd0da71acc68a97a5e) )
+	ROM_LOAD( "ts_24.18k",    0x38000, 0x8000, CRC(f156e564) SHA1(a6cad05bcc6d9ded6294f9b5aa856d05641aed02) )
+
+	ROM_REGION( 0x40000, "spritegen", 0 )
+	ROM_LOAD32_BYTE( "ts_10.13f",    0x00003, 0x8000, CRC(c3587d05) SHA1(ad0898a5d4cf110783ef092bf8e65b6ef31a8ae0) )   /* Sprites */
+	ROM_LOAD32_BYTE( "ts_09.11f",    0x20003, 0x8000, CRC(6b63eef2) SHA1(5d1580db7f49c5994c2a08a36c2d05f3e246930d) )
+	ROM_LOAD32_BYTE( "ts_15.13g",    0x00002, 0x8000, CRC(db8cebb0) SHA1(1cc9eac14851cde95fb2d69d6f5ffb08bc9c0d93) )
+	ROM_LOAD32_BYTE( "ts_14.11g",    0x20002, 0x8000, CRC(e2e41abf) SHA1(d002d0d8fdbb9ec3e2eac218f6338f733953ca82) )
+	ROM_LOAD32_BYTE( "ts_20.13j",    0x00001, 0x8000, CRC(bfd1a695) SHA1(bf93486b96bfa1a1d5015189043b07e6130e6df1) )
+	ROM_LOAD32_BYTE( "ts_19.11j",    0x20001, 0x8000, CRC(928b669e) SHA1(98ea9d23a46b0700490fd2fa7ab4fb0988dd5ca6) )
+	ROM_LOAD32_BYTE( "ts_22.17j",    0x00000, 0x8000, CRC(3fe05d9a) SHA1(32e28ef03fb82785019d1ae8b3859215b5368c2b) )
+	ROM_LOAD32_BYTE( "ts_21.15j",    0x20000, 0x8000, CRC(27a9bb7c) SHA1(bb60332c0ecde4d7797960dec39c1079498175c3) )
+
+	ROM_REGION( 0x0100, "proms", 0 )
+	ROM_LOAD( "63s141.18f",   0x0000, 0x0100, CRC(b58d0023) SHA1(e8a4a2e2951bf73b3d9eed6957e9ee1e61c9c58a) )    /* priority (not used), Labeled "TSB" */
+ROM_END
+
+ROM_START( bioniccbl )
+	ROM_REGION( 0x40000, "maincpu", 0 )      /* 68000 code */
+	ROM_LOAD16_BYTE( "02l.bin",   0x00000, 0x10000, CRC(b2fe1ddb) SHA1(892f19124993add96edabdba3aafeecc6668c5d9) )
+	ROM_LOAD16_BYTE( "03l.bin",   0x00001, 0x10000, CRC(427a003d) SHA1(5a379fe2942e5565810939d5eb843003226222cc) )
+	ROM_LOAD16_BYTE( "02u.bin",   0x20000, 0x10000, CRC(27f04bb6) SHA1(41d17b84b34dc8b2e5dfa67794a8df3e898b740b) )
+	ROM_LOAD16_BYTE( "03u.bin",   0x20001, 0x10000, CRC(c01547b1) SHA1(563bf6be4f10f5e6eb5b562266accf168f62bf30) )
+
+	ROM_REGION( 0x10000, "audiocpu", 0 )
+	ROM_LOAD( "01.bin",       0x00000, 0x8000, CRC(8ea07917) SHA1(e9ace70d89482fc3669860450a41aacacbee9083) )
+
+	ROM_REGION( 0x1000, "mcu", 0 )  /* i8751 microcontroller */
+	ROM_LOAD( "d8751h.bin",     0x0000, 0x1000, CRC(3ed7f0be) SHA1(db9e972065c8e60b5d74762dc3424271ea9524cb) )  /* from 'topsecrt' bootleg, but appears to be original */
+
+	ROM_REGION( 0x08000, "gfx1", 0 )
+	ROM_LOAD( "06.bin",       0x00000, 0x4000, CRC(4e6b81d9) SHA1(052784d789b0c9193edf218fa1883b6e3b7df988) )
+
+	ROM_REGION( 0x10000, "gfx2", 0 )
+	ROM_LOAD( "05.bin",       0x00000, 0x8000, CRC(9bf8dc7f) SHA1(539a52087ed1f58839b6aa8c0b5ed249f4f4041e) )
+	ROM_LOAD( "04.bin",       0x08000, 0x8000, CRC(1b43bf63) SHA1(b80d675a07cebd83daf202d1c3d3f7c2dedf5c30) )
+
+	ROM_REGION( 0x40000, "gfx3", 0 )
+	ROM_LOAD( "ts_12.17f",    0x00000, 0x8000, CRC(e4b4619e) SHA1(3bec8399ffb28fd50ce6ae88d90b091eadf8bda1) ) // 09.bin
+	ROM_LOAD( "ts_11.15f",    0x08000, 0x8000, CRC(ab30237a) SHA1(ea6c07df992ba48f9eca7daa4ea775faa94358d2) ) // 08.bin
+	ROM_LOAD( "ts_17.17g",    0x10000, 0x8000, CRC(deb657e4) SHA1(b36b468f9bbb7a4937286230d3f6caa14c61d4dd) ) // 13.bin
+	ROM_LOAD( "ts_16.15g",    0x18000, 0x8000, CRC(d363b5f9) SHA1(1dd3991d99db2d6bcbdb12879ba50a01fef95004) ) // 12.bin
+	ROM_LOAD( "ts_13.18f",    0x20000, 0x8000, CRC(a8f5a004) SHA1(36ab0cb8ec9ce0519876f7461ccc5020c9c5b597) ) // 10.bin
+	ROM_LOAD( "ts_18.18g",    0x28000, 0x8000, CRC(3b36948c) SHA1(d85fcc0265ba1729c587b046cc5a7ba6f25363dd) ) // 14.bin
+	ROM_LOAD( "ts_23.18j",    0x30000, 0x8000, CRC(bbfbe58a) SHA1(9b1d5672b6f3c5c0952f8dcd0da71acc68a97a5e) ) // 17.bin
+	ROM_LOAD( "ts_24.18k",    0x38000, 0x8000, CRC(f156e564) SHA1(a6cad05bcc6d9ded6294f9b5aa856d05641aed02) ) // 18.bin
+
+	ROM_REGION( 0x40000, "spritegen", 0 )
+	ROM_LOAD32_BYTE( "07.bin",       0x00003, 0x10000, CRC(a0e78996) SHA1(810a54e657c0faaff6a8494acaf803d1d2151893) )
+	ROM_LOAD32_BYTE( "11.bin",       0x00002, 0x10000, CRC(37cb11c2) SHA1(af8c2ae4bb6e6c13ea3e8b7c96e5b18f1eb1d5a5) )
+	ROM_LOAD32_BYTE( "15.bin",       0x00001, 0x10000, CRC(4e0354ce) SHA1(d3256c891b44c6593b0b44c0d0a3e754ce78c1cb) )
+	ROM_LOAD32_BYTE( "16.bin",       0x00000, 0x10000, CRC(ac89e5cc) SHA1(aa7e065ece6d25b7e83fadcd22c09e1f7dc0b86f) )
+
+	ROM_REGION( 0x0100, "proms", 0 )
+	ROM_LOAD( "63s141.18f",   0x0000, 0x0100, CRC(b58d0023) SHA1(e8a4a2e2951bf73b3d9eed6957e9ee1e61c9c58a) )    /* priority (not used), Labeled "TSB" */
+ROM_END
+
+ROM_START( bioniccbl2 ) // only the 4 maincpu ROMs differ, they came from an original, not working, Capcom board, but the title screen is Bionic Commandos like a bootleg? The other ROMs match topsecrt
+	ROM_REGION( 0x40000, "maincpu", 0 )      /* 68000 code */
+	ROM_LOAD16_BYTE( "tsu_02.1a",   0x00000, 0x10000, CRC(c03d3424) SHA1(1d47185e10813c2792bda31c7dfbb40e88fd46ee) ) //sldc
+	ROM_LOAD16_BYTE( "tsu_04.1b",   0x00001, 0x10000, CRC(9f13eb9d) SHA1(b9c8cfc22a1d2adcc6a93e3e382b2126446c05aa) ) //sldc
+	ROM_LOAD16_BYTE( "3",   0x20000, 0x10000, CRC(a909ec2c) SHA1(7979480b5d82704f7d15546bda6af78316505f85) ) // the only ROM without an original sticker
+	ROM_LOAD16_BYTE( "tsu_05.1d",   0x20001, 0x10000, CRC(4e6b75ce) SHA1(44c3900b8dc9f375a7d6ed57c4025bc35771e29c) ) //sldc
+
+	ROM_REGION( 0x10000, "audiocpu", 0 )
+	ROM_LOAD( "ts_01.4e",    0x00000, 0x8000, CRC(8ea07917) SHA1(e9ace70d89482fc3669860450a41aacacbee9083) )
+
+	ROM_REGION( 0x1000, "mcu", 0 )  /* i8751 microcontroller */
+	ROM_LOAD( "d8751h.bin",     0x0000, 0x1000, CRC(3ed7f0be) SHA1(db9e972065c8e60b5d74762dc3424271ea9524cb) )  /* from 'topsecrt' bootleg, but appears to be original */
+
+	ROM_REGION( 0x08000, "gfx1", 0 )
+	ROM_LOAD( "ts_08.8l",    0x00000, 0x8000, CRC(96ad379e) SHA1(accd3a560b259c186bc28cdc004ed8de0b12f9d5) )    /* VIDEORAM (text layer) tiles */
+
+	ROM_REGION( 0x10000, "gfx2", 0 )
+	ROM_LOAD( "ts_07.5l",    0x00000, 0x8000, CRC(25cdf8b2) SHA1(316f6acc46878682dabeab12722e6a64504d23bd) )    /* SCROLL2 Layer Tiles */
+	ROM_LOAD( "ts_06.4l",    0x08000, 0x8000, CRC(314fb12d) SHA1(dab0519a49b64fe7a837b3c6383f6147e1ab6ffd) )
+
+	ROM_REGION( 0x40000, "gfx3", 0 )
+	ROM_LOAD( "ts_12.17f",    0x00000, 0x8000, CRC(e4b4619e) SHA1(3bec8399ffb28fd50ce6ae88d90b091eadf8bda1) )   /* SCROLL1 Layer Tiles */
+	ROM_LOAD( "ts_11.15f",    0x08000, 0x8000, CRC(ab30237a) SHA1(ea6c07df992ba48f9eca7daa4ea775faa94358d2) )
+	ROM_LOAD( "ts_17.17g",    0x10000, 0x8000, CRC(deb657e4) SHA1(b36b468f9bbb7a4937286230d3f6caa14c61d4dd) )
+	ROM_LOAD( "ts_16.15g",    0x18000, 0x8000, CRC(d363b5f9) SHA1(1dd3991d99db2d6bcbdb12879ba50a01fef95004) )
+	ROM_LOAD( "ts_13.18f",    0x20000, 0x8000, CRC(a8f5a004) SHA1(36ab0cb8ec9ce0519876f7461ccc5020c9c5b597) )
+	ROM_LOAD( "ts_18.18g",    0x28000, 0x8000, CRC(3b36948c) SHA1(d85fcc0265ba1729c587b046cc5a7ba6f25363dd) )
+	ROM_LOAD( "ts_23.18j",    0x30000, 0x8000, CRC(bbfbe58a) SHA1(9b1d5672b6f3c5c0952f8dcd0da71acc68a97a5e) )
+	ROM_LOAD( "ts_24.18k",    0x38000, 0x8000, CRC(f156e564) SHA1(a6cad05bcc6d9ded6294f9b5aa856d05641aed02) )
+
+	ROM_REGION( 0x40000, "spritegen", 0 )
+	ROM_LOAD32_BYTE( "tse_10.13f",   0x00003, 0x8000, CRC(d28eeacc) SHA1(8b4a655a48da276b07f3464c65743b13cec52bcb) )   /* Sprites */
+	ROM_LOAD32_BYTE( "tsu_09.11f",   0x20003, 0x8000, CRC(6a049292) SHA1(525c862061f426d679b539b6926af4c9f14b47b5) )
+	ROM_LOAD32_BYTE( "tse_15.13g",   0x00002, 0x8000, CRC(9b5593c0) SHA1(73c0acbb01fe69c2bd29dea11b6a223c8efb54a0) )
+	ROM_LOAD32_BYTE( "tsu_14.11g",   0x20002, 0x8000, CRC(46b2ad83) SHA1(21ebd5691a544323fdfcf330b9a37bbe0428e3e3) )
+	ROM_LOAD32_BYTE( "tse_20.13j",   0x00001, 0x8000, CRC(b03db778) SHA1(f72a93e73196c800c1893fd3b523394d702547dd) )
+	ROM_LOAD32_BYTE( "tsu_19.11j",   0x20001, 0x8000, CRC(b5c82722) SHA1(969f9159f7d59e4e4c9ef9ddbdc27cbfa531eabf) )
+	ROM_LOAD32_BYTE( "tse_22.17j",   0x00000, 0x8000, CRC(d4dedeb3) SHA1(e121057bb541f3f5c755963ca22832c3fe2637c0) )
+	ROM_LOAD32_BYTE( "tsu_21.15j",   0x20000, 0x8000, CRC(98777006) SHA1(bcc2058b639e9b71d16af05f63df298bcce91fdc) )
+
+	ROM_REGION( 0x0100, "proms", 0 )
+	ROM_LOAD( "63s141.18f",   0x0000, 0x0100, CRC(b58d0023) SHA1(e8a4a2e2951bf73b3d9eed6957e9ee1e61c9c58a) )    /* priority (not used), Labeled "TSB" */
+ROM_END
+
+
+//**************************************************************************
+//  SYSTEM DRIVERS
+//**************************************************************************
+
+//    YEAR  NAME        PARENT   MACHINE  INPUT    CLASS          INIT        ROT   COMPANY    FULLNAME                             FLAGS
+GAME( 1987, bionicc,    0,       bionicc, bionicc, bionicc_state, empty_init, ROT0, "Capcom",  "Bionic Commando (Euro)",            MACHINE_SUPPORTS_SAVE )
+GAME( 1987, bionicc1,   bionicc, bionicc, bionicc, bionicc_state, empty_init, ROT0, "Capcom",  "Bionic Commando (US set 1)",        MACHINE_SUPPORTS_SAVE )
+GAME( 1987, bionicc2,   bionicc, bionicc, bionicc, bionicc_state, empty_init, ROT0, "Capcom",  "Bionic Commando (US set 2)",        MACHINE_SUPPORTS_SAVE )
+GAME( 1987, topsecrt,   bionicc, bionicc, bionicc, bionicc_state, empty_init, ROT0, "Capcom",  "Top Secret (Japan, old revision)",  MACHINE_SUPPORTS_SAVE )
+GAME( 1987, topsecrt2,  bionicc, bionicc, bionicc, bionicc_state, empty_init, ROT0, "Capcom",  "Top Secret (Japan, revision B)",    MACHINE_SUPPORTS_SAVE )
+GAME( 1987, bioniccbl,  bionicc, bionicc, bionicc, bionicc_state, empty_init, ROT0, "bootleg", "Bionic Commandos (bootleg, set 1)", MACHINE_SUPPORTS_SAVE )
+GAME( 1987, bioniccbl2, bionicc, bionicc, bionicc, bionicc_state, empty_init, ROT0, "bootleg", "Bionic Commandos (bootleg, set 2)", MACHINE_SUPPORTS_SAVE )
+
+// there's also an undumped JP new revision on which there are no extra lives after 1 million points, plus other bug-fixes / changes (possibly topsecrt2 set?)

snapshots/jotego_jtcores_pr1100/cores/biocom/hdl/jtbiocom_bus.v

@@ -0,0 +1,53 @@
+/*  This file is part of JTCORES.
+    JTCORES program is free software: you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation, either version 3 of the License, or
+    (at your option) any later version.
+
+    JTCORES program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with JTCORES.  If not, see <http://www.gnu.org/licenses/>.
+
+    Author: Jose Tejada Gomez. Twitter: @topapate
+    Version: 1.0
+    Date: 12-9-2019 */
+
+// Bionic Commando: Main CPU
+
+
+module jtbiocom_bus(
+    input      [16:1]  mcu_addr,
+    input      [19:1]  cpu_addr,
+    input              mcu_wr,
+    input              UDSWn,
+    input              LDSWn,
+    input              mcu_DMAn,
+    input      [ 7:0]  mcu_dout,
+    input      [15:0]  cpu_dout,
+
+    output reg [19:1]  bus_addr,
+    output reg [15:0]  bus_din,
+    output reg         bus_UDSWn,
+    output reg         bus_LDSWn
+);
+
+always @(*) begin
+    if ( !mcu_DMAn ) begin // MCU access
+        bus_addr  = {3'b111, mcu_addr };
+        bus_din   = { 8'hff, mcu_dout };
+        bus_UDSWn = 1'b1;
+        bus_LDSWn = ~mcu_wr;
+    end else begin // OBJ access
+        bus_addr  = cpu_addr;
+        bus_din   = cpu_dout;
+        bus_UDSWn = UDSWn;
+        bus_LDSWn = LDSWn;
+    end
+end
+
+
+endmodule

snapshots/jotego_jtcores_pr1100/cores/biocom/hdl/jtbiocom_colmix.v

@@ -0,0 +1,190 @@
+/*  This file is part of JTCORES.
+    JTCORES program is free software: you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation, either version 3 of the License, or
+    (at your option) any later version.
+
+    JTCORES program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with JTCORES.  If not, see <http://www.gnu.org/licenses/>.
+
+    Author: Jose Tejada Gomez. Twitter: @topapate
+    Version: 1.0
+    Date: 22-9-2019 */
+
+// Resistor values measured on PCB by Caius (Twitter @Caius63417737)
+// Pin number    7    6    5  4  3   2    1
+// R2R ladders: 4.7k-2.2K-1K-470-220-100  common net
+// R9  470, R10 470, R11 470, R12 1K, R14 1K, R16 1K, R13 220, R15 220, R17 220
+
+// Table of colours (voltages)
+//                      Brightness
+//       0      1    2     3     4     5     6     7
+// Colour
+// 0   0.000 0.194 0.412 0.606 0.881 1.075 1.293 1.487
+// 1   0.088 0.282 0.500 0.694 0.969 1.163 1.381 1.575
+// 2   0.194 0.388 0.606 0.800 1.075 1.268 1.487 1.681
+// 3   0.282 0.476 0.694 0.888 1.163 1.357 1.575 1.769
+// 4   0.412 0.606 0.825 1.018 1.293 1.487 1.706 1.899
+// 5   0.500 0.694 0.913 1.107 1.381 1.575 1.794 1.987
+// 6   0.606 0.800 1.018 1.212 1.487 1.681 1.899 2.093
+// 7   0.694 0.888 1.107 1.300 1.575 1.769 1.987 2.181
+// 8   0.881 1.075 1.293 1.487 1.762 1.956 2.174 2.368
+// 9   0.969 1.163 1.381 1.575 1.850 2.044 2.262 2.456
+// 10  1.075 1.268 1.487 1.681 1.956 2.149 2.368 2.562
+// 11  1.163 1.357 1.575 1.769 2.044 2.237 2.456 2.650
+// 12  1.293 1.487 1.706 1.899 2.174 2.368 2.586 2.780
+// 13  1.381 1.575 1.794 1.987 2.262 2.456 2.674 2.868
+// 14  1.487 1.681 1.899 2.093 2.368 2.562 2.780 2.974
+// 15  1.575 1.769 1.987 2.181 2.456 2.650 2.868 3.062
+//
+// For a 5-bit value:
+// Col    0   1   2   3   4   5   6   7
+// 0      0   2   4   6   9   11  13  15
+// 1      1   3   5   7   10  12  14  16
+// 2      2   4   6   8   11  13  15  17
+// 3      3   5   7   9   12  14  16  18
+// 4      4   6   8   10  13  15  17  19
+// 5      5   7   9   11  14  16  18  20
+// 6      6   8   10  12  15  17  19  21
+// 7      7   9   11  13  16  18  20  22
+// 8      9   11  13  15  18  20  22  24
+// 9      10  12  14  16  19  21  23  25
+// 10     11  13  15  17  20  22  24  26
+// 11     12  14  16  18  21  23  25  27
+// 12     13  15  17  19  22  24  26  28
+// 13     14  16  18  20  23  25  27  29
+// 14     15  17  19  21  24  26  28  30
+// 15     16  18  20  22  25  27  29  31
+
+module jtbiocom_colmix(
+    input            rst,
+    input            clk,
+    input            cen6 /* synthesis direct_enable = 1 */,
+    input            cpu_cen,
+    // pixel input from generator modules
+    input [5:0]      char_pxl,        // character color code
+    input [7:0]      scr1_pxl,
+    input [7:0]      scr2_pxl,
+    input [7:0]      obj_pxl,
+    input            preLVBL,
+    input            preLHBL,
+    output           LHBL,
+    output           LVBL,
+    // Priority PROM
+    input [7:0]      prog_addr,
+    input            prom_prio_we,
+    input [3:0]      prom_din,
+    // CPU inteface
+    input [10:1]     AB,
+    input            col_uw,
+    input            col_lw,
+    input [15:0]     DB,
+
+    output     [4:0] red,
+    output     [4:0] green,
+    output     [4:0] blue,
+    // Debug
+    input      [3:0] gfx_en
+);
+
+parameter SIM_PRIO = "../../../rom/biocom/63s141.18f";
+localparam BLANK_DLY=2;
+
+reg [9:0] pxl_mux;
+
+wire char_en = gfx_en[0];
+wire scr1_en = gfx_en[1];
+wire scr2_en = gfx_en[2];
+wire obj_en  = gfx_en[3];
+
+wire [1:0] pre_prio;
+reg  [7:0] seladdr;
+reg  [1:0] prio, presel;
+wire       char_blank_n = ~&char_pxl[1:0];
+wire       preLBL;
+
+always @(*) begin
+    seladdr[0]   = scr2_en ? ~&scr2_pxl[3:0] : 1'b0;
+    seladdr[6:1] = scr1_en ? { scr1_pxl[7:6], scr1_pxl[3:0] } : 6'h3f;
+    seladdr[7]   = obj_en  ? ~&obj_pxl[3:0] : 1'b0;
+    prio         = pre_prio  | ( char_en ? {2{char_blank_n}} : 2'b0 );
+end
+
+always @(posedge clk) if(cen6) begin
+    case( prio )
+        2'b11: pxl_mux[7:0] <= { 2'b0, char_pxl };
+        2'b10: pxl_mux[7:0] <= obj_pxl;
+        2'b01: pxl_mux[7:0] <= { 2'b0, scr1_pxl[5:0] };
+        2'b00: pxl_mux[7:0] <= { 1'b0, scr2_pxl[6:0] };
+    endcase
+    pxl_mux[9:8] <= prio;
+end
+
+// Address mux
+wire [3:0] pal_red, pal_green, pal_blue, pal_bright;
+
+jtframe_dual_ram16 #(
+    .AW        (10          ),
+    .SIMFILE_LO("pal_lo.bin"), // palrg.hex
+    .SIMFILE_HI("pal_hi.bin")  // palbb.hex
+) u_ram(
+    .clk0   ( clk       ),
+    .clk1   ( clk       ),
+
+    // CPU writes
+    .addr0  ( AB  ),
+    .data0  ( DB        ),
+    .we0    ( {col_uw, col_lw} ),
+    .q0     (           ),
+
+    // Video reads
+    .addr1  ( pxl_mux ),
+    .data1  (           ),
+    .we1    ( 2'b0      ),
+    .q1     ( {pal_red, pal_green, pal_blue, pal_bright } )
+);
+
+// Clock must be faster than 6MHz so pre_prio is ready for the next
+// 6MHz clock cycle:
+jtframe_prom #(.AW(8),.DW(2),.SIMFILE(SIM_PRIO)) u_pre_prio(
+    .clk    ( clk           ),
+    .cen    ( 1'b1          ),
+    .data   ( prom_din[1:0] ),
+    .rd_addr( seladdr       ),
+    .wr_addr( prog_addr     ),
+    .we     ( prom_prio_we  ),
+    .q      ( pre_prio      )
+);
+
+reg [4:0] pre_r, pre_g, pre_b;
+
+always @(posedge clk) begin
+    if( ~preLBL ) begin
+        pre_r <= 5'd0;
+        pre_g <= 5'd0;
+        pre_b <= 5'd0;
+    end else begin
+        pre_r <= pal_bright[3] ? { pal_red,  pal_red[3]   } : { 1'b0, pal_red   } + { 1'b0, pal_bright[2:0], pal_bright[2]};
+        pre_g <= pal_bright[3] ? { pal_green,pal_green[3] } : { 1'b0, pal_green } + { 1'b0, pal_bright[2:0], pal_bright[2]};
+        pre_b <= pal_bright[3] ? { pal_blue, pal_blue[3]  } : { 1'b0, pal_blue  } + { 1'b0, pal_bright[2:0], pal_bright[2]};
+    end
+end
+
+jtframe_blank #(.DLY(BLANK_DLY),.DW(15)) u_dly(
+    .clk        ( clk                 ),
+    .pxl_cen    ( cen6                ),
+    .preLHBL    ( preLHBL             ),
+    .preLVBL    ( preLVBL             ),
+    .LHBL       ( LHBL                ),
+    .LVBL       ( LVBL                ),
+    .preLBL     ( preLBL              ),
+    .rgb_in     ( {pre_r, pre_g, pre_b}),
+    .rgb_out    ( {red, green, blue }  )
+);
+
+endmodule

snapshots/jotego_jtcores_pr1100/cores/biocom/hdl/jtbiocom_game.v

@@ -0,0 +1,287 @@
+/*  This file is part of JTCORES.
+    JTCORES program is free software: you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation, either version 3 of the License, or
+    (at your option) any later version.
+
+    JTCORES program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with JTCORES.  If not, see <http://www.gnu.org/licenses/>.
+
+    Author: Jose Tejada Gomez. Twitter: @topapate
+    Version: 1.0
+    Date: 14-9-2019 */
+
+
+module jtbiocom_game(
+    `include "jtframe_game_ports.inc" // see $JTFRAME/hdl/inc/jtframe_game_ports.inc
+);
+
+wire [ 8:0] V, H;
+wire        HINIT;
+
+wire [13:1] cpu_AB;
+wire        char_cs, col_uw, col_lw, RnW;
+wire        flip;
+wire [ 7:0] char_dout, scr1_dout, scr2_dout;
+wire [15:0] cpu_dout;
+wire        rd, cpu_cen;
+wire        char_busy, scr1_busy, scr2_busy;
+wire        clk_mcu;
+
+// MCU interface
+wire [ 7:0] snd_din, snd_dout;
+wire        snd_mcu_wr, snd_mcu_rd;
+wire        mcu_brn;
+wire [ 7:0] mcu_din, mcu_dout;
+wire [16:1] mcu_addr;
+wire        mcu_wr, mcu_DMAn, mcu_DMAONn;
+
+wire        preLHBL, preLVBL,
+            LHBL_obj, LVBL_obj;
+
+wire        nc,ncb;
+
+// sound
+wire [7:0] snd_latch;
+wire        snd_nmi_n;
+// OBJ
+wire        OKOUT, blcnten, obj_br, bus_ack;
+wire [13:1] obj_AB;     // 1 more bit than older games
+wire [15:0] oram_dout;
+
+wire        prom_mcu_we, prom_prio_we;
+
+wire        scr1_cs, scr2_cs;
+wire [15:0] scr1_hpos, scr1_vpos;
+wire [ 8:0] scr2_hpos, scr2_vpos;
+
+assign clk_mcu = clk24;
+assign prom_mcu_we  = prom_we && !ioctl_addr[12];
+assign prom_prio_we = prom_we &&  ioctl_addr[12];
+assign debug_view   = 0;
+assign dip_flip     = ~flip;
+
+always @* begin
+    post_addr = prog_addr;
+    if( ioctl_addr>=`JTFRAME_BA2_START && ioctl_addr<`JTFRAME_BA3_START ) begin
+        post_addr[5:1] = { prog_addr[4:1], prog_addr[5] };
+    end
+end
+
+jtgng_timer u_timer(
+    .clk       ( clk      ),
+    .cen6      ( pxl_cen  ),
+    .V         ( V        ),
+    .H         ( H        ),
+    .Hinit     ( HINIT    ),
+    .LHBL      ( preLHBL  ),
+    .LHBL_obj  ( LHBL_obj ),
+    .LVBL      ( preLVBL  ),
+    .LVBL_obj  ( LVBL_obj ),
+    .HS        ( HS       ),
+    .VS        ( VS       ),
+    .Vinit     (          )
+);
+
+jtbiocom_main u_main(
+    .rst        ( rst           ),
+    .clk        ( clk           ),
+    .cpu_cen    ( cpu_cen       ),
+    .cpu_cenb   (               ),
+    // Timing
+    .flip       ( flip          ),
+    .V          ( V             ),
+    .LHBL       ( LHBL          ),
+    .LVBL       ( LVBL          ),
+    // sound
+    .snd_latch  ( snd_latch     ),
+    .snd_nmi_n  ( snd_nmi_n     ),
+    // CHAR
+    .char_dout  ( { 8'hff, char_dout } ), // upper 8 bits unused
+    .cpu_dout   ( cpu_dout      ),
+    .char_cs    ( char_cs       ),
+    .char_busy  ( char_busy     ),
+    // SCROLL 1
+    .scr1_dout  ( scr1_dout     ),
+    .scr1_cs    ( scr1_cs       ),
+    .scr1_busy  ( scr1_busy     ),
+    .scr1_hpos  ( scr1_hpos     ),
+    .scr1_vpos  ( scr1_vpos     ),
+    .scr_bank   (               ),  // only Tiger Road
+    // SCROLL 2
+    .scr2_dout  ( scr2_dout     ),
+    .scr2_cs    ( scr2_cs       ),
+    .scr2_busy  ( scr2_busy     ),
+    .scr2_hpos  ( scr2_hpos     ),
+    .scr2_vpos  ( scr2_vpos     ),
+    // OBJ - bus sharing
+    .UDSWn      (               ),
+    .LDSWn      (               ),
+    .obj_AB     ( obj_AB        ),
+    .cpu_AB     ( cpu_AB        ),
+    .oram_dout  ( oram_dout     ),
+    .OKOUT      ( OKOUT         ),
+    .blcnten    ( blcnten       ),
+    .obj_br     ( obj_br        ),
+    .bus_ack    ( bus_ack       ),
+    .col_uw     ( col_uw        ),
+    .col_lw     ( col_lw        ),
+    // MCU interface
+    .mcu_cen    (  mcu_cen      ),
+    .mcu_brn    (  mcu_brn      ),
+    .mcu_din    (  mcu_din      ),
+    .mcu_dout   (  mcu_dout     ),
+    .mcu_addr   (  mcu_addr     ),
+    .mcu_wr     (  mcu_wr       ),
+    .mcu_DMAn   (  mcu_DMAn     ),
+    .mcu_DMAONn (  mcu_DMAONn   ),
+    // ROM
+    .rom_cs     ( main_cs       ),
+    .rom_addr   ( main_addr     ),
+    .rom_data   ( main_data     ),
+    .rom_ok     ( main_ok       ),
+    // Cabinet input
+    .cab_1p     ( cab_1p[1:0]   ),
+    .coin       ( coin[1:0]     ),
+    .joystick1  ( joystick1[5:0]),
+    .joystick2  ( joystick2[5:0]),
+
+    .RnW        ( RnW           ),
+    // DIP switches
+    .service    ( service       ),
+    .dip_pause  ( dip_pause     ),
+    .dipsw_a    ( dipsw[ 7:0]   ),
+    .dipsw_b    ( dipsw[15:8]   )
+);
+
+jtbiocom_mcu u_mcu(
+    .rst        ( rst24         ),
+    .clk        ( clk_mcu       ),
+    .rst_cpu    ( rst           ),
+    .clk_rom    ( clk           ),
+    .clk_cpu    ( clk           ),
+    .cen6a      ( mcu_cen       ),       //  6   MHz
+    // Main CPU interface
+    .DMAONn     ( mcu_DMAONn    ),
+    .mcu_din    ( mcu_din       ),
+    .mcu_dout   ( mcu_dout      ),
+    .mcu_wr     ( mcu_wr        ),   // always write to low bytes
+    .mcu_addr   ( mcu_addr      ),
+    .mcu_brn    ( mcu_brn       ), // RQBSQn
+    .DMAn       ( mcu_DMAn      ),
+
+    // Sound CPU interface
+    .snd_din    ( snd_din       ),
+    .snd_dout   ( snd_dout      ),
+    .snd_mcu_wr ( snd_mcu_wr    ),
+    .snd_mcu_rd ( snd_mcu_rd    ),
+    // ROM programming
+    .prog_addr  ( prog_addr[11:0] ),
+    .prom_din   ( prog_data[7:0]  ),
+    .prom_we    ( prom_mcu_we     )
+);
+
+jtbiocom_sound #(.RECOVERY(1)) u_sound (
+    .rst            ( rst            ),
+    .clk            ( clk            ),
+    .cen_fm         ( cen_fm         ),
+    .cen_fm2        ( cen_fm2        ),
+    // Interface with main CPU
+    .snd_latch      ( snd_latch      ),
+    .nmi_n          ( snd_nmi_n      ),
+    // Interface with MCU
+    .snd_din        ( snd_din        ),
+    .snd_dout       ( snd_dout       ),
+    .snd_mcu_wr     ( snd_mcu_wr     ),
+    .snd_mcu_rd     ( snd_mcu_rd     ),
+    // ROM
+    .rom_addr       ( snd_addr       ),
+    .rom_data       ( snd_data       ),
+    .rom_cs         ( snd_cs         ),
+    .rom_ok         ( snd_ok         ),
+    // sound output
+    .fm_l           ( fm_l           ),
+    .fm_r           ( fm_r           )
+);
+
+jtbiocom_video #(
+    .OBJ_PAL      (2'b10),
+    .PALETTE_PROM (1),
+    .SCRWIN       (0)
+) u_video(
+    .rst        ( rst           ),
+    .clk        ( clk           ),
+    .cen12      ( pxl2_cen      ),
+    .cen8       ( video_cen8    ),
+    .cen6       ( pxl_cen       ),
+    .cpu_cen    ( cpu_cen       ),
+    .cpu_AB     ( cpu_AB        ),
+    .V          ( V             ),
+    .H          ( H             ),
+    .RnW        ( RnW           ),
+    .flip       ( flip          ),
+    .cpu_dout   ( cpu_dout      ),
+    // CHAR
+    .char_cs    ( char_cs       ),
+    .char_dout  ( char_dout     ),
+    .char_addr  ( char_addr     ),
+    .char_data  ( char_data     ),
+    .char_busy  ( char_busy     ),
+    .char_ok    ( char_ok       ),
+    // SCROLL 1
+    .scr1_cs    ( scr1_cs       ),
+    .scr1_dout  ( scr1_dout     ),
+    .scr1_addr  ( scr1_addr     ),
+    .scr1_data  ( scr1_data     ),
+    .scr1_busy  ( scr1_busy     ),
+    .scr1_hpos  ( scr1_hpos[9:0]),
+    .scr1_vpos  ( scr1_vpos[9:0]),
+    .scr1_ok    ( scr1_ok       ),
+    // SCROLL 2
+    .scr2_cs    ( scr2_cs       ),
+    .scr2_dout  ( scr2_dout     ),
+    .scr2_addr  ( scr2_addr     ),
+    .scr2_data  ( scr2_data     ),
+    .scr2_busy  ( scr2_busy     ),
+    .scr2_hpos  ( scr2_hpos     ),
+    .scr2_vpos  ( scr2_vpos     ),
+    .scr2_ok    ( scr2_ok       ),
+    // OBJ
+    .HINIT      ( HINIT         ),
+    .obj_AB     ( obj_AB        ),
+    .oram_dout  ( oram_dout[11:0] ),
+    .obj_addr   ( obj_addr      ),
+    .obj_data   ( obj_data      ),
+    .obj_cs     ( obj_cs        ),
+    .OKOUT      ( OKOUT         ),
+    .bus_req    ( obj_br        ), // Request bus
+    .bus_ack    ( bus_ack       ), // bus acknowledge
+    .blcnten    ( blcnten       ), // bus line counter enable
+    .col_uw     ( col_uw        ),
+    .col_lw     ( col_lw        ),
+    .obj_ok     ( obj_ok        ),
+    // PROMs
+    .prog_addr    ( prog_addr[7:0]),
+    .prom_prio_we ( prom_prio_we  ),
+    .prom_din     ( prog_data[3:0]),
+    // Color Mix
+    .HS         ( HS            ),
+    .preLHBL    ( preLHBL       ),
+    .preLVBL    ( preLVBL       ),
+    .LHBL_obj   ( LHBL_obj      ),
+    .LVBL_obj   ( LVBL_obj      ),
+    .LHBL       ( LHBL          ),
+    .LVBL       ( LVBL          ),
+    .gfx_en     ( gfx_en        ),
+    // Pixel Output
+    .red        ( red           ),
+    .green      ( green         ),
+    .blue       ( blue          )
+);
+
+endmodule

snapshots/jotego_jtcores_pr1100/cores/biocom/hdl/jtbiocom_main.v

@@ -0,0 +1,514 @@
+/*  This file is part of JTCORES.
+    JTCORES program is free software: you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation, either version 3 of the License, or
+    (at your option) any later version.
+
+    JTCORES program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with JTCORES.  If not, see <http://www.gnu.org/licenses/>.
+
+    Author: Jose Tejada Gomez. Twitter: @topapate
+    Version: 1.0
+    Date: 12-9-2019 */
+
+// Bionic Commando: Main CPU
+
+
+module jtbiocom_main(
+    input              rst,
+    input              clk,
+    output             cpu_cen,
+    output             cpu_cenb,
+    // Timing
+    output  reg        flip,
+    input   [8:0]      V,
+    input              LHBL,
+    input              LVBL,
+    // Sound
+    output  reg  [7:0] snd_latch,
+    //output  reg  [7:0] snd_hack,
+    output  reg        snd_nmi_n,
+    // Characters
+    input       [15:0] char_dout,
+    output      [15:0] cpu_dout,
+    output  reg        char_cs,
+    input              char_busy,
+    // scroll
+    input   [7:0]      scr1_dout,
+    input   [7:0]      scr2_dout,
+    output  reg        scr1_cs,
+    output  reg        scr2_cs,
+    input              scr1_busy,
+    input              scr2_busy,
+    output reg [15:0]  scr1_hpos,
+    output reg [15:0]  scr1_vpos,
+    output reg [8:0]   scr2_hpos,
+    output reg [8:0]   scr2_vpos,
+    output reg         scr_bank,
+    // cabinet I/O
+    input   [5:0]      joystick1,
+    input   [5:0]      joystick2,
+    input   [1:0]      cab_1p,
+    input   [1:0]      coin,
+    // BUS sharing
+    output             UDSWn,
+    output             LDSWn,
+    output  [13:1]     cpu_AB,
+    output  [15:0]     oram_dout,
+    input   [13:1]     obj_AB,
+    output             RnW,
+    output  reg        OKOUT,
+    input              obj_br,   // Request bus
+    output             bus_ack,  // bus acknowledge for Object engine
+    input              blcnten,  // bus line counter enable
+    // MCU interface
+    input              mcu_cen,
+    input              mcu_brn,
+    input      [ 7:0]  mcu_dout,
+    output reg [ 7:0]  mcu_din,
+    input      [16:1]  mcu_addr,
+    input              mcu_wr,
+    input              mcu_DMAn,
+    output  reg        mcu_DMAONn,
+    // Palette
+    output             col_uw,
+    output             col_lw,
+    // ROM access
+    output  reg        rom_cs,
+    output      [17:1] rom_addr,
+    input       [15:0] rom_data,
+    input              rom_ok,
+    // DIP switches
+    input              service,
+    input              dip_pause,
+    input    [7:0]     dipsw_a,
+    input    [7:0]     dipsw_b
+);
+
+parameter GAME=0; // 0 for Bionic Commando, 1 for Tiger Road/F1Dream
+`ifndef NOMAIN
+wire [19:1] A;
+wire [3:0] ncA;
+
+`ifdef SIMULATION
+wire [23:0] A_full = {ncA, A,1'b0};
+`endif
+wire [15:0] wram_dout;
+reg  [15:0] cpu_din;
+wire        BRn, BGACKn, BGn;
+reg         io_cs, ram_cs, obj_cs, col_cs;
+reg         scr1hpos_cs, scr2hpos_cs, scr1vpos_cs, scr2vpos_cs;
+wire        ASn;
+
+wire mreq_n, rfsh_n, busak_n;
+reg  BERRn;
+
+// high during DMA transfer
+wire UDSn, LDSn;
+
+assign UDSWn   = RnW | UDSn;
+assign LDSWn   = RnW | LDSn;
+assign col_uw  = col_cs & ~UDSWn;
+assign col_lw  = col_cs & ~LDSWn;
+
+wire CPUbus = !blcnten && mcu_DMAn; // main CPU in control of the bus
+wire [16:1] mcu_addr_s;
+wire [ 7:0] mcu_dout_s;
+wire        mcu_wr_s;
+wire [16:1] Aeff   = CPUbus ? A[16:1] : mcu_addr_s;
+
+jtframe_sync #(.W(16+8+1)) u_mcus(
+    .clk_in ( 1'b0      ),
+    .clk_out( clk       ),
+    .raw    ( {mcu_addr, mcu_dout, mcu_wr } ),
+    .sync   ( {mcu_addr_s, mcu_dout_s, mcu_wr_s } )
+);
+
+always @(*) begin
+    ram_cs        = 1'b0;
+    obj_cs        = 1'b0;
+    col_cs        = 1'b0;
+    io_cs         = 1'b0;
+    char_cs       = 1'b0;
+    scr1_cs       = 1'b0;
+    scr2_cs       = 1'b0;
+    OKOUT         = 1'b0;
+    mcu_DMAONn    = 1'b1;   // for once, I leave the original active low setting
+    scr1vpos_cs   = 1'b0;
+    scr1hpos_cs   = 1'b0;
+    scr2vpos_cs   = 1'b0;
+    scr2hpos_cs   = 1'b0;
+
+    // The address decoder is shared with the MCU like the original design
+    if( !CPUbus || (A[19:17]==3'b111 && !ASn) )
+        case( Aeff[16:14] )  // 111X
+            3'd0: obj_cs  = 1'b1; // E_0000
+            3'd1: begin
+                io_cs   = 1'b1; // E_4000
+                if( GAME==1 ) mcu_DMAONn = !(A[1] && !RnW);// E_4002
+            end
+            3'd2: if( !UDSWn && !LDSWn && (Aeff[4]^GAME==1)) begin // E_8010
+                // scrpt_cs
+                // $display("SCRPTn");
+                case( Aeff[3:1]) // SCRPTn in the schematics
+                        0: scr1hpos_cs = 1;
+                        1: scr1vpos_cs = 1;
+                        2: scr2hpos_cs = 1; // Unused if GAME==1
+                        3: scr2vpos_cs = 1;
+                        4: if( GAME==0 ) OKOUT = 1;
+                        5: if( GAME==0 ) mcu_DMAONn = 0; // to MCU
+                        7: if( GAME==1 ) OKOUT = 1;
+                    default:;
+                endcase
+            end
+            3'd3: char_cs = 1'b1; // E_C000
+            3'd4: scr1_cs = GAME==0; // F_0000
+            3'd5: scr2_cs = GAME==0; // F_4000
+            3'd6: col_cs  = 1'b1; // F_8000
+            3'd7: ram_cs  = 1'b1; // F_C000
+        endcase
+end
+
+always @(*) begin
+    rom_cs        = 1'b0;
+    BERRn         = 1'b1;
+    if( CPUbus ) begin
+        case(A[19:18])
+            2'd0: rom_cs = 1'b1;
+            2'd1, 2'd2: BERRn = ASn;
+            default:;
+        endcase
+    end
+end
+
+// SCROLL H/V POSITION
+always @(posedge clk, posedge rst) begin
+    if( rst ) begin
+        scr1_hpos <= 0;
+        scr1_vpos <= 0;
+        scr2_hpos <= 0;
+        scr2_vpos <= 0;
+    end else if(cpu_cen) begin
+        if( GAME==0 ) begin
+            if( scr1hpos_cs && !RnW) scr1_hpos <= {6'd0, cpu_dout[9:0]};
+            if( scr1vpos_cs && !RnW) scr1_vpos <= {6'd0, cpu_dout[9:0]};
+            if( scr2hpos_cs && !RnW) scr2_hpos <= cpu_dout[8:0];
+            if( scr2vpos_cs && !RnW) scr2_vpos <= cpu_dout[8:0];
+        end else begin
+            scr2_hpos <= 0;
+            scr2_vpos <= 0;
+            if( scr1hpos_cs ) begin
+                if(!UDSWn) scr1_hpos[15:8] <= cpu_dout[15:8];
+                if(!LDSWn) scr1_hpos[ 7:0] <= cpu_dout[ 7:0];
+            end
+            if( scr1vpos_cs ) begin
+                if(!UDSWn) scr1_vpos[15:8] <= cpu_dout[15:8];
+                if(!LDSWn) scr1_vpos[ 7:0] <= cpu_dout[ 7:0];
+            end
+        end
+    end
+end
+
+// special registers
+always @(posedge clk) begin
+    if( rst ) begin
+        flip         <= 1'b0;
+        snd_latch    <= 8'b0;
+        snd_nmi_n    <= 1'b1;
+        scr_bank     <= 1'b0;
+    end else if(cpu_cen) begin
+        snd_nmi_n  <= 1'b1;
+        if( !UDSWn && io_cs)
+            case( { A[1]} )
+                1'b0: begin
+                    flip <= cpu_dout[GAME==0 ? 8 : 1];
+                    scr_bank  <= cpu_dout[2];
+                end
+                1'b1: begin
+                    // sound latch is updated here on the actual PCB
+                    // however, the main CPU software never writes a
+                    // value here. This is only used to trigger the NMI
+                    // in practice
+                    snd_latch <= GAME==0 ? cpu_dout[7:0] : // real PCB behaviour
+                                           cpu_dout[15:8];
+                    snd_nmi_n  <= 1'b0; // only Biocom ?
+                end
+            endcase
+        // Hack to capture the sound code that is sent to the MCU
+        // if( !LDSWn && work_A==13'h1ffc && ram_cs)
+        //     snd_hack <= cpu_dout[7:0]; // hack
+    end
+end
+
+reg [15:0] cabinet_input;
+
+always @(posedge clk) begin
+    if( GAME==0 ) // Bionic Commando:
+        cabinet_input = Aeff[1] ?
+            { dipsw_b, dipsw_a } :
+            { coin[0], coin[1],        // COINS
+              cab_1p[0], cab_1p[1],    // START
+              { joystick1[3:0], joystick1[4], joystick1[5]},   //  2 buttons
+              { joystick2[3:0], joystick2[4], joystick2[5]} };
+    else // Tiger Road:
+        case( A[2:1] )
+            2'b00: cabinet_input <= {
+                2'b11, joystick2[5:0],
+                2'b11, joystick1[5:0] };
+            2'b01: cabinet_input <=
+                { coin,
+                    service,
+                    2'b11,
+                    ~LVBL, cab_1p, 8'hff };
+            2'b10: cabinet_input <= { dipsw_a, dipsw_b };
+            default:;
+        endcase
+end
+
+/////////////////////////////////////////////////////
+// MCU DMA data output mux
+always @(posedge clk) begin
+    mcu_din <= cpu_din[7:0];
+end
+
+/////////////////////////////////////////////////////
+// Work RAM, 16kB
+wire [1:0] wram_dsn = {2{ram_cs}} & ~{UDSWn, LDSWn};
+wire       wmcu_wr  = mcu_wr_s & ram_cs;
+
+jtframe_dual_ram16 #(.AW(13)) u_work_ram (
+    .clk0   ( clk            ),
+    .clk1   ( clk            ),
+    // Port 0: CPU
+    .data0  ( cpu_dout       ),
+    .addr0  ( Aeff[13:1]     ),
+    .we0    ( wram_dsn       ),
+    .q0     ( wram_dout      ),
+    // Port 1: MCU
+    .data1  ( { 8'hff, mcu_dout_s} ) ,
+    .addr1  ( mcu_addr_s[13:1] ),
+    .we1    ( {1'b0,wmcu_wr} ),
+    .q1     (                )
+);
+
+/////////////////////////////////////////////////////
+// Object RAM, 4kB
+assign cpu_AB = Aeff[13:1];
+
+wire [10:0] oram_addr = blcnten ? obj_AB[11:1] : Aeff[11:1];
+wire [ 1:0] oram_dsn = {2{obj_cs}} & ~{UDSWn, LDSWn};
+wire        omcu_wr  = mcu_wr_s & obj_cs;
+
+jtframe_dual_ram16 #(.AW(11)) u_obj_ram (
+    .clk0   ( clk            ),
+    .clk1   ( clk        ),
+    // Port 0: CPU or Object DMA
+    .data0  ( cpu_dout       ),
+    .addr0  ( oram_addr      ),
+    .we0    ( oram_dsn       ),
+    .q0     ( oram_dout      ),
+    // Port 1: MCU
+    .data1  ( { 8'hff, mcu_dout_s} ) ,
+    .addr1  ( mcu_addr_s[11:1] ),
+    .we1    ( {1'b0,omcu_wr} ),
+    .q1     (                )
+);
+
+// Data bus input
+reg  [ 7:0] video_dout;
+wire        video_cs = char_cs | scr2_cs | scr1_cs;
+reg  [15:0] owram_dout;
+wire        owram_cs = obj_cs | ram_cs;
+
+always @(posedge clk) begin
+    owram_dout <= obj_cs ? oram_dout : wram_dout;
+    // GAME==0 uses this:
+    case( {scr2_cs, scr1_cs} )
+        2'b10:   video_dout <= scr2_dout;
+        2'b01:   video_dout <= scr1_dout;
+        default: video_dout <= char_dout[7:0];
+    endcase
+end
+
+always @(*)
+    case( {owram_cs, video_cs, io_cs} )
+        3'b100:  cpu_din = owram_dout;
+        3'b010:  cpu_din = GAME==1 ? char_dout : { 8'hff, video_dout };
+        3'b001:  cpu_din = cabinet_input;
+        default: cpu_din = rom_data;
+    endcase
+
+assign rom_addr = A[17:1];
+
+// DTACKn generation
+wire       inta_n;
+reg  [7:0] io_busy_cnt;
+wire       io_busy = io_busy_cnt[0];
+wire       bus_cs    = |{ rom_cs, scr1_cs, scr2_cs, char_cs };
+// io_busy must be bus_legit or it will halt the machine
+wire       bus_legit = |{scr1_busy, scr2_busy, char_busy, io_busy};
+wire       bus_busy  = |{ rom_cs & ~rom_ok, bus_legit };
+
+// DTACK is also held down during IO access in order to make
+// the NMI request to the Z80 CPU long enough
+// If the Z80 misses these requests it will not play any sound at all.
+always @(posedge clk, posedge rst) begin : io_busy_gen
+    reg       last_iocs;
+    if( rst ) begin
+        io_busy_cnt <= 8'd0;
+        last_iocs   <= 1'b0;
+    end else if(cpu_cen) begin
+        last_iocs <= io_cs;
+        if( io_cs && !last_iocs )
+            io_busy_cnt <= ~8'd0;
+        else
+            io_busy_cnt <= io_busy_cnt>>1;
+    end
+end
+
+wire DTACKn;
+
+localparam [3:0] DIV_NUM= GAME==0 ? 4'd1 : 4'd5;
+localparam [4:0] DIV_DEN= GAME==0 ? 5'd4 : 5'd24;
+
+jtframe_68kdtack_cen u_dtack( // cen = 12 or 10 MHz
+    .rst        ( rst        ),
+    .clk        ( clk        ),
+    .num        ( DIV_NUM    ),
+    .den        ( DIV_DEN    ),
+    .cpu_cen    ( cpu_cen    ),
+    .cpu_cenb   ( cpu_cenb   ),
+    .bus_cs     ( bus_cs     ),
+    .bus_busy   ( bus_busy   ),
+    .bus_legit  ( bus_legit  ),
+    .ASn        ( ASn        ),
+    .DSn        ({UDSn,LDSn} ),
+    .DTACKn     ( DTACKn     ),
+    .wait2      ( 1'b0       ),
+    .wait3      ( 1'b0       ),
+    // Unused
+    .fave       (            ),
+    .fworst     (            )
+);
+
+// interrupt generation
+reg        int1, int2;
+wire [2:0] FC;
+assign inta_n = ~&{ FC[2], FC[1], FC[0], ~ASn }; // interrupt ack.
+
+always @(posedge clk, posedge rst) begin : int_gen
+    reg last_LVBL, last_V256;
+    if( rst ) begin
+        int1 <= 1'b1;
+        int2 <= 1'b1;
+    end else begin
+        last_LVBL <= LVBL;
+        last_V256 <= V[8];
+
+        if( !inta_n ) begin
+            int1 <= 1'b1;
+            int2 <= 1'b1;
+        end
+        else if(dip_pause) begin
+            if( V[8] && !last_V256 ) int2 <= 1'b0;
+            if( !LVBL && last_LVBL ) int1 <= 1'b0;
+        end
+    end
+end
+
+// Original design uses HALT signal instead of BR/BG/BGACK triad
+// but fx68k does not support it, so HALT operation is implemented
+// through regular bus arbitrion
+
+wire [1:0] dev_br = { ~mcu_brn, obj_br };
+assign bus_ack = ~BGACKn;
+
+jtframe_68kdma #(.BW(2)) u_arbitration(
+    .clk        (  clk          ),
+    .rst        (  rst          ),
+    .cen        (  cpu_cenb     ),
+    .cpu_BRn    (  BRn          ),
+    .cpu_BGACKn (  BGACKn       ),
+    .cpu_BGn    (  BGn          ),
+    .cpu_ASn    (  ASn          ),
+    .cpu_DTACKn (  DTACKn       ),
+    .dev_br     (  dev_br       )
+);
+
+fx68k u_cpu(
+    .clk        ( clk         ),
+    .extReset   ( rst         ),
+    .pwrUp      ( rst         ),
+    .enPhi1     ( cpu_cen     ),
+    .enPhi2     ( cpu_cenb    ),
+    .HALTn      ( 1'b1        ),
+
+    // Buses
+    .eab        ( { ncA, A }  ),
+    .iEdb       ( cpu_din     ),
+    .oEdb       ( cpu_dout    ),
+
+
+    .eRWn       ( RnW         ),
+    .LDSn       ( LDSn        ),
+    .UDSn       ( UDSn        ),
+    .ASn        ( ASn         ),
+    .VPAn       ( inta_n      ),
+    .FC0        ( FC[0]       ),
+    .FC1        ( FC[1]       ),
+    .FC2        ( FC[2]       ),
+
+    .BERRn      ( BERRn       ),
+    // Bus arbitrion
+    .BRn        ( BRn         ),
+    .BGACKn     ( BGACKn      ),
+    .BGn        ( BGn         ),
+
+    .DTACKn     ( DTACKn      ),
+    .IPL0n      ( 1'b1        ),
+    .IPL1n      ( int1        ),
+    .IPL2n      ( int2        ),
+
+    // Unused
+    .oRESETn    (             ),
+    .oHALTEDn   (             ),
+    .VMAn       (             ),
+    .E          (             )
+);
+`else // NOMAIN
+    assign cpu_cen = 0;
+    assign cpu_cenb = 0;
+    assign cpu_dout = 0;
+    assign UDSWn = 1;
+    assign LDSWn = 1;
+    assign cpu_AB = 0;
+    assign oram_dout = 0;
+    assign RnW = 1;
+    assign bus_ack = 0;
+    assign col_uw = 0;
+    assign col_lw = 0;
+    assign rom_addr = 0;
+    initial begin
+        flip = 0;
+        snd_latch = 0;
+        snd_nmi_n = 1;
+        char_cs = 0;
+        scr1_cs = 0;
+        scr2_cs = 0;
+        scr1_hpos = `ifdef SIM_SCR1_HPOS `SIM_SCR1_HPOS `else 0 `endif;
+        scr1_vpos = `ifdef SIM_SCR1_VPOS `SIM_SCR1_VPOS `else 0 `endif;
+        scr2_hpos = `ifdef SIM_SCR2_HPOS `SIM_SCR2_HPOS `else 0 `endif;
+        scr2_vpos = `ifdef SIM_SCR2_VPOS `SIM_SCR2_VPOS `else 0 `endif;
+        scr_bank = `ifdef SIM_SCR_BANK `SIM_SCR_BANK `else 0 `endif;
+        OKOUT = 0;
+        mcu_din = 0;
+        mcu_DMAONn = 0;
+        rom_cs = 0;
+    end
+`endif
+endmodule

snapshots/jotego_jtcores_pr1100/cores/biocom/hdl/jtbiocom_mcu.v

@@ -0,0 +1,208 @@
+/*  This file is part of JTCORES.
+    JTCORES program is free software: you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation, either version 3 of the License, or
+    (at your option) any later version.
+
+    JTCORES program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with JTCORES.  If not, see <http://www.gnu.org/licenses/>.
+
+    Author: Jose Tejada Gomez. Twitter: @topapate
+    Version: 1.0
+    Date: 14-9-2019 */
+
+
+// Interface with sound CPU:
+// The sound CPU can read and write to the MCU at a fixed
+// address. The MCU only knows when data has been written to it
+// The MCU responds by writting an answer. The MCU cannot
+// know whether the sound CPU has read the value
+
+// Interface with main CPU:
+// The MCU takes control of the bus directly, including the bus decoder
+// Because it doesn't drive AB[19:17], which will remain high, the MCU
+// cannot access the PROM, OBJRAM, IO, scroll positions or char RAM
+// It can drive both scrolls, palette and work RAM because it drives
+// AB[16:14]. However, it doesn't have any bus arbitrion with the video
+// components, so it wouldn't be able to access video components
+// successfully. Thus, I am assuming that it only interacts with the
+// work RAM
+
+module jtbiocom_mcu(
+    input                rst,
+    input                rst_cpu,
+    input                clk_rom,
+    input                clk_cpu,
+    input                clk,
+    input                cen6a,       //  6   MHz
+    // Main CPU interface
+    (*keep*) input       DMAONn,
+    output       [ 7:0]  mcu_dout,
+    input        [ 7:0]  mcu_din,
+    output               mcu_wr,   // always write to low bytes
+    output       [16:1]  mcu_addr,
+    (*keep*) output      mcu_brn,   // RQBSQn
+    (*keep*) output      DMAn,
+    // Sound CPU interface
+    input        [ 7:0]  snd_dout,
+    output reg   [ 7:0]  snd_din,
+    input                snd_mcu_wr,
+    input                snd_mcu_rd,
+    // ROM programming
+    input        [11:0]  prog_addr,
+    input        [ 7:0]  prom_din,
+    input                prom_we
+);
+
+parameter SINC_XDATA=1;
+parameter ROMBIN="../../../../rom/biocom/ts.2f";
+`ifndef NOMCU
+wire [15:0] ext_addr;
+
+wire [ 7:0] p0_o, p1_o, p2_o, p3_o;
+reg         int0n, int1n;
+
+// interface with main CPU
+wire [7:0] p3_os;
+assign mcu_addr[13:9] = ~5'b0;
+assign { mcu_addr[16:14], mcu_addr[8:1] } = ext_addr[10:0];
+assign mcu_brn  = int0n;
+assign DMAn     = p3_os[5];
+reg    last_DMAONn;
+
+jtframe_sync #(.W(8)) u_p3sync(
+    .clk_in ( 1'b0      ),
+    .clk_out( clk_cpu   ),
+    .raw    ( p3_o      ),
+    .sync   ( p3_os     )
+);
+
+wire int0n_mcu;
+
+jtframe_sync #(.W(1)) u_intsync(
+    .clk_in ( 1'b0      ),
+    .clk_out( clk       ),
+    .raw    ( int0n     ),
+    .sync   ( int0n_mcu )
+);
+
+always @(posedge clk_cpu, posedge rst_cpu) begin
+    if( rst_cpu ) begin
+        int0n <= 1;
+        last_DMAONn <= 1;
+    end else begin
+        last_DMAONn <= DMAONn;
+        if(!p3_os[0]) // CLR
+            int0n <= 1;
+        else if(!p3_os[1])
+            int0n <= 0; // PR
+        else if( DMAONn && !last_DMAONn )
+            int0n <= 0;
+    end
+end
+
+// interface with sound CPU
+wire      int1_clrn = p3_o[4];
+
+reg [7:0] snd_dout_latch;
+reg       last_snd_mcu_wr, last_p3_6, last_snd_mcu_rd;
+wire      posedge_snd    = snd_mcu_wr && !last_snd_mcu_wr;
+wire      posedge_snd_rd = snd_mcu_rd && !last_snd_mcu_rd;
+wire      posedge_p3_6 = p3_o[6] && !last_p3_6;
+wire      snd_blank = p1_o == 8'hff;
+reg       snd_done;
+
+always @(posedge clk, posedge rst) begin
+    if( rst ) begin
+        snd_dout_latch  <= 8'd0;
+        int1n           <= 1;
+        last_snd_mcu_wr <= 1'b0;
+        snd_done        <= 1'b1;
+    end else begin
+        last_snd_mcu_wr <= snd_mcu_wr;
+        last_snd_mcu_rd <= snd_mcu_rd;
+        last_p3_6       <= p3_o[6];
+        if( posedge_snd )
+            snd_dout_latch <= snd_dout;
+        // interrupt line
+        if( !int1_clrn )
+            int1n <= 1;
+        else if( posedge_snd ) int1n <= 0;
+        // latch sound data
+        if( posedge_snd_rd ) snd_done <= 1'b1;
+        if( posedge_p3_6 && (snd_done || !snd_blank) ) begin
+            snd_done <= snd_blank;
+            snd_din  <= p1_o;
+        end
+    end
+end
+
+wire [7:0] mcu_din_s, x_dout;
+wire       x_wr;
+
+assign mcu_wr = x_wr | ~p3_o[6]; // wr pin
+assign mcu_dout = x_wr ? x_dout : p0_o;
+
+jtframe_sync #(.W(8)) u_sync(
+    .clk_in ( clk_cpu   ),
+    .clk_out( clk       ),
+    .raw    ( mcu_din   ),
+    .sync   ( mcu_din_s )
+);
+
+jtframe_8751mcu #(
+    .ROMBIN(ROMBIN),
+    .SYNC_XDATA(SINC_XDATA)
+) u_mcu(
+    .rst        ( rst       ),
+    .clk        ( clk       ),
+    .cen        ( cen6a     ),
+    // external memory: connected to main CPU
+    .x_din      ( mcu_din_s ),
+    .x_dout     ( x_dout    ),
+    .x_addr     ( ext_addr  ),
+    .x_wr       ( x_wr      ),
+    .x_acc      (           ),
+    // interrupts
+    .int0n      ( int0n_mcu ),
+    .int1n      ( int1n     ),
+    // Ports
+    .p0_i       ( 8'hff     ),
+    .p0_o       ( p0_o      ),
+
+    .p1_i       ( snd_dout_latch   ),
+    .p1_o       ( p1_o      ),
+
+    .p2_i       ( 8'hff     ),
+    .p2_o       ( p2_o      ),
+
+    .p3_i       ( 8'hff     ),
+    .p3_o       ( p3_o      ),
+
+    .clk_rom    ( clk_rom   ),
+    .prog_addr  ( prog_addr ),
+    .prom_din   ( prom_din  ),
+    .prom_we    ( prom_we   )
+);
+
+`ifdef SIMULATION
+always @(negedge int0n)
+    $display ("MCU: int0n edge - main CPU");
+
+always @(negedge int1n)
+    $display ("MCU: int1n edge - sound CPU");
+`endif
+`else // NOMCU
+    assign mcu_dout=0;
+    assign mcu_wr=0;
+    assign mcu_addr=0;
+    assign mcu_brn=1;
+    assign DMAn=1;
+    initial snd_din=0;
+`endif
+endmodule

snapshots/jotego_jtcores_pr1100/cores/biocom/hdl/jtbiocom_sound.v

@@ -0,0 +1,184 @@
+/*  This file is part of JTCORES.
+    JTCORES program is free software: you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation, either version 3 of the License, or
+    (at your option) any later version.
+
+    JTCORES program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with JTCORES.  If not, see <http://www.gnu.org/licenses/>.
+
+    Author: Jose Tejada Gomez. Twitter: @topapate
+    Version: 1.0
+    Date: 27-10-2017 */
+
+// This module is equivalent to the function
+// of CAPCOM's 85H001 package found in GunSmoke, GnG, etc.
+
+module jtbiocom_sound(
+    input           rst,
+    input           clk,
+    input           cen_fm,   // 14.31318/4   MHz ~ 3.5  MHz => 10/134 of 48MHz clock
+    input           cen_fm2,  // 14.31318/4/8 MHz ~ 1.75 MHz =>  5/134 of 48MHz clock
+    // Interface with main CPU
+    input   [7:0]   snd_latch,
+    input           nmi_n,
+    // Interface with MCU
+    input   [7:0]   snd_din,
+    output  [7:0]   snd_dout,
+    output          snd_mcu_wr,
+    output          snd_mcu_rd,
+    // ROM
+    output reg [14:0]  rom_addr,
+    output  reg     rom_cs,
+    input   [ 7:0]  rom_data,
+    input           rom_ok,
+
+    // Sound output
+    output  signed [15:0] fm_l,
+    output  signed [15:0] fm_r
+);
+
+parameter LAYOUT  = 3, // 9 for SF
+          RECOVERY= 0;
+`ifndef NOSOUND
+
+wire [15:0] A;
+reg         fm_cs, latch_cs, ram_cs, mcu_cs;
+wire        mreq_n, rfsh_n, int_n, iorq_n, m1_n, nmiff_n;
+wire        WRn, rd_n, wr_n, fm_csn, RAM_we;
+wire [ 7:0] ram_dout, dout, fm_dout;
+reg  [ 7:0] din;
+reg         rom2_ok;
+
+assign fm_csn     = ~fm_cs;
+assign RAM_we     = ram_cs && !WRn;
+assign snd_mcu_wr = mcu_cs && !WRn;
+assign snd_mcu_rd = mcu_cs &&  WRn;
+
+always @(posedge clk) begin
+    rom_cs   <= 1'b0;
+    ram_cs   <= 1'b0;
+    latch_cs <= 1'b0;
+    fm_cs    <= 1'b0;
+    mcu_cs   <= 1'b0;
+    rom2_ok  <= rom_ok;
+    if(!mreq_n) begin
+        if( LAYOUT==9 ) begin // Stret Fighter
+             casez( A[15:13] )
+                3'b0??: begin
+                    rom_cs <= 1;
+                    rom_addr <= A[14:0];
+                end
+                3'b110: begin
+                    ram_cs   <= !A[11];
+                    latch_cs <=  A[11];
+                end
+                3'b111: fm_cs <= 1;
+                default:;
+            endcase
+        end else begin // Bionic Commando
+             casez( A[15:13] )
+                3'b0??: begin
+                    rom_cs   <= 1'b1;
+                    rom_addr <= A[14:0];
+                end
+                3'b100: fm_cs    <= 1'b1;
+                3'b101: mcu_cs   <= 1'b1;
+                3'b110: ram_cs   <= 1'b1;
+                3'b111: latch_cs <= 1'b1;
+            endcase
+        end
+    end
+end
+
+assign WRn      = wr_n | mreq_n;
+assign snd_dout = dout;
+
+always @(posedge clk, posedge rst) begin
+    if( rst ) begin
+        din <= 8'hff;
+    end else begin
+        din <= rom_cs   ? rom_data : (
+               fm_cs    ? fm_dout   : (
+               latch_cs ? (LAYOUT==9 ? snd_latch : snd_din) : (
+               mcu_cs   ? snd_din   : (
+               ram_cs   ? ram_dout  :
+               8'hff ))));
+    end
+end
+
+jtframe_ram #(.AW(11)) u_ram(
+    .clk    ( clk      ),
+    .cen    ( 1'b1     ),
+    .data   ( dout     ),
+    .addr   ( A[10:0]  ),
+    .we     ( RAM_we   ),
+    .q      ( ram_dout )
+);
+
+
+jtframe_z80_romwait #(.RECOVERY(RECOVERY)) u_cpu(
+    .rst_n      ( ~rst        ),
+    .clk        ( clk         ),
+    .cen        ( cen_fm      ),
+    .int_n      ( int_n       ),
+    .nmi_n      ( nmi_n       ),
+    .busrq_n    ( 1'b1        ),
+    .m1_n       ( m1_n        ),
+    .mreq_n     ( mreq_n      ),
+    .iorq_n     ( iorq_n      ),
+    .rd_n       ( rd_n        ),
+    .wr_n       ( wr_n        ),
+    .rfsh_n     ( rfsh_n      ),
+    .halt_n     (             ),
+    .busak_n    (             ),
+    .A          ( A           ),
+    .din        ( din         ),
+    .dout       ( dout        ),
+    // manage access to ROM data from SDRAM
+    .rom_cs     ( rom_cs      ),
+    .rom_ok     ( rom2_ok     ),
+    // unused
+    .cpu_cen    (             )
+);
+
+jt51 u_jt51(
+    .rst        ( rst       ), // reset
+    .clk        ( clk       ), // main clock
+    .cen        ( cen_fm    ),
+    .cen_p1     ( cen_fm2   ),
+    .cs_n       ( fm_csn    ), // chip select
+    .wr_n       ( WRn       ), // write
+    .a0         ( A[0]      ),
+    .din        ( dout      ), // data in
+    .dout       ( fm_dout   ), // data out
+    .ct1        (           ),
+    .ct2        (           ),
+    .irq_n      ( int_n     ),
+    // Low resolution output (same as real chip)
+    .sample     (           ),
+    .left       (           ),
+    .right      (           ),
+    // Full resolution output
+    .xleft      ( fm_l      ),
+    .xright     ( fm_r      )
+);
+
+`else // NOSOUND
+    assign snd_dout   = 0;
+    assign snd_mcu_wr = 0;
+    assign snd_mcu_rd = 0;
+    assign fm_l       = 0;
+    assign fm_r       = 0;
+    initial begin
+        rom_addr = 0;
+        rom_cs = 0;
+    end
+`endif
+
+endmodule

snapshots/jotego_jtcores_pr1100/cores/biocom/hdl/jtbiocom_video.v

@@ -0,0 +1,315 @@
+/*  This file is part of JTCORES.
+    JTCORES program is free software: you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation, either version 3 of the License, or
+    (at your option) any later version.
+
+    JTCORES program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with JTCORES.  If not, see <http://www.gnu.org/licenses/>.
+
+    Author: Jose Tejada Gomez. Twitter: @topapate
+    Version: 1.0
+    Date: 15-9-2019 */
+
+module jtbiocom_video(
+    input               rst,
+    input               clk,
+    input               cen12,
+    input               cen8,
+    input               cen6,
+    input               cpu_cen,
+    input       [13:1]  cpu_AB,
+    input       [ 8:0]  V,
+    input       [ 8:0]  H,
+    input               RnW,
+    input               flip,
+    input       [15:0]  cpu_dout,
+    // CHAR
+    input               char_cs,
+    output      [ 7:0]  char_dout,
+    input               char_ok,
+    output              char_busy,
+    output      [12:0]  char_addr,
+    input       [15:0]  char_data,
+    // SCROLL 1
+    input               scr1_cs,
+    output      [ 7:0]  scr1_dout,
+    output      [16:0]  scr1_addr,
+    input       [15:0]  scr1_data,
+    input               scr1_ok,
+    output              scr1_busy,
+    input       [ 9:0]  scr1_hpos,
+    input       [ 9:0]  scr1_vpos,
+    // SCROLL 2
+    input               scr2_cs,
+    output      [ 7:0]  scr2_dout,
+    output      [14:0]  scr2_addr,
+    input       [15:0]  scr2_data,
+    input               scr2_ok,
+    output              scr2_busy,
+    input       [ 8:0]  scr2_hpos,
+    input       [ 8:0]  scr2_vpos,
+    // OBJ
+    input               HINIT,
+    output      [13:1]  obj_AB,
+    input       [11:0]  oram_dout,   // only 12 bits are read
+    input               OKOUT,
+    output              bus_req, // Request bus
+    input               bus_ack, // bus acknowledge
+    output              blcnten,    // bus line counter enable
+    output      [17:2]  obj_addr,
+    input       [31:0]  obj_data,
+    input               obj_ok,
+    output              obj_cs,
+    // Color Mix
+    input               HS,
+    input               preLHBL,
+    input               preLVBL,
+    input               LVBL_obj,
+    input               LHBL_obj,
+    output              LHBL,
+    output              LVBL,
+    input               col_uw,
+    input               col_lw,
+    input       [3:0]   gfx_en,
+    // Priority PROM
+    input       [7:0]   prog_addr,
+    input               prom_prio_we,
+    input       [3:0]   prom_din,
+    // Pixel output: 5 bits per colour!
+    output      [4:0]   red,
+    output      [4:0]   green,
+    output      [4:0]   blue
+);
+
+// parameters from jtgng_colmix:
+parameter SCRWIN        = 1,
+          PALETTE_PROM  = 0,
+          PALETTE_RED   = "",
+          PALETTE_GREEN = "",
+          PALETTE_BLUE  = "";
+parameter [1:0] OBJ_PAL = 2'b01; // 01 for GnG, 10 for Commando
+    // These two bits mark the region of the palette RAM/PROM where
+    // palettes for objects are stored
+
+localparam CHAR_OFFSET = 9'd5;
+localparam SCR1_OFFSET = 9'd1;
+localparam SCR2_OFFSET = 9'd1;
+localparam OBJ_DLY     = 3;
+
+wire [5:0] char_pxl;
+wire [7:0] obj_pxl;
+wire [3:0] scr1_col, scr2_col;
+wire [3:0] scr1_pal, scr2_pal;
+wire [3:0] cc;
+
+reg [7:0] scr1_pxl, scr2_pxl;
+
+always @(posedge clk) if(cen6) begin
+    scr1_pxl <= { scr1_pal, scr1_col };
+    scr2_pxl <= { scr2_pal, scr2_col };
+end
+
+jtgng_char #(.HOFFSET(CHAR_OFFSET)) u_char (
+    .clk        ( clk           ),
+    .pxl_cen    ( cen6          ),
+    .AB         ( cpu_AB[11:1]  ),
+    .V          ( V[7:0]        ),
+    .H          ( H[7:0]        ),
+    .flip       ( flip          ),
+    .din        ( cpu_dout[7:0] ),
+    .dout       ( char_dout     ),
+    // Bus arbitrion
+    .char_cs    ( char_cs       ),
+    .wr_n       ( RnW           ),
+    .busy       ( char_busy     ),
+    // ROM
+    .char_addr  ( char_addr     ),
+    .rom_data   ( char_data     ),
+    .rom_ok     ( char_ok       ),
+    // Pixel output
+    .char_on    ( 1'b1          ),
+    .char_pxl   ( char_pxl      ),
+    // unused
+    .dseln      ( 2'b11         ),
+    .prog_addr  (               ),
+    .prog_din   (               ),
+    .prom_we    (               )
+);
+
+`ifdef NOSCR
+    `define NOSCR1
+    `define NOSCR2
+`endif
+
+`ifndef NOSCR1
+jtgng_scroll #(
+    .ROM_AW     ( 17            ),
+    .SCANW      ( 12            ),
+    .POSW       ( 10            ),
+    .HOFFSET    ( SCR1_OFFSET   ),
+    .TILE4      (  1            ), // 4bpp
+    .LAYOUT     (  1            ),
+    .SIMID      (  1            ))
+u_scroll1 (
+    .clk        ( clk           ),
+    .pxl_cen    ( cen6          ),
+    // screen position
+    .H          ( H             ),
+    .V          ( V[7:0]        ),
+    .hpos       ( scr1_hpos     ),
+    .vpos       ( scr1_vpos     ),
+    .flip       ( flip          ),
+    // bus arbitrion
+    .Asel       ( cpu_AB[1]     ),
+    .AB         ( cpu_AB[13:2]  ),
+    .scr_cs     ( scr1_cs       ),
+    .din        ( cpu_dout[7:0] ),
+    .dout       ( scr1_dout     ),
+    .wr_n       ( RnW           ),
+    .busy       ( scr1_busy     ),
+    // ROM
+    .scr_addr   ( scr1_addr     ),
+    .rom_data   ( scr1_data     ),
+    .rom_ok     ( scr1_ok       ),
+    // pixel output
+    .scr_col    ( scr1_col      ),
+    .scr_pal    ( scr1_pal      )
+);
+`else
+assign scr1_busy  = 0;
+assign scr1_col   = ~4'd0;
+assign scr1_pal   = ~4'd0;
+assign scr1_addr  = 0;
+assign scr1_dout  = 0;
+`endif
+
+
+
+`ifndef NOSCR2
+jtgng_scroll #(
+    .ROM_AW     ( 15            ),
+    .SCANW      ( 12            ),
+    .HOFFSET    ( SCR2_OFFSET   ),
+    .TILE4      (  1            ), // 4bpp
+    .LAYOUT     (  2            ),
+    .SIMID      (  2            ))
+u_scroll2 (
+    .clk        ( clk           ),
+    .pxl_cen    ( cen6          ),
+    // screen position
+    .H          ( H             ),
+    .V          ( V[7:0]        ),
+    .hpos       ( scr2_hpos     ),
+    .vpos       ( scr2_vpos     ),
+    .flip       ( flip          ),
+    // bus arbitrion
+    .Asel       ( cpu_AB[1]     ),
+    .AB         ( cpu_AB[13:2]  ),
+    .scr_cs     ( scr2_cs       ),
+    .din        ( cpu_dout[7:0] ),
+    .dout       ( scr2_dout     ),
+    .wr_n       ( RnW           ),
+    .busy       ( scr2_busy     ),
+    // ROM
+    .scr_addr   ( scr2_addr     ),
+    .rom_data   ( scr2_data     ),
+    .rom_ok     ( scr2_ok       ),
+    // pixel output
+    .scr_col    ( scr2_col      ),
+    .scr_pal    ( scr2_pal      )
+);
+`else
+assign scr2_busy  = 0;
+assign scr2_col   = ~4'd0;
+assign scr2_pal   = ~4'd0;
+assign scr2_addr  = 0;
+assign scr2_dout  = 0;
+`endif
+
+/* verilator tracing_off */
+jttora_obj #( // 160 objects scanned. Max 31 objects drawn per line
+    .VINV       (  0         ),
+    .HOFF       ( 9'h8       ),
+    .VOFF       ( 9'h1fe     ),
+    .ROM_AW     ( 18         ),
+    .DMA_AW     ( 10         ),
+    .DMA_DW     ( 12         ))
+u_obj (
+    .rst        ( rst         ),
+    .clk        ( clk         ),
+    .dma_cen    ( cen8        ),
+    .pxl_cen    ( cen6        ),
+    // screen
+    .hs         ( HS          ),
+    .LVBL       ( LVBL        ),
+    .vdump      ( V           ),
+    .hdump      ( H           ),
+    .flip       ( flip        ),
+    // CPU bus
+    .AB         ( obj_AB[10:1]),
+    .DB         ( oram_dout   ),
+    // shared bus
+    .OKOUT      ( OKOUT       ),
+    .bus_req    ( bus_req     ),
+    .bus_ack    ( bus_ack     ),
+    .blen       ( blcnten     ),
+    // SDRAM interface
+    .rom_addr   ( obj_addr    ),
+    .rom_data   ( obj_data    ),
+    .rom_cs     ( obj_cs      ),
+    .rom_ok     ( obj_ok      ),
+    // pixel data
+    .pxl        ( obj_pxl     ),
+    .debug_bus  ( 8'd0        )
+);
+
+assign obj_AB[13:11] = 3'b111;
+/* verilator tracing_on */
+`ifndef NOCOLMIX
+jtbiocom_colmix u_colmix (
+    .rst          ( rst           ),
+    .clk          ( clk           ),
+    .cen6         ( cen6          ),
+    .cpu_cen      ( cpu_cen       ),
+
+    .char_pxl     ( char_pxl      ),
+    .scr1_pxl     ( scr1_pxl      ),
+    .scr2_pxl     ( scr2_pxl      ),
+    .obj_pxl      ( obj_pxl       ),
+    .LVBL         ( LVBL          ),
+    .LHBL         ( LHBL          ),
+    .preLHBL      ( preLHBL       ),
+    .preLVBL      ( preLVBL       ),
+
+    // PROMs
+    .prog_addr    ( prog_addr     ),
+    .prom_prio_we ( prom_prio_we  ),
+    .prom_din     ( prom_din      ),
+
+    // DEBUG
+    .gfx_en       ( gfx_en        ),
+
+    // CPU interface
+    .AB           ( cpu_AB[10:1]  ),
+    .col_uw       ( col_uw        ),
+    .col_lw       ( col_lw        ),
+    .DB           ( cpu_dout      ),
+
+    // colour output
+    .red          ( red           ),
+    .green        ( green         ),
+    .blue         ( blue          )
+);
+`else
+assign  red = 4'd0;
+assign blue = 4'd0;
+assign green= 4'd0;
+`endif
+
+endmodule

snapshots/jotego_jtcores_pr1100/cores/biocom/ver/game/biocom.mame

@@ -0,0 +1,5 @@
+save biocom_obj.bin,   0xfe0800,0x500
+save biocom_char.bin,  0xfec000,0x1000
+save biocom_scr1.bin,  0xff0000,0x4000
+save biocom_scr2.bin,  0xff4000,0x4000
+save biocom_pal.bin,   0xff8000,0x800

snapshots/jotego_jtcores_pr1100/cores/biocom/ver/game/biocom_wp.mame

@@ -0,0 +1,4 @@
+wpset 0xfe8010,2,w,1,{printf "Write SCR1 HPOS=%04X\n",wpdata;g}
+wpset 0xfe8012,2,w,1,{printf "Write SCR1 VPOS=%04X\n",wpdata;g}
+wpset 0xfe8014,2,w,1,{printf "Write SCR2 HPOS=%04X\n",wpdata;g}
+wpset 0xfe8016,2,w,1,{printf "Write SCR2 VPOS=%04X\n",wpdata;g}

snapshots/jotego_jtcores_pr1100/cores/biocom/ver/game/gomcu.sh

@@ -0,0 +1,4 @@
+#/bin/bash
+cp sim_inputs_game.hex sim_inputs.hex || exit $?
+go.sh -nosnd -video 190 -w -d DUMP_START=139 -inputs
+#go.sh -nosnd -video 19 -w -inputs

snapshots/jotego_jtcores_pr1100/cores/biocom/ver/game/mame2char.sh

@@ -0,0 +1,8 @@
+#!/bin/bash
+# Convert character MAME memory dump to input files
+if [ ! -e jtutil drop1 ]; then
+    g++ jtutil drop1.cc -o jtutil drop1
+fi
+
+dd if=biocom_char.bin count=4        | jtutil drop1 > char_lower.bin 
+dd if=biocom_char.bin count=4 skip=4 | jtutil drop1 > char_upper.bin 

snapshots/jotego_jtcores_pr1100/cores/biocom/ver/game/mame2sim.sh

@@ -0,0 +1,73 @@
+#!/bin/bash
+
+# Use MAME debugger command files:
+#   biocom.cmd and biocom_wp.cmd
+#   to obtain the input files and scroll position bytes for the sim
+
+SCR1HPOS=0000
+SCR2HPOS=0000
+SCR1VPOS=0300
+SCR2VPOS=0100
+
+while [ $# -gt 0 ]; do
+case "$1" in
+    -h1|-scr1hpos)
+        shift
+        SCR1HPOS=$1;;
+    -h2|-scr2hpos)
+        shift
+        SCR2HPOS=$1;;
+    -v1|-scr1vpos)
+        shift
+        SCR1VPOS=$1;;
+    -v2|-scr2vpos)
+        shift
+        SCR2VPOS=$1;;
+    -help)
+        cat <<EOF
+-h1 or -scr1hpos: indicate horizontal scroll 1 in hexadecimal
+-h2 or -scr2hpos: indicate horizontal scroll 2 in hexadecimal
+-v1 or -scr1vpos: indicate vertical   scroll 1 in hexadecimal
+-v2 or -scr2vpos: indicate vertical   scroll 2 in hexadecimal
+EOF
+        exit 0;;
+    *) echo "Unknown option $1. Use -help to see the list of options"; exit 1;;        
+esac
+shift
+done
+
+# Characters:
+# Convert character MAME memory dump to input files
+if [ ! -e jtutil drop1 ]; then
+    g++ jtutil drop1.cc -o jtutil drop1 || exit 1
+fi
+
+dd if=biocom_char.bin count=4        | jtutil drop1 > char_lower.bin 
+dd if=biocom_char.bin count=4 skip=4 | jtutil drop1 > char_upper.bin 
+
+# Palette 
+if [ ! -e pal_bin2hex ]; then
+    g++ pal_bin2hex.cc -o pal_bin2hex || exit 1
+fi
+
+pal_bin2hex < biocom_pal.bin
+
+# Objects
+cp -f biocom_obj.bin objdma.bin
+
+# Scroll 1
+jtutil drop1 < biocom_scr1.bin | jtutil drop1    > scr1_upper.bin
+jtutil drop1 < biocom_scr1.bin | jtutil drop1 -l > scr1_lower.bin
+
+# Scroll 2
+jtutil drop1 < biocom_scr2.bin | jtutil drop1    > scr2_upper.bin
+jtutil drop1 < biocom_scr2.bin | jtutil drop1 -l > scr2_lower.bin
+
+go.sh -d NOSOUND -d NOMAIN -d NOMCU -video 2 \
+    -d JTCHAR_UPPER_SIMFILE=',.simfile({SIMID,"_upper.bin"})' \
+    -d JTCHAR_LOWER_SIMFILE=',.simfile({SIMID,"_lower.bin"})' \
+    -d SIM_SCR1_VPOS=10\'h$SCR1VPOS \
+    -d SIM_SCR2_VPOS=9\'h$SCR2VPOS \
+    -d SIM_SCR1_HPOS=10\'h0$SCR1HPOS \
+    -d SIM_SCR2_HPOS=10\'h0$SCR2HPOS \
+    -deep $*

snapshots/jotego_jtcores_pr1100/cores/biocom/ver/game/pal_bin2hex.cc

@@ -0,0 +1,21 @@
+#include <iostream>
+#include <fstream>
+
+using namespace std;
+
+// convert palette from MAME save command in debugger
+// input binary palette file as stdin
+
+int main() {
+    ofstream fr("palrg.hex");
+    ofstream fgb("palbb.hex");
+    char buf[2];
+    cin.read(buf,2);
+    while( !cin.eof() ) {        
+        int v = 0xff&(int)buf[0];
+        fr << hex << v << '\n';
+        v = 0xff&(int)buf[1];
+        fgb << hex << v << '\n';
+        cin.read(buf,2);
+    }
+}

snapshots/jotego_jtcores_pr1100/cores/biocom/ver/game/simload.sh

@@ -0,0 +1,3 @@
+#!/bin/bash
+
+jtsim -nosnd -d NOMAIN -d NOMCU -setname bionicc -load $*

snapshots/jotego_jtcores_pr1100/cores/biocom/ver/prom_we/go.sh

@@ -0,0 +1,6 @@
+#!/bin/bash
+
+iverilog test.v ../../hdl/jtbiocom_prom_we.v \
+    -D ROM_LEN=22\'hF1100 -D PROM_W=2 -D SIMULATION \
+    -o sim \
+    && sim -lxt

snapshots/jotego_jtcores_pr1100/cores/biocom/ver/prom_we/test.v

@@ -0,0 +1,56 @@
+`timescale 1ns/1ps
+
+module test;
+
+reg         clk, downloading=1'b1;
+reg  [21:0] ioctl_addr=22'd0;
+reg  [ 7:0] ioctl_dout= 8'd0;
+reg         ioctl_wr;
+
+wire [21:0] prog_addr;
+wire [ 7:0] prog_data;
+wire [ 1:0] prog_mask;
+wire        prog_we;
+wire [`PROM_W-1:0] prom_we;
+
+jtbiocom_prom_we
+    u_uut(
+    .clk         (  clk          ),
+    .downloading (  downloading  ),
+    .ioctl_addr  (  ioctl_addr   ),
+    .ioctl_dout  (  ioctl_dout   ),
+    .ioctl_wr    (  ioctl_wr     ),
+    .prog_addr   (  prog_addr    ),
+    .prog_data   (  prog_data    ),
+    .prog_mask   (  prog_mask    ),
+    .prog_we     (  prog_we      ),
+    .prom_we     (  prom_we      )
+);
+
+initial begin
+    clk = 1'b0;    
+    forever #10 clk = ~clk;
+end
+
+reg [1:0] cnt=2'b0;
+
+always @(posedge clk) begin
+    cnt      <= cnt+2'd1;
+    ioctl_wr <= 1'b0;
+    if( ioctl_addr < `ROM_LEN && cnt==2'b11 ) begin
+        ioctl_addr <= ioctl_addr + 22'd1;
+        ioctl_dout <= ioctl_dout+8'd1;
+        ioctl_wr   <= 1'b1;
+    end else if( ioctl_addr >= `ROM_LEN ) begin
+        downloading <= 1'b0;        
+        #100 $finish;
+    end
+end
+
+initial begin
+    $dumpfile("test.lxt");
+    $dumpvars(0,test);
+    $dumpon;    
+end
+
+endmodule

snapshots/jotego_jtcores_pr1100/cores/btiger/cfg/files.yaml

@@ -0,0 +1,32 @@
+btiger:
+  - get:
+    - jtbtiger_main.v
+    - jtbtiger_game.v
+    - jtbtiger_video.v
+    - jtbtiger_mcu.v
+    - jtbtiger_colmix.v
+    - jtbtiger_scroll.v
+gng:
+  - get:
+    - jtgng_video.v
+    - jtgng_video.yaml
+    - jtgng_sound.yaml
+    - jtgng_dual_ram.v
+    - jtgng_colmix.v
+jtframe:
+  - from: clocking
+    get:
+      - jtframe_cen48.v
+  - from: cpu
+    get:
+      - jtframe_z80.yaml
+      - jtframe_8751.yaml
+  - from: video
+    get:
+      - jtframe_blank.v
+  - from: ram
+    get:
+      - jtframe_ram.v
+jt12:
+  - get:
+    - jt12_rst.v

snapshots/jotego_jtcores_pr1100/cores/btiger/cfg/macros.def

@@ -0,0 +1,25 @@
+[*]
+CORENAME=JTBTIGER
+JTFRAME_BUTTONS=2
+JTFRAME_WIDTH=256
+JTFRAME_HEIGHT=224
+# 24 MHz used in MCU to avoid timing errors
+JTFRAME_CLK24
+JTFRAME_CREDITS_PAGES=1
+
+# SDRAM
+JTFRAME_BA1_START=0x48000
+CHAR_START=0x50000
+JTFRAME_BA2_START=0x58000
+JTFRAME_BA3_START=0x98000
+JTFRAME_PROM_START=0xD8000
+
+# OSD options
+JOIN_JOYSTICKS
+
+[sidi]
+-JTFRAME_CREDITS
+
+[mister]
+JTFRAME_ARX=5
+JTFRAME_ARY=4

snapshots/jotego_jtcores_pr1100/cores/btiger/cfg/mame2mra.toml

@@ -0,0 +1,33 @@
+[global]
+author=["jotego"]
+
+[parse]
+sourcefile=[ "blktiger.cpp" ]
+skip.bootlegs=true
+
+[Audio]
+volume = [
+    { machine="blktiger", value=0x25 },
+]
+
+[buttons]
+names=[
+    { names="Attack,Jump" }
+]
+
+[ROM]
+regions=[
+    { name="maincpu", no_offset=true, sequence=[1,2,3,4,0]                     },
+    { name="audiocpu", start="JTFRAME_BA1_START"                               },
+    { name="chars",    start="CHAR_START", reverse=true, no_offset=true        },
+    { name="tiles",    start="JTFRAME_BA2_START", sequence=[2,0,3,1], width=16 },
+    # { name="sprites",  start="JTFRAME_BA3_START", sequence=[0,2,1,3], width=16 },
+    { name="sprites",  start="JTFRAME_BA3_START", sequence=[2,0,3,1], width=16 },
+    { name="mcu",      start="JTFRAME_PROM_START"                              },
+    { name="proms"                                                             }
+]
+
+order=[
+    "maincpu", "audiocpu", "chars",
+    "tiles", "sprites", "mcu", "proms"
+]

snapshots/jotego_jtcores_pr1100/cores/btiger/cfg/mem.yaml

@@ -0,0 +1,36 @@
+params:
+  - { name: CHAR_OFFSET, value: "(`CHAR_START-`JTFRAME_BA1_START)>>1" }
+audio:
+  missing_info: true # unknown value for PSG resistors, assuming same filtering as gng
+  channels:
+    - { name: psg0, module: jt03_psg, rsum: 68k }
+    - { name: psg1, module: jt03_psg, rsum: 68k }
+    - { name: fm0,  module: jt03_fm,  rsum: 47k, rc: [{ r: 1rout,  c: 1n }]}
+    - { name: fm1,  module: jt03_fm,  rsum: 47k, rc: [{ r: 1rout,  c: 1n }]}
+download:
+  post_addr: true
+sdram:
+  banks:
+    - buses:
+      - name: main
+        addr_width: 19
+        data_width: 8
+    - buses:
+      - name: snd
+        addr_width: 15
+        data_width: 8
+      - name: char
+        addr_width: 15
+        data_width: 16
+        cs: LVBL
+        offset: CHAR_OFFSET
+    - buses:
+      - name: scr
+        addr_width: 18
+        data_width: 16
+        cs: LVBL
+    - buses:
+      - name: obj
+        addr_width: 18
+        data_width: 16
+        cs: LVBL

snapshots/jotego_jtcores_pr1100/cores/btiger/cfg/msg

@@ -0,0 +1,25 @@
+     BLACK TIGER/DRAGON         
+    BROUGHT TO YOU BY JOTEGO.   
+  HTTP://PATREON.COM/JOTEGO
+
+       6th January 2020
+
+    SCRALINGS     SUVERMAN
+
+      ARCADE EXPRESS          
+FREDERIC MAHE  JO TOMIYORI
+BRIAN SALLEE   PHILLIP MCMAHON
+DUSTIN HUBBARD DANIEL BAUZA
+                                
+  Andrew Moore   Andyways
+  Don Gafford    J. Slowfret
+  Kyle Good      Leslie Law
+  M. Astudillo   Mary Marshall
+  Matthew Young  Oliver Jaksch
+  Blackstar      Oscar Laguna
+  Roman Buser    Ryan Fig
+  Steve Suavek   Steve Wilson
+  Toby Boreham   Xzarian
+  Xzarian        Sembiance
+ultrarobotninja William Clemens
+         Victor Gomariz

snapshots/jotego_jtcores_pr1100/cores/btiger/doc/blktiger.cpp

@@ -0,0 +1,1086 @@
+// license:BSD-3-Clause
+// copyright-holders:Paul Leaman
+/***************************************************************************
+
+    Black Tiger
+
+    Driver provided by Paul Leaman
+
+    Thanks to Ishmair for providing information about the screen
+    layout on level 3.
+
+    Notes:
+    - sprites/tile priority is a guess. I didn't find a PROM that would simply
+      translate to the scheme I implemented.
+
+***************************************************************************
+
+Black Tiger / Black Dragon (Capcom, 1987)
+Hardware info by Guru
+
+Note boards connect solder side to solder side and parts face outwards
+on both boards.
+
+Top Board
+---------
+
+CAPCOM
+87118-A-X1
+|-------------------------------------------------------------------------|
+|            VOL                          |------------------| BD_06.1L   |
+|  HA13001         YM3014   YM2203        |138  138   21  08 |            |
+|                                         |2kB  174 367 74 74| 3.579545MHz|
+|        M5224     YM3014   YM2203        |Z80           139 |    JP7..12 |
+|                                         |---SOUND_MODULE---|            |
+|                                                                         |
+|                 5814             4364                                   |
+|J                                                       BD.6K            |
+|A                               BD_U_01A.5E                              |
+|M                5814                                             24MHz  |
+|M                               BD_U_02A.6E                              |
+|A                                                                        |
+|                                                 BD01.8J                 |
+|                                BD_U_03A.8E                              |
+|                 JP1..6                          BD02.9J                 |
+|         SW2                    BD_U_04A.9E                              |
+|                                                                         |
+|                                BD_U_05A.10E            BD03.11K         |
+|         SW1                                               BD04.11L      |
+|                                  Z80                                    |
+|--------|--------------|-------------------------|--------------|--------|
+         |--------------|                         |--------------|
+Notes:
+               Z80 - Zilog Z084006PSC CPU (main CPU). Clock input 6MHz [24/4]
+Z80 (sound module) - Zilog Z084004PSC CPU (sound CPU). Clock input 3.579545MHz
+             BD.6K - Intel D8751H-8 Microcontroller with internal 4kBx8-bit EPROM and 128 bytes internal RAM. Clock input 8.000MHz [24/3]
+            YM2203 - Yamaha YM2203 FM Operator Type-N (OPN) sound chip. Clock input 3.579545MHz (both)
+            YM3014 - Yamaha YM3014B Serial Input Floating D/A Converter. Clock input 1.193181667MHz [3.579545/3] (both)
+      SOUND_MODULE - Contains commonly available parts.... logic, Z80A and 2kBx8-bit SRAM
+            JP1..6 - 0-ohm jumpers. JP1 & JP6 are shorted, others are open
+           JP7..12 - 0-ohm jumpers. JP10 & JP11 are shorted, others are open
+           HA13001 - Hitachi HA13001 5.5W Dual / 17.5W BTL Audio Power Amplifier
+             SW1/2 - 8-position DIP switch
+             M5224 - Mitsubishi M5224 Quad Operational Amplifier (compatible with LM324)
+               2kB - 2kBx8-bit SRAM (inside sound module). Compatible with 6116, 2018, 5814, 4016 etc.
+              5814 - Sony CXK5814 2kBx8-bit SRAM (color RAM)
+              4364 - NEC D4364 8kBx8-bit SRAM (main program RAM)
+           BD01.8J - Signetics 82S129 bipolar PROM. When removed: No backgrounds and no sprites. Text layer/characters ok.
+           BD02.9J - Signetics 82S129 bipolar PROM. When removed: Affects sprites, sometimes they are partial or disappear under tiles.
+          BD03.11K - Signetics 82S129 bipolar PROM. Timing. When removed: Black screen, no syncs, game plays blind.
+          BD04.11L - Signetics 82S129 bipolar PROM. Timing. When removed: No bootup, shows only static garbage
+          BD_06.1L - Hitachi HN27256 32kBx8-bit OTP EPROM (sound program)
+       BD_U_01A.5E -  \
+       BD_U_02A.6E -   \ 27C512 EPROM or OTP EPROM (main program)
+       BD_U_03A.8E -   /
+       BD_U_04A.9E -  /
+      BD_U_05A.10E - /
+             VSync - 59.6373Hz
+             HSync - 15.6250kHz
+
+
+Bottom Board
+------------
+
+CAPCOM
+87118-B-X1
+         |--------------|                         |--------------|
+|--------|--------------|-------------------------|--------------|--------|
+|                                                                86S100   |
+|         |-------|                                                       |
+|         |CAPCOM |                                           BD_U_15.2N  |
+|         |86S105 |                                                       |
+|         |RJ5C39 |             2018           2018                       |
+|         |-------|                                                       |
+|                                                                         |
+|                                                                         |
+|  BD_07.4A    BD_U_11A.4B                                                |
+|                                                                         |
+|  BD_08.5A    BD_U_12A.5B                                                |
+|                                                                         |
+|                                                                 4016    |
+|  86S100        86S100                                                   |
+|                                                                         |
+|  BD_09.8A    BD_U_13A.8B                                                |
+|                                                                         |
+|  BD_10.9A    BD_U_14A.9B   43256                                        |
+|            JP7..8  JP9..12                                              |
+|  JP1..6                                                                 |
+|-------------------------------------------------------------------------|
+Notes:
+      86S105 - Custom PLCC84 chip marked 'CAPCOM 86S105 RJ5C39 863 32 JAPAN'. Manufactured by Ricoh
+               This chip is used to generate sprites. Note the chip has 3x 2kBx8-bit (6kB) internal SRAM.
+               This chip fails often so when a game that uses this chip has vertical jailbars in the sprites
+               most likely this chip has failed.
+      86S100 - Custom chip marked 'CAPCOM 86S100 M ^ 73100'. ^ = triangle. Manufactured by Texas Instruments
+               This chip is similar to 2x 74LS165 8-bit parallel-to-serial shift register chips in one package
+               but with direction control and two data modes (4-bit/8-bit).
+      JP1..6 - 0-ohm jumpers. JP1 & JP5 are shorted, others are open
+      JP7..8 - 0-ohm jumpers. JP7 shorted, JP8 open
+     JP9..12 - 0-ohm jumpers. JP12 shorted, others are open
+       43256 - NEC D43256 32kBx8-bit SRAM (background tile RAM)
+        2018 - Toshiba TMM2018 2kBx8-bit SRAM (additional sprite RAM.... see note above re: 86S105)
+        4016 - NEC D4016 2kBx8-bit SRAM (text layer / character RAM)
+    BD_07.4A \
+    BD_08.5A  \ 27C512 EPROM or OTP EPROM
+    BD_09.8A  /
+    BD_10.9A /
+ BD_U_11A.4B \
+ BD_U_12A.5B  \
+ BD_U_13A.8B  / 27512 OTP EPROM
+ BD_U_14A.9B /
+  BD_U_15.2N - 27256 OTP EPROM
+
+***************************************************************************/
+
+
+#include "emu.h"
+
+#include "cpu/mcs51/mcs51.h"
+#include "cpu/z80/z80.h"
+#include "machine/gen_latch.h"
+#include "machine/watchdog.h"
+#include "sound/ymopn.h"
+#include "video/bufsprite.h"
+
+#include "emupal.h"
+#include "screen.h"
+#include "speaker.h"
+#include "tilemap.h"
+
+
+// configurable logging
+#define LOG_MCU     (1U << 1)
+
+//#define VERBOSE (LOG_GENERAL | LOG_MCU)
+
+#include "logmacro.h"
+
+#define LOGMCU(...)     LOGMASKED(LOG_MCU,     __VA_ARGS__)
+
+
+namespace {
+
+class blktiger_state : public driver_device
+{
+public:
+	blktiger_state(const machine_config &mconfig, device_type type, const char *tag) :
+		driver_device(mconfig, type, tag),
+		m_txvideoram(*this, "txvideoram"),
+		m_scrollram(*this, "scrollram", BGRAM_BANK_SIZE * BGRAM_BANKS, ENDIANNESS_LITTLE),
+		m_mainbank(*this, "mainbank"),
+		m_coin_lockout(*this, "COIN_LOCKOUT"),
+		m_maincpu(*this, "maincpu"),
+		m_audiocpu(*this, "audiocpu"),
+		m_spriteram(*this, "spriteram"),
+		m_gfxdecode(*this, "gfxdecode"),
+		m_palette(*this, "palette")
+	{ }
+
+	void init_blktigerb3();
+	void nomcu(machine_config &config);
+
+protected:
+	virtual void machine_start() override;
+	virtual void machine_reset() override;
+	virtual void video_start() override;
+
+	void nomcu_main_io_map(address_map &map);
+
+private:
+	// memory pointers
+	required_shared_ptr<uint8_t> m_txvideoram;
+	memory_share_creator<uint8_t> m_scrollram;
+	required_memory_bank m_mainbank;
+
+	// I/O
+	required_ioport m_coin_lockout;
+
+	// video-related
+	tilemap_t *m_tx_tilemap = nullptr;
+	tilemap_t *m_bg_tilemap8x4 = nullptr;
+	tilemap_t *m_bg_tilemap4x8 = nullptr;
+	uint32_t m_scroll_bank = 0U;
+	uint8_t m_scroll_x[2]{};
+	uint8_t m_scroll_y[2]{};
+	uint8_t m_screen_layout = 0U;
+	uint8_t m_chon = 0U;
+	uint8_t m_objon = 0U;
+	uint8_t m_bgon = 0U;
+	static constexpr uint16_t BGRAM_BANK_SIZE = 0x1000;
+	static constexpr uint8_t BGRAM_BANKS = 4;
+
+	// devices
+	required_device<cpu_device> m_maincpu;
+	required_device<cpu_device> m_audiocpu;
+	required_device<buffered_spriteram8_device> m_spriteram;
+	required_device<gfxdecode_device> m_gfxdecode;
+	required_device<palette_device> m_palette;
+
+	void bankswitch_w(uint8_t data);
+	void coinlockout_w(uint8_t data);
+	void txvideoram_w(offs_t offset, uint8_t data);
+	uint8_t bgvideoram_r(offs_t offset);
+	void bgvideoram_w(offs_t offset, uint8_t data);
+	void bgvideoram_bank_w(uint8_t data);
+	void scrolly_w(offs_t offset, uint8_t data);
+	void scrollx_w(offs_t offset, uint8_t data);
+	void video_control_w(uint8_t data);
+	void video_enable_w(uint8_t data);
+	void screen_layout_w(uint8_t data);
+	TILEMAP_MAPPER_MEMBER(bg8x4_scan);
+	TILEMAP_MAPPER_MEMBER(bg4x8_scan);
+	TILE_GET_INFO_MEMBER(get_bg_tile_info);
+	TILE_GET_INFO_MEMBER(get_tx_tile_info);
+	uint32_t screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
+	void draw_sprites(bitmap_ind16 &bitmap, const rectangle &cliprect);
+
+	void main_prg_map(address_map &map);
+	void sound_map(address_map &map);
+};
+
+class blktiger_mcu_state : public blktiger_state
+{
+public:
+	blktiger_mcu_state(const machine_config &mconfig, device_type type, const char *tag) :
+		blktiger_state(mconfig, type, tag),
+		m_mcu(*this, "mcu")
+	{ }
+
+	void mcu(machine_config &config);
+
+protected:
+	virtual void machine_start() override;
+	virtual void machine_reset() override;
+
+private:
+	// MCU-related
+	uint8_t m_z80_latch = 0U;
+	uint8_t m_i8751_latch = 0U;
+
+	// devices
+	required_device<i8751_device> m_mcu;
+
+	uint8_t from_mcu_r();
+	void to_mcu_w(uint8_t data);
+	uint8_t from_main_r();
+	void to_main_w(uint8_t data);
+
+	void mcu_main_io_map(address_map &map);
+};
+
+
+// video
+
+/***************************************************************************
+
+  Callbacks for the TileMap code
+
+***************************************************************************/
+
+TILEMAP_MAPPER_MEMBER(blktiger_state::bg8x4_scan)
+{
+	// logical (col,row) -> memory offset
+	return (col & 0x0f) + ((row & 0x0f) << 4) + ((col & 0x70) << 4) + ((row & 0x30) << 7);
+}
+
+TILEMAP_MAPPER_MEMBER(blktiger_state::bg4x8_scan)
+{
+	// logical (col,row) -> memory offset
+	return (col & 0x0f) + ((row & 0x0f) << 4) + ((col & 0x30) << 4) + ((row & 0x70) << 6);
+}
+
+TILE_GET_INFO_MEMBER(blktiger_state::get_bg_tile_info)
+{
+	// the tile priority table is a guess compiled by looking at the game. It was not derived from a PROM so it could be wrong.
+	static const uint8_t split_table[16] =
+	{
+		3,3,2,2,
+		1,1,0,0,
+		0,0,0,0,
+		0,0,0,0
+	};
+	uint8_t attr = m_scrollram[2 * tile_index + 1];
+	int color = (attr & 0x78) >> 3;
+	tileinfo.set(1,
+			m_scrollram[2 * tile_index] + ((attr & 0x07) << 8),
+			color,
+			(attr & 0x80) ? TILE_FLIPX : 0);
+	tileinfo.group = split_table[color];
+}
+
+TILE_GET_INFO_MEMBER(blktiger_state::get_tx_tile_info)
+{
+	uint8_t attr = m_txvideoram[tile_index + 0x400];
+	tileinfo.set(0,
+			m_txvideoram[tile_index] + ((attr & 0xe0) << 3),
+			attr & 0x1f,
+			0);
+}
+
+
+/***************************************************************************
+
+  Start the video hardware emulation.
+
+***************************************************************************/
+
+void blktiger_state::video_start()
+{
+	m_chon = 1;
+	m_bgon = 1;
+	m_objon = 1;
+	m_screen_layout = 0;
+
+	m_tx_tilemap =    &machine().tilemap().create(*m_gfxdecode, tilemap_get_info_delegate(*this, FUNC(blktiger_state::get_tx_tile_info)), TILEMAP_SCAN_ROWS, 8, 8, 32, 32);
+	m_bg_tilemap8x4 = &machine().tilemap().create(*m_gfxdecode, tilemap_get_info_delegate(*this, FUNC(blktiger_state::get_bg_tile_info)), tilemap_mapper_delegate(*this, FUNC(blktiger_state::bg8x4_scan)), 16, 16, 128, 64);
+	m_bg_tilemap4x8 = &machine().tilemap().create(*m_gfxdecode, tilemap_get_info_delegate(*this, FUNC(blktiger_state::get_bg_tile_info)), tilemap_mapper_delegate(*this, FUNC(blktiger_state::bg4x8_scan)), 16, 16, 64, 128);
+
+	m_tx_tilemap->set_transparent_pen(3);
+
+	m_bg_tilemap8x4->set_transmask(0, 0xffff, 0x8000);  // split type 0 is totally transparent in front half
+	m_bg_tilemap8x4->set_transmask(1, 0xfff0, 0x800f);  // split type 1 has pens 4-15 transparent in front half
+	m_bg_tilemap8x4->set_transmask(2, 0xff00, 0x80ff);  // split type 1 has pens 8-15 transparent in front half
+	m_bg_tilemap8x4->set_transmask(3, 0xf000, 0x8fff);  // split type 1 has pens 12-15 transparent in front half
+	m_bg_tilemap4x8->set_transmask(0, 0xffff, 0x8000);
+	m_bg_tilemap4x8->set_transmask(1, 0xfff0, 0x800f);
+	m_bg_tilemap4x8->set_transmask(2, 0xff00, 0x80ff);
+	m_bg_tilemap4x8->set_transmask(3, 0xf000, 0x8fff);
+
+	m_tx_tilemap->set_scrolldx(128, 128);
+	m_tx_tilemap->set_scrolldy(  6,   6);
+	m_bg_tilemap8x4->set_scrolldx(128, 128);
+	m_bg_tilemap8x4->set_scrolldy(  6,   6);
+	m_bg_tilemap4x8->set_scrolldx(128, 128);
+	m_bg_tilemap4x8->set_scrolldy(  6,   6);
+}
+
+
+
+/***************************************************************************
+
+  Memory handlers
+
+***************************************************************************/
+
+void blktiger_state::txvideoram_w(offs_t offset, uint8_t data)
+{
+	m_txvideoram[offset] = data;
+	m_tx_tilemap->mark_tile_dirty(offset & 0x3ff);
+}
+
+uint8_t blktiger_state::bgvideoram_r(offs_t offset)
+{
+	return m_scrollram[offset + m_scroll_bank];
+}
+
+void blktiger_state::bgvideoram_w(offs_t offset, uint8_t data)
+{
+	offset += m_scroll_bank;
+
+	m_scrollram[offset] = data;
+	m_bg_tilemap8x4->mark_tile_dirty(offset / 2);
+	m_bg_tilemap4x8->mark_tile_dirty(offset / 2);
+}
+
+void blktiger_state::bgvideoram_bank_w(uint8_t data)
+{
+	m_scroll_bank = (data % BGRAM_BANKS) * BGRAM_BANK_SIZE;
+}
+
+
+void blktiger_state::scrolly_w(offs_t offset, uint8_t data)
+{
+	m_scroll_y[offset] = data;
+	int scrolly = m_scroll_y[0] | (m_scroll_y[1] << 8);
+	m_bg_tilemap8x4->set_scrolly(0, scrolly);
+	m_bg_tilemap4x8->set_scrolly(0, scrolly);
+}
+
+void blktiger_state::scrollx_w(offs_t offset, uint8_t data)
+{
+	m_scroll_x[offset] = data;
+	int scrollx = m_scroll_x[0] | (m_scroll_x[1] << 8);
+	m_bg_tilemap8x4->set_scrollx(0, scrollx);
+	m_bg_tilemap4x8->set_scrollx(0, scrollx);
+}
+
+
+void blktiger_state::video_control_w(uint8_t data)
+{
+	// bits 0 and 1 are coin counters
+	machine().bookkeeping().coin_counter_w(0,data & 1);
+	machine().bookkeeping().coin_counter_w(1,data & 2);
+
+	// bit 5 resets the sound CPU
+	m_audiocpu->set_input_line(INPUT_LINE_RESET, (data & 0x20) ? ASSERT_LINE : CLEAR_LINE);
+
+	// bit 6 flips screen
+	flip_screen_set(data & 0x40);
+
+	// bit 7 enables characters? Just a guess
+	m_chon = ~data & 0x80;
+}
+
+void blktiger_state::video_enable_w(uint8_t data)
+{
+	// not sure which is which, but I think that bit 1 and 2 enable background and sprites
+	// bit 1 enables bg ?
+	m_bgon = ~data & 0x02;
+
+	// bit 2 enables sprites ?
+	m_objon = ~data & 0x04;
+}
+
+void blktiger_state::screen_layout_w(uint8_t data)
+{
+	m_screen_layout = data;
+	m_bg_tilemap8x4->enable(m_screen_layout);
+	m_bg_tilemap4x8->enable(!m_screen_layout);
+}
+
+
+
+/***************************************************************************
+
+  Display refresh
+
+***************************************************************************/
+
+void blktiger_state::draw_sprites(bitmap_ind16 &bitmap, const rectangle &cliprect)
+{
+	uint8_t *buffered_spriteram = m_spriteram->buffer();
+
+	// Draw the sprites.
+	for (int offs = m_spriteram->bytes() - 4; offs >= 0; offs -= 4)
+	{
+		int attr = buffered_spriteram[offs + 1];
+		int sx = buffered_spriteram[offs + 3] - ((attr & 0x10) << 4);
+		int sy = buffered_spriteram[offs + 2];
+		int code = buffered_spriteram[offs] | ((attr & 0xe0) << 3);
+		int color = attr & 0x07;
+		int flipx = attr & 0x08;
+
+		if (flip_screen())
+		{
+			sx = 240 - sx;
+			sy = 240 - sy;
+			flipx = !flipx;
+		}
+
+		m_gfxdecode->gfx(2)->transpen(bitmap, cliprect,
+				code,
+				color,
+				flipx, flip_screen(),
+				sx + 128, sy + 6, 15);
+	}
+}
+
+uint32_t blktiger_state::screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect)
+{
+	bitmap.fill(1023, cliprect);
+
+	if (m_bgon)
+		(m_screen_layout ? m_bg_tilemap8x4 : m_bg_tilemap4x8)->draw(screen, bitmap, cliprect, TILEMAP_DRAW_LAYER1, 0);
+
+	if (m_objon)
+		draw_sprites(bitmap, cliprect);
+
+	if (m_bgon)
+		(m_screen_layout ? m_bg_tilemap8x4 : m_bg_tilemap4x8)->draw(screen, bitmap, cliprect, TILEMAP_DRAW_LAYER0, 0);
+
+	if (m_chon)
+		m_tx_tilemap->draw(screen, bitmap, cliprect, 0, 0);
+
+	return 0;
+}
+
+
+// machine
+
+/**************************************************
+
+Protection comms between main cpu and i8751
+
+**************************************************/
+
+uint8_t blktiger_mcu_state::from_mcu_r()
+{
+	return m_i8751_latch;
+}
+
+void blktiger_mcu_state::to_mcu_w(uint8_t data)
+{
+	m_mcu->set_input_line(MCS51_INT1_LINE, ASSERT_LINE);
+	m_z80_latch = data;
+}
+
+uint8_t blktiger_mcu_state::from_main_r()
+{
+	m_mcu->set_input_line(MCS51_INT1_LINE, CLEAR_LINE);
+	LOGMCU("%02x read\n", m_z80_latch);
+	return m_z80_latch;
+}
+
+void blktiger_mcu_state::to_main_w(uint8_t data)
+{
+	LOGMCU("%02x write\n", data);
+	m_i8751_latch = data;
+}
+
+
+
+void blktiger_state::bankswitch_w(uint8_t data)
+{
+	m_mainbank->set_entry(data & 0x0f);
+}
+
+void blktiger_state::coinlockout_w(uint8_t data)
+{
+	if (m_coin_lockout->read() & 0x01)
+	{
+		machine().bookkeeping().coin_lockout_w(0, ~data & 0x01);
+		machine().bookkeeping().coin_lockout_w(1, ~data & 0x02);
+	}
+}
+
+
+void blktiger_state::main_prg_map(address_map &map)
+{
+	map(0x0000, 0x7fff).rom();
+	map(0x8000, 0xbfff).bankr(m_mainbank);
+	map(0xc000, 0xcfff).rw(FUNC(blktiger_state::bgvideoram_r), FUNC(blktiger_state::bgvideoram_w));
+	map(0xd000, 0xd7ff).ram().w(FUNC(blktiger_state::txvideoram_w)).share(m_txvideoram);
+	map(0xd800, 0xdbff).ram().w(m_palette, FUNC(palette_device::write8)).share("palette");
+	map(0xdc00, 0xdfff).ram().w(m_palette, FUNC(palette_device::write8_ext)).share("palette_ext");
+	map(0xe000, 0xfdff).ram();
+	map(0xfe00, 0xffff).ram().share("spriteram");
+}
+
+void blktiger_state::nomcu_main_io_map(address_map &map)
+{
+	map.global_mask(0xff);
+	map(0x00, 0x00).portr("IN0").w("soundlatch", FUNC(generic_latch_8_device::write));
+	map(0x01, 0x01).portr("IN1").w(FUNC(blktiger_state::bankswitch_w));
+	map(0x02, 0x02).portr("IN2");
+	map(0x03, 0x03).portr("DSW0").w(FUNC(blktiger_state::coinlockout_w));
+	map(0x04, 0x04).portr("DSW1").w(FUNC(blktiger_state::video_control_w));
+	map(0x05, 0x05).portr("FREEZE");
+	map(0x06, 0x06).w("watchdog", FUNC(watchdog_timer_device::reset_w));
+	map(0x07, 0x07).noprw();  // Software protection (7)
+	map(0x08, 0x09).w(FUNC(blktiger_state::scrollx_w));
+	map(0x0a, 0x0b).w(FUNC(blktiger_state::scrolly_w));
+	map(0x0c, 0x0c).w(FUNC(blktiger_state::video_enable_w));
+	map(0x0d, 0x0d).w(FUNC(blktiger_state::bgvideoram_bank_w));
+	map(0x0e, 0x0e).w(FUNC(blktiger_state::screen_layout_w));
+}
+
+void blktiger_mcu_state::mcu_main_io_map(address_map &map)
+{
+	nomcu_main_io_map(map);
+
+	map(0x07, 0x07).rw(FUNC(blktiger_mcu_state::from_mcu_r), FUNC(blktiger_mcu_state::to_mcu_w));     // Software protection (7)
+}
+
+void blktiger_state::sound_map(address_map &map)
+{
+	map(0x0000, 0x7fff).rom();
+	map(0xc000, 0xc7ff).ram();
+	map(0xc800, 0xc800).r("soundlatch", FUNC(generic_latch_8_device::read));
+	map(0xe000, 0xe001).rw("ym1", FUNC(ym2203_device::read), FUNC(ym2203_device::write));
+	map(0xe002, 0xe003).rw("ym2", FUNC(ym2203_device::read), FUNC(ym2203_device::write));
+}
+
+
+
+static INPUT_PORTS_START( blktiger )
+	PORT_START("IN0")
+	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_START1 )
+	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_START2 )
+	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )    // probably unused
+	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNKNOWN )    // probably unused
+	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )    // probably unused
+	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_SERVICE1 )
+	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_COIN1 )
+	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_COIN2 )
+
+	PORT_START("IN1")
+	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY
+	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY
+	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY
+	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY
+	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 )
+	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON2 )
+	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )    // probably unused
+	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )    // probably unused
+
+	PORT_START("IN2")
+	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_COCKTAIL
+	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_COCKTAIL
+	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_COCKTAIL
+	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_COCKTAIL
+	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_COCKTAIL
+	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_COCKTAIL
+	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )    // probably unused
+	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )    // probably unused
+
+	PORT_START("DSW0")
+	PORT_DIPNAME( 0x07, 0x07, DEF_STR( Coin_A ) )       PORT_DIPLOCATION( "SW1:1,2,3" )
+	PORT_DIPSETTING(    0x00, DEF_STR( 4C_1C ) )
+	PORT_DIPSETTING(    0x01, DEF_STR( 3C_1C ) )
+	PORT_DIPSETTING(    0x02, DEF_STR( 2C_1C ) )
+	PORT_DIPSETTING(    0x07, DEF_STR( 1C_1C ) )
+	PORT_DIPSETTING(    0x06, DEF_STR( 1C_2C ) )
+	PORT_DIPSETTING(    0x05, DEF_STR( 1C_3C ) )
+	PORT_DIPSETTING(    0x04, DEF_STR( 1C_4C ) )
+	PORT_DIPSETTING(    0x03, DEF_STR( 1C_5C ) )
+	PORT_DIPNAME( 0x38, 0x38, DEF_STR( Coin_B ) )       PORT_DIPLOCATION( "SW1:4,5,6" )
+	PORT_DIPSETTING(    0x00, DEF_STR( 4C_1C ) )
+	PORT_DIPSETTING(    0x08, DEF_STR( 3C_1C ) )
+	PORT_DIPSETTING(    0x10, DEF_STR( 2C_1C ) )
+	PORT_DIPSETTING(    0x38, DEF_STR( 1C_1C ) )
+	PORT_DIPSETTING(    0x30, DEF_STR( 1C_2C ) )
+	PORT_DIPSETTING(    0x28, DEF_STR( 1C_3C ) )
+	PORT_DIPSETTING(    0x20, DEF_STR( 1C_4C ) )
+	PORT_DIPSETTING(    0x18, DEF_STR( 1C_5C ) )
+	PORT_DIPNAME( 0x40, 0x40, DEF_STR( Flip_Screen ) )  PORT_DIPLOCATION( "SW1:7" )
+	PORT_DIPSETTING(    0x40, DEF_STR( Off ) )
+	PORT_DIPSETTING(    0x00, DEF_STR( On ) )
+	PORT_DIPNAME( 0x80, 0x80, DEF_STR( Test ) )         PORT_DIPLOCATION( "SW1:8" )
+	PORT_DIPSETTING(    0x80, DEF_STR( Off ) )
+	PORT_DIPSETTING(    0x00, DEF_STR( On ) )
+
+	PORT_START("DSW1")
+	PORT_DIPNAME( 0x03, 0x03, DEF_STR( Lives ) )        PORT_DIPLOCATION( "SW2:1,2" )
+	PORT_DIPSETTING(    0x02, "2" )
+	PORT_DIPSETTING(    0x03, "3" )
+	PORT_DIPSETTING(    0x01, "5" )
+	PORT_DIPSETTING(    0x00, "7")
+	PORT_DIPNAME( 0x1c, 0x0c, DEF_STR( Difficulty ) )   PORT_DIPLOCATION( "SW2:3,4,5" )
+	PORT_DIPSETTING(    0x1c, "1 (Easiest)")
+	PORT_DIPSETTING(    0x18, "2" )
+	PORT_DIPSETTING(    0x14, "3" )
+	PORT_DIPSETTING(    0x10, "4" )
+	PORT_DIPSETTING(    0x0c, "5 (Normal)" )
+	PORT_DIPSETTING(    0x08, "6" )
+	PORT_DIPSETTING(    0x04, "7" )
+	PORT_DIPSETTING(    0x00, "8 (Hardest)" )
+	PORT_DIPNAME( 0x20, 0x20, DEF_STR( Demo_Sounds ) )  PORT_DIPLOCATION( "SW2:6" )
+	PORT_DIPSETTING(    0x00, DEF_STR( Off ) )
+	PORT_DIPSETTING(    0x20, DEF_STR( On ) )
+	PORT_DIPNAME( 0x40, 0x40, DEF_STR( Allow_Continue ) )   PORT_DIPLOCATION( "SW2:7" )
+	PORT_DIPSETTING(    0x00, DEF_STR( No ) )
+	PORT_DIPSETTING(    0x40, DEF_STR( Yes ) )
+	PORT_DIPNAME( 0x80, 0x00, DEF_STR( Cabinet ) )      PORT_DIPLOCATION( "SW2:8" )
+	PORT_DIPSETTING(    0x00, DEF_STR( Upright ) )
+	PORT_DIPSETTING(    0x80, DEF_STR( Cocktail ) )
+
+	PORT_START("FREEZE")
+	PORT_DIPNAME( 0x01, 0x01, "Freeze" )    // could be VBLANK
+	PORT_DIPSETTING(    0x01, DEF_STR( Off ) )
+	PORT_DIPSETTING(    0x00, DEF_STR( On ) )
+
+	PORT_START("COIN_LOCKOUT")
+	PORT_CONFNAME( 0x01, 0x01, "Coin Lockout Hardware Present" )
+	PORT_CONFSETTING( 0x01, DEF_STR( Yes ) )
+	PORT_CONFSETTING( 0x00, DEF_STR( No ) )
+INPUT_PORTS_END
+
+
+
+static const gfx_layout charlayout =
+{
+	8,8,
+	RGN_FRAC(1,1),
+	2,
+	{ 4, 0 },
+	{ 0, 1, 2, 3, 8+0, 8+1, 8+2, 8+3 },
+	{ 0*16, 1*16, 2*16, 3*16, 4*16, 5*16, 6*16, 7*16 },
+	16*8
+};
+
+static const gfx_layout spritelayout =
+{
+	16,16,
+	RGN_FRAC(1,2),
+	4,
+	{ RGN_FRAC(1,2)+4, RGN_FRAC(1,2)+0, 4, 0 },
+	{ 0, 1, 2, 3, 8+0, 8+1, 8+2, 8+3,
+			16*16+0, 16*16+1, 16*16+2, 16*16+3, 16*16+8+0, 16*16+8+1, 16*16+8+2, 16*16+8+3 },
+	{ 0*16, 1*16, 2*16, 3*16, 4*16, 5*16, 6*16, 7*16,
+			8*16, 9*16, 10*16, 11*16, 12*16, 13*16, 14*16, 15*16 },
+	32*16
+};
+
+static GFXDECODE_START( gfx_blktiger )
+	GFXDECODE_ENTRY( "chars",   0, charlayout,   0x300, 32 )   // colors 0x300-0x37f
+	GFXDECODE_ENTRY( "tiles",   0, spritelayout, 0x000, 16 )   // colors 0x000-0x0ff
+	GFXDECODE_ENTRY( "sprites", 0, spritelayout, 0x200,  8 )   // colors 0x200-0x27f
+GFXDECODE_END
+
+
+void blktiger_state::machine_start()
+{
+	// configure bankswitching
+	m_mainbank->configure_entries(0, 16, memregion("maincpu")->base() + 0x10000, 0x4000);
+
+	save_item(NAME(m_scroll_bank));
+	save_item(NAME(m_screen_layout));
+	save_item(NAME(m_chon));
+	save_item(NAME(m_objon));
+	save_item(NAME(m_bgon));
+	save_item(NAME(m_scroll_x));
+	save_item(NAME(m_scroll_y));
+}
+
+void blktiger_state::machine_reset()
+{
+	m_scroll_x[0] = 0;
+	m_scroll_x[1] = 0;
+	m_scroll_y[0] = 0;
+	m_scroll_y[1] = 0;
+	m_scroll_bank = 0;
+	m_screen_layout = 0;
+}
+
+void blktiger_mcu_state::machine_start()
+{
+	save_item(NAME(m_z80_latch));
+	save_item(NAME(m_i8751_latch));
+
+	blktiger_state::machine_start();
+}
+
+void blktiger_mcu_state::machine_reset()
+{
+	m_z80_latch = 0;
+	m_i8751_latch = 0;
+
+	blktiger_state::machine_reset();
+}
+
+void blktiger_state::nomcu(machine_config &config)
+{
+	// basic machine hardware
+	Z80(config, m_maincpu, XTAL(24'000'000) / 4); // verified on PCB
+	m_maincpu->set_addrmap(AS_PROGRAM, &blktiger_state::main_prg_map);
+	m_maincpu->set_addrmap(AS_IO, &blktiger_state::nomcu_main_io_map);
+	m_maincpu->set_vblank_int("screen", FUNC(blktiger_state::irq0_line_hold));
+
+	Z80(config, m_audiocpu, XTAL(3'579'545));   // verified on PCB
+	m_audiocpu->set_addrmap(AS_PROGRAM, &blktiger_state::sound_map);
+
+	WATCHDOG_TIMER(config, "watchdog");
+
+	// video hardware
+	screen_device &screen(SCREEN(config, "screen", SCREEN_TYPE_RASTER));
+	screen.set_raw(24_MHz_XTAL / 4, 384, 128, 0, 262, 22, 246); // hsync is 50..77, vsync is 257..259
+	screen.set_screen_update(FUNC(blktiger_state::screen_update));
+	screen.screen_vblank().set("spriteram", FUNC(buffered_spriteram8_device::vblank_copy_rising));
+	screen.set_palette(m_palette);
+
+	GFXDECODE(config, m_gfxdecode, m_palette, gfx_blktiger);
+
+	PALETTE(config, m_palette).set_format(palette_device::xBRG_444, 1024);
+
+	BUFFERED_SPRITERAM8(config, m_spriteram);
+
+	// sound hardware
+	SPEAKER(config, "mono").front_center();
+
+	GENERIC_LATCH_8(config, "soundlatch");
+
+	ym2203_device &ym1(YM2203(config, "ym1", XTAL(3'579'545))); // verified on PCB
+	ym1.irq_handler().set_inputline(m_audiocpu, 0);
+	ym1.add_route(ALL_OUTPUTS, "mono", 0.15);
+
+	ym2203_device &ym2(YM2203(config, "ym2", XTAL(3'579'545))); // verified on PCB
+	ym2.add_route(ALL_OUTPUTS, "mono", 0.15);
+}
+
+void blktiger_mcu_state::mcu(machine_config &config)
+{
+	nomcu(config);
+	subdevice<cpu_device>("maincpu")->set_addrmap(AS_IO, &blktiger_mcu_state::mcu_main_io_map);
+
+	I8751(config, m_mcu, XTAL(24'000'000) / 3);   // verified on PCB
+	m_mcu->port_in_cb<0>().set(FUNC(blktiger_mcu_state::from_main_r));
+	m_mcu->port_out_cb<0>().set(FUNC(blktiger_mcu_state::to_main_w));
+	// other ports unknown
+	//m_mcu->set_vblank_int("screen", FUNC(blktiger_mcu_state::irq0_line_hold));
+}
+
+/***************************************************************************
+
+  Game driver(s)
+
+***************************************************************************/
+
+ROM_START( blktiger )
+	ROM_REGION( 0x50000, "maincpu", 0 ) // 64k for code + banked ROMs images
+	ROM_LOAD( "bdu-01a.5e",  0x00000, 0x08000, CRC(a8f98f22) SHA1(f77c0d0ebf3e52a21d2c0c5004350a408b8e6d24) )   // CODE
+	ROM_LOAD( "bdu-02a.6e",  0x10000, 0x10000, CRC(7bef96e8) SHA1(6d05a73d8400dead78c561b904bf6ef8311e7b91) )   // 0+1
+	ROM_LOAD( "bdu-03a.8e",  0x20000, 0x10000, CRC(4089e157) SHA1(7972b1c745057802d4fd66d88b0101eb3c03e701) )   // 2+3
+	ROM_LOAD( "bd-04.9e",    0x30000, 0x10000, CRC(ed6af6ec) SHA1(bed303c51bcddf233ad0701306d557a60ce9f5a5) )   // 4+5
+	ROM_LOAD( "bd-05.10e",   0x40000, 0x10000, CRC(ae59b72e) SHA1(6e72214b71f2f337af236c8be891a18570cb6fbb) )   // 6+7
+
+	ROM_REGION( 0x10000, "audiocpu", 0 )
+	ROM_LOAD( "bd-06.1l",  0x0000, 0x8000, CRC(2cf54274) SHA1(87df100c65999ba1e9d358ffd0fe4bba23ae0efb) )
+
+	ROM_REGION( 0x1000, "mcu", 0 )
+	ROM_LOAD( "bd.6k",  0x0000, 0x1000, CRC(ac7d14f1) SHA1(46fd6b43f10312e3e8d3c9e0c0fd616af98fdbad) )
+
+	ROM_REGION( 0x08000, "chars", 0 )
+	ROM_LOAD( "bd-15.2n",  0x00000, 0x08000, CRC(70175d78) SHA1(2f02be2785d1824002145ea20db79821d0393929) )
+
+	ROM_REGION( 0x40000, "tiles", 0 )
+	ROM_LOAD( "bd-12.5b",  0x00000, 0x10000, CRC(c4524993) SHA1(9aa6c58004ca1117e5ac44ba8fc51e9128b921b8) )
+	ROM_LOAD( "bd-11.4b",  0x10000, 0x10000, CRC(7932c86f) SHA1(b3b1bc1e2b0db5c2eb8772f8a2c35129cc80d511) )
+	ROM_LOAD( "bd-14.9b",  0x20000, 0x10000, CRC(dc49593a) SHA1(e4ef42ba9f238fd43c8217657c92896f31d3912c) )
+	ROM_LOAD( "bd-13.8b",  0x30000, 0x10000, CRC(7ed7a122) SHA1(3acc6d4c9731db0609c2e26e3bd255847149ca33) )
+
+	ROM_REGION( 0x40000, "sprites", 0 )
+	ROM_LOAD( "bd-08.5a",   0x00000, 0x10000, CRC(e2f17438) SHA1(3e5fdae07d40febedc59c7c7c4d9c6f0d72b58b5) )
+	ROM_LOAD( "bd-07.4a",   0x10000, 0x10000, CRC(5fccbd27) SHA1(33c55aa9c12b3121ca5c3b4c39a9b152b6946461) )
+	ROM_LOAD( "bd-10.9a",   0x20000, 0x10000, CRC(fc33ccc6) SHA1(d492626a88565c2626f98ecb1d74535f1ad68e4c) )
+	ROM_LOAD( "bd-09.8a",   0x30000, 0x10000, CRC(f449de01) SHA1(f6b40e9eb2471b89c42ab84f4214295d284db0c3) )
+
+	ROM_REGION( 0x0400, "proms", 0 )    // PROMs (see hw info on top)
+	ROM_LOAD( "bd01.8j",   0x0000, 0x0100, CRC(29b459e5) SHA1(0034734a533df3dea16b7b48e072485d7f26f850) )
+	ROM_LOAD( "bd02.9j",   0x0100, 0x0100, CRC(8b741e66) SHA1(6c1fda59936a7217b05949f5c54b1f91f4b49dbe) )
+	ROM_LOAD( "bd03.11k",  0x0200, 0x0100, CRC(27201c75) SHA1(c54d87f06bfe0b0908389c005014d97156e272c2) )
+	ROM_LOAD( "bd04.11l",  0x0300, 0x0100, CRC(e5490b68) SHA1(40f9f92efe7dd97b49144aec02eb509834056915) )
+ROM_END
+
+ROM_START( blktigera )
+	ROM_REGION( 0x50000, "maincpu", 0 ) // 64k for code + banked ROMs images
+	ROM_LOAD( "bdu-01.5e",  0x00000, 0x08000, CRC(47b13922) SHA1(a722048d48171b68119b7ef1af6e06953c238ad6) )    // CODE
+	ROM_LOAD( "bdu-02.6e",  0x10000, 0x10000, CRC(2e0daf1b) SHA1(dbcaf2bb1b2c9cd4b2ca1d52b81d6e33b5c7eee9) )    // 0+1
+	ROM_LOAD( "bdu-03.8e",  0x20000, 0x10000, CRC(3b67dfec) SHA1(f9d83f2bb1fbf05d80f6870d91411e9b7bbea917) )    // 2+3
+	ROM_LOAD( "bd-04.9e",    0x30000, 0x10000, CRC(ed6af6ec) SHA1(bed303c51bcddf233ad0701306d557a60ce9f5a5) )   // 4+5
+	ROM_LOAD( "bd-05.10e",   0x40000, 0x10000, CRC(ae59b72e) SHA1(6e72214b71f2f337af236c8be891a18570cb6fbb) )   // 6+7
+
+	ROM_REGION( 0x10000, "audiocpu", 0 )
+	ROM_LOAD( "bd-06.1l",  0x0000, 0x8000, CRC(2cf54274) SHA1(87df100c65999ba1e9d358ffd0fe4bba23ae0efb) )
+
+	ROM_REGION( 0x1000, "mcu", 0 )
+	ROM_LOAD( "bd.6k",  0x0000, 0x1000, CRC(ac7d14f1) SHA1(46fd6b43f10312e3e8d3c9e0c0fd616af98fdbad) )
+
+	ROM_REGION( 0x08000, "chars", 0 )
+	ROM_LOAD( "bd-15.2n",  0x00000, 0x08000, CRC(70175d78) SHA1(2f02be2785d1824002145ea20db79821d0393929) )
+
+	ROM_REGION( 0x40000, "tiles", 0 )
+	ROM_LOAD( "bd-12.5b",  0x00000, 0x10000, CRC(c4524993) SHA1(9aa6c58004ca1117e5ac44ba8fc51e9128b921b8) )
+	ROM_LOAD( "bd-11.4b",  0x10000, 0x10000, CRC(7932c86f) SHA1(b3b1bc1e2b0db5c2eb8772f8a2c35129cc80d511) )
+	ROM_LOAD( "bd-14.9b",  0x20000, 0x10000, CRC(dc49593a) SHA1(e4ef42ba9f238fd43c8217657c92896f31d3912c) )
+	ROM_LOAD( "bd-13.8b",  0x30000, 0x10000, CRC(7ed7a122) SHA1(3acc6d4c9731db0609c2e26e3bd255847149ca33) )
+
+	ROM_REGION( 0x40000, "sprites", 0 )
+	ROM_LOAD( "bd-08.5a",   0x00000, 0x10000, CRC(e2f17438) SHA1(3e5fdae07d40febedc59c7c7c4d9c6f0d72b58b5) )
+	ROM_LOAD( "bd-07.4a",   0x10000, 0x10000, CRC(5fccbd27) SHA1(33c55aa9c12b3121ca5c3b4c39a9b152b6946461) )
+	ROM_LOAD( "bd-10.9a",   0x20000, 0x10000, CRC(fc33ccc6) SHA1(d492626a88565c2626f98ecb1d74535f1ad68e4c) )
+	ROM_LOAD( "bd-09.8a",   0x30000, 0x10000, CRC(f449de01) SHA1(f6b40e9eb2471b89c42ab84f4214295d284db0c3) )
+
+	ROM_REGION( 0x0400, "proms", 0 )    // PROMs (see hw info on top)
+	ROM_LOAD( "bd01.8j",   0x0000, 0x0100, CRC(29b459e5) SHA1(0034734a533df3dea16b7b48e072485d7f26f850) )
+	ROM_LOAD( "bd02.9j",   0x0100, 0x0100, CRC(8b741e66) SHA1(6c1fda59936a7217b05949f5c54b1f91f4b49dbe) )
+	ROM_LOAD( "bd03.11k",  0x0200, 0x0100, CRC(27201c75) SHA1(c54d87f06bfe0b0908389c005014d97156e272c2) )
+	ROM_LOAD( "bd04.11l",  0x0300, 0x0100, CRC(e5490b68) SHA1(40f9f92efe7dd97b49144aec02eb509834056915) )
+ROM_END
+
+ROM_START( blktigerb1 )
+	ROM_REGION( 0x50000, "maincpu", 0 ) // 64k for code + banked ROMs images
+	ROM_LOAD( "btiger1.f6",   0x00000, 0x08000, CRC(9d8464e8) SHA1(c847ee9a22b8b636e85427214747e6bd779023e8) )  // CODE
+	ROM_LOAD( "bdu-02a.6e",   0x10000, 0x10000, CRC(7bef96e8) SHA1(6d05a73d8400dead78c561b904bf6ef8311e7b91) )  // 0+1
+	ROM_LOAD( "btiger3.j6",   0x20000, 0x10000, CRC(52c56ed1) SHA1(b6ea61869dcfcedb8cfc14c613440e3f4649866f) )  // 2+3
+	ROM_LOAD( "bd-04.9e",     0x30000, 0x10000, CRC(ed6af6ec) SHA1(bed303c51bcddf233ad0701306d557a60ce9f5a5) )  // 4+5
+	ROM_LOAD( "bd-05.10e",    0x40000, 0x10000, CRC(ae59b72e) SHA1(6e72214b71f2f337af236c8be891a18570cb6fbb) )  // 6+7
+
+	ROM_REGION( 0x10000, "audiocpu", 0 )
+	ROM_LOAD( "bd-06.1l",  0x0000, 0x8000, CRC(2cf54274) SHA1(87df100c65999ba1e9d358ffd0fe4bba23ae0efb) )
+
+	ROM_REGION( 0x08000, "chars", 0 )
+	ROM_LOAD( "bd-15.2n",  0x00000, 0x08000, CRC(70175d78) SHA1(2f02be2785d1824002145ea20db79821d0393929) )
+
+	ROM_REGION( 0x40000, "tiles", 0 )
+	ROM_LOAD( "bd-12.5b",  0x00000, 0x10000, CRC(c4524993) SHA1(9aa6c58004ca1117e5ac44ba8fc51e9128b921b8) )
+	ROM_LOAD( "bd-11.4b",  0x10000, 0x10000, CRC(7932c86f) SHA1(b3b1bc1e2b0db5c2eb8772f8a2c35129cc80d511) )
+	ROM_LOAD( "bd-14.9b",  0x20000, 0x10000, CRC(dc49593a) SHA1(e4ef42ba9f238fd43c8217657c92896f31d3912c) )
+	ROM_LOAD( "bd-13.8b",  0x30000, 0x10000, CRC(7ed7a122) SHA1(3acc6d4c9731db0609c2e26e3bd255847149ca33) )
+
+	ROM_REGION( 0x40000, "sprites", 0 )
+	ROM_LOAD( "bd-08.5a",  0x00000, 0x10000, CRC(e2f17438) SHA1(3e5fdae07d40febedc59c7c7c4d9c6f0d72b58b5) )
+	ROM_LOAD( "bd-07.4a",  0x10000, 0x10000, CRC(5fccbd27) SHA1(33c55aa9c12b3121ca5c3b4c39a9b152b6946461) )
+	ROM_LOAD( "bd-10.9a",  0x20000, 0x10000, CRC(fc33ccc6) SHA1(d492626a88565c2626f98ecb1d74535f1ad68e4c) )
+	ROM_LOAD( "bd-09.8a",  0x30000, 0x10000, CRC(f449de01) SHA1(f6b40e9eb2471b89c42ab84f4214295d284db0c3) )
+
+	ROM_REGION( 0x0400, "proms", 0 )    // PROMs (see hw info on top)
+	ROM_LOAD( "bd01.8j",   0x0000, 0x0100, CRC(29b459e5) SHA1(0034734a533df3dea16b7b48e072485d7f26f850) )
+	ROM_LOAD( "bd02.9j",   0x0100, 0x0100, CRC(8b741e66) SHA1(6c1fda59936a7217b05949f5c54b1f91f4b49dbe) )
+	ROM_LOAD( "bd03.11k",  0x0200, 0x0100, CRC(27201c75) SHA1(c54d87f06bfe0b0908389c005014d97156e272c2) )
+	ROM_LOAD( "bd04.11l",  0x0300, 0x0100, CRC(e5490b68) SHA1(40f9f92efe7dd97b49144aec02eb509834056915) )
+ROM_END
+
+ROM_START( blktigerb2 )
+	ROM_REGION( 0x50000, "maincpu", 0 ) // 64k for code + banked ROMs images
+	ROM_LOAD( "1.bin",        0x00000, 0x08000, CRC(47e2b21e) SHA1(3f03543ace435239978a95f569ac89f6762253c0) )  // CODE
+	ROM_LOAD( "bdu-02a.6e",   0x10000, 0x10000, CRC(7bef96e8) SHA1(6d05a73d8400dead78c561b904bf6ef8311e7b91) )  // 0+1
+	ROM_LOAD( "3.bin",        0x20000, 0x10000, CRC(52c56ed1) SHA1(b6ea61869dcfcedb8cfc14c613440e3f4649866f) )  // 2+3 : same crc of btiger3.j6 from bktigerb
+	ROM_LOAD( "bd-04.9e",     0x30000, 0x10000, CRC(ed6af6ec) SHA1(bed303c51bcddf233ad0701306d557a60ce9f5a5) )  // 4+5
+	ROM_LOAD( "bd-05.10e",    0x40000, 0x10000, CRC(ae59b72e) SHA1(6e72214b71f2f337af236c8be891a18570cb6fbb) )  // 6+7
+
+	ROM_REGION( 0x10000, "audiocpu", 0 )
+	ROM_LOAD( "bd-06.1l",  0x0000, 0x8000, CRC(2cf54274) SHA1(87df100c65999ba1e9d358ffd0fe4bba23ae0efb) )
+
+	ROM_REGION( 0x08000, "chars", 0 )
+	ROM_LOAD( "bd-15.2n",  0x00000, 0x08000, CRC(70175d78) SHA1(2f02be2785d1824002145ea20db79821d0393929) )
+
+	ROM_REGION( 0x40000, "tiles", 0 )
+	ROM_LOAD( "bd-12.5b",  0x00000, 0x10000, CRC(c4524993) SHA1(9aa6c58004ca1117e5ac44ba8fc51e9128b921b8) )
+	ROM_LOAD( "bd-11.4b",  0x10000, 0x10000, CRC(7932c86f) SHA1(b3b1bc1e2b0db5c2eb8772f8a2c35129cc80d511) )
+	ROM_LOAD( "bd-14.9b",  0x20000, 0x10000, CRC(dc49593a) SHA1(e4ef42ba9f238fd43c8217657c92896f31d3912c) )
+	ROM_LOAD( "bd-13.8b",  0x30000, 0x10000, CRC(7ed7a122) SHA1(3acc6d4c9731db0609c2e26e3bd255847149ca33) )
+
+	ROM_REGION( 0x40000, "sprites", 0 )
+	ROM_LOAD( "bd-08.5a",  0x00000, 0x10000, CRC(e2f17438) SHA1(3e5fdae07d40febedc59c7c7c4d9c6f0d72b58b5) )
+	ROM_LOAD( "bd-07.4a",  0x10000, 0x10000, CRC(5fccbd27) SHA1(33c55aa9c12b3121ca5c3b4c39a9b152b6946461) )
+	ROM_LOAD( "bd-10.9a",  0x20000, 0x10000, CRC(fc33ccc6) SHA1(d492626a88565c2626f98ecb1d74535f1ad68e4c) )
+	ROM_LOAD( "bd-09.8a",  0x30000, 0x10000, CRC(f449de01) SHA1(f6b40e9eb2471b89c42ab84f4214295d284db0c3) )
+
+	ROM_REGION( 0x0400, "proms", 0 )    // PROMs (see hw info on top)
+	ROM_LOAD( "bd01.8j",   0x0000, 0x0100, CRC(29b459e5) SHA1(0034734a533df3dea16b7b48e072485d7f26f850) )
+	ROM_LOAD( "bd02.9j",   0x0100, 0x0100, CRC(8b741e66) SHA1(6c1fda59936a7217b05949f5c54b1f91f4b49dbe) )
+	ROM_LOAD( "bd03.11k",  0x0200, 0x0100, CRC(27201c75) SHA1(c54d87f06bfe0b0908389c005014d97156e272c2) )
+	ROM_LOAD( "bd04.11l",  0x0300, 0x0100, CRC(e5490b68) SHA1(40f9f92efe7dd97b49144aec02eb509834056915) )
+ROM_END
+
+ROM_START( blkdrgon )
+	ROM_REGION( 0x50000, "maincpu", 0 ) // 64k for code + banked ROMs images
+	ROM_LOAD( "bd_01.5e",  0x00000, 0x08000, CRC(27ccdfbc) SHA1(3caafe00735ba9b24d870ee61ad2cae541551024) ) // CODE
+	ROM_LOAD( "bd_02.6e",  0x10000, 0x10000, CRC(7d39c26f) SHA1(562a3f578e109ae020f65e341c876ad7e510a311) ) // 0+1
+	ROM_LOAD( "bd_03.8e",  0x20000, 0x10000, CRC(d1bf3757) SHA1(b19f8b986406bde65ac7f0d55d54f87b37f5e42f) ) // 2+3
+	ROM_LOAD( "bd_04.9e",  0x30000, 0x10000, CRC(4d1d6680) SHA1(e137624c59392de6aaffeded99b024938360bd25) ) // 4+5
+	ROM_LOAD( "bd_05.10e", 0x40000, 0x10000, CRC(c8d0c45e) SHA1(66c2e5a74c5875a2c8e28740fe944bd943246ce5) ) // 6+7
+
+	ROM_REGION( 0x10000, "audiocpu", 0 )
+	ROM_LOAD( "bd_06.1l",  0x0000, 0x8000, CRC(2cf54274) SHA1(87df100c65999ba1e9d358ffd0fe4bba23ae0efb) )
+
+	ROM_REGION( 0x1000, "mcu", 0 )
+	ROM_LOAD( "bd.6k",  0x0000, 0x1000, CRC(ac7d14f1) SHA1(46fd6b43f10312e3e8d3c9e0c0fd616af98fdbad) )
+
+	ROM_REGION( 0x08000, "chars", 0 )
+	ROM_LOAD( "bd_15.2n",  0x00000, 0x08000, CRC(3821ab29) SHA1(576f1839f63b0cad6b851d6e6a3e9dec21ac811d) )
+
+	ROM_REGION( 0x40000, "tiles", 0 )
+	ROM_LOAD( "bd_12.5b",  0x00000, 0x10000, CRC(22d0a4b0) SHA1(f9402ea9ffedcb280497a63c5eb352de9d4ca3fd) )
+	ROM_LOAD( "bd_11.4b",  0x10000, 0x10000, CRC(c8b5fc52) SHA1(621e899285ce6302e5b25d133d9cd52c09b7b202) )
+	ROM_LOAD( "bd_14.9b",  0x20000, 0x10000, CRC(9498c378) SHA1(841934ddef724faf04162c4be4aea1684d8d8e0f) )
+	ROM_LOAD( "bd_13.8b",  0x30000, 0x10000, CRC(5b0df8ce) SHA1(57d10b48bd61b0224ce21b36bde8d2479e8e5df4) )
+
+	ROM_REGION( 0x40000, "sprites", 0 )
+	ROM_LOAD( "bd_08.5a",  0x00000, 0x10000, CRC(e2f17438) SHA1(3e5fdae07d40febedc59c7c7c4d9c6f0d72b58b5) )
+	ROM_LOAD( "bd_07.4a",  0x10000, 0x10000, CRC(5fccbd27) SHA1(33c55aa9c12b3121ca5c3b4c39a9b152b6946461) )
+	ROM_LOAD( "bd_10.9a",  0x20000, 0x10000, CRC(fc33ccc6) SHA1(d492626a88565c2626f98ecb1d74535f1ad68e4c) )
+	ROM_LOAD( "bd_09.8a",  0x30000, 0x10000, CRC(f449de01) SHA1(f6b40e9eb2471b89c42ab84f4214295d284db0c3) )
+
+	ROM_REGION( 0x0400, "proms", 0 )    // PROMs (see hw info on top)
+	ROM_LOAD( "bd01.8j",   0x0000, 0x0100, CRC(29b459e5) SHA1(0034734a533df3dea16b7b48e072485d7f26f850) )
+	ROM_LOAD( "bd02.9j",   0x0100, 0x0100, CRC(8b741e66) SHA1(6c1fda59936a7217b05949f5c54b1f91f4b49dbe) )
+	ROM_LOAD( "bd03.11k",  0x0200, 0x0100, CRC(27201c75) SHA1(c54d87f06bfe0b0908389c005014d97156e272c2) )
+	ROM_LOAD( "bd04.11l",  0x0300, 0x0100, CRC(e5490b68) SHA1(40f9f92efe7dd97b49144aec02eb509834056915) )
+ROM_END
+
+
+ROM_START( blkdrgonb )
+	ROM_REGION( 0x50000, "maincpu", 0 ) // 64k for code + banked ROMs images
+	ROM_LOAD( "a1",           0x00000, 0x08000, CRC(7caf2ba0) SHA1(57b17caff67d36b24075f5865d433bfc8bcc9bc2) )  // CODE
+	ROM_LOAD( "blkdrgon.6e",  0x10000, 0x10000, CRC(7d39c26f) SHA1(562a3f578e109ae020f65e341c876ad7e510a311) )  // 0+1
+	ROM_LOAD( "a3",           0x20000, 0x10000, CRC(f4cd0f39) SHA1(9efc5161c861c7ec8ae72509e71c6d7b71b22fc6) )  // 2+3
+	ROM_LOAD( "blkdrgon.9e",  0x30000, 0x10000, CRC(4d1d6680) SHA1(e137624c59392de6aaffeded99b024938360bd25) )  // 4+5
+	ROM_LOAD( "blkdrgon.10e", 0x40000, 0x10000, CRC(c8d0c45e) SHA1(66c2e5a74c5875a2c8e28740fe944bd943246ce5) )  // 6+7
+
+	ROM_REGION( 0x10000, "audiocpu", 0 )
+	ROM_LOAD( "bd-06.1l",  0x0000, 0x8000, CRC(2cf54274) SHA1(87df100c65999ba1e9d358ffd0fe4bba23ae0efb) )
+
+	ROM_REGION( 0x08000, "chars", 0 )
+	ROM_LOAD( "b5",           0x00000, 0x08000, CRC(852ad2b7) SHA1(9f30c0d7e1127589b03d8f45ea50e0f907181a4b) )
+
+	ROM_REGION( 0x40000, "tiles", 0 )
+	ROM_LOAD( "blkdrgon.5b",  0x00000, 0x10000, CRC(22d0a4b0) SHA1(f9402ea9ffedcb280497a63c5eb352de9d4ca3fd) )
+	ROM_LOAD( "b1",           0x10000, 0x10000, CRC(053ab15c) SHA1(f0ddc71009ab5dd69ae463c3636ec2332c0556f8) )
+	ROM_LOAD( "blkdrgon.9b",  0x20000, 0x10000, CRC(9498c378) SHA1(841934ddef724faf04162c4be4aea1684d8d8e0f) )
+	ROM_LOAD( "b3",           0x30000, 0x10000, CRC(9dc6e943) SHA1(0818c1fb2cc8ff403a479457b268bba6ec0730bc) )
+
+	ROM_REGION( 0x40000, "sprites", 0 )
+	ROM_LOAD( "bd-08.5a",  0x00000, 0x10000, CRC(e2f17438) SHA1(3e5fdae07d40febedc59c7c7c4d9c6f0d72b58b5) )
+	ROM_LOAD( "bd-07.4a",  0x10000, 0x10000, CRC(5fccbd27) SHA1(33c55aa9c12b3121ca5c3b4c39a9b152b6946461) )
+	ROM_LOAD( "bd-10.9a",  0x20000, 0x10000, CRC(fc33ccc6) SHA1(d492626a88565c2626f98ecb1d74535f1ad68e4c) )
+	ROM_LOAD( "bd-09.8a",  0x30000, 0x10000, CRC(f449de01) SHA1(f6b40e9eb2471b89c42ab84f4214295d284db0c3) )
+
+	ROM_REGION( 0x0400, "proms", 0 )    // PROMs (see hw info on top)
+	ROM_LOAD( "bd01.8j",   0x0000, 0x0100, CRC(29b459e5) SHA1(0034734a533df3dea16b7b48e072485d7f26f850) )
+	ROM_LOAD( "bd02.9j",   0x0100, 0x0100, CRC(8b741e66) SHA1(6c1fda59936a7217b05949f5c54b1f91f4b49dbe) )
+	ROM_LOAD( "bd03.11k",  0x0200, 0x0100, CRC(27201c75) SHA1(c54d87f06bfe0b0908389c005014d97156e272c2) )
+	ROM_LOAD( "bd04.11l",  0x0300, 0x0100, CRC(e5490b68) SHA1(40f9f92efe7dd97b49144aec02eb509834056915) )
+ROM_END
+
+
+ROM_START( blktigerb3 )
+	ROM_REGION( 0x50000, "maincpu", 0 ) // 64k for code + banked ROMs images // == same as blktigerb2 maincpu
+	ROM_LOAD( "1.5e",  0x00000, 0x08000, CRC(47e2b21e) SHA1(3f03543ace435239978a95f569ac89f6762253c0) )   // CODE
+	ROM_LOAD( "2.6e",  0x10000, 0x10000, CRC(7bef96e8) SHA1(6d05a73d8400dead78c561b904bf6ef8311e7b91) )   // 0+1
+	ROM_LOAD( "3.8e",  0x20000, 0x10000, CRC(52c56ed1) SHA1(b6ea61869dcfcedb8cfc14c613440e3f4649866f) )   // 2+3
+	ROM_LOAD( "4.9e",    0x30000, 0x10000, CRC(ed6af6ec) SHA1(bed303c51bcddf233ad0701306d557a60ce9f5a5) )   // 4+5
+	ROM_LOAD( "5.10e",   0x40000, 0x10000, CRC(ae59b72e) SHA1(6e72214b71f2f337af236c8be891a18570cb6fbb) )   // 6+7
+
+	ROM_REGION( 0x10000, "audiocpu", 0 ) // == same as other sets but with an address swap
+	ROM_LOAD( "6.1l",  0x0000, 0x8000, CRC(6dfab115) SHA1(05f10bdfa4dff50ccc7707a7dbd8eab1680e09b9) )
+
+	ROM_REGION( 0x08000, "chars", 0 ) // == same as blkdrgon
+	ROM_LOAD( "15.2n",  0x00000, 0x08000, CRC(3821ab29) SHA1(576f1839f63b0cad6b851d6e6a3e9dec21ac811d) )
+
+	ROM_REGION( 0x40000, "tiles", 0 ) // == same as other sets
+	ROM_LOAD( "12.5b",  0x00000, 0x10000, CRC(c4524993) SHA1(9aa6c58004ca1117e5ac44ba8fc51e9128b921b8) )
+	ROM_LOAD( "11.4b",  0x10000, 0x10000, CRC(7932c86f) SHA1(b3b1bc1e2b0db5c2eb8772f8a2c35129cc80d511) )
+	ROM_LOAD( "14.9b",  0x20000, 0x10000, CRC(dc49593a) SHA1(e4ef42ba9f238fd43c8217657c92896f31d3912c) )
+	ROM_LOAD( "13.8b",  0x30000, 0x10000, CRC(7ed7a122) SHA1(3acc6d4c9731db0609c2e26e3bd255847149ca33) )
+
+	ROM_REGION( 0x40000, "sprites", 0 ) // == same as other sets
+	ROM_LOAD( "8.5a",   0x00000, 0x10000, CRC(e2f17438) SHA1(3e5fdae07d40febedc59c7c7c4d9c6f0d72b58b5) )
+	ROM_LOAD( "7.4a",   0x10000, 0x10000, CRC(5fccbd27) SHA1(33c55aa9c12b3121ca5c3b4c39a9b152b6946461) )
+	ROM_LOAD( "10.9a",  0x20000, 0x10000, CRC(fc33ccc6) SHA1(d492626a88565c2626f98ecb1d74535f1ad68e4c) )
+	ROM_LOAD( "9.8a",   0x30000, 0x10000, CRC(f449de01) SHA1(f6b40e9eb2471b89c42ab84f4214295d284db0c3) )
+
+	ROM_REGION( 0x0400, "proms", 0 )    // PROMs (see hw info on top), missing in this dump
+	ROM_LOAD( "bd01.8j",   0x0000, 0x0100, CRC(29b459e5) SHA1(0034734a533df3dea16b7b48e072485d7f26f850) )
+	ROM_LOAD( "bd02.9j",   0x0100, 0x0100, CRC(8b741e66) SHA1(6c1fda59936a7217b05949f5c54b1f91f4b49dbe) )
+	ROM_LOAD( "bd03.11k",  0x0200, 0x0100, CRC(27201c75) SHA1(c54d87f06bfe0b0908389c005014d97156e272c2) )
+	ROM_LOAD( "bd04.11l",  0x0300, 0x0100, CRC(e5490b68) SHA1(40f9f92efe7dd97b49144aec02eb509834056915) )
+ROM_END
+
+void blktiger_state::init_blktigerb3()
+{
+	uint8_t *src = memregion("audiocpu")->base();
+	int len = 0x8000;
+	std::vector<uint8_t> buffer(len);
+
+	for (int i = 0; i < len; i++)
+	{
+		int addr = bitswap<16>(i, 15, 14, 13, 12, 11, 10, 9, 8, 3, 4, 5, 6, 7, 2, 1, 0);
+		buffer[i] = src[addr];
+
+	}
+
+	memcpy(src, &buffer[0], len);
+}
+
+} // anonymous namespace
+
+
+GAME( 1987, blktiger,   0,        mcu,   blktiger, blktiger_mcu_state, empty_init,      ROT0, "Capcom",  "Black Tiger",                 MACHINE_SUPPORTS_SAVE )
+GAME( 1987, blktigera,  blktiger, mcu,   blktiger, blktiger_mcu_state, empty_init,      ROT0, "Capcom",  "Black Tiger (older)",         MACHINE_SUPPORTS_SAVE )
+GAME( 1987, blktigerb1, blktiger, nomcu, blktiger, blktiger_state,     empty_init,      ROT0, "bootleg", "Black Tiger (bootleg set 1)", MACHINE_SUPPORTS_SAVE )
+GAME( 1987, blktigerb2, blktiger, nomcu, blktiger, blktiger_state,     empty_init,      ROT0, "bootleg", "Black Tiger (bootleg set 2)", MACHINE_SUPPORTS_SAVE )
+GAME( 1987, blkdrgon,   blktiger, mcu,   blktiger, blktiger_mcu_state, empty_init,      ROT0, "Capcom",  "Black Dragon (Japan)",        MACHINE_SUPPORTS_SAVE )
+GAME( 1987, blkdrgonb,  blktiger, nomcu, blktiger, blktiger_state,     empty_init,      ROT0, "bootleg", "Black Dragon (bootleg)",      MACHINE_SUPPORTS_SAVE )
+// this board has Capcom markings (boards 87118-A-X1 / 87118-B-X1, but no MCU, a mix of bootleg Black Tiger and Black Dragon ROMs, and an address swapped sound ROM? is the latter an alternative security measure?
+GAME( 1987, blktigerb3, blktiger, nomcu, blktiger, blktiger_state,     init_blktigerb3, ROT0, "bootleg", "Black Tiger / Black Dragon (mixed bootleg?)", MACHINE_SUPPORTS_SAVE )

snapshots/jotego_jtcores_pr1100/cores/btiger/doc/blktiger_ms.cpp

@@ -0,0 +1,376 @@
+// license:BSD-3-Clause
+// copyright-holders:
+
+/*
+    Black Tiger (Modular System)
+
+    As with most of the 'Modular System' setups, the hardware is heavily modified from the original
+    and consists of a multi-board stack in a cage, hence different driver.
+
+    The Modular System cage contains 6 main boards for this game.
+
+    MOD3-4 - Z80 board (CPU + 5 ROMs + RAM + 24MHz XTAL).
+    MOD21/1 - RAM board? 20 MHz XTAL.
+    MOD1/5 - Sound board (Z80, 2xYM2203C). 2 8-dips banks.
+    MOD51/1 - Sprite board, has logic + 4 sprite ROMs.
+    MOD 4/3 - Tilemap board, has logic + 2 tilemap ROMs, long thin sub-board (CAR-0484/1 SOLD) with no chips, just routing along one edge.
+    MOD 4/3 - Tilemap board, has logic + 4 tilemap ROMs, long thin sub-board (CAR-0484/1 SOLD) with no chips, just routing along one edge.
+
+    TODO: practically everything:
+    - derive from blktiger_state? (eventually, if differences aren't too much)
+    - chars and sprites related functions are copied from blktiger.cpp. Verify differences
+    - correct GFX decoding
+    - tiles
+    - palette
+    - banking: seems to work by accident, tweaking the ROM loading. Pretty sure it's wrong.
+    - where are the sound latch and the other functions that the original has mapped in the io space?
+    - lots of other stuff
+*/
+
+
+#include "emu.h"
+#include "cpu/z80/z80.h"
+#include "machine/gen_latch.h"
+#include "sound/ymopn.h"
+#include "emupal.h"
+#include "screen.h"
+#include "speaker.h"
+#include "tilemap.h"
+
+
+namespace {
+
+class blktiger_ms_state : public driver_device
+{
+public:
+	blktiger_ms_state(const machine_config &mconfig, device_type type, const char *tag) :
+		driver_device(mconfig, type, tag),
+		m_maincpu(*this, "maincpu"),
+		m_screen(*this, "screen"),
+		m_gfxdecode(*this, "gfxdecode"),
+		m_txvideoram(*this, "txvideoram"),
+		m_spriteram(*this, "spriteram")
+	{ }
+
+	void blktigerm(machine_config &config);
+
+	void init_blktigerm();
+
+protected:
+	virtual void machine_start() override;
+	virtual void video_start() override;
+
+private:
+	required_device<cpu_device> m_maincpu;
+	required_device<screen_device> m_screen;
+	required_device<gfxdecode_device> m_gfxdecode;
+
+	required_shared_ptr<uint8_t> m_txvideoram;
+	required_shared_ptr<uint8_t> m_spriteram;
+
+	TILE_GET_INFO_MEMBER(get_tx_tile_info);
+	void txvideoram_w(offs_t offset, uint8_t data);
+	void draw_sprites(bitmap_ind16 &bitmap, const rectangle &cliprect);
+	uint32_t screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
+
+	void main_map(address_map &map);
+	void sound_map(address_map &map);
+
+	tilemap_t *m_tx_tilemap = nullptr;
+};
+
+
+void blktiger_ms_state::main_map(address_map &map)
+{
+	map(0x0000, 0x7fff).rom().region("maincpu", 0);
+	map(0x8000, 0xbfff).bankr("mainbank");
+	map(0xc000, 0xcfff).ram();
+	map(0xc000, 0xc000).portr("IN0");
+	map(0xc001, 0xc001).portr("IN1");
+	map(0xc002, 0xc002).portr("IN2");
+	map(0xc003, 0xc003).portr("DSW0");
+	map(0xc004, 0xc004).portr("DSW1");
+	map(0xd000, 0xd7ff).ram().w(FUNC(blktiger_ms_state::txvideoram_w)).share(m_txvideoram);
+	map(0xd800, 0xd800).lw8(NAME([this] (u8 data) { membank("mainbank")->set_entry(data & 0x0f); })); // very probably wrong
+	map(0xe000, 0xfdff).ram();
+	map(0xfe00, 0xffff).ram().share(m_spriteram);
+}
+
+void blktiger_ms_state::sound_map(address_map &map) // seems similar to toki_ms.cpp and raiden_ms.cpp
+{
+	map(0x0000, 0x7fff).rom().region("audiocpu", 0);
+	map(0xc000, 0xc7ff).ram();
+	map(0xc900, 0xc900).noprw(); // what lives here?
+	map(0xdff8, 0xdff8).r("soundlatch", FUNC(generic_latch_8_device::read));
+	map(0xdff0, 0xdfff).nopw(); // what lives here?
+	map(0xe000, 0xe001).w("ym1", FUNC(ym2203_device::write));
+	map(0xe002, 0xe003).w("ym2", FUNC(ym2203_device::write));
+	map(0xe008, 0xe009).r("ym1", FUNC(ym2203_device::read));
+	map(0xe00a, 0xe00b).r("ym2", FUNC(ym2203_device::read));
+}
+
+void blktiger_ms_state::machine_start()
+{
+	membank("mainbank")->configure_entries(0, 16, memregion("maincpu")->base() + 0x10000, 0x4000);
+}
+
+void blktiger_ms_state::video_start()
+{
+	m_tx_tilemap =  &machine().tilemap().create(*m_gfxdecode, tilemap_get_info_delegate(*this, FUNC(blktiger_ms_state::get_tx_tile_info)), TILEMAP_SCAN_ROWS, 8, 8, 32, 32);
+}
+
+void blktiger_ms_state::txvideoram_w(offs_t offset, uint8_t data)
+{
+	m_txvideoram[offset] = data;
+	m_tx_tilemap->mark_tile_dirty(offset & 0x3ff);
+}
+
+void blktiger_ms_state::draw_sprites(bitmap_ind16 &bitmap, const rectangle &cliprect)
+{
+	for (int offs = m_spriteram.bytes() - 4; offs >= 0; offs -= 4)
+	{
+		int attr = m_spriteram[offs + 1];
+		int sx = m_spriteram[offs + 3] - ((attr & 0x10) << 4);
+		int sy = m_spriteram[offs + 2];
+		int code = m_spriteram[offs] | ((attr & 0xe0) << 3);
+		int color = attr & 0x07;
+		int flipx = attr & 0x08;
+
+		if (flip_screen())
+		{
+			sx = 240 - sx;
+			sy = 240 - sy;
+			flipx = !flipx;
+		}
+
+		m_gfxdecode->gfx(1)->transpen(bitmap, cliprect,
+				code,
+				color,
+				flipx, flip_screen(),
+				sx, sy, 15);
+	}
+}
+
+uint32_t blktiger_ms_state::screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect)
+{
+	m_tx_tilemap->draw(screen, bitmap, cliprect, 0, 0);
+
+	draw_sprites(bitmap, cliprect);
+
+	return 0;
+}
+
+TILE_GET_INFO_MEMBER(blktiger_ms_state::get_tx_tile_info)
+{
+	uint8_t attr = m_txvideoram[tile_index + 0x400];
+	tileinfo.set(0,
+			m_txvideoram[tile_index] + ((attr & 0xe0) << 3),
+			attr & 0x1f,
+			0);
+}
+
+static INPUT_PORTS_START( blktigerm )
+	PORT_START("IN0")
+	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_START1 )
+	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_START2 )
+	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
+	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNKNOWN )
+	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_UNKNOWN )
+	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_SERVICE1 )
+	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_COIN1 )
+	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_COIN2 )
+
+	PORT_START("IN1")
+	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY
+	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY
+	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY
+	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY
+	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 )
+	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON2 )
+	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
+	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
+
+	PORT_START("IN2")
+	PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_8WAY PORT_COCKTAIL
+	PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_8WAY PORT_COCKTAIL
+	PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_8WAY PORT_COCKTAIL
+	PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_8WAY PORT_COCKTAIL
+	PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_COCKTAIL
+	PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_BUTTON2 ) PORT_COCKTAIL
+	PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
+	PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
+
+	PORT_START("DSW0")
+	PORT_DIPNAME( 0x07, 0x07, DEF_STR( Coin_A ) )       PORT_DIPLOCATION( "SW1:1,2,3" )
+	PORT_DIPSETTING(    0x00, DEF_STR( 4C_1C ) )
+	PORT_DIPSETTING(    0x01, DEF_STR( 3C_1C ) )
+	PORT_DIPSETTING(    0x02, DEF_STR( 2C_1C ) )
+	PORT_DIPSETTING(    0x07, DEF_STR( 1C_1C ) )
+	PORT_DIPSETTING(    0x06, DEF_STR( 1C_2C ) )
+	PORT_DIPSETTING(    0x05, DEF_STR( 1C_3C ) )
+	PORT_DIPSETTING(    0x04, DEF_STR( 1C_4C ) )
+	PORT_DIPSETTING(    0x03, DEF_STR( 1C_5C ) )
+	PORT_DIPNAME( 0x38, 0x38, DEF_STR( Coin_B ) )       PORT_DIPLOCATION( "SW1:4,5,6" )
+	PORT_DIPSETTING(    0x00, DEF_STR( 4C_1C ) )
+	PORT_DIPSETTING(    0x08, DEF_STR( 3C_1C ) )
+	PORT_DIPSETTING(    0x10, DEF_STR( 2C_1C ) )
+	PORT_DIPSETTING(    0x38, DEF_STR( 1C_1C ) )
+	PORT_DIPSETTING(    0x30, DEF_STR( 1C_2C ) )
+	PORT_DIPSETTING(    0x28, DEF_STR( 1C_3C ) )
+	PORT_DIPSETTING(    0x20, DEF_STR( 1C_4C ) )
+	PORT_DIPSETTING(    0x18, DEF_STR( 1C_5C ) )
+	PORT_DIPNAME( 0x40, 0x40, DEF_STR( Flip_Screen ) )  PORT_DIPLOCATION( "SW1:7" )
+	PORT_DIPSETTING(    0x40, DEF_STR( Off ) )
+	PORT_DIPSETTING(    0x00, DEF_STR( On ) )
+	PORT_DIPNAME( 0x80, 0x80, DEF_STR( Test ) )         PORT_DIPLOCATION( "SW1:8" )
+	PORT_DIPSETTING(    0x80, DEF_STR( Off ) )
+	PORT_DIPSETTING(    0x00, DEF_STR( On ) )
+
+	PORT_START("DSW1")
+	PORT_DIPNAME( 0x03, 0x03, DEF_STR( Lives ) )        PORT_DIPLOCATION( "SW2:1,2" )
+	PORT_DIPSETTING(    0x02, "2" )
+	PORT_DIPSETTING(    0x03, "3" )
+	PORT_DIPSETTING(    0x01, "5" )
+	PORT_DIPSETTING(    0x00, "7")
+	PORT_DIPNAME( 0x1c, 0x0c, DEF_STR( Difficulty ) )   PORT_DIPLOCATION( "SW2:3,4,5" )
+	PORT_DIPSETTING(    0x1c, "1 (Easiest)")
+	PORT_DIPSETTING(    0x18, "2" )
+	PORT_DIPSETTING(    0x14, "3" )
+	PORT_DIPSETTING(    0x10, "4" )
+	PORT_DIPSETTING(    0x0c, "5 (Normal)" )
+	PORT_DIPSETTING(    0x08, "6" )
+	PORT_DIPSETTING(    0x04, "7" )
+	PORT_DIPSETTING(    0x00, "8 (Hardest)" )
+	PORT_DIPNAME( 0x20, 0x20, DEF_STR( Demo_Sounds ) )  PORT_DIPLOCATION( "SW2:6" )
+	PORT_DIPSETTING(    0x00, DEF_STR( Off ) )
+	PORT_DIPSETTING(    0x20, DEF_STR( On ) )
+	PORT_DIPNAME( 0x40, 0x40, DEF_STR( Allow_Continue ) )   PORT_DIPLOCATION( "SW2:7" )
+	PORT_DIPSETTING(    0x00, DEF_STR( No ) )
+	PORT_DIPSETTING(    0x40, DEF_STR( Yes ) )
+	PORT_DIPNAME( 0x80, 0x00, DEF_STR( Cabinet ) )      PORT_DIPLOCATION( "SW2:8" )
+	PORT_DIPSETTING(    0x00, DEF_STR( Upright ) )
+	PORT_DIPSETTING(    0x80, DEF_STR( Cocktail ) )
+INPUT_PORTS_END
+
+static const gfx_layout charlayout =
+{
+	8,8,
+	RGN_FRAC(1,4),
+	4,
+	{ RGN_FRAC(0,4), RGN_FRAC(1,4), RGN_FRAC(2,4), RGN_FRAC(3,4) },
+	{ 0, 1, 2, 3, 4, 5, 6, 7 },
+	{ 0*8, 1*8, 2*8, 3*8, 4*8, 5*8, 6*8, 7*8 },
+	8*8
+};
+
+static const gfx_layout tiles16x16x4_layout =
+{
+	16,16,
+	RGN_FRAC(1,1),
+	4,
+	{ 0,8,16,24 },
+	{ 0,1,2,3,4,5,6,7, 512,513,514,515,516,517,518,519 },
+	{ STEP16(0,32) },
+	16 * 16 * 4
+};
+
+static GFXDECODE_START( gfx_blktiger_ms )
+	GFXDECODE_ENTRY( "chars", 0, charlayout, 0x300, 32 )
+	GFXDECODE_ENTRY( "sprites", 0, tiles16x16x4_layout, 0x100, 32 )
+GFXDECODE_END
+
+void blktiger_ms_state::blktigerm(machine_config &config)
+{
+	// basic machine hardware
+	Z80(config, m_maincpu, 24_MHz_XTAL / 4); // divisor unknown
+	m_maincpu->set_addrmap(AS_PROGRAM, &blktiger_ms_state::main_map);
+	m_maincpu->set_vblank_int("screen", FUNC(blktiger_ms_state::irq0_line_hold));
+
+	z80_device &audiocpu(Z80(config, "audiocpu", 24_MHz_XTAL / 8)); // divisor unknown, no XTAL on the PCB, might also use the 20 MHz one
+	audiocpu.set_addrmap(AS_PROGRAM, &blktiger_ms_state::sound_map);
+
+	// video hardware
+	SCREEN(config, m_screen, SCREEN_TYPE_RASTER); // all wrong
+	m_screen->set_refresh_hz(60);
+	m_screen->set_vblank_time(ATTOSECONDS_IN_USEC(0));
+	m_screen->set_size(32*8, 32*8);
+	m_screen->set_visarea(0*8, 32*8-1, 2*8, 30*8-1);
+	m_screen->set_screen_update(FUNC(blktiger_ms_state::screen_update));
+	m_screen->set_palette("palette");
+
+	PALETTE(config, "palette").set_format(palette_device::xBRG_444, 1024);
+
+	GFXDECODE(config, "gfxdecode", "palette", gfx_blktiger_ms);
+
+	// sound hardware
+	SPEAKER(config, "mono").front_center();
+
+	GENERIC_LATCH_8(config, "soundlatch");
+
+	YM2203(config, "ym1", 24_MHz_XTAL / 8).add_route(ALL_OUTPUTS, "mono", 0.15); // divisor unknown, no XTAL on the PCB, might also use the 20 MHz one
+
+	YM2203(config, "ym2", 24_MHz_XTAL / 8).add_route(ALL_OUTPUTS, "mono", 0.15); // divisor unknown, no XTAL on the PCB, might also use the 20 MHz one
+}
+
+ROM_START( blktigerm )
+	ROM_REGION( 0x50000, "maincpu", 0 ) // on MOD 3/4 board
+	ROM_LOAD( "3_bl_301.ic14",   0x00000, 0x08000, CRC(b4525312) SHA1(958ce9a7f41422f3011412e4a16dd3ad65019733) )
+	ROM_LOAD( "3_bl_304.ic18",   0x10000, 0x10000, CRC(36f669c6) SHA1(e91fd222919904d4d4b3ef70a22ab599a7cfa263) )
+	ROM_LOAD( "3_bl_305.ic19",   0x20000, 0x10000, CRC(b30a99af) SHA1(19d6dbe11ffeb9a21dbfe75eb39ce9ceaef5eb31) )
+	ROM_LOAD( "3_bl_302_c.ic13", 0x30000, 0x10000, CRC(c943415f) SHA1(08e82d2557de01c979a0a58b5433e9bdcdb118cb) )
+	ROM_LOAD( "3_bl_303_b.ic12", 0x40000, 0x10000, CRC(72114f6b) SHA1(049e747431cd95db2e7414467754424f68a8d757) )
+
+	ROM_REGION( 0x8000, "audiocpu", 0 )
+	ROM_LOAD( "1_bl_101.ic12",  0x0000, 0x8000, CRC(14028686) SHA1(64dc219d906f1bdd0c2bc05aff5aa73e001a6901) )
+
+	ROM_REGION( 0x10000, "chars", ROMREGION_INVERT ) // on one of the MOD 4/3 boards, both ROMs 0xxxxxxxxxxxxxx = 0xFF
+	ROM_LOAD( "4_bl_401.ic17",  0x0000, 0x8000, CRC(ab1afb3d) SHA1(555332ccfb69e65b776f94ffac9a4a051fb6f09e) )
+	ROM_LOAD( "4_bl_402.ic16",  0x8000, 0x8000, CRC(89445b11) SHA1(7d9ab6e88d7de3a0e31b3b8a5e57dd39afd7940d) )
+
+	ROM_REGION( 0x40000, "tiles", 0 ) // on the other MOD 4/3 board
+	ROM_LOAD32_BYTE( "4_a_bl_4a01.ic17",  0x00003, 0x10000, CRC(fc00fd6c) SHA1(066714421fa782c6cfad9f695f05e6e3551ffdc7) )
+	ROM_LOAD32_BYTE( "4_a_bl_4a02.ic16",  0x00002, 0x10000, CRC(49cd8afa) SHA1(147b65dad4f05b940d1f7a4028f5748ba1b7daa5) )
+	ROM_LOAD32_BYTE( "4_a_bl_4a03.ic15",  0x00001, 0x10000, CRC(50207dd4) SHA1(bee343fbefc817fa14b8b303f013bf5b89e911f8) )
+	ROM_LOAD32_BYTE( "4_a_bl_4a04.ic14",  0x00000, 0x10000, CRC(4bb0c1ba) SHA1(9433c78f0de7cb1f92b22612b9f3c51d813b025a) )
+
+	ROM_REGION( 0x40000, "sprites", ROMREGION_INVERT ) // on MOD 51/1 board
+	ROM_LOAD32_BYTE( "51_bl_501.ic43",   0x00003, 0x10000, CRC(ace32b94) SHA1(4a09e8dc73bd16f7d378aefbe5d433dd1396f97d) )
+	ROM_LOAD32_BYTE( "51_bl_502.ic42",   0x00002, 0x10000, CRC(f6c4cc0b) SHA1(678fd71e90237f8e19eae78fe150a4c5d3494c6c) )
+	ROM_LOAD32_BYTE( "51_bl_503.ic41",   0x00001, 0x10000, CRC(61e3ae0b) SHA1(cbb83827f027acd6b905f4210476810bcd4b03a9) )
+	ROM_LOAD32_BYTE( "51_bl_504.ic40",   0x00000, 0x10000, CRC(2cb45034) SHA1(b2fd3b7b7b9d68b6ff1985166b106e65b17dbb23) )
+
+	ROM_REGION( 0x0700, "proms", 0 )    // PROMs (function unknown)
+	ROM_LOAD( "1_p0101_82s123.ic20",       0x0000, 0x0020, CRC(3fd60d3a) SHA1(8100fa7453638ac40193b5d92404f41b101ed2cc) )
+	ROM_LOAD( "21_p0201_82s129.ic4",       0x0100, 0x0100, CRC(2697da58) SHA1(e62516b886ff6e204b718e5f0c6ce2712e4b7fc5) )
+	ROM_LOAD( "21_p0202_82s129.ic12",      0x0200, 0x0100, CRC(e434128a) SHA1(ef0f6d8daef8b25211095577a182cdf120a272c1) )
+	ROM_LOAD( "3_subcpu_p0322_82s147.bin", 0x0300, 0x0200, CRC(6d427336) SHA1(6ce1ef41df2b450fafe11c3021991618bdb771ed) )
+	ROM_LOAD( "4_a_bl_82s123.ic13",        0x0500, 0x0020, CRC(671f1183) SHA1(dbc21c3922c5e69340daa9008e1200f1304b3e8f) )
+	ROM_LOAD( "51_p0502_82s129.ic10",      0x0600, 0x0100, CRC(15085e44) SHA1(646e7100fcb112594023cf02be036bd3d42cc13c) )
+
+	ROM_REGION( 0x1000, "plds", ROMREGION_ERASEFF )
+	ROM_LOAD( "4_p0403_pal16r8a-2cn.ic29",      0x000, 0x104, CRC(506156cc) SHA1(5560671fc2c9872ed28620491af5dc486909fc6e) )
+	ROM_LOAD( "4_a_p0403_pal16r8a-2cn.ic29",    0x000, 0x104, CRC(506156cc) SHA1(5560671fc2c9872ed28620491af5dc486909fc6e) ) // identical to the above one (same PCB type)
+	ROM_LOAD( "51_p0503_pal16r8a.ic56",         0x000, 0x104, CRC(07eb86d2) SHA1(482eb325df5bc60353bac85412cf45429cd03c6d) )
+ROM_END
+
+void blktiger_ms_state::init_blktigerm()
+{
+	uint8_t *const src = memregion("maincpu")->base();
+	int const len = 0x50000;
+
+	// bitswap data
+	for (int i = 0; i < len; i++)
+		src[i] = bitswap<8>(src[i], 5, 3, 7, 2, 0, 1, 4, 6);
+
+	// descramble address
+	std::vector<uint8_t> buffer(len);
+	memcpy(&buffer[0], src, len);
+
+	for (int i = 0; i < len; i++)
+		src[i] = buffer[bitswap<24>(i, 23, 22, 21, 20, 19, 18, 17, 16, 15, 14, 13, 12, 10, 8, 6, 4, 0, 2, 7, 3, 1, 9, 11, 5)];
+}
+
+} // Anonymous namespace
+
+
+GAME( 1991, blktigerm,  blktiger,  blktigerm,  blktigerm,  blktiger_ms_state, init_blktigerm, ROT0, "bootleg (Gaelco / Ervisa)", "Black Tiger (Modular System)", MACHINE_IS_SKELETON )

snapshots/jotego_jtcores_pr1100/cores/btiger/doc/scan.cc

@@ -0,0 +1,35 @@
+#include <iostream>
+#include <iomanip>
+
+using namespace std;
+
+int bg8x4_scan(int col, int row ) {
+    return (col & 0x0f) + ((row & 0x0f) << 4) + ((col & 0x70) << 4) + ((row & 0x30) << 7);
+}
+
+int bg4x8_scan(int col, int row ) {
+    return (col & 0x0f) + ((row & 0x0f) << 4) + ((col & 0x30) << 4) + ((row & 0x70) << 6);
+}
+
+void all_8x4() {    
+    for( int row=0; row<64; row++ ) {
+        for( int col=0; col<128; col++ ) {
+            cout << hex << row << '\t' << hex << col << '\t' 
+                << hex << bg8x4_scan(row,col) << '\n';
+        }
+    }
+}
+
+void all_4x8() {    
+    for( int row=0; row<128; row++ ) {
+        for( int col=0; col<64; col++ ) {
+            cout << hex << row << '\t' << hex << col << '\t' 
+                << hex << bg4x8_scan(row,col) << '\n';
+        }
+    }
+}
+
+int main() {
+    //all_4x8();
+    all_8x4();
+}

snapshots/jotego_jtcores_pr1100/cores/btiger/hdl/jtbtiger_colmix.v

@@ -0,0 +1,141 @@
+/*  This file is part of JTCORES.
+    JTCORES program is free software: you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation, either version 3 of the License, or
+    (at your option) any later version.
+
+    JTCORES program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with JTCORES.  If not, see <http://www.gnu.org/licenses/>.
+
+    Author: Jose Tejada Gomez. Twitter: @topapate
+    Version: 1.0
+    Date: 20-11-2019 */
+
+// bd02.9j is probably the priority PROM. It isn't really worth using
+// as the content is quite plain
+
+
+module jtbtiger_colmix(
+    input            rst,
+    input            clk,
+    input            cen12,
+    input            cen6 /* synthesis direct_enable = 1 */,
+
+    // pixel input from generator modules
+    input [6:0]      char_pxl,        // character color code
+    input [7:0]      scr_pxl,
+    input [6:0]      obj_pxl,
+    input            preLVBL,
+    input            preLHBL,
+    output           LHBL,
+    output           LVBL,
+
+    // CPU inteface
+    input [9:0]      AB,
+    input            blue_cs,
+    input            redgreen_cs,
+    input [7:0]      DB,
+
+    output     [3:0] red,
+    output     [3:0] green,
+    output     [3:0] blue,
+    // Priority PROMs bd01.8j
+    input [7:0]     prog_addr,
+    input           prom_prior_we,
+    input [3:0]     prom_din
+);
+
+reg  [9:0] pixel_mux;
+
+wire char_blank  = &char_pxl[1:0];
+wire obj_blank   = &obj_pxl [3:0];
+
+reg  [2:0] obj_sel; // signals whether an object pixel is selected
+
+reg  [7:0] seladdr;
+wire [3:0] selbus;
+
+reg  [7:0] scr0;
+reg  [6:0] char0, obj0;
+
+wire [1:0] scr_prio = scr_pxl[6:5] + 2'b01;
+
+always @(posedge clk) if(cen6) begin
+    seladdr <= { ~char_blank, ~obj_blank,
+        scr_pxl[7] ? 2'b00 : {scr_prio}, scr_pxl[3:0] };
+    scr0  <= scr_pxl;
+    char0 <= char_pxl;
+    obj0  <= obj_pxl;
+
+    obj_sel[2] <= obj_sel[1];
+    obj_sel[1] <= obj_sel[0];
+    obj_sel[0] <= 1'b0;
+
+    pixel_mux[9:8] <= selbus[3:2];
+    case( selbus[1:0] )
+        2'b11: pixel_mux[7:0] <= { 1'b0, char0 };
+        2'b10: pixel_mux[7:0] <= scr0;
+        2'b01: begin
+            pixel_mux[7:0] <= { 1'b0, obj0 };
+            obj_sel[0] <= 1'b1;
+        end
+        2'b00: pixel_mux[7:0] <= 8'd0; // this value is a guess
+    endcase
+end
+
+wire [3:0] pal_red, pal_green, pal_blue;
+
+// Palette is in RAM
+wire we_rg = /* !LVBL && */ redgreen_cs;
+wire we_b  = /* !LVBL && */ blue_cs;
+
+jtgng_dual_ram #(.AW(10),.SIMFILE("rg_ram.bin")) u_redgreen(
+    .clk        ( clk         ),
+    .clk_en     ( cen6        ), // clock enable only applies to write operation
+    .data       ( DB          ),
+    .rd_addr    ( pixel_mux   ),
+    .wr_addr    ( AB          ),
+    .we         ( we_rg       ),
+    .q          ( {pal_red, pal_green}     )
+);
+
+jtgng_dual_ram #(.AW(10),.DW(4),.SIMFILE("b_ram.bin")) u_blue(
+    .clk        ( clk         ),
+    .clk_en     ( cen6        ), // clock enable only applies to write operation
+    .data       ( DB[3:0]     ),
+    .rd_addr    ( pixel_mux   ),
+    .wr_addr    ( AB          ),
+    .we         ( we_b        ),
+    .q          ( pal_blue    )
+);
+
+// Clock must be faster than 6MHz so selbus is ready for the next
+// 6MHz clock cycle:
+jtframe_prom #(.AW(8),.DW(4),.SIMFILE("../../../rom/btiger/bd01.8j")) u_selbus(
+    .clk    ( clk           ),
+    .cen    ( cen12         ),
+    .data   ( prom_din      ),
+    .rd_addr( seladdr       ),
+    .wr_addr( prog_addr     ),
+    .we     ( prom_prior_we ),
+    .q      ( selbus        )
+);
+
+jtframe_blank #(.DLY(8),.DW(12)) u_dly(
+    .clk        ( clk                 ),
+    .pxl_cen    ( cen6                ),
+    .preLHBL    ( preLHBL             ),
+    .preLVBL    ( preLVBL             ),
+    .LHBL       ( LHBL                ),
+    .LVBL       ( LVBL                ),
+    .rgb_in     ( {pal_red, pal_green, pal_blue} ),
+    .preLBL     (                     ),
+    .rgb_out    ( {red, green, blue } )
+);
+
+endmodule // jtgng_colmix

snapshots/jotego_jtcores_pr1100/cores/btiger/hdl/jtbtiger_game.v

@@ -0,0 +1,288 @@
+/*  This file is part of JTCORES.
+    JTCORES program is free software: you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation, either version 3 of the License, or
+    (at your option) any later version.
+
+    JTCORES program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with JTCORES.  If not, see <http://www.gnu.org/licenses/>.
+
+    Author: Jose Tejada Gomez. Twitter: @topapate
+    Version: 1.0
+    Date: 18-11-2019 */
+
+module jtbtiger_game(
+    `include "jtframe_game_ports.inc" // see $JTFRAME/hdl/inc/jtframe_game_ports.inc
+);
+
+localparam [25:0]   OBJ_START  = `JTFRAME_BA3_START,
+                    PROM_START = `JTFRAME_PROM_START,
+                    MCUOVER    = PROM_START+26'h1000;
+
+wire [12:0] cpu_AB;
+wire [10:0] scr_hpos, scr_vpos;
+wire [ 8:0] obj_AB, V, H;
+wire [ 7:0] mcu_din, mcu_dout, cpu_dout, char_dout, scr_dout, snd_latch, main_ram;
+wire [ 4:0] prom;
+wire [ 1:0] scr_bank;
+wire        mcu_wr, mcu_rd, preLHBL, preLVBL, sres_b,
+            cen12, cen6, cen3, cen1p5, cenfm,
+            cen8, RnW, blue_cs, redgreen_cs, CHRON, SCRON, OBJON,
+            OKOUT, blcnten, bus_req, bus_ack, LHBL_obj, LVBL_obj,
+            rd, cpu_cen, char_busy, scr_busy, mcuover,
+            scr_layout, HINIT, char_cs, flip, scr_cs;
+reg         pause;
+wire        prom_prior_we = prom[0];
+wire        prom_mcu      = prom[4];
+
+assign debug_view  = { 5'd0, OBJON, SCRON, CHRON };
+assign dip_flip    = ~dipsw[6];
+assign pxl2_cen    = cen12;
+assign pxl_cen     = cen6;
+assign mcuover     = ioctl_addr>=MCUOVER;
+assign prom[0] = prom_we &&  mcuover && ioctl_addr[10:8]==0;
+assign prom[1] = prom_we &&  mcuover && ioctl_addr[10:8]==1;
+assign prom[2] = prom_we &&  mcuover && ioctl_addr[10:8]==2;
+assign prom[3] = prom_we &&  mcuover && ioctl_addr[10:8]==3;
+assign prom[4] = prom_we && !mcuover;
+/* verilator tracing_off */
+always @(posedge clk) pause <= ~dip_pause;
+
+always @* begin
+    post_addr = prog_addr;
+    if( ioctl_addr >= OBJ_START ) begin
+        post_addr[5:1] = {prog_addr[4:1],prog_addr[5]};
+    end
+end
+/* verilator lint_off PINMISSING */
+jtframe_cen48 u_cen(
+    .clk    ( clk       ),
+    .cen12  ( cen12     ),
+    .cen12b (           ),
+    .cen8   ( cen8      ),
+    .cen6   ( cen6      ),
+    .cen6b  (           ),
+    .cen3   ( cen3      ),
+    .cen1p5 ( cen1p5    )
+);
+
+jtframe_cen3p57 u_cen3p57(
+    .clk      ( clk       ),
+    .cen_3p57 ( cenfm     ),
+    .cen_1p78 (           )     // unused
+);/* verilator lint_on PINMISSING */
+
+jtgng_timer u_timer(
+    .clk       ( clk      ),
+    .cen6      ( cen6     ),
+    .V         ( V        ),
+    .H         ( H        ),
+    .Hinit     ( HINIT    ),
+    .LHBL      ( preLHBL  ),
+    .LVBL      ( preLVBL  ),
+    .LHBL_obj  ( LHBL_obj ),
+    .LVBL_obj  ( LVBL_obj ),
+    .HS        ( HS       ),
+    .VS        ( VS       ),
+    .Vinit     (          )
+);
+
+`ifndef NOMAIN
+jtbtiger_main u_main(
+    .rst        ( rst           ),
+    .clk        ( clk           ),
+    .cen6       ( cen6          ),
+    .cen3       ( cen3          ),
+    .cpu_cen    ( cpu_cen       ),
+    // Timing
+    .flip       ( flip          ),
+    .V          ( V             ),
+    .LHBL       ( LHBL          ),
+    .LVBL       ( LVBL          ),
+    .H1         ( H[0]          ),
+    // Palette
+    .blue_cs    ( blue_cs       ),
+    .redgreen_cs( redgreen_cs   ),
+    // sound
+    .sres_b     ( sres_b        ),
+    .snd_latch  ( snd_latch     ),
+    // security
+    .mcu_din    ( mcu_din       ),
+    .mcu_dout   ( mcu_dout      ),
+    .mcu_wr     ( mcu_wr        ),
+    .mcu_rd     ( mcu_rd        ),
+    // CHAR
+    .char_dout  ( char_dout     ),
+    .cpu_dout   ( cpu_dout      ),
+    .char_cs    ( char_cs       ),
+    .char_busy  ( char_busy     ),
+    .CHRON      ( CHRON         ),
+    // SCROLL
+    .scr_dout   ( scr_dout      ),
+    .scr_cs     ( scr_cs        ),
+    .scr_busy   ( scr_busy      ),
+    .scr_hpos   ( scr_hpos      ),
+    .scr_vpos   ( scr_vpos      ),
+    .SCRON      ( SCRON         ),
+    .scr_bank   ( scr_bank      ),
+    .scr_layout ( scr_layout    ),
+    // OBJ - bus sharing
+    .obj_AB     ( obj_AB        ),
+    .cpu_AB     ( cpu_AB        ),
+    .ram_dout   ( main_ram      ),
+    .OKOUT      ( OKOUT         ),
+    .blcnten    ( blcnten       ),
+    .bus_req    ( bus_req       ),
+    .bus_ack    ( bus_ack       ),
+    .OBJON      ( OBJON         ),
+    // ROM
+    .rom_cs     ( main_cs       ),
+    .rom_addr   ( main_addr     ),
+    .rom_data   ( main_data     ),
+    .rom_ok     ( main_ok       ),
+    // Cabinet input
+    .cab_1p     ( cab_1p[1:0]   ),
+    .coin       ( coin[1:0]     ),
+    .service    ( service       ),
+    .joystick1  ( joystick1[5:0]),
+    .joystick2  ( joystick2[5:0]),
+
+    .RnW        ( RnW           ),
+    // DIP switches
+    .dip_pause  ( dip_pause     ),
+    .dipsw_a    ( dipsw[15:8]   ),
+    .dipsw_b    ( dipsw[ 7:0]   )
+);
+`else
+assign main_addr   = 19'd0;
+assign char_cs     = 1'b0;
+assign scr_cs      = 1'b0;
+assign bus_ack     = 1'b0;
+assign flip        = 1'b0;
+assign RnW         = 1'b1;
+assign scr_hpos    = 9'd0;
+assign scr_vpos    = 9'd0;
+assign cpu_cen     = cen3;
+assign scr_layout  = 1'b0;
+assign scr_bank    = 2'b0;
+`endif
+
+`ifndef NOMCU
+jtbtiger_mcu u_mcu(
+    .rst        (  rst24      ),
+    .clk        (  clk24      ),
+    .clk_rom    (  clk        ),
+    .LVBL       ( LVBL        ),
+    .mcu_dout   (  mcu_dout   ),
+    .mcu_din    (  mcu_din    ),
+    .mcu_wr     (  mcu_wr     ),
+    .mcu_rd     (  mcu_rd     ),
+    .prog_addr  (  prog_addr[11:0]  ),
+    .prom_din   (  prog_data  ),
+    .prom_we    (  prom_mcu   )
+);
+`else
+assign mcu_dout = 8'hff;
+`endif
+
+jtgng_sound #(.LAYOUT(4)) u_sound (
+    .rst            ( rst            ),
+    .clk            ( clk            ),
+    .cen3           ( cenfm          ),
+    .cen1p5         ( cenfm          ),
+    // Interface with main CPU
+    .sres_b         ( sres_b         ),
+    .snd_latch      ( snd_latch      ),
+    .snd_int        ( 1'b0           ),
+    // ROM
+    .rom_addr       ( snd_addr       ),
+    .rom_data       ( snd_data       ),
+    .rom_cs         ( snd_cs         ),
+    .rom_ok         ( snd_ok         ),
+    // sound output
+    .fm0            ( fm0            ),
+    .fm1            ( fm1            ),
+    .psg0           ( psg0           ),
+    .psg1           ( psg1           ),
+    // Unused
+    .mcu_sdin       ( 8'd0           ),
+    .mcu_srd        (                ),
+    .snd2_latch     (                ),
+    .debug_view     (                ),
+    .debug_bus      ( debug_bus      )
+);
+
+jtbtiger_video u_video(
+    .rst        ( rst           ),
+    .clk        ( clk           ),
+    .cen12      ( cen12         ),
+    .cen8       ( cen8          ),
+    .cen6       ( cen6          ),
+    .cen3       ( cen3          ),
+    .cpu_cen    ( cpu_cen       ),
+    .cpu_AB     ( cpu_AB[11:0]  ),
+    .V          ( V[7:0]        ),
+    .H          ( H             ),
+    .RnW        ( RnW           ),
+    .flip       ( flip          ),
+    .cpu_dout   ( cpu_dout      ),
+    .pause      ( pause         ),
+    // CHAR
+    .char_cs    ( char_cs       ),
+    .char_dout  ( char_dout     ),
+    .char_addr  ( char_addr     ),
+    .char_data  ( char_data     ),
+    .char_busy  ( char_busy     ),
+    .char_ok    ( char_ok       ),
+    .CHRON      ( CHRON         ),
+    // SCROLL - ROM
+    .scr_cs     ( scr_cs        ),
+    .scr_dout   ( scr_dout      ),
+    .scr_addr   ( scr_addr      ),
+    .scr_data   ( scr_data      ),
+    .scr_busy   ( scr_busy      ),
+    .scr_hpos   ( scr_hpos      ),
+    .scr_vpos   ( scr_vpos      ),
+    .scr_ok     ( scr_ok        ),
+    .scr_bank   ( scr_bank      ),
+    .scr_layout ( scr_layout    ),
+    .SCRON      ( SCRON         ),
+    // OBJ
+    .HINIT      ( HINIT         ),
+    .obj_AB     ( obj_AB        ),
+    .main_ram   ( main_ram      ),
+    .obj_addr   ( obj_addr      ),
+    .obj_data   ( obj_data      ),
+    .obj_ok     ( obj_ok        ),
+    .OKOUT      ( OKOUT         ),
+    .bus_req    ( bus_req       ), // Request bus
+    .bus_ack    ( bus_ack       ), // bus acknowledge
+    .blcnten    ( blcnten       ), // bus line counter enable
+    .OBJON      ( OBJON         ),
+    // PROMs
+    .prog_addr    ( prog_addr[7:0]),
+    .prom_prior_we( prom_prior_we ),
+    .prom_din     ( prog_data[3:0]),
+    // Palette RAM
+    .blue_cs    ( blue_cs       ),
+    .redgreen_cs( redgreen_cs   ),
+    // Color Mix
+    .preLHBL    ( preLHBL       ),
+    .preLVBL    ( preLVBL       ),
+    .LHBL_obj   ( LHBL_obj      ),
+    .LVBL_obj   ( LVBL_obj      ),
+    .LHBL       ( LHBL          ),
+    .LVBL       ( LVBL          ),
+    .gfx_en     ( gfx_en        ),
+    // Pixel Output
+    .red        ( red           ),
+    .green      ( green         ),
+    .blue       ( blue          )
+);
+
+endmodule

snapshots/jotego_jtcores_pr1100/cores/btiger/hdl/jtbtiger_main.v

@@ -0,0 +1,342 @@
+/*  This file is part of JTCORES.
+    JTCORES program is free software: you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation, either version 3 of the License, or
+    (at your option) any later version.
+
+    JTCORES program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with JTCORES.  If not, see <http://www.gnu.org/licenses/>.
+
+    Author: Jose Tejada Gomez. Twitter: @topapate
+    Version: 1.0
+    Date: 18-11-2019 */
+
+
+module jtbtiger_main(
+    input              rst,
+    input              clk,
+    input              cen6,   // 6MHz
+    input              cen3    /* synthesis direct_enable = 1 */,   // 3MHz
+    output             cpu_cen,
+    // Timing
+    output  reg        flip,
+    output  reg        blue_cs,
+    output  reg        redgreen_cs,
+    input   [8:0]      V,
+    input              LHBL,
+    input              LVBL,
+    input              H1,
+    // Sound
+    output  reg        sres_b, // sound reset
+    output  reg  [7:0] snd_latch,
+    // Characters
+    input        [7:0] char_dout,
+    output       [7:0] cpu_dout,
+    output  reg        char_cs,
+    input              char_busy,
+    // scroll
+    input   [7:0]      scr_dout,
+    output  reg        scr_cs,
+    input              scr_busy,
+    output reg [10:0]  scr_hpos,
+    output reg [10:0]  scr_vpos,
+    output reg [1:0]   scr_bank,
+    output reg         scr_layout,
+    output  reg        CHRON,
+    output  reg        SCRON,
+    output  reg        OBJON,
+    // Security
+    input      [7:0]   mcu_dout,
+    output reg [7:0]   mcu_din,
+    output reg         mcu_wr,
+    output reg         mcu_rd,
+    // cabinet I/O
+    input   [5:0]      joystick1,
+    input   [5:0]      joystick2,
+    input   [1:0]      cab_1p,
+    input   [1:0]      coin,
+    // BUS sharing
+    output  [12:0]     cpu_AB,
+    output  [ 7:0]     ram_dout,
+    input   [ 8:0]     obj_AB,
+    output             RnW,
+    output  reg        OKOUT,
+    input              bus_req,  // Request bus
+    output             bus_ack,  // bus acknowledge
+    input              blcnten,  // bus line counter enable
+    // ROM access
+    output  reg        rom_cs,
+    output  reg [18:0] rom_addr,
+    input       [ 7:0] rom_data,
+    input              rom_ok,
+    // DIP switches
+    input              service,
+    input              dip_pause,
+    input    [7:0]     dipsw_a,
+    input    [7:0]     dipsw_b
+);
+
+wire [15:0] A;
+wire t80_rst_n;
+reg in_cs, ram_cs, bank_cs, scrpos_cs, snd_latch_cs;
+wire rd_n, wr_n;
+
+assign RnW = wr_n;
+
+wire mreq_n, rfsh_n, busak_n;
+assign cpu_cen = cen6;
+assign bus_ack = ~busak_n;
+
+reg [7:0] cpu_din;
+wire iorq_n, m1_n;
+wire irq_ack = !iorq_n && !m1_n;
+
+// Memory map
+always @(*) begin
+    rom_cs        = 1'b0;
+    ram_cs        = 1'b0;
+    char_cs       = 1'b0;
+    scr_cs        = 1'b0;
+    blue_cs       = 1'b0;
+    redgreen_cs   = 1'b0;
+    if( rfsh_n && !mreq_n ) casez(A[15:13])
+        3'b0??: rom_cs = 1'b1;
+        3'b10?: rom_cs = 1'b1; // banked ROM
+        3'b110: // CXXX, DXXX
+            casez(A[12:11])
+                2'b0?: // C0
+                    scr_cs = 1'b1;
+                2'b10: // D0
+                    char_cs = 1'b1; // D0CS
+                2'b11: // D8
+                    if( A[10] )
+                        blue_cs     = 1'b1;
+                    else
+                        redgreen_cs = 1'b1;
+                default:;
+            endcase
+        3'b111: ram_cs = 1'b1; // EXXX, FXXX
+    endcase
+end
+
+// Port map
+reg en_cs, scr_bank_cs, mcu_cs, video_cs, layout_cs;
+
+always @(*) begin
+    snd_latch_cs  = 1'b0;
+    bank_cs       = 1'b0;
+    in_cs         = 1'b0;
+    scrpos_cs     = 1'b0;
+    en_cs         = 1'b0;
+    OKOUT         = 1'b0;
+    scr_bank_cs   = 1'b0;
+    mcu_cs        = 1'b0;
+    video_cs      = 1'b0;
+    layout_cs     = 1'b0;
+    if( rfsh_n && !iorq_n ) begin
+        in_cs  = A[3:0] <= 4'd5 && RnW;
+        mcu_cs = A[3:0] == 4'd7;
+        if( !RnW ) casez(A[3:0])
+                4'd0: snd_latch_cs = 1'b1;
+                4'd1: bank_cs      = 1'b1;
+                4'd4: video_cs     = 1'b1;
+                4'd6: OKOUT        = 1'b1;
+                4'd8, 4'd9, 4'd10, 4'd11: scrpos_cs = 1'b1;
+                4'd12: en_cs       = 1'b1; // video enable
+                4'd13: scr_bank_cs = 1'b1; // BG bank
+                4'd14: layout_cs   = 1'b1; // screen alyout
+                default:;
+            endcase
+    end
+end
+
+// SCROLL H/V POSITION
+always @(posedge clk, negedge t80_rst_n) begin
+    if( !t80_rst_n ) begin
+        scr_hpos <= 11'd0;
+        scr_vpos <= 11'd0;
+    end else if(cpu_cen) begin
+        if( scrpos_cs )
+        case(A[1:0])
+            2'd0: scr_hpos[ 7:0] <= cpu_dout;
+            2'd1: scr_hpos[10:8] <= cpu_dout[2:0];
+            2'd2: scr_vpos[ 7:0] <= cpu_dout;
+            2'd3: scr_vpos[10:8] <= cpu_dout[2:0];
+        endcase
+    end
+end
+
+// special registers
+reg [3:0] bank;
+
+always @(posedge clk)
+    if( rst ) begin
+        flip      <= 1'b0;
+        sres_b    <= 1'b1;
+        bank      <= 4'd0;
+        CHRON     <= 1'b1;
+        SCRON     <= 1'b1;
+        OBJON     <= 1'b1;
+        scr_bank  <= 2'b0;
+        mcu_wr    <= 1'b0;
+        mcu_rd    <= 0;
+        scr_layout<= 1'b0;
+    end
+    else if(cpu_cen) begin
+        mcu_wr   <= 1'b0;
+        mcu_rd   <= 0;
+        if( bank_cs ) bank <= cpu_dout[3:0];
+        if( mcu_cs ) begin
+            mcu_din  <= cpu_dout;
+            mcu_wr   <= !wr_n;
+            mcu_rd   <= wr_n;
+        end
+        if( video_cs ) begin
+            // bits 0,1 coin counters
+            CHRON    <= ~cpu_dout[7];
+            flip     <=  cpu_dout[6];
+            sres_b   <= ~cpu_dout[5]; // inverted through NPN
+        end
+        if( en_cs ) begin
+            SCRON    <= ~cpu_dout[1];
+            OBJON    <= ~cpu_dout[2];
+        end
+        if( scr_bank_cs  ) scr_bank   <= cpu_dout[1:0];
+        if( snd_latch_cs ) snd_latch  <= cpu_dout;
+        if( layout_cs    ) scr_layout <= cpu_dout[0];
+    end
+
+jt12_rst u_rst(
+    .rst    ( rst       ),
+    .clk    ( clk       ),
+    .rst_n  ( t80_rst_n )
+);
+
+reg [7:0] cabinet_input;
+
+always @(*)
+    case( A[2:0] )
+        3'd0: cabinet_input = { coin, // COINS IN0
+                     service, // undocumented. D5 & D4 what are those?
+                     1'b1,    // tilt?
+                     1'b1,
+                     1'b1,
+                     cab_1p }; // START
+        3'd1: cabinet_input = { 2'b11, joystick1 }; // IN1
+        3'd2: cabinet_input = { 2'b11, joystick2 }; // IN2
+        3'd3: cabinet_input = dipsw_b;
+        3'd4: cabinet_input = dipsw_a;
+        3'd5: cabinet_input = 8'hff; //dip_pause, LVBL?;
+        default: cabinet_input = 8'hff;
+    endcase
+
+
+// RAM, 16kB
+wire cpu_ram_we = ram_cs && !wr_n;
+assign cpu_AB = A[12:0];
+
+wire [12:0] RAM_addr = blcnten ? {4'b1111, obj_AB} : cpu_AB;
+wire RAM_we   = blcnten ? 1'b0 : cpu_ram_we;
+
+jtframe_ram #(.AW(13),.CEN_RD(0)) RAM(
+    .clk        ( clk       ),
+    .cen        ( cpu_cen   ),
+    .addr       ( RAM_addr  ),
+    .data       ( cpu_dout  ),
+    .we         ( RAM_we    ),
+    .q          ( ram_dout  )
+);
+
+
+always @(*) begin
+    cpu_din = 8'hff;
+    case( 1'b1 )
+        // ram_cs : cpu_din = A==16'hf3a1 && ram_dout==8'd0 ? 8'd4 : ram_dout; // cheat to start on level 5
+        ram_cs : cpu_din = ram_dout;
+        char_cs: cpu_din = char_dout;
+        scr_cs : cpu_din = scr_dout;
+        rom_cs : cpu_din = rom_data;
+        in_cs  : cpu_din = cabinet_input;
+        mcu_cs : cpu_din = mcu_dout;
+        default:;
+    endcase
+end
+
+always @(A,bank) begin
+    rom_addr[13:0]  = A[13:0];
+    rom_addr[18:14] = A[15] ? { 1'b0, bank } : {3'h4, A[15:14] };
+end
+
+/////////////////////////////////////////////////////////////////
+// wait_n generation
+wire cpu_cenw;
+
+jtframe_z80wait #(2) u_wait(
+    .rst_n      ( t80_rst_n ),
+    .clk        ( clk       ),
+    .cen_in     ( cpu_cen   ),
+    .cen_out    ( cpu_cenw  ),
+    // manage access to shared memory
+    .dev_busy   ( { scr_busy, char_busy } ),
+    // manage access to ROM data from SDRAM
+    .rom_cs     ( rom_cs    ),
+    .rom_ok     ( rom_ok    ),
+    // unused
+    .busak_n    ( busak_n   ),
+    .iorq_n     ( iorq_n    ),
+    .mreq_n     ( mreq_n    ),
+    .gate       (           )
+);
+
+
+///////////////////////////////////////////////////////////////////
+// interrupt generation.
+reg int_n, int_rqb, int_rqb_last;
+wire int_rqb_negedge = !int_rqb && int_rqb_last;
+
+always @(posedge clk, posedge rst)
+    if(rst) begin
+        int_n <= 1'b1;
+    end else if(cpu_cen) begin
+        int_rqb_last <= int_rqb;
+        int_rqb <= LVBL;
+        if( irq_ack )
+            int_n <= 1'b1;
+        else
+            if ( int_rqb_negedge && dip_pause ) int_n <= 1'b0;
+    end
+
+jtframe_z80 u_cpu(
+    .rst_n      ( t80_rst_n   ),
+    .clk        ( clk         ),
+    .cen        ( cpu_cenw    ),
+    .wait_n     ( 1'b1        ),
+    .int_n      ( int_n       ),
+    .nmi_n      ( 1'b1        ),
+    .busrq_n    ( ~bus_req    ),
+    .m1_n       ( m1_n        ),
+    .mreq_n     ( mreq_n      ),
+    .iorq_n     ( iorq_n      ),
+    .rd_n       ( rd_n        ),
+    .wr_n       ( wr_n        ),
+    .rfsh_n     ( rfsh_n      ),
+    .halt_n     (             ),
+    .busak_n    ( busak_n     ),
+    .A          ( A           ),
+    .din        ( cpu_din     ),
+    .dout       ( cpu_dout    )
+);
+
+//`ifdef SIMULATION
+//reg [15:0] Acode;
+//always @(posedge rom_ok)
+//    Acode <= A;
+//    //if( rom_cs ) $display("%1X,%4X (%5X) -> %2X", bank, A, rom_addr, rom_data );
+//`endif
+
+endmodule // jtgng_main

snapshots/jotego_jtcores_pr1100/cores/btiger/hdl/jtbtiger_mcu.v

@@ -0,0 +1,100 @@
+/*  This file is part of JTCORES.
+    JTCORES program is free software: you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation, either version 3 of the License, or
+    (at your option) any later version.
+
+    JTCORES program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with JTCORES.  If not, see <http://www.gnu.org/licenses/>.
+
+    Author: Jose Tejada Gomez. Twitter: @topapate
+    Version: 1.0
+    Date: 19-11-2019 */
+
+
+// based on 1943 schematics
+
+module jtbtiger_mcu(
+    input                rst,
+    input                clk,       // 24 MHz
+    input                clk_rom,
+    input                LVBL,
+    // Main CPU interface
+    output       [ 7:0]  mcu_dout,
+    input        [ 7:0]  mcu_din,
+    input                mcu_wr,
+    input                mcu_rd,
+    // ROM programming
+    input        [11:0]  prog_addr,
+    input        [ 7:0]  prom_din,
+    input                prom_we
+);
+
+wire [ 7:0] p1_o, p2_o, p3_o;
+
+reg  mcu_int1;
+reg  last_mcu_wr;
+wire nc, cen;
+
+jtframe_frac_cen u_cen(
+    .clk    ( clk       ),
+    .n      ( 10'd1     ),
+    .m      ( 10'd24    ),
+    .cen    ( {nc, cen} ), // cen = 1MHz
+    .cenb   (           )
+);
+
+// Port 3. All bits active low
+// 4 output enable of from-CPU latch
+// 5 clock pin of to-CPU latch
+// 1 clear interrupt
+// only bit 1 is needed in FPGA implementation
+// Note that MAME clears the interrupt in a different way
+// as it does it when the main CPU reads from the MCU
+
+always @(posedge clk) begin
+    last_mcu_wr <= mcu_wr;
+    if( mcu_wr && !last_mcu_wr ) mcu_int1 <= 1'b0;
+    if( !p3_o[1] || mcu_rd ) mcu_int1 <= 1'b1;
+end
+
+jtframe_8751mcu u_mcu(
+    .rst        ( rst       ),
+    .clk        ( clk       ),
+    .cen        ( cen       ),
+
+    .int0n      ( 1'b1      ),
+    .int1n      ( mcu_int1  ),
+
+    .p0_i       ( mcu_din   ),
+    .p0_o       ( mcu_dout  ),
+
+    .p1_i       ( 8'd0      ),
+    .p1_o       ( p1_o      ),
+
+    .p2_i       ( p2_o      ),
+    .p2_o       ( p2_o      ),
+
+    .p3_i       ( {p3_o[7:5], LVBL, p3_o[3:0] } ),
+    .p3_o       ( p3_o      ),
+
+    // external memory
+    .x_din      (           ),
+    .x_dout     (           ),
+    .x_addr     (           ),
+    .x_wr       (           ),
+    .x_acc      (           ),
+
+    // ROM programming
+    .clk_rom    ( clk_rom   ),
+    .prog_addr  ( prog_addr ),
+    .prom_din   ( prom_din  ),
+    .prom_we    ( prom_we   )
+);
+
+endmodule

snapshots/jotego_jtcores_pr1100/cores/btiger/hdl/jtbtiger_scroll.v

@@ -0,0 +1,134 @@
+/*  This file is part of JTCORES.
+    JTCORES program is free software: you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation, either version 3 of the License, or
+    (at your option) any later version.
+
+    JTCORES program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with JTCORES.  If not, see <http://www.gnu.org/licenses/>.
+
+    Author: Jose Tejada Gomez. Twitter: @topapate
+    Version: 1.0
+    Date: 19-11-2017 */
+
+module jtbtiger_scroll #(parameter
+    HOFFSET  = 9'd0
+) (
+    input              clk,
+    input              pxl_cen,
+    input              cpu_cen,
+    input              scr_en,
+    input       [11:0] AB,
+    input        [7:0] V, // V128-V1
+    input        [8:0] H, // H256-H1
+    input              Hinit,
+    input       [10:0] hpos,
+    input       [10:0] vpos,
+    input              scr_cs,
+    input              layout,
+    input        [1:0] bank,
+    input              flip,
+    input        [7:0] din,
+    output       [7:0] dout,
+    input              wr_n,
+    output             busy,
+
+    // ROM
+    output      [16:0] scr_addr,
+    input       [15:0] rom_data,
+    input              rom_ok,
+    output       [7:0] scr_pxl
+);
+
+localparam POSW = 11;   // Scroll offset width
+
+wire [8:0] Hfix = H + HOFFSET[8:0]; // Corrects pixel output offset
+reg  [POSW-1:0] HS, VS;
+wire [ 7:0] VF = {8{flip}}^V;
+wire [ 7:0] HF = {8{flip}}^Hfix[7:0];
+
+wire H7 = (~Hfix[8] & (~flip ^ HF[6])) ^HF[7];
+
+reg [2:0] HSaux;
+reg       layout2;
+
+wire [7:0] dout_low, dout_high;
+
+localparam DATAREAD = 3'd1;
+
+wire [POSW-2:0] Vtilemap = VS[POSW-1:1];
+wire [POSW-2:0] Htilemap = HS[POSW-1:1];
+
+wire [12:0] tile_addr = { bank, AB[11:1] };
+
+assign busy = (HS[2:0]<2) && scr_cs;
+
+always @(posedge clk) if(pxl_cen) begin
+    VS = vpos + { {POSW-8{1'b0}}, VF};
+    { HS[POSW-1:3], HSaux } = hpos + { {POSW-8{~Hfix[8]}}, H7, HF[6:0]};
+    HS[2:0] = HSaux ^ {3{flip}};
+
+    if( Hinit ) layout2 <= layout; // latching layout changes prevent
+        // wrong lines at the top of the screen
+        // I wonder if the original PCB was gating writes to this register
+        // instead of latching at the beginning of the line
+end
+
+jtgng_tilemap #(
+    .INVERT_SCAN( 1         ),
+    .DATAREAD   ( DATAREAD  ),
+    .SCANW      ( 13        ),
+    .VW         ( POSW-1    ),
+    .HW         ( POSW-1    ),
+    .SIMID      ( 1         )
+) u_tilemap(
+    .clk        ( clk       ),
+    .pxl_cen    ( pxl_cen   ),
+    .Asel       ( AB[0]     ),
+    .AB         ( tile_addr ),
+    .V          ( Vtilemap  ),
+    .H          ( Htilemap  ),
+    .flip       ( 1'b0      ),  // Flip is already done on HS and VS
+    .din        ( din       ),
+    .dout       ( dout      ),
+    .layout     ( layout2   ),
+    // Bus arbitrion
+    .cs         ( scr_cs    ),
+    .wr_n       ( wr_n      ),
+    // Current tile
+    .dout_low   ( dout_low  ),
+    .dout_high  ( dout_high ),
+    // unused:
+    .dseln      (           )
+);
+
+jtgng_tile4 #(
+    .PALETTE( 0  ),
+    .ROM_AW ( 17 ),
+    .LAYOUT ( 4  ))
+u_tile4 (
+    .clk        (  clk        ),
+    .cen6       (  pxl_cen    ),
+    .HS         (  HS[4:0]    ),
+    .SV         (  VS[4:0]    ),
+    .attr       (  dout_high  ),
+    .id         (  dout_low   ),
+    .SCxON      (  scr_en     ),
+    .flip       (  flip       ),
+    // Palette PROMs
+    .prog_addr  ( 8'd0        ),
+    .prom_hi_we ( 1'b0        ),
+    .prom_lo_we ( 1'b0        ),
+    .prom_din   ( 4'd0        ),
+    // Gfx ROM
+    .scr_addr   (  scr_addr   ),
+    .rom_data   (  rom_data   ),
+    .scr_pxl    (  scr_pxl    )
+);
+
+endmodule

snapshots/jotego_jtcores_pr1100/cores/btiger/hdl/jtbtiger_video.v

@@ -0,0 +1,262 @@
+/*  This file is part of JTCORES.
+    JTCORES program is free software: you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation, either version 3 of the License, or
+    (at your option) any later version.
+
+    JTCORES program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with JTCORES.  If not, see <http://www.gnu.org/licenses/>.
+
+    Author: Jose Tejada Gomez. Twitter: @topapate
+    Version: 1.0
+    Date: 19-11-2018 */
+
+module jtbtiger_video(
+    input               rst,
+    input               clk,
+    input               cen12,
+    input               cen8,
+    input               cen6,
+    input               cen3,
+    input               cpu_cen,
+    input       [11:0]  cpu_AB,
+    input       [ 7:0]  V,
+    input       [ 8:0]  H,
+    input               RnW,
+    input               flip,
+    input       [ 7:0]  cpu_dout,
+    input               pause,
+    // CHAR
+    input               char_cs,
+    output      [ 7:0]  char_dout,
+    input               char_ok,
+    output              char_busy,
+    output      [13:0]  char_addr,
+    input       [15:0]  char_data,
+    input               CHRON,
+    // SCROLL - ROM
+    input               scr_cs,
+    output      [ 7:0]  scr_dout,
+    output      [16:0]  scr_addr,
+    input       [15:0]  scr_data,
+    input               scr_ok,
+    output              scr_busy,
+    input       [10:0]  scr_hpos,
+    input       [10:0]  scr_vpos,
+    input       [ 1:0]  scr_bank,
+    input               scr_layout,
+    input               SCRON,
+    // OBJ
+    input               HINIT,
+    output      [ 8:0]  obj_AB,
+    input       [ 7:0]  main_ram,
+    input               OKOUT,
+    output              bus_req, // Request bus
+    input               bus_ack, // bus acknowledge
+    output              blcnten,    // bus line counter enable
+    output      [16:0]  obj_addr,
+    input       [15:0]  obj_data,
+    input               obj_ok,
+    input               OBJON,
+    // Color Mix
+    input               preLHBL,
+    input               preLVBL,
+    input               LVBL_obj,
+    input               LHBL_obj,
+    output              LHBL,
+    output              LVBL,
+    // Palette PROMs
+    input       [7:0]   prog_addr,
+    input               prom_prior_we,
+    input       [3:0]   prom_din,
+    // Palette RAM
+    input               blue_cs,
+    input               redgreen_cs,
+    input       [3:0]   gfx_en,
+    // Pixel output
+    output      [3:0]   red,
+    output      [3:0]   green,
+    output      [3:0]   blue
+);
+
+localparam OBJMAX       = 10'h200, // DMA buffer 512 bytes = 4*128
+           OBJMAX_LINE  = 6'd32;
+
+wire [6:0] char_pxl;
+wire [6:0] obj_pxl;
+wire [7:0] scr_pxl;
+wire [3:0] cc;
+wire       char_en = CHRON & gfx_en[0],
+           scr_en  = SCRON & gfx_en[1],
+           obj_en  = SCRON & gfx_en[3];
+
+jtgng_char #(
+    .HOFFSET ( 0),
+    .ROM_AW  (14),
+    .PALW    ( 5),
+    .VFLIP_EN( 0),
+    .HFLIP_EN( 0),
+    .IDMSB0  ( 5)
+) u_char (
+    .clk        ( clk           ),
+    .pxl_cen    ( cen6          ),
+    .AB         ( cpu_AB[10:0]  ),
+    .V          ( V             ),
+    .H          ( H[7:0]        ),
+    .flip       ( flip          ),
+    .din        ( cpu_dout      ),
+    .dout       ( char_dout     ),
+    // Bus arbitrion
+    .char_cs    ( char_cs       ),
+    .wr_n       ( RnW           ),
+    .busy       ( char_busy     ),
+    // ROM
+    .char_addr  ( char_addr     ),
+    .rom_data   ( char_data     ),
+    .rom_ok     ( char_ok       ),
+    // Pixel output
+    .char_on    ( char_en       ),
+    .char_pxl   ( char_pxl      ),
+    // unused
+    .dseln      (               ),
+    .prog_addr  (               ),
+    .prog_din   (               ),
+    .prom_we    (               )
+);
+
+
+`ifndef NOSCR
+wire [7:0] scr_pre;
+
+jtframe_sh #(.W(8),.L(5)) u_hb_dly(
+    .clk    ( clk      ),
+    .clk_en ( cen6     ),
+    .din    ( scr_pre  ),
+    .drop   ( scr_pxl  )
+);
+
+jtbtiger_scroll #(.HOFFSET(0)) u_scroll (
+    .clk        ( clk           ),
+    .pxl_cen    ( cen6          ),
+    .cpu_cen    ( cpu_cen       ),
+    .scr_en     ( scr_en        ),
+    // screen position
+    .H          ( H             ),
+    .V          ( V[7:0]        ),
+    .Hinit      ( HINIT         ),
+    .hpos       ( scr_hpos      ),
+    .vpos       ( scr_vpos      ),
+    .flip       ( flip          ),
+    .layout     ( scr_layout    ),
+    .bank       ( scr_bank      ),
+    // bus arbitrion
+    .AB         ( cpu_AB[11:0]  ),
+    .scr_cs     ( scr_cs        ),
+    .din        ( cpu_dout      ),
+    .dout       ( scr_dout      ),
+    .wr_n       ( RnW           ),
+    .busy       ( scr_busy      ),
+    // ROM
+    .scr_addr   ( scr_addr      ),
+    .rom_data   ( scr_data      ),
+    .rom_ok     ( scr_ok        ),
+    // pixel output
+    .scr_pxl    ( scr_pre       )
+);
+`else
+assign scr_busy   = 1'b0;
+assign scr_pxl    = 8'hff;
+assign scr_addr   = 17'd0;
+assign scr_dout   = 8'd0;
+`endif
+
+`ifndef NOOBJ
+jtgng_obj #(
+    .OBJMAX       ( OBJMAX      ),
+    .OBJMAX_LINE  ( OBJMAX_LINE ),
+    .ROM_AW       ( 17          ),
+    .PALW         (  3          ),
+    .PXL_DLY      (  8          ),
+    .LAYOUT       (  4          ))
+u_obj (
+    .rst        ( rst         ),
+    .clk        ( clk         ),
+    .draw_cen   ( cen12       ),
+    .dma_cen    ( cen8        ),
+    .pxl_cen    ( cen6        ),
+    .AB         ( obj_AB      ),
+    .DB         ( main_ram    ),
+    .OKOUT      ( OKOUT       ),
+    .bus_req    ( bus_req     ),
+    .bus_ack    ( bus_ack     ),
+    .blen       ( blcnten     ),
+    .LHBL       ( LHBL_obj    ),
+    .LVBL       ( LVBL        ),
+    .LVBL_obj   ( LVBL_obj    ),
+    .HINIT      ( HINIT       ),
+    .flip       ( flip        ),
+    .alt        ( 1'b0        ),
+    .V          ( V[7:0]      ),
+    .H          ( H           ),
+    // SDRAM interface
+    .obj_addr   ( obj_addr    ),
+    .obj_data   ( obj_data    ),
+    .rom_ok     ( obj_ok      ),
+    // pixel data
+    .obj_pxl    ( obj_pxl     ),
+    // unused
+    .prog_addr  (             ),
+    .prog_din   (             ),
+    .prom_hi_we ( 1'b0        ),
+    .prom_lo_we ( 1'b0        ),
+    .OBJON      ( obj_en      )
+);
+`else
+assign blcnten = 1'b0;
+assign bus_req = 1'b0;
+assign obj_pxl = ~6'd0;
+`endif
+
+`ifndef NOCOLMIX
+jtbtiger_colmix u_colmix (
+    .rst          ( rst           ),
+    .clk          ( clk           ),
+    .cen12        ( cen12         ),
+    .cen6         ( cen6          ),
+
+    .char_pxl     ( char_pxl      ),
+    .scr_pxl      ( scr_pxl       ),
+    .obj_pxl      ( obj_pxl       ),
+    .preLHBL      ( preLHBL       ),
+    .preLVBL      ( preLVBL       ),
+    .LVBL         ( LVBL          ),
+    .LHBL         ( LHBL          ),
+
+    // Priority PROM
+    .prog_addr    ( prog_addr     ),
+    .prom_prior_we( prom_prior_we ),
+    .prom_din     ( prom_din      ),
+
+    // CPU interface
+    .AB           ( cpu_AB[9:0]   ),
+    .blue_cs      ( blue_cs       ),
+    .redgreen_cs  ( redgreen_cs   ),
+    .DB           ( cpu_dout      ),
+
+    // colour output
+    .red          ( red           ),
+    .green        ( green         ),
+    .blue         ( blue          )
+);
+`else
+assign  red = 4'd0;
+assign blue = 4'd0;
+assign green= 4'd0;
+`endif
+
+endmodule

snapshots/jotego_jtcores_pr1100/cores/btiger/ver/game/pal.cc

@@ -0,0 +1,15 @@
+#include <iostream>
+#include <fstream>
+
+using namespace std;
+
+int main() {
+    ofstream ob("b_ram.bin", ios_base::binary);
+    ofstream org("rg_ram.bin", ios_base::binary);
+    for( int k=0; k<256; k++ ) {
+        char buf[4] = { 0xff, 0x88, 0x44, 0 };
+        ob.write(buf, 4 );
+        org.write(buf, 4 );
+    }
+    return 0;
+}

snapshots/jotego_jtcores_pr1100/cores/btiger/ver/game/scr.sh

@@ -0,0 +1,7 @@
+#!/bin/bash
+
+
+go.sh -d NOMAIN -d NOSOUND -d NOMCU -d NOCHAR \
+    -d JTCHAR_LOWER_SIMFILE=',.simfile("scr0.bin")' \
+    -d JTCHAR_UPPER_SIMFILE=',.simfile("scr1.bin")' \
+    -video 2 -w

snapshots/jotego_jtcores_pr1100/cores/btiger/ver/game/sim.sh

@@ -0,0 +1,3 @@
+#!/bin/bash
+
+jtsim $*

snapshots/jotego_jtcores_pr1100/cores/btiger/ver/prom_we/go.sh

@@ -0,0 +1,17 @@
+#!/bin/bash
+
+ROM=$JTGNG/rom/JTBTIGER.rom
+GAME_ROM_LEN=$(stat -c%s $ROM)
+
+if which ncverilog > /dev/null; then
+ncverilog test.v ../../hdl/jtbtiger_prom_we.v  \
+    +access+r \
+    +define+ROM_LEN=$GAME_ROM_LEN +define+PROM_W=1 +define+SIMULATION \
+    +define+ROM_PATH=\""$ROM"\" 
+else
+iverilog test.v ../../hdl/jtbtiger_prom_we.v  \
+    -D ROM_LEN=$GAME_ROM_LEN -D PROM_W=1 -D SIMULATION \
+    -D ROM_PATH=\""$ROM"\" \
+    -o sim \
+    && sim -lxt
+fi

snapshots/jotego_jtcores_pr1100/cores/btiger/ver/prom_we/test.v

@@ -0,0 +1,120 @@
+`timescale 1ns/1ps
+
+module test;
+
+localparam MAIN0_ADDR  = 22'h00000;
+localparam MAIN1_ADDR  = 22'h20000;
+localparam SND_ADDR    = 22'h40000;
+localparam SND2_ADDR   = 22'h48000;
+localparam CHAR_ADDR   = 22'h58000;
+localparam MAP_ADDR    = 22'h60000;
+// Scroll
+localparam SCRZW_ADDR  = 22'h70000;
+localparam SCRXY_ADDR  = 22'hF0000;
+// even words
+localparam OBJWZ_ADDR0 = 22'h170000;
+localparam OBJXY_ADDR0 = 22'h190000;
+// odd words
+localparam OBJWZ_ADDR1 = 22'h1B0000;
+localparam OBJXY_ADDR1 = 22'h1D0000;
+// FPGA BRAM:
+localparam PROM_ADDR   = 22'h1F0000;
+// ROM length 1F0100
+
+reg         rst;
+reg         clk, downloading=1'b1;
+reg  [21:0] ioctl_addr= 22'd0;
+reg  [ 7:0] ioctl_dout= 8'd0;
+reg         ioctl_wr;
+
+wire [21:0] prog_addr;
+wire [ 7:0] prog_data;
+wire [ 1:0] prog_mask;
+wire        prog_we, jap;
+wire [`PROM_W-1:0] prom_we;
+
+jtbtiger_prom_we
+    u_uut(
+    .clk         (  clk          ),
+    .downloading (  downloading  ),
+    .ioctl_addr  (  ioctl_addr   ),
+    .ioctl_dout  (  ioctl_dout   ),
+    .ioctl_wr    (  ioctl_wr     ),
+    .prog_addr   (  prog_addr    ),
+    .prog_data   (  prog_data    ),
+    .prog_mask   (  prog_mask    ),
+    .prog_we     (  prog_we      ),
+    .prom_we     (  prom_we      )
+);
+
+wire [21:0] obj_addr;
+wire [ 7:0] obj_data;
+wire [ 4:0] obj_mask;
+wire        obj_we;
+
+wire [15:0] sdram_dout = 16'habcd;
+
+
+initial begin
+    clk = 1'b0;    
+    forever #10 clk = ~clk;
+end
+
+initial begin
+    rst = 1'b0;
+    #7 rst = 1'b1;
+    #7 rst = 1'b0;
+end
+
+reg [1:0] cnt=2'b0;
+reg [7:0] romfile[0:`ROM_LEN-1];
+integer f;
+
+initial begin    
+    f=$fopen(`ROM_PATH,"rb");
+    if( f==0 ) begin
+        $display("ERROR: cannot open file %s",`ROM_PATH);
+        $finish;
+    end
+    cnt=$fread(romfile,f);
+    $display("INFO: %s ROM lentgh 0x%h",`ROM_PATH,cnt);
+    $fclose(f);
+end
+
+reg [15:0] sdram[0:2**22-1];
+integer cnt2;
+reg tx_done = 1'b0;
+
+always @(posedge clk) begin
+    cnt      <= cnt+2'd1;
+    ioctl_wr <= 1'b0;
+    if( ioctl_addr < `ROM_LEN && cnt==2'b10 ) begin
+        ioctl_dout <= romfile[ioctl_addr];
+        ioctl_wr   <= 1'b1;
+    end else if(cnt==2'b11) begin
+        ioctl_addr <= ioctl_addr + 22'd1;
+    end else if( ioctl_addr >= `ROM_LEN && !tx_done) begin
+        downloading <= 1'b0;
+        f=$fopen("sdram.hex");
+        for( cnt2=0; cnt2<(2**22-1); cnt2=cnt2+1) begin
+            $fdisplay(f,"%04X",sdram[cnt2]);
+        end
+        $fclose(f);
+        $display("INFO: SDRAM download done");
+        tx_done <= 1'b1;
+        $finish;
+    end
+end
+
+always @(negedge prog_we) begin
+    if(!prog_mask[1]) sdram[ prog_addr ][15:8] <= prog_data;
+    if(!prog_mask[0]) sdram[ prog_addr ][ 7:0] <= prog_data;
+end
+
+initial begin
+    $dumpfile("test.lxt");
+    $dumpvars(0,test);
+    $dumpon;    
+end
+
+endmodule

snapshots/jotego_jtcores_pr1100/cores/btiger/ver/regrun/blkdrgon.sha

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snapshots/jotego_jtcores_pr1100/cores/btiger/ver/regrun/blktiger.sha

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snapshots/jotego_jtcores_pr1100/cores/btiger/ver/regrun/blktigera.sha

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snapshots/jotego_jtcores_pr1100/cores/btiger/ver/scroll/go.sh

@@ -0,0 +1,9 @@
+#!/bin/bash
+
+iverilog test.v ../../hdl/jtbtiger_scroll.v \
+    $JTGNG/modules/jtgng_{cen,timer,tilemap,tile4}.v \
+    $JTGNG/modules/jtframe/hdl/ram/jtgng_ram.v \
+    -DJTCHAR_LOWER_SIMFILE=',.simfile("bg0.bin")' \
+    -DJTCHAR_UPPER_SIMFILE=',.simfile("bg1.bin")' \
+    -DSIMULATION \
+    -o sim && sim -lxt

snapshots/jotego_jtcores_pr1100/cores/btiger/ver/scroll/test.v

@@ -0,0 +1,100 @@
+`timescale 1ns/1ps
+
+
+module test;
+
+reg           clk;     // 24 MHz
+reg           rst;
+wire   [11:0] AB = 12'd0;
+wire    [8:0] V; // V128-V1
+wire    [8:0] H; // H256-H1
+wire   [10:0] hpos=11'd0;
+wire   [10:0] vpos=11'h0;
+wire          scr_cs = 1'b0;
+wire          layout = 1'b0;
+wire    [1:0] bank = 2'b0;
+wire          flip = 1'b0;
+reg     [7:0] din = 8'd0;
+wire    [7:0] dout;
+reg           wr_n = 1'b1;
+wire          busy;
+wire   [16:0] scr_addr;
+wire   [15:0] rom_data = 16'hdead;
+wire          rom_ok = 1'b1;
+wire   [ 7:0] scr_pxl;
+
+wire cen6;
+
+initial begin
+    clk = 0;
+    forever #(1/10.416) clk = ~clk;
+end
+
+initial begin
+    rst=1;
+    #30 rst=0;
+end
+
+integer framecnt=0;
+
+always @(posedge LVBL) begin
+    framecnt <= framecnt+1;
+    if (framecnt==1) $finish;
+end
+
+jtgng_cen #(.CLK_SPEED(48)) u_cen(
+    .clk    ( clk       ),
+    .cen12  (           ),
+    .cen12b (           ),
+    .cen8   (           ),
+    .cen6   ( cen6      ),
+    .cen6b  (           ),
+    .cen3   (           ),
+    .cen1p5 (           )
+);
+
+jtgng_timer u_timer(
+    .clk       ( clk      ),
+    .cen6      ( cen6     ),
+    .V         ( V        ),
+    .H         ( H        ),
+    .Hinit     (          ),
+    .LHBL      ( LHBL     ),
+    .LHBL_obj  (          ),
+    .LVBL      ( LVBL     ),
+    .LVBL_obj  (          ),
+    .HS        (          ),
+    .VS        (          ),
+    .Vinit     (          )
+);
+
+jtbtiger_scroll uut(
+    .clk        (  clk      ),
+    .pxl_cen    (  cen6     ),
+    .cpu_cen    (  cen6     ),
+    .AB         (  AB       ),
+    .V          (  V[7:0]   ), // V128-V1
+    .H          (  H        ), // H256-H1
+    .hpos       (  hpos     ),
+    .vpos       (  vpos     ),
+    .scr_cs     (  scr_cs   ),
+    .layout     (  layout   ),
+    .bank       (  bank     ),
+    .flip       (  flip     ),
+    .din        (  din      ),
+    .dout       (  dout     ),
+    .wr_n       (  wr_n     ),
+    .busy       (  busy     ),
+    .scr_addr   (  scr_addr ),
+    .rom_data   (  rom_data ),
+    .rom_ok     (  rom_ok   ),
+    .scr_pxl    (  scr_pxl  )
+);
+
+initial begin
+    $dumpfile("test.lxt");
+    $dumpvars;
+    $dumpon;
+end
+
+endmodule

snapshots/jotego_jtcores_pr1100/cores/capbowl/sch/bowl.kicad_pcb

@@ -0,0 +1 @@
+(kicad_pcb (version 4) (host kicad "dummy file") )

snapshots/jotego_jtcores_pr1100/cores/capbowl/sch/bowl.kicad_prl

@@ -0,0 +1,90 @@
+{
+  "board": {
+    "active_layer": 0,
+    "active_layer_preset": "",
+    "auto_track_width": true,
+    "hidden_netclasses": [],
+    "hidden_nets": [],
+    "high_contrast_mode": 0,
+    "net_color_mode": 1,
+    "opacity": {
+      "images": 0.6,
+      "pads": 1.0,
+      "tracks": 1.0,
+      "vias": 1.0,
+      "zones": 0.6
+    },
+    "ratsnest_display_mode": 0,
+    "selection_filter": {
+      "dimensions": true,
+      "footprints": true,
+      "graphics": true,
+      "keepouts": true,
+      "lockedItems": true,
+      "otherItems": true,
+      "pads": true,
+      "text": true,
+      "tracks": true,
+      "vias": true,
+      "zones": true
+    },
+    "visible_items": [
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+      1,
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+      29,
+      30,
+      32,
+      33,
+      34,
+      35,
+      36
+    ],
+    "visible_layers": "fffffff_ffffffff",
+    "zone_display_mode": 0
+  },
+  "meta": {
+    "filename": "bowl.kicad_prl",
+    "version": 3
+  },
+  "project": {
+    "files": [
+      {
+        "name": "bowl.kicad_sch",
+        "open": false,
+        "window": {
+          "display": 0,
+          "maximized": true,
+          "pos_x": 607,
+          "pos_y": 243,
+          "size_x": 842,
+          "size_y": 610
+        }
+      }
+    ]
+  }
+}

snapshots/jotego_jtcores_pr1100/cores/capbowl/sch/bowl.kicad_pro

@@ -0,0 +1,357 @@
+{
+  "board": {
+    "3dviewports": [],
+    "design_settings": {
+      "defaults": {
+        "board_outline_line_width": 0.1,
+        "copper_line_width": 0.2,
+        "copper_text_size_h": 1.5,
+        "copper_text_size_v": 1.5,
+        "copper_text_thickness": 0.3,
+        "other_line_width": 0.15,
+        "silk_line_width": 0.15,
+        "silk_text_size_h": 1.0,
+        "silk_text_size_v": 1.0,
+        "silk_text_thickness": 0.15
+      },
+      "diff_pair_dimensions": [],
+      "drc_exclusions": [],
+      "rules": {
+        "solder_mask_clearance": 0.0,
+        "solder_mask_min_width": 0.0
+      },
+      "track_widths": [],
+      "via_dimensions": []
+    },
+    "layer_presets": [],
+    "viewports": []
+  },
+  "boards": [],
+  "cvpcb": {
+    "equivalence_files": []
+  },
+  "erc": {
+    "erc_exclusions": [],
+    "meta": {
+      "version": 0
+    },
+    "pin_map": [
+      [
+        0,
+        0,
+        0,
+        0,
+        0,
+        0,
+        1,
+        0,
+        0,
+        0,
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+      ],
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+      [
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+      [
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+      ],
+      [
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+      [
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+        2,
+        2,
+        2,
+        2,
+        2,
+        2,
+        2,
+        2
+      ]
+    ],
+    "rule_severities": {
+      "bus_definition_conflict": "error",
+      "bus_entry_needed": "error",
+      "bus_to_bus_conflict": "error",
+      "bus_to_net_conflict": "error",
+      "conflicting_netclasses": "error",
+      "different_unit_footprint": "error",
+      "different_unit_net": "error",
+      "duplicate_reference": "error",
+      "duplicate_sheet_names": "error",
+      "endpoint_off_grid": "warning",
+      "extra_units": "error",
+      "global_label_dangling": "warning",
+      "hier_label_mismatch": "error",
+      "label_dangling": "error",
+      "lib_symbol_issues": "warning",
+      "missing_bidi_pin": "warning",
+      "missing_input_pin": "warning",
+      "missing_power_pin": "error",
+      "missing_unit": "warning",
+      "multiple_net_names": "warning",
+      "net_not_bus_member": "warning",
+      "no_connect_connected": "warning",
+      "no_connect_dangling": "warning",
+      "pin_not_connected": "error",
+      "pin_not_driven": "error",
+      "pin_to_pin": "warning",
+      "power_pin_not_driven": "error",
+      "similar_labels": "warning",
+      "simulation_model_issue": "ignore",
+      "unannotated": "error",
+      "unit_value_mismatch": "error",
+      "unresolved_variable": "error",
+      "wire_dangling": "error"
+    }
+  },
+  "libraries": {
+    "pinned_footprint_libs": [],
+    "pinned_symbol_libs": []
+  },
+  "meta": {
+    "filename": "bowl.kicad_pro",
+    "version": 1
+  },
+  "net_settings": {
+    "classes": [
+      {
+        "bus_width": 12,
+        "clearance": 0.2,
+        "diff_pair_gap": 0.25,
+        "diff_pair_via_gap": 0.25,
+        "diff_pair_width": 0.2,
+        "line_style": 0,
+        "microvia_diameter": 0.3,
+        "microvia_drill": 0.1,
+        "name": "Default",
+        "pcb_color": "rgba(0, 0, 0, 0.000)",
+        "schematic_color": "rgba(0, 0, 0, 0.000)",
+        "track_width": 0.25,
+        "via_diameter": 0.8,
+        "via_drill": 0.4,
+        "wire_width": 6
+      }
+    ],
+    "meta": {
+      "version": 3
+    },
+    "net_colors": null,
+    "netclass_assignments": null,
+    "netclass_patterns": []
+  },
+  "pcbnew": {
+    "last_paths": {
+      "gencad": "",
+      "idf": "",
+      "netlist": "",
+      "specctra_dsn": "",
+      "step": "",
+      "vrml": ""
+    },
+    "page_layout_descr_file": ""
+  },
+  "schematic": {
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+    "drawing": {
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+      "dashed_lines_gap_length_ratio": 3.0,
+      "default_line_thickness": 6.0,
+      "default_text_size": 50.0,
+      "field_names": [],
+      "intersheets_ref_own_page": false,
+      "intersheets_ref_prefix": "",
+      "intersheets_ref_short": false,
+      "intersheets_ref_show": false,
+      "intersheets_ref_suffix": "",
+      "junction_size_choice": 3,
+      "label_size_ratio": 0.25,
+      "pin_symbol_size": 0.0,
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+    },
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+    "legacy_lib_list": [],
+    "meta": {
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+    },
+    "net_format_name": "",
+    "ngspice": {
+      "fix_include_paths": true,
+      "fix_passive_vals": false,
+      "meta": {
+        "version": 0
+      },
+      "model_mode": 0,
+      "workbook_filename": ""
+    },
+    "page_layout_descr_file": "",
+    "plot_directory": "",
+    "spice_adjust_passive_values": false,
+    "spice_current_sheet_as_root": false,
+    "spice_external_command": "spice \"%I\"",
+    "spice_model_current_sheet_as_root": true,
+    "spice_save_all_currents": false,
+    "spice_save_all_voltages": false,
+    "subpart_first_id": 65,
+    "subpart_id_separator": 0
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+}