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issues/AsFigo_pyslint_pr140

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+# SV: post/pre randomize return value check - COMPAT issue
+
+- Source URL: https://github.com/AsFigo/pyslint/issues/139
+
+```verilog
+class gen_c;
+  rand bit b;
+
+  function pre_randomize();
+  endfunction
+
+  function post_randomize();
+  endfunction
+endclass : gen_c
+```
+
+Above code works fine in one but not in all others.
+
+## PR Content from GitHub
+
+# Pull Request #140 Summary
+
+**PR Title:** Added rule to address issue 139
+
+**PR Description Body:**
+The page does not display a full description body beyond the title. The only substantive comment is: "Fixes #139"
+
+**PR Comments:**
+- **Author: svenka3** - "Fixes #139"
+
+**Linked Issue #139:**
+**Title:** "SV: post/pre randomize return value check - COMPAT issue"
+
+**Issue Body:**
+Not provided in the extracted content.
+
+**Status:** This PR was merged by svenka3 on November 29, 2023, into the main branch from the i139 branch.

issues/AsFigo_pyslint_pr149

@@ -0,0 +1,56 @@
+# DPI - checks needed inside interface context
+
+- Source URL: https://github.com/AsFigo/pyslint/issues/147
+
+DPI checks to be added for interface context.
+
+```verilog
+interface af_sv_if;
+  import "DPI" function int c_sum();
+endinterface : af_sv_if
+```
+
+## PR Content from GitHub
+
+# Pull Request Summary
+
+**PR Title:** DPI enhancements
+
+**PR Number:** #149
+
+**Status:** Merged
+
+**Author:** svenka3
+
+**Merge Date:** December 1, 2023
+
+---
+
+## PR Description
+
+The pull request description is minimal. The author only states: "Fixes #147 and #148"
+
+---
+
+## Commits
+
+Two commits were included:
+1. "Fixes Issue #147" (commit f340d60)
+2. "Support for DPI inside PKG is added" (commit e15120a)
+
+---
+
+## Comments
+
+**svenka3** commented on December 1, 2023:
+"Fixes #147 and #148"
+
+---
+
+## Linked Issues
+
+This PR references two issues:
+- **Issue #147:** "DPI - checks needed inside interface context"
+- **Issue #148:** "DPI - checks need to be performed for package scoped DPI methods"
+
+The pull request successfully closed Issue #147. Issue #148 was also referenced and addressed through the implementation of DPI (Direct Programming Interface) support within package scoping contexts.

issues/AsFigo_pyslint_pr175

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+# COMPAT SVA missing ;
+
+- Source URL: https://github.com/AsFigo/pyslint/issues/174
+
+```verilog
+module m;
+  bit clk, a, b;
+
+  property p_ex;
+    @(posedge clk) a |=> b
+  endproperty : p_ex
+
+endmodule : m
+```
+
+## PR Content from GitHub
+
+# GitHub Pull Request Summary
+
+**PR Title:** Added rule 174 - COMPAT
+
+**PR Number:** #175
+
+**Status:** Merged
+
+**Author:** svenka3
+
+**Merge Date:** December 8, 2023
+
+---
+
+## PR Description
+The PR description body is not explicitly shown in the provided content beyond the title.
+
+## Comments
+
+**svenka3** commented:
+> "Fixes #174"
+
+This brief comment references the linked issue.
+
+---
+
+## Linked Issue
+
+**Issue #174 Title:** "COMPAT SVA missing ;"
+
+The issue title indicates this PR addresses a missing semicolon issue related to COMPAT SVA functionality.
+
+---
+
+## Additional Details
+
+- **Commits:** 1 commit merged (09108a8)
+- **Branch:** Merged from `i174` into `main`
+- **Reviewers:** None listed
+- **Assignees:** None listed

issues/FPGA-MAFIA_fpga_mafia_pr465

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+# add HW interrupt support to core_rrv
+
+- Source URL: https://github.com/FPGA-MAFIA/fpga_mafia/issues/437
+
+The interrupt will start when one of the counters will reach a predefined value.
+
+PR Title: fix issues we talked about csr
+
+Description:
+The contributor implemented an initial version that executes instructions once the timer interrupt is triggered. This approach ensures interrupts are processed when NOPs are absent, preventing loops. The implementation was tested with multiple timers using the comparison method for valid instructions. All relevant CSR updates are handled in the CSR module rather than software.
+
+Commits (4):
+1. Remove CSR check in ctrl and pass to CSR unit
+2. Merge branch 'main' into core_rrv
+3. Fix merge conflict issues
+4. Fix timer interrupt handler
+
+Comments:
+roman012285 (Collaborator): "I chose to implement our initial version and execute the instruction once the timer interrupt is triggered... All the updated of relevant csrs are handled in CSR module and not in the software."
+
+amichai-bd (Reviewer/Merger): "Great job!"
+
+Linked Issue: #437 - "add HW interrupt support to core_rrv"
+
+Status: Merged by amichai-bd on February 2, 2024

issues/HiSA-Team_Simply-V_pr52

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+# [feature/core_selection] Add core selection to Make flow
+
+- Source URL: https://github.com/HiSA-Team/Simply-V/issues/20
+
+## Issue Title
+[feature/core_selection] Add core selection to Make flow
+
+## Issue Description
+Add core selection to Make flow for RVM socket CORE_SELECTION parameter.
+
+## Issue Comments
+None visible.
+
+## Issue Metadata
+- Status: Closed
+- Assignee: MaistoV
+- Milestone: MCU release
+
+## Linked Issues / PRs
+- PR #52 — implementation (closed)

issues/HiSA-Team_Simply-V_pr92

@@ -0,0 +1,24 @@
+# [feature/cores/ibex] Integrate Ibex core as custom IP
+
+- Source URL: https://github.com/HiSA-Team/Simply-V/issues/66
+
+## Issue Title
+[feature/cores/ibex] Integrate Ibex core as custom IP
+
+## Issue Description
+From https://github.com/lowRISC/ibex.
+
+Issues:
+- which release?
+- which DTM to use? from PULP or ibex-demo-system?
+
+## Issue Comments
+None visible.
+
+## Issue Metadata
+- Status: Closed (via PR #92)
+- Opened by: MaistoV on March 11, 2025
+- Assignees: Granp4sso, MaistoV
+
+## Linked Issues / PRs
+- PR #92 — appears to be the resolution implementation

issues/Lampro-Mellon_LM-RISCV-DV_pr81

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+# Enable Verilator in the RTL Simulation Flow for SweRV integration
+
+- Source URL: https://github.com/Lampro-Mellon/LM-RISCV-DV/issues/69
+
+
+## Fetched Issue/PR Details
+
+Title: Enable Verilator in the RTL Simulation Flow for SweRV integration (#69)
+
+Description: No description was provided in the original issue.
+
+Status: Closed (resolved via PR #81)
+Assignee: amnafayyaz28
+Label: enhancement
+Reporter: haroon-shafique
+Opened: January 7, 2021
+
+Comments: No comments, reactions, or additional context were visible on the page.
+
+Linked Issues: Resolving PR #81. The issue requests integration of Verilator (an open-source RTL simulator) into the RTL simulation workflow for SweRV core integration within the LM-RISCV-DV project.

issues/MiSTer-devel_Arcade-Robotron_MiSTer_pr25

@@ -0,0 +1,24 @@
+# Core is outputting at 296 x 243...
+
+- Source URL: https://github.com/MiSTer-devel/Arcade-Robotron_MiSTer/issues/24
+
+...instead of 292 x 240 and as such doesn't seem to want to scale to 720p.
+
+## Fetched Issue/PR Details
+
+Title: Core is outputting at 296 x 243... (#24)
+
+Description: The core outputs a resolution of 296 x 243 pixels instead of the expected 292 x 240, which prevents proper scaling to 720p.
+
+Repository: MiSTer-devel/Arcade-Robotron_MiSTer
+Author: dazzer69
+Opened: September 27, 2021
+Status: Closed (linked to PR #25)
+
+Additional Details:
+- No assignees or labels
+- No open branches or pull requests associated
+
+Comments: No comments visible.
+
+Linked Issues: Resolving PR #25.

issues/MiSTer-devel_NES_MiSTer_pr135

@@ -0,0 +1,39 @@
+# Indiana Jones 3 glitchy title screen
+
+- Source URL: https://github.com/MiSTer-devel/NES_MiSTer/issues/129
+
+Indiana Jones and The Last Crusade (Taito) shows some flickering lines that shouldn't be there in the title screen.
+
+---
+
+## Pull Request
+
+**PR Title:** Timing fixes
+
+**PR Number:** #135
+
+**Status:** Merged on Sep 15, 2019
+
+### Description
+
+Kitrinx's initial comment detailed the changes:
+
+> "Several timing related fixes. Passes 3 more tests. Resolves #129 (Indiana Jones) Resolves flickering line on Zelda 2 title screen Resolves colored line on Micro Machines title screen"
+
+The PR also addressed preliminary support for Mapper 4, submacker 3 (Acclaim's MMC3) for games including Mickey's Safari in Letterland and Incredible Crash Dummies. Additionally, it fixed SNAC controller swap issues and cleaned up compiler warnings.
+
+### Comments
+
+**MP2E** responded positively: "Outstanding work"
+
+**Kitrinx** added: The update also resolved SNAC controller swap issues and cleaned up several warnings.
+
+**yxkalle** expressed gratitude: "Thank you very much"
+
+### Linked Issues
+
+The PR resolved **#129**: "Indiana Jones 3 glitchy title screen"
+
+### Participants
+
+Kitrinx (author), sorgelig (merged), MP2E, yxkalle

issues/Multimedia-Processing_Digital-Logic-Design_pr48

@@ -0,0 +1,50 @@
+# 6-3 多工器與解多工器的實習
+
+- Source URL: https://github.com/Multimedia-Processing/Digital-Logic-Design/issues/44
+
+1. 明瞭多工器的原理與電路設計的方法
+2. 明瞭解多工器的原理與電路設計的方法
+3. 學習解多工器與解碼器的互用方式
+4. 學習直接套用制式IC完成所需
+
+---
+
+## Pull Request
+
+**PR Title:** 47 verilog hdl practice ch4
+
+**PR Number:** #48
+
+**Status:** Merged on November 19, 2020
+
+**Author:** timmy61109
+
+**Target:** master branch
+
+**Source Branch:** 47-VerilogHDL-Practice-CH4
+
+### Description
+
+No description was provided by the author.
+
+### Commits (19 total)
+
+The pull request contained 19 commits with messages in Traditional Chinese, including:
+
+- Updates to `.gitignore` for Vivado-generated directories
+- Implementation of 2-to-1 and 4-to-2 multiplexers
+- Completion of a 1-bit full adder with gate-level descriptions
+- Four work items related to Chapter 6, Section 3
+- 4-to-1 multiplexer implementation
+- Addition of execution scripts
+
+### Linked Issue
+
+This PR closes issue #44: "6-3 多工器與解多工器的實習" (Chapter 6-3 Multiplexer and Demultiplexer Practice)
+
+### Metadata
+
+- Assigned to: JulianHsia, timmy61109, JulianXia-2020
+- Labels: documentation, enhancement
+- Milestone: Chapter 6
+- Participants: 3 users

issues/Multimedia-Processing_Digital-Logic-Design_pr50

@@ -0,0 +1,57 @@
+# Verilog硬體描述語言實務 第二版 Chapter4
+
+- Source URL: https://github.com/Multimedia-Processing/Digital-Logic-Design/issues/47
+
+- 4-1 基本邏輯閘
+- 4-2 實例說明
+
+練習題
+
+- [x] 1
+- [x] 2
+
+---
+
+## Pull Request
+
+**PR Title:** 47 verilog hdl practice ch4
+
+**PR Number:** #50
+
+**Status:** Merged on November 27, 2020
+
+**Author:** timmy61109
+
+### Description
+
+No description was provided for this pull request.
+
+### Commits
+
+The PR contained three commits:
+1. "如果採用，此提交將新增練習題第一題" (adds practice problem 1)
+2. "如果採用，此提交將完成第四章練習題第二題" (completes Chapter 4 practice problem 2)
+3. "如果採用，此提交將新增執行的腳本" (adds execution scripts)
+
+### Labels
+
+- Documentation (improvements/additions to documentation)
+- Enhancement (new feature or request)
+
+### Assignees
+
+- JulianHsia
+- timmy61109
+- JulianXia-2020
+
+### Linked Issue
+
+"Verilog硬體描述語言實務 第二版 Chapter4" (#47)
+
+### Milestone
+
+Verilog硬體描述語言實務 第二版
+
+### Comments
+
+No substantive comments were recorded in the conversation thread.

issues/Multimedia-Processing_Digital-Logic-Design_pr60

@@ -0,0 +1,43 @@
+# Verilog硬體描述語言實務 第二版 Chapter5 資料留層次之敘述
+
+- Source URL: https://github.com/Multimedia-Processing/Digital-Logic-Design/issues/52
+
+- assign連續指定
+- 運算子
+- 綜合範例
+
+---
+
+## Pull Request
+
+**PR Title:** Verilog硬體描述語言實務 第二版 Chapter5 資料留層次之敘述 (#60)
+
+**PR Number:** #60
+
+**Status:** Merged on December 17, 2020
+
+### Description
+
+The pull request introduces content for Chapter 5 of a Verilog hardware description language textbook (second edition), focusing on dataflow-level descriptions. The contributor listed three main topics:
+
+- assign連續指定 (continuous assignment)
+- 運算子 (operators)
+- 綜合範例 (synthesis examples)
+
+### Key Details
+
+**Author:** timmy61109
+
+**Commits:** 6 commits added between December 3-17, 2020
+
+**Linked Issue:** #52 - "Verilog硬體描述語言實務 第二版 Chapter5 資料留層次之敘述"
+
+**Labels:** documentation, enhancement
+
+**Milestone:** Verilog硬體描述語言實務 第二版
+
+### Notable Elements
+
+The pull request included two example modules: "vector" (demonstrating vector access operations) and "op" (demonstrating operator calculations). Subsequent commits through 2022 expanded the content with arithmetic micro-operations, test files, presentations, and circuit diagrams.
+
+**Reviewers Requested:** JulianHsia, JulianXia-2020

issues/Wren6991_Hazard3_pr23

@@ -0,0 +1,21 @@
+# Fix abstract command using wrong register when initiated by abstractauto
+
+Instance: Wren6991_Hazard3_pr23
+Source: https://github.com/Wren6991/Hazard3/pull/23
+Fetched: 2026-04-26
+Repository: Wren6991/Hazard3
+Pull request: #23
+Author: Wren6991
+State: closed
+Base branch: stable
+Head branch: fix-dm-abstractauto-regno
+Created: 2024-10-12T18:58:43Z
+Updated: 2024-10-12T22:57:18Z
+Closed: 2024-10-12T19:03:45Z
+Merged: 2024-10-12T19:03:45Z
+
+This affects memory downloads from the debugger when System Bus Access is not enabled or not configured.
+
+This bug was introduced in https://github.com/Wren6991/Hazard3/commit/78a5cb98ea5d184c7b8bf31249ce8ac69e4abf68
+
+Releasing as a point fix due to severity and due to the fix being localised to the Debug Module.

issues/Wren6991_Hazard3_pr41

@@ -0,0 +1,36 @@
+# Release v1.1.1 to stable
+
+Instance: Wren6991_Hazard3_pr41
+Source: https://github.com/Wren6991/Hazard3/pull/41
+Fetched: 2026-04-26
+Repository: Wren6991/Hazard3
+Pull request: #41
+Author: Wren6991
+State: closed
+Base branch: stable
+Head branch: develop
+Created: 2026-03-12T18:19:01Z
+Updated: 2026-03-12T18:28:21Z
+Closed: 2026-03-12T18:28:21Z
+Merged: 2026-03-12T18:28:21Z
+
+## PR Title
+Release v1.1.1 to stable
+
+## PR Description
+No description was provided for this pull request. The PR is a release-merge of `develop` into `stable` containing 8 commits that constitute Hazard3 v1.1.1:
+
+1. Update mimpid: 1.2 prerelease
+2. Fix repeated transfer on APB async bridge when instantiated separately to the JTAG-DTM
+3. Don't report failed exclusive writes as faults in `rvfi_bus_observer`; latch `rvfi_intr` signal; fix exclusives hookup in riscv-formal tb
+4. Fix uninitialised variable in `wfi_loop` tests
+5. Fix non-synthesisable statement in `hazard3_rvfi_monitor` when `HAZARD3_RVFI_STANDALONE` is defined
+6. Fix RVFI monitor reporting memory write for exclusive store that fails in data phase
+7. Fix: hardware breakpoint on CSR-writing instruction does not inhibit CSR write
+8. Set `mimpid` version to 1.1.1; update release notes in asciidoc
+
+## PR Comments
+No conversation comments were posted on the PR. No assignees, labels, milestones, or external reviewers.
+
+## Linked Issues
+No linked issues are referenced in this pull request.

issues/aolofsson_oh_pr75

@@ -0,0 +1,20 @@
+# Gpio fpga project
+
+Instance: aolofsson_oh_pr75
+Source: https://github.com/aolofsson/oh/pull/75
+Fetched: 2026-04-26
+Repository: aolofsson/oh
+Pull request: #75
+Author: olajep
+State: closed
+Base branch: master
+Head branch: gpio-fpga-project
+Created: 2016-05-03T15:49:33Z
+Updated: 2016-05-03T17:35:54Z
+Closed: 2016-05-03T17:35:54Z
+Merged: 2016-05-03T17:35:54Z
+
+Reading and writing from Porcupine pins now works.
+
+There's something wrong with edge-triggered interrupts (what you can get via sysfs).
+Loks like clearing the interrupt (in the interrupt handler) will create a new edge and a new interrupt and ... spam the system with interrupts. Will look into that next.

issues/bensampson5_libsv_pr150

@@ -0,0 +1,48 @@
+# Fix reconvergence issue with synchronizer
+
+- Source URL: https://github.com/bensampson5/libsv/issues/149
+
+Synchronizer can't handle multibit data so update to be just a single bit synchronizer
+
+## PR Content from GitHub
+
+# Pull Request Summary
+
+**PR Title:** Fix reconvergence issue in synchronizer
+
+**PR Number:** #150
+
+**Repository:** bensampson5/libsv
+
+**Status:** Merged (February 7, 2022)
+
+---
+
+## PR Description
+The PR description body was not fully visible in the provided content. The only explicit reference states: "Closes #149"
+
+---
+
+## Comments
+
+**Author:** bensampson5
+
+Comment text: "Closes #149"
+
+---
+
+## Linked Issue
+
+**Issue #149 Title:** Fix reconvergence issue with synchronizer
+
+**Issue Description:** The full issue body was not included in the extracted content, though the PR references it as the issue being resolved.
+
+---
+
+## Merge Information
+
+- **Merged by:** bensampson5
+- **Merge commit:** 989a51a
+- **Source branch:** issue-149-Fix_reconvergence_issue_with_synchronizer
+- **Target branch:** main
+- **Commits included:** 1

issues/bensampson5_libsv_pr19

@@ -0,0 +1,32 @@
+# Write Verilator testbench for counter
+
+- Source URL: https://github.com/bensampson5/libsv/issues/7
+
+
+## PR Content from GitHub
+
+# Pull Request Summary
+
+**PR Title:** Docker try catch2 #19
+
+**PR Status:** Merged (December 29, 2020)
+
+**PR Description Body:**
+The description content failed to load properly in the provided page content, showing "Uh oh! There was an error while loading. Please reload this page." However, the PR closing statement indicates: "Closes #7" and "Closes #11"
+
+**PR Comments:**
+No readable comment content was successfully extracted from the conversation section due to loading errors displayed on the page.
+
+**Linked Issues:**
+1. **Issue #11:** "See if catch2 can be leveraged for unit testing IP"
+2. **Issue #7:** "Write Verilator testbench for counter"
+
+**Commits Included (6 total):**
+- Add catch2 install to Dockerfile
+- Integrate catch2
+- Write unit test for counter
+- Added SRC_DIR to CMake
+- Add ninja-build install to Dockerfile
+- Update readme and format counter.sv
+
+**Author:** bensampson5

issues/bensampson5_libsv_pr98

@@ -0,0 +1,16 @@
+# 8b/10b encoder
+
+- Source URL: https://github.com/bensampson5/libsv/issues/97
+
+Implement 8b/10b encoder
+
+https://en.wikipedia.org/wiki/8b/10b_encoding
+
+## Linked Issue Content from GitHub
+
+**Issue #97: 8b/10b encoder**
+
+- Body: "Implement 8b/10b encoder. https://en.wikipedia.org/wiki/8b/10b_encoding"
+- Status: Closed (related PR #98)
+- Assignee: bensampson5, Label: enhancement, Created November 23, 2021
+- Comments: None.

issues/bespoke-silicon-group_basejump_stl_pr472

@@ -0,0 +1,16 @@
+# Potential bug in hardened fifo module
+
+The hardened fifo module contains a variable `read_write_same_addr_n`, which is currently assigned as `wptr_r == rptr_r`. The comment for this variable mentions that it should be 1 when the fifo is empty, but the condition is true for both empty and full fifo conditions. The line in question is given below:
+
+https://github.com/bespoke-silicon-group/basejump_stl/blob/4cfaeb454a7278f7d13eb766dad07ce34fefcdea/bsg_dataflow/bsg_fifo_1r1w_small_hardened.v#L118
+
+If this variable is 1 when the fifo is full, it prevents the memory read as in https://github.com/bespoke-silicon-group/basejump_stl/blob/4cfaeb454a7278f7d13eb766dad07ce34fefcdea/bsg_dataflow/bsg_fifo_1r1w_small_hardened.v#L95
+The assignment can instead be `assign read_write_same_addr_n = empty`.
+
+## Linked Issue Content from GitHub
+
+**Issue #465: Potential bug in hardened fifo module**
+
+- Body: `read_write_same_addr_n = wptr_r == rptr_r` is true for both empty AND full conditions, but the comment says it should be 1 only when empty. When fifo is full, this prevents memory read at line 95 (`r_v_i (~read_write_same_addr_n)`). Suggested fix: `assign read_write_same_addr_n = empty`.
+- Author: Shashank-Vijay, Opened July 19, 2021. Status: Closed (resolved via PR #472). Label: bug.
+- Comments: None.

issues/bespoke-silicon-group_basejump_stl_pr715

@@ -0,0 +1,30 @@
+# Fix ipoly for bank 4 and 8
+
+Instance: bespoke-silicon-group_basejump_stl_pr715
+Source: https://github.com/bespoke-silicon-group/basejump_stl/pull/715
+Fetched: 2026-04-26
+Repository: bespoke-silicon-group/basejump_stl
+Pull request: #715
+Author: tommydcjung
+State: closed
+Base branch: master
+Head branch: hotfix_20250201
+Created: 2025-02-01T13:23:29Z
+Updated: 2025-02-02T00:00:51Z
+Closed: 2025-02-02T00:00:51Z
+Merged: 2025-02-02T00:00:51Z
+
+PR Title: Fix ipoly for bank 4 and 8
+
+PR Description:
+(No description provided.)
+
+PR Comments:
+- tommydcjung (Feb 1, 2025, 13:23): Requested review from gaozihou
+- gaozihou (Feb 1, 2025): "LGTM, simple typo fix" - Approved the changes
+
+Status: Merged by gaozihou into master on Feb 2, 2025 (commit 5a8a602).
+
+Linked Issues: None explicitly mentioned.
+
+Additional Context: The PR contains a single commit (a6c328e) with the message "fix ipoly" and was characterized as a straightforward typo correction.

issues/black-parrot_black-parrot_pr947

@@ -0,0 +1,39 @@
+PR Title: fix LCE uncached store overflow - #945
+
+PR Description:
+Summary: This PR adjusts the cache request valid register in the LCE Request module and tweaks credit counting to prevent overwriting and dropping of uncached store requests.
+
+Issue Fixed: Fixes #945
+
+Area: LCE Request
+
+Reasoning: Functional bug fix
+
+Additional Changes Required: None
+
+Verification: A newly added `mc_uc_store` test in bp-tests exposes this bug. Testing revealed that "~25% of stores were dropped in a sequence of 100 consecutive stores" without the fix. With the fix applied, all stores are accounted for. A debug check was added to catch recurrence.
+
+PR Comments:
+- muwyse (Oct 13, 2021): "Thanks for contributing to BlackParrot! Check out the CONTRIBUTING guide, if this is your first time."
+- dpetrisko (Oct 13, 2021): "Thanks, great!"
+
+Linked Issue #945: "Potential uncached store drops in LCE"
+
+Original local content (issue context):
+Potential uncached store drops in LCE #945
+
+black-parrot/bp_me/src/v/lce/bp_lce_req.sv
+
+Line 223 in b095d30
+
+ // TODO: This could drop uncached stores, if we accept but lce is not ready
+This should be handled as in https://github.com/black-parrot/black-parrot/blob/master/bp_me/src/v/cce/bp_uce.sv#L599. where the request is not accepted if it cannot go on the network (or if there is no currently pending request)
+
+I thought the cache_req_yumi_o signal accounted for this:
+
+black-parrot/bp_me/src/v/lce/bp_lce_req.sv
+
+Line 237 in b095d30
+
+ cache_req_yumi_o = cache_req_v_i
+Namely, the first part of the && conditions is (~cache_req_v_r | lce_req_v_o), which will block a new request from being accepted from the cache if we already have a valid request and it is not sending this cycle.

issues/black-parrot_black-parrot_pr974

@@ -0,0 +1,26 @@
+PR Title: Fix inferred latches
+
+PR Description:
+The pull request removed inferred latches from `bp_me_axil_master` and `bp_me_axil_client` components. The issue was that `state_n` lacked a default value, causing it to become a latch unintentionally.
+
+Area Affected: AXI master and client subcomponents
+
+Linked Issue: Fixes #972
+
+PR Activity:
+- Self-assigned: dpetrisko (Dec 1, 2021)
+- Label added: bug
+- Merged commit: 7f9a1e2 (Dec 14, 2021)
+- Branch deleted: dev_fix_axilatch
+
+Status: Merged on Dec 14, 2021 by dpetrisko.
+
+Linked Issue #972 body:
+I'm using:
+Master branch / dd2d845
+
+Area
+The 'state_n' variables in bp_me_axil_master and client will be inferred into latches due to incomplete cases.
+
+https://github.com/black-parrot/black-parrot/blob/master/bp_me/src/v/network/bp_me_axil_master.sv#L68
+https://github.com/black-parrot/black-parrot/blob/master/bp_me/src/v/network/bp_me_axil_client.sv#L73

issues/chipsalliance_adams-bridge_pr176

@@ -0,0 +1,28 @@
+PR Title: [RTL][TB] Fix issues in compress, decompress, and input checks
+
+PR Description:
+The PR addresses four GitHub issues (165, 167, 168, 169) by implementing several fixes:
+- Input validation for encapsulation keys (each coefficient must be < MLKEM Q)
+- Input validation for decapsulation keys (encapsulation portion and hash verification)
+- Reset of decompress write address after completion
+- Proper timing of done signal in compress operation after all pipeline stages empty
+- Random test cases for both input checks
+
+Commits (10 total):
+The pull request includes commits addressing: decompress write address clearing, done signal timing, sequencer state renaming with ABR prefix, flop coding fixes, decompression logic corrections, error status implementation, test cases for encap/decap input errors, and error state persistence.
+
+Author: Nitsirks
+Reviewer & Merger: mojtaba-bisheh (approved July 30, 2025)
+
+Linked Issues Closed:
+- #165: Compression block done signal assertion timing
+- #167: Second decompression raising done prematurely
+- #168: Decaps flow missing input check
+- #169: Encaps flow missing input check
+
+Linked Issue #165 body:
+# mlkem: compression block done signal asserts before tx end
+
+- Source URL: https://github.com/chipsalliance/adams-bridge/issues/165
+
+In the compression when the last chunk of data being written to the memory the read done is asserted as the last rd is done but data arrives next cycle and buffer_valid_f to be set in next clock cycle. This would set the done and api write would happen in next clock cycle. But if the compress mode toggles in this cycle then the api wr isn't triggered and this causes the loss of data.

issues/chipsalliance_adams-bridge_pr66

@@ -0,0 +1,41 @@
+# [Security question] Extracting HW-bound keys of Caliptra
+
+- Source URL: https://github.com/chipsalliance/adams-bridge/issues/48
+
+Reference commit: 46d8b6e9cfd0020d485012cf261a21278a5e8671
+Related SV files: mldsa_ctrl.sv
+
+### High-level summary
+
+If I understand correctly, when integrated into Caliptra, one of the security properties ABR wants to preserve is the secrecy of HW-bound keys (i.e. the seed originating from Key Vault IP) against Caliptra SW. In other words, ABR wants to make sure that no logical path is introduced to Caliptra with ABR that SW can exploit to extract HW-bound secrets. That should also include the intermediate secret values appearing in ML-DSA algorithms that give an attacker the signing capabilities. Such example values would be s_1, s_2 vectors, which are also part of the secret key.
+
+I reach to this security goal assumption from the fact that there is a dedicated Key Vault IP in Caliptra and that the ABR spec says "If seed comes from key vault, this register will not contain the private key to avoid exposing secret assets to software." (Section 1.10).
+
+I am thinking about the following scenario, and my question is whether the HW-bound secret can be leaked. In particular, I am thinking about leaking s_1 and s_2 values through SW interactions (or simply the signing key as defined in ML-DSA).
+
+If SW is compromised, I suspect it can do the following to extract the secret signing key (originating from Key Vault IP) from ABR:
+
+1. SW loads the seed value from Key Vault (by configuring `mldsa_kv_rd_seed_ctrl` register).
+2. SW starts the KeyGen operation and waits until the operation completes.
+3. In particular, SW does not run zeroize command.
+4. SW reads PRIVKEY_OUT register to extract HW-bound signing key.
+
+### Low-level details
+
+In the following line:
+
+https://github.com/chipsalliance/adams-bridge/blob/46d8b6e9cfd0020d485012cf261a21278a5e8671/src/mldsa_top/rtl/mldsa_ctrl.sv#L585
+
+it seems to me that this line disables reading PRIVKEY_OUT register in two cases:
+
+* In the middle of the KeyGen operation (which is good),
+* when KeyGen is completed but the seed is coming from KeyVault. So I interpret this as an attempt to prevent SW from reading these values at the end of the KeyGen operation (`mldsa_privkey_lock` signal). This part does not seem right to me.
+
+My understanding is that `mldsa_privkey_lock` goes down few clock cycles after KeyGen is completed. I trace this signal to `mldsa_valid_reg` in RTL eventually, if I am not mistaken. I think this signal goes down after few clock cycles KeyGen operation is completed:
+https://github.com/chipsalliance/adams-bridge/blob/46d8b6e9cfd0020d485012cf261a21278a5e8671/src/mldsa_top/rtl/mldsa_ctrl.sv#L187
+
+### Question
+
+I am wondering if SW can extract HW-bound ML-DSA signing key by simply running KeyGen and reading PRIVKEY_OUT register. 
+
+@mojtaba-bisheh @ekarabu

issues/chipsalliance_adams-bridge_pr82

@@ -0,0 +1,27 @@
+# Update directed KATs with pure MLDSA
+
+- Source URL: https://github.com/chipsalliance/adams-bridge/issues/60
+
+PR Title: updated KATs
+Status: Merged on January 30, 2025
+
+Description:
+The PR description provided only states: "Updated KAT vectors"
+
+Commits:
+1. 9c6c65b - "updated KATs"
+2. 1119aa7 - "MICROSOFT AUTOMATED PIPELINE: Stamp 'user/dev/ekarabulut/KAT_uvm_update' with updated timestamp and hash after successful run"
+
+Comments:
+ekarabu (Jan 29, 2025): "Updated KAT vectors"
+Copilot AI (Jan 30, 2025): Could not review the pull request. Five files with unsupported languages were present, including SystemVerilog sequence files and workflow metadata files.
+mojtaba-bisheh (Jan 30, 2025): Approved the changes
+
+Linked Issues:
+- #60 - "Update directed KATs with pure MLDSA" (closed by this PR)
+
+Reviewers:
+- mojtaba-bisheh: Approved
+- Nitsirks: Awaiting review
+- upadhyayulakiran: Awaiting review
+- Copilot: Reviewed (unable to process files)

issues/chipsalliance_caliptra-rtl_pr921

@@ -0,0 +1,36 @@
+# ECC pubkey check in ECDH
+
+- Source URL: https://github.com/chipsalliance/caliptra-rtl/issues/917
+
+In the ECDH feature, ecc_dsa_ctrl we check if the input publickey is on the curve but the flag which is set when publickey is valid is not used for any external output indicating the publickey is valid or invalid. Ideally, I expect an error in this whereas the error_flag is not set in this case.
+
+[This line](https://github.com/chipsalliance/caliptra-rtl/blob/3964d76133a48befb0a192501e6f75b290e2d84e/src/ecc/rtl/ecc_dsa_ctrl.sv#L674) needs to be updated to validate pubkey in both verifying and ECDH flow.
+
+PR Title: [RTL/VAL] Fix ECDH pubkey check
+Status: Merged on July 14, 2025
+
+Description:
+The PR addresses a bug in the ECDH feature where the ecc_dsa_ctrl block performs internal validation of input public keys to verify they lie on the curve. The update ensures that invalid public keys properly trigger error conditions rather than proceeding silently.
+
+Related Issue: #917 - "ECC pubkey check in ECDH"
+
+Key Changes:
+- Fixed ECDH public key validation logic
+- Updated ECC test coverage
+- Includes automated pipeline stamps with updated timestamps
+
+Review & Approval:
+Reviewers:
+- Nitsirks (approved)
+- calebofearth (approved and merged)
+
+Participants: mojtaba-bisheh, calebofearth, Nitsirks
+
+Commits (6 total):
+Notable commits include:
+- "fixed ECDH pbkey check"
+- "updated ecc coverage"
+- Merge commits integrating main branch updates
+- Automated pipeline validation stamps
+
+The pull request successfully passed 78 checks before merging.

issues/hdl-util_hdmi_pr15

@@ -0,0 +1,37 @@
+# add format 34 (1080p30)
+
+Instance: hdl-util_hdmi_pr15
+Source: https://github.com/hdl-util/hdmi/pull/15
+Fetched: 2026-04-26
+Repository: hdl-util/hdmi
+Pull request: #15
+Author: sameer
+State: closed
+Base branch: master
+Head branch: 1080p30
+Created: 2021-02-06T23:53:38Z
+Updated: 2021-02-06T23:57:06Z
+Closed: 2021-02-06T23:57:03Z
+Merged: 2021-02-06T23:57:03Z
+
+## PR Title
+add format 34 (1080p30)
+
+## PR Description
+Derived from contributions by @nockieboy and BrianHG https://www.eevblog.com/forum/fpga/hdmi-dvi-encoder-with-audio-smart-quartus-pll-integration-in-systemverilog/
+
+## PR Comments
+
+**sameer** (Feb 6, 2021):
+"Derived from contributions by @nockieboy and BrianHG https://www.eevblog.com/forum/fpga/hdmi-dvi-encoder-with-audio-smart-quartus-pll-integration-in-systemverilog/"
+
+## PR Metadata
+- Status: Merged
+- Merge commit: 2a35976
+- Branch deleted after merge: 1080p30
+- Reviewers: None
+- Assignees: None
+- Labels: None
+
+## Linked Issues
+No linked issues are referenced in this pull request.

issues/hdl-util_hdmi_pr23

@@ -0,0 +1,19 @@
+# add ip-less option for non intel/xilinx
+
+Instance: hdl-util_hdmi_pr23
+Source: https://github.com/hdl-util/hdmi/pull/23
+Fetched: 2026-04-26
+Repository: hdl-util/hdmi
+Pull request: #23
+Author: sameer
+State: closed
+Base branch: master
+Head branch: no_ip
+Created: 2021-03-07T17:43:44Z
+Updated: 2021-03-07T18:05:15Z
+Closed: 2021-03-07T18:05:11Z
+Merged: 2021-03-07T18:05:11Z
+
+This is the same implementation used in v1.1 but with added ip-less ddr io.
+
+Hopefully it covers lattice and others but I don't know enough about those to confirm.

issues/jotego_jtcores_pr1100

@@ -0,0 +1,21 @@
+# riders -> lgtnfght: correctly implement dimming
+
+- Source URL: https://github.com/jotego/jtcores/issues/1084
+
+## Issue Title
+riders -> lgtnfght: correctly implement dimming
+
+## Issue Description
+Currently (5c567cc92) only the Sunset Riders implementation is in place. The task involves implementing dimming functionality for the lgtnfght (Light Fighting) game on the existing core.
+
+## Issue Comments
+None visible.
+
+## Issue Metadata
+- Status: Closed (resolved via PR #1100)
+- Assignees: jotego, rp-jt
+- Labels: new game on existing core
+- Project: JTCores
+
+## Linked Issues / PRs
+- PR #1100 — resolution

issues/jotego_jtcores_pr1177

@@ -0,0 +1,20 @@
+# support for SRAM memory on Analogue Pocket
+
+- Source URL: https://github.com/jotego/jtcores/issues/1147
+
+## Issue Title
+support for SRAM memory on Analogue Pocket
+
+## Issue Description
+Add SRAM blocks to mem.yaml that can be enabled with macros.
+
+## Issue Comments
+None visible.
+
+## Issue Metadata
+- Status: Closed (linked to PR #1177)
+- Assignee: jotego
+- Project: JTCores (Status: Done)
+
+## Linked Issues / PRs
+- PR #1177 — resolution

issues/jotego_jtcores_pr1242

@@ -0,0 +1,24 @@
+# s18/wwallyj: missing borders
+
+- Source URL: https://github.com/jotego/jtcores/issues/1061
+
+## Issue Title
+s18/wwallyj: missing borders
+
+## Issue Description
+Black borders are missing for the sprites shown when explaining how to play the game (ball, button, table, hands).
+
+Comparison screenshots were provided: the current core output versus the original arcade video, highlighting the visual discrepancy in border rendering.
+
+Arcade reference video: https://www.youtube.com/watch?v=Kn0mct3ZUk4
+
+## Issue Comments
+None visible.
+
+## Issue Metadata
+- Status: Closed (linked to PR #1242)
+- Assignee: rp-jt
+- Project: JTCores
+
+## Linked Issues / PRs
+- PR #1242 — resolution

issues/jotego_jtcores_pr951

@@ -0,0 +1,23 @@
+# Screen rotation on SiDi128 is broken since version 6d1d2ef of cores
+
+- Source URL: https://github.com/jotego/jtcores/issues/950
+
+Commit 8d403ed broke screen rotation on SiDi128. `bitcounter` is set to a wrong value.
+
+This works better:
+
+```diff
+--- a/modules/jtframe/hdl/video/rotate/unsigned_division.v
++++ b/modules/jtframe/hdl/video/rotate/unsigned_division.v
+@@ -37,7 +37,7 @@ always @(posedge clk) begin
+                                        quot<=dividend;
+                                        div<=divisor;
+                                        /* verilator lint_off WIDTH */
+-                                       bitcounter<={widthlog2{1'd1}};
++                                       bitcounter<=(widthlog2[widthlog2-1:0]-1'd1);
+                                        /* verilator lint_on WIDTH */
+                                        state <= RUN;
+                                end                     
+```
+
+Thanks!

issues/kumarrishav14_AMBA_APB_pr18

@@ -0,0 +1,22 @@
+# Add dut
+
+- Source URL: https://github.com/kumarrishav14/AMBA_APB/issues/15
+
+Implement a DUT which is a simple memory having **APB interface**
+
+## Fetched Issue/PR Details
+
+Title: Add dut (#15)
+
+Description: The issue requests implementation of a DUT (Device Under Test) component described as "a simple memory having APB interface."
+
+Repository: kumarrishav14/AMBA_APB
+Status: Closed (via PR #18)
+Assignee: kumarrishav14
+Label: New Feature
+Milestone: version 1 release
+Opened: November 10, 2020
+
+Comments: No comments visible.
+
+Linked Issues: Resolving PR #18.

issues/lowRISC_ibex_pr1839

@@ -0,0 +1,34 @@
+# [pmp] Instruction straddling two TOR regions cosim mismatch
+
+- Source URL: https://github.com/lowRISC/ibex/pull/1839
+
+When running the following test:
+`make -j1 --keep-going IBEX_CONFIG=opentitan ITERATIONS=1 TEST=riscv_epmp_mml_test WAVES=0 COV=0 SEED=30325`
+
+Ibex and Spike have different behavior. Spike throws an instruction access fault exception for the address `0x80005cc4`. The TOR region ends at `0x80005cc4`, which is the expected behavior.
+
+I think Ibex somehow does not perform the check for fetched instructions properly. In this test case there is a branch instruction that straddles two PMP entries, so Ibex must do two requests.
+
+Ibex commit: 0e396d594435c0acca9df785ac40309c76576cc3
+Spike commit: 0dc2de5d76add7b218b31053792a676973034b9e
+
+> estimate 4
+
+## Fetched Issue/PR Details
+
+Title: [if,pmp] Check second bit instead of third for instruction alignment (PR #1839)
+
+Description: The PR addresses a bug where Ibex was checking the wrong bit when looking at PMP errors and when to count the error it received from instruction fetch +2. This PR closes issue #1837 ("[pmp] Instruction straddling two TOR regions cosim mismatch").
+
+Status: Merged
+Author: marnovandermaas
+Merge Date: October 6, 2022
+Reviewer: ctopal (approved)
+Label: Type:Bug
+
+Comments:
+- marnovandermaas (Oct 5, 2022): Provided the description above and noted this fixes a cosmetic simulation mismatch related to PMP instruction alignment checking.
+- ctopal (Oct 6, 2022): Approved the changes after reviewing file modifications.
+- GregAC (Oct 6, 2022): Added the "Type:Bug" label to categorize this as a bug fix.
+
+Linked Issues: Closes #1837 (the cosim mismatch reported above).

issues/lowRISC_ibex_pr1865

@@ -0,0 +1,43 @@
+Observed Behavior
+The core_busy_o output signal of the non-lockstep core is used to gate the core clock, which is used by the regular Ibex core and its lockstep counterpart.
+
+ibex/rtl/ibex_top.sv
+
+Lines 211 to 219 in 3943a4e
+
+ assign clock_en     = core_busy_q | debug_req_i | irq_pending | irq_nm_i; 
+ assign core_sleep_o = ~clock_en; 
+  
+ prim_clock_gating core_clock_gate_i ( 
+   .clk_i    (clk_i), 
+   .en_i     (clock_en), 
+   .test_en_i(test_en_i), 
+   .clk_o    (clk) 
+ ); 
+
+ibex/rtl/ibex_top.sv
+
+Lines 286 to 287 in 3943a4e
+
+ ) u_ibex_core ( 
+   .clk_i(clk), 
+
+ibex/rtl/ibex_top.sv
+
+Lines 927 to 928 in 3943a4e
+
+ ) u_ibex_lockstep ( 
+   .clk_i                  (clk), 
+This means that the lockstep core gets gated in the same clock cycle as the regular core, even though the lockstep core is a few cycles delayed. A low-glitch in the core_busy_o output of the non-lockstep core thus does not lead to a comparison mismatch and a major alert because the lockstep core is already clock-gated when it would produce the value of core_busy_o that is used in the comparison.
+
+ibex/rtl/ibex_lockstep.sv
+
+Lines 453 to 454 in 3943a4e
+
+ assign outputs_mismatch       = enable_cmp_q & (shadow_outputs_q != core_outputs_q[0]); 
+ assign alert_major_internal_o = outputs_mismatch | shadow_alert_major_internal; 
+Expected Behavior
+A low-glitch/mismatch in the core_busy_o output signal of the non-lockstep core should lead to a major alert by the lockstep core.
+
+Steps to reproduce the issue
+Run the chip_sw_ibex_lockstep_glitch test in OpenTitan (currently in lowRISC/opentitan#15221) and override port_idx to the index of core_busy_o in output_ports.

issues/lowRISC_ibex_pr2261

@@ -0,0 +1,90 @@
+# simulator report error
+
+<!--
+Thank you for your interest in Ibex. We are continuously improving Ibex, and your bug report will help us with that. To help us understand and reproduce your problem as quickly as possible we have prepared a little template below.
+
+No text in blocks starting with < !-- will be shown in the final bug report.
+
+You can also copy/paste images into the bug report, and you can attach files to it by simply dragging them into the issue window.
+-->
+
+## Observed Behavior
+Test ibex in verilator with cosim, simulator report error illegal instruction.
+```
+001003e8 <main>:
+  1003e8:	1141                	addi	sp,sp,-16
+  1003ea:	c606                	sw	ra,12(sp)
+  1003ec:	0000                	unimp                # <---  This is the illegal instruction!
+  1003ee:	0000                	unimp
+  1003f0:	37b9                	jal	10033e <func>
+  1003f2:	00000517          	auipc	a0,0x0
+  1003f6:	05650513          	addi	a0,a0,86 # 100448 <main+0x60>
+  1003fa:	3959                	jal	100090 <puts>
+  1003fc:	40b2                	lw	ra,12(sp)
+  1003fe:	4501                	li	a0,0
+  100400:	0141                	addi	sp,sp,16
+  100402:	8082                	ret
+```
+```
+DASM(0x00010413)
+mv      s0, sp
+```
+
+![Image](https://github.com/user-attachments/assets/321158de-0306-44b2-a11b-64c2fcfc4a7f)
+
+MTVAL in `ibex_simple_system.log` file is 0x00000000
+<!--
+Please describe the problem you saw. Include waveforms (in VCD or Verilator/GtkWave FST format only please) and log files if possible.
+-->
+
+## Expected Behavior
+The terminal should print right mtval value.
+<!-- Please describe the behavior you expected to see instead. -->
+
+## Steps to reproduce the issue
+Run `build/lowrisc_ibex_ibex_simple_system_cosim_0/sim-verilator/Vibex_simple_system --meminit=ram,ibex/examples/sw/simple_system/input/test.elf`
+```
+#include "simple_system_common.h"
+int main(void){
+    // puts("Starting test");
+    __asm__ volatile(".word 0x000000");
+    puts("Test complete");
+    return 0;
+}
+```
+<!--
+Please help us to reproduce the issue you're seeing by including a detailed description of what you did to get to the problem.
+
+For example:
+* What command did you run? (Also include the output of the command.)
+* What parameters/defines did you set?
+* Did you make modifications to the source code?
+-->
+
+## My Environment
+Build verilator to run ibex by [co-sim](https://ibex-core.readthedocs.io/en/latest/03_reference/cosim.html#quick-build-and-run-instructions).
+<!--
+Let us know how you're using Ibex. This helps us to better understand your problem and find a solution more quickly.
+-->
+
+**EDA tool and version:**
+None
+<!--
+If you are using an EDA tool to work with Ibex let us know which tool and which version you're using.
+For example, "Xilinx Vivado 2020.1" or "Synopsys VCS 2020.03-SP1"
+-->
+
+**Operating system:**
+Ubuntu Linux 18.04
+<!--
+Please let us know the operating system/Linux distribution you're using.
+For example "Ubuntu Linux 18.04" or "CentOS 7.3".
+-->
+
+**Version of the Ibex source code:**
+8f4c75c5e43e61b994248307c814e01860303056
+<!--
+Which version of the Ibex source code are you using?
+You can call `git rev-parse HEAD` in your Ibex source directory to get this information.
+Please also let us know if you have made changes to the code.
+-->

issues/muneeb-mbytes_pulpino__spi_master__ip_verification_pr42

@@ -0,0 +1,53 @@
+# Develop the first testcase
+
+- Source URL: https://github.com/muneeb-mbytes/pulpino__spi_master__ip_verification/issues/10
+
+Title: Develop the first testcase #10
+
+Body: We need to develop a testcase and run to check the flow
+
+Comments: None
+
+Linked PR: #42 (closed)
+
+Metadata:
+- Assignee: venkateshs-t
+- Milestone: 💻 Development
+- Status: Closed
+- Created: February 5, 2022
+- Author: muneebullashariff
+
+---
+
+## Pull Request
+
+**PR Title:** [PR] :: Added Directed testcases for each feature mention in the following issues
+
+**PR Number:** #42
+
+**Status:** Merged on Feb 18, 2022
+
+### Description
+
+The contributor proposed synchronizing with the RTL VIPs integration branch and developing directed testcases aligned with feature requirements. Key accomplishments include:
+
+- Created initial testcase with required sequences and virtual sequences
+- Demonstrated data flow from APB master and SPI slave
+- Developed directed testcases for features outlined in issue #41
+
+**Testcases Added:**
+Twelve testcases covering basic read/write operations, standard mode configurations with varying command/address/data lengths, dummy cycle generation, clock division settings (even/odd), and timing parameter variations.
+
+### Comments
+
+**venkateshs-t** (Feb 17, 2022):
+"Fixes #10 #14 #41" - The contributor linked three related issues, indicating this work addresses multiple feature development and testing objectives.
+
+**muneebullashariff** (Feb 18, 2022):
+Approved changes with comment: "Accepting the changes"
+
+### Linked Issues Closed
+
+- Develop the first testcase (#10)
+- Develop more tests (#14)
+- Develop Directed Testcases (#41)

issues/muneeb-mbytes_pulpino__spi_master__ip_verification_pr56

@@ -0,0 +1,26 @@
+# Incorrect Sampling of MOSI data
+
+- Source URL: https://github.com/muneeb-mbytes/pulpino__spi_master__ip_verification/issues/46
+
+**Brief explanation of the question/help**
+![image](https://user-images.githubusercontent.com/91044066/154654361-e0e54fd0-462f-4e01-b07e-760e85513ff5.png)
+![image](https://user-images.githubusercontent.com/91044066/154654513-40ef35ef-3cf2-40a0-8044-067d37249038.png)
+![image](https://user-images.githubusercontent.com/91044066/154654940-dcee028e-f69d-4d87-b7c3-2f15dd2d6be6.png)
+
+if you can see in fig(1) the first 2 locked cursors shows 8 bits of command data
+and 2nd block shows you the next 8 bits of address data
+and the last block shows you the 32 bits of actual MOSI data
+
+In fig(2) shows you the both MOSI data that has been sampled and MISO data that was driven 
+so if you observe MOSI data the MOSI[0] tells the first 8 bits of **CMD** data and MOSI[1] shows the next 8 bits of **ADDR** data and remaining four MOSI transfers shows the **actual data** 
+
+In fig(3) i have shown you the 8 bits of command data which is indicated by **SPICMD** label which is of **FF** but if you can observe the sampled command data in fig(2) it is **FE** there is 1 bit missing(last bit is supposed be 1 but it is sampling 0 this you can observe in fig(1))
+
+Similarly for the address data bits and for the actual data bits there is miss match in data that has been send to the sampled data
+
+**Branch name:**  test_cases_branch
+**Test_name:**  apb_master_std_mode_write_8_cmd_8_addr_32_data_length_test.sv
+
+**Add the required following items to the issue**
+1.  Projects
+2.  Milestone

issues/muneeb-mbytes_pulpino__spi_master__ip_verification_pr61

@@ -0,0 +1,45 @@
+# Develop more test for covering the coverage holes
+
+- Source URL: https://github.com/muneeb-mbytes/pulpino__spi_master__ip_verification/issues/18
+
+Title: Develop more test for covering the coverage holes
+
+Body: No description provided.
+
+Comments: None
+
+Linked PR: #61 (Closed)
+
+Metadata:
+- Assignee: venkateshs-t
+- Milestone: 🥂 Coverage Closure
+
+## PR Title
+[PR] :: Testcases for Coverage closure
+
+## PR Description
+Fixes #18
+
+Changes proposed in this pull request:
+- Added more tests cases to cover the coverage holes as suggested
+- added negative testcases for lsb shift
+- added tx fifo testcase to hit the max count of fifo
+- added the write test for 8 bit dummy cycles
+
+Make sure you do the following:
+- Create the pull request to branch development_branch_v1
+- Use @mention to assign this pull request
+- Select Reviewer
+
+## PR Comments
+
+**muneebullashariff** (March 14, 2022):
+"Approved!"
+
+## Linked Issue
+#18: Develop more test for covering the coverage holes
+
+## PR Metadata
+- Author: venkateshs-t
+- Reviewer/Merger: muneebullashariff
+- Status: Merged (March 14, 2022)

issues/muneeb-mbytes_pulpino__spi_master__subsystem_verification_pr28

@@ -0,0 +1,47 @@
+# Integrate RTL and VIPs
+
+- Source URL: https://github.com/muneeb-mbytes/pulpino__spi_master__subsystem_verification/issues/4
+
+Title: Integrate RTL and VIPs #4
+
+Body: Integrate the RTL design and VIPs by developing the top module
+
+Comments: None
+
+Linked PR: #28 (Closed)
+
+Metadata:
+- Assignee: sivareddykostam
+- Milestone: 💻 Development
+- Status: Closed
+
+## PR Title
+Added the final width for the axi data
+
+## PR Description
+Fixes: #4 #2 #6
+
+Changes proposed in this pull request:
+- adding the .gitignore file
+- updated the collector
+
+Requirements checklist:
+- Create the pull request to branch development_branch_v1
+- Use @mention to assign this pull request
+- Select Reviewer
+
+## PR Comments
+
+**sivareddykostam** (Mar 14, 2022):
+"added the .gitignore file to remove the unwanted files"
+
+## Linked Issue
+#4: Integrate RTL and VIPs
+
+## PR Metadata
+- Author: sivareddykostam
+- Source Branch: collector_branch
+- Target Branch: development_branch_v1
+- Assignee: sivareddykostam
+- Milestone: 💻 Development
+- Status: Merged (Mar 14, 2022)

issues/olofk_serv_pr105

@@ -0,0 +1,38 @@
+# alu with support for W=4
+
+Instance: olofk_serv_pr105
+Source: https://github.com/olofk/serv/pull/105
+Fetched: 2026-04-26
+Repository: olofk/serv
+Pull request: #105
+Author: uhit332
+State: closed
+Base branch: main
+Head branch: incremental
+Created: 2023-10-31T11:31:13Z
+Updated: 2023-10-31T11:42:58Z
+Closed: 2023-10-31T11:42:52Z
+Merged: 2023-10-31T11:42:52Z
+
+## PR Title
+alu with support for W=4
+
+## PR Description
+No description provided.
+
+## PR Comments
+
+**uhit332** (Contributor, Oct 31, 2023):
+No description provided.
+
+**olofk** (Owner, Oct 31, 2023):
+"Excellent! Approved"
+
+## Linked Issues
+No linked issues.
+
+## PR Metadata
+- Source branch: uhit332/serv:incremental
+- Target branch: olofk/serv:main
+- No reviews, assignees, labels, or milestone
+- Merged by olofk on Oct 31, 2023 (commit 2e23b53)

issues/openhwgroup_cv32e40s_pr259

@@ -0,0 +1,32 @@
+# Wrong execute permission with mseccfg.MML and no matching region
+
+### Component
+
+**Component:RTL**: For issues in the RTL (e.g. for files in the rtl directory)
+
+### Steps to Reproduce
+When the first instruction after reset sets mseccfg.MML, the fetch of the next instruction actually goes through. However, the Smepmp spec states that for MML set, "Executing code from a region without a matching rule or with a matching S/U-mode-only rule is denied." With no PMPs set up, the whole memory should thus be denied execute access after setting MML. This is also nicely illustrated in the picture in section 2.2: setting MML is enough to deny execute rights to M mode without a matching region.
+The issue was found with assertion RV_chk.ops.XCPT_IF_ID_a of the OneSpin Processor Verification App.
+
+## PR Title
+PMP fix (issue 249)
+
+## PR Description
+Should fix #249
+
+Signed-off-by: Arjan Bink <Arjan.Bink@silabs.com>
+
+## PR Comments
+
+**Silabs-ArjanB** (July 18, 2022):
+"Should fix #249. Signed-off-by: Arjan Bink Arjan.Bink@silabs.com"
+
+## Linked Issue
+#249: Wrong execute permission with mseccfg.MML and no matching region
+
+## PR Metadata
+- Author: Silabs-ArjanB
+- Reviewer: silabs-oivind (review requested)
+- Labels: Component:RTL
+- Status: Merged (July 18, 2022)
+- Commit hash: 38ed6a0

issues/pulp-platform_apb_pr2

@@ -0,0 +1,22 @@
+# APB4 structs
+
+Instance: pulp-platform_apb_pr2
+Source: https://github.com/pulp-platform/apb/pull/2
+Fetched: 2026-04-26
+Repository: pulp-platform/apb
+Pull request: #2
+Author: WRoenninger
+State: closed
+Base branch: master
+Head branch: apb-structs
+Created: 2020-02-21T14:43:13Z
+Updated: 2020-03-13T10:05:08Z
+Closed: 2020-03-13T10:05:07Z
+Merged: 2020-03-13T10:05:07Z
+
+This PR  mainly has the same changes as [#1](https://github.com/pulp-platform/apb/pull/1).
+However this differs in the regard that the changes made here have the same structure as in the [AXI repository](https://github.com/pulp-platform/axi).
+* Added struct typedef macros.
+* Added struct assign macros.
+* Added APB4 read only / write only registers (+testbenches).
+* Added synthesis bench.

issues/pulp-platform_apb_pr3

@@ -0,0 +1,20 @@
+# apb_regs: Tool compatibility improvements
+
+Instance: pulp-platform_apb_pr3
+Source: https://github.com/pulp-platform/apb/pull/3
+Fetched: 2026-04-26
+Repository: pulp-platform/apb
+Pull request: #3
+Author: zarubaf
+State: closed
+Base branch: master
+Head branch: tool-fixes
+Created: 2020-04-23T07:10:42Z
+Updated: 2026-02-14T23:10:27Z
+Closed: 2022-12-02T15:03:23Z
+Merged: 2022-12-02T15:03:23Z
+
+- Some tools require explicit hints on the type
+  for the structured assignment.
+- Reset values driven from signals are generally considered
+  unsafe. A tiny FSM initializes these values.

issues/pulp-platform_apb_pr8

@@ -0,0 +1,35 @@
+# Adds an APB Error Slave
+
+Instance: pulp-platform_apb_pr8
+Source: https://github.com/pulp-platform/apb/pull/8
+Fetched: 2026-04-26
+Repository: pulp-platform/apb
+Pull request: #8
+Author: meggiman
+State: closed
+Base branch: master
+Head branch: apb_err_slv
+Created: 2022-12-05T20:41:29Z
+Updated: 2026-02-14T23:10:24Z
+Closed: 2022-12-20T12:13:33Z
+Merged: 2022-12-20T12:13:33Z
+
+## PR Title
+Adds an APB Error Slave
+
+## PR Description
+Depends on #7
+
+## PR Comments
+
+**meggiman** (Dec 5, 2022):
+"Depends on #7"
+
+**meggiman** (Dec 20, 2022):
+Marked the pull request as ready for review.
+
+**paulsc96** (Dec 20, 2022):
+Force-pushed changes and merged commit c736c05 into master.
+
+## Linked Issues
+No linked issues are referenced in this pull request.

issues/pulp-platform_axi_pr74

@@ -0,0 +1,25 @@
+# Verilator compile issues
+
+I am working on simulating the AXI4 code in Verilator and are running into a problem with the parameter types of the modules. The issue is the `parameter type resp_t = logic` definition in al modules. However renaming the definitions to `parameter type rsp_t = logic` seems to not trigger the issue. I think the issue could be that in `axi_pkg` the parameter `resp_t` is already defined and part of the response struct which is the parameter which has this problem. 
+Should I do a fix for all modules, this will however break all other projects which are using the new AXI4 infrastructure currently. 
+
+Related to Verilator: In #43 there is in file `src/axi_dw_upsizer.sv` line 321 a struct definition for `r_req_d` and `r_req_q` inside a generate. Verilator complains about multiple type definitions.
+I was able to fix this by declaring a separate typedef outside the generate and defining the signals separate in the generate:
+
+```systemverilog
+typedef struct packed {
+      ar_chan_t ar         ;
+      logic ar_valid       ;
+      logic ar_throw_error ;
+      slv_r_chan_t r       ;
+      logic r_valid        ;
+      burst_len_t burst_len;
+      size_t orig_ar_size  ;
+} r_req_t;
+
+// code
+
+for (genvar ...
+  r_req_t r_req_d, r_req_q;
+end
+```

issues/pulp-platform_axi_riscv_atomics_pr15

@@ -0,0 +1,52 @@
+# Guarantee atomicity by tracking downstream transactions
+
+Instance: pulp-platform_axi_riscv_atomics_pr15
+Source: https://github.com/pulp-platform/axi_riscv_atomics/pull/15
+Fetched: 2026-05-03
+Repository: pulp-platform/axi_riscv_atomics
+Pull request: #15
+Author: SamuelRiedel
+State: closed
+Base branch: master
+Head branch: testbench
+Created: 2022-02-23
+Updated: 2022-03-11
+Closed: 2022-03-11
+Merged: 2022-03-11
+
+## PR Title
+Guarantee atomicity by tracking downstream transactions
+
+## PR Description
+This PR adds several updates to the axi_riscv_atomics repository:
+
+- `axi_riscv_lrsc`: Tracks downstream writes to guarantee atomicity, addressing cases where reads can overtake writes in the downstream AXI bus, violating atomicity guarantees.
+- `axi_riscv_amos`: Uses the updated `axi_riscv_lrsc` module to guarantee atomicity of atomic memory operations without duplicating logic; translates AMOs into LR and SC operations.
+- `axi_riscv_atomics_tb`: Adds a testbench to verify both modules together.
+
+The PR initially contained a bug identified in issue #16, which was subsequently fixed.
+
+## PR Comments
+
+**SamuelRiedel** (Feb 23, 2022):
+Requested review from andreaskurth, noting the PR contains WIP commits that looked good and offering to split into multiple PRs if preferred.
+
+**SamuelRiedel** (Mar 11, 2022):
+Indicated readiness pending AXI upstream changes and official release.
+
+**andreaskurth** (Mar 11, 2022):
+Approved changes; released axi v0.35.0.
+
+**SamuelRiedel** (Mar 11, 2022):
+Confirmed new AXI release works as expected; approved for merge.
+
+## Linked Issues
+
+**Issue #3: Add unit and top-level TBs to repo**
+Requires some common verification modules to be updated first.
+
+**Issue #4: Fix ordering guarantees for multiple outstanding and conflicting SWs/SCs/AMOs**
+(Closed by this PR; body not available.)
+
+**Issue #16: typedef typo in axi_riscv_lrsc.sv**
+(Closed by this PR; body not available.)

issues/pulp-platform_axi_riscv_atomics_pr27

@@ -0,0 +1,32 @@
+# [fix] lrsc: Add missing sequential logic for aw_wait reg
+
+Instance: pulp-platform_axi_riscv_atomics_pr27
+Source: https://github.com/pulp-platform/axi_riscv_atomics/pull/27
+Fetched: 2026-04-26
+Repository: pulp-platform/axi_riscv_atomics
+Pull request: #27
+Author: niwis
+State: closed
+Base branch: master
+Head branch: fix/aw_wait
+Created: 2023-08-02T15:42:06Z
+Updated: 2023-08-02T20:47:22Z
+Closed: 2023-08-02T16:42:57Z
+Merged: 2023-08-02T16:42:57Z
+
+## PR Title
+[fix] lrsc: Add missing sequential logic for aw_wait reg
+
+## PR Description
+Not sure how this was missed so far.
+
+## PR Comments
+
+**niwis** (Aug 2, 2023):
+"Not sure how this was missed so far"
+
+**SamuelRiedel** (Aug 2, 2023):
+"Thanks! I also wonder how we could have missed this. But it indicates that the testbench never reaches the `AW_BURST` state. We have to double-check this."
+
+## Linked Issues
+No linked issues are referenced in this pull request.

issues/pulp-platform_axi_riscv_atomics_pr31

@@ -0,0 +1,37 @@
+# lrsc: Fix burst invalidation length
+
+Instance: pulp-platform_axi_riscv_atomics_pr31
+Source: https://github.com/pulp-platform/axi_riscv_atomics/pull/31
+Fetched: 2026-05-03
+Repository: pulp-platform/axi_riscv_atomics
+Pull request: #31
+Author: niwis
+State: closed
+Base branch: master
+Head branch: nwistoff/lrsc-burst-len
+Created: 2023-10-02
+Updated: 2023-10-05
+Closed: 2023-10-05
+Merged: 2023-10-05
+
+## PR Title
+lrsc: Fix burst invalidation length
+
+## PR Description
+Terminate invalidation after the last beat. Fixes #30.
+
+## PR Comments
+
+**niwis** (Oct 2, 2023):
+Requested review from SamuelRiedel.
+
+**SamuelRiedel** (Oct 5, 2023):
+Force-pushed the branch with commit 427f84d.
+
+**SamuelRiedel** (Oct 5, 2023):
+Merged commit 424697e into master and deleted the nwistoff/lrsc-burst-len branch.
+
+## Linked Issues
+
+**Issue #30: AW burst of length N clears N+1 addresses**
+When an AW burst of length N with start address A is sent to the axi_riscv_lrsc module, it submits a check+clear request for addresses [A, A+N], but the correct range would be [A, A+(N-1)]. Probably it would be sufficient to change line 761 from `clr_len_d = aw_res_len - 1;` to `clr_len_d = aw_res_len - 2;`.

issues/pulp-platform_carfield_pr41

@@ -0,0 +1,49 @@
+# Add atomics support to shared L2 memory
+
+Instance: pulp-platform_carfield_pr41
+Source: https://github.com/pulp-platform/carfield/pull/41
+Fetched: 2026-05-03
+Repository: pulp-platform/carfield
+Pull request: #41
+Author: alex96295
+State: closed
+Base branch: main
+Head branch: aottaviano/l2-atomics
+Created: 2023-05-17
+Updated: 2023-05-30
+Closed: 2023-05-30
+Merged: 2023-05-30
+
+## PR Title
+Add atomics support to shared L2 memory
+
+## PR Description
+Expose extra parameters to config the `axi_riscv_atomics_structs`. They default to Cheshire, which is fine for now. Fixes #34.
+
+## PR Comments
+
+**alex96295** (May 17, 2023):
+"Expose extra parameters to config the `axi_riscv_atomics_structs`. They default to Cheshire, which is fine for now."
+
+**husterZC** (May 17, 2023):
+"Aha ;) , Thanks Ale!"
+
+**husterZC** (May 17, 2023):
+"Should we also change the `Bender.lock` there?"
+
+**alex96295** (May 17, 2023):
+"I upstreamed it"
+
+**alex96295** (May 21, 2023):
+"Rebased onto main"
+
+**alex96295** (May 30, 2023):
+"Rebased onto main"
+
+**alex96295** (May 30, 2023):
+"lgtm"
+
+## Linked Issues
+
+**Issue #34: Check `atomics`: `axi_riscv_atomics_structs` before the L2 SPM**
+Atomics support is needed towards every memory inside `carfield`. `Cheshire` already instantiates `axi_riscv_atomics_structs` before the main memory, the debug module and the `idma` slave port. We need it before the `L2SPM`.