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verilog_data-1 / AngeloJacobo_UberDDR3 /rtl
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SAIFIINDUSTRIES
Add batch 5 (vicharak-in_shrike, hunterlew_convolution_network_on_FPGA, jhshi_openofdm, dpretet_async_fifo, AngeloJacobo_UberDDR3)
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