verilog_data-1 / AngeloJacobo_UberDDR3

51 MB

1 contributor

Add batch 5 (vicharak-in_shrike, hunterlew_convolution_network_on_FPGA, jhshi_openofdm, dpretet_async_fifo, AngeloJacobo_UberDDR3)

12bef33 verified 3 days ago

example_demo
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formal
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rtl
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testbench
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vivado_custom_ip
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.gitignore

558 Bytes
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LICENSE

35.1 kB
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README.md

26 kB
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flake.lock

2.98 kB
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flake.nix

1.86 kB
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run_compile.sh

2.36 kB
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