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Datasets:
SAIFIINDUSTRIES
/
verilog_data-1
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verilog_data-1
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AngeloJacobo_UberDDR3
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rtl
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spd
65.5 kB
1 contributor
History:
1 commit
SAIFIINDUSTRIES
Add batch 5 (vicharak-in_shrike, hunterlew_convolution_network_on_FPGA, jhshi_openofdm, dpretet_async_fifo, AngeloJacobo_UberDDR3)
12bef33
verified
6 days ago
i2c_master.sv
Safe
27.3 kB
Add batch 5 (vicharak-in_shrike, hunterlew_convolution_network_on_FPGA, jhshi_openofdm, dpretet_async_fifo, AngeloJacobo_UberDDR3)
6 days ago
spd_clk_wiz.v
Safe
1 kB
Add batch 5 (vicharak-in_shrike, hunterlew_convolution_network_on_FPGA, jhshi_openofdm, dpretet_async_fifo, AngeloJacobo_UberDDR3)
6 days ago
spd_reader.v
Safe
28.8 kB
Add batch 5 (vicharak-in_shrike, hunterlew_convolution_network_on_FPGA, jhshi_openofdm, dpretet_async_fifo, AngeloJacobo_UberDDR3)
6 days ago
spd_reader_top.v
Safe
3.12 kB
Add batch 5 (vicharak-in_shrike, hunterlew_convolution_network_on_FPGA, jhshi_openofdm, dpretet_async_fifo, AngeloJacobo_UberDDR3)
6 days ago
uart_tx.v
Safe
5.27 kB
Add batch 5 (vicharak-in_shrike, hunterlew_convolution_network_on_FPGA, jhshi_openofdm, dpretet_async_fifo, AngeloJacobo_UberDDR3)
6 days ago
