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verilog_data-1

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verilog_data-1 / AngeloJacobo_UberDDR3 /rtl /ecp5_phy

28.8 kB

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Add batch 5 (vicharak-in_shrike, hunterlew_convolution_network_on_FPGA, jhshi_openofdm, dpretet_async_fifo, AngeloJacobo_UberDDR3)

12bef33 verified 6 days ago

ddr3_phy_ecp5.v

19.1 kB
Add batch 5 (vicharak-in_shrike, hunterlew_convolution_network_on_FPGA, jhshi_openofdm, dpretet_async_fifo, AngeloJacobo_UberDDR3) 6 days ago
iserdes_soft.v

6.79 kB
Add batch 5 (vicharak-in_shrike, hunterlew_convolution_network_on_FPGA, jhshi_openofdm, dpretet_async_fifo, AngeloJacobo_UberDDR3) 6 days ago
oserdes_soft.v

2.87 kB
Add batch 5 (vicharak-in_shrike, hunterlew_convolution_network_on_FPGA, jhshi_openofdm, dpretet_async_fifo, AngeloJacobo_UberDDR3) 6 days ago