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🧠 ASIC Design Roadmap

Empowering students worldwide with a complete roadmap to learn Application Specific Integrated Circuit (ASIC) Design — from logic to layout, RTL to GDSII.

بِسْمِ اللهِ الرَّحْمنِ الرَّحِيم

“وَمَا أُوتِيتُمْ مِنَ الْعِلْمِ إِلَّا قَلِيلًا”

The journey of designing an ASIC (Application Specific Integrated Circuit) is long and deeply technical — transforming an idea into silicon requires precision, planning, and patience. Despite the final chip being only a few nanometers in scale, the design process includes multiple sophisticated steps filled with engineering challenges and opportunities for learning.

ASICs are purpose-built chips tailored for specific applications. Unlike general-purpose processors or FPGAs, they are optimized for power, performance, and area (PPA), making them ideal for mass production. Their circuits, built from permanent gates and flip-flops, are described using hardware description languages such as Verilog, SystemVerilog, or VHDL.

✅ More power-efficient than FPGAs
✅ Capable of higher frequencies
✅ Ideal for high-volume production
⚠️ Not suitable for frequent upgrades
⚠️ Bugs after tape-out are costly

📌 Why This Roadmap?

Many students and entry-level engineers want to break into the world of IC design but are unsure where to begin or how to build strong fundamentals. When you search for resources online, the flood of random posts and YouTube videos can leave you even more lost and overwhelmed. That’s why I decided to build this open-source roadmap — to make the learning process smoother and more organized for anyone looking to enter the industry.

🎯 Who Is This For?

Whether you’re a student, fresh graduate, or an engineer transitioning into VLSI, this roadmap is tailored to help you navigate Physical Design — one of the most critical and challenging domains in ASIC development.

🚀 What’s Inside?

This roadmap is not just a list of tools or topics. It’s a carefully structured guide with:

Step-by-step learning paths from basic concepts to industry-level knowledge

Hands-on projects and scripts to give you practical experience

Tips and insights from real-world Physical Design workflows

Links to trusted resources — not just random Google or YouTube results

🧾 Introduction

The aim of this roadmap is to provide aspiring ASIC and Digital IC designers a clear path to follow — with carefully selected courses, resources, and projects that balance theory and practice. Whether you're a beginner or transitioning from FPGA/Embedded design, this roadmap is crafted to guide you through every phase of ASIC development.

🧱 Fundamentals

1. Digital Electronics & CMOS Basics

Digital Electronics (Playlist) 📽
Focus: Logic gates, FFs, CMOS inverter, MOSFET switching.

2. Digital Logic Design / Frontend

3. Computer Architecture

Digital Design and Computer Architecture (YouTube) 📽

4. Digital IC Design (RTL to ASIC)

Based on "CMOS VLSI Design" by Weste & Harris

Part 1 📽
Part 2 📽
Part 3 📽

🔧 ASIC Design Flow

Logic Synthesis & Timing Closure

Advanced Logic Synthesis by Dhiraj Taneja 📽
Includes Synopsys DC/PT Labs – skip first 12 videos if needed

Physical Design

Physical Design – Prof. Indranil Sengupta 📽
Covers Floorplanning, Placement, CTS, Routing, DRC/LVS
RTL to GDSII (by Adi Teman) 📽
Very recommended ✅
My Slideshare RTL2GDSII Notes 📚

🌍 Awesome Digital IC Resources

Curated lists and tools for ASIC/VLSI/FPGA engineers

Name	Type	Description
Awesome FPGA	📍⭐	FPGA resources and boards
Awesome HDL	📍⭐	Hardware description languages
Awesome Open Source EDA	📍	Open-source EDA tools
Awesome Hardware Verification	📍	Verification tools
Awesome HWD Tools	📍	Open-source IC design tools
Awesome Lattice FPGAs	📍	Lattice FPGA board list

📦 Project Repositories and IPs

Core IPs and Repos

OpenCores ⭐ - IP Cores Archive
FreeCores 📍 - Legacy IPs from OpenCores
Basic Verilog Modules 📍 - Synthesizable Verilog modules
32 Mini Projects (Verilog) 📍👶

Communication Protocols

Alex Forencich's IPs - PCIe, Ethernet, I2C, UART and more

Information Technology

RISC-V

RISC-V Instruction Set Manual - This repository contains the LaTeX source for the draft RISC-V Instruction Set Manual.
RISC-V Exchange: Cores & SoCs - A list of RICS-V cores and SoCs.
PULP - Open source Parallel Ultra-Low-Power RISC-V core.
openc910 📍 - OpenXuantie C910 Core.
XiangShan 📍 - Open-source high-performance RISC-V processor.
riscv-starship 📍 - Run rocket-chip on FPGA(Xilinx Virtex-7 VC707).
Wujian100 📍 - A MCU base SoC.
picorv32 📍 - A Size-Optimized RISC-V CPU.
Hummingbirdv2 E203 Core and SoC 📍 Docs - A Ultra-Low Power RISC-V Core.
darkriscv 📍 - A proof of concept for the opensource RISC-V instruction set.
CVA6 RISC-V CPU 📍 - An application class 6-stage RISC-V CPU capable of booting Linux.
VexRiscv 📍 - A FPGA friendly 32 bit RISC-V CPU implementation.

Others

zipcpu ⭐📍 - with detailed comments.
openmsp430 - The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog.
Nyuzi Processor 📍 - GPGPU microprocessor architecture.

Tutorials and Courses 💬Intro

zipcpu 👶 - Verilog, Formal Verification and Verilator Beginner's Tutorial
WORLD OF ASIC ⭐ - A great source of detailed VLSI tutorials and examples.

HDL

More information about hardware description language on Awesome HDL

Verilog Grammar

Verilog TUTORIAL for beginners 👶 - A tutorial based upon free Icarus Verilog compiler.
ChipVerify: Verilog Tutorial - A guide for someone new to Verilog.
Verilog/SystemVerilog Guide 📍 - A guide covering Verilog & SystemVerilog.

VHDL Grammar

VHDL Guide 📍 - A guide covering VHDL.

Verification

Verification Academy - The most comprehensive resource for verification training.
Verification Guide - Tutorials with links to example codes on EDA Playground.
Doulos - Global training solutions for engineers creating the world's electronics products.
testbench - Some training articals for systemverilog.
ClueLogic - Providing the clues to solve your verification problems.
ChipVerify - A simple and complete set of verilog/System Verilog/UVM tutorials.

Build a CPU

RISC-V Guide 📍 - A guide covering the RISC-V Architecture.
ARM Guide 📍 - A guide covering ARM architecture.
nand2tetris - Build an advanced computer from nand gate.
Building a RISC-V CPU Core - edX 📽 - Build a RISC-V cpu core. No prior knowledge of digital logic design is required.
Build a Modern Computer from First Principles: From Nand to Tetris - coursera 📽 - Build a modern computer system.

FPGA

FPGA Tutorial
Complex Programmable Logic Device (CPLD) Guide 📍 - A guide covering CPLD.

Tools

EDA Playground - Edit, save, simulate, synthesize SystemVerilog, Verilog, VHDL and other HDLs from your web browser.
tree-core-ide 📍- A VSCode-based HDL extension.
WaveDrom - Digital Timing Diagram everywhere
Icarus Verilog 📍Github - A Verilog simulation and synthesis tool.
GTKWave - GTKWave is a fully featured GTK+ based wave viewer.
OpenROAD 💬Doc 📍Github - An RTL-to-GDS Flow
More information about hardware dv tools on Awesome Open Hardware Verification - Tools and Awesome HWD Tools

Online Judge Platforms

HDL bits - A collection of small circuit design exercises for practicing digital hardware design using Verilog Hardware Description Language (HDL).
nowcoder - Verilog Part - A verilog oj platform.

🧠 Final Thoughts

🔹 Start slow, stay consistent.
🔹 Simulate everything before synthesizing.
🔹 Join VLSI communities and open-source projects.
🔹 Learn by doing – replicate designs, break them, and fix them.

If this roadmap helped you, consider sharing it with others or contributing back to the repo!
📬 For inquiries or collaborations: a.abdelazeem201@gmail.com

“Whoever treads a path in search of knowledge, Allah will make easy for him the path to Paradise.” – Prophet Muhammad ﷺ