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Datasets:
SAIFIINDUSTRIES
/
verilog_data-1
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xet
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27be9c5
verilog_data-1
/
abdelazeem201_ASIC-Design-Roadmap
/
IC Compiler
28.5 kB
1 contributor
History:
1 commit
SAIFIINDUSTRIES
Add batch 3 (alexforencich_verilog-uart, schlae_graphics-gremlin, quanzaihh_Neural-Network-Accelerator, google_CFU-Playground, abdelazeem201_ASIC-Design-Roadmap)
a33685b
verified
7 days ago
01_design_planning.tcl
5.43 kB
Add batch 3 (alexforencich_verilog-uart, schlae_graphics-gremlin, quanzaihh_Neural-Network-Accelerator, google_CFU-Playground, abdelazeem201_ASIC-Design-Roadmap)
7 days ago
02_preroute.tcl
4.47 kB
Add batch 3 (alexforencich_verilog-uart, schlae_graphics-gremlin, quanzaihh_Neural-Network-Accelerator, google_CFU-Playground, abdelazeem201_ASIC-Design-Roadmap)
7 days ago
create_phy_cell.tcl
915 Bytes
Add batch 3 (alexforencich_verilog-uart, schlae_graphics-gremlin, quanzaihh_Neural-Network-Accelerator, google_CFU-Playground, abdelazeem201_ASIC-Design-Roadmap)
7 days ago
io.tdf
17.6 kB
Add batch 3 (alexforencich_verilog-uart, schlae_graphics-gremlin, quanzaihh_Neural-Network-Accelerator, google_CFU-Playground, abdelazeem201_ASIC-Design-Roadmap)
7 days ago
