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Datasets:
SAIFIINDUSTRIES
/
verilog_data-1
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xet
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27be9c5
verilog_data-1
/
AngeloJacobo_UberDDR3
/
testbench
44.6 MB
1 contributor
History:
1 commit
SAIFIINDUSTRIES
Add batch 5 (vicharak-in_shrike, hunterlew_convolution_network_on_FPGA, jhshi_openofdm, dpretet_async_fifo, AngeloJacobo_UberDDR3)
12bef33
verified
6 days ago
axi_tb
Add batch 5 (vicharak-in_shrike, hunterlew_convolution_network_on_FPGA, jhshi_openofdm, dpretet_async_fifo, AngeloJacobo_UberDDR3)
6 days ago
icarus_sim
Add batch 5 (vicharak-in_shrike, hunterlew_convolution_network_on_FPGA, jhshi_openofdm, dpretet_async_fifo, AngeloJacobo_UberDDR3)
6 days ago
models
Add batch 5 (vicharak-in_shrike, hunterlew_convolution_network_on_FPGA, jhshi_openofdm, dpretet_async_fifo, AngeloJacobo_UberDDR3)
6 days ago
spd_tb
Add batch 5 (vicharak-in_shrike, hunterlew_convolution_network_on_FPGA, jhshi_openofdm, dpretet_async_fifo, AngeloJacobo_UberDDR3)
6 days ago
xsim
Add batch 5 (vicharak-in_shrike, hunterlew_convolution_network_on_FPGA, jhshi_openofdm, dpretet_async_fifo, AngeloJacobo_UberDDR3)
6 days ago
8192Mb_ddr3_parameters.vh
Safe
39.5 kB
Add batch 5 (vicharak-in_shrike, hunterlew_convolution_network_on_FPGA, jhshi_openofdm, dpretet_async_fifo, AngeloJacobo_UberDDR3)
6 days ago
README.txt
Safe
3.16 kB
Add batch 5 (vicharak-in_shrike, hunterlew_convolution_network_on_FPGA, jhshi_openofdm, dpretet_async_fifo, AngeloJacobo_UberDDR3)
6 days ago
ddr3.sv
Safe
167 kB
Add batch 5 (vicharak-in_shrike, hunterlew_convolution_network_on_FPGA, jhshi_openofdm, dpretet_async_fifo, AngeloJacobo_UberDDR3)
6 days ago
ddr3_dimm.sv
Safe
18.2 kB
Add batch 5 (vicharak-in_shrike, hunterlew_convolution_network_on_FPGA, jhshi_openofdm, dpretet_async_fifo, AngeloJacobo_UberDDR3)
6 days ago
ddr3_dimm_micron_sim.sv
Safe
51.3 kB
Add batch 5 (vicharak-in_shrike, hunterlew_convolution_network_on_FPGA, jhshi_openofdm, dpretet_async_fifo, AngeloJacobo_UberDDR3)
6 days ago
ddr3_dimm_micron_sim_behav.wcfg
Safe
50.3 kB
Add batch 5 (vicharak-in_shrike, hunterlew_convolution_network_on_FPGA, jhshi_openofdm, dpretet_async_fifo, AngeloJacobo_UberDDR3)
6 days ago
ddr3_module.sv
Safe
35.4 kB
Add batch 5 (vicharak-in_shrike, hunterlew_convolution_network_on_FPGA, jhshi_openofdm, dpretet_async_fifo, AngeloJacobo_UberDDR3)
6 days ago
design.txt
Safe
76 Bytes
Add batch 5 (vicharak-in_shrike, hunterlew_convolution_network_on_FPGA, jhshi_openofdm, dpretet_async_fifo, AngeloJacobo_UberDDR3)
6 days ago
readme.txt
Safe
9.42 kB
Add batch 5 (vicharak-in_shrike, hunterlew_convolution_network_on_FPGA, jhshi_openofdm, dpretet_async_fifo, AngeloJacobo_UberDDR3)
6 days ago
sim_defines.vh
Safe
423 Bytes
Add batch 5 (vicharak-in_shrike, hunterlew_convolution_network_on_FPGA, jhshi_openofdm, dpretet_async_fifo, AngeloJacobo_UberDDR3)
6 days ago
