task_id string | shuttle_name string | project_name string | task_name string | system_message string | prompt string | golden_module string |
|---|---|---|---|---|---|---|
ttsky25b_0301 | ttsky25b | StrasTi-8-Bit-ALU | task_eight_bit_alu | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "constants/constants.vh" 1
// ALU operation codes
// Bit width definitions
// ALU status flag
// ALU overflow flag
`line 34 "constants/constants.vh" 2
`line 1 "modules/one_bit_alu.v" 1
// Copyright 2026 Timon Strassern
//
// Licensed under the Apache License, V... | module eight_bit_alu (
input [8-1:0] a8_i,
input [8-1:0] b8_i,
input [5-1:0] f8_i,
input carry_borrow_i,
output [8-1:0] y8_o,
output carry_borrow_o,
output [1:0] status_flag_o
);
wire [8-1:0] carry_bits;
wire [8-1:0] borrow_bits;
reg carry_borrow_out;
reg [1:0] status_flag;
... |
ttsky25b_0302 | ttsky25b | StrasTi-8-Bit-ALU | task_enable_gate | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "constants/constants.vh" 1
// ALU operation codes
// Bit width definitions
// ALU status flag
// ALU overflow flag
`line 34 "constants/constants.vh" 2
`line 1 "modules/one_bit_alu.v" 1
// Copyright 2026 Timon Strassern
//
// Licensed under the Apache License, V... | module enable_gate(
input input_i,
input enable_i,
output output_o
);
assign output_o = enable_i ? input_i : 0;
endmodule |
ttsky25b_0303 | ttsky25b | StrasTi-8-Bit-ALU | task_full_adder | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "constants/constants.vh" 1
// ALU operation codes
// Bit width definitions
// ALU status flag
// ALU overflow flag
`line 34 "constants/constants.vh" 2
`line 1 "modules/one_bit_alu.v" 1
// Copyright 2026 Timon Strassern
//
// Licensed under the Apache License, V... | module full_adder(
input a_i,
input b_i,
input carry_in_i,
output carry_out_o,
output sum_o
);
wire first_xor_o, second_xor_o, first_and_o, second_and_o;
// A xor B
xor_gate first_xor (.a_i(a_i), .b_i(b_i), .result_o(first_xor_o));
// (A xor B) xor carry_in
xor_gate second_xor... |
ttsky25b_0304 | ttsky25b | StrasTi-8-Bit-ALU | task_full_subtractor | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "constants/constants.vh" 1
// ALU operation codes
// Bit width definitions
// ALU status flag
// ALU overflow flag
`line 34 "constants/constants.vh" 2
`line 1 "modules/one_bit_alu.v" 1
// Copyright 2026 Timon Strassern
//
// Licensed under the Apache License, V... | module full_subtractor(
input a_i,
input b_i,
input borrow_in_i,
output borrow_out_o,
output diff_o
);
wire a_b_xor_o, nota_b_and_o, bout_and_o;
// A xor B
xor_gate first_xor (.a_i(a_i), .b_i(b_i), .result_o(a_b_xor_o));
// not A and B
and_gate first_and (.a_i(~a_i), .b_i(b_i)... |
ttsky25b_0305 | ttsky25b | StrasTi-8-Bit-ALU | task_inverter_gate | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "constants/constants.vh" 1
// ALU operation codes
// Bit width definitions
// ALU status flag
// ALU overflow flag
`line 34 "constants/constants.vh" 2
`line 1 "modules/one_bit_alu.v" 1
// Copyright 2026 Timon Strassern
//
// Licensed under the Apache License, V... | module inverter_gate(
input input_i,
input invert_i,
output output_o
);
// if invert_i = '1', a_i gets inverted
assign output_o = invert_i ? ~input_i : input_i;
endmodule |
ttsky25b_0306 | ttsky25b | StrasTi-8-Bit-ALU | task_or_gate | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "constants/constants.vh" 1
// ALU operation codes
// Bit width definitions
// ALU status flag
// ALU overflow flag
`line 34 "constants/constants.vh" 2
`line 1 "modules/one_bit_alu.v" 1
// Copyright 2026 Timon Strassern
//
// Licensed under the Apache License, V... | module or_gate(
input a_i,
input b_i,
output reg result_o
);
// using built in operator:
// assign result_o = a_i || b_i;
always @(*) begin : or_logic
if (a_i == 1'b1 || b_i == 1'b1)
result_o = 1'b1;
else
result_o = 1'b0;
end
endmodule |
ttsky25b_0307 | ttsky25b | StrasTi-8-Bit-ALU | task_top_level_alu_control | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "constants/constants.vh" 1
// ALU operation codes
// Bit width definitions
// ALU status flag
// ALU overflow flag
`line 34 "constants/constants.vh" 2
`line 1 "modules/one_bit_alu.v" 1
// Copyright 2026 Timon Strassern
//
// Licensed under the Apache License, V... | module top_level_alu_control(
input wire [7:0] alu_in, // ALU data input
input wire [7:0] ctrl_in, // ALU operation control
output wire [7:0] alu_out, // ALU controlled output (result or status)
input wire clk, // clock
input wire rst_n // reset_n - low to reset
);
... |
ttsky25b_0308 | ttsky25b | StrasTi-8-Bit-ALU | task_xor_gate | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "constants/constants.vh" 1
// ALU operation codes
// Bit width definitions
// ALU status flag
// ALU overflow flag
`line 34 "constants/constants.vh" 2
`line 1 "modules/one_bit_alu.v" 1
// Copyright 2026 Timon Strassern
//
// Licensed under the Apache License, V... | module xor_gate(
input a_i,
input b_i,
output reg result_o
);
// using built in operator:
// assign result_o = a_i ^ b_i;
always @(*) begin : xor_logic
if ((a_i == 1'b0 && b_i == 1'b0) || (a_i == 1'b1 && b_i == 1'b1))
result_o = 1'b0;
else
result_o = 1'b1... |
ttgf0p2_0309 | ttgf0p2 | TinyTapeout-tt-waferspace-vga-screensaver | task_bitmap_rom | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_waferspace_vga_screensaver.v" 1
/*
* Copyright (c) 2024 Tiny Tapeout LTD
* SPDX-License-Identifier: Apache-2.0
* Author: Uri Shaked
*/
`default_nettype none
parameter LOGO_SIZE = 128; // Size of the logo in pixels
parameter DISPLAY_WIDTH = 640; // VGA display width
parameter DISPLAY_HEIGHT = 480;... | module bitmap_rom (
input wire [6:0] x,
input wire [6:0] y,
output wire pixel
);
reg [7:0] mem[2047:0];
initial begin
mem[0] = 8'h00;
mem[1] = 8'h00;
mem[2] = 8'h00;
mem[3] = 8'h00;
mem[4] = 8'h00;
mem[5] = 8'h00;
mem[6] = 8'h00;
mem[7] = 8'h00;
mem[8] = 8'h00;
m... |
ttsky25b_0310 | ttsky25b | TobiasPfaffeneder-tt-sky25b-can-you-count-binary-game | task_bcd_splitter | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_dip_switch_game_TobiasPfaffeneder.v" 1
/*
* Top-level module for the "dip_switch_game" project
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
`line 9 "tt_um_dip_switch_game_TobiasPfaffeneder.v" 0
`line 1 "sevenseg_display_controller.v" 1
`default_nettype none
`line 2 "sevenseg_d... | module bcd_splitter (
input wire [7:0] value,
output wire [3:0] hundreds,
output wire [3:0] tens,
output wire [3:0] ones
);
// xxxx_full wires are required because for example "hundreds = (value / 8'd100)[3:0]" leads to an error (Linter warnings can be ignored)
wire [7:0] hundreds_full = value /... |
ttsky25b_0311 | ttsky25b | TobiasPfaffeneder-tt-sky25b-can-you-count-binary-game | task_blink_controller | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_dip_switch_game_TobiasPfaffeneder.v" 1
/*
* Top-level module for the "dip_switch_game" project
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
`line 9 "tt_um_dip_switch_game_TobiasPfaffeneder.v" 0
`line 1 "sevenseg_display_controller.v" 1
`default_nettype none
`line 2 "sevenseg_d... | module blink_controller (
input wire clk,
input wire rst,
input wire enable,
input wire [7:0] timer_value,
input wire [7:0] MAXTIME,
output reg point_state
);
reg [15:0] blink_counter = 0;
wire [15:0] blink_threshold;
wire [7:0] remaining = MAXTIME - timer_value;
wire [7:0] third... |
ttsky25b_0312 | ttsky25b | TobiasPfaffeneder-tt-sky25b-can-you-count-binary-game | task_digit_selector | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_dip_switch_game_TobiasPfaffeneder.v" 1
/*
* Top-level module for the "dip_switch_game" project
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
`line 9 "tt_um_dip_switch_game_TobiasPfaffeneder.v" 0
`line 1 "sevenseg_display_controller.v" 1
`default_nettype none
`line 2 "sevenseg_d... | module digit_selector (
input wire clk,
input wire rst,
input wire trigger,
output reg [1:0] state = 2'b11,
output reg done = 1'b0
);
reg [10:0] counter = 0;
reg pause = 0;
reg active = 0;
reg [1:0] digit = 0;
localparam DISPLAY_TIME = 1000; // 1 second
localparam PAUSE_TI... |
ttsky25b_0313 | ttsky25b | TobiasPfaffeneder-tt-sky25b-can-you-count-binary-game | task_random_number_generator | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_dip_switch_game_TobiasPfaffeneder.v" 1
/*
* Top-level module for the "dip_switch_game" project
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
`line 9 "tt_um_dip_switch_game_TobiasPfaffeneder.v" 0
`line 1 "sevenseg_display_controller.v" 1
`default_nettype none
`line 2 "sevenseg_d... | module random_number_generator (
input wire clk,
input wire rst,
output reg [7:0] random
);
wire feedback = random[7] ^ random[5] ^ random[4] ^ random[3];
always @(posedge clk or posedge rst) begin
if (rst)
random <= 8'hA5;
else
random <= {random[6:0], feedba... |
ttsky25b_0314 | ttsky25b | TobiasPfaffeneder-tt-sky25b-can-you-count-binary-game | task_sevenseg_decoder | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_dip_switch_game_TobiasPfaffeneder.v" 1
/*
* Top-level module for the "dip_switch_game" project
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
`line 9 "tt_um_dip_switch_game_TobiasPfaffeneder.v" 0
`line 1 "sevenseg_display_controller.v" 1
`default_nettype none
`line 2 "sevenseg_d... | module sevenseg_decoder (
input wire [3:0] digit,
output reg [6:0] seg
);
always @(*) begin
case (digit)
4'd0: seg = 7'b0111111;
4'd1: seg = 7'b0000110;
4'd2: seg = 7'b1011011;
4'd3: seg = 7'b1001111;
4'd4: seg = 7'b1100110;
4'd... |
ttsky25b_0315 | ttsky25b | TobiasPfaffeneder-tt-sky25b-can-you-count-binary-game | task_sevenseg_display_controller | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_dip_switch_game_TobiasPfaffeneder.v" 1
/*
* Top-level module for the "dip_switch_game" project
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
`line 9 "tt_um_dip_switch_game_TobiasPfaffeneder.v" 0
`line 1 "sevenseg_display_controller.v" 1
`default_nettype none
`line 2 "sevenseg_d... | module sevenseg_display_controller(
input wire clk,
input wire rst,
input wire trigger,
input wire [7:0] value,
output wire [6:0] seg,
output wire done
);
wire [1:0] state;
wire [3:0] hundreds, tens, ones;
reg [3:0] current_digit;
localparam DISPLAY_OFF = 4'd10;
bcd_splitte... |
ttsky25b_0316 | ttsky25b | TobiasPfaffeneder-tt-sky25b-can-you-count-binary-game | task_timer | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_dip_switch_game_TobiasPfaffeneder.v" 1
/*
* Top-level module for the "dip_switch_game" project
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
`line 9 "tt_um_dip_switch_game_TobiasPfaffeneder.v" 0
`line 1 "sevenseg_display_controller.v" 1
`default_nettype none
`line 2 "sevenseg_d... | module timer (
input wire clk,
input wire rst,
input wire restart_timer,
output reg [7:0] timer_value
);
localparam TIMER_DURATION = 10'd1000; // 1 second
reg [9:0] counter = 0;
reg active = 0;
always @(posedge clk or posedge rst) begin
if (rst) begin
counter <= 0... |
ttsky26a_0317 | ttsky26a | Tomvdsch-tt-cyclonerunner | task_audio_engine | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "project.v" 1
module tt_um_tomvdsch_cyclopsrunner (
input wire [7:0] ui_in,
output wire [7:0] uo_out,
input wire [7:0] uio_in,
output wire [7:0] uio_out,
output wire [7:0] uio_oe,
input wire ena,
input wire clk,
input wire rst_n
);
wire core_rst_n = rs... | module audio_engine (
input wire clk,
input wire rst_n,
input wire frame_tick,
input wire audio_tick,
input wire game_over,
output reg audio_pwm
);
localparam [11:0] H_A2 = 12'd3551;
localparam [11:0] H_B2 = 12'd3164;
localparam [11:0] H_C3 = 12'd2986;
localparam [2:0] STE... |
ttsky26a_0318 | ttsky26a | Tomvdsch-tt-cyclonerunner | task_game_state | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "project.v" 1
module tt_um_tomvdsch_cyclopsrunner (
input wire [7:0] ui_in,
output wire [7:0] uo_out,
input wire [7:0] uio_in,
output wire [7:0] uio_out,
output wire [7:0] uio_oe,
input wire ena,
input wire clk,
input wire rst_n
);
wire core_rst_n = rs... | module game_state (
input wire clk,
input wire rst_n,
input wire frame_tick,
input wire jump_btn,
input wire duck_btn,
input wire start_btn,
output reg [6:0] player_y,
output wire ducking,
output wire game_over,
output reg ... |
ttsky26a_0319 | ttsky26a | Tomvdsch-tt-cyclonerunner | task_gamepad_pmod_single | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "project.v" 1
module tt_um_tomvdsch_cyclopsrunner (
input wire [7:0] ui_in,
output wire [7:0] uo_out,
input wire [7:0] uio_in,
output wire [7:0] uio_out,
output wire [7:0] uio_oe,
input wire ena,
input wire clk,
input wire rst_n
);
wire core_rst_n = rs... | module gamepad_pmod_single (
input wire rst_n,
input wire clk,
input wire pmod_data,
input wire pmod_clk,
input wire pmod_latch,
output wire start,
output wire up,
output wire down,
output wire a,
output wire b
);
reg [1:0] data_sync;
reg [1:0] clk_sync;
reg [1... |
ttsky26a_0320 | ttsky26a | Tomvdsch-tt-cyclonerunner | task_renderer | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "project.v" 1
module tt_um_tomvdsch_cyclopsrunner (
input wire [7:0] ui_in,
output wire [7:0] uo_out,
input wire [7:0] uio_in,
output wire [7:0] uio_out,
output wire [7:0] uio_oe,
input wire ena,
input wire clk,
input wire rst_n
);
wire core_rst_n = rs... | module renderer (
input wire clk,
input wire rst_n,
input wire [9:0] pix_x,
input wire [9:0] pix_y,
input wire visible,
input wire game_over,
input wire [6:0] player_y,
input wire ducking,
input wire [8:0] obs0_x,
input wire [8:0] obs1_x... |
ttsky26a_0321 | ttsky26a | Tomvdsch-tt-cyclonerunner | task_vga_timing | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "project.v" 1
module tt_um_tomvdsch_cyclopsrunner (
input wire [7:0] ui_in,
output wire [7:0] uo_out,
input wire [7:0] uio_in,
output wire [7:0] uio_out,
output wire [7:0] uio_oe,
input wire ena,
input wire clk,
input wire rst_n
);
wire core_rst_n = rs... | module vga_timing (
input wire clk,
input wire rst_n,
output reg [9:0] pix_x,
output reg [9:0] pix_y,
output wire visible,
output wire hsync,
output wire vsync,
output wire frame_tick
);
localparam H_VISIBLE = 10'd640;
localparam H_FRONT ... |
ttgf26b_0322 | ttgf26b | Ushaop-op-ttgf-spi | task_reg_file | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_spi_slave.v" 1
`default_nettype none
module tt_um_spi_slave (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, //... | module reg_file (
input wire clk,
input wire rst_n,
input wire [2:0] addr,
input wire [7:0] wdata,
input wire we,
output reg [7:0] rdata,
output wire [7:0] reg0_out
);
reg [7:0] storage [0:7];
integer i;
assign reg0_out = storage[0];
always @(posedg... |
ttgf26b_0323 | ttgf26b | Ushaop-op-ttgf-spi | task_spi_slave | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_spi_slave.v" 1
`default_nettype none
module tt_um_spi_slave (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, //... | module spi_slave (
input wire clk,
input wire rst_n,
input wire sclk,
input wire mosi,
output reg miso,
input wire cs_n,
output reg [2:0] reg_addr,
output reg [7:0] reg_wdata,
output reg reg_we,
input wire [7:0] reg_rdata
);
... |
ttgf26b_0324 | ttgf26b | Vincent2405-BSD-Convolution-Adder-Tree-TinyTapeout | task_DIG_ROM_512X5_FilterKernel | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "project.v" 1
/*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_Vincent2405_adder_tree (
input wire [7:0] ui_in,
output wire [7:0] uo_out,
input wire [7:0] uio_in,
output wire [7:0] uio_out,
output wire [7:0] uio_oe,
inpu... | module DIG_ROM_512X5_FilterKernel (
input [8:0] A,
input sel,
output reg [4:0] D
);
reg [4:0] my_rom [0:511];
always @ (*) begin
if (~sel)
D = 5'hz;
else
D = my_rom[A];
end
initial begin
my_rom[0] = 5'h0;
my_rom[1] = 5'h1;
my_... |
ttgf26b_0325 | ttgf26b | Vincent2405-BSD-Convolution-Adder-Tree-TinyTapeout | task_DIG_Register | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "project.v" 1
/*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_Vincent2405_adder_tree (
input wire [7:0] ui_in,
output wire [7:0] uo_out,
input wire [7:0] uio_in,
output wire [7:0] uio_out,
output wire [7:0] uio_oe,
inpu... | module DIG_Register
(
input C,
input en,
input D,
output Q
);
reg state = 'h0;
assign Q = state;
always @ (posedge C) begin
if (en)
state <= D;
end
endmodule |
ttgf26b_0326 | ttgf26b | Vincent2405-BSD-Convolution-Adder-Tree-TinyTapeout | task_HDC_Calc | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "project.v" 1
/*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_Vincent2405_adder_tree (
input wire [7:0] ui_in,
output wire [7:0] uo_out,
input wire [7:0] uio_in,
output wire [7:0] uio_out,
output wire [7:0] uio_oe,
inpu... | module HDC_Calc (
input [7:0] R3,
input [7:0] R2,
input [7:0] R0,
input [7:0] R1,
output [7:0] BUNDLE
);
assign BUNDLE = ((R3 ^ R2) & (R0 ^ R1));
endmodule |
ttgf26b_0327 | ttgf26b | Vincent2405-BSD-Convolution-Adder-Tree-TinyTapeout | task_Mux_2x1 | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "project.v" 1
/*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_Vincent2405_adder_tree (
input wire [7:0] ui_in,
output wire [7:0] uo_out,
input wire [7:0] uio_in,
output wire [7:0] uio_out,
output wire [7:0] uio_oe,
inpu... | module Mux_2x1
(
input [0:0] sel,
input in_0,
input in_1,
output reg out
);
always @ (*) begin
case (sel)
1'h0: out = in_0;
1'h1: out = in_1;
default:
out = 'h0;
endcase
end
endmodule |
ttgf26b_0328 | ttgf26b | Vincent2405-BSD-Convolution-Adder-Tree-TinyTapeout | task_Mux_8x1 | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "project.v" 1
/*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_Vincent2405_adder_tree (
input wire [7:0] ui_in,
output wire [7:0] uo_out,
input wire [7:0] uio_in,
output wire [7:0] uio_out,
output wire [7:0] uio_oe,
inpu... | module Mux_8x1
(
input [2:0] sel,
input in_0,
input in_1,
input in_2,
input in_3,
input in_4,
input in_5,
input in_6,
input in_7,
output reg out
);
always @ (*) begin
case (sel)
3'h0: out = in_0;
3'h1: out = in_1;
3'h2: out = in_2;
... |
ttgf26b_0329 | ttgf26b | Vincent2405-BSD-Convolution-Adder-Tree-TinyTapeout | task_RomInterpretation | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "project.v" 1
/*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_Vincent2405_adder_tree (
input wire [7:0] ui_in,
output wire [7:0] uo_out,
input wire [7:0] uio_in,
output wire [7:0] uio_out,
output wire [7:0] uio_oe,
inpu... | module RomInterpretation (
input [7:0] w3,
input [7:0] w4,
input [7:0] w5,
input [7:0] w6,
input [7:0] w7,
input [7:0] w8,
input [7:0] w9,
input [7:0] w1,
input [7:0] w2,
input clk,
input en,
input rst, // active_high
output [4:0] o1,
output [4:0] o2,
output [4:0] o3,
output [4:0] o4,
... |
ttgf26b_0330 | ttgf26b | Vincent2405-BSD-Convolution-Adder-Tree-TinyTapeout | task_SPIReader | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "project.v" 1
/*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_Vincent2405_adder_tree (
input wire [7:0] ui_in,
output wire [7:0] uo_out,
input wire [7:0] uio_in,
output wire [7:0] uio_out,
output wire [7:0] uio_oe,
inpu... | module SPIReader (
input A0,
input A1,
input A2,
input A3,
input A4,
input A5,
input A6,
input A7,
input A8,
input A9,
input A10,
input A11,
input A12,
input A13,
input A14,
input A15,
input CLK,
input START,
input MISO,
input rst,
output MOSI,
output [7:0] R3,
output [7:0]... |
ttgf26b_0331 | ttgf26b | Vincent2405-BSD-Convolution-Adder-Tree-TinyTapeout | task_TinyTapeoutAdderTreeMitSPI_HDC | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "project.v" 1
/*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_Vincent2405_adder_tree (
input wire [7:0] ui_in,
output wire [7:0] uo_out,
input wire [7:0] uio_in,
output wire [7:0] uio_out,
output wire [7:0] uio_oe,
inpu... | module TinyTapeoutAdderTreeMitSPI_HDC (
input [7:0] ui_in,
input clk,
input rst,
input \[uio1] ,
input \[uio4] ,
input \[uio5] ,
input \[uio6] ,
input \[uio7] ,
output [7:0] uo_out,
output \[uio0] ,
output \[uio2] ,
output \[uio3]
);
wire [4:0] s0;
wire [7:0] s1;
wire [4:0] s2;
wire [7:... |
ttgf26b_0332 | ttgf26b | Vincent2405-BSD-Convolution-Adder-Tree-TinyTapeout | task_conv5to8 | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "project.v" 1
/*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_Vincent2405_adder_tree (
input wire [7:0] ui_in,
output wire [7:0] uo_out,
input wire [7:0] uio_in,
output wire [7:0] uio_out,
output wire [7:0] uio_oe,
inpu... | module conv5to8 (
input [4:0] in,
output [15:0] \10bdd
);
assign \10bdd [0] = in[0];
assign \10bdd [1] = 1'b1;
assign \10bdd [2] = in[1];
assign \10bdd [3] = 1'b1;
assign \10bdd [4] = in[2];
assign \10bdd [5] = 1'b1;
assign \10bdd [6] = in[3];
assign \10bdd [7] = 1'b1;
assign \10bdd [8] = in[4];
... |
ttgf26b_0333 | ttgf26b | Vincent2405-BSD-Convolution-Adder-Tree-TinyTapeout | task_shift1 | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "project.v" 1
/*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_Vincent2405_adder_tree (
input wire [7:0] ui_in,
output wire [7:0] uo_out,
input wire [7:0] uio_in,
output wire [7:0] uio_out,
output wire [7:0] uio_oe,
inpu... | module shift1 (
input [7:0] in,
output [7:0] out
);
assign out[0] = 1'b0;
assign out[1] = in[0];
assign out[2] = in[1];
assign out[3] = in[2];
assign out[4] = in[3];
assign out[5] = in[4];
assign out[6] = in[5];
assign out[7] = in[6];
endmodule |
ttgf26b_0334 | ttgf26b | Vincent2405-BSD-Convolution-Adder-Tree-TinyTapeout | task_shift2 | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "project.v" 1
/*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_Vincent2405_adder_tree (
input wire [7:0] ui_in,
output wire [7:0] uo_out,
input wire [7:0] uio_in,
output wire [7:0] uio_out,
output wire [7:0] uio_oe,
inpu... | module shift2 (
input [7:0] in,
output [7:0] out
);
assign out[0] = 1'b0;
assign out[1] = 1'b0;
assign out[2] = in[0];
assign out[3] = in[1];
assign out[4] = in[2];
assign out[5] = in[3];
assign out[6] = in[4];
assign out[7] = in[5];
endmodule |
ttgf26b_0335 | ttgf26b | Vincent2405-BSD-Convolution-Adder-Tree-TinyTapeout | task_shift3 | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "project.v" 1
/*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_Vincent2405_adder_tree (
input wire [7:0] ui_in,
output wire [7:0] uo_out,
input wire [7:0] uio_in,
output wire [7:0] uio_out,
output wire [7:0] uio_oe,
inpu... | module shift3 (
input [7:0] in,
output [7:0] out
);
wire s0;
assign out[0] = 1'b0;
assign out[1] = 1'b0;
assign out[2] = 1'b0;
assign out[3] = in[0];
assign out[4] = in[1];
assign out[5] = in[2];
assign out[6] = in[3];
assign out[7] = in[4];
assign s0 = in[5];
endmodule |
ttgf26b_0336 | ttgf26b | Vincent2405-BSD-Convolution-Adder-Tree-TinyTapeout | task_shift4 | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "project.v" 1
/*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_Vincent2405_adder_tree (
input wire [7:0] ui_in,
output wire [7:0] uo_out,
input wire [7:0] uio_in,
output wire [7:0] uio_out,
output wire [7:0] uio_oe,
inpu... | module shift4 (
input [17:0] in,
output [25:0] out
);
assign out[0] = 1'b1;
assign out[1] = 1'b0;
assign out[2] = 1'b1;
assign out[3] = 1'b0;
assign out[4] = 1'b1;
assign out[5] = 1'b0;
assign out[6] = 1'b1;
assign out[7] = 1'b0;
assign out[8] = in[0];
assign out[9] = in[1];
assign out[10] = i... |
ttsky26a_0337 | ttsky26a | XeonicsCA-ECE298A-TT-MAU | task_add10 | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "alu_pkg.sv" 1
// ALU control structure definition
package alu_pkg;
typedef struct packed {
// X lane
logic pre_x_en; // 0:x0, 1:add
logic pre_x_sub; // 0:add, 1:sub
logic mul_x_en; // 0:m0,m1, 1:mul
logic [2:0] mul_x_sel; // 0:x0, 1:x1, 2:... | module add10 (
input logic en,
input logic sub, // 0 to add, 1 to sub
input logic [9:0] a, b,
output logic [9:0] res,
output logic carry
);
logic [10:0] tmp;
logic [4:0] a_5;
logic [4:0] b_5;
logic [10:0] a_11;
logic [10:0] b_11;
always_comb begin
// default values
tmp = '0;
res = '0;
... |
ttsky26a_0338 | ttsky26a | XeonicsCA-ECE298A-TT-MAU | task_alu_stage_4b | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "alu_pkg.sv" 1
// ALU control structure definition
package alu_pkg;
typedef struct packed {
// X lane
logic pre_x_en; // 0:x0, 1:add
logic pre_x_sub; // 0:add, 1:sub
logic mul_x_en; // 0:m0,m1, 1:mul
logic [2:0] mul_x_sel; // 0:x0, 1:x1, 2:... | module alu_stage_4b (
input logic clk, rst_n,
input logic [3:0] x0, x1, // inputs from operand router
input logic [3:0] y0, y1,
input alu_pkg::alu_ctrl_t ctrl, // control from decode
// handshake logic with op decode/tx stage
input logic cmd_valid, // rx command in is valid
output logic cmd_ready,... |
ttsky26a_0339 | ttsky26a | XeonicsCA-ECE298A-TT-MAU | task_decode_stage_4b | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "alu_pkg.sv" 1
// ALU control structure definition
package alu_pkg;
typedef struct packed {
// X lane
logic pre_x_en; // 0:x0, 1:add
logic pre_x_sub; // 0:add, 1:sub
logic mul_x_en; // 0:m0,m1, 1:mul
logic [2:0] mul_x_sel; // 0:x0, 1:x1, 2:... | module decode_stage_4b (
input logic clk, // System clock
input logic rst_n, // Active low reset
input logic rx_valid_in, // Valid instruction from RX stage
input logic cmd_ready_in, // ALU ready to accept new instruction (from ALU)
input logic [3:0] op, // Opcode from R... |
ttsky26a_0340 | ttsky26a | XeonicsCA-ECE298A-TT-MAU | task_mul5x5 | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "alu_pkg.sv" 1
// ALU control structure definition
package alu_pkg;
typedef struct packed {
// X lane
logic pre_x_en; // 0:x0, 1:add
logic pre_x_sub; // 0:add, 1:sub
logic mul_x_en; // 0:m0,m1, 1:mul
logic [2:0] mul_x_sel; // 0:x0, 1:x1, 2:... | module mul5x5 (
input logic en,
input logic [4:0] m0, m1, // 5 bit inputs
output logic [9:0] p // 10 bit outputs
);
always_comb begin
// if not enabled, pass through concat m0 and m1
if (!en) begin
p = {m0, m1};
end
// if enabled, output multiplication
else begin
p = m0 * m1;
end
end
en... |
ttsky26a_0341 | ttsky26a | XeonicsCA-ECE298A-TT-MAU | task_pre_add4 | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "alu_pkg.sv" 1
// ALU control structure definition
package alu_pkg;
typedef struct packed {
// X lane
logic pre_x_en; // 0:x0, 1:add
logic pre_x_sub; // 0:add, 1:sub
logic mul_x_en; // 0:m0,m1, 1:mul
logic [2:0] mul_x_sel; // 0:x0, 1:x1, 2:... | module pre_add4 (
input logic en,
input logic sub, // 0 to add, 1 to sub
input logic [3:0] in0, in1, // 4 bit inputs
output logic [4:0] out5 // 5 bit output (going to multiplier)
);
// concat in0 and in1 with 0 in MSB for 5 bit inputs
logic [4:0] a, b;
assign a = {1'b0, in0};
assign b = {1'b0, in1};... |
ttsky26a_0342 | ttsky26a | XeonicsCA-ECE298A-TT-MAU | task_rx_4b | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "alu_pkg.sv" 1
// ALU control structure definition
package alu_pkg;
typedef struct packed {
// X lane
logic pre_x_en; // 0:x0, 1:add
logic pre_x_sub; // 0:add, 1:sub
logic mul_x_en; // 0:m0,m1, 1:mul
logic [2:0] mul_x_sel; // 0:x0, 1:x1, 2:... | module rx_4b (
input logic clk, //System clock
input logic rst_n, //Active low reset
input logic spi_clk, //SPI clock
input logic spi_w, //SPI write enable
input logic [3:0] mosi, //4 bit MOSI data input
input logic alu_ready, //ALU ready to accept n... |
ttsky26a_0343 | ttsky26a | XeonicsCA-ECE298A-TT-MAU | task_tx_4b | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "alu_pkg.sv" 1
// ALU control structure definition
package alu_pkg;
typedef struct packed {
// X lane
logic pre_x_en; // 0:x0, 1:add
logic pre_x_sub; // 0:add, 1:sub
logic mul_x_en; // 0:m0,m1, 1:mul
logic [2:0] mul_x_sel; // 0:x0, 1:x1, 2:... | module tx_4b (
input logic clk, //System clock
input logic rst_n, //Active low reset
input logic spi_clk, //SPI clock
input logic spi_r, //SPI read enable
//ALU interface
input logic [9:0] res_data, //10 bit result from ALU
input logic carry_in, ... |
ttihp26a_0344 | ttihp26a | ZeduloAdmin-ttihp-timer | task_spi_byte_sm | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_ztimer_top.v" 1
`default_nettype none
module tt_um_ztimer_top (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, ... | module spi_byte_sm (
input wire clk_i,
input wire rst_ni,
input wire cio_sck_i,
input wire cio_csb_i,
input wire cio_sd_i, //mosi
output wire cio_sd_o, //miso
input wire [7:0] tx_data, // byte to send
output reg tx_load,
output reg [7:0] rx_data, // byte recieved
output ... |
ttihp26a_0345 | ttihp26a | ZeduloAdmin-ttihp-timer | task_spi_core | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_ztimer_top.v" 1
`default_nettype none
module tt_um_ztimer_top (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, ... | module spi_core (
input wire clk_i,
input wire rst_ni,
// interface to spi
input wire [7:0] rx_data,
input wire rx_valid,
output reg [7:0] tx_data,
input wire tx_load,
input wire cio_csb_syned,
// interface to counters
output reg [1:0] cnt_idx,
output reg ... |
ttsky26a_0346 | ttsky26a | Zufallsgenerat0r-tt-interference | task_hvsync_generator | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "project.v" 1
/*
* Copyright (c) 2026 Kilian
* SPDX-License-Identifier: Apache-2.0
*
* Wave Lattice — a dot-grid port of https://taylor.town/waves (Taylor Troesh,
* inspired by Zach Lieberman). Two interfering radial wave sources displace
* a 40x30 dot lattice on a 640x480 VGA signal. Source A follows a v... | module hvsync_generator(clk, clken, reset, hsync, vsync, display_on, hpos, vpos);
input clk;
input clken;
input reset;
output reg hsync, vsync;
output display_on;
output reg [9:0] hpos;
output reg [9:0] vpos;
parameter H_DISPLAY = 640;
parameter H_BACK = 48;
para... |
ttsky26b_0347 | ttsky26b | abhinavputhran-ttsky-verilog-raycaster | task_map | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_abhi_raycast.sv" 1
`default_nettype none
// ui_in[0] = btn_fwd
// ui_in[1] = btn_back
// ui_in[2] = btn_left
// ui_in[3] = btn_right
// ui_in[4] = btn_demo
// ui_in[6:5] = wall_color_sel 00=blue 01=red 10=green 11=white
// ui_in[7] = spare
//
// uo_out[0] = hsync_n
// uo_out[1] = vsync_n
// uo_out[3:... | module map (input logic [4:0] cell_x,
input logic [4:0] cell_y,
output logic is_wall);
logic [31:0] rows [0:31];
initial begin
rows[0] = 32'hFFFFFFFF;
rows[1] = 32'hA8B64899;
rows[2] = 32'h800DC215;
rows[3] = 32'h81900827;
rows[4] = 32'hC4104082;
rows[5] = 32'h85094... |
ttsky26b_0348 | ttsky26b | abhinavputhran-ttsky-verilog-raycaster | task_pov_ctrl | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_abhi_raycast.sv" 1
`default_nettype none
// ui_in[0] = btn_fwd
// ui_in[1] = btn_back
// ui_in[2] = btn_left
// ui_in[3] = btn_right
// ui_in[4] = btn_demo
// ui_in[6:5] = wall_color_sel 00=blue 01=red 10=green 11=white
// ui_in[7] = spare
//
// uo_out[0] = hsync_n
// uo_out[1] = vsync_n
// uo_out[3:... | module pov_ctrl (input logic clk,
input logic reset,
input logic vsync,
input logic btn_fwd,
input logic btn_back,
input logic btn_left,
input logic btn_right,
input logic btn_demo,
ou... |
ttsky26b_0349 | ttsky26b | abhinavputhran-ttsky-verilog-raycaster | task_recip | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_abhi_raycast.sv" 1
`default_nettype none
// ui_in[0] = btn_fwd
// ui_in[1] = btn_back
// ui_in[2] = btn_left
// ui_in[3] = btn_right
// ui_in[4] = btn_demo
// ui_in[6:5] = wall_color_sel 00=blue 01=red 10=green 11=white
// ui_in[7] = spare
//
// uo_out[0] = hsync_n
// uo_out[1] = vsync_n
// uo_out[3:... | module recip (input logic [15:0] i_data,
input logic i_abs,
output logic [15:0] o_data,
output logic o_sat);
localparam [15:0] NSAT = 16'hFFFF;
wire sign = i_data[15];
wire [15:0] unsigned_data = sign ? (~i_data + 16'd1) : i_data;
logic [3:0] lzc;
always_comb casez... |
ttsky26b_0350 | ttsky26b | abhinavputhran-ttsky-verilog-raycaster | task_recip_lut | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_abhi_raycast.sv" 1
`default_nettype none
// ui_in[0] = btn_fwd
// ui_in[1] = btn_back
// ui_in[2] = btn_left
// ui_in[3] = btn_right
// ui_in[4] = btn_demo
// ui_in[6:5] = wall_color_sel 00=blue 01=red 10=green 11=white
// ui_in[7] = spare
//
// uo_out[0] = hsync_n
// uo_out[1] = vsync_n
// uo_out[3:... | module recip_lut (
input logic [6:0] idx, // scale_data[9:3], valid range [64,127]
output logic [10:0] out // reciprocal in [1024,2047]
);
logic [10:0] rom [0:127];
initial begin
rom[64] = 11'd2032;
rom[65] = 11'd2001;
rom[66] = 11'd1971;
rom[67] = 11'd1942;
rom[68] = 11'd1913;
r... |
ttsky26b_0351 | ttsky26b | abhinavputhran-ttsky-verilog-raycaster | task_top_bare | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_abhi_raycast.sv" 1
`default_nettype none
// ui_in[0] = btn_fwd
// ui_in[1] = btn_back
// ui_in[2] = btn_left
// ui_in[3] = btn_right
// ui_in[4] = btn_demo
// ui_in[6:5] = wall_color_sel 00=blue 01=red 10=green 11=white
// ui_in[7] = spare
//
// uo_out[0] = hsync_n
// uo_out[1] = vsync_n
// uo_out[3:... | module top_bare (input logic clk,
input logic reset,
input logic btn_fwd,
input logic btn_back,
input logic btn_left,
input logic btn_right,
input logic btn_demo,
input logic [1:0] wall_color_sel, /... |
ttsky26a_0352 | ttsky26a | adityaamehra-FFT-tiny-tapeout | task_Butterfly | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "project.v" 1
/*
* Copyright (c) 2026 UGRA IIT(BHU)
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
`line 6 "project.v" 0
`line 1 "top.v" 1
module top #(parameter N = 64, parameter STAGES = 6)(
`line 2 "top.v" 0
input wire clk, reset_n, start,
input wire signed [7:0] x... | module Butterfly (
`line 2 "Butterfly.v" 0
input wire signed [7:0] x0_r, x0_i,
input wire signed [7:0] x1_r, x1_i,
input wire signed [7:0] w_r, w_i,
output wire signed [7:0] y0_r, y0_i,
output wire signed [7:0] y1_r, y1_i
);
wire signed [8:0] sum_r = {x0_r[7], x0_r} + {x... |
ttsky26b_0353 | ttsky26b | aelobo-ttsky-verilog-template | task_counter | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_aelobo.sv" 1
/*
* Copyright (c) 2024 Amelia Lobo
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_aelobo (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output... | module counter (
input clk,
input rst,
output reg [7:0] value
);
parameter SIZE = 4'h8;
parameter DIV = 1'h0;
parameter TOP = 1'h0;
parameter UP = 1'h1;
reg [7:0] M_ctr_d, M_ctr_q = 1'h0;
localparam MAX_VALUE = 1'h0;
always @* begin
M_ctr_d = M_ctr_q;
value = M_ctr_q[0+7-:8];
... |
ttsky26b_0354 | ttsky26b | aelobo-ttsky-verilog-template | task_day_counter | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_aelobo.sv" 1
/*
* Copyright (c) 2024 Amelia Lobo
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_aelobo (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output... | module day_counter (
input logic clk,
input logic rst_n,
input logic carry_in, // from hour_counter carry_out
input logic [4:0] max_days, // from rollover
input logic we,
input logic inc,
input logic dec,
output logic [4:0] day,
output l... |
ttsky26b_0355 | ttsky26b | aelobo-ttsky-verilog-template | task_hour_counter | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_aelobo.sv" 1
/*
* Copyright (c) 2024 Amelia Lobo
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_aelobo (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output... | module hour_counter (
input logic clk,
input logic rst_n,
input logic carry_in, // from min_counter carry_out
input logic we,
input logic inc,
input logic dec,
output logic [4:0] hour,
output logic carry_out
);
always_ff @(posedge clk ... |
ttsky26b_0356 | ttsky26b | aelobo-ttsky-verilog-template | task_main_mode_fsm | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_aelobo.sv" 1
/*
* Copyright (c) 2024 Amelia Lobo
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_aelobo (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output... | module main_mode_fsm (
input logic clk,
input logic rst_n,
input logic btn_mode, // cycle display mode
input logic btn_set, // enter / exit setup
output logic [1:0] display_mode, // 00=CLOCK 01=DATE 10=POMODORO
output logic in_setup, // any SETUP ... |
ttsky26b_0357 | ttsky26b | aelobo-ttsky-verilog-template | task_max7219 | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_aelobo.sv" 1
/*
* Copyright (c) 2024 Amelia Lobo
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_aelobo (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output... | module max7219 (
input clk,
input rst,
input [7:0] addr_in,
input [7:0] din,
input start,
output reg cs,
output reg dout,
output reg sck,
output reg busy
);
localparam IDLE_state = 2'd0;
localparam TRANSFER_ADDR_state = 2'd1;
localparam TRANSFER_DATA_state = 2'd2;
reg [... |
ttsky26b_0358 | ttsky26b | aelobo-ttsky-verilog-template | task_min_counter | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_aelobo.sv" 1
/*
* Copyright (c) 2024 Amelia Lobo
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_aelobo (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output... | module min_counter (
input logic clk,
input logic rst_n,
input logic carry_in, // from sec_counter carry_out
input logic we,
input logic inc,
input logic dec,
output logic [5:0] min,
output logic carry_out
);
always_ff @(posedge clk or... |
ttsky26b_0359 | ttsky26b | aelobo-ttsky-verilog-template | task_month_counter | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_aelobo.sv" 1
/*
* Copyright (c) 2024 Amelia Lobo
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_aelobo (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output... | module month_counter (
input logic clk,
input logic rst_n,
input logic carry_in, // from day_counter carry_out
input logic we,
input logic inc,
input logic dec,
output logic [3:0] month
);
always_ff @(posedge clk or negedge rst_n) begin
... |
ttsky26b_0360 | ttsky26b | aelobo-ttsky-verilog-template | task_rollover | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_aelobo.sv" 1
/*
* Copyright (c) 2024 Amelia Lobo
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_aelobo (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output... | module rollover (
input logic [3:0] month, // 1–12
input logic leap_year, // 1 = current year is a leap year
output logic [4:0] max_days // 28–31
);
always_comb begin
case (month)
4'd1: max_days = 5'd31; // january
4'd2: max_days = leap_yea... |
ttsky26b_0361 | ttsky26b | aelobo-ttsky-verilog-template | task_sec_counter | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_aelobo.sv" 1
/*
* Copyright (c) 2024 Amelia Lobo
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_aelobo (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output... | module sec_counter (
input logic clk,
input logic rst_n,
input logic tick_1hz, // 1 Hz tick
input logic we, // write enable from setup FSM
input logic inc, // increment selected field
input logic dec, // decrement selected field
o... |
ttsky26b_0362 | ttsky26b | aelobo-ttsky-verilog-template | task_setup_field_fsm | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_aelobo.sv" 1
/*
* Copyright (c) 2024 Amelia Lobo
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_aelobo (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output... | module setup_field_fsm (
input logic clk,
input logic rst_n,
input logic in_setup,
input logic setup_is_date,
input logic btn_set, // advance to next field
input logic btn_up, // increment current field
input logic btn... |
ttsky26b_0363 | ttsky26b | aelobo-ttsky-verilog-template | task_spi_master | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_aelobo.sv" 1
/*
* Copyright (c) 2024 Amelia Lobo
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_aelobo (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output... | module spi_master (
input clk,
input rst,
input miso,
output reg mosi,
output reg sck,
input start,
input [7:0] data_in,
output reg [7:0] data_out,
output reg new_data,
output reg busy
);
localparam CLK_DIV = 4'h8;
localparam CPOL = 1'h0;
localparam CPHA = 1'h0;
loca... |
ttgf26b_0364 | ttgf26b | aidenkoch4-ece430-tt-GF26A | task_rgb_pwm_core | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_aidenkoch4.v" 1
/*
* Copyright (c) 2024 Aiden Koch
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_aidenkoch4 (
input wire [7:0] ui_in,
output wire [7:0] uo_out,
input wire [7:0] uio_in,
output wire [7:0] uio_out,
output wire [7:0] uio_oe,
inpu... | module rgb_pwm_core (
input wire clk,
input wire rst_n,
input wire [1:0] mode,
input wire [5:0] value,
output wire pwm_r,
output wire pwm_g,
output wire pwm_b
);
reg [5:0] duty_r;
reg [5:0] duty_g;
reg [5:0] duty_b;
reg [5:0] clk_div;
... |
ttsky26a_0365 | ttsky26a | alexanderholden-tinytapeoutalexander | task_accumulator | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_sap_alexanderholden.v" 1
module tt_um_sap_alexanderholden(
input wire clk,
input wire rst_n,
input wire [7:0] ui_in,
output wire [7:0] uo_out,
input wire [7:0] uio_in,
output wire [7:0] uio_out,
output wire [7:0] uio_oe,
input wire ena
);
wire Cp;
wire Ep;
w... | module accumulator( // WORKING
input wire LA, // active high load into accumulator
input wire CLK, // active high clock
input wire EA, // active high enable output to bus
input wire [7:0] acc_bus_in, // input bus
output wire [7:0] acc_bus_out, // outp... |
ttsky26a_0366 | ttsky26a | alexanderholden-tinytapeoutalexander | task_add_sub | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_sap_alexanderholden.v" 1
module tt_um_sap_alexanderholden(
input wire clk,
input wire rst_n,
input wire [7:0] ui_in,
output wire [7:0] uo_out,
input wire [7:0] uio_in,
output wire [7:0] uio_out,
output wire [7:0] uio_oe,
input wire ena
);
wire Cp;
wire Ep;
w... | module add_sub(
input wire [7:0] A, // accumulator input
input wire [7:0] B, // B register input
input wire SU, // 0 = add, 1 = sub
input wire EU, // enable output to bus
output wire [7:0] ADD_SUB_bus_out
);
reg [7:0] result;
al... |
ttsky26a_0367 | ttsky26a | alexanderholden-tinytapeoutalexander | task_b_register | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_sap_alexanderholden.v" 1
module tt_um_sap_alexanderholden(
input wire clk,
input wire rst_n,
input wire [7:0] ui_in,
output wire [7:0] uo_out,
input wire [7:0] uio_in,
output wire [7:0] uio_out,
output wire [7:0] uio_oe,
input wire ena
);
wire Cp;
wire Ep;
w... | module b_register(
input wire LB, // load enable
input wire CLK, // clock
input wire [7:0] b_bus_in, // input bus
output wire [7:0] b_add_sum_in, // output to add/sub module
input wire rst_n
);
reg [7:0] b_reg = 8'b0;
// Load process
always @(... |
ttsky26a_0368 | ttsky26a | alexanderholden-tinytapeoutalexander | task_controller | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_sap_alexanderholden.v" 1
module tt_um_sap_alexanderholden(
input wire clk,
input wire rst_n,
input wire [7:0] ui_in,
output wire [7:0] uo_out,
input wire [7:0] uio_in,
output wire [7:0] uio_out,
output wire [7:0] uio_oe,
input wire ena
);
wire Cp;
wire Ep;
w... | module controller(
input wire clk,
input wire rst_n,
input wire [3:0] inst_in,
output reg Cp,
output reg Ep,
output reg Lm,
output reg CE,
output reg Li,
output reg Ei,
output reg La,
output reg Ea,
output reg Su,
output reg Eu,
output reg Lb,
... |
ttsky26a_0369 | ttsky26a | alexanderholden-tinytapeoutalexander | task_instruction_register | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_sap_alexanderholden.v" 1
module tt_um_sap_alexanderholden(
input wire clk,
input wire rst_n,
input wire [7:0] ui_in,
output wire [7:0] uo_out,
input wire [7:0] uio_in,
output wire [7:0] uio_out,
output wire [7:0] uio_oe,
input wire ena
);
wire Cp;
wire Ep;
w... | module instruction_register(
input wire LI, // load instruction
input wire CLK, // clock
input wire rst_n, // active low clear
input wire EI, // enable output
input wire [7:0] ir_bus_in, // input bus
output wire [3:0] ir... |
ttsky26a_0370 | ttsky26a | alexanderholden-tinytapeoutalexander | task_mar | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_sap_alexanderholden.v" 1
module tt_um_sap_alexanderholden(
input wire clk,
input wire rst_n,
input wire [7:0] ui_in,
output wire [7:0] uo_out,
input wire [7:0] uio_in,
output wire [7:0] uio_out,
output wire [7:0] uio_oe,
input wire ena
);
wire Cp;
wire Ep;
w... | module mar(
input wire LM, // active high load from bus
input wire CLK, // clock
input wire [3:0] bus_in, // 4-bit input bus
output wire [3:0] mar_addr_bus_out, // 4-bit address output
input wire rst_n
);
reg [3:0] mar_reg = 4'b0;
// Loa... |
ttsky26a_0371 | ttsky26a | alexanderholden-tinytapeoutalexander | task_mem | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_sap_alexanderholden.v" 1
module tt_um_sap_alexanderholden(
input wire clk,
input wire rst_n,
input wire [7:0] ui_in,
output wire [7:0] uo_out,
input wire [7:0] uio_in,
output wire [7:0] uio_out,
output wire [7:0] uio_oe,
input wire ena
);
wire Cp;
wire Ep;
w... | module mem(
input wire [3:0] mar_addr,
input wire CE,
output wire [7:0] ram_bus_out
);
reg [7:0] ram [0:15];
initial begin
// preload instructions and data
ram[0] = 8'b00001001; // LDA @9
ram[1] = 8'b00011100; // ADD @A
ram[2] = 8'b11101111; // OUT
ram[3... |
ttsky26a_0372 | ttsky26a | alexanderholden-tinytapeoutalexander | task_mux | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_sap_alexanderholden.v" 1
module tt_um_sap_alexanderholden(
input wire clk,
input wire rst_n,
input wire [7:0] ui_in,
output wire [7:0] uo_out,
input wire [7:0] uio_in,
output wire [7:0] uio_out,
output wire [7:0] uio_oe,
input wire ena
);
wire Cp;
wire Ep;
w... | module mux(
input wire [7:0] pc_bus_out,
input wire [7:0] acc_bus_out,
input wire [7:0] ADD_SUB_bus_out,
input wire [7:0] ram_bus_out,
input wire [7:0] ir_addr_out, // zero-extended outside if needed
input wire EP, // PC
input wire CE, // RAM
input wire EI, // IR
input ... |
ttsky26a_0373 | ttsky26a | alexanderholden-tinytapeoutalexander | task_outregister | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_sap_alexanderholden.v" 1
module tt_um_sap_alexanderholden(
input wire clk,
input wire rst_n,
input wire [7:0] ui_in,
output wire [7:0] uo_out,
input wire [7:0] uio_in,
output wire [7:0] uio_out,
output wire [7:0] uio_oe,
input wire ena
);
wire Cp;
wire Ep;
w... | module outregister(
input wire LO, // load enable
input wire CLK, // clock
input wire [7:0] out_bus_in, // input bus
output wire [7:0] out_reg_bus_out, // output bus
input wire rst_n
);
reg [7:0] out_reg = 8'b0;
// Load process
always @(pos... |
ttsky26a_0374 | ttsky26a | alexanderholden-tinytapeoutalexander | task_programcounter | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_sap_alexanderholden.v" 1
module tt_um_sap_alexanderholden(
input wire clk,
input wire rst_n,
input wire [7:0] ui_in,
output wire [7:0] uo_out,
input wire [7:0] uio_in,
output wire [7:0] uio_out,
output wire [7:0] uio_oe,
input wire ena
);
wire Cp;
wire Ep;
w... | module programcounter(
input wire C_P, // increment enable
input wire nCLK, // active-low clock
input wire rst_n, // active-low clear
input wire E_P, // enable output to bus
input wire [3:0] pc_bus_in, // input bus (optional for top-level)... |
ttsky26a_0375 | ttsky26a | altcar-ttsky-sesh | task_atan_lut | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "fsm_control.v" 1
module control_fsm (
input wire clk,
input wire rst_n,
input wire spi_ready, // From spi_controller
input wire clear_in, // Manual clear input (from uio_in[3])
output reg mac_en,
output reg acc_clr,
output reg done_pulse
);
typedef enum reg [2:0] {IDL... | module atan_lut (
input wire [3:0] step,
input wire is_hyperbolic,
output reg [11:0] lut_value
);
always @(*) begin
if (is_hyperbolic) begin
case (step)
4'd1: lut_value = 12'h232;
4'd2: lut_value = 12'h106;
4'd3: lut_value = 12'h081;... |
ttsky26a_0376 | ttsky26a | altcar-ttsky-sesh | task_control_fsm | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "fsm_control.v" 1
module control_fsm (
input wire clk,
input wire rst_n,
input wire spi_ready, // From spi_controller
input wire clear_in, // Manual clear input (from uio_in[3])
output reg mac_en,
output reg acc_clr,
output reg done_pulse
);
// >>> Module Implementation Be... | module control_fsm (
input wire clk,
input wire rst_n,
input wire spi_ready, // From spi_controller
input wire clear_in, // Manual clear input (from uio_in[3])
output reg mac_en,
output reg acc_clr,
output reg done_pulse
);
typedef enum reg [2:0] {IDLE, START, BUSY, WAIT_SPI, ... |
ttsky26a_0377 | ttsky26a | altcar-ttsky-sesh | task_cordic_core | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "fsm_control.v" 1
module control_fsm (
input wire clk,
input wire rst_n,
input wire spi_ready, // From spi_controller
input wire clear_in, // Manual clear input (from uio_in[3])
output reg mac_en,
output reg acc_clr,
output reg done_pulse
);
typedef enum reg [2:0] {IDL... | module cordic_core (
input wire clk,
input wire rst_n,
input wire [1:0] mode, // uio_in[7:6]
input wire [7:0] theta_in, // From ui_in
output reg [15:0] x_out, // COS / COSH
output reg [15:0] y_out, // SIN / SINH
output reg [15:0] z_out, // ATAN / ATANH
output reg do... |
ttsky26a_0378 | ttsky26a | altcar-ttsky-sesh | task_npu_core | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "fsm_control.v" 1
module control_fsm (
input wire clk,
input wire rst_n,
input wire spi_ready, // From spi_controller
input wire clear_in, // Manual clear input (from uio_in[3])
output reg mac_en,
output reg acc_clr,
output reg done_pulse
);
typedef enum reg [2:0] {IDL... | module npu_core (
input wire clk,
input wire reset, // System reset (active high)
input wire clear, // User-triggered reset
input wire [7:0] input_data, // data from pin
input wire [7:0] weight_data, // weight from SPI
input wire enable, // Start MAC operation pulse
output w... |
ttsky26a_0379 | ttsky26a | altcar-ttsky-sesh | task_spi_receiver | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "fsm_control.v" 1
module control_fsm (
input wire clk,
input wire rst_n,
input wire spi_ready, // From spi_controller
input wire clear_in, // Manual clear input (from uio_in[3])
output reg mac_en,
output reg acc_clr,
output reg done_pulse
);
typedef enum reg [2:0] {IDL... | module spi_receiver (
input wire clk, // System clock
input wire rst_n, // Reset, active low
input wire sclk, // SPI clock from external source
input wire mosi, // Data bit
input wire cs, // Chip Select Active low
output reg [7:0] weight, // The full byt... |
ttsky26b_0380 | ttsky26b | amc1635-ttsky-verilog-bootcamp | task_ACC | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "project.v" 1
/*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_processor_top (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output ... | module ACC(
input clk,
input reset,
input load,
input [7:0] data_in,
output reg [7:0] data_out
);
always @(posedge clk) begin
if (reset)
data_out <= 8'b00000000;
else if (load)
data_out <= data_in;
else
data_out <= data_out;
end
endmodule |
ttsky26b_0381 | ttsky26b | amc1635-ttsky-verilog-bootcamp | task_Integrated_ALU_8 | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "project.v" 1
/*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_processor_top (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output ... | module Integrated_ALU_8 (
input wire clk,
input wire reset,
input wire [7:0] A, // Accumulator input
input wire [7:0] B, // Operand input
input wire [3:0] alu_op, // Opcode input
output reg [7:0] result,
output reg update_acc,
output reg fl... |
ttsky26b_0382 | ttsky26b | amc1635-ttsky-verilog-bootcamp | task_ex_decoder | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "project.v" 1
/*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_processor_top (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output ... | module ex_decoder (
input wire [11:0] instr_in,
output wire [3:0] opcode,
output wire [7:0] operand
);
// Physically split the incoming bus
assign opcode = instr_in[11:8];
assign operand = instr_in[7:0];
endmodule |
ttsky26b_0383 | ttsky26b | amc1635-ttsky-verilog-bootcamp | task_ex_memory | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "project.v" 1
/*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_processor_top (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output ... | module ex_memory (
input wire clk,
input wire rst,
input wire [3:0] opcode,
input wire [7:0] alu_result,
input wire alu_update_acc,
output reg [7:0] accumulator,
output reg [7:0] scratchpad
);
localparam STORE = 4'b1110; // Opcode 14
localparam LOAD_MEM = 4'b111... |
ttsky26b_0384 | ttsky26b | amc1635-ttsky-verilog-bootcamp | task_ex_stage_top | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "project.v" 1
/*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_processor_top (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output ... | module ex_stage_top (
input wire clk,
input wire rst,
input wire [11:0] instr_in,
output wire [7:0] out_pins,
// We also expose the flags to the top level just in case
// you want to map them to external LEDs later!
output wire status_Z,
output wire ... |
ttsky26b_0385 | ttsky26b | amc1635-ttsky-verilog-bootcamp | task_instr_mem | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "project.v" 1
/*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_processor_top (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output ... | module instr_mem (
input wire clk,
input wire rst,
input wire [11:0] instr_in,
input wire done,
input wire [2:0] rd_addr,
input wire re,
output wire [11:0] instr_out,
output reg [2:0] wr_addr
);
reg [11:0] mem [0:7];
reg done_d;
// Declare iterator for... |
ttsky26b_0386 | ttsky26b | amc1635-ttsky-verilog-bootcamp | task_instruction_register | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "project.v" 1
/*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_processor_top (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output ... | module instruction_register (
input clk,
input reset,
input [11:0] Instruction,
output reg [11:0] instr_out);
always @(posedge clk ) begin
if (reset)
instr_out <= 12'd0;
else
instr_out <= Instruction;end
endmodule |
ttsky26b_0387 | ttsky26b | amc1635-ttsky-verilog-bootcamp | task_pc | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "project.v" 1
/*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_processor_top (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output ... | module pc (
input wire reset,
input wire clk,
input wire re, // The "Pause Button" (Read Enable)
output reg [2:0] rd_addr
);
always @(posedge clk) begin
if (reset)
rd_addr <= 3'b000;
else if (re) // ONLY count up if Read Enable is HIGH
rd_... |
ttsky26b_0388 | ttsky26b | amc1635-ttsky-verilog-bootcamp | task_pipeline_register | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "project.v" 1
/*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_processor_top (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output ... | module pipeline_register(
input clk,reset,
input [11:0]instr_in,
output reg[11:0] instr_out );
always@(posedge clk)
begin
if(reset)
instr_out<=12'b0;
else
instr_out<=instr_in;
end
endmodule |
ttsky26b_0389 | ttsky26b | amc1635-ttsky-verilog-bootcamp | task_sipo | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "project.v" 1
/*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_processor_top (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output ... | module sipo(
input wire clk,
input wire rst,
input wire in0,
input wire in1,
input wire in2,
input wire mod,
input wire data_valid, // NEW: The Handshake clock from the Arduino
output reg [11:0] out,
output reg done
);
// --- The 2-Stage Synchronizer & Edge Detector ---
... |
ttsky26b_0390 | ttsky26b | amc1635-ttsky-verilog-bootcamp | task_top_cpu | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "project.v" 1
/*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_processor_top (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output ... | module top_cpu(
input clk,
input rst, mod,
input in0, in1, in2,
input data_valid, // <-- ADDED: Must expose the handshake pin!
input re,
output reg [11:0] instr_out
);
wire [11:0] sipo_out;
wire done;
wire [11:0] mem_out;
wire [2:0] rd_addr;
wire [2:0] wr_addr;
wire [11:0] pipe_out;
wire [1... |
ttihp26a_0391 | ttihp26a | apedersen00-tt6581 | task_controller | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt6581.sv" 1
//-------------------------------------------------------------------------------------------------
//
// File: tt6581.sv
// Description: Top module for the TT6581.
//
// Author:
// - Andreas Pedersen
//
//--------------------------------------------------------------------------------------... | module controller (
input logic clk_i, // 50 MHz
input logic rst_ni, // Active low reset
input logic sample_tick_i, // 50 kHz tick
// Register file
input logic [23:0] freq_lo_i,
input logic [23:0] freq_hi_i,
input log... |
ttihp26a_0392 | ttihp26a | apedersen00-tt6581 | task_delta_sigma | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt6581.sv" 1
//-------------------------------------------------------------------------------------------------
//
// File: tt6581.sv
// Description: Top module for the TT6581.
//
// Author:
// - Andreas Pedersen
//
//--------------------------------------------------------------------------------------... | module delta_sigma (
input logic clk_i, // 50 MHz
input logic rst_ni,
input logic audio_valid_i,
input logic signed [13:0] audio_i,
output wave_o
);
/************************************
* Counter for CLK division (1... |
ttihp26a_0393 | ttihp26a | apedersen00-tt6581 | task_envelope | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt6581.sv" 1
//-------------------------------------------------------------------------------------------------
//
// File: tt6581.sv
// Description: Top module for the TT6581.
//
// Author:
// - Andreas Pedersen
//
//--------------------------------------------------------------------------------------... | module envelope (
input logic clk_i,
input logic rst_ni,
input logic start_i, // Start processing voice_idx_i
input logic [1:0] voice_idx_i, // Active voice [0-2]
input logic gate_i, // Gate control
input logic [3:0] attack_i,
input logic [3:0] decay_i,
... |
ttihp26a_0394 | ttihp26a | apedersen00-tt6581 | task_mult | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt6581.sv" 1
//-------------------------------------------------------------------------------------------------
//
// File: tt6581.sv
// Description: Top module for the TT6581.
//
// Author:
// - Andreas Pedersen
//
//--------------------------------------------------------------------------------------... | module mult (
input logic clk_i,
input logic rst_ni,
input logic start_i,
input logic signed [23:0] op_a_i, // Operand A (24 bit)
input logic signed [15:0] op_b_i, // Operand B (16 bit)
output logic ready_o,
output logic... |
ttihp26a_0395 | ttihp26a | apedersen00-tt6581 | task_multi_voice | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt6581.sv" 1
//-------------------------------------------------------------------------------------------------
//
// File: tt6581.sv
// Description: Top module for the TT6581.
//
// Author:
// - Andreas Pedersen
//
//--------------------------------------------------------------------------------------... | module multi_voice (
input logic clk_i, // 50 MHz
input logic rst_ni, // Active low reset
input logic start_i, // Start generating voice
input logic [1:0] act_voice_i, // Active voice 0..2
input logic [15:0] freq_word_i, // Frequency control word
inpu... |
ttihp26a_0396 | ttihp26a | apedersen00-tt6581 | task_reg_file | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt6581.sv" 1
//-------------------------------------------------------------------------------------------------
//
// File: tt6581.sv
// Description: Top module for the TT6581.
//
// Author:
// - Andreas Pedersen
//
//--------------------------------------------------------------------------------------... | module reg_file (
input logic clk_i,
input logic rst_ni,
input logic [6:0] addr_i,
input logic [7:0] wdata_i,
input logic we_i,
output logic [7:0] rdata_o,
// Group: VOICE (Array x3)
output logic [23:0] voice_freq_lo_o,
output logic [23:0] voice_freq_hi_... |
ttihp26a_0397 | ttihp26a | apedersen00-tt6581 | task_spi | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt6581.sv" 1
//-------------------------------------------------------------------------------------------------
//
// File: tt6581.sv
// Description: Top module for the TT6581.
//
// Author:
// - Andreas Pedersen
//
//--------------------------------------------------------------------------------------... | module spi (
input logic clk_i, // System clock (50 MHz)
input logic rst_ni, // Active low reset
input logic sclk_i, // SPI Clock
input logic cs_i, // SPI Chip select
input logic mosi_i, // SPI MOSI
output logic miso_o, // SPI MISO
... |
ttihp26a_0398 | ttihp26a | apedersen00-tt6581 | task_svf | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt6581.sv" 1
//-------------------------------------------------------------------------------------------------
//
// File: tt6581.sv
// Description: Top module for the TT6581.
//
// Author:
// - Andreas Pedersen
//
//--------------------------------------------------------------------------------------... | module svf (
input logic clk_i,
input logic rst_ni,
input logic start_i,
input logic [2:0] filt_sel_i, // Filter select
input logic signed [13:0] wave_i, // Unsigned voice mix
input logic signed [15:0] coeff_f_i, // Q1.15 frequency coe... |
ttihp26a_0399 | ttihp26a | apedersen00-tt6581 | task_tick_gen | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt6581.sv" 1
//-------------------------------------------------------------------------------------------------
//
// File: tt6581.sv
// Description: Top module for the TT6581.
//
// Author:
// - Andreas Pedersen
//
//--------------------------------------------------------------------------------------... | module tick_gen (
input logic clk_i,
input logic rst_ni,
output logic tick_o
);
logic [9:0] cnt;
always_ff @(posedge clk_i or negedge rst_ni) begin
if (!rst_ni) begin
cnt <= 0;
tick_o <= 0;
end else begin
if (cnt == 10'd999) begin
cnt <= 0;
tick_o <= 1'b1;
... |
ttihp26a_0400 | ttihp26a | apedersen00-tt6581 | task_tt6581 | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt6581.sv" 1
//-------------------------------------------------------------------------------------------------
//
// File: tt6581.sv
// Description: Top module for the TT6581.
//
// Author:
// - Andreas Pedersen
//
//--------------------------------------------------------------------------------------... | module tt6581 (
input logic clk_i, // System clock (50 MHz)
input logic rst_ni, // Active low reset
input logic sclk_i, // SPI Clock
input logic cs_i, // SPI Chip select
input logic mosi_i, // SPI MOSI
output logic miso_o, // SPI MISO... |
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