task_id string | shuttle_name string | project_name string | task_name string | system_message string | prompt string | golden_module string |
|---|---|---|---|---|---|---|
ttihp26a_0201 | ttihp26a | Nampuk-tapatapatapa | task_alu_ext | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_nampukk_top.v" 1
/*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_nampukk_top (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
... | module alu_ext (
input wire [2:0] ctl,
input wire increment,
input [7:0] a_lo,
input [7:0] a_hi,
input [7:0] b_lo,
input [7:0] b_hi,
output [7:0] res_lo,
output [7:0] res_hi,
output wire [3:0] flags
);
localparam CF = 2'd3;
wire [7:0] alu_res;
wire [3:0] alu_flags;
wire alu_carry = alu_flags[CF];
alu #(.... |
ttihp26a_0202 | ttihp26a | Nampuk-tapatapatapa | task_idecoder | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_nampukk_top.v" 1
/*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_nampukk_top (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
... | module idecoder (
input wire [15:0] instruction,
output wire [1:0] mode_outer,
output wire [1:0] mode_inner,
output wire [2:0] ctl_alu,
output wire ctl_carry,
output wire [1:0] dst,
output wire [1:0] src_1,
output wire [1:0] src_2,
output wire [7:0] word,
output wire [3:0] flag_mask
);
assign mode_outer =... |
ttihp26a_0203 | ttihp26a | Nampuk-tapatapatapa | task_memio | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_nampukk_top.v" 1
/*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_nampukk_top (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
... | module memio (
input clk,
input rst_n,
// External SPI interface
input spi_miso,
output spi_select,
output spi_clk_out,
output spi_mosi,
///
input [15:0] addr_in,
input [7:0] data_in,
input is_write,
input start,
output [7:0] data_out,
output busy
);
spi_ram_control... |
ttihp26a_0204 | ttihp26a | Nampuk-tapatapatapa | task_processor | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_nampukk_top.v" 1
/*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_nampukk_top (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
... | module processor (
input clk, // clock
input rst_n, // reset_n - low to reset
// memory interface
output [15:0] mem_addr, //
output [7:0] mem_data_in, //
output mem_is_write,//
output mem_start, //
input [7:0] mem_data_out,//
input mem_busy, //
/... |
ttsky26b_0205 | ttsky26b | Nay0805-CursoTinyP1 | task_CDN_flop | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "project.v" 1
/*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype wire
module tt_um_Nay0805_detector_de_patrones_generados_aleatoreamente (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio... | module CDN_flop(clk, d, sena, aclr, apre, srl, srd, q);
input clk, d, sena, aclr, apre, srl, srd;
output q;
wire clk, d, sena, aclr, apre, srl, srd;
wire q;
reg qi;
assign #1 q = qi;
always
@(posedge clk or posedge apre or posedge aclr)
if (aclr)
qi <= 0;
else if (apre)
... |
ttsky26b_0206 | ttsky26b | Nay0805-CursoTinyP1 | task_Comparador | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "project.v" 1
/*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype wire
module tt_um_Nay0805_detector_de_patrones_generados_aleatoreamente (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio... | module Comparador (
input wire [3:0] bit_REGISTRO, // 4 bits desde registro UART
input wire [3:0] bit_LFSR, // 4 bits desde registro LFSR
output wire igual // 1 si los 4 bits son iguales
);
assign igual = (bit_REGISTRO == bit_LFSR);
endmodule |
ttsky26b_0207 | ttsky26b | Nay0805-CursoTinyP1 | task_FSM_DETECTOR | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "project.v" 1
/*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype wire
module tt_um_Nay0805_detector_de_patrones_generados_aleatoreamente (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio... | module FSM_DETECTOR (
// Entradas
input wire clk,
input wire rst, // reset sincrono, ACTIVO-BAJO
input wire Pulso, // indica que los registros estan listos para comparar
input wire Igual_alto, // resultado comparador bits [7:4] del LFSR vs UART
input wire Igual_bajo, // resultado compar... |
ttsky26b_0208 | ttsky26b | Nay0805-CursoTinyP1 | task_Top_Detector_de_patrones | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "project.v" 1
/*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype wire
module tt_um_Nay0805_detector_de_patrones_generados_aleatoreamente (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio... | module Top_Detector_de_patrones (
input wire clk,
input wire rst,
input wire [7:0] bit_REGISTRO, // viene de ui_in
input wire [7:0] bit_LFSR, // viene de uio_in
input wire pulso, // o lo generás internamente
output wire [3:0] leds
);
wire igual_alto;
wire igual_b... |
ttsky26b_0209 | ttsky26b | Nay0805-CursoTinyP1 | task_UART | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "project.v" 1
/*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype wire
module tt_um_Nay0805_detector_de_patrones_generados_aleatoreamente (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio... | module UART(clk, reset, tx_start, tx_rdy, rx_data_rdy, data_in,
data_out, rx, tx);
input clk, reset, tx_start, rx;
input [7:0] data_in;
output tx_rdy, rx_data_rdy, tx;
output [7:0] data_out;
wire clk, reset, tx_start, rx;
wire [7:0] data_in;
wire tx_rdy, rx_data_rdy, tx;
wire [7:0] data_out;
UART... |
ttsky26b_0210 | ttsky26b | Nay0805-CursoTinyP1 | task_UART_rx | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "project.v" 1
/*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype wire
module tt_um_Nay0805_detector_de_patrones_generados_aleatoreamente (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio... | module UART_rx(clk, reset, rx_data_in, rx_data_rdy, rx_data_out);
input clk, reset, rx_data_in;
output rx_data_rdy;
output [7:0] rx_data_out;
wire clk, reset, rx_data_in;
wire rx_data_rdy;
wire [7:0] rx_data_out;
wire [3:0] baud_x16_count;
wire [2:0] bit_count;
wire [3:0] bit_duration_count;
wire [1... |
ttsky26b_0211 | ttsky26b | Nay0805-CursoTinyP1 | task_UART_tx | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "project.v" 1
/*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype wire
module tt_um_Nay0805_detector_de_patrones_generados_aleatoreamente (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio... | module UART_tx(clk, reset, tx_start, tx_rdy, tx_data_in, tx_data_out);
input clk, reset, tx_start;
input [7:0] tx_data_in;
output tx_rdy, tx_data_out;
wire clk, reset, tx_start;
wire [7:0] tx_data_in;
wire tx_rdy, tx_data_out;
wire [7:0] baud_count;
wire [2:0] data_index;
wire [1:0] tx_state;
wire [... |
ttsky26b_0212 | ttsky26b | Nay0805-CursoTinyP1 | task_reg_pp_8b_en_ar | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "project.v" 1
/*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype wire
module tt_um_Nay0805_detector_de_patrones_generados_aleatoreamente (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio... | module reg_pp_8b_en_ar(
input logic clk_i,
input logic rst_n_i,
input logic [7:0] d_i,
input logic en_i,
output logic [7:0] q_o
);
always_ff @(posedge clk_i or negedge rst_n_i) begin
if (!rst_n_i) begin
q_o <= 8'b0000_0000;
end
else if (en_i) begin
q_o <= ... |
ttsky26b_0213 | ttsky26b | Nay0805-CursoTinyP1 | task_register_8bit | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "project.v" 1
/*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype wire
module tt_um_Nay0805_detector_de_patrones_generados_aleatoreamente (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio... | module register_8bit (
input clk_i,
input reset_n_i, // Reset activo en bajo
input load_i, // Habilita almacenamiento
input [7:0] data_i,
output [7:0] data_o
);
reg [7:0] reg_data;
always @(posedge clk_i or negedge reset_n_i) begin
if (!reset_n_i) ... |
ttsky26b_0214 | ttsky26b | Nay0805-CursoTinyP1 | task_top_uart_lfsr_detector | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "project.v" 1
/*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype wire
module tt_um_Nay0805_detector_de_patrones_generados_aleatoreamente (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio... | module top_uart_lfsr_detector (
input wire clk,
input wire rst, // Reset activo en alto
input wire rx, // Entrada UART desde consola
input wire pulso, // Pulso para avanzar el LFSR/FSM
output wire tx, // Salida UART
output wire [3:0] leds... |
ttihp26a_0215 | ttihp26a | Neuromurf-ttihp26a-inferenceFCNN-16h3 | task_argmax_unit | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_neuromurf_seq_mac_inf.v" 1
`default_nettype none
`timescale 1ns/1ps
//==============================================================================
module tt_um_neuromurf_seq_mac_inf (
//==========================================================================
// TinyTapeout Standard Interfac... | module argmax_unit (
//==========================================================================
// Clock and Reset
//==========================================================================
input wire clk, // System clock (50 MHz)
input wire rst_n, // Async active... |
ttihp26a_0216 | ttihp26a | Neuromurf-ttihp26a-inferenceFCNN-16h3 | task_hidden_reg_bank | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_neuromurf_seq_mac_inf.v" 1
`default_nettype none
`timescale 1ns/1ps
//==============================================================================
module tt_um_neuromurf_seq_mac_inf (
//==========================================================================
// TinyTapeout Standard Interfac... | module hidden_reg_bank (
//==========================================================================
// Clock and Reset
//==========================================================================
input wire clk, // System clock (50 MHz)
input wire rst_n, // Async ac... |
ttihp26a_0217 | ttihp26a | Neuromurf-ttihp26a-inferenceFCNN-16h3 | task_seq_mac_datapath | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_neuromurf_seq_mac_inf.v" 1
`default_nettype none
`timescale 1ns/1ps
//==============================================================================
module tt_um_neuromurf_seq_mac_inf (
//==========================================================================
// TinyTapeout Standard Interfac... | module seq_mac_datapath (
//==========================================================================
// Clock and Reset
//==========================================================================
input wire clk, // System clock (50 MHz)
input wire rst_n, // Async... |
ttihp26a_0218 | ttihp26a | Neuromurf-ttihp26a-inferenceFCNN-16h3 | task_seq_mac_inf_fsm | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_neuromurf_seq_mac_inf.v" 1
`default_nettype none
`timescale 1ns/1ps
//==============================================================================
module tt_um_neuromurf_seq_mac_inf (
//==========================================================================
// TinyTapeout Standard Interfac... | module seq_mac_inf_fsm (
//==========================================================================
// Clock and Reset
//==========================================================================
input wire clk, // System clock (50 MHz)
input wire rst_n, // Async ... |
ttihp26a_0219 | ttihp26a | Neuromurf-ttihp26a-inferenceFCNN-16h3 | task_seq_mac_inf_top | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_neuromurf_seq_mac_inf.v" 1
`default_nettype none
`timescale 1ns/1ps
//==============================================================================
module tt_um_neuromurf_seq_mac_inf (
//==========================================================================
// TinyTapeout Standard Interfac... | module seq_mac_inf_top (
//==========================================================================
// Clock and Reset
//==========================================================================
input wire clk, // System clock (50 MHz)
input wire rst_n, // Async ... |
ttgf0p3_0220 | ttgf0p3 | ODGrip-ttgf-polywave | task_polywave_top_analog_stub | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "project.v" 1
/*
* Copyright (c) 2026 Riccardo Pellegrini
* SPDX-License-Identifier: Apache-2.0
*
* Quad 16-bit R2R performance engine for a 328.72um x 206um TT GF180 pgvaa slot.
*
* The engine is intentionally area-aware: four phase accumulators, shared noise,
* cross-modulated timing, sequencer offsets... | module polywave_top_analog_stub (
input wire VGND,
input wire VDPWR,
input wire VAPWR,
input wire [15:0] R2R_Bn_0,
input wire [15:0] R2R_Bn_1,
input wire [15:0] R2R_Bn_2,
input wire [15:0] R2R_Bn_3,
inout wire [7:0] ua
);
wire _unused = VGND ^ VDPWR ^ V... |
ttgf0p3_0221 | ttgf0p3 | ODGrip-ttgf-polywave | task_polywave_top_digital | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "project.v" 1
/*
* Copyright (c) 2026 Riccardo Pellegrini
* SPDX-License-Identifier: Apache-2.0
*
* Quad 16-bit R2R performance engine for a 328.72um x 206um TT GF180 pgvaa slot.
*
* The engine is intentionally area-aware: four phase accumulators, shared noise,
* cross-modulated timing, sequencer offsets... | module polywave_top_digital (
input wire VGND,
input wire VDPWR,
input wire VAPWR,
input wire [7:0] ui_in,
output wire [7:0] uo_out,
input wire [7:0] uio_in,
output wire [7:0] uio_out,
output wire [7:0] uio_oe,
output wire [15:0] R2R_Bn_0,
output wire [15:0... |
ttgf26b_0222 | ttgf26b | Omar90551-TTGF-PWM | task_pwm_comparator | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_PWM.v" 1
`default_nettype none
module tt_um_PWM (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable... | module pwm_comparator (
input wire clk,
input wire rst_n,
input wire enable,
input wire [7:0] count_in,
input wire [7:0] period_cfg,
input wire [7:0] duty_cfg,
output reg pwm_out
);
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
... |
ttgf26b_0223 | ttgf26b | Omar90551-TTGF-PWM | task_pwm_counter | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_PWM.v" 1
`default_nettype none
module tt_um_PWM (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7:0] uio_out, // IOs: Output path
output wire [7:0] uio_oe, // IOs: Enable... | module pwm_counter (
input wire clk,
input wire rst_n,
input wire enable,
input wire [7:0] period_cfg,
output reg [7:0] count_out
);
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
// REQ-07: Asynchronous Reset
count_out <= 8... |
ttsky26b_0224 | ttsky26b | Oreoluwa16-tt-water-level | task_WaterLevelController | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "project.v" 1
/*
* Copyright (c) 2026 Ore-Oluwa
* SPDX-License-Identifier: Apache-2.0
*
* Tiny Tapeout top-level wrapper for a 4-state Water Level Controller FSM.
*
* Pin map
* -------
* Inputs (ui_in):
* ui_in[0] = s0_low -- Low-level sensor (1 = water reaches low sensor)
* ui_in[1] = s1_high... | module WaterLevelController (
input wire clk, // System clock
input wire reset_n, // Active-low asynchronous reset
input wire s1_high, // High-level sensor (Bit 1)
input wire s0_low, // Low-level sensor (Bit 0)
output reg pump_out, ... |
ttihp26a_0225 | ttihp26a | Paafu-Create-the-GDS | task_ChiselTop | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "project.v" 1
/*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module PIDControllerTop(
input clock,
input reset,
input [7:0] io_pitch_desired,
input [7:0] io_roll_desired,
input [7:0] io_yaw_desired,
input [7:0] io_control,
in... | module ChiselTop(
input clock,
input reset,
input [7:0] io_ui_in,
output [7:0] io_uo_out,
input [7:0] io_uio_in,
output [7:0] io_uio_out,
output [7:0] io_uio_oe
);
// RANDOMIZE_REG_INIT
wire pid_clock; // @[ChiselTop.scala 50:19]
wire pid_re... |
ttihp26a_0226 | ttihp26a | Paafu-Create-the-GDS | task_DS1050PWMAdapter | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "project.v" 1
/*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module PIDControllerTop(
input clock,
input reset,
input [7:0] io_pitch_desired,
input [7:0] io_roll_desired,
input [7:0] io_yaw_desired,
input [7:0] io_control,
in... | module DS1050PWMAdapter(
input [15:0] io_pid_pwm,
output [4:0] io_ds_pwm
);
assign io_ds_pwm = io_pid_pwm[15:11]; // @[ChiselTop.scala 333:27]
endmodule |
ttihp26a_0227 | ttihp26a | Paafu-Create-the-GDS | task_DataCollector | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "project.v" 1
/*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module PIDControllerTop(
input clock,
input reset,
input [7:0] io_pitch_desired,
input [7:0] io_roll_desired,
input [7:0] io_yaw_desired,
input [7:0] io_control,
in... | module DataCollector(
input clock,
input reset,
input [7:0] io_ui_in,
output [7:0] io_uo_out,
output [7:0] io_uio_out,
output [7:0] io_uio_oe,
output [15:0] io_word_out,
output io_word_valid
);
// RANDOMIZE_REG_INIT
reg [1:0] state; // @[ChiselTo... |
ttihp26a_0228 | ttihp26a | Paafu-Create-the-GDS | task_PIDControllerTop | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "project.v" 1
/*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module PIDControllerTop(
input clock,
input reset,
input [7:0] io_pitch_desired,
input [7:0] io_roll_desired,
input [7:0] io_yaw_desired,
input [7:0] io_control,
in... | module PIDControllerTop(
input clock,
input reset,
input [7:0] io_pitch_desired,
input [7:0] io_roll_desired,
input [7:0] io_yaw_desired,
input [7:0] io_control,
input [7:0] io_data_in,
output [7:0] io_left_elevon,
output [7:0] io_right_elevon,
output [7:0] io_rudder
);
... |
ttihp26a_0229 | ttihp26a | PaxPlay-tiny-tapeout-design | task_synth | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "project.v" 1
/*
* Copyright (c) 2024 Benedikt Krimmel
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_krimmel_mini_synth (
input wire [7:0] ui_in, // [6:0] MIDI note 0-127, [7] gate
output wire [7:0] uo_out, // [7] = audio PWM (AudioPWM on uo[7])
input wire [... | module synth (
input wire clk,
input wire rst_n,
input wire [6:0] midi_note, // MIDI note 0-127
input wire gate, // 1 = note on
output wire [11:0] audio_sample, // unsigned 12-bit for simulation
output reg audio_out // 1-bit sigma-delta PWM
);
//... |
ttsky26b_0230 | ttsky26b | Petros-Emmanouilidis-ttnn | task_TTNN_TOP | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "project.v" 1
/*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_petros (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
output wire [7... | module TTNN_TOP (
clk,
rst_l,
in_en,
in_data,
out_prediction,
out_ready
);
reg _sv2v_0;
input wire clk;
input wire rst_l;
input wire in_en;
input wire in_data;
output reg [3:0] out_prediction;
output reg out_ready;
localparam IMAGE_SIZE = 64;
reg [63:0] image_flat;
always @(posedge clk)
if (~rst_l)
... |
ttsky25b_0231 | ttsky25b | PomMarkus-TinyTapeout | task_DFFx8 | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_pommarkus_i2c_slave.v" 1
/*
* Copyright (c) 2025 Markus Pommermayr
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
`line 10 "tt_um_pommarkus_i2c_slave.v" 0
`line 1 "i2c_top.v" 1
/*
* Copyright (c) 2025 Markus Pommermayr
* SPDX-License-Identifier: Apache-2.0
*/
`line 5 "i2c_to... | module DFFx8(
input wire clk,
input wire rst,
input wire data_in,
input wire [7:0] ff_enable,
output reg [7:0] data
);
always @(negedge clk or posedge rst) begin
if (rst)
data <= 8'b0;
else begin
if (ff_enable[7]) data[0] <= data_in;
if (f... |
ttsky25b_0232 | ttsky25b | PomMarkus-TinyTapeout | task_I2C_active | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_pommarkus_i2c_slave.v" 1
/*
* Copyright (c) 2025 Markus Pommermayr
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
`line 10 "tt_um_pommarkus_i2c_slave.v" 0
`line 1 "i2c_top.v" 1
/*
* Copyright (c) 2025 Markus Pommermayr
* SPDX-License-Identifier: Apache-2.0
*/
`line 5 "i2c_to... | module I2C_active(
input wire SDA,
input wire SCL,
input wire rst,
output reg Start,
output reg Stop
);
reg SDA_prev;
// Latch SDA on SCL high
always @(posedge SCL or posedge rst) begin
if (rst)
SDA_prev <= 1'b1;
else
SDA_prev <= SDA;
end
// Detect Start/Stop based on... |
ttsky25b_0233 | ttsky25b | PomMarkus-TinyTapeout | task_decoder | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_pommarkus_i2c_slave.v" 1
/*
* Copyright (c) 2025 Markus Pommermayr
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
`line 10 "tt_um_pommarkus_i2c_slave.v" 0
`line 1 "i2c_top.v" 1
/*
* Copyright (c) 2025 Markus Pommermayr
* SPDX-License-Identifier: Apache-2.0
*/
`line 5 "i2c_to... | module decoder(
input [3:0] regAdr,
input rst,
input clk_AdrLatch,
input enable_output,
output wire [10:0] registerSelect
);
reg [3:0] latchedAddr;
always @(negedge clk_AdrLatch or posedge rst) begin
if (rst)
latchedAddr <= 4'b0;
else
latchedAddr <= {r... |
ttsky25b_0234 | ttsky25b | PomMarkus-TinyTapeout | task_enabler | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_pommarkus_i2c_slave.v" 1
/*
* Copyright (c) 2025 Markus Pommermayr
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
`line 10 "tt_um_pommarkus_i2c_slave.v" 0
`line 1 "i2c_top.v" 1
/*
* Copyright (c) 2025 Markus Pommermayr
* SPDX-License-Identifier: Apache-2.0
*/
`line 5 "i2c_to... | module enabler (
input wire [7:0] d, // input byte
input wire en, // enable
output wire [7:0] q // output byte
);
assign q = en ? d : 8'b0;
endmodule |
ttsky25b_0235 | ttsky25b | PomMarkus-TinyTapeout | task_i2c_top | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_pommarkus_i2c_slave.v" 1
/*
* Copyright (c) 2025 Markus Pommermayr
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
`line 10 "tt_um_pommarkus_i2c_slave.v" 0
`line 1 "i2c_top.v" 1
/*
* Copyright (c) 2025 Markus Pommermayr
* SPDX-License-Identifier: Apache-2.0
*/
`line 5 "i2c_to... | module i2c_top(
input wire SDA, // I2C data line (also data input)
input wire SCL, // I2C clock
input wire rst, // global reset
output wire ACK_enable_out, // for master
output wire [7:0] data, // current byte received
output wire [10:0] registerSelect
);
wire start; ... |
ttsky25b_0236 | ttsky25b | PomMarkus-TinyTapeout | task_latch8 | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_pommarkus_i2c_slave.v" 1
/*
* Copyright (c) 2025 Markus Pommermayr
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
`line 10 "tt_um_pommarkus_i2c_slave.v" 0
`line 1 "i2c_top.v" 1
/*
* Copyright (c) 2025 Markus Pommermayr
* SPDX-License-Identifier: Apache-2.0
*/
`line 5 "i2c_to... | module latch8 (
input wire en, // enable: transparent when high
input wire rst, // asynchronous reset (active high)
input wire [7:0] d, // data input
output reg [7:0] q // latched output
);
/* verilator lint_off UNOPTFLAT */
/* verilator lint_off LATCH */
always @(*) b... |
ttsky25b_0237 | ttsky25b | PomMarkus-TinyTapeout | task_output_part | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_pommarkus_i2c_slave.v" 1
/*
* Copyright (c) 2025 Markus Pommermayr
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
`line 10 "tt_um_pommarkus_i2c_slave.v" 0
`line 1 "i2c_top.v" 1
/*
* Copyright (c) 2025 Markus Pommermayr
* SPDX-License-Identifier: Apache-2.0
*/
`line 5 "i2c_to... | module output_part(
input wire clk,
input wire rst,
input wire [7:0] data,
input wire [10:0] register_select, // 11-bit register trigger
input wire [7:0] ui_in, // direct passthrough input
output wire [7:0] uo_out
);
// 11 identical latches (CTRL0–CTRL2, DATA... |
ttsky25b_0238 | ttsky25b | PomMarkus-TinyTapeout | task_rs_latch | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_pommarkus_i2c_slave.v" 1
/*
* Copyright (c) 2025 Markus Pommermayr
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
`line 10 "tt_um_pommarkus_i2c_slave.v" 0
`line 1 "i2c_top.v" 1
/*
* Copyright (c) 2025 Markus Pommermayr
* SPDX-License-Identifier: Apache-2.0
*/
`line 5 "i2c_to... | module rs_latch(
input S,
input R,
output reg Q //,
// output Qn CHANGED -> not used
);
// assign Qn = ~Q; // Qn is always complement of Q CHANGED -> not used
/* verilator lint_off LATCH */
always @(*) begin
if (S & ~R)
Q = 1; // Set
else if (~S & R)
Q = 0; /... |
ttsky25b_0239 | ttsky25b | PomMarkus-TinyTapeout | task_stepper_onehot | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_pommarkus_i2c_slave.v" 1
/*
* Copyright (c) 2025 Markus Pommermayr
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
`line 10 "tt_um_pommarkus_i2c_slave.v" 0
`line 1 "i2c_top.v" 1
/*
* Copyright (c) 2025 Markus Pommermayr
* SPDX-License-Identifier: Apache-2.0
*/
`line 5 "i2c_to... | module stepper_onehot(
input wire clk,
input wire rst,
output reg [8:0] step
);
always @(posedge clk or posedge rst) begin
if (rst)
step <= 9'b000000001; // Start mit LSB = 1
else
if (step[8])
step <= 9'b000000010; // reset to step 1
else
step <= {ste... |
ttsky25b_0240 | ttsky25b | PomMarkus-TinyTapeout | task_stepper_onehot_28 | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_pommarkus_i2c_slave.v" 1
/*
* Copyright (c) 2025 Markus Pommermayr
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
`line 10 "tt_um_pommarkus_i2c_slave.v" 0
`line 1 "i2c_top.v" 1
/*
* Copyright (c) 2025 Markus Pommermayr
* SPDX-License-Identifier: Apache-2.0
*/
`line 5 "i2c_to... | module stepper_onehot_28(
input wire clk,
input wire rst,
output reg [28:0] step
);
reg [4:0] cnt; // 5-bit counter, counts 0..28
// Counter
always @(posedge clk or posedge rst) begin
if (rst)
cnt <= 5'd0;
else if (cnt == 5'd28)
cnt <= 5'd0; // wrap ... |
ttsky25b_0241 | ttsky25b | RebeccaRGB-tt-arrowboard | task_arrow_board | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "project.v" 1
/*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_rebeccargb_arrow_board (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
... | module arrow_board (
input wire [1:0] phase,
input wire [3:0] pattern,
input wire flashing,
input wire sequential,
input wire lt, bi, al,
output wire [15:0] lamps
);
reg [15:0] data;
assign lamps = ((data | {16{~lt}}) & {16{bi}}) ^ {16{~al}};
always_comb begin
case (pattern)
4'h0: data = (sequential & ... |
ttihp26a_0242 | ttihp26a | RebeccaRGB-ttihp-vga-pride | task_hvsync_generator | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "project.v" 1
/*
* Copyright (c) 2024 Rebecca G. Bettencourt
* Original idea by Foone Turing
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_rebeccargb_vga_pride (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input... | module hvsync_generator(clk, reset, hsync, vsync, display_on, hpos, vpos);
input clk;
input reset;
output reg hsync, vsync;
output display_on;
output reg [9:0] hpos;
output reg [9:0] vpos;
// declarations for TV-simulator sync parameters
// horizontal constants
parameter H_DISPLAY = 640; // ho... |
ttihp26a_0243 | ttihp26a | Romultra-2-bit-adder-TTIHP26a | task_SPI_RAM | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "project.v" 1
/*
* Copyright (c) 2026 Roméo Estezet
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_romultra_top (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: Input path
outp... | module SPI_RAM (
// SPI Interface
output reg o_SPI_CS, // Also used by the internal control to notify when spi action is done
output reg o_SPI_MOSI,
input wire i_SPI_MISO,
output reg o_SPI_SCK,
// data and address path
input wire i_ready_to_execute,
input wire [15:0] i_address,
inpu... |
ttsky26a_0244 | ttsky26a | Rongbin99-ece298a-f25 | task_phase_counter | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "audio_chip.v" 1
/*
* Copyright (c) 2025 Rongbin Gu, Evan Li
* SPDX-License-Identifier: MIT
*/
`default_nettype none
module tt_um_rongbin99_happyredmapleleaf_audio_chip (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, ... | module phase_counter (
output reg [9:0] subsample_phase, // subsample phase output
input wire clk, // clock
input wire rst_n // reset_n - low to reset
);
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
subsample_phase <= 10'b0; // ... |
ttsky26a_0245 | ttsky26a | Rongbin99-ece298a-f25 | task_pwm | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "audio_chip.v" 1
/*
* Copyright (c) 2025 Rongbin Gu, Evan Li
* SPDX-License-Identifier: MIT
*/
`default_nettype none
module tt_um_rongbin99_happyredmapleleaf_audio_chip (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, ... | module pwm (
input wire [7:0] subsample_phase, // subsample phase input
input wire [6:0] bitstream_ch1, // first bitstream input
input wire [6:0] bitstream_ch2, // second bitstream input
input wire clk, // clock
input wire rst_n, // reset_n - low to re... |
ttsky26a_0246 | ttsky26a | Rongbin99-ece298a-f25 | task_sync | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "audio_chip.v" 1
/*
* Copyright (c) 2025 Rongbin Gu, Evan Li
* SPDX-License-Identifier: MIT
*/
`default_nettype none
module tt_um_rongbin99_happyredmapleleaf_audio_chip (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, ... | module sync (
input wire in, // input to sync
input wire clk, // clock
input wire rst_n, // reset_n - low to reset
output reg out // output of sync (1 bit)
);
reg sync1;
always @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
sync... |
ttsky26a_0247 | ttsky26a | SGovindVLSI-ttsky-verilog-EV11 | task_lfsr_core | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "project.v" 1
/*
* Copyright (c) 2025 Govind
* SPDX-License-Identifier: Apache-2.0
*
* project.v — tt_um_LFSR top-level wrapper
*
* Configurable Galois LFSR for Tiny Tapeout SKY130 (1×1 tile)
*
* ┌──────────────────────────────────── Pin Map ─────────────────────────────────────┐
* │ ui_in[1:0] → mo... | module lfsr_core (
input wire [15:0] lfsr_reg,
input wire [15:0] tap_reg,
input wire [15:0] width_mask,
output wire [15:0] lfsr_next
);
wire fb;
wire [15:0] shifted;
wire [15:0] tapped;
wire all_zero;
assign fb = lfsr_reg[0];
assign ... |
ttsky26a_0248 | ttsky26a | SGovindVLSI-ttsky-verilog-EV11 | task_lfsr_ctrl | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "project.v" 1
/*
* Copyright (c) 2025 Govind
* SPDX-License-Identifier: Apache-2.0
*
* project.v — tt_um_LFSR top-level wrapper
*
* Configurable Galois LFSR for Tiny Tapeout SKY130 (1×1 tile)
*
* ┌──────────────────────────────────── Pin Map ─────────────────────────────────────┐
* │ ui_in[1:0] → mo... | module lfsr_ctrl (
input wire clk,
input wire rst_n,
input wire [1:0] mode,
input wire [1:0] width_sel,
input wire [1:0] poly_idx,
input wire [3:0] data_in,
output reg [15:0] lfsr_reg
);
localparam MODE_RUN = 2'b00;
localparam MODE_LOAD_SE... |
ttsky26b_0249 | ttsky26b | SalihOmerOngun-tt-basic-processor-project | task_alu | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "project.v" 1
/*
* Copyright (c) 2024 Your Name
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_basic8 (
input wire [7:0] ui_in,
output wire [7:0] uo_out,
input wire [7:0] uio_in,
output wire [7:0] uio_out,
output wire [7:0] uio_oe,
input wire en... | module alu (
input wire [7:0] a,
input wire [7:0] b,
input wire [2:0] sel,
output reg [7:0] result
);
always @(*) begin
case (sel)
3'd0: result = a + b;
3'd1: result = a - b;
3'd2: result = a | b;
3'd3: result = a ^ b;
3'd4: res... |
ttsky26b_0250 | ttsky26b | SharifGiraldoo-BootcampChipProject | task_alu_7b | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "alu_7b.v" 1
/*
* alu_7b.v — 7-bit Arithmetic Logic Unit (combinational)
*
* Bootcamp IC Design & Fabrication — IEEE OpenSilicon / IEEE CASS UTP 2026
*
* Pure combinational module. Receives two 7-bit operands and a 3-bit
* operation code; delivers an 8-bit result.
* Bit [7] of the result carries the over... | module alu_7b (
input wire [6:0] A, // Operand A (7 bits)
input wire [6:0] B, // Operand B (7 bits)
input wire [2:0] op, // Operation code
output reg [7:0] result // 8-bit result (includes carry/borrow in bit[7])
);
always @(*) begin
case (op)
3'b000: resu... |
ttgf0p2_0251 | ttgf0p2 | Sheffield-Chip-Design-Team-SPI-CPU-Final | task_ADD_MUX | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_spi_cpu.v" 1
/*
* Copyright (c) 2024 Mohammad Eissa, James Ashie Kotey, Bowen Shi
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_spi_cpu_top (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] u... | module ADD_MUX (
input wire _ADD,
input wire _SNZA,
input wire _SNZS,
input wire SF,
output reg _ADDin
);
// mux implimentation
/* always @(*) begin
if (SF & (_SNZA | _SNZS))
_ADDin = 1'b1;
else
_ADDin = _ADD;
end
*/
// combi... |
ttgf0p2_0252 | ttgf0p2 | Sheffield-Chip-Design-Team-SPI-CPU-Final | task_ALU_MUX | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_spi_cpu.v" 1
/*
* Copyright (c) 2024 Mohammad Eissa, James Ashie Kotey, Bowen Shi
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_spi_cpu_top (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] u... | module ALU_MUX (
input wire _SNZA,
input wire _SNZS,
input wire SF,
input wire [7:0] shiftOut,
input wire [7:0] ACCout,
input wire [3:0] Aout,
input wire [3:0] Bout,
output reg [7:0] in1,
output reg [7:0] in2
);
wire cond_snza = (_SNZA && SF);
wire cond_snzs... |
ttgf0p2_0253 | ttgf0p2 | Sheffield-Chip-Design-Team-SPI-CPU-Final | task_ArithmeticLogicUnit | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_spi_cpu.v" 1
/*
* Copyright (c) 2024 Mohammad Eissa, James Ashie Kotey, Bowen Shi
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_spi_cpu_top (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] u... | module ArithmeticLogicUnit (
input ADD,
input SUB,
input wire AND,
input wire OR,
input wire XOR,
input wire INV,
input wire CLR,
input wire [INPUT_DATA_WIDTH-1:0] in1,
input wire [INPUT_DATA_WIDTH-1:0] in2,
output reg [INPUT_D... |
ttgf0p2_0254 | ttgf0p2 | Sheffield-Chip-Design-Team-SPI-CPU-Final | task_Counter | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_spi_cpu.v" 1
/*
* Copyright (c) 2024 Mohammad Eissa, James Ashie Kotey, Bowen Shi
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_spi_cpu_top (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] u... | module Counter ( // counter D-type Flip Flop
input wire clk,
input wire reset,
input wire enable,
output reg [DATA_WIDTH-1:0] Q
);
parameter DATA_WIDTH = 4;
always @(posedge clk) begin
if (reset) begin // Reset should be checked first
Q <= 0;
end else if (e... |
ttgf0p2_0255 | ttgf0p2 | Sheffield-Chip-Design-Team-SPI-CPU-Final | task_DFF | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_spi_cpu.v" 1
/*
* Copyright (c) 2024 Mohammad Eissa, James Ashie Kotey, Bowen Shi
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_spi_cpu_top (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] u... | module DFF ( // standard D-type Flip Flop
input wire clk,
input wire [DATA_WIDTH-1:0] D,
output reg [DATA_WIDTH-1:0] Q
);
parameter DATA_WIDTH = 4;
always @(posedge clk) begin
Q <= D;
end
endmodule |
ttgf0p2_0256 | ttgf0p2 | Sheffield-Chip-Design-Team-SPI-CPU-Final | task_ENABLE_ACC_MUX | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_spi_cpu.v" 1
/*
* Copyright (c) 2024 Mohammad Eissa, James Ashie Kotey, Bowen Shi
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_spi_cpu_top (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] u... | module ENABLE_ACC_MUX(
input wire _AND, _OR, _XOR, _INV, _ADDin, _SUB, _CLR,
output wire enableACC
);
assign enableACC = _CLR || _ADDin || _SUB || _AND || _OR || _XOR || _INV; // alu needs to be enabled usign the relevant instruction
endmodule |
ttgf0p2_0257 | ttgf0p2 | Sheffield-Chip-Design-Team-SPI-CPU-Final | task_EnableDFF | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_spi_cpu.v" 1
/*
* Copyright (c) 2024 Mohammad Eissa, James Ashie Kotey, Bowen Shi
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_spi_cpu_top (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] u... | module EnableDFF ( // DFF with enable
input wire clk,
input wire enable,
input wire [DATA_WIDTH-1:0] D,
output reg [DATA_WIDTH-1:0] Q
);
parameter DATA_WIDTH = 4;
always @(posedge clk) begin
if (enable) begin
Q <= D;
end
end
endmodule |
ttgf0p2_0258 | ttgf0p2 | Sheffield-Chip-Design-Team-SPI-CPU-Final | task_FullAdder | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_spi_cpu.v" 1
/*
* Copyright (c) 2024 Mohammad Eissa, James Ashie Kotey, Bowen Shi
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_spi_cpu_top (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] u... | module FullAdder (
input wire in1,
input wire in2,
input wire carryIn,
output sum,
output carryOut
);
assign {carryOut,sum} = in1 + in2; // behavioural description
endmodule |
ttgf0p2_0259 | ttgf0p2 | Sheffield-Chip-Design-Team-SPI-CPU-Final | task_InstructionDecoder | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_spi_cpu.v" 1
/*
* Copyright (c) 2024 Mohammad Eissa, James Ashie Kotey, Bowen Shi
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_spi_cpu_top (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] u... | module InstructionDecoder(
input [3:0] instructionIn,
output reg LDA,
output reg LDB,
output reg LDO,
output reg LDSA,
output reg LDSB,
output reg LSH,
output reg RSH,
output reg CLR,
output reg SNZA,
output reg SNZS,
output reg ADD,
output reg SUB,
... |
ttgf0p2_0260 | ttgf0p2 | Sheffield-Chip-Design-Team-SPI-CPU-Final | task_RegisterFile | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_spi_cpu.v" 1
/*
* Copyright (c) 2024 Mohammad Eissa, James Ashie Kotey, Bowen Shi
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_spi_cpu_top (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] u... | module RegisterFile (
input clk,
input reset,
input [INPUT_WIDTH -1:0] AIn,
input [INPUT_WIDTH -1:0] BIn,
input [OUTPUT_WIDTH -1:0] OIn,
input LDA,
input LDB,
input LDO,
outp... |
ttgf0p2_0261 | ttgf0p2 | Sheffield-Chip-Design-Team-SPI-CPU-Final | task_ResetDFF | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_spi_cpu.v" 1
/*
* Copyright (c) 2024 Mohammad Eissa, James Ashie Kotey, Bowen Shi
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_spi_cpu_top (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] u... | module ResetDFF ( // synchronous reset, no enable
input wire clk,
input wire reset,
input wire [DATA_WIDTH-1:0] D,
output reg [DATA_WIDTH-1:0] Q
);
parameter DATA_WIDTH = 8;
always @(posedge clk) begin
if (~reset) begin
Q <= D;
end else begin // reset behaviour
... |
ttgf0p2_0262 | ttgf0p2 | Sheffield-Chip-Design-Team-SPI-CPU-Final | task_ResetEnableDFF | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_spi_cpu.v" 1
/*
* Copyright (c) 2024 Mohammad Eissa, James Ashie Kotey, Bowen Shi
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_spi_cpu_top (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] u... | module ResetEnableDFF ( // synchronous reset with enable
input wire clk,
input wire reset,
input wire enable,
input wire [DATA_WIDTH-1:0] D,
output reg [DATA_WIDTH-1:0] Q
);
parameter DATA_WIDTH = 4;
always @(posedge clk) begin
if (reset) begin // Reset should be checked first
... |
ttgf0p2_0263 | ttgf0p2 | Sheffield-Chip-Design-Team-SPI-CPU-Final | task_SR_MUX | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_spi_cpu.v" 1
/*
* Copyright (c) 2024 Mohammad Eissa, James Ashie Kotey, Bowen Shi
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_spi_cpu_top (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] u... | module SR_MUX (
input wire _LDSA,
input wire _LDSB,
input wire [3:0] Aout,
input wire [3:0] Bout,
output wire [3:0] shiftIn,
output wire _LSR
);
assign _LSR = _LDSA | _LDSB;
/* always @(*) begin
if (_LDSA) begin
shiftIn = Aout;
end else if ... |
ttgf0p2_0264 | ttgf0p2 | Sheffield-Chip-Design-Team-SPI-CPU-Final | task_ShiftRegister | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_spi_cpu.v" 1
/*
* Copyright (c) 2024 Mohammad Eissa, James Ashie Kotey, Bowen Shi
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_spi_cpu_top (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] u... | module ShiftRegister ( // synchronous reset, with enable
input wire clk,
input wire reset,
input wire [3:0] in,
input wire loadEnable,
input wire [1:0] shiftState,
output reg [7:0] out,
output reg flag
);
always @(posedge clk) begin
if (~reset) be... |
ttgf0p2_0265 | ttgf0p2 | Sheffield-Chip-Design-Team-SPI-CPU-Final | task_combAdder | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_spi_cpu.v" 1
/*
* Copyright (c) 2024 Mohammad Eissa, James Ashie Kotey, Bowen Shi
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_spi_cpu_top (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] u... | module combAdder ( // Conbinational, Behavioural Description
input wire [DATA_WIDTH - 1:0] in1,
input wire [DATA_WIDTH - 1:0] in2,
output reg [DATA_WIDTH - 1:0] out,
output reg overflow
);
parameter DATA_WIDTH = 4; //4-bit by default;
always @(*) begin
{ov... |
ttgf0p2_0266 | ttgf0p2 | Sheffield-Chip-Design-Team-SPI-CPU-Final | task_combAdderSubtractor | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_spi_cpu.v" 1
/*
* Copyright (c) 2024 Mohammad Eissa, James Ashie Kotey, Bowen Shi
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_spi_cpu_top (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] u... | module combAdderSubtractor( // optimised adder/subtractor
input wire [DATA_WIDTH-1:0] in1, in2,
input wire sub,
output wire [DATA_WIDTH-1:0] out,
output wire overflow
);
parameter DATA_WIDTH = 8;
assign {overflow, out} = in1 + (sub ? (~in2 + 1) : in2); // Two's complement for subtraction
endmod... |
ttgf0p2_0267 | ttgf0p2 | Sheffield-Chip-Design-Team-SPI-CPU-Final | task_combINV | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_spi_cpu.v" 1
/*
* Copyright (c) 2024 Mohammad Eissa, James Ashie Kotey, Bowen Shi
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_spi_cpu_top (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] u... | module combINV (
input wire [DATA_WIDTH-1:0] in1,
output wire [DATA_WIDTH-1:0] out
);
parameter DATA_WIDTH = 4; //4-bit by default;
assign out = ~in1;
endmodule |
ttgf0p2_0268 | ttgf0p2 | Sheffield-Chip-Design-Team-SPI-CPU-Final | task_combXOR | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_spi_cpu.v" 1
/*
* Copyright (c) 2024 Mohammad Eissa, James Ashie Kotey, Bowen Shi
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_spi_cpu_top (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] u... | module combXOR (
input wire [DATA_WIDTH-1:0] in1, in2,
output wire [DATA_WIDTH-1:0] out
);
parameter DATA_WIDTH = 4; //4-bit by default;
assign out = in1 ^ in2;
endmodule |
ttgf0p2_0269 | ttgf0p2 | Sheffield-Chip-Design-Team-SPI-CPU-Final | task_spi_read_byte | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_spi_cpu.v" 1
/*
* Copyright (c) 2024 Mohammad Eissa, James Ashie Kotey, Bowen Shi
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_spi_cpu_top (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] u... | module spi_read_byte (
input wire clk,
input wire rst_n,
// Control from CPU
input wire start, // pulse / level, ignored when busy
input wire [15:0] addr, // address in external RAM
// Status back to CPU
output reg busy, // 1 while transact... |
ttgf0p2_0270 | ttgf0p2 | Sheffield-Chip-Design-Team-SPI-CPU-Final | task_spi_wrap | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_spi_cpu.v" 1
/*
* Copyright (c) 2024 Mohammad Eissa, James Ashie Kotey, Bowen Shi
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_spi_cpu_top (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] u... | module spi_wrap (
input wire clk,
input wire rst_n,
input wire [7:0] in_port, // input port (from ui_in)
output wire [7:0] out_port, // what we show on uo_out
output wire valid,
// SPI interface to external RAM (RP2040 emu)
output wire spi_cs_n,
output wi... |
ttsky25b_0271 | ttsky25b | Sheffield-Chip-Design-Team-TinyTapeStation | task_APU_trigger | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_Enjimneering_TTS.v" 1
/*
* Copyright (c) 2024 Tiny Tapeout LTD
* SPDX-License-Identifier: Apache-2.0
* Authors: James Ashie Kotey, Bowen Shi, Kwashie Andoh, Anubhav Avinash
* Abdulatif Babli, Rupert Bowen, K Arjunan, Cameron Brizland
* Last Updated: 16/06/2025 @ 16:21:00
*/
// Tiny Tapestation T... | module APU_trigger (
input wire clk,
input wire reset,
input wire frame_end,
input wire test_mode,
input wire SheepDragonCollision,
input wire SwordDragonCollision,
input wire PlayerDragonCollision,
output reg eat_sound,
output reg die_sound,
output reg hit_sound
);
... |
ttsky25b_0272 | ttsky25b | Sheffield-Chip-Design-Team-TinyTapeStation | task_AudioProcessingUnit | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_Enjimneering_TTS.v" 1
/*
* Copyright (c) 2024 Tiny Tapeout LTD
* SPDX-License-Identifier: Apache-2.0
* Authors: James Ashie Kotey, Bowen Shi, Kwashie Andoh, Anubhav Avinash
* Abdulatif Babli, Rupert Bowen, K Arjunan, Cameron Brizland
* Last Updated: 16/06/2025 @ 16:21:00
*/
// Tiny Tapestation T... | module AudioProcessingUnit (
input wire clk,
input wire reset,
input wire saw_trigger,
input wire square_trigger,
input wire noise_trigger,
input wire [9:0] x,
input wire [9:0] y,
output wire sound
);
reg [15:0] counter_reg; // current value of the oscillator counter (used as value... |
ttsky25b_0273 | ttsky25b | Sheffield-Chip-Design-Team-TinyTapeStation | task_CollisionDetector | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_Enjimneering_TTS.v" 1
/*
* Copyright (c) 2024 Tiny Tapeout LTD
* SPDX-License-Identifier: Apache-2.0
* Authors: James Ashie Kotey, Bowen Shi, Kwashie Andoh, Anubhav Avinash
* Abdulatif Babli, Rupert Bowen, K Arjunan, Cameron Brizland
* Last Updated: 16/06/2025 @ 16:21:00
*/
// Tiny Tapestation T... | module CollisionDetector (
input wire clk,
input wire reset,
input wire [7:0] playerPos,
input wire [7:0] swordPos,
input wire attack_enable,
input wire [7:0] sheepPos,
input wire [55:0] dragonSegmentPositions,
input wire [6:0] activeDragonSegments,
output re... |
ttsky25b_0274 | ttsky25b | Sheffield-Chip-Design-Team-TinyTapeStation | task_Comparator | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_Enjimneering_TTS.v" 1
/*
* Copyright (c) 2024 Tiny Tapeout LTD
* SPDX-License-Identifier: Apache-2.0
* Authors: James Ashie Kotey, Bowen Shi, Kwashie Andoh, Anubhav Avinash
* Abdulatif Babli, Rupert Bowen, K Arjunan, Cameron Brizland
* Last Updated: 16/06/2025 @ 16:21:00
*/
// Tiny Tapestation T... | module Comparator (
input wire [7:0] inA,
input wire [7:0] inB,
output wire out
);
assign out = (inA == inB);
endmodule |
ttsky25b_0275 | ttsky25b | Sheffield-Chip-Design-Team-TinyTapeStation | task_DragonBody | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_Enjimneering_TTS.v" 1
/*
* Copyright (c) 2024 Tiny Tapeout LTD
* SPDX-License-Identifier: Apache-2.0
* Authors: James Ashie Kotey, Bowen Shi, Kwashie Andoh, Anubhav Avinash
* Abdulatif Babli, Rupert Bowen, K Arjunan, Cameron Brizland
* Last Updated: 16/06/2025 @ 16:21:00
*/
// Tiny Tapestation T... | module DragonBody(
input clk,
input reset,
input vsync,
input heal, // grow
input hit, // shrink
input [31:0] current_time,
input [5:0] movementCounter,
input [9:0] Dragon_Head, // [9:8] orientation, [7:0] position
output... |
ttsky25b_0276 | ttsky25b | Sheffield-Chip-Design-Team-TinyTapeStation | task_DragonHead | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_Enjimneering_TTS.v" 1
/*
* Copyright (c) 2024 Tiny Tapeout LTD
* SPDX-License-Identifier: Apache-2.0
* Authors: James Ashie Kotey, Bowen Shi, Kwashie Andoh, Anubhav Avinash
* Abdulatif Babli, Rupert Bowen, K Arjunan, Cameron Brizland
* Last Updated: 16/06/2025 @ 16:21:00
*/
// Tiny Tapestation T... | module DragonHead (
input clk,
input reset,
input [7:0] targetPos,
input vsync,
output reg [1:0] dragon_direction,
output reg [7:0] dragon_pos,
output reg [5:0] movement_counter// Counter for delaying dragon's movement otherwise sticks to player
);
reg [3:0] dragon_x;
reg [3:0... |
ttsky25b_0277 | ttsky25b | Sheffield-Chip-Design-Team-TinyTapeStation | task_DragonTarget | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_Enjimneering_TTS.v" 1
/*
* Copyright (c) 2024 Tiny Tapeout LTD
* SPDX-License-Identifier: Apache-2.0
* Authors: James Ashie Kotey, Bowen Shi, Kwashie Andoh, Anubhav Avinash
* Abdulatif Babli, Rupert Bowen, K Arjunan, Cameron Brizland
* Last Updated: 16/06/2025 @ 16:21:00
*/
// Tiny Tapestation T... | module DragonTarget(
input wire clk,
input wire reset,
input wire trigger,
input wire dragon_hurt,
input wire target_reached_player,
input wire target_reached_sheep,
input wire [6:0] dragon_state,
input wire [7:0] dragon_pos,
input wire [7:0] player_pos,
inpu... |
ttsky25b_0278 | ttsky25b | Sheffield-Chip-Design-Team-TinyTapeStation | task_InputCollector | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_Enjimneering_TTS.v" 1
/*
* Copyright (c) 2024 Tiny Tapeout LTD
* SPDX-License-Identifier: Apache-2.0
* Authors: James Ashie Kotey, Bowen Shi, Kwashie Andoh, Anubhav Avinash
* Abdulatif Babli, Rupert Bowen, K Arjunan, Cameron Brizland
* Last Updated: 16/06/2025 @ 16:21:00
*/
// Tiny Tapestation T... | module InputCollector (
input wire clk,
input wire reset,
input wire up,
input wire down,
input wire left,
input wire right,
input wire attack,
output reg [9:0] control_state
);
initial begin
control_state = 0;
end
reg [4:0] previous_state = 5'b0;
... |
ttsky25b_0279 | ttsky25b | Sheffield-Chip-Design-Team-TinyTapeStation | task_NESTest_Top | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_Enjimneering_TTS.v" 1
/*
* Copyright (c) 2024 Tiny Tapeout LTD
* SPDX-License-Identifier: Apache-2.0
* Authors: James Ashie Kotey, Bowen Shi, Kwashie Andoh, Anubhav Avinash
* Abdulatif Babli, Rupert Bowen, K Arjunan, Cameron Brizland
* Last Updated: 16/06/2025 @ 16:21:00
*/
// Tiny Tapestation T... | module NESTest_Top (
// system
input wire system_clk_25MHz, // System clock
input wire rst_n, // active low reset
// controller interface [GPIO]
input wire NES_Data, // NES controller data -> ui_in[1]
output wire NES_Latch, // uo_out[1] -> NES controller latch
output wire NES_... |
ttsky25b_0280 | ttsky25b | Sheffield-Chip-Design-Team-TinyTapeStation | task_NES_Reciever | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_Enjimneering_TTS.v" 1
/*
* Copyright (c) 2024 Tiny Tapeout LTD
* SPDX-License-Identifier: Apache-2.0
* Authors: James Ashie Kotey, Bowen Shi, Kwashie Andoh, Anubhav Avinash
* Abdulatif Babli, Rupert Bowen, K Arjunan, Cameron Brizland
* Last Updated: 16/06/2025 @ 16:21:00
*/
// Tiny Tapestation T... | module NES_Reciever (
input wire clk,
input wire reset,
input wire data, // input data from nes controller to FPGA
output reg latch,
output reg nes_clk, // outputs from FPGA to nes controller
output wire A,
output wire B,
output wire select,
output wire start,
output wire up,... |
ttsky25b_0281 | ttsky25b | Sheffield-Chip-Design-Team-TinyTapeStation | task_PictureProcessingUnit | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_Enjimneering_TTS.v" 1
/*
* Copyright (c) 2024 Tiny Tapeout LTD
* SPDX-License-Identifier: Apache-2.0
* Authors: James Ashie Kotey, Bowen Shi, Kwashie Andoh, Anubhav Avinash
* Abdulatif Babli, Rupert Bowen, K Arjunan, Cameron Brizland
* Last Updated: 16/06/2025 @ 16:21:00
*/
// Tiny Tapestation T... | module PictureProcessingUnit(
input clk_in,
input reset,
input wire [17:0] entity_1,
input wire [17:0] entity_2, //Simultaneously supports up to 9 objects in the scene.
input wire [17:0] entity_3, //Set the entity ID to 4'hf for unused channels.
input wire [17:0] entity_4,
input wire... |
ttsky25b_0282 | ttsky25b | Sheffield-Chip-Design-Team-TinyTapeStation | task_PlayerLogic | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_Enjimneering_TTS.v" 1
/*
* Copyright (c) 2024 Tiny Tapeout LTD
* SPDX-License-Identifier: Apache-2.0
* Authors: James Ashie Kotey, Bowen Shi, Kwashie Andoh, Anubhav Avinash
* Abdulatif Babli, Rupert Bowen, K Arjunan, Cameron Brizland
* Last Updated: 16/06/2025 @ 16:21:00
*/
// Tiny Tapestation T... | module PlayerLogic (
input clk,
input reset,
input wire trigger,
input wire [9:0] input_data,
output reg [7:0] player_pos,
output reg [1:0] player_orientation, // player orientation
output reg [1:0] player_direction, // player direction
output reg [3:0] ... |
ttsky25b_0283 | ttsky25b | Sheffield-Chip-Design-Team-TinyTapeStation | task_SpriteROM | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_Enjimneering_TTS.v" 1
/*
* Copyright (c) 2024 Tiny Tapeout LTD
* SPDX-License-Identifier: Apache-2.0
* Authors: James Ashie Kotey, Bowen Shi, Kwashie Andoh, Anubhav Avinash
* Abdulatif Babli, Rupert Bowen, K Arjunan, Cameron Brizland
* Last Updated: 16/06/2025 @ 16:21:00
*/
// Tiny Tapestation T... | module SpriteROM (
input clk,
input reset,
// input wire read_enable,
input [1:0] orientation,
input [3:0] sprite_ID,
input [2:0] line_index,
output reg [7:0] data
);
localparam UP = 2'b00;
localparam RIGHT = 2'b01;
localparam DOWN = ... |
ttsky25b_0284 | ttsky25b | Sheffield-Chip-Design-Team-TinyTapeStation | task_gamepad_pmod_decoder | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_Enjimneering_TTS.v" 1
/*
* Copyright (c) 2024 Tiny Tapeout LTD
* SPDX-License-Identifier: Apache-2.0
* Authors: James Ashie Kotey, Bowen Shi, Kwashie Andoh, Anubhav Avinash
* Abdulatif Babli, Rupert Bowen, K Arjunan, Cameron Brizland
* Last Updated: 16/06/2025 @ 16:21:00
*/
// Tiny Tapestation T... | module gamepad_pmod_decoder (
input wire clk,
input wire rst_n,
input wire [11:0] data_reg,
output wire b,
output wire y,
output wire select,
output wire start,
output wire up,
output wire down,
output wire left,
output wire right,
output wire a,
output wire x,
ou... |
ttsky25b_0285 | ttsky25b | Sheffield-Chip-Design-Team-TinyTapeStation | task_rng | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_Enjimneering_TTS.v" 1
/*
* Copyright (c) 2024 Tiny Tapeout LTD
* SPDX-License-Identifier: Apache-2.0
* Authors: James Ashie Kotey, Bowen Shi, Kwashie Andoh, Anubhav Avinash
* Abdulatif Babli, Rupert Bowen, K Arjunan, Cameron Brizland
* Last Updated: 16/06/2025 @ 16:21:00
*/
// Tiny Tapestation T... | module rng ( // random nuumber generator based on linear feedback + seed
input wire clk,
input wire reset,
input wire trigger,
input wire [7:0] seed, // Seed input for initializing randomness
output wire ready,
output reg [7:0] rdm_num
);
localparam [7:0] default_value = 8'b1001_1011;
reg trigger_r... |
ttsky25b_0286 | ttsky25b | Sheffield-Chip-Design-Team-TinyTapeStation | task_sync_generator | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_Enjimneering_TTS.v" 1
/*
* Copyright (c) 2024 Tiny Tapeout LTD
* SPDX-License-Identifier: Apache-2.0
* Authors: James Ashie Kotey, Bowen Shi, Kwashie Andoh, Anubhav Avinash
* Abdulatif Babli, Rupert Bowen, K Arjunan, Cameron Brizland
* Last Updated: 16/06/2025 @ 16:21:00
*/
// Tiny Tapestation T... | module sync_generator (
input clk,
input reset,
output reg hsync,
output reg vsync,
output wire display_on,
output wire [9:0] screen_hpos,
output wire [9:0] screen_vpos,
output wire frame_end,
output wire input_enable... |
ttsky26b_0287 | ttsky26b | Sheffield-Chip-Design-Team-tiny-demoscene | task_bitmap_rom | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_vga_sharc_demo.v" 1
/*
* Based on demos by Renaldas Zioma, Tom Verbeure and Uri Shaked.
*
* Multi-logo DVD-style bouncing:
* - ui_in[0] = checkerboard parallax background
* - ui_in[1] = diamond ripple effect
* - ui_in[2] = colour cycling on logo bounces
* - ui_in[5:0] used as checker base colo... | module bitmap_rom (
input wire [6:0] x,
input wire [6:0] y,
output wire pixel
);
reg [7:0] mem[2047:0];
initial begin
mem[0] = 8'h00;
mem[1] = 8'h00;
mem[2] = 8'h00;
mem[3] = 8'h00;
mem[4] = 8'h00;
mem[5] = 8'h00;
mem[6] = 8'h00;
mem[7] = 8'h00;
mem[8] = 8'h00;
m... |
ttsky26b_0288 | ttsky26b | Sheffield-Chip-Design-Team-tiny-spi-mem-ctrl-test | task_spi_mem_ctrl | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_enjimneering_spi_mem.v" 1
/*
* Copyright (c) 2024 Uri Shaked
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_enjimneering_spi_mem (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: I... | module spi_mem_ctrl (
input wire clk,
input wire rst_n,
// Control signals from regs
input wire [15:0] addr, // address in external RAM
input wire start, // pulse to start transaction
input wire last, // asserted when this is the last byte to read in seque... |
ttsky26b_0289 | ttsky26b | Sheffield-Chip-Design-Team-tiny-spi-mem-ctrl-test | task_vga_sync | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_enjimneering_spi_mem.v" 1
/*
* Copyright (c) 2024 Uri Shaked
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_enjimneering_spi_mem (
input wire [7:0] ui_in, // Dedicated inputs
output wire [7:0] uo_out, // Dedicated outputs
input wire [7:0] uio_in, // IOs: I... | module vga_sync (
input clk,
input rst,
output reg hsync,
output reg vsync,
output wire display_on,
output wire [9:0] screen_hpos,
output wire [9:0] screen_vpos,
output wire frame_end
);
//--------------------------------------------------------------... |
ttsky26b_0290 | ttsky26b | Sheffield-Chip-Design-Team-tiny-uart-test | task_bss_uart | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_enjimneering_bss_uart.v" 1
/*
* Copyright (c) 2024 James Ashie Kotey, Kreesha Ramachandran
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
module tt_um_enjimneering_bss_uart (
input wire [7:0] ui_in,
output wire [7:0] uo_out,
input wire [7:0] uio_in,
output wire [7:... | module bss_uart (
input wire clk,
input wire rst_n,
input wire uart_rx,
output wire uart_tx,
input wire [2:0] baud_select,
input wire parity_en,
input wire parity_odd,
input wire rx_valid,
output wire rx_ready,
output wire [7:0] rx_data,
input wire tx_vali... |
ttihp26a_0291 | ttihp26a | StaCu-ttihp-snake-game | task_apple | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_snake_game.sv" 1
/*
* Copyright (c) 2025 David Volz
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
`line 7 "tt_um_snake_game.sv" 0
`line 1 "common.sv" 1
/*
* Copyright (c) 2025 David Volz
* SPDX-License-Identifier: Apache-2.0
*/
`line 5 "common.sv" 0
// Game dimensions
// N... | module apple (
input logic clk,
input logic rst_n,
input logic rng_rst_n,
input logic i_new_user_input,
input logic [4:0] i_snake_x,
input logic [3:0] i_snake_y,
input logic i_snake_first,
input logic i_snake_last,
input logic i_snake_valid,
output logic [4:0... |
ttihp26a_0292 | ttihp26a | StaCu-ttihp-snake-game | task_control | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_snake_game.sv" 1
/*
* Copyright (c) 2025 David Volz
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
`line 7 "tt_um_snake_game.sv" 0
`line 1 "common.sv" 1
/*
* Copyright (c) 2025 David Volz
* SPDX-License-Identifier: Apache-2.0
*/
`line 5 "common.sv" 0
// Game dimensions
// N... | module control (
input logic clk,
input logic rst_n,
input logic i_up,
input logic i_down,
input logic i_left,
input logic i_right,
input logic [1:0] i_head_dir,
output logic [1:0] o_dir,
output logic o_start,
output logic o_new_user_input
);
l... |
ttihp26a_0293 | ttihp26a | StaCu-ttihp-snake-game | task_game | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_snake_game.sv" 1
/*
* Copyright (c) 2025 David Volz
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
`line 7 "tt_um_snake_game.sv" 0
`line 1 "common.sv" 1
/*
* Copyright (c) 2025 David Volz
* SPDX-License-Identifier: Apache-2.0
*/
`line 5 "common.sv" 0
// Game dimensions
// N... | module game (
input logic clk,
input logic rst_n,
input logic i_up,
input logic i_down,
input logic i_left,
input logic i_right,
input logic i_pause,
input logic i_restart,
output logic [1:0] o_vga_r,
output logic [1:0] o_vga_g,
output logic [1:0] o_v... |
ttihp26a_0294 | ttihp26a | StaCu-ttihp-snake-game | task_random | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_snake_game.sv" 1
/*
* Copyright (c) 2025 David Volz
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
`line 7 "tt_um_snake_game.sv" 0
`line 1 "common.sv" 1
/*
* Copyright (c) 2025 David Volz
* SPDX-License-Identifier: Apache-2.0
*/
`line 5 "common.sv" 0
// Game dimensions
// N... | module random (
input logic clk,
input logic rst_n,
input logic update,
output logic [3:0] rng4,
output logic [4:0] rng5
);
logic [3:0] lfsr4;
logic [4:0] lfsr5;
logic feedback4;
logic feedback5;
assign feedback4 = lfsr4[0] ^ lfsr4[3];
assign feedback5 = lfsr5[2] ^ lfsr5[4];
assign rn... |
ttihp26a_0295 | ttihp26a | StaCu-ttihp-snake-game | task_snake | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_snake_game.sv" 1
/*
* Copyright (c) 2025 David Volz
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
`line 7 "tt_um_snake_game.sv" 0
`line 1 "common.sv" 1
/*
* Copyright (c) 2025 David Volz
* SPDX-License-Identifier: Apache-2.0
*/
`line 5 "common.sv" 0
// Game dimensions
// N... | module snake (
input logic clk,
input logic rst_n,
input logic i_tick,
input logic [1:0] i_dir,
output logic [1:0] o_head_dir,
output logic o_tick_done,
output logic o_tick_interval,
input logic i_eat,
output logic [4:0] o_head_x,
output logic [3:0] o_head_y,
outpu... |
ttihp26a_0296 | ttihp26a | StaCu-ttihp-snake-game | task_sound | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_snake_game.sv" 1
/*
* Copyright (c) 2025 David Volz
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
`line 7 "tt_um_snake_game.sv" 0
`line 1 "common.sv" 1
/*
* Copyright (c) 2025 David Volz
* SPDX-License-Identifier: Apache-2.0
*/
`line 5 "common.sv" 0
// Game dimensions
// N... | module sound (
input logic clk,
input logic rst_n,
input logic vsync_pulse,
input logic pwm_base,
// sound sources (all single cycle events)
input logic failure,
input logic success,
input logic eat,
input logic tick,
// sou... |
ttihp26a_0297 | ttihp26a | StaCu-ttihp-snake-game | task_tickgen | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_snake_game.sv" 1
/*
* Copyright (c) 2025 David Volz
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
`line 7 "tt_um_snake_game.sv" 0
`line 1 "common.sv" 1
/*
* Copyright (c) 2025 David Volz
* SPDX-License-Identifier: Apache-2.0
*/
`line 5 "common.sv" 0
// Game dimensions
// N... | module tickgen (
input logic clk,
input logic rst_n,
input logic i_up,
input logic i_down,
input logic i_restart,
input logic i_vsync,
input logic i_tick_done,
output logic o_tick
);
logic prev_user_input;
logic [3:0] counter_ma... |
ttihp26a_0298 | ttihp26a | StaCu-ttihp-snake-game | task_vga | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_snake_game.sv" 1
/*
* Copyright (c) 2025 David Volz
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
`line 7 "tt_um_snake_game.sv" 0
`line 1 "common.sv" 1
/*
* Copyright (c) 2025 David Volz
* SPDX-License-Identifier: Apache-2.0
*/
`line 5 "common.sv" 0
// Game dimensions
// N... | module vga (
input logic clk,
input logic rst_n,
input logic game_rst_n,
output logic [1:0] r,
output logic [1:0] g,
output logic [1:0] b,
output logic vsync,
output logic vsync_pulse,
output logic hsync,
output logic pwm_base,
input logic [4:0] apple_x,
input ... |
ttihp26a_0299 | ttihp26a | StaCu-ttihp-snake-game | task_vga_sync | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "tt_um_snake_game.sv" 1
/*
* Copyright (c) 2025 David Volz
* SPDX-License-Identifier: Apache-2.0
*/
`default_nettype none
`line 7 "tt_um_snake_game.sv" 0
`line 1 "common.sv" 1
/*
* Copyright (c) 2025 David Volz
* SPDX-License-Identifier: Apache-2.0
*/
`line 5 "common.sv" 0
// Game dimensions
// N... | module vga_sync (
input logic clk,
input logic rst_n,
output logic [9:0] px,
output logic [9:0] py,
output logic [9:0] next_px,
output logic [9:0] next_py,
output logic visible,
output logic vsync,
output logic hsync
);
assign next_px = px + 1;
assign next_py = py + 1;
// d... |
ttsky25b_0300 | ttsky25b | StrasTi-8-Bit-ALU | task_and_gate | You are an expert Verilog hardware designer working on a complete FPGA or ASIC project. You are given the full source code of a Verilog project. One of the modules in the project is incomplete — its implementation is missing and marked with:
// >>> Module Implementation Begin
// <<< Module Implementation End
Your ta... | `line 1 "constants/constants.vh" 1
// ALU operation codes
// Bit width definitions
// ALU status flag
// ALU overflow flag
`line 34 "constants/constants.vh" 2
`line 1 "modules/one_bit_alu.v" 1
// Copyright 2026 Timon Strassern
//
// Licensed under the Apache License, V... | module and_gate(
input a_i,
input b_i,
output reg result_o
);
// using built in operator:
// assign result_o = a_i && b_i;
always @(*) begin : and_logic
if (a_i == 1'b1 && b_i == 1'b1)
result_o = 1'b1;
else
result_o = 1'b0;
end
endmodule |
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