cxlssd-results / AUDIT_20AGENT_REPORT.md
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20-Agent Deep Audit Report

Date: 2026-04-19 21:55
Scope: Method "Stall-Aware Embedding Layout + E+L0 Dual-Path Routing + Host LFU L0"
Wave 1: 12 agents(narrative / prior art / code / fairness)
Wave 2: 8 agents(statistics / simulation / data / traceability)


💀 論文不可送審的 Catastrophic Blockers(需立刻修)

1. RESULTS.md Optane row 數字錯 → 結論 INVERT

  • Claim "MaxEmbed 5.62 ms/batch, CV 5.4%, 贏 E+L0 2.31x"
  • 真實:MaxEmbed overall_us = 15.80 ms/batch, CV 21.3%
  • E+L0 在 Optane 也贏 9.5x,不是輸 2.31x
  • Agent 13: parse unit swap(5.62 是 per-sample μs,5.4% 是 ops/s CV)
  • 立刻修 RESULTS.md + 所有引用該結論的地方

2. Paper 捏造 stall + scheduling 實驗數字

  • Agent 3 + 20 雙重確認:
    • 所有 stall numbers(80.10 / 11.47 / 6.02 / 4.04 / 5.08 / 7.80 / 10.38 / 14.41 / 3844 ms)都是 analytic 推導,但 paper 寫成 "MQSim cycle-accurate 輸出"
    • 隱含 per-miss latency 在不同 step 不一致(7.56/37/47/9.34μs 不可能同時為真)
    • Tagged flash 234,895 完全虛構(實際 92,331)
    • Scheduling flash 5,160/5,224/26,132/31,600 虛構(沒跑過 miss_first/hit_first/spread_miss 實驗)
    • SE spread-miss 29,532 MISLABELED(實際是 cog_v2_se K10000)
  • 行動:重跑 scheduling 實驗或改寫 paper 去掉假數字

3. Paper Narrative 3 docs 互相矛盾 + E+L0 核心未寫

  • Agent 1 + 19 雙重確認:
    • paper_story.md 推 miss-first
    • algorithm_design.md 推 COG v2 spread-miss
    • page_oriented_embedding_spec.md 是舊 project
    • E+L0 Dual-Path Routing + Host LFU L0(宣稱的核心)3 個 doc 都沒寫
  • dual_path_pollution_model.md100% vapor claim:Score_MEM / PC(p) / ConflictRisk / 最佳 split k* / frequency-sketch admission filter 全無 code 實作,code 用 hardcoded EWMA_THETA=0.926f(archived doc previously labelled the admission filter "TinyLFU" — that claim is now withdrawn; the shipped L0 is aging LFU, Arlitt et al. 2000)
  • 行動:完全重寫 paper_story + algorithm_design,用 E+L0 + Host LFU L0 當核心

4. MaxEmbed Tail 比較不成立

  • Agent 14:MaxEmbed 報的是 windowed avg 100-200 batches(CLT 壓低 variance ~10x)
  • 我方 E+L0 是 true per-batch
  • Paper claim "MaxEmbed tail 窄 p99/mean=1.04" 是 averaging artifact
  • 真實 MaxEmbed tail 未知
  • batch_latencies.csv 根本沒存,每 run 被覆蓋
  • 行動不能 claim tail,或重跑兩邊都 dump per-batch CSV

5. Dataset Scale 兩個 dataset 不對

  • CriteoTB: 宣稱 882M/4.37B,實際 126.6M/450M(-85% / -90%),HF 10% subsample
  • Alibaba-iFashion: 宣稱 4.46M items,實際 2.18M(-51%)referenced in 999K outfits
  • 行動:修 paper wording 或下 Tianchi 370GB full

🔴 Code Bugs(修不難,立刻動)

# Bug File:Line Agent Severity
6 Mode 2 timer 包 posix_memalign + pthread_create race_trace_v3.c:580 7 🔴
7 nhit = nm Mode 2 永遠 report miss=0,CSV 說謊 race_trace_v3.c:589 7 🔴
8 Mode 2 無 _mm_lfence(Mode 4 有)→ OoO overlap 讓 Mode 2 假快 race_trace_v3.c 7 🔴
9 l0_hit_primary_or_replica 定義但 unused(replicas dead code) race_trace_v3.c 7 🔴
10 LFU tie-break 永遠 bias way-0(comment 說 xorshift 但沒實作) race_trace_v3.c:252-258 8 🔴
11 LFU hash pg % sets 非均勻(table_offset bit clustering) race_trace_v3.c:231 8 🔴
12 LFU 16-bit counter 無 aging → scan resistance failure race_trace_v3.c:254 8 🟡
13 Criteo encoding insertion-order(paper 是 descending-freq) criteo_raw_to_maxembed.py 18 🔴
14 L0 預設 16384 (64MB),但 paper 聲稱 4096/16MB race_trace_v3.c L0_CAPACITY 8 🟡
15 Alibaba v1 converter(outfit-based)需 delete convert_alibaba_ifashion.py 18 🟡

🔴 Baseline Fairness(MaxEmbed 被削弱)

Agent 11 發現 4 個參數不對齊 paper AE:

參數 Paper AE 我方 影響
-n threads 64 1 64x 少 concurrency
-b batch_size 32 (Criteo) 16 減半
-c cache_ratio 0.01-0.4 sweep 0.0039(低於 paper range) off-regime
rep_ratio sweep 5 個 single 選最差 rep_ratio?

行動:補 anchor run at -n 64 -b 32 -c 0.01,讓 MaxEmbed 跑在它被調過的 regime


📚 Must-cite Competitors(Agent 4, 5, 6)

Paper Venue 重疊
CARINA SIGMOD'25 ~70% overlap on LFU filter for DLRM CXL(最嚴重)
Fleche EuroSys'22 "probability-based filter policy" 已用 filter cache 術語
RomeFS SoCC'24 Dual-path CXL.mem + CXL.io(非 DLRM,但協議層已被做)
Hotline MLSys'23 DLRM + DRAM/SSD tiering,直接 predecessor
FlexEMR EuroSys'24 3-tier DRAM/CXL/SSD recsys
UGACHE SOSP'23 Near-optimal hotness policy for embeddings
Merlin HPS NVIDIA 3-tier GPU/CPU/SSD 已建立 pattern
RecShard ASPLOS'22 HBM+DRAM embedding sharding
RecSSD ASPLOS'21 SSD embedding caching
TPP / Pond / TMO / HeMem ASPLOS'22-23, SOSP'21 Generic OS tiering(orthogonal)

我方剩下的 noveltyCXL-SSD × DLRM × stall-aware 三維交集(single-device dual-path + recsys-specific + offline+online hybrid)


🟡 Math / Statistical Rigor(Agent 2, 13, 14)

Issue Agent
dual_path_math_theory.md 基本空 2
Threshold 推導 0.64 vs 0.761 矛盾,中間推導缺失 2
ĥₚ, α, , effective_parallelism 都 undefined 2
Independence assumption 被 PC(p) 破壞(coupling) 2
n=5 對 CV>10% 不夠,CV 21% 要 n≥17,CV 50% 要 n≥95 13
E+L0 Optane ConfigD CV=49.6%(run3 spike 39.5ms)系統擾動 13
Warmup 沒 drop,B0 冷啟 3.4ms 主導 p99 14
5x 的 500 樣本只有 ~100 獨立(trace replay) 14
1/100 sampling rate,p9999 無法取得 14

🟡 Simulation Fidelity(Agent 15, 16)

Issue Status
FEMU direct-mapped vs CMM-H 8-way SA 🟡 config 一行可修 buffer_way=3
FEMU FIFO vs CMM-H LRU + MRU 🔴 FEMU 無 LRU 實作,需寫 lru.c
FEMU MEM MISS (60μs) < NAND (68μs) inverted 🔴 已知 bug,絕對數不可信
FEMU buffer 5MB vs CMM-H 48GB(1:10000) 🟡 residency-budget framing 可辯護
SPDK TCP loopback 加 10-15μs/IO vs PCIe 5μs 🟡 conservative 偏向(compressed speedup)
SPDK p99 = avg(真 P4510 p99 ≈ 2.5x avg) 🟡 對我方 claim 保守
SPDK ch_xfer_lat = 0(真 ONFI 3-4μs) 🟡 minor

📊 Verdict

Paper 目前狀態:不可直接送審

主要問題:

  1. 核心結論數字錯(Optane invert)
  2. Paper 捏造 stall + scheduling 實驗數字
  3. Narrative 描述的方法跟實際 code 不一致
  4. Tail latency 比較不合法
  5. Dataset 規模 2 個不對 paper

建議修復順序(優先級最高 → 最低):

  1. 🚨 修 RESULTS.md Optane row + 重新算勝負表
  2. 🚨 重寫 paper_story.md / algorithm_design.md 為 "E+L0 + Host LFU L0"
  3. 🚨 刪 paper_story 捏造 stall 數字 + 改寫 scheduling table(或 rerun 補實驗)
  4. 🚨 改 pollution_model 為 "future work / analytic bound" 或實作
  5. 🔴 修 code bugs(Mode 2 timer, nhit=nm, LFU tie-break, encoding)
  6. 🔴 補 MaxEmbed -n 64 -b 32 -c 0.01 anchor run
  7. 🔴 加 CARINA / Fleche / RomeFS / Hotline 等 related work
  8. 🟡 補 Criteo TB Tianchi full + Alibaba items 正確標註
  9. 🟡 修 FEMU buffer_way=3 + 考慮 LRU policy
  10. 🟡 補 tail latency 正確 instrumentation

預估整體修復 1-2 週(主要 paper 重寫 + rerun scheduling 實驗 + bug fix)。


📋 20 Agents 各自 Report Links

Agent Focus Flag level
1 Narrative audit 🔴
2 Math rigor 🔴
3 Claims vs data 💀
4 CXL+DLRM prior art 🔴
5 L0 filter prior art 🔴
6 Dual-path prior art 🔴
7 race_trace_v3.c audit 🔴
8 LFU L0 impl 🔴
9 FEMU mods 🟡
10 Timer placement 🟡
11 MaxEmbed baseline 🔴
12 HW param P4510 🟡
13 Variance CV 💀
14 Tail latency 💀
15 CMM-H fidelity 🔴
16 SPDK TCP overhead 🟡
17 Dataset scale 🔴
18 Preprocess alignment 🔴
19 Claim ↔ code 💀
20 Figure → data 💀

💀 = catastrophic blocker
🔴 = significant flag
🟡 = concern, fixable