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Datasets:
SAIFIINDUSTRIES
/
verilog_data-2
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0
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Files
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xet
Community
main
verilog_data-2
/
AugustinJose1221_FPGA-Build
/
design
116 kB
1 contributor
History:
1 commit
SAIFIINDUSTRIES
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387c3d6
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6 days ago
Controller.v
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2.13 kB
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Grayscaler.v
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3.02 kB
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README.md
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1.99 kB
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RWM_1.v
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4.2 kB
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RWM_2.v
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4.22 kB
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camera.v
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2.17 kB
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descriptor.v
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51.7 kB
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display.v
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361 Bytes
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filter5x5.v
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31.8 kB
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image.v
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image2.v
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525 Bytes
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keypoints.v
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3.39 kB
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matcher.v
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4.64 kB
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sobel_filter.v
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2.53 kB
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stitcher.v
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2.68 kB
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