Add Batch 5 with 10 repos

AngeloJacobo_RISC-V/README.md

@@ -0,0 +1,136 @@
+# Table of Contents  
+- [Project Overview](https://github.com/AngeloJacobo/RISC-V/tree/main#project-overview)
+- [Top Level Diagram (Classic 5-stage Pipeline)](https://github.com/AngeloJacobo/RISC-V/tree/main#top-level-diagram-classic-5-stage-pipeline)
+- [Top Level Diagram (Memory-mapped Peripherals)](https://github.com/AngeloJacobo/RISC-V/tree/main#top-level-diagram-memory-mapped-peripherals)
+- [Pipeline Features](https://github.com/AngeloJacobo/RISC-V/tree/main#pipeline-features)
+- [Supported Features of Zicsr Extension Module](https://github.com/AngeloJacobo/RISC-V/tree/main#supported-features-of-zicsr-extension-module)
+- [Regression Tests](https://github.com/AngeloJacobo/RISC-V/tree/main#regression-tests)
+- [Run Individual Tests](https://github.com/AngeloJacobo/RISC-V/tree/main#run-individual-tests)
+- [Install Design to FPGA (CMOD S7 FPGA Board)](https://github.com/AngeloJacobo/RISC-V/tree/main#install-design-to-fpga-cmod-s7-fpga-board)
+- [Sample Application [Smart Garden Assistant with Real-time Monitoring and Security]](https://github.com/AngeloJacobo/RISC-V/tree/main#sample-application-smart-garden-assistant-with-real-time-monitoring-and-security)
+- [Performance Metrics](https://github.com/AngeloJacobo/RISC-V/tree/main#performance-metrics)
+- [Paper Access](https://github.com/AngeloJacobo/RISC-V/tree/main#paper-access)
+
+## Project Overview
+This project involves the design and implementation of the RISC-V Base 32 Integer core using Verilog HDL. This work includes a 5-stage pipeline processor core, which supports the Zicsr (Control Status Registers) extension. The design is RISC-V compliant and has successfully passed the `rv32ui` (RV32 User-Mode Integer-Only) and `rv32mi` (RV32 Machine-Mode Integer-Only) [tests provided by RISC-V International](https://github.com/riscv-software-src/riscv-tests). Additionally, this includes support for [FreeRTOS](https://www.freertos.org/).
+
+The RISC-V ISA implemented here is based on [Volume 1, Unprivileged Spec v. 20191213](https://github.com/riscv/riscv-isa-manual/releases/tag/Ratified-IMAFDQC) and [Volume 2, Privileged Spec v. 20211203.](https://github.com/riscv/riscv-isa-manual/releases/tag/Priv-v1.12) 
+
+Inside the `rtl/` folder are the following:  
+ - `rv32i_core.v` = top module for the RV32I core and contains formal verification properties
+ - `rv32i_forwarding.v` = operand forwarding logic for data dependency hazards
+ - `rv32i_basereg.v` = regfile controller for the 32 integer base registers 
+ - `rv32i_fetch.v` =  retrieves instruction from the memory [FETCH STAGE]
+ - `rv32i_decoder.v`= decodes the 32 bit instruction [DECODE STAGE]
+ - `rv32i_alu.v` =  execute arithmetic operations and determines next `PC` and `rd` values [EXECUTE STAGE]
+ - `rv32i_memoryaccess.v` = sends and retrieves data to and from the memory [MEMORYACCESS STAGE]
+ - `rv32i_csr.v` = Zicsr extension module [executes parallel to MEMORYACCESS STAGE]
+ - `rv32i_writeback.v` = writes `rd` to basereg and handles pipeline flushes due to traps [WRITEBACK STAGE]
+ - `rv32i_header.vh` = header file which contains all necessary constants, magic numbers, and parameters
+ 
+ Inside the `test/` folder are the following: 
+ - `test.sh` = bash script for automating regression tests, program compilation, and design installation to FPGA board
+ - `entry.s` = start-up assembly code used by C programs
+ - `rv32i_linkerscript.ld` = script used by linker for partitioning memory sections
+ - `rv32i_core.sby` = SymbiYosys script for formal verification
+ - `rv32i_soc_TB.v` = testbench for `rv32i_soc`
+ - `rv32i_soc.v` = complete package containing the rv32i core, main memory, IO peripherals (CLINT, I2C, UART, and GPIO), and the memory wrapper.
+ - `wave.do` = Modelsim waveform template file
+ - `wave.gtkw` = GTKWave waveform template file
+ - `freertos/` folder = contains files for running FreeRTOS (`FreeRTOSConfig.h` and `freertos_risc_v_chip_specific_extensions.h`)
+ - `extra/` folder = contains custom assembly testfiles for all basic instructions, system instructions, and pipeline hazards.
+ - `lib/` folder = contains custom software library. The function APIs can be found on `rv32i.h`. This includes:
+     - LCD 1602 driver
+     - HygroPMOD (Digilent) driver
+     - DS1307 Real-time Clock driver
+     - CLINT (Core Logic Interrupt) interface
+     - UART interface
+     - I2C interface
+     - GPIOs interface
+     - sprintf implementation  
+     
+Inside the `Vivado Files/` folder are the following:
+- `run_vivado.tcl` = script for running Vivado in non-project mode. Used by `test.sh` to synthesize, implement, and install the design to the FPGA board.
+- `Cmod-S7-25-Master.xdc` = constraint file used by Vivado to install design to the [CMOD S7 FPGA Board](https://digilent.com/reference/programmable-logic/cmod-s7/start)
+
+## Top Level Diagram (Classic 5-stage Pipeline)
+![338910881_6488549441175863_7408166598375532727_n](https://user-images.githubusercontent.com/87559347/229502697-9e7bd8c9-cb11-44e1-9ccb-7dcd42e52f9f.png)
+## Top Level Diagram (Memory-mapped Peripherals)
+![338677885_186797960804225_4190069677959905489_n](https://user-images.githubusercontent.com/87559347/229550336-ae914d2f-a207-404a-8652-eda9cf90b9a6.png)
+
+## Pipeline Features
+ - 5 pipelined stages  
+ - Separate data and instruction memory interface **[Harvard architecture]**  
+ - Load instructions take a minimum of 3 clk cycles plus any additional memory stalls   
+ - Taken branch and jump instructions take a minimum of 3 clk cycles **[No Branch Prediction Used]**  
+ - An instruction with data dependency to the next instruction that is a CSR write or Load instruction will take a minimum of 2 clk cycles **[Operand Forwarding used]**   
+ - **All remaining instructions take a minimum of 1 clk cycle**   
+
+## Supported Features of Zicsr Extension Module
+ - **CSR instructions**: `CSRRW`, `CSRRS`, `CSRRC`, `CSRRWI`, `CSRRSI`, `CSRRCI`
+ - **Interrupts**: `External Interrupt`, `Timer Interrupt`, `Software Interrupt`
+ - **Exceptions**: `Illegal Instruction`, `Instruction Address Misaligned`, `Ecall`, `Ebreak`, `Load/Store Address Misaligned`
+ - **All relevant machine level CSRs**
+
+
+## Regression Tests
+The RISC-V toolchain `riscv64-unknown-elf-` and Modelsim executables `vsim` and `vlog` must be callable from PATH. If Modelsim executables are missing, the script will then call Icarus Verilog executables `iverilog` and `vvp` instead. Run **regression tests** inside `test/` directory either with:
+ - `$ ./test.sh` = run regression tests for both `riscv-tests/isa/rv32ui/` and `riscv-tests/isa/rv32mi/`
+ - `$ ./test.sh rv32ui` = run regression tests only for the `riscv-tests/isa/rv32ui/`
+ - `$ ./test.sh rv32mi` = run regression tests only for the `riscv-tests/isa/rv32mi/`
+ - `$ ./test.sh extra` =  run regression tests for `extra/` 
+ - `$ ./test.sh all` = run regression tests for `riscv-tests/isa/rv32ui/`, `riscv-tests/isa/rv32mi/`, and `extra/`  
+ - `$ ./test.sh compile` = compile-only the rtl files
+ 
+ ## Run Individual Tests
+ - `$ ./test.sh <testfile>` = test and debug testfile (without simulating) which is located at INDIVIDUAL_TESTDIR
+ - `$ ./test.sh <testfile> -gui` = test and debug testfile and open wave in Icarus
+ - `$ ./test.sh <testfile> -nosim` = compile and debug testfile without simulating it  
+Below is the expected output after running `$ ./test.sh`:   
+
+![image](https://user-images.githubusercontent.com/87559347/229745971-c1e2265b-6344-4666-b93b-8685c5e06e2a.png) 
+
+## Install Design to FPGA (CMOD S7 FPGA Board)
+ - `$ ./test.sh <design> -install` = compile and install design (located at INDIVIDUAL_TESTDIR) to FPGA board
+ - `$ ./test.sh freertos -install` = compile and install FreeRTOS program to FPGA board
+
+## Sample Application [Smart Garden Assistant with Real-time Monitoring and Security]
+The application code for this project can be found in `test/freertos/freertos.c`. The schematic is presented below along with the mobile app to access the device via Bluetooth. This mobile app was developed using [MIT App Inventor](https://appinventor.mit.edu/). The `apk` file is located at `test/freertos/mobile_app.apk` and the `aia` file, which can be imported to MIT App Inventor for further customization, is at `test/freertos/mobile_app.aia`.  
+![image](https://github.com/AngeloJacobo/RISC-V/assets/87559347/f3ccf912-d768-4635-a7ee-a862aa411870)
+ Below is the video demonstration for the sample application:  
+ 
+[![optimized_1685749569](https://github-production-user-asset-6210df.s3.amazonaws.com/87559347/243013492-b374190a-c51d-465e-a8f4-98bc5a34159f.png)](https://youtu.be/azBM6czbunY)
+
+
+## Performance Metrics 
+The whole design (core + zicsr + memory-mapped peripherals + 16KB memory) is implemented on an Arty S7 FPGA board. The following metrics were collected:  
+- Maximum operating frequency: 90MHz  
+- Resource Utilization: 1780 LUT, 1346 FF   
+- Total Power: 0.106W  
+
+![image](https://user-images.githubusercontent.com/87559347/229773269-1f06e104-c436-4aee-9ab1-b7cb840e866e.png)
+
+## Paper Access
+The title of the paper is `Design, Implementation, and Verification of a 32-bit RISC-V Processor with Real-Time Operating System and Regression Testing Framework`. As of this moment, the paper remains unpublished so I have refrained on linking it in this public repository. But I will post it here as soon as it is published (hopefully). But if you are still interested to have a look at the paper, you can chat me via [my LinkedIn](https://www.linkedin.com/in/angelo-jacobo/) so we can discuss it. Below is the abstract of the paper:   
+
+> RISC-V, an open standard Instruction Set Architecture (ISA), is gaining traction in various industries recently due to its open nature, straightforward design, modularity, and scalability. This paper presents the design, implementation, and verification of a 32-bit RISC-V processor with Real-Time Operating System (RTOS) support and a regression testing framework. The RISC-V core is designed using Verilog Hardware Description Language (HDL) based on the classic five-stage pipeline architecture. A comprehensive regression test is then conducted to ensure the processor core's compliance with the RISC-V ISA specifications. Thereafter, FreeRTOS is then integrated into the core, enabling effective management of time-sensitive microcontroller applications and multitasking, proving its relevance in the Internet of Things (IoT) domain. Top-level peripherals and a custom software library are also integrated to enhance the core's versatility and user-friendliness. A real-world application, the "Smart Garden Assistant with Real-time Monitoring and Security," is then developed to demonstrate the functioning RISC-V core with RTOS capability. Finally, a design evaluation is conducted and a comparative analysis is then performed to assess the design implementation against previous studies. This study aims to contribute to the growing body of research on RISC-V processors, emphasizing their value in the emerging era of open-source and customizable processor architectures.
+
+## Goal Checklist
+ :white_check_mark: Automate the testbench   
+ :white_check_mark: Add Zicsr extension   
+ :white_check_mark: Pass the Official RISC-V International Tests   
+ :white_check_mark: Convert FSM based core implementation to pipeline   
+ :white_check_mark: Add formal verification   
+ :white_check_mark: Be able to run C codes  
+ :white_check_mark: Add FreeRTOS Support  
+ :white_check_mark: Add custom software library   
+ :white_check_mark: Create a sample application using the core  
+ :black_square_button: Add AXI interface     
+
+# Donate   
+Support these open-source projects by donating  
+
+[![paypal](https://www.paypalobjects.com/en_US/i/btn/btn_donateCC_LG.gif)](https://www.paypal.com/donate?hosted_button_id=GBJQGJNCJZVRU)
+
+# Inquiries  
+Connect with me on LinkedIn: https://www.linkedin.com/in/angelo-jacobo/

AngeloJacobo_RISC-V/Vivado Files/run_vivado.tcl

@@ -0,0 +1,51 @@
+# run_vivado.tcl
+# NOTE:  typical usage would be "vivado -mode tcl -source run_vivado.tcl" 
+#
+# STEP#0: define output directory area.
+#
+set outputDir ./runs             
+file delete -force ./runs
+file mkdir $outputDir
+#
+# STEP#1: setup design sources and constraints
+#
+read_verilog  [ glob ../rtl/*.v ]
+read_verilog ../test/rv32i_soc.v
+read_mem ../test/memory.mem
+read_xdc ./Cmod-S7-25-Master.xdc
+#
+# STEP#2: run synthesis, report utilization and timing estimates, write checkpoint design
+#
+synth_design -top rv32i_soc -part xc7s25csga225-1
+#
+# STEP#3: run placement and logic optimzation, report utilization and timing estimates, write checkpoint design
+#
+opt_design 
+place_design 
+phys_opt_design 
+#
+# STEP#4: run router, report actual utilization and timing, write checkpoint design, run drc, write verilog and xdc out
+#
+route_design 
+#
+# STEP#5: generate a bitstream
+# 
+write_bitstream -force $outputDir/rv32i_soc.bit
+
+# Connect to the Digilent Cable on localhost:3121
+open_hw_manager
+connect_hw_server -url localhost:3121
+current_hw_target [get_hw_targets */xilinx_tcf/Digilent/210376AC734EA]
+open_hw_target
+
+# Program and Refresh the XC7K325T Device
+
+current_hw_device [lindex [get_hw_devices] 0]
+refresh_hw_device -update_hw_probes false [lindex [get_hw_devices] 0]
+set_property PROGRAM.FILE {./runs/rv32i_soc.bit} [lindex [get_hw_devices] 0]
+
+program_hw_devices [lindex [get_hw_devices] 0]
+refresh_hw_device [lindex [get_hw_devices] 0]
+quit
+
+

AngeloJacobo_RISC-V/rtl/fwb_master.v

@@ -0,0 +1,558 @@
+////////////////////////////////////////////////////////////////////////////////
+//
+// Filename:	fwb_master.v
+// {{{
+// Project:	Zip CPU -- a small, lightweight, RISC CPU soft core
+//
+// Purpose:	This file describes the rules of a wishbone interaction from the
+//		perspective of a wishbone master.  These formal rules may be
+//	used with SymbiYosys to *prove* that the master properly handles
+//	outgoing transactions and incoming responses.
+//
+//	This module contains no functional logic.  It is intended for formal
+//	verification only.  The outputs returned, the number of requests that
+//	have been made, the number of acknowledgements received, and the number
+//	of outstanding requests, are designed for further formal verification
+//	purposes *only*.
+//
+//	This file is different from a companion formal_slave.v file in that the
+//	assertions are made on the outputs of the wishbone master: o_wb_cyc,
+//	o_wb_stb, o_wb_we, o_wb_addr, o_wb_data, and o_wb_sel, while only
+//	assumptions are made about the inputs: i_wb_stall, i_wb_ack, i_wb_data,
+//	i_wb_err.  In the formal_slave.v, assumptions are made about the
+//	slave inputs (the master outputs), and assertions are made about the
+//	slave outputs (the master inputs).
+//
+//	In order to make it easier to compare the slave against the master,
+//	assumptions with respect to the slave have been marked with the
+//	`SLAVE_ASSUME macro.  Similarly, assertions the slave would make have
+//	been marked with `SLAVE_ASSERT.  This allows the master to redefine
+//	these two macros to be from his perspective, and therefore the
+//	diffs between the two files actually show true differences, rather
+//	than just these differences in perspective.
+//
+//
+// Creator:	Dan Gisselquist, Ph.D.
+//		Gisselquist Technology, LLC
+//
+////////////////////////////////////////////////////////////////////////////////
+// }}}
+// Copyright (C) 2017-2023, Gisselquist Technology, LLC
+// {{{
+// This program is free software (firmware): you can redistribute it and/or
+// modify it under the terms of the GNU General Public License as published
+// by the Free Software Foundation, either version 3 of the License, or (at
+// your option) any later version.
+//
+// This program is distributed in the hope that it will be useful, but WITHOUT
+// ANY WARRANTY; without even the implied warranty of MERCHANTIBILITY or
+// FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+// for more details.
+//
+// You should have received a copy of the GNU General Public License along
+// with this program.  (It's in the $(ROOT)/doc directory.  Run make with no
+// target there if the PDF file isn't present.)  If not, see
+// <http://www.gnu.org/licenses/> for a copy.
+// }}}
+// License:	GPL, v3, as defined and found on www.gnu.org,
+// {{{
+//		http://www.gnu.org/licenses/gpl.html
+//
+////////////////////////////////////////////////////////////////////////////////
+//
+//
+`default_nettype none
+// }}}
+module	fwb_master #(
+		// {{{
+		parameter		AW=32, DW=32,
+		parameter		F_MAX_STALL = 0,
+					F_MAX_ACK_DELAY = 0,
+		parameter		F_LGDEPTH = 4,
+		parameter [(F_LGDEPTH-1):0] F_MAX_REQUESTS = 0,
+		// OPT_BUS_ABORT: If true, the master can drop CYC at any time
+		// and must drop CYC following any bus error
+		parameter [0:0]		OPT_BUS_ABORT = 1'b1,
+		//
+		// If true, allow the bus to be kept open when there are no
+		// outstanding requests.  This is useful for any master that
+		// might execute a read modify write cycle, such as an atomic
+		// add.
+		parameter [0:0]		F_OPT_RMW_BUS_OPTION = 1,
+		//
+		//
+		// If true, allow the bus to issue multiple discontinuous
+		// requests.
+		// Unlike F_OPT_RMW_BUS_OPTION, these requests may be issued
+		// while other requests are outstanding
+		parameter	[0:0]	F_OPT_DISCONTINUOUS = 1,
+		//
+		//
+		// If true, insist that there be a minimum of a single clock
+		// delay between request and response.  This defaults to off
+		// since the wishbone specification specifically doesn't
+		// require this.  However, some interfaces do, so we allow it
+		// as an option here.
+		parameter	[0:0]	F_OPT_MINCLOCK_DELAY = 0,
+		//
+		//
+		//
+		localparam [(F_LGDEPTH-1):0] MAX_OUTSTANDING
+						= {(F_LGDEPTH){1'b1}},
+		localparam	MAX_DELAY = (F_MAX_STALL > F_MAX_ACK_DELAY)
+				? F_MAX_STALL : F_MAX_ACK_DELAY,
+		localparam	DLYBITS= (MAX_DELAY < 4) ? 2
+				: (MAX_DELAY >= 65536) ? 32
+				: $clog2(MAX_DELAY+1),
+		//
+		parameter [0:0]		F_OPT_SHORT_CIRCUIT_PROOF = 0,
+		//
+		// If this is the source of a request, then we can assume STB and CYC
+		// will initially start out high.  Master interfaces following the
+		// source on the way to the slave may not have this property
+		parameter [0:0]		F_OPT_SOURCE = 0
+		//
+		//
+		// }}}
+	) (
+		// {{{
+		input	wire			i_clk, i_reset,
+		// The Wishbone bus
+		input	wire			i_wb_cyc, i_wb_stb, i_wb_we,
+		input	wire	[(AW-1):0]	i_wb_addr,
+		input	wire	[(DW-1):0]	i_wb_data,
+		input	wire	[(DW/8-1):0]	i_wb_sel,
+		//
+		input	wire			i_wb_ack,
+		input	wire			i_wb_stall,
+		input	wire	[(DW-1):0]	i_wb_idata,
+		input	wire			i_wb_err,
+		// Some convenience output parameters
+		output	reg	[(F_LGDEPTH-1):0]	f_nreqs, f_nacks,
+		output	wire	[(F_LGDEPTH-1):0]	f_outstanding
+		// }}}
+	);
+
+`define	SLAVE_ASSUME	assert
+`define	SLAVE_ASSERT	assume
+	//
+	// Let's just make sure our parameters are set up right
+	// {{{
+	initial	assert(F_MAX_REQUESTS < {(F_LGDEPTH){1'b1}});
+	// }}}
+
+	// f_request
+	// {{{
+	// Wrap the request line in a bundle.  The top bit, named STB_BIT,
+	// is the bit indicating whether the request described by this vector
+	// is a valid request or not.
+	//
+	localparam	STB_BIT = 2+AW+DW+DW/8-1;
+	wire	[STB_BIT:0]	f_request;
+	assign	f_request = { i_wb_stb, i_wb_we, i_wb_addr, i_wb_data, i_wb_sel };
+	// }}}
+
+	// f_past_valid and i_reset
+	// {{{
+	// A quick register to be used later to know if the $past() operator
+	// will yield valid result
+	reg	f_past_valid;
+	initial	f_past_valid = 1'b0;
+	always @(posedge i_clk)
+		f_past_valid <= 1'b1;
+
+	always @(*)
+	if (!f_past_valid)
+		`SLAVE_ASSUME(i_reset);
+	// }}}
+	////////////////////////////////////////////////////////////////////////
+	//
+	// Assertions regarding the initial (and reset) state
+	// {{{
+	////////////////////////////////////////////////////////////////////////
+	//
+	//
+
+	//
+	// Assume we start from a reset condition
+	initial assert(i_reset);
+	initial `SLAVE_ASSUME(!i_wb_cyc);
+	initial `SLAVE_ASSUME(!i_wb_stb);
+	//
+	initial	`SLAVE_ASSERT(!i_wb_ack);
+	initial	`SLAVE_ASSERT(!i_wb_err);
+
+`ifdef	VERIFIC
+	always @(*)
+	if (!f_past_valid)
+	begin
+		`SLAVE_ASSUME(!i_wb_cyc);
+		`SLAVE_ASSUME(!i_wb_stb);
+		//
+		`SLAVE_ASSERT(!i_wb_ack);
+		`SLAVE_ASSERT(!i_wb_err);
+	end
+`endif
+	always @(posedge i_clk)
+	if ((!f_past_valid)||($past(i_reset)))
+	begin
+		`SLAVE_ASSUME(!i_wb_cyc);
+		`SLAVE_ASSUME(!i_wb_stb);
+		//
+		`SLAVE_ASSERT(!i_wb_ack);
+		`SLAVE_ASSERT(!i_wb_err);
+	end
+
+	always @(*)
+	if (!f_past_valid)
+		`SLAVE_ASSUME(!i_wb_cyc);
+	// }}}
+	////////////////////////////////////////////////////////////////////////
+	//
+	// Bus requests
+	// {{{
+	////////////////////////////////////////////////////////////////////////
+	//
+	//
+
+	// Following any bus error, the CYC line should be dropped to abort
+	// the transaction
+	always @(posedge i_clk)
+	if (f_past_valid && OPT_BUS_ABORT && $past(i_wb_err)&& $past(i_wb_cyc))
+		`SLAVE_ASSUME(!i_wb_cyc);
+
+	always @(*)
+	if (!OPT_BUS_ABORT && !i_reset && (f_nreqs != f_nacks))
+		`SLAVE_ASSUME(i_wb_cyc);
+
+	always @(posedge i_clk)
+	if (f_past_valid && !OPT_BUS_ABORT
+			&& $past(!i_reset && i_wb_stb && i_wb_stall))
+		`SLAVE_ASSUME(i_wb_cyc);
+
+	// STB can only be true if CYC is also true
+	always @(*)
+	if (i_wb_stb)
+		`SLAVE_ASSUME(i_wb_cyc);
+
+	// If a request was both outstanding and stalled on the last clock,
+	// then nothing should change on this clock regarding it.
+	always @(posedge i_clk)
+	if ((f_past_valid)&&(!$past(i_reset))&&($past(i_wb_stb))
+			&&($past(i_wb_stall))&&(i_wb_cyc))
+	begin
+		`SLAVE_ASSUME(i_wb_stb);
+		`SLAVE_ASSUME(i_wb_we   == $past(i_wb_we));
+		`SLAVE_ASSUME(i_wb_addr == $past(i_wb_addr));
+		`SLAVE_ASSUME(i_wb_sel  == $past(i_wb_sel));
+		if (i_wb_we)
+			`SLAVE_ASSUME(i_wb_data == $past(i_wb_data));
+	end
+
+	// Within any series of STB/requests, the direction of the request
+	// may not change.
+	always @(posedge i_clk)
+	if ((f_past_valid)&&($past(i_wb_stb))&&(i_wb_stb))
+		`SLAVE_ASSUME(i_wb_we == $past(i_wb_we));
+
+
+	// Within any given bus cycle, the direction may *only* change when
+	// there are no further outstanding requests.
+	always @(posedge i_clk)
+	if ((f_past_valid)&&(f_outstanding > 0))
+		`SLAVE_ASSUME(i_wb_we == $past(i_wb_we));
+
+	// Write requests must also set one (or more) of i_wb_sel
+	//
+	// This test has been removed since down-sizers (taking bus from width
+	// DW to width dw < DW) might actually create empty requests that this
+	// would prevent.  Re-enabling it would also complicate AXI to WB
+	// transfers, since AXI explicitly allows WSTRB == 0.  Finally, this
+	// criteria isn't found in the WB spec--so while it might be a good
+	// idea to check, in hind sight there are too many exceptions to be
+	// dogmatic about it.
+	//
+	// always @(*)
+	// if ((i_wb_stb)&&(i_wb_we))
+	//	`SLAVE_ASSUME(|i_wb_sel);
+
+	// }}}
+	////////////////////////////////////////////////////////////////////////
+	//
+	// Bus responses
+	// {{{
+	////////////////////////////////////////////////////////////////////////
+	//
+	//
+
+	// If CYC was low on the last clock, then both ACK and ERR should be
+	// low on this clock.
+	always @(posedge i_clk)
+	if ((f_past_valid)&&(!$past(i_wb_cyc))&&(!i_wb_cyc))
+	begin
+		`SLAVE_ASSERT(!i_wb_ack);
+		`SLAVE_ASSERT(!i_wb_err);
+		// Stall may still be true--such as when we are not
+		// selected at some arbiter between us and the slave
+	end
+
+	//
+	// Any time the CYC line drops, it is possible that there may be a
+	// remaining (registered) ACK or ERR that hasn't yet been returned.
+	// Restrict such out of band returns so that they are *only* returned
+	// if there is an outstanding operation.
+	//
+	// Update: As per spec, WB-classic to WB-pipeline conversions require
+	// that the ACK|ERR might come back on the same cycle that STB
+	// is low, yet also be registered.  Hence, if STB & STALL are true on
+	// one cycle, then CYC is dropped, ACK|ERR might still be true on the
+	// cycle when CYC is dropped
+	always @(posedge i_clk)
+	if ((f_past_valid)&&(!$past(i_reset))&&($past(i_wb_cyc))&&(!i_wb_cyc))
+	begin
+		// Note that, unlike f_outstanding, f_nreqs and f_nacks are both
+		// registered.  Hence, we can check here if a response is still
+		// pending.  If not, no response should be returned.
+		if (f_nreqs == f_nacks)
+		begin
+			`SLAVE_ASSERT(!i_wb_ack);
+			`SLAVE_ASSERT(!i_wb_err);
+		end
+	end
+
+	// ACK and ERR may never both be true at the same time
+	always @(*)
+		`SLAVE_ASSERT((!i_wb_ack)||(!i_wb_err));
+	// }}}
+	////////////////////////////////////////////////////////////////////////
+	//
+	// Stall checking
+	// {{{
+	////////////////////////////////////////////////////////////////////////
+	//
+	//
+	generate if (F_MAX_STALL > 0)
+	begin : MXSTALL
+		//
+		// Assume the slave cannnot stall for more than F_MAX_STALL
+		// counts.  We'll count this forward any time STB and STALL
+		// are both true.
+		//
+		reg	[(DLYBITS-1):0]		f_stall_count;
+
+		initial	f_stall_count = 0;
+		always @(posedge i_clk)
+		if ((!i_reset)&&(i_wb_stb)&&(i_wb_stall))
+			f_stall_count <= f_stall_count + 1'b1;
+		else
+			f_stall_count <= 0;
+
+		always @(*)
+		if (i_wb_cyc)
+			`SLAVE_ASSERT(f_stall_count < F_MAX_STALL);
+	end endgenerate
+	// }}}
+	////////////////////////////////////////////////////////////////////////
+	//
+	// Maximum delay in any response
+	// {{{
+	////////////////////////////////////////////////////////////////////////
+	//
+	//
+
+	generate if (F_MAX_ACK_DELAY > 0)
+	begin : MXWAIT
+		//
+		// Assume the slave will respond within F_MAX_ACK_DELAY cycles,
+		// counted either from the end of the last request, or from the
+		// last ACK received
+		//
+		reg	[(DLYBITS-1):0]		f_ackwait_count;
+
+		initial	f_ackwait_count = 0;
+		always @(posedge i_clk)
+		if ((!i_reset)&&(i_wb_cyc)&&(!i_wb_stb)
+				&&(!i_wb_ack)&&(!i_wb_err)
+				&&(f_outstanding > 0))
+			f_ackwait_count <= f_ackwait_count + 1'b1;
+		else
+			f_ackwait_count <= 0;
+
+		always @(*)
+		if ((!i_reset)&&(i_wb_cyc)&&(!i_wb_stb)
+					&&(!i_wb_ack)&&(!i_wb_err)
+					&&(f_outstanding > 0))
+			`SLAVE_ASSERT(f_ackwait_count < F_MAX_ACK_DELAY);
+	end endgenerate
+	// }}}
+	////////////////////////////////////////////////////////////////////////
+	//
+	// Count outstanding requests vs acknowledgments
+	// {{{
+	////////////////////////////////////////////////////////////////////////
+	//
+	//
+
+	// Count the number of requests that have been received
+	//
+	initial	f_nreqs = 0;
+	always @(posedge i_clk)
+	if ((i_reset)||(!i_wb_cyc))
+		f_nreqs <= 0;
+	else if ((i_wb_stb)&&(!i_wb_stall))
+		f_nreqs <= f_nreqs + 1'b1;
+
+
+	//
+	// Count the number of acknowledgements that have been returned
+	//
+	initial	f_nacks = 0;
+	always @(posedge i_clk)
+	if (i_reset)
+		f_nacks <= 0;
+	else if (!i_wb_cyc)
+		f_nacks <= 0;
+	else if ((i_wb_ack)||(i_wb_err))
+		f_nacks <= f_nacks + 1'b1;
+
+	//
+	// The number of outstanding requests is the difference between
+	// the number of requests and the number of acknowledgements
+	//
+	assign	f_outstanding = (i_wb_cyc) ? (f_nreqs - f_nacks):0;
+
+	always @(*)
+	if ((i_wb_cyc)&&(F_MAX_REQUESTS > 0))
+	begin
+		if (i_wb_stb)
+		begin
+			`SLAVE_ASSUME(f_nreqs < F_MAX_REQUESTS);
+		end else
+			`SLAVE_ASSUME(f_nreqs <= F_MAX_REQUESTS);
+		`SLAVE_ASSERT(f_nacks <= f_nreqs);
+		assert(f_outstanding < MAX_OUTSTANDING);
+	end else
+		assume(f_outstanding < MAX_OUTSTANDING);
+
+	always @(*)
+	if ((i_wb_cyc)&&(f_outstanding == 0))
+	begin
+		// If nothing is outstanding, then there should be
+		// no acknowledgements ... however, an acknowledgement
+		// *can* come back on the same clock as the stb is
+		// going out.
+		if (F_OPT_MINCLOCK_DELAY)
+		begin
+			`SLAVE_ASSERT(!i_wb_ack);
+			`SLAVE_ASSERT(!i_wb_err);
+		end else begin
+			`SLAVE_ASSERT((!i_wb_ack)||((i_wb_stb)&&(!i_wb_stall)));
+			// The same is true of errors.  They may not be
+			// created before the request gets through
+			`SLAVE_ASSERT((!i_wb_err)||((i_wb_stb)&&(!i_wb_stall)));
+		end
+	end else if (!i_wb_cyc && f_nacks == f_nreqs)
+	begin
+		`SLAVE_ASSERT(!i_wb_ack);
+		`SLAVE_ASSERT(!i_wb_err);
+	end
+	// }}}
+	////////////////////////////////////////////////////////////////////////
+	//
+	// Bus direction
+	// {{{
+	////////////////////////////////////////////////////////////////////////
+	//
+	//
+	generate if (!F_OPT_RMW_BUS_OPTION)
+	begin
+		// If we aren't waiting for anything, and we aren't issuing
+		// any requests, then then our transaction is over and we
+		// should be dropping the CYC line.
+		always @(*)
+		if (f_outstanding == 0)
+			`SLAVE_ASSUME((i_wb_stb)||(!i_wb_cyc));
+		// Not all masters will abide by this restriction.  Some
+		// masters may wish to implement read-modify-write bus
+		// interactions.  These masters need to keep CYC high between
+		// transactions, even though nothing is outstanding.  For
+		// these busses, turn F_OPT_RMW_BUS_OPTION on.
+	end endgenerate
+	// }}}
+	////////////////////////////////////////////////////////////////////////
+	//
+	// Discontinuous request checking
+	// {{{
+	////////////////////////////////////////////////////////////////////////
+	//
+	//
+
+	generate if ((!F_OPT_DISCONTINUOUS)&&(!F_OPT_RMW_BUS_OPTION))
+	begin : INSIST_ON_NO_DISCONTINUOUS_STBS
+		// Within my own code, once a request begins it goes to
+		// completion and the CYC line is dropped.  The master
+		// is not allowed to raise STB again after dropping it.
+		// Doing so would be a *discontinuous* request.
+		//
+		// However, in any RMW scheme, discontinuous requests are
+		// necessary, and the spec doesn't disallow them.  Hence we
+		// make this check optional.
+		always @(posedge i_clk)
+		if ((f_past_valid)&&($past(i_wb_cyc))&&(!$past(i_wb_stb)))
+			`SLAVE_ASSUME(!i_wb_stb);
+	end endgenerate
+	// }}}
+	////////////////////////////////////////////////////////////////////////
+	//
+	// Master only checks
+	// {{{
+	////////////////////////////////////////////////////////////////////////
+	//
+	//
+
+	generate if (F_OPT_SHORT_CIRCUIT_PROOF)
+	begin
+		// In many ways, we don't care what happens on the bus return
+		// lines if the cycle line is low, so restricting them to a
+		// known value makes a lot of sense.
+		//
+		// On the other hand, if something above *does* depend upon
+		// these values (when it shouldn't), then we might want to know
+		// about it.
+		//
+		//
+		always @(posedge i_clk)
+		begin
+			if (!i_wb_cyc)
+			begin
+				assume(!i_wb_stall);
+				assume($stable(i_wb_idata));
+			end else if ((!$past(i_wb_ack))&&(!i_wb_ack))
+				assume($stable(i_wb_idata));
+		end
+	end endgenerate
+
+	generate if (F_OPT_SOURCE)
+	begin : SRC
+		// Any opening bus request starts with both CYC and STB high
+		// This is true for the master only, and more specifically
+		// only for those masters that are the initial source of any
+		// transaction.  By the time an interaction gets to the slave,
+		// the CYC line may go high or low without actually affecting
+		// the STB line of the slave.
+		always @(posedge i_clk)
+		if ((f_past_valid)&&(!$past(i_wb_cyc))&&(i_wb_cyc))
+			`SLAVE_ASSUME(i_wb_stb);
+	end endgenerate
+	// }}}
+
+	// Keep Verilator happy
+	// {{{
+	// Verilator lint_off UNUSED
+	wire	unused;
+	assign	unused = &{ 1'b0, f_request };
+	// Verilator lint_on  UNUSED
+	// }}}
+endmodule
+`undef	SLAVE_ASSUME
+`undef	SLAVE_ASSERT

AngeloJacobo_RISC-V/rtl/rv32i_alu.v

@@ -0,0 +1,234 @@
+/* The rv32i_alu module serves as the Arithmetic Logic Unit (ALU) for the RISC-V core 
+during the execute stage of the pipeline. The ALU is responsible for executing arithmetic, 
+logic, and comparison operations based on the instruction and operands provided. This
+module is a crucial part of the RISC-V core, as it processes the instructions and computes 
+the results required for program execution. Function includes:
+ - Operand Selection: The module first selects the appropriate operands for the ALU operation 
+    depending on the opcode. Operand A can be the program counter (PC) or the value of the 
+    first source register (rs1), while operand B can be either the second source register 
+    (rs2) or an immediate value.
+ - ALU Operation: The ALU performs various operations, such as ADD, SUB, SLT, SLTU, XOR, OR, 
+    AND, SLL, SRL, SRA, EQ, NEQ, GE, and GEU, depending on the instruction type. The result 
+    of the ALU operation is stored in the y_d register.
+- Handling Branches and Jumps: The module computes the next PC value based on the instruction 
+    type (e.g., branch, jump, or jump-and-link). It also generates the o_change_pc signal to 
+    indicate whether the PC needs to jump to a new address.
+- Register Writeback: The module computes the value to be written back to the destination 
+    register (rd) and sets the appropriate control signals (o_wr_rd and o_rd_valid) based on
+    the instruction type. For example, it disables writing to the destination register for 
+    branch or store instructions.
+ - Stalling and Flushing: The ALU manages stalling and flushing of the pipeline. It generates 
+    the o_stall_from_alu signal to stall the memory-access stage for load/store instructions 
+    since accessing data memory may take multiple cycles. It also handles pipeline stalls 
+    and flushes based on the input signals (i_stall, i_force_stall, and i_flush).
+*/
+
+
+`timescale 1ns / 1ps
+`default_nettype none
+`include "rv32i_header.vh"
+
+module rv32i_alu(
+    input wire i_clk,i_rst_n,
+    input wire[`ALU_WIDTH-1:0] i_alu, //alu operation type from previous stage
+    input wire[4:0] i_rs1_addr, //address for register source 1
+    output reg[4:0] o_rs1_addr, //address for register source 1
+    input wire[31:0] i_rs1, //Source register 1 value
+    output reg[31:0] o_rs1, //Source register 1 value
+    input wire[31:0] i_rs2, //Source register 2 value
+    output reg[31:0] o_rs2, //Source register 2 value
+    input wire[31:0] i_imm, //Immediate value from previous stage
+    output reg[11:0] o_imm, //Immediate value
+    input wire[2:0] i_funct3, //function type from previous stage
+    output reg[2:0] o_funct3, // function type
+    input wire[`OPCODE_WIDTH-1:0] i_opcode, //opcode type from previous stage
+    output reg[`OPCODE_WIDTH-1:0] o_opcode, //opcode type 
+    input wire[`EXCEPTION_WIDTH-1:0] i_exception, //exception from decoder stage
+    output reg[`EXCEPTION_WIDTH-1:0] o_exception, //exception: illegal inst,ecall,ebreak,mret
+    output reg[31:0] o_y, //result of arithmetic operation
+    // PC Control
+    input wire[31:0] i_pc, //Program Counter
+    output reg[31:0] o_pc, //pc register in pipeline
+    output reg[31:0] o_next_pc, //new pc value
+    output reg o_change_pc, //high if PC needs to jump
+    // Basereg Control
+    output reg o_wr_rd, //write rd to the base reg if enabled
+    input wire[4:0] i_rd_addr, //address for destination register (from previous stage)
+    output reg[4:0] o_rd_addr, //address for destination register
+    output reg[31:0] o_rd, //value to be written back to destination register
+    output reg o_rd_valid, //high if o_rd is valid (not load nor csr instruction)
+    /// Pipeline Control ///
+    output reg o_stall_from_alu, //prepare to stall next stage(memory-access stage) for load/store instruction
+    input wire i_ce, // input clk enable for pipeline stalling of this stage
+    output reg o_ce, // output clk enable for pipeline stalling of next stage
+    input wire i_stall, //informs this stage to stall
+    input wire i_force_stall, //force this stage to stall
+    output reg o_stall, //informs pipeline to stall
+    input wire i_flush, //flush this stage
+    output reg o_flush //flush previous stages
+);
+
+    wire alu_add = i_alu[`ADD];
+    wire alu_sub = i_alu[`SUB];
+    wire alu_slt = i_alu[`SLT];
+    wire alu_sltu = i_alu[`SLTU];
+    wire alu_xor = i_alu[`XOR];
+    wire alu_or = i_alu[`OR];
+    wire alu_and = i_alu[`AND];
+    wire alu_sll = i_alu[`SLL];
+    wire alu_srl = i_alu[`SRL];
+    wire alu_sra = i_alu[`SRA];
+    wire alu_eq = i_alu[`EQ];
+    wire alu_neq = i_alu[`NEQ];
+    wire alu_ge = i_alu[`GE];
+    wire alu_geu = i_alu[`GEU];
+    wire opcode_rtype = i_opcode[`RTYPE];
+    wire opcode_itype = i_opcode[`ITYPE];
+    wire opcode_load = i_opcode[`LOAD];
+    wire opcode_store = i_opcode[`STORE];
+    wire opcode_branch = i_opcode[`BRANCH];
+    wire opcode_jal = i_opcode[`JAL];
+    wire opcode_jalr = i_opcode[`JALR];
+    wire opcode_lui = i_opcode[`LUI];
+    wire opcode_auipc = i_opcode[`AUIPC];
+    wire opcode_system = i_opcode[`SYSTEM];
+    wire opcode_fence = i_opcode[`FENCE];
+
+    reg[31:0] a; //operand A
+    reg[31:0] b; //operand B
+    reg[31:0] y_d; //ALU output
+    reg[31:0] rd_d; //next value to be written back to destination register
+    reg wr_rd_d; //write rd to basereg if enabled
+    reg rd_valid_d; //high if rd is valid (not load nor csr instruction)
+    reg[31:0] a_pc;
+    wire[31:0] sum;
+    wire stall_bit = o_stall || i_stall;
+
+    //register the output of i_alu
+    always @(posedge i_clk, negedge i_rst_n) begin
+        if(!i_rst_n) begin
+            o_exception <= 0;
+            o_ce <= 0;
+            o_stall_from_alu <= 0;
+        end
+        else begin
+            if(i_ce && !stall_bit) begin //update register only if this stage is enabled
+                o_opcode <= i_opcode;
+                o_exception <= i_exception;
+                o_y <= y_d; 
+                o_rs1_addr <= i_rs1_addr;
+                o_rs1 <= i_rs1;
+                o_rs2 <= i_rs2;
+                o_rd_addr <= i_rd_addr;
+                o_imm <= i_imm[11:0];
+                o_funct3 <= i_funct3;
+                o_rd <= rd_d;
+                o_rd_valid <= rd_valid_d;
+                o_wr_rd <= wr_rd_d;
+                o_stall_from_alu <= i_opcode[`STORE] || i_opcode[`LOAD]; //stall next stage(memory-access stage) when need to store/load 
+                o_pc <= i_pc;                                               //since accessing data memory always takes more than 1 cycle
+            end
+            if(i_flush && !stall_bit) begin //flush this stage so clock-enable of next stage is disabled at next clock cycle
+                o_ce <= 0;
+            end
+            else if(!stall_bit) begin //clock-enable will change only when not stalled
+                o_ce <= i_ce;
+            end
+            else if(stall_bit && !i_stall) o_ce <= 0; //if this stage is stalled but next stage is not, disable 
+                                                                    //clock enable of next stage at next clock cycle (pipeline bubble)
+        end
+        
+    end 
+
+    // determine operation used then compute for y output
+    always @* begin  
+        y_d = 0;
+        
+        a = (opcode_jal || opcode_auipc)? i_pc:i_rs1;  // a can either be pc or rs1
+        b = (opcode_rtype || opcode_branch)? i_rs2:i_imm; // b can either be rs2 or imm 
+        
+        if(alu_add) y_d = a + b;
+        if(alu_sub) y_d = a - b;
+        if(alu_slt || alu_sltu) begin
+            y_d = {31'b0, (a < b)};
+            if(alu_slt) y_d = (a[31] ^ b[31])? {31'b0,a[31]}:y_d;
+        end 
+        if(alu_xor) y_d = a ^ b;
+        if(alu_or)  y_d = a | b;
+        if(alu_and) y_d = a & b;
+        if(alu_sll) y_d = a << b[4:0];
+        if(alu_srl) y_d = a >> b[4:0];
+        if(alu_sra) y_d = $signed(a) >>> b[4:0];
+        if(alu_eq || alu_neq) begin
+            y_d = {31'b0, (a == b)};
+            if(alu_neq) y_d = {31'b0,!y_d[0]};
+        end
+        if(alu_ge || alu_geu) begin
+            y_d = {31'b0, (a >= b)};
+            if(alu_ge) y_d = (a[31] ^ b[31])? {31'b0, b[31]}:y_d;
+        end
+    end
+
+    
+    //determine o_rd to be saved to baseg and next value of PC
+    always @* begin
+        o_flush = i_flush; //flush this stage along with the previous stages
+        rd_d = 0;
+        rd_valid_d = 0;
+        o_change_pc = 0;
+        o_next_pc = 0;
+        wr_rd_d = 0;
+        a_pc = i_pc;
+        if(!i_flush) begin
+            if(opcode_rtype || opcode_itype) rd_d = y_d;
+            if(opcode_branch && y_d[0]) begin
+                    o_next_pc = sum; //branch iff value of ALU is 1(true)
+                    o_change_pc = i_ce; //change PC when ce of this stage is high (o_change_pc is valid)
+                    o_flush = i_ce;
+            end
+            if(opcode_jal || opcode_jalr) begin
+                if(opcode_jalr) a_pc = i_rs1;
+                o_next_pc = sum; //jump to new PC
+                o_change_pc = i_ce; //change PC when ce of this stage is high (o_change_pc is valid)
+                o_flush = i_ce;
+                rd_d = i_pc + 4; //register the next pc value to destination register
+            end 
+        end
+        if(opcode_lui) rd_d = i_imm;
+        if(opcode_auipc) rd_d = sum;
+
+        if(opcode_branch || opcode_store || (opcode_system && i_funct3 == 0) || opcode_fence ) wr_rd_d = 0; //i_funct3==0 are the non-csr system instructions 
+        else wr_rd_d = 1; //always write to the destination reg except when instruction is BRANCH or STORE or SYSTEM(except CSR system instruction)  
+
+        if(opcode_load || (opcode_system && i_funct3!=0)) rd_valid_d = 0;  //value of o_rd for load and CSR write is not yet available at this stage
+        else rd_valid_d = 1;
+
+        //stall logic (stall when upper stages are stalled, when forced to stall, or when needs to flush previous stages but are still stalled)
+        o_stall = (i_stall || i_force_stall) && !i_flush; //stall when alu needs wait time
+    end
+        
+    assign sum = a_pc + i_imm; //share adder for all addition operation for less resource utilization
+
+    `ifdef FORMAL
+        // assumption on inputs(not more than one opcode and alu operation is high)
+        wire[4:0] f_alu=i_alu[`ADD]+i_alu[`SUB]+i_alu[`SLT]+i_alu[`SLTU]+i_alu[`XOR]+i_alu[`OR]+i_alu[`AND]+i_alu[`SLL]+i_alu[`SRL]+i_alu[`SRA]+i_alu[`EQ]+i_alu[`NEQ]+i_alu[`GE]+i_alu[`GEU]+0;
+        wire[4:0] f_opcode=i_opcode[`RTYPE]+i_opcode[`ITYPE]+i_opcode[`LOAD]+i_opcode[`STORE]+i_opcode[`BRANCH]+i_opcode[`JAL]+i_opcode[`JALR]+i_opcode[`LUI]+i_opcode[`AUIPC]+i_opcode[`SYSTEM]+i_opcode[`FENCE];
+
+        always @* begin
+            assume(f_alu <= 1);
+            assume(f_opcode <= 1);
+        end
+
+        // verify all operations with $signed/$unsigned distinctions
+        always @* begin 
+            if(i_alu[`SLTU]) assert(y_d[0] == $unsigned(a) < $unsigned(b));
+            if(i_alu[`SLT]) assert(y_d[0] == $signed(a) < $signed(b));
+            if(i_alu[`SLL]) assert($unsigned(y_d) == $unsigned(a) << $unsigned(b[4:0]));
+            if(i_alu[`SRL]) assert($unsigned(y_d) == $unsigned(a) >> $unsigned(b[4:0]));
+            if(i_alu[`SRA]) assert($signed(y_d) == ($signed(a) >>> $unsigned(b[4:0])));
+            if(i_alu[`GEU]) assert(y_d[0] == ($unsigned(a) >= $unsigned(b)));
+            if(i_alu[`GE]) assert(y_d[0] == ($signed(a) >= $signed(b)));
+        end
+        
+    `endif
+endmodule

AngeloJacobo_RISC-V/rtl/rv32i_basereg.v

@@ -0,0 +1,38 @@
+//regfile controller for the 32 integer base registers
+
+`timescale 1ns / 1ps
+`default_nettype none
+
+module rv32i_basereg
+    (
+        input wire i_clk,
+        input wire i_ce_read, //clock enable for reading from basereg [STAGE 2]
+        input wire[4:0] i_rs1_addr, //source register 1 address
+        input wire[4:0] i_rs2_addr, //source register 2 address
+        input wire[4:0] i_rd_addr, //destination register address
+        input wire[31:0] i_rd, //data to be written to destination register
+        input wire i_wr, //write enable
+        output wire[31:0] o_rs1, //source register 1 value
+        output wire[31:0] o_rs2 //source register 2 value
+    );
+    
+    reg[4:0] rs1_addr_q, rs2_addr_q;
+    reg[31:0] base_regfile[31:1]; //base register file (base_regfile[0] is hardwired to zero)
+    wire write_to_basereg;
+    
+    always @(posedge i_clk) begin
+        if(write_to_basereg) begin //only write to register if stage 5 is previously enabled (output of stage 5[WRITEBACK] is registered so delayed by 1 clk)
+           base_regfile[i_rd_addr] <= i_rd; //synchronous write
+        end
+        if(i_ce_read) begin //only read the register if stage 2 is enabled [DECODE]
+            rs1_addr_q <= i_rs1_addr; //synchronous read
+            rs2_addr_q <= i_rs2_addr; //synchronous read
+        end
+    end
+    
+    assign write_to_basereg = i_wr && i_rd_addr!=0; //no need to write to basereg 0 (hardwired to zero) 
+    assign o_rs1 = rs1_addr_q==0? 0: base_regfile[rs1_addr_q]; // if regfile is about to be written at the same time we read it
+    assign o_rs2 = rs2_addr_q==0? 0: base_regfile[rs2_addr_q];    //then return the next value to be written to that address
+    
+endmodule
+

AngeloJacobo_RISC-V/rtl/rv32i_core.v

@@ -0,0 +1,626 @@
+/* The rv32i_core module represents the top module for an RV32I RISC-V processor 
+core. The module is structured around a 5-stage pipeline architecture, which 
+includes Fetch, Decode, Execute, Memory Access, and Writeback stages. The RV32I 
+core is designed to interface with separate instruction and data memories, and 
+supports external, software, and timer interrupts. The module contains several 
+sub-modules that carry out various functions within the processor:
+ - rv32i_forwarding: This sub-module is responsible for handling operand
+    forwarding. It ensures that the correct operand values are used in the ALU 
+    stage, even when they have not yet been written back to the register file.
+    Operand forwarding helps to reduce pipeline stalls caused by data 
+    dependencies.
+ - rv32i_basereg: This sub-module serves as a controller for the 32 integer 
+    base registers. It manages reading from and writing to the register file, 
+    with read operations occurring during the Decode stage and write operations 
+    during the Writeback stage.
+ - rv32i_fetch: This sub-module is responsible for fetching instructions from
+    the instruction memory. It generates the instruction address, retrieves 
+    the instruction, and controls the program counter (PC). It also manages 
+    the pipeline stall and flush signals for the Fetch stage.
+ - rv32i_decoder: This sub-module takes care of decoding the fetched 32-bit
+    instruction. It extracts various fields from the instruction, such as opcode,
+    function type, immediate value, and register addresses. The sub-module also 
+    detects exceptions, manages pipeline stall and flush signals for the Decode 
+    stage, and provides a clock enable signal for the next stage.
+ - rv32i_alu: This sub-module is the Arithmetic Logic Unit (ALU) of the core.
+    It performs arithmetic and logical operations based on the opcode and 
+    function type provided by the decoder. It also controls the program counter
+    for branches and jumps, manages register write enable signals, and handles 
+    pipeline stall and flush signals for the Execute stage.
+ - rv32i_memoryaccess: This sub-module controls data memory access for load and 
+    store operations. It computes the memory address based on the ALU output 
+    and provides the appropriate signals for reading from or writing to the data
+    memory. The sub-module also manages pipeline stall and flush signals for 
+    the Memory Access stage.
+ - rv32i_writeback: This sub-module is responsible for writing the results of ALU 
+    and load operations back to the register file. It also manages the program 
+    counter for returning from traps and provides clock enable signals for the 
+    Writeback stage.
+ - rv32i_csr: This sub-module manages the Control and Status Registers (CSRs) in 
+    the core. It handles traps and exceptions, updates CSR values, and controls 
+    the program counter for trap handling.
+*/
+
+`timescale 1ns / 1ps
+`default_nettype none
+`include "rv32i_header.vh"
+
+module rv32i_core #(parameter PC_RESET = 32'h00_00_00_00, TRAP_ADDRESS = 0, ZICSR_EXTENSION = 1) ( 
+    input wire i_clk, i_rst_n,
+    //Instruction Memory Interface (32 bit rom)
+    input wire[31:0] i_inst, //32-bit instruction
+    output wire[31:0] o_iaddr, //address of instruction 
+    output wire o_stb_inst, //request for read access to instruction memory
+    input wire i_ack_inst, //ack (high if new instruction is ready)
+    //Data Memory Interface (32 bit ram)
+    output wire o_wb_cyc_data, //bus cycle active (1 = normal operation, 0 = all ongoing transaction are to be cancelled)
+    output wire o_wb_stb_data, //request for read/write access to data memory
+    output wire o_wb_we_data, //write-enable (1 = write, 0 = read)
+    output wire[31:0] o_wb_addr_data, //address of data memory for store/load
+    output wire[31:0] o_wb_data_data, //data to be stored to memory
+    output wire[3:0] o_wb_sel_data, //byte strobe for write (1 = write the byte) {byte3,byte2,byte1,byte0}
+    input wire i_wb_ack_data, //ack by data memory (high when read data is ready or when write data is already written)
+    input wire i_wb_stall_data, //stall by data memory 
+    input wire[31:0] i_wb_data_data, //data retrieve from memory
+    //Interrupts
+    input wire i_external_interrupt, //interrupt from external source
+    input wire i_software_interrupt, //interrupt from software (inter-processor interrupt)
+    input wire i_timer_interrupt //interrupt from timer
+);
+    
+   
+    //wires for basereg
+    wire[31:0] rs1_orig,rs2_orig;   
+    wire[31:0] rs1,rs2;  
+    wire ce_read;
+
+    //wires for rv32i_fetch
+     wire[31:0] fetch_pc;
+     wire[31:0] fetch_inst;
+
+    //wires for rv32i_decoder
+    wire[`ALU_WIDTH-1:0] decoder_alu;
+    wire[`OPCODE_WIDTH-1:0] decoder_opcode;
+    wire[31:0] decoder_pc;
+    wire[4:0] decoder_rs1_addr, decoder_rs2_addr;
+    wire[4:0] decoder_rs1_addr_q, decoder_rs2_addr_q;
+    wire[4:0] decoder_rd_addr; 
+    wire[31:0] decoder_imm; 
+    wire[2:0] decoder_funct3;
+    wire[`EXCEPTION_WIDTH-1:0] decoder_exception;
+    wire decoder_ce;
+    wire decoder_flush;
+
+    //wires for rv32i_alu
+    wire[`OPCODE_WIDTH-1:0] alu_opcode;
+    wire[4:0] alu_rs1_addr;
+    wire[31:0] alu_rs1;
+    wire[31:0] alu_rs2;
+    wire[11:0] alu_imm;
+    wire[2:0] alu_funct3;
+    wire[31:0] alu_y;
+    wire[31:0] alu_pc;
+    wire[31:0] alu_next_pc;
+    wire alu_change_pc;
+    wire alu_wr_rd;
+    wire[4:0] alu_rd_addr;
+    wire[31:0] alu_rd;
+    wire alu_rd_valid;
+    wire[`EXCEPTION_WIDTH-1:0] alu_exception;
+    wire alu_ce;
+    wire alu_flush;
+    wire alu_force_stall;
+
+    //wires for rv32i_memoryaccess
+    wire[`OPCODE_WIDTH-1:0] memoryaccess_opcode;
+    wire[2:0] memoryaccess_funct3;
+    wire[31:0] memoryaccess_pc;
+    wire memoryaccess_wr_rd;
+    wire[4:0] memoryaccess_rd_addr;
+    wire[31:0] memoryaccess_rd;
+    wire[31:0] memoryaccess_data_load;
+    wire memoryaccess_wr_mem;
+    wire memoryaccess_ce;
+    wire memoryaccess_flush;
+    wire o_stall_from_alu;
+    //wires for rv32i_writeback
+    wire writeback_wr_rd; 
+    wire[4:0] writeback_rd_addr; 
+    wire[31:0] writeback_rd;
+    wire[31:0] writeback_next_pc;
+    wire writeback_change_pc;
+    wire writeback_ce;
+    wire writeback_flush;
+
+    //wires for rv32i_csr
+    wire[31:0] csr_out; //CSR value to be stored to basereg
+    wire[31:0] csr_return_address; //mepc CSR
+    wire[31:0] csr_trap_address; //mtvec CSR
+    wire csr_go_to_trap; //high before going to trap (if exception/interrupt detected)
+    wire csr_return_from_trap; //high before returning from trap (via mret)
+    
+    wire stall_decoder,
+         stall_alu,
+         stall_memoryaccess,
+         stall_writeback; //control stall of each pipeline stages
+    assign ce_read = decoder_ce && !stall_decoder; //reads basereg only decoder is not stalled 
+
+    //module instantiations
+    rv32i_forwarding operand_forwarding ( //logic for operand forwarding
+        .i_rs1_orig(rs1_orig), //current rs1 value saved in basereg
+        .i_rs2_orig(rs2_orig), //current rs2 value saved in basereg
+        .i_decoder_rs1_addr_q(decoder_rs1_addr_q), //address of operand rs1 used in ALU stage
+        .i_decoder_rs2_addr_q(decoder_rs2_addr_q), //address of operand rs2 used in ALU stage
+        .o_alu_force_stall(alu_force_stall), //high to force ALU stage to stall
+        .o_rs1(rs1), //rs1 value with Operand Forwarding
+        .o_rs2(rs2), //rs2 value with Operand Forwarding
+        // Stage 4 [MEMORYACCESS]
+        .i_alu_rd_addr(alu_rd_addr), //destination register address
+        .i_alu_wr_rd(alu_wr_rd), //high if rd_addr will be written
+        .i_alu_rd_valid(alu_rd_valid), //high if rd is already valid at this stage (not LOAD nor CSR instruction)
+        .i_alu_rd(alu_rd), //rd value in stage 4
+        .i_memoryaccess_ce(memoryaccess_ce), //high if stage 4 is enabled
+        // Stage 5 [WRITEBACK]
+        .i_memoryaccess_rd_addr(memoryaccess_rd_addr), //destination register address
+        .i_memoryaccess_wr_rd(memoryaccess_wr_rd), //high if rd_addr will be written
+        .i_writeback_rd(writeback_rd), //rd value in stage 5
+        .i_writeback_ce(writeback_ce) //high if stage 4 is enabled
+    );
+
+    rv32i_basereg m0( //regfile controller for the 32 integer base registers
+        .i_clk(i_clk),
+        .i_ce_read(ce_read), //clock enable for reading from basereg [STAGE 2]
+        .i_rs1_addr(decoder_rs1_addr), //source register 1 address
+        .i_rs2_addr(decoder_rs2_addr), //source register 2 address
+        .i_rd_addr(writeback_rd_addr), //destination register address
+        .i_rd(writeback_rd), //data to be written to destination register
+        .i_wr(writeback_wr_rd), //write enable
+        .o_rs1(rs1_orig), //source register 1 value
+        .o_rs2(rs2_orig) //source register 2 value
+    );
+    
+    rv32i_fetch #(.PC_RESET(PC_RESET)) m1( // logic for fetching instruction [FETCH STAGE , STAGE 1]
+        .i_clk(i_clk),
+        .i_rst_n(i_rst_n),
+        .o_iaddr(o_iaddr), //Instruction address
+        .o_pc(fetch_pc), //PC value of o_inst
+        .i_inst(i_inst), // retrieved instruction from Memory
+        .o_inst(fetch_inst), // instruction
+        .o_stb_inst(o_stb_inst), // request for instruction
+        .i_ack_inst(i_ack_inst), //ack (high if new instruction is ready)
+        // PC Control
+        .i_writeback_change_pc(writeback_change_pc), //high when PC needs to change when going to trap or returning from trap
+        .i_writeback_next_pc(writeback_next_pc), //next PC due to trap
+        .i_alu_change_pc(alu_change_pc), //high when PC needs to change for taken branches and jumps
+        .i_alu_next_pc(alu_next_pc), //next PC due to branch or jump
+        /// Pipeline Control ///
+        .o_ce(decoder_ce), // output clk enable for pipeline stalling of next stage
+        .i_stall((stall_decoder || stall_alu || stall_memoryaccess || stall_writeback)), //informs this stage to stall
+        .i_flush(decoder_flush) //flush this stage
+    ); 
+  
+    rv32i_decoder m2( //logic for the decoding of the 32 bit instruction [DECODE STAGE , STAGE 2]
+        .i_clk(i_clk),
+        .i_rst_n(i_rst_n),
+        .i_inst(fetch_inst), //32 bit instruction
+        .i_pc(fetch_pc), //PC value from fetch stage
+        .o_pc(decoder_pc), //PC value
+        .o_rs1_addr(decoder_rs1_addr),// address for register source 1
+        .o_rs1_addr_q(decoder_rs1_addr_q), // registered address for register source 1
+        .o_rs2_addr(decoder_rs2_addr), // address for register source 2
+        .o_rs2_addr_q(decoder_rs2_addr_q), // registered address for register source 2
+        .o_rd_addr(decoder_rd_addr), // address for destination register
+        .o_imm(decoder_imm), // extended value for immediate
+        .o_funct3(decoder_funct3), // function type
+        .o_alu(decoder_alu), //alu operation type
+        .o_opcode(decoder_opcode), //opcode type
+        .o_exception(decoder_exception), //exceptions: illegal inst, ecall, ebreak, mret
+         /// Pipeline Control ///
+        .i_ce(decoder_ce), // input clk enable for pipeline stalling of this stage
+        .o_ce(alu_ce), // output clk enable for pipeline stalling of next stage
+        .i_stall((stall_alu || stall_memoryaccess || stall_writeback)), //informs this stage to stall
+        .o_stall(stall_decoder), //informs pipeline to stall
+        .i_flush(alu_flush), //flush this stage
+        .o_flush(decoder_flush) //flushes previous stages
+    );
+
+    rv32i_alu m3( //ALU combinational logic [EXECUTE STAGE , STAGE 3]
+        .i_clk(i_clk),
+        .i_rst_n(i_rst_n),
+        .i_alu(decoder_alu), //alu operation type
+        .i_rs1_addr(decoder_rs1_addr_q), //address for register source 1
+        .o_rs1_addr(alu_rs1_addr), //address for register source 1
+        .i_rs1(rs1), //Source register 1 value
+        .o_rs1(alu_rs1), //Source register 1 value
+        .i_rs2(rs2), //Source Register 2 value
+        .o_rs2(alu_rs2), //Source Register 2 value
+        .i_imm(decoder_imm), //Immediate value from previous stage
+        .o_imm(alu_imm), //Immediate value
+        .i_funct3(decoder_funct3), //function type from decoder stage
+        .o_funct3(alu_funct3), //function type
+        .i_opcode(decoder_opcode), //opcode type from previous stage
+        .o_opcode(alu_opcode), //opcode type
+        .i_exception(decoder_exception), //exception from decoder stage
+        .o_exception(alu_exception), //exception: illegal inst,ecall,ebreak,mret
+        .o_y(alu_y), //result of arithmetic operation
+        // PC Control
+        .i_pc(decoder_pc), //pc from decoder stage
+        .o_pc(alu_pc), // current pc 
+        .o_next_pc(alu_next_pc), //next pc 
+        .o_change_pc(alu_change_pc), //change pc if high
+        // Basereg Control
+        .o_wr_rd(alu_wr_rd), //write rd to basereg if enabled
+        .i_rd_addr(decoder_rd_addr), //address for destination register (from previous stage)
+        .o_rd_addr(alu_rd_addr), //address for destination register
+        .o_rd(alu_rd), //value to be written back to destination register
+        .o_rd_valid(alu_rd_valid), //high if o_rd is valid (not load nor csr instruction)
+         /// Pipeline Control ///
+        .o_stall_from_alu(o_stall_from_alu), //prepare to stall next stage(memory-access stage) for load/store instruction
+        .i_ce(alu_ce), // input clk enable for pipeline stalling of this stage
+        .o_ce(memoryaccess_ce), // output clk enable for pipeline stalling of next stage
+        .i_stall((stall_memoryaccess || stall_writeback)), //informs this stage to stall
+        .i_force_stall(alu_force_stall), //force this stage to stall
+        .o_stall(stall_alu), //informs pipeline to stall
+        .i_flush(memoryaccess_flush), //flush this stage
+        .o_flush(alu_flush) //flushes previous stages
+    );
+    
+    rv32i_memoryaccess m4( //logic controller for data memory access (load/store) [MEMORY STAGE , STAGE 4]
+        .i_clk(i_clk),
+        .i_rst_n(i_rst_n),
+        .i_rs2(alu_rs2), //data to be stored to memory is always rs2
+        .i_y(alu_y), //y value from ALU (address of data to memory be stored or loaded)
+        .i_funct3(alu_funct3), //funct3 from previous stage
+        .o_funct3(memoryaccess_funct3), //funct3 (byte,halfword,word)
+        .i_opcode(alu_opcode), //opcode type from previous stage
+        .o_opcode(memoryaccess_opcode), //opcode type
+        .i_pc(alu_pc), //PC from previous stage
+        .o_pc(memoryaccess_pc), //PC value
+        // Basereg Control
+        .i_wr_rd(alu_wr_rd), //write rd to base reg is enabled (from memoryaccess stage)
+        .o_wr_rd(memoryaccess_wr_rd), //write rd to the base reg if enabled
+        .i_rd_addr(alu_rd_addr), //address for destination register (from previous stage)
+        .o_rd_addr(memoryaccess_rd_addr), //address for destination register
+        .i_rd(alu_rd), //value to be written back to destination reg
+        .o_rd(memoryaccess_rd), //value to be written back to destination register
+        // Data Memory Control
+        .o_wb_cyc_data(o_wb_cyc_data), //bus cycle active (1 = normal operation, 0 = all ongoing transaction are to be cancelled)
+        .o_wb_stb_data(o_wb_stb_data), //request for read/write access to data memory
+        .o_wb_we_data(o_wb_we_data),  //write-enable (1 = write, 0 = read)
+        .o_wb_addr_data(o_wb_addr_data), //data memory address
+        .o_wb_data_data(o_wb_data_data), //data to be stored to memory (mask-aligned)
+        .o_wb_sel_data(o_wb_sel_data), //byte strobe for write (1 = write the byte) {byte3,byte2,byte1,byte0}
+        .i_wb_ack_data(i_wb_ack_data), //ack by data memory (high when read data is ready or when write data is already written
+        .i_wb_stall_data(i_wb_stall_data), //stall by data memory (1 = data memory is busy)
+        .i_wb_data_data(i_wb_data_data), //data retrieve from data memory 
+        .o_data_load(memoryaccess_data_load), //data to be loaded to base reg (z-or-s extended) 
+         /// Pipeline Control ///   
+        .i_stall_from_alu(o_stall_from_alu), //stalls this stage when incoming instruction is a load/store
+        .i_ce(memoryaccess_ce), // input clk enable for pipeline stalling of this stage
+        .o_ce(writeback_ce), // output clk enable for pipeline stalling of next stage
+        .i_stall(stall_writeback), //informs this stage to stall
+        .o_stall(stall_memoryaccess), //informs pipeline to stall
+        .i_flush(writeback_flush), //flush this stage
+        .o_flush(memoryaccess_flush) //flushes previous stages
+    );
+    
+    rv32i_writeback m5( //logic controller for the next PC and rd value [WRITEBACK STAGE , STAGE 5]
+        .i_funct3(memoryaccess_funct3), //function type
+        .i_data_load(memoryaccess_data_load), //data to be loaded to base reg (from previous stage)
+        .i_csr_out(csr_out), //CSR value to be loaded to basereg
+        .i_opcode_load(memoryaccess_opcode[`LOAD]),
+        .i_opcode_system(memoryaccess_opcode[`SYSTEM]), 
+        // Basereg Control
+        .i_wr_rd(memoryaccess_wr_rd), //write rd to base reg is enabled (from memoryaccess stage)
+        .o_wr_rd(writeback_wr_rd), //write rd to the base reg if enabled
+        .i_rd_addr(memoryaccess_rd_addr), //address for destination register (from previous stage)
+        .o_rd_addr(writeback_rd_addr), //address for destination register
+        .i_rd(memoryaccess_rd), //value to be written back to destination reg
+        .o_rd(writeback_rd), //value to be written back to destination register
+        // PC Control
+        .i_pc(memoryaccess_pc), //pc value
+        .o_next_pc(writeback_next_pc), //new PC value
+        .o_change_pc(writeback_change_pc), //high if PC needs to jump
+        // Trap-Handler
+        .i_go_to_trap(csr_go_to_trap), //high before going to trap (if exception/interrupt detected)
+        .i_return_from_trap(csr_return_from_trap), //high before returning from trap (via mret)
+        .i_return_address(csr_return_address), //mepc CSR
+        .i_trap_address(csr_trap_address), //mtvec CSR
+        /// Pipeline Control ///
+        .i_ce(writeback_ce), // input clk enable for pipeline stalling of this stage
+        .o_stall(stall_writeback), //informs pipeline to stall
+        .o_flush(writeback_flush) //flushes previous stages 
+    );
+    
+    // removable extensions
+    if(ZICSR_EXTENSION == 1) begin: zicsr
+        rv32i_csr #(.TRAP_ADDRESS(TRAP_ADDRESS)) m6( // control logic for Control and Status Registers (CSR) [STAGE 4]
+            .i_clk(i_clk),
+            .i_rst_n(i_rst_n),
+            // Interrupts
+            .i_external_interrupt(i_external_interrupt), //interrupt from external source
+            .i_software_interrupt(i_software_interrupt), //interrupt from software (inter-processor interrupt)
+            .i_timer_interrupt(i_timer_interrupt), //interrupt from timer
+            /// Exceptions ///
+            .i_is_inst_illegal(alu_exception[`ILLEGAL]), //illegal instruction
+            .i_is_ecall(alu_exception[`ECALL]), //ecall instruction
+            .i_is_ebreak(alu_exception[`EBREAK]), //ebreak instruction
+            .i_is_mret(alu_exception[`MRET]), //mret (return from trap) instruction
+            /// Load/Store Misaligned Exception///
+            .i_opcode(alu_opcode), //opcode type from alu stage
+            .i_y(alu_y), //y value from ALU (address used in load/store/jump/branch)
+            /// CSR instruction ///
+            .i_funct3(alu_funct3), // CSR instruction operation
+            .i_csr_index(alu_imm), //immediate value decoded by decoder
+            .i_imm({27'b0,alu_rs1_addr}), //unsigned immediate for immediate type of CSR instruction (new value to be stored to CSR)
+            .i_rs1(alu_rs1), //Source register 1 value (new value to be stored to CSR)
+            .o_csr_out(csr_out), //CSR value to be loaded to basereg
+            // Trap-Handler 
+            .i_pc(alu_pc), //Program Counter  (three stages had already been filled [fetch -> decode -> execute ])
+            .writeback_change_pc(writeback_change_pc), //high if writeback will issue change_pc (which will override this stage)
+            .o_return_address(csr_return_address), //mepc CSR
+            .o_trap_address(csr_trap_address), //mtvec CSR
+            .o_go_to_trap_q(csr_go_to_trap), //high before going to trap (if exception/interrupt detected)
+            .o_return_from_trap_q(csr_return_from_trap), //high before returning from trap (via mret)
+            .i_minstret_inc(writeback_ce), //high for one clock cycle at the end of every instruction
+            /// Pipeline Control ///
+            .i_ce(memoryaccess_ce), // input clk enable for pipeline stalling of this stage
+            .i_stall((stall_writeback || stall_memoryaccess)) //informs this stage to stall
+        );
+    end
+    else begin: zicsr
+        assign csr_out = 0;
+        assign csr_return_address = 0;
+        assign csr_trap_address = 0;
+        assign csr_go_to_trap = 0;
+        assign csr_return_from_trap = 0;
+    end
+     
+
+
+
+   `ifdef FORMAL 
+        //f_past_valid logic
+        reg f_past_valid = 0;
+        always @(posedge i_clk) f_past_valid <= 1;
+
+        // assume initial conditions
+        initial begin
+            assume(i_rst_n == 0);
+        end
+
+        // assumption on inputs(not more than one opcode and alu operation is high)
+        wire[4:0] f_alu=decoder_alu[`ADD]+decoder_alu[`SUB]+decoder_alu[`SLT]+decoder_alu[`SLTU]+decoder_alu[`XOR]+decoder_alu[`OR]+decoder_alu[`AND]+decoder_alu[`SLL]+decoder_alu[`SRL]+decoder_alu[`SRA]+decoder_alu[`EQ]+decoder_alu[`NEQ]+decoder_alu[`GE]+decoder_alu[`GEU]+0;
+        wire[4:0] f_opcode=decoder_opcode[`RTYPE]+decoder_opcode[`ITYPE]+decoder_opcode[`LOAD]+decoder_opcode[`STORE]+decoder_opcode[`BRANCH]+decoder_opcode[`JAL]+decoder_opcode[`JALR]+decoder_opcode[`LUI]+decoder_opcode[`AUIPC]+decoder_opcode[`SYSTEM]+decoder_opcode[`FENCE]+0;
+        always @* begin
+            assume(f_alu <= 1);
+            assume(f_opcode <= 1);
+        end
+
+        wire[4:0] f_outstanding;
+
+   fwb_master #(
+		// {{{
+		.AW(32),
+        .DW(32),
+		.F_MAX_STALL(1),
+		.F_MAX_ACK_DELAY(1),
+		.F_LGDEPTH(4),
+		.F_MAX_REQUESTS(0),
+		// OPT_BUS_ABORT: If true, the master can drop CYC at any time
+		// and must drop CYC following any bus error
+		.OPT_BUS_ABORT(1'b1),
+		//
+		// If true, allow the bus to be kept open when there are no
+		// outstanding requests.  This is useful for any master that
+		// might execute a read modify write cycle, such as an atomic
+		// add.
+		.F_OPT_RMW_BUS_OPTION (1),
+		//
+		//
+		// If true, allow the bus to issue multiple discontinuous
+		// requests.
+		// Unlike F_OPT_RMW_BUS_OPTION, these requests may be issued
+		// while other requests are outstanding
+		.F_OPT_DISCONTINUOUS(1),
+		//
+		//
+		// If true, insist that there be a minimum of a single clock
+		// delay between request and response.  This defaults to off
+		// since the wishbone specification specifically doesn't
+		// require this.  However, some interfaces do, so we allow it
+		// as an option here.
+		.F_OPT_MINCLOCK_DELAY(1)
+	) fwb_master (
+		// {{{
+		.i_clk(i_clk), 
+        .i_reset(!i_rst_n),
+		// The Wishbone bus
+		.i_wb_cyc(o_wb_cyc_data), 
+        .i_wb_stb(o_wb_stb_data), 
+        .i_wb_we(o_wb_we_data),
+		.i_wb_addr(o_wb_addr_data),
+		.i_wb_data(o_wb_data_data),
+		.i_wb_sel(o_wb_sel_data),
+		//
+		.i_wb_ack(i_wb_ack_data),
+		.i_wb_stall(i_wb_stall_data),
+		.i_wb_idata(i_wb_data_data),
+		.i_wb_err(1'b0),
+		// Some convenience output parameters
+		.f_nreqs(), 
+        .f_nacks(),
+		.f_outstanding(f_outstanding)
+		// }}}
+	);
+        always @* begin
+            assert(f_outstanding <= 1);
+            if(f_outstanding == 1) begin
+                assert(!o_wb_stb_data);
+            end
+        end
+  
+        /*
+        //////////////////////////////////////////////// verify Operand Forwarding ///////////////////////////////////////////////////
+        reg[4:0] f_alu_rs2_addr;
+        reg[4:0] f_memoryaccess_rs1_addr; 
+        reg[4:0] f_memoryaccess_rs2_addr; 
+        reg[31:0] f_memoryaccess_rs1;
+        reg[31:0] f_memoryaccess_rs2;
+
+        always @(posedge i_clk) begin 
+            if(alu_ce && !(stall[`ALU] || stall[`MEMORYACCESS] || stall[`WRITEBACK])) begin //store rs2_addr pipeline register for ALU stage
+                f_alu_rs2_addr <= decoder_rs2_addr_q;
+            end
+            if(memoryaccess_ce && !(stall[`MEMORYACCESS] || stall[`WRITEBACK])) begin //store rs1_addr, rs2_addr, rs1, and rs2  pipeline registers for STAGE 4
+                f_memoryaccess_rs1_addr <= alu_rs1_addr;
+                f_memoryaccess_rs2_addr <= f_alu_rs2_addr;
+                f_memoryaccess_rs1 <= alu_rs1;
+                f_memoryaccess_rs2 <= alu_rs2;
+            end
+        end
+        always @(posedge i_clk) begin
+            if(writeback_ce) begin //Stage 5 is enabled
+                if(f_memoryaccess_rs1_addr != 0) begin
+                    assert(f_memoryaccess_rs1 == m0.base_regfile[f_memoryaccess_rs1_addr]); //verify that the rs1 value used from the ALU stage is the MOST updated value
+                end
+                else assert(f_memoryaccess_rs1 == 0);
+
+                if(f_memoryaccess_rs2_addr != 0) begin
+                    assert(f_memoryaccess_rs2 == m0.base_regfile[f_memoryaccess_rs2_addr]); //verify that the rs2 value used from the ALU stage is the MOST updated value
+                end
+                else assert(f_memoryaccess_rs2 == 0);
+            end
+        end
+        /////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+        
+
+        ///////////////////////////////// verify that taken branches, jumps, and traps will update PC ///////////////////////////////////
+        always @(posedge i_clk) begin
+            // change_pc in stage 5 (due to traps) will force first stage to change PC in next clk cycle and all _ce to be
+            // disabled
+            if($past(writeback_change_pc) && $past(writeback_ce) && i_rst_n && f_past_valid) begin
+                assert(o_iaddr == $past(writeback_next_pc));  
+                assert({writeback_ce,memoryaccess_ce,alu_ce,decoder_ce}  == 0);
+            end
+
+            // change_pc in stage 3 (due to jumps and branches) will force first stage to change PC in next clock cycle unless
+            // stalled by stage 3(due to data dependency) or stage 4(due to load instruction) or be flushed by stage 5(due traps)
+            // and all _ce of previous stages of STAGE 3 to be disabled
+            else if($past(alu_change_pc) && $past(alu_ce) && !$past(stall_alu) && i_rst_n && f_past_valid) begin
+                assert(o_iaddr == $past(alu_next_pc));         
+                assert({alu_ce,decoder_ce} == 0);
+            end
+            
+            // verify that if no taken branches,jumps,or traps then PC  will just be added by 4
+            if(!$past(writeback_change_pc) && !$past(alu_change_pc) && !$past(stall_decoder || stall_alu || stall_memoryaccess || stall_writeback) 
+                 && $past(i_rst_n) && i_rst_n && f_past_valid) begin 
+                assert(o_iaddr == $past(o_iaddr)+4);
+            end
+        end
+        /////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+        */
+
+        /*
+        //////////////////////////////////////// verify valid writes to basereg and data memory /////////////////////////////////////////
+        always @(posedge i_clk) begin
+            // verify that basereg will be written only if writeback_ce is high
+            if(writeback_wr_rd) assert(writeback_ce);
+            
+            // verify data memory will be written at next clk cycle only if memoryaccess_ce is high and stage 5 does not have to change PC
+            if(o_wr_en) assert($past(memoryaccess_ce) && !$past(writeback_change_pc) && !writeback_change_pc);
+        end
+        /////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+
+        
+
+        /////////////////////////////////////////////////// verify pipeline stalls /////////////////////////////////////////////////////
+        reg cover_tick = 0;
+        always @(posedge i_clk) begin
+            // verify that when stalled, PC address and _ce will not change
+            if(($past(stall)!=0) && i_rst_n && f_past_valid) assert(o_iaddr == $past(o_iaddr));
+            if($past(stall[`WRITEBACK]) && i_rst_n && f_past_valid) begin
+               assert(writeback_ce == $past(writeback_ce));
+               assert(memoryaccess_ce == $past(memoryaccess_ce));
+               assert(alu_ce == $past(alu_ce));
+               assert(decoder_ce == $past(decoder_ce));
+               assert(fetch_ce == $past(fetch_ce));
+            end
+            if($past(stall[`MEMORYACCESS]) && i_rst_n && f_past_valid) begin
+               assert(memoryaccess_ce == $past(memoryaccess_ce));
+               assert(alu_ce == $past(alu_ce));
+               assert(decoder_ce == $past(decoder_ce));
+               assert(fetch_ce == $past(fetch_ce));
+            end
+            if($past(stall[`ALU]) && i_rst_n && f_past_valid) begin
+               assert(alu_ce == $past(alu_ce));
+               assert(decoder_ce == $past(decoder_ce));
+               assert(fetch_ce == $past(fetch_ce));
+            end
+            if($past(stall[`DECODER]) && i_rst_n && f_past_valid) begin
+               assert(decoder_ce == $past(decoder_ce));
+               assert(fetch_ce == $past(fetch_ce));
+            end
+            if($past(stall[`FETCH]) && i_rst_n && f_past_valid) begin
+               assert(fetch_ce == $past(fetch_ce));
+            end
+            
+            //verify that output states of ALU stage will not change if pipeline is stalled
+            if($past(alu_ce) && $past(stall[`MEMORYACCESS]) && i_rst_n && f_past_valid) begin
+               assert(alu_change_pc == $past(alu_change_pc));
+               assert(alu_next_pc == $past(alu_next_pc));
+               assert(alu_force_stall == $past(alu_force_stall));
+            end
+
+            // verify that if a stage is stalled, then the previous stage should be stalled too
+            if(stall[`WRITEBACK]) assert(stall[`MEMORYACCESS]);
+            if(stall[`MEMORYACCESS] || (alu_force_stall && !writeback_change_pc)) assert(stall[`ALU]);
+            if(stall[`ALU]) assert(stall[`DECODER]);
+            if(stall[`DECODER]) assert(stall[`FETCH]);
+            if(writeback_change_pc) assert(stall == 0); //pipeline will never be stalled and flushed(by stage 5) at same time
+                                                        //No stall can stop flush from stage 5
+
+            // verify that if stage 4 is stalled while stage 5 is not, stage 5 will be disabled at next clk cycle (writeback_ce wil be low) (pipeline bubbling)
+            if($past(stall[`MEMORYACCESS]) && !$past(stall[`WRITEBACK]) && $past(i_rst_n) && i_rst_n && f_past_valid) begin
+                assert(memoryaccess_ce && !writeback_ce);
+            end 
+            // verify that if stage 3 is stalled while stage 4 is not, stage 4 will be disabled at next clk cycle (memoryaccess_ce will be low) (pipeline bubbling)
+           if($past(alu_force_stall) && !$past(stall[`MEMORYACCESS]) && $past(i_rst_n) && i_rst_n && !$past(writeback_change_pc) && f_past_valid) begin
+                assert(alu_ce && !memoryaccess_ce);
+           end
+
+        end
+        /////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+        */
+
+        /*
+        //////////////////////////////////////// verify increments of mcycle and minstret CSR ///////////////////////////////////////////
+        always @(posedge i_clk) begin
+            //verify mcycle will always increment
+            if(!$past(zicsr.m6.mcountinhibit_cy) && $past(i_rst_n) && i_rst_n && f_past_valid) begin
+                assert(zicsr.m6.mcycle == $past(zicsr.m6.mcycle) + 1);
+            end
+
+            //verify minstret will increment for every instruction executed (except for go_to_trap and return_from_trap)
+            if($past(!zicsr.m6.mcountinhibit_ir && writeback_ce && !stall[`WRITEBACK] && !csr_go_to_trap && !csr_return_from_trap && i_rst_n) && i_rst_n) begin
+              assert(zicsr.m6.minstret == $past(zicsr.m6.minstret) + 1);
+            end
+        end
+        /////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+        */
+
+
+        ////////////////////////////////////////////////////// COVER STATEMENTS /////////////////////////////////////////////////////////
+        /*
+        always @(posedge i_clk) begin
+            // cover 10 instruction executed
+            cover(zicsr.m6.minstret == 10);
+            // cover write to basereg address 2
+            cover(($past(m0.base_regfile[2]) != m0.base_regfile[2]) && f_past_valid); 
+            // cover if basereg can change without the wr_rd enabled by writeback stage [FAIL]
+            //cover(($past(m0.base_regfile[3]) != m0.base_regfile[3] && f_past_valid) && !$past(writeback_wr_rd));
+        end
+        */
+        /////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
+    `endif
+endmodule

AngeloJacobo_RISC-V/rtl/rv32i_csr.v

@@ -0,0 +1,540 @@
+// control logic for Control and Status Registers (CSR) [ZICSR EXTENSION]
+
+`timescale 1ns / 1ps
+`default_nettype none
+`include "rv32i_header.vh"
+
+module rv32i_csr #(parameter TRAP_ADDRESS = 0) (
+    input wire i_clk, i_rst_n,
+    // Interrupts
+    input wire i_external_interrupt, //interrupt from external source
+    input wire i_software_interrupt, //interrupt from software (inter-processor interrupt)
+    input wire i_timer_interrupt, //interrupt from timer
+    /// Exceptions ///
+    input wire i_is_inst_illegal, //illegal instruction
+    input wire i_is_ecall, //ecall instruction
+    input wire i_is_ebreak, //ebreak instruction
+    input wire i_is_mret, //mret (return from trap) instruction
+    /// Instruction/Load/Store Misaligned Exception///
+    input wire[`OPCODE_WIDTH-1:0] i_opcode, //opcode types
+    input wire[31:0] i_y, //y value from ALU (address used in load/store/jump/branch)
+    /// CSR instruction ///
+    input wire[2:0] i_funct3, // CSR instruction operation
+    input wire[11:0] i_csr_index, // immediate value from decoder
+    input wire[31:0] i_imm, //unsigned immediate for immediate type of CSR instruction (new value to be stored to CSR)
+    input wire[31:0] i_rs1, //Source register 1 value (new value to be stored to CSR)
+    output reg[31:0] o_csr_out, //CSR value to be loaded to basereg
+    // Trap-Handler 
+    input wire[31:0] i_pc, //Program Counter 
+    input wire writeback_change_pc, //high if writeback will issue change_pc (which will override this stage)
+    output reg[31:0] o_return_address, //mepc CSR
+    output reg[31:0] o_trap_address, //mtvec CSR
+    output reg o_go_to_trap_q, //high before going to trap (if exception/interrupt detected)
+    output reg o_return_from_trap_q, //high before returning from trap (via mret)
+    input wire i_minstret_inc, //increment minstret after executing an instruction
+    /// Pipeline Control ///
+    input wire i_ce, // input clk enable for pipeline stalling of this stage
+    input wire i_stall //informs this stage to stall
+);
+    
+               //CSR operation type
+    localparam CSRRW = 3'b001,
+               CSRRS = 3'b010,
+               CSRRC = 3'b011,
+               CSRRWI = 3'b101,
+               CSRRSI = 3'b110,
+               CSRRCI = 3'b111;
+               
+               //CSR addresses
+               //machine info
+    localparam MVENDORID = 12'hF11,  
+               MARCHID = 12'hF12,
+               MIMPID = 12'hF13,
+               MHARTID = 12'hF14,
+               //machine trap setup
+               MSTATUS = 12'h300, 
+               MISA = 12'h301,
+               MIE = 12'h304,
+               MTVEC = 12'h305,
+               //machine trap handling
+               MSCRATCH = 12'h340, 
+               MEPC = 12'h341,
+               MCAUSE = 12'h342,
+               MTVAL = 12'h343,
+               MIP = 12'h344,
+               //machine counters/timers
+               MCYCLE = 12'hB00,
+               MCYCLEH = 12'hB80,
+               //TIME = 12'hC01,
+               //TIMEH = 12'hC81,
+               MINSTRET = 12'hB02,
+               MINSTRETH = 12'hBB2,
+               MCOUNTINHIBIT = 12'h320;
+                
+               //mcause codes
+    localparam MACHINE_SOFTWARE_INTERRUPT =3,
+               MACHINE_TIMER_INTERRUPT = 7,
+               MACHINE_EXTERNAL_INTERRUPT = 11,
+               INSTRUCTION_ADDRESS_MISALIGNED = 0,
+               ILLEGAL_INSTRUCTION = 2,
+               EBREAK = 3,
+               LOAD_ADDRESS_MISALIGNED = 4,
+               STORE_ADDRESS_MISALIGNED = 6,
+               ECALL = 11;
+    
+    
+    wire opcode_store=i_opcode[`STORE];
+    wire opcode_load=i_opcode[`LOAD];
+    wire opcode_branch=i_opcode[`BRANCH];
+    wire opcode_jal=i_opcode[`JAL];
+    wire opcode_jalr=i_opcode[`JALR];
+    wire opcode_system=i_opcode[`SYSTEM];
+    reg[31:0] csr_in; //value to be stored to CSR
+    reg[31:0] csr_data; //value at current CSR address
+    wire csr_enable = opcode_system && i_funct3!=0 && i_ce && !writeback_change_pc; //csr read/write operation is enabled only at this conditions
+    reg[1:0] new_pc = 0; //last two bits of i_pc that will be used in taken branch and jumps
+    reg go_to_trap; //high before going to trap (if exception/interrupt detected)
+    reg return_from_trap; //high before returning from trap (via mret)
+    reg is_load_addr_misaligned; 
+    reg is_store_addr_misaligned;
+    reg is_inst_addr_misaligned;
+    //reg timer_interrupt;
+    reg external_interrupt_pending; 
+    reg software_interrupt_pending;
+    reg timer_interrupt_pending;
+    reg is_interrupt;
+    reg is_exception;
+    reg is_trap;
+    wire stall_bit =i_stall;
+
+    // CSR register bits
+    reg mstatus_mie; //Machine Interrupt Enable
+    reg mstatus_mpie; //Machine Previous Interrupt Enable
+    reg[1:0] mstatus_mpp; //MPP
+    reg mie_meie; //machine external interrupt enable
+    reg mie_mtie; //machine timer interrupt enable
+    reg mie_msie; //machine software interrupt enable
+    reg[29:0] mtvec_base; //address of i_pc after returning from interrupt (via MRET)
+    reg[1:0] mtvec_mode; //vector mode addressing 
+    reg[31:0] mscratch; //dedicated for use by machine code
+    reg[31:0] mepc; //machine exception i_pc (address of interrupted instruction)
+    reg mcause_intbit; //interrupt(1) or exception(0)
+    reg[3:0] mcause_code; //indicates event that caused the trap
+    reg[31:0] mtval; //exception-specific infotmation to assist software in handling trap
+    reg mip_meip; //machine external interrupt pending
+    reg mip_mtip; //machine timer interrupt pending
+    reg mip_msip; //machine software interrupt pending
+    reg[63:0] mcycle; //counts number of i_clk cycle executed by core
+    //reg[63:0] mtime; //real-time i_clk (millisecond increment)
+    //reg[$clog2(MILLISEC_WRAP)-1:0] millisec;  //counter with period of 1 millisec
+    //reg[63:0] mtimecmp; //compare register for mtime
+    reg[63:0] minstret; //counts number instructions retired/executed by core
+    reg mcountinhibit_cy; //controls increment of mcycle
+    reg mcountinhibit_ir; //controls increment of minstret
+    
+    //control logic for load/store/instruction misaligned exception detection
+    always @* begin
+        is_load_addr_misaligned = 0;
+        is_store_addr_misaligned = 0;
+        is_inst_addr_misaligned = 0;
+        new_pc = 0;
+        
+        // Misaligned Load/Store Address
+        if(i_funct3[1:0] == 2'b01) begin //halfword load/store
+            is_load_addr_misaligned = opcode_load? i_y[0] : 0;
+            is_store_addr_misaligned = opcode_store? i_y[0] : 0;
+        end
+        if(i_funct3[1:0] == 2'b10) begin //word load/store
+            is_load_addr_misaligned = opcode_load? i_y[1:0]!=2'b00 : 0;
+            is_store_addr_misaligned = opcode_store? i_y[1:0]!=2'b00 : 0;
+        end
+        
+        // Misaligned Instruction Address
+        /* Volume 1 pg. 15: Instructions are 32 bits in length and must be aligned on a four-byte boundary in memory.
+        An instruction-address-misaligned exception is generated on a taken branch or unconditional jump
+        if the target address is not four-byte aligned. This exception is reported on the branch or jump
+        instruction, not on the target instruction. No instruction-address-misaligned exception is generated
+        for a conditional branch that is not taken. */
+        if((opcode_branch && i_y[0]) || opcode_jal || opcode_jalr) begin // branch or jump to new instruction
+            new_pc = i_pc[1:0] + i_csr_index[1:0];
+            if(opcode_jalr) new_pc = i_rs1[1:0] +  i_csr_index[1:0];
+            is_inst_addr_misaligned = (new_pc == 2'b00)? 1'b0:1'b1; //i_pc (instruction address) must always be four bytes aligned
+        end
+        
+    end
+    
+    //control logic for writing to CSRs
+    always @(posedge i_clk,negedge i_rst_n) begin
+        if(!i_rst_n) begin
+            o_go_to_trap_q <= 0;
+            o_return_from_trap_q <= 0;        
+            mstatus_mie <= 0;
+            mstatus_mpie <= 0;
+            mstatus_mpp <= 2'b11;
+            mie_meie <= 0;
+            mie_mtie <= 0;
+            mie_msie <= 0;
+            mtvec_base <= TRAP_ADDRESS[31:2];
+            mtvec_mode <= TRAP_ADDRESS[1:0];
+            mscratch <= 0;
+            mepc <= 0;
+            mcause_intbit <= 0;
+            mcause_code <= 0;
+            mtval <= 0;
+            mip_meip <= 0;
+            mip_meip <= 0;
+            mip_msip <= 0;
+            mcycle <= 0;
+            //mtime <= 0;
+            //millisec <= 0;
+            //mtimecmp <= -1; //timer interrup will be triggered uninttentionally if reset at 0 (equal to mtime)
+            minstret <= 0;
+            mcountinhibit_cy <= 0;
+            mcountinhibit_ir <= 0;
+        end
+        else if(!stall_bit) begin
+            /***************************************************** CSR control logic *****************************************************/
+            //MSTATUS (controls hart's current operating state (mie and mpie are the only configurable bits))
+            if(i_csr_index == MSTATUS && csr_enable) begin 
+                mstatus_mie <= csr_in[3];
+                mstatus_mpie <= csr_in[7];
+                //mstatus_mpp <= csr_in[12:11];
+            end
+            else begin
+                if(go_to_trap && !o_go_to_trap_q) begin
+                    /* Volume 2 pg. 21: xPIE holds the value of the interrupt-enable bit active prior to the trap. 
+                    When a trap is taken from privilege mode y into privilege mode x,xPIE is set to the value of x IE;
+                    x IE is set to 0; and xPP is set to y. */
+                    mstatus_mie <= 0; //no nested interrupt allowed 
+                    mstatus_mpie <= mstatus_mie; 
+                    mstatus_mpp <= 2'b11;
+                end
+                else if(return_from_trap) begin
+                    /* Volume 2 pg. 21: An MRET or SRET instruction is used to return from a trap in M-mode or S-mode respectively. 
+                    When executing an xRET instruction, supposing xPP holds the value y, xIE is set to xPIE; the
+                    privilege mode is changed to y; xPIE is set to 1; */
+                    mstatus_mie <= mstatus_mpie; 
+                    mstatus_mpie <= 1;
+                    mstatus_mpp <= 2'b11;
+                end
+            end
+     
+     
+            //MIE (interrupt enable bits)
+            if(i_csr_index == MIE && csr_enable) begin   
+                mie_msie <= csr_in[3]; 
+                mie_mtie <= csr_in[7]; 
+                mie_meie <= csr_in[11]; 
+            end  
+            
+            
+            //MTVEC (trap vector configuration (base+mode))
+            if(i_csr_index == MTVEC && csr_enable) begin
+                mtvec_base <= csr_in[31:2];
+                mtvec_mode <= csr_in[1:0]; 
+            end
+            
+            
+            //MSCRATCH (dedicated for use by machine code)   
+            if(i_csr_index == MSCRATCH && csr_enable) begin
+                mscratch <= csr_in;
+            end
+            
+            
+            //MEPC (address of interrupted instruction)
+            if(i_csr_index == MEPC && csr_enable) begin 
+                mepc <= {csr_in[31:2],2'b00};
+            end
+            /* Volume 2 pg. 38: When a trap is taken into M-mode, mepc is written with the virtual address of the 
+             instruction that was interrupted or that encountered the exception */
+            if(go_to_trap && !o_go_to_trap_q) mepc <= i_pc; 
+            
+            
+            //MCAUSE (indicates cause of trap(either interrupt or exception))
+            if(i_csr_index == MCAUSE && csr_enable) begin
+               mcause_intbit <= csr_in[31];
+               mcause_code <= csr_in[3:0];         
+            end
+            /* Volume 2 pg. 38: When a trap is taken into M-mode, mcause is written with a code indicating the event that caused the trap */
+            // Interrupts have priority (external first, then s/w, then timer---[2] sec 3.1.9), then synchronous traps.
+            if(go_to_trap && !o_go_to_trap_q) begin
+                if(external_interrupt_pending) begin 
+                    mcause_code <= MACHINE_EXTERNAL_INTERRUPT; 
+                    mcause_intbit <= 1;
+                end
+                else if(software_interrupt_pending) begin
+                    mcause_code <= MACHINE_SOFTWARE_INTERRUPT; 
+                    mcause_intbit <= 1;
+                end
+                else if(timer_interrupt_pending) begin 
+                    mcause_code <= MACHINE_TIMER_INTERRUPT; 
+                    mcause_intbit <= 1;
+                end
+                else if(i_is_inst_illegal) begin
+                    mcause_code <= ILLEGAL_INSTRUCTION;
+                    mcause_intbit <= 0 ;
+                end
+                else if(is_inst_addr_misaligned) begin
+                    mcause_code <= INSTRUCTION_ADDRESS_MISALIGNED;
+                    mcause_intbit <= 0;
+                end
+                else if(i_is_ecall) begin 
+                    mcause_code <= ECALL;
+                    mcause_intbit <= 0;
+                end
+                else if(i_is_ebreak) begin
+                    mcause_code <= EBREAK;
+                    mcause_intbit <= 0;
+                end
+                else if(is_load_addr_misaligned) begin
+                    mcause_code <= LOAD_ADDRESS_MISALIGNED;
+                    mcause_intbit <= 0;
+                end
+                else if(is_store_addr_misaligned) begin
+                    mcause_code <= STORE_ADDRESS_MISALIGNED;
+                    mcause_intbit <= 0;
+                end
+            end
+            
+            
+            //MTVAL (exception-specific information to assist software in handling trap)
+            if(i_csr_index == MTVAL && csr_enable) begin
+                mtval <= csr_in;
+            end
+            /*If mtval is written with a nonzero value when a breakpoint, address-misaligned, access-fault, or
+            page-fault exception occurs on an instruction fetch, load, or store, then mtval will contain the
+            faulting virtual address.*/
+            if(go_to_trap && !o_go_to_trap_q) begin
+                if(is_load_addr_misaligned || is_store_addr_misaligned) mtval <= i_y;
+            end           
+            
+            
+            //MCYCLE (counts number of i_clk cycle executed by core [LOWER HALF])
+            if(i_csr_index == MCYCLE && csr_enable) begin
+                mcycle[31:0] <= csr_in; 
+            end
+            
+            
+            //MCYCLEH (counts number of i_clk cycle executed by core [UPPER HALF])
+            if(i_csr_index == MCYCLEH && csr_enable) begin
+                mcycle[63:32] <= csr_in; 
+            end
+            mcycle <= mcountinhibit_cy? mcycle : mcycle + 1; //increments mcycle every clock cycle
+            
+            //MTIME (real-time counter [millisecond increment])
+            /* Volume 2 pg. 44: Platforms provide a real-time counter, exposed as a memory-mapped machine-mode
+             read-write register, mtime. mtime must increment at constant frequency, and the platform must provide a
+            mechanism for determining the period of an mtime tick. */
+           /*
+            if(i_mtime_wr) begin 
+                mtime<=i_mtime_din;
+                millisec <= 0;
+            end
+            else begin
+                millisec <= (millisec == MILLISEC_WRAP)? 0 : millisec + 1'b1;  //mod-one-millisecond counter
+                mtime <= mtime + ((millisec==MILLISEC_WRAP)? 1:0); //counter that increments every 1 millisecond
+            end
+            */
+            /* Volume 2 pg. 44: Platforms provide a 64-bit memory-mapped machine-mode timer compare register (mtimecmp). 
+            A machine timer interrupt becomes pending whenever mtime contains a value greater than or equal to mtimecmp, 
+            treating the values as unsigned integers. The interrupt remains posted until mtimecmp becomes greater than
+            mtime (typically as a result of writing mtimecmp). */
+           /*
+            if(i_mtimecmp_wr) begin
+                mtimecmp <= i_mtimecmp_din;
+            end
+            timer_interrupt = (mtime >= mtimecmp)? 1:0;
+            */
+           
+                   
+                            
+            //MIP (pending interrupts)       
+            mip_msip <= i_software_interrupt;
+            mip_mtip <= i_timer_interrupt;
+            mip_meip <= i_external_interrupt;
+            
+            
+            //MINSTRET (counts number instructions retired/executed by core [upper half])       
+            if(i_csr_index == MINSTRET && csr_enable) begin
+                minstret[31:0] <= csr_in; 
+            end
+            
+            
+            //MINSTRETH (counts number instructions retired/executed by core [lower half])       
+            if(i_csr_index == MINSTRETH && csr_enable) begin
+                minstret[63:32] <= csr_in; 
+            end
+             minstret <= mcountinhibit_ir? minstret : minstret + {63'b0,(i_minstret_inc && !o_go_to_trap_q && !o_return_from_trap_q)}; //increment minstret every instruction
+             
+             
+            //MCOUNTINHIBIT (controls which hardware performance-monitoring counters can increment)
+            if(i_csr_index == MCOUNTINHIBIT && csr_enable) begin
+                mcountinhibit_cy <= csr_in[0];
+                mcountinhibit_ir <= csr_in[2];
+            end
+
+             /****************************************************************************************************************************/
+             
+             /************************************** Registered Outputs for Trap Handlers ************************************************/
+             if(i_ce) begin
+                 o_go_to_trap_q <= go_to_trap;
+                 o_return_from_trap_q <= return_from_trap;
+                 o_return_address <= mepc;
+                 /* Volume 2 pg. 30: When MODE=Direct (0), all traps into machine mode cause the i_pc to be set to the address in the  
+                 BASE field. When MODE=Vectored (1), all synchronous exceptions into machine mode cause the i_pc to be set to the address 
+                 in the BASE field, whereas interrupts cause the i_pc to be set to the address in the BASE field plus four times the
+                 interrupt cause number */
+                 if(mtvec_mode[1] && is_interrupt) o_trap_address <= {mtvec_base,2'b00} + {28'b0,mcause_code<<2};
+                 else o_trap_address <= {mtvec_base,2'b00};
+                 
+                 /****************************************************************************************************************************/
+                 
+                 o_csr_out <= csr_data;
+              end
+              else begin //THIS SOLVES THE PROBLEM OF FREERTOS NOT WORKING
+                o_go_to_trap_q <= 0;
+                o_return_from_trap_q <= 0;
+              end
+        end
+        else begin
+            // this CSR will always be updated
+            mcycle <= mcountinhibit_cy? mcycle : mcycle + 1; //increments mcycle every clock cycle
+            minstret <= mcountinhibit_ir? minstret : minstret + {63'b0,(i_minstret_inc && !o_go_to_trap_q && !o_return_from_trap_q)}; //increment minstret every instruction
+        end
+    end
+
+   always @* begin
+        /************************************************** control logic for trap detection **************************************************/
+        external_interrupt_pending = 0;
+        software_interrupt_pending = 0;
+        timer_interrupt_pending = 0;
+        is_interrupt = 0;
+        is_exception = 0;
+        is_trap = 0;
+        go_to_trap = 0;
+        return_from_trap = 0;
+        
+        if(i_ce) begin
+             external_interrupt_pending =  mstatus_mie && mie_meie && (mip_meip); //machine_interrupt_enable + machine_external_interrupt_enable + machine_external_interrupt_pending must all be high
+             software_interrupt_pending = mstatus_mie && mie_msie && mip_msip;  //machine_interrupt_enable + machine_software_interrupt_enable + machine_software_interrupt_pending must all be high
+             timer_interrupt_pending = mstatus_mie && mie_mtie && mip_mtip; //machine_interrupt_enable + machine_timer_interrupt_enable + machine_timer_interrupt_pending must all be high
+             
+             is_interrupt = external_interrupt_pending || software_interrupt_pending || timer_interrupt_pending;
+             is_exception = (i_is_inst_illegal || is_inst_addr_misaligned || i_is_ecall || i_is_ebreak || is_load_addr_misaligned || is_store_addr_misaligned) && !writeback_change_pc;
+             is_trap = is_interrupt || is_exception;
+             go_to_trap = is_trap; //a trap is taken, save i_pc, and go to trap address
+             return_from_trap = i_is_mret; // return from trap, go back to saved i_pc
+             
+         end
+         /*************************************************************************************************************************************/
+         
+         
+        csr_data = 0;
+        csr_in = 0;
+        /************************************ specify csr_data (data CURRENTLY stored at the CSR) *********************************************/
+        case(i_csr_index)
+            //machine info
+            MVENDORID: csr_data = 32'h0;  //MVENDORID (JEDEC manufacturer ID)
+              MARCHID: csr_data = 32'h0; //MARCHID (open-source project architecture ID allocated by RISC-V International  ( https://github.com/riscv/riscv-isa-manual/blob/master/marchid.md ))
+               MIMPID: csr_data = 32'h0; //MIMPID (version of the processor implementation (provided by author of source code))
+              MHARTID: csr_data = 32'h0; //MHARTID (integer ID of the hart that is currently running the code (one hart must have an ID of zero))             
+            
+            //machine trap setup  
+              MSTATUS: begin //MSTATUS (controls hart's current operating state (mie and mpie are the only configurable bits))
+                        csr_data[3] = mstatus_mie;
+                        csr_data[7] = mstatus_mpie;
+                        csr_data[12:11] = mstatus_mpp; //MPP
+                       end
+                       
+                 MISA: begin //MISA (control and monitor hart's current operating state)
+                        csr_data[8] = 1'b1; //RV32I/64I/128I base ISA (ISA supported by the hart)
+                        csr_data[31:30] = 2'b01; //Base 32
+                       end
+                       
+                  MIE: begin //MIE (interrupt enable bits)
+                        csr_data[3] = mie_msie;
+                        csr_data[7] = mie_mtie;
+                        csr_data[11] = mie_meie;
+                       end
+                       
+                MTVEC: begin //MTVEC (trap vector configuration (base+mode))
+                        csr_data = {mtvec_base,mtvec_mode};
+                       end
+                       
+            //machine trap handling
+             MSCRATCH: begin //MSCRATCH (dedicated for use by machine code) 
+                        csr_data = mscratch;
+                       end
+                       
+                 MEPC: begin //MEPC (address of interrupted instruction)
+                        csr_data = mepc; 
+                       end
+                       
+               MCAUSE: begin //MCAUSE (indicates cause of trap(either interrupt or exception))
+                        csr_data[31] = mcause_intbit; 
+                        csr_data[3:0] = mcause_code;
+                       end
+                       
+                MTVAL: begin //MTVAL (exception-specific information to assist software in handling trap)
+                        csr_data = mtval;
+                       end
+                
+                  MIP: begin //MIP (pending interrupts)
+                        csr_data[3] = mip_msip;
+                        csr_data[7] = mip_mtip;
+                        csr_data[11] = mip_meip;
+                       end
+                       
+            //machine counters/timers
+               MCYCLE: begin //MCYCLE (counts number of i_clk cycle executed by core [LOWER HALF])
+                        csr_data = mcycle[31:0];
+                       end
+                       
+               MCYCLEH: begin //MCYCLE (counts number of i_clk cycle executed by core [UPPER HALF])
+                        csr_data = mcycle[63:32];
+                       end
+              /* timer is brought outside as part of CLINT (Core Logic
+                 Interrupt and this will be a memory-mapped register
+                 TIME: begin //TIME (real-time i_clk [millisecond increment] [LOWER HALF])
+                        csr_data = mtime[31:0];  
+                       end
+                 
+                TIMEH: begin //TIME (real-time i_clk [millisecond increment] [LOWER HALF])
+                        csr_data = mtime[63:32]; 
+                       end
+               */
+             MINSTRET: begin //MINSTRET (counts number instructions retired/executed by core [LOWER half])     
+                        csr_data = minstret[31:0];
+                       end
+                       
+            MINSTRETH: begin //MINSTRET (counts number instructions retired/executed by core [UPPER half])     
+                        csr_data = minstret[63:32];
+                       end
+                       
+        MCOUNTINHIBIT: begin //MCOUNTINHIBIT (controls which hardware performance-monitoring counters can increment)
+                        csr_data[0] = mcountinhibit_cy;
+                        csr_data[2] = mcountinhibit_ir;
+                       end
+                       
+              default: csr_data = 0;
+        endcase
+        /*****************************************************************************************************************************/
+        
+        
+        
+        /************************************ specify csr_in (data TO BE stored at the CSR ) *****************************************/
+        // specify csr_in (data TO BE stored to CSR)
+        case(i_funct3) //csr instruction type
+            CSRRW: csr_in = i_rs1; //CSR read-write
+            CSRRS: csr_in = csr_data | i_rs1; //CSR read-set
+            CSRRC: csr_in = csr_data & (~i_rs1); //CSR read-clear
+           CSRRWI: csr_in = i_imm; //csr read-write immediate
+           CSRRSI: csr_in = csr_data | i_imm;  //csr read-set immediate
+           CSRRCI: csr_in = csr_data & (~i_imm); //csr read-clear immediate
+          default: csr_in = 0;
+        endcase
+        /*****************************************************************************************************************************/
+   
+   end
+    
+endmodule

AngeloJacobo_RISC-V/rtl/rv32i_decoder.v

@@ -0,0 +1,249 @@
+/* The rv32i_decoder module is responsible for decoding the 32-bit RISC-V instructions, 
+producing the necessary control signals, and extracting the operand addresses and immediate 
+values required by the execution stage of the RISC-V processor. It is a crucial component
+in the decode stage of the pipeline. This module has several key components:
+ - Operand address extraction:
+    The module extracts the source and destination register addresses (rs1, rs2, and rd) 
+    from the input instruction. These addresses are used to access the register file in 
+    the next stage of the pipeline.
+ - Immediate value extraction: Depending on the instruction type, this module extracts 
+    and sign-extends the immediate value (imm) from the input instruction. This value is
+    used as an operand for arithmetic or load/store instructions, or as an offset for 
+    branch and jump instructions.
+ - ALU operation decoding: The module decodes the required ALU operation based on the 
+    opcode and funct3 fields of the instruction. It sets the appropriate signals 
+    (alu_add_d, alu_sub_d, alu_slt_d, etc.) to indicate the desired operation to be 
+    executed in the ALU during the execution stage.
+ - Opcode type decoding: The module identifies the type of instruction based on its opcode 
+    (opcode_rtype_d, opcode_itype_d, opcode_load_d, etc.). These signals are used in the 
+    next stages of the pipeline to control the flow of data and determine the required 
+    operations.
+ - Exception decoding: The module checks for illegal instructions, system instructions 
+    (ECALL, EBREAK, and MRET), and unsupported shift operations. If any of these conditions 
+    are detected, the corresponding exception signals (o_exception) are set.
+ - Pipeline control: The module supports pipeline stalling and flushing. If the next stage 
+    of the pipeline is stalled (i_stall), the module will stall the decode stage (o_stall) 
+    and prevent updating the output registers. If a flush signal (i_flush) is received, the 
+    module will flush its internal state and disable the clock enable signal (o_ce) for the 
+    next stage.
+*/
+
+`timescale 1ns / 1ps
+`default_nettype none
+`include "rv32i_header.vh"
+
+module rv32i_decoder(
+    input wire i_clk,i_rst_n,
+    input wire[31:0] i_inst, //32 bit instruction
+    input wire[31:0] i_pc, //PC value from previous stage
+    output reg[31:0] o_pc, //PC value
+    output wire[4:0] o_rs1_addr,//address for register source 1
+    output reg[4:0] o_rs1_addr_q,//registered address for register source 1
+    output wire[4:0] o_rs2_addr, //address for register source 2
+    output reg[4:0] o_rs2_addr_q, //registered address for register source 2
+    output reg[4:0] o_rd_addr, //address for destination address
+    output reg[31:0] o_imm, //extended value for immediate
+    output reg[2:0] o_funct3, //function type
+    output reg[`ALU_WIDTH-1:0] o_alu, //alu operation type
+    output reg[`OPCODE_WIDTH-1:0] o_opcode, //opcode type
+    output reg[`EXCEPTION_WIDTH-1:0] o_exception, //exceptions: illegal inst, ecall, ebreak, mret
+    /// Pipeline Control ///
+    input wire i_ce, // input clk enable for pipeline stalling of this stage
+    output reg o_ce, // output clk enable for pipeline stalling of next stage
+    input wire i_stall, //informs this stage to stall
+    output reg o_stall, //informs pipeline to stall
+    input wire i_flush, //flush this stage
+    output reg o_flush //flush previous stages
+);
+
+    assign o_rs2_addr = i_inst[24:20]; //o_rs1_addrando_rs2_addr are not registered 
+    assign o_rs1_addr = i_inst[19:15];   //since rv32i_basereg module do the registering itself
+    
+
+    wire[2:0] funct3_d = i_inst[14:12];
+    wire[6:0] opcode = i_inst[6:0];
+
+    reg[31:0] imm_d;
+    reg alu_add_d;
+    reg alu_sub_d;
+    reg alu_slt_d;
+    reg alu_sltu_d;
+    reg alu_xor_d;
+    reg alu_or_d;
+    reg alu_and_d;
+    reg alu_sll_d;
+    reg alu_srl_d;
+    reg alu_sra_d;
+    reg alu_eq_d; 
+    reg alu_neq_d;
+    reg alu_ge_d; 
+    reg alu_geu_d;
+    
+    reg opcode_rtype_d;
+    reg opcode_itype_d;
+    reg opcode_load_d;
+    reg opcode_store_d;
+    reg opcode_branch_d;
+    reg opcode_jal_d;
+    reg opcode_jalr_d;
+    reg opcode_lui_d;
+    reg opcode_auipc_d;
+    reg opcode_system_d;
+    reg opcode_fence_d;
+            
+    reg system_noncsr = 0;
+    reg valid_opcode = 0;
+    reg illegal_shift = 0;
+    wire stall_bit = o_stall || i_stall; //stall this stage when next stages are stalled
+
+    //register the outputs of this decoder module for shorter combinational timing paths
+    always @(posedge i_clk, negedge i_rst_n) begin
+        if(!i_rst_n) begin
+            o_ce <= 0;
+        end
+        else begin
+            if(i_ce && !stall_bit) begin //update registers only if this stage is enabled and pipeline is not stalled
+                o_pc       <= i_pc;
+                o_rs1_addr_q <= o_rs1_addr;
+                o_rs2_addr_q <= o_rs2_addr;
+                o_rd_addr  <= i_inst[11:7];
+                o_funct3   <= funct3_d;
+                o_imm      <= imm_d;
+                
+                /// ALU Operations ////
+                o_alu[`ADD]  <= alu_add_d;
+                o_alu[`SUB]  <= alu_sub_d;
+                o_alu[`SLT]  <= alu_slt_d;
+                o_alu[`SLTU] <= alu_sltu_d;
+                o_alu[`XOR]  <= alu_xor_d;
+                o_alu[`OR]   <= alu_or_d; 
+                o_alu[`AND]  <= alu_and_d;
+                o_alu[`SLL]  <= alu_sll_d; 
+                o_alu[`SRL]  <= alu_srl_d;
+                o_alu[`SRA]  <= alu_sra_d;
+                o_alu[`EQ]   <= alu_eq_d; 
+                o_alu[`NEQ]  <= alu_neq_d;
+                o_alu[`GE]   <= alu_ge_d; 
+                o_alu[`GEU]  <= alu_geu_d;
+                          
+                o_opcode[`RTYPE]  <= opcode_rtype_d;
+                o_opcode[`ITYPE]  <= opcode_itype_d;
+                o_opcode[`LOAD]   <= opcode_load_d;
+                o_opcode[`STORE]  <= opcode_store_d;
+                o_opcode[`BRANCH] <= opcode_branch_d;
+                o_opcode[`JAL]    <= opcode_jal_d;
+                o_opcode[`JALR]   <= opcode_jalr_d;
+                o_opcode[`LUI]    <= opcode_lui_d;
+                o_opcode[`AUIPC]  <= opcode_auipc_d;
+                o_opcode[`SYSTEM] <= opcode_system_d;
+                o_opcode[`FENCE]  <= opcode_fence_d;
+                
+                /*********************** decode possible exceptions ***********************/
+                o_exception[`ILLEGAL] <= !valid_opcode || illegal_shift;
+
+                // Check if ECALL
+                o_exception[`ECALL] <= (system_noncsr && i_inst[21:20]==2'b00)? 1:0;
+                
+                // Check if EBREAK
+                o_exception[`EBREAK] <= (system_noncsr && i_inst[21:20]==2'b01)? 1:0;
+                
+                // Check if MRET
+                 o_exception[`MRET] <= (system_noncsr && i_inst[21:20]==2'b10)? 1:0;
+                /***************************************************************************/
+            end
+            if(i_flush && !stall_bit) begin //flush this stage so clock-enable of next stage is disabled at next clock cycle
+                o_ce <= 0;
+            end
+            else if(!stall_bit) begin //clock-enable will change only when not stalled
+                o_ce <= i_ce;
+            end
+            else if(stall_bit && !i_stall) o_ce <= 0; //if this stage is stalled but next stage is not, disable 
+                                                                    //clock enable of next stage at next clock cycle (pipeline bubble)
+        end
+    end
+    always @* begin
+        //// Opcode Type ////
+        opcode_rtype_d  = opcode == `OPCODE_RTYPE;
+        opcode_itype_d  = opcode == `OPCODE_ITYPE;
+        opcode_load_d   = opcode == `OPCODE_LOAD;
+        opcode_store_d  = opcode == `OPCODE_STORE;
+        opcode_branch_d = opcode == `OPCODE_BRANCH;
+        opcode_jal_d    = opcode == `OPCODE_JAL;
+        opcode_jalr_d   = opcode == `OPCODE_JALR;
+        opcode_lui_d    = opcode == `OPCODE_LUI;
+        opcode_auipc_d  = opcode == `OPCODE_AUIPC;
+        opcode_system_d = opcode == `OPCODE_SYSTEM;
+        opcode_fence_d  = opcode == `OPCODE_FENCE;
+        
+        /*********************** decode possible exceptions ***********************/
+        system_noncsr = opcode == `OPCODE_SYSTEM && funct3_d == 0 ; //system instruction but not CSR operation
+        
+        // Check if instruction is illegal    
+        valid_opcode = (opcode_rtype_d || opcode_itype_d || opcode_load_d || opcode_store_d || opcode_branch_d || opcode_jal_d || opcode_jalr_d || opcode_lui_d || opcode_auipc_d || opcode_system_d || opcode_fence_d);
+        illegal_shift = (opcode_itype_d && (alu_sll_d || alu_srl_d || alu_sra_d)) && i_inst[25];
+    end
+
+     //decode operation for ALU and the extended value of immediate
+    always @* begin
+        o_stall = i_stall; //stall previous stage when decoder needs wait time
+        o_flush = i_flush; //flush this stage along with the previous stages 
+        imm_d = 0;
+        alu_add_d = 0;
+        alu_sub_d = 0;
+        alu_slt_d = 0;
+        alu_sltu_d = 0;
+        alu_xor_d = 0;
+        alu_or_d = 0;
+        alu_and_d = 0;
+        alu_sll_d = 0;
+        alu_srl_d = 0;
+        alu_sra_d = 0;
+        alu_eq_d = 0; 
+        alu_neq_d = 0;
+        alu_ge_d = 0; 
+        alu_geu_d = 0;
+        
+        /********** Decode ALU Operation **************/
+        if(opcode == `OPCODE_RTYPE || opcode == `OPCODE_ITYPE) begin
+            if(opcode == `OPCODE_RTYPE) begin
+                alu_add_d = funct3_d == `FUNCT3_ADD ? !i_inst[30] : 0; //add and sub has same o_funct3 code
+                alu_sub_d = funct3_d == `FUNCT3_ADD ? i_inst[30] : 0;      //differs on i_inst[30]
+            end
+            else alu_add_d = funct3_d == `FUNCT3_ADD;
+            alu_slt_d = funct3_d == `FUNCT3_SLT;
+            alu_sltu_d = funct3_d == `FUNCT3_SLTU;
+            alu_xor_d = funct3_d == `FUNCT3_XOR;
+            alu_or_d = funct3_d == `FUNCT3_OR;
+            alu_and_d = funct3_d == `FUNCT3_AND;
+            alu_sll_d = funct3_d == `FUNCT3_SLL;
+            alu_srl_d = funct3_d == `FUNCT3_SRA ? !i_inst[30]:0; //srl and sra has same o_funct3 code
+            alu_sra_d = funct3_d == `FUNCT3_SRA ? i_inst[30]:0 ;      //differs on i_inst[30]
+        end
+
+        else if(opcode == `OPCODE_BRANCH) begin
+           alu_eq_d = funct3_d == `FUNCT3_EQ;
+           alu_neq_d = funct3_d == `FUNCT3_NEQ;    
+           alu_slt_d = funct3_d == `FUNCT3_LT;
+           alu_ge_d = funct3_d == `FUNCT3_GE;
+           alu_sltu_d = funct3_d == `FUNCT3_LTU;
+           alu_geu_d= funct3_d == `FUNCT3_GEU;
+        end
+
+        else alu_add_d = 1'b1; //add operation for all remaining instructions
+        /*********************************************/
+
+        /************************** extend the immediate (o_imm) *********************/
+        case(opcode)
+        `OPCODE_ITYPE , `OPCODE_LOAD , `OPCODE_JALR: imm_d = {{20{i_inst[31]}},i_inst[31:20]}; 
+                                      `OPCODE_STORE: imm_d = {{20{i_inst[31]}},i_inst[31:25],i_inst[11:7]};
+                                     `OPCODE_BRANCH: imm_d = {{19{i_inst[31]}},i_inst[31],i_inst[7],i_inst[30:25],i_inst[11:8],1'b0};
+                                        `OPCODE_JAL: imm_d = {{11{i_inst[31]}},i_inst[31],i_inst[19:12],i_inst[20],i_inst[30:21],1'b0};
+                        `OPCODE_LUI , `OPCODE_AUIPC: imm_d = {i_inst[31:12],12'h000};
+                     `OPCODE_SYSTEM , `OPCODE_FENCE: imm_d = {20'b0,i_inst[31:20]};   
+                     default: imm_d = 0;
+        endcase
+        /**************************************************************************/
+        
+    end
+    
+endmodule

AngeloJacobo_RISC-V/rtl/rv32i_fetch.v

@@ -0,0 +1,140 @@
+/* The rv32i_fetch module is primarily for fetching instructions from the memory
+and prepare them for the decode stage of the pipeline. The module is responsible
+for managing the Program Counter (PC), fetching instructions, and controlling 
+the pipeline. Below are the key functions of the rv32i_fetch module:
+ - Program Counter (PC) management: The module maintains a Program Counter (PC) 
+    that holds the address of the current instruction in memory. The PC is 
+    initialized at the reset vector address (specified by the parameter PC_RESET),
+    and it is incremented or updated based on the instruction flow control, 
+    such as branches, jumps, or traps.
+ - Instruction fetching: The module fetches the instruction from memory based on 
+    the current PC value. It sends a request for a new instruction (o_stb_inst) 
+    when the fetch stage is enabled (ce), and waits for an acknowledgment 
+    (i_ack_inst) from the memory. The fetched instruction (i_inst) is then sent
+    to the pipeline (o_inst).
+ - Pipeline control: The rv32i_fetch module manages the pipeline by controlling 
+    clock enable (o_ce) signals for the next stage. It can stall the fetch stage
+    (stall_fetch) when the next stages are stalled (i_stall), a requested 
+    instruction has not yet been acknowledged, or when there is no request for a
+    new instruction. Moreover, it can create pipeline bubbles when the PC needs 
+    to be changed, disabling clock enable signals for the next stages, ensuring
+    no instructions are executed during this period.
+ - PC control: The module updates the PC based on the control signals received 
+    from other stages in the pipeline. It can update the PC with a new address
+    (i_writeback_next_pc) when handling traps, or with the address of a taken 
+    branch or jump (i_alu_next_pc). The fetch stage can be stalled during this
+    process to prevent instructions from being executed in the pipeline.
+  - Handling stalls and flushes: The rv32i_fetch module can stall the fetch 
+    stage based on different conditions and store the current PC and instruction
+    values. When the stall condition is resolved, it can return to the stored 
+    values and continue fetching instructions. The module can also flush the 
+    fetch stage when required (i_flush), disabling the clock enable signal 
+    for the next stage, effectively clearing any pending instructions.
+*/
+`timescale 1ns / 1ps
+`default_nettype none
+`include "rv32i_header.vh"
+
+module rv32i_fetch #(parameter PC_RESET = 32'h00_00_00_00) (
+    input wire i_clk,i_rst_n,
+    output reg[31:0] o_iaddr, //instruction memory address
+    output reg[31:0] o_pc, //PC value of current instruction 
+    input wire[31:0] i_inst, // retrieved instruction from Memory
+    output reg[31:0] o_inst, // instruction sent to pipeline
+    output wire o_stb_inst, // request for instruction
+    input wire i_ack_inst, //ack (high if new instruction is now on the bus)
+    // PC Control
+    input wire i_writeback_change_pc, //high when PC needs to change when going to trap or returning from trap
+    input wire[31:0] i_writeback_next_pc, //next PC due to trap
+    input wire i_alu_change_pc, //high when PC needs to change for taken branches and jumps
+    input wire[31:0] i_alu_next_pc, //next PC due to branch or jump
+    /// Pipeline Control ///
+    output reg o_ce, // output clk enable for pipeline stalling of next stage
+    input wire i_stall, //stall logic for whole pipeline
+    input wire i_flush //flush this stage
+);
+
+    reg[31:0] iaddr_d, prev_pc, stalled_inst, stalled_pc;
+    reg ce, ce_d;
+    reg stall_fetch;
+    reg stall_q;
+    //stall this stage when:
+    //- next stages are stalled
+    //- you have request but no ack yeti
+    //- you dont have a request at all (no request then no instruction to execute for this stage)
+    wire stall_bit = stall_fetch || i_stall || (o_stb_inst && !i_ack_inst) || !o_stb_inst; 
+    assign o_stb_inst = ce; //request for new instruction if this stage is enabled                                                               
+    
+    //ce logic for fetch stage
+    always @(posedge i_clk, negedge i_rst_n) begin
+         if(!i_rst_n) ce <= 0;
+         else if((i_alu_change_pc || i_writeback_change_pc) && !(i_stall || stall_fetch)) ce <= 0; //do pipeline bubble when need to change pc so that next stages will be disabled 
+         else ce <= 1;                                                  //and will not execute the instructions already inside the pipeline
+     end
+
+
+
+    always @(posedge i_clk, negedge i_rst_n) begin
+        if(!i_rst_n) begin
+            o_ce <= 0;
+            o_iaddr <= PC_RESET;
+            prev_pc <= PC_RESET;
+            stalled_inst <= 0;
+            o_pc <= 0;
+        end
+        else begin 
+            if((ce && !stall_bit) || (stall_bit && !o_ce && ce) || i_writeback_change_pc) begin //update registers only if this stage is enabled and next stages are not stalled
+                o_iaddr <= iaddr_d;
+                o_pc <= stall_q? stalled_pc:prev_pc;
+                o_inst <= stall_q? stalled_inst:i_inst;
+            end
+            if(i_flush && !stall_bit) begin //flush this stage(only when not stalled) so that clock-enable of next stage is disabled at next clock cycle
+                o_ce <= 0;
+            end
+            else if(!stall_bit) begin //clock-enable will change only when not stalled
+                o_ce <= ce_d;
+            end
+            //if this stage is stalled but next stage is not, disable 
+            //clock enable of next stage at next clock cycle (pipeline bubble)
+            else if(stall_bit && !i_stall) o_ce <= 0; 
+                                                                    
+                
+            stall_q <= i_stall || stall_fetch; //raise stall when any of 5 stages is stalled
+
+            //store both instruction and PC before stalling so that we can
+            //come back to these values when we need to return from stall 
+            if(stall_bit && !stall_q) begin
+                stalled_pc <= prev_pc; 
+                stalled_inst <= i_inst; 
+            end
+            prev_pc <= o_iaddr; //this is the first delay to align the PC to the pipeline
+        end
+    end
+    // logic for PC and pipeline clock_enable control
+    always @* begin
+        iaddr_d = 0;
+        ce_d = 0;
+        stall_fetch = i_stall; //stall when retrieving instructions need wait time
+        //prepare next PC when changing pc, then do a pipeline bubble
+        //to disable the ce of next stage
+        if(i_writeback_change_pc) begin
+            iaddr_d = i_writeback_next_pc;
+            ce_d = 0;
+        end
+        else if(i_alu_change_pc) begin
+            iaddr_d  = i_alu_next_pc;
+            ce_d = 0;
+        end
+        else begin
+            iaddr_d = o_iaddr + 32'd4;
+            ce_d = ce;
+        end
+    end
+    
+endmodule
+
+
+
+
+
+

AngeloJacobo_RISC-V/rtl/rv32i_forwarding.v

@@ -0,0 +1,98 @@
+/*The rv32i_forwarding module is responsible for handling data hazards in the
+pipelined processor by implementing operand forwarding. Data hazards occur 
+when a register value is about to be overwritten by previous instructions that 
+are still in the pipeline and have not yet been written to the base register. 
+Operand forwarding resolves this issue by either stalling the pipeline until 
+the base register is updated (less efficient) or forwarding the updated operand
+value directly from the pipeline stage where it is currently being computed. Key
+functionalities of the rv32i_forwarding module include:
+ - Forwarding rs1 and rs2 operands: The module initially sets the output values
+    o_rs1 and o_rs2 to their original values from the base register (i_rs1_orig
+    and i_rs2_orig). It then checks for any data hazards by comparing the register
+    addresses of the operands (i_decoder_rs1_addr_q and i_decoder_rs2_addr_q) with
+    the destination register addresses in the pipeline stages (i_alu_rd_addr and 
+    i_memoryaccess_rd_addr).
+ - Operand forwarding for rs1:If the next value of rs1 is in stage 4 (Memory Access), 
+    and the Memory Access stage is enabled and if the next value of rs1 comes from a
+    load or CSR instruction (i.e., rd is not valid at stage 4), the module stalls the
+    ALU stage by asserting o_alu_force_stall. Otherwise, the module forwards the value
+    of rd from stage 4 (i_alu_rd) to o_rs1. If the next value of rs1 is in stage 5 
+    (Writeback), and the Writeback stage is enabled, the module forwards the value of
+    rd from stage 5 (i_writeback_rd) to o_rs1.
+ - Operand forwarding for rs2: If the next value of rs2 is in stage 4 (Memory Access),
+    and the Memory Access stage is enabled and if the next value of rs2 comes from a 
+    load or CSR instruction (i.e., rd is not yet valid at stage 4), the module stalls 
+    the ALU stage by asserting o_alu_force_stall. Otherwise, the module forwards the
+    value of rd from stage 4 (i_alu_rd) to o_rs2. If the next value of rs2 is in stage
+    5 (Writeback), and the Writeback stage is enabled, the module forwards the value
+    of rd from stage 5 (i_writeback_rd) to o_rs2.
+ - Handling zero register (x0) forwarding: The module ensures that no operation 
+    forwarding is performed when the register address is zero, as this register is
+    hardwired to zero. If either i_decoder_rs1_addr_q or i_decoder_rs2_addr_q is zero,
+    the corresponding output register (o_rs1 or o_rs2) is set to zero. By implementing
+    operand forwarding, the rv32i_forwarding module helps to mitigate data hazards,
+    ensuring the correct execution of instructions and improving the overall efficiency
+    of the RV32I pipelined processor.
+*/
+
+`timescale 1ns / 1ps
+`default_nettype none
+`include "rv32i_header.vh"
+
+module rv32i_forwarding (
+    input wire[31:0] i_rs1_orig, //current rs1 value saved in basereg
+    input wire[31:0] i_rs2_orig, //current rs2 value saved in basereg
+    input wire[4:0] i_decoder_rs1_addr_q, //address of operand rs1 used in ALU stage
+    input wire[4:0] i_decoder_rs2_addr_q, //address of operand rs2 used in ALU stage
+    output reg o_alu_force_stall, //high to force ALU stage to stall
+    output reg[31:0] o_rs1, //rs1 value with Operand Forwarding
+    output reg[31:0] o_rs2, //rs2 value with Operand Forwarding
+    // Stage 4 [MEMORYACCESS]
+    input wire[4:0] i_alu_rd_addr, //destination register address
+    input wire i_alu_wr_rd, //high if rd_addr will be written
+    input wire i_alu_rd_valid, //high if rd is already valid at this stage (not LOAD nor CSR instruction)
+    input wire[31:0] i_alu_rd, //rd value in stage 4
+    input wire i_memoryaccess_ce, //high if stage 4 is enabled
+    // Stage 5 [WRITEBACK]
+    input wire[4:0] i_memoryaccess_rd_addr, //destination register address
+    input wire i_memoryaccess_wr_rd, //high if rd_addr will be written
+    input wire[31:0] i_writeback_rd, //rd value in stage 5
+    input wire i_writeback_ce //high if stage 4 is enabled
+);
+
+    always @* begin
+        o_rs1 = i_rs1_orig; //original value from basereg
+        o_rs2 = i_rs2_orig; //original value from basereg
+        o_alu_force_stall = 0;
+         
+        // Data Hazard = Register value is about to be overwritten by previous instructions but are still on the pipeline and are not yet written to basereg.
+        // The solution to make sure the updated value of rs1 or rs2 is used is to either stall the pipeline until the basereg is updated (very inefficient) or use Operand Forwarding
+
+            // Operand Forwarding for rs1
+            if((i_decoder_rs1_addr_q == i_alu_rd_addr) && i_alu_wr_rd && i_memoryaccess_ce) begin //next value of rs1 is currently on stage 4
+                if(!i_alu_rd_valid) begin   //if next value of rs1 comes from load or CSR instruction then we must stall from ALU stage and wait until 
+                    o_alu_force_stall = 1;   //stage 4(Memoryaccess) becomes disabled, which means next value of rs1 is already at stage 5   
+                end
+                o_rs1 = i_alu_rd;
+            end
+            else if((i_decoder_rs1_addr_q == i_memoryaccess_rd_addr) && i_memoryaccess_wr_rd && i_writeback_ce) begin //next value of rs1 is currently on stage 5
+                o_rs1 = i_writeback_rd;
+            end
+            
+            // Operand Forwarding for rs2
+            if((i_decoder_rs2_addr_q == i_alu_rd_addr) && i_alu_wr_rd && i_memoryaccess_ce) begin //next value of rs2 is currently on stage 4
+                if(!i_alu_rd_valid) begin   //if next value of rs2 comes from load or CSR instruction(rd is only available at stage 5) then we must stall from ALU stage and wait until 
+                    o_alu_force_stall = 1;   //stage 4(Memoryaccess) becomes disabled (which implicitly means that next value of rs2 is already at stage 5)   
+                end
+                o_rs2 = i_alu_rd;
+            end
+            else if((i_decoder_rs2_addr_q == i_memoryaccess_rd_addr) && i_memoryaccess_wr_rd && i_writeback_ce) begin //next value of rs2 is currently on stage 5
+                o_rs2 = i_writeback_rd;
+            end
+
+            // No operation forwarding necessary when addr is zero since that address is hardwired to zero
+            if(i_decoder_rs1_addr_q == 0) o_rs1 = 0;
+            if(i_decoder_rs2_addr_q == 0) o_rs2 = 0;
+    end
+
+endmodule

AngeloJacobo_RISC-V/rtl/rv32i_header.vh

@@ -0,0 +1,62 @@
+`define ALU_WIDTH 14
+`define ADD 0
+`define SUB 1
+`define SLT 2
+`define SLTU 3
+`define XOR 4
+`define OR 5
+`define AND 6
+`define SLL 7
+`define SRL 8
+`define SRA 9
+`define EQ 10
+`define NEQ 11
+`define GE 12
+`define GEU 13
+
+`define OPCODE_WIDTH 11
+`define RTYPE 0
+`define ITYPE 1
+`define LOAD 2
+`define STORE 3
+`define BRANCH 4
+`define JAL 5
+`define JALR 6
+`define LUI 7
+`define AUIPC 8
+`define SYSTEM 9
+`define FENCE 10
+
+`define EXCEPTION_WIDTH 4
+`define ILLEGAL 0
+`define ECALL 1
+`define EBREAK 2
+`define MRET 3
+
+`define OPCODE_RTYPE 7'b0110011 
+`define OPCODE_ITYPE 7'b0010011
+`define OPCODE_LOAD 7'b0000011
+`define OPCODE_STORE 7'b0100011
+`define OPCODE_BRANCH 7'b1100011
+`define OPCODE_JAL 7'b1101111
+`define OPCODE_JALR 7'b1100111
+`define OPCODE_LUI 7'b0110111
+`define OPCODE_AUIPC 7'b0010111
+`define OPCODE_SYSTEM 7'b1110011
+`define OPCODE_FENCE 7'b0001111
+                      
+`define FUNCT3_ADD 3'b000
+`define FUNCT3_SLT 3'b010 
+`define FUNCT3_SLTU 3'b011
+`define FUNCT3_XOR 3'b100
+`define FUNCT3_OR 3'b110
+`define FUNCT3_AND 3'b111
+`define FUNCT3_SLL 3'b001
+`define FUNCT3_SRA 3'b101
+`define FUNCT3_EQ 3'b000
+`define FUNCT3_NEQ 3'b001
+`define FUNCT3_LT 3'b100
+`define FUNCT3_GE 3'b101
+`define FUNCT3_LTU 3'b110
+`define FUNCT3_GEU 3'b111 
+

AngeloJacobo_RISC-V/rtl/rv32i_memoryaccess.v

@@ -0,0 +1,198 @@
+ /* The rv32i_memoryaccess module serves as the memory access stage of the 
+ pipelined processor. This module primarily handles data memory access for
+ load and store instructions, as well as passing the necessary information 
+ to subsequent pipeline stas. The module is responsible for generating 
+ appropriate data memory addresses, data to be stored, and write masks for
+ different load/store operations, as well as handling pipeline stalls and 
+ flushes when required. Key functionalities of the rv32i_memoryaccess module
+ include:
+ - Address and data handling for load/store operations: The module uses the 
+ incoming address (i_y) to generate the appropriate data memory address (o_wb_addr_data)
+ and stores it in the o_data_store register. It also selects the correct byte, 
+ halfword, or word data from the data memory input (i_wb_data_data) based on the 
+ instruction's funct3 field and stores it in the o_data_load register. The 
+ write mask (o_wb_sel_data) is generated based on the address and the size of the 
+ operation (byte, halfword, or word). The mask is used to control which part
+ of the data memory will be written during store operations.
+ - Register writeback control: The module i_wb_stall_datadetermines whether a destination register
+ should be written (o_wr_rd) based on the input i_wr_rd signal. It passes the 
+ destination register address (o_rd_addr) and the data to be written (o_rd) to the 
+ next stage.
+ - Data memory control: The module controls the data memory read/write requests by
+ generating the o_stb_data signal, which indicates a request for data memory access.
+It also generates the o_wb_we_data signal, which indicates whether a write operation 
+should be performed on the data memory.
+ - Pipeline control: The module can stall the pipeline by asserting the o_stall signal
+ if the data memory access is not yet acknowledged (i_wb_ack_data) or if there is a stall
+ request from the ALU stage (i_stall_from_alu). It can also flush the current stage and
+ previous stages using the o_flush signal based on the input i_flush signal. The module 
+ controls the clock enable signals (o_ce) for the next stage based on the stall and flush 
+ conditions.
+*/ 
+ 
+`timescale 1ns / 1ps
+`default_nettype none
+`include "rv32i_header.vh"
+
+module rv32i_memoryaccess(
+    input wire i_clk, i_rst_n,
+    input wire[31:0] i_rs2, //data to be stored to memory is always i_rs2
+    input wire[31:0] i_y, //y value from ALU (address of data to memory be stored or loaded)
+    input wire[2:0] i_funct3, //funct3 from previous stage
+    output reg[2:0] o_funct3, //funct3 (byte,halfword,word)
+    input wire[`OPCODE_WIDTH-1:0] i_opcode, //determines if data_store will be to stored to data memory
+    output reg[`OPCODE_WIDTH-1:0] o_opcode,//opcode type
+    input wire[31:0] i_pc, //PC from previous stage
+    output reg[31:0] o_pc, //PC value
+    // Basereg Control
+    input wire i_wr_rd, //write rd to base reg is enabled (from memoryaccess stage)
+    output reg o_wr_rd, //write rd to the base reg if enabled
+    input wire[4:0] i_rd_addr, //address for destination register (from previous stage)
+    output reg[4:0] o_rd_addr, //address for destination register
+    input wire[31:0] i_rd, //value to be written back to destination reg
+    output reg[31:0] o_rd, //value to be written back to destination register
+    // Data Memory Control
+    output reg o_wb_cyc_data, //bus cycle active (1 = normal operation, 0 = all ongoing transaction are to be cancelled)
+    output reg o_wb_stb_data, //request for read/write access to data memory
+    output reg o_wb_we_data, //write-enable (1 = write, 0 = read)
+    output reg [31:0] o_wb_addr_data, //data memory address 
+    output reg[31:0] o_wb_data_data, //data to be stored to memory 
+    output reg[3:0] o_wb_sel_data, //byte strobe for write (1 = write the byte) {byte3,byte2,byte1,byte0}
+    input wire i_wb_ack_data, //ack by data memory (high when data to be read is ready or when write data is already written)
+    input wire i_wb_stall_data, //stall by data memory (1 = data memory is busy)
+    input wire[31:0] i_wb_data_data, //data retrieve from data memory 
+    output reg[31:0] o_data_load, //data to be loaded to base reg (z-or-s extended) 
+    /// Pipeline Control ///
+    input wire i_stall_from_alu, //stalls this stage when incoming instruction is a load/store
+    input wire i_ce, // input clk enable for pipeline stalling of this stage
+    output reg o_ce, // output clk enable for pipeline stalling of next stage
+    input wire i_stall, //informs this stage to stall
+    output reg o_stall, //informs pipeline to stall
+    input wire i_flush, //flush this stage
+    output reg o_flush //flush previous stages
+);
+    
+    reg[31:0] data_store_d; //data to be stored to memory
+    reg[31:0] data_load_d; //data to be loaded to basereg
+    reg[3:0] wr_mask_d; 
+    reg pending_request; //high if there is still a pending request (request which have not yet acknowledged)
+    wire[1:0] addr_2 = i_y[1:0]; //last 2  bits of data memory address
+    wire stall_bit = i_stall || o_stall;
+
+    //register the outputs of this module
+    always @(posedge i_clk, negedge i_rst_n) begin
+        if(!i_rst_n) begin
+            o_wr_rd <= 0;
+            o_wb_we_data <= 0;
+            o_ce <= 0;
+            o_wb_stb_data <= 0;
+            pending_request <= 0;
+            o_wb_cyc_data <= 0;
+        end
+        else begin
+            // wishbone cycle will only be high if this stage is enabled
+            o_wb_cyc_data <= i_ce;
+            //request completed after ack
+            if(i_wb_ack_data) begin 
+                pending_request <= 0;
+            end
+
+            //update register only if this stage is enabled and not stalled (after load/store operation)
+            if(i_ce && !stall_bit) begin 
+                o_rd_addr <= i_rd_addr;
+                o_funct3 <= i_funct3;
+                o_opcode <= i_opcode;
+                o_pc <= i_pc;
+                o_wr_rd <= i_wr_rd;
+                o_rd <= i_rd;
+                o_data_load <= data_load_d; 
+            end
+            //update request to memory when no pending request yet
+            if(i_ce && !pending_request) begin
+                //stb goes high when instruction is a load/store and when
+                //request is not already high (request lasts for 1 clk cycle
+                //only)
+                o_wb_stb_data <= i_opcode[`LOAD] || i_opcode[`STORE]; 
+                o_wb_sel_data <= wr_mask_d;
+                o_wb_we_data <= i_opcode[`STORE]; 
+                pending_request <= i_opcode[`LOAD] || i_opcode[`STORE]; 
+                o_wb_addr_data <= i_y; 
+                o_wb_data_data <= data_store_d;
+            end
+
+            // if there is pending request but no stall from memory: idle the stb line
+            if(pending_request && !i_wb_stall_data) begin
+                o_wb_stb_data <= 0;
+            end
+
+            if(!i_ce) begin
+                o_wb_stb_data <= 0;
+            end 
+            
+            //flush this stage so clock-enable of next stage is disabled at next clock cycle
+            if(i_flush && !stall_bit) begin 
+                o_ce <= 0;
+            end
+            else if(!stall_bit) begin //clock-enable will change only when not stalled
+                o_ce <= i_ce;
+            end
+
+            //if this stage is stalled but next stage is not, disable 
+            //clock enable of next stage at next clock cycle (pipeline bubble)
+            else if(stall_bit && !i_stall) o_ce <= 0;         
+        end
+
+    end 
+
+    //determine data to be loaded to basereg or stored to data memory 
+    always @* begin
+        //stall while data memory has not yet acknowledged i.e.write data is not yet written or
+        //read data is not yet available (no ack yet). Don't stall when need to flush by next stage
+        o_stall = ((i_stall_from_alu && i_ce && !i_wb_ack_data) || i_stall) && !i_flush;         
+        o_flush = i_flush; //flush this stage along with previous stages
+        data_store_d = 0;
+        data_load_d = 0;
+        wr_mask_d = 0; 
+           
+        case(i_funct3[1:0]) 
+            2'b00: begin //byte load/store
+                    case(addr_2)  //choose which of the 4 byte will be loaded to basereg
+                        2'b00: data_load_d = {24'b0, i_wb_data_data[7:0]};
+                        2'b01: data_load_d = {24'b0, i_wb_data_data[15:8]};
+                        2'b10: data_load_d = {24'b0, i_wb_data_data[23:16]};
+                        2'b11: data_load_d = {24'b0, i_wb_data_data[31:24]};
+                    endcase
+                    data_load_d = {{{24{!i_funct3[2]}} & {24{data_load_d[7]}}} , data_load_d[7:0]}; //signed and unsigned extension in 1 equation
+                    wr_mask_d = 4'b0001<<addr_2; //mask 1 of the 4 bytes
+                    data_store_d = i_rs2<<{addr_2,3'b000}; //i_rs2<<(addr_2*8) , align data to mask
+                   end
+            2'b01: begin //halfword load/store
+                    data_load_d = addr_2[1]? {16'b0,i_wb_data_data[31:16]}: {16'b0,i_wb_data_data[15:0]}; //choose which of the 2 halfwords will be loaded to basereg
+                    data_load_d = {{{16{!i_funct3[2]}} & {16{data_load_d[15]}}},data_load_d[15:0]}; //signed and unsigned extension in 1 equation
+                    wr_mask_d = 4'b0011<<{addr_2[1],1'b0}; //mask either the upper or lower half-word
+                    data_store_d = i_rs2<<{addr_2[1],4'b0000}; //i_rs2<<(addr_2[1]*16) , align data to mask
+                   end
+            2'b10: begin //word load/store
+                    data_load_d = i_wb_data_data;
+                    wr_mask_d = 4'b1111; //mask all
+                    data_store_d = i_rs2;
+                   end
+          default: begin
+                    data_store_d = 0;
+                    data_load_d = 0;
+                    wr_mask_d = 0; 
+                   end
+        endcase
+    end
+    
+`ifdef FORMAL
+    always @* begin
+        if(o_wb_stb_data) begin
+            assert(pending_request);
+        end
+    end
+
+`endif 
+
+endmodule
+

AngeloJacobo_RISC-V/rtl/rv32i_writeback.v

@@ -0,0 +1,98 @@
+/* The rv32i_writeback module serves as the writeback stage of the pipelined 
+processor. This stage is responsible for determining the next value of the
+program counter (PC), writing data back to the destination register, and 
+handling trap-related operations (interrupts and exceptions). In addition,
+the module manages pipeline control, such as stalling and flushing previous 
+stages. Key functionalities of the rv32i_writeback module include:
+ - Determining the next value of the program counter (PC) and updating the
+    o_next_pc register: If an interrupt or exception is detected, the module
+    sets the PC to the trap address (i_trap_address) and asserts the o_change_pc 
+    signal. If the processor is returning from a trap, the module sets the PC to 
+    the return address (i_return_address) and asserts the o_change_pc signal. In
+    normal operation, the PC value from the previous stage (i_pc) is passed through.
+ - Handling writeback to destination registers: The module writes data back to the
+    destination register based on the opcode and funct3 fields of the instruction:
+    If the instruction is a load operation, the data from the memory (i_data_load) 
+    is written back. If the instruction is a CSR write operation, the CSR value 
+    (i_csr_out) is written back. In other cases, the data is computed at the ALU
+    stage (i_rd) and is written back. The o_wr_rd signal is set based on the i_wr_rd 
+    input and the current pipeline control state (i_ce and o_stall). The destination 
+    register address (o_rd_addr) is passed through from the i_rd_addr input.
+ - Trap-handler control: The module handles interrupts and exceptions by checking the
+    i_go_to_trap and i_return_from_trap input signals. When the processor goes to a 
+    trap, the o_next_pc register is set to the trap address (i_trap_address) and the
+    pipeline is flushed. When the processor returns from a trap, the o_next_pc register
+    is set to the return address (i_return_address) and the pipeline is flushed.
+ - Pipeline control: The module can stall the pipeline by asserting the o_stall signal
+    when necessary. It can also flush the current stage and previous stages by asserting
+    the o_flush signal based on the state of the pipeline and trap-related operations.
+*/
+
+//logic controller for the next PC and rd value [WRITEBACK STAGE]
+
+`timescale 1ns / 1ps
+`default_nettype none
+`include "rv32i_header.vh"
+
+module rv32i_writeback (
+    input wire[2:0] i_funct3, //function type 
+    input wire[31:0] i_data_load, //data to be loaded to base reg
+    input wire[31:0] i_csr_out, //CSR value to be loaded to basereg
+    input wire i_opcode_load,
+    input wire i_opcode_system, 
+    // Basereg Control
+    input wire i_wr_rd, //write rd to basereg if enabled (from previous stage)
+    output reg o_wr_rd, //write rd to the base reg if enabled
+    input wire[4:0] i_rd_addr, //address for destination register (from previous stage)
+    output reg[4:0] o_rd_addr, //address for destination register
+    input wire[31:0] i_rd, //value to be written back to destination register (from previous stage)
+    output reg[31:0] o_rd, //value to be written back to destination register
+    // PC Control
+    input wire[31:0] i_pc, // pc value (from previous stage)
+    output reg[31:0] o_next_pc, //new pc value
+    output reg o_change_pc, //high if PC needs to jump
+    // Trap-Handler
+    input wire i_go_to_trap, //high before going to trap (if exception/interrupt detected)
+    input wire i_return_from_trap, //high before returning from trap (via mret)
+    input wire[31:0] i_return_address, //mepc CSR
+    input wire[31:0] i_trap_address, //mtvec CSR
+    /// Pipeline Control ///
+    input wire i_ce, // input clk enable for pipeline stalling of this stage
+    output reg o_stall, //informs pipeline to stall
+    output reg o_flush //flush previous stages
+);
+//
+    //determine next value of pc and o_rd
+    always @* begin
+        o_stall = 0; //stall when this stage needs wait time
+        o_flush = 0; //flush this stage along with previous stages when changing PC
+        o_wr_rd = i_wr_rd && i_ce && !o_stall;
+        o_rd_addr = i_rd_addr;
+        o_rd = 0;
+        o_next_pc = 0;
+        o_change_pc = 0;
+
+        if(i_go_to_trap) begin
+            o_change_pc = 1; //change PC only when ce of this stage is high (o_change_pc is valid)
+            o_next_pc = i_trap_address;  //interrupt or exception detected so go to trap address (mtvec value)
+            o_flush = i_ce;
+            o_wr_rd = 0;
+        end
+        
+        else if(i_return_from_trap) begin
+            o_change_pc = 1; //change PC only when ce of this stage is high (o_change_pc is valid)
+             o_next_pc = i_return_address; //return from trap via mret (mepc value)
+             o_flush = i_ce;
+             o_wr_rd = 0;
+        end
+        
+        else begin //normal operation
+            if(i_opcode_load) o_rd = i_data_load; //load data from memory to basereg
+            else if(i_opcode_system && i_funct3!=0) begin //CSR write
+                o_rd = i_csr_out; 
+            end
+            else o_rd = i_rd; //rd value is already computed at ALU stage
+        end
+        
+    end
+endmodule

AngeloJacobo_RISC-V/test/extra/demo1.c

@@ -0,0 +1,22 @@
+#include <stdint.h>
+#include <rv32i.h>
+ 
+int main() {
+  LCD_Init(); // Initialize LCD module with I2C address = 0x4E
+
+  while(1){  
+      LCD_Set_Cursor(1, 1); //set cursor to row 1 col 1
+      LCD_Write_String("Demonstration #1");
+      LCD_Set_Cursor(2, 1); //set cursor to row 2 col 1
+      LCD_Write_String("Hello World!!!");
+  }
+  return 0;
+}
+
+
+
+
+
+
+
+

AngeloJacobo_RISC-V/test/extra/test_gpio.c

@@ -0,0 +1,16 @@
+#include <stdint.h>
+#include <rv32i.h>
+
+int main(){
+    int counter = 0;
+    gpio_write_pin(10, 1); //write to a specific GPIO pin (automatically set pin to write mode)
+    delay_ticks(100); //after 100 cpu clock ticks
+    gpio_write_pin(10, 0); //write to a specific GPIO pin (automatically set pin to write mode)
+    delay_ticks(100); //after 100 cpu clock ticks
+    gpio_write_pin(10, 1); //write to a specific GPIO pin (automatically set pin to write mode)
+    delay_ticks(100); //after 100 cpu clock ticks
+    /*while(1)*/{
+        toggle_gpio(5); //toggle a specific GPIO pin (automatically set pin to write mode)
+        delay_ticks(100); //after 100 cpu clock ticks
+    }
+}

AngeloJacobo_RISC-V/test/extra/test_hygro.c

@@ -0,0 +1,25 @@
+#include <stdint.h>
+#include <stdio.h>
+#include <rv32i.h>
+
+int main(){
+    uart_print("Start HygroPMOD....\n");
+    
+  // Capture and print temperature and humidity data 2x per second
+  int val;
+  char msg[5]; //max of 5 chars
+  
+  while(1){
+      hygroi2c_begin();
+      val = (int) hygroi2c_getTemperature();
+      itoa(val, msg, 10);
+      uart_print("\nTemperature: ");
+      uart_print(msg);
+      
+      val = (int) hygroi2c_getHumidity();   
+      itoa(val, msg, 10);
+      uart_print("\nHumidity: ");
+      uart_print(msg);
+      delay_ms(1000); // 1 sample per second (temp + humidity) maximum
+  }
+}

AngeloJacobo_RISC-V/test/extra/test_i2c.c

@@ -0,0 +1,37 @@
+#include <stdint.h> 
+#include <rv32i.h>
+
+int main() {
+    i2c_write_address(0xaa);
+    i2c_write_byte('A');
+    i2c_write_byte('Z');
+    i2c_stop();
+    return 0;
+    
+    
+    /* I2C Address Finder
+    uart_print("\n\nSTART THE I2C ADDRES FINDER\n\n");
+    int address;
+    uint8_t ack; 
+    for(address=1; address<128; address++){ 
+        ack = i2c_write_address(address<<1); //rightmost bit is 0(write)
+        i2c_stop(); //make sure to stop before accessing new address slave
+        if(ack){
+            uart_print("\nFound the address:");
+            //char str_address[20];
+           // sprintf(str_address,"%d",address);
+            //uart_print(str_address);
+            uart_print("\n\n\n\n");
+        } 
+        else{
+            uart_print("\nWRONG:");
+            //char str_address[20];
+            //sprintf(str_address,"%d",address);
+            //uart_print(str_address);
+        }
+    }
+
+    return 0;
+    */    
+}
+

AngeloJacobo_RISC-V/test/extra/test_lcd.c

@@ -0,0 +1,26 @@
+#include <stdint.h>
+#include <rv32i.h>
+ 
+int main(void) {
+ 
+  uart_print("INITIALIZING LCD MODULE.....\n");
+  LCD_Init(0x4E); // Initialize LCD module with I2C address = 0x4E
+  uart_print("INITIALIZING DONE!\n\n");
+ 
+  LCD_Set_Cursor(1, 1);
+  LCD_Write_String(" Angelo Jacobo");
+  LCD_Set_Cursor(2, 1);
+  LCD_Write_String("BSECE-4A");
+  //while(1){
+  //}
+ 
+  return 1;
+}
+
+
+
+
+
+
+
+

AngeloJacobo_RISC-V/test/extra/test_timer.c

@@ -0,0 +1,26 @@
+#include <stdint.h>
+#include <rv32i.h>
+
+int finish;
+
+
+void __attribute__((interrupt)) trap_handler(void) {
+    mtime_set_timecmp(-1);
+    finish = 1;
+}
+int main() {
+    trap_handler_setup(trap_handler); //configure MTVEC to call "trap_handler" and initially disable all interrupts 
+    csr_set(MSTATUS, 1<<MSTATUS_MIE); //set global interrupt enable
+    csr_set(MIE, 1<<MIE_MTIE); //set timer interrupt enable
+    csr_set(MIP, 1<<MIP_MTIP); //set timer interrupt pending enable
+
+    mtime_set_timecmp(mtime_get_time() + 1000); //set time compare to +1000 ticks of current time
+    finish = 0;
+    
+    while(1){ //wait here until interrupt fires
+        if(finish) return 0;
+    }
+}
+
+
+

AngeloJacobo_RISC-V/test/extra/test_uart.c

@@ -0,0 +1,8 @@
+#include <stdint.h>
+#include <rv32i.h>
+
+int main() {
+    uart_print("Angelo Jacobo");
+    return 0;
+}
+

AngeloJacobo_RISC-V/test/extra/ultrasonic_sensor.c

@@ -0,0 +1,36 @@
+#include <stdint.h>
+#include <rv32i.h>
+
+int main(){
+    int trig_pin = 0;
+    int echo_pin = 1;
+    int pulse_duration_us;
+    int distance_cm;
+    char string[16]; //max of 16 chars
+    
+    gpio_set_mode_pin(trig_pin, 1); //set mode setting of a single GPIO pin(read = 0, write = 1)
+    gpio_set_mode_pin(echo_pin, 0); //set mode setting of a single GPIO pin(read = 0, write = 1)
+    uart_print("Start Ultrasonic Sensor\n\n");
+    
+    while(1) {
+    // set trig_pin for 10us
+    gpio_write_pin(trig_pin, 0); //write to a specific GPIO pin (automatically set pin to write mode)
+    delay_us(2); // delay function based on microseconds
+    gpio_write_pin(trig_pin, 1); //write to a specific GPIO pin (automatically set pin to write mode)
+    delay_us(10); // delay function based on microseconds
+    gpio_write_pin(trig_pin, 0); //write to a specific GPIO pin (automatically set pin to write mode)
+    
+    pulse_duration_us = gpio_pulse_duration_us(echo_pin, 1); //measure how long will be the high pulse
+    distance_cm = pulse_duration_us*(0.034/2); 
+    
+    //convert distance_cm to string
+    itoa(distance_cm, string, 10);
+    uart_print("Distance (cm): ");
+    uart_print(string);
+    uart_print("\n");
+    }
+    
+}
+
+
+

AngeloJacobo_RISC-V/test/freertos/FreeRTOSConfig.h

@@ -0,0 +1,143 @@
+/*
+    FreeRTOS V8.2.3 - Copyright (C) 2015 Real Time Engineers Ltd.
+    All rights reserved
+    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+    This file is part of the FreeRTOS distribution.
+    FreeRTOS is free software; you can redistribute it and/or modify it under
+    the terms of the GNU General Public License (version 2) as published by the
+    Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
+    ***************************************************************************
+    >>!   NOTE: The modification to the GPL is included to allow you to     !<<
+    >>!   distribute a combined work that includes FreeRTOS without being   !<<
+    >>!   obliged to provide the source code for proprietary components     !<<
+    >>!   outside of the FreeRTOS kernel.                                   !<<
+    ***************************************************************************
+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+    FOR A PARTICULAR PURPOSE.  Full license text is available on the following
+    link: http://www.freertos.org/a00114.html
+    ***************************************************************************
+     *                                                                       *
+     *    FreeRTOS provides completely free yet professionally developed,    *
+     *    robust, strictly quality controlled, supported, and cross          *
+     *    platform software that is more than just the market leader, it     *
+     *    is the industry's de facto standard.                               *
+     *                                                                       *
+     *    Help yourself get started quickly while simultaneously helping     *
+     *    to support the FreeRTOS project by purchasing a FreeRTOS           *
+     *    tutorial book, reference manual, or both:                          *
+     *    http://www.FreeRTOS.org/Documentation                              *
+     *                                                                       *
+    ***************************************************************************
+    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading
+    the FAQ page "My application does not run, what could be wrong?".  Have you
+    defined configASSERT()?
+    http://www.FreeRTOS.org/support - In return for receiving this top quality
+    embedded software for free we request you assist our global community by
+    participating in the support forum.
+    http://www.FreeRTOS.org/training - Investing in training allows your team to
+    be as productive as possible as early as possible.  Now you can receive
+    FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
+    Ltd, and the world's leading authority on the world's leading RTOS.
+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+    compatible FAT file system, and our tiny thread aware UDP/IP stack.
+    http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
+    Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
+    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
+    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS
+    licenses offer ticketed support, indemnification and commercial middleware.
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+    engineered and independently SIL3 certified version for use in safety and
+    mission critical applications that require provable dependability.
+    1 tab == 4 spaces!
+*/
+
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+//#include "clock_config.h"
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+/* See https://www.freertos.org/Using-FreeRTOS-on-RISC-V.html */
+
+
+/******************************************************************************
+ * Modified for the RISC-V core: https://github.com/AngeloJacobo/RISC-V
+ ******************************************************************************/
+#define configMTIME_BASE_ADDRESS 	( 0x80000000UL  )
+#define configMTIMECMP_BASE_ADDRESS ( 0x80000008UL  )
+
+#define configISR_STACK_SIZE_WORDS ( 128 )
+
+#define configUSE_PREEMPTION			1
+#define configUSE_IDLE_HOOK				1
+#define configUSE_TICK_HOOK				1
+#define configCPU_CLOCK_HZ				12000000 //Frequency in Hz at which the internal clock that drives the peripheral used to generate the tick interrupt will be executing
+#define configTICK_RATE_HZ				( ( TickType_t ) 1000 ) //
+#define configMAX_PRIORITIES			( 5 ) //Each task is assigned a priority from 0 to ( configMAX_PRIORITIES - 1 )
+#define configMINIMAL_STACK_SIZE		( ( unsigned short ) 128 ) /* Can be as low as 60 but some of the demo tasks that use this constant require it to be higher. */
+#define configSUPPORT_DYNAMIC_ALLOCATION  1
+#define configTOTAL_HEAP_SIZE			( ( size_t ) ( 14*1024 ) ) //RAM length is set to 16K
+                                            //You can make this configTOTAL_HEAP_SIZE as big as you want, the linker will issue an error when you’re running out of RAM.
+                                            //https://www.freertos.org/FreeRTOS_Support_Forum_Archive/March_2015/freertos_How_to_configure_the_Total_Heap_Size_5a94a34cj.html
+#define configMAX_TASK_NAME_LEN			( 16 ) //The maximum permissible length of the descriptive name given to a task when the task is created. 
+#define configUSE_TRACE_FACILITY		1
+#define configUSE_16_BIT_TICKS			0 //Defining configUSE_16_BIT_TICKS as 0 causes TickType_t to be defined (typedef'ed) as an unsigned 32bit type. 
+#define configIDLE_SHOULD_YIELD			0 //Setting configIDLE_SHOULD_YIELD to 0 prevents the idle task from yielding processing time until the end of its time slice. This ensure all tasks at the idle priority are allocated an equal amount of processing time
+#define configUSE_MUTEXES				1
+#define configQUEUE_REGISTRY_SIZE		8
+#define configCHECK_FOR_STACK_OVERFLOW	2
+#define configUSE_RECURSIVE_MUTEXES		1
+#define configUSE_MALLOC_FAILED_HOOK	1
+#define configUSE_APPLICATION_TASK_TAG	0
+#define configUSE_COUNTING_SEMAPHORES	1
+#define configGENERATE_RUN_TIME_STATS	0
+#define configTASK_NOTIFICATION_ARRAY_ENTRIES 4
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES 			0
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
+
+/* Software timer definitions. */
+#define configUSE_TIMERS				1
+#define configTIMER_TASK_PRIORITY		( configMAX_PRIORITIES - 1 )
+#define configTIMER_QUEUE_LENGTH		4
+#define configTIMER_TASK_STACK_DEPTH	( configMINIMAL_STACK_SIZE )
+
+
+
+/* Set the following definitions to 1 to include the API function, or zero
+to exclude the API function. */
+#define INCLUDE_vTaskPrioritySet			1
+#define INCLUDE_uxTaskPriorityGet			1
+#define INCLUDE_vTaskDelete					1
+#define INCLUDE_vTaskCleanUpResources		1
+#define INCLUDE_vTaskSuspend				1
+#define INCLUDE_vTaskDelayUntil				1
+#define INCLUDE_vTaskDelay					1
+#define INCLUDE_eTaskGetState				1
+#define INCLUDE_xTimerPendFunctionCall		1
+#define INCLUDE_xTaskAbortDelay				1
+#define INCLUDE_xTaskGetHandle				1
+#define INCLUDE_xSemaphoreGetMutexHolder	1
+
+
+/* Normal assert() semantics without relying on the provision of an assert.h
+header file. */
+#define configASSERT( x ) if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); __asm volatile( "ebreak" ); for( ;; ); }
+
+#endif /* FREERTOS_CONFIG_H */

AngeloJacobo_RISC-V/test/freertos/freertos.c

@@ -0,0 +1,449 @@
+// This is sourced from: https://github.com/stnolting/neorv32/blob/main/sw/example/demo_freeRTOS/main.c
+
+/* Standard includes. */
+#include <stdint.h>
+#include "rv32i.h"
+
+/* Kernel includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "queue.h"
+#include "semphr.h"
+
+// CONFIGURABLES 
+int moisture_sensor_pin = 0; //gpio pin for moisture sensor
+int motor_pump_pin = 1; //gpio pin fot water pump motor
+int trig_pin = 2; //trigger pin for ultrasonic sensor
+int echo_pin = 3; //echo pin for ultrasonic sensor 
+int buzzer_pin = 4; //buzzer pin 
+char buzzer_on_code[2] = "a"; //code for buzzer on
+char buzzer_off_code[2] = "b"; //code for buzzer off
+char water_pump_on_code[2] = "c"; //code for turning on water pump
+
+// Tasks function prototypes
+void vBluetoothReceive( void *pvParameters );
+void vBluetoothSend( void *pvParameters );
+void vHygroTempSensor( void *pvParameters );
+void vMoistureSensor( void *pvParameters );
+void vWaterPumpMotor( void *pvParameters );
+void vUltraSonicSensor( void *pvParameters );
+void vBuzzerOn( void *pvParameters );
+void vBuzzerOff( void *pvParameters );
+void vRTC( void *pvParameters );
+void vLCD( void *pvParameters );
+
+// Freertos functions
+extern void freertos_risc_v_trap_handler( void );
+void vApplicationTickHook( void );
+
+// Global variables shared by tasks
+char rx_data; //stores data received from bluetooth
+int humidity, temperature; //stores humidity and temperature values
+int buzzer_on; //turns on-off the buzzer
+int moist; //stores if moist detected
+int ultrasonic_distance_cm; //stores distance in cm detected by ultrasonic sensor
+SemaphoreHandle_t i2c_mutex; //mutex for accessing I2C peripheral
+
+
+// main function
+int main( void )
+{
+    BaseType_t vBluetoothReceive_task,
+                vBluetoothSend_task,
+                vHygroTempSensor_task,
+                vMoistureSensor_task,
+                vWaterPumpMotor_task,
+                vUltraSonicSensor_task,
+                vBuzzerOn_task,
+                vBuzzerOff_task,
+                vLCD_task;
+                
+    csr_write(MTVEC, (uint32_t) &freertos_risc_v_trap_handler); // set the trap handler to FreeRTOS
+    i2c_mutex = xSemaphoreCreateMutex(); //create semaphoe for accessing I2C peripheral
+    
+    // Create tasks
+    vBluetoothReceive_task = 
+        xTaskCreate( vBluetoothReceive,		/* The function that implements the task. */
+        "vBluetoothReceive", 						/* The text name assigned to the task - for debug only as it is not used by the kernel. */
+        100, 		                        /* The size of the stack to allocate to the task. */
+        NULL, 								/* The parameter passed to the task - not used in this case. */
+        1, 	                                /* The priority assigned to the task. */
+        NULL );	
+    
+     vBluetoothSend_task = 
+        xTaskCreate( vBluetoothSend,		/* The function that implements the task. */
+        "vBluetoothSend", 						/* The text name assigned to the task - for debug only as it is not used by the kernel. */
+        300, 		                        /* The size of the stack to allocate to the task. */
+        NULL, 								/* The parameter passed to the task - not used in this case. */
+        1, 	                                /* The priority assigned to the task. */
+        NULL );	
+    
+    vHygroTempSensor_task = 
+        xTaskCreate( vHygroTempSensor,		/* The function that implements the task. */
+        "vHygroTempSensor", 						/* The text name assigned to the task - for debug only as it is not used by the kernel. */
+        300, 		                        /* The size of the stack to allocate to the task. */
+        NULL, 								/* The parameter passed to the task - not used in this case. */
+        1, 	                                /* The priority assigned to the task. */
+        NULL );	
+
+    vMoistureSensor_task = 
+        xTaskCreate( vMoistureSensor,		/* The function that implements the task. */
+        "vMoistureSensor", 						/* The text name assigned to the task - for debug only as it is not used by the kernel. */
+        300, 		                        /* The size of the stack to allocate to the task. */
+        NULL, 								/* The parameter passed to the task - not used in this case. */
+        1, 	                                /* The priority assigned to the task. */
+        NULL );	
+    
+    vWaterPumpMotor_task = 
+        xTaskCreate( vWaterPumpMotor,		/* The function that implements the task. */
+        "vWaterPumpMotor", 						/* The text name assigned to the task - for debug only as it is not used by the kernel. */
+        200, 		                        /* The size of the stack to allocate to the task. */
+        NULL, 								/* The parameter passed to the task - not used in this case. */
+        1, 	                                /* The priority assigned to the task. */
+        NULL );	
+
+    vUltraSonicSensor_task = 
+        xTaskCreate( vUltraSonicSensor,		/* The function that implements the task. */
+        "vUltraSonicSensor", 						/* The text name assigned to the task - for debug only as it is not used by the kernel. */
+        300, 		                        /* The size of the stack to allocate to the task. */
+        NULL, 								/* The parameter passed to the task - not used in this case. */
+        1, 	                                /* The priority assigned to the task. */
+        NULL );	
+    
+    vBuzzerOn_task = 
+        xTaskCreate( vBuzzerOn,		/* The function that implements the task. */
+        "vBuzzerOn", 						/* The text name assigned to the task - for debug only as it is not used by the kernel. */
+        200, 		                        /* The size of the stack to allocate to the task. */
+        NULL, 								/* The parameter passed to the task - not used in this case. */
+        1, 	                                /* The priority assigned to the task. */
+        NULL );	
+
+    vBuzzerOff_task = 
+        xTaskCreate( vBuzzerOff,		/* The function that implements the task. */
+        "vBuzzerOff", 						/* The text name assigned to the task - for debug only as it is not used by the kernel. */
+        200, 		                        /* The size of the stack to allocate to the task. */
+        NULL, 								/* The parameter passed to the task - not used in this case. */
+        1, 	                                /* The priority assigned to the task. */
+        NULL );	
+    
+    vLCD_task = 
+        xTaskCreate( vLCD,		/* The function that implements the task. */
+        "vLCD", 						/* The text name assigned to the task - for debug only as it is not used by the kernel. */
+        300, 		                        /* The size of the stack to allocate to the task. */
+        NULL, 								/* The parameter passed to the task - not used in this case. */
+        1, 	                                /* The priority assigned to the task. */
+        NULL );	
+    
+
+    // Check if all task creation passed
+   
+   	if( vBluetoothReceive_task != pdPASS )
+    {
+        uart_print("vBluetoothReceive Task Failed to Create\n");
+        return(1);
+    }
+   
+   	if( vBluetoothSend_task != pdPASS )
+    {
+        uart_print("vBluetoothSend Task Failed to Create\n");
+        return(1);
+    }
+   
+   	if( vHygroTempSensor_task != pdPASS )
+    {
+        uart_print("vHygroTempSensor Task Failed to Create\n");
+        return(1);
+    }
+   
+   	if( vMoistureSensor_task != pdPASS )
+    {
+        uart_print("vMoistureSensor Task Failed to Create\n");
+        return(1);
+    }
+    
+   	if( vWaterPumpMotor_task != pdPASS )
+    {
+        uart_print("vWaterPumpMotor Task Failed to Create\n");
+        return(1);
+    }
+   
+   	if( vUltraSonicSensor_task != pdPASS )
+    {
+        uart_print("vUltraSonicSensor Task Failed to Create\n");
+        return(1);
+    }
+    
+   	if( vBuzzerOn_task != pdPASS )
+    {
+        uart_print("vBuzzerOn Task Failed to Create\n");
+        return(1);
+    }
+    
+   	if( vBuzzerOff_task != pdPASS )
+    {
+        uart_print("vBuzzerOff Task Failed to Create\n");
+        return(1);
+    }
+   
+   	if( vLCD_task != pdPASS )
+    {
+        uart_print("vLCD Task Failed to Create\n");
+        return(1);
+    }
+   
+	/* Start the tasks and timer running. */
+	vTaskStartScheduler();
+
+	uart_print("ERROR: You reached past the vTaskStartScheduler()");
+
+}
+
+void vBluetoothReceive( void *pvParameters ){
+    int buffer_full;
+    while(1){
+        buffer_full = uart_rx_buffer_full(); //check if read buffer is full and data can be read
+        if(buffer_full){
+            rx_data = uart_read(); //read data from buffer (make sure to check first if rx buffer is full)
+        }
+    }
+}
+
+void vBluetoothSend( void *pvParameters ){
+    char msg[10];
+    while(1){
+        sprintf_(msg, "%d", temperature); //convert temperatue value in integer to char array
+        uart_print(msg);  //print serially to bluetooth
+        uart_print(";"); //delimiter
+        sprintf_(msg, "%d", humidity); //convert humidity value in integer to char array
+        uart_print(msg); //print serially to bluetooth
+        uart_print(";"); //delimiter
+        
+        if(buzzer_on){ 
+            uart_print(buzzer_on_code); //code for buzzer on
+            uart_print(";"); //delimiter
+        }
+        else {
+            uart_print(buzzer_off_code); //code for buzzer off
+            uart_print(";"); //delimiter
+        }
+        uart_print("\n");
+        delay_ms(500);
+    }
+}
+
+void vHygroTempSensor( void *pvParameters ){
+    while(1){ 
+      xSemaphoreTake(i2c_mutex, portMAX_DELAY); //gain access to the i2c peripheral and not let other task to use it for the meantime
+      hygroi2c_begin(); //restart hygroi2c sensor
+      xSemaphoreGive(i2c_mutex); //release the mutex
+      delay_ms(1); //add delay between taking semaphores
+      
+      xSemaphoreTake(i2c_mutex, portMAX_DELAY); //gain access to the i2c peripheral and not let other task to use it for the meantime
+      temperature = (int)hygroi2c_getTemperature(); //retrieve temperature value
+      xSemaphoreGive(i2c_mutex); //release the mutex
+      delay_ms(1);
+      
+      xSemaphoreTake(i2c_mutex, portMAX_DELAY); //gain access to the i2c peripheral and not let other task to use it for the meantim
+      humidity = (int)hygroi2c_getHumidity(); //retrieve humidity value
+      xSemaphoreGive(i2c_mutex);
+      delay_ms(1);
+    }
+}
+
+void vMoistureSensor( void *pvParameters ){
+    while(1){
+        moist = !gpio_read_pin(moisture_sensor_pin); //moisture sensor is active low (0 when moist detected)
+        delay_ms(1);
+    }
+}
+
+void vWaterPumpMotor( void *pvParameters ){
+   
+    gpio_write_pin(motor_pump_pin, 1);
+    while(1){
+        if(!moist) {
+           gpio_write_pin(motor_pump_pin, 0);
+        }
+        else{
+           gpio_write_pin(motor_pump_pin, 1);
+        }
+        if(rx_data == water_pump_on_code[0]) {
+            rx_data = 0;
+            gpio_write_pin(motor_pump_pin, 0);
+            delay_ms(3000);
+            gpio_write_pin(motor_pump_pin, 1);
+        }
+        delay_ms(1);
+    }
+}
+
+void vUltraSonicSensor( void *pvParameters ){
+    while(1){
+    ultrasonic_distance_cm = ultrasonic_sensor_cm(trig_pin, echo_pin); // returns distance in cm detected by the ultrasonic sensor
+    delay_ms(1);
+    }
+}
+
+void vBuzzerOff( void *pvParameters ){ 
+    while(1){
+        if(rx_data == buzzer_off_code[0]){
+            gpio_write_pin(buzzer_pin, 0); //turn off buzzer using serial line
+            rx_data = 0;
+            buzzer_on = 0;
+            gpio_write_pin(8, 0); //buzzer will turn on when distance detected is less than 10cm
+        }
+        delay_ms(1);
+    }
+} 
+
+void vBuzzerOn( void *pvParameters ){
+    gpio_write_pin(buzzer_pin, 0); //buzzer off
+    buzzer_on = 0;
+    delay_ms(5000);
+    while(1){  
+        if(ultrasonic_distance_cm < 10){ 
+            gpio_write_pin(buzzer_pin, 1); //buzzer will turn on when distance detected is less than 10cm
+            buzzer_on = 1; 
+            delay_ms(10000); //buzzer remain on for 10 sec
+        }
+        else{
+            gpio_write_pin(buzzer_pin, 0); //else turn buzzer off
+            buzzer_on = 0;
+        }
+        delay_ms(1);
+    }
+}
+
+void vLCD( void *pvParameters ){
+    char msg[10];
+    xSemaphoreTake(i2c_mutex, portMAX_DELAY); //gain access to the i2c peripheral and not let other task to use it for the meantime
+    LCD_Init(); // Initialize LCD module
+    LCD_Set_Cursor(1, 1);
+    LCD_Write_String("RISC-V with RTOS");
+    LCD_Set_Cursor(2, 1);
+    LCD_Write_String("Team GraduatECEs");
+    delay_ms(1000);
+    LCD_Clear();
+    xSemaphoreGive(i2c_mutex); //release the mutex
+    while(1){
+        xSemaphoreTake(i2c_mutex, portMAX_DELAY); //gain access to the i2c peripheral and not let other task to use it for the meantime
+        LCD_Set_Cursor(1, 1);
+        xSemaphoreGive(i2c_mutex); //release the mutex
+        delay_ms(1); 
+ 
+        xSemaphoreTake(i2c_mutex, portMAX_DELAY); //gain access to the i2c peripheral and not let other task to use it for the meantime
+        LCD_Write_String("Temp:");
+        xSemaphoreGive(i2c_mutex); //release the mutex
+        delay_ms(1); 
+                
+        sprintf_(msg, "%d", temperature); //convert humidity value in integer to char array
+        xSemaphoreTake(i2c_mutex, portMAX_DELAY); //gain access to the i2c peripheral and not let other task to use it for the meantime
+        LCD_Write_String(msg);
+        xSemaphoreGive(i2c_mutex); //release the mutex
+        delay_ms(1); 
+                
+        xSemaphoreTake(i2c_mutex, portMAX_DELAY); //gain access to the i2c peripheral and not let other task to use it for the meantime
+        LCD_Write_String("C ");
+        xSemaphoreGive(i2c_mutex); //release the mutex
+        delay_ms(1); 
+        
+        xSemaphoreTake(i2c_mutex, portMAX_DELAY); //gain access to the i2c peripheral and not let other task to use it for the meantime
+        LCD_Write_String("Hum:");
+        xSemaphoreGive(i2c_mutex); //release the mutex
+        delay_ms(1); 
+        
+        sprintf_(msg, "%d", humidity); //convert humidity value in integer to char array
+        xSemaphoreTake(i2c_mutex, portMAX_DELAY); //gain access to the i2c peripheral and not let other task to use it for the meantime
+        LCD_Write_String(msg);
+        xSemaphoreGive(i2c_mutex); //release the mutex
+        delay_ms(1); 
+        
+        xSemaphoreTake(i2c_mutex, portMAX_DELAY); //gain access to the i2c peripheral and not let other task to use it for the meantime
+        LCD_Write_String("%");
+        xSemaphoreGive(i2c_mutex); //release the mutex
+        delay_ms(1); 
+    }
+}
+
+
+/* This handler is responsible for handling all interrupts. Only the machine timer interrupt is handled by the kernel. */
+void SystemIrqHandler( uint32_t mcause )
+{
+  uart_print("freeRTOS: Unknown interrupt \n");
+}
+
+void vApplicationTickHook( void ){
+}
+
+
+
+
+void vApplicationMallocFailedHook( void )
+{
+	/* vApplicationMallocFailedHook() will only be called if
+	configUSE_MALLOC_FAILED_HOOK is set to 1 in FreeRTOSConfig.h.  It is a hook
+	function that will get called if a call to pvPortMalloc() fails.
+	pvPortMalloc() is called internally by the kernel whenever a task, queue,
+	timer or semaphore is created.  It is also called by various parts of the
+	demo application.  If heap_1.c or heap_2.c are used, then the size of the
+	heap available to pvPortMalloc() is defined by configTOTAL_HEAP_SIZE in
+	FreeRTOSConfig.h, and the xPortGetFreeHeapSize() API function can be used
+	to query the size of free heap space that remains (although it does not
+	provide information on how the remaining heap might be fragmented). */
+	taskDISABLE_INTERRUPTS();
+    uart_print("FreeRTOS_FAULT: vApplicationMallocFailedHook (solution: increase 'configTOTAL_HEAP_SIZE' in FreeRTOSConfig.h)\n");
+    __asm volatile( "nop" );
+	__asm volatile( "ebreak" );
+	for( ;; );
+}
+/*-----------------------------------------------------------*/
+
+void vApplicationIdleHook( void )
+{
+	/* vApplicationIdleHook() will only be called if configUSE_IDLE_HOOK is set
+	to 1 in FreeRTOSConfig.h.  It will be called on each iteration of the idle
+	task.  It is essential that code added to this hook function never attempts
+	to block in any way (for example, call xQueueReceive() with a block time
+	specified, or call vTaskDelay()).  If the application makes use of the
+	vTaskDelete() API function (as this demo application does) then it is also
+	important that vApplicationIdleHook() is permitted to return to its calling
+	function, because it is the responsibility of the idle task to clean up
+	memory allocated by the kernel to any task that has since been deleted. */
+}
+
+/*-----------------------------------------------------------*/
+
+void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName )
+{
+	( void ) pcTaskName;
+	( void ) pxTask;
+
+	/* Run time stack overflow checking is performed if
+	configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2.  This hook
+	function is called if a stack overflow is detected. */
+	taskDISABLE_INTERRUPTS();
+    uart_print("FreeRTOS_FAULT: vApplicationStackOverflowHook\n");
+    __asm volatile( "nop" );
+    __asm volatile( "nop" );
+	__asm volatile( "ebreak" );
+	for( ;; );
+}
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

AngeloJacobo_RISC-V/test/freertos/freertos_old.c

@@ -0,0 +1,254 @@
+// This is sourced from: https://github.com/stnolting/neorv32/blob/main/sw/example/demo_freeRTOS/main.c
+
+/* Standard includes. */
+#include <stdint.h>
+#include "rv32i.h"
+
+/* Kernel includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "queue.h"
+#include "semphr.h"
+
+
+void vApplicationTickHook( void );
+void vUartSend( void *pvParameters );
+void vUARTReceive( void *pvParameters );
+void vToggleGPIO( void *pvParameters );
+void vLCD( void *pvParameters );
+extern void freertos_risc_v_trap_handler( void );
+
+char rx_data[2];
+SemaphoreHandle_t uart_mutex;
+
+int main( void )
+{
+    BaseType_t a;
+    BaseType_t b;
+    BaseType_t c;
+    BaseType_t d;
+    uart_print("FreeRTOS DEMO\n");
+    csr_write(MTVEC, (uint32_t) &freertos_risc_v_trap_handler);
+    uart_mutex = xSemaphoreCreateMutex();
+    
+	a = xTaskCreate( vUartSend,				            /* The function that implements the task. */
+				"UART_SEND", 						/* The text name assigned to the task - for debug only as it is not used by the kernel. */
+				500, 		/* The size of the stack to allocate to the task. */
+				NULL, 								/* The parameter passed to the task - not used in this case. */
+				1, 	                                /* The priority assigned to the task. */
+				NULL );								/* The task handle is not required, so NULL is passed. */
+	
+	if( a != pdPASS )
+   {
+        uart_print("First Task Failed to Create\n");
+        return(1);
+    }
+    
+    b = xTaskCreate( vLCD,				            /* The function that implements the task. */
+		"LCD_WRITE", 						/* The text name assigned to the task - for debug only as it is not used by the kernel. */
+		500, 		/* The size of the stack to allocate to the task. */
+		NULL, 								/* The parameter passed to the task - not used in this case. */
+		1, 	                                /* The priority assigned to the task. */
+		NULL );	
+    
+	if( b != pdPASS )
+    {
+        uart_print("Second Task Failed to Create\n");
+        return(2);
+    }
+    
+    c = xTaskCreate( vUARTReceive,				            /* The function that implements the task. */
+		"LCD_WRITE", 						/* The text name assigned to the task - for debug only as it is not used by the kernel. */
+		500, 		/* The size of the stack to allocate to the task. */
+		NULL, 								/* The parameter passed to the task - not used in this case. */
+		1, 	                                /* The priority assigned to the task. */
+		NULL );	
+    
+	if( c != pdPASS )
+    {
+        uart_print("Third Task Failed to Create\n");
+        return(3);
+    }
+    
+    d = xTaskCreate( vToggleGPIO,				            /* The function that implements the task. */
+		"LCD_WRITE", 						/* The text name assigned to the task - for debug only as it is not used by the kernel. */
+		500, 		/* The size of the stack to allocate to the task. */
+		NULL, 								/* The parameter passed to the task - not used in this case. */
+		1, 	                                /* The priority assigned to the task. */
+		NULL );	
+    
+	if( d != pdPASS )
+    {
+        uart_print("Fourth Task Failed to Create\n");
+        return(3);
+    }
+
+	/* Start the tasks and timer running. */
+	vTaskStartScheduler();
+
+	uart_print("ERROR: You reached past the vTaskStartScheduler()");
+
+}
+
+void vUartSend( void *pvParameters ){
+    while(1){
+        xSemaphoreTake(uart_mutex, portMAX_DELAY);
+        uart_print("This is the 1st line and this is pretty long do you understand?\n");
+        xSemaphoreGive(uart_mutex);
+        vTaskDelay(1); //100 ticks
+        xSemaphoreTake(uart_mutex, portMAX_DELAY);
+        uart_print("This is the 2nd line and I guess I'm already out of words. Let's see if I can think of more things to say or am I stuck?\n");
+        xSemaphoreGive(uart_mutex);
+        vTaskDelay(1); //100 ticks
+        xSemaphoreTake(uart_mutex, portMAX_DELAY);
+        uart_print("This is the 3rd line and this is pretty long do you understand?\n");
+        xSemaphoreGive(uart_mutex);
+        vTaskDelay(1); //100 ticks
+        xSemaphoreTake(uart_mutex, portMAX_DELAY);
+        uart_print("This is the 4th line and I guess I'm already out of words. Let's see if I can think of more things to say or am I stuck?\n");
+        xSemaphoreGive(uart_mutex);
+        vTaskDelay(1); //100 ticks
+    }
+    
+}
+
+void vUARTReceive( void *pvParameters ){
+    int buffer_full;
+    rx_data[1] = '\0';
+    while(1){
+        buffer_full = uart_rx_buffer_full(); //check if read buffer is full and data can be read
+        if(buffer_full){
+            rx_data[0] = uart_read(); //read data from buffer (make sure to check first if rx buffer is full)
+        }
+        xSemaphoreTake(uart_mutex, portMAX_DELAY);
+        uart_print("This is from vUARTReceive, is this still jumbled?\n");
+        xSemaphoreGive(uart_mutex);
+        vTaskDelay(1); //100 ticks
+    }
+}
+
+void vToggleGPIO( void *pvParameters ){
+    while(1){
+        if(rx_data[0] == '0'){
+            gpio_write_pin(8, 0); //write to a specific GPIO pin (automatically set pin to write mode)
+            gpio_write_pin(9, 0); //write to a specific GPIO pin (automatically set pin to write mode)
+            gpio_write_pin(10, 0); //write to a specific GPIO pin (automatically set pin to write mode)
+            gpio_write_pin(11, 0); //write to a specific GPIO pin (automatically set pin to write mode)
+        }
+        else if(rx_data[0] == '1') {
+            gpio_write_pin(8, 1); //write to a specific GPIO pin (automatically set pin to write mode)
+            gpio_write_pin(9, 1); //write to a specific GPIO pin (automatically set pin to write mode)
+            gpio_write_pin(10, 1); //write to a specific GPIO pin (automatically set pin to write mode)
+            gpio_write_pin(11, 1); //write to a specific GPIO pin (automatically set pin to write mode)
+        }
+    }
+}
+
+void vLCD( void *pvParameters ){
+    int counter = 0;
+    int length = 0;
+    char string[16]; //max of 16 chars
+    //uart_print("INITIALIZING LCD MODULE.....\n");
+    LCD_Init(0x4E); // Initialize LCD module with I2C address = 0x4E
+    //uart_print("INITIALIZING DONE!\n\n");
+
+    LCD_Set_Cursor(1, 1);
+    LCD_Write_String(" Angelo Jacobo");
+    LCD_Set_Cursor(2, 3);
+    //LCD_Clear();
+    delay_ms(1000);
+    while(1){
+        //convert counter to string
+        sprintf_(string, "%d", counter);
+        //print to LCD
+        LCD_Set_Cursor(2, 7);
+        LCD_Write_String(string);
+        delay_ms(1000); 
+        //increment counter
+        counter++;
+    }
+}
+
+
+
+/* This handler is responsible for handling all interrupts. Only the machine timer interrupt is handled by the kernel. */
+void SystemIrqHandler( uint32_t mcause )
+{
+  uart_print("freeRTOS: Unknown interrupt \n");
+}
+
+void vApplicationTickHook( void ){
+}
+
+
+
+
+void vApplicationMallocFailedHook( void )
+{
+	/* vApplicationMallocFailedHook() will only be called if
+	configUSE_MALLOC_FAILED_HOOK is set to 1 in FreeRTOSConfig.h.  It is a hook
+	function that will get called if a call to pvPortMalloc() fails.
+	pvPortMalloc() is called internally by the kernel whenever a task, queue,
+	timer or semaphore is created.  It is also called by various parts of the
+	demo application.  If heap_1.c or heap_2.c are used, then the size of the
+	heap available to pvPortMalloc() is defined by configTOTAL_HEAP_SIZE in
+	FreeRTOSConfig.h, and the xPortGetFreeHeapSize() API function can be used
+	to query the size of free heap space that remains (although it does not
+	provide information on how the remaining heap might be fragmented). */
+	taskDISABLE_INTERRUPTS();
+    uart_print("FreeRTOS_FAULT: vApplicationMallocFailedHook (solution: increase 'configTOTAL_HEAP_SIZE' in FreeRTOSConfig.h)\n");
+    __asm volatile( "nop" );
+	__asm volatile( "ebreak" );
+	for( ;; );
+}
+/*-----------------------------------------------------------*/
+
+void vApplicationIdleHook( void )
+{
+	/* vApplicationIdleHook() will only be called if configUSE_IDLE_HOOK is set
+	to 1 in FreeRTOSConfig.h.  It will be called on each iteration of the idle
+	task.  It is essential that code added to this hook function never attempts
+	to block in any way (for example, call xQueueReceive() with a block time
+	specified, or call vTaskDelay()).  If the application makes use of the
+	vTaskDelete() API function (as this demo application does) then it is also
+	important that vApplicationIdleHook() is permitted to return to its calling
+	function, because it is the responsibility of the idle task to clean up
+	memory allocated by the kernel to any task that has since been deleted. */
+}
+
+/*-----------------------------------------------------------*/
+
+void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName )
+{
+	( void ) pcTaskName;
+	( void ) pxTask;
+
+	/* Run time stack overflow checking is performed if
+	configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2.  This hook
+	function is called if a stack overflow is detected. */
+	taskDISABLE_INTERRUPTS();
+    uart_print("FreeRTOS_FAULT: vApplicationStackOverflowHook\n");
+    __asm volatile( "nop" );
+    __asm volatile( "nop" );
+	__asm volatile( "ebreak" );
+	for( ;; );
+}
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

AngeloJacobo_RISC-V/test/freertos/freertos_risc_v_chip_specific_extensions.h

@@ -0,0 +1,74 @@
+/*
+ * FreeRTOS Kernel V10.3.1
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*
+ * The FreeRTOS kernel's RISC-V port is split between the the code that is
+ * common across all currently supported RISC-V chips (implementations of the
+ * RISC-V ISA), and code that tailors the port to a specific RISC-V chip:
+ *
+ * + FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S contains the code that
+ *   is common to all currently supported RISC-V chips.  There is only one
+ *   portASM.S file because the same file is built for all RISC-V target chips.
+ *
+ * + Header files called freertos_risc_v_chip_specific_extensions.h contain the
+ *   code that tailors the FreeRTOS kernel's RISC-V port to a specific RISC-V
+ *   chip.  There are multiple freertos_risc_v_chip_specific_extensions.h files
+ *   as there are multiple RISC-V chip implementations.
+ *
+ * !!!NOTE!!!
+ * TAKE CARE TO INCLUDE THE CORRECT freertos_risc_v_chip_specific_extensions.h
+ * HEADER FILE FOR THE CHIP IN USE.  This is done using the assembler's (not the
+ * compiler's!) include path.  For example, if the chip in use includes a core
+ * local interrupter (CLINT) and does not include any chip specific register
+ * extensions then add the path below to the assembler's include path:
+ * FreeRTOS\Source\portable\GCC\RISC-V-RV32\chip_specific_extensions\RV32I_CLINT_no_extensions
+ *
+ */
+
+/*
+ * NEORV32 chip specific extensions
+ */
+
+
+#ifndef __FREERTOS_RISC_V_EXTENSIONS_H__
+#define __FREERTOS_RISC_V_EXTENSIONS_H__
+
+#define portasmHAS_SIFIVE_CLINT 0
+#define portasmHAS_MTIME 1
+#define portasmADDITIONAL_CONTEXT_SIZE 0 /* Must be even number on 32-bit cores. */
+
+.macro portasmSAVE_ADDITIONAL_REGISTERS
+	/* No additional registers to save, so this macro does nothing. */
+	.endm
+
+.macro portasmRESTORE_ADDITIONAL_REGISTERS
+	/* No additional registers to restore, so this macro does nothing. */
+	.endm
+
+#endif /* __FREERTOS_RISC_V_EXTENSIONS_H__ */
+
+

AngeloJacobo_RISC-V/test/freertos/main_blinky.c

@@ -0,0 +1,305 @@
+// This is sourced from: https://github.com/stnolting/neorv32/blob/main/sw/example/demo_freeRTOS/blinky_demo/main_blinky.c
+
+/*
+ * FreeRTOS Kernel V10.3.0
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/******************************************************************************
+ * NOTE 1:  This project provides two demo applications.  A simple blinky
+ * style project, and a more comprehensive test and demo application.  The
+ * mainCREATE_SIMPLE_BLINKY_DEMO_ONLY setting in main.c is used to select
+ * between the two.  See the notes on using mainCREATE_SIMPLE_BLINKY_DEMO_ONLY
+ * in main.c.  This file implements the simply blinky style version.
+ *
+ * NOTE 2:  This file only contains the source code that is specific to the
+ * basic demo.  Generic functions, such FreeRTOS hook functions, and functions
+ * required to configure the hardware are defined in main.c.
+ ******************************************************************************
+ *
+ * main_blinky() creates one queue, and two tasks.  It then starts the
+ * scheduler.
+ *
+ * The Queue Send Task:
+ * The queue send task is implemented by the prvQueueSendTask() function in
+ * this file.  prvQueueSendTask() sits in a loop that causes it to repeatedly
+ * block for 1000 milliseconds, before sending the value 100 to the queue that
+ * was created within main_blinky().  Once the value is sent, the task loops
+ * back around to block for another 1000 milliseconds...and so on.
+ *
+ * The Queue Receive Task:
+ * The queue receive task is implemented by the prvQueueReceiveTask() function
+ * in this file.  prvQueueReceiveTask() sits in a loop where it repeatedly
+ * blocks on attempts to read data from the queue that was created within
+ * main_blinky().  When data is received, the task checks the value of the
+ * data, and if the value equals the expected 100, writes 'Blink' to the UART
+ * (the UART is used in place of the LED to allow easy execution in QEMU).  The
+ * 'block time' parameter passed to the queue receive function specifies that
+ * the task should be held in the Blocked state indefinitely to wait for data to
+ * be available on the queue.  The queue receive task will only leave the
+ * Blocked state when the queue send task writes to the queue.  As the queue
+ * send task writes to the queue every 1000 milliseconds, the queue receive
+ * task leaves the Blocked state every 1000 milliseconds, and therefore toggles
+ * the LED every 200 milliseconds.
+ */
+
+/* Standard includes. */
+#include <stdio.h>
+#include <string.h>
+#include <unistd.h>
+#include "rv32i.h"
+
+/* Kernel includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "queue.h"
+
+/* Priorities used by the tasks. */
+#define mainQUEUE_RECEIVE_TASK_PRIORITY		( tskIDLE_PRIORITY + 2 )
+#define	mainQUEUE_SEND_TASK_PRIORITY		( tskIDLE_PRIORITY + 1 )
+
+/* The rate at which data is sent to the queue.  The 200ms value is converted
+to ticks using the pdMS_TO_TICKS() macro. */
+#define mainQUEUE_SEND_FREQUENCY_MS			pdMS_TO_TICKS( 1000 )
+
+/* The maximum number items the queue can hold.  The priority of the receiving
+task is above the priority of the sending task, so the receiving task will
+preempt the sending task and remove the queue items each time the sending task
+writes to the queue.  Therefore the queue will never have more than one item in
+it at any time, and even with a queue length of 1, the sending task will never
+find the queue full. */
+#define mainQUEUE_LENGTH					( 1 )
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Called by main when mainCREATE_SIMPLE_BLINKY_DEMO_ONLY is set to 1 in
+ * main.c.
+ */
+void main_blinky( void );
+
+/*
+ * The tasks as described in the comments at the top of this file.
+ */
+static void prvQueueReceiveTask( void *pvParameters );
+static void prvQueueSendTask( void *pvParameters );
+
+/*-----------------------------------------------------------*/
+
+/* The queue used by both tasks. */
+static QueueHandle_t xQueue = NULL;
+
+/*-----------------------------------------------------------*/
+
+
+void vApplicationTickHook( void );
+extern void freertos_risc_v_trap_handler( void );
+
+
+int main( void )
+{
+    uart_print("FreeRTOS DEMO\n");
+    csr_write(MTVEC, (uint32_t) &freertos_risc_v_trap_handler);
+    main_blinky();
+}
+
+
+/* This handler is responsible for handling all interrupts. Only the machine timer interrupt is handled by the kernel. */
+void SystemIrqHandler( uint32_t mcause )
+{
+  uart_print("freeRTOS: Unknown interrupt \n");
+}
+
+void vApplicationTickHook( void ){
+}
+
+
+
+
+void vApplicationMallocFailedHook( void )
+{
+	/* vApplicationMallocFailedHook() will only be called if
+	configUSE_MALLOC_FAILED_HOOK is set to 1 in FreeRTOSConfig.h.  It is a hook
+	function that will get called if a call to pvPortMalloc() fails.
+	pvPortMalloc() is called internally by the kernel whenever a task, queue,
+	timer or semaphore is created.  It is also called by various parts of the
+	demo application.  If heap_1.c or heap_2.c are used, then the size of the
+	heap available to pvPortMalloc() is defined by configTOTAL_HEAP_SIZE in
+	FreeRTOSConfig.h, and the xPortGetFreeHeapSize() API function can be used
+	to query the size of free heap space that remains (although it does not
+	provide information on how the remaining heap might be fragmented). */
+	taskDISABLE_INTERRUPTS();
+    uart_print("FreeRTOS_FAULT: vApplicationMallocFailedHook (solution: increase 'configTOTAL_HEAP_SIZE' in FreeRTOSConfig.h)\n");
+    __asm volatile( "nop" );
+	__asm volatile( "ebreak" );
+	for( ;; );
+}
+/*-----------------------------------------------------------*/
+
+void vApplicationIdleHook( void )
+{
+	/* vApplicationIdleHook() will only be called if configUSE_IDLE_HOOK is set
+	to 1 in FreeRTOSConfig.h.  It will be called on each iteration of the idle
+	task.  It is essential that code added to this hook function never attempts
+	to block in any way (for example, call xQueueReceive() with a block time
+	specified, or call vTaskDelay()).  If the application makes use of the
+	vTaskDelete() API function (as this demo application does) then it is also
+	important that vApplicationIdleHook() is permitted to return to its calling
+	function, because it is the responsibility of the idle task to clean up
+	memory allocated by the kernel to any task that has since been deleted. */
+}
+
+/*-----------------------------------------------------------*/
+
+void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName )
+{
+	( void ) pcTaskName;
+	( void ) pxTask;
+
+	/* Run time stack overflow checking is performed if
+	configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2.  This hook
+	function is called if a stack overflow is detected. */
+	taskDISABLE_INTERRUPTS();
+    uart_print("FreeRTOS_FAULT: vApplicationStackOverflowHook\n");
+    __asm volatile( "nop" );
+    __asm volatile( "nop" );
+	__asm volatile( "ebreak" );
+	for( ;; );
+}
+
+
+void main_blinky( void )
+{
+	/* Create the queue. */
+	xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( uint32_t ) );
+
+	if( xQueue != NULL )
+	{
+		/* Start the two tasks as described in the comments at the top of this
+		file. */
+		xTaskCreate( prvQueueReceiveTask,				/* The function that implements the task. */
+					"Rx", 								/* The text name assigned to the task - for debug only as it is not used by the kernel. */
+					configMINIMAL_STACK_SIZE * 2U, 		/* The size of the stack to allocate to the task. */
+					NULL, 								/* The parameter passed to the task - not used in this case. */
+					mainQUEUE_RECEIVE_TASK_PRIORITY, 	/* The priority assigned to the task. */
+					NULL );								/* The task handle is not required, so NULL is passed. */
+
+		xTaskCreate( prvQueueSendTask, "TX", configMINIMAL_STACK_SIZE * 2U, NULL, mainQUEUE_SEND_TASK_PRIORITY, NULL );
+
+		/* Start the tasks and timer running. */
+		vTaskStartScheduler();
+	}
+
+	/* If all is well, the scheduler will now be running, and the following
+	line will never be reached.  If the following line does execute, then
+	there was insufficient FreeRTOS heap memory available for the Idle and/or
+	timer tasks to be created.  See the memory management section on the
+	FreeRTOS web site for more details on the FreeRTOS heap
+	http://www.freertos.org/a00111.html. */
+	for( ;; );
+}
+/*-----------------------------------------------------------*/
+
+static void prvQueueSendTask( void *pvParameters )
+{
+TickType_t xNextWakeTime;
+const unsigned long ulValueToSend = 100UL;
+BaseType_t xReturned;
+
+	/* Remove compiler warning about unused parameter. */
+	( void ) pvParameters;
+
+	/* Initialise xNextWakeTime - this only needs to be done once. */
+	xNextWakeTime = xTaskGetTickCount();
+
+	for( ;; )
+	{
+		/* Place this task in the blocked state until it is time to run again. */
+		vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS );
+
+		/* Send to the queue - causing the queue receive task to unblock and
+		toggle the LED.  0 is used as the block time so the sending operation
+		will not block - it shouldn't need to block as the queue should always
+		be empty at this point in the code. */
+		xReturned = xQueueSend( xQueue, &ulValueToSend, 0U );
+		configASSERT( xReturned == pdPASS );
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvQueueReceiveTask( void *pvParameters )
+{
+unsigned long ulReceivedValue;
+const unsigned long ulExpectedValue = 100UL;
+char * const pcPassMessage = "Blink\r\n";
+char * const pcFailMessage = "Unexpected value received\r\n";
+
+	/* Remove compiler warning about unused parameter. */
+	( void ) pvParameters;
+
+	for( ;; )
+	{
+		/* Wait until something arrives in the queue - this task will block
+		indefinitely provided INCLUDE_vTaskSuspend is set to 1 in
+		FreeRTOSConfig.h. */
+		xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY );
+
+		/*  To get here something must have been received from the queue, but
+		is it the expected value?  If it is, toggle the LED. */
+		if( ulReceivedValue == ulExpectedValue )
+		{
+			uart_print( pcPassMessage );
+			ulReceivedValue = 0U;
+		}
+		else
+		{
+			uart_print( pcFailMessage );
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

AngeloJacobo_RISC-V/test/lib/clint.c

@@ -0,0 +1,140 @@
+#include <stdint.h> 
+#include <rv32i.h>
+
+
+volatile uint32_t *mtime_low = (volatile uint32_t *) MTIME_BASE_ADDRESS;
+volatile uint32_t *mtime_hi = (volatile uint32_t *) (MTIME_BASE_ADDRESS + 4);
+volatile uint32_t *mtimecmp_low = (volatile uint32_t *) MTIMECMP_BASE_ADDRESS;
+volatile uint32_t *mtimecmp_hi = (volatile uint32_t *) (MTIMECMP_BASE_ADDRESS + 4);
+volatile uint32_t *software_interrupt = (volatile uint32_t *) MSIP_BASE_ADDRESS;
+
+// Set current system time.
+void mtime_set_time(uint64_t time) {
+
+  union {
+    uint64_t uint64;
+    uint32_t uint32[sizeof(uint64_t)/sizeof(uint32_t)];
+  } time_union;
+
+  time_union.uint64 = time;
+  //set it up this way to not trigger false timer interrupt
+  *mtime_low = 0;
+  *mtime_hi = time_union.uint32[1];
+  *mtime_low = time_union.uint32[0];
+
+}
+
+
+// Get current system time.
+uint64_t mtime_get_time(void) {
+
+  union {
+    uint64_t uint64;
+    uint32_t uint32[sizeof(uint64_t)/sizeof(uint32_t)];
+  } time_union;
+
+
+  time_union.uint32[0] = *mtime_low;
+  time_union.uint32[1] = *mtime_hi;
+
+  return time_union.uint64;
+}
+
+
+// Set compare time register (MTIMECMP) for generating interrupts.
+void mtime_set_timecmp(uint64_t timecmp) {
+
+  union {
+    uint64_t uint64;
+    uint32_t uint32[sizeof(uint64_t)/sizeof(uint32_t)];
+  } timecmp_union;
+
+  timecmp_union.uint64 = timecmp;
+
+  *mtimecmp_low = -1; // prevent MTIMECMP from temporarily becoming smaller than the lesser of the old and new values
+  *mtimecmp_hi = timecmp_union.uint32[1];
+  *mtimecmp_low = timecmp_union.uint32[0];
+}
+
+
+// Get compare time register (MTIMECMP).
+uint64_t mtime_get_timecmp(void) {
+
+  union {
+    uint64_t uint64;
+    uint32_t uint32[sizeof(uint64_t)/sizeof(uint32_t)];
+  } timecmp_union;
+
+  timecmp_union.uint32[0] = *mtimecmp_low;
+  timecmp_union.uint32[1] = *mtimecmp_hi;
+
+  return timecmp_union.uint64;
+}
+
+//setup trap handler by setting MTVEC and initially disabling all interrupts
+//NOTE: trap handler function MUST HAVE ATTRIBUTE INTERRUPT
+void trap_handler_setup(void (*trap_handler)(void)) { //this is a pointer to a function with void arguments and returns void
+    csr_write(MTVEC,(uint32_t) trap_handler); //store the address of the function to MTVEC (the input is a pointer which is simply an address)
+    //disable all interrupts
+    csr_write(MSTATUS, 0);
+    csr_write(MIE, 0);
+    csr_write(MIP, 0);
+}
+
+// trurn on software interrupt
+void enable_software_interrupt(void){
+	*software_interrupt = 1;
+}
+
+// turn off software interrupt
+void disable_software_interrupt(void){
+	*software_interrupt = 0;
+}
+
+
+// convert milliseconds input to cpu clock ticks
+uint64_t ms_to_cpu_ticks (uint64_t ms){
+    uint64_t cpu_clk_ticks = ms*(CPU_CLK_HZ/1000);
+    return cpu_clk_ticks;
+}
+
+// convert milliseconds input to cpu clock ticks
+uint64_t us_to_cpu_ticks (uint64_t us){
+    uint64_t cpu_clk_ticks = us*(CPU_CLK_HZ/1000000);
+    return cpu_clk_ticks;
+}
+
+// convert cpu clock ticks to us
+uint32_t cpu_ticks_to_us (uint64_t ticks){
+    uint32_t us = (ticks*1000000)/CPU_CLK_HZ;
+    return us;
+}
+
+
+// delay function based on milliseconds
+void delay_ms(uint64_t ms) {
+	uint64_t initial_time = mtime_get_time();
+	uint64_t ms_in_ticks = ms_to_cpu_ticks(ms);
+	while ((initial_time + ms_in_ticks) > (uint64_t)mtime_get_time()){ //do nothing while delay has not yet passed
+	}
+}
+
+// delay function based on microseconds
+void delay_us(uint64_t us) {
+	uint64_t initial_time = mtime_get_time();
+	uint64_t us_in_ticks = us_to_cpu_ticks(us);
+	while ((initial_time + us_in_ticks) > (uint64_t)mtime_get_time()){ //do nothing while delay has not yet passed
+	}
+}
+
+// delay function based on cpu clock tick
+void delay_ticks(uint32_t ticks) {
+	uint64_t initial_time = mtime_get_time();
+	while ((initial_time + ticks) > (uint64_t)mtime_get_time()){ //do nothing while delay has not yet passed
+	}
+}
+
+
+
+
+

AngeloJacobo_RISC-V/test/lib/gpio.c

@@ -0,0 +1,91 @@
+#include <stdint.h>
+#include <rv32i.h>
+
+volatile uint32_t *gpio_mode_reg = (volatile uint32_t *) GPIO_MODE;
+volatile uint32_t *gpio_write_reg = (volatile uint32_t *) GPIO_WRITE;
+volatile uint32_t *gpio_read_reg = (volatile uint32_t *) GPIO_READ;
+
+//read mode setting of the GPIOs (read = 0, write = 1)
+uint32_t gpio_read_mode(){
+    return *gpio_mode_reg;
+}
+
+//set mode setting og the GPIOs (read = 0, write = 1)
+void gpio_set_mode(uint32_t mode){
+    *gpio_mode_reg = mode;
+}
+
+//write to GPIOs
+void gpio_write(uint32_t write){
+    *gpio_write_reg = write;
+}
+
+//read current write value of GPIOs
+uint32_t gpio_write_value(){
+    return *gpio_write_reg;
+}
+
+//read GPIO
+uint32_t gpio_read(){
+    return *gpio_read_reg;
+}
+
+//toggle a specific GPIO pin
+void toggle_gpio(uint32_t pin_number){
+    gpio_set_mode_pin(pin_number, 1); //set pin to write mode
+    uint32_t value;
+    value = gpio_write_value(); //read current write value 
+    gpio_write(value ^ (1<<pin_number)); //reverse the value of the pin
+}
+
+//write to a specific GPIO pin
+void gpio_write_pin(uint32_t pin_number, uint32_t val){
+    gpio_set_mode_pin(pin_number, 1); //set pin to write mode
+    uint32_t value;
+    value = gpio_write_value(); //read current write value 
+    if(val) gpio_write(value | (1<<pin_number)); //set the pin high
+    else gpio_write(value & (~(1<<pin_number))); //set the pin low
+}
+
+//read a specific GPIO pin
+uint32_t gpio_read_pin(uint32_t pin_number){
+    gpio_set_mode_pin(pin_number, 0); //set pin to read mode
+    uint32_t value;
+    value = gpio_read();
+    if(value & (1<<pin_number)){
+        return 1;
+    }
+    else{
+        return 0;
+    }
+}
+
+
+//set mode setting of a single GPIO pin(read = 0, write = 1)
+void gpio_set_mode_pin(uint32_t pin_number, uint32_t mode){
+    uint32_t all_modes = gpio_read_mode();
+    if(mode){ //write
+        gpio_set_mode(all_modes | (1<<pin_number));
+    }
+    else{ //read
+        gpio_set_mode(all_modes & (~(1<<pin_number)));
+    }
+}
+
+//measure pulse duration of a GPIO pin in us
+uint32_t gpio_pulse_duration_us(uint32_t pin_number, uint32_t val){
+    uint64_t time;
+
+    while(gpio_read_pin(pin_number) != val); //wait until pin value becomes val
+    time = mtime_get_time(); //record time
+    while(gpio_read_pin(pin_number) == val);// wait until pin value changes
+    time = (uint32_t) (mtime_get_time() - time); 
+    return cpu_ticks_to_us(time); // convert cpu clock ticks to us
+}
+
+
+
+
+
+
+

AngeloJacobo_RISC-V/test/lib/hygro_pmod.c

@@ -0,0 +1,238 @@
+/************************************************************************/
+/*																		*/
+/*	HYGROI2C.cpp		--		Definition for HYGROI2C library 	    */
+/*																		*/
+/************************************************************************/
+/*	Author:		Arthur Brown											*/
+/*	Copyright 2017, Digilent Inc.										*/
+/************************************************************************/
+/*  File Description:													*/
+/*		This file defines functions for HYGROI2C						*/
+/*																		*/
+/************************************************************************/
+/*  Revision History:													*/
+/*																		*/
+/*	01/30/2017(ArtVVB): created											*/
+/*																		*/
+/************************************************************************/
+
+
+/* ------------------------------------------------------------ */
+/*				Include File Definitions						*/
+/* ------------------------------------------------------------ */
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <rv32i.h>
+/* ------------------------------------------------------------ */
+/*				Procedure Definitions							*/
+/* ------------------------------------------------------------ */
+
+
+
+/* ------------------------------------------------------------ */
+/*        HYGROI2C::writeRegI2C
+**
+**        Synopsis:
+**				writeRegI2C(bConfig);
+**
+**        Parameters:
+**				uint8_t bReg - the register address to be written to
+**				uint16_t bVal - the bytes to be written
+**
+**        Return Values:
+**                void 
+**
+**        Errors:
+**			none
+**
+**        Description:
+**			This function writes to a register over I2C. 
+**
+*/
+uint8_t hygroi2c_writeRegI2C(uint8_t bReg, uint16_t bVal)
+{   
+    uint8_t ack;
+    ack = i2c_write_address(HYGROI2C_I2C_ADDR<<1); // start i2c by writing slave address (returns slave ack)
+    i2c_write_byte(bReg); // write to slave (returns slave ack) (after i2c_write_address())
+	i2c_write_byte((bVal>>8)&0xff); // send upper byte
+	i2c_write_byte((bVal)&0xff);    // send lower byte
+	i2c_stop(); // stop current i2c transaction
+	return ack;
+}
+
+/* ------------------------------------------------------------ */
+/*        HYGROI2C::readRegI2C
+**
+**        Synopsis:
+**				readRegI2C(bReg, rVal, delay_ms);
+**
+**        Parameters:
+**				uint8_t bReg - the register address to be written to
+**				uint16_t* rVal - the return location for the read bytes
+**				unsigned int delay_ms - the number of milliseconds required for the HYGRO to convert the desired data
+**
+**        Return Values:
+**                bool success - whether valid data has been successfully captured
+**
+**        Errors:
+**			failure on bad rVal pointer
+**
+**        Description:
+**			This function reads a register over I2C. 
+**
+*/
+ uint8_t hygroi2c_readRegI2C(uint8_t bReg, uint16_t *rVal, uint32_t delay_in_ms)
+ {
+	int n, i;
+	uint8_t ack;
+    char msg[20]; 
+	i2c_write_address(HYGROI2C_I2C_ADDR<<1); // start i2c by writing slave address (returns slave ack)
+    i2c_write_byte(bReg); // write to slave (returns slave ack) (after i2c_write_address())
+	if (delay_in_ms > 0)
+		delay_ms(delay_in_ms); // wait for conversion to complete
+	i2c_stop(); // stop current i2c transaction	
+	
+
+	ack = i2c_write_address(((HYGROI2C_I2C_ADDR<<1) | 0x01)); // start i2c by writing slave address (returns slave ack)
+    //read two bytes from slave
+	*rVal |= (uint16_t)i2c_read_byte(); //read a byte from the slave (after i2c_write_address())
+	*rVal <<= 8;
+	*rVal |= (uint16_t)i2c_read_byte(); //read a byte from the slave (after i2c_write_address()) 
+    i2c_stop(); // stop current i2c transaction
+
+    return ack;
+}
+
+
+/* ------------------------------------------------------------ */
+/*        HYGROI2C::begin
+**
+**        Synopsis:
+**				myHYGROI2C.begin();
+**
+**        Parameters:
+**
+**        Return Values:
+**                void 
+**
+**        Errors:
+**
+**        Description:
+**				This function initializes the I2C interface #1 that is used to communicate with PmodAD2.
+**
+*/
+void hygroi2c_begin()
+{
+    uint8_t ack;
+	delay_ms(15);
+	ack = hygroi2c_writeRegI2C(HYGROI2C_CONFIG_REG, 0x00); // use non-sequential acquisition mode, all other config bits are default
+	if(!ack){
+        //uart_print("hygroi2c_begin() FAILED\n");
+    }
+
+	
+}
+
+/* ------------------------------------------------------------ */
+/*        HYGROI2C::getTemperature
+**
+**        Synopsis:
+**				myHYGROI2C.getTemperature();
+**
+**        Parameters:
+**
+**        Return Values:
+**                float deg_c - the temperature reading in degrees celsius
+**
+**        Errors: - modify to manage read failures
+**
+**        Description:
+**				This function captures a temperature reading from the Pmod HYGRO.
+**
+*/
+float hygroi2c_getTemperature()
+{
+    uint8_t ack;
+	uint16_t raw_t;
+	float deg_c;
+	ack = hygroi2c_readRegI2C(HYGROI2C_TMP_REG, &raw_t, 7); // conversion time for temperature at 14 bit resolution is 6.5 ms
+	deg_c = (float)raw_t / 0x10000;
+	deg_c *= 165.0;
+	deg_c -= 40.0; // conversion provided in reference manual
+	return deg_c;
+}
+
+/* ------------------------------------------------------------ */
+/*        HYGROI2C::getHumidity
+**
+**        Synopsis:
+**				HYGROI2C.getHumidity();
+**
+**        Parameters:
+**
+**        Return Values:
+**                float per_rh - the humidity reading in percent relative humidity.
+**
+**        Errors: - modify to manage read failures
+**
+**        Description:
+**				This function captures a humidity reading from the Pmod HYGRO.
+**
+*/
+float hygroi2c_getHumidity() {
+	uint16_t raw_h;
+	float per_rh;
+	uint8_t ack;
+	ack = hygroi2c_readRegI2C(HYGROI2C_HUM_REG, &raw_h, 7); // conversion time for humidity at 14 bit resolution is 6.35 ms
+	per_rh = (float)raw_h / 0x10000;
+	per_rh *= 100.0; // conversion provided in reference manual
+	return per_rh;
+}
+
+/* ------------------------------------------------------------ */
+/*        HYGROI2C::tempF2C
+**
+**        Synopsis:
+**				HYGROI2C.tempF2C(deg_f);
+**
+**        Parameters:
+**				float deg_f - the temperature in degrees fahrenheit
+**        Return Values:
+**              float deg_c - the temperature in degrees celsius
+**
+**        Errors:
+**
+**        Description:
+**				This function converts a fahrenheit temperature to celsius
+**
+*/
+float hygroi2c_tempF2C(float deg_f)
+{
+	return (deg_f - 32) / 1.8;
+}
+
+/* ------------------------------------------------------------ */
+/*        HYGROI2C::tempC2F
+**
+**        Synopsis:
+**				HYGROI2C.tempC2F(deg_c);
+**
+**        Parameters:
+**              float deg_c - the temperature in degrees celsius
+**        Return Values:
+**				float deg_f - the temperature in degrees fahrenheit
+**
+**        Errors:
+**
+**        Description:
+**				This function converts a celsius temperature to fahrenheit
+**
+*/
+float hygroi2c_tempC2F(float deg_c)
+{
+	return deg_c * 1.8 + 32;
+}
+
+
+

AngeloJacobo_RISC-V/test/lib/i2c.c

@@ -0,0 +1,49 @@
+// [REPEATED START NOT SUPPORTED]
+#include <stdint.h> 
+#include <rv32i.h>
+
+volatile uint32_t *i2c_start = (volatile uint32_t *) I2C_START;
+volatile uint32_t *i2c_write = (volatile uint32_t *) I2C_WRITE;
+volatile uint32_t *i2c_busy = (volatile uint32_t *) I2C_BUSY;
+volatile uint32_t *i2c_halt = (volatile uint32_t *) I2C_STOP;
+volatile uint32_t *i2c_ack = (volatile uint32_t *) I2C_ACK;
+volatile uint32_t *i2c_read_ready = (volatile uint32_t *) I2C_READ_DATA_READY;
+volatile uint32_t *i2c_read = (volatile uint32_t *) I2C_READ;
+
+
+// start i2c by writing slave address (returns slave ack)
+uint8_t i2c_write_address(uint8_t addr){
+    uint8_t ack;
+    while(*i2c_busy); //stay here if busy
+    *i2c_start = addr; //write to i2c address of slave
+    while(*i2c_busy); //wait until write is finished
+    ack = *i2c_ack; //check if slave acknowledged
+    return ack;
+}
+
+// stop current i2c transaction
+void i2c_stop(void){
+    while(*i2c_busy);
+    *i2c_halt = 0x01;
+    while(*i2c_busy);
+    *i2c_halt = 0x00; //set it back to zero in preparation for next transaction
+    delay_ticks(100);
+}
+
+uint8_t i2c_write_byte(uint8_t data){
+    uint8_t ack;
+    while(*i2c_busy); //stay here if busy
+    *i2c_write = data; //write data byte to slave
+    while(*i2c_busy); //wait until write is finished
+    ack = *i2c_ack; //check if slave acknowledged
+    return ack;
+}
+
+uint8_t i2c_read_byte(){ //read a byte from the slave (after i2c_write_address())
+    uint8_t read_data;
+    while(*i2c_busy);
+    while(*i2c_read_ready == 0){ //while read data is not yet available
+    }
+    read_data = *i2c_read; //retrieve data
+};
+

AngeloJacobo_RISC-V/test/lib/lcd.c

@@ -0,0 +1,115 @@
+#include <stdint.h> 
+#include <rv32i.h>
+// Source: https://deepbluembedded.com/interfacing-i2c-lcd-16x2-tutorial-with-pic-microcontrollers-mplab-xc8/
+
+unsigned char RS, i2c_add, BackLight_State = LCD_BACKLIGHT;
+ 
+void LCD_Init() //initialize LCD with proper routine
+{
+  i2c_add = LCD_I2C_ADDR;
+  IO_Expander_Write(0x00);
+   delay_ms(30); 
+  LCD_CMD(0x03);
+   delay_ms(5);
+  LCD_CMD(0x03);
+   delay_ms(5);
+  LCD_CMD(0x03);
+   delay_ms(5);
+  LCD_CMD(LCD_RETURN_HOME);
+   delay_ms(5); 
+  LCD_CMD(0x20 | (LCD_TYPE << 2));
+   delay_ms(50);
+  LCD_CMD(LCD_TURN_ON);
+   delay_ms(50);
+  LCD_CMD(LCD_CLEAR);
+   delay_ms(50);
+  LCD_CMD(LCD_ENTRY_MODE_SET | LCD_RETURN_HOME);
+   delay_ms(50);
+}
+ 
+void IO_Expander_Write(unsigned char Data) 
+{
+  uint8_t addr_ack, data_ack;
+  addr_ack = i2c_write_address(i2c_add<<1);
+  data_ack = i2c_write_byte(Data | BackLight_State);
+  i2c_stop();
+}
+ 
+void LCD_Write_4Bit(unsigned char Nibble)
+{
+  // Get The RS Value To LSB OF Data
+  Nibble |= RS;
+  IO_Expander_Write(Nibble | 0x04);
+  IO_Expander_Write(Nibble & 0xFB);
+   delay_ms(50);
+}
+ 
+void LCD_CMD(unsigned char CMD)
+{
+  RS = 0; // Command Register Select
+  LCD_Write_4Bit(CMD & 0xF0);
+  LCD_Write_4Bit((CMD << 4) & 0xF0);
+}
+ 
+void LCD_Write_Char(char Data)
+{
+  RS = 1; // Data Register Select
+  LCD_Write_4Bit(Data & 0xF0);
+  LCD_Write_4Bit((Data << 4) & 0xF0);
+}
+ 
+void LCD_Write_String(char* Str) //write string to LCD
+{
+  for(int i=0; Str[i]!='\0'; i++)
+    LCD_Write_Char(Str[i]);
+}
+ 
+void LCD_Set_Cursor(unsigned char ROW, unsigned char COL) //Set cursor where to start writing to LCD
+{
+  switch(ROW)
+  {
+    case 2:
+      LCD_CMD(0xC0 + COL-1);
+      break;
+    case 3:
+      LCD_CMD(0x94 + COL-1);
+      break;
+    case 4:
+      LCD_CMD(0xD4 + COL-1);
+      break;
+    // Case 1
+    default:
+      LCD_CMD(0x80 + COL-1);
+  }
+}
+ 
+void Backlight(void) //turn on backlight (initially turned on)
+{
+  BackLight_State = LCD_BACKLIGHT;
+  IO_Expander_Write(0);
+}
+ 
+void noBacklight(void) //turn off backlight
+{
+  BackLight_State = LCD_NOBACKLIGHT;
+  IO_Expander_Write(0);
+}
+ 
+void LCD_SL(void)
+{
+  LCD_CMD(0x18);
+   delay_ms(40); 
+}
+ 
+void LCD_SR(void)
+{
+  LCD_CMD(0x1C);
+   delay_ms(40); 
+}
+ 
+void LCD_Clear(void)
+{
+  LCD_CMD(0x01);
+   delay_ms(40); 
+}
+

AngeloJacobo_RISC-V/test/lib/printf.c

@@ -0,0 +1,914 @@
+///////////////////////////////////////////////////////////////////////////////
+// \author (c) Marco Paland (info@paland.com)
+//             2014-2019, PALANDesign Hannover, Germany
+//
+// \license The MIT License (MIT)
+//
+// Permission is hereby granted, free of charge, to any person obtaining a copy
+// of this software and associated documentation files (the "Software"), to deal
+// in the Software without restriction, including without limitation the rights
+// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+// copies of the Software, and to permit persons to whom the Software is
+// furnished to do so, subject to the following conditions:
+//
+// The above copyright notice and this permission notice shall be included in
+// all copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+// THE SOFTWARE.
+//
+// \brief Tiny printf, sprintf and (v)snprintf implementation, optimized for speed on
+//        embedded systems with a very limited resources. These routines are thread
+//        safe and reentrant!
+//        Use this instead of the bloated standard/newlib printf cause these use
+//        malloc for printf (and may not be thread safe).
+//
+///////////////////////////////////////////////////////////////////////////////
+
+#include <stdbool.h>
+#include <stdint.h>
+
+#include "rv32i.h"
+
+
+// define this globally (e.g. gcc -DPRINTF_INCLUDE_CONFIG_H ...) to include the
+// printf_config.h header file
+// default: undefined
+#ifdef PRINTF_INCLUDE_CONFIG_H
+#include "printf_config.h"
+#endif
+
+
+// 'ntoa' conversion buffer size, this must be big enough to hold one converted
+// numeric number including padded zeros (dynamically created on stack)
+// default: 32 byte
+#ifndef PRINTF_NTOA_BUFFER_SIZE
+#define PRINTF_NTOA_BUFFER_SIZE    32U
+#endif
+
+// 'ftoa' conversion buffer size, this must be big enough to hold one converted
+// float number including padded zeros (dynamically created on stack)
+// default: 32 byte
+#ifndef PRINTF_FTOA_BUFFER_SIZE
+#define PRINTF_FTOA_BUFFER_SIZE    32U
+#endif
+
+// support for the floating point type (%f)
+// default: activated
+#ifndef PRINTF_DISABLE_SUPPORT_FLOAT
+#define PRINTF_SUPPORT_FLOAT
+#endif
+
+// support for exponential floating point notation (%e/%g)
+// default: activated
+#ifndef PRINTF_DISABLE_SUPPORT_EXPONENTIAL
+#define PRINTF_SUPPORT_EXPONENTIAL
+#endif
+
+// define the default floating point precision
+// default: 6 digits
+#ifndef PRINTF_DEFAULT_FLOAT_PRECISION
+#define PRINTF_DEFAULT_FLOAT_PRECISION  6U
+#endif
+
+// define the largest float suitable to print with %f
+// default: 1e9
+#ifndef PRINTF_MAX_FLOAT
+#define PRINTF_MAX_FLOAT  1e9
+#endif
+
+// support for the long long types (%llu or %p)
+// default: activated
+#ifndef PRINTF_DISABLE_SUPPORT_LONG_LONG
+#define PRINTF_SUPPORT_LONG_LONG
+#endif
+
+// support for the ptrdiff_t type (%t)
+// ptrdiff_t is normally defined in <stddef.h> as long or long long type
+// default: activated
+#ifndef PRINTF_DISABLE_SUPPORT_PTRDIFF_T
+#define PRINTF_SUPPORT_PTRDIFF_T
+#endif
+
+///////////////////////////////////////////////////////////////////////////////
+
+// internal flag definitions
+#define FLAGS_ZEROPAD   (1U <<  0U)
+#define FLAGS_LEFT      (1U <<  1U)
+#define FLAGS_PLUS      (1U <<  2U)
+#define FLAGS_SPACE     (1U <<  3U)
+#define FLAGS_HASH      (1U <<  4U)
+#define FLAGS_UPPERCASE (1U <<  5U)
+#define FLAGS_CHAR      (1U <<  6U)
+#define FLAGS_SHORT     (1U <<  7U)
+#define FLAGS_LONG      (1U <<  8U)
+#define FLAGS_LONG_LONG (1U <<  9U)
+#define FLAGS_PRECISION (1U << 10U)
+#define FLAGS_ADAPT_EXP (1U << 11U)
+
+
+// import float.h for DBL_MAX
+#if defined(PRINTF_SUPPORT_FLOAT)
+#include <float.h>
+#endif
+
+
+// output function type
+typedef void (*out_fct_type)(char character, void* buffer, size_t idx, size_t maxlen);
+
+
+// wrapper (used as buffer) for output function type
+typedef struct {
+  void  (*fct)(char character, void* arg);
+  void* arg;
+} out_fct_wrap_type;
+
+
+// internal buffer output
+static inline void _out_buffer(char character, void* buffer, size_t idx, size_t maxlen)
+{
+  if (idx < maxlen) {
+    ((char*)buffer)[idx] = character;
+  }
+}
+
+
+// internal null output
+static inline void _out_null(char character, void* buffer, size_t idx, size_t maxlen)
+{
+  (void)character; (void)buffer; (void)idx; (void)maxlen;
+}
+
+
+// internal _putchar wrapper
+static inline void _out_char(char character, void* buffer, size_t idx, size_t maxlen)
+{
+  (void)buffer; (void)idx; (void)maxlen;
+  if (character) {
+    _putchar(character);
+  }
+}
+
+
+// internal output function wrapper
+static inline void _out_fct(char character, void* buffer, size_t idx, size_t maxlen)
+{
+  (void)idx; (void)maxlen;
+  if (character) {
+    // buffer is the output fct pointer
+    ((out_fct_wrap_type*)buffer)->fct(character, ((out_fct_wrap_type*)buffer)->arg);
+  }
+}
+
+
+// internal secure strlen
+// \return The length of the string (excluding the terminating 0) limited by 'maxsize'
+static inline unsigned int _strnlen_s(const char* str, size_t maxsize)
+{
+  const char* s;
+  for (s = str; *s && maxsize--; ++s);
+  return (unsigned int)(s - str);
+}
+
+
+// internal test if char is a digit (0-9)
+// \return true if char is a digit
+static inline bool _is_digit(char ch)
+{
+  return (ch >= '0') && (ch <= '9');
+}
+
+
+// internal ASCII string to unsigned int conversion
+static unsigned int _atoi(const char** str)
+{
+  unsigned int i = 0U;
+  while (_is_digit(**str)) {
+    i = i * 10U + (unsigned int)(*((*str)++) - '0');
+  }
+  return i;
+}
+
+
+// output the specified string in reverse, taking care of any zero-padding
+static size_t _out_rev(out_fct_type out, char* buffer, size_t idx, size_t maxlen, const char* buf, size_t len, unsigned int width, unsigned int flags)
+{
+  const size_t start_idx = idx;
+
+  // pad spaces up to given width
+  if (!(flags & FLAGS_LEFT) && !(flags & FLAGS_ZEROPAD)) {
+    for (size_t i = len; i < width; i++) {
+      out(' ', buffer, idx++, maxlen);
+    }
+  }
+
+  // reverse string
+  while (len) {
+    out(buf[--len], buffer, idx++, maxlen);
+  }
+
+  // append pad spaces up to given width
+  if (flags & FLAGS_LEFT) {
+    while (idx - start_idx < width) {
+      out(' ', buffer, idx++, maxlen);
+    }
+  }
+
+  return idx;
+}
+
+
+// internal itoa format
+static size_t _ntoa_format(out_fct_type out, char* buffer, size_t idx, size_t maxlen, char* buf, size_t len, bool negative, unsigned int base, unsigned int prec, unsigned int width, unsigned int flags)
+{
+  // pad leading zeros
+  if (!(flags & FLAGS_LEFT)) {
+    if (width && (flags & FLAGS_ZEROPAD) && (negative || (flags & (FLAGS_PLUS | FLAGS_SPACE)))) {
+      width--;
+    }
+    while ((len < prec) && (len < PRINTF_NTOA_BUFFER_SIZE)) {
+      buf[len++] = '0';
+    }
+    while ((flags & FLAGS_ZEROPAD) && (len < width) && (len < PRINTF_NTOA_BUFFER_SIZE)) {
+      buf[len++] = '0';
+    }
+  }
+
+  // handle hash
+  if (flags & FLAGS_HASH) {
+    if (!(flags & FLAGS_PRECISION) && len && ((len == prec) || (len == width))) {
+      len--;
+      if (len && (base == 16U)) {
+        len--;
+      }
+    }
+    if ((base == 16U) && !(flags & FLAGS_UPPERCASE) && (len < PRINTF_NTOA_BUFFER_SIZE)) {
+      buf[len++] = 'x';
+    }
+    else if ((base == 16U) && (flags & FLAGS_UPPERCASE) && (len < PRINTF_NTOA_BUFFER_SIZE)) {
+      buf[len++] = 'X';
+    }
+    else if ((base == 2U) && (len < PRINTF_NTOA_BUFFER_SIZE)) {
+      buf[len++] = 'b';
+    }
+    if (len < PRINTF_NTOA_BUFFER_SIZE) {
+      buf[len++] = '0';
+    }
+  }
+
+  if (len < PRINTF_NTOA_BUFFER_SIZE) {
+    if (negative) {
+      buf[len++] = '-';
+    }
+    else if (flags & FLAGS_PLUS) {
+      buf[len++] = '+';  // ignore the space if the '+' exists
+    }
+    else if (flags & FLAGS_SPACE) {
+      buf[len++] = ' ';
+    }
+  }
+
+  return _out_rev(out, buffer, idx, maxlen, buf, len, width, flags);
+}
+
+
+// internal itoa for 'long' type
+static size_t _ntoa_long(out_fct_type out, char* buffer, size_t idx, size_t maxlen, unsigned long value, bool negative, unsigned long base, unsigned int prec, unsigned int width, unsigned int flags)
+{
+  char buf[PRINTF_NTOA_BUFFER_SIZE];
+  size_t len = 0U;
+
+  // no hash for 0 values
+  if (!value) {
+    flags &= ~FLAGS_HASH;
+  }
+
+  // write if precision != 0 and value is != 0
+  if (!(flags & FLAGS_PRECISION) || value) {
+    do {
+      const char digit = (char)(value % base);
+      buf[len++] = digit < 10 ? '0' + digit : (flags & FLAGS_UPPERCASE ? 'A' : 'a') + digit - 10;
+      value /= base;
+    } while (value && (len < PRINTF_NTOA_BUFFER_SIZE));
+  }
+
+  return _ntoa_format(out, buffer, idx, maxlen, buf, len, negative, (unsigned int)base, prec, width, flags);
+}
+
+
+// internal itoa for 'long long' type
+#if defined(PRINTF_SUPPORT_LONG_LONG)
+static size_t _ntoa_long_long(out_fct_type out, char* buffer, size_t idx, size_t maxlen, unsigned long long value, bool negative, unsigned long long base, unsigned int prec, unsigned int width, unsigned int flags)
+{
+  char buf[PRINTF_NTOA_BUFFER_SIZE];
+  size_t len = 0U;
+
+  // no hash for 0 values
+  if (!value) {
+    flags &= ~FLAGS_HASH;
+  }
+
+  // write if precision != 0 and value is != 0
+  if (!(flags & FLAGS_PRECISION) || value) {
+    do {
+      const char digit = (char)(value % base);
+      buf[len++] = digit < 10 ? '0' + digit : (flags & FLAGS_UPPERCASE ? 'A' : 'a') + digit - 10;
+      value /= base;
+    } while (value && (len < PRINTF_NTOA_BUFFER_SIZE));
+  }
+
+  return _ntoa_format(out, buffer, idx, maxlen, buf, len, negative, (unsigned int)base, prec, width, flags);
+}
+#endif  // PRINTF_SUPPORT_LONG_LONG
+
+
+#if defined(PRINTF_SUPPORT_FLOAT)
+
+#if defined(PRINTF_SUPPORT_EXPONENTIAL)
+// forward declaration so that _ftoa can switch to exp notation for values > PRINTF_MAX_FLOAT
+static size_t _etoa(out_fct_type out, char* buffer, size_t idx, size_t maxlen, double value, unsigned int prec, unsigned int width, unsigned int flags);
+#endif
+
+
+// internal ftoa for fixed decimal floating point
+static size_t _ftoa(out_fct_type out, char* buffer, size_t idx, size_t maxlen, double value, unsigned int prec, unsigned int width, unsigned int flags)
+{
+  char buf[PRINTF_FTOA_BUFFER_SIZE];
+  size_t len  = 0U;
+  double diff = 0.0;
+
+  // powers of 10
+  static const double pow10[] = { 1, 10, 100, 1000, 10000, 100000, 1000000, 10000000, 100000000, 1000000000 };
+
+  // test for special values
+  if (value != value)
+    return _out_rev(out, buffer, idx, maxlen, "nan", 3, width, flags);
+  if (value < -DBL_MAX)
+    return _out_rev(out, buffer, idx, maxlen, "fni-", 4, width, flags);
+  if (value > DBL_MAX)
+    return _out_rev(out, buffer, idx, maxlen, (flags & FLAGS_PLUS) ? "fni+" : "fni", (flags & FLAGS_PLUS) ? 4U : 3U, width, flags);
+
+  // test for very large values
+  // standard printf behavior is to print EVERY whole number digit -- which could be 100s of characters overflowing your buffers == bad
+  if ((value > PRINTF_MAX_FLOAT) || (value < -PRINTF_MAX_FLOAT)) {
+#if defined(PRINTF_SUPPORT_EXPONENTIAL)
+    return _etoa(out, buffer, idx, maxlen, value, prec, width, flags);
+#else
+    return 0U;
+#endif
+  }
+
+  // test for negative
+  bool negative = false;
+  if (value < 0) {
+    negative = true;
+    value = 0 - value;
+  }
+
+  // set default precision, if not set explicitly
+  if (!(flags & FLAGS_PRECISION)) {
+    prec = PRINTF_DEFAULT_FLOAT_PRECISION;
+  }
+  // limit precision to 9, cause a prec >= 10 can lead to overflow errors
+  while ((len < PRINTF_FTOA_BUFFER_SIZE) && (prec > 9U)) {
+    buf[len++] = '0';
+    prec--;
+  }
+
+  int whole = (int)value;
+  double tmp = (value - whole) * pow10[prec];
+  unsigned long frac = (unsigned long)tmp;
+  diff = tmp - frac;
+
+  if (diff > 0.5) {
+    ++frac;
+    // handle rollover, e.g. case 0.99 with prec 1 is 1.0
+    if (frac >= pow10[prec]) {
+      frac = 0;
+      ++whole;
+    }
+  }
+  else if (diff < 0.5) {
+  }
+  else if ((frac == 0U) || (frac & 1U)) {
+    // if halfway, round up if odd OR if last digit is 0
+    ++frac;
+  }
+
+  if (prec == 0U) {
+    diff = value - (double)whole;
+    if ((!(diff < 0.5) || (diff > 0.5)) && (whole & 1)) {
+      // exactly 0.5 and ODD, then round up
+      // 1.5 -> 2, but 2.5 -> 2
+      ++whole;
+    }
+  }
+  else {
+    unsigned int count = prec;
+    // now do fractional part, as an unsigned number
+    while (len < PRINTF_FTOA_BUFFER_SIZE) {
+      --count;
+      buf[len++] = (char)(48U + (frac % 10U));
+      if (!(frac /= 10U)) {
+        break;
+      }
+    }
+    // add extra 0s
+    while ((len < PRINTF_FTOA_BUFFER_SIZE) && (count-- > 0U)) {
+      buf[len++] = '0';
+    }
+    if (len < PRINTF_FTOA_BUFFER_SIZE) {
+      // add decimal
+      buf[len++] = '.';
+    }
+  }
+
+  // do whole part, number is reversed
+  while (len < PRINTF_FTOA_BUFFER_SIZE) {
+    buf[len++] = (char)(48 + (whole % 10));
+    if (!(whole /= 10)) {
+      break;
+    }
+  }
+
+  // pad leading zeros
+  if (!(flags & FLAGS_LEFT) && (flags & FLAGS_ZEROPAD)) {
+    if (width && (negative || (flags & (FLAGS_PLUS | FLAGS_SPACE)))) {
+      width--;
+    }
+    while ((len < width) && (len < PRINTF_FTOA_BUFFER_SIZE)) {
+      buf[len++] = '0';
+    }
+  }
+
+  if (len < PRINTF_FTOA_BUFFER_SIZE) {
+    if (negative) {
+      buf[len++] = '-';
+    }
+    else if (flags & FLAGS_PLUS) {
+      buf[len++] = '+';  // ignore the space if the '+' exists
+    }
+    else if (flags & FLAGS_SPACE) {
+      buf[len++] = ' ';
+    }
+  }
+
+  return _out_rev(out, buffer, idx, maxlen, buf, len, width, flags);
+}
+
+
+#if defined(PRINTF_SUPPORT_EXPONENTIAL)
+// internal ftoa variant for exponential floating-point type, contributed by Martijn Jasperse <m.jasperse@gmail.com>
+static size_t _etoa(out_fct_type out, char* buffer, size_t idx, size_t maxlen, double value, unsigned int prec, unsigned int width, unsigned int flags)
+{
+  // check for NaN and special values
+  if ((value != value) || (value > DBL_MAX) || (value < -DBL_MAX)) {
+    return _ftoa(out, buffer, idx, maxlen, value, prec, width, flags);
+  }
+
+  // determine the sign
+  const bool negative = value < 0;
+  if (negative) {
+    value = -value;
+  }
+
+  // default precision
+  if (!(flags & FLAGS_PRECISION)) {
+    prec = PRINTF_DEFAULT_FLOAT_PRECISION;
+  }
+
+  // determine the decimal exponent
+  // based on the algorithm by David Gay (https://www.ampl.com/netlib/fp/dtoa.c)
+  union {
+    uint64_t U;
+    double   F;
+  } conv;
+
+  conv.F = value;
+  int exp2 = (int)((conv.U >> 52U) & 0x07FFU) - 1023;           // effectively log2
+  conv.U = (conv.U & ((1ULL << 52U) - 1U)) | (1023ULL << 52U);  // drop the exponent so conv.F is now in [1,2)
+  // now approximate log10 from the log2 integer part and an expansion of ln around 1.5
+  int expval = (int)(0.1760912590558 + exp2 * 0.301029995663981 + (conv.F - 1.5) * 0.289529654602168);
+  // now we want to compute 10^expval but we want to be sure it won't overflow
+  exp2 = (int)(expval * 3.321928094887362 + 0.5);
+  const double z  = expval * 2.302585092994046 - exp2 * 0.6931471805599453;
+  const double z2 = z * z;
+  conv.U = (uint64_t)(exp2 + 1023) << 52U;
+  // compute exp(z) using continued fractions, see https://en.wikipedia.org/wiki/Exponential_function#Continued_fractions_for_ex
+  conv.F *= 1 + 2 * z / (2 - z + (z2 / (6 + (z2 / (10 + z2 / 14)))));
+  // correct for rounding errors
+  if (value < conv.F) {
+    expval--;
+    conv.F /= 10;
+  }
+
+  // the exponent format is "%+03d" and largest value is "307", so set aside 4-5 characters
+  unsigned int minwidth = ((expval < 100) && (expval > -100)) ? 4U : 5U;
+
+  // in "%g" mode, "prec" is the number of *significant figures* not decimals
+  if (flags & FLAGS_ADAPT_EXP) {
+    // do we want to fall-back to "%f" mode?
+    if ((value >= 1e-4) && (value < 1e6)) {
+      if ((int)prec > expval) {
+        prec = (unsigned)((int)prec - expval - 1);
+      }
+      else {
+        prec = 0;
+      }
+      flags |= FLAGS_PRECISION;   // make sure _ftoa respects precision
+      // no characters in exponent
+      minwidth = 0U;
+      expval   = 0;
+    }
+    else {
+      // we use one sigfig for the whole part
+      if ((prec > 0) && (flags & FLAGS_PRECISION)) {
+        --prec;
+      }
+    }
+  }
+
+  // will everything fit?
+  unsigned int fwidth = width;
+  if (width > minwidth) {
+    // we didn't fall-back so subtract the characters required for the exponent
+    fwidth -= minwidth;
+  } else {
+    // not enough characters, so go back to default sizing
+    fwidth = 0U;
+  }
+  if ((flags & FLAGS_LEFT) && minwidth) {
+    // if we're padding on the right, DON'T pad the floating part
+    fwidth = 0U;
+  }
+
+  // rescale the float value
+  if (expval) {
+    value /= conv.F;
+  }
+
+  // output the floating part
+  const size_t start_idx = idx;
+  idx = _ftoa(out, buffer, idx, maxlen, negative ? -value : value, prec, fwidth, flags & ~FLAGS_ADAPT_EXP);
+
+  // output the exponent part
+  if (minwidth) {
+    // output the exponential symbol
+    out((flags & FLAGS_UPPERCASE) ? 'E' : 'e', buffer, idx++, maxlen);
+    // output the exponent value
+    idx = _ntoa_long(out, buffer, idx, maxlen, (expval < 0) ? -expval : expval, expval < 0, 10, 0, minwidth-1, FLAGS_ZEROPAD | FLAGS_PLUS);
+    // might need to right-pad spaces
+    if (flags & FLAGS_LEFT) {
+      while (idx - start_idx < width) out(' ', buffer, idx++, maxlen);
+    }
+  }
+  return idx;
+}
+#endif  // PRINTF_SUPPORT_EXPONENTIAL
+#endif  // PRINTF_SUPPORT_FLOAT
+
+
+// internal vsnprintf
+static int _vsnprintf(out_fct_type out, char* buffer, const size_t maxlen, const char* format, va_list va)
+{
+  unsigned int flags, width, precision, n;
+  size_t idx = 0U;
+
+  if (!buffer) {
+    // use null output function
+    out = _out_null;
+  }
+
+  while (*format)
+  {
+    // format specifier?  %[flags][width][.precision][length]
+    if (*format != '%') {
+      // no
+      out(*format, buffer, idx++, maxlen);
+      format++;
+      continue;
+    }
+    else {
+      // yes, evaluate it
+      format++;
+    }
+
+    // evaluate flags
+    flags = 0U;
+    do {
+      switch (*format) {
+        case '0': flags |= FLAGS_ZEROPAD; format++; n = 1U; break;
+        case '-': flags |= FLAGS_LEFT;    format++; n = 1U; break;
+        case '+': flags |= FLAGS_PLUS;    format++; n = 1U; break;
+        case ' ': flags |= FLAGS_SPACE;   format++; n = 1U; break;
+        case '#': flags |= FLAGS_HASH;    format++; n = 1U; break;
+        default :                                   n = 0U; break;
+      }
+    } while (n);
+
+    // evaluate width field
+    width = 0U;
+    if (_is_digit(*format)) {
+      width = _atoi(&format);
+    }
+    else if (*format == '*') {
+      const int w = va_arg(va, int);
+      if (w < 0) {
+        flags |= FLAGS_LEFT;    // reverse padding
+        width = (unsigned int)-w;
+      }
+      else {
+        width = (unsigned int)w;
+      }
+      format++;
+    }
+
+    // evaluate precision field
+    precision = 0U;
+    if (*format == '.') {
+      flags |= FLAGS_PRECISION;
+      format++;
+      if (_is_digit(*format)) {
+        precision = _atoi(&format);
+      }
+      else if (*format == '*') {
+        const int prec = (int)va_arg(va, int);
+        precision = prec > 0 ? (unsigned int)prec : 0U;
+        format++;
+      }
+    }
+
+    // evaluate length field
+    switch (*format) {
+      case 'l' :
+        flags |= FLAGS_LONG;
+        format++;
+        if (*format == 'l') {
+          flags |= FLAGS_LONG_LONG;
+          format++;
+        }
+        break;
+      case 'h' :
+        flags |= FLAGS_SHORT;
+        format++;
+        if (*format == 'h') {
+          flags |= FLAGS_CHAR;
+          format++;
+        }
+        break;
+#if defined(PRINTF_SUPPORT_PTRDIFF_T)
+      case 't' :
+        flags |= (sizeof(ptrdiff_t) == sizeof(long) ? FLAGS_LONG : FLAGS_LONG_LONG);
+        format++;
+        break;
+#endif
+      case 'j' :
+        flags |= (sizeof(intmax_t) == sizeof(long) ? FLAGS_LONG : FLAGS_LONG_LONG);
+        format++;
+        break;
+      case 'z' :
+        flags |= (sizeof(size_t) == sizeof(long) ? FLAGS_LONG : FLAGS_LONG_LONG);
+        format++;
+        break;
+      default :
+        break;
+    }
+
+    // evaluate specifier
+    switch (*format) {
+      case 'd' :
+      case 'i' :
+      case 'u' :
+      case 'x' :
+      case 'X' :
+      case 'o' :
+      case 'b' : {
+        // set the base
+        unsigned int base;
+        if (*format == 'x' || *format == 'X') {
+          base = 16U;
+        }
+        else if (*format == 'o') {
+          base =  8U;
+        }
+        else if (*format == 'b') {
+          base =  2U;
+        }
+        else {
+          base = 10U;
+          flags &= ~FLAGS_HASH;   // no hash for dec format
+        }
+        // uppercase
+        if (*format == 'X') {
+          flags |= FLAGS_UPPERCASE;
+        }
+
+        // no plus or space flag for u, x, X, o, b
+        if ((*format != 'i') && (*format != 'd')) {
+          flags &= ~(FLAGS_PLUS | FLAGS_SPACE);
+        }
+
+        // ignore '0' flag when precision is given
+        if (flags & FLAGS_PRECISION) {
+          flags &= ~FLAGS_ZEROPAD;
+        }
+
+        // convert the integer
+        if ((*format == 'i') || (*format == 'd')) {
+          // signed
+          if (flags & FLAGS_LONG_LONG) {
+#if defined(PRINTF_SUPPORT_LONG_LONG)
+            const long long value = va_arg(va, long long);
+            idx = _ntoa_long_long(out, buffer, idx, maxlen, (unsigned long long)(value > 0 ? value : 0 - value), value < 0, base, precision, width, flags);
+#endif
+          }
+          else if (flags & FLAGS_LONG) {
+            const long value = va_arg(va, long);
+            idx = _ntoa_long(out, buffer, idx, maxlen, (unsigned long)(value > 0 ? value : 0 - value), value < 0, base, precision, width, flags);
+          }
+          else {
+            const int value = (flags & FLAGS_CHAR) ? (char)va_arg(va, int) : (flags & FLAGS_SHORT) ? (short int)va_arg(va, int) : va_arg(va, int);
+            idx = _ntoa_long(out, buffer, idx, maxlen, (unsigned int)(value > 0 ? value : 0 - value), value < 0, base, precision, width, flags);
+          }
+        }
+        else {
+          // unsigned
+          if (flags & FLAGS_LONG_LONG) {
+#if defined(PRINTF_SUPPORT_LONG_LONG)
+            idx = _ntoa_long_long(out, buffer, idx, maxlen, va_arg(va, unsigned long long), false, base, precision, width, flags);
+#endif
+          }
+          else if (flags & FLAGS_LONG) {
+            idx = _ntoa_long(out, buffer, idx, maxlen, va_arg(va, unsigned long), false, base, precision, width, flags);
+          }
+          else {
+            const unsigned int value = (flags & FLAGS_CHAR) ? (unsigned char)va_arg(va, unsigned int) : (flags & FLAGS_SHORT) ? (unsigned short int)va_arg(va, unsigned int) : va_arg(va, unsigned int);
+            idx = _ntoa_long(out, buffer, idx, maxlen, value, false, base, precision, width, flags);
+          }
+        }
+        format++;
+        break;
+      }
+#if defined(PRINTF_SUPPORT_FLOAT)
+      case 'f' :
+      case 'F' :
+        if (*format == 'F') flags |= FLAGS_UPPERCASE;
+        idx = _ftoa(out, buffer, idx, maxlen, va_arg(va, double), precision, width, flags);
+        format++;
+        break;
+#if defined(PRINTF_SUPPORT_EXPONENTIAL)
+      case 'e':
+      case 'E':
+      case 'g':
+      case 'G':
+        if ((*format == 'g')||(*format == 'G')) flags |= FLAGS_ADAPT_EXP;
+        if ((*format == 'E')||(*format == 'G')) flags |= FLAGS_UPPERCASE;
+        idx = _etoa(out, buffer, idx, maxlen, va_arg(va, double), precision, width, flags);
+        format++;
+        break;
+#endif  // PRINTF_SUPPORT_EXPONENTIAL
+#endif  // PRINTF_SUPPORT_FLOAT
+      case 'c' : {
+        unsigned int l = 1U;
+        // pre padding
+        if (!(flags & FLAGS_LEFT)) {
+          while (l++ < width) {
+            out(' ', buffer, idx++, maxlen);
+          }
+        }
+        // char output
+        out((char)va_arg(va, int), buffer, idx++, maxlen);
+        // post padding
+        if (flags & FLAGS_LEFT) {
+          while (l++ < width) {
+            out(' ', buffer, idx++, maxlen);
+          }
+        }
+        format++;
+        break;
+      }
+
+      case 's' : {
+        const char* p = va_arg(va, char*);
+        unsigned int l = _strnlen_s(p, precision ? precision : (size_t)-1);
+        // pre padding
+        if (flags & FLAGS_PRECISION) {
+          l = (l < precision ? l : precision);
+        }
+        if (!(flags & FLAGS_LEFT)) {
+          while (l++ < width) {
+            out(' ', buffer, idx++, maxlen);
+          }
+        }
+        // string output
+        while ((*p != 0) && (!(flags & FLAGS_PRECISION) || precision--)) {
+          out(*(p++), buffer, idx++, maxlen);
+        }
+        // post padding
+        if (flags & FLAGS_LEFT) {
+          while (l++ < width) {
+            out(' ', buffer, idx++, maxlen);
+          }
+        }
+        format++;
+        break;
+      }
+
+      case 'p' : {
+        width = sizeof(void*) * 2U;
+        flags |= FLAGS_ZEROPAD | FLAGS_UPPERCASE;
+#if defined(PRINTF_SUPPORT_LONG_LONG)
+        const bool is_ll = sizeof(uintptr_t) == sizeof(long long);
+        if (is_ll) {
+          idx = _ntoa_long_long(out, buffer, idx, maxlen, (uintptr_t)va_arg(va, void*), false, 16U, precision, width, flags);
+        }
+        else {
+#endif
+          idx = _ntoa_long(out, buffer, idx, maxlen, (unsigned long)((uintptr_t)va_arg(va, void*)), false, 16U, precision, width, flags);
+#if defined(PRINTF_SUPPORT_LONG_LONG)
+        }
+#endif
+        format++;
+        break;
+      }
+
+      case '%' :
+        out('%', buffer, idx++, maxlen);
+        format++;
+        break;
+
+      default :
+        out(*format, buffer, idx++, maxlen);
+        format++;
+        break;
+    }
+  }
+
+  // termination
+  out((char)0, buffer, idx < maxlen ? idx : maxlen - 1U, maxlen);
+
+  // return written chars without terminating \0
+  return (int)idx;
+}
+
+
+///////////////////////////////////////////////////////////////////////////////
+
+int printf_(const char* format, ...)
+{
+  va_list va;
+  va_start(va, format);
+  char buffer[1];
+  const int ret = _vsnprintf(_out_char, buffer, (size_t)-1, format, va);
+  va_end(va);
+  return ret;
+}
+
+
+int sprintf_(char* buffer, const char* format, ...)
+{
+  va_list va;
+  va_start(va, format);
+  const int ret = _vsnprintf(_out_buffer, buffer, (size_t)-1, format, va);
+  va_end(va);
+  return ret;
+}
+
+
+int snprintf_(char* buffer, size_t count, const char* format, ...)
+{
+  va_list va;
+  va_start(va, format);
+  const int ret = _vsnprintf(_out_buffer, buffer, count, format, va);
+  va_end(va);
+  return ret;
+}
+
+
+int vprintf_(const char* format, va_list va)
+{
+  char buffer[1];
+  return _vsnprintf(_out_char, buffer, (size_t)-1, format, va);
+}
+
+
+int vsnprintf_(char* buffer, size_t count, const char* format, va_list va)
+{
+  return _vsnprintf(_out_buffer, buffer, count, format, va);
+}
+
+
+int fctprintf(void (*out)(char character, void* arg), void* arg, const char* format, ...)
+{
+  va_list va;
+  va_start(va, format);
+  const out_fct_wrap_type out_fct_wrap = { out, arg };
+  const int ret = _vsnprintf(_out_fct, (char*)(uintptr_t)&out_fct_wrap, (size_t)-1, format, va);
+  va_end(va);
+  return ret;
+}

AngeloJacobo_RISC-V/test/lib/rv32i.h

@@ -0,0 +1,282 @@
+#include <stdint.h>
+
+// I2C memory-mapped registers
+#define I2C_START 0x800000A0
+#define I2C_WRITE 0x800000A4
+#define I2C_READ 0x800000A8
+#define I2C_BUSY 0x800000AC
+#define I2C_ACK 0x800000B0
+#define I2C_READ_DATA_READY 0x800000B4
+#define I2C_STOP 0x800000B8
+
+// UART memory-mapped registers
+#define UART_TX_DATA 0x80000050
+#define UART_TX_BUSY 0x80000054
+#define UART_RX_BUFFER_FULL 0x80000058
+#define UART_RX_DATA 0x8000005C
+
+//GPIO memory-mapped registers
+#define GPIO_MODE 0x800000F0
+#define GPIO_READ 0x800000F4
+#define GPIO_WRITE 0x800000F8
+
+// CLINT memory-mapped registers
+#define CPU_CLK_HZ 12000000
+#define MTIME_BASE_ADDRESS 0x80000000
+#define MTIMECMP_BASE_ADDRESS 0x80000008
+#define MSIP_BASE_ADDRESS 0x80000010
+
+// Registers used in HygroPMOD
+#define HYGROI2C_I2C_ADDR   0x40
+#define HYGROI2C_TMP_REG    0x00
+#define HYGROI2C_HUM_REG    0x01
+#define HYGROI2C_CONFIG_REG 0x02
+
+// Control Status Registers
+#define MARCHID 0xF12
+#define MIMPID 0xF13
+#define MHARTID 0xF14
+#define MSTATUS 0x300 
+#define MISA 0x301
+#define MIE 0x304
+#define MTVEC 0x305
+#define MSCRATCH 0x340 
+#define MEPC 0x341
+#define MCAUSE 0x342
+#define MTVAL 0x343
+#define MIP 0x344
+#define MCYCLE 0xB00
+#define MCYCLEH 0xB80
+#define TIME 0xC01
+#define TIMEH 0xC81
+#define MINSTRET 0xB02
+#define MINSTRETH 0xBB2
+#define MCOUNTINHIBIT 0x320
+
+#define MSTATUS_MIE 3
+#define MIP_MSIP 3
+#define MIP_MTIP 7
+#define MIP_MEIP 11
+#define MIE_MSIE 3
+#define MIE_MTIE 7
+#define MIE_MEIE 11
+
+// LCD cpnfigurations
+#define LCD_I2C_ADDR 0x27 
+#define LCD_BACKLIGHT 0x08
+#define LCD_NOBACKLIGHT 0x00
+#define LCD_FIRST_ROW  0x80
+#define LCD_SECOND_ROW 0xC0
+#define LCD_THIRD_ROW 0x94
+#define LCD_FOURTH_ROW 0xD4
+#define LCD_CLEAR 0x01
+#define LCD_RETURN_HOME 0x02
+#define LCD_ENTRY_MODE_SET 0x04
+#define LCD_CURSOR_OFF 0x0C
+#define LCD_UNDERLINE_ON 0x0E
+#define LCD_BLINK_CURSOR_ON 0x0F
+#define LCD_MOVE_CURSOR_LEFT 0x10
+#define LCD_MOVE_CURSOR_RIGHT 0x14
+#define LCD_TURN_ON 0x0C
+#define LCD_TURN_OFF 0x08
+#define LCD_SHIFT_LEFT 0x18
+#define LCD_SHIFT_RIGHT 0x1E
+#define LCD_TYPE 2 // 0 -> 5x7 | 1 -> 5x10 | 2 -> 2 lines
+
+// Function prototypes for clint.c
+void mtime_set_time(uint64_t time); // set current system time.
+uint64_t mtime_get_time(void) ; // return current system time.
+void mtime_set_timecmp(uint64_t timecmp); // set compare time register (generates timer interrupts when mtime>=mtimecmp)
+uint64_t mtime_get_timecmp(void); // Get compare time register 
+void trap_handler_setup(void (*trap_handler)(void)); //setup trap handler by setting MTVEC and initially disabling all interrupts (NOTE: trap handler function MUST HAVE ATTRIBUTE INTERRUPT)
+void enable_software_interrupt(void); // trurn on software interrupt
+void disable_software_interrupt(void); // turn off software interrupt
+uint64_t ms_to_cpu_ticks (uint64_t ms); // convert milliseconds input to cpu clock ticks
+void delay_ms(uint64_t ms); // delay function based on milliseconds
+void delay_ticks(uint32_t ticks); // delay function based on cpu clock tick
+void delay_us(uint64_t us); // delay function based on microseconds
+uint32_t cpu_ticks_to_us (uint64_t ticks); // convert cpu clock ticks to us
+
+// Inline functions go to header file
+static inline void __attribute__ ((always_inline)) csr_set(const int csr_id, uint32_t mask) { // set bits in CSR
+  uint32_t csr_data = mask;
+  asm volatile ("csrs %[input_i], %[input_j]" :  : [input_i] "i" (csr_id), [input_j] "r" (csr_data));
+}
+inline void __attribute__ ((always_inline)) csr_write(const int csr_id, uint32_t data) { // write to csr
+  uint32_t csr_data = data;
+  asm volatile ("csrw %[input_i], %[input_j]" :  : [input_i] "i" (csr_id), [input_j] "r" (csr_data));
+}
+
+// Function prototypes for i2c.c [[REPEATED START NOT SUPPORTED]]
+uint8_t i2c_write_address(uint8_t addr); // start i2c by writing slave address (returns slave ack)
+void i2c_stop(void); // stop current i2c transaction
+uint8_t i2c_write_byte(uint8_t data); // write to slave (returns slave ack) (after i2c_write_address())
+uint8_t i2c_read_byte(); //read a byte from the slave (after i2c_write_address())
+
+// Function prototypes for uart.c
+void uart_print(char *message); // print characters serially via UART
+int uart_rx_buffer_full(); //check if read buffer is full and data can be read
+char uart_read(); //read data from buffer (make sure to check first if rx buffer is full)
+
+// Function prototypes for gpio.c
+void toggle_gpio(uint32_t pin_number); //toggle a specific GPIO pin (automatically set pin to write mode)
+void gpio_set_mode_pin(uint32_t pin_number, uint32_t mode); //set mode setting of a single GPIO pin(read = 0, write = 1)
+void gpio_write_pin(uint32_t pin_number, uint32_t val); //write to a specific GPIO pin (automatically set pin to write mode)
+uint32_t gpio_read_pin(uint32_t pin_number); //read a specific GPIO pin
+uint32_t gpio_pulse_duration_us(uint32_t pin_number, uint32_t val); //measure pulse duration of a GPIO pin in us
+uint32_t gpio_read_mode(); //read mode setting of the GPIOs (read = 0, write = 1)
+void gpio_set_mode(uint32_t mode); //set mode setting og the GPIOs (read = 0, write = 1)
+void gpio_write(uint32_t write); //write to GPIOs
+uint32_t gpio_write_value(); //read current write value of GPIOs
+uint32_t gpio_read(); //read GPIO
+
+// Function prototypes for lcd.c
+void LCD_Init(); //initialize LCD with proper routine
+void LCD_Set_Cursor(unsigned char ROW, unsigned char COL); //Set cursor where to start writing to LCD
+void LCD_Write_String(char*); //write string to LCD
+void Backlight(void); //turn on backlight (initially turned on)
+void noBacklight(void); //turn off backlight
+void IO_Expander_Write(unsigned char Data);
+void LCD_Write_4Bit(unsigned char Nibble);
+void LCD_CMD(unsigned char CMD);
+void LCD_Write_Char(char);
+void LCD_SR(void);
+void LCD_SL(void);
+void LCD_Clear(void);
+
+// Function prototypes for hygro_pmod.c
+float hygroi2c_getTemperature(); //captures a temperature reading from the Pmod HYGRO
+float hygroi2c_getHumidity(); //captures a humidity reading from the Pmod HYGRO
+void  hygroi2c_begin(); //initializes the Hygro I2C interface (must be done before every temp and humidity measurement)
+uint8_t hygroi2c_writeRegI2C(uint8_t bReg, uint16_t bVal);
+uint8_t hygroi2c_readRegI2C(uint8_t bReg, uint16_t *rVal, uint32_t delay_in_ms);
+float hygroi2c_tempC2F(float tempC);
+float hygroi2c_tempF2C(float tempF);
+
+
+// Function prototypes for ultrasonic_sensor.c
+int ultrasonic_sensor_cm(int trig_pin, int echo_pin); // returns distance in cm detected by the ultrasonic sensor
+
+
+// Header file for prinf.c Sourced from: https://github.com/mpaland/printf
+///////////////////////////////////////////////////////////////////////////////
+// \author (c) Marco Paland (info@paland.com)
+//             2014-2019, PALANDesign Hannover, Germany
+//
+// \license The MIT License (MIT)
+//
+// Permission is hereby granted, free of charge, to any person obtaining a copy
+// of this software and associated documentation files (the "Software"), to deal
+// in the Software without restriction, including without limitation the rights
+// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+// copies of the Software, and to permit persons to whom the Software is
+// furnished to do so, subject to the following conditions:
+// 
+// The above copyright notice and this permission notice shall be included in
+// all copies or substantial portions of the Software.
+// 
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+// THE SOFTWARE.
+//
+// \brief Tiny printf, sprintf and snprintf implementation, optimized for speed on
+//        embedded systems with a very limited resources.
+//        Use this instead of bloated standard/newlib printf.
+//        These routines are thread safe and reentrant.
+//
+///////////////////////////////////////////////////////////////////////////////
+
+#ifndef _PRINTF_H_
+#define _PRINTF_H_
+
+#include <stdarg.h>
+#include <stddef.h>
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/**
+ * Output a character to a custom device like UART, used by the printf() function
+ * This function is declared here only. You have to write your custom implementation somewhere
+ * \param character Character to output
+ */
+void _putchar(char character);
+
+
+/**
+ * Tiny printf implementation
+ * You have to implement _putchar if you use printf()
+ * To avoid conflicts with the regular printf() API it is overridden by macro defines
+ * and internal underscore-appended functions like printf_() are used
+ * \param format A string that specifies the format of the output
+ * \return The number of characters that are written into the array, not counting the terminating null character
+ */
+#define printf printf_
+int printf_(const char* format, ...);
+
+
+/**
+ * Tiny sprintf implementation
+ * Due to security reasons (buffer overflow) YOU SHOULD CONSIDER USING (V)SNPRINTF INSTEAD!
+ * \param buffer A pointer to the buffer where to store the formatted string. MUST be big enough to store the output!
+ * \param format A string that specifies the format of the output
+ * \return The number of characters that are WRITTEN into the buffer, not counting the terminating null character
+ */
+#define sprintf sprintf_
+int sprintf_(char* buffer, const char* format, ...);
+
+
+/**
+ * Tiny snprintf/vsnprintf implementation
+ * \param buffer A pointer to the buffer where to store the formatted string
+ * \param count The maximum number of characters to store in the buffer, including a terminating null character
+ * \param format A string that specifies the format of the output
+ * \param va A value identifying a variable arguments list
+ * \return The number of characters that COULD have been written into the buffer, not counting the terminating
+ *         null character. A value equal or larger than count indicates truncation. Only when the returned value
+ *         is non-negative and less than count, the string has been completely written.
+ */
+#define snprintf  snprintf_
+#define vsnprintf vsnprintf_
+int  snprintf_(char* buffer, size_t count, const char* format, ...);
+int vsnprintf_(char* buffer, size_t count, const char* format, va_list va);
+
+
+/**
+ * Tiny vprintf implementation
+ * \param format A string that specifies the format of the output
+ * \param va A value identifying a variable arguments list
+ * \return The number of characters that are WRITTEN into the buffer, not counting the terminating null character
+ */
+#define vprintf vprintf_
+int vprintf_(const char* format, va_list va);
+
+
+/**
+ * printf with output function
+ * You may use this as dynamic alternative to printf() with its fixed _putchar() output
+ * \param out An output function which takes one character and an argument pointer
+ * \param arg An argument pointer for user data passed to output function
+ * \param format A string that specifies the format of the output
+ * \return The number of characters that are sent to the output function, not counting the terminating null character
+ */
+int fctprintf(void (*out)(char character, void* arg), void* arg, const char* format, ...);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif  // _PRINTF_H_
+
+
+
+

AngeloJacobo_RISC-V/test/lib/uart.c

@@ -0,0 +1,37 @@
+#include <stdint.h> 
+#include <rv32i.h>
+
+volatile uint32_t *uart_tx_data = (volatile uint32_t *) UART_TX_DATA;
+volatile uint32_t *uart_tx_busy = (volatile uint32_t *) UART_TX_BUSY;
+volatile uint32_t *uart_rx_full = (volatile uint32_t *) UART_RX_BUFFER_FULL;
+volatile uint32_t *uart_rx_data = (volatile uint32_t *) UART_RX_DATA;
+
+// print characters serially via UART
+void uart_print(char *message) {
+    int i = 0;
+    while (message[i] != '\0') {
+        while (*uart_tx_busy);  // wait for UART to be ready
+        *uart_tx_data = message[i];
+        i++;
+    }
+}
+
+//check if read buffer is full and data can be read
+int uart_rx_buffer_full(){
+    int ready = *uart_rx_full;
+    return ready;
+}
+
+//read data from buffer (make sure to check first if rx buffer is full)
+char uart_read(){
+    char read_data;
+    read_data = *uart_rx_data; 
+    return read_data;
+}
+
+
+
+
+
+
+

AngeloJacobo_RISC-V/test/lib/ultrasonic_sensor.c

@@ -0,0 +1,27 @@
+#include <stdint.h>
+#include <rv32i.h>
+
+// returns distance in cm detected by the ultrasonic sensor
+int ultrasonic_sensor_cm(int trig_pin, int echo_pin){
+    int pulse_duration_us;
+    int distance_cm;
+    
+    gpio_set_mode_pin(trig_pin, 1); //set mode setting of a single GPIO pin(read = 0, write = 1)
+    gpio_set_mode_pin(echo_pin, 0); //set mode setting of a single GPIO pin(read = 0, write = 1)
+
+    // set trig_pin for 10us
+    gpio_write_pin(trig_pin, 0); //write to a specific GPIO pin (automatically set pin to write mode)
+    delay_us(2); // delay function based on microseconds
+    gpio_write_pin(trig_pin, 1); //write to a specific GPIO pin (automatically set pin to write mode)
+    delay_us(10); // delay function based on microseconds
+    gpio_write_pin(trig_pin, 0); //write to a specific GPIO pin (automatically set pin to write mode)
+    
+    pulse_duration_us = gpio_pulse_duration_us(echo_pin, 1); //measure how long will be the high pulse
+    distance_cm = pulse_duration_us*(0.034/2);  
+    return distance_cm;
+}
+
+
+
+
+

AngeloJacobo_RISC-V/test/rv32i_soc.v

@@ -0,0 +1,1357 @@
+// Core plus memory
+
+`timescale 1ns / 1ps
+`default_nettype none
+//`define ICARUS use faster UARt and I2C rate for faster simulation
+
+//complete package containing the rv32i_core, RAM, and IO peripherals (I2C and UART)
+module rv32i_soc #(parameter CLK_FREQ_MHZ=12, PC_RESET=32'h00_00_00_00, TRAP_ADDRESS=32'h00_00_00_00, ZICSR_EXTENSION=1, MEMORY_DEPTH=81920, GPIO_COUNT = 12) ( 
+    input wire i_clk,
+    input wire i_rst,
+    //UART
+    input wire uart_rx,
+    output wire uart_tx,
+    //I2C
+    inout wire i2c_sda,
+    inout wire i2c_scl,
+    //GPIO
+    inout wire[GPIO_COUNT-1:0] gpio_pins
+    );
+
+    
+    //Instruction Memory Interface
+    wire[31:0] inst; 
+    wire[31:0] iaddr;  
+    wire i_stb_inst;
+    wire o_ack_inst;
+    
+    //Data Memory Interface
+    wire[31:0] i_wb_data_data; //data retrieved from memory
+    wire[31:0] o_wb_data_data; //data to be stored to memory
+    wire[31:0] wb_addr_data; //address of data memory for store/load
+    wire[3:0] wb_sel_data; //byte strobe for write (1 = write the byte) {byte3,byte2,byte1,byte0}
+    wire wb_we_data; //write-enable (1 = write, 0 = read) 
+    wire wb_stb_data; //request for read/write access to data memory
+    wire wb_ack_data; //ack by data memory (high when data to be read is ready or when write data is already written
+    wire wb_cyc_data; //bus cycle active (1 = normal operation, 0 = all ongoing transaction are to be cancelled)
+    wire wb_stall_data; //stall by data memory
+    
+    //Interrupts
+    wire i_external_interrupt = 0; //interrupt from external source
+    wire o_timer_interrupt; //interrupt from CLINT
+    wire o_software_interrupt; //interrupt from CLINT
+    
+    //Memory Wrapper
+    wire device0_wb_cyc;
+    wire device0_wb_stb;
+    wire device0_wb_we;
+    wire[31:0] device0_wb_addr;
+    wire[31:0] o_device0_wb_data;
+    wire[3:0] device0_wb_sel;
+    wire device0_wb_ack;
+    wire device0_wb_stall;
+    wire[31:0] i_device0_wb_data;
+
+    wire device1_wb_cyc;
+    wire device1_wb_stb;
+    wire device1_wb_we;
+    wire[31:0] device1_wb_addr;
+    wire[31:0] o_device1_wb_data;
+    wire[3:0] device1_wb_sel;
+    wire device1_wb_ack;
+    wire device1_wb_stall;
+    wire[31:0] i_device1_wb_data;
+
+    wire device2_wb_cyc;
+    wire device2_wb_stb;
+    wire device2_wb_we;
+    wire[31:0] device2_wb_addr;
+    wire[31:0] o_device2_wb_data;
+    wire[3:0] device2_wb_sel;
+    wire device2_wb_ack;
+    wire device2_wb_stall;
+    wire[31:0] i_device2_wb_data;
+
+    wire device3_wb_cyc;
+    wire device3_wb_stb;
+    wire device3_wb_we;
+    wire[31:0] device3_wb_addr;
+    wire[31:0] o_device3_wb_data;
+    wire[3:0] device3_wb_sel;
+    wire device3_wb_ack;
+    wire device3_wb_stall;
+    wire[31:0] i_device3_wb_data;
+
+    wire device4_wb_cyc;
+    wire device4_wb_stb;
+    wire device4_wb_we;
+    wire[31:0] device4_wb_addr;
+    wire[31:0] o_device4_wb_data;
+    wire[3:0] device4_wb_sel;
+    wire device4_wb_ack;
+    wire device4_wb_stall;
+    wire[31:0] i_device4_wb_data;
+
+    wire device5_wb_cyc;
+    wire device5_wb_stb;
+    wire device5_wb_we;
+    wire[31:0] device5_wb_addr;
+    wire[31:0] o_device5_wb_data;
+    wire[3:0] device5_wb_sel;
+    wire device5_wb_ack;
+    wire device5_wb_stall;
+    wire[31:0] i_device5_wb_data;
+
+    rv32i_core #(.PC_RESET(PC_RESET), .TRAP_ADDRESS(TRAP_ADDRESS), .ZICSR_EXTENSION(ZICSR_EXTENSION)) m0( //main RV32I core
+        .i_clk(i_clk),
+        .i_rst_n(!i_rst),
+        //Instruction Memory Interface
+        .i_inst(inst), //32-bit instruction
+        .o_iaddr(iaddr), //address of instruction 
+        .o_stb_inst(i_stb_inst), //request for read access to instruction memory
+        .i_ack_inst(o_ack_inst),  //ack (high if new instruction is ready)
+        //Data Memory Interface
+        .o_wb_cyc_data(wb_cyc_data), //bus cycle active (1 = normal operation, 0 = all ongoing transaction are to be cancelled)
+        .o_wb_stb_data(wb_stb_data), //request for read/write access to data memory
+        .o_wb_we_data(wb_we_data), //write-enable (1 = write, 0 = read)
+        .o_wb_addr_data(wb_addr_data), //address of data memory for store/load
+        .o_wb_data_data(o_wb_data_data), //data to be stored to memory
+        .o_wb_sel_data(wb_sel_data), //byte strobe for write (1 = write the byte) {byte3,byte2,byte1,byte0}
+        .i_wb_ack_data(wb_ack_data), //ack by data memory (high when read data is ready or when write data is already written)
+        .i_wb_stall_data(wb_stall_data), //stall by data memory
+        .i_wb_data_data(i_wb_data_data), //data retrieved from memory
+        //Interrupts
+        .i_external_interrupt(i_external_interrupt), //interrupt from external source
+        .i_software_interrupt(o_software_interrupt), //interrupt from software (inter-processor interrupt)
+        .i_timer_interrupt(o_timer_interrupt) //interrupt from timer
+     );
+        
+    memory_wrapper wrapper( //decodes address and access the corresponding memory-mapped device
+        //RISC-V Core
+        .i_wb_cyc(wb_cyc_data),
+        .i_wb_stb(wb_stb_data),
+        .i_wb_we(wb_we_data),
+        .i_wb_addr(wb_addr_data),
+        .i_wb_data(o_wb_data_data),
+        .i_wb_sel(wb_sel_data),
+        .o_wb_ack(wb_ack_data),
+        .o_wb_stall(wb_stall_data),
+        .o_wb_data(i_wb_data_data),
+
+        //Device 0 Interface (RAM)
+        .o_device0_wb_cyc(device0_wb_cyc),
+        .o_device0_wb_stb(device0_wb_stb),
+        .o_device0_wb_we(device0_wb_we),
+        .o_device0_wb_addr(device0_wb_addr),
+        .o_device0_wb_data(o_device0_wb_data),
+        .o_device0_wb_sel(device0_wb_sel),
+        .i_device0_wb_ack(device0_wb_ack),
+        .i_device0_wb_stall(device0_wb_stall),
+        .i_device0_wb_data(i_device0_wb_data),
+
+        //Device 1 Interface (CLINT)
+        .o_device1_wb_cyc(device1_wb_cyc),
+        .o_device1_wb_stb(device1_wb_stb),
+        .o_device1_wb_we(device1_wb_we),
+        .o_device1_wb_addr(device1_wb_addr),
+        .o_device1_wb_data(o_device1_wb_data),
+        .o_device1_wb_sel(device1_wb_sel),
+        .i_device1_wb_ack(device1_wb_ack),
+        .i_device1_wb_stall(device1_wb_stall),
+        .i_device1_wb_data(i_device1_wb_data),
+        
+        //Device 2 Interface (UART)
+        .o_device2_wb_cyc(device2_wb_cyc),
+        .o_device2_wb_stb(device2_wb_stb),
+        .o_device2_wb_we(device2_wb_we),
+        .o_device2_wb_addr(device2_wb_addr),
+        .o_device2_wb_data(o_device2_wb_data),
+        .o_device2_wb_sel(device2_wb_sel),
+        .i_device2_wb_ack(device2_wb_ack),
+        .i_device2_wb_stall(device2_wb_stall),
+        .i_device2_wb_data(i_device2_wb_data),
+        
+        //Device 3 Interface (I2C)
+        .o_device3_wb_cyc(device3_wb_cyc),
+        .o_device3_wb_stb(device3_wb_stb),
+        .o_device3_wb_we(device3_wb_we),
+        .o_device3_wb_addr(device3_wb_addr),
+        .o_device3_wb_data(o_device3_wb_data),
+        .o_device3_wb_sel(device3_wb_sel),
+        .i_device3_wb_ack(device3_wb_ack),
+        .i_device3_wb_stall(device3_wb_stall),
+        .i_device3_wb_data(i_device3_wb_data),
+        
+        //Device 4 Interface (GPIO)
+        .o_device4_wb_cyc(device4_wb_cyc),
+        .o_device4_wb_stb(device4_wb_stb),
+        .o_device4_wb_we(device4_wb_we),
+        .o_device4_wb_addr(device4_wb_addr),
+        .o_device4_wb_data(o_device4_wb_data),
+        .o_device4_wb_sel(device4_wb_sel),
+        .i_device4_wb_ack(device4_wb_ack),
+        .i_device4_wb_stall(device4_wb_stall),
+        .i_device4_wb_data(i_device4_wb_data),
+
+        //Device 5 Interface (DDR3)
+        .o_device5_wb_cyc(device5_wb_cyc),
+        .o_device5_wb_stb(device5_wb_stb),
+        .o_device5_wb_we(device5_wb_we),
+        .o_device5_wb_addr(device5_wb_addr),
+        .o_device5_wb_data(o_device5_wb_data),
+        .o_device5_wb_sel(device5_wb_sel),
+        .i_device5_wb_ack(device5_wb_ack),
+        .i_device5_wb_stall(device5_wb_stall),
+        .i_device5_wb_data(i_device5_wb_data)
+    );   
+
+    // DEVICE 0
+     main_memory #(.MEMORY_DEPTH(MEMORY_DEPTH)) m1( //Instruction and Data memory (combined memory) 
+        .i_clk(i_clk),
+        // Instruction Memory
+        .i_inst_addr(iaddr[$clog2(MEMORY_DEPTH)-1:0]),
+        .o_inst_out(inst),
+        .i_stb_inst(i_stb_inst), 
+        .o_ack_inst(o_ack_inst), 
+        // Data Memory
+        .i_wb_cyc(device0_wb_cyc),
+        .i_wb_stb(device0_wb_stb),
+        .i_wb_we(device0_wb_we),
+        .i_wb_addr(device0_wb_addr[$clog2(MEMORY_DEPTH)-1:0]),
+        .i_wb_data(o_device0_wb_data),
+        .i_wb_sel(device0_wb_sel),
+        .o_wb_ack(device0_wb_ack),
+        .o_wb_stall(device0_wb_stall),
+        .o_wb_data(i_device0_wb_data)
+    );
+
+    // DEVICE 1
+    rv32i_clint #( //Core Logic Interrupt [memory-mapped to < h50 (MSB=1)]
+        .CLK_FREQ_MHZ(CLK_FREQ_MHZ), //input clock frequency in MHz
+        .MTIME_BASE_ADDRESS(32'h8000_0000),  //Machine-level timer register (64-bits, 2 words)
+        .MTIMECMP_BASE_ADDRESS(32'h8000_0008), //Machine-level Time Compare register (64-bits, 2 words)
+        .MSIP_BASE_ADDRESS(32'h8000_0010) //Machine-level Software Interrupt register
+    ) clint  (
+        .clk(i_clk),
+        .rst_n(!i_rst),
+        .i_wb_cyc(device1_wb_cyc),
+        .i_wb_stb(device1_wb_stb),
+        .i_wb_we(device1_wb_we),
+        .i_wb_addr(device1_wb_addr),
+        .i_wb_data(o_device1_wb_data),
+        .i_wb_sel(device1_wb_sel),
+        .o_wb_ack(device1_wb_ack),
+        .o_wb_stall(device1_wb_stall),
+        .o_wb_data(i_device1_wb_data),
+        // Interrupts
+        .o_timer_interrupt(o_timer_interrupt),
+        .o_software_interrupt(o_software_interrupt)
+    );
+
+    // DEVICE 2
+    uart #( .CLOCK_FREQ(CLK_FREQ_MHZ*1_000_000), //UART (TX only) [memory-mapped to >=h50,<hA0 (MSB=1)]
+            .BAUD_RATE( //UART Baud rate
+              `ifdef ICARUS
+               2_000_000 //faster simulation            delay_count <= 5;
+
+               `else 
+               9600 //9600 Baud
+               `endif),
+            .UART_TX_DATA(32'h8000_0050), //memory-mapped address for TX
+            .UART_TX_BUSY(32'h8000_0054), //memory-mapped address to check if TX is busy (has ongoing request)
+            .UART_RX_BUFFER_FULL(32'h8000_0058), //memory-mapped address  to check if a read has completed
+            .UART_RX_DATA(32'h8000_005C), //memory-mapped address for RX 
+            .DBIT(8), //UART Data Bits
+            .SBIT(1) //UART Stop Bits
+     ) uart
+     (
+        .clk(i_clk),
+        .rst_n(!i_rst),
+        .i_wb_cyc(device2_wb_cyc),
+        .i_wb_stb(device2_wb_stb),
+        .i_wb_we(device2_wb_we),
+        .i_wb_addr(device2_wb_addr),
+        .i_wb_data(o_device2_wb_data[7:0]),
+        .i_wb_sel(device2_wb_sel),
+        .o_wb_ack(device2_wb_ack),
+        .o_wb_stall(device2_wb_stall),
+        .o_wb_data(i_device2_wb_data[7:0]),
+        .uart_rx(uart_rx), //UART RX line
+        .uart_tx(uart_tx) //UART TX line
+      );
+
+    // CONTINUE////////////////////////////////////////
+    //DEVICE 3
+    i2c #(.main_clock(CLK_FREQ_MHZ*1_000_000), //SCCB mode(no pullups resistors needed) [memory-mapped to >=A0,<F0 (MSB=1)]
+          .freq( //i2c freqeuncy
+          `ifdef ICARUS
+           2_000_000 //faster simulation
+           `else 
+           100_000 //100KHz
+           `endif),
+          .addr_bytes(1), //addr_bytes=number of bytes of an address
+          .I2C_START(32'h8000_00A0), //write-only memory-mapped address to start i2c (write the i2c slave address)
+          .I2C_WRITE(32'h8000_00A4), //write-only memory-mapped address for sending data to slave
+          .I2C_READ(32'h8000_00A8), //read-only memory-mapped address to read data received from slave (this will also continue reading from slave) 
+          .I2C_BUSY(32'h8000_00AC), //read-only memory-mapped address to check if i2c is busy (cannot accept request)
+          .I2C_ACK(32'h8000_00B0), //read-only memory-mapped address to check if last access has benn acknowledge by slave
+          .I2C_READ_DATA_READY(32'h8000_00B4), //read-only memory-mapped address to check if data to be received from slave is ready
+          .I2C_STOP(32'h8000_00B8) //write-only memory-mapped address to stop i2c (this is persistent thus must be manually turned off after stopping i2c)
+      ) i2c
+      (
+        .clk(i_clk),
+        .rst_n(!i_rst),
+        .i_wb_cyc(device3_wb_cyc),
+        .i_wb_stb(device3_wb_stb),
+        .i_wb_we(device3_wb_we),
+        .i_wb_addr(device3_wb_addr),
+        .i_wb_data(o_device3_wb_data[7:0]),
+        .i_wb_sel(device3_wb_sel),
+        .o_wb_ack(device3_wb_ack),
+        .o_wb_stall(device3_wb_stall),
+        .o_wb_data(i_device3_wb_data[7:0]),
+        .scl(i2c_scl), //i2c bidrectional clock line
+        .sda(i2c_sda) //i2c bidrectional data line
+    );
+    
+    //DEVICE 4
+    gpio #( //General-Purpose Input-Ouput
+        .GPIO_MODE(32'h8000_00F0), //set if GPIO will be read(0) or write(1) 
+        .GPIO_READ(32'h8000_00F4), //read GPIO value
+        .GPIO_WRITE(32'h8000_00F8), //write to GPIO
+        .GPIO_COUNT(12)
+    ) gpio (
+        .clk(i_clk),
+        .rst_n(!i_rst),
+        .i_wb_cyc(device4_wb_cyc),
+        .i_wb_stb(device4_wb_stb),
+        .i_wb_we(device4_wb_we),
+        .i_wb_addr(device4_wb_addr),
+        .i_wb_data(o_device4_wb_data[GPIO_COUNT-1:0]),
+        .i_wb_sel(device4_wb_sel),
+        .o_wb_ack(device4_wb_ack),
+        .o_wb_stall(device4_wb_stall),
+        .o_wb_data(i_device4_wb_data[GPIO_COUNT-1:0]),
+        //GPIO
+        .gpio(gpio_pins) //gpio pins
+    );
+
+`ifdef DDR3
+    wire clk_locked;
+    wire i_controller_clk, i_ddr3_clk, i_ref_clk, i_ddr3_clk_90;
+
+    clk_wiz_0 clk_wiz_inst
+    (
+    // Clock out ports
+    .clk_out1(i_controller_clk), //83.33333 Mhz
+    .clk_out2(i_ddr3_clk), // 333.33333 MHz
+    .clk_out3(i_ref_clk), //200MHz
+    .clk_out4(i_ddr3_clk_90), // 333.33333 MHz vs 90 degrees shift
+    // Status and control signals
+    .reset(i_rst),
+    .locked(clk_locked),
+    // Clock in ports
+    .clk_in1(i_clk) 
+    );
+
+    //DEVICE 5 (DDR3 Controller)
+    ddr3_top #(
+        .CONTROLLER_CLK_PERIOD(12_000), //ps, clock period of the controller interface
+        .DDR3_CLK_PERIOD(3_000), //ps, clock period of the DDR3 RAM device (must be 1/4 of the CONTROLLER_CLK_PERIOD) 
+        .ROW_BITS(14), //width of row address
+        .COL_BITS(10), //width of column address
+        .BA_BITS(3), //width of bank address
+        .DQ_BITS(8),  //device width
+        .LANES(2), //number of DDR3 device to be controlled
+        .AUX_WIDTH(4), //width of aux line (must be >= 4) 
+        .WB2_ADDR_BITS(32), //width of 2nd wishbone address bus 
+        .WB2_DATA_BITS(32), //width of 2nd wishbone data bus
+        .OPT_LOWPOWER(1), //1 = low power, 0 = low logic
+        .OPT_BUS_ABORT(1),  //1 = can abort bus, 0 = no absort (i_wb_cyc will be ignored, ideal for an AXI implementation which cannot abort transaction)
+        .MICRON_SIM(0), //enable faster simulation for micron ddr3 model (shorten POWER_ON_RESET_HIGH and INITIAL_CKE_LOW)
+        .ODELAY_SUPPORTED(0), //set to 1 when ODELAYE2 is supported
+        .SECOND_WISHBONE(0) //set to 1 if 2nd wishbone is needed 
+        ) ddr3_top
+        (
+            //clock and reset
+            .i_controller_clk(i_controller_clk),
+            .i_ddr3_clk(i_ddr3_clk), //i_controller_clk has period of CONTROLLER_CLK_PERIOD, i_ddr3_clk has period of DDR3_CLK_PERIOD 
+            .i_ref_clk(i_ref_clk),
+            .i_ddr3_clk_90(i_ddr3_clk_90),
+            .i_rst_n(!i_rst && clk_locked), 
+            //
+            // Wishbone inputs
+            .i_wb_cyc(device5_wb_cyc), //bus cycle active (1 = normal operation, 0 = all ongoing transaction are to be cancelled)
+            .i_wb_stb(device5_wb_stb), //request a transfer
+            .i_wb_we(device5_wb_we), //write-enable (1 = write, 0 = read)
+            .i_wb_addr(device5_wb_addr), //burst-addressable {row,bank,col} 
+            .i_wb_data(o_device5_wb_data), //write data, for a 4:1 controller data width is 8 times the number of pins on the device
+            .i_wb_sel(device5_wb_sel), //byte strobe for write (1 = write the byte)
+            .i_aux(0), //for AXI-interface compatibility (given upon strobe)
+            // Wishbone outputs
+            .o_wb_stall(device5_wb_stall), //1 = busy, cannot accept requests
+            .o_wb_ack(device5_wb_ack), //1 = read/write request has completed
+            .o_wb_data(i_device5_wb_data), //read data, for a 4:1 controller data width is 8 times the number of pins on the device
+            .o_aux(),
+            //
+            // Wishbone 2 (PHY) inputs
+            .i_wb2_cyc(), //bus cycle active (1 = normal operation, 0 = all ongoing transaction are to be cancelled)
+            .i_wb2_stb(), //request a transfer
+            .i_wb2_we(), //write-enable (1 = write, 0 = read)
+            .i_wb2_addr(), //burst-addressable {row,bank,col} 
+            .i_wb2_data(), //write data, for a 4:1 controller data width is 8 times the number of pins on the device
+            .i_wb2_sel(), //byte strobe for write (1 = write the byte)
+            // Wishbone 2 (Controller) outputs
+            .o_wb2_stall(), //1 = busy, cannot accept requests
+            .o_wb2_ack(), //1 = read/write request has completed
+            .o_wb2_data(), //read data, for a 4:1 controller data width is 8 times the number of pins on the device
+            //
+            // DDR3 I/O Interface
+            .o_ddr3_clk_p(ddr3_clk_p),
+            .o_ddr3_clk_n(ddr3_clk_n),
+            .o_ddr3_reset_n(ddr3_reset_n),
+            .o_ddr3_cke(ddr3_cke), // CKE
+            .o_ddr3_cs_n(ddr3_cs_n), // chip select signal (controls rank 1 only)
+            .o_ddr3_ras_n(ddr3_ras_n), // RAS#
+            .o_ddr3_cas_n(ddr3_cas_n), // CAS#
+            .o_ddr3_we_n(ddr3_we_n), // WE#
+            .o_ddr3_addr(ddr3_addr),
+            .o_ddr3_ba_addr(ddr3_ba),
+            .io_ddr3_dq(ddr3_dq),
+            .io_ddr3_dqs(ddr3_dqs_p),
+            .io_ddr3_dqs_n(ddr3_dqs_n),
+            .o_ddr3_dm(ddr3_dm),
+            .o_ddr3_odt(ddr3_odt), // on-die termination
+            // Debug outputs
+            .o_debug1(),
+            .o_debug2(),
+            .o_debug3(),
+            .o_ddr3_debug_read_dqs_p(),
+            .o_ddr3_debug_read_dqs_n()
+            ////////////////////////////////////
+        );
+        
+`endif
+
+endmodule
+
+
+module memory_wrapper ( //decodes address and access the corresponding memory-mapped device
+    //RISC-V Core
+    input wire i_wb_cyc,
+    input wire i_wb_stb,
+    input wire i_wb_we,
+    input wire[31:0] i_wb_addr,
+    input wire[31:0] i_wb_data,
+    input wire[3:0] i_wb_sel,
+    output reg o_wb_ack,
+    output reg o_wb_stall,
+    output reg[31:0] o_wb_data,
+
+    //Device 0 Interface (RAM)
+    output reg o_device0_wb_cyc,
+    output reg o_device0_wb_stb,
+    output reg o_device0_wb_we,
+    output reg[31:0] o_device0_wb_addr,
+    output reg[31:0] o_device0_wb_data,
+    output reg[3:0] o_device0_wb_sel,
+    input wire i_device0_wb_ack,
+    input wire i_device0_wb_stall,
+    input wire[31:0] i_device0_wb_data,
+
+    //Device 1 Interface (CLINT)
+    output reg o_device1_wb_cyc,
+    output reg o_device1_wb_stb,
+    output reg o_device1_wb_we,
+    output reg[31:0] o_device1_wb_addr,
+    output reg[31:0] o_device1_wb_data,
+    output reg[3:0] o_device1_wb_sel,
+    input wire i_device1_wb_ack,
+    input wire i_device1_wb_stall,
+    input wire[31:0] i_device1_wb_data,
+
+    //Device 2 Interface (UART)
+    output reg o_device2_wb_cyc,
+    output reg o_device2_wb_stb,
+    output reg o_device2_wb_we,
+    output reg[31:0] o_device2_wb_addr,
+    output reg[31:0] o_device2_wb_data,
+    output reg[3:0] o_device2_wb_sel,
+    input wire i_device2_wb_ack,
+    input wire i_device2_wb_stall,
+    input wire[31:0] i_device2_wb_data,
+
+    //Device 3 Interface (I2C)
+    output reg o_device3_wb_cyc,
+    output reg o_device3_wb_stb,
+    output reg o_device3_wb_we,
+    output reg[31:0] o_device3_wb_addr,
+    output reg[31:0] o_device3_wb_data,
+    output reg[3:0] o_device3_wb_sel,
+    input wire i_device3_wb_ack,
+    input wire i_device3_wb_stall,
+    input wire[31:0] i_device3_wb_data,
+    
+    //Device 4 Interface (GPIO)
+    output reg o_device4_wb_cyc,
+    output reg o_device4_wb_stb,
+    output reg o_device4_wb_we,
+    output reg[31:0] o_device4_wb_addr,
+    output reg[31:0] o_device4_wb_data,
+    output reg[3:0] o_device4_wb_sel,
+    input wire i_device4_wb_ack,
+    input wire i_device4_wb_stall,
+    input wire[31:0] i_device4_wb_data,
+
+    //Device 5 Interface (DDR3)
+    output reg o_device5_wb_cyc,
+    output reg o_device5_wb_stb,
+    output reg o_device5_wb_we,
+    output reg[31:0] o_device5_wb_addr,
+    output reg[31:0] o_device5_wb_data,
+    output reg[3:0] o_device5_wb_sel,
+    input wire i_device5_wb_ack,
+    input wire i_device5_wb_stall,
+    input wire[31:0] i_device5_wb_data
+);
+
+
+    always @* begin 
+        o_wb_ack = 0;
+        o_wb_stall = 0;
+        o_wb_data = 0;
+
+        o_device0_wb_cyc = 0;
+        o_device0_wb_stb = 0;
+        o_device0_wb_we = 0;
+        o_device0_wb_addr = 0;
+        o_device0_wb_data = 0;
+        o_device0_wb_sel = 0;
+
+        o_device1_wb_cyc = 0;
+        o_device1_wb_stb = 0;
+        o_device1_wb_we = 0;
+        o_device1_wb_addr = 0;
+        o_device1_wb_data = 0;
+        o_device1_wb_sel = 0;
+
+        o_device2_wb_cyc = 0;
+        o_device2_wb_stb = 0;
+        o_device2_wb_we = 0;
+        o_device2_wb_addr = 0;
+        o_device2_wb_data = 0;
+        o_device2_wb_sel = 0;
+
+        o_device3_wb_cyc = 0;
+        o_device3_wb_stb = 0;
+        o_device3_wb_we = 0;
+        o_device3_wb_addr = 0;
+        o_device3_wb_data = 0;
+        o_device3_wb_sel = 0;
+
+        o_device4_wb_cyc = 0;
+        o_device4_wb_stb = 0;
+        o_device4_wb_we = 0;
+        o_device4_wb_addr = 0;
+        o_device4_wb_data = 0;
+        o_device4_wb_sel = 0;
+
+        o_device5_wb_cyc = 0;
+        o_device5_wb_stb = 0;
+        o_device5_wb_we = 0;
+        o_device5_wb_addr = 0;
+        o_device5_wb_data = 0;
+        o_device5_wb_sel = 0;
+
+        // Memory-mapped peripherals address has MSB set to 1
+        if(i_wb_addr[31]) begin
+            if(i_wb_addr[11:0] < 12'h50) begin //Device 1 Interface (CLINT) (20 words)
+                o_device1_wb_cyc = i_wb_cyc;
+                o_device1_wb_stb = i_wb_stb;
+                o_device1_wb_we = i_wb_we;
+                o_device1_wb_addr = i_wb_addr; 
+                o_device1_wb_data = i_wb_data;
+                o_device1_wb_sel = i_wb_sel; 
+                o_wb_ack = i_device1_wb_ack;
+                o_wb_stall = i_device1_wb_stall;
+                o_wb_data = i_device1_wb_data;
+            end
+            
+            if(i_wb_addr[11:0] >= 12'h50 && i_wb_addr[11:0] < 12'hA0) begin //Device 2 Interface (UART) (20 words)
+                o_device2_wb_cyc = i_wb_cyc;
+                o_device2_wb_stb = i_wb_stb;
+                o_device2_wb_we = i_wb_we;
+                o_device2_wb_addr = i_wb_addr; 
+                o_device2_wb_data = i_wb_data;
+                o_device2_wb_sel = i_wb_sel; 
+                o_wb_ack = i_device2_wb_ack;
+                o_wb_stall = i_device2_wb_stall;
+                o_wb_data = i_device2_wb_data;
+            end
+
+            if(i_wb_addr[11:0] >= 12'hA0 && i_wb_addr[11:0] < 12'hF0) begin //Device 3 Interface (I2C) (20 words)
+                o_device3_wb_cyc = i_wb_cyc;
+                o_device3_wb_stb = i_wb_stb;
+                o_device3_wb_we = i_wb_we;
+                o_device3_wb_addr = i_wb_addr; 
+                o_device3_wb_data = i_wb_data;
+                o_device3_wb_sel = i_wb_sel; 
+                o_wb_ack = i_device3_wb_ack;
+                o_wb_stall = i_device3_wb_stall;
+                o_wb_data = i_device3_wb_data;
+            end
+            
+            if(i_wb_addr[11:0] >= 12'hF0 && i_wb_addr[11:0] < 12'h140) begin //Device 4 Interface (GPIO) (20 words)
+                o_device4_wb_cyc = i_wb_cyc;
+                o_device4_wb_stb = i_wb_stb;
+                o_device4_wb_we = i_wb_we;
+                o_device4_wb_addr = i_wb_addr; 
+                o_device4_wb_data = i_wb_data;
+                o_device4_wb_sel = i_wb_sel; 
+                o_wb_ack = i_device4_wb_ack;
+                o_wb_stall = i_device4_wb_stall;
+                o_wb_data = i_device4_wb_data;
+            end
+
+            if(i_wb_addr[30]) begin //Device 5 Interface (DDR3) (last two bits of address are high)
+                o_device5_wb_cyc = i_wb_cyc;
+                o_device5_wb_stb = i_wb_stb;
+                o_device5_wb_we = i_wb_we;
+                o_device5_wb_addr = i_wb_addr; 
+                o_device5_wb_data = i_wb_data;
+                o_device5_wb_sel = i_wb_sel; 
+                o_wb_ack = i_device5_wb_ack;
+                o_wb_stall = i_device5_wb_stall;
+                o_wb_data = i_device5_wb_data;
+            end
+        end
+        
+        // Else access RAM
+        else begin  //Device 0 Interface (RAM)
+            o_device0_wb_cyc = i_wb_cyc;
+            o_device0_wb_stb = i_wb_stb;
+            o_device0_wb_we = i_wb_we;
+            o_device0_wb_addr = i_wb_addr; 
+            o_device0_wb_data = i_wb_data;
+            o_device0_wb_sel = i_wb_sel; 
+            o_wb_ack = i_device0_wb_ack;
+            o_wb_stall = i_device0_wb_stall;
+            o_wb_data = i_device0_wb_data;
+        end
+    end
+ 
+endmodule
+module main_memory #(parameter MEMORY_DEPTH=1024) ( //Instruction and Data memory (combined memory)
+    input wire i_clk,
+    // Instruction Memory
+    input wire[$clog2(MEMORY_DEPTH)-1:0] i_inst_addr,
+    output reg[31:0] o_inst_out,
+    input wire i_stb_inst, // request for instruction
+    output reg o_ack_inst, //ack (high if new instruction is now on the bus)
+    // Data Memory
+    input wire i_wb_cyc,
+    input wire i_wb_stb,
+    input wire i_wb_we,
+    input wire[$clog2(MEMORY_DEPTH)-1:0] i_wb_addr,
+    input wire[31:0] i_wb_data,
+    input wire[3:0] i_wb_sel,
+    output reg o_wb_ack,
+    output wire o_wb_stall,
+    output reg[31:0] o_wb_data
+);
+    reg[31:0] memory_regfile[MEMORY_DEPTH/4 - 1:0];
+    integer i;
+    assign o_wb_stall = 0; // never stall
+
+    initial begin //initialize memory to zero
+        o_ack_inst <= 0;
+        o_wb_ack <= 0;
+        o_inst_out <= 0;
+    end
+    
+    //reading must be registered to be inferred as block ram
+    always @(posedge i_clk) begin 
+        o_ack_inst <= i_stb_inst; //go high next cycle after receiving request (data o_inst_out is also sent at next cycle)
+        o_wb_ack <= i_wb_stb && i_wb_cyc;
+        o_inst_out <= memory_regfile[{i_inst_addr>>2}]; //read instruction 
+        o_wb_data <= memory_regfile[i_wb_addr[$clog2(MEMORY_DEPTH)-1:2]]; //read data    
+    end
+
+    // write data
+    always @(posedge i_clk) begin
+        if(i_wb_we && i_wb_stb && i_wb_cyc) begin
+            if(i_wb_sel[0]) memory_regfile[i_wb_addr[$clog2(MEMORY_DEPTH)-1:2]][7:0] <= i_wb_data[7:0]; 
+            if(i_wb_sel[1]) memory_regfile[i_wb_addr[$clog2(MEMORY_DEPTH)-1:2]][15:8] <= i_wb_data[15:8];
+            if(i_wb_sel[2]) memory_regfile[i_wb_addr[$clog2(MEMORY_DEPTH)-1:2]][23:16] <= i_wb_data[23:16];
+            if(i_wb_sel[3]) memory_regfile[i_wb_addr[$clog2(MEMORY_DEPTH)-1:2]][31:24] <= i_wb_data[31:24];
+        end      
+        
+    end
+    
+endmodule
+
+
+module uart #( //UART (TX only)
+    parameter CLOCK_FREQ = 12_000_000,//Input clock frequency
+    parameter BAUD_RATE  = 9600, //UART Baud rate
+    parameter UART_TX_DATA = 8140, //memory-mapped address for TX (write to UART)
+    parameter UART_TX_BUSY = 8144, //memory-mapped address to check if TX is busy (has ongoing request)
+    parameter UART_RX_BUFFER_FULL = 8148, //memory-mapped address  to check if a read has completed
+    parameter UART_RX_DATA = 8152, //memory-mapped address for RX (read the data)
+    parameter DBIT = 8, //UART Data Bits
+    parameter SBIT = 1 //UART Stop Bits
+    )(
+        input wire clk,
+        input wire rst_n,
+        input wire i_wb_cyc,
+        input wire i_wb_stb,
+        input wire i_wb_we,
+        input wire[31:0] i_wb_addr,
+        input wire[DBIT - 1:0 ] i_wb_data,
+        input wire[3:0] i_wb_sel,
+        output reg o_wb_ack,
+        output wire o_wb_stall,
+        output reg[DBIT - 1:0] o_wb_data,
+        input wire uart_rx, //UART RX line
+        output wire uart_tx //UART TX line
+    );
+
+
+    localparam DVSR = CLOCK_FREQ/(16*BAUD_RATE);
+    localparam DVSR_WIDTH = $clog2(DVSR); //array size needed by DVSR
+    localparam SB_TICK = 16*SBIT;
+    
+     //FSM state declarations
+     localparam[1:0] idle=2'd0,
+                    start=2'd1,
+                    data=2'd2,
+                    stop=2'd3;
+                    
+    reg[DBIT - 1:0] uart_busy;    
+    reg tx_done_tick;          
+    reg[1:0] state_reg,state_nxt;
+    reg[3:0] s_reg,s_nxt; //count to 16 for every data bit
+    reg[2:0] n_reg,n_nxt; //count the number of data bits already transmitted
+    reg[DBIT - 1:0] din_reg,din_nxt; //stores the word to be transmitted
+    reg tx_reg,tx_nxt;
+    reg s_tick;
+    reg wr_uart;
+    reg[1:0] state_reg_rx,state_nxt_rx;
+    reg[3:0] s_reg_rx,s_nxt_rx; //check if number of ticks is 7(middle of start bit), or 15(middle of a data bit)
+    reg[2:0] n_reg_rx,n_nxt_rx; //checks how many data bits is already passed(value is 7 for last bit)
+    reg[7:0] b_reg,b_nxt; //stores 8-bit binary value of received data bits
+    reg[7:0] dout; //data read from UART
+    reg rx_done_tick; //goes high if a read is done
+    reg rx_buffer_full; //goes high if a read is done
+
+    assign o_wb_stall = 0;
+
+    //baud tick generator
+     reg[DVSR_WIDTH-1:0] counter=0;
+     always @(posedge clk,negedge rst_n) begin
+        if(!rst_n) counter<=0;
+        else begin
+            s_tick=0;
+            if(counter == DVSR-1) begin
+                s_tick=1;
+                counter<=0;
+            end
+            else begin
+                counter<=counter+1;
+            end
+            
+        end
+     end
+     //Read memory-mapped registers
+     always @(posedge clk, negedge rst_n) begin
+        if(!rst_n) begin
+            o_wb_data <= 0;
+            o_wb_ack <= 0;
+        end
+        else begin
+            if(i_wb_stb && i_wb_cyc && !i_wb_we && i_wb_addr == UART_TX_BUSY) begin //read request to UART_TX_BUSY_ADDR (check if there is an ongoing request)
+                o_wb_data <= uart_busy;
+            end
+            else if(i_wb_stb && i_wb_cyc && !i_wb_we && i_wb_addr == UART_RX_BUFFER_FULL) begin //read request to UART_RX_BUFFER_FULL (check if a read is completed)
+                o_wb_data <= rx_buffer_full;
+            end
+            else if(i_wb_stb && i_wb_cyc && !i_wb_we && i_wb_addr == UART_RX_DATA) begin //read request to UART_RX_DATA (read the data)
+                o_wb_data <= dout;
+            end
+            o_wb_ack <= i_wb_stb && i_wb_cyc;
+        end
+     end
+     
+     
+     /******************************** UART TX ****************************************/
+
+    
+     //FSM register operation
+     always @(posedge clk,negedge rst_n) begin
+        if(!rst_n) begin
+            state_reg<=idle;
+            s_reg<=0;
+            n_reg<=0;
+            din_reg<=0;
+            tx_reg<=0;
+        end
+        else begin
+            state_reg<=state_nxt;
+            s_reg<=s_nxt;
+            n_reg<=n_nxt;
+            din_reg<=din_nxt;
+            tx_reg<=tx_nxt;
+        end
+     end
+     
+     //FSM next-state logic
+     always @* begin
+        state_nxt=state_reg;
+        s_nxt=s_reg;
+        n_nxt=n_reg;
+        din_nxt=din_reg;
+        tx_nxt=tx_reg;
+        tx_done_tick=0; 
+        uart_busy= 1; //uart is busy unless its in idle state
+         case(state_reg)
+                idle: begin 
+                            tx_nxt=1;
+                            uart_busy = 0;
+                            //start transmit operation when there is a write request to UART_TX_DATA_ADDR and we are in idle
+                            if(i_wb_we && i_wb_stb && i_wb_cyc && i_wb_addr == UART_TX_DATA && !uart_busy) begin 
+                                din_nxt=i_wb_data;
+                                s_nxt=0;
+                                state_nxt=start;
+                                uart_busy = 1;
+                            end
+                        end
+              start: begin   //wait to finish the start bit
+                            tx_nxt=0;
+                            if(s_tick==1) begin
+                                if(s_reg==15) begin
+                                    s_nxt=0;
+                                    n_nxt=0;
+                                    state_nxt=data;
+                                end
+                                else s_nxt=s_reg+1;
+                            end
+                        end
+                data: begin  //wait for all data bits to be transmitted serially
+                            tx_nxt=din_reg[0];
+                            if(s_tick==1) begin
+                                if(s_reg==15) begin
+                                    din_nxt=din_reg>>1;
+                                    s_nxt=0;
+                                    if(n_reg==DBIT-1) state_nxt=stop;
+                                    else n_nxt=n_reg+1;
+                                end
+                                else s_nxt=s_reg+1;
+                            end
+                        end
+                stop: begin  //wait to finish the stop bit 
+                            tx_nxt=1;
+                            if(s_tick==1) begin
+                                if(s_reg==SB_TICK-1) begin
+                                    tx_done_tick=1;
+                                    state_nxt=idle;
+                                end
+                                else s_nxt=s_reg+1;
+                            end
+                        end
+            default: state_nxt=idle;
+         endcase
+     end
+     assign uart_tx=tx_reg;
+    /*********************************************************************************/
+    
+    /******************************** UART RX ****************************************/
+	 
+	 //FSM register operation
+	 always @(posedge clk,negedge rst_n) begin
+		if(!rst_n) begin
+			state_reg_rx<=idle;
+			s_reg_rx<=0;
+			n_reg_rx<=0;
+			b_reg<=0;
+			dout<=0;
+			rx_buffer_full<=0;
+		end
+		else begin
+			state_reg_rx<=state_nxt_rx;
+			s_reg_rx<=s_nxt_rx;
+			n_reg_rx<=n_nxt_rx;
+			b_reg<=b_nxt;	
+			if(rx_done_tick) begin
+			    dout <= b_reg; //memory-mapped register storing the completed read data	
+			    rx_buffer_full <= 1'b1; //memory-mapped register to check if a read is done
+			end
+			else if(i_wb_stb && i_wb_cyc && !i_wb_we && i_wb_addr == UART_RX_DATA) begin //read request to UART_RX_DATA (read the data)
+                rx_buffer_full <= 1'b0;
+            end
+		end
+	 end
+	 
+	 //FSM next-state logic
+	 always @* begin
+		state_nxt_rx=state_reg_rx;
+		s_nxt_rx=s_reg_rx;
+		n_nxt_rx=n_reg_rx;
+		b_nxt=b_reg;
+		rx_done_tick=0;
+		case(state_reg_rx)
+			 idle: if(uart_rx==0) begin //wait for start bit(rx of zero)
+						s_nxt_rx=0;
+						state_nxt_rx=start;
+					 end						
+			start: if(s_tick==1) begin //wait for middle of start bit
+						if(s_reg_rx==7) begin
+							s_nxt_rx=0;
+							n_nxt_rx=0;
+							state_nxt_rx=data;
+						end
+						else s_nxt_rx=s_reg_rx+1;
+					 end
+		    data: if(s_tick==1) begin //wait to pass all middle points of every data bits
+						if(s_reg_rx==15) begin
+							b_nxt={uart_rx,b_reg[7:1]};
+							s_nxt_rx=0;
+							if(n_reg_rx==DBIT-1) state_nxt_rx=stop;
+							else n_nxt_rx=n_reg_rx+1;
+						end
+						else s_nxt_rx=s_reg_rx+1;
+					 end
+			 stop: if(s_tick==1) begin  //wait to pass the required stop bits
+						if(s_reg_rx==SB_TICK-1) begin
+							rx_done_tick=1;
+							state_nxt_rx=idle;
+						end
+  						else s_nxt_rx=s_reg_rx+1;
+					 end	
+		 default: state_nxt_rx=idle;
+		endcase
+	 end
+	 /*********************************************************************************/
+	 
+endmodule
+
+
+
+module i2c //SCCB mode(no pullups resistors needed) [REPEATED START NOT SUPPORTED]
+    #(parameter main_clock=12_000_000, //frequency of clk
+                freq=100_000, //i2c freqeuncy
+                addr_bytes=2,//addr_bytes=number of bytes of an address
+                I2C_START=8100, //write-only memory-mapped address to start i2c (write the i2c slave address)
+                I2C_WRITE=8104, //write-only memory-mapped address for sending data to slave
+                I2C_READ=8108, //read-only memory-mapped address to read data received from slave (this will also continue reading from slave) 
+                I2C_BUSY=8112, //read-only memory-mapped address to check if i2c is busy (cannot accept request)
+                I2C_ACK=8116, //read-only memory-mapped address to check if last access has benn acknowledge by slave
+                I2C_READ_DATA_READY=8120, //read-only memory-mapped address to check if data to be received from slave is ready
+                I2C_STOP=8124 //write-only memory-mapped address to stop i2c (this is persistent thus must be manually turned off after stopping i2c)
+    ) 
+    (
+        input wire clk,
+        input wire rst_n,
+        // Wishbone Interface
+        input wire i_wb_cyc,
+        input wire i_wb_stb,
+        input wire i_wb_we,
+        input wire[31:0] i_wb_addr,
+        input wire[7:0] i_wb_data,
+        input wire[3:0] i_wb_sel,
+        output reg o_wb_ack,
+        output wire o_wb_stall,
+        output reg[7:0] o_wb_data,
+        inout wire scl, sda //i2c bidrectional clock and data line
+    ); 
+     
+
+    //memory-mapped registers for controlling i2c
+    wire[7:0] i2c_busy = {7'b0, !((state_q == idle) || (state_q == stop_or_write) || (state_q == stop_or_read))}; //check if busy (busy unless we are on these states)
+    wire[7:0] i2c_read_data_ready = {7'b0, (state_q == stop_or_read)}; //check if data is ready to be read (data is ready ONLY WHEN we are already waiting for another read request!)
+    reg[7:0] i2c_ack; //check last access request has been acknowledged by slave
+    reg[7:0] i2c_stop; //write non-zero data here to stop current read/write transaction
+
+    
+    wire start = i_wb_stb && i_wb_cyc;
+    wire[7:0] wr_data = i_wb_data;
+    reg ack;
+    reg rd_tick;
+
+     localparam full= (main_clock)/(2*freq),
+                    half= full/2,           
+                    counter_width=$clog2(full);
+         
+     //FSM state declarations
+    localparam[3:0] idle=0,
+                    starting=1,
+                    packet=2,
+                    ack_servant=3,
+                    read=4,
+                    ack_master=5,
+                    stop_1=6,
+                    stop_2=7,
+                    stop_or_read = 8,
+                    stop_or_write = 9;
+    reg[3:0] state_q=idle,state_d;
+     reg op_q=0,op_d;
+     reg[3:0] idx_q=0,idx_d;
+     reg[8:0] wr_data_q=0,wr_data_d;
+     reg[7:0] rd_data_q,rd_data_d;
+     reg scl_q=0,scl_d;
+     reg sda_q=0,sda_d;
+     reg[counter_width-1:0] counter_q=0,counter_d;
+     reg[1:0] addr_bytes_q=0,addr_bytes_d;
+     wire scl_lo,scl_hi;
+     wire sda_in, sda_out;
+    
+    assign o_wb_stall = 0;
+    //access memory-mapped register
+    always @(posedge clk, negedge rst_n) begin
+        if(!rst_n) begin
+            i2c_stop <= 0;
+            o_wb_ack <= 0;
+        end
+        else begin
+            if(i_wb_stb && i_wb_cyc && i_wb_we && i_wb_addr == I2C_STOP) i2c_stop <= i_wb_data; //write to i2c_stop to stop transaction
+            if(i_wb_stb && i_wb_cyc && !i_wb_we && i_wb_addr == I2C_ACK) o_wb_data <= i2c_ack; //read i2c_ack to know if last access request has been ack by slave
+            if(i_wb_stb && i_wb_cyc && !i_wb_we && i_wb_addr == I2C_READ_DATA_READY) o_wb_data <= i2c_read_data_ready;//read this to know if data is ready to be read
+            if(i_wb_stb && i_wb_cyc && !i_wb_we && i_wb_addr == I2C_BUSY) o_wb_data <= i2c_busy; //read this to know if i2c is still busy
+            if(i_wb_stb && i_wb_cyc && !i_wb_we && i_wb_addr == I2C_READ) o_wb_data <= rd_data_q; //read this to know what has been read from slave (make sure I2C_READ_DATA_READY is already high) 
+
+            o_wb_ack <= i_wb_stb && i_wb_cyc; 
+        end
+    end
+
+    //register operations
+     always@(posedge clk, negedge rst_n) begin
+        if(!rst_n) begin
+            state_q<=idle;
+            idx_q<=0;
+            wr_data_q<=0;
+            scl_q<=0;
+            sda_q<=0;
+            counter_q<=0;
+            rd_data_q<=0;
+            addr_bytes_q<=0;
+            i2c_ack <= 0;
+        end
+        else begin
+            state_q<=state_d;
+            op_q<=op_d;
+            idx_q<=idx_d;
+            wr_data_q<=wr_data_d;
+            scl_q<=scl_d;
+            sda_q<=sda_d;
+            if(i2c_busy[0]) counter_q<=counter_d; //freeze the scl (by freezing the counter) if we are on wait/idle state (not busy states)
+            rd_data_q<=rd_data_d;
+            addr_bytes_q<=addr_bytes_d;
+            i2c_ack <= {7'd0,ack};
+        end
+     end
+     
+     
+     //free-running clk, freq depends on parameter "freq"
+     always @* begin
+        counter_d=counter_q+1;
+        scl_d=scl_q;
+        if(state_q==idle || state_q==starting) scl_d=1'b1;
+        else if(counter_q==full[counter_width-1:0]) begin
+            counter_d=0;
+            scl_d=(scl_q==0)?1'b1:1'b0;
+        end
+     end
+     
+    //I2C_START 
+     //FSM next-state logic
+     always @* begin
+        state_d=state_q;
+        op_d=op_q;
+        idx_d=idx_q;
+        wr_data_d=wr_data_q;
+        rd_data_d=rd_data_q;
+        addr_bytes_d=addr_bytes_q;
+        sda_d=sda_q;
+        rd_tick=0;
+        ack=i2c_ack[0];
+        case(state_q)
+                    idle: begin //wait for user to start i2c by writing the slave address to I2C_START
+                                sda_d=1'b1;
+                                addr_bytes_d=addr_bytes; 
+                                if(start==1'b1 && i_wb_we && i_wb_addr == I2C_START) begin //wait for a request
+                                    wr_data_d={wr_data,1'b1}; //the last 1'b1 is for the ACK coming from the servant("1" means high impedance or "reading")
+                                    op_d= (wr_data[0])? 1:0; // if last bit(R/W bit) is one:read operation, else write operation
+                                    idx_d=8; //index to be used on transmitting the wr_data serially(MSB first)
+                                    state_d=starting;
+                                end
+                             end
+                             
+                starting: if(scl_hi) begin //start command, change sda to low while scl is high
+                                sda_d=0;
+                                state_d=packet;
+                             end
+                             
+                  packet: if(scl_lo) begin //transmit wr_data serially(MSB first)
+                                sda_d= (wr_data_q[idx_q]==0)? 0:1'b1;
+                                idx_d= idx_q-1;
+                                if(idx_q==0) begin
+                                    state_d=ack_servant;
+                                    idx_d=0;
+                                end
+                             end
+                             
+            ack_servant: if(scl_hi) begin //wait for ACK bit response(9th bit) from servant
+                                ack=!sda_in; 
+                                if(i2c_stop[0]) state_d=stop_1; //master can forcefully stops the transaction (i2c_stop is memory-mapped)
+                                else if(op_q/* && addr_bytes_q==0*/) begin //start reading after writing "addr_bytes" of packets for address
+                                    idx_d=7;
+                                    state_d=read;
+                                end
+                                else begin //write next packet
+                                    state_d = stop_or_write;
+                                    idx_d=8;
+                                end
+                             end
+                             
+               stop_or_write:  if(i2c_stop[0]) begin //wait until user explicitly say to either stop i2c or continue writing
+                                state_d = stop_1;
+                            end
+                            else if(start && i_wb_we && i_wb_addr == I2C_WRITE) begin//continue writing                   
+                                    state_d = packet;
+                                    wr_data_d={wr_data,1'b1}; 
+                                    addr_bytes_d=addr_bytes_q-1;
+                            end
+
+                     read: if(scl_hi) begin //read data from slave(MSB first)
+                                rd_data_d[idx_q[2:0]]=sda_in;
+                                idx_d=idx_q-1;
+                                if(idx_q==0) state_d=ack_master;
+                             end
+                             
+             ack_master: if(scl_lo) begin //master must ACK after receiving data from servant
+                                sda_d=1'b0; 
+                                if(sda_q==0) begin //one whole bit(two scl_lo) had passed
+                                    rd_tick=1;
+                                    idx_d=7;
+                                    if(i2c_stop[0]) state_d=stop_1; //after receiving data, master can opt to stop
+                                    else state_d=stop_or_read;
+                                end
+                             end
+            stop_or_read: if(i2c_stop[0]) begin //wait until user explicitly say to either stop i2c or continue reading
+                             state_d = stop_1;
+                         end
+                         else if(start && !i_wb_we && i_wb_addr == I2C_READ) begin //continue reading when current data is read
+                             state_d = read;
+                         end
+
+                  stop_1: if(scl_lo) begin 
+                                sda_d=1'b0;
+                                state_d=stop_2;
+                             end
+                  stop_2: if(scl_hi) begin
+                                sda_d=1'b1;
+                                state_d=idle;
+                             end
+                 default: state_d=idle;
+        endcase
+     end
+     
+     //i2c IO logic requires pull-ups (2 logic levels: 0 or Z)
+     //assign scl=scl_q? 1'bz:0; //bidiectional logic for pull-up scl
+     //assign sda=sda_q? 1'bz:0; //bidirectional logic for pull-up scl
+     //assign sda_in=sda;
+     
+     //We don't used pull-ups here so logic can be 0 or 1 (instead of high
+     //impedance). This is similar to SCCB protocol. 
+     wire is_reading;
+     assign is_reading = (state_q==read || state_q==ack_servant);
+     assign sda_out = sda_q;
+    
+    //Vivado, use IOBUF primitive
+    `ifndef ICARUS 
+     IOBUF sda_iobuf ( //Vivado IOBUF instantiationGPIO_COUNT-1
+            .IO(sda),
+            .I(sda_out),//write SDA when is_reading low
+            .T(is_reading), 
+            .O(sda_in) //read SDA when is_reading high
+        );
+     `endif
+     //Icarus simulator
+    `ifdef ICARUS
+        assign sda = sda_q;
+    `endif
+
+    assign scl = scl_q;
+    assign scl_hi= scl_q==1'b1 && counter_q==half[counter_width-1:0] /*&& scl==1'b1*/; //scl is on the middle of a high(1) bit
+    assign scl_lo= scl_q==1'b0 && counter_q==half[counter_width-1:0]; //scl is on the middle of a low(0) bit
+
+endmodule
+
+
+
+module rv32i_clint #( //Core Logic Interrupt
+    parameter CLK_FREQ_MHZ = 12, //input clock frequency in MHz
+    // A MTIMER device has two separate base addresses: one for the MTIME register and another for the MTIMECMP registers. 
+    parameter MTIME_BASE_ADDRESS = 8008,
+              MTIMECMP_BASE_ADDRESS = 8016,
+              MSIP_BASE_ADDRESS = 8024
+)(
+        input wire clk,
+        input wire rst_n,
+        input wire i_wb_cyc,
+        input wire i_wb_stb,
+        input wire i_wb_we,
+        input wire[31:0] i_wb_addr,
+        input wire[31:0] i_wb_data,
+        input wire[3:0] i_wb_sel,
+        output reg o_wb_ack,
+        output wire o_wb_stall,
+        output reg[31:0] o_wb_data,
+        // Interrupts
+        output wire o_timer_interrupt,
+        output wire o_software_interrupt
+);
+    // This is based from RISC-V Advanced Core Local Interruptor
+    // Specification: https://github.com/riscv/riscv-aclint/blob/main/riscv-aclint.adoc
+
+    // This RISC-V ACLINT specification defines a set of memory mapped devices which provide 
+    // inter-processor interrupts (IPI) and timer functionalities.
+    // The MTIMER device provides machine-level timer functionality for a set of HARTs on a RISC-V platform. 
+    // It has a single fixed-frequency monotonic time counter (MTIME) register and a time 
+    // compare register (MTIMECMP) for each HART connected to the MTIMER device.
+    reg[63:0] mtime = 0;
+    reg[63:0] mtimecmp = {64{1'b1}};   
+    reg msip = 0; //Inter-processor (or software) interrupts
+    assign o_wb_stall = 0;
+
+   //READ memory-mapped registers 
+    always @(posedge clk, negedge rst_n) begin
+        if(!rst_n) begin
+            o_wb_ack <= 0;
+            o_wb_data <= 0;
+        end
+        else begin
+            if(i_wb_stb && i_wb_cyc && !i_wb_we) begin //read the memory-mapped register
+                if(i_wb_addr == MTIME_BASE_ADDRESS) o_wb_data <= mtime[31:0]; //first half 
+                else if(i_wb_addr == MTIME_BASE_ADDRESS + 4) o_wb_data <= mtime[63:32]; //second half
+                if(i_wb_addr == MTIMECMP_BASE_ADDRESS) o_wb_data <= mtimecmp[31:0]; //first half
+                else if(i_wb_addr == MTIMECMP_BASE_ADDRESS + 4) o_wb_data <= mtimecmp[63:32]; //second half
+                if(i_wb_addr == MSIP_BASE_ADDRESS) o_wb_data <= {31'b0, msip}; //machine software interrupt
+            end
+            o_wb_ack <= i_wb_stb && i_wb_cyc; //wishbone protocol stb-ack mechanism
+        end
+    end
+
+
+    //WRITE to memory-mapped registers 
+    always @(posedge clk, negedge rst_n) begin
+        if(!rst_n) begin
+            mtime <= 64'd0;
+            mtimecmp <= {64{1'b1}}; //timer interrupt will be triggered unintentionally if reset at 0 (equal to mtime) 
+                                  //thus we set it at highest value (all 1s)
+            msip <= 0;
+        end
+        else begin
+            if(i_wb_stb && i_wb_cyc && i_wb_we) begin //write to the memory-mapped registers
+                if(i_wb_addr == MTIME_BASE_ADDRESS)  mtime[31:0] <= i_wb_data; //first half 
+                else if(i_wb_addr == MTIME_BASE_ADDRESS + 4) mtime[63:32] <= i_wb_data; //second half
+                if(i_wb_addr == MTIMECMP_BASE_ADDRESS) mtimecmp[31:0] <= i_wb_data; //first half
+                else if(i_wb_addr == MTIMECMP_BASE_ADDRESS + 4) mtimecmp[63:32] <= i_wb_data; //second half
+                if(i_wb_addr == MSIP_BASE_ADDRESS) msip <= i_wb_data[0]; //machine software interrupt
+            end
+            mtime <= mtime + 1'b1; //increment every clock tick (so timer freq is same as cpu clock freq)
+        end
+    end
+
+    //Volume 2 pg. 44: Platforms provide a 64-bit memory-mapped machine-mode timer compare register (mtimecmp). 
+    //A machine timer interrupt becomes pending whenever mtime contains a value greater than or equal to mtimecmp, 
+    //treating the values as unsigned integers. The interrupt remains posted until mtimecmp becomes greater than
+    //mtime (typically as a result of writing mtimecmp). 
+    assign o_timer_interrupt = (mtime >= mtimecmp);
+
+    //Each MSIP register is a 32-bit wide WARL register where the upper 31 bits are wired to zero.
+    //The least significant bit is reflected in MSIP of the mip CSR. A machine-level software interrupt 
+    //for a HART is pending or cleared by writing 1 or 0 respectively to the corresponding MSIP register.
+    assign o_software_interrupt = msip;
+
+endmodule
+
+
+
+module gpio #( //UART (TX only)
+    parameter GPIO_MODE = 32'hF0, //set if GPIO will be read(0) or write(1) 
+    parameter GPIO_READ = 32'hF4, //read from GPIO
+    parameter GPIO_WRITE = 32'hF8, //write to GPIO
+    parameter GPIO_COUNT = 12
+    )(
+        input wire clk,
+        input wire rst_n,
+        // Wishbone Interface
+        input wire i_wb_cyc,
+        input wire i_wb_stb,
+        input wire i_wb_we,
+        input wire[31:0] i_wb_addr,
+        input wire[GPIO_COUNT-1:0] i_wb_data,
+        input wire[3:0] i_wb_sel,
+        output reg o_wb_ack,
+        output wire o_wb_stall,
+        output reg[GPIO_COUNT-1:0] o_wb_data,
+        //GPIO
+        inout wire[11:0] gpio //gpio pins
+    );
+       
+        
+    reg[GPIO_COUNT-1:0] gpio_reg;
+    reg[GPIO_COUNT-1:0] gpio_write;
+    wire[GPIO_COUNT-1:0] gpio_read;
+    reg[GPIO_COUNT-1:0] gpio_mode;
+
+    assign o_wb_stall = 0;
+    always @(posedge clk,negedge rst_n) begin
+        if(!rst_n) begin
+            gpio_write <= 0;
+            gpio_mode <= 0;
+            gpio_reg <= 0;
+        end
+        else begin
+            if(i_wb_stb && i_wb_we && i_wb_addr == GPIO_MODE) gpio_mode <= i_wb_data; //set mode of the gpio (write(1) or low(0))
+            if(i_wb_stb && !i_wb_we && i_wb_addr == GPIO_MODE) o_wb_data <= gpio_mode; //read gpio mode
+            if(i_wb_stb && i_wb_we && i_wb_addr == GPIO_WRITE) gpio_write <= i_wb_data; //write to gpio
+            if(i_wb_stb && !i_wb_we && i_wb_addr == GPIO_WRITE) o_wb_data <= gpio_write; //read write value to gpio
+            if(i_wb_stb && !i_wb_we && i_wb_addr == GPIO_READ) o_wb_data <= gpio_read; //read from gpio
+            
+            o_wb_ack <= i_wb_stb; 
+        end
+    end
+    
+    `ifndef ICARUS 
+        genvar i;
+        generate
+            for(i = 0 ; i < GPIO_COUNT ; i = i+1) begin
+                 IOBUF gpio_iobuf ( //Vivado IOBUF instantiation
+                    .IO(gpio[i]),
+                    .I(gpio_write[i]),//write to GPIO when gpio_mode is high
+                    .T(!gpio_mode[i]), 
+                    .O(gpio_read[i]) //read from GPIO when gpio_mode is low
+                 );
+            end
+         endgenerate
+     `else
+         genvar i;
+         for(i = 0 ; i < GPIO_COUNT ; i = i+1) begin
+	        assign gpio[i] = gpio_mode[i]? gpio_write[i]:1'bz; //in icarus simulation we will only write to the pin
+	     end        
+     `endif
+     
+    
+        
+endmodule
+
+
+
+
+
+
+
+
+
+

AngeloJacobo_RISC-V/test/rv32i_soc_TB.v

@@ -0,0 +1,189 @@
+`timescale 1ns / 1ns
+`default_nettype none
+`define DISPLAY
+//`define HALT_ON_ILLEGAL_INSTRUCTION // stop core when instruction is illegal
+ //`define HALT_ON_EBREAK // halt core on ebreak
+// `define HALT_ON_ECALL // halt core on ecall
+`include "rv32i_header.vh"
+
+module rv32i_soc_TB;
+    parameter MEMORY="memory.mem";
+    parameter ZICSR_EXTENSION = 1;
+    /******************************* MODIFY ****************************************/
+    localparam MEMORY_DEPTH = 81920, //number of memory bytes
+               DATA_START_ADDR = 32'h1004; //starting address of data memory to be displayed
+    /*******************************************************************************/
+   
+    reg clk,rst_n;
+    reg temp;
+    integer i,j;          
+    
+    
+    rv32i_soc #(.PC_RESET(32'h00_00_00_00), .MEMORY_DEPTH(MEMORY_DEPTH), .CLK_FREQ_MHZ(100), .TRAP_ADDRESS(32'h00000004), .ZICSR_EXTENSION(ZICSR_EXTENSION)) uut (
+        .i_clk(clk),
+        .i_rst(!rst_n)
+        );
+    
+    always #5 clk=!clk; //100MHz clock
+    
+    initial begin //2nd reset to test resetting while core is executing instruction
+        #200;
+        rst_n = 0;
+        #500;
+        rst_n = 1;
+    end  
+        
+    /*********************** initialize instruction memory and data memory **************************/
+    initial begin 
+        #1;
+        $readmemh(MEMORY,uut.m1.memory_regfile); //write instruction and data to memory
+        //uut.m1.memory_regfile[{32'h0000_1000>>2}] = 32'h12345678; //initial data memory 
+    end
+    /***********************************************************************************************/
+    reg[1024:0] cause;
+    
+    initial begin
+        $dumpfile("wave.vcd");
+        $dumpvars(0,rv32i_soc_TB);
+        $dumpvars(0,uut.m0.m0.base_regfile[1],uut.m0.m0.base_regfile[2],uut.m0.m0.base_regfile[3],uut.m0.m0.base_regfile[4],uut.m0.m0.base_regfile[5]);
+        $dumpvars(0,uut.m0.m0.base_regfile[6],uut.m0.m0.base_regfile[7],uut.m0.m0.base_regfile[8],uut.m0.m0.base_regfile[9],uut.m0.m0.base_regfile[10]);
+        $dumpvars(0,uut.m0.m0.base_regfile[11],uut.m0.m0.base_regfile[12],uut.m0.m0.base_regfile[13],uut.m0.m0.base_regfile[14],uut.m0.m0.base_regfile[15]);
+        $dumpvars(0,uut.m0.m0.base_regfile[16],uut.m0.m0.base_regfile[17],uut.m0.m0.base_regfile[18],uut.m0.m0.base_regfile[19],uut.m0.m0.base_regfile[20]);
+        $dumpvars(0,uut.m0.m0.base_regfile[21],uut.m0.m0.base_regfile[22],uut.m0.m0.base_regfile[23],uut.m0.m0.base_regfile[24],uut.m0.m0.base_regfile[25]);
+        $dumpvars(0,uut.m0.m0.base_regfile[26],uut.m0.m0.base_regfile[27],uut.m0.m0.base_regfile[28],uut.m0.m0.base_regfile[29],uut.m0.m0.base_regfile[30]);
+        $dumpvars(0,uut.m0.m0.base_regfile[31]);
+		
+        rst_n = 1;
+        #50;
+        clk=0;
+        rst_n=0;
+        #50;
+        
+        rst_n=1; //release reset
+        
+        $display("\nStart executing instructions......\n");
+        $display("Monitor All Writes to Base Register and Data Memory");
+        
+        /**************************************************************************************************************************/
+		
+        while(  `ifdef HALT_ON_ILLEGAL_INSTRUCTION
+                    uut.iaddr < MEMORY_DEPTH-4 && !(uut.m0.zicsr.m6.i_is_inst_illegal && uut.m0.zicsr.m6.i_ce) //exception testing (halt core only when instruction is illegal)
+                `elsif HALT_ON_EBREAK
+                    !uut.m0.alu_exception[`EBREAK] //ebreak test (halt core on ebreak)
+                `elsif HALT_ON_ECALL
+                    !uut.m0.alu_exception[`ECALL] //ecall test (halt core on ecall)
+                `else
+                    !uut.m0.alu_exception[`ECALL] && !uut.m0.alu_exception[`EBREAK] //normal test (halt core on ebreak/ecall)
+                `endif
+             ) begin
+             
+            
+            @(negedge clk);
+            `ifdef DISPLAY
+            if(ZICSR_EXTENSION != 0) begin
+                if(!uut.m0.stall_memoryaccess && uut.m0.zicsr.m6.csr_enable) begin //csr is written
+                    $display("\nPC: %h    %h [%s]\n  [CSR] address:0x%0h   value:0x%h ",uut.m0.zicsr.m6.i_pc, uut.m1.memory_regfile[{uut.m0.zicsr.m6.i_pc}>>2],"SYSTEM",uut.m0.zicsr.m6.i_csr_index,uut.m0.zicsr.m6.csr_in); //display address of csr changed and its new value
+                end
+            end
+            
+            if(uut.m0.writeback_ce && !uut.m0.stall_writeback) begin
+                    if(uut.m0.memoryaccess_opcode[`RTYPE]) $display("\nPC: %h    %h [%s]", uut.m0.m5.i_pc, uut.m1.memory_regfile[{uut.m0.m5.i_pc}>>2],"RTYPE"); //Display PC and instruction 
+                    else if(uut.m0.memoryaccess_opcode[`ITYPE]) $display("\nPC: %h    %h [%s]", uut.m0.m5.i_pc, uut.m1.memory_regfile[{uut.m0.m5.i_pc}>>2],"ITYPE"); //Display PC and instruction      
+                    else if(uut.m0.memoryaccess_opcode[`LOAD]) $display("\nPC: %h    %h [%s]", uut.m0.m5.i_pc, uut.m1.memory_regfile[{uut.m0.m5.i_pc}>>2],"LOAD"); //Display PC and instruction 
+                    else if(uut.m0.memoryaccess_opcode[`STORE]) $display("\nPC: %h    %h [%s]", uut.m0.m5.i_pc, uut.m1.memory_regfile[{uut.m0.m5.i_pc}>>2],"STORE"); //Display PC and instruction 
+                    else if(uut.m0.memoryaccess_opcode[`BRANCH]) $display("\nPC: %h    %h [%s]", uut.m0.m5.i_pc, uut.m1.memory_regfile[{uut.m0.m5.i_pc}>>2],"BRANCH"); //Display PC and instruction 
+                    else if(uut.m0.memoryaccess_opcode[`JAL]) $display("\nPC: %h    %h [%s]", uut.m0.m5.i_pc, uut.m1.memory_regfile[{uut.m0.m5.i_pc}>>2],"JAL"); //Display PC and instruction 
+                    else if(uut.m0.memoryaccess_opcode[`JALR]) $display("\nPC: %h    %h [%s]", uut.m0.m5.i_pc, uut.m1.memory_regfile[{uut.m0.m5.i_pc}>>2],"JALR"); //Display PC and instruction 
+                    else if(uut.m0.memoryaccess_opcode[`LUI]) $display("\nPC: %h    %h [%s]", uut.m0.m5.i_pc, uut.m1.memory_regfile[{uut.m0.m5.i_pc}>>2],"LUI"); //Display PC and instruction 
+                    else if(uut.m0.memoryaccess_opcode[`AUIPC]) $display("\nPC: %h    %h [%s]", uut.m0.m5.i_pc, uut.m1.memory_regfile[{uut.m0.m5.i_pc}>>2],"AUIPC"); //Display PC and instruction 
+                    else if(uut.m0.memoryaccess_opcode[`SYSTEM]) $display("\nPC: %h    %h [%s]", uut.m0.m5.i_pc, uut.m1.memory_regfile[{uut.m0.m5.i_pc}>>2],"SYSTEM"); //Display PC and instruction 
+                    else if(uut.m0.memoryaccess_opcode[`FENCE]) $display("\nPC: %h    %h [%s]", uut.m0.m5.i_pc, uut.m1.memory_regfile[{uut.m0.m5.i_pc}>>2],"FENCE"); //Display PC and instruction 
+                    else $display("\nPC: %h    %h [%s]", uut.m0.m5.i_pc, uut.m1.memory_regfile[{uut.m0.m5.i_pc}>>2],"UNKNOWN INSTRUCTION"); //Display PC and instruction 
+                    
+                #1;
+                if(ZICSR_EXTENSION != 0) begin
+                     if(uut.m0.csr_go_to_trap) begin //exception or interrupt detected
+                        case({uut.m0.zicsr.m6.mcause_intbit,uut.m0.zicsr.m6.mcause_code})
+                            {1'b1,4'd3}: $display("  GO TO TRAP: %s","SOFTWARE INTERRUPT");
+                            {1'b1,4'd7}: $display("  GO TO TRAP: %s","TIMER INTERRUPT");
+                           {1'b1,4'd11}: $display("  GO TO TRAP: %s","EXTERNAL INTERRUPT"); 
+                            {1'b0,4'd0}: $display("  GO TO TRAP: %s","INSTRUCTION ADDRESS MISALIGNED");
+                            {1'b0,4'd2}: $display("  GO TO TRAP: %s","ILLEGAL INSTRUCTION");
+                            {1'b0,4'd3}: $display("  GO TO TRAP: %s","EBREAK"); 
+                            {1'b0,4'd4}: $display("  GO TO TRAP: %s","LOAD ADDRESS MISALIGNED"); 
+                            {1'b0,4'd6}: $display("  GO TO TRAP: %s","STORE ADDRESS MISALIGNED"); 
+                           {1'b0,4'd11}: $display("  GO TO TRAP: %s","ECALL");
+                                default: $display("  GO TO TRAP: %s","UNKNOWN TRAP");
+                        endcase
+                     end
+                 end
+                 if(uut.m1.i_wb_we) begin //data memory is written
+                    $display("  [MEMORY] address:0x%h   value:0x%h [MASK:%b]",uut.m1.i_wb_addr,uut.m1.i_wb_data,uut.m1.i_wb_sel); //display address of memory changed and its new value
+                end
+                
+                if(uut.m0.m5.o_wr_rd && uut.m0.m5.o_rd_addr!=0) begin //base register is written
+                    $display("  [BASEREG] address:0x%0d   value:0x%h",uut.m0.m5.o_rd_addr,uut.m0.m5.o_rd); //display address of base reg changed and its new value
+                end
+                
+                if(uut.m0.csr_return_from_trap) begin
+                    $display("  RETURN FROM TRAP"); //go back from trap via mret
+                end
+                
+            end
+            #1; 
+            `endif
+        
+        end
+
+        
+        @(negedge clk);
+        $display("\nAll instructions executed......");
+        
+        /************* Dump Base Register and Memory Values *******************/
+        $display("\nFinal Register State:");
+        
+        for(i=0; i<8; i=i+1) begin
+            for(j=0; j<4 ; j=j+1) begin
+                $write("0x%02d: 0x%h\t",4*i+j,uut.m0.m0.base_regfile[4*i+j]);
+            end
+            $write("\n");
+        end
+        $display("\n\nFinal Memory State:");
+        for(i=DATA_START_ADDR; i<(DATA_START_ADDR+10*4) ; i=i+4) begin
+            $display("0x%0h: 0x%h",i,uut.m1.memory_regfile[i>>2]);
+        end
+       
+        /***********************************************************************/
+        if(ZICSR_EXTENSION != 0) begin
+            if(uut.m0.m0.base_regfile[17] == 32'h5d) begin //Exit test using RISC-V International's riscv-tests pass/fail criteria
+                if(uut.m0.m0.base_regfile[10] == 0)
+                    $display("\nPASS: exit code = 0x%h \n[%0d instructions in %0d clk cycles]\n",uut.m0.m0.base_regfile[10]>>1,uut.m0.zicsr.m6.minstret,uut.m0.zicsr.m6.mcycle);
+                else begin
+                    $display("\nFAIL: exit code = 0x%h \n[%0d instructions in %0d clk cycles]\n",uut.m0.m0.base_regfile[10]>>1,uut.m0.zicsr.m6.minstret,uut.m0.zicsr.m6.mcycle);
+                end
+            end
+            else $display("\nUNKNOWN: basereg[17] = 0x%h (must be 0x0000005d)",uut.m0.m0.base_regfile[17]);
+        end
+        else begin
+            if(uut.m0.m0.base_regfile[17] == 32'h5d) begin //Exit test using RISC-V International's riscv-tests pass/fail criteria
+                if(uut.m0.m0.base_regfile[10] == 0)
+                    $display("\nPASS: exit code = 0x%h\n",uut.m0.m0.base_regfile[10]>>1);
+                else begin
+                    $display("\nFAIL: exit code = 0x%h\n",uut.m0.m0.base_regfile[10]>>1);
+                end
+            end
+            else $display("\nUNKNOWN: basereg[17] = 0x%h (must be 0x0000005d)",uut.m0.m0.base_regfile[17]);
+        end
+        $stop;
+        
+        /**************************************************************************************************************************/
+        
+    end
+	initial begin
+		#100_000; //simulation time limit
+		`ifdef LONGER_SIM_LIMIT
+		#25_000_000;
+		`endif
+		$stop;
+	end
+endmodule

AugustinJose1221_FPGA-Build/.github/FUNDING.yml

@@ -0,0 +1,6 @@
+# These are supported funding model platforms
+
+patreon: augustinjose
+ko_fi: augustinjose
+liberapay: augustinjose
+custom: ['www.buymeacoffee.com/augustinjose']

AugustinJose1221_FPGA-Build/README.md

@@ -0,0 +1,367 @@
+[![Contributors][contributors-shield]][contributors-url]
+[![Forks][forks-shield]][forks-url]
+[![Stargazers][stars-shield]][stars-url]
+[![Issues][issues-shield]][issues-url]
+[![MIT License][license-shield]][license-url]
+[![LinkedIn][linkedin-shield]][linkedin-url]
+
+
+
+<!-- PROJECT LOGO -->
+<br />
+<p align="center">
+  <a href="https://github.com/AugustinJose1221/FPGA-Build">
+    <img src="img/logo.png" alt="Logo" width="209" height="100">
+  </a>
+
+  <h3 align="center">FPGA Architecture for Real-time Video Stitching</h3>
+
+  <p align="center">
+    A novel architectural design for stitching video streams in real-time on an FPGA.
+    <br />
+    <a href="https://github.com/AugustinJose1221/FPGA-Build"><strong>Explore the docs »</strong></a>
+    <br />
+    <br />
+  </p>
+</p>
+
+
+
+<!-- TABLE OF CONTENTS -->
+<details open="open">
+  <summary>Table of Contents</summary>
+  <ol>
+    <li>
+      <a href="#about-the-project">About The Project</a>
+       <ul>
+        <li><a href="#algorithm">Algorithm</a></li>
+        <li><a href="#top-level-design">Top Level Design</a></li>
+      </ul>
+    </li>
+    <li>
+      <a href="#getting-started">Getting Started</a>
+      <ul>
+        <li><a href="#prerequisites">Prerequisites</a></li>
+        <li><a href="#installation">Installation</a></li>
+      </ul>
+    </li>
+    <li><a href="#usage">Usage</a></li>
+    <li><a href="#roadmap">Roadmap</a></li>
+    <li><a href="#contributing">Contributing</a></li>
+    <li><a href="#license">License</a></li>
+    <li><a href="#contact">Contact</a></li>
+  </ol>
+</details>
+
+
+
+<!-- ABOUT THE PROJECT -->
+## About The Project
+The designed architecture generates a video having a wider feild of view by stitching two video input based on features and keypoints. In simple terms, the output generated will be a panorama but with video. The architecture is optimized such that the output can be produced in real-time.
+
+### Algorithm
+The figure below illustrates the block diagram of the system depicting each step of the algorithm.
+ 
+![Block Diagram](https://github.com/AugustinJose1221/FPGA-Build/blob/beta/img/System%20Design.jpg)
+
+The system can be broadly divided into three subystems:
+* Preprocessing
+* SIFT Based Feature Extraction
+* Frame Stitching
+
+#### Preprocessing
+
+The  input  video  stream  for  the  system  is  in  8  bit  RGB format. The input 8 bit image is shown in figure. Each  individual  frame  of  the  video  stream  will  have three  channels  corresponding  to  red,  green  and  blue.  The colour  information  in  the  video  frames  does  not  enhance feature  detection.  Moreover,  computation  on  a  3  channel  8 bit image takes more time compared to a single channel 8 bit image. Therefore, the RGB video frame is converted to an 8 bit grayscale image. The generated grayscale images will have lesser noise, more details in the shadows and provides better computational efficiency, shown in figure. 
+
+| ![Input image](https://github.com/AugustinJose1221/FPGA-Build/blob/beta/img/Final1.jpg) | ![Grayscale image](https://github.com/AugustinJose1221/FPGA-Build/blob/beta/img/OUT2.jpg) |
+|:---:|:---:|
+| Input image | Grayscale image |
+
+#### SIFT Based Feature Extraction
+
+Feature extraction from the grayscale images is done using SIFT  algorithm.  SIFT  algorithm  can  be  separated  into  two main steps:
+* Keypoint Detection
+
+  SIFT operation begins with discrete convolution of the input image with different Gaussian filters. A Gaussian filter is a widely used image smoothing algorithm defined as:
+  <p align="center">
+    <img src="https://latex.codecogs.com/svg.latex?\Large&space;G(x,%20y,%20\sigma%20)%20=\frac{1}{2\pi%20\sigma%20^{2}}%20e^{-\frac{(x^{2}%20+%20y^{2})}{2\sigma%20^{2}}}">  
+  </p>
+  In the above equation,  G  is  the  Gaussian  kernel  at  the  point  (x,  y) and σ is  the  Gaussian  parameter. Using a larger  value  of σ produces a greater smoothing  effect  on  the  image.  Discrete  convolution of  the  image  with  Gaussian  kernel  generates  an  image  with lesser  noise  and  lesser  details.  In  SIFT,  discrete  convolution with Gaussian kernel is done with four different values of σ. Progressively  higher  values  of σ is  used  to  generate  a  set  of blurred images or an octave. 
+| ![Input image](https://github.com/AugustinJose1221/FPGA-Build/blob/beta/res/Final2.jpg) | ![Sigma1_6](https://github.com/AugustinJose1221/FPGA-Build/blob/beta/res/SIGMA_1_6.jpg) | ![Sigma2_26](https://github.com/AugustinJose1221/FPGA-Build/blob/beta/res/SIGMA_2_26.jpg) | ![Sigma3_2](https://github.com/AugustinJose1221/FPGA-Build/blob/beta/res/SIGMA_3_2.jpg) | ![Sigma4_5](https://github.com/AugustinJose1221/FPGA-Build/blob/beta/res/SIGMA_4_5.jpg) |
+|:---:|:---:|:---:|:---:|:---:|
+| Input image | Sigma = 1.6 | Sigma = 2.26 | Sigma = 3.2 | Sigma = 4.5 |
+
+  For a given value of σ, the sum of all coefficients in the convolution kernal should be equal to unity. Therefore, the size of the kernal increases as the value of σ increases. 
+
+  Once the octave is generated,  a  DoG  space  is  built  based on the four images in the octave. DoG stands for difference of Gaussian.  DoG is a very computationally efficient approximation of Laplacian of Gaussian (LoG). The DoG space is built by  computing  the  difference  between  two  adjacent  Gaussian scale images, pixel by pixel. DoG space of four images in the octave will have three levels. 
+| ![DoG1](https://github.com/AugustinJose1221/FPGA-Build/blob/beta/res/DIFF1.jpg) | ![DoG2](https://github.com/AugustinJose1221/FPGA-Build/blob/beta/res/DIFF2.jpg) | ![DoG3](https://github.com/AugustinJose1221/FPGA-Build/blob/beta/res/DIFF3.jpg) |
+|:---:|:---:|:---:|
+| Top level DoG | Middle level DoG | Bottom level DoG |
+
+  Keypoints  are  extracted  from  the  DoG  space  by  finding the  local  maxima  or  minima  values.  A  pixel  is  considered a keypoint if it is a local maxima or minima within a 26 pixel neighbourhood consisting of 9 pixels in the top level, 8 pixels in the middle level and 9 pixels in the bottom level.
+  <p align = "center">
+  <img src = "https://github.com/AugustinJose1221/FPGA-Build/blob/beta/res/KEYPOINTS4.jpg"> <br>
+  Keypoints
+  </p>
+  
+  | ![SIFT1](https://github.com/AugustinJose1221/FPGA-Build/blob/main/res/CV2SIFT.jpg) | ![SIFT2](https://github.com/AugustinJose1221/FPGA-Build/blob/main/img/LayerCheck0.jpg) | ![SIFT3](https://github.com/AugustinJose1221/FPGA-Build/blob/main/img/Keypointoverlay.png) |
+|:---:|:---:|:---:|
+| Keypoints using OpenCV sift function | Keypoints using SIFT implementation in Python | Keypoint generated by the FPGA design |
+  * Descriptor Generation
+
+  Keypoint descriptor is a unique identifier  for  a  particular  keypoint.  SIFT  uses  gradient  magnitude  and  direction  of  the  keypoint  as  the  basis  for  the descriptor.  Gradient  magnitude  and  direction  at  a  point  can be calculated by discrete convolution of the image with Sobel filters. 
+  <p align = "center">
+  <img src = "https://github.com/AugustinJose1221/FPGA-Build/blob/beta/res/SOBEL1.jpg"> <br>
+  Sobel convolution output
+  </p>
+  To generate the keypoint descriptor, gradient magnitude and direction  of  every  point  inside  a  16x16  window  around  each keypoint is calculated. The gradient magnitudes of the 16x16 window  is  convolved  with  a  Gaussian  kernel.  The  gradient magnitudes in every 4x4 cell is combined such that the 16x16 window is reduced to a 4x4 window and 16 gradient directions. Finally, these 16 gradient directions are transferred into eight bins.  Hence  a  128  element  vector  is  built  which  acts  as  the keypoint descriptor.
+  
+#### Frame Stitching
+
+Frame stitching is the process of combining two frames into a single image. Frame stitching is done in two steps:
+* Keypoint Matching
+
+  The  keypoint  descriptors  of  keypoints  in  the  video  frames  from  both  camera  sensors  are compared.  If  the  difference  between  the  keypoint  descriptors of  two  keypoints,  one  from  each  camera  sensor,  is  below  a error  threshold,  then  they  are considered  as  a  keypoint  pair.  The keypoint pair with the least difference between their keypoint descriptors is taken as the reference keypoints.  
+  | ![DoG1](https://github.com/AugustinJose1221/FPGA-Build/blob/beta/res/left.jpg) | ![DoG1](https://github.com/AugustinJose1221/FPGA-Build/blob/beta/res/right.jpg) |
+  |:---:|:---:|
+  | Input image from left camera | Input image from right camera |
+* Image Blending
+
+  A  weighed  average  method  is  used to  blend  the  two  frames  into  a  single  image. The  values  of  pixels  in  the  overlapped  region  is  equal to  the  weighted  average  values  of  pixels  of  both  the  frames. The  weights  are  chosen  based  on  the  distance  between  the overlapped  pixel  and  the  border  of  the  corresponding  frame.
+  <p align = "center">
+  <img src = "https://github.com/AugustinJose1221/FPGA-Build/blob/beta/res/STITCH1.jpg"> <br>
+  Stitched image
+  </p>
+### Top Level Design
+The block schematic of the architecture from top level is shown in figure below.
+<p align = "center">
+  <img src = "https://github.com/AugustinJose1221/FPGA-Build/blob/beta/img/Diagram0.png"> <br>
+  Block Schematic
+</p>
+  
+ The top level design is divided into five stages: 
+ * [Preprocessing stage](https://github.com/AugustinJose1221/FPGA-Build/blob/beta/design/README.md#preprocessing-stage)
+ * [Filter stage](https://github.com/AugustinJose1221/FPGA-Build/blob/beta/design/README.md#filter-stage)
+ * [Keypoint stage](https://github.com/AugustinJose1221/FPGA-Build/blob/beta/design/README.md#keypoint-stage)
+ * [Keypoint matching stage](https://github.com/AugustinJose1221/FPGA-Build/blob/beta/design/README.md#keypoint-matching-stage)
+ * [Frame blending stage](https://github.com/AugustinJose1221/FPGA-Build/blob/beta/design/README.md#frame-blending-stage)
+ 
+ 
+<!-- GETTING STARTED -->
+## Getting Started
+### Prerequisites
+The following packages needs to be installed on the Linux system before executing the source code.
+* Icarus Verilog
+  ```sh
+  apt-get install iverilog
+  ```
+  
+* Python
+  ```sh
+  apt-get install python3
+  ```
+
+* OpenCV
+  ```sh
+  pip3 install opencv-contrib-python
+  ```
+* numpy
+  ```sh
+  pip3 install numpy
+  ```
+  
+* PIL (Python Image Library)
+  ```sh
+  pip3 install pillow
+  ```
+
+### Installation
+
+1. Clone the repo
+   ```sh
+   git clone https://github.com/AugustinJose1221/FPGA-Build.git
+   ```
+2. Change working directory
+   ```sh
+   cd FPGA-Build/make
+   ```
+3. Compile the design
+   ```sh
+   make create
+   ```
+4. To view the RTL waveform
+   ```sh
+   make simulate
+   ```
+5. Generate output image
+   ```sh
+   python3 hexToImage.py
+   ```
+<!-- USAGE EXAMPLES -->
+## Usage
+### Project Tree
+ * [Templates](./Templates)
+   * [controller_tb.vcd](./Templates/controller_tb.vcd)
+   * [controller.v](./Templates/controller.v)
+   * [slave_1_tb.v](./Templates/slave_1_tb.v)
+   * [slave_1_tb.vcd](./Templates/slave_1_tb.vcd)
+   * [slave_1.v](./Templates/slave_1.v)
+   * [controller_tb.v](./Templates/controller_tb.v)
+   * [Makefile](./Templates/Makefile)
+   * [README.md](./Templates/README.md)
+   * [filter.v](./Templates/filter.v)
+   * [gaussian.v](./Templates/gaussian.v)
+ * [vcd](./vcd)
+   * [BRWM_tb.vcd](./vcd/BRWM_tb.vcd)
+   * [README.md](./vcd/README.md)
+   * [filter5x5.vcd](./vcd/filter5x5.vcd)
+   * [image.vcd](./vcd/image.vcd)
+   * [video_stitcher_tb.vcd](./vcd/video_stitcher_tb.vcd)
+   * [interface_tb.vcd](./vcd/interface_tb.vcd)
+ * [design](./design)
+   * [README.md](./design/README.md)
+   * [Controller.v](./design/Controller.v)
+   * [matcher.v](./design/matcher.v)
+   * [display.v](./design/display.v)
+   * [camera.v](./design/camera.v)
+   * [descriptor.v](./design/descriptor.v)
+   * [filter5x5.v](./design/filter5x5.v)
+   * [Grayscaler.v](./design/Grayscaler.v)
+   * [image.v](./design/image.v)
+   * [image2.v](./design/image2.v)
+   * [keypoints.v](./design/keypoints.v)
+   * [RWM_1.v](./design/RWM_1.v)
+   * [RWM_2.v](./design/RWM_2.v)
+   * [sobel_filter.v](./design/sobel_filter.v)
+   * [stitcher.v](./design/stitcher.v)
+ * [res](./res)
+   * [CV2SIFT.jpg](./res/CV2SIFT.jpg)
+   * [DIFF1.jpg](./res/DIFF1.jpg)
+   * [DIFF2.jpg](./res/DIFF2.jpg)
+   * [DIFF3.jpg](./res/DIFF3.jpg)
+   * [data1.txt](./res/data1.txt)
+   * [data2.txt](./res/data2.txt)
+   * [data.txt](./res/data.txt)
+   * [FilterOut3.jpg](./res/FilterOut3.jpg)
+   * [FILTEROUT3.jpg](./res/FILTEROUT3.jpg)
+   * [FilterOut5.jpg](./res/FilterOut5.jpg)
+   * [FILTEROUT5.jpg](./res/FILTEROUT5.jpg)
+   * [FILTEROUT6.jpg](./res/FILTEROUT6.jpg)
+   * [FilterOut7.jpg](./res/FilterOut7.jpg)
+   * [FILTEROUT7.jpg](./res/FILTEROUT7.jpg)
+   * [FilterOut9.jpg](./res/FilterOut9.jpg)
+   * [Final1.jpg](./res/Final1.jpg)
+   * [Final2.jpg](./res/Final2.jpg)
+   * [Final.jpg](./res/Final.jpg)
+   * [Grayscale-Out.jpg](./res/Grayscale-Out.jpg)
+   * [KEYPOINTS1.jpg](./res/KEYPOINTS1.jpg)
+   * [KEYPOINTS2.jpg](./res/KEYPOINTS2.jpg)
+   * [KEYPOINTS3.jpg](./res/KEYPOINTS3.jpg)
+   * [KEYPOINTS4.jpg](./res/KEYPOINTS4.jpg)
+   * [KEYPOINTS5.jpg](./res/KEYPOINTS5.jpg)
+   * [KEYPOINTS6.jpg](./res/KEYPOINTS6.jpg)
+   * [OUT1.jpg](./res/OUT1.jpg)
+   * [OUT2.jpg](./res/OUT2.jpg)
+   * [Out.jpg](./res/Out.jpg)
+   * [OUT.jpg](./res/OUT.jpg)
+   * [random.jpg](./res/random.jpg)
+   * [sift.py](./res/sift.py)
+   * [SIGMA_1_6.jpg](./res/SIGMA_1_6.jpg)
+   * [SIGMA_2_26.jpg](./res/SIGMA_2_26.jpg)
+   * [SIGMA_3_2.jpg](./res/SIGMA_3_2.jpg)
+   * [SIGMA_4_5.jpg](./res/SIGMA_4_5.jpg)
+   * [SUBKEYPOINTS1.jpg](./res/SUBKEYPOINTS1.jpg)
+   * [left.jpg](./res/left.jpg)
+   * [left.txt](./res/left.txt)
+   * [right.jpg](./res/right.jpg)
+   * [right.txt](./res/right.txt)
+   * [SOBEL1.jpg](./res/SOBEL1.jpg)
+   * [SOBEL.jpg](./res/SOBEL.jpg)
+   * [SOBEL_X.jpg](./res/SOBEL_X.jpg)
+   * [SOBEL_Y.jpg](./res/SOBEL_Y.jpg)
+   * [imageToHex.py](./res/imageToHex.py)
+   * [STITCH1.jpg](./res/STITCH1.jpg)
+   * [out.txt](./res/out.txt)
+   * [hexToImage.py](./res/hexToImage.py)
+ * [make](./make)
+   * [Makefile](./make/Makefile)
+ * [outfiles](./outfiles)
+   * [display](./outfiles/display)
+   * [FILTER](./outfiles/FILTER)
+   * [Gaussian](./outfiles/Gaussian)
+   * [image](./outfiles/image)
+   * [interface](./outfiles/interface)
+   * [output.bin](./outfiles/output.bin)
+ * [testbenches](./testbenches)
+   * [BRWM_tb.v](./testbenches/BRWM_tb.v)
+   * [README.md](./testbenches/README.md)
+   * [video_stitcher_tb.v](./testbenches/video_stitcher_tb.v)
+   * [interface_tb.v](./testbenches/interface_tb.v)
+   * [top_tb.v](./testbenches/top_tb.v)
+   * [display_tb.v](./testbenches/display_tb.v)
+   * [filter5x5_tb.v](./testbenches/filter5x5_tb.v)
+   * [image_tb.v](./testbenches/image_tb.v)
+   * [interface.v](./testbenches/interface.v)
+   * [top.v](./testbenches/top.v)
+ * [img](./img)
+   * [System Design.jpg](./img/System%20Design.jpg)
+   * [Final1.jpg](./img/Final1.jpg)
+   * [OUT2.jpg](./img/OUT2.jpg)
+ * [README.md](./README.md)
+ * [tree.sh](./tree.sh)
+
+
+<!-- ROADMAP -->
+## Roadmap
+
+See the [open issues](https://github.com/AugustinJose1221/FPGA-Build/issues) for a list of proposed features (and known issues).
+
+
+
+<!-- CONTRIBUTING -->
+## Contributing
+Any contributions you make are **greatly appreciated**.
+
+1. Fork the Project
+2. Create your Feature Branch (`git checkout -b feature/AmazingFeature`)
+3. Commit your Changes (`git commit -m 'Add some AmazingFeature'`)
+4. Push to the Branch (`git push origin feature/AmazingFeature`)
+5. Open a Pull Request
+
+
+
+<!-- LICENSE -->
+## License
+
+Distributed under the MIT License. See `LICENSE` for more information.
+
+
+
+<!-- CONTACT -->
+## Contact
+
+Twitter: [@augustinjose121](https://twitter.com/augustinjose121) <br>
+Gmail: [augustinjose1221@gmail..com](https://mail.google.com/mail/?view=cm&fs=1&to=augustinjose1221@gmail.com) <br>
+Discuss: [Github Discussions](https://github.com/AugustinJose1221/FPGA-Build/discussions) <br>
+
+
+
+
+
+
+
+<!-- MARKDOWN LINKS & IMAGES -->
+<!-- https://www.markdownguide.org/basic-syntax/#reference-style-links -->
+[contributors-shield]: https://img.shields.io/github/contributors/AugustinJose1221/FPGA-Build.svg?style=for-the-badge
+[contributors-url]: https://github.com/AugustinJose1221/FPGA-Build/graphs/contributors
+[forks-shield]: https://img.shields.io/github/forks/AugustinJose1221/FPGA-Build.svg?style=for-the-badge
+[forks-url]: https://github.com/AugustinJose1221/FPGA-Build/network/members
+[stars-shield]: https://img.shields.io/github/stars/AugustinJose1221/FPGA-Build.svg?style=for-the-badge
+[stars-url]: https://github.com/AugustinJose1221/FPGA-Build/stargazers
+[issues-shield]: https://img.shields.io/github/issues/AugustinJose1221/FPGA-Build.svg?style=for-the-badge
+[issues-url]: https://github.com/AugustinJose1221/FPGA-Build/issues
+[license-shield]: https://img.shields.io/github/license/AugustinJose1221/FPGA-Build.svg?style=for-the-badge
+[license-url]: https://github.com/AugustinJose1221/FPGA-Build/blob/master/LICENSE.txt
+[linkedin-shield]: https://img.shields.io/badge/-LinkedIn-black.svg?style=for-the-badge&logo=linkedin&colorB=555
+[linkedin-url]: https://linkedin.com/in/augustin-jose1221
+[product-screenshot]: images/screenshot.png

AugustinJose1221_FPGA-Build/Templates/README.md

@@ -0,0 +1 @@
+This folder contains a set of module templates that is used accross all the design files.

AugustinJose1221_FPGA-Build/Templates/controller.v

@@ -0,0 +1,47 @@
+
+module controller(
+input clk,                 //clock
+input rst_n,               //external reset
+input done_1,              //
+input done_2,
+input start,               //external start command
+output trigger_1,          //
+output trigger_2
+);
+
+parameter [1:0] IDLE = 2'b00, SLAVE_1 = 2'b01, SLAVE_2 = 2'b10;
+reg [1:0] CS, NS;
+
+always @(posedge clk or negedge rst_n)
+begin
+ if (~rst_n)
+  CS <= IDLE;
+ else CS <= NS;
+end
+
+always @(start, done_1, done_2)
+begin
+ case(CS)
+ IDLE: begin
+        if (start == 1'b1)
+         NS = SLAVE_1;
+        else NS = IDLE;
+       end
+ SLAVE_1: begin
+               if (done_1 == 1'b1)
+                NS = SLAVE_2;
+               else NS = SLAVE_1;
+              end
+ SLAVE_2: begin
+               if (done_2 == 1'b1)
+                NS = IDLE;
+               else NS = SLAVE_2;
+             end
+ default: NS = IDLE;
+ endcase
+end
+
+assign trigger_1 = (CS == SLAVE_1) ? 1'b1 : 1'b0; 
+assign trigger_2 = (CS == SLAVE_2) ? 1'b1 : 1'b0; 
+
+endmodule

AugustinJose1221_FPGA-Build/Templates/controller_tb.v

@@ -0,0 +1,34 @@
+
+
+module controller_tb();
+
+reg clk, rst_n, start;
+wire done_1, done_2, trigger_1, trigger_2;
+wire [3:0] slave_out_1, slave_out_2;
+
+slave_1 one (clk, rst_n, trigger_1, done_1, slave_out_1);
+slave_1 two (clk, rst_n, trigger_2, done_2, slave_out_2);
+controller control (clk, rst_n, done_1, done_2, start, trigger_1, trigger_2);
+
+initial
+begin
+ $dumpfile("controller_tb.vcd");
+ $dumpvars(0, controller_tb);
+
+ rst_n = 0;
+ start = 0;
+ #10;
+ rst_n = 1;
+ start = 1;
+ #200;
+ $finish;
+end
+
+always
+begin
+ clk = 1'b1;
+ #5;
+ clk = 1'b0;
+ #5;
+end
+endmodule

AugustinJose1221_FPGA-Build/Templates/filter.v

@@ -0,0 +1,148 @@
+/*
+Working of this module:
+It uses two reg arrays, one to store the image of resolution n x m pixels in one frame and the other to select the required pixels for the convolution.
+Here one pixel is considered to be of 1 byte wide. To do this, the entire operation is divided into 3 subtasks:-
+a) storage of the n x m pixels
+b) selecting the 9 bytes needed to perform the sobel filter convolution
+c) performing the 3 x 3 sobel convolution
+This cycle repeats for every subsequent frames. A FSM with 4 states is defined to sequence these subtasks correctly.
+*/
+`timescale 1ns/1ns
+
+module filter(
+input [7:0]         Din,
+input               data_valid, rst, clk,
+output              fill_now,                                                 //status signal to indicate whether the first reg matrix is empty or not
+output [15:0]       Dout
+);
+
+
+reg [7:0] storage[0:N*M-1];                                                   //reg array to store the image pixels in a frame of operation
+reg [7:0] image_kernal[0:24];                                                  //reg array to house the 9 bytes for the sobel convolution
+reg [15:0] result;
+reg [15:0] result0;
+reg [15:0] result1;
+reg [15:0] result2;
+reg [15:0] result3;
+reg [15:0] result4;
+reg [1:0] PS, NS;
+
+integer count, i, j, k;
+
+parameter IDLE = 2'b00, STORE = 2'b01, FIX = 2'b10, CONVOLUTE = 2'b11;
+parameter N = 450, M = 600;                                                       //resolution of the image
+
+
+//sequential logic
+always @(posedge clk or posedge rst)
+begin
+ if (~rst)
+  PS <= IDLE;    //every value is reset to its default value in IDLE
+ else PS <= NS;
+end
+
+always @(posedge clk)
+begin
+ if(data_valid)//PS == STORE)
+ begin
+  storage[i] <= Din;    //to store the incoming pixel byte into the next position in the storage array
+  i <= (i == N*M-1) ? 0 : i + 1;
+ end
+ else i <= 0;
+end
+
+//combinatorial logic
+always @(Din,data_valid,i,count,k,PS)
+begin
+ case (PS)
+ IDLE: begin
+        result = 16'h0000;
+        result0 = 16'h0000;
+        result1 = 16'h0000;
+        result2 = 16'h0000;
+        result3 = 16'h0000;
+        result4 = 16'h0000;
+        count = 0;  //to count the number of convolutions in a frame
+        j = 0;
+        k = 0;
+
+        if(data_valid)
+         NS = STORE;
+        else NS = IDLE;
+       end
+ STORE: begin
+         NS = (i == N*M-1) ? FIX : STORE;
+        end
+ FIX: begin
+       //to place the the required bytes in the kernal for convolution
+       image_kernal[0] = storage[j];
+       image_kernal[1] = storage[j+1];
+       image_kernal[2] = storage[j+2];
+       image_kernal[3] = storage[j+3];
+       image_kernal[4] = storage[j+4];
+
+       image_kernal[5] = storage[j+M];
+       image_kernal[6] = storage[j+M+1];
+       image_kernal[7] = storage[j+M+2];
+       image_kernal[8] = storage[j+M+3];
+       image_kernal[9] = storage[j+M+4];
+
+       image_kernal[10] = storage[j+(2*M)];
+       image_kernal[11] = storage[j+(2*M)+1];
+       image_kernal[12] = storage[j+(2*M)+2];
+       image_kernal[13] = storage[j+(2*M)+3];
+       image_kernal[14] = storage[j+(2*M)+4];
+
+       image_kernal[15] = storage[j+(3*M)];
+       image_kernal[16] = storage[j+(3*M)+1];
+       image_kernal[17] = storage[j+(3*M)+2];
+       image_kernal[18] = storage[j+(3*M)+3];
+       image_kernal[19] = storage[j+(3*M)+4];
+
+       image_kernal[20] = storage[j+(4*M)];
+       image_kernal[21] = storage[j+(4*M)+1];
+       image_kernal[22] = storage[j+(4*M)+2];
+       image_kernal[23] = storage[j+(4*M)+3];
+       image_kernal[23] = storage[j+(4*M)+4];
+
+       NS = CONVOLUTE;
+      end
+ CONVOLUTE: begin
+             // sigma = 3
+             result0 = (0.011339 * image_kernal[0]) + (0.013395 * image_kernal[1]) + (0.01416 * image_kernal[2]) + (0.013395 * image_kernal[3]) + (0.011339 * image_kernal[4]) + (0.013395 * image_kernal[5]) + (0.015824 * image_kernal[6]) + (0.016728 * image_kernal[7]) + (0.015824 * image_kernal[8]) + (0.013395 * image_kernal[9]) + (0.01416 * image_kernal[10]) + (0.016728 * image_kernal[11]) + (0.017684 * image_kernal[12]) + (0.016728 * image_kernal[13]) + (0.01416 * image_kernal[14]) + (0.013395 * image_kernal[15]) + (0.015824 * image_kernal[16]) + (0.016728 * image_kernal[17]) + (0.015824 * image_kernal[18]) + (0.013395 * image_kernal[19]) + (0.011339 * image_kernal[20]) + (0.013395 * image_kernal[21]) + (0.01416 * image_kernal[22]) + (0.013395 * image_kernal[23]) + (0.011339 * image_kernal[24]);
+             // sigma = 5
+             result1 = (0.005425 * image_kernal[0]) + (0.00576 * image_kernal[1]) + (0.005877 * image_kernal[2]) + (0.00576 * image_kernal[3]) + (0.005425 * image_kernal[4]) + (0.00576 * image_kernal[5]) + (0.006117 * image_kernal[6]) + (0.00624 * image_kernal[7]) + (0.006117 * image_kernal[8]) + (0.00576 * image_kernal[9]) + (0.005877 * image_kernal[10]) + (0.00624 * image_kernal[11]) + (0.006366 * image_kernal[12]) + (0.00624 * image_kernal[13]) + (0.005877 * image_kernal[14]) + (0.00576 * image_kernal[15]) + (0.006117 * image_kernal[16]) + (0.00624 * image_kernal[17]) + (0.006117 * image_kernal[18]) + (0.00576 * image_kernal[19]) + (0.005425 * image_kernal[20]) + (0.00576 * image_kernal[21]) + (0.005877 * image_kernal[22]) + (0.00576 * image_kernal[23]) + (0.005425 * image_kernal[24]);
+             // sigma = 7
+             result2 = (0.002993 * image_kernal[0]) + (0.003086 * image_kernal[1]) + (0.003118 * image_kernal[2]) + (0.003086 * image_kernal[3]) + (0.002993 * image_kernal[4]) + (0.003086 * image_kernal[5]) + (0.003182 * image_kernal[6]) + (0.003215 * image_kernal[7]) + (0.003182 * image_kernal[8]) + (0.003086 * image_kernal[9]) + (0.003118 * image_kernal[10]) + (0.003215 * image_kernal[11]) + (0.003248 * image_kernal[12]) + (0.003215 * image_kernal[13]) + (0.003118 * image_kernal[14]) + (0.003086 * image_kernal[15]) + (0.003182 * image_kernal[16]) + (0.003215 * image_kernal[17]) + (0.003182 * image_kernal[18]) + (0.003086 * image_kernal[19]) + (0.002993 * image_kernal[20]) + (0.003086 * image_kernal[21]) + (0.003118 * image_kernal[22]) + (0.003086 * image_kernal[23]) + (0.002993 * image_kernal[24]);
+             // sigma = 9
+             result3 =  (0.00187 * image_kernal[0]) + (0.001905 * image_kernal[1]) + (0.001917 * image_kernal[2]) + (0.001905 * image_kernal[3]) + (0.00187 * image_kernal[4]) + (0.001905 * image_kernal[5]) + (0.001941 * image_kernal[6]) + (0.001953 * image_kernal[7]) + (0.001941 * image_kernal[8]) + (0.001905 * image_kernal[9]) + (0.001917 * image_kernal[10]) + (0.001953 * image_kernal[11]) + (0.001965 * image_kernal[12]) + (0.001953 * image_kernal[13]) + (0.001917 * image_kernal[14]) + (0.001905 * image_kernal[15]) + (0.001941 * image_kernal[16]) + (0.001953 * image_kernal[17]) + (0.001941 * image_kernal[18]) + (0.001905 * image_kernal[19]) + (0.00187 * image_kernal[20]) + (0.001905 * image_kernal[21]) + (0.001917 * image_kernal[22]) + (0.001905 * image_kernal[23]) + (0.00187 * image_kernal[24]);
+
+             result4 = (0.002915 * image_kernal[0]) + (0.013064 * image_kernal[1]) + (0.021539 * image_kernal[2]) + (0.013064 * image_kernal[3]) + (0.002915 * image_kernal[4]) + (0.013064 * image_kernal[5]) + (0.05855 * image_kernal[6]) + (0.096532 * image_kernal[7]) + (0.05855 * image_kernal[8]) + (0.013064 * image_kernal[9]) + (0.021539 * image_kernal[10]) + (0.096532 * image_kernal[11]) + (0.159155 * image_kernal[12]) + (0.096532 * image_kernal[13]) + (0.021539 * image_kernal[14]) + (0.013064 * image_kernal[15]) + (0.05855 * image_kernal[16]) + (0.096532 * image_kernal[17]) + (0.05855 * image_kernal[18]) + (0.013064 * image_kernal[19]) + (0.002915 * image_kernal[20]) + (0.013064 * image_kernal[21]) + (0.021539 * image_kernal[22]) + (0.013064 * image_kernal[23]) + (0.002915 * image_kernal[24]);
+
+             result = image_kernal[0];
+             count = count + 1;
+             if(count != (N-4)*(M-4))
+             begin
+              if(k != (M-4))
+              begin
+               j = j + 1;
+               k = k + 1;
+               NS = FIX;
+              end
+              else
+              begin
+               j = j + 5;
+               k = 0;
+               NS = FIX;
+              end
+             end
+             else NS = IDLE;
+            end
+
+ endcase
+end
+
+assign fill_now = (PS==CONVOLUTE) ? 1'b1 : 1'b0; //storage is full when PS is in FIX and CONVOLUTE states.
+assign Dout = (PS==CONVOLUTE) ? result : 16'hzzzz;  //output data is available when PS is in CONVOLUTE state.
+
+endmodule

AugustinJose1221_FPGA-Build/Templates/gaussian.v

@@ -0,0 +1,12 @@
+module gaussian();
+reg [7:0] s;
+reg [7:0] size;
+reg [7:0] G;
+
+initial
+begin
+ size = 4*s + 1;
+ G = 1/(2*3.1415);
+ $display("%f", G);
+end
+endmodule

AugustinJose1221_FPGA-Build/Templates/slave_1.v

@@ -0,0 +1,18 @@
+
+module slave_1(
+ input              clk,
+ input              rst_n,
+ input              slave_en,
+ output             slave_done,
+ output reg [3:0]   slave_out
+);
+always @(posedge clk or negedge rst_n)
+begin
+ if (~rst_n)
+  slave_out <= 0;
+ else if (slave_en)
+  slave_out <= slave_out + 1;
+ else slave_out <= 0;
+end
+assign slave_done = (slave_out == 4) ? 1'b1 : 1'b0;
+endmodule

AugustinJose1221_FPGA-Build/Templates/slave_1_tb.v

@@ -0,0 +1,34 @@
+
+
+module slave_1_tb();
+
+reg clk, rst_n, slave_en;
+wire slave_done;
+wire [3:0] slave_out;
+
+slave_1 obey (clk, rst_n, slave_en, slave_done, slave_out);
+
+initial 
+begin
+ $dumpfile("slave_1_tb.vcd");
+ $dumpvars(0, slave_1_tb);
+
+ rst_n = 0;
+ slave_en = 0;
+ #10;
+ rst_n = 1;
+ slave_en = 1;
+ #40;
+ slave_en = 0;
+ #200;
+ $finish;
+end
+
+always
+begin
+ clk = 1'b1;
+ #5;
+ clk = 1'b0;
+ #5;
+end
+endmodule

AugustinJose1221_FPGA-Build/design/Controller.v

@@ -0,0 +1,69 @@
+
+//`timescale 1ns/1ns
+
+module Controller(
+input             clk,                      //clock
+input             rst_n,                    //external asynchronous active low reset
+input             RWM_1_done,               //status signal from the RWM_1 module
+input             RWM_2_done,               //status signal from the RWM_2 module
+input             GS_done,                  //status signal from the Grayscaler module
+input             start,                    //external start command from user
+output            RWM_1_enable,             //status signal to the RWM_1 module
+output            rw_1,                     //status signal to the RWM_1 module
+output            RWM_2_enable,             //status signal to the RWM_2 module
+output            rw_2,                     //status signal to the RWM_2 module
+output            camera_enable,            //status signal to the camera
+output            GS_enable                 //status signal to the Grayscaler module
+);
+
+parameter [2:0] IDLE = 3'b000, CAMERA_READ = 3'b001, GRAYSCALE = 3'b010, FILTER = 3'b011;
+reg [2:0] CS, NS;
+
+//Sequential logic
+always @(posedge clk or negedge rst_n)
+begin
+ if (~rst_n)
+  CS <= IDLE;
+ else CS <= NS;
+end
+
+//Combinatorial logic
+always @(start, GS_done, RWM_1_done, RWM_2_done)
+begin
+ case (CS)
+ IDLE:
+ begin
+  if (start == 1'b1)
+   NS = CAMERA_READ;
+  else NS = IDLE;
+ end
+ CAMERA_READ:
+ begin
+  if (RWM_1_done == 1'b1)
+   NS = GRAYSCALE;
+  else NS = CAMERA_READ;
+ end
+ GRAYSCALE:
+ begin
+  if (RWM_1_done == 1'b1)
+   NS = FILTER;
+  else NS = GRAYSCALE;
+ end
+ FILTER:
+ begin
+  if ((GS_done == 1'b1) || RWM_2_done == 1'b0)
+   NS = FILTER;
+  else NS = IDLE;
+ end
+ default: NS = IDLE;
+ endcase
+end
+
+assign camera_enable = (CS == CAMERA_READ) ? 1'b1 : 1'b0;
+assign RWM_1_enable = ((CS == CAMERA_READ) || (CS == GRAYSCALE)) ? 1'b1 : 1'b0;
+assign rw_1 = (CS == CAMERA_READ) ? 1'b1 :((CS == GRAYSCALE) ? 1'b0 : 1'bz);
+assign RWM_2_enable = ((CS == GRAYSCALE) || (CS == FILTER)) ? 1'b1 : 1'b0;
+assign rw_2 = (CS == GRAYSCALE) ? 1'b1 : ((CS == FILTER) ? 1'b0 : 1'bz);
+assign GS_enable = (CS == GRAYSCALE) ? 1'b1 : 1'b0;
+
+endmodule

AugustinJose1221_FPGA-Build/design/Grayscaler.v

@@ -0,0 +1,93 @@
+/*
+MODULE OVERVIEW:
+Function of this module:
+To calculate the grayscale values of each colour pixel(R,G,B respectively) stored in first memory module.
+It communicates with the controller and the memory modules.
+
+Working:
+The module makes use of a FSM with 3 states:-
+1)IDLE: Whenever the module is not in use, it is in this state. It waits for further commands from the controller.
+
+2)FILL: Here every three pixel bytes at the input data bus is loaded into the internal registers for grayscale calculation.
+        First byte is stored in 'red', second in 'green' and third in 'blue'.
+        After the third byte is recieved, a status signal is sent to the first memory module to pause its operation.
+
+3)CALCULATE: To find the grayscale value of the three bytes recieved.
+             After placing the computed value in the output bus, a status signal is sent to the second memory module to store this value.
+*/
+
+
+module Grayscaler(
+ input          clk,                     //clock
+ input          rst_n,                   //external asynchronous active low reset
+ input          GS_enable,               //to enable or disable this module. Driven by controller
+ input          RWM_valid,               //an active high signal indicating the presence of desired data at the output data bus
+ input [7:0]    Din,                     //input data bus. Connected to RWM_1 module
+ output [7:0]   Dout,                    //output data bus. Connected to RWM_2 module
+ output         GS_valid,                //an active high signal that tells the RWM_2 module that desired data bytes is present in the output data bus
+ output         pause,                   //an active high signal that tells the RWM_1 module to pause whatever operation it is doing.
+ output reg     GS_done                  //after the completion of an operation done is set to 1. It is a status signal to drive the controller
+);
+
+parameter N = 450, M = 450;
+
+reg [7:0] red, green, blue, result;
+integer c, d, k=0;
+
+parameter IDLE = 2'b00, FILL = 2'b01, CALCULATE = 2'b10;
+reg [1:0] CS, NS;
+
+always @(posedge clk or negedge rst_n)
+begin
+if(~rst_n)
+  CS <= IDLE;
+ else
+ begin
+  CS <= NS;
+  k = (RWM_valid) ?  k + 1 : 0;
+  d = (k == 2) ? d + 1 : d;
+ end
+end
+
+
+always @(*)
+begin
+ case (CS)
+ IDLE:
+ begin
+  d = 0;
+  c = 0;
+  red = 8'h00;
+  green = 8'h00;
+  blue = 8'h00;
+  GS_done = 1'b0;
+  if(GS_enable)
+  begin
+   NS = FILL;
+  end
+  else NS = IDLE;
+ end
+ FILL:
+ begin
+  GS_done = 1'b0;
+  c = (c != 3) ? c + 1 : 1;
+  red = (k == 0) ? Din : red;
+  green = (k == 1) ? Din : green;
+  blue = (k == 2) ? Din : blue;
+  NS = (k == 2) ? CALCULATE : FILL;
+ end
+ CALCULATE:
+ begin
+  result = (red>>2) + (red>>5) + (green>>1) + (green>>4) + (blue>>4) + (blue>>5);
+  NS = (d == N*M) ? IDLE : FILL;
+  GS_done = (d == N*M) ? 1'b1 : 1'b0;
+ end
+ default: NS = IDLE;
+ endcase
+end
+
+assign pause = ((CS == FILL) && (c == 3) && (d != N*M)) ? 1'b1 : 1'b0;
+assign Dout = (CS == CALCULATE) ? result : 8'hzz;
+assign GS_valid = ((CS == FILL) && (k == 2)) ? 1'b1 : 1'b0;
+
+endmodule

AugustinJose1221_FPGA-Build/design/README.md

@@ -0,0 +1,45 @@
+# Top Level Design
+
+ The top level design is divided into five stages: 
+ * Preprocessing stage
+ * Filter stage
+ * Keypoint stage
+ * Keypoint matching stage
+ * Frame blending stage
+ 
+ ### Preprocessing Stage
+ A detailed veiw of this stage of operation is shown in figure:
+ <p align = "center">
+  <img src = "https://github.com/AugustinJose1221/FPGA-Build/blob/beta/img/Diagram1.png"> <br>
+  Preprocessing stage
+</p>
+
+To emulate the working of camera sensors, [image.v](https://github.com/AugustinJose1221/FPGA-Build/blob/beta/design/image.v) and [image2.v](https://github.com/AugustinJose1221/FPGA-Build/blob/beta/design/image.v) are used, which inputs images corresponding to left and right camera sensor respectively. [RWM_1.v](https://github.com/AugustinJose1221/FPGA-Build/blob/beta/design/RWM_1.v) is a read-write memory that stores the 8 bit RGB image. When it is WRITE mode, the RGB image pixel data is written into the memory. After all the pixel values are stored, the memory is put in READ mode. In READ mode, each pixel value is read sequentially from the memory. 
+
+### Filter Stage
+ A detailed veiw of this stage of operation is shown in figure:
+ <p align = "center">
+  <img src = "https://github.com/AugustinJose1221/FPGA-Build/blob/beta/img/Diagram3.png"> <br>
+  Filter stage
+</p>
+
+### Keypoint Stage
+ A detailed veiw of this stage of operation is shown in figure:
+ <p align = "center">
+  <img src = "https://github.com/AugustinJose1221/FPGA-Build/blob/beta/img/Diagram4.png"> <br>
+  Keypoint stage
+</p>
+
+### Keypoint Matching Stage
+ A detailed veiw of this stage of operation is shown in figure:
+ <p align = "center">
+  <img src = "https://github.com/AugustinJose1221/FPGA-Build/blob/beta/img/Diagram5.png"> <br>
+  Keypoint matching stage
+</p>
+
+### Frame Blending Stage
+ A detailed veiw of this stage of operation is shown in figure:
+ <p align = "center">
+  <img src = "https://github.com/AugustinJose1221/FPGA-Build/blob/beta/img/Diagram6.png"> <br>
+  Frame blending stage
+</p>

AugustinJose1221_FPGA-Build/design/RWM_1.v

@@ -0,0 +1,127 @@
+/*
+MODULE OVERVIEW:
+Purpose of this module:
+To store the RGB pixel bytes coming from the camera. It works with the camera, controller and the grayscaling module.
+
+Working:
+The 5 states of the FSM used in this module are described below:-
+1)INACTIVE: Whenever the module is not in use, it is in this state. It waits for further commands from the controller.
+
+2)WRITE: Writes the contents of the input data bus to the internal register array. After completion, it goes back to INACTIVE.
+
+3)READ: Writes the contents of the internal data bus to the output data bus. After completion, it goes back to INACTIVE.
+
+4)WAIT: The grayscaling module can interrupt this module during the READ operation by asserting the 'pause' signal.
+        If this happens, the module goes to this state, where it preserves the location address.
+        It then waits for the 'pause' signal to be disabled so that it can go back to READ state.
+
+5)CLEANUP: Clears the contents of the internal register array to 8'h00 upon receiving the 'clear' command from the controller.
+           After completion, it goes back to INACTIVE.
+*/
+
+
+module RWM_1(
+input           clk,                      // clock
+input           rst_n,                    // external asynchronous active low reset
+input           RWM_enable,               // to enable or disable the R/W memory. Driven by controller
+input           rw,                       // rw = 0: read, rw = 1: write. Driven by controller
+input           clear,                    // an active high signal to clear all the contents of the R/W memory. Driven by controller
+input           pause,                    // an active high signal that tells the module to pause whatever operation it is doing. Driven by Grayscaler
+input [7:0]     data_in,                  // input data bus. Comes from the camera
+output [7:0]    data_out,                 // ouput data bus. Connected to Grayscaling module
+output          RWM_valid,                // an active high signal indicating the presence of desired data at the output data bus
+output reg      RWM_done                  // after the completion of an operation done is set to 1. It is a status signal to drive the controller
+);
+
+parameter N = 450, M = 450;
+
+reg [7:0] DATA[0:(3*N*M - 1)];            // RWM register array
+
+reg [2:0] CS, NS;                         // RWM state variables
+
+//RWM states
+parameter INACTIVE = 3'b000, READ = 3'b001, WRITE = 3'b010, WAIT = 3'b011, CLEANUP = 3'b100;
+
+integer i, j, k = 0;                      // Loop variable for addressing the RWM register array
+
+// Sequential Logic
+always @(posedge clk or negedge rst_n)
+begin
+  if (~rst_n)
+    CS <= INACTIVE;
+  else
+  begin
+   CS <= NS;
+   k = (CS == READ) ? k + 1 : 0;
+  end
+end
+
+always @(posedge clk)
+begin
+ case (CS)
+ INACTIVE: i <= 0;                        // Keep the memory address pointer at 0
+ WRITE:
+ begin
+  DATA[i] <= data_in;                     // Writing into RWM
+  i <= (i == 3*N*M - 1) ? 0 : i + 1;
+ end
+ READ:
+ begin                                    // Reading from RWM
+  i <= (i == 3*N*M - 1) ? 0 : i + 1;
+ end
+ WAIT: i <= i;                            // Preserve the address location
+ CLEANUP:
+ begin
+  for(j = 0; j < N*M*3; j = j+1)
+  begin
+   DATA[j] <= 8'h00;                      // Clearing RWM registers
+  end
+ end
+ endcase
+end
+
+// Combinatorial Logic
+always @(RWM_enable, rw, i, pause)
+begin
+  case (CS)
+  INACTIVE:
+  begin
+   RWM_done = 1'b0;
+   if (RWM_enable == 1'b0)
+    NS = INACTIVE;
+   else if (clear == 1'b1)
+    NS = CLEANUP;
+   else NS = (rw == 1) ? WRITE : READ;
+  end
+  WRITE:
+  begin
+   NS = (i == 3*N*M - 1) ? INACTIVE : WRITE;
+   RWM_done = (i == 3*N*M - 1) ? 1'b1 : 1'b0;
+  end
+  READ:
+  begin
+   if (k == 2 && i != 3*N*M - 1)
+    NS = WAIT;
+   else NS = (i == 3*N*M - 1) ? INACTIVE : READ;
+   RWM_done = (i == 3*N*M - 1) ? 1'b1 : 1'b0;
+  end
+  WAIT:
+  begin
+   RWM_done = 1'b0;
+   if (k == 3)
+    NS = READ;
+   else NS = WAIT;
+  end
+  CLEANUP:
+  begin
+   NS = (j == 3*N*M - 1) ? INACTIVE : CLEANUP;
+   RWM_done = (j == 3*N*M - 1) ? 1'b1 : 1'b0;
+  end
+  default: NS = INACTIVE;
+  endcase
+end
+
+assign data_out = (CS == READ) ? DATA[i] : 8'hzz;
+assign RWM_valid = (CS == READ) ? 1'b1 : 1'b0;
+
+endmodule