Add Batch 4 with 10 repos

.gitattributes

@@ -83,3 +83,9 @@ The-OpenROAD-Project_OpenROAD-flow-scripts/flow/designs/src/coyote/coyote.sv2v.v
 OpenTimer_OpenTimer/benchmark/vga_lcd/vga_lcd.v filter=lfs diff=lfs merge=lfs -text
 hguq_HG-PIPE/SPINAL/BlockSequence_bb.v filter=lfs diff=lfs merge=lfs -text
 hguq_HG-PIPE/SPINAL/vivado/BlockSequence_bb_replaced.v filter=lfs diff=lfs merge=lfs -text
+efabless_caravel_mpw-one/verilog/gl/DFFRAM.v filter=lfs diff=lfs merge=lfs -text
+efabless_caravel_mpw-one/verilog/gl/mgmt_core.v filter=lfs diff=lfs merge=lfs -text
+lamda-bbo_Open3DBench/OpenROAD-3D/flow/designs/nangate45/bp_quad/bsg_chip_block.sv2v.v filter=lfs diff=lfs merge=lfs -text
+lamda-bbo_Open3DBench/OpenROAD-3D/flow/designs/nangate45_3D/bp_quad/bsg_chip_block.sv2v.v filter=lfs diff=lfs merge=lfs -text
+lamda-bbo_Open3DBench/OpenROAD-3D/flow/designs/src/bp_quad/bsg_chip_block.sv2v.v filter=lfs diff=lfs merge=lfs -text
+lamda-bbo_Open3DBench/OpenROAD-3D/flow/designs/src/coyote/coyote.sv2v.v filter=lfs diff=lfs merge=lfs -text

HDLForBeginners_Examples/30092022_testbench_start_finish/30092022_testbench_start_finish.tcl

@@ -0,0 +1,1426 @@
+#*****************************************************************************************
+# Vivado (TM) v2021.1 (64-bit)
+#
+# eth_pdm_fft.tcl: Tcl script for re-creating project 'eth_pdm_fft'
+#
+# Generated by Vivado on Wed Sep 28 21:50:21 SAST 2022
+# IP Build 3246043 on Fri Jun 11 00:30:35 MDT 2021
+#
+# This file contains the Vivado Tcl commands for re-creating the project to the state*
+# when this script was generated. In order to re-create the project, please source this
+# file in the Vivado Tcl Shell.
+#
+# * Note that the runs in the created project will be configured the same way as the
+#   original project, however they will not be launched automatically. To regenerate the
+#   run results please launch the synthesis/implementation runs as needed.
+#
+#*****************************************************************************************
+# NOTE: In order to use this script for source control purposes, please make sure that the
+#       following files are added to the source control system:-
+#
+# 1. This project restoration tcl script (eth_pdm_fft.tcl) that was generated.
+#
+# 2. The following source(s) files that were local or imported into the original project.
+#    (Please see the '$orig_proj_dir' and '$origin_dir' variable setting below at the start of the script)
+#
+#    "/media/edata/git/Examples/30_sep_2022_testbench_start_finish/ip/window_multiplier/window_multiplier.xci"
+#
+# 3. The following remote source files that were added to the original project:-
+#
+#    "/media/edata/git/Examples/30_sep_2022_testbench_start_finish/ip/data_fifo/data_fifo.xci"
+#    "/media/edata/git/Examples/30_sep_2022_testbench_start_finish/ip/cic_compiler/cic_compiler_0.xci"
+#    "/media/edata/git/Examples/30_sep_2022_testbench_start_finish/ip/clk_wiz_0/clk_wiz_0.xci"
+#    "/media/edata/git/Examples/30_sep_2022_testbench_start_finish/src/crc_gen.sv"
+#    "/media/edata/git/Examples/30_sep_2022_testbench_start_finish/src/endian_switch.sv"
+#    "/media/edata/git/Examples/30_sep_2022_testbench_start_finish/src/ethernet_header_pkg.sv"
+#    "/media/edata/git/Examples/30_sep_2022_testbench_start_finish/src/eth_header_gen.sv"
+#    "/media/edata/git/Examples/30_sep_2022_testbench_start_finish/src/eth_rst_gen.sv"
+#    "/media/edata/git/Examples/30_sep_2022_testbench_start_finish/src/packet_gen.sv"
+#    "/media/edata/git/Examples/30_sep_2022_testbench_start_finish/src/parzen.sv"
+#    "/media/edata/git/Examples/30_sep_2022_testbench_start_finish/src/pdm_clk_gen.sv"
+#    "/media/edata/git/Examples/30_sep_2022_testbench_start_finish/src/pdm_microphone.sv"
+#    "/media/edata/git/Examples/30_sep_2022_testbench_start_finish/src/rst_gen.sv"
+#    "/media/edata/git/Examples/30_sep_2022_testbench_start_finish/src/triangle_gen.sv"
+#    "/media/edata/git/Examples/30_sep_2022_testbench_start_finish/src/ethernet_top.sv"
+#    "/media/edata/git/Examples/30_sep_2022_testbench_start_finish/ip/xfft_0/xfft_0.xci"
+#    "/media/edata/git/Examples/30_sep_2022_testbench_start_finish/xdc/Nexys-A7-100T-Master.xdc"
+#    "/media/edata/git/Examples/30_sep_2022_testbench_start_finish/tb/log_data.sv"
+#    "/media/edata/git/Examples/30_sep_2022_testbench_start_finish/tb/read_stim.sv"
+#    "/media/edata/git/Examples/30_sep_2022_testbench_start_finish/tb/ethernet_tb.sv"
+#
+#*****************************************************************************************
+
+# Check file required for this script exists
+proc checkRequiredFiles { origin_dir} {
+  set status true
+  set files [list \
+ "[file normalize "$origin_dir/ip/window_multiplier/window_multiplier.xci"]"\
+  ]
+  foreach ifile $files {
+    if { ![file isfile $ifile] } {
+      puts " Could not find local file $ifile "
+      set status false
+    }
+  }
+
+  set files [list \
+ "[file normalize "$origin_dir/ip/data_fifo/data_fifo.xci"]"\
+ "[file normalize "$origin_dir/ip/cic_compiler/cic_compiler_0.xci"]"\
+ "[file normalize "$origin_dir/ip/clk_wiz_0/clk_wiz_0.xci"]"\
+ "[file normalize "$origin_dir/src/crc_gen.sv"]"\
+ "[file normalize "$origin_dir/src/endian_switch.sv"]"\
+ "[file normalize "$origin_dir/src/ethernet_header_pkg.sv"]"\
+ "[file normalize "$origin_dir/src/eth_header_gen.sv"]"\
+ "[file normalize "$origin_dir/src/eth_rst_gen.sv"]"\
+ "[file normalize "$origin_dir/src/packet_gen.sv"]"\
+ "[file normalize "$origin_dir/src/parzen.sv"]"\
+ "[file normalize "$origin_dir/src/pdm_clk_gen.sv"]"\
+ "[file normalize "$origin_dir/src/pdm_microphone.sv"]"\
+ "[file normalize "$origin_dir/src/rst_gen.sv"]"\
+ "[file normalize "$origin_dir/src/triangle_gen.sv"]"\
+ "[file normalize "$origin_dir/src/ethernet_top.sv"]"\
+ "[file normalize "$origin_dir/ip/xfft_0/xfft_0.xci"]"\
+ "[file normalize "$origin_dir/xdc/Nexys-A7-100T-Master.xdc"]"\
+ "[file normalize "$origin_dir/tb/log_data.sv"]"\
+ "[file normalize "$origin_dir/tb/read_stim.sv"]"\
+ "[file normalize "$origin_dir/tb/ethernet_tb.sv"]"\
+  ]
+  foreach ifile $files {
+    if { ![file isfile $ifile] } {
+      puts " Could not find remote file $ifile "
+      set status false
+    }
+  }
+
+  return $status
+}
+# Set the reference directory for source file relative paths (by default the value is script directory path)
+set origin_dir [file dirname [info script]]
+
+# Use origin directory path location variable, if specified in the tcl shell
+if { [info exists ::origin_dir_loc] } {
+  set origin_dir $::origin_dir_loc
+}
+
+# Set the project name
+set _xil_proj_name_ "30_sep_2022_testbench_start_finish"
+
+# Use project name variable, if specified in the tcl shell
+if { [info exists ::user_project_name] } {
+  set _xil_proj_name_ $::user_project_name
+}
+
+variable script_file
+set script_file "30_sep_2022_testbench_start_finish.tcl"
+
+# Help information for this script
+proc print_help {} {
+  variable script_file
+  puts "\nDescription:"
+  puts "Recreate a Vivado project from this script. The created project will be"
+  puts "functionally equivalent to the original project for which this script was"
+  puts "generated. The script contains commands for creating a project, filesets,"
+  puts "runs, adding/importing sources and setting properties on various objects.\n"
+  puts "Syntax:"
+  puts "$script_file"
+  puts "$script_file -tclargs \[--origin_dir <path>\]"
+  puts "$script_file -tclargs \[--project_name <name>\]"
+  puts "$script_file -tclargs \[--help\]\n"
+  puts "Usage:"
+  puts "Name                   Description"
+  puts "-------------------------------------------------------------------------"
+  puts "\[--origin_dir <path>\]  Determine source file paths wrt this path. Default"
+  puts "                       origin_dir path value is \".\", otherwise, the value"
+  puts "                       that was set with the \"-paths_relative_to\" switch"
+  puts "                       when this script was generated.\n"
+  puts "\[--project_name <name>\] Create project with the specified name. Default"
+  puts "                       name is the name of the project from where this"
+  puts "                       script was generated.\n"
+  puts "\[--help\]               Print help information for this script"
+  puts "-------------------------------------------------------------------------\n"
+  exit 0
+}
+
+if { $::argc > 0 } {
+  for {set i 0} {$i < $::argc} {incr i} {
+    set option [string trim [lindex $::argv $i]]
+    switch -regexp -- $option {
+      "--origin_dir"   { incr i; set origin_dir [lindex $::argv $i] }
+      "--project_name" { incr i; set _xil_proj_name_ [lindex $::argv $i] }
+      "--help"         { print_help }
+      default {
+        if { [regexp {^-} $option] } {
+          puts "ERROR: Unknown option '$option' specified, please type '$script_file -tclargs --help' for usage info.\n"
+          return 1
+        }
+      }
+    }
+  }
+}
+
+# Set the directory path for the original project from where this script was exported
+set orig_proj_dir "[file normalize "$origin_dir/30_sep_2022_testbench_start_finish"]"
+
+# Check for paths and files needed for project creation
+set validate_required 0
+if { $validate_required } {
+  if { [checkRequiredFiles $origin_dir] } {
+    puts "Tcl file $script_file is valid. All files required for project creation is accesable. "
+  } else {
+    puts "Tcl file $script_file is not valid. Not all files required for project creation is accesable. "
+    return
+  }
+}
+
+# Create project
+create_project ${_xil_proj_name_} ${origin_dir}/${_xil_proj_name_} -part xc7a100tcsg324-1
+
+# Set the directory path for the new project
+set proj_dir [get_property directory [current_project]]
+
+# Set project properties
+set obj [current_project]
+
+set digilent_boardname "digilentinc.com:nexys-a7-100t:part0:1.0"
+
+# Check if board file is available
+if {[string first ${digilent_boardname} [get_board_parts]] != -1} {
+    set_property -name "board_part" -value ${digilent_boardname} -objects $obj
+}
+
+# Set project properties
+set obj [current_project]
+set_property -name "default_lib" -value "xil_defaultlib" -objects $obj
+set_property -name "enable_vhdl_2008" -value "1" -objects $obj
+set_property -name "ip_cache_permissions" -value "read write" -objects $obj
+set_property -name "ip_output_repo" -value "$proj_dir/${_xil_proj_name_}.cache/ip" -objects $obj
+set_property -name "mem.enable_memory_map_generation" -value "1" -objects $obj
+set_property -name "platform.board_id" -value "nexys-a7-100t" -objects $obj
+set_property -name "revised_directory_structure" -value "1" -objects $obj
+set_property -name "sim.central_dir" -value "$proj_dir/${_xil_proj_name_}.ip_user_files" -objects $obj
+set_property -name "sim.ip.auto_export_scripts" -value "1" -objects $obj
+set_property -name "simulator_language" -value "Mixed" -objects $obj
+set_property -name "webtalk.activehdl_export_sim" -value "10" -objects $obj
+set_property -name "webtalk.ies_export_sim" -value "10" -objects $obj
+set_property -name "webtalk.modelsim_export_sim" -value "10" -objects $obj
+set_property -name "webtalk.questa_export_sim" -value "10" -objects $obj
+set_property -name "webtalk.riviera_export_sim" -value "10" -objects $obj
+set_property -name "webtalk.vcs_export_sim" -value "10" -objects $obj
+set_property -name "webtalk.xsim_export_sim" -value "10" -objects $obj
+set_property -name "webtalk.xsim_launch_sim" -value "187" -objects $obj
+set_property -name "xpm_libraries" -value "XPM_CDC XPM_MEMORY" -objects $obj
+
+# Create 'sources_1' fileset (if not found)
+if {[string equal [get_filesets -quiet sources_1] ""]} {
+  create_fileset -srcset sources_1
+}
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+set files [list \
+ [file normalize "${origin_dir}/ip/data_fifo/data_fifo.xci"] \
+ [file normalize "${origin_dir}/ip/cic_compiler/cic_compiler_0.xci"] \
+ [file normalize "${origin_dir}/ip/clk_wiz_0/clk_wiz_0.xci"] \
+ [file normalize "${origin_dir}/src/crc_gen.sv"] \
+ [file normalize "${origin_dir}/src/endian_switch.sv"] \
+ [file normalize "${origin_dir}/src/ethernet_header_pkg.sv"] \
+ [file normalize "${origin_dir}/src/eth_header_gen.sv"] \
+ [file normalize "${origin_dir}/src/eth_rst_gen.sv"] \
+ [file normalize "${origin_dir}/src/packet_gen.sv"] \
+ [file normalize "${origin_dir}/src/parzen.sv"] \
+ [file normalize "${origin_dir}/src/pdm_clk_gen.sv"] \
+ [file normalize "${origin_dir}/src/pdm_microphone.sv"] \
+ [file normalize "${origin_dir}/src/rst_gen.sv"] \
+ [file normalize "${origin_dir}/src/triangle_gen.sv"] \
+ [file normalize "${origin_dir}/src/ethernet_top.sv"] \
+]
+add_files -norecurse -fileset $obj $files
+
+# Set 'sources_1' fileset file properties for remote files
+set file "$origin_dir/ip/data_fifo/data_fifo.xci"
+set file [file normalize $file]
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "generate_synth_checkpoint" -value "1" -objects $file_obj
+}
+set_property -name "is_enabled" -value "1" -objects $file_obj
+set_property -name "is_global_include" -value "0" -objects $file_obj
+set_property -name "library" -value "xil_defaultlib" -objects $file_obj
+set_property -name "path_mode" -value "RelativeFirst" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+set_property -name "used_in" -value "synthesis implementation simulation" -objects $file_obj
+set_property -name "used_in_implementation" -value "1" -objects $file_obj
+set_property -name "used_in_simulation" -value "1" -objects $file_obj
+set_property -name "used_in_synthesis" -value "1" -objects $file_obj
+
+set file "$origin_dir/ip/cic_compiler/cic_compiler_0.xci"
+set file [file normalize $file]
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "generate_synth_checkpoint" -value "1" -objects $file_obj
+}
+set_property -name "is_enabled" -value "1" -objects $file_obj
+set_property -name "is_global_include" -value "0" -objects $file_obj
+set_property -name "library" -value "xil_defaultlib" -objects $file_obj
+set_property -name "path_mode" -value "RelativeFirst" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+set_property -name "used_in" -value "synthesis implementation simulation" -objects $file_obj
+set_property -name "used_in_implementation" -value "1" -objects $file_obj
+set_property -name "used_in_simulation" -value "1" -objects $file_obj
+set_property -name "used_in_synthesis" -value "1" -objects $file_obj
+
+set file "$origin_dir/ip/clk_wiz_0/clk_wiz_0.xci"
+set file [file normalize $file]
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "generate_synth_checkpoint" -value "1" -objects $file_obj
+}
+set_property -name "is_enabled" -value "1" -objects $file_obj
+set_property -name "is_global_include" -value "0" -objects $file_obj
+set_property -name "library" -value "xil_defaultlib" -objects $file_obj
+set_property -name "path_mode" -value "RelativeFirst" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+set_property -name "used_in" -value "synthesis implementation simulation" -objects $file_obj
+set_property -name "used_in_implementation" -value "1" -objects $file_obj
+set_property -name "used_in_simulation" -value "1" -objects $file_obj
+set_property -name "used_in_synthesis" -value "1" -objects $file_obj
+
+set file "$origin_dir/src/crc_gen.sv"
+set file [file normalize $file]
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "SystemVerilog" -objects $file_obj
+set_property -name "is_enabled" -value "1" -objects $file_obj
+set_property -name "is_global_include" -value "0" -objects $file_obj
+set_property -name "library" -value "xil_defaultlib" -objects $file_obj
+set_property -name "path_mode" -value "RelativeFirst" -objects $file_obj
+set_property -name "used_in" -value "synthesis implementation simulation" -objects $file_obj
+set_property -name "used_in_implementation" -value "1" -objects $file_obj
+set_property -name "used_in_simulation" -value "1" -objects $file_obj
+set_property -name "used_in_synthesis" -value "1" -objects $file_obj
+
+set file "$origin_dir/src/endian_switch.sv"
+set file [file normalize $file]
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "SystemVerilog" -objects $file_obj
+set_property -name "is_enabled" -value "1" -objects $file_obj
+set_property -name "is_global_include" -value "0" -objects $file_obj
+set_property -name "library" -value "xil_defaultlib" -objects $file_obj
+set_property -name "path_mode" -value "RelativeFirst" -objects $file_obj
+set_property -name "used_in" -value "synthesis implementation simulation" -objects $file_obj
+set_property -name "used_in_implementation" -value "1" -objects $file_obj
+set_property -name "used_in_simulation" -value "1" -objects $file_obj
+set_property -name "used_in_synthesis" -value "1" -objects $file_obj
+
+set file "$origin_dir/src/ethernet_header_pkg.sv"
+set file [file normalize $file]
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "SystemVerilog" -objects $file_obj
+set_property -name "is_enabled" -value "1" -objects $file_obj
+set_property -name "is_global_include" -value "0" -objects $file_obj
+set_property -name "library" -value "xil_defaultlib" -objects $file_obj
+set_property -name "path_mode" -value "RelativeFirst" -objects $file_obj
+set_property -name "used_in" -value "synthesis implementation simulation" -objects $file_obj
+set_property -name "used_in_implementation" -value "1" -objects $file_obj
+set_property -name "used_in_simulation" -value "1" -objects $file_obj
+set_property -name "used_in_synthesis" -value "1" -objects $file_obj
+
+set file "$origin_dir/src/eth_header_gen.sv"
+set file [file normalize $file]
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "SystemVerilog" -objects $file_obj
+set_property -name "is_enabled" -value "1" -objects $file_obj
+set_property -name "is_global_include" -value "0" -objects $file_obj
+set_property -name "library" -value "xil_defaultlib" -objects $file_obj
+set_property -name "path_mode" -value "RelativeFirst" -objects $file_obj
+set_property -name "used_in" -value "synthesis implementation simulation" -objects $file_obj
+set_property -name "used_in_implementation" -value "1" -objects $file_obj
+set_property -name "used_in_simulation" -value "1" -objects $file_obj
+set_property -name "used_in_synthesis" -value "1" -objects $file_obj
+
+set file "$origin_dir/src/eth_rst_gen.sv"
+set file [file normalize $file]
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "SystemVerilog" -objects $file_obj
+set_property -name "is_enabled" -value "1" -objects $file_obj
+set_property -name "is_global_include" -value "0" -objects $file_obj
+set_property -name "library" -value "xil_defaultlib" -objects $file_obj
+set_property -name "path_mode" -value "RelativeFirst" -objects $file_obj
+set_property -name "used_in" -value "synthesis implementation simulation" -objects $file_obj
+set_property -name "used_in_implementation" -value "1" -objects $file_obj
+set_property -name "used_in_simulation" -value "1" -objects $file_obj
+set_property -name "used_in_synthesis" -value "1" -objects $file_obj
+
+set file "$origin_dir/src/packet_gen.sv"
+set file [file normalize $file]
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "SystemVerilog" -objects $file_obj
+set_property -name "is_enabled" -value "1" -objects $file_obj
+set_property -name "is_global_include" -value "0" -objects $file_obj
+set_property -name "library" -value "xil_defaultlib" -objects $file_obj
+set_property -name "path_mode" -value "RelativeFirst" -objects $file_obj
+set_property -name "used_in" -value "synthesis implementation simulation" -objects $file_obj
+set_property -name "used_in_implementation" -value "1" -objects $file_obj
+set_property -name "used_in_simulation" -value "1" -objects $file_obj
+set_property -name "used_in_synthesis" -value "1" -objects $file_obj
+
+set file "$origin_dir/src/parzen.sv"
+set file [file normalize $file]
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "SystemVerilog" -objects $file_obj
+set_property -name "is_enabled" -value "1" -objects $file_obj
+set_property -name "is_global_include" -value "0" -objects $file_obj
+set_property -name "library" -value "xil_defaultlib" -objects $file_obj
+set_property -name "path_mode" -value "RelativeFirst" -objects $file_obj
+set_property -name "used_in" -value "synthesis implementation simulation" -objects $file_obj
+set_property -name "used_in_implementation" -value "1" -objects $file_obj
+set_property -name "used_in_simulation" -value "1" -objects $file_obj
+set_property -name "used_in_synthesis" -value "1" -objects $file_obj
+
+set file "$origin_dir/src/pdm_clk_gen.sv"
+set file [file normalize $file]
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "SystemVerilog" -objects $file_obj
+set_property -name "is_enabled" -value "1" -objects $file_obj
+set_property -name "is_global_include" -value "0" -objects $file_obj
+set_property -name "library" -value "xil_defaultlib" -objects $file_obj
+set_property -name "path_mode" -value "RelativeFirst" -objects $file_obj
+set_property -name "used_in" -value "synthesis implementation simulation" -objects $file_obj
+set_property -name "used_in_implementation" -value "1" -objects $file_obj
+set_property -name "used_in_simulation" -value "1" -objects $file_obj
+set_property -name "used_in_synthesis" -value "1" -objects $file_obj
+
+set file "$origin_dir/src/pdm_microphone.sv"
+set file [file normalize $file]
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "SystemVerilog" -objects $file_obj
+set_property -name "is_enabled" -value "1" -objects $file_obj
+set_property -name "is_global_include" -value "0" -objects $file_obj
+set_property -name "library" -value "xil_defaultlib" -objects $file_obj
+set_property -name "path_mode" -value "RelativeFirst" -objects $file_obj
+set_property -name "used_in" -value "synthesis implementation simulation" -objects $file_obj
+set_property -name "used_in_implementation" -value "1" -objects $file_obj
+set_property -name "used_in_simulation" -value "1" -objects $file_obj
+set_property -name "used_in_synthesis" -value "1" -objects $file_obj
+
+set file "$origin_dir/src/rst_gen.sv"
+set file [file normalize $file]
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "SystemVerilog" -objects $file_obj
+set_property -name "is_enabled" -value "1" -objects $file_obj
+set_property -name "is_global_include" -value "0" -objects $file_obj
+set_property -name "library" -value "xil_defaultlib" -objects $file_obj
+set_property -name "path_mode" -value "RelativeFirst" -objects $file_obj
+set_property -name "used_in" -value "synthesis implementation simulation" -objects $file_obj
+set_property -name "used_in_implementation" -value "1" -objects $file_obj
+set_property -name "used_in_simulation" -value "1" -objects $file_obj
+set_property -name "used_in_synthesis" -value "1" -objects $file_obj
+
+set file "$origin_dir/src/triangle_gen.sv"
+set file [file normalize $file]
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "SystemVerilog" -objects $file_obj
+set_property -name "is_enabled" -value "1" -objects $file_obj
+set_property -name "is_global_include" -value "0" -objects $file_obj
+set_property -name "library" -value "xil_defaultlib" -objects $file_obj
+set_property -name "path_mode" -value "RelativeFirst" -objects $file_obj
+set_property -name "used_in" -value "synthesis implementation simulation" -objects $file_obj
+set_property -name "used_in_implementation" -value "1" -objects $file_obj
+set_property -name "used_in_simulation" -value "1" -objects $file_obj
+set_property -name "used_in_synthesis" -value "1" -objects $file_obj
+
+set file "$origin_dir/src/ethernet_top.sv"
+set file [file normalize $file]
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "SystemVerilog" -objects $file_obj
+set_property -name "is_enabled" -value "1" -objects $file_obj
+set_property -name "is_global_include" -value "0" -objects $file_obj
+set_property -name "library" -value "xil_defaultlib" -objects $file_obj
+set_property -name "path_mode" -value "RelativeFirst" -objects $file_obj
+set_property -name "used_in" -value "synthesis implementation simulation" -objects $file_obj
+set_property -name "used_in_implementation" -value "1" -objects $file_obj
+set_property -name "used_in_simulation" -value "1" -objects $file_obj
+set_property -name "used_in_synthesis" -value "1" -objects $file_obj
+
+
+# Set 'sources_1' fileset file properties for local files
+# None
+
+# Set 'sources_1' fileset properties
+set obj [get_filesets sources_1]
+set_property -name "design_mode" -value "RTL" -objects $obj
+set_property -name "edif_extra_search_paths" -value "" -objects $obj
+set_property -name "elab_link_dcps" -value "1" -objects $obj
+set_property -name "elab_load_timing_constraints" -value "1" -objects $obj
+set_property -name "generic" -value "" -objects $obj
+set_property -name "include_dirs" -value "" -objects $obj
+set_property -name "lib_map_file" -value "" -objects $obj
+set_property -name "loop_count" -value "1000" -objects $obj
+set_property -name "name" -value "sources_1" -objects $obj
+set_property -name "top" -value "ethernet_top" -objects $obj
+set_property -name "top_auto_set" -value "0" -objects $obj
+set_property -name "verilog_define" -value "" -objects $obj
+set_property -name "verilog_uppercase" -value "0" -objects $obj
+set_property -name "verilog_version" -value "verilog_2001" -objects $obj
+set_property -name "vhdl_version" -value "vhdl_2k" -objects $obj
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+set files [list \
+ [file normalize "${origin_dir}/ip/xfft_0/xfft_0.xci"] \
+]
+add_files -norecurse -fileset $obj $files
+
+# Set 'sources_1' fileset file properties for remote files
+set file "$origin_dir/ip/xfft_0/xfft_0.xci"
+set file [file normalize $file]
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "generate_synth_checkpoint" -value "1" -objects $file_obj
+}
+set_property -name "is_enabled" -value "1" -objects $file_obj
+set_property -name "is_global_include" -value "0" -objects $file_obj
+set_property -name "library" -value "xil_defaultlib" -objects $file_obj
+set_property -name "path_mode" -value "RelativeFirst" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+set_property -name "used_in" -value "synthesis implementation simulation" -objects $file_obj
+set_property -name "used_in_implementation" -value "1" -objects $file_obj
+set_property -name "used_in_simulation" -value "1" -objects $file_obj
+set_property -name "used_in_synthesis" -value "1" -objects $file_obj
+
+
+# Set 'sources_1' fileset file properties for local files
+# None
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+# Add local files from the original project (-no_copy_sources specified)
+set files [list \
+ [file normalize "${origin_dir}/ip/window_multiplier/window_multiplier.xci" ]\
+]
+set added_files [add_files -fileset sources_1 $files]
+
+# Set 'sources_1' fileset file properties for remote files
+# None
+
+# Set 'sources_1' fileset file properties for local files
+set file "window_multiplier/window_multiplier.xci"
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "generate_synth_checkpoint" -value "1" -objects $file_obj
+}
+set_property -name "is_enabled" -value "1" -objects $file_obj
+set_property -name "is_global_include" -value "0" -objects $file_obj
+set_property -name "library" -value "xil_defaultlib" -objects $file_obj
+set_property -name "path_mode" -value "RelativeFirst" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+set_property -name "used_in" -value "synthesis implementation simulation" -objects $file_obj
+set_property -name "used_in_implementation" -value "1" -objects $file_obj
+set_property -name "used_in_simulation" -value "1" -objects $file_obj
+set_property -name "used_in_synthesis" -value "1" -objects $file_obj
+
+
+# Create 'constrs_1' fileset (if not found)
+if {[string equal [get_filesets -quiet constrs_1] ""]} {
+  create_fileset -constrset constrs_1
+}
+
+# Set 'constrs_1' fileset object
+set obj [get_filesets constrs_1]
+
+# Add/Import constrs file and set constrs file properties
+set file "[file normalize "$origin_dir/xdc/Nexys-A7-100T-Master.xdc"]"
+set file_added [add_files -norecurse -fileset $obj [list $file]]
+set file "$origin_dir/xdc/Nexys-A7-100T-Master.xdc"
+set file [file normalize $file]
+set file_obj [get_files -of_objects [get_filesets constrs_1] [list "*$file"]]
+set_property -name "file_type" -value "XDC" -objects $file_obj
+set_property -name "is_enabled" -value "1" -objects $file_obj
+set_property -name "is_global_include" -value "0" -objects $file_obj
+set_property -name "library" -value "xil_defaultlib" -objects $file_obj
+set_property -name "path_mode" -value "RelativeFirst" -objects $file_obj
+set_property -name "processing_order" -value "NORMAL" -objects $file_obj
+set_property -name "scoped_to_cells" -value "" -objects $file_obj
+set_property -name "scoped_to_ref" -value "" -objects $file_obj
+set_property -name "used_in" -value "synthesis implementation" -objects $file_obj
+set_property -name "used_in_implementation" -value "1" -objects $file_obj
+set_property -name "used_in_synthesis" -value "1" -objects $file_obj
+
+# Set 'constrs_1' fileset properties
+set obj [get_filesets constrs_1]
+set_property -name "constrs_type" -value "XDC" -objects $obj
+set_property -name "name" -value "constrs_1" -objects $obj
+set_property -name "target_constrs_file" -value "" -objects $obj
+
+# Create 'sim_1' fileset (if not found)
+if {[string equal [get_filesets -quiet sim_1] ""]} {
+  create_fileset -simset sim_1
+}
+
+# Set 'sim_1' fileset object
+set obj [get_filesets sim_1]
+set files [list \
+ [file normalize "${origin_dir}/tb/log_data.sv"] \
+ [file normalize "${origin_dir}/tb/read_stim.sv"] \
+ [file normalize "${origin_dir}/tb/ethernet_tb.sv"] \
+]
+add_files -norecurse -fileset $obj $files
+
+# Set 'sim_1' fileset file properties for remote files
+set file "$origin_dir/tb/log_data.sv"
+set file [file normalize $file]
+set file_obj [get_files -of_objects [get_filesets sim_1] [list "*$file"]]
+set_property -name "file_type" -value "SystemVerilog" -objects $file_obj
+set_property -name "is_enabled" -value "1" -objects $file_obj
+set_property -name "is_global_include" -value "0" -objects $file_obj
+set_property -name "library" -value "xil_defaultlib" -objects $file_obj
+set_property -name "path_mode" -value "RelativeFirst" -objects $file_obj
+set_property -name "used_in" -value "synthesis implementation simulation" -objects $file_obj
+set_property -name "used_in_implementation" -value "1" -objects $file_obj
+set_property -name "used_in_simulation" -value "1" -objects $file_obj
+set_property -name "used_in_synthesis" -value "1" -objects $file_obj
+
+set file "$origin_dir/tb/read_stim.sv"
+set file [file normalize $file]
+set file_obj [get_files -of_objects [get_filesets sim_1] [list "*$file"]]
+set_property -name "file_type" -value "SystemVerilog" -objects $file_obj
+set_property -name "is_enabled" -value "1" -objects $file_obj
+set_property -name "is_global_include" -value "0" -objects $file_obj
+set_property -name "library" -value "xil_defaultlib" -objects $file_obj
+set_property -name "path_mode" -value "RelativeFirst" -objects $file_obj
+set_property -name "used_in" -value "synthesis implementation simulation" -objects $file_obj
+set_property -name "used_in_implementation" -value "1" -objects $file_obj
+set_property -name "used_in_simulation" -value "1" -objects $file_obj
+set_property -name "used_in_synthesis" -value "1" -objects $file_obj
+
+set file "$origin_dir/tb/ethernet_tb.sv"
+set file [file normalize $file]
+set file_obj [get_files -of_objects [get_filesets sim_1] [list "*$file"]]
+set_property -name "file_type" -value "SystemVerilog" -objects $file_obj
+set_property -name "is_enabled" -value "1" -objects $file_obj
+set_property -name "is_global_include" -value "0" -objects $file_obj
+set_property -name "library" -value "xil_defaultlib" -objects $file_obj
+set_property -name "path_mode" -value "RelativeFirst" -objects $file_obj
+set_property -name "used_in" -value "synthesis implementation simulation" -objects $file_obj
+set_property -name "used_in_implementation" -value "1" -objects $file_obj
+set_property -name "used_in_simulation" -value "1" -objects $file_obj
+set_property -name "used_in_synthesis" -value "1" -objects $file_obj
+
+
+# Set 'sim_1' fileset file properties for local files
+# None
+
+# Set 'sim_1' fileset properties
+set obj [get_filesets sim_1]
+set_property -name "32bit" -value "0" -objects $obj
+set_property -name "force_compile_glbl" -value "0" -objects $obj
+set_property -name "force_no_compile_glbl" -value "0" -objects $obj
+set_property -name "generate_scripts_only" -value "0" -objects $obj
+set_property -name "generic" -value "" -objects $obj
+set_property -name "hbs.configure_design_for_hier_access" -value "1" -objects $obj
+set_property -name "hw_emu.debug_mode" -value "wdb" -objects $obj
+set_property -name "include_dirs" -value "" -objects $obj
+set_property -name "incremental" -value "1" -objects $obj
+set_property -name "name" -value "sim_1" -objects $obj
+set_property -name "nl.cell" -value "" -objects $obj
+set_property -name "nl.incl_unisim_models" -value "0" -objects $obj
+set_property -name "nl.process_corner" -value "slow" -objects $obj
+set_property -name "nl.rename_top" -value "" -objects $obj
+set_property -name "nl.sdf_anno" -value "1" -objects $obj
+set_property -name "nl.write_all_overrides" -value "0" -objects $obj
+set_property -name "simmodel_value_check" -value "1" -objects $obj
+set_property -name "simulator_launch_mode" -value "off" -objects $obj
+set_property -name "source_set" -value "sources_1" -objects $obj
+set_property -name "systemc_include_dirs" -value "" -objects $obj
+set_property -name "top" -value "ethernet_tb" -objects $obj
+set_property -name "top_auto_set" -value "0" -objects $obj
+set_property -name "top_lib" -value "xil_defaultlib" -objects $obj
+set_property -name "transport_int_delay" -value "0" -objects $obj
+set_property -name "transport_path_delay" -value "0" -objects $obj
+set_property -name "unifast" -value "0" -objects $obj
+set_property -name "verilog_define" -value "" -objects $obj
+set_property -name "verilog_uppercase" -value "0" -objects $obj
+set_property -name "xelab.dll" -value "0" -objects $obj
+set_property -name "xsim.compile.tcl.pre" -value "" -objects $obj
+set_property -name "xsim.compile.xsc.more_options" -value "" -objects $obj
+set_property -name "xsim.compile.xvhdl.more_options" -value "" -objects $obj
+set_property -name "xsim.compile.xvhdl.nosort" -value "1" -objects $obj
+set_property -name "xsim.compile.xvhdl.relax" -value "1" -objects $obj
+set_property -name "xsim.compile.xvlog.more_options" -value "" -objects $obj
+set_property -name "xsim.compile.xvlog.nosort" -value "1" -objects $obj
+set_property -name "xsim.compile.xvlog.relax" -value "1" -objects $obj
+set_property -name "xsim.elaborate.coverage.celldefine" -value "0" -objects $obj
+set_property -name "xsim.elaborate.coverage.dir" -value "" -objects $obj
+set_property -name "xsim.elaborate.coverage.library" -value "0" -objects $obj
+set_property -name "xsim.elaborate.coverage.name" -value "" -objects $obj
+set_property -name "xsim.elaborate.coverage.type" -value "" -objects $obj
+set_property -name "xsim.elaborate.debug_level" -value "typical" -objects $obj
+set_property -name "xsim.elaborate.load_glbl" -value "1" -objects $obj
+set_property -name "xsim.elaborate.mt_level" -value "auto" -objects $obj
+set_property -name "xsim.elaborate.rangecheck" -value "0" -objects $obj
+set_property -name "xsim.elaborate.relax" -value "1" -objects $obj
+set_property -name "xsim.elaborate.sdf_delay" -value "sdfmax" -objects $obj
+set_property -name "xsim.elaborate.snapshot" -value "" -objects $obj
+set_property -name "xsim.elaborate.xelab.more_options" -value "" -objects $obj
+set_property -name "xsim.elaborate.xsc.more_options" -value "" -objects $obj
+set_property -name "xsim.simulate.add_positional" -value "0" -objects $obj
+set_property -name "xsim.simulate.custom_tcl" -value "" -objects $obj
+set_property -name "xsim.simulate.log_all_signals" -value "0" -objects $obj
+set_property -name "xsim.simulate.no_quit" -value "0" -objects $obj
+set_property -name "xsim.simulate.runtime" -value "1000ns" -objects $obj
+set_property -name "xsim.simulate.saif" -value "" -objects $obj
+set_property -name "xsim.simulate.saif_all_signals" -value "0" -objects $obj
+set_property -name "xsim.simulate.saif_scope" -value "" -objects $obj
+set_property -name "xsim.simulate.tcl.post" -value "" -objects $obj
+set_property -name "xsim.simulate.wdb" -value "" -objects $obj
+set_property -name "xsim.simulate.xsim.more_options" -value "" -objects $obj
+
+# Set 'utils_1' fileset object
+set obj [get_filesets utils_1]
+# Empty (no sources present)
+
+# Set 'utils_1' fileset properties
+set obj [get_filesets utils_1]
+set_property -name "name" -value "utils_1" -objects $obj
+
+set idrFlowPropertiesConstraints ""
+catch {
+ set idrFlowPropertiesConstraints [get_param runs.disableIDRFlowPropertyConstraints]
+ set_param runs.disableIDRFlowPropertyConstraints 1
+}
+
+# Create 'synth_1' run (if not found)
+if {[string equal [get_runs -quiet synth_1] ""]} {
+    create_run -name synth_1 -part xc7a100tcsg324-1 -flow {Vivado Synthesis 2020} -strategy "Vivado Synthesis Defaults" -report_strategy {No Reports} -constrset constrs_1
+} else {
+  set_property strategy "Vivado Synthesis Defaults" [get_runs synth_1]
+  set_property flow "Vivado Synthesis 2020" [get_runs synth_1]
+}
+set obj [get_runs synth_1]
+set_property set_report_strategy_name 1 $obj
+set_property report_strategy {Vivado Synthesis Default Reports} $obj
+set_property set_report_strategy_name 0 $obj
+# Create 'synth_1_synth_report_utilization_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0] "" ] } {
+  create_report_config -report_name synth_1_synth_report_utilization_0 -report_type report_utilization:1.0 -steps synth_design -runs synth_1
+}
+set obj [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "1" -objects $obj
+set_property -name "display_name" -value "Utilization - Synth Design" -objects $obj
+set_property -name "options.pblocks" -value "" -objects $obj
+set_property -name "options.cells" -value "" -objects $obj
+set_property -name "options.slr" -value "0" -objects $obj
+set_property -name "options.packthru" -value "0" -objects $obj
+set_property -name "options.hierarchical" -value "0" -objects $obj
+set_property -name "options.hierarchical_depth" -value "" -objects $obj
+set_property -name "options.hierarchical_percentages" -value "0" -objects $obj
+set_property -name "options.more_options" -value "" -objects $obj
+
+}
+set obj [get_runs synth_1]
+set_property -name "constrset" -value "constrs_1" -objects $obj
+set_property -name "description" -value "Vivado Synthesis Defaults" -objects $obj
+set_property -name "flow" -value "Vivado Synthesis 2020" -objects $obj
+set_property -name "name" -value "synth_1" -objects $obj
+set_property -name "needs_refresh" -value "1" -objects $obj
+set_property -name "srcset" -value "sources_1" -objects $obj
+set_property -name "incremental_checkpoint" -value "" -objects $obj
+set_property -name "auto_incremental_checkpoint" -value "0" -objects $obj
+set_property -name "rqs_files" -value "" -objects $obj
+set_property -name "incremental_checkpoint.more_options" -value "" -objects $obj
+set_property -name "include_in_archive" -value "1" -objects $obj
+set_property -name "gen_full_bitstream" -value "1" -objects $obj
+set_property -name "write_incremental_synth_checkpoint" -value "0" -objects $obj
+set_property -name "auto_incremental_checkpoint.directory" -value "/media/edata/git/Examples/eth_pdm_fft/eth_pdm_fft/eth_pdm_fft.srcs/utils_1/imports/synth_1" -objects $obj
+set_property -name "strategy" -value "Vivado Synthesis Defaults" -objects $obj
+set_property -name "steps.synth_design.tcl.pre" -value "" -objects $obj
+set_property -name "steps.synth_design.tcl.post" -value "" -objects $obj
+set_property -name "steps.synth_design.args.flatten_hierarchy" -value "rebuilt" -objects $obj
+set_property -name "steps.synth_design.args.gated_clock_conversion" -value "off" -objects $obj
+set_property -name "steps.synth_design.args.bufg" -value "12" -objects $obj
+set_property -name "steps.synth_design.args.directive" -value "Default" -objects $obj
+set_property -name "steps.synth_design.args.retiming" -value "0" -objects $obj
+set_property -name "steps.synth_design.args.fsm_extraction" -value "auto" -objects $obj
+set_property -name "steps.synth_design.args.keep_equivalent_registers" -value "0" -objects $obj
+set_property -name "steps.synth_design.args.resource_sharing" -value "auto" -objects $obj
+set_property -name "steps.synth_design.args.control_set_opt_threshold" -value "auto" -objects $obj
+set_property -name "steps.synth_design.args.no_lc" -value "0" -objects $obj
+set_property -name "steps.synth_design.args.no_srlextract" -value "0" -objects $obj
+set_property -name "steps.synth_design.args.shreg_min_size" -value "3" -objects $obj
+set_property -name "steps.synth_design.args.max_bram" -value "-1" -objects $obj
+set_property -name "steps.synth_design.args.max_uram" -value "-1" -objects $obj
+set_property -name "steps.synth_design.args.max_dsp" -value "-1" -objects $obj
+set_property -name "steps.synth_design.args.max_bram_cascade_height" -value "-1" -objects $obj
+set_property -name "steps.synth_design.args.max_uram_cascade_height" -value "-1" -objects $obj
+set_property -name "steps.synth_design.args.cascade_dsp" -value "auto" -objects $obj
+set_property -name "steps.synth_design.args.assert" -value "0" -objects $obj
+set_property -name "steps.synth_design.args.more options" -value "" -objects $obj
+
+# set the current synth run
+current_run -synthesis [get_runs synth_1]
+
+# Create 'impl_1' run (if not found)
+if {[string equal [get_runs -quiet impl_1] ""]} {
+    create_run -name impl_1 -part xc7a100tcsg324-1 -flow {Vivado Implementation 2020} -strategy "Vivado Implementation Defaults" -report_strategy {No Reports} -constrset constrs_1 -parent_run synth_1
+} else {
+  set_property strategy "Vivado Implementation Defaults" [get_runs impl_1]
+  set_property flow "Vivado Implementation 2020" [get_runs impl_1]
+}
+set obj [get_runs impl_1]
+set_property set_report_strategy_name 1 $obj
+set_property report_strategy {Vivado Implementation Default Reports} $obj
+set_property set_report_strategy_name 0 $obj
+# Create 'impl_1_init_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_init_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps init_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "display_name" -value "Timing Summary - Design Initialization" -objects $obj
+set_property -name "options.check_timing_verbose" -value "0" -objects $obj
+set_property -name "options.delay_type" -value "" -objects $obj
+set_property -name "options.setup" -value "0" -objects $obj
+set_property -name "options.hold" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+set_property -name "options.nworst" -value "" -objects $obj
+set_property -name "options.unique_pins" -value "0" -objects $obj
+set_property -name "options.path_type" -value "" -objects $obj
+set_property -name "options.slack_lesser_than" -value "" -objects $obj
+set_property -name "options.report_unconstrained" -value "0" -objects $obj
+set_property -name "options.warn_on_violation" -value "0" -objects $obj
+set_property -name "options.significant_digits" -value "" -objects $obj
+set_property -name "options.cell" -value "" -objects $obj
+set_property -name "options.more_options" -value "" -objects $obj
+
+}
+# Create 'impl_1_opt_report_drc_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0] "" ] } {
+  create_report_config -report_name impl_1_opt_report_drc_0 -report_type report_drc:1.0 -steps opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "1" -objects $obj
+set_property -name "display_name" -value "DRC - Opt Design" -objects $obj
+set_property -name "options.upgrade_cw" -value "0" -objects $obj
+set_property -name "options.checks" -value "" -objects $obj
+set_property -name "options.ruledecks" -value "" -objects $obj
+set_property -name "options.more_options" -value "" -objects $obj
+
+}
+# Create 'impl_1_opt_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "display_name" -value "Timing Summary - Opt Design" -objects $obj
+set_property -name "options.check_timing_verbose" -value "0" -objects $obj
+set_property -name "options.delay_type" -value "" -objects $obj
+set_property -name "options.setup" -value "0" -objects $obj
+set_property -name "options.hold" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+set_property -name "options.nworst" -value "" -objects $obj
+set_property -name "options.unique_pins" -value "0" -objects $obj
+set_property -name "options.path_type" -value "" -objects $obj
+set_property -name "options.slack_lesser_than" -value "" -objects $obj
+set_property -name "options.report_unconstrained" -value "0" -objects $obj
+set_property -name "options.warn_on_violation" -value "0" -objects $obj
+set_property -name "options.significant_digits" -value "" -objects $obj
+set_property -name "options.cell" -value "" -objects $obj
+set_property -name "options.more_options" -value "" -objects $obj
+
+}
+# Create 'impl_1_power_opt_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps power_opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "display_name" -value "Timing Summary - Power Opt Design" -objects $obj
+set_property -name "options.check_timing_verbose" -value "0" -objects $obj
+set_property -name "options.delay_type" -value "" -objects $obj
+set_property -name "options.setup" -value "0" -objects $obj
+set_property -name "options.hold" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+set_property -name "options.nworst" -value "" -objects $obj
+set_property -name "options.unique_pins" -value "0" -objects $obj
+set_property -name "options.path_type" -value "" -objects $obj
+set_property -name "options.slack_lesser_than" -value "" -objects $obj
+set_property -name "options.report_unconstrained" -value "0" -objects $obj
+set_property -name "options.warn_on_violation" -value "0" -objects $obj
+set_property -name "options.significant_digits" -value "" -objects $obj
+set_property -name "options.cell" -value "" -objects $obj
+set_property -name "options.more_options" -value "" -objects $obj
+
+}
+# Create 'impl_1_place_report_io_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0] "" ] } {
+  create_report_config -report_name impl_1_place_report_io_0 -report_type report_io:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "1" -objects $obj
+set_property -name "display_name" -value "IO - Place Design" -objects $obj
+set_property -name "options.more_options" -value "" -objects $obj
+
+}
+# Create 'impl_1_place_report_utilization_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_utilization_0] "" ] } {
+  create_report_config -report_name impl_1_place_report_utilization_0 -report_type report_utilization:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_utilization_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "1" -objects $obj
+set_property -name "display_name" -value "Utilization - Place Design" -objects $obj
+set_property -name "options.pblocks" -value "" -objects $obj
+set_property -name "options.cells" -value "" -objects $obj
+set_property -name "options.slr" -value "0" -objects $obj
+set_property -name "options.packthru" -value "0" -objects $obj
+set_property -name "options.hierarchical" -value "0" -objects $obj
+set_property -name "options.hierarchical_depth" -value "" -objects $obj
+set_property -name "options.hierarchical_percentages" -value "0" -objects $obj
+set_property -name "options.more_options" -value "" -objects $obj
+
+}
+# Create 'impl_1_place_report_control_sets_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_control_sets_0] "" ] } {
+  create_report_config -report_name impl_1_place_report_control_sets_0 -report_type report_control_sets:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_control_sets_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "1" -objects $obj
+set_property -name "display_name" -value "Control Sets - Place Design" -objects $obj
+set_property -name "options.verbose" -value "1" -objects $obj
+set_property -name "options.cells" -value "" -objects $obj
+set_property -name "options.more_options" -value "" -objects $obj
+
+}
+# Create 'impl_1_place_report_incremental_reuse_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0] "" ] } {
+  create_report_config -report_name impl_1_place_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "display_name" -value "Incremental Reuse - Place Design" -objects $obj
+set_property -name "options.cells" -value "" -objects $obj
+set_property -name "options.hierarchical" -value "0" -objects $obj
+set_property -name "options.hierarchical_depth" -value "" -objects $obj
+set_property -name "options.more_options" -value "" -objects $obj
+
+}
+# Create 'impl_1_place_report_incremental_reuse_1' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_1] "" ] } {
+  create_report_config -report_name impl_1_place_report_incremental_reuse_1 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_1]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "display_name" -value "Incremental Reuse - Place Design" -objects $obj
+set_property -name "options.cells" -value "" -objects $obj
+set_property -name "options.hierarchical" -value "0" -objects $obj
+set_property -name "options.hierarchical_depth" -value "" -objects $obj
+set_property -name "options.more_options" -value "" -objects $obj
+
+}
+# Create 'impl_1_place_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_place_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "display_name" -value "Timing Summary - Place Design" -objects $obj
+set_property -name "options.check_timing_verbose" -value "0" -objects $obj
+set_property -name "options.delay_type" -value "" -objects $obj
+set_property -name "options.setup" -value "0" -objects $obj
+set_property -name "options.hold" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+set_property -name "options.nworst" -value "" -objects $obj
+set_property -name "options.unique_pins" -value "0" -objects $obj
+set_property -name "options.path_type" -value "" -objects $obj
+set_property -name "options.slack_lesser_than" -value "" -objects $obj
+set_property -name "options.report_unconstrained" -value "0" -objects $obj
+set_property -name "options.warn_on_violation" -value "0" -objects $obj
+set_property -name "options.significant_digits" -value "" -objects $obj
+set_property -name "options.cell" -value "" -objects $obj
+set_property -name "options.more_options" -value "" -objects $obj
+
+}
+# Create 'impl_1_post_place_power_opt_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_power_opt_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_post_place_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_place_power_opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_power_opt_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "display_name" -value "Timing Summary - Post-Place Power Opt Design" -objects $obj
+set_property -name "options.check_timing_verbose" -value "0" -objects $obj
+set_property -name "options.delay_type" -value "" -objects $obj
+set_property -name "options.setup" -value "0" -objects $obj
+set_property -name "options.hold" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+set_property -name "options.nworst" -value "" -objects $obj
+set_property -name "options.unique_pins" -value "0" -objects $obj
+set_property -name "options.path_type" -value "" -objects $obj
+set_property -name "options.slack_lesser_than" -value "" -objects $obj
+set_property -name "options.report_unconstrained" -value "0" -objects $obj
+set_property -name "options.warn_on_violation" -value "0" -objects $obj
+set_property -name "options.significant_digits" -value "" -objects $obj
+set_property -name "options.cell" -value "" -objects $obj
+set_property -name "options.more_options" -value "" -objects $obj
+
+}
+# Create 'impl_1_phys_opt_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps phys_opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "display_name" -value "Timing Summary - Post-Place Phys Opt Design" -objects $obj
+set_property -name "options.check_timing_verbose" -value "0" -objects $obj
+set_property -name "options.delay_type" -value "" -objects $obj
+set_property -name "options.setup" -value "0" -objects $obj
+set_property -name "options.hold" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+set_property -name "options.nworst" -value "" -objects $obj
+set_property -name "options.unique_pins" -value "0" -objects $obj
+set_property -name "options.path_type" -value "" -objects $obj
+set_property -name "options.slack_lesser_than" -value "" -objects $obj
+set_property -name "options.report_unconstrained" -value "0" -objects $obj
+set_property -name "options.warn_on_violation" -value "0" -objects $obj
+set_property -name "options.significant_digits" -value "" -objects $obj
+set_property -name "options.cell" -value "" -objects $obj
+set_property -name "options.more_options" -value "" -objects $obj
+
+}
+# Create 'impl_1_route_report_drc_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_drc_0 -report_type report_drc:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "1" -objects $obj
+set_property -name "display_name" -value "DRC - Route Design" -objects $obj
+set_property -name "options.upgrade_cw" -value "0" -objects $obj
+set_property -name "options.checks" -value "" -objects $obj
+set_property -name "options.ruledecks" -value "" -objects $obj
+set_property -name "options.more_options" -value "" -objects $obj
+
+}
+# Create 'impl_1_route_report_methodology_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_methodology_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_methodology_0 -report_type report_methodology:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_methodology_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "1" -objects $obj
+set_property -name "display_name" -value "Methodology - Route Design" -objects $obj
+set_property -name "options.checks" -value "" -objects $obj
+set_property -name "options.more_options" -value "" -objects $obj
+
+}
+# Create 'impl_1_route_report_power_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_power_0 -report_type report_power:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "1" -objects $obj
+set_property -name "display_name" -value "Power - Route Design" -objects $obj
+set_property -name "options.advisory" -value "0" -objects $obj
+set_property -name "options.xpe" -value "" -objects $obj
+set_property -name "options.more_options" -value "" -objects $obj
+
+}
+# Create 'impl_1_route_report_route_status_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_route_status_0 -report_type report_route_status:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "1" -objects $obj
+set_property -name "display_name" -value "Route Status - Route Design" -objects $obj
+set_property -name "options.of_objects" -value "" -objects $obj
+set_property -name "options.route_type" -value "" -objects $obj
+set_property -name "options.list_all_nets" -value "0" -objects $obj
+set_property -name "options.show_all" -value "0" -objects $obj
+set_property -name "options.has_routing" -value "0" -objects $obj
+set_property -name "options.more_options" -value "" -objects $obj
+
+}
+# Create 'impl_1_route_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "1" -objects $obj
+set_property -name "display_name" -value "Timing Summary - Route Design" -objects $obj
+set_property -name "options.check_timing_verbose" -value "0" -objects $obj
+set_property -name "options.delay_type" -value "" -objects $obj
+set_property -name "options.setup" -value "0" -objects $obj
+set_property -name "options.hold" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+set_property -name "options.nworst" -value "" -objects $obj
+set_property -name "options.unique_pins" -value "0" -objects $obj
+set_property -name "options.path_type" -value "" -objects $obj
+set_property -name "options.slack_lesser_than" -value "" -objects $obj
+set_property -name "options.report_unconstrained" -value "0" -objects $obj
+set_property -name "options.warn_on_violation" -value "0" -objects $obj
+set_property -name "options.significant_digits" -value "" -objects $obj
+set_property -name "options.cell" -value "" -objects $obj
+set_property -name "options.more_options" -value "" -objects $obj
+
+}
+# Create 'impl_1_route_report_incremental_reuse_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "1" -objects $obj
+set_property -name "display_name" -value "Incremental Reuse - Route Design" -objects $obj
+set_property -name "options.cells" -value "" -objects $obj
+set_property -name "options.hierarchical" -value "0" -objects $obj
+set_property -name "options.hierarchical_depth" -value "" -objects $obj
+set_property -name "options.more_options" -value "" -objects $obj
+
+}
+# Create 'impl_1_route_report_clock_utilization_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_clock_utilization_0 -report_type report_clock_utilization:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "1" -objects $obj
+set_property -name "display_name" -value "Clock Utilization - Route Design" -objects $obj
+set_property -name "options.write_xdc" -value "0" -objects $obj
+set_property -name "options.clock_roots_only" -value "0" -objects $obj
+set_property -name "options.more_options" -value "" -objects $obj
+
+}
+# Create 'impl_1_route_report_bus_skew_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_bus_skew_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_bus_skew_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "1" -objects $obj
+set_property -name "display_name" -value "Bus Skew - Route Design" -objects $obj
+set_property -name "options.delay_type" -value "" -objects $obj
+set_property -name "options.setup" -value "0" -objects $obj
+set_property -name "options.hold" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "" -objects $obj
+set_property -name "options.nworst" -value "" -objects $obj
+set_property -name "options.unique_pins" -value "0" -objects $obj
+set_property -name "options.path_type" -value "" -objects $obj
+set_property -name "options.slack_lesser_than" -value "" -objects $obj
+set_property -name "options.slack_greater_than" -value "" -objects $obj
+set_property -name "options.significant_digits" -value "" -objects $obj
+set_property -name "options.warn_on_violation" -value "1" -objects $obj
+set_property -name "options.more_options" -value "" -objects $obj
+
+}
+# Create 'impl_1_post_route_phys_opt_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_post_route_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_route_phys_opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "1" -objects $obj
+set_property -name "display_name" -value "Timing Summary - Post-Route Phys Opt Design" -objects $obj
+set_property -name "options.check_timing_verbose" -value "0" -objects $obj
+set_property -name "options.delay_type" -value "" -objects $obj
+set_property -name "options.setup" -value "0" -objects $obj
+set_property -name "options.hold" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+set_property -name "options.nworst" -value "" -objects $obj
+set_property -name "options.unique_pins" -value "0" -objects $obj
+set_property -name "options.path_type" -value "" -objects $obj
+set_property -name "options.slack_lesser_than" -value "" -objects $obj
+set_property -name "options.report_unconstrained" -value "0" -objects $obj
+set_property -name "options.warn_on_violation" -value "1" -objects $obj
+set_property -name "options.significant_digits" -value "" -objects $obj
+set_property -name "options.cell" -value "" -objects $obj
+set_property -name "options.more_options" -value "" -objects $obj
+
+}
+# Create 'impl_1_post_route_phys_opt_report_bus_skew_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_bus_skew_0] "" ] } {
+  create_report_config -report_name impl_1_post_route_phys_opt_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps post_route_phys_opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_bus_skew_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "1" -objects $obj
+set_property -name "display_name" -value "Bus Skew - Post-Route Phys Opt Design" -objects $obj
+set_property -name "options.delay_type" -value "" -objects $obj
+set_property -name "options.setup" -value "0" -objects $obj
+set_property -name "options.hold" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "" -objects $obj
+set_property -name "options.nworst" -value "" -objects $obj
+set_property -name "options.unique_pins" -value "0" -objects $obj
+set_property -name "options.path_type" -value "" -objects $obj
+set_property -name "options.slack_lesser_than" -value "" -objects $obj
+set_property -name "options.slack_greater_than" -value "" -objects $obj
+set_property -name "options.significant_digits" -value "" -objects $obj
+set_property -name "options.warn_on_violation" -value "1" -objects $obj
+set_property -name "options.more_options" -value "" -objects $obj
+
+}
+set obj [get_runs impl_1]
+set_property -name "constrset" -value "constrs_1" -objects $obj
+set_property -name "description" -value "Default settings for Implementation." -objects $obj
+set_property -name "flow" -value "Vivado Implementation 2020" -objects $obj
+set_property -name "name" -value "impl_1" -objects $obj
+set_property -name "needs_refresh" -value "1" -objects $obj
+set_property -name "pr_configuration" -value "" -objects $obj
+set_property -name "srcset" -value "sources_1" -objects $obj
+set_property -name "incremental_checkpoint" -value "" -objects $obj
+set_property -name "auto_incremental_checkpoint" -value "0" -objects $obj
+set_property -name "incremental_checkpoint.directive" -value "" -objects $obj
+set_property -name "rqs_files" -value "" -objects $obj
+set_property -name "incremental_checkpoint.more_options" -value "" -objects $obj
+set_property -name "include_in_archive" -value "1" -objects $obj
+set_property -name "gen_full_bitstream" -value "1" -objects $obj
+set_property -name "auto_incremental_checkpoint.directory" -value "/media/edata/git/Examples/eth_pdm_fft/eth_pdm_fft/eth_pdm_fft.srcs/utils_1/imports/impl_1" -objects $obj
+set_property -name "strategy" -value "Vivado Implementation Defaults" -objects $obj
+set_property -name "steps.init_design.tcl.pre" -value "" -objects $obj
+set_property -name "steps.init_design.tcl.post" -value "" -objects $obj
+set_property -name "steps.init_design.args.more options" -value "" -objects $obj
+set_property -name "steps.opt_design.is_enabled" -value "1" -objects $obj
+set_property -name "steps.opt_design.tcl.pre" -value "" -objects $obj
+set_property -name "steps.opt_design.tcl.post" -value "" -objects $obj
+set_property -name "steps.opt_design.args.verbose" -value "0" -objects $obj
+set_property -name "steps.opt_design.args.directive" -value "Default" -objects $obj
+set_property -name "steps.opt_design.args.more options" -value "" -objects $obj
+set_property -name "steps.power_opt_design.is_enabled" -value "0" -objects $obj
+set_property -name "steps.power_opt_design.tcl.pre" -value "" -objects $obj
+set_property -name "steps.power_opt_design.tcl.post" -value "" -objects $obj
+set_property -name "steps.power_opt_design.args.more options" -value "" -objects $obj
+set_property -name "steps.place_design.tcl.pre" -value "" -objects $obj
+set_property -name "steps.place_design.tcl.post" -value "" -objects $obj
+set_property -name "steps.place_design.args.directive" -value "Default" -objects $obj
+set_property -name "steps.place_design.args.more options" -value "" -objects $obj
+set_property -name "steps.post_place_power_opt_design.is_enabled" -value "0" -objects $obj
+set_property -name "steps.post_place_power_opt_design.tcl.pre" -value "" -objects $obj
+set_property -name "steps.post_place_power_opt_design.tcl.post" -value "" -objects $obj
+set_property -name "steps.post_place_power_opt_design.args.more options" -value "" -objects $obj
+set_property -name "steps.phys_opt_design.is_enabled" -value "1" -objects $obj
+set_property -name "steps.phys_opt_design.tcl.pre" -value "" -objects $obj
+set_property -name "steps.phys_opt_design.tcl.post" -value "" -objects $obj
+set_property -name "steps.phys_opt_design.args.directive" -value "Default" -objects $obj
+set_property -name "steps.phys_opt_design.args.more options" -value "" -objects $obj
+set_property -name "steps.route_design.tcl.pre" -value "" -objects $obj
+set_property -name "steps.route_design.tcl.post" -value "" -objects $obj
+set_property -name "steps.route_design.args.directive" -value "Default" -objects $obj
+set_property -name "steps.route_design.args.more options" -value "" -objects $obj
+set_property -name "steps.post_route_phys_opt_design.is_enabled" -value "0" -objects $obj
+set_property -name "steps.post_route_phys_opt_design.tcl.pre" -value "" -objects $obj
+set_property -name "steps.post_route_phys_opt_design.tcl.post" -value "" -objects $obj
+set_property -name "steps.post_route_phys_opt_design.args.directive" -value "Default" -objects $obj
+set_property -name "steps.post_route_phys_opt_design.args.more options" -value "" -objects $obj
+set_property -name "steps.write_bitstream.tcl.pre" -value "" -objects $obj
+set_property -name "steps.write_bitstream.tcl.post" -value "" -objects $obj
+set_property -name "steps.write_bitstream.args.raw_bitfile" -value "0" -objects $obj
+set_property -name "steps.write_bitstream.args.mask_file" -value "0" -objects $obj
+set_property -name "steps.write_bitstream.args.no_binary_bitfile" -value "0" -objects $obj
+set_property -name "steps.write_bitstream.args.bin_file" -value "0" -objects $obj
+set_property -name "steps.write_bitstream.args.readback_file" -value "0" -objects $obj
+set_property -name "steps.write_bitstream.args.logic_location_file" -value "0" -objects $obj
+set_property -name "steps.write_bitstream.args.verbose" -value "0" -objects $obj
+set_property -name "steps.write_bitstream.args.more options" -value "" -objects $obj
+
+# set the current impl run
+current_run -implementation [get_runs impl_1]
+catch {
+ if { $idrFlowPropertiesConstraints != {} } {
+   set_param runs.disableIDRFlowPropertyConstraints $idrFlowPropertiesConstraints
+ }
+}
+
+puts "INFO: Project created:${_xil_proj_name_}"
+# Create 'drc_1' gadget (if not found)
+if {[string equal [get_dashboard_gadgets  [ list "drc_1" ] ] ""]} {
+create_dashboard_gadget -name {drc_1} -type drc
+}
+set obj [get_dashboard_gadgets [ list "drc_1" ] ]
+set_property -name "active_reports" -value "" -objects $obj
+set_property -name "active_reports_invalid" -value "" -objects $obj
+set_property -name "active_run" -value "0" -objects $obj
+set_property -name "hide_unused_data" -value "1" -objects $obj
+set_property -name "incl_new_reports" -value "0" -objects $obj
+set_property -name "reports" -value "impl_1#impl_1_route_report_drc_0" -objects $obj
+set_property -name "run.step" -value "route_design" -objects $obj
+set_property -name "run.type" -value "implementation" -objects $obj
+set_property -name "statistics.critical_warning" -value "1" -objects $obj
+set_property -name "statistics.error" -value "1" -objects $obj
+set_property -name "statistics.info" -value "1" -objects $obj
+set_property -name "statistics.warning" -value "1" -objects $obj
+set_property -name "view.orientation" -value "Horizontal" -objects $obj
+set_property -name "view.type" -value "Graph" -objects $obj
+
+# Create 'methodology_1' gadget (if not found)
+if {[string equal [get_dashboard_gadgets  [ list "methodology_1" ] ] ""]} {
+create_dashboard_gadget -name {methodology_1} -type methodology
+}
+set obj [get_dashboard_gadgets [ list "methodology_1" ] ]
+set_property -name "active_reports" -value "" -objects $obj
+set_property -name "active_reports_invalid" -value "" -objects $obj
+set_property -name "active_run" -value "0" -objects $obj
+set_property -name "hide_unused_data" -value "1" -objects $obj
+set_property -name "incl_new_reports" -value "0" -objects $obj
+set_property -name "reports" -value "impl_1#impl_1_route_report_methodology_0" -objects $obj
+set_property -name "run.step" -value "route_design" -objects $obj
+set_property -name "run.type" -value "implementation" -objects $obj
+set_property -name "statistics.critical_warning" -value "1" -objects $obj
+set_property -name "statistics.error" -value "1" -objects $obj
+set_property -name "statistics.info" -value "1" -objects $obj
+set_property -name "statistics.warning" -value "1" -objects $obj
+set_property -name "view.orientation" -value "Horizontal" -objects $obj
+set_property -name "view.type" -value "Graph" -objects $obj
+
+# Create 'power_1' gadget (if not found)
+if {[string equal [get_dashboard_gadgets  [ list "power_1" ] ] ""]} {
+create_dashboard_gadget -name {power_1} -type power
+}
+set obj [get_dashboard_gadgets [ list "power_1" ] ]
+set_property -name "active_reports" -value "" -objects $obj
+set_property -name "active_reports_invalid" -value "" -objects $obj
+set_property -name "active_run" -value "0" -objects $obj
+set_property -name "hide_unused_data" -value "1" -objects $obj
+set_property -name "incl_new_reports" -value "0" -objects $obj
+set_property -name "reports" -value "impl_1#impl_1_route_report_power_0" -objects $obj
+set_property -name "run.step" -value "route_design" -objects $obj
+set_property -name "run.type" -value "implementation" -objects $obj
+set_property -name "statistics.bram" -value "1" -objects $obj
+set_property -name "statistics.clocks" -value "1" -objects $obj
+set_property -name "statistics.dsp" -value "1" -objects $obj
+set_property -name "statistics.gth" -value "1" -objects $obj
+set_property -name "statistics.gtp" -value "1" -objects $obj
+set_property -name "statistics.gtx" -value "1" -objects $obj
+set_property -name "statistics.gtz" -value "1" -objects $obj
+set_property -name "statistics.io" -value "1" -objects $obj
+set_property -name "statistics.logic" -value "1" -objects $obj
+set_property -name "statistics.mmcm" -value "1" -objects $obj
+set_property -name "statistics.pcie" -value "1" -objects $obj
+set_property -name "statistics.phaser" -value "1" -objects $obj
+set_property -name "statistics.pll" -value "1" -objects $obj
+set_property -name "statistics.pl_static" -value "1" -objects $obj
+set_property -name "statistics.ps7" -value "1" -objects $obj
+set_property -name "statistics.ps" -value "1" -objects $obj
+set_property -name "statistics.ps_static" -value "1" -objects $obj
+set_property -name "statistics.signals" -value "1" -objects $obj
+set_property -name "statistics.total_power" -value "1" -objects $obj
+set_property -name "statistics.transceiver" -value "1" -objects $obj
+set_property -name "statistics.xadc" -value "1" -objects $obj
+set_property -name "view.orientation" -value "Horizontal" -objects $obj
+set_property -name "view.type" -value "Graph" -objects $obj
+
+# Create 'timing_1' gadget (if not found)
+if {[string equal [get_dashboard_gadgets  [ list "timing_1" ] ] ""]} {
+create_dashboard_gadget -name {timing_1} -type timing
+}
+set obj [get_dashboard_gadgets [ list "timing_1" ] ]
+set_property -name "active_reports" -value "" -objects $obj
+set_property -name "active_reports_invalid" -value "" -objects $obj
+set_property -name "active_run" -value "0" -objects $obj
+set_property -name "hide_unused_data" -value "1" -objects $obj
+set_property -name "incl_new_reports" -value "0" -objects $obj
+set_property -name "reports" -value "impl_1#impl_1_route_report_timing_summary_0" -objects $obj
+set_property -name "run.step" -value "route_design" -objects $obj
+set_property -name "run.type" -value "implementation" -objects $obj
+set_property -name "statistics.ths" -value "1" -objects $obj
+set_property -name "statistics.tns" -value "1" -objects $obj
+set_property -name "statistics.tpws" -value "1" -objects $obj
+set_property -name "statistics.whs" -value "1" -objects $obj
+set_property -name "statistics.wns" -value "1" -objects $obj
+set_property -name "view.orientation" -value "Horizontal" -objects $obj
+set_property -name "view.type" -value "Table" -objects $obj
+
+# Create 'utilization_1' gadget (if not found)
+if {[string equal [get_dashboard_gadgets  [ list "utilization_1" ] ] ""]} {
+create_dashboard_gadget -name {utilization_1} -type utilization
+}
+set obj [get_dashboard_gadgets [ list "utilization_1" ] ]
+set_property -name "active_reports" -value "" -objects $obj
+set_property -name "active_reports_invalid" -value "" -objects $obj
+set_property -name "active_run" -value "0" -objects $obj
+set_property -name "hide_unused_data" -value "1" -objects $obj
+set_property -name "incl_new_reports" -value "0" -objects $obj
+set_property -name "reports" -value "synth_1#synth_1_synth_report_utilization_0" -objects $obj
+set_property -name "run.step" -value "synth_design" -objects $obj
+set_property -name "run.type" -value "synthesis" -objects $obj
+set_property -name "statistics.bram" -value "1" -objects $obj
+set_property -name "statistics.bufg" -value "1" -objects $obj
+set_property -name "statistics.dsp" -value "1" -objects $obj
+set_property -name "statistics.ff" -value "1" -objects $obj
+set_property -name "statistics.gt" -value "1" -objects $obj
+set_property -name "statistics.io" -value "1" -objects $obj
+set_property -name "statistics.lut" -value "1" -objects $obj
+set_property -name "statistics.lutram" -value "1" -objects $obj
+set_property -name "statistics.mmcm" -value "1" -objects $obj
+set_property -name "statistics.pcie" -value "1" -objects $obj
+set_property -name "statistics.pll" -value "1" -objects $obj
+set_property -name "statistics.uram" -value "1" -objects $obj
+set_property -name "view.orientation" -value "Horizontal" -objects $obj
+set_property -name "view.type" -value "Graph" -objects $obj
+
+# Create 'utilization_2' gadget (if not found)
+if {[string equal [get_dashboard_gadgets  [ list "utilization_2" ] ] ""]} {
+create_dashboard_gadget -name {utilization_2} -type utilization
+}
+set obj [get_dashboard_gadgets [ list "utilization_2" ] ]
+set_property -name "active_reports" -value "" -objects $obj
+set_property -name "active_reports_invalid" -value "" -objects $obj
+set_property -name "active_run" -value "0" -objects $obj
+set_property -name "hide_unused_data" -value "1" -objects $obj
+set_property -name "incl_new_reports" -value "0" -objects $obj
+set_property -name "reports" -value "impl_1#impl_1_place_report_utilization_0" -objects $obj
+set_property -name "run.step" -value "place_design" -objects $obj
+set_property -name "run.type" -value "implementation" -objects $obj
+set_property -name "statistics.bram" -value "1" -objects $obj
+set_property -name "statistics.bufg" -value "1" -objects $obj
+set_property -name "statistics.dsp" -value "1" -objects $obj
+set_property -name "statistics.ff" -value "1" -objects $obj
+set_property -name "statistics.gt" -value "1" -objects $obj
+set_property -name "statistics.io" -value "1" -objects $obj
+set_property -name "statistics.lut" -value "1" -objects $obj
+set_property -name "statistics.lutram" -value "1" -objects $obj
+set_property -name "statistics.mmcm" -value "1" -objects $obj
+set_property -name "statistics.pcie" -value "1" -objects $obj
+set_property -name "statistics.pll" -value "1" -objects $obj
+set_property -name "statistics.uram" -value "1" -objects $obj
+set_property -name "view.orientation" -value "Horizontal" -objects $obj
+set_property -name "view.type" -value "Graph" -objects $obj
+
+move_dashboard_gadget -name {utilization_1} -row 0 -col 0
+move_dashboard_gadget -name {power_1} -row 1 -col 0
+move_dashboard_gadget -name {drc_1} -row 2 -col 0
+move_dashboard_gadget -name {timing_1} -row 0 -col 1
+move_dashboard_gadget -name {utilization_2} -row 1 -col 1
+move_dashboard_gadget -name {methodology_1} -row 2 -col 1

HDLForBeginners_Examples/30092022_testbench_start_finish/README.md

@@ -0,0 +1,29 @@
+
+
+This code is companion code for the video "Reading from and writing to file: My PDM testbench from start to finish"
+https://youtu.be/PGTaECnh7ZA
+
+
+To run this code, download and install Vivado 2021.1 or higher from here
+https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/vivado-design-tools/2021-1.html
+
+You need to register and fill in a form, but the download is free.
+
+Once installed, open and go to Tools -> Run Tcl Script
+
+Navigate to 30_sep_2022_testbench_start_finish.tcl in the same directory as this readme file.
+
+Once it is finished running, check for errors in the Tcl Console window tab on the bottom left.
+
+Click Simultion -> Run Simulation -> Run Behavioural Simulation on the left
+
+Select the module of interest in the "Scope" window, and the signals of interest in the "Objects" window, and drag accross to the simulation waveform viewer.
+
+Click the Play button (blue triangle button) to run the simulation.
+
+Folder breakdown:
+py: Python code
+src: synthesizable SystemVerilog code
+tb: testbench SystemVerilog code
+xdc: constraints
+ip: IP cores

HDLForBeginners_Examples/30092022_testbench_start_finish/ip/data_fifo/sim/data_fifo.v

@@ -0,0 +1,522 @@
+// (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+// 
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+// 
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+// 
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+// 
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+// 
+// DO NOT MODIFY THIS FILE.
+
+
+// IP VLNV: xilinx.com:ip:fifo_generator:13.2
+// IP Revision: 5
+
+`timescale 1ns/1ps
+
+(* DowngradeIPIdentifiedWarnings = "yes" *)
+module data_fifo (
+  clk,
+  srst,
+  din,
+  wr_en,
+  rd_en,
+  dout,
+  full,
+  empty,
+  data_count
+);
+
+(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME core_clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0" *)
+(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 core_clk CLK" *)
+input wire clk;
+input wire srst;
+(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA" *)
+input wire [31 : 0] din;
+(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN" *)
+input wire wr_en;
+(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN" *)
+input wire rd_en;
+(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA" *)
+output wire [31 : 0] dout;
+(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL" *)
+output wire full;
+(* X_INTERFACE_INFO = "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY" *)
+output wire empty;
+output wire [11 : 0] data_count;
+
+  fifo_generator_v13_2_5 #(
+    .C_COMMON_CLOCK(1),
+    .C_SELECT_XPM(0),
+    .C_COUNT_TYPE(0),
+    .C_DATA_COUNT_WIDTH(12),
+    .C_DEFAULT_VALUE("BlankString"),
+    .C_DIN_WIDTH(32),
+    .C_DOUT_RST_VAL("0"),
+    .C_DOUT_WIDTH(32),
+    .C_ENABLE_RLOCS(0),
+    .C_FAMILY("artix7"),
+    .C_FULL_FLAGS_RST_VAL(0),
+    .C_HAS_ALMOST_EMPTY(0),
+    .C_HAS_ALMOST_FULL(0),
+    .C_HAS_BACKUP(0),
+    .C_HAS_DATA_COUNT(1),
+    .C_HAS_INT_CLK(0),
+    .C_HAS_MEMINIT_FILE(0),
+    .C_HAS_OVERFLOW(0),
+    .C_HAS_RD_DATA_COUNT(0),
+    .C_HAS_RD_RST(0),
+    .C_HAS_RST(0),
+    .C_HAS_SRST(1),
+    .C_HAS_UNDERFLOW(0),
+    .C_HAS_VALID(0),
+    .C_HAS_WR_ACK(0),
+    .C_HAS_WR_DATA_COUNT(0),
+    .C_HAS_WR_RST(0),
+    .C_IMPLEMENTATION_TYPE(0),
+    .C_INIT_WR_PNTR_VAL(0),
+    .C_MEMORY_TYPE(1),
+    .C_MIF_FILE_NAME("BlankString"),
+    .C_OPTIMIZATION_MODE(0),
+    .C_OVERFLOW_LOW(0),
+    .C_PRELOAD_LATENCY(0),
+    .C_PRELOAD_REGS(1),
+    .C_PRIM_FIFO_TYPE("2kx18"),
+    .C_PROG_EMPTY_THRESH_ASSERT_VAL(4),
+    .C_PROG_EMPTY_THRESH_NEGATE_VAL(5),
+    .C_PROG_EMPTY_TYPE(0),
+    .C_PROG_FULL_THRESH_ASSERT_VAL(2047),
+    .C_PROG_FULL_THRESH_NEGATE_VAL(2046),
+    .C_PROG_FULL_TYPE(0),
+    .C_RD_DATA_COUNT_WIDTH(12),
+    .C_RD_DEPTH(2048),
+    .C_RD_FREQ(1),
+    .C_RD_PNTR_WIDTH(11),
+    .C_UNDERFLOW_LOW(0),
+    .C_USE_DOUT_RST(1),
+    .C_USE_ECC(0),
+    .C_USE_EMBEDDED_REG(0),
+    .C_USE_PIPELINE_REG(0),
+    .C_POWER_SAVING_MODE(0),
+    .C_USE_FIFO16_FLAGS(0),
+    .C_USE_FWFT_DATA_COUNT(1),
+    .C_VALID_LOW(0),
+    .C_WR_ACK_LOW(0),
+    .C_WR_DATA_COUNT_WIDTH(12),
+    .C_WR_DEPTH(2048),
+    .C_WR_FREQ(1),
+    .C_WR_PNTR_WIDTH(11),
+    .C_WR_RESPONSE_LATENCY(1),
+    .C_MSGON_VAL(1),
+    .C_ENABLE_RST_SYNC(1),
+    .C_EN_SAFETY_CKT(0),
+    .C_ERROR_INJECTION_TYPE(0),
+    .C_SYNCHRONIZER_STAGE(2),
+    .C_INTERFACE_TYPE(0),
+    .C_AXI_TYPE(1),
+    .C_HAS_AXI_WR_CHANNEL(1),
+    .C_HAS_AXI_RD_CHANNEL(1),
+    .C_HAS_SLAVE_CE(0),
+    .C_HAS_MASTER_CE(0),
+    .C_ADD_NGC_CONSTRAINT(0),
+    .C_USE_COMMON_OVERFLOW(0),
+    .C_USE_COMMON_UNDERFLOW(0),
+    .C_USE_DEFAULT_SETTINGS(0),
+    .C_AXI_ID_WIDTH(1),
+    .C_AXI_ADDR_WIDTH(32),
+    .C_AXI_DATA_WIDTH(64),
+    .C_AXI_LEN_WIDTH(8),
+    .C_AXI_LOCK_WIDTH(1),
+    .C_HAS_AXI_ID(0),
+    .C_HAS_AXI_AWUSER(0),
+    .C_HAS_AXI_WUSER(0),
+    .C_HAS_AXI_BUSER(0),
+    .C_HAS_AXI_ARUSER(0),
+    .C_HAS_AXI_RUSER(0),
+    .C_AXI_ARUSER_WIDTH(1),
+    .C_AXI_AWUSER_WIDTH(1),
+    .C_AXI_WUSER_WIDTH(1),
+    .C_AXI_BUSER_WIDTH(1),
+    .C_AXI_RUSER_WIDTH(1),
+    .C_HAS_AXIS_TDATA(1),
+    .C_HAS_AXIS_TID(0),
+    .C_HAS_AXIS_TDEST(0),
+    .C_HAS_AXIS_TUSER(1),
+    .C_HAS_AXIS_TREADY(1),
+    .C_HAS_AXIS_TLAST(0),
+    .C_HAS_AXIS_TSTRB(0),
+    .C_HAS_AXIS_TKEEP(0),
+    .C_AXIS_TDATA_WIDTH(8),
+    .C_AXIS_TID_WIDTH(1),
+    .C_AXIS_TDEST_WIDTH(1),
+    .C_AXIS_TUSER_WIDTH(4),
+    .C_AXIS_TSTRB_WIDTH(1),
+    .C_AXIS_TKEEP_WIDTH(1),
+    .C_WACH_TYPE(0),
+    .C_WDCH_TYPE(0),
+    .C_WRCH_TYPE(0),
+    .C_RACH_TYPE(0),
+    .C_RDCH_TYPE(0),
+    .C_AXIS_TYPE(0),
+    .C_IMPLEMENTATION_TYPE_WACH(1),
+    .C_IMPLEMENTATION_TYPE_WDCH(1),
+    .C_IMPLEMENTATION_TYPE_WRCH(1),
+    .C_IMPLEMENTATION_TYPE_RACH(1),
+    .C_IMPLEMENTATION_TYPE_RDCH(1),
+    .C_IMPLEMENTATION_TYPE_AXIS(1),
+    .C_APPLICATION_TYPE_WACH(0),
+    .C_APPLICATION_TYPE_WDCH(0),
+    .C_APPLICATION_TYPE_WRCH(0),
+    .C_APPLICATION_TYPE_RACH(0),
+    .C_APPLICATION_TYPE_RDCH(0),
+    .C_APPLICATION_TYPE_AXIS(0),
+    .C_PRIM_FIFO_TYPE_WACH("512x36"),
+    .C_PRIM_FIFO_TYPE_WDCH("1kx36"),
+    .C_PRIM_FIFO_TYPE_WRCH("512x36"),
+    .C_PRIM_FIFO_TYPE_RACH("512x36"),
+    .C_PRIM_FIFO_TYPE_RDCH("1kx36"),
+    .C_PRIM_FIFO_TYPE_AXIS("1kx18"),
+    .C_USE_ECC_WACH(0),
+    .C_USE_ECC_WDCH(0),
+    .C_USE_ECC_WRCH(0),
+    .C_USE_ECC_RACH(0),
+    .C_USE_ECC_RDCH(0),
+    .C_USE_ECC_AXIS(0),
+    .C_ERROR_INJECTION_TYPE_WACH(0),
+    .C_ERROR_INJECTION_TYPE_WDCH(0),
+    .C_ERROR_INJECTION_TYPE_WRCH(0),
+    .C_ERROR_INJECTION_TYPE_RACH(0),
+    .C_ERROR_INJECTION_TYPE_RDCH(0),
+    .C_ERROR_INJECTION_TYPE_AXIS(0),
+    .C_DIN_WIDTH_WACH(1),
+    .C_DIN_WIDTH_WDCH(64),
+    .C_DIN_WIDTH_WRCH(2),
+    .C_DIN_WIDTH_RACH(32),
+    .C_DIN_WIDTH_RDCH(64),
+    .C_DIN_WIDTH_AXIS(1),
+    .C_WR_DEPTH_WACH(16),
+    .C_WR_DEPTH_WDCH(1024),
+    .C_WR_DEPTH_WRCH(16),
+    .C_WR_DEPTH_RACH(16),
+    .C_WR_DEPTH_RDCH(1024),
+    .C_WR_DEPTH_AXIS(1024),
+    .C_WR_PNTR_WIDTH_WACH(4),
+    .C_WR_PNTR_WIDTH_WDCH(10),
+    .C_WR_PNTR_WIDTH_WRCH(4),
+    .C_WR_PNTR_WIDTH_RACH(4),
+    .C_WR_PNTR_WIDTH_RDCH(10),
+    .C_WR_PNTR_WIDTH_AXIS(10),
+    .C_HAS_DATA_COUNTS_WACH(0),
+    .C_HAS_DATA_COUNTS_WDCH(0),
+    .C_HAS_DATA_COUNTS_WRCH(0),
+    .C_HAS_DATA_COUNTS_RACH(0),
+    .C_HAS_DATA_COUNTS_RDCH(0),
+    .C_HAS_DATA_COUNTS_AXIS(0),
+    .C_HAS_PROG_FLAGS_WACH(0),
+    .C_HAS_PROG_FLAGS_WDCH(0),
+    .C_HAS_PROG_FLAGS_WRCH(0),
+    .C_HAS_PROG_FLAGS_RACH(0),
+    .C_HAS_PROG_FLAGS_RDCH(0),
+    .C_HAS_PROG_FLAGS_AXIS(0),
+    .C_PROG_FULL_TYPE_WACH(0),
+    .C_PROG_FULL_TYPE_WDCH(0),
+    .C_PROG_FULL_TYPE_WRCH(0),
+    .C_PROG_FULL_TYPE_RACH(0),
+    .C_PROG_FULL_TYPE_RDCH(0),
+    .C_PROG_FULL_TYPE_AXIS(0),
+    .C_PROG_FULL_THRESH_ASSERT_VAL_WACH(1023),
+    .C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023),
+    .C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(1023),
+    .C_PROG_FULL_THRESH_ASSERT_VAL_RACH(1023),
+    .C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023),
+    .C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),
+    .C_PROG_EMPTY_TYPE_WACH(0),
+    .C_PROG_EMPTY_TYPE_WDCH(0),
+    .C_PROG_EMPTY_TYPE_WRCH(0),
+    .C_PROG_EMPTY_TYPE_RACH(0),
+    .C_PROG_EMPTY_TYPE_RDCH(0),
+    .C_PROG_EMPTY_TYPE_AXIS(0),
+    .C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(1022),
+    .C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1022),
+    .C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(1022),
+    .C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(1022),
+    .C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1022),
+    .C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022),
+    .C_REG_SLICE_MODE_WACH(0),
+    .C_REG_SLICE_MODE_WDCH(0),
+    .C_REG_SLICE_MODE_WRCH(0),
+    .C_REG_SLICE_MODE_RACH(0),
+    .C_REG_SLICE_MODE_RDCH(0),
+    .C_REG_SLICE_MODE_AXIS(0)
+  ) inst (
+    .backup(1'D0),
+    .backup_marker(1'D0),
+    .clk(clk),
+    .rst(1'D0),
+    .srst(srst),
+    .wr_clk(1'D0),
+    .wr_rst(1'D0),
+    .rd_clk(1'D0),
+    .rd_rst(1'D0),
+    .din(din),
+    .wr_en(wr_en),
+    .rd_en(rd_en),
+    .prog_empty_thresh(11'B0),
+    .prog_empty_thresh_assert(11'B0),
+    .prog_empty_thresh_negate(11'B0),
+    .prog_full_thresh(11'B0),
+    .prog_full_thresh_assert(11'B0),
+    .prog_full_thresh_negate(11'B0),
+    .int_clk(1'D0),
+    .injectdbiterr(1'D0),
+    .injectsbiterr(1'D0),
+    .sleep(1'D0),
+    .dout(dout),
+    .full(full),
+    .almost_full(),
+    .wr_ack(),
+    .overflow(),
+    .empty(empty),
+    .almost_empty(),
+    .valid(),
+    .underflow(),
+    .data_count(data_count),
+    .rd_data_count(),
+    .wr_data_count(),
+    .prog_full(),
+    .prog_empty(),
+    .sbiterr(),
+    .dbiterr(),
+    .wr_rst_busy(),
+    .rd_rst_busy(),
+    .m_aclk(1'D0),
+    .s_aclk(1'D0),
+    .s_aresetn(1'D0),
+    .m_aclk_en(1'D0),
+    .s_aclk_en(1'D0),
+    .s_axi_awid(1'B0),
+    .s_axi_awaddr(32'B0),
+    .s_axi_awlen(8'B0),
+    .s_axi_awsize(3'B0),
+    .s_axi_awburst(2'B0),
+    .s_axi_awlock(1'B0),
+    .s_axi_awcache(4'B0),
+    .s_axi_awprot(3'B0),
+    .s_axi_awqos(4'B0),
+    .s_axi_awregion(4'B0),
+    .s_axi_awuser(1'B0),
+    .s_axi_awvalid(1'D0),
+    .s_axi_awready(),
+    .s_axi_wid(1'B0),
+    .s_axi_wdata(64'B0),
+    .s_axi_wstrb(8'B0),
+    .s_axi_wlast(1'D0),
+    .s_axi_wuser(1'B0),
+    .s_axi_wvalid(1'D0),
+    .s_axi_wready(),
+    .s_axi_bid(),
+    .s_axi_bresp(),
+    .s_axi_buser(),
+    .s_axi_bvalid(),
+    .s_axi_bready(1'D0),
+    .m_axi_awid(),
+    .m_axi_awaddr(),
+    .m_axi_awlen(),
+    .m_axi_awsize(),
+    .m_axi_awburst(),
+    .m_axi_awlock(),
+    .m_axi_awcache(),
+    .m_axi_awprot(),
+    .m_axi_awqos(),
+    .m_axi_awregion(),
+    .m_axi_awuser(),
+    .m_axi_awvalid(),
+    .m_axi_awready(1'D0),
+    .m_axi_wid(),
+    .m_axi_wdata(),
+    .m_axi_wstrb(),
+    .m_axi_wlast(),
+    .m_axi_wuser(),
+    .m_axi_wvalid(),
+    .m_axi_wready(1'D0),
+    .m_axi_bid(1'B0),
+    .m_axi_bresp(2'B0),
+    .m_axi_buser(1'B0),
+    .m_axi_bvalid(1'D0),
+    .m_axi_bready(),
+    .s_axi_arid(1'B0),
+    .s_axi_araddr(32'B0),
+    .s_axi_arlen(8'B0),
+    .s_axi_arsize(3'B0),
+    .s_axi_arburst(2'B0),
+    .s_axi_arlock(1'B0),
+    .s_axi_arcache(4'B0),
+    .s_axi_arprot(3'B0),
+    .s_axi_arqos(4'B0),
+    .s_axi_arregion(4'B0),
+    .s_axi_aruser(1'B0),
+    .s_axi_arvalid(1'D0),
+    .s_axi_arready(),
+    .s_axi_rid(),
+    .s_axi_rdata(),
+    .s_axi_rresp(),
+    .s_axi_rlast(),
+    .s_axi_ruser(),
+    .s_axi_rvalid(),
+    .s_axi_rready(1'D0),
+    .m_axi_arid(),
+    .m_axi_araddr(),
+    .m_axi_arlen(),
+    .m_axi_arsize(),
+    .m_axi_arburst(),
+    .m_axi_arlock(),
+    .m_axi_arcache(),
+    .m_axi_arprot(),
+    .m_axi_arqos(),
+    .m_axi_arregion(),
+    .m_axi_aruser(),
+    .m_axi_arvalid(),
+    .m_axi_arready(1'D0),
+    .m_axi_rid(1'B0),
+    .m_axi_rdata(64'B0),
+    .m_axi_rresp(2'B0),
+    .m_axi_rlast(1'D0),
+    .m_axi_ruser(1'B0),
+    .m_axi_rvalid(1'D0),
+    .m_axi_rready(),
+    .s_axis_tvalid(1'D0),
+    .s_axis_tready(),
+    .s_axis_tdata(8'B0),
+    .s_axis_tstrb(1'B0),
+    .s_axis_tkeep(1'B0),
+    .s_axis_tlast(1'D0),
+    .s_axis_tid(1'B0),
+    .s_axis_tdest(1'B0),
+    .s_axis_tuser(4'B0),
+    .m_axis_tvalid(),
+    .m_axis_tready(1'D0),
+    .m_axis_tdata(),
+    .m_axis_tstrb(),
+    .m_axis_tkeep(),
+    .m_axis_tlast(),
+    .m_axis_tid(),
+    .m_axis_tdest(),
+    .m_axis_tuser(),
+    .axi_aw_injectsbiterr(1'D0),
+    .axi_aw_injectdbiterr(1'D0),
+    .axi_aw_prog_full_thresh(4'B0),
+    .axi_aw_prog_empty_thresh(4'B0),
+    .axi_aw_data_count(),
+    .axi_aw_wr_data_count(),
+    .axi_aw_rd_data_count(),
+    .axi_aw_sbiterr(),
+    .axi_aw_dbiterr(),
+    .axi_aw_overflow(),
+    .axi_aw_underflow(),
+    .axi_aw_prog_full(),
+    .axi_aw_prog_empty(),
+    .axi_w_injectsbiterr(1'D0),
+    .axi_w_injectdbiterr(1'D0),
+    .axi_w_prog_full_thresh(10'B0),
+    .axi_w_prog_empty_thresh(10'B0),
+    .axi_w_data_count(),
+    .axi_w_wr_data_count(),
+    .axi_w_rd_data_count(),
+    .axi_w_sbiterr(),
+    .axi_w_dbiterr(),
+    .axi_w_overflow(),
+    .axi_w_underflow(),
+    .axi_w_prog_full(),
+    .axi_w_prog_empty(),
+    .axi_b_injectsbiterr(1'D0),
+    .axi_b_injectdbiterr(1'D0),
+    .axi_b_prog_full_thresh(4'B0),
+    .axi_b_prog_empty_thresh(4'B0),
+    .axi_b_data_count(),
+    .axi_b_wr_data_count(),
+    .axi_b_rd_data_count(),
+    .axi_b_sbiterr(),
+    .axi_b_dbiterr(),
+    .axi_b_overflow(),
+    .axi_b_underflow(),
+    .axi_b_prog_full(),
+    .axi_b_prog_empty(),
+    .axi_ar_injectsbiterr(1'D0),
+    .axi_ar_injectdbiterr(1'D0),
+    .axi_ar_prog_full_thresh(4'B0),
+    .axi_ar_prog_empty_thresh(4'B0),
+    .axi_ar_data_count(),
+    .axi_ar_wr_data_count(),
+    .axi_ar_rd_data_count(),
+    .axi_ar_sbiterr(),
+    .axi_ar_dbiterr(),
+    .axi_ar_overflow(),
+    .axi_ar_underflow(),
+    .axi_ar_prog_full(),
+    .axi_ar_prog_empty(),
+    .axi_r_injectsbiterr(1'D0),
+    .axi_r_injectdbiterr(1'D0),
+    .axi_r_prog_full_thresh(10'B0),
+    .axi_r_prog_empty_thresh(10'B0),
+    .axi_r_data_count(),
+    .axi_r_wr_data_count(),
+    .axi_r_rd_data_count(),
+    .axi_r_sbiterr(),
+    .axi_r_dbiterr(),
+    .axi_r_overflow(),
+    .axi_r_underflow(),
+    .axi_r_prog_full(),
+    .axi_r_prog_empty(),
+    .axis_injectsbiterr(1'D0),
+    .axis_injectdbiterr(1'D0),
+    .axis_prog_full_thresh(10'B0),
+    .axis_prog_empty_thresh(10'B0),
+    .axis_data_count(),
+    .axis_wr_data_count(),
+    .axis_rd_data_count(),
+    .axis_sbiterr(),
+    .axis_dbiterr(),
+    .axis_overflow(),
+    .axis_underflow(),
+    .axis_prog_full(),
+    .axis_prog_empty()
+  );
+endmodule

HDLForBeginners_Examples/30092022_testbench_start_finish/ip/data_fifo/synth/data_fifo.vhd

@@ -0,0 +1,857 @@
+-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:ip:fifo_generator:13.2
+-- IP Revision: 5
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+LIBRARY fifo_generator_v13_2_5;
+USE fifo_generator_v13_2_5.fifo_generator_v13_2_5;
+
+ENTITY data_fifo IS
+  PORT (
+    clk : IN STD_LOGIC;
+    srst : IN STD_LOGIC;
+    din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+    wr_en : IN STD_LOGIC;
+    rd_en : IN STD_LOGIC;
+    dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+    full : OUT STD_LOGIC;
+    empty : OUT STD_LOGIC;
+    data_count : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
+  );
+END data_fifo;
+
+ARCHITECTURE data_fifo_arch OF data_fifo IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF data_fifo_arch: ARCHITECTURE IS "yes";
+  COMPONENT fifo_generator_v13_2_5 IS
+    GENERIC (
+      C_COMMON_CLOCK : INTEGER;
+      C_SELECT_XPM : INTEGER;
+      C_COUNT_TYPE : INTEGER;
+      C_DATA_COUNT_WIDTH : INTEGER;
+      C_DEFAULT_VALUE : STRING;
+      C_DIN_WIDTH : INTEGER;
+      C_DOUT_RST_VAL : STRING;
+      C_DOUT_WIDTH : INTEGER;
+      C_ENABLE_RLOCS : INTEGER;
+      C_FAMILY : STRING;
+      C_FULL_FLAGS_RST_VAL : INTEGER;
+      C_HAS_ALMOST_EMPTY : INTEGER;
+      C_HAS_ALMOST_FULL : INTEGER;
+      C_HAS_BACKUP : INTEGER;
+      C_HAS_DATA_COUNT : INTEGER;
+      C_HAS_INT_CLK : INTEGER;
+      C_HAS_MEMINIT_FILE : INTEGER;
+      C_HAS_OVERFLOW : INTEGER;
+      C_HAS_RD_DATA_COUNT : INTEGER;
+      C_HAS_RD_RST : INTEGER;
+      C_HAS_RST : INTEGER;
+      C_HAS_SRST : INTEGER;
+      C_HAS_UNDERFLOW : INTEGER;
+      C_HAS_VALID : INTEGER;
+      C_HAS_WR_ACK : INTEGER;
+      C_HAS_WR_DATA_COUNT : INTEGER;
+      C_HAS_WR_RST : INTEGER;
+      C_IMPLEMENTATION_TYPE : INTEGER;
+      C_INIT_WR_PNTR_VAL : INTEGER;
+      C_MEMORY_TYPE : INTEGER;
+      C_MIF_FILE_NAME : STRING;
+      C_OPTIMIZATION_MODE : INTEGER;
+      C_OVERFLOW_LOW : INTEGER;
+      C_PRELOAD_LATENCY : INTEGER;
+      C_PRELOAD_REGS : INTEGER;
+      C_PRIM_FIFO_TYPE : STRING;
+      C_PROG_EMPTY_THRESH_ASSERT_VAL : INTEGER;
+      C_PROG_EMPTY_THRESH_NEGATE_VAL : INTEGER;
+      C_PROG_EMPTY_TYPE : INTEGER;
+      C_PROG_FULL_THRESH_ASSERT_VAL : INTEGER;
+      C_PROG_FULL_THRESH_NEGATE_VAL : INTEGER;
+      C_PROG_FULL_TYPE : INTEGER;
+      C_RD_DATA_COUNT_WIDTH : INTEGER;
+      C_RD_DEPTH : INTEGER;
+      C_RD_FREQ : INTEGER;
+      C_RD_PNTR_WIDTH : INTEGER;
+      C_UNDERFLOW_LOW : INTEGER;
+      C_USE_DOUT_RST : INTEGER;
+      C_USE_ECC : INTEGER;
+      C_USE_EMBEDDED_REG : INTEGER;
+      C_USE_PIPELINE_REG : INTEGER;
+      C_POWER_SAVING_MODE : INTEGER;
+      C_USE_FIFO16_FLAGS : INTEGER;
+      C_USE_FWFT_DATA_COUNT : INTEGER;
+      C_VALID_LOW : INTEGER;
+      C_WR_ACK_LOW : INTEGER;
+      C_WR_DATA_COUNT_WIDTH : INTEGER;
+      C_WR_DEPTH : INTEGER;
+      C_WR_FREQ : INTEGER;
+      C_WR_PNTR_WIDTH : INTEGER;
+      C_WR_RESPONSE_LATENCY : INTEGER;
+      C_MSGON_VAL : INTEGER;
+      C_ENABLE_RST_SYNC : INTEGER;
+      C_EN_SAFETY_CKT : INTEGER;
+      C_ERROR_INJECTION_TYPE : INTEGER;
+      C_SYNCHRONIZER_STAGE : INTEGER;
+      C_INTERFACE_TYPE : INTEGER;
+      C_AXI_TYPE : INTEGER;
+      C_HAS_AXI_WR_CHANNEL : INTEGER;
+      C_HAS_AXI_RD_CHANNEL : INTEGER;
+      C_HAS_SLAVE_CE : INTEGER;
+      C_HAS_MASTER_CE : INTEGER;
+      C_ADD_NGC_CONSTRAINT : INTEGER;
+      C_USE_COMMON_OVERFLOW : INTEGER;
+      C_USE_COMMON_UNDERFLOW : INTEGER;
+      C_USE_DEFAULT_SETTINGS : INTEGER;
+      C_AXI_ID_WIDTH : INTEGER;
+      C_AXI_ADDR_WIDTH : INTEGER;
+      C_AXI_DATA_WIDTH : INTEGER;
+      C_AXI_LEN_WIDTH : INTEGER;
+      C_AXI_LOCK_WIDTH : INTEGER;
+      C_HAS_AXI_ID : INTEGER;
+      C_HAS_AXI_AWUSER : INTEGER;
+      C_HAS_AXI_WUSER : INTEGER;
+      C_HAS_AXI_BUSER : INTEGER;
+      C_HAS_AXI_ARUSER : INTEGER;
+      C_HAS_AXI_RUSER : INTEGER;
+      C_AXI_ARUSER_WIDTH : INTEGER;
+      C_AXI_AWUSER_WIDTH : INTEGER;
+      C_AXI_WUSER_WIDTH : INTEGER;
+      C_AXI_BUSER_WIDTH : INTEGER;
+      C_AXI_RUSER_WIDTH : INTEGER;
+      C_HAS_AXIS_TDATA : INTEGER;
+      C_HAS_AXIS_TID : INTEGER;
+      C_HAS_AXIS_TDEST : INTEGER;
+      C_HAS_AXIS_TUSER : INTEGER;
+      C_HAS_AXIS_TREADY : INTEGER;
+      C_HAS_AXIS_TLAST : INTEGER;
+      C_HAS_AXIS_TSTRB : INTEGER;
+      C_HAS_AXIS_TKEEP : INTEGER;
+      C_AXIS_TDATA_WIDTH : INTEGER;
+      C_AXIS_TID_WIDTH : INTEGER;
+      C_AXIS_TDEST_WIDTH : INTEGER;
+      C_AXIS_TUSER_WIDTH : INTEGER;
+      C_AXIS_TSTRB_WIDTH : INTEGER;
+      C_AXIS_TKEEP_WIDTH : INTEGER;
+      C_WACH_TYPE : INTEGER;
+      C_WDCH_TYPE : INTEGER;
+      C_WRCH_TYPE : INTEGER;
+      C_RACH_TYPE : INTEGER;
+      C_RDCH_TYPE : INTEGER;
+      C_AXIS_TYPE : INTEGER;
+      C_IMPLEMENTATION_TYPE_WACH : INTEGER;
+      C_IMPLEMENTATION_TYPE_WDCH : INTEGER;
+      C_IMPLEMENTATION_TYPE_WRCH : INTEGER;
+      C_IMPLEMENTATION_TYPE_RACH : INTEGER;
+      C_IMPLEMENTATION_TYPE_RDCH : INTEGER;
+      C_IMPLEMENTATION_TYPE_AXIS : INTEGER;
+      C_APPLICATION_TYPE_WACH : INTEGER;
+      C_APPLICATION_TYPE_WDCH : INTEGER;
+      C_APPLICATION_TYPE_WRCH : INTEGER;
+      C_APPLICATION_TYPE_RACH : INTEGER;
+      C_APPLICATION_TYPE_RDCH : INTEGER;
+      C_APPLICATION_TYPE_AXIS : INTEGER;
+      C_PRIM_FIFO_TYPE_WACH : STRING;
+      C_PRIM_FIFO_TYPE_WDCH : STRING;
+      C_PRIM_FIFO_TYPE_WRCH : STRING;
+      C_PRIM_FIFO_TYPE_RACH : STRING;
+      C_PRIM_FIFO_TYPE_RDCH : STRING;
+      C_PRIM_FIFO_TYPE_AXIS : STRING;
+      C_USE_ECC_WACH : INTEGER;
+      C_USE_ECC_WDCH : INTEGER;
+      C_USE_ECC_WRCH : INTEGER;
+      C_USE_ECC_RACH : INTEGER;
+      C_USE_ECC_RDCH : INTEGER;
+      C_USE_ECC_AXIS : INTEGER;
+      C_ERROR_INJECTION_TYPE_WACH : INTEGER;
+      C_ERROR_INJECTION_TYPE_WDCH : INTEGER;
+      C_ERROR_INJECTION_TYPE_WRCH : INTEGER;
+      C_ERROR_INJECTION_TYPE_RACH : INTEGER;
+      C_ERROR_INJECTION_TYPE_RDCH : INTEGER;
+      C_ERROR_INJECTION_TYPE_AXIS : INTEGER;
+      C_DIN_WIDTH_WACH : INTEGER;
+      C_DIN_WIDTH_WDCH : INTEGER;
+      C_DIN_WIDTH_WRCH : INTEGER;
+      C_DIN_WIDTH_RACH : INTEGER;
+      C_DIN_WIDTH_RDCH : INTEGER;
+      C_DIN_WIDTH_AXIS : INTEGER;
+      C_WR_DEPTH_WACH : INTEGER;
+      C_WR_DEPTH_WDCH : INTEGER;
+      C_WR_DEPTH_WRCH : INTEGER;
+      C_WR_DEPTH_RACH : INTEGER;
+      C_WR_DEPTH_RDCH : INTEGER;
+      C_WR_DEPTH_AXIS : INTEGER;
+      C_WR_PNTR_WIDTH_WACH : INTEGER;
+      C_WR_PNTR_WIDTH_WDCH : INTEGER;
+      C_WR_PNTR_WIDTH_WRCH : INTEGER;
+      C_WR_PNTR_WIDTH_RACH : INTEGER;
+      C_WR_PNTR_WIDTH_RDCH : INTEGER;
+      C_WR_PNTR_WIDTH_AXIS : INTEGER;
+      C_HAS_DATA_COUNTS_WACH : INTEGER;
+      C_HAS_DATA_COUNTS_WDCH : INTEGER;
+      C_HAS_DATA_COUNTS_WRCH : INTEGER;
+      C_HAS_DATA_COUNTS_RACH : INTEGER;
+      C_HAS_DATA_COUNTS_RDCH : INTEGER;
+      C_HAS_DATA_COUNTS_AXIS : INTEGER;
+      C_HAS_PROG_FLAGS_WACH : INTEGER;
+      C_HAS_PROG_FLAGS_WDCH : INTEGER;
+      C_HAS_PROG_FLAGS_WRCH : INTEGER;
+      C_HAS_PROG_FLAGS_RACH : INTEGER;
+      C_HAS_PROG_FLAGS_RDCH : INTEGER;
+      C_HAS_PROG_FLAGS_AXIS : INTEGER;
+      C_PROG_FULL_TYPE_WACH : INTEGER;
+      C_PROG_FULL_TYPE_WDCH : INTEGER;
+      C_PROG_FULL_TYPE_WRCH : INTEGER;
+      C_PROG_FULL_TYPE_RACH : INTEGER;
+      C_PROG_FULL_TYPE_RDCH : INTEGER;
+      C_PROG_FULL_TYPE_AXIS : INTEGER;
+      C_PROG_FULL_THRESH_ASSERT_VAL_WACH : INTEGER;
+      C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : INTEGER;
+      C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : INTEGER;
+      C_PROG_FULL_THRESH_ASSERT_VAL_RACH : INTEGER;
+      C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : INTEGER;
+      C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : INTEGER;
+      C_PROG_EMPTY_TYPE_WACH : INTEGER;
+      C_PROG_EMPTY_TYPE_WDCH : INTEGER;
+      C_PROG_EMPTY_TYPE_WRCH : INTEGER;
+      C_PROG_EMPTY_TYPE_RACH : INTEGER;
+      C_PROG_EMPTY_TYPE_RDCH : INTEGER;
+      C_PROG_EMPTY_TYPE_AXIS : INTEGER;
+      C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : INTEGER;
+      C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : INTEGER;
+      C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : INTEGER;
+      C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : INTEGER;
+      C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : INTEGER;
+      C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : INTEGER;
+      C_REG_SLICE_MODE_WACH : INTEGER;
+      C_REG_SLICE_MODE_WDCH : INTEGER;
+      C_REG_SLICE_MODE_WRCH : INTEGER;
+      C_REG_SLICE_MODE_RACH : INTEGER;
+      C_REG_SLICE_MODE_RDCH : INTEGER;
+      C_REG_SLICE_MODE_AXIS : INTEGER
+    );
+    PORT (
+      backup : IN STD_LOGIC;
+      backup_marker : IN STD_LOGIC;
+      clk : IN STD_LOGIC;
+      rst : IN STD_LOGIC;
+      srst : IN STD_LOGIC;
+      wr_clk : IN STD_LOGIC;
+      wr_rst : IN STD_LOGIC;
+      rd_clk : IN STD_LOGIC;
+      rd_rst : IN STD_LOGIC;
+      din : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      wr_en : IN STD_LOGIC;
+      rd_en : IN STD_LOGIC;
+      prog_empty_thresh : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
+      prog_empty_thresh_assert : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
+      prog_empty_thresh_negate : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
+      prog_full_thresh : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
+      prog_full_thresh_assert : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
+      prog_full_thresh_negate : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
+      int_clk : IN STD_LOGIC;
+      injectdbiterr : IN STD_LOGIC;
+      injectsbiterr : IN STD_LOGIC;
+      sleep : IN STD_LOGIC;
+      dout : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+      full : OUT STD_LOGIC;
+      almost_full : OUT STD_LOGIC;
+      wr_ack : OUT STD_LOGIC;
+      overflow : OUT STD_LOGIC;
+      empty : OUT STD_LOGIC;
+      almost_empty : OUT STD_LOGIC;
+      valid : OUT STD_LOGIC;
+      underflow : OUT STD_LOGIC;
+      data_count : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
+      rd_data_count : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
+      wr_data_count : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
+      prog_full : OUT STD_LOGIC;
+      prog_empty : OUT STD_LOGIC;
+      sbiterr : OUT STD_LOGIC;
+      dbiterr : OUT STD_LOGIC;
+      wr_rst_busy : OUT STD_LOGIC;
+      rd_rst_busy : OUT STD_LOGIC;
+      m_aclk : IN STD_LOGIC;
+      s_aclk : IN STD_LOGIC;
+      s_aresetn : IN STD_LOGIC;
+      m_aclk_en : IN STD_LOGIC;
+      s_aclk_en : IN STD_LOGIC;
+      s_axi_awid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+      s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+      s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
+      s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+      s_axi_awlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+      s_axi_awcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+      s_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
+      s_axi_awqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+      s_axi_awregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+      s_axi_awuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+      s_axi_awvalid : IN STD_LOGIC;
+      s_axi_awready : OUT STD_LOGIC;
+      s_axi_wid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+      s_axi_wdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
+      s_axi_wstrb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+      s_axi_wlast : IN STD_LOGIC;
+      s_axi_wuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+      s_axi_wvalid : IN STD_LOGIC;
+      s_axi_wready : OUT STD_LOGIC;
+      s_axi_bid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+      s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+      s_axi_buser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+      s_axi_bvalid : OUT STD_LOGIC;
+      s_axi_bready : IN STD_LOGIC;
+      m_axi_awid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+      m_axi_awaddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+      m_axi_awlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+      m_axi_awsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
+      m_axi_awburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+      m_axi_awlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+      m_axi_awcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+      m_axi_awprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
+      m_axi_awqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+      m_axi_awregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+      m_axi_awuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+      m_axi_awvalid : OUT STD_LOGIC;
+      m_axi_awready : IN STD_LOGIC;
+      m_axi_wid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+      m_axi_wdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
+      m_axi_wstrb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+      m_axi_wlast : OUT STD_LOGIC;
+      m_axi_wuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+      m_axi_wvalid : OUT STD_LOGIC;
+      m_axi_wready : IN STD_LOGIC;
+      m_axi_bid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+      m_axi_bresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+      m_axi_buser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+      m_axi_bvalid : IN STD_LOGIC;
+      m_axi_bready : OUT STD_LOGIC;
+      s_axi_arid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+      s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+      s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+      s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
+      s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+      s_axi_arlock : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+      s_axi_arcache : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+      s_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
+      s_axi_arqos : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+      s_axi_arregion : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+      s_axi_aruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+      s_axi_arvalid : IN STD_LOGIC;
+      s_axi_arready : OUT STD_LOGIC;
+      s_axi_rid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+      s_axi_rdata : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
+      s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+      s_axi_rlast : OUT STD_LOGIC;
+      s_axi_ruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+      s_axi_rvalid : OUT STD_LOGIC;
+      s_axi_rready : IN STD_LOGIC;
+      m_axi_arid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+      m_axi_araddr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+      m_axi_arlen : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+      m_axi_arsize : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
+      m_axi_arburst : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+      m_axi_arlock : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+      m_axi_arcache : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+      m_axi_arprot : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
+      m_axi_arqos : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+      m_axi_arregion : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+      m_axi_aruser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+      m_axi_arvalid : OUT STD_LOGIC;
+      m_axi_arready : IN STD_LOGIC;
+      m_axi_rid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+      m_axi_rdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
+      m_axi_rresp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+      m_axi_rlast : IN STD_LOGIC;
+      m_axi_ruser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+      m_axi_rvalid : IN STD_LOGIC;
+      m_axi_rready : OUT STD_LOGIC;
+      s_axis_tvalid : IN STD_LOGIC;
+      s_axis_tready : OUT STD_LOGIC;
+      s_axis_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+      s_axis_tstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+      s_axis_tkeep : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+      s_axis_tlast : IN STD_LOGIC;
+      s_axis_tid : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+      s_axis_tdest : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+      s_axis_tuser : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+      m_axis_tvalid : OUT STD_LOGIC;
+      m_axis_tready : IN STD_LOGIC;
+      m_axis_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+      m_axis_tstrb : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+      m_axis_tkeep : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+      m_axis_tlast : OUT STD_LOGIC;
+      m_axis_tid : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+      m_axis_tdest : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+      m_axis_tuser : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+      axi_aw_injectsbiterr : IN STD_LOGIC;
+      axi_aw_injectdbiterr : IN STD_LOGIC;
+      axi_aw_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+      axi_aw_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+      axi_aw_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
+      axi_aw_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
+      axi_aw_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
+      axi_aw_sbiterr : OUT STD_LOGIC;
+      axi_aw_dbiterr : OUT STD_LOGIC;
+      axi_aw_overflow : OUT STD_LOGIC;
+      axi_aw_underflow : OUT STD_LOGIC;
+      axi_aw_prog_full : OUT STD_LOGIC;
+      axi_aw_prog_empty : OUT STD_LOGIC;
+      axi_w_injectsbiterr : IN STD_LOGIC;
+      axi_w_injectdbiterr : IN STD_LOGIC;
+      axi_w_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
+      axi_w_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
+      axi_w_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
+      axi_w_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
+      axi_w_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
+      axi_w_sbiterr : OUT STD_LOGIC;
+      axi_w_dbiterr : OUT STD_LOGIC;
+      axi_w_overflow : OUT STD_LOGIC;
+      axi_w_underflow : OUT STD_LOGIC;
+      axi_w_prog_full : OUT STD_LOGIC;
+      axi_w_prog_empty : OUT STD_LOGIC;
+      axi_b_injectsbiterr : IN STD_LOGIC;
+      axi_b_injectdbiterr : IN STD_LOGIC;
+      axi_b_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+      axi_b_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+      axi_b_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
+      axi_b_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
+      axi_b_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
+      axi_b_sbiterr : OUT STD_LOGIC;
+      axi_b_dbiterr : OUT STD_LOGIC;
+      axi_b_overflow : OUT STD_LOGIC;
+      axi_b_underflow : OUT STD_LOGIC;
+      axi_b_prog_full : OUT STD_LOGIC;
+      axi_b_prog_empty : OUT STD_LOGIC;
+      axi_ar_injectsbiterr : IN STD_LOGIC;
+      axi_ar_injectdbiterr : IN STD_LOGIC;
+      axi_ar_prog_full_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+      axi_ar_prog_empty_thresh : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+      axi_ar_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
+      axi_ar_wr_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
+      axi_ar_rd_data_count : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
+      axi_ar_sbiterr : OUT STD_LOGIC;
+      axi_ar_dbiterr : OUT STD_LOGIC;
+      axi_ar_overflow : OUT STD_LOGIC;
+      axi_ar_underflow : OUT STD_LOGIC;
+      axi_ar_prog_full : OUT STD_LOGIC;
+      axi_ar_prog_empty : OUT STD_LOGIC;
+      axi_r_injectsbiterr : IN STD_LOGIC;
+      axi_r_injectdbiterr : IN STD_LOGIC;
+      axi_r_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
+      axi_r_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
+      axi_r_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
+      axi_r_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
+      axi_r_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
+      axi_r_sbiterr : OUT STD_LOGIC;
+      axi_r_dbiterr : OUT STD_LOGIC;
+      axi_r_overflow : OUT STD_LOGIC;
+      axi_r_underflow : OUT STD_LOGIC;
+      axi_r_prog_full : OUT STD_LOGIC;
+      axi_r_prog_empty : OUT STD_LOGIC;
+      axis_injectsbiterr : IN STD_LOGIC;
+      axis_injectdbiterr : IN STD_LOGIC;
+      axis_prog_full_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
+      axis_prog_empty_thresh : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
+      axis_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
+      axis_wr_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
+      axis_rd_data_count : OUT STD_LOGIC_VECTOR(10 DOWNTO 0);
+      axis_sbiterr : OUT STD_LOGIC;
+      axis_dbiterr : OUT STD_LOGIC;
+      axis_overflow : OUT STD_LOGIC;
+      axis_underflow : OUT STD_LOGIC;
+      axis_prog_full : OUT STD_LOGIC;
+      axis_prog_empty : OUT STD_LOGIC
+    );
+  END COMPONENT fifo_generator_v13_2_5;
+  ATTRIBUTE X_CORE_INFO : STRING;
+  ATTRIBUTE X_CORE_INFO OF data_fifo_arch: ARCHITECTURE IS "fifo_generator_v13_2_5,Vivado 2021.1";
+  ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
+  ATTRIBUTE CHECK_LICENSE_TYPE OF data_fifo_arch : ARCHITECTURE IS "data_fifo,fifo_generator_v13_2_5,{}";
+  ATTRIBUTE CORE_GENERATION_INFO : STRING;
+  ATTRIBUTE CORE_GENERATION_INFO OF data_fifo_arch: ARCHITECTURE IS "data_fifo,fifo_generator_v13_2_5,{x_ipProduct=Vivado 2021.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=fifo_generator,x_ipVersion=13.2,x_ipCoreRevision=5,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_COMMON_CLOCK=1,C_SELECT_XPM=0,C_COUNT_TYPE=0,C_DATA_COUNT_WIDTH=12,C_DEFAULT_VALUE=BlankString,C_DIN_WIDTH=32,C_DOUT_RST_VAL=0,C_DOUT_WIDTH=32,C_ENABLE_RLOCS=0,C_FAMILY=artix7,C_FULL_FLAGS_RST_VAL=0,C_HAS_ALMOST_EMPTY=0,C_HAS_ALMOST_FULL=0,C_HAS_BACKUP=0,C_HAS_DATA_COUNT=1,C_HAS_INT_CLK=0,C_HAS_ME" & 
+"MINIT_FILE=0,C_HAS_OVERFLOW=0,C_HAS_RD_DATA_COUNT=0,C_HAS_RD_RST=0,C_HAS_RST=0,C_HAS_SRST=1,C_HAS_UNDERFLOW=0,C_HAS_VALID=0,C_HAS_WR_ACK=0,C_HAS_WR_DATA_COUNT=0,C_HAS_WR_RST=0,C_IMPLEMENTATION_TYPE=0,C_INIT_WR_PNTR_VAL=0,C_MEMORY_TYPE=1,C_MIF_FILE_NAME=BlankString,C_OPTIMIZATION_MODE=0,C_OVERFLOW_LOW=0,C_PRELOAD_LATENCY=0,C_PRELOAD_REGS=1,C_PRIM_FIFO_TYPE=2kx18,C_PROG_EMPTY_THRESH_ASSERT_VAL=4,C_PROG_EMPTY_THRESH_NEGATE_VAL=5,C_PROG_EMPTY_TYPE=0,C_PROG_FULL_THRESH_ASSERT_VAL=2047,C_PROG_FULL_THR" & 
+"ESH_NEGATE_VAL=2046,C_PROG_FULL_TYPE=0,C_RD_DATA_COUNT_WIDTH=12,C_RD_DEPTH=2048,C_RD_FREQ=1,C_RD_PNTR_WIDTH=11,C_UNDERFLOW_LOW=0,C_USE_DOUT_RST=1,C_USE_ECC=0,C_USE_EMBEDDED_REG=0,C_USE_PIPELINE_REG=0,C_POWER_SAVING_MODE=0,C_USE_FIFO16_FLAGS=0,C_USE_FWFT_DATA_COUNT=1,C_VALID_LOW=0,C_WR_ACK_LOW=0,C_WR_DATA_COUNT_WIDTH=12,C_WR_DEPTH=2048,C_WR_FREQ=1,C_WR_PNTR_WIDTH=11,C_WR_RESPONSE_LATENCY=1,C_MSGON_VAL=1,C_ENABLE_RST_SYNC=1,C_EN_SAFETY_CKT=0,C_ERROR_INJECTION_TYPE=0,C_SYNCHRONIZER_STAGE=2,C_INTERF" & 
+"ACE_TYPE=0,C_AXI_TYPE=1,C_HAS_AXI_WR_CHANNEL=1,C_HAS_AXI_RD_CHANNEL=1,C_HAS_SLAVE_CE=0,C_HAS_MASTER_CE=0,C_ADD_NGC_CONSTRAINT=0,C_USE_COMMON_OVERFLOW=0,C_USE_COMMON_UNDERFLOW=0,C_USE_DEFAULT_SETTINGS=0,C_AXI_ID_WIDTH=1,C_AXI_ADDR_WIDTH=32,C_AXI_DATA_WIDTH=64,C_AXI_LEN_WIDTH=8,C_AXI_LOCK_WIDTH=1,C_HAS_AXI_ID=0,C_HAS_AXI_AWUSER=0,C_HAS_AXI_WUSER=0,C_HAS_AXI_BUSER=0,C_HAS_AXI_ARUSER=0,C_HAS_AXI_RUSER=0,C_AXI_ARUSER_WIDTH=1,C_AXI_AWUSER_WIDTH=1,C_AXI_WUSER_WIDTH=1,C_AXI_BUSER_WIDTH=1,C_AXI_RUSER_WID" & 
+"TH=1,C_HAS_AXIS_TDATA=1,C_HAS_AXIS_TID=0,C_HAS_AXIS_TDEST=0,C_HAS_AXIS_TUSER=1,C_HAS_AXIS_TREADY=1,C_HAS_AXIS_TLAST=0,C_HAS_AXIS_TSTRB=0,C_HAS_AXIS_TKEEP=0,C_AXIS_TDATA_WIDTH=8,C_AXIS_TID_WIDTH=1,C_AXIS_TDEST_WIDTH=1,C_AXIS_TUSER_WIDTH=4,C_AXIS_TSTRB_WIDTH=1,C_AXIS_TKEEP_WIDTH=1,C_WACH_TYPE=0,C_WDCH_TYPE=0,C_WRCH_TYPE=0,C_RACH_TYPE=0,C_RDCH_TYPE=0,C_AXIS_TYPE=0,C_IMPLEMENTATION_TYPE_WACH=1,C_IMPLEMENTATION_TYPE_WDCH=1,C_IMPLEMENTATION_TYPE_WRCH=1,C_IMPLEMENTATION_TYPE_RACH=1,C_IMPLEMENTATION_TYP" & 
+"E_RDCH=1,C_IMPLEMENTATION_TYPE_AXIS=1,C_APPLICATION_TYPE_WACH=0,C_APPLICATION_TYPE_WDCH=0,C_APPLICATION_TYPE_WRCH=0,C_APPLICATION_TYPE_RACH=0,C_APPLICATION_TYPE_RDCH=0,C_APPLICATION_TYPE_AXIS=0,C_PRIM_FIFO_TYPE_WACH=512x36,C_PRIM_FIFO_TYPE_WDCH=1kx36,C_PRIM_FIFO_TYPE_WRCH=512x36,C_PRIM_FIFO_TYPE_RACH=512x36,C_PRIM_FIFO_TYPE_RDCH=1kx36,C_PRIM_FIFO_TYPE_AXIS=1kx18,C_USE_ECC_WACH=0,C_USE_ECC_WDCH=0,C_USE_ECC_WRCH=0,C_USE_ECC_RACH=0,C_USE_ECC_RDCH=0,C_USE_ECC_AXIS=0,C_ERROR_INJECTION_TYPE_WACH=0,C_E" & 
+"RROR_INJECTION_TYPE_WDCH=0,C_ERROR_INJECTION_TYPE_WRCH=0,C_ERROR_INJECTION_TYPE_RACH=0,C_ERROR_INJECTION_TYPE_RDCH=0,C_ERROR_INJECTION_TYPE_AXIS=0,C_DIN_WIDTH_WACH=1,C_DIN_WIDTH_WDCH=64,C_DIN_WIDTH_WRCH=2,C_DIN_WIDTH_RACH=32,C_DIN_WIDTH_RDCH=64,C_DIN_WIDTH_AXIS=1,C_WR_DEPTH_WACH=16,C_WR_DEPTH_WDCH=1024,C_WR_DEPTH_WRCH=16,C_WR_DEPTH_RACH=16,C_WR_DEPTH_RDCH=1024,C_WR_DEPTH_AXIS=1024,C_WR_PNTR_WIDTH_WACH=4,C_WR_PNTR_WIDTH_WDCH=10,C_WR_PNTR_WIDTH_WRCH=4,C_WR_PNTR_WIDTH_RACH=4,C_WR_PNTR_WIDTH_RDCH=10" & 
+",C_WR_PNTR_WIDTH_AXIS=10,C_HAS_DATA_COUNTS_WACH=0,C_HAS_DATA_COUNTS_WDCH=0,C_HAS_DATA_COUNTS_WRCH=0,C_HAS_DATA_COUNTS_RACH=0,C_HAS_DATA_COUNTS_RDCH=0,C_HAS_DATA_COUNTS_AXIS=0,C_HAS_PROG_FLAGS_WACH=0,C_HAS_PROG_FLAGS_WDCH=0,C_HAS_PROG_FLAGS_WRCH=0,C_HAS_PROG_FLAGS_RACH=0,C_HAS_PROG_FLAGS_RDCH=0,C_HAS_PROG_FLAGS_AXIS=0,C_PROG_FULL_TYPE_WACH=0,C_PROG_FULL_TYPE_WDCH=0,C_PROG_FULL_TYPE_WRCH=0,C_PROG_FULL_TYPE_RACH=0,C_PROG_FULL_TYPE_RDCH=0,C_PROG_FULL_TYPE_AXIS=0,C_PROG_FULL_THRESH_ASSERT_VAL_WACH=10" & 
+"23,C_PROG_FULL_THRESH_ASSERT_VAL_WDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_WRCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RACH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_RDCH=1023,C_PROG_FULL_THRESH_ASSERT_VAL_AXIS=1023,C_PROG_EMPTY_TYPE_WACH=0,C_PROG_EMPTY_TYPE_WDCH=0,C_PROG_EMPTY_TYPE_WRCH=0,C_PROG_EMPTY_TYPE_RACH=0,C_PROG_EMPTY_TYPE_RDCH=0,C_PROG_EMPTY_TYPE_AXIS=0,C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH=1022,C_PROG_EMPTY_THRESH_ASSE" & 
+"RT_VAL_RACH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH=1022,C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS=1022,C_REG_SLICE_MODE_WACH=0,C_REG_SLICE_MODE_WDCH=0,C_REG_SLICE_MODE_WRCH=0,C_REG_SLICE_MODE_RACH=0,C_REG_SLICE_MODE_RDCH=0,C_REG_SLICE_MODE_AXIS=0}";
+  ATTRIBUTE X_INTERFACE_INFO : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
+  ATTRIBUTE X_INTERFACE_INFO OF empty: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ EMPTY";
+  ATTRIBUTE X_INTERFACE_INFO OF full: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE FULL";
+  ATTRIBUTE X_INTERFACE_INFO OF dout: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_DATA";
+  ATTRIBUTE X_INTERFACE_INFO OF rd_en: SIGNAL IS "xilinx.com:interface:fifo_read:1.0 FIFO_READ RD_EN";
+  ATTRIBUTE X_INTERFACE_INFO OF wr_en: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_EN";
+  ATTRIBUTE X_INTERFACE_INFO OF din: SIGNAL IS "xilinx.com:interface:fifo_write:1.0 FIFO_WRITE WR_DATA";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF clk: SIGNAL IS "XIL_INTERFACENAME core_clk, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 core_clk CLK";
+BEGIN
+  U0 : fifo_generator_v13_2_5
+    GENERIC MAP (
+      C_COMMON_CLOCK => 1,
+      C_SELECT_XPM => 0,
+      C_COUNT_TYPE => 0,
+      C_DATA_COUNT_WIDTH => 12,
+      C_DEFAULT_VALUE => "BlankString",
+      C_DIN_WIDTH => 32,
+      C_DOUT_RST_VAL => "0",
+      C_DOUT_WIDTH => 32,
+      C_ENABLE_RLOCS => 0,
+      C_FAMILY => "artix7",
+      C_FULL_FLAGS_RST_VAL => 0,
+      C_HAS_ALMOST_EMPTY => 0,
+      C_HAS_ALMOST_FULL => 0,
+      C_HAS_BACKUP => 0,
+      C_HAS_DATA_COUNT => 1,
+      C_HAS_INT_CLK => 0,
+      C_HAS_MEMINIT_FILE => 0,
+      C_HAS_OVERFLOW => 0,
+      C_HAS_RD_DATA_COUNT => 0,
+      C_HAS_RD_RST => 0,
+      C_HAS_RST => 0,
+      C_HAS_SRST => 1,
+      C_HAS_UNDERFLOW => 0,
+      C_HAS_VALID => 0,
+      C_HAS_WR_ACK => 0,
+      C_HAS_WR_DATA_COUNT => 0,
+      C_HAS_WR_RST => 0,
+      C_IMPLEMENTATION_TYPE => 0,
+      C_INIT_WR_PNTR_VAL => 0,
+      C_MEMORY_TYPE => 1,
+      C_MIF_FILE_NAME => "BlankString",
+      C_OPTIMIZATION_MODE => 0,
+      C_OVERFLOW_LOW => 0,
+      C_PRELOAD_LATENCY => 0,
+      C_PRELOAD_REGS => 1,
+      C_PRIM_FIFO_TYPE => "2kx18",
+      C_PROG_EMPTY_THRESH_ASSERT_VAL => 4,
+      C_PROG_EMPTY_THRESH_NEGATE_VAL => 5,
+      C_PROG_EMPTY_TYPE => 0,
+      C_PROG_FULL_THRESH_ASSERT_VAL => 2047,
+      C_PROG_FULL_THRESH_NEGATE_VAL => 2046,
+      C_PROG_FULL_TYPE => 0,
+      C_RD_DATA_COUNT_WIDTH => 12,
+      C_RD_DEPTH => 2048,
+      C_RD_FREQ => 1,
+      C_RD_PNTR_WIDTH => 11,
+      C_UNDERFLOW_LOW => 0,
+      C_USE_DOUT_RST => 1,
+      C_USE_ECC => 0,
+      C_USE_EMBEDDED_REG => 0,
+      C_USE_PIPELINE_REG => 0,
+      C_POWER_SAVING_MODE => 0,
+      C_USE_FIFO16_FLAGS => 0,
+      C_USE_FWFT_DATA_COUNT => 1,
+      C_VALID_LOW => 0,
+      C_WR_ACK_LOW => 0,
+      C_WR_DATA_COUNT_WIDTH => 12,
+      C_WR_DEPTH => 2048,
+      C_WR_FREQ => 1,
+      C_WR_PNTR_WIDTH => 11,
+      C_WR_RESPONSE_LATENCY => 1,
+      C_MSGON_VAL => 1,
+      C_ENABLE_RST_SYNC => 1,
+      C_EN_SAFETY_CKT => 0,
+      C_ERROR_INJECTION_TYPE => 0,
+      C_SYNCHRONIZER_STAGE => 2,
+      C_INTERFACE_TYPE => 0,
+      C_AXI_TYPE => 1,
+      C_HAS_AXI_WR_CHANNEL => 1,
+      C_HAS_AXI_RD_CHANNEL => 1,
+      C_HAS_SLAVE_CE => 0,
+      C_HAS_MASTER_CE => 0,
+      C_ADD_NGC_CONSTRAINT => 0,
+      C_USE_COMMON_OVERFLOW => 0,
+      C_USE_COMMON_UNDERFLOW => 0,
+      C_USE_DEFAULT_SETTINGS => 0,
+      C_AXI_ID_WIDTH => 1,
+      C_AXI_ADDR_WIDTH => 32,
+      C_AXI_DATA_WIDTH => 64,
+      C_AXI_LEN_WIDTH => 8,
+      C_AXI_LOCK_WIDTH => 1,
+      C_HAS_AXI_ID => 0,
+      C_HAS_AXI_AWUSER => 0,
+      C_HAS_AXI_WUSER => 0,
+      C_HAS_AXI_BUSER => 0,
+      C_HAS_AXI_ARUSER => 0,
+      C_HAS_AXI_RUSER => 0,
+      C_AXI_ARUSER_WIDTH => 1,
+      C_AXI_AWUSER_WIDTH => 1,
+      C_AXI_WUSER_WIDTH => 1,
+      C_AXI_BUSER_WIDTH => 1,
+      C_AXI_RUSER_WIDTH => 1,
+      C_HAS_AXIS_TDATA => 1,
+      C_HAS_AXIS_TID => 0,
+      C_HAS_AXIS_TDEST => 0,
+      C_HAS_AXIS_TUSER => 1,
+      C_HAS_AXIS_TREADY => 1,
+      C_HAS_AXIS_TLAST => 0,
+      C_HAS_AXIS_TSTRB => 0,
+      C_HAS_AXIS_TKEEP => 0,
+      C_AXIS_TDATA_WIDTH => 8,
+      C_AXIS_TID_WIDTH => 1,
+      C_AXIS_TDEST_WIDTH => 1,
+      C_AXIS_TUSER_WIDTH => 4,
+      C_AXIS_TSTRB_WIDTH => 1,
+      C_AXIS_TKEEP_WIDTH => 1,
+      C_WACH_TYPE => 0,
+      C_WDCH_TYPE => 0,
+      C_WRCH_TYPE => 0,
+      C_RACH_TYPE => 0,
+      C_RDCH_TYPE => 0,
+      C_AXIS_TYPE => 0,
+      C_IMPLEMENTATION_TYPE_WACH => 1,
+      C_IMPLEMENTATION_TYPE_WDCH => 1,
+      C_IMPLEMENTATION_TYPE_WRCH => 1,
+      C_IMPLEMENTATION_TYPE_RACH => 1,
+      C_IMPLEMENTATION_TYPE_RDCH => 1,
+      C_IMPLEMENTATION_TYPE_AXIS => 1,
+      C_APPLICATION_TYPE_WACH => 0,
+      C_APPLICATION_TYPE_WDCH => 0,
+      C_APPLICATION_TYPE_WRCH => 0,
+      C_APPLICATION_TYPE_RACH => 0,
+      C_APPLICATION_TYPE_RDCH => 0,
+      C_APPLICATION_TYPE_AXIS => 0,
+      C_PRIM_FIFO_TYPE_WACH => "512x36",
+      C_PRIM_FIFO_TYPE_WDCH => "1kx36",
+      C_PRIM_FIFO_TYPE_WRCH => "512x36",
+      C_PRIM_FIFO_TYPE_RACH => "512x36",
+      C_PRIM_FIFO_TYPE_RDCH => "1kx36",
+      C_PRIM_FIFO_TYPE_AXIS => "1kx18",
+      C_USE_ECC_WACH => 0,
+      C_USE_ECC_WDCH => 0,
+      C_USE_ECC_WRCH => 0,
+      C_USE_ECC_RACH => 0,
+      C_USE_ECC_RDCH => 0,
+      C_USE_ECC_AXIS => 0,
+      C_ERROR_INJECTION_TYPE_WACH => 0,
+      C_ERROR_INJECTION_TYPE_WDCH => 0,
+      C_ERROR_INJECTION_TYPE_WRCH => 0,
+      C_ERROR_INJECTION_TYPE_RACH => 0,
+      C_ERROR_INJECTION_TYPE_RDCH => 0,
+      C_ERROR_INJECTION_TYPE_AXIS => 0,
+      C_DIN_WIDTH_WACH => 1,
+      C_DIN_WIDTH_WDCH => 64,
+      C_DIN_WIDTH_WRCH => 2,
+      C_DIN_WIDTH_RACH => 32,
+      C_DIN_WIDTH_RDCH => 64,
+      C_DIN_WIDTH_AXIS => 1,
+      C_WR_DEPTH_WACH => 16,
+      C_WR_DEPTH_WDCH => 1024,
+      C_WR_DEPTH_WRCH => 16,
+      C_WR_DEPTH_RACH => 16,
+      C_WR_DEPTH_RDCH => 1024,
+      C_WR_DEPTH_AXIS => 1024,
+      C_WR_PNTR_WIDTH_WACH => 4,
+      C_WR_PNTR_WIDTH_WDCH => 10,
+      C_WR_PNTR_WIDTH_WRCH => 4,
+      C_WR_PNTR_WIDTH_RACH => 4,
+      C_WR_PNTR_WIDTH_RDCH => 10,
+      C_WR_PNTR_WIDTH_AXIS => 10,
+      C_HAS_DATA_COUNTS_WACH => 0,
+      C_HAS_DATA_COUNTS_WDCH => 0,
+      C_HAS_DATA_COUNTS_WRCH => 0,
+      C_HAS_DATA_COUNTS_RACH => 0,
+      C_HAS_DATA_COUNTS_RDCH => 0,
+      C_HAS_DATA_COUNTS_AXIS => 0,
+      C_HAS_PROG_FLAGS_WACH => 0,
+      C_HAS_PROG_FLAGS_WDCH => 0,
+      C_HAS_PROG_FLAGS_WRCH => 0,
+      C_HAS_PROG_FLAGS_RACH => 0,
+      C_HAS_PROG_FLAGS_RDCH => 0,
+      C_HAS_PROG_FLAGS_AXIS => 0,
+      C_PROG_FULL_TYPE_WACH => 0,
+      C_PROG_FULL_TYPE_WDCH => 0,
+      C_PROG_FULL_TYPE_WRCH => 0,
+      C_PROG_FULL_TYPE_RACH => 0,
+      C_PROG_FULL_TYPE_RDCH => 0,
+      C_PROG_FULL_TYPE_AXIS => 0,
+      C_PROG_FULL_THRESH_ASSERT_VAL_WACH => 1023,
+      C_PROG_FULL_THRESH_ASSERT_VAL_WDCH => 1023,
+      C_PROG_FULL_THRESH_ASSERT_VAL_WRCH => 1023,
+      C_PROG_FULL_THRESH_ASSERT_VAL_RACH => 1023,
+      C_PROG_FULL_THRESH_ASSERT_VAL_RDCH => 1023,
+      C_PROG_FULL_THRESH_ASSERT_VAL_AXIS => 1023,
+      C_PROG_EMPTY_TYPE_WACH => 0,
+      C_PROG_EMPTY_TYPE_WDCH => 0,
+      C_PROG_EMPTY_TYPE_WRCH => 0,
+      C_PROG_EMPTY_TYPE_RACH => 0,
+      C_PROG_EMPTY_TYPE_RDCH => 0,
+      C_PROG_EMPTY_TYPE_AXIS => 0,
+      C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH => 1022,
+      C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH => 1022,
+      C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH => 1022,
+      C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH => 1022,
+      C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH => 1022,
+      C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS => 1022,
+      C_REG_SLICE_MODE_WACH => 0,
+      C_REG_SLICE_MODE_WDCH => 0,
+      C_REG_SLICE_MODE_WRCH => 0,
+      C_REG_SLICE_MODE_RACH => 0,
+      C_REG_SLICE_MODE_RDCH => 0,
+      C_REG_SLICE_MODE_AXIS => 0
+    )
+    PORT MAP (
+      backup => '0',
+      backup_marker => '0',
+      clk => clk,
+      rst => '0',
+      srst => srst,
+      wr_clk => '0',
+      wr_rst => '0',
+      rd_clk => '0',
+      rd_rst => '0',
+      din => din,
+      wr_en => wr_en,
+      rd_en => rd_en,
+      prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 11)),
+      prog_empty_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 11)),
+      prog_empty_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 11)),
+      prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 11)),
+      prog_full_thresh_assert => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 11)),
+      prog_full_thresh_negate => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 11)),
+      int_clk => '0',
+      injectdbiterr => '0',
+      injectsbiterr => '0',
+      sleep => '0',
+      dout => dout,
+      full => full,
+      empty => empty,
+      data_count => data_count,
+      m_aclk => '0',
+      s_aclk => '0',
+      s_aresetn => '0',
+      m_aclk_en => '0',
+      s_aclk_en => '0',
+      s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
+      s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
+      s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
+      s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
+      s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
+      s_axi_awlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
+      s_axi_awcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
+      s_axi_awprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
+      s_axi_awqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
+      s_axi_awregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
+      s_axi_awuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
+      s_axi_awvalid => '0',
+      s_axi_wid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
+      s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
+      s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
+      s_axi_wlast => '0',
+      s_axi_wuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
+      s_axi_wvalid => '0',
+      s_axi_bready => '0',
+      m_axi_awready => '0',
+      m_axi_wready => '0',
+      m_axi_bid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
+      m_axi_bresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
+      m_axi_buser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
+      m_axi_bvalid => '0',
+      s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
+      s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
+      s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
+      s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
+      s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
+      s_axi_arlock => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
+      s_axi_arcache => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
+      s_axi_arprot => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
+      s_axi_arqos => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
+      s_axi_arregion => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
+      s_axi_aruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
+      s_axi_arvalid => '0',
+      s_axi_rready => '0',
+      m_axi_arready => '0',
+      m_axi_rid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
+      m_axi_rdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 64)),
+      m_axi_rresp => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
+      m_axi_rlast => '0',
+      m_axi_ruser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
+      m_axi_rvalid => '0',
+      s_axis_tvalid => '0',
+      s_axis_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
+      s_axis_tstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
+      s_axis_tkeep => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
+      s_axis_tlast => '0',
+      s_axis_tid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
+      s_axis_tdest => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
+      s_axis_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
+      m_axis_tready => '0',
+      axi_aw_injectsbiterr => '0',
+      axi_aw_injectdbiterr => '0',
+      axi_aw_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
+      axi_aw_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
+      axi_w_injectsbiterr => '0',
+      axi_w_injectdbiterr => '0',
+      axi_w_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
+      axi_w_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
+      axi_b_injectsbiterr => '0',
+      axi_b_injectdbiterr => '0',
+      axi_b_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
+      axi_b_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
+      axi_ar_injectsbiterr => '0',
+      axi_ar_injectdbiterr => '0',
+      axi_ar_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
+      axi_ar_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
+      axi_r_injectsbiterr => '0',
+      axi_r_injectdbiterr => '0',
+      axi_r_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
+      axi_r_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
+      axis_injectsbiterr => '0',
+      axis_injectdbiterr => '0',
+      axis_prog_full_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10)),
+      axis_prog_empty_thresh => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 10))
+    );
+END data_fifo_arch;

HDLForBeginners_Examples/30092022_testbench_start_finish/ip/xfft_0/sim/xfft_0.vhd

@@ -0,0 +1,241 @@
+-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:ip:xfft:9.1
+-- IP Revision: 6
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+LIBRARY xfft_v9_1_6;
+USE xfft_v9_1_6.xfft_v9_1_6;
+
+ENTITY xfft_0 IS
+  PORT (
+    aclk : IN STD_LOGIC;
+    s_axis_config_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+    s_axis_config_tvalid : IN STD_LOGIC;
+    s_axis_config_tready : OUT STD_LOGIC;
+    s_axis_data_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
+    s_axis_data_tvalid : IN STD_LOGIC;
+    s_axis_data_tready : OUT STD_LOGIC;
+    s_axis_data_tlast : IN STD_LOGIC;
+    m_axis_data_tdata : OUT STD_LOGIC_VECTOR(79 DOWNTO 0);
+    m_axis_data_tvalid : OUT STD_LOGIC;
+    m_axis_data_tready : IN STD_LOGIC;
+    m_axis_data_tlast : OUT STD_LOGIC;
+    event_frame_started : OUT STD_LOGIC;
+    event_tlast_unexpected : OUT STD_LOGIC;
+    event_tlast_missing : OUT STD_LOGIC;
+    event_status_channel_halt : OUT STD_LOGIC;
+    event_data_in_channel_halt : OUT STD_LOGIC;
+    event_data_out_channel_halt : OUT STD_LOGIC
+  );
+END xfft_0;
+
+ARCHITECTURE xfft_0_arch OF xfft_0 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF xfft_0_arch: ARCHITECTURE IS "yes";
+  COMPONENT xfft_v9_1_6 IS
+    GENERIC (
+      C_XDEVICEFAMILY : STRING;
+      C_PART : STRING;
+      C_S_AXIS_CONFIG_TDATA_WIDTH : INTEGER;
+      C_S_AXIS_DATA_TDATA_WIDTH : INTEGER;
+      C_M_AXIS_DATA_TDATA_WIDTH : INTEGER;
+      C_M_AXIS_DATA_TUSER_WIDTH : INTEGER;
+      C_M_AXIS_STATUS_TDATA_WIDTH : INTEGER;
+      C_THROTTLE_SCHEME : INTEGER;
+      C_CHANNELS : INTEGER;
+      C_NFFT_MAX : INTEGER;
+      C_ARCH : INTEGER;
+      C_HAS_NFFT : INTEGER;
+      C_USE_FLT_PT : INTEGER;
+      C_INPUT_WIDTH : INTEGER;
+      C_TWIDDLE_WIDTH : INTEGER;
+      C_OUTPUT_WIDTH : INTEGER;
+      C_HAS_SCALING : INTEGER;
+      C_HAS_BFP : INTEGER;
+      C_HAS_ROUNDING : INTEGER;
+      C_HAS_ACLKEN : INTEGER;
+      C_HAS_ARESETN : INTEGER;
+      C_HAS_OVFLO : INTEGER;
+      C_HAS_NATURAL_INPUT : INTEGER;
+      C_HAS_NATURAL_OUTPUT : INTEGER;
+      C_HAS_CYCLIC_PREFIX : INTEGER;
+      C_HAS_XK_INDEX : INTEGER;
+      C_DATA_MEM_TYPE : INTEGER;
+      C_TWIDDLE_MEM_TYPE : INTEGER;
+      C_BRAM_STAGES : INTEGER;
+      C_REORDER_MEM_TYPE : INTEGER;
+      C_USE_HYBRID_RAM : INTEGER;
+      C_OPTIMIZE_GOAL : INTEGER;
+      C_CMPY_TYPE : INTEGER;
+      C_BFLY_TYPE : INTEGER
+    );
+    PORT (
+      aclk : IN STD_LOGIC;
+      aclken : IN STD_LOGIC;
+      aresetn : IN STD_LOGIC;
+      s_axis_config_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+      s_axis_config_tvalid : IN STD_LOGIC;
+      s_axis_config_tready : OUT STD_LOGIC;
+      s_axis_data_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
+      s_axis_data_tvalid : IN STD_LOGIC;
+      s_axis_data_tready : OUT STD_LOGIC;
+      s_axis_data_tlast : IN STD_LOGIC;
+      m_axis_data_tdata : OUT STD_LOGIC_VECTOR(79 DOWNTO 0);
+      m_axis_data_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+      m_axis_data_tvalid : OUT STD_LOGIC;
+      m_axis_data_tready : IN STD_LOGIC;
+      m_axis_data_tlast : OUT STD_LOGIC;
+      m_axis_status_tdata : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+      m_axis_status_tvalid : OUT STD_LOGIC;
+      m_axis_status_tready : IN STD_LOGIC;
+      event_frame_started : OUT STD_LOGIC;
+      event_tlast_unexpected : OUT STD_LOGIC;
+      event_tlast_missing : OUT STD_LOGIC;
+      event_fft_overflow : OUT STD_LOGIC;
+      event_status_channel_halt : OUT STD_LOGIC;
+      event_data_in_channel_halt : OUT STD_LOGIC;
+      event_data_out_channel_halt : OUT STD_LOGIC
+    );
+  END COMPONENT xfft_v9_1_6;
+  ATTRIBUTE X_INTERFACE_INFO : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER OF event_data_out_channel_halt: SIGNAL IS "XIL_INTERFACENAME event_data_out_channel_halt_intf, SENSITIVITY EDGE_RISING, PortWidth 1";
+  ATTRIBUTE X_INTERFACE_INFO OF event_data_out_channel_halt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 event_data_out_channel_halt_intf INTERRUPT";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF event_data_in_channel_halt: SIGNAL IS "XIL_INTERFACENAME event_data_in_channel_halt_intf, SENSITIVITY EDGE_RISING, PortWidth 1";
+  ATTRIBUTE X_INTERFACE_INFO OF event_data_in_channel_halt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 event_data_in_channel_halt_intf INTERRUPT";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF event_status_channel_halt: SIGNAL IS "XIL_INTERFACENAME event_status_channel_halt_intf, SENSITIVITY EDGE_RISING, PortWidth 1";
+  ATTRIBUTE X_INTERFACE_INFO OF event_status_channel_halt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 event_status_channel_halt_intf INTERRUPT";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF event_tlast_missing: SIGNAL IS "XIL_INTERFACENAME event_tlast_missing_intf, SENSITIVITY EDGE_RISING, PortWidth 1";
+  ATTRIBUTE X_INTERFACE_INFO OF event_tlast_missing: SIGNAL IS "xilinx.com:signal:interrupt:1.0 event_tlast_missing_intf INTERRUPT";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF event_tlast_unexpected: SIGNAL IS "XIL_INTERFACENAME event_tlast_unexpected_intf, SENSITIVITY EDGE_RISING, PortWidth 1";
+  ATTRIBUTE X_INTERFACE_INFO OF event_tlast_unexpected: SIGNAL IS "xilinx.com:signal:interrupt:1.0 event_tlast_unexpected_intf INTERRUPT";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF event_frame_started: SIGNAL IS "XIL_INTERFACENAME event_frame_started_intf, SENSITIVITY EDGE_RISING, PortWidth 1";
+  ATTRIBUTE X_INTERFACE_INFO OF event_frame_started: SIGNAL IS "xilinx.com:signal:interrupt:1.0 event_frame_started_intf INTERRUPT";
+  ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TLAST";
+  ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TVALID";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF m_axis_data_tdata: SIGNAL IS "XIL_INTERFACENAME M_AXIS_DATA, TDATA_NUM_BYTES 10, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TDATA";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TLAST";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TVALID";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF s_axis_data_tdata: SIGNAL IS "XIL_INTERFACENAME S_AXIS_DATA, TDATA_NUM_BYTES 8, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TDATA";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axis_config_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_CONFIG TREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axis_config_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_CONFIG TVALID";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF s_axis_config_tdata: SIGNAL IS "XIL_INTERFACENAME S_AXIS_CONFIG, TDATA_NUM_BYTES 1, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axis_config_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_CONFIG TDATA";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF aclk: SIGNAL IS "XIL_INTERFACENAME aclk_intf, ASSOCIATED_BUSIF S_AXIS_CONFIG:M_AXIS_DATA:M_AXIS_STATUS:S_AXIS_DATA, ASSOCIATED_RESET aresetn, ASSOCIATED_CLKEN aclken, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
+BEGIN
+  U0 : xfft_v9_1_6
+    GENERIC MAP (
+      C_XDEVICEFAMILY => "artix7",
+      C_PART => "xc7a100tcsg324-1",
+      C_S_AXIS_CONFIG_TDATA_WIDTH => 8,
+      C_S_AXIS_DATA_TDATA_WIDTH => 64,
+      C_M_AXIS_DATA_TDATA_WIDTH => 80,
+      C_M_AXIS_DATA_TUSER_WIDTH => 1,
+      C_M_AXIS_STATUS_TDATA_WIDTH => 1,
+      C_THROTTLE_SCHEME => 1,
+      C_CHANNELS => 1,
+      C_NFFT_MAX => 8,
+      C_ARCH => 4,
+      C_HAS_NFFT => 0,
+      C_USE_FLT_PT => 0,
+      C_INPUT_WIDTH => 29,
+      C_TWIDDLE_WIDTH => 32,
+      C_OUTPUT_WIDTH => 38,
+      C_HAS_SCALING => 0,
+      C_HAS_BFP => 0,
+      C_HAS_ROUNDING => 0,
+      C_HAS_ACLKEN => 0,
+      C_HAS_ARESETN => 0,
+      C_HAS_OVFLO => 0,
+      C_HAS_NATURAL_INPUT => 1,
+      C_HAS_NATURAL_OUTPUT => 1,
+      C_HAS_CYCLIC_PREFIX => 0,
+      C_HAS_XK_INDEX => 0,
+      C_DATA_MEM_TYPE => 1,
+      C_TWIDDLE_MEM_TYPE => 1,
+      C_BRAM_STAGES => 0,
+      C_REORDER_MEM_TYPE => 1,
+      C_USE_HYBRID_RAM => 0,
+      C_OPTIMIZE_GOAL => 0,
+      C_CMPY_TYPE => 1,
+      C_BFLY_TYPE => 0
+    )
+    PORT MAP (
+      aclk => aclk,
+      aclken => '1',
+      aresetn => '1',
+      s_axis_config_tdata => s_axis_config_tdata,
+      s_axis_config_tvalid => s_axis_config_tvalid,
+      s_axis_config_tready => s_axis_config_tready,
+      s_axis_data_tdata => s_axis_data_tdata,
+      s_axis_data_tvalid => s_axis_data_tvalid,
+      s_axis_data_tready => s_axis_data_tready,
+      s_axis_data_tlast => s_axis_data_tlast,
+      m_axis_data_tdata => m_axis_data_tdata,
+      m_axis_data_tvalid => m_axis_data_tvalid,
+      m_axis_data_tready => m_axis_data_tready,
+      m_axis_data_tlast => m_axis_data_tlast,
+      m_axis_status_tready => '1',
+      event_frame_started => event_frame_started,
+      event_tlast_unexpected => event_tlast_unexpected,
+      event_tlast_missing => event_tlast_missing,
+      event_status_channel_halt => event_status_channel_halt,
+      event_data_in_channel_halt => event_data_in_channel_halt,
+      event_data_out_channel_halt => event_data_out_channel_halt
+    );
+END xfft_0_arch;

HDLForBeginners_Examples/30092022_testbench_start_finish/ip/xfft_0/synth/xfft_0.vhd

@@ -0,0 +1,248 @@
+-- (c) Copyright 1995-2022 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+-- 
+-- DO NOT MODIFY THIS FILE.
+
+-- IP VLNV: xilinx.com:ip:xfft:9.1
+-- IP Revision: 6
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+
+LIBRARY xfft_v9_1_6;
+USE xfft_v9_1_6.xfft_v9_1_6;
+
+ENTITY xfft_0 IS
+  PORT (
+    aclk : IN STD_LOGIC;
+    s_axis_config_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+    s_axis_config_tvalid : IN STD_LOGIC;
+    s_axis_config_tready : OUT STD_LOGIC;
+    s_axis_data_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
+    s_axis_data_tvalid : IN STD_LOGIC;
+    s_axis_data_tready : OUT STD_LOGIC;
+    s_axis_data_tlast : IN STD_LOGIC;
+    m_axis_data_tdata : OUT STD_LOGIC_VECTOR(79 DOWNTO 0);
+    m_axis_data_tvalid : OUT STD_LOGIC;
+    m_axis_data_tready : IN STD_LOGIC;
+    m_axis_data_tlast : OUT STD_LOGIC;
+    event_frame_started : OUT STD_LOGIC;
+    event_tlast_unexpected : OUT STD_LOGIC;
+    event_tlast_missing : OUT STD_LOGIC;
+    event_status_channel_halt : OUT STD_LOGIC;
+    event_data_in_channel_halt : OUT STD_LOGIC;
+    event_data_out_channel_halt : OUT STD_LOGIC
+  );
+END xfft_0;
+
+ARCHITECTURE xfft_0_arch OF xfft_0 IS
+  ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
+  ATTRIBUTE DowngradeIPIdentifiedWarnings OF xfft_0_arch: ARCHITECTURE IS "yes";
+  COMPONENT xfft_v9_1_6 IS
+    GENERIC (
+      C_XDEVICEFAMILY : STRING;
+      C_PART : STRING;
+      C_S_AXIS_CONFIG_TDATA_WIDTH : INTEGER;
+      C_S_AXIS_DATA_TDATA_WIDTH : INTEGER;
+      C_M_AXIS_DATA_TDATA_WIDTH : INTEGER;
+      C_M_AXIS_DATA_TUSER_WIDTH : INTEGER;
+      C_M_AXIS_STATUS_TDATA_WIDTH : INTEGER;
+      C_THROTTLE_SCHEME : INTEGER;
+      C_CHANNELS : INTEGER;
+      C_NFFT_MAX : INTEGER;
+      C_ARCH : INTEGER;
+      C_HAS_NFFT : INTEGER;
+      C_USE_FLT_PT : INTEGER;
+      C_INPUT_WIDTH : INTEGER;
+      C_TWIDDLE_WIDTH : INTEGER;
+      C_OUTPUT_WIDTH : INTEGER;
+      C_HAS_SCALING : INTEGER;
+      C_HAS_BFP : INTEGER;
+      C_HAS_ROUNDING : INTEGER;
+      C_HAS_ACLKEN : INTEGER;
+      C_HAS_ARESETN : INTEGER;
+      C_HAS_OVFLO : INTEGER;
+      C_HAS_NATURAL_INPUT : INTEGER;
+      C_HAS_NATURAL_OUTPUT : INTEGER;
+      C_HAS_CYCLIC_PREFIX : INTEGER;
+      C_HAS_XK_INDEX : INTEGER;
+      C_DATA_MEM_TYPE : INTEGER;
+      C_TWIDDLE_MEM_TYPE : INTEGER;
+      C_BRAM_STAGES : INTEGER;
+      C_REORDER_MEM_TYPE : INTEGER;
+      C_USE_HYBRID_RAM : INTEGER;
+      C_OPTIMIZE_GOAL : INTEGER;
+      C_CMPY_TYPE : INTEGER;
+      C_BFLY_TYPE : INTEGER
+    );
+    PORT (
+      aclk : IN STD_LOGIC;
+      aclken : IN STD_LOGIC;
+      aresetn : IN STD_LOGIC;
+      s_axis_config_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+      s_axis_config_tvalid : IN STD_LOGIC;
+      s_axis_config_tready : OUT STD_LOGIC;
+      s_axis_data_tdata : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
+      s_axis_data_tvalid : IN STD_LOGIC;
+      s_axis_data_tready : OUT STD_LOGIC;
+      s_axis_data_tlast : IN STD_LOGIC;
+      m_axis_data_tdata : OUT STD_LOGIC_VECTOR(79 DOWNTO 0);
+      m_axis_data_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+      m_axis_data_tvalid : OUT STD_LOGIC;
+      m_axis_data_tready : IN STD_LOGIC;
+      m_axis_data_tlast : OUT STD_LOGIC;
+      m_axis_status_tdata : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+      m_axis_status_tvalid : OUT STD_LOGIC;
+      m_axis_status_tready : IN STD_LOGIC;
+      event_frame_started : OUT STD_LOGIC;
+      event_tlast_unexpected : OUT STD_LOGIC;
+      event_tlast_missing : OUT STD_LOGIC;
+      event_fft_overflow : OUT STD_LOGIC;
+      event_status_channel_halt : OUT STD_LOGIC;
+      event_data_in_channel_halt : OUT STD_LOGIC;
+      event_data_out_channel_halt : OUT STD_LOGIC
+    );
+  END COMPONENT xfft_v9_1_6;
+  ATTRIBUTE X_CORE_INFO : STRING;
+  ATTRIBUTE X_CORE_INFO OF xfft_0_arch: ARCHITECTURE IS "xfft_v9_1_6,Vivado 2021.1";
+  ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
+  ATTRIBUTE CHECK_LICENSE_TYPE OF xfft_0_arch : ARCHITECTURE IS "xfft_0,xfft_v9_1_6,{}";
+  ATTRIBUTE CORE_GENERATION_INFO : STRING;
+  ATTRIBUTE CORE_GENERATION_INFO OF xfft_0_arch: ARCHITECTURE IS "xfft_0,xfft_v9_1_6,{x_ipProduct=Vivado 2021.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=xfft,x_ipVersion=9.1,x_ipCoreRevision=6,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=artix7,C_PART=xc7a100tcsg324-1,C_S_AXIS_CONFIG_TDATA_WIDTH=8,C_S_AXIS_DATA_TDATA_WIDTH=64,C_M_AXIS_DATA_TDATA_WIDTH=80,C_M_AXIS_DATA_TUSER_WIDTH=1,C_M_AXIS_STATUS_TDATA_WIDTH=1,C_THROTTLE_SCHEME=1,C_CHANNELS=1,C_NFFT_MAX=8,C_ARCH=4,C_HAS_NFFT=0,C_USE_FLT_PT=0,C_INPUT_WIDTH=29,C_TWIDDLE_WIDTH=32,C_OUTPUT_WIDT" & 
+"H=38,C_HAS_SCALING=0,C_HAS_BFP=0,C_HAS_ROUNDING=0,C_HAS_ACLKEN=0,C_HAS_ARESETN=0,C_HAS_OVFLO=0,C_HAS_NATURAL_INPUT=1,C_HAS_NATURAL_OUTPUT=1,C_HAS_CYCLIC_PREFIX=0,C_HAS_XK_INDEX=0,C_DATA_MEM_TYPE=1,C_TWIDDLE_MEM_TYPE=1,C_BRAM_STAGES=0,C_REORDER_MEM_TYPE=1,C_USE_HYBRID_RAM=0,C_OPTIMIZE_GOAL=0,C_CMPY_TYPE=1,C_BFLY_TYPE=0}";
+  ATTRIBUTE X_INTERFACE_INFO : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
+  ATTRIBUTE X_INTERFACE_PARAMETER OF event_data_out_channel_halt: SIGNAL IS "XIL_INTERFACENAME event_data_out_channel_halt_intf, SENSITIVITY EDGE_RISING, PortWidth 1";
+  ATTRIBUTE X_INTERFACE_INFO OF event_data_out_channel_halt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 event_data_out_channel_halt_intf INTERRUPT";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF event_data_in_channel_halt: SIGNAL IS "XIL_INTERFACENAME event_data_in_channel_halt_intf, SENSITIVITY EDGE_RISING, PortWidth 1";
+  ATTRIBUTE X_INTERFACE_INFO OF event_data_in_channel_halt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 event_data_in_channel_halt_intf INTERRUPT";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF event_status_channel_halt: SIGNAL IS "XIL_INTERFACENAME event_status_channel_halt_intf, SENSITIVITY EDGE_RISING, PortWidth 1";
+  ATTRIBUTE X_INTERFACE_INFO OF event_status_channel_halt: SIGNAL IS "xilinx.com:signal:interrupt:1.0 event_status_channel_halt_intf INTERRUPT";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF event_tlast_missing: SIGNAL IS "XIL_INTERFACENAME event_tlast_missing_intf, SENSITIVITY EDGE_RISING, PortWidth 1";
+  ATTRIBUTE X_INTERFACE_INFO OF event_tlast_missing: SIGNAL IS "xilinx.com:signal:interrupt:1.0 event_tlast_missing_intf INTERRUPT";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF event_tlast_unexpected: SIGNAL IS "XIL_INTERFACENAME event_tlast_unexpected_intf, SENSITIVITY EDGE_RISING, PortWidth 1";
+  ATTRIBUTE X_INTERFACE_INFO OF event_tlast_unexpected: SIGNAL IS "xilinx.com:signal:interrupt:1.0 event_tlast_unexpected_intf INTERRUPT";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF event_frame_started: SIGNAL IS "XIL_INTERFACENAME event_frame_started_intf, SENSITIVITY EDGE_RISING, PortWidth 1";
+  ATTRIBUTE X_INTERFACE_INFO OF event_frame_started: SIGNAL IS "xilinx.com:signal:interrupt:1.0 event_frame_started_intf INTERRUPT";
+  ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TLAST";
+  ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TVALID";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF m_axis_data_tdata: SIGNAL IS "XIL_INTERFACENAME M_AXIS_DATA, TDATA_NUM_BYTES 10, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF m_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_DATA TDATA";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tlast: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TLAST";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TVALID";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF s_axis_data_tdata: SIGNAL IS "XIL_INTERFACENAME S_AXIS_DATA, TDATA_NUM_BYTES 8, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 1, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axis_data_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_DATA TDATA";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axis_config_tready: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_CONFIG TREADY";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axis_config_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_CONFIG TVALID";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF s_axis_config_tdata: SIGNAL IS "XIL_INTERFACENAME S_AXIS_CONFIG, TDATA_NUM_BYTES 1, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 0, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 0, HAS_TLAST 0, FREQ_HZ 100000000, PHASE 0.0, LAYERED_METADATA undef, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF s_axis_config_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_CONFIG TDATA";
+  ATTRIBUTE X_INTERFACE_PARAMETER OF aclk: SIGNAL IS "XIL_INTERFACENAME aclk_intf, ASSOCIATED_BUSIF S_AXIS_CONFIG:M_AXIS_DATA:M_AXIS_STATUS:S_AXIS_DATA, ASSOCIATED_RESET aresetn, ASSOCIATED_CLKEN aclken, FREQ_HZ 100000000, FREQ_TOLERANCE_HZ 0, PHASE 0.0, INSERT_VIP 0";
+  ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
+BEGIN
+  U0 : xfft_v9_1_6
+    GENERIC MAP (
+      C_XDEVICEFAMILY => "artix7",
+      C_PART => "xc7a100tcsg324-1",
+      C_S_AXIS_CONFIG_TDATA_WIDTH => 8,
+      C_S_AXIS_DATA_TDATA_WIDTH => 64,
+      C_M_AXIS_DATA_TDATA_WIDTH => 80,
+      C_M_AXIS_DATA_TUSER_WIDTH => 1,
+      C_M_AXIS_STATUS_TDATA_WIDTH => 1,
+      C_THROTTLE_SCHEME => 1,
+      C_CHANNELS => 1,
+      C_NFFT_MAX => 8,
+      C_ARCH => 4,
+      C_HAS_NFFT => 0,
+      C_USE_FLT_PT => 0,
+      C_INPUT_WIDTH => 29,
+      C_TWIDDLE_WIDTH => 32,
+      C_OUTPUT_WIDTH => 38,
+      C_HAS_SCALING => 0,
+      C_HAS_BFP => 0,
+      C_HAS_ROUNDING => 0,
+      C_HAS_ACLKEN => 0,
+      C_HAS_ARESETN => 0,
+      C_HAS_OVFLO => 0,
+      C_HAS_NATURAL_INPUT => 1,
+      C_HAS_NATURAL_OUTPUT => 1,
+      C_HAS_CYCLIC_PREFIX => 0,
+      C_HAS_XK_INDEX => 0,
+      C_DATA_MEM_TYPE => 1,
+      C_TWIDDLE_MEM_TYPE => 1,
+      C_BRAM_STAGES => 0,
+      C_REORDER_MEM_TYPE => 1,
+      C_USE_HYBRID_RAM => 0,
+      C_OPTIMIZE_GOAL => 0,
+      C_CMPY_TYPE => 1,
+      C_BFLY_TYPE => 0
+    )
+    PORT MAP (
+      aclk => aclk,
+      aclken => '1',
+      aresetn => '1',
+      s_axis_config_tdata => s_axis_config_tdata,
+      s_axis_config_tvalid => s_axis_config_tvalid,
+      s_axis_config_tready => s_axis_config_tready,
+      s_axis_data_tdata => s_axis_data_tdata,
+      s_axis_data_tvalid => s_axis_data_tvalid,
+      s_axis_data_tready => s_axis_data_tready,
+      s_axis_data_tlast => s_axis_data_tlast,
+      m_axis_data_tdata => m_axis_data_tdata,
+      m_axis_data_tvalid => m_axis_data_tvalid,
+      m_axis_data_tready => m_axis_data_tready,
+      m_axis_data_tlast => m_axis_data_tlast,
+      m_axis_status_tready => '1',
+      event_frame_started => event_frame_started,
+      event_tlast_unexpected => event_tlast_unexpected,
+      event_tlast_missing => event_tlast_missing,
+      event_status_channel_halt => event_status_channel_halt,
+      event_data_in_channel_halt => event_data_in_channel_halt,
+      event_data_out_channel_halt => event_data_out_channel_halt
+    );
+END xfft_0_arch;

HDLForBeginners_Examples/30092022_testbench_start_finish/py/cic_comp_filter.py

@@ -0,0 +1,17 @@
+import numpy as np
+from scipy import signal
+import matplotlib.pyplot as plt
+sr = 3000
+w, h = signal.freqz(b=[-0.5,2, -0.5], a=1)
+x = w * sr * 1.0 / (2 * np.pi)
+y = 20 * np.log10(abs(h))
+plt.figure(figsize=(10,5))
+plt.semilogx(x, y)
+plt.ylabel('Amplitude [dB]')
+plt.xlabel('Frequency [Hz]')
+plt.title('Frequency response')
+plt.grid(which='both', linestyle='-', color='grey')
+plt.xticks([20, 50, 100, 200, 500, 1000, 2000, 5000, 10000, 20000], ["20", "50", "100", "200", "500", "1K", "2K", "5K", "10K", "20K"])
+plt.show()
+
+#from https://dsp.stackexchange.com/questions/49009/get-the-frequency-response-curve-from-fir-filter-coefficients-sampling-rate

HDLForBeginners_Examples/30092022_testbench_start_finish/py/gen_stimulus.py

@@ -0,0 +1,33 @@
+import numpy
+from matplotlib import pyplot as plt
+
+
+fs = 3e6
+f0 = 1e3
+N = 2**14
+
+w = 2*numpy.pi*f0/fs*numpy.arange(0,N)
+
+stim = numpy.cos(w)+1
+
+print(stim)
+
+IMPULSE_HEIGHT = numpy.amax(stim)
+THRESHOLD = IMPULSE_HEIGHT/2
+
+output_pdm = numpy.zeros(N)
+running_sum = 0
+
+with open('pdm_stimulus.txt', 'w') as fd:
+    for i, sample in enumerate(stim):
+        running_sum = running_sum + sample
+        if running_sum > THRESHOLD:
+            running_sum = running_sum - IMPULSE_HEIGHT
+            output_pdm[i] = 1
+
+        fd.write(f"{int(output_pdm[i])}\n")
+
+
+ax = plt.plot(output_pdm)
+ax = plt.plot(stim)
+plt.show()

HDLForBeginners_Examples/30092022_testbench_start_finish/py/receive_fft.py

@@ -0,0 +1,46 @@
+import socket
+import struct
+import numpy as np
+from matplotlib import pyplot as plt
+from matplotlib import animation
+
+ETH_P_ALL=3 # not defined in socket module, sadly...
+s=socket.socket(socket.AF_PACKET, socket.SOCK_RAW, socket.htons(ETH_P_ALL))
+s.bind(("eth0", 0))
+
+fpga_src_dest = b"\x08\x00\x27\xfb\xdd\x65\xe8\x6a\x64\xe7\xe8\x30"
+sample_bytes = 4
+sample_rate = 2.4e6//64
+
+fig = plt.figure()
+ax = plt.axes(xlim=(0, 256), ylim=(0, ( (2**3))))
+line, = ax.plot([], [], lw=2)
+
+# initialization function: plot the background of each frame
+def init():
+    line.set_data([], [])
+    return line,
+
+
+# animation function.  This is called sequentially
+def animate(i):
+    data = None
+    for i in range(0,16):
+        r=s.recv(2000)
+        # Only receive packets from FPGA
+        if r[0:12]==fpga_src_dest:
+            x = np.arange(0,256)
+            y = np.frombuffer(r[14:], ">i4")
+            if data is None:
+                data = np.fft.fftshift((np.abs(np.sqrt(y))))
+            else:
+                data = data + np.fft.fftshift((np.abs((np.sqrt(y)))))
+            line.set_data(x, data/16)
+            return line,
+
+# call the animator.  blit=True means only re-draw the parts that have changed.
+anim = animation.FuncAnimation(fig, animate, init_func=init,
+                               frames=20000, interval=10)
+
+
+plt.show()

HDLForBeginners_Examples/30092022_testbench_start_finish/py/testbench.py

@@ -0,0 +1,30 @@
+from matplotlib import pyplot as plt
+import numpy
+
+with open('output_mic_data.log', 'r') as fd:
+   content = fd.read()
+
+with open('output_mic_data_avg.log', 'r') as fd:
+    content_avg = fd.read()
+
+pdm_data = []
+nums_avg = []
+
+for x in content.split(','):
+     pdm_data.append(int(x))
+
+for x in content_avg.split(','):
+     nums_avg.append(int(x))
+
+
+N = 512
+fs = 3e6/64
+
+window = numpy.hanning(N)
+
+fft_data = numpy.fft.fftshift(numpy.abs(numpy.fft.fft(pdm_data[0:N]*window)))
+x_data = numpy.arange(-N/2,N/2)*fs*2/N
+
+
+ax = plt.plot(x_data,fft_data)
+plt.show()

HDLForBeginners_Examples/30092022_testbench_start_finish/src/crc_gen.sv

@@ -0,0 +1,103 @@
+`timescale 1ps / 1ps
+
+//////////////////////////////////////////////////////////////////////////////////
+// Company: HdlForBeginners
+// Engineer:
+//
+// Create Date: 13.11.2021 13:55:40
+// Design Name:
+// Module Name: crc_gen
+// Project Name:
+// Target Devices:
+// Tool Versions:
+// Description:
+//
+// Dependencies:
+//
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+module crc_gen
+  (
+   input [1:0]   data_in,
+   input         crc_en,
+   output [31:0] crc_out,
+   input         rst,
+   input         clk);
+
+   logic [31:0]  lfsr_q,lfsr_c;
+
+   // xor on the output
+   assign crc_out = lfsr_c ^ 32'hffffffff;
+
+   // used https://bues.ch/cms/hacking/crcgen to generate this code
+
+   // -------------------------------------------------------------------------
+   // THIS IS GENERATED VERILOG CODE.
+   // https://bues.ch/h/crcgen
+   //
+   // This code is Public Domain.
+   // Permission to use, copy, modify, and/or distribute this software for any
+   // purpose with or without fee is hereby granted.
+   //
+   // THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+   // WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+   // MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+   // SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER
+   // RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT,
+   // NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE
+   // USE OR PERFORMANCE OF THIS SOFTWARE.
+
+   // CRC polynomial coefficients: x^32 + x^26 + x^23 + x^22 + x^16 + x^12 + x^11 + x^10 + x^8 + x^7 + x^5 + x^4 + x^2 + x + 1
+   //                              0xEDB88320 (hex)
+   // CRC width:                   32 bits
+   // CRC shift direction:         right (little endian)
+   // Input word width:            2 bits
+
+   assign lfsr_c[0] = lfsr_q[2];
+   assign lfsr_c[1] = lfsr_q[3];
+   assign lfsr_c[2] = lfsr_q[4];
+   assign lfsr_c[3] = lfsr_q[5];
+   assign lfsr_c[4] = (data_in[0] ^ lfsr_q[0] ^ lfsr_q[6]);
+   assign lfsr_c[5] = (data_in[1] ^ lfsr_q[1] ^ lfsr_q[7]);
+   assign lfsr_c[6] = lfsr_q[8];
+   assign lfsr_c[7] = (data_in[0] ^ lfsr_q[0] ^ lfsr_q[9]);
+   assign lfsr_c[8] = (data_in[0] ^ data_in[1] ^ lfsr_q[0] ^ lfsr_q[1] ^ lfsr_q[10]);
+   assign lfsr_c[9] = (data_in[1] ^ lfsr_q[1] ^ lfsr_q[11]);
+   assign lfsr_c[10] = lfsr_q[12];
+   assign lfsr_c[11] = lfsr_q[13];
+   assign lfsr_c[12] = lfsr_q[14];
+   assign lfsr_c[13] = lfsr_q[15];
+   assign lfsr_c[14] = (data_in[0] ^ lfsr_q[0] ^ lfsr_q[16]);
+   assign lfsr_c[15] = (data_in[1] ^ lfsr_q[1] ^ lfsr_q[17]);
+   assign lfsr_c[16] = lfsr_q[18];
+   assign lfsr_c[17] = lfsr_q[19];
+   assign lfsr_c[18] = (data_in[0] ^ lfsr_q[0] ^ lfsr_q[20]);
+   assign lfsr_c[19] = (data_in[0] ^ data_in[1] ^ lfsr_q[0] ^ lfsr_q[1] ^ lfsr_q[21]);
+   assign lfsr_c[20] = (data_in[0] ^ data_in[1] ^ lfsr_q[0] ^ lfsr_q[1] ^ lfsr_q[22]);
+   assign lfsr_c[21] = (data_in[1] ^ lfsr_q[1] ^ lfsr_q[23]);
+   assign lfsr_c[22] = (data_in[0] ^ lfsr_q[0] ^ lfsr_q[24]);
+   assign lfsr_c[23] = (data_in[0] ^ data_in[1] ^ lfsr_q[0] ^ lfsr_q[1] ^ lfsr_q[25]);
+   assign lfsr_c[24] = (data_in[1] ^ lfsr_q[1] ^ lfsr_q[26]);
+   assign lfsr_c[25] = (data_in[0] ^ lfsr_q[0] ^ lfsr_q[27]);
+   assign lfsr_c[26] = (data_in[0] ^ data_in[1] ^ lfsr_q[0] ^ lfsr_q[1] ^ lfsr_q[28]);
+   assign lfsr_c[27] = (data_in[1] ^ lfsr_q[1] ^ lfsr_q[29]);
+   assign lfsr_c[28] = (data_in[0] ^ lfsr_q[0] ^ lfsr_q[30]);
+   assign lfsr_c[29] = (data_in[0] ^ data_in[1] ^ lfsr_q[0] ^ lfsr_q[1] ^ lfsr_q[31]);
+   assign lfsr_c[30] = (data_in[0] ^ data_in[1] ^ lfsr_q[0] ^ lfsr_q[1]);
+   assign lfsr_c[31] = (data_in[1] ^ lfsr_q[1]);
+
+   // -------------------------------------------------------------------------
+
+  always @(posedge clk, posedge rst) begin
+    if(rst) begin
+      lfsr_q <= {32{1'b1}};
+    end
+    else begin
+      lfsr_q <= crc_en ? lfsr_c : lfsr_q;
+    end
+  end // always
+endmodule // crc

HDLForBeginners_Examples/30092022_testbench_start_finish/src/dc_removal.sv

@@ -0,0 +1,85 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company:
+// Engineer:
+//
+// Create Date: 13.11.2021 14:32:12
+// Design Name:
+// Module Name: rst_gen
+// Project Name:
+// Target Devices:
+// Tool Versions:
+// Description:
+//
+// Dependencies:
+//
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module dc_removal
+  #(
+    parameter DATA_WIDTH = 32
+    )
+   (
+    input                   clk,
+    input                   rst,
+    input                   clk_en,
+
+    // x in
+    input [DATA_WIDTH-1:0]  s_axis_data_tdata,
+
+    // y out
+    output [DATA_WIDTH-1:0] m_axis_data_tdata
+
+
+    );
+
+
+   // Real-Time DC Removal
+   // https://www.embedded.com/dsp-tricks-dc-removal/
+   // Figure 13(b)
+
+
+   // 973/1024 = 0.95
+   localparam a_coeff_num = 973;
+   localparam a_coeff_denom_pow2 = 10;
+
+
+   logic signed [DATA_WIDTH-1:0] x_data;
+   logic signed [DATA_WIDTH-1:0] y_data;
+   logic signed [DATA_WIDTH-1:0] f_data;
+   logic signed [DATA_WIDTH-1:0] f_data_q;
+   logic signed [DATA_WIDTH-1:0] f_data_q_multa;
+
+   // drive input signal
+   assign x_data = s_axis_data_tdata;
+
+   // f = x(n) + f_q*a
+   assign f_data = x_data + f_data_q_multa;
+
+   // fq*a = fq*a
+   assign f_data_q_multa = f_data_q*a_coeff_num >>> a_coeff_denom_pow2;
+
+   // y = f - f_q
+   assign y_data = f_data - f_data_q;
+
+   // f_q
+   always_ff@(posedge clk) begin
+      if (rst) begin
+         f_data_q <= 0;
+
+      end
+      else if (clk_en) begin
+         f_data_q <= f_data;
+
+      end
+   end
+
+   assign m_axis_data_tdata = y_data;
+
+
+endmodule

HDLForBeginners_Examples/30092022_testbench_start_finish/src/endian_switch.sv

@@ -0,0 +1,48 @@
+// HDLbits example excercise "vector2"
+// https://hdlbits.01xz.net/wiki/Vector2
+
+
+module endian_switch
+    #(
+    parameter BYTE_SIZE = 8,
+    parameter INPUT_BYTES = 4
+    )
+    (
+    input [INPUT_BYTES*BYTE_SIZE-1:0] in,
+    
+    // both array and flat versions are driven
+    // connect up as required
+    output [INPUT_BYTES*BYTE_SIZE-1:0] out,
+    output [INPUT_BYTES-1:0][BYTE_SIZE-1:0] out_array
+    
+    );//
+
+
+   // $size gives number of bits in a vector
+   localparam NUM_BYTES = INPUT_BYTES;
+
+   // generate variable
+   genvar             i;
+   generate
+      for (i = 1;i<=NUM_BYTES;i++) begin : endian_switch_for  // loop name
+         // mimics the same format as intermediate, but this just automatically expands based on the constants
+         assign out[i*BYTE_SIZE-1 -: BYTE_SIZE] = in[(NUM_BYTES-i+1)*BYTE_SIZE-1 -: BYTE_SIZE];
+         
+         // Array driven too
+         // for arrays, they are indexed in the same order as declared
+         // out_array is declared as [INPUT_BYTES-1:0][BYTE_SIZE-1:0] 
+         // so assign out_array[x][y] 
+         // x -> INPUT_BYTES dimension
+         // y -> BYTE_SIZE dimension.
+         // right-side dimensions can be left off 
+         // assign out_array[x] is OK (as seen below), but there is no way to index [y] on its own
+         // so be careful to get the order right according to the application.
+         // else manual dimension switch is required
+         assign out_array[i-1] = in[(NUM_BYTES-i+1)*BYTE_SIZE-1 -: BYTE_SIZE];
+      end
+   endgenerate
+
+
+
+
+endmodule

HDLForBeginners_Examples/30092022_testbench_start_finish/src/eth_header_gen.sv

@@ -0,0 +1,47 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company:
+// Engineer:
+//
+// Create Date: 13.11.2021 13:55:40
+// Design Name:eth_header_gen
+// Module Name:
+// Project Name:
+// Target Devices:
+// Tool Versions:
+// Description:
+// Creates an ethernet header object based on supplied parameters
+// Dependencies:
+//
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+import ethernet_header_pkg::*;
+
+module eth_header_gen
+  #(
+    parameter [47:0] SOURCE_MAC = 48'he86a64e7e830,
+    parameter [47:0] DEST_MAC = 48'he86a64e7e829,
+    parameter [15:0] PACKET_PAYLOAD_BYTES = 128
+
+    )
+   (
+
+     output ethernet_header output_header
+
+    );
+
+
+   ethernet_header header;
+
+   // Endian switch parameters
+   endian_switch #( .BYTE_SIZE(8), .INPUT_BYTES(6) ) endian_switch_src_mac ( .in(SOURCE_MAC), .out_array(header.mac_source) );
+   endian_switch #( .BYTE_SIZE(8), .INPUT_BYTES(6) ) endian_switch_dest_mac ( .in(DEST_MAC), .out_array(header.mac_destination) );
+   endian_switch #( .BYTE_SIZE(8), .INPUT_BYTES(2) ) endian_switch_ipv4_length ( .in(PACKET_PAYLOAD_BYTES), .out_array(header.eth_type_length));
+
+   assign output_header = header;
+
+endmodule

HDLForBeginners_Examples/30092022_testbench_start_finish/src/eth_rst_gen.sv

@@ -0,0 +1,89 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company:
+// Engineer:
+//
+// Create Date: 13.11.2021 14:32:12
+// Design Name:
+// Module Name: eth_rst_gen
+// Project Name:
+// Target Devices:
+// Tool Versions:
+// Description:
+//
+// Dependencies:
+//
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module eth_rst_gen(
+    input clk,
+    input rst,
+    output eth_clk_out,
+    output eth_rst_out,
+    output ETH_REFCLK,
+    output ETH_RSTN
+    );
+
+    logic locked;
+    logic eth_rst;
+    logic eth_clk;
+
+
+    // 50M clk gen
+  clk_wiz_0 gen_50M
+   (
+    .clk_out1(eth_clk),         // output clk_out1
+    .clk_out2(ETH_REFCLK),     // output clk_out2
+    .reset(rst),            // input reset
+    .locked(locked),           // output locked
+    .clk_in1(clk));         // input clk_in1
+
+
+`ifdef XILINX_SIMULATOR
+   // So simulation doesn't have to wait so long to come out of reset
+   localparam WAIT_CYCLES_50M = 20;
+`else
+   // synthesis uses full 40ms
+   localparam WAIT_CYCLES_50M = 2000000; // 40ms
+`endif
+    logic [31:0] wait_counter_50M;
+
+    // Generate output reset signals in 50M domain
+    always_ff@(posedge eth_clk) begin
+        // remain in reset until global reset is released
+        if (rst) begin
+            eth_rst <= 1;
+            wait_counter_50M <= 0;
+        end
+        else begin
+            // PLL locked
+            if (locked) begin
+                // remain in rst till counter is done
+                if (wait_counter_50M < WAIT_CYCLES_50M-1) begin
+                    eth_rst <= 1;
+                    wait_counter_50M <= wait_counter_50M + 1;
+                end
+                else begin
+                    eth_rst <= 0;
+                end
+            end
+            // PLL not locked. Remain in reset until locked
+            else begin
+                eth_rst <= 1;
+                wait_counter_50M <= 0;
+
+
+            end
+        end
+    end
+
+    assign ETH_RSTN = ~eth_rst;
+    assign eth_clk_out = eth_clk;
+    assign eth_rst_out = eth_rst;
+
+endmodule

HDLForBeginners_Examples/30092022_testbench_start_finish/src/ethernet_header_pkg.sv

@@ -0,0 +1,22 @@
+//////////////////////////////////////////////////////////////////////////////////
+// Company: HDLForBeginners
+// Engineer: Stacey
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+package ethernet_header_pkg;
+
+   // Order matters
+   // Must be defined in the file before being used.
+
+   typedef struct      packed {
+      // Ethernet Frame Header
+      // no FCS, added later
+      logic [1:0][7:0] eth_type_length;
+      logic [5:0][7:0] mac_source;
+      logic [5:0][7:0] mac_destination;
+   } ethernet_header;
+
+
+
+endpackage

HDLForBeginners_Examples/30092022_testbench_start_finish/src/ethernet_top.sv

@@ -0,0 +1,250 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company:
+// Engineer:
+//
+// Create Date: 12.11.2021 22:54:19
+// Design Name:
+// Module Name: ethernet_top
+// Project Name:
+// Target Devices:
+// Tool Versions:
+// Description:
+//
+// Dependencies:
+//
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module ethernet_top
+  (
+   input        CLK,
+   input        RST_N,
+
+   // Microphone
+   output       M_CLK,
+   input        M_DATA,
+   output       M_LRSEL,
+
+
+   output       ETH_MDC,
+   inout        ETH_MDIO,
+   output       ETH_RSTN,
+   inout        ETH_CRSDV,
+   input        ETH_RXERR,
+   inout [1:0]  ETH_RXD,
+   output       ETH_TXEN,
+   output [1:0] ETH_TXD,
+   output       ETH_REFCLK,
+   input        ETH_INTN
+   );
+
+
+   logic        rst;
+
+   rst_gen rst_gen_i
+     (
+      .clk_in(CLK),
+      .rst_in(~RST_N),
+      .rst_out(rst)
+
+      );
+
+   logic        eth_clk;
+   logic        eth_rst;
+
+   // Boot Mode config
+   // Mode 111
+   assign ETH_CRSDV  = (eth_rst) ? 1 : 1'bz;
+   assign ETH_RXD[0] = (eth_rst) ? 1 : 1'bz;
+   assign ETH_RXD[1] = (eth_rst) ? 1 : 1'bz;
+
+   // No mdio interface
+   assign ETH_MDC = 0;
+
+   eth_rst_gen eth_rst_gen_i
+     (
+      .clk(CLK),
+      .rst(rst),
+      .eth_clk_out(eth_clk),
+      .eth_rst_out(eth_rst),
+      .ETH_REFCLK(ETH_REFCLK),
+      .ETH_RSTN(ETH_RSTN)
+      );
+
+   // Timer to generate a packet after every interval
+   logic [63:0] packet_timer;
+
+   // if simulating, send packets more often
+`ifdef XILINX_SIMULATOR
+   localparam packet_max = 2_000;
+`else
+   localparam packet_max = 600;
+`endif
+
+   // PDM MICROPHONE
+
+   localparam MIC_DATA_INT = 1;
+   localparam MIC_DATA_FRAC = 31;
+
+   logic signed [MIC_DATA_INT-1:-MIC_DATA_FRAC] mic_data;
+   logic                                        mic_data_valid;
+
+
+   // 2.4M out
+   pdm_microphone
+     #(
+       .INPUT_FREQ(50_000_000),
+       .PDM_FREQ(2_400_000) // 2.4M out
+
+       )
+   pdm_microphone_i
+     (
+      .clk(eth_clk),
+      .rst(eth_rst),
+
+      .mic_data(mic_data),
+      .mic_data_valid(mic_data_valid),
+
+
+      .M_CLK(M_CLK),
+      .M_DATA(M_DATA),
+      .M_LRSEL(M_LRSEL)
+
+      );
+
+
+
+   parameter PACKET_PAYLOAD_WORDS = 256;
+   parameter WORD_BYTES = 4;
+   localparam WINDOW_INT = 1;
+   localparam WINDOW_FRAC = 16;
+
+   logic signed [WINDOW_INT-1:-WINDOW_FRAC]     window_out;
+   logic                                        window_out_valid;
+   logic                                        window_out_last;
+   logic                                        window_out_ready;
+
+
+   parzen
+     #(
+       .WINDOW_SIZE_POW2($clog2(PACKET_PAYLOAD_WORDS)),
+       .INTERNAL_FRAC(16),
+       .OUTPUT_INT(WINDOW_INT),
+       .OUTPUT_FRAC(WINDOW_FRAC)
+       )
+   parzen_i
+     (
+      .clk(eth_clk),
+      .rst(eth_rst),
+
+      .window_out_ready(window_out_ready),
+      .window_out(window_out),
+      .window_out_valid(window_out_valid),
+      .window_out_last(window_out_last)
+
+      );
+
+   assign window_out_ready = windowed_data_ready & mic_data_valid;
+
+   // combined axi stream interface
+   // Apply window by multiplying mic data with parzen
+   localparam WINDOWED_DATA_INT = MIC_DATA_INT + WINDOW_INT;
+   localparam WINDOWED_DATA_FRAC = MIC_DATA_FRAC + WINDOW_FRAC;
+
+   logic signed [WINDOWED_DATA_INT-1:-WINDOWED_DATA_FRAC] windowed_data_fullscale;
+   logic signed [MIC_DATA_INT-1:-MIC_DATA_FRAC]           windowed_data;
+   logic                                                  windowed_data_valid;
+   logic                                                  windowed_data_last;
+   logic                                                  windowed_data_ready;
+
+
+   assign windowed_data_valid = mic_data_valid & window_out_valid;
+   assign windowed_data_last = window_out_last;
+   //assign windowed_data_fullscale = mic_data*window_out[0:-WINDOW_FRAC];
+
+   window_multiplier  window_multiplier_i
+     (
+      .A(mic_data),  // input wire [28 : 0] A
+      .B(window_out),  // input wire [15 : 0] B
+      .P(windowed_data_fullscale)  // output wire [44 : 0] P
+      );
+
+
+   // reduce to MIC_DATA size
+   assign windowed_data = windowed_data_fullscale[MIC_DATA_INT-1:-MIC_DATA_FRAC];
+
+
+
+   localparam FFT_DATA_INT = 7;
+   localparam FFT_DATA_FRAC = MIC_DATA_FRAC;
+
+   logic signed [95:0]                                    fft_data_fullscale;
+   logic signed [FFT_DATA_INT-1:-FFT_DATA_FRAC]           fft_data_re;
+   logic signed [FFT_DATA_INT-1:-FFT_DATA_FRAC]           fft_data_im;
+   logic signed [FFT_DATA_INT*2-1:-FFT_DATA_FRAC*2]       fft_data_re_sq;
+   logic signed [FFT_DATA_INT*2-1:-FFT_DATA_FRAC*2]       fft_data_im_sq;
+   logic [31:0]                                           fft_data_byteswapped;
+   logic                                                  fft_data_valid;
+   logic                                                  fft_data_last;
+   logic                                                  fft_data_ready;
+   logic [FFT_DATA_INT*2:-FFT_DATA_FRAC*2]                fft_data_sum_squares;
+
+
+   xfft_0  xfft_0_i
+     (
+      .aclk(eth_clk),                                                // input wire aclk
+      .s_axis_config_tdata(1),                  // input wire [7 : 0] s_axis_config_tdata
+      .s_axis_config_tvalid(1),                // input wire s_axis_config_tvalid
+      .s_axis_config_tready(s_axis_config_tready),                // output wire s_axis_config_tready
+      .s_axis_data_tdata({32'b0,windowed_data}),                      // input wire [63 : 0] s_axis_data_tdata
+      .s_axis_data_tvalid(windowed_data_valid),                    // input wire s_axis_data_tvalid
+      .s_axis_data_tready(windowed_data_ready),                    // output wire s_axis_data_tready
+      .s_axis_data_tlast(windowed_data_last),                      // input wire s_axis_data_tlast
+      .m_axis_data_tdata(fft_data_fullscale),                      // output wire [95 : 0] m_axis_data_tdata
+      .m_axis_data_tvalid(fft_data_valid),                    // output wire m_axis_data_tvalid
+      .m_axis_data_tready(fft_data_ready),                    // input wire m_axis_data_tready
+      .m_axis_data_tlast(fft_data_last),                      // output wire m_axis_data_tlast
+      .event_frame_started(event_frame_started),                  // output wire event_frame_started
+      .event_tlast_unexpected(event_tlast_unexpected),            // output wire event_tlast_unexpected
+      .event_tlast_missing(event_tlast_missing),                  // output wire event_tlast_missing
+      .event_status_channel_halt(event_status_channel_halt),      // output wire event_status_channel_halt
+      .event_data_in_channel_halt(event_data_in_channel_halt),    // output wire event_data_in_channel_halt
+      .event_data_out_channel_halt(event_data_out_channel_halt)  // output wire event_data_out_channel_halt
+      );
+
+
+   assign fft_data_re = fft_data_fullscale[37:0];
+   assign fft_data_im = fft_data_fullscale[77:40];
+   assign fft_data_re_sq  = fft_data_re*fft_data_re;
+   assign fft_data_im_sq  = fft_data_im*fft_data_im;
+   assign fft_data_sum_squares = fft_data_re_sq + fft_data_im_sq;
+
+
+   endian_switch #( .BYTE_SIZE(8), .INPUT_BYTES(WORD_BYTES) ) endian_switch_data ( .in(fft_data_sum_squares[FFT_DATA_INT-1 -: 32]), .out(fft_data_byteswapped) );
+
+
+   packet_gen
+     #(
+       .PACKET_PAYLOAD_WORDS(PACKET_PAYLOAD_WORDS),
+       .WORD_BYTES(WORD_BYTES),
+       .DEST_MAC(48'h080027fbdd65)
+       )
+   packet_gen_i
+     (
+      .clk(eth_clk),
+      .rst(eth_rst),
+      .s_axis_tdata(fft_data_byteswapped),
+      .s_axis_tvalid(fft_data_valid),
+      .s_axis_tlast(fft_data_last),
+      .s_axis_tready(fft_data_ready),
+      .tx_en(ETH_TXEN),
+      .txd(ETH_TXD)
+      );
+
+
+endmodule

HDLForBeginners_Examples/30092022_testbench_start_finish/src/packet_gen.sv

@@ -0,0 +1,471 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: HdlForBeginners
+// Engineer:
+//
+// Create Date: 13.11.2021 13:55:40
+// Design Name:
+// Module Name: packet_gen
+// Project Name:
+// Target Devices:
+// Tool Versions:
+// Description:
+//
+// Dependencies:
+//
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+import ethernet_header_pkg::*;
+
+module packet_gen
+  #(
+    parameter SOURCE_MAC = 48'he86a64e7e830,
+    parameter DEST_MAC = 48'h080027fbdd65,
+    parameter MII_WIDTH = 2,
+    parameter PACKET_PAYLOAD_WORDS = 64,
+    parameter WORD_BYTES = 4
+
+    )
+   (
+    input                        clk,
+    input                        rst,
+
+    input [WORD_BYTES*8-1:0]     s_axis_tdata,
+    input                        s_axis_tvalid,
+    input                        s_axis_tlast,
+    output                       s_axis_tready,
+
+
+    output logic                 tx_en,
+    output logic [MII_WIDTH-1:0] txd
+    );
+
+
+   localparam PACKET_PAYLOAD_BYTES = PACKET_PAYLOAD_WORDS*WORD_BYTES;
+
+   // create a first
+   logic                         s_axis_tfirst;
+
+
+   always_ff @(posedge clk)
+     begin
+	    if(rst) begin
+           s_axis_tfirst <= 1;
+
+	    end
+	    else begin
+           if (s_axis_tvalid && s_axis_tready) begin
+              if (s_axis_tlast) begin
+                 // After tlast pulse, drive first high
+                 s_axis_tfirst <= 1;
+
+              end
+              else begin
+                 // otherwise, drive it low on valid and ready
+                 s_axis_tfirst <= 0;
+
+              end
+           end
+	    end
+     end
+
+
+   // header and state buffers
+   ethernet_header header;
+   logic [$bits(ethernet_header)-1 : 0] header_buffer;
+   logic [WORD_BYTES*8-1:0]             data_buffer;
+   logic [7*8-1:0]                      preamble_buffer;
+   logic [1*8-1:0]                      sfd_buffer;
+   logic [4*8-1:0]                      fcs;
+   logic [4*8-1:0]                      fcs_buffer;
+
+   // Number of bytes transferred in each stage
+   localparam HEADER_BYTES = $bits(ethernet_header)/8;
+   localparam DATA_BYTES = PACKET_PAYLOAD_BYTES;
+   localparam WAIT_BYTES = 12;
+   localparam SFD_BYTES = 1;
+   localparam PREAMBLE_BYTES = 7;
+   localparam FCS_BYTES = 4;
+
+   // RMII interface is MII_WIDTH bits wide, so divide by MII_WIDTH to get the correct
+   // number of iterations per each stage
+   localparam HEADER_LENGTH = HEADER_BYTES*8/MII_WIDTH;
+   localparam WAIT_LENGTH = WAIT_BYTES*8/MII_WIDTH;
+   localparam SFD_LENGTH = SFD_BYTES*8/MII_WIDTH;
+   localparam PREAMBLE_LENGTH = PREAMBLE_BYTES*8/MII_WIDTH;
+   localparam FCS_LENGTH = FCS_BYTES*8/MII_WIDTH;
+   localparam DATA_LENGTH = DATA_BYTES*8/MII_WIDTH;
+   localparam DATA_COUNTER_BITS = $clog2(WORD_BYTES*8/MII_WIDTH);
+
+
+
+   // State machine
+   typedef enum                         {IDLE, PREAMBLE, SFD, HEADER, DATA, FCS, WAIT}  state_type;
+
+   state_type current_state = IDLE;
+   state_type next_state    = IDLE;
+
+   // Data fifo
+   logic                                fifo_full;
+   logic                                fifo_empty;
+   logic [11:0]                         fifo_count;
+   logic [WORD_BYTES*8-1:0]             fifo_out;
+   logic                                fifo_rd_en;
+   logic                                fifo_wr_en;
+   logic                                packet_start_valid;
+   logic                                packet_valid;
+   logic                                fifo_has_space;
+
+   localparam FIFO_DEPTH = 2048;
+
+   assign fifo_has_space = (fifo_count < FIFO_DEPTH-PACKET_PAYLOAD_BYTES ) ? 1 : 0;
+
+   // Packet start is only valid when
+   // First beat of axi stream and
+   // Axis Stream is valid and
+   // Axis Stream is ready and
+   // Space in FIFO
+   // This indicates that this packet has space to go into the fifo
+   // Otherwise, it is skipped
+   assign packet_start_valid = s_axis_tvalid && s_axis_tready && s_axis_tfirst && fifo_has_space;
+
+   // create packet_valid flag
+   always_ff @(posedge clk)
+     begin
+	    if(rst) begin
+           packet_valid <= 0;
+
+	    end
+	    else begin
+           // If the start of this packet is valid
+           if (packet_start_valid) begin
+              // The entire packet is valid
+              packet_valid <= 1;
+
+           end
+
+           // If this is the end of a valid packet
+           if (packet_valid && s_axis_tvalid && s_axis_tready && s_axis_tlast) begin
+              // End of valid packet
+              packet_valid <= 0;
+           end
+	    end
+     end
+
+   // only write a valid packet
+   assign fifo_wr_en = s_axis_tvalid & s_axis_tready & (packet_start_valid || packet_valid);
+
+   // ready if fifo has space
+   assign s_axis_tready = (fifo_has_space & s_axis_tfirst) | packet_valid;
+
+   // Get header
+   eth_header_gen
+     #(
+       .SOURCE_MAC(SOURCE_MAC),
+       .DEST_MAC(DEST_MAC),
+       .PACKET_PAYLOAD_BYTES(PACKET_PAYLOAD_BYTES)
+       )
+   eth_header_gen
+     (
+      .output_header(header)
+
+      );
+
+   data_fifo data_fifo_i
+     (
+      .clk(clk),
+      .srst(rst),
+      .din(s_axis_tdata),
+      .wr_en(fifo_wr_en),
+      .rd_en(fifo_rd_en),
+      .dout(fifo_out),
+      .full(fifo_full),
+      .empty(fifo_empty),
+      .data_count(fifo_count)
+      );
+
+
+   // count the time spent in each state
+   logic [31:0]                         state_counter;
+
+   always @(posedge clk)
+     begin
+	    if(rst) begin
+           state_counter  <= '0;
+
+	    end
+	    else begin
+           if (current_state != next_state) begin
+              state_counter  <= '0;
+
+           end
+           else begin
+              // otherwise increment counter and shift buffer
+              state_counter <= state_counter  + 'd1;
+           end
+	    end
+     end
+
+   // 3 process state machine
+   // 1) decide which state to go into next
+   always @(*)
+     begin
+        case (current_state)
+          IDLE   :
+            begin
+               // If there's enough data in fifo
+               if (fifo_count >= PACKET_PAYLOAD_WORDS) begin
+                  next_state = PREAMBLE;
+
+               end
+               else begin
+                  next_state = current_state;
+
+               end
+            end
+          PREAMBLE:
+            begin
+               if (state_counter == PREAMBLE_LENGTH-1) begin
+                  next_state = SFD;
+               end
+               else begin
+                  next_state = current_state;
+
+               end
+            end
+          SFD:
+            begin
+               if (state_counter == SFD_LENGTH-1) begin
+                  next_state = HEADER;
+               end
+               else begin
+                  next_state = current_state;
+
+               end
+            end
+          HEADER  :
+            begin
+               if (state_counter == HEADER_LENGTH-1) begin
+                  next_state = DATA;
+               end
+               else begin
+                  next_state = current_state;
+
+               end
+            end
+          DATA  :
+            begin
+               if (state_counter == DATA_LENGTH-1) begin
+                  next_state = FCS;
+               end
+               else begin
+                  next_state = current_state;
+
+               end
+            end
+          FCS  :
+            begin
+               if (state_counter == FCS_LENGTH-1) begin
+                  next_state = WAIT;
+               end
+               else begin
+                  next_state = current_state;
+
+               end
+            end
+          WAIT   :
+            begin
+               if (state_counter == WAIT_LENGTH-1) begin
+                  next_state = IDLE;
+               end
+               else begin
+                  next_state = current_state;
+
+               end
+            end
+          default:
+            next_state = current_state;
+        endcase
+     end
+
+   //2) register into that state
+   always @(posedge clk)
+     begin
+	    if(rst) begin
+           current_state <= IDLE;
+	    end
+	    else begin
+           current_state <= next_state;
+	    end
+
+     end
+
+
+   // state dependant variables
+   logic [MII_WIDTH-1:0]                          tx_data;
+   logic                                          tx_valid;
+   logic                                          fcs_en;
+   logic                                          fcs_rst;
+
+   //3) drive output according to state
+   always @(*)
+     begin
+        case (current_state)
+          IDLE   :
+            begin
+               tx_valid = 0;
+               tx_data  = 0;
+               fcs_en   = 0;
+               fcs_rst   = 1;
+
+            end
+          PREAMBLE  :
+            begin
+               tx_valid = 1;
+               tx_data  = preamble_buffer[MII_WIDTH-1:0];
+               fcs_en   = 0;
+               fcs_rst   = 0;
+
+            end
+          SFD  :
+            begin
+               tx_valid = 1;
+               tx_data  = sfd_buffer[MII_WIDTH-1:0];
+               fcs_en   = 0;
+               fcs_rst   = 0;
+            end
+          HEADER  :
+            begin
+               tx_valid = 1;
+               tx_data  = header_buffer[MII_WIDTH-1:0];
+               fcs_en   = 1;
+               fcs_rst   = 0;
+
+            end
+          DATA  :
+            begin
+               tx_valid = 1;
+               tx_data  = data_buffer[MII_WIDTH-1:0];
+               fcs_en   = 1;
+               fcs_rst   = 0;
+
+            end
+          FCS:
+            begin
+               tx_valid = 1;
+               tx_data  = fcs_buffer[MII_WIDTH-1:0];
+               fcs_en   = 0;
+               fcs_rst  = 0;
+
+            end
+          WAIT   :
+            begin
+               tx_valid = 0;
+               tx_data  = 0;
+               fcs_en   = 0;
+               fcs_rst  = 0;
+
+            end
+          default:
+            begin
+               tx_valid = 0;
+               tx_data  = 0;
+               fcs_en   = 0;
+               fcs_rst  = 0;
+
+            end
+        endcase
+     end
+
+   logic [DATA_COUNTER_BITS-1:0] data_ones;
+   assign data_ones = '1;
+
+   // populate and shift buffers according to state
+   always_ff@(posedge clk) begin
+      if (rst == 1) begin
+         header_buffer   <= 0;
+         preamble_buffer <= 0;
+         fifo_rd_en      <= 0;
+
+      end
+      else begin
+         fifo_rd_en      <= 0;
+
+         // buffer loading
+         if (current_state == IDLE) begin
+            header_buffer   <= header;
+            preamble_buffer <= 56'h55555555555555;
+            sfd_buffer      <= 8'hd5;
+         end
+         // and fcs when it's available
+         if (next_state == FCS && current_state != FCS) begin
+            fcs_buffer <= fcs;
+         end
+         // and fcs when it's available
+         if (next_state == DATA && current_state != DATA) begin
+            data_buffer <= fifo_out;
+            fifo_rd_en  <= 1;
+
+         end
+
+         // shift buffers during those states
+         if (current_state == HEADER) begin
+            header_buffer <= header_buffer >> MII_WIDTH;
+         end
+         if (current_state == PREAMBLE) begin
+            preamble_buffer <= preamble_buffer >> MII_WIDTH;
+         end
+         if (current_state == SFD) begin
+            sfd_buffer <= sfd_buffer >> MII_WIDTH;
+         end
+         if (current_state == DATA && next_state == DATA ) begin
+            if (state_counter[DATA_COUNTER_BITS-1:0] == data_ones) begin
+               data_buffer <= fifo_out;
+               fifo_rd_en  <= 1;
+
+            end
+            else begin
+               data_buffer <= data_buffer >> MII_WIDTH;
+            end
+         end
+         if (current_state == FCS) begin
+            fcs_buffer <= fcs_buffer >> MII_WIDTH;
+         end
+      end
+   end
+
+   // crc generator
+   crc_gen crc_gen_i
+     (
+      .clk(clk),
+      .rst(rst || fcs_rst),
+
+      .data_in(tx_data),
+      .crc_en(fcs_en),
+      .crc_out(fcs)
+
+      );
+
+   // Register outputs
+   //drive tx interfaces
+
+   always @(posedge clk)
+
+     begin
+	    if(rst) begin
+           tx_en <= 0;
+
+	    end
+	    else begin
+           tx_en <= tx_valid;
+           txd   <= tx_data;
+
+	    end
+
+     end
+
+endmodule

HDLForBeginners_Examples/30092022_testbench_start_finish/src/parzen.sv

@@ -0,0 +1,262 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: HDLForBeginners
+// Engineer: Stacey
+//
+// Create Date: 14.07.2021 13:47:50
+// Design Name: parzen
+// Module Name: parzen
+// Project Name: parzen
+// Target Devices:
+// Tool Versions:
+// Description:
+//
+// Dependencies:
+//
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module parzen
+  #(
+    parameter WINDOW_SIZE_POW2 = 10,
+    parameter INTERNAL_FRAC = 16,
+    parameter OUTPUT_INT = 1,
+    parameter OUTPUT_FRAC = 16
+    )
+   (
+    input                              clk,
+    input                              rst,
+
+    input                              window_out_ready,
+    output [OUTPUT_INT-1:-OUTPUT_FRAC] window_out,
+    output                             window_out_valid,
+    output                             window_out_last
+
+    );
+
+
+
+   // Sizes
+   // When multiplying, the sizes add.
+   // B * B is B_SIZE + B_SIZE
+   // B2 * B is B2_SIZE + B_SIZE;
+   localparam B_INT  = WINDOW_SIZE_POW2;
+   localparam B2_INT = B_INT + B_INT;
+   localparam B3_INT = B2_INT + B_INT;
+   localparam B_SCALED_INT = B_INT + 3;
+
+   // When multiplying, the fractionals add with the same rules
+   localparam B_FRAC  = INTERNAL_FRAC;
+   localparam B2_FRAC = B_FRAC + B_FRAC;
+   localparam B3_FRAC = B2_FRAC + B_FRAC;
+   localparam B_SCALED_FRAC = B_FRAC;
+
+   //Signals
+
+   logic [WINDOW_SIZE_POW2-1:0]        triangle_q0;
+   logic                               triangle_valid_q0;
+   logic                               triangle_last_q0;
+   logic [WINDOW_SIZE_POW2-1:0]        triangle_q1;
+   logic                               triangle_valid_q1;
+   logic                               triangle_last_q1;
+   logic [WINDOW_SIZE_POW2-1:0]        triangle_q2;
+   logic                               triangle_valid_q2;
+   logic                               triangle_last_q2;
+   logic [WINDOW_SIZE_POW2-1:0]        triangle_q3;
+   logic                               triangle_valid_q3;
+   logic                               triangle_last_q3;
+
+   // also could be
+   // logic [3:0][WINDOW_SIZE_POW2-1:0]  triangle;
+   // logic [3:0]                        triangle_valid;
+   // And indexed with
+   // triangle[3] to indicate the q3 signal
+   // triangle[3][2:0] to bit-slice the 3 lsbs of the q3 signal
+
+
+   // I'm creating individual signals instead of using arrays
+   // to keep it simple
+   logic [B_INT-1:-B_FRAC]             abs_n_q0;
+   logic                               abs_n_valid_q0;
+
+   logic [B_INT-1:-B_FRAC]             b_q0;
+   logic                               b_valid_q0;
+
+   // Also need delayed versions of b
+   logic [B_INT-1:-B_FRAC]             b_q1;
+   logic                               b_valid_q1;
+   logic [B_INT-1:-B_FRAC]             b_q2;
+   logic                               b_valid_q2;
+
+   logic [B2_INT-1:-B2_FRAC]           b2_q0;
+   logic                               b2_valid_q0;
+
+   // And Delayed version of b2
+   logic [B2_INT-1:-B2_FRAC]           b2_q1;
+   logic                               b2_valid_q1;
+   logic [B2_INT-1:-B2_FRAC]           b2_q2;
+   logic                               b2_valid_q2;
+
+   logic [B3_INT-1:-B3_FRAC]           b3_q1;
+   logic                               b3_valid_q1;
+
+   logic [B3_INT-1:-B3_FRAC]           b3_q2;
+   logic                               b3_valid_q2;
+
+   // create scaled values
+   logic [B_SCALED_INT-1:-B_SCALED_FRAC] c6b1_q2;
+   logic [B_SCALED_INT-1:-B_SCALED_FRAC] c6b2_q2;
+   logic [B_SCALED_INT-1:-B_SCALED_FRAC] c6b3_q2;
+   logic [B_SCALED_INT-1:-B_SCALED_FRAC] c2b3_q2;
+   logic                                 cnbn_valid_q2;
+
+   logic [B_SCALED_INT-1:-B_SCALED_FRAC] f1_q2;
+   logic [B_SCALED_INT-1:-B_SCALED_FRAC] f2_q2;
+   logic                                 fn_valid_q2;
+
+   logic signed [B_SCALED_INT-1:-B_SCALED_FRAC] f1_q3;
+   logic signed [B_SCALED_INT-1:-B_SCALED_FRAC] f2_q3;
+   logic                                        fn_valid_q3;
+
+
+   logic [B_SCALED_INT-1:-B_SCALED_FRAC] one_const;
+   logic [B_SCALED_INT-1:-B_SCALED_FRAC] two_const;
+
+   // RULES FOR KEEPING SIGNALS IN SYNC
+   // assign, the q value stays the same
+   // always@(*) block, the q value stays the same
+   // always@(clk) block, the q value goes up by one.
+   // All operations must occur with the same q value signals!
+
+
+   // Stage 0
+   triangle_gen
+     #(
+       .WIDTH_POW2(WINDOW_SIZE_POW2)
+
+       )
+   triangle_gen_i
+     (
+      .clk(clk),
+      .rst(rst),
+
+      .triangle_out_ready(window_out_ready),
+      .triangle_out(triangle_q0),
+      .triangle_out_valid(triangle_valid_q0),
+      .triangle_out_last(triangle_last_q0)
+
+      );
+
+   // abs_n
+   assign abs_n_q0[B_INT-1:0] = triangle_q0;
+   assign abs_n_q0[-1:-B_FRAC] = '0;
+   assign abs_n_valid_q0 = triangle_valid_q0;
+
+
+   //  b = {|n|}/{N/2} = |n| >> (N-1)
+   // |n| is abs_n
+   // N is WINDOW_SIZE_POW2
+   assign b_q0 =  abs_n_q0 >>> (WINDOW_SIZE_POW2 - 1);
+   assign b_valid_q0 = abs_n_valid_q0;
+
+
+   assign b2_q0 = b_q0 * b_q0;
+   assign b2_valid_q0 = b_valid_q0;
+
+
+   // Stage 1
+   // Use registered versions of b and b2 for b3
+   assign b3_q1 = b_q1 * b2_q1;
+   assign b3_valid_q1 = b_valid_q1 * b2_valid_q1;
+
+
+   // Stage 2
+
+   // Up to now, I've been working with full-scale numbers to create my b values
+   // But I need to make them all B Size to combine
+
+   assign c6b1_q2 = b_q2[B_INT-1:-B_FRAC]*6;
+   assign c6b2_q2 = b2_q2[B_INT-1:-B_FRAC]*6;
+   assign c6b3_q2 = b3_q2[B_INT-1:-B_FRAC]*6;
+   assign c2b3_q2 = b3_q2[B_INT-1:-B_FRAC]*2;
+   assign cnbn_valid_q2 = b3_valid_q2;
+
+
+
+   // Polynomials
+
+   assign one_const[B_SCALED_INT-1:0] = 1;
+   assign one_const[-1:-B_SCALED_FRAC] = '0;
+
+   assign two_const[B_SCALED_INT-1:0] = 2;
+   assign two_const[-1:-B_SCALED_FRAC] = '0;
+
+   assign f1_q2       = one_const + c6b3_q2  - c6b2_q2  ;
+   assign f2_q2       = two_const + c6b2_q2  - c6b1_q2  - c2b3_q2 ;
+   assign fn_valid_q2 = cnbn_valid_q2;
+
+   // Stage 3
+   assign window_out = !window_out_valid ? '0 :
+                       (triangle_q3[WINDOW_SIZE_POW2-1:WINDOW_SIZE_POW2-2] > 0) ? f2_q3 :
+                       f1_q3;
+   assign window_out_valid = fn_valid_q3;
+   assign window_out_last = triangle_last_q3;
+
+
+
+   always_ff @(posedge clk)
+     begin
+        if(rst) begin
+           triangle_q1      <= '0;
+           triangle_q2      <= '0;
+           triangle_q3      <= '0;
+           triangle_last_q1 <= 0;
+           triangle_last_q2 <= 0;
+           triangle_last_q3 <= 0;
+
+           b_q1             <= '0;
+           b_valid_q1       <= '0;
+           b_q2             <= '0;
+           b_valid_q2       <= '0;
+           b2_q1            <= '0;
+           b2_valid_q1      <= '0;
+           b2_q2            <= '0;
+           b2_valid_q2      <= '0;
+           b3_q2            <= '0;
+           b3_valid_q2      <= '0;
+           f1_q3            <= '0;
+           f2_q3            <= '0;
+           fn_valid_q3      <= '0;
+
+
+        end
+        else if (window_out_ready) begin
+           triangle_q1 <= triangle_q0;
+           triangle_q2 <= triangle_q1;
+           triangle_q3 <= triangle_q2;
+           triangle_last_q1 <= triangle_last_q0;
+           triangle_last_q2 <= triangle_last_q1;
+           triangle_last_q3 <= triangle_last_q2;
+           b_q1        <= b_q0;
+           b_valid_q1  <= b_valid_q0;
+           b_q2        <= b_q1;
+           b_valid_q2  <= b_valid_q1;
+           b2_q1       <= b2_q0;
+           b2_valid_q1 <= b2_valid_q0;
+           b2_q2       <= b2_q1;
+           b2_valid_q2 <= b2_valid_q1;
+           b3_q2       <= b3_q1;
+           b3_valid_q2 <= b3_valid_q1;
+           f1_q3       <= f1_q2;
+           f2_q3       <= f2_q2;
+           fn_valid_q3 <= fn_valid_q2;
+
+        end
+     end
+
+
+endmodule

HDLForBeginners_Examples/30092022_testbench_start_finish/src/pdm_clk_gen.sv

@@ -0,0 +1,91 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company:
+// Engineer:
+//
+// Create Date: 13.11.2021 14:32:12
+// Design Name:
+// Module Name: pdm_microphone
+// Project Name:
+// Target Devices:
+// Tool Versions:
+// Description:
+//
+// Dependencies:
+//
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module pdm_clk_gen
+  #(
+    parameter INPUT_FREQ = 100000000,
+    parameter OUTPUT_FREQ = 2_500_000 // 2.5M out
+
+    )
+   (
+    input  clk,
+    input  rst,
+
+    output M_CLK,
+    output m_clk_rising
+
+    );
+
+   logic   m_clk_rising_i;
+   logic   m_clk_i;
+
+
+   // generate clock
+   // Clock wizard doesn't generate clocks < 5M.
+   // for clocks < 5M, anything higher use the clock wizard
+   // Why the clock wizard?
+   // - The FPGA has dedocated clock routes that are designed specifically for clock signals
+   // - These get the clocks where they need to go ASAP
+   // - The tool knows these signals are clocks because of a create_clock constraint
+   // - Or if the wizard was used to generate them
+   // - This way the timing analyzer tool knows about them and can use them in the timing analysis
+
+   // This clock is so slow that it doesn't need to be on the dedicated clock paths
+   // All I am doing here is creating an output pulse on the rising edge of the clock
+   // That is used in other logic. It behaves as an enable signal in the clk domain
+
+   // M_CLK is taken off chip to the PDM microphone IC and is not used on the FPGA anywhere.
+
+
+   localparam CLK_DIVIDE = INPUT_FREQ/OUTPUT_FREQ;
+
+   // count clock samples
+   logic [$clog2(CLK_DIVIDE)-1:0] clk_counter;
+
+   always_ff@(posedge clk) begin
+      if (rst) begin
+         clk_counter    <= 0;
+         m_clk_i        <= 0;
+         m_clk_rising_i <= 0;
+
+      end
+      else begin
+         m_clk_rising_i <= 0;
+
+         if (clk_counter < (CLK_DIVIDE/2)-1) begin
+            clk_counter <= clk_counter + 1;
+
+         end
+         else begin
+            clk_counter    <= 0;
+            m_clk_i        <= ~m_clk_i;
+            m_clk_rising_i <= ~m_clk_i;
+
+         end
+      end
+   end
+
+   assign M_CLK = m_clk_i;
+   assign m_clk_rising = m_clk_rising_i;
+
+
+endmodule

HDLForBeginners_Examples/30092022_testbench_start_finish/src/pdm_microphone.sv

@@ -0,0 +1,96 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company:
+// Engineer:
+//
+// Create Date: 13.11.2021 14:32:12
+// Design Name:
+// Module Name: pdm_microphone
+// Project Name:
+// Target Devices:
+// Tool Versions:
+// Description:
+//
+// Dependencies:
+//
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module pdm_microphone
+  #(
+    parameter INPUT_FREQ = 100000000,
+    parameter PDM_FREQ = 2400000
+
+    )
+   (
+    input         clk,
+    input         rst,
+
+    output [31:0] mic_data,
+    output        mic_data_valid,
+
+
+    output        M_CLK,
+    input         M_DATA,
+    output        M_LRSEL
+
+    );
+
+   logic [2:0]      m_data_q;
+   logic            m_clk_rising;
+
+   // triple register data into clk domain
+   always_ff@(posedge clk) begin
+      if (rst) begin
+         m_data_q       <= 0;
+
+      end
+      else begin
+         m_data_q[0]   <= M_DATA;
+         m_data_q[2:1] <= m_data_q[1:0];
+
+      end
+   end
+
+   // clock gen
+   pdm_clk_gen
+     #(
+       .INPUT_FREQ(INPUT_FREQ),
+       .OUTPUT_FREQ(PDM_FREQ)
+
+       )
+   pdm_clk_gen_i
+     (
+      .clk(clk),
+      .rst(rst),
+
+      .M_CLK(M_CLK),
+      .m_clk_rising(m_clk_rising)
+
+      );
+
+   logic [31:0] cic_out_data;
+   logic        cic_out_valid;
+
+   cic_compiler_0 cic_compiler
+     (
+      .aclk(clk),                              // input wire aclk
+      .s_axis_data_tdata({{7{m_data_q[2]}},1'b1}),    // input wire [7 : 0] s_axis_data_tdata
+      //.s_axis_data_tdata({7'b0,m_data_q[2]}),    // input wire [7 : 0] s_axis_data_tdata
+      .s_axis_data_tvalid(m_clk_rising),         // input wire s_axis_data_tvalid
+      .s_axis_data_tready(),   // output wire s_axis_data_tready
+
+      .m_axis_data_tdata(cic_out_data),    // output wire [39 : 0] m_axis_data_tdata
+      .m_axis_data_tvalid(cic_out_valid)  // output wire m_axis_data_tvalid
+      );
+
+
+   assign M_LRSEL = 0;
+   assign mic_data = cic_out_data;
+   assign mic_data_valid = cic_out_valid;
+
+endmodule

HDLForBeginners_Examples/30092022_testbench_start_finish/src/rst_gen.sv

@@ -0,0 +1,45 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 13.11.2021 14:32:12
+// Design Name: 
+// Module Name: rst_gen
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module rst_gen(
+    input clk_in,
+    input rst_in,
+    output rst_out
+
+    );
+    
+    logic [2:0] rst_q;
+    
+    
+    // Triple Register into clk_in domain
+    always_ff@(posedge clk_in) begin
+       rst_q[0] <= rst_in;
+       rst_q[2:1] <= rst_q[1:0];
+       
+    end
+    
+    // internal reset 
+    // only come out of reset when rst_q is all zeros
+    assign rst_out = (rst_q == 0) ? 0 : 1;
+    
+    
+endmodule

HDLForBeginners_Examples/30092022_testbench_start_finish/src/triangle_gen.sv

@@ -0,0 +1,100 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: HDLForBeginners
+// Engineer: Stacey
+//
+// Create Date: 14.07.2021 13:47:50
+// Design Name: triangle_gen
+// Module Name: triangle_gen
+// Project Name: triangle_gen
+// Target Devices:
+// Tool Versions:
+// Description:
+// Increments a counter and and drives an output gpio pin
+//
+// Dependencies:
+//
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module triangle_gen
+  #(
+    parameter WIDTH_POW2 = 10
+
+    )
+   (
+    input                   clk,
+    input                   rst,
+
+    input                   triangle_out_ready,
+    output [WIDTH_POW2-1:0] triangle_out,
+    output                  triangle_out_valid,
+    output                  triangle_out_last
+
+    );
+
+   // Initial value for the window counter
+   localparam WINDOW_COUNTER_INITIAL = 2**(WIDTH_POW2-1);
+
+   logic [WIDTH_POW2-1:0] window_counter;
+   logic                  window_counter_valid;
+
+   // Flag to check if we are counting down or up
+   // This could be a state machine! But a flag will also do.
+   // It is also a state machine, just not an explicit one.
+   logic                        window_counter_down;
+   logic                        window_done;
+
+   assign window_done = ((window_counter == WINDOW_COUNTER_INITIAL) && ~window_counter_down) ? 1 : 0;
+
+   // Valid when not reset
+   assign window_counter_valid = ~rst;
+
+   always_ff @(posedge clk)
+     begin
+	    if(rst) begin
+           window_counter       <= WINDOW_COUNTER_INITIAL-1;
+           window_counter_down  <= 1'b1;
+
+	    end
+	    else if (triangle_out_ready) begin
+           if (window_counter_down) begin
+              if (window_counter == 0) begin
+                 // Done counting down, so switch direction
+                 window_counter_down <= 0;
+                 window_counter <= window_counter + 1;
+              end
+              else begin
+                 // Otherwise, carry on down
+                 window_counter <= window_counter - 1;
+              end
+           end
+           else begin
+              if (window_counter == WINDOW_COUNTER_INITIAL) begin
+                 // Done counting up, so switch direction
+                 window_counter_down <= 1;
+                 window_counter <= window_counter - 1;
+
+              end
+              else begin
+                 // Carry on up
+                 window_counter <= window_counter + 1;
+
+              end
+           end
+
+
+	    end
+     end
+
+
+   assign triangle_out = window_counter;
+   assign triangle_out_valid = window_counter_valid;
+   assign triangle_out_last = window_done;
+
+
+endmodule

HDLForBeginners_Examples/30092022_testbench_start_finish/tb/ethernet_tb.sv

@@ -0,0 +1,104 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company:
+// Engineer:
+//
+// Create Date: 15.11.2021 16:17:08
+// Design Name:
+// Module Name: ethernet_tb
+// Project Name:
+// Target Devices:
+// Tool Versions:
+// Description:
+//
+// Dependencies:
+//
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module ethernet_tb(
+
+    );
+
+
+   // Clock definition
+   localparam CLK_PERIOD = 10; // 50 Mhz (counter is in ns)
+   localparam RST_COUNT = 10; //Clock cycles that reset is high
+
+   logic clk = 0;
+   logic rst;
+
+   always begin
+      clk   = #(CLK_PERIOD/2) ~clk;
+   end
+
+   // reset definition
+   initial begin
+      rst = 1;
+      #(RST_COUNT*CLK_PERIOD);
+      @(posedge clk);
+      rst = 0;
+   end
+
+   logic  lsfr_data;
+   logic  lsfr_clk;
+
+   /*
+   // Gen input data
+   lfsr_8bit  lfsr_8bit_i
+     (
+      .clk(lsfr_clk),
+      .rst(1'b0),
+      .clk_en(1'b1),
+      .data(lsfr_data)
+
+      );*/
+
+   read_stim
+     #(
+       .FILENAME("../../../../../tb/pdm_stimulus.txt"),
+       .LENGTH(1)
+
+       )
+   read_stim_i
+     (
+      .clk(lsfr_clk),
+      .rst(~rst),
+      .data(lsfr_data),
+      .data_valid()
+
+      );
+
+
+   ethernet_top ethernet_top_i
+     (
+      .CLK(clk),
+      .RST_N(~rst),
+
+      .M_CLK(lsfr_clk),
+      .M_DATA(lsfr_data),
+      .M_LRSEL()
+
+      );
+
+
+   log_data
+     #(
+       .FILENAME("output_mic_data.log"),
+       .LENGTH(32)
+
+       )
+   log_data_mic_data
+     (
+      .clk(clk),
+      .rst(rst),
+      .data(ethernet_tb.ethernet_top_i.mic_data),
+      .data_valid(ethernet_tb.ethernet_top_i.mic_data_valid)
+
+      );
+
+endmodule

HDLForBeginners_Examples/30092022_testbench_start_finish/tb/lfsr_8bit.sv

@@ -0,0 +1,51 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: HDLForBeginners
+// Engineer: Stacey
+//
+// Create Date: 14.07.2021 13:47:50
+// Design Name: lfsr_4bit
+// Module Name: lfsr_4bit_top
+// Project Name: lfsr_4bit
+// Target Devices:
+// Tool Versions:
+// Description:
+// Increments a counter and and drives an output gpio pin
+//
+// Dependencies:
+//
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module lfsr_8bit
+  (
+   input 	clk,
+   input 	rst,
+   input    clk_en,
+   output [7:0] data
+   );
+
+
+   logic [8:0] 	lfsr = 8'b11111111;
+   logic [3:0] 	lfsr_feedback;
+   assign lfsr_feedback= {lfsr[7],lfsr[5:3]};
+
+   always @(posedge clk)
+     begin
+	if(rst) begin
+           lfsr <= 8'b11111111;
+
+	end
+	else if (clk_en) begin
+           lfsr[7:1] <= lfsr[6:0];
+           lfsr[0] <= ^lfsr_feedback;
+	end
+     end
+
+   assign data = lfsr;
+
+endmodule

HDLForBeginners_Examples/30092022_testbench_start_finish/tb/log_data.sv

@@ -0,0 +1,41 @@
+`timescale 1ps / 1ps
+
+
+module log_data
+  #(
+    parameter FILENAME = "output.log",
+    parameter LENGTH = 29
+
+    )
+   (
+    input                     clk,
+    input                     rst,
+    input signed [LENGTH-1:0] data,
+    input                     data_valid
+
+    );
+
+
+   integer                    output_err_file;
+
+   initial begin
+      output_err_file  = $fopen(FILENAME, "w");
+
+
+   end
+
+
+   always@(posedge clk) begin
+      if (rst) begin
+
+      end
+      else begin
+         if (data_valid) begin
+            $fwrite(output_err_file,"%d,",data);
+         end
+      end
+   end
+
+
+
+endmodule

HDLForBeginners_Examples/30092022_testbench_start_finish/tb/read_stim.sv

@@ -0,0 +1,53 @@
+`timescale 1ps / 1ps
+
+
+module read_stim
+  #(
+    parameter FILENAME = "output.log",
+    parameter LENGTH = 29
+
+    )
+   (
+    input                      clk,
+    input                      rst,
+    output signed [LENGTH-1:0] data,
+    output                     data_valid
+
+    );
+
+   integer                     input_file;
+   integer                     scan_file;
+
+   initial begin
+      input_file     = $fopen(FILENAME, "r");
+      if (input_file == 0) begin
+         $display("ERROR opening file!!");
+         $finish;
+      end
+   end
+
+   logic [LENGTH-1:0] stim;
+   logic              stim_valid;
+
+
+   initial begin
+      stim       = 0;
+      stim_valid = 0;
+
+      wait(~rst);
+
+      while(!$feof(input_file)) begin
+         scan_file  = $fscanf(input_file, "%d\n", stim);
+         stim_valid = 1;
+
+         @(posedge clk);
+
+      end
+   end
+
+   assign data = stim;
+   assign data_valid = stim_valid;
+
+
+
+endmodule

HDLForBeginners_Examples/LED_Flash/src/led_flash.sv

@@ -0,0 +1,78 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 18.09.2021 12:06:18
+// Design Name: 
+// Module Name: led_flash
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module led_flash(
+    input clk,
+    input rst_n,
+    output led
+    );
+    
+    parameter [63:0] CLK_RATE = 100000000;
+    parameter [63:0]  FLASH_RATE_ON_MS = 1000;
+    parameter [63:0]  FLASH_RATE_OFF_MS = 1000;    
+    
+    parameter [63:0]  FLASH_RATE_ON_CYCLES = CLK_RATE*FLASH_RATE_ON_MS/1000;
+    parameter [63:0]  FLASH_RATE_OFF_CYCLES = CLK_RATE*FLASH_RATE_OFF_MS/1000;
+    
+    logic [31:0] flash_counter;
+    logic on_not_off_flag;
+    
+    
+    
+    always_ff@(posedge clk, negedge rst_n) begin
+       if (rst_n == 0) begin
+           flash_counter <= 0;
+           on_not_off_flag <= 0;
+           
+       end
+       else begin
+           if (on_not_off_flag) begin
+               if (flash_counter < FLASH_RATE_ON_CYCLES-1) begin
+                   flash_counter <= flash_counter + 1;
+                   
+               end  
+               else begin
+                   flash_counter <= 0;
+                   on_not_off_flag <= ~on_not_off_flag;
+                   
+               end
+           end
+           else begin
+               if (flash_counter < FLASH_RATE_OFF_CYCLES-1) begin
+                   flash_counter <= flash_counter + 1;
+                   
+               end  
+               else begin
+                   flash_counter <= 0;
+                   on_not_off_flag <= ~on_not_off_flag;
+               
+               end
+           end  
+       end
+    end
+    
+    assign led = on_not_off_flag;
+    
+    
+    
+    
+endmodule

HDLForBeginners_Examples/LED_Flash/tb/led_flash_tb.sv

@@ -0,0 +1,53 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 18.09.2021 12:30:56
+// Design Name: 
+// Module Name: led_flash_tb
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module led_flash_tb(
+
+    );
+    
+       logic clk = 0;
+       logic rst = 1;
+       
+       // Clock definition
+       localparam CLK_PERIOD = 10; // 100 Mhz (counter is in ns)
+       localparam RST_COUNT = 10; //Clock cycles that reset is high
+       
+       always begin
+          clk   = #(CLK_PERIOD/2) ~clk;
+       end
+       
+       // reset definition
+       initial begin
+          rst = 1;
+          #(RST_COUNT*CLK_PERIOD);
+          @(posedge clk);
+          rst = 0;
+       end
+    
+
+ led_flash 
+ led_flash_i(
+     .clk(clk),
+     .rst_n(~rst),
+     .led()
+    );
+endmodule

HDLForBeginners_Examples/LFSR4Bit/lfsr_4Bit.tcl

@@ -0,0 +1,529 @@
+#*****************************************************************************************
+# Vivado (TM) v2020.2 (64-bit)
+#
+# lfsr_4Bit.tcl: Tcl script for re-creating project 'lfsr_4bit'
+#
+# Generated by Vivado on Fri Jul 23 22:17:45 SAST 2021
+# IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020
+#
+# This file contains the Vivado Tcl commands for re-creating the project to the state*
+# when this script was generated. In order to re-create the project, please source this
+# file in the Vivado Tcl Shell.
+#
+# * Note that the runs in the created project will be configured the same way as the
+#   original project, however they will not be launched automatically. To regenerate the
+#   run results please launch the synthesis/implementation runs as needed.
+#
+#*****************************************************************************************
+# NOTE: In order to use this script for source control purposes, please make sure that the
+#       following files are added to the source control system:-
+#
+# 1. This project restoration tcl script (lfsr_4Bit.tcl) that was generated.
+#
+# 2. The following source(s) files that were local or imported into the original project.
+#    (Please see the '$orig_proj_dir' and '$origin_dir' variable setting below at the start of the script)
+#
+#    <none>
+#
+# 3. The following remote source files that were added to the original project:-
+#
+#    "/home/stacey/git/Examples/LFSR4Bit/src/lfsr_4bit_top.sv"
+#    "/home/stacey/git/Examples/LFSR4Bit/xdc/constraints.xdc"
+#    "/home/stacey/git/Examples/LFSR4Bit/tb/lfsr_4bit_tb.sv"
+#    "/home/stacey/git/Examples/LFSR4Bit/lfsr_4bit_tb_behav.wcfg"
+#
+#*****************************************************************************************
+
+# Check file required for this script exists
+proc checkRequiredFiles { origin_dir} {
+  set status true
+  set files [list \
+   "src/lfsr_4bit_top.sv" \
+   "xdc/constraints.xdc" \
+   "tb/lfsr_4bit_tb.sv" \
+   "lfsr_4bit_tb_behav.wcfg" \
+  ]
+  foreach ifile $files {
+    if { ![file isfile $ifile] } {
+      puts " Could not find remote file $ifile "
+      set status false
+    }
+  }
+
+  return $status
+}
+# Set the reference directory for source file relative paths (by default the value is script directory path)
+set origin_dir  [file dirname [info script]]
+
+# Use origin directory path location variable, if specified in the tcl shell
+if { [info exists ::origin_dir_loc] } {
+  set origin_dir $::origin_dir_loc
+}
+
+# Set the project name
+set _xil_proj_name_ "lfsr_4bit"
+
+# Use project name variable, if specified in the tcl shell
+if { [info exists ::user_project_name] } {
+  set _xil_proj_name_ $::user_project_name
+}
+
+variable script_file
+set script_file "lfsr_4Bit.tcl"
+
+# Help information for this script
+proc print_help {} {
+  variable script_file
+  puts "\nDescription:"
+  puts "Recreate a Vivado project from this script. The created project will be"
+  puts "functionally equivalent to the original project for which this script was"
+  puts "generated. The script contains commands for creating a project, filesets,"
+  puts "runs, adding/importing sources and setting properties on various objects.\n"
+  puts "Syntax:"
+  puts "$script_file"
+  puts "$script_file -tclargs \[--origin_dir <path>\]"
+  puts "$script_file -tclargs \[--project_name <name>\]"
+  puts "$script_file -tclargs \[--help\]\n"
+  puts "Usage:"
+  puts "Name                   Description"
+  puts "-------------------------------------------------------------------------"
+  puts "\[--origin_dir <path>\]  Determine source file paths wrt this path. Default"
+  puts "                       origin_dir path value is \".\", otherwise, the value"
+  puts "                       that was set with the \"-paths_relative_to\" switch"
+  puts "                       when this script was generated.\n"
+  puts "\[--project_name <name>\] Create project with the specified name. Default"
+  puts "                       name is the name of the project from where this"
+  puts "                       script was generated.\n"
+  puts "\[--help\]               Print help information for this script"
+  puts "-------------------------------------------------------------------------\n"
+  exit 0
+}
+
+if { $::argc > 0 } {
+  for {set i 0} {$i < $::argc} {incr i} {
+    set option [string trim [lindex $::argv $i]]
+    switch -regexp -- $option {
+      "--origin_dir"   { incr i; set origin_dir [lindex $::argv $i] }
+      "--project_name" { incr i; set _xil_proj_name_ [lindex $::argv $i] }
+      "--help"         { print_help }
+      default {
+        if { [regexp {^-} $option] } {
+          puts "ERROR: Unknown option '$option' specified, please type '$script_file -tclargs --help' for usage info.\n"
+          return 1
+        }
+      }
+    }
+  }
+}
+
+# Set the directory path for the original project from where this script was exported
+set orig_proj_dir "[file normalize "$origin_dir/lfsr_4bit"]"
+
+# Check for paths and files needed for project creation
+set validate_required 0
+if { $validate_required } {
+  if { [checkRequiredFiles $origin_dir] } {
+    puts "Tcl file $script_file is valid. All files required for project creation is accesable. "
+  } else {
+    puts "Tcl file $script_file is not valid. Not all files required for project creation is accesable. "
+    return
+  }
+}
+
+# Create project
+create_project ${_xil_proj_name_} ${origin_dir}/${_xil_proj_name_} -part xc7z010clg400-1
+
+# Set the directory path for the new project
+set proj_dir [get_property directory [current_project]]
+
+# Set project properties
+set obj [current_project]
+set_property -name "board_part" -value "digilentinc.com:zybo:part0:2.0" -objects $obj
+set_property -name "default_lib" -value "xil_defaultlib" -objects $obj
+set_property -name "enable_vhdl_2008" -value "1" -objects $obj
+set_property -name "ip_cache_permissions" -value "read write" -objects $obj
+set_property -name "ip_output_repo" -value "$proj_dir/${_xil_proj_name_}.cache/ip" -objects $obj
+set_property -name "mem.enable_memory_map_generation" -value "1" -objects $obj
+set_property -name "platform.board_id" -value "zybo" -objects $obj
+set_property -name "platform.description" -value "Vivado generated DSA" -objects $obj
+set_property -name "platform.emu_dir" -value "emu" -objects $obj
+set_property -name "platform.uses_pr" -value "1" -objects $obj
+set_property -name "sim.central_dir" -value "$proj_dir/${_xil_proj_name_}.ip_user_files" -objects $obj
+set_property -name "sim.ip.auto_export_scripts" -value "1" -objects $obj
+set_property -name "simulator_language" -value "Mixed" -objects $obj
+set_property -name "webtalk.xsim_launch_sim" -value "14" -objects $obj
+
+# Create 'sources_1' fileset (if not found)
+if {[string equal [get_filesets -quiet sources_1] ""]} {
+  create_fileset -srcset sources_1
+}
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+set files [list \
+ [file normalize "${origin_dir}/src/lfsr_4bit_top.sv"] \
+]
+add_files -norecurse -fileset $obj $files
+
+# Set 'sources_1' fileset file properties for remote files
+set file "$origin_dir/src/lfsr_4bit_top.sv"
+set file [file normalize $file]
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "SystemVerilog" -objects $file_obj
+
+
+# Set 'sources_1' fileset file properties for local files
+# None
+
+# Set 'sources_1' fileset properties
+set obj [get_filesets sources_1]
+set_property -name "top" -value "lfsr_4bit_top" -objects $obj
+set_property -name "top_auto_set" -value "0" -objects $obj
+
+# Create 'constrs_1' fileset (if not found)
+if {[string equal [get_filesets -quiet constrs_1] ""]} {
+  create_fileset -constrset constrs_1
+}
+
+# Set 'constrs_1' fileset object
+set obj [get_filesets constrs_1]
+
+# Add/Import constrs file and set constrs file properties
+set file "[file normalize "$origin_dir/xdc/constraints.xdc"]"
+set file_added [add_files -norecurse -fileset $obj [list $file]]
+set file "$origin_dir/xdc/constraints.xdc"
+set file [file normalize $file]
+set file_obj [get_files -of_objects [get_filesets constrs_1] [list "*$file"]]
+set_property -name "file_type" -value "XDC" -objects $file_obj
+
+# Set 'constrs_1' fileset properties
+set obj [get_filesets constrs_1]
+
+# Create 'sim_1' fileset (if not found)
+if {[string equal [get_filesets -quiet sim_1] ""]} {
+  create_fileset -simset sim_1
+}
+
+# Set 'sim_1' fileset object
+set obj [get_filesets sim_1]
+set files [list \
+ [file normalize "${origin_dir}/tb/lfsr_4bit_tb.sv"] \
+ [file normalize "${origin_dir}/lfsr_4bit_tb_behav.wcfg"] \
+]
+add_files -norecurse -fileset $obj $files
+
+# Set 'sim_1' fileset file properties for remote files
+set file "$origin_dir/tb/lfsr_4bit_tb.sv"
+set file [file normalize $file]
+set file_obj [get_files -of_objects [get_filesets sim_1] [list "*$file"]]
+set_property -name "file_type" -value "SystemVerilog" -objects $file_obj
+
+
+# Set 'sim_1' fileset file properties for local files
+# None
+
+# Set 'sim_1' fileset properties
+set obj [get_filesets sim_1]
+set_property -name "hbs.configure_design_for_hier_access" -value "1" -objects $obj
+set_property -name "top" -value "lfsr_4bit_tb" -objects $obj
+set_property -name "top_auto_set" -value "0" -objects $obj
+set_property -name "top_lib" -value "xil_defaultlib" -objects $obj
+
+# Set 'utils_1' fileset object
+set obj [get_filesets utils_1]
+# Empty (no sources present)
+
+# Set 'utils_1' fileset properties
+set obj [get_filesets utils_1]
+
+# Create 'synth_1' run (if not found)
+if {[string equal [get_runs -quiet synth_1] ""]} {
+    create_run -name synth_1 -part xc7z010clg400-1 -flow {Vivado Synthesis 2018} -strategy "Vivado Synthesis Defaults" -report_strategy {No Reports} -constrset constrs_1
+} else {
+  set_property strategy "Vivado Synthesis Defaults" [get_runs synth_1]
+  set_property flow "Vivado Synthesis 2018" [get_runs synth_1]
+}
+set obj [get_runs synth_1]
+set_property set_report_strategy_name 1 $obj
+set_property report_strategy {Vivado Synthesis Default Reports} $obj
+set_property set_report_strategy_name 0 $obj
+# Create 'synth_1_synth_report_utilization_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0] "" ] } {
+  create_report_config -report_name synth_1_synth_report_utilization_0 -report_type report_utilization:1.0 -steps synth_design -runs synth_1
+}
+set obj [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0]
+if { $obj != "" } {
+
+}
+set obj [get_runs synth_1]
+set_property -name "strategy" -value "Vivado Synthesis Defaults" -objects $obj
+
+# set the current synth run
+current_run -synthesis [get_runs synth_1]
+
+# Create 'impl_1' run (if not found)
+if {[string equal [get_runs -quiet impl_1] ""]} {
+    create_run -name impl_1 -part xc7z010clg400-1 -flow {Vivado Implementation 2018} -strategy "Vivado Implementation Defaults" -report_strategy {No Reports} -constrset constrs_1 -parent_run synth_1
+} else {
+  set_property strategy "Vivado Implementation Defaults" [get_runs impl_1]
+  set_property flow "Vivado Implementation 2018" [get_runs impl_1]
+}
+set obj [get_runs impl_1]
+set_property set_report_strategy_name 1 $obj
+set_property report_strategy {Vivado Implementation Default Reports} $obj
+set_property set_report_strategy_name 0 $obj
+# Create 'impl_1_init_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_init_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps init_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'impl_1_opt_report_drc_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0] "" ] } {
+  create_report_config -report_name impl_1_opt_report_drc_0 -report_type report_drc:1.0 -steps opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_opt_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'impl_1_power_opt_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps power_opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'impl_1_place_report_io_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0] "" ] } {
+  create_report_config -report_name impl_1_place_report_io_0 -report_type report_io:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_place_report_utilization_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_utilization_0] "" ] } {
+  create_report_config -report_name impl_1_place_report_utilization_0 -report_type report_utilization:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_utilization_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_place_report_control_sets_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_control_sets_0] "" ] } {
+  create_report_config -report_name impl_1_place_report_control_sets_0 -report_type report_control_sets:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_control_sets_0]
+if { $obj != "" } {
+set_property -name "options.verbose" -value "1" -objects $obj
+
+}
+# Create 'impl_1_place_report_incremental_reuse_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0] "" ] } {
+  create_report_config -report_name impl_1_place_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+
+}
+# Create 'impl_1_place_report_incremental_reuse_1' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_1] "" ] } {
+  create_report_config -report_name impl_1_place_report_incremental_reuse_1 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_1]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+
+}
+# Create 'impl_1_place_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_place_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'impl_1_post_place_power_opt_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_power_opt_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_post_place_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_place_power_opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_power_opt_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'impl_1_phys_opt_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps phys_opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'impl_1_route_report_drc_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_drc_0 -report_type report_drc:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_route_report_methodology_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_methodology_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_methodology_0 -report_type report_methodology:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_methodology_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_route_report_power_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_power_0 -report_type report_power:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_route_report_route_status_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_route_status_0 -report_type report_route_status:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_route_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'impl_1_route_report_incremental_reuse_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_route_report_clock_utilization_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_clock_utilization_0 -report_type report_clock_utilization:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_route_report_bus_skew_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_bus_skew_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_bus_skew_0]
+if { $obj != "" } {
+set_property -name "options.warn_on_violation" -value "1" -objects $obj
+
+}
+# Create 'impl_1_post_route_phys_opt_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_post_route_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_route_phys_opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "options.max_paths" -value "10" -objects $obj
+set_property -name "options.warn_on_violation" -value "1" -objects $obj
+
+}
+# Create 'impl_1_post_route_phys_opt_report_bus_skew_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_bus_skew_0] "" ] } {
+  create_report_config -report_name impl_1_post_route_phys_opt_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps post_route_phys_opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_bus_skew_0]
+if { $obj != "" } {
+set_property -name "options.warn_on_violation" -value "1" -objects $obj
+
+}
+set obj [get_runs impl_1]
+set_property -name "strategy" -value "Vivado Implementation Defaults" -objects $obj
+set_property -name "steps.write_bitstream.args.readback_file" -value "0" -objects $obj
+set_property -name "steps.write_bitstream.args.verbose" -value "0" -objects $obj
+
+# set the current impl run
+current_run -implementation [get_runs impl_1]
+
+puts "INFO: Project created:${_xil_proj_name_}"
+# Create 'drc_1' gadget (if not found)
+if {[string equal [get_dashboard_gadgets  [ list "drc_1" ] ] ""]} {
+create_dashboard_gadget -name {drc_1} -type drc
+}
+set obj [get_dashboard_gadgets [ list "drc_1" ] ]
+set_property -name "reports" -value "impl_1#impl_1_route_report_drc_0" -objects $obj
+
+# Create 'methodology_1' gadget (if not found)
+if {[string equal [get_dashboard_gadgets  [ list "methodology_1" ] ] ""]} {
+create_dashboard_gadget -name {methodology_1} -type methodology
+}
+set obj [get_dashboard_gadgets [ list "methodology_1" ] ]
+set_property -name "reports" -value "impl_1#impl_1_route_report_methodology_0" -objects $obj
+
+# Create 'power_1' gadget (if not found)
+if {[string equal [get_dashboard_gadgets  [ list "power_1" ] ] ""]} {
+create_dashboard_gadget -name {power_1} -type power
+}
+set obj [get_dashboard_gadgets [ list "power_1" ] ]
+set_property -name "reports" -value "impl_1#impl_1_route_report_power_0" -objects $obj
+
+# Create 'timing_1' gadget (if not found)
+if {[string equal [get_dashboard_gadgets  [ list "timing_1" ] ] ""]} {
+create_dashboard_gadget -name {timing_1} -type timing
+}
+set obj [get_dashboard_gadgets [ list "timing_1" ] ]
+set_property -name "reports" -value "impl_1#impl_1_route_report_timing_summary_0" -objects $obj
+
+# Create 'utilization_1' gadget (if not found)
+if {[string equal [get_dashboard_gadgets  [ list "utilization_1" ] ] ""]} {
+create_dashboard_gadget -name {utilization_1} -type utilization
+}
+set obj [get_dashboard_gadgets [ list "utilization_1" ] ]
+set_property -name "reports" -value "synth_1#synth_1_synth_report_utilization_0" -objects $obj
+set_property -name "run.step" -value "synth_design" -objects $obj
+set_property -name "run.type" -value "synthesis" -objects $obj
+
+# Create 'utilization_2' gadget (if not found)
+if {[string equal [get_dashboard_gadgets  [ list "utilization_2" ] ] ""]} {
+create_dashboard_gadget -name {utilization_2} -type utilization
+}
+set obj [get_dashboard_gadgets [ list "utilization_2" ] ]
+set_property -name "reports" -value "impl_1#impl_1_place_report_utilization_0" -objects $obj
+
+move_dashboard_gadget -name {utilization_1} -row 0 -col 0
+move_dashboard_gadget -name {power_1} -row 1 -col 0
+move_dashboard_gadget -name {drc_1} -row 2 -col 0
+move_dashboard_gadget -name {timing_1} -row 0 -col 1
+move_dashboard_gadget -name {utilization_2} -row 1 -col 1
+move_dashboard_gadget -name {methodology_1} -row 2 -col 1

HDLForBeginners_Examples/LFSR4Bit/src/lfsr_4bit_top.sv

@@ -0,0 +1,50 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: HDLForBeginners
+// Engineer: Stacey
+// 
+// Create Date: 14.07.2021 13:47:50
+// Design Name: lfsr_4bit
+// Module Name: lfsr_4bit_top
+// Project Name: lfsr_4bit
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// Increments a counter and and drives an output gpio pin
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module lfsr_4bit_top(
+    input clk,
+    input rst,
+    output logic led
+    );
+    
+    
+    logic [3:0] lfsr;
+    
+    always @(posedge clk)
+    begin
+       if(rst) begin
+           lfsr <= 4'b1111;
+ 
+       end
+       else begin
+           lfsr[3] <= lfsr[2]; 
+           lfsr[2] <= lfsr[1]; 
+           lfsr[1] <= lfsr[0]; 
+           lfsr[0] <= lfsr[2]^lfsr[3];           
+       end
+    end
+    
+    
+    assign led = (lfsr > 4'd10) ? 1'b1 : 1'b0;
+            
+endmodule

HDLForBeginners_Examples/LFSR4Bit/tb/lfsr_4bit_tb.sv

@@ -0,0 +1,56 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 14.07.2021 18:18:52
+// Design Name: 
+// Module Name: simple_increment_tb
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+module lfsr_4bit_tb(
+
+    );
+    
+    logic clk = 0;
+    logic rst = 1;
+    logic led;
+    
+    
+    // Clock definition
+    localparam CLK_PERIOD = 20000; // 50 Mhz (counter is in ps)
+    localparam RST_COUNT = 10; //Clock cycles that reset is high
+     
+    always begin
+        clk   = #(CLK_PERIOD/2) ~clk;
+    end
+       
+    // reset definition
+    initial begin
+        rst = 1;
+        #(RST_COUNT*CLK_PERIOD);
+        @(posedge clk);
+        rst = 0;
+    end
+
+    lfsr_4bit_top
+    lfsr_4bit_top_i
+    (
+        .clk(clk),
+        .rst(rst),
+        .led(led)
+        
+        );
+    
+endmodule

HDLForBeginners_Examples/NexysBaseProject/NexysBaseProject.tcl

@@ -0,0 +1,579 @@
+#*****************************************************************************************
+# Vivado (TM) v2020.2 (64-bit)
+#
+# NexysBaseProject.tcl: Tcl script for re-creating project 'NexysBaseProject'
+#
+# Generated by Vivado on Sat Nov 20 12:22:43 SAST 2021
+# IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020
+#
+# This file contains the Vivado Tcl commands for re-creating the project to the state*
+# when this script was generated. In order to re-create the project, please source this
+# file in the Vivado Tcl Shell.
+#
+# * Note that the runs in the created project will be configured the same way as the
+#   original project, however they will not be launched automatically. To regenerate the
+#   run results please launch the synthesis/implementation runs as needed.
+#
+#*****************************************************************************************
+# NOTE: In order to use this script for source control purposes, please make sure that the
+#       following files are added to the source control system:-
+#
+# 1. This project restoration tcl script (NexysBaseProject.tcl) that was generated.
+#
+# 2. The following source(s) files that were local or imported into the original project.
+#    (Please see the '$orig_proj_dir' and '$origin_dir' variable setting below at the start of the script)
+#
+#    <none>
+#
+# 3. The following remote source files that were added to the original project:-
+#
+#    "ip/clk_wiz_0/clk_wiz_0.xci"
+#    "src/debounce.sv"
+#    "src/edge_detect.sv"
+#    "src/eth_rst_gen.sv"
+#    "src/rst_gen.sv"
+#    "src/NexysBaseProject_top.sv"
+#    "xdc/Nexys-A7-100T-Master.xdc"
+#    "tb/NexysBaseProject_tb.sv"
+#
+#*****************************************************************************************
+
+# Check file required for this script exists
+proc checkRequiredFiles { origin_dir} {
+  set status true
+  set files [list \
+   "ip/clk_wiz_0/clk_wiz_0.xci" \
+   "src/debounce.sv" \
+   "src/edge_detect.sv" \
+   "src/eth_rst_gen.sv" \
+   "src/rst_gen.sv" \
+   "src/NexysBaseProject_top.sv" \
+   "xdc/Nexys-A7-100T-Master.xdc" \
+   "tb/NexysBaseProject_tb.sv" \
+  ]
+  foreach ifile $files {
+    if { ![file isfile $ifile] } {
+      puts " Could not find remote file $ifile "
+      set status false
+    }
+  }
+
+  return $status
+}
+# Set the reference directory for source file relative paths (by default the value is script directory path)
+set origin_dir [file dirname [info script]]
+
+# Use origin directory path location variable, if specified in the tcl shell
+if { [info exists ::origin_dir_loc] } {
+  set origin_dir $::origin_dir_loc
+}
+
+# Set the project name
+set _xil_proj_name_ "NexysBaseProject"
+
+# Use project name variable, if specified in the tcl shell
+if { [info exists ::user_project_name] } {
+  set _xil_proj_name_ $::user_project_name
+}
+
+variable script_file
+set script_file "NexysBaseProject.tcl"
+
+# Help information for this script
+proc print_help {} {
+  variable script_file
+  puts "\nDescription:"
+  puts "Recreate a Vivado project from this script. The created project will be"
+  puts "functionally equivalent to the original project for which this script was"
+  puts "generated. The script contains commands for creating a project, filesets,"
+  puts "runs, adding/importing sources and setting properties on various objects.\n"
+  puts "Syntax:"
+  puts "$script_file"
+  puts "$script_file -tclargs \[--origin_dir <path>\]"
+  puts "$script_file -tclargs \[--project_name <name>\]"
+  puts "$script_file -tclargs \[--help\]\n"
+  puts "Usage:"
+  puts "Name                   Description"
+  puts "-------------------------------------------------------------------------"
+  puts "\[--origin_dir <path>\]  Determine source file paths wrt this path. Default"
+  puts "                       origin_dir path value is \".\", otherwise, the value"
+  puts "                       that was set with the \"-paths_relative_to\" switch"
+  puts "                       when this script was generated.\n"
+  puts "\[--project_name <name>\] Create project with the specified name. Default"
+  puts "                       name is the name of the project from where this"
+  puts "                       script was generated.\n"
+  puts "\[--help\]               Print help information for this script"
+  puts "-------------------------------------------------------------------------\n"
+  exit 0
+}
+
+if { $::argc > 0 } {
+  for {set i 0} {$i < $::argc} {incr i} {
+    set option [string trim [lindex $::argv $i]]
+    switch -regexp -- $option {
+      "--origin_dir"   { incr i; set origin_dir [lindex $::argv $i] }
+      "--project_name" { incr i; set _xil_proj_name_ [lindex $::argv $i] }
+      "--help"         { print_help }
+      default {
+        if { [regexp {^-} $option] } {
+          puts "ERROR: Unknown option '$option' specified, please type '$script_file -tclargs --help' for usage info.\n"
+          return 1
+        }
+      }
+    }
+  }
+}
+
+# Set the directory path for the original project from where this script was exported
+set orig_proj_dir "[file normalize "$origin_dir/NexysBaseProject"]"
+
+# Check for paths and files needed for project creation
+set validate_required 0
+if { $validate_required } {
+  if { [checkRequiredFiles $origin_dir] } {
+    puts "Tcl file $script_file is valid. All files required for project creation is accesable. "
+  } else {
+    puts "Tcl file $script_file is not valid. Not all files required for project creation is accesable. "
+    return
+  }
+}
+
+# Create project
+create_project ${_xil_proj_name_} ${origin_dir}/${_xil_proj_name_} -part xc7z010clg400-1
+
+# Set the directory path for the new project
+set proj_dir [get_property directory [current_project]]
+
+# Set project properties
+set obj [current_project]
+set_property -name "board_part" -value "digilentinc.com:nexys-a7-100t:part0:1.0" -objects $obj
+set_property -name "default_lib" -value "xil_defaultlib" -objects $obj
+set_property -name "enable_vhdl_2008" -value "1" -objects $obj
+set_property -name "ip_cache_permissions" -value "read write" -objects $obj
+set_property -name "ip_output_repo" -value "$proj_dir/${_xil_proj_name_}.cache/ip" -objects $obj
+set_property -name "mem.enable_memory_map_generation" -value "1" -objects $obj
+set_property -name "platform.board_id" -value "nexys-a7-100t" -objects $obj
+set_property -name "platform.description" -value "Vivado generated DSA" -objects $obj
+set_property -name "platform.emu_dir" -value "emu" -objects $obj
+set_property -name "platform.uses_pr" -value "1" -objects $obj
+set_property -name "sim.central_dir" -value "$proj_dir/${_xil_proj_name_}.ip_user_files" -objects $obj
+set_property -name "sim.ip.auto_export_scripts" -value "1" -objects $obj
+set_property -name "simulator_language" -value "Mixed" -objects $obj
+set_property -name "webtalk.activehdl_export_sim" -value "8" -objects $obj
+set_property -name "webtalk.ies_export_sim" -value "8" -objects $obj
+set_property -name "webtalk.modelsim_export_sim" -value "8" -objects $obj
+set_property -name "webtalk.questa_export_sim" -value "8" -objects $obj
+set_property -name "webtalk.riviera_export_sim" -value "8" -objects $obj
+set_property -name "webtalk.vcs_export_sim" -value "8" -objects $obj
+set_property -name "webtalk.xcelium_export_sim" -value "6" -objects $obj
+set_property -name "webtalk.xsim_export_sim" -value "8" -objects $obj
+set_property -name "webtalk.xsim_launch_sim" -value "42" -objects $obj
+set_property -name "xpm_libraries" -value "XPM_CDC" -objects $obj
+
+# Create 'sources_1' fileset (if not found)
+if {[string equal [get_filesets -quiet sources_1] ""]} {
+  create_fileset -srcset sources_1
+}
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+set files [list \
+ [file normalize "${origin_dir}/ip/clk_wiz_0/clk_wiz_0.xci"] \
+ [file normalize "${origin_dir}/src/debounce.sv"] \
+ [file normalize "${origin_dir}/src/edge_detect.sv"] \
+ [file normalize "${origin_dir}/src/eth_rst_gen.sv"] \
+ [file normalize "${origin_dir}/src/rst_gen.sv"] \
+ [file normalize "${origin_dir}/src/NexysBaseProject_top.sv"] \
+]
+add_files -norecurse -fileset $obj $files
+
+# Set 'sources_1' fileset file properties for remote files
+set file "$origin_dir/ip/clk_wiz_0/clk_wiz_0.xci"
+set file [file normalize $file]
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+set file "$origin_dir/src/debounce.sv"
+set file [file normalize $file]
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "SystemVerilog" -objects $file_obj
+
+set file "$origin_dir/src/edge_detect.sv"
+set file [file normalize $file]
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "SystemVerilog" -objects $file_obj
+
+set file "$origin_dir/src/eth_rst_gen.sv"
+set file [file normalize $file]
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "SystemVerilog" -objects $file_obj
+
+set file "$origin_dir/src/rst_gen.sv"
+set file [file normalize $file]
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "SystemVerilog" -objects $file_obj
+
+set file "$origin_dir/src/NexysBaseProject_top.sv"
+set file [file normalize $file]
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "SystemVerilog" -objects $file_obj
+
+
+# Set 'sources_1' fileset file properties for local files
+# None
+
+# Set 'sources_1' fileset properties
+set obj [get_filesets sources_1]
+set_property -name "top" -value "NexysBaseProject_top" -objects $obj
+set_property -name "top_auto_set" -value "0" -objects $obj
+
+# Create 'constrs_1' fileset (if not found)
+if {[string equal [get_filesets -quiet constrs_1] ""]} {
+  create_fileset -constrset constrs_1
+}
+
+# Set 'constrs_1' fileset object
+set obj [get_filesets constrs_1]
+
+# Add/Import constrs file and set constrs file properties
+set file "[file normalize "$origin_dir/xdc/Nexys-A7-100T-Master.xdc"]"
+set file_added [add_files -norecurse -fileset $obj [list $file]]
+set file "$origin_dir/xdc/Nexys-A7-100T-Master.xdc"
+set file [file normalize $file]
+set file_obj [get_files -of_objects [get_filesets constrs_1] [list "*$file"]]
+set_property -name "file_type" -value "XDC" -objects $file_obj
+
+# Set 'constrs_1' fileset properties
+set obj [get_filesets constrs_1]
+
+# Create 'sim_1' fileset (if not found)
+if {[string equal [get_filesets -quiet sim_1] ""]} {
+  create_fileset -simset sim_1
+}
+
+# Set 'sim_1' fileset object
+set obj [get_filesets sim_1]
+set files [list \
+ [file normalize "${origin_dir}/tb/NexysBaseProject_tb.sv"] \
+]
+add_files -norecurse -fileset $obj $files
+
+# Set 'sim_1' fileset file properties for remote files
+set file "$origin_dir/tb/NexysBaseProject_tb.sv"
+set file [file normalize $file]
+set file_obj [get_files -of_objects [get_filesets sim_1] [list "*$file"]]
+set_property -name "file_type" -value "SystemVerilog" -objects $file_obj
+
+
+# Set 'sim_1' fileset file properties for local files
+# None
+
+# Set 'sim_1' fileset properties
+set obj [get_filesets sim_1]
+set_property -name "hbs.configure_design_for_hier_access" -value "1" -objects $obj
+set_property -name "top" -value "NexysBaseProject_tb" -objects $obj
+set_property -name "top_auto_set" -value "0" -objects $obj
+set_property -name "top_lib" -value "xil_defaultlib" -objects $obj
+
+# Set 'utils_1' fileset object
+set obj [get_filesets utils_1]
+# Empty (no sources present)
+
+# Set 'utils_1' fileset properties
+set obj [get_filesets utils_1]
+
+# Create 'synth_1' run (if not found)
+if {[string equal [get_runs -quiet synth_1] ""]} {
+    create_run -name synth_1 -part xc7a100tcsg324-1 -flow {Vivado Synthesis 2018} -strategy "Vivado Synthesis Defaults" -report_strategy {No Reports} -constrset constrs_1
+} else {
+  set_property strategy "Vivado Synthesis Defaults" [get_runs synth_1]
+  set_property flow "Vivado Synthesis 2018" [get_runs synth_1]
+}
+set obj [get_runs synth_1]
+set_property set_report_strategy_name 1 $obj
+set_property report_strategy {Vivado Synthesis Default Reports} $obj
+set_property set_report_strategy_name 0 $obj
+# Create 'synth_1_synth_report_utilization_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0] "" ] } {
+  create_report_config -report_name synth_1_synth_report_utilization_0 -report_type report_utilization:1.0 -steps synth_design -runs synth_1
+}
+set obj [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0]
+if { $obj != "" } {
+
+}
+set obj [get_runs synth_1]
+set_property -name "strategy" -value "Vivado Synthesis Defaults" -objects $obj
+
+# set the current synth run
+current_run -synthesis [get_runs synth_1]
+
+# Create 'impl_1' run (if not found)
+if {[string equal [get_runs -quiet impl_1] ""]} {
+    create_run -name impl_1 -part xc7a100tcsg324-1 -flow {Vivado Implementation 2018} -strategy "Vivado Implementation Defaults" -report_strategy {No Reports} -constrset constrs_1 -parent_run synth_1
+} else {
+  set_property strategy "Vivado Implementation Defaults" [get_runs impl_1]
+  set_property flow "Vivado Implementation 2018" [get_runs impl_1]
+}
+set obj [get_runs impl_1]
+set_property set_report_strategy_name 1 $obj
+set_property report_strategy {Vivado Implementation Default Reports} $obj
+set_property set_report_strategy_name 0 $obj
+# Create 'impl_1_init_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_init_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps init_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'impl_1_opt_report_drc_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0] "" ] } {
+  create_report_config -report_name impl_1_opt_report_drc_0 -report_type report_drc:1.0 -steps opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_opt_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'impl_1_power_opt_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps power_opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'impl_1_place_report_io_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0] "" ] } {
+  create_report_config -report_name impl_1_place_report_io_0 -report_type report_io:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_place_report_utilization_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_utilization_0] "" ] } {
+  create_report_config -report_name impl_1_place_report_utilization_0 -report_type report_utilization:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_utilization_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_place_report_control_sets_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_control_sets_0] "" ] } {
+  create_report_config -report_name impl_1_place_report_control_sets_0 -report_type report_control_sets:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_control_sets_0]
+if { $obj != "" } {
+set_property -name "options.verbose" -value "1" -objects $obj
+
+}
+# Create 'impl_1_place_report_incremental_reuse_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0] "" ] } {
+  create_report_config -report_name impl_1_place_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+
+}
+# Create 'impl_1_place_report_incremental_reuse_1' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_1] "" ] } {
+  create_report_config -report_name impl_1_place_report_incremental_reuse_1 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_1]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+
+}
+# Create 'impl_1_place_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_place_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'impl_1_post_place_power_opt_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_power_opt_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_post_place_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_place_power_opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_power_opt_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'impl_1_phys_opt_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps phys_opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'impl_1_route_report_drc_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_drc_0 -report_type report_drc:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_route_report_methodology_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_methodology_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_methodology_0 -report_type report_methodology:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_methodology_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_route_report_power_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_power_0 -report_type report_power:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_route_report_route_status_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_route_status_0 -report_type report_route_status:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_route_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'impl_1_route_report_incremental_reuse_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_route_report_clock_utilization_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_clock_utilization_0 -report_type report_clock_utilization:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_route_report_bus_skew_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_bus_skew_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_bus_skew_0]
+if { $obj != "" } {
+set_property -name "options.warn_on_violation" -value "1" -objects $obj
+
+}
+# Create 'impl_1_post_route_phys_opt_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_post_route_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_route_phys_opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "options.max_paths" -value "10" -objects $obj
+set_property -name "options.warn_on_violation" -value "1" -objects $obj
+
+}
+# Create 'impl_1_post_route_phys_opt_report_bus_skew_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_bus_skew_0] "" ] } {
+  create_report_config -report_name impl_1_post_route_phys_opt_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps post_route_phys_opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_bus_skew_0]
+if { $obj != "" } {
+set_property -name "options.warn_on_violation" -value "1" -objects $obj
+
+}
+set obj [get_runs impl_1]
+set_property -name "strategy" -value "Vivado Implementation Defaults" -objects $obj
+set_property -name "steps.write_bitstream.args.readback_file" -value "0" -objects $obj
+set_property -name "steps.write_bitstream.args.verbose" -value "0" -objects $obj
+
+# set the current impl run
+current_run -implementation [get_runs impl_1]
+
+puts "INFO: Project created:${_xil_proj_name_}"
+# Create 'drc_1' gadget (if not found)
+if {[string equal [get_dashboard_gadgets  [ list "drc_1" ] ] ""]} {
+create_dashboard_gadget -name {drc_1} -type drc
+}
+set obj [get_dashboard_gadgets [ list "drc_1" ] ]
+set_property -name "reports" -value "impl_1#impl_1_route_report_drc_0" -objects $obj
+
+# Create 'methodology_1' gadget (if not found)
+if {[string equal [get_dashboard_gadgets  [ list "methodology_1" ] ] ""]} {
+create_dashboard_gadget -name {methodology_1} -type methodology
+}
+set obj [get_dashboard_gadgets [ list "methodology_1" ] ]
+set_property -name "reports" -value "impl_1#impl_1_route_report_methodology_0" -objects $obj
+
+# Create 'power_1' gadget (if not found)
+if {[string equal [get_dashboard_gadgets  [ list "power_1" ] ] ""]} {
+create_dashboard_gadget -name {power_1} -type power
+}
+set obj [get_dashboard_gadgets [ list "power_1" ] ]
+set_property -name "reports" -value "impl_1#impl_1_route_report_power_0" -objects $obj
+
+# Create 'timing_1' gadget (if not found)
+if {[string equal [get_dashboard_gadgets  [ list "timing_1" ] ] ""]} {
+create_dashboard_gadget -name {timing_1} -type timing
+}
+set obj [get_dashboard_gadgets [ list "timing_1" ] ]
+set_property -name "reports" -value "impl_1#impl_1_route_report_timing_summary_0" -objects $obj
+
+# Create 'utilization_1' gadget (if not found)
+if {[string equal [get_dashboard_gadgets  [ list "utilization_1" ] ] ""]} {
+create_dashboard_gadget -name {utilization_1} -type utilization
+}
+set obj [get_dashboard_gadgets [ list "utilization_1" ] ]
+set_property -name "reports" -value "synth_1#synth_1_synth_report_utilization_0" -objects $obj
+set_property -name "run.step" -value "synth_design" -objects $obj
+set_property -name "run.type" -value "synthesis" -objects $obj
+
+# Create 'utilization_2' gadget (if not found)
+if {[string equal [get_dashboard_gadgets  [ list "utilization_2" ] ] ""]} {
+create_dashboard_gadget -name {utilization_2} -type utilization
+}
+set obj [get_dashboard_gadgets [ list "utilization_2" ] ]
+set_property -name "reports" -value "impl_1#impl_1_place_report_utilization_0" -objects $obj
+
+move_dashboard_gadget -name {utilization_1} -row 0 -col 0
+move_dashboard_gadget -name {power_1} -row 1 -col 0
+move_dashboard_gadget -name {drc_1} -row 2 -col 0
+move_dashboard_gadget -name {timing_1} -row 0 -col 1
+move_dashboard_gadget -name {utilization_2} -row 1 -col 1
+move_dashboard_gadget -name {methodology_1} -row 2 -col 1

HDLForBeginners_Examples/NexysBaseProject/src/NexysBaseProject_top.sv

@@ -0,0 +1,178 @@
+//////////////////////////////////////////////////////////////////////////////////
+// Company:
+// Engineer:
+//
+// Create Date: 14.07.2021 18:18:52
+// Design Name:
+// Module Name: NexysBaseProject_top
+// Project Name:
+// Target Devices:
+// Tool Versions:
+// Description:
+//
+// Dependencies:
+//
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+`include "../src/version.vh"
+
+module NexysBaseProject_top
+   (
+    input         CLK,
+    input         RST_N,
+
+    // // Switches
+    // input [15:0]  SW,
+     input         BTNC,
+    // input         BTNU,
+    // input         BTNL,
+    // input         BTNR,
+    // input         BTND,
+
+    // // PMOD headers
+    // // Can be both inputs and outputs
+    // // Set to input to be safe
+    // input [10:1]  JA,
+    // input [10:1]  JB,
+    // input [10:1]  JC,
+    // input [10:1]  JD,
+    // input [4:1]   XA_N,
+    // input [4:1]   XA_P,
+
+    // // LEDs
+    // output [15:0] LED,
+    // output        LED16_B,
+    // output        LED16_G,
+    // output        LED16_R,
+    // output        LED17_B,
+    // output        LED17_G,
+    // output        LED17_R,
+
+    // //7 segment display
+    // output        CA,
+    // output        CB,
+    // output        CC,
+    // output        CD,
+    // output        CE,
+    // output        CF,
+    // output        CG,
+    // output        DP,
+    // output [7:0]  AN,
+
+    // // VGA
+    // output [3:0]  VGA_R,
+    // output [3:0]  VGA_G,
+    // output [3:0]  VGA_B,
+    // output        VGA_HS,
+    // output        VGA_VS,
+
+    // // SD Card
+    // output        SD_RESET,
+    // input         SD_CD,
+    // inout         SD_SCK,
+    // inout         SD_CMD,
+    // inout [3:0]   SD_DAT,
+
+    // // Accelerometer
+    // input         ACL_MISO,
+    // output        ACL_MOSI,
+    // output        ACL_SCLK,
+    // output        ACL_CSN,
+    // input [2:1]   ACL_INT,
+
+    // // Temperature Sensor
+    // output        TMP_SCL,
+    // inout         TMP_SDA,
+    // input         TMP_INT,
+    // input         TMP_CT,
+
+    // // Microphone
+    // output        M_CLK,
+    // input         M_DATA,
+    // output        M_LRSEL,
+
+    // // PWM Audio Amplifier
+    // output        AUD_PWM,
+    // output        AUD_SD,
+
+    // // UART
+    // input         UART_TXD_IN,
+    // input         UART_RTS,
+    // output        UART_RXD_OUT,
+    // output        UART_CTS,
+
+    // // USB HID
+    // inout         PS2_CLK,
+    // inout         PS2_DATA,
+
+    // // Ethernet
+    // output        ETH_MDC,
+    // inout         ETH_MDIO,
+     output        ETH_RSTN,
+    // inout         ETH_CRSDV,
+    // input         ETH_RXERR,
+    // inout [1:0]   ETH_RXD,
+    // output        ETH_TXEN,
+    // output [1:0]  ETH_TXD,
+     output        ETH_REFCLK
+    // input         ETH_INTN
+
+    // // QSPI Flash
+    // output        QSPI_CSN,
+    // inout [3:0]   QSPI_DQ
+
+
+
+    );
+
+   // Reset Generate
+   logic          rst;
+
+   rst_gen rst_gen_i
+     (
+      .clk_in(CLK),
+      .rst_in(~RST_N),
+      .rst_out(rst)
+
+     );
+
+   // Ethernet clk and reset generate
+   logic          eth_clk;
+   logic          eth_rst;
+
+   eth_rst_gen eth_rst_gen_i
+     (
+      .clk(CLK),
+      .rst(rst),
+      .eth_clk_out(eth_clk),
+      .eth_rst_out(eth_rst),
+      .ETH_REFCLK(ETH_REFCLK),
+      .ETH_RSTN(ETH_RSTN)
+      );
+
+   // Debounce on buttons
+   logic          btn_c_debounce;
+   logic          btn_c_i;
+   logic          count_en;
+
+   debounce debounce_sw
+     (
+      .clk(clk),
+      .rst(~rst_n),
+      .sw_in(BTNC),
+      .sw_out(btn_c_debounce)
+      );
+
+   edge_detect edge_detect_i
+     (
+      .clk(clk),
+      .rst(~rst_n),
+      .data_in(btn_c_debounce),
+      .data_out(btn_c_i)
+      );
+
+endmodule

HDLForBeginners_Examples/NexysBaseProject/src/debounce.sv

@@ -0,0 +1,65 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 13.11.2021 13:30:52
+// Design Name: 
+// Module Name: debounce
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module debounce
+(
+    input clk,
+    input rst,
+    input sw_in,
+    output sw_out
+    );
+    
+    localparam DEBOUNCE_LENGTH = 10;
+    logic [DEBOUNCE_LENGTH-1:0] sw_in_q;
+    logic sw_out_i;
+    logic [DEBOUNCE_LENGTH-1:0] ones;
+    assign ones = '1;
+    
+    always_ff@(posedge clk) begin
+        if (rst==1) begin
+            sw_in_q <= 0;
+            sw_out_i <= 0;
+            
+        end
+        else begin
+            sw_in_q[0] <= sw_in;
+            sw_in_q[DEBOUNCE_LENGTH-1:1] <= sw_in_q[DEBOUNCE_LENGTH-2:0];
+            
+            // if history is all ones and previously off, turn on
+            if ((sw_in_q == ones) && (sw_out_i == 0)) begin
+                sw_out_i <= 1;
+                
+            end
+            
+            // if history is all 0s and previously on, turn off
+            if ((sw_in_q == 0) && (sw_out_i == 1)) begin
+                sw_out_i <= 0;
+                
+            end
+            
+        end
+    end
+    
+    assign sw_out = sw_out_i;
+    
+    
+endmodule

HDLForBeginners_Examples/NexysBaseProject/src/edge_detect.sv

@@ -0,0 +1,46 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 13.11.2021 14:00:19
+// Design Name: 
+// Module Name: edge_detect
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module edge_detect(
+    input clk,
+    input rst,
+    input data_in,
+    output data_out
+    );
+    
+    
+    logic data_in_q;
+    
+    always_ff@(posedge clk) begin
+        if (rst) begin
+            data_in_q <= 0;
+        end
+        else begin
+            data_in_q <= data_in;
+            
+        end
+    end
+    
+    assign data_out = (data_in != data_in_q) ? data_in : 0;
+    
+    
+endmodule

HDLForBeginners_Examples/NexysBaseProject/src/eth_rst_gen.sv

@@ -0,0 +1,83 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 13.11.2021 14:32:12
+// Design Name: 
+// Module Name: eth_rst_gen
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module eth_rst_gen(
+    input clk,
+    input rst,
+    output eth_clk_out,
+    output eth_rst_out,
+    output ETH_REFCLK,
+    output ETH_RSTN
+    );
+    
+    logic locked;
+    logic eth_rst;
+    logic eth_clk;
+    
+   
+    // 50M clk gen
+  clk_wiz_0 gen_50M
+   (
+    .clk_out1(eth_clk),         // output clk_out1
+    .clk_out2(ETH_REFCLK),     // output clk_out2
+    .reset(rst),            // input reset
+    .locked(locked),           // output locked
+    .clk_in1(clk));         // input clk_in1
+    
+    
+    localparam WAIT_CYCLES_50M = 2000000; // 40ms
+    logic [31:0] wait_counter_50M;
+    
+    // Generate output reset signals in 50M domain
+    always_ff@(posedge eth_clk) begin
+        // remain in reset until global reset is released
+        if (rst) begin
+            eth_rst <= 1;
+            wait_counter_50M <= 0;
+        end 
+        else begin
+            // PLL locked
+            if (locked) begin
+                // remain in rst till counter is done
+                if (wait_counter_50M < WAIT_CYCLES_50M-1) begin
+                    eth_rst <= 1;
+                    wait_counter_50M <= wait_counter_50M + 1;
+                end
+                else begin
+                    eth_rst <= 0;
+                end 
+            end
+            // PLL not locked. Remain in reset until locked
+            else begin
+                eth_rst <= 1;
+                wait_counter_50M <= 0;
+                
+                
+            end
+        end
+    end
+    
+    assign ETH_RSTN = ~eth_rst;
+    assign eth_clk_out = eth_clk;
+    assign eth_rst_out = eth_rst;
+    
+endmodule

HDLForBeginners_Examples/NexysBaseProject/src/rst_gen.sv

@@ -0,0 +1,45 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 13.11.2021 14:32:12
+// Design Name: 
+// Module Name: rst_gen
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module rst_gen(
+    input clk_in,
+    input rst_in,
+    output rst_out
+
+    );
+    
+    logic [2:0] rst_q;
+    
+    
+    // Triple Register into clk_in domain
+    always_ff@(posedge clk_in) begin
+       rst_q[0] <= rst_in;
+       rst_q[2:1] <= rst_q[1:0];
+       
+    end
+    
+    // internal reset 
+    // only come out of reset when rst_q is all zeros
+    assign rst_out = (rst_q == 0) ? 0 : 1;
+    
+    
+endmodule

HDLForBeginners_Examples/NexysBaseProject/src/version.vh

@@ -0,0 +1,2 @@
+`define VERSION_MAJOR 1
+`define VERSION_MINOR 1

HDLForBeginners_Examples/NexysBaseProject/tb/NexysBaseProject_tb.sv

@@ -0,0 +1,54 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company:
+// Engineer:
+//
+// Create Date: 14.07.2021 18:18:52
+// Design Name:
+// Module Name: NexysBaseProject_tb
+// Project Name:
+// Target Devices:
+// Tool Versions:
+// Description:
+//
+// Dependencies:
+//
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+module NexysBaseProject_tb
+  (
+
+   );
+
+   logic clk = 0;
+   logic rst = 1;
+
+   // Clock definition
+   localparam CLK_PERIOD = 10; // 100 Mhz (counter is in ns)
+   localparam RST_COUNT = 10; //Clock cycles that reset is high
+
+   always begin
+      clk   = #(CLK_PERIOD/2) ~clk;
+   end
+
+   // reset definition
+   initial begin
+      rst = 1;
+      #(RST_COUNT*CLK_PERIOD);
+      @(posedge clk);
+      rst = 0;
+   end
+
+   // UUT
+   NexysBaseProject_top NexysBaseProject_top_i
+     (
+      .CLK(clk),
+      .RST_N(~rst)
+      );
+
+
+endmodule

HDLForBeginners_Examples/NexysBaseProject/tcl/post-build.tcl

@@ -0,0 +1,45 @@
+
+# relative
+# The dir the implementation is running from
+set run_dir [pwd]
+# This script dir
+set script_path [ file dirname [ file normalize [ info script ] ] ]
+
+# My version file
+set filename "$script_path/../src/version.vh"
+
+# Where the final binary should land
+set build_final_dir "$script_path/../builds/"
+
+#  Slurp up the version data file
+set fp [open $filename r]
+set file_data [read $fp]
+close $fp
+
+#  Extract the version data
+set data [split $file_data "\n"]
+foreach line $data {
+    if {[string first "VERSION_MAJOR" $line] != -1} {
+        set line_major [split $line " "]
+    }
+
+    if {[string first "VERSION_MINOR" $line] != -1} {
+        set line_minor [split $line " "]
+    }
+
+}
+
+# Get version numbers
+set version_major [lindex $line_major 2]
+set version_minor [lindex $line_minor 2]
+
+# Vivado produced bitstream filename
+set bitstream_filename "$run_dir/NexysBaseProject_top.bit"
+
+# New bitstream filename
+set new_bitstream_filename  "$build_final_dir/NexysBaseProject_top_v${version_major}_${version_minor}.bit"
+
+# Copy file to new location
+puts "Build file v${version_major}.${version_minor} located in $new_bitstream_filename."
+file mkdir "$build_final_dir/"
+file copy -force $bitstream_filename $new_bitstream_filename

HDLForBeginners_Examples/UART/src/uart.sv

@@ -0,0 +1,80 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: HDLForBeginners
+// Engineer: Stacey
+// 
+// Create Date: 14.07.2021 13:47:50
+// Design Name: uart_tx
+// Module Name: 
+// Project Name: uart_tx
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// transmits a supplied word over uart
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module uart
+  #(
+    parameter CLKRATE = 100000000,
+    parameter BAUD = 115200,
+    parameter WORD_LENGTH = 8
+    )
+   (
+    input 		    clk,
+    input 		    rst,
+    input [WORD_LENGTH-1:0] tx_data,
+    input 		    tx_data_valid,
+    input 		    tx_data_last,
+    output 		    tx_data_ready,
+    output 		    UART_TX
+    );
+   
+    logic           tx_data_fifo_m_axis_tlast;
+    logic           tx_data_fifo_m_axis_tready;
+    logic           tx_data_fifo_m_axis_tvalid;
+    logic [WORD_LENGTH-1:0] tx_data_fifo_m_axis_tdata;
+   
+   tx_fifo 
+    tx_data_fifo_i(
+   // unused
+  .wr_rst_busy(),      // output wire wr_rst_busy
+  .rd_rst_busy(),      // output wire rd_rst_busy
+  .s_aclk(clk),                // input wire s_aclk
+  .s_aresetn(~rst),          // input wire s_aresetn
+  // slave
+  .s_axis_tvalid(tx_data_valid),  // input wire s_axis_tvalid
+  .s_axis_tready(tx_data_ready),  // output wire s_axis_tready
+  .s_axis_tdata(tx_data),    // input wire [7 : 0] s_axis_tdata
+  .s_axis_tlast(tx_data_last),    // input wire s_axis_tlast
+  //master
+  .m_axis_tvalid(tx_data_fifo_m_axis_tvalid),  // output wire m_axis_tvalid
+  .m_axis_tready(tx_data_fifo_m_axis_tready),  // input wire m_axis_tready
+  .m_axis_tdata(tx_data_fifo_m_axis_tdata),    // output wire [7 : 0] m_axis_tdata
+  .m_axis_tlast(tx_data_fifo_m_axis_tlast)    // output wire m_axis_tlast
+);
+   
+ uart_tx
+  #(
+     .CLKRATE(CLKRATE),
+     .BAUD(BAUD),
+     .WORD_LENGTH(WORD_LENGTH)
+    )
+    uart_tx_i
+   (
+     .clk(clk),
+     .rst(rst),
+     .tx_data(tx_data_fifo_m_axis_tdata),
+     .tx_data_valid(tx_data_fifo_m_axis_tvalid),
+     .tx_data_ready(tx_data_fifo_m_axis_tready),
+     .UART_TX(UART_TX)
+    );
+    
+endmodule

HDLForBeginners_Examples/UART/src/uart_tx.sv

@@ -0,0 +1,384 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: HDLForBeginners
+// Engineer: Stacey
+//
+// Create Date: 14.07.2021 13:47:50
+// Design Name: uart_tx
+// Module Name:
+// Project Name: uart_tx
+// Target Devices:
+// Tool Versions:
+// Description:
+// transmits a supplied word over uart
+//
+// Dependencies:
+//
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+//
+//////////////////////////////////////////////////////////////////////////////////
+
+module uart_tx
+  #(
+    parameter CLKRATE = 100000000,
+    parameter BAUD = 115200,
+    parameter WORD_LENGTH = 8
+    )
+   (
+    input 		    clk,
+    input 		    rst,
+    input [WORD_LENGTH-1:0] tx_data,
+    input 		    tx_data_valid,
+    output 		    tx_data_ready,
+    output 		    UART_TX
+    );
+
+   // internal signals
+   logic                    tx_data_ready_i;
+   logic                    uart_tx_i = 1'b0;
+   logic [WORD_LENGTH-1:0]  tx_data_i;
+
+
+   // store tx_data_i when valid for use later
+   always @(posedge clk)
+     begin
+	if(rst) begin
+           tx_data_i <= '0;
+
+	end
+	else begin
+           // don't store the data unless we're ready
+           if (tx_data_valid & tx_data_ready_i) begin
+              tx_data_i <= tx_data;
+
+           end
+	end
+     end
+
+   // Define our states
+   typedef enum {IDLE, START, DATA, PARITY, STOP,WAIT}  my_state;
+
+   my_state current_state = IDLE;
+   my_state next_state    = IDLE;
+
+   // Define tx signal constants
+   localparam TX_IDLE = 1'b1;
+   localparam TX_START = 1'b0;
+   localparam TX_STOP = 1'b1;
+
+   // counter parameters
+   // count the baud
+   localparam BAUD_COUNTER_MAX = CLKRATE/BAUD;
+   localparam BAUD_COUNTER_SIZE = $clog2(BAUD_COUNTER_MAX);
+   // count the data
+   localparam DATA_COUNTER_MAX = WORD_LENGTH;
+   localparam DATA_COUNTER_SIZE = $clog2(DATA_COUNTER_MAX);
+
+   logic [BAUD_COUNTER_SIZE-1:0] uart_baud_counter;
+   logic [DATA_COUNTER_SIZE-1:0] uart_data_counter;
+   logic                         uart_baud_done;
+   logic                         uart_data_done;
+
+   // buffer to store tx data while shifting
+   logic [WORD_LENGTH-1:0] 	 uart_data_shift_buffer;
+
+   // UART Baud Clock
+   always @(posedge clk)
+     begin
+	if(rst) begin
+           uart_baud_counter <= '0;
+	end
+	else begin
+           // Reset at state transition
+           if (uart_baud_done) begin
+              uart_baud_counter <= '0;
+
+           end
+           else begin
+              uart_baud_counter <= uart_baud_counter + 'd1;
+
+           end
+	end
+     end
+
+   // baud clock is done
+   assign uart_baud_done = (uart_baud_counter == BAUD_COUNTER_MAX-1) ? 1'b1 : 1'b0;
+
+   // data counting and shifting
+   always @(posedge clk)
+     begin
+	if(rst) begin
+           uart_data_counter <= '0;
+           uart_data_shift_buffer <= '0;
+
+	end
+	// note uart_baud_done is clk enable
+	else if (uart_baud_done) begin
+           // Reset at state transition
+           if (current_state != next_state) begin
+              uart_data_counter <= '0;
+              uart_data_shift_buffer <= tx_data_i;
+
+           end
+           else begin
+              // otherwise increment counter and shift buffer
+              uart_data_counter <= uart_data_counter + 'd1;
+              uart_data_shift_buffer <= uart_data_shift_buffer >> 1;
+           end
+	end
+     end
+   // uart_data_done indicates all bits are transmitted
+   assign uart_data_done = (uart_data_counter == DATA_COUNTER_MAX-1) ? 1'b1 : 1'b0;
+
+   // State Machine
+   always @(*)
+     begin
+        case (current_state)
+          IDLE   :
+            begin
+               if (tx_data_valid) begin
+                  next_state = START;
+
+               end
+               else begin
+                  next_state = current_state;
+
+               end
+            end
+          START  :
+            begin
+               if (uart_baud_done) begin
+                  next_state = DATA;
+               end
+               else begin
+                  next_state = current_state;
+
+               end
+            end
+          DATA   :
+            begin
+               if (uart_data_done & uart_baud_done) begin
+                  next_state = PARITY;
+
+               end
+               else begin
+                  next_state = current_state;
+
+               end
+            end
+          PARITY :
+            begin
+               if (uart_baud_done) begin
+                  next_state = STOP;
+               end
+               else begin
+                  next_state = current_state;
+
+               end
+            end
+          STOP   :
+            begin
+               if (uart_baud_done) begin
+                  next_state = WAIT;
+               end
+               else begin
+                  next_state = current_state;
+
+               end
+            end
+          WAIT   :
+            begin
+               if (uart_baud_done) begin
+                  next_state = IDLE;
+               end
+               else begin
+                  next_state = current_state;
+
+               end
+            end
+          default:
+            next_state = current_state;
+        endcase
+     end
+
+
+   always @(posedge clk)
+     begin
+	if(rst) begin
+           current_state <= IDLE;
+	end
+	else begin
+           current_state <= next_state;
+	end
+
+     end
+
+   always @(*)
+     begin
+        case (current_state)
+          IDLE   :
+            begin
+               uart_tx_i = TX_IDLE;
+            end
+          START  :
+            begin
+               uart_tx_i = TX_START;
+            end
+          DATA   :
+            begin
+               uart_tx_i = uart_data_shift_buffer[0];
+            end
+          PARITY :
+            begin
+               uart_tx_i = ^tx_data_i;
+            end
+          STOP   :
+            begin
+               uart_tx_i = TX_STOP;
+
+            end
+          WAIT   :
+            begin
+               uart_tx_i = TX_IDLE;
+
+            end
+        endcase
+     end
+
+   assign tx_data_ready_i = (current_state == IDLE) ? 1'b1 : 1'b0;
+   assign tx_data_ready = tx_data_ready_i;
+   assign UART_TX = uart_tx_i;
+
+   
+   ////////////////////////////////////////////////////////////////////////////////
+   ////////////////////////////////////////////////////////////////////////////////
+   ////////////////////////////////////////////////////////////////////////////////
+   //
+   // Formal properties
+   // {{{
+   ////////////////////////////////////////////////////////////////////////////////
+   ////////////////////////////////////////////////////////////////////////////////
+   ////////////////////////////////////////////////////////////////////////////////
+`ifdef	FORMAL
+   // Register declarations, reset assertion
+   // {{{
+   reg	f_past_valid;
+   reg [WORD_LENGTH-1:0] fv_data;
+
+   initial	f_past_valid = 0;
+   always @(posedge clk)
+     f_past_valid <= 1;
+
+   always @(*)
+     if (!f_past_valid)
+       assume(rst);
+   // }}}
+   ////////////////////////////////////////////////////////////////////////
+   //
+   // Input AXI-stream assumptions
+   // {{{
+   ////////////////////////////////////////////////////////////////////////
+   //
+   //
+   always @(posedge clk)
+     if (!f_past_valid || $past(rst))
+       begin
+	  assume(!tx_data_valid);
+       end
+     else if ($past(tx_data_valid && !tx_data_ready))
+       begin
+	  assume(tx_data_valid);
+	  assume($stable(tx_data));
+       end
+   // }}}
+
+   always @(*)
+     if (f_past_valid)
+       begin
+	  assert(uart_data_counter < DATA_COUNTER_MAX);
+	  assert(uart_baud_done == (uart_baud_counter == BAUD_COUNTER_MAX-1));
+       end
+
+   always @(*)
+     if (f_past_valid)
+       case(current_state)
+	 IDLE:  assert(UART_TX);
+	 START: assert(!UART_TX);
+	 DATA:  begin
+         end
+	 PARITY: assert(UART_TX == ^tx_data_i);
+	 STOP:  assert(UART_TX);
+	 WAIT:  assert(UART_TX);
+	 default: assert(0);
+       endcase
+
+   always @(*)
+     if (f_past_valid)
+       case(current_state)
+	 DATA:  begin
+	    assert(uart_data_counter < WORD_LENGTH);
+	    assert(UART_TX == fv_data[uart_data_counter]);
+	 end
+	 default: begin end
+       endcase
+
+   always @(*)
+     if (f_past_valid)
+       assert(tx_data_ready == (current_state == IDLE));
+
+   always @(posedge clk)
+     if (tx_data_valid && tx_data_ready)
+       fv_data <= tx_data;
+
+   always @(*)
+     if (f_past_valid && current_state != IDLE)
+       assert(fv_data == tx_data_i);
+   ////////////////////////////////////////////////////////////////////////
+   //
+   // Cover checks
+   // {{{
+   ////////////////////////////////////////////////////////////////////////
+   //
+   //
+
+   reg	[2:0]	cvr_count;
+
+   always @(posedge clk)
+     if (rst)
+       cvr_count <= 0;
+     else if (tx_data_valid && tx_data_ready)
+       begin
+	  if (cvr_count == 0 && tx_data == 8'h01)
+	    cvr_count <= 1;
+	  else if (cvr_count == 1 && tx_data == 8'h7e)
+	    cvr_count <= 2;
+	  else if (cvr_count >= 2 && !(&cvr_count))
+	    cvr_count <= cvr_count + 1;
+       end
+
+   always @(*)
+     if (!rst)
+       begin
+	  cover(cvr_count == 1);
+	  cover(cvr_count == 1 && current_state == START);
+	  cover(cvr_count == 1 && current_state == DATA);
+	  cover(cvr_count == 1 && current_state == PARITY);
+	  cover(cvr_count == 1 && current_state == STOP);
+	  cover(cvr_count == 1 && current_state == WAIT);
+	  cover(cvr_count == 1 && current_state == IDLE);
+	  cover(cvr_count == 2);
+	  cover(cvr_count == 2 && current_state == START);
+	  cover(cvr_count == 2 && current_state == DATA);		// @88
+	  cover(cvr_count == 2 && current_state == PARITY);	// @149
+	  cover(cvr_count == 2 && current_state == STOP);
+	  cover(cvr_count == 2 && current_state == WAIT);
+	  cover(cvr_count == 2 && current_state == IDLE);
+	  cover(cvr_count == 3);
+	  cover(cvr_count == 4);
+       end
+   // }}}
+   // }}}
+`endif
+endmodule

HDLForBeginners_Examples/UART/tb/lfsr_8bit.sv

@@ -0,0 +1,51 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: HDLForBeginners
+// Engineer: Stacey
+// 
+// Create Date: 14.07.2021 13:47:50
+// Design Name: lfsr_4bit
+// Module Name: lfsr_4bit_top
+// Project Name: lfsr_4bit
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// Increments a counter and and drives an output gpio pin
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module lfsr_8bit
+  (
+   input 	clk,
+   input 	rst,
+   input    clk_en,
+   output [7:0] data
+   );
+   
+   
+   logic [8:0] 	lfsr;
+   logic [3:0] 	lfsr_feedback;
+   assign lfsr_feedback= {lfsr[7],lfsr[5:3]};
+   
+   always @(posedge clk)
+     begin
+	if(rst) begin
+           lfsr <= 8'b11111111;
+	   
+	end
+	else if (clk_en) begin
+           lfsr[7:1] <= lfsr[6:0]; 
+           lfsr[0] <= ^lfsr_feedback;           
+	end
+     end
+   
+   assign data = lfsr;
+   
+endmodule

HDLForBeginners_Examples/UART/tb/uart_tb.sv

@@ -0,0 +1,99 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 14.07.2021 18:18:52
+// Design Name: 
+// Module Name: simple_increment_tb
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+module uart_tb(
+
+	       );
+   
+   logic clk = 0;
+   logic rst = 1;
+   logic [7:0] tx_data;
+   logic       tx_ready;
+   logic       tx_valid;
+   logic       tx_last;
+   logic       tx_out;
+   
+   
+   // Clock definition
+   localparam CLK_PERIOD = 20000; // 50 Mhz (counter is in ps)
+   localparam RST_COUNT = 10; //Clock cycles that reset is high
+   
+   always begin
+      clk   = #(CLK_PERIOD/2) ~clk;
+   end
+   
+   // reset definition
+   initial begin
+      rst = 1;
+      #(RST_COUNT*CLK_PERIOD);
+      @(posedge clk);
+      rst = 0;
+   end
+
+    localparam PACKET_COUNTER_MAX = 10;
+    localparam PACKET_COUNTER_SIZE = $clog2(PACKET_COUNTER_MAX);
+    
+    logic [PACKET_COUNTER_SIZE-1:0] packet_counter;
+    
+   always @(posedge clk)
+     begin
+	if(rst) begin
+           packet_counter <= '0;
+           
+	end
+	else begin
+           // don't store the data unless we're ready
+           if (tx_last & tx_valid & tx_ready) begin
+              packet_counter <= '0;
+              end
+           else if (tx_valid & tx_ready) begin
+              packet_counter <= packet_counter + 'd1;;
+              
+           end
+	end
+    end
+
+   assign tx_last = (packet_counter == PACKET_COUNTER_MAX-1) ? 1'b1 : 1'b0;
+   // UUT
+   uart uart_i
+     (
+      .clk(clk),
+      .rst(rst),
+      .tx_data(tx_data),
+      .tx_data_valid(tx_valid),
+      .tx_data_ready(tx_ready),
+      .tx_data_last(tx_last),
+      .UART_TX(tx_out)
+      );
+
+   // Gen input tx data
+   lfsr_8bit  lfsr_8bit_i
+     (
+      .clk(clk),
+      .rst(rst),
+      .clk_en(tx_ready),
+      .data(tx_data)
+      
+      );
+      
+  assign tx_valid = ~rst;
+   
+endmodule

HDLForBeginners_Examples/UART/uart.tcl

@@ -0,0 +1,569 @@
+#*****************************************************************************************
+# Vivado (TM) v2020.2 (64-bit)
+#
+# uart.tcl: Tcl script for re-creating project 'uart'
+#
+# Generated by Vivado on Sat Jul 31 13:11:31 SAST 2021
+# IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020
+#
+# This file contains the Vivado Tcl commands for re-creating the project to the state*
+# when this script was generated. In order to re-create the project, please source this
+# file in the Vivado Tcl Shell.
+#
+# * Note that the runs in the created project will be configured the same way as the
+#   original project, however they will not be launched automatically. To regenerate the
+#   run results please launch the synthesis/implementation runs as needed.
+#
+#*****************************************************************************************
+# NOTE: In order to use this script for source control purposes, please make sure that the
+#       following files are added to the source control system:-
+#
+# 1. This project restoration tcl script (uart.tcl) that was generated.
+#
+# 2. The following source(s) files that were local or imported into the original project.
+#    (Please see the '$orig_proj_dir' and '$origin_dir' variable setting below at the start of the script)
+#
+#    <none>
+#
+# 3. The following remote source files that were added to the original project:-
+#
+#    "src/uart_tx.sv"
+#    "tb/lfsr_8bit.sv"
+#    "src/uart.sv"
+#    "ip/tx_fifo/tx_fifo.xci"
+#    "xdc/constraints.xdc"
+#    "tb/uart_tb.sv"
+#    "uart_tb_behav.wcfg"
+#
+#*****************************************************************************************
+
+# Check file required for this script exists
+proc checkRequiredFiles { origin_dir} {
+  set status true
+  set files [list \
+   "src/uart_tx.sv" \
+   "tb/lfsr_8bit.sv" \
+   "src/uart.sv" \
+   "ip/tx_fifo/tx_fifo.xci" \
+   "xdc/constraints.xdc" \
+   "tb/uart_tb.sv" \
+   "uart_tb_behav.wcfg" \
+  ]
+  foreach ifile $files {
+    if { ![file isfile $ifile] } {
+      puts " Could not find remote file $ifile "
+      set status false
+    }
+  }
+
+  return $status
+}
+# Set the reference directory for source file relative paths (by default the value is script directory path)
+set origin_dir [file dirname [info script]]
+
+# Use origin directory path location variable, if specified in the tcl shell
+if { [info exists ::origin_dir_loc] } {
+  set origin_dir $::origin_dir_loc
+}
+
+# Set the project name
+set _xil_proj_name_ "uart"
+
+# Use project name variable, if specified in the tcl shell
+if { [info exists ::user_project_name] } {
+  set _xil_proj_name_ $::user_project_name
+}
+
+variable script_file
+set script_file "uart.tcl"
+
+# Help information for this script
+proc print_help {} {
+  variable script_file
+  puts "\nDescription:"
+  puts "Recreate a Vivado project from this script. The created project will be"
+  puts "functionally equivalent to the original project for which this script was"
+  puts "generated. The script contains commands for creating a project, filesets,"
+  puts "runs, adding/importing sources and setting properties on various objects.\n"
+  puts "Syntax:"
+  puts "$script_file"
+  puts "$script_file -tclargs \[--origin_dir <path>\]"
+  puts "$script_file -tclargs \[--project_name <name>\]"
+  puts "$script_file -tclargs \[--help\]\n"
+  puts "Usage:"
+  puts "Name                   Description"
+  puts "-------------------------------------------------------------------------"
+  puts "\[--origin_dir <path>\]  Determine source file paths wrt this path. Default"
+  puts "                       origin_dir path value is \".\", otherwise, the value"
+  puts "                       that was set with the \"-paths_relative_to\" switch"
+  puts "                       when this script was generated.\n"
+  puts "\[--project_name <name>\] Create project with the specified name. Default"
+  puts "                       name is the name of the project from where this"
+  puts "                       script was generated.\n"
+  puts "\[--help\]               Print help information for this script"
+  puts "-------------------------------------------------------------------------\n"
+  exit 0
+}
+
+if { $::argc > 0 } {
+  for {set i 0} {$i < $::argc} {incr i} {
+    set option [string trim [lindex $::argv $i]]
+    switch -regexp -- $option {
+      "--origin_dir"   { incr i; set origin_dir [lindex $::argv $i] }
+      "--project_name" { incr i; set _xil_proj_name_ [lindex $::argv $i] }
+      "--help"         { print_help }
+      default {
+        if { [regexp {^-} $option] } {
+          puts "ERROR: Unknown option '$option' specified, please type '$script_file -tclargs --help' for usage info.\n"
+          return 1
+        }
+      }
+    }
+  }
+}
+
+# Set the directory path for the original project from where this script was exported
+set orig_proj_dir "[file normalize "$origin_dir/uart"]"
+
+# Check for paths and files needed for project creation
+set validate_required 0
+if { $validate_required } {
+  if { [checkRequiredFiles $origin_dir] } {
+    puts "Tcl file $script_file is valid. All files required for project creation is accesable. "
+  } else {
+    puts "Tcl file $script_file is not valid. Not all files required for project creation is accesable. "
+    return
+  }
+}
+
+# Create project
+create_project ${_xil_proj_name_} ${origin_dir}/${_xil_proj_name_} -part xc7z010clg400-1
+
+# Set the directory path for the new project
+set proj_dir [get_property directory [current_project]]
+
+# Set project properties
+set obj [current_project]
+set_property -name "board_part" -value "digilentinc.com:zybo:part0:2.0" -objects $obj
+set_property -name "default_lib" -value "xil_defaultlib" -objects $obj
+set_property -name "enable_vhdl_2008" -value "1" -objects $obj
+set_property -name "ip_cache_permissions" -value "read write" -objects $obj
+set_property -name "ip_output_repo" -value "$proj_dir/${_xil_proj_name_}.cache/ip" -objects $obj
+set_property -name "mem.enable_memory_map_generation" -value "1" -objects $obj
+set_property -name "platform.board_id" -value "zybo" -objects $obj
+set_property -name "platform.description" -value "Vivado generated DSA" -objects $obj
+set_property -name "platform.emu_dir" -value "emu" -objects $obj
+set_property -name "platform.uses_pr" -value "1" -objects $obj
+set_property -name "sim.central_dir" -value "$proj_dir/${_xil_proj_name_}.ip_user_files" -objects $obj
+set_property -name "sim.ip.auto_export_scripts" -value "1" -objects $obj
+set_property -name "simulator_language" -value "Mixed" -objects $obj
+set_property -name "webtalk.activehdl_export_sim" -value "7" -objects $obj
+set_property -name "webtalk.ies_export_sim" -value "7" -objects $obj
+set_property -name "webtalk.modelsim_export_sim" -value "7" -objects $obj
+set_property -name "webtalk.questa_export_sim" -value "7" -objects $obj
+set_property -name "webtalk.riviera_export_sim" -value "7" -objects $obj
+set_property -name "webtalk.vcs_export_sim" -value "7" -objects $obj
+set_property -name "webtalk.xcelium_export_sim" -value "5" -objects $obj
+set_property -name "webtalk.xsim_export_sim" -value "7" -objects $obj
+set_property -name "webtalk.xsim_launch_sim" -value "42" -objects $obj
+
+# Create 'sources_1' fileset (if not found)
+if {[string equal [get_filesets -quiet sources_1] ""]} {
+  create_fileset -srcset sources_1
+}
+
+# Set 'sources_1' fileset object
+set obj [get_filesets sources_1]
+set files [list \
+ [file normalize "${origin_dir}/src/uart_tx.sv"] \
+ [file normalize "${origin_dir}/tb/lfsr_8bit.sv"] \
+ [file normalize "${origin_dir}/src/uart.sv"] \
+ [file normalize "${origin_dir}/ip/tx_fifo/tx_fifo.xci"] \
+]
+add_files -norecurse -fileset $obj $files
+
+# Set 'sources_1' fileset file properties for remote files
+set file "$origin_dir/src/uart_tx.sv"
+set file [file normalize $file]
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "SystemVerilog" -objects $file_obj
+
+set file "$origin_dir/tb/lfsr_8bit.sv"
+set file [file normalize $file]
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "SystemVerilog" -objects $file_obj
+set_property -name "used_in" -value "simulation" -objects $file_obj
+set_property -name "used_in_implementation" -value "0" -objects $file_obj
+set_property -name "used_in_synthesis" -value "0" -objects $file_obj
+
+set file "$origin_dir/src/uart.sv"
+set file [file normalize $file]
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "file_type" -value "SystemVerilog" -objects $file_obj
+
+set file "$origin_dir/ip/tx_fifo/tx_fifo.xci"
+set file [file normalize $file]
+set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
+set_property -name "generate_files_for_reference" -value "0" -objects $file_obj
+set_property -name "registered_with_manager" -value "1" -objects $file_obj
+if { ![get_property "is_locked" $file_obj] } {
+  set_property -name "synth_checkpoint_mode" -value "Singular" -objects $file_obj
+}
+
+
+# Set 'sources_1' fileset file properties for local files
+# None
+
+# Set 'sources_1' fileset properties
+set obj [get_filesets sources_1]
+set_property -name "top" -value "uart_tx" -objects $obj
+set_property -name "top_auto_set" -value "0" -objects $obj
+
+# Create 'constrs_1' fileset (if not found)
+if {[string equal [get_filesets -quiet constrs_1] ""]} {
+  create_fileset -constrset constrs_1
+}
+
+# Set 'constrs_1' fileset object
+set obj [get_filesets constrs_1]
+
+# Add/Import constrs file and set constrs file properties
+set file "[file normalize "$origin_dir/xdc/constraints.xdc"]"
+set file_added [add_files -norecurse -fileset $obj [list $file]]
+set file "$origin_dir/xdc/constraints.xdc"
+set file [file normalize $file]
+set file_obj [get_files -of_objects [get_filesets constrs_1] [list "*$file"]]
+set_property -name "file_type" -value "XDC" -objects $file_obj
+
+# Set 'constrs_1' fileset properties
+set obj [get_filesets constrs_1]
+
+# Create 'sim_1' fileset (if not found)
+if {[string equal [get_filesets -quiet sim_1] ""]} {
+  create_fileset -simset sim_1
+}
+
+# Set 'sim_1' fileset object
+set obj [get_filesets sim_1]
+set files [list \
+ [file normalize "${origin_dir}/tb/uart_tb.sv"] \
+ [file normalize "${origin_dir}/uart_tb_behav.wcfg"] \
+]
+add_files -norecurse -fileset $obj $files
+
+# Set 'sim_1' fileset file properties for remote files
+set file "$origin_dir/tb/uart_tb.sv"
+set file [file normalize $file]
+set file_obj [get_files -of_objects [get_filesets sim_1] [list "*$file"]]
+set_property -name "file_type" -value "SystemVerilog" -objects $file_obj
+
+
+# Set 'sim_1' fileset file properties for local files
+# None
+
+# Set 'sim_1' fileset properties
+set obj [get_filesets sim_1]
+set_property -name "hbs.configure_design_for_hier_access" -value "1" -objects $obj
+set_property -name "top" -value "uart_tb" -objects $obj
+set_property -name "top_auto_set" -value "0" -objects $obj
+set_property -name "top_lib" -value "xil_defaultlib" -objects $obj
+
+# Set 'utils_1' fileset object
+set obj [get_filesets utils_1]
+# Empty (no sources present)
+
+# Set 'utils_1' fileset properties
+set obj [get_filesets utils_1]
+
+# Create 'synth_1' run (if not found)
+if {[string equal [get_runs -quiet synth_1] ""]} {
+    create_run -name synth_1 -part xc7z010clg400-1 -flow {Vivado Synthesis 2018} -strategy "Vivado Synthesis Defaults" -report_strategy {No Reports} -constrset constrs_1
+} else {
+  set_property strategy "Vivado Synthesis Defaults" [get_runs synth_1]
+  set_property flow "Vivado Synthesis 2018" [get_runs synth_1]
+}
+set obj [get_runs synth_1]
+set_property set_report_strategy_name 1 $obj
+set_property report_strategy {Vivado Synthesis Default Reports} $obj
+set_property set_report_strategy_name 0 $obj
+# Create 'synth_1_synth_report_utilization_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0] "" ] } {
+  create_report_config -report_name synth_1_synth_report_utilization_0 -report_type report_utilization:1.0 -steps synth_design -runs synth_1
+}
+set obj [get_report_configs -of_objects [get_runs synth_1] synth_1_synth_report_utilization_0]
+if { $obj != "" } {
+
+}
+set obj [get_runs synth_1]
+set_property -name "needs_refresh" -value "1" -objects $obj
+set_property -name "strategy" -value "Vivado Synthesis Defaults" -objects $obj
+
+# set the current synth run
+current_run -synthesis [get_runs synth_1]
+
+# Create 'impl_1' run (if not found)
+if {[string equal [get_runs -quiet impl_1] ""]} {
+    create_run -name impl_1 -part xc7z010clg400-1 -flow {Vivado Implementation 2018} -strategy "Vivado Implementation Defaults" -report_strategy {No Reports} -constrset constrs_1 -parent_run synth_1
+} else {
+  set_property strategy "Vivado Implementation Defaults" [get_runs impl_1]
+  set_property flow "Vivado Implementation 2018" [get_runs impl_1]
+}
+set obj [get_runs impl_1]
+set_property set_report_strategy_name 1 $obj
+set_property report_strategy {Vivado Implementation Default Reports} $obj
+set_property set_report_strategy_name 0 $obj
+# Create 'impl_1_init_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_init_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps init_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_init_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'impl_1_opt_report_drc_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0] "" ] } {
+  create_report_config -report_name impl_1_opt_report_drc_0 -report_type report_drc:1.0 -steps opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_drc_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_opt_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_opt_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'impl_1_power_opt_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps power_opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_power_opt_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'impl_1_place_report_io_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0] "" ] } {
+  create_report_config -report_name impl_1_place_report_io_0 -report_type report_io:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_io_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_place_report_utilization_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_utilization_0] "" ] } {
+  create_report_config -report_name impl_1_place_report_utilization_0 -report_type report_utilization:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_utilization_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_place_report_control_sets_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_control_sets_0] "" ] } {
+  create_report_config -report_name impl_1_place_report_control_sets_0 -report_type report_control_sets:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_control_sets_0]
+if { $obj != "" } {
+set_property -name "options.verbose" -value "1" -objects $obj
+
+}
+# Create 'impl_1_place_report_incremental_reuse_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0] "" ] } {
+  create_report_config -report_name impl_1_place_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+
+}
+# Create 'impl_1_place_report_incremental_reuse_1' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_1] "" ] } {
+  create_report_config -report_name impl_1_place_report_incremental_reuse_1 -report_type report_incremental_reuse:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_incremental_reuse_1]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+
+}
+# Create 'impl_1_place_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_place_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps place_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_place_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'impl_1_post_place_power_opt_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_power_opt_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_post_place_power_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_place_power_opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_place_power_opt_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'impl_1_phys_opt_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps phys_opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_phys_opt_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "is_enabled" -value "0" -objects $obj
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'impl_1_route_report_drc_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_drc_0 -report_type report_drc:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_drc_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_route_report_methodology_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_methodology_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_methodology_0 -report_type report_methodology:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_methodology_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_route_report_power_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_power_0 -report_type report_power:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_power_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_route_report_route_status_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_route_status_0 -report_type report_route_status:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_route_status_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_route_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "options.max_paths" -value "10" -objects $obj
+
+}
+# Create 'impl_1_route_report_incremental_reuse_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_incremental_reuse_0 -report_type report_incremental_reuse:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_incremental_reuse_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_route_report_clock_utilization_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_clock_utilization_0 -report_type report_clock_utilization:1.0 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_clock_utilization_0]
+if { $obj != "" } {
+
+}
+# Create 'impl_1_route_report_bus_skew_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_bus_skew_0] "" ] } {
+  create_report_config -report_name impl_1_route_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps route_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_route_report_bus_skew_0]
+if { $obj != "" } {
+set_property -name "options.warn_on_violation" -value "1" -objects $obj
+
+}
+# Create 'impl_1_post_route_phys_opt_report_timing_summary_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0] "" ] } {
+  create_report_config -report_name impl_1_post_route_phys_opt_report_timing_summary_0 -report_type report_timing_summary:1.0 -steps post_route_phys_opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_timing_summary_0]
+if { $obj != "" } {
+set_property -name "options.max_paths" -value "10" -objects $obj
+set_property -name "options.warn_on_violation" -value "1" -objects $obj
+
+}
+# Create 'impl_1_post_route_phys_opt_report_bus_skew_0' report (if not found)
+if { [ string equal [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_bus_skew_0] "" ] } {
+  create_report_config -report_name impl_1_post_route_phys_opt_report_bus_skew_0 -report_type report_bus_skew:1.1 -steps post_route_phys_opt_design -runs impl_1
+}
+set obj [get_report_configs -of_objects [get_runs impl_1] impl_1_post_route_phys_opt_report_bus_skew_0]
+if { $obj != "" } {
+set_property -name "options.warn_on_violation" -value "1" -objects $obj
+
+}
+set obj [get_runs impl_1]
+set_property -name "strategy" -value "Vivado Implementation Defaults" -objects $obj
+set_property -name "steps.write_bitstream.args.readback_file" -value "0" -objects $obj
+set_property -name "steps.write_bitstream.args.verbose" -value "0" -objects $obj
+
+# set the current impl run
+current_run -implementation [get_runs impl_1]
+
+puts "INFO: Project created:${_xil_proj_name_}"
+# Create 'drc_1' gadget (if not found)
+if {[string equal [get_dashboard_gadgets  [ list "drc_1" ] ] ""]} {
+create_dashboard_gadget -name {drc_1} -type drc
+}
+set obj [get_dashboard_gadgets [ list "drc_1" ] ]
+set_property -name "reports" -value "impl_1#impl_1_route_report_drc_0" -objects $obj
+
+# Create 'methodology_1' gadget (if not found)
+if {[string equal [get_dashboard_gadgets  [ list "methodology_1" ] ] ""]} {
+create_dashboard_gadget -name {methodology_1} -type methodology
+}
+set obj [get_dashboard_gadgets [ list "methodology_1" ] ]
+set_property -name "reports" -value "impl_1#impl_1_route_report_methodology_0" -objects $obj
+
+# Create 'power_1' gadget (if not found)
+if {[string equal [get_dashboard_gadgets  [ list "power_1" ] ] ""]} {
+create_dashboard_gadget -name {power_1} -type power
+}
+set obj [get_dashboard_gadgets [ list "power_1" ] ]
+set_property -name "reports" -value "impl_1#impl_1_route_report_power_0" -objects $obj
+
+# Create 'timing_1' gadget (if not found)
+if {[string equal [get_dashboard_gadgets  [ list "timing_1" ] ] ""]} {
+create_dashboard_gadget -name {timing_1} -type timing
+}
+set obj [get_dashboard_gadgets [ list "timing_1" ] ]
+set_property -name "reports" -value "impl_1#impl_1_route_report_timing_summary_0" -objects $obj
+
+# Create 'utilization_1' gadget (if not found)
+if {[string equal [get_dashboard_gadgets  [ list "utilization_1" ] ] ""]} {
+create_dashboard_gadget -name {utilization_1} -type utilization
+}
+set obj [get_dashboard_gadgets [ list "utilization_1" ] ]
+set_property -name "reports" -value "synth_1#synth_1_synth_report_utilization_0" -objects $obj
+set_property -name "run.step" -value "synth_design" -objects $obj
+set_property -name "run.type" -value "synthesis" -objects $obj
+
+# Create 'utilization_2' gadget (if not found)
+if {[string equal [get_dashboard_gadgets  [ list "utilization_2" ] ] ""]} {
+create_dashboard_gadget -name {utilization_2} -type utilization
+}
+set obj [get_dashboard_gadgets [ list "utilization_2" ] ]
+set_property -name "reports" -value "impl_1#impl_1_place_report_utilization_0" -objects $obj
+
+move_dashboard_gadget -name {utilization_1} -row 0 -col 0
+move_dashboard_gadget -name {power_1} -row 1 -col 0
+move_dashboard_gadget -name {drc_1} -row 2 -col 0
+move_dashboard_gadget -name {timing_1} -row 0 -col 1
+move_dashboard_gadget -name {utilization_2} -row 1 -col 1
+move_dashboard_gadget -name {methodology_1} -row 2 -col 1

HDLForBeginners_Examples/ZynqSeries/fibonacci.sv

@@ -0,0 +1,70 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 08/08/2023 10:01:25 PM
+// Design Name: 
+// Module Name: fibonacci
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module fibonacci
+  #(
+    parameter SEQ_BITS = 32
+    )
+   (
+     
+    input		  clk, 
+    input		  rst, 
+   
+    input		  get_next_number, 
+   
+    output [SEQ_BITS-1:0] seq,
+    output		  seq_valid
+   
+    );
+   
+   // calculates the next number in the fibonacci series
+   
+   // initial values in sequence
+   // _i indicates an internal value
+   logic [1:0][SEQ_BITS-1:0] seq_i;
+   logic		     seq_valid_i;
+   
+   
+   
+   always_ff @(posedge clk) begin
+      if (rst) begin
+         seq_i[0] <= 0;
+         seq_i[1] <= 1; 
+         seq_valid_i <= 0;
+         
+      end
+      else begin
+         seq_valid_i <= 0;
+         if (get_next_number) begin
+            seq_valid_i <= 1;
+            seq_i[1] <= seq_i[0];
+            seq_i[0] <= seq_i[0] + seq_i[1];
+         end
+      end
+   end
+   
+   
+   assign seq = seq_i[1];
+   assign seq_valid = seq_valid_i;
+   
+   
+endmodule

HDLForBeginners_Examples/ZynqSeries/fibonacci_bram.sv

@@ -0,0 +1,112 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 08/08/2023 10:01:25 PM
+// Design Name: 
+// Module Name: fibonacci_bram
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module fibonacci_bram
+  (
+   
+   input	 clk, 
+   input	 rst, 
+  
+   output [31:0] BRAM_addr,
+   output	 BRAM_clk,
+   output [31:0] BRAM_din,
+   input [31:0]	 BRAM_dout,
+   output	 BRAM_en,
+   output	 BRAM_rst,
+   output [3:0]	 BRAM_we
+  
+   );
+   
+   localparam	 BRAM_DEPTH = 2048;
+   localparam	 SEQ_BITS = 32;
+   localparam	 CLK_MHZ = 100;
+   
+   logic [SEQ_BITS-1:0]	seq_num;
+   logic		seq_valid;
+   
+   logic [31:0]		address;
+   logic [31:0]		counter;
+   
+   logic		get_next_number;
+   assign get_next_number = (counter == 1) ? 1 : 0;
+   
+   localparam		COUNTER_MAX = CLK_MHZ*500000;
+   
+   fibonacci
+     #(
+       .SEQ_BITS(SEQ_BITS)
+       ) 
+   fibonacci_i
+     (
+      .clk(clk),
+      .rst(rst | address == BRAM_DEPTH-1),
+
+      .get_next_number(get_next_number),
+      .seq(seq_num),
+      .seq_valid(seq_valid)
+
+      );
+   
+   
+   always_ff @(posedge clk) begin
+      if (rst) begin
+         address <= 0;
+         
+      end
+      else begin
+         if (seq_valid) begin
+            if (address < BRAM_DEPTH-1) begin
+               address <= address + 1;
+            end
+            else begin
+               address <= 0;
+               
+            end            
+         end
+      end
+   end 
+   
+   always_ff @(posedge clk) begin
+      if (rst) begin
+         counter <= 0; 
+         
+      end
+      else begin
+         if (counter < COUNTER_MAX-1) begin
+            counter <= counter + 1;
+         end 
+         else begin
+            counter <= 0;
+         end
+      end
+   end 
+   
+   
+   assign BRAM_addr = address << 2;
+   assign BRAM_clk = clk;
+   assign BRAM_din = seq_num;
+   assign BRAM_en = 1;
+   assign BRAM_rst = rst;
+   assign BRAM_we = {4{seq_valid}};
+   
+   
+endmodule