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WangXuan95_FPGA-NFC/README.md

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+![语言](https://img.shields.io/badge/语言-verilog_(IEEE1364_2001)-9A90FD.svg) ![仿真](https://img.shields.io/badge/仿真-iverilog-green.svg) ![部署](https://img.shields.io/badge/部署-quartus-blue.svg) ![部署](https://img.shields.io/badge/部署-vivado-FF1010.svg)
+
+[English](#en) | [中文](#cn)
+
+　
+
+<span id="en">FPGA NFC (RFID)</span>
+===========================
+
+Use FPGA to build an NFC PCD (card reader) from discrete components to protocol layer, supporting the ISO14443A standard.
+
+![FPGA_NFC](./figures/FPGA_NFC.png)
+
+　
+
+## Why?
+
+I want to play with Radio Freqency (RF), and show something different from others who play SDR. Then I find that the carrier frequency of NFC is only 13.56MHz, and the modulation method is amplitude modulation (ASK), which can realize a card reader with very low cost (the cheapest FPGA + 3Msps ADC + several discrete components). Both digital signal processing and protocol processing are performed in the FPGA, which is a complete small system. So here comes this project, which can fully support ISO14443A under the control of the serial port commands, and has successfully interacted with the M1 card.
+
+　
+
+## Concept Definition
+
+| concept                   | short name      | introduction                                                 |
+| ------------------------- | --------------- | ------------------------------------------------------------ |
+| Proximity Coupling Device | PCD, reader     | Provides energy to PICC and acts as a communication host, which is what this project wants to implement using FPGA. |
+| Proximity Card            | PICC, card, tag | These cards such as M1 card, UID card, electronic tag and so on. |
+| PCD-to-PICC               | TX, send        | PCD modulates the carrier to send information to the PICC.   |
+| PICC-to-PCD               | RX, receive     | PICC changes its impedance, so that the PCD can detect changes of carrier amplitude to receive information from PICC. |
+| NXP MIFARE Classic 1K     | M1 card         | A type of card that meets ISO14443A, which is very common in daily life, such as door control cards. |
+| ISO14443A                 | NFCA            | An NFC standard for personal cards. This project fully supports it from hardware to protocol. See [1,2,3] for details. |
+| ISO14443B                 | NFCB            | An NFC standard for personal cards. This project do not support its hardware. |
+| ISO15693                  | NFCV            | An NFC standard for industrial electronic tags. This project supports its hardware, but I haven't write its protocol in FPGA. |
+| Carrier                   | fc              | 13.56MHz, the drive coil of PCD resonates at this frequency. |
+| Subcarrier                | fs              | The smallest unit of modulation, that is, PCD and PICC will change the carrier amplitude at this frequency, 847.5 kHz, which is 1/16 of the carrier frequency. |
+| bit rate                  |                 | 8 subcarrier cycles may carry one bit, so bit rate is 105.9375 kHz |
+| Amplitude Shift Keying    | ASK             | carry information by changing the amplitude of the carrier.  |
+
+　
+
+## Poject ideas
+
+The 1st step is carrier generation. I use an FPGA pin to generate a 13.56MHz signal, which drives a resonant circuit by a MOSFET (FDV301N). Corresponding to the source file nfca_tx_modulate.v
+
+The 2nd step is the implementation of PCD-to-PICC (sub-carrier modulation). The modulation method of ISO14443A's PCD-to-PICC is 100% ASK (that is, in a sub-carrier cycle, either the carrier is sent at full amplitude, or the carrier is not sent at all), which is also very easy for FPGA. Corresponding to the source file nfca_tx_modulate.v.
+
+The 3rd step is the implementation of PCD-to-PICC-to-PCD. The modulation method of PICC-to-PCD is 2%~10% ASK (that is, in a subcarrier cycle, the carrier is either attenuated a little or not attenuated). I use a diode (1N4148), a capacitor, and a resistor for envelope detection, obtain the frequency of envelope=subcarrier frequency=847.5kHz, and then use an ADC to sample this envelope (corresponding to the source file ad7276_read.v). Envelope detection reduces the requirement for ADC sampling rate, avoiding directly sample the carrier with an ADC ≥ 20Msps, but only using a 3Msps ADC (AD7276B) to sample the subcarrier. In the FPGA, a digital signal processing (DSP) algorithm is used to detect the ASK signal of the PICC-to-PCD from the ADC sampling data, that is, to detect the small change of the ADC sampling data amplitude, which requires anti-noise capability and adaptive signal amplitude. I use median filtering to subtract the original signal, and then do proportional threshold judgment, the effect is good enough. corresponding to the source file nfca_rx_dsp.v.
+
+The last step is to implement the codec protocol of ISO14443A, including sending checksum generation and packetization (corresponding to the source file nfca_tx_frame.v), unpacking the receiving protocol (corresponding to the source files nfca_rx_tobits.v and nfca_rx_tobytes.v), this part is in accordance with the Specification [3].
+
+I also implemented the serial port control logic in FPGA, parsed the serial port commands sent by the Host-PC to the FPGA into NFC send data (corresponding to the code files uart_rx.v and uart_rx_parser.v), and sent the NFC received data to the Host- PC (corresponding to the code file uart_tx.v). The user can send data to the card in the "serial assistant" software, and then receive the data returned by the PICC.
+
+The following figure is the system block diagram, in which the Verilog source file names are marked under the modules.
+
+```
+_________   _________________________________________________________________________________________________________
+        |   |  ___________________________________________________________________________________________________  |
+        |   |  |                       _________________________________________________________                 |  |
+        |   |  |         ___________   |    ____________          _____________                |                 |  |   ____________    ____________
+        |   |  | uart_rx | UART RX |   |    |  frame   |          | RFID TX   |                |                 |  |   | FDV301N  |    | Resonant |      ___________
+uart_tx |---|->|-------->|  logic  |---|--->|  pack    |--------->| modulate  |--------------->|---------------->|--|-->| N-MOSFET |--->| circuit  |      |         |
+        |   |  |         -----------   |    ------------          -------------                |   carrier_out   |  |   |          |    |          |---v->| Antenna |
+        |   |  |           uart_rx.v   | nfca_tx_frame.v            | nfca_tx_modulate.v       |                 |  |   ------------    ------------   |  |  Coil   |
+        |   |  |    uart_rx_parser.v   |                      rx_on |                          |                 |  |                                  |  |         |
+        |   |  |          fifo_sync.v  |                            |                          |                 |  |                                  |  -----------
+        |   |  |         ___________   |  ___________         ______V____        ____________  |  _____________  |  |     ___________   ____________   |
+        |   |  | uart_tx | UART TX |   |  | bytes   |         | bits    |        | ADC data |  |  | AD7276B   |  |  |     | AD7276B |   | Envelop  |   |
+uart_rx |<--|--|<--------|  logic  |<--|--| rebuild |<--------| rebuild |<-------| DSP      |<-|--|ADC reader |<-|<-|-----|   ADC   |<--| detection|<---
+        |   |  |         -----------   |  -----------         -----------        ------------  |  -------------  |  | SPI |         |   |          |
+        |   |  |          uart_tx.v    |nfca_rx_tobytes.v    nfca_rx_tobits.v   nfca_rx_dsp.v  |  ad7276_read.v  |  |     -----------   ------------
+    GND |---|  |                       --------------------------------------------------------|                 |  |
+        |   |  |                                      nfca_controller.v                                          |  |
+        |   |  ---------------------------------------------------------------------------------------------------  |
+        |   |                                    uart2nfca_system_top.v                                             |
+---------    --------------------------------------------------------------------------------------------------------
+ Host-PC                                               FPGA (fpga_top.v )                                                       Analog Circuit
+```
+
+　
+
+# Build Hardware
+
+This PCB design is available at LCEDA: [oshwhub.com/wangxuan/rfid_nfc_iso14443a_iso15693_breakoutboard](https://oshwhub.com/wangxuan/rfid_nfc_iso14443a_iso15693_breakoutboard)
+
+In the PCB folder is the hardware design of this repository (named NFC_BreakoutBoard), which mainly includes:
+
+- Sender circuit: N-MOSFET, inductor, etc.
+- Receiver circuit: envelop detection diode, AD7276B.
+- A 4 turns coil.
+
+Please use the manufacturing file [NFC_BreakoutBoard_gerber.zip](./PCB) to proof the PCB and then solder its components.
+
+After soldering, connect the PCB to FPGA:
+
+- J1 should be connected to 7V\~9V power supply.
+- J2 should be connected to the FPGA board (occupies 4 common IO pins of the FPGA, and the level should be 3.3V or 2.5V). Note: The frequency of ADC_SCK is up to 40.68MHz, so it is not recommended to use Dupont wires, but to plug it directly into the FPGA development board with pin headers.
+
+| ![sch](./figures/NFC_BreakoutBoard_sch.png)  |
+| :------------------------------------------: |
+| **Figure** : Schematic of NFC_BreakoutBoard. |
+
+| ![board](./figures/NFC_BreakoutBoard.jpg) |
+| :---------------------------------------: |
+|      **Figure** : NFC_BreakoutBoard.      |
+
+　
+
+# FPGA Deployment
+
+When deploying to an FPGA, all [.v]() files in the [RTL](./RTL) directory and the [RTL/nfca_controller](./RTL/nfca_controller) directory need to be added to the project. The top-level file is fpga_top.v , and the constraint method of each pin of it is shown in the code comments, as follows:
+
+```verilog
+module fpga_top(
+    input  wire        rstn_btn,        // press button to reset, pressed=0, unpressed=1
+    input  wire        clk50m,          // a 50MHz Crystal oscillator
+    
+    // AD7276 ADC SPI interface
+    output wire        ad7276_csn,      // connect to AD7276's CSN   (NFC_Breakboard's AD7276_CSN)
+    output wire        ad7276_sclk,     // connect to AD7276's SCLK  (NFC_Breakboard's AD7276_SCLK)
+    input  wire        ad7276_sdata,    // connect to AD7276's SDATA (NFC_Breakboard's AD7276_SDATA)
+    
+    // NFC carrier generation signal
+    output wire        carrier_out,     // connect to FDV301N(N-MOSFET)'s gate (栅极)  (NFC_Breakboard's CARRIER_OUT)
+    
+    // connect to Host-PC (typically via a USB-to-UART chip on FPGA board, such as FT232, CP2102 or CH340)
+    input  wire        uart_rx,         // connect to USB-to-UART chip's UART-TX
+    output wire        uart_tx,         // connect to USB-to-UART chip's UART-RX
+    
+    // connect to on-board LED's (optional)
+    output wire        led0,            // led0=1 indicates PLL is normally run
+    output wire        led1,            // led1=1 indicates carrier is on
+    output wire        led2             // led2=1 indicates PCD-to-PICC communication is done, and PCD is waiting for PICC-to-PCD
+);
+```
+
+All code is a Verilog behavior-level implementation that supports any FPGA platform. Except that the altpll block in fpga_top.v is an Altera Cyclone IV-only primitive that generates the 81.36MHz clock to drive the NFC controller. If you are not using Altera Cyclone IV, please use other IP cores (such as Xilinx's clock wizard) or primitives instead, just generate an 81.36MHz clock to drive the NFC submodule.
+
+　
+
+# Interaction via serial port
+
+After the FPGA is programmed, the Host-PC can control the FPGA to interact with the PICC through the serial port. The serial port configuration should be `9600,8,n,1` (that is, baud rate=9600, 8 data bits, no parity bit, 1 stop bit). Serial port communication is in the form of "one question and one answer", sending the data you want to send to the card, and then the card returns the data. Each command and response ends with `\r` or `\n` or `\r\n` (i.e. one command/response per line)
+
+First of all, it is recommended to use the "Serial Assistant" software on the PC instead of software such as Putty. Because the logic I designed is: FPGA will turn on the carrier when it receives a serial command, and automatically turn off the carrier if there is no next command within 1.2 seconds. This is enough time for an application that controls the serial port. But 1.2 seconds is not enough for human to type the next command, which will cause the carrier to be turned off, the card to be powered off, and the state obtained before the card will disappear. "Serial Assistant" can send multiple lines of commands at a time, while Putty cannot.
+
+## Communicate with an M1 card
+
+I tried it with my door control card and some M1 "white cards" I bought online, because they are all M1 cards and behave similarly. Take one of the cards as an example:
+
+Enter the following command in the "Serial Assistant" and click send, which will send 0x26 (which is the "REQA" specified by ISO14443 [3]) to the card (note that a carriage return (`\n`) must be added at the end, so that it will be regarded as a complete command):
+
+```
+26
+```
+
+Then the "Serial Assistant" gets receives as following, which is the "ATQA" specified by ISO14443, which means Bit frame anticollision.
+
+```
+04 00
+```
+
+> **Note**: If the card is not detected, or a waveform that does not meet the standard is received due to noise interference, the serial port will receive the character `n` . Indicates: The FPGA is functioning normally, but no card detected/error has occurred.
+
+Then we add an "AntiCollision" command specified by ISO14443 to the next line in the "send box", this new command is to obtain the UID of the card.
+
+```
+26
+93 20
+```
+
+The card response is as follows (the first line is the "ATQA" in response to "REQA", the second line is the UID in response to the "AntiCollision" command):
+
+```
+04 00
+4B BE DE 79 52
+```
+
+Then we append a "SELECT" command specified by ISO14443 to the next line in the "send box", it will select the card with the UID we just obtained:
+
+```
+26
+93 20
+93 70 4B BE DE 79 52
+```
+
+The card responds "SAK=0x08" specified by ISO14443 (representing it is an M1 card. The following 0xB6 0xDD is the CRC code):
+
+```
+04 00
+4B BE DE 79 52
+08 B6 DD
+```
+
+> **Note**: The user does not need to add the CRC code when sending, FPGA will automatically calculate and append the CRC where the check code needs to be added as specified in the protocol.
+>
+> **Note**: When receiving, the CRC code will not be checked and deleted by FPGA, and will be displayed on the serial port. 
+
+After knowing that this is the M1 card, we can send Phase1 (the first stage) of the M1 card's Key authentication command to obtain a random number from the card (note that this command is not specified by ISO14443, but is unique to the M1 card, and other cards do not will respond to this command). We append the next line in the "Send Box":
+
+```
+26
+93 20
+93 70 4B BE DE 79 52
+60 07
+```
+
+The card responds with a 4-byte random number:
+
+```
+04 00
+4B BE DE 79 52
+08 B6 DD
+EF 9B B6 5A
+```
+
+The subsequent authentication, reading, and writing steps of M1 card are very complicated and are not the scope of this project. This project only focuses on the underlying implementation of the interaction between PCD and PICC. You can use the upper-layer application (C, Python, C# programming) to control the serial port for further operation of the M1 card.
+
+## More test for AntiCollision 
+
+"AntiCollision" is a multi-card detection and anti-collision mechanism specified by ISO14443, because different cards have different UIDs, and the PCD uses UIDs to distinguish different cards.
+
+I put two M1 cards on the coil, and sends REQA and AntiCollision commands, trying to get the UID of the card:
+
+```
+26
+93 20 
+```
+
+Serial port receives:
+
+```
+04 00
+01:1
+```
+
+The meaning of `01:1` is an incomplete byte 0x01 (00000001), and `:1` means that the collision occurred in the lowest 1st bit of the byte. This shows that the lower 2 bits of the first byte of the UIDs of the two cards are 01 and 11 respectively. The 0th bit is the same, so there is no conflict, and the 1st bit is different, so there is a conflict.
+
+Now if you want to select the card whose lower 2 bits are 11, you need to send a bit-oriented frame specified by ISO14443, the last byte of this frame is incomplete. Send with serial port:
+
+```
+26
+93 20
+93 22 03:2
+```
+
+Note that `93 22 03:2` is a bit-oriented frame. `22` means: The card reader additionally specifies 2 bits in the UID, and the card that is satisfied will respond, and the card that is not satisfied will not respond. The following `03:2` means that only the lower 2 bits of 0x03 (00000011) are sent, which is 11 .
+
+Serial port receives:
+
+```
+04 00
+01:1
+48 BE DE 79 52
+```
+
+The last response is 48 BE DE 79 52. Note that 48 is not a complete byte. It is only valid for the upper 6 bits. It also needs to be spliced with the lower 2 bits (that is, the lower 2 bits of 0x03) to be a complete byte.
+
+A simple splicing method is to bitwise OR the incomplete byte 0x03 sent by the card reader and the incomplete byte 0x48 returned by the card to get 0x4B. Indicate the UID of this card = 4B BE DE 79 52.
+
+Similarly, if you want to select the card whose lower 2 bits are 01, you need to send via serial port:
+
+```
+26
+93 20
+93 22 01:2
+```
+
+Serial port receives:
+
+```
+04 00
+01:1
+00 1D DD 79 B8
+```
+
+Bitwise OR the incomplete byte 0x01 sent by the card reader and the incomplete byte 0x00 returned by the card to get 0x01. Indicates the UID of the other card = 01 1D DD 79 B8.
+
+If the number of cards is more than 3, there may be multiple conflicts according to this process. For each conflict, you must specify the card with the digit = 0 or the card with = 1 that you want to choose.
+
+## Bitwise AntiCollision Example
+
+In order to facilitate everyone to deepen the understanding of the AntiCollision process of ISO14443, here we show an example of bit-by-bit AntiCollision, send the following commands through the serial port, and each command only specifies one more bit.
+
+```
+26
+93 20
+93 21 01:1
+93 22 01:2
+93 23 01:3
+93 24 01:4
+93 25 01:5
+93 26 01:6
+93 27 01:7
+93 30 01
+93 31 01 01:1
+93 32 01 01:2
+93 33 01 05:3
+93 34 01 0D:4
+93 35 01 1D:5
+93 36 01 1D:6
+93 37 01 1D:7
+93 40 01 1D 
+93 41 01 1D 01:1
+93 42 01 1D 01:2
+93 43 01 1D 05:3
+93 44 01 1D 0D:4
+93 45 01 1D 1D:5
+93 46 01 1D 1D:6
+93 47 01 1D 5D:7
+93 50 01 1D DD 
+93 51 01 1D DD 01:1
+93 52 01 1D DD 01:2
+93 53 01 1D DD 01:3
+93 54 01 1D DD 09:4
+93 55 01 1D DD 19:5
+93 56 01 1D DD 39:6
+93 57 01 1D DD 79:7
+93 60 01 1D DD 79
+93 61 01 1D DD 79 00:1
+93 62 01 1D DD 79 00:2
+93 63 01 1D DD 79 00:3
+93 64 01 1D DD 79 08:4
+93 65 01 1D DD 79 18:5
+93 66 01 1D DD 79 38:6
+93 67 01 1D DD 79 38:7
+```
+
+Serial port will receive:
+
+```
+04 00
+01 1D DD 79 B8
+00 1D DD 79 B8
+00 1D DD 79 B8
+00 1D DD 79 B8
+00 1D DD 79 B8
+00 1D DD 79 B8
+00 1D DD 79 B8
+00 1D DD 79 B8
+1D DD 79 B8
+1C DD 79 B8
+1C DD 79 B8
+18 DD 79 B8
+10 DD 79 B8
+00 DD 79 B8
+00 DD 79 B8
+00 DD 79 B8
+DD 79 B8
+DC 79 B8
+DC 79 B8
+D8 79 B8
+D0 79 B8
+C0 79 B8
+C0 79 B8
+80 79 B8
+79 B8
+78 B8
+78 B8
+78 B8
+70 B8
+60 B8
+40 B8
+00 B8
+B8
+B8
+B8
+B8
+B0
+A0
+80
+80
+```
+
+　
+
+# Debug
+
+If you put the card on the coil and send serial commands, the serial response is not as expected, you should:
+
+- Check if the serial port responds with the character `n`, if not, the FPGA is not working properly. Check the serial connection and baud rate settings, and see if the program is programed into the FPGA.
+- If it responds with the character `n` no matter what, it means that the FPGA is working properly, but no card is detected. Please check the NFC_BreakoutBoard's power supply, FPGA and NFC_BreakoutBoard's connections and pin assignments. If there's no problem, stick the card to the coil to ensure signal strength.
+- If it still doesn't work, the further debugging method is to observe the signal with an oscilloscope, connect the oscilloscope to the J3 (SMA interface) of the NFC_BreakoutBoard, and the envelope detection of the carrier should be observed here. Let the serial port send 26 (REQA) every 2 seconds, and you should be able to see the modulation process of carrier startup and modulation of 0x26 on the oscilloscope. Then observe whether there is a weak signal change (probably only a few tens of mV) after the modulation is sent, which is the response of the card to the card reader.
+
+　
+
+# RTL Simulation
+
+The files of simulation are in the directory [SIM](./SIM), where:
+
+- [tb_nfca_controller.v](./SIM) is a testbench for nfca_controller.v.
+- [tb_nfca_controller_run_iverilog.bat](./SIM) is a iverilog simulation command script.
+
+The behavior of the simulation is: send some frames to the nfca_controller's transmit interface, and on the carrier_out signal you can see the modulated PCD-to-PICC modulation waveform. But it cannot simulate PICC-to-PCD because I didn't write the PICC's Verilog model.
+
+Before using iverilog for simulation, you need to install iverilog , see: [iverilog_usage](https://github.com/WangXuan95/WangXuan95/blob/main/iverilog_usage/iverilog_usage.md)
+
+Then double-click tb_nfca_controller_run_iverilog.bat to run the simulation, and then you can open the generated dump.vcd file to view the waveform. The following figure is the modulation waveform of the 0x26 (REQA) frame:
+
+|                 ![wave](./figures/wave.png)                  |
+| :----------------------------------------------------------: |
+| Figure: Modulation waveform for frame 0x26 (REQA) in simulation. |
+
+　
+
+# Reference
+
+* [1] ST TN1216 Technical note, ST NFC guide, https://www.st.com/resource/en/technical_note/dm00190233-st25-nfc-guide-stmicroelectronics.pdf
+* [2] ISO/NFC Standards and Specifications Overview, https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/667/2072.ISO_5F00_NFC-Standards-and-Specifications-Overview_5F00_2014.pdf
+* [3] ISO/IEC STANDARD 14443-3, http://emutag.com/iso/14443-3.pdf
+* [4] THM3060 Card Reader.
+
+　
+
+　
+
+　
+
+　
+
+　
+
+
+<span id="cn">FPGA NFC (RFID)</span>
+===========================
+
+用 FPGA 从底层开始搭建一个 NFC PCD (读卡器)，支持 ISO14443A 标准。
+
+![FPGA_NFC](./figures/FPGA_NFC.png)
+
+　
+
+## 为什么要做本项目？
+
+本人想玩玩射频，又想展示一些和其它玩 SDR 的人不一样的东西。然后发现 NFC 的载波频率只有 13.56MHz，且调制方式为调幅（ASK） ，可以用很低的成本（最廉价的 FPGA + 1个3Msps 的ADC + 几个分立器件）实现一个读卡器。FPGA内既进行数字信号处理，又进行协议处理，是一个完整的~~可以装X的~~小系统。于是就有了本项目，它能在 PC 端串口命令控制下，完整地支持 ISO14443A 。并成功地与 M1卡 交互。
+
+　
+
+## 名词释义
+
+| 名词                      | 简称 | 直观名称               | 释义                                                         |
+| ------------------------- | ---- | ---------------------- | ------------------------------------------------------------ |
+| Proximity Coupling Device | PCD  | 读卡器、读写器、Reader | 给卡片提供能量，并作为通讯主机的设备，其实就是读卡器，也就是本项目要实现的东西。 |
+| Proximity Card            | PICC | 标签、卡片、TAG        | M1卡、UID卡、电子标签这些卡片。不同类的卡片可能满足不同标准。 |
+| PCD-to-PICC               | TX   | 发送                   | PCD 对载波进行调制，传输信息到 PICC                          |
+| PICC-to-PCD               | RX   | 接收                   | PICC 改变自身阻抗，使得 PCD 探测到载波幅度发生变化，从而传输信息到 PCD 。 |
+| NXP MIFARE Classic 1K     | M1卡 |                        | 一种满足 ISO14443A 的卡片，日常生活很常见，比如门禁卡。      |
+| ISO14443A                 | NFCA |                        | 一种 NFC 标准，用于个人卡片。本项目从硬件到协议完全支持。详见 [1,2,3] |
+| ISO14443B                 | NFCB |                        | 一种 NFC 标准，用于个人卡片。本项目硬件不支持。详见 [1,2,3]  |
+| ISO15693                  | NFCV |                        | 一种 NFC 标准，用于工业电子标签。本项目硬件支持，但 FPGA 尚未编写其协议。详见 [1,2] |
+| Carrier、载波             | fc   | 13.56MHz 载波          | FPGA 发射引脚需要产生的频率，驱动线圈在这个频率下谐振。      |
+| Subcarrier、副载波        | fs   | 847.5 kHz 副载波       | 调制的最小单位（PCD和PICC会以这个频率改变调制幅度），是载波频率的 1/16 |
+| 位频率                    |      | 105.9375 kHz           | 8个副载波周期可能携带一位 (bit) 数据信息                     |
+| Amplitude Shift Keying    | ASK  | 调幅                   | 通过改变载波幅度来传送信息                                   |
+
+更多简称详见引用 [1,2,3]
+
+　
+
+## 项目思路
+
+首先是载波生成，我们用 FPGA 的引脚产生 13.56MHz 的信号（对应代码文件 nfca_tx_modulate.v），该信号驱动一个 MOS 管 (FDV301N) + 一个谐振电路来让天线(线圈)谐振。
+
+其次是载波调制发送，ISO14443A 的 PCD-to-PICC 的副载波调制方式是 100% ASK （即在一个副载波周期内，要么满幅度发送载波，要么完全不发送载波），这对 FPGA 也是很容易实现的（对应代码文件 nfca_tx_modulate.v）。
+
+然后是接收卡片的调制信息，PICC-to-PCD 的调制方式是 2%~10% 的 ASK （即在一个副载波周期内，要么让载波衰减一点，要么不衰减）。我用二极管(1N4148)+电容+电阻来做包络检波，得到包络线的频率=副载波频率=847.5kHz，然后用 ADC 对包络线采样（对应代码文件 ad7276_read.v）。包络检波降低了 ADC 采样率的需求，避免直接使用 ≥20Msps 的 ADC 来采样载波，而是只用一个 3Msps 的 ADC (AD7276B) 来采样副载波即可。在 FPGA 内，用一个数字信号处理(DSP)算法来从 ADC 采样数据中检测 PICC-to-PCD 的 ASK 信号，即检测 ADC 采样数据幅度的微小变化，需要有抗噪声能力，并自适应信号幅度。我用的是中值滤波减去原始信号，再做比例阈值判断，效果不错（对应代码文件 nfca_rx_dsp.v）。
+
+最后是实现 ISO14443A 的编解码协议，包括发送校验生成和封包（对应代码文件 nfca_tx_frame.v）、接收协议的解包（对应代码文件 nfca_rx_tobits.v 和 nfca_rx_tobytes.v），这部分是按照 Spec 文档  [3] 编写的。
+
+我还在 FPGA 中实现了串口控制逻辑，将 Host-PC 发送给 FPGA 的串口命令解析成 NFC 发送数据（对应代码文件 uart_rx.v 和 uart_rx_parser.v），并将 NFC 接收数据通过串口发送给 Host-PC （对应代码文件 uart_tx.v）。用户可以在 Host-PC 的”串口调试工具“中发送数据给卡片，然后收到卡片返回的数据。
+
+下图是系统框图，其中 FPGA 中的模块下方逐个标注了 Verilog 代码文件名。
+
+```
+_________   _________________________________________________________________________________________________________
+        |   |  ___________________________________________________________________________________________________  |
+        |   |  |                       _________________________________________________________                 |  |
+        |   |  |         ___________   |    ____________          _____________                |                 |  |   ____________    ____________
+        |   |  | uart_rx | UART RX |   |    |  frame   |          | RFID TX   |                |                 |  |   | FDV301N  |    | Resonant |      ___________
+uart_tx |---|->|-------->|  logic  |---|--->|  pack    |--------->| modulate  |--------------->|---------------->|--|-->| N-MOSFET |--->| circuit  |      |         |
+        |   |  |         -----------   |    ------------          -------------                |   carrier_out   |  |   |          |    |          |---v->| Antenna |
+        |   |  |           uart_rx.v   | nfca_tx_frame.v            | nfca_tx_modulate.v       |                 |  |   ------------    ------------   |  |  Coil   |
+        |   |  |    uart_rx_parser.v   |                      rx_on |                          |                 |  |                                  |  |         |
+        |   |  |          fifo_sync.v  |                            |                          |                 |  |                                  |  -----------
+        |   |  |         ___________   |  ___________         ______V____        ____________  |  _____________  |  |     ___________   ____________   |
+        |   |  | uart_tx | UART TX |   |  | bytes   |         | bits    |        | ADC data |  |  | AD7276B   |  |  |     | AD7276B |   | Envelop  |   |
+uart_rx |<--|--|<--------|  logic  |<--|--| rebuild |<--------| rebuild |<-------| DSP      |<-|--|ADC reader |<-|<-|-----|   ADC   |<--| detection|<---
+        |   |  |         -----------   |  -----------         -----------        ------------  |  -------------  |  | SPI |         |   |          |
+        |   |  |          uart_tx.v    |nfca_rx_tobytes.v    nfca_rx_tobits.v   nfca_rx_dsp.v  |  ad7276_read.v  |  |     -----------   ------------
+    GND |---|  |                       --------------------------------------------------------|                 |  |
+        |   |  |                                      nfca_controller.v                                          |  |
+        |   |  ---------------------------------------------------------------------------------------------------  |
+        |   |                                    uart2nfca_system_top.v                                             |
+---------    --------------------------------------------------------------------------------------------------------
+ Host-PC                                               FPGA (fpga_top.v )                                                       Analog Circuit
+```
+
+　
+
+# 搭建硬件
+
+该 PCB 设计在立创 EDA 开源： [oshwhub.com/wangxuan/rfid_nfc_iso14443a_iso15693_breakoutboard](https://oshwhub.com/wangxuan/rfid_nfc_iso14443a_iso15693_breakoutboard)
+
+PCB 文件夹里是硬件设计（命名为 NFC_BreakoutBoard），上面主要包括：
+
+- 发送电路 (驱动电路)： N-MOSFET、电感等。
+- 接收电路 (检波电路)：检波二极管、AD7276B。
+- 4匝线圈。
+
+请用制造文件 NFC_BreakoutBoard_gerber.zip 来打样 PCB 。然后焊接元件。最后把该PCB与FPGA连接，连接方法为：
+
+- J1 连接 7V~9V 的电源。
+- J2 连接 FPGA 开发板（占用 FPGA 4 个普通 IO 引脚，电平为 3.3V 或 2.5V 均可）。注意：ADC_SCK 的频率高达 40.68MHz，因此不建议用杜邦线，而是用排针直插到 FPGA 开发板。
+
+| ![sch](./figures/NFC_BreakoutBoard_sch.png) |
+| :-----------------------------------------: |
+|        图： NFC_BreakoutBoard 原理图        |
+
+| ![board](./figures/NFC_BreakoutBoard.jpg) |
+| :---------------------------------------: |
+|          图： NFC_BreakoutBoard           |
+
+　
+
+# FPGA 部署
+
+部署到 FPGA 时，所有 RTL 目录 和 RTL/nfca_controller 目录 中的 .v 文件都需要加入工程。顶层文件为 fpga_top.v ，它的每个引脚的连接方式见代码注释，如下：
+
+```verilog
+module fpga_top(
+    input  wire        rstn_btn,        // press button to reset, pressed=0, unpressed=1
+    input  wire        clk50m,          // a 50MHz Crystal oscillator
+    
+    // AD7276 ADC SPI interface
+    output wire        ad7276_csn,      // connect to AD7276's CSN   (NFC_Breakboard's AD7276_CSN)
+    output wire        ad7276_sclk,     // connect to AD7276's SCLK  (NFC_Breakboard's AD7276_SCLK)
+    input  wire        ad7276_sdata,    // connect to AD7276's SDATA (NFC_Breakboard's AD7276_SDATA)
+    
+    // NFC carrier generation signal
+    output wire        carrier_out,     // connect to FDV301N(N-MOSFET)'s gate (栅极)  (NFC_Breakboard's CARRIER_OUT)
+    
+    // connect to Host-PC (typically via a USB-to-UART chip on FPGA board, such as FT232, CP2102 or CH340)
+    input  wire        uart_rx,         // connect to USB-to-UART chip's UART-TX
+    output wire        uart_tx,         // connect to USB-to-UART chip's UART-RX
+    
+    // connect to on-board LED's (optional)
+    output wire        led0,            // led0=1 indicates PLL is normally run
+    output wire        led1,            // led1=1 indicates carrier is on
+    output wire        led2             // led2=1 indicates PCD-to-PICC communication is done, and PCD is waiting for PICC-to-PCD
+);
+```
+
+所有代码都是 Verilog 行为级实现，支持任意 FPGA 平台。除了 fpga_top.v 里的 altpll 模块是仅限于 Altera Cyclone IV 的原语，它用来生成 81.36MHz 时钟，驱动 NFC 控制器。如果你用的不是 Altera Cyclone IV，请使用其它的 IP 核（例如Xilinx 的 clock wizard）或原语来替换，总之只要生成 81.36MHz 的时钟来驱动 NFC 子模块即可。
+
+　
+
+# 串口交互
+
+FPGA 烧录之后，Host-PC 可以通过串口控制 FPGA 和 PICC 进行交互。串口格式为 9600,8,n,1 (即波特率=9600，8个数据位，无校验位，1个停止位)。串口通信是“一问一答”的形式，发送你要发给卡片的数据，然后卡片返回数据。每个命令和响应都以 \r 或 \n 或 \r\n 结尾（也就是一行一个命令/响应）
+
+首先，建议在 PC 上使用“串口调试助手”，而不是 putty 等软件。因为我设计的逻辑是： FPGA 会在收到串口命令时打开载波，如果1.2秒内没有下一个命令到来，就自动关闭载波。这对于一个控制串口的应用程序是足够的时间。但1.2秒是不够人是打出下一条命令的，会导致载波关闭，卡片下电，卡片之前获得的状态都消失了。“串口调试助手”可以一次发送多行命令，而 Putty 则一次只能打一条命令。
+
+> 注意：“串口调试助手” 往往有“16进制显示”和“16进制发送”选项，不需要勾选。本项目里 FPGA 会把收到的 ASCII 的十六进制形式处理成数字，也会把发出的 数字转成 ASCII 十六进制形��。
+
+## 与 M1 卡通信
+
+我用自己的门禁卡，和几个在 taobao 上买了的 M1 “白卡”试了试，因为都是 M1 卡，行为类似。以其中一个卡举例：
+
+在 “串口调试助手” 中输入如下命令并点击发送，这会发送 0x26（ISO14443 [3] 规定的 REQA）给卡片（注意末尾要加回车，这样才会被当成一条完整的命令）：
+
+```
+26
+```
+
+然后串口收到如下，这是 ISO14443 规定的 ATQA，含义是 Bit frame anticollision 。
+
+```
+04 00
+```
+
+> **注：如果没检测到卡，或者因噪声干扰而收到不符合标准规定的波形，串口的行尾会收到字符 n。表示： FPGA正常工作，但没检测到卡/出现错误。**
+
+然后我们在“发送框”里下一行附加一个  ISO14443 规定的 AntiCollision 命令，用来获得卡的 UID （因为很可能1.2秒已经过去了，卡片已经丢失了上次上电的信息，需要重新发送 REQA 0x26）。
+
+```
+26
+93 20
+```
+
+卡片响应如下（第一行是响应 REQA 的 ATQA，第二行是 响应 anticollision 的 UID）：
+
+```
+04 00
+4B BE DE 79 52
+```
+
+然后我们在“发送框”里下一行附加一个 ISO14443 规定的 SELECT 命令，用刚刚获取到的 UID 选中该卡：
+
+```
+26
+93 20
+93 70 4B BE DE 79 52
+```
+
+卡响应 ISO14443 规定的 SAK=0x08（代表它是 M1 卡。后面的 0xB6 0xDD 则是 CRC 校验码）：
+
+```
+04 00
+4B BE DE 79 52
+08 B6 DD
+```
+
+> **注：发送时不需要用户附加 CRC 校验码， FPGA 会在协议规定的需要加校验码的地方自动计算并追加 CRC。**
+>
+> **注：接收时，CRC 码不会被 FPGA 检查和删掉，会从串口展示出来。**
+
+根据卡片返回的 SAK ，知道这是 M1 卡后，我们可以发送 M1 卡的 Key 认证命令的 Phase1 （第一阶段），从卡片获取随机数（注意，该命令不是 ISO14443 规定的，而是 M1 卡独有的，其它卡不会响应这个命令）。我们在“发送框”里下一行附加：
+
+```
+26
+93 20
+93 70 4B BE DE 79 52
+60 07
+```
+
+卡片响应 4 字节随机数：
+
+```
+04 00
+4B BE DE 79 52
+08 B6 DD
+EF 9B B6 5A
+```
+
+M1 卡的后续认证、读写步骤很复杂，不是本工程关注的范围。本工程仅关注 ISO14443A PCD 与 PICC 交互的底层实现。你可以用上层应用程序（C, Python, C# 编程）控制串口来进行 M1 卡的进一步操作。
+
+## 测试 AntiCollision 
+
+AntiCollision 是 ISO14443 规定的多卡检测和防冲突机制，因为不同的卡拥有不同的 UID，读卡器用 UID 来区分不同的卡。
+
+我把 2 张 M1 卡放在线圈上，串口发送 REQA 和 AntiCollision 命令，试图获取卡的 UID：
+
+```
+26
+93 20 
+```
+
+串口收到：
+
+```
+04 00
+01:1
+```
+
+01:1 的含义是一个不完整的字节 0x01（00000001），:1 代表该冲突发生在该字节的从低到高第1位。
+
+这说明，这两个卡的 UID 的第一个字节的低2位分别是 01 和 11。第0位一样所以没发生冲突，第1位不一样所以发生了冲突。
+
+现在你想选择低2位是 11 的那个卡，就需要发送 ISO14443 规定的 bit-oriented 帧，这种帧的最后一个字节是不完整的。用串口发送：
+
+```
+26
+93 20
+93 22 03:2
+```
+
+93 22 03:2 是一个 bit-oriented 帧。 22 代表：读卡器额外指定 UID 中的 2 个 bit，满足的卡才会响应，不满足的卡就不要响应。后面的 03:2 代表只发送 0x03 (00000011) 的低2位，即 11 。
+
+串口收到：
+
+```
+04 00
+01:1
+48 BE DE 79 52
+```
+
+最后一条响应是 48 BE DE 79 52 ，注意，48 并不是一个完整字节，它只有高6bit有效，他还需要拼接上低2bit（即0x03的低2bit），才是完整的字节。
+
+一个简单的拼接方法是将读卡器发送的不完整字节 0x03 和卡片返回的不完整字节 0x48 进行按位或，得到 0x4B。
+
+表明这张卡的 UID = 4B BE DE 79 52。
+
+同理，如果想选择低2位是 01 的那个卡，就需要串口发送：
+
+```
+26
+93 20
+93 22 01:2
+```
+
+串口收到：
+
+```
+04 00
+01:1
+00 1D DD 79 B8
+```
+
+将读卡器发送的不完整字节 0x01 和卡片返回的不完整字节 0x00 进行按位或，得到 0x01。
+
+表明另一张卡的 UID = 01 1D DD 79 B8。
+
+如果卡的数量有3张以上，依照这个流程还可能发生多次冲突，每发生一次冲突都要指定你要选择发生冲突的那一位=0的卡，还是=1的卡。
+
+## 逐位 AntiCollision 的例子
+
+为了方便大家加深对 ISO14443 的 AntiCollision 过程的理解，下面我们展示一个逐位 AntiCollision 的例子，用串口发送如下这些命令，每条命令都只多指定一位。
+
+```
+26
+93 20
+93 21 01:1
+93 22 01:2
+93 23 01:3
+93 24 01:4
+93 25 01:5
+93 26 01:6
+93 27 01:7
+93 30 01
+93 31 01 01:1
+93 32 01 01:2
+93 33 01 05:3
+93 34 01 0D:4
+93 35 01 1D:5
+93 36 01 1D:6
+93 37 01 1D:7
+93 40 01 1D 
+93 41 01 1D 01:1
+93 42 01 1D 01:2
+93 43 01 1D 05:3
+93 44 01 1D 0D:4
+93 45 01 1D 1D:5
+93 46 01 1D 1D:6
+93 47 01 1D 5D:7
+93 50 01 1D DD 
+93 51 01 1D DD 01:1
+93 52 01 1D DD 01:2
+93 53 01 1D DD 01:3
+93 54 01 1D DD 09:4
+93 55 01 1D DD 19:5
+93 56 01 1D DD 39:6
+93 57 01 1D DD 79:7
+93 60 01 1D DD 79
+93 61 01 1D DD 79 00:1
+93 62 01 1D DD 79 00:2
+93 63 01 1D DD 79 00:3
+93 64 01 1D DD 79 08:4
+93 65 01 1D DD 79 18:5
+93 66 01 1D DD 79 38:6
+93 67 01 1D DD 79 38:7
+```
+
+串口收到：
+
+```
+04 00
+01 1D DD 79 B8
+00 1D DD 79 B8
+00 1D DD 79 B8
+00 1D DD 79 B8
+00 1D DD 79 B8
+00 1D DD 79 B8
+00 1D DD 79 B8
+00 1D DD 79 B8
+1D DD 79 B8
+1C DD 79 B8
+1C DD 79 B8
+18 DD 79 B8
+10 DD 79 B8
+00 DD 79 B8
+00 DD 79 B8
+00 DD 79 B8
+DD 79 B8
+DC 79 B8
+DC 79 B8
+D8 79 B8
+D0 79 B8
+C0 79 B8
+C0 79 B8
+80 79 B8
+79 B8
+78 B8
+78 B8
+78 B8
+70 B8
+60 B8
+40 B8
+00 B8
+B8
+B8
+B8
+B8
+B0
+A0
+80
+80
+```
+
+
+~~读卡器：你这每一位都保响应吗？~~
+
+~~卡片：瞧瞧你附近哪儿有那么多卡啊？这都是近场的通信，你想防冲突我还没必要防冲突呢。~~
+
+~~读卡器：我问你你每一位都保响应吗？~~
+
+~~卡片：你是故意找茬是不是？你 SELECT 不 SELECT 吧！~~
+
+~~读卡器：你要每一位都正确响应我肯定 SELECT 啊。~~
+
+~~读卡器：那他要是不响应呢？~~
+
+~~卡片：不响应，我免认证让你读写，满意了吧？~~
+
+~~卡片：00 1D DD 79 B8，无冲突。~~
+
+~~读卡器：93 22 01:2，剩下 38 bit 响应给我看看。~~
+
+~~卡片：你是故意找茬是不是！你 SELECT 不 SELECT 吧！~~
+
+　
+
+# 调试
+
+如果你将卡放在线圈上，并发送串口命令后，串口响应不符合预期，应该：
+
+- 看看串口是否响应字符 'n'，若没有，说明 FPGA 工作不正常。检查串口连接和波特率设置，并看看程序有没有烧到 FPGA 里。
+- 如果无论发什么，都响应字符 'n' ，说明 FPGA 正常工作，但没检测到卡。请检查 NFC_BreakoutBoard 的电源、FPGA 和 NFC_BreakoutBoard 的连接和引脚分配。如果没问题，将卡贴在线圈上保证信号强度。
+- 如果还不行，进一步的调试方法是用示波器观察信号，将示波器接在 NFC_BreakoutBoard 的 J3 (SMA 接口上)，这里应该能观察到对载波的包络检波。让串口每隔2秒发送一次 26 (REQA)，在示波器上应该能看到载波启动、调制 0x26 的调制过程。然后观察发送调制后大概 8us 后是否有微弱的信号变化（大概只会有几十 mV的浮动），这就是卡片对读卡器的响应。
+
+　
+
+# 仿真
+
+仿真所需要的文件在目录 SIM 里，其中：
+
+- tb_nfca_controller.v 是针对 nfca_controller.v 的 testbench 。
+- tb_nfca_controller_run_iverilog.bat 包含了 iverilog 仿真命令。
+
+该仿真的行为是：向 nfca_controller 的发送接口发送一些帧，在 carrier_out 信号上可以看到调制的 PCD-to-PICC 发送数据。但该仿真并不会仿真 PICC-to-PCD ，因为我没有编写 PICC 的 model 代码。
+
+使用 iverilog 进行仿真前，需要安装 iverilog ，见：[iverilog_usage](https://github.com/WangXuan95/WangXuan95/blob/main/iverilog_usage/iverilog_usage.md)
+
+然后双击 tb_nfca_controller_run_iverilog.bat 运行仿真，然后可以打开生成的 dump.vcd 文件查看波形。下图是看到的 0x26（REQA）帧的调制波形：
+
+|         ![wave](./figures/wave.png)         |
+| :-----------------------------------------: |
+| 图：仿真中看到的 0x26（REQA）帧的调制波形。 |
+
+　
+
+# 引用
+
+* [1] ST TN1216 Technical note, ST NFC guide, https://www.st.com/resource/en/technical_note/dm00190233-st25-nfc-guide-stmicroelectronics.pdf
+* [2] ISO/NFC Standards and Specifications Overview, https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/667/2072.ISO_5F00_NFC-Standards-and-Specifications-Overview_5F00_2014.pdf
+* [3] ISO/IEC STANDARD 14443-3, http://emutag.com/iso/14443-3.pdf
+* [4] THM3060 读卡器 原理图（好像没有官方公开，~~国内公司老毛病了~~。可以上 baidu 搜，或 taobao 买个模块，商家就给你原理图了）
+
+
+

WangXuan95_FPGA-NFC/RTL/ad7276_read.v

@@ -0,0 +1,60 @@
+
+module ad7276_read (
+    input  wire       rstn, 
+    input  wire       clk,      // require 81.36MHz
+    // connect to AD7276
+    output reg        ad7276_csn,
+    output reg        ad7276_sclk,
+    input  wire       ad7276_sdata,
+    // 12bit ADC data output
+    output reg        adc_data_en,
+    output reg [11:0] adc_data
+);
+
+
+initial {ad7276_csn, ad7276_sclk} = 2'b11;
+initial {adc_data_en, adc_data} = 0;
+
+reg [ 4:0] cnt = 0;
+reg        data_en = 0;
+reg [11:0] data = 0;
+
+// cnt runs from 0~31 cyclic
+always @ (posedge clk or negedge rstn)
+    if(~rstn)
+        cnt <= 0;
+    else
+        cnt <= cnt + 5'd1;
+
+
+always @ (posedge clk or negedge rstn)
+    if(~rstn) begin
+        {ad7276_csn, ad7276_sclk} <= 2'b11;
+    end else begin
+        if(cnt >= 5'd29 || cnt == 5'd0)
+            {ad7276_csn, ad7276_sclk} <= 2'b11;
+        else
+            {ad7276_csn, ad7276_sclk} <= {1'b0, cnt[0]};
+    end
+
+
+always @ (posedge clk or negedge rstn)
+    if(~rstn) begin
+        data_en <= 1'b0;
+        data <= 0;
+        adc_data_en <= 1'b0;
+        adc_data <= 0;
+    end else begin
+        if(ad7276_csn) begin                     // submit result
+            data_en <= 1'b0;
+            adc_data_en <= data_en;
+            if(data_en) adc_data <= data;
+        end else if(ad7276_sclk) begin           // sample at negedge of ad7276_sclk
+            data_en <= 1'b1;
+            data <= {data[10:0], ad7276_sdata};
+            adc_data_en <= 1'b0;
+        end
+    end
+
+
+endmodule

WangXuan95_FPGA-NFC/RTL/fifo_sync.v

@@ -0,0 +1,73 @@
+
+//--------------------------------------------------------------------------------------------------------
+// Module  : fifo_sync
+// Type    : synthesizable, IP's sub-module
+// Standard: Verilog 2001 (IEEE1364-2001)
+// Function: synchronous fifo
+//--------------------------------------------------------------------------------------------------------
+
+module fifo_sync #(
+    parameter            DW = 8,     // bit width
+    parameter            EA = 10     // 9:depth=512   10:depth=1024   11:depth=2048   12:depth=4096
+) (
+    input  wire          rstn,
+    input  wire          clk,
+    // input interface
+    output wire          i_rdy,
+    input  wire          i_en,
+    input  wire [DW-1:0] i_data,
+    // output interface
+    input  wire          o_rdy,
+    output reg           o_en,
+    output reg  [DW-1:0] o_data
+);
+
+
+
+reg  [DW-1:0] buffer [ ((1<<EA)-1) : 0 ];
+
+localparam [EA:0] A_ZERO = {{EA{1'b0}}, 1'b0};
+localparam [EA:0] A_ONE  = {{EA{1'b0}}, 1'b1};
+
+reg  [EA:0] wptr      = A_ZERO;
+reg  [EA:0] wptr_d1   = A_ZERO;
+reg  [EA:0] wptr_d2   = A_ZERO;
+reg  [EA:0] rptr      = A_ZERO;
+wire [EA:0] rptr_next = (o_en & o_rdy) ? (rptr+A_ONE) : rptr;
+
+
+
+assign i_rdy = ( wptr != {~rptr[EA], rptr[EA-1:0]} );
+
+always @ (posedge clk or negedge rstn)
+    if (~rstn) begin
+        wptr    <= A_ZERO;
+        wptr_d1 <= A_ZERO;
+        wptr_d2 <= A_ZERO;
+    end else begin
+        if (i_en & i_rdy)
+            wptr <= wptr + A_ONE;
+        wptr_d1 <= wptr;
+        wptr_d2 <= wptr_d1;
+    end
+
+always @ (posedge clk)
+    if (i_en & i_rdy)
+        buffer[wptr[EA-1:0]] <= i_data;
+
+
+
+always @ (posedge clk or negedge rstn)
+    if (~rstn) begin
+        rptr <= A_ZERO;
+        o_en <= 1'b0;
+    end else begin
+        rptr <= rptr_next;
+        o_en <= (rptr_next != wptr_d2);
+    end
+
+always @ (posedge clk)
+    o_data <= buffer[rptr_next[EA-1:0]];
+
+
+endmodule

WangXuan95_FPGA-NFC/RTL/fpga_top.v

@@ -0,0 +1,60 @@
+
+module fpga_top (
+
+    input  wire        rstn_btn,        // press button to reset, pressed=0, unpressed=1
+    input  wire        clk50m,          // a 50MHz Crystal oscillator
+    
+    // AD7276 ADC SPI interface
+    output wire        ad7276_csn,      // connect to AD7276's CSN   (NFC_Breakboard's AD7276_CSN)
+    output wire        ad7276_sclk,     // connect to AD7276's SCLK  (NFC_Breakboard's AD7276_SCLK)
+    input  wire        ad7276_sdata,    // connect to AD7276's SDATA (NFC_Breakboard's AD7276_SDATA)
+    
+    // NFC carrier generation signal
+    output wire        carrier_out,     // connect to FDV301N(N-MOSFET)'s gate （栅极）  (NFC_Breakboard's CARRIER_OUT)
+    
+    // connect to Host-PC (typically via a USB-to-UART chip on FPGA board, such as FT232, CP2102 or CH340)
+    input  wire        uart_rx,         // connect to USB-to-UART chip's UART-TX
+    output wire        uart_tx,         // connect to USB-to-UART chip's UART-RX
+    
+    // connect to on-board LED's (optional)
+    output wire        led0,            // led0=1 indicates PLL is normally run
+    output wire        led1,            // led1=1 indicates carrier is on
+    output wire        led2             // led2=1 indicates PCD-to-PICC communication is done, and PCD is waiting for PICC-to-PCD
+);
+
+
+//-------------------------------------------------------------------------------------------------------------------------------------
+// The NFC controller core needs a 81.36MHz clock, this PLL module is to convert clk50m to clk81m36
+// This PLL module is only available on Altera Cyclone IV E.
+// If you use other FPGA families, please use their compatible primitives or IP-cores to generate clk81m36
+//-------------------------------------------------------------------------------------------------------------------------------------
+wire [3:0] subwire0;
+wire       clk81m36;
+wire       clk_locked;
+altpll pll_i ( .areset (~rstn_btn), .inclk ({1'b0,clk50m}), .clk ({subwire0,clk81m36}), .locked (clk_locked), .activeclock (), .clkbad (), .clkena ({6{1'b1}}), .clkloss (), .clkswitch (1'b0), .configupdate (1'b0), .enable0 (), .enable1 (), .extclk (), .extclkena ({4{1'b1}}), .fbin (1'b1), .fbmimicbidir (), .fbout (), .fref (), .icdrclk (), .pfdena (1'b1), .phasecounterselect ({4{1'b1}}), .phasedone (), .phasestep (1'b1), .phaseupdown (1'b1), .pllena (1'b1), .scanaclr (1'b0), .scanclk (1'b0), .scanclkena (1'b1), .scandata (1'b0), .scandataout (), .scandone (), .scanread (1'b0), .scanwrite (1'b0), .sclkout0 (), .sclkout1 (), .vcooverrange (), .vcounderrange ()); defparam pll_i.bandwidth_type = "AUTO", pll_i.clk0_divide_by = 625, pll_i.clk0_duty_cycle = 50, pll_i.clk0_multiply_by = 1017, pll_i.clk0_phase_shift = "0", pll_i.compensate_clock = "CLK0", pll_i.inclk0_input_frequency = 20000, pll_i.intended_device_family = "Cyclone IV E", pll_i.lpm_hint = "CBX_MODULE_PREFIX=pll", pll_i.lpm_type = "altpll", pll_i.operation_mode = "NORMAL", pll_i.pll_type = "AUTO", pll_i.port_activeclock = "PORT_UNUSED", pll_i.port_areset = "PORT_USED", pll_i.port_clkbad0 = "PORT_UNUSED", pll_i.port_clkbad1 = "PORT_UNUSED", pll_i.port_clkloss = "PORT_UNUSED", pll_i.port_clkswitch = "PORT_UNUSED", pll_i.port_configupdate = "PORT_UNUSED", pll_i.port_fbin = "PORT_UNUSED", pll_i.port_inclk0 = "PORT_USED", pll_i.port_inclk1 = "PORT_UNUSED", pll_i.port_locked = "PORT_USED", pll_i.port_pfdena = "PORT_UNUSED", pll_i.port_phasecounterselect = "PORT_UNUSED", pll_i.port_phasedone = "PORT_UNUSED", pll_i.port_phasestep = "PORT_UNUSED", pll_i.port_phaseupdown = "PORT_UNUSED", pll_i.port_pllena = "PORT_UNUSED", pll_i.port_scanaclr = "PORT_UNUSED", pll_i.port_scanclk = "PORT_UNUSED", pll_i.port_scanclkena = "PORT_UNUSED", pll_i.port_scandata = "PORT_UNUSED", pll_i.port_scandataout = "PORT_UNUSED", pll_i.port_scandone = "PORT_UNUSED", pll_i.port_scanread = "PORT_UNUSED", pll_i.port_scanwrite = "PORT_UNUSED", pll_i.port_clk0 = "PORT_USED", pll_i.port_clk1 = "PORT_UNUSED", pll_i.port_clk2 = "PORT_UNUSED", pll_i.port_clk3 = "PORT_UNUSED", pll_i.port_clk4 = "PORT_UNUSED", pll_i.port_clk5 = "PORT_UNUSED", pll_i.port_clkena0 = "PORT_UNUSED", pll_i.port_clkena1 = "PORT_UNUSED", pll_i.port_clkena2 = "PORT_UNUSED", pll_i.port_clkena3 = "PORT_UNUSED", pll_i.port_clkena4 = "PORT_UNUSED", pll_i.port_clkena5 = "PORT_UNUSED", pll_i.port_extclk0 = "PORT_UNUSED", pll_i.port_extclk1 = "PORT_UNUSED", pll_i.port_extclk2 = "PORT_UNUSED", pll_i.port_extclk3 = "PORT_UNUSED", pll_i.self_reset_on_loss_lock = "OFF", pll_i.width_clock = 5;
+
+
+//-------------------------------------------------------------------------------------------------------------------------------------
+// UART-to-NFCA system
+//-------------------------------------------------------------------------------------------------------------------------------------
+uart2nfca_system_top u_uart2nfca_system (
+    .rstn          ( clk_locked        ),
+    .clk           ( clk81m36          ),
+    .ad7276_csn    ( ad7276_csn        ),
+    .ad7276_sclk   ( ad7276_sclk       ),
+    .ad7276_sdata  ( ad7276_sdata      ),
+    .carrier_out   ( carrier_out       ),
+    .uart_rx       ( uart_rx           ),
+    .uart_tx       ( uart_tx           ),
+    .rx_on         ( led2              )
+);
+
+
+//-------------------------------------------------------------------------------------------------------------------------------------
+// LEDs' assignment
+//-------------------------------------------------------------------------------------------------------------------------------------
+assign led0 = clk_locked;
+assign led1 = carrier_out;
+
+
+endmodule

WangXuan95_FPGA-NFC/RTL/nfca_controller/nfca_controller.v

@@ -0,0 +1,119 @@
+
+//--------------------------------------------------------------------------------------------------------
+// Module  : nfca_controller
+// Type    : synthesizable, IP's top
+// Standard: Verilog 2001 (IEEE1364-2001)
+// Function: NFC-A (ISO14443A) controller
+//--------------------------------------------------------------------------------------------------------
+
+module nfca_controller (
+    input  wire       rstn,           // 0:reset, 1:work
+    input  wire       clk,            // require 81.36MHz,  (81.36 = 13.56*6)
+    // TX byte stream interface for NFC PCD-to-PICC (axis sink liked)
+    input  wire       tx_tvalid,
+    output wire       tx_tready,
+    input  wire [7:0] tx_tdata,
+    input  wire [3:0] tx_tdatab,      // indicate how many bits are valid in the last byte. range=[1,8]. for the last byte of bit-oriented frame
+    input  wire       tx_tlast,
+    // RX status
+    output wire       rx_on,
+    // RX byte stream interface for NFC PICC-to-PCD (axis source liked, without tready)
+    output wire       rx_tvalid,
+    output wire [7:0] rx_tdata,
+    output wire [3:0] rx_tdatab,
+    output wire       rx_tend,
+    output wire       rx_terr,
+    // 12bit ADC data interface, the ADC is to sample the envelope detection signal of RFID RX. Required sample rate = 2.5425Msa/s = 81.36/32, that is, transmit 12bit on adc_data every 32 clk cycles.
+    input  wire       adc_data_en,    // After starting to work, adc_data_en=1 pulse needs to be generated every 32 clk cycles, and adc_data_en=0 in the rest of the cycles. adc_data_en=1 means adc_data is valid.
+    input  wire[11:0] adc_data,       // adc_data should valid when adc_data_en=1
+    // RFID carrier output, connect to a NMOS transistor to drive the antenna coil
+    output wire       carrier_out
+);
+
+wire [2:0] remainb;
+
+wire       tx_req;
+wire       tx_en;
+wire       tx_bit;
+
+wire       rx_ask_en;
+wire       rx_ask;
+
+// RX bit parsed (105.9375 kbps base-band)
+wire       rx_bit_en;     // when rx_bit_en=1 pulses, a received bit is valid on rx_bit
+wire       rx_bit;        // exclude S (start of communication) and E (end of communication)
+wire       rx_end;        // end of a communication pulse, because of detect E, or detect a bit collision, or detect an error.
+wire       rx_end_col;    // indicate a bit collision, only valid when rx_end=1
+wire       rx_end_err;    // indicate an unknown error, such a PICC (card) do not match ISO14443A, or noise, only valid when rx_end=1
+
+
+nfca_tx_frame u_nfca_tx_frame (
+    .rstn          ( rstn              ),
+    .clk           ( clk               ),
+    .tx_tvalid     ( tx_tvalid         ),
+    .tx_tready     ( tx_tready         ),
+    .tx_tdata      ( tx_tdata          ),
+    .tx_tdatab     ( tx_tdatab         ),
+    .tx_tlast      ( tx_tlast          ),
+    .tx_req        ( tx_req            ),
+    .tx_en         ( tx_en             ),
+    .tx_bit        ( tx_bit            ),
+    .remainb       ( remainb           )
+);
+
+
+nfca_tx_modulate u_nfca_tx_modulate (
+    .rstn          ( rstn              ),
+    .clk           ( clk               ),
+    .tx_req        ( tx_req            ),
+    .tx_en         ( tx_en             ),
+    .tx_bit        ( tx_bit            ),
+    .carrier_out   ( carrier_out       ),
+    .rx_on         ( rx_on             )
+);
+
+
+nfca_rx_dsp u_nfca_rx_dsp (
+    .rstn          ( rstn              ),
+    .clk           ( clk               ),
+    .adc_data_en   ( adc_data_en       ),
+    .adc_data      ( adc_data          ),
+    .rx_ask_en     ( rx_ask_en         ),
+    .rx_ask        ( rx_ask            ),
+    .rx_lpf_data   (                   ),
+    .rx_raw_data   (                   )
+);
+
+
+nfca_rx_tobits u_nfca_rx_tobits (
+    .rstn          ( rstn              ),
+    .clk           ( clk               ),
+    .rx_on         ( rx_on             ),
+    .rx_ask_en     ( rx_ask_en         ),
+    .rx_ask        ( rx_ask            ),
+    .rx_bit_en     ( rx_bit_en         ),
+    .rx_bit        ( rx_bit            ),
+    .rx_end        ( rx_end            ),
+    .rx_end_col    ( rx_end_col        ),
+    .rx_end_err    ( rx_end_err        )
+);
+
+
+nfca_rx_tobytes u_nfca_rx_tobytes (
+    .rstn          ( rstn              ),
+    .clk           ( clk               ),
+    .rx_on         ( rx_on             ),
+    .remainb       ( remainb           ),
+    .rx_bit_en     ( rx_bit_en         ),
+    .rx_bit        ( rx_bit            ),
+    .rx_end        ( rx_end            ),
+    .rx_end_col    ( rx_end_col        ),
+    .rx_end_err    ( rx_end_err        ),
+    .rx_tvalid     ( rx_tvalid         ),
+    .rx_tdata      ( rx_tdata          ),
+    .rx_tdatab     ( rx_tdatab         ),
+    .rx_tend       ( rx_tend           ),
+    .rx_terr       ( rx_terr           )
+);
+
+endmodule

WangXuan95_FPGA-NFC/RTL/nfca_controller/nfca_rx_dsp.v

@@ -0,0 +1,88 @@
+
+//--------------------------------------------------------------------------------------------------------
+// Module  : nfca_rx_dsp
+// Type    : synthesizable, IP's sub module
+// Standard: Verilog 2001 (IEEE1364-2001)
+// Function: called by nfca_controller
+//--------------------------------------------------------------------------------------------------------
+
+module nfca_rx_dsp (
+    input  wire       rstn,              // 0:reset, 1:work
+    input  wire       clk,               // require 81.36MHz
+    // 12bit ADC data input (2.5425 Msa/s)
+    input  wire       adc_data_en,
+    input  wire[11:0] adc_data,
+    // RX DSP result (2.5425 Mbps)
+    output reg        rx_ask_en,         // rx_ask_en=1 will pulses every 32 clk cycles. When rx_ask_en=1, rx_ask, rx_lpf_data and rx_raw_data is valid.
+    output reg        rx_ask,            // ASK demodulated signal. 1 means detected rx_raw_data is significantly less than rx_lpf_data, that is, the PICC (TAG) is sending a ASK signal.
+    output reg [11:0] rx_lpf_data,       // low-frequency baseline, only for debug
+    output reg [11:0] rx_raw_data        // rx_raw_data, which is to compare with rx_lpf_data, only for debug
+);
+
+
+initial {rx_ask_en, rx_ask, rx_lpf_data, rx_raw_data} = 0;
+
+localparam       N           = 21;
+localparam [5:0] SORT_CYCLES = 6'd24;
+
+reg [ 5:0] ccnt = 0;
+reg [ 5:0] acnt = 0;
+reg [11:0] array  [0:(N-1)];
+reg [11:0] sorted [0:(N-1)];
+
+wire [11:0] lpf = sorted[12];              // sorted 是 排序后的过去21个样点，lpf 取其中第12个（中间偏大一点的一个），可以将 lpf 看作中值滤波的结果。
+wire [11:0] raw = array [10];              // array  是 未排序的过去21个样点，raw 取其中第10个（最中间那个），即 raw 是观察窗内最中心的数据。
+
+integer ii;
+
+// ASK 解调的 DSP 算法的思路： 用中值滤波获取 ADC 数据的基线(baseline)， ADC 数据小于 baseline 一定的值，认为检测到 ASK 调制的 '1'
+// 中值滤波： 用 array 存储过去 21 个 ADC 样点，每获取一个新样点，就用把 array 赋值给 sorted，并用排序网络（冒泡排序）花费 22 个周期对 sorted 排序。最终得到的 sorted 的中间数就是中值滤波结果。
+always @ (posedge clk or negedge rstn)
+    if(~rstn) begin
+        rx_ask_en <= 1'b0;
+        {rx_ask, rx_lpf_data, rx_raw_data} <= 0;
+        ccnt <= 0;
+        acnt <= 0;
+        for (ii=0; ii<N; ii=ii+1) begin
+            array[ii]  <= 0;
+            sorted[ii] <= 0;
+        end
+    end else begin
+        rx_ask_en <= 1'b0;
+        if(adc_data_en) begin
+            ccnt <= 0;
+            array[0] <= adc_data;
+            for(ii=0; ii<N-1; ii=ii+1) array[ii+1] <= array[ii];
+        end else if(ccnt <= 6'd0) begin 
+            ccnt <= ccnt + 6'd1;
+            for(ii=0; ii<N; ii=ii+1) sorted[ii] <= array[ii];
+        end else if(ccnt <= SORT_CYCLES) begin                        // 花费 SORT_CYCLES 周期运行冒泡排序网络（实际上考虑到 array len=N，只要 N+1 个周期就够，更多无害）
+            ccnt <= ccnt + 6'd1;
+            if(ccnt[0]) begin
+                for(ii=0; ii<N-1; ii=ii+2) begin                      // 排序网络在 ccnt=奇数 时的行为： 0和1尝试交换，2和3尝试交换，4和5尝试交换，……以此类推
+                    if( sorted[ii] > sorted[ii+1] ) begin
+                        sorted[ii] <= sorted[ii+1];
+                        sorted[ii+1] <= sorted[ii];
+                    end
+                end
+            end else begin
+                for(ii=1; ii<N  ; ii=ii+2) begin                      // 排序网络在 ccnt=偶数 时的行为： 1和2尝试交换，3和4尝试交换，5和6尝试交换，……以此类推
+                    if( sorted[ii] > sorted[ii+1] ) begin
+                        sorted[ii] <= sorted[ii+1];
+                        sorted[ii+1] <= sorted[ii];
+                    end
+                end
+            end
+        end else if(ccnt == SORT_CYCLES + 6'd1) begin
+            ccnt <= ccnt + 6'd1;
+            if(acnt[5]) begin
+                rx_ask_en <= 1'b1;
+                rx_ask <= ( lpf - {7'h0,lpf[11:7]} - {8'h0,lpf[11:8]} > raw );               // 若 raw < 0.988*lpf , 认为 PICC 在发送 ASK 。
+                rx_lpf_data <= lpf;
+                rx_raw_data <= raw;
+            end else
+                acnt <= acnt + 6'd1;
+        end
+    end
+
+endmodule

WangXuan95_FPGA-NFC/RTL/nfca_controller/nfca_rx_tobits.v

@@ -0,0 +1,115 @@
+
+//--------------------------------------------------------------------------------------------------------
+// Module  : nfca_rx_tobits
+// Type    : synthesizable, IP's sub module
+// Standard: Verilog 2001 (IEEE1364-2001)
+// Function: called by nfca_controller
+//--------------------------------------------------------------------------------------------------------
+
+module nfca_rx_tobits (
+    input  wire       rstn,          // 0:reset, 1:work
+    input  wire       clk,           // require 81.36MHz
+    // RX on/off control
+    input  wire       rx_on,         // 0:off, 1:on
+    // RX DSP result input  (2.5425 Mbps)
+    input  wire       rx_ask_en,
+    input  wire       rx_ask,
+    // RX bit parsed (105.9375 kbps base-band)
+    output reg        rx_bit_en,     // when rx_bit_en=1 pulses, a received bit is valid on rx_bit
+    output reg        rx_bit,        // exclude S (start of communication) and E (end of communication)
+    output reg        rx_end,        // end of a communication pulse, because of detect E, or detect a bit collision, or detect an error.
+    output reg        rx_end_col,    // indicate a bit collision, only valid when rx_end=1
+    output reg        rx_end_err     // indicate an unknown error, such a PICC (card) do not match ISO14443A, or noise, or PICC's frame is too long. Only valid when rx_end=1
+);
+
+initial {rx_bit_en, rx_bit, rx_end, rx_end_err, rx_end_col} = 0;
+
+
+reg [ 3:0] detect_zeros = 0;
+reg [ 3:0] detect_ones = 0;
+reg [11:0] shift0 = 0;
+reg [11:0] shift1 = 0;
+reg [11:0] shift2 = 0;
+reg [11:0] shift3 = 0;
+reg [ 4:0] cnt = 0;
+
+localparam [1:0] IDLE  = 2'd0,
+                 PARSE = 2'd1,
+                 STOP  = 2'd2;
+
+reg        [1:0] status = IDLE;
+
+reg  [3:0] sum [0:3];                 // not real register
+
+integer ii, jj;                       // not real register, just loop variable
+
+always @ (posedge clk or negedge rstn)
+    if(~rstn) begin
+        detect_zeros <= 0;
+        detect_ones <= 0;
+        {shift3, shift2, shift1, shift0} <= 0;
+    end else begin
+        if(~rx_on) begin
+            detect_zeros <= 0;
+            detect_ones <= 0;
+            {shift3, shift2, shift1, shift0} <= 0;
+        end else if(rx_ask_en) begin
+            for(ii=0; ii<4; ii=ii+1) sum[ii] = 0;
+            for(ii=0; ii<12; ii=ii+1) begin
+                sum[0] = sum[0] + {3'h0, shift0[ii]};
+                sum[1] = sum[1] + {3'h0, shift1[ii]};
+                sum[2] = sum[2] + {3'h0, shift2[ii]};
+                sum[3] = sum[3] + {3'h0, shift3[ii]};
+            end
+            for(jj=0; jj<4; jj=jj+1) begin
+                detect_ones[jj]  <= sum[jj] >= 4'd3;
+                detect_zeros[jj] <= sum[jj] <= 4'd1;
+            end
+            {shift3, shift2, shift1, shift0} <= {shift3[10:0], shift2, shift1, shift0, rx_ask};
+        end
+    end
+
+
+always @ (posedge clk or negedge rstn)
+    if(~rstn) begin
+        {rx_bit_en, rx_bit, rx_end, rx_end_err, rx_end_col} <= 0;
+        cnt <= 0;
+        status <= IDLE;
+    end else begin
+        {rx_bit_en, rx_bit, rx_end, rx_end_err, rx_end_col} <= 0;
+        if(~rx_on) begin
+            cnt <= 0;
+            status <= IDLE;
+        end else if(rx_ask_en) begin
+            if(status == IDLE) begin
+                cnt <= 0;
+                if(detect_ones == 4'b0010 && detect_zeros == 4'b1101)
+                    status <= PARSE;
+            end else if(status == PARSE) begin
+                if(cnt < 5'd23) begin
+                    cnt <= cnt + 5'd1;
+                end else begin
+                    cnt <= 0;
+                    if(~(&(detect_ones^detect_zeros))) begin               // noise
+                        {rx_end, rx_end_err} <= 2'b11;
+                        status <= STOP;
+                    end else if(detect_ones[1:0] == 2'b00) begin           // end of communication
+                        rx_end <= 1'b1;
+                        status <= STOP;
+                    end else if(detect_ones[1:0] == 2'b11) begin           // collision
+                        {rx_end, rx_end_col} <= 2'b11;
+                        status <= STOP;
+                    end else if(detect_ones[1:0] == 2'b10) begin           // logic '1'
+                        {rx_bit_en, rx_bit} <= 2'b11;
+                    end else if(detect_ones[1:0] == 2'b01) begin           // logic '0'
+                        rx_bit_en <= 1'b1;
+                    end else begin                                         // undefined error
+                        {rx_end, rx_end_err} <= 2'b11;
+                        status <= STOP;
+                    end
+                end
+            end
+        end
+    end
+
+endmodule

WangXuan95_FPGA-NFC/RTL/nfca_controller/nfca_rx_tobytes.v

@@ -0,0 +1,86 @@
+
+//--------------------------------------------------------------------------------------------------------
+// Module  : nfca_rx_tobytes
+// Type    : synthesizable, IP's sub module
+// Standard: Verilog 2001 (IEEE1364-2001)
+// Function: called by nfca_controller
+//--------------------------------------------------------------------------------------------------------
+
+module nfca_rx_tobytes (
+    input  wire       rstn,          // 0:reset, 1:work
+    input  wire       clk,           // require 81.36MHz
+    // RX on/off control
+    input  wire       rx_on,         // 0:off, 1:on
+    // indicate how many bits remain for an incomplete byte for PICC to send
+    input  wire [2:0] remainb,
+    // RX bit parsed (105.9375 kbps base-band)
+    input  wire       rx_bit_en,     // when rx_bit_en=1 pulses, a received bit is valid on rx_bit
+    input  wire       rx_bit,        // exclude S (start of communication) and E (end of communication)
+    input  wire       rx_end,        // end of a communication pulse, because of detect E, or detect a bit collision, or detect an error.
+    input  wire       rx_end_col,    // indicate a bit collision, only valid when rx_end=1
+    input  wire       rx_end_err,    // indicate an unknown error, such a PICC (card) do not match ISO14443A, or noise, or PICC's frame is too long. Only valid when rx_end=1
+    // RX byte parsed
+    output reg        rx_tvalid,
+    output reg  [7:0] rx_tdata,
+    output reg  [3:0] rx_tdatab,
+    output reg        rx_tend,
+    output reg        rx_terr
+);
+
+initial {rx_tvalid, rx_tdata, rx_tend, rx_tdatab, rx_terr} = 0;
+
+reg [3:0] cnt = 0;
+reg [7:0] byte_saved = 0;
+
+localparam [2:0] IDLE   = 3'd0,
+                 START  = 3'd1,
+                 PARSE  = 3'd2,
+                 CSTOP  = 3'd3,
+                 STOP   = 3'd4;
+reg        [2:0] status = IDLE;
+
+wire      error_parity = (status==PARSE) & ~(^{rx_bit,byte_saved});
+
+always @ (posedge clk or negedge rstn)
+    if(~rstn) begin
+        {rx_tvalid, rx_tdata, rx_tdatab, rx_tend, rx_terr} <= 0;
+        cnt <= 0;
+        byte_saved <= 0;
+        status <= IDLE;
+    end else begin
+        {rx_tvalid, rx_tdata, rx_tdatab, rx_tend, rx_terr} <= 0;
+        if(status == CSTOP) begin
+            {rx_tvalid, rx_tdata, rx_tdatab, rx_tend, rx_terr} <= {1'b1,      8'h00, 4'd0, 1'b1, 1'b0};   // end with collision (step2)
+            status <= STOP;
+        end else if(~rx_on) begin
+            cnt <= {1'b0, remainb};
+            byte_saved <= 0;
+            status <= IDLE;
+            if(status == START || status == PARSE)
+                {rx_tvalid, rx_tdata, rx_tdatab, rx_tend, rx_terr}     <= {1'b1, byte_saved, cnt, 1'b1, 1'b1};
+        end else if(status == IDLE) begin
+            status <= START;
+        end else if(status != STOP) begin
+            if(rx_bit_en) begin
+                if(cnt < 4'd8) begin
+                    cnt <= cnt + 4'd1;
+                    byte_saved[cnt] <= rx_bit;
+                end else begin
+                    {rx_tvalid, rx_tdata, rx_tdatab, rx_tend, rx_terr} <= {1'b1, byte_saved,4'd8, error_parity, error_parity};
+                    cnt <= 0;
+                    byte_saved <= 0;
+                    status <= error_parity ? STOP : PARSE;
+                end
+            end else if(rx_end) begin
+                status <= rx_end_col ? CSTOP : STOP;
+                if(rx_end_col)
+                    {rx_tvalid, rx_tdata, rx_tdatab, rx_tend, rx_terr} <= {1'b1, byte_saved, cnt, 1'b0, 1'b0};   // end with collision
+                else if(rx_end_err | (|cnt) )
+                    {rx_tvalid, rx_tdata, rx_tdatab, rx_tend, rx_terr} <= {1'b1, byte_saved, cnt, 1'b1, 1'b1};   // end with error
+                else
+                    {rx_tvalid, rx_tdata, rx_tdatab, rx_tend, rx_terr} <= {1'b1,      8'h00,4'd0, 1'b1, 1'b0};   // end normally
+            end
+        end
+    end
+
+endmodule

WangXuan95_FPGA-NFC/RTL/nfca_controller/nfca_tx_frame.v

@@ -0,0 +1,142 @@
+
+//--------------------------------------------------------------------------------------------------------
+// Module  : nfca_tx_frame
+// Type    : synthesizable, IP's sub module
+// Standard: Verilog 2001 (IEEE1364-2001)
+// Function: called by nfca_controller
+//--------------------------------------------------------------------------------------------------------
+
+module nfca_tx_frame (
+    input  wire       rstn,           // 0:reset, 1:work
+    input  wire       clk,            // require 81.36MHz
+    // TX byte stream interface (axis sink liked)
+    input  wire       tx_tvalid,
+    output reg        tx_tready,
+    input  wire [7:0] tx_tdata,
+    input  wire [3:0] tx_tdatab,      // indicate how many bits are valid in the last byte. range=[1,8]. for the last byte of bit-oriented frame
+    input  wire       tx_tlast,
+    // tx bit modulate interface
+    input  wire       tx_req,
+    output reg        tx_en,
+    output reg        tx_bit,
+    // indicate how many bits remain for an incomplete byte for PICC to send, for nfca_rx_tobytes to reconstruct the bytes
+    output reg  [2:0] remainb
+);
+
+
+function  [15:0] CRC16;
+    input [15:0] crc;
+    input [ 7:0] inbyte;
+//function automatic logic [15:0] CRC16(input logic [15:0] crc, input logic [7:0] inbyte);
+    reg   [ 7:0] tmp;
+begin
+    tmp = inbyte ^ crc[7:0];
+    tmp = tmp ^ {tmp[3:0], 4'h0};
+    CRC16 = ( {8'h0, crc[15:8]} ^ {tmp, 8'h0} ^ {5'h0, tmp, 3'h0} ^ {12'h0, tmp[7:4]} );
+end
+endfunction
+
+
+initial tx_tready = 1'b0;
+initial {tx_en, tx_bit} = 0;
+initial remainb = 0;
+
+reg [ 7:0] buffer [0:4095];   // will synthesis to BRAM
+reg [ 7:0] rdata = 0;
+reg [11:0] wptr = 0;
+reg [11:0] rptr = 0;
+reg [ 3:0] lastb = 0;
+reg [17:0] txshift = 0;
+reg [ 4:0] txcount = 0;
+reg        end_of = 1'b0;
+reg        has_crc = 1'b0;
+reg [15:0] crc = 16'h6363;
+reg        incomplete = 1'b0;
+
+wire short_frame = (rdata == 8'h26 || rdata == 8'h52 || rdata == 8'h35 || rdata[7:4] == 4'h4 || rdata[7:3] == 5'h0F);
+
+
+always @ (posedge clk)
+    rdata <= buffer[rptr];
+
+
+always @ (posedge clk)
+    if(tx_tready & tx_tvalid)
+        buffer[wptr] <= tx_tdata;
+
+
+always @ (posedge clk or negedge rstn)
+    if(~rstn) begin
+        tx_tready <= 0;
+        {tx_bit, tx_en} <= 0;
+        {wptr, rptr} <= 0;
+        lastb <= 0;
+        txshift <= 0;
+        txcount <= 0;
+        end_of <= 1'b0;
+        has_crc <= 1'b0;
+        crc <= 16'h6363;
+        incomplete <= 1'b0;
+        remainb <= 0;
+    end else begin
+        if(tx_tready) begin
+            if(tx_tvalid) begin
+                crc <= CRC16(crc, tx_tdata);
+                if (wptr != 12'hFFF) wptr <= wptr + 12'd1;
+                lastb <= tx_tdatab==4'd0 ? 4'd1 : tx_tdatab>4'd8 ? 4'd8 : tx_tdatab;
+                if(tx_tlast) begin                   // end of a frame input
+                    if (wptr != 12'hFFF) begin       // not overflow
+                        txshift <= 0;                //
+                        txcount <= 5'd1;             //     send the S bit (start of communication)
+                        tx_tready <= 1'b0;           //     start to send a frame
+                    end else begin                   // overflow!
+                        wptr <= 0;                   //     reset wptr
+                        crc <= 16'h6363;             //     reset CRC
+                    end
+                end
+            end
+        end else if(txcount != 0) begin
+            if(tx_req) begin
+                {txshift, tx_bit, tx_en} <= {1'b0, txshift, 1'b1};
+                txcount <= txcount - 5'd1;
+            end
+        end else if(rptr == wptr) begin
+            if(has_crc) begin
+                txshift <= {~(^crc[15:8]), crc[15:8], ~(^crc[7:0]), crc[7:0]};     // append CRC (16bit + 2bit parity) 
+                txcount <= 5'd18;
+            end else if(end_of) begin
+                txshift <= 0;
+                txcount <= 5'd1;              //     send the E bit (end of communication)
+                end_of <= 1'b0;
+                remainb <= incomplete ? lastb[2:0] : 3'd0;
+            end else if(tx_req) begin
+                tx_tready <= 1'b1;
+                {tx_bit, tx_en} <= 0;
+                {wptr, rptr} <= 0;
+            end
+            has_crc <= 1'b0;
+            crc <= 16'h6363;
+        end else begin
+            incomplete <= 1'b0;
+            end_of <= 1'b1;
+            rptr <= rptr + 12'd1;
+            txshift <= {9'd0, ~(^rdata), rdata};
+            if         (rptr == 12'h0) begin                                                                           // the 1st byte
+                has_crc <= ~(rdata == 8'h93 || rdata == 8'h95 || rdata == 8'h97 || short_frame);
+                txcount <= short_frame ? 4'd7 : 4'd9;
+            end else if(rptr == 12'h1) begin                                                                           // the 2nd byte
+                has_crc <= has_crc | (rdata == 8'h70);
+                txcount <= 4'd9;
+            end else if(rptr+12'd1 < wptr) begin                                                                       // inner bytes
+                txcount <= 4'd9;
+            end else if(lastb < 4'd8) begin                                                                            // last byte (incomplete)
+                incomplete <= 1'b1;
+                has_crc <= 1'b0;
+                txcount <= {1'h0,lastb};
+            end else begin                                                                                             // last byte (complete)
+                txcount <= 5'd9;
+            end
+        end
+    end
+
+endmodule 

WangXuan95_FPGA-NFC/RTL/nfca_controller/nfca_tx_modulate.v

@@ -0,0 +1,117 @@
+
+//--------------------------------------------------------------------------------------------------------
+// Module  : nfca_tx_modulate
+// Type    : synthesizable, IP's sub module
+// Standard: Verilog 2001 (IEEE1364-2001)
+// Function: called by nfca_controller
+//--------------------------------------------------------------------------------------------------------
+
+module nfca_tx_modulate (
+    input  wire       rstn,       // 0:reset, 1:work
+    input  wire       clk,        // require 81.36MHz
+    // tx bit modulate interface
+    output reg        tx_req,
+    input  wire       tx_en,
+    input  wire       tx_bit,
+    // RFID carrier output, connect to a NMOS transistor to drive the antenna coil
+    output reg        carrier_out,
+    // 1:in RX window,  0:out of RX window
+    output reg        rx_on
+);
+
+
+localparam    CARRIER_SETUP = 2048;
+localparam    CARRIER_HOLD  = 131072;
+
+initial tx_req  = 1'b0;
+initial carrier_out = 1'b0;
+initial rx_on = 1'b0;
+
+reg [ 1:0] clkcnt = 2'd0;
+reg [ 7:0] ccnt = 8'd0;
+reg [31:0] wcnt = 32'hFFFFFFFF;
+reg [ 1:0] bdata = 2'd0;            // {1 bits for future, 1 bit for current, 1 bit for past}
+
+
+always @ (posedge clk or negedge rstn)
+    if(~rstn) begin
+        clkcnt <= 2'd0;
+        ccnt <= 8'd0;
+    end else begin
+        if(clkcnt >= 2'd2) begin
+            clkcnt <= 2'd0;
+            ccnt <= ccnt + 8'h01;
+        end else begin
+            clkcnt <= clkcnt + 2'd1;
+        end
+    end
+
+
+always @ (posedge clk or negedge rstn)
+    if(~rstn)
+        tx_req <= 1'b0;
+    else
+        tx_req <= clkcnt == 2'h0 && ccnt == 8'hff && (wcnt == CARRIER_SETUP || wcnt >= CARRIER_SETUP*2 && wcnt <= CARRIER_SETUP*2 + CARRIER_HOLD || wcnt > CARRIER_SETUP*2 + CARRIER_HOLD + 16);
+
+
+always @ (posedge clk or negedge rstn)
+    if(~rstn) begin
+        wcnt <= 32'hFFFFFFFF;
+        bdata <= 2'd0;
+    end else begin
+        if(clkcnt >= 2'd2 && ccnt == 8'hff) begin
+            if         (wcnt <  CARRIER_SETUP) begin
+                wcnt <= wcnt + 1;
+            end else if(wcnt == CARRIER_SETUP) begin
+                if(tx_en) begin
+                    bdata <= {tx_bit, bdata[1]};
+                    //$write("%d", tx_bit);           // only for simulation
+                end else begin
+                    wcnt <= wcnt + 1;
+                    //$write("\n");                   // only for simulation
+                end
+            end else if(wcnt <  CARRIER_SETUP*2) begin
+                wcnt <= wcnt + 1;
+            end else if(wcnt <= CARRIER_SETUP*2 + CARRIER_HOLD) begin
+                if(tx_en) begin
+                    wcnt <= CARRIER_SETUP;
+                    bdata <= {tx_bit, 1'b0};
+                    //$write("%d", tx_bit);           // only for simulation
+                end else
+                    wcnt <= wcnt + 1;
+            end else if(wcnt <= CARRIER_SETUP*2 + CARRIER_HOLD + 16) begin
+                wcnt <= wcnt + 1;
+            end else if(tx_en) begin
+                wcnt <= 0;
+                bdata <= {tx_bit, 1'b0};
+                //$write("%d", tx_bit);               // only for simulation
+            end
+        end
+    end
+
+
+always @ (posedge clk or negedge rstn)
+    if(~rstn) begin
+        carrier_out <= 1'b0;
+    end else begin
+        if(wcnt == CARRIER_SETUP && ~ccnt[6]) begin
+            if(ccnt[7])
+                carrier_out <= ~ccnt[0] && bdata[1] == 1'b0;
+            else
+                carrier_out <= ~ccnt[0] && bdata[1:0] != 2'b00;
+        end else if(wcnt <= CARRIER_SETUP*2 + CARRIER_HOLD) begin
+            carrier_out <= ~ccnt[0];
+        end else begin
+            carrier_out <= 1'b0;
+        end
+    end
+
+
+always @ (posedge clk or negedge rstn)
+    if(~rstn)
+        rx_on <= 1'b0;
+    else
+        rx_on <= wcnt >= CARRIER_SETUP + 7 && wcnt < CARRIER_SETUP*2 - 128;
+
+endmodule
+

WangXuan95_FPGA-NFC/RTL/uart2nfca_system_top.v

@@ -0,0 +1,145 @@
+
+module uart2nfca_system_top (
+    input  wire       rstn,           // 0:reset, 1:work
+    input  wire       clk,            // require 81.36MHz,  (81.36 = 13.56*6)
+    // connect to AD7276, which is a 12bit 3Msps ADC to sample the envelope detection result of RFID RX. Actually work at 2.5456 Msa/s in this system
+    output wire       ad7276_csn,
+    output wire       ad7276_sclk,
+    input  wire       ad7276_sdata,
+    // RFID carrier output, connect to a NMOS transistor to drive the antenna coil
+    output wire       carrier_out,
+    // UART interface, typically connect to host-PC or MCU, and run NFC user applications on host-PC or MCU.
+    input  wire       uart_rx,
+    output wire       uart_tx,
+    // for debug external trigger (optional)
+    output wire       rx_on
+);
+
+wire       adc_data_en;
+wire[11:0] adc_data;
+
+wire       uart_rx_byte_en;
+wire [7:0] uart_rx_byte;
+
+wire       tvalid;
+wire [7:0] tdata;
+wire [3:0] tdatab;
+wire       tlast;
+
+wire       tx_tvalid;
+wire       tx_tready;
+wire [7:0] tx_tdata;
+wire [3:0] tx_tdatab;
+wire       tx_tlast;
+
+wire       rx_tvalid;
+wire [7:0] rx_tdata;
+wire [3:0] rx_tdatab;
+wire       rx_tend;
+wire       rx_terr;
+
+
+ad7276_read u_ad7276_read (
+    .rstn             ( rstn                            ),
+    .clk              ( clk                             ),
+    .ad7276_csn       ( ad7276_csn                      ),
+    .ad7276_sclk      ( ad7276_sclk                     ),
+    .ad7276_sdata     ( ad7276_sdata                    ),
+    .adc_data_en      ( adc_data_en                     ),
+    .adc_data         ( adc_data                        )
+);
+
+
+uart_rx #(
+    .CLK_FREQ         ( 81360000                        ),  // 81.36 MHz
+    .BAUD_RATE        ( 9600                            ),
+    .PARITY           ( "NONE"                          ),
+    .FIFO_EA          ( 0                               )
+) u_uart_rx (
+    .rstn             ( rstn                            ),
+    .clk              ( clk                             ),
+    .i_uart_rx        ( uart_rx                         ),
+    .o_tready         ( 1'b1                            ),
+    .o_tvalid         ( uart_rx_byte_en                 ),
+    .o_tdata          ( uart_rx_byte                    ),
+    .o_overflow       (                                 )
+);
+
+
+uart_rx_parser u_uart_rx_parser (
+    .rstn             ( rstn                            ),
+    .clk              ( clk                             ),
+    .uart_rx_byte_en  ( uart_rx_byte_en                 ),
+    .uart_rx_byte     ( uart_rx_byte                    ),
+    .tvalid           ( tvalid                          ),
+    .tdata            ( tdata                           ),
+    .tdatab           ( tdatab                          ),
+    .tlast            ( tlast                           )
+);
+
+
+fifo_sync #(
+    .DW               ( 8 + 4 + 1                       ),
+    .EA               ( 12                              )
+) u_fifo_sync (
+    .rstn             ( rstn                            ),
+    .clk              ( clk                             ),
+    .i_rdy            (                                 ),
+    .i_en             ( tvalid                          ),
+    .i_data           ( {   tdata,    tdatab,    tlast} ),
+    .o_rdy            ( tx_tready                       ),
+    .o_en             ( tx_tvalid                       ),
+    .o_data           ( {tx_tdata, tx_tdatab, tx_tlast} )
+);
+
+
+nfca_controller u_nfca_controller (
+    .rstn             ( rstn                            ),
+    .clk              ( clk                             ),
+    .tx_tvalid        ( tx_tvalid                       ),
+    .tx_tready        ( tx_tready                       ),
+    .tx_tdata         ( tx_tdata                        ),
+    .tx_tdatab        ( tx_tdatab                       ),
+    .tx_tlast         ( tx_tlast                        ),
+    .rx_on            ( rx_on                           ),
+    .rx_tvalid        ( rx_tvalid                       ),
+    .rx_tdata         ( rx_tdata                        ),
+    .rx_tdatab        ( rx_tdatab                       ),
+    .rx_tend          ( rx_tend                         ),
+    .rx_terr          ( rx_terr                         ),
+    .adc_data_en      ( adc_data_en                     ),
+    .adc_data         ( adc_data                        ),
+    .carrier_out      ( carrier_out                     )
+);
+
+
+function  [7:0] hex2ascii;
+    input [3:0] hex;
+begin
+    hex2ascii = (hex<4'hA) ? (hex+"0") : (hex+("A"-8'hA)) ;
+end
+endfunction
+
+
+uart_tx #(
+    .CLK_FREQ         ( 81360000                        ),
+    .BAUD_RATE        ( 9600                            ),
+    .PARITY           ( "NONE"                          ),
+    .STOP_BITS        ( 4                               ),
+    .BYTE_WIDTH       ( 4                               ),
+    .FIFO_EA          ( 12                              ),
+    .EXTRA_BYTE_AFTER_TRANSFER ( ""                     ),
+    .EXTRA_BYTE_AFTER_PACKET   ( ""                     )
+) u_uart_tx (
+    .rstn             ( rstn                            ),
+    .clk              ( clk                             ),
+    .i_tready         (                                 ),
+    .i_tvalid         ( rx_tvalid                       ),
+    .i_tdata          ( rx_tend ? {8'h00, 8'h00, "\n", (rx_terr ? "n" : 8'h00)} : { ((rx_tdatab<4'd8) ? hex2ascii(rx_tdatab) : 8'h00), ((rx_tdatab<4'd8) ? ":" : " "), hex2ascii(rx_tdata[3:0]), hex2ascii(rx_tdata[7:4]) } ),
+    .i_tkeep          ( rx_tend ? {1'b0 , 1'b0 , 1'b1, (rx_terr ? 1'b1 : 1'b0)} : { ((rx_tdatab<4'd8) ? 1'b1                 : 1'b0 ),  3'b111                                                                            } ),
+    .i_tlast          ( 1'b0                            ),
+    .o_uart_tx        ( uart_tx                         )
+);
+
+
+endmodule

WangXuan95_FPGA-NFC/RTL/uart_rx.v

@@ -0,0 +1,335 @@
+
+//--------------------------------------------------------------------------------------------------------
+// Module  : uart_rx
+// Type    : synthesizable, IP's top
+// Standard: Verilog 2001 (IEEE1364-2001)
+// Function: input  UART signal,
+//           output AXI-stream (1 byte data width)
+//--------------------------------------------------------------------------------------------------------
+
+module uart_rx #(
+    // clock frequency
+    parameter  CLK_FREQ  = 50000000,     // clk frequency, Unit : Hz
+    // UART format
+    parameter  BAUD_RATE = 115200,       // Unit : Hz
+    parameter  PARITY    = "NONE",       // "NONE", "ODD", or "EVEN"
+    // RX fifo depth
+    parameter  FIFO_EA   = 0             // 0:no fifo   1,2:depth=4   3:depth=8   4:depth=16  ...  10:depth=1024   11:depth=2048  ...
+) (
+    input  wire        rstn,
+    input  wire        clk,
+    // UART RX input signal
+    input  wire        i_uart_rx,
+    // output AXI-stream master. Associated clock = clk. 
+    input  wire        o_tready,
+    output reg         o_tvalid,
+    output reg  [ 7:0] o_tdata,
+    // report whether there's a overflow
+    output reg         o_overflow
+);
+
+
+
+//---------------------------------------------------------------------------------------------------------------------------------------------------------------
+// Generate fractional precise upper limit for counter
+//---------------------------------------------------------------------------------------------------------------------------------------------------------------
+localparam  BAUD_CYCLES      = ( (CLK_FREQ*10*2 + BAUD_RATE) / (BAUD_RATE*2) ) / 10 ;
+localparam  BAUD_CYCLES_FRAC = ( (CLK_FREQ*10*2 + BAUD_RATE) / (BAUD_RATE*2) ) % 10 ;
+
+localparam           HALF_BAUD_CYCLES =  BAUD_CYCLES    / 2;
+localparam  THREE_QUARTER_BAUD_CYCLES = (BAUD_CYCLES*3) / 4;
+
+localparam [9:0] ADDITION_CYCLES = (BAUD_CYCLES_FRAC == 0) ? 10'b0000000000 :
+                                   (BAUD_CYCLES_FRAC == 1) ? 10'b0000010000 :
+                                   (BAUD_CYCLES_FRAC == 2) ? 10'b0010000100 :
+                                   (BAUD_CYCLES_FRAC == 3) ? 10'b0010010010 :
+                                   (BAUD_CYCLES_FRAC == 4) ? 10'b0101001010 :
+                                   (BAUD_CYCLES_FRAC == 5) ? 10'b0101010101 :
+                                   (BAUD_CYCLES_FRAC == 6) ? 10'b1010110101 :
+                                   (BAUD_CYCLES_FRAC == 7) ? 10'b1101101101 :
+                                   (BAUD_CYCLES_FRAC == 8) ? 10'b1101111011 :
+                                  /*BAUD_CYCLES_FRAC == 9)*/ 10'b1111101111 ;
+
+wire [31:0] cycles [9:0];
+
+assign cycles[0] = BAUD_CYCLES + (ADDITION_CYCLES[0] ? 1 : 0);
+assign cycles[1] = BAUD_CYCLES + (ADDITION_CYCLES[1] ? 1 : 0);
+assign cycles[2] = BAUD_CYCLES + (ADDITION_CYCLES[2] ? 1 : 0);
+assign cycles[3] = BAUD_CYCLES + (ADDITION_CYCLES[3] ? 1 : 0);
+assign cycles[4] = BAUD_CYCLES + (ADDITION_CYCLES[4] ? 1 : 0);
+assign cycles[5] = BAUD_CYCLES + (ADDITION_CYCLES[5] ? 1 : 0);
+assign cycles[6] = BAUD_CYCLES + (ADDITION_CYCLES[6] ? 1 : 0);
+assign cycles[7] = BAUD_CYCLES + (ADDITION_CYCLES[7] ? 1 : 0);
+assign cycles[8] = BAUD_CYCLES + (ADDITION_CYCLES[8] ? 1 : 0);
+assign cycles[9] = BAUD_CYCLES + (ADDITION_CYCLES[9] ? 1 : 0);
+
+
+
+//---------------------------------------------------------------------------------------------------------------------------------------------------------------
+// Input beat
+//---------------------------------------------------------------------------------------------------------------------------------------------------------------
+reg        rx_d1 = 1'b0;
+
+always @ (posedge clk or negedge rstn)
+    if (~rstn)
+        rx_d1 <= 1'b0;
+    else
+        rx_d1 <= i_uart_rx;
+
+
+
+//---------------------------------------------------------------------------------------------------------------------------------------------------------------
+// count continuous '1'
+//---------------------------------------------------------------------------------------------------------------------------------------------------------------
+reg [31:0] count1 = 0;
+
+always @ (posedge clk or negedge rstn)
+    if (~rstn) begin
+        count1 <= 0;
+    end else begin
+        if (rx_d1)
+            count1 <= (count1 < 'hFFFFFFFF) ? (count1 + 1) : count1;
+        else
+            count1 <= 0;
+    end
+
+
+
+//---------------------------------------------------------------------------------------------------------------------------------------------------------------
+// main FSM
+//---------------------------------------------------------------------------------------------------------------------------------------------------------------
+localparam [ 3:0] TOTAL_BITS_MINUS1 = (PARITY == "ODD" || PARITY == "EVEN") ? 4'd9 : 4'd8;
+
+localparam [ 1:0] S_IDLE     = 2'd0 ,
+                  S_RX       = 2'd1 ,
+                  S_STOP_BIT = 2'd2 ;
+
+reg        [ 1:0] state   = S_IDLE;
+reg        [ 8:0] rxbits  = 9'b0;
+reg        [ 3:0] rxcnt   = 4'd0;
+reg        [31:0] cycle   = 1;
+reg        [32:0] countp  = 33'h1_0000_0000;       // countp>=0x100000000 means '1' is majority       , countp<0x100000000 means '0' is majority
+wire              rxbit   = countp[32];            // countp>=0x100000000 corresponds to countp[32]==1, countp<0x100000000 corresponds to countp[32]==0
+
+wire [ 7:0] rbyte   = (PARITY == "ODD" ) ? rxbits[7:0] : 
+                      (PARITY == "EVEN") ? rxbits[7:0] : 
+                    /*(PARITY == "NONE")*/ rxbits[8:1] ;
+
+wire parity_correct = (PARITY == "ODD" ) ? ((~(^(rbyte))) == rxbits[8]) : 
+                      (PARITY == "EVEN") ? (  (^(rbyte))  == rxbits[8]) : 
+                    /*(PARITY == "NONE")*/      1'b1                    ;
+
+
+always @ (posedge clk or negedge rstn)
+    if (~rstn) begin
+        state    <= S_IDLE;
+        rxbits   <= 9'b0;
+        rxcnt    <= 4'd0;
+        cycle    <= 1;
+        countp   <= 33'h1_0000_0000;
+    end else begin
+        case (state)
+            S_IDLE : begin
+                if ((count1 >= THREE_QUARTER_BAUD_CYCLES) && (rx_d1 == 1'b0))  // receive a '0' which is followed by continuous '1' for half baud cycles
+                    state <= S_RX;
+                rxcnt  <= 4'd0;
+                cycle  <= 2;                                                   // we've already receive a '0', so here cycle  = 2
+                countp <= (33'h1_0000_0000 - 33'd1);                           // we've already receive a '0', so here countp = initial_value - 1
+            end
+            
+            S_RX :
+                if ( cycle < cycles[rxcnt] ) begin                             // cycle loop from 1 to cycles[rxcnt]
+                    cycle  <= cycle + 1;
+                    countp <= rx_d1 ? (countp + 33'd1) : (countp - 33'd1);
+                end else begin
+                    cycle  <= 1;                                               // reset counter
+                    countp <= 33'h1_0000_0000;                                 // reset counter
+                    
+                    if ( rxcnt < TOTAL_BITS_MINUS1 ) begin                     // rxcnt loop from 0 to TOTAL_BITS_MINUS1
+                        rxcnt <= rxcnt + 4'd1;
+                        if ((rxcnt == 4'd0) && (rxbit == 1'b1))                // except start bit, but get '1'
+                            state <= S_IDLE;                                   // RX failed, back to IDLE
+                    end else begin
+                        rxcnt <= 4'd0;
+                        state <= S_STOP_BIT;
+                    end
+                    
+                    rxbits <= {rxbit, rxbits[8:1]};                            // put current rxbit to MSB of rxbits, and right shift other bits
+                end
+            
+            default :  // S_STOP_BIT
+                if ( cycle < THREE_QUARTER_BAUD_CYCLES) begin                  // cycle loop from 1 to THREE_QUARTER_BAUD_CYCLES
+                    cycle <= cycle + 1;
+                end else begin
+                    cycle <= 1;                                                // reset counter
+                    state <= S_IDLE;                                           // back to IDLE
+                end
+        endcase
+    end
+
+
+
+//---------------------------------------------------------------------------------------------------------------------------------------------------------------
+// RX result byte
+//---------------------------------------------------------------------------------------------------------------------------------------------------------------
+reg       f_tvalid = 1'b0;
+reg [7:0] f_tdata  = 8'h0;
+
+always @ (posedge clk or negedge rstn)
+    if (~rstn) begin
+        f_tvalid <= 1'b0;
+        f_tdata  <= 8'h0;
+    end else begin
+        f_tvalid <= 1'b0;
+        f_tdata  <= 8'h0;
+        if (state == S_STOP_BIT) begin
+            if ( cycle < THREE_QUARTER_BAUD_CYCLES) begin
+            end else begin
+                if ((count1 >= HALF_BAUD_CYCLES) && parity_correct) begin  // stop bit have enough '1', and parity correct
+                    f_tvalid <= 1'b1;
+                    f_tdata  <= rbyte;                                     // received a correct byte, output it
+                end
+            end
+        end
+    end
+
+
+
+//---------------------------------------------------------------------------------------------------------------------------------------------------------------
+// RX fifo
+//---------------------------------------------------------------------------------------------------------------------------------------------------------------
+wire f_tready;
+
+generate if (FIFO_EA <= 0) begin          // no RX fifo
+    
+    assign       f_tready = o_tready;
+    always @ (*) o_tvalid = f_tvalid;
+    always @ (*) o_tdata  = f_tdata;
+
+end else begin                            // TX fifo
+
+    localparam        EA     = (FIFO_EA <= 2) ? 2 : FIFO_EA;
+
+    reg  [7:0] buffer [ ((1<<EA)-1) : 0 ];
+
+    localparam [EA:0] A_ZERO = {{EA{1'b0}}, 1'b0};
+    localparam [EA:0] A_ONE  = {{EA{1'b0}}, 1'b1};
+
+    reg  [EA:0] wptr      = A_ZERO;
+    reg  [EA:0] wptr_d1   = A_ZERO;
+    reg  [EA:0] wptr_d2   = A_ZERO;
+    reg  [EA:0] rptr      = A_ZERO;
+    wire [EA:0] rptr_next = (o_tvalid & o_tready) ? (rptr+A_ONE) : rptr;
+
+    assign f_tready = ( wptr != {~rptr[EA], rptr[EA-1:0]} );
+
+    always @ (posedge clk or negedge rstn)
+        if (~rstn) begin
+            wptr    <= A_ZERO;
+            wptr_d1 <= A_ZERO;
+            wptr_d2 <= A_ZERO;
+        end else begin
+            if (f_tvalid & f_tready)
+                wptr <= wptr + A_ONE;
+            wptr_d1 <= wptr;
+            wptr_d2 <= wptr_d1;
+        end
+
+    always @ (posedge clk)
+        if (f_tvalid & f_tready)
+            buffer[wptr[EA-1:0]] <= f_tdata;
+
+    always @ (posedge clk or negedge rstn)
+        if (~rstn) begin
+            rptr <= A_ZERO;
+            o_tvalid <= 1'b0;
+        end else begin
+            rptr <= rptr_next;
+            o_tvalid <= (rptr_next != wptr_d2);
+        end
+
+    always @ (posedge clk)
+        o_tdata <= buffer[rptr_next[EA-1:0]];
+
+    initial o_tvalid = 1'b0;
+    initial o_tdata  = 8'h0;
+end endgenerate
+
+
+
+//---------------------------------------------------------------------------------------------------------------------------------------------------------------
+// detect RX fifo overflow
+//---------------------------------------------------------------------------------------------------------------------------------------------------------------
+initial o_overflow = 1'b0;
+
+always @ (posedge clk or negedge rstn)
+    if (~rstn)
+        o_overflow <= 1'b0;
+    else
+        o_overflow <= (f_tvalid & (~f_tready));
+
+
+
+//---------------------------------------------------------------------------------------------------------------------------------------------------------------
+// parameter checking
+//---------------------------------------------------------------------------------------------------------------------------------------------------------------
+initial begin
+    if (BAUD_CYCLES < 10) begin $error("invalid parameter : BAUD_CYCLES < 10, please use a faster driving clock"); $stop; end
+    
+    $display("uart_rx :           parity = %s" , PARITY );
+    $display("uart_rx :     clock period = %.0f ns   (%-10d Hz)" , 1000000000.0/CLK_FREQ  , CLK_FREQ );
+    $display("uart_rx : baud rate period = %.0f ns   (%-10d Hz)" , 1000000000.0/BAUD_RATE , BAUD_RATE);
+    $display("uart_rx :      baud cycles = %-10d"    , BAUD_CYCLES );
+    $display("uart_rx : baud cycles frac = %-10d"    , BAUD_CYCLES_FRAC  );
+    
+    if (PARITY == "ODD" || PARITY == "EVEN") begin
+        $display("uart_rx :             __      ____ ____ ____ ____ ____ ____ ____ ____________ ");
+        $display("uart_rx :        wave   \\____/____X____X____X____X____X____X____X____X____/   ");
+        $display("uart_rx :        bits   | S  | B0 | B1 | B2 | B3 | B4 | B5 | B6 | B7 | P  |   ");
+        $display("uart_rx : time_points  t0   t1   t2   t3   t4   t5   t6   t7   t8   t9   t10  ");
+        $display("uart_rx :");
+    end else begin
+        $display("uart_rx :             __      ____ ____ ____ ____ ____ ____ ____ _______ ");
+        $display("uart_rx :        wave   \\____/____X____X____X____X____X____X____X____/   ");
+        $display("uart_rx :        bits   | S  | B0 | B1 | B2 | B3 | B4 | B5 | B6 | B7 |   ");
+        $display("uart_rx : time_points  t0   t1   t2   t3   t4   t5   t6   t7   t8   t9   ");
+        $display("uart_rx :");
+    end
+end
+
+generate genvar index;
+    for (index=0; index<=9; index=index+1) begin : print_and_check_time
+        localparam cycles_acc = ( (index >= 0) ? (BAUD_CYCLES + (ADDITION_CYCLES[0] ? 1 : 0)) : 0 )
+                              + ( (index >= 1) ? (BAUD_CYCLES + (ADDITION_CYCLES[1] ? 1 : 0)) : 0 )
+                              + ( (index >= 2) ? (BAUD_CYCLES + (ADDITION_CYCLES[2] ? 1 : 0)) : 0 )
+                              + ( (index >= 3) ? (BAUD_CYCLES + (ADDITION_CYCLES[3] ? 1 : 0)) : 0 )
+                              + ( (index >= 4) ? (BAUD_CYCLES + (ADDITION_CYCLES[4] ? 1 : 0)) : 0 )
+                              + ( (index >= 5) ? (BAUD_CYCLES + (ADDITION_CYCLES[5] ? 1 : 0)) : 0 )
+                              + ( (index >= 6) ? (BAUD_CYCLES + (ADDITION_CYCLES[6] ? 1 : 0)) : 0 )
+                              + ( (index >= 7) ? (BAUD_CYCLES + (ADDITION_CYCLES[7] ? 1 : 0)) : 0 )
+                              + ( (index >= 8) ? (BAUD_CYCLES + (ADDITION_CYCLES[8] ? 1 : 0)) : 0 )
+                              + ( (index >= 9) ? (BAUD_CYCLES + (ADDITION_CYCLES[9] ? 1 : 0)) : 0 ) ;
+        
+        localparam real ideal_time_ns  = ((index+1)*1000000000.0/BAUD_RATE);
+        localparam real actual_time_ns = (cycles_acc*1000000000.0/CLK_FREQ);
+        localparam real uncertainty    = (1000000000.0/CLK_FREQ);
+        localparam real error          = ( (ideal_time_ns>actual_time_ns) ? (ideal_time_ns-actual_time_ns) : (-ideal_time_ns+actual_time_ns) ) + uncertainty;
+        localparam real relative_error_percent = (error / (1000000000.0/BAUD_RATE)) * 100.0;
+        
+        initial if (PARITY == "ODD" || PARITY == "EVEN" || index < 9) begin
+            $display("uart_rx : t%-2d- t0 = %.0f ns (ideal)  %.0f +- %.0f ns (actual).   error=%.0f ns   relative_error=%.3f%%" ,
+                (index+1) ,
+                ideal_time_ns ,
+                actual_time_ns,
+                uncertainty,
+                error,
+                relative_error_percent
+            );
+            
+            if ( relative_error_percent > 8.0 ) begin $error("relative_error is too large"); $stop; end   // if relative error larger than 8%
+        end
+    end
+endgenerate
+
+
+endmodule

WangXuan95_FPGA-NFC/RTL/uart_rx_parser.v

@@ -0,0 +1,130 @@
+
+module uart_rx_parser #(
+    parameter CLK_DIV = 108  // UART baud rate = clk freq/(4*CLK_DIV), modify CLK_DIV to change the UART baud
+                             // for example, when clk=125MHz, CLK_DIV=271, then baud=125MHz/(4*271)=115200, 115200 is a typical baud rate for UART
+) (
+    input  wire       rstn,
+    input  wire       clk,
+    // uart RX bytes input
+    input  wire       uart_rx_byte_en,
+    input  wire [7:0] uart_rx_byte,
+    // parsed byte stream
+    output reg        tvalid,
+    output reg  [7:0] tdata,
+    output reg  [3:0] tdatab,
+    output reg        tlast
+);
+
+
+initial {tvalid, tdata, tlast, tdatab} = 0;
+
+localparam [7:0] CHAR_0  = 8'h30,  // "0"
+                 CHAR_9  = 8'h39,  // "9"
+                 CHAR_A  = 8'h41,  // "A"
+                 CHAR_F  = 8'h46,  // "F"
+                 CHAR_a  = 8'h61,  // "a"
+                 CHAR_f  = 8'h66,  // "f"
+                 CHAR_ht = 8'h09,  // "\t"
+                 CHAR_sp = 8'h20,  // " "
+                 CHAR_cr = 8'h0D,  // "\r"
+                 CHAR_lf = 8'h0A,  // "\n"
+                 CHAR_cl = 8'h3A;  // ":"
+
+
+function  [4:0] ascii2hex;
+    input [7:0] ascii;
+    reg   [7:0] tmp;
+begin
+    if         ( ascii >= CHAR_0 && ascii <= CHAR_9 ) begin
+        tmp = ascii - CHAR_0;
+        ascii2hex = {1'b1, tmp[3:0]};
+    end else if( ascii >= CHAR_A && ascii <= CHAR_F ) begin
+        tmp = ascii - CHAR_A + 8'd10;
+        ascii2hex = {1'b1, tmp[3:0]};
+    end else if( ascii >= CHAR_a && ascii <= CHAR_f ) begin
+        tmp = ascii - CHAR_a + 8'd10;
+        ascii2hex = {1'b1, tmp[3:0]};
+    end else begin
+        tmp = ascii;
+        ascii2hex = {1'b0, 4'h0};
+    end
+end
+endfunction
+
+
+wire       isspace = (uart_rx_byte == CHAR_sp) || (uart_rx_byte == CHAR_ht);
+wire       iscrlf  = (uart_rx_byte == CHAR_cr) || (uart_rx_byte == CHAR_lf);
+wire       iscolon = (uart_rx_byte == CHAR_cl);
+wire       ishex;
+wire [3:0] hexvalue;
+
+assign {ishex, hexvalue} = ascii2hex(uart_rx_byte);
+
+localparam [2:0] INIT   = 3'd0,
+                 HEXH   = 3'd1,
+                 HEXL   = 3'd2,
+                 LASTB  = 3'd3,
+                 INVALID= 3'd4;
+reg [2:0] fsm = INIT;
+
+reg [7:0] savedata = 0;
+
+always @ (posedge clk or negedge rstn)
+    if(~rstn) begin
+        {tvalid, tdata, tlast, tdatab} <= 0;
+        fsm <= INIT;
+        savedata <= 0;
+    end else begin
+        {tvalid, tdata, tlast} <= 0;
+        tdatab <= 4'd8;
+        if(uart_rx_byte_en) begin        
+            if         (fsm == INIT) begin
+                if(ishex) begin
+                    savedata <= {4'h0, hexvalue};
+                    fsm <= HEXH;
+                end else if(~iscrlf & ~isspace) begin
+                    fsm <= INVALID;
+                end
+            end else if(fsm == HEXH || fsm==HEXL) begin
+                if(ishex) begin
+                    if(fsm == HEXH) begin
+                        savedata <= {savedata[3:0], hexvalue};
+                        fsm <= HEXL;
+                    end else begin
+                        {tvalid, tdata, tlast} <= {1'b1, savedata, 1'b0};
+                        savedata <= {4'h0, hexvalue};
+                        fsm <= HEXH;
+                    end
+                end else if(iscolon) begin
+                    fsm <= LASTB;
+                end else if(isspace) begin
+                    fsm <= HEXL;
+                end else if(iscrlf) begin
+                    {tvalid, tdata, tlast} <= {1'b1, savedata, 1'b1};
+                    fsm <= INIT;
+                end else begin
+                    {tvalid, tdata, tlast} <= {1'b1, savedata, 1'b1};
+                    fsm <= INVALID;
+                end
+            end else if(fsm == LASTB) begin
+                if(ishex) begin
+                    {tvalid, tdata, tlast} <= {1'b1, savedata, 1'b1};
+                    if     (hexvalue == 4'd0)
+                        tdatab <= 4'd1;
+                    else if(hexvalue <= 4'd7)
+                        tdatab <= hexvalue;
+                    fsm <= INVALID;
+                end else if(iscrlf) begin
+                    {tvalid, tdata, tlast} <= {1'b1, savedata, 1'b1};
+                    fsm <= INIT;
+                end else begin
+                    {tvalid, tdata, tlast} <= {1'b1, savedata, 1'b1};
+                    fsm <= INVALID;
+                end
+            end else if(iscrlf) begin
+                fsm <= INIT;
+            end
+        end
+    end
+
+endmodule

WangXuan95_FPGA-NFC/RTL/uart_tx.v

@@ -0,0 +1,340 @@
+
+//--------------------------------------------------------------------------------------------------------
+// Module  : uart_tx
+// Type    : synthesizable, IP's top
+// Standard: Verilog 2001 (IEEE1364-2001)
+// Function: input  AXI-stream (configurable data width),
+//           output UART signal
+//--------------------------------------------------------------------------------------------------------
+
+module uart_tx #(
+    // clock frequency
+    parameter  CLK_FREQ                  = 50000000,     // clk frequency, Unit : Hz
+    // UART format
+    parameter  BAUD_RATE                 = 115200,       // Unit : Hz
+    parameter  PARITY                    = "NONE",       // "NONE", "ODD", or "EVEN"
+    parameter  STOP_BITS                 = 2,            // can be 1, 2, 3, 4, ...
+    // AXI stream data width
+    parameter  BYTE_WIDTH                = 1,            // can be 1, 2, 3, 4, ...
+    // TX fifo depth
+    parameter  FIFO_EA                   = 0,            // 0:no fifo   1,2:depth=4   3:depth=8   4:depth=16  ...  10:depth=1024   11:depth=2048  ...
+    // do you want to send extra byte after each AXI-stream transfer or packet?
+    parameter  EXTRA_BYTE_AFTER_TRANSFER = "",           // specify a extra byte to send after each AXI-stream transfer. when ="", do not send this extra byte
+    parameter  EXTRA_BYTE_AFTER_PACKET   = ""            // specify a extra byte to send after each AXI-stream packet  . when ="", do not send this extra byte
+) (
+    input  wire                    rstn,
+    input  wire                    clk,
+    // input  stream : AXI-stream slave. Associated clock = clk
+    output wire                    i_tready,
+    input  wire                    i_tvalid,
+    input  wire [8*BYTE_WIDTH-1:0] i_tdata,
+    input  wire [  BYTE_WIDTH-1:0] i_tkeep,
+    input  wire                    i_tlast,
+    // UART TX output signal
+    output reg                     o_uart_tx
+);
+
+
+
+//---------------------------------------------------------------------------------------------------------------------------------------------------------------
+// TX fifo
+//---------------------------------------------------------------------------------------------------------------------------------------------------------------
+wire                    f_tready;
+reg                     f_tvalid;
+reg  [8*BYTE_WIDTH-1:0] f_tdata;
+reg  [  BYTE_WIDTH-1:0] f_tkeep;
+reg                     f_tlast;
+
+generate if (FIFO_EA <= 0) begin          // no TX fifo
+
+    assign       i_tready = f_tready;
+    always @ (*) f_tvalid = i_tvalid;
+    always @ (*) f_tdata  = i_tdata;
+    always @ (*) f_tkeep  = i_tkeep;
+    always @ (*) f_tlast  = i_tlast;
+
+end else begin                            // TX fifo
+
+    localparam        EA     = (FIFO_EA<=2) ? 2 : FIFO_EA;
+    localparam        DW     = ( 1 + BYTE_WIDTH + 8*BYTE_WIDTH );     // 1-bit tlast, (BYTE_WIDTH)-bit tkeep, (8*BYTE_WIDTH)-bit tdata
+    
+    reg  [DW-1:0] buffer [ ((1<<EA)-1) : 0 ];
+    
+    localparam [EA:0] A_ZERO = {{EA{1'b0}}, 1'b0};
+    localparam [EA:0] A_ONE  = {{EA{1'b0}}, 1'b1};
+
+    reg  [EA:0] wptr      = A_ZERO;
+    reg  [EA:0] wptr_d1   = A_ZERO;
+    reg  [EA:0] wptr_d2   = A_ZERO;
+    reg  [EA:0] rptr      = A_ZERO;
+    wire [EA:0] rptr_next = (f_tvalid & f_tready) ? (rptr+A_ONE) : rptr;
+    
+    assign i_tready = ( wptr != {~rptr[EA], rptr[EA-1:0]} );
+
+    always @ (posedge clk or negedge rstn)
+        if (~rstn) begin
+            wptr    <= A_ZERO;
+            wptr_d1 <= A_ZERO;
+            wptr_d2 <= A_ZERO;
+        end else begin
+            if (i_tvalid & i_tready)
+                wptr <= wptr + A_ONE;
+            wptr_d1 <= wptr;
+            wptr_d2 <= wptr_d1;
+        end
+
+    always @ (posedge clk)
+        if (i_tvalid & i_tready)
+            buffer[wptr[EA-1:0]] <= {i_tlast, i_tkeep, i_tdata};
+
+    always @ (posedge clk or negedge rstn)
+        if (~rstn) begin
+            rptr <= A_ZERO;
+            f_tvalid <= 1'b0;
+        end else begin
+            rptr <= rptr_next;
+            f_tvalid <= (rptr_next != wptr_d2);
+        end
+
+    always @ (posedge clk)
+        {f_tlast, f_tkeep, f_tdata} <= buffer[rptr_next[EA-1:0]];
+    
+    initial {f_tvalid, f_tlast, f_tkeep, f_tdata} = 0;
+    
+end endgenerate
+
+
+
+
+//---------------------------------------------------------------------------------------------------------------------------------------------------------------
+// Generate fractional precise upper limit for counter
+//---------------------------------------------------------------------------------------------------------------------------------------------------------------
+localparam      BAUD_CYCLES              = ( (CLK_FREQ*10*2 + BAUD_RATE) / (BAUD_RATE*2) ) / 10 ;
+localparam      BAUD_CYCLES_FRAC         = ( (CLK_FREQ*10*2 + BAUD_RATE) / (BAUD_RATE*2) ) % 10 ;
+localparam      STOP_BIT_CYCLES          = (BAUD_CYCLES_FRAC == 0) ? BAUD_CYCLES : (BAUD_CYCLES + 1);
+
+localparam [9:0] ADDITION_CYCLES = (BAUD_CYCLES_FRAC == 0) ? 10'b0000000000 :
+                                   (BAUD_CYCLES_FRAC == 1) ? 10'b0000010000 :
+                                   (BAUD_CYCLES_FRAC == 2) ? 10'b0010000100 :
+                                   (BAUD_CYCLES_FRAC == 3) ? 10'b0010010010 :
+                                   (BAUD_CYCLES_FRAC == 4) ? 10'b0101001010 :
+                                   (BAUD_CYCLES_FRAC == 5) ? 10'b0101010101 :
+                                   (BAUD_CYCLES_FRAC == 6) ? 10'b1010110101 :
+                                   (BAUD_CYCLES_FRAC == 7) ? 10'b1101101101 :
+                                   (BAUD_CYCLES_FRAC == 8) ? 10'b1101111011 :
+                                  /*BAUD_CYCLES_FRAC == 9)*/ 10'b1111101111 ;
+
+wire [31:0] cycles [9:0];
+
+assign cycles[0] = BAUD_CYCLES + (ADDITION_CYCLES[0] ? 1 : 0);
+assign cycles[1] = BAUD_CYCLES + (ADDITION_CYCLES[1] ? 1 : 0);
+assign cycles[2] = BAUD_CYCLES + (ADDITION_CYCLES[2] ? 1 : 0);
+assign cycles[3] = BAUD_CYCLES + (ADDITION_CYCLES[3] ? 1 : 0);
+assign cycles[4] = BAUD_CYCLES + (ADDITION_CYCLES[4] ? 1 : 0);
+assign cycles[5] = BAUD_CYCLES + (ADDITION_CYCLES[5] ? 1 : 0);
+assign cycles[6] = BAUD_CYCLES + (ADDITION_CYCLES[6] ? 1 : 0);
+assign cycles[7] = BAUD_CYCLES + (ADDITION_CYCLES[7] ? 1 : 0);
+assign cycles[8] = BAUD_CYCLES + (ADDITION_CYCLES[8] ? 1 : 0);
+assign cycles[9] = BAUD_CYCLES + (ADDITION_CYCLES[9] ? 1 : 0);
+
+
+
+//---------------------------------------------------------------------------------------------------------------------------------------------------------------
+// 
+//---------------------------------------------------------------------------------------------------------------------------------------------------------------
+localparam [BYTE_WIDTH-1:0] ZERO_KEEP   = 0;
+
+localparam           [31:0] PARITY_BITS = (PARITY == "ODD" || PARITY == "EVEN") ? 1 : 0;
+localparam           [31:0] TOTAL_BITS  = (STOP_BITS >= ('hFFFFFFFF-9-PARITY_BITS)) ? 'hFFFFFFFF : (PARITY_BITS+STOP_BITS+9);
+
+localparam           [ 0:0] BYTE_T_EN   = (EXTRA_BYTE_AFTER_TRANSFER == "") ? 1'b0 : 1'b1;
+localparam           [ 0:0] BYTE_B_EN   = (EXTRA_BYTE_AFTER_PACKET   == "") ? 1'b0 : 1'b1;
+localparam           [ 7:0] BYTE_T      =  EXTRA_BYTE_AFTER_TRANSFER;
+localparam           [ 7:0] BYTE_P      =  EXTRA_BYTE_AFTER_PACKET;
+
+
+
+//---------------------------------------------------------------------------------------------------------------------------------------------------------------
+// function for calculate parity bit
+//---------------------------------------------------------------------------------------------------------------------------------------------------------------
+function  [0:0] get_parity;
+    input [7:0] data;
+begin
+    get_parity = (PARITY == "ODD" ) ? (~(^(data[7:0]))) : 
+                 (PARITY == "EVEN") ?   (^(data[7:0]))  : 
+               /*(PARITY == "NONE")*/      1'b1         ;
+end
+endfunction
+
+
+
+//---------------------------------------------------------------------------------------------------------------------------------------------------------------
+// main FSM
+//---------------------------------------------------------------------------------------------------------------------------------------------------------------
+localparam [       1:0] S_IDLE     = 2'b01 ,       // only in state S_IDLE, state[0]==1, the goal is to make f_tready pure register-out
+                        S_PREPARE  = 2'b00 ,
+                        S_TX       = 2'b10 ;
+
+reg  [             1:0] state      = S_IDLE;       // FSM state register
+
+reg  [8*BYTE_WIDTH-1:0] data       = 0;
+reg  [  BYTE_WIDTH-1:0] keep       = 0;
+reg                     byte_t_en  = 1'b0;
+reg                     byte_p_en  = 1'b0;
+reg  [             9:0] txbits     = 10'b0;
+reg  [            31:0] txcnt      = 0;
+reg  [            31:0] cycle      = 1;
+
+
+always @ (posedge clk or negedge rstn)
+    if (~rstn) begin
+        state      <= S_IDLE;
+        data       <= 0;
+        keep       <= 0;
+        byte_t_en  <= 1'b0;
+        byte_p_en  <= 1'b0;
+        txbits     <= 10'b0;
+        txcnt      <= 0;
+        cycle      <= 1;
+    end else begin
+        case (state)
+            S_IDLE : begin
+                state      <= f_tvalid ? S_PREPARE : S_IDLE;
+                data       <= f_tdata;
+                keep       <= f_tkeep;
+                byte_t_en  <= BYTE_T_EN;
+                byte_p_en  <= BYTE_B_EN & f_tlast;
+                txbits     <= 10'b0;
+                txcnt      <= 0;
+                cycle      <= 1;
+            end
+            
+            S_PREPARE : begin
+                data <= (data >> 8);
+                keep <= (keep >> 1);
+                if          ( keep[0] == 1'b1   ) begin
+                    txbits     <= {get_parity(data[7:0]), data[7:0], 1'b0};
+                    state      <= S_TX;
+                end else if ( keep != ZERO_KEEP ) begin
+                    state      <= S_PREPARE;
+                end else if ( byte_t_en         ) begin
+                    byte_t_en <= 1'b0;
+                    txbits     <= {get_parity(BYTE_T), BYTE_T, 1'b0};
+                    state      <= S_TX;
+                end else if ( byte_p_en         ) begin
+                    byte_p_en <= 1'b0;
+                    txbits     <= {get_parity(BYTE_P), BYTE_P, 1'b0};
+                    state      <= S_TX;
+                end else begin
+                    state      <= S_IDLE;
+                end
+                txcnt <= 0;
+                cycle <= 1;
+            end
+            
+            default : begin  // S_TX
+                if (keep[0] == 1'b0) begin
+                    data <= (data >> 8);
+                    keep <= (keep >> 1);
+                end
+                if ( cycle < ((txcnt<=9) ? cycles[txcnt] : STOP_BIT_CYCLES) ) begin      // cycle loop from 1 to ((txcnt<=9) ? cycles[txcnt] : STOP_BIT_CYCLES)
+                    cycle  <= cycle + 1;
+                end else begin
+                    cycle  <= 1;
+                    txbits <= {1'b1, txbits[9:1]};                                       // right shift txbits, and fill '1' to MSB
+                    if ( txcnt < (TOTAL_BITS-1) ) begin                                  // txcnt loop from 0 to (TOTAL_BITS-1)
+                        txcnt <= txcnt + 1;
+                    end else begin
+                        txcnt <= 0;
+                        state <= S_PREPARE;
+                    end
+                end
+            end
+        endcase
+    end
+
+
+
+//---------------------------------------------------------------------------------------------------------------------------------------------------------------
+// generate UART output
+//---------------------------------------------------------------------------------------------------------------------------------------------------------------
+initial o_uart_tx = 1'b1;
+
+always @ (posedge clk or negedge rstn)
+    if (~rstn)
+        o_uart_tx <= 1'b1;
+    else
+        o_uart_tx <= (state == S_TX) ? txbits[0] : 1'b1;
+
+
+
+//---------------------------------------------------------------------------------------------------------------------------------------------------------------
+// generate AXI-stream TREADY
+//---------------------------------------------------------------------------------------------------------------------------------------------------------------
+assign f_tready = state[0];   // (state == S_IDLE)
+
+
+
+//---------------------------------------------------------------------------------------------------------------------------------------------------------------
+// parameter checking
+//---------------------------------------------------------------------------------------------------------------------------------------------------------------
+initial begin
+    if (BYTE_WIDTH <= 0) begin $error("invalid parameter : BYTE_WIDTH<=0"); $stop; end
+    if (STOP_BITS  <= 0) begin $error("invalid parameter : STOP_BITS <=0"); $stop; end
+    if (BAUD_CYCLES < 1) begin $error("invalid parameter : BAUD_CYCLES < 1, please use a faster driving clock"); $stop; end
+    
+    $display("uart_tx :           parity = %s" , PARITY );
+    $display("uart_tx :     clock period = %.0f ns   (%-10d Hz)" , 1000000000.0/CLK_FREQ  , CLK_FREQ );
+    $display("uart_tx : baud rate period = %.0f ns   (%-10d Hz)" , 1000000000.0/BAUD_RATE , BAUD_RATE);
+    $display("uart_tx :      baud cycles = %-10d"   , BAUD_CYCLES );
+    $display("uart_tx : baud cycles frac = %-10d"   , BAUD_CYCLES_FRAC  );
+    
+    if (PARITY == "ODD" || PARITY == "EVEN") begin
+        $display("uart_tx :             __      ____ ____ ____ ____ ____ ____ ____ ____________ ");
+        $display("uart_tx :        wave   \\____/____X____X____X____X____X____X____X____X____/   ");
+        $display("uart_tx :        bits   | S  | B0 | B1 | B2 | B3 | B4 | B5 | B6 | B7 | P  |   ");
+        $display("uart_tx : time_points  t0   t1   t2   t3   t4   t5   t6   t7   t8   t9   t10  ");
+        $display("uart_tx :");
+    end else begin
+        $display("uart_tx :             __      ____ ____ ____ ____ ____ ____ ____ _______ ");
+        $display("uart_tx :        wave   \\____/____X____X____X____X____X____X____X____/   ");
+        $display("uart_tx :        bits   | S  | B0 | B1 | B2 | B3 | B4 | B5 | B6 | B7 |   ");
+        $display("uart_tx : time_points  t0   t1   t2   t3   t4   t5   t6   t7   t8   t9   ");
+        $display("uart_tx :");
+    end
+end
+
+generate genvar index, i;
+    for (index=0; index<=9; index=index+1) begin : print_and_check_time
+        localparam cycles_acc = ( (index >= 0) ? (BAUD_CYCLES + (ADDITION_CYCLES[0] ? 1 : 0)) : 0 )
+                              + ( (index >= 1) ? (BAUD_CYCLES + (ADDITION_CYCLES[1] ? 1 : 0)) : 0 )
+                              + ( (index >= 2) ? (BAUD_CYCLES + (ADDITION_CYCLES[2] ? 1 : 0)) : 0 )
+                              + ( (index >= 3) ? (BAUD_CYCLES + (ADDITION_CYCLES[3] ? 1 : 0)) : 0 )
+                              + ( (index >= 4) ? (BAUD_CYCLES + (ADDITION_CYCLES[4] ? 1 : 0)) : 0 )
+                              + ( (index >= 5) ? (BAUD_CYCLES + (ADDITION_CYCLES[5] ? 1 : 0)) : 0 )
+                              + ( (index >= 6) ? (BAUD_CYCLES + (ADDITION_CYCLES[6] ? 1 : 0)) : 0 )
+                              + ( (index >= 7) ? (BAUD_CYCLES + (ADDITION_CYCLES[7] ? 1 : 0)) : 0 )
+                              + ( (index >= 8) ? (BAUD_CYCLES + (ADDITION_CYCLES[8] ? 1 : 0)) : 0 )
+                              + ( (index >= 9) ? (BAUD_CYCLES + (ADDITION_CYCLES[9] ? 1 : 0)) : 0 ) ;
+        
+        localparam real ideal_time_ns  = ((index+1)*1000000000.0/BAUD_RATE);
+        localparam real actual_time_ns = (cycles_acc*1000000000.0/CLK_FREQ);
+        localparam real error          = (ideal_time_ns>actual_time_ns) ? (ideal_time_ns-actual_time_ns) : (-ideal_time_ns+actual_time_ns);
+        localparam real relative_error_percent = (error / (1000000000.0/BAUD_RATE)) * 100.0;
+        
+        initial if (PARITY == "ODD" || PARITY == "EVEN" || index < 9) begin
+            $display("uart_tx : t%-2d- t0 = %.0f ns (ideal)  %.0f ns (actual).   error=%.0f ns   relative_error=%.3f%%" ,
+                (index+1) ,
+                ideal_time_ns ,
+                actual_time_ns,
+                error,
+                relative_error_percent
+            );
+            
+            if ( relative_error_percent > 3.0 ) begin $error("relative_error is too large"); $stop; end   // if relative error larger than 3%
+        end
+    end
+endgenerate
+
+
+endmodule

WangXuan95_FPGA-NFC/SIM/tb_nfca_controller.v

@@ -0,0 +1,90 @@
+
+//--------------------------------------------------------------------------------------------------------
+// Module  : tb_nfca_controller
+// Type    : simulation, top
+// Standard: Verilog 2001 (IEEE1364-2001)
+// Function: testbench for nfca_controller
+//           only a simulation for PCD-to-PICC,
+//           because there is no PICC model, it can not simulate PICC-to-PCD
+//--------------------------------------------------------------------------------------------------------
+
+`timescale 1ps/1ps
+
+module tb_nfca_controller ();
+
+initial $dumpvars(0, tb_nfca_controller);
+
+
+reg clk = 1'b0;
+always #6000 clk = ~clk;   // 81.36MHz approx.
+
+
+reg        tx_tvalid = 1'b0;
+wire       tx_tready;
+reg  [7:0] tx_tdata  = 0;
+reg  [3:0] tx_tdatab = 0;
+reg        tx_tlast  = 0;
+
+wire       carrier_out;
+
+
+nfca_controller nfca_controller_i (
+    .rstn          ( 1'b1              ),
+    .clk           ( clk               ),
+    .tx_tvalid     ( tx_tvalid         ),
+    .tx_tready     ( tx_tready         ),
+    .tx_tdata      ( tx_tdata          ),
+    .tx_tdatab     ( tx_tdatab         ),
+    .tx_tlast      ( tx_tlast          ),
+    .rx_on         (                   ),
+    .rx_tvalid     (                   ),
+    .rx_tdata      (                   ),
+    .rx_tdatab     (                   ),
+    .rx_tend       (                   ),
+    .rx_terr       (                   ),
+    .adc_data_en   ( 1'b0              ),
+    .adc_data      ( 12'h0             ),
+    .carrier_out   ( carrier_out       )
+);
+
+
+task tx_frame;
+    input [255:0] data_array;
+    input integer byte_len;
+    input [  3:0] datab;
+    integer ii;
+begin
+    $display("PCD-to-PICC: %d Bytes", byte_len);
+    {tx_tvalid, tx_tdata, tx_tdatab, tx_tlast} <= 0;
+    @ (posedge clk);
+    for (ii=0; ii<byte_len; ii=ii+1) begin
+        tx_tvalid <= 1'b1;
+        tx_tdata  <= data_array[8*ii+:8];
+        tx_tdatab <= ii+1 == byte_len ? datab : 4'd8;
+        tx_tlast  <= ii+1 == byte_len;
+        @ (posedge clk);
+        while(~tx_tready) @ (posedge clk);
+    end
+    {tx_tvalid, tx_tdata, tx_tdatab, tx_tlast} <= 0;
+end
+endtask
+
+
+initial begin
+    tx_frame(256'h00_00_00_26, 1, 4'd8);
+    tx_frame(256'h00_00_34_12, 2, 4'd8);
+    tx_frame(256'h00_12_34_12, 3, 4'd6);
+    tx_frame(256'h00_12_56_93, 3, 4'd7);
+    tx_frame(256'h34_12_56_93, 4, 4'd1);
+    tx_frame(256'h34_12_70_95, 4, 4'd8);
+    tx_frame(256'h34_12_6f_95, 4, 4'd8);
+    
+    @ (posedge clk);
+    while(~tx_tready) @ (posedge clk);
+    repeat(10000) @ (posedge clk);
+    $finish;
+end
+
+
+endmodule
+

aquaxis_IPCORE/README.md

@@ -0,0 +1,2 @@
+IPCORE
+======

aquaxis_IPCORE/aq_axi_djpeg/aq_axi_djpeg.model/cjpeg.c

@@ -0,0 +1,728 @@
+/*
+* Copyright (C)2005-2014 H.Ishihara
+*
+* License: The Open Software License 3.0
+* License URI: http://www.opensource.org/licenses/OSL-3.0
+*
+* For further information please contact.
+*	http://www.aquaxis.com/
+*	info(at)aquaxis.com or hidemi(at)sweetcafe.jp
+*/
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+static struct APP0infotype {
+  unsigned short int marker;           // = 0xFFE0
+  unsigned short int length;           // = 16 for usual JPEG, no thumbnail
+  unsigned char      JFIFsignature[5]; // = "JFIF",'\0'
+  unsigned char      versionhi;        // 1
+  unsigned char      versionlo;        // 1
+  unsigned char      xyunits;          // 0 = no units, normal density
+  unsigned short int xdensity;         // 1
+  unsigned short int ydensity;         // 1
+  unsigned char      thumbnwidth;      // 0
+  unsigned char      thumbnheight;     // 0
+} APP0info={0xFFE0,16,'J','F','I','F',0,1,1,0,1,1,0,0};
+
+static struct  SOF0infotype {
+  unsigned short int marker;         // = 0xFFC0
+  unsigned short int length;         // = 17 for a truecolor YCbCr JPG
+  unsigned char      precision ;     // Should be 8: 8 bits/sample
+  unsigned short int height ;
+  unsigned short int width;
+  unsigned char      nrofcomponents; //Should be 3: We encode a truecolor JPG
+  unsigned char      IdY;            // = 1
+  unsigned char      HVY;            // sampling factors for Y
+                                     // (bit 0-3 vert., 4-7 hor.)
+  unsigned char      QTY;            // Quantization Table number for Y = 0
+  unsigned char      IdCb;           // = 2
+  unsigned char      HVCb;
+  unsigned char      QTCb;           // 1
+  unsigned char      IdCr;           // = 3
+  unsigned char      HVCr;
+  unsigned char      QTCr;           // Normally equal to QTCb = 1
+} SOF0info = { 0xFFC0,17,8,0,0,3,1,0x22,0,2,0x11,1,3,0x11,1};
+// Default sampling factors are 1,1 for every image component: No downsampling
+
+static struct DQTinfotype {
+  unsigned short int marker;      // = 0xFFDB
+  unsigned short int length;      // = 132
+  unsigned char      QTYinfo;     // = 0:  bit 0..3: number of QT = 0 
+                                  // (table for Y)
+                                  //   bit 4..7: precision of QT, 0 = 8 bit
+  unsigned char      Ytable[64];
+  unsigned char      QTCbinfo;    // = 1 (quantization table for Cb,Cr}
+  unsigned char      Cbtable[64];
+} DQTinfo;
+// Ytable from DQTinfo should be equal to a scaled and zizag reordered version
+// of the table which can be found in "tables.h": std_luminance_qt
+// Cbtable , similar = std_chrominance_qt
+// We'll init them in the program using set_DQTinfo function
+
+static struct DHTinfotype {
+  unsigned short int marker;          // = 0xFFC4
+  unsigned short int length;          //0x01A2
+  unsigned char      HTYDCinfo;       // bit 0..3: number of HT (0..3), for Y =0
+                                      //bit 4  :type of HT, 0 = DC table,1 = AC table
+                                      //bit 5..7: not used, must be 0
+  unsigned char      YDC_nrcodes[16]; //at index i = nr of codes with length i
+  unsigned char      YDC_values[12];
+  unsigned char      HTYACinfo;        // = 0x10
+  unsigned char      YAC_nrcodes[16];
+  unsigned char      YAC_values[162];  //we'll use the standard Huffman tables
+  unsigned char      HTCbDCinfo;       // = 1
+  unsigned char      CbDC_nrcodes[16];
+  unsigned char      CbDC_values[12];
+  unsigned char      HTCbACinfo;       //  = 0x11
+  unsigned char      CbAC_nrcodes[16];
+  unsigned char      CbAC_values[162];
+} DHTinfo;
+
+static struct SOSinfotype {
+  unsigned short int marker;    // = 0xFFDA
+  unsigned short int length;    // = 12
+  unsigned char      nrofcomponents; // Should be 3: truecolor JPG
+  unsigned char      IdY;            //1
+  unsigned char      HTY;            //0 // bits 0..3: AC table (0..3)
+                                     // bits 4..7: DC table (0..3)
+  unsigned char      IdCb;           //2
+  unsigned char      HTCb;           //0x11
+  unsigned char      IdCr;           //3
+  unsigned char      HTCr;           //0x11
+  unsigned char      Ss,Se,Bf;       // not interesting, they should be 0,63,0
+} SOSinfo={0xFFDA,12,3,1,0,2,0x11,3,0x11,0,0x3F,0};
+
+typedef struct { unsigned char length;  unsigned short int value;} bitstring;
+
+#define  Y(R,G,B) ((unsigned char)( (YRtab[(R)]+YGtab[(G)]+YBtab[(B)])>>16 ) - 128)
+#define Cb(R,G,B) ((unsigned char)( (CbRtab[(R)]+CbGtab[(G)]+CbBtab[(B)])>>16 ) )
+#define Cr(R,G,B) ((unsigned char)( (CrRtab[(R)]+CrGtab[(G)]+CrBtab[(B)])>>16 ) )
+
+#define writebyte(b) fputc((b),fp_jpeg_stream)
+#define writeword(w) writebyte((w)/256);writebyte((w)%256);
+
+static unsigned char zigzag[64]={
+  0, 1, 5, 6,14,15,27,28,
+  2, 4, 7,13,16,26,29,42,
+  3, 8,12,17,25,30,41,43,
+  9,11,18,24,31,40,44,53,
+  10,19,23,32,39,45,52,54,
+  20,22,33,38,46,51,55,60,
+  21,34,37,47,50,56,59,61,
+  35,36,48,49,57,58,62,63 
+};
+
+/* These are the sample quantization tables given in JPEG spec section K.1.
+   The spec says that the values given produce "good" quality, and
+   when divided by 2, "very good" quality.*/
+static unsigned char DQT_Y[64] = {
+  0x08, 0x06, 0x06, 0x07, 0x06, 0x05, 0x08, 0x07,
+  0x07, 0x07, 0x09, 0x09, 0x08, 0x0a, 0x0c, 0x14,
+  0x0d, 0x0c, 0x0b, 0x0b, 0x0c, 0x19, 0x12, 0x13,
+  0x0f, 0x14, 0x1d, 0x1a, 0x1f, 0x1e, 0x1d, 0x1a,
+  0x1c, 0x1c, 0x20, 0x24, 0x2e, 0x27, 0x20, 0x22,
+  0x2c, 0x23, 0x1c, 0x1c, 0x28, 0x37, 0x29, 0x2c,
+  0x30, 0x31, 0x34, 0x34, 0x34, 0x1f, 0x27, 0x39,
+  0x3d, 0x38, 0x32, 0x3c, 0x2e, 0x33, 0x34, 0x32
+};
+
+static unsigned char DQT_C[64] = {
+  0x09, 0x09, 0x09, 0x0c, 0x0b, 0x0c, 0x18, 0x0d,
+  0x0d, 0x18, 0x32, 0x21, 0x1c, 0x21, 0x32, 0x32,
+  0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32,
+  0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 
+  0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32,
+  0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32,
+  0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32,
+  0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32, 0x32
+};
+
+static unsigned char std_luminance_qt[64] = {
+  16,  11,  10,  16,  24,  40,  51,  61,
+  12,  12,  14,  19,  26,  58,  60,  55,
+  14,  13,  16,  24,  40,  57,  69,  56,
+  14,  17,  22,  29,  51,  87,  80,  62,
+  18,  22,  37,  56,  68, 109, 103,  77,
+  24,  35,  55,  64,  81, 104, 113,  92,
+  49,  64,  78,  87, 103, 121, 120, 101,
+  72,  92,  95,  98, 112, 100, 103,  99
+};
+static unsigned char std_chrominance_qt[64] = {
+  17,  18,  24,  47,  99,  99,  99,  99,
+  18,  21,  26,  66,  99,  99,  99,  99,
+  24,  26,  56,  99,  99,  99,  99,  99,
+  47,  66,  99,  99,  99,  99,  99,  99,
+  99,  99,  99,  99,  99,  99,  99,  99,
+  99,  99,  99,  99,  99,  99,  99,  99,
+  99,  99,  99,  99,  99,  99,  99,  99,
+  99,  99,  99,  99,  99,  99,  99,  99
+};
+// Standard Huffman tables (cf. JPEG standard section K.3) */
+
+static unsigned char std_dc_luminance_nrcodes[17]={0,0,1,5,1,1,1,1,1,1,0,0,0,0,0,0,0};
+static unsigned char std_dc_luminance_values[12]={0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11};
+
+static unsigned char std_dc_chrominance_nrcodes[17]={0,0,3,1,1,1,1,1,1,1,1,1,0,0,0,0,0};
+static unsigned char std_dc_chrominance_values[12]={0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11};
+
+static unsigned char std_ac_luminance_nrcodes[17]={0,0,2,1,3,3,2,4,3,5,5,4,4,0,0,1,0x7d };
+static unsigned char std_ac_luminance_values[162]= {
+  0x01, 0x02, 0x03, 0x00, 0x04, 0x11, 0x05, 0x12,
+  0x21, 0x31, 0x41, 0x06, 0x13, 0x51, 0x61, 0x07,
+  0x22, 0x71, 0x14, 0x32, 0x81, 0x91, 0xa1, 0x08,
+  0x23, 0x42, 0xb1, 0xc1, 0x15, 0x52, 0xd1, 0xf0,
+  0x24, 0x33, 0x62, 0x72, 0x82, 0x09, 0x0a, 0x16,
+  0x17, 0x18, 0x19, 0x1a, 0x25, 0x26, 0x27, 0x28,
+  0x29, 0x2a, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39,
+  0x3a, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49,
+  0x4a, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59,
+  0x5a, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69,
+  0x6a, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79,
+  0x7a, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88, 0x89,
+  0x8a, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98,
+  0x99, 0x9a, 0xa2, 0xa3, 0xa4, 0xa5, 0xa6, 0xa7,
+  0xa8, 0xa9, 0xaa, 0xb2, 0xb3, 0xb4, 0xb5, 0xb6,
+  0xb7, 0xb8, 0xb9, 0xba, 0xc2, 0xc3, 0xc4, 0xc5,
+  0xc6, 0xc7, 0xc8, 0xc9, 0xca, 0xd2, 0xd3, 0xd4,
+  0xd5, 0xd6, 0xd7, 0xd8, 0xd9, 0xda, 0xe1, 0xe2,
+  0xe3, 0xe4, 0xe5, 0xe6, 0xe7, 0xe8, 0xe9, 0xea,
+  0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, 0xf8,
+  0xf9, 0xfa };
+
+static unsigned char std_ac_chrominance_nrcodes[17]={0,0,2,1,2,4,4,3,4,7,5,4,4,0,1,2,0x77};
+static unsigned char std_ac_chrominance_values[162]={
+  0x00, 0x01, 0x02, 0x03, 0x11, 0x04, 0x05, 0x21,
+  0x31, 0x06, 0x12, 0x41, 0x51, 0x07, 0x61, 0x71,
+  0x13, 0x22, 0x32, 0x81, 0x08, 0x14, 0x42, 0x91,
+  0xa1, 0xb1, 0xc1, 0x09, 0x23, 0x33, 0x52, 0xf0,
+  0x15, 0x62, 0x72, 0xd1, 0x0a, 0x16, 0x24, 0x34,
+  0xe1, 0x25, 0xf1, 0x17, 0x18, 0x19, 0x1a, 0x26,
+  0x27, 0x28, 0x29, 0x2a, 0x35, 0x36, 0x37, 0x38,
+  0x39, 0x3a, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48,
+  0x49, 0x4a, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58,
+  0x59, 0x5a, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68,
+  0x69, 0x6a, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78,
+  0x79, 0x7a, 0x82, 0x83, 0x84, 0x85, 0x86, 0x87,
+  0x88, 0x89, 0x8a, 0x92, 0x93, 0x94, 0x95, 0x96,
+  0x97, 0x98, 0x99, 0x9a, 0xa2, 0xa3, 0xa4, 0xa5,
+  0xa6, 0xa7, 0xa8, 0xa9, 0xaa, 0xb2, 0xb3, 0xb4,
+  0xb5, 0xb6, 0xb7, 0xb8, 0xb9, 0xba, 0xc2, 0xc3,
+  0xc4, 0xc5, 0xc6, 0xc7, 0xc8, 0xc9, 0xca, 0xd2,
+  0xd3, 0xd4, 0xd5, 0xd6, 0xd7, 0xd8, 0xd9, 0xda,
+  0xe2, 0xe3, 0xe4, 0xe5, 0xe6, 0xe7, 0xe8, 0xe9,
+  0xea, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, 0xf8,
+  0xf9, 0xfa };
+
+static unsigned char bytenew=0; // The byte that will be written in the JPG file
+static signed char bytepos=7; //bit position in the byte we write (bytenew)
+			//should be<=7 and >=0
+static unsigned short int mask[16]={1,2,4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384,32768};
+
+// The Huffman tables we'll use:
+static bitstring YDC_HT[12];
+static bitstring CbDC_HT[12];
+static bitstring YAC_HT[256];
+static bitstring CbAC_HT[256];
+
+static unsigned char *category_alloc;
+static unsigned char *category; //Here we'll keep the category of the numbers in range: -32767..32767
+static bitstring *bitcode_alloc;
+static bitstring *bitcode; // their bitcoded representation
+
+static unsigned char *buffer; //image to be encoded
+unsigned short int Ximage,Yimage;// image dimensions divisible by 8
+
+// Data Unit YCbCr
+static signed char DU_Y[256];
+static signed char DU_Cb[64];
+static signed char DU_Cr[64];
+
+static signed short int DU_DCT[64]; // Current DU (after DCT and quantization) which we'll zigzag
+
+static signed short int DU[64]; //zigzag reordered DU which will be Huffman coded
+
+FILE *fp_jpeg_stream;
+
+void write_APP0info(){
+//Nothing to overwrite for APP0info
+  writeword(APP0info.marker);
+  writeword(APP0info.length);
+  writebyte('J');writebyte('F');writebyte('I');writebyte('F');writebyte(0);
+  writebyte(APP0info.versionhi);
+  writebyte(APP0info.versionlo);
+  writebyte(APP0info.xyunits);
+  writeword(APP0info.xdensity);
+  writeword(APP0info.ydensity);
+  writebyte(APP0info.thumbnwidth);
+  writebyte(APP0info.thumbnheight);
+}
+
+void write_SOF0info(){
+// We should overwrite width and height
+  writeword(SOF0info.marker);
+  writeword(SOF0info.length);
+  writebyte(SOF0info.precision);
+  writeword(SOF0info.height);
+  writeword(SOF0info.width);
+  writebyte(SOF0info.nrofcomponents);
+  writebyte(SOF0info.IdY);
+  writebyte(SOF0info.HVY);
+  writebyte(SOF0info.QTY);
+  writebyte(SOF0info.IdCb);
+  writebyte(SOF0info.HVCb);
+  writebyte(SOF0info.QTCb);
+  writebyte(SOF0info.IdCr);
+  writebyte(SOF0info.HVCr);
+  writebyte(SOF0info.QTCr);
+}
+
+void write_DQTinfo(){
+  unsigned char i;
+  writeword(DQTinfo.marker);
+  writeword(DQTinfo.length);
+  writebyte(DQTinfo.QTYinfo);
+  for (i=0;i<64;i++) writebyte(DQTinfo.Ytable[i]);
+  writebyte(DQTinfo.QTCbinfo);
+  for (i=0;i<64;i++) writebyte(DQTinfo.Cbtable[i]);
+}
+
+void set_DQTinfo(){
+  int i;
+  DQTinfo.marker=0xFFDB;
+  DQTinfo.length=132;
+  DQTinfo.QTYinfo=0;
+  DQTinfo.QTCbinfo=1;
+  for(i=0;i<64;i++) DQTinfo.Ytable[i]  = DQT_Y[i];
+  for(i=0;i<64;i++) DQTinfo.Cbtable[i] = DQT_C[i];
+}
+
+void write_DHTinfo(){
+  unsigned char i;
+  writeword(DHTinfo.marker);
+  writeword(DHTinfo.length);
+  writebyte(DHTinfo.HTYDCinfo);
+  for (i=0;i<16;i++)  writebyte(DHTinfo.YDC_nrcodes[i]);
+  for (i=0;i<=11;i++) writebyte(DHTinfo.YDC_values[i]);
+  writebyte(DHTinfo.HTYACinfo);
+  for (i=0;i<16;i++)  writebyte(DHTinfo.YAC_nrcodes[i]);
+  for (i=0;i<=161;i++) writebyte(DHTinfo.YAC_values[i]);
+  writebyte(DHTinfo.HTCbDCinfo);
+  for (i=0;i<16;i++)  writebyte(DHTinfo.CbDC_nrcodes[i]);
+  for (i=0;i<=11;i++)  writebyte(DHTinfo.CbDC_values[i]);
+  writebyte(DHTinfo.HTCbACinfo);
+  for (i=0;i<16;i++)  writebyte(DHTinfo.CbAC_nrcodes[i]);
+  for (i=0;i<=161;i++) writebyte(DHTinfo.CbAC_values[i]);
+}
+
+void set_DHTinfo(){
+  unsigned char i;
+  DHTinfo.marker=0xFFC4;
+  DHTinfo.length=0x01A2;
+  DHTinfo.HTYDCinfo=0;
+  for (i=0;i<16;i++)  DHTinfo.YDC_nrcodes[i]=std_dc_luminance_nrcodes[i+1];
+  for (i=0;i<=11;i++)  DHTinfo.YDC_values[i]=std_dc_luminance_values[i];
+  DHTinfo.HTYACinfo=0x10;
+  for (i=0;i<16;i++)  DHTinfo.YAC_nrcodes[i]=std_ac_luminance_nrcodes[i+1];
+  for (i=0;i<=161;i++) DHTinfo.YAC_values[i]=std_ac_luminance_values[i];
+  DHTinfo.HTCbDCinfo=1;
+  for (i=0;i<16;i++)  DHTinfo.CbDC_nrcodes[i]=std_dc_chrominance_nrcodes[i+1];
+  for (i=0;i<=11;i++)  DHTinfo.CbDC_values[i]=std_dc_chrominance_values[i];
+  DHTinfo.HTCbACinfo=0x11;
+  for (i=0;i<16;i++)  DHTinfo.CbAC_nrcodes[i]=std_ac_chrominance_nrcodes[i+1];
+  for (i=0;i<=161;i++) DHTinfo.CbAC_values[i]=std_ac_chrominance_values[i];
+}
+
+void write_SOSinfo(){
+  //Nothing to overwrite for SOSinfo
+  writeword(SOSinfo.marker);
+  writeword(SOSinfo.length);
+  writebyte(SOSinfo.nrofcomponents);
+  writebyte(SOSinfo.IdY);
+  writebyte(SOSinfo.HTY);
+  writebyte(SOSinfo.IdCb);
+  writebyte(SOSinfo.HTCb);
+  writebyte(SOSinfo.IdCr);
+  writebyte(SOSinfo.HTCr);
+  writebyte(SOSinfo.Ss);
+  writebyte(SOSinfo.Se);
+  writebyte(SOSinfo.Bf);
+}
+
+void writebits(bitstring bs){
+  unsigned short int value;
+  signed char posval;
+  value=bs.value;
+  posval=bs.length-1;
+  while(posval>=0){
+    if(value & mask[posval]) bytenew|=mask[bytepos];
+    posval--;bytepos--;
+    if(bytepos<0) {
+      if(bytenew==0xFF) {
+	writebyte(0xFF);
+	writebyte(0);
+      }else{
+	writebyte(bytenew);
+      }
+      bytepos=7;
+      bytenew=0;
+    }
+  }
+}
+
+void compute_Huffman_table(unsigned char *nrcodes,unsigned char *std_table,bitstring *HT){
+  unsigned char k,j;
+  unsigned char pos_in_table;
+  unsigned short int codevalue;
+  codevalue=0; pos_in_table=0;
+  for (k=1;k<=16;k++){
+    for (j=1;j<=nrcodes[k];j++) {
+      HT[std_table[pos_in_table]].value=codevalue;
+      HT[std_table[pos_in_table]].length=k;
+      pos_in_table++;
+      codevalue++;
+    }
+    codevalue*=2;
+  }
+}
+void init_Huffman_tables(){
+  compute_Huffman_table(std_dc_luminance_nrcodes,std_dc_luminance_values,YDC_HT);
+  compute_Huffman_table(std_dc_chrominance_nrcodes,std_dc_chrominance_values,CbDC_HT);
+  compute_Huffman_table(std_ac_luminance_nrcodes,std_ac_luminance_values,YAC_HT);
+  compute_Huffman_table(std_ac_chrominance_nrcodes,std_ac_chrominance_values,CbAC_HT);
+}
+
+void set_numbers_category_and_bitcode(){
+  signed long int nr;
+  signed long int nrlower,nrupper;
+  unsigned char cat,value;
+  
+  category_alloc=(unsigned char *)malloc(65535*sizeof(unsigned char));
+  category=category_alloc+32767; //allow negative subscripts
+  bitcode_alloc=(bitstring *)malloc(65535*sizeof(bitstring));
+  bitcode=bitcode_alloc+32767;
+  nrlower=1;nrupper=2;
+  for (cat=1;cat<=15;cat++) {
+    //Positive numbers
+    for (nr=nrlower;nr<nrupper;nr++){
+      category[nr]=cat;
+      bitcode[nr].length=cat;
+      bitcode[nr].value=(unsigned short int)nr;
+    }
+    //Negative numbers
+    for (nr=-(nrupper-1);nr<=-nrlower;nr++){
+      category[nr]=cat;
+      bitcode[nr].length=cat;
+      bitcode[nr].value=(unsigned short int)(nrupper-1+nr);
+    }
+    nrlower<<=1;
+    nrupper<<=1;
+  }
+}
+
+void DCT(signed char *data,unsigned char *fdtbl,signed short int *outdata){
+  double aanscalefactor[8] = {1.0, 1.387039845, 1.306562965, 1.175875602,
+			      1.0, 0.785694958, 0.541196100, 0.275899379};
+  float tmp0, tmp1, tmp2, tmp3, tmp4, tmp5, tmp6, tmp7;
+  float tmp10, tmp11, tmp12, tmp13, tmp14, tmp15, tmp16, tmp17, tmp18, tmp19;
+  float z1, z2, z3, z4, z5, z11, z13;
+  float *dataptr;
+  float datafloat[64];
+  float temp;
+  signed char ctr;
+  unsigned char i;
+  for (i=0;i<64;i++) datafloat[i]=data[i];
+
+  /* Pass 1: process rows. */
+  dataptr=datafloat;
+  for (ctr = 7; ctr >= 0; ctr--) {
+    tmp0 = dataptr[0] + dataptr[7];
+    tmp7 = dataptr[0] - dataptr[7];
+    tmp1 = dataptr[1] + dataptr[6];
+    tmp6 = dataptr[1] - dataptr[6];
+    tmp2 = dataptr[2] + dataptr[5];
+    tmp5 = dataptr[2] - dataptr[5];
+    tmp3 = dataptr[3] + dataptr[4];
+    tmp4 = dataptr[3] - dataptr[4];
+
+    // Phase 2
+    tmp10 = tmp0 + tmp3;
+    tmp13 = tmp0 - tmp3;
+    tmp11 = tmp1 + tmp2;
+    tmp12 = tmp1 - tmp2;
+    tmp14 = (tmp4 + tmp5) * ((float) 0.923879533);
+    tmp15 = (tmp4 + tmp5) * ((float) 0.382683432);
+    tmp16 = (tmp6 + tmp7) * ((float) 0.382683432);
+    tmp17 = (tmp6 + tmp7) * ((float) 0.923879533) ;
+    tmp18 = tmp7;
+    tmp19 = (tmp5 + tmp6) * ((float) 0.707106781);
+
+    // Phase 3
+    dataptr[0] = (tmp10 + tmp11) / aanscalefactor[0];
+    dataptr[4] = (tmp10 - tmp11) / aanscalefactor[1];
+    z1  = (tmp12 + tmp13) * ((float) 0.707106781);
+    z2  = tmp14 - tmp16;
+    z4  = tmp15 + tmp17;
+    z11 = tmp18 + tmp19;
+    z13 = tmp18 - tmp19;
+
+    // Phase 4
+    dataptr[2] = (tmp13 + z1) / aanscalefactor[2];
+    dataptr[6] = (tmp13 - z1) / aanscalefactor[6];
+    dataptr[5] = (z13 + z2) / aanscalefactor[5];
+    dataptr[3] = (z13 - z2) / aanscalefactor[3];
+    dataptr[1] = (z11 + z4) / aanscalefactor[1];
+    dataptr[7] = (z11 - z4) / aanscalefactor[7];
+
+    dataptr += 8;
+  }
+
+  /* Pass 2: process columns. */
+
+  dataptr -= 64;
+  for (ctr = 7; ctr >= 0; ctr--) {
+    tmp0 = dataptr[0] + dataptr[56];
+    tmp7 = dataptr[0] - dataptr[56];
+    tmp1 = dataptr[8] + dataptr[48];
+    tmp6 = dataptr[8] - dataptr[48];
+    tmp2 = dataptr[16] + dataptr[40];
+    tmp5 = dataptr[16] - dataptr[40];
+    tmp3 = dataptr[24] + dataptr[32];
+    tmp4 = dataptr[24] - dataptr[32];
+
+    // Phase 2
+    tmp10 = tmp0 + tmp3;
+    tmp13 = tmp0 - tmp3;
+    tmp11 = tmp1 + tmp2;
+    tmp12 = tmp1 - tmp2;
+    tmp14 = (tmp4 + tmp5) * ((float) 0.923879533);
+    tmp15 = (tmp4 + tmp5) * ((float) 0.382683432);
+    tmp16 = (tmp6 + tmp7) * ((float) 0.382683432);
+    tmp17 = (tmp6 + tmp7) * ((float) 0.923879533) ;
+    tmp18 = tmp7;
+    tmp19 = (tmp5 + tmp6) * ((float) 0.707106781);
+
+    // Phase 3
+    dataptr[ 0] = (tmp10 + tmp11) / aanscalefactor[0];
+    dataptr[32] = (tmp10 - tmp11) / aanscalefactor[1];
+    z1  = (tmp12 + tmp13) * ((float) 0.707106781);
+    z2  = tmp14 - tmp16;
+    z4  = tmp15 + tmp17;
+    z11 = tmp18 + tmp19;
+    z13 = tmp18 - tmp19;
+
+    // Phase 4
+    dataptr[16] = (tmp13 + z1) / aanscalefactor[2];
+    dataptr[48] = (tmp13 - z1) / aanscalefactor[6];
+    dataptr[40] = (z13 + z2) / aanscalefactor[5];
+    dataptr[24] = (z13 - z2) / aanscalefactor[3];
+    dataptr[ 8] = (z11 + z4) / aanscalefactor[1];
+    dataptr[56] = (z11 - z4) / aanscalefactor[7];
+
+    dataptr ++;
+  }
+
+  // DQT
+  for (i = 0; i < 64; i++) {
+    temp = datafloat[i] / (float)((double) fdtbl[zigzag[i]] * 8.0);
+    outdata[i] = (signed short int) ((signed short int)(temp + 16384.5) - 16384);
+  }
+}
+
+void process_DU(signed char *ComponentDU,unsigned char *fdtbl,
+		signed short int *DC,
+		bitstring *HTDC,bitstring *HTAC){
+  unsigned char i;
+  unsigned char startpos;
+  unsigned char end0pos;
+  unsigned char nrzeroes;
+  unsigned char nrmarker;
+  signed short int Diff;
+  
+  DCT(ComponentDU,fdtbl,DU_DCT);
+  // ��������
+  for (i=0;i<=63;i++) DU[zigzag[i]]=DU_DCT[i];
+  Diff=DU[0]-*DC;
+  *DC=DU[0];
+  // DC��ʬ�Υ��󥳡���
+  if (Diff==0) writebits(HTDC[0]); //Diff might be 0
+  else {
+    writebits(HTDC[category[Diff]]);
+    writebits(bitcode[Diff]);
+  }
+  // AC��ʬ�Υ��󥳡���
+  // 0�ο���դ��������
+  for (end0pos=63;(end0pos>0)&&(DU[end0pos]==0);end0pos--) ;
+  if (end0pos==0) {
+    // ����0�ʤ�EOB(����ɥ��֥֥��å�)��񤭹���
+    writebits(HTAC[0x00]);
+    return;
+  }
+  
+  i=1;
+  while (i<=end0pos){
+    startpos=i;
+    for (; (DU[i]==0)&&(i<=end0pos);i++) ;
+    nrzeroes=i-startpos;
+    if (nrzeroes>=16) {
+      // 0��16�İʾ�³������0��16�ĥ����ɤ���Ϥ���
+      for (nrmarker=1;nrmarker<=nrzeroes/16;nrmarker++) writebits(HTAC[0xF0]);
+      nrzeroes=nrzeroes%16;
+    }
+    writebits(HTAC[nrzeroes*16+category[DU[i]]]);
+    writebits(bitcode[DU[i]]);
+    i++;
+  }
+  if (end0pos!=63) writebits(HTAC[0x00]); // �Ĥ꤬���ʤ�EOB
+}
+
+void RGB2YCbCr(unsigned short int xpos,unsigned short int ypos){
+  unsigned char x,y;
+  unsigned char R,G,B;
+  for(y=0;y<16;y++){
+    for(x=0;x<16;x++){
+      R=buffer[ypos*Ximage*3+xpos*3+y*Ximage*3+x*3+2];
+      G=buffer[ypos*Ximage*3+xpos*3+y*Ximage*3+x*3+1];
+      B=buffer[ypos*Ximage*3+xpos*3+y*Ximage*3+x*3+0];
+      DU_Y[y*16+x]  = (unsigned char)(0.299 *R + 0.587 *G + 0.114 *B) -128;
+      if(x%2==0 & y%2==0){
+	DU_Cb[y/2*8+x/2] = (unsigned char)(0.5 *B - 0.33126 *G - 0.16874 *R);
+	DU_Cr[y/2*8+x/2] = (unsigned char)(0.5 *R - 0.41869 *G - 0.08131 *B);
+      }
+    }
+  }
+}
+
+void main_encoder(){
+  signed short int DCY=0,DCCb=0,DCCr=0;
+  unsigned short int xpos,ypos;
+  signed char DU[64];
+  int i;
+  for (ypos=0;ypos<Yimage;ypos+=16){
+    for (xpos=0;xpos<Ximage;xpos+=16){
+      RGB2YCbCr(xpos,ypos);
+      for(i=0;i<64;i++) DU[i] = DU_Y[(i/8)*16+i%8+0];
+      process_DU(DU,DQTinfo.Ytable,&DCY,YDC_HT,YAC_HT);
+      for(i=0;i<64;i++) DU[i] = DU_Y[(i/8)*16+i%8+8];
+      process_DU(DU,DQTinfo.Ytable,&DCY,YDC_HT,YAC_HT);
+      for(i=0;i<64;i++) DU[i] = DU_Y[(i/8)*16+i%8+128];
+      process_DU(DU,DQTinfo.Ytable,&DCY,YDC_HT,YAC_HT);
+      for(i=0;i<64;i++) DU[i] = DU_Y[(i/8)*16+i%8+136];
+      process_DU(DU,DQTinfo.Ytable,&DCY,YDC_HT,YAC_HT);
+      process_DU(DU_Cb,DQTinfo.Cbtable,&DCCb,CbDC_HT,CbAC_HT);
+      process_DU(DU_Cr,DQTinfo.Cbtable,&DCCr,CbDC_HT,CbAC_HT);
+    }
+  }
+}
+
+void load_bitmap(char *bitmap_name, unsigned short int *Ximage_original, unsigned short int *Yimage_original){
+  unsigned short int Xdiv8,Ydiv8;
+  unsigned char nr_fillingbytes;//The number of the filling bytes in the BMP file
+  unsigned int offset;
+  // (the dimension in bytes of a BMP line on the disk is divisible by 4)
+  unsigned char lastcolor[3];
+  unsigned short int column;
+  unsigned char TMPBUF[256];
+  unsigned short int nrline_up,nrline_dn,nrline;
+  unsigned short int dimline;
+  unsigned char *tmpline;
+  FILE *fp_bitmap=fopen(bitmap_name,"rb");
+  fread(TMPBUF,1,54,fp_bitmap);
+  Ximage=(unsigned short int)TMPBUF[19]*256+TMPBUF[18];Yimage=(unsigned short int)TMPBUF[23]*256+TMPBUF[22];
+  *Ximage_original=Ximage;
+  *Yimage_original=Yimage; //Keep the old dimensions of the image
+  if (Ximage%16!=0) Xdiv8=(Ximage/16)*16+16;
+  else Xdiv8=Ximage;
+  if (Yimage%16!=0) Ydiv8=(Yimage/16)*16+16;
+  else Ydiv8=Yimage;
+
+  offset = TMPBUF[10];
+  if(offset > 54){
+    offset -= 51;
+    fread(TMPBUF,1,offset,fp_bitmap);
+  }
+
+  // The image we encode shall be filled with the last line and the last column
+  // from the original bitmap, until Ximage and Yimage are divisible by 8
+  // Load BMP image from disk and complete X
+  buffer=(unsigned char *)(malloc(3*Xdiv8*Ydiv8));
+  if (Ximage%4!=0) nr_fillingbytes=4-(Ximage%4);
+  else nr_fillingbytes=0;
+  for (nrline=0;nrline<Yimage;nrline++){
+    fread(buffer+nrline*Xdiv8*3,1,Ximage*3,fp_bitmap);
+    fread(TMPBUF,1,nr_fillingbytes,fp_bitmap);
+    memcpy(&lastcolor,buffer+nrline*Xdiv8*3+Ximage*3-1,3);
+    for (column=Ximage;column<Xdiv8;column++){
+      memcpy(buffer+nrline*Xdiv8*3+column,&lastcolor,3);
+    }
+  }
+  Ximage=Xdiv8;
+  dimline=Ximage*3;
+  tmpline=(unsigned char *)malloc(dimline);
+
+  //Reorder in memory the inversed bitmap
+  for (nrline_up=Yimage-1,nrline_dn=0;nrline_up>nrline_dn;nrline_up--,nrline_dn++){
+    memcpy(tmpline,buffer+nrline_up*Ximage*3, dimline);
+    memcpy(buffer+nrline_up*Ximage*3,buffer+nrline_dn*Ximage*3,dimline);
+    memcpy(buffer+nrline_dn*Ximage*3,tmpline,dimline);
+  }
+
+  // Y completion:
+  memcpy(tmpline,buffer+(Yimage-1)*Ximage*3,dimline);
+  for (nrline=Yimage;nrline<Ydiv8;nrline++){
+    memcpy(buffer+nrline*Ximage*3,tmpline,dimline);
+  }
+  Yimage=Ydiv8;
+  free(tmpline);fclose(fp_bitmap);
+}
+
+void init_all(){
+  set_DQTinfo();
+  set_DHTinfo();
+  init_Huffman_tables();
+  set_numbers_category_and_bitcode();
+}
+
+int main(int argc,char *argv[]){
+  char BMP_filename[64];
+  char JPG_filename[64];
+  unsigned short int Ximage_original,Yimage_original; //the original image dimensions,
+  // before we made them divisible by 8
+  unsigned char len_filename;
+  bitstring fillbits; //filling bitstring for the bit alignment of the EOI marker
+  if (argc>1) { strcpy(BMP_filename,argv[1]);
+    if (argc>2) strcpy(JPG_filename,argv[2]);
+    else{
+      strcpy(JPG_filename,BMP_filename);
+      len_filename=strlen(BMP_filename);
+      strcpy(JPG_filename+(len_filename-3),"jpg");
+    }
+  }
+  load_bitmap(BMP_filename, &Ximage_original, &Yimage_original);
+  fp_jpeg_stream=fopen(JPG_filename,"wb");
+  init_all();
+  SOF0info.width=Ximage_original;
+  SOF0info.height=Yimage_original;
+
+  writeword(0xFFD8); //SOI
+
+  write_APP0info();
+  write_DQTinfo();
+  write_SOF0info();
+  write_DHTinfo();
+  write_SOSinfo();
+  
+  bytenew=0;bytepos=7;
+  main_encoder();
+  //Do the bit alignment of the EOI marker
+  if(bytepos>=0){
+    fillbits.length=bytepos+1;
+    fillbits.value=(1<<(bytepos+1))-1;
+    writebits(fillbits);
+  }
+  writeword(0xFFD9); //EOI
+  free(buffer);
+  free(category_alloc);
+  free(bitcode_alloc);
+  fclose(fp_jpeg_stream);
+}

aquaxis_IPCORE/aq_axi_djpeg/aq_axi_djpeg.model/convbtoh.c

@@ -0,0 +1,41 @@
+/*
+* Copyright (C)2005-2014 H.Ishihara
+*
+* License: The Open Software License 3.0
+* License URI: http://www.opensource.org/licenses/OSL-3.0
+*
+* For further information please contact.
+*	http://www.aquaxis.com/
+*	info(at)aquaxis.com or hidemi(at)sweetcafe.jp
+*/
+//////////////////////////////////////////////////////////////////////////////
+#include <stdio.h>
+#include <stdlib.h>
+
+//////////////////////////////////////////////////////////////////////////////
+// ���C���֐�
+//////////////////////////////////////////////////////////////////////////////
+int main(int argc, char *argv[])
+{
+  unsigned char buff[4];
+  char data[256];
+  FILE *rfp,*wfp;
+
+  if((rfp = fopen(argv[1],"rb")) == NULL){
+    perror(0);
+    exit(0);
+  }
+  if((wfp = fopen(argv[2],"wb")) == NULL){
+    perror(0);
+    exit(0);
+  }
+  while(!feof(rfp)){
+    fread(buff,1,4,rfp);
+    sprintf(data,"%02X%02X%02X%02X\n",buff[3],buff[2],buff[1],buff[0]);
+    fwrite(data,1,9,wfp);
+  }
+  fclose(rfp);
+  fclose(wfp);
+
+  return 0;
+}

aquaxis_IPCORE/aq_axi_djpeg/aq_axi_djpeg.model/convsim.c

@@ -0,0 +1,118 @@
+/*
+* Copyright (C)2005-2014 H.Ishihara
+*
+* License: The Open Software License 3.0
+* License URI: http://www.opensource.org/licenses/OSL-3.0
+*
+* For further information please contact.
+*	http://www.aquaxis.com/
+*	info(at)aquaxis.com or hidemi(at)sweetcafe.jp
+*/
+//////////////////////////////////////////////////////////////////////////////
+#include <stdio.h>
+#include <stdlib.h>
+
+typedef unsigned short WORD;
+typedef unsigned int DWORD;
+typedef int LONG;
+
+typedef struct tagBITMAPINFOHEADER{
+  DWORD  biSize;
+  LONG   biWidth;
+  LONG   biHeight;
+  WORD   biPlanes;
+  WORD   biBitCount;
+  DWORD  biCompression;
+  DWORD  biSizeImage;
+  LONG   biXPelsPerMeter;
+  LONG   biYPelsPerMeter;
+  DWORD  biClrUsed;
+  DWORD  biClrImportant;
+} BITMAPINFOHEADER, *PBITMAPINFOHEADER;
+
+//////////////////////////////////////////////////////////////////////////////
+// メイン関数
+//////////////////////////////////////////////////////////////////////////////
+int main(int argc, char *argv[])
+{
+  unsigned char buff[4];
+  char data[256];
+  FILE *rfp,*wfp;
+
+  unsigned long width;
+  unsigned long height;
+  unsigned long bitdata;
+  unsigned char tbuff[4];
+  BITMAPINFOHEADER lpBi;
+
+  unsigned char *image;
+  unsigned int i;
+
+  if((rfp = fopen(argv[1],"rb")) == NULL){
+    perror(0);
+    exit(0);
+  }
+
+  if((wfp = fopen(argv[2],"wb")) == NULL){
+    perror(0);
+    exit(0);
+  }
+ 
+
+  fgets(data,256,rfp);
+  width = (unsigned int)strtol(data,NULL,10);
+  fgets(data,256,rfp);
+  height = (unsigned int)strtol(data,NULL,10);
+
+  image = (unsigned char *)malloc(height*width*3);
+
+  // ファイルヘッダの設定
+  tbuff[0] = 'B';
+  tbuff[1] = 'M';
+  fwrite(tbuff,2,1,wfp);
+  tbuff[3] = ((14 +40 +width * height * 3) >> 24) & 0xff;
+  tbuff[2] = ((14 +40 +width * height * 3) >> 16) & 0xff;
+  tbuff[1] = ((14 +40 +width * height * 3) >>  8) & 0xff;
+  tbuff[0] = ((14 +40 +width * height * 3) >>  0) & 0xff;
+  fwrite(tbuff,4,1,wfp);
+  tbuff[1] = 0;
+  tbuff[0] = 0;
+  fwrite(tbuff,2,1,wfp);
+  fwrite(tbuff,2,1,wfp);
+  tbuff[3] = 0;
+  tbuff[2] = 0;
+  tbuff[1] = 0;
+  tbuff[0] = 54;
+  fwrite(tbuff,4,1,wfp);
+
+  // インフォメーションの設定
+  lpBi.biSize            = 40;
+  lpBi.biWidth           = width;
+  lpBi.biHeight          = height;
+  lpBi.biPlanes          = 1;
+  lpBi.biBitCount        = 3*8;
+  lpBi.biCompression     = 0;
+  lpBi.biSizeImage       = width*height*3;
+  lpBi.biXPelsPerMeter   = 300;
+  lpBi.biYPelsPerMeter   = 300;
+  lpBi.biClrUsed         = 0;
+  lpBi.biClrImportant    = 0;
+  fwrite(&lpBi,1,40,wfp);
+
+  i = 0;
+  while(!feof(rfp)){
+    if(i>=width*height) break;
+    fgets(data,256,rfp);
+    bitdata=strtol(data,NULL,16);
+    image[((height-i/width-1)*width*3)+(i%width)*3+0] = (bitdata >>  0) & 0xff;
+    image[((height-i/width-1)*width*3)+(i%width)*3+1] = (bitdata >>  8) & 0xff;
+    image[((height-i/width-1)*width*3)+(i%width)*3+2] = (bitdata >> 16) & 0xff;
+    i++;
+  }
+  fwrite(image,1,width*height*3,wfp);
+  fclose(rfp);
+  fclose(wfp);
+  free(image);
+
+  return 0;
+}

aquaxis_IPCORE/aq_axi_djpeg/aq_axi_djpeg.model/djpeg.c

@@ -0,0 +1,863 @@
+/*
+* Copyright (C)2005-2014 H.Ishihara
+*
+* License: The Open Software License 3.0
+* License URI: http://www.opensource.org/licenses/OSL-3.0
+*
+* For further information please contact.
+*	http://www.aquaxis.com/
+*	info(at)aquaxis.com or hidemi(at)sweetcafe.jp
+*/
+
+//////////////////////////////////////////////////////////////////////////////
+// JPEGデコード
+// 2005年10月26日 V1.0 
+// All Rights Reserved, Copyright (c) Hidemi Ishihara
+//////////////////////////////////////////////////////////////////////////////
+//
+// JPEGを入力するとBitmapを出力します。
+// 
+// % gcc -o djpeg fjpeg.c
+// % djpeg 入力ファイル名　出力ファイル名
+//////////////////////////////////////////////////////////////////////////////
+#include <stdio.h>
+#include <stdlib.h>
+
+#define log_printf(...) 
+
+unsigned int BuffIndex;	// JPEGデータの位置
+unsigned int BuffSize;	// JPEGデータの大きさ
+unsigned int BuffX;		// 画像の横サイズ
+unsigned int BuffY;		// 画像の縦サイズ
+unsigned int BuffBlockX; // MCUの横個数
+unsigned int BuffBlockY; // MCUの縦個数
+unsigned char *Buff;		// 伸長したデータを入れるバッファ
+
+unsigned char	TableDQT[4][64];	// 量子化テーブル
+unsigned short TableDHT[4][162]; // ハフマンテーブル
+
+unsigned short TableHT[4][16];	// ハフマンスタートテーブル
+unsigned char	TableHN[4][16];	// ハフマンスタート番号
+
+unsigned char BitCount = 0;	// 圧縮データの読み込み位置
+unsigned int LineData;		// 伸長に使うデータ
+unsigned int NextData;		// 伸長に使うデータ
+
+unsigned int PreData[3];		// DC成分用の貯めバッファ
+
+unsigned char CompCount;		// コンポーネント数
+unsigned char CompNum[4];	// コンポーネント番号(未使用)
+unsigned char CompSample[4];	// コンポーネント
+unsigned char CompDQT[4];	// コンポーネントのDQTテーブル番号
+unsigned char CompDHT[4];	// コンポーネントのDHTテーブル番号
+unsigned char CompSampleX, CompSampleY;
+
+// ジグザグテーブル
+int zigzag_table[]={
+	 0, 1, 8, 16,9, 2, 3,10,
+	17,24,32,25,18,11, 4, 5,
+	12,19,26,33,40,48,41,34,
+	27,20,13, 6, 7,14,21,28,
+	35,42,49,56,57,50,43,36,
+	29,22,15,23,30,37,44,51,
+	58,59,52,45,38,31,39,46,
+	53,60,61,54,47,55,62,63,
+	0
+};
+
+typedef unsigned short WORD;
+//typedef unsigned long DWORD;
+//typedef long LONG;
+typedef unsigned int DWORD;
+typedef int LONG;
+
+typedef struct tagBITMAPFILEHEADER {
+	WORD	bfType;
+	DWORD	bfSize;
+	WORD	bfReserved1;
+	WORD	bfReserved2;
+	DWORD	bfOffBits;
+} BITMAPFILEHEADER, *PBITMAPFILEHEADER;
+
+typedef struct tagBITMAPINFOHEADER{
+	DWORD	biSize;
+	LONG	biWidth;
+	LONG	biHeight;
+	WORD	biPlanes;
+	WORD	biBitCount;
+	DWORD	biCompression;
+	DWORD	biSizeImage;
+	LONG	biXPelsPerMeter;
+	LONG	biYPelsPerMeter;
+	DWORD	biClrUsed;
+	DWORD	biClrImportant;
+} BITMAPINFOHEADER, *PBITMAPINFOHEADER;
+
+/*
+ * Bitmap出力
+ * file: ファイル名
+ * x,y:  画像のサイズ
+ * b:    バイトカウント(1ドット辺りのバイト数)
+ */
+void BmpSave(unsigned char *file,unsigned char *buff,
+			 unsigned int x,unsigned int y,unsigned int b){
+	BITMAPFILEHEADER lpBf;
+	BITMAPINFOHEADER lpBi;
+	unsigned char tbuff[4];
+	FILE *fp;
+	unsigned char str;
+	int i,k;
+
+	if((fp = fopen(file,"wb")) == NULL){
+	perror(0);
+	exit(0);
+	}
+
+	// ファイルヘッダの設定
+	tbuff[0] = 'B';
+	tbuff[1] = 'M';
+	fwrite(tbuff,2,1,fp);
+	tbuff[3] = ((14 +40 +x *y *b) >> 24) & 0xff;
+	tbuff[2] = ((14 +40 +x *y *b) >> 16) & 0xff;
+	tbuff[1] = ((14 +40 +x *y *b) >>	8) & 0xff;
+	tbuff[0] = ((14 +40 +x *y *b) >>	0) & 0xff;
+	fwrite(tbuff,4,1,fp);
+	tbuff[1] = 0;
+	tbuff[0] = 0;
+	fwrite(tbuff,2,1,fp);
+	fwrite(tbuff,2,1,fp);
+	tbuff[3] = 0;
+	tbuff[2] = 0;
+	tbuff[1] = 0;
+	tbuff[0] = 54;
+	fwrite(tbuff,4,1,fp);
+
+	// インフォメーションの設定
+	lpBi.biSize			= 40;
+	lpBi.biWidth			= x;
+	lpBi.biHeight			= y;
+	lpBi.biPlanes			= 1;
+	lpBi.biBitCount		= b*8;
+	lpBi.biCompression	 = 0;
+	lpBi.biSizeImage		= x*y*b;
+	lpBi.biXPelsPerMeter	= 300;
+	lpBi.biYPelsPerMeter	= 300;
+	lpBi.biClrUsed		 = 0;
+	lpBi.biClrImportant	= 0;
+	fwrite(&lpBi,1,40,fp);
+
+	// 上下反転
+	for(k=0;k<y/2;k++){
+		for(i=0;i<x*3;i++){
+			str = buff[k*x*3+i];
+			buff[k*x*3+i] = buff[((y-1)*x*3 -k*x*3) +i];
+			buff[((y-1)*x*3-k*x*3) +i] = str;
+		}
+	}
+
+	fwrite(buff,1,x*y*b,fp);
+
+	fclose(fp);
+}
+
+/*****************************************
+ * データ取得部
+ *****************************************/
+
+/*
+ * 1Byte取得
+ */
+unsigned char get_byte(unsigned char *buff){
+	if(BuffIndex >= BuffSize) return 0;
+	return buff[BuffIndex++];
+}
+/*
+ * 2Byte取得
+ */
+unsigned short get_word(unsigned char *buff){
+	unsigned char h,l;
+	h = get_byte(buff);
+	l = get_byte(buff);
+	return (h<<8)|l;
+}
+
+/*
+ * 4Byte取得(伸張時のみ使��)
+ */
+unsigned int get_data(unsigned char *buff){
+	unsigned char str = 0;
+	unsigned int data = 0;
+	str = get_byte(buff);
+	if(str ==0xff) if(get_byte(buff)== 0x00) str = 0xFF; else str = 0x00;
+	data = str;
+	str = get_byte(buff);
+	if(str ==0xff) if(get_byte(buff)== 0x00) str = 0xFF; else str = 0x00;
+	data = (data << 8) | str;
+	str = get_byte(buff);
+	if(str ==0xff) if(get_byte(buff)== 0x00) str = 0xFF; else str = 0x00;
+	data = (data << 8) | str;
+	str = get_byte(buff);
+	if(str ==0xff) if(get_byte(buff)== 0x00) str = 0xFF; else str = 0x00;
+	data = (data << 8) | str;
+	//log_printf(" Get Data: %08x\n",data);
+	return data;
+}
+
+/*
+ * ビットデータ取得(伸張時のみ使用)
+ */
+unsigned int get_bit(unsigned char *buff){
+	unsigned int BitData;
+
+	// ビットカウントの位置が32を越えた場合、新たにデータを取得する
+	if(BitCount >=32){
+		LineData = NextData;
+		NextData = get_data(buff);
+		BitCount -= 32;
+	}
+	// Huffmanデコードで使用するデータに置き換える
+	if(BitCount >0){
+		BitData = (LineData << BitCount) | (NextData >> (32 - BitCount));
+	}else{
+		BitData = LineData;
+	}
+
+	return BitData;
+}
+
+/********************
+ * マーカー解析
+ ********************/
+/*
+ * APP0処理
+ */
+void GetAPP0(unsigned char *buff){
+	unsigned short data;
+	unsigned char str;
+	unsigned int i;
+	
+	data = get_word(buff); // Lp(レングス)
+	// APP0は読まなくてもいいので取り合えずレングス分スキップする
+	for(i=0;i<data-2;i++){
+    str = get_byte(buff);
+	}
+#if 0
+	str = get_byte(buff);		// 識別子(5文字,"JFIF"と[00])
+	str = get_byte(buff);
+	str = get_byte(buff);
+	str = get_byte(buff);
+	str = get_byte(buff);
+	data = get_word(buff);	// バージョン
+	str = get_byte(buff);		// 解像度の単位
+	data = get_word(buff);	// 横方向の解像度
+	data = get_word(buff);	// 縦方向の解像度
+	data = get_word(buff);	// サムネイルの横ピクセル数
+	data = get_word(buff);	// サムネイルの縦ピクセル数
+	data = get_word(buff);	// サムネイルデータ(ある場合だけ)
+#endif
+}
+
+/*
+ * DQT処理
+ */
+void GetDQT(unsigned char *buff){
+	unsigned short data;
+	unsigned char str;
+	unsigned int i;
+	unsigned int tablenum;
+
+	data = get_word(buff);
+	str = get_byte(buff); // テーブル番号
+	
+	log_printf("*** DQT Table %d\n",str);
+	for(i=0;i<64;i++){
+    TableDQT[str][i] = get_byte(buff);
+    log_printf(" %2d: %2x\n",i,TableDQT[str][i]);
+	}
+}
+
+/*
+ * DHT処理
+ */
+void GetDHT(unsigned char *buff){
+	unsigned short data;
+	unsigned char str;
+	unsigned int i;
+	unsigned char max,count;
+	unsigned short ShiftData = 0x8000,HuffmanData =0x0000;
+	unsigned int tablenum;
+
+	data = get_word(buff);
+	str = get_byte(buff);
+
+	switch(str){
+	case 0x00:
+		// Y直流成分
+		tablenum = 0x00;
+		break;
+	case 0x10:
+		// Y交流成分
+		tablenum = 0x01;
+		break;
+	case 0x01:
+		// CbCr直流成分
+		tablenum = 0x02;
+		break;
+	case 0x11:
+		// CbCr交流成分
+		tablenum = 0x03;
+		break;
+	}
+
+	log_printf("*** DHT Table/Number %d\n",tablenum);
+	// テーブルを作成する
+	max = 0;
+	for(i=0;i<16;i++){
+		count = get_byte(buff);
+		TableHT[tablenum][i] = HuffmanData;
+		TableHN[tablenum][i] = max;
+		log_printf(" %2d: %4x,%2x\n",i,TableHT[tablenum][i],TableHN[tablenum][i]);
+		max = max + count;
+		while(!(count==0)){
+			HuffmanData += ShiftData;
+			count--;
+		}
+		ShiftData = ShiftData >> 1; // 右に1bitシフトする
+	}
+
+	log_printf("*** DHT Table %d\n",tablenum);
+	for(i=0;i<max;i++){
+		TableDHT[tablenum][i] = get_byte(buff);
+		log_printf(" %2d: %2x\n",i,TableDHT[tablenum][i]);
+	}
+}
+
+/*
+ * SOF処理
+ */
+void GetSOF(unsigned char *buff){
+	unsigned short data;
+	unsigned char str;
+	unsigned int i;
+	unsigned char count;
+	unsigned char num;
+
+	data = get_word(buff);
+	str = get_byte(buff);
+	BuffY = get_word(buff); // 画像の横サイズ
+	BuffX = get_word(buff); // 画像の縦サイズ
+	CompCount	= get_byte(buff); // データのコンポーネント数
+	log_printf(" CompCount: %d\n", CompCount);
+	for(i=0;i<CompCount;i++){
+		str = get_byte(buff); // コンポーネント番号
+		num = str;
+		log_printf(" Comp[%d]: %02X\n", i, str);
+		str = get_byte(buff); // サンプリング比率
+		CompSample[num] = str;
+		log_printf(" Sample[%d]: %02X\n", i, str);
+		str = get_byte(buff); // DQTテーブル番号
+		CompDQT[num] = str;
+		log_printf(" DQT[%d]: %02X\n", i, str);
+	}
+	
+	if(CompCount == 1){
+		CompSampleX = 1;
+		CompSampleY = 1;
+	}else{
+		CompSampleX =  CompSample[1]       & 0x0F;
+		CompSampleY = (CompSample[1] >> 4) & 0x0F;
+	}
+
+	// MCUのサイズを算出する(ひと塊分)
+	BuffBlockX = (int)(BuffX /(8 * CompSampleX));
+	if(BuffX % (8 * CompSampleX) >0) BuffBlockX++;
+	BuffBlockY = (int)(BuffY /(8 * CompSampleY));
+	if(BuffY % (8 * CompSampleY) >0) BuffBlockY++;
+	Buff = (unsigned char*)malloc(BuffBlockY*(8 * CompSampleY)*BuffBlockX*(8 * CompSampleX)*3);
+
+	log_printf(" size : %d x %d,(%d x %d)\n",BuffX,BuffY,BuffBlockX,BuffBlockY);
+}
+
+/*
+ * SOS処理
+ */
+void GetSOS(unsigned char *buff){
+	unsigned short data;
+	unsigned char str;
+	unsigned int i;
+	unsigned char count;
+	unsigned char num;
+
+	data = get_word(buff);
+	count = get_byte(buff);
+	for(i=0;i<count;i++){
+		str = get_byte(buff);
+		num = str;
+		log_printf(" CompNum[%d]: %02X\n", i, str);
+		str = get_byte(buff);
+		CompDHT[num] = str;
+		log_printf(" CompDHT[%d]: %02X\n", i, str);
+	}
+	str = get_byte(buff);
+	str = get_byte(buff);
+	str = get_byte(buff);
+}
+
+/*
+ * ハフマンデコード＋逆量子化＋逆ジグザグ
+ */
+void HuffmanDecode(unsigned char *buff, unsigned char table, int *BlockData){
+	unsigned int data;
+	unsigned char zero;
+	unsigned short code,huffman;
+	unsigned char count =0;
+	unsigned int BitData;
+	unsigned int i;
+	unsigned char tabledqt,tabledc,tableac,tablen;
+	unsigned char ZeroCount,DataCount;
+	int DataCode;
+
+	for(i=0;i<64;i++) BlockData[i] = 0x0; // データのリセット
+
+	// テーブル番号を設定する
+	if(table ==0x00){
+		tabledqt =0x00;
+		tabledc =0x00;
+		tableac =0x01;
+	}else if(table ==0x01){
+		tabledqt =0x01;
+		tabledc	=0x02;
+		tableac	=0x03;
+	}else{
+		tabledqt =0x01;
+		tabledc	=0x02;
+		tableac	=0x03;
+	}
+
+	count = 0; // 念のために
+	while(count <64){
+
+	BitData = get_bit(buff);
+  
+	log_printf(" Haffuman BitData(%2d,%2d): %8x\n",table,count,BitData);
+
+	// 使用するテーブルのセレクト
+	if(count ==0) tablen = tabledc; else tablen = tableac;
+	code = (unsigned short)(BitData >> 16); // コードは16ビット使用する
+	// ハフマンコードがどのビット数にいるか割り出す
+	for(i=0;i<16;i++) {
+		log_printf(" Haff hit(%2d:%2d): %8x,%8x\n",table,i,TableHT[tablen][i],code);
+		if(TableHT[tablen][i]>code) break;
+	}
+	i--;
+
+	code	= (unsigned short)(code >> (15 - i)); // コードの下位を揃える
+	huffman = (unsigned short)(TableHT[tablen][i] >> (15 - i));
+
+	log_printf(" PreUse Dht Number(%2d): %8x,%8x,%8x\n",i,code,huffman,TableHN[tablen][i]);
+
+	// ハフマンテーブルの場所を算出する
+	code = code - huffman + TableHN[tablen][i];
+
+	log_printf(" Use Dht Number: %8x\n",code);
+
+	ZeroCount = (TableDHT[tablen][code] >> 4) & 0x0F; // ゼロレングスの個数
+	DataCount = (TableDHT[tablen][code]) & 0x0F;		// 続くデータのビット長
+	log_printf(" Dht Table: %8x,%8x\n",ZeroCount,DataCount);
+	// ハフマンコードを抜き、続くデータを取得する
+	DataCode	= (BitData << (i + 1)) >> (16 + (16 - DataCount));
+	// 先頭ビットが"0"であれば負のデータ、上位ビットに１を立てて、１を足す
+	//if(!(DataCode & (1<<(DataCount-1)))) DataCode=DataCode-(1<<DataCount)+1;
+	if(!(DataCode & (1<<(DataCount-1))) && DataCount !=0){
+		DataCode |= (~0) << DataCount;
+		DataCode += 1;
+	}
+
+	log_printf(" Use Bit: %d\n",(i + DataCount +1));
+	BitCount += (i + DataCount +1); // 使用したビット数を加算する
+
+	if(count ==0){
+		// DC成分の場合、データとなる
+		if(DataCount ==0) DataCode =0x0; // DataCountが0ならデータは0である
+		PreData[table] += DataCode; // DC成分は加算しなければならない
+		// 逆量子化＋ジグザグ
+		BlockData[zigzag_table[count]] =PreData[table]*TableDQT[tabledqt][count];
+		count ++;
+	}else{
+		if(ZeroCount == 0x0 && DataCount == 0x0){
+			// AC成分でEOB符号が来た場合は終了する
+			break;
+		}else if(ZeroCount ==0xF && DataCount == 0x0){
+			// ZRL符号が来た場合、15個のゼロデータとみなす
+			count += 15;
+		}else{
+			count += ZeroCount;
+			// 逆量子化＋ジグザグ
+			BlockData[zigzag_table[count]] = DataCode * TableDQT[tabledqt][count];
+		}
+		count ++;
+	}
+	}
+}
+
+const int C1_16 = 4017; // cos( pi/16) x4096
+const int C2_16 = 3784; // cos(2pi/16) x4096
+const int C3_16 = 3406; // cos(3pi/16) x4096
+const int C4_16 = 2896; // cos(4pi/16) x4096
+const int C5_16 = 2276; // cos(5pi/16) x4096
+const int C6_16 = 1567; // cos(6pi/16) x4096
+const int C7_16 = 799;	// cos(7pi/16) x4096
+
+/*
+ * iDCT
+ */
+void DctDecode(int *BlockIn, int *BlockOut){
+	int i;
+	int s0,s1,s2,s3,s4,s5,s6,s7;
+	int t0,t1,t2,t3,t4,t5,t6,t7;
+
+  /* iDCT X方向 */
+	log_printf("-----------------------------\n");
+	log_printf(" iDCT(In)\n");
+	log_printf("-----------------------------\n");
+	for(i=0;i<64;i++){
+    log_printf("%2d: %8x\n",i,BlockIn[i]);
+	}
+
+	for(i=0;i<8;i++) {
+		s0 = (BlockIn[0] + BlockIn[4]) * C4_16;
+		s1 = (BlockIn[0] - BlockIn[4]) * C4_16;
+		s3 = (BlockIn[2] * C2_16) + (BlockIn[6] * C6_16);
+		s2 = (BlockIn[2] * C6_16) - (BlockIn[6] * C2_16);
+		s7 = (BlockIn[1] * C1_16) + (BlockIn[7] * C7_16);
+		s4 = (BlockIn[1] * C7_16) - (BlockIn[7] * C1_16);
+		s6 = (BlockIn[5] * C5_16) + (BlockIn[3] * C3_16);
+		s5 = (BlockIn[5] * C3_16) - (BlockIn[3] * C5_16);
+
+		log_printf("s0:%8x\n",s0);
+		log_printf("s1:%8x\n",s1);
+		log_printf("s2:%8x\n",s2);
+		log_printf("s3:%8x\n",s3);
+		log_printf("s4:%8x\n",s4);
+		log_printf("s5:%8x\n",s5);
+		log_printf("s6:%8x\n",s6);
+		log_printf("s7:%8x\n",s7);
+
+		t0 = s0 + s3;
+		t3 = s0 - s3;
+		t1 = s1 + s2;
+		t2 = s1 - s2;
+		t4 = s4 + s5;
+		t5 = s4 - s5;
+		t7 = s7 + s6;
+		t6 = s7 - s6;
+
+		log_printf("t0:%8x\n",t0);
+		log_printf("t1:%8x\n",t1);
+		log_printf("t2:%8x\n",t2);
+		log_printf("t3:%8x\n",t3);
+		log_printf("t4:%8x\n",t4);
+		log_printf("t5:%8x\n",t5);
+		log_printf("t6:%8x\n",t6);
+		log_printf("t7:%8x\n",t7);
+
+		s6 = (t5 + t6) * 181 / 256; // 1/sqrt(2)
+		s5 = (t6 - t5) * 181 / 256; // 1/sqrt(2)
+
+		log_printf("s5:%8x\n",s5);
+		log_printf("s6:%8x\n",s6);
+
+		*BlockIn++ = (t0 + t7) >> 11;
+		*BlockIn++ = (t1 + s6) >> 11;
+		*BlockIn++ = (t2 + s5) >> 11;
+		*BlockIn++ = (t3 + t4) >> 11;
+		*BlockIn++ = (t3 - t4) >> 11;
+		*BlockIn++ = (t2 - s5) >> 11;
+		*BlockIn++ = (t1 - s6) >> 11;
+		*BlockIn++ = (t0 - t7) >> 11;
+	}
+
+	BlockIn -= 64;
+
+  /* iDCT Y方向 */
+	log_printf("-----------------------------\n");
+	log_printf(" iDCT(Middle)\n");
+	log_printf("-----------------------------\n");
+	for(i=0;i<64;i++){
+	log_printf("%2d: %8x\n",i,BlockIn[i]);
+	}
+
+	for(i=0;i<8;i++){
+		s0 = (BlockIn[ 0] + BlockIn[32]) * C4_16;
+		s1 = (BlockIn[ 0] - BlockIn[32]) * C4_16;
+		s3 = BlockIn[16] * C2_16 + BlockIn[48] * C6_16;
+		s2 = BlockIn[16] * C6_16 - BlockIn[48] * C2_16;
+		s7 = BlockIn[ 8] * C1_16 + BlockIn[56] * C7_16;
+		s4 = BlockIn[ 8] * C7_16 - BlockIn[56] * C1_16;
+		s6 = BlockIn[40] * C5_16 + BlockIn[24] * C3_16;
+		s5 = BlockIn[40] * C3_16 - BlockIn[24] * C5_16;
+
+		log_printf("s0:%8x\n",s0);
+		log_printf("s1:%8x\n",s1);
+		log_printf("s2:%8x\n",s2);
+		log_printf("s3:%8x\n",s3);
+		log_printf("s4:%8x\n",s4);
+		log_printf("s5:%8x\n",s5);
+		log_printf("s6:%8x\n",s6);
+		log_printf("s7:%8x\n",s7);
+
+		t0 = s0 + s3;
+		t1 = s1 + s2;
+		t2 = s1 - s2;
+		t3 = s0 - s3;
+		t4 = s4 + s5;
+		t5 = s4 - s5;
+		t6 = s7 - s6;
+		t7 = s6 + s7;
+
+		log_printf("t0:%8x\n",t0);
+		log_printf("t1:%8x\n",t1);
+		log_printf("t2:%8x\n",t2);
+		log_printf("t3:%8x\n",t3);
+		log_printf("t4:%8x\n",t4);
+		log_printf("t5:%8x\n",t5);
+		log_printf("t6:%8x\n",t6);
+		log_printf("t7:%8x\n",t7);
+
+		s5 = (t6 - t5) * 181 / 256; // 1/sqrt(2)
+		s6 = (t5 + t6) * 181 / 256; // 1/sqrt(2)
+
+		log_printf("s5:%8x\n",s5);
+		log_printf("s6:%8x\n",s6);
+
+		BlockOut[ 0] = ((t0 + t7) >> 15);
+		BlockOut[56] = ((t0 - t7) >> 15);
+		BlockOut[ 8] = ((t1 + s6) >> 15);
+		BlockOut[48] = ((t1 - s6) >> 15);
+		BlockOut[16] = ((t2 + s5) >> 15);
+		BlockOut[40] = ((t2 - s5) >> 15);
+		BlockOut[24] = ((t3 + t4) >> 15);
+		BlockOut[32] = ((t3 - t4) >> 15);
+		
+		BlockIn++;
+		BlockOut++;
+	}
+	BlockOut-=8;
+
+	log_printf("-----------------------------\n");
+	log_printf(" iDCT(Out)\n");
+	log_printf("-----------------------------\n");
+	for(i=0;i<8;i++){
+    log_printf(" %2d: %04x;\n",i+ 0,BlockOut[i+ 0]&0xFFFF);
+    log_printf(" %2d: %04x;\n",i+56,BlockOut[i+56]&0xFFFF);
+    log_printf(" %2d: %04x;\n",i+ 8,BlockOut[i+ 8]&0xFFFF);
+    log_printf(" %2d: %04x;\n",i+48,BlockOut[i+48]&0xFFFF);
+    log_printf(" %2d: %04x;\n",i+16,BlockOut[i+16]&0xFFFF);
+    log_printf(" %2d: %04x;\n",i+40,BlockOut[i+40]&0xFFFF);
+    log_printf(" %2d: %04x;\n",i+24,BlockOut[i+24]&0xFFFF);
+    log_printf(" %2d: %04x;\n",i+32,BlockOut[i+32]&0xFFFF);
+	}
+}
+
+//////////////////////////////////////////////////////////////////////////////
+// 4:1:1のデコード処理
+void Decode411(unsigned char *buff, int *BlockY, int *BlockCb, int *BlockCr){
+	int BlockHuffman[64];
+	int BlockYLT[64];
+	int BlockYRT[64];
+	int BlockYLB[64];
+	int BlockYRB[64];
+	int Block[64];
+	unsigned int i;
+	unsigned int m, n;
+
+	for(n=0;n<CompSampleY;n++){
+		for(m=0;m<CompSampleX;m++){
+			log_printf("BlockY:%d,%d\n",m,n);
+			HuffmanDecode(buff,0x00,BlockHuffman);
+			DctDecode(BlockHuffman,Block);
+			for(i=0;i<64;i++){
+				BlockY[(int)(i/8)*8*CompSampleX+(i%8)+(m*8)+(n*64*CompSampleY)] = Block[i];
+			}
+		}
+	}
+
+	if(CompCount > 1){
+		// 青色差
+		log_printf("Block:10\n");
+		HuffmanDecode(buff,0x01,BlockHuffman);
+		DctDecode(BlockHuffman,BlockCb);
+
+		// 赤色差
+		log_printf("Block:11\n");
+		HuffmanDecode(buff,0x02,BlockHuffman);
+		DctDecode(BlockHuffman,BlockCr);
+	}
+}
+
+/*
+ * YUV→RGBに変換
+ */
+void DecodeYUV(int *y, int *cb, int *cr, unsigned char *rgb){
+	int r,g,b;
+	int p,i;
+
+	log_printf("----RGB----\n");
+	for(i=0;i<((CompCount>1)?256:64);i++){
+		p = ((int)(i/32) * 8) + ((int)((i % 16)/2));
+		r = 128 + y[i] + ((CompCount>1)?cr[p]*1.402:0);
+		r = (r & 0xffffff00) ? (r >> 24) ^ 0xff : r;
+		g = 128 + y[i] - ((CompCount>1)?cb[p]*0.34414:0) - ((CompCount>1)?cr[p]*0.71414:0);
+		g = (g & 0xffffff00) ? (g >> 24) ^ 0xff : g;
+		b = 128 + y[i] + ((CompCount>1)?cb[p]*1.772:0);
+		b = (b & 0xffffff00) ? (b >> 24) ^ 0xff : b;
+		rgb[i*3+0] = b;
+		rgb[i*3+1] = g;
+		rgb[i*3+2] = r;
+	log_printf("[RGB]%3d: %3x,%3x,%3x = %2x,%2x,%2x\n",i,
+			y[i]&0x1FF,cr[p]&0x1FF,cb[p]&0x1FF,
+			rgb[i*3+2],rgb[i*3+1],rgb[i*3+0]);
+	}
+}
+
+//////////////////////////////////////////////////////////////////////////////
+// イメージのデコード
+void Decode(unsigned char *buff,unsigned char *rgb){
+	int BlockY[256];
+	int BlockCb[256];
+	int BlockCr[256];
+	int x,y,i,p;
+
+	for(y=0;y<BuffBlockY;y++){
+		for(x=0;x<BuffBlockX;x++){
+			Decode411(buff,BlockY,BlockCb,BlockCr);	// 4:1:1のデコード
+			DecodeYUV(BlockY,BlockCb,BlockCr,rgb);		// YUV→RGB変換
+			for(i=0;i<((CompCount>1)?256:64);i++){
+				if((x*(8*CompSampleX)+(i%(8*CompSampleX))<BuffX) && (y*(8*CompSampleY)+i/(8*CompSampleY)<BuffY)){
+					p=y*(8*CompSampleY)*BuffX*3+x*(8*CompSampleX)*3+(int)(i/(8*CompSampleY))*BuffX*3+(i%(8*CompSampleX))*3;
+					Buff[p+0] = rgb[i*3+0];
+					Buff[p+1] = rgb[i*3+1];
+					Buff[p+2] = rgb[i*3+2];
+			
+					log_printf("RGB[%4d,%4d]: %2x,%2x,%2x\n",x*(8*CompSampleX)+(i%(8*CompSampleX)),y*(8*CompSampleY)+i/(8*CompSampleY),rgb[i*3+2],rgb[i*3+1],rgb[i*3+0]);
+				}
+			}
+		}
+	}
+}
+
+/*
+ * デコード
+ */
+void JpegDecode(unsigned char *buff){
+	unsigned short data;
+	unsigned int i;
+	unsigned int Image =0;
+	unsigned char RGB[256*3];
+	while(!(BuffIndex >= BuffSize)){
+		if(Image ==0){
+			data = get_word(buff);
+			switch(data){
+				case 0xFFD8: // SOI
+				log_printf("Header: SOI\n");
+				break;
+			case 0xFFE0: // APP0
+				log_printf("Header: APP0\n");
+				GetAPP0(buff);
+				break;
+			case 0xFFDB: // DQT
+				log_printf("Header: DQT\n");
+				GetDQT(buff);
+				break;
+			case 0xFFC4: // DHT
+				log_printf("Header: DHT\n");
+				GetDHT(buff);
+				break;
+			case 0xFFC0: // SOF
+				log_printf("Header: SOF\n");
+				GetSOF(buff);
+				break;
+			case 0xFFDA: // SOS
+				log_printf("Header: SOS\n");
+				GetSOS(buff);
+				Image = 1;
+				// データの準備
+				PreData[0] = 0x00;
+				PreData[1] = 0x00;
+				PreData[2] = 0x00;
+				LineData = get_data(buff);
+				NextData = get_data(buff);
+				BitCount =0;
+				break;
+			case 0xFFD9: // EOI
+				log_printf("Header: EOI\n");
+				break;
+			default:
+				// 判別できないヘッダーは読み飛ばす
+				log_printf("Header: other(%X)\n", data);
+				if((data & 0xFF00) == 0xFF00 && !(data == 0xFF00)){
+					data = get_word(buff);
+					for(i=0;i<data-2;i++){
+					get_byte(buff);
+					}
+				}
+				break;
+			}
+		}else{
+			// 伸長(SOSが来ている)
+			log_printf("/****Image****/\n");
+			Decode(buff,RGB);
+		}
+	}
+}
+
+//////////////////////////////////////////////////////////////////////////////
+// メイン関数
+//////////////////////////////////////////////////////////////////////////////
+int main(int argc, char* argv[])
+{
+	unsigned char *buff;
+	FILE *fp;
+
+	// 型のサイズを表示する
+	log_printf( " sizeof(char):           %02d\n", sizeof( char ) );
+	log_printf( " sizeof(unsigned char):  %02d\n", sizeof( unsigned char ) );
+	log_printf( " sizeof(short):          %02d\n", sizeof( short ) );
+	log_printf( " sizeof(unsigned short): %02d\n", sizeof( unsigned short ) );
+	log_printf( " sizeof(int):            %02d\n", sizeof( int ) );
+	log_printf( " sizeof(unsigned int):   %02d\n", sizeof( unsigned int ) );
+	log_printf( " sizeof(long):           %02d\n", sizeof( long ) );
+	log_printf( " sizeof(unsigned long):  %02d\n", sizeof( unsigned long ) );
+
+	log_printf( " sizeof:                 %02d\n", sizeof( BITMAPFILEHEADER ) );
+	log_printf( " sizeof:                 %02d\n", sizeof( BITMAPINFOHEADER ) );
+
+	if((fp = fopen(argv[1], "rb")) == NULL){
+		perror(0);
+		exit(0);
+	}
+
+	// ファイルサイズを取得する
+	BuffSize = 0;
+	while(!feof(fp)){
+		fgetc(fp);
+		BuffSize ++;
+	}
+	BuffSize--;
+	rewind(fp);	// ファイルポインタを最初に戻す
+
+	buff = (unsigned char *)malloc(BuffSize);	// バッファを確保する
+	fread(buff,1,BuffSize,fp);					// バッファに読み込む
+	BuffIndex = 0;
+	JpegDecode(buff);								// JPEGデコードする
+	log_printf("Finished decode\n");
+	BmpSave(argv[2],Buff,BuffX,BuffY,3);			// Bitmapに保存する
+	log_printf("Saved BMP\n");
+
+	// 全て開放します
+	fclose(fp);
+	free(buff);
+	free(Buff);
+
+	return 0;
+}

aquaxis_IPCORE/aq_axi_djpeg/aq_axi_djpeg.srcs/sim/tb_aq_djpeg.v

@@ -0,0 +1,412 @@
+/*
+ * Copyright (C)2006-2015 AQUAXIS TECHNOLOGY.
+ *  Don't remove this header. 
+ * When you use this source, there is a need to inherit this header.
+ *
+ * License
+ *  For no commercial -
+ *   License:     The Open Software License 3.0
+ *   License URI: http://www.opensource.org/licenses/OSL-3.0
+ *
+ *  For commmercial -
+ *   License:     AQUAXIS License 1.0
+ *   License URI: http://www.aquaxis.com/licenses
+ *
+ * For further information please contact.
+ *	URI:    http://www.aquaxis.com/
+ *	E-Mail: info(at)aquaxis.com
+ */
+`timescale 1ps / 1ps
+
+module tb_aq_djpeg;
+	reg rst;
+	reg clk;
+
+	reg [31:0] JPEG_MEM [0:1*1024*1024-1];
+
+	integer	DATA_COUNT;
+
+	parameter clkP = 10000; // 100MHz
+	parameter clkH = clkP /2;
+	parameter clkL = clkP - clkH;
+
+	wire [31:0] JPEG_DATA;
+	reg		 DATA_ENABLE;
+	wire		READ_ENABLE;
+	wire		JPEG_IDLE;
+
+	wire		OutEnable;
+	wire [15:0] OutWidth;
+	wire [15:0] OutHeight;
+	wire [15:0] OutPixelX;
+	wire [15:0] OutPixelY;
+	wire [7:0]	OutR;
+	wire [7:0]	OutG;
+	wire [7:0]	OutB;
+
+	integer	 count;
+	reg [23:0]	rgb_mem [0:1920*1080-1];
+
+	initial begin
+		count = 0;
+		while(1) begin
+		 @(posedge clk);
+		 count = count +1;
+		end
+	end
+
+	aq_djpeg u_aq_djpeg
+	 (
+		.rst(rst),
+		.clk(clk),
+
+		.DataIn			(JPEG_DATA),
+		.DataInEnable		(DATA_ENABLE),
+		.DataInRead		(READ_ENABLE),
+		.JpegDecodeIdle	(JPEG_IDLE),
+
+		.OutEnable		( OutEnable ),
+		.OutWidth		( OutWidth	),
+		.OutHeight		( OutHeight ),
+		.OutPixelX		( OutPixelX ),
+		.OutPixelY		( OutPixelY ),
+		.OutR			( OutR		),
+		.OutG			( OutG		),
+		.OutB			( OutB		)
+		);
+
+
+	// Clock
+	always begin
+		#clkH clk = 0;
+		#clkL clk = 1;
+	end
+
+	initial begin
+		rst = 1'b0;
+		repeat (300) @(posedge clk);
+		rst = 1'b1;
+	end
+
+	// Read JPEG File
+	initial begin
+		$readmemh("/mnt/disk1/Public/FPGA_Magazine_No.6/DJPEG_IP/test.mem",JPEG_MEM);
+	end
+
+	// Initial
+	initial begin
+		DATA_COUNT	<= 0;
+		DATA_ENABLE <= 1'b0;
+		wait (rst == 1'b1);
+		@(posedge clk);
+		$display(" Start Clock: %d",count);
+		@(posedge clk);
+		@(posedge clk);
+		DATA_ENABLE <= 1'b1;
+		forever begin
+		 if(READ_ENABLE == 1'b1) begin
+			DATA_COUNT	<= DATA_COUNT +1;
+		 end
+		 @(posedge clk);
+		end
+	end // initial begin
+
+	assign JPEG_DATA = JPEG_MEM[DATA_COUNT];
+
+	integer i;
+
+	initial begin
+		@(posedge u_aq_djpeg.ImageEnable);
+
+		$display("------------------------------");
+		$display("Image Run");
+		$display("------------------------------");
+		$display(" X: %4d",i,u_aq_djpeg.OutWidth);
+		$display(" Y: %4d",i,u_aq_djpeg.OutHeight);
+		$display(" Component: %4d",i,u_aq_djpeg.JpegComp);
+		$display(" BlockWidth: %4d",i,u_aq_djpeg.JpegBlockWidth);
+		$display("------------------------------");
+		$display(" DQT Y Table");
+		for(i=0;i<64;i=i+1) begin
+		 $display(" %2d: %2x",i,u_aq_djpeg.u_jpeg_huffman.u_jpeg_dqt.DQT_Y[i]);
+		end
+
+		$display("------------------------------");
+		$display(" DQT Cb/Cr Table");
+		for(i=0;i<64;i=i+1) begin
+		 $display(" %2d: %2x",i,u_aq_djpeg.u_jpeg_huffman.u_jpeg_dqt.DQT_C[i]);
+		end
+		$display("------------------------------");
+
+		$display("------------------------------");
+		$display(" huffman Y-DC Code/Number");
+		for(i=0;i<16;i=i+1) begin
+		 $display(" %2d: %2x,%2x",i,u_aq_djpeg.u_jpeg_huffman.u_jpeg_hm_decode.HuffmanTable0r[i],u_aq_djpeg.u_jpeg_huffman.u_jpeg_hm_decode.HuffmanNumber0r[i]);
+		end
+		$display("------------------------------");
+
+		$display("------------------------------");
+		$display(" huffman Y-DC Table");
+		for(i=0;i<16;i=i+1) begin
+		 $display(" %2d: %2x",i,u_aq_djpeg.u_jpeg_huffman.u_jpeg_dht.DHT_Ydc[i]);
+		end
+		$display("------------------------------");
+
+		$display("------------------------------");
+		$display(" huffman Y-AC Code/Number");
+		for(i=0;i<16;i=i+1) begin
+		 $display(" %2d: %2x,%2x",i,u_aq_djpeg.u_jpeg_huffman.u_jpeg_hm_decode.HuffmanTable1r[i],u_aq_djpeg.u_jpeg_huffman.u_jpeg_hm_decode.HuffmanNumber1r[i]);
+		end
+		$display("------------------------------");
+
+		$display("------------------------------");
+		$display(" huffman Y-AC Table");
+		for(i=0;i<162;i=i+1) begin
+		 $display(" %2d: %2x",i,u_aq_djpeg.u_jpeg_huffman.u_jpeg_dht.DHT_Yac[i]);
+		end
+		$display("------------------------------");
+
+		$display("------------------------------");
+		$display(" huffman C-DC Table");
+		for(i=0;i<16;i=i+1) begin
+		 $display(" %2d: %2x,%2x",i,u_aq_djpeg.u_jpeg_huffman.u_jpeg_hm_decode.HuffmanTable2r[i],u_aq_djpeg.u_jpeg_huffman.u_jpeg_hm_decode.HuffmanNumber2r[i]);
+		end
+		$display("------------------------------");
+
+		$display("------------------------------");
+		$display(" huffman C-DC Table");
+		for(i=0;i<16;i=i+1) begin
+		 $display(" %2d: %2x",i,u_aq_djpeg.u_jpeg_huffman.u_jpeg_dht.DHT_Cdc[i]);
+		end
+		$display("------------------------------");
+
+		$display("------------------------------");
+		$display(" huffman C-AC Table");
+		for(i=0;i<16;i=i+1) begin
+		 $display(" %2d: %2x,%2x",i,u_aq_djpeg.u_jpeg_huffman.u_jpeg_hm_decode.HuffmanTable3r[i],u_aq_djpeg.u_jpeg_huffman.u_jpeg_hm_decode.HuffmanNumber3r[i]);
+		end
+		$display("------------------------------");
+
+		$display("------------------------------");
+		$display(" huffman C-AC Table");
+		for(i=0;i<162;i=i+1) begin
+		 $display(" %2d: %2x",i,u_aq_djpeg.u_jpeg_huffman.u_jpeg_dht.DHT_Cac[i]);
+		end
+		$display("------------------------------");
+	end
+/*
+	integer Phase8Count;
+	initial begin
+		Phase8Count <= 0;
+		while(1) begin
+		 @(posedge clk);
+		 if((u_aq_djpeg.u_jpeg_huffman.u_jpeg_hm_decode.Process == 4'h8) && !(u_aq_djpeg.u_jpeg_huffman.u_jpeg_hm_decode.ProcessCount < 63)) begin
+			Phase8Count <= Phase8Count + 1;
+			$display(" Process Phase8: %d", Phase8Count);
+		end
+		end
+	end
+*/
+	integer DataOutEnable;
+	initial begin
+		DataOutEnable <= 0;
+		while(1) begin
+		 @(posedge clk);
+		 if(u_aq_djpeg.u_jpeg_huffman.u_jpeg_hm_decode.DataOutEnable == 1'b1) begin
+			DataOutEnable <= DataOutEnable + 1;
+			$display(" DataOutEnable: %d", DataOutEnable);
+		end
+		end
+	end
+
+	integer ConvertEnable;
+	initial begin
+		ConvertEnable <= 0;
+		while(1) begin
+		 @(posedge clk);
+		 if((u_aq_djpeg.u_jpeg_ycbcr.ConvertRead == 1'b1 == 1'b1) && (u_aq_djpeg.u_jpeg_ycbcr.ConvertAddress == 8'd255)) begin
+			ConvertEnable <= ConvertEnable + 1;
+			$display(" ConvertEnable: %d", ConvertEnable);
+		end
+		end
+	end
+
+
+/*
+	initial begin
+		while(1) begin
+		 @(posedge clk);
+		 if(u_aq_djpeg.u_jpeg_huffman.u_jpeg_hm_decode.Process == 4'h2)
+			$display(" Color: %d,%d",u_aq_djpeg.u_jpeg_huffman.u_jpeg_hm_decode.ProcessColor,
+					u_aq_djpeg.u_jpeg_huffman.u_jpeg_hm_decode.ProcessCount);
+		end
+	end
+
+	initial begin
+		while(1) begin
+		 @(posedge clk);
+		 if(u_aq_djpeg.u_jpeg_huffman.u_jpeg_hm_decode.Process == 4'h4)
+			for(i=0;i<16;i=i+1) begin
+				$display(" Data Code: %8x,%8x",u_aq_djpeg.u_jpeg_huffman.u_jpeg_hm_decode.HuffmanTable[i],u_aq_djpeg.u_jpeg_huffman.u_jpeg_hm_decode.HuffmanNumber[i]);
+			end
+		end
+	end
+*/
+
+/*
+	initial begin
+		while(1) begin
+		 @(posedge clk);
+		 if(u_aq_djpeg.u_jpeg_huffman.u_jpeg_hm_decode.Process == 4'h6)
+			$display(" Wait for RAM");
+		end
+	end
+*/
+/*
+	initial begin
+		while(1) begin
+		 @(posedge clk);
+		 if(u_aq_djpeg.u_jpeg_huffman.u_jpeg_hm_decode.Process == 4'h4)
+			$display(" Data Code: %8x",u_aq_djpeg.u_jpeg_huffman.u_jpeg_hm_decode.ProcessData);
+		end
+	end
+*/
+/*
+	initial begin
+		while(1) begin
+		 @(posedge clk);
+		 if(u_aq_djpeg.u_jpeg_huffman.u_jpeg_hm_decode.Process == 4'hB)
+			$display(" Data Code: %d,%d,%4x,%4x,%4x,%4x,%2x,%4x,%4x,%4x,%8x",
+					u_aq_djpeg.u_jpeg_huffman.u_jpeg_hm_decode.CodeNumber,
+					u_aq_djpeg.u_jpeg_huffman.u_jpeg_hm_decode.ProcessCount,
+					u_aq_djpeg.u_jpeg_huffman.u_jpeg_hm_decode.DhtNumber,
+					u_aq_djpeg.u_jpeg_huffman.u_jpeg_hm_decode.DhtZero,
+					u_aq_djpeg.u_jpeg_huffman.u_jpeg_hm_decode.DataNumber,
+					u_aq_djpeg.u_jpeg_huffman.u_jpeg_hm_decode.TableCode,
+					u_aq_djpeg.u_jpeg_huffman.u_jpeg_hm_decode.NumberCode,
+					u_aq_djpeg.u_jpeg_huffman.u_jpeg_hm_decode.DqtData,
+					u_aq_djpeg.u_jpeg_huffman.u_jpeg_hm_decode.OutCode,
+					u_aq_djpeg.u_jpeg_huffman.u_jpeg_hm_decode.OutData,
+					u_aq_djpeg.u_jpeg_huffman.u_jpeg_hm_decode.ProcessData);
+		end
+	end
+
+
+
+	initial begin
+		while(1) begin
+		 @(posedge clk);
+		 if(u_aq_djpeg.u_jpeg_huffman.HmDecEnable == 1'b1)
+				$display(" HmDec Code: %d,%4x",
+						u_aq_djpeg.u_jpeg_huffman.HmDecCount,
+						u_aq_djpeg.u_jpeg_huffman.HmDecData);
+		end
+	end
+*/
+
+/*
+	initial begin
+		while(1) begin
+		 @(posedge clk);
+		 if(u_aq_djpeg.u_jpeg_huffman.HmOutEnable == 1'b1)
+			for(i=0;i<64;i=i+1) begin
+				$display(" Data Code: %d,%4x",i,
+						u_aq_djpeg.u_jpeg_huffman.u_jpeg_ziguzagu.RegData[i]);
+			end
+		end
+	end
+*/
+
+/*
+	initial begin
+		while(1) begin
+		 @(posedge clk);
+		 if(u_aq_djpeg.u_jpeg_idct.u_jpeg_idctx.Phase4Enable.O == 1'b1)
+		 //if(u_aq_djpeg.u_jpeg_idct.u_jpeg_idctx.Phase4Enable == 1'b1)
+			$display(" Dct Data[X]: %d:%d,%016x,%016x",u_aq_djpeg.u_jpeg_idct.u_jpeg_idctx.Phase4Page,u_aq_djpeg.u_jpeg_idct.u_jpeg_idctx.Phase4Count,u_aq_djpeg.u_jpeg_idct.u_jpeg_idctx.Phase4R0r,u_aq_djpeg.u_jpeg_idct.u_jpeg_idctx.Phase4R1r);
+		end
+	end
+*/
+/*
+	initial begin
+		while(1) begin
+		 @(posedge clk);
+		 if(u_aq_djpeg.u_jpeg_idct.DctXEnable == 1'b1)
+			$display(" Dct Data[X]: %d:%d,%4x,%4x",u_aq_djpeg.u_jpeg_idct.DctXPage,u_aq_djpeg.u_jpeg_idct.DctXCount,u_aq_djpeg.u_jpeg_idct.DctXData0r,u_aq_djpeg.u_jpeg_idct.DctXData1r);
+		end
+	end
+*/
+
+/*
+	initial begin
+		while(1) begin
+		 @(posedge clk);
+		 if(u_aq_djpeg.u_jpeg_idct.u_jpeg_idcty.Phase3Enable == 1'b1)
+			$display(" Dct Data[Y2]: %d,%8x,%8x,%8x,%8x,%8x,%8x,%8x,%8x",u_aq_djpeg.u_jpeg_idct.u_jpeg_idcty.Phase3Count,u_aq_djpeg.u_jpeg_idct.u_jpeg_idcty.Phase2Reg[0],u_aq_djpeg.u_jpeg_idct.u_jpeg_idcty.Phase2Reg[1],u_aq_djpeg.u_jpeg_idct.u_jpeg_idcty.Phase2Reg[2],u_aq_djpeg.u_jpeg_idct.u_jpeg_idcty.Phase2Reg[3],u_aq_djpeg.u_jpeg_idct.u_jpeg_idcty.Phase2Reg[4],u_aq_djpeg.u_jpeg_idct.u_jpeg_idcty.Phase2Reg[5],u_aq_djpeg.u_jpeg_idct.u_jpeg_idcty.Phase3Reg[6],u_aq_djpeg.u_jpeg_idct.u_jpeg_idcty.Phase2Reg[7]);
+		end
+	end
+
+	initial begin
+		while(1) begin
+		 @(posedge clk);
+		 if(u_aq_djpeg.u_jpeg_idct.u_jpeg_idcty.Phase5Enable == 1'b1)
+			$display(" Dct Data[Y5]: %d,%8x,%8x,%8x,%8x,%8x,%8x,%8x,%8x,%8x,%8x",u_aq_djpeg.u_jpeg_idct.u_jpeg_idcty.Phase5Count,u_aq_djpeg.u_jpeg_idct.u_jpeg_idcty.Phase5R0w,u_aq_djpeg.u_jpeg_idct.u_jpeg_idcty.Phase5R1w,u_aq_djpeg.u_jpeg_idct.u_jpeg_idcty.Phase3Reg[0],u_aq_djpeg.u_jpeg_idct.u_jpeg_idcty.Phase3Reg[1],u_aq_djpeg.u_jpeg_idct.u_jpeg_idcty.Phase3Reg[2],u_aq_djpeg.u_jpeg_idct.u_jpeg_idcty.Phase3Reg[3],u_aq_djpeg.u_jpeg_idct.u_jpeg_idcty.Phase3Reg[4],u_aq_djpeg.u_jpeg_idct.u_jpeg_idcty.Phase3Reg[5],u_aq_djpeg.u_jpeg_idct.u_jpeg_idcty.Phase3Reg[6],u_aq_djpeg.u_jpeg_idct.u_jpeg_idcty.Phase3Reg[7]);
+		end
+	end
+
+
+
+	initial begin
+		while(1) begin
+		 @(posedge clk);
+		 if(u_aq_djpeg.DctEnable == 1'b1)
+			$display(" Dct Data[Y]: %d,%4x,%4x",u_aq_djpeg.DctCount,u_aq_djpeg.Dct0Data,u_aq_djpeg.Dct1Data);
+		end
+	end
+*/
+
+	integer address;
+	integer fp;
+
+	// ??????????????????????????????
+	initial begin
+		while(1) begin
+		 if(u_aq_djpeg.OutEnable == 1'b1) begin
+			address = u_aq_djpeg.OutWidth * u_aq_djpeg.OutPixelY + u_aq_djpeg.OutPixelX;
+			$display(" RGB[%4d,%4d][%4d,%4d]: %2x,%2x,%2x",OutPixelX,OutPixelY,OutWidth,OutHeight,OutR,OutG,OutB);
+			rgb_mem[address] = {OutR,OutG,OutB};
+		 end
+		 @(posedge clk);
+		end
+	end
+
+
+	initial begin
+		wait(!JPEG_IDLE);
+		wait(JPEG_IDLE);
+
+		@(posedge clk);
+		@(posedge clk);
+		@(posedge clk);
+		@(posedge clk);
+		@(posedge clk);
+		@(posedge clk);
+		@(posedge clk);
+		@(posedge clk);
+
+		$display(" End Clock %d",count);
+		fp = $fopen("sim.dat");
+		$fwrite(fp,"%0d\n",OutWidth);
+		$fwrite(fp,"%0d\n",OutHeight);
+
+		for(i=0;i<OutWidth*OutHeight;i=i+1) begin
+		 $fwrite(fp,"%06x\n",rgb_mem[i]);
+		end
+		$fclose(fp);
+
+//		$coverage_save("sim.cov");
+		$finish();
+		//$stop();
+	end
+
+endmodule

aquaxis_IPCORE/aq_axi_djpeg/aq_axi_djpeg.srcs/sources/aq_axi_djpeg.v

@@ -0,0 +1,195 @@
+/*
+ * Copyright (C)2014-2015 AQUAXIS TECHNOLOGY.
+ *  Don't remove this header. 
+ * When you use this source, there is a need to inherit this header.
+ *
+ * License
+ *  For no commercial -
+ *   License:     The Open Software License 3.0
+ *   License URI: http://www.opensource.org/licenses/OSL-3.0
+ *
+ *  For commmercial -
+ *   License:     AQUAXIS License 1.0
+ *   License URI: http://www.aquaxis.com/licenses
+ *
+ * For further information please contact.
+ *	URI:    http://www.aquaxis.com/
+ *	E-Mail: info(at)aquaxis.com
+ */
+`timescale 1ps / 1ps
+
+module aq_axi_djpeg
+#(
+  parameter     C_BASEADRS  = 32'h4001_0000,
+  parameter     C_ADRSWIDTH = 8
+  )
+(
+  input         RST_N,
+  input         CLK,
+
+  // --------------------------------------------------
+  // AXI4 Lite Interface
+  // --------------------------------------------------
+  input           S_AXI_ACLK,
+    
+  // Write Address Channel
+  input [31:0]  S_AXI_AWADDR,
+  input [3:0]   S_AXI_AWCACHE,
+  input [2:0]   S_AXI_AWPROT,
+  input         S_AXI_AWVALID,
+  output        S_AXI_AWREADY, 
+        
+  // Write Data Channel
+  input [31:0]  S_AXI_WDATA,
+  input [3:0]   S_AXI_WSTRB,
+  input         S_AXI_WVALID,
+  output        S_AXI_WREADY,
+        
+  // Write Response Channel
+  output        S_AXI_BVALID,
+  input         S_AXI_BREADY,
+  output [1:0]  S_AXI_BRESP,
+
+  // Read Address Channel
+  input [31:0]  S_AXI_ARADDR,
+  input [3:0]   S_AXI_ARCACHE,
+  input [2:0]   S_AXI_ARPROT,
+  input         S_AXI_ARVALID,
+  output        S_AXI_ARREADY,
+
+  // Read Data Channel
+  output [31:0] S_AXI_RDATA,
+  output [1:0]  S_AXI_RRESP,
+  output        S_AXI_RVALID,
+  input         S_AXI_RREADY,
+
+
+  // JPEG Data In
+  input [31:0]  DATA_IN,
+  input         EMPTY,
+  output        READ,
+
+
+// Bitmap Data Out
+  output [31:0] DATA_OUT,
+  output        WRITE,
+  input         FULL,
+
+  output [31:0] DEBUG
+);
+
+  wire           local_cs;
+  wire           local_rnw;
+  wire           local_ack;
+  wire [31:0]    local_addr;
+  wire [3:0]     local_be;
+  wire [31:0]    local_wdata;
+  wire [31:0]    local_rdata;
+
+wire        Empty, Read;
+wire [31:0] Data;
+
+wire JpegDecodeIdle;
+wire [15:0] OutWidth, OutHeight, OutPixelX, OutPixelY;
+wire [7:0] OutR, OutG, OutB;
+
+  aq_axi_lite_slave
+    #(
+      .C_BASEADRS(C_BASEADRS),
+      .C_ADRSWIDTH(C_ADRSWIDTH)
+    )
+  u_aq_axi_lite_slave 
+    (
+      .ARESETN(RST_N),
+      .ACLK(S_AXI_ACLK),
+      
+      .S_AXI_AWADDR(S_AXI_AWADDR),
+      .S_AXI_AWCACHE(S_AXI_AWCACHE),
+      .S_AXI_AWPROT(S_AXI_AWPROT),
+      .S_AXI_AWVALID(S_AXI_AWVALID),
+      .S_AXI_AWREADY(S_AXI_AWREADY),
+      
+      .S_AXI_WDATA(S_AXI_WDATA),
+      .S_AXI_WSTRB(S_AXI_WSTRB),
+      .S_AXI_WVALID(S_AXI_WVALID),
+      .S_AXI_WREADY(S_AXI_WREADY),
+      
+      .S_AXI_BVALID(S_AXI_BVALID),
+      .S_AXI_BREADY(S_AXI_BREADY),
+      .S_AXI_BRESP(S_AXI_BRESP),
+      
+      .S_AXI_ARADDR(S_AXI_ARADDR),
+      .S_AXI_ARCACHE(S_AXI_ARCACHE),
+      .S_AXI_ARPROT(S_AXI_ARPROT),
+      .S_AXI_ARVALID(S_AXI_ARVALID),
+      .S_AXI_ARREADY(S_AXI_ARREADY),
+      
+      .S_AXI_RDATA(S_AXI_RDATA),
+      .S_AXI_RRESP(S_AXI_RRESP),
+      .S_AXI_RVALID(S_AXI_RVALID),
+      .S_AXI_RREADY(S_AXI_RREADY),
+      
+      .LOCAL_CS(local_cs),
+      .LOCAL_RNW(local_rnw),
+      .LOCAL_ACK(local_ack),
+      .LOCAL_ADDR(local_addr),
+      .LOCAL_BE(local_be),
+      .LOCAL_WDATA(local_wdata),
+      .LOCAL_RDATA(local_rdata),
+      
+      .DEBUG(debug_slave)
+    );
+
+wire JpegDecodeRst;
+   
+aq_djpeg u_aq_djpeg(
+  .rst            ( ~JpegDecodeRst  ),
+  .clk            ( CLK             ),
+
+  // From FIFO
+  .DataIn         ( DATA_IN[31:0]   ),
+  .DataInEnable   ( ~EMPTY          ),
+  .DataInRead     ( READ            ),
+
+  .JpegDecodeIdle ( JpegDecodeIdle  ),
+
+  .OutEnable      ( WRITE           ),
+  .OutWidth       ( OutWidth[15:0]  ),
+  .OutHeight      ( OutHeight[15:0] ),
+  .OutPixelX      ( OutPixelX[15:0] ),
+  .OutPixelY      ( OutPixelY[15:0] ),
+  .OutR           ( OutR[7:0]       ),
+  .OutG           ( OutG[7:0]       ),
+  .OutB           ( OutB[7:0]       )
+);
+
+assign DATA_OUT[31:0] = {8'd0, OutR[7:0], OutG[7:0], OutB[7:0]};
+//assign DATA_OUT[31:0] = {OutPixelY[15:0], OutPixelX[15:0]};
+
+  aq_axi_djpeg_ctl u_aq_axi_djpeg_ctl
+    (
+      .RST_N(RST_N),
+      .CLK(S_AXI_ACLK),
+      
+      .LOCAL_CS(local_cs),
+      .LOCAL_RNW(local_rnw),
+      .LOCAL_ACK(local_ack),
+      .LOCAL_ADDR(local_addr),
+      .LOCAL_BE(local_be),
+      .LOCAL_WDATA(local_wdata),
+      .LOCAL_RDATA(local_rdata),
+
+      .LOGIC_RST(JpegDecodeRst),
+      .LOGIC_IDLE(JpegDecodeIdle),
+      
+      .WIDTH(OutWidth[15:0]),
+      .HEIGHT(OutHeight[15:0]),
+      .PIXELX(OutPixelX[15:0]),
+      .PIXELY(OutPixelY[15:0]),
+      
+      .DEBUG()
+    );
+    
+    assign DEBUG = {24'd0, 2'b00, S_AXI_RREADY, S_AXI_RVALID, local_ack, local_rnw, local_cs, RST_N};
+
+endmodule

aquaxis_IPCORE/aq_axi_djpeg/aq_axi_djpeg.srcs/sources/aq_axi_djpeg_ctrl.v

@@ -0,0 +1,113 @@
+/*
+ * Copyright (C)2014-2015 AQUAXIS TECHNOLOGY.
+ *  Don't remove this header. 
+ * When you use this source, there is a need to inherit this header.
+ *
+ * License
+ *  For no commercial -
+ *   License:     The Open Software License 3.0
+ *   License URI: http://www.opensource.org/licenses/OSL-3.0
+ *
+ *  For commmercial -
+ *   License:     AQUAXIS License 1.0
+ *   License URI: http://www.aquaxis.com/licenses
+ *
+ * For further information please contact.
+ *	URI:    http://www.aquaxis.com/
+ *	E-Mail: info(at)aquaxis.com
+ */
+module aq_axi_djpeg_ctl(
+  input         RST_N,
+  input         CLK,
+
+  input         LOCAL_CS,
+  input         LOCAL_RNW,
+  output        LOCAL_ACK,
+  input [31:0]  LOCAL_ADDR,
+  input [3:0]   LOCAL_BE,
+  input [31:0]  LOCAL_WDATA,
+  output [31:0] LOCAL_RDATA,
+  
+  output        LOGIC_RST,
+  input         LOGIC_IDLE,
+  
+  input [15:0]  WIDTH,
+  input [15:0]  HEIGHT,
+  input [15:0]  PIXELX,
+  input [15:0]  PIXELY,
+
+  output [31:0] DEBUG 
+);
+
+  localparam A_STATUS    = 8'h00;
+  localparam A_SIZE      = 8'h04;
+  localparam A_PIXEL     = 8'h08;
+
+  wire        wr_ena, rd_ena, wr_ack;
+  reg         rd_ack;
+
+  reg [31:0]  reg_rdata;
+
+  reg         reg_rst;
+
+  assign wr_ena = (LOCAL_CS & ~LOCAL_RNW)?1'b1:1'b0;
+  assign rd_ena = (LOCAL_CS &  LOCAL_RNW)?1'b1:1'b0;
+  assign wr_ack = wr_ena;
+
+  // Write Register
+  always @(posedge CLK or negedge RST_N) begin
+    if(!RST_N) begin
+      reg_rst <= 1'b0;
+    end else begin
+      if(wr_ena) begin
+        case(LOCAL_ADDR[7:0] & 8'hFC)
+          A_STATUS: begin
+            reg_rst <= LOCAL_WDATA[31];
+          end
+          A_SIZE: begin
+          end
+          A_PIXEL: begin
+          end
+          default: begin
+          end
+        endcase
+      end
+    end
+  end
+
+  // Read Register
+  always @(posedge CLK or negedge RST_N) begin
+    if(!RST_N) begin
+      reg_rdata[31:0] <= 32'd0;
+      rd_ack <= 1'b0;
+    end else begin
+      rd_ack <= rd_ena;
+      if(rd_ena) begin
+        case(LOCAL_ADDR[7:0] & 8'hFC)
+          A_STATUS: begin
+            reg_rdata[31:0] <= {reg_rst, 30'd0, LOGIC_IDLE};
+          end
+          A_SIZE: begin
+            reg_rdata[31:0] <= {HEIGHT[15:0], WIDTH[15:0]};
+          end
+          A_PIXEL: begin
+            reg_rdata[31:0] <= {PIXELY[15:0], PIXELX[15:0]};
+          end
+          default: begin
+            reg_rdata[31:0] <= 32'd0;
+          end
+        endcase
+      end else begin
+        reg_rdata[31:0] <= 32'd0;
+      end
+    end
+  end
+  
+  assign LOGIC_RST = reg_rst;
+
+  assign LOCAL_ACK          = rd_ack | wr_ack;
+  assign LOCAL_RDATA[31:0]  = reg_rdata[31:0];
+
+  assign DEBUG[31:0] = {32'd0};
+
+endmodule

aquaxis_IPCORE/aq_axi_djpeg/aq_axi_djpeg.srcs/sources/aq_axi_lite_slave.v

@@ -0,0 +1,176 @@
+/*
+ * Copyright (C)2014-2015 AQUAXIS TECHNOLOGY.
+ *  Don't remove this header. 
+ * When you use this source, there is a need to inherit this header.
+ *
+ * License
+ *  For no commercial -
+ *   License:     The Open Software License 3.0
+ *   License URI: http://www.opensource.org/licenses/OSL-3.0
+ *
+ *  For commmercial -
+ *   License:     AQUAXIS License 1.0
+ *   License URI: http://www.aquaxis.com/licenses
+ *
+ * For further information please contact.
+ *	URI:    http://www.aquaxis.com/
+ *	E-Mail: info(at)aquaxis.com
+ */
+module aq_axi_lite_slave
+  #(
+    parameter     C_BASEADRS  = 32'h0000_0000,
+    parameter     C_ADRSWIDTH = 16
+    )
+  (
+    // AXI4 Lite Interface
+    input         ARESETN,
+    input         ACLK,
+    
+    // Write Address Channel
+    input [31:0]  S_AXI_AWADDR,
+    input [3:0]   S_AXI_AWCACHE,  // 4'b0011
+    input [2:0]   S_AXI_AWPROT,   // 3'b000
+    input         S_AXI_AWVALID,
+    output        S_AXI_AWREADY, 
+        
+    // Write Data Channel
+    input [31:0]  S_AXI_WDATA,
+    input [3:0]   S_AXI_WSTRB,
+    input         S_AXI_WVALID,
+    output        S_AXI_WREADY,
+        
+    // Write Response Channel
+    output        S_AXI_BVALID,
+    input         S_AXI_BREADY,
+    output [1:0]  S_AXI_BRESP,
+
+    // Read Address Channel
+    input [31:0]  S_AXI_ARADDR,
+    input [3:0]   S_AXI_ARCACHE,  // 4'b0011
+    input [2:0]   S_AXI_ARPROT,   // 3'b000
+    input         S_AXI_ARVALID,
+    output        S_AXI_ARREADY,
+
+    // Read Data Channel
+    output [31:0] S_AXI_RDATA,
+    output [1:0]  S_AXI_RRESP,
+    output        S_AXI_RVALID,
+    input         S_AXI_RREADY,
+    
+    // Local Interface
+    output        LOCAL_CS,
+    output        LOCAL_RNW,
+    input         LOCAL_ACK,
+    output [31:0] LOCAL_ADDR,
+    output [3:0]  LOCAL_BE,
+    output [31:0] LOCAL_WDATA,
+    input [31:0]  LOCAL_RDATA,
+    
+    output [31:0] DEBUG
+  );
+
+/*
+CACHE[3:0]
+WA RA C  B 
+0  0  0  0 Noncacheable and nonbufferable
+0  0  0  1 Bufferable only
+0  0  1  0 Cacheable, but do not allocate
+0  0  1  1 Cacheable and Bufferable, but do not allocate
+0  1  1  0 Cacheable write-through, allocate on reads only
+0  1  1  1 Cacheable write-back, allocate on reads only
+1  0  1  0 Cacheable write-through, allocate on write only
+1  0  1  1 Cacheable write-back, allocate on writes only
+1  1  1  0 Cacheable write-through, allocate on both reads and writes
+1  1  1  1 Cacheable write-back, allocate on both reads and writes
+
+PROR
+[2]:0:Data Access
+    1:Instruction Access
+[1]:0:Secure Access
+    1:NoSecure Access
+[0]:0:Privileged Access
+    1:Normal Access
+
+RESP
+00: OK
+01: EXOK
+10: SLVERR
+11: DECERR
+*/
+
+  localparam S_IDLE   = 2'd0;
+  localparam S_WRITE  = 2'd1;
+  localparam S_WRITE2 = 2'd2;
+  localparam S_READ   = 2'd3;
+
+  reg [1:0]   state;
+  reg         reg_rnw;
+  reg [31:0]  reg_addr, reg_wdata;
+  reg [3:0]   reg_be;
+   
+  always @( posedge ACLK or negedge ARESETN ) begin
+    if( !ARESETN ) begin
+      state     <= S_IDLE;
+      reg_rnw   <= 1'b0;
+      reg_addr  <= 32'd0;
+      reg_wdata <= 32'd0;
+      reg_be    <= 4'd0;
+    end else begin
+      case( state )
+        S_IDLE: begin
+          if( S_AXI_AWVALID && ( S_AXI_AWADDR[31:(32 - C_ADRSWIDTH)] == C_BASEADRS[31:(32 - C_ADRSWIDTH)] ) ) begin
+            reg_rnw   <= 1'b0;
+            reg_addr  <= S_AXI_AWADDR;
+            state     <= S_WRITE;
+          end else if( S_AXI_ARVALID && (S_AXI_ARADDR[31:(32 - C_ADRSWIDTH)] == C_BASEADRS[31:(32 - C_ADRSWIDTH)]) ) begin
+            reg_rnw   <= 1'b1;
+            reg_addr  <= S_AXI_ARADDR;
+            state     <= S_READ;
+          end
+        end
+        S_WRITE: begin
+          if( S_AXI_WVALID ) begin
+            state     <= S_WRITE2;
+            reg_wdata <= S_AXI_WDATA;
+            reg_be    <= S_AXI_WSTRB;
+          end
+        end
+        S_WRITE2: begin
+          if( LOCAL_ACK & S_AXI_BREADY ) begin
+            state     <= S_IDLE;
+          end
+        end
+        S_READ: begin
+          if( LOCAL_ACK & S_AXI_RREADY ) begin
+            state     <= S_IDLE;
+          end
+        end
+        default: begin
+          state        <= S_IDLE;
+        end
+      endcase
+    end
+  end
+   
+  // Local Interface
+  assign LOCAL_CS       = (( state == S_WRITE2 )?1'b1:1'b0) | (( state == S_READ )?1'b1:1'b0) | 1'b0;
+  assign LOCAL_RNW      = reg_rnw;
+  assign LOCAL_ADDR     = reg_addr;
+  assign LOCAL_BE       = reg_be;
+  assign LOCAL_WDATA    = reg_wdata;
+   
+  // Write Channel
+  assign S_AXI_AWREADY  = ( state == S_WRITE )?S_AXI_AWVALID:1'b0;
+  assign S_AXI_WREADY   = ( state == S_WRITE )?S_AXI_WVALID:1'b0;
+  assign S_AXI_BVALID   = ( state == S_WRITE2 )?LOCAL_ACK:1'b0;
+  assign S_AXI_BRESP    = 2'b00;
+   
+  // Read Channel
+  assign S_AXI_ARREADY  = ( state == S_READ )?S_AXI_ARVALID:1'b0;
+  assign S_AXI_RVALID   = ( state == S_READ )?LOCAL_ACK:1'b0;
+  assign S_AXI_RRESP    = 2'b00;
+  assign S_AXI_RDATA    = ( state == S_READ )?LOCAL_RDATA:32'd0;
+
+  // Debug
+  assign DEBUG[31:0]    = {24'd0, 1'd0, S_AXI_RVALID, S_AXI_ARREADY, LOCAL_ACK, LOCAL_RNW, LOCAL_CS, state[1:0]};
+endmodule

aquaxis_IPCORE/aq_axi_djpeg/aq_axi_djpeg.srcs/sources/aq_djpeg.v

@@ -0,0 +1,272 @@
+/*
+ * Copyright (C)2006-2015 AQUAXIS TECHNOLOGY.
+ *  Don't remove this header. 
+ * When you use this source, there is a need to inherit this header.
+ *
+ * License
+ *  For no commercial -
+ *   License:     The Open Software License 3.0
+ *   License URI: http://www.opensource.org/licenses/OSL-3.0
+ *
+ *  For commmercial -
+ *   License:     AQUAXIS License 1.0
+ *   License URI: http://www.aquaxis.com/licenses
+ *
+ * For further information please contact.
+ *	URI:    http://www.aquaxis.com/
+ *	E-Mail: info(at)aquaxis.com
+ */
+`timescale 1ps / 1ps
+
+module aq_djpeg(
+	input			rst,
+	input			clk,
+
+	// From FIFO
+	input [31:0]	DataIn,
+	input			DataInEnable,
+	output			DataInRead,
+
+	output			JpegDecodeIdle,	// Deocdeer Process Idle(1:Idle, 0:Run)
+
+	output			OutEnable,
+	output [15:0]	OutWidth,
+	output [15:0]	OutHeight,
+	output [15:0]	OutPixelX,
+	output [15:0]	OutPixelY,
+	output [7:0]	OutR,
+	output [7:0]	OutG,
+	output [7:0]	OutB
+);
+	wire [31:0]		JpegData;
+	wire			JpegDataEnable;
+	wire			JpegDecodeIdle;
+
+	wire			UseBit;
+	wire [6:0]		UseWidth;
+	wire			UseByte;
+	wire			UseWord;
+
+	wire			ImageEnable;
+	wire			EnableFF00;
+	wire			DataInFull;
+
+	//reg			 ProcessIdle;
+
+	wire			JpegDataEnableW;
+	
+	assign JpegDataEnable = (!DataInFull)?JpegDataEnableW:1'b0;
+
+	//--------------------------------------------------------------------------
+	// Read JPEG Data from FIFO
+	//--------------------------------------------------------------------------
+	aq_djpeg_regdata u_jpeg_regdata(
+		.rst				( rst				),
+		.clk				( clk				),
+
+		// Read Data
+		.DataIn			( DataIn			),
+		.DataInEnable		( DataInEnable	),
+		.DataInRead		( DataInRead		),
+
+		// DataOut
+		.DataOut			( JpegData			),
+		.DataOutEnable	( JpegDataEnableW	),
+
+		//
+		.ImageEnable		( ImageEnable		),
+		.ProcessIdle		( JpegDecodeIdle	),
+
+		// UseData
+		.UseBit			( UseBit			),
+		.UseWidth			( UseWidth			),
+		.UseByte			( UseByte			),
+		.UseWord			( UseWord			)
+		);
+
+	//--------------------------------------------------------------------------
+	// Read Maker from Jpeg Data
+	//--------------------------------------------------------------------------
+	wire			DqtEnable;
+	wire			DqtTable;
+	wire [5:0]		DqtCount;
+	wire [7:0]		DqtData;
+
+	wire			DhtEnable;
+	wire [1:0]		DhtTable;
+	wire [7:0]		DhtCount;
+	wire [7:0]		DhtData;
+
+	//
+	wire			HuffmanEnable;
+	wire [1:0]		HuffmanTable;
+	wire [3:0]		HuffmanCount;
+	wire [15:0]		HuffmanData;
+	wire [7:0]		HuffmanStart;
+
+	wire [11:0]		JpegBlockWidth;
+	wire [2:0]		JpegComp;
+
+	aq_djpeg_fsm u_jpeg_fsm(
+		.rst				( rst				),
+		.clk				( clk				),
+
+		// From FIFO
+		.DataInEnable		( JpegDataEnable	),
+		.DataIn			( JpegData			),
+
+		.JpegDecodeIdle	( JpegDecodeIdle	),
+
+		.OutWidth			( OutWidth			),
+		.OutHeight			( OutHeight		),
+		.OutBlockWidth	( JpegBlockWidth	),
+		.OutEnable			( OutEnable		),
+		.OutPixelX			( OutPixelX		),
+		.OutPixelY			( OutPixelY		),
+
+		//
+		.DqtEnable			( DqtEnable		),
+		.DqtTable			( DqtTable			),
+		.DqtCount			( DqtCount			),
+		.DqtData			( DqtData			),
+
+		//
+		.DhtEnable			( DhtEnable		),
+		.DhtTable			( DhtTable			),
+		.DhtCount			( DhtCount			),
+		.DhtData			( DhtData			),
+
+		//
+		.HuffmanEnable	( HuffmanEnable	),
+		.HuffmanTable		( HuffmanTable	),
+		.HuffmanCount		( HuffmanCount	),
+		.HuffmanData		( HuffmanData		),
+		.HuffmanStart		( HuffmanStart	),
+
+		//
+		.ImageEnable		( ImageEnable		),
+		.JpegComp			( JpegComp			),
+
+		//
+		.UseByte			( UseByte			),
+		.UseWord			( UseWord			)
+		);
+
+
+	wire			HmDecEnable;
+	wire [2:0]		HmDecColor;
+	wire			HmRead;
+	wire [4:0]		HmAddress;
+
+	wire [15:0]		HmDataA, HmDataB;
+
+	aq_djpeg_huffman u_jpeg_huffman(
+		.rst					( rst				),
+		.clk					( clk				),
+
+		.ProcessInit			( JpegDecodeIdle	),
+
+		// DQT Table
+		.DqtInEnable			( DqtEnable		),
+		.DqtInColor			( DqtTable			),
+		.DqtInCount			( DqtCount[5:0]	),
+		.DqtInData				( DqtData			),
+
+		// DHT Table
+		.DhtInEnable			( DhtEnable		),
+		.DhtInColor			( DhtTable			),
+		.DhtInCount			( DhtCount			),
+		.DhtInData				( DhtData			),
+
+		// Huffman Table
+		.HuffmanTableEnable	( HuffmanEnable	),
+		.HuffmanTableColor	( HuffmanTable	),
+		.HuffmanTableCount	( HuffmanCount	),
+		.HuffmanTableCode		( HuffmanData		),
+		.HuffmanTableStart	( HuffmanStart	),
+
+		// Huffman Decode
+		.DataInRun				( ImageEnable		),
+		.DataInEnable			( JpegDataEnable	),
+		.DataIn				( JpegData			),
+		.JpegComp				( JpegComp			),
+
+		// Output decode data
+		.DecodeUseBit			( UseBit			),
+		.DecodeUseWidth		( UseWidth			),
+
+		// Data Out
+		.DataOutEnable		( HmDecEnable		),
+		.DataOutRead			( HmRead			),
+		.DataOutAddress		( HmAddress		),
+		.DataOutColor			( HmDecColor		),
+		.DataOutA				( HmDataA			),
+		.DataOutB				( HmDataB			)
+	);
+
+	wire			DctEnable;
+	wire [2:0]		DctColor;
+	wire [2:0]		DctPage;
+	wire [1:0]		DctCount;
+	wire [8:0]		Dct0Data, Dct1Data;
+
+	wire [15:0]		DctWidth, DctHeight;
+	wire [11:0]		DctBlockX, DctBlockY;
+
+	wire			YCbCrIdle;
+
+	aq_djpeg_idct u_jpeg_idct(
+		.rst				( rst				),
+		.clk				( clk				),
+
+		.ProcessInit		( JpegDecodeIdle	),
+
+		.DataInEnable		( HmDecEnable		),
+		.DataInRead		( HmRead			),
+		.DataInAddress	( HmAddress		),
+		.DataInA			( HmDataA			),
+		.DataInB			( HmDataB			),
+
+		.DataOutEnable	( DctEnable		),
+		.DataOutPage		( DctPage			),
+		.DataOutCount		( DctCount			),
+		.Data0Out			( Dct0Data			),
+		.Data1Out			( Dct1Data			)
+		);
+
+	wire			ColorEnable;
+	wire [15:0]		ColorPixelX, ColorPixelY;
+	wire [7:0]		ColorR, ColorG, ColorB;
+	aq_djpeg_ycbcr u_jpeg_ycbcr(
+		.rst				( rst				),
+		.clk				( clk				),
+
+		.ProcessInit		( JpegDecodeIdle	),
+		.JpegComp			( JpegComp			),
+
+		.DataInEnable		( DctEnable		),
+		.DataInPage		( DctPage			),
+		.DataInCount		( DctCount			),
+		.DataInIdle		( YCbCrIdle		),
+		.Data0In			( Dct0Data			),
+		.Data1In			( Dct1Data			),
+		.DataInBlockWidth	( JpegBlockWidth	),
+		.DataInFull		( DataInFull		),
+
+		.OutEnable			( ColorEnable		),
+		.OutPixelX			( ColorPixelX		),
+		.OutPixelY			( ColorPixelY		),
+		.OutR				( ColorR			),
+		.OutG				( ColorG			),
+		.OutB				( ColorB			)
+	);
+	// OutData
+//	assign OutEnable	= (ImageEnable)?ColorEnable:1'b0;
+	assign OutEnable	= (ImageEnable && (ColorPixelX < OutWidth) && (ColorPixelY < OutHeight))?ColorEnable:1'b0;
+	assign OutPixelX	= (ImageEnable)?ColorPixelX:16'd0;
+	assign OutPixelY	= (ImageEnable)?ColorPixelY:16'd0;
+	assign OutR		= (ImageEnable)?ColorR:8'd0;
+	assign OutG		= (ImageEnable)?ColorG:8'd0;
+	assign OutB		= (ImageEnable)?ColorB:8'd0;
+
+endmodule

aquaxis_IPCORE/aq_axi_djpeg/aq_axi_djpeg.srcs/sources/aq_djpeg_dht.v

@@ -0,0 +1,92 @@
+/*
+ * Copyright (C)2006-2015 AQUAXIS TECHNOLOGY.
+ *  Don't remove this header. 
+ * When you use this source, there is a need to inherit this header.
+ *
+ * License
+ *  For no commercial -
+ *   License:     The Open Software License 3.0
+ *   License URI: http://www.opensource.org/licenses/OSL-3.0
+ *
+ *  For commmercial -
+ *   License:     AQUAXIS License 1.0
+ *   License URI: http://www.aquaxis.com/licenses
+ *
+ * For further information please contact.
+ *	URI:    http://www.aquaxis.com/
+ *	E-Mail: info(at)aquaxis.com
+ */
+`timescale 1ps / 1ps
+
+module aq_djpeg_dht(
+	input			rst,
+	input			clk,
+
+	input			DataInEnable,
+	input [1:0]	DataInColor,
+	input [7:0]	DataInCount,
+	input [7:0]	DataIn,
+
+	input [1:0]	ColorNumber,
+	input [7:0]	TableNumber,
+	output [3:0]	ZeroTable,
+	output [3:0]	WidhtTable
+);
+	// RAM
+	reg [7:0]	   DHT_Ydc [0:15];
+	reg [7:0]	   DHT_Yac [0:255];
+	reg [7:0]	   DHT_Cdc [0:15];
+	reg [7:0]	   DHT_Cac [0:255];
+
+	reg [7:0]	   ReadDataYdc;
+	reg [7:0]	   ReadDataYac;
+	reg [7:0]	   ReadDataCdc;
+	reg [7:0]	   ReadDataCac;
+
+	wire [7:0]	  ReadData;
+
+	// RAM
+	always @(posedge clk) begin
+		if((DataInEnable == 1'b1) & (DataInColor == 2'b00)) begin
+			DHT_Ydc[DataInCount[3:0]] <= DataIn;
+		end
+		if(DataInEnable ==1'b1 & DataInColor ==2'b01) begin
+			DHT_Yac[DataInCount] <= DataIn;
+		end
+		if(DataInEnable ==1'b1 & DataInColor ==2'b10) begin
+			DHT_Cdc[DataInCount[3:0]] <= DataIn;
+		end
+		if(DataInEnable ==1'b1 & DataInColor ==2'b11) begin
+			DHT_Cac[DataInCount] <= DataIn;
+		end
+	end
+
+	always @(posedge clk) begin
+		ReadDataYdc[7:0] <= DHT_Ydc[TableNumber[3:0]];
+		ReadDataYac[7:0] <= DHT_Yac[TableNumber];
+		ReadDataCdc[7:0] <= DHT_Cdc[TableNumber[3:0]];
+		ReadDataCac[7:0] <= DHT_Cac[TableNumber];
+	end
+
+	// Selector
+	function [7:0] ReadDataSel;
+		input [1:0]	ColorNumber;
+		input [7:0]	ReadDataYdc;
+		input [7:0]	ReadDataYac;
+		input [7:0]	ReadDataCdc;
+		input [7:0]	ReadDataCac;
+		begin
+			case (ColorNumber[1:0])
+			2'b00: ReadDataSel[7:0] = ReadDataYdc[7:0];
+			2'b01: ReadDataSel[7:0] = ReadDataYac[7:0];
+			2'b10: ReadDataSel[7:0] = ReadDataCdc[7:0];
+			2'b11: ReadDataSel[7:0] = ReadDataCac[7:0];
+			endcase
+		end
+	endfunction
+
+	assign ReadData = ReadDataSel(ColorNumber, ReadDataYdc, ReadDataYac, ReadDataCdc, ReadDataCac);
+
+	assign ZeroTable  = ReadData[7:4];
+	assign WidhtTable = ReadData[3:0];
+endmodule

aquaxis_IPCORE/aq_axi_djpeg/aq_axi_djpeg.srcs/sources/aq_djpeg_dqt.v

@@ -0,0 +1,59 @@
+/*
+ * Copyright (C)2006-2015 AQUAXIS TECHNOLOGY.
+ *  Don't remove this header. 
+ * When you use this source, there is a need to inherit this header.
+ *
+ * License
+ *  For no commercial -
+ *   License:     The Open Software License 3.0
+ *   License URI: http://www.opensource.org/licenses/OSL-3.0
+ *
+ *  For commmercial -
+ *   License:     AQUAXIS License 1.0
+ *   License URI: http://www.aquaxis.com/licenses
+ *
+ * For further information please contact.
+ *	URI:    http://www.aquaxis.com/
+ *	E-Mail: info(at)aquaxis.com
+ */
+`timescale 1ps / 1ps
+
+module aq_djpeg_dqt(
+    input           rst,
+    input           clk,
+
+    input           DataInEnable,
+    input           DataInColor,
+    input [5:0]     DataInCount,
+    input [7:0]     DataIn,
+
+    input           TableColor,
+    input  [5:0]    TableNumber,
+    output [7:0]    TableData
+);
+    // RAM
+    reg [7:0]       DQT_Y [0:63];
+    reg [7:0]       DQT_C [0:63];
+
+    // RAM
+    always @(posedge clk) begin
+        if(DataInEnable ==1'b1 && DataInColor ==1'b0) begin
+            DQT_Y[DataInCount] <= DataIn;
+        end
+        if(DataInEnable ==1'b1 && DataInColor ==1'b1) begin
+            DQT_C[DataInCount] <= DataIn;
+        end
+    end
+
+    reg [7:0] TableDataY;
+    reg [7:0] TableDataC;
+
+    // RAM out
+    always @(posedge clk) begin
+        TableDataY <= DQT_Y[TableNumber];
+        TableDataC <= DQT_C[TableNumber];
+    end
+
+    // Selector
+    assign TableData = (TableColor)?TableDataC:TableDataY;
+endmodule

aquaxis_IPCORE/aq_axi_djpeg/aq_axi_djpeg.srcs/sources/aq_djpeg_fsm.v

@@ -0,0 +1,470 @@
+/*
+ * Copyright (C)2006-2015 AQUAXIS TECHNOLOGY.
+ *  Don't remove this header. 
+ * When you use this source, there is a need to inherit this header.
+ *
+ * License
+ *  For no commercial -
+ *   License:     The Open Software License 3.0
+ *   License URI: http://www.opensource.org/licenses/OSL-3.0
+ *
+ *  For commmercial -
+ *   License:     AQUAXIS License 1.0
+ *   License URI: http://www.aquaxis.com/licenses
+ *
+ * For further information please contact.
+ *	URI:    http://www.aquaxis.com/
+ *	E-Mail: info(at)aquaxis.com
+ */
+`timescale 1ps / 1ps
+
+module aq_djpeg_fsm(
+	input			rst,
+	input			clk,
+
+	// From FIFO
+	input			DataInEnable,
+	input [31:0]	DataIn,
+
+	output			JpegDecodeIdle,	// Deocder Process Idle(1:Idle, 0:Run)
+
+	//
+	output [15:0]	OutWidth,
+	output [15:0]	OutHeight,
+	output [11:0]	OutBlockWidth,
+	input			OutEnable,
+	input [15:0]	OutPixelX,
+	input [15:0]	OutPixelY,
+
+	//
+	output			DqtEnable,
+	output			DqtTable,
+	output [5:0]	DqtCount,
+	output [7:0]	DqtData,
+
+	//
+	output			DhtEnable,
+	output [1:0]	DhtTable,
+	output [7:0]	DhtCount,
+	output [7:0]	DhtData,
+
+	//
+	output			HuffmanEnable,
+	output [1:0]	HuffmanTable,
+	output [3:0]	HuffmanCount,
+	output [15:0]	HuffmanData,
+	output [7:0]	HuffmanStart,
+
+	//
+	output			ImageEnable,
+	output [2:0]	JpegComp,
+
+	//
+	output			UseByte,
+	output			UseWord
+);
+
+	//--------------------------------------------------------------------------
+	// Read Maker from Jpeg Data
+	//--------------------------------------------------------------------------
+	// State Machine localparam
+	localparam S_Idle					= 5'd0;
+	localparam S_GetMarker			= 5'd1;
+	localparam S_ImageData			= 5'd2;
+	// APP Segment
+	localparam S_APPLength			= 5'd3;
+	localparam S_APPRead				= 5'd4;
+	// DQT Segment
+	localparam S_DQTLength			= 5'd5;
+	localparam S_DQTTable			= 5'd6;
+	localparam S_DQTRead				= 5'd7;
+	// DHT Segmen
+	localparam S_DHTLength			= 5'd8;
+	localparam S_DHTTable			= 5'd9;
+	localparam S_DHTMakeHm0			= 5'd10;
+	localparam S_DHTMakeHm1			= 5'd11;
+	localparam S_DHTMakeHm2			= 5'd12;
+	localparam S_DHTReadTable		= 5'd13;
+	// SOS Segment
+	localparam S_SOSLength			= 5'd14;
+	localparam S_SOSRead0			= 5'd15;
+	localparam S_SOSRead1			= 5'd16;
+	localparam S_SOSRead2			= 5'd17;
+	localparam S_SOSRead3			= 5'd18;
+	localparam S_SOSRead4			= 5'd19;
+	// SOF Segment
+	localparam S_SOFLength			= 5'd20;
+	localparam S_SOFRead0			= 5'd21;
+	localparam S_SOFReadY			= 5'd22;
+	localparam S_SOFReadX			= 5'd23;
+	localparam S_SOFReadComp			= 5'd24;
+	localparam S_SOFReadCompColor	= 5'd25;
+	localparam S_SOFReadCompColor0	= 5'd26;
+	localparam S_SOFReadCompColor1	= 5'd27;
+	localparam S_SOFReadCompColor2	= 5'd28;
+	localparam S_SOFMakeBlock0		= 5'd29;
+	localparam S_SOFMakeBlock1		= 5'd30;
+
+	reg [4:0]		State;
+	//wire			ImageEnable;
+	reg [15:0]		ReadCount;
+
+	reg [15:0]		JpegWidth;
+	reg [15:0]		JpegHeight;
+
+	reg				ReadDqtTable;
+	reg [1:0]		ReadDhtTable;
+
+	reg [15:0]		HmShift;
+	reg [15:0]		HmData;
+	reg [7:0]		HmMax;
+	reg [7:0]		HmCount;
+	reg				HmEnable;
+
+	reg [2:0]		JpegComp;
+	reg [15:0]		JpegBlockWidth;
+	reg [15:0]		JpegBlockHeight;
+
+	reg				ImageEnable;
+
+	always @(posedge clk or negedge rst) begin
+		if(!rst) begin
+			State				<= S_Idle;
+			ReadCount			<= 16'd0;
+			JpegWidth			<= 16'd0;
+			JpegHeight			<= 16'd0;
+			ReadDqtTable		<= 1'b0;
+			ReadDhtTable		<= 2'd0;
+			HmShift			<= 16'd0;
+			HmData				<= 16'd0;
+			HmMax				<= 8'd0;
+			HmCount			<= 8'd0;
+			HmEnable			<= 1'b0;
+			JpegBlockWidth	<= 16'd0;
+			JpegBlockHeight	<= 16'd0;
+			JpegComp			<= 3'd0;
+			ImageEnable		<= 1'b0;
+		end else begin
+			case(State)
+				S_Idle: begin
+					if(DataInEnable == 1'b1) begin
+						State	<= S_GetMarker;
+					end
+				end
+
+				// Get Marker(with Header)
+				S_GetMarker: begin
+					if(DataInEnable == 1'b1) begin
+						case(DataIn[31:16])
+							16'hFFD8: begin		// SOI Segment
+								State <= S_GetMarker;
+							end
+							16'hFFE0: begin		// APP0 Segment
+								State <= S_APPLength;
+							end
+							16'hFFDB: begin		// DQT Segment
+								State <= S_DQTLength;
+							end
+							16'hFFC4: begin		// DHT Segment
+								State <= S_DHTLength;
+							end
+							16'hFFC0: begin		// SOF0 Segment
+								State <= S_SOFLength;
+							end
+							16'hFFDA: begin		// SOS Segment
+								State <= S_SOSLength;
+							end
+							//16'hFFDD: begin		// DRI Segment
+							//		State <= S_DRI;
+							//end
+							//16'hFFDx: begin		// RSTn Segment
+							//		State <= S_RST;
+							//end
+							//16'hFFD9: begin		// EOI Segment
+							//		State <= S_EOI;
+							//end
+							default: begin
+								State <= S_APPLength;
+							end
+						endcase
+					end
+				end
+
+				// APP Segment
+				S_APPLength: begin
+					if(DataInEnable == 1'b1) begin
+						ReadCount	<= DataIn[31:16] -16'd2;
+						State		<= S_APPRead;
+					end
+				end
+				S_APPRead: begin
+					if(DataInEnable == 1'b1) begin
+						if(ReadCount == 16'd1) begin
+							State		<= S_GetMarker;
+						end else begin
+							ReadCount	<= ReadCount -16'd1;
+						end
+					end
+				end
+
+				// DQT Segment
+				S_DQTLength: begin
+					if(DataInEnable == 1'b1) begin
+						State		<= S_DQTTable;
+						ReadCount	<= DataIn[31:16] -16'd2;
+					end
+				end
+				S_DQTTable: begin
+					if(DataInEnable == 1'b1) begin
+						State			<= S_DQTRead;
+						ReadDqtTable	<= DataIn[24];
+						ReadCount		<= 16'd0;
+					end
+				end
+				S_DQTRead: begin
+					if(DataInEnable == 1'b1) begin
+						if(ReadCount ==63) begin
+							State		<= S_GetMarker;
+						end
+						ReadCount		<= ReadCount +16'd1;
+					end
+				end
+
+				// DHT Segment
+				S_DHTLength: begin
+					if(DataInEnable == 1'b1) begin
+						State			<= S_DHTTable;
+						ReadCount		<= DataIn[31:16];
+					end
+				end
+				S_DHTTable: begin
+					if(DataInEnable == 1'b1) begin
+						State <= S_DHTMakeHm0;
+						case(DataIn[31:24])
+							8'h00: ReadDhtTable <= 2'b00;
+							8'h10: ReadDhtTable <= 2'b01;
+							8'h01: ReadDhtTable <= 2'b10;
+							8'h11: ReadDhtTable <= 2'b11;
+						endcase
+					end
+					HmShift		<= 16'h8000;
+					HmData			<= 16'h0000;
+					HmMax			<= 8'h00;
+					ReadCount		<= 16'd0;
+				end
+				S_DHTMakeHm0: begin
+					if(DataInEnable == 1'b1) begin
+						State		<= S_DHTMakeHm1;
+						HmCount	<= DataIn[31:24];
+					end
+					HmEnable		<= 1'b0;
+				end
+				S_DHTMakeHm1: begin
+					State	<= S_DHTMakeHm2;
+					HmMax	<= HmMax + HmCount;
+				end
+				S_DHTMakeHm2: begin
+					if(HmCount != 0) begin
+						HmData	<= HmData + HmShift;
+						HmCount <= HmCount -8'd1;
+					end else begin
+						if(ReadCount == 15) begin
+							State		<= S_DHTReadTable;
+							HmCount	<= 8'h00;
+						end else begin
+							HmEnable	<= 1'b1;
+							State		<= S_DHTMakeHm0;
+							ReadCount	<= ReadCount +16'd1;
+						end
+						HmShift <= HmShift >> 1;
+					end
+				end
+				S_DHTReadTable: begin
+					HmEnable	<= 1'b0;
+					if(DataInEnable == 1'b1) begin
+						if(HmMax == HmCount +1) begin
+							State	<= S_GetMarker;
+						end
+						HmCount	<= HmCount +8'd1;
+					end
+				end
+
+				// SOS Segment
+				S_SOSLength: begin
+					if(DataInEnable == 1'b1) begin
+						State		<= S_SOSRead0;
+						ReadCount	<= DataIn[31:16];
+					end
+				end
+				S_SOSRead0: begin
+					if(DataInEnable == 1'b1) begin
+						State		<= S_SOSRead1;
+						ReadCount	<= {8'h00,DataIn[31:24]};
+					end
+				end
+				S_SOSRead1: begin
+					if(DataInEnable == 1'b1) begin
+						if(ReadCount == 1) begin
+							State		<= S_SOSRead2;
+						end else begin
+							ReadCount	<= ReadCount -16'd1;
+						end
+					end
+				end
+				S_SOSRead2: begin
+					if(DataInEnable == 1'b1) begin
+						State	<= S_SOSRead3;
+					end
+				end
+				S_SOSRead3: begin
+					if(DataInEnable == 1'b1) begin
+						State	<= S_SOSRead4;
+					end
+				end
+				S_SOSRead4: begin
+					if(DataInEnable == 1'b1) begin
+						State			<= S_ImageData;
+						ImageEnable	<= 1'b1;
+					end
+				end
+
+				// SOF0 Segment
+				S_SOFLength: begin
+					if(DataInEnable == 1'b1) begin
+						State		<= S_SOFRead0;
+						ReadCount	<= DataIn[31:16];
+					end
+				end
+				S_SOFRead0: begin
+					if(DataInEnable == 1'b1) begin
+						State	<= S_SOFReadY;
+					end
+				end
+				S_SOFReadY: begin
+					if(DataInEnable == 1'b1) begin
+						State				<= S_SOFReadX;
+						JpegHeight			<= DataIn[31:16];
+						JpegBlockHeight	<= DataIn[31:16];
+					end
+				end
+				S_SOFReadX: begin
+					if(DataInEnable == 1'b1) begin
+						State				<= S_SOFReadComp;
+						JpegWidth			<= DataIn[31:16];
+						JpegBlockWidth	<= DataIn[31:16];
+						ReadCount			<= 16'd0;
+					end
+				end
+				S_SOFReadComp: begin
+					// コンポーネント数
+					// 1:グレースケール
+					// 3:YCbCr or YIQ
+					// 4:CMYK
+					if(DataInEnable == 1'b1) begin
+						State			<= S_SOFReadCompColor;
+						JpegComp		<= DataIn[26:24];
+						if(ReadCount == 9) begin
+						end else begin
+							ReadCount	<= ReadCount +16'd1;
+						end
+					end
+				end
+				S_SOFReadCompColor: begin
+					State			<= S_SOFReadCompColor0;
+					ReadCount		<= {13'd0, JpegComp[2:0]} - 16'd1;
+				end
+				S_SOFReadCompColor0: begin
+					if(DataInEnable == 1'b1) begin
+						State			<= S_SOFReadCompColor1;
+					end
+				end
+				S_SOFReadCompColor1: begin
+					if(DataInEnable == 1'b1) begin
+						State			<= S_SOFReadCompColor2;
+					end
+				end
+				S_SOFReadCompColor2: begin
+					if(DataInEnable == 1'b1) begin
+						if(ReadCount == 0) begin
+							State			<= S_SOFMakeBlock0;
+						end else begin
+							ReadCount		<= ReadCount -16'd1;
+							State			<= S_SOFReadCompColor0;
+						end
+					end
+				end
+				S_SOFMakeBlock0:begin
+					State				<= S_SOFMakeBlock1;
+					if(JpegComp == 3) begin
+						// コンポーネント数が3の場合、16x16が1ブロック
+						JpegBlockWidth	<= JpegBlockWidth	+16'd15;
+						JpegBlockHeight	<= JpegBlockHeight +16'd15;
+					end else begin
+						// コンポーネント数が1の場合、32x8が1ブロック
+						JpegBlockWidth	<= JpegBlockWidth	+16'd31;
+						JpegBlockHeight	<= JpegBlockHeight +16'd7;
+					end
+				end
+				S_SOFMakeBlock1:begin
+					State				<= S_GetMarker;
+					if(JpegComp == 3) begin
+						// コンポーネント数が3の場合、16x16が1ブロック
+						JpegBlockWidth	<= JpegBlockWidth	>> 4;
+						JpegBlockHeight	<= JpegBlockHeight >> 4;
+					end else begin
+						// コンポーネント数が1の場合、32x8が1ブロック
+						JpegBlockWidth	<= JpegBlockWidth	>> 5;
+						JpegBlockHeight	<= JpegBlockHeight >> 3;
+					end
+				end
+
+				// Image Process
+				S_ImageData: begin
+					if(OutEnable & (JpegWidth == (OutPixelX +1)) & (JpegHeight == (OutPixelY +1))) begin
+						State			<= S_Idle;
+						ImageEnable	<= 1'b0;
+					end
+				end
+			endcase
+		end
+	end
+
+	assign UseByte = (DataInEnable == 1'b1) & ((State == S_APPRead) |
+												(State == S_DQTRead) | (State == S_DQTTable) |
+												(State == S_DHTTable) | (State == S_DHTMakeHm0) | (State == S_DHTReadTable) |
+												(State == S_SOSRead0) | (State == S_SOSRead2) | (State == S_SOSRead3) | (State == S_SOSRead4) |
+												(State == S_SOFRead0) | (State == S_SOFReadComp) | 
+												(State == S_SOFReadComp) | (State == S_SOFReadCompColor0) | (State == S_SOFReadCompColor1) | (State == S_SOFReadCompColor2)
+												);
+	assign UseWord = (DataInEnable == 1'b1) & ((State == S_GetMarker) |
+												(State == S_APPLength) |
+												(State == S_DQTLength) |
+												(State == S_DHTLength) |
+												(State == S_SOSLength) | (State == S_SOSRead1) |
+												(State == S_SOFLength) | (State == S_SOFReadX) | (State == S_SOFReadY)
+												);
+
+	assign JpegDecodeIdle	= (State == S_Idle);
+	//assign ImageEnable		= (State == S_ImageData);
+
+	assign OutWidth		= JpegWidth;
+	assign OutHeight		= JpegHeight;
+	assign OutBlockWidth	= JpegBlockWidth[11:0];
+
+	assign DqtEnable		= (State == S_DQTRead);
+	assign DqtTable		= ReadDqtTable;
+	assign DqtCount		= ReadCount[5:0];
+	assign DqtData		= DataIn[31:24];
+
+	assign DhtEnable		= (State == S_DHTReadTable);
+	assign DhtTable		= ReadDhtTable;
+	assign DhtCount		= HmCount;
+	assign DhtData		= DataIn[31:24];
+
+	assign HuffmanEnable	= HmEnable;
+	assign HuffmanTable	= ReadDhtTable;
+	assign HuffmanCount	= ReadCount[3:0];
+	assign HuffmanData	= HmData;
+	assign HuffmanStart	= HmMax;
+
+endmodule

aquaxis_IPCORE/aq_axi_djpeg/aq_axi_djpeg.srcs/sources/aq_djpeg_hm_decode.v

@@ -0,0 +1,755 @@
+/*
+ * Copyright (C)2006-2015 AQUAXIS TECHNOLOGY.
+ *  Don't remove this header. 
+ * When you use this source, there is a need to inherit this header.
+ *
+ * License
+ *  For no commercial -
+ *   License:     The Open Software License 3.0
+ *   License URI: http://www.opensource.org/licenses/OSL-3.0
+ *
+ *  For commmercial -
+ *   License:     AQUAXIS License 1.0
+ *   License URI: http://www.aquaxis.com/licenses
+ *
+ * For further information please contact.
+ *	URI:    http://www.aquaxis.com/
+ *	E-Mail: info(at)aquaxis.com
+ */
+`timescale 1ps / 1ps
+
+module aq_djpeg_hm_decode(
+	input			rst,
+	input			clk,					// Reset and Clock
+
+	// Huffman Table
+	input			HuffmanTableEnable,	// Table Data In Enable
+	input [1:0]	HuffmanTableColor,	// Huffman Table Color Number
+	input [3:0]	HuffmanTableCount,	// Table Number
+	input [15:0]	HuffmanTableCode,		// Huffman Table Data
+	input [7:0]	HuffmanTableStart,	// Huffman Table Start Number
+
+	// Huffman Decode
+	input			DataInRun,				// Data In Start
+	input			DataInEnable,			// Data In Enable
+	input [31:0]	DataIn,				// Data In
+	input [2:0]	JpegComp,
+
+	// DHT table
+	output [1:0]	DhtColor,				// Color Number
+	output [7:0]	DhtNumber,				// Decode Dht Number
+	input [3:0]	DhtZero,				// Zero Count of Dht Number
+	input [3:0]	DhtWidth,				// Data Width of Dht Number
+
+	// DQT Table
+	output			DqtColor,				// Color Number
+	output [5:0]	DqtNumber,				// Dqt Number
+	input [7:0]	DqtData,				// Dqt Data
+
+	input			DataOutIdle,
+	output			DataOutEnable,
+	output [2:0]	DataOutColor,
+
+	// Output decode data
+	output			DecodeUseBit,			// Used Data Bit
+	output [6:0]	DecodeUseWidth,		// Used Data Width
+	output			DecodeEnable,			// Data Out Enable
+	output [2:0]	DecodeColor,
+	output [5:0]	DecodeCount,
+	output [3:0]	DecodeZero,			// Data Out with Zero Count
+	output [15:0]	DecodeCode				// Data Out with Code
+);
+	//--------------------------------------------------------------------------
+	// Register Huffman Table(YCbCr)
+	//--------------------------------------------------------------------------
+	// Y-DC Huffman Table
+	reg [15:0]		HuffmanTable0r [0:15];	// Y-DC Huffman Table
+	reg [15:0]		HuffmanTable1r [0:15];	// Y-AC Huffman Table
+	reg [15:0]		HuffmanTable2r [0:15];	// C-DC Huffman Table
+	reg [15:0]		HuffmanTable3r [0:15];	// C-AC Huffman Table
+
+	reg [7:0]		HuffmanNumber0r [0:15];	// Y-DC Huffman Number
+	reg [7:0]		HuffmanNumber1r [0:15];	// Y-AC Huffman Number
+	reg [7:0]		HuffmanNumber2r [0:15];	// C-DC Huffman Number
+	reg [7:0]		HuffmanNumber3r [0:15];	// C-AC Huffman Number
+
+	always @(posedge clk or negedge rst) begin
+		if(!rst) begin
+			HuffmanTable0r[0]		<= 16'h0000;
+			HuffmanNumber0r[0]	<=	8'h00;
+			HuffmanTable1r[0]		<= 16'h0000;
+			HuffmanNumber1r[0]	<=	8'h00;
+			HuffmanTable2r[0]		<= 16'h0000;
+			HuffmanNumber2r[0]	<=	8'h00;
+			HuffmanTable3r[0]		<= 16'h0000;
+			HuffmanNumber3r[0]	<=	8'h00;
+
+			HuffmanTable0r[1]		<= 16'h0000;
+			HuffmanNumber0r[1]	<=	8'h00;
+			HuffmanTable1r[1]		<= 16'h0000;
+			HuffmanNumber1r[1]	<=	8'h00;
+			HuffmanTable2r[1]		<= 16'h0000;
+			HuffmanNumber2r[1]	<=	8'h00;
+			HuffmanTable3r[1]		<= 16'h0000;
+			HuffmanNumber3r[1]	<=	8'h00;
+
+			HuffmanTable0r[2]		<= 16'h0000;
+			HuffmanNumber0r[2]	<=	8'h00;
+			HuffmanTable1r[2]		<= 16'h0000;
+			HuffmanNumber1r[2]	<=	8'h00;
+			HuffmanTable2r[2]		<= 16'h0000;
+			HuffmanNumber2r[2]	<=	8'h00;
+			HuffmanTable3r[2]		<= 16'h0000;
+			HuffmanNumber3r[2]	<=	8'h00;
+
+			HuffmanTable0r[3]		<= 16'h0000;
+			HuffmanNumber0r[3]	<=	8'h00;
+			HuffmanTable1r[3]		<= 16'h0000;
+			HuffmanNumber1r[3]	<=	8'h00;
+			HuffmanTable2r[3]		<= 16'h0000;
+			HuffmanNumber2r[3]	<=	8'h00;
+			HuffmanTable3r[3]		<= 16'h0000;
+			HuffmanNumber3r[3]	<=	8'h00;
+
+			HuffmanTable0r[4]		<= 16'h0000;
+			HuffmanNumber0r[4]	<=	8'h00;
+			HuffmanTable1r[4]		<= 16'h0000;
+			HuffmanNumber1r[4]	<=	8'h00;
+			HuffmanTable2r[4]		<= 16'h0000;
+			HuffmanNumber2r[4]	<=	8'h00;
+			HuffmanTable3r[4]		<= 16'h0000;
+			HuffmanNumber3r[4]	<=	8'h00;
+
+			HuffmanTable0r[5]		<= 16'h0000;
+			HuffmanNumber0r[5]	<=	8'h00;
+			HuffmanTable1r[5]		<= 16'h0000;
+			HuffmanNumber1r[5]	<=	8'h00;
+			HuffmanTable2r[5]		<= 16'h0000;
+			HuffmanNumber2r[5]	<=	8'h00;
+			HuffmanTable3r[5]		<= 16'h0000;
+			HuffmanNumber3r[5]	<=	8'h00;
+
+			HuffmanTable0r[6]		<= 16'h0000;
+			HuffmanNumber0r[6]	<=	8'h00;
+			HuffmanTable1r[6]		<= 16'h0000;
+			HuffmanNumber1r[6]	<=	8'h00;
+			HuffmanTable2r[6]		<= 16'h0000;
+			HuffmanNumber2r[6]	<=	8'h00;
+			HuffmanTable3r[6]		<= 16'h0000;
+			HuffmanNumber3r[6]	<=	8'h00;
+
+			HuffmanTable0r[7]		<= 16'h0000;
+			HuffmanNumber0r[7]	<=	8'h00;
+			HuffmanTable1r[7]		<= 16'h0000;
+			HuffmanNumber1r[7]	<=	8'h00;
+			HuffmanTable2r[7]		<= 16'h0000;
+			HuffmanNumber2r[7]	<=	8'h00;
+			HuffmanTable3r[7]		<= 16'h0000;
+			HuffmanNumber3r[7]	<=	8'h00;
+
+			HuffmanTable0r[8]		<= 16'h0000;
+			HuffmanNumber0r[8]	<=	8'h00;
+			HuffmanTable1r[8]		<= 16'h0000;
+			HuffmanNumber1r[8]	<=	8'h00;
+			HuffmanTable2r[8]		<= 16'h0000;
+			HuffmanNumber2r[8]	<=	8'h00;
+			HuffmanTable3r[8]		<= 16'h0000;
+			HuffmanNumber3r[8]	<=	8'h00;
+
+			HuffmanTable0r[9]		<= 16'h0000;
+			HuffmanNumber0r[9]	<=	8'h00;
+			HuffmanTable1r[9]		<= 16'h0000;
+			HuffmanNumber1r[9]	<=	8'h00;
+			HuffmanTable2r[9]		<= 16'h0000;
+			HuffmanNumber2r[9]	<=	8'h00;
+			HuffmanTable3r[9]		<= 16'h0000;
+			HuffmanNumber3r[9]	<=	8'h00;
+
+			HuffmanTable0r[10]	<= 16'h0000;
+			HuffmanNumber0r[10]	<=	8'h00;
+			HuffmanTable1r[10]	<= 16'h0000;
+			HuffmanNumber1r[10]	<=	8'h00;
+			HuffmanTable2r[10]	<= 16'h0000;
+			HuffmanNumber2r[10]	<=	8'h00;
+			HuffmanTable3r[10]	<= 16'h0000;
+			HuffmanNumber3r[10]	<=	8'h00;
+
+			HuffmanTable0r[11]	<= 16'h0000;
+			HuffmanNumber0r[11]	<=	8'h00;
+			HuffmanTable1r[11]	<= 16'h0000;
+			HuffmanNumber1r[11]	<=	8'h00;
+			HuffmanTable2r[11]	<= 16'h0000;
+			HuffmanNumber2r[11]	<=	8'h00;
+			HuffmanTable3r[11]	<= 16'h0000;
+			HuffmanNumber3r[11]	<=	8'h00;
+
+			HuffmanTable0r[12]	<= 16'h0000;
+			HuffmanNumber0r[12]	<=	8'h00;
+			HuffmanTable1r[12]	<= 16'h0000;
+			HuffmanNumber1r[12]	<=	8'h00;
+			HuffmanTable2r[12]	<= 16'h0000;
+			HuffmanNumber2r[12]	<=	8'h00;
+			HuffmanTable3r[12]	<= 16'h0000;
+			HuffmanNumber3r[12]	<=	8'h00;
+
+			HuffmanTable0r[13]	<= 16'h0000;
+			HuffmanNumber0r[13]	<=	8'h00;
+			HuffmanTable1r[13]	<= 16'h0000;
+			HuffmanNumber1r[13]	<=	8'h00;
+			HuffmanTable2r[13]	<= 16'h0000;
+			HuffmanNumber2r[13]	<=	8'h00;
+			HuffmanTable3r[13]	<= 16'h0000;
+			HuffmanNumber3r[13]	<=	8'h00;
+
+			HuffmanTable0r[14]	<= 16'h0000;
+			HuffmanNumber0r[14]	<=	8'h00;
+			HuffmanTable1r[14]	<= 16'h0000;
+			HuffmanNumber1r[14]	<=	8'h00;
+			HuffmanTable2r[14]	<= 16'h0000;
+			HuffmanNumber2r[14]	<=	8'h00;
+			HuffmanTable3r[14]	<= 16'h0000;
+			HuffmanNumber3r[14]	<=	8'h00;
+
+			HuffmanTable0r[15]	<= 16'h0000;
+			HuffmanNumber0r[15]	<=	8'h00;
+			HuffmanTable1r[15]	<= 16'h0000;
+			HuffmanNumber1r[15]	<=	8'h00;
+			HuffmanTable2r[15]	<= 16'h0000;
+			HuffmanNumber2r[15]	<=	8'h00;
+			HuffmanTable3r[15]	<= 16'h0000;
+			HuffmanNumber3r[15]	<=	8'h00;
+		end else begin
+			if(HuffmanTableEnable ==2'b1) begin
+				if(HuffmanTableColor ==2'b00) begin
+					HuffmanTable0r[HuffmanTableCount]	<= HuffmanTableCode;
+					HuffmanNumber0r[HuffmanTableCount]	<= HuffmanTableStart;
+				end else if(HuffmanTableColor ==2'b01) begin
+					HuffmanTable1r[HuffmanTableCount]	<= HuffmanTableCode;
+					HuffmanNumber1r[HuffmanTableCount]	<= HuffmanTableStart;
+				end else if(HuffmanTableColor ==2'b10) begin
+					HuffmanTable2r[HuffmanTableCount]	<= HuffmanTableCode;
+					HuffmanNumber2r[HuffmanTableCount]	<= HuffmanTableStart;
+				end else begin
+					HuffmanTable3r[HuffmanTableCount]	<= HuffmanTableCode;
+					HuffmanNumber3r[HuffmanTableCount]	<= HuffmanTableStart;
+				end
+			end
+		end
+	end
+
+	//--------------------------------------------------------------------------
+	// Decode Process
+	//--------------------------------------------------------------------------
+	reg [3:0]	Process;		// Process State
+	reg [31:0]	ProcessData;	// Data
+
+	// Huffman Table
+	reg [15:0]	HuffmanTable [0:15];
+	// Huffman Table Number
+	reg [7:0]	HuffmanNumber [0:15];
+
+	reg [15:0]	Place;			// Place bit
+	reg [15:0]	TableCode;		// Table Code
+	reg [7:0]	NumberCode;	// Start Number of Table Code
+	reg [3:0]	CodeNumber;	// Huffman code width
+	reg [15:0]	DataNumber;	// Huffman code
+
+	reg [2:0]	ProcessColor;
+	reg [5:0]	ProcessCount;
+
+	reg		 OutEnable;		// Output Enable
+	reg [3:0]	OutZero;		// Output Zero Count
+	reg [15:0]	OutCode;		// Output Data Code
+	wire [15:0] OutCodeP;		// Output Data Code
+
+	reg [4:0]	UseWidth;		// Output used width
+
+//	reg				 DataOutEnable;
+	reg [2:0]	DataOutColor;
+
+	reg signed [31:0] PreData [0:2];
+
+	wire [15:0] SubCode;
+
+	localparam ProcIdle	= 4'h0;
+	localparam Phase1	= 4'h1;
+	localparam Phase2	= 4'h2;
+	localparam Phase3	= 4'h3;
+	localparam Phase4	= 4'h4;
+	localparam Phase5	= 4'h5;
+	localparam Phase6	= 4'h6;
+	localparam Phase7	= 4'h7;
+	localparam Phase8	= 4'h8;
+
+	function [15:0] OutCodePSel;
+		input [3:0]		DhtWidth;
+		input [31:0]	 ProcessData;
+		begin
+			case (DhtWidth)
+				4'h0: OutCodePSel = 16'h0000;
+				4'h1: OutCodePSel = {15'h0000,ProcessData[31]};
+				4'h2: OutCodePSel = {14'h0000,ProcessData[31:30]};
+				4'h3: OutCodePSel = {13'h0000,ProcessData[31:29]};
+				4'h4: OutCodePSel = {12'h000, ProcessData[31:28]};
+				4'h5: OutCodePSel = {11'h000, ProcessData[31:27]};
+				4'h6: OutCodePSel = {10'h000, ProcessData[31:26]};
+				4'h7: OutCodePSel = {9'h000,	ProcessData[31:25]};
+				4'h8: OutCodePSel = {8'h00,	ProcessData[31:24]};
+				4'h9: OutCodePSel = {7'h00,	ProcessData[31:23]};
+				4'hA: OutCodePSel = {6'h00,	ProcessData[31:22]};
+				4'hB: OutCodePSel = {5'h00,	ProcessData[31:21]};
+				4'hC: OutCodePSel = {4'h0,	 ProcessData[31:20]};
+				4'hD: OutCodePSel = {3'h0,	 ProcessData[31:19]};
+				4'hE: OutCodePSel = {2'h0,	 ProcessData[31:18]};
+				4'hF: OutCodePSel = {1'h0,	 ProcessData[31:17]};
+			endcase
+		end
+	endfunction
+	assign OutCodeP = OutCodePSel(DhtWidth, ProcessData);
+
+	function [15:0] SubCodeSel;
+		input [3:0]		DhtWidth;
+		begin
+		case (DhtWidth)
+			4'h0: SubCodeSel = 16'hFFFF;
+			4'h1: SubCodeSel = 16'hFFFE;
+			4'h2: SubCodeSel = 16'hFFFC;
+			4'h3: SubCodeSel = 16'hFFF8;
+			4'h4: SubCodeSel = 16'hFFF0;
+			4'h5: SubCodeSel = 16'hFFE0;
+			4'h6: SubCodeSel = 16'hFFC0;
+			4'h7: SubCodeSel = 16'hFF80;
+			4'h8: SubCodeSel = 16'hFF00;
+			4'h9: SubCodeSel = 16'hFE00;
+			4'hA: SubCodeSel = 16'hFC00;
+			4'hB: SubCodeSel = 16'hF800;
+			4'hC: SubCodeSel = 16'hF000;
+			4'hD: SubCodeSel = 16'hE000;
+			4'hE: SubCodeSel = 16'hC000;
+			4'hF: SubCodeSel = 16'h8000;
+		endcase
+	end
+	endfunction
+	assign SubCode = SubCodeSel(DhtWidth);
+
+	always @(posedge clk or negedge rst) begin
+		if(!rst) begin
+			Process			<= ProcIdle;
+			ProcessData		<= 32'h00000000;
+			ProcessCount	<= 6'd0;
+			OutEnable		<= 1'b0;
+//			DataOutEnable	<= 1'b0;
+			DataOutColor	<= 3'b000;
+			PreData[0]		<= 32'h00000000;
+			PreData[1]		<= 32'h00000000;
+			PreData[2]		<= 32'h00000000;
+			UseWidth		<= 5'h00;
+			CodeNumber		<= 4'd0;
+		end else begin
+			case (Process)
+				ProcIdle: begin
+					if(DataInRun == 1'b1) begin
+						Process	<= Phase1;
+					end else begin
+						// Reset DC code
+						PreData[0]	<= 32'h00000000;
+						PreData[1]	<= 32'h00000000;
+						PreData[2]	<= 32'h00000000;
+					end
+					OutEnable		<= 1'b0;
+					ProcessColor	<= 3'b000;
+					ProcessCount	<= 6'd0;
+//					DataOutEnable	<= 1'b0;
+					DataOutColor	<= 3'b000;
+				end
+				// get a table-data and table-number
+				Phase1: begin
+					if(DataInRun == 1'b0) begin
+						Process		<= ProcIdle;
+					end else if(DataInEnable == 1'b1 & DataOutIdle == 1'b1) begin
+						Process		<= Phase2;
+						ProcessData	<= DataIn;
+					end
+					OutEnable	<= 1'b0;
+//					DataOutEnable	<= 1'b0;
+					if(ProcessColor[2] == 1'b0) begin
+						if(ProcessCount == 0) begin
+							HuffmanTable[0]	<= HuffmanTable0r[0];
+							HuffmanNumber[0]	<= HuffmanNumber0r[0];
+							HuffmanTable[1]	<= HuffmanTable0r[1];
+							HuffmanNumber[1]	<= HuffmanNumber0r[1];
+							HuffmanTable[2]	<= HuffmanTable0r[2];
+							HuffmanNumber[2]	<= HuffmanNumber0r[2];
+							HuffmanTable[3]	<= HuffmanTable0r[3];
+							HuffmanNumber[3]	<= HuffmanNumber0r[3];
+							HuffmanTable[4]	<= HuffmanTable0r[4];
+							HuffmanNumber[4]	<= HuffmanNumber0r[4];
+							HuffmanTable[5]	<= HuffmanTable0r[5];
+							HuffmanNumber[5]	<= HuffmanNumber0r[5];
+							HuffmanTable[6]	<= HuffmanTable0r[6];
+							HuffmanNumber[6]	<= HuffmanNumber0r[6];
+							HuffmanTable[7]	<= HuffmanTable0r[7];
+							HuffmanNumber[7]	<= HuffmanNumber0r[7];
+							HuffmanTable[8]	<= HuffmanTable0r[8];
+							HuffmanNumber[8]	<= HuffmanNumber0r[8];
+							HuffmanTable[9]	<= HuffmanTable0r[9];
+							HuffmanNumber[9]	<= HuffmanNumber0r[9];
+							HuffmanTable[10]	<= HuffmanTable0r[10];
+							HuffmanNumber[10]	<= HuffmanNumber0r[10];
+							HuffmanTable[11]	<= HuffmanTable0r[11];
+							HuffmanNumber[11]	<= HuffmanNumber0r[11];
+							HuffmanTable[12]	<= HuffmanTable0r[12];
+							HuffmanNumber[12]	<= HuffmanNumber0r[12];
+							HuffmanTable[13]	<= HuffmanTable0r[13];
+							HuffmanNumber[13]	<= HuffmanNumber0r[13];
+							HuffmanTable[14]	<= HuffmanTable0r[14];
+							HuffmanNumber[14]	<= HuffmanNumber0r[14];
+							HuffmanTable[15]	<= HuffmanTable0r[15];
+							HuffmanNumber[15]	<= HuffmanNumber0r[15];
+						end else begin
+							HuffmanTable[0]	<= HuffmanTable1r[0];
+							HuffmanNumber[0]	<= HuffmanNumber1r[0];
+							HuffmanTable[1]	<= HuffmanTable1r[1];
+							HuffmanNumber[1]	<= HuffmanNumber1r[1];
+							HuffmanTable[2]	<= HuffmanTable1r[2];
+							HuffmanNumber[2]	<= HuffmanNumber1r[2];
+							HuffmanTable[3]	<= HuffmanTable1r[3];
+							HuffmanNumber[3]	<= HuffmanNumber1r[3];
+							HuffmanTable[4]	<= HuffmanTable1r[4];
+							HuffmanNumber[4]	<= HuffmanNumber1r[4];
+							HuffmanTable[5]	<= HuffmanTable1r[5];
+							HuffmanNumber[5]	<= HuffmanNumber1r[5];
+							HuffmanTable[6]	<= HuffmanTable1r[6];
+							HuffmanNumber[6]	<= HuffmanNumber1r[6];
+							HuffmanTable[7]	<= HuffmanTable1r[7];
+							HuffmanNumber[7]	<= HuffmanNumber1r[7];
+							HuffmanTable[8]	<= HuffmanTable1r[8];
+							HuffmanNumber[8]	<= HuffmanNumber1r[8];
+							HuffmanTable[9]	<= HuffmanTable1r[9];
+							HuffmanNumber[9]	<= HuffmanNumber1r[9];
+							HuffmanTable[10]	<= HuffmanTable1r[10];
+							HuffmanNumber[10]	<= HuffmanNumber1r[10];
+							HuffmanTable[11]	<= HuffmanTable1r[11];
+							HuffmanNumber[11]	<= HuffmanNumber1r[11];
+							HuffmanTable[12]	<= HuffmanTable1r[12];
+							HuffmanNumber[12]	<= HuffmanNumber1r[12];
+							HuffmanTable[13]	<= HuffmanTable1r[13];
+							HuffmanNumber[13]	<= HuffmanNumber1r[13];
+							HuffmanTable[14]	<= HuffmanTable1r[14];
+							HuffmanNumber[14]	<= HuffmanNumber1r[14];
+							HuffmanTable[15]	<= HuffmanTable1r[15];
+							HuffmanNumber[15]	<= HuffmanNumber1r[15];
+						end
+					end else begin
+						if(ProcessCount == 0) begin
+							HuffmanTable[0]	<= HuffmanTable2r[0];
+							HuffmanNumber[0]	<= HuffmanNumber2r[0];
+							HuffmanTable[1]	<= HuffmanTable2r[1];
+							HuffmanNumber[1]	<= HuffmanNumber2r[1];
+							HuffmanTable[2]	<= HuffmanTable2r[2];
+							HuffmanNumber[2]	<= HuffmanNumber2r[2];
+							HuffmanTable[3]	<= HuffmanTable2r[3];
+							HuffmanNumber[3]	<= HuffmanNumber2r[3];
+							HuffmanTable[4]	<= HuffmanTable2r[4];
+							HuffmanNumber[4]	<= HuffmanNumber2r[4];
+							HuffmanTable[5]	<= HuffmanTable2r[5];
+							HuffmanNumber[5]	<= HuffmanNumber2r[5];
+							HuffmanTable[6]	<= HuffmanTable2r[6];
+							HuffmanNumber[6]	<= HuffmanNumber2r[6];
+							HuffmanTable[7]	<= HuffmanTable2r[7];
+							HuffmanNumber[7]	<= HuffmanNumber2r[7];
+							HuffmanTable[8]	<= HuffmanTable2r[8];
+							HuffmanNumber[8]	<= HuffmanNumber2r[8];
+							HuffmanTable[9]	<= HuffmanTable2r[9];
+							HuffmanNumber[9]	<= HuffmanNumber2r[9];
+							HuffmanTable[10]	<= HuffmanTable2r[10];
+							HuffmanNumber[10]	<= HuffmanNumber2r[10];
+							HuffmanTable[11]	<= HuffmanTable2r[11];
+							HuffmanNumber[11]	<= HuffmanNumber2r[11];
+							HuffmanTable[12]	<= HuffmanTable2r[12];
+							HuffmanNumber[12]	<= HuffmanNumber2r[12];
+							HuffmanTable[13]	<= HuffmanTable2r[13];
+							HuffmanNumber[13]	<= HuffmanNumber2r[13];
+							HuffmanTable[14]	<= HuffmanTable2r[14];
+							HuffmanNumber[14]	<= HuffmanNumber2r[14];
+							HuffmanTable[15]	<= HuffmanTable2r[15];
+							HuffmanNumber[15]	<= HuffmanNumber2r[15];
+						end else begin
+							HuffmanTable[0]	<= HuffmanTable3r[0];
+							HuffmanNumber[0]	<= HuffmanNumber3r[0];
+							HuffmanTable[1]	<= HuffmanTable3r[1];
+							HuffmanNumber[1]	<= HuffmanNumber3r[1];
+							HuffmanTable[2]	<= HuffmanTable3r[2];
+							HuffmanNumber[2]	<= HuffmanNumber3r[2];
+							HuffmanTable[3]	<= HuffmanTable3r[3];
+							HuffmanNumber[3]	<= HuffmanNumber3r[3];
+							HuffmanTable[4]	<= HuffmanTable3r[4];
+							HuffmanNumber[4]	<= HuffmanNumber3r[4];
+							HuffmanTable[5]	<= HuffmanTable3r[5];
+							HuffmanNumber[5]	<= HuffmanNumber3r[5];
+							HuffmanTable[6]	<= HuffmanTable3r[6];
+							HuffmanNumber[6]	<= HuffmanNumber3r[6];
+							HuffmanTable[7]	<= HuffmanTable3r[7];
+							HuffmanNumber[7]	<= HuffmanNumber3r[7];
+							HuffmanTable[8]	<= HuffmanTable3r[8];
+							HuffmanNumber[8]	<= HuffmanNumber3r[8];
+							HuffmanTable[9]	<= HuffmanTable3r[9];
+							HuffmanNumber[9]	<= HuffmanNumber3r[9];
+							HuffmanTable[10]	<= HuffmanTable3r[10];
+							HuffmanNumber[10]	<= HuffmanNumber3r[10];
+							HuffmanTable[11]	<= HuffmanTable3r[11];
+							HuffmanNumber[11]	<= HuffmanNumber3r[11];
+							HuffmanTable[12]	<= HuffmanTable3r[12];
+							HuffmanNumber[12]	<= HuffmanNumber3r[12];
+							HuffmanTable[13]	<= HuffmanTable3r[13];
+							HuffmanNumber[13]	<= HuffmanNumber3r[13];
+							HuffmanTable[14]	<= HuffmanTable3r[14];
+							HuffmanNumber[14]	<= HuffmanNumber3r[14];
+							HuffmanTable[15]	<= HuffmanTable3r[15];
+							HuffmanNumber[15]	<= HuffmanNumber3r[15];
+						end
+					end
+				end
+				// compare table
+				Phase2: begin
+					Process		<= Phase4;
+					if(ProcessData[31:16] >= HuffmanTable[0])	Place[0]	<= 1'b1;
+					else											Place[0]	<= 1'b0;
+					if(ProcessData[31:16] >= HuffmanTable[1])	Place[1]	<= 1'b1;
+					else											Place[1]	<= 1'b0;
+					if(ProcessData[31:16] >= HuffmanTable[2])	Place[2]	<= 1'b1;
+					else											Place[2]	<= 1'b0;
+					if(ProcessData[31:16] >= HuffmanTable[3])	Place[3]	<= 1'b1;
+					else											Place[3]	<= 1'b0;
+					if(ProcessData[31:16] >= HuffmanTable[4])	Place[4]	<= 1'b1;
+					else											Place[4]	<= 1'b0;
+					if(ProcessData[31:16] >= HuffmanTable[5])	Place[5]	<= 1'b1;
+					else											Place[5]	<= 1'b0;
+					if(ProcessData[31:16] >= HuffmanTable[6])	Place[6]	<= 1'b1;
+					else											Place[6]	<= 1'b0;
+					if(ProcessData[31:16] >= HuffmanTable[7])	Place[7]	<= 1'b1;
+					else											Place[7]	<= 1'b0;
+					if(ProcessData[31:16] >= HuffmanTable[8])	Place[8]	<= 1'b1;
+					else											Place[8]	<= 1'b0;
+					if(ProcessData[31:16] >= HuffmanTable[9])	Place[9]	<= 1'b1;
+					else											Place[9]	<= 1'b0;
+					if(ProcessData[31:16] >= HuffmanTable[10])	Place[10]	<= 1'b1;
+					else											Place[10]	<= 1'b0;
+					if(ProcessData[31:16] >= HuffmanTable[11])	Place[11]	<= 1'b1;
+					else											Place[11]	<= 1'b0;
+					if(ProcessData[31:16] >= HuffmanTable[12])	Place[12]	<= 1'b1;
+					else											Place[12]	<= 1'b0;
+					if(ProcessData[31:16] >= HuffmanTable[13])	Place[13]	<= 1'b1;
+					else											Place[13]	<= 1'b0;
+					if(ProcessData[31:16] >= HuffmanTable[14])	Place[14]	<= 1'b1;
+					else											Place[14]	<= 1'b0;
+					if(ProcessData[31:16] >= HuffmanTable[15])	Place[15]	<= 1'b1;
+					else											Place[15]	<= 1'b0;
+				end
+				// shift code
+				Phase4: begin
+					Process	<= Phase5;
+					case (Place)
+						16'b0000000000000001: begin
+							TableCode		<= {15'h0000,HuffmanTable[0][15]};
+							NumberCode		<= HuffmanNumber[0];
+							CodeNumber		<= 4'h0;
+							DataNumber		<= {15'h0000,ProcessData[31]};
+							ProcessData	<= {ProcessData[30:0],1'b0};
+						end
+						16'b0000000000000011: begin
+							TableCode		<= {14'h0000,HuffmanTable[1][15:14]};
+							NumberCode		<= HuffmanNumber[1];
+							CodeNumber		<= 4'h1;
+							DataNumber		<= {14'h0000,ProcessData[31:30]};
+							ProcessData	<= {ProcessData[29:0],2'b00};
+						end
+						16'b0000000000000111: begin
+							TableCode		<= {13'h0000,HuffmanTable[2][15:13]};
+							NumberCode		<= HuffmanNumber[2];
+							CodeNumber		<= 4'h2;
+							DataNumber		<= {13'h0000,ProcessData[31:29]};
+							ProcessData	<= {ProcessData[28:0],3'b000};
+						end
+						16'b0000000000001111: begin
+							TableCode		<= {12'h000,HuffmanTable[3][15:12]};
+							NumberCode		<= HuffmanNumber[3];
+							CodeNumber		<= 4'h3;
+							DataNumber		<= {12'h000,ProcessData[31:28]};
+							ProcessData	<= {ProcessData[27:0],4'h0};
+						end
+						16'b0000000000011111: begin
+							TableCode		<= {11'h000,HuffmanTable[4][15:11]};
+							NumberCode		<= HuffmanNumber[4];
+							CodeNumber		<= 4'h4;
+							DataNumber		<= {11'h000,ProcessData[31:27]};
+							ProcessData	<= {ProcessData[26:0],5'h00};
+						end
+						16'b0000000000111111: begin
+							TableCode		<= {10'h000,HuffmanTable[5][15:10]};
+							NumberCode		<= HuffmanNumber[5];
+							CodeNumber		<= 4'h5;
+							DataNumber		<= {10'h000,ProcessData[31:26]};
+							ProcessData	<= {ProcessData[25:0],6'h00};
+						end
+						16'b0000000001111111: begin
+							TableCode		<= {9'h000,HuffmanTable[6][15:9]};
+							NumberCode		<= HuffmanNumber[6];
+							CodeNumber		<= 4'h6;
+							DataNumber		<= {9'h000,ProcessData[31:25]};
+							ProcessData	<= {ProcessData[24:0],7'h00};
+						end
+						16'b0000000011111111: begin
+							TableCode		<= {8'h00,HuffmanTable[7][15:8]};
+							NumberCode		<= HuffmanNumber[7];
+							CodeNumber		<= 4'h7;
+							DataNumber		<= {8'h00,ProcessData[31:24]};
+							ProcessData	<= {ProcessData[23:0],8'h00};
+						end
+						16'b0000000111111111: begin
+							TableCode		<= {7'h00,HuffmanTable[8][15:7]};
+							NumberCode		<= HuffmanNumber[8];
+							CodeNumber		<= 4'h8;
+							DataNumber		<= {7'h00,ProcessData[31:23]};
+							ProcessData	<= {ProcessData[22:0],9'h000};
+						end
+						16'b0000001111111111: begin
+							TableCode		<= {6'h00,HuffmanTable[9][15:6]};
+							NumberCode		<= HuffmanNumber[9];
+							CodeNumber		<= 4'h9;
+							DataNumber		<= {6'h00,ProcessData[31:22]};
+							ProcessData	<= {ProcessData[21:0],10'h000};
+						end
+						16'b0000011111111111: begin
+							TableCode		<= {5'h00,HuffmanTable[10][15:5]};
+							NumberCode		<= HuffmanNumber[10];
+							CodeNumber		<= 4'hA;
+							DataNumber		<= {5'h00,ProcessData[31:21]};
+							ProcessData	<= {ProcessData[20:0],11'h000};
+						end
+						16'b0000111111111111: begin
+							TableCode		<= {4'h0,HuffmanTable[11][15:4]};
+							NumberCode		<= HuffmanNumber[11];
+							CodeNumber		<= 4'hB;
+							DataNumber		<= {4'h0,ProcessData[31:20]};
+							ProcessData	<= {ProcessData[19:0],12'h000};
+						end
+						16'b0001111111111111: begin
+							TableCode		<= {3'h0,HuffmanTable[12][15:3]};
+							NumberCode		<= HuffmanNumber[12];
+							CodeNumber		<= 4'hC;
+							DataNumber		<= {3'h0,ProcessData[31:19]};
+							ProcessData	<= {ProcessData[18:0],13'h0000};
+						end
+						16'b0011111111111111: begin
+							TableCode		<= {2'h0,HuffmanTable[13][15:2]};
+							NumberCode		<= HuffmanNumber[13];
+							CodeNumber		<= 4'hD;
+							DataNumber		<= {2'h0,ProcessData[31:18]};
+							ProcessData	<= {ProcessData[17:0],14'h0000};
+						end
+						16'b0111111111111111: begin
+							TableCode		<= {1'h0,HuffmanTable[14][15:1]};
+							NumberCode		<= HuffmanNumber[14];
+							CodeNumber		<= 4'hE;
+							DataNumber		<= {1'h0,ProcessData[31:17]};
+							ProcessData	<= {ProcessData[16:0],15'h0000};
+						end
+						16'b1111111111111111: begin
+							TableCode		<= HuffmanTable[15];
+							NumberCode		<= HuffmanNumber[15];
+							CodeNumber		<= 4'hF;
+							DataNumber		<= ProcessData[31:16] ;
+							ProcessData	<= {ProcessData[15:0],16'h0000};
+						end
+					endcase
+				end
+				Phase5: begin
+					if(DataOutIdle == 1'b1) Process	<= Phase6;
+				end
+				Phase6: begin
+					Process	<= Phase7;
+					OutZero	<= DhtZero;
+					UseWidth	<= CodeNumber + DhtWidth +5'd1;
+					if(ProcessCount == 0) begin
+						OutEnable	<= 1'b1;
+					end else begin
+						if(DhtZero == 4'h0 & DhtWidth == 4'h0) begin
+							ProcessCount	<= 6'd63;
+							OutEnable		<= 1'b0;
+						end else if(DhtZero == 4'hF & DhtWidth == 4'h0) begin
+							ProcessCount	<= ProcessCount + 6'd15;
+							OutEnable		<= 1'b0;
+						end else begin
+							ProcessCount	<= ProcessCount + DhtZero;
+							OutEnable		<= 1'b1;
+						end
+					end
+
+					if(ProcessData[31] == 1'b0 & DhtWidth != 0) begin
+						OutCode	<= (OutCodeP | SubCode) + 16'h0001;
+					end else begin
+						OutCode	<= OutCodeP;
+					end
+				end
+				Phase7: begin
+					Process	<= Phase8;
+					if(ProcessCount == 0) begin
+						if(ProcessColor[2] == 1'b0) begin
+							OutCode	<= OutCode + PreData[0][15:0];
+							PreData[0]	<= OutCode + PreData[0];
+						end else begin
+							if(ProcessColor[0] == 1'b0) begin
+								OutCode	<= OutCode + PreData[1][15:0];
+								PreData[1]	<= OutCode + PreData[1];
+							end else begin
+								OutCode	<= OutCode + PreData[2][15:0];
+								PreData[2]	<= OutCode + PreData[2];
+							end
+						end
+					end
+				end
+				Phase8: begin
+					OutEnable	<= 1'b0;
+					Process		<= Phase1;
+					if(ProcessCount <6'd63) begin
+						ProcessCount	<= ProcessCount +6'd1;
+					end else begin
+						ProcessCount	<= 6'd0;
+//						DataOutEnable	<= 1'b1;
+						DataOutColor	<= ProcessColor;
+						// JPEGコンポーネント数が3ならブロックは6つある
+						// JPEGコンポーネント数が1ならブロックは4つしかない(グレースケール)
+						if(	((JpegComp == 3) && (ProcessColor == 5)) ||
+							((JpegComp == 1) && (ProcessColor == 3))
+						) begin
+//						if(ProcessColor == 5) begin
+							ProcessColor	<= 3'b000;
+						end else begin
+							ProcessColor	<= ProcessColor +3'd1;
+						end
+					end
+				end	
+			endcase
+		end
+	end
+
+	assign DhtColor[1]		= ProcessColor[2];
+	assign DhtColor[0]		= ProcessCount != 6'd0;
+	assign DhtNumber			= DataNumber - TableCode + NumberCode;
+
+	assign DqtColor			= ProcessColor[2];
+	assign DqtNumber			= ProcessCount[5:0];
+
+	assign DecodeUseBit		= Process == Phase7;
+	assign DecodeUseWidth	= UseWidth;
+
+	assign DecodeEnable		= OutEnable == 1'b1 & Process == Phase8;
+	assign DecodeColor		= ProcessColor;
+	assign DecodeCount		= ProcessCount[5:0];
+	assign DecodeZero			= OutZero;
+	assign DecodeCode			= DqtData * OutCode;
+
+	assign DataOutEnable		= (Process == Phase8) & (ProcessCount >= 6'd63);
+
+endmodule

aquaxis_IPCORE/aq_axi_djpeg/aq_axi_djpeg.srcs/sources/aq_djpeg_huffman.v

@@ -0,0 +1,173 @@
+/*
+ * Copyright (C)2006-2015 AQUAXIS TECHNOLOGY.
+ *  Don't remove this header. 
+ * When you use this source, there is a need to inherit this header.
+ *
+ * License
+ *  For no commercial -
+ *   License:     The Open Software License 3.0
+ *   License URI: http://www.opensource.org/licenses/OSL-3.0
+ *
+ *  For commmercial -
+ *   License:     AQUAXIS License 1.0
+ *   License URI: http://www.aquaxis.com/licenses
+ *
+ * For further information please contact.
+ *	URI:    http://www.aquaxis.com/
+ *	E-Mail: info(at)aquaxis.com
+ */
+`timescale 1ps / 1ps
+
+module aq_djpeg_huffman(
+	input			rst,
+	input			clk,
+
+	// Init
+	input			ProcessInit,
+
+	// DQT Table
+	input			DqtInEnable,
+	input			DqtInColor,
+	input [5:0]	 DqtInCount,
+	input [7:0]	 DqtInData,
+
+	// DHT Table
+	input			DhtInEnable,
+	input [1:0]	 DhtInColor,
+	input [7:0]	 DhtInCount,
+	input [7:0]	 DhtInData,
+
+	// Huffman Table
+	input			HuffmanTableEnable,	// Table Data In Enable
+	input [1:0]	 HuffmanTableColor,	// Huffman Table Color Number
+	input [3:0]	 HuffmanTableCount,	// Table Number
+	input [15:0]	HuffmanTableCode,	// Huffman Table Data
+	input [7:0]	 HuffmanTableStart,	// Huffman Table Start Number
+
+	// Huffman Decode
+	input			DataInRun,			// Data In Start
+	input			DataInEnable,			// Data In Enable
+	input [31:0]	DataIn,				// Data In
+	input [2:0]	JpegComp,
+
+	output			DecodeUseBit,
+	output [6:0]	DecodeUseWidth,
+
+	// Data Out
+	output			DataOutEnable,
+	output [2:0]	DataOutColor,
+	input			DataOutRead,
+	input [4:0]	 DataOutAddress,
+	output [15:0]	DataOutA,
+	output [15:0]	DataOutB
+);
+	wire			HmDqtColor;
+	wire [5:0]		HmDqtNumber;
+	wire [7:0]		HmDqtData;
+
+	// DQT Table
+	aq_djpeg_dqt u_jpeg_dqt(
+		.rst			( rst				),
+		.clk			( clk				),
+
+		.DataInEnable	( DqtInEnable		),
+		.DataInColor	( DqtInColor		),
+		.DataInCount	( DqtInCount[5:0]	),
+		.DataIn			( DqtInData		 ),
+
+		.TableColor		( HmDqtColor		),
+		.TableNumber	( HmDqtNumber		),
+		.TableData		( HmDqtData		 )
+	);
+
+	wire [1:0]		HmDhtColor;
+	wire [7:0]		HmDhtNumber;
+	wire [3:0]		HmDhtZero;
+	wire [3:0]		HmDhtWidth;
+
+	aq_djpeg_dht u_jpeg_dht(
+		.rst			( rst			),
+		.clk			( clk			),
+
+		.DataInEnable	( DhtInEnable	),
+		.DataInColor	( DhtInColor	),
+		.DataInCount	( DhtInCount	),
+		.DataIn			( DhtInData	 ),
+
+		.ColorNumber	( HmDhtColor	),
+		.TableNumber	( HmDhtNumber	),
+		.ZeroTable		( HmDhtZero	 ),
+		.WidhtTable		( HmDhtWidth	)
+	);
+
+	wire [5:0]		HmDecCount;
+	wire [15:0]	 HmDecData;
+
+	wire			HmOutEnable;
+	wire [2:0]		HmOutColor;
+
+	aq_djpeg_hm_decode u_jpeg_hm_decode(
+		.rst				( rst					),
+		.clk				( clk					),
+
+		// Huffman Table
+		.HuffmanTableEnable	( HuffmanTableEnable	),
+		.HuffmanTableColor	( HuffmanTableColor	 ),
+		.HuffmanTableCount	( HuffmanTableCount	 ),
+		.HuffmanTableCode	( HuffmanTableCode		),
+		.HuffmanTableStart	( HuffmanTableStart	 ),
+
+		// Huffman Decode
+		.DataInRun			( DataInRun			 ),
+		.DataInEnable		( DataInEnable		),
+		.DataIn			( DataIn				),
+		.JpegComp			( JpegComp				),
+
+		// Huffman Table List
+		.DhtColor			( HmDhtColor			),
+		.DhtNumber			( HmDhtNumber			),
+		.DhtZero			( HmDhtZero			 ),
+		.DhtWidth			( HmDhtWidth			),
+
+		// DQT Table
+		.DqtColor			( HmDqtColor			),
+		.DqtNumber			( HmDqtNumber			),
+		.DqtData			( HmDqtData			 ),
+
+		.DataOutIdle		( HmOutIdle			 ),
+		.DataOutEnable		( HmOutEnable			),
+		.DataOutColor		( HmOutColor			),
+
+		// Output decode data
+		.DecodeUseBit		( DecodeUseBit			),
+		.DecodeUseWidth		( DecodeUseWidth		),
+
+		.DecodeEnable		( HmDecEnable			),
+		.DecodeColor		(						),
+		.DecodeCount		( HmDecCount			),
+		.DecodeZero			(						),
+		.DecodeCode			( HmDecData			 )
+		);
+
+	// Ziguzagu to iDCTx Matrix
+	aq_djpeg_ziguzagu u_jpeg_ziguzagu(
+		.rst				( rst				),
+		.clk				( clk				),
+
+		.DataInit			( ProcessInit		),
+		.HuffmanEndEnable	( HmOutEnable		),
+
+		.DataInEnable		( HmDecEnable		),
+		.DataInAddress		( HmDecCount		),
+		.DataInColor		( HmOutColor		),
+		.DataInIdle			( HmOutIdle		 ),
+		.DataIn				( HmDecData		 ),
+
+		.DataOutEnable		( DataOutEnable	 ),
+		.DataOutRead		( DataOutRead		),
+		.DataOutAddress		( DataOutAddress	),
+		.DataOutColor		( DataOutColor		),
+		.DataOutA			( DataOutA			),
+		.DataOutB			( DataOutB			)
+	);
+endmodule

aquaxis_IPCORE/aq_axi_djpeg/aq_axi_djpeg.srcs/sources/aq_djpeg_idct.v

@@ -0,0 +1,111 @@
+/*
+ * Copyright (C)2006-2015 AQUAXIS TECHNOLOGY.
+ *  Don't remove this header. 
+ * When you use this source, there is a need to inherit this header.
+ *
+ * License
+ *  For no commercial -
+ *   License:     The Open Software License 3.0
+ *   License URI: http://www.opensource.org/licenses/OSL-3.0
+ *
+ *  For commmercial -
+ *   License:     AQUAXIS License 1.0
+ *   License URI: http://www.aquaxis.com/licenses
+ *
+ * For further information please contact.
+ *	URI:    http://www.aquaxis.com/
+ *	E-Mail: info(at)aquaxis.com
+ */
+`timescale 1ps / 1ps
+
+module aq_djpeg_idct(
+    input               rst,
+    input               clk,
+
+    input               ProcessInit,
+
+    input               DataInEnable,
+    output              DataInRead,
+    output [4:0]        DataInAddress,
+    input [15:0]        DataInA,
+    input [15:0]        DataInB,
+
+    output              DataOutEnable,
+    output [2:0]        DataOutPage,
+    output [1:0]        DataOutCount,
+    output [8:0]        Data0Out,
+    output [8:0]        Data1Out
+);
+    wire                DctXEnable;
+    wire [2:0]          DctXPage;
+    wire [1:0]          DctXCount;
+    wire [31:0]         DctXData0r;
+    wire [31:0]         DctXData1r;
+
+    aq_djpeg_idct_calc u_jpeg_idctx(
+        .rst            ( rst           ),
+        .clk            ( clk           ),
+
+        .DataInEnable   ( DataInEnable  ),
+        .DataInRead     ( DataInRead    ),
+        .DataInAddress  ( DataInAddress ),
+        .DataInA        ( DataInA       ),
+        .DataInB        ( DataInB       ),
+
+        .DataOutEnable  ( DctXEnable    ),
+        .DataOutPage    ( DctXPage      ),
+        .DataOutCount   ( DctXCount     ),
+        .Data0Out       ( DctXData0r    ),
+        .Data1Out       ( DctXData1r    )
+    );
+
+    wire            DctBEnable;
+    wire            DctBRead;
+    wire [4:0]      DctBAddress;
+    wire [15:0]     DctBDataA;
+    wire [15:0]     DctBDataB;
+
+    aq_djpeg_idctb u_jpeg_idctb(
+        .rst            ( rst               ),
+        .clk            ( clk               ),
+
+        .DataInit       ( ProcessInit       ),
+
+        .DataInEnable   ( DctXEnable        ),
+        .DataInPage     ( DctXPage          ),
+        .DataInCount    ( DctXCount         ),
+        .DataInIdle     ( DctBIdle          ),
+        .DataInA        ( DctXData0r[26:11] ),
+        .DataInB        ( DctXData1r[26:11] ),
+
+        .DataOutEnable  ( DctBEnable        ),
+        .DataOutRead    ( DctBRead          ),
+        .DataOutAddress ( DctBAddress       ),
+        .DataOutA       ( DctBDataA         ),
+        .DataOutB       ( DctBDataB         )
+
+    );
+
+    wire [31:0] Data0OutW, Data1OutW;
+
+    aq_djpeg_idct_calc u_jpeg_idcty(
+        .rst            ( rst           ),
+        .clk            ( clk           ),
+
+        .DataInEnable   ( DctBEnable    ),
+        .DataInRead     ( DctBRead      ),
+        .DataInAddress  ( DctBAddress   ),
+        .DataInA        ( DctBDataA     ),
+        .DataInB        ( DctBDataB     ),
+
+        .DataOutEnable  ( DataOutEnable ),
+        .DataOutPage    ( DataOutPage   ),
+        .DataOutCount   ( DataOutCount  ),
+        .Data0Out       ( Data0OutW     ),
+        .Data1Out       ( Data1OutW     )
+    );
+
+    assign Data0Out = Data0OutW[23:15];
+    assign Data1Out = Data1OutW[23:15];
+
+endmodule

aquaxis_IPCORE/aq_axi_djpeg/aq_axi_djpeg.srcs/sources/aq_djpeg_idct_calc.v

@@ -0,0 +1,498 @@
+/*
+ * Copyright (C)2006-2015 AQUAXIS TECHNOLOGY.
+ *  Don't remove this header. 
+ * When you use this source, there is a need to inherit this header.
+ *
+ * License
+ *  For no commercial -
+ *   License:     The Open Software License 3.0
+ *   License URI: http://www.opensource.org/licenses/OSL-3.0
+ *
+ *  For commmercial -
+ *   License:     AQUAXIS License 1.0
+ *   License URI: http://www.aquaxis.com/licenses
+ *
+ * For further information please contact.
+ *	URI:    http://www.aquaxis.com/
+ *	E-Mail: info(at)aquaxis.com
+ */
+`timescale 1ps / 1ps
+
+module aq_djpeg_idct_calc(
+    input           clk,
+    input           rst,
+
+    input           DataInEnable,
+    output          DataInRead,
+    output [4:0]    DataInAddress,
+    input [15:0]    DataInA,
+    input [15:0]    DataInB,
+
+    output          DataOutEnable,
+    output [2:0]    DataOutPage,
+    output [1:0]    DataOutCount,
+    output [31:0]   Data0Out,
+    output [31:0]   Data1Out
+);
+    //-------------------------------------------------------------------------
+    // Phase1
+    //-------------------------------------------------------------------------
+    reg           Phase1Enable;
+    reg [2:0]     Phase1Page;
+    reg [2:0]     Phase1Count;
+    reg           Phase1EnableD;
+    reg [2:0]     Phase1PageD;
+    reg [2:0]     Phase1CountD;
+
+    always @(posedge clk or negedge rst) begin
+        if(!rst) begin
+            Phase1Enable  <= 1'b0;
+            Phase1Page    <= 3'd0;
+            Phase1Count   <= 3'd0;
+            Phase1EnableD <= 1'b0;
+            Phase1PageD   <= 3'd0;
+            Phase1CountD  <= 3'd0;
+        end else begin
+            if(Phase1Enable == 1'b0) begin
+                if(DataInEnable == 1'b1) begin
+                    Phase1Enable <= 1'b1;
+                    Phase1Page   <= 3'd0;
+                    Phase1Count  <= 3'd0;
+                end
+            end else begin
+                if(Phase1Count == 3'd6) begin
+                    if(Phase1Page == 3'd7) begin
+                        Phase1Enable <= 1'b0;
+                        Phase1Page   <= 3'd0;
+                    end else begin
+                        Phase1Page   <= Phase1Page + 3'd1;
+                    end
+                    Phase1Count <= 3'd0;
+                end else begin
+                    Phase1Count <= Phase1Count + 3'd1;
+                end
+            end
+            Phase1EnableD <= Phase1Enable;
+            Phase1PageD   <= Phase1Page;
+            Phase1CountD  <= Phase1Count;
+        end
+    end
+
+    assign DataInRead       = Phase1Enable & (Phase1Count < 3'd4);
+    assign DataInAddress    = {Phase1Page, Phase1Count[1:0]};
+
+    wire signed [15:0] Phase1R0w;
+    wire signed [15:0] Phase1R1w;
+    wire signed [15:0] Phase1C0w;
+    wire signed [15:0] Phase1C1w;
+    wire signed [15:0] Phase1C2w;
+    wire signed [15:0] Phase1C3w;
+
+    assign Phase1R0w = DataInA;
+    assign Phase1R1w = DataInB;
+
+    function [15:0] Phase1C0wSel;
+        input [2:0] Phase1Count;
+        begin
+            case(Phase1Count)
+                3'd0: begin
+                    Phase1C0wSel = 16'd2896; // C4_16
+                end
+                3'd1: begin
+                    Phase1C0wSel = 16'd3784; // C2_16
+                end
+                3'd2: begin
+                    Phase1C0wSel = 16'd4017; // C1_16
+                end
+                3'd3: begin
+                    Phase1C0wSel = 16'd2276; // C5_16
+                end
+                default: begin
+                    Phase1C0wSel = 16'd0;
+                end
+            endcase
+        end
+    endfunction
+
+    function [15:0] Phase1C1wSel;
+        input [2:0]     Phase1Count;
+        begin
+            case(Phase1Count)
+                3'd0: begin
+                    Phase1C1wSel = 16'd2896; // C4_16
+                end
+                3'd1: begin
+                    Phase1C1wSel = 16'd1567; // C6_16
+                end
+                3'd2: begin
+                    Phase1C1wSel = 16'd799;  // C7_16
+                end
+                3'd3: begin
+                    Phase1C1wSel = 16'd3406; // C3_16
+                end
+                default: begin
+                    Phase1C1wSel = 16'd0;
+                end
+            endcase
+        end
+    endfunction
+
+    function [15:0] Phase1C2wSel;
+        input [2:0]     Phase1Count;
+        begin
+            case(Phase1Count)
+                3'd0: begin
+                    Phase1C2wSel = 16'd2896; // C4_16
+                end
+                3'd1: begin
+                    Phase1C2wSel = 16'd1567; // C6_16
+                end
+                3'd2: begin
+                    Phase1C2wSel = 16'd799;  // C7_16
+                end
+                3'd3: begin
+                    Phase1C2wSel = 16'd3406; // C3_16
+                end
+                default: begin
+                    Phase1C2wSel = 16'd0;
+                end
+            endcase
+        end
+    endfunction
+
+    function [15:0] Phase1C3wSel;
+        input [2:0]     Phase1Count;
+        begin
+            case(Phase1Count)
+                3'd0: begin
+                    Phase1C3wSel = 16'd2896; // C4_16
+                end
+                3'd1: begin
+                    Phase1C3wSel = 16'd3784; // C2_16
+                end
+                3'd2: begin
+                    Phase1C3wSel = 16'd4017; // C1_16
+                end
+                3'd3: begin
+                    Phase1C3wSel = 16'd2276; // C5_16
+                end
+                default: begin
+                    Phase1C3wSel = 16'd0;
+                end
+            endcase
+        end
+    endfunction
+
+    assign Phase1C0w = Phase1C0wSel(Phase1CountD);
+    assign Phase1C1w = Phase1C1wSel(Phase1CountD);
+    assign Phase1C2w = Phase1C2wSel(Phase1CountD);
+    assign Phase1C3w = Phase1C3wSel(Phase1CountD);
+
+    reg signed [31:0] Phase1R0r;
+    reg signed [31:0] Phase1R1r;
+    reg signed [31:0] Phase1R2r;
+    reg signed [31:0] Phase1R3r;
+
+    always @(posedge clk or negedge rst) begin
+        if(!rst) begin
+            Phase1R0r <= 0;
+            Phase1R1r <= 0;
+            Phase1R2r <= 0;
+            Phase1R3r <= 0;
+        end else begin
+            Phase1R0r <= Phase1R0w * Phase1C0w;
+            Phase1R1r <= Phase1R1w * Phase1C1w;
+            Phase1R2r <= Phase1R0w * Phase1C2w;
+            Phase1R3r <= Phase1R1w * Phase1C3w;
+        end
+    end
+
+/*
+    always @(posedge clk) begin
+        if((Phase1EnableD == 1'b1) && (Phase1CountD < 3'd4)) begin
+            $display("(%d,%d) = %8x, %8x",Phase1PageD ,Phase1CountD,
+                                                   Phase1R0w, Phase1R1w);
+        end
+        //if((Phase1EnableD == 1'b1) && (Phase1CountD < 3'd4)) begin
+        //    $display("(%d,%d) = %8x, %8x, %8x, %8x",Phase1PageD ,Phase1CountD,
+        //                                           Phase1R0r, Phase1R1r, Phase1R2r, Phase1R3r);
+        //end
+    end
+*/
+    //-------------------------------------------------------------------------
+    // Phase2
+    //  R0: s0,s3,s7,s6
+    //  R1: s1,s2,s4,s5
+    //-------------------------------------------------------------------------
+    reg             Phase2Enable;
+    reg [2:0]       Phase2Page;
+    reg [2:0]       Phase2Count;
+    reg             Phase2EnableD;
+    reg [2:0]       Phase2PageD;
+    reg [2:0]       Phase2CountD;
+
+    always @(posedge clk or negedge rst) begin
+        if(!rst) begin
+            Phase2Enable  <= 1'b0;
+            Phase2Page    <= 3'd0;
+            Phase2Count   <= 3'd0;
+            Phase2EnableD <= 1'b0;
+            Phase2PageD   <= 3'd0;
+            Phase2CountD  <= 3'd0;
+        end else begin
+            Phase2Enable  <= Phase1EnableD;
+            Phase2Page    <= Phase1PageD;
+            Phase2Count   <= Phase1CountD;
+            Phase2EnableD <= Phase2Enable;
+            Phase2PageD   <= Phase2Page;
+            Phase2CountD  <= Phase2Count;
+        end
+    end
+
+    wire signed [31:0] Phase2A0w;
+    wire signed [31:0] Phase2A1w;
+
+    assign             Phase2A0w = Phase1R0r + Phase1R1r;
+    assign             Phase2A1w = Phase1R2r - Phase1R3r;
+
+    reg signed [31:0]  Phase2Reg [0:7];
+
+    always @(posedge clk or negedge rst) begin
+        if(!rst) begin
+            Phase2Reg[0] <= 0;
+            Phase2Reg[1] <= 0;
+            Phase2Reg[2] <= 0;
+            Phase2Reg[3] <= 0;
+            Phase2Reg[4] <= 0;
+            Phase2Reg[5] <= 0;
+            Phase2Reg[6] <= 0;
+            Phase2Reg[7] <= 0;
+        end else begin
+            case(Phase2Count)
+              3'd0: begin
+                  Phase2Reg[0] <= Phase2A0w;
+                  Phase2Reg[1] <= Phase2A1w;
+              end
+              3'd1: begin
+                  Phase2Reg[3] <= Phase2A0w;
+                  Phase2Reg[2] <= Phase2A1w;
+              end
+              3'd2: begin
+                  Phase2Reg[7] <= Phase2A0w;
+                  Phase2Reg[4] <= Phase2A1w;
+              end
+              3'd3: begin
+                  Phase2Reg[6] <= Phase2A0w;
+                  Phase2Reg[5] <= Phase2A1w;
+              end
+            endcase
+        end
+    end
+
+    //-------------------------------------------------------------------------
+    // Phase3
+    //  R0: t0,t1,t4,t7
+    //  R1: t3,t2,t5,t6
+    //-------------------------------------------------------------------------
+    reg           Phase3Enable;
+    reg [2:0]     Phase3Page;
+    reg [2:0]     Phase3Count;
+    reg           Phase3EnableD;
+    reg [2:0]     Phase3PageD;
+    reg [2:0]     Phase3CountD;
+
+    always @(posedge clk or negedge rst) begin
+        if(!rst) begin
+            Phase3Enable  <= 1'b0;
+            Phase3Page    <= 3'd0;
+            Phase3Count   <= 3'd0;
+            Phase3EnableD <= 1'b0;
+            Phase3PageD   <= 3'd0;
+            Phase3CountD  <= 3'd0;
+        end else begin
+            Phase3Enable  <= Phase2EnableD;
+            Phase3Page    <= Phase2PageD;
+            Phase3Count   <= Phase2CountD;
+            Phase3EnableD <= Phase3Enable;
+            Phase3PageD   <= Phase3Page;
+            Phase3CountD  <= Phase3Count;
+        end
+    end
+
+    wire signed [31:0] Phase3R0w;
+    wire signed [31:0] Phase3R1w;
+
+    assign             Phase3R0w = (Phase3Count == 3'd0)?Phase2Reg[0]:
+                                   (Phase3Count == 3'd1)?Phase2Reg[1]:
+                                   (Phase3Count == 3'd2)?Phase2Reg[4]:
+                                   (Phase3Count == 3'd3)?Phase2Reg[7]:
+                                   32'd0;
+    assign             Phase3R1w = (Phase3Count == 3'd0)?Phase2Reg[3]:
+                                   (Phase3Count == 3'd1)?Phase2Reg[2]:
+                                   (Phase3Count == 3'd2)?Phase2Reg[5]:
+                                   (Phase3Count == 3'd3)?Phase2Reg[6]:
+                                   32'd0;
+
+
+
+    wire signed [31:0] Phase3A0w;
+    wire signed [31:0] Phase3A1w;
+    assign             Phase3A0w = Phase3R0w + Phase3R1w;
+    assign             Phase3A1w = Phase3R0w - Phase3R1w;
+
+    reg signed [31:0]  Phase3Reg [0:7];
+
+    always @(posedge clk or negedge rst) begin
+        if(!rst) begin
+            Phase3Reg[0] <= 0;
+            Phase3Reg[1] <= 0;
+            Phase3Reg[2] <= 0;
+            Phase3Reg[3] <= 0;
+            Phase3Reg[4] <= 0;
+            Phase3Reg[5] <= 0;
+            Phase3Reg[6] <= 0;
+            Phase3Reg[7] <= 0;
+        end else begin
+            case(Phase3Count)
+              3'd0: begin
+                  Phase3Reg[0] <= Phase3A0w;
+                  Phase3Reg[3] <= Phase3A1w;
+              end
+              3'd1: begin
+                  Phase3Reg[1] <= Phase3A0w;
+                  Phase3Reg[2] <= Phase3A1w;
+              end
+              3'd2: begin
+                  Phase3Reg[4] <= Phase3A0w;
+                  Phase3Reg[5] <= Phase3A1w;
+              end
+              3'd3: begin
+                  Phase3Reg[7] <= Phase3A0w;
+                  Phase3Reg[6] <= Phase3A1w;
+              end
+            endcase
+        end
+    end
+
+    //-------------------------------------------------------------------------
+    // Phase4
+    //  R0: s6
+    //  R1: s5
+    //-------------------------------------------------------------------------
+    reg           Phase4Enable;
+    reg [2:0]     Phase4Page;
+    reg [2:0]     Phase4Count;
+    reg           Phase4EnableD;
+    reg [2:0]     Phase4PageD;
+    reg [2:0]     Phase4CountD;
+
+    always @(posedge clk or negedge rst) begin
+        if(!rst) begin
+            Phase4Enable  <= 1'b0;
+            Phase4Page    <= 3'd0;
+            Phase4Count   <= 3'd0;
+            Phase4EnableD <= 1'b0;
+            Phase4PageD   <= 3'd0;
+            Phase4CountD  <= 3'd0;
+        end else begin
+            Phase4Enable  <= Phase3EnableD;
+            Phase4Page    <= Phase3PageD;
+            Phase4Count   <= Phase3CountD;
+            Phase4EnableD <= Phase4Enable;
+            Phase4PageD   <= Phase4Page;
+            Phase4CountD  <= Phase4Count;
+        end
+    end
+
+    reg signed [42:0] Phase4R0r;
+    reg signed [42:0] Phase4R1r;
+
+    wire signed [8:0] C_181;
+    assign            C_181 = 9'h0B5;
+
+    wire signed [32:0] Phase4R0w;
+    wire signed [32:0] Phase4R1w;
+
+    assign Phase4R0w = Phase3Reg[6] + Phase3Reg[5];
+    assign Phase4R1w = Phase3Reg[6] - Phase3Reg[5];
+
+    always @(posedge clk or negedge rst) begin
+        if(!rst) begin
+            Phase4R0r <= 0;
+            Phase4R1r <= 0;
+        end else begin
+            case(Phase4Count)
+              3'd2: begin
+                  //Phase4R0r <= (Phase3Reg[6] + Phase3Reg[5]) * C_181;
+                  //Phase4R1r <= (Phase3Reg[6] - Phase3Reg[5]) * C_181;
+                  Phase4R0r <= Phase4R0w * C_181;
+                  Phase4R1r <= Phase4R1w * C_181;
+              end
+            endcase
+        end
+    end
+
+    //-------------------------------------------------------------------------
+    // Phase5
+    //  R0: B0,B1,B2,B3
+    //  R1: B7,B6,B5,B4
+    //-------------------------------------------------------------------------
+    reg           Phase5Enable;
+    reg [2:0]     Phase5Page;
+    reg [2:0]     Phase5Count;
+    reg           Phase5EnableD;
+    reg [2:0]     Phase5PageD;
+    reg [2:0]     Phase5CountD;
+
+    always @(posedge clk or negedge rst) begin
+        if(!rst) begin
+            Phase5Enable  <= 1'b0;
+            Phase5Page    <= 3'd0;
+            Phase5Count   <= 3'd0;
+            Phase5EnableD <= 1'b0;
+            Phase5PageD   <= 3'd0;
+            Phase5CountD  <= 3'd0;
+        end else begin
+            Phase5Enable  <= Phase4EnableD;
+            Phase5Page    <= Phase4PageD;
+            Phase5Count   <= Phase4CountD;
+            Phase5EnableD <= Phase5Enable;
+            Phase5PageD   <= Phase5Page;
+            Phase5CountD  <= Phase5Count;
+        end
+    end
+
+    wire signed [31:0] Phase5R0w;
+    wire signed [31:0] Phase5R1w;
+    assign             Phase5R0w = (Phase5Count == 3'd0)?Phase3Reg[0]:
+                                   (Phase5Count == 3'd1)?Phase3Reg[1]:
+                                   (Phase5Count == 3'd2)?Phase3Reg[2]:
+                                   (Phase5Count == 3'd3)?Phase3Reg[3]:
+                                   32'd0;
+    assign             Phase5R1w = (Phase5Count == 3'd0)?Phase3Reg[7]:
+                                   (Phase5Count == 3'd1)?Phase4R0r >> 8:
+                                   (Phase5Count == 3'd2)?Phase4R1r >> 8:
+                                   (Phase5Count == 3'd3)?Phase3Reg[4]:
+                                   32'd0;
+
+    reg signed [31:0]  Phase5R0r;
+    reg signed [31:0]  Phase5R1r;
+
+    always @(posedge clk or negedge rst) begin
+        if(!rst) begin
+            Phase5R0r <= 0;
+            Phase5R1r <= 0;
+        end else begin
+            Phase5R0r <= Phase5R0w + Phase5R1w;
+            Phase5R1r <= Phase5R0w - Phase5R1w;
+        end
+    end
+
+    assign DataOutEnable = Phase5EnableD == 1'b1 & Phase5CountD[2] == 1'b0;
+    assign DataOutPage   = Phase5PageD;
+    assign DataOutCount  = Phase5CountD[1:0];
+
+    assign Data0Out = Phase5R0r;
+    assign Data1Out = Phase5R1r;
+
+endmodule

aquaxis_IPCORE/aq_axi_djpeg/aq_axi_djpeg.srcs/sources/aq_djpeg_idctb.v

@@ -0,0 +1,177 @@
+/*
+ * Copyright (C)2006-2015 AQUAXIS TECHNOLOGY.
+ *  Don't remove this header. 
+ * When you use this source, there is a need to inherit this header.
+ *
+ * License
+ *  For no commercial -
+ *   License:     The Open Software License 3.0
+ *   License URI: http://www.opensource.org/licenses/OSL-3.0
+ *
+ *  For commmercial -
+ *   License:     AQUAXIS License 1.0
+ *   License URI: http://www.aquaxis.com/licenses
+ *
+ * For further information please contact.
+ *	URI:    http://www.aquaxis.com/
+ *	E-Mail: info(at)aquaxis.com
+ */
+`timescale 1ps / 1ps
+
+module aq_djpeg_idctb(
+    input           clk,
+    input           rst,
+
+    input           DataInit,
+
+    input           DataInEnable,
+    input [2:0]     DataInPage,
+    input [1:0]     DataInCount,
+    output          DataInIdle,
+    input [15:0]    DataInA,
+    input [15:0]    DataInB,
+
+    output          DataOutEnable,
+    input           DataOutRead,
+    input [4:0]     DataOutAddress,
+    output [15:0]   DataOutA,
+    output [15:0]   DataOutB
+);
+    wire [4:0]      DataInAddress;
+    reg [1:0]       WriteBank, ReadBank;
+
+    assign DataInAddress = {DataInPage, DataInCount};
+
+    // Bank
+    always @(posedge clk or negedge rst) begin
+        if(!rst) begin
+            WriteBank <= 2'd0;
+            ReadBank <= 2'd0;
+        end else begin
+            if(DataInit) begin
+                WriteBank <= 2'd0;
+            end else if(DataInEnable && (DataInAddress == 5'h1F)) begin
+                WriteBank <= WriteBank + 2'd1;
+            end
+            if(DataInit) begin
+                ReadBank <= 2'd0;
+            end else if(DataOutRead && (DataOutAddress == 5'h1F)) begin
+                ReadBank <= ReadBank + 2'd1;
+            end
+        end
+    end
+
+    wire [5:0]  WriteQueryA, WriteQueryB;
+
+    // Make a Write Address
+    function [5:0] F_WriteQueryA;
+        input [4:0] Count;
+        case(Count)
+            5'd0:  F_WriteQueryA = {1'd0, 5'd0};    // 0
+            5'd1:  F_WriteQueryA = {1'd0, 5'd4};    // 1
+            5'd2:  F_WriteQueryA = {1'd0, 5'd8};    // 2
+            5'd3:  F_WriteQueryA = {1'd0, 5'd12};   // 3
+            5'd4:  F_WriteQueryA = {1'd0, 5'd2};    // 8
+            5'd5:  F_WriteQueryA = {1'd0, 5'd6};    // 9
+            5'd6:  F_WriteQueryA = {1'd0, 5'd10};   // 10
+            5'd7:  F_WriteQueryA = {1'd0, 5'd14};   // 11
+            5'd8:  F_WriteQueryA = {1'd0, 5'd1};    // 16
+            5'd9:  F_WriteQueryA = {1'd0, 5'd5};    // 17
+            5'd10: F_WriteQueryA = {1'd0, 5'd9};    // 18
+            5'd11: F_WriteQueryA = {1'd0, 5'd13};   // 19
+            5'd12: F_WriteQueryA = {1'd1, 5'd3};    // 24
+            5'd13: F_WriteQueryA = {1'd1, 5'd7};    // 25
+            5'd14: F_WriteQueryA = {1'd1, 5'd11};   // 26
+            5'd15: F_WriteQueryA = {1'd1, 5'd15};   // 27
+            5'd16: F_WriteQueryA = {1'd1, 5'd0};    // 32
+            5'd17: F_WriteQueryA = {1'd1, 5'd4};    // 33
+            5'd18: F_WriteQueryA = {1'd1, 5'd8};    // 34
+            5'd19: F_WriteQueryA = {1'd1, 5'd12};   // 35
+            5'd20: F_WriteQueryA = {1'd0, 5'd3};    // 40
+            5'd21: F_WriteQueryA = {1'd0, 5'd7};    // 41
+            5'd22: F_WriteQueryA = {1'd0, 5'd11};   // 42
+            5'd23: F_WriteQueryA = {1'd0, 5'd15};   // 43
+            5'd24: F_WriteQueryA = {1'd1, 5'd1};    // 48
+            5'd25: F_WriteQueryA = {1'd1, 5'd5};    // 49
+            5'd26: F_WriteQueryA = {1'd1, 5'd9};    // 50
+            5'd27: F_WriteQueryA = {1'd1, 5'd13};   // 51
+            5'd28: F_WriteQueryA = {1'd1, 5'd2};    // 56
+            5'd29: F_WriteQueryA = {1'd1, 5'd6};    // 57
+            5'd30: F_WriteQueryA = {1'd1, 5'd10};   // 58
+            5'd31: F_WriteQueryA = {1'd1, 5'd14};   // 59
+        endcase
+    endfunction
+
+    function [5:0] F_WriteQueryB;
+        input [4:0] Count;
+        case(Count)
+            5'd0:  F_WriteQueryB = {1'd1, 5'd28};   // 7
+            5'd1:  F_WriteQueryB = {1'd1, 5'd24};   // 6
+            5'd2:  F_WriteQueryB = {1'd1, 5'd20};   // 5
+            5'd3:  F_WriteQueryB = {1'd1, 5'd16};   // 4
+            5'd4:  F_WriteQueryB = {1'd1, 5'd30};   // 15
+            5'd5:  F_WriteQueryB = {1'd1, 5'd26};   // 14
+            5'd6:  F_WriteQueryB = {1'd1, 5'd22};   // 13
+            5'd7:  F_WriteQueryB = {1'd1, 5'd18};   // 12
+            5'd8:  F_WriteQueryB = {1'd1, 5'd29};   // 23
+            5'd9:  F_WriteQueryB = {1'd1, 5'd25};   // 22
+            5'd10: F_WriteQueryB = {1'd1, 5'd21};   // 21
+            5'd11: F_WriteQueryB = {1'd1, 5'd17};   // 20
+            5'd12: F_WriteQueryB = {1'd0, 5'd31};   // 31
+            5'd13: F_WriteQueryB = {1'd0, 5'd27};   // 30
+            5'd14: F_WriteQueryB = {1'd0, 5'd23};   // 29
+            5'd15: F_WriteQueryB = {1'd0, 5'd19};   // 28
+            5'd16: F_WriteQueryB = {1'd0, 5'd28};   // 39
+            5'd17: F_WriteQueryB = {1'd0, 5'd24};   // 38
+            5'd18: F_WriteQueryB = {1'd0, 5'd20};   // 37
+            5'd19: F_WriteQueryB = {1'd0, 5'd16};   // 36
+            5'd20: F_WriteQueryB = {1'd1, 5'd31};   // 47
+            5'd21: F_WriteQueryB = {1'd1, 5'd27};   // 46
+            5'd22: F_WriteQueryB = {1'd1, 5'd23};   // 45
+            5'd23: F_WriteQueryB = {1'd1, 5'd19};   // 44
+            5'd24: F_WriteQueryB = {1'd0, 5'd29};   // 55
+            5'd25: F_WriteQueryB = {1'd0, 5'd25};   // 54
+            5'd26: F_WriteQueryB = {1'd0, 5'd21};   // 53
+            5'd27: F_WriteQueryB = {1'd0, 5'd17};   // 52
+            5'd28: F_WriteQueryB = {1'd0, 5'd30};   // 63
+            5'd29: F_WriteQueryB = {1'd0, 5'd26};   // 62
+            5'd30: F_WriteQueryB = {1'd0, 5'd22};   // 61
+            5'd31: F_WriteQueryB = {1'd0, 5'd18};   // 60
+        endcase
+    endfunction
+
+    assign WriteQueryA = F_WriteQueryA(DataInAddress);
+    assign WriteQueryB = F_WriteQueryB(DataInAddress);
+
+    // RAM(16bit x 32word x 2Bank)
+    reg [15:0]  MemoryA  [0:127];
+    reg [15:0]  MemoryB  [0:127];
+
+    wire [6:0]  WriteAddressA, WriteAddressB;
+    wire [15:0] WriteDataA, WriteDataB;
+
+    assign WriteAddressA = {WriteBank, (WriteQueryA[5])?WriteQueryB[4:0]:WriteQueryA[4:0]};
+    assign WriteAddressB = {WriteBank, (WriteQueryB[5])?WriteQueryB[4:0]:WriteQueryA[4:0]};
+
+    assign WriteDataA = (WriteQueryA[5])?DataInB:DataInA;
+    assign WriteDataB = (WriteQueryB[5])?DataInB:DataInA;
+
+    // Port A(Write Only)
+    always @(posedge clk) begin
+        if(DataInEnable) MemoryA[WriteAddressA] <= WriteDataA;
+        if(DataInEnable) MemoryB[WriteAddressB] <= WriteDataB;
+    end
+
+    reg [15:0]  RegMemoryA, RegMemoryB;
+
+    // Port B(Read/Wirte)
+    always @(posedge clk) begin
+        RegMemoryA <= MemoryA[{ReadBank, DataOutAddress}];
+        RegMemoryB <= MemoryB[{ReadBank, DataOutAddress}];
+    end
+
+    assign DataOutEnable    = (WriteBank != ReadBank);
+    assign DataOutA         = (DataOutAddress[4])?RegMemoryB:RegMemoryA;
+    assign DataOutB         = (DataOutAddress[4])?RegMemoryA:RegMemoryB;
+
+endmodule

aquaxis_IPCORE/aq_axi_djpeg/aq_axi_djpeg.srcs/sources/aq_djpeg_regdata.v

@@ -0,0 +1,271 @@
+/*
+ * Copyright (C)2006-2015 AQUAXIS TECHNOLOGY.
+ *  Don't remove this header. 
+ * When you use this source, there is a need to inherit this header.
+ *
+ * License
+ *  For no commercial -
+ *   License:     The Open Software License 3.0
+ *   License URI: http://www.opensource.org/licenses/OSL-3.0
+ *
+ *  For commmercial -
+ *   License:     AQUAXIS License 1.0
+ *   License URI: http://www.aquaxis.com/licenses
+ *
+ * For further information please contact.
+ *	URI:    http://www.aquaxis.com/
+ *	E-Mail: info(at)aquaxis.com
+ */
+`timescale 1ps / 1ps
+
+module aq_djpeg_regdata(
+	input			rst,
+	input			clk,
+
+	// Read Data
+	input [31:0]	DataIn,
+	input			DataInEnable,		// Data Enable
+	output			DataInRead,		// Data Read
+
+	// DataOut
+	output [31:0]	DataOut,			// Data Out
+	output			DataOutEnable,	// Data Out Enable
+
+	input			ImageEnable,
+	input			ProcessIdle,
+
+	// UseData
+	input			UseBit,		// Used data bit
+	input [6:0]	UseWidth,		// Used data bit width
+	input			UseByte,		// Used data byte
+	input			UseWord		// Used data word
+);
+	wire			RegValid;
+	reg [95:0]		RegData;
+	reg [6:0]		RegWidth;
+	reg				CheckMode;
+	reg				DataEnd;
+
+	wire			PreImageEnable;
+	reg				ImageReady;
+
+//	assign RegValid	= (ImageEnable)?(RegWidth > 7'd64):(RegWidth > 7'd32);
+	assign RegValid	= (ImageReady)?(RegWidth > 7'd64):(RegWidth > 7'd32);
+	assign DataInRead	= ((RegValid == 1'b0) & (DataInEnable == 1'b1) & (DataEnd == 1'b0));
+	
+	assign PreImageEnable	= ((ImageEnable == 1'b1) && (ImageReady == 1'b0))?1'b1:1'b0;
+
+	always @(posedge clk or negedge rst) begin
+		if(!rst) begin
+			RegData	<= 96'd0;
+			RegWidth	<= 7'd0;
+			CheckMode	<= 1'b0;
+			ImageReady	<= 1'b0;
+		end else begin
+			if(DataEnd == 1'b1 & ProcessIdle == 1'b1) begin
+				RegData	<= 96'd0;
+				RegWidth	<= 7'd0;
+				CheckMode	<= 1'b0;
+				ImageReady	<= 1'b0;
+			end else if(RegValid == 1'b0 & (DataInEnable == 1'b1 | DataEnd == 1'b1)) begin
+				if(ImageReady == 1'b1) begin
+					if(RegData[39: 8] == 32'hFF00FF00 & CheckMode != 1'b1) begin
+						RegWidth		<= RegWidth + 7'd16;
+						RegData[95:64]	<= {8'h00,RegData[71:48]};
+						RegData[63:32]	<= {RegData[47:40],16'hFFFF,RegData[7:0]};
+						CheckMode		<= 1'b0;
+					end else if(RegData[39:24] == 16'hFF00 & RegData[15: 0] == 16'hFF00 & CheckMode != 1'b1) begin
+						RegWidth		<= RegWidth + 7'd16;
+						RegData[95:64]	<= {8'h00,RegData[71:48]};
+						RegData[63:32]	<= {RegData[47:40],8'hFF,RegData[23:16],8'hFF};
+						CheckMode		<= 1'b1;
+					end else if(RegData[31: 0] == 32'hFF00FF00) begin
+						RegWidth		<= RegWidth + 7'd16;
+						RegData[95:64]	<= {16'h0000,RegData[63:48]};
+						RegData[63:32]	<= {RegData[47:32],16'hFFFF};
+						CheckMode		<= 1'b1;
+					end else if(RegData[39:24] == 16'hFF00 & CheckMode != 1'b1) begin
+						RegWidth		<= RegWidth + 7'd24;
+						RegData[95:64]	<= {RegData[71:40]};
+						RegData[63:32]	<= {8'hFF,RegData[23:0]};
+						CheckMode		<= 1'b0;
+					end else if(RegData[31:16] == 16'hFF00) begin
+						RegWidth		<= RegWidth + 7'd24;
+						RegData[95:64]	<= {RegData[71:40]};
+						RegData[63:32]	<= {RegData[39:32],8'hFF,RegData[15:0]};
+						CheckMode		<= 1'b0;
+					end else if(RegData[23: 8] == 16'hFF00) begin
+						RegWidth		<= RegWidth + 7'd24;
+						RegData[95:64]	<= {RegData[71:40]};
+						RegData[63:32]	<= {RegData[39:32],RegData[31:24],8'hFF,RegData[7:0]};
+						CheckMode		<= 1'b0;
+					end else if(RegData[15: 0] == 16'hFF00) begin
+						RegWidth		<= RegWidth + 7'd24;
+						RegData[95:64]	<= {RegData[71:40]};
+						RegData[63:32]	<= {RegData[39:32],RegData[31:16],8'hFF};
+						CheckMode		<= 1'b1;
+					end else begin
+						RegWidth		<= RegWidth + 7'd32;
+						RegData[95:64]	<= RegData[63:32];
+						RegData[63:32]	<= RegData[31:0];
+						CheckMode		<= 1'b0;
+					end
+				end else begin
+					RegWidth		<= RegWidth + 7'd32;
+					RegData[95:64]	<= RegData[63:32];
+					RegData[63:32]	<= RegData[31:0];
+					CheckMode		<= 1'b0;
+				end
+				RegData[31: 0] <= {DataIn[7:0],DataIn[15:8],DataIn[23:16],DataIn[31:24]};
+			end else if(PreImageEnable == 1'b1) begin
+				if((RegData[63:32] == 32'hFF00FF00) && (RegWidth == 7'd64)) begin
+                    RegWidth        <= 7'd48;
+					RegData[63:32]	<= {32'h0000FFFF};
+					CheckMode		<= 1'b1;
+				end else if ((RegData[63:48] == 16'hFF00) && (RegWidth == 7'd64)) begin
+                    RegWidth        <= 7'd56;
+					RegData[63:32]	<= {16'h00FF, RegData[47:32]};
+					CheckMode		<= 1'b0;
+				end else if ((RegData[55:40] == 16'hFF00) && (RegWidth == 7'd64)) begin
+                    RegWidth        <= 7'd56;
+					RegData[63:32]	<= {8'h00,RegData[63:56],8'hFF,RegData[39:32]};
+					CheckMode		<= 1'b0;
+				end else if ((RegData[47:32] == 16'hFF00) && (RegWidth == 7'd64)) begin
+                    RegWidth        <= 7'd56;
+					RegData[63:32]	<= {8'h00,RegData[55:48],8'hFF};
+					CheckMode		<= 1'b1;
+				end else if ((RegData[55:40] == 16'hFF00) && (RegWidth == 7'd56)) begin
+                    RegWidth        <= 7'd48;
+					RegData[63:32]	<= {24'h0000FF, RegData[39:32]};
+					CheckMode		<= 1'b0;
+				end else if ((RegData[47:32] == 16'hFF00) && (RegWidth == 7'd56)) begin
+                    RegWidth        <= 7'd48;
+					RegData[63:32]	<= {16'h0000, RegData[55:48],8'hFF};
+					CheckMode		<= 1'b1;
+				end else if ((RegData[47:32] == 16'hFF00) && (RegWidth == 7'd48)) begin
+                    RegWidth        <= 7'd40;
+					RegData[63:32]	<= {24'h000000FF};
+					CheckMode		<= 1'b1;
+				end
+				ImageReady		<= 1'b1;
+			end else if(UseBit == 1'b1) begin
+				RegWidth <= RegWidth - UseWidth;
+			end else if(UseByte == 1'b1) begin
+				RegWidth <= RegWidth - 7'd8;
+			end else if(UseWord == 1'b1) begin
+				RegWidth <= RegWidth - 7'd16;
+			end
+		end
+	end
+
+	// PickUp with End of Jpeg Data
+	always @(posedge clk or negedge rst) begin
+		if(!rst) begin
+			DataEnd <= 1'b0;
+		end else begin
+			if(ProcessIdle) begin
+				DataEnd <= 1'b0;
+			end else if(ImageEnable == 1'b1 & ((RegData[39:24] == 16'hFFD9 & CheckMode != 1'b1) | RegData[31:16] == 16'hFFD9 | RegData[23: 8] == 16'hFFD9 | RegData[15: 0] == 16'hFFD9)) begin
+				DataEnd <= 1'b1;
+			end
+		end
+	end
+
+	function [31:0]	SliceData;
+		input [95:0]	RegData;
+		input [7:0]	RegWidth;
+
+		case(RegWidth)
+			//8'd33: SliceData = RegData[32: 1];
+			//8'd34: SliceData = RegData[33: 2];
+			//8'd35: SliceData = RegData[34: 3];
+			//8'd36: SliceData = RegData[35: 4];
+			//8'd37: SliceData = RegData[36: 5];
+			//8'd38: SliceData = RegData[37: 6];
+			//8'd39: SliceData = RegData[38: 7];
+			8'd40: SliceData = RegData[39: 8];
+			//8'd41: SliceData = RegData[40: 9];
+			//8'd42: SliceData = RegData[41:10];
+			//8'd43: SliceData = RegData[42:11];
+			//8'd44: SliceData = RegData[43:12];
+			//8'd45: SliceData = RegData[44:13];
+			//8'd46: SliceData = RegData[45:14];
+			//8'd47: SliceData = RegData[46:15];
+			8'd48: SliceData = RegData[47:16];
+			//8'd49: SliceData = RegData[48:17];
+			//8'd50: SliceData = RegData[49:18];
+			//8'd51: SliceData = RegData[50:19];
+			//8'd52: SliceData = RegData[51:20];
+			//8'd53: SliceData = RegData[52:21];
+			//8'd54: SliceData = RegData[53:22];
+			//8'd55: SliceData = RegData[54:23];
+			8'd56: SliceData = RegData[55:24];
+			//8'd57: SliceData = RegData[56:25];
+			//8'd58: SliceData = RegData[57:26];
+			//8'd59: SliceData = RegData[58:27];
+			//8'd60: SliceData = RegData[59:28];
+			//8'd61: SliceData = RegData[60:29];
+			//8'd62: SliceData = RegData[61:30];
+			//8'd63: SliceData = RegData[62:31];
+			8'd64: SliceData = RegData[63:32];
+			8'd65: SliceData = RegData[64:33];
+			8'd66: SliceData = RegData[65:34];
+			8'd67: SliceData = RegData[66:35];
+			8'd68: SliceData = RegData[67:36];
+			8'd69: SliceData = RegData[68:37];
+			8'd70: SliceData = RegData[69:38];
+			8'd71: SliceData = RegData[70:39];
+			8'd72: SliceData = RegData[71:40];
+			8'd73: SliceData = RegData[72:41];
+			8'd74: SliceData = RegData[73:42];
+			8'd75: SliceData = RegData[74:43];
+			8'd76: SliceData = RegData[75:44];
+			8'd77: SliceData = RegData[76:45];
+			8'd78: SliceData = RegData[77:46];
+			8'd79: SliceData = RegData[78:47];
+			8'd80: SliceData = RegData[79:48];
+			8'd81: SliceData = RegData[80:49];
+			8'd82: SliceData = RegData[81:50];
+			8'd83: SliceData = RegData[82:51];
+			8'd84: SliceData = RegData[83:52];
+			8'd85: SliceData = RegData[84:53];
+			8'd86: SliceData = RegData[85:54];
+			8'd87: SliceData = RegData[86:55];
+			8'd88: SliceData = RegData[87:56];
+			8'd89: SliceData = RegData[88:57];
+			8'd90: SliceData = RegData[89:58];
+			8'd91: SliceData = RegData[90:59];
+			8'd92: SliceData = RegData[91:60];
+			8'd93: SliceData = RegData[92:61];
+			8'd94: SliceData = RegData[93:62];
+			8'd95: SliceData = RegData[94:63];
+			8'd96: SliceData = RegData[95:64];
+			default: SliceData = 32'h00000000;
+		endcase
+	endfunction
+
+	reg				OutEnable;
+	reg				PreEnable;
+	reg [31:0]		DataOut;
+
+	always @(posedge clk or negedge rst) begin
+		if(!rst) begin
+			OutEnable	<= 1'b0;
+			PreEnable	<= 1'b0;
+			DataOut	<= 32'h00000000;
+		end else begin
+			if(DataEnd == 1'b1 & ProcessIdle == 1'b1) begin
+				OutEnable	<= 1'b0;
+				PreEnable	<= 1'b0;
+				DataOut	<= 32'h00000000;
+			end else begin
+				OutEnable	<= RegValid;
+				PreEnable	<= (UseBit == 1'b1 | UseByte == 1'b1 | UseWord == 1'b1);
+				DataOut	<= SliceData(RegData,RegWidth);
+			end
+		end
+	end
+
+	assign DataOutEnable = (PreEnable == 1'b0)?OutEnable:1'b0;
+
+endmodule

aquaxis_IPCORE/aq_axi_djpeg/aq_axi_djpeg.srcs/sources/aq_djpeg_ycbcr.v

@@ -0,0 +1,159 @@
+/*
+ * Copyright (C)2006-2015 AQUAXIS TECHNOLOGY.
+ *  Don't remove this header. 
+ * When you use this source, there is a need to inherit this header.
+ *
+ * License
+ *  For no commercial -
+ *   License:     The Open Software License 3.0
+ *   License URI: http://www.opensource.org/licenses/OSL-3.0
+ *
+ *  For commmercial -
+ *   License:     AQUAXIS License 1.0
+ *   License URI: http://www.aquaxis.com/licenses
+ *
+ * For further information please contact.
+ *	URI:    http://www.aquaxis.com/
+ *	E-Mail: info(at)aquaxis.com
+ */
+`timescale 1ps / 1ps
+
+module aq_djpeg_ycbcr(
+	input			rst,
+	input			clk,
+
+	input			ProcessInit,
+	input [2:0]	JpegComp,
+
+	input			DataInEnable,
+	input [2:0]	DataInPage,
+	input [1:0]	DataInCount,
+	output			DataInIdle,
+	input [8:0]	Data0In,
+	input [8:0]	Data1In,
+	input [11:0]	DataInBlockWidth,
+	output			DataInFull,
+
+	output			OutEnable,
+	output [15:0]	OutPixelX,
+	output [15:0]	OutPixelY,
+	output [7:0]	OutR,
+	output [7:0]	OutG,
+	output [7:0]	OutB
+);
+	reg [2:0]		DataInColor;
+	reg [11:0]		DataInBlockX;
+	reg [11:0]		DataInBlockY;
+
+	wire			ConvertEnable;
+	wire			ConvertRead;
+	wire			ConvertBank;
+	wire [7:0]		ConvertAddress;
+	wire [8:0]		DataY;
+	wire [8:0]		DataCb;
+	wire [8:0]		DataCr;
+	wire [11:0]		ConvertBlockX;
+	wire [11:0]		ConvertBlockY;
+
+	always @(posedge clk or negedge rst) begin
+		if(!rst) begin
+			DataInColor	<= 3'd0;
+		end else begin
+			if(ProcessInit) begin
+				DataInColor <= 3'd0;
+			end else if((DataInEnable == 1'b1) && (DataInPage == 3'd7) && (DataInCount == 2'd3)) begin
+				// コンポーネント数が3ならYCbCrで411
+				// コンポーネント数が1ならグレースケールで400
+				if(	((JpegComp == 3) && (DataInColor == 3'd5)) || 
+					((JpegComp == 1) && (DataInColor == 3'd3))) begin
+//				if(DataInColor == 3'd5) begin 
+					DataInColor <= 3'd0;
+				end else begin
+					DataInColor <= DataInColor + 3'd1;
+				end
+			end
+		end
+	end
+
+	//------------------------------------------------------------------------
+	// YCbCr Memory
+	//------------------------------------------------------------------------
+	aq_djpeg_ycbcr_mem u_jpeg_ycbcr_mem(
+		.rst				( rst				),
+		.clk				( clk				),
+
+		.DataInit			( ProcessInit		),
+		.JpegComp			( JpegComp			),
+
+		.DataInEnable		( DataInEnable	),
+		.DataInColor		( DataInColor		),
+		.DataInPage		( DataInPage		),
+		.DataInCount		( DataInCount		),
+		.Data0In			( Data0In			),
+		.Data1In			( Data1In			),
+		.DataInFull		( DataInFull		),
+
+		.DataOutEnable	( ConvertEnable	),
+		.DataOutAddress	( ConvertAddress	),
+		.DataOutRead		( ConvertRead		),
+		.DataOutY			( DataY			),
+		.DataOutCb			( DataCb			),
+		.DataOutCr			( DataCr			)
+	);
+	//------------------------------------------------------------------------
+	// YCbCr to RGB
+	//------------------------------------------------------------------------
+	always @(posedge clk or negedge rst) begin
+		if(!rst) begin
+			DataInBlockX <= 12'd0;
+			DataInBlockY <= 12'd0;
+		end else begin
+			if(ProcessInit) begin
+				DataInBlockX <= 12'd0;
+				DataInBlockY <= 12'd0;
+			end else if((ConvertRead == 1'b1) && (ConvertAddress == 8'd255)) begin
+//				if(JpegComp == 3)  begin
+					if(DataInBlockWidth == DataInBlockX +1) begin
+						DataInBlockX <= 12'd0;
+						DataInBlockY <= DataInBlockY + 12'd1;
+					end else begin
+						DataInBlockX <= DataInBlockX + 12'd1;
+					end
+//				end else begin
+//					if(DataInBlockWidth == DataInBlockX +3) begin
+//						DataInBlockX <= 12'd0;
+//						DataInBlockY <= DataInBlockY + 12'd1;
+//					end else begin
+//						DataInBlockX <= DataInBlockX + 12'd1;
+//					end
+//				end
+			end
+		end
+	end
+	
+	wire [8:0]	tDataCb,tDataCr;
+	assign tDataCb = (JpegComp == 1)?9'd0:DataCb;
+	assign tDataCr = (JpegComp == 1)?9'd0:DataCr;
+
+	aq_djpeg_ycbcr2rgb u_jpeg_yccr2rgb(
+		.rst		( rst				),
+		.clk		( clk				),
+
+		.InEnable	( ConvertEnable	),
+		.InRead	( ConvertRead		),
+		.InBlockX	( DataInBlockX	),
+		.InBlockY	( DataInBlockY	),
+		.InComp	( JpegComp			),
+		.InAddress	( ConvertAddress	),
+		.InY		( DataY			),
+		.InCb		( tDataCb			),
+		.InCr		( tDataCr			),
+
+		.OutEnable	( OutEnable		),
+		.OutPixelX	( OutPixelX		),
+		.OutPixelY	( OutPixelY		),
+		.OutR		( OutR				),
+		.OutG		( OutG				),
+		.OutB		( OutB				)
+	);
+endmodule

aquaxis_IPCORE/aq_axi_djpeg/aq_axi_djpeg.srcs/sources/aq_djpeg_ycbcr2rgb.v

@@ -0,0 +1,225 @@
+/*
+ * Copyright (C)2006-2015 AQUAXIS TECHNOLOGY.
+ *  Don't remove this header. 
+ * When you use this source, there is a need to inherit this header.
+ *
+ * License
+ *  For no commercial -
+ *   License:     The Open Software License 3.0
+ *   License URI: http://www.opensource.org/licenses/OSL-3.0
+ *
+ *  For commmercial -
+ *   License:     AQUAXIS License 1.0
+ *   License URI: http://www.aquaxis.com/licenses
+ *
+ * For further information please contact.
+ *	URI:    http://www.aquaxis.com/
+ *	E-Mail: info(at)aquaxis.com
+ */
+`timescale 1ps / 1ps
+
+//----------------------------------------------------------------------------
+// JPEG YCbCr -> RGB Conveter
+//----------------------------------------------------------------------------
+module aq_djpeg_ycbcr2rgb(
+	input			clk,
+	input			rst,
+
+	input			InEnable,
+	output			InRead,
+	input [11:0]	InBlockX,
+	input [11:0]	InBlockY,
+	input [2:0]	InComp,
+	output [7:0]	InAddress,
+	input [8:0]	InY,
+	input [8:0]	InCb,
+	input [8:0]	InCr,
+
+	output			OutEnable,
+	output [15:0]	OutPixelX,
+	output [15:0]	OutPixelY,
+	output [7:0]	OutR,
+	output [7:0]	OutG,
+	output [7:0]	OutB
+);
+	reg				RunActive;
+	reg [7:0]		RunCount;
+	reg [11:0]	 	RunBlockX;
+	reg [11:0]	 	RunBlockY;
+	reg [2:0]		RunComp;
+
+	always @(posedge clk or negedge rst) begin
+		if(!rst) begin
+			RunActive	<= 1'b0;
+			RunCount	<= 8'h00;
+			RunBlockX	<= 12'h000;
+			RunBlockY	<= 12'h000;
+			RunComp	<= 1'b0;
+		end else begin
+			if(RunActive == 1'b0) begin
+				if(InEnable == 1'b1) begin
+					RunActive	<= 1'b1;
+					RunBlockX	<= InBlockX;
+					RunBlockY	<= InBlockY;
+					RunComp	<= InComp;
+				end
+				RunCount	<= 8'h00;
+			end else begin
+				if(RunCount == 8'd255) begin
+					RunActive	<= 1'b0;
+					RunCount	<= 8'd0;
+				end else begin
+					RunCount	<= RunCount +8'd1;
+				end
+			end
+		end
+	end
+
+	assign InRead		= RunActive;
+	assign InAddress	= RunCount;
+
+	reg			PreEnable;
+	reg [15:0]	PreCountX;
+	reg [15:0]	PreCountY;
+	reg			Phase0Enable;
+	reg [15:0]	Phase0CountX;
+	reg [15:0]	Phase0CountY;
+	reg			Phase1Enable;
+	reg [15:0]	Phase1CountX;
+	reg [15:0]	Phase1CountY;
+	reg			Phase2Enable;
+	reg [15:0]	Phase2CountX;
+	reg [15:0]	Phase2CountY;
+	reg			Phase3Enable;
+	reg [15:0]	Phase3CountX;
+	reg [15:0]	Phase3CountY;
+
+	reg signed [31:0] rgb00r;
+	reg signed [31:0] r00r;
+	reg signed [31:0] g00r;
+	reg signed [31:0] g01r;
+	reg signed [31:0] b00r;
+	reg signed [31:0] r10r;
+	reg signed [31:0] g10r;
+	reg signed [31:0] g11r;
+	reg signed [31:0] b10r;
+	reg signed [31:0] r20r;
+	reg signed [31:0] g20r;
+	reg signed [31:0] b20r;
+
+	wire signed [8:0] DataY;
+	wire signed [8:0] DataCb;
+	wire signed [8:0] DataCr;
+
+	reg signed [8:0]	Phase0Y;
+	reg signed [8:0]	Phase0Cb;
+	reg signed [8:0]	Phase0Cr;
+
+	wire signed [19:0] C_RR = 20'h59BA5; // R_Cr: 1.402	* 0x4000
+	wire signed [19:0] C_GB = 20'h16066; // G_Cb: 0.34414 * 0x4000
+	wire signed [19:0] C_GR = 20'h2DB47; // G_Cr: 0.71414 * 0x4000
+	wire signed [19:0] C_BB = 20'h71687; // B_Cb: 1.772	* 0x4000
+
+	assign			 DataY	= InY;
+	assign			 DataCb = InCb;
+	assign			 DataCr = InCr;
+
+	reg signed [8:0]	Phase1Y,Phase1Cb,Phase1Cr;
+	reg signed [8:0]	Phase2Y,Phase2Cb,Phase2Cr;
+
+	always @(posedge clk or negedge rst) begin
+		if(!rst) begin
+			rgb00r <= 0;
+			r00r	<= 0;
+			g00r	<= 0;
+			g01r	<= 0;
+			b00r	<= 0;
+
+			r10r	<= 0;
+			g10r	<= 0;
+			g11r	<= 0;
+			b10r	<= 0;
+
+			r20r	<= 0;
+			g20r	<= 0;
+			b20r	<= 0;
+
+			Phase0Enable <= 1'b0;
+			Phase0CountX <= 16'h0000;
+			Phase0CountY <= 16'h0000;
+			Phase1Enable <= 1'b0;
+			Phase1CountX <= 16'h0000;
+			Phase1CountY <= 16'h0000;
+			Phase2Enable <= 1'b0;
+			Phase2CountX <= 16'h0000;
+			Phase2CountY <= 16'h0000;
+			Phase3Enable <= 1'b0;
+			Phase3CountX <= 16'h0000;
+			Phase3CountY <= 16'h0000;
+		end else begin
+			// Pre
+			PreEnable <= RunActive;
+			if(RunComp == 3) begin
+				// コンポーネント数が3のとき、16x16が1ブロック
+				PreCountX <= {RunBlockX,RunCount[3:0]};
+				PreCountY <= {RunBlockY,RunCount[7:4]};
+			end else begin
+				// コンポーネント数が1のとき、32x8が1ブロック
+				PreCountX <= {RunBlockX[10:0],RunCount[7],RunCount[3:0]};
+				PreCountY <= {1'b0,RunBlockY[11:0],RunCount[6:4]};
+			end
+
+			// Phase0
+			Phase0Enable	<= PreEnable;
+			Phase0CountX	<= PreCountX;
+			Phase0CountY	<= PreCountY;
+			Phase0Y		<= DataY;
+			Phase0Cb		<= DataCb;
+			Phase0Cr		<= DataCr;
+
+			// Phase1
+			Phase1Enable	<= Phase0Enable;
+			Phase1CountX	<= Phase0CountX;
+			Phase1CountY	<= Phase0CountY;
+
+			rgb00r <= 32'h02000000 + {Phase0Y[8],Phase0Y[8],Phase0Y[8],Phase0Y[8],Phase0Y[8],Phase0Y[8:0],18'h0000};
+			r00r	<= Phase0Cr * C_RR;
+			g00r	<= Phase0Cb * C_GB;
+			g01r	<= Phase0Cr * C_GR;
+			b00r	<= Phase0Cb * C_BB;
+
+			Phase1Y	<= Phase0Y;
+			Phase1Cb	<= Phase0Cb;
+			Phase1Cr	<= Phase0Cr;
+
+			// Phase2
+			Phase2Enable	<= Phase1Enable;
+			Phase2CountX	<= Phase1CountX;
+			Phase2CountY	<= Phase1CountY;
+
+			r10r	<= rgb00r + r00r;
+			g10r	<= rgb00r - g00r;
+			g11r	<= g01r;
+			b10r	<= rgb00r + b00r;
+
+			Phase2Y	<= Phase1Y;
+			Phase2Cb	<= Phase1Cb;
+			Phase2Cr	<= Phase1Cr;
+
+			// Phase3
+			Phase3Enable	<= Phase2Enable;
+			Phase3CountX	<= Phase2CountX;
+			Phase3CountY	<= Phase2CountY;
+			r20r	<= r10r;
+			g20r	<= g10r - g11r;
+			b20r	<= b10r;
+		end
+	end
+
+	assign OutEnable	= Phase3Enable;
+	assign OutPixelX	= Phase3CountX;
+	assign OutPixelY	= Phase3CountY;
+	assign OutR		= (r20r[31])?8'h00:(r20r[26])?8'hFF:r20r[25:18];
+	assign OutG		= (g20r[31])?8'h00:(g20r[26])?8'hFF:g20r[25:18];
+	assign OutB		= (b20r[31])?8'h00:(b20r[26])?8'hFF:b20r[25:18];
+endmodule

aquaxis_IPCORE/aq_axi_djpeg/aq_axi_djpeg.srcs/sources/aq_djpeg_ycbcr_mem.v

@@ -0,0 +1,201 @@
+/*
+ * Copyright (C)2006-2015 AQUAXIS TECHNOLOGY.
+ *  Don't remove this header. 
+ * When you use this source, there is a need to inherit this header.
+ *
+ * License
+ *  For no commercial -
+ *   License:     The Open Software License 3.0
+ *   License URI: http://www.opensource.org/licenses/OSL-3.0
+ *
+ *  For commmercial -
+ *   License:     AQUAXIS License 1.0
+ *   License URI: http://www.aquaxis.com/licenses
+ *
+ * For further information please contact.
+ *	URI:    http://www.aquaxis.com/
+ *	E-Mail: info(at)aquaxis.com
+ */
+`timescale 1ps / 1ps
+
+module aq_djpeg_ycbcr_mem(
+	input			rst,
+	input			clk,
+
+	input			DataInit,
+	input [2:0]	JpegComp,
+
+	input			DataInEnable,
+	input [2:0]	DataInColor,
+	input [2:0]	DataInPage,
+	input [1:0]	DataInCount,
+	input [8:0]	Data0In,
+	input [8:0]	Data1In,
+	output			DataInFull,
+
+	output			DataOutEnable,
+	input [7:0]	DataOutAddress,
+	input			DataOutRead,
+	output [8:0]	DataOutY,
+	output [8:0]	DataOutCb,
+	output [8:0]	DataOutCr
+);
+	reg [8:0]		MemYA	[0:511];
+	reg [8:0]		MemYB	[0:511];
+	reg [8:0]		MemCbA [0:127];
+	reg [8:0]		MemCbB [0:127];
+	reg [8:0]		MemCrA [0:127];
+	reg [8:0]		MemCrB [0:127];
+
+	reg [1:0]		WriteBank, ReadBank;
+
+	wire [5:0]		DataInAddress;
+
+	assign DataInAddress = {DataInPage, DataInCount};
+
+	wire WriteNext, ReadNext;
+	
+	assign WriteNext = (DataInEnable && (DataInAddress == 5'd63) && 
+							(((JpegComp == 3'd3) && (DataInColor == 3'd5)) ||
+							((JpegComp == 3'd1) && (DataInColor == 3'd3))))?1'b1:1'b0;
+	assign ReadNext = (DataOutRead && (DataOutAddress == 8'd255))?1'b1:1'b0;
+
+	// Bank
+	always @(posedge clk or negedge rst) begin
+		if(!rst) begin
+			WriteBank	<= 2'd0;
+			ReadBank	<= 2'd0;
+		end else begin
+			if(DataInit) begin
+				WriteBank	<= 2'd0;
+			end else if(WriteNext == 1'b1) begin
+//				(DataInColor == 3'd5)) begin
+				WriteBank	<= WriteBank + 2'd1;
+			end
+			if(DataInit) begin
+				ReadBank	<= 2'd0;
+			end else if(ReadNext == 1'b1) begin
+				ReadBank	<= ReadBank + 2'd1;
+			end
+		end
+	end
+	
+	reg [1:0]	state;
+	localparam S_IDLE = 2'd0;
+	localparam S_FULL = 2'd1;
+	
+	always @(posedge clk or negedge rst) begin
+		if(!rst) begin
+			state <= S_IDLE;
+		end else begin
+			if(DataInit) begin
+				state <= S_IDLE;
+			end else begin
+				case(state)
+					S_IDLE: begin
+						if((WriteNext == 1'b1) && (ReadBank == (WriteBank +2'b1)) && (ReadNext == 1'b0)) begin
+							state <= S_FULL;
+						end
+					end
+					S_FULL: begin
+						if((ReadNext == 1'b1) && (ReadBank == WriteBank)) begin
+							state <= S_IDLE;
+						end
+					end
+					default: begin
+						state <= S_IDLE;
+					end
+				endcase
+			end
+		end
+	end
+	assign DataInFull = (state == S_FULL)?1'b1:1'b0;
+
+	wire [6:0]		WriteAddressA;
+	wire [6:0]		WriteAddressB;
+
+	function [6:0] F_WriteAddressA;
+		input [2:0]	DataInColor;
+		input [2:0]	DataInPage;
+		input [1:0]	DataInCount;
+		begin
+			F_WriteAddressA[6]	= DataInColor[1];
+			if(DataInColor[2] == 1'b0) begin
+				F_WriteAddressA[5:4]	= DataInCount[1:0];
+				F_WriteAddressA[3]	= DataInColor[0] & ~DataInColor[2];
+			end else begin
+				F_WriteAddressA[5]	= 1'b0;
+				F_WriteAddressA[4:3]	= DataInCount[1:0];
+			end
+			F_WriteAddressA[2:0]		= DataInPage[2:0];
+		end
+	endfunction
+
+	function [6:0] F_WriteAddressB;
+		input [2:0]	DataInColor;
+		input [2:0]	DataInPage;
+		input [1:0]	DataInCount;
+		begin
+			F_WriteAddressB[6]	= DataInColor[1];
+			if(DataInColor[2] == 1'b0) begin
+				F_WriteAddressB[5:4]	= ~DataInCount[1:0];
+				F_WriteAddressB[3]	= DataInColor[0] & ~DataInColor[2];
+			end else begin
+				F_WriteAddressB[5]	= 1'b0;
+				F_WriteAddressB[4:3]	= ~DataInCount[1:0];
+			end
+			F_WriteAddressB[2:0]		= DataInPage[2:0];
+		end
+	endfunction
+
+	assign WriteAddressA = F_WriteAddressA(DataInColor, DataInPage, DataInCount);
+	assign WriteAddressB = F_WriteAddressB(DataInColor, DataInPage, DataInCount);
+
+	always @(posedge clk) begin
+		if(DataInColor[2] == 1'b0 & DataInEnable == 1'b1) begin
+			MemYA[{WriteBank, WriteAddressA}] <= Data0In;
+			MemYB[{WriteBank, WriteAddressB}] <= Data1In;
+		end
+	end
+
+	always @(posedge clk) begin
+		if(DataInColor == 3'b100 & DataInEnable == 1'b1) begin
+			MemCbA[{WriteBank, WriteAddressA[4:0]}] <= Data0In;
+			MemCbB[{WriteBank, WriteAddressB[4:0]}] <= Data1In;
+		end
+	end
+
+	always @(posedge clk) begin
+		if(DataInColor == 3'b101 & DataInEnable == 1'b1) begin
+			MemCrA[{WriteBank, WriteAddressA[4:0]}] <= Data0In;
+			MemCrB[{WriteBank, WriteAddressB[4:0]}] <= Data1In;
+		end
+	end
+
+	reg [8:0] ReadYA;
+	reg [8:0] ReadYB;
+	reg [8:0] ReadCbA;
+	reg [8:0] ReadCbB;
+	reg [8:0] ReadCrA;
+	reg [8:0] ReadCrB;
+
+	reg [7:0] RegAdrs;
+
+	always @(posedge clk) begin
+		RegAdrs <= DataOutAddress;
+
+		ReadYA	<= MemYA[{ReadBank, DataOutAddress[7],DataOutAddress[5:0]}];
+		ReadYB	<= MemYB[{ReadBank, DataOutAddress[7],DataOutAddress[5:0]}];
+
+		ReadCbA <= MemCbA[{ReadBank, DataOutAddress[6:5],DataOutAddress[3:1]}];
+		ReadCrA <= MemCrA[{ReadBank, DataOutAddress[6:5],DataOutAddress[3:1]}];
+
+		ReadCbB <= MemCbB[{ReadBank, DataOutAddress[6:5],DataOutAddress[3:1]}];
+		ReadCrB <= MemCrB[{ReadBank, DataOutAddress[6:5],DataOutAddress[3:1]}];
+	end
+
+	assign DataOutEnable	= (WriteBank != ReadBank);
+	assign DataOutY		= (RegAdrs[6] ==1'b0)?ReadYA:ReadYB;
+	assign DataOutCb		= (RegAdrs[7] ==1'b0)?ReadCbA:ReadCbB;
+	assign DataOutCr		= (RegAdrs[7] ==1'b0)?ReadCrA:ReadCrB;
+endmodule

aquaxis_IPCORE/aq_axi_djpeg/aq_axi_djpeg.srcs/sources/aq_djpeg_ziguzagu.v

@@ -0,0 +1,319 @@
+/*
+ * Copyright (C)2006-2015 AQUAXIS TECHNOLOGY.
+ *  Don't remove this header. 
+ * When you use this source, there is a need to inherit this header.
+ *
+ * License
+ *  For no commercial -
+ *   License:     The Open Software License 3.0
+ *   License URI: http://www.opensource.org/licenses/OSL-3.0
+ *
+ *  For commmercial -
+ *   License:     AQUAXIS License 1.0
+ *   License URI: http://www.aquaxis.com/licenses
+ *
+ * For further information please contact.
+ *	URI:    http://www.aquaxis.com/
+ *	E-Mail: info(at)aquaxis.com
+ */
+`timescale 1ps / 1ps
+
+module aq_djpeg_ziguzagu(
+    input           clk,
+    input           rst,
+
+    input           DataInit,
+    input           HuffmanEndEnable,
+
+    input           DataInEnable,
+    input [5:0]     DataInAddress,
+    input [2:0]     DataInColor,
+    output          DataInIdle,
+    input [15:0]    DataIn,
+
+    output          DataOutEnable,
+    input           DataOutRead,
+    input [4:0]     DataOutAddress,
+    output [2:0]    DataOutColor,
+    output [15:0]   DataOutA,
+    output [15:0]   DataOutB
+);
+    // State Machine Parameter
+    parameter S_IDLE    = 2'd0;
+    parameter S_VALID   = 2'd1;
+    parameter S_FULL    = 2'd2;
+    parameter S_INIT    = 2'd3;
+
+    reg [1:0]   State;
+    reg [1:0]   BankCount;
+
+    reg [2:0]   BankColor [0:3];
+    reg [1:0]   WriteBank;
+    reg [1:0]   ReadBank;
+
+    wire [5:0]  WriteQuery;
+
+    // State Machine
+    always @(posedge clk or negedge rst) begin
+        if(!rst) begin
+            State <= S_IDLE;
+            BankCount <= 2'd0;
+        end else begin
+            case(State)
+                S_IDLE: begin
+                    if(DataInit) begin
+                        State       <= S_INIT;
+                    end else if(HuffmanEndEnable) begin
+                        State       <= S_VALID;
+                        BankCount   <= 2'd0;
+                    end
+                end
+                S_VALID: begin
+                    if(HuffmanEndEnable && !(DataOutRead && (DataOutAddress == 5'd31))) begin
+                        if(BankCount == 2'd2) begin
+                            State       <= S_FULL;
+                            BankCount   <= 2'd3;
+                        end else begin
+                            BankCount <= BankCount + 2'd1;
+                        end
+                    end else if(!HuffmanEndEnable && (DataOutRead && (DataOutAddress == 5'd31))) begin
+                        if(BankCount == 2'd0) begin
+                            State       <= S_IDLE;
+                            BankCount   <= 2'd0;
+                        end else begin
+                            BankCount   <= BankCount - 2'd1;
+                        end
+                    end
+                end
+                S_FULL: begin
+                    if(DataOutRead && (DataOutAddress == 5'd31)) begin
+                        State       <= S_VALID;
+                        BankCount   <= 2'd2;
+                    end
+                end
+                S_INIT: begin
+                    State <= S_IDLE;
+                end
+            endcase
+        end
+    end
+
+    // Color
+    always @(posedge clk or negedge rst) begin
+        if(!rst) begin
+            BankColor[0]    <= 3'd0;
+            BankColor[1]    <= 3'd0;
+            BankColor[2]    <= 3'd0;
+            BankColor[3]    <= 3'd0;
+        end else begin
+            if(HuffmanEndEnable) BankColor[WriteBank] <= DataInColor;
+        end
+    end
+
+    // Bank
+    always @(posedge clk or negedge rst) begin
+        if(!rst) begin
+            WriteBank   <= 2'd0;
+            ReadBank    <= 2'd0;
+        end else begin
+            // Write Bank
+            if(State == S_INIT) begin
+                WriteBank <= 2'd0;
+            end else if(HuffmanEndEnable) begin
+                WriteBank <= WriteBank + 2'd1;
+            end
+            // Read Bank
+            if(State == S_INIT) begin
+                ReadBank <= 2'd0;
+            end else if(DataOutRead && (DataOutAddress == 5'd31)) begin
+                ReadBank <= ReadBank + 2'd1;
+            end
+        end
+    end
+
+    // Make a Write Address
+    function [5:0] F_WriteQuery;
+        input [5:0] Count;
+        case(Count)
+            6'd0:  F_WriteQuery = {1'b0, 5'd0 };
+            6'd1:  F_WriteQuery = {1'b0, 5'd2 };
+            6'd2:  F_WriteQuery = {1'b0, 5'd4 };
+            6'd3:  F_WriteQuery = {1'b0, 5'd8 };
+            6'd4:  F_WriteQuery = {1'b0, 5'd6 };
+            6'd5:  F_WriteQuery = {1'b0, 5'd1 };
+            6'd6:  F_WriteQuery = {1'b1, 5'd3 };
+            6'd7:  F_WriteQuery = {1'b0, 5'd5 };
+            6'd8:  F_WriteQuery = {1'b0, 5'd10};
+            6'd9:  F_WriteQuery = {1'b0, 5'd12};
+            6'd10: F_WriteQuery = {1'b0, 5'd16};
+            6'd11: F_WriteQuery = {1'b0, 5'd14};
+            6'd12: F_WriteQuery = {1'b0, 5'd9 };
+            6'd13: F_WriteQuery = {1'b1, 5'd7 };
+            6'd14: F_WriteQuery = {1'b1, 5'd0 };
+            6'd15: F_WriteQuery = {1'b0, 5'd3 };
+            6'd16: F_WriteQuery = {1'b1, 5'd4 };
+            6'd17: F_WriteQuery = {1'b1, 5'd11};
+            6'd18: F_WriteQuery = {1'b0, 5'd13};
+            6'd19: F_WriteQuery = {1'b0, 5'd18};
+            6'd20: F_WriteQuery = {1'b0, 5'd20};
+            6'd21: F_WriteQuery = {1'b0, 5'd24};
+            6'd22: F_WriteQuery = {1'b0, 5'd22};
+            6'd23: F_WriteQuery = {1'b0, 5'd17};
+            6'd24: F_WriteQuery = {1'b1, 5'd15};
+            6'd25: F_WriteQuery = {1'b1, 5'd8 };
+            6'd26: F_WriteQuery = {1'b0, 5'd7 };
+            6'd27: F_WriteQuery = {1'b1, 5'd1 };
+            6'd28: F_WriteQuery = {1'b1, 5'd2 };
+            6'd29: F_WriteQuery = {1'b1, 5'd5 };
+            6'd30: F_WriteQuery = {1'b0, 5'd11};
+            6'd31: F_WriteQuery = {1'b1, 5'd12};
+            6'd32: F_WriteQuery = {1'b1, 5'd19};
+            6'd33: F_WriteQuery = {1'b0, 5'd21};
+            6'd34: F_WriteQuery = {1'b0, 5'd26};
+            6'd35: F_WriteQuery = {1'b0, 5'd28};
+            6'd36: F_WriteQuery = {1'b0, 5'd30};
+            6'd37: F_WriteQuery = {1'b0, 5'd25};
+            6'd38: F_WriteQuery = {1'b1, 5'd23};
+            6'd39: F_WriteQuery = {1'b1, 5'd16};
+            6'd40: F_WriteQuery = {1'b0, 5'd15};
+            6'd41: F_WriteQuery = {1'b1, 5'd9 };
+            6'd42: F_WriteQuery = {1'b1, 5'd6 };
+            6'd43: F_WriteQuery = {1'b1, 5'd10};
+            6'd44: F_WriteQuery = {1'b1, 5'd13};
+            6'd45: F_WriteQuery = {1'b0, 5'd19};
+            6'd46: F_WriteQuery = {1'b1, 5'd20};
+            6'd47: F_WriteQuery = {1'b1, 5'd27};
+            6'd48: F_WriteQuery = {1'b0, 5'd29};
+            6'd49: F_WriteQuery = {1'b1, 5'd31};
+            6'd50: F_WriteQuery = {1'b1, 5'd24};
+            6'd51: F_WriteQuery = {1'b0, 5'd23};
+            6'd52: F_WriteQuery = {1'b1, 5'd17};
+            6'd53: F_WriteQuery = {1'b1, 5'd14};
+            6'd54: F_WriteQuery = {1'b1, 5'd18};
+            6'd55: F_WriteQuery = {1'b1, 5'd21};
+            6'd56: F_WriteQuery = {1'b0, 5'd27};
+            6'd57: F_WriteQuery = {1'b1, 5'd28};
+            6'd58: F_WriteQuery = {1'b0, 5'd31};
+            6'd59: F_WriteQuery = {1'b1, 5'd25};
+            6'd60: F_WriteQuery = {1'b1, 5'd22};
+            6'd61: F_WriteQuery = {1'b1, 5'd26};
+            6'd62: F_WriteQuery = {1'b1, 5'd29};
+            6'd63: F_WriteQuery = {1'b1, 5'd30};
+        endcase
+    endfunction
+
+    assign WriteQuery = F_WriteQuery(DataInAddress);
+
+    // RAM(16bit x 32word x 2Bank)
+    reg [15:0]  MemoryA  [0:127];
+    reg [15:0]  MemoryB  [0:127];
+
+    wire [6:0]  WriteAddress;
+    wire        WriteEnableA, WriteEnableB;
+
+    assign WriteEnableA = DataInEnable & ~WriteQuery[5];
+    assign WriteEnableB = DataInEnable &  WriteQuery[5];
+    assign WriteAddress = {WriteBank, WriteQuery[4:0]};
+
+    // Port A(Write Only)
+    always @(posedge clk) begin
+        if(WriteEnableA) MemoryA[WriteAddress] <= DataIn;
+        if(WriteEnableB) MemoryB[WriteAddress] <= DataIn;
+    end
+
+    reg [15:0]  RegMemoryA, RegMemoryB;
+
+    // Port B(Read/Wirte)
+    always @(posedge clk) begin
+        RegMemoryA <= MemoryA[{ReadBank, DataOutAddress}];
+        RegMemoryB <= MemoryB[{ReadBank, DataOutAddress}];
+    end
+
+    // Data Enable Register
+    reg [127:0] DataEnableA, DataEnableB;
+
+    always @(posedge clk or negedge rst) begin
+        if(!rst) begin
+            DataEnableA <= 128'd0;
+            DataEnableB <= 128'd0;
+        end else begin
+            if(State == S_INIT) begin
+                DataEnableA <= 128'd0;
+                DataEnableB <= 128'd0;
+            end else begin
+                if(DataInEnable && (WriteBank == 2'd0)) begin
+                    if(WriteEnableA) begin
+                        if(WriteAddress[4:0] == 5'd0) begin
+                            DataEnableA[{2'd0, WriteAddress[4:0]}] <= 1'b1;
+                            DataEnableA[31:1] <= 31'd0;
+                            DataEnableB[31:0] <= 32'd0;
+                        end else begin
+                            DataEnableA[{2'd0, WriteAddress[4:0]}] <= 1'b1;
+                        end
+                    end else begin
+                        DataEnableB[{2'd0, WriteAddress[4:0]}] <= 1'b1;
+                    end
+                end
+                if(DataInEnable && (WriteBank == 2'd1)) begin
+                    if(WriteEnableA) begin
+                        if(WriteAddress[4:0] == 5'd0) begin
+                            DataEnableA[{2'd1, WriteAddress[4:0]}] <= 1'b1;
+                            DataEnableA[63:33] <= 31'd0;
+                            DataEnableB[63:32] <= 32'd0;
+                        end else begin
+                            DataEnableA[{2'd1, WriteAddress[4:0]}] <= 1'b1;
+                        end
+                    end else begin
+                        DataEnableB[{2'd1, WriteAddress[4:0]}] <= 1'b1;
+                    end
+                end
+                if(DataInEnable && (WriteBank == 2'd2)) begin
+                    if(WriteEnableA) begin
+                        if(WriteAddress[4:0] == 5'd0) begin
+                            DataEnableA[{2'd2, WriteAddress[4:0]}] <= 1'b1;
+                            DataEnableA[95:65] <= 31'd0;
+                            DataEnableB[95:64] <= 32'd0;
+                        end else begin
+                            DataEnableA[{2'd2, WriteAddress[4:0]}] <= 1'b1;
+                        end
+                    end else begin
+                        DataEnableB[{2'd2, WriteAddress[4:0]}] <= 1'b1;
+                    end
+                end
+                if(DataInEnable && (WriteBank == 2'd3)) begin
+                    if(WriteEnableA) begin
+                        if(WriteAddress[4:0] == 5'd0) begin
+                            DataEnableA[{2'd3, WriteAddress[4:0]}] <= 1'b1;
+                            DataEnableA[127:97] <= 31'd0;
+                            DataEnableB[127:96] <= 32'd0;
+                        end else begin
+                            DataEnableA[{2'd3, WriteAddress[4:0]}] <= 1'b1;
+                        end
+                    end else begin
+                        DataEnableB[{2'd3, WriteAddress[4:0]}] <= 1'b1;
+                    end
+                end
+            end
+        end
+    end
+
+    reg AddressDelayA, AddressDelayB;
+
+    always @(posedge clk or negedge rst) begin
+        if(!rst) begin
+            AddressDelayA <= 1'b0;
+            AddressDelayB <= 1'b0;
+        end else begin
+            AddressDelayA <= DataEnableA[{ReadBank, DataOutAddress}];
+            AddressDelayB <= DataEnableB[{ReadBank, DataOutAddress}];
+        end
+    end
+
+    // Output Signal
+    assign DataInIdle       = (State == S_IDLE) | (State == S_VALID);
+    assign DataOutEnable    = (State == S_VALID) | (State == S_FULL);
+    assign DataOutColor     = BankColor[ReadBank];
+    assign DataOutA         = (AddressDelayA)?RegMemoryA:16'd0;
+    assign DataOutB         = (AddressDelayB)?RegMemoryB:16'd0;
+
+endmodule

aquaxis_IPCORE/aq_axi_djpeg/aq_axi_djpeg.srcs/xgui/aq_axi_djpeg_v1_0.tcl

@@ -0,0 +1,37 @@
+# Definitional proc to organize widgets for parameters.
+proc init_gui { IPINST } {
+	set Page0 [ipgui::add_page $IPINST -name "Page 0" -layout vertical]
+	set Component_Name [ipgui::add_param $IPINST -parent $Page0 -name Component_Name]
+	set C_ADRSWIDTH [ipgui::add_param $IPINST -parent $Page0 -name C_ADRSWIDTH]
+	set C_BASEADRS [ipgui::add_param $IPINST -parent $Page0 -name C_BASEADRS]
+}
+
+proc update_PARAM_VALUE.C_ADRSWIDTH { PARAM_VALUE.C_ADRSWIDTH } {
+	# Procedure called to update C_ADRSWIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_ADRSWIDTH { PARAM_VALUE.C_ADRSWIDTH } {
+	# Procedure called to validate C_ADRSWIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_BASEADRS { PARAM_VALUE.C_BASEADRS } {
+	# Procedure called to update C_BASEADRS when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_BASEADRS { PARAM_VALUE.C_BASEADRS } {
+	# Procedure called to validate C_BASEADRS
+	return true
+}
+
+
+proc update_MODELPARAM_VALUE.C_BASEADRS { MODELPARAM_VALUE.C_BASEADRS PARAM_VALUE.C_BASEADRS } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_BASEADRS}] ${MODELPARAM_VALUE.C_BASEADRS}
+}
+
+proc update_MODELPARAM_VALUE.C_ADRSWIDTH { MODELPARAM_VALUE.C_ADRSWIDTH PARAM_VALUE.C_ADRSWIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_ADRSWIDTH}] ${MODELPARAM_VALUE.C_ADRSWIDTH}
+}
+

aquaxis_IPCORE/aq_axi_fifo/aq_axi_fifo.srcs/sim/tb_aq_axi_fifo.v

@@ -0,0 +1,472 @@
+/*
+ * Copyright (C)2014-2015 AQUAXIS TECHNOLOGY.
+ *  Don't remove this header. 
+ * When you use this source, there is a need to inherit this header.
+ *
+ * License
+ *  For no commercial -
+ *   License:     The Open Software License 3.0
+ *   License URI: http://www.opensource.org/licenses/OSL-3.0
+ *
+ *  For commmercial -
+ *   License:     AQUAXIS License 1.0
+ *   License URI: http://www.aquaxis.com/licenses
+ *
+ * For further information please contact.
+ *	URI:    http://www.aquaxis.com/
+ *	E-Mail: info(at)aquaxis.com
+ */
+`timescale 1ns / 100ps
+module tb_aq_axi_fifo;
+
+  // Reset, Clock
+  reg           ARESETN;
+  reg           ACLK;
+
+    reg           S_AXI_ACLK;
+    
+    // Write Address Channel
+    reg [31:0]  S_AXI_AWADDR;
+    reg [3:0]   S_AXI_AWCACHE;
+    reg [2:0]   S_AXI_AWPROT;
+    reg         S_AXI_AWVALID;
+    wire        S_AXI_AWREADY; 
+        
+    // Write Data Channel
+    reg [31:0]  S_AXI_WDATA;
+    reg [3:0]   S_AXI_WSTRB;
+    reg         S_AXI_WVALID;
+    wire        S_AXI_WREADY;
+        
+    // Write Response Channel
+    wire        S_AXI_BVALID;
+    wire        S_AXI_BREADY;
+    wire [1:0]  S_AXI_BRESP;
+
+    // Read Address Channe
+    reg [31:0]  S_AXI_ARADDR;
+    reg [3:0]   S_AXI_ARCACHE;
+    reg [2:0]   S_AXI_ARPROT;
+    reg         S_AXI_ARVALID;
+    wire        S_AXI_ARREADY;
+
+    // Read Data Channel
+    wire [31:0] S_AXI_RDATA;
+    wire [1:0]  S_AXI_RRESP;
+    wire        S_AXI_RVALID;
+    reg         S_AXI_RREADY;
+
+  // Master Write Address
+  wire [0:0]  M_AXI_AWID;
+  wire [31:0] M_AXI_AWADDR;
+  wire [7:0]  M_AXI_AWLEN;
+  wire [2:0]  M_AXI_AWSIZE;
+  wire [1:0]  M_AXI_AWBURST;
+  wire        M_AXI_AWLOCK;
+  wire [3:0]  M_AXI_AWCACHE;
+  wire [2:0]  M_AXI_AWPROT;
+  wire [3:0]  M_AXI_AWQOS;
+  wire [0:0]  M_AXI_AWUSER;
+  wire        M_AXI_AWVALID;
+  reg         M_AXI_AWREADY;
+
+  // Master Write Data
+  wire [63:0] M_AXI_WDATA;
+  wire [2:0]  M_AXI_WSTRB;
+  wire        M_AXI_WLAST;
+  wire [0:0]  M_AXI_WUSER;
+  wire        M_AXI_WVALID;
+  reg         M_AXI_WREADY;
+
+  // Master Write Response
+  reg [0:0]   M_AXI_BID;
+  reg [1:0]   M_AXI_BRESP;
+  reg [0:0]   M_AXI_BUSER;
+  reg         M_AXI_BVALID;
+  wire        M_AXI_BREADY;
+    
+  // Master Read Address
+  wire [0:0]  M_AXI_ARID;
+  wire [31:0] M_AXI_ARADDR;
+  wire [7:0]  M_AXI_ARLEN;
+  wire [2:0]  M_AXI_ARSIZE;
+  wire [1:0]  M_AXI_ARBURST;
+  wire [1:0]  M_AXI_ARLOCK;
+  wire [3:0]  M_AXI_ARCACHE;
+  wire [2:0]  M_AXI_ARPROT;
+  wire [3:0]  M_AXI_ARQOS;
+  wire [0:0]  M_AXI_ARUSER;
+  wire        M_AXI_ARVALID;
+  reg         M_AXI_ARREADY;
+    
+  // Master Read Data 
+  reg [0:0]   M_AXI_RID;
+  wire [63:0]  M_AXI_RDATA;
+  reg [1:0]   M_AXI_RRESP;
+  reg         M_AXI_RLAST;
+  reg [0:0]   M_AXI_RUSER;
+  reg         M_AXI_RVALID;
+  wire        M_AXI_RREADY;
+        
+  // Local Bus
+  reg         WR_START;
+  reg [31:0]  WR_ADRS;
+  reg [15:0]  WR_LEN;
+  wire        WR_READY;
+  wire        WR_FIFO_RE;
+  reg         WR_FIFO_EMPTY;
+  reg [63:0]  WR_FIFO_DATA;
+
+  reg         RD_START;
+  reg [31:0]  RD_ADRS;
+  reg [15:0]  RD_LEN;
+  wire        RD_READY;
+  wire        RD_FIFO_WE;
+  reg         RD_FIFO_FULL;
+  wire [63:0] RD_FIFO_DATA;
+
+  wire [31:0] DEBUG;
+
+    // FIFO
+    wire          FIFO_RST;
+    
+    reg           FIFO_RD_CLK;
+    reg           FIFO_RD_EN;
+    wire [63:0]   FIFO_DOUT;
+    wire          FIFO_EMPTY;
+
+    reg           FIFO_WR_CLK;
+    reg [63:0]    FIFO_DIN;
+    reg           FIFO_WR_EN;
+    wire          FIFO_FULL;
+
+  wire fifo_we;
+
+
+  parameter CLK10N = 10;
+
+
+aq_axi_fifo u_aq_axi_fifo(
+  // Reset, Clock
+  .ARESETN(ARESETN),
+
+  .S_AXI_ACLK(ACLK),
+    
+    // Write Address Channel
+  .S_AXI_AWADDR(S_AXI_AWADDR),
+  .S_AXI_AWCACHE(S_AXI_AWCACHE),
+  .S_AXI_AWPROT(S_AXI_AWPROT),
+  .S_AXI_AWVALID(S_AXI_AWVALID),
+  .S_AXI_AWREADY(S_AXI_AWREADY), 
+        
+    // Write Data Channel
+  .S_AXI_WDATA(S_AXI_WDATA),
+  .S_AXI_WSTRB(S_AXI_WSTRB),
+  .S_AXI_WVALID(S_AXI_WVALID),
+  .S_AXI_WREADY(S_AXI_WREADY),
+        
+    // Write Response Channel
+  .S_AXI_BVALID(S_AXI_BVALID),
+  .S_AXI_BREADY(S_AXI_BREADY),
+  .S_AXI_BRESP(S_AXI_BRESP),
+
+    // Read Address Channel
+  .S_AXI_ARADDR(S_AXI_ARADDR),
+  .S_AXI_ARCACHE(S_AXI_ARCACHE),
+  .S_AXI_ARPROT(S_AXI_ARPROT),
+  .S_AXI_ARVALID(S_AXI_ARVALID),
+  .S_AXI_ARREADY(S_AXI_ARREADY),
+
+    // Read Data Channel
+  .S_AXI_RDATA(S_AXI_RDATA),
+  .S_AXI_RRESP(S_AXI_RRESP),
+  .S_AXI_RVALID(S_AXI_RVALID),
+  .S_AXI_RREADY(S_AXI_RREADY),
+
+
+  .M_AXI_ACLK(ACLK),
+
+  // Master Write Address
+  .M_AXI_AWID(M_AXI_AWID),
+  .M_AXI_AWADDR(M_AXI_AWADDR),
+  .M_AXI_AWLEN(M_AXI_AWLEN),
+  .M_AXI_AWSIZE(M_AXI_AWSIZE),
+  .M_AXI_AWBURST(M_AXI_AWBURST),
+  .M_AXI_AWLOCK(M_AXI_AWLOCK),
+  .M_AXI_AWCACHE(M_AXI_AWCACHE),
+  .M_AXI_AWPROT(M_AXI_AWPROT),
+  .M_AXI_AWQOS(M_AXI_AWQOS),
+  .M_AXI_AWUSER(M_AXI_AWUSER),
+  .M_AXI_AWVALID(M_AXI_AWVALID),
+  .M_AXI_AWREADY(M_AXI_AWREADY),
+
+  // Master Write Data
+  .M_AXI_WDATA(M_AXI_WDATA),
+  .M_AXI_WSTRB(M_AXI_WSTRB),
+  .M_AXI_WLAST(M_AXI_WLAST),
+  .M_AXI_WUSER(M_AXI_WUSER),
+  .M_AXI_WVALID(M_AXI_WVALID),
+  .M_AXI_WREADY(M_AXI_WREADY),
+
+  // Master Write Response
+  .M_AXI_BID(M_AXI_BID),
+  .M_AXI_BRESP(M_AXI_BRESP),
+  .M_AXI_BUSER(M_AXI_BUSER),
+  .M_AXI_BVALID(M_AXI_BVALID),
+  .M_AXI_BREADY(M_AXI_BREADY),
+    
+  // Master Read Address
+  .M_AXI_ARID(M_AXI_ARID),
+  .M_AXI_ARADDR(M_AXI_ARADDR),
+  .M_AXI_ARLEN(M_AXI_ARLEN),
+  .M_AXI_ARSIZE(M_AXI_ARSIZE),
+  .M_AXI_ARBURST(M_AXI_ARBURST),
+  .M_AXI_ARLOCK(M_AXI_ARLOCK),
+  .M_AXI_ARCACHE(M_AXI_ARCACHE),
+  .M_AXI_ARPROT(M_AXI_ARPROT),
+  .M_AXI_ARQOS(M_AXI_ARQOS),
+  .M_AXI_ARUSER(M_AXI_ARUSER),
+  .M_AXI_ARVALID(M_AXI_ARVALID),
+  .M_AXI_ARREADY(M_AXI_ARREADY),
+    
+  // Master Read Data 
+  .M_AXI_RID(M_AXI_RID),
+  .M_AXI_RDATA(M_AXI_RDATA),
+  .M_AXI_RRESP(M_AXI_RRESP),
+  .M_AXI_RLAST(M_AXI_RLAST),
+  .M_AXI_RUSER(M_AXI_RUSER),
+  .M_AXI_RVALID(M_AXI_RVALID),
+  .M_AXI_RREADY(M_AXI_RREADY),
+        
+  .FIFO_RST(FIFO_RST),
+    
+  .FIFO_RD_CLK(ACLK),
+  .FIFO_RD_EN(fifo_we),
+  .FIFO_DOUT(FIFO_DOUT),
+  .FIFO_EMPTY(FIFO_EMPTY),
+
+  .FIFO_WR_CLK(ACLK),
+  .FIFO_DIN(FIFO_DOUT),
+  .FIFO_WR_EN(fifo_we),
+  .FIFO_FULL(FIFO_FULL),
+
+  .DEBUG(DEBUG)
+);
+
+reg fifo_we_ena;
+initial begin
+  fifo_we_ena <= 0;
+  
+  wait(!FIFO_EMPTY);
+
+end
+
+assign fifo_we = (fifo_we_ena)?~FIFO_EMPTY:1'b0;
+
+initial begin
+  ACLK <=1'b0;
+end
+
+// Clock
+always begin
+  #(CLK10N/2) ACLK <= ~ACLK;
+end
+
+// Reset
+initial begin
+  ARESETN <= 1'b0;
+  #(100);
+  ARESETN <= 1'b1;
+end
+
+assign S_AXI_BREADY = S_AXI_BVALID;
+
+// Read Control
+initial begin
+  S_AXI_AWADDR  <= 32'h4000_0000;
+  S_AXI_AWCACHE <= 3'd0;
+  S_AXI_AWPROT  <= 2'd0;
+  S_AXI_AWVALID   <= 1'b0;
+  S_AXI_WDATA  <= 32'h0000_0000;
+  S_AXI_WSTRB  <= 4'H0;
+  S_AXI_WVALID <= 1'b0;
+
+  wait (ARESETN);
+
+  @(negedge ACLK);
+  @(negedge ACLK);
+
+// Read Count
+  @(negedge ACLK);
+
+  S_AXI_AWADDR <= 32'h4000_0014;
+  S_AXI_AWVALID  <= 1'b1;
+
+  @(negedge ACLK);
+
+  wait(S_AXI_AWREADY);
+  S_AXI_AWVALID  <= 1'b0;
+
+  @(negedge ACLK);
+
+  S_AXI_WDATA  <= 32'h0000_2000;
+  S_AXI_WSTRB  <= 4'HF;
+  S_AXI_WVALID <= 1'b1;
+
+  wait(S_AXI_WREADY);
+
+  @(negedge ACLK);
+
+  S_AXI_WVALID <= 1'b0;
+
+  @(negedge ACLK);
+//
+
+// Read Address
+  @(negedge ACLK);
+
+  S_AXI_AWADDR <= 32'h4000_0010;
+  S_AXI_AWVALID  <= 1'b1;
+
+  @(negedge ACLK);
+
+  wait(S_AXI_AWREADY);
+  S_AXI_AWVALID  <= 1'b0;
+
+  @(negedge ACLK);
+
+  S_AXI_WDATA  <= 32'h3322_1100;
+  S_AXI_WSTRB  <= 4'HF;
+  S_AXI_WVALID <= 1'b1;
+
+  wait(S_AXI_WREADY);
+
+  @(negedge ACLK);
+
+  S_AXI_WVALID <= 1'b0;
+
+  @(negedge ACLK);
+//
+
+// Start Read
+  @(negedge ACLK);
+
+  S_AXI_AWADDR <= 32'h4000_000C;
+  S_AXI_AWVALID  <= 1'b1;
+
+  @(negedge ACLK);
+
+  wait(S_AXI_AWREADY);
+  S_AXI_AWVALID  <= 1'b0;
+
+  @(negedge ACLK);
+
+  S_AXI_WDATA  <= 32'h0000_0001;
+  S_AXI_WSTRB  <= 4'HF;
+  S_AXI_WVALID <= 1'b1;
+
+  wait(S_AXI_WREADY);
+
+  @(negedge ACLK);
+
+  S_AXI_WVALID <= 1'b0;
+
+  @(negedge ACLK);
+//
+
+
+end
+
+initial begin
+  RD_FIFO_FULL <= 1'b0;
+end
+
+// Write Control
+initial begin
+  WR_START <= 1'b0;
+  WR_ADRS <= 32'd0;
+  WR_LEN <= 16'd0;
+
+  wait (ARESETN);
+
+  @(negedge ACLK);
+  @(negedge ACLK);
+  @(negedge ACLK);
+
+  WR_START <= 1'b1;
+  WR_ADRS <= 32'h1C800000;
+  WR_LEN <= 16'd8;
+
+  @(negedge ACLK);
+
+  WR_START <= 1'b0;
+
+  @(negedge ACLK);
+  @(negedge ACLK);
+
+  @(negedge ACLK);
+  @(negedge ACLK);
+  @(negedge ACLK);
+
+
+end
+
+
+
+// AXI Read Data
+assign M_AXI_ARREADY = M_AXI_ARVALID;
+
+reg [31:0] count,rcount;
+always @(posedge ACLK or negedge ARESETN) begin
+    if(!ARESETN) begin
+        count <= 32'd0;
+        rcount <= 32'd0;
+        M_AXI_RVALID<=1'b0;
+    end else begin
+      if(M_AXI_RLAST) begin
+        axi_rena <= 0;
+      end else if(M_AXI_ARVALID) begin
+        axi_rena <= 1;
+      end
+
+      if(axi_rena) begin
+        count <= count + 32'd1;
+      end else begin
+        count <= 0;
+      end
+
+      if(M_AXI_RVALID & M_AXI_RREADY) begin
+          rcount <= rcount + 32'd1;
+      end
+    end
+end
+assign M_AXI_RDATA  = {rcount,rcount};
+assign M_AXI_RLAST  = (axi_rena & (count == 255))?1:0;
+assign M_AXI_RVALID = axi_rena;
+
+// AXI Write Control
+initial begin
+
+  M_AXI_BID <= 1'b0;
+  M_AXI_BRESP <= 2'b00;
+  M_AXI_BUSER <= 1'b0;
+
+end
+
+always @(posedge ACLK or negedge ARESETN)begin
+  if(!ARESETN) begin
+    axiwvalid <= 0;
+  end else begin
+    if(M_AXI_BREADY) begin
+      axiwvalid <= 0;
+    end else if (M_AXI_WVALID & M_AXI_WLAST) begin
+      axiwvalid <= 1;
+    end
+  end
+end
+
+assign M_AXI_AWREADY = M_AXI_AWVALID;
+assign M_AXI_WREADY  = M_AXI_WVALID;
+assign M_AXI_BVALID  = axi_wvalid;
+
+endmodule

aquaxis_IPCORE/aq_axi_fifo/aq_axi_fifo.srcs/sim/tb_aq_axi_master.v

@@ -0,0 +1,361 @@
+/*
+ * Copyright (C)2014-2015 AQUAXIS TECHNOLOGY.
+ *  Don't remove this header. 
+ * When you use this source, there is a need to inherit this header.
+ *
+ * License
+ *  For no commercial -
+ *   License:     The Open Software License 3.0
+ *   License URI: http://www.opensource.org/licenses/OSL-3.0
+ *
+ *  For commmercial -
+ *   License:     AQUAXIS License 1.0
+ *   License URI: http://www.aquaxis.com/licenses
+ *
+ * For further information please contact.
+ *	URI:    http://www.aquaxis.com/
+ *	E-Mail: info(at)aquaxis.com
+ */
+`timescale 1ns / 100ps
+module tb_aq_axi_master;
+
+  // Reset, Clock
+  reg           ARESETN;
+  reg           ACLK;
+
+  // Master Write Address
+  wire [0:0]  M_AXI_AWID;
+  wire [31:0] M_AXI_AWADDR;
+  wire [7:0]  M_AXI_AWLEN;
+  wire [2:0]  M_AXI_AWSIZE;
+  wire [1:0]  M_AXI_AWBURST;
+  wire        M_AXI_AWLOCK;
+  wire [3:0]  M_AXI_AWCACHE;
+  wire [2:0]  M_AXI_AWPROT;
+  wire [3:0]  M_AXI_AWQOS;
+  wire [0:0]  M_AXI_AWUSER;
+  wire        M_AXI_AWVALID;
+  reg         M_AXI_AWREADY;
+
+  // Master Write Data
+  wire [63:0] M_AXI_WDATA;
+  wire [2:0]  M_AXI_WSTRB;
+  wire        M_AXI_WLAST;
+  wire [0:0]  M_AXI_WUSER;
+  wire        M_AXI_WVALID;
+  reg         M_AXI_WREADY;
+
+  // Master Write Response
+  reg [0:0]   M_AXI_BID;
+  reg [1:0]   M_AXI_BRESP;
+  reg [0:0]   M_AXI_BUSER;
+  reg         M_AXI_BVALID;
+  wire        M_AXI_BREADY;
+    
+  // Master Read Address
+  wire [0:0]  M_AXI_ARID;
+  wire [31:0] M_AXI_ARADDR;
+  wire [7:0]  M_AXI_ARLEN;
+  wire [2:0]  M_AXI_ARSIZE;
+  wire [1:0]  M_AXI_ARBURST;
+  wire [1:0]  M_AXI_ARLOCK;
+  wire [3:0]  M_AXI_ARCACHE;
+  wire [2:0]  M_AXI_ARPROT;
+  wire [3:0]  M_AXI_ARQOS;
+  wire [0:0]  M_AXI_ARUSER;
+  wire        M_AXI_ARVALID;
+  reg         M_AXI_ARREADY;
+    
+  // Master Read Data 
+  reg [0:0]   M_AXI_RID;
+  reg [63:0]  M_AXI_RDATA;
+  reg [1:0]   M_AXI_RRESP;
+  reg         M_AXI_RLAST;
+  reg [0:0]   M_AXI_RUSER;
+  reg         M_AXI_RVALID;
+  wire        M_AXI_RREADY;
+        
+  // Local Bus
+  reg         WR_START;
+  reg [31:0]  WR_ADRS;
+  reg [15:0]  WR_LEN;
+  wire        WR_READY;
+  wire        WR_FIFO_RE;
+  reg         WR_FIFO_EMPTY;
+  reg [63:0]  WR_FIFO_DATA;
+
+  reg         RD_START;
+  reg [31:0]  RD_ADRS;
+  reg [15:0]  RD_LEN;
+  wire        RD_READY;
+  wire        RD_FIFO_WE;
+  reg         RD_FIFO_FULL;
+  wire [63:0] RD_FIFO_DATA;
+
+  wire [31:0] DEBUG;
+
+  parameter CLK10N = 10;
+
+
+aq_axi_master u_aq_axi_master(
+  // Reset, Clock
+  .ARESETN(ARESETN),
+  .ACLK(ACLK),
+
+  // Master Write Address
+  .M_AXI_AWID(M_AXI_AWID),
+  .M_AXI_AWADDR(M_AXI_AWADDR),
+  .M_AXI_AWLEN(M_AXI_AWLEN),
+  .M_AXI_AWSIZE(M_AXI_AWSIZE),
+  .M_AXI_AWBURST(M_AXI_AWBURST),
+  .M_AXI_AWLOCK(M_AXI_AWLOCK),
+  .M_AXI_AWCACHE(M_AXI_AWCACHE),
+  .M_AXI_AWPROT(M_AXI_AWPROT),
+  .M_AXI_AWQOS(M_AXI_AWQOS),
+  .M_AXI_AWUSER(M_AXI_AWUSER),
+  .M_AXI_AWVALID(M_AXI_AWVALID),
+  .M_AXI_AWREADY(M_AXI_AWREADY),
+
+  // Master Write Data
+  .M_AXI_WDATA(M_AXI_WDATA),
+  .M_AXI_WSTRB(M_AXI_WSTRB),
+  .M_AXI_WLAST(M_AXI_WLAST),
+  .M_AXI_WUSER(M_AXI_WUSER),
+  .M_AXI_WVALID(M_AXI_WVALID),
+  .M_AXI_WREADY(M_AXI_WREADY),
+
+  // Master Write Response
+  .M_AXI_BID(M_AXI_BID),
+  .M_AXI_BRESP(M_AXI_BRESP),
+  .M_AXI_BUSER(M_AXI_BUSER),
+  .M_AXI_BVALID(M_AXI_BVALID),
+  .M_AXI_BREADY(M_AXI_BREADY),
+    
+  // Master Read Address
+  .M_AXI_ARID(M_AXI_ARID),
+  .M_AXI_ARADDR(M_AXI_ARADDR),
+  .M_AXI_ARLEN(M_AXI_ARLEN),
+  .M_AXI_ARSIZE(M_AXI_ARSIZE),
+  .M_AXI_ARBURST(M_AXI_ARBURST),
+  .M_AXI_ARLOCK(M_AXI_ARLOCK),
+  .M_AXI_ARCACHE(M_AXI_ARCACHE),
+  .M_AXI_ARPROT(M_AXI_ARPROT),
+  .M_AXI_ARQOS(M_AXI_ARQOS),
+  .M_AXI_ARUSER(M_AXI_ARUSER),
+  .M_AXI_ARVALID(M_AXI_ARVALID),
+  .M_AXI_ARREADY(M_AXI_ARREADY),
+    
+  // Master Read Data 
+  .M_AXI_RID(M_AXI_RID),
+  .M_AXI_RDATA(M_AXI_RDATA),
+  .M_AXI_RRESP(M_AXI_RRESP),
+  .M_AXI_RLAST(M_AXI_RLAST),
+  .M_AXI_RUSER(M_AXI_RUSER),
+  .M_AXI_RVALID(M_AXI_RVALID),
+  .M_AXI_RREADY(M_AXI_RREADY),
+        
+  // Local Bus
+  .WR_START(WR_START),
+  .WR_ADRS(WR_ADRS),
+  .WR_LEN(WR_LEN), 
+  .WR_READY(WR_READY),
+  .WR_FIFO_RE(WR_FIFO_RE),
+  .WR_FIFO_EMPTY(WR_FIFO_EMPTY),
+  .WR_FIFO_DATA(WR_FIFO_DATA),
+
+  .RD_START(RD_START),
+  .RD_ADRS(RD_ADRS),
+  .RD_LEN(RD_LEN), 
+  .RD_READY(RD_READY),
+  .RD_FIFO_WE(RD_FIFO_WE),
+  .RD_FIFO_FULL(RD_FIFO_FULL),
+  .RD_FIFO_DATA(RD_FIFO_DATA),
+
+  .DEBUG(DEBUG)
+);
+
+initial begin
+  ACLK <=1'b0;
+end
+
+// Clock
+always begin
+  #(CLK10N/2) ACLK <= ~ACLK;
+end
+
+// Reset
+initial begin
+  ARESETN <= 1'b0;
+  #(100);
+  ARESETN <= 1'b1;
+end
+
+// Read Control
+initial begin
+  RD_START <= 1'b0;
+  RD_ADRS <= 32'd0;
+  RD_LEN <= 16'd0;
+
+  wait (ARESETN);
+
+  @(negedge ACLK);
+  @(negedge ACLK);
+  @(negedge ACLK);
+
+  RD_START <= 1'b0;
+  RD_ADRS <= 32'h1C000000;
+  RD_LEN <= 16'd8;
+
+  @(negedge ACLK);
+
+  RD_START <= 1'b0;
+  RD_ADRS <= 32'd0;
+  RD_LEN <= 16'd0;
+
+  @(negedge ACLK);
+
+end
+
+initial begin
+  RD_FIFO_FULL <= 1'b0;
+end
+
+// Write Control
+initial begin
+  WR_START <= 1'b0;
+  WR_ADRS <= 32'd0;
+  WR_LEN <= 16'd0;
+
+  wait (ARESETN);
+
+  @(negedge ACLK);
+  @(negedge ACLK);
+  @(negedge ACLK);
+
+  WR_START <= 1'b1;
+  WR_ADRS <= 32'h1C800000;
+  WR_LEN <= 16'd8;
+
+  @(negedge ACLK);
+
+  WR_START <= 1'b0;
+
+  @(negedge ACLK);
+  @(negedge ACLK);
+
+  @(negedge ACLK);
+  @(negedge ACLK);
+  @(negedge ACLK);
+
+
+end
+
+initial begin
+  WR_FIFO_EMPTY <= 1'b0;
+  WR_FIFO_DATA  <= 64'h0000_0000_0000_0000;
+
+  wait (ARESETN);
+
+  @(negedge ACLK);
+  @(negedge ACLK);
+  @(negedge ACLK);
+
+  WR_FIFO_DATA  <= 64'h3333_2222_1111_1010;
+
+  wait(WR_FIFO_RE);
+
+  WR_FIFO_DATA  <= 64'h4444_3333_2222_1111;
+
+  wait(WR_FIFO_RE);
+
+  WR_FIFO_DATA  <= 64'h5555_4444_3333_2222;
+
+  wait(WR_FIFO_RE);
+
+  WR_FIFO_DATA  <= 64'h6666_5555_4444_3333;
+
+end
+
+// AXI Read Control
+initial begin
+
+  M_AXI_ARREADY <= 1'b0;
+
+  wait (ARESETN);
+
+  @(negedge ACLK);
+  @(negedge ACLK);
+  @(negedge ACLK);
+
+  wait(M_AXI_ARVALID);
+
+  @(negedge ACLK);
+
+  M_AXI_ARREADY <= 1'b1;
+
+  @(negedge ACLK);
+
+  M_AXI_ARREADY <= 1'b0;
+
+  @(negedge ACLK);
+
+
+
+end
+
+// AXI Write Control
+initial begin
+
+  M_AXI_AWREADY <= 1'b0;
+  M_AXI_WREADY <= 1'b0;
+  M_AXI_BID <= 1'b0;
+  M_AXI_BRESP <= 2'b00;
+  M_AXI_BUSER <= 1'b0;
+  M_AXI_BVALID <= 1'b0;
+
+  wait (ARESETN);
+
+  @(negedge ACLK);
+  @(negedge ACLK);
+  @(negedge ACLK);
+
+  wait(M_AXI_AWVALID);
+
+  @(negedge ACLK);
+
+  M_AXI_AWREADY <= 1'b1;
+
+  @(negedge ACLK);
+
+  M_AXI_AWREADY <= 1'b0;
+
+  wait(M_AXI_WVALID);
+
+  @(negedge ACLK);
+
+  M_AXI_WREADY <= 1'b1;
+
+  @(negedge ACLK);
+
+  M_AXI_WREADY <= 1'b0;
+
+  @(negedge ACLK);
+
+  M_AXI_BID <= 1'b0;
+  M_AXI_BRESP <= 2'b00;
+  M_AXI_BUSER <= 1'b0;
+
+  wait(M_AXI_BREADY);
+
+  @(negedge ACLK);
+
+  M_AXI_BVALID <= 1'b1;
+
+  @(negedge ACLK);
+
+  M_AXI_BVALID <= 1'b0;
+
+
+end
+
+endmodule

aquaxis_IPCORE/aq_axi_fifo/aq_axi_fifo.srcs/sim/tb_aq_fifo.v

@@ -0,0 +1,109 @@
+/*
+ * Copyright (C)2014-2015 AQUAXIS TECHNOLOGY.
+ *  Don't remove this header. 
+ * When you use this source, there is a need to inherit this header.
+ *
+ * License
+ *  For no commercial -
+ *   License:     The Open Software License 3.0
+ *   License URI: http://www.opensource.org/licenses/OSL-3.0
+ *
+ *  For commmercial -
+ *   License:     AQUAXIS License 1.0
+ *   License URI: http://www.aquaxis.com/licenses
+ *
+ * For further information please contact.
+ *	URI:    http://www.aquaxis.com/
+ *	E-Mail: info(at)aquaxis.com
+ */
+`timescale 1ns / 1ps
+module tb_aq_fifo;
+
+reg         RST;
+
+reg         WRCLK;
+reg         WREN;
+reg [63:0]  DI;
+wire        FULL;
+wire        AFULL;
+wire [7:0]  WRCOUNT;
+
+reg         RDCLK;
+reg         RDEN;
+wire [63:0] DO;
+wire        EMPTY;
+wire        AEMPTY;
+wire [7:0]  RDCOUNT;
+
+  aq_fifo u_aq_rfifo
+    (
+      .RST(RST),
+      
+      .WRCLK(WRCLK),
+      .WREN(WREN),
+      .DI(DI),
+      .FULL(FULL),
+      .AFULL(AFULL),
+      .WRCOUNT(WRCOUNT),
+      
+      .RDCLK(RDCLK),
+      .RDEN(RDEN), 
+      .DO(DO),
+      .EMPTY(EMPTY),
+      .AEMPTY(AEMPTY),
+      .RDCOUNT(RDCOUNT)
+    );
+
+// Clock
+initial begin
+WRCLK <= 1'b0;
+RDCLK <= 1'b0;
+end
+
+parameter CLK100N = 10;
+
+always begin
+  #(CLK100N/2) WRCLK <= ~WRCLK;
+end
+always begin
+  #(CLK100N/2) RDCLK <= ~RDCLK;
+end
+
+// Reset
+initial begin
+  RST <= 1'b0;
+  #(1000);
+  RST <= 1'b1;
+  #(1000);
+  RST <= 1'b0;
+end
+
+// Signal
+integer wrcount, rdcount;
+
+always @(negedge WRCLK or posedge RST) begin
+  if(RST) begin
+    wrcount <= 0;
+    WREN <= 1'b0;
+    DI <= 64'd0;
+  end else begin
+    wrcount <= wrcount +1;
+    if((wrcount >= 100) && (wrcount < 1024+100-256)) begin
+      WREN <= 1'b1;
+      DI <= DI + 64'd1;
+    end else begin
+      WREN <= 1'b0;
+      DI <= 64'd0;
+    end
+  end
+end
+
+always @(negedge RDCLK or posedge RST) begin
+  if(RST) begin
+    rdcount <= 0;
+    RDEN <= 1'b0;
+  end else begin
+  end
+end
+
+endmodule

aquaxis_IPCORE/aq_axi_fifo/aq_axi_fifo.srcs/sources/aq_axi_fifo.v

@@ -0,0 +1,412 @@
+/*
+ * Copyright (C)2014-2015 AQUAXIS TECHNOLOGY.
+ *  Don't remove this header. 
+ * When you use this source, there is a need to inherit this header.
+ *
+ * License
+ *  For no commercial -
+ *   License:     The Open Software License 3.0
+ *   License URI: http://www.opensource.org/licenses/OSL-3.0
+ *
+ *  For commmercial -
+ *   License:     AQUAXIS License 1.0
+ *   License URI: http://www.aquaxis.com/licenses
+ *
+ * For further information please contact.
+ *	URI:    http://www.aquaxis.com/
+ *	E-Mail: info(at)aquaxis.com
+ */
+module aq_axi_fifo
+  #(
+    parameter       C_BASEADRS  = 32'h4000_0000,
+    parameter       C_ADRSWIDTH = 8
+    )
+  (
+    input           ARESETN,
+
+    // --------------------------------------------------
+    // AXI4 Lite Interface
+    // --------------------------------------------------
+    input           S_AXI_ACLK,
+    
+    // Write Address Channel
+    input [31:0]  S_AXI_AWADDR,
+    input [3:0]   S_AXI_AWCACHE,
+    input [2:0]   S_AXI_AWPROT,
+    input         S_AXI_AWVALID,
+    output        S_AXI_AWREADY, 
+        
+    // Write Data Channel
+    input [31:0]  S_AXI_WDATA,
+    input [3:0]   S_AXI_WSTRB,
+    input         S_AXI_WVALID,
+    output        S_AXI_WREADY,
+        
+    // Write Response Channel
+    output        S_AXI_BVALID,
+    input         S_AXI_BREADY,
+    output [1:0]  S_AXI_BRESP,
+
+    // Read Address Channel
+    input [31:0]  S_AXI_ARADDR,
+    input [3:0]   S_AXI_ARCACHE,
+    input [2:0]   S_AXI_ARPROT,
+    input         S_AXI_ARVALID,
+    output        S_AXI_ARREADY,
+
+    // Read Data Channel
+    output [31:0] S_AXI_RDATA,
+    output [1:0]  S_AXI_RRESP,
+    output        S_AXI_RVALID,
+    input         S_AXI_RREADY,
+
+    // --------------------------------------------------
+    // AXI4 Master
+    // --------------------------------------------------
+    // Reset, Clock
+    input         M_AXI_ACLK,
+
+    // Master Write Address
+    output [0:0]  M_AXI_AWID,
+    output [31:0] M_AXI_AWADDR,
+    output [7:0]  M_AXI_AWLEN,
+    output [2:0]  M_AXI_AWSIZE,
+    output [1:0]  M_AXI_AWBURST,
+    output        M_AXI_AWLOCK,
+    output [3:0]  M_AXI_AWCACHE,
+    output [2:0]  M_AXI_AWPROT,
+    output [3:0]  M_AXI_AWQOS,
+    output [0:0]  M_AXI_AWUSER,
+    output        M_AXI_AWVALID,
+    input         M_AXI_AWREADY,
+
+    // Master Write Data
+    output [63:0] M_AXI_WDATA,
+    output [7:0]  M_AXI_WSTRB,
+    output        M_AXI_WLAST,
+    output [0:0]  M_AXI_WUSER,
+    output        M_AXI_WVALID,
+    input         M_AXI_WREADY,
+
+    // Master Write Response
+    input [0:0]   M_AXI_BID,
+    input [1:0]   M_AXI_BRESP,
+    input [0:0]   M_AXI_BUSER,
+    input         M_AXI_BVALID,
+    output        M_AXI_BREADY,
+    
+    // Master Read Address
+    output [0:0]  M_AXI_ARID,
+    output [31:0] M_AXI_ARADDR,
+    output [7:0]  M_AXI_ARLEN,
+    output [2:0]  M_AXI_ARSIZE,
+    output [1:0]  M_AXI_ARBURST,
+    output [1:0]  M_AXI_ARLOCK,
+    output [3:0]  M_AXI_ARCACHE,
+    output [2:0]  M_AXI_ARPROT,
+    output [3:0]  M_AXI_ARQOS,
+    output [0:0]  M_AXI_ARUSER,
+    output        M_AXI_ARVALID,
+    input         M_AXI_ARREADY,
+    
+    // Master Read Data 
+    input [0:0]   M_AXI_RID,
+    input [63:0]  M_AXI_RDATA,
+    input [1:0]   M_AXI_RRESP,
+    input         M_AXI_RLAST,
+    input [0:0]   M_AXI_RUSER,
+    input         M_AXI_RVALID,
+    output        M_AXI_RREADY,
+
+    // FIFO
+    output          FIFO_RST,
+    
+    input           FIFO_RD_CLK,
+    input           FIFO_RD_EN,
+    output [63:0]   FIFO_RD_DO,
+    output          FIFO_RD_EMPTY,
+
+    input           FIFO_WR_CLK,
+    input [63:0]    FIFO_WR_DI,
+    input           FIFO_WR_EN,
+    output          FIFO_WR_FULL,
+
+    output [31:0]   DEBUG
+   );
+
+  wire           local_cs;
+  wire           local_rnw;
+  wire           local_ack;
+  wire [31:0]    local_addr;
+  wire [3:0]     local_be;
+  wire [31:0]    local_wdata;
+  wire [31:0]    local_rdata;
+
+  wire           wr_start;
+   
+  wire [31:0]    wr_adrs;
+  wire [31:0]    wr_len;
+  wire           wr_ready;
+  wire           wr_fifo_re;
+  wire           wr_fifo_empty;
+  wire           wr_fifo_aempty;
+  wire [63:0]    wr_fifo_data;
+
+  wire           rd_start;
+  wire [31:0]    rd_adrs;
+  wire [31:0]    rd_len;
+  wire           rd_ready;
+  wire           rd_fifo_we;
+  wire           rd_fifo_full;
+  wire           rd_fifo_afull;
+  wire [63:0]    rd_fifo_data;
+
+  wire [31:0]    master_status;
+
+  reg [31:0]      wr_fifo_wrcnt, wr_fifo_rdcnt, rd_fifo_wrcnt, rd_fifo_rdcnt;
+
+  wire [31:0]    debug_slave, debug_ctl, debug_master;
+
+  aq_axi_lite_slave
+    #(
+      .C_BASEADRS(C_BASEADRS),
+      .C_ADRSWIDTH(C_ADRSWIDTH)
+    )
+  u_aq_axi_lite_slave 
+    (
+      .ARESETN(ARESETN),
+      .ACLK(S_AXI_ACLK),
+      
+      .S_AXI_AWADDR(S_AXI_AWADDR),
+      .S_AXI_AWCACHE(S_AXI_AWCACHE),
+      .S_AXI_AWPROT(S_AXI_AWPROT),
+      .S_AXI_AWVALID(S_AXI_AWVALID),
+      .S_AXI_AWREADY(S_AXI_AWREADY),
+      
+      .S_AXI_WDATA(S_AXI_WDATA),
+      .S_AXI_WSTRB(S_AXI_WSTRB),
+      .S_AXI_WVALID(S_AXI_WVALID),
+      .S_AXI_WREADY(S_AXI_WREADY),
+      
+      .S_AXI_BVALID(S_AXI_BVALID),
+      .S_AXI_BREADY(S_AXI_BREADY),
+      .S_AXI_BRESP(S_AXI_BRESP),
+      
+      .S_AXI_ARADDR(S_AXI_ARADDR),
+      .S_AXI_ARCACHE(S_AXI_ARCACHE),
+      .S_AXI_ARPROT(S_AXI_ARPROT),
+      .S_AXI_ARVALID(S_AXI_ARVALID),
+      .S_AXI_ARREADY(S_AXI_ARREADY),
+      
+      .S_AXI_RDATA(S_AXI_RDATA),
+      .S_AXI_RRESP(S_AXI_RRESP),
+      .S_AXI_RVALID(S_AXI_RVALID),
+      .S_AXI_RREADY(S_AXI_RREADY),
+      
+      .LOCAL_CS(local_cs),
+      .LOCAL_RNW(local_rnw),
+      .LOCAL_ACK(local_ack),
+      .LOCAL_ADDR(local_addr),
+      .LOCAL_BE(local_be),
+      .LOCAL_WDATA(local_wdata),
+      .LOCAL_RDATA(local_rdata),
+      
+      .DEBUG(debug_slave)
+      );
+   
+  aq_axi_master u_aq_axi_master
+    (
+      .ARESETN(ARESETN),
+      .ACLK(M_AXI_ACLK),
+      
+      .M_AXI_AWID(M_AXI_AWID),
+      .M_AXI_AWADDR(M_AXI_AWADDR),
+      .M_AXI_AWLEN(M_AXI_AWLEN),
+      .M_AXI_AWSIZE(M_AXI_AWSIZE),
+      .M_AXI_AWBURST(M_AXI_AWBURST),
+      .M_AXI_AWLOCK(M_AXI_AWLOCK),
+      .M_AXI_AWCACHE(M_AXI_AWCACHE),
+      .M_AXI_AWPROT(M_AXI_AWPROT),
+      .M_AXI_AWQOS(M_AXI_AWQOS),
+      .M_AXI_AWUSER(M_AXI_AWUSER),
+      .M_AXI_AWVALID(M_AXI_AWVALID),
+      .M_AXI_AWREADY(M_AXI_AWREADY),
+      
+      .M_AXI_WDATA(M_AXI_WDATA),
+      .M_AXI_WSTRB(M_AXI_WSTRB),
+      .M_AXI_WLAST(M_AXI_WLAST),
+      .M_AXI_WUSER(M_AXI_WUSER),
+      .M_AXI_WVALID(M_AXI_WVALID),
+      .M_AXI_WREADY(M_AXI_WREADY),
+      
+      .M_AXI_BID(M_AXI_BID),
+      .M_AXI_BRESP(M_AXI_BRESP),
+      .M_AXI_BUSER(M_AXI_BUSER),
+      .M_AXI_BVALID(M_AXI_BVALID),
+      .M_AXI_BREADY(M_AXI_BREADY),
+      
+      .M_AXI_ARID(M_AXI_ARID),
+      .M_AXI_ARADDR(M_AXI_ARADDR),
+      .M_AXI_ARLEN(M_AXI_ARLEN),
+      .M_AXI_ARSIZE(M_AXI_ARSIZE),
+      .M_AXI_ARBURST(M_AXI_ARBURST),
+      .M_AXI_ARLOCK(M_AXI_ARLOCK),
+      .M_AXI_ARCACHE(M_AXI_ARCACHE),
+      .M_AXI_ARPROT(M_AXI_ARPROT),
+      .M_AXI_ARQOS(M_AXI_ARQOS),
+      .M_AXI_ARUSER(M_AXI_ARUSER),
+      .M_AXI_ARVALID(M_AXI_ARVALID),
+      .M_AXI_ARREADY(M_AXI_ARREADY),
+      
+      .M_AXI_RID(M_AXI_RID),
+      .M_AXI_RDATA(M_AXI_RDATA),
+      .M_AXI_RRESP(M_AXI_RRESP),
+      .M_AXI_RLAST(M_AXI_RLAST),
+      .M_AXI_RUSER(M_AXI_RUSER),
+      .M_AXI_RVALID(M_AXI_RVALID),
+      .M_AXI_RREADY(M_AXI_RREADY),
+      
+      .MASTER_RST(FIFO_RST),
+      
+      .WR_START(wr_start),
+      .WR_ADRS(wr_adrs),
+      .WR_LEN(wr_len), 
+      .WR_READY(wr_ready),
+      .WR_FIFO_RE(wr_fifo_re),
+      .WR_FIFO_EMPTY(wr_fifo_empty),
+      .WR_FIFO_AEMPTY(wr_fifo_aempty),
+      .WR_FIFO_DATA(wr_fifo_data),
+      
+      .RD_START(rd_start),
+      .RD_ADRS(rd_adrs),
+      .RD_LEN(rd_len), 
+      .RD_READY(rd_ready),
+      .RD_FIFO_WE(rd_fifo_we),
+      .RD_FIFO_FULL(rd_fifo_full),
+      .RD_FIFO_AFULL(rd_fifo_afull),
+      .RD_FIFO_DATA(rd_fifo_data),
+      
+      .DEBUG(debug_master)                                         
+    );
+
+  aq_fifo u_aq_wfifo
+    (
+      .RST(FIFO_RST),
+      
+      .WRCLK(M_AXI_ACLK),
+      .WREN(rd_fifo_we),
+      .DI(rd_fifo_data),
+      .FULL(rd_fifo_full),
+      .AFULL(rd_fifo_afull),
+      .WRCOUNT(),
+      
+      .RDCLK(FIFO_RD_CLK),
+      .RDEN(FIFO_RD_EN), 
+      .DO(FIFO_RD_DO),
+      .EMPTY(FIFO_RD_EMPTY),
+      .AEMPTY(),
+      .RDCOUNT()
+    );
+  always @(posedge M_AXI_ACLK or posedge FIFO_RST) begin
+    if(FIFO_RST) begin
+      rd_fifo_wrcnt <= 32'd0;
+    end else begin
+      if(rd_fifo_we) begin
+        rd_fifo_wrcnt <= rd_fifo_wrcnt +32'd1;
+      end
+    end
+  end
+  always @(posedge FIFO_RD_CLK or posedge FIFO_RST) begin
+    if(FIFO_RST) begin
+      rd_fifo_rdcnt <= 32'd0;
+    end else begin
+      if(FIFO_RD_EN) begin
+        rd_fifo_rdcnt <= rd_fifo_rdcnt +32'd1;
+      end
+    end
+  end
+
+  aq_fifo u_aq_rfifo
+    (
+      .RST(FIFO_RST),
+      
+      .WRCLK(FIFO_WR_CLK),
+      .WREN(FIFO_WR_EN),
+      .DI(FIFO_WR_DI),
+      .FULL(FIFO_WR_FULL),
+      .AFULL(),
+      .WRCOUNT(),
+      
+      .RDCLK(M_AXI_ACLK),
+      .RDEN(wr_fifo_re), 
+      .DO(wr_fifo_data),
+      .EMPTY(wr_fifo_empty),
+      .AEMPTY(wr_fifo_aempty),
+      .RDCOUNT()
+    );
+  always @(posedge FIFO_WR_CLK or posedge FIFO_RST) begin
+    if(FIFO_RST) begin
+      wr_fifo_wrcnt <= 32'd0;
+    end else begin
+      if(FIFO_WR_EN) begin
+        wr_fifo_wrcnt <= wr_fifo_wrcnt +32'd1;
+      end
+    end
+  end
+  always @(posedge M_AXI_ACLK or posedge FIFO_RST) begin
+    if(FIFO_RST) begin
+      wr_fifo_rdcnt <= 32'd0;
+    end else begin
+      if(wr_fifo_re) begin
+        wr_fifo_rdcnt <= wr_fifo_rdcnt +32'd1;
+      end
+    end
+  end
+
+  aq_axi_fifo_ctl u_aq_axi_fifo_ctl
+    (
+      .RST_N(ARESETN),
+      .CLK(S_AXI_ACLK),
+      
+      .LOCAL_CS(local_cs),
+      .LOCAL_RNW(local_rnw),
+      .LOCAL_ACK(local_ack),
+      .LOCAL_ADDR(local_addr),
+      .LOCAL_BE(local_be),
+      .LOCAL_WDATA(local_wdata),
+      .LOCAL_RDATA(local_rdata),
+
+      .CMD_CLK(M_AXI_ACLK),
+      
+      .WR_START(wr_start),
+      .WR_ADRS(wr_adrs),
+      .WR_COUNT(wr_len),
+      .WR_READY(wr_ready),
+      .WR_FIFO_EMPTY(wr_fifo_empty),
+      .WR_FIFO_AEMPTY(wr_fifo_aempty),
+      .WR_FIFO_FULL(FIFO_RD_FULL),
+      .WR_FIFO_AFULL(1'b0),
+
+      .RD_START(rd_start),
+      .RD_ADRS(rd_adrs),
+      .RD_COUNT(rd_len),
+      .RD_READY(rd_ready),
+      .RD_FIFO_EMPTY(FIFO_WR_EMPTY),
+      .RD_FIFO_AEMPTY(1'b0),
+      .RD_FIFO_FULL(rd_fifo_full),
+      .RD_FIFO_AFULL(rd_fifo_afull),
+      
+      .MASTER_STATUS(debug_master),
+      .FIFO_STATUS0(rd_fifo_wrcnt),
+      .FIFO_STATUS1(rd_fifo_rdcnt),
+      .FIFO_STATUS2(wr_fifo_wrcnt),
+      .FIFO_STATUS3(wr_fifo_rdcnt),
+
+      .FIFO_RST(FIFO_RST),
+      
+      .DEBUG(debug_ctl)
+    );
+
+    assign DEBUG[31:0] = {32'd0};
+endmodule
+ 

aquaxis_IPCORE/aq_axi_fifo/aq_axi_fifo.srcs/sources/aq_axi_fifo_ctl.v

@@ -0,0 +1,269 @@
+/*
+ * Copyright (C)2014-2015 AQUAXIS TECHNOLOGY.
+ *  Don't remove this header. 
+ * When you use this source, there is a need to inherit this header.
+ *
+ * License
+ *  For no commercial -
+ *   License:     The Open Software License 3.0
+ *   License URI: http://www.opensource.org/licenses/OSL-3.0
+ *
+ *  For commmercial -
+ *   License:     AQUAXIS License 1.0
+ *   License URI: http://www.aquaxis.com/licenses
+ *
+ * For further information please contact.
+ *	URI:    http://www.aquaxis.com/
+ *	E-Mail: info(at)aquaxis.com
+ */
+module aq_axi_fifo_ctl(
+  input         RST_N,
+  input         CLK,
+
+  input         LOCAL_CS,
+  input         LOCAL_RNW,
+  output        LOCAL_ACK,
+  input [31:0]  LOCAL_ADDR,
+  input [3:0]   LOCAL_BE,
+  input [31:0]  LOCAL_WDATA,
+  output [31:0] LOCAL_RDATA,
+
+  input         CMD_CLK, 
+  
+  output        WR_START,
+  output [31:0] WR_ADRS,
+  output [31:0] WR_COUNT,
+  input         WR_READY,
+  input         WR_FIFO_EMPTY,
+  input         WR_FIFO_AEMPTY,
+  input         WR_FIFO_FULL,
+  input         WR_FIFO_AFULL,
+
+  output        RD_START,
+  output [31:0] RD_ADRS,
+  output [31:0] RD_COUNT,
+  input         RD_READY,
+  input         RD_FIFO_EMPTY,
+  input         RD_FIFO_AEMPTY,
+  input         RD_FIFO_FULL,
+  input         RD_FIFO_AFULL,
+
+  input [31:0]  MASTER_STATUS,
+  input [31:0]  FIFO_STATUS0,
+  input [31:0]  FIFO_STATUS1,
+  input [31:0]  FIFO_STATUS2,
+  input [31:0]  FIFO_STATUS3,
+
+  output        FIFO_RST,
+
+  output [31:0] DEBUG 
+);
+
+  localparam A_WR_START      = 8'h00;
+  localparam A_WR_ADRS       = 8'h04;
+  localparam A_WR_COUNT      = 8'h08;
+  localparam A_RD_START      = 8'h0C;
+  localparam A_RD_ADRS       = 8'h10;
+  localparam A_RD_COUNT      = 8'h14;
+  localparam A_MASTER_STATUS = 8'h18;
+  localparam A_TESTDATA      = 8'h1C;
+  localparam A_FIFORST       = 8'h20;
+  localparam A_DEBUG         = 8'h24;
+  localparam A_FIFO_STATUS0  = 8'h28;
+  localparam A_FIFO_STATUS1  = 8'h2C;
+  localparam A_FIFO_STATUS2  = 8'h30;
+  localparam A_FIFO_STATUS3  = 8'h34;
+
+  wire        wr_ena, rd_ena, wr_ack;
+  reg         rd_ack;
+   
+  reg         reg_wrreq_clk;
+  reg [1:0]   req_wrack_clk;
+  reg [2:0]   reg_wrreq_cmd_clk;
+
+  reg         reg_rdreq_clk;
+  reg [1:0]   req_rdack_clk;
+  reg [2:0]   reg_rdreq_cmd_clk;
+
+  reg [31:0]  reg_wr_adrs, reg_rd_adrs;
+  reg [31:0]  reg_wr_count, reg_rd_count;
+  reg [31:0]  reg_testdata;
+
+  reg [31:0]  reg_rdata;
+
+  reg         reg_fifo_rst;
+
+  reg [7:0]   reg_rdreq_count;
+
+  assign wr_ena = (LOCAL_CS & ~LOCAL_RNW)?1'b1:1'b0;
+  assign rd_ena = (LOCAL_CS &  LOCAL_RNW)?1'b1:1'b0;
+  assign wr_ack = wr_ena;
+
+  // Write Register
+  always @(posedge CLK or negedge RST_N) begin
+    if(!RST_N) begin
+      reg_wr_adrs[31:0] <= 32'd0;
+      reg_wr_count[31:0] <= 32'd0;
+      reg_rd_adrs[31:0] <= 32'd0;
+      reg_rd_count[31:0] <= 32'd0;
+      reg_fifo_rst <= 1'b0;
+    end else begin
+      if(wr_ena) begin
+        case(LOCAL_ADDR[7:0] & 8'hFC)
+          A_WR_START: begin
+          end
+          A_WR_ADRS: begin
+            reg_wr_adrs[31:0] <= LOCAL_WDATA[31:0];
+          end
+          A_WR_COUNT: begin
+            reg_wr_count[31:0] <= LOCAL_WDATA[31:0];
+          end
+          A_RD_START: begin
+          end
+            A_RD_ADRS: begin
+            reg_rd_adrs[31:0] <= LOCAL_WDATA[31:0];
+          end
+          A_RD_COUNT: begin
+            reg_rd_count[31:0] <= LOCAL_WDATA[31:0];
+          end
+          A_MASTER_STATUS: begin
+          end
+          A_TESTDATA: begin
+            reg_testdata[31:0] <= LOCAL_WDATA[31:0];
+          end
+          A_FIFORST: begin
+            reg_fifo_rst <= LOCAL_WDATA[0];
+          end
+          default: begin
+          end
+        endcase
+      end
+    end
+  end
+
+  // Read Register
+  always @(posedge CLK or negedge RST_N) begin
+    if(!RST_N) begin
+      reg_rdata[31:0] <= 32'd0;
+      rd_ack <= 1'b0;
+    end else begin
+      rd_ack <= rd_ena;
+      if(rd_ena) begin
+        case(LOCAL_ADDR[7:0] & 8'hFC)
+          A_WR_START: begin
+            reg_rdata[31:0] <= {12'd0, WR_FIFO_AEMPTY, WR_FIFO_EMPTY, WR_FIFO_AFULL, WR_FIFO_FULL, 7'd0, WR_READY, 7'd0, reg_wrreq_clk};
+          end
+          A_WR_ADRS: begin
+            reg_rdata[31:0] <= reg_wr_adrs[31:0];
+          end
+          A_WR_COUNT: begin
+            reg_rdata[31:0] <= reg_wr_count[31:0];
+          end
+          A_RD_START: begin
+            reg_rdata[31:0] <= {12'd0, RD_FIFO_AEMPTY, RD_FIFO_EMPTY, RD_FIFO_AFULL, RD_FIFO_FULL, 7'd0, RD_READY, 7'd0, reg_rdreq_clk};
+          end
+          A_RD_ADRS: begin
+            reg_rdata[31:0] <= reg_rd_adrs[31:0];
+          end
+          A_RD_COUNT: begin
+            reg_rdata[31:0] <= reg_rd_count[31:0];
+          end
+          A_MASTER_STATUS: begin
+            reg_rdata[31:0] <= MASTER_STATUS;
+          end
+          A_TESTDATA: begin
+            reg_rdata[31:0] <= reg_testdata[31:0];
+          end
+          A_FIFORST: begin
+            reg_rdata[31:0] <= {31'd0, reg_fifo_rst};
+          end
+          A_DEBUG: begin
+            reg_rdata[31:0] <= {24'd0, reg_rdreq_count};
+          end
+          A_FIFO_STATUS0: begin
+            reg_rdata[31:0] <= FIFO_STATUS0;
+          end
+          A_FIFO_STATUS1: begin
+            reg_rdata[31:0] <= FIFO_STATUS1;
+          end
+          A_FIFO_STATUS2: begin
+            reg_rdata[31:0] <= FIFO_STATUS2;
+          end
+          A_FIFO_STATUS3: begin
+            reg_rdata[31:0] <= FIFO_STATUS3;
+          end
+          default: begin
+            reg_rdata[31:0] <= 32'd0;
+          end
+        endcase
+      end else begin
+        reg_rdata[31:0] <= 32'd0;
+      end
+    end
+  end
+   
+  assign LOCAL_ACK         = (wr_ack | rd_ack);
+  assign LOCAL_RDATA[31:0] = reg_rdata[31:0];
+
+  // Request Sending(1shot)
+  always @(posedge CLK or negedge RST_N) begin
+    if(!RST_N) begin
+      reg_wrreq_clk <= 1'b0;
+      req_wrack_clk[1:0] <= 2'd0;
+    end else begin
+      if(req_wrack_clk[1]) begin
+        reg_wrreq_clk <= 1'b0;
+      end else if((wr_ena && (LOCAL_ADDR[7:0] == A_WR_START[7:0])) &&
+                  (WR_READY)) begin
+        reg_wrreq_clk <= 1'b1;
+      end
+      req_wrack_clk[1:0] <= {req_wrack_clk[0], reg_wrreq_cmd_clk[2]};
+    end
+  end
+
+  always @(posedge CMD_CLK or negedge RST_N) begin
+    if(!RST_N) begin
+      reg_wrreq_cmd_clk[2:0] <= 3'd0;
+    end else begin
+      reg_wrreq_cmd_clk[2:0] <= {reg_wrreq_cmd_clk[1:0], reg_wrreq_clk};
+    end
+  end
+
+  always @(posedge CLK or negedge RST_N) begin
+    if(!RST_N) begin
+      reg_rdreq_clk <= 1'b0;
+      req_rdack_clk[1:0] <= 2'd0;
+      reg_rdreq_count[7:0] <= 8'd0;
+    end else begin
+      if(req_rdack_clk[1]) begin
+        reg_rdreq_clk <= 1'b0;
+      end else if((wr_ena && (LOCAL_ADDR[7:0] == A_RD_START[7:0])) &&
+                  (RD_READY)) begin
+        reg_rdreq_clk <= 1'b1;
+        reg_rdreq_count[7:0] <= reg_rdreq_count[7:0] + 8'd1;
+      end
+      req_rdack_clk[1:0] <= {req_rdack_clk[0], reg_rdreq_cmd_clk[2]};
+    end
+  end
+
+  always @(posedge CMD_CLK or negedge RST_N) begin
+    if(!RST_N) begin
+      reg_rdreq_cmd_clk[2:0] <= 3'd0;
+    end else begin
+      reg_rdreq_cmd_clk[2:0] <= {reg_rdreq_cmd_clk[1:0], reg_rdreq_clk};
+    end
+  end
+
+  assign WR_START       = (reg_wrreq_cmd_clk[2:1] == 2'b01)?1'b1:1'b0;
+  assign WR_ADRS[31:0]  = reg_wr_adrs[31:0];
+  assign WR_COUNT[31:0] = reg_wr_count[31:0];
+  assign RD_START       = (reg_rdreq_cmd_clk[2:1] == 2'b01)?1'b1:1'b0;
+  assign RD_ADRS[31:0]  = reg_rd_adrs[31:0];
+  assign RD_COUNT[31:0] = reg_rd_count[31:0];
+
+  assign FIFO_RST       = reg_fifo_rst;
+
+  assign DEBUG[31:0]    = {24'd0, rd_ack, rd_ena, LOCAL_RNW, LOCAL_CS};
+
+endmodule
+

aquaxis_IPCORE/aq_axi_fifo/aq_axi_fifo.srcs/sources/aq_axi_lite_slave.v

@@ -0,0 +1,176 @@
+/*
+ * Copyright (C)2014-2015 AQUAXIS TECHNOLOGY.
+ *  Don't remove this header. 
+ * When you use this source, there is a need to inherit this header.
+ *
+ * License
+ *  For no commercial -
+ *   License:     The Open Software License 3.0
+ *   License URI: http://www.opensource.org/licenses/OSL-3.0
+ *
+ *  For commmercial -
+ *   License:     AQUAXIS License 1.0
+ *   License URI: http://www.aquaxis.com/licenses
+ *
+ * For further information please contact.
+ *	URI:    http://www.aquaxis.com/
+ *	E-Mail: info(at)aquaxis.com
+ */
+module aq_axi_lite_slave
+  #(
+    parameter     C_BASEADRS  = 32'h0000_0000,
+    parameter     C_ADRSWIDTH = 16
+    )
+  (
+    // AXI4 Lite Interface
+    input         ARESETN,
+    input         ACLK,
+    
+    // Write Address Channel
+    input [31:0]  S_AXI_AWADDR,
+    input [3:0]   S_AXI_AWCACHE,  // 4'b0011
+    input [2:0]   S_AXI_AWPROT,   // 3'b000
+    input         S_AXI_AWVALID,
+    output        S_AXI_AWREADY, 
+        
+    // Write Data Channel
+    input [31:0]  S_AXI_WDATA,
+    input [3:0]   S_AXI_WSTRB,
+    input         S_AXI_WVALID,
+    output        S_AXI_WREADY,
+        
+    // Write Response Channel
+    output        S_AXI_BVALID,
+    input         S_AXI_BREADY,
+    output [1:0]  S_AXI_BRESP,
+
+    // Read Address Channel
+    input [31:0]  S_AXI_ARADDR,
+    input [3:0]   S_AXI_ARCACHE,  // 4'b0011
+    input [2:0]   S_AXI_ARPROT,   // 3'b000
+    input         S_AXI_ARVALID,
+    output        S_AXI_ARREADY,
+
+    // Read Data Channel
+    output [31:0] S_AXI_RDATA,
+    output [1:0]  S_AXI_RRESP,
+    output        S_AXI_RVALID,
+    input         S_AXI_RREADY,
+    
+    // Local Interface
+    output        LOCAL_CS,
+    output        LOCAL_RNW,
+    input         LOCAL_ACK,
+    output [31:0] LOCAL_ADDR,
+    output [3:0]  LOCAL_BE,
+    output [31:0] LOCAL_WDATA,
+    input [31:0]  LOCAL_RDATA,
+    
+    output [31:0] DEBUG
+  );
+
+/*
+CACHE[3:0]
+WA RA C  B 
+0  0  0  0 Noncacheable and nonbufferable
+0  0  0  1 Bufferable only
+0  0  1  0 Cacheable, but do not allocate
+0  0  1  1 Cacheable and Bufferable, but do not allocate
+0  1  1  0 Cacheable write-through, allocate on reads only
+0  1  1  1 Cacheable write-back, allocate on reads only
+1  0  1  0 Cacheable write-through, allocate on write only
+1  0  1  1 Cacheable write-back, allocate on writes only
+1  1  1  0 Cacheable write-through, allocate on both reads and writes
+1  1  1  1 Cacheable write-back, allocate on both reads and writes
+
+PROR
+[2]:0:Data Access
+    1:Instruction Access
+[1]:0:Secure Access
+    1:NoSecure Access
+[0]:0:Privileged Access
+    1:Normal Access
+
+RESP
+00: OK
+01: EXOK
+10: SLVERR
+11: DECERR
+*/
+
+  localparam S_IDLE   = 2'd0;
+  localparam S_WRITE  = 2'd1;
+  localparam S_WRITE2 = 2'd2;
+  localparam S_READ   = 2'd3;
+
+  reg [1:0]   state;
+  reg         reg_rnw;
+  reg [31:0]  reg_addr, reg_wdata;
+  reg [3:0]   reg_be;
+   
+  always @( posedge ACLK or negedge ARESETN ) begin
+    if( !ARESETN ) begin
+      state     <= S_IDLE;
+      reg_rnw   <= 1'b0;
+      reg_addr  <= 32'd0;
+      reg_wdata <= 32'd0;
+      reg_be    <= 4'd0;
+    end else begin
+      case( state )
+        S_IDLE: begin
+          if( S_AXI_AWVALID && ( S_AXI_AWADDR[31:(32 - C_ADRSWIDTH)] == C_BASEADRS[31:(32 - C_ADRSWIDTH)] ) ) begin
+            reg_rnw   <= 1'b0;
+            reg_addr  <= S_AXI_AWADDR;
+            state     <= S_WRITE;
+          end else if( S_AXI_ARVALID && (S_AXI_ARADDR[31:(32 - C_ADRSWIDTH)] == C_BASEADRS[31:(32 - C_ADRSWIDTH)]) ) begin
+            reg_rnw   <= 1'b1;
+            reg_addr  <= S_AXI_ARADDR;
+            state     <= S_READ;
+          end
+        end
+        S_WRITE: begin
+          if( S_AXI_WVALID ) begin
+            state     <= S_WRITE2;
+            reg_wdata <= S_AXI_WDATA;
+            reg_be    <= S_AXI_WSTRB;
+          end
+        end
+        S_WRITE2: begin
+          if( LOCAL_ACK & S_AXI_BREADY ) begin
+            state     <= S_IDLE;
+          end
+        end
+        S_READ: begin
+          if( LOCAL_ACK & S_AXI_RREADY ) begin
+            state     <= S_IDLE;
+          end
+        end
+        default: begin
+          state        <= S_IDLE;
+        end
+      endcase
+    end
+  end
+   
+  // Local Interface
+  assign LOCAL_CS       = (( state == S_WRITE2 )?1'b1:1'b0) | (( state == S_READ )?1'b1:1'b0) | 1'b0;
+  assign LOCAL_RNW      = reg_rnw;
+  assign LOCAL_ADDR     = reg_addr;
+  assign LOCAL_BE       = reg_be;
+  assign LOCAL_WDATA    = reg_wdata;
+   
+  // Write Channel
+  assign S_AXI_AWREADY  = ( state == S_WRITE )?S_AXI_AWVALID:1'b0;
+  assign S_AXI_WREADY   = ( state == S_WRITE )?S_AXI_WVALID:1'b0;
+  assign S_AXI_BVALID   = ( state == S_WRITE2 )?LOCAL_ACK:1'b0;
+  assign S_AXI_BRESP    = 2'b00;
+   
+  // Read Channel
+  assign S_AXI_ARREADY  = ( state == S_READ )?S_AXI_ARVALID:1'b0;
+  assign S_AXI_RVALID   = ( state == S_READ )?LOCAL_ACK:1'b0;
+  assign S_AXI_RRESP    = 2'b00;
+  assign S_AXI_RDATA    = ( state == S_READ )?LOCAL_RDATA:32'd0;
+
+  // Debug
+  assign DEBUG[31:0]    = {24'd0, 1'd0, S_AXI_RVALID, S_AXI_ARREADY, LOCAL_ACK, LOCAL_RNW, LOCAL_CS, state[1:0]};
+endmodule

aquaxis_IPCORE/aq_axi_fifo/aq_axi_fifo.srcs/sources/aq_axi_master.v

@@ -0,0 +1,366 @@
+/*
+ * Copyright (C)2014-2015 AQUAXIS TECHNOLOGY.
+ *  Don't remove this header. 
+ * When you use this source, there is a need to inherit this header.
+ *
+ * License
+ *  For no commercial -
+ *   License:     The Open Software License 3.0
+ *   License URI: http://www.opensource.org/licenses/OSL-3.0
+ *
+ *  For commmercial -
+ *   License:     AQUAXIS License 1.0
+ *   License URI: http://www.aquaxis.com/licenses
+ *
+ * For further information please contact.
+ *	URI:    http://www.aquaxis.com/
+ *	E-Mail: info(at)aquaxis.com
+ */
+module aq_axi_master(
+  // Reset, Clock
+  input           ARESETN,
+  input           ACLK,
+
+  // Master Write Address
+  output [0:0]  M_AXI_AWID,
+  output [31:0] M_AXI_AWADDR,
+  output [7:0]  M_AXI_AWLEN,    // Burst Length: 0-255
+  output [2:0]  M_AXI_AWSIZE,   // Burst Size: Fixed 2'b011
+  output [1:0]  M_AXI_AWBURST,  // Burst Type: Fixed 2'b01(Incremental Burst)
+  output        M_AXI_AWLOCK,   // Lock: Fixed 2'b00
+  output [3:0]  M_AXI_AWCACHE,  // Cache: Fiex 2'b0011
+  output [2:0]  M_AXI_AWPROT,   // Protect: Fixed 2'b000
+  output [3:0]  M_AXI_AWQOS,    // QoS: Fixed 2'b0000
+  output [0:0]  M_AXI_AWUSER,   // User: Fixed 32'd0
+  output        M_AXI_AWVALID,
+  input         M_AXI_AWREADY,
+
+  // Master Write Data
+  output [63:0] M_AXI_WDATA,
+  output [7:0]  M_AXI_WSTRB,
+  output        M_AXI_WLAST,
+  output [0:0]  M_AXI_WUSER,
+  output        M_AXI_WVALID,
+  input         M_AXI_WREADY,
+
+  // Master Write Response
+  input [0:0]   M_AXI_BID,
+  input [1:0]   M_AXI_BRESP,
+  input [0:0]   M_AXI_BUSER,
+  input         M_AXI_BVALID,
+  output        M_AXI_BREADY,
+    
+  // Master Read Address
+  output [0:0]  M_AXI_ARID,
+  output [31:0] M_AXI_ARADDR,
+  output [7:0]  M_AXI_ARLEN,
+  output [2:0]  M_AXI_ARSIZE,
+  output [1:0]  M_AXI_ARBURST,
+  output [1:0]  M_AXI_ARLOCK,
+  output [3:0]  M_AXI_ARCACHE,
+  output [2:0]  M_AXI_ARPROT,
+  output [3:0]  M_AXI_ARQOS,
+  output [0:0]  M_AXI_ARUSER,
+  output        M_AXI_ARVALID,
+  input         M_AXI_ARREADY,
+    
+  // Master Read Data 
+  input [0:0]   M_AXI_RID,
+  input [63:0]  M_AXI_RDATA,
+  input [1:0]   M_AXI_RRESP,
+  input         M_AXI_RLAST,
+  input [0:0]   M_AXI_RUSER,
+  input         M_AXI_RVALID,
+  output        M_AXI_RREADY,
+        
+  // Local Bus
+  input         MASTER_RST,
+  
+  input         WR_START,
+  input [31:0]  WR_ADRS,
+  input [31:0]  WR_LEN, 
+  output        WR_READY,
+  output        WR_FIFO_RE,
+  input         WR_FIFO_EMPTY,
+  input         WR_FIFO_AEMPTY,
+  input [63:0]  WR_FIFO_DATA,
+
+  input         RD_START,
+  input [31:0]  RD_ADRS,
+  input [31:0]  RD_LEN, 
+  output        RD_READY,
+  output        RD_FIFO_WE,
+  input         RD_FIFO_FULL,
+  input         RD_FIFO_AFULL,
+  output [63:0] RD_FIFO_DATA,
+
+  output [31:0] DEBUG
+);
+
+  localparam S_WR_IDLE  = 3'd0;
+  localparam S_WA_WAIT  = 3'd1;
+  localparam S_WA_START = 3'd2;
+  localparam S_WD_WAIT  = 3'd3;
+  localparam S_WD_PROC  = 3'd4;
+  localparam S_WR_WAIT  = 3'd5;
+
+  reg [2:0]   wr_state;
+  reg [31:0]  reg_wr_adrs;
+  reg [31:0]  reg_wr_len;
+  reg         reg_awvalid, reg_wvalid, reg_w_last;
+  reg [7:0]   reg_w_len;
+  reg [7:0]   reg_w_stb;
+  reg [1:0]   reg_wr_status;
+  reg [3:0]   reg_w_count, reg_r_count;
+
+  reg [7:0]   rd_chkdata, wr_chkdata;
+  reg [1:0]   resp;
+
+  // Write State
+  always @(posedge ACLK or negedge ARESETN) begin
+    if(!ARESETN) begin
+      wr_state            <= S_WR_IDLE;
+      reg_wr_adrs[31:0]   <= 32'd0;
+      reg_wr_len[31:0]    <= 32'd0;
+      reg_awvalid         <= 1'b0;
+      reg_wvalid          <= 1'b0;
+      reg_w_last          <= 1'b0;
+      reg_w_len[7:0]      <= 8'd0;
+      reg_w_stb[7:0]      <= 8'd0;
+      reg_wr_status[1:0]  <= 2'd0;
+      reg_w_count[3:0]    <= 4'd0;
+      reg_r_count[3:0]  <= 4'd0;
+      wr_chkdata          <= 8'd0;
+        rd_chkdata <= 8'd0;
+      resp <= 2'd0;
+  end else begin
+    if(MASTER_RST) begin
+      wr_state <= S_WR_IDLE;
+    end else begin
+      case(wr_state)
+        S_WR_IDLE: begin
+          if(WR_START) begin
+            wr_state          <= S_WA_WAIT;
+            reg_wr_adrs[31:0] <= WR_ADRS[31:0];
+            reg_wr_len[31:0]  <= WR_LEN[31:0] -32'd1;
+          end
+          reg_awvalid         <= 1'b0;
+          reg_wvalid          <= 1'b0;
+          reg_w_last          <= 1'b0;
+          reg_w_len[7:0]      <= 8'd0;
+          reg_w_stb[7:0]      <= 8'd0;
+          reg_wr_status[1:0]  <= 2'd0;
+        end
+        S_WA_WAIT: begin
+          if(!WR_FIFO_AEMPTY | (reg_wr_len[31:11] == 21'd0)) begin
+            wr_state          <= S_WA_START;
+          end
+        end
+        S_WA_START: begin
+          wr_state            <= S_WD_WAIT;
+          reg_awvalid         <= 1'b1;
+          reg_wr_len[31:11]    <= reg_wr_len[31:11] - 21'd1;
+          if(reg_wr_len[31:11] != 21'd0) begin
+            reg_w_len[7:0]  <= 8'hFF;
+            reg_w_last      <= 1'b0;
+            reg_w_stb[7:0]  <= 8'hFF;
+          end else begin
+            reg_w_len[7:0]  <= reg_wr_len[10:3];
+            reg_w_last      <= 1'b1;
+            reg_w_stb[7:0]  <= 8'hFF;
+/*
+            case(reg_wr_len[2:0]) begin
+              case 3'd0: reg_w_stb[7:0]  <= 8'b0000_0000;
+              case 3'd1: reg_w_stb[7:0]  <= 8'b0000_0001;
+              case 3'd2: reg_w_stb[7:0]  <= 8'b0000_0011;
+              case 3'd3: reg_w_stb[7:0]  <= 8'b0000_0111;
+              case 3'd4: reg_w_stb[7:0]  <= 8'b0000_1111;
+              case 3'd5: reg_w_stb[7:0]  <= 8'b0001_1111;
+              case 3'd6: reg_w_stb[7:0]  <= 8'b0011_1111;
+              case 3'd7: reg_w_stb[7:0]  <= 8'b0111_1111;
+              default:   reg_w_stb[7:0]  <= 8'b1111_1111;
+            endcase
+*/
+          end
+        end
+        S_WD_WAIT: begin
+          if(M_AXI_AWREADY) begin
+            wr_state        <= S_WD_PROC;
+            reg_awvalid     <= 1'b0;
+            reg_wvalid      <= 1'b1;
+          end
+        end
+        S_WD_PROC: begin
+          if(M_AXI_WREADY & ~WR_FIFO_EMPTY) begin
+            if(reg_w_len[7:0] == 8'd0) begin
+              wr_state        <= S_WR_WAIT;
+              reg_wvalid      <= 1'b0;
+              reg_w_stb[7:0]  <= 8'h00;
+            end else begin
+              reg_w_len[7:0]  <= reg_w_len[7:0] -8'd1;
+            end
+          end
+        end
+        S_WR_WAIT: begin
+          if(M_AXI_BVALID) begin
+            reg_wr_status[1:0]  <= reg_wr_status[1:0] | M_AXI_BRESP[1:0];
+            if(reg_w_last) begin
+              wr_state          <= S_WR_IDLE;
+            end else begin
+              wr_state          <= S_WA_WAIT;
+              reg_wr_adrs[31:0] <= reg_wr_adrs[31:0] + 32'd2048;
+            end
+          end
+        end
+        default: begin
+          wr_state <= S_WR_IDLE;
+        end
+      endcase
+/*
+      if(WR_FIFO_RE) begin
+        reg_w_count[3:0]  <= reg_w_count[3:0] + 4'd1;
+      end
+      if(RD_FIFO_WE)begin
+        reg_r_count[3:0]  <= reg_r_count[3:0] + 4'd1;
+      end
+      if(M_AXI_AWREADY & M_AXI_AWVALID) begin
+        wr_chkdata <= 8'hEE;
+      end else if(M_AXI_WSTRB[7] & M_AXI_WVALID) begin
+        wr_chkdata <= WR_FIFO_DATA[63:56];
+      end
+      if(M_AXI_AWREADY & M_AXI_AWVALID) begin
+        rd_chkdata <= 8'hDD;
+      end else if(M_AXI_WSTRB[7] & M_AXI_WREADY) begin
+        rd_chkdata <= WR_FIFO_DATA[63:56];
+      end
+      if(M_AXI_BVALID & M_AXI_BREADY) begin
+        resp <= M_AXI_BRESP;
+      end
+*/
+      end
+    end
+  end
+   
+  assign M_AXI_AWID         = 1'b0;
+  assign M_AXI_AWADDR[31:0] = reg_wr_adrs[31:0];
+  assign M_AXI_AWLEN[7:0]   = reg_w_len[7:0];
+  assign M_AXI_AWSIZE[2:0]  = 2'b011;
+  assign M_AXI_AWBURST[1:0] = 2'b01;
+  assign M_AXI_AWLOCK       = 1'b0;
+  assign M_AXI_AWCACHE[3:0] = 4'b0011;
+  assign M_AXI_AWPROT[2:0]  = 3'b000;
+  assign M_AXI_AWQOS[3:0]   = 4'b0000;
+  assign M_AXI_AWUSER[0]    = 1'b1;
+  assign M_AXI_AWVALID      = reg_awvalid;
+
+  assign M_AXI_WDATA[63:0]  = WR_FIFO_DATA[63:0];
+//  assign M_AXI_WSTRB[7:0]   = (reg_w_len[7:0] == 8'd0)?reg_w_stb[7:0]:8'hFF;
+//  assign M_AXI_WSTRB[7:0]   = (wr_state == S_WD_PROC)?8'hFF:8'h00;
+  assign M_AXI_WSTRB[7:0]   = (reg_wvalid & ~WR_FIFO_EMPTY)?8'hFF:8'h00;
+  assign M_AXI_WLAST        = (reg_w_len[7:0] == 8'd0)?1'b1:1'b0;
+  assign M_AXI_WUSER        = 1;
+  assign M_AXI_WVALID       = reg_wvalid & ~WR_FIFO_EMPTY;
+//  assign M_AXI_WVALID       = (wr_state == S_WD_PROC)?1'b1:1'b0;
+
+  assign M_AXI_BREADY       = M_AXI_BVALID;
+
+  assign WR_READY           = (wr_state == S_WR_IDLE)?1'b1:1'b0;
+  assign WR_FIFO_RE         = reg_wvalid & ~WR_FIFO_EMPTY & M_AXI_WREADY;
+//  assign WR_FIFO_RE         = (wr_state == S_WD_PROC)?M_AXI_WREADY:1'b0;
+
+  localparam S_RD_IDLE  = 3'd0;
+  localparam S_RA_WAIT  = 3'd1;
+  localparam S_RA_START = 3'd2;
+  localparam S_RD_WAIT  = 3'd3;
+  localparam S_RD_PROC  = 3'd4;
+   
+  reg [2:0]   rd_state;
+  reg [31:0]  reg_rd_adrs;
+  reg [31:0]  reg_rd_len;
+  reg         reg_arvalid, reg_r_last;
+  reg [7:0]   reg_r_len;
+   
+  // Read State
+  always @(posedge ACLK or negedge ARESETN) begin
+    if(!ARESETN) begin
+      rd_state          <= S_RD_IDLE;
+      reg_rd_adrs[31:0] <= 32'd0;
+      reg_rd_len[31:0]  <= 32'd0;
+      reg_arvalid       <= 1'b0;
+      reg_r_len[7:0]    <= 8'd0;
+    end else begin
+      case(rd_state)
+        S_RD_IDLE: begin
+          if(RD_START) begin
+            rd_state          <= S_RA_WAIT;
+            reg_rd_adrs[31:0] <= RD_ADRS[31:0];
+            reg_rd_len[31:0]  <= RD_LEN[31:0] -32'd1;
+          end
+          reg_arvalid     <= 1'b0;
+          reg_r_len[7:0]  <= 8'd0;
+        end
+        S_RA_WAIT: begin
+          if(~RD_FIFO_AFULL) begin
+            rd_state          <= S_RA_START;
+          end
+        end
+        S_RA_START: begin
+          rd_state          <= S_RD_WAIT;
+          reg_arvalid       <= 1'b1;
+          reg_rd_len[31:11] <= reg_rd_len[31:11] -21'd1;
+          if(reg_rd_len[31:11] != 21'd0) begin
+            reg_r_last      <= 1'b0;
+            reg_r_len[7:0]  <= 8'd255;
+          end else begin
+            reg_r_last      <= 1'b1;
+            reg_r_len[7:0]  <= reg_rd_len[10:3];
+          end
+        end
+        S_RD_WAIT: begin
+          if(M_AXI_ARREADY) begin
+            rd_state        <= S_RD_PROC;
+            reg_arvalid     <= 1'b0;
+          end
+        end
+        S_RD_PROC: begin
+          if(M_AXI_RVALID) begin
+            if(M_AXI_RLAST) begin
+              if(reg_r_last) begin
+                rd_state          <= S_RD_IDLE;
+              end else begin
+                rd_state          <= S_RA_WAIT;
+                reg_rd_adrs[31:0] <= reg_rd_adrs[31:0] + 32'd2048;
+              end
+            end else begin
+              reg_r_len[7:0] <= reg_r_len[7:0] -8'd1;
+            end
+          end
+        end
+      endcase
+    end
+  end
+   
+  // Master Read Address
+  assign M_AXI_ARID         = 1'b0;
+  assign M_AXI_ARADDR[31:0] = reg_rd_adrs[31:0];
+  assign M_AXI_ARLEN[7:0]   = reg_r_len[7:0];
+  assign M_AXI_ARSIZE[2:0]  = 3'b011;
+  assign M_AXI_ARBURST[1:0] = 2'b01;
+  assign M_AXI_ARLOCK       = 1'b0;
+  assign M_AXI_ARCACHE[3:0] = 4'b0011;
+  assign M_AXI_ARPROT[2:0]  = 3'b000;
+  assign M_AXI_ARQOS[3:0]   = 4'b0000;
+  assign M_AXI_ARUSER[0]    = 1'b1;
+  assign M_AXI_ARVALID      = reg_arvalid;
+
+  assign M_AXI_RREADY       = M_AXI_RVALID & ~RD_FIFO_FULL;
+
+  assign RD_READY           = (rd_state == S_RD_IDLE)?1'b1:1'b0;
+  assign RD_FIFO_WE         = M_AXI_RVALID;
+  assign RD_FIFO_DATA[63:0] = M_AXI_RDATA[63:0];
+
+  assign DEBUG[31:0] = {reg_wr_len[31:8],
+                        1'd0, wr_state[2:0], 1'd0, rd_state[2:0]};
+   
+endmodule
+

aquaxis_IPCORE/aq_axi_fifo/aq_axi_fifo.srcs/sources/aq_fifo.v

@@ -0,0 +1,86 @@
+/*
+ * Copyright (C)2014-2015 AQUAXIS TECHNOLOGY.
+ *  Don't remove this header. 
+ * When you use this source, there is a need to inherit this header.
+ *
+ * License
+ *  For no commercial -
+ *   License:     The Open Software License 3.0
+ *   License URI: http://www.opensource.org/licenses/OSL-3.0
+ *
+ *  For commmercial -
+ *   License:     AQUAXIS License 1.0
+ *   License URI: http://www.aquaxis.com/licenses
+ *
+ * For further information please contact.
+ *	URI:    http://www.aquaxis.com/
+ *	E-Mail: info(at)aquaxis.com
+ */
+module aq_fifo(
+  input         RST,
+
+  input         WRCLK,
+  input         WREN,
+  input [63:0]  DI,
+  output        FULL,
+  output        AFULL,
+  output [12:0] WRCOUNT,
+
+  input         RDCLK,
+  input         RDEN, 
+  output [63:0] DO,
+  output        EMPTY,
+  output        AEMPTY,
+  output [12:0] RDCOUNT
+);
+
+FIFO36E1 
+  #(
+    .ALMOST_EMPTY_OFFSET      ( 13'd128      ),
+    .ALMOST_FULL_OFFSET       ( 13'd258      ),
+    .DATA_WIDTH               ( 72           ),
+    .DO_REG                   ( 1            ),
+    .EN_ECC_READ              ( "FALSE"      ),
+    .EN_ECC_WRITE             ( "FALSE"      ),
+    .EN_SYN                   ( "FALSE"      ),
+    .FIFO_MODE                ( "FIFO36_72"  ),
+    .FIRST_WORD_FALL_THROUGH  ( "TRUE"       ),
+    .INIT                     ( 72'h0        ),
+    .SIM_DEVICE               ( "7SERIES"    ),
+    .SRVAL                    ( 72'h0        )
+  )
+  u_FIFO(
+    .RST           ( RST      ),
+
+    .WRCLK         ( WRCLK    ),
+    .WREN          ( WREN     ),
+    .DI            ( DI       ),
+    .DIP           ( 8'h00    ),
+    .WRCOUNT       ( WRCOUNT  ),
+    .WRERR         (),
+    .FULL          ( FULL     ),
+    .ALMOSTFULL    ( AFULL    ),
+      
+    .RDCLK         ( RDCLK    ),
+    .RDEN          ( RDEN     ),
+    .DO            ( DO       ),
+    .DOP           (),
+    .RDCOUNT       ( RDCOUNT  ),
+    .RDERR         (),
+    .EMPTY         ( EMPTY    ),
+    .ALMOSTEMPTY   ( AEMPTY   ),
+      
+    .REGCE         ( 1'b1     ),
+    .RSTREG        ( RST      ),
+      
+    .ECCPARITY     (),
+      
+    .DBITERR       (),
+    .SBITERR       (),
+      
+    .INJECTDBITERR ( 1'b0     ),
+    .INJECTSBITERR ( 1'b0     )
+  );
+
+endmodule
+

aquaxis_IPCORE/aq_axi_fifo/aq_axi_fifo.srcs/xgui/aq_axi_fifo_v1_0.tcl

@@ -0,0 +1,37 @@
+# Definitional proc to organize widgets for parameters.
+proc init_gui { IPINST } {
+	set Page0 [ipgui::add_page $IPINST -name "Page 0" -layout vertical]
+	set Component_Name [ipgui::add_param $IPINST -parent $Page0 -name Component_Name]
+	set C_ADRSWIDTH [ipgui::add_param $IPINST -parent $Page0 -name C_ADRSWIDTH]
+	set C_BASEADRS [ipgui::add_param $IPINST -parent $Page0 -name C_BASEADRS]
+}
+
+proc update_PARAM_VALUE.C_ADRSWIDTH { PARAM_VALUE.C_ADRSWIDTH } {
+	# Procedure called to update C_ADRSWIDTH when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_ADRSWIDTH { PARAM_VALUE.C_ADRSWIDTH } {
+	# Procedure called to validate C_ADRSWIDTH
+	return true
+}
+
+proc update_PARAM_VALUE.C_BASEADRS { PARAM_VALUE.C_BASEADRS } {
+	# Procedure called to update C_BASEADRS when any of the dependent parameters in the arguments change
+}
+
+proc validate_PARAM_VALUE.C_BASEADRS { PARAM_VALUE.C_BASEADRS } {
+	# Procedure called to validate C_BASEADRS
+	return true
+}
+
+
+proc update_MODELPARAM_VALUE.C_BASEADRS { MODELPARAM_VALUE.C_BASEADRS PARAM_VALUE.C_BASEADRS } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_BASEADRS}] ${MODELPARAM_VALUE.C_BASEADRS}
+}
+
+proc update_MODELPARAM_VALUE.C_ADRSWIDTH { MODELPARAM_VALUE.C_ADRSWIDTH PARAM_VALUE.C_ADRSWIDTH } {
+	# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
+	set_property value [get_property value ${PARAM_VALUE.C_ADRSWIDTH}] ${MODELPARAM_VALUE.C_ADRSWIDTH}
+}
+

aquaxis_IPCORE/aq_axi_i2c/aq_axi_i2c.srcs/sources/aq_axi_i2c.v

@@ -0,0 +1,161 @@
+/*
+ * Copyright (C)2014-2015 AQUAXIS TECHNOLOGY.
+ *  Don't remove this header. 
+ * When you use this source, there is a need to inherit this header.
+ *
+ * License
+ *  For no commercial -
+ *   License:     The Open Software License 3.0
+ *   License URI: http://www.opensource.org/licenses/OSL-3.0
+ *
+ *  For commmercial -
+ *   License:     AQUAXIS License 1.0
+ *   License URI: http://www.aquaxis.com/licenses
+ *
+ * For further information please contact.
+ *	URI:    http://www.aquaxis.com/
+ *	E-Mail: info(at)aquaxis.com
+ */
+`timescale 1ns / 1ps
+module aq_axi_i2c(
+    input         ARESETN,
+
+    // --------------------------------------------------
+    // AXI4 Lite Interface
+    // --------------------------------------------------
+    input           S_AXI_ACLK,
+    
+    // Write Address Channel
+    input [15:0]  S_AXI_AWADDR,
+    input [3:0]   S_AXI_AWCACHE,  // 4'b0011
+    input [2:0]   S_AXI_AWPROT,   // 3'b000
+    input         S_AXI_AWVALID,
+    output        S_AXI_AWREADY, 
+        
+    // Write Data Channel
+    input [31:0]  S_AXI_WDATA,
+    input [3:0]   S_AXI_WSTRB,
+    input         S_AXI_WVALID,
+    output        S_AXI_WREADY,
+        
+    // Write Response Channel
+    output        S_AXI_BVALID,
+    input         S_AXI_BREADY,
+    output [1:0]  S_AXI_BRESP,
+    
+    // Read Address Channel
+    input [15:0]  S_AXI_ARADDR,
+    input [3:0]   S_AXI_ARCACHE,  // 4'b0011
+    input [2:0]   S_AXI_ARPROT,   // 3'b000
+    input         S_AXI_ARVALID,
+    output        S_AXI_ARREADY,
+    
+    // Read Data Channel
+    output [31:0] S_AXI_RDATA,
+    output [1:0]  S_AXI_RRESP,
+    output        S_AXI_RVALID,
+    input         S_AXI_RREADY,
+
+    // I2C
+    inout           I2C_SDA,
+    inout           I2C_SCL    
+    );
+
+  wire           local_cs;
+  wire           local_rnw;
+  wire           local_ack;
+  wire [31:0]    local_addr;
+  wire [3:0]     local_be;
+  wire [31:0]    local_wdata;
+  wire [31:0]    local_rdata;
+    
+  aq_axi_lite_slave u_aq_axi_lite_slave 
+    (
+      .ARESETN(ARESETN),
+      .ACLK(S_AXI_ACLK),
+      
+      .S_AXI_AWADDR(S_AXI_AWADDR),
+      .S_AXI_AWCACHE(S_AXI_AWCACHE),
+      .S_AXI_AWPROT(S_AXI_AWPROT),
+      .S_AXI_AWVALID(S_AXI_AWVALID),
+      .S_AXI_AWREADY(S_AXI_AWREADY),
+      
+      .S_AXI_WDATA(S_AXI_WDATA),
+      .S_AXI_WSTRB(S_AXI_WSTRB),
+      .S_AXI_WVALID(S_AXI_WVALID),
+      .S_AXI_WREADY(S_AXI_WREADY),
+      
+      .S_AXI_BVALID(S_AXI_BVALID),
+      .S_AXI_BREADY(S_AXI_BREADY),
+      .S_AXI_BRESP(S_AXI_BRESP),
+      
+      .S_AXI_ARADDR(S_AXI_ARADDR),
+      .S_AXI_ARCACHE(S_AXI_ARCACHE),
+      .S_AXI_ARPROT(S_AXI_ARPROT),
+      .S_AXI_ARVALID(S_AXI_ARVALID),
+      .S_AXI_ARREADY(S_AXI_ARREADY),
+      
+      .S_AXI_RDATA(S_AXI_RDATA),
+      .S_AXI_RRESP(S_AXI_RRESP),
+      .S_AXI_RVALID(S_AXI_RVALID),
+      .S_AXI_RREADY(S_AXI_RREADY),
+      
+      .LOCAL_CS(local_cs),
+      .LOCAL_RNW(local_rnw),
+      .LOCAL_ACK(local_ack),
+      .LOCAL_ADDR(local_addr),
+      .LOCAL_BE(local_be),
+      .LOCAL_WDATA(local_wdata),
+      .LOCAL_RDATA(local_rdata),
+      
+      .DEBUG(debug_slave)
+      );
+
+    wire [3:0] i2c_cmd_wr, i2c_ram_wr;
+    wire [31:0] i2c_cmd_dout, i2c_sts_dout, i2c_rdata;
+    
+    reg local_cs_d;
+    always @(posedge S_AXI_ACLK or negedge ARESETN) begin
+        if(!ARESETN) begin
+            local_cs_d <= 1'b0;
+        end else begin
+            local_cs_d <= local_cs;
+        end
+    end
+    
+    assign local_ack = (local_cs & (~local_rnw)) | local_cs_d;
+    assign i2c_cmd_wr[3:0] = (local_cs & (~local_rnw) & (local_addr[15:0] == 16'h0400))?local_be[3:0]:4'd0;
+    assign i2c_ram_wr[3:0] = (local_cs & (~local_rnw) & (local_addr[15:10] == 6'd0))?local_be[3:0]:4'd0;
+
+    assign local_rdata[31:0] =  ((local_addr[15:10] == 6'd0)?i2c_rdata[31:0]:32'd0) |
+                                ((local_addr[15:0] == 16'h0400)?i2c_cmd_dout[31:0]:32'd0) |
+                                ((local_addr[15:0] == 16'h0404)?i2c_sts_dout[31:0]:32'd0) |
+                                ((local_addr[15:0] == 16'h0408)?32'hAA55AA55:32'd0);
+
+    wire w_isda, w_osda, w_oscl;
+
+    aq_i2c_master u_aq_i2c_master(
+	   .rst_n(ARESETN),
+	   .clk(S_AXI_ACLK),
+
+	   .cmd_wr(i2c_cmd_wr[3:0]),
+	   .cmd_din(local_wdata[31:0]),
+	   .cmd_dout(i2c_cmd_dout[31:0]),
+
+	   .sts_dout(i2c_sts_dout[31:0]),
+
+	   .adrs(local_addr[9:0]),
+	   .wena(i2c_ram_wr[3:0]),
+	   .wdata(local_wdata[31:0]),
+	   .rdata(i2c_rdata[31:0]),
+
+	   .osda(w_osda),
+	   .isda(w_isda),
+	   .osck(w_oscl)
+    );
+
+    assign I2C_SDA = (w_osda)?1'bZ:1'b0;
+    assign w_isda = I2C_SDA;
+    assign I2C_SCL = (w_oscl)?1'b1:1'b0;
+    
+endmodule

aquaxis_IPCORE/aq_axi_i2c/aq_axi_i2c.srcs/sources/aq_axi_lite_slave.v

@@ -0,0 +1,173 @@
+/*
+ * Copyright (C)2014-2015 AQUAXIS TECHNOLOGY.
+ *  Don't remove this header. 
+ * When you use this source, there is a need to inherit this header.
+ *
+ * License
+ *  For no commercial -
+ *   License:     The Open Software License 3.0
+ *   License URI: http://www.opensource.org/licenses/OSL-3.0
+ *
+ *  For commmercial -
+ *   License:     AQUAXIS License 1.0
+ *   License URI: http://www.aquaxis.com/licenses
+ *
+ * For further information please contact.
+ *	URI:    http://www.aquaxis.com/
+ *	E-Mail: info(at)aquaxis.com
+ */
+module aq_axi_lite_slave
+  (
+    // AXI4 Lite Interface
+    input         ARESETN,
+    input         ACLK,
+    
+    // Write Address Channel
+    input [31:0]  S_AXI_AWADDR,
+    input [3:0]   S_AXI_AWCACHE,  // 4'b0011
+    input [2:0]   S_AXI_AWPROT,   // 3'b000
+    input         S_AXI_AWVALID,
+    output        S_AXI_AWREADY, 
+        
+    // Write Data Channel
+    input [31:0]  S_AXI_WDATA,
+    input [3:0]   S_AXI_WSTRB,
+    input         S_AXI_WVALID,
+    output        S_AXI_WREADY,
+        
+    // Write Response Channel
+    output        S_AXI_BVALID,
+    input         S_AXI_BREADY,
+    output [1:0]  S_AXI_BRESP,
+
+    // Read Address Channel
+    input [31:0]  S_AXI_ARADDR,
+    input [3:0]   S_AXI_ARCACHE,  // 4'b0011
+    input [2:0]   S_AXI_ARPROT,   // 3'b000
+    input         S_AXI_ARVALID,
+    output        S_AXI_ARREADY,
+
+    // Read Data Channel
+    output [31:0] S_AXI_RDATA,
+    output [1:0]  S_AXI_RRESP,
+    output        S_AXI_RVALID,
+    input         S_AXI_RREADY,
+    
+    // Local Interface
+    output        LOCAL_CS,
+    output        LOCAL_RNW,
+    input         LOCAL_ACK,
+    output [31:0] LOCAL_ADDR,
+    output [3:0]  LOCAL_BE,
+    output [31:0] LOCAL_WDATA,
+    input [31:0]  LOCAL_RDATA,
+    
+    output [31:0] DEBUG
+  );
+
+/*
+CACHE[3:0]
+WA RA C  B 
+0  0  0  0 Noncacheable and nonbufferable
+0  0  0  1 Bufferable only
+0  0  1  0 Cacheable, but do not allocate
+0  0  1  1 Cacheable and Bufferable, but do not allocate
+0  1  1  0 Cacheable write-through, allocate on reads only
+0  1  1  1 Cacheable write-back, allocate on reads only
+1  0  1  0 Cacheable write-through, allocate on write only
+1  0  1  1 Cacheable write-back, allocate on writes only
+1  1  1  0 Cacheable write-through, allocate on both reads and writes
+1  1  1  1 Cacheable write-back, allocate on both reads and writes
+
+PROR
+[2]:0:Data Access
+    1:Instruction Access
+[1]:0:Secure Access
+    1:NoSecure Access
+[0]:0:Privileged Access
+    1:Normal Access
+
+RESP
+00: OK
+01: EXOK
+10: SLVERR
+11: DECERR
+*/
+
+  localparam S_IDLE   = 2'd0;
+  localparam S_WRITE  = 2'd1;
+  localparam S_WRITE2 = 2'd2;
+  localparam S_READ   = 2'd3;
+
+  reg [1:0]   state;
+  reg         reg_rnw;
+  reg [31:0]  reg_addr, reg_wdata;
+  reg [3:0]   reg_be;
+   
+  always @( posedge ACLK or negedge ARESETN ) begin
+    if( !ARESETN ) begin
+      state     <= S_IDLE;
+      reg_rnw   <= 1'b0;
+      reg_addr  <= 32'd0;
+      reg_wdata <= 32'd0;
+      reg_be    <= 4'd0;
+    end else begin
+      case( state )
+        S_IDLE: begin
+          if( S_AXI_AWVALID ) begin
+            reg_rnw   <= 1'b0;
+            reg_addr  <= S_AXI_AWADDR;
+            state     <= S_WRITE;
+          end else if( S_AXI_ARVALID ) begin
+            reg_rnw   <= 1'b1;
+            reg_addr  <= S_AXI_ARADDR;
+            state     <= S_READ;
+          end
+        end
+        S_WRITE: begin
+          if( S_AXI_WVALID ) begin
+            state     <= S_WRITE2;
+            reg_wdata <= S_AXI_WDATA;
+            reg_be    <= S_AXI_WSTRB;
+          end
+        end
+        S_WRITE2: begin
+          if( LOCAL_ACK & S_AXI_BREADY ) begin
+            state     <= S_IDLE;
+          end
+        end
+        S_READ: begin
+          if( LOCAL_ACK & S_AXI_RREADY ) begin
+            state     <= S_IDLE;
+          end
+        end
+        default: begin
+          state        <= S_IDLE;
+        end
+      endcase
+    end
+  end
+   
+  // Local Interface
+  assign LOCAL_CS       = (( state == S_WRITE2 )?1'b1:1'b0) | (( state == S_READ )?1'b1:1'b0) | 1'b0;
+  assign LOCAL_RNW      = reg_rnw;
+  assign LOCAL_ADDR     = reg_addr;
+  assign LOCAL_BE       = reg_be;
+  assign LOCAL_WDATA    = reg_wdata;
+   
+  // Write Channel
+  assign S_AXI_AWREADY  = ( state == S_WRITE )?S_AXI_AWVALID:1'b0;
+  assign S_AXI_WREADY   = ( state == S_WRITE )?S_AXI_WVALID:1'b0;
+  assign S_AXI_BVALID   = ( state == S_WRITE2 )?LOCAL_ACK:1'b0;
+  assign S_AXI_BRESP    = 2'b00;
+   
+  // Read Channel
+//  assign S_AXI_ARREADY  = ( state == S_READ )?S_AXI_ARVALID:1'b0;
+  assign S_AXI_ARREADY  = ( state == S_IDLE )?1'b1:1'b0;
+  assign S_AXI_RVALID   = ( state == S_READ )?LOCAL_ACK:1'b0;
+  assign S_AXI_RRESP    = 2'b00;
+  assign S_AXI_RDATA    = ( state == S_READ )?LOCAL_RDATA:32'd0;
+
+  // Debug
+  assign DEBUG[31:0]    = {24'd0, 1'd0, S_AXI_RVALID, S_AXI_ARREADY, LOCAL_ACK, LOCAL_RNW, LOCAL_CS, state[1:0]};
+endmodule