Add Batch 2 with 10 repos

.gitattributes

@@ -81,3 +81,5 @@ The-OpenROAD-Project_OpenROAD-flow-scripts/flow/designs/nangate45/bp_quad/bsg_ch
 The-OpenROAD-Project_OpenROAD-flow-scripts/flow/designs/src/bp_quad/bsg_chip_block.sv2v.v filter=lfs diff=lfs merge=lfs -text
 The-OpenROAD-Project_OpenROAD-flow-scripts/flow/designs/src/coyote/coyote.sv2v.v filter=lfs diff=lfs merge=lfs -text
 OpenTimer_OpenTimer/benchmark/vga_lcd/vga_lcd.v filter=lfs diff=lfs merge=lfs -text
+hguq_HG-PIPE/SPINAL/BlockSequence_bb.v filter=lfs diff=lfs merge=lfs -text
+hguq_HG-PIPE/SPINAL/vivado/BlockSequence_bb_replaced.v filter=lfs diff=lfs merge=lfs -text

CutestPanda_Opensoc/100_apb_gpio/firmware/apb_gpio.c

@@ -0,0 +1,107 @@
+/************************************************************************************************************************
+APB-GPIO����(��Դ�ļ�)
+@brief  APB-GPIO����
+@date   2024/08/23
+@author �¼�ҫ
+@eidt   2024/08/23 1.00 �����˵�һ����ʽ�汾
+************************************************************************************************************************/
+
+#include "apb_gpio.h"
+
+////////////////////////////////////////////////////////////////////////////////////////////////////////////
+
+/*************************
+@init
+@public
+@brief  ��ʼ��APB-GPIO
+@param  apb_gpio APB-GPIO(�ṹ��ָ��)
+        base_addr APB-GPIO�������ַ
+@return none
+*************************/
+void apb_gpio_init(ApbGPIO* apb_gpio, uint32_t base_addr){
+	apb_gpio->hardware = (ApbGPIOHd*)base_addr;
+}
+
+/*************************
+@io
+@public
+@brief  APB-GPIOд��ƽ
+@param  apb_gpio APB-GPIO(�ṹ��ָ��)
+        mask д��ƽ����
+        value ��д��ƽֵ
+@return none
+*************************/
+void apb_gpio_write_pin(ApbGPIO* apb_gpio, uint32_t mask, uint32_t value){
+	apb_gpio->hardware->out_mask = mask;
+	apb_gpio->hardware->out_v = value;
+}
+
+/*************************
+@io
+@public
+@brief  APB-GPIO����ƽ
+@param  apb_gpio APB-GPIO(�ṹ��ָ��)
+@return ��ȡ���ĵ�ƽֵ
+*************************/
+uint32_t apb_gpio_read_pin(ApbGPIO* apb_gpio){
+	return apb_gpio->hardware->in_v;
+}
+
+/*************************
+@io
+@public
+@brief  APB-GPIO������̬�ŷ���
+@param  apb_gpio APB-GPIO(�ṹ��ָ��)
+        dire ��������(0��ʾ���, 1��ʾ����)
+@return none
+*************************/
+void apb_gpio_set_direction(ApbGPIO* apb_gpio, uint32_t dire){
+	apb_gpio->now_dire = dire;
+	apb_gpio->hardware->dire = dire;
+}
+
+/*************************
+@cfg
+@public
+@brief  APB-GPIOʹ���ж�
+@param  apb_gpio APB-GPIO(�ṹ��ָ��)
+        itr_en �ж�ʹ������
+@return none
+*************************/
+void apb_gpio_enable_itr(ApbGPIO* apb_gpio, uint32_t itr_en){
+	apb_gpio->hardware->itr_global = 0x00000001;
+	apb_gpio->hardware->itr_en = itr_en;
+}
+
+/*************************
+@cfg
+@public
+@brief  APB-GPIO�����ж�
+@param  apb_gpio APB-GPIO(�ṹ��ָ��)
+@return none
+*************************/
+void apb_gpio_disable_itr(ApbGPIO* apb_gpio){
+	apb_gpio->hardware->itr_global = 0x00000000;
+}
+
+/*************************
+@sts
+@public
+@brief  APB-GPIO��ȡ�ж�״̬
+@param  apb_gpio APB-GPIO(�ṹ��ָ��)
+@return �ж�״̬����
+*************************/
+uint32_t apb_gpio_get_itr_status(ApbGPIO* apb_gpio){
+	return apb_gpio->hardware->itr_status;
+}
+
+/*************************
+@cfg
+@public
+@brief  APB-GPIO����жϱ�־
+@param  apb_gpio APB-GPIO(�ṹ��ָ��)
+@return none
+*************************/
+void apb_gpio_clear_itr_flag(ApbGPIO* apb_gpio){
+	apb_gpio->hardware->itr_global = 0x00000001;
+}

CutestPanda_Opensoc/100_apb_gpio/firmware/apb_gpio.h

@@ -0,0 +1,42 @@
+/************************************************************************************************************************
+APB-GPIO����(�ӿ�ͷ�ļ�)
+@brief  APB-GPIO����
+@date   2024/08/23
+@author �¼�ҫ
+************************************************************************************************************************/
+
+#include <stdint.h>
+
+////////////////////////////////////////////////////////////////////////////////////////////////////////////
+
+#ifndef __APB_GPIO_H
+#define __APB_GPIO_H
+
+typedef struct{
+	uint32_t out_v; // GPIO���
+	uint32_t out_mask; // GPIOд��ƽ����
+	uint32_t dire; // GPIO����(0��ʾ���, 1��ʾ����)
+	uint32_t in_v; // GPIO����
+	uint32_t itr_global; // ȫ���ж�ʹ��, ȫ���жϱ�־
+	uint32_t itr_status; // �ж�״̬
+	uint32_t itr_en; // �ж�ʹ��
+}ApbGPIOHd;
+
+typedef struct{
+	ApbGPIOHd* hardware; // APB-GPIO�Ĵ����ӿ�(�ṹ��ָ��)
+	uint32_t now_dire; // ��ǰ��GPIO����(0��ʾ���, 1��ʾ����)
+}ApbGPIO;
+
+#endif
+
+////////////////////////////////////////////////////////////////////////////////////////////////////////////
+
+void apb_gpio_init(ApbGPIO* apb_gpio, uint32_t base_addr); // ��ʼ��APB-GPIO
+void apb_gpio_write_pin(ApbGPIO* apb_gpio, uint32_t mask, uint32_t value); // APB-GPIOд��ƽ
+uint32_t apb_gpio_read_pin(ApbGPIO* apb_gpio); // APB-GPIO����ƽ
+void apb_gpio_set_direction(ApbGPIO* apb_gpio, uint32_t dire); // APB-GPIO������̬�ŷ���
+
+void apb_gpio_enable_itr(ApbGPIO* apb_gpio, uint32_t itr_en); // APB-GPIOʹ���ж�
+void apb_gpio_disable_itr(ApbGPIO* apb_gpio); // APB-GPIO�����ж�
+uint32_t apb_gpio_get_itr_status(ApbGPIO* apb_gpio); // APB-GPIO��ȡ�ж�״̬
+void apb_gpio_clear_itr_flag(ApbGPIO* apb_gpio); // APB-GPIO����жϱ�־

CutestPanda_Opensoc/100_apb_gpio/firmware/examples/apb_gpio_in_itr_example.c

@@ -0,0 +1,55 @@
+/************************************************************************************************************************
+APB-GPIOʾ������
+@brief  GPIO�����ж�ʾ��
+@attention �����Ӳ��ƽ̨������ȫ���жϿ�������ص�API
+@date   2024/08/23
+@author �¼�ҫ
+@eidt   2024/08/23 1.00 �����˵�һ����ʽ�汾
+************************************************************************************************************************/
+
+#include "../apb_gpio.h"
+
+#include "CMSDK_CM0.h"
+
+////////////////////////////////////////////////////////////////////////////////////////////////////////////
+
+#define APB_GPIO_BASEADDR 0x40000000 // APB-GPIO����ַ
+
+////////////////////////////////////////////////////////////////////////////////////////////////////////////
+
+static ApbGPIO gpio; // APB-GPIO����ṹ��
+
+static uint8_t led_pin_value = 0x00; // 1��ͨ����ǰ�������ƽֵ
+
+////////////////////////////////////////////////////////////////////////////////////////////////////////////
+
+/*************************
+@itr_handler
+@private
+@brief  APB-GPIO�����жϷ������(ʾ��)
+@param  none
+@return none
+*************************/
+void USER_GPIO_Handler(void){
+	// ��ת1��ͨ���������ƽ
+	led_pin_value = !led_pin_value;
+	apb_gpio_write_pin(&gpio, 0x00000002, led_pin_value ? 0xFFFFFFFF:0x00000000);
+	
+	apb_gpio_clear_itr_flag(&gpio); // ����жϱ�־
+}
+
+////////////////////////////////////////////////////////////////////////////////////////////////////////////
+
+void apb_gpio_in_itr_toggle_example(void){
+	apb_gpio_init(&gpio, APB_GPIO_BASEADDR); // ��ʼ��APB-GPIO
+	
+	apb_gpio_set_direction(&gpio, 0xFFFFFFFD); // ����0��ͨ������Ϊ����, 1��ͨ������Ϊ���
+	apb_gpio_write_pin(&gpio, 0x00000002, 0x00000000); // ����1��ͨ������͵�ƽ
+	
+	NVIC_SetPriority((IRQn_Type)3, 0x03); // NVIC����3���ж����ȼ�
+	NVIC_EnableIRQ((IRQn_Type)3); // NVICʹ��3���ж�
+	
+	apb_gpio_enable_itr(&gpio, 0x00000001); // APB-GPIOʹ��0��ͨ���������ж�
+	
+	while(1);
+}

CutestPanda_Opensoc/100_apb_gpio/firmware/examples/apb_gpio_out_example.c

@@ -0,0 +1,45 @@
+/************************************************************************************************************************
+APB-GPIOʾ������
+@brief  ����APB-GPIOʵ����ˮ��
+				��ˮ�ư���GPIO�����0~5��ͨ��
+@attention �����Ӳ��ƽ̨�������ӳ�(delay)��ص�API
+@date   2024/08/23
+@author �¼�ҫ
+@eidt   2024/08/23 1.00 �����˵�һ����ʽ�汾
+************************************************************************************************************************/
+
+#include "../apb_gpio.h"
+#include "delay.h"
+
+////////////////////////////////////////////////////////////////////////////////////////////////////////////
+
+#define APB_GPIO_BASEADDR 0x40000000 // APB-GPIO����ַ
+
+////////////////////////////////////////////////////////////////////////////////////////////////////////////
+
+const static uint8_t flow_led_out_value[7] = {0x20, 0x10, 0x08, 0x04, 0x02, 0x01, 0x00}; // ��ˮ����ʽ
+
+static ApbGPIO gpio; // APB-GPIO����ṹ��
+static uint8_t flow_led_stage_cnt = 0; // ��ˮ�ƽ׶μ�����
+
+////////////////////////////////////////////////////////////////////////////////////////////////////////////
+
+void apb_gpio_flow_led_example(void){
+	apb_gpio_init(&gpio, APB_GPIO_BASEADDR); // ��ʼ��APB-GPIO
+	
+	apb_gpio_set_direction(&gpio, 0xFFFFFFC0); // ����0~5��ͨ������Ϊ���
+	apb_gpio_write_pin(&gpio, 0x0000003F, 0x00000000); // ����0~5��ͨ������͵�ƽ
+	
+	while(1){
+		apb_gpio_write_pin(&gpio, 0x0000003F, (uint32_t)flow_led_out_value[flow_led_stage_cnt]); // �����ˮ�Ƶ�ƽ
+		
+		// ������ˮ�ƽ׶μ�����
+		if(flow_led_stage_cnt == 6){
+			flow_led_stage_cnt = 0;
+		}else{
+			flow_led_stage_cnt++;
+		}
+		
+		delay_ms(500); // �ӳ�0.5s
+	}
+}

CutestPanda_Opensoc/100_apb_gpio/firmware/examples/delay.c

@@ -0,0 +1,17 @@
+#include "delay.h"
+
+////////////////////////////////////////////////////////////////////////////////////////////////////////////
+
+static uint32_t cnt = 0;
+
+////////////////////////////////////////////////////////////////////////////////////////////////////////////
+
+void SysTick_Handler(void){
+	cnt++;
+}
+
+void delay_ms(uint32_t t){
+	cnt = 0;
+
+	while(cnt != t);
+}

CutestPanda_Opensoc/100_apb_gpio/firmware/examples/delay.h

@@ -0,0 +1,5 @@
+#include <stdint.h>
+
+////////////////////////////////////////////////////////////////////////////////////////////////////////////
+
+void delay_ms(uint32_t t);

CutestPanda_Opensoc/100_apb_gpio/rtl/apb_gpio.v

@@ -0,0 +1,314 @@
+/*
+MIT License
+
+Copyright (c) 2024 Panda, 2257691535@qq.com
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+*/
+
+`timescale 1ns / 1ps
+/********************************************************************
+本模块: 符合APB协议的GPIO控制器
+
+描述: 
+APB-GPIO控制器
+支持GPIO输入中断
+
+寄存器->
+    偏移量  |    含义                     |   读写特性   |    备注
+    0x00    gpio_width-1~0:GPIO输出             W
+    0x04    gpio_width-1~0:GPIO写电平掩码       W
+    0x08    gpio_width-1~0:GPIO方向             W         0为输出, 1为输入
+    0x0C    gpio_width-1~0:GPIO输入             R
+    0x10    0:全局中断使能                      W
+            1:全局中断标志                      RWC   请在中断服务函数中清除中断标志
+    0x14    gpio_width-1~0:中断状态             R
+    0x18    gpio_width-1~0:中断使能             W
+
+注意：
+无
+
+协议:
+APB SLAVE
+GPIO
+
+作者: 陈家耀
+日期: 2023/11/06
+********************************************************************/
+
+
+module apb_gpio #(
+    parameter integer gpio_width = 16, // GPIO位宽(1~32)
+    parameter gpio_dire = "inout", // GPIO方向(inout|input|output)
+    parameter default_output_value = 32'hffff_ffff, // GPIO默认输出电平
+    parameter default_tri_value = 32'hffff_ffff, // GPIO默认方向(0->输出 1->输入)(仅在inout模式下可用)
+    parameter en_itr = "true", // 是否使能GPIO中断
+    parameter itr_edge = "neg", // 中断极性(pos|neg)
+    parameter real simulation_delay = 1 // 仿真延时
+)(
+    // 时钟和复位
+    input wire clk,
+    input wire resetn,
+    
+    // APB从机接口
+    input wire[31:0] paddr,
+    input wire psel,
+    input wire penable,
+    input wire pwrite,
+    input wire[31:0] pwdata,
+    output wire pready_out, // const -> 1'b1
+    output wire[31:0] prdata_out,
+    output wire pslverr_out, // const -> 1'b0
+    
+    // GPIO
+    output wire[gpio_width-1:0] gpio_o,
+    output wire[gpio_width-1:0] gpio_t, // 0->输出, 1->输入
+    input wire[gpio_width-1:0] gpio_i,
+    
+    // 中断
+    output wire gpio_itr
+);
+    
+    /** GPIO三态总线 **/
+    wire[gpio_width-1:0] gpio_o_w;
+    wire[gpio_width-1:0] gpio_t_w;
+    wire[gpio_width-1:0] gpio_i_w;
+    
+    generate
+        if(gpio_dire != "input")
+            assign gpio_o = gpio_o_w;
+        else
+            assign gpio_o = default_output_value;
+        
+        if(gpio_dire == "inout")
+            assign gpio_t = gpio_t_w;
+        else if(gpio_dire == "input")
+            assign gpio_t = 32'hffff_ffff;
+        else
+            assign gpio_t = 32'h0000_0000;
+        
+        if(gpio_dire != "output")
+        begin
+            reg[gpio_width-1:0] gpio_i_d;
+            reg[gpio_width-1:0] gpio_i_d2;
+            
+            assign gpio_i_w = gpio_i_d2;
+            
+            always @(posedge clk)
+            begin
+                # simulation_delay;
+                
+                gpio_i_d <= gpio_i;
+                gpio_i_d2 <= gpio_i_d;
+            end
+        end
+        else
+            assign gpio_i_w = gpio_o_w;
+    endgenerate
+    
+    /** GPIO中断 **/
+    wire[gpio_width-1:0] gpio_i_w_d; // 延迟1clk的gpio输入
+    wire gpio_global_itr_en_w; // 全局中断使能
+    wire[gpio_width-1:0] gpio_itr_en_w; // 中断使能
+    wire gpio_itr_flag_w; // 中断标志
+    wire[gpio_width-1:0] gpio_itr_mask_w; // 中断掩码
+    wire[gpio_width-1:0] gpio_itr_mask_w_d; // 延迟1clk的中断掩码
+    wire gpio_org_itr_pulse; // 原始中断脉冲
+    wire gpio_itr_w; // 中断信号
+    
+    assign gpio_itr = gpio_itr_w;
+    
+    generate
+        if((en_itr == "true") && (gpio_dire != "output"))
+        begin
+            reg[gpio_width-1:0] gpio_org_itr_mask_regs;
+            reg[gpio_width-1:0] gpio_itr_mask_regs_d;
+            reg gpio_org_itr_pulse_reg;
+            
+            assign gpio_itr_mask_w = gpio_org_itr_mask_regs;
+            assign gpio_itr_mask_w_d = gpio_itr_mask_regs_d;
+            assign gpio_org_itr_pulse = gpio_org_itr_pulse_reg;
+            
+            always @(posedge clk or negedge resetn)
+            begin
+                if(~resetn)
+                begin
+                    gpio_org_itr_pulse_reg <= 1'b0;
+                    gpio_org_itr_mask_regs <= {gpio_width{1'b0}};
+                    gpio_itr_mask_regs_d <= {gpio_width{1'b0}};
+                end
+                else
+                begin
+                    # simulation_delay;
+                    
+                    gpio_org_itr_pulse_reg <= (gpio_org_itr_mask_regs != {gpio_width{1'b0}}) & gpio_global_itr_en_w & (~gpio_itr_flag_w); // 原始中断脉冲
+                    gpio_org_itr_mask_regs <= ((itr_edge == "pos") ? (gpio_i_w & (~gpio_i_w_d)):((~gpio_i_w) & gpio_i_w_d)) & // 捕获上升沿或下降沿
+                        gpio_t_w & // 仅考虑输入模式gpio的中断
+                        gpio_itr_en_w; // gpio输入中断使能
+                    gpio_itr_mask_regs_d <= gpio_org_itr_mask_regs; // 对中断状态打1拍
+                end
+            end
+            
+            // 对原始中断脉冲进行延展
+            itr_generator #(
+                .pulse_w(10),
+                .simulation_delay(simulation_delay)
+            )itr_generator_u(
+                .clk(clk),
+                .rst_n(resetn),
+                .itr_org(gpio_org_itr_pulse),
+                .itr(gpio_itr_w)
+            );
+        end
+        else
+        begin
+            assign gpio_itr_w = 1'b0;
+            
+            assign gpio_itr_mask_w = 32'd0;
+            assign gpio_org_itr_pulse = 1'b0;
+        end
+    endgenerate
+    
+    /** APB写寄存器 **/
+    reg[31:0] gpio_o_value_regs; // GPIO输出
+    reg[31:0] gpio_o_mask_regs; // GPIO写电平掩码
+    reg[31:0] gpio_direction_regs; // GPIO方向
+    reg[31:0] gpio_i_value_regs; // GPIO输入
+    reg[31:0] gpio_itr_status_regs; // 全局中断使能, 中断标志
+    reg[31:0] gpio_itr_mask_regs; // 中断状态
+    reg[31:0] gpio_itr_en_regs; // 中断使能
+    
+    assign gpio_o_w = gpio_o_value_regs[gpio_width-1:0];
+    assign gpio_t_w = gpio_direction_regs[gpio_width-1:0];
+    
+    assign gpio_i_w_d = gpio_i_value_regs[gpio_width-1:0];
+    assign gpio_global_itr_en_w = gpio_itr_status_regs[0];
+    assign gpio_itr_en_w = gpio_itr_en_regs;
+    assign gpio_itr_flag_w = gpio_itr_status_regs[1];
+    
+    genvar gpio_o_value_regs_i;
+    generate
+        for(gpio_o_value_regs_i = 0;gpio_o_value_regs_i < gpio_width;gpio_o_value_regs_i = gpio_o_value_regs_i + 1)
+        begin
+            always @(posedge clk or negedge resetn)
+            begin
+                if(~resetn)
+                    gpio_o_value_regs[gpio_o_value_regs_i] <= default_output_value[gpio_o_value_regs_i];
+                else if(psel & pwrite & penable & (paddr[4:2] == 3'd0) & gpio_o_mask_regs[gpio_o_value_regs_i]) // 写GPIO输出电平
+                    # simulation_delay gpio_o_value_regs[gpio_o_value_regs_i] <= pwdata[gpio_o_value_regs_i];
+            end
+        end
+    endgenerate
+    
+    always @(posedge clk or negedge resetn)
+    begin
+        if(~resetn)
+        begin
+            gpio_o_mask_regs[gpio_width-1:0] <= {gpio_width{1'b1}};
+            
+            if(gpio_dire == "inout")
+                gpio_direction_regs[gpio_width-1:0] <= default_tri_value;
+            else if(gpio_dire == "input")
+                gpio_direction_regs[gpio_width-1:0] <= {gpio_width{1'b1}};
+            else
+                gpio_direction_regs[gpio_width-1:0] <= {gpio_width{1'b0}};
+            
+            gpio_itr_status_regs[0] <= 1'b0;
+            gpio_itr_en_regs[gpio_width-1:0] <= {gpio_width{1'b0}};
+        end
+        else if(psel & pwrite & penable)
+        begin
+            # simulation_delay;
+            
+            case(paddr[4:2])
+                3'd1: // 写GPIO写电平掩码
+                    gpio_o_mask_regs[gpio_width-1:0] <= pwdata[gpio_width-1:0];
+                3'd2: // 写GPIO方向, 仅inout下修改有效
+                    gpio_direction_regs[gpio_width-1:0] <= pwdata[gpio_width-1:0];
+                3'd4: // 写全局中断使能
+                    gpio_itr_status_regs[0] <= pwdata[0];
+                3'd6: // 写中断使能
+                    gpio_itr_en_regs[gpio_width-1:0] <= pwdata[gpio_width-1:0];
+                default: // hold
+                begin
+                    gpio_o_mask_regs[gpio_width-1:0] <= gpio_o_mask_regs[gpio_width-1:0];
+                    gpio_direction_regs[gpio_width-1:0] <= gpio_direction_regs[gpio_width-1:0];
+                    gpio_itr_status_regs[0] <= gpio_itr_status_regs[0];
+                    gpio_itr_en_regs[gpio_width-1:0] <= gpio_itr_en_regs[gpio_width-1:0];
+                end
+            endcase
+        end
+    end
+    
+    always @(posedge clk or negedge resetn)
+    begin
+        if(~resetn)
+            gpio_itr_status_regs[1] <= 1'b0;
+        else if(psel & pwrite & penable & (paddr[4:2] == 3'd4)) // 清除中断���志
+            # simulation_delay gpio_itr_status_regs[1] <= 1'b0;
+        else if(~gpio_itr_status_regs[1]) // 等待新的GPIO中断, 中断标志为高时屏蔽新的GPIO中断
+            # simulation_delay gpio_itr_status_regs[1] <= gpio_org_itr_pulse;
+    end
+    
+    // 生成状态信息
+    always @(posedge clk or negedge resetn)
+    begin
+        if(~resetn)
+        begin
+            gpio_i_value_regs[gpio_width-1:0] <= (itr_edge == "pos") ? {gpio_width{1'b0}}:{gpio_width{1'b1}};
+            gpio_itr_mask_regs[gpio_width-1:0] <= {gpio_width{1'b0}};
+        end
+        else
+        begin
+            # simulation_delay;
+            
+            gpio_i_value_regs[gpio_width-1:0] <= gpio_i_w; // 载入GPIO输入电平
+            
+            if(gpio_org_itr_pulse) // 载入中断状态
+                gpio_itr_mask_regs[gpio_width-1:0] <= gpio_itr_mask_w_d;
+        end
+    end
+    
+    /** APB读寄存器 **/
+    reg[31:0] prdata_out_regs;
+	
+	assign pready_out = 1'b1;
+    assign pslverr_out = 1'b0;
+    assign prdata_out = prdata_out_regs;
+    
+    always @(posedge clk)
+    begin
+        if(psel & (~pwrite))
+        begin
+            # simulation_delay;
+            
+            case(paddr[4:2])
+                3'd3: // 读GPIO输入
+                    prdata_out_regs <= {{(32-gpio_width){1'bx}}, gpio_i_value_regs[gpio_width-1:0]};
+                3'd4: // 读中断标志
+                    prdata_out_regs <= {30'dx, gpio_itr_status_regs[1], 1'bx};
+                3'd5: // 读中断状态
+                    prdata_out_regs <= {{(32-gpio_width){1'bx}}, gpio_itr_mask_regs[gpio_width-1:0]};
+                default: // not care
+                    prdata_out_regs <= 32'dx;
+            endcase
+        end
+    end
+
+endmodule

CutestPanda_Opensoc/100_apb_gpio/rtl/itr_generator.v

@@ -0,0 +1,104 @@
+/*
+MIT License
+
+Copyright (c) 2024 Panda, 2257691535@qq.com
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+*/
+
+`timescale 1ns / 1ps
+/********************************************************************
+本模块: 中断信号发生器
+
+描述: 
+将原始的中断脉冲拓展为一定脉宽的中断信号
+
+注意：
+中断脉宽必须 >= 2
+
+协议:
+无
+
+作者: 陈家耀
+日期: 2023/11/08
+********************************************************************/
+
+
+module itr_generator #(
+    parameter integer pulse_w = 100, // 中断脉宽(必须>=1)
+    parameter real simulation_delay = 1 // 仿真延时
+)(
+    // 时钟和复位
+    input wire clk,
+    input wire rst_n,
+    
+    input wire itr_org, // 原始中断输入
+    output wire itr // 中断输出
+);
+
+    // 计算log2(bit_depth)               
+    function integer clogb2 (input integer bit_depth);
+        integer temp;
+    begin
+        temp = bit_depth;
+        for(clogb2 = -1;temp > 0;clogb2 = clogb2 + 1)                   
+            temp = temp >> 1;                                 
+    end                                        
+    endfunction
+    
+    // 产生中断信号
+    reg itr_reg; // 中断信号
+    reg[clogb2(pulse_w - 1):0] itr_cnt; // 中断计数器
+    
+    assign itr = itr_reg;
+    
+    generate
+        if(pulse_w == 1)
+        begin
+            always @(posedge clk or negedge rst_n)
+            begin
+                if(~rst_n)
+                    itr_reg <= 1'b0;
+                else
+                    # simulation_delay itr_reg <= itr_org;
+            end
+        end
+        else
+        begin
+            always @(posedge clk or negedge rst_n)
+            begin
+                if(~rst_n)
+                    itr_reg <= 1'b0;
+                else
+                begin
+                    # simulation_delay;
+                    
+                    if(~itr_reg) // 等待原始中断脉冲
+                        itr_reg <= itr_org;
+                    else // 等待计数完成
+                        itr_reg <= itr_cnt != pulse_w - 1;
+                end
+            end
+        end
+    endgenerate
+    
+    always @(posedge clk)
+        # simulation_delay itr_cnt <= (~itr_reg) ? 0:(itr_cnt + 1);
+
+endmodule

CutestPanda_Opensoc/101_apb_uart/firmware/apb_uart.c

@@ -0,0 +1,153 @@
+/************************************************************************************************************************
+APB-UART����(��Դ�ļ�)
+@brief  APB-UART����
+@date   2024/08/28
+@author �¼�ҫ
+@eidt   2024/08/28 1.00 �����˵�һ����ʽ�汾
+************************************************************************************************************************/
+
+#include "apb_uart.h"
+
+////////////////////////////////////////////////////////////////////////////////////////////////////////////
+
+/*************************
+@init
+@public
+@brief  ��ʼ��APB-UART
+@param  uart APB-UART(�ṹ��ָ��)
+        base_addr APB-UART�������ַ
+@return none
+*************************/
+void apb_uart_init(ApbUART* uart, uint32_t base_addr){
+	uart->hardware = (ApbUARTHd*)base_addr;
+	uart->itr_en = 0x00;
+}
+
+/*************************
+@io
+@public
+@brief  APB-UART����һ���ֽ�
+@param  uart APB-UART(�ṹ��ָ��)
+        byte �����͵��ֽ�����
+@return �Ƿ�ɹ�
+*************************/
+int apb_uart_send_byte(ApbUART* uart, uint8_t byte){
+	uint32_t fifo_cs = uart->hardware->fifo_cs;
+	
+	if(fifo_cs & 0x01){
+		return -1;
+	}else{
+		fifo_cs &= (~0x3FC);
+		fifo_cs |= ((uint32_t)byte) << 2;
+		uart->hardware->fifo_cs = fifo_cs;
+		
+		uart->hardware->fifo_cs = (fifo_cs | 0x02);
+		uart->hardware->fifo_cs = (fifo_cs & (~0x02));
+		
+		return 0;
+	}
+}
+
+/*************************
+@io
+@public
+@brief  APB-UART��ȡһ�������ֽ�
+@param  uart APB-UART(�ṹ��ָ��)
+        byte �����ֽ����ݻ�����(�׵�ַ)
+@return �Ƿ�ɹ�
+*************************/
+int apb_uart_rev_byte(ApbUART* uart, uint8_t* byte){
+	uint32_t fifo_cs = uart->hardware->fifo_cs;
+	
+	if(fifo_cs & 0x400){
+		return -1;
+	}else{
+		uart->hardware->fifo_cs = (fifo_cs | 0x800);
+		uart->hardware->fifo_cs = (fifo_cs & (~0x800));
+		
+		fifo_cs = uart->hardware->fifo_cs;
+		*byte = (fifo_cs >> 12) & 0xFF;
+		
+		return 0;
+	}
+}
+
+/*************************
+@cfg
+@public
+@brief  APB-UARTʹ���ж�
+@param  uart APB-UART(�ṹ��ָ��)
+        itr_mask �ж�ʹ������
+				config �շ��ж���ֵ����(�ṹ��ָ��)
+@return none
+*************************/
+void apb_uart_enable_itr(ApbUART* uart, uint8_t itr_mask, const ApbUartItrThConfig* config){
+	uart->hardware->itr_status_en = 0x00000001 | (itr_mask << 1);
+	uart->itr_en = itr_mask;
+	
+	uart->hardware->tx_itr_th = 
+		((uint32_t)(config->tx_bytes_n_th - 1)) | (((uint32_t)(config->tx_idle_th - 2)) << 16);
+	uart->hardware->rx_itr_th =
+		((uint32_t)(config->rx_bytes_n_th - 1)) | (((uint32_t)(config->rx_idle_th - 2)) << 16);
+}
+
+/*************************
+@cfg
+@public
+@brief  APB-UART�����ж�
+@param  uart APB-UART(�ṹ��ָ��)
+@return none
+*************************/
+void apb_uart_disable_itr(ApbUART* uart){
+	uart->hardware->itr_status_en = 0x00000000;
+	uart->itr_en = 0x00;
+}
+
+/*************************
+@sts
+@public
+@brief  APB-UART��ȡ�ж�״̬
+@param  uart APB-UART(�ṹ��ָ��)
+@return �ж�״̬
+*************************/
+uint8_t apb_uart_get_itr_status(ApbUART* uart){
+	uint32_t itr_status_en = uart->hardware->itr_status_en;
+	
+	return (uint8_t)(itr_status_en >> 17) & 0x1F;
+}
+
+/*************************
+@cfg
+@public
+@brief  APB-UART����жϱ�־
+@param  uart APB-UART(�ṹ��ָ��)
+@return none
+*************************/
+void apb_uart_clear_itr_flag(ApbUART* uart){
+	uart->hardware->itr_status_en = 0x00000001 | (uart->itr_en << 1);
+}
+
+/*************************
+@io
+@public
+@brief  APB-UART��ʽ�������ַ���
+@param  uart APB-UART(�ṹ��ָ��)
+			  fmt ��ʽ���ַ���
+        ... �ַ������Ӳ���
+@return none
+*************************/
+void uart_printf(ApbUART* uart, char *fmt, ...){
+	unsigned char UsartPrintfBuf[296];
+	va_list ap;
+	unsigned char* pStr = UsartPrintfBuf;
+	
+	va_start(ap, fmt);
+	vsnprintf((char *)UsartPrintfBuf, sizeof(UsartPrintfBuf), (const char *)fmt, ap);                      
+	va_end(ap);
+	
+	while(*pStr != 0){
+		while (!apb_uart_send_byte(uart, *pStr));
+		
+		pStr++;
+	}
+}

CutestPanda_Opensoc/101_apb_uart/firmware/apb_uart.h

@@ -0,0 +1,60 @@
+/************************************************************************************************************************
+APB-UART����(�ӿ�ͷ�ļ�)
+@brief  APB-UART����
+@date   2024/08/28
+@author �¼�ҫ
+************************************************************************************************************************/
+
+#include <stdint.h>
+#include <stdarg.h>
+#include <string.h>
+#include <stdio.h>
+
+////////////////////////////////////////////////////////////////////////////////////////////////////////////
+
+#ifndef __APB_UART_H
+#define __APB_UART_H
+
+typedef struct{
+	uint32_t fifo_cs; // �շ�fifo����
+	uint32_t itr_status_en; // �жϿ���
+	uint32_t tx_itr_th; // �����ж���ֵ
+	uint32_t rx_itr_th; // �����ж���ֵ
+}ApbUARTHd;
+
+typedef struct{
+	ApbUARTHd* hardware; // APB-UART�Ĵ����ӿ�(�ṹ��ָ��)
+	uint8_t itr_en; // ��ǰ���ж�ʹ������
+}ApbUART;
+
+typedef struct{
+	uint16_t tx_bytes_n_th; // UART�����ж��ֽ�����ֵ
+	uint16_t tx_idle_th; // UART�����ж�IDLE��������ֵ
+	uint16_t rx_bytes_n_th; // UART�����ж��ֽ�����ֵ
+	uint16_t rx_idle_th; // UART�����ж�IDLE��������ֵ
+}ApbUartItrThConfig;
+
+#endif
+
+////////////////////////////////////////////////////////////////////////////////////////////////////////////
+
+// ���������
+#define APB_UART_TX_BYTES_N_ITR_MASK 0x01 // UART���ʹﵽ�涨�ֽ����ж�
+#define APB_UART_TX_IDLE_ITR_MASK 0x02 // UART����IDLE�ж�
+#define APB_UART_RX_BYTES_N_ITR_MASK 0x04 // UART���մﵽ�涨�ֽ����ж�
+#define APB_UART_RX_IDLE_ITR_MASK 0x08 // UART����IDLE�ж�
+#define APB_UART_RX_ERR_ITR_MASK 0x10 // UART����FIFO����ж�
+
+////////////////////////////////////////////////////////////////////////////////////////////////////////////
+
+void apb_uart_init(ApbUART* uart, uint32_t base_addr); // ��ʼ��APB-UART
+
+int apb_uart_send_byte(ApbUART* uart, uint8_t byte); // APB-UART����һ���ֽ�
+int apb_uart_rev_byte(ApbUART* uart, uint8_t* byte); // APB-UART��ȡһ�������ֽ�
+
+void apb_uart_enable_itr(ApbUART* uart, uint8_t itr_mask, const ApbUartItrThConfig* config); // APB-UARTʹ���ж�
+void apb_uart_disable_itr(ApbUART* uart); // APB-UART�����ж�
+uint8_t apb_uart_get_itr_status(ApbUART* uart); // APB-UART��ȡ�ж�״̬
+void apb_uart_clear_itr_flag(ApbUART* uart); // APB-UART����жϱ�־
+
+void uart_printf(ApbUART* uart, char *fmt, ...); // APB-UART��ʽ�������ַ���

CutestPanda_Opensoc/101_apb_uart/firmware/examples/apb_uart_rx_itr_example.c

@@ -0,0 +1,55 @@
+/************************************************************************************************************************
+APB-UARTʾ������
+@brief  UART����IDLE�ж�ʾ��
+@attention �����Ӳ��ƽ̨������ȫ���жϿ�������ص�API
+@date   2024/08/28
+@author �¼�ҫ
+@eidt   2024/08/28 1.00 �����˵�һ����ʽ�汾
+************************************************************************************************************************/
+
+#include "../apb_uart.h"
+
+#include "CMSDK_CM0.h"
+
+////////////////////////////////////////////////////////////////////////////////////////////////////////////
+
+#define APB_UART_BASEADDR 0x40000000 // APB-UART�������ַ
+
+////////////////////////////////////////////////////////////////////////////////////////////////////////////
+
+static ApbUART uart; // APB-UART����ṹ��
+
+////////////////////////////////////////////////////////////////////////////////////////////////////////////
+
+/*************************
+@itr_handler
+@private
+@brief  APB-UART�շ��жϷ������(ʾ��)
+@param  none
+@return none
+*************************/
+void USER_UART_Handler(void){
+	uint8_t byte;
+	
+	while(!apb_uart_rev_byte(&uart, &byte)){ // �ռ�UART���ݰ�
+		apb_uart_send_byte(&uart, byte); // ��ԭ������
+	}
+	
+	apb_uart_clear_itr_flag(&uart); // �����жϱ�־
+}
+
+////////////////////////////////////////////////////////////////////////////////////////////////////////////
+
+void apb_uart_rx_itr_example(void){
+	apb_uart_init(&uart, APB_UART_BASEADDR); // ��ʼ��APB-UART
+	
+	// ����UART����IDLE�ж�
+	const ApbUartItrThConfig uart_config = {10, 100, 10, 100}; // UART�����ж�IDLE��������ֵ = 100
+	
+	apb_uart_enable_itr(&uart, APB_UART_RX_IDLE_ITR_MASK, &uart_config); // ʹ��UART����IDLE�ж�
+	
+	NVIC_SetPriority((IRQn_Type)4, 0x03); // NVIC����4���ж����ȼ�
+	NVIC_EnableIRQ((IRQn_Type)4); // NVICʹ��4���ж�
+	
+	while(1);
+}

CutestPanda_Opensoc/101_apb_uart/firmware/examples/apb_uart_tx_example.c

@@ -0,0 +1,28 @@
+/************************************************************************************************************************
+APB-UARTʾ������
+@brief  UART����ʾ��
+@date   2024/08/28
+@author �¼�ҫ
+@eidt   2024/08/28 1.00 �����˵�һ����ʽ�汾
+************************************************************************************************************************/
+
+#include "../apb_uart.h"
+
+////////////////////////////////////////////////////////////////////////////////////////////////////////////
+
+#define APB_UART_BASEADDR 0x40000000 // APB-UART�������ַ
+
+////////////////////////////////////////////////////////////////////////////////////////////////////////////
+
+static ApbUART uart; // APB-UART����ṹ��
+
+////////////////////////////////////////////////////////////////////////////////////////////////////////////
+
+void apb_uart_tx_example(void){
+	apb_uart_init(&uart, APB_UART_BASEADDR); // ��ʼ��APB-UART
+	
+	// �����ַ���
+	uart_printf(&uart, "hello, world!\n\r");
+	
+	while(1);
+}

CutestPanda_Opensoc/101_apb_uart/rtl/apb_uart.v

@@ -0,0 +1,617 @@
+`timescale 1ns / 1ps
+/********************************************************************
+本模块: 符合APB协议的UART控制器
+
+描述: 
+APB-UART控制器
+支持UART发送/接收中断
+
+寄存器->
+    偏移量  |    含义                     |   读写特性    |        备注
+    0x00    0:发送fifo是否满                    R
+            1:发送fifo写使能                    W         发送fifo写使能取上升沿
+            9~2:发送fifo写数据                  W
+            10:接收fifo是否空                   R
+            11:接收fifo读使能                   W         接收fifo读使能取上升沿
+            19~12:接收fifo读数据                R
+    0x04    0:UART全局中断使能                  W
+            1:UART发送达到规定字节数中断使能     W
+            2:UART发送IDLE中断使能              W
+            3:UART接收达到规定字节数中断使能     W
+            4:UART接收IDLE中断使能              W
+            5:UART接收FIFO溢出中断使能          W
+            16:UART中断标志                    RWC      请在中断服务函数中清除中断标志
+            21~17:UART中断状态                  R
+    0x08    15~0:UART发送中断字节数阈值         W               注意要减1
+            31~16:UART发送中断IDLE周期数阈值    W               注意要减2
+    0x0C    15~0:UART接收中断字节数阈值         W               注意要减1
+            31~16:UART接收中断IDLE周期数阈值    W               注意要减2
+
+注意：
+无
+
+协议:
+APB SLAVE
+UART
+
+作者: 陈家耀
+日期: 2023/11/07
+********************************************************************/
+
+
+module apb_uart #(
+    parameter integer clk_frequency_MHz = 50, // 时钟频率
+    parameter integer baud_rate = 115200, // 波特率
+    parameter tx_rx_fifo_ram_type = "bram", // 发送接收fifo的RAM类型(lutram|bram)
+    parameter integer tx_fifo_depth = 1024, // 发送fifo深度(32|64|128|...|2048)
+    parameter integer rx_fifo_depth = 1024, // 接收fifo深度(32|64|128|...|2048)
+    parameter en_itr = "false", // 是否使能UART中断
+    parameter real simulation_delay = 1 // 仿真延时
+)(
+    // 时钟和复位
+    input wire clk,
+    input wire resetn,
+    
+    // APB从机接口
+    input wire[31:0] paddr,
+    input wire psel,
+    input wire penable,
+    input wire pwrite,
+    input wire[31:0] pwdata,
+    output wire pready_out, // const -> 1'b1
+    output wire[31:0] prdata_out,
+    output wire pslverr_out, // const -> 1'b0
+    
+    // UART
+    output wire uart_tx,
+    input wire uart_rx,
+    
+    // 中断
+    output wire uart_itr
+);
+
+    /* UART发送和接收fifo */
+    // 发送fifo写端口
+    wire tx_fifo_wen;
+    wire tx_fifo_full;
+    wire[7:0] tx_fifo_din;
+    // 发送fifo读端口
+    wire tx_fifo_ren;
+    wire tx_fifo_empty;
+    wire[7:0] tx_fifo_dout;
+    // 接收fifo写端口
+    wire rx_fifo_wen;
+    wire rx_fifo_full;
+    wire[7:0] rx_fifo_din;
+    // 接收fifo读端口
+    wire rx_fifo_ren;
+    wire rx_fifo_empty;
+    wire[7:0] rx_fifo_dout;
+    
+    // 发送fifo
+    ram_fifo_wrapper #(
+        .fwft_mode("false"),
+        .ram_type(tx_rx_fifo_ram_type),
+        .en_bram_reg("false"),
+        .fifo_depth(tx_fifo_depth),
+        .fifo_data_width(8),
+        .full_assert_polarity("high"),
+        .empty_assert_polarity("high"),
+        .almost_full_assert_polarity("no"),
+        .almost_empty_assert_polarity("no"),
+        .en_data_cnt("false"),
+        .almost_full_th(),
+        .almost_empty_th(),
+        .simulation_delay(simulation_delay)
+    )tx_fifo(
+        .clk(clk),
+        .rst_n(resetn),
+        .fifo_wen(tx_fifo_wen),
+        .fifo_din(tx_fifo_din),
+        .fifo_full(tx_fifo_full),
+        .fifo_ren(tx_fifo_ren),
+        .fifo_dout(tx_fifo_dout),
+        .fifo_empty(tx_fifo_empty)
+    );
+    
+    // 接收fifo
+    ram_fifo_wrapper #(
+        .fwft_mode("false"),
+        .ram_type(tx_rx_fifo_ram_type),
+        .en_bram_reg("false"),
+        .fifo_depth(rx_fifo_depth),
+        .fifo_data_width(8),
+        .full_assert_polarity("high"),
+        .empty_assert_polarity("high"),
+        .almost_full_assert_polarity("no"),
+        .almost_empty_assert_polarity("no"),
+        .en_data_cnt("false"),
+        .almost_full_th(),
+        .almost_empty_th(),
+        .simulation_delay(simulation_delay)
+    )rx_fifo(
+        .clk(clk),
+        .rst_n(resetn),
+        .fifo_wen(rx_fifo_wen),
+        .fifo_din(rx_fifo_din),
+        .fifo_full(rx_fifo_full),
+        .fifo_ren(rx_fifo_ren),
+        .fifo_dout(rx_fifo_dout),
+        .fifo_empty(rx_fifo_empty)
+    );
+    
+    /** UART中断 **/
+    wire uart_org_itr_pulse; // 原始的UART中断脉冲
+    wire uart_org_itr_pulse_d; // 延迟1clk的原始的UART中断脉冲
+    wire uart_itr_flag; // UART总中断标志
+    wire[4:0] uart_itr_mask; // UART子中断标志向量(UART接收FIFO溢出中断使能, UART接收IDLE中断使能, UART接收达到规定字节数中断使能, UART发送IDLE中断使能, UART发送达到规定字节数中断使能)
+    wire[4:0] uart_itr_mask_d; // 延迟1clk的UART子中断标志向量
+    wire uart_global_itr_en; // UART全局中断使能
+    wire[4:0] uart_itr_en; // UART中断使能(UART接收FIFO溢出中断使能, UART接收IDLE中断使能, UART接收达到规定字节数中断使能, UART发送IDLE中断使能, UART发送达到规定字节数中断使能)
+    
+    wire[15:0] tx_bytes_n_th; // UART发送中断字节数阈值
+    wire[15:0] tx_bytes_n_th_sub1; // UART发送中断字节数阈值-1
+    wire tx_bytes_n_th_eq0; // UART发送中断字节数阈值等于0(标志)
+    wire[15:0] tx_idle_n_th; // UART发送中断IDLE周期数阈值
+    wire[15:0] rx_bytes_n_th; // UART接收中断字节数阈值
+    wire[15:0] rx_bytes_n_th_sub1; // UART接收中断字节数阈值-1
+    wire rx_bytes_n_th_eq0; // UART接收中断字节数阈值等于0(标志)
+    wire[15:0] rx_idle_n_th; // UART接收中断IDLE周期数阈值
+    
+    wire rx_err; // 接收溢出(脉冲)
+    wire tx_idle; // 发送空闲(标志)
+    wire rx_idle; // 接收空闲(标志)
+    wire tx_done; // 发送完成(脉冲)
+    wire rx_done; // 接收完成(脉冲)
+    wire rx_start; // 接收开始(脉冲)
+    
+    generate
+        if(en_itr == "true")
+        begin
+            reg[15:0] uart_tx_finished_bytes_n_cnt; // 已发送字节数(计数器)
+            reg uart_tx_finished_bytes_n_cnt_eq_th_sub1; // 已发送字节数 == UART发送中断字节数阈值-1(标志)
+            reg uart_tx_finished_bytes_n_itr_pulse; // UART发送达到规定字节数(原始中断脉冲)
+            
+            always @(posedge clk or negedge resetn)
+            begin
+                if(~resetn)
+                begin
+                    uart_tx_finished_bytes_n_cnt <= 16'd0;
+                    uart_tx_finished_bytes_n_cnt_eq_th_sub1 <= 1'b0;
+                end
+                else if((~uart_itr_en[0]) | (~uart_global_itr_en))
+                begin
+                    # simulation_delay;
+                    
+                    uart_tx_finished_bytes_n_cnt <= 16'd0;
+                    uart_tx_finished_bytes_n_cnt_eq_th_sub1 <= 1'b0;
+                end
+                else if(tx_done)
+                begin
+                    # simulation_delay;
+                    
+                    uart_tx_finished_bytes_n_cnt <= (uart_tx_finished_bytes_n_cnt_eq_th_sub1 | tx_bytes_n_th_eq0) ? 16'd0:(uart_tx_finished_bytes_n_cnt + 16'd1);
+                    uart_tx_finished_bytes_n_cnt_eq_th_sub1 <= uart_tx_finished_bytes_n_cnt == tx_bytes_n_th_sub1;
+                end
+            end
+            
+            always @(posedge clk or negedge resetn)
+            begin
+                if(~resetn)
+                    uart_tx_finished_bytes_n_itr_pulse <= 1'b0;
+                else
+                    # simulation_delay uart_tx_finished_bytes_n_itr_pulse <= (uart_itr_en[0] & uart_global_itr_en) &
+                        (uart_tx_finished_bytes_n_cnt_eq_th_sub1 | tx_bytes_n_th_eq0) & tx_done;
+            end
+            
+            reg is_waiting_for_uart_tx_done; // 是否正在等待UART发送完成脉冲
+            reg[15:0] uart_tx_idle_cnt; // UART发送空闲周期数(计数器)
+            reg uart_tx_idle_cnt_eq_th_sub1; // UART发送空闲周期数 == UART发送中断IDLE周期数阈值
+            reg uart_tx_idle_itr_pulse; // UART发送空闲(原始中断脉冲)
+            
+            always @(posedge clk or negedge resetn)
+            begin
+                if(~resetn)
+                    is_waiting_for_uart_tx_done <= 1'b1;
+                else
+                    # simulation_delay is_waiting_for_uart_tx_done <= is_waiting_for_uart_tx_done ? (~tx_done):(uart_tx_idle_cnt_eq_th_sub1 | (~tx_idle));
+            end
+            
+            always @(posedge clk or negedge resetn)
+            begin
+                if(~resetn)
+                begin
+                    uart_tx_idle_cnt <= 16'd0;
+                    uart_tx_idle_cnt_eq_th_sub1 <= 1'b0;
+                end
+                else if((~uart_itr_en[1]) | (~uart_global_itr_en))
+                begin
+                    # simulation_delay;
+                    
+                    uart_tx_idle_cnt <= 16'd0;
+                    uart_tx_idle_cnt_eq_th_sub1 <= 1'b0;
+                end
+                else if(~is_waiting_for_uart_tx_done)
+                begin
+                    # simulation_delay;
+                    
+                    uart_tx_idle_cnt <= (uart_tx_idle_cnt_eq_th_sub1 | (~tx_idle)) ? 16'd0:(uart_tx_idle_cnt + 16'd1);
+                    uart_tx_idle_cnt_eq_th_sub1 <= uart_tx_idle_cnt == tx_idle_n_th;
+                end
+            end
+            
+            always @(posedge clk or negedge resetn)
+            begin
+                if(~resetn)
+                    uart_tx_idle_itr_pulse <= 1'b0;
+                else
+                    # simulation_delay uart_tx_idle_itr_pulse <= (~is_waiting_for_uart_tx_done) & uart_tx_idle_cnt_eq_th_sub1 & tx_idle;
+            end
+            
+            reg[15:0] uart_rx_finished_bytes_n_cnt;
+            reg uart_rx_finished_bytes_n_cnt_eq_th_sub1;
+            reg uart_rx_finished_bytes_n_itr_pulse;
+            
+            always @(posedge clk or negedge resetn)
+            begin
+                if(~resetn)
+                begin
+                    uart_rx_finished_bytes_n_cnt <= 16'd0;
+                    uart_rx_finished_bytes_n_cnt_eq_th_sub1 <= 1'b0;
+                end
+                else if((~uart_itr_en[2]) | (~uart_global_itr_en))
+                begin
+                    # simulation_delay;
+                    
+                    uart_rx_finished_bytes_n_cnt <= 16'd0;
+                    uart_rx_finished_bytes_n_cnt_eq_th_sub1 <= 1'b0;
+                end
+                else if(rx_done)
+                begin
+                    # simulation_delay;
+                    
+                    uart_rx_finished_bytes_n_cnt <= (uart_rx_finished_bytes_n_cnt_eq_th_sub1 | rx_bytes_n_th_eq0) ? 16'd0:(uart_rx_finished_bytes_n_cnt + 16'd1);
+                    uart_rx_finished_bytes_n_cnt_eq_th_sub1 <= uart_rx_finished_bytes_n_cnt == rx_bytes_n_th_sub1;
+               end
+            end
+            
+            always @(posedge clk or negedge resetn)
+            begin
+                if(~resetn)
+                    uart_rx_finished_bytes_n_itr_pulse <= 1'b0;
+                else
+                    # simulation_delay uart_rx_finished_bytes_n_itr_pulse <= (uart_itr_en[2] & uart_global_itr_en) &
+                        (uart_rx_finished_bytes_n_cnt_eq_th_sub1 | rx_bytes_n_th_eq0) & rx_done;
+            end
+            
+            reg is_waiting_for_uart_rx_done;
+            reg[15:0] uart_rx_idle_cnt;
+            reg uart_rx_idle_cnt_eq_th_sub1;
+            reg uart_rx_idle_itr_pulse;
+            
+            always @(posedge clk or negedge resetn)
+            begin
+                if(~resetn)
+                    is_waiting_for_uart_rx_done <= 1'b1;
+                else
+                    # simulation_delay is_waiting_for_uart_rx_done <= is_waiting_for_uart_rx_done ? (~rx_done):(uart_rx_idle_cnt_eq_th_sub1 | rx_start);
+            end
+            
+            always @(posedge clk or negedge resetn)
+            begin
+                if(~resetn)
+                begin
+                    uart_rx_idle_cnt <= 16'd0;
+                    uart_rx_idle_cnt_eq_th_sub1 <= 1'b0;
+                end
+                else if((~uart_itr_en[3]) | (~uart_global_itr_en))
+                begin
+                    # simulation_delay;
+                    
+                    uart_rx_idle_cnt <= 16'd0;
+                    uart_rx_idle_cnt_eq_th_sub1 <= 1'b0;
+                end
+                else if((~is_waiting_for_uart_rx_done) & (rx_start | rx_idle))
+                begin
+                    # simulation_delay;
+                    
+                    uart_rx_idle_cnt <= (uart_rx_idle_cnt_eq_th_sub1 | rx_start) ? 16'd0:(uart_rx_idle_cnt + 16'd1);
+                    uart_rx_idle_cnt_eq_th_sub1 <= rx_start ? 1'b0:(uart_rx_idle_cnt == rx_idle_n_th);
+                end
+            end
+            
+            always @(posedge clk or negedge resetn)
+            begin
+                if(~resetn)
+                    uart_rx_idle_itr_pulse <= 1'b0;
+                else
+                    # simulation_delay uart_rx_idle_itr_pulse <= (~is_waiting_for_uart_rx_done) & uart_rx_idle_cnt_eq_th_sub1 & rx_idle;
+            end
+            
+            reg rx_err_d;
+            reg uart_rx_err_itr_pulse;
+            
+            always @(posedge clk or negedge resetn)
+            begin
+                if(~resetn)
+                    rx_err_d <= 1'b0;
+                else
+                    # simulation_delay rx_err_d <= rx_err;
+            end
+            
+            always @(posedge clk or negedge resetn)
+            begin
+                if(~resetn)
+                    uart_rx_err_itr_pulse <= 1'b0;
+                else if((~uart_itr_en[4]) | (~uart_global_itr_en))
+                    uart_rx_err_itr_pulse <= 1'b0;
+                else
+                    # simulation_delay uart_rx_err_itr_pulse <= rx_err & (~rx_err_d);
+            end
+            
+            assign uart_org_itr_pulse = (uart_rx_err_itr_pulse | uart_rx_idle_itr_pulse |
+                uart_rx_finished_bytes_n_itr_pulse | uart_tx_idle_itr_pulse | uart_tx_finished_bytes_n_itr_pulse)
+                & (~uart_itr_flag);
+            assign uart_itr_mask = {uart_rx_err_itr_pulse, uart_rx_idle_itr_pulse, uart_rx_finished_bytes_n_itr_pulse,
+                uart_tx_idle_itr_pulse, uart_tx_finished_bytes_n_itr_pulse};
+            
+            reg uart_org_itr_pulse_delay;
+            reg[4:0] uart_itr_mask_delay;
+            
+            assign {uart_org_itr_pulse_d, uart_itr_mask_d} = {uart_org_itr_pulse_delay, uart_itr_mask_delay};
+            
+            always @(posedge clk or negedge resetn)
+            begin
+                if(~resetn)
+                begin
+                    uart_org_itr_pulse_delay <= 1'b0;
+                    uart_itr_mask_delay <= 5'd0;
+                end
+                else
+                begin
+                    # simulation_delay;
+                    
+                    uart_org_itr_pulse_delay <= uart_org_itr_pulse;
+                    uart_itr_mask_delay <= uart_itr_mask;
+                end
+            end
+            
+            itr_generator #(
+                .pulse_w(10),
+                .simulation_delay(simulation_delay)
+            )itr_generator_u(
+                .clk(clk),
+                .rst_n(resetn),
+                .itr_org(uart_org_itr_pulse),
+                .itr(uart_itr)
+            );
+        end
+        else
+        begin
+            assign uart_itr = 1'b0;
+            
+            assign {uart_org_itr_pulse, uart_itr_mask} = 6'd0;
+            assign {uart_org_itr_pulse_d, uart_itr_mask_d} = 6'd0;
+        end
+    endgenerate
+    
+    /** UART控制器 **/
+    uart_rx_tx #(
+        .clk_frequency_MHz(clk_frequency_MHz),
+        .baud_rate(baud_rate),
+        .interface("fifo"),
+        .simulation_delay(simulation_delay)
+    )uart_ctrler(
+        .clk(clk),
+        .resetn(resetn),
+        .rx(uart_rx),
+        .tx(uart_tx),
+        .m_axis_rx_byte_data(),
+        .m_axis_rx_byte_valid(),
+        .m_axis_rx_byte_ready(),
+        .rx_buf_fifo_din(rx_fifo_din),
+        .rx_buf_fifo_wen(rx_fifo_wen),
+        .rx_buf_fifo_full(rx_fifo_full),
+        .s_axis_tx_byte_data(),
+        .s_axis_tx_byte_valid(),
+        .s_axis_tx_byte_ready(),
+        .tx_buf_fifo_dout(tx_fifo_dout),
+        .tx_buf_fifo_empty(tx_fifo_empty),
+        .tx_buf_fifo_almost_empty(),
+        .tx_buf_fifo_ren(tx_fifo_ren),
+        .rx_err(rx_err),
+        .tx_idle(tx_idle),
+        .rx_idle(rx_idle),
+        .tx_done(tx_done),
+        .rx_done(rx_done),
+        .rx_start(rx_start)
+    );
+
+    /*
+    寄存器区->
+    偏移量  |    含义                     |   读写特性    |        备注
+    0x00    0:发送fifo是否满                    R
+            1:发送fifo写使能                    W         发送fifo写使能取上升沿
+            9~2:发送fifo写数据                  W
+            10:接收fifo是否空                   R
+            11:接收fifo读使能                   W         接收fifo读使能取上升沿
+            19~12:接收fifo读数据                R
+    0x04    0:UART全局中断使能                  W
+            1:UART发送达到规定字节数中断使能     W
+            2:UART发送IDLE中断使能              W
+            3:UART接收达到规定字节数中断使能     W
+            4:UART接收IDLE中断使能              W
+            5:UART接收FIFO溢出中断使能          W
+            16:UART中断标志                    RWC      请在中断服务函数中清除中断标志
+            21~17:UART中断状态                  R
+    0x08    15~0:UART发送中断字节数阈值         W               注意要减1
+            31~16:UART发送中断IDLE周期数阈值    W               注意要减2
+    0x0A    15~0:UART接收中断字节数阈值         W               注意要减1
+            31~16:UART接收中断IDLE周期数阈值    W               注意要减2
+    */
+    // 控制/状态寄存器
+    reg[31:0] uart_fifo_cs;
+    reg[31:0] uart_itr_status_en;
+    reg[31:0] uart_tx_itr_th;
+    reg[31:0] uart_rx_itr_th;
+    
+    reg[15:0] tx_bytes_n_th_sub1_regs; // UART发送中断字节数阈值-1
+    reg[15:0] rx_bytes_n_th_sub1_regs; // UART接收中断字节数阈值-1
+    reg tx_bytes_n_th_eq0_reg; // UART发送中断字节数阈值等于0(标志)
+    reg rx_bytes_n_th_eq0_reg; // UART接收中断字节数阈值等于0(标志)
+    
+    reg tx_fifo_wen_d;
+    reg rx_fifo_ren_d;
+    
+    assign tx_fifo_wen = uart_fifo_cs[1] & (~tx_fifo_wen_d); // 发送fifo写使能取上升沿
+    assign tx_fifo_din = uart_fifo_cs[9:2];
+    assign rx_fifo_ren = uart_fifo_cs[11] & (~rx_fifo_ren_d); // 接收fifo读使能取上升沿
+    
+    assign {uart_itr_en, uart_global_itr_en} = uart_itr_status_en[5:0];
+    assign uart_itr_flag = uart_itr_status_en[16];
+    assign {tx_idle_n_th, tx_bytes_n_th} = uart_tx_itr_th;
+    assign {rx_idle_n_th, rx_bytes_n_th} = uart_rx_itr_th;
+    
+    assign {tx_bytes_n_th_sub1, rx_bytes_n_th_sub1} = {tx_bytes_n_th_sub1_regs, rx_bytes_n_th_sub1_regs};
+    assign {tx_bytes_n_th_eq0, rx_bytes_n_th_eq0} = {tx_bytes_n_th_eq0_reg, rx_bytes_n_th_eq0_reg};
+    
+    always @(posedge clk or negedge resetn)
+    begin
+        if(~resetn)
+            {tx_fifo_wen_d, rx_fifo_ren_d} <= 2'b00;
+        else
+            # simulation_delay {tx_fifo_wen_d, rx_fifo_ren_d} <= {uart_fifo_cs[1], uart_fifo_cs[11]};
+    end
+    
+    // APB写寄存器
+    always @(posedge clk or negedge resetn)
+    begin
+        if(~resetn)
+        begin
+            {uart_fifo_cs[11], uart_fifo_cs[9:1]} <= {1'b0, 9'd0};
+            {uart_itr_status_en[16], uart_itr_status_en[5:0]} <= {1'b0, 6'd0};
+            uart_tx_itr_th <= {16'd100, 16'd1};
+            uart_rx_itr_th <= {16'd100, 16'd1};
+        end
+        else if(psel & pwrite & penable)
+        begin
+            # simulation_delay;
+            
+            case(paddr[3:2])
+                2'd0: {uart_fifo_cs[11], uart_fifo_cs[9:1]} <= {pwdata[11], pwdata[9:1]}; // 接收fifo读使能, 发送fifo写数据, 发送fifo写使能
+                2'd1: {uart_itr_status_en[16], uart_itr_status_en[5:0]} <= {1'b0, pwdata[5:0]}; // UART总中断标志, UART中断使能
+                2'd2: uart_tx_itr_th <= pwdata; // UART发送中断IDLE周期数阈值, UART发送中断字节数阈值
+                2'd3: uart_rx_itr_th <= pwdata; // UART接收中断IDLE周期数阈值, UART接收中断字节数阈值
+            endcase
+        end
+        else
+        begin
+            # simulation_delay;
+            
+            if(~uart_itr_status_en[16])
+                uart_itr_status_en[16] <= uart_org_itr_pulse; // UART总中断标志
+        end
+    end
+    
+    // UART发送中断字节数阈值-1
+    // UART接收中断字节数阈值-1
+    // UART发送中断字节数阈值等于0(标志)
+    // UART接收中断字节数阈值等于0(标志)
+    always @(posedge clk or negedge resetn)
+    begin
+        if(~resetn)
+        begin
+            tx_bytes_n_th_eq0_reg <= 1'b1;
+            tx_bytes_n_th_sub1_regs <= 16'hffff;
+            rx_bytes_n_th_eq0_reg <= 1'b1;
+            rx_bytes_n_th_sub1_regs <= 16'hffff;
+        end
+        else if(psel & pwrite & penable)
+        begin
+            # simulation_delay;
+            
+            if(paddr[3:2] == 2)
+            begin
+                tx_bytes_n_th_eq0_reg <= pwdata[15:0] == 16'd0;
+                tx_bytes_n_th_sub1_regs <= pwdata[15:0] - 16'd1;
+            end
+            
+            if(paddr[3:2] == 3)
+            begin
+                rx_bytes_n_th_eq0_reg <= pwdata[15:0] == 16'd0;
+                rx_bytes_n_th_sub1_regs <= pwdata[15:0] - 16'd1;
+            end
+        end
+    end
+    
+    // 子中断标志向量
+    always @(posedge clk)
+    begin
+        if(uart_org_itr_pulse_d)
+            # simulation_delay uart_itr_status_en[21:17] <= uart_itr_mask_d; // UART子中断标志
+    end
+    
+    // APB读寄存器
+    reg[31:0] prdata_out_regs;
+    
+    generate
+		if(simulation_delay == 0)
+		begin
+			always @(posedge clk)
+			begin
+				if(psel & (~pwrite))
+				begin
+					# simulation_delay;
+					
+					case(paddr[3:2])
+						2'd0:
+						begin
+							prdata_out_regs[0] <= tx_fifo_full; // 发送fifo是否满
+							prdata_out_regs[10] <= rx_fifo_empty; // 接收fifo是否空
+							prdata_out_regs[19:12] <= rx_fifo_dout; // 接收fifo读数据
+							{prdata_out_regs[31:20], prdata_out_regs[11], prdata_out_regs[9:1]} <= 22'dx;
+						end
+						2'd1:
+						begin
+							prdata_out_regs[21:16] <= uart_itr_status_en[21:16];
+							{prdata_out_regs[31:22], prdata_out_regs[15:0]} <= 26'dx;
+						end
+						default: prdata_out_regs <= 32'dx;
+					endcase
+				end
+			end
+		end
+		else
+		begin
+			always @(posedge clk)
+			begin
+				if(psel & (~pwrite))
+				begin
+					# simulation_delay;
+					
+					case(paddr[3:2])
+						2'd0:
+						begin
+							prdata_out_regs[0] <= tx_fifo_full; // 发送fifo是否满
+							prdata_out_regs[10] <= rx_fifo_empty; // 接收fifo是否空
+							prdata_out_regs[19:12] <= rx_fifo_dout; // 接收fifo读数据
+							{prdata_out_regs[31:20], prdata_out_regs[11], prdata_out_regs[9:1]} <= 22'd0;
+						end
+						2'd1:
+						begin
+							prdata_out_regs[21:16] <= uart_itr_status_en[21:16];
+							{prdata_out_regs[31:22], prdata_out_regs[15:0]} <= 26'd0;
+						end
+						default: prdata_out_regs <= 32'd0;
+					endcase
+				end
+			end
+		end
+	endgenerate
+    
+    /** APB从机接口 **/
+    assign pready_out = 1'b1;
+    assign prdata_out = prdata_out_regs;
+    assign pslverr_out = 1'b0;
+
+endmodule

CutestPanda_Opensoc/101_apb_uart/rtl/bram_simple_dual_port.v

@@ -0,0 +1,132 @@
+/*
+MIT License
+
+Copyright (c) 2024 Panda, 2257691535@qq.com
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+*/
+
+`timescale 1ns / 1ps
+/********************************************************************
+本模块: 简单双端口Bram
+
+描述: 
+可选读延迟1clk或2clk
+
+注意：
+无
+
+协议:
+MEM READ/WRITE
+
+作者: 陈家耀
+日期: 2022/1/11
+********************************************************************/
+
+
+module bram_simple_dual_port #(
+    parameter style = "HIGH_PERFORMANCE", // 存储器样式(HIGH_PERFORMANCE|LOW_LATENCY)
+    parameter integer mem_width = 32, // 存储器位宽
+    parameter integer mem_depth = 4096, // 存储器深度
+    parameter INIT_FILE = "no_init", // 初始化文件路径
+    parameter integer simulation_delay = 1 // 仿真延时
+)
+(
+    // clk
+    input wire clk,
+    
+    // mem write
+    input wire wen_a,
+    input wire[clogb2(mem_depth-1):0] addr_a,
+    input wire[mem_width-1:0] din_a,
+    
+    // mem read
+    input wire ren_b,
+    input wire[clogb2(mem_depth-1):0] addr_b,
+    output wire[mem_width-1:0] dout_b
+);
+
+    // 计算bit_depth的最高有效位编号(即位数-1)             
+    function integer clogb2 (input integer bit_depth);              
+    begin                                                           
+        for(clogb2=-1; bit_depth>0; clogb2=clogb2+1)                   
+          bit_depth = bit_depth >> 1;                                 
+        end                                        
+    endfunction
+    
+    (* ram_style="block" *) reg[mem_width-1:0] mem[mem_depth-1:0]; // 存储器
+    reg[mem_width-1:0] ram_data_b;
+    
+    generate
+        if (INIT_FILE != "")
+        begin
+            if(INIT_FILE == "default")
+            begin
+                integer ram_index;
+                initial
+                for (ram_index = 0; ram_index < mem_depth; ram_index = ram_index + 1)
+                    mem[ram_index] = ram_index;
+            end
+            else if(INIT_FILE != "no_init")
+            begin
+                initial
+                    $readmemh(INIT_FILE, mem, 0, mem_depth - 1);
+            end
+        end
+        else
+        begin
+            integer ram_index;
+            initial
+            for (ram_index = 0; ram_index < mem_depth; ram_index = ram_index + 1)
+                mem[ram_index] = {mem_width{1'b0}};
+        end
+    endgenerate
+    
+    // 读写控制逻辑
+    always @(posedge clk)
+    begin
+        if(wen_a)
+            # simulation_delay mem[addr_a] <= din_a;
+    end
+    
+    always @(posedge clk)
+    begin
+        if(ren_b)
+            # simulation_delay ram_data_b <= mem[addr_b];
+    end
+    
+    generate
+        if(style == "HIGH_PERFORMANCE")
+        begin
+            // 使用输出寄存器
+            reg[mem_width-1:0] data_b;
+            
+            assign dout_b = data_b;
+            
+            always @(posedge clk)
+                #simulation_delay data_b <= ram_data_b;
+        end
+        else
+        begin
+            // 不使用输出寄存器
+            assign dout_b = ram_data_b;
+        end
+    endgenerate
+    
+endmodule

CutestPanda_Opensoc/101_apb_uart/rtl/dram_simple_dual_port.v

@@ -0,0 +1,129 @@
+/*
+MIT License
+
+Copyright (c) 2024 Panda, 2257691535@qq.com
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+*/
+
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// 项目: 简单双端口Dram
+/* 
+描述: 
+可选的输出寄存器
+*/
+/*
+注意：
+无
+*/
+// 作者: 陈家耀
+// 日期: 2022/1/13
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module dram_simple_dual_port #(
+    parameter integer mem_width = 24, // 存储器位宽
+    parameter integer mem_depth = 32, // 存储器深度
+    parameter INIT_FILE = "no_init", // 初始化文件路径
+    parameter use_output_register = "true", // 是否使用输出寄存器
+    parameter output_register_init_v = 0, // 输出寄存器复位值
+    parameter real simulation_delay = 10 // 仿真时用的延时
+)(
+    // 时钟和复位
+    input wire clk,
+    input wire rst_n,
+    
+    // mem
+    // write port
+    input wire wen_a,
+    input wire[clogb2(mem_depth-1):0] addr_a,
+    input wire[mem_width-1:0] din_a,
+    // read port
+    input wire ren_b,
+    input wire[clogb2(mem_depth-1):0] addr_b,
+    output wire[mem_width-1:0] dout_b
+);
+
+    // 计算bit_depth的最高有效位编号(即位数-1)
+    function integer clogb2 (input integer bit_depth);
+        integer temp;
+    begin
+        temp = bit_depth;
+        for(clogb2 = -1;temp > 0;clogb2 = clogb2 + 1)                   
+            temp = temp >> 1;                                 
+        end                                        
+    endfunction
+    
+    (* ram_style="distributed" *) reg[mem_width-1:0] mem[mem_depth-1:0]; // 存储器
+    
+    generate
+    if (INIT_FILE != "")
+    begin
+        if(INIT_FILE != "no_init")
+        begin
+            initial
+                $readmemh(INIT_FILE, mem, 0, mem_depth - 1);
+        end
+    end
+    else
+    begin
+        integer ram_index;
+        initial
+        for (ram_index = 0; ram_index < mem_depth; ram_index = ram_index + 1)
+            mem[ram_index] = {mem_width{1'b0}};
+    end
+    endgenerate
+    
+    // 读写控制逻辑
+    generate
+        if(use_output_register == "true")
+        begin
+            reg[mem_width-1:0] dout_b_regs;
+            
+            assign dout_b = dout_b_regs;
+            
+            always @(posedge clk)
+            begin
+                if(wen_a)
+                    # simulation_delay mem[addr_a] <= din_a;
+            end
+            
+            always @(posedge clk or negedge rst_n)
+            begin
+                if(~rst_n)
+                    dout_b_regs <= output_register_init_v;
+                else if(ren_b)
+                    # simulation_delay dout_b_regs <= mem[addr_b];
+            end
+        end
+        else
+        begin
+            always @(posedge clk)
+            begin
+                # simulation_delay;
+                if(wen_a)
+                    mem[addr_a] <= din_a;
+            end
+            
+            assign dout_b = mem[addr_b];
+        end
+    endgenerate
+
+endmodule

CutestPanda_Opensoc/101_apb_uart/rtl/fifo_base_on_ram.v

@@ -0,0 +1,200 @@
+/*
+MIT License
+
+Copyright (c) 2024 Panda, 2257691535@qq.com
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+*/
+
+`timescale 1ns / 1ps
+/********************************************************************
+本模块: 基于ram的同步fifo控制器
+
+描述: 
+全流水的高性能同步fifo控制器
+基于ram
+支持first word fall through特性(READ LA = 0)
+可选的固定阈值将满/将空信号
+
+注意：
+将满信号当存储计数 >= almost_full_th时有效
+将空信号当存储计数 <= almost_empty_th时有效
+almost_full_th和almost_empty_th必须在[1, fifo_depth-1]范围内
+不使能FWFT时, 要求ram的读延迟=1或2clk; 使能FWFT时, 要求ram的读延迟=1clk
+
+协议:
+FIFO WRITE/READ
+MEM WRITE/READ
+
+作者: 陈家耀
+日期: 2023/10/29
+********************************************************************/
+
+
+module fifo_based_on_ram #(
+    parameter fwft_mode = "true", // 是否启用first word fall through特性
+    parameter ram_read_la = 1, // ram读延迟(1|2)(仅在不使能FWFT时可用)
+    parameter integer fifo_depth = 32, // fifo深度(必须为2|4|8|16|...)
+    parameter integer fifo_data_width = 32, // fifo位宽
+    parameter integer almost_full_th = 20, // fifo将满阈值
+    parameter integer almost_empty_th = 5, // fifo将空阈值
+    parameter real simulation_delay = 1 // 仿真延时
+)(
+    // 时钟和复位
+    input wire clk,
+    input wire rst_n,
+    
+    // FIFO WRITE(fifo写端口)
+    input wire fifo_wen,
+    input wire[fifo_data_width-1:0] fifo_din,
+    output wire fifo_full,
+    output wire fifo_full_n,
+    output wire fifo_almost_full,
+    output wire fifo_almost_full_n,
+    
+    // FIFO READ(fifo读端口)
+    input wire fifo_ren,
+    output wire[fifo_data_width-1:0] fifo_dout,
+    output wire fifo_empty,
+    output wire fifo_empty_n,
+    output wire fifo_almost_empty,
+    output wire fifo_almost_empty_n,
+    
+    // MEM WRITE(ram写端口)
+    output wire ram_wen,
+    output wire[clogb2(fifo_depth-1):0] ram_w_addr,
+    output wire[fifo_data_width-1:0] ram_din,
+    
+    // MEM RAD(ram读端口)
+    output wire ram_ren,
+    output wire[clogb2(fifo_depth-1):0] ram_r_addr,
+    input wire[fifo_data_width-1:0] ram_dout,
+    
+    // 存储计数
+    output wire[clogb2(fifo_depth):0] data_cnt
+);
+
+    // 计算log2(bit_depth)               
+    function integer clogb2 (input integer bit_depth);
+        integer temp;
+    begin
+        temp = bit_depth;
+        for(clogb2 = -1;temp > 0;clogb2 = clogb2 + 1)                   
+            temp = temp >> 1;                                 
+    end                                        
+    endfunction
+    
+    /** 主fifo **/
+    wire m_fifo_ren;
+    wire[fifo_data_width-1:0] m_fifo_dout;
+    wire m_fifo_empty_n;
+    
+    generate
+        if(fwft_mode == "true")
+        begin
+            // FWFT模式
+            fifo_based_on_ram_std #(
+                .fifo_depth(fifo_depth),
+                .fifo_data_width(fifo_data_width),
+                .almost_full_th(almost_full_th),
+                .almost_empty_th(almost_empty_th),
+                .simulation_delay(simulation_delay)
+            )fifo_based_on_ram_std_u(
+                .clk(clk),
+                .rst_n(rst_n),
+                .fifo_wen(fifo_wen),
+                .fifo_din(fifo_din),
+                .fifo_full(fifo_full),
+                .fifo_full_n(fifo_full_n),
+                .fifo_almost_full(fifo_almost_full),
+                .fifo_almost_full_n(fifo_almost_full_n),
+                .fifo_ren(m_fifo_ren),
+                .fifo_dout(m_fifo_dout),
+                .fifo_empty(),
+                .fifo_empty_n(m_fifo_empty_n),
+                .fifo_almost_empty(fifo_almost_empty),
+                .fifo_almost_empty_n(fifo_almost_empty_n),
+                .ram_wen(ram_wen),
+                .ram_w_addr(ram_w_addr),
+                .ram_din(ram_din),
+                .ram_ren(ram_ren),
+                .ram_r_addr(ram_r_addr),
+                .ram_dout(ram_dout),
+                .data_cnt(data_cnt)
+            );
+        end
+        else
+        begin
+            // 标准模式
+            fifo_based_on_ram_std #(
+                .fifo_depth(fifo_depth),
+                .fifo_data_width(fifo_data_width),
+                .almost_full_th(almost_full_th),
+                .almost_empty_th(almost_empty_th),
+                .simulation_delay(simulation_delay)
+            )fifo_based_on_ram_std_u(
+                .clk(clk),
+                .rst_n(rst_n),
+                .fifo_wen(fifo_wen),
+                .fifo_din(fifo_din),
+                .fifo_full(fifo_full),
+                .fifo_full_n(fifo_full_n),
+                .fifo_almost_full(fifo_almost_full),
+                .fifo_almost_full_n(fifo_almost_full_n),
+                .fifo_ren(fifo_ren),
+                .fifo_dout(fifo_dout),
+                .fifo_empty(fifo_empty),
+                .fifo_empty_n(fifo_empty_n),
+                .fifo_almost_empty(fifo_almost_empty),
+                .fifo_almost_empty_n(fifo_almost_empty_n),
+                .ram_wen(ram_wen),
+                .ram_w_addr(ram_w_addr),
+                .ram_din(ram_din),
+                .ram_ren(ram_ren),
+                .ram_r_addr(ram_r_addr),
+                .ram_dout(ram_dout),
+                .data_cnt(data_cnt)
+            );
+        end
+    endgenerate
+    
+    /** 从fifo(仅FWFT模式下需要) **/
+    generate
+        if(fwft_mode == "true")
+        begin
+            fifo_show_ahead_buffer #(
+                .fifo_data_width(fifo_data_width),
+                .simulation_delay(simulation_delay)
+            )fifo_show_ahead_buffer_u(
+                .clk(clk),
+                .rst_n(rst_n),
+                
+                .std_fifo_ren(m_fifo_ren),
+                .std_fifo_dout(m_fifo_dout),
+                .std_fifo_empty(~m_fifo_empty_n),
+                
+                .fwft_fifo_ren(fifo_ren),
+                .fwft_fifo_dout(fifo_dout),
+                .fwft_fifo_empty(fifo_empty),
+                .fwft_fifo_empty_n(fifo_empty_n)
+            );
+        end
+    endgenerate
+    
+endmodule

CutestPanda_Opensoc/101_apb_uart/rtl/fifo_based_on_lutram.v

@@ -0,0 +1,235 @@
+/*
+MIT License
+
+Copyright (c) 2024 Panda, 2257691535@qq.com
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+*/
+
+`timescale 1ns / 1ps
+/********************************************************************
+本模块: 基于lutram的同步fifo
+
+描述: 
+全流水的高性能同步fifo
+基于lutram
+支持first word fall through特性(READ LA = 0)
+可选的固定阈值将满/将空信号
+
+注意：
+将满信号当存储计数 >= almost_full_th时有效
+将空信号当存储计数 <= almost_empty_th时有效
+almost_full_th和almost_empty_th必须在[1, fifo_depth-1]范围内
+
+协议:
+FIFO WRITE/READ
+
+作者: 陈家耀
+日期: 2023/10/13
+********************************************************************/
+
+
+module fifo_based_on_lutram #(
+    parameter fwft_mode = "true", // 是否启用first word fall through特性
+    parameter integer fifo_depth = 32, // fifo深度(必须为2|4|8|16|...)
+    parameter integer fifo_data_width = 32, // fifo位宽
+    parameter integer almost_full_th = 20, // fifo将满阈值
+    parameter integer almost_empty_th = 5, // fifo将空阈值
+    parameter real simulation_delay = 1 // 仿真延时
+)(
+    // 时钟和复位
+    input wire clk,
+    input wire rst_n,
+    
+    // FIFO WRITE(fifo写端口)
+    input wire fifo_wen,
+    input wire[fifo_data_width-1:0] fifo_din,
+    output wire fifo_full,
+    output wire fifo_full_n,
+    output wire fifo_almost_full,
+    output wire fifo_almost_full_n,
+    
+    // FIFO READ(fifo读端口)
+    input wire fifo_ren,
+    output wire[fifo_data_width-1:0] fifo_dout,
+    output wire fifo_empty,
+    output wire fifo_empty_n,
+    output wire fifo_almost_empty,
+    output wire fifo_almost_empty_n,
+    
+    // 存储计数
+    output wire[clogb2(fifo_depth):0] data_cnt
+);
+
+    // 计算log2(bit_depth)               
+    function integer clogb2 (input integer bit_depth);
+        integer temp;
+    begin
+        temp = bit_depth;
+        for(clogb2 = -1;temp > 0;clogb2 = clogb2 + 1)                   
+            temp = temp >> 1;                                 
+    end                                        
+    endfunction
+    
+    /** 参数 **/
+    localparam integer use_cnt_th = 8;
+    
+    /** 空满标志和存储计数 **/
+    reg fifo_empty_reg;
+    reg fifo_full_reg;
+    reg fifo_almost_empty_reg;
+    reg fifo_almost_full_reg;
+    reg fifo_empty_n_reg;
+    reg fifo_full_n_reg;
+    reg fifo_almost_empty_n_reg;
+    reg fifo_almost_full_n_reg;
+    reg[clogb2(fifo_depth):0] data_cnt_regs;
+    reg[fifo_depth:0] data_cnt_onehot_regs;
+    
+    assign {fifo_empty, fifo_full} = {fifo_empty_reg, fifo_full_reg};
+    assign {fifo_empty_n, fifo_full_n} = {fifo_empty_n_reg, fifo_full_n_reg};
+    assign {fifo_almost_empty, fifo_almost_full} = {fifo_almost_empty_reg, fifo_almost_full_reg};
+    assign {fifo_almost_empty_n, fifo_almost_full_n} = {fifo_almost_empty_n_reg, fifo_almost_full_n_reg};
+    assign data_cnt = data_cnt_regs;
+    
+    always @(posedge clk or negedge rst_n)
+    begin
+        if(~rst_n)
+        begin
+            fifo_empty_reg <= 1'b1;
+            fifo_empty_n_reg <= 1'b0;
+            fifo_full_reg <= 1'b0;
+            fifo_full_n_reg <= 1'b1;
+            fifo_almost_empty_reg <= 1'b1;
+            fifo_almost_empty_n_reg <= 1'b0;
+            fifo_almost_full_reg <= 1'b0;
+            fifo_almost_full_n_reg <= 1'b1;
+            
+            data_cnt_regs <= 0;
+            data_cnt_onehot_regs <= 1;
+        end
+        else if((fifo_wen & fifo_full_n_reg) ^ (fifo_ren & fifo_empty_n_reg))
+		begin
+            # simulation_delay;
+			
+            if(fifo_wen & fifo_full_n_reg)
+            begin
+                // fifo数据增加1个
+                fifo_empty_reg <= 1'b0;
+                fifo_empty_n_reg <= 1'b1;
+                fifo_full_reg <= (fifo_depth >= use_cnt_th) ? data_cnt_regs == fifo_depth - 1:data_cnt_onehot_regs[fifo_depth-1];
+                fifo_full_n_reg <= (fifo_depth >= use_cnt_th) ? data_cnt_regs != fifo_depth - 1:(~data_cnt_onehot_regs[fifo_depth-1]);
+                fifo_almost_empty_reg <= (data_cnt_regs <= almost_empty_th - 1);
+                fifo_almost_empty_n_reg <= ~(data_cnt_regs <= almost_empty_th - 1);
+                fifo_almost_full_reg <= (data_cnt_regs >= almost_full_th - 1);
+                fifo_almost_full_n_reg <= ~(data_cnt_regs >= almost_full_th - 1);
+                
+                data_cnt_regs <= data_cnt_regs + 1;
+                data_cnt_onehot_regs <= {data_cnt_onehot_regs[fifo_depth-1:0], 1'b0}; // 左移
+            end
+            else
+            begin
+                // fifo数据减少1个
+                fifo_empty_reg <= (fifo_depth >= use_cnt_th) ? data_cnt_regs == 1:data_cnt_onehot_regs[1];
+                fifo_empty_n_reg <= (fifo_depth >= use_cnt_th) ? data_cnt_regs != 1:(~data_cnt_onehot_regs[1]);
+                fifo_full_reg <= 1'b0;
+                fifo_full_n_reg <= 1'b1;
+                fifo_almost_empty_reg <= (data_cnt_regs <= almost_empty_th + 1);
+                fifo_almost_empty_n_reg <= ~(data_cnt_regs <= almost_empty_th + 1);
+                fifo_almost_full_reg <= (data_cnt_regs >= almost_full_th + 1);
+                fifo_almost_full_n_reg <= ~(data_cnt_regs >= almost_full_th + 1);
+                
+                data_cnt_regs <= data_cnt_regs - 1;
+                data_cnt_onehot_regs <= {1'b0, data_cnt_onehot_regs[fifo_depth:1]}; // 右移
+            end
+        end
+    end
+    
+    /** 读写指针 **/
+    reg[clogb2(fifo_depth-1):0] fifo_rptr;
+    reg[clogb2(fifo_depth-1):0] fifo_rptr_add1;
+    reg[clogb2(fifo_depth-1):0] fifo_wptr;
+    reg[fifo_depth-1:0] fifo_wptr_onehot;
+    
+    always @(posedge clk or negedge rst_n)
+    begin
+        if(~rst_n)
+            fifo_rptr <= 0;
+        else if(fifo_ren & fifo_empty_n_reg)
+            #simulation_delay fifo_rptr <= fifo_rptr + 1;
+    end
+    
+    always @(posedge clk or negedge rst_n)
+    begin
+        if(~rst_n)
+            fifo_rptr_add1 <= 1;
+        else if(fifo_ren & fifo_empty_n_reg)
+            #simulation_delay fifo_rptr_add1 <= fifo_rptr_add1 + 1;
+    end
+    
+    always @(posedge clk or negedge rst_n)
+    begin
+        if(~rst_n)
+            fifo_wptr <= 0;
+        else if(fifo_wen & fifo_full_n_reg)
+            #simulation_delay fifo_wptr <= fifo_wptr + 1;
+    end
+    
+    always @(posedge clk or negedge rst_n)
+    begin
+        if(~rst_n)
+            fifo_wptr_onehot <= 1;
+        else if(fifo_wen & fifo_full_n_reg)
+            #simulation_delay fifo_wptr_onehot <= {fifo_wptr_onehot[fifo_depth-2:0], fifo_wptr_onehot[fifo_depth-1]}; // 循环左移
+    end
+    
+    /** 读写数据 **/
+    (* ram_style="distributed" *) reg[fifo_data_width-1:0] fifo_regs[fifo_depth-1:0];
+    reg[fifo_data_width-1:0] fifo_dout_regs;
+    
+    assign fifo_dout = fifo_dout_regs;
+    
+    always @(posedge clk)
+    begin
+        if(fifo_wen & fifo_full_n_reg)
+            #simulation_delay fifo_regs[fifo_wptr] <= fifo_din;
+    end
+    
+    generate
+        if(fwft_mode == "true")
+        begin
+            always @(posedge clk)
+            begin
+                if({fifo_empty_n_reg, fifo_ren} != 2'b10)
+                    #simulation_delay fifo_dout_regs <= fifo_empty_n_reg & (~(fifo_wen & ((fifo_depth >= use_cnt_th) ? data_cnt_regs == 1:data_cnt_onehot_regs[1]))) ?
+                        fifo_regs[fifo_rptr_add1]:fifo_din;
+            end
+        end
+        else
+        begin
+            always @(posedge clk)
+            begin
+                if(fifo_ren & fifo_empty_n_reg)
+                    #simulation_delay fifo_dout_regs <= fifo_regs[fifo_rptr];
+            end
+        end
+    endgenerate
+
+endmodule
+

CutestPanda_Opensoc/101_apb_uart/rtl/fifo_based_on_ram_std.v

@@ -0,0 +1,223 @@
+/*
+MIT License
+
+Copyright (c) 2024 Panda, 2257691535@qq.com
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+*/
+
+`timescale 1ns / 1ps
+/********************************************************************
+本模块: 基于ram的标准同步fifo控制器
+
+描述: 
+全流水的高性能同步fifo控制器
+基于ram
+标准fifo(READ LA = 1|2)
+可选的固定阈值将满/将空信号
+
+注意：
+将满信号当存储计数 >= almost_full_th时有效
+将空信号当存储计数 <= almost_empty_th时有效
+almost_full_th和almost_empty_th必须在[1, fifo_depth-1]范围内
+要求ram的读延迟=1clk
+
+协议:
+FIFO WRITE/READ
+MEM WRITE/READ
+
+作者: 陈家耀
+日期: 2023/10/29
+********************************************************************/
+
+
+module fifo_based_on_ram_std #(
+    parameter integer fifo_depth = 32, // fifo深度(必须为2|4|8|16|...)
+    parameter integer fifo_data_width = 32, // fifo位宽
+    parameter integer almost_full_th = 20, // fifo将满阈值
+    parameter integer almost_empty_th = 5, // fifo将空阈值
+    parameter real simulation_delay = 1 // 仿真延时
+)(
+    // 时钟和复位
+    input wire clk,
+    input wire rst_n,
+    
+    // FIFO WRITE(fifo写端口)
+    input wire fifo_wen,
+    input wire[fifo_data_width-1:0] fifo_din,
+    output wire fifo_full,
+    output wire fifo_full_n,
+    output wire fifo_almost_full,
+    output wire fifo_almost_full_n,
+    
+    // FIFO READ(fifo读端口)
+    input wire fifo_ren,
+    output wire[fifo_data_width-1:0] fifo_dout,
+    output wire fifo_empty,
+    output wire fifo_empty_n,
+    output wire fifo_almost_empty,
+    output wire fifo_almost_empty_n,
+    
+    // MEM WRITE(ram写端口)
+    output wire ram_wen,
+    output wire[clogb2(fifo_depth-1):0] ram_w_addr,
+    output wire[fifo_data_width-1:0] ram_din,
+    
+    // MEM RAD(ram读端口)
+    output wire ram_ren,
+    output wire[clogb2(fifo_depth-1):0] ram_r_addr,
+    input wire[fifo_data_width-1:0] ram_dout,
+    
+    // 存储计数
+    output wire[clogb2(fifo_depth):0] data_cnt
+);
+
+    // 计算log2(bit_depth)               
+    function integer clogb2 (input integer bit_depth);
+        integer temp;
+    begin
+        temp = bit_depth;
+        for(clogb2 = -1;temp > 0;clogb2 = clogb2 + 1)                   
+            temp = temp >> 1;                                 
+    end                                        
+    endfunction
+    
+    /** 参数 **/
+    localparam integer use_cnt_th = 8;
+    
+    /** 空满标志和存储计数 **/
+    reg fifo_empty_reg;
+    reg fifo_full_reg;
+    reg fifo_almost_empty_reg;
+    reg fifo_almost_full_reg;
+    reg fifo_empty_n_reg;
+    reg fifo_full_n_reg;
+    reg fifo_almost_empty_n_reg;
+    reg fifo_almost_full_n_reg;
+    reg[clogb2(fifo_depth):0] data_cnt_regs;
+    reg[fifo_depth:0] data_cnt_onehot_regs;
+    
+    assign {fifo_empty, fifo_full} = {fifo_empty_reg, fifo_full_reg};
+    assign {fifo_empty_n, fifo_full_n} = {fifo_empty_n_reg, fifo_full_n_reg};
+    assign {fifo_almost_empty, fifo_almost_full} = {fifo_almost_empty_reg, fifo_almost_full_reg};
+    assign {fifo_almost_empty_n, fifo_almost_full_n} = {fifo_almost_empty_n_reg, fifo_almost_full_n_reg};
+    assign data_cnt = data_cnt_regs;
+    
+    always @(posedge clk or negedge rst_n)
+    begin
+        if(~rst_n)
+        begin
+            fifo_empty_reg <= 1'b1;
+            fifo_empty_n_reg <= 1'b0;
+            fifo_full_reg <= 1'b0;
+            fifo_full_n_reg <= 1'b1;
+            fifo_almost_empty_reg <= 1'b1;
+            fifo_almost_empty_n_reg <= 1'b0;
+            fifo_almost_full_reg <= 1'b0;
+            fifo_almost_full_n_reg <= 1'b1;
+            
+            data_cnt_regs <= 0;
+            data_cnt_onehot_regs <= 1;
+        end
+        else if((fifo_wen & fifo_full_n_reg) ^ (fifo_ren & fifo_empty_n_reg))
+		begin
+            # simulation_delay;
+			
+            if(fifo_wen & fifo_full_n_reg)
+            begin
+                // fifo数据增加1个
+                fifo_empty_reg <= 1'b0;
+                fifo_empty_n_reg <= 1'b1;
+                fifo_full_reg <= (fifo_depth >= use_cnt_th) ? data_cnt_regs == fifo_depth - 1:data_cnt_onehot_regs[fifo_depth-1];
+                fifo_full_n_reg <= (fifo_depth >= use_cnt_th) ? data_cnt_regs != fifo_depth - 1:(~data_cnt_onehot_regs[fifo_depth-1]);
+                fifo_almost_empty_reg <= (data_cnt_regs <= almost_empty_th - 1);
+                fifo_almost_empty_n_reg <= ~(data_cnt_regs <= almost_empty_th - 1);
+                fifo_almost_full_reg <= (data_cnt_regs >= almost_full_th - 1);
+                fifo_almost_full_n_reg <= ~(data_cnt_regs >= almost_full_th - 1);
+                
+                data_cnt_regs <= data_cnt_regs + 1;
+                data_cnt_onehot_regs <= {data_cnt_onehot_regs[fifo_depth-1:0], 1'b0}; // 左移
+            end
+            else
+            begin
+                // fifo数据减少1个
+                fifo_empty_reg <= (fifo_depth >= use_cnt_th) ? data_cnt_regs == 1:data_cnt_onehot_regs[1];
+                fifo_empty_n_reg <= (fifo_depth >= use_cnt_th) ? data_cnt_regs != 1:(~data_cnt_onehot_regs[1]);
+                fifo_full_reg <= 1'b0;
+                fifo_full_n_reg <= 1'b1;
+                fifo_almost_empty_reg <= (data_cnt_regs <= almost_empty_th + 1);
+                fifo_almost_empty_n_reg <= ~(data_cnt_regs <= almost_empty_th + 1);
+                fifo_almost_full_reg <= (data_cnt_regs >= almost_full_th + 1);
+                fifo_almost_full_n_reg <= ~(data_cnt_regs >= almost_full_th + 1);
+                
+                data_cnt_regs <= data_cnt_regs - 1;
+                data_cnt_onehot_regs <= {1'b0, data_cnt_onehot_regs[fifo_depth:1]}; // 右移
+            end
+        end
+    end
+    
+    /** 读写指针 **/
+    reg[clogb2(fifo_depth-1):0] fifo_rptr;
+    reg[clogb2(fifo_depth-1):0] fifo_rptr_add1;
+    reg[clogb2(fifo_depth-1):0] fifo_wptr;
+    reg[fifo_depth-1:0] fifo_wptr_onehot;
+    
+    always @(posedge clk or negedge rst_n)
+    begin
+        if(~rst_n)
+            fifo_rptr <= 0;
+        else if(fifo_ren & fifo_empty_n_reg)
+            #simulation_delay fifo_rptr <= fifo_rptr + 1;
+    end
+    
+    always @(posedge clk or negedge rst_n)
+    begin
+        if(~rst_n)
+            fifo_rptr_add1 <= 1;
+        else if(fifo_ren & fifo_empty_n_reg)
+            #simulation_delay fifo_rptr_add1 <= fifo_rptr_add1 + 1;
+    end
+    
+    always @(posedge clk or negedge rst_n)
+    begin
+        if(~rst_n)
+            fifo_wptr <= 0;
+        else if(fifo_wen & fifo_full_n_reg)
+            #simulation_delay fifo_wptr <= fifo_wptr + 1;
+    end
+    
+    always @(posedge clk or negedge rst_n)
+    begin
+        if(~rst_n)
+            fifo_wptr_onehot <= 1;
+        else if(fifo_wen & fifo_full_n_reg)
+            #simulation_delay fifo_wptr_onehot <= {fifo_wptr_onehot[fifo_depth-2:0], fifo_wptr_onehot[fifo_depth-1]}; // 循环左移
+    end
+    
+    /** 读写数据 **/
+    assign ram_wen = fifo_wen & fifo_full_n_reg;
+    assign ram_w_addr = fifo_wptr;
+    assign ram_din = fifo_din;
+    
+    assign ram_ren = fifo_ren & fifo_empty_n_reg;
+    assign ram_r_addr = fifo_rptr;
+    assign fifo_dout = ram_dout;
+    
+endmodule
+

CutestPanda_Opensoc/101_apb_uart/rtl/fifo_show_ahead_buffer.v

@@ -0,0 +1,122 @@
+/*
+MIT License
+
+Copyright (c) 2024 Panda, 2257691535@qq.com
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+*/
+
+`timescale 1ns / 1ps
+/********************************************************************
+本模块: fifo FWFT缓冲区
+
+描述: 
+用于将读延迟为1clk的fifo转换为FWFT的fifo
+
+注意：
+无
+
+协议:
+FIFO READ
+
+作者: 陈家耀
+日期: 2024/05/30
+********************************************************************/
+
+
+module fifo_show_ahead_buffer #(
+    parameter integer fifo_data_width = 32, // fifo位宽
+    parameter real simulation_delay = 1 // 仿真延时
+)(
+    // 时钟和复位
+    input wire clk,
+    input wire rst_n,
+    
+    // 标准fifo的读端口
+    output wire std_fifo_ren,
+    input wire[fifo_data_width-1:0] std_fifo_dout,
+    input wire std_fifo_empty,
+    
+    // FWFT fifo的读端口
+    input wire fwft_fifo_ren,
+    output wire[fifo_data_width-1:0] fwft_fifo_dout,
+    output wire fwft_fifo_empty,
+    output wire fwft_fifo_empty_n
+);
+    
+    /** 寄存器buffer **/
+    reg std_fifo_rvld; // 标准fifo有效读(指示)
+    reg[fifo_data_width-1:0] regs_buffer[1:0]; // 寄存器buffer
+    reg[2:0] buffer_data_cnt; // buffer存储计数(3'b001 -> 0, 3'b010 -> 1, 3'b100 -> 2)
+    wire[2:0] buffer_data_cnt_sub1; // buffer存储计数 - 1(3'b001 -> 0, 3'b010 -> 1, 3'b100 -> 2)
+    
+    assign buffer_data_cnt_sub1 = {buffer_data_cnt[0], buffer_data_cnt[2:1]};
+    
+    // 标准fifo有效读(指示)
+    always @(posedge clk or negedge rst_n)
+    begin
+        if(~rst_n)
+            std_fifo_rvld <= 1'b0;
+        else
+            # simulation_delay std_fifo_rvld <= std_fifo_ren & (~std_fifo_empty);
+    end
+    
+    // 寄存器buffer
+    always @(posedge clk)
+    begin
+        if(std_fifo_rvld & ((fwft_fifo_ren & fwft_fifo_empty_n) ? buffer_data_cnt_sub1[0]:buffer_data_cnt[0]))
+            # simulation_delay regs_buffer[0] <= std_fifo_dout;
+        else if(fwft_fifo_ren & fwft_fifo_empty_n)
+            # simulation_delay regs_buffer[0] <= regs_buffer[1];
+    end
+    
+    always @(posedge clk)
+    begin
+        if(std_fifo_rvld & ((fwft_fifo_ren & fwft_fifo_empty_n) ? buffer_data_cnt_sub1[1]:buffer_data_cnt[1]))
+            # simulation_delay regs_buffer[1] <= std_fifo_dout;
+    end
+    
+    // buffer存储计数独热码
+    always @(posedge clk or negedge rst_n)
+    begin
+        if(~rst_n)
+            buffer_data_cnt <= 3'b001;
+        else if(std_fifo_rvld ^ (fwft_fifo_ren & fwft_fifo_empty_n))
+            # simulation_delay buffer_data_cnt <= std_fifo_rvld ? {buffer_data_cnt[1:0], buffer_data_cnt[2]}:{buffer_data_cnt[0], buffer_data_cnt[2:1]};
+    end
+    
+    /** 标准fifo的读端口 **/
+    assign std_fifo_ren = buffer_data_cnt[0] | fwft_fifo_ren; // buffer存储计数==0或者FWFT-fifo读使能时标准fifo读使能有效
+    
+    /** FWFT fifo的读端口 **/
+    reg fwft_fifo_empty_n_reg;
+    
+    assign fwft_fifo_dout = regs_buffer[0];
+    assign fwft_fifo_empty = buffer_data_cnt[0];
+    assign fwft_fifo_empty_n = fwft_fifo_empty_n_reg;
+    
+    always @(posedge clk or negedge rst_n)
+    begin
+        if(~rst_n)
+            fwft_fifo_empty_n_reg <= 1'b0;
+        else if(std_fifo_rvld ^ (fwft_fifo_ren & fwft_fifo_empty_n))
+            # simulation_delay fwft_fifo_empty_n_reg <= std_fifo_rvld ? 1'b1:(~buffer_data_cnt[1]);
+    end
+    
+endmodule

CutestPanda_Opensoc/101_apb_uart/rtl/itr_generator.v

@@ -0,0 +1,104 @@
+/*
+MIT License
+
+Copyright (c) 2024 Panda, 2257691535@qq.com
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+*/
+
+`timescale 1ns / 1ps
+/********************************************************************
+本模块: 中断信号发生器
+
+描述: 
+将原始的中断脉冲拓展为一定脉宽的中断信号
+
+注意：
+中断脉宽必须 >= 2
+
+协议:
+无
+
+作者: 陈家耀
+日期: 2023/11/08
+********************************************************************/
+
+
+module itr_generator #(
+    parameter integer pulse_w = 100, // 中断脉宽(必须>=1)
+    parameter real simulation_delay = 1 // 仿真延时
+)(
+    // 时钟和复位
+    input wire clk,
+    input wire rst_n,
+    
+    input wire itr_org, // 原始中断输入
+    output wire itr // 中断输出
+);
+
+    // 计算log2(bit_depth)               
+    function integer clogb2 (input integer bit_depth);
+        integer temp;
+    begin
+        temp = bit_depth;
+        for(clogb2 = -1;temp > 0;clogb2 = clogb2 + 1)                   
+            temp = temp >> 1;                                 
+    end                                        
+    endfunction
+    
+    // 产生中断信号
+    reg itr_reg; // 中断信号
+    reg[clogb2(pulse_w - 1):0] itr_cnt; // 中断计数器
+    
+    assign itr = itr_reg;
+    
+    generate
+        if(pulse_w == 1)
+        begin
+            always @(posedge clk or negedge rst_n)
+            begin
+                if(~rst_n)
+                    itr_reg <= 1'b0;
+                else
+                    # simulation_delay itr_reg <= itr_org;
+            end
+        end
+        else
+        begin
+            always @(posedge clk or negedge rst_n)
+            begin
+                if(~rst_n)
+                    itr_reg <= 1'b0;
+                else
+                begin
+                    # simulation_delay;
+                    
+                    if(~itr_reg) // 等待原始中断脉冲
+                        itr_reg <= itr_org;
+                    else // 等待计数完成
+                        itr_reg <= itr_cnt != pulse_w - 1;
+                end
+            end
+        end
+    endgenerate
+    
+    always @(posedge clk)
+        # simulation_delay itr_cnt <= (~itr_reg) ? 0:(itr_cnt + 1);
+
+endmodule

CutestPanda_Opensoc/101_apb_uart/rtl/ram_fifo_wrapper.v

@@ -0,0 +1,220 @@
+/*
+MIT License
+
+Copyright (c) 2024 Panda, 2257691535@qq.com
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+*/
+
+`timescale 1ns / 1ps
+/********************************************************************
+本模块: 基于lutram或bram的同步fifo
+
+描述: 
+全流水的高性能同步fifo
+基于lutram或bram
+支持first word fall through特性(READ LA = 0)
+可选的固定阈值将满/将空信号
+可选的存储计数输出
+
+注意：
+将满信号当存储计数 >= almost_full_th时有效
+将空信号当存储计数 <= almost_empty_th时有效
+almost_full_th和almost_empty_th必须在[1, fifo_depth-1]范围内
+本模块用于fpga, 子模块fifo_based_on_ram可用于asic设计
+寄存器fifo请用子模块fifo_based_on_regs
+
+协议:
+FIFO WRITE/READ
+
+作者: 陈家耀
+日期: 2023/10/29
+********************************************************************/
+
+
+module ram_fifo_wrapper #(
+    parameter fwft_mode = "true", // 是否启用first word fall through特性
+    parameter ram_type = "lutram", // RAM类型(lutram|bram)
+    parameter en_bram_reg = "false", // 是否启用BRAM输出寄存器
+    parameter integer fifo_depth = 32, // fifo深度(必须为2|4|8|16|...)
+    parameter integer fifo_data_width = 32, // fifo位宽
+    parameter full_assert_polarity = "low", // 满信号有效极性(low|high)
+    parameter empty_assert_polarity = "low", // 空信号有效极性(low|high)
+    parameter almost_full_assert_polarity = "no", // 将满信号有效极性(low|high|no)
+    parameter almost_empty_assert_polarity = "no", // 将空信号有效极性(low|high|no)
+    parameter en_data_cnt = "false", // 是否启用存储计数器
+    parameter integer almost_full_th = 20, // fifo将满阈值
+    parameter integer almost_empty_th = 5, // fifo将空阈值
+    parameter real simulation_delay = 1 // 仿真延时
+)(
+    // 时钟和复位
+    input wire clk,
+    input wire rst_n,
+    
+    // FIFO WRITE(fifo写端口)
+    input wire fifo_wen,
+    input wire[fifo_data_width-1:0] fifo_din,
+    output wire fifo_full,
+    output wire fifo_full_n,
+    output wire fifo_almost_full,
+    output wire fifo_almost_full_n,
+    
+    // FIFO READ(fifo读端口)
+    input wire fifo_ren,
+    output wire[fifo_data_width-1:0] fifo_dout,
+    output wire fifo_empty,
+    output wire fifo_empty_n,
+    output wire fifo_almost_empty,
+    output wire fifo_almost_empty_n,
+    
+    // 存储计数
+    output wire[clogb2(fifo_depth):0] data_cnt
+);
+
+    // 计算log2(bit_depth)               
+    function integer clogb2 (input integer bit_depth);
+        integer temp;
+    begin
+        temp = bit_depth;
+        for(clogb2 = -1;temp > 0;clogb2 = clogb2 + 1)
+            temp = temp >> 1;
+    end
+    endfunction
+    
+    wire fifo_full_w;
+    wire fifo_full_n_w;
+    wire fifo_almost_full_w;
+    wire fifo_almost_full_n_w;
+    wire fifo_empty_w;
+    wire fifo_empty_n_w;
+    wire fifo_almost_empty_w;
+    wire fifo_almost_empty_n_w;
+    wire[clogb2(fifo_depth):0] data_cnt_w;
+    
+    generate
+        if(full_assert_polarity == "low")
+            assign fifo_full_n = fifo_full_n_w;
+        else
+            assign fifo_full = fifo_full_w;
+        
+        if(almost_full_assert_polarity == "low")
+            assign fifo_almost_full_n = fifo_almost_full_n_w;
+        else if(almost_full_assert_polarity == "high")
+            assign fifo_almost_full = fifo_almost_full_w;
+        
+        if(empty_assert_polarity == "low")
+            assign fifo_empty_n = fifo_empty_n_w;
+        else
+            assign fifo_empty = fifo_empty_w;
+        
+        if(almost_empty_assert_polarity == "low")
+            assign fifo_almost_empty_n = fifo_almost_empty_n_w;
+        else if(almost_empty_assert_polarity == "high")
+            assign fifo_almost_empty = fifo_almost_empty_w;
+        
+        if(en_data_cnt == "true")
+            assign data_cnt = data_cnt_w;
+    
+        if(ram_type == "lutram")
+        begin
+            fifo_based_on_lutram #(
+                .fwft_mode(fwft_mode),
+                .fifo_depth(fifo_depth),
+                .fifo_data_width(fifo_data_width),
+                .almost_full_th(almost_full_th),
+                .almost_empty_th(almost_empty_th),
+                .simulation_delay(simulation_delay)
+            )fifo(
+                .clk(clk),
+                .rst_n(rst_n),
+                .fifo_wen(fifo_wen),
+                .fifo_din(fifo_din),
+                .fifo_full(fifo_full_w),
+                .fifo_full_n(fifo_full_n_w),
+                .fifo_almost_full(fifo_almost_full_w),
+                .fifo_almost_full_n(fifo_almost_full_n_w),
+                .fifo_ren(fifo_ren),
+                .fifo_dout(fifo_dout),
+                .fifo_empty(fifo_empty_w),
+                .fifo_empty_n(fifo_empty_n_w),
+                .fifo_almost_empty(fifo_almost_empty_w),
+                .fifo_almost_empty_n(fifo_almost_empty_n_w),
+                .data_cnt(data_cnt_w)
+            );
+        end
+        else
+        begin
+            wire ram_wen_a;
+            wire[clogb2(fifo_depth-1):0] ram_addr_a;
+            wire[fifo_data_width-1:0] ram_din_a;
+            wire ram_ren_b;
+            wire[clogb2(fifo_depth-1):0] ram_addr_b;
+            wire[fifo_data_width-1:0] ram_dout_b;
+    
+            fifo_based_on_ram #(
+                .fwft_mode(fwft_mode),
+                .ram_read_la((en_bram_reg == "true") ? 2:1),
+                .fifo_depth(fifo_depth),
+                .fifo_data_width(fifo_data_width),
+                .almost_full_th(almost_full_th),
+                .almost_empty_th(almost_empty_th),
+                .simulation_delay(simulation_delay)
+            )fifo_ctrler(
+                .clk(clk),
+                .rst_n(rst_n),
+                .fifo_wen(fifo_wen),
+                .fifo_din(fifo_din),
+                .fifo_full(fifo_full_w),
+                .fifo_full_n(fifo_full_n_w),
+                .fifo_almost_full(fifo_almost_full_w),
+                .fifo_almost_full_n(fifo_almost_full_n_w),
+                .fifo_ren(fifo_ren),
+                .fifo_dout(fifo_dout),
+                .fifo_empty(fifo_empty_w),
+                .fifo_empty_n(fifo_empty_n_w),
+                .fifo_almost_empty(fifo_almost_empty_w),
+                .fifo_almost_empty_n(fifo_almost_empty_n_w),
+                .ram_wen(ram_wen_a),
+                .ram_w_addr(ram_addr_a),
+                .ram_din(ram_din_a),
+                .ram_ren(ram_ren_b),
+                .ram_r_addr(ram_addr_b),
+                .ram_dout(ram_dout_b),
+                .data_cnt(data_cnt_w)
+            );
+            
+            bram_simple_dual_port #(
+                .style((en_bram_reg == "true") ? "HIGH_PERFORMANCE":"LOW_LATENCY"),
+                .mem_width(fifo_data_width),
+                .mem_depth(fifo_depth),
+                .INIT_FILE("no_init"),
+                .simulation_delay(simulation_delay)
+            )fifo_ram(
+                .clk(clk),
+                .wen_a(ram_wen_a),
+                .addr_a(ram_addr_a),
+                .din_a(ram_din_a),
+                .ren_b(ram_ren_b),
+                .addr_b(ram_addr_b),
+                .dout_b(ram_dout_b)
+            );
+        end
+    endgenerate
+    
+endmodule

CutestPanda_Opensoc/101_apb_uart/rtl/uart_rx.v

@@ -0,0 +1,263 @@
+/*
+MIT License
+
+Copyright (c) 2024 Panda, 2257691535@qq.com
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+*/
+
+`timescale 1ns / 1ps
+/********************************************************************
+本模块: UART接收控制器
+
+描述: 
+符合AXIS协议的UART接收控制器
+
+注意：
+UART接收可能溢出
+
+协议:
+AXIS MASTER
+UART
+
+作者: 陈家耀
+日期: 2023/11/08
+********************************************************************/
+
+
+module uart_rx #(
+    parameter integer clk_frequency = 200000000, // 时钟频率
+    parameter integer baud_rate = 115200, // 波特率
+    parameter real simulation_delay = 1 // 仿真延时
+)(
+    input wire clk,
+    input wire rst_n,
+    
+    input wire rx,
+    
+    output wire[7:0] rx_byte_data,
+    output wire rx_byte_valid,
+    input wire rx_byte_ready,
+    
+    output wire rx_idle,
+    output wire rx_done,
+    output wire rx_start
+);
+
+    // 计算log2(bit_depth)               
+    function integer clogb2 (input integer bit_depth);
+        integer temp;
+    begin
+        temp = bit_depth;
+        for(clogb2 = -1;temp > 0;clogb2 = clogb2 + 1)                   
+            temp = temp >> 1;                                 
+    end                                        
+    endfunction
+
+    localparam integer clk_n_per_bit = clk_frequency / baud_rate; // 传输每一位所用的时钟周期个数
+    
+    /** 打两拍消除亚稳态 **/
+    reg rx_d;
+    reg rx_d2;
+    wire rx_stable;
+    
+    assign rx_stable = rx_d2;
+    
+    always @(posedge clk or negedge rst_n)
+    begin
+        if(~rst_n)
+            {rx_d2, rx_d} <= 2'b11;
+        else
+            # simulation_delay {rx_d2, rx_d} <= {rx_d, rx};
+    end
+    
+    /** 检测下降沿 **/
+    reg rx_stable_d;
+    reg rx_neg_edge_detected; // 检测到下降沿(脉冲)
+    
+    always @(posedge clk or negedge rst_n)
+    begin
+        if(~rst_n)
+            rx_stable_d <= 1'b1;
+        else
+            # simulation_delay rx_stable_d <= rx_stable;
+    end
+    
+    always @(posedge clk or negedge rst_n)
+    begin
+        if(~rst_n)
+            rx_neg_edge_detected <= 1'b0;
+        else
+            # simulation_delay rx_neg_edge_detected <= (~rx_stable) & rx_stable_d;
+    end
+    
+    /** 数据接收状态机 **/
+    localparam status_idle = 2'b00; // 状态:空闲
+    localparam status_start = 2'b01; // 状态:起始位
+    localparam status_data = 2'b10; // 状态:数据位
+    localparam status_stop = 2'b11; // 状态:停止位
+    
+    reg[1:0] now_status;
+    
+    reg[clogb2(clk_n_per_bit-1):0] cnt; // 波特率计数器
+    reg[2:0] now_bit_i; // 当前接收字节位编号
+    reg[7:0] byte; // 当前接收的字节
+    reg byte_vld; // 接收字节完成(脉冲)
+    reg rx_idle_reg; // UART控制器接收空闲(标志)
+    
+    reg cnt_eq_clk_n_per_bit_div2_sub1; // 波特率计数器 == UART位时钟周期 / 2 - 1(脉冲)
+    reg cnt_eq_clk_n_per_bit_sub1; // 波特率计数器 == UART位时钟周期 - 1(脉冲)
+    
+    assign rx_byte_data = byte;
+    assign rx_byte_valid = byte_vld;
+    assign rx_idle = rx_idle_reg;
+    assign rx_done = byte_vld;
+    assign rx_start = rx_neg_edge_detected;
+    
+    // 波特率计数器比较结果指示
+    always @(posedge clk or negedge rst_n)
+    begin
+        if(~rst_n)
+        begin
+            cnt_eq_clk_n_per_bit_div2_sub1 <= 1'b0;
+            cnt_eq_clk_n_per_bit_sub1 <= 1'b0;
+        end
+        else
+        begin
+            # simulation_delay;
+            
+            cnt_eq_clk_n_per_bit_div2_sub1 <= (cnt == clk_n_per_bit / 2 - 2);
+            cnt_eq_clk_n_per_bit_sub1 <= (cnt == clk_n_per_bit - 2);
+        end
+    end
+    
+    always @(posedge clk or negedge rst_n)
+    begin
+        if(~rst_n)
+        begin
+            now_status <= status_idle;
+            cnt <= 0;
+            now_bit_i <= 3'b000;
+            byte_vld <= 1'b0;
+            rx_idle_reg <= 1'b1;
+        end
+        else
+        begin
+            # simulation_delay;
+            
+            byte_vld <= 1'b0;
+            case(now_status)
+                status_idle: // 状态:空闲
+                begin
+                    rx_idle_reg <= rx_idle_reg | cnt_eq_clk_n_per_bit_div2_sub1; // 为了跳过上一次传输的停止位, idle信号只能在波特率计数器 == UART位时钟周期 / 2 - 1时置为有效
+                    
+                    if(rx_neg_edge_detected) // 检测到开始位
+                    begin
+                        now_status <= status_start;
+                        cnt <= 0;
+                    end
+                    else
+                    begin
+                        now_status <= status_idle;
+                        cnt <= cnt + 1;
+                    end
+                end
+                status_start: // 状态:起始位
+                begin
+                    rx_idle_reg <= 1'b0;
+                    
+                    if(cnt_eq_clk_n_per_bit_div2_sub1) // 对齐到起始位中央再继续接收
+                    begin
+                        now_status <= status_data;
+                        cnt <= 0;
+                    end
+                    else
+                    begin
+                        now_status <= status_start;
+                        cnt <= cnt + 1;
+                    end
+                end
+                status_data: // 状态:数据位
+                begin
+                    rx_idle_reg <= 1'b0;
+                    
+                    if(cnt_eq_clk_n_per_bit_sub1) // 接收UART数据位
+                    begin
+                        cnt <= 0;
+                        now_bit_i <= now_bit_i + 3'b001;
+                        
+                        if(now_bit_i == 3'b111)
+                            now_status <= status_stop;
+                        else
+                            now_status <= status_data;
+                    end
+                    else
+                    begin
+                        now_status <= status_data;
+                        cnt <= cnt + 1;
+                    end
+                end
+                status_stop: // 状态:停止位
+                begin
+                    rx_idle_reg <= 1'b0;
+                    
+                    if(cnt_eq_clk_n_per_bit_sub1) // 此时对齐到停止位的中央
+                    begin
+                        now_status <= status_idle;
+                        cnt <= 0;
+                        byte_vld <= 1'b1;
+                    end
+                    else
+                    begin
+                        now_status <= status_stop;
+                        cnt <= cnt + 1;
+                    end
+                end
+                default:
+                begin
+                    now_status <= status_idle;
+                    cnt <= 0;
+                    now_bit_i <= 3'b000;
+                    rx_idle_reg <= 1'b1;
+                end
+            endcase
+        end
+    end
+    
+    // 当前接收的字节
+    always @(posedge clk)
+    begin
+        # simulation_delay;
+        
+        if(now_status == status_data)
+        begin
+            case(now_bit_i)
+                3'b000: byte[0] <= rx_stable;
+                3'b001: byte[1] <= rx_stable;
+                3'b010: byte[2] <= rx_stable;
+                3'b011: byte[3] <= rx_stable;
+                3'b100: byte[4] <= rx_stable;
+                3'b101: byte[5] <= rx_stable;
+                3'b110: byte[6] <= rx_stable;
+                3'b111: byte[7] <= rx_stable;
+            endcase
+        end
+    end
+
+endmodule

CutestPanda_Opensoc/101_apb_uart/rtl/uart_rx_tx.v

@@ -0,0 +1,138 @@
+/*
+MIT License
+
+Copyright (c) 2024 Panda, 2257691535@qq.com
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+*/
+
+`timescale 1ns / 1ps
+/********************************************************************
+本模块: UART控制器
+
+描述: 
+使用发送/接收fifo的UART控制器
+可选AXIS接口或FIFO接口
+
+注意：
+当使用FIFO接口时, UART发送FIFO请使用标准FIFO
+UART接收可能溢出
+
+协议:
+AXIS MASTER/SLAVE
+FIFO READ/WRITE
+UART
+
+作者: 陈家耀
+日期: 2023/11/08
+********************************************************************/
+
+
+module uart_rx_tx #(
+    parameter integer clk_frequency_MHz = 200, // 时钟频率
+    parameter integer baud_rate = 115200, // 波特率
+    parameter interface = "fifo", // 接口协议(axis|fifo)
+    parameter real simulation_delay = 1 // 仿真延时
+)(
+    input wire clk,
+    input wire resetn,
+    
+    input wire rx,
+    output wire tx,
+    
+    output wire[7:0] m_axis_rx_byte_data,
+    output wire m_axis_rx_byte_valid,
+    input wire m_axis_rx_byte_ready,
+    
+    output wire[7:0] rx_buf_fifo_din,
+    output wire rx_buf_fifo_wen,
+    input wire rx_buf_fifo_full,
+    
+    input wire[7:0] s_axis_tx_byte_data,
+    input wire s_axis_tx_byte_valid,
+    output wire s_axis_tx_byte_ready,
+    
+    input wire[7:0] tx_buf_fifo_dout,
+    input wire tx_buf_fifo_empty,
+    input wire tx_buf_fifo_almost_empty,
+    output wire tx_buf_fifo_ren,
+    
+    output wire rx_err,
+    output wire tx_idle,
+    output wire rx_idle,
+    output wire tx_done,
+    output wire rx_done,
+    output wire rx_start
+);
+    
+    // 检查接收缓冲区是否溢出
+    reg rx_err_reg;
+    
+    assign rx_err = rx_err_reg;
+    
+    always @(posedge clk or negedge resetn)
+    begin
+        if(~resetn)
+            rx_err_reg <= 1'b0;
+        else
+            # simulation_delay rx_err_reg <= (interface == "axis") ? (m_axis_rx_byte_valid & (~m_axis_rx_byte_ready)):(rx_buf_fifo_wen & rx_buf_fifo_full);
+    end
+    
+    /** uart收发 **/
+    localparam integer clk_frequency = clk_frequency_MHz * 1000000;
+    
+    assign rx_buf_fifo_din = m_axis_rx_byte_data;
+    assign rx_buf_fifo_wen = m_axis_rx_byte_valid;
+    
+    uart_rx #(
+        .clk_frequency(clk_frequency),
+        .baud_rate(baud_rate),
+        .simulation_delay(simulation_delay)
+    )uart_rx_u(
+        .clk(clk),
+        .rst_n(resetn),
+        .rx(rx),
+        .rx_byte_data(m_axis_rx_byte_data),
+        .rx_byte_valid(m_axis_rx_byte_valid),
+        .rx_byte_ready((interface == "axis") ? m_axis_rx_byte_ready:(~rx_buf_fifo_full)),
+        .rx_idle(rx_idle),
+        .rx_done(rx_done),
+        .rx_start(rx_start)
+    );
+    
+    uart_tx #(
+        .clk_frequency(clk_frequency),
+        .baud_rate(baud_rate),
+        .interface(interface),
+        .simulation_delay(simulation_delay)
+    )uart_tx_u(
+        .clk(clk),    
+        .rst_n(resetn),
+        .tx(tx),
+        .tx_byte_data(s_axis_tx_byte_data),
+        .tx_byte_valid(s_axis_tx_byte_valid),
+        .tx_byte_ready(s_axis_tx_byte_ready),
+        .tx_fifo_dout(tx_buf_fifo_dout),
+        .tx_fifo_empty(tx_buf_fifo_empty),
+        .tx_fifo_ren(tx_buf_fifo_ren),
+        .tx_idle(tx_idle),
+        .tx_done(tx_done)
+    );
+
+endmodule

CutestPanda_Opensoc/101_apb_uart/rtl/uart_tx.v

@@ -0,0 +1,226 @@
+/*
+MIT License
+
+Copyright (c) 2024 Panda, 2257691535@qq.com
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+*/
+
+`timescale 1ns / 1ps
+/********************************************************************
+本模块: UART发送控制器
+
+描述: 
+UART发送控制器
+可选AXIS接口或FIFO接口
+
+注意：
+无
+
+协议:
+AXIS SLAVE
+FIFO READ
+UART
+
+作者: 陈家耀
+日期: 2023/11/08
+********************************************************************/
+
+
+module uart_tx #(
+    parameter integer clk_frequency = 200000000, // 时钟频率
+    parameter integer baud_rate = 115200, // 波特率
+    parameter interface = "axis", // 接口协议(axis|fifo)
+    parameter real simulation_delay = 1 // 仿真延时
+)(
+    input wire clk,
+    input wire rst_n,
+    
+    output wire tx,
+    
+    input wire[7:0] tx_byte_data,
+    input wire tx_byte_valid,
+    output wire tx_byte_ready,
+    
+    input wire[7:0] tx_fifo_dout,
+    input wire tx_fifo_empty,
+    output wire tx_fifo_ren,
+    
+    output wire tx_idle,
+    output wire tx_done
+);
+
+    // 计算log2(bit_depth)               
+    function integer clogb2 (input integer bit_depth);
+        integer temp;
+    begin
+        temp = bit_depth;
+        for(clogb2 = -1;temp > 0;clogb2 = clogb2 + 1)                   
+            temp = temp >> 1;                                 
+    end                                        
+    endfunction
+    
+    localparam integer div_n = clk_frequency / baud_rate;
+    
+    /** 发送fifo读端口 **/
+    wire[7:0] tx_fifo_data_out;
+    wire tx_fifo_empty_n;
+    
+    reg ready_reg;
+    
+    assign tx_byte_ready = ready_reg;
+    assign tx_fifo_data_out = (interface == "axis") ? tx_byte_data:tx_fifo_dout;
+    assign tx_fifo_empty_n = (interface == "axis") ? tx_byte_valid:(~tx_fifo_empty);
+    
+    assign tx_fifo_ren = ready_reg;
+    
+    /** 分频计数器 **/
+    reg[clogb2(div_n-1):0] cnt;
+    reg cnt_last_flag;
+    
+    always @(posedge clk or negedge rst_n)
+    begin
+        if(~rst_n)
+        begin
+            cnt <= 0;
+            cnt_last_flag <= 1'b0;
+        end
+        else
+        begin
+            # simulation_delay;
+            
+            if(cnt_last_flag)
+                cnt <= 0;
+            else
+                cnt <= cnt + 1;
+            
+            cnt_last_flag <= cnt == div_n - 2;
+        end
+    end
+    
+    /** 数据发送状态机 **/
+    localparam status_idle = 2'b00; // 状态:空闲
+    localparam status_start = 2'b01; // 状态:起始位
+    localparam status_data = 2'b10; // 状态:数据位
+    localparam status_stop = 2'b11; // 状态:停止位
+    
+    reg[1:0] now_status; // 当前状态
+    reg[7:0] now_byte; // 待发送字节
+    reg tx_reg; // UART的tx端
+    reg[7:0] now_byte_i; // 当前发送字节的位编号(独一码)
+    reg byte_loaded; // 已加载待发送字节(标志)
+    reg tx_idle_reg; // UART控制器发送空闲(标志)
+    reg tx_done_reg; // UART控制器发送完成(标志)
+    
+    assign tx = tx_reg;
+    assign tx_idle = tx_idle_reg;
+    assign tx_done = tx_done_reg;
+    
+    always @(posedge clk or negedge rst_n)
+    begin
+        if(~rst_n)
+        begin
+            now_status <= status_idle;
+            tx_reg <= 1'b1;
+            now_byte_i <= 8'd1;
+            byte_loaded <= 1'b0;
+            ready_reg <= 1'b0;
+            tx_idle_reg <= 1'b1;
+            tx_done_reg <= 1'b0;
+        end
+        else
+        begin
+            # simulation_delay;
+        
+            ready_reg <= 1'b0;
+            tx_done_reg <= 1'b0;
+            
+            case(now_status)
+                status_idle: // 状态:空闲
+                begin
+                    if(byte_loaded)
+                        now_status <= status_start;
+                    
+                    byte_loaded <= tx_fifo_empty_n & ready_reg;
+                    tx_reg <= 1'b1;
+                    ready_reg <= (~byte_loaded) & (~(tx_fifo_empty_n & ready_reg));
+                    tx_idle_reg <= ~(byte_loaded | tx_fifo_empty_n); // 直接判断~tx_fifo_empty_n也可以???
+                end
+                status_start: // 状态:起始位
+                begin
+                    if(cnt_last_flag)
+                    begin
+                        now_status <= status_data;
+                        tx_reg <= 1'b0; // 产生下降沿 -> 起始位
+                    end
+                    
+                    byte_loaded <= 1'b0;
+                    tx_idle_reg <= 1'b0;
+                end
+                status_data: // 状态:数据位
+                begin
+                    if(cnt_last_flag)
+                    begin
+                        if(now_byte_i[7])
+                            now_status <= status_stop;
+                        
+                        now_byte_i <= {now_byte_i[6:0], now_byte_i[7]}; // 对当前发送字节的位编号(独一码)做循环左移
+                        tx_reg <= now_byte[0]; // 发送下一数据位
+                    end
+                    
+                    byte_loaded <= 1'b0;
+                    tx_idle_reg <= 1'b0;
+                end
+                status_stop: // 状态:停止位
+                begin
+                    if(cnt_last_flag)
+                    begin
+                        now_status <= status_idle;
+                        tx_reg <= 1'b1; // 产生停止位
+                        tx_done_reg <= 1'b1;
+                    end
+                    
+                    byte_loaded <= 1'b0;
+                    tx_idle_reg <= 1'b0;
+                end
+                default:
+                begin
+                    now_status <= status_idle;
+                    tx_reg <= 1'b1;
+                    now_byte_i <= 8'd1;
+                    byte_loaded <= 1'b0;
+                    tx_idle_reg <= 1'b1;
+                end
+            endcase
+        end
+    end
+    
+    // 待发送字节
+    always @(posedge clk)
+    begin
+        # simulation_delay;
+        
+        if((now_status == status_idle) &
+            ((interface == "axis") ? (tx_fifo_empty_n & ready_reg):byte_loaded)) // 载入
+            now_byte <= tx_fifo_data_out;
+        else if((now_status == status_data) & cnt_last_flag) // 右移
+            now_byte <= {1'bx, now_byte[7:1]};
+    end
+
+endmodule

CutestPanda_Opensoc/102_apb_i2c/firmware/apb_i2c.c

@@ -0,0 +1,187 @@
+/************************************************************************************************************************
+APB-I2C����(��Դ�ļ�)
+@brief  APB-I2C����
+@date   2024/08/28
+@author �¼�ҫ
+@eidt   2024/08/28 1.00 �����˵�һ����ʽ�汾
+************************************************************************************************************************/
+
+#include "apb_i2c.h"
+
+////////////////////////////////////////////////////////////////////////////////////////////////////////////
+
+static int apb_i2c_tx(ApbI2C* i2c, uint8_t byte, uint8_t is_last); // ����FIFOд��һ���ֽ�����
+
+////////////////////////////////////////////////////////////////////////////////////////////////////////////
+
+/*************************
+@init
+@public
+@brief  ��ʼ��APB-I2C
+@param  i2c APB-I2C(�ṹ��ָ��)
+        base_addr APB-I2C�������ַ
+@return none
+*************************/
+void apb_i2c_init(ApbI2C* i2c, uint32_t base_addr){
+	i2c->hardware = (ApbI2CHd*)base_addr;
+}
+
+/*************************
+@io
+@public
+@brief  APB-I2C�������
+@param  i2c APB-I2C(�ṹ��ָ��)
+        slave_addr �ӻ���ַ
+        data �������ֽڻ�����(�׵�ַ)
+        len �������ֽ���
+@attention ����fifoд���ݿ��ܻ��������
+@return �Ƿ�ɹ�
+*************************/
+int apb_i2c_start_wt_trans(ApbI2C* i2c, uint8_t slave_addr, uint8_t* data, uint8_t len){
+	if(len > 15){ // ÿ��I2C���ݰ����ܳ���15�ֽ�
+		return -1;
+	}else{
+		while(apb_i2c_tx(i2c, slave_addr, 0));
+		
+		for(uint8_t i = 0;i < len;i++){
+			while(apb_i2c_tx(i2c, data[i], i == (len - 1)));
+		}
+		
+		return 0;
+	}
+}
+
+/*************************
+@io
+@public
+@brief  APB-I2C����������
+@param  i2c APB-I2C(�ṹ��ָ��)
+        slave_addr �ӻ���ַ
+        len �������ֽ���
+@attention ����fifoд���ݿ��ܻ��������
+@return �Ƿ�ɹ�
+*************************/
+int apb_i2c_start_rd_trans(ApbI2C* i2c, uint8_t slave_addr, uint8_t len){
+	if(len > 15){ // ÿ��I2C���ݰ����ܳ���15�ֽ�
+		return -1;
+	}else{
+		while(apb_i2c_tx(i2c, slave_addr | 0x01, 0));
+		while(apb_i2c_tx(i2c, len, 1));
+		
+		return 0;
+	}
+}
+
+/*************************
+@io
+@public
+@brief  �ӽ���FIFO��ȡһ���ֽ�����
+@param  i2c APB-I2C(�ṹ��ָ��)
+        byte �����ֽڻ�����(�׵�ַ)
+@return �Ƿ�ɹ�
+*************************/
+int apb_i2c_get_rx_byte(ApbI2C* i2c, uint8_t* byte){
+	uint32_t fifo_cs = i2c->hardware->fifo_cs;
+	
+	if(fifo_cs & 0x00010000){
+		return -1;
+	}else{
+		i2c->hardware->fifo_cs = 0x00020000;
+		
+		*byte = (uint8_t)(i2c->hardware->fifo_cs >> 18);
+		
+		return 0;
+	}
+}
+
+/*************************
+@cfg
+@public
+@brief  APB-I2Cʹ���ж�
+@param  i2c APB-I2C(�ṹ��ָ��)
+        itr_en �ж�ʹ������
+@return none
+*************************/
+void apb_i2c_enable_itr(ApbI2C* i2c, uint8_t itr_en){
+	i2c->hardware->itr_status_en = 0x00000001 | (((uint32_t)itr_en) << 8);
+}
+
+/*************************
+@cfg
+@public
+@brief  APB-I2C�����ж�
+@param  i2c APB-I2C(�ṹ��ָ��)
+@return none
+*************************/
+void apb_i2c_disable_itr(ApbI2C* i2c){
+	i2c->hardware->itr_status_en = 0x00000000;
+}
+
+/*************************
+@cfg
+@public
+@brief  APB-I2C��������ʱ����
+@param  i2c APB-I2C(�ṹ��ָ��)
+			  tx_bytes_n_th I2C�����ж��ֽ�����ֵ
+				rx_bytes_n_th I2C�����ж��ֽ�����ֵ
+				scl_div_n I2Cʱ�ӷ�Ƶϵ��
+@return none
+*************************/
+void apb_i2c_config_params(ApbI2C* i2c, uint8_t tx_bytes_n_th, uint8_t rx_bytes_n_th, uint8_t scl_div_n){
+	i2c->hardware->itr_th = ((uint32_t)tx_bytes_n_th) | (((uint32_t)rx_bytes_n_th) << 8)
+		 | (((uint32_t)scl_div_n) << 16);
+}
+
+/*************************
+@sts
+@public
+@brief  APB-I2C��ȡ�ж�״̬
+@param  i2c APB-I2C(�ṹ��ָ��)
+			  tx_bytes_n I2C�����ֽ���(ָ��)
+				rx_bytes_n I2C�����ֽ���(ָ��)
+@return �ж�״̬
+*************************/
+uint8_t apb_i2c_get_itr_status(ApbI2C* i2c, uint16_t* tx_bytes_n, uint16_t* rx_bytes_n){
+	uint8_t itr_status = ((uint8_t)(i2c->hardware->itr_flag_status >> 1)) & 0x0000000F;
+	
+	uint32_t rx_tx_bytes_n = (i2c->hardware->itr_flag_status >> 8);
+	
+	*tx_bytes_n = (uint16_t)(rx_tx_bytes_n & 0x00000FFF);
+	*rx_bytes_n = (uint16_t)(rx_tx_bytes_n >> 12);
+	
+	return itr_status;
+}
+
+/*************************
+@sts
+@public
+@brief  APB-I2C����жϱ�־
+@param  i2c APB-I2C(�ṹ��ָ��)
+@return none
+*************************/
+void apb_i2c_clear_itr_flag(ApbI2C* i2c){
+	i2c->hardware->itr_flag_status = 0x00000000;
+}
+
+////////////////////////////////////////////////////////////////////////////////////////////////////////////
+
+/*************************
+@io
+@private
+@brief  ����FIFOд��һ���ֽ�����
+@param  i2c APB-I2C(�ṹ��ָ��)
+        byte ��д����ֽ�����
+			  is_last ������lastָʾ
+@return �Ƿ�ɹ�
+*************************/
+static int apb_i2c_tx(ApbI2C* i2c, uint8_t byte, uint8_t is_last){
+	uint32_t fifo_cs = i2c->hardware->fifo_cs;
+	
+	if(fifo_cs & 0x00000001){
+		return -1;
+	}else{
+		i2c->hardware->fifo_cs = 0x00000002 | (((uint32_t)byte) << 2) | (((uint32_t)is_last) << 10);
+		
+		return 0;
+	}
+}

CutestPanda_Opensoc/102_apb_i2c/firmware/apb_i2c.h

@@ -0,0 +1,44 @@
+#include <stdint.h>
+
+////////////////////////////////////////////////////////////////////////////////////////////////////////////
+
+// ���������
+#define I2C_TX_BYTES_N_ITR_MASK 0x01 // I2C����ָ���ֽ����жϱ�־
+#define I2C_SLAVE_RESP_ERR_ITR_MASK 0x02 // I2C�ӻ���Ӧ�����жϱ�־
+#define I2C_RX_BYTES_N_ITR_MASK 0x04 // I2C����ָ���ֽ����жϱ�־
+#define I2C_RX_OVF_ITR_MASK 0x08 // I2C��������жϱ�־
+
+////////////////////////////////////////////////////////////////////////////////////////////////////////////
+
+#ifndef __APB_I2C_H
+#define __APB_I2C_H
+
+typedef struct{
+	uint32_t fifo_cs; // �շ�fifo����
+	uint32_t itr_status_en; // �ж�ʹ��
+	uint32_t itr_th; // ����ʱ����
+	uint32_t itr_flag_status; // �жϱ�־��״̬��Ϣ
+}ApbI2CHd;
+
+typedef struct{
+	ApbI2CHd* hardware; // APB-I2C�Ĵ����ӿ�(�ṹ��ָ��)
+}ApbI2C;
+
+#endif
+
+////////////////////////////////////////////////////////////////////////////////////////////////////////////
+
+void apb_i2c_init(ApbI2C* i2c, uint32_t base_addr); // ��ʼ��APB-I2C
+
+int apb_i2c_start_wt_trans(ApbI2C* i2c, uint8_t slave_addr, uint8_t* data, uint8_t len); // APB-I2C�������
+int apb_i2c_start_rd_trans(ApbI2C* i2c, uint8_t slave_addr, uint8_t len); // APB-I2C����������
+
+int apb_i2c_get_rx_byte(ApbI2C* i2c, uint8_t* byte); // �ӽ���FIFO��ȡһ���ֽ�����
+
+// APB-I2C��������ʱ����
+void apb_i2c_config_params(ApbI2C* i2c, uint8_t tx_bytes_n_th, uint8_t rx_bytes_n_th, uint8_t scl_div_n);
+
+void apb_i2c_enable_itr(ApbI2C* i2c, uint8_t itr_en); // APB-I2Cʹ���ж�
+void apb_i2c_disable_itr(ApbI2C* i2c); // APB-I2C�����ж�
+uint8_t apb_i2c_get_itr_status(ApbI2C* i2c, uint16_t* tx_bytes_n, uint16_t* rx_bytes_n); // APB-I2C��ȡ�ж�״̬
+void apb_i2c_clear_itr_flag(ApbI2C* i2c); // APB-I2C����жϱ�־

CutestPanda_Opensoc/102_apb_i2c/firmware/examples/apb_i2c_eeprom_example.c

@@ -0,0 +1,101 @@
+/************************************************************************************************************************
+APB-I2Cʾ������
+@brief  ����APB-I2Cʵ��EEPROM��д
+@attention �����Ӳ��ƽ̨�������ӳ�(delay)��ص�API
+@date   2024/08/28
+@author �¼�ҫ
+@eidt   2024/08/28 1.00 �����˵�һ����ʽ�汾
+************************************************************************************************************************/
+
+#include "../apb_i2c.h"
+#include "delay.h"
+
+////////////////////////////////////////////////////////////////////////////////////////////////////////////
+
+#define APB_I2C_BASEADDR 0x40000000 // APB-I2C�������ַ
+
+#define EEPROM_I2C_ADDR 0xA0 // EEPROM I2C�ӻ���ַ
+
+////////////////////////////////////////////////////////////////////////////////////////////////////////////
+
+static ApbI2C i2c; // APB-I2C����ṹ��
+
+////////////////////////////////////////////////////////////////////////////////////////////////////////////
+
+static uint8_t read_eeprom_by_i2c(ApbI2C* i2c, uint8_t slave_addr, uint16_t mem_addr); // ��EEPROM
+static void write_eeprom_by_i2c(ApbI2C* i2c, uint8_t slave_addr, uint16_t mem_addr, uint8_t data); // дEEPROM
+
+////////////////////////////////////////////////////////////////////////////////////////////////////////////
+
+/*************************
+@io
+@public
+@brief  ��EEPROM
+@param  i2c APB-I2C(�ṹ��ָ��)
+        slave_addr I2C�ӻ���ַ
+				mem_addr ��ȡ�ĵ�ַ
+@return ��ȡ�����ֽ�����
+*************************/
+static uint8_t read_eeprom_by_i2c(ApbI2C* i2c, uint8_t slave_addr, uint16_t mem_addr){
+	uint8_t recv_buf;
+	
+	uint8_t send_buf[2] = {(uint8_t)(mem_addr >> 8), (uint8_t)(mem_addr & 0x00FF)};
+	
+	apb_i2c_start_wt_trans(i2c, slave_addr, send_buf, 2); // �������
+	apb_i2c_start_rd_trans(i2c, slave_addr, 1); // ����������
+	
+	while(!apb_i2c_get_rx_byte(i2c, &recv_buf)); // ��ȡ1���ֽ�
+	
+	return recv_buf;
+}
+
+/*************************
+@io
+@public
+@brief  дEEPROM
+@param  i2c APB-I2C(�ṹ��ָ��)
+        slave_addr I2C�ӻ���ַ
+				mem_addr д��ĵ�ַ
+			  data ��д����ֽ�����
+@return none
+*************************/
+static void write_eeprom_by_i2c(ApbI2C* i2c, uint8_t slave_addr, uint16_t mem_addr, uint8_t data){
+	uint8_t send_buf[3] = {(uint8_t)(mem_addr >> 8), (uint8_t)(mem_addr & 0x00FF), data};
+	
+	apb_i2c_start_wt_trans(i2c, slave_addr, send_buf, 3); // �������
+	
+	delay_ms(10); // ��ʱ0.01s
+}
+
+////////////////////////////////////////////////////////////////////////////////////////////////////////////
+
+void apb_i2c_eeprom_example(void){
+	// ��ʼ��APB-I2C
+	apb_i2c_init(&i2c, APB_I2C_BASEADDR);
+	
+	// ��������ʱ����
+	// I2Cʱ�ӷ�Ƶϵ�� = 7
+	apb_i2c_config_params(&i2c, 1, 1, 7);
+	
+	// ���ַ0x00д���ֽ�0x0A
+	write_eeprom_by_i2c(&i2c, EEPROM_I2C_ADDR, 0x00, 0x0A);
+	
+	// ���ַ0x01д���ֽ�0xFE
+	write_eeprom_by_i2c(&i2c, EEPROM_I2C_ADDR, 0x01, 0xFE);
+	
+	// ��ȡ��ַ0x00��0x01
+	uint8_t rdata[2];
+	
+	rdata[0] = read_eeprom_by_i2c(&i2c, EEPROM_I2C_ADDR, 0x00);
+	rdata[1] = read_eeprom_by_i2c(&i2c, EEPROM_I2C_ADDR, 0x01);
+	
+	if((rdata[0] == 0x0A) && (rdata[1] == 0xFE)){
+		// ��д��֤�ɹ�
+		// ...
+	}else{
+		// ��д��֤ʧ��
+		// ...
+	}
+	
+	while(1);
+}

CutestPanda_Opensoc/102_apb_i2c/firmware/examples/delay.c

@@ -0,0 +1,17 @@
+#include "delay.h"
+
+////////////////////////////////////////////////////////////////////////////////////////////////////////////
+
+static uint32_t cnt = 0;
+
+////////////////////////////////////////////////////////////////////////////////////////////////////////////
+
+void SysTick_Handler(void){
+	cnt++;
+}
+
+void delay_ms(uint32_t t){
+	cnt = 0;
+
+	while(cnt != t);
+}

CutestPanda_Opensoc/102_apb_i2c/firmware/examples/delay.h

@@ -0,0 +1,5 @@
+#include <stdint.h>
+
+////////////////////////////////////////////////////////////////////////////////////////////////////////////
+
+void delay_ms(uint32_t t);

CutestPanda_Opensoc/102_apb_i2c/rtl/apb_i2c.v

@@ -0,0 +1,285 @@
+/*
+MIT License
+
+Copyright (c) 2024 Panda, 2257691535@qq.com
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+*/
+
+`timescale 1ns / 1ps
+/********************************************************************
+本模块: 符合APB协议的I2C控制器
+
+描述: 
+APB-I2C控制器
+支持I2C收发中断
+支持7位/10位地址
+
+发送fifo数据包格式：
+    写数据 -> last0 xxxx_xxx0 地址阶段
+             [last0 xxxx_xxxx 地址阶段(仅10位地址时需要)]
+             last0 xxxx_xxxx 数据阶段
+             ...
+             last1 xxxx_xxxx 数据阶段
+    读数据 -> last0 xxxx_xxx1 地址阶段
+             [last0 xxxx_xxxx 地址阶段(仅10位地址时需要)]
+             last1 8位待读取字节数
+
+寄存器->
+    偏移量  |    含义                     |   读写特性    |                 备注
+    0x00    0:发送fifo是否满                    R
+            1:发送fifo写使能                    W         写该寄存器且该位为1'b1时产生发送fifo写使能
+            10~2:发送fifo写数据                 W                 {last(1bit), data(8bit)}
+            16:接收fifo是否空                   R
+            17:接收fifo读使能                   W         写该寄存器且该位为1'b1时产生接收fifo读使能
+            25~18:接收fifo读数据                R
+    0x04    0:I2C全局中断使能                   W
+            8:I2C发送指定字节数中断使能         W
+            9:I2C从机响应错误中断使能           W
+            10:I2C接收指定字节数中断使能        W
+            11:I2C接收溢出中断使能              W
+    0x08    7~0:I2C发送中断字节数阈值           W                  发送字节数 > 阈值时发生中断
+            15~8:I2C接收中断字节数阈值          W                  接收字节数 > 阈值时发生中断
+			23~16:I2C时钟分频系数               W                  分频数 = (分频系数 + 1) * 2
+			                                                              分频系数应>=1
+    0x0C    0:I2C全局中断标志                  RWC                 请在中断服务函数中清除中断标志
+            1:I2C发送指定字节数中断标志         R
+            2:I2C从机响应错误中断标志           R
+            3:I2C接收指定字节数中断标志         R
+            4:I2C接收溢出中断标志               R
+            19~8:I2C发送字节数                RWC                  每当发送一个I2C数据包后更新
+            31~20:I2C接收字节数               RWC                  每当接收一个I2C数据包后更新
+
+注意：
+I2C发送/接收指定字节数中断每当发送/接收一个I2C数据包后判断
+每个I2C数据包不能超过15字节
+
+协议:
+APB SLAVE
+I2C MASTER
+
+作者: 陈家耀
+日期: 2024/06/14
+********************************************************************/
+
+
+module apb_i2c #(
+    parameter integer addr_bits_n = 7, // 地址位数(7|10)
+	parameter en_i2c_rx = "true", // 是否使能i2c接收
+    parameter tx_rx_fifo_ram_type = "bram", // 发送接收fifo的RAM类型(lutram|bram)
+    parameter integer tx_fifo_depth = 1024, // 发送fifo深度(32|64|128|...)
+    parameter integer rx_fifo_depth = 1024, // 接收fifo深度(32|64|128|...)
+    parameter real simulation_delay = 1 // 仿真延时
+)(
+    // 时钟和复位
+    input wire clk,
+    input wire resetn,
+    
+    // APB从机接口
+    input wire[31:0] paddr,
+    input wire psel,
+    input wire penable,
+    input wire pwrite,
+    input wire[31:0] pwdata,
+    output wire pready_out, // const -> 1'b1
+    output wire[31:0] prdata_out,
+    output wire pslverr_out, // const -> 1'b0
+    
+    // I2C主机接口
+    // scl
+    output wire scl_t, // 1'b1为输入, 1'b0为输出
+    input wire scl_i,
+    output wire scl_o,
+    // sda
+    output wire sda_t, // 1'b1为输入, 1'b0为输出
+    input wire sda_i,
+    output wire sda_o,
+    
+    // 中断信号
+    output wire itr
+);
+	
+    /** 收发fifo **/
+    // 发送fifo写端口
+    wire[8:0] tx_fifo_din;
+    wire tx_fifo_wen;
+    wire tx_fifo_full;
+    // 发送fifo读端口
+    wire tx_fifo_ren;
+    wire tx_fifo_empty;
+    wire[7:0] tx_fifo_dout;
+    wire tx_fifo_dout_last;
+    // 接收fifo写端口
+    wire rx_fifo_wen;
+    wire rx_fifo_full;
+    wire[7:0] rx_fifo_din;
+    // 接收fifo读端口
+    wire rx_fifo_ren;
+    wire rx_fifo_empty;
+    wire[7:0] rx_fifo_dout;
+    
+    // 发送fifo
+    ram_fifo_wrapper #(
+        .fwft_mode("false"),
+        .ram_type(tx_rx_fifo_ram_type),
+        .en_bram_reg("false"),
+        .fifo_depth(tx_fifo_depth),
+        .fifo_data_width(9),
+        .full_assert_polarity("high"),
+        .empty_assert_polarity("high"),
+        .almost_full_assert_polarity("no"),
+        .almost_empty_assert_polarity("no"),
+        .en_data_cnt("false"),
+        .almost_full_th(),
+        .almost_empty_th(),
+        .simulation_delay(simulation_delay)
+    )tx_fifo(
+        .clk(clk),
+        .rst_n(resetn),
+        .fifo_wen(tx_fifo_wen),
+        .fifo_din(tx_fifo_din),
+        .fifo_full(tx_fifo_full),
+        .fifo_ren(tx_fifo_ren),
+        .fifo_dout({tx_fifo_dout_last, tx_fifo_dout}),
+        .fifo_empty(tx_fifo_empty)
+    );
+    
+    // 接收fifo
+	generate
+		if(en_i2c_rx == "true")
+		begin
+			ram_fifo_wrapper #(
+				.fwft_mode("false"),
+				.ram_type(tx_rx_fifo_ram_type),
+				.en_bram_reg("false"),
+				.fifo_depth(rx_fifo_depth),
+				.fifo_data_width(8),
+				.full_assert_polarity("high"),
+				.empty_assert_polarity("high"),
+				.almost_full_assert_polarity("no"),
+				.almost_empty_assert_polarity("no"),
+				.en_data_cnt("false"),
+				.almost_full_th(),
+				.almost_empty_th(),
+				.simulation_delay(simulation_delay)
+			)rx_fifo(
+				.clk(clk),
+				.rst_n(resetn),
+				.fifo_wen(rx_fifo_wen),
+				.fifo_din(rx_fifo_din),
+				.fifo_full(rx_fifo_full),
+				.fifo_ren(rx_fifo_ren),
+				.fifo_dout(rx_fifo_dout),
+				.fifo_empty(rx_fifo_empty)
+			);
+		end
+		else
+		begin
+			assign rx_fifo_full = 1'b0;
+			
+			assign rx_fifo_dout = 8'dx;
+			assign rx_fifo_empty = 1'b1;
+		end
+	endgenerate
+    
+    /** 寄存器接口和中断处理 **/
+	// I2C时钟分频系数
+    wire[7:0] i2c_scl_div_rate;
+    // I2C发送完成指示
+    wire i2c_tx_done;
+    wire[3:0] i2c_tx_bytes_n;
+    // I2C接收完成指示
+    wire i2c_rx_done;
+    wire[3:0] i2c_rx_bytes_n;
+    // I2C从机响应错误
+    wire i2c_slave_resp_err;
+    // I2C接收溢出
+    wire i2c_rx_overflow;
+    
+    // 寄存器接口和中断处理
+    regs_if_for_i2c #(
+        .simulation_delay(simulation_delay)
+    )regs_if_for_i2c_u(
+        .clk(clk),
+        .resetn(resetn),
+        
+        .paddr(paddr),
+        .psel(psel),
+        .penable(penable),
+        .pwrite(pwrite),
+        .pwdata(pwdata),
+        .pready_out(pready_out),
+        .prdata_out(prdata_out),
+        .pslverr_out(pslverr_out),
+        
+        .tx_fifo_wen(tx_fifo_wen),
+        .tx_fifo_din(tx_fifo_din),
+        .tx_fifo_full(tx_fifo_full),
+        
+        .rx_fifo_ren(rx_fifo_ren),
+        .rx_fifo_dout(rx_fifo_dout),
+        .rx_fifo_empty(rx_fifo_empty),
+        
+        .i2c_scl_div_rate(i2c_scl_div_rate),
+        
+        .i2c_tx_done(i2c_tx_done),
+        .i2c_tx_bytes_n(i2c_tx_bytes_n),
+        .i2c_rx_done(i2c_rx_done),
+        .i2c_rx_bytes_n(i2c_rx_bytes_n),
+        .i2c_slave_resp_err(i2c_slave_resp_err),
+        .i2c_rx_overflow(i2c_rx_overflow),
+        
+        .itr(itr)
+    );
+    
+    /** I2C控制器 **/
+    i2c_ctrler #(
+        .addr_bits_n(addr_bits_n),
+        .simulation_delay(simulation_delay)
+    )i2c_ctrler_u(
+        .clk(clk),
+        .resetn(resetn),
+        
+        .i2c_scl_div_rate(i2c_scl_div_rate),
+        
+        .tx_fifo_ren(tx_fifo_ren),
+        .tx_fifo_empty(tx_fifo_empty),
+        .tx_fifo_dout(tx_fifo_dout),
+        .tx_fifo_dout_last(tx_fifo_dout_last),
+        
+        .rx_fifo_wen(rx_fifo_wen),
+        .rx_fifo_full(rx_fifo_full),
+        .rx_fifo_din(rx_fifo_din),
+        
+        .i2c_tx_done(i2c_tx_done),
+        .i2c_tx_bytes_n(i2c_tx_bytes_n),
+        .i2c_rx_done(i2c_rx_done),
+        .i2c_rx_bytes_n(i2c_rx_bytes_n),
+        .i2c_slave_resp_err(i2c_slave_resp_err),
+        .i2c_rx_overflow(i2c_rx_overflow),
+        
+        .scl_t(scl_t),
+        .scl_i(scl_i),
+        .scl_o(scl_o),
+        .sda_t(sda_t),
+        .sda_i(sda_i),
+        .sda_o(sda_o)
+    );
+    
+endmodule

CutestPanda_Opensoc/102_apb_i2c/rtl/bram_simple_dual_port.v

@@ -0,0 +1,132 @@
+/*
+MIT License
+
+Copyright (c) 2024 Panda, 2257691535@qq.com
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+*/
+
+`timescale 1ns / 1ps
+/********************************************************************
+本模块: 简单双端口Bram
+
+描述: 
+可选读延迟1clk或2clk
+
+注意：
+无
+
+协议:
+MEM READ/WRITE
+
+作者: 陈家耀
+日期: 2022/1/11
+********************************************************************/
+
+
+module bram_simple_dual_port #(
+    parameter style = "HIGH_PERFORMANCE", // 存储器样式(HIGH_PERFORMANCE|LOW_LATENCY)
+    parameter integer mem_width = 32, // 存储器位宽
+    parameter integer mem_depth = 4096, // 存储器深度
+    parameter INIT_FILE = "no_init", // 初始化文件路径
+    parameter integer simulation_delay = 1 // 仿真延时
+)
+(
+    // clk
+    input wire clk,
+    
+    // mem write
+    input wire wen_a,
+    input wire[clogb2(mem_depth-1):0] addr_a,
+    input wire[mem_width-1:0] din_a,
+    
+    // mem read
+    input wire ren_b,
+    input wire[clogb2(mem_depth-1):0] addr_b,
+    output wire[mem_width-1:0] dout_b
+);
+
+    // 计算bit_depth的最高有效位编号(即位数-1)             
+    function integer clogb2 (input integer bit_depth);              
+    begin                                                           
+        for(clogb2=-1; bit_depth>0; clogb2=clogb2+1)                   
+          bit_depth = bit_depth >> 1;                                 
+        end                                        
+    endfunction
+    
+    (* ram_style="block" *) reg[mem_width-1:0] mem[mem_depth-1:0]; // 存储器
+    reg[mem_width-1:0] ram_data_b;
+    
+    generate
+        if (INIT_FILE != "")
+        begin
+            if(INIT_FILE == "default")
+            begin
+                integer ram_index;
+                initial
+                for (ram_index = 0; ram_index < mem_depth; ram_index = ram_index + 1)
+                    mem[ram_index] = ram_index;
+            end
+            else if(INIT_FILE != "no_init")
+            begin
+                initial
+                    $readmemh(INIT_FILE, mem, 0, mem_depth - 1);
+            end
+        end
+        else
+        begin
+            integer ram_index;
+            initial
+            for (ram_index = 0; ram_index < mem_depth; ram_index = ram_index + 1)
+                mem[ram_index] = {mem_width{1'b0}};
+        end
+    endgenerate
+    
+    // 读写控制逻辑
+    always @(posedge clk)
+    begin
+        if(wen_a)
+            # simulation_delay mem[addr_a] <= din_a;
+    end
+    
+    always @(posedge clk)
+    begin
+        if(ren_b)
+            # simulation_delay ram_data_b <= mem[addr_b];
+    end
+    
+    generate
+        if(style == "HIGH_PERFORMANCE")
+        begin
+            // 使用输出寄存器
+            reg[mem_width-1:0] data_b;
+            
+            assign dout_b = data_b;
+            
+            always @(posedge clk)
+                #simulation_delay data_b <= ram_data_b;
+        end
+        else
+        begin
+            // 不使用输出寄存器
+            assign dout_b = ram_data_b;
+        end
+    endgenerate
+    
+endmodule

CutestPanda_Opensoc/102_apb_i2c/rtl/dram_simple_dual_port.v

@@ -0,0 +1,129 @@
+/*
+MIT License
+
+Copyright (c) 2024 Panda, 2257691535@qq.com
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+*/
+
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// 项目: 简单双端口Dram
+/* 
+描述: 
+可选的输出寄存器
+*/
+/*
+注意：
+无
+*/
+// 作者: 陈家耀
+// 日期: 2022/1/13
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module dram_simple_dual_port #(
+    parameter integer mem_width = 24, // 存储器位宽
+    parameter integer mem_depth = 32, // 存储器深度
+    parameter INIT_FILE = "no_init", // 初始化文件路径
+    parameter use_output_register = "true", // 是否使用输出寄存器
+    parameter output_register_init_v = 0, // 输出寄存器复位值
+    parameter real simulation_delay = 10 // 仿真时用的延时
+)(
+    // 时钟和复位
+    input wire clk,
+    input wire rst_n,
+    
+    // mem
+    // write port
+    input wire wen_a,
+    input wire[clogb2(mem_depth-1):0] addr_a,
+    input wire[mem_width-1:0] din_a,
+    // read port
+    input wire ren_b,
+    input wire[clogb2(mem_depth-1):0] addr_b,
+    output wire[mem_width-1:0] dout_b
+);
+
+    // 计算bit_depth的最高有效位编号(即位数-1)
+    function integer clogb2 (input integer bit_depth);
+        integer temp;
+    begin
+        temp = bit_depth;
+        for(clogb2 = -1;temp > 0;clogb2 = clogb2 + 1)                   
+            temp = temp >> 1;                                 
+        end                                        
+    endfunction
+    
+    (* ram_style="distributed" *) reg[mem_width-1:0] mem[mem_depth-1:0]; // 存储器
+    
+    generate
+    if (INIT_FILE != "")
+    begin
+        if(INIT_FILE != "no_init")
+        begin
+            initial
+                $readmemh(INIT_FILE, mem, 0, mem_depth - 1);
+        end
+    end
+    else
+    begin
+        integer ram_index;
+        initial
+        for (ram_index = 0; ram_index < mem_depth; ram_index = ram_index + 1)
+            mem[ram_index] = {mem_width{1'b0}};
+    end
+    endgenerate
+    
+    // 读写控制逻辑
+    generate
+        if(use_output_register == "true")
+        begin
+            reg[mem_width-1:0] dout_b_regs;
+            
+            assign dout_b = dout_b_regs;
+            
+            always @(posedge clk)
+            begin
+                if(wen_a)
+                    # simulation_delay mem[addr_a] <= din_a;
+            end
+            
+            always @(posedge clk or negedge rst_n)
+            begin
+                if(~rst_n)
+                    dout_b_regs <= output_register_init_v;
+                else if(ren_b)
+                    # simulation_delay dout_b_regs <= mem[addr_b];
+            end
+        end
+        else
+        begin
+            always @(posedge clk)
+            begin
+                # simulation_delay;
+                if(wen_a)
+                    mem[addr_a] <= din_a;
+            end
+            
+            assign dout_b = mem[addr_b];
+        end
+    endgenerate
+
+endmodule

CutestPanda_Opensoc/102_apb_i2c/rtl/fifo_base_on_ram.v

@@ -0,0 +1,200 @@
+/*
+MIT License
+
+Copyright (c) 2024 Panda, 2257691535@qq.com
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+*/
+
+`timescale 1ns / 1ps
+/********************************************************************
+本模块: 基于ram的同步fifo控制器
+
+描述: 
+全流水的高性能同步fifo控制器
+基于ram
+支持first word fall through特性(READ LA = 0)
+可选的固定阈值将满/将空信号
+
+注意：
+将满信号当存储计数 >= almost_full_th时有效
+将空信号当存储计数 <= almost_empty_th时有效
+almost_full_th和almost_empty_th必须在[1, fifo_depth-1]范围内
+不使能FWFT时, 要求ram的读延迟=1或2clk; 使能FWFT时, 要求ram的读延迟=1clk
+
+协议:
+FIFO WRITE/READ
+MEM WRITE/READ
+
+作者: 陈家耀
+日期: 2023/10/29
+********************************************************************/
+
+
+module fifo_based_on_ram #(
+    parameter fwft_mode = "true", // 是否启用first word fall through特性
+    parameter ram_read_la = 1, // ram读延迟(1|2)(仅在不使能FWFT时可用)
+    parameter integer fifo_depth = 32, // fifo深度(必须为2|4|8|16|...)
+    parameter integer fifo_data_width = 32, // fifo位宽
+    parameter integer almost_full_th = 20, // fifo将满阈值
+    parameter integer almost_empty_th = 5, // fifo将空阈值
+    parameter real simulation_delay = 1 // 仿真延时
+)(
+    // 时钟和复位
+    input wire clk,
+    input wire rst_n,
+    
+    // FIFO WRITE(fifo写端口)
+    input wire fifo_wen,
+    input wire[fifo_data_width-1:0] fifo_din,
+    output wire fifo_full,
+    output wire fifo_full_n,
+    output wire fifo_almost_full,
+    output wire fifo_almost_full_n,
+    
+    // FIFO READ(fifo读端口)
+    input wire fifo_ren,
+    output wire[fifo_data_width-1:0] fifo_dout,
+    output wire fifo_empty,
+    output wire fifo_empty_n,
+    output wire fifo_almost_empty,
+    output wire fifo_almost_empty_n,
+    
+    // MEM WRITE(ram写端口)
+    output wire ram_wen,
+    output wire[clogb2(fifo_depth-1):0] ram_w_addr,
+    output wire[fifo_data_width-1:0] ram_din,
+    
+    // MEM RAD(ram读端口)
+    output wire ram_ren,
+    output wire[clogb2(fifo_depth-1):0] ram_r_addr,
+    input wire[fifo_data_width-1:0] ram_dout,
+    
+    // 存储计数
+    output wire[clogb2(fifo_depth):0] data_cnt
+);
+
+    // 计算log2(bit_depth)               
+    function integer clogb2 (input integer bit_depth);
+        integer temp;
+    begin
+        temp = bit_depth;
+        for(clogb2 = -1;temp > 0;clogb2 = clogb2 + 1)                   
+            temp = temp >> 1;                                 
+    end                                        
+    endfunction
+    
+    /** 主fifo **/
+    wire m_fifo_ren;
+    wire[fifo_data_width-1:0] m_fifo_dout;
+    wire m_fifo_empty_n;
+    
+    generate
+        if(fwft_mode == "true")
+        begin
+            // FWFT模式
+            fifo_based_on_ram_std #(
+                .fifo_depth(fifo_depth),
+                .fifo_data_width(fifo_data_width),
+                .almost_full_th(almost_full_th),
+                .almost_empty_th(almost_empty_th),
+                .simulation_delay(simulation_delay)
+            )fifo_based_on_ram_std_u(
+                .clk(clk),
+                .rst_n(rst_n),
+                .fifo_wen(fifo_wen),
+                .fifo_din(fifo_din),
+                .fifo_full(fifo_full),
+                .fifo_full_n(fifo_full_n),
+                .fifo_almost_full(fifo_almost_full),
+                .fifo_almost_full_n(fifo_almost_full_n),
+                .fifo_ren(m_fifo_ren),
+                .fifo_dout(m_fifo_dout),
+                .fifo_empty(),
+                .fifo_empty_n(m_fifo_empty_n),
+                .fifo_almost_empty(fifo_almost_empty),
+                .fifo_almost_empty_n(fifo_almost_empty_n),
+                .ram_wen(ram_wen),
+                .ram_w_addr(ram_w_addr),
+                .ram_din(ram_din),
+                .ram_ren(ram_ren),
+                .ram_r_addr(ram_r_addr),
+                .ram_dout(ram_dout),
+                .data_cnt(data_cnt)
+            );
+        end
+        else
+        begin
+            // 标准模式
+            fifo_based_on_ram_std #(
+                .fifo_depth(fifo_depth),
+                .fifo_data_width(fifo_data_width),
+                .almost_full_th(almost_full_th),
+                .almost_empty_th(almost_empty_th),
+                .simulation_delay(simulation_delay)
+            )fifo_based_on_ram_std_u(
+                .clk(clk),
+                .rst_n(rst_n),
+                .fifo_wen(fifo_wen),
+                .fifo_din(fifo_din),
+                .fifo_full(fifo_full),
+                .fifo_full_n(fifo_full_n),
+                .fifo_almost_full(fifo_almost_full),
+                .fifo_almost_full_n(fifo_almost_full_n),
+                .fifo_ren(fifo_ren),
+                .fifo_dout(fifo_dout),
+                .fifo_empty(fifo_empty),
+                .fifo_empty_n(fifo_empty_n),
+                .fifo_almost_empty(fifo_almost_empty),
+                .fifo_almost_empty_n(fifo_almost_empty_n),
+                .ram_wen(ram_wen),
+                .ram_w_addr(ram_w_addr),
+                .ram_din(ram_din),
+                .ram_ren(ram_ren),
+                .ram_r_addr(ram_r_addr),
+                .ram_dout(ram_dout),
+                .data_cnt(data_cnt)
+            );
+        end
+    endgenerate
+    
+    /** 从fifo(仅FWFT模式下需要) **/
+    generate
+        if(fwft_mode == "true")
+        begin
+            fifo_show_ahead_buffer #(
+                .fifo_data_width(fifo_data_width),
+                .simulation_delay(simulation_delay)
+            )fifo_show_ahead_buffer_u(
+                .clk(clk),
+                .rst_n(rst_n),
+                
+                .std_fifo_ren(m_fifo_ren),
+                .std_fifo_dout(m_fifo_dout),
+                .std_fifo_empty(~m_fifo_empty_n),
+                
+                .fwft_fifo_ren(fifo_ren),
+                .fwft_fifo_dout(fifo_dout),
+                .fwft_fifo_empty(fifo_empty),
+                .fwft_fifo_empty_n(fifo_empty_n)
+            );
+        end
+    endgenerate
+    
+endmodule

CutestPanda_Opensoc/102_apb_i2c/rtl/fifo_based_on_lutram.v

@@ -0,0 +1,235 @@
+/*
+MIT License
+
+Copyright (c) 2024 Panda, 2257691535@qq.com
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+*/
+
+`timescale 1ns / 1ps
+/********************************************************************
+本模块: 基于lutram的同步fifo
+
+描述: 
+全流水的高性能同步fifo
+基于lutram
+支持first word fall through特性(READ LA = 0)
+可选的固定阈值将满/将空信号
+
+注意：
+将满信号当存储计数 >= almost_full_th时有效
+将空信号当存储计数 <= almost_empty_th时有效
+almost_full_th和almost_empty_th必须在[1, fifo_depth-1]范围内
+
+协议:
+FIFO WRITE/READ
+
+作者: 陈家耀
+日期: 2023/10/13
+********************************************************************/
+
+
+module fifo_based_on_lutram #(
+    parameter fwft_mode = "true", // 是否启用first word fall through特性
+    parameter integer fifo_depth = 32, // fifo深度(必须为2|4|8|16|...)
+    parameter integer fifo_data_width = 32, // fifo位宽
+    parameter integer almost_full_th = 20, // fifo将满阈值
+    parameter integer almost_empty_th = 5, // fifo将空阈值
+    parameter real simulation_delay = 1 // 仿真延时
+)(
+    // 时钟和复位
+    input wire clk,
+    input wire rst_n,
+    
+    // FIFO WRITE(fifo写端口)
+    input wire fifo_wen,
+    input wire[fifo_data_width-1:0] fifo_din,
+    output wire fifo_full,
+    output wire fifo_full_n,
+    output wire fifo_almost_full,
+    output wire fifo_almost_full_n,
+    
+    // FIFO READ(fifo读端口)
+    input wire fifo_ren,
+    output wire[fifo_data_width-1:0] fifo_dout,
+    output wire fifo_empty,
+    output wire fifo_empty_n,
+    output wire fifo_almost_empty,
+    output wire fifo_almost_empty_n,
+    
+    // 存储计数
+    output wire[clogb2(fifo_depth):0] data_cnt
+);
+
+    // 计算log2(bit_depth)               
+    function integer clogb2 (input integer bit_depth);
+        integer temp;
+    begin
+        temp = bit_depth;
+        for(clogb2 = -1;temp > 0;clogb2 = clogb2 + 1)                   
+            temp = temp >> 1;                                 
+    end                                        
+    endfunction
+    
+    /** 参数 **/
+    localparam integer use_cnt_th = 8;
+    
+    /** 空满标志和存储计数 **/
+    reg fifo_empty_reg;
+    reg fifo_full_reg;
+    reg fifo_almost_empty_reg;
+    reg fifo_almost_full_reg;
+    reg fifo_empty_n_reg;
+    reg fifo_full_n_reg;
+    reg fifo_almost_empty_n_reg;
+    reg fifo_almost_full_n_reg;
+    reg[clogb2(fifo_depth):0] data_cnt_regs;
+    reg[fifo_depth:0] data_cnt_onehot_regs;
+    
+    assign {fifo_empty, fifo_full} = {fifo_empty_reg, fifo_full_reg};
+    assign {fifo_empty_n, fifo_full_n} = {fifo_empty_n_reg, fifo_full_n_reg};
+    assign {fifo_almost_empty, fifo_almost_full} = {fifo_almost_empty_reg, fifo_almost_full_reg};
+    assign {fifo_almost_empty_n, fifo_almost_full_n} = {fifo_almost_empty_n_reg, fifo_almost_full_n_reg};
+    assign data_cnt = data_cnt_regs;
+    
+    always @(posedge clk or negedge rst_n)
+    begin
+        if(~rst_n)
+        begin
+            fifo_empty_reg <= 1'b1;
+            fifo_empty_n_reg <= 1'b0;
+            fifo_full_reg <= 1'b0;
+            fifo_full_n_reg <= 1'b1;
+            fifo_almost_empty_reg <= 1'b1;
+            fifo_almost_empty_n_reg <= 1'b0;
+            fifo_almost_full_reg <= 1'b0;
+            fifo_almost_full_n_reg <= 1'b1;
+            
+            data_cnt_regs <= 0;
+            data_cnt_onehot_regs <= 1;
+        end
+        else if((fifo_wen & fifo_full_n_reg) ^ (fifo_ren & fifo_empty_n_reg))
+		begin
+            # simulation_delay;
+			
+            if(fifo_wen & fifo_full_n_reg)
+            begin
+                // fifo数据增加1个
+                fifo_empty_reg <= 1'b0;
+                fifo_empty_n_reg <= 1'b1;
+                fifo_full_reg <= (fifo_depth >= use_cnt_th) ? data_cnt_regs == fifo_depth - 1:data_cnt_onehot_regs[fifo_depth-1];
+                fifo_full_n_reg <= (fifo_depth >= use_cnt_th) ? data_cnt_regs != fifo_depth - 1:(~data_cnt_onehot_regs[fifo_depth-1]);
+                fifo_almost_empty_reg <= (data_cnt_regs <= almost_empty_th - 1);
+                fifo_almost_empty_n_reg <= ~(data_cnt_regs <= almost_empty_th - 1);
+                fifo_almost_full_reg <= (data_cnt_regs >= almost_full_th - 1);
+                fifo_almost_full_n_reg <= ~(data_cnt_regs >= almost_full_th - 1);
+                
+                data_cnt_regs <= data_cnt_regs + 1;
+                data_cnt_onehot_regs <= {data_cnt_onehot_regs[fifo_depth-1:0], 1'b0}; // 左移
+            end
+            else
+            begin
+                // fifo数据减少1个
+                fifo_empty_reg <= (fifo_depth >= use_cnt_th) ? data_cnt_regs == 1:data_cnt_onehot_regs[1];
+                fifo_empty_n_reg <= (fifo_depth >= use_cnt_th) ? data_cnt_regs != 1:(~data_cnt_onehot_regs[1]);
+                fifo_full_reg <= 1'b0;
+                fifo_full_n_reg <= 1'b1;
+                fifo_almost_empty_reg <= (data_cnt_regs <= almost_empty_th + 1);
+                fifo_almost_empty_n_reg <= ~(data_cnt_regs <= almost_empty_th + 1);
+                fifo_almost_full_reg <= (data_cnt_regs >= almost_full_th + 1);
+                fifo_almost_full_n_reg <= ~(data_cnt_regs >= almost_full_th + 1);
+                
+                data_cnt_regs <= data_cnt_regs - 1;
+                data_cnt_onehot_regs <= {1'b0, data_cnt_onehot_regs[fifo_depth:1]}; // 右移
+            end
+        end
+    end
+    
+    /** 读写指针 **/
+    reg[clogb2(fifo_depth-1):0] fifo_rptr;
+    reg[clogb2(fifo_depth-1):0] fifo_rptr_add1;
+    reg[clogb2(fifo_depth-1):0] fifo_wptr;
+    reg[fifo_depth-1:0] fifo_wptr_onehot;
+    
+    always @(posedge clk or negedge rst_n)
+    begin
+        if(~rst_n)
+            fifo_rptr <= 0;
+        else if(fifo_ren & fifo_empty_n_reg)
+            #simulation_delay fifo_rptr <= fifo_rptr + 1;
+    end
+    
+    always @(posedge clk or negedge rst_n)
+    begin
+        if(~rst_n)
+            fifo_rptr_add1 <= 1;
+        else if(fifo_ren & fifo_empty_n_reg)
+            #simulation_delay fifo_rptr_add1 <= fifo_rptr_add1 + 1;
+    end
+    
+    always @(posedge clk or negedge rst_n)
+    begin
+        if(~rst_n)
+            fifo_wptr <= 0;
+        else if(fifo_wen & fifo_full_n_reg)
+            #simulation_delay fifo_wptr <= fifo_wptr + 1;
+    end
+    
+    always @(posedge clk or negedge rst_n)
+    begin
+        if(~rst_n)
+            fifo_wptr_onehot <= 1;
+        else if(fifo_wen & fifo_full_n_reg)
+            #simulation_delay fifo_wptr_onehot <= {fifo_wptr_onehot[fifo_depth-2:0], fifo_wptr_onehot[fifo_depth-1]}; // 循环左移
+    end
+    
+    /** 读写数据 **/
+    (* ram_style="distributed" *) reg[fifo_data_width-1:0] fifo_regs[fifo_depth-1:0];
+    reg[fifo_data_width-1:0] fifo_dout_regs;
+    
+    assign fifo_dout = fifo_dout_regs;
+    
+    always @(posedge clk)
+    begin
+        if(fifo_wen & fifo_full_n_reg)
+            #simulation_delay fifo_regs[fifo_wptr] <= fifo_din;
+    end
+    
+    generate
+        if(fwft_mode == "true")
+        begin
+            always @(posedge clk)
+            begin
+                if({fifo_empty_n_reg, fifo_ren} != 2'b10)
+                    #simulation_delay fifo_dout_regs <= fifo_empty_n_reg & (~(fifo_wen & ((fifo_depth >= use_cnt_th) ? data_cnt_regs == 1:data_cnt_onehot_regs[1]))) ?
+                        fifo_regs[fifo_rptr_add1]:fifo_din;
+            end
+        end
+        else
+        begin
+            always @(posedge clk)
+            begin
+                if(fifo_ren & fifo_empty_n_reg)
+                    #simulation_delay fifo_dout_regs <= fifo_regs[fifo_rptr];
+            end
+        end
+    endgenerate
+
+endmodule
+

CutestPanda_Opensoc/102_apb_i2c/rtl/fifo_based_on_ram_std.v

@@ -0,0 +1,223 @@
+/*
+MIT License
+
+Copyright (c) 2024 Panda, 2257691535@qq.com
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+*/
+
+`timescale 1ns / 1ps
+/********************************************************************
+本模块: 基于ram的标准同步fifo控制器
+
+描述: 
+全流水的高性能同步fifo控制器
+基于ram
+标准fifo(READ LA = 1|2)
+可选的固定阈值将满/将空信号
+
+注意：
+将满信号当存储计数 >= almost_full_th时有效
+将空信号当存储计数 <= almost_empty_th时有效
+almost_full_th和almost_empty_th必须在[1, fifo_depth-1]范围内
+要求ram的读延迟=1clk
+
+协议:
+FIFO WRITE/READ
+MEM WRITE/READ
+
+作者: 陈家耀
+日期: 2023/10/29
+********************************************************************/
+
+
+module fifo_based_on_ram_std #(
+    parameter integer fifo_depth = 32, // fifo深度(必须为2|4|8|16|...)
+    parameter integer fifo_data_width = 32, // fifo位宽
+    parameter integer almost_full_th = 20, // fifo将满阈值
+    parameter integer almost_empty_th = 5, // fifo将空阈值
+    parameter real simulation_delay = 1 // 仿真延时
+)(
+    // 时钟和复位
+    input wire clk,
+    input wire rst_n,
+    
+    // FIFO WRITE(fifo写端口)
+    input wire fifo_wen,
+    input wire[fifo_data_width-1:0] fifo_din,
+    output wire fifo_full,
+    output wire fifo_full_n,
+    output wire fifo_almost_full,
+    output wire fifo_almost_full_n,
+    
+    // FIFO READ(fifo读端口)
+    input wire fifo_ren,
+    output wire[fifo_data_width-1:0] fifo_dout,
+    output wire fifo_empty,
+    output wire fifo_empty_n,
+    output wire fifo_almost_empty,
+    output wire fifo_almost_empty_n,
+    
+    // MEM WRITE(ram写端口)
+    output wire ram_wen,
+    output wire[clogb2(fifo_depth-1):0] ram_w_addr,
+    output wire[fifo_data_width-1:0] ram_din,
+    
+    // MEM RAD(ram读端口)
+    output wire ram_ren,
+    output wire[clogb2(fifo_depth-1):0] ram_r_addr,
+    input wire[fifo_data_width-1:0] ram_dout,
+    
+    // 存储计数
+    output wire[clogb2(fifo_depth):0] data_cnt
+);
+
+    // 计算log2(bit_depth)               
+    function integer clogb2 (input integer bit_depth);
+        integer temp;
+    begin
+        temp = bit_depth;
+        for(clogb2 = -1;temp > 0;clogb2 = clogb2 + 1)                   
+            temp = temp >> 1;                                 
+    end                                        
+    endfunction
+    
+    /** 参数 **/
+    localparam integer use_cnt_th = 8;
+    
+    /** 空满标志和存储计数 **/
+    reg fifo_empty_reg;
+    reg fifo_full_reg;
+    reg fifo_almost_empty_reg;
+    reg fifo_almost_full_reg;
+    reg fifo_empty_n_reg;
+    reg fifo_full_n_reg;
+    reg fifo_almost_empty_n_reg;
+    reg fifo_almost_full_n_reg;
+    reg[clogb2(fifo_depth):0] data_cnt_regs;
+    reg[fifo_depth:0] data_cnt_onehot_regs;
+    
+    assign {fifo_empty, fifo_full} = {fifo_empty_reg, fifo_full_reg};
+    assign {fifo_empty_n, fifo_full_n} = {fifo_empty_n_reg, fifo_full_n_reg};
+    assign {fifo_almost_empty, fifo_almost_full} = {fifo_almost_empty_reg, fifo_almost_full_reg};
+    assign {fifo_almost_empty_n, fifo_almost_full_n} = {fifo_almost_empty_n_reg, fifo_almost_full_n_reg};
+    assign data_cnt = data_cnt_regs;
+    
+    always @(posedge clk or negedge rst_n)
+    begin
+        if(~rst_n)
+        begin
+            fifo_empty_reg <= 1'b1;
+            fifo_empty_n_reg <= 1'b0;
+            fifo_full_reg <= 1'b0;
+            fifo_full_n_reg <= 1'b1;
+            fifo_almost_empty_reg <= 1'b1;
+            fifo_almost_empty_n_reg <= 1'b0;
+            fifo_almost_full_reg <= 1'b0;
+            fifo_almost_full_n_reg <= 1'b1;
+            
+            data_cnt_regs <= 0;
+            data_cnt_onehot_regs <= 1;
+        end
+        else if((fifo_wen & fifo_full_n_reg) ^ (fifo_ren & fifo_empty_n_reg))
+		begin
+            # simulation_delay;
+			
+            if(fifo_wen & fifo_full_n_reg)
+            begin
+                // fifo数据增加1个
+                fifo_empty_reg <= 1'b0;
+                fifo_empty_n_reg <= 1'b1;
+                fifo_full_reg <= (fifo_depth >= use_cnt_th) ? data_cnt_regs == fifo_depth - 1:data_cnt_onehot_regs[fifo_depth-1];
+                fifo_full_n_reg <= (fifo_depth >= use_cnt_th) ? data_cnt_regs != fifo_depth - 1:(~data_cnt_onehot_regs[fifo_depth-1]);
+                fifo_almost_empty_reg <= (data_cnt_regs <= almost_empty_th - 1);
+                fifo_almost_empty_n_reg <= ~(data_cnt_regs <= almost_empty_th - 1);
+                fifo_almost_full_reg <= (data_cnt_regs >= almost_full_th - 1);
+                fifo_almost_full_n_reg <= ~(data_cnt_regs >= almost_full_th - 1);
+                
+                data_cnt_regs <= data_cnt_regs + 1;
+                data_cnt_onehot_regs <= {data_cnt_onehot_regs[fifo_depth-1:0], 1'b0}; // 左移
+            end
+            else
+            begin
+                // fifo数据减少1个
+                fifo_empty_reg <= (fifo_depth >= use_cnt_th) ? data_cnt_regs == 1:data_cnt_onehot_regs[1];
+                fifo_empty_n_reg <= (fifo_depth >= use_cnt_th) ? data_cnt_regs != 1:(~data_cnt_onehot_regs[1]);
+                fifo_full_reg <= 1'b0;
+                fifo_full_n_reg <= 1'b1;
+                fifo_almost_empty_reg <= (data_cnt_regs <= almost_empty_th + 1);
+                fifo_almost_empty_n_reg <= ~(data_cnt_regs <= almost_empty_th + 1);
+                fifo_almost_full_reg <= (data_cnt_regs >= almost_full_th + 1);
+                fifo_almost_full_n_reg <= ~(data_cnt_regs >= almost_full_th + 1);
+                
+                data_cnt_regs <= data_cnt_regs - 1;
+                data_cnt_onehot_regs <= {1'b0, data_cnt_onehot_regs[fifo_depth:1]}; // 右移
+            end
+        end
+    end
+    
+    /** 读写指针 **/
+    reg[clogb2(fifo_depth-1):0] fifo_rptr;
+    reg[clogb2(fifo_depth-1):0] fifo_rptr_add1;
+    reg[clogb2(fifo_depth-1):0] fifo_wptr;
+    reg[fifo_depth-1:0] fifo_wptr_onehot;
+    
+    always @(posedge clk or negedge rst_n)
+    begin
+        if(~rst_n)
+            fifo_rptr <= 0;
+        else if(fifo_ren & fifo_empty_n_reg)
+            #simulation_delay fifo_rptr <= fifo_rptr + 1;
+    end
+    
+    always @(posedge clk or negedge rst_n)
+    begin
+        if(~rst_n)
+            fifo_rptr_add1 <= 1;
+        else if(fifo_ren & fifo_empty_n_reg)
+            #simulation_delay fifo_rptr_add1 <= fifo_rptr_add1 + 1;
+    end
+    
+    always @(posedge clk or negedge rst_n)
+    begin
+        if(~rst_n)
+            fifo_wptr <= 0;
+        else if(fifo_wen & fifo_full_n_reg)
+            #simulation_delay fifo_wptr <= fifo_wptr + 1;
+    end
+    
+    always @(posedge clk or negedge rst_n)
+    begin
+        if(~rst_n)
+            fifo_wptr_onehot <= 1;
+        else if(fifo_wen & fifo_full_n_reg)
+            #simulation_delay fifo_wptr_onehot <= {fifo_wptr_onehot[fifo_depth-2:0], fifo_wptr_onehot[fifo_depth-1]}; // 循环左移
+    end
+    
+    /** 读写数据 **/
+    assign ram_wen = fifo_wen & fifo_full_n_reg;
+    assign ram_w_addr = fifo_wptr;
+    assign ram_din = fifo_din;
+    
+    assign ram_ren = fifo_ren & fifo_empty_n_reg;
+    assign ram_r_addr = fifo_rptr;
+    assign fifo_dout = ram_dout;
+    
+endmodule
+

CutestPanda_Opensoc/102_apb_i2c/rtl/fifo_show_ahead_buffer.v

@@ -0,0 +1,122 @@
+/*
+MIT License
+
+Copyright (c) 2024 Panda, 2257691535@qq.com
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+*/
+
+`timescale 1ns / 1ps
+/********************************************************************
+本模块: fifo FWFT缓冲区
+
+描述: 
+用于将读延迟为1clk的fifo转换为FWFT的fifo
+
+注意：
+无
+
+协议:
+FIFO READ
+
+作者: 陈家耀
+日期: 2024/05/30
+********************************************************************/
+
+
+module fifo_show_ahead_buffer #(
+    parameter integer fifo_data_width = 32, // fifo位宽
+    parameter real simulation_delay = 1 // 仿真延时
+)(
+    // 时钟和复位
+    input wire clk,
+    input wire rst_n,
+    
+    // 标准fifo的读端口
+    output wire std_fifo_ren,
+    input wire[fifo_data_width-1:0] std_fifo_dout,
+    input wire std_fifo_empty,
+    
+    // FWFT fifo的读端口
+    input wire fwft_fifo_ren,
+    output wire[fifo_data_width-1:0] fwft_fifo_dout,
+    output wire fwft_fifo_empty,
+    output wire fwft_fifo_empty_n
+);
+    
+    /** 寄存器buffer **/
+    reg std_fifo_rvld; // 标准fifo有效读(指示)
+    reg[fifo_data_width-1:0] regs_buffer[1:0]; // 寄存器buffer
+    reg[2:0] buffer_data_cnt; // buffer存储计数(3'b001 -> 0, 3'b010 -> 1, 3'b100 -> 2)
+    wire[2:0] buffer_data_cnt_sub1; // buffer存储计数 - 1(3'b001 -> 0, 3'b010 -> 1, 3'b100 -> 2)
+    
+    assign buffer_data_cnt_sub1 = {buffer_data_cnt[0], buffer_data_cnt[2:1]};
+    
+    // 标准fifo有效读(指示)
+    always @(posedge clk or negedge rst_n)
+    begin
+        if(~rst_n)
+            std_fifo_rvld <= 1'b0;
+        else
+            # simulation_delay std_fifo_rvld <= std_fifo_ren & (~std_fifo_empty);
+    end
+    
+    // 寄存器buffer
+    always @(posedge clk)
+    begin
+        if(std_fifo_rvld & ((fwft_fifo_ren & fwft_fifo_empty_n) ? buffer_data_cnt_sub1[0]:buffer_data_cnt[0]))
+            # simulation_delay regs_buffer[0] <= std_fifo_dout;
+        else if(fwft_fifo_ren & fwft_fifo_empty_n)
+            # simulation_delay regs_buffer[0] <= regs_buffer[1];
+    end
+    
+    always @(posedge clk)
+    begin
+        if(std_fifo_rvld & ((fwft_fifo_ren & fwft_fifo_empty_n) ? buffer_data_cnt_sub1[1]:buffer_data_cnt[1]))
+            # simulation_delay regs_buffer[1] <= std_fifo_dout;
+    end
+    
+    // buffer存储计数独热码
+    always @(posedge clk or negedge rst_n)
+    begin
+        if(~rst_n)
+            buffer_data_cnt <= 3'b001;
+        else if(std_fifo_rvld ^ (fwft_fifo_ren & fwft_fifo_empty_n))
+            # simulation_delay buffer_data_cnt <= std_fifo_rvld ? {buffer_data_cnt[1:0], buffer_data_cnt[2]}:{buffer_data_cnt[0], buffer_data_cnt[2:1]};
+    end
+    
+    /** 标准fifo的读端口 **/
+    assign std_fifo_ren = buffer_data_cnt[0] | fwft_fifo_ren; // buffer存储计数==0或者FWFT-fifo读使能时标准fifo读使能有效
+    
+    /** FWFT fifo的读端口 **/
+    reg fwft_fifo_empty_n_reg;
+    
+    assign fwft_fifo_dout = regs_buffer[0];
+    assign fwft_fifo_empty = buffer_data_cnt[0];
+    assign fwft_fifo_empty_n = fwft_fifo_empty_n_reg;
+    
+    always @(posedge clk or negedge rst_n)
+    begin
+        if(~rst_n)
+            fwft_fifo_empty_n_reg <= 1'b0;
+        else if(std_fifo_rvld ^ (fwft_fifo_ren & fwft_fifo_empty_n))
+            # simulation_delay fwft_fifo_empty_n_reg <= std_fifo_rvld ? 1'b1:(~buffer_data_cnt[1]);
+    end
+    
+endmodule

CutestPanda_Opensoc/102_apb_i2c/rtl/i2c_ctrler.v

@@ -0,0 +1,363 @@
+/*
+MIT License
+
+Copyright (c) 2024 Panda, 2257691535@qq.com
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+*/
+
+`timescale 1ns / 1ps
+/********************************************************************
+本模块: I2C控制器
+
+描述: 
+通用IC2控制器
+支持7位/10位地址
+
+发送fifo数据包格式：
+    写数据 -> last0 xxxx_xxx0 地址阶段
+             [last0 xxxx_xxxx 地址阶段(仅10位地址时需要)]
+             last0 xxxx_xxxx 数据阶段
+             ...
+             last1 xxxx_xxxx 数据阶段
+    读数据 -> last0 xxxx_xxx1 地址阶段
+             [last0 xxxx_xxxx 地址阶段(仅10位地址时需要)]
+             last1 8位待读取字节数
+
+注意：
+每个I2C数据包不能超过15字节
+
+协议:
+I2C MASTER
+
+作者: 陈家耀
+日期: 2024/06/14
+********************************************************************/
+
+
+module i2c_ctrler #(
+    parameter integer addr_bits_n = 7, // 地址位数(7|10)
+    parameter real simulation_delay = 1 // 仿真延时
+)(
+    // 时钟和复位
+    input wire clk,
+    input wire resetn,
+    
+    // I2C时钟分频系数
+    // 分频数 = (分频系数 + 1) * 2
+    // 断言:分频系数>=1!
+    input wire[7:0] i2c_scl_div_rate,
+    
+    // 发送fifo读端口
+    output wire tx_fifo_ren,
+    input wire tx_fifo_empty,
+    input wire[7:0] tx_fifo_dout,
+    input wire tx_fifo_dout_last,
+    // 接收fifo写端口
+    output wire rx_fifo_wen,
+    input wire rx_fifo_full,
+    output wire[7:0] rx_fifo_din,
+    
+    // I2C发送完成指示
+    output wire i2c_tx_done,
+    output wire[3:0] i2c_tx_bytes_n,
+    // I2C接收完成指示
+    output wire i2c_rx_done,
+    output wire[3:0] i2c_rx_bytes_n,
+    // I2C从机响应错误
+    output wire i2c_slave_resp_err,
+    // I2C接收溢出
+    output wire i2c_rx_overflow,
+    
+    // I2C主机接口
+    // scl
+    output wire scl_t, // 1'b1为输入, 1'b0为输出
+    input wire scl_i,
+    output wire scl_o,
+    // sda
+    output wire sda_t, // 1'b1为输入, 1'b0为输出
+    input wire sda_i,
+    output wire sda_o
+);
+    
+    /** 常量 **/
+    // 状态常量
+    localparam I2C_CTRLER_STS_IDLE = 2'b00; // 状态:空闲
+    localparam I2C_CTRLER_STS_LOAD = 2'b01; // 状态:加载数据
+    localparam I2C_CTRLER_STS_RX_TX = 2'b10; // 状态:收发
+    localparam I2C_CTRLER_STS_DONE = 2'b11; // 状态:完成
+    
+    /** 流程控制 **/
+    reg[1:0] i2c_ctrler_sts; // 控制器状态
+    reg[2:0] tx_fifo_ren_onehot; // 发送fifo读使能(独热码)
+    reg[2:0] i2c_if_stage_onehot; // i2c主接口控制器阶段(独热码)
+    wire i2c_if_ctrler_done; // i2c主接口控制器完成(指示)
+    reg is_rd_trans; // 是否读传输
+    reg last_loaded; // 载入的last信号
+    wire is_addr_stage; // 是否处于地址阶段
+    reg[3:0] bytes_n_to_rx; // 待接收字节数
+    reg trans_first; // 收发第1个字节(标志)
+    reg[3:0] trans_bytes_n; // 已收发的字节数
+    reg[3:0] trans_bytes_n_add1; // 已收发的字节数 + 1
+    
+    assign tx_fifo_ren = tx_fifo_ren_onehot[1];
+    
+    // 控制器状态
+    always @(posedge clk or negedge resetn)
+    begin
+        if(~resetn)
+            i2c_ctrler_sts <= I2C_CTRLER_STS_IDLE;
+        else
+        begin
+            # simulation_delay;
+            
+            case(i2c_ctrler_sts)
+                I2C_CTRLER_STS_IDLE: // 状态:空闲
+                    if(~tx_fifo_empty)
+                        i2c_ctrler_sts <= I2C_CTRLER_STS_LOAD; // -> 状态:加载数据
+                I2C_CTRLER_STS_LOAD: // 状态:加载数据
+                    if(tx_fifo_ren_onehot[2])
+                        i2c_ctrler_sts <= I2C_CTRLER_STS_RX_TX; // -> 状态:收发
+                I2C_CTRLER_STS_RX_TX: // 状态:收发
+                    if(i2c_if_stage_onehot[2] & i2c_if_ctrler_done)
+                        i2c_ctrler_sts <= I2C_CTRLER_STS_DONE; // -> 状态:完成
+                I2C_CTRLER_STS_DONE:
+                begin
+                    if(is_rd_trans)
+                    begin
+                        if(last_loaded)
+                            i2c_ctrler_sts <= (trans_bytes_n == bytes_n_to_rx) ? I2C_CTRLER_STS_IDLE: // -> 状态:空闲
+                                                                                 I2C_CTRLER_STS_RX_TX; // -> 状态:收发
+                        else
+                            i2c_ctrler_sts <= I2C_CTRLER_STS_LOAD; // -> 状态:加载数据
+                    end
+                    else
+                        i2c_ctrler_sts <= last_loaded ? I2C_CTRLER_STS_IDLE: // -> 状态:空闲
+                                                        I2C_CTRLER_STS_LOAD; // -> 状态:加载数据
+                end
+                default:
+                    i2c_ctrler_sts <= I2C_CTRLER_STS_IDLE;
+            endcase
+        end
+    end
+    
+    // 发送fifo读使能(独热码)
+    always @(posedge clk or negedge resetn)
+    begin
+        if(~resetn)
+            tx_fifo_ren_onehot <= 3'b001;
+        else if((tx_fifo_ren_onehot[0] & (i2c_ctrler_sts == I2C_CTRLER_STS_LOAD)) | (tx_fifo_ren_onehot[1] & (~tx_fifo_empty)) | tx_fifo_ren_onehot[2])
+            # simulation_delay tx_fifo_ren_onehot <= {tx_fifo_ren_onehot[1:0], tx_fifo_ren_onehot[2]};
+    end
+    
+    // i2c主接口控制器阶段(独热码)
+    always @(posedge clk or negedge resetn)
+    begin
+        if(~resetn)
+            i2c_if_stage_onehot <= 3'b001;
+        else if((i2c_if_stage_onehot[0] & (i2c_ctrler_sts == I2C_CTRLER_STS_RX_TX)) | i2c_if_stage_onehot[1] | (i2c_if_stage_onehot[2] & i2c_if_ctrler_done))
+            # simulation_delay i2c_if_stage_onehot <= {i2c_if_stage_onehot[1:0], i2c_if_stage_onehot[2]};
+    end
+    
+    // 收发第1个字节(标志)
+    always @(posedge clk)
+    begin
+        if(i2c_ctrler_sts == I2C_CTRLER_STS_IDLE)
+            # simulation_delay trans_first <= 1'b1;
+        else if(trans_first)
+            # simulation_delay trans_first <= ~(i2c_if_stage_onehot[2] & i2c_if_ctrler_done);
+    end
+    
+    // 已收发的字节数
+    always @(posedge clk)
+    begin
+        if(i2c_ctrler_sts == I2C_CTRLER_STS_IDLE)
+            # simulation_delay trans_bytes_n <= 4'd0;
+        else if(i2c_if_stage_onehot[2] & i2c_if_ctrler_done & (~is_addr_stage))
+            # simulation_delay trans_bytes_n <= trans_bytes_n + 4'd1;
+    end
+    // 已收发的字节数 + 1
+    always @(posedge clk)
+    begin
+        if(i2c_ctrler_sts == I2C_CTRLER_STS_IDLE)
+            # simulation_delay trans_bytes_n_add1 <= 4'd1;
+        else if(i2c_if_stage_onehot[2] & i2c_if_ctrler_done & (~is_addr_stage))
+            # simulation_delay trans_bytes_n_add1 <= trans_bytes_n_add1 + 4'd1;
+    end
+    
+    /** 数据载入 **/
+    reg first_load; // 本I2C数据包第1次载入数据(标志)
+    reg[7:0] data_loaded; // 载入的数据
+    wire resp_dire; // 响应方向(1'b0 -> 主机接收响应, 1'b1 -> 主机发送响应)
+    
+    assign resp_dire = is_addr_stage ? 1'b0:is_rd_trans;
+    
+    // 本I2C数据包第1次载入数据(标志)
+    always @(posedge clk)
+    begin
+        if(i2c_ctrler_sts == I2C_CTRLER_STS_IDLE)
+            # simulation_delay first_load <= 1'b1;
+        else if(first_load)
+            # simulation_delay first_load <= ~tx_fifo_ren_onehot[2];
+    end
+    
+    // 载入的数据
+    // 载入的last信号
+    always @(posedge clk)
+    begin
+        if(tx_fifo_ren_onehot[2])
+            # simulation_delay {last_loaded, data_loaded} <= {tx_fifo_dout_last, tx_fifo_dout};
+    end
+    
+    // 是否读传输
+    always @(posedge clk)
+    begin
+        if(tx_fifo_ren_onehot[2] & first_load)
+            # simulation_delay is_rd_trans <= tx_fifo_dout[0];
+    end
+    
+    // 是否处于地址阶段
+    generate
+        if(addr_bits_n == 7) // 7位地址
+        begin
+            reg[1:0] is_addr_stage_onehot;
+            
+            assign is_addr_stage = is_addr_stage_onehot[0];
+            
+            always @(posedge clk)
+            begin
+                if(i2c_ctrler_sts == I2C_CTRLER_STS_IDLE)
+                    # simulation_delay is_addr_stage_onehot <= 2'b01;
+                else if((~is_addr_stage_onehot[1]) & (i2c_if_stage_onehot[2] & i2c_if_ctrler_done))
+                    # simulation_delay is_addr_stage_onehot <= {is_addr_stage_onehot[0], is_addr_stage_onehot[1]};
+            end
+        end
+        else // 10位地址
+        begin
+            reg[2:0] is_addr_stage_onehot;
+            
+            assign is_addr_stage = ~is_addr_stage_onehot[2];
+            
+            always @(posedge clk)
+            begin
+                if(i2c_ctrler_sts == I2C_CTRLER_STS_IDLE)
+                    # simulation_delay is_addr_stage_onehot <= 3'b001;
+                else if((~is_addr_stage_onehot[2]) & (i2c_if_stage_onehot[2] & i2c_if_ctrler_done))
+                    # simulation_delay is_addr_stage_onehot <= {is_addr_stage_onehot[1:0], is_addr_stage_onehot[2]};
+            end
+        end
+    endgenerate
+    
+    // 待接收字节数
+    always @(posedge clk)
+    begin
+        if(tx_fifo_ren_onehot[2] & tx_fifo_dout_last & is_rd_trans)
+            # simulation_delay bytes_n_to_rx <= tx_fifo_dout[3:0];
+    end
+    
+    /** I2C主接口 **/
+    wire[7:0] byte_recv; // 接收到数据
+    reg i2c_rx_overflow_reg; // I2C接收溢出
+    wire i2c_if_ctrler_start; // i2c主接口控制器开始(指示)
+    reg[1:0] i2c_if_ctrler_mode; // i2c主接口控制器传输模式(2'b00 -> 带起始位, 2'b01 -> 带结束位, 2'b10 -> 正常, 2'b11 -> 预留)
+    wire i2c_if_ctrler_dire; // i2c主接口控制器传输方向(1'b0 -> 发送, 1'b1 -> 接收)
+    
+    assign rx_fifo_wen = i2c_if_ctrler_done & resp_dire;
+    assign rx_fifo_din = byte_recv;
+    
+    assign i2c_rx_overflow = i2c_rx_overflow_reg;
+    
+    assign i2c_if_ctrler_start = i2c_if_stage_onehot[1];
+    assign i2c_if_ctrler_dire = resp_dire;
+    
+    // I2C接收溢出
+    always @(posedge clk or negedge resetn)
+    begin
+        if(~resetn)
+            i2c_rx_overflow_reg <= 1'b0;
+        else
+            # simulation_delay i2c_rx_overflow_reg <= rx_fifo_wen & rx_fifo_full;
+    end
+    
+    // i2c主接口控制器传输模式
+    always @(posedge clk)
+    begin
+        if(trans_first)
+            # simulation_delay i2c_if_ctrler_mode <= 2'b00;
+        else if(is_rd_trans ? (last_loaded & (trans_bytes_n_add1 == bytes_n_to_rx)):last_loaded)
+            # simulation_delay i2c_if_ctrler_mode <= 2'b01;
+        else
+            # simulation_delay i2c_if_ctrler_mode <= 2'b10;
+    end
+    
+    // i2c主接口控制器
+    i2c_master_if #(
+        .simulation_delay(simulation_delay)
+    )i2c_master_if_u(
+        .clk(clk),
+        .resetn(resetn),
+        
+        .i2c_scl_div_rate(i2c_scl_div_rate),
+        
+        .ctrler_start(i2c_if_ctrler_start),
+        .ctrler_idle(),
+        .ctrler_done(i2c_if_ctrler_done),
+        
+        .mode(i2c_if_ctrler_mode),
+        .direction(i2c_if_ctrler_dire),
+        .byte_to_send(data_loaded),
+        .byte_recv(byte_recv),
+        
+        .i2c_slave_resp_err(i2c_slave_resp_err),
+        
+        .scl_t(scl_t),
+        .scl_i(scl_i),
+        .scl_o(scl_o),
+        .sda_t(sda_t),
+        .sda_i(sda_i),
+        .sda_o(sda_o)
+    );
+    
+    /** I2C收发完成指示 **/
+    reg i2c_tx_done_reg; // I2C发送完成指示
+    reg i2c_rx_done_reg; // I2C接收完成指示
+    
+    assign i2c_tx_done = i2c_tx_done_reg;
+    assign i2c_tx_bytes_n = trans_bytes_n;
+    assign i2c_rx_done = i2c_rx_done_reg;
+    assign i2c_rx_bytes_n = trans_bytes_n;
+    
+    // I2C发送完成指示
+    always @(posedge clk or negedge resetn)
+    begin
+        if(~resetn)
+            i2c_tx_done_reg <= 1'b0;
+        else
+            # simulation_delay i2c_tx_done_reg <= (i2c_ctrler_sts == I2C_CTRLER_STS_DONE) & (~is_rd_trans) & last_loaded;
+    end
+    // I2C接收完成指示
+    always @(posedge clk or negedge resetn)
+    begin
+        if(~resetn)
+            i2c_rx_done_reg <= 1'b0;
+        else
+            # simulation_delay i2c_rx_done_reg <= (i2c_ctrler_sts == I2C_CTRLER_STS_DONE) & is_rd_trans & last_loaded & (trans_bytes_n == bytes_n_to_rx);
+    end
+    
+endmodule

CutestPanda_Opensoc/102_apb_i2c/rtl/i2c_master_if.v

@@ -0,0 +1,358 @@
+/*
+MIT License
+
+Copyright (c) 2024 Panda, 2257691535@qq.com
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+*/
+
+`timescale 1ns / 1ps
+/********************************************************************
+本模块: I2C主接口
+
+描述: 
+根据传输方向和待发送数据来驱动I2C主接口
+
+注意：
+无
+
+协议:
+I2C MASTER
+
+作者: 陈家耀
+日期: 2024/06/15
+********************************************************************/
+
+
+module i2c_master_if #(
+    parameter real simulation_delay = 1 // 仿真延时
+)(
+    // 时钟和复位
+    input wire clk,
+    input wire resetn,
+    
+    // I2C时钟分频系数
+    // 分频数 = (分频系数 + 1) * 2
+    // 断言:分频系数>=1!
+    input wire[7:0] i2c_scl_div_rate,
+    
+    // 流程控制
+    input wire ctrler_start,
+    output wire ctrler_idle,
+    output wire ctrler_done,
+    
+    // 收发控制
+    input wire[1:0] mode, // 传输模式(2'b00 -> 带起始位, 2'b01 -> 带结束位, 2'b10 -> 正常, 2'b11 -> 预留)
+    input wire direction, // 传输方向(1'b0 -> 发送, 1'b1 -> 接收)
+    input wire[7:0] byte_to_send, // 待发送数据
+    output wire[7:0] byte_recv, // 接收到的数据
+    
+    // I2C从机响应错误
+    output wire i2c_slave_resp_err,
+    
+    // I2C主机接口
+    // scl
+    output wire scl_t, // 1'b1为输入, 1'b0为输出
+    input wire scl_i,
+    output wire scl_o,
+    // sda
+    output wire sda_t, // 1'b1为输入, 1'b0为输出
+    input wire sda_i,
+    output wire sda_o
+);
+    
+    /** 常量 **/
+    // 模式常量
+    localparam MODE_WITH_START = 2'b00; // 模式:带起始位
+    localparam MODE_WITH_STOP = 2'b01; // 模式:带结束位
+    localparam MODE_NORMAL = 2'b10; // 模式:正常
+    // 控制器状态常量
+    localparam CTRLER_STS_IDLE = 3'b000; // 状态:空闲
+    localparam CTRLER_STS_START = 3'b001; // 状态:起始位
+    localparam CTRLER_STS_DATA = 3'b010; // 状态:数据位
+    localparam CTRLER_STS_RESP = 3'b011; // 状态:响应
+    localparam CTRLER_STS_STOP = 3'b100; // 状态:停止位
+    localparam CTRLER_STS_DONE = 3'b101; // 状态:完成
+    
+    /** 载入的控制信息 **/
+    reg[1:0] mode_latched; // 锁存的传输模式(2'b00 -> 带起始位, 2'b01 -> 带结束位, 2'b10 -> 正常, 2'b11 -> 预留)
+    reg direction_latched; // 锁存的传输方向(1'b0 -> 发送, 1'b1 -> 接收)
+    
+    // 锁存的传输模式
+    always @(posedge clk)
+    begin
+        if(ctrler_idle & ctrler_start)
+            # simulation_delay mode_latched <= mode;
+    end
+    // 锁存的传输方向
+    always @(posedge clk)
+    begin
+        if(ctrler_idle & ctrler_start)
+            # simulation_delay direction_latched <= direction;
+    end
+    
+    /** 流程控制 **/
+    reg[2:0] i2c_if_ctrler_sts; // 控制器状态
+    wire rx_tx_byte_done; // 字节收发完成(指示)
+    wire resp_disposed; // 响应处理完成(指示)
+    wire stop_disposed; // 停止位处理完成(指示)
+    reg ctrler_idle_reg; // 控制器空闲(标志)
+    reg ctrler_done_reg; // 控制器完成(指示)
+    
+    assign ctrler_idle = ctrler_idle_reg;
+    assign ctrler_done = ctrler_done_reg;
+    
+    // 控制器状态
+    always @(posedge clk or negedge resetn)
+    begin
+        if(~resetn)
+            i2c_if_ctrler_sts <= CTRLER_STS_IDLE;
+        else
+        begin
+            # simulation_delay;
+            
+            case(i2c_if_ctrler_sts)
+                CTRLER_STS_IDLE: // 状态:空闲
+                    if(ctrler_start)
+                        i2c_if_ctrler_sts <= CTRLER_STS_START; // -> 状态:起始位
+                CTRLER_STS_START: // 状态:起始位
+                    i2c_if_ctrler_sts <= CTRLER_STS_DATA; // -> 状态:数据位
+                CTRLER_STS_DATA: // 状态:数据位
+                    if(rx_tx_byte_done)
+                        i2c_if_ctrler_sts <= CTRLER_STS_RESP; // -> 状态:响应
+                CTRLER_STS_RESP: // 状态:响应
+                    if(resp_disposed)
+                        i2c_if_ctrler_sts <= CTRLER_STS_STOP; // -> 状态:停止位
+                CTRLER_STS_STOP: // 状态:停止位
+                    if((mode_latched == MODE_WITH_STOP) ? stop_disposed:1'b1)
+                        i2c_if_ctrler_sts <= CTRLER_STS_DONE; // -> 状态:完成
+                CTRLER_STS_DONE: // 状态:完成
+                    i2c_if_ctrler_sts <= CTRLER_STS_IDLE; // -> 状态:空闲
+                default:
+                    i2c_if_ctrler_sts <= CTRLER_STS_IDLE;
+            endcase
+        end
+    end
+    
+    // 控制器空闲(标志)
+    always @(posedge clk or negedge resetn)
+    begin
+        if(~resetn)
+            ctrler_idle_reg <= 1'b1;
+        else
+            # simulation_delay ctrler_idle_reg <= ctrler_idle_reg ? (~ctrler_start):ctrler_done_reg;
+    end
+    // 控制器完成(指示)
+    always @(posedge clk or negedge resetn)
+    begin
+        if(~resetn)
+            ctrler_done_reg <= 1'b0;
+        else
+            # simulation_delay ctrler_done_reg <= (i2c_if_ctrler_sts == CTRLER_STS_STOP) & ((mode_latched == MODE_WITH_STOP) ? stop_disposed:1'b1);
+    end
+    
+    /** 数据收发控制 **/
+    reg shift_send_bit; // 待发送数据移位标志
+    reg sample_recv_bit; // 待接收数据采样标志
+    reg[7:0] send_byte_buffer; // 待发送数据缓冲区
+    reg[7:0] recv_byte_buffer; // 待接收数据缓冲区
+    reg[7:0] rx_tx_stage_onehot; // 收发进程独热码
+    
+    assign byte_recv = recv_byte_buffer;
+    
+    assign rx_tx_byte_done = rx_tx_stage_onehot[7] & sample_recv_bit;
+    
+    // 待发送数据缓冲区
+    always @(posedge clk)
+    begin
+        if(ctrler_idle & ctrler_start)
+            # simulation_delay send_byte_buffer <= byte_to_send;
+        else if(shift_send_bit)
+            # simulation_delay send_byte_buffer <= {send_byte_buffer[6:0], 1'bx};
+    end
+    // 待接收数据缓冲区
+    always @(posedge clk)
+    begin
+        if(sample_recv_bit)
+            # simulation_delay recv_byte_buffer <= {recv_byte_buffer[6:0], sda_i};
+    end
+    
+    // 收发进程独热码
+    always @(posedge clk or negedge resetn)
+    begin
+        if(~resetn)
+            rx_tx_stage_onehot <= 8'b0000_0001;
+        else if(sample_recv_bit)
+            # simulation_delay rx_tx_stage_onehot <= {rx_tx_stage_onehot[6:0], rx_tx_stage_onehot[7]};
+    end
+    
+    /** 响应控制 **/
+	reg[7:0] resp_div_cnt; // 响应时scl分频计数器
+    reg[5:0] resp_stage_onehot; // 响应进程独热码(6'b000001 -> SCL高, 6'b000010 -> SCL高, 6'b000100 -> SCL低, 6'b001000 -> SCL低且输出响应, 6'b010000 -> SCL高, 6'b100000 -> SCL高)
+    reg i2c_slave_resp_err_reg; // I2C从机响应错误
+    
+    assign i2c_slave_resp_err = i2c_slave_resp_err_reg;
+    
+    assign resp_disposed = resp_stage_onehot[5];
+	
+	// 响应时scl分频计数器
+	always @(posedge clk)
+	begin
+		if((i2c_if_ctrler_sts == CTRLER_STS_RESP) & (resp_stage_onehot[0] | resp_stage_onehot[2]))
+            # simulation_delay resp_div_cnt <= resp_div_cnt + 8'd1;
+		else
+			# simulation_delay resp_div_cnt <= 8'd0;
+	end
+    
+    // 响应进程独热码
+    always @(posedge clk or negedge resetn)
+    begin
+        if(~resetn)
+            resp_stage_onehot <= 6'b00_00_01;
+        else if((i2c_if_ctrler_sts == CTRLER_STS_RESP) & 
+			((resp_stage_onehot[0] | resp_stage_onehot[2]) ? (resp_div_cnt == i2c_scl_div_rate):1'b1))
+            # simulation_delay resp_stage_onehot <= {resp_stage_onehot[4:0], resp_stage_onehot[5]};
+    end
+    
+    // I2C从机响应错误
+    always @(posedge clk or negedge resetn)
+    begin
+        if(~resetn)
+            i2c_slave_resp_err_reg <= 1'b0;
+        else
+            # simulation_delay i2c_slave_resp_err_reg <= (i2c_if_ctrler_sts == CTRLER_STS_RESP) & resp_stage_onehot[4] & sda_i;
+    end
+    
+    /** 停止位控制 **/
+	reg[7:0] stop_div_cnt; // 停止位scl分频计数器
+    reg[5:0] stop_stage_onehot; // 停止位进程独热码(6'b000001 -> SCL高, 6'b000010 -> SCL高, 6'b000100 -> SCL低, 6'b001000 -> SCL低且SDA低, 6'b010000 -> SCL高, 6'b100000 -> SCL高且SDA高)
+    
+    assign stop_disposed = stop_stage_onehot[5];
+    
+	// 停止位scl分频计数器
+	always @(posedge clk)
+	begin
+		if((i2c_if_ctrler_sts == CTRLER_STS_STOP) & (mode_latched == MODE_WITH_STOP) & 
+			(stop_stage_onehot[0] | stop_stage_onehot[2]))
+            # simulation_delay stop_div_cnt <= stop_div_cnt + 8'd1;
+		else
+			# simulation_delay stop_div_cnt <= 8'd0;
+	end
+	
+    // 停止位进程独热码
+    always @(posedge clk or negedge resetn)
+    begin
+        if(~resetn)
+            stop_stage_onehot <= 6'b00_00_01;
+        else if((i2c_if_ctrler_sts == CTRLER_STS_STOP) & (mode_latched == MODE_WITH_STOP) & 
+			((stop_stage_onehot[0] | stop_stage_onehot[2]) ? (stop_div_cnt == i2c_scl_div_rate):1'b1))
+            # simulation_delay stop_stage_onehot <= {stop_stage_onehot[4:0], stop_stage_onehot[5]};
+    end
+    
+    /** I2C时钟分频 **/
+    reg[7:0] i2c_scl_div_cnt; // I2C时钟分频计数器
+    wire i2c_scl_div_cnt_rst; // I2C时钟分频计数器回零指示
+    
+    assign i2c_scl_div_cnt_rst = i2c_scl_div_cnt == i2c_scl_div_rate;
+    
+    // 待发送数据移位标志
+    always @(posedge clk or negedge resetn)
+    begin
+        if(~resetn)
+            shift_send_bit <= 1'b0;
+        else
+            # simulation_delay shift_send_bit <= scl_o & (i2c_if_ctrler_sts == CTRLER_STS_DATA) & i2c_scl_div_cnt_rst;
+    end
+    // 待接收数据采样标志
+    always @(posedge clk or negedge resetn)
+    begin
+        if(~resetn)
+            sample_recv_bit <= 1'b0;
+        else
+            # simulation_delay sample_recv_bit <= (~scl_o) & (i2c_if_ctrler_sts == CTRLER_STS_DATA) & i2c_scl_div_cnt_rst;
+    end
+    
+    // I2C时钟分频计数器
+    always @(posedge clk)
+    begin
+        if(i2c_if_ctrler_sts == CTRLER_STS_DATA)
+            # simulation_delay i2c_scl_div_cnt <= (i2c_scl_div_cnt == i2c_scl_div_rate) ? 8'd0:(i2c_scl_div_cnt + 8'd1);
+        else
+            # simulation_delay i2c_scl_div_cnt <= 8'd0;
+    end
+    
+    /** I2C主接口 **/
+    reg scl_o_reg; // SCL输出
+    reg sda_t_reg; // SDA方向
+    reg sda_o_reg; // SDA输出
+    
+    assign scl_t = 1'b0;
+    assign scl_o = scl_o_reg;
+    assign sda_t = sda_t_reg;
+    assign sda_o = sda_o_reg;
+    
+    // SCL输出
+    always @(posedge clk or negedge resetn)
+    begin
+        if(~resetn)
+            scl_o_reg <= 1'b1;
+        else if(((i2c_if_ctrler_sts == CTRLER_STS_DATA) & i2c_scl_div_cnt_rst) |
+            ((i2c_if_ctrler_sts == CTRLER_STS_RESP) & (resp_stage_onehot[1] | resp_stage_onehot[3])) |
+            ((i2c_if_ctrler_sts == CTRLER_STS_STOP) & (mode_latched == MODE_WITH_STOP) & (stop_stage_onehot[1] | stop_stage_onehot[3])))
+        begin
+            # simulation_delay scl_o_reg <= ~scl_o_reg;
+        end
+    end
+    
+    // SDA方向(1'b1为输入, 1'b0为输出)
+    always @(posedge clk or negedge resetn)
+    begin
+        if(~resetn)
+            sda_t_reg <= 1'b1;
+        else if(((i2c_if_ctrler_sts == CTRLER_STS_START) & (mode_latched == MODE_WITH_START)) | 
+            ((i2c_if_ctrler_sts == CTRLER_STS_DATA) & shift_send_bit) |
+            ((i2c_if_ctrler_sts == CTRLER_STS_RESP) & resp_stage_onehot[2]) |
+            ((i2c_if_ctrler_sts == CTRLER_STS_STOP) & stop_stage_onehot[2]))
+        begin
+            # simulation_delay sda_t_reg <= 
+                (i2c_if_ctrler_sts == CTRLER_STS_START) ? 1'b0:
+                (i2c_if_ctrler_sts == CTRLER_STS_DATA) ? direction_latched:
+                (i2c_if_ctrler_sts == CTRLER_STS_RESP) ? (~direction_latched):
+                    1'b0;
+        end
+    end
+    // SDA输出
+    always @(posedge clk or negedge resetn)
+    begin
+        if(~resetn)
+            sda_o_reg <= 1'b1;
+        else if(((i2c_if_ctrler_sts == CTRLER_STS_START) & (mode_latched == MODE_WITH_START)) | 
+            ((i2c_if_ctrler_sts == CTRLER_STS_DATA) & (~direction_latched) & shift_send_bit) |
+            ((i2c_if_ctrler_sts == CTRLER_STS_RESP) & resp_stage_onehot[2] & direction_latched) |
+            ((i2c_if_ctrler_sts == CTRLER_STS_STOP) & (stop_stage_onehot[2] | stop_stage_onehot[4])))
+        begin
+            # simulation_delay sda_o_reg <= 
+                (i2c_if_ctrler_sts == CTRLER_STS_START) ? 1'b0:
+                (i2c_if_ctrler_sts == CTRLER_STS_DATA) ? send_byte_buffer[7]:
+                (i2c_if_ctrler_sts == CTRLER_STS_RESP) ? (mode_latched == MODE_WITH_STOP):
+                    stop_stage_onehot[4];
+        end
+    end
+    
+endmodule

CutestPanda_Opensoc/102_apb_i2c/rtl/itr_generator.v

@@ -0,0 +1,104 @@
+/*
+MIT License
+
+Copyright (c) 2024 Panda, 2257691535@qq.com
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+*/
+
+`timescale 1ns / 1ps
+/********************************************************************
+本模块: 中断信号发生器
+
+描述: 
+将原始的中断脉冲拓展为一定脉宽的中断信号
+
+注意：
+中断脉宽必须 >= 2
+
+协议:
+无
+
+作者: 陈家耀
+日期: 2023/11/08
+********************************************************************/
+
+
+module itr_generator #(
+    parameter integer pulse_w = 100, // 中断脉宽(必须>=1)
+    parameter real simulation_delay = 1 // 仿真延时
+)(
+    // 时钟和复位
+    input wire clk,
+    input wire rst_n,
+    
+    input wire itr_org, // 原始中断输入
+    output wire itr // 中断输出
+);
+
+    // 计算log2(bit_depth)               
+    function integer clogb2 (input integer bit_depth);
+        integer temp;
+    begin
+        temp = bit_depth;
+        for(clogb2 = -1;temp > 0;clogb2 = clogb2 + 1)                   
+            temp = temp >> 1;                                 
+    end                                        
+    endfunction
+    
+    // 产生中断信号
+    reg itr_reg; // 中断信号
+    reg[clogb2(pulse_w - 1):0] itr_cnt; // 中断计数器
+    
+    assign itr = itr_reg;
+    
+    generate
+        if(pulse_w == 1)
+        begin
+            always @(posedge clk or negedge rst_n)
+            begin
+                if(~rst_n)
+                    itr_reg <= 1'b0;
+                else
+                    # simulation_delay itr_reg <= itr_org;
+            end
+        end
+        else
+        begin
+            always @(posedge clk or negedge rst_n)
+            begin
+                if(~rst_n)
+                    itr_reg <= 1'b0;
+                else
+                begin
+                    # simulation_delay;
+                    
+                    if(~itr_reg) // 等待原始中断脉冲
+                        itr_reg <= itr_org;
+                    else // 等待计数完成
+                        itr_reg <= itr_cnt != pulse_w - 1;
+                end
+            end
+        end
+    endgenerate
+    
+    always @(posedge clk)
+        # simulation_delay itr_cnt <= (~itr_reg) ? 0:(itr_cnt + 1);
+
+endmodule

CutestPanda_Opensoc/102_apb_i2c/rtl/ram_fifo_wrapper.v

@@ -0,0 +1,220 @@
+/*
+MIT License
+
+Copyright (c) 2024 Panda, 2257691535@qq.com
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+*/
+
+`timescale 1ns / 1ps
+/********************************************************************
+本模块: 基于lutram或bram的同步fifo
+
+描述: 
+全流水的高性能同步fifo
+基于lutram或bram
+支持first word fall through特性(READ LA = 0)
+可选的固定阈值将满/将空信号
+可选的存储计数输出
+
+注意：
+将满信号当存储计数 >= almost_full_th时有效
+将空信号当存储计数 <= almost_empty_th时有效
+almost_full_th和almost_empty_th必须在[1, fifo_depth-1]范围内
+本模块用于fpga, 子模块fifo_based_on_ram可用于asic设计
+寄存器fifo请用子模块fifo_based_on_regs
+
+协议:
+FIFO WRITE/READ
+
+作者: 陈家耀
+日期: 2023/10/29
+********************************************************************/
+
+
+module ram_fifo_wrapper #(
+    parameter fwft_mode = "true", // 是否启用first word fall through特性
+    parameter ram_type = "lutram", // RAM类型(lutram|bram)
+    parameter en_bram_reg = "false", // 是否启用BRAM输出寄存器
+    parameter integer fifo_depth = 32, // fifo深度(必须为2|4|8|16|...)
+    parameter integer fifo_data_width = 32, // fifo位宽
+    parameter full_assert_polarity = "low", // 满信号有效极性(low|high)
+    parameter empty_assert_polarity = "low", // 空信号有效极性(low|high)
+    parameter almost_full_assert_polarity = "no", // 将满信号有效极性(low|high|no)
+    parameter almost_empty_assert_polarity = "no", // 将空信号有效极性(low|high|no)
+    parameter en_data_cnt = "false", // 是否启用存储计数器
+    parameter integer almost_full_th = 20, // fifo将满阈值
+    parameter integer almost_empty_th = 5, // fifo将空阈值
+    parameter real simulation_delay = 1 // 仿真延时
+)(
+    // 时钟和复位
+    input wire clk,
+    input wire rst_n,
+    
+    // FIFO WRITE(fifo写端口)
+    input wire fifo_wen,
+    input wire[fifo_data_width-1:0] fifo_din,
+    output wire fifo_full,
+    output wire fifo_full_n,
+    output wire fifo_almost_full,
+    output wire fifo_almost_full_n,
+    
+    // FIFO READ(fifo读端口)
+    input wire fifo_ren,
+    output wire[fifo_data_width-1:0] fifo_dout,
+    output wire fifo_empty,
+    output wire fifo_empty_n,
+    output wire fifo_almost_empty,
+    output wire fifo_almost_empty_n,
+    
+    // 存储计数
+    output wire[clogb2(fifo_depth):0] data_cnt
+);
+
+    // 计算log2(bit_depth)               
+    function integer clogb2 (input integer bit_depth);
+        integer temp;
+    begin
+        temp = bit_depth;
+        for(clogb2 = -1;temp > 0;clogb2 = clogb2 + 1)
+            temp = temp >> 1;
+    end
+    endfunction
+    
+    wire fifo_full_w;
+    wire fifo_full_n_w;
+    wire fifo_almost_full_w;
+    wire fifo_almost_full_n_w;
+    wire fifo_empty_w;
+    wire fifo_empty_n_w;
+    wire fifo_almost_empty_w;
+    wire fifo_almost_empty_n_w;
+    wire[clogb2(fifo_depth):0] data_cnt_w;
+    
+    generate
+        if(full_assert_polarity == "low")
+            assign fifo_full_n = fifo_full_n_w;
+        else
+            assign fifo_full = fifo_full_w;
+        
+        if(almost_full_assert_polarity == "low")
+            assign fifo_almost_full_n = fifo_almost_full_n_w;
+        else if(almost_full_assert_polarity == "high")
+            assign fifo_almost_full = fifo_almost_full_w;
+        
+        if(empty_assert_polarity == "low")
+            assign fifo_empty_n = fifo_empty_n_w;
+        else
+            assign fifo_empty = fifo_empty_w;
+        
+        if(almost_empty_assert_polarity == "low")
+            assign fifo_almost_empty_n = fifo_almost_empty_n_w;
+        else if(almost_empty_assert_polarity == "high")
+            assign fifo_almost_empty = fifo_almost_empty_w;
+        
+        if(en_data_cnt == "true")
+            assign data_cnt = data_cnt_w;
+    
+        if(ram_type == "lutram")
+        begin
+            fifo_based_on_lutram #(
+                .fwft_mode(fwft_mode),
+                .fifo_depth(fifo_depth),
+                .fifo_data_width(fifo_data_width),
+                .almost_full_th(almost_full_th),
+                .almost_empty_th(almost_empty_th),
+                .simulation_delay(simulation_delay)
+            )fifo(
+                .clk(clk),
+                .rst_n(rst_n),
+                .fifo_wen(fifo_wen),
+                .fifo_din(fifo_din),
+                .fifo_full(fifo_full_w),
+                .fifo_full_n(fifo_full_n_w),
+                .fifo_almost_full(fifo_almost_full_w),
+                .fifo_almost_full_n(fifo_almost_full_n_w),
+                .fifo_ren(fifo_ren),
+                .fifo_dout(fifo_dout),
+                .fifo_empty(fifo_empty_w),
+                .fifo_empty_n(fifo_empty_n_w),
+                .fifo_almost_empty(fifo_almost_empty_w),
+                .fifo_almost_empty_n(fifo_almost_empty_n_w),
+                .data_cnt(data_cnt_w)
+            );
+        end
+        else
+        begin
+            wire ram_wen_a;
+            wire[clogb2(fifo_depth-1):0] ram_addr_a;
+            wire[fifo_data_width-1:0] ram_din_a;
+            wire ram_ren_b;
+            wire[clogb2(fifo_depth-1):0] ram_addr_b;
+            wire[fifo_data_width-1:0] ram_dout_b;
+    
+            fifo_based_on_ram #(
+                .fwft_mode(fwft_mode),
+                .ram_read_la((en_bram_reg == "true") ? 2:1),
+                .fifo_depth(fifo_depth),
+                .fifo_data_width(fifo_data_width),
+                .almost_full_th(almost_full_th),
+                .almost_empty_th(almost_empty_th),
+                .simulation_delay(simulation_delay)
+            )fifo_ctrler(
+                .clk(clk),
+                .rst_n(rst_n),
+                .fifo_wen(fifo_wen),
+                .fifo_din(fifo_din),
+                .fifo_full(fifo_full_w),
+                .fifo_full_n(fifo_full_n_w),
+                .fifo_almost_full(fifo_almost_full_w),
+                .fifo_almost_full_n(fifo_almost_full_n_w),
+                .fifo_ren(fifo_ren),
+                .fifo_dout(fifo_dout),
+                .fifo_empty(fifo_empty_w),
+                .fifo_empty_n(fifo_empty_n_w),
+                .fifo_almost_empty(fifo_almost_empty_w),
+                .fifo_almost_empty_n(fifo_almost_empty_n_w),
+                .ram_wen(ram_wen_a),
+                .ram_w_addr(ram_addr_a),
+                .ram_din(ram_din_a),
+                .ram_ren(ram_ren_b),
+                .ram_r_addr(ram_addr_b),
+                .ram_dout(ram_dout_b),
+                .data_cnt(data_cnt_w)
+            );
+            
+            bram_simple_dual_port #(
+                .style((en_bram_reg == "true") ? "HIGH_PERFORMANCE":"LOW_LATENCY"),
+                .mem_width(fifo_data_width),
+                .mem_depth(fifo_depth),
+                .INIT_FILE("no_init"),
+                .simulation_delay(simulation_delay)
+            )fifo_ram(
+                .clk(clk),
+                .wen_a(ram_wen_a),
+                .addr_a(ram_addr_a),
+                .din_a(ram_din_a),
+                .ren_b(ram_ren_b),
+                .addr_b(ram_addr_b),
+                .dout_b(ram_dout_b)
+            );
+        end
+    endgenerate
+    
+endmodule

CutestPanda_Opensoc/102_apb_i2c/rtl/regs_if_for_i2c.v

@@ -0,0 +1,307 @@
+/*
+MIT License
+
+Copyright (c) 2024 Panda, 2257691535@qq.com
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+*/
+
+`timescale 1ns / 1ps
+/********************************************************************
+本模块: APB-I2C的寄存器接口
+
+描述: 
+寄存器->
+    偏移量  |    含义                     |   读写特性    |                 备注
+    0x00    0:发送fifo是否满                    R
+            1:发送fifo写使能                    W         写该寄存器且该位为1'b1时产生发送fifo写使能
+            10~2:发送fifo写数据                 W                 {last(1bit), data(8bit)}
+            16:接收fifo是否空                   R
+            17:接收fifo读使能                   W         写该寄存器且该位为1'b1时产生接收fifo读使能
+            25~18:接收fifo读数据                R
+    0x04    0:I2C全局中断使能                   W
+            8:I2C发送指定字节数中断使能         W
+            9:I2C从机响应错误中断使能           W
+            10:I2C接收指定字节数中断使能        W
+            11:I2C接收溢出中断使能              W
+    0x08    7~0:I2C发送中断字节数阈值           W                  发送字节数 > 阈值时发生中断
+            15~8:I2C接收中断字节数阈值          W                  接收字节数 > 阈值时发生中断
+			23~16:I2C时钟分频系数               W                  分频数 = (分频系数 + 1) * 2
+			                                                              分频系数应>=1
+    0x0C    0:I2C全局中断标志                  RWC                 请在中断服务函数中清除中断标志
+            1:I2C发送指定字节数中断标志         R
+            2:I2C从机响应错误中断标志           R
+            3:I2C接收指定字节数中断标志         R
+            4:I2C接收溢出中断标志               R
+            19~8:I2C发送字节数                RWC                  每当发送一个I2C数据包后更新
+            31~20:I2C接收字节数               RWC                  每当接收一个I2C数据包后更新
+
+注意：
+I2C发送/接收指定字节数中断每当发送/接收一个I2C数据包后判断
+每个I2C数据包不能超过15字节
+
+协议:
+APB SLAVE
+
+作者: 陈家耀
+日期: 2024/06/14
+********************************************************************/
+
+
+module regs_if_for_i2c #(
+    parameter real simulation_delay = 1 // 仿真延时
+)(
+    // 时钟和复位
+    input wire clk,
+    input wire resetn,
+    
+    // APB从机接口
+    input wire[31:0] paddr,
+    input wire psel,
+    input wire penable,
+    input wire pwrite,
+    input wire[31:0] pwdata,
+    output wire pready_out, // const -> 1'b1
+    output wire[31:0] prdata_out,
+    output wire pslverr_out, // const -> 1'b0
+    
+    // 发送fifo写端口
+    output wire tx_fifo_wen,
+    output wire[8:0] tx_fifo_din,
+    input wire tx_fifo_full,
+    // 接收fifo读端口
+    output wire rx_fifo_ren,
+    input wire[7:0] rx_fifo_dout,
+    input wire rx_fifo_empty,
+    
+    // I2C时钟分频系数
+    output wire[7:0] i2c_scl_div_rate,
+    
+    // I2C发送完成指示
+    input wire i2c_tx_done,
+    input wire[3:0] i2c_tx_bytes_n,
+    // I2C接收完成指示
+    input wire i2c_rx_done,
+    input wire[3:0] i2c_rx_bytes_n,
+    // I2C从机响应错误
+    input wire i2c_slave_resp_err,
+    // I2C接收溢出
+    input wire i2c_rx_overflow,
+    
+    // 中断信号
+    output wire itr
+);
+    
+    /** APB写寄存器和中断处理 **/
+    // 0x00
+    reg tx_fifo_wen_reg; // 发送fifo写使能
+    reg[8:0] tx_fifo_din_regs; // 发送fifo写数据
+    reg rx_fifo_ren_reg; // 接收fifo读使能
+    // 0x04
+    reg global_itr_en; // 全局中断使能
+    reg i2c_tx_reach_bytes_n_itr_en; // I2C发送指定字节数中断使能
+    reg i2c_slave_resp_err_itr_en; // I2C从机响应错误中断使能
+    reg i2c_rx_reach_bytes_n_itr_en; // I2C接收指定字节数中���使能
+    reg i2c_rx_overflow_itr_en; // I2C接收溢出中断使能
+    // 0x08
+    reg[7:0] i2c_tx_bytes_n_th; // I2C发送中断字节数阈值
+    reg[7:0] i2c_rx_bytes_n_th; // I2C接收中断字节数阈值
+    reg[7:0] i2c_scl_div_rate_regs; // I2C时钟分频系数
+    // 0x0C
+    reg global_itr_flag; // 全局中断标志
+    reg[3:0] sub_itr_flag; // 子中断标志
+    reg[11:0] i2c_bytes_n_sent; // I2C发送字节数
+    reg[11:0] i2c_bytes_n_rev; // I2C接收字节数
+    // 中断处理
+    reg i2c_tx_done_d; // 延迟1clk的I2C发送完成指示
+    reg i2c_rx_done_d; // 延迟1clk的I2C发送完成指示
+    reg i2c_tx_reach_bytes_n_itr_req; // I2C发送指定字节数中断请求
+    wire i2c_slave_resp_err_itr_req; // I2C从机响应错误中断请求
+    reg i2c_rx_reach_bytes_n_itr_req; // I2C接收指定字节数中断请求
+    wire i2c_rx_overflow_itr_req; // I2C接收溢出中断请求
+    wire[3:0] org_itr_req_vec; // 原始中断请求向量
+    wire global_itr_req; // 总中断请求
+    
+    assign tx_fifo_wen = tx_fifo_wen_reg;
+    assign tx_fifo_din = tx_fifo_din_regs;
+    assign rx_fifo_ren = rx_fifo_ren_reg;
+    
+    assign i2c_scl_div_rate = i2c_scl_div_rate_regs;
+    
+    assign i2c_slave_resp_err_itr_req = i2c_slave_resp_err;
+    assign i2c_rx_overflow_itr_req = i2c_rx_overflow;
+    
+    assign org_itr_req_vec = {i2c_rx_overflow_itr_req, i2c_rx_reach_bytes_n_itr_req, i2c_slave_resp_err_itr_req, i2c_tx_reach_bytes_n_itr_req} & 
+        {i2c_rx_overflow_itr_en, i2c_rx_reach_bytes_n_itr_en, i2c_slave_resp_err_itr_en, i2c_tx_reach_bytes_n_itr_en};
+    assign global_itr_req = (|org_itr_req_vec) & global_itr_en & (~global_itr_flag);
+    
+    // 发送fifo写使能
+    always @(posedge clk or negedge resetn)
+    begin
+        if(~resetn)
+            tx_fifo_wen_reg <= 1'b0;
+        else
+            # simulation_delay tx_fifo_wen_reg <= psel & penable & pwrite & (paddr[3:2] == 2'd0) & pwdata[1];
+    end
+    // 发送fifo写数据
+    always @(posedge clk)
+    begin
+        if(psel & penable & pwrite & (paddr[3:2] == 2'd0))
+            # simulation_delay tx_fifo_din_regs <= pwdata[10:2];
+    end
+    // 接收fifo读使能
+    always @(posedge clk or negedge resetn)
+    begin
+        if(~resetn)
+            rx_fifo_ren_reg <= 1'b0;
+        else
+            # simulation_delay rx_fifo_ren_reg <= psel & penable & pwrite & (paddr[3:2] == 2'd0) & pwdata[17];
+    end
+    
+    // 全局中断使能
+    // I2C发送指定字节数中断使能
+    // I2C从机响应错误中断使能
+    // I2C接收指定字节数中断使能
+    // I2C接收溢出中断使能
+    always @(posedge clk or negedge resetn)
+    begin
+        if(~resetn)
+            {i2c_rx_overflow_itr_en, i2c_rx_reach_bytes_n_itr_en, i2c_slave_resp_err_itr_en, i2c_tx_reach_bytes_n_itr_en, global_itr_en} <= 5'd0;
+        else if(psel & penable & pwrite & (paddr[3:2] == 2'd1))
+            # simulation_delay {i2c_rx_overflow_itr_en, i2c_rx_reach_bytes_n_itr_en, i2c_slave_resp_err_itr_en, i2c_tx_reach_bytes_n_itr_en, global_itr_en} <= 
+                {pwdata[11:8], pwdata[0]};
+    end
+    
+    // I2C发送中断字节数阈值
+    // I2C接收中断字节数阈值
+    // I2C时钟分频系数
+    always @(posedge clk)
+    begin
+        if(psel & penable & pwrite & (paddr[3:2] == 2'd2))
+            # simulation_delay {i2c_scl_div_rate_regs, i2c_rx_bytes_n_th, i2c_tx_bytes_n_th} <= pwdata[23:0];
+    end
+    
+    // 全局中断标志
+    always @(posedge clk or negedge resetn)
+    begin
+        if(~resetn)
+            global_itr_flag <= 1'b0;
+        else if(psel & penable & pwrite & (paddr[3:2] == 2'd3))
+            # simulation_delay global_itr_flag <= 1'b0;
+        else if(~global_itr_flag)
+            # simulation_delay global_itr_flag <= global_itr_req;
+    end
+    // 子中断标志
+    always @(posedge clk)
+    begin
+        if(global_itr_req)
+            # simulation_delay sub_itr_flag <= org_itr_req_vec;
+    end
+    // I2C发送字节数
+    always @(posedge clk or negedge resetn)
+    begin
+        if(~resetn)
+            i2c_bytes_n_sent <= 12'd0;
+        else if(psel & penable & pwrite & (paddr[3:2] == 2'd3))
+            # simulation_delay i2c_bytes_n_sent <= 12'd0;
+        else if(i2c_tx_done)
+            # simulation_delay i2c_bytes_n_sent <= i2c_bytes_n_sent + i2c_tx_bytes_n;
+    end
+    // I2C接收字节数
+    always @(posedge clk or negedge resetn)
+    begin
+        if(~resetn)
+            i2c_bytes_n_rev <= 12'd0;
+        else if(psel & penable & pwrite & (paddr[3:2] == 2'd3))
+            # simulation_delay i2c_bytes_n_rev <= 12'd0;
+        else if(i2c_rx_done)
+            # simulation_delay i2c_bytes_n_rev <= i2c_bytes_n_rev + i2c_rx_bytes_n;
+    end
+    
+    // 延迟1clk的I2C发送完成指示
+    always @(posedge clk or negedge resetn)
+    begin
+        if(~resetn)
+            i2c_tx_done_d <= 1'b0;
+        else
+            # simulation_delay i2c_tx_done_d <= i2c_tx_done;
+    end
+    // 延迟1clk的I2C发送完成指示
+    always @(posedge clk or negedge resetn)
+    begin
+        if(~resetn)
+            i2c_rx_done_d <= 1'b0;
+        else
+            # simulation_delay i2c_rx_done_d <= i2c_rx_done;
+    end
+    // I2C发送指定字节数中断请求
+    always @(posedge clk or negedge resetn)
+    begin
+        if(~resetn)
+            i2c_tx_reach_bytes_n_itr_req <= 1'b0;
+        else
+            # simulation_delay i2c_tx_reach_bytes_n_itr_req <= i2c_tx_done_d & (i2c_bytes_n_sent > i2c_tx_bytes_n_th);
+    end
+    // I2C接收指定字节数中断请求
+    always @(posedge clk or negedge resetn)
+    begin
+        if(~resetn)
+            i2c_rx_reach_bytes_n_itr_req <= 1'b0;
+        else
+            # simulation_delay i2c_rx_reach_bytes_n_itr_req <= i2c_rx_done_d & (i2c_bytes_n_rev > i2c_rx_bytes_n_th);
+    end
+    
+    // 中断发生器
+    itr_generator #(
+        .pulse_w(10),
+        .simulation_delay(simulation_delay)
+    )itr_generator_u(
+        .clk(clk),
+        .rst_n(resetn),
+        
+        .itr_org(global_itr_req),
+        
+        .itr(itr)
+    );
+    
+    /** APB读寄存器 **/
+    reg[31:0] prdata_out_regs; // APB读数据输出
+    
+    assign pready_out = 1'b1;
+    assign prdata_out = prdata_out_regs;
+    assign pslverr_out = 1'b0;
+    
+    // APB读数据输出
+    always @(posedge clk)
+    begin
+        if(psel & (~pwrite))
+        begin
+            # simulation_delay;
+            
+            case(paddr[3:2])
+                2'd0: prdata_out_regs <= {6'dx, rx_fifo_dout, 1'bx, rx_fifo_empty, 15'dx, tx_fifo_full};
+                2'd1: prdata_out_regs <= 32'dx;
+                2'd2: prdata_out_regs <= 32'dx;
+                2'd3: prdata_out_regs <= {i2c_bytes_n_rev, i2c_bytes_n_sent, 3'dx, sub_itr_flag, global_itr_flag};
+                default: prdata_out_regs <= 32'dx;
+            endcase
+        end
+    end
+    
+endmodule

CutestPanda_Opensoc/103_generic_fsmc_ctrler/firmware/examples/fsmc_example.c

@@ -0,0 +1,61 @@
+/************************************************************************************************************************
+FSMC������ʾ������
+@brief  ����FSMC������ʵ���ⲿSRAM��д
+@date   2024/08/29
+@author �¼�ҫ
+@eidt   2024/08/29 1.00 �����˵�һ����ʽ�汾
+************************************************************************************************************************/
+
+#include "../generic_fsmc_ctrler.h"
+
+////////////////////////////////////////////////////////////////////////////////////////////////////////////
+
+#define BASEADDR_FSMC 0x60000000 // FSMC�������ַ
+
+////////////////////////////////////////////////////////////////////////////////////////////////////////////
+
+static Fsmc fsmc; // FSMC����������ṹ��
+
+////////////////////////////////////////////////////////////////////////////////////////////////////////////
+
+void fsmc_example(void){
+	init_fsmc(BASEADDR_FSMC, &fsmc); // ��ʼ��FSMC����
+	
+	/*
+	����FSMC������ʱ�����
+	
+	��ַ���������� = 10
+	���ݽ��������� = 10
+	���ݱ��������� = 10
+	*/
+	fsmc_cfg_rt_pars(&fsmc, 9, 9, 9);
+	
+	/** д�ⲿSRAM **/
+	for(uint32_t i = 0;i < 50;i++){
+		fsmc_write_16(&fsmc, i << 1, i + 1);
+	}
+	
+	/** ���ⲿSRAM **/
+	uint8_t verify_ok = 1;
+	
+	for(uint32_t i = 0;i < 50;i++){
+		uint16_t d = fsmc_read_16(&fsmc, i << 1);
+		
+		if(d != (i + 1)){
+			verify_ok = 0;
+			
+			break;
+		}
+	}
+	
+	/** ��֤��д����һ���� **/
+	if(verify_ok){
+		// ��д����һ��
+		// ...
+	}else{
+		// ��д���ݲ�һ��
+		// ...
+	}
+	
+	while(1);
+}

CutestPanda_Opensoc/103_generic_fsmc_ctrler/firmware/generic_fsmc_ctrler.c

@@ -0,0 +1,99 @@
+/************************************************************************************************************************
+ͨ��FSMC����������(��Դ�ļ�)
+@brief  ͨ��FSMC����������
+@date   2024/08/29
+@author �¼�ҫ
+@eidt   2024/08/29 1.00 �����˵�һ����ʽ�汾
+************************************************************************************************************************/
+
+#include "generic_fsmc_ctrler.h"
+
+////////////////////////////////////////////////////////////////////////////////////////////////////////////
+
+/*************************
+@init
+@public
+@brief  ��ʼ��FSMC������
+@param  base_addr FSMC�������ַ
+			  fsmc FSMC����(�ṹ��ָ��)
+@return none
+*************************/
+void init_fsmc(uint32_t base_addr, Fsmc* fsmc){
+	fsmc->base_addr_regs = base_addr;
+	fsmc->base_addr_mem = base_addr + 0x00001000;
+}
+
+/*************************
+@cfg
+@public
+@brief  ����FSMC������ʱ�����
+@param  fsmc FSMC����(�ṹ��ָ��)
+		    addr_set  ��ַ���������� - 1
+			  data_set  ���ݽ��������� - 1
+	      data_hold ���ݱ��������� - 1
+@return none
+*************************/
+void fsmc_cfg_rt_pars(Fsmc* fsmc, uint8_t addr_set, uint8_t data_set, uint8_t data_hold){
+	uint16_t* ptr = (uint16_t*)fsmc->base_addr_regs;
+	
+	ptr[0] = ((uint16_t)addr_set) | (((uint16_t)data_set) << 8);
+	ptr[1] = (uint16_t)data_hold;
+}
+
+/*************************
+@io
+@public
+@brief  FSMC��������16λ����λ��д����
+@param  fsmc FSMC����(�ṹ��ָ��)
+		    ofs FSMC�洢ƫ�Ƶ�ַ
+        data ��д�İ�������
+@return none
+*************************/
+void fsmc_write_16(Fsmc* fsmc, uint32_t ofs, uint16_t data){
+	uint16_t* ptr = (uint16_t*)(fsmc->base_addr_mem + ofs);
+	
+	*ptr = data;
+}
+
+/*************************
+@io
+@public
+@brief  FSMC��������8λ����λ��д����
+@param  fsmc FSMC����(�ṹ��ָ��)
+		    ofs FSMC�洢ƫ�Ƶ�ַ
+        data ��д���ֽ�����
+@return none
+*************************/
+void fsmc_write_8(Fsmc* fsmc, uint32_t ofs, uint8_t data){
+	uint16_t* ptr = (uint16_t*)(fsmc->base_addr_mem + (ofs << 1));
+	
+	*ptr = (uint16_t)data;
+}
+
+/*************************
+@io
+@public
+@brief  FSMC��������16����������
+@param  fsmc FSMC����(�ṹ��ָ��)
+		    ofs FSMC�洢ƫ�Ƶ�ַ
+@return ��ȡ���İ�������
+*************************/
+uint16_t fsmc_read_16(Fsmc* fsmc, uint32_t ofs){
+	uint16_t* ptr = (uint16_t*)(fsmc->base_addr_mem + ofs);
+	
+	return *ptr;
+}
+
+/*************************
+@io
+@public
+@brief  FSMC��������8����������
+@param  fsmc FSMC����(�ṹ��ָ��)
+		    ofs FSMC�洢ƫ�Ƶ�ַ
+@return ��ȡ�����ֽ�����
+*************************/
+uint8_t fsmc_read_8(Fsmc* fsmc, uint32_t ofs){
+	uint16_t* ptr = (uint16_t*)(fsmc->base_addr_mem + (ofs << 1));
+	
+	return (uint8_t)(*ptr & 0x00FF);
+}

CutestPanda_Opensoc/103_generic_fsmc_ctrler/firmware/generic_fsmc_ctrler.h

@@ -0,0 +1,25 @@
+#include <stdint.h>
+
+////////////////////////////////////////////////////////////////////////////////////////////////////////////
+
+#ifndef __AHB_FSMC
+#define __AHB_FSMC
+
+typedef struct{
+	uint32_t base_addr_regs; // ���üĴ���Ƭ����ַ
+	uint32_t base_addr_mem; // FSMC����ַ
+}Fsmc;
+
+#endif
+
+////////////////////////////////////////////////////////////////////////////////////////////////////////////
+
+void init_fsmc(uint32_t base_addr, Fsmc* fsmc); // ��ʼ��FSMC������
+
+void fsmc_cfg_rt_pars(Fsmc* fsmc, uint8_t addr_set, uint8_t data_set, uint8_t data_hold); // ����FSMC������ʱ�����
+
+void fsmc_write_16(Fsmc* fsmc, uint32_t ofs, uint16_t data); // FSMC��������16λ����λ��д����
+void fsmc_write_8(Fsmc* fsmc, uint32_t ofs, uint8_t data); // FSMC��������8λ����λ��д����
+
+uint16_t fsmc_read_16(Fsmc* fsmc, uint32_t ofs); // FSMC��������16����������
+uint8_t fsmc_read_8(Fsmc* fsmc, uint32_t ofs); // FSMC��������8����������

CutestPanda_Opensoc/103_generic_fsmc_ctrler/rtl/ahb_fsmc.v

@@ -0,0 +1,229 @@
+/*
+MIT License
+
+Copyright (c) 2024 Panda, 2257691535@qq.com
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+*/
+
+`timescale 1ns / 1ps
+/********************************************************************
+本模块: AHB-FSMC
+
+描述:
+带AHB-Lite从接口的FSMC控制器
+
+突发大小固定为16位
+
+偏移量0x000_0000~0x000_0FFF:
+	子偏移量0x00 -> 7~0:   地址建立周期数 - 1
+					15~8:  数据建立周期数 - 1
+	子偏移量0x02 -> 7~0:   数据保持周期数 - 1
+偏移量0x000_1000~0x3FF_FFFF:
+	子偏移量0x000_0000~0x3FF_EFFF -> FSMC
+
+注意：
+不支持非对齐传输
+
+协议:
+AHB SLAVE
+FSMC MASTER
+
+作者: 陈家耀
+日期: 2024/07/18
+********************************************************************/
+
+
+module ahb_fsmc #(
+	parameter real simulation_delay = 0 // 仿真延时
+)(
+	// 时钟和复位
+    input wire hclk,
+    input wire hresetn,
+    
+    // AHB-Lite SLAVE
+    input wire[31:0] s_ahb_haddr,
+    input wire[2:0] s_ahb_hburst, // ignored(assumed to be 3'b000, i.e. SINGLE)
+    input wire[3:0] s_ahb_hprot, // ignored
+    output wire[31:0] s_ahb_hrdata,
+    input wire s_ahb_hready_in,
+    output wire s_ahb_hready_out,
+    output wire s_ahb_hresp, // const -> 1'b0
+    input wire[2:0] s_ahb_hsize, // ignored(assumed to be 3'b001)
+    input wire[1:0] s_ahb_htrans, // only 2'b00(IDLE) and 2'b10(NONSEQ) are supported
+    input wire[31:0] s_ahb_hwdata,
+    input wire[3:0] s_ahb_hwstrb,
+    input wire s_ahb_hwrite,
+    input wire s_ahb_hsel,
+	
+	// FSMC MASTER
+	output wire[1:0] fsmc_nbl, // 数据掩码
+	output wire[25:0] fsmc_addr, // 地址线
+	output wire fsmc_nwe, // 写入使能
+	output wire fsmc_noe, // 输出使能(读使能)
+	output wire fsmc_ne, // 片选信号
+	// 数据线(1'b1 -> 输入, 1'b0 -> 输出)
+	input wire[15:0] fsmc_data_i,
+	output wire[15:0] fsmc_data_o,
+	output wire[15:0] fsmc_data_t
+);
+
+	/** FSMC控制器 **/
+    // AHB传输开始指示
+    wire ahb_trans_start;
+	// 运行时参数
+	reg to_upd_rt_pars_0; // 更新第0组运行时参数(指示)
+	reg to_upd_rt_pars_1; // 更新第1组运行时参数(指示)
+	reg[7:0] addr_set; // 地址建立周期数 - 1
+	reg[7:0] data_set; // 数据建立周期数 - 1
+	reg[7:0] data_hold; // 数据保持周期数 - 1
+	// 流程控制
+	reg fsmc_ctrler_start;
+	wire fsmc_ctrler_done;
+	// 传输参数
+	wire[15:0] wdata; // 写数据
+	wire[1:0] data_mask; // 字节使能掩码
+	wire[25:0] trans_addr; // 传输地址
+	wire is_rd; // 是否读传输
+	// 读数据输出
+	wire[15:0] m_axis_rd_data;
+	wire m_axis_rd_valid;
+    
+    assign ahb_trans_start = s_ahb_hready_in & s_ahb_htrans[1] & s_ahb_hsel;
+	
+	// 更新第0组运行时参数(指示)
+	always @(posedge hclk or negedge hresetn)
+	begin
+		if(~hresetn)
+			to_upd_rt_pars_0 <= 1'b0;
+		else
+			# simulation_delay to_upd_rt_pars_0 <= ahb_trans_start & (s_ahb_haddr[25:12] == 14'd0) & (~s_ahb_haddr[1]);
+	end
+	// 更新第1组运行时参数(指示)
+	always @(posedge hclk or negedge hresetn)
+	begin
+		if(~hresetn)
+			to_upd_rt_pars_1 <= 1'b0;
+		else
+			# simulation_delay to_upd_rt_pars_1 <= ahb_trans_start & (s_ahb_haddr[25:12] == 14'd0) & s_ahb_haddr[1];
+	end
+	
+	// 控制器运行时参数
+	always @(posedge hclk)
+	begin
+		if(to_upd_rt_pars_0)
+			# simulation_delay {data_set, addr_set} <= s_ahb_hwdata[15:0];
+	end
+	always @(posedge hclk)
+	begin
+		if(to_upd_rt_pars_1)
+			# simulation_delay data_hold <= s_ahb_hwdata[23:16];
+	end
+	
+	fsmc_ctrler #(
+		.simulation_delay(simulation_delay)
+	)fsmc_ctrler_u(
+		.clk(hclk),
+		.rst_n(hresetn),
+		
+		.ctrler_start(fsmc_ctrler_start),
+		.ctrler_idle(),
+		.ctrler_done(fsmc_ctrler_done),
+		
+		.addr_set(addr_set),
+		.data_set(data_set),
+		.data_hold(data_hold),
+		
+		.wdata(wdata),
+		.data_mask(data_mask),
+		.trans_addr(trans_addr),
+		.is_rd(is_rd),
+		
+		.m_axis_rd_data(m_axis_rd_data),
+		.m_axis_rd_valid(m_axis_rd_valid),
+		
+		.fsmc_nbl(fsmc_nbl),
+		.fsmc_addr(fsmc_addr),
+		.fsmc_nwe(fsmc_nwe),
+		.fsmc_noe(fsmc_noe),
+		.fsmc_ne(fsmc_ne),
+		.fsmc_data_i(fsmc_data_i),
+		.fsmc_data_o(fsmc_data_o),
+		.fsmc_data_t(fsmc_data_t)
+	);
+	
+	/** AHB从接口 **/
+	reg[31:0] haddr_latched; // 锁存的AHB传输地址
+	reg hwrite_latched; // 锁存的AHB传输读写类型
+	reg[31:0] hrdata_regs; // AHB读数据
+	reg hready_out_reg; // AHB上一次传输完成
+	
+	assign s_ahb_hrdata = hrdata_regs;
+	assign s_ahb_hready_out = hready_out_reg;
+	assign s_ahb_hresp = 1'b0;
+	
+	assign wdata = haddr_latched[1] ? s_ahb_hwdata[31:16]:s_ahb_hwdata[15:0];
+	assign data_mask = hwrite_latched ? (haddr_latched[1] ? (~s_ahb_hwstrb[3:2]):(~s_ahb_hwstrb[1:0])):2'b00;
+	assign trans_addr = haddr_latched[25:0];
+	assign is_rd = ~hwrite_latched;
+	
+	// 锁存的AHB传输地址
+	always @(posedge hclk)
+	begin
+		if(s_ahb_hready_in & s_ahb_htrans[1] & s_ahb_hsel)
+			# simulation_delay haddr_latched <= s_ahb_haddr - 32'h0000_1000;
+	end
+	// 锁存的AHB传输读写类型
+	always @(posedge hclk)
+	begin
+		if(s_ahb_hready_in & s_ahb_htrans[1] & s_ahb_hsel)
+			# simulation_delay hwrite_latched <= s_ahb_hwrite;
+	end
+	
+	// AHB读数据
+	always @(posedge hclk)
+	begin
+		if(m_axis_rd_valid & haddr_latched[1])
+			# simulation_delay hrdata_regs[31:16] <= m_axis_rd_data;
+	end
+	always @(posedge hclk)
+	begin
+		if(m_axis_rd_valid & (~haddr_latched[1]))
+			# simulation_delay hrdata_regs[15:0] <= m_axis_rd_data;
+	end
+	// AHB上一次传输完成
+	always @(posedge hclk or negedge hresetn)
+	begin
+		if(~hresetn)
+			hready_out_reg <= 1'b1;
+		else
+			# simulation_delay hready_out_reg <= hready_out_reg ? 
+				(~(ahb_trans_start & (s_ahb_haddr[25:12] != 14'd0))):fsmc_ctrler_done;
+	end
+	
+	// FSMC控制器开始信号
+	always @(posedge hclk or negedge hresetn)
+	begin
+		if(~hresetn)
+			fsmc_ctrler_start <= 1'b0;
+		else
+			# simulation_delay fsmc_ctrler_start <= ahb_trans_start & (s_ahb_haddr[25:12] != 14'd0);
+	end
+	
+endmodule

CutestPanda_Opensoc/103_generic_fsmc_ctrler/rtl/axi_fsmc.v

@@ -0,0 +1,368 @@
+/*
+MIT License
+
+Copyright (c) 2024 Panda, 2257691535@qq.com
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+*/
+
+`timescale 1ns / 1ps
+/********************************************************************
+本模块: AXI-FSMC
+
+描述:
+带AXI-Lite从接口的FSMC控制器
+
+突发大小固定为16位
+
+偏移量0x000_0000~0x000_0FFF:
+	子偏移量0x00 -> 7~0:   地址建立周期数 - 1
+					15~8:  数据建立周期数 - 1
+	子偏移量0x02 -> 7~0:   数据保持周期数 - 1
+偏移量0x000_1000~0x3FF_FFFF:
+	子偏移量0x000_0000~0x3FF_EFFF -> FSMC
+
+注意：
+不支持非对齐传输
+
+协议:
+AXI SLAVE
+FSMC MASTER
+
+作者: 陈家耀
+日期: 2024/08/29
+********************************************************************/
+
+
+module axi_fsmc #(
+	parameter real simulation_delay = 0 // 仿真延时
+)(
+	// 时钟和复位
+    input wire s_axi_clk,
+    input wire s_axi_resetn,
+    
+    // AXI-Lite SLAVE
+    // 读地址通道
+    input wire[31:0] s_axi_araddr,
+    input wire[2:0] s_axi_arsize, // ignored(assumed to be 3'b001)
+    input wire s_axi_arvalid,
+    output wire s_axi_arready,
+    // 写地址通道
+    input wire[31:0] s_axi_awaddr,
+    input wire[2:0] s_axi_awsize, // ignored(assumed to be 3'b001)
+    input wire s_axi_awvalid,
+    output wire s_axi_awready,
+    // 写响应通道
+    output wire[1:0] s_axi_bresp, // const -> 2'b00
+    output wire s_axi_bvalid,
+    input wire s_axi_bready,
+    // 读数据通道
+    output wire[31:0] s_axi_rdata,
+    output wire[1:0] s_axi_rresp, // const -> 2'b00
+    output wire s_axi_rvalid,
+    input wire s_axi_rready,
+    // 写数据通道
+    input wire[31:0] s_axi_wdata,
+    input wire[3:0] s_axi_wstrb,
+    input wire s_axi_wvalid,
+    output wire s_axi_wready,
+	
+	// FSMC MASTER
+	output wire[1:0] fsmc_nbl, // 数据掩码
+	output wire[25:0] fsmc_addr, // 地址线
+	output wire fsmc_nwe, // 写入使能
+	output wire fsmc_noe, // 输出使能(读使能)
+	output wire fsmc_ne, // 片选信号
+	// 数据线(1'b1 -> 输入, 1'b0 -> 输出)
+	input wire[15:0] fsmc_data_i,
+	output wire[15:0] fsmc_data_o,
+	output wire[15:0] fsmc_data_t
+);
+	
+	/** AXI传输流程控制 **/
+	wire axi_trans_done; // AXI传输完成(指示)
+	reg axi_addr_available; // AXI地址寄存器可用(标志)
+	reg axi_wdata_available; // AXI写数据寄存器可用(标志)
+	reg axi_rd_reg; // 是否AXI读传输
+	
+	// AXI地址寄存器可用(标志)
+	always @(posedge s_axi_clk or negedge s_axi_resetn)
+	begin
+		if(~s_axi_resetn)
+			axi_addr_available <= 1'b1;
+		else
+			# simulation_delay axi_addr_available <= axi_addr_available ? 
+				(~((s_axi_arvalid & s_axi_arready) | (s_axi_awvalid & s_axi_awready))):axi_trans_done;
+	end
+	
+	// AXI写数据寄存器可用(标志)
+	always @(posedge s_axi_clk or negedge s_axi_resetn)
+	begin
+		if(~s_axi_resetn)
+			axi_wdata_available <= 1'b1;
+		else
+			# simulation_delay axi_wdata_available <= axi_wdata_available ? 
+				(~(s_axi_wvalid & s_axi_wready)):(axi_trans_done & (~axi_rd_reg));
+	end
+	
+	/** AXI读/写地址通道 **/
+	wire axi_ar_req; // AXI读传输请求
+	wire axi_aw_req; // AXI写传输请求
+	wire arb_valid; // 仲裁结果有效
+	reg arb_valid_d; // 延迟1clk的仲裁结果有效
+	wire[1:0] arb_grant; // 仲裁授权(独热码)
+	reg[1:0] arb_grant_d; // 延迟1clk的仲裁授权(独热码)
+	reg[31:0] axi_addr_regs; // AXI地址寄存器
+	
+	assign {s_axi_arready, s_axi_awready} = arb_grant_d;
+	
+	assign axi_ar_req = s_axi_arvalid & axi_addr_available & (~arb_valid_d);
+	assign axi_aw_req = s_axi_awvalid & axi_addr_available & (~arb_valid_d);
+	
+	// 延迟1clk的仲裁结果有效
+	always @(posedge s_axi_clk or negedge s_axi_resetn)
+	begin
+		if(~s_axi_resetn)
+			arb_valid_d <= 1'b0;
+		else
+			# simulation_delay arb_valid_d <= arb_valid;
+	end
+	// 延迟1clk的仲裁授权(独热码)
+	always @(posedge s_axi_clk or negedge s_axi_resetn)
+	begin
+		if(~s_axi_resetn)
+			arb_grant_d <= 2'b00;
+		else
+			# simulation_delay arb_grant_d <= arb_grant;
+	end
+	
+	// AXI地址���存器
+	always @(posedge s_axi_clk)
+	begin
+		if((s_axi_arvalid & s_axi_arready) | (s_axi_awvalid & s_axi_awready))
+			// 断言: AR通道和AW通道不会同时握手!
+			# simulation_delay axi_addr_regs <= (s_axi_arvalid & s_axi_arready) ? 
+				s_axi_araddr:s_axi_awaddr;
+	end
+	// 是否AXI读传输
+	always @(posedge s_axi_clk)
+	begin
+		if((s_axi_arvalid & s_axi_arready) | (s_axi_awvalid & s_axi_awready))
+			// 断言: AR通道和AW通道不会同时握手!
+			# simulation_delay axi_rd_reg <= s_axi_arvalid & s_axi_arready;
+	end
+	
+	// Round-Robin仲裁器
+	round_robin_arbitrator #(
+		.chn_n(2),
+		.simulation_delay(simulation_delay)
+	)round_robin_arbitrator_u(
+		.clk(s_axi_clk),
+		.rst_n(s_axi_resetn),
+		
+		.req({axi_ar_req, axi_aw_req}),
+		.grant(arb_grant),
+		.sel(),
+		.arb_valid(arb_valid)
+	);
+	
+	/** AXI写响应通道 **/
+	reg axi_bvalid; // AXI写响应有效
+	
+	assign s_axi_bresp = 2'b00;
+	assign s_axi_bvalid = axi_bvalid;
+	
+	// AXI写响应有效
+	always @(posedge s_axi_clk or negedge s_axi_resetn)
+	begin
+		if(~s_axi_resetn)
+			axi_bvalid <= 1'b0;
+		else
+			# simulation_delay axi_bvalid <= axi_bvalid ? (~s_axi_bready):(axi_trans_done & (~axi_rd_reg));
+	end
+	
+	/** AXI读数据通道 **/
+	// 配置寄存器片读数据输出
+	wire[15:0] cfg_reg_slice_rdata;
+	wire cfg_reg_slice_rdata_vld;
+	// FSMC控制器读数据输出
+	wire[15:0] m_axis_rd_data;
+	wire m_axis_rd_valid;
+	// AXI读数据
+	reg[31:0] axi_rdata_regs; // AXI读数据寄存器
+	reg axi_rdata_valid; // AXI读数据有效
+	
+	assign s_axi_rdata = axi_rdata_regs;
+	assign s_axi_rresp = 2'b00;
+	assign s_axi_rvalid = axi_rdata_valid;
+	
+	// AXI读数据寄存器
+	always @(posedge s_axi_clk)
+	begin
+		if((m_axis_rd_valid | cfg_reg_slice_rdata_vld) & axi_addr_regs[1])
+			# simulation_delay axi_rdata_regs[31:16] <= m_axis_rd_valid ? m_axis_rd_data:cfg_reg_slice_rdata;
+	end
+	always @(posedge s_axi_clk)
+	begin
+		if((m_axis_rd_valid | cfg_reg_slice_rdata_vld) & (~axi_addr_regs[1]))
+			# simulation_delay axi_rdata_regs[15:0] <= m_axis_rd_valid ? m_axis_rd_data:cfg_reg_slice_rdata;
+	end
+	// AXI读数据有效
+	always @(posedge s_axi_clk or negedge s_axi_resetn)
+	begin
+		if(~s_axi_resetn)
+			axi_rdata_valid <= 1'b0;
+		else
+			# simulation_delay axi_rdata_valid <= axi_rdata_valid ? (~s_axi_rready):(m_axis_rd_valid | cfg_reg_slice_rdata_vld);
+	end
+	
+	/** AXI写数据通道 **/
+	reg[31:0] axi_wdata_regs; // AXI写数据寄存器
+	reg[3:0] axi_wstrb_regs; // AXI写字节使能寄存器
+	
+	assign s_axi_wready = axi_wdata_available;
+	
+	// AXI写数据寄存器
+	always @(posedge s_axi_clk)
+	begin
+		if(s_axi_wvalid & s_axi_wready)
+			# simulation_delay axi_wdata_regs <= s_axi_wdata;
+	end
+	// AXI写字节使能寄存器
+	always @(posedge s_axi_clk)
+	begin
+		if(s_axi_wvalid & s_axi_wready)
+			# simulation_delay axi_wstrb_regs <= s_axi_wstrb;
+	end
+	
+	/**
+	配置寄存器片
+	
+	偏移量0x000_0000~0x000_0FFF:
+		子偏移量0x00 -> 7~0:   地址建立周期数 - 1
+						15~8:  数据建立周期数 - 1
+		子偏移量0x02 -> 7~0:   数据保持周期数 - 1
+	**/
+	reg[2:0] cfg_reg_slice_proc_ctrl; // 流程独热码
+	// FSMC控制器运行时参数
+	reg[7:0] addr_set; // 地址建立周期数 - 1
+	reg[7:0] data_set; // 数据建立周期数 - 1
+	reg[7:0] data_hold; // 数据保持周期数 - 1
+	
+	assign cfg_reg_slice_rdata = 16'dx;
+	assign cfg_reg_slice_rdata_vld = cfg_reg_slice_proc_ctrl[2] & axi_rd_reg;
+	
+	// 流程独热码
+	always @(posedge s_axi_clk or negedge s_axi_resetn)
+	begin
+		if(~s_axi_resetn)
+			cfg_reg_slice_proc_ctrl <= 3'b001;
+		else if((cfg_reg_slice_proc_ctrl[0] & (~axi_addr_available) & 
+			(axi_addr_regs[25:12] == 14'd0) & (axi_rd_reg ? 1'b1:(~axi_wdata_available))) | 
+			cfg_reg_slice_proc_ctrl[1] | 
+			cfg_reg_slice_proc_ctrl[2])
+			# simulation_delay cfg_reg_slice_proc_ctrl <= {cfg_reg_slice_proc_ctrl[1:0], cfg_reg_slice_proc_ctrl[2]};
+	end
+	
+	// 地址建立周期数 - 1
+	// 数据建立周期数 - 1
+	always @(posedge s_axi_clk)
+	begin
+		if(cfg_reg_slice_proc_ctrl[1] & (~axi_addr_regs[1]) & (~axi_rd_reg))
+			# simulation_delay {data_set, addr_set} <= axi_wdata_regs[15:0];
+	end
+	// 数据保持周期数 - 1
+	always @(posedge s_axi_clk)
+	begin
+		if(cfg_reg_slice_proc_ctrl[1] & axi_addr_regs[1] & (~axi_rd_reg))
+			# simulation_delay data_hold <= axi_wdata_regs[23:16];
+	end
+	
+	/** 
+	FSMC存储映射区
+	
+	偏移量0x000_1000~0x3FF_FFFF:
+		子偏移量0x000_0000~0x3FF_EFFF -> FSMC
+	**/
+	reg[2:0] fsmc_proc_ctrl; // 流程独热码
+	// FSMC控制器流程控制
+	wire fsmc_ctrler_start;
+	wire fsmc_ctrler_done;
+	
+	assign axi_trans_done = cfg_reg_slice_proc_ctrl[2] | fsmc_ctrler_done;
+	
+	assign fsmc_ctrler_start = fsmc_proc_ctrl[1];
+	
+	// 流程独热码
+	always @(posedge s_axi_clk or negedge s_axi_resetn)
+	begin
+		if(~s_axi_resetn)
+			fsmc_proc_ctrl <= 3'b001;
+		else if((fsmc_proc_ctrl[0] & (~axi_addr_available) & 
+			(axi_addr_regs[25:12] != 14'd0) & (axi_rd_reg ? 1'b1:(~axi_wdata_available))) | 
+			fsmc_proc_ctrl[1] | 
+			(fsmc_proc_ctrl[2] & fsmc_ctrler_done))
+			# simulation_delay fsmc_proc_ctrl <= {fsmc_proc_ctrl[1:0], fsmc_proc_ctrl[2]};
+	end
+	
+	/** FSMC控制器 **/
+	// 传输参数
+	wire[15:0] wdata; // 写数据
+	wire[1:0] data_mask; // 字节使能掩码
+	wire[25:0] trans_addr; // 传输地址
+	wire is_rd; // 是否读传输
+	
+	assign wdata = axi_addr_regs[1] ? axi_wdata_regs[31:16]:axi_wdata_regs[15:0];
+	assign data_mask = axi_rd_reg ? 2'b00:(axi_addr_regs[1] ? (~axi_wstrb_regs[3:2]):(~axi_wstrb_regs[1:0]));
+	assign trans_addr = axi_addr_regs[25:0] - 32'h0000_1000;
+	assign is_rd = axi_rd_reg;
+	
+	fsmc_ctrler #(
+		.simulation_delay(simulation_delay)
+	)fsmc_ctrler_u(
+		.clk(s_axi_clk),
+		.rst_n(s_axi_resetn),
+		
+		.ctrler_start(fsmc_ctrler_start),
+		.ctrler_idle(),
+		.ctrler_done(fsmc_ctrler_done),
+		
+		.addr_set(addr_set),
+		.data_set(data_set),
+		.data_hold(data_hold),
+		
+		.wdata(wdata),
+		.data_mask(data_mask),
+		.trans_addr(trans_addr),
+		.is_rd(is_rd),
+		
+		.m_axis_rd_data(m_axis_rd_data),
+		.m_axis_rd_valid(m_axis_rd_valid),
+		
+		.fsmc_nbl(fsmc_nbl),
+		.fsmc_addr(fsmc_addr),
+		.fsmc_nwe(fsmc_nwe),
+		.fsmc_noe(fsmc_noe),
+		.fsmc_ne(fsmc_ne),
+		.fsmc_data_i(fsmc_data_i),
+		.fsmc_data_o(fsmc_data_o),
+		.fsmc_data_t(fsmc_data_t)
+	);
+	
+endmodule

CutestPanda_Opensoc/103_generic_fsmc_ctrler/rtl/fsmc_ctrler.v

@@ -0,0 +1,210 @@
+/*
+MIT License
+
+Copyright (c) 2024 Panda, 2257691535@qq.com
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+*/
+
+`timescale 1ns / 1ps
+/********************************************************************
+本模块: FSMC控制器
+
+描述:
+通用FSMC控制器
+
+每次FSMC传输: 地址建立 -> 数据建立 -> 数据保持
+
+注意：
+无
+
+协议:
+AP CTRL
+AXIS MASTER
+FSMC MASTER
+
+作者: 陈家耀
+日期: 2024/07/18
+********************************************************************/
+
+
+module fsmc_ctrler #(
+	parameter real simulation_delay = 0 // 仿真延时
+)(
+	// 时钟和复位
+	input wire clk,
+	input wire rst_n,
+	
+	// 流程控制
+	input wire ctrler_start,
+	output wire ctrler_idle,
+	output wire ctrler_done,
+	
+	// 运行时参数
+	// 断言:运行时参数在控制器开始工作后保持有效值不变!
+	input wire[7:0] addr_set, // 地址建立周期数 - 1
+	input wire[7:0] data_set, // 数据建立周期数 - 1
+	input wire[7:0] data_hold, // 数据保持周期数 - 1
+	
+	// 传输参数
+	input wire[15:0] wdata, // 写数据
+	input wire[1:0] data_mask, // 字节使能掩码
+	input wire[25:0] trans_addr, // 传输地址
+	input wire is_rd, // 是否读传输
+	
+	// 读数据输出
+	output wire[15:0] m_axis_rd_data,
+	output wire m_axis_rd_valid,
+	
+	// FSMC MASTER
+	output wire[1:0] fsmc_nbl, // 数据掩码
+	output wire[25:0] fsmc_addr, // 地址线
+	output wire fsmc_nwe, // 写入使能
+	output wire fsmc_noe, // 输出使能(读使能)
+	output wire fsmc_ne, // 片选信号
+	// 数据线(1'b1 -> 输入, 1'b0 -> 输出)
+	input wire[15:0] fsmc_data_i,
+	output wire[15:0] fsmc_data_o,
+	output wire[15:0] fsmc_data_t
+);
+	
+	/** 锁存的传输信息 **/
+	reg[15:0] wdata_latched; // 锁存的写数据
+	reg[1:0] data_mask_latched; // 锁存的字节使能掩码
+	reg[25:0] trans_addr_latched; // 锁存的传输地址
+	reg is_rd_latched; // 锁存的是否读传输
+	
+	// 锁存的写数据
+	always @(posedge clk)
+	begin
+		if(ctrler_start & ctrler_idle)
+			# simulation_delay wdata_latched <= wdata;
+	end
+	// 锁存的字节使能掩码
+	always @(posedge clk)
+	begin
+		if(ctrler_start & ctrler_idle)
+			# simulation_delay data_mask_latched <= data_mask;
+	end
+	// 锁存的传输地址
+	always @(posedge clk)
+	begin
+		if(ctrler_start & ctrler_idle)
+			# simulation_delay trans_addr_latched <= trans_addr;
+	end
+	// 锁存的是否读传输
+	always @(posedge clk)
+	begin
+		if(ctrler_start & ctrler_idle)
+			# simulation_delay is_rd_latched <= is_rd;
+	end
+	
+	/**
+	流程控制
+	
+	空闲 -> 地址建立 -> 数据建立 -> 数据保持
+	**/
+	reg[3:0] proc_onehot; // 流程独热码
+	reg[7:0] setup_cnt; // 地址/数据建立计数器
+	reg[7:0] hold_cnt; // 数据保持计数器
+	wire addr_set_done; // 地址建立完成指示
+	wire data_set_done; // 数据建立完成指示
+	wire data_hold_done; // 数据保持完成指示
+	
+	assign ctrler_idle = proc_onehot[0];
+	assign ctrler_done = data_hold_done;
+	
+	assign addr_set_done = proc_onehot[1] & (setup_cnt == addr_set);
+	assign data_set_done = proc_onehot[2] & (setup_cnt == data_set);
+	assign data_hold_done = proc_onehot[3] & (hold_cnt == data_hold);
+	
+	// 流程独热码
+	always @(posedge clk or negedge rst_n)
+	begin
+		if(~rst_n)
+			proc_onehot <= 4'b0001;
+		else if((proc_onehot[0] & ctrler_start) | 
+			(proc_onehot[1] & (setup_cnt == addr_set)) | 
+			(proc_onehot[2] & (setup_cnt == data_set)) | 
+			(proc_onehot[3] & (hold_cnt == data_hold)))
+			# simulation_delay proc_onehot <= {proc_onehot[2:0], proc_onehot[3]};
+	end
+	
+	// 地址/数据建立计数器
+	always @(posedge clk or negedge rst_n)
+	begin
+		if(~rst_n)
+			setup_cnt <= 8'd0;
+		else if(proc_onehot[1] | proc_onehot[2])
+			# simulation_delay setup_cnt <= (setup_cnt == (proc_onehot[1] ? addr_set:data_set)) ? 
+				8'd0:(setup_cnt + 8'd1);
+	end
+	
+	// 数据保持计数器
+	always @(posedge clk)
+	begin
+		if(proc_onehot[3])
+			# simulation_delay hold_cnt <= hold_cnt + 8'd1;
+		else
+			# simulation_delay hold_cnt <= 8'd0;
+	end
+	
+	/** FSMC主接口 **/
+	reg fsmc_nwe_reg; // 写入使能
+	reg fsmc_noe_reg; // 输出使能(读使能)
+	reg fsmc_data_t_reg; // 数据三态方向选择
+	
+	assign fsmc_nbl = data_mask_latched;
+	assign fsmc_addr = trans_addr_latched;
+	assign fsmc_nwe = fsmc_nwe_reg;
+	assign fsmc_noe = fsmc_noe_reg;
+	assign fsmc_ne = ctrler_idle;
+	assign fsmc_data_o = wdata_latched;
+	assign fsmc_data_t = {16{fsmc_data_t_reg}};
+	
+	// 写入使能
+	always @(posedge clk or negedge rst_n)
+	begin
+		if(~rst_n)
+			fsmc_nwe_reg <= 1'b1;
+		else if((~is_rd_latched) & (addr_set_done | data_set_done))
+			# simulation_delay fsmc_nwe_reg <= data_set_done;
+	end
+	// 输出使能(读使能)
+	always @(posedge clk or negedge rst_n)
+	begin
+		if(~rst_n)
+			fsmc_noe_reg <= 1'b1;
+		else if(is_rd_latched & (addr_set_done | data_hold_done))
+			# simulation_delay fsmc_noe_reg <= data_hold_done;
+	end
+	// 数据三态方向选择
+	always @(posedge clk or negedge rst_n)
+	begin
+		if(~rst_n)
+			fsmc_data_t_reg <= 1'b1;
+		else if(((~is_rd_latched) & addr_set_done) | data_hold_done)
+			# simulation_delay fsmc_data_t_reg <= data_hold_done;
+	end
+	
+	/** 读数据输出 **/
+	assign m_axis_rd_data = fsmc_data_i;
+	assign m_axis_rd_valid = is_rd_latched & proc_onehot[3] & (hold_cnt == 8'd0);
+	
+endmodule

CutestPanda_Opensoc/103_generic_fsmc_ctrler/rtl/round_robin_arbitrator.v

@@ -0,0 +1,105 @@
+/*
+MIT License
+
+Copyright (c) 2024 Panda, 2257691535@qq.com
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+*/
+
+`timescale 1ns / 1ps
+/********************************************************************
+本模块: Round-Robin仲裁器
+
+描述: 
+基于Round-Robin算法的0时延仲裁器
+
+注意：
+无
+
+协议:
+ARB SLAVE
+
+作者: 陈家耀
+日期: 2024/04/28
+********************************************************************/
+
+
+module round_robin_arbitrator #(
+    parameter integer chn_n = 4, // 通道个数(必须>=2)
+    parameter real simulation_delay = 1 // 仿真延时
+)(
+    // 时钟和复位
+    input wire clk,
+    input wire rst_n,
+    
+    // 仲裁器
+    input wire[chn_n-1:0] req, // 请求
+    output wire[chn_n-1:0] grant, // 授权(独热码)
+    output wire[clogb2(chn_n-1):0] sel, // 选择(相当于授权的二进制表示)
+    output wire arb_valid // 仲裁结果有效
+);
+    
+    // 计算log2(bit_depth)               
+    function integer clogb2 (input integer bit_depth);
+        integer temp;
+    begin
+        temp = bit_depth;
+        for(clogb2 = -1;temp > 0;clogb2 = clogb2 + 1)
+            temp = temp >> 1;
+    end
+    endfunction
+    // 独热码 -> 二进制码
+    function [clogb2(chn_n-1):0] onehot_to_bin(input[chn_n-1:0] onehot);
+        integer i;
+    begin
+        onehot_to_bin = 0;
+        
+        for(i = 0;i < chn_n;i = i + 1)
+        begin
+            if(onehot[i])
+                onehot_to_bin = i;
+        end
+    end
+    endfunction
+
+    /** 仲裁优先级 **/
+    reg[chn_n-1:0] priority_cnt; // 优先级独热码计数器
+    
+    // 优先级独热码计数器
+    // 1的位置表征最高优先级的通道
+    always @(posedge clk or negedge rst_n)
+    begin
+        if(~rst_n)
+            priority_cnt <= {{(chn_n-1){1'b0}}, 1'b1};
+        else if(|req) // 当前有请求
+            # simulation_delay priority_cnt <= {grant[chn_n-2:0], grant[chn_n-1]};
+    end
+    
+    /** 仲裁授权与选择 **/
+    wire[chn_n*2-1:0] double_req;
+    wire[chn_n*2-1:0] double_grant;
+    
+    assign double_req = {req, req};
+    assign double_grant = double_req & (~(double_req - priority_cnt));
+    
+    assign grant = double_grant[chn_n-1:0] | double_grant[chn_n*2-1:chn_n];
+    assign sel = onehot_to_bin(grant);
+    assign arb_valid = |req;
+    
+endmodule

CutestPanda_Opensoc/103_generic_fsmc_ctrler/tb/axi_fsmc/agents.sv

@@ -0,0 +1,413 @@
+/*
+MIT License
+
+Copyright (c) 2024 Panda, 2257691535@qq.com
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
+*/
+
+`timescale 1ns / 1ps
+
+`ifndef __AGENT_H
+
+`define __AGENT_H
+
+// `define BlkCtrlMstAgt
+`define AXIMstAgt
+// `define AXISlvAgt
+// `define AXISMstAgt
+// `define AXISSlvAgt
+// `define APBSlvAgt
+// `define AHBMstAgt
+
+`include "transactions.sv"
+`include "sequencers.sv"
+`include "drivers.sv"
+`include "monitors.sv"
+
+/** 代理:块级控制主机 **/
+`ifdef BlkCtrlMstAgt
+class BlkCtrlMasterAgent #(
+	real out_drive_t = 1 // 输出驱动延迟量
+)extends uvm_agent;
+	
+	// 组件
+	local BlkCtrlSeqr sequencer; // 序列发生器
+	local BlkCtrlMasterDriver #(.out_drive_t(out_drive_t)) driver; // 驱动器
+	
+	// 注册component
+	`uvm_component_param_utils(BlkCtrlMasterAgent #(.out_drive_t(out_drive_t)))
+	
+	function new(string name = "BlkCtrlMasterAgent", uvm_component parent = null);
+		super.new(name, parent);
+	endfunction
+	
+	virtual function void build_phase(uvm_phase phase);
+		super.build_phase(phase);
+		
+		this.sequencer = BlkCtrlSeqr::type_id::create("sqr", this); // 创建sequencer
+		this.driver = BlkCtrlMasterDriver #(.out_drive_t(out_drive_t))::type_id::create("drv", this); // 创建driver
+		
+		`uvm_info("BlkCtrlMasterAgent", "BlkCtrlMasterAgent built!", UVM_LOW)
+	endfunction
+	
+	virtual function void connect_phase(uvm_phase phase);
+		super.connect_phase(phase);
+		
+		this.driver.seq_item_port.connect(this.sequencer.seq_item_export); // 连接sequence-port
+	endfunction
+	
+endclass
+`endif
+
+/** 代理:AXI主机 **/
+`ifdef AXIMstAgt
+class AXIMasterAgent #(
+	real out_drive_t = 1, // 输出驱动延迟量
+	integer addr_width = 32, // 地址位宽(1~64)
+	integer data_width = 32, // 数据位宽(8 | 16 | 32 | 64 | 128 | 256 | 512 | 1024)
+    integer bresp_width = 2, // 写响应信号位宽(0 | 2 | 3)
+    integer rresp_width = 2 // 读响应信号位宽(0 | 2 | 3)
+)extends uvm_agent;
+	
+	// 组件
+	local AXISequencer #(.addr_width(addr_width), .data_width(data_width), 
+		.bresp_width(bresp_width), .rresp_width(rresp_width)) sequencer; // 序列发生器
+	local AXIMasterDriver #(.out_drive_t(out_drive_t), .addr_width(addr_width), .data_width(data_width), 
+		.bresp_width(bresp_width), .rresp_width(rresp_width)) driver; // 驱动器
+	local AXIMonitor #(.out_drive_t(out_drive_t), .addr_width(addr_width), .data_width(data_width), 
+		.bresp_width(bresp_width), .rresp_width(rresp_width)) monitor; // 监测器
+	
+	// 通信端口
+	uvm_analysis_port #(AXITrans #(.addr_width(addr_width), .data_width(data_width), 
+		.bresp_width(bresp_width), .rresp_width(rresp_width))) rd_trans_analysis_port;
+	uvm_analysis_port #(AXITrans #(.addr_width(addr_width), .data_width(data_width), 
+		.bresp_width(bresp_width), .rresp_width(rresp_width))) wt_trans_analysis_port;
+	
+	// 注册component
+	`uvm_component_param_utils(AXIMasterAgent #(.out_drive_t(out_drive_t), .addr_width(addr_width), .data_width(data_width), .bresp_width(bresp_width), .rresp_width(rresp_width)))
+	
+	function new(string name = "AXIMasterAgent", uvm_component parent = null);
+		super.new(name, parent);
+	endfunction
+	
+	virtual function void build_phase(uvm_phase phase);
+		super.build_phase(phase);
+		
+		if (this.is_active == UVM_ACTIVE)
+		begin
+		  this.sequencer = AXISequencer #(.addr_width(addr_width), .data_width(data_width), 
+			.bresp_width(bresp_width), .rresp_width(rresp_width))::type_id::create("sqr", this); // 创建sequencer
+		  this.driver = AXIMasterDriver #(.out_drive_t(out_drive_t), .addr_width(addr_width), .data_width(data_width), 
+			.bresp_width(bresp_width), .rresp_width(rresp_width))::type_id::create("drv", this); // 创建driver
+		end
+		
+		this.monitor = AXIMonitor #(.out_drive_t(out_drive_t), .addr_width(addr_width), .data_width(data_width), 
+			.bresp_width(bresp_width), .rresp_width(rresp_width))::type_id::create("mon", this); // 创建monitor
+		
+		`uvm_info("AXIMasterAgent", "AXIMasterAgent built!", UVM_LOW)
+	endfunction
+	
+	virtual function void connect_phase(uvm_phase phase);
+		super.connect_phase(phase);
+		
+		if(this.is_active == UVM_ACTIVE)
+			this.driver.seq_item_port.connect(this.sequencer.seq_item_export); // 连接sequence-port
+		
+		this.rd_trans_analysis_port = this.monitor.rd_trans_analysis_port;
+		this.wt_trans_analysis_port = this.monitor.wt_trans_analysis_port;
+	endfunction
+	
+endclass
+`endif
+
+/** 代理:AXI从机 **/
+`ifdef AXISlvAgt
+class AXISlaveAgent #(
+	real out_drive_t = 1, // 输出驱动延迟量
+	integer addr_width = 32, // 地址位宽(1~64)
+	integer data_width = 32, // 数据位宽(8 | 16 | 32 | 64 | 128 | 256 | 512 | 1024)
+    integer bresp_width = 2, // 写响应信号位宽(0 | 2 | 3)
+    integer rresp_width = 2 // 读响应信号位宽(0 | 2 | 3)
+)extends uvm_agent;
+	
+	// 组件
+	local AXISequencer #(.addr_width(addr_width), .data_width(data_width), 
+		.bresp_width(bresp_width), .rresp_width(rresp_width)) sequencer; // 序列发生器
+	local AXISlaveDriver #(.out_drive_t(out_drive_t), .addr_width(addr_width), .data_width(data_width), 
+		.bresp_width(bresp_width), .rresp_width(rresp_width)) driver; // 驱动器
+	local AXIMonitor #(.out_drive_t(out_drive_t), .addr_width(addr_width), .data_width(data_width), 
+		.bresp_width(bresp_width), .rresp_width(rresp_width)) monitor; // 监测器
+	
+	// 通信端口
+	uvm_analysis_port #(AXITrans #(.addr_width(addr_width), .data_width(data_width), 
+		.bresp_width(bresp_width), .rresp_width(rresp_width))) rd_trans_analysis_port;
+	uvm_analysis_port #(AXITrans #(.addr_width(addr_width), .data_width(data_width), 
+		.bresp_width(bresp_width), .rresp_width(rresp_width))) wt_trans_analysis_port;
+	
+	// 注册component
+	`uvm_component_param_utils(AXISlaveAgent #(.out_drive_t(out_drive_t), .addr_width(addr_width), .data_width(data_width), .bresp_width(bresp_width), .rresp_width(rresp_width)))
+	
+	function new(string name = "AXISlaveAgent", uvm_component parent = null);
+		super.new(name, parent);
+	endfunction
+	
+	virtual function void build_phase(uvm_phase phase);
+		super.build_phase(phase);
+		
+		if (this.is_active == UVM_ACTIVE)
+		begin
+		  this.sequencer = AXISequencer #(.addr_width(addr_width), .data_width(data_width), 
+			.bresp_width(bresp_width), .rresp_width(rresp_width))::type_id::create("sqr", this); // 创建sequencer
+		  this.driver = AXISlaveDriver #(.out_drive_t(out_drive_t), .addr_width(addr_width), .data_width(data_width), 
+			.bresp_width(bresp_width), .rresp_width(rresp_width))::type_id::create("drv", this); // 创建driver
+		end
+		
+		this.monitor = AXIMonitor #(.out_drive_t(out_drive_t), .addr_width(addr_width), .data_width(data_width), 
+			.bresp_width(bresp_width), .rresp_width(rresp_width))::type_id::create("mon", this); // 创建monitor
+		
+		`uvm_info("AXISlaveAgent", "AXISlaveAgent built!", UVM_LOW)
+	endfunction
+	
+	virtual function void connect_phase(uvm_phase phase);
+		super.connect_phase(phase);
+		
+		if(this.is_active == UVM_ACTIVE)
+			this.driver.seq_item_port.connect(this.sequencer.seq_item_export); // 连接sequence-port
+		
+		this.rd_trans_analysis_port = this.monitor.rd_trans_analysis_port;
+		this.wt_trans_analysis_port = this.monitor.wt_trans_analysis_port;
+	endfunction
+	
+endclass
+`endif
+
+/** 代理:AXIS主机 **/
+`ifdef AXISMstAgt
+class AXISMasterAgent #(
+	real out_drive_t = 1, // 输出驱动延迟量
+    integer data_width = 32, // 数据位宽(必须能被8整除)
+    integer user_width = 0 // 用户数据位宽
+)extends uvm_agent;
+	
+	// 组件
+	local AXISSequencer #(.data_width(data_width), .user_width(user_width)) sequencer; // 序列发生器
+	local AXISMasterDriver #(.out_drive_t(out_drive_t), .data_width(data_width), .user_width(user_width)) driver; // 驱动器
+	local AXISMonitor #(.out_drive_t(out_drive_t), .data_width(data_width), .user_width(user_width)) monitor; // 监测器
+	
+	// 通信端口
+	uvm_analysis_port #(AXISTrans #(.data_width(data_width), .user_width(user_width))) axis_analysis_port;
+	
+	// 注册component
+	`uvm_component_param_utils(AXISMasterAgent #(.out_drive_t(out_drive_t), .data_width(data_width), .user_width(user_width)))
+	
+	function new(string name = "AXISMasterAgent", uvm_component parent = null);
+		super.new(name, parent);
+	endfunction
+	
+	virtual function void build_phase(uvm_phase phase);
+		super.build_phase(phase);
+		
+		if (this.is_active == UVM_ACTIVE)
+		begin
+		  this.sequencer = AXISSequencer #(.data_width(data_width), .user_width(user_width))::
+			type_id::create("sqr", this); // 创建sequencer
+		  this.driver = AXISMasterDriver #(.out_drive_t(out_drive_t), .data_width(data_width), .user_width(user_width))::
+			type_id::create("drv", this); // 创建driver
+		end
+		
+		this.monitor = AXISMonitor #(.out_drive_t(out_drive_t), .data_width(data_width), .user_width(user_width))::
+			type_id::create("mon", this); // 创建monitor
+		
+		`uvm_info("AXISMasterAgent", "AXISMasterAgent built!", UVM_LOW)
+	endfunction
+	
+	virtual function void connect_phase(uvm_phase phase);
+		super.connect_phase(phase);
+		
+		if(this.is_active == UVM_ACTIVE)
+			this.driver.seq_item_port.connect(this.sequencer.seq_item_export); // 连接sequence-port
+		
+		this.axis_analysis_port = this.monitor.in_analysis_port;
+	endfunction
+	
+endclass
+`endif
+
+/** 代理:AXIS从机 **/
+`ifdef AXISSlvAgt
+class AXISSlaveAgent #(
+	real out_drive_t = 1, // 输出驱动延迟量
+    integer data_width = 32, // 数据位宽(必须能被8整除)
+    integer user_width = 0 // 用户数据位宽
+)extends uvm_agent;
+	
+	// 组件
+	local AXISSlaveDriver #(.out_drive_t(out_drive_t), .data_width(data_width), .user_width(user_width)) driver; // 驱动器
+	local AXISMonitor #(.out_drive_t(out_drive_t), .data_width(data_width), .user_width(user_width)) monitor; // 监测器
+	
+	// 通信端口
+	uvm_analysis_port #(AXISTrans #(.data_width(data_width), .user_width(user_width))) axis_analysis_port;
+	
+	// 注册component
+	`uvm_component_param_utils(AXISSlaveAgent #(.out_drive_t(out_drive_t), .data_width(data_width), .user_width(user_width)))
+	
+	function new(string name = "AXISSlaveAgent", uvm_component parent = null);
+		super.new(name, parent);
+	endfunction
+	
+	virtual function void build_phase(uvm_phase phase);
+		super.build_phase(phase);
+		
+		if (this.is_active == UVM_ACTIVE)
+		begin
+		  this.driver = AXISSlaveDriver #(.out_drive_t(out_drive_t), .data_width(data_width), .user_width(user_width))::
+			type_id::create("drv", this); // 创建driver
+		end
+		
+		this.monitor = AXISMonitor #(.out_drive_t(out_drive_t), .data_width(data_width), .user_width(user_width))::
+			type_id::create("mon", this); // 创建monitor
+		
+		`uvm_info("AXISSlaveAgent", "AXISSlaveAgent built!", UVM_LOW)
+	endfunction
+	
+	virtual function void connect_phase(uvm_phase phase);
+		super.connect_phase(phase);
+		
+		this.axis_analysis_port = this.monitor.in_analysis_port;
+	endfunction
+	
+endclass
+`endif
+
+/** 代理:APB从机 **/
+`ifdef APBSlvAgt
+class APBSlaveAgent #(
+	real out_drive_t = 1, // 输出驱动延迟量
+    integer addr_width = 32, // 地址位宽(1~32)
+    integer data_width = 32 // 数据位宽(8 | 16 | 32)
+)extends uvm_agent;
+	
+	// 组件
+	local APBSequencer #(.addr_width(addr_width), .data_width(data_width)) sequencer; // 序列发生器
+	local APBSlaveDriver #(.out_drive_t(out_drive_t), .addr_width(addr_width), .data_width(data_width)) driver; // 驱动器
+	local APBMonitor #(.out_drive_t(out_drive_t), .addr_width(addr_width), .data_width(data_width)) monitor; // 监测器
+	
+	// 通信端口
+	uvm_analysis_port #(APBTrans #(.addr_width(addr_width), .data_width(data_width))) apb_analysis_port;
+	
+	// 注册component
+	`uvm_component_param_utils(APBSlaveAgent #(.out_drive_t(out_drive_t), .addr_width(addr_width), .data_width(data_width)))
+	
+	function new(string name = "APBSlaveAgent", uvm_component parent = null);
+		super.new(name, parent);
+	endfunction
+	
+	virtual function void build_phase(uvm_phase phase);
+		super.build_phase(phase);
+		
+		if (this.is_active == UVM_ACTIVE)
+		begin
+		  this.sequencer = APBSequencer #(.addr_width(addr_width), .data_width(data_width))::
+			type_id::create("sqr", this); // 创建sequencer
+		  this.driver = APBSlaveDriver #(.out_drive_t(out_drive_t), .addr_width(addr_width), .data_width(data_width))::
+			type_id::create("drv", this); // 创建driver
+		end
+		
+		this.monitor = APBMonitor #(.out_drive_t(out_drive_t), .addr_width(addr_width), .data_width(data_width))::
+			type_id::create("mon", this); // 创建monitor
+		
+		`uvm_info("APBSlaveAgent", "APBSlaveAgent built!", UVM_LOW)
+	endfunction
+	
+	virtual function void connect_phase(uvm_phase phase);
+		super.connect_phase(phase);
+		
+		if(this.is_active == UVM_ACTIVE)
+			this.driver.seq_item_port.connect(this.sequencer.seq_item_export); // 连接sequence-port
+		
+		this.apb_analysis_port = this.monitor.in_analysis_port;
+	endfunction
+	
+endclass
+`endif
+
+/** 代理:AHB主机 **/
+`ifdef AHBMstAgt
+class AHBMasterAgent #(
+	real out_drive_t = 1, // 输出驱动延迟量
+    integer slave_n = 1, // 从机个数
+    integer addr_width = 32, // 地址位宽(10~64)
+    integer data_width = 32, // 数据位宽(8 | 16 | 32 | 64 | 128 | 256 | 512 | 1024)
+    integer burst_width = 3, // 突发类型位宽(0~3)
+    integer prot_width = 4, // 保护类型位宽(0 | 4 | 7)
+    integer master_width = 1 // 主机标识位宽(0~8)
+)extends uvm_agent;
+	
+	// 组件
+	local AHBSequencer #(.addr_width(addr_width), .data_width(data_width), .burst_width(burst_width), 
+		.prot_width(prot_width), .master_width(master_width)) sequencer; // 序列发生器
+	local AHBMasterDriver #(.out_drive_t(out_drive_t), .slave_n(slave_n), .addr_width(addr_width), .data_width(data_width), 
+		.burst_width(burst_width), .prot_width(prot_width), .master_width(master_width)) driver; // 驱动器
+	local AHBMonitor #(.out_drive_t(out_drive_t), .slave_n(slave_n), .addr_width(addr_width), .data_width(data_width), 
+		.burst_width(burst_width), .prot_width(prot_width), .master_width(master_width)) monitor; // 监测器
+	
+	// 通信端口
+	uvm_analysis_port #(AHBTrans #(.addr_width(addr_width), .data_width(data_width), 
+		.burst_width(burst_width), .prot_width(prot_width), .master_width(master_width))) ahb_analysis_port;
+	
+	// 注册component
+	`uvm_component_param_utils(AHBMasterAgent #(.out_drive_t(out_drive_t), .slave_n(slave_n), .addr_width(addr_width), .data_width(data_width), .burst_width(burst_width), .prot_width(prot_width), .master_width(master_width)))
+	
+	function new(string name = "AHBMasterAgent", uvm_component parent = null);
+		super.new(name, parent);
+	endfunction
+	
+	virtual function void build_phase(uvm_phase phase);
+		super.build_phase(phase);
+		
+		if (this.is_active == UVM_ACTIVE)
+		begin
+		  this.sequencer = AHBSequencer #(.addr_width(addr_width), .data_width(data_width), .burst_width(burst_width), 
+			.prot_width(prot_width), .master_width(master_width))::type_id::create("sqr", this); // 创建sequencer
+		  this.driver = AHBMasterDriver #(.out_drive_t(out_drive_t), .slave_n(slave_n), .addr_width(addr_width), 
+			.data_width(data_width), .burst_width(burst_width), .prot_width(prot_width), 
+			.master_width(master_width))::type_id::create("drv", this); // 创建driver
+		end
+		
+		this.monitor = AHBMonitor #(.out_drive_t(out_drive_t), .slave_n(slave_n), .addr_width(addr_width), 
+			.data_width(data_width), .burst_width(burst_width), .prot_width(prot_width), .master_width(master_width))::
+			type_id::create("mon", this); // 创建monitor
+		
+		`uvm_info("AHBMasterAgent", "AHBMasterAgent built!", UVM_LOW)
+	endfunction
+	
+	virtual function void connect_phase(uvm_phase phase);
+		super.connect_phase(phase);
+		
+		if(this.is_active == UVM_ACTIVE)
+			this.driver.seq_item_port.connect(this.sequencer.seq_item_export); // 连接sequence-port
+		
+		this.ahb_analysis_port = this.monitor.in_analysis_port;
+	endfunction
+	
+endclass
+`endif
+
+`endif