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Datasets:
SAIFIINDUSTRIES
/
verilog_data-2
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0
Dataset card
Files
Files and versions
xet
Community
35f18cd
verilog_data-2
/
CutestPanda_Opensoc
/
109_axi_sdram
/
rtl
227 kB
1 contributor
History:
1 commit
SAIFIINDUSTRIES
Add Batch 2 with 10 repos
0693bdd
verified
7 days ago
axi_sdram.v
Safe
11.4 kB
Add Batch 2 with 10 repos
7 days ago
axis_reg_slice.v
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5.09 kB
Add Batch 2 with 10 repos
7 days ago
axis_reg_slice_core.v
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6.59 kB
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7 days ago
axis_sdram_cmd_agent.v
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34.6 kB
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7 days ago
bram_simple_dual_port.v
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4.07 kB
Add Batch 2 with 10 repos
7 days ago
cool_down_cnt.v
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3.42 kB
Add Batch 2 with 10 repos
7 days ago
dram_simple_dual_port.v
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3.98 kB
Add Batch 2 with 10 repos
7 days ago
fifo_based_on_regs.v
Safe
8.65 kB
Add Batch 2 with 10 repos
7 days ago
ram_based_shift_regs.v
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5.76 kB
Add Batch 2 with 10 repos
7 days ago
round_robin_arbitrator.v
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2.21 kB
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7 days ago
s_axi_if_for_axi_sdram.v
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21.1 kB
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7 days ago
sdram_active_precharge_insert.v
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9.86 kB
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7 days ago
sdram_auto_refresh.v
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32.6 kB
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7 days ago
sdram_data_agent.v
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23.8 kB
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7 days ago
sdram_data_buffer.v
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16.2 kB
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7 days ago
sdram_init_cmd_gen.v
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6.57 kB
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7 days ago
sdram_phy.v
Safe
25.5 kB
Add Batch 2 with 10 repos
7 days ago
sdram_rfs_monitor.v
Safe
5.64 kB
Add Batch 2 with 10 repos
7 days ago
