Add Repo: Misaka-N_TJCS-SingleCircleCPU31

Misaka-N_TJCS-SingleCircleCPU31/Behavior Simulation/test_tb.v

@@ -0,0 +1,103 @@
+`timescale 1ns / 1ps
+module cpu_tb;
+reg clk;            //时钟信号
+reg rst;            //复位信号
+wire [31:0] inst;   //要执行的指令
+wire [31:0] pc;     //下一条指令的地址
+reg  [31:0] cnt;    //计数器，已经执行了几条指令
+integer file_open;
+
+initial 
+begin
+    clk = 1'b0;
+    rst = 1'b1;
+    #50 rst = 1'b0;
+    cnt = 0;
+end
+
+always  #50 clk = ~clk;
+
+always @ (posedge clk) begin
+    cnt <= cnt + 1'b1;
+    file_open = $fopen("C:\\Users\\Lenovo\\Desktop\\Project\\SingleCPU31\\output.txt", "a+");
+    $fdisplay(file_open, "OP: %d", cnt);
+    $fdisplay(file_open, "Instr_addr = %h", sc_inst.inst);
+    $fdisplay(file_open, "$zero = %h", sc_inst.sccpu.cpu_ref.array_reg[0]);
+    $fdisplay(file_open, "$at   = %h", sc_inst.sccpu.cpu_ref.array_reg[1]);
+    $fdisplay(file_open, "$v0   = %h", sc_inst.sccpu.cpu_ref.array_reg[2]);
+    $fdisplay(file_open, "$v1   = %h", sc_inst.sccpu.cpu_ref.array_reg[3]);
+    $fdisplay(file_open, "$a0   = %h", sc_inst.sccpu.cpu_ref.array_reg[4]);
+    $fdisplay(file_open, "$a1   = %h", sc_inst.sccpu.cpu_ref.array_reg[5]);
+    $fdisplay(file_open, "$a2   = %h", sc_inst.sccpu.cpu_ref.array_reg[6]);
+    $fdisplay(file_open, "$a3   = %h", sc_inst.sccpu.cpu_ref.array_reg[7]);
+    $fdisplay(file_open, "$t0   = %h", sc_inst.sccpu.cpu_ref.array_reg[8]);
+    $fdisplay(file_open, "$t1   = %h", sc_inst.sccpu.cpu_ref.array_reg[9]);
+    $fdisplay(file_open, "$t2   = %h", sc_inst.sccpu.cpu_ref.array_reg[10]);
+    $fdisplay(file_open, "$t3   = %h", sc_inst.sccpu.cpu_ref.array_reg[11]);
+    $fdisplay(file_open, "$t4   = %h", sc_inst.sccpu.cpu_ref.array_reg[12]);
+    $fdisplay(file_open, "$t5   = %h", sc_inst.sccpu.cpu_ref.array_reg[13]);
+    $fdisplay(file_open, "$t6   = %h", sc_inst.sccpu.cpu_ref.array_reg[14]);
+    $fdisplay(file_open, "$t7   = %h", sc_inst.sccpu.cpu_ref.array_reg[15]);
+    $fdisplay(file_open, "$s0   = %h", sc_inst.sccpu.cpu_ref.array_reg[16]);
+    $fdisplay(file_open, "$s1   = %h", sc_inst.sccpu.cpu_ref.array_reg[17]);
+    $fdisplay(file_open, "$s2   = %h", sc_inst.sccpu.cpu_ref.array_reg[18]);
+    $fdisplay(file_open, "$s3   = %h", sc_inst.sccpu.cpu_ref.array_reg[19]);
+    $fdisplay(file_open, "$s4   = %h", sc_inst.sccpu.cpu_ref.array_reg[20]);
+    $fdisplay(file_open, "$s5   = %h", sc_inst.sccpu.cpu_ref.array_reg[21]);
+    $fdisplay(file_open, "$s6   = %h", sc_inst.sccpu.cpu_ref.array_reg[22]);
+    $fdisplay(file_open, "$s7   = %h", sc_inst.sccpu.cpu_ref.array_reg[23]);
+    $fdisplay(file_open, "$t8   = %h", sc_inst.sccpu.cpu_ref.array_reg[24]);
+    $fdisplay(file_open, "$t9   = %h", sc_inst.sccpu.cpu_ref.array_reg[25]);
+    $fdisplay(file_open, "$k0   = %h", sc_inst.sccpu.cpu_ref.array_reg[26]);
+    $fdisplay(file_open, "$k1   = %h", sc_inst.sccpu.cpu_ref.array_reg[27]);
+    $fdisplay(file_open, "$gp   = %h", sc_inst.sccpu.cpu_ref.array_reg[28]);
+    $fdisplay(file_open, "$sp   = %h", sc_inst.sccpu.cpu_ref.array_reg[29]);
+    $fdisplay(file_open, "$fp   = %h", sc_inst.sccpu.cpu_ref.array_reg[30]);
+    $fdisplay(file_open, "$ra   = %h", sc_inst.sccpu.cpu_ref.array_reg[31]);
+//    $fdisplay(file_open, "dmem_addr = %h", sc_inst.dmem.dm_addr);
+//    $fdisplay(file_open, "dm_data_in = %h", sc_inst.dmem.dm_data_in);
+//    $fdisplay(file_open, "dm_data_out = %h", sc_inst.dmem.dm_data_out);
+//    $fdisplay(file_open, "$dmem0 = %h", sc_inst.dmem.dmem[0]);
+//    $fdisplay(file_open, "$dmem1 = %h", sc_inst.dmem.dmem[1]);
+//    $fdisplay(file_open, "$dmem2 = %h", sc_inst.dmem.dmem[2]);
+//    $fdisplay(file_open, "$dmem3 = %h", sc_inst.dmem.dmem[3]);
+//    $fdisplay(file_open, "$dmem4 = %h", sc_inst.dmem.dmem[4]);
+//    $fdisplay(file_open, "$dmem5 = %h", sc_inst.dmem.dmem[5]);
+//    $fdisplay(file_open, "$dmem6 = %h", sc_inst.dmem.dmem[6]);
+//    $fdisplay(file_open, "$dmem7 = %h", sc_inst.dmem.dmem[7]);
+//    $fdisplay(file_open, "$dmem8 = %h", sc_inst.dmem.dmem[8]);
+//    $fdisplay(file_open, "$dmem9 = %h", sc_inst.dmem.dmem[9]);
+//    $fdisplay(file_open, "$dmem10 = %h", sc_inst.dmem.dmem[10]);
+//    $fdisplay(file_open, "$dmem11 = %h", sc_inst.dmem.dmem[11]);
+//    $fdisplay(file_open, "$dmem12 = %h", sc_inst.dmem.dmem[12]);
+//    $fdisplay(file_open, "$dmem13 = %h", sc_inst.dmem.dmem[13]);
+//    $fdisplay(file_open, "$dmem14 = %h", sc_inst.dmem.dmem[14]);                                                          
+//    $fdisplay(file_open, "$dmem15 = %h", sc_inst.dmem.dmem[15]);
+//    $fdisplay(file_open, "$dmem16 = %h", sc_inst.dmem.dmem[16]);
+//    $fdisplay(file_open, "$dmem17 = %h", sc_inst.dmem.dmem[17]);
+//    $fdisplay(file_open, "$dmem18 = %h", sc_inst.dmem.dmem[18]);
+//    $fdisplay(file_open, "$dmem19 = %h", sc_inst.dmem.dmem[19]);
+//    $fdisplay(file_open, "$dmem20 = %h", sc_inst.dmem.dmem[20]);
+//    $fdisplay(file_open, "$dmem21 = %h", sc_inst.dmem.dmem[21]);
+//    $fdisplay(file_open, "$dmem22 = %h", sc_inst.dmem.dmem[22]);
+//    $fdisplay(file_open, "$dmem23 = %h", sc_inst.dmem.dmem[23]);                                                          
+//    $fdisplay(file_open, "$dmem24 = %h", sc_inst.dmem.dmem[24]);
+//    $fdisplay(file_open, "$dmem25 = %h", sc_inst.dmem.dmem[25]);
+//    $fdisplay(file_open, "$dmem26 = %h", sc_inst.dmem.dmem[26]);
+//    $fdisplay(file_open, "$dmem27 = %h", sc_inst.dmem.dmem[27]);
+//    $fdisplay(file_open, "$dmem28 = %h", sc_inst.dmem.dmem[28]);
+//    $fdisplay(file_open, "$dmem29 = %h", sc_inst.dmem.dmem[29]);
+//    $fdisplay(file_open, "$dmem30 = %h", sc_inst.dmem.dmem[30]);
+//    $fdisplay(file_open, "$dmem31 = %h", sc_inst.dmem.dmem[31]);
+    $fdisplay(file_open, "$pc   = %h\n", sc_inst.pc);
+    $fclose(file_open);
+end
+
+sccomp_dataflow sc_inst(
+    .clk_in(clk),
+    .reset(rst),
+    .inst(inst),
+    .pc(pc)
+);
+
+endmodule

Misaka-N_TJCS-SingleCircleCPU31/Post-Synthesis Timing Simulation/simulation/test_tb.v

@@ -0,0 +1,31 @@
+`timescale 1ns / 1ps
+module cpu_tb;
+reg clk;            //ʱ���ź�
+reg rst;            //��λ�ź�
+wire [31:0] inst;   //Ҫִ�е�ָ��
+wire [31:0] pc;     //��һ��ָ��ĵ�ַ
+wire [7:0]  o_seg;  //�������
+wire [7:0]  o_sel;  //Ƭѡ�ź�
+wire clk_cpu;
+//integer file_open;
+
+initial 
+begin
+    clk = 1'b0;
+    rst = 1'b1;
+    #50 rst = 1'b0;
+end
+
+always  #50 clk = ~clk;
+
+sccomp_dataflow sc_inst(
+    .clk_in(clk),
+    .reset(rst),
+    .clk_cpu(clk_cpu),
+    .inst(inst), //���ָ��
+    .pc(pc),   //ִ�е�ַ
+    .o_seg(o_seg),//�������
+    .o_sel(o_sel) //Ƭѡ�ź�
+);
+
+endmodule

Misaka-N_TJCS-SingleCircleCPU31/Post-Synthesis Timing Simulation/sources/Divider.v

@@ -0,0 +1,25 @@
+`timescale 1ns / 1ps
+module Divider(clk,rst_n,clk_out);
+/* ģ������������� */
+input clk;                //ϵͳʱ��
+input rst_n;              //��λ�ź�,�͵�ƽ��Ч
+output reg clk_out;       //�������CPU��ʱ��
+/* ģ���м���� */
+reg [31:0] count3=32'd0; //50,000,000��Ƶ
+//50,000,000��Ƶ
+always @(posedge clk) 
+begin 
+    if(!rst_n)
+    begin
+      count3 <= 1'b0;
+      clk_out <= 0;  
+    end
+    else if(count3 == 32'd50000000) 
+    begin 
+        count3 <= 32'd0; 
+        clk_out <= ~clk_out; 
+    end 
+    else
+        count3 <= count3+1'b1; 
+end
+endmodule

Misaka-N_TJCS-SingleCircleCPU31/Post-Synthesis Timing Simulation/sources/sccomp_dataflow.v

@@ -0,0 +1,81 @@
+`timescale 1ns / 1ps
+module sccomp_dataflow(
+    input clk_in,       //ʱ���ź�
+    input reset,        //��λ�ź�
+    output [7:0]  o_seg,//�������
+    output [7:0]  o_sel //Ƭѡ�ź�
+    );
+
+/* CPU�� */
+wire [31:0] pc_out;          //���ָ���ַ������IMEMҪȡ����
+wire [31:0] dm_addr_temp;    //DMEM��ʱ��ַ����Ҫת��
+
+
+/* IMEM�� */
+wire [31:0] im_addr_in;     //11λָ�����ַ����IMEM�ж�ָ��
+wire [31:0] im_instr_out;   //32λָ����
+
+assign im_addr_in = pc_out - 32'h00400000;
+
+/* DMEM�� */
+wire dm_ena;                //�Ƿ���Ҫ����DMEM
+wire dm_r, dm_w;            //��дָ��
+wire [31:0] dm_addr;        //��Ҫ�õ���DMEM��ַ
+wire [31:0] dm_data_out;    //DMEM��ȡʱ��ȡ��������
+wire [31:0] dm_data_w;      //Ҫд��DMEM������ 
+
+assign dm_addr = (dm_addr_temp -  32'h10010000)/4;
+
+/* ����� */
+assign pc = pc_out;
+assign inst = im_instr_out;
+
+
+/* IMEMָ��洢������ */
+IMEM imem(
+    .im_addr_in(im_addr_in[12:2]),  //11λָ�����ַ����IMEM�ж�ָ��
+    .im_instr_out(im_instr_out)     //32λָ����
+    );
+
+/* DMEM���ݴ洢������ */
+DMEM dmem(                      //DMEM�������ܿ�������Ƴ��첽��ȡ���ݣ�ͬ��д�����ݵ���ʽ
+    .dm_clk(clk_cpu),            //DMEMʱ���źţ�ֻ��д����ʱʹ��
+    .dm_ena(dm_ena),            //ʹ���źŶˣ��ߵ�ƽ��Ч����Чʱ���ܶ�ȡ/д������
+    .dm_r(dm_r),                //read���źţ���ȡʱ����
+    .dm_w(dm_w),                //writeд�źţ�д��ʱ����
+    .dm_addr(dm_addr[10:0]),    //11λ��ַ��Ҫ��ȡ/д��ĵ�ַ
+    .dm_data_in(dm_data_w),     //д��ʱҪд�������
+    .dm_data_out(dm_data_out)   //��ȡʱ��ȡ��������
+    );
+
+/* CPU���� */
+cpu sccpu(
+    .clk(clk_cpu),               //CPUִ��ʱ��
+    .ena(1'b1),                 //ʹ���źŶ�
+    .rst_n(reset),              //��λ�ź�
+    .instr_in(im_instr_out),    //��ǰҪִ�е�ָ��
+    .dm_data(dm_data_out),      //��ȡ����DMEM�ľ�������
+    .dm_ena(dm_ena),            //�Ƿ���Ҫ����DMEM
+    .dm_w(dm_w),                //�������DMEM���Ƿ�Ϊд��
+    .dm_r(dm_r),                //�������DMEM���Ƿ�Ϊ��ȡ
+    .pc_out(pc_out),            //���ָ���ַ������IMEMҪȡ����
+    .dm_addr(dm_addr_temp),     //��Ҫ�õ���DMEM��ַ
+    .dm_data_w(dm_data_w)       //Ҫд��DMEM������ 
+    );
+
+seg7x16 seg7x16_inst(
+    .clk(clk_in),
+	.reset(reset),
+	.cs(1'b1),
+	.i_data(im_instr_out),
+	.o_seg(o_seg),
+	.o_sel(o_sel)
+    );
+
+Divider Divider_inst(
+    .clk(clk_in),                   //ϵͳʱ��
+    .rst_n(~reset),                 //��λ�ź�
+    .clk_out(clk_cpu)               //�������CPU��ʱ��
+    );
+
+endmodule

Misaka-N_TJCS-SingleCircleCPU31/Post-Synthesis Timing Simulation/sources/seg7x16.v

@@ -0,0 +1,89 @@
+`timescale 1ns / 1ps
+module seg7x16(
+    input clk,
+	input reset,
+	input cs,
+	input [31:0] i_data,	//需要数码管输出的内容
+	output [7:0] o_seg,		//输出内容
+	output [7:0] o_sel		//片选信号
+    );
+
+    reg [14:0] cnt;
+	 always @ (posedge clk, posedge reset)
+      if (reset)
+        cnt <= 0;
+      else
+        cnt <= cnt + 1'b1;
+ 
+    wire seg7_clk = cnt[14]; 
+	 
+	 reg [2:0] seg7_addr;
+	 
+	 always @ (posedge seg7_clk, posedge reset)
+	   if(reset)
+		  seg7_addr <= 0;
+		else
+		  seg7_addr <= seg7_addr + 1'b1;
+		  
+	 reg [7:0] o_sel_r;
+	 
+	 always @ (*)
+	   case(seg7_addr)
+		  7 : o_sel_r = 8'b01111111;
+		  6 : o_sel_r = 8'b10111111;
+		  5 : o_sel_r = 8'b11011111;
+		  4 : o_sel_r = 8'b11101111;
+		  3 : o_sel_r = 8'b11110111;
+		  2 : o_sel_r = 8'b11111011;
+		  1 : o_sel_r = 8'b11111101;
+		  0 : o_sel_r = 8'b11111110;
+		endcase
+	
+	 reg [31:0] i_data_store;
+	 always @ (posedge clk, posedge reset)
+	   if(reset)
+		  i_data_store <= 0;
+		else if(cs)
+		  i_data_store <= i_data;
+		  
+	 reg [7:0] seg_data_r;
+	 always @ (*)
+	   case(seg7_addr)
+		  0 : seg_data_r = i_data_store[3:0];
+		  1 : seg_data_r = i_data_store[7:4];
+		  2 : seg_data_r = i_data_store[11:8];
+		  3 : seg_data_r = i_data_store[15:12];
+		  4 : seg_data_r = i_data_store[19:16];
+		  5 : seg_data_r = i_data_store[23:20];
+		  6 : seg_data_r = i_data_store[27:24];
+		  7 : seg_data_r = i_data_store[31:28];
+		endcase
+	 
+	 reg [7:0] o_seg_r;
+	 always @ (posedge clk, posedge reset)
+	   if(reset)
+		  o_seg_r <= 8'hff;
+		else
+		  case(seg_data_r)
+		    	4'h0 : o_seg_r <= 8'hC0;
+          		4'h1 : o_seg_r <= 8'hF9;
+          		4'h2 : o_seg_r <= 8'hA4;
+          		4'h3 : o_seg_r <= 8'hB0;
+          		4'h4 : o_seg_r <= 8'h99;
+          		4'h5 : o_seg_r <= 8'h92;
+          		4'h6 : o_seg_r <= 8'h82;
+          		4'h7 : o_seg_r <= 8'hF8;
+          		4'h8 : o_seg_r <= 8'h80;
+         		4'h9 : o_seg_r <= 8'h90;
+          		4'hA : o_seg_r <= 8'h88;
+          		4'hB : o_seg_r <= 8'h83;
+          		4'hC : o_seg_r <= 8'hC6;
+			4'hD : o_seg_r <= 8'hA1;
+          		4'hE : o_seg_r <= 8'h86;
+          		4'hF : o_seg_r <= 8'h8E;
+		  endcase
+		  
+	 assign o_sel = o_sel_r;
+	 assign o_seg = o_seg_r;
+
+endmodule

Misaka-N_TJCS-SingleCircleCPU31/README.md

@@ -0,0 +1,23 @@
+# TJCS-SingleCircleCPU31
+同济大学2021级计算机科学与技术系 计算机组成与原理实验 单周期31条指令CPU
+
+
+
+Update(2023.5.8)：给大家写了6500字的教程，希望对大家有帮助呀！🥳
+
+
+
+Update(2023.5.9)：经过大家的反馈，在最后的提交流程中加入了提交文件清单。
+
+
+
+Update(2023.5.10)：今天问了CYS，他说要过后仿真和下板，所以补充了后仿真和下板的教程，目前教程已达10000字。
+
+
+
+Update(2023.5.16)：修改了数据通路中的一些笔误。
+
+
+
+Update(2023.5.22)：修改了教程后仿真部分中的tb文件，使其能够适合更多人的CPU。
+

Misaka-N_TJCS-SingleCircleCPU31/sources/ALU.v

@@ -0,0 +1,61 @@
+`timescale 1ns / 1ps
+module ALU(                      //ALU相比上学期已经进行了重构。注意：其实ALU中只有组合逻辑，并不涉及时序逻辑和存储信息，也就不需要加复位信号
+    input  [31:0] A,             //对应A接口
+    input  [31:0] B,             //对应B接口
+    input  [3:0] ALUC,           //ALUC四位操作指令
+    output [31:0] alu_data_out,  //输出数据
+    output zero,                 //ZF标志位，BEQ/BNE使用
+    output carry,                //CF标志位，SLTI/SLTIU使用
+    output negative,             //NF(SF)标志位，SLT/SLTU使用
+    output overflow              //OF标志位，其实没有用到
+    );
+/* 定义各指令对应的操作 */
+parameter ADDU = 4'b0000;
+parameter ADD  = 4'b0010;
+parameter SUBU = 4'b0001;
+parameter SUB  = 4'b0011;
+parameter AND  = 4'b0100;
+parameter OR   = 4'b0101;
+parameter XOR  = 4'b0110;
+parameter NOR  = 4'b0111;
+parameter LUI1 = 4'b1000;
+parameter LUI2 = 4'b1001;   //注意：LUI是100X，因此有LUI1和LUI2之分
+parameter SLT  = 4'b1011;
+parameter SLTU = 4'b1010;
+parameter SRA  = 4'b1100;
+parameter SLL  = 4'b1110;   //SLL和SLA本质上是一样的，但是由于SLL和SLR的指令为111X，因此将其分开了
+parameter SLA  = 4'b1111;
+parameter SRL  = 4'b1101;
+/* 定义一些内部用的变量 */
+reg [32:0] result;                  //存储结果，设置成33位是为了标志位的判断
+wire signed [31:0] signedA,signedB; //由于A和B传进来是无符号的，因此我们需要定义两个有符号wire型变量来存储A和B在有符号解释下的值
+assign signedA = A;
+assign signedB = B;
+
+always @(*)
+begin
+    case(ALUC)
+        ADDU:       begin result <= A + B;                          end 
+        ADD:        begin result <= signedA + signedB;              end
+        SUBU:       begin result <= A - B;                          end
+        SUB:        begin result <= signedA - signedB;              end
+        AND:        begin result <= A & B;                          end
+        OR:         begin result <= A | B;                          end
+        XOR:        begin result <= A ^ B;                          end
+        NOR:        begin result <= ~(A | B);                       end
+        LUI1,LUI2:  begin result <= { B[15:0] , 16'b0 };            end
+        SLT:        begin result <= signedA - signedB;              end
+        SLTU:       begin result <= A - B;                          end
+        SRA:        begin result <= signedB >>> signedA;            end
+        SLL,SLA:    begin result <= B << A;                         end
+        SRL:        begin result <= B >> A;                         end
+    endcase
+end 
+
+assign alu_data_out = result[31:0];
+assign zero = (result == 32'b0) ? 1 : 0;
+assign carry = result[32]; 
+assign negative =  (ALUC == SLT ? (signedA < signedB) : ((ALUC == SLTU) ? (A < B) : 1'b0));//因为其他计算用不到negtive位，所以可以这么写
+assign overflow = result[32];
+
+endmodule

Misaka-N_TJCS-SingleCircleCPU31/sources/CPU.v

@@ -0,0 +1,240 @@
+`timescale 1ns / 1ps
+module cpu(
+    input clk,                  //CPUִ��ʱ��
+    input ena,                  //ʹ���źŶ�
+    input rst_n,                //��λ�ź�
+    input [31:0] instr_in,      //��ǰҪִ�е�ָ��
+    input [31:0] dm_data,       //��ȡ����DMEM�ľ�������
+    output dm_ena,              //�Ƿ���Ҫ����DMEM
+    output dm_w,                //�������DMEM���Ƿ�Ϊд��
+    output dm_r,                //�������DMEM���Ƿ�Ϊ��ȡ
+    output [31:0] pc_out,       //���ָ���ַ������IMEMҪȡ����
+    output [31:0] dm_addr,      //����DMEM�ĵ�ַ
+    output [31:0] dm_data_w     //Ҫд��DMEM������ 
+    );
+/* ����һЩ�ڲ����� */
+/* Decoder�� */
+wire add_flag,  addu_flag, sub_flag, subu_flag, and_flag, or_flag, xor_flag, nor_flag,
+     slt_flag,  sltu_flag,
+     sll_flag,  srl_flag,  sra_flag, sllv_flag,
+     srlv_flag, srav_flag,
+     jr_flag,
+     addi_flag, addiu_flag,
+     andi_flag, ori_flag,  xori_flag,
+     lw_flag,   sw_flag,
+     beq_flag,  bne_flag,
+     slti_flag, sltiu_flag,
+     lui_flag,
+     j_flag,    jal_flag;       //����ָ��ı�־��Ϣ
+wire [4:0] RsC;                 //Rs��Ӧ�ļĴ����ĵ�ַ
+wire [4:0] RtC;                 //Rt��Ӧ�ļĴ����ĵ�ַ
+wire [4:0] RdC;                 //Rd��Ӧ�ļĴ����ĵ�ַ
+wire [4:0] shamt;               //λ��ƫ������SLL��SRL��SRA�ã�
+wire [15:0] immediate;          //��������I��ָ���ã�
+wire [25:0] address;            //��ת��ַ��J��ָ���ã�
+
+/* Control�� */
+wire reg_w;                     //RegFile�Ĵ������Ƿ��д��
+wire [9:0] mux;                 //9����·ѡ������״̬
+wire [4:0] ext_ena;             //EXT��չ�Ƿ�����5��״̬�ֱ��ӦEXT1��EXT5��EXT16��EXT16(S)��EXT18(S),����EXT[0]��ӦEXT1
+wire cat_ena;                   //�Ƿ���Ҫƴ��
+
+/* ALU�� */
+wire [31:0] a, b;                              //ALU��A��B���������
+wire [3:0]  aluc;                       //ALUC��λ����ָ��
+wire [31:0] alu_data_out;               //ALU���������
+wire zero, carry, negative, overflow;   //�ĸ���־λ
+
+/* �Ĵ�����RegFile�� */
+wire [31:0] Rd_data_in;     //Ҫ��Ĵ�����д���ֵ
+wire [31:0] Rs_data_out;    //Rs��Ӧ�ļĴ��������ֵ
+wire [31:0] Rt_data_out;    //Rt��Ӧ�ļĴ��������ֵ
+
+/* PC�Ĵ����� */
+wire [31:0] pc_addr_in;     //��������PC�Ĵ�����ָ���ַ��Ҳ������һ��Ҫִ�е�ָ��
+wire [31:0] pc_addr_out;    //���δ�PC�Ĵ����д�����ָ���ַ��Ҳ���ǵ�ǰ��Ҫִ�е�ָ��
+
+/* ���Ӹ�ģ�� */
+/* ���š�������չ����· */
+wire [31:0] ext1_out;
+wire [31:0] ext5_out;
+wire [31:0] ext16_out;
+wire signed [31:0] ext16_out_signed;
+wire signed [31:0] ext18_out_signed;
+
+assign ext1_out         = (slt_flag  || sltu_flag) ? negative : (slti_flag || sltiu_flag) ? carry : 32'hz;
+assign ext5_out         = (sll_flag  || srl_flag   || sra_flag) ? shamt : 32'hz;
+assign ext16_out        = (andi_flag || ori_flag   || xori_flag || lui_flag) ? { 16'h0 , immediate[15:0] } : 32'hz;
+assign ext16_out_signed = (addi_flag || addiu_flag || lw_flag || sw_flag || slti_flag || sltiu_flag) ?  { {16{immediate[15]}} , immediate[15:0] } : 32'hz;
+assign ext18_out_signed = (beq_flag  || bne_flag) ? {{14{immediate[15]}}, immediate[15:0], 2'b0} : 32'hz;
+//ע�⣺Verilog������ʽ�ؽ��޷�������Ϊ�з�������ֻ��������ʱ�Ż���в�����������Dz���ͨ����ֵ�ķ�����ɴ��޷��������з���������չ�����뽫����λ���Ƶ���λ
+
+/* ||ƴ������· */
+wire [31:0] cat_out;
+
+assign cat_out = cat_ena ? {pc_out[31:28], address[25:0], 2'h0} : 32'hz;
+
+/* NPC��· */
+wire [31:0] npc;
+assign npc = pc_addr_out + 4;
+
+/* ��·ѡ������· */
+wire [31:0] mux1_out;
+wire [31:0] mux2_out;
+wire [31:0] mux3_out;
+wire [31:0] mux4_out;
+wire [31:0] mux5_out;
+wire [31:0] mux6_out;
+wire [31:0] mux7_out;
+wire [31:0] mux8_out;
+wire [31:0] mux9_out;
+
+assign mux1_out = mux[1] ? cat_out          : mux4_out;
+assign mux2_out = mux[2] ? mux9_out         : dm_data;
+assign mux3_out = mux[3] ? ext5_out         : ((sllv_flag || srlv_flag || srav_flag) ? { 27'h0, Rs_data_out[4:0] } : Rs_data_out);//�ر�ע������ǼĴ�������λָ�Ҫ�Խ���a�����ݽ��д�����ֻȡ�����λ
+assign mux4_out = mux[4] ? mux6_out         : Rs_data_out;
+assign mux5_out = mux[5] ? mux8_out         : Rt_data_out;
+assign mux6_out = mux[6] ? npc              : ext18_out_signed + npc;
+assign mux7_out = mux[7] ? pc_addr_out + 4  : mux2_out;
+assign mux8_out = mux[8] ? ext16_out_signed : ext16_out;
+assign mux9_out = mux[9] ? alu_data_out     : ext1_out;
+
+/* PC��· */
+assign pc_addr_in = mux1_out;
+
+/* ALU ���߿� */
+assign a = mux3_out;
+assign b = mux5_out;
+
+/* IMEM�ӿ� */
+assign pc_out = pc_addr_out;
+
+/* DMEM�ӿ� */
+assign dm_ena  = (dm_r || dm_w) ? 1'b1 : 1'b0;
+assign dm_addr = alu_data_out;
+assign dm_data_w = Rt_data_out;
+
+/* �Ĵ�������· */
+assign Rd_data_in = mux7_out;
+
+/* ʵ���������� */
+Decoder Decoder_inst(
+    .instr_in(instr_in),        //��Ҫ�����ָ�Ҳ���ǵ�ǰҪִ�е�ָ��
+    .add_flag(add_flag),        //ָ���Ƿ�ΪADD
+    .addu_flag(addu_flag),      //ָ���Ƿ�ΪADDU
+    .sub_flag(sub_flag),        //ָ���Ƿ�ΪSUB
+    .subu_flag(subu_flag),      //ָ���Ƿ�ΪSUBU
+    .and_flag(and_flag),        //ָ���Ƿ�ΪAND
+    .or_flag(or_flag),          //ָ���Ƿ�ΪOR
+    .xor_flag(xor_flag),        //ָ���Ƿ�ΪXOR
+    .nor_flag(nor_flag),        //ָ���Ƿ�ΪNOR
+    .slt_flag(slt_flag),        //ָ���Ƿ�ΪSLT
+    .sltu_flag(sltu_flag),      //ָ���Ƿ�ΪSLTU
+    .sll_flag(sll_flag) ,       //ָ���Ƿ�ΪSLL
+    .srl_flag(srl_flag),        //ָ���Ƿ�ΪSRL
+    .sra_flag(sra_flag),        //ָ���Ƿ�ΪSRA
+    .sllv_flag(sllv_flag),      //ָ���Ƿ�ΪSLLV
+    .srlv_flag(srlv_flag),      //ָ���Ƿ�ΪSRLV
+    .srav_flag(srav_flag),      //ָ���Ƿ�ΪSRAV
+    .jr_flag(jr_flag),          //ָ���Ƿ�ΪJR
+    .addi_flag(addi_flag),      //ָ���Ƿ�ΪADDI
+    .addiu_flag(addiu_flag),    //ָ���Ƿ�ΪADDIU
+    .andi_flag(andi_flag),      //ָ���Ƿ�ΪANDI
+    .ori_flag(ori_flag),        //ָ���Ƿ�ΪORI
+    .xori_flag(xori_flag),      //ָ���Ƿ�ΪXORI
+    .lw_flag(lw_flag),          //ָ���Ƿ�ΪLW
+    .sw_flag(sw_flag),          //ָ���Ƿ�ΪSW
+    .beq_flag(beq_flag),        //ָ���Ƿ�ΪBEQ
+    .bne_flag(bne_flag),        //ָ���Ƿ�ΪBNE
+    .slti_flag(slti_flag),      //ָ���Ƿ�ΪSLTI
+    .sltiu_flag(sltiu_flag),    //ָ���Ƿ�ΪSLTIU
+    .lui_flag(lui_flag),        //ָ���Ƿ�ΪLUI
+    .j_flag(j_flag),            //ָ���Ƿ�ΪJ
+    .jal_flag(jal_flag),        //ָ���Ƿ�ΪJAL
+    .RsC(RsC),                  //Rs��Ӧ�ļĴ����ĵ�ַ
+    .RtC(RtC),                  //Rt��Ӧ�ļĴ����ĵ�ַ
+    .RdC(RdC),                  //Rd��Ӧ�ļĴ����ĵ�ַ
+    .shamt(shamt),              //λ��ƫ������SLL��SRL��SRA�ã�
+    .immediate(immediate),      //��������I��ָ���ã�
+    .address(address)           //��ת��ַ��J��ָ���ã�
+    );
+
+/* ʵ���������� */
+Controler Controler_inst(              
+    .add_flag(add_flag),        //ָ���Ƿ�ΪADD
+    .addu_flag(addu_flag),      //ָ���Ƿ�ΪADDU
+    .sub_flag(sub_flag),        //ָ���Ƿ�ΪSUB
+    .subu_flag(subu_flag),      //ָ���Ƿ�ΪSUBU
+    .and_flag(and_flag),        //ָ���Ƿ�ΪAND
+    .or_flag(or_flag),          //ָ���Ƿ�ΪOR
+    .xor_flag(xor_flag),        //ָ���Ƿ�ΪXOR
+    .nor_flag(nor_flag),        //ָ���Ƿ�ΪNOR
+    .slt_flag(slt_flag),        //ָ���Ƿ�ΪSLT
+    .sltu_flag(sltu_flag),      //ָ���Ƿ�ΪSLTU
+    .sll_flag(sll_flag) ,       //ָ���Ƿ�ΪSLL
+    .srl_flag(srl_flag),        //ָ���Ƿ�ΪSRL
+    .sra_flag(sra_flag),        //ָ���Ƿ�ΪSRA
+    .sllv_flag(sllv_flag),      //ָ���Ƿ�ΪSLLV
+    .srlv_flag(srlv_flag),      //ָ���Ƿ�ΪSRLV
+    .srav_flag(srav_flag),      //ָ���Ƿ�ΪSRAV
+    .jr_flag(jr_flag),          //ָ���Ƿ�ΪJR
+    .addi_flag(addi_flag),      //ָ���Ƿ�ΪADDI
+    .addiu_flag(addiu_flag),    //ָ���Ƿ�ΪADDIU
+    .andi_flag(andi_flag),      //ָ���Ƿ�ΪANDI
+    .ori_flag(ori_flag),        //ָ���Ƿ�ΪORI
+    .xori_flag(xori_flag),      //ָ���Ƿ�ΪXORI
+    .lw_flag(lw_flag),          //ָ���Ƿ�ΪLW
+    .sw_flag(sw_flag),          //ָ���Ƿ�ΪSW
+    .beq_flag(beq_flag),        //ָ���Ƿ�ΪBEQ
+    .bne_flag(bne_flag),        //ָ���Ƿ�ΪBNE
+    .slti_flag(slti_flag),      //ָ���Ƿ�ΪSLTI
+    .sltiu_flag(sltiu_flag),    //ָ���Ƿ�ΪSLTIU
+    .lui_flag(lui_flag),        //ָ���Ƿ�ΪLUI
+    .j_flag(j_flag),            //ָ���Ƿ�ΪJ
+    .jal_flag(jal_flag),        //ָ���Ƿ�ΪJAL
+    .zero(zero),                //ALU��־λZF
+    .reg_w(reg_w),              //RegFile�Ĵ������Ƿ��д��
+    .aluc(aluc),                //ALUC��ָ�����ALUCִ�к��ֲ���
+    .dm_r(dm_r),                //DMEM�Ƿ��д��
+    .dm_w(dm_w),                //�Ƿ��DMEM�ж�ȡ����
+    .ext_ena(ext_ena),          //EXT��չ�Ƿ�����5��״̬�ֱ��ӦEXT1��EXT5��EXT16��EXT16(S)��EXT18(S),����EXT[0]��ӦEXT1
+    .cat_ena(cat_ena),          //�Ƿ���Ҫƴ��
+    .mux(mux)                   //9����·ѡ������״̬��ѡ��0����ѡ��1��(0û�õ���Ϊ��ʹMUX��ź������±��Ӧ���Զ�һ��)
+    );
+
+/* ʵ����ALU */
+ALU ALU_inst(                      
+    .A(a),                      //��ӦA�ӿ�
+    .B(b),                      //��ӦB�ӿ�
+    .ALUC(aluc),                //ALUC��λ����ָ��
+    .alu_data_out(alu_data_out),//�������
+    .zero(zero),                //ZF��־λ��BEQ/BNEʹ��
+    .carry(carry),              //CF��־λ��SLTI/SLTIUʹ��
+    .negative(negative),        //NF(SF)��־λ��SLT/SLTUʹ��
+    .overflow(overflow)         //OF��־λ����ʵû���õ�
+    );
+
+/* ʵ�����Ĵ����� */
+regfile cpu_ref(                //�Ĵ�����RegFile��д��Ϊͬ������ȡΪ�첽
+    .reg_clk(clk),              //ʱ���źţ��½�����Ч
+    .reg_ena(ena),              //ʹ���źŶˣ���������Ч
+    .rst_n(rst_n),              //��λ�źţ��ߵ�ƽ��Ч����������أ�
+    .reg_w(reg_w),              //д�źţ��ߵ�ƽʱ�Ĵ�����д�룬�͵�ƽ����д��
+    .RdC(RdC),                  //Rd��Ӧ�ļĴ����ĵ�ַ��д��ˣ�
+    .RtC(RtC),                  //Rt��Ӧ�ļĴ����ĵ�ַ������ˣ�
+    .RsC(RsC),                  //Rs��Ӧ�ļĴ����ĵ�ַ������ˣ�
+    .Rd_data_in(Rd_data_in),    //Ҫ��Ĵ�����д���ֵ��������reg_w��
+    .Rs_data_out(Rs_data_out),  //Rs��Ӧ�ļĴ��������ֵ
+    .Rt_data_out(Rt_data_out)   //Rt��Ӧ�ļĴ��������ֵ
+    );
+
+/* ʵ����PC�Ĵ��� */
+PC PC_inst(                     //ָ���ַ�Ĵ���
+    .pc_clk(clk),               //PC�Ĵ�����ʱ���źţ�д��Ϊͬ����ʱ���½�����Ч������ȡΪ�첽
+    .pc_ena(ena),               //ʹ�ܶ��źţ��ߵ�ƽ��Ч
+    .rst_n(rst_n),              //��λ�źţ��ߵ�ƽ��Ч
+    .pc_addr_in(pc_addr_in),    //��������PC�Ĵ�����ָ���ַ��Ҳ������һ��Ҫִ�е�ָ��
+    .pc_addr_out(pc_addr_out)   //���δ�PC�Ĵ����д�����ָ���ַ��Ҳ���ǵ�ǰ��Ҫִ�е�ָ��
+    );
+
+endmodule

Misaka-N_TJCS-SingleCircleCPU31/sources/Controler.v

@@ -0,0 +1,92 @@
+`timescale 1ns / 1ps
+module Controler(              //�����������ݵ�ǰҪִ�е�ָ���������Ԫ������״̬
+    input add_flag,            //ָ���Ƿ�ΪADD
+    input addu_flag,           //ָ���Ƿ�ΪADDU
+    input sub_flag,            //ָ���Ƿ�ΪSUB
+    input subu_flag,           //ָ���Ƿ�ΪSUBU
+    input and_flag,            //ָ���Ƿ�ΪAND
+    input or_flag,             //ָ���Ƿ�ΪOR
+    input xor_flag,            //ָ���Ƿ�ΪXOR
+    input nor_flag,            //ָ���Ƿ�ΪNOR
+    input slt_flag,            //ָ���Ƿ�ΪSLT
+    input sltu_flag,           //ָ���Ƿ�ΪSLTU
+    input sll_flag,            //ָ���Ƿ�ΪSLL
+    input srl_flag,            //ָ���Ƿ�ΪSRL
+    input sra_flag,            //ָ���Ƿ�ΪSRA
+    input sllv_flag,           //ָ���Ƿ�ΪSLLV
+    input srlv_flag,           //ָ���Ƿ�ΪSRLV
+    input srav_flag,           //ָ���Ƿ�ΪSRAV
+    input jr_flag,             //ָ���Ƿ�ΪJR
+    input addi_flag,           //ָ���Ƿ�ΪADDI
+    input addiu_flag,          //ָ���Ƿ�ΪADDIU
+    input andi_flag,           //ָ���Ƿ�ΪANDI
+    input ori_flag,            //ָ���Ƿ�ΪORI
+    input xori_flag,           //ָ���Ƿ�ΪXORI
+    input lw_flag,             //ָ���Ƿ�ΪLW
+    input sw_flag,             //ָ���Ƿ�ΪSW
+    input beq_flag,            //ָ���Ƿ�ΪBEQ
+    input bne_flag,            //ָ���Ƿ�ΪBNE
+    input slti_flag,           //ָ���Ƿ�ΪSLTI
+    input sltiu_flag,          //ָ���Ƿ�ΪSLTIU
+    input lui_flag,            //ָ���Ƿ�ΪLUI
+    input j_flag,              //ָ���Ƿ�ΪJ
+    input jal_flag,            //ָ���Ƿ�ΪJAL
+    input zero,                //ALU��־λZF
+    /* �����õ���Ԫ����ָ�����ﶼ���漰�� */
+    output reg_w,              //RegFile�Ĵ������Ƿ��д��
+    output [3:0] aluc,         //ALUC��ָ�����ALUCִ�к��ֲ���
+    output dm_r,               //DMEM�Ƿ��д��
+    output dm_w,               //�Ƿ��DMEM�ж�ȡ����
+    output [4:0] ext_ena,      //EXT��չ�Ƿ�����5��״̬�ֱ��ӦEXT1��EXT5��EXT16��EXT16(S)��EXT18(S),����EXT[0]��ӦEXT1
+    output cat_ena,            //�Ƿ���Ҫƴ��
+    output [9:0] mux           //9����·ѡ������״̬��ѡ��0����ѡ��1��(0û�õ���Ϊ��ʹMUX��ź������±��Ӧ���Զ�һ��)
+    );
+/* �����Ǹ�ֵ��Ҳ���Ǹ���Ҫִ�еIJ���������Ԫ������״̬ */
+assign reg_w = (!jr_flag && !sw_flag && !beq_flag && !bne_flag && !j_flag) ? 1'b1 : 1'b0;
+
+assign aluc[3] = (slt_flag  || sltu_flag  || sllv_flag || srlv_flag ||
+                  srav_flag || sll_flag   || srl_flag  || sra_flag  || 
+                  slti_flag || sltiu_flag || lui_flag) ? 1'b1 : 1'b0;
+assign aluc[2] = (and_flag  || or_flag    || xor_flag  || nor_flag  ||
+                  sllv_flag || srlv_flag  || srav_flag || sll_flag  ||
+                  srl_flag  || sra_flag   || andi_flag || ori_flag  ||
+                  xori_flag) ? 1'b1 : 1'b0;
+assign aluc[1] = (add_flag  || sub_flag   || xor_flag  || nor_flag  ||
+                  slt_flag  || sltu_flag  || sllv_flag || sll_flag  ||
+                  addi_flag || xori_flag  || slti_flag || sltiu_flag) ? 1'b1 : 1'b0;
+assign aluc[0] = (sub_flag  || subu_flag  || or_flag   || nor_flag  ||
+                  slt_flag  || sllv_flag  || srlv_flag || sll_flag  ||
+                  srl_flag  || ori_flag   || slti_flag || lui_flag  ||
+                  beq_flag  || bne_flag) ? 1'b1 : 1'b0;
+//aluc[0]��SLLV��SLL��LUI�Ӳ��Ӿ���
+
+assign dm_r = lw_flag ? 1'b1 : 1'b0;
+assign dm_w = sw_flag ? 1'b1 : 1'b0;
+
+assign ext_ena[4] = (beq_flag  || bne_flag) ? 1'b1 : 1'b0;                              //EXT18(S)
+assign ext_ena[3] = (addi_flag || addiu_flag || lw_flag   || sw_flag ||
+                     slti_flag || sltiu_flag) ? 1'b1 : 1'b0;                            //EXT16(S)
+assign ext_ena[2] = (andi_flag || ori_flag   || xori_flag || lui_flag) ? 1'b1 : 1'b0;   //EXT16
+assign ext_ena[1] = (sll_flag  || srl_flag   || sra_flag) ? 1'b1 : 1'b0;                //EXT5
+assign ext_ena[0] = (slt_flag  || sltu_flag  || slti_flag || sltiu_flag) ? 1'b1 : 1'b0; //EXT1
+
+assign cat_ena = (j_flag || jal_flag) ? 1'b1 : 1'b0;
+
+assign mux[9] = (add_flag   || addu_flag  || sub_flag  || subu_flag  ||
+                 and_flag   || or_flag    || xor_flag  || nor_flag   ||
+                 sll_flag   || srl_flag   || sra_flag  || sllv_flag  ||
+                 srlv_flag  || srav_flag  || lui_flag  || addi_flag  || 
+                 addiu_flag || andi_flag  || ori_flag  || xori_flag) ? 1'b1 : 1'b0;
+assign mux[8] = (addi_flag  || addiu_flag || lw_flag   || sw_flag    ||
+                 slti_flag  || sltiu_flag) ? 1'b1 : 1'b0;
+assign mux[7] = jal_flag ? 1'b1 : 1'b0;
+assign mux[6] = beq_flag ? ~zero : (bne_flag ? zero : 1'b1);
+assign mux[5] = (addi_flag  || addiu_flag || andi_flag || ori_flag  ||
+                 xori_flag  || lw_flag    || sw_flag   || slti_flag ||
+                 sltiu_flag || lui_flag) ? 1'b1 : 1'b0;
+assign mux[4] = (!jr_flag && !j_flag && !jal_flag) ? 1'b1 : 1'b0;
+assign mux[3] = (sll_flag   || srl_flag   || sra_flag) ? 1'b1 : 1'b0;
+assign mux[2] = !lw_flag ? 1'b1 : 1'b0;
+assign mux[1] = (j_flag || jal_flag) ? 1'b1 : 1'b0;
+
+endmodule

Misaka-N_TJCS-SingleCircleCPU31/sources/DMEM.v

@@ -0,0 +1,22 @@
+`timescale 1ns / 1ps
+module DMEM(                    //DMEM�������ܿ�������Ƴ��첽��ȡ���ݣ�ͬ��д�����ݵ���ʽ
+    input dm_clk,               //DMEMʱ���źţ�ֻ��д����ʱʹ��
+    input dm_ena,               //ʹ���źŶˣ��ߵ�ƽ��Ч����Чʱ���ܶ�ȡ/д������
+    input dm_r,                 //read���źţ���ȡʱ����
+    input dm_w,                 //writeд�źţ�д��ʱ����
+    input [10:0] dm_addr,       //11λ��ַ��Ҫ��ȡ/д��ĵ�ַ
+    input [31:0] dm_data_in,    //д��ʱҪд�������
+    output [31:0] dm_data_out   //��ȡʱ��ȡ��������
+    );
+
+reg [31:0] dmem [31:0];//DMEM����
+
+assign dm_data_out = (dm_ena && dm_r && !dm_w) ? dmem[dm_addr] : 32'bz;//������ʹ�ܶ˿�������ָ����Ч��дָ����Чʱ���Ž���Ӧ��ַ�������ͳ���������Ϊ���迹
+
+always @(negedge dm_clk)//ʱ��������д������
+begin
+    if(dm_ena && dm_w &&!dm_r)//������ʹ�ܶ˿�����дָ����Ч�Ҷ�ָ����Чʱ������Ĵ�����д������
+        dmem[dm_addr]<=dm_data_in;
+end
+//������߶�û����/ͬʱ���ߣ�������ʲô����������ֹ������д�ֶ��ij�ͻ���
+endmodule

Misaka-N_TJCS-SingleCircleCPU31/sources/Decoder.v

@@ -0,0 +1,152 @@
+`timescale 1ns / 1ps
+module Decoder(                 //���нӿ������ǰ�������ָ���Ҫ����Ϊ���迹
+    input  [31:0] instr_in,     //��Ҫ�����ָ�Ҳ���ǵ�ǰҪִ�е�ָ��
+    output add_flag,            //ָ���Ƿ�ΪADD
+    output addu_flag,           //ָ���Ƿ�ΪADDU
+    output sub_flag,            //ָ���Ƿ�ΪSUB
+    output subu_flag,           //ָ���Ƿ�ΪSUBU
+    output and_flag,            //ָ���Ƿ�ΪAND
+    output or_flag,             //ָ���Ƿ�ΪOR
+    output xor_flag,            //ָ���Ƿ�ΪXOR
+    output nor_flag,            //ָ���Ƿ�ΪNOR
+    output slt_flag,            //ָ���Ƿ�ΪSLT
+    output sltu_flag,           //ָ���Ƿ�ΪSLTU
+    output sll_flag,            //ָ���Ƿ�ΪSLL
+    output srl_flag,            //ָ���Ƿ�ΪSRL
+    output sra_flag,            //ָ���Ƿ�ΪSRA
+    output sllv_flag,           //ָ���Ƿ�ΪSLLV
+    output srlv_flag,           //ָ���Ƿ�ΪSRLV
+    output srav_flag,           //ָ���Ƿ�ΪSRAV
+    output jr_flag,             //ָ���Ƿ�ΪJR
+    output addi_flag,           //ָ���Ƿ�ΪADDI
+    output addiu_flag,          //ָ���Ƿ�ΪADDIU
+    output andi_flag,           //ָ���Ƿ�ΪANDI
+    output ori_flag,            //ָ���Ƿ�ΪORI
+    output xori_flag,           //ָ���Ƿ�ΪXORI
+    output lw_flag,             //ָ���Ƿ�ΪLW
+    output sw_flag,             //ָ���Ƿ�ΪSW
+    output beq_flag,            //ָ���Ƿ�ΪBEQ
+    output bne_flag,            //ָ���Ƿ�ΪBNE
+    output slti_flag,           //ָ���Ƿ�ΪSLTI
+    output sltiu_flag,          //ָ���Ƿ�ΪSLTIU
+    output lui_flag,            //ָ���Ƿ�ΪLUI
+    output j_flag,              //ָ���Ƿ�ΪJ
+    output jal_flag,            //ָ���Ƿ�ΪJAL
+    output [4:0]  RsC,          //Rs��Ӧ�ļĴ����ĵ�ַ
+    output [4:0]  RtC,          //Rt��Ӧ�ļĴ����ĵ�ַ
+    output [4:0]  RdC,          //Rd��Ӧ�ļĴ����ĵ�ַ
+    output [4:0]  shamt,        //λ��ƫ������SLL��SRL��SRA�ã�
+    output [15:0] immediate,    //��������I��ָ���ã�
+    output [25:0] address       //��ת��ַ��J��ָ���ã�
+    );
+/* �����ָ����ԭָ���ж�Ӧ�ı��� */
+/* ������Щָ�������չ��OP��ȫΪ0����Ҫ�����6λFUNC�������� */
+parameter ADD_OPE   = 6'b100000;
+parameter ADDU_OPE  = 6'b100001;
+parameter SUB_OPE   = 6'b100010;
+parameter SUBU_OPE  = 6'b100011;
+parameter AND_OPE   = 6'b100100;
+parameter OR_OPE    = 6'b100101;
+parameter XOR_OPE   = 6'b100110;
+parameter NOR_OPE   = 6'b100111;
+parameter SLT_OPE   = 6'b101010;
+parameter SLTU_OPE  = 6'b101011;
+
+parameter SLL_OPE   = 6'b000000;
+parameter SRL_OPE   = 6'b000010;
+parameter SRA_OPE   = 6'b000011;
+
+parameter SLLV_OPE  = 6'b000100;
+parameter SRLV_OPE  = 6'b000110;
+parameter SRAV_OPE  = 6'b000111;
+
+parameter JR_OPE    = 6'b001000;
+/* ������Щָ��ͨ��OP��ֱ�Ӽ������� */
+parameter ADDI_OPE  = 6'b001000;
+parameter ADDIU_OPE = 6'b001001;
+parameter ANDI_OPE  = 6'b001100;
+parameter ORI_OPE   = 6'b001101;
+parameter XORI_OPE  = 6'b001110;
+parameter LW_OPE    = 6'b100011;
+parameter SW_OPE    = 6'b101011;
+parameter BEQ_OPE   = 6'b000100;
+parameter BNE_OPE   = 6'b000101;
+parameter SLTI_OPE  = 6'b001010;
+parameter SLTIU_OPE = 6'b001011;
+
+parameter LUI_OPE   = 6'b001111;
+
+parameter J_OPE     = 6'b000010;
+parameter JAL_OPE   = 6'b000011;
+
+/* �����Ǹ�ֵ */
+/* ��ָ��������룬�ж����ĸ�ָ�� */
+assign add_flag  = ((instr_in[31:26] == 6'h0) && (instr_in[5:0] == ADD_OPE )) ? 1'b1 : 1'b0;
+assign addu_flag = ((instr_in[31:26] == 6'h0) && (instr_in[5:0] == ADDU_OPE)) ? 1'b1 : 1'b0;
+assign sub_flag  = ((instr_in[31:26] == 6'h0) && (instr_in[5:0] == SUB_OPE )) ? 1'b1 : 1'b0;
+assign subu_flag = ((instr_in[31:26] == 6'h0) && (instr_in[5:0] == SUBU_OPE)) ? 1'b1 : 1'b0;
+assign and_flag  = ((instr_in[31:26] == 6'h0) && (instr_in[5:0] == AND_OPE )) ? 1'b1 : 1'b0;
+assign or_flag   = ((instr_in[31:26] == 6'h0) && (instr_in[5:0] == OR_OPE  )) ? 1'b1 : 1'b0;
+assign xor_flag  = ((instr_in[31:26] == 6'h0) && (instr_in[5:0] == XOR_OPE )) ? 1'b1 : 1'b0;
+assign nor_flag  = ((instr_in[31:26] == 6'h0) && (instr_in[5:0] == NOR_OPE )) ? 1'b1 : 1'b0;
+assign slt_flag  = ((instr_in[31:26] == 6'h0) && (instr_in[5:0] == SLT_OPE )) ? 1'b1 : 1'b0;
+assign sltu_flag = ((instr_in[31:26] == 6'h0) && (instr_in[5:0] == SLTU_OPE)) ? 1'b1 : 1'b0;
+
+assign sll_flag  = ((instr_in[31:26] == 6'h0) && (instr_in[5:0] == SLL_OPE )) ? 1'b1 : 1'b0;
+assign srl_flag  = ((instr_in[31:26] == 6'h0) && (instr_in[5:0] == SRL_OPE )) ? 1'b1 : 1'b0;
+assign sra_flag  = ((instr_in[31:26] == 6'h0) && (instr_in[5:0] == SRA_OPE )) ? 1'b1 : 1'b0;
+
+assign sllv_flag = ((instr_in[31:26] == 6'h0) && (instr_in[5:0] == SLLV_OPE)) ? 1'b1 : 1'b0;
+assign srlv_flag = ((instr_in[31:26] == 6'h0) && (instr_in[5:0] == SRLV_OPE)) ? 1'b1 : 1'b0;
+assign srav_flag = ((instr_in[31:26] == 6'h0) && (instr_in[5:0] == SRAV_OPE)) ? 1'b1 : 1'b0;
+assign jr_flag   = ((instr_in[31:26] == 6'h0) && (instr_in[5:0] == JR_OPE  )) ? 1'b1 : 1'b0;
+
+assign addi_flag  = (instr_in[31:26] == ADDI_OPE ) ? 1'b1 : 1'b0;
+assign addiu_flag = (instr_in[31:26] == ADDIU_OPE) ? 1'b1 : 1'b0;
+assign andi_flag  = (instr_in[31:26] == ANDI_OPE ) ? 1'b1 : 1'b0;
+assign ori_flag   = (instr_in[31:26] == ORI_OPE  ) ? 1'b1 : 1'b0;
+assign xori_flag  = (instr_in[31:26] == XORI_OPE ) ? 1'b1 : 1'b0;
+assign lw_flag    = (instr_in[31:26] == LW_OPE   ) ? 1'b1 : 1'b0;
+assign sw_flag    = (instr_in[31:26] == SW_OPE   ) ? 1'b1 : 1'b0;
+assign beq_flag   = (instr_in[31:26] == BEQ_OPE  ) ? 1'b1 : 1'b0;
+assign bne_flag   = (instr_in[31:26] == BNE_OPE  ) ? 1'b1 : 1'b0;
+assign slti_flag  = (instr_in[31:26] == SLTI_OPE ) ? 1'b1 : 1'b0;
+assign sltiu_flag = (instr_in[31:26] == SLTIU_OPE) ? 1'b1 : 1'b0;
+
+assign lui_flag   = (instr_in[31:26] == LUI_OPE  ) ? 1'b1 : 1'b0;
+
+assign j_flag     = (instr_in[31:26] == J_OPE    ) ? 1'b1 : 1'b0;
+assign jal_flag   = (instr_in[31:26] == JAL_OPE  ) ? 1'b1 : 1'b0;
+
+/* ȡ��ָ���и����ֵ�ֵ */
+assign RsC = (add_flag  || addu_flag || sub_flag  || subu_flag  ||
+              and_flag  || or_flag   || xor_flag  || nor_flag   ||
+              slt_flag  || sltu_flag || sllv_flag || srlv_flag  ||
+              srav_flag || jr_flag   || addi_flag || addiu_flag ||
+              andi_flag || ori_flag  || xori_flag || lw_flag    ||
+              sw_flag   || beq_flag  || bne_flag  || slti_flag  ||
+              sltiu_flag) ? instr_in[25:21] : 5'hz;
+
+assign RtC = (add_flag  || addu_flag  || sub_flag   || subu_flag ||
+              and_flag  || or_flag    || xor_flag   || nor_flag  ||
+              slt_flag  || sltu_flag  || sll_flag   || srl_flag  ||
+              sra_flag  || sllv_flag  || srlv_flag  || srav_flag ||
+              sw_flag   || beq_flag   || bne_flag ) ? instr_in[20:16] : 5'hz;
+
+assign RdC = (add_flag  || addu_flag  || sub_flag  || subu_flag  ||
+              and_flag  || or_flag    || xor_flag  || nor_flag   ||
+              slt_flag  || sltu_flag  || sll_flag  || srl_flag   ||
+              sra_flag  || sllv_flag  || srlv_flag || srav_flag) ? instr_in[15:11] : ((
+              addi_flag || addiu_flag || andi_flag || ori_flag   || 
+              xori_flag || lw_flag    || slti_flag || sltiu_flag ||
+              lui_flag) ? instr_in[20:16] : (jal_flag ? 5'd31 : 5'hz));
+
+assign shamt = (sll_flag || srl_flag || sra_flag) ? instr_in[10:6] : 5'hz;        
+
+assign immediate = (addi_flag || addiu_flag || andi_flag  || ori_flag || 
+                    xori_flag || lw_flag    || sw_flag    || beq_flag || 
+                    bne_flag  || slti_flag  || sltiu_flag || lui_flag) ? instr_in[15:0] : 16'hz;
+
+assign address = (j_flag || jal_flag) ? instr_in[25:0] : 26'hz;     
+
+endmodule

Misaka-N_TJCS-SingleCircleCPU31/sources/IMEM.v

@@ -0,0 +1,11 @@
+`timescale 1ns / 1ps
+module IMEM(
+    input [10:0] im_addr_in,     //11λָ�����ַ����IMEM�ж�ָ��
+    output [31:0] im_instr_out   //32λָ����
+    ); 
+
+dist_mem_gen_0 imem(    //ʵ����IP�ˣ�����ָ�����ַ���ض�Ӧ��ָ��
+    .a(im_addr_in),   //�ӿں�IMEMģ���Ӧ
+    .spo(im_instr_out)
+    );
+endmodule

Misaka-N_TJCS-SingleCircleCPU31/sources/PC.v

@@ -0,0 +1,25 @@
+`timescale 1ns / 1ps
+module PC(                      //ָ���ַ�Ĵ���
+    input  pc_clk,              //PC�Ĵ�����ʱ���źţ�д��Ϊͬ����ʱ���½�����Ч������ȡΪ�첽
+    input  pc_ena,              //ʹ�ܶ��źţ��ߵ�ƽ��Ч
+    input  rst_n,               //��λ�źţ��ߵ�ƽ��Ч
+    input  [31:0] pc_addr_in,   //��������PC�Ĵ�����ָ���ַ��Ҳ������һ��Ҫִ�е�ָ��
+    output [31:0] pc_addr_out   //���δ�PC�Ĵ����д�����ָ���ַ��Ҳ���ǵ�ǰ��Ҫִ�е�ָ��
+    );
+/* �ڲ��ñ��� */
+reg [31:0] pc_reg = 32'h00400000;//��ʼλ����32'h00400000����˸���ֵҲ�����
+
+/* ��ֵ���첽��ȡ */
+assign pc_addr_out = pc_ena ? pc_reg : 32'hz;   //ֻҪʹ�ܶ�Ϊ�ߵ�ƽ������PC�Ĵ���������ʱ���Զ�ȡ����
+
+/* �����������첽д������� */
+always @(negedge pc_clk or posedge rst_n)   //��λ�ź������ػ�ʱ���½�����Ч
+begin
+    if(rst_n && pc_ena)         //��λ�źŸߵ�ƽ����λ��ȫ����0������������д������ena����ֻ�����üĴ����Ѻ������գ����Ӵ�����ʱ���ԣ�Ϊ�����ݰ�ȫ���ǣ��������ǰ�ߣ���ֹ�Ĵ������ݱ���������գ�
+        pc_reg <= 32'h00400000; //ע����ʼλ��ʱ32'h00400000
+    else if(pc_ena)             //��ִ�е�����˵��clk�����½��أ�ֻҪʹ�ܶ�Ϊ�ߵ�ƽ�Ϳ��޸�PC��ֵ
+        pc_reg <= pc_addr_in;
+
+end
+
+endmodule

Misaka-N_TJCS-SingleCircleCPU31/sources/Regfile.v

@@ -0,0 +1,63 @@
+`timescale 1ns / 1ps
+module regfile(                 //�Ĵ�����RegFile��д��Ϊͬ������ȡΪ�첽
+    input  reg_clk,             //ʱ���źţ��½�����Ч
+    input  reg_ena,             //ʹ���źŶˣ���������Ч
+    input  rst_n,               //��λ�źţ��ߵ�ƽ��Ч����������أ�
+    input  reg_w,               //д�źţ��ߵ�ƽʱ�Ĵ�����д�룬�͵�ƽ����д��
+    input  [4:0] RdC,           //Rd��Ӧ�ļĴ����ĵ�ַ��д��ˣ�
+    input  [4:0] RtC,           //Rt��Ӧ�ļĴ����ĵ�ַ������ˣ�
+    input  [4:0] RsC,           //Rs��Ӧ�ļĴ����ĵ�ַ������ˣ�
+    input  [31:0] Rd_data_in,   //Ҫ��Ĵ�����д���ֵ��������reg_w��
+    output [31:0] Rs_data_out,  //Rs��Ӧ�ļĴ��������ֵ
+    output [31:0] Rt_data_out   //Rt��Ӧ�ļĴ��������ֵ
+    );
+/* �ڲ��ñ��� */
+reg [31:0] array_reg [31:0];    //����Ĵ�����
+
+/* ��ֵ���첽��ȡ */
+assign Rs_data_out = reg_ena ? array_reg[RsC] : 32'bz;
+assign Rt_data_out = reg_ena ? array_reg[RtC] : 32'bz;  //ֻҪʹ�ܶ�Ϊ�ߵ�ƽ�����üĴ����ѣ�����ʱ���Զ�ȡ����
+
+/* �����������첽д������� */
+always @(negedge reg_clk or posedge rst_n)  //��λ�ź������ػ�ʱ���½�����Ч
+begin
+    if(rst_n && reg_ena)    //��λ�źŸߵ�ƽ����λ��ȫ����0������������д������ena����ֻ�����üĴ����Ѻ������գ����Ӵ�����ʱ���ԣ�Ϊ�����ݰ�ȫ���ǣ��������ǰ�ߣ���ֹ�Ĵ������ݱ���������գ�
+    begin
+        array_reg[0]  <= 32'h0;
+        array_reg[1]  <= 32'h0;
+        array_reg[2]  <= 32'h0;
+        array_reg[3]  <= 32'h0;
+        array_reg[4]  <= 32'h0;
+        array_reg[5]  <= 32'h0;
+        array_reg[6]  <= 32'h0;
+        array_reg[7]  <= 32'h0;
+        array_reg[8]  <= 32'h0;
+        array_reg[9]  <= 32'h0;
+        array_reg[10] <= 32'h0;
+        array_reg[11] <= 32'h0;
+        array_reg[12] <= 32'h0;
+        array_reg[13] <= 32'h0;
+        array_reg[14] <= 32'h0;
+        array_reg[15] <= 32'h0;
+        array_reg[16] <= 32'h0;
+        array_reg[17] <= 32'h0;
+        array_reg[18] <= 32'h0;
+        array_reg[19] <= 32'h0;
+        array_reg[20] <= 32'h0;
+        array_reg[21] <= 32'h0;
+        array_reg[22] <= 32'h0;
+        array_reg[23] <= 32'h0;
+        array_reg[24] <= 32'h0;
+        array_reg[25] <= 32'h0;
+        array_reg[26] <= 32'h0;
+        array_reg[27] <= 32'h0;
+        array_reg[28] <= 32'h0;
+        array_reg[29] <= 32'h0;
+        array_reg[30] <= 32'h0;
+        array_reg[31] <= 32'h0;
+    end
+    else if(reg_ena && reg_w && (RdC != 5'h0)) //reg_ena��reg_w��Ϊ�ߵ�ƽ�����üĴ���������Ҫд���ݣ�����д���ر�ע�⣺0�żĴ�����0���������޸ģ�����д�뷶Χ֮�ڣ�
+        array_reg[RdC] <= Rd_data_in;
+end
+
+endmodule

Misaka-N_TJCS-SingleCircleCPU31/sources/dist_mem_gen_v8_0.v

@@ -0,0 +1,579 @@
+/*
+ *******************************************************************************
+ *
+ * Distributed Memory Generator - Verilog Behavioral Model
+ *
+ *******************************************************************************
+ *
+ * (c) Copyright 1995 - 2009 Xilinx, Inc. All rights reserved.
+ *
+ * This file contains confidential and proprietary information
+ * of Xilinx, Inc. and is protected under U.S. and
+ * international copyright and other intellectual property
+ * laws.
+ *
+ * DISCLAIMER
+ * This disclaimer is not a license and does not grant any
+ * rights to the materials distributed herewith. Except as
+ * otherwise provided in a valid license issued to you by
+ * Xilinx, and to the maximum extent permitted by applicable
+ * law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+ * WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+ * AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+ * BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+ * INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+ * (2) Xilinx shall not be liable (whether in contract or tort,
+ * including negligence, or under any other theory of
+ * liability) for any loss or damage of any kind or nature
+ * related to, arising under or in connection with these
+ * materials, including for any direct, or any indirect,
+ * special, incidental, or consequential loss or damage
+ * (including loss of data, profits, goodwill, or any type of
+ * loss or damage suffered as a result of any action brought
+ * by a third party) even if such damage or loss was
+ * reasonably foreseeable or Xilinx had been advised of the
+ * possibility of the same.
+ *
+ * CRITICAL APPLICATIONS
+ * Xilinx products are not designed or intended to be fail-
+ * safe, or for use in any application requiring fail-safe
+ * performance, such as life-support or safety devices or
+ * systems, Class III medical devices, nuclear facilities,
+ * applications related to the deployment of airbags, or any
+ * other applications that could lead to death, personal
+ * injury, or severe property or environmental damage
+ * (individually and collectively, "Critical
+ * Applications"). Customer assumes the sole risk and
+ * liability of any use of Xilinx products in Critical
+ * Applications, subject only to applicable laws and
+ * regulations governing limitations on product liability.
+ *
+ * THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+ * PART OF THIS FILE AT ALL TIMES.
+ *
+ *******************************************************************************
+ *******************************************************************************
+ *
+ * Filename    : dist_mem_gen_v8_0_10.v
+ *
+ * Author      : Xilinx
+ *
+ * Description : Distributed Memory Simulation Model
+ *
+ *******************************************************************************
+ */
+
+`timescale 1ps/1ps
+`ifndef TCQ
+ `define TCQ 100
+`endif
+
+`define all0s {C_WIDTH{1'b0}}
+`define allXs {C_WIDTH{1'bx}}
+`define c_rom 0
+`define c_sp_ram 1
+`define c_dp_ram 2
+`define c_sdp_ram 4
+
+module dist_mem_gen_v8_0_10 (a, d, dpra, clk, we, i_ce, qspo_ce, qdpo_ce, qdpo_clk, qspo_rst, qdpo_rst, qspo_srst, qdpo_srst, spo, dpo, qspo, qdpo);
+
+   parameter C_FAMILY             = "virtex5";
+   parameter C_ADDR_WIDTH         = 6;
+   parameter C_DEFAULT_DATA       = "0";
+   parameter C_ELABORATION_DIR    = "./";
+   parameter C_DEPTH              = 64;
+   parameter C_HAS_CLK            = 1;
+   parameter C_HAS_D              = 1;
+   parameter C_HAS_DPO            = 0;
+   parameter C_HAS_DPRA           = 0;
+   parameter C_HAS_I_CE           = 0;
+   parameter C_HAS_QDPO           = 0;
+   parameter C_HAS_QDPO_CE        = 0;
+   parameter C_HAS_QDPO_CLK       = 0;
+   parameter C_HAS_QDPO_RST       = 0;
+   parameter C_HAS_QDPO_SRST      = 0;
+   parameter C_HAS_QSPO           = 0;
+   parameter C_HAS_QSPO_CE        = 0;
+   parameter C_HAS_QSPO_RST       = 0;
+   parameter C_HAS_QSPO_SRST      = 0;
+   parameter C_HAS_SPO            = 1;
+   parameter C_HAS_WE             = 1;
+   parameter C_MEM_INIT_FILE      = "null.mif";
+   parameter C_MEM_TYPE           = 1;
+   parameter C_PIPELINE_STAGES    = 0;
+   parameter C_QCE_JOINED         = 0;
+   parameter C_QUALIFY_WE         = 0;
+   parameter C_READ_MIF           = 0;
+   parameter C_REG_A_D_INPUTS     = 0;
+   parameter C_REG_DPRA_INPUT     = 0;
+   parameter C_SYNC_ENABLE        = 0;
+   parameter C_WIDTH              = 16;
+   parameter C_PARSER_TYPE        = 1;
+     
+   input  [C_ADDR_WIDTH-1:0] a;
+   input  [C_WIDTH-1 : 0] d;
+   input  [C_ADDR_WIDTH-1 : 0] dpra;
+   input  clk;
+   input  we;
+   input  i_ce;
+   input  qspo_ce;
+   input  qdpo_ce;
+   input  qdpo_clk;
+   input  qspo_rst;
+   input  qdpo_rst;
+   input  qspo_srst;
+   input  qdpo_srst;
+   output [C_WIDTH-1 : 0] spo;
+   output [C_WIDTH-1 : 0] qspo;
+   output [C_WIDTH-1 : 0] dpo;
+   output [C_WIDTH-1 : 0] qdpo;
+
+   // Address signal connected to memory
+   wire [C_ADDR_WIDTH - 1 : 0] a_int;
+   
+   // Input data signal connected to memory
+   wire [C_WIDTH - 1 : 0] d_int;
+
+   // Internal Write Enable
+   wire 		       we_int;
+
+   // Internal QSPO Clock Enable
+   wire 		       qspo_ce_int;
+
+   // Internal QDPO Clock
+   wire 		       qdpo_clk_int;
+
+   // Internal Dual Port Read Address connected to memory
+   wire [C_ADDR_WIDTH - 1 : 0] dpra_int;
+
+   // Internal QDPO Clock Enable
+   wire 		       qdpo_ce_int;
+
+   // Registered Write Enable
+   reg 			       we_reg;
+
+   // Registered Address connected to memory
+   reg [C_ADDR_WIDTH - 1 : 0]  a_reg;
+
+   // Registered data signal connected to memory
+   reg [C_WIDTH-1 : 0] 	       d_reg;
+
+   // Registered QSPO Clock Enable
+   reg 			       qspo_ce_reg;
+
+   // Registered Dual Port Read Address connected to memory
+   reg [C_ADDR_WIDTH - 1 : 0]  dpra_reg;
+
+   // Registered QDPO Clock Enable
+   reg 			       qdpo_ce_reg;
+
+   // Internal Single Port RAM output signal
+   wire [C_WIDTH - 1 : 0]       spo_int;
+
+   // Internal Dual Port RAM output signal
+   wire [C_WIDTH - 1 : 0]       dpo_int;
+
+   // Internal ROM/Single Port RAM
+   //  registered output
+   reg [C_WIDTH - 1 : 0]       qspo_int;
+
+   // Pipeline registers
+   reg [C_WIDTH - 1 : 0]       qspo_pipe;
+   
+   // Internal Dual Port RAM registered output
+   reg [C_WIDTH - 1 : 0]       qdpo_int;
+
+   // Pipeline registers
+   reg [C_WIDTH - 1 : 0]       qdpo_pipe;
+   
+   reg [C_WIDTH-1 : 0] 	       ram_data [(2**C_ADDR_WIDTH)-1 : 0];
+   reg [C_WIDTH-1 : 0] 	       ram_data_tmp[C_DEPTH-1 : 0];
+   
+  
+   reg [C_WIDTH-1 : 0] 	       default_data;
+   
+   wire [C_WIDTH-1 : 0]        data_sp;  
+   wire [C_WIDTH-1 : 0]        data_dp;
+
+   wire [C_WIDTH-1 : 0]        data_sp_over;  
+   wire [C_WIDTH-1 : 0]        data_dp_over;
+
+   wire [C_ADDR_WIDTH - 1 : 0] a_over;
+   wire [C_ADDR_WIDTH - 1 : 0] dpra_over;   
+
+   wire 		       a_is_over;
+   wire 		       dpra_is_over;
+   
+   reg [C_ADDR_WIDTH-1 : 0]    max_address;
+   
+   integer 		       i;
+   integer 		       j;   
+
+            
+   // Initial block - initialise the memory,
+   // and when appropriate write content into the given address.
+   initial
+     begin
+	$display("WARNING: This core is supplied with a behavioral model. To model cycle-accurate behavior you must run timing simulation.");
+	
+
+	default_data = 'b0;
+	default_data = binstr_conv(C_DEFAULT_DATA);       	
+	
+        // Assign that C_DEFAULT_DATA to each address in the memory.
+        for (i = 0; i < C_DEPTH; i = i + 1)
+	  begin
+	     ram_data[i] = default_data;
+	     ram_data_tmp[i] = default_data;
+	  end	      
+
+        //Read the MIF file, and use it to initialise the content of ram_data
+        //if that is required.
+        if (C_READ_MIF)
+	  begin
+	     $readmemb(C_MEM_INIT_FILE, ram_data_tmp, 0, C_DEPTH-1);
+    
+	     for (i = 0; i < C_DEPTH; i = i + 1)    
+		  ram_data[i] = ram_data_tmp[i];
+
+	  end
+	
+	if (C_DEPTH != (2**C_ADDR_WIDTH))
+          begin
+	     for (i = C_DEPTH; i < (2**C_ADDR_WIDTH); i = i + 1)
+	       ram_data[i] = 'b0;	     
+	  end
+
+	a_reg       = 'b0;
+	we_reg      = 1'b0;
+	d_reg       = 'b0;
+	qspo_ce_reg = 1'b0;
+	dpra_reg    = 'b0;
+	qdpo_ce_reg = 1'b0;
+
+        qspo_int = default_data;
+	qspo_pipe = 'b0;
+        qdpo_int = default_data;
+	qdpo_pipe = 'b0;
+
+        max_address = C_DEPTH-1;
+
+	
+     end // initial begin  
+   
+   // Now look for writes to the memory (note that this means the
+   // memory is not a ROM and that the Write Enable WE is active.
+   always@(posedge clk)
+     begin
+	if (C_MEM_TYPE != `c_rom && we_int)
+	  begin
+	     if (a_is_over)
+	       begin
+		  $display("WARNING in %m at time %d ns", $time);
+		  $write("Writing to out of range address. ");
+		  $display("Max address in %m is %d", C_DEPTH-1);
+		  $display("Write will be ignored.");
+	       end
+	     else
+	       ram_data[a_int] <= #`TCQ d_int;
+	  end // if (C_MEM_TYPE != `c_rom && we_int)
+     end // always@ (posedge CLK)
+   	 
+   // Model optional input registers, which operate in the CLK clock domain.
+   always @(posedge clk)
+     begin
+        if (C_MEM_TYPE == 0) begin // ROM
+          if (C_HAS_QSPO_CE == 1) begin
+            if (qspo_ce == 1)
+              a_reg  <= #`TCQ a;
+          end else
+    	     a_reg  <= #`TCQ a;
+        end else if (!C_HAS_I_CE)
+	  begin
+	     we_reg <= #`TCQ we;
+    	     a_reg  <= #`TCQ a;
+	     d_reg <= #`TCQ d;
+	  end
+	else if (!C_QUALIFY_WE)
+	  begin
+	     we_reg <= #`TCQ we;
+	     if (i_ce)
+	       begin
+		  a_reg <= #`TCQ a;
+		  d_reg <= #`TCQ d;
+	       end
+	  end
+	else if (C_QUALIFY_WE)
+	  if (i_ce)
+	    begin
+	       we_reg <= #`TCQ we;
+	       a_reg <= #`TCQ a;
+	       d_reg <= #`TCQ d;
+	    end
+
+	qspo_ce_reg <= #`TCQ qspo_ce;
+     end // always @ (posedge CLK)
+   
+      
+   assign we_int      = (C_HAS_WE ? (C_REG_A_D_INPUTS ? we_reg : we) : 1'b0);
+   assign d_int       = (C_MEM_TYPE > 0 ? (C_REG_A_D_INPUTS ? d_reg : d) : 'b0);   
+   assign a_int       = (C_REG_A_D_INPUTS ? a_reg : a);
+   
+   assign qspo_ce_int = (C_HAS_QSPO_CE ? (C_REG_A_D_INPUTS ? qspo_ce_reg : qspo_ce) : 1'b0);   
+
+   assign qdpo_clk_int = (((C_MEM_TYPE == `c_dp_ram) || (C_MEM_TYPE == `c_sdp_ram)) ? 
+      (C_HAS_QDPO_CLK == 1 ? qdpo_clk : clk) : 1'b0);   
+   
+   always@(posedge qdpo_clk_int)
+     begin
+        if (C_QCE_JOINED)
+	  begin
+	     if (!C_HAS_QSPO_CE)
+	       dpra_reg <= #`TCQ dpra;
+	     else if (qspo_ce)
+	       dpra_reg <= #`TCQ dpra;
+	  end
+	else
+	  begin
+	     if (!C_HAS_QDPO_CE)
+	       dpra_reg <= #`TCQ dpra;
+	     else if (qdpo_ce)
+	       dpra_reg <= #`TCQ dpra;
+	  end // else: !if(C_QCE_JOINED)
+
+	qdpo_ce_reg <= #`TCQ qdpo_ce;
+
+     end // always@ (posedge qdpo_clk_int)
+
+   assign dpra_int    = (((C_MEM_TYPE == `c_dp_ram) || (C_MEM_TYPE == `c_sdp_ram)) ? 
+      (C_REG_DPRA_INPUT == 1 ? dpra_reg : dpra) : 1'b0);
+     
+   assign qdpo_ce_int = (((C_MEM_TYPE == `c_dp_ram) || (C_MEM_TYPE == `c_sdp_ram)) ? 
+     (C_HAS_QDPO_CE ? (C_REG_DPRA_INPUT ? qdpo_ce_reg : qdpo_ce) : 1'b0) : 1'b0);
+   
+   always@(posedge a_is_over)
+     begin
+	$display("WARNING in %m at time %d ns: ", $time);
+	$write("Reading from out-of-range address. ");
+	$display("Max address in %m is %d", C_DEPTH-1);
+     end // always@ (a_int or posedge CLK)
+   
+   assign spo = (C_HAS_SPO ? spo_int : `allXs);
+
+   always@(posedge dpra_is_over)
+     begin
+	if ((C_MEM_TYPE == `c_dp_ram) || (C_MEM_TYPE == `c_sdp_ram))
+	  begin
+	     $display("WARNING in %m at time %d ns: ", $time);
+	     $write("Reading from out-of-range address. ");
+	     $display("Max address in %m is %d", C_DEPTH-1);
+	  end // if (C_MEM_TYPE == `c_dp_ram)
+     end // always@ (dpra_int)
+
+   assign spo_int = (a_is_over ? data_sp_over : data_sp);
+   
+   assign dpo_int = (((C_MEM_TYPE == `c_dp_ram) || (C_MEM_TYPE == `c_sdp_ram)) ? (dpra_is_over ? data_dp_over : data_dp) : `allXs);	
+
+   assign data_sp  = ram_data[a_int];
+   assign data_dp  = ram_data[dpra_int];
+
+   assign a_is_over    = (a_int > max_address ? 1'b1 : 1'b0);
+   assign dpra_is_over = (dpra_int > max_address ? 1'b1 : 1'b0);
+
+   assign a_over    = a_int & max_address;
+   assign dpra_over = dpra_int & max_address;
+
+   assign data_sp_over = 'bx;
+   assign data_dp_over = 'bx;
+      
+   assign dpo = (C_HAS_DPO ? dpo_int : `allXs);
+
+   always@(posedge clk or posedge qspo_rst)
+     begin
+	if (C_HAS_QSPO_RST && qspo_rst)
+	  begin
+	     qspo_pipe <= 'b0;
+	     qspo_int <= 'b0;
+	  end
+	else if (C_HAS_QSPO_SRST && qspo_srst)
+	  begin
+	     if (!C_HAS_QSPO_CE)
+	       begin
+		  qspo_pipe <= #`TCQ 'b0;
+		  qspo_int <= #`TCQ 'b0;
+	       end
+	     else if (!C_SYNC_ENABLE)
+	       begin
+		  qspo_pipe <= #`TCQ 'b0;
+		  qspo_int <= #`TCQ 'b0;
+	       end
+	     else if (C_HAS_QSPO_CE && qspo_ce_int)
+	       begin
+		  qspo_pipe <= #`TCQ 'b0;
+		  qspo_int <= #`TCQ 'b0;
+	       end
+	  end // if (C_HAS_QSPO_SRST && QSPO_SRST)
+
+	else if (C_HAS_QSPO_CE && qspo_ce_int)
+	  begin
+	     if (C_PIPELINE_STAGES == 1)
+	       begin
+		  qspo_int <= #`TCQ qspo_pipe;
+	       end
+	     else
+	       begin
+		  qspo_int <= #`TCQ spo_int;
+	       end
+	     qspo_pipe <= #`TCQ spo_int;
+          end
+	else if (!C_HAS_QSPO_CE)
+	  begin
+	     if (C_PIPELINE_STAGES == 1)
+	       begin
+		  qspo_int <= #`TCQ qspo_pipe;
+	       end
+	     else
+	       begin
+		  qspo_int <= #`TCQ spo_int;
+	       end
+	     qspo_pipe <= #`TCQ spo_int;
+	  end // if (!C_HAS_QSPO_CE)
+     end // always@ (posedge CLK or QSPO_RST)
+
+   assign qspo = (C_HAS_QSPO == 1 ? qspo_int : `allXs);   
+
+   always@(posedge qdpo_clk_int or posedge qdpo_rst)
+     begin
+	if (C_HAS_QDPO_RST && qdpo_rst)
+	  begin
+	     qdpo_pipe <= 'b0;
+	     qdpo_int <= 'b0;
+	  end
+	else if (C_HAS_QDPO_SRST && qdpo_srst)
+	  begin
+	     if (!C_SYNC_ENABLE)
+	       begin
+		  qdpo_pipe <= #`TCQ 'b0;
+		  qdpo_int <= #`TCQ 'b0;
+	       end
+	     else if (!C_QCE_JOINED)
+	       begin
+		  if (!C_HAS_QDPO_CE)
+		    begin
+		       qdpo_pipe <= #`TCQ 'b0;
+		       qdpo_int <= #`TCQ 'b0;
+		    end
+		  else if (C_HAS_QDPO_CE && qdpo_ce_int)
+		    begin
+		       qdpo_pipe <= #`TCQ 'b0;
+		       qdpo_int <= #`TCQ 'b0;
+		    end
+	       end
+	     else
+	       begin
+		  if (!C_HAS_QSPO_CE)
+		    begin
+		       qdpo_pipe <= #`TCQ 'b0;
+		       qdpo_int <= #`TCQ 'b0;
+		    end
+		  else if (C_HAS_QSPO_CE && qspo_ce_int)
+		    begin
+		       qdpo_pipe <= #`TCQ 'b0;
+		       qdpo_int <= #`TCQ 'b0;
+		    end
+	       end
+	  end // if (C_HAS_QDPO_SRST && QDPO_SRST)
+	
+	else if (!C_QCE_JOINED)
+	  begin
+	     if (!C_HAS_QDPO_CE)
+	       begin
+		  qdpo_pipe <= #`TCQ dpo_int;
+		  if (C_PIPELINE_STAGES == 1)
+		    begin
+		       qdpo_int <= #`TCQ qdpo_pipe;
+		    end
+		  else
+		    begin
+		       qdpo_int <= #`TCQ dpo_int;
+		    end
+	       end // if (!C_HAS_QDPO_CE)
+	     else if (C_HAS_QDPO_CE && qdpo_ce_int)
+	       begin
+		  qdpo_pipe <= #`TCQ dpo_int;
+		  if (C_PIPELINE_STAGES == 1)
+		    begin
+		       qdpo_int <= #`TCQ qdpo_pipe;
+		    end
+		  else
+		    begin
+		       qdpo_int <= #`TCQ dpo_int;
+		    end
+	       end // if (C_HAS_QDPO_CE && qdpo_ce_int)
+	  end // if (!C_QCE_JOINED)
+	else if (C_QCE_JOINED)
+	  begin
+	     if (C_HAS_QSPO_CE && qspo_ce_int)
+	       begin
+		  qdpo_pipe <= #`TCQ dpo_int;
+		  if (C_PIPELINE_STAGES == 1)
+		    begin
+		       qdpo_int <= #`TCQ qdpo_pipe;
+		    end
+		  else
+		    begin
+		       qdpo_int <= #`TCQ dpo_int;
+		    end
+	       end // if (C_HAS_QSPO_CE && qspo_ce_int)
+	     else if (!C_HAS_QSPO_CE)
+	       begin
+		  qdpo_pipe <= #`TCQ dpo_int;
+		  if (C_PIPELINE_STAGES == 1)
+		    begin
+		       qdpo_int <= #`TCQ qdpo_pipe;
+		    end
+		  else
+		    begin
+		       qdpo_int <= #`TCQ dpo_int;
+		    end
+	       end // if (!C_HAS_QSPO_CE)
+	  end // if (C_QCE_JOINED)
+     end // always@ (posedge qdpo_clk_int or posedge QDPO_RST)
+
+   assign qdpo = (C_HAS_QDPO == 1 ? qdpo_int : `allXs);
+
+   function [C_WIDTH - 1 : 0] binstr_conv;
+      input [(C_WIDTH * 8) - 1 : 0] def_data;
+      integer index,i;
+      begin
+	 index = 0;
+	 binstr_conv = 'b0;	 
+	 
+         for (i=C_WIDTH-1; i>=0; i=i-1)
+	   begin
+	      case (def_data[7:0])
+		8'b00000000 : i = -1;
+		8'b00110000 : binstr_conv[index] = 1'b0;
+		8'b00110001 : binstr_conv[index] = 1'b1;
+		default :
+		  begin
+		     $display("ERROR in %m at time %d ns: NOT A BINARY CHARACTER", $time);
+		     binstr_conv[index] = 1'bx;
+		  end
+	      endcase // case(def_data[7:0])
+
+	      index = index + 1;
+	      def_data = def_data >> 8;
+	   end // for (i=C_WIDTH-1; i>=0; i=i-1)	 
+	 
+      end
+   endfunction // binstr_conv      
+
+endmodule // dist_mem_gen_v8_0_10
+
+`undef all0s
+`undef allXs
+`undef c_rom
+`undef c_sp_ram
+`undef c_dp_ram
+`undef c_sdp_ram

Misaka-N_TJCS-SingleCircleCPU31/sources/sccomp_dataflow.v

@@ -0,0 +1,66 @@
+`timescale 1ns / 1ps
+module sccomp_dataflow(
+    input clk_in,       //ʱ���ź�
+    input reset,        //��λ�ź�
+    output [31:0] inst, //���ָ��
+    output [31:0] pc    //ִ�е�ַ
+    );
+
+/* CPU�� */
+wire [31:0] pc_out;          //���ָ���ַ������IMEMҪȡ����
+wire [31:0] dm_addr_temp;    //DMEM��ʱ��ַ����Ҫת��
+
+
+/* IMEM�� */
+wire [31:0] im_addr_in;     //11λָ�����ַ����IMEM�ж�ָ��
+wire [31:0] im_instr_out;   //32λָ����
+
+assign im_addr_in = pc_out - 32'h00400000;
+
+/* DMEM�� */
+wire dm_ena;                //�Ƿ���Ҫ����DMEM
+wire dm_r, dm_w;            //��дָ��
+wire [31:0] dm_addr;        //��Ҫ�õ���DMEM��ַ
+wire [31:0] dm_data_out;    //DMEM��ȡʱ��ȡ��������
+wire [31:0] dm_data_w;      //Ҫд��DMEM������ 
+
+assign dm_addr = (dm_addr_temp -  32'h10010000)/4;
+
+/* ����� */
+assign pc = pc_out;
+assign inst = im_instr_out;
+
+
+/* IMEMָ��洢������ */
+IMEM imem(
+    .im_addr_in(im_addr_in[12:2]),  //11λָ�����ַ����IMEM�ж�ָ��
+    .im_instr_out(im_instr_out)     //32λָ����
+    );
+
+/* DMEM���ݴ洢������ */
+DMEM dmem(                      //DMEM�������ܿ�������Ƴ��첽��ȡ���ݣ�ͬ��д�����ݵ���ʽ
+    .dm_clk(clk_in),            //DMEMʱ���źţ�ֻ��д����ʱʹ��
+    .dm_ena(dm_ena),            //ʹ���źŶˣ��ߵ�ƽ��Ч����Чʱ���ܶ�ȡ/д������
+    .dm_r(dm_r),                //read���źţ���ȡʱ����
+    .dm_w(dm_w),                //writeд�źţ�д��ʱ����
+    .dm_addr(dm_addr[10:0]),    //11λ��ַ��Ҫ��ȡ/д��ĵ�ַ
+    .dm_data_in(dm_data_w),     //д��ʱҪд�������
+    .dm_data_out(dm_data_out)   //��ȡʱ��ȡ��������
+    );
+
+/* CPU���� */
+cpu sccpu(
+    .clk(clk_in),               //CPUִ��ʱ��
+    .ena(1'b1),                 //ʹ���źŶ�
+    .rst_n(reset),              //��λ�ź�
+    .instr_in(im_instr_out),    //��ǰҪִ�е�ָ��
+    .dm_data(dm_data_out),      //��ȡ����DMEM�ľ�������
+    .dm_ena(dm_ena),            //�Ƿ���Ҫ����DMEM
+    .dm_w(dm_w),                //�������DMEM���Ƿ�Ϊд��
+    .dm_r(dm_r),                //�������DMEM���Ƿ�Ϊ��ȡ
+    .pc_out(pc_out),            //���ָ���ַ������IMEMҪȡ����
+    .dm_addr(dm_addr_temp),     //��Ҫ�õ���DMEM��ַ
+    .dm_data_w(dm_data_w)       //Ҫд��DMEM������ 
+    );
+
+endmodule