Add Repo: steveicarus_ivtest (part 8)

steveicarus_ivtest/ivltests/vhdl_and23_bit.vhd

@@ -0,0 +1,15 @@
+library ieee;
+use ieee.numeric_bit.all;
+
+entity and23 is
+  port (
+    a_i : in bit_vector (22 downto 0);
+    b_i : in bit_vector (22 downto 0);
+    c_o : out bit_vector (22 downto 0)
+  );
+end entity and23;
+
+architecture rtl of and23 is
+begin
+  c_o <= a_i and b_i;
+end architecture rtl;

steveicarus_ivtest/ivltests/vhdl_and_gate.v

@@ -0,0 +1,46 @@
+module stimulus (output reg A, B);
+  reg unsigned [1:0] stimulus_count = 2'b0;
+
+  initial begin
+    {A, B} = 2'b00;
+    #10 {A, B} = 2'b01;
+    #10 {A, B} = 2'b10;
+    #10 {A, B} = 2'b11;
+  end
+
+endmodule
+
+module scoreboard (input Y, A, B);
+  reg [3:0] truth_table;
+  reg Y_s;
+
+initial begin
+  truth_table['b00] = 0;
+  truth_table['b01] = 0;
+  truth_table['b10] = 0;
+  truth_table['b11] = 1;
+end
+
+always @(A or B) begin
+  Y_s = truth_table[{A,B}];
+  #1;
+  //$display ("a = %b, b = %b, Y_s = %b, Y = %b", A, B, Y_s, Y);
+  if (Y_s !== Y) begin
+      $display("FAILED! - mismatch found for inputs %b and %b", A, B);
+      $finish;
+  end
+end
+
+endmodule
+
+module test;
+  stimulus     stim    (A, B);
+  and_gate     duv     (.a_i(A), .b_i(B), .c_o(Y) );
+  scoreboard   mon     (Y, A, B);
+
+  initial begin
+    #100 $display("PASSED");
+    $finish;
+  end
+
+endmodule

steveicarus_ivtest/ivltests/vhdl_and_gate.vhd

@@ -0,0 +1,16 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+
+entity and_gate is
+  port (
+       a_i : in std_logic;    -- inputs
+       b_i : in std_logic;
+       c_o : out std_logic    -- output
+       );
+end entity and_gate;
+
+architecture rtl of and_gate is
+begin
+   c_o <= a_i and b_i;
+end architecture rtl;

steveicarus_ivtest/ivltests/vhdl_andg_bit.v

@@ -0,0 +1,57 @@
+module stimulus (output reg A, B);
+
+
+  initial begin
+    {A, B} = 2'b00;
+    #10 {A, B} = 2'b01;
+    #10 {A, B} = 2'b10;
+    #10 {A, B} = 2'b11;
+  end
+
+endmodule
+
+module scoreboard (input Y, A, B);
+
+function truth_table (input a, b);
+  reg [1:0] gate_operand;
+  reg       gate_output;
+  begin
+    gate_operand[1:0] = {a, b};
+    case (gate_operand)
+        2'b00: gate_output = 0;
+        2'b01: gate_output = 0;
+        2'b10: gate_output = 0;
+        2'b11: gate_output = 1;
+      endcase
+
+    truth_table = gate_output;
+    end
+endfunction
+
+
+reg Y_t;
+
+always @(A or B) begin
+  Y_t = truth_table (A, B);
+  #1;
+  //$display ("a = %b, b = %b, Y_s = %b, Y = %b", A, B, Y_s, Y);
+  if (Y_t !== Y) begin
+      $display("FAILED! - mismatch found for inputs %b and %b in AND operation", A, B);
+      $finish;
+  end
+end
+
+endmodule
+
+module test;
+  stimulus     stim    (A, B);
+  and_gate     duv     (.a_i(A), .b_i(B), .c_o(Y) );
+  scoreboard   mon     (Y, A, B);
+
+  initial begin
+    #100;
+    $display("PASSED");
+    $finish;
+  end
+
+endmodule

steveicarus_ivtest/ivltests/vhdl_andg_bit.vhd

@@ -0,0 +1,16 @@
+library IEEE;
+use IEEE.numeric_bit.all;
+
+
+entity and_gate is
+  port (
+       a_i : in bit;    -- inputs
+       b_i : in bit;
+       c_o : out bit    -- output
+       );
+end entity and_gate;
+
+architecture rtl of and_gate is
+begin
+   c_o <= a_i and b_i;
+end architecture rtl;

steveicarus_ivtest/ivltests/vhdl_andg_stdlogic.v

@@ -0,0 +1,89 @@
+module stimulus (output reg A, B);
+
+  initial begin
+    // both inputs are x
+    #0  {A, B} = 2'bxx;
+     // both inputs are z
+    #10 {A, B} = 2'bzz;
+    // one input is a zero
+    #10 {A, B} = 2'b0x;
+    #10 {A, B} = 2'bx0;
+    #10 {A, B} = 2'b0z;
+    #10 {A, B} = 2'bz0;
+    // one input is a one
+    #10 {A, B} = 2'b1x;
+    #10 {A, B} = 2'bx1;
+    #10 {A, B} = 2'b1z;
+    #10 {A, B} = 2'bz1;
+   // normal bit operands
+    #10 {A, B} = 2'b00;
+    #10 {A, B} = 2'b01;
+    #10 {A, B} = 2'b10;
+    #10 {A, B} = 2'b11;
+  end
+
+endmodule
+
+module scoreboard (input Y, A, B);
+
+function truth_table (input a, b);
+  reg [1:0] gate_operand;
+  reg       gate_output;
+  begin
+    gate_operand[1:0] = {a, b};
+    case (gate_operand)
+        // both inputs are x
+        2'bxx: gate_output = 1'bx;
+        // both inputs are z
+        2'bzz: gate_output = 1'bx;
+        // output should be zero (one input is a zero)
+        2'b0x: gate_output = 0;
+        2'bx0: gate_output = 0;
+        2'b0z: gate_output = 0;
+        2'bz0: gate_output = 0;
+        // output is x  (one input is a one)
+        2'b1x: gate_output = 1'bx;
+        2'bx1: gate_output = 1'bx;
+        2'b1z: gate_output = 1'bx;
+        2'bz1: gate_output = 1'bx;
+        // inputs x, z
+        2'bxz: gate_output = 1'bx;
+        2'bzx: gate_output = 1'bx;
+        // normal operation on bit
+        2'b00: gate_output = 0;
+        2'b01: gate_output = 0;
+        2'b10: gate_output = 0;
+        2'b11: gate_output = 1;
+      endcase
+
+    truth_table = gate_output;
+    end
+endfunction
+
+
+reg Y_t;
+
+always @(A or B) begin
+  Y_t = truth_table (A, B);
+  #1;
+  //$display ("a = %b, b = %b, Y_s = %b, Y = %b", A, B, Y_s, Y);
+  if (Y_t !== Y) begin
+      $display("FAILED! - mismatch found for inputs %b and %b in AND operation", A, B);
+      $finish;
+  end
+end
+
+endmodule
+
+module test;
+  stimulus     stim    (A, B);
+  and_gate     duv     (.a_i(A), .b_i(B), .c_o(Y) );
+  scoreboard   mon     (Y, A, B);
+
+  initial begin
+    #200;
+    $display("PASSED");
+    $finish;
+  end
+
+endmodule

steveicarus_ivtest/ivltests/vhdl_andg_stdlogic.vhd

@@ -0,0 +1,16 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+
+entity and_gate is
+  port (
+       a_i : in std_logic;    -- inputs
+       b_i : in std_logic;
+       c_o : out std_logic    -- output
+       );
+end entity and_gate;
+
+architecture rtl of and_gate is
+begin
+   c_o <= a_i and b_i;
+end architecture rtl;

steveicarus_ivtest/ivltests/vhdl_array_of_array.v

@@ -0,0 +1,35 @@
+// Copyright (c) 2015 CERN
+// Maciej Suminski <maciej.suminski@cern.ch>
+//
+// This source code is free software; you can redistribute it
+// and/or modify it in source code form under the terms of the GNU
+// General Public License as published by the Free Software
+// Foundation; either version 2 of the License, or (at your option)
+// any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the Free Software
+// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+
+
+// Test case for handling an array of arrays
+
+module vhdl_array_of_array_test;
+vhdl_array_of_array dut();
+
+initial begin
+    if(dut.sig[0] !== 8'haa)
+    begin
+        $display("FAILED");
+        $finish();
+    end
+
+    $display("PASSED");
+end
+
+endmodule

steveicarus_ivtest/ivltests/vhdl_array_of_array.vhd

@@ -0,0 +1,35 @@
+-- Copyright (c) 2015 CERN
+-- Maciej Suminski <maciej.suminski@cern.ch>
+--
+-- This source code is free software; you can redistribute it
+-- and/or modify it in source code form under the terms of the GNU
+-- General Public License as published by the Free Software
+-- Foundation; either version 2 of the License, or (at your option)
+-- any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+
+
+-- Test case for handling an array of arrays
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity vhdl_array_of_array is
+end entity vhdl_array_of_array;
+
+architecture test of vhdl_array_of_array is
+  type t_byte_array is array (natural range <>) of std_logic_vector(7 downto 0);
+  signal sig : t_byte_array(2 downto 0);
+
+begin
+    sig <= (0 => x"aa", 1 => x"bb", 2 => x"cc");
+end architecture test;

steveicarus_ivtest/ivltests/vhdl_boolean.v

@@ -0,0 +1,93 @@
+// Copyright (c) 2015 CERN
+// @author Maciej Suminski <maciej.suminski@cern.ch>
+//
+// This source code is free software; you can redistribute it
+// and/or modify it in source code form under the terms of the GNU
+// General Public License as published by the Free Software
+// Foundation; either version 2 of the License, or (at your option)
+// any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the Free Software
+// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+
+
+// boolean values test.
+
+module vhdl_boolean_test;
+
+vhdl_boolean dut();
+
+initial begin
+    if(dut.true_val != \true ) begin
+        $display("FAILED true 1");
+        $finish();
+    end
+
+    if(!dut.true_val) begin
+        $display("FAILED true 2");
+        $finish();
+    end
+
+
+    if(dut.false_val != \false ) begin
+        $display("FAILED false 1");
+        $finish();
+    end
+
+    if(dut.false_val) begin
+        $display("FAILED false 2");
+        $finish();
+    end
+
+
+    if(!dut.and1) begin
+        $display("FAILED and1");
+        $finish();
+    end
+
+    if(dut.and2) begin
+        $display("FAILED and2");
+        $finish();
+    end
+
+    if(dut.and3) begin
+        $display("FAILED and3");
+        $finish();
+    end
+
+
+    if(!dut.or1) begin
+        $display("FAILED or1");
+        $finish();
+    end
+
+    if(!dut.or2) begin
+        $display("FAILED or2");
+        $finish();
+    end
+
+    if(dut.or3) begin
+        $display("FAILED or3");
+        $finish();
+    end
+
+
+    if(!dut.not1) begin
+        $display("FAILED not1");
+        $finish();
+    end
+
+    if(dut.not2) begin
+        $display("FAILED not2");
+        $finish();
+    end
+
+    $display("PASSED");
+end
+endmodule

steveicarus_ivtest/ivltests/vhdl_boolean.vhd

@@ -0,0 +1,43 @@
+-- Copyright (c) 2015 CERN
+-- @author Maciej Suminski <maciej.suminski@cern.ch>
+--
+-- This source code is free software; you can redistribute it
+-- and/or modify it in source code form under the terms of the GNU
+-- General Public License as published by the Free Software
+-- Foundation; either version 2 of the License, or (at your option)
+-- any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+
+
+-- boolean values test.
+
+library ieee;
+
+entity vhdl_boolean is
+end vhdl_boolean;
+
+architecture test of vhdl_boolean is
+    signal true_val, false_val, and1, and2, and3, or1, or2, or3, not1, not2 : boolean;
+begin
+    true_val <= true;
+    false_val <= false;
+
+    and1 <= true and true;
+    and2 <= true and false;
+    and3 <= false and false;
+
+    or1 <= true or true;
+    or2 <= true or false;
+    or3 <= false or false;
+
+    not1 <= not false;
+    not2 <= not true;
+end architecture test;

steveicarus_ivtest/ivltests/vhdl_case_multi.v

@@ -0,0 +1,45 @@
+// Copyright (c) 2014 CERN
+// Maciej Suminski <maciej.suminski@cern.ch>
+//
+// This source code is free software; you can redistribute it
+// and/or modify it in source code form under the terms of the GNU
+// General Public License as published by the Free Software
+// Foundation; either version 2 of the License, or (at your option)
+// any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the Free Software
+// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+
+// Test for multiple choices in case alternative statements.
+
+module vhdl_case_multi_test;
+  reg [2:0] test_vec;
+  reg parity;
+  vhdl_case_multi dut(test_vec, parity);
+
+  initial begin
+    // Execute both paths
+    test_vec = 'b101;
+    #1;
+    if(parity !== 1'b0) begin
+        $display("FAILED 1");
+        $finish();
+    end
+
+    test_vec = 'b001;
+    #1;
+    if(parity !== 1'b1) begin
+        $display("FAILED 2");
+        $finish();
+    end
+
+    $display("PASSED");
+  end
+endmodule
+

steveicarus_ivtest/ivltests/vhdl_case_multi.vhd

@@ -0,0 +1,41 @@
+-- Copyright (c) 2014 CERN
+-- Maciej Suminski <maciej.suminski@cern.ch>
+--
+-- This source code is free software; you can redistribute it
+-- and/or modify it in source code form under the terms of the GNU
+-- General Public License as published by the Free Software
+-- Foundation; either version 2 of the License, or (at your option)
+-- any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+
+-- Test for multiple choices in case alternative statements.
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity vhdl_case_multi is
+  port ( inp: in std_logic_vector (0 to 2);
+         parity: out std_logic );
+end vhdl_case_multi;
+
+architecture vhdl_case_multi_rtl of vhdl_case_multi is
+begin
+
+  process (inp)
+  begin
+    case inp is
+        when "000"|"011"|"101"|"110" => parity <= "0";
+        when "001"|"010"|"100"|"111" => parity <= "1";
+        when others  => parity <= "Z";
+    end case;
+  end process;
+
+end vhdl_case_multi_rtl;

steveicarus_ivtest/ivltests/vhdl_concat.v

@@ -0,0 +1,42 @@
+// Copyright (c) 2014 CERN
+// Maciej Suminski <maciej.suminski@cern.ch>
+//
+// This source code is free software; you can redistribute it
+// and/or modify it in source code form under the terms of the GNU
+// General Public License as published by the Free Software
+// Foundation; either version 2 of the License, or (at your option)
+// any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the Free Software
+// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+
+
+// Test for expression concatenation in VHDL.
+
+module concat_test;
+concat dut();
+
+initial begin
+  #1;       // wait for signal assignments
+
+  if(dut.concat1 !== 2'b10)
+  begin
+    $display("FAILED: concat1 should be 10 but is %b", dut.concat1);
+    $finish();
+  end
+
+  if(dut.concat2 !== 5'b11010)
+  begin
+    $display("FAILED: concat2 should be 11010 but is %b", dut.concat2);
+    $finish();
+  end
+
+  $display("PASSED");
+end
+endmodule

steveicarus_ivtest/ivltests/vhdl_concat.vhd

@@ -0,0 +1,34 @@
+-- Copyright (c) 2014 CERN
+-- Maciej Suminski <maciej.suminski@cern.ch>
+--
+-- This source code is free software; you can redistribute it
+-- and/or modify it in source code form under the terms of the GNU
+-- General Public License as published by the Free Software
+-- Foundation; either version 2 of the License, or (at your option)
+-- any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+
+
+-- Test for expression concatenation in VHDL.
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity concat is
+end concat;
+
+architecture test of concat is
+  signal concat1 : std_logic_vector(1 downto 0);
+  signal concat2 : std_logic_vector(0 to 4);
+begin
+  concat1 <= '1' & '0';
+  concat2 <= '1' & "10" & concat1;
+end test;

steveicarus_ivtest/ivltests/vhdl_concat_func.v

@@ -0,0 +1,38 @@
+// Copyright (c) 2015 CERN
+// Maciej Suminski <maciej.suminski@cern.ch>
+//
+// This source code is free software; you can redistribute it
+// and/or modify it in source code form under the terms of the GNU
+// General Public License as published by the Free Software
+// Foundation; either version 2 of the License, or (at your option)
+// any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the Free Software
+// Foundation, Inc., 59 Temple Place / Suite 330, Boston, MA 02111/1307, USA
+
+
+// Test for concatenation of function call results.
+
+module test_concat_func();
+  logic [7:0] in_word, out_word;
+
+  concat_func dut(in_word, out_word);
+
+  initial begin
+    in_word = 8'b11101010;
+    #1;
+
+    if(out_word !== 8'b11010010) begin
+        $display("FAILED out_word = %b", out_word);
+        $finish();
+    end
+
+    $display("PASSED");
+  end
+endmodule

steveicarus_ivtest/ivltests/vhdl_concat_func.vhd

@@ -0,0 +1,41 @@
+-- Copyright (c) 2015 CERN
+-- Maciej Suminski <maciej.suminski@cern.ch>
+--
+-- This source code is free software; you can redistribute it
+-- and/or modify it in source code form under the terms of the GNU
+-- General Public License as published by the Free Software
+-- Foundation; either version 2 of the License, or (at your option)
+-- any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+
+
+-- Test for concatenation of function call results.
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity concat_func is
+  port(in_word : in std_logic_vector(7 downto 0);
+       out_word : out std_logic_vector(7 downto 0));
+end entity concat_func;
+
+architecture test of concat_func is
+begin
+  process(in_word)
+    variable tmp  : unsigned(7 downto 0);
+    variable int : integer;
+  begin
+    tmp := unsigned(in_word);
+    int := to_integer(tmp);
+    out_word <= in_word(7 downto 6) & std_logic_vector(to_unsigned(int, 3)) & std_logic_vector(resize(tmp, 3));
+  end process;
+end architecture test;

steveicarus_ivtest/ivltests/vhdl_concurrent_assert.v

@@ -0,0 +1,25 @@
+// Copyright (c) 2016 CERN
+// Maciej Suminski <maciej.suminski@cern.ch>
+//
+// This source code is free software; you can redistribute it
+// and/or modify it in source code form under the terms of the GNU
+// General Public License as published by the Free Software
+// Foundation; either version 2 of the License, or (at your option)
+// any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the Free Software
+// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+
+
+// Test for concurrent assertion statements.
+
+module vhdl_concurrent_assert_test;
+vhdl_concurrent_assert dut();
+// we do not need anything else here
+endmodule

steveicarus_ivtest/ivltests/vhdl_concurrent_assert.vhd

@@ -0,0 +1,37 @@
+-- Copyright (c) 2016 CERN
+-- Maciej Suminski <maciej.suminski@cern.ch>
+--
+-- This source code is free software; you can redistribute it
+-- and/or modify it in source code form under the terms of the GNU
+-- General Public License as published by the Free Software
+-- Foundation; either version 2 of the License, or (at your option)
+-- any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+
+
+-- Test for concurrent assertion statements.
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity vhdl_concurrent_assert is
+end vhdl_concurrent_assert;
+
+architecture test of vhdl_concurrent_assert is
+    signal bool_false: boolean := false;
+    signal bool_true: boolean := true;
+begin
+    assert (bool_false)
+    report "this assert should be fired";
+
+    assert (bool_true)
+    report "this assert should not be fired";
+end test;

steveicarus_ivtest/ivltests/vhdl_const_array.v

@@ -0,0 +1,72 @@
+// Copyright (c) 2015 CERN
+// Maciej Suminski <maciej.suminski@cern.ch>
+//
+// This source code is free software; you can redistribute it
+// and/or modify it in source code form under the terms of the GNU
+// General Public License as published by the Free Software
+// Foundation; either version 2 of the License, or (at your option)
+// any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the Free Software
+// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+
+
+// Test for constant arrays access
+
+module constant_array_test();
+reg [7:0] out_word;
+reg [2:0] index;
+constant_array dut(index, out_word);
+
+initial begin
+  index = 2;
+  #1;       // wait for signal assignments
+
+  if(out_word !== 16)
+  begin
+    $display("FAILED 1");
+    $finish();
+  end
+
+  index = 4;
+  #1;
+
+  if(out_word !== 64)
+  begin
+    $display("FAILED 2");
+    $finish();
+  end
+
+  if(dut.test_a !== 32)
+  begin
+    $display("FAILED 3");
+    $finish();
+  end
+
+  if(dut.test_b !== 4)
+  begin
+    $display("FAILED 4");
+    $finish();
+  end
+
+  if(dut.test_c !== 3'b100)
+  begin
+    $display("FAILED 5");
+    $finish();
+  end
+
+  if(dut.test_d !== 1'b1)
+  begin
+    $display("FAILED 6");
+    $finish();
+  end
+
+  $display("PASSED");
+end
+endmodule

steveicarus_ivtest/ivltests/vhdl_const_array.vhd

@@ -0,0 +1,59 @@
+-- Copyright (c) 2015 CERN
+-- Maciej Suminski <maciej.suminski@cern.ch>
+--
+-- This source code is free software; you can redistribute it
+-- and/or modify it in source code form under the terms of the GNU
+-- General Public License as published by the Free Software
+-- Foundation; either version 2 of the License, or (at your option)
+-- any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+
+
+-- Test for constant arrays access
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use work.constant_array_pkg.all;
+
+entity constant_array is
+    port (index  : in  std_logic_vector(2 downto 0);
+          output : out std_logic_vector(7 downto 0));
+end entity constant_array;
+
+architecture test of constant_array is
+  type logic_array is array (integer range <>) of std_logic_vector(0 to 3);
+  constant test_array : logic_array(0 to 5) :=
+    (0      => "0010",
+     1      => "1000",
+     2      => "0100",
+     3      => "0110",
+     4      => "0101",
+     5      => "1100");
+
+  -- Check if constant vectors are not broken with the changes
+  constant vector : std_logic_vector(5 downto 0) := "110011";
+
+  signal test_a : unsigned(7 downto 0);
+  signal test_b : std_logic_vector(3 downto 0);
+  signal test_c : std_logic_vector(2 downto 0);
+  signal test_d : std_logic;
+begin
+  test_a <= const_array(3);
+  test_b <= test_array(2);
+  test_c <= vector(4 downto 2);
+  test_d <= vector(5);
+
+  process (index)
+  begin
+    output <= const_array(to_integer(unsigned(index)));
+  end process;
+end architecture test;

steveicarus_ivtest/ivltests/vhdl_const_array_pkg.vhd

@@ -0,0 +1,36 @@
+-- Copyright (c) 2015 CERN
+-- Maciej Suminski <maciej.suminski@cern.ch>
+--
+-- This source code is free software; you can redistribute it
+-- and/or modify it in source code form under the terms of the GNU
+-- General Public License as published by the Free Software
+-- Foundation; either version 2 of the License, or (at your option)
+-- any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+
+
+-- Test for constant arrays access
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+package constant_array_pkg is
+  type t_unsigned_array is array (natural range <>) of unsigned(7 downto 0);
+  constant const_array : t_unsigned_array(7 downto 0) :=
+    (0      => "00000010",
+     1      => "00001000",
+     2      => "00010000",
+     3      => "00100000",
+     4      => "01000000",
+     5      => "01111100",
+     others => "00000010");
+end package constant_array_pkg;

steveicarus_ivtest/ivltests/vhdl_const_package.v

@@ -0,0 +1,40 @@
+// Copyright (c) 2014 CERN
+// Maciej Suminski <maciej.suminski@cern.ch>
+//
+// This source code is free software; you can redistribute it
+// and/or modify it in source code form under the terms of the GNU
+// General Public License as published by the Free Software
+// Foundation; either version 2 of the License, or (at your option)
+// any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the Free Software
+// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+
+// Tests if constants in packages can be initialized with expressions
+// that normally require elaboration to be properly emitted.
+
+module const_package_test;
+  const_package dut();
+
+  initial begin
+    if(dut.c_bitstring != 'b1001) begin
+      $display("FAILED 1");
+      $finish;
+    end
+
+    #1;   // wait for signal assignment
+
+    if(dut.c_aggregate != 'b10001000) begin
+      $display("FAILED 2");
+      $finish;
+    end
+
+    $display("PASSED");
+  end
+endmodule

steveicarus_ivtest/ivltests/vhdl_const_package.vhd

@@ -0,0 +1,35 @@
+-- Copyright (c) 2014 CERN
+-- Maciej Suminski <maciej.suminski@cern.ch>
+--
+-- This source code is free software; you can redistribute it
+-- and/or modify it in source code form under the terms of the GNU
+-- General Public License as published by the Free Software
+-- Foundation; either version 2 of the License, or (at your option)
+-- any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+
+
+-- Tests if constants in packages can be initialized with expressions
+-- that normally require elaboration to be properly emitted.
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use work.const_package_pkg.all;
+
+entity const_package is
+end const_package;
+
+architecture test of const_package is
+    signal bitstring : std_logic_vector(3 downto 0) := c_bitstring;
+    signal aggregate : std_logic_vector(7 downto 0);
+begin
+   aggregate <= c_aggregate;
+end test;

steveicarus_ivtest/ivltests/vhdl_const_package_pkg.vhd

@@ -0,0 +1,32 @@
+-- Copyright (c) 2014 CERN
+-- Maciej Suminski <maciej.suminski@cern.ch>
+--
+-- This source code is free software; you can redistribute it
+-- and/or modify it in source code form under the terms of the GNU
+-- General Public License as published by the Free Software
+-- Foundation; either version 2 of the License, or (at your option)
+-- any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+
+
+-- Tests if constants in packages can be initialized with expressions
+-- that normally require elaboration to be properly emitted.
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+
+package const_package_pkg is
+    constant c_bitstring : std_logic_vector(3 downto 0) := "1001";
+    constant c_aggregate : std_logic_vector(7 downto 0) := (7 => '1', 3 => '1', others => '0');
+end const_package_pkg;
+
+package body const_package_pkg is
+end const_package_pkg;

steveicarus_ivtest/ivltests/vhdl_const_record.v

@@ -0,0 +1,70 @@
+// Copyright (c) 2015 CERN
+// Maciej Suminski <maciej.suminski@cern.ch>
+//
+// This source code is free software; you can redistribute it
+// and/or modify it in source code form under the terms of the GNU
+// General Public License as published by the Free Software
+// Foundation; either version 2 of the License, or (at your option)
+// any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the Free Software
+// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+
+
+// Test for accessing constant records & arrays of records in VHDL.
+
+module vhdl_const_record_test;
+int sel;
+logic [7:0] hex;
+logic [7:0] aval;
+vhdl_const_record dut(sel, hex, aval);
+
+initial begin
+  if(dut.sig !== 8'h66)
+  begin
+    $display("FAILED 1");
+    $finish();
+  end
+
+  sel = 0;
+  #1;
+  if(hex !== 8'h14 || aval !== 8'haa || dut.sig2 !== 8'h00)
+  begin
+    $display("FAILED 2");
+    $finish();
+  end
+
+  sel = 1;
+  #1;
+  if(hex !== 8'h24 || aval !== 8'hbb || dut.sig2 !== 8'h11)
+  begin
+    $display("FAILED 3");
+    $finish();
+  end
+
+  sel = 2;
+  #1;
+  if(hex !== 8'h34 || aval !== 8'hcc || dut.sig2 !== 8'h22)
+  begin
+    $display("FAILED 4");
+    $finish();
+  end
+
+  sel = 3;
+  #1;
+  if(hex !== 8'h56 || aval !== 8'hdd || dut.sig2 !== 8'h33)
+  begin
+    $display("FAILED 5");
+    $finish();
+  end
+
+  $display("PASSED");
+end
+endmodule
+

steveicarus_ivtest/ivltests/vhdl_const_record.vhd

@@ -0,0 +1,75 @@
+-- Copyright (c) 2015 CERN
+-- Maciej Suminski <maciej.suminski@cern.ch>
+--
+-- This source code is free software; you can redistribute it
+-- and/or modify it in source code form under the terms of the GNU
+-- General Public License as published by the Free Software
+-- Foundation; either version 2 of the License, or (at your option)
+-- any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+
+
+-- Test for accessing constant records & arrays of records in VHDL.
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity vhdl_const_record is
+    port(sel : in integer range 0 to 3;
+         hex : out std_logic_vector(7 downto 0);
+         aval : out std_logic_vector(7 downto 0));
+end entity vhdl_const_record;
+
+architecture test of vhdl_const_record is
+  type t_var is (var_presence, var_identif, var_1, var_2, var_3, var_rst, var_4, var_5, var_whatever);
+  type t_byte_array is array (natural range <>) of std_logic_vector(7 downto 0);
+
+  type t_var_record is record
+    var          : t_var;                           -- 32 bits
+    a            : t_byte_array (3 downto 0);       -- 4*8 bits
+    hexvalue     : std_logic_vector (7 downto 0);   -- 8 bits
+  end record;                                       -- total 72 bits
+
+  type t_var_array is array (natural range <>) of t_var_record;
+
+  constant c_vars_array : t_var_array(0 to 3) := (
+     0 => (var      => var_presence,
+           hexvalue => x"14",
+           a        => (0 => x"aa", 1 => x"ab", 2 => x"ac", 3 => x"ad")),
+     1 => (var      => var_identif,
+           hexvalue => x"24",
+           a        => (0 => x"ba", 1 => x"bb", 2 => x"bc", 3 => x"bd")),
+     2 => (var      => var_1,
+           hexvalue => x"34",
+           a        => (0 => x"ca", 1 => x"cb", 2 => x"cc", 3 => x"cd")),
+     3 => (var      => var_2,
+           hexvalue => x"56",
+           a        => (0 => x"da", 1 => x"db", 2 => x"dc", 3 => x"dd"))
+  );
+
+  constant c_record : t_var_record := (
+    var      => var_4,
+    hexvalue => x"66",
+    a        => (0 => x"00", 1 => x"11", 2 => x"22", 3 => x"33")
+  );
+  signal sig : std_logic_vector(7 downto 0);
+  signal sig2 : std_logic_vector(7 downto 0);
+begin
+  sig <= c_record.hexvalue;
+
+  process(sel)
+  begin
+      sig2 <= c_record.a(sel);
+      hex <= c_vars_array(sel).hexvalue;
+      aval <= c_vars_array(sel).a(sel);
+  end process;
+end architecture test;

steveicarus_ivtest/ivltests/vhdl_delay_assign.v

@@ -0,0 +1,59 @@
+// Copyright (c) 2016 CERN
+// Maciej Suminski <maciej.suminski@cern.ch>
+//
+// This source code is free software; you can redistribute it
+// and/or modify it in source code form under the terms of the GNU
+// General Public License as published by the Free Software
+// Foundation; either version 2 of the License, or (at your option)
+// any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the Free Software
+// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+
+
+// Test for delayed assignment statements.
+
+module vhdl_delay_assign_test;
+logic a, b, c;
+int passed = 0;
+vhdl_delay_assign dut(a, b, c);
+
+always @(b)
+begin
+    if($time == 10) begin
+        passed = passed + 1;
+    end else begin
+        $display("FAILED 1");
+        $finish();
+    end
+end
+
+always @(c)
+begin
+    if($time == 10) begin
+        passed = passed + 1;
+    end else begin
+        $display("FAILED 2");
+        $finish();
+    end
+end
+
+initial begin
+    a = 1;
+    #11;
+
+    if(passed !== 2) begin
+        $display("FAILED 3");
+        $finish();
+    end
+
+    $display("PASSED");
+end
+
+endmodule

steveicarus_ivtest/ivltests/vhdl_delay_assign.vhd

@@ -0,0 +1,38 @@
+-- Copyright (c) 2016 CERN
+-- Maciej Suminski <maciej.suminski@cern.ch>
+--
+-- This source code is free software; you can redistribute it
+-- and/or modify it in source code form under the terms of the GNU
+-- General Public License as published by the Free Software
+-- Foundation; either version 2 of the License, or (at your option)
+-- any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+
+
+-- Test for delayed assignment statements.
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity vhdl_delay_assign is
+    port(a : in std_logic;
+         b, c : out std_logic);
+end vhdl_delay_assign;
+
+architecture test of vhdl_delay_assign is
+begin
+    b <= a after 10 ns;
+
+    process(a)
+    begin
+        c <= a after 10 ns;
+    end process;
+end test;

steveicarus_ivtest/ivltests/vhdl_elab_range.v

@@ -0,0 +1,42 @@
+// Copyright (c) 2016 CERN
+// Maciej Suminski <maciej.suminski@cern.ch>
+//
+// This source code is free software; you can redistribute it
+// and/or modify it in source code form under the terms of the GNU
+// General Public License as published by the Free Software
+// Foundation; either version 2 of the License, or (at your option)
+// any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the Free Software
+// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+
+
+// Bug report test (could not elaborate a function used to specify a range).
+
+module vhdl_elab_range_test;
+integer left, right;
+vhdl_elab_range dut(left, right);
+
+initial begin
+    #1;
+
+    if(left !== 2) begin
+        $display("FAILED 1");
+        $finish();
+    end
+
+    if(right !== 0) begin
+        $display("FAILED 2");
+        $finish();
+    end
+
+    $display("PASSED");
+end
+
+endmodule

steveicarus_ivtest/ivltests/vhdl_elab_range.vhd

@@ -0,0 +1,44 @@
+-- Copyright (c) 2016 CERN
+-- Maciej Suminski <maciej.suminski@cern.ch>
+--
+-- This source code is free software; you can redistribute it
+-- and/or modify it in source code form under the terms of the GNU
+-- General Public License as published by the Free Software
+-- Foundation; either version 2 of the License, or (at your option)
+-- any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+
+
+-- Bug report test (could not elaborate a function used to specify a range).
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity vhdl_elab_range is
+    port(sig_left, sig_right : out integer);
+end entity vhdl_elab_range;
+
+architecture test of vhdl_elab_range is
+    function inc_by_two(a : in integer) return integer is
+    begin
+        return a + 2;
+    end function inc_by_two;
+
+  signal test_sig : unsigned(inc_by_two(0) downto 0) := (others => '0');
+begin
+  process
+  begin
+      sig_left <= test_sig'left;
+      sig_right <= test_sig'right;
+      wait;
+  end process;
+end architecture test;

steveicarus_ivtest/ivltests/vhdl_eval_cond.v

@@ -0,0 +1,35 @@
+// Copyright (c) 2016 CERN
+// Maciej Suminski <maciej.suminski@cern.ch>
+//
+// This source code is free software; you can redistribute it
+// and/or modify it in source code form under the terms of the GNU
+// General Public License as published by the Free Software
+// Foundation; either version 2 of the License, or (at your option)
+// any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the Free Software
+// Foundation, Inc., 59 Temple Place / Suite 330, Boston, MA 02111/1307, USA
+
+
+// Test initial conditional assignment evaluation
+
+module vhdl_eval_cond_test;
+logic in, out;
+vhdl_eval_cond dut(in, out);
+
+assign in = 1;
+
+initial begin
+    if(out === 1'b0)
+        $display("PASSED");
+    else
+        $display("FAILED");
+end
+
+endmodule

steveicarus_ivtest/ivltests/vhdl_eval_cond.vhd

@@ -0,0 +1,37 @@
+-- Copyright (c) 2016 CERN
+-- Maciej Suminski <maciej.suminski@cern.ch>
+--
+-- This source code is free software; you can redistribute it
+-- and-or modify it in source code form under the terms of the GNU
+-- General Public License as published by the Free Software
+-- Foundation; either version 2 of the License, or (at your option)
+-- any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+
+
+-- Test initial conditional assignment evaluation
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity vhdl_eval_cond is
+    port(
+        input : in std_logic;
+        output : out std_logic
+    );
+end vhdl_eval_cond;
+
+architecture rtl of vhdl_eval_cond is
+
+begin
+    output <= '1' when input = '0' else '0';
+end rtl;
+

steveicarus_ivtest/ivltests/vhdl_expr1.v

@@ -0,0 +1,22 @@
+module main;
+
+   wire [3:0] a, b;
+   wire [3:0] out;
+
+   subtract dut (.a(a), .b(b), .out_sig(out));
+
+   reg [8:0]  test_vector;
+   assign {a, b} = test_vector;
+
+   initial begin
+      for (test_vector=0 ; test_vector[8]==0 ; test_vector=test_vector+1) begin
+	 #1 if (out != a-b) begin
+	    $display("FAILED -- out=%b, expecting %b-%b=%b", out, a, b, a-b);
+	    $finish;
+	 end
+      end
+
+      $display("PASSED");
+      $finish;
+   end // initial begin
+endmodule // main

steveicarus_ivtest/ivltests/vhdl_expr1.vhd

@@ -0,0 +1,19 @@
+-- This VHDL was converted from Verilog using the
+-- Icarus Verilog VHDL Code Generator 0.10.0 (devel) (s20090923-519-g6ce96cc)
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity subtract is
+  port (
+    a : in unsigned(3 downto 0);
+    b : in unsigned(3 downto 0);
+    out_sig : out unsigned(3 downto 0)
+  );
+end entity;
+
+architecture test of subtract is
+begin
+  out_sig <= (a + not b) + 1;
+end architecture;

steveicarus_ivtest/ivltests/vhdl_fa4_test1.v

@@ -0,0 +1,31 @@
+/*
+ * This module instantiates the fa4 entity, which in turn
+ * instantiates other entities. This demonstrates hierarchical
+ * constructs in VHDL.
+ */
+module test;
+
+reg [3:0] a, b;
+reg cin;
+
+wire [3:0] s;
+wire cout;
+
+initial begin
+  cin = 0;
+  a = 4'h2;
+  b = 4'h3;
+end
+
+initial begin
+  #1;
+  if (s !== 4'h5) begin
+     $display("Error in trivial sum");
+     $finish;
+   end
+   $display ("PASSED");
+end
+
+fa4 duv (.c_i(cin), .va_i(a), .vb_i(b), .vs_o(s), .c_o(cout) );
+
+endmodule // test

steveicarus_ivtest/ivltests/vhdl_fa4_test1.vhd

@@ -0,0 +1,80 @@
+library ieee;
+use ieee.numeric_bit.all;
+
+-- Declare a 1-bit full-adder.
+entity fa1 is
+  port (a_i, b_i, c_i: in bit;
+        s_o, c_o: out bit
+        );
+end entity fa1;
+
+architecture fa1_rtl of fa1 is
+begin
+
+  s_o <= a_i xor b_i xor c_i;
+  c_o <= (a_i and b_i) or (c_i and (a_i xor b_i));
+
+end architecture fa1_rtl;
+
+-- Declare and implement a 4-bit full-adder that uses the
+-- 1-bit full-adder described above.
+entity fa4 is
+  port (va_i, vb_i: in bit_vector (3 downto 0);
+        c_i: in bit;
+        vs_o: out bit_vector (3 downto 0);
+        c_o: out bit
+        );
+end entity fa4;
+
+architecture fa4_rtl of fa4 is
+
+  -- full 1-bit adder
+  component fa1 is
+    port (a_i, b_i, c_i: in bit;
+          s_o, c_o: out bit);
+  end component fa1;
+
+  -- internal carry signals propagation
+  signal c_int4, c_int3, c_int2, c_int1, c_int0: bit;
+
+  begin
+
+    -- carry in
+    c_int0 <= c_i;
+
+    -- slice 0
+    s0: fa1 port map (c_i => c_int0,
+                      a_i => va_i(0),
+                      b_i => vb_i(0),
+                      s_o => vs_o(0),
+                      c_o => c_int1
+                      );
+
+    -- slice 1
+    s1: fa1 port map (c_i => c_int1,
+                      a_i => va_i(1),
+                      b_i => vb_i(1),
+                      s_o => vs_o(1),
+                      c_o => c_int2
+                      );
+
+    -- slice 2
+    s2: fa1 port map (c_i => c_int2,
+                      a_i => va_i(2),
+                      b_i => vb_i(2),
+                      s_o => vs_o(2),
+                      c_o => c_int3
+                      );
+
+    -- slice 3
+    s3: fa1 port map (c_i => c_int3,
+                      a_i => va_i(3),
+                      b_i => vb_i(3),
+                      s_o => vs_o(3),
+                      c_o => c_int4
+                      );
+
+    -- carry out
+    c_o <= c_int4;
+
+end architecture fa4_rtl;

steveicarus_ivtest/ivltests/vhdl_fa4_test2.v

@@ -0,0 +1,31 @@
+/*
+ * This module instantiates the fa4 entity, which in turn
+ * instantiates other entities. This demonstrates hierarchical
+ * constructs in VHDL.
+ */
+module test;
+
+reg [3:0] a, b;
+reg cin;
+
+wire [3:0] s;
+wire cout;
+
+initial begin
+  cin = 0;
+  a = 4'h2;
+  b = 4'h3;
+end
+
+initial begin
+  #1;
+  if (s !== 4'h5) begin
+     $display("Error in trivial sum");
+     $finish;
+   end
+   $display ("PASSED");
+end
+
+fa4 duv (.c_i(cin), .va_i(a), .vb_i(b), .vs_o(s), .c_o(cout) );
+
+endmodule // test

steveicarus_ivtest/ivltests/vhdl_fa4_test2.vhd

@@ -0,0 +1,80 @@
+library ieee;
+use ieee.numeric_bit.all;
+
+-- Declare a 1-bit full-adder.
+entity fa1 is
+  port (a_i, b_i, c_i: in bit;
+        s_o, c_o: out bit
+        );
+end entity fa1;
+
+architecture fa1_rtl of fa1 is
+begin
+
+  s_o <= a_i xor b_i xor c_i;
+  c_o <= (a_i and b_i) or (c_i and (a_i xor b_i));
+
+end architecture fa1_rtl;
+
+-- Declare and implement a 4-bit full-adder that uses the
+-- 1-bit full-adder described above.
+entity fa4 is
+  port (va_i, vb_i: in bit_vector (3 downto 0);
+        c_i: in bit;
+        vs_o: out bit_vector (3 downto 0);
+        c_o: out bit
+        );
+end entity fa4;
+
+architecture fa4_rtl of fa4 is
+
+  -- full 1-bit adder
+  component fa1 is
+    port (a_i, b_i, c_i: in bit;
+          s_o, c_o: out bit);
+  end component fa1;
+
+  -- internal carry signals propagation
+  signal c_int: bit_vector (4 downto 0);
+
+  begin
+
+    -- carry in
+    c_int(0) <= c_i;
+
+    -- slice 0
+    s0: fa1 port map (c_i => c_int(0),
+                      a_i => va_i(0),
+                      b_i => vb_i(0),
+                      s_o => vs_o(0),
+                      c_o => c_int(1)
+                      );
+
+    -- slice 1
+    s1: fa1 port map (c_i => c_int(1),
+                      a_i => va_i(1),
+                      b_i => vb_i(1),
+                      s_o => vs_o(1),
+                      c_o => c_int(2)
+                      );
+
+    -- slice 2
+    s2: fa1 port map (c_i => c_int(2),
+                      a_i => va_i(2),
+                      b_i => vb_i(2),
+                      s_o => vs_o(2),
+                      c_o => c_int(3)
+                      );
+
+    -- slice 3
+    s3: fa1 port map (c_i => c_int(3),
+                      a_i => va_i(3),
+                      b_i => vb_i(3),
+                      s_o => vs_o(3),
+                      c_o => c_int(4)
+                      );
+
+    -- carry out
+    c_o <= c_int(4);
+
+end architecture fa4_rtl;

steveicarus_ivtest/ivltests/vhdl_fa4_test3.v

@@ -0,0 +1,31 @@
+/*
+ * This module instantiates the fa4 entity, which in turn
+ * instantiates other entities. This demonstrates hierarchical
+ * constructs in VHDL.
+ */
+module test;
+
+reg [3:0] a, b;
+reg cin;
+
+wire [3:0] s;
+wire cout;
+
+initial begin
+  cin = 0;
+  a = 4'h2;
+  b = 4'h3;
+end
+
+initial begin
+  #1;
+  if (s !== 4'h5) begin
+     $display("Error in trivial sum");
+     $finish;
+   end
+   $display ("PASSED");
+end
+
+fa4 duv (.c_i(cin), .va_i(a), .vb_i(b), .vs_o(s), .c_o(cout) );
+
+endmodule // test

steveicarus_ivtest/ivltests/vhdl_fa4_test3.vhd

@@ -0,0 +1,85 @@
+-- In this test, we declare a component in the "gates" package
+-- and show that it can be referenced within the package namespace.
+
+library ieee;
+use ieee.numeric_bit.all;
+
+package gates is
+  -- full 1-bit adder
+  component fa1 is
+    port (a_i, b_i, c_i: in bit;
+          s_o, c_o: out bit);
+  end component fa1;
+end package gates;
+
+-- Declare and implement a 4-bit full-adder that uses the
+-- 1-bit full-adder described above.
+entity fa4 is
+  port (va_i, vb_i: in bit_vector (3 downto 0);
+        c_i: in bit;
+        vs_o: out bit_vector (3 downto 0);
+        c_o: out bit
+        );
+end entity fa4;
+
+architecture fa4_rtl of fa4 is
+
+  use work.gates.fa1;
+
+  -- internal carry signals propagation
+  signal c_int: bit_vector (4 downto 0);
+
+  begin
+
+    -- carry in
+    c_int(0) <= c_i;
+
+    -- slice 0
+    s0: fa1 port map (c_i => c_int(0),
+                      a_i => va_i(0),
+                      b_i => vb_i(0),
+                      s_o => vs_o(0),
+                      c_o => c_int(1)
+                      );
+
+    -- slice 1
+    s1: fa1 port map (c_i => c_int(1),
+                      a_i => va_i(1),
+                      b_i => vb_i(1),
+                      s_o => vs_o(1),
+                      c_o => c_int(2)
+                      );
+
+    -- slice 2
+    s2: fa1 port map (c_i => c_int(2),
+                      a_i => va_i(2),
+                      b_i => vb_i(2),
+                      s_o => vs_o(2),
+                      c_o => c_int(3)
+                      );
+
+    -- slice 3
+    s3: fa1 port map (c_i => c_int(3),
+                      a_i => va_i(3),
+                      b_i => vb_i(3),
+                      s_o => vs_o(3),
+                      c_o => c_int(4)
+                      );
+
+    -- carry out
+    c_o <= c_int(4);
+
+end architecture fa4_rtl;
+
+-- Declare a 1-bit full-adder.
+entity fa1 is
+  port (a_i, b_i, c_i: in bit;
+        s_o, c_o: out bit
+        );
+end entity fa1;
+
+architecture fa1_rtl of fa1 is
+begin
+  s_o <= a_i xor b_i xor c_i;
+  c_o <= (a_i and b_i) or (c_i and (a_i xor b_i));
+end architecture fa1_rtl;

steveicarus_ivtest/ivltests/vhdl_fa4_test4.v

@@ -0,0 +1,31 @@
+/*
+ * This module instantiates the fa4 entity, which in turn
+ * instantiates other entities. This demonstrates hierarchical
+ * constructs in VHDL.
+ */
+module test;
+
+reg [3:0] a, b;
+reg cin;
+
+wire [3:0] s;
+wire cout;
+
+initial begin
+  cin = 0;
+  a = 4'h2;
+  b = 4'h3;
+end
+
+initial begin
+  #1;
+  if (s !== 4'h5) begin
+     $display("Error in trivial sum");
+     $finish;
+   end
+   $display ("PASSED");
+end
+
+fa4 duv (.c_i(cin), .va_i(a), .vb_i(b), .vs_o(s), .c_o(cout) );
+
+endmodule // test

steveicarus_ivtest/ivltests/vhdl_fa4_test4.vhd

@@ -0,0 +1,102 @@
+-- In this test, we declare a component in the "mypackage" package
+-- and show that it can be referenced within the package namespace.
+-- it also shows the usage of subtypes, constants and signals
+-- expressed in terms of defined subtypes
+
+library ieee;
+use ieee.numeric_bit.all;
+
+package mypackage is
+
+  -- trivial sub type
+  subtype Myrange_t is integer range 0 to 4;
+
+  -- some constants
+  constant ZERO: Myrange_t := 0;
+  constant ONE: Myrange_t := 1;
+  constant TWO: Myrange_t := 2;
+  constant THREE: Myrange_t := 3;
+  constant FOUR: Myrange_t := 4;
+
+  -- another subtype
+  subtype AdderWidth_t is bit_vector (THREE downto ZERO);
+  subtype CarryWidth_t is bit_vector (THREE+1 downto ZERO);
+
+  -- full 1-bit adder
+  component fa1 is
+    port (a_i, b_i, c_i: in bit;
+          s_o, c_o: out bit);
+  end component fa1;
+end package mypackage;
+
+-- Declare and implement a 4-bit full-adder that uses the
+-- 1-bit full-adder described above.
+
+use work.mypackage.all;
+entity fa4 is
+  port (va_i, vb_i: in AdderWidth_t;
+        c_i: in bit;
+        vs_o: out AdderWidth_t;
+        c_o: out bit
+        );
+end entity fa4;
+
+architecture fa4_rtl of fa4 is
+
+-- auxiliary signal for carry
+signal c_int: CarryWidth_t;
+
+begin
+
+    -- carry in
+    c_int(ZERO) <= c_i;
+
+    -- slice 0
+    s0: fa1 port map (c_i => c_int(ZERO),
+                      a_i => va_i(ZERO),
+                      b_i => vb_i(ZERO),
+                      s_o => vs_o(ZERO),
+                      c_o => c_int(ONE)
+                      );
+
+    -- slice 1
+    s1: fa1 port map (c_i => c_int(ONE),
+                      a_i => va_i(ONE),
+                      b_i => vb_i(ONE),
+                      s_o => vs_o(ONE),
+                      c_o => c_int(TWO)
+                      );
+
+    -- slice 2
+    s2: fa1 port map (c_i => c_int(TWO),
+                      a_i => va_i(TWO),
+                      b_i => vb_i(TWO),
+                      s_o => vs_o(TWO),
+                      c_o => c_int(THREE)
+                      );
+
+    -- slice 3
+    s3: fa1 port map (c_i => c_int(THREE),
+                      a_i => va_i(THREE),
+                      b_i => vb_i(THREE),
+                      s_o => vs_o(THREE),
+                      c_o => c_int(FOUR)
+                      );
+
+    -- carry out
+    c_o <= c_int(FOUR);
+
+end architecture fa4_rtl;
+
+-- Declare a 1-bit full-adder.
+entity fa1 is
+  port (a_i, b_i, c_i: in bit;
+        s_o, c_o: out bit
+        );
+end entity fa1;
+
+architecture fa1_rtl of fa1 is
+begin
+  s_o <= a_i xor b_i xor c_i;
+  c_o <= (a_i and b_i) or (c_i and (a_i xor b_i));
+end architecture fa1_rtl;

steveicarus_ivtest/ivltests/vhdl_file_open.v

@@ -0,0 +1,36 @@
+// Copyright (c) 2016 CERN
+// Maciej Suminski <maciej.suminski@cern.ch>
+//
+// This source code is free software; you can redistribute it
+// and/or modify it in source code form under the terms of the GNU
+// General Public License as published by the Free Software
+// Foundation; either version 2 of the License, or (at your option)
+// any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the Free Software
+// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+
+
+// Test file_open() function.
+
+module file_open_test;
+logic active, ok;
+vhdl_file_open dut(active, ok);
+
+initial begin
+    active = 1;
+    #1;
+    if(ok !== 1'b1) begin
+        $display("FAILED");
+        $finish();
+    end
+
+    $display("PASSED");
+end
+endmodule

steveicarus_ivtest/ivltests/vhdl_file_open.vhd

@@ -0,0 +1,50 @@
+-- Copyright (c) 2016 CERN
+-- Maciej Suminski <maciej.suminski@cern.ch>
+--
+-- This source code is free software; you can redistribute it
+-- and/or modify it in source code form under the terms of the GNU
+-- General Public License as published by the Free Software
+-- Foundation; either version 2 of the License, or (at your option)
+-- any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+
+
+-- Test file_open() function.
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use std.textio.all;
+
+entity vhdl_file_open is
+    port(active : in std_logic;
+         ok : out std_logic);
+end vhdl_file_open;
+
+architecture test of vhdl_file_open is
+begin
+    process(active)
+        file ok_file, bad_file : text;
+        variable ok_status, bad_status : FILE_OPEN_STATUS;
+    begin
+        if rising_edge(active) then
+            file_open(ok_status, ok_file, "ivltests/vhdl_file_open.vhd", read_mode);
+            file_open(bad_status, bad_file, "not_existing_file", read_mode);
+
+            if ok_status = OPEN_OK and bad_status = NAME_ERROR then
+                ok := '1';
+            else
+                ok := '0';
+            end if;
+            file_close(ok_file);
+        end if;
+    end process;
+end test;

steveicarus_ivtest/ivltests/vhdl_generic_default.v

@@ -0,0 +1,33 @@
+// Copyright (c) 2015 CERN
+// Maciej Suminski <maciej.suminski@cern.ch>
+//
+// This source code is free software; you can redistribute it
+// and/or modify it in source code form under the terms of the GNU
+// General Public License as published by the Free Software
+// Foundation; either version 2 of the License, or (at your option)
+// any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the Free Software
+// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+
+
+// Test for generics without a default value.
+
+module vhdl_generic_default_test;
+logic a;
+vhdl_generic_default #(.\value (1'b1))dut(a);
+
+initial begin
+    if(a !== 1'b1) begin
+        $display("FAILED");
+        $finish();
+    end
+    $display("PASSED");
+end
+endmodule

steveicarus_ivtest/ivltests/vhdl_generic_default.vhd

@@ -0,0 +1,33 @@
+-- Copyright (c) 2015 CERN
+-- Maciej Suminski <maciej.suminski@cern.ch>
+--
+-- This source code is free software; you can redistribute it
+-- and/or modify it in source code form under the terms of the GNU
+-- General Public License as published by the Free Software
+-- Foundation; either version 2 of the License, or (at your option)
+-- any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+
+
+-- Test for generics without a default value.
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity vhdl_generic_default is
+    generic(value : std_logic);
+    port(a : out std_logic);
+end vhdl_generic_default;
+
+architecture test of vhdl_generic_default is
+begin
+    a <= value;
+end test;

steveicarus_ivtest/ivltests/vhdl_generic_eval.v

@@ -0,0 +1,38 @@
+// Copyright (c) 2015 CERN
+// Maciej Suminski <maciej.suminski@cern.ch>
+//
+// This source code is free software; you can redistribute it
+// and/or modify it in source code form under the terms of the GNU
+// General Public License as published by the Free Software
+// Foundation; either version 2 of the License, or (at your option)
+// any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the Free Software
+// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+
+
+// Test for generics evaluation.
+
+module generic_eval();
+reg [7:0] data;
+reg out_bit_def, out_bit_ovr;
+test_eval_generic dut(data, out_bit_def, out_bit_ovr);
+
+initial begin
+    data = 8'b11010010;
+    #1;
+
+    if(out_bit_def !== 1'b0 || out_bit_ovr !== 1'b1) begin
+        $display("FAILED");
+        $finish();
+    end
+
+    $display("PASSED");
+end
+endmodule

steveicarus_ivtest/ivltests/vhdl_generic_eval.vhd

@@ -0,0 +1,79 @@
+-- Copyright (c) 2015 CERN
+-- Maciej Suminski <maciej.suminski@cern.ch>
+--
+-- This source code is free software; you can redistribute it
+-- and/or modify it in source code form under the terms of the GNU
+-- General Public License as published by the Free Software
+-- Foundation; either version 2 of the License, or (at your option)
+-- any later version.
+--
+-- This program is distributed in the hope that it will be useful,
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+-- GNU General Public License for more details.
+--
+-- You should have received a copy of the GNU General Public License
+-- along with this program; if not, write to the Free Software
+-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+
+
+-- Test for generics evaluation.
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity eval_generic is
+  generic(
+        msb : integer range 1 to 7 := 7;
+        bit_select : integer range 0 to 7 := 3
+  );
+  port(
+        in_word : in std_logic_vector(msb downto 0);
+        out_bit : out std_logic
+  );
+end entity eval_generic;
+
+architecture test of eval_generic is
+begin
+    out_bit <= in_word(bit_select);
+end architecture test;
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity test_eval_generic is
+  port(
+        in_word : in std_logic_vector(7 downto 0);
+        out_bit_def, out_bit_ovr : out std_logic
+  );
+end entity test_eval_generic;
+
+architecture test of test_eval_generic is
+    constant const_int : integer := 7;
+
+    component eval_generic is
+    generic(
+          msb : integer range 1 to 7;
+          bit_select : integer range 0 to 7
+    );
+    port(
+            in_word : in std_logic_vector(msb downto 0);
+            out_bit : out std_logic
+    );
+    end component eval_generic;
+begin
+    override_test_unit: eval_generic
+    generic map(bit_select => 2,
+                msb => const_int)
+    port map(
+                in_word => (others => '1'),
+                out_bit => out_bit_ovr
+    );
+
+    default_test_unit: eval_generic
+    port map(
+                in_word => in_word,
+                out_bit => out_bit_def
+    );
+end architecture test;

steveicarus_ivtest/ivltests/vhdl_image_attr.v

@@ -0,0 +1,30 @@
+// Copyright (c) 2016 CERN
+// Maciej Suminski <maciej.suminski@cern.ch>
+//
+// This source code is free software; you can redistribute it
+// and/or modify it in source code form under the terms of the GNU
+// General Public License as published by the Free Software
+// Foundation; either version 2 of the License, or (at your option)
+// any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the Free Software
+// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
+
+
+// Test for 'image attribute in VHDL.
+
+module image_attr_test;
+logic start_test;
+image_attr_entity dut(start_test);
+
+initial begin
+    start_test = 1'b0;
+    #1 start_test = 1'b1;
+end
+endmodule