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Add Repo: ETH-PLUS_Jingzhao (part 6)

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  1. ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Common/SRAM_SDP_Template.v +295 -0
  2. ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Common/SRAM_TDP_Template.v +817 -0
  3. ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Common/SyncFIFO_2Port_Ctrl_SRAM.v +180 -0
  4. ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Common/SyncFIFO_2Port_SRAM.v +96 -0
  5. ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Common/SyncFIFO_Template.v +211 -0
  6. ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Common/slice/gp_slice.v +157 -0
  7. ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Common/slice/gp_slice_ml.v +55 -0
  8. ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Common/st_demux.v +333 -0
  9. ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Common/st_mux.v +791 -0
  10. ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Common/st_reg.v +110 -0
  11. ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Common/stream_fifo.v +101 -0
  12. ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Common/stream_reg.v +62 -0
  13. ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Common/sync_reset.v +35 -0
  14. ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/EthSubsystem/README.md +1 -0
  15. ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/DMA/DMA.v +826 -0
  16. ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/DMA/DMA_Read/dma_demux.v +347 -0
  17. ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/DMA/DMA_Read/np_tag_mgmt.v +337 -0
  18. ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/DMA/DMA_Read/read_req_rsp.v +709 -0
  19. ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/DMA/DMA_Read/read_request.v +306 -0
  20. ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/DMA/DMA_Read/read_response.v +351 -0
  21. ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/DMA/DMA_Read/reorder_buf.v +220 -0
  22. ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/DMA/DMA_Read/rrsp_dealign.v +343 -0
  23. ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/DMA/DMA_Read/rsp_data_fifo.v +222 -0
  24. ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/DMA/DMA_Read/sub_req_rsp_concat.v +363 -0
  25. ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/DMA/DMA_Read/sub_req_rsp_wrapper.v +239 -0
  26. ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/DMA/DMA_Read/sub_rsp_concat.v +485 -0
  27. ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/DMA/DMA_Read/tag_buf.v +192 -0
  28. ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/DMA/DMA_Read/tag_matching.v +199 -0
  29. ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/DMA/DMA_Read/tag_request.v +180 -0
  30. ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/DMA/DMA_Write/wreq_align.v +357 -0
  31. ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/DMA/DMA_Write/wreq_split.v +319 -0
  32. ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/DMA/DMA_Write/write_request.v +209 -0
  33. ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/DMA/int_proc.v +171 -0
  34. ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/DMA/rc_async_fifos.v +114 -0
  35. ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/DMA/req_arbiter.v +937 -0
  36. ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/DMA/req_converter.v +290 -0
  37. ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/DMA/rq_async_fifos.v +221 -0
  38. ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/DMA/rrsp_async_fifo.v +142 -0
  39. ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/DMA/rsp_converter.v +300 -0
  40. ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/P2P/P2P.v +349 -0
  41. ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/P2P/ini_dev2addr_table.v +181 -0
  42. ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/P2P/ini_dst_nic_proc.v +170 -0
  43. ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/P2P/ini_pyld_split_proc.v +48 -0
  44. ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/P2P/p2p_initiator.v +312 -0
  45. ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/P2P/p2p_target.v +601 -0
  46. ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/P2P/tgt_desc_queue.v +504 -0
  47. ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/P2P/tgt_pyld_buf.v +264 -0
  48. ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/P2P/tgt_pyld_recv_proc.v +236 -0
  49. ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/P2P/tgt_pyld_send_proc.v +247 -0
  50. ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/P2P/tgt_queue_struct.v +293 -0
ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Common/SRAM_SDP_Template.v ADDED
@@ -0,0 +1,295 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ `timescale 1ns / 1ps
2
+
3
+ `include "common_function_def.vh"
4
+
5
+ module SRAM_SDP_Template #(
6
+ parameter RAM_WIDTH = 32,
7
+ parameter RAM_DEPTH = 32,
8
+ parameter ADDR_WIDTH = log2b(RAM_DEPTH - 1)
9
+ )
10
+ (
11
+ input wire clk,
12
+ input wire rst,
13
+
14
+ input wire wea,
15
+ input wire [ADDR_WIDTH - 1 : 0] addra,
16
+ input wire [RAM_WIDTH - 1 : 0] dina,
17
+
18
+ input wire [ADDR_WIDTH - 1 : 0] addrb,
19
+ output wire [RAM_WIDTH - 1 : 0] doutb
20
+ );
21
+
22
+ //Resolve read-write collisions
23
+ reg wea_diff;
24
+ reg [ADDR_WIDTH - 1 : 0] addra_diff;
25
+ reg [RAM_WIDTH - 1 : 0] dina_diff;
26
+
27
+ reg [ADDR_WIDTH - 1 : 0] addrb_diff;
28
+ wire [RAM_WIDTH - 1 : 0] doutb_fake;
29
+
30
+ generate
31
+ if(RAM_WIDTH == 32 && RAM_DEPTH == 32) begin : GEN_BRAM_SDP_32W_32D
32
+ //Instantiate Xilinx IP
33
+ end
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+ else if(RAM_WIDTH == 129 && RAM_DEPTH == 64) begin : GEN_BRAM_SDP_129W_64D
35
+ // BRAM_SDP_129w_64d BRAM_SDP_129w_64d_inst(
36
+ // .clka (clk),
37
+ // .wea (wea),
38
+ // .addra (addra),
39
+ // .dina (dina),
40
+ // .clkb (clk),
41
+ // .addrb (addrb),
42
+ // .doutb (doutb_fake)
43
+ // );
44
+
45
+ end
46
+ else if(RAM_WIDTH == 24 && RAM_DEPTH == 16384) begin : GEN_BRAM_SDP_24W_16384D
47
+ // BRAM_SDP_24w_16384d BRAM_SDP_24w_16384d_inst(
48
+ // .clka (clk),
49
+ // .wea (wea),
50
+ // .addra (addra),
51
+ // .dina (dina),
52
+ // .clkb (clk),
53
+ // .addrb (addrb),
54
+ // .doutb (doutb_fake)
55
+ // );
56
+
57
+ end
58
+ else if(RAM_WIDTH == 52 && RAM_DEPTH == 1) begin : GEN_BRAM_SDP_52W_1D
59
+ BRAM_SDP_52w_1d BRAM_SDP_52w_1d_inst(
60
+ .clka ( clk ),
61
+ .wea ( wea ),
62
+ .addra ( addra ),
63
+ .dina ( dina ),
64
+ .clkb ( clk ),
65
+ .addrb ( addrb ),
66
+ .doutb ( doutb_fake )
67
+ );
68
+ end
69
+ else if(RAM_WIDTH == 52 && RAM_DEPTH == 512) begin : GEN_BRAM_SDP_52W_512D
70
+ BRAM_SDP_52w_512d BRAM_SDP_52w_512d_inst(
71
+ .clka ( clk ),
72
+ .wea ( wea ),
73
+ .addra ( addra ),
74
+ .dina ( dina ),
75
+ .clkb ( clk ),
76
+ .addrb ( addrb ),
77
+ .doutb ( doutb_fake )
78
+ );
79
+ end
80
+ else if(RAM_WIDTH == 52 && RAM_DEPTH == 1024) begin : GEN_BRAM_SDP_52W_1024D
81
+ BRAM_SDP_52w_1024d BRAM_SDP_52w_1024d_inst(
82
+ .clka ( clk ),
83
+ .wea ( wea ),
84
+ .addra ( addra ),
85
+ .dina ( dina ),
86
+ .clkb ( clk ),
87
+ .addrb ( addrb ),
88
+ .doutb ( doutb_fake )
89
+ );
90
+ end
91
+ else if(RAM_WIDTH == 52 && RAM_DEPTH == 8192) begin : GEN_BRAM_SDP_52W_8192D
92
+ BRAM_SDP_52w_8192d BRAM_SDP_52w_8192d_inst(
93
+ .clka ( clk ),
94
+ .wea ( wea ),
95
+ .addra ( addra ),
96
+ .dina ( dina ),
97
+ .clkb ( clk ),
98
+ .addrb ( addrb ),
99
+ .doutb ( doutb_fake )
100
+ );
101
+ end
102
+ else if(RAM_WIDTH == 128 && RAM_DEPTH == 1024) begin : GEN_BRAM_SDP_128W_1024D
103
+ BRAM_SDP_128w_1024d BRAM_SDP_128w_1024d_inst(
104
+ .clka ( clk ),
105
+ .wea ( wea ),
106
+ .addra ( addra ),
107
+ .dina ( dina ),
108
+ .clkb ( clk ),
109
+ .addrb ( addrb ),
110
+ .doutb ( doutb_fake )
111
+ );
112
+ end
113
+ else if(RAM_WIDTH == 128 && RAM_DEPTH == 32768) begin : GEN_BRAM_SDP_128W_32768D
114
+ BRAM_SDP_128w_32768d BRAM_SDP_128w_32768d_inst(
115
+ .clka ( clk ),
116
+ .wea ( wea ),
117
+ .addra ( addra ),
118
+ .dina ( dina ),
119
+ .clkb ( clk ),
120
+ .addrb ( addrb ),
121
+ .doutb ( doutb_fake )
122
+ );
123
+ end
124
+ else if(RAM_WIDTH == 1 && RAM_DEPTH == 256) begin : GEN_BRAM_SDP_1W_256D
125
+ BRAM_SDP_1w_256d BRAM_SDP_1w_256d_inst(
126
+ .clka ( clk ),
127
+ .wea ( wea ),
128
+ .addra ( addra ),
129
+ .dina ( dina ),
130
+ .clkb ( clk ),
131
+ .addrb ( addrb ),
132
+ .doutb ( doutb_fake )
133
+ );
134
+ end
135
+ else if(RAM_WIDTH == 8 && RAM_DEPTH == 32) begin : GEN_BRAM_SDP_8W_32D
136
+ BRAM_SDP_8w_32d BRAM_SDP_8w_32d_inst(
137
+ .clka ( clk ),
138
+ .wea ( wea ),
139
+ .addra ( addra ),
140
+ .dina ( dina ),
141
+ .clkb ( clk ),
142
+ .addrb ( addrb ),
143
+ .doutb ( doutb_fake )
144
+ );
145
+ end
146
+ else if(RAM_WIDTH == 8 && RAM_DEPTH == 128) begin : GEN_BRAM_SDP_8W_128D
147
+ BRAM_SDP_8w_128d BRAM_SDP_8w_128d_inst(
148
+ .clka ( clk ),
149
+ .wea ( wea ),
150
+ .addra ( addra ),
151
+ .dina ( dina ),
152
+ .clkb ( clk ),
153
+ .addrb ( addrb ),
154
+ .doutb ( doutb_fake )
155
+ );
156
+ end
157
+ else if(RAM_WIDTH == 32 && RAM_DEPTH == 256) begin : GEN_BRAM_SDP_32W_256D
158
+ BRAM_SDP_32w_256d BRAM_SDP_32w_256d_inst(
159
+ .clka ( clk ),
160
+ .wea ( wea ),
161
+ .addra ( addra ),
162
+ .dina ( dina ),
163
+ .clkb ( clk ),
164
+ .addrb ( addrb ),
165
+ .doutb ( doutb_fake )
166
+ );
167
+ end
168
+ else if(RAM_WIDTH == 416 && RAM_DEPTH == 32) begin : GEN_BRAM_SDP_416W_32D
169
+ BRAM_SDP_416w_32d BRAM_SDP_416w_32d_inst(
170
+ .clka ( clk ),
171
+ .wea ( wea ),
172
+ .addra ( addra ),
173
+ .dina ( dina ),
174
+ .clkb ( clk ),
175
+ .addrb ( addrb ),
176
+ .doutb ( doutb_fake )
177
+ );
178
+ end
179
+ else if(RAM_WIDTH == 128 && RAM_DEPTH == 32) begin : GEN_BRAM_SDP_128W_32D
180
+ BRAM_SDP_128w_32d BRAM_SDP_128w_32d_inst(
181
+ .clka ( clk ),
182
+ .wea ( wea ),
183
+ .addra ( addra ),
184
+ .dina ( dina ),
185
+ .clkb ( clk ),
186
+ .addrb ( addrb ),
187
+ .doutb ( doutb_fake )
188
+ );
189
+ end
190
+ else if(RAM_WIDTH == 641 && RAM_DEPTH == 32) begin : GEN_BRAM_SDP_641W_32D
191
+ BRAM_SDP_641w_32d BRAM_SDP_641w_32d_inst(
192
+ .clka ( clk ),
193
+ .wea ( wea ),
194
+ .addra ( addra ),
195
+ .dina ( dina ),
196
+ .clkb ( clk ),
197
+ .addrb ( addrb ),
198
+ .doutb ( doutb_fake )
199
+ );
200
+ end
201
+ else if(RAM_WIDTH == 161 && RAM_DEPTH == 32) begin : GEN_BRAM_SDP_161W_32D
202
+ BRAM_SDP_161w_32d BRAM_SDP_161w_32d_inst(
203
+ .clka ( clk ),
204
+ .wea ( wea ),
205
+ .addra ( addra ),
206
+ .dina ( dina ),
207
+ .clkb ( clk ),
208
+ .addrb ( addrb ),
209
+ .doutb ( doutb_fake )
210
+ );
211
+ end
212
+ else if(RAM_WIDTH == 225 && RAM_DEPTH == 32) begin : GEN_BRAM_SDP_225W_32D
213
+ BRAM_SDP_225w_32d BRAM_SDP_225w_32d_inst(
214
+ .clka ( clk ),
215
+ .wea ( wea ),
216
+ .addra ( addra ),
217
+ .dina ( dina ),
218
+ .clkb ( clk ),
219
+ .addrb ( addrb ),
220
+ .doutb ( doutb_fake )
221
+ );
222
+ end
223
+ else if(RAM_WIDTH == 24 && RAM_DEPTH == 256) begin : GEN_BRAM_SDP_24W_256D
224
+ BRAM_SDP_24w_256d BRAM_SDP_24w_256d_inst(
225
+ .clka ( clk ),
226
+ .wea ( wea ),
227
+ .addra ( addra ),
228
+ .dina ( dina ),
229
+ .clkb ( clk ),
230
+ .addrb ( addrb ),
231
+ .doutb ( doutb_fake )
232
+ );
233
+ end
234
+ else if(RAM_WIDTH == 416 && RAM_DEPTH == 256) begin : GEN_BRAM_SDP_416W_256D
235
+ BRAM_SDP_416w_256d BRAM_SDP_416w_256d_inst(
236
+ .clka ( clk ),
237
+ .wea ( wea ),
238
+ .addra ( addra ),
239
+ .dina ( dina ),
240
+ .clkb ( clk ),
241
+ .addrb ( addrb ),
242
+ .doutb ( doutb_fake )
243
+ );
244
+ end
245
+ else if(RAM_WIDTH == 8 && RAM_DEPTH == 256) begin : GEN_BRAM_SDP_8W_256D
246
+ BRAM_SDP_8w_256d BRAM_SDP_8w_256d_inst(
247
+ .clka ( clk ),
248
+ .wea ( wea ),
249
+ .addra ( addra ),
250
+ .dina ( dina ),
251
+ .clkb ( clk ),
252
+ .addrb ( addrb ),
253
+ .doutb ( doutb_fake )
254
+ );
255
+ end
256
+ else if(RAM_WIDTH == 128 && RAM_DEPTH == 256) begin : GEN_BRAM_SDP_128W_256D
257
+ BRAM_SDP_128w_256d BRAM_SDP_128w_256d_inst(
258
+ .clka ( clk ),
259
+ .wea ( wea ),
260
+ .addra ( addra ),
261
+ .dina ( dina ),
262
+ .clkb ( clk ),
263
+ .addrb ( addrb ),
264
+ .doutb ( doutb_fake )
265
+ );
266
+ end
267
+ endgenerate
268
+
269
+ always @(posedge clk or posedge rst) begin
270
+ if(rst) begin
271
+ wea_diff <= 'd0;
272
+ addra_diff <= 'd0;
273
+ dina_diff <= 'd0;
274
+
275
+ addrb_diff <= 'd0;
276
+ end
277
+ else begin
278
+ wea_diff <= wea;
279
+ addra_diff <= addra;
280
+ dina_diff <= dina;
281
+
282
+ addrb_diff <= addrb;
283
+ end
284
+ end
285
+
286
+ assign doutb = (wea_diff && (addra_diff == addrb_diff)) ? dina_diff : doutb_fake;
287
+
288
+ /*Debug subsystem : Begin*/
289
+ `ifdef DEBUG_ON
290
+
291
+ `endif
292
+ /*Debug subsystem : End*/
293
+
294
+
295
+ endmodule
ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Common/SRAM_TDP_Template.v ADDED
@@ -0,0 +1,817 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ `timescale 1ns / 1ps
2
+
3
+ `include "common_function_def.vh"
4
+
5
+ module SRAM_TDP_Template #(
6
+ parameter RAM_WIDTH = 32,
7
+ parameter RAM_DEPTH = 32,
8
+ parameter ADDR_WIDTH = log2b(RAM_DEPTH - 1)
9
+ )
10
+ (
11
+ input wire clk,
12
+ input wire rst,
13
+
14
+ input wire wea,
15
+ input wire [ADDR_WIDTH - 1 : 0] addra,
16
+ input wire [RAM_WIDTH - 1 : 0] dina,
17
+ output wire [RAM_WIDTH - 1 : 0] douta,
18
+
19
+ input wire web,
20
+ input wire [ADDR_WIDTH - 1 : 0] addrb,
21
+ input wire [RAM_WIDTH - 1 : 0] dinb,
22
+ output wire [RAM_WIDTH - 1 : 0] doutb
23
+ );
24
+
25
+ wire [RAM_WIDTH - 1 : 0] douta_fake;
26
+ wire [RAM_WIDTH - 1 : 0] doutb_fake;
27
+
28
+ generate
29
+ if(RAM_WIDTH == 1 && RAM_DEPTH == 4096) begin : GEN_BRAM_TDP_1W_4096D
30
+ BRAM_TDP_1w_4096d BRAM_TDP_1w_4096d_Inst(
31
+ .clka ( clk ),
32
+ .rsta ( rst ),
33
+ .wea ( wea ),
34
+ .addra ( addra ),
35
+ .dina ( dina ),
36
+ .douta ( douta_fake ),
37
+ .clkb ( clk ),
38
+ .rstb ( rst ),
39
+ .web ( web ),
40
+ .addrb ( addrb ),
41
+ .dinb ( dinb ),
42
+ .doutb ( doutb_fake )
43
+ );
44
+ end
45
+ else if(RAM_WIDTH == 76 && RAM_DEPTH == 4096) begin : GEN_BRAM_TDP_76W_4096D
46
+ BRAM_TDP_76w_4096d BRAM_TDP_76w_4096d_Inst(
47
+ .clka ( clk ),
48
+ .rsta ( rst ),
49
+ .wea ( wea ),
50
+ .addra ( addra ),
51
+ .dina ( dina ),
52
+ .douta ( douta_fake ),
53
+ .clkb ( clk ),
54
+ .rstb ( rst ),
55
+ .web ( web ),
56
+ .addrb ( addrb ),
57
+ .dinb ( dinb ),
58
+ .doutb ( doutb_fake )
59
+ );
60
+ end
61
+ else if(RAM_WIDTH == 87 && RAM_DEPTH == 2) begin : GEN_BRAM_TDP_87W_2D //Test cache miss case, MTT CACHE_SET_NUM = 2
62
+ BRAM_TDP_87w_2d BRAM_TDP_87w_2d_Inst(
63
+ .clka ( clk ),
64
+ .rsta ( rst ),
65
+ .wea ( wea ),
66
+ .addra ( addra ),
67
+ .dina ( dina ),
68
+ .douta ( douta_fake ),
69
+ .clkb ( clk ),
70
+ .rstb ( rst ),
71
+ .web ( web ),
72
+ .addrb ( addrb ),
73
+ .dinb ( dinb ),
74
+ .doutb ( doutb_fake )
75
+ );
76
+ end
77
+ else if(RAM_WIDTH == 340 && RAM_DEPTH == 2) begin : GEN_BRAM_TDP_340W_2D //Test cache miss case, MPT CACHE_SET_NUM = 2
78
+ BRAM_TDP_340w_2d BRAM_TDP_340w_2d_Inst(
79
+ .clka ( clk ),
80
+ .rsta ( rst ),
81
+ .wea ( wea ),
82
+ .addra ( addra ),
83
+ .dina ( dina ),
84
+ .douta ( douta_fake ),
85
+ .clkb ( clk ),
86
+ .rstb ( rst ),
87
+ .web ( web ),
88
+ .addrb ( addrb ),
89
+ .dinb ( dinb ),
90
+ .doutb ( doutb_fake )
91
+ );
92
+ end
93
+ else if(RAM_WIDTH == 143 && RAM_DEPTH == 2) begin : GEN_BRAM_TDP_143W_2D //Test cache miss case, CQC CACHE_SET_NUM = 2
94
+ BRAM_TDP_143w_2d BRAM_TDP_143w_2d_Inst(
95
+ .clka ( clk ),
96
+ .rsta ( rst ),
97
+ .wea ( wea ),
98
+ .addra ( addra ),
99
+ .dina ( dina ),
100
+ .douta ( douta_fake ),
101
+ .clkb ( clk ),
102
+ .rstb ( rst ),
103
+ .web ( web ),
104
+ .addrb ( addrb ),
105
+ .dinb ( dinb ),
106
+ .doutb ( doutb_fake )
107
+ );
108
+ end
109
+ else if(RAM_WIDTH == 102 && RAM_DEPTH == 2) begin : GEN_BRAM_TDP_102W_2D //Test cache miss case, EQC CACHE_SET_NUM = 2
110
+ BRAM_TDP_102w_2d BRAM_TDP_102w_2d_Inst(
111
+ .clka ( clk ),
112
+ .rsta ( rst ),
113
+ .wea ( wea ),
114
+ .addra ( addra ),
115
+ .dina ( dina ),
116
+ .douta ( douta_fake ),
117
+ .clkb ( clk ),
118
+ .rstb ( rst ),
119
+ .web ( web ),
120
+ .addrb ( addrb ),
121
+ .dinb ( dinb ),
122
+ .doutb ( doutb_fake )
123
+ );
124
+ end
125
+ else if(RAM_WIDTH == 431 && RAM_DEPTH == 2) begin : GEN_BRAM_TDP_431W_2D //Test cache miss case, QPC CACHE_SET_NUM = 2
126
+ BRAM_TDP_431w_2d BRAM_TDP_431w_2d_Inst(
127
+ .clka ( clk ),
128
+ .rsta ( rst ),
129
+ .wea ( wea ),
130
+ .addra ( addra ),
131
+ .dina ( dina ),
132
+ .douta ( douta_fake ),
133
+ .clkb ( clk ),
134
+ .rstb ( rst ),
135
+ .web ( web ),
136
+ .addrb ( addrb ),
137
+ .dinb ( dinb ),
138
+ .doutb ( doutb_fake )
139
+ );
140
+ end
141
+ else if(RAM_WIDTH == 1 && RAM_DEPTH == 2) begin : GEN_BRAM_TDP_1W_2D //Test cache miss case, LRU Table
142
+ BRAM_TDP_1w_2d BRAM_TDP_1w_2d_Inst(
143
+ .clka ( clk ),
144
+ .rsta ( rst ),
145
+ .wea ( wea ),
146
+ .addra ( addra ),
147
+ .dina ( dina ),
148
+ .douta ( douta_fake ),
149
+ .clkb ( clk ),
150
+ .rstb ( rst ),
151
+ .web ( web ),
152
+ .addrb ( addrb ),
153
+ .dinb ( dinb ),
154
+ .doutb ( doutb_fake )
155
+ );
156
+ end
157
+ else if(RAM_WIDTH == 2 && RAM_DEPTH == 128) begin : GEN_BRAM_TDP_2W_128D
158
+ BRAM_TDP_2w_128d BRAM_TDP_2w_128d_Inst(
159
+ .clka ( clk ),
160
+ .rsta ( rst ),
161
+ .wea ( wea ),
162
+ .addra ( addra ),
163
+ .dina ( dina ),
164
+ .douta ( douta_fake ),
165
+ .clkb ( clk ),
166
+ .rstb ( rst ),
167
+ .web ( web ),
168
+ .addrb ( addrb ),
169
+ .dinb ( dinb ),
170
+ .doutb ( doutb_fake )
171
+ );
172
+ end
173
+ else if(RAM_WIDTH == 8 && RAM_DEPTH == 128) begin : GEN_BRAM_TDP_8W_128D
174
+ BRAM_TDP_8w_128d BRAM_TDP_8w_128d_Inst(
175
+ .clka ( clk ),
176
+ .rsta ( rst ),
177
+ .wea ( wea ),
178
+ .addra ( addra ),
179
+ .dina ( dina ),
180
+ .douta ( douta_fake ),
181
+ .clkb ( clk ),
182
+ .rstb ( rst ),
183
+ .web ( web ),
184
+ .addrb ( addrb ),
185
+ .dinb ( dinb ),
186
+ .doutb ( doutb_fake )
187
+ );
188
+ end
189
+ else if(RAM_WIDTH == 1 && RAM_DEPTH == 512) begin : GEN_BRAM_TDP_1W_512D
190
+ BRAM_TDP_1w_512d BRAM_TDP_1w_512d_Inst(
191
+ .clka ( clk ),
192
+ .rsta ( rst ),
193
+ .wea ( wea ),
194
+ .addra ( addra ),
195
+ .dina ( dina ),
196
+ .douta ( douta_fake ),
197
+ .clkb ( clk ),
198
+ .rstb ( rst ),
199
+ .web ( web ),
200
+ .addrb ( addrb ),
201
+ .dinb ( dinb ),
202
+ .doutb ( doutb_fake )
203
+ );
204
+ end
205
+ else if(RAM_WIDTH == 332 && RAM_DEPTH == 512) begin : GEN_BRAM_TDP_332W_512D
206
+ BRAM_TDP_332w_512d BRAM_TDP_332w_512d_Inst(
207
+ .clka ( clk ),
208
+ .rsta ( rst ),
209
+ .wea ( wea ),
210
+ .addra ( addra ),
211
+ .dina ( dina ),
212
+ .douta ( douta_fake ),
213
+ .clkb ( clk ),
214
+ .rstb ( rst ),
215
+ .web ( web ),
216
+ .addrb ( addrb ),
217
+ .dinb ( dinb ),
218
+ .doutb ( doutb_fake )
219
+ );
220
+ end
221
+ else if(RAM_WIDTH == 82 && RAM_DEPTH == 4096) begin : GEN_BRAM_TDP_82W_4096D
222
+ BRAM_TDP_82w_4096d BRAM_TDP_82w_4096d_Inst(
223
+ .clka ( clk ),
224
+ .rsta ( rst ),
225
+ .wea ( wea ),
226
+ .addra ( addra ),
227
+ .dina ( dina ),
228
+ .douta ( douta_fake ),
229
+ .clkb ( clk ),
230
+ .rstb ( rst ),
231
+ .web ( web ),
232
+ .addrb ( addrb ),
233
+ .dinb ( dinb ),
234
+ .doutb ( doutb_fake )
235
+ );
236
+ end
237
+ else if(RAM_WIDTH == 99 && RAM_DEPTH == 16) begin : GEN_BRAM_TDP_99W_16D
238
+ BRAM_TDP_99w_16d BRAM_TDP_99w_16d_Inst(
239
+ .clka ( clk ),
240
+ .rsta ( rst ),
241
+ .wea ( wea ),
242
+ .addra ( addra ),
243
+ .dina ( dina ),
244
+ .douta ( douta_fake ),
245
+ .clkb ( clk ),
246
+ .rstb ( rst ),
247
+ .web ( web ),
248
+ .addrb ( addrb ),
249
+ .dinb ( dinb ),
250
+ .doutb ( doutb_fake )
251
+ );
252
+ end
253
+ else if(RAM_WIDTH == 136 && RAM_DEPTH == 256) begin : GEN_BRAM_TDP_136W_256D
254
+ BRAM_TDP_136w_256d BRAM_TDP_136w_256d_Inst(
255
+ .clka ( clk ),
256
+ .rsta ( rst ),
257
+ .wea ( wea ),
258
+ .addra ( addra ),
259
+ .dina ( dina ),
260
+ .douta ( douta_fake ),
261
+ .clkb ( clk ),
262
+ .rstb ( rst ),
263
+ .web ( web ),
264
+ .addrb ( addrb ),
265
+ .dinb ( dinb ),
266
+ .doutb ( doutb_fake )
267
+ );
268
+ end
269
+ else if(RAM_WIDTH == 424 && RAM_DEPTH == 256) begin : GEN_BRAM_TDP_424W_256D
270
+ BRAM_TDP_424w_256d BRAM_TDP_424w_256d_Inst(
271
+ .clka ( clk ),
272
+ .rsta ( rst ),
273
+ .wea ( wea ),
274
+ .addra ( addra ),
275
+ .dina ( dina ),
276
+ .douta ( douta_fake ),
277
+ .clkb ( clk ),
278
+ .rstb ( rst ),
279
+ .web ( web ),
280
+ .addrb ( addrb ),
281
+ .dinb ( dinb ),
282
+ .doutb ( doutb_fake )
283
+ );
284
+ end
285
+ else if(RAM_WIDTH == 52 && RAM_DEPTH == 8192) begin : GEN_BRAM_TDP_52W_8192D
286
+ BRAM_TDP_52w_8192d BRAM_TDP_52w_8192d_Inst(
287
+ .clka ( clk ),
288
+ .rsta ( rst ),
289
+ .wea ( wea ),
290
+ .addra ( addra ),
291
+ .dina ( dina ),
292
+ .douta ( douta_fake ),
293
+ .clkb ( clk ),
294
+ .rstb ( rst ),
295
+ .web ( web ),
296
+ .addrb ( addrb ),
297
+ .dinb ( dinb ),
298
+ .doutb ( doutb_fake )
299
+ );
300
+ end
301
+ else if(RAM_WIDTH == 24 && RAM_DEPTH == 256) begin : GEN_BRAM_TDP_24W_256D
302
+ BRAM_TDP_24w_256d BRAM_TDP_24w_256d_Inst(
303
+ .clka ( clk ),
304
+ .rsta ( rst ),
305
+ .wea ( wea ),
306
+ .addra ( addra ),
307
+ .dina ( dina ),
308
+ .douta ( douta_fake ),
309
+ .clkb ( clk ),
310
+ .rstb ( rst ),
311
+ .web ( web ),
312
+ .addrb ( addrb ),
313
+ .dinb ( dinb ),
314
+ .doutb ( doutb_fake )
315
+ );
316
+ end
317
+ else if(RAM_WIDTH == 5 && RAM_DEPTH == 16) begin : GEN_BRAM_TDP_5W_16D
318
+ BRAM_TDP_5w_16d BRAM_TDP_5w_16d_Inst(
319
+ .clka ( clk ),
320
+ .rsta ( rst ),
321
+ .wea ( wea ),
322
+ .addra ( addra ),
323
+ .dina ( dina ),
324
+ .douta ( douta_fake ),
325
+ .clkb ( clk ),
326
+ .rstb ( rst ),
327
+ .web ( web ),
328
+ .addrb ( addrb ),
329
+ .dinb ( dinb ),
330
+ .doutb ( doutb_fake )
331
+ );
332
+ end
333
+ else if(RAM_WIDTH == 6 && RAM_DEPTH == 16) begin : GEN_BRAM_TDP_6W_16D
334
+ BRAM_TDP_6w_16d BRAM_TDP_6w_16d_Inst(
335
+ .clka ( clk ),
336
+ .rsta ( rst ),
337
+ .wea ( wea ),
338
+ .addra ( addra ),
339
+ .dina ( dina ),
340
+ .douta ( douta_fake ),
341
+ .clkb ( clk ),
342
+ .rstb ( rst ),
343
+ .web ( web ),
344
+ .addrb ( addrb ),
345
+ .dinb ( dinb ),
346
+ .doutb ( doutb_fake )
347
+ );
348
+ end
349
+ else if(RAM_WIDTH == 512 && RAM_DEPTH == 32) begin : GEN_BRAM_TDP_512W_32D
350
+ BRAM_TDP_512w_32d BRAM_TDP_512w_32d_Inst(
351
+ .clka ( clk ),
352
+ .rsta ( rst ),
353
+ .wea ( wea ),
354
+ .addra ( addra ),
355
+ .dina ( dina ),
356
+ .douta ( douta_fake ),
357
+ .clkb ( clk ),
358
+ .rstb ( rst ),
359
+ .web ( web ),
360
+ .addrb ( addrb ),
361
+ .dinb ( dinb ),
362
+ .doutb ( doutb_fake )
363
+ );
364
+ end
365
+ else if(RAM_WIDTH == 1 && RAM_DEPTH == 16) begin : GEN_BRAM_TDP_1W_16D
366
+ BRAM_TDP_1w_16d BRAM_TDP_1w_16d_Inst(
367
+ .clka ( clk ),
368
+ .rsta ( rst ),
369
+ .wea ( wea ),
370
+ .addra ( addra ),
371
+ .dina ( dina ),
372
+ .douta ( douta_fake ),
373
+ .clkb ( clk ),
374
+ .rstb ( rst ),
375
+ .web ( web ),
376
+ .addrb ( addrb ),
377
+ .dinb ( dinb ),
378
+ .doutb ( doutb_fake )
379
+ );
380
+ end
381
+ else if(RAM_WIDTH == 1 && RAM_DEPTH == 256) begin : GEN_BRAM_TDP_1W_256D
382
+ BRAM_TDP_1w_256d BRAM_TDP_1w_256d_Inst(
383
+ .clka ( clk ),
384
+ .rsta ( rst ),
385
+ .wea ( wea ),
386
+ .addra ( addra ),
387
+ .dina ( dina ),
388
+ .douta ( douta_fake ),
389
+ .clkb ( clk ),
390
+ .rstb ( rst ),
391
+ .web ( web ),
392
+ .addrb ( addrb ),
393
+ .dinb ( dinb ),
394
+ .doutb ( doutb_fake )
395
+ );
396
+ end
397
+ else if(RAM_WIDTH == 5 && RAM_DEPTH == 256) begin : GEN_BRAM_TDP_5W_256D
398
+ BRAM_TDP_5w_256d BRAM_TDP_5w_256d_Inst(
399
+ .clka ( clk ),
400
+ .rsta ( rst ),
401
+ .wea ( wea ),
402
+ .addra ( addra ),
403
+ .dina ( dina ),
404
+ .douta ( douta_fake ),
405
+ .clkb ( clk ),
406
+ .rstb ( rst ),
407
+ .web ( web ),
408
+ .addrb ( addrb ),
409
+ .dinb ( dinb ),
410
+ .doutb ( doutb_fake )
411
+ );
412
+ end
413
+ else if(RAM_WIDTH == 5 && RAM_DEPTH == 32) begin : GEN_BRAM_TDP_5W_32D
414
+ BRAM_TDP_5w_32d BRAM_TDP_5w_32d_Inst(
415
+ .clka ( clk ),
416
+ .rsta ( rst ),
417
+ .wea ( wea ),
418
+ .addra ( addra ),
419
+ .dina ( dina ),
420
+ .douta ( douta_fake ),
421
+ .clkb ( clk ),
422
+ .rstb ( rst ),
423
+ .web ( web ),
424
+ .addrb ( addrb ),
425
+ .dinb ( dinb ),
426
+ .doutb ( doutb_fake )
427
+ );
428
+ end
429
+ else if(RAM_WIDTH == 98 && RAM_DEPTH == 32) begin : GEN_BRAM_TDP_98W_32D
430
+ BRAM_TDP_98w_32d BRAM_TDP_98w_32d_Inst(
431
+ .clka ( clk ),
432
+ .rsta ( rst ),
433
+ .wea ( wea ),
434
+ .addra ( addra ),
435
+ .dina ( dina ),
436
+ .douta ( douta_fake ),
437
+ .clkb ( clk ),
438
+ .rstb ( rst ),
439
+ .web ( web ),
440
+ .addrb ( addrb ),
441
+ .dinb ( dinb ),
442
+ .doutb ( doutb_fake )
443
+ );
444
+ end
445
+ else if(RAM_WIDTH == 418 && RAM_DEPTH == 32) begin : GEN_BRAM_TDP_418W_32D
446
+ BRAM_TDP_418w_32d BRAM_TDP_418w_32d_Inst(
447
+ .clka ( clk ),
448
+ .rsta ( rst ),
449
+ .wea ( wea ),
450
+ .addra ( addra ),
451
+ .dina ( dina ),
452
+ .douta ( douta_fake ),
453
+ .clkb ( clk ),
454
+ .rstb ( rst ),
455
+ .web ( web ),
456
+ .addrb ( addrb ),
457
+ .dinb ( dinb ),
458
+ .doutb ( doutb_fake )
459
+ );
460
+ end
461
+ else if(RAM_WIDTH == 130 && RAM_DEPTH == 32) begin : GEN_BRAM_TDP_130W_32D
462
+ BRAM_TDP_130w_32d BRAM_TDP_130w_32d_Inst(
463
+ .clka ( clk ),
464
+ .rsta ( rst ),
465
+ .wea ( wea ),
466
+ .addra ( addra ),
467
+ .dina ( dina ),
468
+ .douta ( douta_fake ),
469
+ .clkb ( clk ),
470
+ .rstb ( rst ),
471
+ .web ( web ),
472
+ .addrb ( addrb ),
473
+ .dinb ( dinb ),
474
+ .doutb ( doutb_fake )
475
+ );
476
+ end
477
+ else if(RAM_WIDTH == 322 && RAM_DEPTH == 32) begin : GEN_BRAM_TDP_322W_32D
478
+ BRAM_TDP_322w_32d BRAM_TDP_322w_32d_Inst(
479
+ .clka ( clk ),
480
+ .rsta ( rst ),
481
+ .wea ( wea ),
482
+ .addra ( addra ),
483
+ .dina ( dina ),
484
+ .douta ( douta_fake ),
485
+ .clkb ( clk ),
486
+ .rstb ( rst ),
487
+ .web ( web ),
488
+ .addrb ( addrb ),
489
+ .dinb ( dinb ),
490
+ .doutb ( doutb_fake )
491
+ );
492
+ end
493
+ else if(RAM_WIDTH == 192 && RAM_DEPTH == 32) begin : GEN_BRAM_TDP_192W_32D
494
+ BRAM_TDP_192w_32d BRAM_TDP_192w_32d_Inst(
495
+ .clka ( clk ),
496
+ .rsta ( rst ),
497
+ .wea ( wea ),
498
+ .addra ( addra ),
499
+ .dina ( dina ),
500
+ .douta ( douta_fake ),
501
+ .clkb ( clk ),
502
+ .rstb ( rst ),
503
+ .web ( web ),
504
+ .addrb ( addrb ),
505
+ .dinb ( dinb ),
506
+ .doutb ( doutb_fake )
507
+ );
508
+ end
509
+ else if(RAM_WIDTH == 12 && RAM_DEPTH == 32) begin : GEN_BRAM_TDP_12W_32D
510
+ BRAM_TDP_12w_32d BRAM_TDP_12w_32d_Inst(
511
+ .clka ( clk ),
512
+ .rsta ( rst ),
513
+ .wea ( wea ),
514
+ .addra ( addra ),
515
+ .dina ( dina ),
516
+ .douta ( douta_fake ),
517
+ .clkb ( clk ),
518
+ .rstb ( rst ),
519
+ .web ( web ),
520
+ .addrb ( addrb ),
521
+ .dinb ( dinb ),
522
+ .doutb ( doutb_fake )
523
+ );
524
+ end
525
+ else if(RAM_WIDTH == 44 && RAM_DEPTH == 32) begin : GEN_BRAM_TDP_44W_32D
526
+ BRAM_TDP_44w_32d BRAM_TDP_44w_32d_Inst(
527
+ .clka ( clk ),
528
+ .rsta ( rst ),
529
+ .wea ( wea ),
530
+ .addra ( addra ),
531
+ .dina ( dina ),
532
+ .douta ( douta_fake ),
533
+ .clkb ( clk ),
534
+ .rstb ( rst ),
535
+ .web ( web ),
536
+ .addrb ( addrb ),
537
+ .dinb ( dinb ),
538
+ .doutb ( doutb_fake )
539
+ );
540
+ end
541
+ else if(RAM_WIDTH == 576 && RAM_DEPTH == 32) begin : GEN_BRAM_TDP_576W_32D
542
+ BRAM_TDP_576w_32d BRAM_TDP_576w_32d_Inst(
543
+ .clka ( clk ),
544
+ .rsta ( rst ),
545
+ .wea ( wea ),
546
+ .addra ( addra ),
547
+ .dina ( dina ),
548
+ .douta ( douta_fake ),
549
+ .clkb ( clk ),
550
+ .rstb ( rst ),
551
+ .web ( web ),
552
+ .addrb ( addrb ),
553
+ .dinb ( dinb ),
554
+ .doutb ( doutb_fake )
555
+ );
556
+ end
557
+ else if(RAM_WIDTH == 6 && RAM_DEPTH == 256) begin : GEN_BRAM_TDP_6W_256D
558
+ BRAM_TDP_6w_256d BRAM_TDP_6w_256d_Inst(
559
+ .clka ( clk ),
560
+ .rsta ( rst ),
561
+ .wea ( wea ),
562
+ .addra ( addra ),
563
+ .dina ( dina ),
564
+ .douta ( douta_fake ),
565
+ .clkb ( clk ),
566
+ .rstb ( rst ),
567
+ .web ( web ),
568
+ .addrb ( addrb ),
569
+ .dinb ( dinb ),
570
+ .doutb ( doutb_fake )
571
+ );
572
+ end
573
+ else if(RAM_WIDTH == 6 && RAM_DEPTH == 64) begin : GEN_BRAM_TDP_6W_64D
574
+ BRAM_TDP_6w_64d BRAM_TDP_6w_64d_Inst(
575
+ .clka ( clk ),
576
+ .rsta ( rst ),
577
+ .wea ( wea ),
578
+ .addra ( addra ),
579
+ .dina ( dina ),
580
+ .douta ( douta_fake ),
581
+ .clkb ( clk ),
582
+ .rstb ( rst ),
583
+ .web ( web ),
584
+ .addrb ( addrb ),
585
+ .dinb ( dinb ),
586
+ .doutb ( doutb_fake )
587
+ );
588
+ end
589
+ else if(RAM_WIDTH == 256 && RAM_DEPTH == 64) begin : GEN_BRAM_TDP_256W_64D
590
+ BRAM_TDP_256w_64d BRAM_TDP_256w_64d_Inst(
591
+ .clka ( clk ),
592
+ .rsta ( rst ),
593
+ .wea ( wea ),
594
+ .addra ( addra ),
595
+ .dina ( dina ),
596
+ .douta ( douta_fake ),
597
+ .clkb ( clk ),
598
+ .rstb ( rst ),
599
+ .web ( web ),
600
+ .addrb ( addrb ),
601
+ .dinb ( dinb ),
602
+ .doutb ( doutb_fake )
603
+ );
604
+ end
605
+ else if(RAM_WIDTH == 512 && RAM_DEPTH == 512) begin : GEN_BRAM_TDP_512W_512D
606
+ BRAM_TDP_512w_512d BRAM_TDP_512w_512d_Inst(
607
+ .clka ( clk ),
608
+ .rsta ( rst ),
609
+ .wea ( wea ),
610
+ .addra ( addra ),
611
+ .dina ( dina ),
612
+ .douta ( douta_fake ),
613
+ .clkb ( clk ),
614
+ .rstb ( rst ),
615
+ .web ( web ),
616
+ .addrb ( addrb ),
617
+ .dinb ( dinb ),
618
+ .doutb ( doutb_fake )
619
+ );
620
+ end
621
+ else if(RAM_WIDTH == 9 && RAM_DEPTH == 512) begin : GEN_BRAM_TDP_9W_512D
622
+ BRAM_TDP_9w_512d BRAM_TDP_9w_512d_Inst(
623
+ .clka ( clk ),
624
+ .rsta ( rst ),
625
+ .wea ( wea ),
626
+ .addra ( addra ),
627
+ .dina ( dina ),
628
+ .douta ( douta_fake ),
629
+ .clkb ( clk ),
630
+ .rstb ( rst ),
631
+ .web ( web ),
632
+ .addrb ( addrb ),
633
+ .dinb ( dinb ),
634
+ .doutb ( doutb_fake )
635
+ );
636
+ end
637
+ else if(RAM_WIDTH == 488 && RAM_DEPTH == 32) begin : GEN_BRAM_TDP_488W_32D
638
+ BRAM_TDP_488w_32d BRAM_TDP_488w_32d_Inst(
639
+ .clka ( clk ),
640
+ .rsta ( rst ),
641
+ .wea ( wea ),
642
+ .addra ( addra ),
643
+ .dina ( dina ),
644
+ .douta ( douta_fake ),
645
+ .clkb ( clk ),
646
+ .rstb ( rst ),
647
+ .web ( web ),
648
+ .addrb ( addrb ),
649
+ .dinb ( dinb ),
650
+ .doutb ( doutb_fake )
651
+ );
652
+ end
653
+ else if(RAM_WIDTH == 352 && RAM_DEPTH == 32) begin : GEN_BRAM_TDP_352W_32D
654
+ BRAM_TDP_352w_32d BRAM_TDP_352w_32d_Inst(
655
+ .clka ( clk ),
656
+ .rsta ( rst ),
657
+ .wea ( wea ),
658
+ .addra ( addra ),
659
+ .dina ( dina ),
660
+ .douta ( douta_fake ),
661
+ .clkb ( clk ),
662
+ .rstb ( rst ),
663
+ .web ( web ),
664
+ .addrb ( addrb ),
665
+ .dinb ( dinb ),
666
+ .doutb ( doutb_fake )
667
+ );
668
+ end
669
+ else if(RAM_WIDTH == 192 && RAM_DEPTH == 256) begin : GEN_BRAM_TDP_192W_256D
670
+ BRAM_TDP_192w_256d BRAM_TDP_192w_256d_Inst(
671
+ .clka ( clk ),
672
+ .rsta ( rst ),
673
+ .wea ( wea ),
674
+ .addra ( addra ),
675
+ .dina ( dina ),
676
+ .douta ( douta_fake ),
677
+ .clkb ( clk ),
678
+ .rstb ( rst ),
679
+ .web ( web ),
680
+ .addrb ( addrb ),
681
+ .dinb ( dinb ),
682
+ .doutb ( doutb_fake )
683
+ );
684
+ end
685
+ else if(RAM_WIDTH == 44 && RAM_DEPTH == 256) begin : GEN_BRAM_TDP_44W_256D
686
+ BRAM_TDP_44w_256d BRAM_TDP_44w_256d_Inst(
687
+ .clka ( clk ),
688
+ .rsta ( rst ),
689
+ .wea ( wea ),
690
+ .addra ( addra ),
691
+ .dina ( dina ),
692
+ .douta ( douta_fake ),
693
+ .clkb ( clk ),
694
+ .rstb ( rst ),
695
+ .web ( web ),
696
+ .addrb ( addrb ),
697
+ .dinb ( dinb ),
698
+ .doutb ( doutb_fake )
699
+ );
700
+ end
701
+ else if(RAM_WIDTH == 322 && RAM_DEPTH == 256) begin : GEN_BRAM_TDP_322W_256D
702
+ BRAM_TDP_322w_256d BRAM_TDP_322w_256d_Inst(
703
+ .clka ( clk ),
704
+ .rsta ( rst ),
705
+ .wea ( wea ),
706
+ .addra ( addra ),
707
+ .dina ( dina ),
708
+ .douta ( douta_fake ),
709
+ .clkb ( clk ),
710
+ .rstb ( rst ),
711
+ .web ( web ),
712
+ .addrb ( addrb ),
713
+ .dinb ( dinb ),
714
+ .doutb ( doutb_fake )
715
+ );
716
+ end
717
+ else if(RAM_WIDTH == 130 && RAM_DEPTH == 256) begin : GEN_BRAM_TDP_130W_256D
718
+ BRAM_TDP_130w_256d BRAM_TDP_130w_256d_Inst(
719
+ .clka ( clk ),
720
+ .rsta ( rst ),
721
+ .wea ( wea ),
722
+ .addra ( addra ),
723
+ .dina ( dina ),
724
+ .douta ( douta_fake ),
725
+ .clkb ( clk ),
726
+ .rstb ( rst ),
727
+ .web ( web ),
728
+ .addrb ( addrb ),
729
+ .dinb ( dinb ),
730
+ .doutb ( doutb_fake )
731
+ );
732
+ end
733
+ else if(RAM_WIDTH == 98 && RAM_DEPTH == 256) begin : GEN_BRAM_TDP_98W_256D
734
+ BRAM_TDP_98w_256d BRAM_TDP_98w_256d_Inst(
735
+ .clka ( clk ),
736
+ .rsta ( rst ),
737
+ .wea ( wea ),
738
+ .addra ( addra ),
739
+ .dina ( dina ),
740
+ .douta ( douta_fake ),
741
+ .clkb ( clk ),
742
+ .rstb ( rst ),
743
+ .web ( web ),
744
+ .addrb ( addrb ),
745
+ .dinb ( dinb ),
746
+ .doutb ( doutb_fake )
747
+ );
748
+ end
749
+ else if(RAM_WIDTH == 418 && RAM_DEPTH == 256) begin : GEN_BRAM_TDP_418W_256D
750
+ BRAM_TDP_418w_256d BRAM_TDP_418w_256d_Inst(
751
+ .clka ( clk ),
752
+ .rsta ( rst ),
753
+ .wea ( wea ),
754
+ .addra ( addra ),
755
+ .dina ( dina ),
756
+ .douta ( douta_fake ),
757
+ .clkb ( clk ),
758
+ .rstb ( rst ),
759
+ .web ( web ),
760
+ .addrb ( addrb ),
761
+ .dinb ( dinb ),
762
+ .doutb ( doutb_fake )
763
+ );
764
+ end
765
+ endgenerate
766
+
767
+ //Resolve read-write collisions
768
+ reg wea_diff;
769
+ reg [ADDR_WIDTH - 1 : 0] addra_diff;
770
+ reg [RAM_WIDTH - 1 : 0] dina_diff;
771
+
772
+ reg web_diff;
773
+ reg [ADDR_WIDTH - 1 : 0] addrb_diff;
774
+ reg [RAM_WIDTH - 1 : 0] dinb_diff;
775
+
776
+ always @(posedge clk or posedge rst) begin
777
+ if(rst) begin
778
+ wea_diff <= 'd0;
779
+ addra_diff <= 'd0;
780
+ dina_diff <= 'd0;
781
+ end
782
+ else begin
783
+ wea_diff <= wea;
784
+ addra_diff <= addra;
785
+ dina_diff <= dina;
786
+ end
787
+ end
788
+
789
+ assign douta = (addra_diff == addrb_diff) && wea_diff && !web_diff ? dina_diff :
790
+ (addra_diff == addrb_diff) && !wea_diff && web_diff ? dinb_diff :
791
+ (addra_diff != addrb_diff) && wea_diff ? dina_diff : douta_fake;
792
+
793
+ always @(posedge clk or posedge rst) begin
794
+ if(rst) begin
795
+ web_diff <= 'd0;
796
+ addrb_diff <= 'd0;
797
+ dinb_diff <= 'd0;
798
+ end
799
+ else begin
800
+ web_diff <= web;
801
+ addrb_diff <= addrb;
802
+ dinb_diff <= dinb;
803
+ end
804
+ end
805
+
806
+ assign doutb = (addra_diff == addrb_diff) && wea_diff && !web_diff ? dina_diff :
807
+ (addra_diff == addrb_diff) && !wea_diff && web_diff ? dinb_diff :
808
+ (addra_diff != addrb_diff) && web_diff ? dinb_diff : doutb_fake;
809
+
810
+ /*Debug subsystem : Begin*/
811
+ `ifdef DEBUG_ON
812
+
813
+ `endif
814
+ /*Debug subsystem : End*/
815
+
816
+
817
+ endmodule
ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Common/SyncFIFO_2Port_Ctrl_SRAM.v ADDED
@@ -0,0 +1,180 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ // sync FIFO controller which uses two-port SRAM as data array
2
+ `timescale 1ns / 100ps
3
+
4
+ module SyncFIFO_2Port_Ctrl_SRAM #(
5
+ parameter DATA_WIDTH = 32'd10,
6
+ parameter FIFO_DEPTH = 4,
7
+ parameter ADDR_WIDTH = log2b(FIFO_DEPTH-1), // local param, do not modify
8
+ parameter DEPTH_WIDTH = log2b(FIFO_DEPTH) // local param, do not modify
9
+ )
10
+ (
11
+ input clk,
12
+ input rst_n,
13
+ input push,
14
+ input pop,
15
+ input [DATA_WIDTH-1:0] data_in,
16
+ output [DATA_WIDTH-1:0] data_out,
17
+ output full,
18
+ output progfull,
19
+ output empty,
20
+ output [DEPTH_WIDTH-1:0] remain, // This is inaccurate, and only indicates the remaining data count in sram
21
+ output reg [DEPTH_WIDTH-1:0] count, // This is inaccurate, and only indicates the data count in sram
22
+ output reg ovflow,
23
+ output reg undflow,
24
+
25
+ output sram_wr_cen,
26
+ output [ADDR_WIDTH-1:0] sram_wr_a,
27
+ output [DATA_WIDTH-1:0] sram_wr_d,
28
+
29
+ output sram_rd_cen,
30
+ output [ADDR_WIDTH-1:0] sram_rd_a,
31
+ input [DATA_WIDTH-1:0] sram_rd_q
32
+ );
33
+
34
+ assign remain = FIFO_DEPTH - count;
35
+
36
+ function integer log2b;
37
+ input integer val;
38
+ begin: func_log2b
39
+ integer i;
40
+ log2b = 1;
41
+ for (i=0; i<32; i=i+1) begin
42
+ if (|(val >> i)) begin
43
+ log2b = i+1;
44
+ end
45
+ end
46
+ end
47
+ endfunction
48
+
49
+ reg [ADDR_WIDTH-1:0] waddr;
50
+ reg [ADDR_WIDTH-1:0] raddr;
51
+
52
+ reg [DATA_WIDTH-1:0] rd_buf;
53
+ reg rd_buf_vld;
54
+ reg sram_q_vld;
55
+
56
+ assign sram_rd_cen = ~((count != {DEPTH_WIDTH{1'b0}}) & ((~sram_q_vld) & (~rd_buf_vld) |
57
+ (~sram_q_vld) & pop |
58
+ (~rd_buf_vld) & pop));
59
+ assign sram_rd_a = raddr;
60
+
61
+ assign sram_wr_cen = ~((~full) & push);
62
+ assign sram_wr_a = waddr;
63
+ assign sram_wr_d = data_in;
64
+
65
+ assign data_out = rd_buf_vld ? rd_buf : sram_rd_q;
66
+ assign empty = ~(sram_q_vld | rd_buf_vld);
67
+ assign full = (count == FIFO_DEPTH);
68
+ assign progfull = (count > (FIFO_DEPTH - 3));
69
+
70
+ always @(posedge clk or negedge rst_n)
71
+ begin
72
+ if (~rst_n) begin
73
+ sram_q_vld <= `TD 1'b0;
74
+ end
75
+ else begin
76
+ sram_q_vld <= `TD ~sram_rd_cen;
77
+ end
78
+ end
79
+
80
+ always @(posedge clk or negedge rst_n)
81
+ begin
82
+ if (~rst_n) begin
83
+ rd_buf <= `TD {DATA_WIDTH{1'b0}};
84
+ rd_buf_vld <= `TD 1'b0;
85
+ end
86
+ else if (sram_q_vld & (~pop)) begin
87
+ rd_buf_vld <= `TD 1'b1;
88
+ rd_buf <= `TD sram_rd_q;
89
+ end
90
+ else if (rd_buf_vld & pop) begin
91
+ rd_buf_vld <= `TD 1'b0;
92
+ end
93
+ end
94
+
95
+ always @(posedge clk or negedge rst_n)
96
+ begin
97
+ if (~rst_n) begin
98
+ waddr <= `TD {ADDR_WIDTH{1'b0}};
99
+ end
100
+ else if (~sram_wr_cen) begin
101
+ if (waddr == FIFO_DEPTH - 1) begin
102
+ waddr <= `TD {ADDR_WIDTH{1'b0}};
103
+ end
104
+ else begin
105
+ waddr <= `TD waddr + {{ADDR_WIDTH-1{1'b0}}, 1'b1};
106
+ end
107
+ end
108
+ end
109
+
110
+ always @(posedge clk or negedge rst_n)
111
+ begin
112
+ if (~rst_n) begin
113
+ raddr <= `TD {ADDR_WIDTH{1'b0}};
114
+ end
115
+ else if (~sram_rd_cen) begin
116
+ if (raddr == FIFO_DEPTH - 1) begin
117
+ raddr <= `TD {ADDR_WIDTH{1'b0}};
118
+ end
119
+ else begin
120
+ raddr <= `TD raddr + {{ADDR_WIDTH-1{1'b0}}, 1'b1};
121
+ end
122
+ end
123
+ end
124
+
125
+ always @(posedge clk or negedge rst_n)
126
+ begin
127
+ if (~rst_n) begin
128
+ count <= `TD {DEPTH_WIDTH{1'b0}};
129
+ end
130
+ // else if ((~sram_wr_cen) & (~sram_rd_cen) & empty) begin
131
+ // count <= `TD count + {{(DEPTH_WIDTH-1){1'b0}}, 1'h1};
132
+ // end
133
+ // else if ((~sram_wr_cen) & (~sram_rd_cen) & !empty) begin
134
+ // count <= `TD count;
135
+ // end
136
+ else if ((~sram_wr_cen) & (~sram_rd_cen)) begin
137
+ count <= `TD count;
138
+ end
139
+ else if (~sram_wr_cen) begin
140
+ count <= `TD count + {{(DEPTH_WIDTH-1){1'b0}}, 1'h1};
141
+ end
142
+ else if (~sram_rd_cen) begin
143
+ count <= `TD count - {{(DEPTH_WIDTH-1){1'b0}}, 1'h1};
144
+ end
145
+ end
146
+
147
+ always @(posedge clk or negedge rst_n)
148
+ begin
149
+ if (~rst_n) begin
150
+ ovflow <= `TD 1'b0;
151
+ end
152
+ else if (push & full) begin
153
+ ovflow <= `TD 1'b1;
154
+ end
155
+ end
156
+
157
+ always @(posedge clk or negedge rst_n)
158
+ begin
159
+ if (~rst_n) begin
160
+ undflow <= `TD 1'b0;
161
+ end
162
+ else if (pop & empty) begin
163
+ undflow <= `TD 1'b1;
164
+ end
165
+ end
166
+
167
+ //synopsys translate_off
168
+ initial begin
169
+ if (ADDR_WIDTH != log2b(FIFO_DEPTH-1)) begin
170
+ $display("\nFatal: ADDR_WIDTH must not be modified @(%m)\n");
171
+ $finish;
172
+ end
173
+ if (DEPTH_WIDTH != log2b(FIFO_DEPTH)) begin
174
+ $display("\nFatal: DEPTH_WIDTH must not be modified @(%m)\n");
175
+ $finish;
176
+ end
177
+ end
178
+ //synopsys translate_on
179
+
180
+ endmodule
ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Common/SyncFIFO_2Port_SRAM.v ADDED
@@ -0,0 +1,96 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+
2
+ module SyncFIFO_2Port_SRAM
3
+ #(
4
+ parameter DATA_WIDTH = 16,
5
+ parameter FIFO_DEPTH = 16,
6
+ parameter ADDR_WIDTH = log2b(FIFO_DEPTH - 1),
7
+ parameter DEPTH_WIDTH = log2b(FIFO_DEPTH)
8
+ )
9
+ (
10
+ input wire clk,
11
+ input wire rst,
12
+
13
+ input wire wr_en,
14
+ input wire [DATA_WIDTH - 1 : 0] din,
15
+ output wire prog_full,
16
+
17
+ input wire rd_en,
18
+ output wire [DATA_WIDTH - 1 : 0] dout,
19
+ output wire empty,
20
+ output wire [DEPTH_WIDTH - 1 : 0] data_count
21
+
22
+ );
23
+
24
+ function integer log2b;
25
+ input integer val;
26
+ begin: func_log2b
27
+ integer i;
28
+ log2b = 1;
29
+ for (i=0; i<32; i=i+1) begin
30
+ if (|(val >> i)) begin
31
+ log2b = i+1;
32
+ end
33
+ end
34
+ end
35
+ endfunction
36
+
37
+ wire sram_wr_cen;
38
+ wire [ADDR_WIDTH-1:0] sram_wr_a;
39
+ wire [DATA_WIDTH-1:0] sram_wr_d;
40
+
41
+ wire sram_rd_cen;
42
+ wire [ADDR_WIDTH-1:0] sram_rd_a;
43
+ wire [DATA_WIDTH-1:0] sram_rd_q;
44
+
45
+ wire [DEPTH_WIDTH - 1 : 0] empty_entry_num;
46
+
47
+ wire rst_n;
48
+ assign rst_n = !rst;
49
+
50
+ assign prog_full = (empty_entry_num < 3) ? 1'b1 : 1'b0;
51
+ assign data_count = (FIFO_DEPTH - empty_entry_num);
52
+
53
+ SyncFIFO_2Port_Ctrl_SRAM #(
54
+ .DATA_WIDTH(DATA_WIDTH),
55
+ .FIFO_DEPTH(FIFO_DEPTH)
56
+ ) U_SyncFIFO_2Port_Ctrl_SRAM
57
+ (
58
+ .clk(clk),
59
+ .rst_n(rst_n),
60
+ .push(wr_en),
61
+ .pop(rd_en),
62
+ .data_in(din),
63
+ .data_out(dout),
64
+ .full(),
65
+ .empty(empty),
66
+ .remain(empty_entry_num),
67
+ .count(),
68
+ .ovflow(),
69
+ .undflow(),
70
+ .sram_wr_cen(sram_wr_cen),
71
+ .sram_wr_a (sram_wr_a ),
72
+ .sram_wr_d (sram_wr_d ),
73
+ .sram_rd_cen(sram_rd_cen),
74
+ .sram_rd_a (sram_rd_a ),
75
+ .sram_rd_q (sram_rd_q )
76
+ );
77
+
78
+ SRAM_SDP_Model
79
+ #(
80
+ .DATA_WIDTH(DATA_WIDTH),
81
+ .ADDR_WIDTH(ADDR_WIDTH),
82
+ .RAM_DEPTH(FIFO_DEPTH)
83
+ ) U_sram_2port_model(
84
+ .clk(clk),
85
+ .rst(rst),
86
+ .sram_wr_cen(sram_wr_cen),
87
+ .sram_wr_a(sram_wr_a),
88
+ .sram_wr_d(sram_wr_d),
89
+ .sram_rd_cen(sram_rd_cen),
90
+ .sram_rd_a(sram_rd_a),
91
+ .sram_rd_q(sram_rd_q)
92
+ );
93
+
94
+ endmodule
95
+
96
+
ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Common/SyncFIFO_Template.v ADDED
@@ -0,0 +1,211 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ `timescale 1ns / 1ps
2
+
3
+ `include "common_function_def.vh"
4
+
5
+ module SyncFIFO_Template #(
6
+ parameter FIFO_TYPE = 0, //0: Xilinx IP, 1: RegFiles
7
+ parameter FIFO_WIDTH = 32,
8
+ parameter FIFO_DEPTH = 32,
9
+ parameter COUNT_WIDTH = log2b(FIFO_DEPTH)
10
+ )
11
+ (
12
+ input wire clk,
13
+ input wire rst,
14
+
15
+ input wire wr_en,
16
+ input wire [FIFO_WIDTH - 1 : 0] din,
17
+ output wire prog_full,
18
+ input wire rd_en,
19
+ output wire [FIFO_WIDTH - 1 : 0] dout,
20
+ output wire empty,
21
+ output wire [COUNT_WIDTH - 1 : 0] data_count
22
+ );
23
+
24
+
25
+ generate
26
+ if(FIFO_TYPE == 0) begin //Xilinx IP
27
+ if(FIFO_WIDTH == 64 && FIFO_DEPTH == 128) begin : GEN_SYNC_FIFO_64W_128D
28
+ SyncFIFO_64w_128d SyncFIFO_64w_128d_Inst(
29
+ .clk(clk),
30
+ .srst(rst),
31
+
32
+ .wr_en(wr_en),
33
+ .din(din),
34
+ .prog_full(prog_full),
35
+ .rd_en(rd_en),
36
+ .dout(dout),
37
+ .empty(empty),
38
+ .data_count(data_count)
39
+ );
40
+ end
41
+ else if(FIFO_WIDTH == 128 && FIFO_DEPTH == 16) begin : GEN_SYNC_FIFO_128W_16D
42
+ SyncFIFO_128w_16d SyncFIFO_128w_16d_Inst(
43
+ .clk(clk),
44
+ .srst(rst),
45
+
46
+ .wr_en(wr_en),
47
+ .din(din),
48
+ .prog_full(prog_full),
49
+ .rd_en(rd_en),
50
+ .dout(dout),
51
+ .empty(empty),
52
+ .data_count(data_count)
53
+ );
54
+ end
55
+ else if(FIFO_WIDTH == 258 && FIFO_DEPTH == 16) begin : GEN_SYNC_FIFO_258W_16D
56
+ SyncFIFO_258w_16d SyncFIFO_258w_16d_Inst(
57
+ .clk(clk),
58
+ .srst(rst),
59
+
60
+ .wr_en(wr_en),
61
+ .din(din),
62
+ .prog_full(prog_full),
63
+ .rd_en(rd_en),
64
+ .dout(dout),
65
+ .empty(empty),
66
+ .data_count(data_count)
67
+ );
68
+ end
69
+ else if(FIFO_WIDTH == 24 && FIFO_DEPTH == 256) begin : GEN_SYNC_FIFO_24W_256D
70
+ SyncFIFO_24w_256d SyncFIFO_24w_256d_Inst(
71
+ .clk(clk),
72
+ .srst(rst),
73
+
74
+ .wr_en(wr_en),
75
+ .din(din),
76
+ .prog_full(prog_full),
77
+ .rd_en(rd_en),
78
+ .dout(dout),
79
+ .empty(empty),
80
+ .data_count(data_count)
81
+ );
82
+ end
83
+ else if(FIFO_WIDTH == 5 && FIFO_DEPTH == 32) begin : GEN_SYNC_FIFO_5W_32D
84
+ SyncFIFO_5w_32d SyncFIFO_5w_32d_Inst(
85
+ .clk(clk),
86
+ .srst(rst),
87
+
88
+ .wr_en(wr_en),
89
+ .din(din),
90
+ .prog_full(prog_full),
91
+ .rd_en(rd_en),
92
+ .dout(dout),
93
+ .empty(empty),
94
+ .data_count(data_count)
95
+ );
96
+ end
97
+ else if(FIFO_WIDTH == 140 && FIFO_DEPTH == 32) begin : GEN_SYNC_FIFO_140W_32D
98
+ SyncFIFO_140w_32d SyncFIFO_140w_32d_Inst(
99
+ .clk(clk),
100
+ .srst(rst),
101
+
102
+ .wr_en(wr_en),
103
+ .din(din),
104
+ .prog_full(prog_full),
105
+ .rd_en(rd_en),
106
+ .dout(dout),
107
+ .empty(empty),
108
+ .data_count(data_count)
109
+ );
110
+ end
111
+ else if(FIFO_WIDTH == 512 && FIFO_DEPTH == 64) begin : GEN_SYNC_FIFO_512W_64D
112
+ SyncFIFO_512w_64d SyncFIFO_512w_64d_Inst(
113
+ .clk(clk),
114
+ .srst(rst),
115
+
116
+ .wr_en(wr_en),
117
+ .din(din),
118
+ .prog_full(prog_full),
119
+ .rd_en(rd_en),
120
+ .dout(dout),
121
+ .empty(empty),
122
+ .data_count(data_count)
123
+ );
124
+ end
125
+ else if(FIFO_WIDTH == 128 && FIFO_DEPTH == 64) begin : GEN_SYNC_FIFO_128W_64D
126
+ SyncFIFO_128w_64d SyncFIFO_128w_64d_Inst(
127
+ .clk(clk),
128
+ .srst(rst),
129
+
130
+ .wr_en(wr_en),
131
+ .din(din),
132
+ .prog_full(prog_full),
133
+ .rd_en(rd_en),
134
+ .dout(dout),
135
+ .empty(empty),
136
+ .data_count(data_count)
137
+ );
138
+ end
139
+ else if(FIFO_WIDTH == 576 && FIFO_DEPTH == 32) begin : GEN_SYNC_FIFO_576W_32D
140
+ SyncFIFO_576w_32d SyncFIFO_576w_32d_Inst(
141
+ .clk(clk),
142
+ .srst(rst),
143
+
144
+ .wr_en(wr_en),
145
+ .din(din),
146
+ .prog_full(prog_full),
147
+ .rd_en(rd_en),
148
+ .dout(dout),
149
+ .empty(empty),
150
+ .data_count(data_count)
151
+ );
152
+ end
153
+ else if(FIFO_WIDTH == 6 && FIFO_DEPTH == 64) begin : GEN_SYNC_FIFO_6W_64D
154
+ SyncFIFO_6w_64d SyncFIFO_6w_64d_Inst(
155
+ .clk(clk),
156
+ .srst(rst),
157
+
158
+ .wr_en(wr_en),
159
+ .din(din),
160
+ .prog_full(prog_full),
161
+ .rd_en(rd_en),
162
+ .dout(dout),
163
+ .empty(empty),
164
+ .data_count(data_count)
165
+ );
166
+ end
167
+ else if(FIFO_WIDTH == 9 && FIFO_DEPTH == 512) begin : GEN_SYNC_FIFO_9W_512D
168
+ SyncFIFO_9w_512d SyncFIFO_9w_512d_Inst(
169
+ .clk(clk),
170
+ .srst(rst),
171
+
172
+ .wr_en(wr_en),
173
+ .din(din),
174
+ .prog_full(prog_full),
175
+ .rd_en(rd_en),
176
+ .dout(dout),
177
+ .empty(empty),
178
+ .data_count(data_count)
179
+ );
180
+ end
181
+ end
182
+ else begin //Register File
183
+ //Instantiate RegFile FIFO
184
+ SyncFIFO_2Port_SRAM #(
185
+ .DATA_WIDTH(FIFO_WIDTH),
186
+ .FIFO_DEPTH(FIFO_DEPTH)
187
+ )
188
+ SyncFIFO_RegFile_Inst
189
+ (
190
+ .clk(clk),
191
+ .rst(rst),
192
+
193
+ .wr_en(wr_en),
194
+ .din(din),
195
+ .prog_full(prog_full),
196
+
197
+ .rd_en(rd_en),
198
+ .dout(dout),
199
+ .empty(empty),
200
+ .data_count(data_count)
201
+ );
202
+ end
203
+ endgenerate
204
+
205
+ /*Debug subsystem : Begin*/
206
+ `ifdef DEBUG_ON
207
+
208
+ `endif
209
+ /*Debug subsystem : End*/
210
+
211
+ endmodule
ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Common/slice/gp_slice.v ADDED
@@ -0,0 +1,157 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ // general purpose slice
2
+
3
+ module gp_slice #(
4
+ parameter PAYLD_WIDTH = 32'd32,
5
+ parameter MODE = 0, // slice mode: 0 -- full, 1 -- forward, 2 -- reverse, 3 -- bypass
6
+ parameter SYNC_RESET = 0
7
+ )
8
+ (
9
+ input clk,
10
+ input rst_n,
11
+
12
+ input vld_m,
13
+ output rdy_m,
14
+ input [PAYLD_WIDTH-1:0] payld_m,
15
+ output vld_s,
16
+ input rdy_s,
17
+ output [PAYLD_WIDTH-1:0] payld_s
18
+ );
19
+
20
+ wire rst_n_sync;
21
+
22
+ generate
23
+ if (SYNC_RESET) begin: reset_sync
24
+
25
+ reset_sync #(
26
+ .SYNC_MODE (1 )
27
+ ) u_reset_sync (
28
+ .rstn_d (rst_n_sync ),
29
+ .rstn_s (rst_n ),
30
+ .clk_d (clk )
31
+ );
32
+
33
+ end
34
+ else begin: reset_no_sync
35
+
36
+ assign rst_n_sync = rst_n;
37
+
38
+ end
39
+ endgenerate
40
+
41
+ generate if (MODE == 0) begin: FUL_MODE
42
+
43
+ reg [PAYLD_WIDTH-1:0] slice_a;
44
+ reg valid_a;
45
+ reg [PAYLD_WIDTH-1:0] slice_b;
46
+ reg valid_b;
47
+ reg sel_b;
48
+
49
+ assign rdy_m = (~valid_a) | (~valid_b);
50
+
51
+ assign vld_s = valid_a | valid_b;
52
+ assign payld_s = sel_b ? slice_b : slice_a;
53
+
54
+ always @(posedge clk or negedge rst_n_sync)
55
+ begin
56
+ if (!rst_n_sync) begin
57
+ sel_b <= `TD 1'b0;
58
+ end
59
+ else if (vld_s & rdy_s) begin
60
+ sel_b <= `TD ~sel_b;
61
+ end
62
+ end
63
+
64
+ always @(posedge clk or negedge rst_n_sync)
65
+ begin
66
+ if (!rst_n_sync) begin
67
+ slice_a <= `TD {PAYLD_WIDTH{1'b0}};
68
+ valid_a <= `TD 1'b0;
69
+ end
70
+ else if ((~valid_a) & (valid_b | (~sel_b)) & vld_m) begin
71
+ slice_a <= `TD payld_m;
72
+ valid_a <= `TD 1'b1;
73
+ end
74
+ else if (valid_a & (~sel_b) & rdy_s) begin
75
+ valid_a <= `TD 1'b0;
76
+ end
77
+ end
78
+
79
+ always @(posedge clk or negedge rst_n_sync)
80
+ begin
81
+ if (!rst_n_sync) begin
82
+ slice_b <= `TD {PAYLD_WIDTH{1'b0}};
83
+ valid_b <= `TD 1'b0;
84
+ end
85
+ else if ((~valid_b) & (valid_a | sel_b) & vld_m) begin
86
+ slice_b <= `TD payld_m;
87
+ valid_b <= `TD 1'b1;
88
+ end
89
+ else if (valid_b & sel_b & rdy_s) begin
90
+ valid_b <= `TD 1'b0;
91
+ end
92
+ end
93
+
94
+ end
95
+ else if (MODE == 1) begin: FWD_MODE
96
+
97
+ reg [PAYLD_WIDTH-1:0] slice;
98
+ reg valid;
99
+
100
+ assign rdy_m = ~valid | rdy_s;
101
+
102
+ assign vld_s = valid;
103
+ assign payld_s = slice;
104
+
105
+ always @(posedge clk or negedge rst_n_sync)
106
+ begin
107
+ if (!rst_n_sync) begin
108
+ slice <= `TD {PAYLD_WIDTH{1'b0}};
109
+ valid <= `TD 1'b0;
110
+ end
111
+ else if (vld_m & rdy_m) begin
112
+ slice <= `TD payld_m;
113
+ valid <= `TD 1'b1;
114
+ end
115
+ else if (vld_s & rdy_s) begin
116
+ valid <= `TD 1'b0;
117
+ end
118
+ end
119
+
120
+ end
121
+ else if (MODE == 2) begin: REV_MODE
122
+
123
+ reg [PAYLD_WIDTH-1:0] slice;
124
+ reg valid;
125
+
126
+ assign rdy_m = ~valid;
127
+
128
+ assign vld_s = valid | vld_m;
129
+ assign payld_s = valid ? slice : payld_m;
130
+
131
+ always @(posedge clk or negedge rst_n_sync)
132
+ begin
133
+ if (!rst_n_sync) begin
134
+ slice <= `TD {PAYLD_WIDTH{1'b0}};
135
+ valid <= `TD 1'b0;
136
+ end
137
+ else if (vld_m & rdy_m & (~rdy_s)) begin
138
+ slice <= `TD payld_m;
139
+ valid <= `TD 1'b1;
140
+ end
141
+ else if (valid & rdy_s) begin
142
+ valid <= `TD 1'b0;
143
+ end
144
+ end
145
+
146
+ end
147
+ else begin: BYP_MODE
148
+
149
+ assign rdy_m = rdy_s;
150
+
151
+ assign vld_s = vld_m;
152
+ assign payld_s = payld_m;
153
+
154
+ end
155
+ endgenerate
156
+
157
+ endmodule
ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Common/slice/gp_slice_ml.v ADDED
@@ -0,0 +1,55 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ // multi-level general purpose slice
2
+
3
+ module gp_slice_ml #(
4
+ parameter NUM_LEVELS = 1,
5
+ parameter PAYLD_WIDTH = 32'd32,
6
+ parameter MODE = 0, // slice mode: 0 -- full, 1 -- forward, 2 -- reverse, 3 -- bypass
7
+ parameter SYNC_RESET = 0
8
+ )
9
+ (
10
+ input clk,
11
+ input rst_n,
12
+
13
+ input vld_m,
14
+ output rdy_m,
15
+ input [PAYLD_WIDTH-1:0] payld_m,
16
+ output vld_s,
17
+ input rdy_s,
18
+ output [PAYLD_WIDTH-1:0] payld_s
19
+ );
20
+
21
+ wire vld[NUM_LEVELS:0];
22
+ wire rdy[NUM_LEVELS:0];
23
+ wire [PAYLD_WIDTH-1:0] payld[NUM_LEVELS:0];
24
+
25
+ genvar i;
26
+
27
+ assign vld[0] = vld_m;
28
+ assign rdy_m = rdy[0];
29
+ assign payld[0] = payld_m;
30
+
31
+ assign vld_s = vld[NUM_LEVELS];
32
+ assign rdy[NUM_LEVELS] = rdy_s;
33
+ assign payld_s = payld[NUM_LEVELS];
34
+
35
+ generate for (i=0; i<NUM_LEVELS; i=i+1) begin: slice
36
+
37
+ gp_slice #(
38
+ .PAYLD_WIDTH (PAYLD_WIDTH ),
39
+ .MODE (MODE ),
40
+ .SYNC_RESET (SYNC_RESET )
41
+ ) u_gp_slice (
42
+ .clk (clk ),
43
+ .rst_n (rst_n ),
44
+ .vld_m (vld[i] ),
45
+ .rdy_m (rdy[i] ),
46
+ .payld_m (payld[i] ),
47
+ .vld_s (vld[i+1] ),
48
+ .rdy_s (rdy[i+1] ),
49
+ .payld_s (payld[i+1] )
50
+ );
51
+
52
+ end
53
+ endgenerate
54
+
55
+ endmodule
ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Common/st_demux.v ADDED
@@ -0,0 +1,333 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ `timescale 1ns / 100ps
2
+ //*************************************************************************
3
+ // > File : st_demux.v
4
+ // > Author : Kangning
5
+ // > Date : 2022-12-02
6
+ // > Note : demux one channel into multiply channel.
7
+ //*************************************************************************
8
+
9
+ module st_demux #(
10
+ parameter CHNL_NUM = 8 , // number of slave signals to arbit
11
+ parameter CHNL_NUM_LOG = 3 ,
12
+ parameter TUSER_WIDTH = 128,
13
+ parameter TDATA_WIDTH = 256
14
+ ) (
15
+ input wire clk , // i, 1
16
+ input wire rst_n, // i, 1
17
+
18
+ input wire nxt_chnl_vld, // i, 1
19
+ input wire [7 : 0] nxt_chnl_sel, // i, 8
20
+
21
+ /* -------Slave AXIS Interface{begin}------- */
22
+ input wire s_axis_demux_valid, // i, 1
23
+ input wire s_axis_demux_last , // i, 1
24
+ input wire [TDATA_WIDTH - 1 : 0] s_axis_demux_data , // i, TDATA_WIDTH
25
+ input wire [TUSER_WIDTH - 1 : 0] s_axis_demux_head , // i, TUSER_WIDTH
26
+ output wire s_axis_demux_ready, // o, 1
27
+ /* -------Slave AXIS Interface{end}------- */
28
+
29
+ /* ------- Master AXIS Interface{begin} ------- */
30
+ output wire [CHNL_NUM * 1 - 1 : 0] m_axis_demux_valid, // o, CHNL_NUM * 1
31
+ output wire [CHNL_NUM * 1 - 1 : 0] m_axis_demux_last , // o, CHNL_NUM * 1
32
+ output wire [CHNL_NUM * TDATA_WIDTH - 1 : 0] m_axis_demux_data , // o, CHNL_NUM * TDATA_WIDTH
33
+ output wire [CHNL_NUM * TUSER_WIDTH - 1 : 0] m_axis_demux_head , // o, CHNL_NUM * TUSER_WIDTH
34
+ input wire [CHNL_NUM * 1 - 1 : 0] m_axis_demux_ready // i, CHNL_NUM * 1
35
+ /* ------- Master AXIS Interface{end} ------- */
36
+
37
+ );
38
+
39
+ /* -------State relevant in FSM{begin}------- */
40
+ localparam IDLE = 2'b01,
41
+ TRANS = 2'b10;
42
+
43
+ reg [1:0] cur_state;
44
+ reg [1:0] nxt_state;
45
+
46
+ wire is_idle, is_trans;
47
+ /* -------State relevant in FSM{end}------- */
48
+
49
+ /* --------Channel selection{begin}-------- */
50
+ reg [CHNL_NUM_LOG-1:0] sel;
51
+ /* --------Channel selection{end}-------- */
52
+
53
+ //-----------------------------------------------------------------------------------------------------------------------------------------------------------------------//
54
+
55
+ /* --------Channel selection{begin}--------- */
56
+ always @(posedge clk, negedge rst_n) begin
57
+ if (~rst_n) begin
58
+ sel <= `TD 8'd0;
59
+ end
60
+ else if ((is_idle & nxt_chnl_vld) ||
61
+ (is_trans & s_axis_demux_last & s_axis_demux_valid & s_axis_demux_ready & nxt_chnl_vld)) begin
62
+ sel <= `TD nxt_chnl_sel;
63
+ end
64
+ end
65
+
66
+ // assign mem_addr = s_axis_demux_head[63:32];
67
+ // assign nxt_chnl_sel = s_axis_demux_valid ? (mem_addr[13:12] == 2'b11) : 0;
68
+ /* --------Channel selection{end}--------- */
69
+
70
+ /* -------{DEMUX FSM}begin------- */
71
+ /******************** Stage 1: State Register **********************/
72
+ assign is_idle = (cur_state == IDLE );
73
+ assign is_trans = (cur_state == TRANS);
74
+
75
+ always @(posedge clk, negedge rst_n) begin
76
+ if(~rst_n)
77
+ cur_state <= `TD IDLE;
78
+ else
79
+ cur_state <= `TD nxt_state;
80
+ end
81
+
82
+ /******************** Stage 2: State Transition **********************/
83
+ always @(*) begin
84
+ case(cur_state)
85
+ IDLE: begin
86
+ if (nxt_chnl_vld) begin
87
+ nxt_state = TRANS;
88
+ end
89
+ else begin
90
+ nxt_state = IDLE;
91
+ end
92
+ end
93
+ TRANS: begin
94
+ if (s_axis_demux_last & s_axis_demux_valid & s_axis_demux_ready & nxt_chnl_vld) begin
95
+ nxt_state = TRANS;
96
+ end
97
+ else if (s_axis_demux_last & s_axis_demux_valid & s_axis_demux_ready) begin
98
+ nxt_state = IDLE;
99
+ end
100
+ else begin
101
+ nxt_state = TRANS;
102
+ end
103
+ end
104
+ default: begin
105
+ nxt_state = IDLE;
106
+ end
107
+ endcase
108
+ end
109
+ /******************** Stage 3: Output **********************/
110
+
111
+ /* -------Generate block{begin}------- */
112
+ /* This is used for different Channel Numbers, the default Number is 4
113
+ */
114
+ generate
115
+ if (CHNL_NUM == 16) begin:CHNL_DEMUX_16
116
+
117
+ assign s_axis_demux_ready = ((sel == 0) & is_trans & m_axis_demux_ready[0]) |
118
+ ((sel == 1) & is_trans & m_axis_demux_ready[1]) |
119
+ ((sel == 2) & is_trans & m_axis_demux_ready[2]) |
120
+ ((sel == 3) & is_trans & m_axis_demux_ready[3]) |
121
+ ((sel == 4) & is_trans & m_axis_demux_ready[4]) |
122
+ ((sel == 5) & is_trans & m_axis_demux_ready[5]) |
123
+ ((sel == 6) & is_trans & m_axis_demux_ready[6]) |
124
+ ((sel == 7) & is_trans & m_axis_demux_ready[7]) |
125
+ ((sel == 8) & is_trans & m_axis_demux_ready[8]) |
126
+ ((sel == 9) & is_trans & m_axis_demux_ready[9]) |
127
+ ((sel == 10) & is_trans & m_axis_demux_ready[10])|
128
+ ((sel == 11) & is_trans & m_axis_demux_ready[11])|
129
+ ((sel == 12) & is_trans & m_axis_demux_ready[12])|
130
+ ((sel == 13) & is_trans & m_axis_demux_ready[13])|
131
+ ((sel == 14) & is_trans & m_axis_demux_ready[14])|
132
+ ((sel == 15) & is_trans & m_axis_demux_ready[15]);
133
+
134
+ end // CHNL_DEMUX_16
135
+ else if (CHNL_NUM == 15) begin:CHNL_DEMUX_15
136
+
137
+ assign s_axis_demux_ready = ((sel == 0) & is_trans & m_axis_demux_ready[0]) |
138
+ ((sel == 1) & is_trans & m_axis_demux_ready[1]) |
139
+ ((sel == 2) & is_trans & m_axis_demux_ready[2]) |
140
+ ((sel == 3) & is_trans & m_axis_demux_ready[3]) |
141
+ ((sel == 4) & is_trans & m_axis_demux_ready[4]) |
142
+ ((sel == 5) & is_trans & m_axis_demux_ready[5]) |
143
+ ((sel == 6) & is_trans & m_axis_demux_ready[6]) |
144
+ ((sel == 7) & is_trans & m_axis_demux_ready[7]) |
145
+ ((sel == 8) & is_trans & m_axis_demux_ready[8]) |
146
+ ((sel == 9) & is_trans & m_axis_demux_ready[9]) |
147
+ ((sel == 10) & is_trans & m_axis_demux_ready[10])|
148
+ ((sel == 11) & is_trans & m_axis_demux_ready[11])|
149
+ ((sel == 12) & is_trans & m_axis_demux_ready[12])|
150
+ ((sel == 13) & is_trans & m_axis_demux_ready[13])|
151
+ ((sel == 14) & is_trans & m_axis_demux_ready[14]);
152
+
153
+ end // CHNL_DEMUX_15
154
+ else if (CHNL_NUM == 14) begin:CHNL_DEMUX_14
155
+
156
+ assign s_axis_demux_ready = ((sel == 0) & is_trans & m_axis_demux_ready[0]) |
157
+ ((sel == 1) & is_trans & m_axis_demux_ready[1]) |
158
+ ((sel == 2) & is_trans & m_axis_demux_ready[2]) |
159
+ ((sel == 3) & is_trans & m_axis_demux_ready[3]) |
160
+ ((sel == 4) & is_trans & m_axis_demux_ready[4]) |
161
+ ((sel == 5) & is_trans & m_axis_demux_ready[5]) |
162
+ ((sel == 6) & is_trans & m_axis_demux_ready[6]) |
163
+ ((sel == 7) & is_trans & m_axis_demux_ready[7]) |
164
+ ((sel == 8) & is_trans & m_axis_demux_ready[8]) |
165
+ ((sel == 9) & is_trans & m_axis_demux_ready[9]) |
166
+ ((sel == 10) & is_trans & m_axis_demux_ready[10])|
167
+ ((sel == 11) & is_trans & m_axis_demux_ready[11])|
168
+ ((sel == 12) & is_trans & m_axis_demux_ready[12])|
169
+ ((sel == 13) & is_trans & m_axis_demux_ready[13]);
170
+
171
+ end // CHNL_DEMUX_14
172
+ else if (CHNL_NUM == 13) begin:CHNL_DEMUX_13
173
+
174
+ assign s_axis_demux_ready = ((sel == 0) & is_trans & m_axis_demux_ready[0]) |
175
+ ((sel == 1) & is_trans & m_axis_demux_ready[1]) |
176
+ ((sel == 2) & is_trans & m_axis_demux_ready[2]) |
177
+ ((sel == 3) & is_trans & m_axis_demux_ready[3]) |
178
+ ((sel == 4) & is_trans & m_axis_demux_ready[4]) |
179
+ ((sel == 5) & is_trans & m_axis_demux_ready[5]) |
180
+ ((sel == 6) & is_trans & m_axis_demux_ready[6]) |
181
+ ((sel == 7) & is_trans & m_axis_demux_ready[7]) |
182
+ ((sel == 8) & is_trans & m_axis_demux_ready[8]) |
183
+ ((sel == 9) & is_trans & m_axis_demux_ready[9]) |
184
+ ((sel == 10) & is_trans & m_axis_demux_ready[10])|
185
+ ((sel == 11) & is_trans & m_axis_demux_ready[11])|
186
+ ((sel == 12) & is_trans & m_axis_demux_ready[12]);
187
+
188
+ end // CHNL_DEMUX_13
189
+ else if (CHNL_NUM == 12) begin:CHNL_DEMUX_12
190
+
191
+ assign s_axis_demux_ready = ((sel == 0) & is_trans & m_axis_demux_ready[0]) |
192
+ ((sel == 1) & is_trans & m_axis_demux_ready[1]) |
193
+ ((sel == 2) & is_trans & m_axis_demux_ready[2]) |
194
+ ((sel == 3) & is_trans & m_axis_demux_ready[3]) |
195
+ ((sel == 4) & is_trans & m_axis_demux_ready[4]) |
196
+ ((sel == 5) & is_trans & m_axis_demux_ready[5]) |
197
+ ((sel == 6) & is_trans & m_axis_demux_ready[6]) |
198
+ ((sel == 7) & is_trans & m_axis_demux_ready[7]) |
199
+ ((sel == 8) & is_trans & m_axis_demux_ready[8]) |
200
+ ((sel == 9) & is_trans & m_axis_demux_ready[9]) |
201
+ ((sel == 10) & is_trans & m_axis_demux_ready[10])|
202
+ ((sel == 11) & is_trans & m_axis_demux_ready[11]);
203
+
204
+ end // CHNL_DEMUX_12
205
+ else if (CHNL_NUM == 11) begin:CHNL_DEMUX_11
206
+
207
+ assign s_axis_demux_ready = ((sel == 0) & is_trans & m_axis_demux_ready[0]) |
208
+ ((sel == 1) & is_trans & m_axis_demux_ready[1]) |
209
+ ((sel == 2) & is_trans & m_axis_demux_ready[2]) |
210
+ ((sel == 3) & is_trans & m_axis_demux_ready[3]) |
211
+ ((sel == 4) & is_trans & m_axis_demux_ready[4]) |
212
+ ((sel == 5) & is_trans & m_axis_demux_ready[5]) |
213
+ ((sel == 6) & is_trans & m_axis_demux_ready[6]) |
214
+ ((sel == 7) & is_trans & m_axis_demux_ready[7]) |
215
+ ((sel == 8) & is_trans & m_axis_demux_ready[8]) |
216
+ ((sel == 9) & is_trans & m_axis_demux_ready[9]) |
217
+ ((sel == 10) & is_trans & m_axis_demux_ready[10]);
218
+
219
+ end // CHNL_DEMUX_11
220
+ else if (CHNL_NUM == 10) begin:CHNL_DEMUX_10
221
+
222
+ assign s_axis_demux_ready = ((sel == 0) & is_trans & m_axis_demux_ready[0]) |
223
+ ((sel == 1) & is_trans & m_axis_demux_ready[1]) |
224
+ ((sel == 2) & is_trans & m_axis_demux_ready[2]) |
225
+ ((sel == 3) & is_trans & m_axis_demux_ready[3]) |
226
+ ((sel == 4) & is_trans & m_axis_demux_ready[4]) |
227
+ ((sel == 5) & is_trans & m_axis_demux_ready[5]) |
228
+ ((sel == 6) & is_trans & m_axis_demux_ready[6]) |
229
+ ((sel == 7) & is_trans & m_axis_demux_ready[7]) |
230
+ ((sel == 8) & is_trans & m_axis_demux_ready[8]) |
231
+ ((sel == 9) & is_trans & m_axis_demux_ready[9]);
232
+
233
+ end // CHNL_DEMUX_10
234
+ else if (CHNL_NUM == 9) begin:CHNL_DEMUX_9
235
+
236
+ assign s_axis_demux_ready = ((sel == 0) & is_trans & m_axis_demux_ready[0]) |
237
+ ((sel == 1) & is_trans & m_axis_demux_ready[1]) |
238
+ ((sel == 2) & is_trans & m_axis_demux_ready[2]) |
239
+ ((sel == 3) & is_trans & m_axis_demux_ready[3]) |
240
+ ((sel == 4) & is_trans & m_axis_demux_ready[4]) |
241
+ ((sel == 5) & is_trans & m_axis_demux_ready[5]) |
242
+ ((sel == 6) & is_trans & m_axis_demux_ready[6]) |
243
+ ((sel == 7) & is_trans & m_axis_demux_ready[7]) |
244
+ ((sel == 8) & is_trans & m_axis_demux_ready[8]);
245
+
246
+ end // CHNL_DEMUX_9
247
+ else if (CHNL_NUM == 8) begin:CHNL_DEMUX_8
248
+
249
+ assign s_axis_demux_ready = ((sel == 0) & is_trans & m_axis_demux_ready[0]) |
250
+ ((sel == 1) & is_trans & m_axis_demux_ready[1]) |
251
+ ((sel == 2) & is_trans & m_axis_demux_ready[2]) |
252
+ ((sel == 3) & is_trans & m_axis_demux_ready[3]) |
253
+ ((sel == 4) & is_trans & m_axis_demux_ready[4]) |
254
+ ((sel == 5) & is_trans & m_axis_demux_ready[5]) |
255
+ ((sel == 6) & is_trans & m_axis_demux_ready[6]) |
256
+ ((sel == 7) & is_trans & m_axis_demux_ready[7]);
257
+
258
+ end // CHNL_DEMUX_8
259
+ else if (CHNL_NUM == 7) begin:CHNL_DEMUX_7
260
+
261
+ assign s_axis_demux_ready = ((sel == 0) & is_trans & m_axis_demux_ready[0]) |
262
+ ((sel == 1) & is_trans & m_axis_demux_ready[1]) |
263
+ ((sel == 2) & is_trans & m_axis_demux_ready[2]) |
264
+ ((sel == 3) & is_trans & m_axis_demux_ready[3]) |
265
+ ((sel == 4) & is_trans & m_axis_demux_ready[4]) |
266
+ ((sel == 5) & is_trans & m_axis_demux_ready[5]) |
267
+ ((sel == 6) & is_trans & m_axis_demux_ready[6]);
268
+
269
+ end // CHNL_DEMUX_7
270
+ else if (CHNL_NUM == 6) begin:CHNL_DEMUX_6
271
+
272
+ assign s_axis_demux_ready = ((sel == 0) & is_trans & m_axis_demux_ready[0]) |
273
+ ((sel == 1) & is_trans & m_axis_demux_ready[1]) |
274
+ ((sel == 2) & is_trans & m_axis_demux_ready[2]) |
275
+ ((sel == 3) & is_trans & m_axis_demux_ready[3]) |
276
+ ((sel == 4) & is_trans & m_axis_demux_ready[4]) |
277
+ ((sel == 5) & is_trans & m_axis_demux_ready[5]);
278
+
279
+ end // CHNL_DEMUX_6
280
+ else if (CHNL_NUM == 5) begin:CHNL_DEMUX_5
281
+
282
+ assign s_axis_demux_ready = ((sel == 0) & is_trans & m_axis_demux_ready[0]) |
283
+ ((sel == 1) & is_trans & m_axis_demux_ready[1]) |
284
+ ((sel == 2) & is_trans & m_axis_demux_ready[2]) |
285
+ ((sel == 3) & is_trans & m_axis_demux_ready[3]) |
286
+ ((sel == 4) & is_trans & m_axis_demux_ready[4]);
287
+
288
+ end // CHNL_DEMUX_5
289
+ else if (CHNL_NUM == 4) begin:CHNL_DEMUX_4
290
+
291
+ assign s_axis_demux_ready = ((sel == 0) & is_trans & m_axis_demux_ready[0]) |
292
+ ((sel == 1) & is_trans & m_axis_demux_ready[1]) |
293
+ ((sel == 2) & is_trans & m_axis_demux_ready[2]) |
294
+ ((sel == 3) & is_trans & m_axis_demux_ready[3]);
295
+
296
+ end // CHNL_DEMUX_4
297
+ else if (CHNL_NUM == 3) begin:CHNL_DEMUX_3
298
+
299
+ assign s_axis_demux_ready = ((sel == 0) & is_trans & m_axis_demux_ready[0]) |
300
+ ((sel == 1) & is_trans & m_axis_demux_ready[1]) |
301
+ ((sel == 2) & is_trans & m_axis_demux_ready[2]);
302
+
303
+ end // CHNL_DEMUX_3
304
+ else if (CHNL_NUM == 2) begin:CHNL_DEMUX_2
305
+
306
+ assign s_axis_demux_ready = ((sel == 0) & is_trans & m_axis_demux_ready[0]) |
307
+ ((sel == 1) & is_trans & m_axis_demux_ready[1]);
308
+
309
+ end // CHNL_DEMUX_2
310
+ endgenerate
311
+ /*
312
+ This is used for different Channel Numbers, the default Number is 4 */
313
+ /* -------Generate block{end}------- */
314
+
315
+ /* -------Generate block{begin}------- */
316
+ /* This is used for different Channel Numbers, the default Number is 4
317
+ */
318
+ genvar i;
319
+ generate
320
+ for (i = 0; i < CHNL_NUM; i = i + 1) begin:CHNL_DEMUX_ASSIGN
321
+
322
+ assign m_axis_demux_valid[(i+1)*1 -1:i*1 ] = ((i == sel) & is_trans) ? s_axis_demux_valid : 0;
323
+ assign m_axis_demux_last [(i+1)*1 -1:i*1 ] = ((i == sel) & is_trans) ? s_axis_demux_last : 0;
324
+ assign m_axis_demux_data [(i+1)*TDATA_WIDTH -1:i*TDATA_WIDTH] = ((i == sel) & is_trans) ? s_axis_demux_data : 0;
325
+ assign m_axis_demux_head [(i+1)*TUSER_WIDTH -1:i*TUSER_WIDTH] = ((i == sel) & is_trans) ? s_axis_demux_head : 0;
326
+
327
+ end
328
+ endgenerate
329
+ /*
330
+ This is used for different Channel Numbers, the default Number is 4 */
331
+ /* -------Generate block{end}------- */
332
+
333
+ endmodule
ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Common/st_mux.v ADDED
@@ -0,0 +1,791 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ `timescale 1ns / 100ps
2
+ //*************************************************************************
3
+ // > File Name: st_mux.v
4
+ // > Author : Kangning
5
+ // > Date : 2022-11-14
6
+ // > Note : st_mux is used to arbiter different channels for data transmission
7
+ // > V1.1 - 2021-02-04 : Add supporting for five channels
8
+ // > V1.5 - 2022-04-24 : Parameterized arbiter, supports arbitrary number of channels
9
+ // > V2.0 - 2022-11-14 : A generalized string mux logic.
10
+ //*************************************************************************
11
+
12
+ module st_mux #(
13
+ parameter CHNL_NUM = 8 , // number of slave signals to arbit
14
+ parameter CHNL_NUM_LOG = 3 ,
15
+ parameter TUSER_WIDTH = 128,
16
+ parameter TDATA_WIDTH = 256
17
+ ) (
18
+ input wire clk ,
19
+ input wire rst_n,
20
+
21
+ /* -------Slave AXIS Interface{begin}------- */
22
+ input wire [CHNL_NUM * 1 -1:0] s_axis_mux_tvalid, // i, CHNL_NUM * 1
23
+ input wire [CHNL_NUM * 1 -1:0] s_axis_mux_tlast , // i, CHNL_NUM * 1
24
+ input wire [CHNL_NUM * TDATA_WIDTH-1:0] s_axis_mux_tdata , // i, CHNL_NUM * TDATA_WIDTH
25
+ input wire [CHNL_NUM * TUSER_WIDTH-1:0] s_axis_mux_tuser , // i, CHNL_NUM * TUSER_WIDTH
26
+ output wire [CHNL_NUM * 1 -1:0] s_axis_mux_tready, // o, CHNL_NUM * 1
27
+ /* -------Slave AXIS Interface{end}------- */
28
+
29
+ /* ------- Master AXIS Interface{begin} ------- */
30
+ output wire m_axis_mux_tvalid, // o, 1
31
+ output wire m_axis_mux_tlast , // o, 1
32
+ output wire [TDATA_WIDTH-1:0] m_axis_mux_tdata , // o, TDATA_WIDTH
33
+ output wire [TUSER_WIDTH-1:0] m_axis_mux_tuser , // o, TUSER_WIDTH
34
+ input wire m_axis_mux_tready // i, 1
35
+ /* ------- Master AXIS Interface{end} ------- */
36
+
37
+ `ifdef SIMULATION
38
+ /* ------- Debug interface {begin}------- */
39
+ /* | reserved | idx | end | out |
40
+ * | 255:CHNL_NUM_LOG+2 | CHNL_NUM_LOG+2-1:2 | 1 | 0 |
41
+ */
42
+ ,output wire [255:0] debug
43
+ /* ------- Debug interface {end}------- */
44
+ `endif
45
+
46
+ );
47
+
48
+ /* ------- Next scheduled channel{begin}------- */
49
+ reg [CHNL_NUM_LOG-1:0] chnl_idx_reg; // Index of channel to be scheduled next time, valid only in REQ_TRANS state.
50
+ reg [CHNL_NUM_LOG-1:0] chnl_idx; // Index of channel to be scheduled next time, valid all the time.
51
+ reg [CHNL_NUM_LOG-1:0] last_chnl; // Index of last selected channel.
52
+
53
+
54
+ /**
55
+ * hit relevant channel is hit (hit_priority[3] == 1 means that last
56
+ * selected channel is still valid.
57
+ */
58
+ wire [CHNL_NUM-1:0] hit_priority;
59
+
60
+ /**
61
+ * index of channel priority in next time, e.g. nxt_priority[1]
62
+ * indicates the index of next next channel; while nxt_priority[0]
63
+ * indicates the index of next channel.
64
+ */
65
+ wire [CHNL_NUM_LOG-1:0] nxt_priority[CHNL_NUM-1:0];
66
+
67
+ wire s_channel_tvalid[CHNL_NUM-1:0];
68
+ wire s_channel_tlast [CHNL_NUM-1:0];
69
+ wire [TDATA_WIDTH-1:0] s_channel_tdata [CHNL_NUM-1:0];
70
+ wire [TUSER_WIDTH-1:0] s_channel_tuser [CHNL_NUM-1:0];
71
+
72
+
73
+ wire req_last; // last beat of the request
74
+ /* ------- Next scheduled channel{end}------- */
75
+
76
+ /* -------State relevant in FSM{begin}------- */
77
+ localparam IDLE = 3'b001,
78
+ SCHEDULE = 3'b010,
79
+ REQ_TRANS = 3'b100;
80
+
81
+ reg [2:0] cur_state;
82
+ reg [2:0] nxt_state;
83
+
84
+ wire is_idle, is_schedule, is_req_trans;
85
+ wire j_req_trans;
86
+ // wire j_schedule;
87
+ /* -------State relevant in FSM{end}------- */
88
+
89
+ /* ------------------------------------------------------------------------ */
90
+
91
+ `ifdef SIMULATION
92
+ /* ------- Debug interface {begin}------- */
93
+ /* | reserved | idx | end | out |
94
+ * | 255:CHNL_NUM_LOG+2 | CHNL_NUM_LOG+2-1:2 | 1 | 0 |
95
+ */
96
+ assign debug = {{254-CHNL_NUM_LOG{1'd0}},
97
+ chnl_idx,
98
+ m_axis_mux_tvalid & m_axis_mux_tready & m_axis_mux_tlast,
99
+ m_axis_mux_tvalid & m_axis_mux_tready};
100
+ /* ------- Debug interface {end}------- */
101
+ `endif
102
+
103
+
104
+
105
+ /* -------Find next channel{begin}------- */
106
+
107
+ always @(posedge clk, negedge rst_n) begin
108
+ if (~rst_n) begin
109
+ last_chnl <= `TD {CHNL_NUM_LOG{1'd0}};
110
+ end
111
+ else if (req_last) begin
112
+ last_chnl <= `TD chnl_idx;
113
+ end
114
+ end
115
+
116
+ always @(posedge clk, negedge rst_n) begin
117
+ if (~rst_n) begin
118
+ chnl_idx_reg <= `TD {CHNL_NUM_LOG{1'd0}};
119
+ end
120
+ else if (j_req_trans) begin
121
+ chnl_idx_reg <= `TD chnl_idx;
122
+ end
123
+ end
124
+
125
+ /* -------Generate block{begin}------- */
126
+ genvar k;
127
+ generate
128
+ for (k = 0; k < CHNL_NUM; k = k + 1) begin:CHNL_PRIORITY
129
+
130
+ assign nxt_priority[k] = ((last_chnl + k + 1) >= CHNL_NUM) ?
131
+ (last_chnl + k + 1 - CHNL_NUM) : (last_chnl + k + 1);
132
+
133
+ end
134
+ endgenerate
135
+ /* -------Generate block{end}------- */
136
+
137
+
138
+ /* -------Generate block{begin}------- */
139
+ /* This is used for different Channel Numbers, the default Number is 5
140
+ */
141
+ generate
142
+ if (CHNL_NUM == 10) begin:CHNL_SEL_10
143
+
144
+ always @(*) begin
145
+ if (is_schedule) begin
146
+ case (last_chnl)
147
+ 0: chnl_idx = hit_priority[0] ? 1 :
148
+ hit_priority[1] ? 2 :
149
+ hit_priority[2] ? 3 :
150
+ hit_priority[3] ? 4 :
151
+ hit_priority[4] ? 5 :
152
+ hit_priority[5] ? 6 :
153
+ hit_priority[6] ? 7 :
154
+ hit_priority[7] ? 8 :
155
+ hit_priority[8] ? 9 :
156
+ hit_priority[9] ? 0 : 1 ; // last branch is chosen when no channel is valid.
157
+ 1: chnl_idx = hit_priority[0] ? 2 :
158
+ hit_priority[1] ? 3 :
159
+ hit_priority[2] ? 4 :
160
+ hit_priority[3] ? 5 :
161
+ hit_priority[4] ? 6 :
162
+ hit_priority[5] ? 7 :
163
+ hit_priority[6] ? 8 :
164
+ hit_priority[7] ? 9 :
165
+ hit_priority[8] ? 0 :
166
+ hit_priority[9] ? 1 : 2 ; // last branch is chosen when no channel is valid.
167
+ 2: chnl_idx = hit_priority[0] ? 3 :
168
+ hit_priority[1] ? 4 :
169
+ hit_priority[2] ? 5 :
170
+ hit_priority[3] ? 6 :
171
+ hit_priority[4] ? 7 :
172
+ hit_priority[5] ? 8 :
173
+ hit_priority[6] ? 9 :
174
+ hit_priority[7] ? 0 :
175
+ hit_priority[8] ? 1 :
176
+ hit_priority[9] ? 2 : 3 ; // last branch is chosen when no channel is valid.
177
+ 3: chnl_idx = hit_priority[0] ? 4 :
178
+ hit_priority[1] ? 5 :
179
+ hit_priority[2] ? 6 :
180
+ hit_priority[3] ? 7 :
181
+ hit_priority[4] ? 8 :
182
+ hit_priority[5] ? 9 :
183
+ hit_priority[6] ? 0 :
184
+ hit_priority[7] ? 1 :
185
+ hit_priority[8] ? 2 :
186
+ hit_priority[9] ? 3 : 4 ; // last branch is chosen when no channel is valid.
187
+ 4: chnl_idx = hit_priority[0] ? 5 :
188
+ hit_priority[1] ? 6 :
189
+ hit_priority[2] ? 7 :
190
+ hit_priority[3] ? 8 :
191
+ hit_priority[4] ? 9 :
192
+ hit_priority[5] ? 0 :
193
+ hit_priority[6] ? 1 :
194
+ hit_priority[7] ? 2 :
195
+ hit_priority[8] ? 3 :
196
+ hit_priority[9] ? 4 : 5 ; // last branch is chosen when no channel is valid.
197
+ 5: chnl_idx = hit_priority[0] ? 6 :
198
+ hit_priority[1] ? 7 :
199
+ hit_priority[2] ? 8 :
200
+ hit_priority[3] ? 9 :
201
+ hit_priority[4] ? 0 :
202
+ hit_priority[5] ? 1 :
203
+ hit_priority[6] ? 2 :
204
+ hit_priority[7] ? 3 :
205
+ hit_priority[8] ? 4 :
206
+ hit_priority[9] ? 5 : 6 ; // last branch is chosen when no channel is valid.
207
+ 6: chnl_idx = hit_priority[0] ? 7 :
208
+ hit_priority[1] ? 8 :
209
+ hit_priority[2] ? 9 :
210
+ hit_priority[3] ? 0 :
211
+ hit_priority[4] ? 1 :
212
+ hit_priority[5] ? 2 :
213
+ hit_priority[6] ? 3 :
214
+ hit_priority[7] ? 4 :
215
+ hit_priority[8] ? 5 :
216
+ hit_priority[9] ? 6 : 7 ; // last branch is chosen when no channel is valid.
217
+ 7: chnl_idx = hit_priority[0] ? 8 :
218
+ hit_priority[1] ? 9 :
219
+ hit_priority[2] ? 0 :
220
+ hit_priority[3] ? 1 :
221
+ hit_priority[4] ? 2 :
222
+ hit_priority[5] ? 3 :
223
+ hit_priority[6] ? 4 :
224
+ hit_priority[7] ? 5 :
225
+ hit_priority[8] ? 6 :
226
+ hit_priority[9] ? 7 : 8 ; // last branch is chosen when no channel is valid.
227
+ 8: chnl_idx = hit_priority[0] ? 9 :
228
+ hit_priority[1] ? 0 :
229
+ hit_priority[2] ? 1 :
230
+ hit_priority[3] ? 2 :
231
+ hit_priority[4] ? 3 :
232
+ hit_priority[5] ? 4 :
233
+ hit_priority[6] ? 5 :
234
+ hit_priority[7] ? 6 :
235
+ hit_priority[8] ? 7 :
236
+ hit_priority[9] ? 8 : 9 ; // last branch is chosen when no channel is valid.
237
+ 9: chnl_idx = hit_priority[0] ? 0 :
238
+ hit_priority[1] ? 1 :
239
+ hit_priority[2] ? 2 :
240
+ hit_priority[3] ? 3 :
241
+ hit_priority[4] ? 4 :
242
+ hit_priority[5] ? 5 :
243
+ hit_priority[6] ? 6 :
244
+ hit_priority[7] ? 7 :
245
+ hit_priority[8] ? 8 :
246
+ hit_priority[9] ? 9 : 0 ; // last branch is chosen when no channel is valid.
247
+ default: chnl_idx = {CHNL_NUM_LOG{1'd0}};
248
+ endcase
249
+ end
250
+ else begin
251
+ chnl_idx = chnl_idx_reg; // chosen in REQ_TRANS state
252
+ end
253
+ end
254
+
255
+ end // CHNL_NUM == 10
256
+ else if (CHNL_NUM == 9) begin:CHNL_SEL_9
257
+
258
+ always @(*) begin
259
+ if (is_schedule) begin
260
+ case (last_chnl)
261
+ 0: chnl_idx = hit_priority[0] ? 1 :
262
+ hit_priority[1] ? 2 :
263
+ hit_priority[2] ? 3 :
264
+ hit_priority[3] ? 4 :
265
+ hit_priority[4] ? 5 :
266
+ hit_priority[5] ? 6 :
267
+ hit_priority[6] ? 7 :
268
+ hit_priority[7] ? 8 :
269
+ hit_priority[8] ? 0 : 1 ; // last branch is chosen when no channel is valid.
270
+ 1: chnl_idx = hit_priority[0] ? 2 :
271
+ hit_priority[1] ? 3 :
272
+ hit_priority[2] ? 4 :
273
+ hit_priority[3] ? 5 :
274
+ hit_priority[4] ? 6 :
275
+ hit_priority[5] ? 7 :
276
+ hit_priority[6] ? 8 :
277
+ hit_priority[7] ? 0 :
278
+ hit_priority[8] ? 1 : 2 ; // last branch is chosen when no channel is valid.
279
+ 2: chnl_idx = hit_priority[0] ? 3 :
280
+ hit_priority[1] ? 4 :
281
+ hit_priority[2] ? 5 :
282
+ hit_priority[3] ? 6 :
283
+ hit_priority[4] ? 7 :
284
+ hit_priority[5] ? 8 :
285
+ hit_priority[6] ? 0 :
286
+ hit_priority[7] ? 1 :
287
+ hit_priority[8] ? 2 : 3 ; // last branch is chosen when no channel is valid.
288
+ 3: chnl_idx = hit_priority[0] ? 4 :
289
+ hit_priority[1] ? 5 :
290
+ hit_priority[2] ? 6 :
291
+ hit_priority[3] ? 7 :
292
+ hit_priority[4] ? 8 :
293
+ hit_priority[5] ? 0 :
294
+ hit_priority[6] ? 1 :
295
+ hit_priority[7] ? 2 :
296
+ hit_priority[8] ? 3 : 4 ; // last branch is chosen when no channel is valid.
297
+ 4: chnl_idx = hit_priority[0] ? 5 :
298
+ hit_priority[1] ? 6 :
299
+ hit_priority[2] ? 7 :
300
+ hit_priority[3] ? 8 :
301
+ hit_priority[4] ? 0 :
302
+ hit_priority[5] ? 1 :
303
+ hit_priority[6] ? 2 :
304
+ hit_priority[7] ? 3 :
305
+ hit_priority[8] ? 4 : 5 ; // last branch is chosen when no channel is valid.
306
+ 5: chnl_idx = hit_priority[0] ? 6 :
307
+ hit_priority[1] ? 7 :
308
+ hit_priority[2] ? 8 :
309
+ hit_priority[3] ? 0 :
310
+ hit_priority[4] ? 1 :
311
+ hit_priority[5] ? 2 :
312
+ hit_priority[6] ? 3 :
313
+ hit_priority[7] ? 4 :
314
+ hit_priority[8] ? 5 : 6 ; // last branch is chosen when no channel is valid.
315
+ 6: chnl_idx = hit_priority[0] ? 7 :
316
+ hit_priority[1] ? 8 :
317
+ hit_priority[2] ? 0 :
318
+ hit_priority[3] ? 1 :
319
+ hit_priority[4] ? 2 :
320
+ hit_priority[5] ? 3 :
321
+ hit_priority[6] ? 4 :
322
+ hit_priority[7] ? 5 :
323
+ hit_priority[8] ? 6 : 7 ; // last branch is chosen when no channel is valid.
324
+ 7: chnl_idx = hit_priority[0] ? 8 :
325
+ hit_priority[1] ? 0 :
326
+ hit_priority[2] ? 1 :
327
+ hit_priority[3] ? 2 :
328
+ hit_priority[4] ? 3 :
329
+ hit_priority[5] ? 4 :
330
+ hit_priority[6] ? 5 :
331
+ hit_priority[7] ? 6 :
332
+ hit_priority[8] ? 7 : 8 ; // last branch is chosen when no channel is valid.
333
+ 8: chnl_idx = hit_priority[0] ? 0 :
334
+ hit_priority[1] ? 1 :
335
+ hit_priority[2] ? 2 :
336
+ hit_priority[3] ? 3 :
337
+ hit_priority[4] ? 4 :
338
+ hit_priority[5] ? 5 :
339
+ hit_priority[6] ? 6 :
340
+ hit_priority[7] ? 7 :
341
+ hit_priority[8] ? 8 : 0 ; // last branch is chosen when no channel is valid.
342
+ default: chnl_idx = {CHNL_NUM_LOG{1'd0}};
343
+ endcase
344
+ end
345
+ else begin
346
+ chnl_idx = chnl_idx_reg; // chosen in REQ_TRANS state
347
+ end
348
+ end
349
+
350
+ end // CHNL_NUM == 9
351
+ else if (CHNL_NUM == 8) begin:CHNL_SEL_8
352
+
353
+ always @(*) begin
354
+ if (is_schedule) begin
355
+ case (last_chnl)
356
+ 0: chnl_idx = hit_priority[0] ? 1 :
357
+ hit_priority[1] ? 2 :
358
+ hit_priority[2] ? 3 :
359
+ hit_priority[3] ? 4 :
360
+ hit_priority[4] ? 5 :
361
+ hit_priority[5] ? 6 :
362
+ hit_priority[6] ? 7 :
363
+ hit_priority[7] ? 0 : 1 ; // last branch is chosen when no channel is valid.
364
+ 1: chnl_idx = hit_priority[0] ? 2 :
365
+ hit_priority[1] ? 3 :
366
+ hit_priority[2] ? 4 :
367
+ hit_priority[3] ? 5 :
368
+ hit_priority[4] ? 6 :
369
+ hit_priority[5] ? 7 :
370
+ hit_priority[6] ? 0 :
371
+ hit_priority[7] ? 1 : 2 ; // last branch is chosen when no channel is valid.
372
+ 2: chnl_idx = hit_priority[0] ? 3 :
373
+ hit_priority[1] ? 4 :
374
+ hit_priority[2] ? 5 :
375
+ hit_priority[3] ? 6 :
376
+ hit_priority[4] ? 7 :
377
+ hit_priority[5] ? 0 :
378
+ hit_priority[6] ? 1 :
379
+ hit_priority[7] ? 2 : 3 ; // last branch is chosen when no channel is valid.
380
+ 3: chnl_idx = hit_priority[0] ? 4 :
381
+ hit_priority[1] ? 5 :
382
+ hit_priority[2] ? 6 :
383
+ hit_priority[3] ? 7 :
384
+ hit_priority[4] ? 0 :
385
+ hit_priority[5] ? 1 :
386
+ hit_priority[6] ? 2 :
387
+ hit_priority[7] ? 3 : 4 ; // last branch is chosen when no channel is valid.
388
+ 4: chnl_idx = hit_priority[0] ? 5 :
389
+ hit_priority[1] ? 6 :
390
+ hit_priority[2] ? 7 :
391
+ hit_priority[3] ? 0 :
392
+ hit_priority[4] ? 1 :
393
+ hit_priority[5] ? 2 :
394
+ hit_priority[6] ? 3 :
395
+ hit_priority[7] ? 4 : 5 ; // last branch is chosen when no channel is valid.
396
+ 5: chnl_idx = hit_priority[0] ? 6 :
397
+ hit_priority[1] ? 7 :
398
+ hit_priority[2] ? 0 :
399
+ hit_priority[3] ? 1 :
400
+ hit_priority[4] ? 2 :
401
+ hit_priority[5] ? 3 :
402
+ hit_priority[6] ? 4 :
403
+ hit_priority[7] ? 5 : 6 ; // last branch is chosen when no channel is valid.
404
+ 6: chnl_idx = hit_priority[0] ? 7 :
405
+ hit_priority[1] ? 0 :
406
+ hit_priority[2] ? 1 :
407
+ hit_priority[3] ? 2 :
408
+ hit_priority[4] ? 3 :
409
+ hit_priority[5] ? 4 :
410
+ hit_priority[6] ? 5 :
411
+ hit_priority[7] ? 6 : 7 ; // last branch is chosen when no channel is valid.
412
+ 7: chnl_idx = hit_priority[0] ? 0 :
413
+ hit_priority[1] ? 1 :
414
+ hit_priority[2] ? 2 :
415
+ hit_priority[3] ? 3 :
416
+ hit_priority[4] ? 4 :
417
+ hit_priority[5] ? 5 :
418
+ hit_priority[6] ? 6 :
419
+ hit_priority[7] ? 7 : 0 ; // last branch is chosen when no channel is valid.
420
+ default: chnl_idx = {CHNL_NUM_LOG{1'd0}};
421
+ endcase
422
+ end
423
+ else begin
424
+ chnl_idx = chnl_idx_reg; // chosen in REQ_TRANS state
425
+ end
426
+ end
427
+
428
+ end // CHNL_NUM == 8
429
+ else if (CHNL_NUM == 7) begin:CHNL_SEL_7
430
+
431
+ always @(*) begin
432
+ if (is_schedule) begin
433
+ case (last_chnl)
434
+ 0: chnl_idx = hit_priority[0] ? 1 :
435
+ hit_priority[1] ? 2 :
436
+ hit_priority[2] ? 3 :
437
+ hit_priority[3] ? 4 :
438
+ hit_priority[4] ? 5 :
439
+ hit_priority[5] ? 6 :
440
+ hit_priority[6] ? 0 : 1 ; // last branch is chosen when no channel is valid.
441
+ 1: chnl_idx = hit_priority[0] ? 2 :
442
+ hit_priority[1] ? 3 :
443
+ hit_priority[2] ? 4 :
444
+ hit_priority[3] ? 5 :
445
+ hit_priority[4] ? 6 :
446
+ hit_priority[5] ? 0 :
447
+ hit_priority[6] ? 1 : 2 ; // last branch is chosen when no channel is valid.
448
+ 2: chnl_idx = hit_priority[0] ? 3 :
449
+ hit_priority[1] ? 4 :
450
+ hit_priority[2] ? 5 :
451
+ hit_priority[3] ? 6 :
452
+ hit_priority[4] ? 0 :
453
+ hit_priority[5] ? 1 :
454
+ hit_priority[6] ? 2 : 3 ; // last branch is chosen when no channel is valid.
455
+ 3: chnl_idx = hit_priority[0] ? 4 :
456
+ hit_priority[1] ? 5 :
457
+ hit_priority[2] ? 6 :
458
+ hit_priority[3] ? 0 :
459
+ hit_priority[4] ? 1 :
460
+ hit_priority[5] ? 2 :
461
+ hit_priority[6] ? 3 : 4 ; // last branch is chosen when no channel is valid.
462
+ 4: chnl_idx = hit_priority[0] ? 5 :
463
+ hit_priority[1] ? 6 :
464
+ hit_priority[2] ? 0 :
465
+ hit_priority[3] ? 1 :
466
+ hit_priority[4] ? 2 :
467
+ hit_priority[5] ? 3 :
468
+ hit_priority[6] ? 4 : 5 ; // last branch is chosen when no channel is valid.
469
+ 5: chnl_idx = hit_priority[0] ? 6 :
470
+ hit_priority[1] ? 0 :
471
+ hit_priority[2] ? 1 :
472
+ hit_priority[3] ? 2 :
473
+ hit_priority[4] ? 3 :
474
+ hit_priority[5] ? 4 :
475
+ hit_priority[6] ? 5 : 6 ; // last branch is chosen when no channel is valid.
476
+ 6: chnl_idx = hit_priority[0] ? 0 :
477
+ hit_priority[1] ? 1 :
478
+ hit_priority[2] ? 2 :
479
+ hit_priority[3] ? 3 :
480
+ hit_priority[4] ? 4 :
481
+ hit_priority[5] ? 5 :
482
+ hit_priority[6] ? 6 : 0 ; // last branch is chosen when no channel is valid.
483
+ default: chnl_idx = {CHNL_NUM_LOG{1'd0}};
484
+ endcase
485
+ end
486
+ else begin
487
+ chnl_idx = chnl_idx_reg; // chosen in REQ_TRANS state
488
+ end
489
+ end
490
+
491
+ end // CHNL_NUM == 7
492
+ else if (CHNL_NUM == 6) begin:CHNL_SEL_6
493
+
494
+ always @(*) begin
495
+ if (is_schedule) begin
496
+ case (last_chnl)
497
+ 0: chnl_idx = hit_priority[0] ? 1 :
498
+ hit_priority[1] ? 2 :
499
+ hit_priority[2] ? 3 :
500
+ hit_priority[3] ? 4 :
501
+ hit_priority[4] ? 5 :
502
+ hit_priority[5] ? 0 : 1 ; // last branch is chosen when no channel is valid.
503
+ 1: chnl_idx = hit_priority[0] ? 2 :
504
+ hit_priority[1] ? 3 :
505
+ hit_priority[2] ? 4 :
506
+ hit_priority[3] ? 5 :
507
+ hit_priority[4] ? 0 :
508
+ hit_priority[5] ? 1 : 2 ; // last branch is chosen when no channel is valid.
509
+ 2: chnl_idx = hit_priority[0] ? 3 :
510
+ hit_priority[1] ? 4 :
511
+ hit_priority[2] ? 5 :
512
+ hit_priority[3] ? 0 :
513
+ hit_priority[4] ? 1 :
514
+ hit_priority[5] ? 2 : 3 ; // last branch is chosen when no channel is valid.
515
+ 3: chnl_idx = hit_priority[0] ? 4 :
516
+ hit_priority[1] ? 5 :
517
+ hit_priority[2] ? 0 :
518
+ hit_priority[3] ? 1 :
519
+ hit_priority[4] ? 2 :
520
+ hit_priority[5] ? 3 : 4 ; // last branch is chosen when no channel is valid.
521
+ 4: chnl_idx = hit_priority[0] ? 5 :
522
+ hit_priority[1] ? 0 :
523
+ hit_priority[2] ? 1 :
524
+ hit_priority[3] ? 2 :
525
+ hit_priority[4] ? 3 :
526
+ hit_priority[5] ? 4 : 5 ; // last branch is chosen when no channel is valid.
527
+ 5: chnl_idx = hit_priority[0] ? 0 :
528
+ hit_priority[1] ? 1 :
529
+ hit_priority[2] ? 2 :
530
+ hit_priority[3] ? 3 :
531
+ hit_priority[4] ? 4 :
532
+ hit_priority[5] ? 5 : 0 ; // last branch is chosen when no channel is valid.
533
+ default: chnl_idx = {CHNL_NUM_LOG{1'd0}};
534
+ endcase
535
+ end
536
+ else begin
537
+ chnl_idx = chnl_idx_reg; // chosen in REQ_TRANS state
538
+ end
539
+ end
540
+
541
+ end // CHNL_NUM == 6
542
+ else if (CHNL_NUM == 5) begin:CHNL_SEL_5
543
+
544
+ always @(*) begin
545
+ if (is_schedule) begin
546
+ case (last_chnl)
547
+ 0: chnl_idx = hit_priority[0] ? 1 :
548
+ hit_priority[1] ? 2 :
549
+ hit_priority[2] ? 3 :
550
+ hit_priority[3] ? 4 :
551
+ hit_priority[4] ? 0 : 1 ; // last branch is chosen when no channel is valid.
552
+ 1: chnl_idx = hit_priority[0] ? 2 :
553
+ hit_priority[1] ? 3 :
554
+ hit_priority[2] ? 4 :
555
+ hit_priority[3] ? 0 :
556
+ hit_priority[4] ? 1 : 2 ; // last branch is chosen when no channel is valid.
557
+ 2: chnl_idx = hit_priority[0] ? 3 :
558
+ hit_priority[1] ? 4 :
559
+ hit_priority[2] ? 0 :
560
+ hit_priority[3] ? 1 :
561
+ hit_priority[4] ? 2 : 3 ; // last branch is chosen when no channel is valid.
562
+ 3: chnl_idx = hit_priority[0] ? 4 :
563
+ hit_priority[1] ? 0 :
564
+ hit_priority[2] ? 1 :
565
+ hit_priority[3] ? 2 :
566
+ hit_priority[4] ? 3 : 4 ; // last branch is chosen when no channel is valid.
567
+ 4: chnl_idx = hit_priority[0] ? 0 :
568
+ hit_priority[1] ? 1 :
569
+ hit_priority[2] ? 2 :
570
+ hit_priority[3] ? 3 :
571
+ hit_priority[4] ? 4 : 0 ; // last branch is chosen when no channel is valid.
572
+ default: chnl_idx = {CHNL_NUM_LOG{1'd0}};
573
+ endcase
574
+ end
575
+ else begin
576
+ chnl_idx = chnl_idx_reg; // chosen in REQ_TRANS state
577
+ end
578
+ end
579
+
580
+ end // CHNL_NUM == 5
581
+ else if (CHNL_NUM == 4) begin:CHNL_SEL_4
582
+
583
+ always @(*) begin
584
+ if (is_schedule) begin
585
+ case (last_chnl)
586
+ 0: chnl_idx = hit_priority[0] ? 1 :
587
+ hit_priority[1] ? 2 :
588
+ hit_priority[2] ? 3 :
589
+ hit_priority[3] ? 0 : 1 ; // last branch is chosen when no channel is valid.
590
+ 1: chnl_idx = hit_priority[0] ? 2 :
591
+ hit_priority[1] ? 3 :
592
+ hit_priority[2] ? 0 :
593
+ hit_priority[3] ? 1 : 2 ; // last branch is chosen when no channel is valid.
594
+ 2: chnl_idx = hit_priority[0] ? 3 :
595
+ hit_priority[1] ? 0 :
596
+ hit_priority[2] ? 1 :
597
+ hit_priority[3] ? 2 : 3 ; // last branch is chosen when no channel is valid.
598
+ 3: chnl_idx = hit_priority[0] ? 0 :
599
+ hit_priority[1] ? 1 :
600
+ hit_priority[2] ? 2 :
601
+ hit_priority[3] ? 3 : 0 ; // last branch is chosen when no channel is valid.
602
+ default: chnl_idx = {CHNL_NUM_LOG{1'd0}};
603
+ endcase
604
+ end
605
+ else begin
606
+ chnl_idx = chnl_idx_reg; // chosen in REQ_TRANS state
607
+ end
608
+ end
609
+
610
+ end // CHNL_NUM == 4
611
+ else if (CHNL_NUM == 3) begin:CHNL_SEL_3
612
+
613
+ always @(*) begin
614
+ if (is_schedule) begin
615
+ case (last_chnl)
616
+ 0: chnl_idx = hit_priority[0] ? 1 :
617
+ hit_priority[1] ? 2 :
618
+ hit_priority[2] ? 0 : 1; // last branch is chosen when no channel is valid.
619
+ 1: chnl_idx = hit_priority[0] ? 2 :
620
+ hit_priority[1] ? 0 :
621
+ hit_priority[2] ? 1 : 2; // last branch is chosen when no channel is valid.
622
+ 2: chnl_idx = hit_priority[0] ? 0 :
623
+ hit_priority[1] ? 1 :
624
+ hit_priority[2] ? 2 : 0; // last branch is chosen when no channel is valid.
625
+ default: chnl_idx = {CHNL_NUM_LOG{1'd0}};
626
+ endcase
627
+ end
628
+ else begin
629
+ chnl_idx = chnl_idx_reg; // chosen in REQ_TRANS state
630
+ end
631
+ end
632
+
633
+ end // CHNL_NUM == 3
634
+ else if (CHNL_NUM == 2) begin:CHNL_SEL_2
635
+
636
+ always @(*) begin
637
+ if (is_schedule) begin
638
+ case (last_chnl)
639
+ 0: chnl_idx = hit_priority[0] ? 1 :
640
+ hit_priority[1] ? 0 : 1 ; // last branch is chosen when no channel is valid.
641
+ 1: chnl_idx = hit_priority[0] ? 0 :
642
+ hit_priority[1] ? 1 : 0 ; // last branch is chosen when no channel is valid.
643
+ default: chnl_idx = {CHNL_NUM_LOG{1'd0}};
644
+ endcase
645
+ end
646
+ else begin
647
+ chnl_idx = chnl_idx_reg; // chosen in REQ_TRANS state
648
+ end
649
+ end
650
+
651
+ end // CHNL_NUM == 2
652
+ endgenerate
653
+ /*
654
+ This is used for different Channel Numbers, the default Number is 4 */
655
+ /* -------Generate block{end}------- */
656
+
657
+ // /* -------Core logic to arbit, a parameterized arbiter{begin}------- */
658
+ // function [CHNL_NUM_LOG-1:0] find_chnl_num;
659
+ // input [CHNL_NUM_LOG-1:0] prio_level;
660
+ // input [CHNL_NUM_LOG-1:0] last_c;
661
+ // begin
662
+ // find_chnl_num = ((last_c+prio_level+1) >= CHNL_NUM) ? last_c+prio_level+1-CHNL_NUM : last_c+prio_level+1;
663
+ // end
664
+ // endfunction
665
+
666
+ // function [CHNL_NUM-1:0] sel_prio;
667
+ // input [CHNL_NUM-1:0] sel;
668
+ // reg tmp;
669
+ // integer i, j;
670
+ // begin
671
+ // sel_prio[0] = sel[0];
672
+ // for (i = 1; i < CHNL_NUM; i = i + 1) begin
673
+ // tmp = 0;
674
+ // for (j = 0; j < i; j = j + 1) begin
675
+ // tmp = tmp | sel[j];
676
+ // end
677
+ // sel_prio[i] = !tmp & sel[i];
678
+ // end
679
+ // end
680
+ // endfunction
681
+
682
+ // function [CHNL_NUM_LOG-1:0] find_nxt_chnl;
683
+ // input [CHNL_NUM_LOG-1:0] last_c;
684
+ // input [CHNL_NUM-1:0] hit_prio;
685
+ // integer i;
686
+ // begin
687
+ // find_nxt_chnl = {CHNL_NUM_LOG{hit_prio[0]}} & find_chnl_num(0, last_c);
688
+ // for (i = 1; i < CHNL_NUM; i = i + 1) begin
689
+ // find_nxt_chnl = find_nxt_chnl | {CHNL_NUM_LOG{hit_prio[i]}} & find_chnl_num(i, last_c);;
690
+ // end
691
+ // end
692
+ // endfunction
693
+
694
+ // always @(*) begin
695
+ // if (is_schedule) begin
696
+ // chnl_idx = find_nxt_chnl(last_chnl, sel_prio(hit_priority));
697
+ // end
698
+ // else begin
699
+ // chnl_idx = chnl_idx_reg; // chosen in REQ_TRANS state
700
+ // end
701
+ // end
702
+ // /* -------Core logic to arbit, a parameterized arbiter{end}------- */
703
+
704
+ // state transform signal
705
+ assign req_last = m_axis_mux_tvalid & m_axis_mux_tready & m_axis_mux_tlast;
706
+
707
+ /* -------Find next channel{end}------- */
708
+
709
+ /* -------{Read Request Arbiter FSM}begin------- */
710
+ /******************** Stage 1: State Register **********************/
711
+ assign is_idle = (cur_state == IDLE );
712
+ assign is_schedule = (cur_state == SCHEDULE );
713
+ assign is_req_trans = (cur_state == REQ_TRANS);
714
+ assign j_req_trans = is_schedule & (!req_last) & (|s_axis_mux_tvalid);
715
+ // assign j_schedule = is_schedule & (req_last) |
716
+ // is_req_trans & (req_last);
717
+
718
+ always @(posedge clk, negedge rst_n) begin
719
+ if(~rst_n)
720
+ cur_state <= `TD IDLE;
721
+ else
722
+ cur_state <= `TD nxt_state;
723
+ end
724
+
725
+ /******************** Stage 2: State Transition **********************/
726
+
727
+ always @(*) begin
728
+ case(cur_state)
729
+ IDLE: begin
730
+ if (|s_axis_mux_tvalid) begin
731
+ nxt_state = SCHEDULE;
732
+ end
733
+ else begin
734
+ nxt_state = IDLE;
735
+ end
736
+ end
737
+ SCHEDULE: begin
738
+ if (req_last) begin // one beat request has already been transmited in
739
+ // schedule state.
740
+ nxt_state = SCHEDULE;
741
+ end
742
+ else if (|s_axis_mux_tvalid) begin // There's valid channel, and not the last beat.
743
+ nxt_state = REQ_TRANS;
744
+ end
745
+ else begin
746
+ nxt_state = IDLE;
747
+ end
748
+ end
749
+ REQ_TRANS: begin
750
+ if (req_last) begin // request has already been transmited in
751
+ // req_trans state.
752
+ nxt_state = SCHEDULE;
753
+ end
754
+ else begin
755
+ nxt_state = REQ_TRANS;
756
+ end
757
+ end
758
+ default: begin
759
+ nxt_state = IDLE;
760
+ end
761
+ endcase
762
+ end
763
+ /******************** Stage 3: Output **********************/
764
+
765
+ /* -------Generate block{begin}------- */
766
+ genvar n;
767
+ generate
768
+ for (n = 0; n < CHNL_NUM; n = n + 1) begin:CHNL_ASSIGN
769
+
770
+ assign s_axis_mux_tready[n] = (is_schedule | is_req_trans) & (n == chnl_idx) & m_axis_mux_tready;
771
+
772
+ assign s_channel_tvalid[n] = s_axis_mux_tvalid[((n+1) * 1 -1):(n * 1 )];
773
+ assign s_channel_tlast [n] = s_axis_mux_tlast [((n+1) * 1 -1):(n * 1 )];
774
+ assign s_channel_tdata [n] = s_axis_mux_tdata [((n+1) * TDATA_WIDTH-1):(n * TDATA_WIDTH)];
775
+ assign s_channel_tuser [n] = s_axis_mux_tuser [((n+1) * TUSER_WIDTH-1):(n * TUSER_WIDTH)];
776
+
777
+ assign hit_priority[n] = s_channel_tvalid[nxt_priority[n]];
778
+
779
+ end
780
+ endgenerate
781
+ /* -------Generate block{end}------- */
782
+
783
+ assign m_axis_mux_tvalid = (is_schedule | is_req_trans) ? s_channel_tvalid[chnl_idx] : 1'd0;
784
+ assign m_axis_mux_tlast = (is_schedule | is_req_trans) ? s_channel_tlast [chnl_idx] : 1'd0;
785
+ assign m_axis_mux_tdata = (is_schedule | is_req_trans) ? s_channel_tdata [chnl_idx] : {TDATA_WIDTH{1'd0}};
786
+ assign m_axis_mux_tuser = (is_schedule | is_req_trans) ? s_channel_tuser [chnl_idx] : {TUSER_WIDTH{1'd0}};
787
+
788
+ /* -------{Read Request Arbiter FSM}end------- */
789
+
790
+
791
+ endmodule
ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Common/st_reg.v ADDED
@@ -0,0 +1,110 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ `timescale 1ns / 100ps
2
+ //*************************************************************************
3
+ // > File Name: st_reg.v
4
+ // > Author : Kangning
5
+ // > Date : 2022-07-18
6
+ // > Note : A general module used to temporarily store the input
7
+ // > axis-like signal for one cycle.
8
+ //*************************************************************************
9
+
10
+
11
+ module st_reg #(
12
+ parameter TUSER_WIDTH = 128,
13
+ parameter TDATA_WIDTH = 256,
14
+ parameter MODE = 0, // The default mode is 0
15
+ parameter NUM_LEVELS = 1
16
+ ) (
17
+ input wire clk , // i, 1
18
+ input wire rst_n , // i, 1
19
+
20
+ /* -------input axis-like interface{begin}------- */
21
+ input wire axis_tvalid , // i, 1
22
+ input wire axis_tlast , // i, 1
23
+ input wire [TUSER_WIDTH-1:0] axis_tuser , // i, TUSER_WIDTH
24
+ input wire [TDATA_WIDTH-1:0] axis_tdata , // i, TDATA_WIDTH
25
+ output wire axis_tready , // o, 1
26
+ /* -------input axis-like interface{end}------- */
27
+
28
+ /* -------output in_reg inteface{begin}------- */
29
+ output wire axis_reg_tvalid, // read valid from input register
30
+ output wire axis_reg_tlast ,
31
+ output wire [TUSER_WIDTH-1:0] axis_reg_tuser ,
32
+ output wire [TDATA_WIDTH-1:0] axis_reg_tdata ,
33
+ input wire axis_reg_tready
34
+
35
+ // input wire is_tuser_clear, // Optional, clear the present tuser.
36
+ // // Usually, it is asserted when
37
+ // // *_valid & *_ready & *_last
38
+ // output reg axis_reg_sop // Indicate the start of a pkt
39
+ /* -------output in_reg inteface{end}------- */
40
+ );
41
+
42
+ wire axis_out_tlast;
43
+ wire [TUSER_WIDTH-1:0] axis_out_tuser;
44
+ wire [TDATA_WIDTH-1:0] axis_out_tdata;
45
+
46
+ gp_slice_ml #(
47
+ .NUM_LEVELS (NUM_LEVELS ),
48
+ .PAYLD_WIDTH (1 + TUSER_WIDTH + TDATA_WIDTH ),
49
+ .MODE (MODE ),
50
+ .SYNC_RESET (0 )
51
+ ) u_gp_slice_ml_PE (
52
+ .clk ( clk ),
53
+ .rst_n ( rst_n ),
54
+
55
+ .vld_m ( axis_tvalid ),
56
+ .rdy_m ( axis_tready ),
57
+ .payld_m ( {axis_tlast, axis_tuser, axis_tdata} ),
58
+ .vld_s ( axis_reg_tvalid ),
59
+ .rdy_s ( axis_reg_tready ),
60
+ .payld_s ( {axis_out_tlast, axis_out_tuser, axis_out_tdata} )
61
+ );
62
+ assign {axis_reg_tlast, axis_reg_tuser, axis_reg_tdata} = axis_reg_tvalid ? {axis_out_tlast, axis_out_tuser, axis_out_tdata} : {1 + TUSER_WIDTH + TDATA_WIDTH{1'd0}};
63
+
64
+ // /* -------in_reg logic{begin}------- */
65
+ // always @(posedge clk, negedge rst_n) begin
66
+ // if (~rst_n) begin
67
+ // axis_reg_sop <= `TD 1;
68
+ // end
69
+ // else if (axis_tvalid & axis_tready & axis_tlast) begin
70
+ // axis_reg_sop <= `TD 1;
71
+ // end
72
+ // else if (axis_tvalid & axis_tready & axis_reg_sop) begin
73
+ // axis_reg_sop <= `TD 0;
74
+ // end
75
+ // end
76
+
77
+ // always @(posedge clk, negedge rst_n) begin
78
+ // if (~rst_n) begin
79
+ // axis_reg_tuser <= `TD 0;
80
+ // end
81
+ // else if (axis_tvalid & axis_tready & axis_reg_sop) begin
82
+ // axis_reg_tuser <= `TD axis_tuser;
83
+ // end
84
+ // else if (is_tuser_clear) begin // after trans finished, axis_reg_tuser is set to 0
85
+ // axis_reg_tuser <= `TD 0;
86
+ // end
87
+ // end
88
+
89
+ // always @(posedge clk, negedge rst_n) begin
90
+ // if (~rst_n) begin
91
+ // axis_reg_tvalid <= `TD 0;
92
+ // axis_reg_tlast <= `TD 0;
93
+ // axis_reg_tdata <= `TD 0;
94
+ // end
95
+ // else if (axis_tvalid & axis_tready) begin // write en & not full
96
+ // axis_reg_tvalid <= `TD 1;
97
+ // axis_reg_tlast <= `TD axis_tlast;
98
+ // axis_reg_tdata <= `TD axis_tdata;
99
+ // end
100
+ // else if (axis_reg_tready & axis_reg_tvalid) begin // read en & not empty
101
+ // axis_reg_tvalid <= `TD 0;
102
+ // axis_reg_tlast <= `TD 0;
103
+ // axis_reg_tdata <= `TD 0;
104
+ // end
105
+ // end
106
+
107
+ // assign axis_tready = !axis_reg_tvalid | axis_reg_tready; // empty | going to empty
108
+ // /* -------in_reg logic{end}------- */
109
+
110
+ endmodule
ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Common/stream_fifo.v ADDED
@@ -0,0 +1,101 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ `timescale 1ns / 100ps
2
+
3
+ module stream_fifo #(
4
+ TUSER_WIDTH = 128,
5
+ TDATA_WIDTH = 256,
6
+ TKEEP_WIDTH = TDATA_WIDTH / 8
7
+ ) (
8
+ input wire clk , // i, 1
9
+ input wire rst , // i, 1
10
+
11
+ /* -------input axis-like interface{begin}------- */
12
+ input wire axis_tvalid , // i, 1
13
+ input wire axis_tlast , // i, 1
14
+ input wire [TUSER_WIDTH-1:0] axis_tuser , // i, TUSER_WIDTH
15
+ input wire [TDATA_WIDTH-1:0] axis_tdata , // i, TDATA_WIDTH
16
+ output wire axis_tready , // o, 1
17
+ input wire axis_tstart,
18
+ input wire [TKEEP_WIDTH-1:0] axis_tkeep,
19
+
20
+ /* -------input axis-like interface{end}------- */
21
+
22
+ /* -------output in_reg inteface{begin}------- */
23
+ output wire in_reg_tvalid, // read valid from input register
24
+ output wire in_reg_tlast ,
25
+ output wire [TUSER_WIDTH-1:0] in_reg_tuser ,
26
+ output wire [TDATA_WIDTH-1:0] in_reg_tdata ,
27
+ output wire [TKEEP_WIDTH-1:0] in_reg_tkeep ,
28
+ output wire in_reg_tstart,
29
+ input wire in_reg_tready
30
+ /* -------output in_reg inteface{end}------- */
31
+ );
32
+
33
+ wire payload_wr_en;
34
+ wire [(TDATA_WIDTH + 1 + 1) - 1 : 0] payload_din;
35
+ wire payload_prog_full;
36
+ wire payload_rd_en;
37
+ wire [(TDATA_WIDTH + 1 + 1) - 1 : 0] payload_dout;
38
+ wire payload_empty;
39
+
40
+ wire header_wr_en;
41
+ wire [TUSER_WIDTH - 1 : 0] header_din;
42
+ wire header_prog_full;
43
+ wire header_rd_en;
44
+ wire [TUSER_WIDTH - 1 : 0] header_dout;
45
+ wire header_empty;
46
+
47
+ assign payload_wr_en = axis_tvalid && axis_tready;
48
+ assign payload_din = {axis_tlast, axis_tstart, axis_tdata};
49
+
50
+ assign header_wr_en = axis_tvalid && axis_tready;
51
+ assign header_din = axis_tuser;
52
+
53
+ assign axis_tready = !header_prog_full && !payload_prog_full;
54
+
55
+ assign header_rd_en = in_reg_tready && !header_empty;
56
+ assign payload_rd_en = in_reg_tready && !payload_empty;
57
+
58
+ SyncFIFO_Template #(
59
+ .FIFO_WIDTH ( TUSER_WIDTH ),
60
+ .FIFO_DEPTH ( 16 )
61
+ )
62
+ HeaderFIFO
63
+ (
64
+ .clk ( clk ),
65
+ .rst ( rst ),
66
+
67
+ .wr_en ( header_wr_en ),
68
+ .din ( header_din ),
69
+ .prog_full ( header_prog_full ),
70
+ .rd_en ( header_rd_en ),
71
+ .dout ( header_dout ),
72
+ .empty ( header_empty ),
73
+ .data_count ( )
74
+ );
75
+
76
+ SyncFIFO_Template #(
77
+ .FIFO_WIDTH ( TDATA_WIDTH + 1 + 1 ),
78
+ .FIFO_DEPTH ( 16 )
79
+ )
80
+ PayloadFIFO
81
+ (
82
+ .clk ( clk ),
83
+ .rst ( rst ),
84
+
85
+ .wr_en ( payload_wr_en ),
86
+ .din ( payload_din ),
87
+ .prog_full ( payload_prog_full ),
88
+ .rd_en ( payload_rd_en ),
89
+ .dout ( payload_dout ),
90
+ .empty ( payload_empty ),
91
+ .data_count ( )
92
+ );
93
+
94
+ assign in_reg_tvalid = !header_empty && !payload_empty;
95
+ assign in_reg_tstart = in_reg_tvalid ? payload_dout[TDATA_WIDTH] : 'd0;
96
+ assign in_reg_tlast = in_reg_tvalid ? payload_dout[TDATA_WIDTH + 1] : 'd0;
97
+ assign in_reg_tkeep = 'd0;
98
+ assign in_reg_tuser = in_reg_tvalid ? header_dout : 'd0;
99
+ assign in_reg_tdata = in_reg_tvalid ? payload_dout : 'd0;
100
+
101
+ endmodule
ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Common/stream_reg.v ADDED
@@ -0,0 +1,62 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ `timescale 1ns / 100ps
2
+
3
+ module stream_reg #(
4
+ TUSER_WIDTH = 128,
5
+ TDATA_WIDTH = 256,
6
+ TKEEP_WIDTH = TDATA_WIDTH / 8,
7
+ MODE = 0,
8
+ NUM_LEVELS = 1
9
+ ) (
10
+ input wire clk , // i, 1
11
+ input wire rst_n , // i, 1
12
+
13
+ /* -------input axis-like interface{begin}------- */
14
+ input wire axis_tvalid , // i, 1
15
+ input wire axis_tlast , // i, 1
16
+ input wire [TUSER_WIDTH-1:0] axis_tuser , // i, TUSER_WIDTH
17
+ input wire [TDATA_WIDTH-1:0] axis_tdata , // i, TDATA_WIDTH
18
+ output wire axis_tready , // o, 1
19
+ input wire axis_tstart,
20
+ input wire [TKEEP_WIDTH-1:0] axis_tkeep,
21
+
22
+ /* -------input axis-like interface{end}------- */
23
+
24
+ /* -------output in_reg inteface{begin}------- */
25
+ output wire in_reg_tvalid, // read valid from input register
26
+ output wire in_reg_tlast ,
27
+ output wire [TUSER_WIDTH-1:0] in_reg_tuser ,
28
+ output wire [TDATA_WIDTH-1:0] in_reg_tdata ,
29
+ output wire [TKEEP_WIDTH-1:0] in_reg_tkeep ,
30
+ output wire in_reg_tstart,
31
+ input wire in_reg_tready,
32
+
33
+ input wire tuser_clear
34
+ /* -------output in_reg inteface{end}------- */
35
+ );
36
+
37
+ wire [(TUSER_WIDTH + TDATA_WIDTH + TKEEP_WIDTH + 1 + 1) - 1 : 0] payload_slave;
38
+
39
+ gp_slice_ml #(
40
+ .NUM_LEVELS (NUM_LEVELS ),
41
+ .PAYLD_WIDTH (TUSER_WIDTH + TDATA_WIDTH + TKEEP_WIDTH + 1 + 1),
42
+ .MODE (MODE ),
43
+ .SYNC_RESET (0 )
44
+ ) u_gp_slice_ml_PE (
45
+ .clk(clk),
46
+ .rst_n(rst_n),
47
+
48
+ .vld_m(axis_tvalid),
49
+ .rdy_m(axis_tready),
50
+ .payld_m({axis_tstart, axis_tlast, axis_tkeep, axis_tuser, axis_tdata}),
51
+ .vld_s(in_reg_tvalid),
52
+ .rdy_s(in_reg_tready),
53
+ .payld_s(payload_slave)
54
+ );
55
+
56
+ assign in_reg_tstart = in_reg_tvalid ? payload_slave[(TUSER_WIDTH + TDATA_WIDTH + TKEEP_WIDTH + 1 + 1) - 1] : 'd0;
57
+ assign in_reg_tlast = in_reg_tvalid ? payload_slave[(TUSER_WIDTH + TDATA_WIDTH + TKEEP_WIDTH + 1 + 1) - 2] : 'd0;
58
+ assign in_reg_tkeep = in_reg_tvalid ? payload_slave[(TUSER_WIDTH + TDATA_WIDTH + TKEEP_WIDTH) - 1 : (TUSER_WIDTH + TDATA_WIDTH)] : 'd0;
59
+ assign in_reg_tuser = in_reg_tvalid ? payload_slave[(TUSER_WIDTH + TDATA_WIDTH) - 1 : (TDATA_WIDTH)] : 'd0;
60
+ assign in_reg_tdata = in_reg_tvalid ? payload_slave[(TDATA_WIDTH) - 1 : 0] : 'd0;
61
+
62
+ endmodule
ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Common/sync_reset.v ADDED
@@ -0,0 +1,35 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ `resetall
2
+ `timescale 1ns / 1ps
3
+ `default_nettype none
4
+
5
+ /*
6
+ * Synchronizes an active-high asynchronous reset signal to a given clock by
7
+ * using a pipeline of N registers.
8
+ */
9
+ module sync_reset #
10
+ (
11
+ // depth of synchronizer
12
+ parameter N = 2
13
+ )
14
+ (
15
+ input wire clk,
16
+ input wire rst,
17
+ output wire out
18
+ );
19
+
20
+ (* srl_style = "register" *)
21
+ reg [N-1:0] sync_reg = {N{1'b1}};
22
+
23
+ assign out = sync_reg[N-1];
24
+
25
+ always @(posedge clk or posedge rst) begin
26
+ if (rst) begin
27
+ sync_reg <= {N{1'b1}};
28
+ end else begin
29
+ sync_reg <= {sync_reg[N-2:0], 1'b0};
30
+ end
31
+ end
32
+
33
+ endmodule
34
+
35
+ `resetall
ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/EthSubsystem/README.md ADDED
@@ -0,0 +1 @@
 
 
1
+ EthSubsystem
ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/DMA/DMA.v ADDED
@@ -0,0 +1,826 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ `timescale 1ns / 100ps
2
+ //*************************************************************************
3
+ // > File Name: DMA.v
4
+ // > Author : Kangning
5
+ // > Date : 2020-08-17
6
+ // > Note : DMA module, used to generate DMA Interface
7
+ // > V1.1 - 2021-01-29: Modify formation of code, make it more generalize.
8
+ //*************************************************************************
9
+
10
+ //`include "../lib/global_include_h.v"
11
+ //`include "../lib/dma_def_h.v"
12
+
13
+ module DMA #(
14
+
15
+ ) (
16
+ input wire pcie_clk ,
17
+ input wire pcie_rst_n,
18
+ input wire dma_clk ,
19
+ input wire rst_n ,
20
+ output wire init_done , // o, 1
21
+
22
+ /* -------dma interface{begin}------- */
23
+ /* *_head of DMA interface (interact with RDMA modules),
24
+ * valid only in first beat of a packet.
25
+ * When Transmiting msi-x interrupt message, 'Byte length'
26
+ * should be 0, 'address' means the address of msi-x, and
27
+ * msi-x data locates in *_data[31:0].
28
+ * | Resvd | Req Type | address | Reserved | Byte length |
29
+ * | |(rd,wr,int)| (msi-x addr) | | (0 for int) |
30
+ * |-------|-----------|--------------|----------|-------------|
31
+ * |127:100| 99:96 | 95:32 | 31:13 | 12:0 |
32
+ */
33
+ // Read Req
34
+ input wire [`DMA_RD_CHNL_NUM * 1 -1:0] dma_rd_req_valid,
35
+ input wire [`DMA_RD_CHNL_NUM * 1 -1:0] dma_rd_req_last ,
36
+ input wire [`DMA_RD_CHNL_NUM * `DMA_DATA_W-1:0] dma_rd_req_data ,
37
+ input wire [`DMA_RD_CHNL_NUM * `DMA_HEAD_W-1:0] dma_rd_req_head ,
38
+ output wire [`DMA_RD_CHNL_NUM * 1 -1:0] dma_rd_req_ready,
39
+
40
+ // DMA Read Resp
41
+ output wire [`DMA_RD_CHNL_NUM * 1 -1:0] dma_rd_rsp_valid,
42
+ output wire [`DMA_RD_CHNL_NUM * 1 -1:0] dma_rd_rsp_last ,
43
+ output wire [`DMA_RD_CHNL_NUM * `DMA_DATA_W-1:0] dma_rd_rsp_data ,
44
+ output wire [`DMA_RD_CHNL_NUM * `DMA_HEAD_W-1:0] dma_rd_rsp_head ,
45
+ input wire [`DMA_RD_CHNL_NUM * 1 -1:0] dma_rd_rsp_ready,
46
+
47
+ // DMA Write Req
48
+ input wire [`DMA_WR_CHNL_NUM * 1 -1:0] dma_wr_req_valid,
49
+ input wire [`DMA_WR_CHNL_NUM * 1 -1:0] dma_wr_req_last ,
50
+ input wire [`DMA_WR_CHNL_NUM * `DMA_DATA_W-1:0] dma_wr_req_data ,
51
+ input wire [`DMA_WR_CHNL_NUM * `DMA_HEAD_W-1:0] dma_wr_req_head ,
52
+ output wire [`DMA_WR_CHNL_NUM * 1 -1:0] dma_wr_req_ready,
53
+ /* -------dma interface{end}------- */
54
+
55
+
56
+ /* -------Requester Request{begin}------- */
57
+ /* RQ tuser
58
+ * | 59:28 | 27:24 | 23:16 | 15 | 14:13 | 12 | 11 | 10:8 | 7:4 | 3:0 |
59
+ * | parity | seq_num | tph_st_tag | tph_indirect_tag_en | tph_type | tph_present | discontinue | addr_offset | last_be | first_be |
60
+ * | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | |
61
+ */
62
+ output wire s_axis_rq_tvalid,
63
+ output wire s_axis_rq_tlast ,
64
+ output wire [`DMA_DATA_W-1:0] s_axis_rq_tdata ,
65
+ output wire [59 :0] s_axis_rq_tuser ,
66
+ output wire [`DMA_KEEP_W-1:0] s_axis_rq_tkeep ,
67
+ input wire s_axis_rq_tready,
68
+ /* -------Requester Request{end}------- */
69
+
70
+ /* -------Requester Completion{begin}------- */
71
+ /* RC tuser
72
+ * | 74:43 | 42 | 41:38 | 37:34 | 33 | 32 | 31:0 |
73
+ * | parity | discontinue | is_eof_1 | is_eof_0 | is_sof_1 | is_sof_0 | byte_en |
74
+ * | ignore | ignore | ignore | ignore | ignore | ignore | |
75
+ */
76
+ input wire m_axis_rc_tvalid,
77
+ input wire m_axis_rc_tlast ,
78
+ input wire [`DMA_DATA_W-1:0] m_axis_rc_tdata ,
79
+ input wire [74 :0] m_axis_rc_tuser ,
80
+ input wire [`DMA_KEEP_W-1:0] m_axis_rc_tkeep ,
81
+ output wire m_axis_rc_tready,
82
+ /* -------Requester Completion{end}------- */
83
+
84
+ /* -------Interrupt Interface Signals{begin}------- */
85
+ input [1:0] cfg_interrupt_msix_enable ,
86
+ input [1:0] cfg_interrupt_msix_mask ,
87
+ output [31:0] cfg_interrupt_msix_data ,
88
+ output [63:0] cfg_interrupt_msix_address ,
89
+ output cfg_interrupt_msix_int ,
90
+ input cfg_interrupt_msix_sent ,
91
+ input cfg_interrupt_msix_fail ,
92
+ output wire [2:0] cfg_interrupt_msi_function_number,
93
+ /* -------Interrupt Interface Signals{end}------- */
94
+
95
+ /* -------Configuration Status Interface{begin}------- */
96
+ input wire [ 2:0] max_pyld_sz ,
97
+ input wire [ 2:0] max_rd_req_sz,
98
+ input wire [15:0] req_id
99
+ /* -------Configuration Status Interface{end}------- */
100
+
101
+ `ifdef PCIEI_APB_DBG
102
+ /* -------APB reated signal{begin}------- */
103
+ ,input wire [(2*`DMA_RD_CHNL_NUM+`DMA_WR_CHNL_NUM+6)*`SRAM_RW_DATA_W-1:0] rw_data // i, (2*`DMA_RD_CHNL_NUM+`DMA_WR_CHNL_NUM+6)*`SRAM_RW_DATA_W
104
+ ,input wire [31:0] dbg_sel // debug bus select
105
+ ,output wire [31:0] dbg_bus // debug bus data
106
+ /* -------APB reated signal{end}------- */
107
+ `endif
108
+
109
+ `ifdef SIMULATION
110
+ /* ------- Debug interface {begin}------- */
111
+ /* | reserved |
112
+ * | 255:47 |
113
+ * | tag_num | tag_chnl | valid |
114
+ * | 46:39 | 38:31 | 30 |
115
+ * | top_idx | top_end | top_out|
116
+ * | 29:22 | 21 | 20 |
117
+ * | rd_idx | rd_end | rd_out |
118
+ * | 19:12 | 11 | 10 |
119
+ * | wr_idx | wr_end | wr_out |
120
+ * | 9:2 | 1 | 0 |
121
+ */
122
+ ,output wire [255:0] debug
123
+ /* ------- Debug interface {end}------- */
124
+ `endif
125
+ );
126
+
127
+ `ifdef SIMULATION
128
+
129
+ wire [255:0] debug_wr, debug_rd, debug_top, debug_tag;
130
+ assign debug = {209'd0, debug_tag[16:0], debug_top[9:0], debug_rd[9:0], debug_wr[9:0]};
131
+
132
+ `endif
133
+
134
+ /* -------Used in wr arbiter{begin}------- */
135
+ wire [`DMA_WR_CHNL_NUM * 1 -1:0] axis_wr_req_tvalid;
136
+ wire [`DMA_WR_CHNL_NUM * 1 -1:0] axis_wr_req_tlast ;
137
+ wire [`DMA_WR_CHNL_NUM * `DMA_DATA_W -1:0] axis_wr_req_tdata ;
138
+ wire [`DMA_WR_CHNL_NUM * `AXIS_TUSER_W-1:0] axis_wr_req_tuser ;
139
+ wire [`DMA_WR_CHNL_NUM * `DMA_KEEP_W -1:0] axis_wr_req_tkeep ;
140
+ wire [`DMA_WR_CHNL_NUM * 1 -1:0] axis_wr_req_tready;
141
+ /* -------Used in wr arbiter{end}------- */
142
+
143
+ /* -------Used in rd & wr arbiter{begin}------- */
144
+ wire axis_wreq_tvalid;
145
+ wire axis_wreq_tlast ;
146
+ wire [`DMA_DATA_W -1:0] axis_wreq_tdata ;
147
+ wire [`AXIS_TUSER_W-1:0] axis_wreq_tuser ;
148
+ wire [`DMA_KEEP_W -1:0] axis_wreq_tkeep ;
149
+ wire axis_wreq_tready;
150
+
151
+ wire axis_rreq_tvalid;
152
+ wire axis_rreq_tlast ;
153
+ wire [`DMA_DATA_W -1:0] axis_rreq_tdata ;
154
+ wire [`AXIS_TUSER_W-1:0] axis_rreq_tuser ;
155
+ wire [`DMA_KEEP_W -1:0] axis_rreq_tkeep ;
156
+ wire axis_rreq_tready;
157
+ /* -------Used in rd & wr arbiter{end}------- */
158
+
159
+ wire axis_req_tvalid;
160
+ wire axis_req_tlast ;
161
+ wire [`DMA_DATA_W -1:0] axis_req_tdata ;
162
+ wire [`AXIS_TUSER_W-1:0] axis_req_tuser ;
163
+ wire [`DMA_KEEP_W -1:0] axis_req_tkeep ;
164
+ wire axis_req_tready;
165
+
166
+
167
+
168
+ /* -------Used in read response{begin}------- */
169
+ // In pcie clock domain
170
+ wire pcie_axis_rrsp_tvalid;
171
+ wire pcie_axis_rrsp_tlast ;
172
+ wire [`DMA_DATA_W -1:0] pcie_axis_rrsp_tdata ;
173
+ wire [`AXIS_TUSER_W-1:0] pcie_axis_rrsp_tuser ;
174
+ wire [`DMA_KEEP_W -1:0] pcie_axis_rrsp_tkeep ;
175
+ wire pcie_axis_rrsp_tready;
176
+
177
+ // in dma clock domain
178
+ wire dma_axis_rrsp_tvalid;
179
+ wire dma_axis_rrsp_tlast ;
180
+ wire [`DMA_DATA_W -1:0] dma_axis_rrsp_tdata ;
181
+ wire [`AXIS_TUSER_W-1:0] dma_axis_rrsp_tuser ;
182
+ wire [`DMA_KEEP_W -1:0] dma_axis_rrsp_tkeep ;
183
+ wire dma_axis_rrsp_tready;
184
+ /* -------Used in read response{end}------- */
185
+
186
+
187
+
188
+ /* --------Used in RQ & RC {begin}-------- */
189
+ wire dma_axis_rq_tvalid;
190
+ wire dma_axis_rq_tlast ;
191
+ wire [`DMA_DATA_W-1:0] dma_axis_rq_tdata ;
192
+ wire [59 :0] dma_axis_rq_tuser ;
193
+ wire [`DMA_KEEP_W-1:0] dma_axis_rq_tkeep ;
194
+ wire dma_axis_rq_tready;
195
+
196
+ // wire dma_axis_rc_tvalid;
197
+ // wire dma_axis_rc_tlast ;
198
+ // wire [`DMA_DATA_W-1:0] dma_axis_rc_tdata ;
199
+ // wire [74 :0] dma_axis_rc_tuser ;
200
+ // wire [`DMA_KEEP_W-1:0] dma_axis_rc_tkeep ;
201
+ // wire dma_axis_rc_tready;
202
+ /* --------Used in RQ & RC {end}-------- */
203
+
204
+ `ifdef PCIEI_APB_DBG
205
+ /* -------APB reated signal{begin}------- */
206
+ wire [(2*`DMA_RD_CHNL_NUM+3)*`SRAM_RW_DATA_W-1:0] rw_data_rd_req_rsp;
207
+ wire [`DMA_WR_CHNL_NUM*`SRAM_RW_DATA_W-1:0] rw_data_wr_req;
208
+ wire [`SRAM_RW_DATA_W-1:0] rw_data_int;
209
+ wire [`SRAM_RW_DATA_W-1:0] rw_data_rq;
210
+ wire [`SRAM_RW_DATA_W-1:0] rw_data_rc;
211
+
212
+ wire [32-1:0] dbg_sel_dma_top, dbg_sel_rd_req_rsp, dbg_sel_wr_req, dbg_sel_wreq_arb, dbg_sel_req_arb,
213
+ dbg_sel_req_convert, dbg_sel_rsp_convert;
214
+ wire [32-1:0] dbg_bus_dma_top, dbg_bus_rd_req_rsp, dbg_bus_wr_req, dbg_bus_wreq_arb, dbg_bus_req_arb,
215
+ dbg_bus_req_convert, dbg_bus_rsp_convert;
216
+
217
+ wire [`DMA_TOP_SIGNAL_W-1:0] dbg_signal_dma_top;
218
+ wire [`DMA_WR_CHNL_NUM*`WR_REQ_SIGNAL_W-1:0] dbg_signal_wr_req;
219
+ wire [`WREQ_ARB_SIGNAL_W-1:0] dbg_signal_wreq_arb;
220
+ wire [`REQ_ARB_SIGNAL_W -1:0] dbg_signal_req_arb;
221
+ wire [`RQ_ASYNC_SIGNAL_W-1:0] dbg_signal_rq_async;
222
+ wire [`RC_ASYNC_SIGNAL_W-1:0] dbg_signal_rc_async;
223
+ wire [`RRSP_ASYNC_SIGNAL_W-1:0] dbg_signal_rrsp_async;
224
+ /* -------APB reated signal{end}------- */
225
+ `endif
226
+
227
+ //-----------------------------------------------------------------------------------------------------------------------------
228
+
229
+ `ifdef PCIEI_APB_DBG
230
+ /* -------APB reated signal{begin}------- */
231
+ assign {rw_data_rd_req_rsp, rw_data_wr_req, rw_data_int, rw_data_rq, rw_data_rc} = rw_data;
232
+
233
+ assign dbg_bus = (`DMA_TOP_DBG_B <= dbg_sel && dbg_sel < `RD_REQ_RSP_DBG_B ) ? dbg_bus_dma_top :
234
+ (`RD_REQ_RSP_DBG_B <= dbg_sel && dbg_sel < `WR_REQ_DBG_B ) ? dbg_bus_rd_req_rsp :
235
+ (`WR_REQ_DBG_B <= dbg_sel && dbg_sel < `WREQ_ARB_DBG_B ) ? dbg_bus_wr_req :
236
+ (`WREQ_ARB_DBG_B <= dbg_sel && dbg_sel < `REQ_ARB_DBG_B ) ? dbg_bus_wreq_arb :
237
+ (`REQ_ARB_DBG_B <= dbg_sel && dbg_sel < `REQ_CONVERT_DBG_B) ? dbg_bus_req_arb :
238
+ (`REQ_CONVERT_DBG_B <= dbg_sel && dbg_sel < `RSP_CONVERT_DBG_B) ? dbg_bus_req_convert :
239
+ (`RSP_CONVERT_DBG_B <= dbg_sel && dbg_sel < `DMA_DBG_SIZE ) ? dbg_bus_rsp_convert : 32'd0;
240
+
241
+ assign dbg_sel_dma_top = (`DMA_TOP_DBG_B <= dbg_sel && dbg_sel < `RD_REQ_RSP_DBG_B ) ? (dbg_sel - `DMA_TOP_DBG_B ) : 32'd0;
242
+ assign dbg_sel_rd_req_rsp = (`RD_REQ_RSP_DBG_B <= dbg_sel && dbg_sel < `WR_REQ_DBG_B ) ? (dbg_sel - `RD_REQ_RSP_DBG_B ) : 32'd0;
243
+ assign dbg_sel_wr_req = (`WR_REQ_DBG_B <= dbg_sel && dbg_sel < `WREQ_ARB_DBG_B ) ? (dbg_sel - `WR_REQ_DBG_B ) : 32'd0;
244
+ assign dbg_sel_wreq_arb = (`WREQ_ARB_DBG_B <= dbg_sel && dbg_sel < `REQ_ARB_DBG_B ) ? (dbg_sel - `WREQ_ARB_DBG_B ) : 32'd0;
245
+ assign dbg_sel_req_arb = (`REQ_ARB_DBG_B <= dbg_sel && dbg_sel < `REQ_CONVERT_DBG_B) ? (dbg_sel - `REQ_ARB_DBG_B ) : 32'd0;
246
+ assign dbg_sel_req_convert = (`REQ_CONVERT_DBG_B <= dbg_sel && dbg_sel < `RSP_CONVERT_DBG_B) ? (dbg_sel - `REQ_CONVERT_DBG_B) : 32'd0;
247
+ assign dbg_sel_rsp_convert = (`RSP_CONVERT_DBG_B <= dbg_sel && dbg_sel < `DMA_DBG_SIZE ) ? (dbg_sel - `RSP_CONVERT_DBG_B) : 32'd0;
248
+
249
+
250
+ // Debug signal for DMA_top
251
+ assign dbg_bus_dma_top = dbg_signal_dma_top >> {dbg_sel_dma_top, 5'd0};
252
+
253
+ // Debug signal for wr req
254
+ assign dbg_bus_wr_req = dbg_signal_wr_req >> {dbg_sel_wr_req, 5'd0};
255
+
256
+ // Debug signal for wreq arbiter
257
+ assign dbg_bus_wreq_arb = dbg_signal_wreq_arb >> {dbg_sel_wreq_arb, 5'd0};
258
+
259
+ // Debug signal for wreq arbiter
260
+ assign dbg_bus_req_arb = dbg_signal_req_arb >> {dbg_sel_req_arb, 5'd0};
261
+
262
+ assign dbg_signal_dma_top = { // 17275
263
+ init_done, // 1
264
+ dma_rd_req_valid, dma_rd_req_last, dma_rd_req_data, dma_rd_req_head, dma_rd_req_ready, // 3483 = 9*387
265
+ dma_rd_rsp_valid, dma_rd_rsp_last, dma_rd_rsp_data, dma_rd_rsp_head, dma_rd_rsp_ready, // 3483 = 9*387
266
+ dma_wr_req_valid, dma_wr_req_last, dma_wr_req_data, dma_wr_req_head, dma_wr_req_ready, // 3096 = 8*387
267
+ s_axis_rq_tvalid, s_axis_rq_tlast, s_axis_rq_tdata, s_axis_rq_tuser, s_axis_rq_tkeep , s_axis_rq_tready, // 327
268
+ m_axis_rc_tvalid, m_axis_rc_tlast, m_axis_rc_tdata, m_axis_rc_tuser, m_axis_rc_tkeep , m_axis_rc_tready, // 342
269
+
270
+ cfg_interrupt_msix_enable ,
271
+ cfg_interrupt_msix_mask ,
272
+ cfg_interrupt_msix_data ,
273
+ cfg_interrupt_msix_address ,
274
+ cfg_interrupt_msix_int ,
275
+ cfg_interrupt_msix_sent ,
276
+ cfg_interrupt_msix_fail ,
277
+ cfg_interrupt_msi_function_number, // 106
278
+
279
+ max_pyld_sz,max_rd_req_sz, // 6
280
+ axis_wr_req_tvalid, axis_wr_req_tlast, axis_wr_req_tdata, axis_wr_req_tuser, axis_wr_req_tkeep, axis_wr_req_tready, // 3160=395*8
281
+ axis_wreq_tvalid, axis_wreq_tlast, axis_wreq_tdata, axis_wreq_tuser, axis_wreq_tkeep, axis_wreq_tready, // 395
282
+ axis_rreq_tvalid, axis_rreq_tlast, axis_rreq_tdata, axis_rreq_tuser, axis_rreq_tkeep, axis_rreq_tready, // 395
283
+ axis_req_tvalid, axis_req_tlast, axis_req_tdata, axis_req_tuser, axis_req_tkeep, axis_req_tready, // 395
284
+ pcie_axis_rrsp_tvalid, pcie_axis_rrsp_tlast, pcie_axis_rrsp_tdata, pcie_axis_rrsp_tuser, pcie_axis_rrsp_tkeep, pcie_axis_rrsp_tready, // 395
285
+ dma_axis_rrsp_tvalid, dma_axis_rrsp_tlast, dma_axis_rrsp_tdata, dma_axis_rrsp_tuser, dma_axis_rrsp_tkeep, dma_axis_rrsp_tready, // 395
286
+ dma_axis_rq_tvalid, dma_axis_rq_tlast, dma_axis_rq_tdata, dma_axis_rq_tuser, dma_axis_rq_tkeep, dma_axis_rq_tready, // 327
287
+ // dma_axis_rc_tvalid, dma_axis_rc_tlast, dma_axis_rc_tdata, dma_axis_rc_tuser, dma_axis_rc_tkeep, dma_axis_rc_tready, // 342
288
+
289
+ dbg_signal_rq_async, // 885
290
+ // dbg_signal_rc_async // 34
291
+ dbg_signal_rrsp_async // 84
292
+ };
293
+ /* -------APB reated signal{end}------- */
294
+ `endif
295
+
296
+ read_req_rsp #(
297
+
298
+ ) rd_req_rsp (
299
+ .dma_clk ( dma_clk ), // i, 1
300
+ .rst_n ( rst_n ), // i, 1
301
+ .init_done ( init_done ), // o, 1
302
+
303
+ /* ------- Read Request from RDMA{begin}------- */
304
+ /* dma_*_head (interact with RDMA modules), valid only in first beat of a packet
305
+ * | Reserved | address | Reserved | Byte length |
306
+ * | 127:96 | 95:32 | 31:13 | 12:0 |
307
+ */
308
+ .dma_rd_req_valid ( dma_rd_req_valid ), // i, `DMA_RD_CHNL_NUM * 1
309
+ .dma_rd_req_last ( dma_rd_req_last ), // i, `DMA_RD_CHNL_NUM * 1
310
+ .dma_rd_req_data ( dma_rd_req_data ), // i, `DMA_RD_CHNL_NUM * `DMA_DATA_W
311
+ .dma_rd_req_head ( dma_rd_req_head ), // i, `DMA_RD_CHNL_NUM * `DMA_HEAD_W
312
+ .dma_rd_req_ready ( dma_rd_req_ready ), // o, `DMA_RD_CHNL_NUM * 1
313
+ /* ------- Read Request from RDMA{end}------- */
314
+
315
+ /* ------- Read Response to RDMA{begin} ------- */
316
+ /* dma_*_head (interact with RDMA modules), valid only in first beat of a packet
317
+ * | Reserved | address | Reserved | Byte length |
318
+ * | 127:96 | 95:32 | 31:13 | 12:0 |
319
+ */
320
+ .dma_rd_rsp_valid ( dma_rd_rsp_valid ), // o, `DMA_RD_CHNL_NUM * 1
321
+ .dma_rd_rsp_last ( dma_rd_rsp_last ), // o, `DMA_RD_CHNL_NUM * 1
322
+ .dma_rd_rsp_data ( dma_rd_rsp_data ), // o, `DMA_RD_CHNL_NUM * `DMA_DATA_W
323
+ .dma_rd_rsp_head ( dma_rd_rsp_head ), // o, `DMA_RD_CHNL_NUM * `DMA_HEAD_W
324
+ .dma_rd_rsp_ready ( dma_rd_rsp_ready ), // i, `DMA_RD_CHNL_NUM * 1
325
+ /* ------- Read Response to RDMA{end} ------- */
326
+
327
+ /* -------axis read request interface{begin}------- */
328
+ /* AXI-Stream read request tuser, interact with read request arbiter.
329
+ * Only valid in first beat of a packet
330
+ * | Reserved | REQ_TYPE | Tag | address | Reserved | DW length | first BE | last BE |
331
+ * | 127:108 | 107:104 | 103:96 | 95:32 | 31:19 | 18:8 | 7:4 | 3:0 |
332
+ */
333
+ .axis_rd_req_tvalid ( axis_rreq_tvalid ), // o, 1
334
+ .axis_rd_req_tlast ( axis_rreq_tlast ), // o, 1
335
+ .axis_rd_req_tdata ( axis_rreq_tdata ), // o, `DMA_DATA_W
336
+ .axis_rd_req_tuser ( axis_rreq_tuser ), // o, `AXIS_TUSER_W
337
+ .axis_rd_req_tkeep ( axis_rreq_tkeep ), // o, `DMA_KEEP_W
338
+ .axis_rd_req_tready ( axis_rreq_tready ), // i, 1
339
+ /* -------axis read request interface{end}------- */
340
+
341
+ /* -------axis read response interface{begin}------- */
342
+ /* AXI-Stream read response tuser, interact with read response distributor.
343
+ * Only valid in first beat of a packet
344
+ * | Reserved | REQ CPL | Tag | address | Reserved | DW length | first BE | last BE |
345
+ * | 119:105 | 104 | 103:96 | 95:32 | 31:19 | 18:8 | 7:4 | 3:0 |
346
+ */
347
+ .axis_rd_rsp_tvalid ( dma_axis_rrsp_tvalid ), // i, 1
348
+ .axis_rd_rsp_tlast ( dma_axis_rrsp_tlast ), // i, 1
349
+ .axis_rd_rsp_tdata ( dma_axis_rrsp_tdata ), // i, `DMA_DATA_W
350
+ .axis_rd_rsp_tuser ( dma_axis_rrsp_tuser ), // i, `AXIS_TUSER_W
351
+ .axis_rd_rsp_tkeep ( dma_axis_rrsp_tkeep ), // i, `DMA_KEEP_W
352
+ .axis_rd_rsp_tready ( dma_axis_rrsp_tready ), // o, 1
353
+ /* -------axis read response interface{end}------- */
354
+
355
+ /* -------PCIe fragment property{begin}------- */
356
+ /* This signal indicates the (max payload size & max read request size) agreed in the communication
357
+ * 3'b000 -- 128 B
358
+ * 3'b001 -- 256 B
359
+ * 3'b010 -- 512 B
360
+ * 3'b011 -- 1024B
361
+ * 3'b100 -- 2048B
362
+ * 3'b101 -- 4096B
363
+ */
364
+ .max_pyld_sz ( max_pyld_sz ), // i, 3
365
+ .max_rd_req_sz ( max_rd_req_sz ) // i, 3
366
+ /* -------PCIe fragment property{end}------- */
367
+
368
+ `ifdef PCIEI_APB_DBG
369
+ /* -------APB reated signal{begin}------- */
370
+ ,.rw_data ( rw_data_rd_req_rsp ) // i, (2*`DMA_RD_CHNL_NUM+3)*`SRAM_RW_DATA_W
371
+ ,.dbg_sel ( dbg_sel_rd_req_rsp ) // i, 32
372
+ ,.dbg_bus ( dbg_bus_rd_req_rsp ) // o, 32
373
+ /* -------APB reated signal{end}------- */
374
+ `endif
375
+
376
+ `ifdef SIMULATION
377
+ /* ------- Debug interface {begin}------- */
378
+ /* | reserved | idx | end | out |
379
+ * | 255:CHNL_NUM_LOG+2 | CHNL_NUM_LOG+2-1:2 | 1 | 0 |
380
+ */
381
+ ,.debug_rd ( debug_rd )
382
+
383
+ /* | reserved | tag_num | chnl_num | valid |
384
+ * | 255:17 | 16:9 | 8:1 | 0 |
385
+ */
386
+ ,.debug_tag( debug_tag)
387
+ /* ------- Debug interface {end}------- */
388
+ `endif
389
+ );
390
+
391
+ genvar i;
392
+ generate
393
+ for (i = 0; i < `DMA_WR_CHNL_NUM; i = i + 1) begin:DMA_WR_CHNL
394
+
395
+ write_request #(
396
+
397
+ ) wr_req (
398
+ .clk ( dma_clk ), // i, 1
399
+ .rst_n ( rst_n ), // i, 1
400
+
401
+ /* -------dma write request interface{begin}------- */
402
+ /* *_head of DMA interface (interact with RDMA modules),
403
+ * valid only in first beat of a packet.
404
+ * When Transmiting msi-x interrupt message, 'Byte length'
405
+ * should be 0, 'address' means the address of msi-x, and
406
+ * msi-x data locates in *_data[31:0].
407
+ * | Resvd | Req Type | address | Reserved | Byte length |
408
+ * | | (wr,int) | (msi-x addr) | | (0 for int) |
409
+ * |-------|----------|--------------|----------|-------------|
410
+ * |127:100| 99:96 | 95:32 | 31:13 | 12:0 |
411
+ */
412
+ .dma_wr_req_valid ( dma_wr_req_valid[(i + 1) * 1 - 1 : i * 1 ] ), // i, 1
413
+ .dma_wr_req_last ( dma_wr_req_last [(i + 1) * 1 - 1 : i * 1 ] ), // i, 1
414
+ .dma_wr_req_data ( dma_wr_req_data [(i + 1) * `DMA_DATA_W - 1 : i * `DMA_DATA_W] ), // i, `DMA_DATA_W
415
+ .dma_wr_req_head ( dma_wr_req_head [(i + 1) * `DMA_HEAD_W - 1 : i * `DMA_HEAD_W] ), // i, `DMA_HEAD_W
416
+ .dma_wr_req_ready ( dma_wr_req_ready[(i + 1) * 1 - 1 : i * 1 ] ), // o, 1
417
+ /* -------dma write request interface{end}------- */
418
+
419
+ /* -------axis write request interface{begin}------- */
420
+ /* AXI-Stream write request tuser, only valid in first beat of a packet
421
+ * | Reserved | REQ_TYPE | Tag | address | Reserved | DW length | first BE | last BE |
422
+ * | 127:108 | 107:104 | 103:96 | 95:32 | 31:19 | 18:8 | 7:4 | 3:0 |
423
+ * or
424
+ * AXI-Stream interrupt request tuser, only valid in first beat of a packet
425
+ * | Reserved | REQ_TYPE | Resv | address | Reserved |
426
+ * | 127:108 | 107:104 | 103:96 | 95:32 | 31:0 |
427
+ */
428
+ .axis_wr_req_tvalid ( axis_wr_req_tvalid[(i+1) * 1 - 1 : i * 1 ] ), // o, 1
429
+ .axis_wr_req_tlast ( axis_wr_req_tlast [(i+1) * 1 - 1 : i * 1 ] ), // o, 1
430
+ .axis_wr_req_tdata ( axis_wr_req_tdata [(i+1) * `DMA_DATA_W - 1 : i * `DMA_DATA_W ] ), // o, `DMA_DATA_W
431
+ .axis_wr_req_tuser ( axis_wr_req_tuser [(i+1) * `AXIS_TUSER_W - 1 : i * `AXIS_TUSER_W] ), // o, `AXIS_TUSER_W ;The field contents are different from dma_*_tuser interface
432
+ .axis_wr_req_tkeep ( axis_wr_req_tkeep [(i+1) * `DMA_KEEP_W - 1 : i * `DMA_KEEP_W ] ), // o, `DMA_KEEP_W
433
+ .axis_wr_req_tready ( axis_wr_req_tready[(i+1) * 1 - 1 : i * 1 ] ), // i, 1
434
+ /* -------axis write request interface{end}------- */
435
+
436
+
437
+ /* -------PCIe fragment property{begin}------- */
438
+ /* This signal indicates the (max payload size & max read request size) agreed in the communication
439
+ * 3'b000 -- 128 B
440
+ * 3'b001 -- 256 B
441
+ * 3'b010 -- 512 B
442
+ * 3'b011 -- 1024B
443
+ * 3'b100 -- 2048B
444
+ * 3'b101 -- 4096B
445
+ */
446
+ .max_pyld_sz ( max_pyld_sz ),
447
+ .max_rd_req_sz ( max_rd_req_sz ) // max read request size
448
+ /* -------PCIe fragment property{end}------- */
449
+
450
+ `ifdef PCIEI_APB_DBG
451
+ /* -------APB reated signal{begin}------- */
452
+ ,.rw_data ( rw_data_wr_req[(i+1)*`SRAM_RW_DATA_W-1:i*`SRAM_RW_DATA_W] ) // i, `SRAM_RW_DATA_W
453
+ ,.dbg_signal ( dbg_signal_wr_req[(i+1)*`WR_REQ_SIGNAL_W-1:i*`WR_REQ_SIGNAL_W] ) // o, `WR_REQ_SIGNAL_W
454
+ /* -------APB reated signal{end}------- */
455
+ `endif
456
+ );
457
+
458
+ end
459
+ endgenerate
460
+
461
+ req_arbiter #(
462
+ .CHNL_NUM_LOG ( `DMA_WR_CHNL_NUM_LOG ),
463
+ .CHANNEL_NUM ( `DMA_WR_CHNL_NUM ) // number of slave signals to arbit
464
+ ) wr_req_arbiter (
465
+
466
+ .dma_clk ( dma_clk ), // i, 1
467
+ .rst_n ( rst_n ), // i, 1
468
+
469
+ /* -------Slave AXIS Interface(Connect to <Write Request> Module){begin}------- */
470
+ /* AXI-Stream write request tuser, only valid in first beat of a packet
471
+ * | Reserved | REQ_TYPE | Tag | address | Reserved | DW length | first BE | last BE |
472
+ * | 127:108 | 107:104 | 103:96 | 95:32 | 31:19 | 18:8 | 7:4 | 3:0 |
473
+ * or
474
+ * AXI-Stream interrupt request tuser, only valid in first beat of a packet
475
+ * | Reserved | REQ_TYPE | Resv | address | Reserved |
476
+ * | 127:108 | 107:104 | 103:96 | 95:32 | 31:0 |
477
+ */
478
+ .s_axis_req_tvalid ( axis_wr_req_tvalid ), // i, 1 * CHANNEL_NUM
479
+ .s_axis_req_tlast ( axis_wr_req_tlast ), // i, 1 * CHANNEL_NUM
480
+ .s_axis_req_tdata ( axis_wr_req_tdata ), // i, `DMA_DATA_W * CHANNEL_NUM
481
+ .s_axis_req_tuser ( axis_wr_req_tuser ), // i, `AXIS_TUSER_W * CHANNEL_NUM ;The field contents are different from dma_*_tuser interface
482
+ .s_axis_req_tkeep ( axis_wr_req_tkeep ), // i, `DMA_KEEP_W * CHANNEL_NUM
483
+ .s_axis_req_tready ( axis_wr_req_tready ), // o, 1 * CHANNEL_NUM
484
+ /* -------Slave AXIS Interface(Connect to <Write Request> Module){end}------- */
485
+
486
+
487
+ /* ------- Master AXIS Interface(Connect to PCIe or converter){begin} ------- */
488
+ /* AXI-Stream write request tuser, only valid in first beat of a packet
489
+ * | Reserved | REQ_TYPE | Tag | address | Reserved | DW length | first BE | last BE |
490
+ * | 127:108 | 107:104 | 103:96 | 95:32 | 31:19 | 18:8 | 7:4 | 3:0 |
491
+ * or
492
+ * AXI-Stream interrupt request tuser, only valid in first beat of a packet
493
+ * | Reserved | REQ_TYPE | Resv | address | Reserved |
494
+ * | 127:108 | 107:104 | 103:96 | 95:32 | 31:0 |
495
+ */
496
+ .m_axis_req_tvalid ( axis_wreq_tvalid ), // o, 1
497
+ .m_axis_req_tlast ( axis_wreq_tlast ), // o, 1
498
+ .m_axis_req_tdata ( axis_wreq_tdata ), // o, `DMA_DATA_W
499
+ .m_axis_req_tuser ( axis_wreq_tuser ), // o, `AXIS_TUSER_W ;The field contents are different from dma_*_head interface
500
+ .m_axis_req_tkeep ( axis_wreq_tkeep ), // o, `DMA_KEEP_W
501
+ .m_axis_req_tready ( axis_wreq_tready ) // i, 1
502
+ /* ------- Master AXIS Interface(Connect to PCIe or converter){end} ------- */
503
+
504
+ `ifdef PCIEI_APB_DBG
505
+ /* -------APB reated signal{begin}------- */
506
+ ,.dbg_signal ( dbg_signal_wreq_arb ) // o, `WREQ_ARB_SIGNAL_W
507
+ /* -------APB reated signal{end}------- */
508
+ `endif
509
+
510
+ `ifdef SIMULATION
511
+ /* ------- Debug interface {begin}------- */
512
+ /* | reserved | idx | end | out |
513
+ * | 255:CHNL_NUM_LOG+2 | CHNL_NUM_LOG+2-1:2 | 1 | 0 |
514
+ */
515
+ ,.debug ( debug_wr )
516
+ /* ------- Debug interface {end}------- */
517
+ `endif
518
+ );
519
+
520
+ req_arbiter #(
521
+ .CHNL_NUM_LOG ( 1 ),
522
+ .CHANNEL_NUM ( 2 ) // number of slave signals to arbit
523
+
524
+ ) req_arbiter (
525
+ .dma_clk ( dma_clk ), // i, 1
526
+ .rst_n ( rst_n ), // i, 1
527
+
528
+ /* -------Slave AXIS Interface(Connect to <Write Request> Module){begin}------- */
529
+ /* AXI-Stream request tuser, only valid in first beat of a packet
530
+ * | Reserved | REQ_TYPE | Tag | address | Reserved | DW length | first BE | last BE |
531
+ * | 127:108 | 107:104 | 103:96 | 95:32 | 31:19 | 18:8 | 7:4 | 3:0 |
532
+ * or
533
+ * AXI-Stream interrupt request tuser, only valid in first beat of a packet
534
+ * | Reserved | REQ_TYPE | Resv | address | Reserved |
535
+ * | 127:108 | 107:104 | 103:96 | 95:32 | 31:0 |
536
+ */
537
+ .s_axis_req_tvalid ( {axis_wreq_tvalid, axis_rreq_tvalid} ), // i, 1 * CHANNEL_NUM
538
+ .s_axis_req_tlast ( {axis_wreq_tlast , axis_rreq_tlast } ), // i, 1 * CHANNEL_NUM
539
+ .s_axis_req_tdata ( {axis_wreq_tdata , axis_rreq_tdata } ), // i, `DMA_DATA_W * CHANNEL_NUM
540
+ .s_axis_req_tuser ( {axis_wreq_tuser , axis_rreq_tuser } ), // i, `AXIS_TUSER_W * CHANNEL_NUM ;The field contents are different from dma_*_tuser interface
541
+ .s_axis_req_tkeep ( {axis_wreq_tkeep , axis_rreq_tkeep } ), // i, `DMA_KEEP_W * CHANNEL_NUM
542
+ .s_axis_req_tready ( {axis_wreq_tready, axis_rreq_tready} ), // o, 1 * CHANNEL_NUM
543
+ /* -------Slave AXIS Interface(Connect to <Write Request> Module){end}------- */
544
+
545
+ /* ------- Master AXIS Interface(Connect to PCIe or converter){begin} ------- */
546
+ /* AXI-Stream request tuser, only valid in first beat of a packet
547
+ * | Reserved | REQ_TYPE | Tag | address | Reserved | DW length | first BE | last BE |
548
+ * | 127:108 | 107:104 | 103:96 | 95:32 | 31:19 | 18:8 | 7:4 | 3:0 |
549
+ * or
550
+ * AXI-Stream interrupt request tuser, only valid in first beat of a packet
551
+ * | Reserved | REQ_TYPE | Resv | address | Reserved |
552
+ * | 127:108 | 107:104 | 103:96 | 95:32 | 31:0 |
553
+ */
554
+ .m_axis_req_tvalid ( axis_req_tvalid ), // o, 1
555
+ .m_axis_req_tlast ( axis_req_tlast ), // o, 1
556
+ .m_axis_req_tdata ( axis_req_tdata ), // o, `DMA_DATA_W
557
+ .m_axis_req_tuser ( axis_req_tuser ), // o, `AXIS_TUSER_W ;The field contents are different from dma_*_head interface
558
+ .m_axis_req_tkeep ( axis_req_tkeep ), // o, `DMA_KEEP_W
559
+ .m_axis_req_tready ( axis_req_tready ) // i, 1
560
+ /* ------- Master AXIS Interface(Connect to PCIe or converter){end} ------- */
561
+
562
+ `ifdef PCIEI_APB_DBG
563
+ /* -------APB reated signal{begin}------- */
564
+ ,.dbg_signal ( dbg_signal_req_arb ) // o, `REQ_ARB_SIGNAL_W
565
+ /* -------APB reated signal{end}------- */
566
+ `endif
567
+
568
+ `ifdef SIMULATION
569
+ /* ------- Debug interface {begin}------- */
570
+ /* | reserved | idx | end | out |
571
+ * | 255:CHNL_NUM_LOG+2 | CHNL_NUM_LOG+2-1:2 | 1 | 0 |
572
+ */
573
+ ,.debug (debug_top)
574
+ /* ------- Debug interface {end}------- */
575
+ `endif
576
+ );
577
+
578
+
579
+ req_converter #(
580
+
581
+ ) req_converter (
582
+ .pcie_clk ( pcie_clk ), // i, 1
583
+ .pcie_rst_n ( pcie_rst_n ), // i, 1
584
+ .dma_clk ( dma_clk ), // i, 1
585
+ .rst_n ( rst_n ), // i, 1
586
+
587
+
588
+ /* ------- Interface with Request Arbiter{begin} ------- */
589
+ /* AXI-Stream request tuser, only valid in first beat of a packet
590
+ * | Reserved | REQ_TYPE | Tag | address | Reserved | DW length | first BE | last BE |
591
+ * | 127:108 | 107:104 | 103:96 | 95:32 | 31:19 | 18:8 | 7:4 | 3:0 |
592
+ * or
593
+ * AXI-Stream interrupt request tuser, only valid in first beat of a packet
594
+ * | Reserved | REQ_TYPE | Resv | address | Reserved |
595
+ * | 127:108 | 107:104 | 103:96 | 95:32 | 31:0 |
596
+ */
597
+ .axis_req_tvalid ( axis_req_tvalid ), // i, 1
598
+ .axis_req_tlast ( axis_req_tlast ), // i, 1
599
+ .axis_req_tdata ( axis_req_tdata ), // i, `DMA_DATA_W
600
+ .axis_req_tuser ( axis_req_tuser ), // i, `AXIS_TUSER_W
601
+ .axis_req_tkeep ( axis_req_tkeep ), // i, `DMA_KEEP_W
602
+ .axis_req_tready ( axis_req_tready ), // o, 1
603
+ /* ------- Interface with Request Arbiter{end} ------- */
604
+
605
+ /* -------dma --> pcie interface{begin}------- */
606
+ // Requester request
607
+ /* RQ tuser
608
+ * | 59:28 | 27:24 | 23:16 | 15 | 14:13 | 12 | 11 | 10:8 | 7:4 | 3:0 |
609
+ * | parity | seq_num | tph_st_tag | tph_indirect_tag_en | tph_type | tph_present | discontinue | addr_offset | last_be | first_be |
610
+ * | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | |
611
+ */
612
+ .s_axis_rq_tvalid ( dma_axis_rq_tvalid ), // o, 1
613
+ .s_axis_rq_tlast ( dma_axis_rq_tlast ), // o, 1
614
+ .s_axis_rq_tdata ( dma_axis_rq_tdata ), // o, `DMA_DATA_W
615
+ .s_axis_rq_tuser ( dma_axis_rq_tuser ), // o, 60
616
+ .s_axis_rq_tkeep ( dma_axis_rq_tkeep ), // o, `DMA_KEEP_W
617
+ .s_axis_rq_tready ( dma_axis_rq_tready ), // i, 1
618
+ /* -------dma --> pcie interface{end}------- */
619
+
620
+ .req_id_in ( req_id ), // i, 16
621
+
622
+ /* -------Interrupt Interface Signals{begin}------- */
623
+ .cfg_interrupt_msix_enable ( cfg_interrupt_msix_enable ), // i, 2
624
+ .cfg_interrupt_msix_mask ( cfg_interrupt_msix_mask ), // i, 2
625
+ .cfg_interrupt_msix_data ( cfg_interrupt_msix_data ), // o, 32
626
+ .cfg_interrupt_msix_address ( cfg_interrupt_msix_address ), // o, 64
627
+ .cfg_interrupt_msix_int ( cfg_interrupt_msix_int ), // o, 1
628
+ .cfg_interrupt_msix_sent ( cfg_interrupt_msix_sent ), // i, 1
629
+ .cfg_interrupt_msix_fail ( cfg_interrupt_msix_fail ), // i, 1
630
+ .cfg_interrupt_msi_function_number ( cfg_interrupt_msi_function_number ) // o, 3
631
+ /* -------Interrupt Interface Signals{end}------- */
632
+
633
+ `ifdef PCIEI_APB_DBG
634
+ /* -------APB reated signal{begin}------- */
635
+ ,.rw_data ( rw_data_int ) // i, `SRAM_RW_DATA_W
636
+ ,.dbg_sel ( dbg_sel_req_convert ) // i, 32
637
+ ,.dbg_bus ( dbg_bus_req_convert ) // o, 32
638
+ /* -------APB reated signal{end}------- */
639
+ `endif
640
+ );
641
+
642
+ rsp_converter #(
643
+
644
+ ) rsp_converter (
645
+ .dma_clk ( pcie_clk ), // i, 1
646
+ .rst_n ( rst_n ), // i, 1
647
+
648
+ /* ------- pcie --> dma interface{begin}------- */
649
+ // Requester Completion
650
+ /* RC tuser
651
+ * | 74:43 | 42 | 41:38 | 37:34 | 33 | 32 | 31:0 |
652
+ * | parity | discontinue | is_eof_1 | is_eof_0 | is_sof_1 | is_sof_0 | byte_en |
653
+ * | ignore | ignore | ignore | ignore | ignore | ignore | |
654
+ */
655
+ .m_axis_rc_tvalid ( m_axis_rc_tvalid ), // i, 1
656
+ .m_axis_rc_tlast ( m_axis_rc_tlast ), // i, 1
657
+ .m_axis_rc_tdata ( m_axis_rc_tdata ), // i, `DMA_DATA_W
658
+ .m_axis_rc_tuser ( m_axis_rc_tuser ), // i, 75
659
+ .m_axis_rc_tkeep ( m_axis_rc_tkeep ), // i, `DMA_KEEP_W
660
+ .m_axis_rc_tready ( m_axis_rc_tready ), // o, 1
661
+ /* ------- pcie --> dma interface{end}------- */
662
+
663
+
664
+ /* ------- Interface with dma read module{begin}------- */
665
+ /* AXI-Stream read response tuser, interact with read response distributor.
666
+ * Only valid in first beat of a packet
667
+ * | Reserved | REQ CPL | Tag | address | Reserved | DW length | first BE | last BE |
668
+ * | 119:105 | 104 | 103:96 | 95:32 | 31:19 | 18:8 | 7:4 | 3:0 |
669
+ */
670
+ .axis_rd_rsp_tvalid ( pcie_axis_rrsp_tvalid ), // o, 1
671
+ .axis_rd_rsp_tlast ( pcie_axis_rrsp_tlast ), // o, 1
672
+ .axis_rd_rsp_tdata ( pcie_axis_rrsp_tdata ), // o, `DMA_DATA_W
673
+ .axis_rd_rsp_tuser ( pcie_axis_rrsp_tuser ), // o, `AXIS_TUSER_W
674
+ .axis_rd_rsp_tkeep ( pcie_axis_rrsp_tkeep ), // o, `DMA_KEEP_W
675
+ .axis_rd_rsp_tready ( pcie_axis_rrsp_tready ) // i, 1
676
+ /* ------- Interface with dma read module{end}------- */
677
+
678
+ `ifdef PCIEI_APB_DBG
679
+ /* -------APB reated signal{begin}------- */
680
+ ,.dbg_sel ( dbg_sel_rsp_convert ) // i, 32
681
+ ,.dbg_bus ( dbg_bus_rsp_convert ) // o, 32
682
+ /* -------APB reated signal{end}------- */
683
+ `endif
684
+ );
685
+
686
+
687
+ rq_async_fifos #(
688
+
689
+ ) rq_async_fifos (
690
+ .dma_clk ( dma_clk ),
691
+ .pcie_clk ( pcie_clk ),
692
+ .dma_rst_n ( rst_n ),
693
+ .pcie_rst_n ( pcie_rst_n ),
694
+
695
+ /* -------rdma write request interface{begin}------- */
696
+
697
+ /* -------dma --> pcie interface, dma part{begin}------- */
698
+ // Requester request
699
+ /* RQ tuser
700
+ * | 59:28 | 27:24 | 23:16 | 15 | 14:13 | 12 | 11 | 10:8 | 7:4 | 3:0 |
701
+ * | parity | seq_num | tph_st_tag | tph_indirect_tag_en | tph_type | tph_present | discontinue | addr_offset | last_be | first_be |
702
+ * | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | |
703
+ */
704
+ .dma_axis_rq_tvalid ( dma_axis_rq_tvalid ), // i, 1
705
+ .dma_axis_rq_tlast ( dma_axis_rq_tlast ), // i, 1
706
+ .dma_axis_rq_tdata ( dma_axis_rq_tdata ), // i, `DMA_DATA_W
707
+ .dma_axis_rq_tuser ( dma_axis_rq_tuser ), // i, 60
708
+ .dma_axis_rq_tkeep ( dma_axis_rq_tkeep ), // i, `DMA_KEEP_W
709
+ .dma_axis_rq_tready ( dma_axis_rq_tready ), // o, 1
710
+ /* -------dma --> pcie interface, dma part{end}------- */
711
+
712
+ /* -------dma --> pcie interface, pcie part{begin}------- */
713
+ // Requester request
714
+ /* RQ tuser
715
+ * | 59:28 | 27:24 | 23:16 | 15 | 14:13 | 12 | 11 | 10:8 | 7:4 | 3:0 |
716
+ * | parity | seq_num | tph_st_tag | tph_indirect_tag_en | tph_type | tph_present | discontinue | addr_offset | last_be | first_be |
717
+ * | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | |
718
+ */
719
+ .st_pcie_axis_rq_tvalid ( s_axis_rq_tvalid ), // o, 1
720
+ .st_pcie_axis_rq_tlast ( s_axis_rq_tlast ), // o, 1
721
+ .st_pcie_axis_rq_tdata ( s_axis_rq_tdata ), // o, `DMA_DATA_W
722
+ .st_pcie_axis_rq_tuser ( s_axis_rq_tuser ), // o, 60
723
+ .st_pcie_axis_rq_tkeep ( s_axis_rq_tkeep ), // o, `DMA_KEEP_W
724
+ .st_pcie_axis_rq_tready ( s_axis_rq_tready ) // i, 1
725
+ /* -------dma --> pcie interface, pcie part{begin}------- */
726
+
727
+ `ifdef PCIEI_APB_DBG
728
+ /* -------APB reated signal{begin}------- */
729
+ ,.rw_data ( rw_data_rq ) // i, `SRAM_RW_DATA_W
730
+ ,.dbg_signal ( dbg_signal_rq_async ) // o, `RQ_ASYNC_SIGNAL_W
731
+ /* -------APB reated signal{end}------- */
732
+ `endif
733
+ );
734
+
735
+
736
+ // rc_async_fifos #(
737
+
738
+ // ) rc_async_fifos (
739
+ // .dma_clk ( dma_clk ),
740
+ // .pcie_clk ( pcie_clk ),
741
+ // .dma_rst_n ( rst_n ),
742
+ // .pcie_rst_n ( pcie_rst_n ),
743
+
744
+ // /* ------- pcie --> dma interface, pcie part{begin}------- */
745
+ // // Requester Completion
746
+ // /* RC tuser
747
+ // * | 74:43 | 42 | 41:38 | 37:34 | 33 | 32 | 31:0 |
748
+ // * | parity | discontinue | is_eof_1 | is_eof_0 | is_sof_1 | is_sof_0 | byte_en |
749
+ // * | ignore | ignore | ignore | ignore | ignore | ignore | |
750
+ // */
751
+ // .pcie_axis_rc_tvalid ( m_axis_rc_tvalid ), // i, 1
752
+ // .pcie_axis_rc_tlast ( m_axis_rc_tlast ), // i, 1
753
+ // .pcie_axis_rc_tdata ( m_axis_rc_tdata ), // i, `DMA_DATA_W
754
+ // .pcie_axis_rc_tuser ( m_axis_rc_tuser ), // i, 75
755
+ // .pcie_axis_rc_tkeep ( m_axis_rc_tkeep ), // i, `DMA_KEEP_W
756
+ // .pcie_axis_rc_tready ( m_axis_rc_tready ), // o, 1
757
+ // /* ------- pcie --> dma interface, pcie part{end}------- */
758
+
759
+ // /* ------- pcie --> dma interface, dma part{begin}------- */
760
+ // // Requester Completion
761
+ // /* RC tuser
762
+ // * | 74:43 | 42 | 41:38 | 37:34 | 33 | 32 | 31:0 |
763
+ // * | parity | discontinue | is_eof_1 | is_eof_0 | is_sof_1 | is_sof_0 | byte_en |
764
+ // * | ignore | ignore | ignore | ignore | ignore | ignore | |
765
+ // */
766
+ // .dma_axis_rc_tvalid ( dma_axis_rc_tvalid ), // o, 1
767
+ // .dma_axis_rc_tlast ( dma_axis_rc_tlast ), // o, 1
768
+ // .dma_axis_rc_tdata ( dma_axis_rc_tdata ), // o, `DMA_DATA_W
769
+ // .dma_axis_rc_tuser ( dma_axis_rc_tuser ), // o, 75
770
+ // .dma_axis_rc_tkeep ( dma_axis_rc_tkeep ), // o, `DMA_KEEP_W
771
+ // .dma_axis_rc_tready ( dma_axis_rc_tready ) // i, 1
772
+ // /* ------- pcie --> dma interface, dma part{end}------- */
773
+
774
+ // `ifdef PCIEI_APB_DBG
775
+ // /* -------APB reated signal{begin}------- */
776
+ // ,.rw_data ( rw_data_rc ) // i, `SRAM_RW_DATA_W
777
+ // ,.dbg_signal ( dbg_signal_rc_async ) // o, `RC_ASYNC_SIGNAL_W
778
+ // /* -------APB reated signal{end}------- */
779
+ // `endif
780
+ // );
781
+
782
+ rrsp_async_fifos #(
783
+
784
+ ) rrsp_async_fifos (
785
+ .dma_clk ( dma_clk ),
786
+ .pcie_clk ( pcie_clk ),
787
+ .dma_rst_n ( rst_n ),
788
+ .pcie_rst_n ( pcie_rst_n ),
789
+
790
+ /* ------- pcie clock domain{begin}------- */
791
+ /* AXI-Stream read response tuser, interact with read response distributor.
792
+ * Only valid in first beat of a packet
793
+ * | Reserved | REQ CPL | Tag | address | Reserved | DW length | first BE | last BE |
794
+ * | 119:105 | 104 | 103:96 | 95:32 | 31:19 | 18:8 | 7:4 | 3:0 |
795
+ */
796
+ .pcie_axis_rrsp_tvalid ( pcie_axis_rrsp_tvalid ), // i, 1
797
+ .pcie_axis_rrsp_tlast ( pcie_axis_rrsp_tlast ), // i, 1
798
+ .pcie_axis_rrsp_tdata ( pcie_axis_rrsp_tdata ), // i, `DMA_DATA_W
799
+ .pcie_axis_rrsp_tuser ( pcie_axis_rrsp_tuser ), // i, `AXIS_TUSER_W
800
+ .pcie_axis_rrsp_tkeep ( pcie_axis_rrsp_tkeep ), // i, `DMA_KEEP_W
801
+ .pcie_axis_rrsp_tready ( pcie_axis_rrsp_tready ), // o, 1
802
+ /* ------- pcie clock domain{end}------- */
803
+
804
+ /* ------- dma clock domain{begin}------- */
805
+ /* AXI-Stream read response tuser, interact with read response distributor.
806
+ * Only valid in first beat of a packet
807
+ * | Reserved | REQ CPL | Tag | address | Reserved | DW length | first BE | last BE |
808
+ * | 119:105 | 104 | 103:96 | 95:32 | 31:19 | 18:8 | 7:4 | 3:0 |
809
+ */
810
+ .dma_axis_rrsp_tvalid ( dma_axis_rrsp_tvalid ), // o, 1
811
+ .dma_axis_rrsp_tlast ( dma_axis_rrsp_tlast ), // o, 1
812
+ .dma_axis_rrsp_tdata ( dma_axis_rrsp_tdata ), // o, `DMA_DATA_W
813
+ .dma_axis_rrsp_tuser ( dma_axis_rrsp_tuser ), // o, `AXIS_TUSER_W
814
+ .dma_axis_rrsp_tkeep ( dma_axis_rrsp_tkeep ), // o, `DMA_KEEP_W
815
+ .dma_axis_rrsp_tready ( dma_axis_rrsp_tready ) // i, 1
816
+ /* ------- dma clock domain{end}------- */
817
+
818
+ `ifdef PCIEI_APB_DBG
819
+ /* -------APB reated signal{begin}------- */
820
+ ,.rw_data ( rw_data_rc ) // i, `SRAM_RW_DATA_W
821
+ ,.dbg_signal ( dbg_signal_rrsp_async ) // o, `RRSP_ASYNC_SIGNAL_W
822
+ /* -------APB reated signal{end}------- */
823
+ `endif
824
+ );
825
+
826
+ endmodule
ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/DMA/DMA_Read/dma_demux.v ADDED
@@ -0,0 +1,347 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ `timescale 1ns / 100ps
2
+ //*************************************************************************
3
+ // > File : dma_demux.v
4
+ // > Author : Kangning
5
+ // > Date : 2022-06-29
6
+ // > Note : demux module for pio, used for read & write request.
7
+ // > V1.1 2022-06-08: Now, It only support 2 or 3 output channels.
8
+ // > V1.2 2022-06-29: Suppports up to 16 channels
9
+ //*************************************************************************
10
+
11
+ module dma_demux #(
12
+ parameter CHANNEL_NUM = 2 // number of channels for output
13
+ ) (
14
+ input wire clk , // i, 1
15
+ input wire rst_n, // i, 1
16
+
17
+ input wire nxt_demux_vld, // i, 1
18
+ input wire [7:0] nxt_demux_sel, // i, 8
19
+
20
+ /* --------PIO Write Request interface{begin}-------- */
21
+ /* head
22
+ * | 130:128 | 127:96 | 95:0 |
23
+ * | bar_id | addr | cc_head |
24
+ */
25
+ input wire s_axis_req_valid, // i, 1
26
+ input wire s_axis_req_last , // i, 1
27
+ input wire [`DMA_HEAD_W-1:0] s_axis_req_head , // i, `DMA_HEAD_W
28
+ input wire [`DMA_DATA_W-1:0] s_axis_req_data , // i, `DMA_DATA_W
29
+ output wire s_axis_req_ready, // o, 1
30
+
31
+ output wire [CHANNEL_NUM * 1 -1:0] m_axis_req_valid, // o, CHANNEL_NUM * 1
32
+ output wire [CHANNEL_NUM * 1 -1:0] m_axis_req_last , // o, CHANNEL_NUM * 1
33
+ output wire [CHANNEL_NUM * `DMA_HEAD_W-1:0] m_axis_req_head , // o, CHANNEL_NUM * `DMA_HEAD_W
34
+ output wire [CHANNEL_NUM * `DMA_DATA_W-1:0] m_axis_req_data , // o, CHANNEL_NUM * `DMA_DATA_W
35
+ input wire [CHANNEL_NUM * 1 -1:0] m_axis_req_ready // i, CHANNEL_NUM * 1
36
+ /* --------PIO Write Request interface{end}-------- */
37
+
38
+ `ifdef PCIEI_APB_DBG
39
+ /* -------APB reated signal{begin}------- */
40
+ ,output wire [`DMA_DEMUX_SIGNAL_W-1:0] dbg_signal // o, `DMA_DEMUX_SIGNAL_W
41
+ /* -------APB reated signal{end}------- */
42
+ `endif
43
+ );
44
+
45
+ reg [7:0] sel;
46
+
47
+ /* -------State relevant in FSM{begin}------- */
48
+ localparam IDLE = 2'b01,
49
+ TRANS = 2'b10;
50
+
51
+ reg [1:0] cur_state;
52
+ reg [1:0] nxt_state;
53
+
54
+ wire is_idle, is_trans;
55
+ /* -------State relevant in FSM{end}------- */
56
+
57
+ //---------------------------------------------------------------------------------------------------------------------------
58
+
59
+ `ifdef PCIEI_APB_DBG
60
+ /* -------APB reated signal{begin}------- */
61
+ assign dbg_signal = { // 14
62
+ sel, // 8
63
+ cur_state, nxt_state, // 4
64
+ is_idle, is_trans // 2
65
+ };
66
+ /* -------APB reated signal{end}------- */
67
+ `endif
68
+
69
+ /* -------{Read Response Distributor FSM}begin------- */
70
+ /******************** Stage 1: State Register **********************/
71
+
72
+ assign is_idle = (cur_state == IDLE );
73
+ assign is_trans = (cur_state == TRANS);
74
+
75
+ always @(posedge clk, negedge rst_n) begin
76
+ if(~rst_n)
77
+ cur_state <= `TD IDLE;
78
+ else
79
+ cur_state <= `TD nxt_state;
80
+ end
81
+
82
+ always @(posedge clk, negedge rst_n) begin
83
+ if (~rst_n) begin
84
+ sel <= `TD 8'd0;
85
+ end
86
+ else if ((is_idle & nxt_demux_vld) ||
87
+ (is_trans & s_axis_req_last & s_axis_req_valid & s_axis_req_ready & nxt_demux_vld)) begin
88
+ sel <= `TD nxt_demux_sel;
89
+ end
90
+ end
91
+
92
+ /* -------Generate block{begin}------- */
93
+ /* This is used for different Channel Numbers, the default Number is 4
94
+ */
95
+ generate
96
+ if (CHANNEL_NUM == 16) begin:CHNL_DEMUX_16
97
+
98
+ assign s_axis_req_ready = ((sel == 0) & is_trans & m_axis_req_ready[0]) |
99
+ ((sel == 1) & is_trans & m_axis_req_ready[1]) |
100
+ ((sel == 2) & is_trans & m_axis_req_ready[2]) |
101
+ ((sel == 3) & is_trans & m_axis_req_ready[3]) |
102
+ ((sel == 4) & is_trans & m_axis_req_ready[4]) |
103
+ ((sel == 5) & is_trans & m_axis_req_ready[5]) |
104
+ ((sel == 6) & is_trans & m_axis_req_ready[6]) |
105
+ ((sel == 7) & is_trans & m_axis_req_ready[7]) |
106
+ ((sel == 8) & is_trans & m_axis_req_ready[8]) |
107
+ ((sel == 9) & is_trans & m_axis_req_ready[9]) |
108
+ ((sel == 10) & is_trans & m_axis_req_ready[10])|
109
+ ((sel == 11) & is_trans & m_axis_req_ready[11])|
110
+ ((sel == 12) & is_trans & m_axis_req_ready[12])|
111
+ ((sel == 13) & is_trans & m_axis_req_ready[13])|
112
+ ((sel == 14) & is_trans & m_axis_req_ready[14])|
113
+ ((sel == 15) & is_trans & m_axis_req_ready[15]);
114
+
115
+ end // CHNL_DEMUX_16
116
+ else if (CHANNEL_NUM == 15) begin:CHNL_DEMUX_15
117
+
118
+ assign s_axis_req_ready = ((sel == 0) & is_trans & m_axis_req_ready[0]) |
119
+ ((sel == 1) & is_trans & m_axis_req_ready[1]) |
120
+ ((sel == 2) & is_trans & m_axis_req_ready[2]) |
121
+ ((sel == 3) & is_trans & m_axis_req_ready[3]) |
122
+ ((sel == 4) & is_trans & m_axis_req_ready[4]) |
123
+ ((sel == 5) & is_trans & m_axis_req_ready[5]) |
124
+ ((sel == 6) & is_trans & m_axis_req_ready[6]) |
125
+ ((sel == 7) & is_trans & m_axis_req_ready[7]) |
126
+ ((sel == 8) & is_trans & m_axis_req_ready[8]) |
127
+ ((sel == 9) & is_trans & m_axis_req_ready[9]) |
128
+ ((sel == 10) & is_trans & m_axis_req_ready[10])|
129
+ ((sel == 11) & is_trans & m_axis_req_ready[11])|
130
+ ((sel == 12) & is_trans & m_axis_req_ready[12])|
131
+ ((sel == 13) & is_trans & m_axis_req_ready[13])|
132
+ ((sel == 14) & is_trans & m_axis_req_ready[14]);
133
+
134
+ end // CHNL_DEMUX_15
135
+ else if (CHANNEL_NUM == 14) begin:CHNL_DEMUX_14
136
+
137
+ assign s_axis_req_ready = ((sel == 0) & is_trans & m_axis_req_ready[0]) |
138
+ ((sel == 1) & is_trans & m_axis_req_ready[1]) |
139
+ ((sel == 2) & is_trans & m_axis_req_ready[2]) |
140
+ ((sel == 3) & is_trans & m_axis_req_ready[3]) |
141
+ ((sel == 4) & is_trans & m_axis_req_ready[4]) |
142
+ ((sel == 5) & is_trans & m_axis_req_ready[5]) |
143
+ ((sel == 6) & is_trans & m_axis_req_ready[6]) |
144
+ ((sel == 7) & is_trans & m_axis_req_ready[7]) |
145
+ ((sel == 8) & is_trans & m_axis_req_ready[8]) |
146
+ ((sel == 9) & is_trans & m_axis_req_ready[9]) |
147
+ ((sel == 10) & is_trans & m_axis_req_ready[10])|
148
+ ((sel == 11) & is_trans & m_axis_req_ready[11])|
149
+ ((sel == 12) & is_trans & m_axis_req_ready[12])|
150
+ ((sel == 13) & is_trans & m_axis_req_ready[13]);
151
+
152
+ end // CHNL_DEMUX_14
153
+ else if (CHANNEL_NUM == 13) begin:CHNL_DEMUX_13
154
+
155
+ assign s_axis_req_ready = ((sel == 0) & is_trans & m_axis_req_ready[0]) |
156
+ ((sel == 1) & is_trans & m_axis_req_ready[1]) |
157
+ ((sel == 2) & is_trans & m_axis_req_ready[2]) |
158
+ ((sel == 3) & is_trans & m_axis_req_ready[3]) |
159
+ ((sel == 4) & is_trans & m_axis_req_ready[4]) |
160
+ ((sel == 5) & is_trans & m_axis_req_ready[5]) |
161
+ ((sel == 6) & is_trans & m_axis_req_ready[6]) |
162
+ ((sel == 7) & is_trans & m_axis_req_ready[7]) |
163
+ ((sel == 8) & is_trans & m_axis_req_ready[8]) |
164
+ ((sel == 9) & is_trans & m_axis_req_ready[9]) |
165
+ ((sel == 10) & is_trans & m_axis_req_ready[10])|
166
+ ((sel == 11) & is_trans & m_axis_req_ready[11])|
167
+ ((sel == 12) & is_trans & m_axis_req_ready[12]);
168
+
169
+ end // CHNL_DEMUX_13
170
+ else if (CHANNEL_NUM == 12) begin:CHNL_DEMUX_12
171
+
172
+ assign s_axis_req_ready = ((sel == 0) & is_trans & m_axis_req_ready[0]) |
173
+ ((sel == 1) & is_trans & m_axis_req_ready[1]) |
174
+ ((sel == 2) & is_trans & m_axis_req_ready[2]) |
175
+ ((sel == 3) & is_trans & m_axis_req_ready[3]) |
176
+ ((sel == 4) & is_trans & m_axis_req_ready[4]) |
177
+ ((sel == 5) & is_trans & m_axis_req_ready[5]) |
178
+ ((sel == 6) & is_trans & m_axis_req_ready[6]) |
179
+ ((sel == 7) & is_trans & m_axis_req_ready[7]) |
180
+ ((sel == 8) & is_trans & m_axis_req_ready[8]) |
181
+ ((sel == 9) & is_trans & m_axis_req_ready[9]) |
182
+ ((sel == 10) & is_trans & m_axis_req_ready[10])|
183
+ ((sel == 11) & is_trans & m_axis_req_ready[11]);
184
+
185
+ end // CHNL_DEMUX_12
186
+ else if (CHANNEL_NUM == 11) begin:CHNL_DEMUX_11
187
+
188
+ assign s_axis_req_ready = ((sel == 0) & is_trans & m_axis_req_ready[0]) |
189
+ ((sel == 1) & is_trans & m_axis_req_ready[1]) |
190
+ ((sel == 2) & is_trans & m_axis_req_ready[2]) |
191
+ ((sel == 3) & is_trans & m_axis_req_ready[3]) |
192
+ ((sel == 4) & is_trans & m_axis_req_ready[4]) |
193
+ ((sel == 5) & is_trans & m_axis_req_ready[5]) |
194
+ ((sel == 6) & is_trans & m_axis_req_ready[6]) |
195
+ ((sel == 7) & is_trans & m_axis_req_ready[7]) |
196
+ ((sel == 8) & is_trans & m_axis_req_ready[8]) |
197
+ ((sel == 9) & is_trans & m_axis_req_ready[9]) |
198
+ ((sel == 10) & is_trans & m_axis_req_ready[10]);
199
+
200
+ end // CHNL_DEMUX_11
201
+ else if (CHANNEL_NUM == 10) begin:CHNL_DEMUX_10
202
+
203
+ assign s_axis_req_ready = ((sel == 0) & is_trans & m_axis_req_ready[0]) |
204
+ ((sel == 1) & is_trans & m_axis_req_ready[1]) |
205
+ ((sel == 2) & is_trans & m_axis_req_ready[2]) |
206
+ ((sel == 3) & is_trans & m_axis_req_ready[3]) |
207
+ ((sel == 4) & is_trans & m_axis_req_ready[4]) |
208
+ ((sel == 5) & is_trans & m_axis_req_ready[5]) |
209
+ ((sel == 6) & is_trans & m_axis_req_ready[6]) |
210
+ ((sel == 7) & is_trans & m_axis_req_ready[7]) |
211
+ ((sel == 8) & is_trans & m_axis_req_ready[8]) |
212
+ ((sel == 9) & is_trans & m_axis_req_ready[9]);
213
+
214
+ end // CHNL_DEMUX_10
215
+ else if (CHANNEL_NUM == 9) begin:CHNL_DEMUX_9
216
+
217
+ assign s_axis_req_ready = ((sel == 0) & is_trans & m_axis_req_ready[0]) |
218
+ ((sel == 1) & is_trans & m_axis_req_ready[1]) |
219
+ ((sel == 2) & is_trans & m_axis_req_ready[2]) |
220
+ ((sel == 3) & is_trans & m_axis_req_ready[3]) |
221
+ ((sel == 4) & is_trans & m_axis_req_ready[4]) |
222
+ ((sel == 5) & is_trans & m_axis_req_ready[5]) |
223
+ ((sel == 6) & is_trans & m_axis_req_ready[6]) |
224
+ ((sel == 7) & is_trans & m_axis_req_ready[7]) |
225
+ ((sel == 8) & is_trans & m_axis_req_ready[8]);
226
+
227
+ end // CHNL_DEMUX_9
228
+ else if (CHANNEL_NUM == 8) begin:CHNL_DEMUX_8
229
+
230
+ assign s_axis_req_ready = ((sel == 0) & is_trans & m_axis_req_ready[0]) |
231
+ ((sel == 1) & is_trans & m_axis_req_ready[1]) |
232
+ ((sel == 2) & is_trans & m_axis_req_ready[2]) |
233
+ ((sel == 3) & is_trans & m_axis_req_ready[3]) |
234
+ ((sel == 4) & is_trans & m_axis_req_ready[4]) |
235
+ ((sel == 5) & is_trans & m_axis_req_ready[5]) |
236
+ ((sel == 6) & is_trans & m_axis_req_ready[6]) |
237
+ ((sel == 7) & is_trans & m_axis_req_ready[7]);
238
+
239
+ end // CHNL_DEMUX_8
240
+ else if (CHANNEL_NUM == 7) begin:CHNL_DEMUX_7
241
+
242
+ assign s_axis_req_ready = ((sel == 0) & is_trans & m_axis_req_ready[0]) |
243
+ ((sel == 1) & is_trans & m_axis_req_ready[1]) |
244
+ ((sel == 2) & is_trans & m_axis_req_ready[2]) |
245
+ ((sel == 3) & is_trans & m_axis_req_ready[3]) |
246
+ ((sel == 4) & is_trans & m_axis_req_ready[4]) |
247
+ ((sel == 5) & is_trans & m_axis_req_ready[5]) |
248
+ ((sel == 6) & is_trans & m_axis_req_ready[6]);
249
+
250
+ end // CHNL_DEMUX_7
251
+ else if (CHANNEL_NUM == 6) begin:CHNL_DEMUX_6
252
+
253
+ assign s_axis_req_ready = ((sel == 0) & is_trans & m_axis_req_ready[0]) |
254
+ ((sel == 1) & is_trans & m_axis_req_ready[1]) |
255
+ ((sel == 2) & is_trans & m_axis_req_ready[2]) |
256
+ ((sel == 3) & is_trans & m_axis_req_ready[3]) |
257
+ ((sel == 4) & is_trans & m_axis_req_ready[4]) |
258
+ ((sel == 5) & is_trans & m_axis_req_ready[5]);
259
+
260
+ end // CHNL_DEMUX_6
261
+ else if (CHANNEL_NUM == 5) begin:CHNL_DEMUX_5
262
+
263
+ assign s_axis_req_ready = ((sel == 0) & is_trans & m_axis_req_ready[0]) |
264
+ ((sel == 1) & is_trans & m_axis_req_ready[1]) |
265
+ ((sel == 2) & is_trans & m_axis_req_ready[2]) |
266
+ ((sel == 3) & is_trans & m_axis_req_ready[3]) |
267
+ ((sel == 4) & is_trans & m_axis_req_ready[4]);
268
+
269
+ end // CHNL_DEMUX_5
270
+ else if (CHANNEL_NUM == 4) begin:CHNL_DEMUX_4
271
+
272
+ assign s_axis_req_ready = ((sel == 0) & is_trans & m_axis_req_ready[0]) |
273
+ ((sel == 1) & is_trans & m_axis_req_ready[1]) |
274
+ ((sel == 2) & is_trans & m_axis_req_ready[2]) |
275
+ ((sel == 3) & is_trans & m_axis_req_ready[3]);
276
+
277
+ end // CHNL_DEMUX_4
278
+ else if (CHANNEL_NUM == 3) begin:CHNL_DEMUX_3
279
+
280
+ assign s_axis_req_ready = ((sel == 0) & is_trans & m_axis_req_ready[0]) |
281
+ ((sel == 1) & is_trans & m_axis_req_ready[1]) |
282
+ ((sel == 2) & is_trans & m_axis_req_ready[2]);
283
+
284
+ end // CHNL_DEMUX_3
285
+ else if (CHANNEL_NUM == 2) begin:CHNL_DEMUX_2
286
+
287
+ assign s_axis_req_ready = ((sel == 0) & is_trans & m_axis_req_ready[0]) |
288
+ ((sel == 1) & is_trans & m_axis_req_ready[1]);
289
+
290
+ end // CHNL_DEMUX_2
291
+ endgenerate
292
+ /*
293
+ This is used for different Channel Numbers, the default Number is 4 */
294
+ /* -------Generate block{end}------- */
295
+
296
+ /******************** Stage 2: State Transition **********************/
297
+
298
+ always @(*) begin
299
+ case(cur_state)
300
+ IDLE: begin
301
+ if (nxt_demux_vld) begin
302
+ nxt_state = TRANS;
303
+ end
304
+ else begin
305
+ nxt_state = IDLE;
306
+ end
307
+ end
308
+ TRANS: begin
309
+ if (s_axis_req_last & s_axis_req_valid & s_axis_req_ready & nxt_demux_vld) begin
310
+ nxt_state = TRANS;
311
+ end
312
+ else if (s_axis_req_last & s_axis_req_valid & s_axis_req_ready) begin
313
+ nxt_state = IDLE;
314
+ end
315
+ else begin
316
+ nxt_state = TRANS;
317
+ end
318
+ end
319
+ default: begin
320
+ nxt_state = IDLE;
321
+ end
322
+ endcase
323
+ end
324
+ /******************** Stage 3: Output **********************/
325
+
326
+ /* -------Generate block{begin}------- */
327
+ /* This is used for different Channel Numbers, the default Number is 4
328
+ */
329
+ genvar i;
330
+ generate
331
+ for (i = 0; i < CHANNEL_NUM; i = i + 1) begin:CHNL_DEMUX_ASSIGN
332
+
333
+ assign m_axis_req_valid[(i+1)*1 -1:i*1 ] = ((i == sel) & is_trans) ? s_axis_req_valid : 0;
334
+ assign m_axis_req_last [(i+1)*1 -1:i*1 ] = ((i == sel) & is_trans) ? s_axis_req_last : 0;
335
+ assign m_axis_req_data [(i+1)*`DMA_DATA_W -1:i*`DMA_DATA_W] = ((i == sel) & is_trans) ? s_axis_req_data : 0;
336
+ assign m_axis_req_head [(i+1)*`DMA_HEAD_W -1:i*`DMA_HEAD_W] = ((i == sel) & is_trans) ? s_axis_req_head : 0;
337
+
338
+ end
339
+ endgenerate
340
+ /*
341
+ This is used for different Channel Numbers, the default Number is 4 */
342
+ /* -------Generate block{end}------- */
343
+
344
+
345
+ /* -------{Read Response Distributor FSM}end------- */
346
+
347
+ endmodule
ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/DMA/DMA_Read/np_tag_mgmt.v ADDED
@@ -0,0 +1,337 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ `timescale 1ns / 100ps
2
+ //*************************************************************************
3
+ // > File Name: np_tag_mgmt.v
4
+ // > Author : Kangning
5
+ // > Date : 2022-06-29
6
+ // > Note : np_tag_mgmt, used for tag allocation of non-post request.
7
+ // > V1.1 2022-06-29 : Add tag_chnl field to store
8
+ // > V2.0 2022-11-03 : Add support for multi-channel tag fifo
9
+ //*************************************************************************
10
+
11
+ module np_tag_mgmt #(
12
+
13
+ ) (
14
+ input wire dma_clk , // i, 1
15
+ input wire rst_n , // i, 1
16
+ output reg init_done, // o, 1; assert at the end of initial state
17
+
18
+ /* -------tag request{begin}------- */
19
+ input wire tag_rreq_ready, // i, 1
20
+ input wire tag_rreq_last , // i, 1 ; Indicate the last sub-req for rd req
21
+ input wire [`DW_LEN_WIDTH-1:0] tag_rreq_sz , // i, `DW_LEN_WIDTH ; Request size(in dw unit) of this tag
22
+ input wire [`TAG_MISC -1:0] tag_rreq_misc , // o, `TAG_MISC ; Including addr && dw empty info
23
+ input wire [8 -1:0] tag_rreq_chnl , // i, 8 ; channel number for this request
24
+ output wire [`TAG_NUM_LOG -1:0] tag_rreq_tag , // o, `TAG_NUM_LOG
25
+ output wire tag_rreq_valid, // o, 1
26
+ /* -------tag request{end}------- */
27
+
28
+ /* -------tag release{begin}------- */
29
+ // Note that only one channel is allowed to assert at the same time
30
+ input wire [`DMA_RD_CHNL_NUM * 1 - 1 : 0] tag_rrsp_ready, // i, 1
31
+ output wire [`DMA_RD_CHNL_NUM * 1 - 1 : 0] tag_rrsp_last , // o, 1
32
+ output wire [`DMA_RD_CHNL_NUM * `DW_LEN_WIDTH - 1 : 0] tag_rrsp_sz , // o, `DW_LEN_WIDTH
33
+ output wire [`DMA_RD_CHNL_NUM * `TAG_MISC - 1 : 0] tag_rrsp_misc , // o, `TAG_MISC ; Including addr && dw empty info
34
+ output wire [`DMA_RD_CHNL_NUM * `TAG_NUM_LOG - 1 : 0] tag_rrsp_tag , // o, `TAG_NUM_LOG
35
+ output wire [`DMA_RD_CHNL_NUM * 1 - 1 : 0] tag_rrsp_valid // o, 1
36
+ /* -------tag release{end}------- */
37
+
38
+ `ifdef PCIEI_APB_DBG
39
+ /* -------APB reated signal{begin}------- */
40
+ ,input wire [(`DMA_RD_CHNL_NUM+1)*`SRAM_RW_DATA_W-1:0] rw_data // i, (`DMA_RD_CHNL_NUM+1)*`SRAM_RW_DATA_W
41
+ ,output wire [`TAG_MGMT_SIGNAL_W-1:0] dbg_signal // o, `TAG_MGMT_SIGNAL_W
42
+ /* -------APB reated signal{end}------- */
43
+ `endif
44
+
45
+ `ifdef SIMULATION
46
+ /* | reserved | tag_num | chnl_num | valid |
47
+ * | 255:17 | 16:9 | 8:1 | 0 |
48
+ */
49
+ ,output wire [255:0] debug
50
+ /* ------- Debug interface {end}------- */
51
+ `endif
52
+ );
53
+
54
+ /* --------Debug signal{begin}-------- */
55
+ `ifdef SIMULATION
56
+
57
+ wire [7:0] dbug_tag_num, dbug_tag_chnl;
58
+ wire dbug_tag_valid;
59
+
60
+ `endif
61
+ /* --------Debug signal{end}-------- */
62
+
63
+ reg [`TAG_NUM_LOG-1:0] init_cnt;
64
+
65
+ /* --------Free tag management{begin}-------- */
66
+ wire free_tag_wen ;
67
+ wire [`TAG_NUM_LOG-1:0] free_tag_din ;
68
+ wire free_tag_full ;
69
+ wire free_tag_ren ;
70
+ wire [`TAG_NUM_LOG-1:0] free_tag_dout ;
71
+ wire free_tag_empty;
72
+ /* --------Free tag management{end}-------- */
73
+
74
+ /* --------Free tag management{begin}-------- */
75
+ wire alloced_tag_wen [`DMA_RD_CHNL_NUM-1:0];
76
+ wire [`TAG_NUM_LOG+`DW_LEN_WIDTH+1+`TAG_MISC-1:0] alloced_tag_din [`DMA_RD_CHNL_NUM-1:0];
77
+ wire alloced_tag_full [`DMA_RD_CHNL_NUM-1:0];
78
+ wire alloced_tag_ren [`DMA_RD_CHNL_NUM-1:0];
79
+ wire [`TAG_NUM_LOG+`DW_LEN_WIDTH+1+`TAG_MISC-1:0] alloced_tag_dout [`DMA_RD_CHNL_NUM-1:0];
80
+ wire alloced_tag_empty[`DMA_RD_CHNL_NUM-1:0];
81
+ /* --------Free tag management{end}-------- */
82
+
83
+ /* --------Arbiter logic{begin}-------- */
84
+ wire arb_tag_wen;
85
+ wire [`TAG_NUM_LOG-1:0] arb_tag_din;
86
+ /* --------Arbiter logic{end}-------- */
87
+
88
+ `ifdef PCIEI_APB_DBG
89
+ /* -------APB reated signal{begin}------- */
90
+ wire [1:0] free_rtsel;
91
+ wire [1:0] free_wtsel;
92
+ wire [1:0] free_ptsel;
93
+ wire free_vg ;
94
+ wire free_vs ;
95
+ wire [`DMA_RD_CHNL_NUM*2-1:0] alloced_rtsel;
96
+ wire [`DMA_RD_CHNL_NUM*2-1:0] alloced_wtsel;
97
+ wire [`DMA_RD_CHNL_NUM*2-1:0] alloced_ptsel;
98
+ wire [`DMA_RD_CHNL_NUM*1-1:0] alloced_vg ;
99
+ wire [`DMA_RD_CHNL_NUM*1-1:0] alloced_vs ;
100
+ /* -------APB reated signal{end}------- */
101
+ `endif
102
+
103
+ //---------------------------------------------------------------------------------------------------------------------------
104
+
105
+ `ifdef PCIEI_APB_DBG
106
+ /* -------APB reated signal{begin}------- */
107
+ assign {
108
+ free_rtsel, free_wtsel, free_ptsel, free_vg, free_vs,
109
+ alloced_rtsel, alloced_wtsel, alloced_ptsel, alloced_vg, alloced_vs} = rw_data;
110
+ assign dbg_signal = { // 605
111
+ init_cnt, // 6
112
+ free_tag_wen , free_tag_din , free_tag_full , free_tag_ren , free_tag_dout , free_tag_empty, // 16
113
+
114
+ alloced_tag_wen [0], alloced_tag_wen [1], alloced_tag_wen [2], alloced_tag_wen [3],
115
+ alloced_tag_wen [4], alloced_tag_wen [5], alloced_tag_wen [6], alloced_tag_wen [7], alloced_tag_wen [8],
116
+ alloced_tag_din [0], alloced_tag_din [1], alloced_tag_din [2], alloced_tag_din [3],
117
+ alloced_tag_din [4], alloced_tag_din [5], alloced_tag_din [6], alloced_tag_din [7], alloced_tag_din [8],
118
+ alloced_tag_full [0], alloced_tag_full [1], alloced_tag_full [2], alloced_tag_full [3],
119
+ alloced_tag_full [4], alloced_tag_full [5], alloced_tag_full [6], alloced_tag_full [7], alloced_tag_full [8],
120
+ alloced_tag_ren [0], alloced_tag_ren [1], alloced_tag_ren [2], alloced_tag_ren [3],
121
+ alloced_tag_ren [4], alloced_tag_ren [5], alloced_tag_ren [6], alloced_tag_ren [7], alloced_tag_ren [8],
122
+ alloced_tag_dout [0], alloced_tag_dout [1], alloced_tag_dout [2], alloced_tag_dout [3],
123
+ alloced_tag_dout [4], alloced_tag_dout [5], alloced_tag_dout [6], alloced_tag_dout [7], alloced_tag_dout [8],
124
+ alloced_tag_empty[0], alloced_tag_empty[1], alloced_tag_empty[2], alloced_tag_empty[3],
125
+ alloced_tag_empty[4], alloced_tag_empty[5], alloced_tag_empty[6], alloced_tag_empty[7], alloced_tag_empty[8], // 64 * 9
126
+
127
+ arb_tag_wen, arb_tag_din // 7
128
+ };
129
+ /* -------APB reated signal{end}------- */
130
+ `endif
131
+
132
+ /* --------Debug signal{begin}-------- */
133
+ `ifdef SIMULATION
134
+
135
+ /* | reserved | tag_num | chnl_num | valid |
136
+ * | 255:9 | 8:1 | 8:1 | 1 |
137
+ */
138
+ assign debug = {dbug_tag_num, dbug_tag_chnl, dbug_tag_valid};
139
+
140
+ generate
141
+ if (`DMA_RD_CHNL_NUM == 9) begin:DBUG_TAG_CHNL9
142
+
143
+ assign dbug_tag_chnl = (tag_rrsp_valid[0] & tag_rrsp_ready[0]) ? 8'd0 :
144
+ (tag_rrsp_valid[1] & tag_rrsp_ready[1]) ? 8'd1 :
145
+ (tag_rrsp_valid[2] & tag_rrsp_ready[2]) ? 8'd2 :
146
+ (tag_rrsp_valid[3] & tag_rrsp_ready[3]) ? 8'd3 :
147
+ (tag_rrsp_valid[4] & tag_rrsp_ready[4]) ? 8'd4 :
148
+ (tag_rrsp_valid[5] & tag_rrsp_ready[5]) ? 8'd5 :
149
+ (tag_rrsp_valid[6] & tag_rrsp_ready[6]) ? 8'd6 :
150
+ (tag_rrsp_valid[7] & tag_rrsp_ready[7]) ? 8'd7 :
151
+ (tag_rrsp_valid[8] & tag_rrsp_ready[8]) ? 8'd8 : 8'd0;
152
+
153
+ assign dbug_tag_num = (tag_rrsp_valid[0] & tag_rrsp_ready[0]) ? tag_rrsp_tag[1*`TAG_NUM_LOG-1:0*`TAG_NUM_LOG] :
154
+ (tag_rrsp_valid[1] & tag_rrsp_ready[1]) ? tag_rrsp_tag[2*`TAG_NUM_LOG-1:1*`TAG_NUM_LOG] :
155
+ (tag_rrsp_valid[2] & tag_rrsp_ready[2]) ? tag_rrsp_tag[3*`TAG_NUM_LOG-1:2*`TAG_NUM_LOG] :
156
+ (tag_rrsp_valid[3] & tag_rrsp_ready[3]) ? tag_rrsp_tag[4*`TAG_NUM_LOG-1:3*`TAG_NUM_LOG] :
157
+ (tag_rrsp_valid[4] & tag_rrsp_ready[4]) ? tag_rrsp_tag[5*`TAG_NUM_LOG-1:4*`TAG_NUM_LOG] :
158
+ (tag_rrsp_valid[5] & tag_rrsp_ready[5]) ? tag_rrsp_tag[6*`TAG_NUM_LOG-1:5*`TAG_NUM_LOG] :
159
+ (tag_rrsp_valid[6] & tag_rrsp_ready[6]) ? tag_rrsp_tag[7*`TAG_NUM_LOG-1:6*`TAG_NUM_LOG] :
160
+ (tag_rrsp_valid[7] & tag_rrsp_ready[7]) ? tag_rrsp_tag[8*`TAG_NUM_LOG-1:7*`TAG_NUM_LOG] :
161
+ (tag_rrsp_valid[8] & tag_rrsp_ready[8]) ? tag_rrsp_tag[9*`TAG_NUM_LOG-1:8*`TAG_NUM_LOG] : 8'd0;
162
+ end
163
+ endgenerate
164
+
165
+ assign dbug_tag_valid = |(tag_rrsp_valid & tag_rrsp_ready);
166
+
167
+ `endif
168
+ /* --------Debug signal{end}-------- */
169
+
170
+ /* --------Init logic{begin}-------- */
171
+ always @(posedge dma_clk, negedge rst_n) begin
172
+ if (~rst_n) begin
173
+ init_cnt <= `TD 0;
174
+ end
175
+ else if (init_cnt < `TAG_NUM - 1'd1) begin
176
+ init_cnt <= `TD init_cnt + 1;
177
+ end
178
+ end
179
+
180
+ always @(posedge dma_clk, negedge rst_n) begin
181
+ if (~rst_n) begin
182
+ init_done <= `TD 0;
183
+ end
184
+ else if (init_cnt == `TAG_NUM - 1'd1) begin
185
+ init_done <= `TD 1;
186
+ end
187
+ end
188
+ /* --------Init logic{end}-------- */
189
+
190
+ /* -------Free tag management{begin}------- */
191
+
192
+ assign free_tag_wen = (init_done ? arb_tag_wen : 1'd1) & !free_tag_full;
193
+ assign free_tag_din = init_done ? arb_tag_din : (init_cnt + `TAG_BASE);
194
+
195
+ pcieifc_sync_fifo #(
196
+ .DSIZE ( `TAG_NUM_LOG ), // 6
197
+ .ASIZE ( `TAG_NUM_LOG ) // 6
198
+ ) free_tag_fifo (
199
+
200
+ .clk ( dma_clk ), // i, i
201
+ .rst_n ( rst_n ), // i, i
202
+ .clr ( 1'd0 ), // i, 1
203
+
204
+ .wen ( free_tag_wen ), // i, 1
205
+ .din ( free_tag_din ), // i, `TAG_NUM_LOG
206
+ .full ( free_tag_full ), // o, 1
207
+
208
+ .ren ( free_tag_ren ), // i, 1
209
+ .dout ( free_tag_dout ), // o, `TAG_NUM_LOG
210
+ .empty( free_tag_empty ) // o, 1
211
+
212
+ `ifdef PCIEI_APB_DBG
213
+ ,.rtsel ( free_rtsel ) // i, 2
214
+ ,.wtsel ( free_wtsel ) // i, 2
215
+ ,.ptsel ( free_ptsel ) // i, 2
216
+ ,.vg ( free_vg ) // i, 1
217
+ ,.vs ( free_vs ) // i, 1
218
+ `endif
219
+ );
220
+ assign free_tag_ren = tag_rreq_valid & tag_rreq_ready;
221
+ /* -------Free tag management{end}------- */
222
+
223
+ /* --------Tag rreq logic{begin}-------- */
224
+ assign tag_rreq_valid = !free_tag_empty;
225
+ assign tag_rreq_tag = free_tag_dout;
226
+ /* --------Tag rreq logic{end}-------- */
227
+
228
+ genvar i;
229
+ generate
230
+ for (i = 0; i < `DMA_RD_CHNL_NUM; i = i + 1) begin:TAG_CHNL
231
+
232
+ /* -------Alloced FIFO logic{begin}------- */
233
+ assign alloced_tag_wen[i] = (tag_rreq_chnl == i) & tag_rreq_valid & tag_rreq_ready; // alloced_tag_full never asserted
234
+ assign alloced_tag_din[i] = {tag_rreq_tag, tag_rreq_sz, tag_rreq_last, tag_rreq_misc};
235
+ pcieifc_sync_fifo #(
236
+ .DSIZE ( `TAG_NUM_LOG + `DW_LEN_WIDTH + 1 + `TAG_MISC ), // Stores tag & sz & last & misc. (30)
237
+ .ASIZE ( `TAG_NUM_LOG ) // (6)
238
+ ) alloced_tag_fifo (
239
+
240
+ .clk ( dma_clk ), // i, i
241
+ .rst_n ( rst_n ), // i, i
242
+ .clr ( 1'd0 ), // i, 1
243
+
244
+ .wen ( alloced_tag_wen [i] ), // i, 1
245
+ .din ( alloced_tag_din [i] ), // i, `TAG_NUM_LOG + `DW_LEN_WIDTH + 1
246
+ .full ( alloced_tag_full[i] ), // o, 1
247
+
248
+ .ren ( alloced_tag_ren [i] ), // i, 1
249
+ .dout ( alloced_tag_dout [i] ), // o, `TAG_NUM_LOG + `DW_LEN_WIDTH + 1
250
+ .empty( alloced_tag_empty[i] ) // o, 1
251
+
252
+ `ifdef PCIEI_APB_DBG
253
+ ,.rtsel ( alloced_rtsel[(i+1)*2-1:i*2] ) // i, 2
254
+ ,.wtsel ( alloced_wtsel[(i+1)*2-1:i*2] ) // i, 2
255
+ ,.ptsel ( alloced_ptsel[(i+1)*2-1:i*2] ) // i, 2
256
+ ,.vg ( alloced_vg [i] ) // i, 1
257
+ ,.vs ( alloced_vs [i] ) // i, 1
258
+ `endif
259
+ );
260
+ assign alloced_tag_ren [i] = (tag_rrsp_ready[i] == 1);
261
+ /* -------Alloced FIFO logic{end}------- */
262
+
263
+ /* --------Tag rrsp logic{begin}-------- */
264
+ assign {tag_rrsp_tag [(i+1) * `TAG_NUM_LOG - 1 : i * `TAG_NUM_LOG ],
265
+ tag_rrsp_sz [(i+1) * `DW_LEN_WIDTH - 1 : i * `DW_LEN_WIDTH],
266
+ tag_rrsp_last[(i+1) * 1 - 1 : i * 1 ],
267
+ tag_rrsp_misc[(i+1) * `TAG_MISC - 1 : i * `TAG_MISC ]} = alloced_tag_dout[i];
268
+
269
+ assign tag_rrsp_valid[i] = !alloced_tag_empty[i];
270
+ /* --------Tag rrsp logic{end}-------- */
271
+
272
+ end
273
+ endgenerate
274
+
275
+ /* --------arbiter logic{begin}-------- */
276
+ generate
277
+ if (`DMA_RD_CHNL_NUM == 2) begin:TAG_CHNL2
278
+
279
+ assign arb_tag_din = tag_rrsp_valid[0] & tag_rrsp_ready[0] ? tag_rrsp_tag[1*`TAG_NUM_LOG-1:0*`TAG_NUM_LOG] :
280
+ tag_rrsp_valid[1] & tag_rrsp_ready[1] ? tag_rrsp_tag[2*`TAG_NUM_LOG-1:1*`TAG_NUM_LOG] : 0;
281
+
282
+ assign arb_tag_wen = tag_rrsp_valid[0] & tag_rrsp_ready[0] |
283
+ tag_rrsp_valid[1] & tag_rrsp_ready[1];
284
+
285
+ end
286
+ else if (`DMA_RD_CHNL_NUM == 9) begin:TAG_CHNL9
287
+
288
+ assign arb_tag_din = (tag_rrsp_valid[0] & tag_rrsp_ready[0]) ? tag_rrsp_tag[1*`TAG_NUM_LOG-1:0*`TAG_NUM_LOG] :
289
+ (tag_rrsp_valid[1] & tag_rrsp_ready[1]) ? tag_rrsp_tag[2*`TAG_NUM_LOG-1:1*`TAG_NUM_LOG] :
290
+ (tag_rrsp_valid[2] & tag_rrsp_ready[2]) ? tag_rrsp_tag[3*`TAG_NUM_LOG-1:2*`TAG_NUM_LOG] :
291
+ (tag_rrsp_valid[3] & tag_rrsp_ready[3]) ? tag_rrsp_tag[4*`TAG_NUM_LOG-1:3*`TAG_NUM_LOG] :
292
+ (tag_rrsp_valid[4] & tag_rrsp_ready[4]) ? tag_rrsp_tag[5*`TAG_NUM_LOG-1:4*`TAG_NUM_LOG] :
293
+ (tag_rrsp_valid[5] & tag_rrsp_ready[5]) ? tag_rrsp_tag[6*`TAG_NUM_LOG-1:5*`TAG_NUM_LOG] :
294
+ (tag_rrsp_valid[6] & tag_rrsp_ready[6]) ? tag_rrsp_tag[7*`TAG_NUM_LOG-1:6*`TAG_NUM_LOG] :
295
+ (tag_rrsp_valid[7] & tag_rrsp_ready[7]) ? tag_rrsp_tag[8*`TAG_NUM_LOG-1:7*`TAG_NUM_LOG] :
296
+ (tag_rrsp_valid[8] & tag_rrsp_ready[8]) ? tag_rrsp_tag[9*`TAG_NUM_LOG-1:8*`TAG_NUM_LOG] : 0;
297
+
298
+ assign arb_tag_wen = (tag_rrsp_valid[0] & tag_rrsp_ready[0]) |
299
+ (tag_rrsp_valid[1] & tag_rrsp_ready[1]) |
300
+ (tag_rrsp_valid[2] & tag_rrsp_ready[2]) |
301
+ (tag_rrsp_valid[3] & tag_rrsp_ready[3]) |
302
+ (tag_rrsp_valid[4] & tag_rrsp_ready[4]) |
303
+ (tag_rrsp_valid[5] & tag_rrsp_ready[5]) |
304
+ (tag_rrsp_valid[6] & tag_rrsp_ready[6]) |
305
+ (tag_rrsp_valid[7] & tag_rrsp_ready[7]) |
306
+ (tag_rrsp_valid[8] & tag_rrsp_ready[8]);
307
+
308
+ end
309
+ else if (`DMA_RD_CHNL_NUM == 10) begin:TAG_CHNL10
310
+
311
+ assign arb_tag_din = (tag_rrsp_valid[0] & tag_rrsp_ready[0]) ? tag_rrsp_tag[1*`TAG_NUM_LOG-1:0*`TAG_NUM_LOG] :
312
+ (tag_rrsp_valid[1] & tag_rrsp_ready[1]) ? tag_rrsp_tag[2*`TAG_NUM_LOG-1:1*`TAG_NUM_LOG] :
313
+ (tag_rrsp_valid[2] & tag_rrsp_ready[2]) ? tag_rrsp_tag[3*`TAG_NUM_LOG-1:2*`TAG_NUM_LOG] :
314
+ (tag_rrsp_valid[3] & tag_rrsp_ready[3]) ? tag_rrsp_tag[4*`TAG_NUM_LOG-1:3*`TAG_NUM_LOG] :
315
+ (tag_rrsp_valid[4] & tag_rrsp_ready[4]) ? tag_rrsp_tag[5*`TAG_NUM_LOG-1:4*`TAG_NUM_LOG] :
316
+ (tag_rrsp_valid[5] & tag_rrsp_ready[5]) ? tag_rrsp_tag[6*`TAG_NUM_LOG-1:5*`TAG_NUM_LOG] :
317
+ (tag_rrsp_valid[6] & tag_rrsp_ready[6]) ? tag_rrsp_tag[7*`TAG_NUM_LOG-1:6*`TAG_NUM_LOG] :
318
+ (tag_rrsp_valid[7] & tag_rrsp_ready[7]) ? tag_rrsp_tag[8*`TAG_NUM_LOG-1:7*`TAG_NUM_LOG] :
319
+ (tag_rrsp_valid[8] & tag_rrsp_ready[8]) ? tag_rrsp_tag[9*`TAG_NUM_LOG-1:8*`TAG_NUM_LOG] :
320
+ (tag_rrsp_valid[9] & tag_rrsp_ready[9]) ? tag_rrsp_tag[10*`TAG_NUM_LOG-1:9*`TAG_NUM_LOG] : 0;
321
+
322
+ assign arb_tag_wen = (tag_rrsp_valid[0] & tag_rrsp_ready[0]) |
323
+ (tag_rrsp_valid[1] & tag_rrsp_ready[1]) |
324
+ (tag_rrsp_valid[2] & tag_rrsp_ready[2]) |
325
+ (tag_rrsp_valid[3] & tag_rrsp_ready[3]) |
326
+ (tag_rrsp_valid[4] & tag_rrsp_ready[4]) |
327
+ (tag_rrsp_valid[5] & tag_rrsp_ready[5]) |
328
+ (tag_rrsp_valid[6] & tag_rrsp_ready[6]) |
329
+ (tag_rrsp_valid[7] & tag_rrsp_ready[7]) |
330
+ (tag_rrsp_valid[8] & tag_rrsp_ready[8]) |
331
+ (tag_rrsp_valid[9] & tag_rrsp_ready[9]);
332
+
333
+ end
334
+ endgenerate
335
+ /* --------Tag rrsp logic{end}-------- */
336
+
337
+ endmodule
ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/DMA/DMA_Read/read_req_rsp.v ADDED
@@ -0,0 +1,709 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ `timescale 1ns / 100ps
2
+ //*************************************************************************
3
+ // > File Name: read_req_rsp.v
4
+ // > Author : Kangning
5
+ // > Date : 2020-08-26
6
+ // > Note : read_req_rsp, used to process read request and read response.
7
+ //*************************************************************************
8
+
9
+ //`include "../lib/dma_def_h.v"
10
+
11
+ module read_req_rsp #(
12
+ parameter [8 * `DMA_RD_CHNL_NUM - 1 : 0] CHNL_NUM_TAB = {
13
+ 8'd9,
14
+ 8'd8,
15
+ 8'd7,
16
+ 8'd6,
17
+ 8'd5,
18
+ 8'd4,
19
+ 8'd3,
20
+ 8'd2,
21
+ 8'd1,
22
+ 8'd0
23
+ }
24
+ ) (
25
+ input wire dma_clk ,
26
+ input wire rst_n ,
27
+ output wire init_done, // o, 1
28
+
29
+
30
+ /* ------- Read Request from RDMA{begin}------- */
31
+ /* dma_*_head, valid only in first beat of a packet
32
+ * | Reserved | address | Reserved | Byte length |
33
+ * | 127:96 | 95:32 | 31:13 | 12:0 |
34
+ */
35
+ input wire [`DMA_RD_CHNL_NUM * 1 -1 : 0] dma_rd_req_valid, // i, `DMA_RD_CHNL_NUM * 1
36
+ input wire [`DMA_RD_CHNL_NUM * 1 -1 : 0] dma_rd_req_last , // i, `DMA_RD_CHNL_NUM * 1
37
+ input wire [`DMA_RD_CHNL_NUM * `DMA_DATA_W-1 : 0] dma_rd_req_data , // i, `DMA_RD_CHNL_NUM * `DMA_DATA_W
38
+ input wire [`DMA_RD_CHNL_NUM * `DMA_HEAD_W-1 : 0] dma_rd_req_head , // i, `DMA_RD_CHNL_NUM * `DMA_HEAD_W
39
+ output wire [`DMA_RD_CHNL_NUM * 1 -1 : 0] dma_rd_req_ready, // o, `DMA_RD_CHNL_NUM * 1
40
+ /* ------- Read Request from RDMA{end}------- */
41
+
42
+ /* ------- Read Response to RDMA{begin} ------- */
43
+ /* dma_*_head , valid only in first beat of a packet
44
+ * | Reserved | address | Reserved | Byte length |
45
+ * | 127:96 | 95:32 | 31:13 | 12:0 |
46
+ */
47
+ output wire [`DMA_RD_CHNL_NUM * 1 -1 : 0] dma_rd_rsp_valid, // o, `DMA_RD_CHNL_NUM * 1
48
+ output wire [`DMA_RD_CHNL_NUM * 1 -1 : 0] dma_rd_rsp_last , // o, `DMA_RD_CHNL_NUM * 1
49
+ output wire [`DMA_RD_CHNL_NUM * `DMA_DATA_W-1 : 0] dma_rd_rsp_data , // o, `DMA_RD_CHNL_NUM * `DMA_DATA_W
50
+ output wire [`DMA_RD_CHNL_NUM * `DMA_HEAD_W-1 : 0] dma_rd_rsp_head , // o, `DMA_RD_CHNL_NUM * `DMA_HEAD_W
51
+ input wire [`DMA_RD_CHNL_NUM * 1 -1 : 0] dma_rd_rsp_ready, // i, `DMA_RD_CHNL_NUM * 1
52
+ /* ------- Read Response to RDMA{end} ------- */
53
+
54
+ /* -------axis read request interface{begin}------- */
55
+ /* AXI-Stream read request tuser.
56
+ * Only valid in first beat of a packet
57
+ * | Reserved | REQ_TYPE | Tag | address | Reserved | DW length | first BE | last BE |
58
+ * | 127:108 | 107:104 | 103:96 | 95:32 | 31:19 | 18:8 | 7:4 | 3:0 |
59
+ */
60
+ output wire axis_rd_req_tvalid , // o, 1
61
+ output wire axis_rd_req_tlast , // o, 1
62
+ output wire [`DMA_DATA_W -1:0] axis_rd_req_tdata , // o, `DMA_DATA_W
63
+ output wire [`AXIS_TUSER_W-1:0] axis_rd_req_tuser , // o, `AXIS_TUSER_W
64
+ output wire [`DMA_KEEP_W -1:0] axis_rd_req_tkeep , // o, `DMA_KEEP_W
65
+ input wire axis_rd_req_tready , // i, 1
66
+ /* -------axis read request interface{end}------- */
67
+
68
+ /* -------axis read response interface{begin}------- */
69
+ /* AXI-Stream read response tuser, interact with read response distributor.
70
+ * Only valid in first beat of a packet
71
+ * | Reserved | REQ CPL | Tag | address | Reserved | DW length | first BE | last BE |
72
+ * | 119:105 | 104 | 103:96 | 95:32 | 31:19 | 18:8 | 7:4 | 3:0 |
73
+ */
74
+ input wire axis_rd_rsp_tvalid, // i, 1
75
+ input wire axis_rd_rsp_tlast , // i, 1
76
+ input wire [`DMA_DATA_W -1:0] axis_rd_rsp_tdata , // i, `DMA_DATA_W
77
+ input wire [`AXIS_TUSER_W-1:0] axis_rd_rsp_tuser , // i, `AXIS_TUSER_W
78
+ input wire [`DMA_KEEP_W -1:0] axis_rd_rsp_tkeep , // i, `DMA_KEEP_W
79
+ output wire axis_rd_rsp_tready, // o, 1
80
+ /* -------axis read response interface{end}------- */
81
+
82
+ /* -------PCIe fragment property{begin}------- */
83
+ /* This signal indicates the (max payload size & max read request size) agreed in the communication
84
+ * 3'b000 -- 128 B
85
+ * 3'b001 -- 256 B
86
+ * 3'b010 -- 512 B
87
+ * 3'b011 -- 1024B
88
+ * 3'b100 -- 2048B
89
+ * 3'b101 -- 4096B
90
+ */
91
+ input wire [2:0] max_pyld_sz ,
92
+ input wire [2:0] max_rd_req_sz // max read request size
93
+ /* -------PCIe fragment property{end}------- */
94
+
95
+ `ifdef PCIEI_APB_DBG
96
+ /* -------APB reated signal{begin}------- */
97
+ ,input wire [(2*`DMA_RD_CHNL_NUM+3)*`SRAM_RW_DATA_W-1:0] rw_data // i, (2*`DMA_RD_CHNL_NUM+3)*`SRAM_RW_DATA_W
98
+ ,input wire [31:0] dbg_sel // debug bus select
99
+ ,output wire [31:0] dbg_bus // debug bus data
100
+ /* -------APB reated signal{end}------- */
101
+ `endif
102
+
103
+
104
+ `ifdef SIMULATION
105
+ /* ------- Debug interface {begin}------- */
106
+ /* | reserved | idx | end | out |
107
+ * | 255:CHNL_NUM_LOG+2 | CHNL_NUM_LOG+2-1:2 | 1 | 0 |
108
+ */
109
+ ,output wire [255:0] debug_rd
110
+
111
+ /* | reserved | tag_num | chnl_num | valid |
112
+ * | 255:17 | 16:9 | 8:1 | 0 |
113
+ */
114
+ ,output wire [255:0] debug_tag
115
+ /* ------- Debug interface {end}------- */
116
+ `endif
117
+ );
118
+
119
+ wire init_done_tag_mgmt, init_done_rd_rsp;
120
+
121
+ /* -------Request FIFO relevant{begin}------- */
122
+ wire [`DMA_RD_CHNL_NUM * 1 -1 : 0] st_rd_req_valid;
123
+ wire [`DMA_RD_CHNL_NUM * 1 -1 : 0] st_rd_req_ready;
124
+ wire [`DMA_RD_CHNL_NUM * `DMA_HEAD_W-1 : 0] st_rd_req_head ;
125
+ /* -------Request FIFO relevant{end}------- */
126
+
127
+ /* -------axis read request interface{begin}------- */
128
+ wire [`DMA_RD_CHNL_NUM * 1 -1:0] axis_rd_request_tvalid;
129
+ wire [`DMA_RD_CHNL_NUM * 1 -1:0] axis_rd_request_tlast ;
130
+ wire [`DMA_RD_CHNL_NUM * `DMA_DATA_W -1:0] axis_rd_request_tdata ;
131
+ wire [`DMA_RD_CHNL_NUM * `AXIS_TUSER_W-1:0] axis_rd_request_tuser ;
132
+ wire [`DMA_RD_CHNL_NUM * `DMA_KEEP_W -1:0] axis_rd_request_tkeep ;
133
+ wire [`DMA_RD_CHNL_NUM * 1 -1:0] axis_rd_request_tready;
134
+ /* -------axis read request interface{end}------- */
135
+
136
+ /* -------axis rd req arbiter interface{begin}------- */
137
+ wire [1 -1:0] axis_rd_req_arb_tvalid;
138
+ wire [1 -1:0] axis_rd_req_arb_tlast ;
139
+ wire [`DMA_DATA_W -1:0] axis_rd_req_arb_tdata ;
140
+ wire [`AXIS_TUSER_W-1:0] axis_rd_req_arb_tuser ;
141
+ wire [`DMA_KEEP_W -1:0] axis_rd_req_arb_tkeep ;
142
+ wire [1 -1:0] axis_rd_req_arb_tready;
143
+ /* -------axis rd req arbiter interface{end}------- */
144
+
145
+ /* -------Tag Management relevant{begin}------- */
146
+ wire tag_rreq_ready;
147
+ wire tag_rreq_last ;
148
+ wire [`DW_LEN_WIDTH-1:0] tag_rreq_sz ;
149
+ wire [`TAG_MISC -1:0] tag_rreq_misc ;
150
+ wire [8 -1:0] tag_rreq_chnl ;
151
+ wire [`TAG_NUM_LOG -1:0] tag_rreq_tag ;
152
+ wire tag_rreq_valid;
153
+
154
+ wire [`DMA_RD_CHNL_NUM * 1 - 1 : 0] tag_rrsp_ready;
155
+ wire [`DMA_RD_CHNL_NUM * 1 - 1 : 0] tag_rrsp_last ;
156
+ wire [`DMA_RD_CHNL_NUM * `DW_LEN_WIDTH - 1 : 0] tag_rrsp_sz ;
157
+ wire [`DMA_RD_CHNL_NUM * `TAG_MISC - 1 : 0] tag_rrsp_misc ;
158
+ wire [`DMA_RD_CHNL_NUM * `TAG_NUM_LOG - 1 : 0] tag_rrsp_tag ;
159
+ wire [`DMA_RD_CHNL_NUM * 1 - 1 : 0] tag_rrsp_valid;
160
+ /* -------Tag Management relevant{end}------- */
161
+
162
+ /* ------- Read sub-req response{begin} ------- */
163
+ /* dma_*_head
164
+ * | emit | chnl_num | Reserved | address | Reserved | Byte length |
165
+ * | 127 | 126:120 | 119:96 | 95:32 | 31:13 | 12:0 |
166
+ */
167
+ wire rd_rsp_demux_valid;
168
+ wire rd_rsp_demux_last ;
169
+ wire [`DMA_DATA_W-1:0] rd_rsp_demux_data ;
170
+ wire [`DMA_HEAD_W-1:0] rd_rsp_demux_head ;
171
+ wire rd_rsp_demux_ready;
172
+
173
+ wire st_rd_rsp_demux_valid;
174
+ wire st_rd_rsp_demux_last ;
175
+ wire [`DMA_DATA_W-1:0] st_rd_rsp_demux_data ;
176
+ wire [`DMA_HEAD_W-1:0] st_rd_rsp_demux_head ;
177
+ wire st_rd_rsp_demux_ready;
178
+ /* ------- Read sub-req response{end} ------- */
179
+
180
+ /* ------- Read sub-req response{begin} ------- */
181
+ /* dma_*_head
182
+ * | emit | chnl_num | Reserved | address | Reserved | Byte length |
183
+ * | 127 | 126:120 | 119:96 | 95:32 | 31:13 | 12:0 |
184
+ */
185
+ wire [`DMA_RD_CHNL_NUM * 1 - 1 : 0] rd_rsp_concat_valid; // o, 1
186
+ wire [`DMA_RD_CHNL_NUM * 1 - 1 : 0] rd_rsp_concat_last ; // o, 1
187
+ wire [`DMA_RD_CHNL_NUM * `DMA_DATA_W- 1 : 0] rd_rsp_concat_data ; // o, `DMA_DATA_W
188
+ wire [`DMA_RD_CHNL_NUM * `DMA_HEAD_W- 1 : 0] rd_rsp_concat_head ; // o, `DMA_HEAD_W
189
+ wire [`DMA_RD_CHNL_NUM * 1 - 1 : 0] rd_rsp_concat_ready; // i, 1
190
+
191
+ /* Indicate that the rsp chnl is available.
192
+ * This signal is deasserted when :
193
+ * 1. rsp output chnl signl dma_rd_rsp_ready is deasserted; &&
194
+ * 2. There is (part of) rsp pkt in sub_req_rsp_concat module.
195
+ */
196
+ wire [`DMA_RD_CHNL_NUM * 1 - 1 : 0] is_rsp_chnl_avail;
197
+ /* ------- Read sub-req response{end} ------- */
198
+
199
+ `ifdef PCIEI_APB_DBG
200
+ /* -------APB reated signal{begin}------- */
201
+ wire [(`DMA_RD_CHNL_NUM+1)*`SRAM_RW_DATA_W-1:0] rw_data_tag;
202
+ wire [2*`SRAM_RW_DATA_W -1:0] rw_data_rsp;
203
+ wire [`DMA_RD_CHNL_NUM*`SRAM_RW_DATA_W -1:0] rw_data_concat;
204
+
205
+ wire [32-1:0] dbg_sel_rd_top, dbg_sel_rd_req, dbg_sel_rreq_arb, dbg_sel_tag_req, dbg_sel_tag_mgmt, dbg_sel_rd_rsp,
206
+ dbg_sel_dma_demux, dbg_sel_rsp_concat;
207
+ wire [32-1:0] dbg_bus_rd_top, dbg_bus_rd_req, dbg_bus_rreq_arb, dbg_bus_tag_req, dbg_bus_tag_mgmt, dbg_bus_rd_rsp,
208
+ dbg_bus_dma_demux, dbg_bus_rsp_concat;
209
+
210
+ wire [`RD_TOP_SIGNAL_W-1:0] dbg_signal_rd_top;
211
+ wire [`DMA_RD_CHNL_NUM*`RD_REQ_SIGNAL_W-1:0] dbg_signal_rd_req;
212
+ wire [`RREQ_ARB_SIGNAL_W -1:0] dbg_signal_rreq_arb;
213
+ wire [`TAG_REQ_SIGNAL_W -1:0] dbg_signal_tag_req;
214
+ wire [`TAG_MGMT_SIGNAL_W -1:0] dbg_signal_tag_mgmt;
215
+ wire [`DMA_DEMUX_SIGNAL_W-1:0] dbg_signal_dma_demux;
216
+ wire [`DMA_RD_CHNL_NUM*`RSP_CONCAT_SIGNAL_W-1:0] dbg_signal_rsp_concat;
217
+ /* -------APB reated signal{end}------- */
218
+ `endif
219
+
220
+ //---------------------------------------------------------------------------------------------------------------------------
221
+
222
+ `ifdef PCIEI_APB_DBG
223
+ /* -------APB reated signal{begin}------- */
224
+ assign {rw_data_tag, rw_data_rsp, rw_data_concat} = rw_data;
225
+ assign dbg_bus = (`RD_TOP_DBG_B <= dbg_sel && dbg_sel < `RD_REQ_DBG_B ) ? dbg_bus_rd_top :
226
+ (`RD_REQ_DBG_B <= dbg_sel && dbg_sel < `RREQ_ARB_DBG_B ) ? dbg_bus_rd_req :
227
+ (`RREQ_ARB_DBG_B <= dbg_sel && dbg_sel < `TAG_REQ_DBG_B ) ? dbg_bus_rreq_arb :
228
+ (`TAG_REQ_DBG_B <= dbg_sel && dbg_sel < `TAG_MGMT_DBG_B ) ? dbg_bus_tag_req :
229
+ (`TAG_MGMT_DBG_B <= dbg_sel && dbg_sel < `RD_RSP_DBG_B ) ? dbg_bus_tag_mgmt :
230
+ (`RD_RSP_DBG_B <= dbg_sel && dbg_sel < `DMA_DEMUX_DBG_B ) ? dbg_bus_rd_rsp :
231
+ (`DMA_DEMUX_DBG_B <= dbg_sel && dbg_sel < `RSP_CONCAT_DBG_B ) ? dbg_bus_dma_demux :
232
+ (`RSP_CONCAT_DBG_B <= dbg_sel && dbg_sel < `RD_REQ_RSP_DBG_SIZE) ? dbg_bus_rsp_concat : 32'd0;
233
+
234
+ assign dbg_sel_rd_top = (`RD_TOP_DBG_B <= dbg_sel && dbg_sel < `RD_REQ_DBG_B ) ? (dbg_sel - `RD_TOP_DBG_B ) : 32'd0;
235
+ assign dbg_sel_rd_req = (`RD_REQ_DBG_B <= dbg_sel && dbg_sel < `RREQ_ARB_DBG_B ) ? (dbg_sel - `RD_REQ_DBG_B ) : 32'd0;
236
+ assign dbg_sel_rreq_arb = (`RREQ_ARB_DBG_B <= dbg_sel && dbg_sel < `TAG_REQ_DBG_B ) ? (dbg_sel - `RREQ_ARB_DBG_B ) : 32'd0;
237
+ assign dbg_sel_tag_req = (`TAG_REQ_DBG_B <= dbg_sel && dbg_sel < `TAG_MGMT_DBG_B ) ? (dbg_sel - `TAG_REQ_DBG_B ) : 32'd0;
238
+ assign dbg_sel_tag_mgmt = (`TAG_MGMT_DBG_B <= dbg_sel && dbg_sel < `RD_RSP_DBG_B ) ? (dbg_sel - `TAG_MGMT_DBG_B ) : 32'd0;
239
+ assign dbg_sel_rd_rsp = (`RD_RSP_DBG_B <= dbg_sel && dbg_sel < `DMA_DEMUX_DBG_B ) ? (dbg_sel - `RD_RSP_DBG_B ) : 32'd0;
240
+ assign dbg_sel_dma_demux = (`DMA_DEMUX_DBG_B <= dbg_sel && dbg_sel < `RSP_CONCAT_DBG_B ) ? (dbg_sel - `DMA_DEMUX_DBG_B ) : 32'd0;
241
+ assign dbg_sel_rsp_concat = (`RSP_CONCAT_DBG_B <= dbg_sel && dbg_sel < `RD_REQ_RSP_DBG_SIZE) ? (dbg_sel - `RSP_CONCAT_DBG_B) : 32'd0;
242
+
243
+ // Debug bus for read top
244
+ assign dbg_bus_rd_top = dbg_signal_rd_top >> {dbg_sel_rd_top, 5'd0};
245
+
246
+ // Debug bus for read request
247
+ assign dbg_bus_rd_req = dbg_signal_rd_req >> {dbg_sel_rd_req, 5'd0};
248
+
249
+ // Debug bus for read arbiter
250
+ assign dbg_bus_rreq_arb = dbg_signal_rreq_arb >> {dbg_sel_rreq_arb, 5'd0};
251
+
252
+ // Debug bus for tag request
253
+ assign dbg_bus_tag_req = dbg_signal_tag_req >> {dbg_sel_tag_req, 5'd0};
254
+
255
+ // Debug bus for tag request
256
+ assign dbg_bus_tag_mgmt = dbg_signal_tag_mgmt >> {dbg_sel_tag_mgmt, 5'd0};
257
+
258
+ // Debug bus for tag request
259
+ assign dbg_bus_dma_demux = dbg_signal_dma_demux >> {dbg_sel_dma_demux, 5'd0};
260
+
261
+ // Debug bus for tag request
262
+ assign dbg_bus_rsp_concat = dbg_signal_rsp_concat >> {dbg_sel_rsp_concat, 5'd0};
263
+
264
+ assign dbg_signal_rd_top = { // 9716
265
+ init_done_tag_mgmt, init_done_rd_rsp, // 2
266
+ st_rd_req_valid, st_rd_req_ready, st_rd_req_head , // 1170
267
+ axis_rd_request_tvalid, axis_rd_request_tlast , axis_rd_request_tdata , axis_rd_request_tuser , axis_rd_request_tkeep , axis_rd_request_tready, // 3555
268
+ axis_rd_req_arb_tvalid, axis_rd_req_arb_tlast , axis_rd_req_arb_tdata , axis_rd_req_arb_tuser , axis_rd_req_arb_tkeep , axis_rd_req_arb_tready, // 395
269
+ tag_rreq_ready, tag_rreq_last, tag_rreq_sz, tag_rreq_misc, tag_rreq_chnl, tag_rreq_tag, tag_rreq_valid, // 40
270
+ tag_rrsp_ready, tag_rrsp_last, tag_rrsp_sz, tag_rrsp_misc, tag_rrsp_tag, tag_rrsp_valid, // 288
271
+ rd_rsp_demux_valid, rd_rsp_demux_last , rd_rsp_demux_data , rd_rsp_demux_head , rd_rsp_demux_ready, // 387
272
+ st_rd_rsp_demux_valid, st_rd_rsp_demux_last , st_rd_rsp_demux_data , st_rd_rsp_demux_head , st_rd_rsp_demux_ready, // 387
273
+ rd_rsp_concat_valid, rd_rsp_concat_last , rd_rsp_concat_data , rd_rsp_concat_head , rd_rsp_concat_ready, // 3483
274
+ is_rsp_chnl_avail // 9
275
+ };
276
+ /* -------APB reated signal{end}------- */
277
+ `endif
278
+
279
+ assign init_done = init_done_tag_mgmt & init_done_rd_rsp;
280
+
281
+ genvar i;
282
+ generate
283
+ for (i = 0; i < `DMA_RD_CHNL_NUM; i = i + 1) begin:DMA_RD_CHNL
284
+
285
+ /* -------Read Request FIFO{begin}------- */
286
+ st_reg #(
287
+ .TUSER_WIDTH ( 1 ),
288
+ .TDATA_WIDTH ( `DMA_HEAD_W )
289
+ ) st_rd_req (
290
+ .clk ( dma_clk ), // i, 1
291
+ .rst_n ( rst_n ), // i, 1
292
+
293
+ /* -------input axis-like interface{begin}------- */
294
+ .axis_tvalid ( dma_rd_req_valid[i] ), // i, 1
295
+ .axis_tlast ( 1'd0 ), // i, 1
296
+ .axis_tuser ( 1'd0 ), // i, TUSER_WIDTH
297
+ .axis_tdata ( {CHNL_NUM_TAB[(i+1)*8-1 : i*8], dma_rd_req_head[(i+1)*`DMA_HEAD_W-1-8 : i*`DMA_HEAD_W]} ), // i, TDATA_WIDTH
298
+ .axis_tready ( dma_rd_req_ready[i] ), // o, 1
299
+ /* -------input axis-like interface{end}------- */
300
+
301
+ /* -------output in_reg inteface{begin}------- */
302
+ .axis_reg_tvalid ( st_rd_req_valid[i] ), // o, 1
303
+ .axis_reg_tlast ( ), // o, 1
304
+ .axis_reg_tuser ( ), // o, TUSER_WIDTH
305
+ .axis_reg_tdata ( st_rd_req_head[(i+1)*`DMA_HEAD_W-1 : i*`DMA_HEAD_W] ), // o, TDATA_WIDTH
306
+ .axis_reg_tready ( st_rd_req_ready[i] ) // i, 1
307
+ /* -------output in_reg inteface{end}------- */
308
+ );
309
+ /* -------Read Request FIFO{end}------- */
310
+
311
+ /* -------Read request handling(align && split req){begin}-------- */
312
+ read_request #(
313
+
314
+ ) read_request (
315
+ .dma_clk ( dma_clk ), // i, 1
316
+ .rst_n ( rst_n ), // i, 1
317
+
318
+ /* ------- Read Request input{begin} ------- */
319
+ /* dma_*_head (interact with RDMA modules), valid only in first beat of a packet
320
+ * | chnl_num | Reserved | address | Reserved | Byte length |
321
+ * | 127:120 | 119:96 | 95:32 | 31:13 | 12:0 |
322
+ */
323
+ .rd_req_valid ( st_rd_req_valid[i] ), // i, 1
324
+ .rd_req_head ( st_rd_req_head[(i+1)*`DMA_HEAD_W-1 : i*`DMA_HEAD_W] ), // i, `DMA_HEAD_W
325
+ .rd_req_ready ( st_rd_req_ready[i] ), // o, 1
326
+ /* ------- Read Request input{end} ------- */
327
+
328
+ /* -------axis read request interface{begin}------- */
329
+ /* AXI-Stream read request tuser, every read request contains only one beat.
330
+ * | chnl_num |last_sub_req | Reserved | REQ_TYPE |Tag(inv)| address | Reserved | DW length | first BE | last BE |
331
+ * | 127:120 | 119 | 118:108 | 107:104 | 103:96 | 95:32 | 31:19 | 18:8 | 7:4 | 3:0 |
332
+ */
333
+ .axis_rd_request_tvalid ( axis_rd_request_tvalid[(i+1) * 1 - 1 : i * 1 ] ), // o, 1
334
+ .axis_rd_request_tlast ( axis_rd_request_tlast [(i+1) * 1 - 1 : i * 1 ] ), // o, 1
335
+ .axis_rd_request_tdata ( axis_rd_request_tdata [(i+1) * `DMA_DATA_W - 1 : i * `DMA_DATA_W ] ), // o, `DMA_DATA_W
336
+ .axis_rd_request_tuser ( axis_rd_request_tuser [(i+1) * `AXIS_TUSER_W - 1 : i * `AXIS_TUSER_W] ), // o, `AXIS_TUSER_W
337
+ .axis_rd_request_tkeep ( axis_rd_request_tkeep [(i+1) * `DMA_KEEP_W - 1 : i * `DMA_KEEP_W ] ), // o, `DMA_KEEP_W
338
+ .axis_rd_request_tready ( axis_rd_request_tready[(i+1) * 1 - 1 : i * 1 ] ), // i, 1
339
+ /* -------axis read request interface{end}------- */
340
+
341
+ /* --------read request blocking detection{begin}-------- */
342
+ .chnl_avail ( dma_rd_rsp_ready[i] ), // i, 1
343
+ .chnl_valid ( tag_rrsp_valid [i] ), // i, 1
344
+ /* --------read request blocking detection{end}-------- */
345
+
346
+ /* -------PCIe fragment property{begin}------- */
347
+ /* This signal indicates the (max payload size & max read request size) agreed in the communication
348
+ * 3'b000 -- 128 B
349
+ * 3'b001 -- 256 B
350
+ * 3'b010 -- 512 B
351
+ * 3'b011 -- 1024B
352
+ * 3'b100 -- 2048B
353
+ * 3'b101 -- 4096B
354
+ */
355
+ .max_pyld_sz ( max_pyld_sz ), // i, 3
356
+ .max_rd_req_sz ( max_rd_req_sz ) // i, 3
357
+ /* -------PCIe fragment property{end}------- */
358
+
359
+ `ifdef PCIEI_APB_DBG
360
+ /* -------APB reated signal{begin}------- */
361
+ ,.dbg_signal ( dbg_signal_rd_req[(i+1)*`RD_REQ_SIGNAL_W-1:i*`RD_REQ_SIGNAL_W] ) // o, `RD_REQ_SIGNAL_W
362
+ /* -------APB reated signal{end}------- */
363
+ `endif
364
+ );
365
+ /* -------Read request handling(align && split req){end}-------- */
366
+
367
+ end
368
+ endgenerate
369
+
370
+ req_arbiter #(
371
+ .CHNL_NUM_LOG ( `DMA_RD_CHNL_NUM_LOG ),
372
+ .CHANNEL_NUM ( `DMA_RD_CHNL_NUM ) // number of slave signals to arbit
373
+ ) rd_req_arbiter (
374
+
375
+ .dma_clk ( dma_clk ), // i, 1
376
+ .rst_n ( rst_n ), // i, 1
377
+
378
+ /* -------Slave AXIS Interface(Connect to Read Request Module){begin}------- */
379
+ /* AXI-Stream read request tuser, every read request contains only one beat.
380
+ * | chnl_num |last_sub_req | Reserved | REQ_TYPE |Tag(inv)| address | Reserved | DW length | first BE | last BE |
381
+ * | 127:120 | 119 | 118:108 | 107:104 | 103:96 | 95:32 | 31:19 | 18:8 | 7:4 | 3:0 |
382
+ */
383
+ .s_axis_req_tvalid ( axis_rd_request_tvalid ), // i, CHANNEL_NUM * 1
384
+ .s_axis_req_tlast ( axis_rd_request_tlast ), // i, CHANNEL_NUM * 1
385
+ .s_axis_req_tdata ( axis_rd_request_tdata ), // i, CHANNEL_NUM * `DMA_DATA_W
386
+ .s_axis_req_tuser ( axis_rd_request_tuser ), // i, CHANNEL_NUM * `AXIS_TUSER_W ;The field contents are different from dma_*_head interface
387
+ .s_axis_req_tkeep ( axis_rd_request_tkeep ), // i, CHANNEL_NUM * `DMA_KEEP_W
388
+ .s_axis_req_tready ( axis_rd_request_tready ), // o, CHANNEL_NUM * 1
389
+ /* -------Slave AXIS Interface(Connect to Read Request Module){end}------- */
390
+
391
+
392
+ /* ------- Master AXIS Interface(Connect to tag_alloc module){begin} ------- */
393
+ /* AXI-Stream read request tuser, every read request contains only one beat.
394
+ * | chnl_num |last_sub_req | Reserved | REQ_TYPE |Tag(inv)| address | Reserved | DW length | first BE | last BE |
395
+ * | 127:120 | 119 | 118:108 | 107:104 | 103:96 | 95:32 | 31:19 | 18:8 | 7:4 | 3:0 |
396
+ */
397
+ .m_axis_req_tvalid ( axis_rd_req_arb_tvalid ), // o, 1
398
+ .m_axis_req_tlast ( axis_rd_req_arb_tlast ), // o, 1
399
+ .m_axis_req_tdata ( axis_rd_req_arb_tdata ), // o, `DMA_DATA_W
400
+ .m_axis_req_tuser ( axis_rd_req_arb_tuser ), // o, `AXIS_TUSER_W ;The field contents are different from dma_*_tuser interface
401
+ .m_axis_req_tkeep ( axis_rd_req_arb_tkeep ), // o, `DMA_KEEP_W
402
+ .m_axis_req_tready ( axis_rd_req_arb_tready ) // i, 1
403
+ /* ------- Master AXIS Interface(Connect to tag_alloc module){end} ------- */
404
+
405
+ `ifdef PCIEI_APB_DBG
406
+ /* -------APB reated signal{begin}------- */
407
+ ,.dbg_signal ( dbg_signal_rreq_arb ) // o, `RREQ_ARB_SIGNAL_W
408
+ /* -------APB reated signal{end}------- */
409
+ `endif
410
+
411
+ `ifdef SIMULATION
412
+ /* ------- Debug interface {begin}------- */
413
+ /* | reserved | idx | end | out |
414
+ * | 255:CHNL_NUM_LOG+2 | CHNL_NUM_LOG+2-1:2 | 1 | 0 |
415
+ */
416
+ ,.debug ( debug_rd )
417
+ /* ------- Debug interface {end}------- */
418
+ `endif
419
+ );
420
+
421
+ tag_request #(
422
+
423
+ ) tag_request (
424
+ .dma_clk ( dma_clk ), // i, 1
425
+ .rst_n ( rst_n ), // i, 1
426
+
427
+ /* ------- Connect to rd_req_arbiter module{begin} ------- */
428
+ /* AXI-Stream read request tuser, every read request contains only one beat.
429
+ * | chnl_num |last_sub_req | Reserved | REQ_TYPE |Tag(inv)| address | Reserved | DW length | first BE | last BE |
430
+ * | 127:120 | 119 | 118:108 | 107:104 | 103:96 | 95:32 | 31:19 | 18:8 | 7:4 | 3:0 |
431
+ */
432
+ .axis_rreq_tvalid ( axis_rd_req_arb_tvalid ), // i, 1
433
+ .axis_rreq_tlast ( axis_rd_req_arb_tlast ), // i, 1
434
+ .axis_rreq_tdata ( axis_rd_req_arb_tdata ), // i, `DMA_DATA_W
435
+ .axis_rreq_tuser ( axis_rd_req_arb_tuser ), // i, `AXIS_TUSER_W ;The field contents are different from dma_*_tuser interface
436
+ .axis_rreq_tkeep ( axis_rd_req_arb_tkeep ), // i, `DMA_KEEP_W
437
+ .axis_rreq_tready ( axis_rd_req_arb_tready ), // o, 1
438
+ /* ------- Connect to rd_req_arbiter module{end} ------- */
439
+
440
+ /* -------tag request{begin}------- */
441
+ .tag_rreq_ready ( tag_rreq_ready ), // o, 1
442
+ .tag_rreq_last ( tag_rreq_last ), // o, 1 ; Indicate the last sub-req for rd req
443
+ .tag_rreq_sz ( tag_rreq_sz ), // o, `DW_LEN_WIDTH ; Request size(in dw unit) of this tag
444
+ .tag_rreq_misc ( tag_rreq_misc ), // o, `TAG_MISC ; Including addr && dw empty info
445
+ .tag_rreq_chnl ( tag_rreq_chnl ), // o, 8 ; channel number for this request
446
+ .tag_rreq_tag ( tag_rreq_tag ), // i, `TAG_NUM_LOG
447
+ .tag_rreq_valid ( tag_rreq_valid ), // i, 1
448
+ /* -------tag request{end}------- */
449
+
450
+ /* -------axis read request interface{begin}------- */
451
+ /* AXI-Stream read request tuser, interact with read request arbiter.
452
+ * Only valid in first beat of a packet
453
+ * | Reserved | REQ_TYPE | Tag | address | Reserved | DW length | first BE | last BE |
454
+ * | 127:108 | 107:104 | 103:96 | 95:32 | 31:19 | 18:8 | 7:4 | 3:0 |
455
+ */
456
+ .axis_rreq_tag_tvalid ( axis_rd_req_tvalid ), // o, 1
457
+ .axis_rreq_tag_tlast ( axis_rd_req_tlast ), // o, 1
458
+ .axis_rreq_tag_tdata ( axis_rd_req_tdata ), // o, `DMA_DATA_W
459
+ .axis_rreq_tag_tuser ( axis_rd_req_tuser ), // o, `AXIS_TUSER_W
460
+ .axis_rreq_tag_tkeep ( axis_rd_req_tkeep ), // o, `DMA_KEEP_W
461
+ .axis_rreq_tag_tready ( axis_rd_req_tready ) // i, 1
462
+ /* -------axis read request interface{end}------- */
463
+
464
+ `ifdef PCIEI_APB_DBG
465
+ /* -------APB reated signal{begin}------- */
466
+ ,.dbg_signal ( dbg_signal_tag_req ) // o, `TAG_REQ_SIGNAL_W
467
+ /* -------APB reated signal{end}------- */
468
+ `endif
469
+ );
470
+
471
+ np_tag_mgmt #(
472
+
473
+ ) np_tag_mgmt (
474
+
475
+ .dma_clk ( dma_clk ), // i, 1
476
+ .rst_n ( rst_n ), // i, 1
477
+ .init_done ( init_done_tag_mgmt ), // o, 1
478
+
479
+ /* -------tag request{begin}------- */
480
+ .tag_rreq_ready ( tag_rreq_ready ), // i, 1
481
+ .tag_rreq_last ( tag_rreq_last ), // i, 1 ; Indicate the last sub-req for rd req
482
+ .tag_rreq_sz ( tag_rreq_sz ), // i, `DW_LEN_WIDTH ; Request size(in dw unit) of this tag
483
+ .tag_rreq_misc ( tag_rreq_misc ), // i, `TAG_MISC ; Including addr && dw empty info
484
+ .tag_rreq_chnl ( tag_rreq_chnl ), // i, 8 ; channel number for this request
485
+ .tag_rreq_tag ( tag_rreq_tag ), // o, `TAG_NUM_LOG
486
+ .tag_rreq_valid ( tag_rreq_valid ), // o, 1
487
+ /* -------tag request{end}------- */
488
+
489
+ /* -------tag release{begin}------- */
490
+ // Note that only one channel is allowed to assert at the same time
491
+ .tag_rrsp_ready ( tag_rrsp_ready ), // i, `DMA_RD_CHNL_NUM * 1
492
+ .tag_rrsp_last ( tag_rrsp_last ), // o, `DMA_RD_CHNL_NUM * 1
493
+ .tag_rrsp_sz ( tag_rrsp_sz ), // o, `DMA_RD_CHNL_NUM * `DW_LEN_WIDTH
494
+ .tag_rrsp_misc ( tag_rrsp_misc ), // o, `DMA_RD_CHNL_NUM * `TAG_MISC ; Including addr && dw empty info
495
+ .tag_rrsp_tag ( tag_rrsp_tag ), // o, `DMA_RD_CHNL_NUM * `TAG_NUM_LOG
496
+ .tag_rrsp_valid ( tag_rrsp_valid ) // o, `DMA_RD_CHNL_NUM * 1
497
+ /* -------tag release{end}------- */
498
+
499
+ `ifdef PCIEI_APB_DBG
500
+ /* -------APB reated signal{begin}------- */
501
+ ,.rw_data ( rw_data_tag ) // i, (`DMA_RD_CHNL_NUM+1)*`SRAM_RW_DATA_W
502
+ ,.dbg_signal ( dbg_signal_tag_mgmt ) // o, `TAG_MGMT_SIGNAL_W
503
+ /* -------APB reated signal{end}------- */
504
+ `endif
505
+
506
+ `ifdef SIMULATION
507
+ /* ------- Debug interface {begin}------- */
508
+ /* | reserved | tag_num | chnl_num | valid |
509
+ * | 255:17 | 16:9 | 8:1 | 0 |
510
+ */
511
+ ,.debug ( debug_tag )
512
+ /* ------- Debug interface {end}------- */
513
+ `endif
514
+ );
515
+
516
+ read_response #(
517
+
518
+ ) read_response (
519
+
520
+ .dma_clk ( dma_clk ), // i, 1
521
+ .rst_n ( rst_n ), // i, 1
522
+ .init_done ( init_done_rd_rsp ), // o, 1
523
+
524
+ /* -------axis read response interface{begin}------- */
525
+ /* AXI-Stream read response tuser, interact with read response distributor.
526
+ * Only valid in first beat of a packet
527
+ * | Reserved | REQ CPL | Tag | address | Reserved | DW length | first BE | last BE |
528
+ * | 119:105 | 104 | 103:96 | 95:32 | 31:19 | 18:8 | 7:4 | 3:0 |
529
+ */
530
+ .axis_rd_rsp_tvalid ( axis_rd_rsp_tvalid ), // i, 1
531
+ .axis_rd_rsp_tlast ( axis_rd_rsp_tlast ), // i, 1
532
+ .axis_rd_rsp_tdata ( axis_rd_rsp_tdata ), // i, `DMA_DATA_W
533
+ .axis_rd_rsp_tuser ( axis_rd_rsp_tuser ), // i, `AXIS_TUSER_W
534
+ .axis_rd_rsp_tkeep ( axis_rd_rsp_tkeep ), // i, `DMA_KEEP_W
535
+ .axis_rd_rsp_tready ( axis_rd_rsp_tready ), // o, 1
536
+ /* -------axis read response interface{end}------- */
537
+
538
+ /* -------tag release{begin}------- */
539
+ // Note that only one channel is allowed to assert at the same time
540
+ .tag_rrsp_ready ( tag_rrsp_ready ), // o, `DMA_RD_CHNL_NUM * 1
541
+ .tag_rrsp_last ( tag_rrsp_last ), // i, `DMA_RD_CHNL_NUM * 1
542
+ .tag_rrsp_sz ( tag_rrsp_sz ), // i, `DMA_RD_CHNL_NUM * `DW_LEN_WIDTH
543
+ .tag_rrsp_misc ( tag_rrsp_misc ), // i, `DMA_RD_CHNL_NUM * `TAG_MISC ; Including addr && dw empty info
544
+ .tag_rrsp_tag ( tag_rrsp_tag ), // i, `DMA_RD_CHNL_NUM * `TAG_NUM_LOG
545
+ .tag_rrsp_valid ( tag_rrsp_valid ), // i, `DMA_RD_CHNL_NUM * 1
546
+ /* -------tag release{end}------- */
547
+
548
+ /* ------- Read Response to RDMA{begin} ------- */
549
+ /* dma_*_head
550
+ * | emit | chnl_num | Reserved | address | Reserved | Byte length |
551
+ * | 127 | 126:120 | 119:96 | 95:32 | 31:13 | 12:0 |
552
+ */
553
+ .sub_req_rsp_valid ( rd_rsp_demux_valid ), // o, 1
554
+ .sub_req_rsp_last ( rd_rsp_demux_last ), // o, 1
555
+ .sub_req_rsp_head ( rd_rsp_demux_head ), // o, `DMA_HEAD_W
556
+ .sub_req_rsp_data ( rd_rsp_demux_data ), // o, `DMA_DATA_W
557
+ .sub_req_rsp_ready ( rd_rsp_demux_ready ), // i, 1
558
+ /* ------- Read Response to RDMA{end} ------- */
559
+
560
+ /* --------chnl_stall{begin}-------- */
561
+ /* Indicate that the rsp chnl is available.
562
+ * This signal is deasserted when :
563
+ * 1. rsp output chnl signl dma_rd_rsp_ready is deasserted; &&
564
+ * 2. There is (part of) rsp pkt in sub_req_rsp_concat module.
565
+ * In this way,
566
+ */
567
+ .chnl_avail ( is_rsp_chnl_avail ) // i, `DMA_RD_CHNL_NUM;
568
+ /* --------chnl_stall{end}-------- */
569
+
570
+ `ifdef PCIEI_APB_DBG
571
+ /* -------APB reated signal{begin}------- */
572
+ ,.rw_data ( rw_data_rsp ) // i, `SRAM_RW_DATA_W*2
573
+ ,.dbg_sel ( dbg_sel_rd_rsp ) // i, 32
574
+ ,.dbg_bus ( dbg_bus_rd_rsp ) // o, 32
575
+ /* -------APB reated signal{end}------- */
576
+ `endif
577
+ );
578
+
579
+ /* -------output reg{begin}------- */
580
+ st_reg #(
581
+ .TUSER_WIDTH ( `DMA_HEAD_W ),
582
+ .TDATA_WIDTH ( `DMA_DATA_W ),
583
+ .MODE( 1 )
584
+ ) out_st_reg (
585
+ .clk ( dma_clk ), // i, 1
586
+ .rst_n ( rst_n ), // i, 1
587
+
588
+ /* -------input axis-like interface{begin}------- */
589
+ .axis_tvalid ( rd_rsp_demux_valid ), // i, 1
590
+ .axis_tlast ( rd_rsp_demux_last ), // i, 1
591
+ .axis_tuser ( rd_rsp_demux_head ), // i, TUSER_WIDTH
592
+ .axis_tdata ( rd_rsp_demux_data ), // i, TDATA_WIDTH
593
+ .axis_tready ( rd_rsp_demux_ready ), // o, 1
594
+ /* -------input axis-like interface{end}------- */
595
+
596
+ /* -------output in_reg inteface{begin}------- */
597
+ .axis_reg_tvalid ( st_rd_rsp_demux_valid ), // o, 1
598
+ .axis_reg_tlast ( st_rd_rsp_demux_last ), // o, 1
599
+ .axis_reg_tuser ( st_rd_rsp_demux_head ), // o, TUSER_WIDTH
600
+ .axis_reg_tdata ( st_rd_rsp_demux_data ), // o, TDATA_WIDTH
601
+ .axis_reg_tready ( st_rd_rsp_demux_ready ) // i, 1
602
+ /* -------output in_reg inteface{end}------- */
603
+ );
604
+ /* -------output reg{end}------- */
605
+
606
+ dma_demux #(
607
+ .CHANNEL_NUM ( `DMA_RD_CHNL_NUM )
608
+ ) dma_demux (
609
+ .clk ( dma_clk ), // i, 1
610
+ .rst_n ( rst_n ), // i, 1
611
+
612
+ .nxt_demux_vld ( rd_rsp_demux_valid ), // i, 1
613
+ .nxt_demux_sel ( {1'd0, rd_rsp_demux_head[126:120]} ), // i, 8
614
+
615
+ /* --------DMA Write Request interface{begin}-------- */
616
+ /* dma_*_head
617
+ * | emit | chnl_num | Reserved | address | Reserved | Byte length |
618
+ * | 127 | 126:120 | 119:96 | 95:32 | 31:13 | 12:0 |
619
+ */
620
+ .s_axis_req_valid ( st_rd_rsp_demux_valid ), // i, 1
621
+ .s_axis_req_last ( st_rd_rsp_demux_last ), // i, 1
622
+ .s_axis_req_head ( st_rd_rsp_demux_head ), // i, `DMA_HEAD_W
623
+ .s_axis_req_data ( st_rd_rsp_demux_data ), // i, `DMA_DATA_W
624
+ .s_axis_req_ready ( st_rd_rsp_demux_ready ), // o, 1
625
+
626
+ /* dma_*_head
627
+ * | emit | chnl_num | Reserved | address | Reserved | Byte length |
628
+ * | 127 | 126:120 | 119:96 | 95:32 | 31:13 | 12:0 |
629
+ */
630
+ .m_axis_req_valid ( rd_rsp_concat_valid ), // o, CHANNEL_NUM * 1
631
+ .m_axis_req_last ( rd_rsp_concat_last ), // o, CHANNEL_NUM * 1
632
+ .m_axis_req_head ( rd_rsp_concat_head ), // o, CHANNEL_NUM * `DMA_HEAD_W
633
+ .m_axis_req_data ( rd_rsp_concat_data ), // o, CHANNEL_NUM * `DMA_DATA_W
634
+ .m_axis_req_ready ( rd_rsp_concat_ready ) // i, CHANNEL_NUM * 1
635
+ /* --------DMA Write Request interface{end}-------- */
636
+
637
+ `ifdef PCIEI_APB_DBG
638
+ /* -------APB reated signal{begin}------- */
639
+ ,.dbg_signal ( dbg_signal_dma_demux ) // o, `DMA_DEMUX_SIGNAL_W
640
+ /* -------APB reated signal{end}------- */
641
+ `endif
642
+ );
643
+
644
+ generate
645
+ for (i = 0; i < `DMA_RD_CHNL_NUM; i = i + 1) begin:SUB_REQ_CONCAT
646
+
647
+ /* -------Sub-req rsp concat{begin}------- */
648
+ sub_req_rsp_concat #(
649
+
650
+ ) sub_req_rsp_concat (
651
+ .dma_clk ( dma_clk ), // i, 1
652
+ .rst_n ( rst_n ), // i, 1
653
+
654
+ /* -------response emission{begin}------- */
655
+ .emit ( rd_rsp_concat_head[(i + 1) * `DMA_HEAD_W - 1 : i * `DMA_HEAD_W + `DMA_HEAD_W - 1] ), // i, 1 ; high active
656
+ /* -------response emission{end}------- */
657
+
658
+ /* ------- Read Response to RDMA{begin} ------- */
659
+ /* dma_*_head
660
+ * | emit | chnl_num | Reserved | address | Reserved | Byte length |
661
+ * | 127 | 126:120 | 119:96 | 95:32 | 31:13 | 12:0 |
662
+ */
663
+ .rd_sub_req_rsp_valid ( rd_rsp_concat_valid[(i + 1) * 1 - 1 : i * 1 ] ), // i, 1
664
+ .rd_sub_req_rsp_last ( rd_rsp_concat_last [(i + 1) * 1 - 1 : i * 1 ] ), // i, 1
665
+ .rd_sub_req_rsp_head ( rd_rsp_concat_head [(i + 1) * `DMA_HEAD_W - 1 : i * `DMA_HEAD_W] ), // i, `DMA_HEAD_W
666
+ .rd_sub_req_rsp_data ( rd_rsp_concat_data [(i + 1) * `DMA_DATA_W - 1 : i * `DMA_DATA_W] ), // i, `DMA_DATA_W
667
+ .rd_sub_req_rsp_ready ( rd_rsp_concat_ready[(i + 1) * 1 - 1 : i * 1 ] ), // o, 1
668
+
669
+ .is_avail ( is_rsp_chnl_avail[(i + 1) * 1 - 1 : i * 1 ] ), // o, 1
670
+ /* ------- Read Response to RDMA{end} ------- */
671
+
672
+ /* ------- Read Response to RDMA{begin} ------- */
673
+ /* *_head
674
+ * | Reserved | address | Reserved | Byte length |
675
+ * | 127:96 | 95:32 | 31:13 | 12:0 |
676
+ */
677
+ .rd_rsp_valid ( dma_rd_rsp_valid [(i + 1) * 1 - 1 : i * 1 ] ), // o, 1
678
+ .rd_rsp_last ( dma_rd_rsp_last [(i + 1) * 1 - 1 : i * 1 ] ), // o, 1
679
+ .rd_rsp_head ( dma_rd_rsp_head [(i + 1) * `DMA_HEAD_W - 1 : i * `DMA_HEAD_W] ), // o, `DMA_HEAD_W
680
+ .rd_rsp_data ( dma_rd_rsp_data [(i + 1) * `DMA_DATA_W - 1 : i * `DMA_DATA_W] ), // o, `DMA_DATA_W
681
+ .rd_rsp_ready ( dma_rd_rsp_ready [(i + 1) * 1 - 1 : i * 1 ] ), // i, 1
682
+ /* ------- Read Response to RDMA{end} ------- */
683
+
684
+ /* -------PCIe fragment property{begin}------- */
685
+ /* This signal indicates the (max payload size & max read request size) agreed in the communication
686
+ * 3'b000 -- 128 B
687
+ * 3'b001 -- 256 B
688
+ * 3'b010 -- 512 B
689
+ * 3'b011 -- 1024B
690
+ * 3'b100 -- 2048B
691
+ * 3'b101 -- 4096B
692
+ */
693
+ .max_pyld_sz ( max_pyld_sz ), // i, 3
694
+ .max_rd_req_sz ( max_rd_req_sz ) // i, 3
695
+ /* -------PCIe fragment property{end}------- */
696
+
697
+ `ifdef PCIEI_APB_DBG
698
+ /* -------APB reated signal{begin}------- */
699
+ ,.rw_data ( rw_data_concat[(i+1)*`SRAM_RW_DATA_W-1:i*`SRAM_RW_DATA_W] ) // i, `SRAM_RW_DATA_W
700
+ ,.dbg_signal ( dbg_signal_rsp_concat[(i+1)*`RSP_CONCAT_SIGNAL_W-1:i*`RSP_CONCAT_SIGNAL_W] ) // o, `RSP_CONCAT_SIGNAL_W
701
+ /* -------APB reated signal{end}------- */
702
+ `endif
703
+ );
704
+ /* -------Sub-req rsp concat{end}------- */
705
+
706
+ end
707
+ endgenerate
708
+
709
+ endmodule
ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/DMA/DMA_Read/read_request.v ADDED
@@ -0,0 +1,306 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ `timescale 1ns / 100ps
2
+ //*************************************************************************
3
+ // > File Name: read_request.v
4
+ // > Author : Kangning
5
+ // > Date : 2022-06-29
6
+ // > Note : read_request, used to generate read request.
7
+ // > Note the request must aligned by 4KB.
8
+ // > V1.1 -- 2020-09-24: Add support for various Max_Read_Request_Size
9
+ // > V1.2 -- 2022-06-29: Add chnl_num field to store
10
+ //*************************************************************************
11
+
12
+ //`include "../lib/global_include_h.v"
13
+ //`include "../lib/dma_def_h.v"
14
+
15
+ module read_request #(
16
+
17
+ ) (
18
+ input wire dma_clk, // i, 1
19
+ input wire rst_n , // i, 1
20
+
21
+ /* ------- Read Request From RDMA{begin} ------- */
22
+ /* dma_*_head, valid only in first beat of a packet
23
+ * | chnl_num | Reserved | address | Reserved | Byte length |
24
+ * | 127:120 | 119:96 | 95:32 | 31:13 | 12:0 |
25
+ */
26
+ output wire rd_req_ready, // o, 1
27
+ input wire [`DMA_HEAD_W-1:0] rd_req_head , // i, `DMA_HEAD_W
28
+ input wire rd_req_valid, // i, 1
29
+ /* ------- Read Request From RDMA{end} ------- */
30
+
31
+ /* -------axis read request interface{begin}------- */
32
+ /* AXI-Stream read request tuser, every read request contains only one beat.
33
+ * | chnl_num |last_sub_req | Reserved | REQ_TYPE |Tag(inv)| address | Reserved | DW length | first BE | last BE |
34
+ * | 127:120 | 119 | 118:108 | 107:104 | 103:96 | 95:32 | 31:19 | 18:8 | 7:4 | 3:0 |
35
+ */
36
+ output wire axis_rd_request_tvalid , // o, 1
37
+ output wire axis_rd_request_tlast , // o, 1
38
+ output wire [`DMA_DATA_W -1:0] axis_rd_request_tdata , // o, `DMA_DATA_W
39
+ output wire [`AXIS_TUSER_W-1:0] axis_rd_request_tuser , // o, `AXIS_TUSER_W
40
+ output wire [`DMA_KEEP_W -1:0] axis_rd_request_tkeep , // o, `DMA_KEEP_W
41
+ input wire axis_rd_request_tready , // i, 1
42
+ /* -------axis read request interface{end}------- */
43
+
44
+ /* --------read request blocking detection{begin}-------- */
45
+ input wire chnl_avail, // i, 1
46
+ input wire chnl_valid, // i, 1
47
+ /* --------read request blocking detection{end}-------- */
48
+
49
+ /* -------PCIe fragment property{begin}------- */
50
+ /* This signal indicates the (max payload size & max read request size) agreed in the communication
51
+ * 3'b000 -- 128 B
52
+ * 3'b001 -- 256 B
53
+ * 3'b010 -- 512 B
54
+ * 3'b011 -- 1024B
55
+ * 3'b100 -- 2048B
56
+ * 3'b101 -- 4096B
57
+ */
58
+ input wire [2:0] max_pyld_sz ,
59
+ input wire [2:0] max_rd_req_sz // max read request size
60
+ /* -------PCIe fragment property{end}------- */
61
+
62
+ `ifdef PCIEI_APB_DBG
63
+ /* -------APB reated signal{begin}------- */
64
+ ,output wire [`RD_REQ_SIGNAL_W-1:0] dbg_signal // o, `RD_REQ_SIGNAL_W
65
+ /* -------APB reated signal{end}------- */
66
+ `endif
67
+ );
68
+
69
+ /* -------State relevant in FSM{begin}------- */
70
+ localparam IDLE = 3'b001, // When there's incomming read req, store the req, and jump to GET_TAG.
71
+ GET_TAG = 3'b010, // Jump to FORWARD directly, we do not get tag at this time.
72
+ FORWARD = 3'b100; // Forward the read request(only one beat). If there is other requests
73
+ // for the dma rd req, jump to GET_TAG. Or jump to IDLE to end tx of the
74
+ // dma rd req.
75
+
76
+ reg [2:0] cur_state;
77
+ reg [2:0] nxt_state;
78
+
79
+
80
+ wire is_idle, is_get_tag, is_forward;
81
+ wire j_idle;
82
+
83
+ reg [`DMA_HEAD_W-1:0] reg_head;
84
+ /* -------State relevant in FSM{end}------- */
85
+
86
+ /* -------Head decode{begin}------- */
87
+ // relate to output
88
+ wire [`DMA_LEN_WIDTH -1:0] byte_len_align;
89
+ wire [`DMA_ADDR_WIDTH-1:0] addr_unalign;
90
+ wire [8 -1:0] chnl_num;
91
+
92
+
93
+ wire [`DMA_ADDR_WIDTH-1:0] addr_align;
94
+ wire [`DW_LEN_WIDTH -1:0] dw_len ;
95
+ wire [`FIRST_BE_WIDTH-1:0] first_be ;
96
+ wire [`LAST_BE_WIDTH -1:0] last_be ;
97
+
98
+ /* -------Head decode{end}------- */
99
+
100
+ /* -------Read request fragment{begin}------- */
101
+ // fragment info
102
+ wire [`DW_LEN_WIDTH-1:0] max_rd_req_dw; // The maximum read request in dw unit
103
+ reg [`DW_LEN_WIDTH-1:0] dw_sent ; // The number of dw read request has been sent in a dma read request
104
+ wire [`DW_LEN_WIDTH-1:0] dw_req ; // read request size of a sub request
105
+ wire is_only_req ;
106
+ wire is_first_req ;
107
+ wire is_middle_req;
108
+ wire is_last_req ;
109
+ wire has_rd_req ; // There's still has read request to be sent in the dma rd request
110
+
111
+
112
+ // axis tuser field
113
+ wire [`TAG_WIDTH+`TAG_EMPTY-1:0] tag ;
114
+ wire [`DMA_ADDR_WIDTH -1:0] axis_addr_align;
115
+ wire [`DW_LEN_WIDTH -1:0] axis_dw_len ;
116
+ wire [`FIRST_BE_WIDTH -1:0] axis_first_be ;
117
+ wire [`LAST_BE_WIDTH -1:0] axis_last_be ;
118
+ /* -------Read Request Fragment{end}------- */
119
+
120
+ /* --------read request blocking detection{begin}-------- */
121
+ reg chnl_avail_reg;
122
+ reg chnl_valid_reg;
123
+ wire is_chnl_blocked;
124
+ wire is_chnl_avail;
125
+ reg is_nxt_req_blocked;
126
+ /* --------read request blocking detection{end}-------- */
127
+
128
+ //---------------------------------------------------------------------------------------------------------------------------
129
+
130
+ `ifdef PCIEI_APB_DBG
131
+ /* -------APB reated signal{begin}------- */
132
+ assign dbg_signal = { // 440
133
+ cur_state, nxt_state, // 6
134
+ is_idle, is_get_tag, is_forward, // 3
135
+ j_idle, // 1
136
+ reg_head, // 128
137
+ byte_len_align, addr_unalign, chnl_num, // 85
138
+ addr_align, dw_len, first_be, last_be, // 83
139
+ max_rd_req_dw, dw_sent, dw_req, is_only_req, is_first_req, is_middle_req, is_last_req, has_rd_req, // 38
140
+ tag, axis_addr_align, axis_dw_len, axis_first_be, axis_last_be, // 91
141
+ chnl_avail_reg, chnl_valid_reg, is_chnl_blocked, is_chnl_avail, is_nxt_req_blocked // 5
142
+ };
143
+ /* -------APB reated signal{end}------- */
144
+ `endif
145
+
146
+ /* --------read request blocking detection{begin}-------- */
147
+ assign is_chnl_avail = (~is_chnl_blocked) | (~is_nxt_req_blocked);
148
+ assign is_chnl_blocked = chnl_valid_reg & (!chnl_avail_reg);
149
+ always @(posedge dma_clk, negedge rst_n) begin
150
+ if (~rst_n) begin
151
+ chnl_avail_reg <= `TD 0;
152
+ chnl_valid_reg <= `TD 0;
153
+ end
154
+ else begin
155
+ chnl_avail_reg <= `TD chnl_avail;
156
+ chnl_valid_reg <= `TD chnl_valid;
157
+ end
158
+ end
159
+
160
+ always @(posedge dma_clk, negedge rst_n) begin
161
+ if (~rst_n) begin
162
+ is_nxt_req_blocked <= `TD 1'b0;
163
+ end
164
+ else if (!is_chnl_blocked) begin
165
+ is_nxt_req_blocked <= `TD 1'b0;
166
+ end
167
+ else if (is_chnl_blocked & axis_rd_request_tvalid & axis_rd_request_tready) begin
168
+ is_nxt_req_blocked <= `TD 1'b1;
169
+ end
170
+ end
171
+ /* --------read request blocking detection{end}-------- */
172
+
173
+ /* -------Head decode{begin}------- */
174
+ // Head storage
175
+ always @(posedge dma_clk, negedge rst_n) begin
176
+ if (~rst_n) begin
177
+ reg_head <= `TD 0;
178
+ end
179
+ else if (is_idle && rd_req_valid && rd_req_ready) begin
180
+ reg_head <= `TD rd_req_head;
181
+ end
182
+ else if (j_idle) begin
183
+ reg_head <= `TD 0;
184
+ end
185
+ end
186
+
187
+ // Head decode
188
+ assign chnl_num = reg_head[127:120];
189
+ assign byte_len_align = reg_head[12:0] + addr_unalign[1:0];
190
+ assign addr_unalign = reg_head[95:32];
191
+ assign addr_align = {addr_unalign[63:2], 2'd0};
192
+ assign dw_len = (byte_len_align>>2) + |byte_len_align[1:0];
193
+ assign first_be = ({4{addr_unalign[1:0] == 2'b00}} & 4'b1111) |
194
+ ({4{addr_unalign[1:0] == 2'b01}} & 4'b1110) |
195
+ ({4{addr_unalign[1:0] == 2'b10}} & 4'b1100) |
196
+ ({4{addr_unalign[1:0] == 2'b11}} & 4'b1000);
197
+ assign last_be = ({4{byte_len_align[1:0] == 2'b00}} & 4'b1111) |
198
+ ({4{byte_len_align[1:0] == 2'b01}} & 4'b0001) |
199
+ ({4{byte_len_align[1:0] == 2'b10}} & 4'b0011) |
200
+ ({4{byte_len_align[1:0] == 2'b11}} & 4'b0111);
201
+ /* -------Head decode{end}------- */
202
+
203
+ /* -------Read request fragment{begin}------- */
204
+ // fragment info
205
+ assign max_rd_req_dw = (11'd1 << (5 + max_rd_req_sz));
206
+ assign dw_req = dw_len - dw_sent;
207
+ assign is_only_req = (is_get_tag | is_forward) & (max_rd_req_dw >= dw_len);
208
+ assign is_first_req = (is_get_tag | is_forward) & (max_rd_req_dw < dw_len) & (dw_sent == 0);
209
+ assign is_middle_req = (is_get_tag | is_forward) & (max_rd_req_dw < dw_req) & (!is_first_req);
210
+ assign is_last_req = (is_get_tag | is_forward) & (max_rd_req_dw >= dw_req) & (!is_only_req);
211
+ assign has_rd_req = is_first_req | is_middle_req;
212
+ always @(posedge dma_clk, negedge rst_n) begin
213
+ if (~rst_n) begin
214
+ dw_sent <= `TD 0;
215
+ end
216
+ else if (is_forward & axis_rd_request_tvalid & axis_rd_request_tready & has_rd_req) begin
217
+ dw_sent <= `TD dw_sent + max_rd_req_dw;
218
+ end
219
+ else if (j_idle) begin
220
+ dw_sent <= `TD 0;
221
+ end
222
+ end
223
+
224
+
225
+ // axis tuser field
226
+ assign tag = {`TAG_EMPTY+`TAG_WIDTH{1'd0}};
227
+ assign axis_addr_align = addr_align + (dw_sent << 2);
228
+ assign axis_dw_len = ({`DW_LEN_WIDTH{is_only_req }} & dw_len ) |
229
+ ({`DW_LEN_WIDTH{is_first_req }} & max_rd_req_dw) |
230
+ ({`DW_LEN_WIDTH{is_middle_req}} & max_rd_req_dw) |
231
+ ({`DW_LEN_WIDTH{is_last_req }} & dw_req );
232
+ assign axis_first_be = (is_only_req & (dw_req == 1)) ? (first_be & last_be) :
233
+ (is_last_req & (dw_req == 1)) ? last_be :
234
+ (is_only_req | is_first_req ) ? first_be : 4'b1111;
235
+
236
+ assign axis_last_be = (is_only_req & (dw_req == 1)) ? 4'b0000 :
237
+ (is_last_req & (dw_req == 1)) ? 4'b0000 :
238
+ (is_only_req | is_last_req ) ? last_be : 4'b1111;
239
+ /* -------Read Request Fragment{end}------- */
240
+
241
+ /* -------{Read Request FSM}begin------- */
242
+ /******************** Stage 1: State Register **********************/
243
+ assign is_idle = (cur_state == IDLE );
244
+ assign is_get_tag = (cur_state == GET_TAG);
245
+ assign is_forward = (cur_state == FORWARD);
246
+ assign j_idle = (cur_state == FORWARD) & axis_rd_request_tvalid & axis_rd_request_tready & !has_rd_req;
247
+
248
+ always @(posedge dma_clk, negedge rst_n) begin
249
+ if(~rst_n)
250
+ cur_state <= `TD IDLE;
251
+ else
252
+ cur_state <= `TD nxt_state;
253
+ end
254
+
255
+ /******************** Stage 2: State Transition **********************/
256
+
257
+ always @(*) begin
258
+ case(cur_state)
259
+ IDLE: begin
260
+ if (rd_req_valid & rd_req_ready) begin
261
+ nxt_state = GET_TAG;
262
+ end
263
+ else begin
264
+ nxt_state = IDLE;
265
+ end
266
+ end
267
+ GET_TAG: begin
268
+ nxt_state = FORWARD;
269
+ end
270
+ FORWARD: begin
271
+ if (axis_rd_request_tvalid & axis_rd_request_tready & has_rd_req) begin
272
+ nxt_state = GET_TAG;
273
+ end
274
+ else if (axis_rd_request_tvalid & axis_rd_request_tready & !has_rd_req) begin
275
+ nxt_state = IDLE;
276
+ end
277
+ else begin
278
+ nxt_state = FORWARD;
279
+ end
280
+ end
281
+ default: begin
282
+ nxt_state = IDLE;
283
+ end
284
+ endcase
285
+ end
286
+ /******************** Stage 3: Output **********************/
287
+ // The module will not receive read req from the channel
288
+ // if the channel is blocked.
289
+ assign rd_req_ready = is_idle & is_chnl_avail;
290
+
291
+ /* AXI-Stream read request tuser, every read request contains only one beat.
292
+ * | chnl_num |last_sub_req | Reserved | REQ_TYPE |Tag(inv)| address | Reserved | DW length | first BE | last BE |
293
+ * | 127:120 | 119 | 118:108 | 107:104 | 103:96 | 95:32 | 31:19 | 18:8 | 7:4 | 3:0 |
294
+ */
295
+ // The module will not output sub_req if the channel id blocked
296
+ assign axis_rd_request_tvalid = is_forward & is_chnl_avail;
297
+ assign axis_rd_request_tlast = is_forward;
298
+ assign axis_rd_request_tdata = {`DMA_DATA_W{1'd0}};
299
+ assign axis_rd_request_tuser = is_forward ? {chnl_num, !has_rd_req, 11'd0, `DMA_READ_REQ, tag, axis_addr_align, {24-`DW_LEN_WIDTH{1'd0}},
300
+ axis_dw_len, axis_first_be, axis_last_be} : 0;
301
+ assign axis_rd_request_tkeep = {`DMA_KEEP_W{1'd0}};
302
+
303
+ /* -------{Read Request FSM}end------- */
304
+
305
+
306
+ endmodule
ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/DMA/DMA_Read/read_response.v ADDED
@@ -0,0 +1,351 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ `timescale 1ns / 100ps
2
+ //*************************************************************************
3
+ // > File Name: read_response.v
4
+ // > Author : Kangning
5
+ // > Date : V1.0 -- 2020-08-27
6
+ // > Note : read_response, used to get read response from PCIe, and
7
+ // > reorder the out-of-order packet.
8
+ // > V1.1 -- 2020-09-27: Add support for sub-request recombination
9
+ // > and response recombination
10
+ // > V1.2 -- 2021-04-14: Reconstruct the file with the following structure.
11
+ // > |------------|------------------|------------|------------|
12
+ // > | input axis | transfrom to | FSM | rsp data |
13
+ // > | data | dma_head type | processing | reassemble |
14
+ // > | | (dw dealignment) | (reorder) | |
15
+ // > |------------|------------------|------------|------------|
16
+ // > V1.3 -- 2022-06-29: Rebuild the read response channel.
17
+ // > |------------|------------------|------------|-------------|
18
+ // > | input axis | transfrom to | push to | ifc warpper |
19
+ // > | data | dma_head type | reorder | sub_req_rsp |
20
+ // > | | (dw dealignment) | buffer | |
21
+ // > |------------|------------------|------------|-------------|
22
+ //*************************************************************************
23
+
24
+ //`include "../lib/global_include_h.v"
25
+ //`include "../lib/dma_def_h.v"
26
+
27
+ module read_response #(
28
+
29
+ ) (
30
+ input wire dma_clk, // i, 1
31
+ input wire rst_n , // i, 1
32
+ output wire init_done, // o, 1
33
+
34
+ /* -------axis read response interface{begin}------- */
35
+ /* AXI-Stream read response tuser, interact with read response distributor.
36
+ * Only valid in first beat of a packet
37
+ * | Reserved | REQ CPL | Tag | address | Reserved | DW length | first BE | last BE |
38
+ * | 119:105 | 104 | 103:96 | 95:32 | 31:19 | 18:8 | 7:4 | 3:0 |
39
+ */
40
+ input wire axis_rd_rsp_tvalid, // i, 1
41
+ input wire axis_rd_rsp_tlast , // i, 1
42
+ input wire [`DMA_DATA_W -1:0] axis_rd_rsp_tdata , // i, `DMA_DATA_W
43
+ input wire [`AXIS_TUSER_W-1:0] axis_rd_rsp_tuser , // i, `AXIS_TUSER_W
44
+ input wire [`DMA_KEEP_W -1:0] axis_rd_rsp_tkeep , // i, `DMA_KEEP_W
45
+ output wire axis_rd_rsp_tready, // o, 1
46
+ /* -------axis read response interface{end}------- */
47
+
48
+ /* -------tag release{begin}------- */
49
+ // Note that only one channel is allowed to assert at the same time
50
+ output wire [`DMA_RD_CHNL_NUM * 1 - 1 : 0] tag_rrsp_ready, // o, 1
51
+ input wire [`DMA_RD_CHNL_NUM * 1 - 1 : 0] tag_rrsp_last , // i, 1
52
+ input wire [`DMA_RD_CHNL_NUM * `DW_LEN_WIDTH - 1 : 0] tag_rrsp_sz , // i, `DW_LEN_WIDTH
53
+ input wire [`DMA_RD_CHNL_NUM * `TAG_MISC - 1 : 0] tag_rrsp_misc , // i, `TAG_MISC ; Including addr && dw empty info
54
+ input wire [`DMA_RD_CHNL_NUM * `TAG_NUM_LOG - 1 : 0] tag_rrsp_tag , // i, `TAG_NUM_LOG
55
+ input wire [`DMA_RD_CHNL_NUM * 1 - 1 : 0] tag_rrsp_valid, // i, 1
56
+ /* -------tag release{end}------- */
57
+
58
+ /* ------- Read sub-req response{begin} ------- */
59
+ /* dma_*_head
60
+ * | emit | chnl_num | Reserved | address | Reserved | Byte length |
61
+ * | 127 | 126:120 | 119:96 | 95:32 | 31:13 | 12:0 |
62
+ */
63
+ output wire sub_req_rsp_valid, // o, 1
64
+ output wire sub_req_rsp_last , // o, 1
65
+ output wire [`DMA_DATA_W-1:0] sub_req_rsp_data , // o, `DMA_DATA_W
66
+ output wire [`DMA_HEAD_W-1:0] sub_req_rsp_head , // o, `DMA_HEAD_W
67
+ input wire sub_req_rsp_ready, // i, 1
68
+ /* ------- Read sub-req response{end} ------- */
69
+
70
+ /* --------chnl_stall{begin}-------- */
71
+ input wire [`DMA_RD_CHNL_NUM - 1 : 0] chnl_avail // i, `DMA_RD_CHNL_NUM
72
+ /* --------chnl_stall{end}-------- */
73
+
74
+ `ifdef PCIEI_APB_DBG
75
+ /* -------APB reated signal{begin}------- */
76
+ ,input wire [`SRAM_RW_DATA_W*2-1:0] rw_data // i, `SRAM_RW_DATA_W*2
77
+ ,input wire [31:0] dbg_sel // i, 32
78
+ ,output wire [31:0] dbg_bus // o, 32
79
+ /* -------APB reated signal{end}------- */
80
+ `endif
81
+ );
82
+
83
+ /* -------tag release{begin}------- */
84
+ wire nxt_match_ready;
85
+ wire nxt_match_last ;
86
+ wire [`DW_LEN_WIDTH-1:0] nxt_match_sz ;
87
+ wire [`TAG_MISC -1:0] nxt_match_misc ;
88
+ wire [8 -1:0] nxt_match_chnl ;
89
+ wire [`TAG_NUM_LOG -1:0] nxt_match_tag ;
90
+ wire nxt_match_valid;
91
+
92
+ wire is_begin_ft; // begin fetch pkt in reorder buffer and forward it to the concat module
93
+
94
+ // wire st_nxt_match_ready;
95
+ // wire st_nxt_match_last ;
96
+ // wire [`DW_LEN_WIDTH-1:0] st_nxt_match_sz ;
97
+ // wire [8 -1:0] st_nxt_match_chnl ;
98
+ // wire [`TAG_NUM_LOG -1:0] st_nxt_match_tag ;
99
+ // wire st_nxt_match_valid;
100
+ /* -------tag release{end}------- */
101
+
102
+ /* ------- Related to Reorder Buffer{begin} ------- */
103
+ wire st_rd_rsp_wen ;
104
+ wire st_rd_rsp_last;
105
+ wire st_rd_rsp_eop ;
106
+ wire [`DMA_HEAD_W -1:0] st_rd_rsp_head;
107
+ wire [`DW_LEN_WIDTH-1:0] st_rd_rsp_dlen;
108
+ wire [`TAG_NUM_LOG -1:0] st_rd_rsp_tag ;
109
+ wire [`DMA_DATA_W -1:0] st_rd_rsp_data;
110
+ wire st_rd_rsp_rdy ;
111
+
112
+ wire ft_rd_rsp_ren ;
113
+ wire [`TAG_NUM_LOG-1:0] ft_rd_rsp_tag ;
114
+ wire [`DMA_HEAD_W -1:0] ft_rd_rsp_head;
115
+ wire [`DMA_DATA_W -1:0] ft_rd_rsp_data;
116
+ wire ft_rd_rsp_last;
117
+ wire ft_rd_rsp_vld ;
118
+ /* ------- Related to Reorder Buffer{end} ------- */
119
+
120
+ `ifdef PCIEI_APB_DBG
121
+ /* -------APB reated signal{begin}------- */
122
+ wire [32-1:0] dbg_sel_rd_rsp_top, dbg_sel_rsp_dealign, dbg_sel_reorder_buf, dbg_sel_tag_matching, dbg_sel_wrapper;
123
+ wire [32-1:0] dbg_bus_rd_rsp_top, dbg_bus_rsp_dealign, dbg_bus_reorder_buf, dbg_bus_tag_matching, dbg_bus_wrapper;
124
+
125
+ wire [`RD_RSP_TOP_SIGNAL_W -1:0] dbg_signal_rd_rsp_top;
126
+ wire [`RSP_DEALIGN_SIGNAL_W -1:0] dbg_signal_rsp_dealign;
127
+ /* -------APB reated signal{end}------- */
128
+ `endif
129
+
130
+ //---------------------------------------------------------------------------------------------------------------------------
131
+
132
+ `ifdef PCIEI_APB_DBG
133
+ /* -------APB reated signal{begin}------- */
134
+ assign dbg_bus = (`RD_RSP_TOP_DBG_B <= dbg_sel && dbg_sel < `RSP_DEALIGN_DBG_B ) ? dbg_bus_rd_rsp_top :
135
+ (`RSP_DEALIGN_DBG_B <= dbg_sel && dbg_sel < `REORDER_BUF_DBG_B ) ? dbg_bus_rsp_dealign :
136
+ (`REORDER_BUF_DBG_B <= dbg_sel && dbg_sel < `TAG_MATCHING_DBG_B) ? dbg_bus_reorder_buf :
137
+ (`TAG_MATCHING_DBG_B <= dbg_sel && dbg_sel < `WRAPPER_DBG_B ) ? dbg_bus_tag_matching :
138
+ (`WRAPPER_DBG_B <= dbg_sel && dbg_sel < `RD_RSP_DBG_SIZE ) ? dbg_bus_wrapper : 32'd0;
139
+
140
+ assign dbg_sel_rd_rsp_top = (`RD_RSP_TOP_DBG_B <= dbg_sel && dbg_sel < `RSP_DEALIGN_DBG_B ) ? (dbg_sel - `RD_RSP_TOP_DBG_B ) : 32'd0;
141
+ assign dbg_sel_rsp_dealign = (`RSP_DEALIGN_DBG_B <= dbg_sel && dbg_sel < `REORDER_BUF_DBG_B ) ? (dbg_sel - `RSP_DEALIGN_DBG_B ) : 32'd0;
142
+ assign dbg_sel_reorder_buf = (`REORDER_BUF_DBG_B <= dbg_sel && dbg_sel < `TAG_MATCHING_DBG_B) ? (dbg_sel - `REORDER_BUF_DBG_B ) : 32'd0;
143
+ assign dbg_sel_tag_matching = (`TAG_MATCHING_DBG_B <= dbg_sel && dbg_sel < `WRAPPER_DBG_B ) ? (dbg_sel - `TAG_MATCHING_DBG_B) : 32'd0;
144
+ assign dbg_sel_wrapper = (`WRAPPER_DBG_B <= dbg_sel && dbg_sel < `RD_RSP_DBG_SIZE ) ? (dbg_sel - `WRAPPER_DBG_B ) : 32'd0;
145
+
146
+ // Debug bus for read rsp top
147
+ assign dbg_bus_rd_rsp_top = dbg_signal_rd_rsp_top >> {dbg_sel_rd_rsp_top, 5'd0};
148
+
149
+ // Debug bus for rrsp dealign
150
+ assign dbg_bus_rsp_dealign = dbg_signal_rsp_dealign >> {dbg_sel_rsp_dealign, 5'd0};
151
+
152
+ assign dbg_signal_rd_rsp_top = { // 827
153
+ nxt_match_ready, nxt_match_last, nxt_match_sz, nxt_match_misc, nxt_match_chnl, nxt_match_tag , nxt_match_valid, // 28
154
+ is_begin_ft, // 1
155
+ st_rd_rsp_wen , st_rd_rsp_last, st_rd_rsp_eop , st_rd_rsp_head, st_rd_rsp_dlen, st_rd_rsp_tag , st_rd_rsp_data, st_rd_rsp_rdy, // 405
156
+ ft_rd_rsp_ren , ft_rd_rsp_tag, ft_rd_rsp_head, ft_rd_rsp_data, ft_rd_rsp_last, ft_rd_rsp_vld // 393
157
+ };
158
+ /* -------APB reated signal{end}------- */
159
+ `endif
160
+
161
+
162
+ /* -------Double word dealignment{begin}------- */
163
+ rrsp_dealign #(
164
+
165
+ ) rrsp_dealign (
166
+ .dma_clk ( dma_clk ), // i, 1
167
+ .rst_n ( rst_n ), // i, 1
168
+
169
+
170
+ /* -------axis read response interface{begin}------- */
171
+ /* AXI-Stream read response tuser, interact with read response distributor.
172
+ * Only valid in first beat of a packet
173
+ * | Reserved | REQ CPL | Tag | address | Reserved | DW length | first BE | last BE |
174
+ * | 119:105 | 104 | 103:96 | 95:32 | 31:19 | 18:8 | 7:4 | 3:0 |
175
+ */
176
+ .axis_rd_rsp_tvalid ( axis_rd_rsp_tvalid ), // i, 1
177
+ .axis_rd_rsp_tlast ( axis_rd_rsp_tlast ), // i, 1
178
+ .axis_rd_rsp_tdata ( axis_rd_rsp_tdata ), // i, `DMA_DATA_W
179
+ .axis_rd_rsp_tuser ( axis_rd_rsp_tuser ), // i, `AXIS_TUSER_W
180
+ .axis_rd_rsp_tkeep ( axis_rd_rsp_tkeep ), // i, `DMA_KEEP_W
181
+ .axis_rd_rsp_tready ( axis_rd_rsp_tready ), // o, 1
182
+ /* -------axis read response interface{end}------- */
183
+
184
+
185
+ /* ------- Read Response store to Reorder Buffer{begin} ------- */
186
+ /* *_head (interact with <reorder_buffer> module, valid only in first beat of a packet
187
+ * | Reserved | address | Reserved | Byte length |
188
+ * | 127:96 | 95:32 | 31:13 | 12:0 |
189
+ */
190
+ .rd_rsp_dealign_valid ( st_rd_rsp_wen ), // o, 1
191
+ .rd_rsp_dealign_last ( st_rd_rsp_last ), // o, 1 ; assert in every last beat of sub-rsp pkt
192
+ .rd_rsp_dealign_eop ( st_rd_rsp_eop ), // o, 1 ; assert when this is the last sub-rsp pkt
193
+ .rd_rsp_dealign_dlen ( st_rd_rsp_dlen ), // o, `DW_LEN_WIDTH ; part of head field in "store channel"
194
+ .rd_rsp_dealign_tag ( st_rd_rsp_tag ), // o, `TAG_NUM_LOG ; part of head field in "store channel"
195
+ .rd_rsp_dealign_head ( st_rd_rsp_head ), // o, `DMA_HEAD_W
196
+ .rd_rsp_dealign_data ( st_rd_rsp_data ), // o, `DMA_DATA_W
197
+ .rd_rsp_dealign_ready ( st_rd_rsp_rdy ) // i, 1
198
+ /* ------- Read Response store to Reorder Buffer{end} ------- */
199
+
200
+ `ifdef PCIEI_APB_DBG
201
+ /* -------APB reated signal{begin}------- */
202
+ ,.dbg_signal ( dbg_signal_rsp_dealign ) // o, `RSP_DEALIGN_SIGNAL_W
203
+ /* -------APB reated signal{end}------- */
204
+ `endif
205
+ );
206
+ /* -------Double word dealignment{end}------- */
207
+
208
+ /* -------Reorder Buffer{begin}------- */
209
+ reorder_buf #(
210
+
211
+ ) reorder_buffer (
212
+ .dma_clk ( dma_clk ), // i, 1
213
+ .rst_n ( rst_n ), // i, 1
214
+ .init_done ( init_done ), // o, 1
215
+
216
+ /* ------- Read Response input{begin} ------- */
217
+ /* *_head, valid only in first beat of a packet
218
+ * | Reserved | address | Reserved | Byte length |
219
+ * | 127:96 | 95:32 | 31:13 | 12:0 |
220
+ */
221
+ .st_rd_rsp_wen ( st_rd_rsp_wen ), // i, 1
222
+ .st_rd_rsp_last ( st_rd_rsp_last ), // i, 1 ; assert in every last beat of sub-rsp pkt
223
+ .st_rd_rsp_eop ( st_rd_rsp_eop ), // i, 1 ; assert when this is the last sub-rsp pkt
224
+ .st_rd_rsp_tag ( st_rd_rsp_tag ), // i, `TAG_NUM_LOG
225
+ .st_rd_rsp_head ( st_rd_rsp_head ), // i, `DMA_HEAD_W
226
+ .st_rd_rsp_data ( st_rd_rsp_data ), // i, `DMA_DATA_W
227
+ .st_rd_rsp_rdy ( st_rd_rsp_rdy ), // o, 1
228
+ /* ------- Read Response input{end} ------- */
229
+
230
+
231
+ /* ------- Read Response output{begin} ------- */
232
+ /* *_head, valid only in first beat of a packet
233
+ * | Reserved | address | Reserved | Byte length |
234
+ * | 127:96 | 95:32 | 31:13 | 12:0 |
235
+ */
236
+ .ft_rd_rsp_ren ( ft_rd_rsp_ren ), // i, 1
237
+ .ft_rd_rsp_tag ( ft_rd_rsp_tag ), // i, `TAG_NUM_LOG
238
+ .ft_rd_rsp_head ( ft_rd_rsp_head ), // o, `DMA_HEAD_W
239
+ .ft_rd_rsp_data ( ft_rd_rsp_data ), // o, `DMA_DATA_W
240
+ .ft_rd_rsp_last ( ft_rd_rsp_last ), // o, 1
241
+ .ft_rd_rsp_vld ( ft_rd_rsp_vld ) // o, 1
242
+ /* ------- Read Response output{end} ------- */
243
+
244
+ `ifdef PCIEI_APB_DBG
245
+ /* -------APB reated signal{begin}------- */
246
+ ,.rw_data ( rw_data ) // i, `SRAM_RW_DATA_W*2
247
+ ,.dbg_sel ( dbg_sel_reorder_buf ) // i, 32
248
+ ,.dbg_bus ( dbg_bus_reorder_buf ) // o, 32
249
+ /* -------APB reated signal{end}------- */
250
+ `endif
251
+ );
252
+ /* -------Reorder Buffer{end}------- */
253
+
254
+ assign is_begin_ft = ft_rd_rsp_ren;
255
+ tag_matching #(
256
+
257
+ ) tag_matching (
258
+
259
+ .dma_clk ( dma_clk ), // i, 1
260
+ .rst_n ( rst_n ), // i, 1
261
+
262
+ /* -------tag release{begin}------- */
263
+ // Note that only one channel is allowed to assert at the same time
264
+ .tag_rrsp_ready ( tag_rrsp_ready ), // o, `DMA_RD_CHNL_NUM * 1
265
+ .tag_rrsp_last ( tag_rrsp_last ), // i, `DMA_RD_CHNL_NUM * 1
266
+ .tag_rrsp_sz ( tag_rrsp_sz ), // i, `DMA_RD_CHNL_NUM * `DW_LEN_WIDTH
267
+ .tag_rrsp_misc ( tag_rrsp_misc ), // i, `DMA_RD_CHNL_NUM * `TAG_MISC ; Including addr && dw empty info
268
+ .tag_rrsp_tag ( tag_rrsp_tag ), // i, `DMA_RD_CHNL_NUM * `TAG_NUM_LOG
269
+ .tag_rrsp_valid ( tag_rrsp_valid ), // i, `DMA_RD_CHNL_NUM * 1
270
+ /* -------tag release{end}------- */
271
+
272
+ /* ------- Store input{begin} ------- */
273
+ .st_rd_rsp_wen ( st_rd_rsp_wen ), // i, 1
274
+ .st_rd_rsp_last ( st_rd_rsp_last ), // i, 1 ; assert in every last beat of sub-rsp pkt
275
+ .st_rd_rsp_dlen ( st_rd_rsp_dlen ), // i, `DW_LEN_WIDTH ; part of head field in "store channel"
276
+ .st_rd_rsp_tag ( st_rd_rsp_tag ), // i, `TAG_NUM_LOG ; part of head field in "store channel"
277
+ .st_rd_rsp_rdy ( st_rd_rsp_rdy ), // i, 1
278
+ /* ------- Store input{end} ------- */
279
+
280
+ /* --------chnl_stall{begin}-------- */
281
+ .chnl_avail ( chnl_avail | {`DMA_RD_CHNL_NUM{is_begin_ft}} ), // i, `DMA_RD_CHNL_NUM
282
+ /* --------chnl_stall{end}-------- */
283
+
284
+ /* -------tag release{begin}------- */
285
+ .nxt_match_ready ( nxt_match_ready ), // i, 1
286
+ .nxt_match_last ( nxt_match_last ), // o, 1
287
+ .nxt_match_sz ( nxt_match_sz ), // o, `DW_LEN_WIDTH
288
+ .nxt_match_misc ( nxt_match_misc ), // o, `TAG_MISC ; Including addr && dw empty info
289
+ .nxt_match_chnl ( nxt_match_chnl ), // o, 8
290
+ .nxt_match_tag ( nxt_match_tag ), // o, `TAG_NUM_LOG
291
+ .nxt_match_valid ( nxt_match_valid ) // o, 1
292
+ /* -------tag release{end}------- */
293
+
294
+ `ifdef PCIEI_APB_DBG
295
+ /* -------APB reated signal{begin}------- */
296
+ ,.dbg_sel ( dbg_sel_tag_matching ) // i, 32
297
+ ,.dbg_bus ( dbg_bus_tag_matching ) // o, 32
298
+ /* -------APB reated signal{end}------- */
299
+ `endif
300
+ );
301
+
302
+ sub_req_rsp_wrapper #(
303
+
304
+ ) sub_req_rsp_wrapper (
305
+ .dma_clk ( dma_clk ), // i, 1
306
+ .rst_n ( rst_n ), // i, 1
307
+
308
+ /* ------- Read Response output{begin} ------- */
309
+ /* *_head (interact with <read_response> module, valid only in first beat of a packet
310
+ * | Reserved | address | Reserved | Byte length |
311
+ * | 127:96 | 95:32 | 31:13 | 12:0 |
312
+ */
313
+ .ft_rd_rsp_ren ( ft_rd_rsp_ren ), // o, 1
314
+ .ft_rd_rsp_tag ( ft_rd_rsp_tag ), // o, `TAG_NUM_LOG
315
+ .ft_rd_rsp_head ( ft_rd_rsp_head ), // i, `DMA_HEAD_W
316
+ .ft_rd_rsp_data ( ft_rd_rsp_data ), // i, `DMA_DATA_W
317
+ .ft_rd_rsp_last ( ft_rd_rsp_last ), // i, 1
318
+ .ft_rd_rsp_vld ( ft_rd_rsp_vld ), // i, 1
319
+ /* ------- Read Response output{end} ------- */
320
+
321
+ /* -------tag release{begin}------- */
322
+ .nxt_match_ready ( nxt_match_ready ), // o, 1
323
+ .nxt_match_last ( nxt_match_last ), // i, 1
324
+ .nxt_match_sz ( nxt_match_sz ), // i, `DW_LEN_WIDTH
325
+ .nxt_match_misc ( nxt_match_misc ), // i, `TAG_MISC ; Including addr && dw empty info
326
+ .nxt_match_chnl ( nxt_match_chnl ), // i, 8
327
+ .nxt_match_tag ( nxt_match_tag ), // i, `TAG_NUM_LOG
328
+ .nxt_match_valid ( nxt_match_valid ), // i, 1
329
+ /* -------tag release{end}------- */
330
+
331
+ /* ------- Read sub-req response{begin} ------- */
332
+ /* dma_*_head
333
+ * | emit | chnl_num | Reserved | address | Reserved | Byte length |
334
+ * | 127 | 126:120 | 119:96 | 95:32 | 31:13 | 12:0 |
335
+ */
336
+ .st_sub_req_rsp_valid ( sub_req_rsp_valid ), // o, 1
337
+ .st_sub_req_rsp_last ( sub_req_rsp_last ), // o, 1
338
+ .st_sub_req_rsp_data ( sub_req_rsp_data ), // o, `DMA_DATA_W
339
+ .st_sub_req_rsp_head ( sub_req_rsp_head ), // o, `DMA_HEAD_W
340
+ .st_sub_req_rsp_ready ( sub_req_rsp_ready ) // i, 1
341
+ /* ------- Read sub-req response{end} ------- */
342
+
343
+ `ifdef PCIEI_APB_DBG
344
+ /* -------APB reated signal{begin}------- */
345
+ ,.dbg_sel ( dbg_sel_wrapper ) // i, 32
346
+ ,.dbg_bus ( dbg_bus_wrapper ) // o, 32
347
+ /* -------APB reated signal{end}------- */
348
+ `endif
349
+ );
350
+
351
+ endmodule
ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/DMA/DMA_Read/reorder_buf.v ADDED
@@ -0,0 +1,220 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ `timescale 1ns / 100ps
2
+ //*************************************************************************
3
+ // > File Name: reorder_buf.v
4
+ // > Author : Kangning
5
+ // > Date : 2023-02-27
6
+ // > Note : reorder_buf, which acts as a reorder buffer
7
+ //*************************************************************************
8
+
9
+ //`include "../lib/dma_def_h.v"
10
+
11
+ module reorder_buf #(
12
+
13
+ ) (
14
+ input wire dma_clk , // i, 1
15
+ input wire rst_n , // i, 1
16
+ output wire init_done, // o, 1
17
+
18
+ /* ------- Reorder buf input{begin} ------- */
19
+ /* *_head (interact with <read_response> module, valid only in first beat of a packet
20
+ * | Reserved | address | Reserved | Byte length |
21
+ * | 127:96 | 95:32 | 31:13 | 12:0 |
22
+ */
23
+ input wire st_rd_rsp_wen , // i, 1
24
+ input wire st_rd_rsp_last, // i, 1 ; assert in every last beat of sub-rsp pkt
25
+ input wire st_rd_rsp_eop , // i, 1 ; assert when this is the last sub-rsp pkt
26
+ input wire [`TAG_NUM_LOG-1:0] st_rd_rsp_tag , // i, `TAG_NUM_LOG
27
+ input wire [`DMA_HEAD_W -1:0] st_rd_rsp_head, // i, `DMA_HEAD_W
28
+ input wire [`DMA_DATA_W -1:0] st_rd_rsp_data, // i, `DMA_DATA_W
29
+ output wire st_rd_rsp_rdy , // o, 1
30
+ /* ------- Reorder buf input{end} ------- */
31
+
32
+
33
+ /* ------- Reorder buf output{begin} ------- */
34
+ /* *_head (interact with <read_response> module, valid only in first beat of a packet
35
+ * | Reserved | address | Reserved | Byte length |
36
+ * | 127:96 | 95:32 | 31:13 | 12:0 |
37
+ */
38
+ input wire ft_rd_rsp_ren , // i, 1
39
+ input wire [`TAG_NUM_LOG-1:0] ft_rd_rsp_tag , // i, `TAG_NUM_LOG
40
+ output wire [`DMA_HEAD_W -1:0] ft_rd_rsp_head, // o, `DMA_HEAD_W
41
+ output wire [`DMA_DATA_W -1:0] ft_rd_rsp_data, // o, `DMA_DATA_W
42
+ output wire ft_rd_rsp_last, // o, 1
43
+ output wire ft_rd_rsp_vld // o, 1
44
+ /* ------- Reorder buf output{end} ------- */
45
+
46
+ `ifdef PCIEI_APB_DBG
47
+ /* -------APB reated signal{begin}------- */
48
+ ,input wire [`SRAM_RW_DATA_W*2-1:0] rw_data // i, `SRAM_RW_DATA_W*2
49
+ ,input wire [31:0] dbg_sel // i, 32
50
+ ,output wire [31:0] dbg_bus // o, 32
51
+ /* -------APB reated signal{end}------- */
52
+ `endif
53
+ );
54
+
55
+ /* ------- Reorder buf input{begin} ------- */
56
+ /* *_head (interact with <read_response> module, valid only in first beat of a packet
57
+ * | Reserved | address | Reserved | Byte length |
58
+ * | 127:96 | 95:32 | 31:13 | 12:0 |
59
+ */
60
+ wire st_store_rd_rsp_wen ;
61
+ wire st_store_rd_rsp_last;
62
+ wire st_store_rd_rsp_eop ;
63
+ wire [`DMA_LEN_WIDTH-1:0] st_store_rd_rsp_blen;
64
+ wire [`TAG_NUM_LOG -1:0] st_store_rd_rsp_tag ;
65
+ wire [`DMA_HEAD_W -1:0] st_store_rd_rsp_head;
66
+ wire [`DMA_DATA_W -1:0] st_store_rd_rsp_data;
67
+ wire st_store_rd_rsp_rdy ;
68
+ /* ------- Reorder buf input{end} ------- */
69
+
70
+ wire [`DMA_LEN_WIDTH -1:0] sub_blen_total ;
71
+ wire [`DMA_LEN_WIDTH -1:0] sub_blen_left ;
72
+ reg [`DMA_LEN_WIDTH -1:0] store_trans_cnt;
73
+
74
+
75
+ wire store_wen ;
76
+ wire [`TAG_NUM_LOG-1:0] store_tag ;
77
+ wire store_last;
78
+ wire [`DMA_DATA_W -1:0] store_data;
79
+ wire store_rdy;
80
+
81
+ `ifdef PCIEI_APB_DBG
82
+ /* -------APB reated signal{begin}------- */
83
+ wire [`SRAM_RW_DATA_W-1:0] concat_rw_data;
84
+ wire [`SRAM_RW_DATA_W-1:0] tag_buf_rw_data;
85
+
86
+ wire [`SUB_RSP_CONCAT_SIGNAL_W-1:0] dbg_signal_sub_rsp_concat;
87
+ wire [`TAG_BUF_SIGNAL_W -1:0] dbg_signal_tag_buf;
88
+ wire [`REBUF_TOP_SIGNAL_W -1:0] dbg_signal_rebuf_top;
89
+ /* -------APB reated signal{end}------- */
90
+ `endif
91
+
92
+ //---------------------------------------------------------------------------------------------------------------------------
93
+
94
+ `ifdef PCIEI_APB_DBG
95
+ /* -------APB reated signal{begin}------- */
96
+ assign {tag_buf_rw_data, concat_rw_data} = rw_data;
97
+
98
+ assign dbg_bus = {dbg_signal_rebuf_top, dbg_signal_sub_rsp_concat, dbg_signal_tag_buf} >> {dbg_sel, 5'd0};
99
+
100
+ assign dbg_signal_rebuf_top = { // 711
101
+ st_store_rd_rsp_wen , st_store_rd_rsp_last, st_store_rd_rsp_eop , st_store_rd_rsp_blen,
102
+ st_store_rd_rsp_tag , st_store_rd_rsp_head, st_store_rd_rsp_data, st_store_rd_rsp_rdy, // 407
103
+
104
+ sub_blen_total , sub_blen_left , store_trans_cnt, // 39
105
+
106
+ store_wen , store_tag , store_last, store_data, store_rdy // 265
107
+ };
108
+ /* -------APB reated signal{end}------- */
109
+ `endif
110
+
111
+ /* -------Stream reg for st channel signal{begin}-------- */
112
+ st_reg #(
113
+ .TUSER_WIDTH ( `TAG_NUM_LOG + `DMA_HEAD_W ),
114
+ .TDATA_WIDTH ( 1 + `DMA_DATA_W )
115
+ ) in_st_reg (
116
+ .clk ( dma_clk ), // i, 1
117
+ .rst_n ( rst_n ), // i, 1
118
+
119
+ /* -------input axis-like interface{begin}------- */
120
+ .axis_tvalid ( st_rd_rsp_wen ), // i, 1
121
+ .axis_tlast ( st_rd_rsp_last ), // i, 1
122
+ .axis_tuser ( {st_rd_rsp_tag, st_rd_rsp_head} ), // i, TUSER_WIDTH
123
+ .axis_tdata ( {st_rd_rsp_eop, st_rd_rsp_data} ), // i, TDATA_WIDTH
124
+ .axis_tready ( st_rd_rsp_rdy ), // o, 1
125
+ /* -------input axis-like interface{end}------- */
126
+
127
+ /* -------output inteface{begin}------- */
128
+ .axis_reg_tvalid ( st_store_rd_rsp_wen ), // o, 1
129
+ .axis_reg_tlast ( st_store_rd_rsp_last ), // o, 1
130
+ .axis_reg_tuser ( {st_store_rd_rsp_tag, st_store_rd_rsp_head} ), // o, TUSER_WIDTH
131
+ .axis_reg_tdata ( {st_store_rd_rsp_eop, st_store_rd_rsp_data} ), // o, TDATA_WIDTH
132
+ .axis_reg_tready ( st_store_rd_rsp_rdy ) // i, 1
133
+ /* -------output inteface{end}------- */
134
+ );
135
+ /* -------Stream reg for st channel signal{end}-------- */
136
+
137
+ /* --------Generate byte length in every cycle{begin}-------- */
138
+ assign st_store_rd_rsp_blen = (sub_blen_left >= `DMA_W_BCNT) ? `DMA_W_BCNT : sub_blen_left;
139
+ assign sub_blen_left = sub_blen_total - store_trans_cnt;
140
+ assign sub_blen_total = st_store_rd_rsp_head[12:0];
141
+ always @(posedge dma_clk, negedge rst_n) begin
142
+ if (~rst_n) begin
143
+ store_trans_cnt <= `TD 0;
144
+ end
145
+ else if (st_store_rd_rsp_wen & st_store_rd_rsp_rdy & st_store_rd_rsp_last) begin
146
+ store_trans_cnt <= `TD 0;
147
+ end
148
+ else if (st_store_rd_rsp_wen & st_store_rd_rsp_rdy) begin
149
+ store_trans_cnt <= `TD store_trans_cnt + `DMA_W_BCNT;
150
+ end
151
+ end
152
+ /* --------Generate byte length in every cycle{end}-------- */
153
+
154
+ /* --------concat sub-rsp data{begin}-------- */
155
+ sub_rsp_concat sub_rsp_concat (
156
+ .dma_clk ( dma_clk ), // i, 1
157
+ .rst_n ( rst_n ), // i, 1
158
+ .init_done ( init_done ), // o, 1
159
+
160
+ /* ------- Store Interface input{begin} ------- */
161
+ .st_rd_rsp_valid ( st_store_rd_rsp_wen ), // i, 1
162
+ .st_rd_rsp_last ( st_store_rd_rsp_last ), // i, 1 ; assert in every last beat of sub-rsp pkt
163
+ .st_rd_rsp_eop ( st_store_rd_rsp_eop ), // i, 1 ; assert when this is the last sub-rsp pkt
164
+ .st_rd_rsp_tag ( st_store_rd_rsp_tag ), // i, `TAG_NUM_LOG
165
+ .st_rd_rsp_blen ( st_store_rd_rsp_blen ), // i, `DMA_LEN_WIDTH
166
+ .st_rd_rsp_data ( st_store_rd_rsp_data ), // i, `DMA_DATA_W
167
+ .st_rd_rsp_ready ( st_store_rd_rsp_rdy ), // o, 1
168
+ /* ------- Store Interface input{end} ------- */
169
+
170
+ /* --------Store Interface Output{begin}-------- */
171
+ .store_fifo_wen ( store_wen ), // o, 1
172
+ .store_fifo_tag ( store_tag ), // o, `TAG_NUM_LOG
173
+ .store_fifo_last ( store_last ), // o, 1 ; assert when this is the last sub-rsp pkt
174
+ .store_fifo_data ( store_data ), // o, `DMA_DATA_W
175
+ .store_fifo_rdy ( store_rdy ) // i, 1
176
+ /* --------Store Interface Output{end}-------- */
177
+
178
+ `ifdef PCIEI_APB_DBG
179
+ /* -------APB reated signal{begin}------- */
180
+ ,.rw_data ( concat_rw_data ) // i, `SRAM_RW_DATA_W
181
+ ,.dbg_signal ( dbg_signal_sub_rsp_concat ) // o, `DATA_FIFO_SIGNAL_W
182
+ /* -------APB reated signal{end}------- */
183
+ `endif
184
+ );
185
+ /* --------concat sub-rsp data{end}-------- */
186
+
187
+
188
+ /* -------data stroage{begin}------- */
189
+ tag_buf tag_buf (
190
+ .dma_clk ( dma_clk ), // i, 1
191
+ .rst_n ( rst_n ), // i, 1
192
+
193
+ /* -------- Store related channel {begin}-------- */
194
+ .store_wen ( store_wen ), // i, 1
195
+ .store_tag ( store_tag ), // i, `TAG_NUM_LOG
196
+ .store_last ( store_last ), // i, 1 ; assert when this is the last sub-rsp pkt
197
+ .store_data ( store_data ), // i, `DMA_DATA_W
198
+ .store_rdy ( store_rdy ), // o, 1
199
+ /* -------- Store related channel {end}-------- */
200
+
201
+ /* -------- Fetch related channel {begin}-------- */
202
+ .fetch_ren ( ft_rd_rsp_ren ), // i, 1
203
+ .fetch_tag ( ft_rd_rsp_tag ), // i, `TAG_NUM_LOG
204
+ .fetch_last ( ft_rd_rsp_last ), // o, 1 ; assert when this is the last sub-rsp pkt
205
+ .fetch_data ( ft_rd_rsp_data ), // o, `DMA_DATA_W
206
+ .fetch_vld ( ft_rd_rsp_vld ) // o, 1
207
+ /* -------- Fetch related channel {end}-------- */
208
+
209
+ `ifdef PCIEI_APB_DBG
210
+ /* -------APB reated signal{begin}------- */
211
+ ,.rw_data ( tag_buf_rw_data ) // i, `SRAM_RW_DATA_W
212
+ ,.dbg_signal ( dbg_signal_tag_buf ) // o, `DATA_FIFO_SIGNAL_W
213
+ /* -------APB reated signal{end}------- */
214
+ `endif
215
+ );
216
+ /* -------data stroage{end}------- */
217
+
218
+ assign ft_rd_rsp_head = {`DMA_HEAD_W{1'd0}};
219
+
220
+ endmodule
ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/DMA/DMA_Read/rrsp_dealign.v ADDED
@@ -0,0 +1,343 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ `timescale 1ns / 100ps
2
+ //*************************************************************************
3
+ // > File Name: rrsp_dealign.v
4
+ // > Author : Kangning
5
+ // > Date : V1.0 -- 2021-04-14
6
+ // > Note : double word dealignment, transfrom data from double word
7
+ // > alignment into address alignment.
8
+ // > V1.0 -- 2021-04-14: Transfrom data from double word
9
+ // > alignment into address alignment. The structure
10
+ // > is as follows:
11
+ // > ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
12
+ // > ^ ^
13
+ // > ^ ########## ########### ^
14
+ // > ^ # #------># tmp_reg # ########### ^
15
+ // > ^ ------># in_reg # ###########-----># # ^
16
+ // > ^ # # # out_reg #----> ^
17
+ // > ^ ##########-----------------------># # ^
18
+ // > ^ ########### ^
19
+ // > ^ ^
20
+ // > ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
21
+ //*************************************************************************
22
+ //`include "../lib/global_include_h.v"
23
+ //`include "../lib/dma_def_h.v"
24
+
25
+ module rrsp_dealign #(
26
+
27
+ ) (
28
+ input wire dma_clk, // i, 1
29
+ input wire rst_n , // i, 1
30
+
31
+
32
+ /* -------axis read response interface{begin}------- */
33
+ /* AXI-Stream read response tuser, interact with read response distributor.
34
+ * Only valid in first beat of a packet
35
+ * | Reserved | REQ CPL | Tag | address | Reserved | DW length | first BE | last BE |
36
+ * | 119:105 | 104 | 103:96 | 95:32 | 31:19 | 18:8 | 7:4 | 3:0 |
37
+ */
38
+ input wire axis_rd_rsp_tvalid, // i, 1
39
+ input wire axis_rd_rsp_tlast , // i, 1
40
+ input wire [`DMA_DATA_W -1:0] axis_rd_rsp_tdata , // i, `DMA_DATA_W
41
+ input wire [`AXIS_TUSER_W-1:0] axis_rd_rsp_tuser , // i, `AXIS_TUSER_W
42
+ input wire [`DMA_KEEP_W -1:0] axis_rd_rsp_tkeep , // i, `DMA_KEEP_W
43
+ output wire axis_rd_rsp_tready, // o, 1
44
+ /* -------axis read response interface{end}------- */
45
+
46
+
47
+ /* ------- Read Response store to Reorder Buffer{begin} ------- */
48
+ /* *_head (interact with <reorder_buffer> module, valid only in first beat of a packet
49
+ * | Reserved | address | Reserved | Byte length |
50
+ * | 127:96 | 95:32 | 31:13 | 12:0 |
51
+ */
52
+ output wire rd_rsp_dealign_valid, // o, 1
53
+ output wire rd_rsp_dealign_last , // o, 1 ; assert in every last beat of sub-rsp pkt
54
+ output wire rd_rsp_dealign_eop , // o, 1 ; assert when this is the last sub-rsp pkt
55
+ output wire[`DW_LEN_WIDTH-1:0] rd_rsp_dealign_dlen , // o, `DW_LEN_WIDTH
56
+ output wire[`TAG_NUM_LOG -1:0] rd_rsp_dealign_tag , // o, `TAG_NUM_LOG
57
+ output wire[`DMA_HEAD_W -1:0] rd_rsp_dealign_head , // o, `DMA_HEAD_W
58
+ output wire[`DMA_DATA_W -1:0] rd_rsp_dealign_data , // o, `DMA_DATA_W
59
+ input wire rd_rsp_dealign_ready // i, 1
60
+ /* ------- Read Response store to Reorder Buffer{end} ------- */
61
+
62
+ `ifdef PCIEI_APB_DBG
63
+ /* -------APB reated signal{begin}------- */
64
+ ,output wire [`RSP_DEALIGN_SIGNAL_W-1:0] dbg_signal // o, `RSP_DEALIGN_SIGNAL_W
65
+ /* -------APB reated signal{end}------- */
66
+ `endif
67
+ );
68
+
69
+ /* -------DW Dealignment FSM{begin}------- */
70
+ localparam IDLE = 3'b001, // This state wait for the first beat of the packet,
71
+ // and store its header.
72
+ RSP_BEAT = 3'b010, // This state caches middle beat of packet.
73
+ LAST_BEAT = 3'b100; // This state caches last beat of packet, in this state,
74
+ // caching new packet beat is not allowed.
75
+
76
+ reg [4:0] cur_state;
77
+ reg [4:0] nxt_state;
78
+
79
+ wire is_idle, is_rsp_beat, is_last_beat;
80
+ /* -------DW Dealignment FSM{end}------- */
81
+
82
+ /* -------Relate to head generation{begin}------- */
83
+ wire [`AXIS_TUSER_W-1:0] axis_rd_rsp_thead;
84
+
85
+ // axis axis_rd_rsp_tuser
86
+ // wire [`TAG_WIDTH -1:0] tag ;
87
+ wire [`DMA_ADDR_WIDTH-1:0] addr_align ;
88
+ wire [`DW_LEN_WIDTH -1:0] axis_dw_len;
89
+ wire [`FIRST_BE_WIDTH-1:0] first_be ;
90
+ wire [`LAST_BE_WIDTH -1:0] last_be ;
91
+
92
+ // relate to sub_req_rsp_head
93
+ wire [1:0] first_empty ; // Number of invalid bytes in first Double word
94
+ wire [1:0] last_empty ; // Number of invalid bytes in last Double word
95
+
96
+ wire [`DMA_ADDR_WIDTH-1:0] addr_unalign;
97
+ wire [`DMA_LEN_WIDTH -1:0] byte_len ;
98
+
99
+ wire rd_rsp_dealign_next_last; // Indicate that in next cycle, rd_rsp_dealign_last asserted
100
+
101
+ wire [5:0] axis_beats_total;
102
+ wire [5:0] dealign_beats_total;
103
+ reg [5:0] dealign_beats_left; // The number of beats left to trans (not including the beat of this cycle)
104
+
105
+ reg is_aligned_last; // Indicate that this pkt is a aligned pkt, whose out_last (rd_rsp_dealigned_*)
106
+ // asserts at the same time when in_last (axis_rd_rsp_*) asserts
107
+ /* -------Relate to head generation{end}------- */
108
+
109
+ // in reg is used to cache input axis data.
110
+ /* -------relate to in_reg{begin}------- */
111
+ wire in_reg_tvalid; // read valid from input register
112
+ wire in_reg_tlast;
113
+ wire [`AXIS_TUSER_W-1:0] in_reg_tuser;
114
+ wire [`DMA_DATA_W -1:0] in_reg_tdata;
115
+ wire in_reg_tready;
116
+ /* -------relate to in_reg{end}------- */
117
+
118
+ /* -------relate to out_reg{begin}------- */
119
+ // reg [`DMA_LEN_WIDTH-1:0] byte_cnt_down;
120
+
121
+ reg [`DMA_DATA_W-1:0] in_out_data; // transform data between tmp_reg and out_reg
122
+ /* -------relate to tmp_reg{end}------- */
123
+
124
+ /* All these signals are valid in the entire trans peroid of packet */
125
+ wire is_eop;
126
+ wire [`DW_LEN_WIDTH-1:0] dw_len;
127
+ wire [`TAG_WIDTH -1:0] tag ;
128
+
129
+ /* --------------------------------------------------------------------------------------- */
130
+
131
+ `ifdef PCIEI_APB_DBG
132
+ /* -------APB reated signal{begin}------- */
133
+ assign dbg_signal = { // 988
134
+ cur_state, nxt_state, // 10
135
+ is_idle, is_rsp_beat, is_last_beat, // 3
136
+ axis_rd_rsp_thead, // 128
137
+ is_eop, addr_align , axis_dw_len, first_be, last_be, // 83
138
+ first_empty, last_empty, // 4
139
+ addr_unalign, byte_len, // 77
140
+ rd_rsp_dealign_next_last, // 1
141
+ axis_beats_total, dealign_beats_total, dealign_beats_left, // 18
142
+ is_aligned_last, // 1
143
+ in_reg_tvalid, in_reg_tlast, in_reg_tuser, in_reg_tdata, in_reg_tready, // 387
144
+ in_out_data, // 256
145
+ is_eop, dw_len, tag // 20
146
+ };
147
+ /* -------APB reated signal{end}------- */
148
+ `endif
149
+
150
+ st_reg #(
151
+ .TUSER_WIDTH ( `AXIS_TUSER_W ),
152
+ .TDATA_WIDTH ( `DMA_DATA_W ),
153
+ .MODE ( 1 )
154
+ ) in_reg (
155
+ .clk ( dma_clk ), // i, 1
156
+ .rst_n ( rst_n ), // i, 1
157
+
158
+ /* -------input axis-like interface{begin}------- */
159
+ .axis_tvalid ( axis_rd_rsp_tvalid ), // i, 1
160
+ .axis_tlast ( axis_rd_rsp_tlast ), // i, 1
161
+ .axis_tuser ( axis_rd_rsp_thead ), // i, TUSER_WIDTH
162
+ .axis_tdata ( axis_rd_rsp_tdata ), // i, `DMA_DATA_W
163
+ .axis_tready ( axis_rd_rsp_tready ), // o, 1
164
+ /* -------input axis-like interface{end}------- */
165
+
166
+ /* -------output in_reg inteface{begin}------- */
167
+ .axis_reg_tvalid ( in_reg_tvalid ), // o, 1
168
+ .axis_reg_tlast ( in_reg_tlast ), // o, 1
169
+ .axis_reg_tuser ( in_reg_tuser ), // o, TUSER_WIDTH
170
+ .axis_reg_tdata ( in_reg_tdata ), // o, `DMA_DATA_W
171
+ .axis_reg_tready ( in_reg_tready ) // i, 1
172
+ /* -------output in_reg inteface{end}------- */
173
+ );
174
+
175
+ /* -------DW Dealignment FSM{begin}------- */
176
+ /******************** Stage 1: State Register **********************/
177
+
178
+ assign is_idle = (cur_state == IDLE );
179
+ assign is_rsp_beat = (cur_state == RSP_BEAT );
180
+ assign is_last_beat = (cur_state == LAST_BEAT);
181
+
182
+ always @(posedge dma_clk, negedge rst_n) begin
183
+ if(~rst_n)
184
+ cur_state <= `TD IDLE;
185
+ else
186
+ cur_state <= `TD nxt_state;
187
+ end
188
+
189
+ /******************** Stage 2: State Transition **********************/
190
+
191
+ always @(*) begin
192
+ case(cur_state)
193
+ IDLE: begin
194
+ if (axis_rd_rsp_tvalid & rd_rsp_dealign_next_last) begin
195
+ nxt_state = LAST_BEAT;
196
+ end
197
+ else if (axis_rd_rsp_tvalid) begin
198
+ nxt_state = RSP_BEAT;
199
+ end
200
+ else begin
201
+ nxt_state = IDLE;
202
+ end
203
+ end
204
+ RSP_BEAT: begin
205
+ if (axis_rd_rsp_tvalid && axis_rd_rsp_tready && rd_rsp_dealign_next_last) begin
206
+ nxt_state = LAST_BEAT;
207
+ end
208
+ else begin
209
+ nxt_state = RSP_BEAT;
210
+ end
211
+ end
212
+ LAST_BEAT: begin
213
+ if (rd_rsp_dealign_valid & rd_rsp_dealign_ready & rd_rsp_dealign_last) begin
214
+ if (axis_rd_rsp_tvalid & axis_rd_rsp_tready & is_aligned_last) begin
215
+ nxt_state = IDLE;
216
+ end
217
+ else if (axis_rd_rsp_tvalid & axis_rd_rsp_tready & rd_rsp_dealign_next_last) begin
218
+ nxt_state = LAST_BEAT;
219
+ end
220
+ else if (axis_rd_rsp_tvalid & axis_rd_rsp_tready) begin
221
+ nxt_state = RSP_BEAT;
222
+ end
223
+ else begin
224
+ nxt_state = IDLE;
225
+ end
226
+ end
227
+ else begin
228
+ nxt_state = LAST_BEAT;
229
+ end
230
+ end
231
+ default: begin
232
+ nxt_state = IDLE;
233
+ end
234
+ endcase
235
+ end
236
+ /******************** Stage 3: Output **********************/
237
+
238
+ assign in_reg_tready = (rd_rsp_dealign_valid & rd_rsp_dealign_ready) | is_idle;
239
+
240
+ /* -------DW Dealignment FSM{end}------- */
241
+
242
+
243
+ /* -------next_last{begin}------- */
244
+ assign rd_rsp_dealign_next_last = (is_idle & (dealign_beats_total == 1)) | // Asserts when next pkt has only one beat
245
+ (is_rsp_beat & (dealign_beats_left == 1)) | // Asserts when this pkt forward last beat next cycle.
246
+ (is_last_beat & !is_aligned_last & (dealign_beats_total == 1)); // Asserts when next pkt has only one beat
247
+
248
+
249
+ /* -------next_last{end}------- */
250
+
251
+ /* -------Head generation{begin}------- */
252
+
253
+ assign addr_align = axis_rd_rsp_tuser[95 :32];
254
+ assign axis_dw_len = axis_rd_rsp_tuser[18 : 8];
255
+ assign first_be = axis_rd_rsp_tuser[7 : 4];
256
+ assign last_be = axis_rd_rsp_tuser[3 : 0];
257
+
258
+ assign first_empty = first_be[0] ? 2'd0 :
259
+ first_be[1] ? 2'd1 :
260
+ first_be[2] ? 2'd2 :
261
+ first_be[3] ? 2'd3 :
262
+ 2'd0; // unlikely
263
+ assign last_empty = (axis_dw_len == 1) ?
264
+ (first_be[3] ? 2'd0 :
265
+ first_be[2] ? 2'd1 :
266
+ first_be[1] ? 2'd2 : 2'd3) :
267
+ ({2{(last_be == 4'b1111)}} & 2'd0 |
268
+ {2{(last_be == 4'b0001)}} & 2'd3 |
269
+ {2{(last_be == 4'b0011)}} & 2'd2 |
270
+ {2{(last_be == 4'b0111)}} & 2'd1);
271
+
272
+ assign addr_unalign = {addr_align[`DMA_ADDR_WIDTH-1:2], first_empty};
273
+ assign byte_len = (axis_dw_len << 2) - first_empty - last_empty;
274
+
275
+ assign dealign_beats_total = byte_len[`DMA_LEN_WIDTH-1:5] + (|byte_len[4:0]);
276
+ assign axis_beats_total = axis_dw_len[`DW_LEN_WIDTH-1:3] + (|axis_dw_len[2:0]);
277
+
278
+ always @(posedge dma_clk, negedge rst_n) begin
279
+ if (~rst_n) begin
280
+ dealign_beats_left <= `TD 0;
281
+ is_aligned_last <= `TD 0;
282
+ end
283
+ else if (is_idle & axis_rd_rsp_tvalid & axis_rd_rsp_tready) begin
284
+ dealign_beats_left <= `TD dealign_beats_total - 1;
285
+ is_aligned_last <= `TD axis_beats_total > dealign_beats_total; // (first_empty > 0) & (first_empty + byte_len[4:0] > 0) & (first_empty + byte_len[4:0] <= 3);
286
+ end
287
+ else if (is_rsp_beat & axis_rd_rsp_tvalid & axis_rd_rsp_tready) begin
288
+ dealign_beats_left <= `TD dealign_beats_left - 1;
289
+ end
290
+ else if (is_last_beat & axis_rd_rsp_tvalid & axis_rd_rsp_tready & !is_aligned_last) begin
291
+ dealign_beats_left <= `TD dealign_beats_total - 1;
292
+ is_aligned_last <= `TD axis_beats_total > dealign_beats_total;
293
+ end
294
+ else if (is_last_beat & axis_rd_rsp_tvalid & axis_rd_rsp_tready & is_aligned_last) begin
295
+ dealign_beats_left <= `TD 0;
296
+ is_aligned_last <= `TD 0;
297
+ end
298
+ end
299
+
300
+ /* AXI-Stream read response tuser
301
+ * | Reserved | REQ CPL | first_empty | Tag | address | Reserved | DW length | byte length |
302
+ * | 127:107 | 106 | 105:104 | 103:96 | 95:32 | 31:24 | 23:13 | 12:0 |
303
+ */
304
+ assign axis_rd_rsp_thead = {22'd0, axis_rd_rsp_tuser[104], first_empty, axis_rd_rsp_tuser[103:96], addr_unalign, 8'd0, axis_dw_len, byte_len};
305
+ /* -------Head Generation{end}------- */
306
+
307
+ /* -------out_reg logic{begin}------- */
308
+ assign rd_rsp_dealign_valid = (is_rsp_beat & axis_rd_rsp_tvalid & in_reg_tvalid) |
309
+ (is_last_beat & !is_aligned_last & in_reg_tvalid) |
310
+ (is_last_beat & is_aligned_last & axis_rd_rsp_tvalid & in_reg_tvalid);
311
+ assign rd_rsp_dealign_head = rd_rsp_dealign_valid ? {32'd0, in_reg_tuser[95:32], {32-`DMA_LEN_WIDTH{1'd0}}, in_reg_tuser[12:0]} : 0;
312
+ assign rd_rsp_dealign_dlen = dw_len;
313
+ assign rd_rsp_dealign_tag = tag;
314
+ assign rd_rsp_dealign_data = in_out_data;
315
+ assign rd_rsp_dealign_last = rd_rsp_dealign_valid & is_last_beat;
316
+ assign rd_rsp_dealign_eop = rd_rsp_dealign_last & is_eop;
317
+
318
+ // Refers to axis_rd_rsp_thead
319
+ assign is_eop = in_reg_tuser[106];
320
+ assign dw_len = in_reg_tuser[23:13];
321
+ assign tag = in_reg_tuser[103:96];
322
+
323
+
324
+ always @(*) begin
325
+ if (is_last_beat & !is_aligned_last) begin
326
+ in_out_data = (in_reg_tdata >> {in_reg_tuser[105:104], 3'd0});
327
+ end
328
+ else if (is_rsp_beat | (is_last_beat & is_aligned_last)) begin
329
+ case (in_reg_tuser[105:104])
330
+ 2'd0: in_out_data = in_reg_tdata; // pkt_aligned
331
+ 2'd1: in_out_data = {axis_rd_rsp_tdata[8 * 1 - 1 : 0], in_reg_tdata[`DMA_DATA_W-1 : 8 * 1]};
332
+ 2'd2: in_out_data = {axis_rd_rsp_tdata[8 * 2 - 1 : 0], in_reg_tdata[`DMA_DATA_W-1 : 8 * 2]};
333
+ 2'd3: in_out_data = {axis_rd_rsp_tdata[8 * 3 - 1 : 0], in_reg_tdata[`DMA_DATA_W-1 : 8 * 3]};
334
+ endcase
335
+ end
336
+ else begin
337
+ in_out_data = 0;
338
+ end
339
+ end
340
+ /* -------out_reg logic{end}------- */
341
+
342
+
343
+ endmodule
ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/DMA/DMA_Read/rsp_data_fifo.v ADDED
@@ -0,0 +1,222 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ `timescale 1ns / 100ps
2
+ //*************************************************************************
3
+ // > File Name: rsp_data_fifo.v
4
+ // > Author : Kangning
5
+ // > Date : 2020-11-15
6
+ // > Note : rsp_data_fifo, store and concat multi-pkts into one message.
7
+ // Note that the fifo could store more than one message.
8
+ // > ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
9
+ // > ^ ^
10
+ // > ^ ########## ########### ^
11
+ // > ^ # #------># tmp_reg # ########### ^
12
+ // > ^ ------># in_reg # ###########-----># # ^
13
+ // > ^ # # #data_fifo#----> ^
14
+ // > ^ ##########-----------------------># # ^
15
+ // > ^ ########### ^
16
+ // > ^ ^
17
+ // > ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
18
+ //*************************************************************************
19
+
20
+ module rsp_data_fifo #(
21
+
22
+ ) (
23
+ input wire dma_clk, // i, 1
24
+ input wire rst_n , // i, 1
25
+
26
+ /* ------- sub_req rsp input{begin} ------- */
27
+ input wire sub_req_rsp_valid, // i, 1
28
+ input wire sub_req_rsp_last , // i, 1; indicate the last cycle of the whole req rsp
29
+ input wire [`DMA_LEN_WIDTH-1:0] sub_req_rsp_blen , // i, `DMA_LEN_WIDTH; blen for every cycle
30
+ input wire [`DMA_DATA_W -1:0] sub_req_rsp_data , // i, `DMA_DATA_W
31
+ output wire sub_req_rsp_ready, // o, 1
32
+ /* ------- sub_req rsp input{end} ------- */
33
+
34
+ /* ------- rsp output{begin} ------- */
35
+ output wire req_rsp_valid, // o, 1
36
+ output wire [`DMA_DATA_W-1:0] req_rsp_data , // o, `DMA_DATA_W
37
+ input wire req_rsp_ready // i, 1
38
+ /* ------- rsp output{end} ------- */
39
+
40
+ `ifdef PCIEI_APB_DBG
41
+ /* -------APB reated signal{begin}------- */
42
+ ,input wire [`SRAM_RW_DATA_W-1:0] rw_data// i, `SRAM_RW_DATA_W
43
+ ,output wire [`DATA_FIFO_SIGNAL_W-1:0] dbg_signal // o, `DATA_FIFO_SIGNAL_W
44
+ /* -------APB reated signal{end}------- */
45
+ `endif
46
+ );
47
+
48
+ /* -------in_reg{begin}------- */
49
+ wire in_reg_valid;
50
+ wire in_reg_last ;
51
+ wire [`DMA_LEN_WIDTH-1:0] in_reg_blen ;
52
+ wire [`DMA_DATA_W -1:0] in_reg_data ;
53
+ wire in_reg_ready;
54
+ /* -------in_reg{end}------- */
55
+
56
+ /* -------tmp_reg{begin}------- */
57
+ wire in_tmp_valid;
58
+ wire in_tmp_last ;
59
+ wire [`DMA_LEN_WIDTH-1:0] in_tmp_blen ;
60
+ wire [`DMA_DATA_W -1:0] in_tmp_data ;
61
+ wire in_tmp_ready;
62
+
63
+ wire [`DMA_LEN_WIDTH :0] avail_bytes;
64
+ wire [`DMA_DATA_W -1:0] concat_tmp_data;
65
+
66
+ wire tmp_reg_valid;
67
+ wire tmp_reg_last ;
68
+ wire [`DMA_LEN_WIDTH-1:0] tmp_reg_blen ;
69
+ wire [`DMA_DATA_W -1:0] tmp_reg_data ;
70
+ wire tmp_reg_ready;
71
+ /* -------tmp_reg{end}------- */
72
+
73
+ /* -------data fifo{begin}------- */
74
+ wire is_msg_eop;
75
+
76
+ wire in_fifo_wen ;
77
+ wire [`DMA_DATA_W-1:0] in_fifo_data;
78
+ wire in_fifo_full;
79
+
80
+ wire out_fifo_ren ;
81
+ wire [`DMA_DATA_W-1:0] out_fifo_data ;
82
+ wire out_fifo_empty;
83
+ /* -------data fifo{end}------- */
84
+
85
+ `ifdef PCIEI_APB_DBG
86
+ /* -------APB reated signal{begin}------- */
87
+ wire [1:0] rtsel;
88
+ wire [1:0] wtsel;
89
+ wire [1:0] ptsel;
90
+ wire vg ;
91
+ wire vs ;
92
+ /* -------APB reated signal{end}------- */
93
+ `endif
94
+
95
+ //---------------------------------------------------------------------------------------------------------------------------
96
+
97
+ `ifdef PCIEI_APB_DBG
98
+ /* -------APB reated signal{begin}------- */
99
+ assign {rtsel, wtsel, ptsel, vg, vs} = rw_data;
100
+ assign dbg_signal = { // 1602
101
+ in_reg_valid, in_reg_last , in_reg_blen , in_reg_data , in_reg_ready, // 272
102
+ in_tmp_valid, in_tmp_last , in_tmp_blen , in_tmp_data , in_tmp_ready, // 272
103
+ avail_bytes, concat_tmp_data, // 269
104
+ tmp_reg_valid, tmp_reg_last, tmp_reg_blen, tmp_reg_data, tmp_reg_ready, // 272
105
+ is_msg_eop, // 1
106
+ in_fifo_wen, in_fifo_data, in_fifo_full, // 258
107
+ out_fifo_ren, out_fifo_data, out_fifo_empty // 258
108
+ };
109
+ /* -------APB reated signal{end}------- */
110
+ `endif
111
+
112
+ /* -------in_reg{begin}------- */
113
+ st_reg #(
114
+ .TUSER_WIDTH ( 1 ),
115
+ .TDATA_WIDTH ( `DMA_DATA_W + `DMA_LEN_WIDTH )
116
+ ) in_st_reg (
117
+ .clk ( dma_clk ), // i, 1
118
+ .rst_n ( rst_n ), // i, 1
119
+
120
+ /* -------input axis-like interface{begin}------- */
121
+ .axis_tvalid ( sub_req_rsp_valid ), // i, 1
122
+ .axis_tlast ( sub_req_rsp_last ), // i, 1
123
+ .axis_tuser ( 1'd0 ), // i, TUSER_WIDTH
124
+ .axis_tdata ( {sub_req_rsp_blen, sub_req_rsp_data} ), // i, TDATA_WIDTH
125
+ .axis_tready ( sub_req_rsp_ready ), // o, 1
126
+ /* -------input axis-like interface{end}------- */
127
+
128
+ /* -------output in_reg inteface{begin}------- */
129
+ .axis_reg_tvalid ( in_reg_valid ), // o, 1
130
+ .axis_reg_tlast ( in_reg_last ), // o, 1
131
+ .axis_reg_tuser ( ), // o, TUSER_WIDTH
132
+ .axis_reg_tdata ( {in_reg_blen, in_reg_data} ), // o, TDATA_WIDTH
133
+ .axis_reg_tready ( in_reg_ready ) // i, 1
134
+ /* -------output in_reg inteface{end}------- */
135
+ );
136
+
137
+ assign in_reg_ready = !in_fifo_full & !is_msg_eop; // & tmp_reg_valid
138
+ /* -------in_reg{end}------- */
139
+
140
+ /* -------tmp_reg{begin}------- */
141
+ assign in_tmp_valid = in_reg_valid & in_reg_ready & (avail_bytes != `DMA_W_BCNT);
142
+ assign in_tmp_last = in_reg_last & (avail_bytes != `DMA_W_BCNT);
143
+ assign in_tmp_blen = (avail_bytes < `DMA_W_BCNT) ? avail_bytes :
144
+ (avail_bytes == `DMA_W_BCNT) ? {`DMA_LEN_WIDTH{1'b0}} :
145
+ (avail_bytes > `DMA_W_BCNT) ? (avail_bytes - `DMA_W_BCNT) : {`DMA_LEN_WIDTH{1'b0}};
146
+ assign in_tmp_data = (avail_bytes < `DMA_W_BCNT) ? concat_tmp_data :
147
+ (avail_bytes == `DMA_W_BCNT) ? {`DMA_DATA_W{1'b0}} :
148
+ (avail_bytes > `DMA_W_BCNT) ? (in_reg_data >> ((`DMA_W_BCNT - tmp_reg_blen) << 3)) : {`DMA_DATA_W{1'b0}};
149
+
150
+ assign avail_bytes = (is_msg_eop ? {`DMA_LEN_WIDTH{1'b0}} : tmp_reg_blen) + in_reg_blen;
151
+ assign concat_tmp_data = (in_reg_data << (tmp_reg_blen << 3)) | (tmp_reg_data); // & ((1 << (tmp_reg_blen << 3))-1)
152
+
153
+ st_reg #(
154
+ .TUSER_WIDTH ( 1 ),
155
+ .TDATA_WIDTH ( `DMA_LEN_WIDTH + `DMA_DATA_W )
156
+ ) tmp_st_reg (
157
+ .clk ( dma_clk ), // i, 1
158
+ .rst_n ( rst_n ), // i, 1
159
+
160
+ /* -------input axis-like interface{begin}------- */
161
+ .axis_tvalid ( in_tmp_valid ), // i, 1
162
+ .axis_tlast ( in_tmp_last ), // i, 1
163
+ .axis_tuser ( 1'd0 ), // i, TUSER_WIDTH
164
+ .axis_tdata ( {in_tmp_blen, in_tmp_data} ), // i, TDATA_WIDTH
165
+ .axis_tready ( in_tmp_ready ), // o, 1
166
+ /* -------input axis-like interface{end}------- */
167
+
168
+ /* -------output st_reg inteface{begin}------- */
169
+ .axis_reg_tvalid ( tmp_reg_valid ), // o, 1
170
+ .axis_reg_tlast ( tmp_reg_last ), // o, 1
171
+ .axis_reg_tuser ( ), // o, TUSER_WIDTH
172
+ .axis_reg_tdata ( {tmp_reg_blen, tmp_reg_data} ), // o, TDATA_WIDTH
173
+ .axis_reg_tready ( tmp_reg_ready ) // i, 1
174
+ /* -------output st_reg inteface{end}------- */
175
+ );
176
+ /*
177
+ * Assert when fifo is not full && there's bytes in tem_reg (tem_reg_blen != 0) && (
178
+ * 1. in_reg data is valid ||
179
+ * 2. The last cycle of the message, draining the last cycle
180
+ * )
181
+ */
182
+ assign tmp_reg_ready = !in_fifo_full & (in_reg_valid | is_msg_eop);
183
+ /* -------tmp_reg{end}------- */
184
+
185
+ /* -------data fifo{begin}------- */
186
+ assign is_msg_eop = (tmp_reg_valid & tmp_reg_last & tmp_reg_blen != 0);
187
+
188
+ assign in_fifo_wen = (in_reg_valid & (avail_bytes >= `DMA_W_BCNT))| is_msg_eop;
189
+ assign in_fifo_data = is_msg_eop ? tmp_reg_data : concat_tmp_data;
190
+ pcieifc_sync_fifo #(
191
+ .DSIZE ( `DMA_DATA_W ), // 256
192
+ .ASIZE ( `RSP_FIFO_DEPTH_LOG ) // 4KB payload capacity
193
+ ) data_fifo (
194
+ .clk ( dma_clk ), // i, 1
195
+ .rst_n ( rst_n ), // i, 1
196
+ .clr ( 1'd0 ), // i, 1
197
+
198
+ .wen ( in_fifo_wen ), // i, 1
199
+ .din ( in_fifo_data ), // i, DSIZE
200
+ .full ( in_fifo_full ), // o, 1
201
+
202
+ .ren ( out_fifo_ren ), // i, 1
203
+ .dout ( out_fifo_data ), // o, DSIZE
204
+ .empty ( out_fifo_empty ) // o, 1
205
+
206
+ `ifdef PCIEI_APB_DBG
207
+ ,.rtsel ( rtsel ) // i, 2
208
+ ,.wtsel ( wtsel ) // i, 2
209
+ ,.ptsel ( ptsel ) // i, 2
210
+ ,.vg ( vg ) // i, 1
211
+ ,.vs ( vs ) // i, 1
212
+ `endif
213
+ );
214
+ assign out_fifo_ren = req_rsp_valid & req_rsp_ready;
215
+ /* -------data fifo{end}------- */
216
+
217
+ /* ------- rsp output{begin} ------- */
218
+ assign req_rsp_valid = !out_fifo_empty;
219
+ assign req_rsp_data = out_fifo_data;
220
+ /* ------- rsp output{end} ------- */
221
+
222
+ endmodule
ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/DMA/DMA_Read/sub_req_rsp_concat.v ADDED
@@ -0,0 +1,363 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ `timescale 1ns / 100ps
2
+ //*************************************************************************
3
+ // > File Name: sub_req_rsp_concat.v
4
+ // > Author : Kangning
5
+ // > Date : 2020-09-24
6
+ // > Note : sub_req_rsp_concat, used to reassemble sub-request according
7
+ // > to Max_Read_Request_Size.
8
+ //*************************************************************************
9
+
10
+ module sub_req_rsp_concat #(
11
+ parameter HEAD_DEPTH_LOG = 6
12
+ ) (
13
+ input wire dma_clk, // i, 1
14
+ input wire rst_n , // i, 1
15
+
16
+ /* -------response emission{begin}------- */
17
+ input wire emit, // i, 1 ; high active
18
+ /* -------response emission{end}------- */
19
+
20
+ /* ------- Read Response from <read_response> module{begin} ------- */
21
+ /* *_head (interact with RDMA modules, through an async fifo), valid only in first beat of a packet
22
+ * | Reserved | address | Reserved | Byte length |
23
+ * | 127:96 | 95:32 | 31:13 | 12:0 |
24
+ */
25
+ input wire rd_sub_req_rsp_valid, // i, 1
26
+ input wire rd_sub_req_rsp_last , // i, 1
27
+ input wire [`DMA_DATA_W-1:0] rd_sub_req_rsp_data , // i, `DMA_DATA_W
28
+ input wire [`DMA_HEAD_W-1:0] rd_sub_req_rsp_head , // i, `DMA_HEAD_W
29
+ output wire rd_sub_req_rsp_ready, // o, 1
30
+
31
+ output reg is_avail, // o, 1
32
+ /* ------- Read Response from <read_response> module{end} ------- */
33
+
34
+ /* ------- Read Response to RDMA Engine{begin} ------- */
35
+ /* *_head (interact with RDMA modules, through an async fifo), valid only in first beat of a packet
36
+ * | Reserved | address | Reserved | Byte length |
37
+ * | 127:96 | 95:32 | 31:13 | 12:0 |
38
+ */
39
+ output wire rd_rsp_valid, // o, 1
40
+ output wire rd_rsp_last , // o, 1
41
+ output wire [`DMA_DATA_W-1:0] rd_rsp_data , // o, `DMA_DATA_W
42
+ output wire [`DMA_HEAD_W-1:0] rd_rsp_head , // o, `DMA_HEAD_W
43
+ input wire rd_rsp_ready, // i, 1
44
+ /* ------- Read Response to RDMA Engine{end} ------- */
45
+
46
+ /* -------PCIe fragment property{begin}------- */
47
+ /* This signal indicates the (max payload size & max read request size) agreed in the communication
48
+ * 3'b000 -- 128 B
49
+ * 3'b001 -- 256 B
50
+ * 3'b010 -- 512 B
51
+ * 3'b011 -- 1024B
52
+ * 3'b100 -- 2048B
53
+ * 3'b101 -- 4096B
54
+ */
55
+ input wire [2:0] max_pyld_sz ,
56
+ input wire [2:0] max_rd_req_sz // max read request size
57
+ /* -------PCIe fragment property{end}------- */
58
+
59
+ `ifdef PCIEI_APB_DBG
60
+ /* -------APB reated signal{begin}------- */
61
+ ,input wire [`SRAM_RW_DATA_W-1:0] rw_data // i, `SRAM_RW_DATA_W
62
+ ,output wire [`RSP_CONCAT_SIGNAL_W-1:0] dbg_signal // o, `RSP_CONCAT_SIGNAL_W
63
+ /* -------APB reated signal{end}------- */
64
+ `endif
65
+ );
66
+
67
+ /* --------Head FIFO{begin}-------- */
68
+ reg is_sub_head_sop;
69
+ reg is_head_sop;
70
+ reg [`DMA_ADDR_WIDTH-1:0] hd_addr;
71
+ reg [`DMA_LEN_WIDTH -1:0] hd_byte_len;
72
+ wire [`DMA_LEN_WIDTH -1:0] nxt_byte_len;
73
+
74
+ wire only_req_rsp_sop ;
75
+ wire last_sub_req_rsp_sop; // sop of last sub_req rsp
76
+ wire last_sub_req_rsp_eop; // eop of last sub_req rsp
77
+
78
+ wire head_in_valid;
79
+ wire [`DMA_HEAD_W-1:0] head_in_head ;
80
+ wire head_in_ready;
81
+ wire head_in_full ;
82
+
83
+ wire head_out_valid;
84
+ wire [`DMA_HEAD_W-1:0] head_out_head ;
85
+ wire head_out_ready;
86
+ wire head_out_empty;
87
+ /* --------Head FIFO{end}-------- */
88
+
89
+ /* --------prog_full{begin}--------- */
90
+ /* The inputt is blocked caused by :
91
+ * 1. data_rsp_fifo cannot accept new pkt;
92
+ * 2. head_store_fifo cannot store new head. */
93
+ wire is_input_blocked;
94
+ wire fifo_prog_full;
95
+ wire [`DW_LEN_WIDTH-1:0] max_rd_req_cycle_num; // The maximum read request in dw unit
96
+ wire [`DMA_LEN_WIDTH-5-1:0] fifo_cycle_cnt;
97
+ reg [`DMA_LEN_WIDTH -1:0] fifo_byte_cnt;
98
+ wire [`DMA_LEN_WIDTH -1:0] nxt_fifo_byte_cnt, fifo_in_inc, fifo_out_dec;
99
+ /* --------prog_full{end}--------- */
100
+
101
+ /* --------Data FIFO{begin}-------- */
102
+ wire sub_req_rsp_valid;
103
+ wire sub_req_rsp_last ;
104
+ wire sub_req_rsp_eop ; // End of the req rsp msg
105
+ wire [`DMA_DATA_W -1:0] sub_req_rsp_data ;
106
+ wire [`DMA_LEN_WIDTH-1:0] sub_req_rsp_blen ;
107
+ wire [`DMA_HEAD_W -1:0] sub_req_rsp_head ;
108
+ wire sub_req_rsp_ready;
109
+
110
+ wire [`DMA_LEN_WIDTH -1:0] sub_blen_total;
111
+ wire [`DMA_LEN_WIDTH -1:0] sub_blen_left ;
112
+ reg [`DMA_LEN_WIDTH -1:0] in_trans_cnt ;
113
+
114
+ wire [`DMA_LEN_WIDTH -1:0] out_blen_total;
115
+ wire [`DMA_LEN_WIDTH -1:0] out_blen_left ;
116
+ reg [`DMA_LEN_WIDTH -1:0] out_trans_cnt ;
117
+
118
+ wire req_rsp_valid;
119
+ wire req_rsp_last ;
120
+ wire [`DMA_DATA_W-1:0] req_rsp_data ;
121
+ wire req_rsp_ready;
122
+ /* --------Data FIFO{end}-------- */
123
+
124
+ `ifdef PCIEI_APB_DBG
125
+ /* -------APB reated signal{begin}------- */
126
+ wire [`DATA_FIFO_SIGNAL_W-1:0] dbg_signal_data_fifo;
127
+ /* -------APB reated signal{end}------- */
128
+ `endif
129
+
130
+ //-----------------------------------------------------------------------------------------------------------------
131
+
132
+ `ifdef PCIEI_APB_DBG
133
+ /* -------APB reated signal{begin}------- */
134
+ assign dbg_signal = { // 2770
135
+ is_sub_head_sop, is_head_sop, // 2
136
+ hd_addr, hd_byte_len, nxt_byte_len, // 90
137
+ only_req_rsp_sop, last_sub_req_rsp_sop, last_sub_req_rsp_eop, // 3
138
+ head_in_valid, head_in_head , head_in_ready, head_in_full , // 131
139
+ head_out_valid, head_out_head , head_out_ready, head_out_empty, // 131
140
+ is_input_blocked, fifo_prog_full, // 2
141
+ max_rd_req_cycle_num, // 11
142
+ fifo_cycle_cnt, // 8
143
+ fifo_byte_cnt, // 13
144
+ nxt_fifo_byte_cnt, fifo_in_inc, fifo_out_dec, // 39
145
+ sub_req_rsp_valid, sub_req_rsp_last, sub_req_rsp_eop, sub_req_rsp_data, sub_req_rsp_blen, sub_req_rsp_head, sub_req_rsp_ready, // 401
146
+ sub_blen_total, sub_blen_left , in_trans_cnt , // 39
147
+ out_blen_total, out_blen_left , out_trans_cnt , // 39
148
+ req_rsp_valid, req_rsp_last , req_rsp_data , req_rsp_ready, // 259
149
+ dbg_signal_data_fifo // 1602
150
+ };
151
+ /* -------APB reated signal{end}------- */
152
+ `endif
153
+
154
+ /* --------Head FIFO{begin}-------- */
155
+ // start of sub_req rsp pkt
156
+ always @(posedge dma_clk, negedge rst_n) begin
157
+ if (~rst_n) begin
158
+ is_sub_head_sop <= `TD 1'b1;
159
+ end
160
+ else if (sub_req_rsp_valid & sub_req_rsp_ready & sub_req_rsp_last) begin
161
+ is_sub_head_sop <= `TD 1'b1;
162
+ end
163
+ else if (sub_req_rsp_valid & sub_req_rsp_ready) begin // invalid after the first cycle
164
+ is_sub_head_sop <= `TD 1'b0;
165
+ end
166
+ end
167
+
168
+ // start of req rsp pkt
169
+ always @(posedge dma_clk, negedge rst_n) begin
170
+ if (~rst_n) begin
171
+ is_head_sop <= `TD 1'b1;
172
+ end
173
+ else if (sub_req_rsp_valid & sub_req_rsp_ready & sub_req_rsp_last & emit) begin
174
+ is_head_sop <= `TD 1'b1;
175
+ end
176
+ else if (sub_req_rsp_valid & sub_req_rsp_ready) begin // invalid after the first cycle
177
+ is_head_sop <= `TD 1'b0;
178
+ end
179
+ end
180
+
181
+ always @(posedge dma_clk, negedge rst_n) begin
182
+ if (~rst_n) begin
183
+ hd_addr <= `TD 0;
184
+ end
185
+ else if (sub_req_rsp_valid & sub_req_rsp_ready & is_head_sop) begin // first cycle of req rsp
186
+ hd_addr <= `TD sub_req_rsp_head[95:32];
187
+ end
188
+ else if (last_sub_req_rsp_eop) begin // last cycle of last sub_req rsp
189
+ hd_addr <= `TD 0;
190
+ end
191
+ end
192
+
193
+ always @(posedge dma_clk, negedge rst_n) begin
194
+ if (~rst_n) begin
195
+ hd_byte_len <= `TD 0;
196
+ end
197
+ else if (sub_req_rsp_valid & sub_req_rsp_ready & is_head_sop) begin // first cycle of req rsp
198
+ hd_byte_len <= `TD sub_req_rsp_head[12:0];
199
+ end
200
+ else if (sub_req_rsp_valid & sub_req_rsp_ready & is_sub_head_sop) begin // first cycle of middle & last sub_req rsp
201
+ hd_byte_len <= `TD nxt_byte_len;
202
+ end
203
+ else if (last_sub_req_rsp_eop) begin // last cycle of last sub_req rsp
204
+ hd_byte_len <= `TD 0;
205
+ end
206
+ end
207
+ assign nxt_byte_len = hd_byte_len + sub_req_rsp_head[12:0];
208
+
209
+ assign only_req_rsp_sop = emit & sub_req_rsp_valid & sub_req_rsp_ready & is_head_sop ;
210
+ assign last_sub_req_rsp_sop = emit & sub_req_rsp_valid & sub_req_rsp_ready & is_sub_head_sop ;
211
+ assign last_sub_req_rsp_eop = emit & sub_req_rsp_valid & sub_req_rsp_ready & sub_req_rsp_last;
212
+
213
+
214
+ // -----------------------------------------Store the head------------------------------------------
215
+ assign head_in_valid = last_sub_req_rsp_sop | only_req_rsp_sop;
216
+ assign head_in_head = only_req_rsp_sop ?
217
+ {32'd0, sub_req_rsp_head[95:32], {32-`DMA_LEN_WIDTH{1'b0}}, sub_req_rsp_head[12:0]} : // if only has one sub_req rsp for a rsp
218
+ {32'd0, hd_addr, {32-`DMA_LEN_WIDTH{1'b0}}, nxt_byte_len};
219
+ assign head_in_ready = !head_in_full;
220
+
221
+ assign head_out_ready = rd_rsp_valid & rd_rsp_ready & req_rsp_last;
222
+ assign head_out_valid = !head_out_empty;
223
+ pcieifc_sync_fifo #(
224
+ .DSIZE ( `DMA_HEAD_W ), // 128
225
+ .ASIZE ( HEAD_DEPTH_LOG ) // 2
226
+ ) head_store_fifo (
227
+
228
+ .clk ( dma_clk ), // i, i
229
+ .rst_n ( rst_n ), // i, i
230
+ .clr ( 1'd0 ), // i, 1
231
+
232
+ .wen ( head_in_valid & head_in_ready ), // i, 1
233
+ .din ( head_in_head ), // i, `DMA_HEAD_W
234
+ .full ( head_in_full ), // o, 1
235
+
236
+ .ren ( head_out_valid & head_out_ready ), // i, 1
237
+ .dout ( head_out_head ), // o, `DMA_HEAD_W
238
+ .empty( head_out_empty ) // o, 1
239
+
240
+ `ifdef PCIEI_APB_DBG
241
+ ,.rtsel ( 2'b0 ) // i, 2
242
+ ,.wtsel ( 2'b0 ) // i, 2
243
+ ,.ptsel ( 2'b0 ) // i, 2
244
+ ,.vg ( 1'b0 ) // i, 1
245
+ ,.vs ( 1'b0 ) // i, 1
246
+ `endif
247
+ );
248
+ /* --------Head FIFO{end}-------- */
249
+
250
+ /* --------is available{begin}-------- */
251
+ always @(posedge dma_clk, negedge rst_n) begin
252
+ if (~rst_n) begin
253
+ is_avail <= `TD 1'd0;
254
+ end
255
+ else if (rd_rsp_ready) begin
256
+ is_avail <= `TD 1'd1;
257
+ end
258
+ else begin
259
+ is_avail <= `TD 1'd0;
260
+ end
261
+ end
262
+ /* --------is available{end}-------- */
263
+
264
+ /* --------prog_full{begin}--------- */
265
+ assign rd_sub_req_rsp_ready = sub_req_rsp_ready & !is_input_blocked;
266
+
267
+ assign max_rd_req_cycle_num = 8'd4 << max_rd_req_sz;
268
+ assign is_input_blocked = is_sub_head_sop & (fifo_prog_full | !head_in_ready);
269
+ assign fifo_prog_full = (fifo_cycle_cnt + max_rd_req_cycle_num) > (8'd1 << `RSP_FIFO_DEPTH_LOG);
270
+ assign fifo_cycle_cnt = (|fifo_byte_cnt[4:0] + fifo_byte_cnt[`DMA_LEN_WIDTH-1:5]);
271
+
272
+ assign nxt_fifo_byte_cnt = fifo_byte_cnt + sub_req_rsp_blen;
273
+ assign fifo_in_inc = last_sub_req_rsp_eop ? ((|nxt_fifo_byte_cnt[4:0] + nxt_fifo_byte_cnt[`DMA_LEN_WIDTH-1:5]) << 5) :
274
+ (sub_req_rsp_valid & sub_req_rsp_ready) ? (fifo_byte_cnt + sub_req_rsp_blen) : fifo_byte_cnt;
275
+ assign fifo_out_dec = (req_rsp_valid & req_rsp_ready) ? `DMA_W_BCNT : {`DMA_LEN_WIDTH{1'd0}};
276
+ always @(posedge dma_clk, negedge rst_n) begin
277
+ if (~rst_n) begin
278
+ fifo_byte_cnt <= `TD 0;
279
+ end
280
+ else begin
281
+ fifo_byte_cnt <= `TD fifo_in_inc - fifo_out_dec;
282
+ end
283
+ end
284
+ /* --------prog_full{end}--------- */
285
+
286
+ /* --------Data FIFO{begin}-------- */
287
+ assign sub_req_rsp_valid = rd_sub_req_rsp_valid & !is_input_blocked;
288
+ assign sub_req_rsp_last = rd_sub_req_rsp_last ;
289
+ assign sub_req_rsp_eop = rd_sub_req_rsp_last & emit;
290
+ assign sub_req_rsp_data = rd_sub_req_rsp_data ;
291
+ assign sub_req_rsp_head = rd_sub_req_rsp_head ;
292
+
293
+ assign sub_req_rsp_blen = (sub_blen_left >= `DMA_W_BCNT) ? `DMA_W_BCNT : sub_blen_left;
294
+ assign sub_blen_left = sub_blen_total - in_trans_cnt;
295
+ assign sub_blen_total = sub_req_rsp_head[12:0];
296
+ always @(posedge dma_clk, negedge rst_n) begin
297
+ if (~rst_n) begin
298
+ in_trans_cnt <= `TD 0;
299
+ end
300
+ else if (sub_req_rsp_valid & sub_req_rsp_ready & sub_req_rsp_last) begin
301
+ in_trans_cnt <= `TD 0;
302
+ end
303
+ else if (sub_req_rsp_valid & sub_req_rsp_ready) begin
304
+ in_trans_cnt <= `TD in_trans_cnt + `DMA_W_BCNT;
305
+ end
306
+ end
307
+
308
+ rsp_data_fifo #(
309
+
310
+ ) rsp_data_fifo (
311
+
312
+ .dma_clk ( dma_clk ), // i, 1
313
+ .rst_n ( rst_n ), // i, 1
314
+
315
+ /* ------- sub_req rsp input{begin} ------- */
316
+ .sub_req_rsp_valid ( sub_req_rsp_valid ), // i, 1
317
+ .sub_req_rsp_last ( sub_req_rsp_last & emit ), // i, 1
318
+ .sub_req_rsp_blen ( sub_req_rsp_blen ), // i, `DMA_LEN_WIDTH; blen for every cycle
319
+ .sub_req_rsp_data ( sub_req_rsp_data ), // i, `DMA_DATA_W
320
+ .sub_req_rsp_ready ( sub_req_rsp_ready ), // o, 1
321
+ /* ------- sub_req rsp input{end} ------- */
322
+
323
+ /* ------- rsp output{begin} ------- */
324
+ .req_rsp_valid ( req_rsp_valid ), // o, 1
325
+ .req_rsp_data ( req_rsp_data ), // o, `DMA_DATA_W
326
+ .req_rsp_ready ( req_rsp_ready ) // i, 1
327
+ /* ------- rsp output{end} ------- */
328
+
329
+ `ifdef PCIEI_APB_DBG
330
+ /* -------APB reated signal{begin}------- */
331
+ ,.rw_data ( rw_data ) // i, `SRAM_RW_DATA_W
332
+ ,.dbg_signal ( dbg_signal_data_fifo ) // o, `DATA_FIFO_SIGNAL_W
333
+ /* -------APB reated signal{end}------- */
334
+ `endif
335
+ );
336
+
337
+ assign out_blen_total = head_out_head[12:0];
338
+ assign out_blen_left = out_blen_total - out_trans_cnt;
339
+ always @(posedge dma_clk, negedge rst_n) begin
340
+ if (~rst_n) begin
341
+ out_trans_cnt <= `TD 0;
342
+ end
343
+ else if (rd_rsp_valid & rd_rsp_ready & rd_rsp_last) begin
344
+ out_trans_cnt <= `TD 0;
345
+ end
346
+ else if (rd_rsp_valid & rd_rsp_ready) begin
347
+ out_trans_cnt <= `TD out_trans_cnt + `DMA_W_BCNT;
348
+ end
349
+ end
350
+
351
+ assign req_rsp_last = (out_blen_left <= `DMA_W_BCNT);
352
+ /* --------Data FIFO{end}-------- */
353
+
354
+ /* --------Output {begin}-------- */
355
+ assign rd_rsp_valid = req_rsp_valid & head_out_valid;
356
+ assign rd_rsp_last = req_rsp_valid & req_rsp_last ;
357
+ assign rd_rsp_data = req_rsp_data ;
358
+ assign rd_rsp_head = head_out_head;
359
+
360
+ assign req_rsp_ready = head_out_valid & rd_rsp_ready;
361
+ /* --------Output {end}-------- */
362
+
363
+ endmodule
ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/DMA/DMA_Read/sub_req_rsp_wrapper.v ADDED
@@ -0,0 +1,239 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ `timescale 1ns / 100ps
2
+ //*************************************************************************
3
+ // > File : sub_req_rsp_wrapper.v
4
+ // > Author : Kangning
5
+ // > Date : 2022-06-29
6
+ // > Note : Wrapper for sub_req_rsp interface
7
+ //*************************************************************************
8
+
9
+ module sub_req_rsp_wrapper #(
10
+
11
+ ) (
12
+ input wire dma_clk, // i, 1
13
+ input wire rst_n , // i, 1
14
+
15
+ /* ------- Read Response output{begin} ------- */
16
+ /* *_head
17
+ * | Reserved | address | Reserved | Byte length |
18
+ * | 127:96 | 95:32 | 31:13 | 12:0 |
19
+ */
20
+ output wire ft_rd_rsp_ren , // o, 1
21
+ output wire [`TAG_NUM_LOG-1:0] ft_rd_rsp_tag , // o, `TAG_NUM_LOG
22
+ input wire [`DMA_HEAD_W -1:0] ft_rd_rsp_head, // i, `DMA_HEAD_W
23
+ input wire [`DMA_DATA_W -1:0] ft_rd_rsp_data, // i, `DMA_DATA_W
24
+ input wire ft_rd_rsp_last, // i, 1
25
+ input wire ft_rd_rsp_vld , // i, 1
26
+ /* ------- Read Response output{end} ------- */
27
+
28
+ /* -------tag release{begin}------- */
29
+ output wire nxt_match_ready, // o, 1
30
+ input wire nxt_match_last , // i, 1
31
+ input wire [`DW_LEN_WIDTH-1:0] nxt_match_sz , // i, `DW_LEN_WIDTH
32
+ input wire [`TAG_MISC -1:0] nxt_match_misc , // i, `TAG_MISC ; Including addr && dw empty info
33
+ input wire [8 -1:0] nxt_match_chnl , // i, `DMA_RD_CHNL_NUM_LOG
34
+ input wire [`TAG_NUM_LOG -1:0] nxt_match_tag , // i, `TAG_NUM_LOG
35
+ input wire nxt_match_valid, // i, 1
36
+ /* -------tag release{end}------- */
37
+
38
+ /* ------- Read sub-req response{begin} ------- */
39
+ /* dma_*_head
40
+ * | emit | chnl_num | Reserved | address | Reserved | Byte length |
41
+ * | 127 | 126:120 | 119:96 | 95:32 | 31:13 | 12:0 |
42
+ */
43
+ output wire st_sub_req_rsp_valid, // o, 1
44
+ output wire st_sub_req_rsp_last , // o, 1
45
+ output wire [`DMA_DATA_W-1:0] st_sub_req_rsp_data , // o, `DMA_DATA_W
46
+ output wire [`DMA_HEAD_W-1:0] st_sub_req_rsp_head , // o, `DMA_HEAD_W
47
+ input wire st_sub_req_rsp_ready // i, 1
48
+ /* ------- Read sub-req response{end} ------- */
49
+
50
+ `ifdef PCIEI_APB_DBG
51
+ /* -------APB reated signal{begin}------- */
52
+ ,input wire [31:0] dbg_sel // i, 32
53
+ ,output wire [31:0] dbg_bus // o, 32
54
+ /* -------APB reated signal{end}------- */
55
+ `endif
56
+ );
57
+
58
+
59
+ /* -------sub_req_rsp_head generation {begin}------- */
60
+ reg [0 :0] last ;
61
+ reg [12 :0] size ;
62
+ reg [`TAG_NUM_LOG-1:0] tag ;
63
+ reg [7 :0] chnl_num;
64
+ reg [6 :0] addr ;
65
+ reg [`DMA_LEN_WIDTH-1:0] byte_len;
66
+ /* ------- sub_req_rsp_head generation{end}------- */
67
+
68
+ /* -------State relevant to FSM{begin}------- */
69
+ localparam IDLE = 2'b01, // Wait for the the release of tag fifo
70
+ FORWARD = 2'b10; // Store the the response to reorder buffer till the out_reg send its
71
+ // last beat. Then jump to IDLE.
72
+
73
+ reg [1:0] cur_state;
74
+ reg [1:0] nxt_state;
75
+
76
+ wire is_idle, is_forward;
77
+ wire j_forward, j_idle;
78
+ wire nxt_forward;
79
+ /* -------State relevant to FSM{end}------- */
80
+
81
+ /* ------- Read sub-req response{begin} ------- */
82
+ /* dma_*_head
83
+ * | emit | chnl_num | Reserved | address | Reserved | Byte length |
84
+ * | 127 | 126:120 | 119:96 | 95:32 | 31:13 | 12:0 |
85
+ */
86
+ wire sub_req_rsp_valid;
87
+ wire sub_req_rsp_last ;
88
+ wire [`DMA_DATA_W-1:0] sub_req_rsp_data ;
89
+ wire [`DMA_HEAD_W-1:0] sub_req_rsp_head ;
90
+ wire sub_req_rsp_ready;
91
+ /* ------- Read sub-req response{end} ------- */
92
+
93
+ `ifdef PCIEI_APB_DBG
94
+ /* -------APB reated signal{begin}------- */
95
+ wire [`WRAPPER_SIGNAL_W-1:0] dbg_signal;
96
+ /* -------APB reated signal{end}------- */
97
+ `endif
98
+
99
+ // ---------------------------------------------------------------------------------------------------------------------------------------------------------------- //
100
+
101
+ `ifdef PCIEI_APB_DBG
102
+ /* -------APB reated signal{begin}------- */
103
+ assign dbg_bus = dbg_signal >> {dbg_sel, 5'd0};
104
+
105
+ assign dbg_signal = { // 444
106
+ last, size, tag, chnl_num, addr, byte_len, // 48
107
+ cur_state, nxt_state, // 4
108
+ is_idle, is_forward, // 2
109
+ j_forward, j_idle, // 2
110
+ nxt_forward, // 1
111
+ sub_req_rsp_valid, sub_req_rsp_last , sub_req_rsp_data , sub_req_rsp_head , sub_req_rsp_ready // 387
112
+ };
113
+ /* -------APB reated signal{end}------- */
114
+ `endif
115
+
116
+ /* -------{Read Response FSM}begin------- */
117
+ /******************** Stage 1: State Register **********************/
118
+ assign is_idle = (cur_state == IDLE );
119
+ assign is_forward = (cur_state == FORWARD);
120
+
121
+ assign j_forward = (cur_state == IDLE) & nxt_match_valid;
122
+ assign nxt_forward = (cur_state == IDLE) & nxt_match_valid;
123
+
124
+ assign j_idle = (cur_state == FORWARD) & (sub_req_rsp_valid & sub_req_rsp_ready & sub_req_rsp_last);
125
+
126
+ always @(posedge dma_clk, negedge rst_n) begin
127
+ if(~rst_n)
128
+ cur_state <= `TD IDLE;
129
+ else
130
+ cur_state <= `TD nxt_state;
131
+ end
132
+
133
+ /******************** Stage 2: State Transition **********************/
134
+
135
+ always @(*) begin
136
+ case(cur_state)
137
+ IDLE: begin
138
+ if (nxt_match_valid) begin
139
+ nxt_state = FORWARD;
140
+ end
141
+ else begin
142
+ nxt_state = IDLE;
143
+ end
144
+ end
145
+ FORWARD: begin
146
+ if (sub_req_rsp_valid & sub_req_rsp_ready & sub_req_rsp_last) begin
147
+ nxt_state = IDLE;
148
+ end
149
+ else begin
150
+ nxt_state = FORWARD;
151
+ end
152
+ end
153
+ default: begin
154
+ nxt_state = IDLE;
155
+ end
156
+ endcase
157
+ end
158
+ /******************** Stage 3: Output **********************/
159
+
160
+ // interface with Reorder buffer Fetch
161
+ assign ft_rd_rsp_ren = is_forward & sub_req_rsp_ready;
162
+ assign ft_rd_rsp_tag = tag;
163
+
164
+ // interface with Non-posted Tag Management
165
+ assign nxt_match_ready = is_forward & sub_req_rsp_valid & sub_req_rsp_ready & sub_req_rsp_last; // j_forward | nxt_forward;
166
+
167
+ // sub_req_rsp interface
168
+ /* dma_*_head
169
+ * | emit | chnl_num | Reserved | address | Reserved | Byte length |
170
+ * | 127 | 126:120 | 119:96 | 95:32 | 31:13 | 12:0 |
171
+ */
172
+ assign sub_req_rsp_valid = ft_rd_rsp_vld & is_forward;
173
+ assign sub_req_rsp_last = sub_req_rsp_valid ? ft_rd_rsp_last : 0;
174
+ assign sub_req_rsp_head = sub_req_rsp_valid ? {((last << 7) | chnl_num), 81'd0, addr, 19'd0, byte_len} : 0;
175
+ assign sub_req_rsp_data = sub_req_rsp_valid ? ft_rd_rsp_data : 0;
176
+ /* -------{Read Response FSM}end------- */
177
+
178
+
179
+ /* -------Sub req rsp signal generation{begin}------- */
180
+ always @(posedge dma_clk, negedge rst_n) begin
181
+ if (~rst_n) begin
182
+ last <= `TD 0;
183
+ size <= `TD 0;
184
+ tag <= `TD 0;
185
+ chnl_num <= `TD 0;
186
+ addr <= `TD 0;
187
+ byte_len <= `TD 0;
188
+ end
189
+ else if (j_idle) begin
190
+ last <= `TD 0;
191
+ size <= `TD 0;
192
+ tag <= `TD 0;
193
+ chnl_num <= `TD 0;
194
+ addr <= `TD 0;
195
+ byte_len <= `TD 0;
196
+ end
197
+ else if (j_forward) begin // j_forward | nxt_forward
198
+ last <= `TD nxt_match_last;
199
+ size <= `TD nxt_match_sz ;
200
+ tag <= `TD nxt_match_tag ;
201
+ chnl_num <= `TD nxt_match_chnl;
202
+ addr <= `TD nxt_match_misc[11:5];
203
+ byte_len <= `TD (nxt_match_sz << 2) - nxt_match_misc[4:0];
204
+ end
205
+ end
206
+ /* -------Sub req rsp signal generation{end}------- */
207
+
208
+ /* -------output reg{begin}------- */
209
+ assign st_sub_req_rsp_valid = sub_req_rsp_valid;
210
+ assign st_sub_req_rsp_last = sub_req_rsp_last ;
211
+ assign st_sub_req_rsp_head = sub_req_rsp_head ;
212
+ assign st_sub_req_rsp_data = sub_req_rsp_data ;
213
+ assign sub_req_rsp_ready = st_sub_req_rsp_ready;
214
+ // st_reg #(
215
+ // .TUSER_WIDTH ( `DMA_HEAD_W ),
216
+ // .TDATA_WIDTH ( `DMA_DATA_W )
217
+ // ) out_st_reg (
218
+ // .clk ( dma_clk ), // i, 1
219
+ // .rst_n ( rst_n ), // i, 1
220
+
221
+ // /* -------input axis-like interface{begin}------- */
222
+ // .axis_tvalid ( sub_req_rsp_valid ), // i, 1
223
+ // .axis_tlast ( sub_req_rsp_last ), // i, 1
224
+ // .axis_tuser ( sub_req_rsp_head ), // i, TUSER_WIDTH
225
+ // .axis_tdata ( sub_req_rsp_data ), // i, TDATA_WIDTH
226
+ // .axis_tready ( sub_req_rsp_ready ), // o, 1
227
+ // /* -------input axis-like interface{end}------- */
228
+
229
+ // /* -------output in_reg inteface{begin}------- */
230
+ // .axis_reg_tvalid ( st_sub_req_rsp_valid ), // o, 1
231
+ // .axis_reg_tlast ( st_sub_req_rsp_last ), // o, 1
232
+ // .axis_reg_tuser ( st_sub_req_rsp_head ), // o, TUSER_WIDTH
233
+ // .axis_reg_tdata ( st_sub_req_rsp_data ), // o, TDATA_WIDTH
234
+ // .axis_reg_tready ( st_sub_req_rsp_ready ) // i, 1
235
+ // /* -------output in_reg inteface{end}------- */
236
+ // );
237
+ /* -------output reg{end}------- */
238
+
239
+ endmodule
ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/DMA/DMA_Read/sub_rsp_concat.v ADDED
@@ -0,0 +1,485 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ `timescale 1ns / 100ps
2
+ //*************************************************************************
3
+ // > File Name: sub_rsp_concat.v
4
+ // > Author : Kangning
5
+ // > Date : 2020-11-15
6
+ // > Note : sub_rsp_concat, store and concat multi-pkts into one message.
7
+ // Note that the fifo could store more than one message.
8
+ // > ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
9
+ // > ^ ^
10
+ // > ^ ########## ########### ^
11
+ // > ^ # #------># tmp_reg # ########### ^
12
+ // > ^ ------># in_reg # ###########-----># # ^
13
+ // > ^ # # #data_fifo#----> ^
14
+ // > ^ ##########-----------------------># # ^
15
+ // > ^ ########### ^
16
+ // > ^ ^
17
+ // > ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
18
+ //*************************************************************************
19
+
20
+ module sub_rsp_concat #(
21
+
22
+ ) (
23
+ input wire dma_clk, // i, 1
24
+ input wire rst_n , // i, 1
25
+ output reg init_done, // o, 1
26
+
27
+ /* ------- sub-rsp input{begin} ------- */
28
+ input wire st_rd_rsp_valid, // i, 1
29
+ input wire st_rd_rsp_last , // i, 1; indicate the last cycle of the whole req rsp
30
+ input wire st_rd_rsp_eop , // i, 1; indicate the last cycle of the whole req rsp
31
+ input wire [`TAG_NUM_LOG -1:0] st_rd_rsp_tag , // i, `TAG_NUM_LOG
32
+ input wire [`DMA_LEN_WIDTH-1:0] st_rd_rsp_blen , // i, `DMA_LEN_WIDTH; blen for every cycle
33
+ input wire [`DMA_DATA_W -1:0] st_rd_rsp_data , // i, `DMA_DATA_W
34
+ output wire st_rd_rsp_ready, // o, 1
35
+ /* ------- sub-rsp input{end} ------- */
36
+
37
+ /* ------- rsp output{begin} ------- */
38
+ output wire store_fifo_wen , // o, 1
39
+ output wire [`TAG_NUM_LOG-1:0] store_fifo_tag , // o, `TAG_NUM_LOG
40
+ output wire store_fifo_last, // o, 1
41
+ output wire [`DMA_DATA_W -1:0] store_fifo_data, // o, `DMA_DATA_W
42
+ input wire store_fifo_rdy // i, 1
43
+ /* ------- rsp output{end} ------- */
44
+
45
+ `ifdef PCIEI_APB_DBG
46
+ /* -------APB reated signal{begin}------- */
47
+ ,input wire [`SRAM_RW_DATA_W-1:0] rw_data// i, `SRAM_RW_DATA_W
48
+ ,output wire [`SUB_RSP_CONCAT_SIGNAL_W-1:0] dbg_signal // o, `SUB_RSP_CONCAT_SIGNAL_W
49
+ /* -------APB reated signal{end}------- */
50
+ `endif
51
+ );
52
+
53
+ /* --------Init related signal{begin}-------- */
54
+ reg [`TAG_NUM_LOG -1:0] init_waddr ;
55
+ /* --------Init related signal{end}-------- */
56
+
57
+ /* -------in_reg{begin}------- */
58
+ wire st_valid;
59
+ wire st_last ;
60
+ wire [`TAG_NUM_LOG -1:0] st_tag ;
61
+ wire [1+`DMA_LEN_WIDTH+`DMA_DATA_W-1:0] st_pyld ;
62
+ wire st_ready;
63
+
64
+ wire in_reg_valid;
65
+ wire in_reg_last ;
66
+ wire in_reg_eop ;
67
+ wire [`TAG_NUM_LOG -1:0] in_reg_tag ;
68
+ wire [`DMA_LEN_WIDTH-1:0] in_reg_blen ;
69
+ wire [`DMA_DATA_W -1:0] in_reg_data ;
70
+ wire in_reg_ready;
71
+
72
+ reg in_reg_first; // First packet of in_reg
73
+ /* -------in_reg{end}------- */
74
+
75
+ /* -------Temp data get FSM{begin}------- */
76
+ localparam IDLE = 3'b001, // Wait for the comming of the data; At this state, we read
77
+ // the temp data in sram and get it in the next cycle.
78
+ FORWARD = 3'b010, // Forward to store the data.
79
+ TMP_CYCLE = 3'b100; // This is the last cycle (eop) with only tmp data outputs
80
+
81
+ reg [2:0] cur_state;
82
+ reg [2:0] nxt_state;
83
+
84
+ wire is_idle, is_forward, is_tmp_cycle;
85
+ wire j_forward, j_tmp_cycle;
86
+
87
+ wire is_forward_last ; // last cycle in forward state
88
+ wire is_tmp_cycle_last; // last cycle in tmp_cycle state
89
+
90
+ wire is_trans_last; // last cycle to trans this pkt (not eop)
91
+ wire is_trans_eop ; // last cycle to trans this pkt (eop)
92
+
93
+
94
+ wire [`DMA_LEN_WIDTH-1:0] tmp_blen;
95
+ wire [`DMA_DATA_W -1:0] tmp_data;
96
+
97
+ wire [`DMA_LEN_WIDTH-1:0] tmp_sram_blen;
98
+ wire [`DMA_DATA_W -1:0] tmp_sram_data;
99
+ /* -------Temp data get FSM{end}------- */
100
+
101
+ /* --------Temp data SRAM{begin}-------- */
102
+ wire temp_wen ;
103
+ wire [`TAG_NUM_LOG -1:0] temp_waddr ;
104
+ wire [`DMA_LEN_WIDTH+`DMA_DATA_W-1:0] temp_din ;
105
+ wire temp_ren ;
106
+ wire [`TAG_NUM_LOG -1:0] temp_raddr ;
107
+ wire [`DMA_LEN_WIDTH+`DMA_DATA_W-1:0] temp_dout ;
108
+
109
+ // Fast forward related
110
+ wire is_fast_forward;
111
+
112
+ wire tmp_ff_valid;
113
+ wire [`DMA_LEN_WIDTH-1:0] tmp_ff_blen ;
114
+ wire [`DMA_DATA_W -1:0] tmp_ff_data ;
115
+ wire tmp_ff_ready;
116
+ /* --------Temp data SRAM{end}-------- */
117
+
118
+ /* --------Tep reg related{begin}-------- */
119
+ wire con_tmp_valid;
120
+ wire con_tmp_last ;
121
+ wire [`TAG_NUM_LOG -1:0] con_tmp_tag ;
122
+ wire [`DMA_LEN_WIDTH-1:0] con_tmp_blen ;
123
+ wire [`DMA_DATA_W -1:0] con_tmp_data ;
124
+ wire con_tmp_eop ;
125
+ wire con_tmp_ready;
126
+
127
+ wire tmp_reg_valid; // We assume tmp_reg is always valid when we use it
128
+ wire tmp_reg_last ;
129
+ wire [`TAG_NUM_LOG -1:0] tmp_reg_tag ;
130
+ wire [`DMA_LEN_WIDTH-1:0] tmp_reg_blen ;
131
+ wire [`DMA_DATA_W -1:0] tmp_reg_data ;
132
+ wire tmp_reg_eop ;
133
+ wire tmp_reg_ready;
134
+ /* --------Tep reg related{end}-------- */
135
+
136
+ /* ---------Concat temp & in_reg{begin}-------- */
137
+ wire concat_valid;
138
+ wire concat_eop ;
139
+ wire [`TAG_NUM_LOG -1:0] concat_tag ;
140
+ wire [`DMA_LEN_WIDTH :0] concat_blen ;
141
+ wire [2*`DMA_DATA_W -1:0] concat_data ;
142
+ /* ---------Concat temp & in_reg{end}-------- */
143
+
144
+ /* -------out_reg{begin}------- */
145
+
146
+ wire con_out_valid;
147
+ wire con_out_last ;
148
+ wire [`TAG_NUM_LOG -1:0] con_out_tag ;
149
+ wire [`DMA_LEN_WIDTH-1:0] con_out_blen ;
150
+ wire [`DMA_DATA_W -1:0] con_out_data ;
151
+ wire con_out_ready;
152
+ /* -------out_reg{end}------- */
153
+
154
+
155
+ `ifdef PCIEI_APB_DBG
156
+ /* -------APB reated signal{begin}------- */
157
+ wire [1:0] rtsel;
158
+ wire [1:0] wtsel;
159
+ wire [1:0] ptsel;
160
+ wire vg ;
161
+ wire vs ;
162
+ /* -------APB reated signal{end}------- */
163
+ `endif
164
+
165
+ //---------------------------------------------------------------------------------------------------------------------------
166
+
167
+ `ifdef PCIEI_APB_DBG
168
+ /* -------APB reated signal{begin}------- */
169
+ assign {rtsel, wtsel, ptsel, vg, vs} = rw_data;
170
+ assign dbg_signal = { // 3311
171
+ init_waddr, // 6
172
+ st_valid, st_last , st_tag , st_pyld , st_ready, // 279
173
+ in_reg_valid, in_reg_last , in_reg_eop , in_reg_tag , in_reg_blen , in_reg_data , in_reg_ready, // 279
174
+ in_reg_first, // 1
175
+ cur_state, nxt_state, // 6
176
+ is_idle, is_forward, is_tmp_cycle, j_forward, j_tmp_cycle, // 5
177
+ is_forward_last , is_tmp_cycle_last, is_trans_last, is_trans_eop , // 4
178
+ tmp_blen, tmp_data, tmp_sram_blen, tmp_sram_data, // 538
179
+ temp_wen , temp_waddr , temp_din , temp_ren , temp_raddr , temp_dout , // 552
180
+ is_fast_forward, // 1
181
+ tmp_ff_valid, tmp_ff_blen , tmp_ff_data , tmp_ff_ready, // 271
182
+ con_tmp_valid, con_tmp_last , con_tmp_tag , con_tmp_blen , con_tmp_data , con_tmp_eop , con_tmp_ready, // 279
183
+ tmp_reg_valid, tmp_reg_last , tmp_reg_tag , tmp_reg_blen , tmp_reg_data , tmp_reg_eop , tmp_reg_ready, // 279
184
+ concat_valid, concat_eop , concat_tag , concat_blen , concat_data , // 533
185
+ con_out_valid, con_out_last , con_out_tag , con_out_blen , con_out_data , con_out_ready // 278
186
+ };
187
+ /* -------APB reated signal{end}------- */
188
+ `endif
189
+
190
+ /* --------Init related signal{begin}-------- */
191
+ always @(posedge dma_clk, negedge rst_n) begin
192
+ if (~rst_n) begin
193
+ init_done <= `TD 1'd0;
194
+ end
195
+ else if (init_waddr == `TAG_NUM - 1) begin
196
+ init_done <= `TD 1'd1;
197
+ end
198
+ end
199
+
200
+ always @(posedge dma_clk, negedge rst_n) begin
201
+ if (~rst_n) begin
202
+ init_waddr <= `TD {`TAG_NUM_LOG{1'd0}};
203
+ end
204
+ else if (init_waddr != `TAG_NUM - 1) begin
205
+ init_waddr <= init_waddr + 1;
206
+ end
207
+ end
208
+ /* --------Init related signal{end}-------- */
209
+
210
+ /* -------in_reg{begin}------- */
211
+ assign st_rd_rsp_ready = st_ready & (!j_tmp_cycle);
212
+
213
+ assign st_valid = st_rd_rsp_valid & (!j_tmp_cycle);
214
+ assign st_last = st_rd_rsp_last;
215
+ assign st_tag = st_rd_rsp_tag ;
216
+ assign st_pyld = {st_rd_rsp_eop, st_rd_rsp_blen, st_rd_rsp_data};
217
+
218
+ st_reg #(
219
+ .TUSER_WIDTH ( `TAG_NUM_LOG ),
220
+ .TDATA_WIDTH ( 1 + `DMA_LEN_WIDTH + `DMA_DATA_W ),
221
+ .MODE ( 1 ) // Allow only one cycle storage
222
+ ) in_st_reg (
223
+ .clk ( dma_clk ), // i, 1
224
+ .rst_n ( rst_n ), // i, 1
225
+
226
+ /* -------input axis-like interface{begin}------- */
227
+ .axis_tvalid ( st_valid ), // i, 1
228
+ .axis_tlast ( st_last ), // i, 1
229
+ .axis_tuser ( st_tag ), // i, TUSER_WIDTH
230
+ .axis_tdata ( st_pyld ), // i, TDATA_WIDTH
231
+ .axis_tready ( st_ready ), // o, 1
232
+ /* -------input axis-like interface{end}------- */
233
+
234
+ /* -------output in_reg inteface{begin}------- */
235
+ .axis_reg_tvalid ( in_reg_valid ), // o, 1
236
+ .axis_reg_tlast ( in_reg_last ), // o, 1
237
+ .axis_reg_tuser ( in_reg_tag ), // o, TUSER_WIDTH
238
+ .axis_reg_tdata ( {in_reg_eop, in_reg_blen, in_reg_data} ), // o, TDATA_WIDTH
239
+ .axis_reg_tready ( in_reg_ready ) // i, 1
240
+ /* -------output in_reg inteface{end}------- */
241
+ );
242
+
243
+ assign in_reg_ready = con_out_ready; // in tmp_cycle state, it is still controlled by con_out_ready,
244
+ // cause we need to drain the input stream reg
245
+
246
+ always @(posedge dma_clk, negedge rst_n) begin
247
+ if (~rst_n) begin
248
+ in_reg_first <= `TD 1'd0;
249
+ end
250
+ else if (j_forward) begin
251
+ in_reg_first <= `TD 1'd1;
252
+ end
253
+ else begin
254
+ in_reg_first <= `TD 1'd0;
255
+ end
256
+ end
257
+ /* -------in_reg{end}------- */
258
+
259
+ /* -------{Temp data get FSM}begin------- */
260
+ /******************** Stage 1: State Register **********************/
261
+ assign is_idle = (cur_state == IDLE );
262
+ assign is_forward = (cur_state == FORWARD );
263
+ assign is_tmp_cycle = (cur_state == TMP_CYCLE);
264
+
265
+ // Last cycle (not eop) to forward
266
+ assign is_forward_last = is_forward & in_reg_valid & in_reg_ready & in_reg_last;
267
+ assign is_tmp_cycle_last = is_tmp_cycle & con_out_valid & con_out_ready & con_out_last;
268
+
269
+ assign is_trans_last = !j_tmp_cycle & is_forward_last & !in_reg_eop;
270
+ assign is_trans_eop = (!j_tmp_cycle & is_forward_last & in_reg_eop) | is_tmp_cycle_last;
271
+
272
+ assign j_forward = (is_idle & st_valid & st_ready) ||
273
+ (is_forward_last & st_valid & st_ready) ||
274
+ (is_tmp_cycle_last & st_valid & st_ready);
275
+
276
+ assign j_tmp_cycle = in_reg_eop & (concat_blen > `DMA_W_BCNT);
277
+
278
+ always @(posedge dma_clk, negedge rst_n) begin
279
+ if(~rst_n)
280
+ cur_state <= `TD IDLE;
281
+ else
282
+ cur_state <= `TD nxt_state;
283
+ end
284
+
285
+ /******************** Stage 2: State Transition **********************/
286
+ always @(*) begin
287
+ case(cur_state)
288
+ IDLE: begin
289
+ if (st_valid & st_ready) begin
290
+ nxt_state = FORWARD;
291
+ end
292
+ else begin
293
+ nxt_state = IDLE;
294
+ end
295
+ end
296
+ FORWARD: begin
297
+ if (in_reg_valid & in_reg_ready & in_reg_last) begin
298
+ if (in_reg_eop & (concat_blen > `DMA_W_BCNT)) begin
299
+ nxt_state = TMP_CYCLE;
300
+ end
301
+ else if (st_valid & st_ready) begin
302
+ nxt_state = FORWARD;
303
+ end
304
+ else begin
305
+ nxt_state = IDLE;
306
+ end
307
+ end
308
+ else begin
309
+ nxt_state = FORWARD;
310
+ end
311
+ end
312
+ TMP_CYCLE: begin
313
+ if (con_out_valid & con_out_ready & con_out_last) begin
314
+ if (st_valid & st_ready) begin
315
+ nxt_state = FORWARD;
316
+ end
317
+ else begin
318
+ nxt_state = IDLE;
319
+ end
320
+ end
321
+ else begin
322
+ nxt_state = TMP_CYCLE;
323
+ end
324
+ end
325
+ default: begin
326
+ nxt_state = IDLE;
327
+ end
328
+ endcase
329
+ end
330
+ /******************** Stage 3: Output **********************/
331
+
332
+ assign tmp_data = in_reg_first ? tmp_sram_data : tmp_reg_data;
333
+ assign tmp_blen = in_reg_first ? tmp_sram_blen : tmp_reg_blen;
334
+ /* -------{Temp data get FSM}end------- */
335
+
336
+ /* --------temp data storge{begin}-------- */
337
+ assign temp_wen = !is_fast_forward & (
338
+ is_trans_last | // When it is not the eop pkt, write back the remained tmp data
339
+ is_trans_eop // When it is the eop pkt, clear the tmp sram entry
340
+ );
341
+ assign temp_waddr = concat_tag;
342
+ assign temp_din = is_trans_last ?
343
+ ((concat_blen >= `DMA_W_BCNT) ? {con_tmp_blen, con_tmp_data} : {con_out_blen, con_out_data}) :
344
+ {`DMA_LEN_WIDTH + `DMA_DATA_W{1'd0}}; // trans_eop is included in this branch
345
+
346
+ assign temp_ren = !is_fast_forward & j_forward;
347
+ assign temp_raddr = st_rd_rsp_tag;
348
+
349
+ pcieifc_sd_sram #(
350
+ .DATAWIDTH ( `DMA_LEN_WIDTH + `DMA_DATA_W ), // 269
351
+ .ADDRWIDTH ( `TAG_NUM_LOG ) // 64 depth
352
+ ) temp_data_sram (
353
+ .clk ( dma_clk ), // i, 1
354
+ .rst_n ( rst_n ), // i, 1
355
+
356
+ .wea ( init_done ? temp_wen : 1'd1 ), // i, 1
357
+ .addra ( init_done ? temp_waddr : init_waddr ), // i, ADDRWIDTH
358
+ .dina ( init_done ? temp_din : {`DMA_LEN_WIDTH+`DMA_DATA_W{1'd0}} ), // i, DATAWIDTH
359
+
360
+ .reb ( temp_ren ), // i, 1
361
+ .addrb ( temp_raddr ), // i, ADDRWIDTH
362
+ .doutb ( temp_dout ) // o, DATAWIDTH
363
+
364
+ `ifdef PCIEI_APB_DBG
365
+ ,.rtsel ( rtsel )
366
+ ,.wtsel ( wtsel )
367
+ ,.ptsel ( ptsel )
368
+ ,.vg ( vg )
369
+ ,.vs ( vs )
370
+ `endif
371
+ );
372
+
373
+
374
+ assign is_fast_forward = (is_trans_last | is_trans_eop) & // Need write temp data
375
+ j_forward & // Need read temp data
376
+ (temp_waddr == temp_raddr); // wr & rd the same addr
377
+ st_reg #(
378
+ .TUSER_WIDTH ( 1 ),
379
+ .TDATA_WIDTH ( `DMA_LEN_WIDTH + `DMA_DATA_W ),
380
+ .MODE ( 1 )
381
+ ) tmp_ff_st_reg (
382
+ .clk ( dma_clk ), // i, 1
383
+ .rst_n ( rst_n ), // i, 1
384
+
385
+ /* -------input axis-like interface{begin}------- */
386
+ .axis_tvalid ( is_fast_forward ), // i, 1
387
+ .axis_tlast ( 1'd0 ), // i, 1
388
+ .axis_tuser ( 1'd0 ), // i, TUSER_WIDTH
389
+ .axis_tdata ( temp_din ), // i, TDATA_WIDTH
390
+ .axis_tready ( ), // o, 1
391
+ /* -------input axis-like interface{end}------- */
392
+
393
+ /* -------output in_reg inteface{begin}------- */
394
+ .axis_reg_tvalid ( tmp_ff_valid ), // o, 1
395
+ .axis_reg_tlast ( ), // o, 1
396
+ .axis_reg_tuser ( ), // o, TUSER_WIDTH
397
+ .axis_reg_tdata ( {tmp_ff_blen, tmp_ff_data} ), // o, TDATA_WIDTH
398
+ .axis_reg_tready ( tmp_ff_ready ) // i, 1
399
+ /* -------output in_reg inteface{end}------- */
400
+ );
401
+ assign tmp_ff_ready = con_out_ready & in_reg_valid;
402
+
403
+ assign tmp_sram_blen = tmp_ff_valid ? tmp_ff_blen : temp_dout[`DMA_LEN_WIDTH+`DMA_DATA_W-1:`DMA_DATA_W];
404
+ assign tmp_sram_data = tmp_ff_valid ? tmp_ff_data : temp_dout[`DMA_DATA_W-1:0];
405
+ /* --------temp data storge{end}-------- */
406
+
407
+ /* ---------Concat temp & in_reg{begin}-------- */
408
+ assign concat_valid = is_tmp_cycle | in_reg_valid;
409
+ assign concat_eop = is_tmp_cycle ? tmp_reg_eop :
410
+ is_forward ? (in_reg_valid & in_reg_eop & !j_tmp_cycle) : 0;
411
+ assign concat_tag = is_tmp_cycle ? tmp_reg_tag :
412
+ is_forward ? ({`TAG_NUM_LOG{in_reg_valid}} & in_reg_tag) : 0;
413
+ assign concat_blen = in_reg_blen + tmp_blen;
414
+ assign concat_data = (in_reg_data << (tmp_blen << 3)) | tmp_data;
415
+ /* ---------Concat temp & in_reg{end}-------- */
416
+
417
+ /* -------tmp_reg{begin}------- */
418
+ assign con_tmp_valid = in_reg_valid & in_reg_ready;
419
+ assign con_tmp_last = in_reg_last;
420
+ assign con_tmp_tag = in_reg_tag ;
421
+ assign con_tmp_data = concat_data[2*`DMA_DATA_W-1:`DMA_DATA_W];
422
+ assign con_tmp_blen = (concat_blen >= `DMA_W_BCNT) ? (concat_blen - `DMA_W_BCNT) : 0;
423
+ assign con_tmp_eop = in_reg_eop;
424
+
425
+ st_reg #(
426
+ .TUSER_WIDTH ( `TAG_NUM_LOG ),
427
+ .TDATA_WIDTH ( 1 + `DMA_LEN_WIDTH + `DMA_DATA_W ),
428
+ .MODE ( 1 )
429
+ ) tmp_st_reg (
430
+ .clk ( dma_clk ), // i, 1
431
+ .rst_n ( rst_n ), // i, 1
432
+
433
+ /* -------input axis-like interface{begin}------- */
434
+ .axis_tvalid ( con_tmp_valid ), // i, 1
435
+ .axis_tlast ( con_tmp_last ), // i, 1
436
+ .axis_tuser ( con_tmp_tag ), // i, TUSER_WIDTH
437
+ .axis_tdata ( {con_tmp_eop, con_tmp_blen, con_tmp_data} ), // i, TDATA_WIDTH
438
+ .axis_tready ( con_tmp_ready ), // o, 1
439
+ /* -------input axis-like interface{end}------- */
440
+
441
+ /* -------output in_reg inteface{begin}------- */
442
+ .axis_reg_tvalid ( tmp_reg_valid ), // o, 1
443
+ .axis_reg_tlast ( tmp_reg_last ), // o, 1
444
+ .axis_reg_tuser ( tmp_reg_tag ), // o, TUSER_WIDTH
445
+ .axis_reg_tdata ( {tmp_reg_eop, tmp_reg_blen, tmp_reg_data} ), // o, TDATA_WIDTH
446
+ .axis_reg_tready ( tmp_reg_ready ) // i, 1
447
+ /* -------output in_reg inteface{end}------- */
448
+ );
449
+ assign tmp_reg_ready = con_out_ready & concat_valid;
450
+ /* -------tmp_reg{end}------- */
451
+
452
+ /* -------out_reg{begin}------- */
453
+ assign con_out_valid = concat_valid &
454
+ ((concat_blen >= `DMA_W_BCNT) | concat_eop); // don't write out if beat size is less than 32 & not eop cycle
455
+ assign con_out_last = concat_eop;
456
+ assign con_out_tag = concat_tag;
457
+ assign con_out_data = concat_data[`DMA_DATA_W-1:0];
458
+ assign con_out_blen = concat_blen;
459
+
460
+ st_reg #(
461
+ .TUSER_WIDTH ( `TAG_NUM_LOG ),
462
+ .TDATA_WIDTH ( `DMA_DATA_W )
463
+ ) out_st_reg (
464
+ .clk ( dma_clk ), // i, 1
465
+ .rst_n ( rst_n ), // i, 1
466
+
467
+ /* -------input axis-like interface{begin}------- */
468
+ .axis_tvalid ( con_out_valid ), // i, 1
469
+ .axis_tlast ( con_out_last ), // i, 1
470
+ .axis_tuser ( con_out_tag ), // i, TUSER_WIDTH
471
+ .axis_tdata ( con_out_data ), // i, TDATA_WIDTH
472
+ .axis_tready ( con_out_ready ), // o, 1
473
+ /* -------input axis-like interface{end}------- */
474
+
475
+ /* -------output in_reg inteface{begin}------- */
476
+ .axis_reg_tvalid ( store_fifo_wen ), // o, 1
477
+ .axis_reg_tlast ( store_fifo_last ), // o, 1
478
+ .axis_reg_tuser ( store_fifo_tag ), // o, TUSER_WIDTH
479
+ .axis_reg_tdata ( store_fifo_data ), // o, TDATA_WIDTH
480
+ .axis_reg_tready ( store_fifo_rdy ) // i, 1
481
+ /* -------output in_reg inteface{end}------- */
482
+ );
483
+ /* -------out_reg{end}------- */
484
+
485
+ endmodule
ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/DMA/DMA_Read/tag_buf.v ADDED
@@ -0,0 +1,192 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ `timescale 1ns / 100ps
2
+ //*************************************************************************
3
+ // > File Name: tag_buf.v
4
+ // > Author : Kangning
5
+ // > Date : 2023-02-28
6
+ // > Note : tag_buf, store reordered rsp pkt.
7
+ //*************************************************************************
8
+
9
+ module tag_buf #(
10
+
11
+ ) (
12
+ input wire dma_clk, // i, 1
13
+ input wire rst_n , // i, 1
14
+
15
+ /* -------- Store related channel {begin}-------- */
16
+ input wire store_wen , // o, 1
17
+ input wire [`TAG_NUM_LOG-1:0] store_tag , // o, `TAG_NUM_LOG
18
+ input wire store_last, // o, 1
19
+ input wire [`DMA_DATA_W -1:0] store_data, // o, `DMA_DATA_W
20
+ output wire store_rdy , // i, 1
21
+ /* -------- Store related channel {end}-------- */
22
+
23
+ /* -------- Fetch related channel {begin}-------- */
24
+ input wire fetch_ren , // i, 1
25
+ input wire [`TAG_NUM_LOG-1:0] fetch_tag , // i, `TAG_NUM_LOG
26
+ output wire fetch_last , // o, 1 ; assert when this is the last sub-rsp pkt
27
+ output wire [`DMA_DATA_W -1:0] fetch_data , // o, `DMA_DATA_W
28
+ output wire fetch_vld // o, 1
29
+ /* -------- Fetch related channel {end}-------- */
30
+
31
+ `ifdef PCIEI_APB_DBG
32
+ /* -------APB reated signal{begin}------- */
33
+ ,input wire [`SRAM_RW_DATA_W-1:0] rw_data// i, `SRAM_RW_DATA_W
34
+ ,output wire [`TAG_BUF_SIGNAL_W-1:0] dbg_signal // o, `TAG_BUF_SIGNAL_W
35
+ /* -------APB reated signal{end}------- */
36
+ `endif
37
+ );
38
+
39
+ /* -------Index file{begin}------- */
40
+ reg [2:0] rd_idx[`TAG_NUM-1:0];
41
+ reg [2:0] wr_idx[`TAG_NUM-1:0];
42
+ reg [3:0] cnt [`TAG_NUM-1:0];
43
+
44
+ reg rd_data_vld;
45
+ wire full, empty;
46
+ /* -------Index file{end}------- */
47
+
48
+ /* --------reordered rsp pkt storge{begin}-------- */
49
+ wire buf_wen ;
50
+ wire [`TAG_NUM_LOG+3-1:0] buf_waddr ;
51
+ wire [1+`DMA_DATA_W -1:0] buf_din ;
52
+
53
+ wire buf_ren ;
54
+ wire [`TAG_NUM_LOG+3-1:0] buf_raddr ;
55
+ wire [1+`DMA_DATA_W -1:0] buf_dout ;
56
+ /* --------reordered rsp pkt storge{end}-------- */
57
+
58
+
59
+ `ifdef PCIEI_APB_DBG
60
+ /* -------APB reated signal{begin}------- */
61
+ wire [1:0] rtsel;
62
+ wire [1:0] wtsel;
63
+ wire [1:0] ptsel;
64
+ wire vg ;
65
+ wire vs ;
66
+ /* -------APB reated signal{end}------- */
67
+ `endif
68
+
69
+ //---------------------------------------------------------------------------------------------------------------------------
70
+
71
+ `ifdef PCIEI_APB_DBG
72
+ /* -------APB reated signal{begin}------- */
73
+ assign {rtsel, wtsel, ptsel, vg, vs} = rw_data;
74
+ assign dbg_signal = { // 537
75
+ rd_data_vld, full, empty, // 3
76
+ buf_wen, buf_waddr, buf_din , // 267
77
+ buf_ren, buf_raddr, buf_dout // 267
78
+ };
79
+ /* -------APB reated signal{end}------- */
80
+ `endif
81
+
82
+ /* -------- Index file update{begin}-------- */
83
+ integer i;
84
+ always @(posedge dma_clk, negedge rst_n) begin
85
+ if (~rst_n) begin
86
+ for (i = 0; i < `TAG_NUM; i = i + 1) begin
87
+ rd_idx[i] <= `TD 0;
88
+ end
89
+ end
90
+ else if (fetch_ren) begin
91
+ rd_idx[fetch_tag] <= `TD rd_idx[fetch_tag] + !empty;
92
+ end
93
+ end
94
+
95
+ integer j;
96
+ always @(posedge dma_clk, negedge rst_n) begin
97
+ if (~rst_n) begin
98
+ for (j = 0; j < `TAG_NUM; j = j + 1) begin
99
+ wr_idx[j] <= `TD 0;
100
+ end
101
+ end
102
+ else if (store_wen) begin
103
+ wr_idx[store_tag] <= `TD wr_idx[store_tag] + !full;
104
+ end
105
+ end
106
+
107
+ integer k;
108
+ always @(posedge dma_clk, negedge rst_n) begin
109
+ if (~rst_n) begin
110
+ for (k = 0; k < `TAG_NUM; k = k + 1) begin
111
+ cnt[k] <= `TD 0;
112
+ end
113
+ end
114
+ else if ((store_tag == fetch_tag) &
115
+ store_wen & fetch_ren) begin // store and fetch the same buffer
116
+ cnt[store_tag] <= `TD cnt[store_tag] + !full - !empty;
117
+ end
118
+ else if (store_wen & fetch_ren) begin
119
+ cnt[store_tag] <= `TD cnt[store_tag] + !full;
120
+ cnt[fetch_tag] <= `TD cnt[fetch_tag] - !empty;
121
+ end
122
+ else if (store_wen) begin
123
+ cnt[store_tag] <= `TD cnt[store_tag] + !full;
124
+ end
125
+ else if (fetch_ren) begin
126
+ cnt[fetch_tag] <= `TD cnt[fetch_tag] - !empty;
127
+ end
128
+ end
129
+ /* -------- Index file update{end}-------- */
130
+
131
+ /* --------Store related logic{begin}-------- */
132
+ assign full = (cnt[store_tag] == 16);
133
+
134
+ assign store_rdy = !full;
135
+ /* --------Store related logic{end}-------- */
136
+
137
+ /* --------Fetch related logic{begin}-------- */
138
+ assign empty = (cnt[fetch_tag] == 0);
139
+
140
+ assign {fetch_last, fetch_data} = fetch_vld ? buf_dout : {1+`DMA_DATA_W{1'd0}};
141
+
142
+ always @(posedge dma_clk, negedge rst_n) begin
143
+ if (~rst_n) begin
144
+ rd_data_vld <= `TD 1'd0;
145
+ end
146
+ else if (fetch_last) begin
147
+ rd_data_vld <= `TD 1'd0;
148
+ end
149
+ else if (fetch_ren) begin
150
+ rd_data_vld <= `TD buf_ren;
151
+ end
152
+ end
153
+ assign fetch_vld = rd_data_vld;
154
+ /* --------Fetch related logic{end}-------- */
155
+
156
+ /* --------reordered rsp pkt storge{begin}-------- */
157
+ assign buf_wen = store_wen & store_rdy;
158
+ assign buf_waddr = (store_tag << 3) + wr_idx[store_tag];
159
+ assign buf_din = {store_last, store_data};
160
+
161
+ assign buf_ren = fetch_ren & !empty;
162
+ assign buf_raddr = (fetch_tag << 3) + rd_idx[fetch_tag];
163
+
164
+ pcieifc_sd_sram #(
165
+ .DATAWIDTH ( 1 + `DMA_DATA_W ), // 257
166
+ .ADDRWIDTH ( `TAG_NUM_LOG + 3 ) // 512 depth
167
+ ) reorder_buf (
168
+ .clk ( dma_clk ), // i, 1
169
+ .rst_n ( rst_n ), // i, 1
170
+
171
+ .wea ( buf_wen ), // i, 1
172
+ .addra ( buf_waddr ), // i, ADDRWIDTH
173
+ .dina ( buf_din ), // i, DATAWIDTH
174
+
175
+ .reb ( buf_ren ), // i, 1
176
+ .addrb ( buf_raddr ), // i, ADDRWIDTH
177
+ .doutb ( buf_dout ) // o, DATAWIDTH
178
+
179
+ `ifdef PCIEI_APB_DBG
180
+ ,.rtsel ( rtsel )
181
+ ,.wtsel ( wtsel )
182
+ ,.ptsel ( ptsel )
183
+ ,.vg ( vg )
184
+ ,.vs ( vs )
185
+ `endif
186
+ );
187
+
188
+ /* --------reordered rsp pkt storge{end}-------- */
189
+
190
+
191
+
192
+ endmodule
ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/DMA/DMA_Read/tag_matching.v ADDED
@@ -0,0 +1,199 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ `timescale 1ns / 100ps
2
+ //*************************************************************************
3
+ // > File : tag_matching.v
4
+ // > Author : Kangning
5
+ // > Date : 2022-11-03
6
+ // > Note : Match tags for different channels.
7
+ // Note that :
8
+ // 1. The channel is under comparsion only when it is not stalled;
9
+ // 2.
10
+ //*************************************************************************
11
+
12
+ module tag_matching #(
13
+
14
+ ) (
15
+ input wire dma_clk, // i, 1
16
+ input wire rst_n , // i, 1
17
+
18
+ /* -------tag release{begin}------- */
19
+ // Note that only one channel is allowed to assert at the same time
20
+ output wire [`DMA_RD_CHNL_NUM * 1 - 1 : 0] tag_rrsp_ready, // o, 1
21
+ input wire [`DMA_RD_CHNL_NUM * 1 - 1 : 0] tag_rrsp_last , // i, 1
22
+ input wire [`DMA_RD_CHNL_NUM * `DW_LEN_WIDTH - 1 : 0] tag_rrsp_sz , // i, `DW_LEN_WIDTH
23
+ input wire [`DMA_RD_CHNL_NUM * `TAG_MISC - 1 : 0] tag_rrsp_misc , // i, `TAG_MISC ; Including addr && dw empty info
24
+ input wire [`DMA_RD_CHNL_NUM * `TAG_NUM_LOG - 1 : 0] tag_rrsp_tag , // i, `TAG_NUM_LOG
25
+ input wire [`DMA_RD_CHNL_NUM * 1 - 1 : 0] tag_rrsp_valid, // i, 1
26
+ /* -------tag release{end}------- */
27
+
28
+ /* ------- Read Response input{begin} ------- */
29
+ input wire st_rd_rsp_wen , // i, 1
30
+ input wire st_rd_rsp_last, // i, 1 ; assert in every last beat of sub-rsp pkt
31
+ input wire [`DW_LEN_WIDTH-1:0] st_rd_rsp_dlen, // i, `DW_LEN_WIDTH ; part of head field in "store channel"
32
+ input wire [`TAG_NUM_LOG -1:0] st_rd_rsp_tag , // i, `TAG_NUM_LOG ; part of head field in "store channel"
33
+ input wire st_rd_rsp_rdy , // i, 1
34
+ /* ------- Read Response input{end} ------- */
35
+
36
+ /* --------chnl_stall{begin}-------- */
37
+ input wire [`DMA_RD_CHNL_NUM - 1 : 0] chnl_avail, // i, `DMA_RD_CHNL_NUM
38
+ /* --------chnl_stall{end}-------- */
39
+
40
+ /* -------tag release{begin}------- */
41
+ input wire nxt_match_ready, // i, 1
42
+ output wire nxt_match_last , // o, 1
43
+ output wire [`DW_LEN_WIDTH-1:0] nxt_match_sz , // o, `DW_LEN_WIDTH
44
+ output wire [`TAG_MISC -1:0] nxt_match_misc , // o, `TAG_MISC ; Including addr && dw empty info
45
+ output wire [8 -1:0] nxt_match_chnl , // o, 8
46
+ output wire [`TAG_NUM_LOG -1:0] nxt_match_tag , // o, `TAG_NUM_LOG
47
+ output wire nxt_match_valid // o, 1
48
+ /* -------tag release{end}------- */
49
+
50
+ `ifdef PCIEI_APB_DBG
51
+ /* -------APB reated signal{begin}------- */
52
+ ,input wire [31:0] dbg_sel // i, 32
53
+ ,output wire [31:0] dbg_bus // o, 32
54
+ /* -------APB reated signal{end}------- */
55
+ `endif
56
+ );
57
+
58
+ localparam CHNL_DATA_W = (`TAG_NUM_LOG + 8 + `DW_LEN_WIDTH + 1 + `TAG_MISC);
59
+
60
+ /* -------rebuf log SRAM{begin}------- */
61
+ reg rebuf_log_sram_tag [`TAG_NUM-1:0]; // store all the tags in reorder buffer.
62
+ reg [`DW_LEN_WIDTH-1:0] rebuf_log_sram_len [`TAG_NUM-1:0]; // Store all the accumulate len stored
63
+ // in reorder buffer (in dw unit).
64
+ /* -------rebuf log SRAM{end}------- */
65
+
66
+ /* -------tag release{begin}------- */
67
+ // Note that only one channel is allowed to assert at the same time
68
+ wire [1 - 1 : 0] tag_chnl_last [`DMA_RD_CHNL_NUM-1:0];
69
+ wire [`DW_LEN_WIDTH - 1 : 0] tag_chnl_sz [`DMA_RD_CHNL_NUM-1:0];
70
+ wire [`TAG_MISC - 1 : 0] tag_chnl_misc [`DMA_RD_CHNL_NUM-1:0];
71
+ wire [8 - 1 : 0] tag_chnl_chnl [`DMA_RD_CHNL_NUM-1:0];
72
+ wire [`TAG_NUM_LOG - 1 : 0] tag_chnl_tag [`DMA_RD_CHNL_NUM-1:0];
73
+ wire [1 - 1 : 0] is_chnl_match [`DMA_RD_CHNL_NUM-1:0];
74
+ wire [`DMA_RD_CHNL_NUM * 1 - 1 : 0] tag_chnl_valid;
75
+ wire [`DMA_RD_CHNL_NUM * CHNL_DATA_W - 1 : 0] tag_chnl_data ;
76
+ wire [`DMA_RD_CHNL_NUM * 1 - 1 : 0] tag_chnl_ready;
77
+ /* -------tag release{end}------- */
78
+
79
+ `ifdef PCIEI_APB_DBG
80
+ /* -------APB reated signal{begin}------- */
81
+ wire [`TAG_MATCHING_SIGNAL_W-1:0] dbg_signal;
82
+ /* -------APB reated signal{end}------- */
83
+ `endif
84
+
85
+ //----------------------------------------------------------------------------------------------------------------------
86
+
87
+ `ifdef PCIEI_APB_DBG
88
+ /* -------APB reated signal{begin}------- */
89
+ generate
90
+ if (`DMA_RD_CHNL_NUM == 9) begin: CHNL_NUM9
91
+
92
+ assign dbg_bus = dbg_signal >> {dbg_sel, 5'd0};
93
+
94
+ assign dbg_signal = { // 693
95
+ tag_chnl_last[0], tag_chnl_sz[0], tag_chnl_misc[0], tag_chnl_chnl[0], tag_chnl_tag[0], is_chnl_match[0],
96
+ tag_chnl_last[1], tag_chnl_sz[1], tag_chnl_misc[1], tag_chnl_chnl[1], tag_chnl_tag[1], is_chnl_match[1],
97
+ tag_chnl_last[2], tag_chnl_sz[2], tag_chnl_misc[2], tag_chnl_chnl[2], tag_chnl_tag[2], is_chnl_match[2],
98
+ tag_chnl_last[3], tag_chnl_sz[3], tag_chnl_misc[3], tag_chnl_chnl[3], tag_chnl_tag[3], is_chnl_match[3],
99
+ tag_chnl_last[4], tag_chnl_sz[4], tag_chnl_misc[4], tag_chnl_chnl[4], tag_chnl_tag[4], is_chnl_match[4],
100
+ tag_chnl_last[5], tag_chnl_sz[5], tag_chnl_misc[5], tag_chnl_chnl[5], tag_chnl_tag[5], is_chnl_match[5],
101
+ tag_chnl_last[6], tag_chnl_sz[6], tag_chnl_misc[6], tag_chnl_chnl[6], tag_chnl_tag[6], is_chnl_match[6],
102
+ tag_chnl_last[7], tag_chnl_sz[7], tag_chnl_misc[7], tag_chnl_chnl[7], tag_chnl_tag[7], is_chnl_match[7],
103
+ tag_chnl_last[8], tag_chnl_sz[8], tag_chnl_misc[8], tag_chnl_chnl[8], tag_chnl_tag[8], is_chnl_match[8], // 9 * 39
104
+ tag_chnl_valid, tag_chnl_data, tag_chnl_ready // 9 * 38
105
+ };
106
+ end
107
+ endgenerate
108
+ /* -------APB reated signal{end}------- */
109
+ `endif
110
+
111
+ /* -------Generate block{begin}------- */
112
+ genvar i;
113
+ generate
114
+ for (i = 0; i < `DMA_RD_CHNL_NUM; i = i + 1) begin:TAG_CHNL
115
+
116
+ assign tag_chnl_last [i] = tag_rrsp_last [(i+1) * 1 - 1 : i * 1 ];
117
+ assign tag_chnl_sz [i] = tag_rrsp_sz [(i+1) * `DW_LEN_WIDTH - 1 : i * `DW_LEN_WIDTH];
118
+ assign tag_chnl_misc [i] = tag_rrsp_misc [(i+1) * `TAG_MISC - 1 : i * `TAG_MISC ];
119
+ assign tag_chnl_chnl [i] = i;
120
+ assign tag_chnl_tag [i] = tag_rrsp_tag [(i+1) * `TAG_NUM_LOG - 1 : i * `TAG_NUM_LOG ];
121
+ assign is_chnl_match [i] = rebuf_log_sram_tag[tag_chnl_tag[i]] & // has returned rsp for this tag
122
+ (rebuf_log_sram_len[tag_chnl_tag[i]] == tag_chnl_sz[i]) & // all sub_rsp has returned
123
+ chnl_avail[i]; // the channel is not blocked
124
+
125
+ assign tag_chnl_valid[i] = tag_rrsp_valid[i] & // The channel tag is valid
126
+ is_chnl_match[i]; // Choose the ready channel
127
+ assign tag_chnl_data[(i+1)*CHNL_DATA_W-1:i*CHNL_DATA_W] = {tag_chnl_tag[i], tag_chnl_chnl[i], tag_chnl_sz[i], tag_chnl_last[i], tag_chnl_misc[i]};
128
+ assign tag_rrsp_ready[i] = tag_chnl_ready[i];
129
+
130
+ end
131
+ endgenerate
132
+ /* -------Generate block{end}------- */
133
+
134
+ /* -------Reordered TAG info stored in RAM{begin}------- */
135
+ integer j;
136
+ always @(posedge dma_clk, negedge rst_n) begin
137
+ if (~rst_n) begin
138
+ for (j = 0; j < `TAG_NUM; j = j+1) begin
139
+ rebuf_log_sram_tag[j] <= `TD 1'd0;
140
+ rebuf_log_sram_len[j] <= `TD {`DW_LEN_WIDTH{1'd0}};
141
+ end
142
+ end
143
+ else begin
144
+ if (nxt_match_valid & nxt_match_ready & (st_rd_rsp_wen & st_rd_rsp_rdy & st_rd_rsp_last)) begin
145
+ rebuf_log_sram_tag[nxt_match_tag] <= `TD 1'd0;
146
+ rebuf_log_sram_len[nxt_match_tag] <= `TD {`DW_LEN_WIDTH{1'd0}};
147
+ rebuf_log_sram_tag[st_rd_rsp_tag] <= `TD 1'd1;
148
+ rebuf_log_sram_len[st_rd_rsp_tag] <= `TD rebuf_log_sram_len[st_rd_rsp_tag] + st_rd_rsp_dlen;
149
+ end
150
+ else if (nxt_match_valid & nxt_match_ready) begin /* clear the info before entering the forward state */
151
+ rebuf_log_sram_tag[nxt_match_tag] <= `TD 1'd0;
152
+ rebuf_log_sram_len[nxt_match_tag] <= `TD {`DW_LEN_WIDTH{1'd0}};
153
+ end
154
+ else if (st_rd_rsp_wen & st_rd_rsp_rdy & st_rd_rsp_last) begin /* store the info only when the last cycle of the storage */
155
+ rebuf_log_sram_tag[st_rd_rsp_tag] <= `TD 1'd1;
156
+ rebuf_log_sram_len[st_rd_rsp_tag] <= `TD rebuf_log_sram_len[st_rd_rsp_tag] + st_rd_rsp_dlen;
157
+ end
158
+ end
159
+ end
160
+ /* -------Reordered TAG info stored in RAM{end}------- */
161
+
162
+ /* --------Next rsp channel{begin}-------- */
163
+ st_mux #(
164
+ .CHNL_NUM ( `DMA_RD_CHNL_NUM ), // number of slave signals to arbit
165
+ .CHNL_NUM_LOG ( `DMA_RD_CHNL_NUM_LOG ),
166
+ .TUSER_WIDTH ( 1 ),
167
+ .TDATA_WIDTH ( CHNL_DATA_W )
168
+ ) st_mux_tag_chnl (
169
+ .clk ( dma_clk ), // i, 1
170
+ .rst_n ( rst_n ), // i, 1
171
+
172
+ /* -------Slave AXIS Interface{begin}------- */
173
+ .s_axis_mux_tvalid ( tag_chnl_valid ),
174
+ .s_axis_mux_tlast ( tag_chnl_valid ),
175
+ .s_axis_mux_tdata ( tag_chnl_data ),
176
+ .s_axis_mux_tuser ( {`DMA_RD_CHNL_NUM{1'b0}} ), // i, CHNL_NUM
177
+ .s_axis_mux_tready ( tag_chnl_ready ),
178
+ /* -------Slave AXIS Interface{end}------- */
179
+
180
+ /* ------- Master AXIS Interface{begin} ------- */
181
+ .m_axis_mux_tvalid ( nxt_match_valid ),
182
+ .m_axis_mux_tlast ( ),
183
+ .m_axis_mux_tdata ( {nxt_match_tag, nxt_match_chnl, nxt_match_sz, nxt_match_last, nxt_match_misc} ),
184
+ .m_axis_mux_tuser ( ),
185
+ .m_axis_mux_tready ( nxt_match_ready )
186
+ /* ------- Master AXIS Interface{end} ------- */
187
+
188
+ `ifdef SIMULATION
189
+ /* ------- Debug interface {begin}------- */
190
+ /* | reserved | idx | end | out |
191
+ * | 255:CHNL_NUM_LOG+2 | CHNL_NUM_LOG+2-1:2 | 1 | 0 |
192
+ */
193
+ ,.debug ( )
194
+ /* ------- Debug interface {end}------- */
195
+ `endif
196
+ );
197
+ /* --------Next rsp channel{end}-------- */
198
+
199
+ endmodule
ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/DMA/DMA_Read/tag_request.v ADDED
@@ -0,0 +1,180 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ `timescale 1ns / 100ps
2
+ //*************************************************************************
3
+ // > File Name: tag_request.v
4
+ // > Author : Kangning
5
+ // > Date : 2022-11-07
6
+ // > Note : tag_request, add tag to the read request.
7
+ //*************************************************************************
8
+
9
+ module tag_request #(
10
+
11
+ ) (
12
+ input wire dma_clk, // i, 1
13
+ input wire rst_n , // i, 1
14
+
15
+ /* ------- Connect to rd_req_arbiter module{begin} ------- */
16
+ /* AXI-Stream read request tuser, every read request contains only one beat.
17
+ * | chnl_num | Reserved | REQ_TYPE |Tag(inv)| address | Reserved | DW length | first BE | last BE |
18
+ * | 127:120 | 119:108 | 107:104 | 103:96 | 95:32 | 31:19 | 18:8 | 7:4 | 3:0 |
19
+ */
20
+ input wire axis_rreq_tvalid, // i, 1
21
+ input wire axis_rreq_tlast , // i, 1
22
+ input wire [`DMA_DATA_W -1:0] axis_rreq_tdata , // i, `DMA_DATA_W
23
+ input wire [`AXIS_TUSER_W-1:0] axis_rreq_tuser , // i, `AXIS_TUSER_W
24
+ input wire [`DMA_KEEP_W -1:0] axis_rreq_tkeep , // i, `DMA_KEEP_W
25
+ output wire axis_rreq_tready, // o, 1
26
+ /* ------- Connect to rd_req_arbiter module{end} ------- */
27
+
28
+ /* -------tag request{begin}------- */
29
+ output wire tag_rreq_ready, // o, 1
30
+ output wire tag_rreq_last , // o, 1 ; Indicate the last sub-req for rd req
31
+ output wire [`DW_LEN_WIDTH-1:0] tag_rreq_sz , // o, `DW_LEN_WIDTH ; Request size(in dw unit) of this tag
32
+ output wire [8 -1:0] tag_rreq_chnl , // o, 8 ; channel number for this request
33
+ output wire [`TAG_MISC -1:0] tag_rreq_misc , // o, `TAG_MISC ; Including addr && dw empty info
34
+ input wire [`TAG_NUM_LOG -1:0] tag_rreq_tag , // i, `TAG_NUM_LOG
35
+ input wire tag_rreq_valid, // i, 1
36
+ /* -------tag request{end}------- */
37
+
38
+ /* -------axis read request interface{begin}------- */
39
+ /* AXI-Stream read request tuser, interact with read request arbiter.
40
+ * Only valid in first beat of a packet
41
+ * | Reserved | REQ_TYPE | Tag | address | Reserved | DW length | first BE | last BE |
42
+ * | 127:108 | 107:104 | 103:96 | 95:32 | 31:19 | 18:8 | 7:4 | 3:0 |
43
+ */
44
+ output wire axis_rreq_tag_tvalid, // o, 1
45
+ output wire axis_rreq_tag_tlast , // o, 1
46
+ output wire [`DMA_DATA_W -1:0] axis_rreq_tag_tdata , // o, `DMA_DATA_W
47
+ output wire [`AXIS_TUSER_W-1:0] axis_rreq_tag_tuser , // o, `AXIS_TUSER_W
48
+ output wire [`DMA_KEEP_W -1:0] axis_rreq_tag_tkeep , // o, `DMA_KEEP_W
49
+ input wire axis_rreq_tag_tready // i, 1
50
+ /* -------axis read request interface{end}------- */
51
+
52
+ `ifdef PCIEI_APB_DBG
53
+ /* -------APB reated signal{begin}------- */
54
+ ,output wire [`TAG_REQ_SIGNAL_W-1:0] dbg_signal // o, `TAG_REQ_SIGNAL_W
55
+ /* -------APB reated signal{end}------- */
56
+ `endif
57
+ );
58
+
59
+ /* -------State relevant in FSM{begin}------- */
60
+ wire rreq_taged_tvalid;
61
+ wire rreq_taged_tlast ;
62
+ wire [`AXIS_TUSER_W-1:0] rreq_taged_tuser ;
63
+ wire [`DMA_DATA_W -1:0] rreq_taged_tdata ;
64
+ wire rreq_taged_tready;
65
+ /* -------State relevant in FSM{end}------- */
66
+
67
+ /* -------Head decode{begin}------- */
68
+ wire [8 -1:0] chnl_num ;
69
+ wire last_sub_req;
70
+ wire [`DW_LEN_WIDTH-1:0] dw_len ;
71
+ wire [4 -1:0] req_type ;
72
+ wire [`DMA_ADDR_WIDTH-1:0] addr_align;
73
+
74
+ wire [`FIRST_BE_WIDTH-1:0] first_be ;
75
+ wire [`LAST_BE_WIDTH -1:0] last_be ;
76
+ wire [1:0] first_empty ; // Number of invalid bytes in first Double word
77
+ wire [1:0] last_empty ; // Number of invalid bytes in last Double word
78
+
79
+ wire [`DMA_ADDR_WIDTH-1:0] addr_unalign;
80
+ wire [5 -1:0] empty ;
81
+ /* -------Head decode{end}------- */
82
+
83
+ /* -------------------------------------------------------------------------------------------------- */
84
+
85
+ `ifdef PCIEI_APB_DBG
86
+ /* -------APB reated signal{begin}------- */
87
+ assign dbg_signal = { // 556
88
+ rreq_taged_tvalid, rreq_taged_tlast, rreq_taged_tuser, rreq_taged_tdata, rreq_taged_tready, // 387
89
+ chnl_num, last_sub_req, dw_len, req_type, addr_align, // 88
90
+ first_be, last_be, first_empty, last_empty, // 12
91
+ addr_unalign, empty // 69
92
+ /* -------Head decode{end}------- */
93
+ };
94
+ /* -------APB reated signal{end}------- */
95
+ `endif
96
+
97
+ /* -------Head decode{begin}------- */
98
+ /* AXI-Stream read request tuser, every read request contains only one beat.
99
+ * | chnl_num | Reserved | REQ_TYPE |Tag(inv)| address | Reserved | DW length | first BE | last BE |
100
+ * | 127:120 | 119:108 | 107:104 | 103:96 | 95:32 | 31:19 | 18:8 | 7:4 | 3:0 |
101
+ */
102
+ assign chnl_num = axis_rreq_tuser[127:120];
103
+ assign last_sub_req = axis_rreq_tuser[119];
104
+ assign dw_len = axis_rreq_tuser[18 :8 ];
105
+ assign req_type = axis_rreq_tuser[107:104];
106
+ assign addr_align = axis_rreq_tuser[95:32];
107
+ assign first_be = axis_rreq_tuser[7:4];
108
+ assign last_be = axis_rreq_tuser[3:0];
109
+
110
+ assign first_empty = first_be[0] ? 2'd0 :
111
+ first_be[1] ? 2'd1 :
112
+ first_be[2] ? 2'd2 :
113
+ first_be[3] ? 2'd3 :
114
+ 2'd0; // unlikely
115
+ assign last_empty = (dw_len == 1) ?
116
+ (first_be[3] ? 2'd0 :
117
+ first_be[2] ? 2'd1 :
118
+ first_be[1] ? 2'd2 : 2'd3) :
119
+ ({2{(last_be == 4'b1111)}} & 2'd0 |
120
+ {2{(last_be == 4'b0001)}} & 2'd3 |
121
+ {2{(last_be == 4'b0011)}} & 2'd2 |
122
+ {2{(last_be == 4'b0111)}} & 2'd1);
123
+
124
+ assign addr_unalign = {addr_align[`DMA_ADDR_WIDTH-1:2], first_empty};
125
+ assign empty = first_empty + last_empty;
126
+ // assign byte_len = (dw_len << 2) - first_empty - last_empty;
127
+ /* -------Head decode{end}------- */
128
+
129
+ /* --------input request{begin}-------- */
130
+ assign axis_rreq_tready = tag_rreq_valid & rreq_taged_tready;
131
+ /* --------input request{end}-------- */
132
+
133
+ /* --------Tag request{begin}-------- */
134
+ assign tag_rreq_ready = axis_rreq_tvalid & rreq_taged_tready;
135
+ assign tag_rreq_last = last_sub_req;
136
+ assign tag_rreq_sz = dw_len ;
137
+ assign tag_rreq_chnl = chnl_num ;
138
+ assign tag_rreq_misc = {addr_unalign[6:0], empty};
139
+ /* --------Tag request{end}-------- */
140
+
141
+ /* --------read request output {begin}-------- */
142
+ /* AXI-Stream read request tuser, every read request contains only one beat.
143
+ * | Reserved | REQ_TYPE | Tag | address | Reserved | DW length | first BE | last BE |
144
+ * | 127:108 | 107:104 | 103:96 | 95:32 | 31:19 | 18:8 | 7:4 | 3:0 |
145
+ */
146
+ assign rreq_taged_tvalid = tag_rreq_valid & axis_rreq_tvalid;
147
+ assign rreq_taged_tlast = 1'd1;
148
+ assign rreq_taged_tdata = {`DMA_DATA_W{1'd0}};
149
+ assign rreq_taged_tuser = {20'd0, req_type, {`TAG_EMPTY+`TAG_WIDTH-`TAG_NUM_LOG{1'd0}}, tag_rreq_tag, axis_rreq_tuser[95:0]};
150
+ /* --------read request output {end}-------- */
151
+
152
+
153
+ /* -------Read Request FIFO{begin}------- */
154
+ st_reg #(
155
+ .TUSER_WIDTH ( `AXIS_TUSER_W ),
156
+ .TDATA_WIDTH ( `DMA_DATA_W )
157
+ ) st_rd_req (
158
+ .clk ( dma_clk ), // i, 1
159
+ .rst_n ( rst_n ), // i, 1
160
+
161
+ /* -------input axis-like interface{begin}------- */
162
+ .axis_tvalid ( rreq_taged_tvalid ), // i, 1
163
+ .axis_tlast ( rreq_taged_tlast ), // i, 1
164
+ .axis_tuser ( rreq_taged_tuser ), // i, TUSER_WIDTH
165
+ .axis_tdata ( rreq_taged_tdata ), // i, TDATA_WIDTH
166
+ .axis_tready ( rreq_taged_tready ), // o, 1
167
+ /* -------input axis-like interface{end}------- */
168
+
169
+ /* -------output in_reg inteface{begin}------- */
170
+ .axis_reg_tvalid ( axis_rreq_tag_tvalid ), // o, 1
171
+ .axis_reg_tlast ( axis_rreq_tag_tlast ), // o, 1
172
+ .axis_reg_tuser ( axis_rreq_tag_tuser ), // o, TUSER_WIDTH
173
+ .axis_reg_tdata ( axis_rreq_tag_tdata ), // o, TDATA_WIDTH
174
+ .axis_reg_tready ( axis_rreq_tag_tready ) // i, 1
175
+ /* -------output in_reg inteface{end}------- */
176
+ );
177
+ assign axis_rreq_tag_tkeep = {`DMA_KEEP_W{1'd0}};
178
+ /* -------Read Request FIFO{end}------- */
179
+
180
+ endmodule
ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/DMA/DMA_Write/wreq_align.v ADDED
@@ -0,0 +1,357 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ `timescale 1ns / 100ps
2
+ //*************************************************************************
3
+ // > File Name : wreq_align.v
4
+ // > Author : Kangning
5
+ // > Date : 2021-09-16
6
+ // > Note : transform pkt to dw aligned
7
+ // > ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
8
+ // > ^ ^
9
+ // > ^ ########## ########### ^
10
+ // > ^ # #------># tmp_reg # ############ ^
11
+ // > ^ ------># in_reg # ###########-----># # ^
12
+ // > ^ # # # out_wire #----> ^
13
+ // > ^ ##########-----------------------># # ^
14
+ // > ^ ############ ^
15
+ // > ^ ^
16
+ // > ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
17
+ //*************************************************************************
18
+
19
+
20
+ module wreq_align #(
21
+
22
+ ) (
23
+ input wire clk , // i, 1
24
+ input wire rst_n , // i, 1
25
+
26
+ /* -------dma write request interface{begin}------- */
27
+ /* *_head of DMA interface (interact with RDMA modules),
28
+ * valid only in first beat of a packet.
29
+ * When Transmiting msi-x interrupt message, 'Byte length'
30
+ * should be 0, 'address' means the address of msi-x, and
31
+ * msi-x data locates in *_data[31:0].
32
+ * | Resvd | Req Type | address | Reserved | Byte length |
33
+ * | | (wr,int) | (msi-x addr) | | (0 for int) |
34
+ * |-------|----------|--------------|----------|-------------|
35
+ * |127:100| 99:96 | 95:32 | 31:13 | 12:0 |
36
+ */
37
+ input wire dma_valid , // i, 1
38
+ input wire dma_last , // i, 1
39
+ input wire [`DMA_HEAD_W-1:0] dma_head , // i, `DMA_HEAD_W
40
+ input wire [`DMA_DATA_W-1:0] dma_data , // i, `DMA_DATA_W
41
+ output wire dma_ready , // o, 1
42
+ /* -------dma write request interface{end}------- */
43
+
44
+ /* -------aligned write request intrface{begin}------- */
45
+ /* AXI-Stream write request tuser, only valid in first beat of a packet
46
+ * | Reserved | REQ_TYPE | Tag | address | Reserved | DW length | first BE | last BE |
47
+ * | 127:108 | 107:104 | 103:96 | 95:32 | 31:19 | 18:8 | 7:4 | 3:0 |
48
+ * or
49
+ * AXI-Stream interrupt request tuser, only valid in first beat of a packet
50
+ * | Reserved | REQ_TYPE | Resv | address | Reserved |
51
+ * | 127:108 | 107:104 | 103:96 | 95:32 | 31:0 |
52
+ */
53
+ output wire align_valid, // o, 1
54
+ output wire align_last , // o, 1
55
+ output wire [`AXIS_TUSER_W-1:0] align_user , // o, `AXIS_TUSER_W
56
+ output wire [`DMA_DATA_W -1:0] align_data , // o, `DMA_DATA_W
57
+ input wire align_ready // i, 1
58
+ /* -------aligned write request intrface{end}------- */
59
+
60
+ `ifdef PCIEI_APB_DBG
61
+ /* -------APB reated signal{begin}------- */
62
+ ,output wire [`WREQ_ALIGN_SIGNAL_W-1:0] dbg_signal // o, `WREQ_ALIGN_SIGNAL_W
63
+ /* -------APB reated signal{end}------- */
64
+ `endif
65
+ );
66
+
67
+ /* -------relate to in_reg{begin}------- */
68
+ reg in_reg_vld ; // read valid from input register
69
+ reg [`DMA_HEAD_W-1:0] in_reg_head;
70
+ reg [`DMA_DATA_W-1:0] in_reg_data;
71
+ wire in_reg_rdy ;
72
+
73
+ reg in_reg_sop ; // Indicate the start of a pkt
74
+ /* -------relate to in_reg{end}------- */
75
+
76
+ /* -------DW Dealignment FSM{begin}------- */
77
+ localparam FIRST_BEAT = 3'b001, // This state emits first beat (or only bits) of packet.
78
+ MID_BEAT = 3'b010, // This state emits middle beat of packet.
79
+ LAST_BEAT = 3'b100; // This state emits last beat of packet, in this state,
80
+ // in_reg_rdy is not asserted if all data comes from tmp_reg.
81
+
82
+ reg [2:0] cur_state;
83
+ reg [2:0] nxt_state;
84
+
85
+ wire is_first_beat, is_mid_beat, is_last_beat;
86
+
87
+ /* Fake last beat for align_* signal. If
88
+ * not aligned, this beat should have been
89
+ * the last beat. But actually, it's not.
90
+ * Note that this signal is different
91
+ * from 'in_reg_last'
92
+ */
93
+ wire fake_align_last;
94
+
95
+ /*
96
+ * indicate that next beat is the last beat.
97
+ * only valid in 'FIRST_BEAT' and 'MID_BEAT'
98
+ * state. */
99
+ wire next_align_last;
100
+
101
+ /* Indicate that data in last beat is all from tmp_reg.
102
+ * This wire is valid in the whole req. */
103
+ wire is_all_from_tmp;
104
+
105
+ /* dw size for last beat. This wire is valid in
106
+ * the whole req. */
107
+ wire [$clog2(`DMA_KEEP_W)-1:0] dw_for_last_beat;
108
+
109
+ /* Packet trans finished, and req_clear all relevant
110
+ * regs. */
111
+ wire req_clear;
112
+
113
+ /* align_* signal goes out one beat */
114
+ wire req_go_out;
115
+ /* -------DW Dealignment FSM{end}------- */
116
+
117
+ /* -------Head gennerator{begin}------- */
118
+ wire [3:0] req_type;
119
+ wire [`DMA_ADDR_WIDTH-1:0] addr ;
120
+ wire [`DMA_LEN_WIDTH -1:0] byte_len;
121
+ wire [`DMA_ADDR_WIDTH-1:0] aligned_addr ;
122
+ wire [`DMA_LEN_WIDTH -1:0] aligned_byte_len;
123
+ wire [`DW_LEN_WIDTH -1:0] dw_len ;
124
+ wire [`FIRST_BE_WIDTH-1:0] first_be;
125
+ wire [`LAST_BE_WIDTH -1:0] last_be ;
126
+ wire [2:0] last_bytes;
127
+ wire [`AXIS_TUSER_W-1:0] wreq_user;
128
+ wire [`AXIS_TUSER_W-1:0] int_user ;
129
+
130
+ reg [`DW_LEN_WIDTH-1:0] dw_cnt ;
131
+ wire [`DW_LEN_WIDTH-1:0] dw_left;
132
+ /* -------Head generator{end}------- */
133
+
134
+ /* -------tmp_reg logic{begin}------- */
135
+ reg [31:0] tmp_reg_data;
136
+ /* -------tmp_reg logic{end}------- */
137
+
138
+ /* -------relate to out_reg{begin}------- */
139
+ reg [`DMA_DATA_W-1:0] in_out_data; // transform data between tmp_reg and out_reg
140
+ /* -------relate to tmp_reg{end}------- */
141
+
142
+ //---------------------------------------------------------------------------------------------------------------------------
143
+
144
+ `ifdef PCIEI_APB_DBG
145
+ /* -------APB reated signal{begin}------- */
146
+ assign dbg_signal = { // 1150
147
+ in_reg_vld, in_reg_head, in_reg_data, in_reg_rdy, // 386
148
+ in_reg_sop, // 1
149
+ cur_state, nxt_state, // 6
150
+ is_first_beat, is_mid_beat, is_last_beat, // 3
151
+ fake_align_last, // 1
152
+ next_align_last, // 1
153
+ is_all_from_tmp, // 1
154
+ dw_for_last_beat, // 3
155
+ req_clear, // 1
156
+ req_go_out, // 1
157
+
158
+ req_type, addr, byte_len, aligned_addr, aligned_byte_len,
159
+ dw_len, first_be, last_be, last_bytes, wreq_user, int_user, // 436
160
+
161
+ dw_cnt, dw_left, // 22
162
+ tmp_reg_data, // 32
163
+ in_out_data // 256
164
+ };
165
+ /* -------APB reated signal{end}------- */
166
+ `endif
167
+
168
+ /* -------in_reg logic{begin}------- */
169
+ always @(posedge clk, negedge rst_n) begin
170
+ if (~rst_n) begin
171
+ in_reg_sop <= `TD 1;
172
+ end
173
+ else if (dma_valid & dma_ready & dma_last) begin
174
+ in_reg_sop <= `TD 1;
175
+ end
176
+ else if (dma_valid & dma_ready & in_reg_sop) begin
177
+ in_reg_sop <= `TD 0;
178
+ end
179
+ end
180
+
181
+ always @(posedge clk, negedge rst_n) begin
182
+ if (~rst_n) begin
183
+ in_reg_head <= `TD 0;
184
+ end
185
+ else if (dma_valid & dma_ready & in_reg_sop) begin
186
+ in_reg_head <= `TD dma_head;
187
+ end
188
+ else if (req_clear) begin // after trans finished, in_reg_head is set to 0
189
+ in_reg_head <= `TD 0;
190
+ end
191
+ end
192
+
193
+ always @(posedge clk, negedge rst_n) begin
194
+ if (~rst_n) begin
195
+ in_reg_vld <= `TD 0;
196
+ in_reg_data <= `TD 0;
197
+ end
198
+ else if (dma_valid & dma_ready) begin // write en & not full
199
+ in_reg_vld <= `TD 1;
200
+ in_reg_data <= `TD dma_data;
201
+ end
202
+ else if (in_reg_rdy & in_reg_vld) begin // read en & not empty
203
+ in_reg_vld <= `TD 0;
204
+ in_reg_data <= `TD 0;
205
+ end
206
+ end
207
+
208
+ assign dma_ready = !in_reg_vld | in_reg_rdy; // empty | going to empty
209
+ /* -------in_reg logic{end}------- */
210
+
211
+ /* -------Head generator{begin}------ */
212
+ assign req_type = in_reg_head[99:96];
213
+ assign addr = in_reg_head[95:32];
214
+ assign byte_len = in_reg_head[12:0];
215
+ assign aligned_addr = {addr[`DMA_ADDR_WIDTH-1:2], 2'd0};
216
+ assign aligned_byte_len = byte_len + addr[1:0];
217
+ assign dw_len = (aligned_byte_len >> 2) + | aligned_byte_len[1:0];
218
+
219
+ // In our implementation, uncontinuous first_be and last_be are forbidden.
220
+ // In our implementation, zero-payload are not allowed, first_be would never be 4'b0000.
221
+ assign first_be = ({4{addr[1:0] == 2'b00}} & 4'b1111) |
222
+ ({4{addr[1:0] == 2'b01}} & 4'b1110) |
223
+ ({4{addr[1:0] == 2'b10}} & 4'b1100) |
224
+ ({4{addr[1:0] == 2'b11}} & 4'b1000);
225
+ assign last_be = ({4{aligned_byte_len[1:0] == 2'b00}} & 4'b1111) |
226
+ ({4{aligned_byte_len[1:0] == 2'b01}} & 4'b0001) |
227
+ ({4{aligned_byte_len[1:0] == 2'b10}} & 4'b0011) |
228
+ ({4{aligned_byte_len[1:0] == 2'b11}} & 4'b0111);
229
+ assign last_bytes = (aligned_byte_len[1:0] == 2'b00) ? 3'b100 : {1'b0, aligned_byte_len[1:0]};
230
+ /* AXI-Stream write request tuser, only valid in first beat of a packet
231
+ * | Reserved | REQ_TYPE | Tag | address | Reserved | DW length | first BE | last BE |
232
+ * | 127:108 | 107:104 | 103:96 | 95:32 | 31:19 | 18:8 | 7:4 | 3:0 |
233
+ */
234
+ assign wreq_user = {20'd0, `DMA_WRITE_REQ, 8'd0, aligned_addr, 13'd0, dw_len, first_be, last_be};
235
+
236
+ /* AXI-Stream interrupt request tuser, only valid in first beat of a packet
237
+ * | Reserved | REQ_TYPE | Resv | address | Reserved |
238
+ * | 127:108 | 107:104 | 103:96 | 95:32 | 31:0 |
239
+ */
240
+ assign int_user = {20'd0, req_type, 8'd0, addr, 32'd0};
241
+
242
+ assign dw_left = dw_len - dw_cnt;
243
+ always @(posedge clk, negedge rst_n) begin
244
+ if (~rst_n) begin
245
+ dw_cnt <= `TD 0;
246
+ end
247
+ else if (req_clear) begin
248
+ dw_cnt <= `TD 0;
249
+ end
250
+ else if (req_go_out) begin
251
+ dw_cnt <= `TD dw_cnt + `DMA_KEEP_W;
252
+ end
253
+ end
254
+ /* -------Head generator{end}------ */
255
+
256
+ /* -------tmp_reg logic{begin}------- */
257
+ always @(posedge clk, negedge rst_n) begin
258
+ if (~rst_n) begin
259
+ tmp_reg_data <= `TD 0;
260
+ end
261
+ else if (req_clear) begin // Clear tmp_reg, in case
262
+ // next pkt contains invalid data.
263
+ tmp_reg_data <= `TD 0;
264
+ end
265
+ else if (req_go_out) begin // Update tmp_reg when it goes out
266
+ tmp_reg_data <= `TD in_reg_data[(`DMA_DATA_W-1)-:32];
267
+ end
268
+ end
269
+ /* -------tmp_reg logic{end}------- */
270
+
271
+ /* -------out_reg logic{begin}------- */
272
+ assign in_reg_rdy = (is_first_beat | is_mid_beat) & align_ready & !fake_align_last |
273
+ (is_last_beat & align_ready);
274
+
275
+ assign align_valid = in_reg_vld |
276
+ !in_reg_vld & is_last_beat & is_all_from_tmp;
277
+ assign align_last = align_valid & (dw_left <= `DMA_KEEP_W);
278
+ assign align_user = (req_type == `DMA_INT_REQ) ? int_user : wreq_user;
279
+ assign align_data = (req_type == `DMA_INT_REQ) ? in_reg_data : in_out_data;
280
+ always @(*) begin
281
+ if (is_last_beat & is_all_from_tmp) begin
282
+ case (addr[1:0])
283
+ 2'd0: in_out_data = in_reg_data;
284
+ 2'd1: in_out_data = {{`DMA_DATA_W - 8 * 1{1'd0}}, tmp_reg_data[(32 - 1)-:(8 * 1)]};
285
+ 2'd2: in_out_data = {{`DMA_DATA_W - 8 * 2{1'd0}}, tmp_reg_data[(32 - 1)-:(8 * 2)]};
286
+ 2'd3: in_out_data = {{`DMA_DATA_W - 8 * 3{1'd0}}, tmp_reg_data[(32 - 1)-:(8 * 3)]};
287
+ endcase
288
+ end
289
+ else if (is_first_beat | is_mid_beat | is_last_beat) begin
290
+ case (addr[1:0])
291
+ 2'd0: in_out_data = in_reg_data;
292
+ 2'd1: in_out_data = {in_reg_data[`DMA_DATA_W - 8 * 1 - 1: 0], tmp_reg_data[(32 - 1)-:(8 * 1)]};
293
+ 2'd2: in_out_data = {in_reg_data[`DMA_DATA_W - 8 * 2 - 1: 0], tmp_reg_data[(32 - 1)-:(8 * 2)]};
294
+ 2'd3: in_out_data = {in_reg_data[`DMA_DATA_W - 8 * 3 - 1: 0], tmp_reg_data[(32 - 1)-:(8 * 3)]};
295
+ endcase
296
+ end
297
+ else begin
298
+ in_out_data = 0;
299
+ end
300
+ end
301
+ /* -------out_reg logic{end}------- */
302
+
303
+ /* -------DW Dealignment FSM{begin}------- */
304
+ /******************** Stage 1: State Register **********************/
305
+ assign fake_align_last = is_all_from_tmp & next_align_last;
306
+ assign next_align_last = (dw_left <= `DMA_KEEP_W * 2) & (dw_left > `DMA_KEEP_W);
307
+ assign is_all_from_tmp = (dw_for_last_beat == 1) & (last_bytes <= addr[1:0]);
308
+ assign dw_for_last_beat = dw_len[$clog2(`DMA_KEEP_W)-1:0];
309
+ assign req_clear = req_go_out & align_last;
310
+ assign req_go_out = align_valid & align_ready;
311
+
312
+ assign is_first_beat = (cur_state == FIRST_BEAT);
313
+ assign is_mid_beat = (cur_state == MID_BEAT );
314
+ assign is_last_beat = (cur_state == LAST_BEAT );
315
+
316
+ always @(posedge clk, negedge rst_n) begin
317
+ if(~rst_n)
318
+ cur_state <= `TD FIRST_BEAT;
319
+ else
320
+ cur_state <= `TD nxt_state;
321
+ end
322
+
323
+ /******************** Stage 2: State Transition **********************/
324
+
325
+ always @(*) begin
326
+ case(cur_state)
327
+ FIRST_BEAT: begin
328
+ if (req_clear) // Imlying the only beat
329
+ nxt_state = FIRST_BEAT;
330
+ else if (req_go_out & next_align_last)
331
+ nxt_state = LAST_BEAT;
332
+ else if (req_go_out)
333
+ nxt_state = MID_BEAT;
334
+ else
335
+ nxt_state = FIRST_BEAT;
336
+ end
337
+ MID_BEAT: begin
338
+ if (req_go_out & next_align_last)
339
+ nxt_state = LAST_BEAT;
340
+ else
341
+ nxt_state = MID_BEAT;
342
+ end
343
+ LAST_BEAT: begin
344
+ if (req_clear)
345
+ nxt_state = FIRST_BEAT;
346
+ else
347
+ nxt_state = LAST_BEAT;
348
+ end
349
+ default: begin
350
+ nxt_state = FIRST_BEAT;
351
+ end
352
+ endcase
353
+ end
354
+ /******************** Stage 3: Output **********************/
355
+ /* -------DW Dealignment FSM{end}------- */
356
+
357
+ endmodule
ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/DMA/DMA_Write/wreq_split.v ADDED
@@ -0,0 +1,319 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ `timescale 1ns / 100ps
2
+ //*************************************************************************
3
+ // > File Name : wreq_split.v
4
+ // > Author : Kangning
5
+ // > Date : 2021-09-16
6
+ // > Note : split one wr req into multiply small subreq
7
+ //*************************************************************************
8
+ `define DMA_KEEP_MASK {`DMA_KEEP_W{1'd1}}
9
+
10
+ module wreq_split #(
11
+
12
+ ) (
13
+ input wire clk , // i, 1
14
+ input wire rst_n, // i, 1
15
+
16
+ input wire [2:0] max_pyld_sz, // i, 3
17
+
18
+ /* -------aligned write request intrface{begin}------- */
19
+ /* AXI-Stream write request tuser, only valid in first beat of a packet
20
+ * | Reserved | REQ_TYPE | Tag | address | Reserved | DW length | first BE | last BE |
21
+ * | 127:108 | 107:104 | 103:96 | 95:32 | 31:19 | 18:8 | 7:4 | 3:0 |
22
+ * or
23
+ * AXI-Stream interrupt request tuser, only valid in first beat of a packet
24
+ * | Reserved | REQ_TYPE | Resv | address | Reserved |
25
+ * | 127:108 | 107:104 | 103:96 | 95:32 | 31:0 |
26
+ */
27
+ input wire align_valid, // i, 1
28
+ input wire align_last , // i, 1
29
+ input wire [`AXIS_TUSER_W-1:0] align_user , // i, `AXIS_TUSER_W
30
+ input wire [`DMA_DATA_W -1:0] align_data , // i, `DMA_DATA_W
31
+ output wire align_ready, // o, 1
32
+ /* -------aligned write request intrface{end}------- */
33
+
34
+ /* -------axis write request interface{begin}------- */
35
+ /* AXI-Stream write request tuser, only valid in first beat of a packet
36
+ * | Reserved | REQ_TYPE | Tag | address | Reserved | DW length | first BE | last BE |
37
+ * | 127:108 | 107:104 | 103:96 | 95:32 | 31:19 | 18:8 | 7:4 | 3:0 |
38
+ * or
39
+ * AXI-Stream interrupt request tuser, only valid in first beat of a packet
40
+ * | Reserved | REQ_TYPE | Resv | address | Reserved |
41
+ * | 127:108 | 107:104 | 103:96 | 95:32 | 31:0 |
42
+ */
43
+ output wire axis_wr_req_tvalid,
44
+ output wire axis_wr_req_tlast ,
45
+ output wire [`DMA_DATA_W -1:0] axis_wr_req_tdata ,
46
+ output wire [`AXIS_TUSER_W-1:0] axis_wr_req_tuser ,
47
+ output wire [`DMA_KEEP_W -1:0] axis_wr_req_tkeep ,
48
+ input wire axis_wr_req_tready
49
+ /* -------axis write request interface{end}------- */
50
+
51
+ `ifdef PCIEI_APB_DBG
52
+ /* -------APB reated signal{begin}------- */
53
+ ,output wire [`WREQ_SPLIT_SIGNAL_W-1:0] dbg_signal // o, `WREQ_SPLIT_SIGNAL_W
54
+ /* -------APB reated signal{end}------- */
55
+ `endif
56
+ );
57
+
58
+ /* -------Constant Value{begin}------- */
59
+ localparam MIN_DWORD_SZ_LOG = 5; // min dwords size for 128B axis packet (2 ^ 5 Dword)
60
+ wire [`DW_LEN_WIDTH-1:0] max_pyld_dw; // Maximum payload size in dw (in one sub req)
61
+ /* -------Constant Value{end}------- */
62
+
63
+ /* -------relate to in_reg{begin}------- */
64
+ reg in_reg_vld ; // read valid from input register
65
+ reg [`AXIS_TUSER_W-1:0] in_reg_user;
66
+ reg [`DMA_DATA_W -1:0] in_reg_data;
67
+ wire [`DMA_KEEP_W -1:0] in_reg_keep;
68
+ wire in_reg_rdy ;
69
+
70
+ reg in_reg_sop ; // Indicate the start of a pkt
71
+ /* -------relate to in_reg{end}------- */
72
+
73
+ /* -------Head relevant{begin}------- */
74
+ // align user decode
75
+ wire [`DW_LEN_WIDTH -1:0] dw_len ;
76
+ wire [`FIRST_BE_WIDTH-1:0] first_be;
77
+ wire [`LAST_BE_WIDTH -1:0] last_be ;
78
+ wire [`DMA_ADDR_WIDTH-1:0] addr ;
79
+ wire [3:0] req_type;
80
+
81
+ // axis_tuser decode
82
+ wire [`DW_LEN_WIDTH -1:0] sub_dw_len ;
83
+ wire [`FIRST_BE_WIDTH-1:0] sub_first_be;
84
+ wire [`LAST_BE_WIDTH -1:0] sub_last_be ;
85
+ wire [`DMA_ADDR_WIDTH-1:0] sub_addr ;
86
+
87
+ reg [`DW_LEN_WIDTH -1:0] dw_cnt , sub_dw_cnt ;
88
+ wire [`DW_LEN_WIDTH -1:0] dw_left, sub_dw_left;
89
+ wire [`DW_LEN_WIDTH -1:0] dw_left_dyn; // how many dw left, count down in dynamically
90
+
91
+ wire [`AXIS_TUSER_W-1:0] int_tuser, wreq_tuser;
92
+ /* -------Head relevant{end}------- */
93
+
94
+ /* -------Split packet{begin}------- */
95
+ wire first_sub_req, last_sub_req;
96
+ wire next_req_last, next_sub_last;
97
+ /* -------Split packet{end}------- */
98
+
99
+ /* -------State relevant in FSM{begin}------- */
100
+ localparam IDLE = 4'b0001,
101
+ TX = 4'b0010, // Transmit normal beat.
102
+ SUB_LAST = 4'b0100, // TX the last beat of sub req.
103
+ REQ_LAST = 4'b1000; // TX the last beat of the enire req
104
+ reg [3:0] cur_state;
105
+ reg [3:0] nxt_state;
106
+ wire is_idle, is_tx, is_sub_last, is_req_last;
107
+
108
+ wire beat_go ; // When asserted, one beat go out of axis_* interface
109
+ wire sub_clear; // When asserted, last beat of sub req are forwarded
110
+ wire req_clear; // When asserted, last beat of entire req are forwarded
111
+ /* -------State relevant in FSM{end}------- */
112
+
113
+ //---------------------------------------------------------------------------------------------------------------------------
114
+
115
+ `ifdef PCIEI_APB_DBG
116
+ /* -------APB reated signal{begin}------- */
117
+ assign dbg_signal = { // 906
118
+ max_pyld_dw, // 11
119
+ in_reg_vld, in_reg_user, in_reg_data, in_reg_keep, in_reg_rdy, // 394
120
+ in_reg_sop, // 1
121
+ dw_len, first_be, last_be, addr, req_type, // 87
122
+ sub_dw_len, sub_first_be, sub_last_be, sub_addr, // 83
123
+ dw_cnt, sub_dw_cnt, // 22
124
+ dw_left, sub_dw_left, // 22
125
+ dw_left_dyn, // 11
126
+ int_tuser, wreq_tuser, // 256
127
+ first_sub_req, last_sub_req, // 2
128
+ next_req_last, next_sub_last, // 2
129
+ cur_state, nxt_state, // 8
130
+ is_idle, is_tx, is_sub_last, is_req_last, // 4
131
+ beat_go, sub_clear, req_clear // 3
132
+ };
133
+ /* -------APB reated signal{end}------- */
134
+ `endif
135
+
136
+ /* -------Constant Value{begin}------- */
137
+ assign max_pyld_dw = 1'd1 << (MIN_DWORD_SZ_LOG + max_pyld_sz);
138
+ /* -------Constant Value{end}------- */
139
+
140
+ /* -------in_reg logic{begin}------- */
141
+ always @(posedge clk, negedge rst_n) begin
142
+ if (~rst_n) begin
143
+ in_reg_sop <= `TD 1;
144
+ end
145
+ else if (align_valid & align_ready & align_last) begin
146
+ in_reg_sop <= `TD 1;
147
+ end
148
+ else if (align_valid & align_ready & in_reg_sop) begin
149
+ in_reg_sop <= `TD 0;
150
+ end
151
+ end
152
+
153
+ always @(posedge clk, negedge rst_n) begin
154
+ if (~rst_n) begin
155
+ in_reg_user <= `TD 0;
156
+ end
157
+ else if (align_valid & align_ready & in_reg_sop) begin
158
+ in_reg_user <= `TD align_user;
159
+ end
160
+ else if (req_clear) begin // after trans finished, in_reg_user is set to 0
161
+ in_reg_user <= `TD 0;
162
+ end
163
+ end
164
+
165
+ always @(posedge clk, negedge rst_n) begin
166
+ if (~rst_n) begin
167
+ in_reg_vld <= `TD 0;
168
+ in_reg_data <= `TD 0;
169
+ end
170
+ else if (align_valid & align_ready) begin // write en & not full
171
+ in_reg_vld <= `TD 1;
172
+ in_reg_data <= `TD align_data;
173
+ end
174
+ else if (in_reg_rdy & in_reg_vld) begin // read en & not empty
175
+ in_reg_vld <= `TD 0;
176
+ in_reg_data <= `TD 0;
177
+ end
178
+ end
179
+
180
+ assign align_ready = !in_reg_vld | in_reg_rdy; // empty | going to empty
181
+ /* -------in_reg logic{end}------- */
182
+
183
+ /* -------tuser logic{begin}------- */
184
+ assign dw_len = in_reg_user[18:8 ];
185
+ assign first_be = in_reg_user[7 :4 ];
186
+ assign last_be = in_reg_user[3 :0 ];
187
+ assign addr = in_reg_user[95:32];
188
+ assign req_type = in_reg_user[107:104];
189
+
190
+ assign sub_dw_len = last_sub_req ? dw_left : max_pyld_dw;
191
+ // assign sub_first_be = ? first_be : 4'b1111;
192
+ // assign sub_last_be = last_sub_req ? last_be : 4'b1111;
193
+ assign sub_addr = addr + (dw_cnt << 2);
194
+
195
+ assign sub_first_be = (dw_len == 1) ? (first_be & last_be) : // when the req only has one DW
196
+ (sub_dw_len == 1) ? (4'b1111 & last_be) : // when the sub_req has one DW.
197
+ first_sub_req ? first_be : 4'b1111;
198
+ assign sub_last_be = (sub_dw_len == 1) ? 4'b0000 : // when the payload has one DW, last_be should be 0.
199
+ last_sub_req ? last_be : 4'b1111;
200
+
201
+ assign wreq_tuser = {20'd0, req_type, 8'd0, sub_addr, 13'd0, sub_dw_len, sub_first_be, sub_last_be};
202
+ assign int_tuser = {20'd0, req_type, 8'd0, sub_addr, 32'd0};
203
+ /* -------tuser logic{end}------- */
204
+
205
+ /* -------Split packet{begin}------- */
206
+ assign first_sub_req = dw_cnt == 0;
207
+ assign last_sub_req = dw_left <= max_pyld_dw;
208
+ assign next_req_last = (dw_left_dyn <= `DMA_KEEP_W * 2) & (dw_left_dyn > `DMA_KEEP_W);
209
+ assign next_sub_last = (sub_dw_left > `DMA_KEEP_W) & (sub_dw_left <= (`DMA_KEEP_W * 2));
210
+
211
+ assign dw_left_dyn = dw_left - sub_dw_cnt;
212
+ assign dw_left = dw_len - dw_cnt;
213
+ always @(posedge clk, negedge rst_n) begin
214
+ if (~rst_n) begin
215
+ dw_cnt <= `TD 0;
216
+ end
217
+ else if (req_clear) begin
218
+ dw_cnt <= `TD 0;
219
+ end
220
+ else if (sub_clear) begin // beat_go & is_sub_last
221
+ dw_cnt <= `TD dw_cnt + max_pyld_dw;
222
+ end
223
+ end
224
+
225
+ assign sub_dw_left = sub_dw_len - sub_dw_cnt;
226
+ always @(posedge clk, negedge rst_n) begin
227
+ if (~rst_n) begin
228
+ sub_dw_cnt <= `TD 0;
229
+ end
230
+ else if (sub_clear) begin
231
+ sub_dw_cnt <= `TD 0;
232
+ end
233
+ else if (beat_go) begin
234
+ sub_dw_cnt <= `TD sub_dw_cnt + `DMA_KEEP_W;
235
+ end
236
+ end
237
+
238
+ /* -------Split packet{end}------- */
239
+
240
+ /* -------{DMA Write Request FSM}begin------- */
241
+ /******************** Stage 1: State Register **********************/
242
+ assign is_idle = (cur_state == IDLE );
243
+ assign is_tx = (cur_state == TX );
244
+ assign is_sub_last = (cur_state == SUB_LAST);
245
+ assign is_req_last = (cur_state == REQ_LAST);
246
+
247
+ assign beat_go = axis_wr_req_tvalid & axis_wr_req_tready;
248
+ assign sub_clear = axis_wr_req_tvalid & axis_wr_req_tready & axis_wr_req_tlast;
249
+ assign req_clear = sub_clear & in_reg_sop;
250
+
251
+ always @(posedge clk, negedge rst_n) begin
252
+ if(~rst_n)
253
+ cur_state <= `TD IDLE;
254
+ else
255
+ cur_state <= `TD nxt_state;
256
+ end
257
+
258
+ /******************** Stage 2: State Transition **********************/
259
+ always @(*) begin
260
+ case(cur_state)
261
+ IDLE: begin
262
+ if (align_valid & align_ready & align_last)
263
+ nxt_state = REQ_LAST;
264
+ else if (align_valid & align_ready)
265
+ nxt_state = TX;
266
+ else
267
+ nxt_state = IDLE;
268
+ end
269
+ TX: begin
270
+ if (beat_go & next_req_last)
271
+ nxt_state = REQ_LAST;
272
+ else if (beat_go & next_sub_last)
273
+ nxt_state = SUB_LAST;
274
+ else
275
+ nxt_state = TX;
276
+ end
277
+ SUB_LAST: begin
278
+ if (sub_clear & next_req_last)
279
+ nxt_state = REQ_LAST;
280
+ else if (sub_clear)
281
+ nxt_state = TX;
282
+ else
283
+ nxt_state = SUB_LAST;
284
+ end
285
+ REQ_LAST: begin
286
+ if (sub_clear) begin
287
+ if (align_valid & align_ready & align_last) // Next req's comming and
288
+ // is a one-beat req
289
+ nxt_state = REQ_LAST;
290
+ else if (align_valid & align_ready) // Next req is comming
291
+ nxt_state = TX;
292
+ else // No incomming next req
293
+ nxt_state = IDLE;
294
+ end
295
+ else
296
+ nxt_state = REQ_LAST;
297
+ end
298
+ default: begin
299
+ nxt_state = IDLE;
300
+ end
301
+ endcase
302
+ end
303
+ /******************** Stage 3: Output **********************/
304
+ assign axis_wr_req_tvalid = in_reg_vld;
305
+ assign axis_wr_req_tlast = is_req_last | is_sub_last;
306
+ assign axis_wr_req_tuser = req_type == `DMA_INT_REQ ? int_tuser : wreq_tuser;
307
+ assign axis_wr_req_tdata = in_reg_data;
308
+ assign axis_wr_req_tkeep = in_reg_keep;
309
+
310
+ assign in_reg_rdy = axis_wr_req_tready;
311
+
312
+
313
+ assign in_reg_keep = (sub_dw_left >= 8) ?
314
+ `DMA_KEEP_MASK :
315
+ (`DMA_KEEP_MASK >> (`DMA_KEEP_W - sub_dw_left));
316
+
317
+ /* -------{DMA Write Request FSM}end------- */
318
+
319
+ endmodule
ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/DMA/DMA_Write/write_request.v ADDED
@@ -0,0 +1,209 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ `timescale 1ns / 100ps
2
+ //*************************************************************************
3
+ // > File Name: write_request.v
4
+ // > Author : Kangning
5
+ // > Date : 2020-08-25
6
+ // > Note : write_request, used to transform DMA write request.
7
+ // > Note that the packet must be 4KB aligned.
8
+ //*************************************************************************
9
+
10
+ //`include "../lib/global_include_h.v"
11
+ //`include "../lib/dma_def_h.v"
12
+
13
+ module write_request #(
14
+
15
+ ) (
16
+ input wire clk ,
17
+ input wire rst_n,
18
+
19
+ /* -------dma write request interface{begin}------- */
20
+ /* *_head of DMA interface (interact with RDMA modules),
21
+ * valid only in first beat of a packet.
22
+ * When Transmiting msi-x interrupt message, 'Byte length'
23
+ * should be 0, 'address' means the address of msi-x, and
24
+ * msi-x data locates in *_data[31:0].
25
+ * | Resvd | Req Type | address | Reserved | Byte length |
26
+ * | | (wr,int) | (msi-x addr) | | (0 for int) |
27
+ * |-------|----------|--------------|----------|-------------|
28
+ * |127:100| 99:96 | 95:32 | 31:13 | 12:0 |
29
+ */
30
+ input wire dma_wr_req_valid,
31
+ input wire dma_wr_req_last ,
32
+ input wire [`DMA_HEAD_W-1:0] dma_wr_req_head ,
33
+ input wire [`DMA_DATA_W-1:0] dma_wr_req_data ,
34
+ output wire dma_wr_req_ready,
35
+ /* -------dma write request interface{end}------- */
36
+
37
+ /* -------axis write request interface{begin}------- */
38
+ /* AXI-Stream write request tuser, only valid in first beat of a packet
39
+ * | Reserved | REQ_TYPE | Tag | address | Reserved | DW length | first BE | last BE |
40
+ * | 127:108 | 107:104 | 103:96 | 95:32 | 31:19 | 18:8 | 7:4 | 3:0 |
41
+ * or
42
+ * AXI-Stream interrupt request tuser, only valid in first beat of a packet
43
+ * | Reserved | REQ_TYPE | Resv | address | Reserved |
44
+ * | 127:108 | 107:104 | 103:96 | 95:32 | 31:0 |
45
+ */
46
+ output wire axis_wr_req_tvalid,
47
+ output wire axis_wr_req_tlast ,
48
+ output wire [`DMA_DATA_W -1:0] axis_wr_req_tdata , // contain only payload
49
+ output wire [`AXIS_TUSER_W-1:0] axis_wr_req_tuser , // The field contents are different from dma_*_tuser interface
50
+ output wire [`DMA_KEEP_W -1:0] axis_wr_req_tkeep ,
51
+ input wire axis_wr_req_tready,
52
+ /* -------axis write request interface{end}------- */
53
+
54
+ /* -------PCIe fragment property{begin}------- */
55
+ /* This signal indicates the (max payload size & max read request size) agreed in the communication
56
+ * 3'b000 -- 128 B
57
+ * 3'b001 -- 256 B
58
+ * 3'b010 -- 512 B
59
+ * 3'b011 -- 1024B
60
+ * 3'b100 -- 2048B
61
+ * 3'b101 -- 4096B
62
+ */
63
+ input wire [2:0] max_pyld_sz ,
64
+ input wire [2:0] max_rd_req_sz // max read request size
65
+ /* -------PCIe fragment property{end}------- */
66
+
67
+ `ifdef PCIEI_APB_DBG
68
+ /* -------APB reated signal{begin}------- */
69
+ ,input wire [`SRAM_RW_DATA_W -1:0] rw_data // i, `SRAM_RW_DATA_W
70
+ ,output wire [`WR_REQ_SIGNAL_W-1:0] dbg_signal // o, `WR_REQ_SIGNAL_W
71
+ /* -------APB reated signal{end}------- */
72
+ `endif
73
+ );
74
+
75
+ /* -------FIFO -> pkt align{begin}------- */
76
+ wire dma_valid;
77
+ wire dma_last ;
78
+ wire [`DMA_HEAD_W-1:0] dma_head ;
79
+ wire [`DMA_DATA_W-1:0] dma_data ;
80
+ wire dma_ready;
81
+
82
+ wire dma_empty, dma_full;
83
+ /* -------FIFO -> pkt align{end}------- */
84
+
85
+ /* -------FIFO -> pkt align{begin}------- */
86
+ wire align_valid;
87
+ wire align_last ;
88
+ wire [`DMA_HEAD_W-1:0] align_user ;
89
+ wire [`DMA_DATA_W-1:0] align_data ;
90
+ wire align_ready;
91
+ /* -------FIFO -> pkt align{end}------- */
92
+
93
+ `ifdef PCIEI_APB_DBG
94
+ /* -------APB reated signal{begin}------- */
95
+ wire [1:0] rtsel;
96
+ wire [1:0] wtsel;
97
+ wire [1:0] ptsel;
98
+ wire vg ;
99
+ wire vs ;
100
+
101
+ wire [`WREQ_TOP_SIGNAL_W -1:0] wreq_top_dbg_signal ;
102
+ wire [`WREQ_ALIGN_SIGNAL_W-1:0] wreq_align_dbg_signal;
103
+ wire [`WREQ_SPLIT_SIGNAL_W-1:0] wreq_split_dbg_signal;
104
+ /* -------APB reated signal{end}------- */
105
+ `endif
106
+
107
+ //---------------------------------------------------------------------------------------------------------------------------
108
+
109
+ `ifdef PCIEI_APB_DBG
110
+ /* -------APB reated signal{begin}------- */
111
+ assign {rtsel, wtsel, ptsel, vg, vs} = rw_data;
112
+ assign dbg_signal = {wreq_top_dbg_signal, wreq_align_dbg_signal, wreq_split_dbg_signal};
113
+
114
+ assign wreq_top_dbg_signal = { // 776
115
+ dma_valid, dma_last, dma_head, dma_data, dma_ready, // 387
116
+ dma_empty, dma_full, // 2
117
+ align_valid, align_last, align_user, align_data, align_ready // 387
118
+ };
119
+ /* -------APB reated signal{end}------- */
120
+ `endif
121
+
122
+ /* ------- Write Request FIFO{begin}------- */
123
+ pcieifc_sync_fifo #(
124
+ .DSIZE ( 1 + `DMA_HEAD_W + `DMA_DATA_W ), // 1 + 128 + 256=385
125
+ .ASIZE ( 7 ) // 128 beats
126
+ ) data_sync_fifo (
127
+ .clk ( clk ), // i, i
128
+ .rst_n ( rst_n ), // i, i
129
+ .clr ( 1'd0 ), // i, 1
130
+
131
+ .wen ( dma_wr_req_valid & dma_wr_req_ready ), // i, 1
132
+ .din ( {dma_wr_req_last, dma_wr_req_head, dma_wr_req_data} ), // i, (1 + `DMA_HEAD_W + `DMA_DATA_W)
133
+ .full ( dma_full ), // o, 1
134
+
135
+ .ren ( dma_valid & dma_ready ), // i, 1
136
+ .dout ( {dma_last, dma_head, dma_data} ), // o, (1 + `DMA_HEAD_W + `DMA_DATA_W)
137
+ .empty( dma_empty ) // o, 1
138
+
139
+ `ifdef PCIEI_APB_DBG
140
+ ,.rtsel ( rtsel ) // i, 2
141
+ ,.wtsel ( wtsel ) // i, 2
142
+ ,.ptsel ( ptsel ) // i, 2
143
+ ,.vg ( vg ) // i, 1
144
+ ,.vs ( vs ) // i, 1
145
+ `endif
146
+ );
147
+ assign dma_wr_req_ready = !dma_full;
148
+ assign dma_valid = !dma_empty;
149
+ /* ------- Write Request FIFO{end}------- */
150
+
151
+
152
+ /* ------- Align data to DW aligned{begin}------- */
153
+ wreq_align #(
154
+
155
+ ) wreq_align (
156
+ .clk ( clk ), // i, 1
157
+ .rst_n ( rst_n ), // i, 1
158
+
159
+ .dma_valid ( dma_valid ), // i, 1
160
+ .dma_last ( dma_last ), // i, 1
161
+ .dma_head ( dma_head ), // i, `DMA_HEAD_W
162
+ .dma_data ( dma_data ), // i, `DMA_DATA_W
163
+ .dma_ready ( dma_ready ), // o, 1
164
+
165
+ .align_valid ( align_valid ), // o, 1
166
+ .align_last ( align_last ), // o, 1
167
+ .align_user ( align_user ), // o, `AXIS_TUSER_W
168
+ .align_data ( align_data ), // o, `DMA_DATA_W
169
+ .align_ready ( align_ready ) // i, 1
170
+
171
+ `ifdef PCIEI_APB_DBG
172
+ /* -------APB reated signal{begin}------- */
173
+ ,.dbg_signal ( wreq_align_dbg_signal ) // o, `WREQ_ALIGN_SIGNAL_W
174
+ /* -------APB reated signal{end}------- */
175
+ `endif
176
+ );
177
+ /* ------- Align data to DW aligned{end}------- */
178
+
179
+ /* ------- Split pkt to fit max_pyld_sz{begin}------- */
180
+ wreq_split #(
181
+
182
+ ) wreq_split (
183
+ .clk ( clk ), // i, 1
184
+ .rst_n ( rst_n ), // i, 1
185
+
186
+ .max_pyld_sz ( max_pyld_sz ), // i, 3
187
+
188
+ .align_valid ( align_valid ), // i, 1
189
+ .align_last ( align_last ), // i, 1
190
+ .align_user ( align_user ), // i, `AXIS_TUSER_W
191
+ .align_data ( align_data ), // i, `DMA_DATA_W
192
+ .align_ready ( align_ready ), // o, 1
193
+
194
+ .axis_wr_req_tvalid ( axis_wr_req_tvalid ), // o, 1
195
+ .axis_wr_req_tlast ( axis_wr_req_tlast ), // o, 1
196
+ .axis_wr_req_tdata ( axis_wr_req_tdata ), // o, `DMA_DATA_W
197
+ .axis_wr_req_tuser ( axis_wr_req_tuser ), // o, `AXIS_TUSER_W
198
+ .axis_wr_req_tkeep ( axis_wr_req_tkeep ), // o, `DMA_KEEP_W
199
+ .axis_wr_req_tready ( axis_wr_req_tready ) // i, 1
200
+
201
+ `ifdef PCIEI_APB_DBG
202
+ /* -------APB reated signal{begin}------- */
203
+ ,.dbg_signal ( wreq_split_dbg_signal ) // o, `WREQ_SPLIT_SIGNAL_W
204
+ /* -------APB reated signal{end}------- */
205
+ `endif
206
+ );
207
+ /* ------- Split pkt to fit max_pyld_sz{end}------- */
208
+
209
+ endmodule
ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/DMA/int_proc.v ADDED
@@ -0,0 +1,171 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ `timescale 1ns / 100ps
2
+ //*************************************************************************
3
+ // > File Name: int_proc.v
4
+ // > Author : Kangning
5
+ // > Date : 2021-09-17
6
+ // > Note : Process interrupt request
7
+ //*************************************************************************
8
+
9
+ module int_proc #(
10
+
11
+ ) (
12
+ input wire pcie_clk ,
13
+ input wire pcie_rst_n,
14
+ input wire dma_clk ,
15
+ input wire rst_n ,
16
+
17
+ input wire int_req_valid,
18
+ input wire [31:0] int_req_data ,
19
+ input wire [63:0] int_req_addr ,
20
+ output wire int_req_ready,
21
+
22
+ /* -------Interrupt Interface Signals{begin}------- */
23
+ input [1:0] cfg_interrupt_msix_enable ,
24
+ input [1:0] cfg_interrupt_msix_mask ,
25
+ output [31:0] cfg_interrupt_msix_data ,
26
+ output [63:0] cfg_interrupt_msix_address ,
27
+ output cfg_interrupt_msix_int ,
28
+ input cfg_interrupt_msix_sent ,
29
+ input cfg_interrupt_msix_fail ,
30
+ output wire [2:0] cfg_interrupt_msi_function_number
31
+ /* -------Interrupt Interface Signals{end}------- */
32
+
33
+ `ifdef PCIEI_APB_DBG
34
+ /* -------APB reated signal{begin}------- */
35
+ ,input wire [`SRAM_RW_DATA_W-1:0] rw_data // i, `SRAM_RW_DATA_W
36
+ ,output wire [`INT_PROC_SIGNAL_W-1:0] dbg_signal // o, `INT_PROC_SIGNAL_W
37
+ /* -------APB reated signal{end}------- */
38
+ `endif
39
+ );
40
+
41
+ /*-------Interrupt related logic{begin}------- */
42
+ wire int_req_full;
43
+
44
+ wire [31:0] int_out_data ;
45
+ wire [63:0] int_out_addr ;
46
+ wire int_out_empty;
47
+ /*-------Interrupt related logic{end}------- */
48
+
49
+ /* -------State relevant in FSM{begin}------- */
50
+ localparam WAIT_SEND = 2'b01, // idle, or send the interrupt
51
+ WAIT_RESP = 2'b10; // Wait for the rsp of interrupt
52
+ reg [1:0] cur_state;
53
+ reg [1:0] nxt_state;
54
+ wire is_wait_send, is_wait_resp;
55
+ wire j_wait_send, j_wait_resp;
56
+
57
+ reg msix_enable;
58
+ /* -------State relevant in FSM{end}------- */
59
+
60
+ `ifdef PCIEI_APB_DBG
61
+ /* -------APB reated signal{begin}------- */
62
+ wire [1:0] rtsel;
63
+ wire [1:0] wtsel;
64
+ wire [1:0] ptsel;
65
+ wire vg ;
66
+ wire vs ;
67
+ /* -------APB reated signal{end}------- */
68
+ `endif
69
+
70
+ //---------------------------------------------------------------------------------------------------------------------------
71
+
72
+ `ifdef PCIEI_APB_DBG
73
+ /* -------APB reated signal{begin}------- */
74
+ assign {rtsel, wtsel, ptsel, vg, vs} = rw_data;
75
+ assign dbg_signal = { // 107
76
+ int_req_full, // 1
77
+ int_out_data, int_out_addr, int_out_empty, // 97
78
+ cur_state, nxt_state, // 4
79
+ is_wait_send, is_wait_resp, // 2
80
+ j_wait_send, j_wait_resp, // 2
81
+ msix_enable // 1
82
+ };
83
+ /* -------APB reated signal{end}------- */
84
+ `endif
85
+
86
+ /*-------Interrupt related logic{begin}------- */
87
+ assign int_req_ready = ~int_req_full;
88
+
89
+ pcieifc_async_fifo #(
90
+ .DATA_WIDTH ( (64 + 32) ),
91
+ .ADDR_WIDTH ( 4 )
92
+ ) async_fifo_int (
93
+ .wr_clk ( dma_clk ), // i, 1
94
+ .rd_clk ( pcie_clk ), // i, 1
95
+ .wrst_n ( rst_n ), // i, 1
96
+ .rrst_n ( pcie_rst_n ), // i, 1
97
+
98
+ .wen ( int_req_valid & int_req_ready), // i, 1
99
+ .din ( {int_req_addr, int_req_data} ), // i, (64 + 32)
100
+ .full ( int_req_full ), // o, 1
101
+
102
+ .ren ( j_wait_send & cfg_interrupt_msix_sent & (!int_out_empty) ), // i, 1
103
+ .dout ( {int_out_addr, int_out_data} ), // o, (64 + 32)
104
+ .empty ( int_out_empty ) // o, 1
105
+
106
+ `ifdef PCIEI_APB_DBG
107
+ ,.rtsel ( rtsel ) // i, 2
108
+ ,.wtsel ( wtsel ) // i, 2
109
+ ,.ptsel ( ptsel ) // i, 2
110
+ ,.vg ( vg ) // i, 1
111
+ ,.vs ( vs ) // i, 1
112
+ `endif
113
+ );
114
+
115
+ /*-------Interrupt related logic{end}------- */
116
+
117
+ /* -------{DMA Write Request FSM}begin------- */
118
+ /******************** Stage 1: State Register **********************/
119
+ assign is_wait_send = cur_state == WAIT_SEND;
120
+ assign is_wait_resp = cur_state == WAIT_RESP;
121
+
122
+ assign j_wait_send = is_wait_resp & (cfg_interrupt_msix_sent |
123
+ cfg_interrupt_msix_fail |
124
+ !msix_enable);
125
+ assign j_wait_resp = is_wait_send & msix_enable & !int_out_empty;
126
+
127
+ always @(posedge pcie_clk, negedge pcie_rst_n) begin
128
+ if(~pcie_rst_n)
129
+ msix_enable <= `TD 1'd0;
130
+ else
131
+ msix_enable <= `TD cfg_interrupt_msix_enable[0];
132
+ end
133
+
134
+ always @(posedge pcie_clk, negedge pcie_rst_n) begin
135
+ if(~pcie_rst_n)
136
+ cur_state <= `TD WAIT_SEND;
137
+ else
138
+ cur_state <= `TD nxt_state;
139
+ end
140
+
141
+ /******************** Stage 2: State Transition **********************/
142
+ always @(*) begin
143
+ case(cur_state)
144
+ WAIT_SEND: begin
145
+ if (msix_enable & !int_out_empty)
146
+ nxt_state = WAIT_RESP;
147
+ else
148
+ nxt_state = WAIT_SEND;
149
+ end
150
+ WAIT_RESP: begin
151
+ if (cfg_interrupt_msix_sent |
152
+ cfg_interrupt_msix_fail | !msix_enable)
153
+ nxt_state = WAIT_SEND;
154
+ else
155
+ nxt_state = WAIT_RESP;
156
+ end
157
+ default: begin
158
+ nxt_state = WAIT_SEND;
159
+ end
160
+ endcase
161
+ end
162
+ /******************** Stage 3: Output **********************/
163
+
164
+ assign cfg_interrupt_msix_data = int_out_data;
165
+ assign cfg_interrupt_msix_address = int_out_addr;
166
+ assign cfg_interrupt_msix_int = j_wait_resp;
167
+ assign cfg_interrupt_msi_function_number = 0;
168
+ /* -------{DMA Write Request FSM}end------- */
169
+
170
+
171
+ endmodule
ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/DMA/rc_async_fifos.v ADDED
@@ -0,0 +1,114 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ `timescale 1ns / 100ps
2
+ //*************************************************************************
3
+ // > File Name: rc_async_fifos.v
4
+ // > Author : Kangning
5
+ // > Date : 2021-08-16
6
+ // > Note : rc_async_fifos, used to separate rdma and pcie clock domain,
7
+ // > in RC (Requester Completion Channel).
8
+ //*************************************************************************
9
+
10
+ //`include "../lib/global_include_h.v"
11
+
12
+ module rc_async_fifos #(
13
+
14
+ ) (
15
+ input wire dma_clk ,
16
+ input wire pcie_clk ,
17
+ input wire dma_rst_n ,
18
+ input wire pcie_rst_n,
19
+
20
+ /* ------- pcie --> dma interface, pcie part{begin}------- */
21
+ // Requester Completion
22
+ /* RC tuser
23
+ * | 74:43 | 42 | 41:38 | 37:34 | 33 | 32 | 31:0 |
24
+ * | parity | discontinue | is_eof_1 | is_eof_0 | is_sof_1 | is_sof_0 | byte_en |
25
+ * | ignore | ignore | ignore | ignore | ignore | ignore | |
26
+ */
27
+ input wire pcie_axis_rc_tvalid, // i, 1
28
+ input wire pcie_axis_rc_tlast , // i, 1
29
+ input wire [`DMA_DATA_W-1:0] pcie_axis_rc_tdata , // i, `DMA_DATA_W
30
+ input wire [74 :0] pcie_axis_rc_tuser , // i, 75
31
+ input wire [`DMA_KEEP_W-1:0] pcie_axis_rc_tkeep , // i, `DMA_KEEP_W
32
+ output wire pcie_axis_rc_tready, // o, 1
33
+ /* ------- pcie --> dma interface, pcie part{end}------- */
34
+
35
+ /* ------- pcie --> dma interface, dma part{begin}------- */
36
+ // Requester Completion
37
+ /* RC tuser
38
+ * | 74:43 | 42 | 41:38 | 37:34 | 33 | 32 | 31:0 |
39
+ * | parity | discontinue | is_eof_1 | is_eof_0 | is_sof_1 | is_sof_0 | byte_en |
40
+ * | ignore | ignore | ignore | ignore | ignore | ignore | |
41
+ */
42
+ output wire dma_axis_rc_tvalid, // i, 1
43
+ output wire dma_axis_rc_tlast , // i, 1
44
+ output wire [`DMA_DATA_W-1:0] dma_axis_rc_tdata , // i, `DMA_DATA_W
45
+ output wire [74 :0] dma_axis_rc_tuser , // i, 75
46
+ output wire [`DMA_KEEP_W-1:0] dma_axis_rc_tkeep , // i, `DMA_KEEP_W
47
+ input wire dma_axis_rc_tready // o, 1
48
+ /* ------- pcie --> dma interface, dma part{end}------- */
49
+
50
+ `ifdef PCIEI_APB_DBG
51
+ /* -------APB reated signal{begin}------- */
52
+ ,input wire [`SRAM_RW_DATA_W -1:0] rw_data // i, `SRAM_RW_DATA_W
53
+ ,output wire [`RC_ASYNC_SIGNAL_W-1:0] dbg_signal // o, `RC_ASYNC_SIGNAL_W
54
+ /* -------APB reated signal{end}------- */
55
+ `endif
56
+ );
57
+ wire pcie_axis_rc_full, dma_axis_rc_empty;
58
+ wire [31:0] rc_tuser;
59
+
60
+ `ifdef PCIEI_APB_DBG
61
+ /* -------APB reated signal{begin}------- */
62
+ wire [1:0] rtsel;
63
+ wire [1:0] wtsel;
64
+ wire [1:0] ptsel;
65
+ wire vg ;
66
+ wire vs ;
67
+ /* -------APB reated signal{end}------- */
68
+ `endif
69
+
70
+ //---------------------------------------------------------------------------------------------------------------------------
71
+
72
+ `ifdef PCIEI_APB_DBG
73
+ /* -------APB reated signal{begin}------- */
74
+ assign {rtsel, wtsel, ptsel, vg, vs} = rw_data;
75
+ assign dbg_signal = {
76
+ pcie_axis_rc_full, dma_axis_rc_empty,
77
+ rc_tuser
78
+ };
79
+ /* -------APB reated signal{end}------- */
80
+ `endif
81
+
82
+ pcieifc_async_fifo #(
83
+ .DATA_WIDTH ( (1 + `DMA_KEEP_W + 32 + `DMA_DATA_W) ),
84
+ .ADDR_WIDTH ( 6 )
85
+ ) pcieifc_async_fifo (
86
+ .wr_clk ( pcie_clk ), // i, 1
87
+ .rd_clk ( dma_clk ), // i, 1
88
+ .wrst_n ( pcie_rst_n ), // i, 1
89
+ .rrst_n ( dma_rst_n ), // i, 1
90
+
91
+ .wen ( pcie_axis_rc_tvalid & pcie_axis_rc_tready ), // i, 1
92
+ .din ( {pcie_axis_rc_tlast, pcie_axis_rc_tkeep, pcie_axis_rc_tuser[31:0], pcie_axis_rc_tdata} ), // i, (1 + `DMA_KEEP_W + 32 + `DMA_DATA_W)
93
+ .full ( pcie_axis_rc_full ), // o, 1
94
+
95
+ .ren ( dma_axis_rc_tvalid & dma_axis_rc_tready ), // i, 1
96
+ .dout ( {dma_axis_rc_tlast, dma_axis_rc_tkeep, rc_tuser, dma_axis_rc_tdata} ), // o, (1 + `DMA_KEEP_W + 32 + `DMA_DATA_W)
97
+ .empty ( dma_axis_rc_empty ) // o, 1
98
+
99
+ `ifdef PCIEI_APB_DBG
100
+ ,.rtsel ( rtsel ) // i, 2
101
+ ,.wtsel ( wtsel ) // i, 2
102
+ ,.ptsel ( ptsel ) // i, 2
103
+ ,.vg ( vg ) // i, 1
104
+ ,.vs ( vs ) // i, 1
105
+ `endif
106
+ );
107
+
108
+ assign pcie_axis_rc_tready = !pcie_axis_rc_full;
109
+ assign dma_axis_rc_tvalid = !dma_axis_rc_empty;
110
+
111
+
112
+ assign dma_axis_rc_tuser = {43'd0, rc_tuser};
113
+
114
+ endmodule
ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/DMA/req_arbiter.v ADDED
@@ -0,0 +1,937 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ `timescale 1ns / 100ps
2
+ //*************************************************************************
3
+ // > File Name: req_arbiter.v
4
+ // > Author : Kangning
5
+ // > Date : 2020-08-27
6
+ // > Note : req_arbiter is used to arbiter different channels for data transmission
7
+ // > V1.1 - 2021-02-04 : Add supporting for five channels
8
+ // > V1.5 - 2022-04-24 : Parameterized arbiter, supports arbitrary number of channels
9
+ //*************************************************************************
10
+
11
+ //`include "../lib/global_include_h.v"
12
+
13
+ module req_arbiter #(
14
+ parameter CHANNEL_NUM = 8 , // number of slave signals to arbit
15
+ parameter CHNL_NUM_LOG = 3
16
+ ) (
17
+ input wire dma_clk ,
18
+ input wire rst_n ,
19
+
20
+ /* -------Slave AXIS Interface{begin}------- */
21
+ /* AXI-Stream request tuser, only valid in first beat of a packet
22
+ * | Reserved | REQ_TYPE | Tag | address | Reserved | DW length | first BE | last BE |
23
+ * | 127:108 | 107:104 | 103:96 | 95:32 | 31:19 | 18:8 | 7:4 | 3:0 |
24
+ * or
25
+ * AXI-Stream interrupt request tuser, only valid in first beat of a packet
26
+ * | Reserved | REQ_TYPE | Resv | address | Reserved |
27
+ * | 127:108 | 107:104 | 103:96 | 95:32 | 31:0 |
28
+ */
29
+ input wire [CHANNEL_NUM * 1 -1:0] s_axis_req_tvalid,
30
+ input wire [CHANNEL_NUM * 1 -1:0] s_axis_req_tlast ,
31
+ input wire [CHANNEL_NUM * `DMA_DATA_W -1:0] s_axis_req_tdata ,
32
+ input wire [CHANNEL_NUM * `AXIS_TUSER_W-1:0] s_axis_req_tuser ,
33
+ input wire [CHANNEL_NUM * `DMA_KEEP_W -1:0] s_axis_req_tkeep ,
34
+ output wire [CHANNEL_NUM * 1 -1:0] s_axis_req_tready,
35
+ /* -------Slave AXIS Interface{end}------- */
36
+
37
+ /* ------- Master AXIS Interface{begin} ------- */
38
+ /* AXI-Stream request tuser, only valid in first beat of a packet
39
+ * | Reserved | REQ_TYPE | Tag | address | Reserved | DW length | first BE | last BE |
40
+ * | 127:108 | 107:104 | 103:96 | 95:32 | 31:19 | 18:8 | 7:4 | 3:0 |
41
+ * or
42
+ * AXI-Stream interrupt request tuser, only valid in first beat of a packet
43
+ * | Reserved | REQ_TYPE | Resv | address | Reserved |
44
+ * | 127:108 | 107:104 | 103:96 | 95:32 | 31:0 |
45
+ */
46
+ output wire m_axis_req_tvalid,
47
+ output wire m_axis_req_tlast ,
48
+ output wire [`DMA_DATA_W -1:0] m_axis_req_tdata , // contain only payload
49
+ output wire [`AXIS_TUSER_W-1:0] m_axis_req_tuser , // The field contents are different from dma_*_tuser interface
50
+ output wire [`DMA_KEEP_W -1:0] m_axis_req_tkeep ,
51
+ input wire m_axis_req_tready
52
+ /* ------- Master AXIS Interface{end} ------- */
53
+
54
+ `ifdef PCIEI_APB_DBG
55
+ /* -------APB reated signal{begin}------- */
56
+ ,output wire [`ARB_BASE_SIGNAL_W+CHANNEL_NUM*CHNL_NUM_LOG+CHNL_NUM_LOG*3+CHANNEL_NUM-1:0] dbg_signal // o, `WREQ_ALIGN_SIGNAL_W
57
+ /* -------APB reated signal{end}------- */
58
+ `endif
59
+
60
+ `ifdef SIMULATION
61
+ /* ------- Debug interface {begin}------- */
62
+ /* | reserved | idx | end | out |
63
+ * | 255:CHNL_NUM_LOG+2 | CHNL_NUM_LOG+2-1:2 | 1 | 0 |
64
+ */
65
+ ,output wire [255:0] debug
66
+ /* ------- Debug interface {end}------- */
67
+ `endif
68
+
69
+ );
70
+
71
+ /* ------- Next scheduled channel{begin}------- */
72
+ reg [CHNL_NUM_LOG-1:0] chnl_idx_reg; // Index of channel to be scheduled next time, valid only in REQ_TRANS state.
73
+ reg [CHNL_NUM_LOG-1:0] chnl_idx; // Index of channel to be scheduled next time, valid all the time.
74
+ reg [CHNL_NUM_LOG-1:0] last_chnl; // Index of last selected channel.
75
+
76
+
77
+ /**
78
+ * hit relevant channel is hit (hit_priority[3] == 1 means that last
79
+ * selected channel is still valid.
80
+ */
81
+ wire [CHANNEL_NUM-1:0] hit_priority;
82
+
83
+ /**
84
+ * index of channel priority in next time, e.g. nxt_priority[1]
85
+ * indicates the index of next next channel; while nxt_priority[0]
86
+ * indicates the index of next channel.
87
+ */
88
+ wire [CHNL_NUM_LOG-1:0] nxt_priority[CHANNEL_NUM-1:0];
89
+
90
+ wire s_channel_tvalid[CHANNEL_NUM-1:0];
91
+ wire s_channel_tlast [CHANNEL_NUM-1:0];
92
+ wire [`DMA_DATA_W -1:0] s_channel_tdata [CHANNEL_NUM-1:0];
93
+ wire [`AXIS_TUSER_W-1:0] s_channel_tuser [CHANNEL_NUM-1:0];
94
+ wire [`DMA_KEEP_W -1:0] s_channel_tkeep [CHANNEL_NUM-1:0];
95
+
96
+
97
+ wire req_last; // last beat of the request
98
+ /* ------- Next scheduled channel{end}------- */
99
+
100
+ /* -------State relevant in FSM{begin}------- */
101
+ localparam IDLE = 3'b001,
102
+ SCHEDULE = 3'b010,
103
+ REQ_TRANS = 3'b100;
104
+
105
+ reg [2:0] cur_state;
106
+ reg [2:0] nxt_state;
107
+
108
+ wire is_idle, is_schedule, is_req_trans;
109
+ wire j_req_trans;
110
+ // wire j_schedule;
111
+ /* -------State relevant in FSM{end}------- */
112
+
113
+ //---------------------------------------------------------------------------------------------------------------------------
114
+
115
+ `ifdef PCIEI_APB_DBG
116
+ /* -------APB reated signal{begin}------- */
117
+ generate
118
+ if (CHANNEL_NUM == 10) begin:CHNL_DBG_10
119
+
120
+ assign dbg_signal = {
121
+ chnl_idx_reg, chnl_idx, last_chnl, hit_priority,
122
+ req_last,
123
+ cur_state, nxt_state,
124
+ is_idle, is_schedule, is_req_trans,
125
+ j_req_trans,
126
+ nxt_priority[0], nxt_priority[1], nxt_priority[2], nxt_priority[3], nxt_priority[4],
127
+ nxt_priority[5], nxt_priority[6], nxt_priority[7], nxt_priority[8], nxt_priority[9]
128
+ };
129
+
130
+ end
131
+ else if (CHANNEL_NUM == 9) begin:CHNL_DBG_9
132
+
133
+ assign dbg_signal = {
134
+ chnl_idx_reg, chnl_idx, last_chnl, hit_priority,
135
+ req_last,
136
+ cur_state, nxt_state,
137
+ is_idle, is_schedule, is_req_trans,
138
+ j_req_trans,
139
+ nxt_priority[0], nxt_priority[1], nxt_priority[2], nxt_priority[3], nxt_priority[4],
140
+ nxt_priority[5], nxt_priority[6], nxt_priority[7], nxt_priority[8]
141
+ };
142
+
143
+ end
144
+ else if (CHANNEL_NUM == 8) begin:CHNL_DBG_8
145
+
146
+ assign dbg_signal = {
147
+ chnl_idx_reg, chnl_idx, last_chnl, hit_priority,
148
+ req_last,
149
+ cur_state, nxt_state,
150
+ is_idle, is_schedule, is_req_trans,
151
+ j_req_trans,
152
+ nxt_priority[0], nxt_priority[1], nxt_priority[2], nxt_priority[3], nxt_priority[4],
153
+ nxt_priority[5], nxt_priority[6], nxt_priority[7]
154
+ };
155
+
156
+ end
157
+ else if (CHANNEL_NUM == 7) begin:CHNL_DBG_7
158
+
159
+ assign dbg_signal = {
160
+ chnl_idx_reg, chnl_idx, last_chnl, hit_priority,
161
+ req_last,
162
+ cur_state, nxt_state,
163
+ is_idle, is_schedule, is_req_trans,
164
+ j_req_trans,
165
+ nxt_priority[0], nxt_priority[1], nxt_priority[2], nxt_priority[3], nxt_priority[4],
166
+ nxt_priority[5], nxt_priority[6]
167
+ };
168
+
169
+ end
170
+ else if (CHANNEL_NUM == 6) begin:CHNL_DBG_6
171
+
172
+ assign dbg_signal = {
173
+ chnl_idx_reg, chnl_idx, last_chnl, hit_priority,
174
+ req_last,
175
+ cur_state, nxt_state,
176
+ is_idle, is_schedule, is_req_trans,
177
+ j_req_trans,
178
+ nxt_priority[0], nxt_priority[1], nxt_priority[2], nxt_priority[3], nxt_priority[4],
179
+ nxt_priority[5]
180
+ };
181
+
182
+ end
183
+ else if (CHANNEL_NUM == 5) begin:CHNL_DBG_5
184
+
185
+ assign dbg_signal = {
186
+ chnl_idx_reg, chnl_idx, last_chnl, hit_priority,
187
+ req_last,
188
+ cur_state, nxt_state,
189
+ is_idle, is_schedule, is_req_trans,
190
+ j_req_trans,
191
+ nxt_priority[0], nxt_priority[1], nxt_priority[2], nxt_priority[3], nxt_priority[4]
192
+ };
193
+
194
+ end
195
+ else if (CHANNEL_NUM == 4) begin:CHNL_DBG_4
196
+
197
+ assign dbg_signal = {
198
+ chnl_idx_reg, chnl_idx, last_chnl, hit_priority,
199
+ req_last,
200
+ cur_state, nxt_state,
201
+ is_idle, is_schedule, is_req_trans,
202
+ j_req_trans,
203
+ nxt_priority[0], nxt_priority[1], nxt_priority[2], nxt_priority[3]
204
+ };
205
+
206
+ end
207
+ else if (CHANNEL_NUM == 3) begin:CHNL_DBG_3
208
+
209
+ assign dbg_signal = {
210
+ chnl_idx_reg, chnl_idx, last_chnl, hit_priority,
211
+ req_last,
212
+ cur_state, nxt_state,
213
+ is_idle, is_schedule, is_req_trans,
214
+ j_req_trans,
215
+ nxt_priority[0], nxt_priority[1], nxt_priority[2]
216
+ };
217
+
218
+ end
219
+ else if (CHANNEL_NUM == 2) begin:CHNL_DBG_2
220
+
221
+ assign dbg_signal = {
222
+ chnl_idx_reg, chnl_idx, last_chnl, hit_priority,
223
+ req_last,
224
+ cur_state, nxt_state,
225
+ is_idle, is_schedule, is_req_trans,
226
+ j_req_trans,
227
+ nxt_priority[0], nxt_priority[1]
228
+ };
229
+
230
+ end
231
+ endgenerate
232
+ /* -------APB reated signal{end}------- */
233
+ `endif
234
+
235
+ `ifdef SIMULATION
236
+ /* ------- Debug interface {begin}------- */
237
+ /* | reserved | idx | end | out |
238
+ * | 255:CHNL_NUM_LOG+2 | CHNL_NUM_LOG+2-1:2 | 1 | 0 |
239
+ */
240
+ assign debug = {{254-CHNL_NUM_LOG{1'd0}},
241
+ chnl_idx,
242
+ m_axis_req_tvalid & m_axis_req_tready & m_axis_req_tlast,
243
+ m_axis_req_tvalid & m_axis_req_tready};
244
+ /* ------- Debug interface {end}------- */
245
+ `endif
246
+
247
+
248
+
249
+ /* -------Find next channel{begin}------- */
250
+
251
+ always @(posedge dma_clk, negedge rst_n) begin
252
+ if (~rst_n) begin
253
+ last_chnl <= `TD {CHNL_NUM_LOG{1'd0}};
254
+ end
255
+ else if (req_last) begin
256
+ last_chnl <= `TD chnl_idx;
257
+ end
258
+ end
259
+
260
+ always @(posedge dma_clk, negedge rst_n) begin
261
+ if (~rst_n) begin
262
+ chnl_idx_reg <= `TD {CHNL_NUM_LOG{1'd0}};
263
+ end
264
+ else if (j_req_trans) begin
265
+ chnl_idx_reg <= `TD chnl_idx;
266
+ end
267
+ end
268
+
269
+ /* -------Generate block{begin}------- */
270
+ genvar k;
271
+ generate
272
+ for (k = 0; k < CHANNEL_NUM; k = k + 1) begin:CHNL_PRIORITY
273
+
274
+ assign nxt_priority[k] = ((last_chnl + k + 1) >= CHANNEL_NUM) ?
275
+ (last_chnl + k + 1 - CHANNEL_NUM) : (last_chnl + k + 1);
276
+
277
+ end
278
+ endgenerate
279
+ /* -------Generate block{end}------- */
280
+
281
+
282
+ /* -------Generate block{begin}------- */
283
+ /* This is used for different Channel Numbers, the default Number is 5
284
+ */
285
+ generate
286
+ if (CHANNEL_NUM == 10) begin:CHNL_SEL_10
287
+
288
+ always @(*) begin
289
+ if (is_schedule) begin
290
+ case (last_chnl)
291
+ 0: chnl_idx = hit_priority[0] ? 1 :
292
+ hit_priority[1] ? 2 :
293
+ hit_priority[2] ? 3 :
294
+ hit_priority[3] ? 4 :
295
+ hit_priority[4] ? 5 :
296
+ hit_priority[5] ? 6 :
297
+ hit_priority[6] ? 7 :
298
+ hit_priority[7] ? 8 :
299
+ hit_priority[8] ? 9 :
300
+ hit_priority[9] ? 0 : 1 ; // last branch is chosen when no channel is valid.
301
+ 1: chnl_idx = hit_priority[0] ? 2 :
302
+ hit_priority[1] ? 3 :
303
+ hit_priority[2] ? 4 :
304
+ hit_priority[3] ? 5 :
305
+ hit_priority[4] ? 6 :
306
+ hit_priority[5] ? 7 :
307
+ hit_priority[6] ? 8 :
308
+ hit_priority[7] ? 9 :
309
+ hit_priority[8] ? 0 :
310
+ hit_priority[9] ? 1 : 2 ; // last branch is chosen when no channel is valid.
311
+ 2: chnl_idx = hit_priority[0] ? 3 :
312
+ hit_priority[1] ? 4 :
313
+ hit_priority[2] ? 5 :
314
+ hit_priority[3] ? 6 :
315
+ hit_priority[4] ? 7 :
316
+ hit_priority[5] ? 8 :
317
+ hit_priority[6] ? 9 :
318
+ hit_priority[7] ? 0 :
319
+ hit_priority[8] ? 1 :
320
+ hit_priority[9] ? 2 : 3 ; // last branch is chosen when no channel is valid.
321
+ 3: chnl_idx = hit_priority[0] ? 4 :
322
+ hit_priority[1] ? 5 :
323
+ hit_priority[2] ? 6 :
324
+ hit_priority[3] ? 7 :
325
+ hit_priority[4] ? 8 :
326
+ hit_priority[5] ? 9 :
327
+ hit_priority[6] ? 0 :
328
+ hit_priority[7] ? 1 :
329
+ hit_priority[8] ? 2 :
330
+ hit_priority[9] ? 3 : 4 ; // last branch is chosen when no channel is valid.
331
+ 4: chnl_idx = hit_priority[0] ? 5 :
332
+ hit_priority[1] ? 6 :
333
+ hit_priority[2] ? 7 :
334
+ hit_priority[3] ? 8 :
335
+ hit_priority[4] ? 9 :
336
+ hit_priority[5] ? 0 :
337
+ hit_priority[6] ? 1 :
338
+ hit_priority[7] ? 2 :
339
+ hit_priority[8] ? 3 :
340
+ hit_priority[9] ? 4 : 5 ; // last branch is chosen when no channel is valid.
341
+ 5: chnl_idx = hit_priority[0] ? 6 :
342
+ hit_priority[1] ? 7 :
343
+ hit_priority[2] ? 8 :
344
+ hit_priority[3] ? 9 :
345
+ hit_priority[4] ? 0 :
346
+ hit_priority[5] ? 1 :
347
+ hit_priority[6] ? 2 :
348
+ hit_priority[7] ? 3 :
349
+ hit_priority[8] ? 4 :
350
+ hit_priority[9] ? 5 : 6 ; // last branch is chosen when no channel is valid.
351
+ 6: chnl_idx = hit_priority[0] ? 7 :
352
+ hit_priority[1] ? 8 :
353
+ hit_priority[2] ? 9 :
354
+ hit_priority[3] ? 0 :
355
+ hit_priority[4] ? 1 :
356
+ hit_priority[5] ? 2 :
357
+ hit_priority[6] ? 3 :
358
+ hit_priority[7] ? 4 :
359
+ hit_priority[8] ? 5 :
360
+ hit_priority[9] ? 6 : 7 ; // last branch is chosen when no channel is valid.
361
+ 7: chnl_idx = hit_priority[0] ? 8 :
362
+ hit_priority[1] ? 9 :
363
+ hit_priority[2] ? 0 :
364
+ hit_priority[3] ? 1 :
365
+ hit_priority[4] ? 2 :
366
+ hit_priority[5] ? 3 :
367
+ hit_priority[6] ? 4 :
368
+ hit_priority[7] ? 5 :
369
+ hit_priority[8] ? 6 :
370
+ hit_priority[9] ? 7 : 8 ; // last branch is chosen when no channel is valid.
371
+ 8: chnl_idx = hit_priority[0] ? 9 :
372
+ hit_priority[1] ? 0 :
373
+ hit_priority[2] ? 1 :
374
+ hit_priority[3] ? 2 :
375
+ hit_priority[4] ? 3 :
376
+ hit_priority[5] ? 4 :
377
+ hit_priority[6] ? 5 :
378
+ hit_priority[7] ? 6 :
379
+ hit_priority[8] ? 7 :
380
+ hit_priority[9] ? 8 : 9 ; // last branch is chosen when no channel is valid.
381
+ 9: chnl_idx = hit_priority[0] ? 0 :
382
+ hit_priority[1] ? 1 :
383
+ hit_priority[2] ? 2 :
384
+ hit_priority[3] ? 3 :
385
+ hit_priority[4] ? 4 :
386
+ hit_priority[5] ? 5 :
387
+ hit_priority[6] ? 6 :
388
+ hit_priority[7] ? 7 :
389
+ hit_priority[8] ? 8 :
390
+ hit_priority[9] ? 9 : 0 ; // last branch is chosen when no channel is valid.
391
+ default: chnl_idx = {CHNL_NUM_LOG{1'd0}};
392
+ endcase
393
+ end
394
+ else begin
395
+ chnl_idx = chnl_idx_reg; // chosen in REQ_TRANS state
396
+ end
397
+ end
398
+
399
+ end // CHANNEL_NUM == 10
400
+ else if (CHANNEL_NUM == 9) begin:CHNL_SEL_9
401
+
402
+ always @(*) begin
403
+ if (is_schedule) begin
404
+ case (last_chnl)
405
+ 4'd0: chnl_idx = hit_priority[0] ? 4'd1 :
406
+ hit_priority[1] ? 4'd2 :
407
+ hit_priority[2] ? 4'd3 :
408
+ hit_priority[3] ? 4'd4 :
409
+ hit_priority[4] ? 4'd5 :
410
+ hit_priority[5] ? 4'd6 :
411
+ hit_priority[6] ? 4'd7 :
412
+ hit_priority[7] ? 4'd8 :
413
+ hit_priority[8] ? 4'd0 : 4'd1 ; // last branch is chosen when no channel is valid.
414
+ 4'd1: chnl_idx = hit_priority[0] ? 4'd2 :
415
+ hit_priority[1] ? 4'd3 :
416
+ hit_priority[2] ? 4'd4 :
417
+ hit_priority[3] ? 4'd5 :
418
+ hit_priority[4] ? 4'd6 :
419
+ hit_priority[5] ? 4'd7 :
420
+ hit_priority[6] ? 4'd8 :
421
+ hit_priority[7] ? 4'd0 :
422
+ hit_priority[8] ? 4'd1 : 4'd2 ; // last branch is chosen when no channel is valid.
423
+ 4'd2: chnl_idx = hit_priority[0] ? 4'd3 :
424
+ hit_priority[1] ? 4'd4 :
425
+ hit_priority[2] ? 4'd5 :
426
+ hit_priority[3] ? 4'd6 :
427
+ hit_priority[4] ? 4'd7 :
428
+ hit_priority[5] ? 4'd8 :
429
+ hit_priority[6] ? 4'd0 :
430
+ hit_priority[7] ? 4'd1 :
431
+ hit_priority[8] ? 4'd2 : 4'd3 ; // last branch is chosen when no channel is valid.
432
+ 4'd3: chnl_idx = hit_priority[0] ? 4'd4 :
433
+ hit_priority[1] ? 4'd5 :
434
+ hit_priority[2] ? 4'd6 :
435
+ hit_priority[3] ? 4'd7 :
436
+ hit_priority[4] ? 4'd8 :
437
+ hit_priority[5] ? 4'd0 :
438
+ hit_priority[6] ? 4'd1 :
439
+ hit_priority[7] ? 4'd2 :
440
+ hit_priority[8] ? 4'd3 : 4'd4 ; // last branch is chosen when no channel is valid.
441
+ 4'd4: chnl_idx = hit_priority[0] ? 4'd5 :
442
+ hit_priority[1] ? 4'd6 :
443
+ hit_priority[2] ? 4'd7 :
444
+ hit_priority[3] ? 4'd8 :
445
+ hit_priority[4] ? 4'd0 :
446
+ hit_priority[5] ? 4'd1 :
447
+ hit_priority[6] ? 4'd2 :
448
+ hit_priority[7] ? 4'd3 :
449
+ hit_priority[8] ? 4'd4 : 4'd5 ; // last branch is chosen when no channel is valid.
450
+ 4'd5: chnl_idx = hit_priority[0] ? 4'd6 :
451
+ hit_priority[1] ? 4'd7 :
452
+ hit_priority[2] ? 4'd8 :
453
+ hit_priority[3] ? 4'd0 :
454
+ hit_priority[4] ? 4'd1 :
455
+ hit_priority[5] ? 4'd2 :
456
+ hit_priority[6] ? 4'd3 :
457
+ hit_priority[7] ? 4'd4 :
458
+ hit_priority[8] ? 4'd5 : 4'd6 ; // last branch is chosen when no channel is valid.
459
+ 4'd6: chnl_idx = hit_priority[0] ? 4'd7 :
460
+ hit_priority[1] ? 4'd8 :
461
+ hit_priority[2] ? 4'd0 :
462
+ hit_priority[3] ? 4'd1 :
463
+ hit_priority[4] ? 4'd2 :
464
+ hit_priority[5] ? 4'd3 :
465
+ hit_priority[6] ? 4'd4 :
466
+ hit_priority[7] ? 4'd5 :
467
+ hit_priority[8] ? 4'd6 : 4'd7 ; // last branch is chosen when no channel is valid.
468
+ 4'd7: chnl_idx = hit_priority[0] ? 4'd8 :
469
+ hit_priority[1] ? 4'd0 :
470
+ hit_priority[2] ? 4'd1 :
471
+ hit_priority[3] ? 4'd2 :
472
+ hit_priority[4] ? 4'd3 :
473
+ hit_priority[5] ? 4'd4 :
474
+ hit_priority[6] ? 4'd5 :
475
+ hit_priority[7] ? 4'd6 :
476
+ hit_priority[8] ? 4'd7 : 4'd8 ; // last branch is chosen when no channel is valid.
477
+ 4'd8: chnl_idx = hit_priority[0] ? 4'd0 :
478
+ hit_priority[1] ? 4'd1 :
479
+ hit_priority[2] ? 4'd2 :
480
+ hit_priority[3] ? 4'd3 :
481
+ hit_priority[4] ? 4'd4 :
482
+ hit_priority[5] ? 4'd5 :
483
+ hit_priority[6] ? 4'd6 :
484
+ hit_priority[7] ? 4'd7 :
485
+ hit_priority[8] ? 4'd8 : 4'd0 ; // last branch is chosen when no channel is valid.
486
+ default: chnl_idx = {CHNL_NUM_LOG{1'd0}};
487
+ endcase
488
+ end
489
+ else begin
490
+ chnl_idx = chnl_idx_reg; // chosen in REQ_TRANS state
491
+ end
492
+ end
493
+
494
+ end // CHANNEL_NUM == 9
495
+ else if (CHANNEL_NUM == 8) begin:CHNL_SEL_8
496
+
497
+ always @(*) begin
498
+ if (is_schedule) begin
499
+ case (last_chnl)
500
+ 3'd0: chnl_idx = hit_priority[0] ? 3'd1 :
501
+ hit_priority[1] ? 3'd2 :
502
+ hit_priority[2] ? 3'd3 :
503
+ hit_priority[3] ? 3'd4 :
504
+ hit_priority[4] ? 3'd5 :
505
+ hit_priority[5] ? 3'd6 :
506
+ hit_priority[6] ? 3'd7 :
507
+ hit_priority[7] ? 3'd0 : 3'd1 ; // last branch is chosen when no channel is valid.
508
+ 3'd1: chnl_idx = hit_priority[0] ? 3'd2 :
509
+ hit_priority[1] ? 3'd3 :
510
+ hit_priority[2] ? 3'd4 :
511
+ hit_priority[3] ? 3'd5 :
512
+ hit_priority[4] ? 3'd6 :
513
+ hit_priority[5] ? 3'd7 :
514
+ hit_priority[6] ? 3'd0 :
515
+ hit_priority[7] ? 3'd1 : 3'd2 ; // last branch is chosen when no channel is valid.
516
+ 3'd2: chnl_idx = hit_priority[0] ? 3'd3 :
517
+ hit_priority[1] ? 3'd4 :
518
+ hit_priority[2] ? 3'd5 :
519
+ hit_priority[3] ? 3'd6 :
520
+ hit_priority[4] ? 3'd7 :
521
+ hit_priority[5] ? 3'd0 :
522
+ hit_priority[6] ? 3'd1 :
523
+ hit_priority[7] ? 3'd2 : 3'd3 ; // last branch is chosen when no channel is valid.
524
+ 3'd3: chnl_idx = hit_priority[0] ? 3'd4 :
525
+ hit_priority[1] ? 3'd5 :
526
+ hit_priority[2] ? 3'd6 :
527
+ hit_priority[3] ? 3'd7 :
528
+ hit_priority[4] ? 3'd0 :
529
+ hit_priority[5] ? 3'd1 :
530
+ hit_priority[6] ? 3'd2 :
531
+ hit_priority[7] ? 3'd3 : 3'd4 ; // last branch is chosen when no channel is valid.
532
+ 3'd4: chnl_idx = hit_priority[0] ? 3'd5 :
533
+ hit_priority[1] ? 3'd6 :
534
+ hit_priority[2] ? 3'd7 :
535
+ hit_priority[3] ? 3'd0 :
536
+ hit_priority[4] ? 3'd1 :
537
+ hit_priority[5] ? 3'd2 :
538
+ hit_priority[6] ? 3'd3 :
539
+ hit_priority[7] ? 3'd4 : 3'd5 ; // last branch is chosen when no channel is valid.
540
+ 3'd5: chnl_idx = hit_priority[0] ? 3'd6 :
541
+ hit_priority[1] ? 3'd7 :
542
+ hit_priority[2] ? 3'd0 :
543
+ hit_priority[3] ? 3'd1 :
544
+ hit_priority[4] ? 3'd2 :
545
+ hit_priority[5] ? 3'd3 :
546
+ hit_priority[6] ? 3'd4 :
547
+ hit_priority[7] ? 3'd5 : 3'd6 ; // last branch is chosen when no channel is valid.
548
+ 3'd6: chnl_idx = hit_priority[0] ? 3'd7 :
549
+ hit_priority[1] ? 3'd0 :
550
+ hit_priority[2] ? 3'd1 :
551
+ hit_priority[3] ? 3'd2 :
552
+ hit_priority[4] ? 3'd3 :
553
+ hit_priority[5] ? 3'd4 :
554
+ hit_priority[6] ? 3'd5 :
555
+ hit_priority[7] ? 3'd6 : 3'd7 ; // last branch is chosen when no channel is valid.
556
+ 3'd7: chnl_idx = hit_priority[0] ? 3'd0 :
557
+ hit_priority[1] ? 3'd1 :
558
+ hit_priority[2] ? 3'd2 :
559
+ hit_priority[3] ? 3'd3 :
560
+ hit_priority[4] ? 3'd4 :
561
+ hit_priority[5] ? 3'd5 :
562
+ hit_priority[6] ? 3'd6 :
563
+ hit_priority[7] ? 3'd7 : 3'd0 ; // last branch is chosen when no channel is valid.
564
+ default: chnl_idx = {CHNL_NUM_LOG{1'd0}};
565
+ endcase
566
+ end
567
+ else begin
568
+ chnl_idx = chnl_idx_reg; // chosen in REQ_TRANS state
569
+ end
570
+ end
571
+
572
+ end // CHANNEL_NUM == 8
573
+ else if (CHANNEL_NUM == 7) begin:CHNL_SEL_7
574
+
575
+ always @(*) begin
576
+ if (is_schedule) begin
577
+ case (last_chnl)
578
+ 0: chnl_idx = hit_priority[0] ? 1 :
579
+ hit_priority[1] ? 2 :
580
+ hit_priority[2] ? 3 :
581
+ hit_priority[3] ? 4 :
582
+ hit_priority[4] ? 5 :
583
+ hit_priority[5] ? 6 :
584
+ hit_priority[6] ? 0 : 1 ; // last branch is chosen when no channel is valid.
585
+ 1: chnl_idx = hit_priority[0] ? 2 :
586
+ hit_priority[1] ? 3 :
587
+ hit_priority[2] ? 4 :
588
+ hit_priority[3] ? 5 :
589
+ hit_priority[4] ? 6 :
590
+ hit_priority[5] ? 0 :
591
+ hit_priority[6] ? 1 : 2 ; // last branch is chosen when no channel is valid.
592
+ 2: chnl_idx = hit_priority[0] ? 3 :
593
+ hit_priority[1] ? 4 :
594
+ hit_priority[2] ? 5 :
595
+ hit_priority[3] ? 6 :
596
+ hit_priority[4] ? 0 :
597
+ hit_priority[5] ? 1 :
598
+ hit_priority[6] ? 2 : 3 ; // last branch is chosen when no channel is valid.
599
+ 3: chnl_idx = hit_priority[0] ? 4 :
600
+ hit_priority[1] ? 5 :
601
+ hit_priority[2] ? 6 :
602
+ hit_priority[3] ? 0 :
603
+ hit_priority[4] ? 1 :
604
+ hit_priority[5] ? 2 :
605
+ hit_priority[6] ? 3 : 4 ; // last branch is chosen when no channel is valid.
606
+ 4: chnl_idx = hit_priority[0] ? 5 :
607
+ hit_priority[1] ? 6 :
608
+ hit_priority[2] ? 0 :
609
+ hit_priority[3] ? 1 :
610
+ hit_priority[4] ? 2 :
611
+ hit_priority[5] ? 3 :
612
+ hit_priority[6] ? 4 : 5 ; // last branch is chosen when no channel is valid.
613
+ 5: chnl_idx = hit_priority[0] ? 6 :
614
+ hit_priority[1] ? 0 :
615
+ hit_priority[2] ? 1 :
616
+ hit_priority[3] ? 2 :
617
+ hit_priority[4] ? 3 :
618
+ hit_priority[5] ? 4 :
619
+ hit_priority[6] ? 5 : 6 ; // last branch is chosen when no channel is valid.
620
+ 6: chnl_idx = hit_priority[0] ? 0 :
621
+ hit_priority[1] ? 1 :
622
+ hit_priority[2] ? 2 :
623
+ hit_priority[3] ? 3 :
624
+ hit_priority[4] ? 4 :
625
+ hit_priority[5] ? 5 :
626
+ hit_priority[6] ? 6 : 0 ; // last branch is chosen when no channel is valid.
627
+ default: chnl_idx = {CHNL_NUM_LOG{1'd0}};
628
+ endcase
629
+ end
630
+ else begin
631
+ chnl_idx = chnl_idx_reg; // chosen in REQ_TRANS state
632
+ end
633
+ end
634
+
635
+ end // CHANNEL_NUM == 7
636
+ else if (CHANNEL_NUM == 6) begin:CHNL_SEL_6
637
+
638
+ always @(*) begin
639
+ if (is_schedule) begin
640
+ case (last_chnl)
641
+ 0: chnl_idx = hit_priority[0] ? 1 :
642
+ hit_priority[1] ? 2 :
643
+ hit_priority[2] ? 3 :
644
+ hit_priority[3] ? 4 :
645
+ hit_priority[4] ? 5 :
646
+ hit_priority[5] ? 0 : 1 ; // last branch is chosen when no channel is valid.
647
+ 1: chnl_idx = hit_priority[0] ? 2 :
648
+ hit_priority[1] ? 3 :
649
+ hit_priority[2] ? 4 :
650
+ hit_priority[3] ? 5 :
651
+ hit_priority[4] ? 0 :
652
+ hit_priority[5] ? 1 : 2 ; // last branch is chosen when no channel is valid.
653
+ 2: chnl_idx = hit_priority[0] ? 3 :
654
+ hit_priority[1] ? 4 :
655
+ hit_priority[2] ? 5 :
656
+ hit_priority[3] ? 0 :
657
+ hit_priority[4] ? 1 :
658
+ hit_priority[5] ? 2 : 3 ; // last branch is chosen when no channel is valid.
659
+ 3: chnl_idx = hit_priority[0] ? 4 :
660
+ hit_priority[1] ? 5 :
661
+ hit_priority[2] ? 0 :
662
+ hit_priority[3] ? 1 :
663
+ hit_priority[4] ? 2 :
664
+ hit_priority[5] ? 3 : 4 ; // last branch is chosen when no channel is valid.
665
+ 4: chnl_idx = hit_priority[0] ? 5 :
666
+ hit_priority[1] ? 0 :
667
+ hit_priority[2] ? 1 :
668
+ hit_priority[3] ? 2 :
669
+ hit_priority[4] ? 3 :
670
+ hit_priority[5] ? 4 : 5 ; // last branch is chosen when no channel is valid.
671
+ 5: chnl_idx = hit_priority[0] ? 0 :
672
+ hit_priority[1] ? 1 :
673
+ hit_priority[2] ? 2 :
674
+ hit_priority[3] ? 3 :
675
+ hit_priority[4] ? 4 :
676
+ hit_priority[5] ? 5 : 0 ; // last branch is chosen when no channel is valid.
677
+ default: chnl_idx = {CHNL_NUM_LOG{1'd0}};
678
+ endcase
679
+ end
680
+ else begin
681
+ chnl_idx = chnl_idx_reg; // chosen in REQ_TRANS state
682
+ end
683
+ end
684
+
685
+ end // CHANNEL_NUM == 6
686
+ else if (CHANNEL_NUM == 5) begin:CHNL_SEL_5
687
+
688
+ always @(*) begin
689
+ if (is_schedule) begin
690
+ case (last_chnl)
691
+ 0: chnl_idx = hit_priority[0] ? 1 :
692
+ hit_priority[1] ? 2 :
693
+ hit_priority[2] ? 3 :
694
+ hit_priority[3] ? 4 :
695
+ hit_priority[4] ? 0 : 1 ; // last branch is chosen when no channel is valid.
696
+ 1: chnl_idx = hit_priority[0] ? 2 :
697
+ hit_priority[1] ? 3 :
698
+ hit_priority[2] ? 4 :
699
+ hit_priority[3] ? 0 :
700
+ hit_priority[4] ? 1 : 2 ; // last branch is chosen when no channel is valid.
701
+ 2: chnl_idx = hit_priority[0] ? 3 :
702
+ hit_priority[1] ? 4 :
703
+ hit_priority[2] ? 0 :
704
+ hit_priority[3] ? 1 :
705
+ hit_priority[4] ? 2 : 3 ; // last branch is chosen when no channel is valid.
706
+ 3: chnl_idx = hit_priority[0] ? 4 :
707
+ hit_priority[1] ? 0 :
708
+ hit_priority[2] ? 1 :
709
+ hit_priority[3] ? 2 :
710
+ hit_priority[4] ? 3 : 4 ; // last branch is chosen when no channel is valid.
711
+ 4: chnl_idx = hit_priority[0] ? 0 :
712
+ hit_priority[1] ? 1 :
713
+ hit_priority[2] ? 2 :
714
+ hit_priority[3] ? 3 :
715
+ hit_priority[4] ? 4 : 0 ; // last branch is chosen when no channel is valid.
716
+ default: chnl_idx = {CHNL_NUM_LOG{1'd0}};
717
+ endcase
718
+ end
719
+ else begin
720
+ chnl_idx = chnl_idx_reg; // chosen in REQ_TRANS state
721
+ end
722
+ end
723
+
724
+ end // CHANNEL_NUM == 5
725
+ else if (CHANNEL_NUM == 4) begin:CHNL_SEL_4
726
+
727
+ always @(*) begin
728
+ if (is_schedule) begin
729
+ case (last_chnl)
730
+ 0: chnl_idx = hit_priority[0] ? 1 :
731
+ hit_priority[1] ? 2 :
732
+ hit_priority[2] ? 3 :
733
+ hit_priority[3] ? 0 : 1 ; // last branch is chosen when no channel is valid.
734
+ 1: chnl_idx = hit_priority[0] ? 2 :
735
+ hit_priority[1] ? 3 :
736
+ hit_priority[2] ? 0 :
737
+ hit_priority[3] ? 1 : 2 ; // last branch is chosen when no channel is valid.
738
+ 2: chnl_idx = hit_priority[0] ? 3 :
739
+ hit_priority[1] ? 0 :
740
+ hit_priority[2] ? 1 :
741
+ hit_priority[3] ? 2 : 3 ; // last branch is chosen when no channel is valid.
742
+ 3: chnl_idx = hit_priority[0] ? 0 :
743
+ hit_priority[1] ? 1 :
744
+ hit_priority[2] ? 2 :
745
+ hit_priority[3] ? 3 : 0 ; // last branch is chosen when no channel is valid.
746
+ default: chnl_idx = {CHNL_NUM_LOG{1'd0}};
747
+ endcase
748
+ end
749
+ else begin
750
+ chnl_idx = chnl_idx_reg; // chosen in REQ_TRANS state
751
+ end
752
+ end
753
+
754
+ end // CHANNEL_NUM == 4
755
+ else if (CHANNEL_NUM == 3) begin:CHNL_SEL_3
756
+
757
+ always @(*) begin
758
+ if (is_schedule) begin
759
+ case (last_chnl)
760
+ 0: chnl_idx = hit_priority[0] ? 1 :
761
+ hit_priority[1] ? 2 :
762
+ hit_priority[2] ? 0 : 1; // last branch is chosen when no channel is valid.
763
+ 1: chnl_idx = hit_priority[0] ? 2 :
764
+ hit_priority[1] ? 0 :
765
+ hit_priority[2] ? 1 : 2; // last branch is chosen when no channel is valid.
766
+ 2: chnl_idx = hit_priority[0] ? 0 :
767
+ hit_priority[1] ? 1 :
768
+ hit_priority[2] ? 2 : 0; // last branch is chosen when no channel is valid.
769
+ default: chnl_idx = {CHNL_NUM_LOG{1'd0}};
770
+ endcase
771
+ end
772
+ else begin
773
+ chnl_idx = chnl_idx_reg; // chosen in REQ_TRANS state
774
+ end
775
+ end
776
+
777
+ end // CHANNEL_NUM == 3
778
+ else if (CHANNEL_NUM == 2) begin:CHNL_SEL_2
779
+
780
+ always @(*) begin
781
+ if (is_schedule) begin
782
+ case (last_chnl)
783
+ 1'd0: chnl_idx = hit_priority[0] ? 1'd1 :
784
+ hit_priority[1] ? 1'd0 : 1'd1 ; // last branch is chosen when no channel is valid.
785
+ 1'd1: chnl_idx = hit_priority[0] ? 1'd0 :
786
+ hit_priority[1] ? 1'd1 : 1'd0 ; // last branch is chosen when no channel is valid.
787
+ default: chnl_idx = {CHNL_NUM_LOG{1'd0}};
788
+ endcase
789
+ end
790
+ else begin
791
+ chnl_idx = chnl_idx_reg; // chosen in REQ_TRANS state
792
+ end
793
+ end
794
+
795
+ end // CHANNEL_NUM == 2
796
+ endgenerate
797
+ /*
798
+ This is used for different Channel Numbers, the default Number is 4 */
799
+ /* -------Generate block{end}------- */
800
+
801
+ // /* -------Core logic to arbit, a parameterized arbiter{begin}------- */
802
+ // function [CHNL_NUM_LOG-1:0] find_chnl_num;
803
+ // input [CHNL_NUM_LOG-1:0] prio_level;
804
+ // input [CHNL_NUM_LOG-1:0] last_c;
805
+ // begin
806
+ // find_chnl_num = ((last_c+prio_level+1) >= CHANNEL_NUM) ? last_c+prio_level+1-CHANNEL_NUM : last_c+prio_level+1;
807
+ // end
808
+ // endfunction
809
+
810
+ // function [CHANNEL_NUM-1:0] sel_prio;
811
+ // input [CHANNEL_NUM-1:0] sel;
812
+ // reg tmp;
813
+ // integer i, j;
814
+ // begin
815
+ // sel_prio[0] = sel[0];
816
+ // for (i = 1; i < CHANNEL_NUM; i = i + 1) begin
817
+ // tmp = 0;
818
+ // for (j = 0; j < i; j = j + 1) begin
819
+ // tmp = tmp | sel[j];
820
+ // end
821
+ // sel_prio[i] = !tmp & sel[i];
822
+ // end
823
+ // end
824
+ // endfunction
825
+
826
+ // function [CHNL_NUM_LOG-1:0] find_nxt_chnl;
827
+ // input [CHNL_NUM_LOG-1:0] last_c;
828
+ // input [CHANNEL_NUM-1:0] hit_prio;
829
+ // integer i;
830
+ // begin
831
+ // find_nxt_chnl = {CHNL_NUM_LOG{hit_prio[0]}} & find_chnl_num(0, last_c);
832
+ // for (i = 1; i < CHANNEL_NUM; i = i + 1) begin
833
+ // find_nxt_chnl = find_nxt_chnl | {CHNL_NUM_LOG{hit_prio[i]}} & find_chnl_num(i, last_c);;
834
+ // end
835
+ // end
836
+ // endfunction
837
+
838
+ // always @(*) begin
839
+ // if (is_schedule) begin
840
+ // chnl_idx = find_nxt_chnl(last_chnl, sel_prio(hit_priority));
841
+ // end
842
+ // else begin
843
+ // chnl_idx = chnl_idx_reg; // chosen in REQ_TRANS state
844
+ // end
845
+ // end
846
+ // /* -------Core logic to arbit, a parameterized arbiter{end}------- */
847
+
848
+ // state transform signal
849
+ assign req_last = m_axis_req_tvalid & m_axis_req_tready & m_axis_req_tlast;
850
+
851
+ /* -------Find next channel{end}------- */
852
+
853
+ /* -------{Read Request Arbiter FSM}begin------- */
854
+ /******************** Stage 1: State Register **********************/
855
+ assign is_idle = (cur_state == IDLE );
856
+ assign is_schedule = (cur_state == SCHEDULE );
857
+ assign is_req_trans = (cur_state == REQ_TRANS);
858
+ assign j_req_trans = is_schedule & (!req_last) & (|s_axis_req_tvalid);
859
+ // assign j_schedule = is_schedule & (req_last) |
860
+ // is_req_trans & (req_last);
861
+
862
+ always @(posedge dma_clk, negedge rst_n) begin
863
+ if(~rst_n)
864
+ cur_state <= `TD IDLE;
865
+ else
866
+ cur_state <= `TD nxt_state;
867
+ end
868
+
869
+ /******************** Stage 2: State Transition **********************/
870
+
871
+ always @(*) begin
872
+ case(cur_state)
873
+ IDLE: begin
874
+ if (|s_axis_req_tvalid) begin
875
+ nxt_state = SCHEDULE;
876
+ end
877
+ else begin
878
+ nxt_state = IDLE;
879
+ end
880
+ end
881
+ SCHEDULE: begin
882
+ if (req_last) begin // one beat request has already been transmited in
883
+ // schedule state.
884
+ nxt_state = SCHEDULE;
885
+ end
886
+ else if (|s_axis_req_tvalid) begin // There's valid channel, and not the last beat.
887
+ nxt_state = REQ_TRANS;
888
+ end
889
+ else begin
890
+ nxt_state = IDLE;
891
+ end
892
+ end
893
+ REQ_TRANS: begin
894
+ if (req_last) begin // request has already been transmited in
895
+ // req_trans state.
896
+ nxt_state = SCHEDULE;
897
+ end
898
+ else begin
899
+ nxt_state = REQ_TRANS;
900
+ end
901
+ end
902
+ default: begin
903
+ nxt_state = IDLE;
904
+ end
905
+ endcase
906
+ end
907
+ /******************** Stage 3: Output **********************/
908
+
909
+ /* -------Generate block{begin}------- */
910
+ genvar n;
911
+ generate
912
+ for (n = 0; n < CHANNEL_NUM; n = n + 1) begin:CHNL_ASSIGN
913
+
914
+ assign s_axis_req_tready[n] = (is_schedule | is_req_trans) & (n == chnl_idx) & m_axis_req_tready;
915
+
916
+ assign s_channel_tvalid[n] = s_axis_req_tvalid[((n+1) * 1 -1):(n * 1 )];
917
+ assign s_channel_tlast [n] = s_axis_req_tlast [((n+1) * 1 -1):(n * 1 )];
918
+ assign s_channel_tdata [n] = s_axis_req_tdata [((n+1) * `DMA_DATA_W -1):(n * `DMA_DATA_W )];
919
+ assign s_channel_tuser [n] = s_axis_req_tuser [((n+1) * `AXIS_TUSER_W-1):(n * `AXIS_TUSER_W)];
920
+ assign s_channel_tkeep [n] = s_axis_req_tkeep [((n+1) * `DMA_KEEP_W -1):(n * `DMA_KEEP_W )];
921
+
922
+ assign hit_priority[n] = s_channel_tvalid[nxt_priority[n]];
923
+
924
+ end
925
+ endgenerate
926
+ /* -------Generate block{end}------- */
927
+
928
+ assign m_axis_req_tvalid = (is_schedule | is_req_trans) ? s_channel_tvalid[chnl_idx] : 1'd0;
929
+ assign m_axis_req_tlast = (is_schedule | is_req_trans) ? s_channel_tlast [chnl_idx] : 1'd0;
930
+ assign m_axis_req_tdata = (is_schedule | is_req_trans) ? s_channel_tdata [chnl_idx] : {`DMA_DATA_W{1'd0}};
931
+ assign m_axis_req_tuser = (is_schedule | is_req_trans) ? s_channel_tuser [chnl_idx] : {`AXIS_TUSER_W{1'd0}};
932
+ assign m_axis_req_tkeep = (is_schedule | is_req_trans) ? s_channel_tkeep [chnl_idx] : {`DMA_KEEP_W{1'd0}};
933
+
934
+ /* -------{Read Request Arbiter FSM}end------- */
935
+
936
+
937
+ endmodule
ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/DMA/req_converter.v ADDED
@@ -0,0 +1,290 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ `timescale 1ns / 100ps
2
+ //*************************************************************************
3
+ // > File Name: req_converter.v
4
+ // > Author : Kangning
5
+ // > Date : 2020-08-25
6
+ // > Note : req_converter used to convert AXI-Stream into
7
+ // > Xilinx PCIe compatible interface.
8
+ //*************************************************************************
9
+
10
+ //`include "../lib/global_include_h.v"
11
+
12
+ module req_converter #(
13
+
14
+ ) (
15
+ input wire pcie_clk ,
16
+ input wire pcie_rst_n,
17
+ input wire dma_clk ,
18
+ input wire rst_n ,
19
+
20
+
21
+ /* ------- Interface with Request Arbiter{begin} ------- */
22
+ /* AXI-Stream request tuser, only valid in first beat of a packet
23
+ * | Reserved | REQ_TYPE | Tag | address | Reserved | DW length | first BE | last BE |
24
+ * | 127:108 | 107:104 | 103:96 | 95:32 | 31:19 | 18:8 | 7:4 | 3:0 |
25
+ * or
26
+ * AXI-Stream interrupt request tuser, only valid in first beat of a packet
27
+ * | Reserved | REQ_TYPE | Resv | address | Reserved |
28
+ * | 127:108 | 107:104 | 103:96 | 95:32 | 31:0 |
29
+ */
30
+ input wire axis_req_tvalid, // i, 1
31
+ input wire axis_req_tlast , // i, 1
32
+ input wire [`DMA_DATA_W -1:0] axis_req_tdata , // i, `DMA_DATA_W
33
+ input wire [`AXIS_TUSER_W-1:0] axis_req_tuser , // i, `AXIS_TUSER_W
34
+ input wire [`DMA_KEEP_W -1:0] axis_req_tkeep , // i, `DMA_KEEP_W
35
+ output wire axis_req_tready, // o, 1
36
+ /* ------- Interface with Request Arbiter{end} ------- */
37
+
38
+
39
+ /* -------dma --> pcie interface{begin}------- */
40
+ // Requester request
41
+ /* RQ tuser
42
+ * | 59:28 | 27:24 | 23:16 | 15 | 14:13 | 12 | 11 | 10:8 | 7:4 | 3:0 |
43
+ * | parity | seq_num | tph_st_tag | tph_indirect_tag_en | tph_type | tph_present | discontinue | addr_offset | last_be | first_be |
44
+ * | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | |
45
+ */
46
+ output wire s_axis_rq_tvalid, // o, 1
47
+ output wire s_axis_rq_tlast , // o, 1
48
+ output wire [`DMA_DATA_W-1:0] s_axis_rq_tdata , // o, `DMA_DATA_W
49
+ output wire [59 :0] s_axis_rq_tuser , // o, 60
50
+ output wire [`DMA_KEEP_W-1:0] s_axis_rq_tkeep , // o, `DMA_KEEP_W
51
+ input wire s_axis_rq_tready, // i, 1
52
+ /* -------dma --> pcie interface{end}------- */
53
+
54
+ input wire [15:0] req_id_in, // i, 16
55
+
56
+ /* -------Interrupt Interface Signals{begin}------- */
57
+ input [1:0] cfg_interrupt_msix_enable ,
58
+ input [1:0] cfg_interrupt_msix_mask ,
59
+ output [31:0] cfg_interrupt_msix_data ,
60
+ output [63:0] cfg_interrupt_msix_address ,
61
+ output cfg_interrupt_msix_int ,
62
+ input cfg_interrupt_msix_sent ,
63
+ input cfg_interrupt_msix_fail ,
64
+ output wire [2:0] cfg_interrupt_msi_function_number
65
+ /* -------Interrupt Interface Signals{end}------- */
66
+
67
+ `ifdef PCIEI_APB_DBG
68
+ /* -------APB reated signal{begin}------- */
69
+ ,input wire [`SRAM_RW_DATA_W-1:0] rw_data // i, `SRAM_RW_DATA_W
70
+ ,input wire [31:0] dbg_sel // debug bus select
71
+ ,output wire [31:0] dbg_bus // debug bus data
72
+ /* -------APB reated signal{end}------- */
73
+ `endif
74
+ );
75
+
76
+ /*-------Interrupt related logic{begin}------- */
77
+ wire int_req_valid;
78
+ wire [31:0] int_req_data ;
79
+ wire [63:0] int_req_addr ;
80
+ wire int_req_ready;
81
+ /*-------Interrupt related logic{end}------- */
82
+
83
+ /* -------related to input regs{begin}------- */
84
+ wire input_tready;
85
+
86
+ wire in_reg_tvalid;
87
+ wire in_reg_tlast ;
88
+ wire [`DMA_DATA_W -1:0] in_reg_tdata ;
89
+ wire [`AXIS_TUSER_W-1:0] in_reg_tuser ;
90
+ wire [`DMA_KEEP_W -1:0] in_reg_tkeep ;
91
+ wire in_reg_tready;
92
+ /* -------related to input regs{end}------- */
93
+
94
+ /* -------RQ head{begin}------- */
95
+ wire [2 :0] attr;
96
+ wire [2 :0] tc;
97
+ wire [15:0] cpl_id;
98
+ wire [7 :0] tag;
99
+ reg [15:0] req_id;
100
+ wire [10:0] dw_cnt;
101
+ wire [3 :0] req_type;
102
+ wire [127:0] rq_head;
103
+ /* -------RQ head{end}------- */
104
+
105
+ /* -------data realignment{begin}------- */
106
+ reg [127:0] tmp_reg_data;
107
+ reg [3 :0] tmp_reg_keep;
108
+
109
+ reg head_beat; // first beat of an s_axis_rq_* packet
110
+ reg tmp_beat; // data in tmp_reg as the last beat of s_axis_rq_* interface for output
111
+
112
+ wire st_tmp; // store tmp_reg in the last beat of axis_req_* interface
113
+ /* -------data realignment{end}------- */
114
+
115
+ `ifdef PCIEI_APB_DBG
116
+ /* -------APB reated signal{begin}------- */
117
+ wire [`REQ_CONVERT_TOP_SIGNAL_W-1:0] req_convert_top_dbg_signal;
118
+ wire [`INT_PROC_SIGNAL_W-1:0] int_proc_dbg_signal;
119
+ /* -------APB reated signal{end}------- */
120
+ `endif
121
+
122
+ //---------------------------------------------------------------------------------------------------------------------------
123
+
124
+ `ifdef PCIEI_APB_DBG
125
+ /* -------APB reated signal{begin}------- */
126
+ assign dbg_bus = {req_convert_top_dbg_signal, int_proc_dbg_signal} >> {dbg_sel, 5'd0}; // 924
127
+
128
+ assign req_convert_top_dbg_signal = { // 818
129
+ int_req_valid, int_req_data, int_req_addr, int_req_ready, // 98
130
+ input_tready, // 1
131
+ in_reg_tvalid, in_reg_tlast, in_reg_tdata, in_reg_tuser, in_reg_tkeep, in_reg_tready, // 395
132
+ attr, tc, cpl_id, tag, req_id, dw_cnt, req_type, rq_head, // 189
133
+ tmp_reg_data, tmp_reg_keep, // 132
134
+ head_beat, tmp_beat, // 2
135
+ st_tmp // 1
136
+ };
137
+ /* -------APB reated signal{end}------- */
138
+ `endif
139
+
140
+ /*-------Interrupt related logic{begin}------- */
141
+ assign int_req_valid = axis_req_tuser[107:104] == `DMA_INT_REQ;
142
+ assign int_req_data = axis_req_tdata[31:0];
143
+ assign int_req_addr = axis_req_tuser[95:32];
144
+
145
+ int_proc int_proc (
146
+ .pcie_clk ( pcie_clk ), // i, 1
147
+ .pcie_rst_n ( pcie_rst_n ), // i, 1
148
+ .dma_clk ( dma_clk ), // i, 1
149
+ .rst_n ( rst_n ), // i, 1
150
+
151
+ .int_req_valid ( int_req_valid ), // i,, 1
152
+ .int_req_data ( int_req_data ), // i,, 32
153
+ .int_req_addr ( int_req_addr ), // i,, 64
154
+ .int_req_ready ( int_req_ready ), // o,, 1
155
+
156
+ /* -------Interrupt Interface Signals{begin}------- */
157
+ .cfg_interrupt_msix_enable ( cfg_interrupt_msix_enable ), // i, 2
158
+ .cfg_interrupt_msix_mask ( cfg_interrupt_msix_mask ), // i, 2
159
+ .cfg_interrupt_msix_data ( cfg_interrupt_msix_data ), // o, 32
160
+ .cfg_interrupt_msix_address ( cfg_interrupt_msix_address ), // o, 64
161
+ .cfg_interrupt_msix_int ( cfg_interrupt_msix_int ), // o, 1
162
+ .cfg_interrupt_msix_sent ( cfg_interrupt_msix_sent ), // i, 1
163
+ .cfg_interrupt_msix_fail ( cfg_interrupt_msix_fail ), // i, 1
164
+ .cfg_interrupt_msi_function_number ( cfg_interrupt_msi_function_number ) // o, 3
165
+ /* -------Interrupt Interface Signals{end}------- */
166
+
167
+ `ifdef PCIEI_APB_DBG
168
+ /* -------APB reated signal{begin}------- */
169
+ ,.rw_data ( rw_data ) // i, `SRAM_RW_DATA_W
170
+ ,.dbg_signal ( int_proc_dbg_signal ) // o, `INT_PROC_SIGNAL_W
171
+ /* -------APB reated signal{end}------- */
172
+ `endif
173
+ );
174
+ /*-------Interrupt related logic{end}------- */
175
+
176
+ /* -------related to in_reg{begin}------- */
177
+ assign axis_req_tready = int_req_valid ? int_req_ready : input_tready;
178
+ st_reg #(
179
+ .TUSER_WIDTH ( `AXIS_TUSER_W ),
180
+ .TDATA_WIDTH ( `DMA_KEEP_W + `DMA_DATA_W )
181
+ ) in_reg (
182
+ .clk ( dma_clk ), // i, 1
183
+ .rst_n ( rst_n ), // i, 1
184
+
185
+ /* -------input axis-like interface{begin}------- */
186
+ .axis_tvalid ( axis_req_tvalid & (~int_req_valid)), // i, 1
187
+ .axis_tlast ( axis_req_tlast ), // i, 1
188
+ .axis_tuser ( axis_req_tuser ), // i, TUSER_WIDTH
189
+ .axis_tdata ( {axis_req_tkeep, axis_req_tdata} ), // i, TDATA_WIDTH
190
+ .axis_tready ( input_tready ), // o, 1
191
+ /* -------input axis-like interface{end}------- */
192
+
193
+ /* -------output in_reg inteface{begin}------- */
194
+ .axis_reg_tvalid ( in_reg_tvalid ), // o, 1
195
+ .axis_reg_tlast ( in_reg_tlast ), // o, 1
196
+ .axis_reg_tuser ( in_reg_tuser ), // o, TUSER_WIDTH
197
+ .axis_reg_tdata ( {in_reg_tkeep, in_reg_tdata} ), // o, TDATA_WIDTH
198
+ .axis_reg_tready ( in_reg_tready ) // i, 1
199
+ /* -------output in_reg inteface{end}------- */
200
+ );
201
+ /* -------related to in_reg{end}------- */
202
+
203
+ /* -------RQ head{begin}------- */
204
+ always @(posedge dma_clk, negedge rst_n) begin
205
+ if (~rst_n) begin
206
+ req_id <= `TD 0;
207
+ end
208
+ else begin
209
+ req_id <= req_id_in;
210
+ end
211
+ end
212
+
213
+ assign attr = 3'd0;
214
+ assign tc = 3'd0;
215
+ assign cpl_id = 16'd0;
216
+ assign tag = in_reg_tuser[103:96];
217
+ // assign req_id = 16'd0;
218
+ assign dw_cnt = in_reg_tuser[18:8];
219
+ assign req_type = in_reg_tuser[107:104];
220
+ assign rq_head = {1'd0, attr, tc, 1'd0, cpl_id, tag, req_id, 1'd0, req_type, dw_cnt,
221
+ in_reg_tuser[95:34], 2'd0};
222
+ /* -------RQ head{end}------- */
223
+
224
+
225
+ /* -------data realignment{begin}------- */
226
+ always @(posedge dma_clk, negedge rst_n) begin
227
+ if (~rst_n) begin
228
+ tmp_reg_data <= `TD 128'd0;
229
+ tmp_reg_keep <= `TD 4'd0;
230
+ end
231
+ else if (in_reg_tvalid & in_reg_tready) begin
232
+ tmp_reg_data <= `TD in_reg_tdata[255:128];
233
+ tmp_reg_keep <= `TD in_reg_tkeep[7:4];
234
+ end
235
+ end
236
+
237
+ always @(posedge dma_clk, negedge rst_n) begin
238
+ if (~rst_n) begin
239
+ head_beat <= `TD 1;
240
+ end
241
+ else if (s_axis_rq_tvalid & s_axis_rq_tready & s_axis_rq_tlast) begin
242
+ head_beat <= `TD 1;
243
+ end
244
+ else if (s_axis_rq_tvalid & s_axis_rq_tready) begin
245
+ head_beat <= `TD 0;
246
+ end
247
+ end
248
+
249
+ always @(posedge dma_clk, negedge rst_n) begin
250
+ if (~rst_n) begin
251
+ tmp_beat <= `TD 0;
252
+ end
253
+ else if (in_reg_tvalid & in_reg_tready & in_reg_tlast & st_tmp) begin
254
+ tmp_beat <= `TD 1;
255
+ end
256
+ else if (tmp_beat & s_axis_rq_tready) begin
257
+ tmp_beat <= `TD 0;
258
+ end
259
+ end
260
+
261
+ assign st_tmp = |in_reg_tkeep[7:4];
262
+ /* -------data realignment{end}------- */
263
+
264
+
265
+ /* -------output {begin}------- */
266
+ assign in_reg_tready = s_axis_rq_tready & !tmp_beat;
267
+
268
+
269
+ assign s_axis_rq_tvalid = in_reg_tvalid | tmp_beat;
270
+ assign s_axis_rq_tlast = (in_reg_tlast & !st_tmp) |
271
+ tmp_beat;
272
+
273
+
274
+ assign s_axis_rq_tdata = head_beat&in_reg_tvalid ? {in_reg_tdata[127:0], rq_head} :
275
+ tmp_beat ? {128'd0, tmp_reg_data} :
276
+ in_reg_tvalid ? {in_reg_tdata[127:0], tmp_reg_data} :
277
+ 256'd0;
278
+ assign s_axis_rq_tkeep = head_beat&in_reg_tvalid ? {in_reg_tkeep[3:0], 4'hf} :
279
+ tmp_beat ? {4'd0, tmp_reg_keep} :
280
+ in_reg_tvalid ? {in_reg_tkeep[3:0], tmp_reg_keep} :
281
+ 8'd0;
282
+
283
+
284
+ assign s_axis_rq_tuser = head_beat ? {32'd0, 4'd0, 8'd0, 1'd0, 2'd0, 1'd0, 1'd0, 3'd0,
285
+ in_reg_tuser[3:0], in_reg_tuser[7:4]} : 0;
286
+ /* -------output {end}------- */
287
+
288
+ /* -------{Read Request Arbiter FSM}end------- */
289
+
290
+ endmodule
ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/DMA/rq_async_fifos.v ADDED
@@ -0,0 +1,221 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ `timescale 1ns / 100ps
2
+ //*************************************************************************
3
+ // > File Name: rq_async_fifos.v
4
+ // > Author : Kangning
5
+ // > Date : 2021-08-16
6
+ // > Note : rq_async_fifos, used to separate rdma and pcie clock domain,
7
+ // > in RQ (Requester request channel).
8
+ //*************************************************************************
9
+
10
+ //`include "../lib/global_include_h.v"
11
+
12
+ module rq_async_fifos #(
13
+
14
+ ) (
15
+ input wire dma_clk ,
16
+ input wire pcie_clk ,
17
+ input wire dma_rst_n ,
18
+ input wire pcie_rst_n,
19
+
20
+
21
+ /* -------dma --> pcie interface, dma part{begin}------- */
22
+ // Requester request
23
+ /* RQ tuser
24
+ * | 59:28 | 27:24 | 23:16 | 15 | 14:13 | 12 | 11 | 10:8 | 7:4 | 3:0 |
25
+ * | parity | seq_num | tph_st_tag | tph_indirect_tag_en | tph_type | tph_present | discontinue | addr_offset | last_be | first_be |
26
+ * | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | |
27
+ */
28
+ input wire dma_axis_rq_tvalid, // o, 1
29
+ input wire dma_axis_rq_tlast , // o, 1
30
+ input wire [`DMA_DATA_W-1:0] dma_axis_rq_tdata , // o, `DMA_DATA_W
31
+ input wire [59 :0] dma_axis_rq_tuser , // o, 60
32
+ input wire [`DMA_KEEP_W-1:0] dma_axis_rq_tkeep , // o, `DMA_KEEP_W
33
+ output wire dma_axis_rq_tready, // i, 1
34
+ /* -------dma --> pcie interface, dma part{end}------- */
35
+
36
+ /* -------dma --> pcie interface, pcie part{begin}------- */
37
+ // Requester request
38
+ /* RQ tuser
39
+ * | 59:28 | 27:24 | 23:16 | 15 | 14:13 | 12 | 11 | 10:8 | 7:4 | 3:0 |
40
+ * | parity | seq_num | tph_st_tag | tph_indirect_tag_en | tph_type | tph_present | discontinue | addr_offset | last_be | first_be |
41
+ * | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | |
42
+ */
43
+ output wire st_pcie_axis_rq_tvalid, // o, 1
44
+ output wire st_pcie_axis_rq_tlast , // o, 1
45
+ output wire [`DMA_DATA_W-1:0] st_pcie_axis_rq_tdata , // o, `DMA_DATA_W
46
+ output wire [59 :0] st_pcie_axis_rq_tuser , // o, 60
47
+ output wire [`DMA_KEEP_W-1:0] st_pcie_axis_rq_tkeep , // o, `DMA_KEEP_W
48
+ input wire st_pcie_axis_rq_tready // i, 1
49
+ /* -------dma --> pcie interface, pcie part{begin}------- */
50
+
51
+ `ifdef PCIEI_APB_DBG
52
+ /* -------APB reated signal{begin}------- */
53
+ ,input wire [`SRAM_RW_DATA_W -1:0] rw_data // i, `SRAM_RW_DATA_W
54
+ ,output wire [`RQ_ASYNC_SIGNAL_W-1:0] dbg_signal // o, `RQ_ASYNC_SIGNAL_W
55
+ /* -------APB reated signal{end}------- */
56
+ `endif
57
+ );
58
+ wire dma_axis_rq_full;
59
+
60
+ /* -------tmp store the whole rq pkt{begin}------- */
61
+ wire fifo_out_ren ;
62
+ wire [1 + `DMA_KEEP_W + 8 + `DMA_DATA_W-1:0] fifo_out_tdata;
63
+ wire fifo_out_empty;
64
+
65
+ wire pkt_store_wen ;
66
+ wire pkt_store_full ;
67
+ wire pkt_store_ren ;
68
+ wire [1 + `DMA_KEEP_W + 8 + `DMA_DATA_W-1:0] pkt_store_tdata;
69
+ wire pkt_store_empty;
70
+
71
+ reg [4:0] pkt_cnt; //
72
+ /* -------tmp store the whole rq pkt{begin}------- */
73
+
74
+ /* -------dma --> pcie interface, pcie part{begin}------- */
75
+ // Requester request
76
+ /* RQ tuser
77
+ * | 59:28 | 27:24 | 23:16 | 15 | 14:13 | 12 | 11 | 10:8 | 7:4 | 3:0 |
78
+ * | parity | seq_num | tph_st_tag | tph_indirect_tag_en | tph_type | tph_present | discontinue | addr_offset | last_be | first_be |
79
+ * | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | |
80
+ */
81
+ wire pcie_axis_rq_tvalid;
82
+ wire pcie_axis_rq_tlast ;
83
+ wire [`DMA_DATA_W-1:0] pcie_axis_rq_tdata ;
84
+ wire [59 :0] pcie_axis_rq_tuser ;
85
+ wire [`DMA_KEEP_W-1:0] pcie_axis_rq_tkeep ;
86
+ wire pcie_axis_rq_tready;
87
+ /* -------dma --> pcie interface, pcie part{begin}------- */
88
+
89
+ `ifdef PCIEI_APB_DBG
90
+ /* -------APB reated signal{begin}------- */
91
+ wire [1:0] rtsel;
92
+ wire [1:0] wtsel;
93
+ wire [1:0] ptsel;
94
+ wire vg ;
95
+ wire vs ;
96
+ /* -------APB reated signal{end}------- */
97
+ `endif
98
+
99
+ //---------------------------------------------------------------------------------------------------------------------------
100
+
101
+ `ifdef PCIEI_APB_DBG
102
+ /* -------APB reated signal{begin}------- */
103
+ assign {rtsel, wtsel, ptsel, vg, vs} = rw_data;
104
+
105
+ assign dbg_signal = { // 885
106
+ dma_axis_rq_full, // 1
107
+ fifo_out_ren, fifo_out_tdata, fifo_out_empty, // 275
108
+ pkt_store_wen, pkt_store_full, pkt_store_ren, pkt_store_tdata, pkt_store_empty, // 277
109
+ pkt_cnt, // 5
110
+ pcie_axis_rq_tvalid, pcie_axis_rq_tlast , pcie_axis_rq_tdata , pcie_axis_rq_tuser , pcie_axis_rq_tkeep , pcie_axis_rq_tready // 327
111
+ };
112
+ /* -------APB reated signal{end}------- */
113
+ `endif
114
+
115
+ pcieifc_async_fifo #(
116
+ .DATA_WIDTH ( 1 + `DMA_KEEP_W + 8 + `DMA_DATA_W ),
117
+ .ADDR_WIDTH ( 4 )
118
+ ) pcieifc_async_fifo (
119
+ .wr_clk ( dma_clk ), // i, 1
120
+ .rd_clk ( pcie_clk ), // i, 1
121
+ .wrst_n ( dma_rst_n ), // i, 1
122
+ .rrst_n ( pcie_rst_n ), // i, 1
123
+
124
+ .wen ( dma_axis_rq_tvalid & dma_axis_rq_tready ), // i, 1
125
+ .din ( {dma_axis_rq_tlast, dma_axis_rq_tkeep, dma_axis_rq_tuser[7:0], dma_axis_rq_tdata} ), // i, (`DMA_KEEP_W + 8 + 1 + `DMA_DATA_W)
126
+ .full ( dma_axis_rq_full ), // o, 1
127
+
128
+ .ren ( fifo_out_ren ), // i, 1
129
+ .dout ( fifo_out_tdata ), // o, (1 + `DMA_KEEP_W + 8 + `DMA_DATA_W)
130
+ .empty ( fifo_out_empty ) // o, 1
131
+
132
+ `ifdef PCIEI_APB_DBG
133
+ ,.rtsel ( rtsel ) // i, 2
134
+ ,.wtsel ( wtsel ) // i, 2
135
+ ,.ptsel ( ptsel ) // i, 2
136
+ ,.vg ( vg ) // i, 1
137
+ ,.vs ( vs ) // i, 1
138
+ `endif
139
+ );
140
+ assign dma_axis_rq_tready = !dma_axis_rq_full;
141
+
142
+ /* --------tmp store the whole rq pkt{begin}------- */
143
+ assign fifo_out_ren = !pkt_store_full;
144
+ assign pkt_store_wen = !fifo_out_empty & !pkt_store_full;
145
+ pcieifc_sync_fifo #(
146
+ .DSIZE ( 1 + `DMA_KEEP_W + 8 + `DMA_DATA_W ), // 1 + 8 + 8 + 256 = 273
147
+ .ASIZE ( 4 ) // 16 depth
148
+ ) pkt_store_fifo (
149
+
150
+ .clk ( pcie_clk ), // i, i
151
+ .rst_n ( pcie_rst_n ), // i, i
152
+ .clr ( 1'd0 ), // i, 1
153
+
154
+ .wen ( pkt_store_wen ), // i, 1
155
+ .din ( fifo_out_tdata ), // i, 1 + `DMA_KEEP_W + 8 + `DMA_DATA_W
156
+ .full ( pkt_store_full ), // o, 1
157
+
158
+ .ren ( pkt_store_ren ), // i, 1
159
+ .dout ( pkt_store_tdata ), // o, 1 + `DMA_KEEP_W + 8 + `DMA_DATA_W
160
+ .empty( pkt_store_empty ) // o, 1
161
+
162
+ `ifdef PCIEI_APB_DBG
163
+ ,.rtsel ( 2'b0 ) // i, 2
164
+ ,.wtsel ( 2'b0 ) // i, 2
165
+ ,.ptsel ( 2'b0 ) // i, 2
166
+ ,.vg ( 1'b0 ) // i, 1
167
+ ,.vs ( 1'b0 ) // i, 1
168
+ `endif
169
+ );
170
+
171
+ always @(posedge pcie_clk, negedge pcie_rst_n) begin
172
+ if (~pcie_rst_n) begin
173
+ pkt_cnt <= `TD 5'd0;
174
+ end
175
+ else if (pkt_store_tdata[272] & pkt_store_ren & fifo_out_tdata[272] & pkt_store_wen) begin
176
+ pkt_cnt <= `TD pkt_cnt;
177
+ end
178
+ else if (pkt_store_tdata[272] & pkt_store_ren) begin
179
+ pkt_cnt <= `TD pkt_cnt - 5'd1;
180
+ end
181
+ else if (fifo_out_tdata[272] & pkt_store_wen) begin
182
+ pkt_cnt <= `TD pkt_cnt + 5'd1;
183
+ end
184
+ end
185
+
186
+ assign pcie_axis_rq_tvalid = !pkt_store_empty & (pkt_cnt > 0);
187
+ assign pcie_axis_rq_tlast = pcie_axis_rq_tvalid ? pkt_store_tdata[272] : 1'd0;
188
+ assign pcie_axis_rq_tdata = pcie_axis_rq_tvalid ? pkt_store_tdata[255:0] : 256'd0;
189
+ assign pcie_axis_rq_tuser = {52'd0, pkt_store_tdata[263:256]};
190
+ assign pcie_axis_rq_tkeep = pcie_axis_rq_tvalid ? pkt_store_tdata[271:264] : 8'd0;
191
+
192
+ assign pkt_store_ren = pcie_axis_rq_tvalid & pcie_axis_rq_tready;
193
+ /* --------tmp store the whole rq pkt{end}------- */
194
+
195
+ /* -------Read Request FIFO{begin}------- */
196
+ st_reg #(
197
+ .TUSER_WIDTH ( 60 ),
198
+ .TDATA_WIDTH ( `DMA_DATA_W + `DMA_KEEP_W )
199
+ ) st_rq (
200
+ .clk ( pcie_clk ), // i, 1
201
+ .rst_n ( pcie_rst_n ), // i, 1
202
+
203
+ /* -------input axis-like interface{begin}------- */
204
+ .axis_tvalid ( pcie_axis_rq_tvalid ), // i, 1
205
+ .axis_tlast ( pcie_axis_rq_tlast ), // i, 1
206
+ .axis_tuser ( pcie_axis_rq_tuser ), // i, TUSER_WIDTH
207
+ .axis_tdata ( {pcie_axis_rq_tdata, pcie_axis_rq_tkeep} ), // i, TDATA_WIDTH
208
+ .axis_tready ( pcie_axis_rq_tready ), // o, 1
209
+ /* -------input axis-like interface{end}------- */
210
+
211
+ /* -------output in_reg inteface{begin}------- */
212
+ .axis_reg_tvalid ( st_pcie_axis_rq_tvalid ), // o, 1
213
+ .axis_reg_tlast ( st_pcie_axis_rq_tlast ), // o, 1
214
+ .axis_reg_tuser ( st_pcie_axis_rq_tuser ), // o, TUSER_WIDTH
215
+ .axis_reg_tdata ( {st_pcie_axis_rq_tdata, st_pcie_axis_rq_tkeep} ), // o, TDATA_WIDTH
216
+ .axis_reg_tready ( st_pcie_axis_rq_tready ) //` i, 1
217
+ /* -------output in_reg inteface{end}------- */
218
+ );
219
+ /* -------Read Request FIFO{end}------- */
220
+
221
+ endmodule
ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/DMA/rrsp_async_fifo.v ADDED
@@ -0,0 +1,142 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ `timescale 1ns / 100ps
2
+ //*************************************************************************
3
+ // > File Name: rrsp_async_fifos.v
4
+ // > Author : Kangning
5
+ // > Date : 2023-04-23
6
+ // > Note : rrsp_async_fifos, used to separate rdma and pcie clock domain,
7
+ // > in RC (Requester Completion Channel).
8
+ //*************************************************************************
9
+
10
+ //`include "../lib/global_include_h.v"
11
+
12
+ module rrsp_async_fifos #(
13
+
14
+ ) (
15
+ input wire dma_clk ,
16
+ input wire pcie_clk ,
17
+ input wire dma_rst_n ,
18
+ input wire pcie_rst_n,
19
+
20
+ /* ------- pcie clock domain{begin}------- */
21
+ /* AXI-Stream read response tuser, interact with read response distributor.
22
+ * Only valid in first beat of a packet
23
+ * | Reserved | REQ CPL | Tag | address | Reserved | DW length | first BE | last BE |
24
+ * | 119:105 | 104 | 103:96 | 95:32 | 31:19 | 18:8 | 7:4 | 3:0 |
25
+ */
26
+ input wire pcie_axis_rrsp_tvalid, // i, 1
27
+ input wire pcie_axis_rrsp_tlast , // i, 1
28
+ input wire [`DMA_DATA_W -1:0] pcie_axis_rrsp_tdata , // i, `DMA_DATA_W
29
+ input wire [`AXIS_TUSER_W-1:0] pcie_axis_rrsp_tuser , // i, `AXIS_TUSER_W
30
+ input wire [`DMA_KEEP_W -1:0] pcie_axis_rrsp_tkeep , // i, `DMA_KEEP_W
31
+ output wire pcie_axis_rrsp_tready, // o, 1
32
+ /* ------- pcie clock domain{end}------- */
33
+
34
+ /* ------- dma clock domain{begin}------- */
35
+ /* AXI-Stream read response tuser, interact with read response distributor.
36
+ * Only valid in first beat of a packet
37
+ * | Reserved | REQ CPL | Tag | address | Reserved | DW length | first BE | last BE |
38
+ * | 119:105 | 104 | 103:96 | 95:32 | 31:19 | 18:8 | 7:4 | 3:0 |
39
+ */
40
+ output wire dma_axis_rrsp_tvalid, // o, 1
41
+ output wire dma_axis_rrsp_tlast , // o, 1
42
+ output wire [`DMA_DATA_W -1:0] dma_axis_rrsp_tdata , // o, `DMA_DATA_W
43
+ output wire [`AXIS_TUSER_W-1:0] dma_axis_rrsp_tuser , // o, `AXIS_TUSER_W
44
+ output wire [`DMA_KEEP_W -1:0] dma_axis_rrsp_tkeep , // o, `DMA_KEEP_W
45
+ input wire dma_axis_rrsp_tready // i, 1
46
+ /* ------- dma clock domain{end}------- */
47
+
48
+ `ifdef PCIEI_APB_DBG
49
+ /* -------APB reated signal{begin}------- */
50
+ ,input wire [`SRAM_RW_DATA_W -1:0] rw_data // i, `SRAM_RW_DATA_W
51
+ ,output wire [`RRSP_ASYNC_SIGNAL_W-1:0] dbg_signal // o, `RRSP_ASYNC_SIGNAL_W
52
+ /* -------APB reated signal{end}------- */
53
+ `endif
54
+ );
55
+ wire pcie_axis_rrsp_full, dma_axis_rrsp_empty;
56
+
57
+
58
+ // | addr | last | keep | tag | req_cpl | dw_len | first BE | last BE |
59
+ // | 12 bit | 1 bit| 8 bit | 8 bit | 1 bit | 11 bit | 4 bit | 4 bit |
60
+ // | 48:37 | 36 | 35:28 | 27:20 | 19 | 18:8 | 7 : 4 | 3 : 0 |
61
+ wire [40:0] pcie_header, dma_header;
62
+
63
+ `ifdef PCIEI_APB_DBG
64
+ /* -------APB reated signal{begin}------- */
65
+ wire [1:0] rtsel;
66
+ wire [1:0] wtsel;
67
+ wire [1:0] ptsel;
68
+ wire vg ;
69
+ wire vs ;
70
+ /* -------APB reated signal{end}------- */
71
+ `endif
72
+
73
+ //---------------------------------------------------------------------------------------------------------------------------
74
+
75
+ `ifdef PCIEI_APB_DBG
76
+ /* -------APB reated signal{begin}------- */
77
+ assign {rtsel, wtsel, ptsel, vg, vs} = rw_data;
78
+ assign dbg_signal = { // 84
79
+ pcie_axis_rrsp_full, dma_axis_rrsp_empty,
80
+ dma_header,
81
+ pcie_header
82
+ };
83
+ /* -------APB reated signal{end}------- */
84
+ `endif
85
+
86
+ assign pcie_header = { pcie_axis_rrsp_tuser[35:32], // addr, 4 bit
87
+ pcie_axis_rrsp_tlast,
88
+ pcie_axis_rrsp_tkeep,
89
+ pcie_axis_rrsp_tuser[103:96], // tag,, 8 bit
90
+ pcie_axis_rrsp_tuser[104], // req cpl, 1 bit
91
+ pcie_axis_rrsp_tuser[18:0]};
92
+
93
+ pcieifc_async_fifo #(
94
+ .DATA_WIDTH ( (41 + `DMA_DATA_W) ),
95
+ .ADDR_WIDTH ( 4 )
96
+ ) pcieifc_async_fifo (
97
+ .wr_clk ( pcie_clk ), // i, 1
98
+ .rd_clk ( dma_clk ), // i, 1
99
+ .wrst_n ( pcie_rst_n ), // i, 1
100
+ .rrst_n ( dma_rst_n ), // i, 1
101
+
102
+ .wen ( pcie_axis_rrsp_tvalid & pcie_axis_rrsp_tready ), // i, 1
103
+ .din ( {pcie_header, pcie_axis_rrsp_tdata} ), // i, (1 + `DMA_KEEP_W + 32 + `DMA_DATA_W)
104
+ .full ( pcie_axis_rrsp_full ), // o, 1
105
+
106
+ .ren ( dma_axis_rrsp_tvalid & dma_axis_rrsp_tready ), // i, 1
107
+ .dout ( {dma_header, dma_axis_rrsp_tdata} ), // o, (1 + `DMA_KEEP_W + 32 + `DMA_DATA_W)
108
+ .empty ( dma_axis_rrsp_empty ) // o, 1
109
+
110
+ `ifdef PCIEI_APB_DBG
111
+ ,.rtsel ( rtsel ) // i, 2
112
+ ,.wtsel ( wtsel ) // i, 2
113
+ ,.ptsel ( ptsel ) // i, 2
114
+ ,.vg ( vg ) // i, 1
115
+ ,.vs ( vs ) // i, 1
116
+ `endif
117
+ );
118
+
119
+ assign pcie_axis_rrsp_tready = !pcie_axis_rrsp_full;
120
+ assign dma_axis_rrsp_tvalid = !dma_axis_rrsp_empty;
121
+
122
+
123
+ // | addr | last | keep | tag | req_cpl | dw_len | first BE | last BE |
124
+ // | 12 bit | 1 bit| 8 bit | 8 bit | 1 bit | 11 bit | 4 bit | 4 bit |
125
+ // | 48:37 | 36 | 35:28 | 27:20 | 19 | 18:8 | 7 : 4 | 3 : 0 |
126
+ assign dma_axis_rrsp_tkeep = dma_header[35:28];
127
+ assign dma_axis_rrsp_tlast = dma_header[36];
128
+
129
+
130
+ /* AXI-Stream read response tuser, interact with read response distributor.
131
+ * Only valid in first beat of a packet
132
+ * | Reserved | REQ CPL | Tag | address | Reserved | DW length | first BE | last BE |
133
+ * | 119:105 | 104 | 103:96 | 95:32 | 31:19 | 18:8 | 7:4 | 3:0 |
134
+ */
135
+ assign dma_axis_rrsp_tuser = {
136
+ 24'd0,
137
+ dma_header[19],
138
+ dma_header[27:20],
139
+ 32'd0, 28'd0, dma_header[40:37], // addr, 64 bit
140
+ 13'd0, dma_header[18:0]};
141
+
142
+ endmodule
ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/DMA/rsp_converter.v ADDED
@@ -0,0 +1,300 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ `timescale 1ns / 100ps
2
+ //*************************************************************************
3
+ // > File Name: rsp_converter.v
4
+ // > Author : Kangning
5
+ // > Date : 2020-08-25
6
+ // > Note : rsp_converter, used to convert Xilinx PCIe compatible
7
+ // > interface into AXI-Stream
8
+ //*************************************************************************
9
+
10
+ //`include "../lib/global_include_h.v"
11
+ //`include "../lib/dma_def_h.v"
12
+
13
+ module rsp_converter #(
14
+
15
+ ) (
16
+ input wire dma_clk ,
17
+ input wire rst_n ,
18
+
19
+ /* ------- pcie --> dma interface{begin}------- */
20
+ // Requester Completion
21
+ /* RC tuser
22
+ * | 74:43 | 42 | 41:38 | 37:34 | 33 | 32 | 31:0 |
23
+ * | parity | discontinue | is_eof_1 | is_eof_0 | is_sof_1 | is_sof_0 | byte_en |
24
+ * | ignore | ignore | ignore | ignore | ignore | ignore | |
25
+ */
26
+ input wire m_axis_rc_tvalid, // i, 1
27
+ input wire m_axis_rc_tlast , // i, 1
28
+ input wire [`DMA_DATA_W-1:0] m_axis_rc_tdata , // i, `DMA_DATA_W
29
+ input wire [74 :0] m_axis_rc_tuser , // i, 75
30
+ input wire [`DMA_KEEP_W-1:0] m_axis_rc_tkeep , // i, `DMA_KEEP_W
31
+ output wire m_axis_rc_tready, // o, 1
32
+ /* ------- pcie --> dma interface{end}------- */
33
+
34
+
35
+ /* ------- Interface with dma read module{begin}------- */
36
+ /* AXI-Stream read response tuser, interact with read response distributor.
37
+ * Only valid in first beat of a packet
38
+ * | Reserved | REQ CPL | Tag | address | Reserved | DW length | first BE | last BE |
39
+ * | 119:105 | 104 | 103:96 | 95:32 | 31:19 | 18:8 | 7:4 | 3:0 |
40
+ */
41
+ output wire axis_rd_rsp_tvalid, // o, 1
42
+ output wire axis_rd_rsp_tlast , // o, 1
43
+ output wire [`DMA_DATA_W -1:0] axis_rd_rsp_tdata , // o, `DMA_DATA_W
44
+ output wire [`AXIS_TUSER_W-1:0] axis_rd_rsp_tuser , // o, `AXIS_TUSER_W
45
+ output wire [`DMA_KEEP_W -1:0] axis_rd_rsp_tkeep , // o, `DMA_KEEP_W
46
+ input wire axis_rd_rsp_tready // i, 1
47
+ /* ------- Interface with dma read module{end}------- */
48
+
49
+ `ifdef PCIEI_APB_DBG
50
+ /* -------APB reated signal{begin}------- */
51
+ ,input wire [31:0] dbg_sel // i, 32
52
+ ,output wire [31:0] dbg_bus // o, 32
53
+ /* -------APB reated signal{end}------- */
54
+ `endif
55
+ );
56
+
57
+ // Generate last signal of m_axis_rc_tlast, cause it doesn't work in FPGA V7 series
58
+ /* -------last generate {begin}------- */
59
+ // reg [`DW_LEN_WIDTH-1:0] dw_left;
60
+ /* -------last generate {end}------- */
61
+
62
+ /* -------axis_dw_left{begin}------- */
63
+ wire axis_next_last; // indicate that next cycle is axis_rd_rsp_last
64
+ wire [`DMA_KEEP_W -1:0] axis_keep ;
65
+ reg [`DW_LEN_WIDTH-1:0] axis_dw_left ;
66
+ /* -------axis_dw_last{end}------- */
67
+
68
+ /* -------tuser generation{begin}------- */
69
+ wire [1 :0] last_dw;
70
+
71
+ wire is_req_cpl;
72
+ wire [`TAG_WIDTH+`TAG_EMPTY-1:0] tag ;
73
+ wire [`DMA_ADDR_WIDTH -1:0] addr ;
74
+ wire [`DW_LEN_WIDTH -1:0] dw_len ;
75
+ wire [`FIRST_BE_WIDTH -1:0] first_be;
76
+ wire [`LAST_BE_WIDTH -1:0] last_be ;
77
+
78
+ wire [`DW_LEN_WIDTH :0] total_dw;
79
+
80
+ reg is_aligned_last;
81
+ reg [`AXIS_TUSER_W-1:0] axis_tuser; // tuser signal output in RX_IDLE state
82
+ /* -------tuser generation{end}------- */
83
+
84
+ /* -------data generation{begin}------- */
85
+
86
+ reg [159:0] tmp_reg_data;
87
+
88
+ wire [`DMA_DATA_W-1:0] axis_tdata_rsp ;
89
+ wire [`DMA_DATA_W-1:0] axis_tdata_last;
90
+ /* -------data generation{end}------- */
91
+
92
+ /* -------State relevant in FSM{begin}------- */
93
+ localparam RX_IDLE = 3'b001, // This State is used to generate tuser for other stage use,
94
+ // this state do not output, but input one beat. When input vld & rdy
95
+ // asserted at the same time (one beat data in), jump to RX_RSP;
96
+ // and if this beat is last beat, jump to RX_LAST state.
97
+ RX_RSP = 3'b010, // This state is used to output & input data, when it is last beat and
98
+ // there's data in temp register, jump to RX_LAST state.
99
+ RX_LAST = 3'b100; // Output data in temp, and jump to RX_IDLE state. Note that this state
100
+ // don't assert ready.
101
+
102
+ reg [2:0] cur_state;
103
+ reg [2:0] nxt_state;
104
+
105
+ wire is_rx_idle, is_rx_rsp, is_rx_last;
106
+ /* -------State relevant in FSM{end}------- */
107
+
108
+ `ifdef PCIEI_APB_DBG
109
+ /* -------APB reated signal{begin}------- */
110
+ wire [`RSP_CONVERT_TOP_SIGNAL_W-1:0] dbg_signal;
111
+ /* -------APB reated signal{end}------- */
112
+ `endif
113
+
114
+ //---------------------------------------------------------------------------------------------------------------------------
115
+
116
+ `ifdef PCIEI_APB_DBG
117
+ /* -------APB reated signal{begin}------- */
118
+ assign dbg_bus = dbg_signal >> {dbg_sel, 5'd0};
119
+
120
+ assign dbg_signal = { // 936
121
+ axis_next_last, axis_keep, axis_dw_left, // 20
122
+ last_dw, // 2
123
+ is_req_cpl, tag, addr, dw_len, first_be, last_be, // 92
124
+ total_dw, // 12
125
+ is_aligned_last, // 1
126
+ axis_tuser, // 128
127
+ tmp_reg_data, // 160
128
+ axis_tdata_rsp, axis_tdata_last, // 512
129
+ cur_state, nxt_state, // 6
130
+ is_rx_idle, is_rx_rsp, is_rx_last // 3
131
+ };
132
+ /* -------APB reated signal{end}------- */
133
+ `endif
134
+
135
+ /* -------axis_dw_left{begin}------- */
136
+ assign axis_next_last = ( is_rx_rsp & ((8 < axis_dw_left) & (axis_dw_left <= 16))) |
137
+ ( is_rx_idle & (dw_len <= 8)) |
138
+ ((is_rx_last & m_axis_rc_tvalid & m_axis_rc_tready) & (dw_len <= 8));
139
+ always @(posedge dma_clk, negedge rst_n) begin
140
+ if (~rst_n) begin
141
+ axis_dw_left <= `TD 0;
142
+ end
143
+ else if ((is_rx_idle & m_axis_rc_tvalid & m_axis_rc_tready) |
144
+ (is_rx_last & m_axis_rc_tvalid & m_axis_rc_tready & !is_aligned_last)) begin
145
+ axis_dw_left <= `TD dw_len;
146
+ end
147
+ else if (axis_rd_rsp_tvalid & axis_rd_rsp_tready) begin
148
+ axis_dw_left <= `TD axis_dw_left - 8;
149
+ end
150
+ end
151
+ assign axis_keep = ({`DMA_KEEP_W{axis_dw_left >= 8}} & 8'hFF) |
152
+ ({`DMA_KEEP_W{axis_dw_left == 7}} & 8'h7F) |
153
+ ({`DMA_KEEP_W{axis_dw_left == 6}} & 8'h3F) |
154
+ ({`DMA_KEEP_W{axis_dw_left == 5}} & 8'h1F) |
155
+ ({`DMA_KEEP_W{axis_dw_left == 4}} & 8'h0F) |
156
+ ({`DMA_KEEP_W{axis_dw_left == 3}} & 8'h07) |
157
+ ({`DMA_KEEP_W{axis_dw_left == 2}} & 8'h03) |
158
+ ({`DMA_KEEP_W{axis_dw_left == 1}} & 8'h01);
159
+ /* -------axis_dw_left{end}------- */
160
+
161
+ /* -------tuser generation{begin}------- */
162
+ assign last_dw = m_axis_rc_tdata[17:16] + m_axis_rc_tdata[1:0];
163
+
164
+ assign is_req_cpl = m_axis_rc_tdata[30];
165
+ assign tag = m_axis_rc_tdata[71:64];
166
+ assign addr = {52'd0, m_axis_rc_tdata[11:2], 2'd0};
167
+ assign dw_len = m_axis_rc_tdata[42:32];
168
+ assign first_be = ({4{m_axis_rc_tdata[1:0] == 2'b00}} & 4'b1111) |
169
+ ({4{m_axis_rc_tdata[1:0] == 2'b01}} & 4'b1110) |
170
+ ({4{m_axis_rc_tdata[1:0] == 2'b10}} & 4'b1100) |
171
+ ({4{m_axis_rc_tdata[1:0] == 2'b11}} & 4'b1000);
172
+ assign last_be = m_axis_rc_tdata[30] ?
173
+ (({4{last_dw == 2'b00}} & 4'b1111) |
174
+ ({4{last_dw == 2'b01}} & 4'b0001) |
175
+ ({4{last_dw == 2'b10}} & 4'b0011) |
176
+ ({4{last_dw == 2'b11}} & 4'b0111)) : 4'b1111;
177
+
178
+ assign total_dw = dw_len + 3;
179
+ always @(posedge dma_clk, negedge rst_n) begin
180
+ if (~rst_n) begin
181
+ axis_tuser <= `TD {`AXIS_TUSER_W{1'd0}};
182
+ is_aligned_last <= `TD 0;
183
+ end
184
+ else if ((is_rx_idle & m_axis_rc_tvalid & m_axis_rc_tready) || // jump from idle to RX_RSP || RX_LAST
185
+ (is_rx_last & m_axis_rc_tvalid & m_axis_rc_tready & !is_aligned_last)) begin // jump from RX_LAST to RX_RSP || RX_LAST
186
+ axis_tuser <= `TD {23'd0, is_req_cpl, tag, addr, 13'd0, dw_len,
187
+ (dw_len == 1) ? (first_be & last_be) : first_be,
188
+ (dw_len == 1) ? 4'b0000 : last_be};
189
+ is_aligned_last <= `TD ((0 == dw_len[2:0]) || (dw_len[2:0] >= 6));
190
+ end
191
+ else if (is_rx_last & m_axis_rc_tvalid & m_axis_rc_tready & is_aligned_last) begin
192
+ axis_tuser <= `TD {`AXIS_TUSER_W{1'd0}};
193
+ is_aligned_last <= `TD 0;
194
+ end
195
+ end
196
+ /* -------tuser generation{end}------- */
197
+
198
+ /* -------data & keep generation{begin}------- */
199
+ always @(posedge dma_clk, negedge rst_n) begin
200
+ if (~rst_n) begin
201
+ tmp_reg_data <= `TD 160'd0;
202
+ end
203
+ else if ((is_rx_last & axis_rd_rsp_tready & is_aligned_last) & (m_axis_rc_tvalid & m_axis_rc_tready)) begin
204
+ tmp_reg_data <= `TD 160'd0;
205
+ end
206
+ else if ((is_rx_last & axis_rd_rsp_tready & !is_aligned_last) & (m_axis_rc_tvalid & m_axis_rc_tready)) begin
207
+ tmp_reg_data <= `TD m_axis_rc_tdata[255:96];
208
+ end
209
+ else if (is_rx_last & axis_rd_rsp_tready & !is_aligned_last) begin
210
+ tmp_reg_data <= `TD 160'd0;
211
+ end
212
+ else if (m_axis_rc_tvalid & m_axis_rc_tready) begin
213
+ tmp_reg_data <= `TD m_axis_rc_tdata[255:96];
214
+ end
215
+ end
216
+
217
+
218
+ assign axis_tdata_rsp = {m_axis_rc_tdata[95:0], tmp_reg_data};
219
+ assign axis_tdata_last = {96'd0, tmp_reg_data};
220
+ /* -------data & keep generation{end}------- */
221
+
222
+
223
+ /* -------{RSP converter FSM}begin------- */
224
+ /******************** Stage 1: State Register **********************/
225
+
226
+ assign is_rx_idle = (cur_state == RX_IDLE);
227
+ assign is_rx_rsp = (cur_state == RX_RSP );
228
+ assign is_rx_last = (cur_state == RX_LAST);
229
+
230
+ always @(posedge dma_clk, negedge rst_n) begin
231
+ if(~rst_n)
232
+ cur_state <= `TD RX_IDLE;
233
+ else
234
+ cur_state <= `TD nxt_state;
235
+ end
236
+
237
+ /******************** Stage 2: State Transition **********************/
238
+
239
+ always @(*) begin
240
+ case(cur_state)
241
+ RX_IDLE: begin
242
+ if (m_axis_rc_tvalid & m_axis_rc_tready & axis_next_last) begin
243
+ nxt_state = RX_LAST;
244
+ end
245
+ else if (m_axis_rc_tvalid & m_axis_rc_tready & !axis_next_last) begin
246
+ nxt_state = RX_RSP;
247
+ end
248
+ else begin
249
+ nxt_state = RX_IDLE;
250
+ end
251
+ end
252
+ RX_RSP: begin
253
+ if (m_axis_rc_tvalid & m_axis_rc_tready & axis_next_last) begin
254
+ nxt_state = RX_LAST;
255
+ end
256
+ else begin
257
+ nxt_state = RX_RSP;
258
+ end
259
+ end
260
+ RX_LAST: begin
261
+ if (axis_rd_rsp_tvalid & axis_rd_rsp_tready) begin
262
+ if (m_axis_rc_tvalid & m_axis_rc_tready & is_aligned_last) begin // prevsious pkt hasn't finished yet.
263
+ nxt_state = RX_IDLE;
264
+ end
265
+ else if (m_axis_rc_tvalid & m_axis_rc_tready & axis_next_last) begin
266
+ nxt_state = RX_LAST;
267
+ end
268
+ else if (m_axis_rc_tvalid & m_axis_rc_tready & !axis_next_last) begin
269
+ nxt_state = RX_RSP;
270
+ end
271
+ else begin
272
+ nxt_state = RX_IDLE;
273
+ end
274
+ end
275
+ else begin
276
+ nxt_state = RX_LAST;
277
+ end
278
+ end
279
+ default: begin
280
+ nxt_state = RX_IDLE;
281
+ end
282
+ endcase
283
+ end
284
+
285
+
286
+ /******************** Stage 3: Output **********************/
287
+
288
+ assign m_axis_rc_tready = is_rx_idle | ((is_rx_rsp | is_rx_last) & axis_rd_rsp_tready);
289
+
290
+ assign axis_rd_rsp_tvalid = (is_rx_rsp & m_axis_rc_tvalid) | (is_rx_last & is_aligned_last & m_axis_rc_tvalid) | (is_rx_last & !is_aligned_last);
291
+ assign axis_rd_rsp_tlast = axis_rd_rsp_tvalid & is_rx_last;
292
+ assign axis_rd_rsp_tuser = axis_rd_rsp_tvalid ? axis_tuser : 0;
293
+ assign axis_rd_rsp_tdata = ({`DMA_DATA_W{is_rx_rsp }} & axis_tdata_rsp ) |
294
+ ({`DMA_DATA_W{is_rx_last & is_aligned_last}} & axis_tdata_rsp ) |
295
+ ({`DMA_DATA_W{is_rx_last & !is_aligned_last}} & axis_tdata_last);
296
+ assign axis_rd_rsp_tkeep = axis_keep;
297
+
298
+ /* -------{RSP converter FSM}end------- */
299
+
300
+ endmodule
ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/P2P/P2P.v ADDED
@@ -0,0 +1,349 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ `timescale 1ns / 100ps
2
+ //*************************************************************************
3
+ // > File : P2P.v
4
+ // > Author : Kangning
5
+ // > Date : 2022-06-10
6
+ // > Note : DMA P2P initiator and target
7
+ //*************************************************************************
8
+
9
+ module P2P #(
10
+
11
+ ) (
12
+ input wire clk , // i, 1
13
+ input wire rst_n , // i, 1
14
+ output wire init_done, // o, 1
15
+
16
+ /* --------P2P Configuration Channel{begin}-------- */
17
+ /* p2p_req head
18
+ * | 127 | 126:64 | 63:32 | 31:13 | 12:0 |
19
+ * | is_wr | Reserved | addr | Reserved | byte_len |
20
+ */
21
+ input wire [1 - 1 : 0] p2p_cfg_req_valid, // i, 1
22
+ input wire [1 - 1 : 0] p2p_cfg_req_last , // i, 1
23
+ input wire [`P2P_HEAD_W - 1 : 0] p2p_cfg_req_head , // i, `P2P_HEAD_W
24
+ input wire [`P2P_DATA_W - 1 : 0] p2p_cfg_req_data , // i, `P2P_DATA_W
25
+ output wire [1 - 1 : 0] p2p_cfg_req_ready, // o, 1
26
+
27
+ output wire [1 - 1 : 0] p2p_cfg_rrsp_valid, // o, 1
28
+ output wire [1 - 1 : 0] p2p_cfg_rrsp_last , // o, 1
29
+ output wire [`P2P_DATA_W - 1 : 0] p2p_cfg_rrsp_data , // o, `P2P_DATA_W
30
+ input wire [1 - 1 : 0] p2p_cfg_rrsp_ready, // i, 1
31
+ /* --------P2P Configuration Channel{end}-------- */
32
+
33
+ /* -------P2P Memory Access Channel{begin}-------- */
34
+ /* p2p_req head
35
+ * | 127 | 126:64 | 63:32 | 31:13 | 12:0 |
36
+ * | is_wr | Reserved | addr | Reserved | byte_len |
37
+ */
38
+ input wire [1 - 1 : 0] p2p_mem_req_valid, // i, 1
39
+ input wire [1 - 1 : 0] p2p_mem_req_last , // i, 1
40
+ input wire [`P2P_HEAD_W - 1 : 0] p2p_mem_req_head , // i, `P2P_HEAD_W
41
+ input wire [`P2P_DATA_W - 1 : 0] p2p_mem_req_data , // i, `P2P_DATA_W
42
+ output wire [1 - 1 : 0] p2p_mem_req_ready, // , 1
43
+ /* -------P2P Memory Access Channel{end}-------- */
44
+
45
+ /* --------P2P DMA Write Req{begin}-------- */
46
+ /* dma_*_head, valid only in first beat of a packet
47
+ * | Reserved | address | Reserved | Byte length |
48
+ * | 127:96 | 95:32 | 31:13 | 12:0 |
49
+ */
50
+ output wire [1 - 1 : 0] p2p_dma_wr_req_valid, // o, 1
51
+ output wire [1 - 1 : 0] p2p_dma_wr_req_last , // o, 1
52
+ output wire [`DMA_HEAD_W - 1 : 0] p2p_dma_wr_req_head , // o, `DMA_HEAD_W
53
+ output wire [`P2P_DATA_W - 1 : 0] p2p_dma_wr_req_data , // o, `P2P_DATA_W
54
+ input wire [1 - 1 : 0] p2p_dma_wr_req_ready, // i, 1
55
+ /* --------P2P DMA Write Req{end}-------- */
56
+
57
+ /* --------p2p forward up channel{begin}-------- */
58
+ /* *_head, valid only in first beat of a packet
59
+ * | Reserved |dst_dev| src_dev | Reserved | Byte length |
60
+ * | 63:- | 47:40 | 39:32 | 31:16 | 15:0 |
61
+ */
62
+ input wire [1 - 1 : 0] p2p_upper_valid, // i, 1
63
+ input wire [1 - 1 : 0] p2p_upper_last , // i, 1
64
+ input wire [`P2P_UHEAD_W - 1 : 0] p2p_upper_head , // i, `P2P_UHEAD_W
65
+ input wire [`P2P_DATA_W - 1 : 0] p2p_upper_data , // i, `P2P_DATA_W
66
+ output wire [1 - 1 : 0] p2p_upper_ready, // o, 1
67
+ /* --------p2p forward up channel{end}-------- */
68
+
69
+ /* --------p2p forward down channel{begin}-------- */
70
+ /* *_head, valid only in first beat of a packet
71
+ * | Reserved |dst_dev| src_dev | Reserved | Byte length |
72
+ * | 63:- | 47:40 | 39:32 | 31:16 | 15:0 |
73
+ */
74
+ output wire [1 - 1 : 0] p2p_down_valid, // o, 1
75
+ output wire [1 - 1 : 0] p2p_down_last , // o, 1
76
+ output wire [`P2P_DHEAD_W - 1 : 0] p2p_down_head , // o, `P2P_DHEAD_W
77
+ output wire [`P2P_DATA_W - 1 : 0] p2p_down_data , // o, `P2P_DATA_W
78
+ input wire [1 - 1 : 0] p2p_down_ready // i, 1
79
+ /* --------p2p forward down channel{end}-------- */
80
+
81
+ `ifdef PCIEI_APB_DBG
82
+ /* -------APB reated signal{begin}------- */
83
+ ,input wire [(2*`QUEUE_NUM+4)*`SRAM_RW_DATA_W-1:0] rw_data // i, (2*`QUEUE_NUM+4)*`SRAM_RW_DATA_W
84
+ ,input wire [31:0] dbg_sel // debug bus select
85
+ ,output wire [31:0] dbg_bus // debug bus data
86
+ /* -------APB reated signal{end}------- */
87
+ `endif
88
+
89
+ );
90
+
91
+ /* --------P2P Configuration Channel{begin}-------- */
92
+ /* p2p_req head
93
+ * | 127 | 126:64 | 63:32 | 31:13 | 12:0 |
94
+ * | is_wr | Reserved | addr | Reserved | byte_len |
95
+ */
96
+ wire [1 - 1 : 0] st_reg_p2p_cfg_req_valid;
97
+ wire [1 - 1 : 0] st_reg_p2p_cfg_req_last ;
98
+ wire [`P2P_HEAD_W - 1 : 0] st_reg_p2p_cfg_req_head ;
99
+ wire [`P2P_DATA_W - 1 : 0] st_reg_p2p_cfg_req_data ;
100
+ wire [1 - 1 : 0] st_reg_p2p_cfg_req_ready;
101
+
102
+ wire [31:0] mem_addr;
103
+ wire [7 :0] nxt_chnl_sel;
104
+ /* --------P2P Configuration Channel{end}-------- */
105
+
106
+ /* --------P2P Configuration Channel{begin}-------- */
107
+ /* p2p_req head
108
+ * | 127 | 126:64 | 63:32 | 31:13 | 12:0 |
109
+ * | is_wr | Reserved | addr | Reserved | byte_len |
110
+ */
111
+ wire [1 - 1 : 0] p2p_tgt_req_valid, p2p_ini_req_valid; // i, 1
112
+ wire [1 - 1 : 0] p2p_tgt_req_last , p2p_ini_req_last ; // i, 1
113
+ wire [`P2P_DATA_W - 1 : 0] p2p_tgt_req_data , p2p_ini_req_data ; // i, `P2P_DATA_W
114
+ wire [`P2P_HEAD_W - 1 : 0] p2p_tgt_req_head , p2p_ini_req_head ; // i, `P2P_HEAD_W
115
+ wire [1 - 1 : 0] p2p_tgt_req_ready, p2p_ini_req_ready; // o, 1
116
+ /* --------P2P Configuration Channel{end}-------- */
117
+
118
+ `ifdef PCIEI_APB_DBG
119
+ /* -------APB reated signal{begin}------- */
120
+ wire [(2*`QUEUE_NUM+3)*`SRAM_RW_DATA_W-1:0] tgt_rw_data;
121
+ wire [`SRAM_RW_DATA_W-1:0] ini_rw_data;
122
+
123
+ wire [31:0] dbg_sel_p2p_top, dbg_sel_ini, dbg_sel_tgt;
124
+ wire [31:0] dbg_bus_p2p_top, dbg_bus_ini, dbg_bus_tgt;
125
+ wire [`P2P_TOP_SIGNAL_W-1:0] dbg_signal_p2p_top;
126
+ /* -------APB reated signal{end}------- */
127
+ `endif
128
+
129
+ //-------------------------------------------------------------------------------------------------------------------
130
+
131
+ `ifdef PCIEI_APB_DBG
132
+ /* -------APB reated signal{begin}------- */
133
+ assign {ini_rw_data, tgt_rw_data} = rw_data;
134
+
135
+ assign dbg_sel_p2p_top = (`P2P_TOP_DBG_B <= dbg_sel && dbg_sel < `INI_DBG_B ) ? (dbg_sel - `P2P_TOP_DBG_B) : 32'd0;
136
+ assign dbg_sel_ini = (`INI_DBG_B <= dbg_sel && dbg_sel < `TGT_DBG_B ) ? (dbg_sel - `INI_DBG_B ) : 32'd0;
137
+ assign dbg_sel_tgt = (`TGT_DBG_B <= dbg_sel && dbg_sel < `P2P_DBG_SIZE ) ? (dbg_sel - `TGT_DBG_B ) : 32'd0;
138
+ assign dbg_bus = (`P2P_TOP_DBG_B <= dbg_sel && dbg_sel < `INI_DBG_B ) ? dbg_bus_p2p_top :
139
+ (`INI_DBG_B <= dbg_sel && dbg_sel < `TGT_DBG_B ) ? dbg_bus_ini :
140
+ (`TGT_DBG_B <= dbg_sel && dbg_sel < `P2P_DBG_SIZE ) ? dbg_bus_tgt : 32'd0;
141
+
142
+ // Debug bus for p2p top
143
+ assign dbg_bus_p2p_top = dbg_signal_p2p_top >> {dbg_sel_p2p_top, 5'd0};
144
+
145
+ // Debug signal for p2p top
146
+ assign dbg_signal_p2p_top = { // 3268
147
+
148
+ init_done, // 1
149
+ p2p_cfg_req_valid, p2p_cfg_req_last , p2p_cfg_req_head , p2p_cfg_req_data , p2p_cfg_req_ready, // 387
150
+ p2p_cfg_rrsp_valid, p2p_cfg_rrsp_last , p2p_cfg_rrsp_data , p2p_cfg_rrsp_ready, // 259
151
+ p2p_mem_req_valid, p2p_mem_req_last , p2p_mem_req_head , p2p_mem_req_data , p2p_mem_req_ready, // 387
152
+ p2p_dma_wr_req_valid, p2p_dma_wr_req_last , p2p_dma_wr_req_head , p2p_dma_wr_req_data , p2p_dma_wr_req_ready, // 387
153
+ p2p_upper_valid, p2p_upper_last , p2p_upper_head , p2p_upper_data , p2p_upper_ready, // 323
154
+ p2p_down_valid, p2p_down_last , p2p_down_head , p2p_down_data , p2p_down_ready, // 323
155
+ st_reg_p2p_cfg_req_valid, st_reg_p2p_cfg_req_last , st_reg_p2p_cfg_req_head , st_reg_p2p_cfg_req_data , st_reg_p2p_cfg_req_ready, // 387
156
+ mem_addr, nxt_chnl_sel, // 40
157
+
158
+ p2p_tgt_req_valid, p2p_ini_req_valid,
159
+ p2p_tgt_req_last , p2p_ini_req_last ,
160
+ p2p_tgt_req_data , p2p_ini_req_data ,
161
+ p2p_tgt_req_head , p2p_ini_req_head ,
162
+ p2p_tgt_req_ready, p2p_ini_req_ready // 774
163
+ };
164
+ /* -------APB reated signal{end}------- */
165
+ `endif
166
+
167
+ /* -------- Related to demux {begin}-------- */
168
+ assign p2p_cfg_rrsp_valid = 0;
169
+ assign p2p_cfg_rrsp_last = 0;
170
+ assign p2p_cfg_rrsp_data = 0;
171
+
172
+ st_reg #(
173
+ .TUSER_WIDTH ( `P2P_HEAD_W ),
174
+ .TDATA_WIDTH ( `P2P_DATA_W ),
175
+ .MODE ( 1 )
176
+ ) st_reg2demux (
177
+ .clk ( clk ), // i, 1
178
+ .rst_n ( rst_n ), // i, 1
179
+
180
+ /* -------input axis-like interface{begin}------- */
181
+ /* p2p_req head
182
+ * | 127 | 126:64 | 63:32 | 31:13 | 12:0 |
183
+ * | is_wr | Reserved | addr | Reserved | byte_len |
184
+ */
185
+ .axis_tvalid ( p2p_cfg_req_valid ), // i, 1
186
+ .axis_tlast ( p2p_cfg_req_last ), // i, 1
187
+ .axis_tuser ( p2p_cfg_req_head ), // i, TUSER_WIDTH
188
+ .axis_tdata ( p2p_cfg_req_data ), // i, TDATA_WIDTH
189
+ .axis_tready ( p2p_cfg_req_ready ), // o, 1
190
+ /* -------input axis-like interface{end}------- */
191
+
192
+ /* -------output in_reg inteface{begin}------- */
193
+ /* p2p_req head
194
+ * | 127 | 126:64 | 63:32 | 31:13 | 12:0 |
195
+ * | is_wr | Reserved | addr | Reserved | byte_len |
196
+ */
197
+ .axis_reg_tvalid ( st_reg_p2p_cfg_req_valid ), // o, 1 // read valid from input register
198
+ .axis_reg_tlast ( st_reg_p2p_cfg_req_last ), // o, 1
199
+ .axis_reg_tuser ( st_reg_p2p_cfg_req_head ), // o, TUSER_WIDTH
200
+ .axis_reg_tdata ( st_reg_p2p_cfg_req_data ), // o, TDATA_WIDTH
201
+ .axis_reg_tready ( st_reg_p2p_cfg_req_ready ) // i, 1
202
+ /* -------output in_reg inteface{end}------- */
203
+ );
204
+
205
+ assign mem_addr = p2p_cfg_req_head[63:32];
206
+ assign nxt_chnl_sel = p2p_cfg_req_valid ? (mem_addr >= `CFG_BAR_TGT_ADDR_BASE) : 0;
207
+ st_demux #(
208
+ .CHNL_NUM ( 2 ), // number of slave signals to arbit
209
+ .CHNL_NUM_LOG ( 1 ),
210
+ .TUSER_WIDTH ( `P2P_HEAD_W ),
211
+ .TDATA_WIDTH ( `P2P_DATA_W )
212
+ ) tgt_mem_demux (
213
+ .clk ( clk ), // i, 1
214
+ .rst_n ( rst_n ), // i, 1
215
+
216
+ .nxt_chnl_vld ( p2p_cfg_req_valid ), // i, 1
217
+ .nxt_chnl_sel ( nxt_chnl_sel ), // i, 8
218
+
219
+ /* --------P2P Memory Access Channel In{begin}-------- */
220
+ /* p2p_req head
221
+ * | 127 | 126:64 | 63:32 | 31:13 | 12:0 |
222
+ * | is_wr | Reserved | addr | Reserved | byte_len |
223
+ */
224
+ .s_axis_demux_valid ( st_reg_p2p_cfg_req_valid ), // i, 1
225
+ .s_axis_demux_last ( st_reg_p2p_cfg_req_last ), // i, 1
226
+ .s_axis_demux_head ( st_reg_p2p_cfg_req_head ), // i, `P2P_HEAD_W
227
+ .s_axis_demux_data ( st_reg_p2p_cfg_req_data ), // i, `P2P_DATA_W
228
+ .s_axis_demux_ready ( st_reg_p2p_cfg_req_ready ), // o, 1
229
+ /* --------P2P Memory Access Channel In{end}-------- */
230
+
231
+ /* --------P2P Memory Access Channel Out{begin}-------- */
232
+ /* p2p_req head
233
+ * | 127 | 126:64 | 63:32 | 31:13 | 12:0 |
234
+ * | is_wr | Reserved | addr | Reserved | byte_len |
235
+ */
236
+ .m_axis_demux_valid ( {p2p_tgt_req_valid, p2p_ini_req_valid} ), // o, 2 * 1
237
+ .m_axis_demux_last ( {p2p_tgt_req_last , p2p_ini_req_last } ), // o, 2 * 1
238
+ .m_axis_demux_head ( {p2p_tgt_req_head , p2p_ini_req_head } ), // o, 2 * `P2P_HEAD_W
239
+ .m_axis_demux_data ( {p2p_tgt_req_data , p2p_ini_req_data } ), // o, 2 * `P2P_DATA_W
240
+ .m_axis_demux_ready ( {p2p_tgt_req_ready, p2p_ini_req_ready} ) // i, 2 * 1
241
+ /* --------P2P Memory Access Channel Out{end}-------- */
242
+ );
243
+ /* -------- Related to demux {end}-------- */
244
+
245
+ p2p_initiator #(
246
+
247
+ ) p2p_initiator (
248
+ .clk ( clk ), // i, 1
249
+ .rst_n ( rst_n ), // i, 1
250
+
251
+ /* --------P2P Configuration Channel{begin}-------- */
252
+ /* p2p_req head
253
+ * | 127 | 126:64 | 63:32 | 31:13 | 12:0 |
254
+ * | is_wr | Reserved | addr | Reserved | byte_len |
255
+ */
256
+ .p2p_cfg_req_valid ( p2p_ini_req_valid ), // i, 1
257
+ .p2p_cfg_req_last ( p2p_ini_req_last ), // i, 1
258
+ .p2p_cfg_req_data ( p2p_ini_req_data ), // i, `P2P_DATA_W
259
+ .p2p_cfg_req_head ( p2p_ini_req_head ), // i, `P2P_HEAD_W
260
+ .p2p_cfg_req_ready ( p2p_ini_req_ready ), // o, 1
261
+ /* --------P2P Configuration Channel{end}-------- */
262
+
263
+ /* --------P2P DMA Write Req{begin}-------- */
264
+ /* dma_*_head, valid only in first beat of a packet
265
+ * | Reserved | address | Reserved | Byte length |
266
+ * | 127:96 | 95:32 | 31:13 | 12:0 |
267
+ */
268
+ .p2p_dma_wr_req_valid ( p2p_dma_wr_req_valid ), // o, 1
269
+ .p2p_dma_wr_req_last ( p2p_dma_wr_req_last ), // o, 1
270
+ .p2p_dma_wr_req_data ( p2p_dma_wr_req_data ), // o, `P2P_DATA_W
271
+ .p2p_dma_wr_req_head ( p2p_dma_wr_req_head ), // o, `DMA_HEAD_W
272
+ .p2p_dma_wr_req_ready ( p2p_dma_wr_req_ready ), // i, 1
273
+ /* --------P2P DMA Write Req{end}-------- */
274
+
275
+ /* --------p2p forward up channel{begin}-------- */
276
+ /* *_head, valid only in first beat of a packet
277
+ * | Reserved |dst_dev| src_dev | Reserved | Byte length |
278
+ * | 63:- | 47:40 | 39:32 | 31:16 | 15:0 |
279
+ */
280
+ .p2p_upper_valid ( p2p_upper_valid ), // i, 1
281
+ .p2p_upper_last ( p2p_upper_last ), // i, 1
282
+ .p2p_upper_data ( p2p_upper_data ), // i, `P2P_DATA_W
283
+ .p2p_upper_head ( p2p_upper_head ), // i, `P2P_UHEAD_W
284
+ .p2p_upper_ready ( p2p_upper_ready ) // o, 1
285
+ /* --------p2p forward up channel{end}-------- */
286
+
287
+ `ifdef PCIEI_APB_DBG
288
+ /* -------APB reated signal{begin}------- */
289
+ ,.rw_data ( ini_rw_data ) // i, `SRAM_RW_DATA_W
290
+ ,.dbg_sel ( dbg_sel_ini ) // i, 32
291
+ ,.dbg_bus ( dbg_bus_ini ) // o, 32
292
+ /* -------APB reated signal{end}------- */
293
+ `endif
294
+ );
295
+
296
+ p2p_target #(
297
+
298
+ ) p2p_target (
299
+
300
+ .clk ( clk ), // i, 1
301
+ .rst_n ( rst_n ), // i, 1
302
+ .init_end ( init_done ), // o, 1
303
+
304
+ /* --------P2P Configuration Channel{begin}-------- */
305
+ /* p2p_req head
306
+ * | 127 | 126:64 | 63:32 | 31:13 | 12:0 |
307
+ * | is_wr | Reserved | addr | Reserved | byte_len |
308
+ */
309
+ .p2p_cfg_req_valid ( p2p_tgt_req_valid ), // i, 1
310
+ .p2p_cfg_req_last ( p2p_tgt_req_last ), // i, 1
311
+ .p2p_cfg_req_data ( p2p_tgt_req_data ), // i, `P2P_DATA_W
312
+ .p2p_cfg_req_head ( p2p_tgt_req_head ), // i, `P2P_HEAD_W
313
+ .p2p_cfg_req_ready ( p2p_tgt_req_ready ), // o, 1
314
+ /* --------P2P Configuration Channel{end}-------- */
315
+
316
+ /* -------P2P Stream Channel{begin}-------- */
317
+ /* p2p_req head
318
+ * | 127 | 126:64 | 63:32 | 31:13 | 12:0 |
319
+ * | is_wr | Reserved | addr | Reserved | byte_len |
320
+ */
321
+ .p2p_mem_req_valid ( p2p_mem_req_valid ), // i, 1
322
+ .p2p_mem_req_last ( p2p_mem_req_last ), // i, 1
323
+ .p2p_mem_req_data ( p2p_mem_req_data ), // i, `P2P_DATA_W
324
+ .p2p_mem_req_head ( p2p_mem_req_head ), // i, `P2P_HEAD_W
325
+ .p2p_mem_req_ready ( p2p_mem_req_ready ), // o, 1
326
+ /* -------P2P Stream Channel{end}-------- */
327
+
328
+ /* --------p2p forward down channel{begin}-------- */
329
+ /* *_head, valid only in first beat of a packet
330
+ * | Reserved |dst_dev| src_dev | Reserved | Byte length |
331
+ * | 63:- | 47:40 | 39:32 | 31:16 | 15:0 |
332
+ */
333
+ .p2p_down_valid ( p2p_down_valid ), // o, 1
334
+ .p2p_down_last ( p2p_down_last ), // o, 1
335
+ .p2p_down_data ( p2p_down_data ), // o, `P2P_DATA_W
336
+ .p2p_down_head ( p2p_down_head ), // o, `P2P_DHEAD_W
337
+ .p2p_down_ready ( p2p_down_ready ) // i, 1
338
+ /* --------p2p forward down channel{end}-------- */
339
+
340
+ `ifdef PCIEI_APB_DBG
341
+ /* -------APB reated signal{begin}------- */
342
+ ,.rw_data ( tgt_rw_data ) // i, (2*`QUEUE_NUM+3)*`SRAM_RW_DATA_W
343
+ ,.dbg_sel ( dbg_sel_tgt ) // i, 32
344
+ ,.dbg_bus ( dbg_bus_tgt ) // o, 32
345
+ /* -------APB reated signal{end}------- */
346
+ `endif
347
+ );
348
+
349
+ endmodule // P2P
ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/P2P/ini_dev2addr_table.v ADDED
@@ -0,0 +1,181 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ `timescale 1ns / 100ps
2
+ //*************************************************************************
3
+ // > File Name: ini_dev2addr_table.v
4
+ // > Author : Kangning
5
+ // > Date : 2022-07-19
6
+ // > Note : dev -> addr table that translate dev number into address.
7
+ //*************************************************************************
8
+
9
+
10
+ module ini_dev2addr_table #(
11
+
12
+ ) (
13
+ input wire clk , // i, 1
14
+ input wire rst_n , // i, 1
15
+
16
+ /* --------P2P Configuration Channel In{begin}-------- */
17
+ /* p2p_req head
18
+ * | 127 | 126:64 | 63:32 | 31:13 | 12:0 |
19
+ * | is_wr | Reserved | addr | Reserved | byte_len |
20
+ */
21
+ input wire [1 - 1 : 0] p2p_cfg_req_valid, // i, 1
22
+ input wire [1 - 1 : 0] p2p_cfg_req_last , // i, 1
23
+ input wire [`P2P_DATA_W - 1 : 0] p2p_cfg_req_data , // i, `P2P_DATA_W
24
+ input wire [`P2P_HEAD_W - 1 : 0] p2p_cfg_req_head , // i, `P2P_HEAD_W
25
+ output wire [1 - 1 : 0] p2p_cfg_req_ready, // o, 1
26
+
27
+ // output wire [1 - 1 : 0] p2p_cfg_rrsp_valid, // o, 1
28
+ // output wire [1 - 1 : 0] p2p_cfg_rrsp_last , // o, 1
29
+ // output wire [`P2P_DATA_W - 1 : 0] p2p_cfg_rrsp_data , // o, `P2P_DATA_W
30
+ // input wire [1 - 1 : 0] p2p_cfg_rrsp_ready, // i, 1
31
+ /* --------P2P Configuration Channel In{end}-------- */
32
+
33
+ /* --------p2p forward up channel{begin}-------- */
34
+ /* *_head, valid only in first beat of a packet
35
+ * | Reserved |dst_dev| src_dev | Reserved | Byte length |
36
+ * | 63:- | 47:40 | 39:32 | 31:16 | 15:0 |
37
+ */
38
+ input wire [1 - 1 : 0] p2p_upper_valid, // i, 1
39
+ input wire [1 - 1 : 0] p2p_upper_last , // i, 1
40
+ input wire [`P2P_UHEAD_W - 1 : 0] p2p_upper_head , // i, `P2P_UHEAD_W
41
+ input wire [1 - 1 : 0] p2p_upper_ready, // i, 1
42
+ /* --------p2p forward up channel{end}-------- */
43
+
44
+ /* --------Output to dst_***_proc{begin}-------- */
45
+ output wire [1 - 1 : 0] is_valid , // o, 1
46
+ output wire [`DEV_TYPE_WIDTH - 1 : 0] dev_type , // o, `DEV_TYPE_WIDTH
47
+ output wire [`BAR_ADDR_BASE_WIDTH - 1 : 0] bar_pyld_addr, // o, `BAR_ADDR_BASE_WIDTH, lower 14 bit is invaliid
48
+ input wire is_ready // i, 1
49
+ /* --------Output to dst_***_proc{end}-------- */
50
+
51
+ `ifdef PCIEI_APB_DBG
52
+ /* -------APB reated signal{begin}------- */
53
+ ,input wire [`SRAM_RW_DATA_W-1:0] rw_data // i, `SRAM_RW_DATA_W
54
+ ,output wire [`INI_DEV2ADDR_SIGNAL_W-1:0] dbg_signal // o, `INI_DEV2ADDR_SIGNAL_W
55
+ /* -------APB reated signal{end}------- */
56
+ `endif
57
+ );
58
+
59
+ localparam DEV2ADDR_TAB_WIDTH = 1 + `BAR_ADDR_BASE_WIDTH + `DEV_TYPE_WIDTH + `DEV_NUM_WIDTH; // 63
60
+
61
+ /* -------- related write interface{begin}-------- */
62
+ wire wr_en;
63
+
64
+ wire cfg_wr;
65
+
66
+ wire [31:0] bar0_addr;
67
+ wire [`D2A_TAB_DEPTH -1: 0] wr_addr;
68
+ wire [DEV2ADDR_TAB_WIDTH-1: 0] wr_data;
69
+ wire [`BAR_ADDR_BASE_WIDTH-1:0] wr_bar_pyld_addr;
70
+ wire [`DEV_TYPE_WIDTH -1:0] wr_dev_type;
71
+ wire [`DEV_NUM_WIDTH -1:0] wr_dev_num ;
72
+ /* -------- related write interface{end}-------- */
73
+
74
+ /* -------- related read interface{begin}-------- */
75
+ reg p2p_upper_sop;
76
+
77
+ wire rd_en;
78
+ // reg rd_en_reg;
79
+ wire [`DEV_TYPE_WIDTH-1:0] dst_dev;
80
+ wire [`DEV_NUM_WIDTH -1:0] dev_num;
81
+ wire [DEV2ADDR_TAB_WIDTH-1:0] rd_data;
82
+ /* -------- related to read interface{end}-------- */
83
+
84
+ `ifdef PCIEI_APB_DBG
85
+ /* -------APB reated signal{begin}------- */
86
+ wire [1:0] rtsel;
87
+ wire [1:0] wtsel;
88
+ wire [1:0] ptsel;
89
+ wire vg ;
90
+ wire vs ;
91
+ /* -------APB reated signal{end}------- */
92
+ `endif
93
+
94
+ //---------------------------------------------------------------------------------------------------------------------------
95
+
96
+ `ifdef PCIEI_APB_DBG
97
+ /* -------APB reated signal{begin}------- */
98
+ assign {rtsel, wtsel, ptsel, vg, vs} = rw_data;
99
+ assign dbg_signal = { // 240
100
+ wr_en, cfg_wr, bar0_addr, // 34
101
+ wr_addr, wr_data, wr_bar_pyld_addr, wr_dev_type, wr_dev_num , // 129
102
+ p2p_upper_sop, rd_en, dst_dev, dev_num, rd_data // 77
103
+ };
104
+ /* -------APB reated signal{end}------- */
105
+ `endif
106
+
107
+ /* -------- related write interface{begin}-------- */
108
+ assign bar0_addr = p2p_cfg_req_head[63:32];
109
+ assign cfg_wr = p2p_cfg_req_head[127];
110
+
111
+ assign wr_en = p2p_cfg_req_valid & p2p_cfg_req_ready & cfg_wr & (bar0_addr[19:`D2A_TAB_DEPTH + 4] == (`CFG_BAR_INI_ADDR_BASE >> (4 + `D2A_TAB_DEPTH)));
112
+ assign wr_addr = wr_en ? bar0_addr[`D2A_TAB_DEPTH + 4 - 1 : 4] : 0;
113
+ assign wr_dev_num = p2p_cfg_req_data[7:0];
114
+ assign wr_dev_type = p2p_cfg_req_data[11:8];
115
+ assign wr_bar_pyld_addr = p2p_cfg_req_data[63:14];
116
+ assign wr_data = {1'd1, wr_bar_pyld_addr, wr_dev_type, wr_dev_num};
117
+ /* -------- related write interface{end}-------- */
118
+
119
+ /* -------- related read interface{begin}-------- */
120
+ assign dst_dev = p2p_upper_head[32+2*`DEV_NUM_WIDTH-1:32+`DEV_NUM_WIDTH];
121
+ assign rd_en = p2p_upper_sop & p2p_upper_valid & p2p_upper_ready;
122
+ always @(posedge clk, negedge rst_n) begin
123
+ if (~rst_n) begin
124
+ p2p_upper_sop <= `TD 1'd1;
125
+ end
126
+ else if (p2p_upper_valid & p2p_upper_ready & p2p_upper_last) begin
127
+ p2p_upper_sop <= `TD 1'd1;
128
+ end
129
+ else if (p2p_upper_valid & p2p_upper_ready) begin
130
+ p2p_upper_sop <= `TD 1'd0;
131
+ end
132
+ end
133
+
134
+ // always @(posedge clk, negedge rst_n) begin
135
+ // if (~rst_n) begin
136
+ // rd_en_reg <= `TD 1'd0;
137
+ // end
138
+ // else if (rd_en) begin
139
+ // rd_en_reg <= `TD 1'd1;
140
+ // end
141
+ // else if (is_ready) begin
142
+ // rd_en_reg <= `TD 1'd0;
143
+ // end
144
+ // end
145
+ /* -------- related to read interface{end}-------- */
146
+
147
+ pcieifc_sd_sram #(
148
+ .DATAWIDTH ( DEV2ADDR_TAB_WIDTH ), // Memory data word width, 63
149
+ .ADDRWIDTH ( `D2A_TAB_DEPTH ) // Number of mem address bits, 4
150
+ ) dev2addr_tab (
151
+ .clk ( clk ), // i, 1
152
+ .rst_n ( rst_n ), // i, 1
153
+
154
+ .wea ( wr_en ), // i, 1; high active
155
+ .addra ( wr_addr ), // i, ADDRWIDTH
156
+ .dina ( wr_data ), // i, DATAWIDTH
157
+
158
+ .reb ( rd_en ), // i, 1
159
+ .addrb ( dst_dev ), // i, ADDRWIDTH
160
+ .doutb ( rd_data ) // o, DATAWIDTH
161
+
162
+ `ifdef PCIEI_APB_DBG
163
+ ,.rtsel ( rtsel ) // i, 2
164
+ ,.wtsel ( wtsel ) // i, 2
165
+ ,.ptsel ( ptsel ) // i, 2
166
+ ,.vg ( vg ) // i, 1
167
+ ,.vs ( vs ) // i, 1
168
+ `endif
169
+ );
170
+
171
+ assign {is_valid, bar_pyld_addr, dev_type, dev_num} = rd_data; // rd_en_reg ? rd_data : 0;
172
+ /* --------CFG interface{begin}-------- */
173
+ assign p2p_cfg_req_ready = !rd_en;
174
+
175
+ // We don't support cfg space read.
176
+ // assign p2p_cfg_rrsp_valid = 0;
177
+ // assign p2p_cfg_rrsp_last = 0;
178
+ // assign p2p_cfg_rrsp_data = 0;
179
+ /* --------CFG interface{end}-------- */
180
+
181
+ endmodule
ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/P2P/ini_dst_nic_proc.v ADDED
@@ -0,0 +1,170 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ `timescale 1ns / 100ps
2
+ //*************************************************************************
3
+ // > File Name: ini_dst_nic_proc.v
4
+ // > Author : Kangning
5
+ // > Date : 2022-07-25
6
+ // > Note : Related processing if destination address is belongs to NIC.
7
+ //*************************************************************************
8
+
9
+
10
+ module ini_dst_nic_proc #(
11
+
12
+ ) (
13
+
14
+ input wire clk , // i, 1
15
+ input wire rst_n , // i, 1
16
+
17
+ /* -------next pkt information{begin}-------- */
18
+ input wire nxt_is_valid, // i, 1
19
+ input wire [`DEV_TYPE_WIDTH - 1 : 0] nxt_dev_type, // i, `DEV_TYPE_WIDTH
20
+ input wire [`BAR_ADDR_BASE_WIDTH - 1 : 0] nxt_bar_addr, // i, `BAR_ADDR_BASE_WIDTH
21
+ /* -------next pkt information{end}-------- */
22
+
23
+ /* --------p2p forward up channel{begin}-------- */
24
+ /* *_head, valid only in first beat of a packet
25
+ * | Reserved |dst_dev| src_dev | Reserved | Byte length |
26
+ * | 63:- | 47:40 | 39:32 | 31:16 | 15:0 |
27
+ */
28
+ input wire p2p_upper_valid, // i, 1
29
+ input wire p2p_upper_last , // i, 1
30
+ input wire [`P2P_UHEAD_W - 1 : 0] p2p_upper_head , // i, `P2P_UHEAD_W
31
+ input wire [`P2P_DATA_W - 1 : 0] p2p_upper_data , // i, `P2P_DATA_W
32
+ output wire p2p_upper_ready, // o, 1
33
+ /* --------p2p forward up channel{end}-------- */
34
+
35
+ /* --------current pkt information{begin}-------- */
36
+ input wire is_valid, // i, 1
37
+ input wire [`DEV_TYPE_WIDTH - 1 : 0] dev_type, // i, `DEV_TYPE_WIDTH
38
+ input wire [`BAR_ADDR_BASE_WIDTH - 1 : 0] bar_addr, // i, `BAR_ADDR_BASE_WIDTH
39
+ /* --------current pkt information{end}-------- */
40
+
41
+ /* -------output inteface{begin}------- */
42
+ /* dma_*_head
43
+ * | Reserved | address | Reserved | Byte length |
44
+ * | 127:96 | 95:32 | 31:16 | 15:0 |
45
+ */
46
+ output wire axis_nic_valid, // o, 1
47
+ output wire axis_nic_last , // o, 1
48
+ output wire [`DMA_HEAD_W - 1 : 0] axis_nic_head , // o, `DMA_HEAD_W
49
+ output wire [`P2P_DATA_W - 1 : 0] axis_nic_data , // o, `P2P_DATA_W
50
+ input wire axis_nic_ready // i, 1
51
+ /* -------output inteface{end}------- */
52
+ );
53
+
54
+ localparam P2P_BYTE_NUM = `P2P_DATA_W / 8; // byte num in one beat
55
+
56
+ /* -------- FSM when Destination is NIC{begin}-------- */
57
+ localparam IDLE = 3'b001,
58
+ TX_DESC = 3'b010,
59
+ TX_PYLD = 3'b100;
60
+
61
+ reg [2:0] cur_state, nxt_state;
62
+ wire is_idle, is_tx_desc, is_tx_pyld;
63
+ /* -------- FSM when Destination is NIC{end}-------- */
64
+
65
+ /* -------- Output head generation {begin} -------- */
66
+ reg [15:0] byte_left;
67
+
68
+ wire [`DEV_NUM_WIDTH-1:0] pyld_dst_dev, pyld_src_dev;
69
+ wire [15:0] pyld_byte_len;
70
+ wire [63:0] pyld_addr;
71
+
72
+ wire [15:0] desc_byte_len;
73
+ wire [63:0] desc_addr;
74
+
75
+ wire [`P2P_DATA_W-1:0] pyld_data_w, desc_data_w;
76
+ wire [`DMA_HEAD_W-1:0] pyld_head_w, desc_head_w;
77
+ /* -------- Output head generation {end} -------- */
78
+
79
+ //----------------------------------------------------------------------------------------------------------------------------------------------//
80
+
81
+ /* -------- Output head generation {begin} -------- */
82
+ always @(posedge clk, negedge rst_n) begin
83
+ if (~rst_n) begin
84
+ byte_left <= `TD 0;
85
+ end
86
+ else if (is_tx_pyld & axis_nic_valid & axis_nic_ready & axis_nic_last) begin
87
+ byte_left <= `TD 0;
88
+ end
89
+ else if (is_tx_desc & axis_nic_valid & axis_nic_ready) begin
90
+ byte_left <= `TD pyld_byte_len;
91
+ end
92
+ else if (is_tx_pyld & axis_nic_valid & axis_nic_ready) begin
93
+ byte_left <= `TD byte_left - P2P_BYTE_NUM;
94
+ end
95
+ end
96
+
97
+ assign pyld_head_w = {32'd0, pyld_addr, 16'd0, pyld_byte_len};
98
+ assign pyld_data_w = p2p_upper_data;
99
+
100
+ assign desc_head_w = {32'd0, desc_addr, 16'd0, desc_byte_len};
101
+ assign desc_data_w = {192'd0, pyld_dst_dev, pyld_src_dev, pyld_byte_len, 32'd0};
102
+
103
+ assign pyld_dst_dev = p2p_upper_head[32+2*`DEV_NUM_WIDTH-1:32+`DEV_NUM_WIDTH];
104
+ assign pyld_src_dev = p2p_upper_head[32+`DEV_NUM_WIDTH-1:32];
105
+ assign pyld_byte_len = p2p_upper_head[15:0];
106
+ assign pyld_addr = {bar_addr, 14'd0};
107
+
108
+ assign desc_byte_len = 16'd16;
109
+ assign desc_addr = {bar_addr, 14'h0} + `BAR_DESC_OFFSET;
110
+ /* -------- Output head generation {end} -------- */
111
+
112
+ /* -------Destinstaion NIC processing FSM{begin}------- */
113
+ /******************** Stage 1: State Register **********************/
114
+ assign is_idle = (cur_state == IDLE );
115
+ assign is_tx_desc = (cur_state == TX_DESC);
116
+ assign is_tx_pyld = (cur_state == TX_PYLD);
117
+
118
+ always @(posedge clk, negedge rst_n) begin
119
+ if(~rst_n)
120
+ cur_state <= `TD IDLE;
121
+ else
122
+ cur_state <= `TD nxt_state;
123
+ end
124
+
125
+ /******************** Stage 2: State Transition **********************/
126
+
127
+ always @(*) begin
128
+ case(cur_state)
129
+ IDLE: begin
130
+ if (nxt_dev_type == `DEV_NIC & nxt_is_valid) // Imlying the only beat
131
+ nxt_state = TX_DESC;
132
+ else
133
+ nxt_state = IDLE;
134
+ end
135
+ TX_DESC: begin
136
+ if (axis_nic_valid & axis_nic_ready)
137
+ nxt_state = TX_PYLD;
138
+ else
139
+ nxt_state = TX_DESC;
140
+ end
141
+ TX_PYLD: begin
142
+ if (axis_nic_valid & axis_nic_ready & axis_nic_last) begin
143
+ if (nxt_dev_type == `DEV_NIC & nxt_is_valid)
144
+ nxt_state = TX_DESC;
145
+ else
146
+ nxt_state = IDLE;
147
+ end
148
+ else
149
+ nxt_state = TX_PYLD;
150
+ end
151
+ default: begin
152
+ nxt_state = IDLE;
153
+ end
154
+ endcase
155
+ end
156
+ /******************** Stage 3: Output **********************/
157
+
158
+ assign axis_nic_valid = is_tx_desc |
159
+ (is_tx_pyld & p2p_upper_valid);
160
+ assign axis_nic_last = is_tx_desc |
161
+ (is_tx_pyld & (byte_left <= 16'd32));
162
+ assign axis_nic_head = ({`DMA_HEAD_W{is_tx_desc}} & desc_head_w) |
163
+ ({`DMA_HEAD_W{is_tx_pyld}} & pyld_head_w);
164
+ assign axis_nic_data = ({`P2P_DATA_W{is_tx_desc}} & desc_data_w) |
165
+ ({`P2P_DATA_W{is_tx_pyld}} & pyld_data_w);
166
+
167
+ assign p2p_upper_ready = is_tx_pyld & axis_nic_ready;
168
+ /* -------Destinstaion NIC processing FSM{end}------- */
169
+
170
+ endmodule
ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/P2P/ini_pyld_split_proc.v ADDED
@@ -0,0 +1,48 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ `timescale 1ns / 100ps
2
+ //*************************************************************************
3
+ // > File Name: ini_pyld_split_proc.v
4
+ // > Author : Kangning
5
+ // > Date : 2022-07-27
6
+ // > Note : split payload into 4KB aligned packet
7
+ //*************************************************************************
8
+
9
+
10
+ module ini_pyld_split_proc #(
11
+
12
+ ) (
13
+
14
+ input wire clk , // i, 1
15
+ input wire rst_n , // i, 1
16
+
17
+ /* --------raw pyld{begin}-------- */
18
+ /* dma_*_head
19
+ * | Reserved | address | Reserved | Byte length |
20
+ * | 127:96 | 95:32 | 31:16 | 15:0 |
21
+ */
22
+ input wire axis_raw_valid, // i, 1
23
+ input wire axis_raw_last , // i, 1
24
+ input wire [`DMA_HEAD_W - 1 : 0] axis_raw_head , // i, `DMA_HEAD_W
25
+ input wire [`P2P_DATA_W - 1 : 0] axis_raw_data , // i, `P2P_DATA_W
26
+ output wire axis_raw_ready, // o, 1
27
+ /* --------raw pyld{end}-------- */
28
+
29
+ /* -------splited_pyld{begin}------- */
30
+ /* dma_*_head
31
+ * | Reserved | address | Reserved | Byte length |
32
+ * | 127:96 | 95:32 | 31:16 | 15:0 |
33
+ */
34
+ output wire axis_splited_valid, // o, 1
35
+ output wire axis_splited_last , // o, 1
36
+ output wire [`DMA_HEAD_W - 1 : 0] axis_splited_head , // o, `DMA_HEAD_W
37
+ output wire [`P2P_DATA_W - 1 : 0] axis_splited_data , // o, `P2P_DATA_W
38
+ input wire axis_splited_ready // i, 1
39
+ /* -------splited_pyld{end}------- */
40
+ );
41
+
42
+ assign axis_splited_valid = axis_raw_valid;
43
+ assign axis_splited_last = axis_raw_last ;
44
+ assign axis_splited_head = axis_raw_head ;
45
+ assign axis_splited_data = axis_raw_data ;
46
+ assign axis_raw_ready = axis_splited_ready;
47
+
48
+ endmodule
ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/P2P/p2p_initiator.v ADDED
@@ -0,0 +1,312 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ `timescale 1ns / 100ps
2
+ //*************************************************************************
3
+ // > File : p2p_initiator.v
4
+ // > Author : Kangning
5
+ // > Date : 2022-06-10
6
+ // > Note : DMA P2P initiator
7
+ //*************************************************************************
8
+
9
+ module p2p_initiator #(
10
+
11
+ ) (
12
+ input wire clk , // i, 1
13
+ input wire rst_n , // i, 1
14
+
15
+ /* --------P2P Configuration Channel{begin}-------- */
16
+ /* p2p_req head
17
+ * | 127 | 126:64 | 63:32 | 31:13 | 12:0 |
18
+ * | is_wr | Reserved | addr | Reserved | byte_len |
19
+ */
20
+ input wire [1 - 1 : 0] p2p_cfg_req_valid, // i, 1
21
+ input wire [1 - 1 : 0] p2p_cfg_req_last , // i, 1
22
+ input wire [`P2P_HEAD_W - 1 : 0] p2p_cfg_req_head , // i, `P2P_HEAD_W
23
+ input wire [`P2P_DATA_W - 1 : 0] p2p_cfg_req_data , // i, `P2P_DATA_W
24
+ output wire [1 - 1 : 0] p2p_cfg_req_ready, // o, 1
25
+
26
+ // output wire [1 - 1 : 0] p2p_cfg_rrsp_valid, // o, 1
27
+ // output wire [1 - 1 : 0] p2p_cfg_rrsp_last , // o, 1
28
+ // output wire [`P2P_DATA_W - 1 : 0] p2p_cfg_rrsp_data , // o, `P2P_DATA_W
29
+ // input wire [1 - 1 : 0] p2p_cfg_rrsp_ready, // i, 1
30
+ /* --------P2P Configuration Channel{end}-------- */
31
+
32
+ /* --------P2P DMA Write Req{begin}-------- */
33
+ /* dma_*_head
34
+ * | Reserved | address | Reserved | Byte length |
35
+ * | 127:96 | 95:32 | 31:13 | 12:0 |
36
+ */
37
+ output wire [1 - 1 : 0] p2p_dma_wr_req_valid, // o, 1
38
+ output wire [1 - 1 : 0] p2p_dma_wr_req_last , // o, 1
39
+ output wire [`DMA_HEAD_W - 1 : 0] p2p_dma_wr_req_head , // o, `DMA_HEAD_W
40
+ output wire [`P2P_DATA_W - 1 : 0] p2p_dma_wr_req_data , // o, `P2P_DATA_W
41
+ input wire [1 - 1 : 0] p2p_dma_wr_req_ready, // i, 1
42
+ /* --------P2P DMA Write Req{end}-------- */
43
+
44
+ /* --------p2p forward up channel{begin}-------- */
45
+ /* *_head, valid only in first beat of a packet
46
+ * | Reserved |dst_dev| src_dev | Reserved | Byte length |
47
+ * | 63:- | 47:40 | 39:32 | 31:16 | 15:0 |
48
+ */
49
+ input wire [1 - 1 : 0] p2p_upper_valid, // i, 1
50
+ input wire [1 - 1 : 0] p2p_upper_last , // i, 1
51
+ input wire [`P2P_UHEAD_W - 1 : 0] p2p_upper_head , // i, `P2P_UHEAD_W
52
+ input wire [`P2P_DATA_W - 1 : 0] p2p_upper_data , // i, `P2P_DATA_W
53
+ output wire [1 - 1 : 0] p2p_upper_ready // o, 1
54
+ /* --------p2p forward up channel{end}-------- */
55
+
56
+ `ifdef PCIEI_APB_DBG
57
+ /* -------APB reated signal{begin}------- */
58
+ ,input wire [`SRAM_RW_DATA_W-1:0] rw_data // i, `SRAM_RW_DATA_W
59
+ ,input wire [31:0] dbg_sel // i, 32
60
+ ,output wire [31:0] dbg_bus // o, 32
61
+ /* -------APB reated signal{end}------- */
62
+ `endif
63
+ );
64
+
65
+ // /* -------next pkt information{begin}-------- */
66
+ // wire nxt_is_valid; // i, 1
67
+ // wire [`DEV_TYPE_WIDTH - 1 : 0] nxt_dev_type; // i, `DEV_TYPE_WIDTH
68
+ // wire [`BAR_ADDR_BASE_WIDTH - 1 : 0] nxt_bar_addr; // i, `BAR_ADDR_BASE_WIDTH
69
+ // /* -------next pkt information{end}-------- */
70
+
71
+ /* --------current pkt information{begin}-------- */
72
+ wire is_valid; // i, 1
73
+ wire [`DEV_TYPE_WIDTH - 1 : 0] dev_type; // i, `DEV_TYPE_WIDTH
74
+ wire [`BAR_ADDR_BASE_WIDTH - 1 : 0] bar_addr; // i, `BAR_ADDR_BASE_WIDTH
75
+ /* --------current pkt information{end}-------- */
76
+
77
+ /* --------current pkt information{begin}-------- */
78
+ wire st1_is_valid; // i, 1
79
+ wire [`DEV_TYPE_WIDTH - 1 : 0] st1_dev_type; // i, `DEV_TYPE_WIDTH
80
+ wire [`BAR_ADDR_BASE_WIDTH - 1 : 0] st1_bar_addr; // i, `BAR_ADDR_BASE_WIDTH
81
+ /* --------current pkt information{end}-------- */
82
+
83
+ /* -------Related to NIC and DSA module{begin}-------- */
84
+ wire st0_upper_valid;
85
+ wire st0_upper_last ;
86
+ wire [`P2P_UHEAD_W - 1 : 0] st0_upper_head ;
87
+ wire [`P2P_DATA_W - 1 : 0] st0_upper_data ;
88
+ wire st0_upper_ready;
89
+
90
+ wire st1_upper_valid;
91
+ wire st1_upper_last ;
92
+ wire [`P2P_UHEAD_W - 1 : 0] st1_upper_head ;
93
+ wire [`P2P_DATA_W - 1 : 0] st1_upper_data ;
94
+ wire st1_upper_ready;
95
+ /* -------Related to NIC and DSA module{end}-------- */
96
+
97
+ /* -------MUX -> pyld_split_proc{begin}------- */
98
+ /* dma_*_head
99
+ * | Reserved | address | Reserved | Byte length |
100
+ * | 127:96 | 95:32 | 31:16 | 15:0 |
101
+ */
102
+ wire axis_proc_out_valid; // o, 1
103
+ wire axis_proc_out_last ; // o, 1
104
+ wire [`DMA_HEAD_W - 1 : 0] axis_proc_out_head ; // o, `DMA_HEAD_W
105
+ wire [`P2P_DATA_W - 1 : 0] axis_proc_out_data ; // o, `P2P_DATA_W
106
+ wire axis_proc_out_ready; // i, 1
107
+ /* -------MUX -> pyld_split_proc{end}------- */
108
+
109
+ `ifdef PCIEI_APB_DBG
110
+ /* -------APB reated signal{begin}------- */
111
+ wire [`INI_TOP_SIGNAL_W-1:0] dbg_signal_ini_top;
112
+ wire [`INI_DEV2ADDR_SIGNAL_W-1:0] dbg_signal_ini_dev2addr;
113
+ /* -------APB reated signal{end}------- */
114
+ `endif
115
+
116
+ //-------------------------------------------------------------------------------------------------------------------
117
+
118
+ `ifdef PCIEI_APB_DBG
119
+ /* -------APB reated signal{begin}------- */
120
+
121
+ // Debug bus for p2p ini
122
+ assign dbg_bus = {dbg_signal_ini_top, dbg_signal_ini_dev2addr} >> {dbg_sel, 5'd0};
123
+
124
+ // Debug signal for p2p ini top
125
+ assign dbg_signal_ini_top = { // 1143
126
+
127
+ is_valid, dev_type, bar_addr, // 55
128
+ st1_is_valid, st1_dev_type, st1_bar_addr, // 55
129
+ st0_upper_valid, st0_upper_last , st0_upper_head , st0_upper_data , st0_upper_ready, // 323
130
+ st1_upper_valid, st1_upper_last , st1_upper_head , st1_upper_data , st1_upper_ready, // 323
131
+ axis_proc_out_valid, axis_proc_out_last , axis_proc_out_head , axis_proc_out_data , axis_proc_out_ready // 387
132
+ };
133
+ /* -------APB reated signal{end}------- */
134
+ `endif
135
+
136
+ ini_dev2addr_table #(
137
+
138
+ ) ini_dev2addr_table (
139
+ .clk ( clk ), // i, 1
140
+ .rst_n ( rst_n ), // i, 1
141
+
142
+ /* --------P2P Configuration Channel In{begin}-------- */
143
+ /* p2p_req head
144
+ * | 127 | 126:64 | 63:32 | 31:13 | 12:0 |
145
+ * | is_wr | Reserved | addr | Reserved | byte_len |
146
+ */
147
+ .p2p_cfg_req_valid ( p2p_cfg_req_valid ), // i, 1
148
+ .p2p_cfg_req_last ( p2p_cfg_req_last ), // i, 1
149
+ .p2p_cfg_req_data ( p2p_cfg_req_data ), // i, `P2P_DATA_W
150
+ .p2p_cfg_req_head ( p2p_cfg_req_head ), // i, `P2P_HEAD_W
151
+ .p2p_cfg_req_ready ( p2p_cfg_req_ready ), // o, 1
152
+
153
+ // .p2p_cfg_rrsp_valid ( p2p_cfg_rrsp_valid ), // o, 1
154
+ // .p2p_cfg_rrsp_last ( p2p_cfg_rrsp_last ), // o, 1
155
+ // .p2p_cfg_rrsp_data ( p2p_cfg_rrsp_data ), // o, `P2P_DATA_W
156
+ // .p2p_cfg_rrsp_ready ( p2p_cfg_rrsp_ready ), // i, 1
157
+ /* --------P2P Configuration Channel In{end}-------- */
158
+
159
+ /* --------p2p forward up channel{begin}-------- */
160
+ /* *_head, valid only in first beat of a packet
161
+ * | Reserved |dst_dev| src_dev | Reserved | Byte length |
162
+ * | 63:- | 47:40 | 39:32 | 31:16 | 15:0 |
163
+ */
164
+ .p2p_upper_valid ( p2p_upper_valid ), // i, 1
165
+ .p2p_upper_last ( p2p_upper_last ), // i, 1
166
+ .p2p_upper_head ( p2p_upper_head ), // i, `P2P_UHEAD_W
167
+ .p2p_upper_ready ( p2p_upper_ready ), // i, 1
168
+ /* --------p2p forward up channel{end}-------- */
169
+
170
+ /* --------Output to dst_***_proc{begin}-------- */
171
+ .is_valid ( is_valid ), // o, 1
172
+ .dev_type ( dev_type ), // o, 4
173
+ .bar_pyld_addr ( bar_addr ), // o, 64, lower 14 bit is invaliid
174
+ .is_ready ( st0_upper_ready ) // i, 1
175
+ /* --------Output to dst_***_proc{end}-------- */
176
+
177
+ `ifdef PCIEI_APB_DBG
178
+ /* -------APB reated signal{begin}------- */
179
+ ,.rw_data ( rw_data ) // i, `SRAM_RW_DATA_W
180
+ ,.dbg_signal ( dbg_signal_ini_dev2addr ) // o, `INI_DEV2ADDR_SIGNAL_W
181
+ /* -------APB reated signal{end}------- */
182
+ `endif
183
+ );
184
+
185
+ /*
186
+ * This reg is used to stall for looking up the dev2addr table
187
+ */
188
+ st_reg #(
189
+ .TUSER_WIDTH ( `P2P_UHEAD_W ),
190
+ .TDATA_WIDTH ( `P2P_DATA_W ),
191
+ .MODE ( 1 )
192
+ ) st_reg0 (
193
+ .clk ( clk ), // i, 1
194
+ .rst_n ( rst_n ), // i, 1
195
+
196
+ /* -------input axis-like interface{begin}------- */
197
+ .axis_tvalid ( p2p_upper_valid ), // i, 1
198
+ .axis_tlast ( p2p_upper_last ), // i, 1
199
+ .axis_tuser ( p2p_upper_head ), // i, TUSER_WIDTH
200
+ .axis_tdata ( p2p_upper_data ), // i, TDATA_WIDTH
201
+ .axis_tready ( p2p_upper_ready ), // o, 1
202
+ /* -------input axis-like interface{end}------- */
203
+
204
+ /* -------output in_reg inteface{begin}------- */
205
+ .axis_reg_tvalid ( st0_upper_valid ), // o, 1 // read valid from input register
206
+ .axis_reg_tlast ( st0_upper_last ), // o, 1
207
+ .axis_reg_tuser ( st0_upper_head ), // o, TUSER_WIDTH
208
+ .axis_reg_tdata ( st0_upper_data ), // o, TDATA_WIDTH
209
+ .axis_reg_tready ( st0_upper_ready ) // i, 1
210
+ /* -------output in_reg inteface{end}------- */
211
+ );
212
+
213
+ st_reg #(
214
+ .TUSER_WIDTH ( 1 + `DEV_TYPE_WIDTH + `BAR_ADDR_BASE_WIDTH + `P2P_UHEAD_W ),
215
+ .TDATA_WIDTH ( `P2P_DATA_W ),
216
+ .MODE ( 1 )
217
+ ) st_reg1 (
218
+ .clk ( clk ), // i, 1
219
+ .rst_n ( rst_n ), // i, 1
220
+
221
+ /* -------input axis-like interface{begin}------- */
222
+ .axis_tvalid ( st0_upper_valid ), // i, 1
223
+ .axis_tlast ( st0_upper_last ), // i, 1
224
+ .axis_tuser ( {is_valid, dev_type, bar_addr, st0_upper_head} ), // i, TUSER_WIDTH
225
+ .axis_tdata ( st0_upper_data ), // i, TDATA_WIDTH
226
+ .axis_tready ( st0_upper_ready ), // o, 1
227
+ /* -------input axis-like interface{end}------- */
228
+
229
+ /* -------output in_reg inteface{begin}------- */
230
+ .axis_reg_tvalid ( st1_upper_valid ), // o, 1 // read valid from input register
231
+ .axis_reg_tlast ( st1_upper_last ), // o, 1
232
+ .axis_reg_tuser ( {st1_is_valid, st1_dev_type, st1_bar_addr, st1_upper_head} ), // o, TUSER_WIDTH
233
+ .axis_reg_tdata ( st1_upper_data ), // o, TDATA_WIDTH
234
+ .axis_reg_tready ( st1_upper_ready ) // i, 1
235
+ /* -------output in_reg inteface{end}------- */
236
+ );
237
+
238
+ ini_dst_nic_proc #(
239
+
240
+ ) ini_dst_nic_proc (
241
+ .clk ( clk ), // i, 1
242
+ .rst_n ( rst_n ), // i, 1
243
+
244
+ /* -------next pkt information{begin}-------- */
245
+ .nxt_is_valid ( is_valid & st0_upper_valid ), // i, 1
246
+ .nxt_dev_type ( dev_type ), // i, `DEV_TYPE_WIDTH
247
+ .nxt_bar_addr ( bar_addr ), // i, `BAR_ADDR_BASE_WIDTH
248
+ /* -------next pkt information{end}-------- */
249
+
250
+ /* --------p2p forward up channel{begin}-------- */
251
+ /* *_head, valid only in first beat of a packet
252
+ * | Reserved |dst_dev| src_dev | Reserved | Byte length |
253
+ * | 63:- | 47:40 | 39:32 | 31:16 | 15:0 |
254
+ */
255
+ .p2p_upper_valid ( st1_upper_valid ), // i, 1
256
+ .p2p_upper_last ( st1_upper_last ), // i, 1
257
+ .p2p_upper_head ( st1_upper_head ), // i, `P2P_UHEAD_W
258
+ .p2p_upper_data ( st1_upper_data ), // i, `P2P_DATA_W
259
+ .p2p_upper_ready ( st1_upper_ready ), // o, 1
260
+ /* --------p2p forward up channel{end}-------- */
261
+
262
+ /* --------current pkt information{begin}-------- */
263
+ .is_valid ( st1_is_valid ), // i, 1
264
+ .dev_type ( st1_dev_type ), // i, `DEV_TYPE_WIDTH
265
+ .bar_addr ( st1_bar_addr ), // i, `BAR_ADDR_BASE_WIDTH
266
+ /* --------current pkt information{end}-------- */
267
+
268
+ /* -------output inteface{begin}------- */
269
+ /* dma_*_head
270
+ * | Reserved | address | Reserved | Byte length |
271
+ * | 127:96 | 95:32 | 31:16 | 15:0 |
272
+ */
273
+ .axis_nic_valid ( axis_proc_out_valid ), // o, 1
274
+ .axis_nic_last ( axis_proc_out_last ), // o, 1
275
+ .axis_nic_head ( axis_proc_out_head ), // o, `DMA_HEAD_W
276
+ .axis_nic_data ( axis_proc_out_data ), // o, `P2P_DATA_W
277
+ .axis_nic_ready ( axis_proc_out_ready ) // i, 1
278
+ /* -------output inteface{end}------- */
279
+ );
280
+
281
+ ini_pyld_split_proc #(
282
+
283
+ ) ini_pyld_split_proc (
284
+ .clk ( clk ), // i, 1
285
+ .rst_n ( rst_n ), // i, 1
286
+
287
+ /* --------raw pyld{begin}-------- */
288
+ /* dma_*_head
289
+ * | Reserved | address | Reserved | Byte length |
290
+ * | 127:96 | 95:32 | 31:16 | 15:0 |
291
+ */
292
+ .axis_raw_valid ( axis_proc_out_valid ), // o, 1
293
+ .axis_raw_last ( axis_proc_out_last ), // o, 1
294
+ .axis_raw_head ( axis_proc_out_head ), // o, `DMA_HEAD_W
295
+ .axis_raw_data ( axis_proc_out_data ), // o, `P2P_DATA_W
296
+ .axis_raw_ready ( axis_proc_out_ready ), // i, 1
297
+ /* --------raw pyld{end}-------- */
298
+
299
+ /* --------splited_pyld{begin}-------- */
300
+ /* dma_*_head
301
+ * | Reserved | address | Reserved | Byte length |
302
+ * | 127:96 | 95:32 | 31:13 | 12:0 |
303
+ */
304
+ .axis_splited_valid ( p2p_dma_wr_req_valid ), // o, 1
305
+ .axis_splited_last ( p2p_dma_wr_req_last ), // o, 1
306
+ .axis_splited_head ( p2p_dma_wr_req_head ), // o, `DMA_HEAD_W
307
+ .axis_splited_data ( p2p_dma_wr_req_data ), // o, `P2P_DATA_W
308
+ .axis_splited_ready ( p2p_dma_wr_req_ready ) // i, 1
309
+ /* --------splited_pyld{end}-------- */
310
+ );
311
+
312
+ endmodule // p2p_initiator
ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/P2P/p2p_target.v ADDED
@@ -0,0 +1,601 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ `timescale 1ns / 100ps
2
+ //*************************************************************************
3
+ // > File : p2p_target.v
4
+ // > Author : Kangning
5
+ // > Date : 2022-06-10
6
+ // > Note : DMA P2P target
7
+ //*************************************************************************
8
+
9
+
10
+ module p2p_target #(
11
+
12
+ ) (
13
+ input wire clk , // i, 1
14
+ input wire rst_n , // i, 1
15
+ output wire init_end, // o, 1
16
+
17
+ /* --------P2P Configuration Channel{begin}-------- */
18
+ /* p2p_req head
19
+ * | 127 | 126:64 | 63:32 | 31:13 | 12:0 |
20
+ * | is_wr | Reserved | addr | Reserved | byte_len |
21
+ */
22
+ input wire p2p_cfg_req_valid, // i, 1
23
+ input wire p2p_cfg_req_last , // i, 1
24
+ input wire [`P2P_DATA_W - 1 : 0] p2p_cfg_req_data , // i, `P2P_DATA_W
25
+ input wire [`P2P_HEAD_W - 1 : 0] p2p_cfg_req_head , // i, `P2P_HEAD_W
26
+ output wire p2p_cfg_req_ready, // o, 1
27
+
28
+ // output wire p2p_cfg_rrsp_valid, // o, 1
29
+ // output wire p2p_cfg_rrsp_last , // o, 1
30
+ // output wire [`P2P_DATA_W - 1 : 0] p2p_cfg_rrsp_data , // o, `P2P_DATA_W
31
+ // input wire p2p_cfg_rrsp_ready, // i, 1
32
+ /* --------P2P Configuration Channel{end}-------- */
33
+
34
+ /* -------P2P Stream Channel{begin}-------- */
35
+ /* p2p_req head
36
+ * | 127 | 126:64 | 63:32 | 31:13 | 12:0 |
37
+ * | is_wr | Reserved | addr | Reserved | byte_len |
38
+ */
39
+ input wire p2p_mem_req_valid, // i, 1
40
+ input wire p2p_mem_req_last , // i, 1
41
+ input wire [`P2P_DATA_W - 1 : 0] p2p_mem_req_data , // i, `P2P_DATA_W
42
+ input wire [`P2P_HEAD_W - 1 : 0] p2p_mem_req_head , // i, `P2P_HEAD_W
43
+ output wire p2p_mem_req_ready, // o, 1
44
+ /* -------P2P Stream Channel{end}-------- */
45
+
46
+ /* --------p2p forward down channel{begin}-------- */
47
+ /* *_head, valid only in first beat of a packet
48
+ * | Reserved |dst_dev| src_dev | Reserved | Byte length |
49
+ * | 63:- | 47:40 | 39:32 | 31:16 | 15:0 |
50
+ */
51
+ output wire p2p_down_valid, // o, 1
52
+ output wire p2p_down_last , // o, 1
53
+ output wire [`P2P_DATA_W - 1 : 0] p2p_down_data , // o, `P2P_DATA_W
54
+ output wire [`P2P_DHEAD_W - 1 : 0] p2p_down_head , // o, `P2P_DHEAD_W
55
+ input wire p2p_down_ready // i, 1
56
+ /* --------p2p forward down channel{end}-------- */
57
+
58
+ `ifdef PCIEI_APB_DBG
59
+ /* -------APB reated signal{begin}------- */
60
+ ,input wire [(2*`QUEUE_NUM+3)*`SRAM_RW_DATA_W-1:0] rw_data // i, (2*`QUEUE_NUM+3)*`SRAM_RW_DATA_W
61
+ ,input wire [31:0] dbg_sel // i, 32
62
+ ,output wire [31:0] dbg_bus // o, 32
63
+ /* -------APB reated signal{end}------- */
64
+ `endif
65
+ );
66
+
67
+ /* -------- Related to demux {begin}-------- */
68
+ /* p2p_req head
69
+ * | 127 | 126:64 | 63:32 | 31:13 | 12:0 |
70
+ * | is_wr | Reserved | addr | Reserved | byte_len |
71
+ */
72
+ wire st_reg_p2p_mem_req_valid;
73
+ wire st_reg_p2p_mem_req_last ;
74
+ wire [`P2P_HEAD_W - 1 : 0] st_reg_p2p_mem_req_head ;
75
+ wire [`P2P_DATA_W - 1 : 0] st_reg_p2p_mem_req_data ;
76
+ wire st_reg_p2p_mem_req_ready;
77
+
78
+ wire [31:0] mem_addr;
79
+ wire [7 :0] nxt_chnl_sel;
80
+ /* -------- Related to demux {end}-------- */
81
+
82
+ wire p2p_mem_desc_req_valid, p2p_mem_pyld_req_valid, st0_p2p_pyld_req_valid;
83
+ wire p2p_mem_desc_req_last , p2p_mem_pyld_req_last , st0_p2p_pyld_req_last ;
84
+ wire [`P2P_HEAD_W-1:0] p2p_mem_desc_req_head , p2p_mem_pyld_req_head , st0_p2p_pyld_req_head ;
85
+ wire [`P2P_DATA_W-1:0] p2p_mem_desc_req_data , p2p_mem_pyld_req_data , st0_p2p_pyld_req_data ;
86
+ wire p2p_mem_desc_req_ready, p2p_mem_pyld_req_ready, st0_p2p_pyld_req_ready;
87
+
88
+ /* --------Next mem payload{begin}-------- */
89
+ wire nxt_valid;
90
+ wire [7:0] nxt_qnum ;
91
+ /* --------Next mem payload{end}-------- */
92
+
93
+ /* --------dropped queue{begin}-------- */
94
+ wire dropped_wen ;
95
+ wire [`QUEUE_NUM_LOG-1:0] dropped_qnum;
96
+ /* --------dropped queue{end}-------- */
97
+
98
+ /* --------p2p mem payload store{begin}-------- */
99
+ wire st_pyld_req_valid ;
100
+ wire st_pyld_req_last ;
101
+ wire [`MSG_BLEN_WIDTH-1:0] st_pyld_req_blen ;
102
+ wire [8 -1:0] st_pyld_req_qnum ;
103
+ wire [`P2P_DATA_W -1:0] st_pyld_req_data ;
104
+ wire st_pyld_req_ready ;
105
+ /* --------p2p mem payload store{begin}-------- */
106
+
107
+ /* --------allocated buffer address{begin}-------- */
108
+ wire pbuf_alloc_valid ;
109
+ wire pbuf_alloc_last ;
110
+ wire [`BUF_ADDR_WIDTH-1:0] pbuf_alloc_buf_addr;
111
+ wire [8 -1:0] pbuf_alloc_qnum ;
112
+ wire pbuf_alloc_ready ;
113
+ /* --------allocated buffer address{end}-------- */
114
+
115
+ /* --------Info from queue struct{begin}-------- */
116
+ wire qstruct_valid ;
117
+ wire qstruct_last ;
118
+ wire [`QUEUE_CONTEXT_WIDTH-1:0] qstruct_head_ctx ;
119
+ wire [`QUEUE_DESC_WIDTH -1:0] qstruct_head_desc;
120
+ wire [`BUF_ADDR_WIDTH -1:0] qstruct_buf_addr ;
121
+ wire qstruct_ready ;
122
+ /* --------Info from queue struct{end}-------- */
123
+
124
+ /* --------Info from queue struct{begin}-------- */
125
+ wire st_qstruct_valid ;
126
+ wire st_qstruct_last ;
127
+ wire [`QUEUE_CONTEXT_WIDTH-1:0] st_qstruct_head_ctx ;
128
+ wire [`QUEUE_DESC_WIDTH -1:0] st_qstruct_head_desc;
129
+ wire [`BUF_ADDR_WIDTH -1:0] st_qstruct_buf_addr ;
130
+ wire st_qstruct_ready ;
131
+ /* --------Info from queue struct{end}-------- */
132
+
133
+ /* --------Ctrl Info to pyld_buf{begin}-------- */
134
+ wire pbuf_free_valid ;
135
+ wire pbuf_free_last ;
136
+ wire [`P2P_DHEAD_W -1:0] pbuf_free_head ;
137
+ wire [1:0] pbuf_free_buf_offset;
138
+ wire [`BUF_ADDR_WIDTH-1:0] pbuf_free_buf_addr ;
139
+ wire pbuf_free_ready ;
140
+ /* --------Ctrl Info to pyld_buf{begin}-------- */
141
+
142
+ /* --------Ctrl Info to pyld_buf{begin}-------- */
143
+ wire st_pbuf_free_valid ;
144
+ wire st_pbuf_free_last ;
145
+ wire [`P2P_DHEAD_W -1:0] st_pbuf_free_head ;
146
+ wire [1:0] st_pbuf_free_buf_offset;
147
+ wire [`BUF_ADDR_WIDTH-1:0] st_pbuf_free_buf_addr ;
148
+ wire st_pbuf_free_ready ;
149
+ /* --------Ctrl Info to pyld_buf{begin}-------- */
150
+
151
+ /* --------p2p mem payload out{begin}-------- */
152
+ wire ft_pyld_req_valid;
153
+ wire ft_pyld_req_last ;
154
+ wire [`P2P_DHEAD_W -1:0] ft_pyld_req_head ;
155
+ wire [`P2P_DATA_W -1:0] ft_pyld_req_data ;
156
+ wire ft_pyld_req_ready;
157
+ /* --------p2p mem payload out{end}-------- */
158
+
159
+ wire prp_init_end, pb_init_end;
160
+
161
+
162
+ `ifdef PCIEI_APB_DBG
163
+ /* -------APB reated signal{begin}------- */
164
+ wire [`SRAM_RW_DATA_W*2-1:0] pbuf_rw_data;
165
+ wire [(2*`QUEUE_NUM+1)*`SRAM_RW_DATA_W-1:0] qstruct_rw_data;
166
+
167
+ wire [`TGT_TOP_SIGNAL_W-1:0] dbg_signal_tgt_top;
168
+ wire [`TGT_RECV_SIGNAL_W-1:0] dbg_signal_tgt_recv;
169
+ wire [`TGT_QSTRUCT_SIGNAL_W-1:0] dbg_signal_tgt_qstruct;
170
+ wire [`TGT_PBUF_SIGNAL_W-1:0] dbg_signal_tgt_pbuf;
171
+ wire [`TGT_SEND_SIGNAL_W-1:0] dbg_signal_tgt_send;
172
+ /* -------APB reated signal{end}------- */
173
+ `endif
174
+
175
+ //-------------------------------------------------------------------------------------------------------------------
176
+
177
+ `ifdef PCIEI_APB_DBG
178
+ /* -------APB reated signal{begin}------- */
179
+ assign {pbuf_rw_data, qstruct_rw_data} = rw_data;
180
+
181
+ // Debug bus for p2p ini
182
+ assign dbg_bus = {dbg_signal_tgt_top, dbg_signal_tgt_recv,
183
+ dbg_signal_tgt_qstruct, dbg_signal_tgt_pbuf, dbg_signal_tgt_send} >> {dbg_sel, 5'd0};
184
+
185
+ // Debug signal for p2p ini top
186
+ assign dbg_signal_tgt_top = { // 2703
187
+
188
+ st_reg_p2p_mem_req_valid, st_reg_p2p_mem_req_last , st_reg_p2p_mem_req_head , st_reg_p2p_mem_req_data , st_reg_p2p_mem_req_ready, // 387
189
+ mem_addr, nxt_chnl_sel, // 40
190
+
191
+ p2p_mem_desc_req_valid, p2p_mem_pyld_req_valid, st0_p2p_pyld_req_valid,
192
+ p2p_mem_desc_req_last , p2p_mem_pyld_req_last , st0_p2p_pyld_req_last ,
193
+ p2p_mem_desc_req_head , p2p_mem_pyld_req_head , st0_p2p_pyld_req_head ,
194
+ p2p_mem_desc_req_data , p2p_mem_pyld_req_data , st0_p2p_pyld_req_data ,
195
+ p2p_mem_desc_req_ready, p2p_mem_pyld_req_ready, st0_p2p_pyld_req_ready, // 1161
196
+
197
+ nxt_valid, nxt_qnum , // 9
198
+ dropped_wen , dropped_qnum, // 5
199
+ st_pyld_req_valid, st_pyld_req_last , st_pyld_req_blen , st_pyld_req_qnum, st_pyld_req_data, st_pyld_req_ready, // 283
200
+ pbuf_alloc_valid, pbuf_alloc_last, pbuf_alloc_buf_addr, pbuf_alloc_qnum, pbuf_alloc_ready, // 21
201
+ qstruct_valid, qstruct_last, qstruct_head_ctx, qstruct_head_desc, qstruct_buf_addr, qstruct_ready, // 157
202
+ st_qstruct_valid, st_qstruct_last, st_qstruct_head_ctx, st_qstruct_head_desc, st_qstruct_buf_addr, st_qstruct_ready, // 157
203
+ pbuf_free_valid, pbuf_free_last, pbuf_free_head, pbuf_free_buf_offset, pbuf_free_buf_addr, pbuf_free_ready, // 79
204
+ st_pbuf_free_valid, st_pbuf_free_last, st_pbuf_free_head, st_pbuf_free_buf_offset, st_pbuf_free_buf_addr, st_pbuf_free_ready, // 79
205
+
206
+ ft_pyld_req_valid, ft_pyld_req_last , ft_pyld_req_head , ft_pyld_req_data , ft_pyld_req_ready, // 323
207
+ prp_init_end, pb_init_end // 2
208
+ };
209
+ /* -------APB reated signal{end}------- */
210
+ `endif
211
+
212
+ /* -------- Related to demux {begin}-------- */
213
+ st_reg #(
214
+ .TUSER_WIDTH ( `P2P_HEAD_W ),
215
+ .TDATA_WIDTH ( `P2P_DATA_W ),
216
+ .MODE ( 1 )
217
+ ) st_reg2demux (
218
+ .clk ( clk ), // i, 1
219
+ .rst_n ( rst_n ), // i, 1
220
+
221
+ /* -------input axis-like interface{begin}------- */
222
+ /* p2p_req head
223
+ * | 127 | 126:64 | 63:32 | 31:13 | 12:0 |
224
+ * | is_wr | Reserved | addr | Reserved | byte_len |
225
+ */
226
+ .axis_tvalid ( p2p_mem_req_valid ), // i, 1
227
+ .axis_tlast ( p2p_mem_req_last ), // i, 1
228
+ .axis_tuser ( p2p_mem_req_head ), // i, TUSER_WIDTH
229
+ .axis_tdata ( p2p_mem_req_data ), // i, TDATA_WIDTH
230
+ .axis_tready ( p2p_mem_req_ready ), // o, 1
231
+ /* -------input axis-like interface{end}------- */
232
+
233
+ /* -------output in_reg inteface{begin}------- */
234
+ /* p2p_req head
235
+ * | 127 | 126:64 | 63:32 | 31:13 | 12:0 |
236
+ * | is_wr | Reserved | addr | Reserved | byte_len |
237
+ */
238
+ .axis_reg_tvalid ( st_reg_p2p_mem_req_valid ), // o, 1 // read valid from input register
239
+ .axis_reg_tlast ( st_reg_p2p_mem_req_last ), // o, 1
240
+ .axis_reg_tuser ( st_reg_p2p_mem_req_head ), // o, TUSER_WIDTH
241
+ .axis_reg_tdata ( st_reg_p2p_mem_req_data ), // o, TDATA_WIDTH
242
+ .axis_reg_tready ( st_reg_p2p_mem_req_ready ) // i, 1
243
+ /* -------output in_reg inteface{end}------- */
244
+ );
245
+
246
+ assign mem_addr = p2p_mem_req_head[63:32];
247
+ assign nxt_chnl_sel = p2p_mem_req_valid ? (mem_addr[13:12] == 2'b11) : 0;
248
+ st_demux #(
249
+ .CHNL_NUM ( 2 ), // number of slave signals to arbit
250
+ .CHNL_NUM_LOG ( 1 ),
251
+ .TUSER_WIDTH ( `P2P_HEAD_W ),
252
+ .TDATA_WIDTH ( `P2P_DATA_W )
253
+ ) tgt_mem_demux (
254
+ .clk ( clk ), // i, 1
255
+ .rst_n ( rst_n ), // i, 1
256
+
257
+ .nxt_chnl_vld ( p2p_mem_req_valid ), // i, 1
258
+ .nxt_chnl_sel ( nxt_chnl_sel ), // i, 8
259
+
260
+ /* --------P2P Memory Access Channel In{begin}-------- */
261
+ /* p2p_req head
262
+ * | 127 | 126:64 | 63:32 | 31:13 | 12:0 |
263
+ * | is_wr | Reserved | addr | Reserved | byte_len |
264
+ */
265
+ .s_axis_demux_valid ( st_reg_p2p_mem_req_valid ), // i, 1
266
+ .s_axis_demux_last ( st_reg_p2p_mem_req_last ), // i, 1
267
+ .s_axis_demux_head ( st_reg_p2p_mem_req_head ), // i, `P2P_HEAD_W
268
+ .s_axis_demux_data ( st_reg_p2p_mem_req_data ), // i, `P2P_DATA_W
269
+ .s_axis_demux_ready ( st_reg_p2p_mem_req_ready ), // o, 1
270
+ /* --------P2P Memory Access Channel In{end}-------- */
271
+
272
+ /* --------P2P Memory Access Channel Out{begin}-------- */
273
+ /* p2p_req head
274
+ * | 127 | 126:64 | 63:32 | 31:13 | 12:0 |
275
+ * | is_wr | Reserved | addr | Reserved | byte_len |
276
+ */
277
+ .m_axis_demux_valid ( {p2p_mem_desc_req_valid, p2p_mem_pyld_req_valid} ), // o, 2 * 1
278
+ .m_axis_demux_last ( {p2p_mem_desc_req_last , p2p_mem_pyld_req_last } ), // o, 2 * 1
279
+ .m_axis_demux_head ( {p2p_mem_desc_req_head , p2p_mem_pyld_req_head } ), // o, 2 * `P2P_HEAD_W
280
+ .m_axis_demux_data ( {p2p_mem_desc_req_data , p2p_mem_pyld_req_data } ), // o, 2 * `P2P_DATA_W
281
+ .m_axis_demux_ready ( {p2p_mem_desc_req_ready, p2p_mem_pyld_req_ready} ) // i, 2 * 1
282
+ /* --------P2P Memory Access Channel Out{end}-------- */
283
+ );
284
+ /* -------- Related to demux {end}-------- */
285
+
286
+ /* -------- Payload receive procedure{begin}-------- */
287
+ st_reg #(
288
+ .TUSER_WIDTH ( `P2P_HEAD_W ),
289
+ .TDATA_WIDTH ( `P2P_DATA_W ),
290
+ .MODE ( 1 )
291
+ ) st_reg0 (
292
+ .clk ( clk ), // i, 1
293
+ .rst_n ( rst_n ), // i, 1
294
+
295
+ /* -------input axis-like interface{begin}------- */
296
+ /* p2p_req head
297
+ * | 127 | 126:64 | 63:32 | 31:13 | 12:0 |
298
+ * | is_wr | Reserved | addr | Reserved | byte_len |
299
+ */
300
+ .axis_tvalid ( p2p_mem_pyld_req_valid ), // i, 1
301
+ .axis_tlast ( p2p_mem_pyld_req_last ), // i, 1
302
+ .axis_tuser ( p2p_mem_pyld_req_head ), // i, TUSER_WIDTH
303
+ .axis_tdata ( p2p_mem_pyld_req_data ), // i, TDATA_WIDTH
304
+ .axis_tready ( p2p_mem_pyld_req_ready ), // o, 1
305
+ /* -------input axis-like interface{end}------- */
306
+
307
+ /* -------output in_reg inteface{begin}------- */
308
+ /* p2p_req head
309
+ * | 127 | 126:64 | 63:32 | 31:13 | 12:0 |
310
+ * | is_wr | Reserved | addr | Reserved | byte_len |
311
+ */
312
+ .axis_reg_tvalid ( st0_p2p_pyld_req_valid ), // o, 1 // read valid from input register
313
+ .axis_reg_tlast ( st0_p2p_pyld_req_last ), // o, 1
314
+ .axis_reg_tuser ( st0_p2p_pyld_req_head ), // o, TUSER_WIDTH
315
+ .axis_reg_tdata ( st0_p2p_pyld_req_data ), // o, TDATA_WIDTH
316
+ .axis_reg_tready ( st0_p2p_pyld_req_ready ) // i, 1
317
+ /* -------output in_reg inteface{end}------- */
318
+ );
319
+
320
+ assign nxt_valid = p2p_mem_pyld_req_valid;
321
+ assign nxt_qnum = (p2p_mem_pyld_req_head[63:32] >> 14) & 4'hf;
322
+ tgt_pyld_recv_proc #(
323
+
324
+ ) tgt_pyld_recv_proc (
325
+
326
+ .clk ( clk ), // i, 1
327
+ .rst_n ( rst_n ), // i, 1
328
+ .init_end ( prp_init_end ), // o, 1
329
+
330
+ /* --------Next mem payload{begin}-------- */
331
+ .nxt_vaild ( nxt_valid ), // i, 1
332
+ .nxt_qnum ( nxt_qnum ), // i, 8
333
+ /* --------Next mem payload{end}-------- */
334
+
335
+ /* --------p2p mem payload in{begin}-------- */
336
+ /* p2p_req head
337
+ * | 127 | 126:64 | 63:32 | 31:13 | 12:0 |
338
+ * | is_wr | Reserved | addr | Reserved | byte_len |
339
+ */
340
+ .st0_p2p_pyld_req_valid ( st0_p2p_pyld_req_valid ), // i, 1
341
+ .st0_p2p_pyld_req_last ( st0_p2p_pyld_req_last ), // i, 1
342
+ .st0_p2p_pyld_req_head ( st0_p2p_pyld_req_head ), // i, `P2P_HEAD_W
343
+ .st0_p2p_pyld_req_data ( st0_p2p_pyld_req_data ), // i, `P2P_DATA_W
344
+ .st0_p2p_pyld_req_ready ( st0_p2p_pyld_req_ready ), // o, 1
345
+ /* --------p2p mem payload in{end}-------- */
346
+
347
+ /* --------p2p mem payload out{begin}-------- */
348
+ .st_pyld_req_valid ( st_pyld_req_valid ), // o, 1
349
+ .st_pyld_req_last ( st_pyld_req_last ), // o, 1
350
+ .st_pyld_req_blen ( st_pyld_req_blen ), // o, `MSG_BLEN_WIDTH
351
+ .st_pyld_req_qnum ( st_pyld_req_qnum ), // o, 8
352
+ .st_pyld_req_data ( st_pyld_req_data ), // o, `P2P_DATA_W
353
+ .st_pyld_req_ready ( st_pyld_req_ready ), // i, 1
354
+ /* --------p2p mem payload out{end}-------- */
355
+
356
+ /* --------dropped queue{begin}-------- */
357
+ .dropped_wen ( dropped_wen ), // i, 1
358
+ .dropped_qnum ( dropped_qnum ), // i, `QUEUE_NUM_LOG
359
+ .dropped_data ( 1'd0 ) // i, 1; we assume no dropped desc
360
+ /* --------dropped queue{end}-------- */
361
+
362
+ `ifdef PCIEI_APB_DBG
363
+ /* -------APB reated signal{begin}------- */
364
+ ,.dbg_signal ( dbg_signal_tgt_recv ) // o, `TGT_RECV_SIGNAL_W
365
+ /* -------APB reated signal{end}------- */
366
+ `endif
367
+ );
368
+ /* -------- Payload receive procedure{end}-------- */
369
+
370
+ tgt_queue_struct #(
371
+
372
+ ) tgt_queue_struct (
373
+
374
+ .clk ( clk ), // i, 1
375
+ .rst_n ( rst_n ), // i, 1
376
+
377
+ /* --------P2P Configuration Channel{begin}-------- */
378
+ /* p2p_req head
379
+ * | 127 | 126:64 | 63:32 | 31:13 | 12:0 |
380
+ * | is_wr | Reserved | addr | Reserved | byte_len |
381
+ */
382
+ .p2p_cfg_req_valid ( p2p_cfg_req_valid ), // i, 1
383
+ .p2p_cfg_req_last ( p2p_cfg_req_last ), // i, 1
384
+ .p2p_cfg_req_data ( p2p_cfg_req_data ), // i, `P2P_DATA_W
385
+ .p2p_cfg_req_head ( p2p_cfg_req_head ), // i, `P2P_HEAD_W
386
+ .p2p_cfg_req_ready ( p2p_cfg_req_ready ), // o, 1
387
+
388
+ // .p2p_cfg_rrsp_valid ( p2p_cfg_rrsp_valid ), // o, 1
389
+ // .p2p_cfg_rrsp_last ( p2p_cfg_rrsp_last ), // o, 1
390
+ // .p2p_cfg_rrsp_data ( p2p_cfg_rrsp_data ), // o, `P2P_DATA_W
391
+ // .p2p_cfg_rrsp_ready ( p2p_cfg_rrsp_ready ), // i, 1
392
+ /* --------P2P Configuration Channel{end}-------- */
393
+
394
+ /* --------p2p mem descriptor in{begin}-------- */
395
+ .p2p_mem_desc_req_valid ( p2p_mem_desc_req_valid ), // i, 1
396
+ .p2p_mem_desc_req_last ( p2p_mem_desc_req_last ), // i, 1
397
+ .p2p_mem_desc_req_data ( p2p_mem_desc_req_data ), // i, `P2P_DATA_W
398
+ .p2p_mem_desc_req_head ( p2p_mem_desc_req_head ), // i, `P2P_HEAD_W
399
+ .p2p_mem_desc_req_ready ( p2p_mem_desc_req_ready ), // o, 1
400
+ /* --------p2p mem descriptor in{end}-------- */
401
+
402
+ /* --------allocated buffer address{begin}-------- */
403
+ .pbuf_alloc_valid ( pbuf_alloc_valid ), // i, 1
404
+ .pbuf_alloc_last ( pbuf_alloc_last ), // i, 1
405
+ .pbuf_alloc_buf_addr ( pbuf_alloc_buf_addr ), // i, 32
406
+ .pbuf_alloc_qnum ( pbuf_alloc_qnum ), // i, 8
407
+ .pbuf_alloc_ready ( pbuf_alloc_ready ), // o, 1
408
+ /* --------allocated buffer address{end}-------- */
409
+
410
+ /* --------dropped queue{begin}-------- */
411
+ .dropped_wen ( dropped_wen ), // o, 1
412
+ .dropped_qnum ( dropped_qnum ), // o, `QUEUE_NUM_LOG
413
+ /* --------dropped queue{end}-------- */
414
+
415
+ /* --------queue struct output for send processing{begin}-------- */
416
+ /* st_qstruct_head_ctx : qcontext of prepared queue
417
+ * st_qstruct_head_desc: payload descriptor
418
+ * st_qstruct_buf_addr : allocated buffer base address in P2P pyld_buf,
419
+ * this is an array. A valid addr outputs when valid
420
+ * and ready assert at the same time.
421
+ * st_qstruct_last : assert when the last st_qstruct_buf_addr is asserted
422
+ */
423
+ .st_qstruct_valid ( qstruct_valid ), // o, 1
424
+ .st_qstruct_last ( qstruct_last ), // o, 1
425
+ .st_qstruct_head_ctx ( qstruct_head_ctx ), // o, `QUEUE_CONTEXT_WIDTH
426
+ .st_qstruct_head_desc ( qstruct_head_desc ), // o, `QUEUE_DESC_WIDTH
427
+ .st_qstruct_buf_addr ( qstruct_buf_addr ), // o, `BUF_ADDR_WIDTH
428
+ .st_qstruct_ready ( qstruct_ready ) // i, 1
429
+ /* --------queue struct output for send processing{end}-------- */
430
+
431
+ `ifdef PCIEI_APB_DBG
432
+ /* -------APB reated signal{begin}------- */
433
+ ,.rw_data ( qstruct_rw_data ) // i, (2*`QUEUE_NUM+1)*`SRAM_RW_DATA_W
434
+ ,.dbg_signal ( dbg_signal_tgt_qstruct ) // o, `TGT_QSTRUCT_SIGNAL_W
435
+ /* -------APB reated signal{end}------- */
436
+ `endif
437
+ );
438
+
439
+ st_reg #(
440
+ .TUSER_WIDTH ( `P2P_DHEAD_W ),
441
+ .TDATA_WIDTH ( `BUF_ADDR_WIDTH + 2 ),
442
+ .MODE ( 1 )
443
+ ) st_pbuf (
444
+ .clk ( clk ), // i, 1
445
+ .rst_n ( rst_n ), // i, 1
446
+
447
+ /* -------input axis-like interface{begin}------- */
448
+ .axis_tvalid ( pbuf_free_valid ), // i, 1
449
+ .axis_tlast ( pbuf_free_last ), // i, 1
450
+ .axis_tuser ( pbuf_free_head ), // i, TUSER_WIDTH
451
+ .axis_tdata ( {pbuf_free_buf_addr, pbuf_free_buf_offset} ), // i, TDATA_WIDTH
452
+ .axis_tready ( pbuf_free_ready ), // o, 1
453
+ /* -------input axis-like interface{end}------- */
454
+
455
+ /* -------output in_reg inteface{begin}------- */
456
+ .axis_reg_tvalid ( st_pbuf_free_valid ), // o, 1 // read valid from input register
457
+ .axis_reg_tlast ( st_pbuf_free_last ), // o, 1
458
+ .axis_reg_tuser ( st_pbuf_free_head ), // o, TUSER_WIDTH
459
+ .axis_reg_tdata ( {st_pbuf_free_buf_addr, st_pbuf_free_buf_offset} ), // o, TDATA_WIDTH
460
+ .axis_reg_tready ( st_pbuf_free_ready ) // i, 1
461
+ /* -------output in_reg inteface{end}------- */
462
+ );
463
+
464
+ tgt_pyld_buf #(
465
+
466
+ ) tgt_pyld_buf (
467
+
468
+ .clk ( clk ), // i, 1
469
+ .rst_n ( rst_n ), // i, 1
470
+ .init_end ( pb_init_end ), // o, 1
471
+
472
+ /* --------allocated buffer address{begin}-------- */
473
+ .pbuf_alloc_valid ( pbuf_alloc_valid ), // o, 1
474
+ .pbuf_alloc_last ( pbuf_alloc_last ), // o, 1
475
+ .pbuf_alloc_buf_addr ( pbuf_alloc_buf_addr ), // o, 32
476
+ .pbuf_alloc_qnum ( pbuf_alloc_qnum ), // o, 8
477
+ .pbuf_alloc_ready ( pbuf_alloc_ready ), // i, 1
478
+ /* --------allocated buffer address{end}-------- */
479
+
480
+ /* --------p2p mem payload in{begin}-------- */
481
+ .st_pyld_req_valid ( st_pyld_req_valid ), // i, 1
482
+ .st_pyld_req_last ( st_pyld_req_last ), // i, 1
483
+ .st_pyld_req_blen ( st_pyld_req_blen ), // i, `MSG_BLEN_WIDTH
484
+ .st_pyld_req_qnum ( st_pyld_req_qnum ), // i, 8
485
+ .st_pyld_req_data ( st_pyld_req_data ), // i, `P2P_DATA_W
486
+ .st_pyld_req_ready ( st_pyld_req_ready ), // o, 1
487
+ /* --------p2p mem payload in{end}-------- */
488
+
489
+ /* --------Ctrl Info to pyld_buf{begin}-------- */
490
+ .pbuf_free_valid ( st_pbuf_free_valid ), // i, 1
491
+ .pbuf_free_last ( st_pbuf_free_last ), // i, 1
492
+ .pbuf_free_head ( st_pbuf_free_head ), // i, `P2P_DHEAD_W
493
+ .pbuf_free_buf_offset ( st_pbuf_free_buf_offset ), // i, 2
494
+ .pbuf_free_buf_addr ( st_pbuf_free_buf_addr ), // i, `BUF_ADDR_WIDTH
495
+ .pbuf_free_ready ( st_pbuf_free_ready ), // o, 1
496
+ /* --------Ctrl Info to pyld_buf{begin}-------- */
497
+
498
+ /* --------p2p mem payload out{begin}-------- */
499
+ .ft_pyld_req_valid ( ft_pyld_req_valid ), // o, 1
500
+ .ft_pyld_req_last ( ft_pyld_req_last ), // o, 1
501
+ .ft_pyld_req_head ( ft_pyld_req_head ), // o, `P2P_DHEAD_W
502
+ .ft_pyld_req_data ( ft_pyld_req_data ), // o, `P2P_DATA_W
503
+ .ft_pyld_req_ready ( ft_pyld_req_ready ) // i, 1
504
+ /* --------p2p mem payload out{end}-------- */
505
+
506
+ `ifdef PCIEI_APB_DBG
507
+ /* -------APB reated signal{begin}------- */
508
+ ,.rw_data ( pbuf_rw_data ) // i, `SRAM_RW_DATA_W*2
509
+ ,.dbg_signal ( dbg_signal_tgt_pbuf ) // o, `TGT_PBUF_SIGNAL_W
510
+ /* -------APB reated signal{end}------- */
511
+ `endif
512
+
513
+ );
514
+
515
+ st_reg #(
516
+ .TUSER_WIDTH ( `QUEUE_CONTEXT_WIDTH + `QUEUE_DESC_WIDTH ),
517
+ .TDATA_WIDTH ( `BUF_ADDR_WIDTH ),
518
+ .MODE ( 1 )
519
+ ) st_qstruct (
520
+ .clk ( clk ), // i, 1
521
+ .rst_n ( rst_n ), // i, 1
522
+
523
+ /* -------input axis-like interface{begin}------- */
524
+ .axis_tvalid ( qstruct_valid ), // i, 1
525
+ .axis_tlast ( qstruct_last ), // i, 1
526
+ .axis_tuser ( {qstruct_head_ctx, qstruct_head_desc} ), // i, TUSER_WIDTH
527
+ .axis_tdata ( qstruct_buf_addr ), // i, TDATA_WIDTH
528
+ .axis_tready ( qstruct_ready ), // o, 1
529
+ /* -------input axis-like interface{end}------- */
530
+
531
+ /* -------output in_reg inteface{begin}------- */
532
+ .axis_reg_tvalid ( st_qstruct_valid ), // o, 1 // read valid from input register
533
+ .axis_reg_tlast ( st_qstruct_last ), // o, 1
534
+ .axis_reg_tuser ( {st_qstruct_head_ctx, st_qstruct_head_desc} ), // o, TUSER_WIDTH
535
+ .axis_reg_tdata ( st_qstruct_buf_addr ), // o, TDATA_WIDTH
536
+ .axis_reg_tready ( st_qstruct_ready ) // i, 1
537
+ /* -------output in_reg inteface{end}------- */
538
+ );
539
+
540
+ tgt_pyld_send_proc #(
541
+
542
+ ) tgt_pyld_send_proc (
543
+
544
+ .clk ( clk ), // i, 1
545
+ .rst_n ( rst_n ), // i, 1
546
+
547
+ /* --------Info from queue struct{begin}-------- */
548
+ /* qstruct_head_ctx : qcontext of prepared queue
549
+ * qstruct_head_desc: payload descriptor
550
+ * qstruct_buf_addr : allocated buffer base address in P2P pyld_buf,
551
+ * this is an array. A valid addr outputs when valid
552
+ * and ready assert at the same time.
553
+ * qstruct_last : assert when the last qstruct_buf_addr is asserted
554
+ */
555
+ .qstruct_valid ( st_qstruct_valid ), // i, 1
556
+ .qstruct_last ( st_qstruct_last ), // i, 1
557
+ .qstruct_head_ctx ( st_qstruct_head_ctx ), // i, `QUEUE_CONTEXT_WIDTH
558
+ .qstruct_head_desc ( st_qstruct_head_desc ), // i, `QUEUE_DESC_WIDTH
559
+ .qstruct_buf_addr ( st_qstruct_buf_addr ), // i, `BUF_ADDR_WIDTH
560
+ .qstruct_ready ( st_qstruct_ready ), // o, 1
561
+ /* --------Info from queue struct{end}-------- */
562
+
563
+ /* --------Ctrl Info to pyld_buf{begin}-------- */
564
+ .pbuf_free_valid ( pbuf_free_valid ), // o, 1
565
+ .pbuf_free_last ( pbuf_free_last ), // o, 1
566
+ .pbuf_free_head ( pbuf_free_head ), // o, `P2P_DHEAD_W
567
+ .pbuf_free_buf_offset ( pbuf_free_buf_offset ), // o, 2
568
+ .pbuf_free_buf_addr ( pbuf_free_buf_addr ), // o, `BUF_ADDR_WIDTH
569
+ .pbuf_free_ready ( pbuf_free_ready ), // i, 1
570
+ /* --------Ctrl Info to pyld_buf{begin}-------- */
571
+
572
+ /* --------p2p mem payload out{begin}-------- */
573
+ .ft_pyld_req_valid ( ft_pyld_req_valid ), // i, 1
574
+ .ft_pyld_req_last ( ft_pyld_req_last ), // i, 1
575
+ .ft_pyld_req_head ( ft_pyld_req_head ), // i, `P2P_DHEAD_W
576
+ .ft_pyld_req_data ( ft_pyld_req_data ), // i, `P2P_DATA_W
577
+ .ft_pyld_req_ready ( ft_pyld_req_ready ), // o, 1
578
+ /* --------p2p mem payload out{end}-------- */
579
+
580
+ /* --------p2p forward down channel{begin}-------- */
581
+ /* *_head, valid only in first beat of a packet
582
+ * | Reserved |dst_dev| src_dev | Reserved | Byte length |
583
+ * | 63:- | 47:40 | 39:32 | 31:16 | 15:0 |
584
+ */
585
+ .st_p2p_down_valid ( p2p_down_valid ), // o, 1
586
+ .st_p2p_down_last ( p2p_down_last ), // o, 1
587
+ .st_p2p_down_data ( p2p_down_data ), // o, `P2P_DATA_W
588
+ .st_p2p_down_head ( p2p_down_head ), // o, `P2P_DHEAD_W
589
+ .st_p2p_down_ready ( p2p_down_ready ) // i, 1
590
+ /* --------p2p forward down channel{end}-------- */
591
+
592
+ `ifdef PCIEI_APB_DBG
593
+ /* -------APB reated signal{begin}------- */
594
+ ,.dbg_signal ( dbg_signal_tgt_send ) // o, `TGT_SEND_SIGNAL_W
595
+ /* -------APB reated signal{end}------- */
596
+ `endif
597
+ );
598
+
599
+ assign init_end = prp_init_end & pb_init_end;
600
+
601
+ endmodule // p2p_target
ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/P2P/tgt_desc_queue.v ADDED
@@ -0,0 +1,504 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ `timescale 1ns / 100ps
2
+ //*************************************************************************
3
+ // > File : tgt_desc_queue.v
4
+ // > Author : Kangning
5
+ // > Date : 2022-08-31
6
+ // > Note : descriptor queue, includes descriptor queue && pbuf allocated
7
+ // > address.
8
+ //*************************************************************************
9
+
10
+ module tgt_desc_queue #(
11
+
12
+ ) (
13
+
14
+ input wire clk , // i, 1
15
+ input wire rst_n, // i, 1
16
+
17
+ /* --------p2p mem descriptor in{begin}-------- */
18
+ /* p2p_req head. We just write mem descriptor space, and the byte_len is 8 byte aligned
19
+ * | 127 | 126:64 | 63:32 | 31:13 | 12:0 |
20
+ * | is_wr | Reserved | addr | Reserved | byte_len |
21
+ */
22
+ input wire p2p_mem_desc_req_valid, // i, 1
23
+ input wire p2p_mem_desc_req_last , // i, 1
24
+ input wire [`P2P_HEAD_W-1:0] p2p_mem_desc_req_head , // i, `P2P_HEAD_W
25
+ input wire [`P2P_DATA_W-1:0] p2p_mem_desc_req_data , // i, `P2P_DATA_W
26
+ output wire p2p_mem_desc_req_ready, // o, 1
27
+ /* --------p2p mem descriptor in{end}-------- */
28
+
29
+ /* --------allocated buffer address{begin}-------- */
30
+ input wire pbuf_alloc_valid , // i, 1
31
+ input wire pbuf_alloc_last , // i, 1
32
+ input wire [`BUF_ADDR_WIDTH-1:0] pbuf_alloc_buf_addr, // i, `BUF_ADDR_WIDTH
33
+ input wire [8 -1:0] pbuf_alloc_qnum , // i, 8
34
+ output wire pbuf_alloc_ready , // o, 1 ; assume it always asserts
35
+ /* --------allocated buffer address{end}-------- */
36
+
37
+ /* --------dropped queue{begin}-------- */
38
+ output wire dropped_wen , // o, 1
39
+ output wire [`QUEUE_NUM_LOG-1:0] dropped_qnum, // o, `QUEUE_NUM_LOG
40
+ /* --------dropped queue{end}-------- */
41
+
42
+ /* --------queue struct output for send processing{begin}-------- */
43
+ /* desc_out_head_desc: payload descriptor
44
+ * desc_out_buf_addr : allocated buffer base address in P2P pyld_buf,
45
+ * this is an array. A valid addr outputs when valid
46
+ * and ready assert at the same time.
47
+ * desc_out_last : assert when the last desc_out_buf_addr is asserted
48
+ */
49
+ output wire desc_out_valid , // o, 1
50
+ output wire desc_out_last , // o, 1
51
+ output reg [`QUEUE_DESC_WIDTH-1:0] desc_out_head_desc, // o, `QUEUE_DESC_WIDTH
52
+ output wire [`QUEUE_NUM_LOG -1:0] desc_out_head_qnum, // o, `QUEUE_NUM_LOG
53
+ output wire [`BUF_ADDR_WIDTH -1:0] desc_out_buf_addr , // o, `BUF_ADDR_WIDTH
54
+ input wire desc_out_ready // i, 1
55
+ /* --------queue struct output for send processing{end}-------- */
56
+
57
+ `ifdef PCIEI_APB_DBG
58
+ /* -------APB reated signal{begin}------- */
59
+ ,input wire [2*`QUEUE_NUM*`SRAM_RW_DATA_W-1:0] rw_data // i, 2*`QUEUE_NUM*`SRAM_RW_DATA_W
60
+ ,output wire [`DESC_QUEUE_SIGNAL_W-1:0] dbg_signal // o, `DESC_QUEUE_SIGNAL_W
61
+ /* -------APB reated signal{end}------- */
62
+ `endif
63
+ );
64
+
65
+ /* --------p2p mem descriptor write{begin}-------- */
66
+ wire [`QUEUE_DESC_WIDTH-1:0] desc_data;
67
+ wire [`QUEUE_NUM_LOG -1:0] desc_qnum;
68
+ /* --------p2p mem descriptor write{end}-------- */
69
+
70
+ /* --------queue descriptor{begin}-------- */
71
+ wire qdesc_0_wen [`QUEUE_NUM-1:0];
72
+ wire [`QUEUE_DESC_WIDTH-1:0] qdesc_0_din [`QUEUE_NUM-1:0];
73
+ wire qdesc_0_ren [`QUEUE_NUM-1:0];
74
+ wire [`QUEUE_DESC_WIDTH-1:0] qdesc_0_dout [`QUEUE_NUM-1:0];
75
+ wire qdesc_0_full [`QUEUE_NUM-1:0];
76
+ wire qdesc_0_empty[`QUEUE_NUM-1:0];
77
+
78
+ // queue receive matching
79
+ wire [`MSG_BLEN_WIDTH-1:0] byte_len[`QUEUE_NUM-1:0];
80
+ reg [`MSG_BLEN_WIDTH:0] byte_cnt[`QUEUE_NUM-1:0]; // This reg may exceed the length of byte_len
81
+ wire is_recved[`QUEUE_NUM-1:0];
82
+
83
+ wire qdesc_1_wen [`QUEUE_NUM-1:0];
84
+ wire [`QUEUE_DESC_WIDTH-1:0] qdesc_1_din [`QUEUE_NUM-1:0];
85
+ wire qdesc_1_ren [`QUEUE_NUM-1:0];
86
+ wire [`QUEUE_DESC_WIDTH-1:0] qdesc_1_dout [`QUEUE_NUM-1:0];
87
+ wire qdesc_1_full [`QUEUE_NUM-1:0];
88
+ wire qdesc_1_empty[`QUEUE_NUM-1:0];
89
+
90
+ wire alloced_buf_wen [`QUEUE_NUM-1:0];
91
+ wire [`BUF_ADDR_WIDTH-1:0] alloced_buf_din [`QUEUE_NUM-1:0];
92
+ wire alloced_buf_ren [`QUEUE_NUM-1:0];
93
+ wire [`BUF_ADDR_WIDTH-1:0] alloced_buf_dout [`QUEUE_NUM-1:0];
94
+ wire alloced_buf_full [`QUEUE_NUM-1:0];
95
+ wire alloced_buf_empty[`QUEUE_NUM-1:0];
96
+
97
+ wire is_que_rdy[`QUEUE_NUM-1:0];
98
+
99
+ wire is_match_succ;
100
+ wire [`QUEUE_NUM_LOG-1:0] match_qnum; // Used only when is_nxt_desc_que_out
101
+ reg [`QUEUE_NUM_LOG-1:0] match_qnum_reg; // It is used only in DESC_QUE_OUT state
102
+ reg [`QUEUE_NUM_LOG-1:0] pri_chnl; // The prior selected channel
103
+ /* --------queue descriptor{end}-------- */
104
+
105
+ /* --------queue struct output FSM{begin}-------- */
106
+ localparam IDLE = 2'b01,
107
+ DESC_QUE_OUT = 2'b10;
108
+
109
+ reg [1:0] nxt_state;
110
+ reg [1:0] cur_state;
111
+
112
+ wire is_idle, is_desc_que_out;
113
+ wire is_nxt_desc_que_out;
114
+
115
+ reg [`MSG_BLEN_WIDTH-1:0] desc_out_byte_left;
116
+ /* --------queue struct output FSM{end}-------- */
117
+
118
+ `ifdef PCIEI_APB_DBG
119
+ /* -------APB reated signal{begin}------- */
120
+ wire [2*`QUEUE_NUM-1:0] desc_que_rtsel, alloced_buf_rtsel;
121
+ wire [2*`QUEUE_NUM-1:0] desc_que_wtsel, alloced_buf_wtsel;
122
+ wire [2*`QUEUE_NUM-1:0] desc_que_ptsel, alloced_buf_ptsel;
123
+ wire [1*`QUEUE_NUM-1:0] desc_que_vg , alloced_buf_vg ;
124
+ wire [1*`QUEUE_NUM-1:0] desc_que_vs , alloced_buf_vs ;
125
+ wire [2-1:0] qcontext_rtsel;
126
+ wire [2-1:0] qcontext_wtsel;
127
+ wire [2-1:0] qcontext_ptsel;
128
+ wire [1-1:0] qcontext_vg ;
129
+ wire [1-1:0] qcontext_vs ;
130
+ /* -------APB reated signal{end}------- */
131
+ `endif
132
+
133
+ //---------------------------------------------------------------------------------------------------------------------------
134
+
135
+ `ifdef PCIEI_APB_DBG
136
+ /* -------APB reated signal{begin}------- */
137
+ assign {
138
+ desc_que_rtsel ,
139
+ desc_que_wtsel ,
140
+ desc_que_ptsel ,
141
+ desc_que_vg ,
142
+ desc_que_vs ,
143
+ alloced_buf_rtsel,
144
+ alloced_buf_wtsel,
145
+ alloced_buf_ptsel,
146
+ alloced_buf_vg ,
147
+ alloced_buf_vs
148
+ } = rw_data;
149
+
150
+ assign dbg_signal = { // 6312
151
+
152
+ desc_data, desc_qnum, // 84
153
+
154
+ qdesc_0_wen [0 ], qdesc_0_wen [1 ], qdesc_0_wen [2 ], qdesc_0_wen [3 ],
155
+ qdesc_0_wen [4 ], qdesc_0_wen [5 ], qdesc_0_wen [6 ], qdesc_0_wen [7 ],
156
+ qdesc_0_wen [8 ], qdesc_0_wen [9 ], qdesc_0_wen [10], qdesc_0_wen [11],
157
+ qdesc_0_wen [12], qdesc_0_wen [13], qdesc_0_wen [14], qdesc_0_wen [15],
158
+ qdesc_0_din [0 ], qdesc_0_din [1 ], qdesc_0_din [2 ], qdesc_0_din [3 ],
159
+ qdesc_0_din [4 ], qdesc_0_din [5 ], qdesc_0_din [6 ], qdesc_0_din [7 ],
160
+ qdesc_0_din [8 ], qdesc_0_din [9 ], qdesc_0_din [10], qdesc_0_din [11],
161
+ qdesc_0_din [12], qdesc_0_din [13], qdesc_0_din [14], qdesc_0_din [15],
162
+ qdesc_0_ren [0 ], qdesc_0_ren [1 ], qdesc_0_ren [2 ], qdesc_0_ren [3 ],
163
+ qdesc_0_ren [4 ], qdesc_0_ren [5 ], qdesc_0_ren [6 ], qdesc_0_ren [7 ],
164
+ qdesc_0_ren [8 ], qdesc_0_ren [9 ], qdesc_0_ren [10], qdesc_0_ren [11],
165
+ qdesc_0_ren [12], qdesc_0_ren [13], qdesc_0_ren [14], qdesc_0_ren [15],
166
+ qdesc_0_dout [0 ], qdesc_0_dout [1 ], qdesc_0_dout [2 ], qdesc_0_dout [3 ],
167
+ qdesc_0_dout [4 ], qdesc_0_dout [5 ], qdesc_0_dout [6 ], qdesc_0_dout [7 ],
168
+ qdesc_0_dout [8 ], qdesc_0_dout [9 ], qdesc_0_dout [10], qdesc_0_dout [11],
169
+ qdesc_0_dout [12], qdesc_0_dout [13], qdesc_0_dout [14], qdesc_0_dout [15],
170
+ qdesc_0_full [0 ], qdesc_0_full [1 ], qdesc_0_full [2 ], qdesc_0_full [3 ],
171
+ qdesc_0_full [4 ], qdesc_0_full [5 ], qdesc_0_full [6 ], qdesc_0_full [7 ],
172
+ qdesc_0_full [8 ], qdesc_0_full [9 ], qdesc_0_full [10], qdesc_0_full [11],
173
+ qdesc_0_full [12], qdesc_0_full [13], qdesc_0_full [14], qdesc_0_full [15],
174
+ qdesc_0_empty[0 ], qdesc_0_empty[1 ], qdesc_0_empty[2 ], qdesc_0_empty[3 ],
175
+ qdesc_0_empty[4 ], qdesc_0_empty[5 ], qdesc_0_empty[6 ], qdesc_0_empty[7 ],
176
+ qdesc_0_empty[8 ], qdesc_0_empty[9 ], qdesc_0_empty[10], qdesc_0_empty[11],
177
+ qdesc_0_empty[12], qdesc_0_empty[13], qdesc_0_empty[14], qdesc_0_empty[15], // 2624
178
+
179
+ byte_len[0 ], byte_len[1 ], byte_len[2 ], byte_len[3 ],
180
+ byte_len[4 ], byte_len[5 ], byte_len[6 ], byte_len[7 ],
181
+ byte_len[8 ], byte_len[9 ], byte_len[10], byte_len[11],
182
+ byte_len[12], byte_len[13], byte_len[14], byte_len[15],
183
+ byte_cnt[0 ], byte_cnt[1 ], byte_cnt[2 ], byte_cnt[3 ],
184
+ byte_cnt[4 ], byte_cnt[5 ], byte_cnt[6 ], byte_cnt[7 ],
185
+ byte_cnt[8 ], byte_cnt[9 ], byte_cnt[10], byte_cnt[11],
186
+ byte_cnt[12], byte_cnt[13], byte_cnt[14], byte_cnt[15], // 528
187
+
188
+ is_recved[0], is_recved[0], is_recved[0], is_recved[0],
189
+ is_recved[0], is_recved[0], is_recved[0], is_recved[0],
190
+ is_recved[0], is_recved[0], is_recved[0], is_recved[0],
191
+ is_recved[0], is_recved[0], is_recved[0], is_recved[0], // 16
192
+
193
+ qdesc_1_wen [0 ], qdesc_1_wen [1 ], qdesc_1_wen [2 ], qdesc_1_wen [3 ],
194
+ qdesc_1_wen [4 ], qdesc_1_wen [5 ], qdesc_1_wen [6 ], qdesc_1_wen [7 ],
195
+ qdesc_1_wen [8 ], qdesc_1_wen [9 ], qdesc_1_wen [10], qdesc_1_wen [11],
196
+ qdesc_1_wen [12], qdesc_1_wen [13], qdesc_1_wen [14], qdesc_1_wen [15],
197
+ qdesc_1_din [0 ], qdesc_1_din [1 ], qdesc_1_din [2 ], qdesc_1_din [3 ],
198
+ qdesc_1_din [4 ], qdesc_1_din [5 ], qdesc_1_din [6 ], qdesc_1_din [7 ],
199
+ qdesc_1_din [8 ], qdesc_1_din [9 ], qdesc_1_din [10], qdesc_1_din [11],
200
+ qdesc_1_din [12], qdesc_1_din [13], qdesc_1_din [14], qdesc_1_din [15],
201
+ qdesc_1_ren [0 ], qdesc_1_ren [1 ], qdesc_1_ren [2 ], qdesc_1_ren [3 ],
202
+ qdesc_1_ren [4 ], qdesc_1_ren [5 ], qdesc_1_ren [6 ], qdesc_1_ren [7 ],
203
+ qdesc_1_ren [8 ], qdesc_1_ren [9 ], qdesc_1_ren [10], qdesc_1_ren [11],
204
+ qdesc_1_ren [12], qdesc_1_ren [13], qdesc_1_ren [14], qdesc_1_ren [15],
205
+ qdesc_1_dout [0 ], qdesc_1_dout [1 ], qdesc_1_dout [2 ], qdesc_1_dout [3 ],
206
+ qdesc_1_dout [4 ], qdesc_1_dout [5 ], qdesc_1_dout [6 ], qdesc_1_dout [7 ],
207
+ qdesc_1_dout [8 ], qdesc_1_dout [9 ], qdesc_1_dout [10], qdesc_1_dout [11],
208
+ qdesc_1_dout [12], qdesc_1_dout [13], qdesc_1_dout [14], qdesc_1_dout [15],
209
+ qdesc_1_full [0 ], qdesc_1_full [1 ], qdesc_1_full [2 ], qdesc_1_full [3 ],
210
+ qdesc_1_full [4 ], qdesc_1_full [5 ], qdesc_1_full [6 ], qdesc_1_full [7 ],
211
+ qdesc_1_full [8 ], qdesc_1_full [9 ], qdesc_1_full [10], qdesc_1_full [11],
212
+ qdesc_1_full [12], qdesc_1_full [13], qdesc_1_full [14], qdesc_1_full [15],
213
+ qdesc_1_empty[0 ], qdesc_1_empty[1 ], qdesc_1_empty[2 ], qdesc_1_empty[3 ],
214
+ qdesc_1_empty[4 ], qdesc_1_empty[5 ], qdesc_1_empty[6 ], qdesc_1_empty[7 ],
215
+ qdesc_1_empty[8 ], qdesc_1_empty[9 ], qdesc_1_empty[10], qdesc_1_empty[11],
216
+ qdesc_1_empty[12], qdesc_1_empty[13], qdesc_1_empty[14], qdesc_1_empty[15], // 2624
217
+
218
+ alloced_buf_wen [0 ], alloced_buf_wen [1 ], alloced_buf_wen [2 ], alloced_buf_wen [3 ],
219
+ alloced_buf_wen [4 ], alloced_buf_wen [5 ], alloced_buf_wen [6 ], alloced_buf_wen [7 ],
220
+ alloced_buf_wen [8 ], alloced_buf_wen [9 ], alloced_buf_wen [10], alloced_buf_wen [11],
221
+ alloced_buf_wen [12], alloced_buf_wen [13], alloced_buf_wen [14], alloced_buf_wen [15],
222
+ alloced_buf_din [0 ], alloced_buf_din [1 ], alloced_buf_din [2 ], alloced_buf_din [3 ],
223
+ alloced_buf_din [4 ], alloced_buf_din [5 ], alloced_buf_din [6 ], alloced_buf_din [7 ],
224
+ alloced_buf_din [8 ], alloced_buf_din [9 ], alloced_buf_din [10], alloced_buf_din [11],
225
+ alloced_buf_din [12], alloced_buf_din [13], alloced_buf_din [14], alloced_buf_din [15],
226
+ alloced_buf_ren [0 ], alloced_buf_ren [1 ], alloced_buf_ren [2 ], alloced_buf_ren [3 ],
227
+ alloced_buf_ren [4 ], alloced_buf_ren [5 ], alloced_buf_ren [6 ], alloced_buf_ren [7 ],
228
+ alloced_buf_ren [8 ], alloced_buf_ren [9 ], alloced_buf_ren [10], alloced_buf_ren [11],
229
+ alloced_buf_ren [12], alloced_buf_ren [13], alloced_buf_ren [14], alloced_buf_ren [15],
230
+ alloced_buf_dout [0 ], alloced_buf_dout [1 ], alloced_buf_dout [2 ], alloced_buf_dout [3 ],
231
+ alloced_buf_dout [4 ], alloced_buf_dout [5 ], alloced_buf_dout [6 ], alloced_buf_dout [7 ],
232
+ alloced_buf_dout [8 ], alloced_buf_dout [9 ], alloced_buf_dout [10], alloced_buf_dout [11],
233
+ alloced_buf_dout [12], alloced_buf_dout [13], alloced_buf_dout [14], alloced_buf_dout [15],
234
+ alloced_buf_full [0 ], alloced_buf_full [1 ], alloced_buf_full [2 ], alloced_buf_full [3 ],
235
+ alloced_buf_full [4 ], alloced_buf_full [5 ], alloced_buf_full [6 ], alloced_buf_full [7 ],
236
+ alloced_buf_full [8 ], alloced_buf_full [9 ], alloced_buf_full [10], alloced_buf_full [11],
237
+ alloced_buf_full [12], alloced_buf_full [13], alloced_buf_full [14], alloced_buf_full [15],
238
+ alloced_buf_empty[0 ], alloced_buf_empty[1 ], alloced_buf_empty[2 ], alloced_buf_empty[3 ],
239
+ alloced_buf_empty[4 ], alloced_buf_empty[5 ], alloced_buf_empty[6 ], alloced_buf_empty[7 ],
240
+ alloced_buf_empty[8 ], alloced_buf_empty[9 ], alloced_buf_empty[10], alloced_buf_empty[11],
241
+ alloced_buf_empty[12], alloced_buf_empty[13], alloced_buf_empty[14], alloced_buf_empty[15], // 384
242
+
243
+ is_que_rdy[0 ], is_que_rdy[1 ], is_que_rdy[2 ], is_que_rdy[3 ],
244
+ is_que_rdy[4 ], is_que_rdy[5 ], is_que_rdy[6 ], is_que_rdy[7 ],
245
+ is_que_rdy[8 ], is_que_rdy[9 ], is_que_rdy[10], is_que_rdy[11],
246
+ is_que_rdy[12], is_que_rdy[13], is_que_rdy[14], is_que_rdy[15], // 16
247
+
248
+ is_match_succ, match_qnum, match_qnum_reg, pri_chnl, // 13
249
+
250
+ nxt_state, cur_state, // 4
251
+ is_idle, is_desc_que_out, is_nxt_desc_que_out, // 3
252
+ desc_out_byte_left // 16
253
+ };
254
+ /* -------APB reated signal{end}------- */
255
+ `endif
256
+
257
+ /* --------queue descriptor{begin}-------- */
258
+ assign p2p_mem_desc_req_ready = !qdesc_0_full[desc_qnum];
259
+
260
+ genvar i;
261
+ generate
262
+ for (i = 0; i < `QUEUE_NUM; i = i + 1) begin: DESC_QUE // 16 pass
263
+
264
+ // -------------------Input descriptor queue------------------------------- //
265
+ pcieifc_sync_fifo #(
266
+ .DSIZE ( `QUEUE_DESC_WIDTH ), // 80
267
+ .ASIZE ( `PBUF_NUM_LOG - 1 ) // 9
268
+ ) desc_que_0 (
269
+ .clk ( clk ),
270
+ .rst_n ( rst_n ),
271
+ .clr ( 1'd0 ),
272
+
273
+ .wen ( qdesc_0_wen [i] ),
274
+ .din ( qdesc_0_din [i] ),
275
+
276
+ .ren ( qdesc_0_ren [i] ),
277
+ .dout ( qdesc_0_dout[i] ),
278
+
279
+ .full ( qdesc_0_full [i] ),
280
+ .empty ( qdesc_0_empty[i] )
281
+
282
+ `ifdef PCIEI_APB_DBG
283
+ ,.rtsel ( desc_que_rtsel[(i+1)*2-1:i*2] ) // i, 2
284
+ ,.wtsel ( desc_que_wtsel[(i+1)*2-1:i*2] ) // i, 2
285
+ ,.ptsel ( desc_que_ptsel[(i+1)*2-1:i*2] ) // i, 2
286
+ ,.vg ( desc_que_vg [i] ) // i, 1
287
+ ,.vs ( desc_que_vs [i] ) // i, 1
288
+ `endif
289
+ );
290
+ assign qdesc_0_wen[i] = (desc_qnum == i) & p2p_mem_desc_req_valid & p2p_mem_desc_req_ready;
291
+ assign qdesc_0_din[i] = qdesc_0_wen[i] ? desc_data : 0;
292
+
293
+ assign qdesc_0_ren[i] = is_recved[i] & !qdesc_1_full[i];
294
+ // ---------------------------------------------------------- //
295
+
296
+ // ---------------------receive matching-------------------------------- //
297
+ assign byte_len[i] = (qdesc_0_dout[i] >> 32) & 16'hFFFF;
298
+ always @(posedge clk, negedge rst_n) begin
299
+ if (~rst_n) begin
300
+ byte_cnt[i] <= `TD 0;
301
+ end
302
+ else if ((byte_cnt[i] >= byte_len[i]) & (!qdesc_1_full[i])) begin
303
+ byte_cnt[i] <= `TD 0;
304
+ end
305
+ else if (pbuf_alloc_valid & pbuf_alloc_ready) begin
306
+ byte_cnt[i] <= `TD byte_cnt[i] + ((pbuf_alloc_qnum == i) ? `PBUF_BLOCK_SZ : 0);
307
+ end
308
+ end
309
+
310
+ assign is_recved[i] = (byte_cnt[i] >= byte_len[i]) & !qdesc_0_empty[i];
311
+ // --------------------------------------------------------------------- //
312
+
313
+ // ---------------------Input descriptor queue {begin}-------------------------- //
314
+ pcieifc_sync_fifo #(
315
+ .DSIZE ( `QUEUE_DESC_WIDTH ), // 80
316
+ .ASIZE ( `PBUF_NUM_LOG - 1 ) // 9
317
+ ) desc_que_1 (
318
+ .clk ( clk ),
319
+ .rst_n ( rst_n ),
320
+ .clr ( 1'd0 ),
321
+
322
+ .wen ( qdesc_1_wen [i] ),
323
+ .din ( qdesc_1_din [i] ),
324
+
325
+ .ren ( qdesc_1_ren [i] ),
326
+ .dout ( qdesc_1_dout[i] ),
327
+
328
+ .full ( qdesc_1_full [i] ),
329
+ .empty ( qdesc_1_empty[i] )
330
+
331
+ `ifdef PCIEI_APB_DBG
332
+ ,.rtsel ( desc_que_rtsel[(i+1)*2-1:i*2] ) // i, 2
333
+ ,.wtsel ( desc_que_wtsel[(i+1)*2-1:i*2] ) // i, 2
334
+ ,.ptsel ( desc_que_ptsel[(i+1)*2-1:i*2] ) // i, 2
335
+ ,.vg ( desc_que_vg [i] ) // i, 1
336
+ ,.vs ( desc_que_vs [i] ) // i, 1
337
+ `endif
338
+ );
339
+ assign qdesc_1_wen[i] = qdesc_0_ren[i];
340
+ assign qdesc_1_din[i] = qdesc_0_dout[i];
341
+
342
+ assign qdesc_1_ren[i] = (match_qnum == i) & is_nxt_desc_que_out;
343
+ // ---------------------Input descriptor queue {end}-------------------------- //
344
+
345
+ pcieifc_sync_fifo #(
346
+ .DSIZE ( `BUF_ADDR_WIDTH ), // 10
347
+ .ASIZE ( `PBUF_NUM_LOG ) // 10
348
+ ) alloced_buf_list (
349
+ .clk ( clk ),
350
+ .rst_n ( rst_n ),
351
+ .clr ( 1'd0 ),
352
+
353
+ .wen ( alloced_buf_wen[i] ),
354
+ .din ( alloced_buf_din[i] ),
355
+
356
+ .ren ( alloced_buf_ren [i] ),
357
+ .dout ( alloced_buf_dout[i] ),
358
+
359
+ .full ( alloced_buf_full [i] ),
360
+ .empty ( alloced_buf_empty[i] )
361
+
362
+ `ifdef PCIEI_APB_DBG
363
+ ,.rtsel ( alloced_buf_rtsel[(i+1)*2-1:i*2] ) // i, 2
364
+ ,.wtsel ( alloced_buf_wtsel[(i+1)*2-1:i*2] ) // i, 2
365
+ ,.ptsel ( alloced_buf_ptsel[(i+1)*2-1:i*2] ) // i, 2
366
+ ,.vg ( alloced_buf_vg [i] ) // i, 1
367
+ ,.vs ( alloced_buf_vs [i] ) // i, 1
368
+ `endif
369
+ );
370
+ assign alloced_buf_wen[i] = (pbuf_alloc_qnum == i) & pbuf_alloc_valid;
371
+ assign alloced_buf_din[i] = pbuf_alloc_buf_addr;
372
+
373
+ assign alloced_buf_ren[i] = (match_qnum_reg == i) & is_desc_que_out & desc_out_valid & desc_out_ready;
374
+
375
+ assign is_que_rdy[i] = !qdesc_1_empty[i] & !alloced_buf_empty[i];
376
+
377
+ end
378
+ endgenerate
379
+
380
+ // -> input descriptor queue
381
+ assign desc_data = p2p_mem_desc_req_data[127:0];
382
+ assign desc_qnum = (p2p_mem_desc_req_head[63:32] & 18'h3FFFF) >> 14;
383
+
384
+ // input descriptor -> output descriptor queue
385
+ assign pbuf_alloc_ready = !alloced_buf_full[pbuf_alloc_qnum] & !qdesc_1_full[pbuf_alloc_qnum];
386
+
387
+ // output descriptor queue ->
388
+ generate
389
+ if (`QUEUE_NUM_LOG == 4) begin: QUEUE16 // 16 queue
390
+ assign is_match_succ = is_que_rdy[0 ] | is_que_rdy[1 ] | is_que_rdy[2 ] | is_que_rdy[3 ] |
391
+ is_que_rdy[4 ] | is_que_rdy[5 ] | is_que_rdy[6 ] | is_que_rdy[7 ] |
392
+ is_que_rdy[8 ] | is_que_rdy[9 ] | is_que_rdy[10] | is_que_rdy[11] |
393
+ is_que_rdy[12] | is_que_rdy[13] | is_que_rdy[14] | is_que_rdy[15];
394
+
395
+ assign match_qnum = is_que_rdy[(pri_chnl ) & 4'hF] ? (pri_chnl ) & 4'hF: is_que_rdy[(pri_chnl+4'd1 ) & 4'hF] ? (pri_chnl+4'd1 ) & 4'hF:
396
+ is_que_rdy[(pri_chnl+4'd2 ) & 4'hF] ? (pri_chnl+4'd2 ) & 4'hF: is_que_rdy[(pri_chnl+4'd3 ) & 4'hF] ? (pri_chnl+4'd3 ) & 4'hF:
397
+ is_que_rdy[(pri_chnl+4'd4 ) & 4'hF] ? (pri_chnl+4'd4 ) & 4'hF: is_que_rdy[(pri_chnl+4'd5 ) & 4'hF] ? (pri_chnl+4'd5 ) & 4'hF:
398
+ is_que_rdy[(pri_chnl+4'd6 ) & 4'hF] ? (pri_chnl+4'd6 ) & 4'hF: is_que_rdy[(pri_chnl+4'd7 ) & 4'hF] ? (pri_chnl+4'd7 ) & 4'hF:
399
+ is_que_rdy[(pri_chnl+4'd8 ) & 4'hF] ? (pri_chnl+4'd8 ) & 4'hF: is_que_rdy[(pri_chnl+4'd9 ) & 4'hF] ? (pri_chnl+4'd9 ) & 4'hF:
400
+ is_que_rdy[(pri_chnl+4'd10) & 4'hF] ? (pri_chnl+4'd10) & 4'hF: is_que_rdy[(pri_chnl+4'd11) & 4'hF] ? (pri_chnl+4'd11) & 4'hF:
401
+ is_que_rdy[(pri_chnl+4'd12) & 4'hF] ? (pri_chnl+4'd12) & 4'hF: is_que_rdy[(pri_chnl+4'd13) & 4'hF] ? (pri_chnl+4'd13) & 4'hF:
402
+ is_que_rdy[(pri_chnl+4'd14) & 4'hF] ? (pri_chnl+4'd14) & 4'hF: is_que_rdy[(pri_chnl+4'd15) & 4'hF] ? (pri_chnl+4'd15) & 4'hF: 0;
403
+ end
404
+ endgenerate
405
+ always @(posedge clk, negedge rst_n) begin
406
+ if (~rst_n) begin
407
+ match_qnum_reg <= `TD 0;
408
+ end
409
+ else if (is_match_succ & is_nxt_desc_que_out) begin
410
+ match_qnum_reg <= `TD match_qnum;
411
+ end
412
+ end
413
+
414
+ always @(posedge clk, negedge rst_n) begin
415
+ if (~rst_n) begin
416
+ pri_chnl <= `TD 0;
417
+ end
418
+ else if (is_match_succ & is_nxt_desc_que_out) begin
419
+ pri_chnl <= `TD pri_chnl + 1;
420
+ end
421
+ end
422
+
423
+ // dropped queue
424
+ assign dropped_wen = p2p_mem_desc_req_valid & p2p_mem_desc_req_ready;
425
+ assign dropped_qnum = (p2p_mem_desc_req_head[63:32] & 18'h3FFFF) >> 14;
426
+ /* --------queue descriptor{end}-------- */
427
+
428
+ /* --------descriptor queue output FSM{begin}-------- */
429
+ /******************** Stage 1: State Register **********************/
430
+ assign is_idle = (cur_state == IDLE );
431
+ assign is_desc_que_out = (cur_state == DESC_QUE_OUT);
432
+ assign is_nxt_desc_que_out = (is_idle || (is_desc_que_out & desc_out_valid & desc_out_ready & desc_out_last)) & is_match_succ;
433
+
434
+ always @(posedge clk, negedge rst_n) begin
435
+ if(~rst_n)
436
+ cur_state <= `TD IDLE;
437
+ else
438
+ cur_state <= `TD nxt_state;
439
+ end
440
+
441
+ /******************** Stage 2: State Transition **********************/
442
+ always @(*) begin
443
+ case(cur_state)
444
+ IDLE: begin
445
+ if (is_match_succ) begin
446
+ nxt_state = DESC_QUE_OUT;
447
+ end
448
+ else begin
449
+ nxt_state = IDLE;
450
+ end
451
+ end
452
+ DESC_QUE_OUT: begin
453
+ if (desc_out_valid & desc_out_ready & desc_out_last) begin
454
+ if (is_match_succ) begin
455
+ nxt_state = DESC_QUE_OUT;
456
+ end
457
+ else begin
458
+ nxt_state = IDLE;
459
+ end
460
+ end
461
+ else begin
462
+ nxt_state = DESC_QUE_OUT;
463
+ end
464
+ end
465
+ default: begin
466
+ nxt_state = IDLE;
467
+ end
468
+ endcase
469
+ end
470
+ /******************** Stage 3: Output **********************/
471
+ always @(posedge clk, negedge rst_n) begin
472
+ if (~rst_n) begin
473
+ desc_out_byte_left <= `TD 0;
474
+ end
475
+ else if (is_nxt_desc_que_out) begin
476
+ desc_out_byte_left <= `TD (qdesc_1_dout[match_qnum] >> 32) & 16'hFFFF;
477
+ end
478
+ else if (is_desc_que_out & desc_out_valid & desc_out_ready & desc_out_last) begin
479
+ desc_out_byte_left <= `TD 0;
480
+ end
481
+ else if (is_desc_que_out & desc_out_valid & desc_out_ready) begin
482
+ desc_out_byte_left <= `TD desc_out_byte_left - `PBUF_BLOCK_SZ;
483
+ end
484
+ end
485
+
486
+ always @(posedge clk, negedge rst_n) begin
487
+ if (~rst_n) begin
488
+ desc_out_head_desc <= `TD 0;
489
+ end
490
+ else if (is_nxt_desc_que_out) begin
491
+ desc_out_head_desc <= `TD qdesc_1_dout[match_qnum];
492
+ end
493
+ else if (is_idle) begin
494
+ desc_out_head_desc <= `TD 0;
495
+ end
496
+ end
497
+
498
+ assign desc_out_valid = is_desc_que_out & !alloced_buf_empty[match_qnum_reg];
499
+ assign desc_out_last = desc_out_valid ? (desc_out_byte_left <= `PBUF_BLOCK_SZ) : 1'd0;
500
+ assign desc_out_head_qnum = match_qnum_reg;
501
+ assign desc_out_buf_addr = alloced_buf_dout[match_qnum_reg];
502
+ /* --------descriptor queue output FSM{begin}-------- */
503
+
504
+ endmodule
ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/P2P/tgt_pyld_buf.v ADDED
@@ -0,0 +1,264 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ `timescale 1ns / 100ps
2
+ //*************************************************************************
3
+ // > File : tgt_pyld_buf.v
4
+ // > Author : Kangning
5
+ // > Date : 2022-08-29
6
+ // > Note : Payload buffer for payload temp store
7
+ //*************************************************************************
8
+
9
+ module tgt_pyld_buf #(
10
+
11
+ ) (
12
+
13
+ input wire clk , // i, 1
14
+ input wire rst_n , // i, 1
15
+ output reg init_end, // o, 1
16
+
17
+ /* --------allocated buffer address{begin}-------- */
18
+ output wire pbuf_alloc_valid , // o, 1
19
+ output wire pbuf_alloc_last , // o, 1
20
+ output wire [`BUF_ADDR_WIDTH-1:0] pbuf_alloc_buf_addr, // o, `BUF_ADDR_WIDTH
21
+ output wire [8 -1:0] pbuf_alloc_qnum , // o, 8
22
+ input wire pbuf_alloc_ready , // i, 1 ; assume it always asserts
23
+ /* --------allocated buffer address{end}-------- */
24
+
25
+ /* --------p2p mem payload in{begin}-------- */
26
+ input wire st_pyld_req_valid, // i, 1
27
+ input wire st_pyld_req_last , // i, 1
28
+ input wire [`MSG_BLEN_WIDTH-1:0] st_pyld_req_blen , // i, `MSG_BLEN_WIDTH
29
+ input wire [8 -1:0] st_pyld_req_qnum , // i, 8
30
+ input wire [`P2P_DATA_W -1:0] st_pyld_req_data , // i, `P2P_DATA_W
31
+ output wire st_pyld_req_ready, // o, 1
32
+ /* --------p2p mem payload in{end}-------- */
33
+
34
+ /* --------Ctrl Info to pyld_buf{begin}-------- */
35
+ input wire pbuf_free_valid , // i, 1
36
+ input wire pbuf_free_last , // i, 1
37
+ input wire [`P2P_DHEAD_W -1:0] pbuf_free_head , // i, `P2P_DHEAD_W
38
+ input wire [1 :0] pbuf_free_buf_offset, // i, 2
39
+ input wire [`BUF_ADDR_WIDTH-1:0] pbuf_free_buf_addr , // i, `BUF_ADDR_WIDTH
40
+ output wire pbuf_free_ready , // o, 1
41
+ /* --------Ctrl Info to pyld_buf{begin}-------- */
42
+
43
+ /* --------p2p mem payload out{begin}-------- */
44
+ output reg ft_pyld_req_valid, // o, 1
45
+ output reg ft_pyld_req_last , // o, 1
46
+ output reg [`P2P_DHEAD_W -1:0] ft_pyld_req_head , // o, `P2P_DHEAD_W
47
+ output wire [`P2P_DATA_W -1:0] ft_pyld_req_data , // o, `P2P_DATA_W
48
+ input wire ft_pyld_req_ready // i, 1
49
+ /* --------p2p mem payload out{end}-------- */
50
+
51
+ `ifdef PCIEI_APB_DBG
52
+ /* -------APB reated signal{begin}------- */
53
+ ,input wire [`SRAM_RW_DATA_W*2-1:0] rw_data // i, `SRAM_RW_DATA_W*2
54
+ ,output wire [`TGT_PBUF_SIGNAL_W-1:0] dbg_signal // o, `TGT_PBUF_SIGNAL_W
55
+ /* -------APB reated signal{end}------- */
56
+ `endif
57
+ );
58
+
59
+ localparam BEAT_BYTE_NUM = `P2P_DATA_W / 8; // 32
60
+ localparam P2P_DATA_W_LOG = $clog2(`P2P_DATA_W); // 8
61
+ localparam PBUF_BLOCK_WIDTH = `PBUF_SZ_LOG + 3 - P2P_DATA_W_LOG; // 2
62
+ localparam PBUF_ADDR_WIDTH = `PBUF_NUM_LOG + PBUF_BLOCK_WIDTH; // 12
63
+
64
+ /* --------free buffer list{begin}-------- */
65
+ wire free_buf_wen , free_buf_ren ;
66
+ wire [`PBUF_NUM_LOG-1:0] free_buf_din , free_buf_dout ;
67
+ wire free_buf_full, free_buf_empty;
68
+
69
+ wire init_stat;
70
+ reg [`PBUF_NUM_LOG-1:0] init_din;
71
+ /* --------free buffer list{end}-------- */
72
+
73
+ /* --------payload buffer{begin}-------- */
74
+ wire is_st_last_pbuf_beat; // the last beat to store payload buffer block
75
+
76
+ wire pbuf_st_wen ;
77
+ wire [PBUF_ADDR_WIDTH-1:0] pbuf_st_addr;
78
+ wire [`P2P_DATA_W -1:0] pbuf_st_din ;
79
+
80
+ wire pbuf_ft_ren ;
81
+ wire [PBUF_ADDR_WIDTH-1:0] pbuf_ft_addr;
82
+ wire [`P2P_DATA_W -1:0] pbuf_ft_dout;
83
+
84
+ reg [PBUF_BLOCK_WIDTH-1:0] st_offset ;
85
+ /* --------payload buffer{end}-------- */
86
+
87
+ `ifdef PCIEI_APB_DBG
88
+ /* -------APB reated signal{begin}------- */
89
+ wire [1:0] pyld_buf_rtsel, free_buf_fifo_rtsel;
90
+ wire [1:0] pyld_buf_wtsel, free_buf_fifo_wtsel;
91
+ wire [1:0] pyld_buf_ptsel, free_buf_fifo_ptsel;
92
+ wire pyld_buf_vg , free_buf_fifo_vg ;
93
+ wire pyld_buf_vs , free_buf_fifo_vs ;
94
+ /* -------APB reated signal{end}------- */
95
+ `endif
96
+
97
+ //---------------------------------------------------------------------------------------------------------------------------
98
+
99
+ `ifdef PCIEI_APB_DBG
100
+ /* -------APB reated signal{begin}------- */
101
+ assign {
102
+ free_buf_fifo_rtsel,
103
+ free_buf_fifo_wtsel,
104
+ free_buf_fifo_ptsel,
105
+ free_buf_fifo_vg ,
106
+ free_buf_fifo_vs ,
107
+ pyld_buf_rtsel ,
108
+ pyld_buf_wtsel ,
109
+ pyld_buf_ptsel ,
110
+ pyld_buf_vg ,
111
+ pyld_buf_vs
112
+ } = rw_data;
113
+
114
+ assign dbg_signal = { // 576
115
+
116
+ free_buf_wen , free_buf_ren ,
117
+ free_buf_din , free_buf_dout ,
118
+ free_buf_full, free_buf_empty, // 24
119
+
120
+ init_stat, init_din, // 11
121
+ is_st_last_pbuf_beat, // 1
122
+
123
+ pbuf_st_wen, pbuf_st_addr, pbuf_st_din , // 269
124
+ pbuf_ft_ren, pbuf_ft_addr, pbuf_ft_dout, // 269
125
+
126
+ st_offset // 2
127
+ };
128
+ /* -------APB reated signal{end}------- */
129
+ `endif
130
+
131
+ /* --------free buffer list{begin}-------- */
132
+ pcieifc_sync_fifo #(
133
+ .DSIZE ( `PBUF_NUM_LOG ), // 10
134
+ .ASIZE ( `PBUF_NUM_LOG ) // 10
135
+ ) free_buf_fifo (
136
+ .clk ( clk ),
137
+ .rst_n ( rst_n ),
138
+ .clr ( 1'd0 ),
139
+
140
+ .wen ( free_buf_wen ),
141
+ .din ( free_buf_din ),
142
+
143
+ .ren ( free_buf_ren ),
144
+ .dout ( free_buf_dout ),
145
+
146
+ .full ( free_buf_full ),
147
+ .empty ( free_buf_empty )
148
+
149
+ `ifdef PCIEI_APB_DBG
150
+ ,.rtsel ( free_buf_fifo_rtsel ) // i, 2
151
+ ,.wtsel ( free_buf_fifo_wtsel ) // i, 2
152
+ ,.ptsel ( free_buf_fifo_ptsel ) // i, 2
153
+ ,.vg ( free_buf_fifo_vg ) // i, 1
154
+ ,.vs ( free_buf_fifo_vs ) // i, 1
155
+ `endif
156
+ );
157
+
158
+ assign free_buf_wen = init_stat ? 1 : (pbuf_free_valid & pbuf_free_ready & (pbuf_free_last || pbuf_free_buf_offset == 3));
159
+ assign free_buf_din = init_stat ? init_din : pbuf_free_buf_addr;
160
+
161
+ assign free_buf_ren = pbuf_alloc_valid & pbuf_alloc_ready;
162
+
163
+ // Initialization related signal
164
+ assign init_stat = (~init_end & rst_n);
165
+ always @(posedge clk, negedge rst_n) begin
166
+ if (~rst_n) begin
167
+ init_din <= `TD 0;
168
+ end
169
+ else if (~init_end) begin
170
+ init_din <= `TD init_din + 1;
171
+ end
172
+ end
173
+ always @(posedge clk, negedge rst_n) begin
174
+ if (~rst_n) begin
175
+ init_end <= `TD 0;
176
+ end
177
+ else if (init_din == 10'd1023) begin
178
+ init_end <= `TD 1;
179
+ end
180
+ end
181
+ /* --------free buffer list{end}-------- */
182
+
183
+ /* --------payload buffer{begin}-------- */
184
+ assign is_st_last_pbuf_beat = (st_offset == 3) || st_pyld_req_last;
185
+
186
+ //pcieifc_sd_sram #(
187
+ // .DATAWIDTH ( `P2P_DATA_W ), // Memory data word width, 256
188
+ // .ADDRWIDTH ( PBUF_ADDR_WIDTH ) // Number of mem address bits, 12
189
+ //) pyld_buf (
190
+ // .clk ( clk ), // i, 1
191
+ // .rst_n ( rst_n ), // i, 1
192
+
193
+ // .wea ( pbuf_st_wen ), // i, 1
194
+ // .addra ( pbuf_st_addr ), // i, ADDRWIDTH
195
+ // .dina ( pbuf_st_din ), // i, DATAWIDTH
196
+
197
+ // .reb ( pbuf_ft_ren ), // i, 1
198
+ // .addrb ( pbuf_ft_addr ), // i, ADDRWIDTH
199
+ // .doutb ( pbuf_ft_dout ) // o, DATAWIDTH
200
+
201
+ //`ifdef PCIEI_APB_DBG
202
+ // ,.rtsel ( pyld_buf_rtsel ) // i, 2
203
+ // ,.wtsel ( pyld_buf_wtsel ) // i, 2
204
+ // ,.ptsel ( pyld_buf_ptsel ) // i, 2
205
+ // ,.vg ( pyld_buf_vg ) // i, 1
206
+ // ,.vs ( pyld_buf_vs ) // i, 1
207
+ //`endif
208
+ //);
209
+
210
+ // payload buffer related signal
211
+ assign pbuf_st_wen = st_pyld_req_valid & st_pyld_req_ready;
212
+ assign pbuf_st_addr = {free_buf_dout, st_offset};
213
+ assign pbuf_st_din = st_pyld_req_data;
214
+
215
+ assign pbuf_ft_ren = pbuf_free_valid & pbuf_free_ready;
216
+ assign pbuf_ft_addr = {pbuf_free_buf_addr, pbuf_free_buf_offset};
217
+
218
+ // store address generation
219
+ always @(posedge clk, negedge rst_n) begin
220
+ if (~rst_n) begin
221
+ st_offset <= `TD 0;
222
+ end
223
+ else if (is_st_last_pbuf_beat & (st_pyld_req_valid & st_pyld_req_ready)) begin
224
+ st_offset <= `TD 0;
225
+ end
226
+ else if (st_pyld_req_valid & st_pyld_req_ready) begin
227
+ st_offset <= `TD st_offset + 1;
228
+ end
229
+ end
230
+ /* --------payload buffer{end}-------- */
231
+
232
+ /* --------store related output{begin}-------- */
233
+ assign st_pyld_req_ready = (is_st_last_pbuf_beat ? pbuf_alloc_ready : 1) & !free_buf_empty;
234
+
235
+ assign pbuf_alloc_valid = is_st_last_pbuf_beat & st_pyld_req_valid & !free_buf_empty;
236
+ assign pbuf_alloc_last = pbuf_alloc_valid & st_pyld_req_last;
237
+ assign pbuf_alloc_buf_addr = free_buf_dout ;
238
+ assign pbuf_alloc_qnum = st_pyld_req_qnum;
239
+ /* --------store related output{end}-------- */
240
+
241
+ /* --------fetch related output{begin}-------- */
242
+ assign pbuf_free_ready = !ft_pyld_req_valid | ft_pyld_req_ready;
243
+
244
+ assign ft_pyld_req_data = pbuf_ft_dout;
245
+ always @(posedge clk, negedge rst_n) begin
246
+ if (~rst_n) begin
247
+ ft_pyld_req_valid <= `TD 1'd0;
248
+ ft_pyld_req_last <= `TD 1'd0;
249
+ ft_pyld_req_head <= `TD {`P2P_DHEAD_W{1'd0}};
250
+ end
251
+ else if (pbuf_free_valid & pbuf_free_ready) begin
252
+ ft_pyld_req_valid <= `TD 1'd1;
253
+ ft_pyld_req_last <= `TD pbuf_free_last;
254
+ ft_pyld_req_head <= `TD pbuf_free_head;
255
+ end
256
+ else if (ft_pyld_req_valid & ft_pyld_req_ready) begin
257
+ ft_pyld_req_valid <= `TD 1'd0;
258
+ ft_pyld_req_last <= `TD 1'd0;
259
+ ft_pyld_req_head <= `TD {`P2P_DHEAD_W{1'd0}};
260
+ end
261
+ end
262
+ /* --------fetch related output{end}-------- */
263
+
264
+ endmodule
ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/P2P/tgt_pyld_recv_proc.v ADDED
@@ -0,0 +1,236 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ `timescale 1ns / 100ps
2
+ //*************************************************************************
3
+ // > File : tgt_pyld_recv_proc.v
4
+ // > Author : Kangning
5
+ // > Date : 2022-08-25
6
+ // > Note : target payload recvive processing
7
+ //*************************************************************************
8
+
9
+ module tgt_pyld_recv_proc #(
10
+
11
+ ) (
12
+
13
+ input wire clk , // i, 1
14
+ input wire rst_n , // i, 1
15
+ output reg init_end, // o, 1
16
+
17
+ /* --------Next mem payload{begin}-------- */
18
+ input wire nxt_vaild, // i, 1
19
+ input wire [7:0] nxt_qnum , // i, 8
20
+ /* --------Next mem payload{end}-------- */
21
+
22
+ /* --------p2p mem payload in{begin}-------- */
23
+ /* p2p_req head
24
+ * | 127 | 126:64 | 63:32 | 31:13 | 12:0 |
25
+ * | is_wr | Reserved | addr | Reserved | byte_len |
26
+ */
27
+ input wire st0_p2p_pyld_req_valid, // i, 1
28
+ input wire st0_p2p_pyld_req_last , // i, 1
29
+ input wire [`P2P_HEAD_W-1:0] st0_p2p_pyld_req_head , // i, `P2P_HEAD_W
30
+ input wire [`P2P_DATA_W-1:0] st0_p2p_pyld_req_data , // i, `P2P_DATA_W
31
+ output wire st0_p2p_pyld_req_ready, // o, 1
32
+ /* --------p2p mem payload in{end}-------- */
33
+
34
+ /* --------p2p mem payload out{begin}-------- */
35
+ output wire st_pyld_req_valid, // o, 1
36
+ output wire st_pyld_req_last , // o, 1
37
+ output wire [`MSG_BLEN_WIDTH-1:0] st_pyld_req_blen , // o, `MSG_BLEN_WIDTH
38
+ output wire [8 -1:0] st_pyld_req_qnum , // o, 8
39
+ output wire [`P2P_DATA_W -1:0] st_pyld_req_data , // o, `P2P_DATA_W
40
+ input wire st_pyld_req_ready, // i, 1
41
+ /* --------p2p mem payload out{end}-------- */
42
+
43
+ /* --------dropped queue{begin}-------- */
44
+ input wire dropped_wen , // i, 1
45
+ input wire [`QUEUE_NUM_LOG-1:0] dropped_qnum, // i, `QUEUE_NUM_LOG
46
+ input wire dropped_data // i, 1
47
+ /* --------dropped queue{end}-------- */
48
+
49
+ `ifdef PCIEI_APB_DBG
50
+ /* -------APB reated signal{begin}------- */
51
+ ,output wire [`TGT_RECV_SIGNAL_W-1:0] dbg_signal
52
+ /* -------APB reated signal{end}------- */
53
+ `endif
54
+ );
55
+
56
+ /* --------Dropped Register{begin}-------- */
57
+ // reg init_end;
58
+ reg [`QUEUE_NUM_LOG-1:0] tab_index;
59
+ reg dropped_tab[`QUEUE_NUM-1:0];
60
+ reg [7:0] pass_qnum;
61
+ /* --------Dropped Register{end}-------- */
62
+
63
+ /* --------Payload Receiving FSM{begin}-------- */
64
+ localparam IDLE = 3'b001,
65
+ PYLD_DROP = 3'b010,
66
+ PYLD_PASS = 3'b100;
67
+
68
+ reg [2:0] cur_state;
69
+ reg [2:0] nxt_state;
70
+
71
+ wire is_idle, is_pyld_drop, is_pyld_pass;
72
+ // wire j_pyld_pass;
73
+ wire is_nxt_pass; // process next pkt in the next cycle
74
+ /* --------Payload Receiving FSM{end}-------- */
75
+
76
+ // ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------- //
77
+
78
+ `ifdef PCIEI_APB_DBG
79
+ /* -------APB reated signal{begin}------- */
80
+
81
+ assign dbg_signal = { // 38
82
+
83
+ tab_index, // 4
84
+
85
+ dropped_tab[0 ], dropped_tab[1 ], dropped_tab[2 ], dropped_tab[3 ],
86
+ dropped_tab[4 ], dropped_tab[5 ], dropped_tab[6 ], dropped_tab[7 ],
87
+ dropped_tab[8 ], dropped_tab[9 ], dropped_tab[10], dropped_tab[11],
88
+ dropped_tab[12], dropped_tab[13], dropped_tab[14], dropped_tab[15], // 16
89
+
90
+ pass_qnum, cur_state, nxt_state, is_idle, is_pyld_drop, is_pyld_pass, is_nxt_pass // 18
91
+ };
92
+ /* -------APB reated signal{end}------- */
93
+ `endif
94
+
95
+ /* --------Dropped Register{begin}-------- */
96
+
97
+ // Init state end
98
+ always @(posedge clk, negedge rst_n) begin
99
+ if (~rst_n) begin
100
+ init_end <= `TD 0;
101
+ end
102
+ else if (tab_index == (1'h1 << `QUEUE_NUM_LOG) - 1) begin
103
+ init_end <= `TD 1;
104
+ end
105
+ end
106
+
107
+ // drop table index calculation
108
+ always @(posedge clk, negedge rst_n) begin
109
+ if (~rst_n) begin
110
+ tab_index <= `TD 0;
111
+ end
112
+ else if (~init_end) begin
113
+ tab_index <= `TD tab_index + 1;
114
+ end
115
+ end
116
+
117
+ // drop table update
118
+ integer i;
119
+ always @(posedge clk, negedge rst_n) begin
120
+ if (~rst_n) begin
121
+ for (i = 0; i < `QUEUE_NUM; i=i+1) begin
122
+ dropped_tab[i] <= `TD 0;
123
+ end
124
+ end
125
+ else if (~init_end) begin // Initialize queue drop table
126
+ dropped_tab[tab_index] <= `TD 1;
127
+ end
128
+ else if (dropped_wen) begin
129
+ dropped_tab[dropped_qnum] <= `TD dropped_data;
130
+ end
131
+ // else if (is_nxt_pass) begin // if next state is pass (pass new payload),
132
+ // // set accordingly queue to dropped state
133
+ // dropped_tab[tab_index] <= `TD 1;
134
+ // end
135
+ end
136
+
137
+ always @(posedge clk, negedge rst_n) begin
138
+ if (~rst_n) begin
139
+ pass_qnum <= `TD 0;
140
+ end
141
+ else if (is_nxt_pass) begin
142
+ pass_qnum <= `TD nxt_qnum;
143
+ end
144
+ end
145
+ /* --------Dropped Register{end}-------- */
146
+
147
+
148
+ /* -------Payload Receiving FSM{begin}------- */
149
+ /******************** Stage 1: State Register **********************/
150
+ assign is_idle = (cur_state == IDLE );
151
+ assign is_pyld_drop = (cur_state == PYLD_DROP);
152
+ assign is_pyld_pass = (cur_state == PYLD_PASS);
153
+
154
+ // assign j_pyld_pass = (nxt_state == IDLE) & (cur_state == PYLD_PASS);
155
+
156
+ assign is_nxt_pass = ((cur_state == IDLE ) & (nxt_state == PYLD_PASS)) |
157
+ ((cur_state == PYLD_DROP) & (nxt_state == PYLD_PASS)) |
158
+ ((cur_state == PYLD_PASS) & (nxt_state == PYLD_PASS) & st0_p2p_pyld_req_valid & st0_p2p_pyld_req_ready & st0_p2p_pyld_req_last);
159
+
160
+ always @(posedge clk, negedge rst_n) begin
161
+ if(~rst_n)
162
+ cur_state <= `TD IDLE;
163
+ else
164
+ cur_state <= `TD nxt_state;
165
+ end
166
+
167
+ /******************** Stage 2: State Transition **********************/
168
+
169
+ always @(*) begin
170
+ case(cur_state)
171
+ IDLE: begin
172
+ if (nxt_vaild) begin
173
+ if (dropped_tab[nxt_qnum]) begin
174
+ nxt_state = PYLD_DROP;
175
+ end
176
+ else begin
177
+ nxt_state = PYLD_PASS;
178
+ end
179
+ end
180
+ else begin
181
+ nxt_state = IDLE;
182
+ end
183
+ end
184
+ PYLD_DROP: begin
185
+ if (st0_p2p_pyld_req_valid & st0_p2p_pyld_req_last) begin
186
+ if (nxt_vaild) begin
187
+ if (dropped_tab[nxt_qnum]) begin
188
+ nxt_state = PYLD_DROP;
189
+ end
190
+ else begin
191
+ nxt_state = PYLD_PASS;
192
+ end
193
+ end
194
+ else begin
195
+ nxt_state = IDLE;
196
+ end
197
+ end
198
+ else begin
199
+ nxt_state = PYLD_DROP;
200
+ end
201
+ end
202
+ PYLD_PASS: begin
203
+ if (st0_p2p_pyld_req_valid & st0_p2p_pyld_req_ready & st0_p2p_pyld_req_last) begin
204
+ if (nxt_vaild) begin
205
+ if (dropped_tab[nxt_qnum]) begin
206
+ nxt_state = PYLD_DROP;
207
+ end
208
+ else begin
209
+ nxt_state = PYLD_PASS;
210
+ end
211
+ end
212
+ else begin
213
+ nxt_state = IDLE;
214
+ end
215
+ end
216
+ else begin
217
+ nxt_state = PYLD_PASS;
218
+ end
219
+ end
220
+ default: begin
221
+ nxt_state = IDLE;
222
+ end
223
+ endcase
224
+ end
225
+ /******************** Stage 3: Output **********************/
226
+
227
+ assign st0_p2p_pyld_req_ready = is_pyld_drop | (is_pyld_pass & st_pyld_req_ready);
228
+
229
+ assign st_pyld_req_valid = is_pyld_pass ? st0_p2p_pyld_req_valid : 0;
230
+ assign st_pyld_req_last = is_pyld_pass ? st0_p2p_pyld_req_last : 0;
231
+ assign st_pyld_req_blen = is_pyld_pass ? st0_p2p_pyld_req_head[`MSG_BLEN_WIDTH-1:0] : 0;
232
+ assign st_pyld_req_qnum = is_pyld_pass ? pass_qnum : 0;
233
+ assign st_pyld_req_data = is_pyld_pass ? st0_p2p_pyld_req_data : 0;
234
+ /* -------Destinstaion NIC processing FSM{end}------- */
235
+
236
+ endmodule
ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/P2P/tgt_pyld_send_proc.v ADDED
@@ -0,0 +1,247 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ `timescale 1ns / 100ps
2
+ //*************************************************************************
3
+ // > File : tgt_pyld_send_proc.v
4
+ // > Author : Kangning
5
+ // > Date : 2022-08-28
6
+ // > Note : DMA P2P target payload send processing
7
+ //*************************************************************************
8
+
9
+
10
+ `define stat_trans if (qstruct_valid) begin \
11
+ nxt_state = DESC_PARSE; \
12
+ end \
13
+ else begin \
14
+ nxt_state = IDLE; \
15
+ end
16
+
17
+ module tgt_pyld_send_proc #(
18
+
19
+ ) (
20
+
21
+ input wire clk , // i, 1
22
+ input wire rst_n, // i, 1
23
+
24
+ /* --------Info from queue struct{begin}-------- */
25
+ /* qstruct_head_ctx : qcontext of prepared queue
26
+ * qstruct_head_desc: payload descriptor
27
+ * qstruct_buf_addr : allocated buffer base address in P2P pyld_buf,
28
+ * this is an array. A valid addr outputs when valid
29
+ * and ready assert at the same time.
30
+ * qstruct_last : assert when the last qstruct_buf_addr is asserted
31
+ */
32
+ input wire qstruct_valid , // i, 1
33
+ input wire qstruct_last , // i, 1
34
+ input wire [`QUEUE_CONTEXT_WIDTH-1:0] qstruct_head_ctx , // i, `QUEUE_CONTEXT_WIDTH
35
+ input wire [`QUEUE_DESC_WIDTH -1:0] qstruct_head_desc, // i, `QUEUE_DESC_WIDTH
36
+ input wire [`BUF_ADDR_WIDTH -1:0] qstruct_buf_addr , // i, `BUF_ADDR_WIDTH
37
+ output wire qstruct_ready , // o, 1
38
+ /* --------Info from queue struct{end}-------- */
39
+
40
+ /* --------Ctrl Info to pyld_buf{begin}-------- */
41
+ /* *_head, valid only in first beat of a packet
42
+ * | Reserved |dst_dev| src_dev | Reserved | Byte length |
43
+ * | 63:- | 47:40 | 39:32 | 31:16 | 15:0 |
44
+ */
45
+ output wire pbuf_free_valid , // o, 1
46
+ output wire pbuf_free_last , // o, 1
47
+ output wire [`P2P_DHEAD_W -1:0] pbuf_free_head , // o, `P2P_DHEAD_W
48
+ output wire [1:0] pbuf_free_buf_offset, // o, 2
49
+ output wire [`BUF_ADDR_WIDTH-1:0] pbuf_free_buf_addr , // o, `BUF_ADDR_WIDTH
50
+ input wire pbuf_free_ready , // i, 1
51
+ /* --------Ctrl Info to pyld_buf{begin}-------- */
52
+
53
+ /* --------p2p mem payload out{begin}-------- */
54
+ /* *_head, valid only in first beat of a packet
55
+ * | Reserved |dst_dev| src_dev | Reserved | Byte length |
56
+ * | 63:- | 47:40 | 39:32 | 31:16 | 15:0 |
57
+ */
58
+ input wire ft_pyld_req_valid, // i, 1
59
+ input wire ft_pyld_req_last , // i, 1
60
+ input wire [`P2P_DHEAD_W-1:0] ft_pyld_req_head , // i, `P2P_DHEAD_W
61
+ input wire [`P2P_DATA_W -1:0] ft_pyld_req_data , // i, `P2P_DATA_W
62
+ output wire ft_pyld_req_ready, // o, 1
63
+ /* --------p2p mem payload out{end}-------- */
64
+
65
+ /* --------p2p forward down channel{begin}-------- */
66
+ /* *_head, valid only in first beat of a packet
67
+ * | Reserved |dst_dev| src_dev | Reserved | Byte length |
68
+ * | 63:- | 47:40 | 39:32 | 31:16 | 15:0 |
69
+ */
70
+ output wire st_p2p_down_valid, // o, 1
71
+ output wire st_p2p_down_last , // o, 1
72
+ output wire [`P2P_DHEAD_W-1:0] st_p2p_down_head , // o, `P2P_DHEAD_W
73
+ output wire [`P2P_DATA_W -1:0] st_p2p_down_data , // o, `P2P_DATA_W
74
+ input wire st_p2p_down_ready // i, 1
75
+ /* --------p2p forward down channel{end}-------- */
76
+
77
+ `ifdef PCIEI_APB_DBG
78
+ /* -------APB reated signal{begin}------- */
79
+ ,output wire [`TGT_SEND_SIGNAL_W-1:0] dbg_signal // o, `TGT_SEND_SIGNAL_W
80
+ /* -------APB reated signal{end}------- */
81
+ `endif
82
+ );
83
+
84
+ localparam BEAT_BYTE_NUM = `P2P_DATA_W / 8;
85
+
86
+ /* --------Payload Sending FSM{begin}-------- */
87
+ localparam IDLE = 2'b01,
88
+ DESC_PARSE = 2'b10;
89
+
90
+ reg [1:0] cur_state;
91
+ reg [1:0] nxt_state;
92
+
93
+ wire [47 :0] qctx_slid ;
94
+ wire [47 :0] qdesc_dlid;
95
+ wire [`MSG_BLEN_WIDTH-1:0] qdesc_blen;
96
+ wire [`DEV_NUM_WIDTH -1:0] qdesc_sdev;
97
+ wire [`DEV_NUM_WIDTH -1:0] qdesc_ddev;
98
+
99
+ wire [1:0] last_offset;
100
+ reg [1:0] ft_offset ;
101
+
102
+ wire is_idle, is_desc_parse;
103
+ wire is_nxt_desc_parse;
104
+ /* --------Payload Sending FSM{end}-------- */
105
+
106
+ /* --------p2p forward down channel{begin}-------- */
107
+ /* *_head, valid only in first beat of a packet
108
+ * | Reserved |dst_dev| src_dev | Reserved | Byte length |
109
+ * | 63:- | 47:40 | 39:32 | 31:16 | 15:0 |
110
+ */
111
+ wire p2p_down_valid;
112
+ wire p2p_down_last ;
113
+ wire [`P2P_DATA_W -1:0] p2p_down_data ;
114
+ wire [`P2P_DHEAD_W-1:0] p2p_down_head ;
115
+ wire p2p_down_ready;
116
+ /* --------p2p forward down channel{end}-------- */
117
+
118
+ //-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------//
119
+
120
+ `ifdef PCIEI_APB_DBG
121
+ /* -------APB reated signal{begin}------- */
122
+ assign dbg_signal = { // 462
123
+
124
+ cur_state, nxt_state, // 4
125
+ qctx_slid , qdesc_dlid, qdesc_blen, qdesc_sdev, qdesc_ddev, // 128
126
+ last_offset, ft_offset , // 4
127
+ is_idle, is_desc_parse, is_nxt_desc_parse, // 3
128
+ p2p_down_valid, p2p_down_last , p2p_down_data , p2p_down_head , p2p_down_ready // 323
129
+ };
130
+ /* -------APB reated signal{end}------- */
131
+ `endif
132
+
133
+ /* -------Payload Sending FSM{begin}------- */
134
+ /******************** Stage 1: State Register **********************/
135
+ assign is_idle = (cur_state == IDLE );
136
+ assign is_desc_parse = (cur_state == DESC_PARSE);
137
+
138
+ assign is_nxt_desc_parse = ((nxt_state == DESC_PARSE) & (cur_state == IDLE )) |
139
+ ((nxt_state == DESC_PARSE) & (cur_state == DESC_PARSE) & p2p_down_valid & p2p_down_ready & p2p_down_last);
140
+
141
+ // assign last_offset = qdesc_blen[`PBUF_SZ_LOG-1:`PBUF_SZ_LOG-2] + |qdesc_blen[`PBUF_SZ_LOG-3:0] - 2'b1;
142
+ assign qctx_slid = qstruct_head_ctx[47:0];
143
+ assign qdesc_dlid = {qstruct_head_desc[79:64], qstruct_head_desc[31:0]};
144
+ assign qdesc_blen = qstruct_head_desc[47:32];
145
+ assign qdesc_sdev = qstruct_head_desc[55:48];
146
+ assign qdesc_ddev = qstruct_head_desc[63:56];
147
+ assign last_offset = qdesc_blen[`PBUF_SZ_LOG-1:`PBUF_SZ_LOG-2] + |qdesc_blen[`PBUF_SZ_LOG-3:0] - 2'b1;
148
+
149
+ always @(posedge clk, negedge rst_n) begin
150
+ if (~rst_n) begin
151
+ ft_offset <= `TD 2'd0;
152
+ end
153
+ else if (is_desc_parse & pbuf_free_valid & pbuf_free_ready & pbuf_free_last) begin
154
+ ft_offset <= `TD 2'd0;
155
+ end
156
+ else if (is_desc_parse & pbuf_free_valid & pbuf_free_ready) begin
157
+ ft_offset <= `TD ft_offset + 2'd1;
158
+ end
159
+ end
160
+
161
+ always @(posedge clk, negedge rst_n) begin
162
+ if(~rst_n)
163
+ cur_state <= `TD IDLE;
164
+ else
165
+ cur_state <= `TD nxt_state;
166
+ end
167
+ /******************** Stage 2: State Transition **********************/
168
+
169
+ always @(*) begin
170
+ case(cur_state)
171
+ IDLE: begin
172
+ `stat_trans
173
+ // if (qstruct_valid) begin
174
+ // nxt_state = DESC_PARSE;
175
+ // end
176
+ // else begin
177
+ // nxt_state = IDLE;
178
+ // end
179
+ end
180
+ DESC_PARSE: begin
181
+ if (p2p_down_valid & p2p_down_ready & p2p_down_last) begin
182
+ `stat_trans
183
+ end
184
+ else begin
185
+ nxt_state = DESC_PARSE;
186
+ end
187
+ end
188
+ default: begin
189
+ nxt_state = IDLE;
190
+ end
191
+ endcase
192
+ end
193
+ /******************** Stage 3: Output **********************/
194
+
195
+ assign qstruct_ready = ((ft_offset == 3) || pbuf_free_last) & pbuf_free_ready & is_desc_parse;
196
+
197
+ assign pbuf_free_valid = qstruct_valid & is_desc_parse;
198
+ assign pbuf_free_last = qstruct_last & (ft_offset == last_offset);
199
+ assign pbuf_free_head = {{32-2*`DEV_NUM_WIDTH{1'd0}}, qdesc_ddev, qdesc_sdev, 16'd0, qdesc_blen};
200
+ assign pbuf_free_buf_offset = ft_offset ;
201
+ assign pbuf_free_buf_addr = qstruct_buf_addr;
202
+
203
+
204
+ /* *_head, valid only in first beat of a packet
205
+ * | Reserved |dst_dev| src_dev | Reserved | Byte length |
206
+ * | 63:- | 47:40 | 39:32 | 31:16 | 15:0 |
207
+ */
208
+ assign p2p_down_valid = ft_pyld_req_valid;
209
+ assign p2p_down_last = ft_pyld_req_last;
210
+ assign p2p_down_head = ft_pyld_req_head;
211
+ assign p2p_down_data = ft_pyld_req_data;
212
+ assign ft_pyld_req_ready = p2p_down_ready;
213
+
214
+ st_reg #(
215
+ .TUSER_WIDTH ( `P2P_DHEAD_W ),
216
+ .TDATA_WIDTH ( `P2P_DATA_W )
217
+ ) st_reg2down (
218
+ .clk ( clk ), // i, 1
219
+ .rst_n ( rst_n ), // i, 1
220
+
221
+ /* -------input axis-like interface{begin}------- */
222
+ /* *_head, valid only in first beat of a packet
223
+ * | Reserved |dst_dev| src_dev | Reserved | Byte length |
224
+ * | 63:- | 47:40 | 39:32 | 31:16 | 15:0 |
225
+ */
226
+ .axis_tvalid ( p2p_down_valid ), // i, 1
227
+ .axis_tlast ( p2p_down_last ), // i, 1
228
+ .axis_tuser ( p2p_down_head ), // i, TUSER_WIDTH
229
+ .axis_tdata ( p2p_down_data ), // i, TDATA_WIDTH
230
+ .axis_tready ( p2p_down_ready ), // o, 1
231
+ /* -------input axis-like interface{end}------- */
232
+
233
+ /* -------output in_reg inteface{begin}------- */
234
+ /* *_head, valid only in first beat of a packet
235
+ * | Reserved |dst_dev| src_dev | Reserved | Byte length |
236
+ * | 63:- | 47:40 | 39:32 | 31:16 | 15:0 |
237
+ */
238
+ .axis_reg_tvalid ( st_p2p_down_valid ), // o, 1 // read valid from input register
239
+ .axis_reg_tlast ( st_p2p_down_last ), // o, 1
240
+ .axis_reg_tuser ( st_p2p_down_head ), // o, TUSER_WIDTH
241
+ .axis_reg_tdata ( st_p2p_down_data ), // o, TDATA_WIDTH
242
+ .axis_reg_tready ( st_p2p_down_ready ) // i, 1
243
+ /* -------output in_reg inteface{end}------- */
244
+ );
245
+ /* -------Payload Sending FSM{end}------- */
246
+
247
+ endmodule
ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/P2P/tgt_queue_struct.v ADDED
@@ -0,0 +1,293 @@
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1
+ `timescale 1ns / 100ps
2
+ //*************************************************************************
3
+ // > File : tgt_queue_struct.v
4
+ // > Author : Kangning
5
+ // > Date : 2022-08-31
6
+ // > Note : queue structure
7
+ //*************************************************************************
8
+
9
+ module tgt_queue_struct #(
10
+
11
+ ) (
12
+
13
+ input wire clk , // i, 1
14
+ input wire rst_n , // i, 1
15
+ // output reg init_end, // o, 1
16
+
17
+ /* --------P2P Configuration Channel{begin}-------- */
18
+ /* p2p_req head. We just write configuration space, and the byte_len is fixed to 8 bytes
19
+ * | 127 | 126:64 | 63:32 | 31:13 | 12:0 |
20
+ * | is_wr | Reserved | addr | Reserved | byte_len |
21
+ */
22
+ input wire p2p_cfg_req_valid, // i, 1
23
+ input wire p2p_cfg_req_last , // i, 1
24
+ input wire [`P2P_HEAD_W - 1 : 0] p2p_cfg_req_head , // i, `P2P_HEAD_W
25
+ input wire [`P2P_DATA_W - 1 : 0] p2p_cfg_req_data , // i, `P2P_DATA_W
26
+ output wire p2p_cfg_req_ready, // o, 1
27
+
28
+ // output wire p2p_cfg_rrsp_valid, // o, 1
29
+ // output wire p2p_cfg_rrsp_last , // o, 1
30
+ // output wire [`P2P_DATA_W - 1 : 0] p2p_cfg_rrsp_data , // o, `P2P_DATA_W
31
+ // input wire p2p_cfg_rrsp_ready, // i, 1
32
+ /* --------P2P Configuration Channel{end}-------- */
33
+
34
+ /* --------p2p mem descriptor in{begin}-------- */
35
+ /* p2p_req head. We just write mem descriptor space, and the byte_len is 8 byte aligned
36
+ * | 127 | 126:64 | 63:32 | 31:13 | 12:0 |
37
+ * | is_wr | Reserved | addr | Reserved | byte_len |
38
+ */
39
+ input wire p2p_mem_desc_req_valid, // i, 1
40
+ input wire p2p_mem_desc_req_last , // i, 1
41
+ input wire [`P2P_HEAD_W-1:0] p2p_mem_desc_req_head , // i, `P2P_HEAD_W
42
+ input wire [`P2P_DATA_W-1:0] p2p_mem_desc_req_data , // i, `P2P_DATA_W
43
+ output wire p2p_mem_desc_req_ready, // o, 1
44
+ /* --------p2p mem descriptor in{end}-------- */
45
+
46
+ /* --------allocated buffer address{begin}-------- */
47
+ input wire pbuf_alloc_valid , // i, 1
48
+ input wire pbuf_alloc_last , // i, 1
49
+ input wire [`BUF_ADDR_WIDTH-1:0] pbuf_alloc_buf_addr, // i, `BUF_ADDR_WIDTH
50
+ input wire [8 -1:0] pbuf_alloc_qnum , // i, 8
51
+ output wire pbuf_alloc_ready , // o, 1 ; assume it always asserts
52
+ /* --------allocated buffer address{end}-------- */
53
+
54
+ /* --------dropped queue{begin}-------- */
55
+ output wire dropped_wen , // o, 1
56
+ output wire [`QUEUE_NUM_LOG-1:0] dropped_qnum, // o, `QUEUE_NUM_LOG
57
+ /* --------dropped queue{end}-------- */
58
+
59
+ /* --------queue struct output for send processing{begin}-------- */
60
+ /* st_qstruct_head_ctx : qcontext of prepared queue
61
+ * st_qstruct_head_desc: payload descriptor
62
+ * st_qstruct_buf_addr : allocated buffer base address in P2P pyld_buf,
63
+ * this is an array. A valid addr outputs when valid
64
+ * and ready assert at the same time.
65
+ * st_qstruct_last : assert when the last st_qstruct_buf_addr is asserted
66
+ */
67
+ output wire st_qstruct_valid , // o, 1
68
+ output wire st_qstruct_last , // o, 1
69
+ output wire [`QUEUE_CONTEXT_WIDTH-1:0] st_qstruct_head_ctx , // o, `QUEUE_CONTEXT_WIDTH
70
+ output wire [`QUEUE_DESC_WIDTH -1:0] st_qstruct_head_desc, // o, `QUEUE_DESC_WIDTH
71
+ output wire [`BUF_ADDR_WIDTH -1:0] st_qstruct_buf_addr , // o, `BUF_ADDR_WIDTH
72
+ input wire st_qstruct_ready // i, 1
73
+ /* --------queue struct output for send processing{end}-------- */
74
+
75
+ `ifdef PCIEI_APB_DBG
76
+ /* -------APB reated signal{begin}------- */
77
+ ,input wire [(2*`QUEUE_NUM+1)*`SRAM_RW_DATA_W-1:0] rw_data // i, (2*`QUEUE_NUM+1)*`SRAM_RW_DATA_W
78
+ ,output wire [`TGT_QSTRUCT_SIGNAL_W-1:0] dbg_signal // o, `TGT_QSTRUCT_SIGNAL_W
79
+ /* -------APB reated signal{end}------- */
80
+ `endif
81
+ );
82
+
83
+ localparam QCTX_BYTE_LEN_LOG = 4; // byte len of one entry of target configure bar space, in log format
84
+
85
+ /* --------Queue context, cfg BAR space{begin}-------- */
86
+ wire [31:0] bar_cfg_addr;
87
+
88
+ wire qcontext_wen ;
89
+ wire [`QUEUE_NUM_LOG -1:0] qcontext_waddr;
90
+ wire [`QUEUE_CONTEXT_WIDTH-1:0] qcontext_din ;
91
+ wire qcontext_ren ;
92
+ wire [`QUEUE_NUM_LOG -1:0] qcontext_raddr;
93
+ wire [`QUEUE_CONTEXT_WIDTH-1:0] qcontext_dout ;
94
+ /* --------Queue context, cfg BAR space{end}-------- */
95
+
96
+ /* --------qstruct out{end}-------- */
97
+ reg qstruct_sop;
98
+
99
+ wire qstruct_valid ;
100
+ wire qstruct_last ;
101
+ wire [`QUEUE_DESC_WIDTH-1:0] qstruct_head_desc;
102
+ wire [`QUEUE_NUM_LOG -1:0] qstruct_head_qnum;
103
+ wire [`BUF_ADDR_WIDTH -1:0] qstruct_buf_addr ;
104
+ wire qstruct_ready ;
105
+ /* --------qstruct out{end}-------- */
106
+
107
+ `ifdef PCIEI_APB_DBG
108
+ /* -------APB reated signal{begin}------- */
109
+ wire [2*`QUEUE_NUM*`SRAM_RW_DATA_W-1:0] desc_que_rw_data;
110
+ wire [2-1:0] qcontext_rtsel;
111
+ wire [2-1:0] qcontext_wtsel;
112
+ wire [2-1:0] qcontext_ptsel;
113
+ wire [1-1:0] qcontext_vg ;
114
+ wire [1-1:0] qcontext_vs ;
115
+
116
+ wire [`QSTRUCT_TOP_SIGNAL_W-1:0] dbg_signal_qstruct_top;
117
+ wire [`DESC_QUEUE_SIGNAL_W -1:0] dbg_signal_desc_queue;
118
+ /* -------APB reated signal{end}------- */
119
+ `endif
120
+
121
+ //---------------------------------------------------------------------------------------------------------------------------
122
+
123
+ `ifdef PCIEI_APB_DBG
124
+ /* -------APB reated signal{begin}------- */
125
+ assign {
126
+ desc_que_rw_data,
127
+ qcontext_rtsel ,
128
+ qcontext_wtsel ,
129
+ qcontext_ptsel ,
130
+ qcontext_vg ,
131
+ qcontext_vs
132
+ } = rw_data;
133
+
134
+ assign dbg_signal = {
135
+ dbg_signal_qstruct_top,
136
+ dbg_signal_desc_queue
137
+ };
138
+
139
+ assign dbg_signal_qstruct_top = { // 268
140
+
141
+ bar_cfg_addr, // 32
142
+ qcontext_wen, qcontext_waddr, qcontext_din, qcontext_ren, qcontext_raddr, qcontext_dout, // 138
143
+ qstruct_sop, // 1
144
+ qstruct_valid, qstruct_last, qstruct_head_desc, qstruct_head_qnum, qstruct_buf_addr, qstruct_ready // 97
145
+ };
146
+ /* -------APB reated signal{end}------- */
147
+ `endif
148
+
149
+ /* --------Queue context, cfg BAR space{begin}-------- */
150
+ assign bar_cfg_addr = p2p_cfg_req_head[63:32];
151
+
152
+ pcieifc_sd_sram #(
153
+ .DATAWIDTH ( `QUEUE_CONTEXT_WIDTH ), // Memory data word width, 64
154
+ .ADDRWIDTH ( `QUEUE_NUM_LOG ) // Number of mem address bits, 4
155
+ ) qcontext (
156
+ .clk ( clk ), // i, 1
157
+ .rst_n ( rst_n ), // i, 1
158
+
159
+ .wea ( qcontext_wen ), // i, 1
160
+ .addra ( qcontext_waddr ), // i, ADDRWIDTH
161
+ .dina ( qcontext_din ), // i, DATAWIDTH
162
+
163
+ .reb ( qcontext_ren ), // i, 1
164
+ .addrb ( qcontext_raddr ), // i, ADDRWIDTH
165
+ .doutb ( qcontext_dout ) // o, DATAWIDTH
166
+
167
+ `ifdef PCIEI_APB_DBG
168
+ ,.rtsel ( 2'b0 ) // i, 2
169
+ ,.wtsel ( 2'b0 ) // i, 2
170
+ ,.ptsel ( 2'b0 ) // i, 2
171
+ ,.vg ( 1'b0 ) // i, 1
172
+ ,.vs ( 1'b0 ) // i, 1
173
+ `endif
174
+ );
175
+
176
+ assign qcontext_wen = p2p_cfg_req_valid;
177
+ assign qcontext_waddr = (bar_cfg_addr[19:0] - `CFG_BAR_TGT_ADDR_BASE) >> QCTX_BYTE_LEN_LOG;
178
+ assign qcontext_din = p2p_cfg_req_data;
179
+
180
+ assign qcontext_ren = qstruct_sop & qstruct_valid & qstruct_ready;
181
+ assign qcontext_raddr = qcontext_ren ? qstruct_head_qnum : 0;
182
+ /* --------Queue context, cfg BAR space{end}-------- */
183
+
184
+ /* --------Descriptor queue{begin}-------- */
185
+ tgt_desc_queue #(
186
+
187
+ ) tgt_desc_queue (
188
+
189
+ .clk ( clk ), // i, 1
190
+ .rst_n ( rst_n ), // i, 1
191
+
192
+ /* --------p2p mem descriptor in{begin}-------- */
193
+ .p2p_mem_desc_req_valid ( p2p_mem_desc_req_valid ), // i, 1
194
+ .p2p_mem_desc_req_last ( p2p_mem_desc_req_last ), // i, 1
195
+ .p2p_mem_desc_req_data ( p2p_mem_desc_req_data ), // i, `P2P_DATA_W
196
+ .p2p_mem_desc_req_head ( p2p_mem_desc_req_head ), // i, `P2P_HEAD_W
197
+ .p2p_mem_desc_req_ready ( p2p_mem_desc_req_ready ), // o, 1
198
+ /* --------p2p mem descriptor in{end}-------- */
199
+
200
+ /* --------allocated buffer address{begin}-------- */
201
+ .pbuf_alloc_valid ( pbuf_alloc_valid ), // i, 1
202
+ .pbuf_alloc_last ( pbuf_alloc_last ), // i, 1
203
+ .pbuf_alloc_buf_addr ( pbuf_alloc_buf_addr ), // i, 32
204
+ .pbuf_alloc_qnum ( pbuf_alloc_qnum ), // i, 8
205
+ .pbuf_alloc_ready ( pbuf_alloc_ready ), // o, 1
206
+ /* --------allocated buffer address{end}-------- */
207
+
208
+ /* --------dropped queue{begin}-------- */
209
+ .dropped_wen ( dropped_wen ), // o, 1
210
+ .dropped_qnum ( dropped_qnum ), // o, `QUEUE_NUM_LOG
211
+ /* --------dropped queue{end}-------- */
212
+
213
+ /* --------queue struct output for send processing{begin}-------- */
214
+ /* st_qstruct_head_desc: payload descriptor
215
+ * st_qstruct_buf_addr : allocated buffer base address in P2P pyld_buf,
216
+ * this is an array. A valid addr outputs when valid
217
+ * and ready assert at the same time.
218
+ * st_qstruct_last : assert when the last st_qstruct_buf_addr is asserted
219
+ */
220
+ .desc_out_valid ( qstruct_valid ), // o, 1
221
+ .desc_out_last ( qstruct_last ), // o, 1
222
+ .desc_out_head_desc ( qstruct_head_desc ), // o, `QUEUE_DESC_WIDTH
223
+ .desc_out_head_qnum ( qstruct_head_qnum ), // o, `QUEUE_NUM_LOG
224
+ .desc_out_buf_addr ( qstruct_buf_addr ), // o, `BUF_ADDR_WIDTH
225
+ .desc_out_ready ( qstruct_ready ) // i, 1
226
+ /* --------queue struct output for send processing{end}-------- */
227
+
228
+ `ifdef PCIEI_APB_DBG
229
+ /* -------APB reated signal{begin}------- */
230
+ ,.rw_data ( desc_que_rw_data ) // i, 2*`QUEUE_NUM*`SRAM_RW_DATA_W
231
+ ,.dbg_signal ( dbg_signal_desc_queue ) // o, `DESC_QUEUE_SIGNAL_W
232
+ /* -------APB reated signal{end}------- */
233
+ `endif
234
+ );
235
+ /* --------Descriptor queue{end}-------- */
236
+
237
+ /* --------P2P Configuration Channel{begin}-------- */
238
+ assign p2p_cfg_req_ready = 1;
239
+ /* --------P2P Configuration Channel{end}-------- */
240
+
241
+ /* --------qstruct out{begin}-------- */
242
+ always @(posedge clk, negedge rst_n) begin
243
+ if (~rst_n) begin
244
+ qstruct_sop <= `TD 1'd1;
245
+ end
246
+ else if (qstruct_valid & qstruct_ready & qstruct_last) begin
247
+ qstruct_sop <= `TD 1'd0;
248
+ end
249
+ else if (qstruct_valid & qstruct_ready) begin
250
+ qstruct_sop <= `TD 1'd1;
251
+ end
252
+ end
253
+
254
+ // read queue context
255
+ assign st_qstruct_head_ctx = qcontext_dout;
256
+ st_reg #(
257
+ .TUSER_WIDTH ( `QUEUE_DESC_WIDTH ),
258
+ .TDATA_WIDTH ( `BUF_ADDR_WIDTH )
259
+ ) st_reg2send (
260
+ .clk ( clk ), // i, 1
261
+ .rst_n ( rst_n ), // i, 1
262
+
263
+ /* -------input axis-like interface{begin}------- */
264
+ /* qstruct_head_desc: payload descriptor
265
+ * qstruct_buf_addr : allocated buffer base address in P2P pyld_buf,
266
+ * this is an array. A valid addr outputs when valid
267
+ * and ready assert at the same time.
268
+ * qstruct_last : assert when the last qstruct_buf_addr is asserted
269
+ */
270
+ .axis_tvalid ( qstruct_valid ), // i, 1
271
+ .axis_tlast ( qstruct_last ), // i, 1
272
+ .axis_tuser ( qstruct_head_desc ), // i, TUSER_WIDTH
273
+ .axis_tdata ( qstruct_buf_addr ), // i, TDATA_WIDTH
274
+ .axis_tready ( qstruct_ready ), // o, 1
275
+ /* -------input axis-like interface{end}------- */
276
+
277
+ /* -------output in_reg inteface{begin}------- */
278
+ /* qstruct_head_desc: payload descriptor
279
+ * qstruct_buf_addr : allocated buffer base address in P2P pyld_buf,
280
+ * this is an array. A valid addr outputs when valid
281
+ * and ready assert at the same time.
282
+ * qstruct_last : assert when the last qstruct_buf_addr is asserted
283
+ */
284
+ .axis_reg_tvalid ( st_qstruct_valid ), // o, 1 // read valid from input register
285
+ .axis_reg_tlast ( st_qstruct_last ), // o, 1
286
+ .axis_reg_tuser ( st_qstruct_head_desc ), // o, TUSER_WIDTH
287
+ .axis_reg_tdata ( st_qstruct_buf_addr ), // o, TDATA_WIDTH
288
+ .axis_reg_tready ( st_qstruct_ready ) // i, 1
289
+ /* -------output in_reg inteface{end}------- */
290
+ );
291
+ /* --------qstruct out{end}-------- */
292
+
293
+ endmodule