diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Common/SRAM_SDP_Template.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Common/SRAM_SDP_Template.v new file mode 100644 index 0000000000000000000000000000000000000000..bc3e6ea30b36f9cbf20f13cfe4ac2bdc2cf3d2d8 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Common/SRAM_SDP_Template.v @@ -0,0 +1,295 @@ +`timescale 1ns / 1ps + +`include "common_function_def.vh" + +module SRAM_SDP_Template #( + parameter RAM_WIDTH = 32, + parameter RAM_DEPTH = 32, + parameter ADDR_WIDTH = log2b(RAM_DEPTH - 1) +) +( + input wire clk, + input wire rst, + + input wire wea, + input wire [ADDR_WIDTH - 1 : 0] addra, + input wire [RAM_WIDTH - 1 : 0] dina, + + input wire [ADDR_WIDTH - 1 : 0] addrb, + output wire [RAM_WIDTH - 1 : 0] doutb +); + +//Resolve read-write collisions +reg wea_diff; +reg [ADDR_WIDTH - 1 : 0] addra_diff; +reg [RAM_WIDTH - 1 : 0] dina_diff; + +reg [ADDR_WIDTH - 1 : 0] addrb_diff; +wire [RAM_WIDTH - 1 : 0] doutb_fake; + +generate + if(RAM_WIDTH == 32 && RAM_DEPTH == 32) begin : GEN_BRAM_SDP_32W_32D + //Instantiate Xilinx IP + end + else if(RAM_WIDTH == 129 && RAM_DEPTH == 64) begin : GEN_BRAM_SDP_129W_64D + // BRAM_SDP_129w_64d BRAM_SDP_129w_64d_inst( + // .clka (clk), + // .wea (wea), + // .addra (addra), + // .dina (dina), + // .clkb (clk), + // .addrb (addrb), + // .doutb (doutb_fake) + // ); + + end + else if(RAM_WIDTH == 24 && RAM_DEPTH == 16384) begin : GEN_BRAM_SDP_24W_16384D + // BRAM_SDP_24w_16384d BRAM_SDP_24w_16384d_inst( + // .clka (clk), + // .wea (wea), + // .addra (addra), + // .dina (dina), + // .clkb (clk), + // .addrb (addrb), + // .doutb (doutb_fake) + // ); + + end + else if(RAM_WIDTH == 52 && RAM_DEPTH == 1) begin : GEN_BRAM_SDP_52W_1D + BRAM_SDP_52w_1d BRAM_SDP_52w_1d_inst( + .clka ( clk ), + .wea ( wea ), + .addra ( addra ), + .dina ( dina ), + .clkb ( clk ), + .addrb ( addrb ), + .doutb ( doutb_fake ) + ); + end + else if(RAM_WIDTH == 52 && RAM_DEPTH == 512) begin : GEN_BRAM_SDP_52W_512D + BRAM_SDP_52w_512d BRAM_SDP_52w_512d_inst( + .clka ( clk ), + .wea ( wea ), + .addra ( addra ), + .dina ( dina ), + .clkb ( clk ), + .addrb ( addrb ), + .doutb ( doutb_fake ) + ); + end + else if(RAM_WIDTH == 52 && RAM_DEPTH == 1024) begin : GEN_BRAM_SDP_52W_1024D + BRAM_SDP_52w_1024d BRAM_SDP_52w_1024d_inst( + .clka ( clk ), + .wea ( wea ), + .addra ( addra ), + .dina ( dina ), + .clkb ( clk ), + .addrb ( addrb ), + .doutb ( doutb_fake ) + ); + end + else if(RAM_WIDTH == 52 && RAM_DEPTH == 8192) begin : GEN_BRAM_SDP_52W_8192D + BRAM_SDP_52w_8192d BRAM_SDP_52w_8192d_inst( + .clka ( clk ), + .wea ( wea ), + .addra ( addra ), + .dina ( dina ), + .clkb ( clk ), + .addrb ( addrb ), + .doutb ( doutb_fake ) + ); + end + else if(RAM_WIDTH == 128 && RAM_DEPTH == 1024) begin : GEN_BRAM_SDP_128W_1024D + BRAM_SDP_128w_1024d BRAM_SDP_128w_1024d_inst( + .clka ( clk ), + .wea ( wea ), + .addra ( addra ), + .dina ( dina ), + .clkb ( clk ), + .addrb ( addrb ), + .doutb ( doutb_fake ) + ); + end + else if(RAM_WIDTH == 128 && RAM_DEPTH == 32768) begin : GEN_BRAM_SDP_128W_32768D + BRAM_SDP_128w_32768d BRAM_SDP_128w_32768d_inst( + .clka ( clk ), + .wea ( wea ), + .addra ( addra ), + .dina ( dina ), + .clkb ( clk ), + .addrb ( addrb ), + .doutb ( doutb_fake ) + ); + end + else if(RAM_WIDTH == 1 && RAM_DEPTH == 256) begin : GEN_BRAM_SDP_1W_256D + BRAM_SDP_1w_256d BRAM_SDP_1w_256d_inst( + .clka ( clk ), + .wea ( wea ), + .addra ( addra ), + .dina ( dina ), + .clkb ( clk ), + .addrb ( addrb ), + .doutb ( doutb_fake ) + ); + end + else if(RAM_WIDTH == 8 && RAM_DEPTH == 32) begin : GEN_BRAM_SDP_8W_32D + BRAM_SDP_8w_32d BRAM_SDP_8w_32d_inst( + .clka ( clk ), + .wea ( wea ), + .addra ( addra ), + .dina ( dina ), + .clkb ( clk ), + .addrb ( addrb ), + .doutb ( doutb_fake ) + ); + end + else if(RAM_WIDTH == 8 && RAM_DEPTH == 128) begin : GEN_BRAM_SDP_8W_128D + BRAM_SDP_8w_128d BRAM_SDP_8w_128d_inst( + .clka ( clk ), + .wea ( wea ), + .addra ( addra ), + .dina ( dina ), + .clkb ( clk ), + .addrb ( addrb ), + .doutb ( doutb_fake ) + ); + end + else if(RAM_WIDTH == 32 && RAM_DEPTH == 256) begin : GEN_BRAM_SDP_32W_256D + BRAM_SDP_32w_256d BRAM_SDP_32w_256d_inst( + .clka ( clk ), + .wea ( wea ), + .addra ( addra ), + .dina ( dina ), + .clkb ( clk ), + .addrb ( addrb ), + .doutb ( doutb_fake ) + ); + end + else if(RAM_WIDTH == 416 && RAM_DEPTH == 32) begin : GEN_BRAM_SDP_416W_32D + BRAM_SDP_416w_32d BRAM_SDP_416w_32d_inst( + .clka ( clk ), + .wea ( wea ), + .addra ( addra ), + .dina ( dina ), + .clkb ( clk ), + .addrb ( addrb ), + .doutb ( doutb_fake ) + ); + end + else if(RAM_WIDTH == 128 && RAM_DEPTH == 32) begin : GEN_BRAM_SDP_128W_32D + BRAM_SDP_128w_32d BRAM_SDP_128w_32d_inst( + .clka ( clk ), + .wea ( wea ), + .addra ( addra ), + .dina ( dina ), + .clkb ( clk ), + .addrb ( addrb ), + .doutb ( doutb_fake ) + ); + end + else if(RAM_WIDTH == 641 && RAM_DEPTH == 32) begin : GEN_BRAM_SDP_641W_32D + BRAM_SDP_641w_32d BRAM_SDP_641w_32d_inst( + .clka ( clk ), + .wea ( wea ), + .addra ( addra ), + .dina ( dina ), + .clkb ( clk ), + .addrb ( addrb ), + .doutb ( doutb_fake ) + ); + end + else if(RAM_WIDTH == 161 && RAM_DEPTH == 32) begin : GEN_BRAM_SDP_161W_32D + BRAM_SDP_161w_32d BRAM_SDP_161w_32d_inst( + .clka ( clk ), + .wea ( wea ), + .addra ( addra ), + .dina ( dina ), + .clkb ( clk ), + .addrb ( addrb ), + .doutb ( doutb_fake ) + ); + end + else if(RAM_WIDTH == 225 && RAM_DEPTH == 32) begin : GEN_BRAM_SDP_225W_32D + BRAM_SDP_225w_32d BRAM_SDP_225w_32d_inst( + .clka ( clk ), + .wea ( wea ), + .addra ( addra ), + .dina ( dina ), + .clkb ( clk ), + .addrb ( addrb ), + .doutb ( doutb_fake ) + ); + end + else if(RAM_WIDTH == 24 && RAM_DEPTH == 256) begin : GEN_BRAM_SDP_24W_256D + BRAM_SDP_24w_256d BRAM_SDP_24w_256d_inst( + .clka ( clk ), + .wea ( wea ), + .addra ( addra ), + .dina ( dina ), + .clkb ( clk ), + .addrb ( addrb ), + .doutb ( doutb_fake ) + ); + end + else if(RAM_WIDTH == 416 && RAM_DEPTH == 256) begin : GEN_BRAM_SDP_416W_256D + BRAM_SDP_416w_256d BRAM_SDP_416w_256d_inst( + .clka ( clk ), + .wea ( wea ), + .addra ( addra ), + .dina ( dina ), + .clkb ( clk ), + .addrb ( addrb ), + .doutb ( doutb_fake ) + ); + end + else if(RAM_WIDTH == 8 && RAM_DEPTH == 256) begin : GEN_BRAM_SDP_8W_256D + BRAM_SDP_8w_256d BRAM_SDP_8w_256d_inst( + .clka ( clk ), + .wea ( wea ), + .addra ( addra ), + .dina ( dina ), + .clkb ( clk ), + .addrb ( addrb ), + .doutb ( doutb_fake ) + ); + end + else if(RAM_WIDTH == 128 && RAM_DEPTH == 256) begin : GEN_BRAM_SDP_128W_256D + BRAM_SDP_128w_256d BRAM_SDP_128w_256d_inst( + .clka ( clk ), + .wea ( wea ), + .addra ( addra ), + .dina ( dina ), + .clkb ( clk ), + .addrb ( addrb ), + .doutb ( doutb_fake ) + ); + end +endgenerate + +always @(posedge clk or posedge rst) begin + if(rst) begin + wea_diff <= 'd0; + addra_diff <= 'd0; + dina_diff <= 'd0; + + addrb_diff <= 'd0; + end + else begin + wea_diff <= wea; + addra_diff <= addra; + dina_diff <= dina; + + addrb_diff <= addrb; + end +end + +assign doutb = (wea_diff && (addra_diff == addrb_diff)) ? dina_diff : doutb_fake; + +/*Debug subsystem : Begin*/ +`ifdef DEBUG_ON + +`endif +/*Debug subsystem : End*/ + + +endmodule diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Common/SRAM_TDP_Template.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Common/SRAM_TDP_Template.v new file mode 100644 index 0000000000000000000000000000000000000000..34173643fdf5226be873bdc36a30fbf7440d45e9 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Common/SRAM_TDP_Template.v @@ -0,0 +1,817 @@ +`timescale 1ns / 1ps + +`include "common_function_def.vh" + +module SRAM_TDP_Template #( + parameter RAM_WIDTH = 32, + parameter RAM_DEPTH = 32, + parameter ADDR_WIDTH = log2b(RAM_DEPTH - 1) +) +( + input wire clk, + input wire rst, + + input wire wea, + input wire [ADDR_WIDTH - 1 : 0] addra, + input wire [RAM_WIDTH - 1 : 0] dina, + output wire [RAM_WIDTH - 1 : 0] douta, + + input wire web, + input wire [ADDR_WIDTH - 1 : 0] addrb, + input wire [RAM_WIDTH - 1 : 0] dinb, + output wire [RAM_WIDTH - 1 : 0] doutb +); + +wire [RAM_WIDTH - 1 : 0] douta_fake; +wire [RAM_WIDTH - 1 : 0] doutb_fake; + +generate + if(RAM_WIDTH == 1 && RAM_DEPTH == 4096) begin : GEN_BRAM_TDP_1W_4096D + BRAM_TDP_1w_4096d BRAM_TDP_1w_4096d_Inst( + .clka ( clk ), + .rsta ( rst ), + .wea ( wea ), + .addra ( addra ), + .dina ( dina ), + .douta ( douta_fake ), + .clkb ( clk ), + .rstb ( rst ), + .web ( web ), + .addrb ( addrb ), + .dinb ( dinb ), + .doutb ( doutb_fake ) + ); + end + else if(RAM_WIDTH == 76 && RAM_DEPTH == 4096) begin : GEN_BRAM_TDP_76W_4096D + BRAM_TDP_76w_4096d BRAM_TDP_76w_4096d_Inst( + .clka ( clk ), + .rsta ( rst ), + .wea ( wea ), + .addra ( addra ), + .dina ( dina ), + .douta ( douta_fake ), + .clkb ( clk ), + .rstb ( rst ), + .web ( web ), + .addrb ( addrb ), + .dinb ( dinb ), + .doutb ( doutb_fake ) + ); + end + else if(RAM_WIDTH == 87 && RAM_DEPTH == 2) begin : GEN_BRAM_TDP_87W_2D //Test cache miss case, MTT CACHE_SET_NUM = 2 + BRAM_TDP_87w_2d BRAM_TDP_87w_2d_Inst( + .clka ( clk ), + .rsta ( rst ), + .wea ( wea ), + .addra ( addra ), + .dina ( dina ), + .douta ( douta_fake ), + .clkb ( clk ), + .rstb ( rst ), + .web ( web ), + .addrb ( addrb ), + .dinb ( dinb ), + .doutb ( doutb_fake ) + ); + end + else if(RAM_WIDTH == 340 && RAM_DEPTH == 2) begin : GEN_BRAM_TDP_340W_2D //Test cache miss case, MPT CACHE_SET_NUM = 2 + BRAM_TDP_340w_2d BRAM_TDP_340w_2d_Inst( + .clka ( clk ), + .rsta ( rst ), + .wea ( wea ), + .addra ( addra ), + .dina ( dina ), + .douta ( douta_fake ), + .clkb ( clk ), + .rstb ( rst ), + .web ( web ), + .addrb ( addrb ), + .dinb ( dinb ), + .doutb ( doutb_fake ) + ); + end + else if(RAM_WIDTH == 143 && RAM_DEPTH == 2) begin : GEN_BRAM_TDP_143W_2D //Test cache miss case, CQC CACHE_SET_NUM = 2 + BRAM_TDP_143w_2d BRAM_TDP_143w_2d_Inst( + .clka ( clk ), + .rsta ( rst ), + .wea ( wea ), + .addra ( addra ), + .dina ( dina ), + .douta ( douta_fake ), + .clkb ( clk ), + .rstb ( rst ), + .web ( web ), + .addrb ( addrb ), + .dinb ( dinb ), + .doutb ( doutb_fake ) + ); + end + else if(RAM_WIDTH == 102 && RAM_DEPTH == 2) begin : GEN_BRAM_TDP_102W_2D //Test cache miss case, EQC CACHE_SET_NUM = 2 + BRAM_TDP_102w_2d BRAM_TDP_102w_2d_Inst( + .clka ( clk ), + .rsta ( rst ), + .wea ( wea ), + .addra ( addra ), + .dina ( dina ), + .douta ( douta_fake ), + .clkb ( clk ), + .rstb ( rst ), + .web ( web ), + .addrb ( addrb ), + .dinb ( dinb ), + .doutb ( doutb_fake ) + ); + end + else if(RAM_WIDTH == 431 && RAM_DEPTH == 2) begin : GEN_BRAM_TDP_431W_2D //Test cache miss case, QPC CACHE_SET_NUM = 2 + BRAM_TDP_431w_2d BRAM_TDP_431w_2d_Inst( + .clka ( clk ), + .rsta ( rst ), + .wea ( wea ), + .addra ( addra ), + .dina ( dina ), + .douta ( douta_fake ), + .clkb ( clk ), + .rstb ( rst ), + .web ( web ), + .addrb ( addrb ), + .dinb ( dinb ), + .doutb ( doutb_fake ) + ); + end + else if(RAM_WIDTH == 1 && RAM_DEPTH == 2) begin : GEN_BRAM_TDP_1W_2D //Test cache miss case, LRU Table + BRAM_TDP_1w_2d BRAM_TDP_1w_2d_Inst( + .clka ( clk ), + .rsta ( rst ), + .wea ( wea ), + .addra ( addra ), + .dina ( dina ), + .douta ( douta_fake ), + .clkb ( clk ), + .rstb ( rst ), + .web ( web ), + .addrb ( addrb ), + .dinb ( dinb ), + .doutb ( doutb_fake ) + ); + end + else if(RAM_WIDTH == 2 && RAM_DEPTH == 128) begin : GEN_BRAM_TDP_2W_128D + BRAM_TDP_2w_128d BRAM_TDP_2w_128d_Inst( + .clka ( clk ), + .rsta ( rst ), + .wea ( wea ), + .addra ( addra ), + .dina ( dina ), + .douta ( douta_fake ), + .clkb ( clk ), + .rstb ( rst ), + .web ( web ), + .addrb ( addrb ), + .dinb ( dinb ), + .doutb ( doutb_fake ) + ); + end + else if(RAM_WIDTH == 8 && RAM_DEPTH == 128) begin : GEN_BRAM_TDP_8W_128D + BRAM_TDP_8w_128d BRAM_TDP_8w_128d_Inst( + .clka ( clk ), + .rsta ( rst ), + .wea ( wea ), + .addra ( addra ), + .dina ( dina ), + .douta ( douta_fake ), + .clkb ( clk ), + .rstb ( rst ), + .web ( web ), + .addrb ( addrb ), + .dinb ( dinb ), + .doutb ( doutb_fake ) + ); + end + else if(RAM_WIDTH == 1 && RAM_DEPTH == 512) begin : GEN_BRAM_TDP_1W_512D + BRAM_TDP_1w_512d BRAM_TDP_1w_512d_Inst( + .clka ( clk ), + .rsta ( rst ), + .wea ( wea ), + .addra ( addra ), + .dina ( dina ), + .douta ( douta_fake ), + .clkb ( clk ), + .rstb ( rst ), + .web ( web ), + .addrb ( addrb ), + .dinb ( dinb ), + .doutb ( doutb_fake ) + ); + end + else if(RAM_WIDTH == 332 && RAM_DEPTH == 512) begin : GEN_BRAM_TDP_332W_512D + BRAM_TDP_332w_512d BRAM_TDP_332w_512d_Inst( + .clka ( clk ), + .rsta ( rst ), + .wea ( wea ), + .addra ( addra ), + .dina ( dina ), + .douta ( douta_fake ), + .clkb ( clk ), + .rstb ( rst ), + .web ( web ), + .addrb ( addrb ), + .dinb ( dinb ), + .doutb ( doutb_fake ) + ); + end + else if(RAM_WIDTH == 82 && RAM_DEPTH == 4096) begin : GEN_BRAM_TDP_82W_4096D + BRAM_TDP_82w_4096d BRAM_TDP_82w_4096d_Inst( + .clka ( clk ), + .rsta ( rst ), + .wea ( wea ), + .addra ( addra ), + .dina ( dina ), + .douta ( douta_fake ), + .clkb ( clk ), + .rstb ( rst ), + .web ( web ), + .addrb ( addrb ), + .dinb ( dinb ), + .doutb ( doutb_fake ) + ); + end + else if(RAM_WIDTH == 99 && RAM_DEPTH == 16) begin : GEN_BRAM_TDP_99W_16D + BRAM_TDP_99w_16d BRAM_TDP_99w_16d_Inst( + .clka ( clk ), + .rsta ( rst ), + .wea ( wea ), + .addra ( addra ), + .dina ( dina ), + .douta ( douta_fake ), + .clkb ( clk ), + .rstb ( rst ), + .web ( web ), + .addrb ( addrb ), + .dinb ( dinb ), + .doutb ( doutb_fake ) + ); + end + else if(RAM_WIDTH == 136 && RAM_DEPTH == 256) begin : GEN_BRAM_TDP_136W_256D + BRAM_TDP_136w_256d BRAM_TDP_136w_256d_Inst( + .clka ( clk ), + .rsta ( rst ), + .wea ( wea ), + .addra ( addra ), + .dina ( dina ), + .douta ( douta_fake ), + .clkb ( clk ), + .rstb ( rst ), + .web ( web ), + .addrb ( addrb ), + .dinb ( dinb ), + .doutb ( doutb_fake ) + ); + end + else if(RAM_WIDTH == 424 && RAM_DEPTH == 256) begin : GEN_BRAM_TDP_424W_256D + BRAM_TDP_424w_256d BRAM_TDP_424w_256d_Inst( + .clka ( clk ), + .rsta ( rst ), + .wea ( wea ), + .addra ( addra ), + .dina ( dina ), + .douta ( douta_fake ), + .clkb ( clk ), + .rstb ( rst ), + .web ( web ), + .addrb ( addrb ), + .dinb ( dinb ), + .doutb ( doutb_fake ) + ); + end + else if(RAM_WIDTH == 52 && RAM_DEPTH == 8192) begin : GEN_BRAM_TDP_52W_8192D + BRAM_TDP_52w_8192d BRAM_TDP_52w_8192d_Inst( + .clka ( clk ), + .rsta ( rst ), + .wea ( wea ), + .addra ( addra ), + .dina ( dina ), + .douta ( douta_fake ), + .clkb ( clk ), + .rstb ( rst ), + .web ( web ), + .addrb ( addrb ), + .dinb ( dinb ), + .doutb ( doutb_fake ) + ); + end + else if(RAM_WIDTH == 24 && RAM_DEPTH == 256) begin : GEN_BRAM_TDP_24W_256D + BRAM_TDP_24w_256d BRAM_TDP_24w_256d_Inst( + .clka ( clk ), + .rsta ( rst ), + .wea ( wea ), + .addra ( addra ), + .dina ( dina ), + .douta ( douta_fake ), + .clkb ( clk ), + .rstb ( rst ), + .web ( web ), + .addrb ( addrb ), + .dinb ( dinb ), + .doutb ( doutb_fake ) + ); + end + else if(RAM_WIDTH == 5 && RAM_DEPTH == 16) begin : GEN_BRAM_TDP_5W_16D + BRAM_TDP_5w_16d BRAM_TDP_5w_16d_Inst( + .clka ( clk ), + .rsta ( rst ), + .wea ( wea ), + .addra ( addra ), + .dina ( dina ), + .douta ( douta_fake ), + .clkb ( clk ), + .rstb ( rst ), + .web ( web ), + .addrb ( addrb ), + .dinb ( dinb ), + .doutb ( doutb_fake ) + ); + end + else if(RAM_WIDTH == 6 && RAM_DEPTH == 16) begin : GEN_BRAM_TDP_6W_16D + BRAM_TDP_6w_16d BRAM_TDP_6w_16d_Inst( + .clka ( clk ), + .rsta ( rst ), + .wea ( wea ), + .addra ( addra ), + .dina ( dina ), + .douta ( douta_fake ), + .clkb ( clk ), + .rstb ( rst ), + .web ( web ), + .addrb ( addrb ), + .dinb ( dinb ), + .doutb ( doutb_fake ) + ); + end + else if(RAM_WIDTH == 512 && RAM_DEPTH == 32) begin : GEN_BRAM_TDP_512W_32D + BRAM_TDP_512w_32d BRAM_TDP_512w_32d_Inst( + .clka ( clk ), + .rsta ( rst ), + .wea ( wea ), + .addra ( addra ), + .dina ( dina ), + .douta ( douta_fake ), + .clkb ( clk ), + .rstb ( rst ), + .web ( web ), + .addrb ( addrb ), + .dinb ( dinb ), + .doutb ( doutb_fake ) + ); + end + else if(RAM_WIDTH == 1 && RAM_DEPTH == 16) begin : GEN_BRAM_TDP_1W_16D + BRAM_TDP_1w_16d BRAM_TDP_1w_16d_Inst( + .clka ( clk ), + .rsta ( rst ), + .wea ( wea ), + .addra ( addra ), + .dina ( dina ), + .douta ( douta_fake ), + .clkb ( clk ), + .rstb ( rst ), + .web ( web ), + .addrb ( addrb ), + .dinb ( dinb ), + .doutb ( doutb_fake ) + ); + end + else if(RAM_WIDTH == 1 && RAM_DEPTH == 256) begin : GEN_BRAM_TDP_1W_256D + BRAM_TDP_1w_256d BRAM_TDP_1w_256d_Inst( + .clka ( clk ), + .rsta ( rst ), + .wea ( wea ), + .addra ( addra ), + .dina ( dina ), + .douta ( douta_fake ), + .clkb ( clk ), + .rstb ( rst ), + .web ( web ), + .addrb ( addrb ), + .dinb ( dinb ), + .doutb ( doutb_fake ) + ); + end + else if(RAM_WIDTH == 5 && RAM_DEPTH == 256) begin : GEN_BRAM_TDP_5W_256D + BRAM_TDP_5w_256d BRAM_TDP_5w_256d_Inst( + .clka ( clk ), + .rsta ( rst ), + .wea ( wea ), + .addra ( addra ), + .dina ( dina ), + .douta ( douta_fake ), + .clkb ( clk ), + .rstb ( rst ), + .web ( web ), + .addrb ( addrb ), + .dinb ( dinb ), + .doutb ( doutb_fake ) + ); + end + else if(RAM_WIDTH == 5 && RAM_DEPTH == 32) begin : GEN_BRAM_TDP_5W_32D + BRAM_TDP_5w_32d BRAM_TDP_5w_32d_Inst( + .clka ( clk ), + .rsta ( rst ), + .wea ( wea ), + .addra ( addra ), + .dina ( dina ), + .douta ( douta_fake ), + .clkb ( clk ), + .rstb ( rst ), + .web ( web ), + .addrb ( addrb ), + .dinb ( dinb ), + .doutb ( doutb_fake ) + ); + end + else if(RAM_WIDTH == 98 && RAM_DEPTH == 32) begin : GEN_BRAM_TDP_98W_32D + BRAM_TDP_98w_32d BRAM_TDP_98w_32d_Inst( + .clka ( clk ), + .rsta ( rst ), + .wea ( wea ), + .addra ( addra ), + .dina ( dina ), + .douta ( douta_fake ), + .clkb ( clk ), + .rstb ( rst ), + .web ( web ), + .addrb ( addrb ), + .dinb ( dinb ), + .doutb ( doutb_fake ) + ); + end + else if(RAM_WIDTH == 418 && RAM_DEPTH == 32) begin : GEN_BRAM_TDP_418W_32D + BRAM_TDP_418w_32d BRAM_TDP_418w_32d_Inst( + .clka ( clk ), + .rsta ( rst ), + .wea ( wea ), + .addra ( addra ), + .dina ( dina ), + .douta ( douta_fake ), + .clkb ( clk ), + .rstb ( rst ), + .web ( web ), + .addrb ( addrb ), + .dinb ( dinb ), + .doutb ( doutb_fake ) + ); + end + else if(RAM_WIDTH == 130 && RAM_DEPTH == 32) begin : GEN_BRAM_TDP_130W_32D + BRAM_TDP_130w_32d BRAM_TDP_130w_32d_Inst( + .clka ( clk ), + .rsta ( rst ), + .wea ( wea ), + .addra ( addra ), + .dina ( dina ), + .douta ( douta_fake ), + .clkb ( clk ), + .rstb ( rst ), + .web ( web ), + .addrb ( addrb ), + .dinb ( dinb ), + .doutb ( doutb_fake ) + ); + end + else if(RAM_WIDTH == 322 && RAM_DEPTH == 32) begin : GEN_BRAM_TDP_322W_32D + BRAM_TDP_322w_32d BRAM_TDP_322w_32d_Inst( + .clka ( clk ), + .rsta ( rst ), + .wea ( wea ), + .addra ( addra ), + .dina ( dina ), + .douta ( douta_fake ), + .clkb ( clk ), + .rstb ( rst ), + .web ( web ), + .addrb ( addrb ), + .dinb ( dinb ), + .doutb ( doutb_fake ) + ); + end + else if(RAM_WIDTH == 192 && RAM_DEPTH == 32) begin : GEN_BRAM_TDP_192W_32D + BRAM_TDP_192w_32d BRAM_TDP_192w_32d_Inst( + .clka ( clk ), + .rsta ( rst ), + .wea ( wea ), + .addra ( addra ), + .dina ( dina ), + .douta ( douta_fake ), + .clkb ( clk ), + .rstb ( rst ), + .web ( web ), + .addrb ( addrb ), + .dinb ( dinb ), + .doutb ( doutb_fake ) + ); + end + else if(RAM_WIDTH == 12 && RAM_DEPTH == 32) begin : GEN_BRAM_TDP_12W_32D + BRAM_TDP_12w_32d BRAM_TDP_12w_32d_Inst( + .clka ( clk ), + .rsta ( rst ), + .wea ( wea ), + .addra ( addra ), + .dina ( dina ), + .douta ( douta_fake ), + .clkb ( clk ), + .rstb ( rst ), + .web ( web ), + .addrb ( addrb ), + .dinb ( dinb ), + .doutb ( doutb_fake ) + ); + end + else if(RAM_WIDTH == 44 && RAM_DEPTH == 32) begin : GEN_BRAM_TDP_44W_32D + BRAM_TDP_44w_32d BRAM_TDP_44w_32d_Inst( + .clka ( clk ), + .rsta ( rst ), + .wea ( wea ), + .addra ( addra ), + .dina ( dina ), + .douta ( douta_fake ), + .clkb ( clk ), + .rstb ( rst ), + .web ( web ), + .addrb ( addrb ), + .dinb ( dinb ), + .doutb ( doutb_fake ) + ); + end + else if(RAM_WIDTH == 576 && RAM_DEPTH == 32) begin : GEN_BRAM_TDP_576W_32D + BRAM_TDP_576w_32d BRAM_TDP_576w_32d_Inst( + .clka ( clk ), + .rsta ( rst ), + .wea ( wea ), + .addra ( addra ), + .dina ( dina ), + .douta ( douta_fake ), + .clkb ( clk ), + .rstb ( rst ), + .web ( web ), + .addrb ( addrb ), + .dinb ( dinb ), + .doutb ( doutb_fake ) + ); + end + else if(RAM_WIDTH == 6 && RAM_DEPTH == 256) begin : GEN_BRAM_TDP_6W_256D + BRAM_TDP_6w_256d BRAM_TDP_6w_256d_Inst( + .clka ( clk ), + .rsta ( rst ), + .wea ( wea ), + .addra ( addra ), + .dina ( dina ), + .douta ( douta_fake ), + .clkb ( clk ), + .rstb ( rst ), + .web ( web ), + .addrb ( addrb ), + .dinb ( dinb ), + .doutb ( doutb_fake ) + ); + end + else if(RAM_WIDTH == 6 && RAM_DEPTH == 64) begin : GEN_BRAM_TDP_6W_64D + BRAM_TDP_6w_64d BRAM_TDP_6w_64d_Inst( + .clka ( clk ), + .rsta ( rst ), + .wea ( wea ), + .addra ( addra ), + .dina ( dina ), + .douta ( douta_fake ), + .clkb ( clk ), + .rstb ( rst ), + .web ( web ), + .addrb ( addrb ), + .dinb ( dinb ), + .doutb ( doutb_fake ) + ); + end + else if(RAM_WIDTH == 256 && RAM_DEPTH == 64) begin : GEN_BRAM_TDP_256W_64D + BRAM_TDP_256w_64d BRAM_TDP_256w_64d_Inst( + .clka ( clk ), + .rsta ( rst ), + .wea ( wea ), + .addra ( addra ), + .dina ( dina ), + .douta ( douta_fake ), + .clkb ( clk ), + .rstb ( rst ), + .web ( web ), + .addrb ( addrb ), + .dinb ( dinb ), + .doutb ( doutb_fake ) + ); + end + else if(RAM_WIDTH == 512 && RAM_DEPTH == 512) begin : GEN_BRAM_TDP_512W_512D + BRAM_TDP_512w_512d BRAM_TDP_512w_512d_Inst( + .clka ( clk ), + .rsta ( rst ), + .wea ( wea ), + .addra ( addra ), + .dina ( dina ), + .douta ( douta_fake ), + .clkb ( clk ), + .rstb ( rst ), + .web ( web ), + .addrb ( addrb ), + .dinb ( dinb ), + .doutb ( doutb_fake ) + ); + end + else if(RAM_WIDTH == 9 && RAM_DEPTH == 512) begin : GEN_BRAM_TDP_9W_512D + BRAM_TDP_9w_512d BRAM_TDP_9w_512d_Inst( + .clka ( clk ), + .rsta ( rst ), + .wea ( wea ), + .addra ( addra ), + .dina ( dina ), + .douta ( douta_fake ), + .clkb ( clk ), + .rstb ( rst ), + .web ( web ), + .addrb ( addrb ), + .dinb ( dinb ), + .doutb ( doutb_fake ) + ); + end + else if(RAM_WIDTH == 488 && RAM_DEPTH == 32) begin : GEN_BRAM_TDP_488W_32D + BRAM_TDP_488w_32d BRAM_TDP_488w_32d_Inst( + .clka ( clk ), + .rsta ( rst ), + .wea ( wea ), + .addra ( addra ), + .dina ( dina ), + .douta ( douta_fake ), + .clkb ( clk ), + .rstb ( rst ), + .web ( web ), + .addrb ( addrb ), + .dinb ( dinb ), + .doutb ( doutb_fake ) + ); + end + else if(RAM_WIDTH == 352 && RAM_DEPTH == 32) begin : GEN_BRAM_TDP_352W_32D + BRAM_TDP_352w_32d BRAM_TDP_352w_32d_Inst( + .clka ( clk ), + .rsta ( rst ), + .wea ( wea ), + .addra ( addra ), + .dina ( dina ), + .douta ( douta_fake ), + .clkb ( clk ), + .rstb ( rst ), + .web ( web ), + .addrb ( addrb ), + .dinb ( dinb ), + .doutb ( doutb_fake ) + ); + end + else if(RAM_WIDTH == 192 && RAM_DEPTH == 256) begin : GEN_BRAM_TDP_192W_256D + BRAM_TDP_192w_256d BRAM_TDP_192w_256d_Inst( + .clka ( clk ), + .rsta ( rst ), + .wea ( wea ), + .addra ( addra ), + .dina ( dina ), + .douta ( douta_fake ), + .clkb ( clk ), + .rstb ( rst ), + .web ( web ), + .addrb ( addrb ), + .dinb ( dinb ), + .doutb ( doutb_fake ) + ); + end + else if(RAM_WIDTH == 44 && RAM_DEPTH == 256) begin : GEN_BRAM_TDP_44W_256D + BRAM_TDP_44w_256d BRAM_TDP_44w_256d_Inst( + .clka ( clk ), + .rsta ( rst ), + .wea ( wea ), + .addra ( addra ), + .dina ( dina ), + .douta ( douta_fake ), + .clkb ( clk ), + .rstb ( rst ), + .web ( web ), + .addrb ( addrb ), + .dinb ( dinb ), + .doutb ( doutb_fake ) + ); + end + else if(RAM_WIDTH == 322 && RAM_DEPTH == 256) begin : GEN_BRAM_TDP_322W_256D + BRAM_TDP_322w_256d BRAM_TDP_322w_256d_Inst( + .clka ( clk ), + .rsta ( rst ), + .wea ( wea ), + .addra ( addra ), + .dina ( dina ), + .douta ( douta_fake ), + .clkb ( clk ), + .rstb ( rst ), + .web ( web ), + .addrb ( addrb ), + .dinb ( dinb ), + .doutb ( doutb_fake ) + ); + end + else if(RAM_WIDTH == 130 && RAM_DEPTH == 256) begin : GEN_BRAM_TDP_130W_256D + BRAM_TDP_130w_256d BRAM_TDP_130w_256d_Inst( + .clka ( clk ), + .rsta ( rst ), + .wea ( wea ), + .addra ( addra ), + .dina ( dina ), + .douta ( douta_fake ), + .clkb ( clk ), + .rstb ( rst ), + .web ( web ), + .addrb ( addrb ), + .dinb ( dinb ), + .doutb ( doutb_fake ) + ); + end + else if(RAM_WIDTH == 98 && RAM_DEPTH == 256) begin : GEN_BRAM_TDP_98W_256D + BRAM_TDP_98w_256d BRAM_TDP_98w_256d_Inst( + .clka ( clk ), + .rsta ( rst ), + .wea ( wea ), + .addra ( addra ), + .dina ( dina ), + .douta ( douta_fake ), + .clkb ( clk ), + .rstb ( rst ), + .web ( web ), + .addrb ( addrb ), + .dinb ( dinb ), + .doutb ( doutb_fake ) + ); + end + else if(RAM_WIDTH == 418 && RAM_DEPTH == 256) begin : GEN_BRAM_TDP_418W_256D + BRAM_TDP_418w_256d BRAM_TDP_418w_256d_Inst( + .clka ( clk ), + .rsta ( rst ), + .wea ( wea ), + .addra ( addra ), + .dina ( dina ), + .douta ( douta_fake ), + .clkb ( clk ), + .rstb ( rst ), + .web ( web ), + .addrb ( addrb ), + .dinb ( dinb ), + .doutb ( doutb_fake ) + ); + end +endgenerate + +//Resolve read-write collisions +reg wea_diff; +reg [ADDR_WIDTH - 1 : 0] addra_diff; +reg [RAM_WIDTH - 1 : 0] dina_diff; + +reg web_diff; +reg [ADDR_WIDTH - 1 : 0] addrb_diff; +reg [RAM_WIDTH - 1 : 0] dinb_diff; + +always @(posedge clk or posedge rst) begin + if(rst) begin + wea_diff <= 'd0; + addra_diff <= 'd0; + dina_diff <= 'd0; + end + else begin + wea_diff <= wea; + addra_diff <= addra; + dina_diff <= dina; + end +end + +assign douta = (addra_diff == addrb_diff) && wea_diff && !web_diff ? dina_diff : + (addra_diff == addrb_diff) && !wea_diff && web_diff ? dinb_diff : + (addra_diff != addrb_diff) && wea_diff ? dina_diff : douta_fake; + +always @(posedge clk or posedge rst) begin + if(rst) begin + web_diff <= 'd0; + addrb_diff <= 'd0; + dinb_diff <= 'd0; + end + else begin + web_diff <= web; + addrb_diff <= addrb; + dinb_diff <= dinb; + end +end + +assign doutb = (addra_diff == addrb_diff) && wea_diff && !web_diff ? dina_diff : + (addra_diff == addrb_diff) && !wea_diff && web_diff ? dinb_diff : + (addra_diff != addrb_diff) && web_diff ? dinb_diff : doutb_fake; + +/*Debug subsystem : Begin*/ +`ifdef DEBUG_ON + +`endif +/*Debug subsystem : End*/ + + +endmodule diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Common/SyncFIFO_2Port_Ctrl_SRAM.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Common/SyncFIFO_2Port_Ctrl_SRAM.v new file mode 100644 index 0000000000000000000000000000000000000000..c742c3fccbe656a488bec5239d804fe816bd3705 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Common/SyncFIFO_2Port_Ctrl_SRAM.v @@ -0,0 +1,180 @@ +// sync FIFO controller which uses two-port SRAM as data array +`timescale 1ns / 100ps + +module SyncFIFO_2Port_Ctrl_SRAM #( + parameter DATA_WIDTH = 32'd10, + parameter FIFO_DEPTH = 4, + parameter ADDR_WIDTH = log2b(FIFO_DEPTH-1), // local param, do not modify + parameter DEPTH_WIDTH = log2b(FIFO_DEPTH) // local param, do not modify +) +( + input clk, + input rst_n, + input push, + input pop, + input [DATA_WIDTH-1:0] data_in, + output [DATA_WIDTH-1:0] data_out, + output full, + output progfull, + output empty, + output [DEPTH_WIDTH-1:0] remain, // This is inaccurate, and only indicates the remaining data count in sram + output reg [DEPTH_WIDTH-1:0] count, // This is inaccurate, and only indicates the data count in sram + output reg ovflow, + output reg undflow, + + output sram_wr_cen, + output [ADDR_WIDTH-1:0] sram_wr_a, + output [DATA_WIDTH-1:0] sram_wr_d, + + output sram_rd_cen, + output [ADDR_WIDTH-1:0] sram_rd_a, + input [DATA_WIDTH-1:0] sram_rd_q +); + +assign remain = FIFO_DEPTH - count; + +function integer log2b; +input integer val; +begin: func_log2b + integer i; + log2b = 1; + for (i=0; i<32; i=i+1) begin + if (|(val >> i)) begin + log2b = i+1; + end + end +end +endfunction + +reg [ADDR_WIDTH-1:0] waddr; +reg [ADDR_WIDTH-1:0] raddr; + +reg [DATA_WIDTH-1:0] rd_buf; +reg rd_buf_vld; +reg sram_q_vld; + +assign sram_rd_cen = ~((count != {DEPTH_WIDTH{1'b0}}) & ((~sram_q_vld) & (~rd_buf_vld) | + (~sram_q_vld) & pop | + (~rd_buf_vld) & pop)); +assign sram_rd_a = raddr; + +assign sram_wr_cen = ~((~full) & push); +assign sram_wr_a = waddr; +assign sram_wr_d = data_in; + +assign data_out = rd_buf_vld ? rd_buf : sram_rd_q; +assign empty = ~(sram_q_vld | rd_buf_vld); +assign full = (count == FIFO_DEPTH); +assign progfull = (count > (FIFO_DEPTH - 3)); + +always @(posedge clk or negedge rst_n) +begin + if (~rst_n) begin + sram_q_vld <= `TD 1'b0; + end + else begin + sram_q_vld <= `TD ~sram_rd_cen; + end +end + +always @(posedge clk or negedge rst_n) +begin + if (~rst_n) begin + rd_buf <= `TD {DATA_WIDTH{1'b0}}; + rd_buf_vld <= `TD 1'b0; + end + else if (sram_q_vld & (~pop)) begin + rd_buf_vld <= `TD 1'b1; + rd_buf <= `TD sram_rd_q; + end + else if (rd_buf_vld & pop) begin + rd_buf_vld <= `TD 1'b0; + end +end + +always @(posedge clk or negedge rst_n) +begin + if (~rst_n) begin + waddr <= `TD {ADDR_WIDTH{1'b0}}; + end + else if (~sram_wr_cen) begin + if (waddr == FIFO_DEPTH - 1) begin + waddr <= `TD {ADDR_WIDTH{1'b0}}; + end + else begin + waddr <= `TD waddr + {{ADDR_WIDTH-1{1'b0}}, 1'b1}; + end + end +end + +always @(posedge clk or negedge rst_n) +begin + if (~rst_n) begin + raddr <= `TD {ADDR_WIDTH{1'b0}}; + end + else if (~sram_rd_cen) begin + if (raddr == FIFO_DEPTH - 1) begin + raddr <= `TD {ADDR_WIDTH{1'b0}}; + end + else begin + raddr <= `TD raddr + {{ADDR_WIDTH-1{1'b0}}, 1'b1}; + end + end +end + +always @(posedge clk or negedge rst_n) +begin + if (~rst_n) begin + count <= `TD {DEPTH_WIDTH{1'b0}}; + end +// else if ((~sram_wr_cen) & (~sram_rd_cen) & empty) begin +// count <= `TD count + {{(DEPTH_WIDTH-1){1'b0}}, 1'h1}; +// end +// else if ((~sram_wr_cen) & (~sram_rd_cen) & !empty) begin +// count <= `TD count; +// end + else if ((~sram_wr_cen) & (~sram_rd_cen)) begin + count <= `TD count; + end + else if (~sram_wr_cen) begin + count <= `TD count + {{(DEPTH_WIDTH-1){1'b0}}, 1'h1}; + end + else if (~sram_rd_cen) begin + count <= `TD count - {{(DEPTH_WIDTH-1){1'b0}}, 1'h1}; + end +end + +always @(posedge clk or negedge rst_n) +begin + if (~rst_n) begin + ovflow <= `TD 1'b0; + end + else if (push & full) begin + ovflow <= `TD 1'b1; + end +end + +always @(posedge clk or negedge rst_n) +begin + if (~rst_n) begin + undflow <= `TD 1'b0; + end + else if (pop & empty) begin + undflow <= `TD 1'b1; + end +end + +//synopsys translate_off +initial begin + if (ADDR_WIDTH != log2b(FIFO_DEPTH-1)) begin + $display("\nFatal: ADDR_WIDTH must not be modified @(%m)\n"); + $finish; + end + if (DEPTH_WIDTH != log2b(FIFO_DEPTH)) begin + $display("\nFatal: DEPTH_WIDTH must not be modified @(%m)\n"); + $finish; + end +end +//synopsys translate_on + +endmodule diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Common/SyncFIFO_2Port_SRAM.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Common/SyncFIFO_2Port_SRAM.v new file mode 100644 index 0000000000000000000000000000000000000000..56a42926df8ef0b37810a13f8d17ae64cd3fb33a --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Common/SyncFIFO_2Port_SRAM.v @@ -0,0 +1,96 @@ + +module SyncFIFO_2Port_SRAM +#( + parameter DATA_WIDTH = 16, + parameter FIFO_DEPTH = 16, + parameter ADDR_WIDTH = log2b(FIFO_DEPTH - 1), + parameter DEPTH_WIDTH = log2b(FIFO_DEPTH) +) +( + input wire clk, + input wire rst, + + input wire wr_en, + input wire [DATA_WIDTH - 1 : 0] din, + output wire prog_full, + + input wire rd_en, + output wire [DATA_WIDTH - 1 : 0] dout, + output wire empty, + output wire [DEPTH_WIDTH - 1 : 0] data_count + +); + +function integer log2b; +input integer val; +begin: func_log2b + integer i; + log2b = 1; + for (i=0; i<32; i=i+1) begin + if (|(val >> i)) begin + log2b = i+1; + end + end +end +endfunction + +wire sram_wr_cen; +wire [ADDR_WIDTH-1:0] sram_wr_a; +wire [DATA_WIDTH-1:0] sram_wr_d; + +wire sram_rd_cen; +wire [ADDR_WIDTH-1:0] sram_rd_a; +wire [DATA_WIDTH-1:0] sram_rd_q; + +wire [DEPTH_WIDTH - 1 : 0] empty_entry_num; + +wire rst_n; +assign rst_n = !rst; + +assign prog_full = (empty_entry_num < 3) ? 1'b1 : 1'b0; +assign data_count = (FIFO_DEPTH - empty_entry_num); + +SyncFIFO_2Port_Ctrl_SRAM #( + .DATA_WIDTH(DATA_WIDTH), + .FIFO_DEPTH(FIFO_DEPTH) +) U_SyncFIFO_2Port_Ctrl_SRAM +( + .clk(clk), + .rst_n(rst_n), + .push(wr_en), + .pop(rd_en), + .data_in(din), + .data_out(dout), + .full(), + .empty(empty), + .remain(empty_entry_num), + .count(), + .ovflow(), + .undflow(), + .sram_wr_cen(sram_wr_cen), + .sram_wr_a (sram_wr_a ), + .sram_wr_d (sram_wr_d ), + .sram_rd_cen(sram_rd_cen), + .sram_rd_a (sram_rd_a ), + .sram_rd_q (sram_rd_q ) +); + +SRAM_SDP_Model +#( + .DATA_WIDTH(DATA_WIDTH), + .ADDR_WIDTH(ADDR_WIDTH), + .RAM_DEPTH(FIFO_DEPTH) +) U_sram_2port_model( + .clk(clk), + .rst(rst), + .sram_wr_cen(sram_wr_cen), + .sram_wr_a(sram_wr_a), + .sram_wr_d(sram_wr_d), + .sram_rd_cen(sram_rd_cen), + .sram_rd_a(sram_rd_a), + .sram_rd_q(sram_rd_q) +); + +endmodule + + diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Common/SyncFIFO_Template.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Common/SyncFIFO_Template.v new file mode 100644 index 0000000000000000000000000000000000000000..ea875cecd666c851c6463ae5c178704daa113a1b --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Common/SyncFIFO_Template.v @@ -0,0 +1,211 @@ +`timescale 1ns / 1ps + +`include "common_function_def.vh" + +module SyncFIFO_Template #( + parameter FIFO_TYPE = 0, //0: Xilinx IP, 1: RegFiles + parameter FIFO_WIDTH = 32, + parameter FIFO_DEPTH = 32, + parameter COUNT_WIDTH = log2b(FIFO_DEPTH) +) +( + input wire clk, + input wire rst, + + input wire wr_en, + input wire [FIFO_WIDTH - 1 : 0] din, + output wire prog_full, + input wire rd_en, + output wire [FIFO_WIDTH - 1 : 0] dout, + output wire empty, + output wire [COUNT_WIDTH - 1 : 0] data_count +); + + +generate + if(FIFO_TYPE == 0) begin //Xilinx IP + if(FIFO_WIDTH == 64 && FIFO_DEPTH == 128) begin : GEN_SYNC_FIFO_64W_128D + SyncFIFO_64w_128d SyncFIFO_64w_128d_Inst( + .clk(clk), + .srst(rst), + + .wr_en(wr_en), + .din(din), + .prog_full(prog_full), + .rd_en(rd_en), + .dout(dout), + .empty(empty), + .data_count(data_count) + ); + end + else if(FIFO_WIDTH == 128 && FIFO_DEPTH == 16) begin : GEN_SYNC_FIFO_128W_16D + SyncFIFO_128w_16d SyncFIFO_128w_16d_Inst( + .clk(clk), + .srst(rst), + + .wr_en(wr_en), + .din(din), + .prog_full(prog_full), + .rd_en(rd_en), + .dout(dout), + .empty(empty), + .data_count(data_count) + ); + end + else if(FIFO_WIDTH == 258 && FIFO_DEPTH == 16) begin : GEN_SYNC_FIFO_258W_16D + SyncFIFO_258w_16d SyncFIFO_258w_16d_Inst( + .clk(clk), + .srst(rst), + + .wr_en(wr_en), + .din(din), + .prog_full(prog_full), + .rd_en(rd_en), + .dout(dout), + .empty(empty), + .data_count(data_count) + ); + end + else if(FIFO_WIDTH == 24 && FIFO_DEPTH == 256) begin : GEN_SYNC_FIFO_24W_256D + SyncFIFO_24w_256d SyncFIFO_24w_256d_Inst( + .clk(clk), + .srst(rst), + + .wr_en(wr_en), + .din(din), + .prog_full(prog_full), + .rd_en(rd_en), + .dout(dout), + .empty(empty), + .data_count(data_count) + ); + end + else if(FIFO_WIDTH == 5 && FIFO_DEPTH == 32) begin : GEN_SYNC_FIFO_5W_32D + SyncFIFO_5w_32d SyncFIFO_5w_32d_Inst( + .clk(clk), + .srst(rst), + + .wr_en(wr_en), + .din(din), + .prog_full(prog_full), + .rd_en(rd_en), + .dout(dout), + .empty(empty), + .data_count(data_count) + ); + end + else if(FIFO_WIDTH == 140 && FIFO_DEPTH == 32) begin : GEN_SYNC_FIFO_140W_32D + SyncFIFO_140w_32d SyncFIFO_140w_32d_Inst( + .clk(clk), + .srst(rst), + + .wr_en(wr_en), + .din(din), + .prog_full(prog_full), + .rd_en(rd_en), + .dout(dout), + .empty(empty), + .data_count(data_count) + ); + end + else if(FIFO_WIDTH == 512 && FIFO_DEPTH == 64) begin : GEN_SYNC_FIFO_512W_64D + SyncFIFO_512w_64d SyncFIFO_512w_64d_Inst( + .clk(clk), + .srst(rst), + + .wr_en(wr_en), + .din(din), + .prog_full(prog_full), + .rd_en(rd_en), + .dout(dout), + .empty(empty), + .data_count(data_count) + ); + end + else if(FIFO_WIDTH == 128 && FIFO_DEPTH == 64) begin : GEN_SYNC_FIFO_128W_64D + SyncFIFO_128w_64d SyncFIFO_128w_64d_Inst( + .clk(clk), + .srst(rst), + + .wr_en(wr_en), + .din(din), + .prog_full(prog_full), + .rd_en(rd_en), + .dout(dout), + .empty(empty), + .data_count(data_count) + ); + end + else if(FIFO_WIDTH == 576 && FIFO_DEPTH == 32) begin : GEN_SYNC_FIFO_576W_32D + SyncFIFO_576w_32d SyncFIFO_576w_32d_Inst( + .clk(clk), + .srst(rst), + + .wr_en(wr_en), + .din(din), + .prog_full(prog_full), + .rd_en(rd_en), + .dout(dout), + .empty(empty), + .data_count(data_count) + ); + end + else if(FIFO_WIDTH == 6 && FIFO_DEPTH == 64) begin : GEN_SYNC_FIFO_6W_64D + SyncFIFO_6w_64d SyncFIFO_6w_64d_Inst( + .clk(clk), + .srst(rst), + + .wr_en(wr_en), + .din(din), + .prog_full(prog_full), + .rd_en(rd_en), + .dout(dout), + .empty(empty), + .data_count(data_count) + ); + end + else if(FIFO_WIDTH == 9 && FIFO_DEPTH == 512) begin : GEN_SYNC_FIFO_9W_512D + SyncFIFO_9w_512d SyncFIFO_9w_512d_Inst( + .clk(clk), + .srst(rst), + + .wr_en(wr_en), + .din(din), + .prog_full(prog_full), + .rd_en(rd_en), + .dout(dout), + .empty(empty), + .data_count(data_count) + ); + end + end + else begin //Register File + //Instantiate RegFile FIFO + SyncFIFO_2Port_SRAM #( + .DATA_WIDTH(FIFO_WIDTH), + .FIFO_DEPTH(FIFO_DEPTH) + ) + SyncFIFO_RegFile_Inst + ( + .clk(clk), + .rst(rst), + + .wr_en(wr_en), + .din(din), + .prog_full(prog_full), + + .rd_en(rd_en), + .dout(dout), + .empty(empty), + .data_count(data_count) + ); + end +endgenerate + +/*Debug subsystem : Begin*/ +`ifdef DEBUG_ON + +`endif +/*Debug subsystem : End*/ + +endmodule diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Common/slice/gp_slice.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Common/slice/gp_slice.v new file mode 100644 index 0000000000000000000000000000000000000000..44ba1f5c94cbba9b6aca2e87f9ef5ac74edd256f --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Common/slice/gp_slice.v @@ -0,0 +1,157 @@ +// general purpose slice + +module gp_slice #( + parameter PAYLD_WIDTH = 32'd32, + parameter MODE = 0, // slice mode: 0 -- full, 1 -- forward, 2 -- reverse, 3 -- bypass + parameter SYNC_RESET = 0 +) +( + input clk, + input rst_n, + + input vld_m, + output rdy_m, + input [PAYLD_WIDTH-1:0] payld_m, + output vld_s, + input rdy_s, + output [PAYLD_WIDTH-1:0] payld_s +); + +wire rst_n_sync; + +generate + if (SYNC_RESET) begin: reset_sync + + reset_sync #( + .SYNC_MODE (1 ) + ) u_reset_sync ( + .rstn_d (rst_n_sync ), + .rstn_s (rst_n ), + .clk_d (clk ) + ); + + end + else begin: reset_no_sync + + assign rst_n_sync = rst_n; + + end +endgenerate + +generate if (MODE == 0) begin: FUL_MODE + + reg [PAYLD_WIDTH-1:0] slice_a; + reg valid_a; + reg [PAYLD_WIDTH-1:0] slice_b; + reg valid_b; + reg sel_b; + + assign rdy_m = (~valid_a) | (~valid_b); + + assign vld_s = valid_a | valid_b; + assign payld_s = sel_b ? slice_b : slice_a; + + always @(posedge clk or negedge rst_n_sync) + begin + if (!rst_n_sync) begin + sel_b <= `TD 1'b0; + end + else if (vld_s & rdy_s) begin + sel_b <= `TD ~sel_b; + end + end + + always @(posedge clk or negedge rst_n_sync) + begin + if (!rst_n_sync) begin + slice_a <= `TD {PAYLD_WIDTH{1'b0}}; + valid_a <= `TD 1'b0; + end + else if ((~valid_a) & (valid_b | (~sel_b)) & vld_m) begin + slice_a <= `TD payld_m; + valid_a <= `TD 1'b1; + end + else if (valid_a & (~sel_b) & rdy_s) begin + valid_a <= `TD 1'b0; + end + end + + always @(posedge clk or negedge rst_n_sync) + begin + if (!rst_n_sync) begin + slice_b <= `TD {PAYLD_WIDTH{1'b0}}; + valid_b <= `TD 1'b0; + end + else if ((~valid_b) & (valid_a | sel_b) & vld_m) begin + slice_b <= `TD payld_m; + valid_b <= `TD 1'b1; + end + else if (valid_b & sel_b & rdy_s) begin + valid_b <= `TD 1'b0; + end + end + +end +else if (MODE == 1) begin: FWD_MODE + + reg [PAYLD_WIDTH-1:0] slice; + reg valid; + + assign rdy_m = ~valid | rdy_s; + + assign vld_s = valid; + assign payld_s = slice; + + always @(posedge clk or negedge rst_n_sync) + begin + if (!rst_n_sync) begin + slice <= `TD {PAYLD_WIDTH{1'b0}}; + valid <= `TD 1'b0; + end + else if (vld_m & rdy_m) begin + slice <= `TD payld_m; + valid <= `TD 1'b1; + end + else if (vld_s & rdy_s) begin + valid <= `TD 1'b0; + end + end + +end +else if (MODE == 2) begin: REV_MODE + + reg [PAYLD_WIDTH-1:0] slice; + reg valid; + + assign rdy_m = ~valid; + + assign vld_s = valid | vld_m; + assign payld_s = valid ? slice : payld_m; + + always @(posedge clk or negedge rst_n_sync) + begin + if (!rst_n_sync) begin + slice <= `TD {PAYLD_WIDTH{1'b0}}; + valid <= `TD 1'b0; + end + else if (vld_m & rdy_m & (~rdy_s)) begin + slice <= `TD payld_m; + valid <= `TD 1'b1; + end + else if (valid & rdy_s) begin + valid <= `TD 1'b0; + end + end + +end +else begin: BYP_MODE + + assign rdy_m = rdy_s; + + assign vld_s = vld_m; + assign payld_s = payld_m; + +end +endgenerate + +endmodule diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Common/slice/gp_slice_ml.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Common/slice/gp_slice_ml.v new file mode 100644 index 0000000000000000000000000000000000000000..c6a674477c02de5c3a4f1f533cf4c1a0504ab71c --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Common/slice/gp_slice_ml.v @@ -0,0 +1,55 @@ +// multi-level general purpose slice + +module gp_slice_ml #( + parameter NUM_LEVELS = 1, + parameter PAYLD_WIDTH = 32'd32, + parameter MODE = 0, // slice mode: 0 -- full, 1 -- forward, 2 -- reverse, 3 -- bypass + parameter SYNC_RESET = 0 +) +( + input clk, + input rst_n, + + input vld_m, + output rdy_m, + input [PAYLD_WIDTH-1:0] payld_m, + output vld_s, + input rdy_s, + output [PAYLD_WIDTH-1:0] payld_s +); + +wire vld[NUM_LEVELS:0]; +wire rdy[NUM_LEVELS:0]; +wire [PAYLD_WIDTH-1:0] payld[NUM_LEVELS:0]; + +genvar i; + +assign vld[0] = vld_m; +assign rdy_m = rdy[0]; +assign payld[0] = payld_m; + +assign vld_s = vld[NUM_LEVELS]; +assign rdy[NUM_LEVELS] = rdy_s; +assign payld_s = payld[NUM_LEVELS]; + +generate for (i=0; i File : st_demux.v +// > Author : Kangning +// > Date : 2022-12-02 +// > Note : demux one channel into multiply channel. +//************************************************************************* + +module st_demux #( + parameter CHNL_NUM = 8 , // number of slave signals to arbit + parameter CHNL_NUM_LOG = 3 , + parameter TUSER_WIDTH = 128, + parameter TDATA_WIDTH = 256 +) ( + input wire clk , // i, 1 + input wire rst_n, // i, 1 + + input wire nxt_chnl_vld, // i, 1 + input wire [7 : 0] nxt_chnl_sel, // i, 8 + + /* -------Slave AXIS Interface{begin}------- */ + input wire s_axis_demux_valid, // i, 1 + input wire s_axis_demux_last , // i, 1 + input wire [TDATA_WIDTH - 1 : 0] s_axis_demux_data , // i, TDATA_WIDTH + input wire [TUSER_WIDTH - 1 : 0] s_axis_demux_head , // i, TUSER_WIDTH + output wire s_axis_demux_ready, // o, 1 + /* -------Slave AXIS Interface{end}------- */ + + /* ------- Master AXIS Interface{begin} ------- */ + output wire [CHNL_NUM * 1 - 1 : 0] m_axis_demux_valid, // o, CHNL_NUM * 1 + output wire [CHNL_NUM * 1 - 1 : 0] m_axis_demux_last , // o, CHNL_NUM * 1 + output wire [CHNL_NUM * TDATA_WIDTH - 1 : 0] m_axis_demux_data , // o, CHNL_NUM * TDATA_WIDTH + output wire [CHNL_NUM * TUSER_WIDTH - 1 : 0] m_axis_demux_head , // o, CHNL_NUM * TUSER_WIDTH + input wire [CHNL_NUM * 1 - 1 : 0] m_axis_demux_ready // i, CHNL_NUM * 1 + /* ------- Master AXIS Interface{end} ------- */ + +); + +/* -------State relevant in FSM{begin}------- */ +localparam IDLE = 2'b01, + TRANS = 2'b10; + +reg [1:0] cur_state; +reg [1:0] nxt_state; + +wire is_idle, is_trans; +/* -------State relevant in FSM{end}------- */ + +/* --------Channel selection{begin}-------- */ +reg [CHNL_NUM_LOG-1:0] sel; +/* --------Channel selection{end}-------- */ + +//-----------------------------------------------------------------------------------------------------------------------------------------------------------------------// + +/* --------Channel selection{begin}--------- */ +always @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + sel <= `TD 8'd0; + end + else if ((is_idle & nxt_chnl_vld) || + (is_trans & s_axis_demux_last & s_axis_demux_valid & s_axis_demux_ready & nxt_chnl_vld)) begin + sel <= `TD nxt_chnl_sel; + end +end + +// assign mem_addr = s_axis_demux_head[63:32]; +// assign nxt_chnl_sel = s_axis_demux_valid ? (mem_addr[13:12] == 2'b11) : 0; +/* --------Channel selection{end}--------- */ + +/* -------{DEMUX FSM}begin------- */ +/******************** Stage 1: State Register **********************/ +assign is_idle = (cur_state == IDLE ); +assign is_trans = (cur_state == TRANS); + +always @(posedge clk, negedge rst_n) begin + if(~rst_n) + cur_state <= `TD IDLE; + else + cur_state <= `TD nxt_state; +end + +/******************** Stage 2: State Transition **********************/ +always @(*) begin + case(cur_state) + IDLE: begin + if (nxt_chnl_vld) begin + nxt_state = TRANS; + end + else begin + nxt_state = IDLE; + end + end + TRANS: begin + if (s_axis_demux_last & s_axis_demux_valid & s_axis_demux_ready & nxt_chnl_vld) begin + nxt_state = TRANS; + end + else if (s_axis_demux_last & s_axis_demux_valid & s_axis_demux_ready) begin + nxt_state = IDLE; + end + else begin + nxt_state = TRANS; + end + end + default: begin + nxt_state = IDLE; + end + endcase +end +/******************** Stage 3: Output **********************/ + +/* -------Generate block{begin}------- */ +/* This is used for different Channel Numbers, the default Number is 4 + */ +generate +if (CHNL_NUM == 16) begin:CHNL_DEMUX_16 + +assign s_axis_demux_ready = ((sel == 0) & is_trans & m_axis_demux_ready[0]) | + ((sel == 1) & is_trans & m_axis_demux_ready[1]) | + ((sel == 2) & is_trans & m_axis_demux_ready[2]) | + ((sel == 3) & is_trans & m_axis_demux_ready[3]) | + ((sel == 4) & is_trans & m_axis_demux_ready[4]) | + ((sel == 5) & is_trans & m_axis_demux_ready[5]) | + ((sel == 6) & is_trans & m_axis_demux_ready[6]) | + ((sel == 7) & is_trans & m_axis_demux_ready[7]) | + ((sel == 8) & is_trans & m_axis_demux_ready[8]) | + ((sel == 9) & is_trans & m_axis_demux_ready[9]) | + ((sel == 10) & is_trans & m_axis_demux_ready[10])| + ((sel == 11) & is_trans & m_axis_demux_ready[11])| + ((sel == 12) & is_trans & m_axis_demux_ready[12])| + ((sel == 13) & is_trans & m_axis_demux_ready[13])| + ((sel == 14) & is_trans & m_axis_demux_ready[14])| + ((sel == 15) & is_trans & m_axis_demux_ready[15]); + +end // CHNL_DEMUX_16 +else if (CHNL_NUM == 15) begin:CHNL_DEMUX_15 + +assign s_axis_demux_ready = ((sel == 0) & is_trans & m_axis_demux_ready[0]) | + ((sel == 1) & is_trans & m_axis_demux_ready[1]) | + ((sel == 2) & is_trans & m_axis_demux_ready[2]) | + ((sel == 3) & is_trans & m_axis_demux_ready[3]) | + ((sel == 4) & is_trans & m_axis_demux_ready[4]) | + ((sel == 5) & is_trans & m_axis_demux_ready[5]) | + ((sel == 6) & is_trans & m_axis_demux_ready[6]) | + ((sel == 7) & is_trans & m_axis_demux_ready[7]) | + ((sel == 8) & is_trans & m_axis_demux_ready[8]) | + ((sel == 9) & is_trans & m_axis_demux_ready[9]) | + ((sel == 10) & is_trans & m_axis_demux_ready[10])| + ((sel == 11) & is_trans & m_axis_demux_ready[11])| + ((sel == 12) & is_trans & m_axis_demux_ready[12])| + ((sel == 13) & is_trans & m_axis_demux_ready[13])| + ((sel == 14) & is_trans & m_axis_demux_ready[14]); + +end // CHNL_DEMUX_15 +else if (CHNL_NUM == 14) begin:CHNL_DEMUX_14 + +assign s_axis_demux_ready = ((sel == 0) & is_trans & m_axis_demux_ready[0]) | + ((sel == 1) & is_trans & m_axis_demux_ready[1]) | + ((sel == 2) & is_trans & m_axis_demux_ready[2]) | + ((sel == 3) & is_trans & m_axis_demux_ready[3]) | + ((sel == 4) & is_trans & m_axis_demux_ready[4]) | + ((sel == 5) & is_trans & m_axis_demux_ready[5]) | + ((sel == 6) & is_trans & m_axis_demux_ready[6]) | + ((sel == 7) & is_trans & m_axis_demux_ready[7]) | + ((sel == 8) & is_trans & m_axis_demux_ready[8]) | + ((sel == 9) & is_trans & m_axis_demux_ready[9]) | + ((sel == 10) & is_trans & m_axis_demux_ready[10])| + ((sel == 11) & is_trans & m_axis_demux_ready[11])| + ((sel == 12) & is_trans & m_axis_demux_ready[12])| + ((sel == 13) & is_trans & m_axis_demux_ready[13]); + +end // CHNL_DEMUX_14 +else if (CHNL_NUM == 13) begin:CHNL_DEMUX_13 + +assign s_axis_demux_ready = ((sel == 0) & is_trans & m_axis_demux_ready[0]) | + ((sel == 1) & is_trans & m_axis_demux_ready[1]) | + ((sel == 2) & is_trans & m_axis_demux_ready[2]) | + ((sel == 3) & is_trans & m_axis_demux_ready[3]) | + ((sel == 4) & is_trans & m_axis_demux_ready[4]) | + ((sel == 5) & is_trans & m_axis_demux_ready[5]) | + ((sel == 6) & is_trans & m_axis_demux_ready[6]) | + ((sel == 7) & is_trans & m_axis_demux_ready[7]) | + ((sel == 8) & is_trans & m_axis_demux_ready[8]) | + ((sel == 9) & is_trans & m_axis_demux_ready[9]) | + ((sel == 10) & is_trans & m_axis_demux_ready[10])| + ((sel == 11) & is_trans & m_axis_demux_ready[11])| + ((sel == 12) & is_trans & m_axis_demux_ready[12]); + +end // CHNL_DEMUX_13 +else if (CHNL_NUM == 12) begin:CHNL_DEMUX_12 + +assign s_axis_demux_ready = ((sel == 0) & is_trans & m_axis_demux_ready[0]) | + ((sel == 1) & is_trans & m_axis_demux_ready[1]) | + ((sel == 2) & is_trans & m_axis_demux_ready[2]) | + ((sel == 3) & is_trans & m_axis_demux_ready[3]) | + ((sel == 4) & is_trans & m_axis_demux_ready[4]) | + ((sel == 5) & is_trans & m_axis_demux_ready[5]) | + ((sel == 6) & is_trans & m_axis_demux_ready[6]) | + ((sel == 7) & is_trans & m_axis_demux_ready[7]) | + ((sel == 8) & is_trans & m_axis_demux_ready[8]) | + ((sel == 9) & is_trans & m_axis_demux_ready[9]) | + ((sel == 10) & is_trans & m_axis_demux_ready[10])| + ((sel == 11) & is_trans & m_axis_demux_ready[11]); + +end // CHNL_DEMUX_12 +else if (CHNL_NUM == 11) begin:CHNL_DEMUX_11 + +assign s_axis_demux_ready = ((sel == 0) & is_trans & m_axis_demux_ready[0]) | + ((sel == 1) & is_trans & m_axis_demux_ready[1]) | + ((sel == 2) & is_trans & m_axis_demux_ready[2]) | + ((sel == 3) & is_trans & m_axis_demux_ready[3]) | + ((sel == 4) & is_trans & m_axis_demux_ready[4]) | + ((sel == 5) & is_trans & m_axis_demux_ready[5]) | + ((sel == 6) & is_trans & m_axis_demux_ready[6]) | + ((sel == 7) & is_trans & m_axis_demux_ready[7]) | + ((sel == 8) & is_trans & m_axis_demux_ready[8]) | + ((sel == 9) & is_trans & m_axis_demux_ready[9]) | + ((sel == 10) & is_trans & m_axis_demux_ready[10]); + +end // CHNL_DEMUX_11 +else if (CHNL_NUM == 10) begin:CHNL_DEMUX_10 + +assign s_axis_demux_ready = ((sel == 0) & is_trans & m_axis_demux_ready[0]) | + ((sel == 1) & is_trans & m_axis_demux_ready[1]) | + ((sel == 2) & is_trans & m_axis_demux_ready[2]) | + ((sel == 3) & is_trans & m_axis_demux_ready[3]) | + ((sel == 4) & is_trans & m_axis_demux_ready[4]) | + ((sel == 5) & is_trans & m_axis_demux_ready[5]) | + ((sel == 6) & is_trans & m_axis_demux_ready[6]) | + ((sel == 7) & is_trans & m_axis_demux_ready[7]) | + ((sel == 8) & is_trans & m_axis_demux_ready[8]) | + ((sel == 9) & is_trans & m_axis_demux_ready[9]); + +end // CHNL_DEMUX_10 +else if (CHNL_NUM == 9) begin:CHNL_DEMUX_9 + +assign s_axis_demux_ready = ((sel == 0) & is_trans & m_axis_demux_ready[0]) | + ((sel == 1) & is_trans & m_axis_demux_ready[1]) | + ((sel == 2) & is_trans & m_axis_demux_ready[2]) | + ((sel == 3) & is_trans & m_axis_demux_ready[3]) | + ((sel == 4) & is_trans & m_axis_demux_ready[4]) | + ((sel == 5) & is_trans & m_axis_demux_ready[5]) | + ((sel == 6) & is_trans & m_axis_demux_ready[6]) | + ((sel == 7) & is_trans & m_axis_demux_ready[7]) | + ((sel == 8) & is_trans & m_axis_demux_ready[8]); + +end // CHNL_DEMUX_9 +else if (CHNL_NUM == 8) begin:CHNL_DEMUX_8 + +assign s_axis_demux_ready = ((sel == 0) & is_trans & m_axis_demux_ready[0]) | + ((sel == 1) & is_trans & m_axis_demux_ready[1]) | + ((sel == 2) & is_trans & m_axis_demux_ready[2]) | + ((sel == 3) & is_trans & m_axis_demux_ready[3]) | + ((sel == 4) & is_trans & m_axis_demux_ready[4]) | + ((sel == 5) & is_trans & m_axis_demux_ready[5]) | + ((sel == 6) & is_trans & m_axis_demux_ready[6]) | + ((sel == 7) & is_trans & m_axis_demux_ready[7]); + +end // CHNL_DEMUX_8 +else if (CHNL_NUM == 7) begin:CHNL_DEMUX_7 + +assign s_axis_demux_ready = ((sel == 0) & is_trans & m_axis_demux_ready[0]) | + ((sel == 1) & is_trans & m_axis_demux_ready[1]) | + ((sel == 2) & is_trans & m_axis_demux_ready[2]) | + ((sel == 3) & is_trans & m_axis_demux_ready[3]) | + ((sel == 4) & is_trans & m_axis_demux_ready[4]) | + ((sel == 5) & is_trans & m_axis_demux_ready[5]) | + ((sel == 6) & is_trans & m_axis_demux_ready[6]); + +end // CHNL_DEMUX_7 +else if (CHNL_NUM == 6) begin:CHNL_DEMUX_6 + +assign s_axis_demux_ready = ((sel == 0) & is_trans & m_axis_demux_ready[0]) | + ((sel == 1) & is_trans & m_axis_demux_ready[1]) | + ((sel == 2) & is_trans & m_axis_demux_ready[2]) | + ((sel == 3) & is_trans & m_axis_demux_ready[3]) | + ((sel == 4) & is_trans & m_axis_demux_ready[4]) | + ((sel == 5) & is_trans & m_axis_demux_ready[5]); + +end // CHNL_DEMUX_6 +else if (CHNL_NUM == 5) begin:CHNL_DEMUX_5 + +assign s_axis_demux_ready = ((sel == 0) & is_trans & m_axis_demux_ready[0]) | + ((sel == 1) & is_trans & m_axis_demux_ready[1]) | + ((sel == 2) & is_trans & m_axis_demux_ready[2]) | + ((sel == 3) & is_trans & m_axis_demux_ready[3]) | + ((sel == 4) & is_trans & m_axis_demux_ready[4]); + +end // CHNL_DEMUX_5 +else if (CHNL_NUM == 4) begin:CHNL_DEMUX_4 + +assign s_axis_demux_ready = ((sel == 0) & is_trans & m_axis_demux_ready[0]) | + ((sel == 1) & is_trans & m_axis_demux_ready[1]) | + ((sel == 2) & is_trans & m_axis_demux_ready[2]) | + ((sel == 3) & is_trans & m_axis_demux_ready[3]); + +end // CHNL_DEMUX_4 +else if (CHNL_NUM == 3) begin:CHNL_DEMUX_3 + +assign s_axis_demux_ready = ((sel == 0) & is_trans & m_axis_demux_ready[0]) | + ((sel == 1) & is_trans & m_axis_demux_ready[1]) | + ((sel == 2) & is_trans & m_axis_demux_ready[2]); + +end // CHNL_DEMUX_3 +else if (CHNL_NUM == 2) begin:CHNL_DEMUX_2 + +assign s_axis_demux_ready = ((sel == 0) & is_trans & m_axis_demux_ready[0]) | + ((sel == 1) & is_trans & m_axis_demux_ready[1]); + +end // CHNL_DEMUX_2 +endgenerate +/* + This is used for different Channel Numbers, the default Number is 4 */ +/* -------Generate block{end}------- */ + +/* -------Generate block{begin}------- */ +/* This is used for different Channel Numbers, the default Number is 4 + */ +genvar i; +generate +for (i = 0; i < CHNL_NUM; i = i + 1) begin:CHNL_DEMUX_ASSIGN + +assign m_axis_demux_valid[(i+1)*1 -1:i*1 ] = ((i == sel) & is_trans) ? s_axis_demux_valid : 0; +assign m_axis_demux_last [(i+1)*1 -1:i*1 ] = ((i == sel) & is_trans) ? s_axis_demux_last : 0; +assign m_axis_demux_data [(i+1)*TDATA_WIDTH -1:i*TDATA_WIDTH] = ((i == sel) & is_trans) ? s_axis_demux_data : 0; +assign m_axis_demux_head [(i+1)*TUSER_WIDTH -1:i*TUSER_WIDTH] = ((i == sel) & is_trans) ? s_axis_demux_head : 0; + +end +endgenerate +/* + This is used for different Channel Numbers, the default Number is 4 */ +/* -------Generate block{end}------- */ + +endmodule diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Common/st_mux.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Common/st_mux.v new file mode 100644 index 0000000000000000000000000000000000000000..eee3609652715f008f8711ceb324a743806dd5f1 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Common/st_mux.v @@ -0,0 +1,791 @@ +`timescale 1ns / 100ps +//************************************************************************* +// > File Name: st_mux.v +// > Author : Kangning +// > Date : 2022-11-14 +// > Note : st_mux is used to arbiter different channels for data transmission +// > V1.1 - 2021-02-04 : Add supporting for five channels +// > V1.5 - 2022-04-24 : Parameterized arbiter, supports arbitrary number of channels +// > V2.0 - 2022-11-14 : A generalized string mux logic. +//************************************************************************* + +module st_mux #( + parameter CHNL_NUM = 8 , // number of slave signals to arbit + parameter CHNL_NUM_LOG = 3 , + parameter TUSER_WIDTH = 128, + parameter TDATA_WIDTH = 256 +) ( + input wire clk , + input wire rst_n, + + /* -------Slave AXIS Interface{begin}------- */ + input wire [CHNL_NUM * 1 -1:0] s_axis_mux_tvalid, // i, CHNL_NUM * 1 + input wire [CHNL_NUM * 1 -1:0] s_axis_mux_tlast , // i, CHNL_NUM * 1 + input wire [CHNL_NUM * TDATA_WIDTH-1:0] s_axis_mux_tdata , // i, CHNL_NUM * TDATA_WIDTH + input wire [CHNL_NUM * TUSER_WIDTH-1:0] s_axis_mux_tuser , // i, CHNL_NUM * TUSER_WIDTH + output wire [CHNL_NUM * 1 -1:0] s_axis_mux_tready, // o, CHNL_NUM * 1 + /* -------Slave AXIS Interface{end}------- */ + + /* ------- Master AXIS Interface{begin} ------- */ + output wire m_axis_mux_tvalid, // o, 1 + output wire m_axis_mux_tlast , // o, 1 + output wire [TDATA_WIDTH-1:0] m_axis_mux_tdata , // o, TDATA_WIDTH + output wire [TUSER_WIDTH-1:0] m_axis_mux_tuser , // o, TUSER_WIDTH + input wire m_axis_mux_tready // i, 1 + /* ------- Master AXIS Interface{end} ------- */ + +`ifdef SIMULATION + /* ------- Debug interface {begin}------- */ + /* | reserved | idx | end | out | + * | 255:CHNL_NUM_LOG+2 | CHNL_NUM_LOG+2-1:2 | 1 | 0 | + */ + ,output wire [255:0] debug + /* ------- Debug interface {end}------- */ +`endif + +); + +/* ------- Next scheduled channel{begin}------- */ +reg [CHNL_NUM_LOG-1:0] chnl_idx_reg; // Index of channel to be scheduled next time, valid only in REQ_TRANS state. +reg [CHNL_NUM_LOG-1:0] chnl_idx; // Index of channel to be scheduled next time, valid all the time. +reg [CHNL_NUM_LOG-1:0] last_chnl; // Index of last selected channel. + + +/** + * hit relevant channel is hit (hit_priority[3] == 1 means that last + * selected channel is still valid. + */ +wire [CHNL_NUM-1:0] hit_priority; + +/** + * index of channel priority in next time, e.g. nxt_priority[1] + * indicates the index of next next channel; while nxt_priority[0] + * indicates the index of next channel. + */ +wire [CHNL_NUM_LOG-1:0] nxt_priority[CHNL_NUM-1:0]; + +wire s_channel_tvalid[CHNL_NUM-1:0]; +wire s_channel_tlast [CHNL_NUM-1:0]; +wire [TDATA_WIDTH-1:0] s_channel_tdata [CHNL_NUM-1:0]; +wire [TUSER_WIDTH-1:0] s_channel_tuser [CHNL_NUM-1:0]; + + +wire req_last; // last beat of the request +/* ------- Next scheduled channel{end}------- */ + +/* -------State relevant in FSM{begin}------- */ +localparam IDLE = 3'b001, + SCHEDULE = 3'b010, + REQ_TRANS = 3'b100; + +reg [2:0] cur_state; +reg [2:0] nxt_state; + +wire is_idle, is_schedule, is_req_trans; +wire j_req_trans; +// wire j_schedule; +/* -------State relevant in FSM{end}------- */ + +/* ------------------------------------------------------------------------ */ + +`ifdef SIMULATION + /* ------- Debug interface {begin}------- */ + /* | reserved | idx | end | out | + * | 255:CHNL_NUM_LOG+2 | CHNL_NUM_LOG+2-1:2 | 1 | 0 | + */ + assign debug = {{254-CHNL_NUM_LOG{1'd0}}, + chnl_idx, + m_axis_mux_tvalid & m_axis_mux_tready & m_axis_mux_tlast, + m_axis_mux_tvalid & m_axis_mux_tready}; + /* ------- Debug interface {end}------- */ +`endif + + + +/* -------Find next channel{begin}------- */ + +always @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + last_chnl <= `TD {CHNL_NUM_LOG{1'd0}}; + end + else if (req_last) begin + last_chnl <= `TD chnl_idx; + end +end + +always @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + chnl_idx_reg <= `TD {CHNL_NUM_LOG{1'd0}}; + end + else if (j_req_trans) begin + chnl_idx_reg <= `TD chnl_idx; + end +end + +/* -------Generate block{begin}------- */ +genvar k; +generate +for (k = 0; k < CHNL_NUM; k = k + 1) begin:CHNL_PRIORITY + +assign nxt_priority[k] = ((last_chnl + k + 1) >= CHNL_NUM) ? + (last_chnl + k + 1 - CHNL_NUM) : (last_chnl + k + 1); + +end +endgenerate +/* -------Generate block{end}------- */ + + +/* -------Generate block{begin}------- */ +/* This is used for different Channel Numbers, the default Number is 5 + */ +generate +if (CHNL_NUM == 10) begin:CHNL_SEL_10 + +always @(*) begin + if (is_schedule) begin + case (last_chnl) + 0: chnl_idx = hit_priority[0] ? 1 : + hit_priority[1] ? 2 : + hit_priority[2] ? 3 : + hit_priority[3] ? 4 : + hit_priority[4] ? 5 : + hit_priority[5] ? 6 : + hit_priority[6] ? 7 : + hit_priority[7] ? 8 : + hit_priority[8] ? 9 : + hit_priority[9] ? 0 : 1 ; // last branch is chosen when no channel is valid. + 1: chnl_idx = hit_priority[0] ? 2 : + hit_priority[1] ? 3 : + hit_priority[2] ? 4 : + hit_priority[3] ? 5 : + hit_priority[4] ? 6 : + hit_priority[5] ? 7 : + hit_priority[6] ? 8 : + hit_priority[7] ? 9 : + hit_priority[8] ? 0 : + hit_priority[9] ? 1 : 2 ; // last branch is chosen when no channel is valid. + 2: chnl_idx = hit_priority[0] ? 3 : + hit_priority[1] ? 4 : + hit_priority[2] ? 5 : + hit_priority[3] ? 6 : + hit_priority[4] ? 7 : + hit_priority[5] ? 8 : + hit_priority[6] ? 9 : + hit_priority[7] ? 0 : + hit_priority[8] ? 1 : + hit_priority[9] ? 2 : 3 ; // last branch is chosen when no channel is valid. + 3: chnl_idx = hit_priority[0] ? 4 : + hit_priority[1] ? 5 : + hit_priority[2] ? 6 : + hit_priority[3] ? 7 : + hit_priority[4] ? 8 : + hit_priority[5] ? 9 : + hit_priority[6] ? 0 : + hit_priority[7] ? 1 : + hit_priority[8] ? 2 : + hit_priority[9] ? 3 : 4 ; // last branch is chosen when no channel is valid. + 4: chnl_idx = hit_priority[0] ? 5 : + hit_priority[1] ? 6 : + hit_priority[2] ? 7 : + hit_priority[3] ? 8 : + hit_priority[4] ? 9 : + hit_priority[5] ? 0 : + hit_priority[6] ? 1 : + hit_priority[7] ? 2 : + hit_priority[8] ? 3 : + hit_priority[9] ? 4 : 5 ; // last branch is chosen when no channel is valid. + 5: chnl_idx = hit_priority[0] ? 6 : + hit_priority[1] ? 7 : + hit_priority[2] ? 8 : + hit_priority[3] ? 9 : + hit_priority[4] ? 0 : + hit_priority[5] ? 1 : + hit_priority[6] ? 2 : + hit_priority[7] ? 3 : + hit_priority[8] ? 4 : + hit_priority[9] ? 5 : 6 ; // last branch is chosen when no channel is valid. + 6: chnl_idx = hit_priority[0] ? 7 : + hit_priority[1] ? 8 : + hit_priority[2] ? 9 : + hit_priority[3] ? 0 : + hit_priority[4] ? 1 : + hit_priority[5] ? 2 : + hit_priority[6] ? 3 : + hit_priority[7] ? 4 : + hit_priority[8] ? 5 : + hit_priority[9] ? 6 : 7 ; // last branch is chosen when no channel is valid. + 7: chnl_idx = hit_priority[0] ? 8 : + hit_priority[1] ? 9 : + hit_priority[2] ? 0 : + hit_priority[3] ? 1 : + hit_priority[4] ? 2 : + hit_priority[5] ? 3 : + hit_priority[6] ? 4 : + hit_priority[7] ? 5 : + hit_priority[8] ? 6 : + hit_priority[9] ? 7 : 8 ; // last branch is chosen when no channel is valid. + 8: chnl_idx = hit_priority[0] ? 9 : + hit_priority[1] ? 0 : + hit_priority[2] ? 1 : + hit_priority[3] ? 2 : + hit_priority[4] ? 3 : + hit_priority[5] ? 4 : + hit_priority[6] ? 5 : + hit_priority[7] ? 6 : + hit_priority[8] ? 7 : + hit_priority[9] ? 8 : 9 ; // last branch is chosen when no channel is valid. + 9: chnl_idx = hit_priority[0] ? 0 : + hit_priority[1] ? 1 : + hit_priority[2] ? 2 : + hit_priority[3] ? 3 : + hit_priority[4] ? 4 : + hit_priority[5] ? 5 : + hit_priority[6] ? 6 : + hit_priority[7] ? 7 : + hit_priority[8] ? 8 : + hit_priority[9] ? 9 : 0 ; // last branch is chosen when no channel is valid. + default: chnl_idx = {CHNL_NUM_LOG{1'd0}}; + endcase + end + else begin + chnl_idx = chnl_idx_reg; // chosen in REQ_TRANS state + end +end + +end // CHNL_NUM == 10 +else if (CHNL_NUM == 9) begin:CHNL_SEL_9 + +always @(*) begin + if (is_schedule) begin + case (last_chnl) + 0: chnl_idx = hit_priority[0] ? 1 : + hit_priority[1] ? 2 : + hit_priority[2] ? 3 : + hit_priority[3] ? 4 : + hit_priority[4] ? 5 : + hit_priority[5] ? 6 : + hit_priority[6] ? 7 : + hit_priority[7] ? 8 : + hit_priority[8] ? 0 : 1 ; // last branch is chosen when no channel is valid. + 1: chnl_idx = hit_priority[0] ? 2 : + hit_priority[1] ? 3 : + hit_priority[2] ? 4 : + hit_priority[3] ? 5 : + hit_priority[4] ? 6 : + hit_priority[5] ? 7 : + hit_priority[6] ? 8 : + hit_priority[7] ? 0 : + hit_priority[8] ? 1 : 2 ; // last branch is chosen when no channel is valid. + 2: chnl_idx = hit_priority[0] ? 3 : + hit_priority[1] ? 4 : + hit_priority[2] ? 5 : + hit_priority[3] ? 6 : + hit_priority[4] ? 7 : + hit_priority[5] ? 8 : + hit_priority[6] ? 0 : + hit_priority[7] ? 1 : + hit_priority[8] ? 2 : 3 ; // last branch is chosen when no channel is valid. + 3: chnl_idx = hit_priority[0] ? 4 : + hit_priority[1] ? 5 : + hit_priority[2] ? 6 : + hit_priority[3] ? 7 : + hit_priority[4] ? 8 : + hit_priority[5] ? 0 : + hit_priority[6] ? 1 : + hit_priority[7] ? 2 : + hit_priority[8] ? 3 : 4 ; // last branch is chosen when no channel is valid. + 4: chnl_idx = hit_priority[0] ? 5 : + hit_priority[1] ? 6 : + hit_priority[2] ? 7 : + hit_priority[3] ? 8 : + hit_priority[4] ? 0 : + hit_priority[5] ? 1 : + hit_priority[6] ? 2 : + hit_priority[7] ? 3 : + hit_priority[8] ? 4 : 5 ; // last branch is chosen when no channel is valid. + 5: chnl_idx = hit_priority[0] ? 6 : + hit_priority[1] ? 7 : + hit_priority[2] ? 8 : + hit_priority[3] ? 0 : + hit_priority[4] ? 1 : + hit_priority[5] ? 2 : + hit_priority[6] ? 3 : + hit_priority[7] ? 4 : + hit_priority[8] ? 5 : 6 ; // last branch is chosen when no channel is valid. + 6: chnl_idx = hit_priority[0] ? 7 : + hit_priority[1] ? 8 : + hit_priority[2] ? 0 : + hit_priority[3] ? 1 : + hit_priority[4] ? 2 : + hit_priority[5] ? 3 : + hit_priority[6] ? 4 : + hit_priority[7] ? 5 : + hit_priority[8] ? 6 : 7 ; // last branch is chosen when no channel is valid. + 7: chnl_idx = hit_priority[0] ? 8 : + hit_priority[1] ? 0 : + hit_priority[2] ? 1 : + hit_priority[3] ? 2 : + hit_priority[4] ? 3 : + hit_priority[5] ? 4 : + hit_priority[6] ? 5 : + hit_priority[7] ? 6 : + hit_priority[8] ? 7 : 8 ; // last branch is chosen when no channel is valid. + 8: chnl_idx = hit_priority[0] ? 0 : + hit_priority[1] ? 1 : + hit_priority[2] ? 2 : + hit_priority[3] ? 3 : + hit_priority[4] ? 4 : + hit_priority[5] ? 5 : + hit_priority[6] ? 6 : + hit_priority[7] ? 7 : + hit_priority[8] ? 8 : 0 ; // last branch is chosen when no channel is valid. + default: chnl_idx = {CHNL_NUM_LOG{1'd0}}; + endcase + end + else begin + chnl_idx = chnl_idx_reg; // chosen in REQ_TRANS state + end +end + +end // CHNL_NUM == 9 +else if (CHNL_NUM == 8) begin:CHNL_SEL_8 + +always @(*) begin + if (is_schedule) begin + case (last_chnl) + 0: chnl_idx = hit_priority[0] ? 1 : + hit_priority[1] ? 2 : + hit_priority[2] ? 3 : + hit_priority[3] ? 4 : + hit_priority[4] ? 5 : + hit_priority[5] ? 6 : + hit_priority[6] ? 7 : + hit_priority[7] ? 0 : 1 ; // last branch is chosen when no channel is valid. + 1: chnl_idx = hit_priority[0] ? 2 : + hit_priority[1] ? 3 : + hit_priority[2] ? 4 : + hit_priority[3] ? 5 : + hit_priority[4] ? 6 : + hit_priority[5] ? 7 : + hit_priority[6] ? 0 : + hit_priority[7] ? 1 : 2 ; // last branch is chosen when no channel is valid. + 2: chnl_idx = hit_priority[0] ? 3 : + hit_priority[1] ? 4 : + hit_priority[2] ? 5 : + hit_priority[3] ? 6 : + hit_priority[4] ? 7 : + hit_priority[5] ? 0 : + hit_priority[6] ? 1 : + hit_priority[7] ? 2 : 3 ; // last branch is chosen when no channel is valid. + 3: chnl_idx = hit_priority[0] ? 4 : + hit_priority[1] ? 5 : + hit_priority[2] ? 6 : + hit_priority[3] ? 7 : + hit_priority[4] ? 0 : + hit_priority[5] ? 1 : + hit_priority[6] ? 2 : + hit_priority[7] ? 3 : 4 ; // last branch is chosen when no channel is valid. + 4: chnl_idx = hit_priority[0] ? 5 : + hit_priority[1] ? 6 : + hit_priority[2] ? 7 : + hit_priority[3] ? 0 : + hit_priority[4] ? 1 : + hit_priority[5] ? 2 : + hit_priority[6] ? 3 : + hit_priority[7] ? 4 : 5 ; // last branch is chosen when no channel is valid. + 5: chnl_idx = hit_priority[0] ? 6 : + hit_priority[1] ? 7 : + hit_priority[2] ? 0 : + hit_priority[3] ? 1 : + hit_priority[4] ? 2 : + hit_priority[5] ? 3 : + hit_priority[6] ? 4 : + hit_priority[7] ? 5 : 6 ; // last branch is chosen when no channel is valid. + 6: chnl_idx = hit_priority[0] ? 7 : + hit_priority[1] ? 0 : + hit_priority[2] ? 1 : + hit_priority[3] ? 2 : + hit_priority[4] ? 3 : + hit_priority[5] ? 4 : + hit_priority[6] ? 5 : + hit_priority[7] ? 6 : 7 ; // last branch is chosen when no channel is valid. + 7: chnl_idx = hit_priority[0] ? 0 : + hit_priority[1] ? 1 : + hit_priority[2] ? 2 : + hit_priority[3] ? 3 : + hit_priority[4] ? 4 : + hit_priority[5] ? 5 : + hit_priority[6] ? 6 : + hit_priority[7] ? 7 : 0 ; // last branch is chosen when no channel is valid. + default: chnl_idx = {CHNL_NUM_LOG{1'd0}}; + endcase + end + else begin + chnl_idx = chnl_idx_reg; // chosen in REQ_TRANS state + end +end + +end // CHNL_NUM == 8 +else if (CHNL_NUM == 7) begin:CHNL_SEL_7 + +always @(*) begin + if (is_schedule) begin + case (last_chnl) + 0: chnl_idx = hit_priority[0] ? 1 : + hit_priority[1] ? 2 : + hit_priority[2] ? 3 : + hit_priority[3] ? 4 : + hit_priority[4] ? 5 : + hit_priority[5] ? 6 : + hit_priority[6] ? 0 : 1 ; // last branch is chosen when no channel is valid. + 1: chnl_idx = hit_priority[0] ? 2 : + hit_priority[1] ? 3 : + hit_priority[2] ? 4 : + hit_priority[3] ? 5 : + hit_priority[4] ? 6 : + hit_priority[5] ? 0 : + hit_priority[6] ? 1 : 2 ; // last branch is chosen when no channel is valid. + 2: chnl_idx = hit_priority[0] ? 3 : + hit_priority[1] ? 4 : + hit_priority[2] ? 5 : + hit_priority[3] ? 6 : + hit_priority[4] ? 0 : + hit_priority[5] ? 1 : + hit_priority[6] ? 2 : 3 ; // last branch is chosen when no channel is valid. + 3: chnl_idx = hit_priority[0] ? 4 : + hit_priority[1] ? 5 : + hit_priority[2] ? 6 : + hit_priority[3] ? 0 : + hit_priority[4] ? 1 : + hit_priority[5] ? 2 : + hit_priority[6] ? 3 : 4 ; // last branch is chosen when no channel is valid. + 4: chnl_idx = hit_priority[0] ? 5 : + hit_priority[1] ? 6 : + hit_priority[2] ? 0 : + hit_priority[3] ? 1 : + hit_priority[4] ? 2 : + hit_priority[5] ? 3 : + hit_priority[6] ? 4 : 5 ; // last branch is chosen when no channel is valid. + 5: chnl_idx = hit_priority[0] ? 6 : + hit_priority[1] ? 0 : + hit_priority[2] ? 1 : + hit_priority[3] ? 2 : + hit_priority[4] ? 3 : + hit_priority[5] ? 4 : + hit_priority[6] ? 5 : 6 ; // last branch is chosen when no channel is valid. + 6: chnl_idx = hit_priority[0] ? 0 : + hit_priority[1] ? 1 : + hit_priority[2] ? 2 : + hit_priority[3] ? 3 : + hit_priority[4] ? 4 : + hit_priority[5] ? 5 : + hit_priority[6] ? 6 : 0 ; // last branch is chosen when no channel is valid. + default: chnl_idx = {CHNL_NUM_LOG{1'd0}}; + endcase + end + else begin + chnl_idx = chnl_idx_reg; // chosen in REQ_TRANS state + end +end + +end // CHNL_NUM == 7 +else if (CHNL_NUM == 6) begin:CHNL_SEL_6 + +always @(*) begin + if (is_schedule) begin + case (last_chnl) + 0: chnl_idx = hit_priority[0] ? 1 : + hit_priority[1] ? 2 : + hit_priority[2] ? 3 : + hit_priority[3] ? 4 : + hit_priority[4] ? 5 : + hit_priority[5] ? 0 : 1 ; // last branch is chosen when no channel is valid. + 1: chnl_idx = hit_priority[0] ? 2 : + hit_priority[1] ? 3 : + hit_priority[2] ? 4 : + hit_priority[3] ? 5 : + hit_priority[4] ? 0 : + hit_priority[5] ? 1 : 2 ; // last branch is chosen when no channel is valid. + 2: chnl_idx = hit_priority[0] ? 3 : + hit_priority[1] ? 4 : + hit_priority[2] ? 5 : + hit_priority[3] ? 0 : + hit_priority[4] ? 1 : + hit_priority[5] ? 2 : 3 ; // last branch is chosen when no channel is valid. + 3: chnl_idx = hit_priority[0] ? 4 : + hit_priority[1] ? 5 : + hit_priority[2] ? 0 : + hit_priority[3] ? 1 : + hit_priority[4] ? 2 : + hit_priority[5] ? 3 : 4 ; // last branch is chosen when no channel is valid. + 4: chnl_idx = hit_priority[0] ? 5 : + hit_priority[1] ? 0 : + hit_priority[2] ? 1 : + hit_priority[3] ? 2 : + hit_priority[4] ? 3 : + hit_priority[5] ? 4 : 5 ; // last branch is chosen when no channel is valid. + 5: chnl_idx = hit_priority[0] ? 0 : + hit_priority[1] ? 1 : + hit_priority[2] ? 2 : + hit_priority[3] ? 3 : + hit_priority[4] ? 4 : + hit_priority[5] ? 5 : 0 ; // last branch is chosen when no channel is valid. + default: chnl_idx = {CHNL_NUM_LOG{1'd0}}; + endcase + end + else begin + chnl_idx = chnl_idx_reg; // chosen in REQ_TRANS state + end +end + +end // CHNL_NUM == 6 +else if (CHNL_NUM == 5) begin:CHNL_SEL_5 + +always @(*) begin + if (is_schedule) begin + case (last_chnl) + 0: chnl_idx = hit_priority[0] ? 1 : + hit_priority[1] ? 2 : + hit_priority[2] ? 3 : + hit_priority[3] ? 4 : + hit_priority[4] ? 0 : 1 ; // last branch is chosen when no channel is valid. + 1: chnl_idx = hit_priority[0] ? 2 : + hit_priority[1] ? 3 : + hit_priority[2] ? 4 : + hit_priority[3] ? 0 : + hit_priority[4] ? 1 : 2 ; // last branch is chosen when no channel is valid. + 2: chnl_idx = hit_priority[0] ? 3 : + hit_priority[1] ? 4 : + hit_priority[2] ? 0 : + hit_priority[3] ? 1 : + hit_priority[4] ? 2 : 3 ; // last branch is chosen when no channel is valid. + 3: chnl_idx = hit_priority[0] ? 4 : + hit_priority[1] ? 0 : + hit_priority[2] ? 1 : + hit_priority[3] ? 2 : + hit_priority[4] ? 3 : 4 ; // last branch is chosen when no channel is valid. + 4: chnl_idx = hit_priority[0] ? 0 : + hit_priority[1] ? 1 : + hit_priority[2] ? 2 : + hit_priority[3] ? 3 : + hit_priority[4] ? 4 : 0 ; // last branch is chosen when no channel is valid. + default: chnl_idx = {CHNL_NUM_LOG{1'd0}}; + endcase + end + else begin + chnl_idx = chnl_idx_reg; // chosen in REQ_TRANS state + end +end + +end // CHNL_NUM == 5 +else if (CHNL_NUM == 4) begin:CHNL_SEL_4 + +always @(*) begin + if (is_schedule) begin + case (last_chnl) + 0: chnl_idx = hit_priority[0] ? 1 : + hit_priority[1] ? 2 : + hit_priority[2] ? 3 : + hit_priority[3] ? 0 : 1 ; // last branch is chosen when no channel is valid. + 1: chnl_idx = hit_priority[0] ? 2 : + hit_priority[1] ? 3 : + hit_priority[2] ? 0 : + hit_priority[3] ? 1 : 2 ; // last branch is chosen when no channel is valid. + 2: chnl_idx = hit_priority[0] ? 3 : + hit_priority[1] ? 0 : + hit_priority[2] ? 1 : + hit_priority[3] ? 2 : 3 ; // last branch is chosen when no channel is valid. + 3: chnl_idx = hit_priority[0] ? 0 : + hit_priority[1] ? 1 : + hit_priority[2] ? 2 : + hit_priority[3] ? 3 : 0 ; // last branch is chosen when no channel is valid. + default: chnl_idx = {CHNL_NUM_LOG{1'd0}}; + endcase + end + else begin + chnl_idx = chnl_idx_reg; // chosen in REQ_TRANS state + end +end + +end // CHNL_NUM == 4 +else if (CHNL_NUM == 3) begin:CHNL_SEL_3 + +always @(*) begin + if (is_schedule) begin + case (last_chnl) + 0: chnl_idx = hit_priority[0] ? 1 : + hit_priority[1] ? 2 : + hit_priority[2] ? 0 : 1; // last branch is chosen when no channel is valid. + 1: chnl_idx = hit_priority[0] ? 2 : + hit_priority[1] ? 0 : + hit_priority[2] ? 1 : 2; // last branch is chosen when no channel is valid. + 2: chnl_idx = hit_priority[0] ? 0 : + hit_priority[1] ? 1 : + hit_priority[2] ? 2 : 0; // last branch is chosen when no channel is valid. + default: chnl_idx = {CHNL_NUM_LOG{1'd0}}; + endcase + end + else begin + chnl_idx = chnl_idx_reg; // chosen in REQ_TRANS state + end +end + +end // CHNL_NUM == 3 +else if (CHNL_NUM == 2) begin:CHNL_SEL_2 + +always @(*) begin + if (is_schedule) begin + case (last_chnl) + 0: chnl_idx = hit_priority[0] ? 1 : + hit_priority[1] ? 0 : 1 ; // last branch is chosen when no channel is valid. + 1: chnl_idx = hit_priority[0] ? 0 : + hit_priority[1] ? 1 : 0 ; // last branch is chosen when no channel is valid. + default: chnl_idx = {CHNL_NUM_LOG{1'd0}}; + endcase + end + else begin + chnl_idx = chnl_idx_reg; // chosen in REQ_TRANS state + end +end + +end // CHNL_NUM == 2 +endgenerate +/* + This is used for different Channel Numbers, the default Number is 4 */ +/* -------Generate block{end}------- */ + +// /* -------Core logic to arbit, a parameterized arbiter{begin}------- */ +// function [CHNL_NUM_LOG-1:0] find_chnl_num; +// input [CHNL_NUM_LOG-1:0] prio_level; +// input [CHNL_NUM_LOG-1:0] last_c; +// begin +// find_chnl_num = ((last_c+prio_level+1) >= CHNL_NUM) ? last_c+prio_level+1-CHNL_NUM : last_c+prio_level+1; +// end +// endfunction + +// function [CHNL_NUM-1:0] sel_prio; +// input [CHNL_NUM-1:0] sel; +// reg tmp; +// integer i, j; +// begin +// sel_prio[0] = sel[0]; +// for (i = 1; i < CHNL_NUM; i = i + 1) begin +// tmp = 0; +// for (j = 0; j < i; j = j + 1) begin +// tmp = tmp | sel[j]; +// end +// sel_prio[i] = !tmp & sel[i]; +// end +// end +// endfunction + +// function [CHNL_NUM_LOG-1:0] find_nxt_chnl; +// input [CHNL_NUM_LOG-1:0] last_c; +// input [CHNL_NUM-1:0] hit_prio; +// integer i; +// begin +// find_nxt_chnl = {CHNL_NUM_LOG{hit_prio[0]}} & find_chnl_num(0, last_c); +// for (i = 1; i < CHNL_NUM; i = i + 1) begin +// find_nxt_chnl = find_nxt_chnl | {CHNL_NUM_LOG{hit_prio[i]}} & find_chnl_num(i, last_c);; +// end +// end +// endfunction + +// always @(*) begin +// if (is_schedule) begin +// chnl_idx = find_nxt_chnl(last_chnl, sel_prio(hit_priority)); +// end +// else begin +// chnl_idx = chnl_idx_reg; // chosen in REQ_TRANS state +// end +// end +// /* -------Core logic to arbit, a parameterized arbiter{end}------- */ + +// state transform signal +assign req_last = m_axis_mux_tvalid & m_axis_mux_tready & m_axis_mux_tlast; + +/* -------Find next channel{end}------- */ + +/* -------{Read Request Arbiter FSM}begin------- */ +/******************** Stage 1: State Register **********************/ +assign is_idle = (cur_state == IDLE ); +assign is_schedule = (cur_state == SCHEDULE ); +assign is_req_trans = (cur_state == REQ_TRANS); +assign j_req_trans = is_schedule & (!req_last) & (|s_axis_mux_tvalid); +// assign j_schedule = is_schedule & (req_last) | +// is_req_trans & (req_last); + +always @(posedge clk, negedge rst_n) begin + if(~rst_n) + cur_state <= `TD IDLE; + else + cur_state <= `TD nxt_state; +end + +/******************** Stage 2: State Transition **********************/ + +always @(*) begin + case(cur_state) + IDLE: begin + if (|s_axis_mux_tvalid) begin + nxt_state = SCHEDULE; + end + else begin + nxt_state = IDLE; + end + end + SCHEDULE: begin + if (req_last) begin // one beat request has already been transmited in + // schedule state. + nxt_state = SCHEDULE; + end + else if (|s_axis_mux_tvalid) begin // There's valid channel, and not the last beat. + nxt_state = REQ_TRANS; + end + else begin + nxt_state = IDLE; + end + end + REQ_TRANS: begin + if (req_last) begin // request has already been transmited in + // req_trans state. + nxt_state = SCHEDULE; + end + else begin + nxt_state = REQ_TRANS; + end + end + default: begin + nxt_state = IDLE; + end + endcase +end +/******************** Stage 3: Output **********************/ + +/* -------Generate block{begin}------- */ +genvar n; +generate +for (n = 0; n < CHNL_NUM; n = n + 1) begin:CHNL_ASSIGN + +assign s_axis_mux_tready[n] = (is_schedule | is_req_trans) & (n == chnl_idx) & m_axis_mux_tready; + +assign s_channel_tvalid[n] = s_axis_mux_tvalid[((n+1) * 1 -1):(n * 1 )]; +assign s_channel_tlast [n] = s_axis_mux_tlast [((n+1) * 1 -1):(n * 1 )]; +assign s_channel_tdata [n] = s_axis_mux_tdata [((n+1) * TDATA_WIDTH-1):(n * TDATA_WIDTH)]; +assign s_channel_tuser [n] = s_axis_mux_tuser [((n+1) * TUSER_WIDTH-1):(n * TUSER_WIDTH)]; + +assign hit_priority[n] = s_channel_tvalid[nxt_priority[n]]; + +end +endgenerate +/* -------Generate block{end}------- */ + +assign m_axis_mux_tvalid = (is_schedule | is_req_trans) ? s_channel_tvalid[chnl_idx] : 1'd0; +assign m_axis_mux_tlast = (is_schedule | is_req_trans) ? s_channel_tlast [chnl_idx] : 1'd0; +assign m_axis_mux_tdata = (is_schedule | is_req_trans) ? s_channel_tdata [chnl_idx] : {TDATA_WIDTH{1'd0}}; +assign m_axis_mux_tuser = (is_schedule | is_req_trans) ? s_channel_tuser [chnl_idx] : {TUSER_WIDTH{1'd0}}; + +/* -------{Read Request Arbiter FSM}end------- */ + + +endmodule diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Common/st_reg.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Common/st_reg.v new file mode 100644 index 0000000000000000000000000000000000000000..1d7e60bd722eeb7dee27f0a7e812b45ad55a7e96 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Common/st_reg.v @@ -0,0 +1,110 @@ +`timescale 1ns / 100ps +//************************************************************************* +// > File Name: st_reg.v +// > Author : Kangning +// > Date : 2022-07-18 +// > Note : A general module used to temporarily store the input +// > axis-like signal for one cycle. +//************************************************************************* + + +module st_reg #( + parameter TUSER_WIDTH = 128, + parameter TDATA_WIDTH = 256, + parameter MODE = 0, // The default mode is 0 + parameter NUM_LEVELS = 1 +) ( + input wire clk , // i, 1 + input wire rst_n , // i, 1 + + /* -------input axis-like interface{begin}------- */ + input wire axis_tvalid , // i, 1 + input wire axis_tlast , // i, 1 + input wire [TUSER_WIDTH-1:0] axis_tuser , // i, TUSER_WIDTH + input wire [TDATA_WIDTH-1:0] axis_tdata , // i, TDATA_WIDTH + output wire axis_tready , // o, 1 + /* -------input axis-like interface{end}------- */ + + /* -------output in_reg inteface{begin}------- */ + output wire axis_reg_tvalid, // read valid from input register + output wire axis_reg_tlast , + output wire [TUSER_WIDTH-1:0] axis_reg_tuser , + output wire [TDATA_WIDTH-1:0] axis_reg_tdata , + input wire axis_reg_tready + + // input wire is_tuser_clear, // Optional, clear the present tuser. + // // Usually, it is asserted when + // // *_valid & *_ready & *_last + // output reg axis_reg_sop // Indicate the start of a pkt + /* -------output in_reg inteface{end}------- */ +); + +wire axis_out_tlast; +wire [TUSER_WIDTH-1:0] axis_out_tuser; +wire [TDATA_WIDTH-1:0] axis_out_tdata; + +gp_slice_ml #( + .NUM_LEVELS (NUM_LEVELS ), + .PAYLD_WIDTH (1 + TUSER_WIDTH + TDATA_WIDTH ), + .MODE (MODE ), + .SYNC_RESET (0 ) +) u_gp_slice_ml_PE ( + .clk ( clk ), + .rst_n ( rst_n ), + + .vld_m ( axis_tvalid ), + .rdy_m ( axis_tready ), + .payld_m ( {axis_tlast, axis_tuser, axis_tdata} ), + .vld_s ( axis_reg_tvalid ), + .rdy_s ( axis_reg_tready ), + .payld_s ( {axis_out_tlast, axis_out_tuser, axis_out_tdata} ) +); +assign {axis_reg_tlast, axis_reg_tuser, axis_reg_tdata} = axis_reg_tvalid ? {axis_out_tlast, axis_out_tuser, axis_out_tdata} : {1 + TUSER_WIDTH + TDATA_WIDTH{1'd0}}; + +// /* -------in_reg logic{begin}------- */ +// always @(posedge clk, negedge rst_n) begin +// if (~rst_n) begin +// axis_reg_sop <= `TD 1; +// end +// else if (axis_tvalid & axis_tready & axis_tlast) begin +// axis_reg_sop <= `TD 1; +// end +// else if (axis_tvalid & axis_tready & axis_reg_sop) begin +// axis_reg_sop <= `TD 0; +// end +// end + +// always @(posedge clk, negedge rst_n) begin +// if (~rst_n) begin +// axis_reg_tuser <= `TD 0; +// end +// else if (axis_tvalid & axis_tready & axis_reg_sop) begin +// axis_reg_tuser <= `TD axis_tuser; +// end +// else if (is_tuser_clear) begin // after trans finished, axis_reg_tuser is set to 0 +// axis_reg_tuser <= `TD 0; +// end +// end + +// always @(posedge clk, negedge rst_n) begin +// if (~rst_n) begin +// axis_reg_tvalid <= `TD 0; +// axis_reg_tlast <= `TD 0; +// axis_reg_tdata <= `TD 0; +// end +// else if (axis_tvalid & axis_tready) begin // write en & not full +// axis_reg_tvalid <= `TD 1; +// axis_reg_tlast <= `TD axis_tlast; +// axis_reg_tdata <= `TD axis_tdata; +// end +// else if (axis_reg_tready & axis_reg_tvalid) begin // read en & not empty +// axis_reg_tvalid <= `TD 0; +// axis_reg_tlast <= `TD 0; +// axis_reg_tdata <= `TD 0; +// end +// end + +// assign axis_tready = !axis_reg_tvalid | axis_reg_tready; // empty | going to empty +// /* -------in_reg logic{end}------- */ + +endmodule diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Common/stream_fifo.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Common/stream_fifo.v new file mode 100644 index 0000000000000000000000000000000000000000..3b5df4ac2fa3da3ac52146d22fee110aef4ef063 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Common/stream_fifo.v @@ -0,0 +1,101 @@ +`timescale 1ns / 100ps + +module stream_fifo #( + TUSER_WIDTH = 128, + TDATA_WIDTH = 256, + TKEEP_WIDTH = TDATA_WIDTH / 8 +) ( + input wire clk , // i, 1 + input wire rst , // i, 1 + + /* -------input axis-like interface{begin}------- */ + input wire axis_tvalid , // i, 1 + input wire axis_tlast , // i, 1 + input wire [TUSER_WIDTH-1:0] axis_tuser , // i, TUSER_WIDTH + input wire [TDATA_WIDTH-1:0] axis_tdata , // i, TDATA_WIDTH + output wire axis_tready , // o, 1 + input wire axis_tstart, + input wire [TKEEP_WIDTH-1:0] axis_tkeep, + + /* -------input axis-like interface{end}------- */ + + /* -------output in_reg inteface{begin}------- */ + output wire in_reg_tvalid, // read valid from input register + output wire in_reg_tlast , + output wire [TUSER_WIDTH-1:0] in_reg_tuser , + output wire [TDATA_WIDTH-1:0] in_reg_tdata , + output wire [TKEEP_WIDTH-1:0] in_reg_tkeep , + output wire in_reg_tstart, + input wire in_reg_tready + /* -------output in_reg inteface{end}------- */ +); + +wire payload_wr_en; +wire [(TDATA_WIDTH + 1 + 1) - 1 : 0] payload_din; +wire payload_prog_full; +wire payload_rd_en; +wire [(TDATA_WIDTH + 1 + 1) - 1 : 0] payload_dout; +wire payload_empty; + +wire header_wr_en; +wire [TUSER_WIDTH - 1 : 0] header_din; +wire header_prog_full; +wire header_rd_en; +wire [TUSER_WIDTH - 1 : 0] header_dout; +wire header_empty; + +assign payload_wr_en = axis_tvalid && axis_tready; +assign payload_din = {axis_tlast, axis_tstart, axis_tdata}; + +assign header_wr_en = axis_tvalid && axis_tready; +assign header_din = axis_tuser; + +assign axis_tready = !header_prog_full && !payload_prog_full; + +assign header_rd_en = in_reg_tready && !header_empty; +assign payload_rd_en = in_reg_tready && !payload_empty; + +SyncFIFO_Template #( + .FIFO_WIDTH ( TUSER_WIDTH ), + .FIFO_DEPTH ( 16 ) +) +HeaderFIFO +( + .clk ( clk ), + .rst ( rst ), + + .wr_en ( header_wr_en ), + .din ( header_din ), + .prog_full ( header_prog_full ), + .rd_en ( header_rd_en ), + .dout ( header_dout ), + .empty ( header_empty ), + .data_count ( ) +); + +SyncFIFO_Template #( + .FIFO_WIDTH ( TDATA_WIDTH + 1 + 1 ), + .FIFO_DEPTH ( 16 ) +) +PayloadFIFO +( + .clk ( clk ), + .rst ( rst ), + + .wr_en ( payload_wr_en ), + .din ( payload_din ), + .prog_full ( payload_prog_full ), + .rd_en ( payload_rd_en ), + .dout ( payload_dout ), + .empty ( payload_empty ), + .data_count ( ) +); + +assign in_reg_tvalid = !header_empty && !payload_empty; +assign in_reg_tstart = in_reg_tvalid ? payload_dout[TDATA_WIDTH] : 'd0; +assign in_reg_tlast = in_reg_tvalid ? payload_dout[TDATA_WIDTH + 1] : 'd0; +assign in_reg_tkeep = 'd0; +assign in_reg_tuser = in_reg_tvalid ? header_dout : 'd0; +assign in_reg_tdata = in_reg_tvalid ? payload_dout : 'd0; + +endmodule diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Common/stream_reg.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Common/stream_reg.v new file mode 100644 index 0000000000000000000000000000000000000000..fd558691c55f3f0f1e577f6451fd6ad3ce93760c --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Common/stream_reg.v @@ -0,0 +1,62 @@ +`timescale 1ns / 100ps + +module stream_reg #( + TUSER_WIDTH = 128, + TDATA_WIDTH = 256, + TKEEP_WIDTH = TDATA_WIDTH / 8, + MODE = 0, + NUM_LEVELS = 1 +) ( + input wire clk , // i, 1 + input wire rst_n , // i, 1 + + /* -------input axis-like interface{begin}------- */ + input wire axis_tvalid , // i, 1 + input wire axis_tlast , // i, 1 + input wire [TUSER_WIDTH-1:0] axis_tuser , // i, TUSER_WIDTH + input wire [TDATA_WIDTH-1:0] axis_tdata , // i, TDATA_WIDTH + output wire axis_tready , // o, 1 + input wire axis_tstart, + input wire [TKEEP_WIDTH-1:0] axis_tkeep, + + /* -------input axis-like interface{end}------- */ + + /* -------output in_reg inteface{begin}------- */ + output wire in_reg_tvalid, // read valid from input register + output wire in_reg_tlast , + output wire [TUSER_WIDTH-1:0] in_reg_tuser , + output wire [TDATA_WIDTH-1:0] in_reg_tdata , + output wire [TKEEP_WIDTH-1:0] in_reg_tkeep , + output wire in_reg_tstart, + input wire in_reg_tready, + + input wire tuser_clear + /* -------output in_reg inteface{end}------- */ +); + +wire [(TUSER_WIDTH + TDATA_WIDTH + TKEEP_WIDTH + 1 + 1) - 1 : 0] payload_slave; + +gp_slice_ml #( + .NUM_LEVELS (NUM_LEVELS ), + .PAYLD_WIDTH (TUSER_WIDTH + TDATA_WIDTH + TKEEP_WIDTH + 1 + 1), + .MODE (MODE ), + .SYNC_RESET (0 ) +) u_gp_slice_ml_PE ( + .clk(clk), + .rst_n(rst_n), + + .vld_m(axis_tvalid), + .rdy_m(axis_tready), + .payld_m({axis_tstart, axis_tlast, axis_tkeep, axis_tuser, axis_tdata}), + .vld_s(in_reg_tvalid), + .rdy_s(in_reg_tready), + .payld_s(payload_slave) +); + +assign in_reg_tstart = in_reg_tvalid ? payload_slave[(TUSER_WIDTH + TDATA_WIDTH + TKEEP_WIDTH + 1 + 1) - 1] : 'd0; +assign in_reg_tlast = in_reg_tvalid ? payload_slave[(TUSER_WIDTH + TDATA_WIDTH + TKEEP_WIDTH + 1 + 1) - 2] : 'd0; +assign in_reg_tkeep = in_reg_tvalid ? payload_slave[(TUSER_WIDTH + TDATA_WIDTH + TKEEP_WIDTH) - 1 : (TUSER_WIDTH + TDATA_WIDTH)] : 'd0; +assign in_reg_tuser = in_reg_tvalid ? payload_slave[(TUSER_WIDTH + TDATA_WIDTH) - 1 : (TDATA_WIDTH)] : 'd0; +assign in_reg_tdata = in_reg_tvalid ? payload_slave[(TDATA_WIDTH) - 1 : 0] : 'd0; + +endmodule diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Common/sync_reset.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Common/sync_reset.v new file mode 100644 index 0000000000000000000000000000000000000000..2e7bcc4b74bd90ccf8654249e7278dbbfd4bda55 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Common/sync_reset.v @@ -0,0 +1,35 @@ +`resetall +`timescale 1ns / 1ps +`default_nettype none + +/* + * Synchronizes an active-high asynchronous reset signal to a given clock by + * using a pipeline of N registers. + */ +module sync_reset # +( + // depth of synchronizer + parameter N = 2 +) +( + input wire clk, + input wire rst, + output wire out +); + +(* srl_style = "register" *) +reg [N-1:0] sync_reg = {N{1'b1}}; + +assign out = sync_reg[N-1]; + +always @(posedge clk or posedge rst) begin + if (rst) begin + sync_reg <= {N{1'b1}}; + end else begin + sync_reg <= {sync_reg[N-2:0], 1'b0}; + end +end + +endmodule + +`resetall \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/EthSubsystem/README.md b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/EthSubsystem/README.md new file mode 100644 index 0000000000000000000000000000000000000000..3e4d26a7ae02107f066bbb3bbb386ef04c7d61b6 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/EthSubsystem/README.md @@ -0,0 +1 @@ +EthSubsystem diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/DMA/DMA.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/DMA/DMA.v new file mode 100644 index 0000000000000000000000000000000000000000..35b30eee795e59812667d72a68588900a74980cf --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/DMA/DMA.v @@ -0,0 +1,826 @@ +`timescale 1ns / 100ps +//************************************************************************* +// > File Name: DMA.v +// > Author : Kangning +// > Date : 2020-08-17 +// > Note : DMA module, used to generate DMA Interface +// > V1.1 - 2021-01-29: Modify formation of code, make it more generalize. +//************************************************************************* + +//`include "../lib/global_include_h.v" +//`include "../lib/dma_def_h.v" + +module DMA #( + +) ( + input wire pcie_clk , + input wire pcie_rst_n, + input wire dma_clk , + input wire rst_n , + output wire init_done , // o, 1 + + /* -------dma interface{begin}------- */ + /* *_head of DMA interface (interact with RDMA modules), + * valid only in first beat of a packet. + * When Transmiting msi-x interrupt message, 'Byte length' + * should be 0, 'address' means the address of msi-x, and + * msi-x data locates in *_data[31:0]. + * | Resvd | Req Type | address | Reserved | Byte length | + * | |(rd,wr,int)| (msi-x addr) | | (0 for int) | + * |-------|-----------|--------------|----------|-------------| + * |127:100| 99:96 | 95:32 | 31:13 | 12:0 | + */ + // Read Req + input wire [`DMA_RD_CHNL_NUM * 1 -1:0] dma_rd_req_valid, + input wire [`DMA_RD_CHNL_NUM * 1 -1:0] dma_rd_req_last , + input wire [`DMA_RD_CHNL_NUM * `DMA_DATA_W-1:0] dma_rd_req_data , + input wire [`DMA_RD_CHNL_NUM * `DMA_HEAD_W-1:0] dma_rd_req_head , + output wire [`DMA_RD_CHNL_NUM * 1 -1:0] dma_rd_req_ready, + + // DMA Read Resp + output wire [`DMA_RD_CHNL_NUM * 1 -1:0] dma_rd_rsp_valid, + output wire [`DMA_RD_CHNL_NUM * 1 -1:0] dma_rd_rsp_last , + output wire [`DMA_RD_CHNL_NUM * `DMA_DATA_W-1:0] dma_rd_rsp_data , + output wire [`DMA_RD_CHNL_NUM * `DMA_HEAD_W-1:0] dma_rd_rsp_head , + input wire [`DMA_RD_CHNL_NUM * 1 -1:0] dma_rd_rsp_ready, + + // DMA Write Req + input wire [`DMA_WR_CHNL_NUM * 1 -1:0] dma_wr_req_valid, + input wire [`DMA_WR_CHNL_NUM * 1 -1:0] dma_wr_req_last , + input wire [`DMA_WR_CHNL_NUM * `DMA_DATA_W-1:0] dma_wr_req_data , + input wire [`DMA_WR_CHNL_NUM * `DMA_HEAD_W-1:0] dma_wr_req_head , + output wire [`DMA_WR_CHNL_NUM * 1 -1:0] dma_wr_req_ready, + /* -------dma interface{end}------- */ + + + /* -------Requester Request{begin}------- */ + /* RQ tuser + * | 59:28 | 27:24 | 23:16 | 15 | 14:13 | 12 | 11 | 10:8 | 7:4 | 3:0 | + * | parity | seq_num | tph_st_tag | tph_indirect_tag_en | tph_type | tph_present | discontinue | addr_offset | last_be | first_be | + * | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | | + */ + output wire s_axis_rq_tvalid, + output wire s_axis_rq_tlast , + output wire [`DMA_DATA_W-1:0] s_axis_rq_tdata , + output wire [59 :0] s_axis_rq_tuser , + output wire [`DMA_KEEP_W-1:0] s_axis_rq_tkeep , + input wire s_axis_rq_tready, + /* -------Requester Request{end}------- */ + + /* -------Requester Completion{begin}------- */ + /* RC tuser + * | 74:43 | 42 | 41:38 | 37:34 | 33 | 32 | 31:0 | + * | parity | discontinue | is_eof_1 | is_eof_0 | is_sof_1 | is_sof_0 | byte_en | + * | ignore | ignore | ignore | ignore | ignore | ignore | | + */ + input wire m_axis_rc_tvalid, + input wire m_axis_rc_tlast , + input wire [`DMA_DATA_W-1:0] m_axis_rc_tdata , + input wire [74 :0] m_axis_rc_tuser , + input wire [`DMA_KEEP_W-1:0] m_axis_rc_tkeep , + output wire m_axis_rc_tready, + /* -------Requester Completion{end}------- */ + + /* -------Interrupt Interface Signals{begin}------- */ + input [1:0] cfg_interrupt_msix_enable , + input [1:0] cfg_interrupt_msix_mask , + output [31:0] cfg_interrupt_msix_data , + output [63:0] cfg_interrupt_msix_address , + output cfg_interrupt_msix_int , + input cfg_interrupt_msix_sent , + input cfg_interrupt_msix_fail , + output wire [2:0] cfg_interrupt_msi_function_number, + /* -------Interrupt Interface Signals{end}------- */ + + /* -------Configuration Status Interface{begin}------- */ + input wire [ 2:0] max_pyld_sz , + input wire [ 2:0] max_rd_req_sz, + input wire [15:0] req_id + /* -------Configuration Status Interface{end}------- */ + +`ifdef PCIEI_APB_DBG + /* -------APB reated signal{begin}------- */ + ,input wire [(2*`DMA_RD_CHNL_NUM+`DMA_WR_CHNL_NUM+6)*`SRAM_RW_DATA_W-1:0] rw_data // i, (2*`DMA_RD_CHNL_NUM+`DMA_WR_CHNL_NUM+6)*`SRAM_RW_DATA_W + ,input wire [31:0] dbg_sel // debug bus select + ,output wire [31:0] dbg_bus // debug bus data + /* -------APB reated signal{end}------- */ +`endif + +`ifdef SIMULATION + /* ------- Debug interface {begin}------- */ + /* | reserved | + * | 255:47 | + * | tag_num | tag_chnl | valid | + * | 46:39 | 38:31 | 30 | + * | top_idx | top_end | top_out| + * | 29:22 | 21 | 20 | + * | rd_idx | rd_end | rd_out | + * | 19:12 | 11 | 10 | + * | wr_idx | wr_end | wr_out | + * | 9:2 | 1 | 0 | + */ + ,output wire [255:0] debug + /* ------- Debug interface {end}------- */ +`endif +); + +`ifdef SIMULATION + +wire [255:0] debug_wr, debug_rd, debug_top, debug_tag; +assign debug = {209'd0, debug_tag[16:0], debug_top[9:0], debug_rd[9:0], debug_wr[9:0]}; + +`endif + +/* -------Used in wr arbiter{begin}------- */ +wire [`DMA_WR_CHNL_NUM * 1 -1:0] axis_wr_req_tvalid; +wire [`DMA_WR_CHNL_NUM * 1 -1:0] axis_wr_req_tlast ; +wire [`DMA_WR_CHNL_NUM * `DMA_DATA_W -1:0] axis_wr_req_tdata ; +wire [`DMA_WR_CHNL_NUM * `AXIS_TUSER_W-1:0] axis_wr_req_tuser ; +wire [`DMA_WR_CHNL_NUM * `DMA_KEEP_W -1:0] axis_wr_req_tkeep ; +wire [`DMA_WR_CHNL_NUM * 1 -1:0] axis_wr_req_tready; +/* -------Used in wr arbiter{end}------- */ + +/* -------Used in rd & wr arbiter{begin}------- */ +wire axis_wreq_tvalid; +wire axis_wreq_tlast ; +wire [`DMA_DATA_W -1:0] axis_wreq_tdata ; +wire [`AXIS_TUSER_W-1:0] axis_wreq_tuser ; +wire [`DMA_KEEP_W -1:0] axis_wreq_tkeep ; +wire axis_wreq_tready; + +wire axis_rreq_tvalid; +wire axis_rreq_tlast ; +wire [`DMA_DATA_W -1:0] axis_rreq_tdata ; +wire [`AXIS_TUSER_W-1:0] axis_rreq_tuser ; +wire [`DMA_KEEP_W -1:0] axis_rreq_tkeep ; +wire axis_rreq_tready; +/* -------Used in rd & wr arbiter{end}------- */ + +wire axis_req_tvalid; +wire axis_req_tlast ; +wire [`DMA_DATA_W -1:0] axis_req_tdata ; +wire [`AXIS_TUSER_W-1:0] axis_req_tuser ; +wire [`DMA_KEEP_W -1:0] axis_req_tkeep ; +wire axis_req_tready; + + + +/* -------Used in read response{begin}------- */ +// In pcie clock domain +wire pcie_axis_rrsp_tvalid; +wire pcie_axis_rrsp_tlast ; +wire [`DMA_DATA_W -1:0] pcie_axis_rrsp_tdata ; +wire [`AXIS_TUSER_W-1:0] pcie_axis_rrsp_tuser ; +wire [`DMA_KEEP_W -1:0] pcie_axis_rrsp_tkeep ; +wire pcie_axis_rrsp_tready; + +// in dma clock domain +wire dma_axis_rrsp_tvalid; +wire dma_axis_rrsp_tlast ; +wire [`DMA_DATA_W -1:0] dma_axis_rrsp_tdata ; +wire [`AXIS_TUSER_W-1:0] dma_axis_rrsp_tuser ; +wire [`DMA_KEEP_W -1:0] dma_axis_rrsp_tkeep ; +wire dma_axis_rrsp_tready; +/* -------Used in read response{end}------- */ + + + +/* --------Used in RQ & RC {begin}-------- */ +wire dma_axis_rq_tvalid; +wire dma_axis_rq_tlast ; +wire [`DMA_DATA_W-1:0] dma_axis_rq_tdata ; +wire [59 :0] dma_axis_rq_tuser ; +wire [`DMA_KEEP_W-1:0] dma_axis_rq_tkeep ; +wire dma_axis_rq_tready; + +// wire dma_axis_rc_tvalid; +// wire dma_axis_rc_tlast ; +// wire [`DMA_DATA_W-1:0] dma_axis_rc_tdata ; +// wire [74 :0] dma_axis_rc_tuser ; +// wire [`DMA_KEEP_W-1:0] dma_axis_rc_tkeep ; +// wire dma_axis_rc_tready; +/* --------Used in RQ & RC {end}-------- */ + +`ifdef PCIEI_APB_DBG +/* -------APB reated signal{begin}------- */ +wire [(2*`DMA_RD_CHNL_NUM+3)*`SRAM_RW_DATA_W-1:0] rw_data_rd_req_rsp; +wire [`DMA_WR_CHNL_NUM*`SRAM_RW_DATA_W-1:0] rw_data_wr_req; +wire [`SRAM_RW_DATA_W-1:0] rw_data_int; +wire [`SRAM_RW_DATA_W-1:0] rw_data_rq; +wire [`SRAM_RW_DATA_W-1:0] rw_data_rc; + +wire [32-1:0] dbg_sel_dma_top, dbg_sel_rd_req_rsp, dbg_sel_wr_req, dbg_sel_wreq_arb, dbg_sel_req_arb, + dbg_sel_req_convert, dbg_sel_rsp_convert; +wire [32-1:0] dbg_bus_dma_top, dbg_bus_rd_req_rsp, dbg_bus_wr_req, dbg_bus_wreq_arb, dbg_bus_req_arb, + dbg_bus_req_convert, dbg_bus_rsp_convert; + +wire [`DMA_TOP_SIGNAL_W-1:0] dbg_signal_dma_top; +wire [`DMA_WR_CHNL_NUM*`WR_REQ_SIGNAL_W-1:0] dbg_signal_wr_req; +wire [`WREQ_ARB_SIGNAL_W-1:0] dbg_signal_wreq_arb; +wire [`REQ_ARB_SIGNAL_W -1:0] dbg_signal_req_arb; +wire [`RQ_ASYNC_SIGNAL_W-1:0] dbg_signal_rq_async; +wire [`RC_ASYNC_SIGNAL_W-1:0] dbg_signal_rc_async; +wire [`RRSP_ASYNC_SIGNAL_W-1:0] dbg_signal_rrsp_async; +/* -------APB reated signal{end}------- */ +`endif + +//----------------------------------------------------------------------------------------------------------------------------- + +`ifdef PCIEI_APB_DBG +/* -------APB reated signal{begin}------- */ +assign {rw_data_rd_req_rsp, rw_data_wr_req, rw_data_int, rw_data_rq, rw_data_rc} = rw_data; + +assign dbg_bus = (`DMA_TOP_DBG_B <= dbg_sel && dbg_sel < `RD_REQ_RSP_DBG_B ) ? dbg_bus_dma_top : + (`RD_REQ_RSP_DBG_B <= dbg_sel && dbg_sel < `WR_REQ_DBG_B ) ? dbg_bus_rd_req_rsp : + (`WR_REQ_DBG_B <= dbg_sel && dbg_sel < `WREQ_ARB_DBG_B ) ? dbg_bus_wr_req : + (`WREQ_ARB_DBG_B <= dbg_sel && dbg_sel < `REQ_ARB_DBG_B ) ? dbg_bus_wreq_arb : + (`REQ_ARB_DBG_B <= dbg_sel && dbg_sel < `REQ_CONVERT_DBG_B) ? dbg_bus_req_arb : + (`REQ_CONVERT_DBG_B <= dbg_sel && dbg_sel < `RSP_CONVERT_DBG_B) ? dbg_bus_req_convert : + (`RSP_CONVERT_DBG_B <= dbg_sel && dbg_sel < `DMA_DBG_SIZE ) ? dbg_bus_rsp_convert : 32'd0; + +assign dbg_sel_dma_top = (`DMA_TOP_DBG_B <= dbg_sel && dbg_sel < `RD_REQ_RSP_DBG_B ) ? (dbg_sel - `DMA_TOP_DBG_B ) : 32'd0; +assign dbg_sel_rd_req_rsp = (`RD_REQ_RSP_DBG_B <= dbg_sel && dbg_sel < `WR_REQ_DBG_B ) ? (dbg_sel - `RD_REQ_RSP_DBG_B ) : 32'd0; +assign dbg_sel_wr_req = (`WR_REQ_DBG_B <= dbg_sel && dbg_sel < `WREQ_ARB_DBG_B ) ? (dbg_sel - `WR_REQ_DBG_B ) : 32'd0; +assign dbg_sel_wreq_arb = (`WREQ_ARB_DBG_B <= dbg_sel && dbg_sel < `REQ_ARB_DBG_B ) ? (dbg_sel - `WREQ_ARB_DBG_B ) : 32'd0; +assign dbg_sel_req_arb = (`REQ_ARB_DBG_B <= dbg_sel && dbg_sel < `REQ_CONVERT_DBG_B) ? (dbg_sel - `REQ_ARB_DBG_B ) : 32'd0; +assign dbg_sel_req_convert = (`REQ_CONVERT_DBG_B <= dbg_sel && dbg_sel < `RSP_CONVERT_DBG_B) ? (dbg_sel - `REQ_CONVERT_DBG_B) : 32'd0; +assign dbg_sel_rsp_convert = (`RSP_CONVERT_DBG_B <= dbg_sel && dbg_sel < `DMA_DBG_SIZE ) ? (dbg_sel - `RSP_CONVERT_DBG_B) : 32'd0; + + +// Debug signal for DMA_top +assign dbg_bus_dma_top = dbg_signal_dma_top >> {dbg_sel_dma_top, 5'd0}; + +// Debug signal for wr req +assign dbg_bus_wr_req = dbg_signal_wr_req >> {dbg_sel_wr_req, 5'd0}; + +// Debug signal for wreq arbiter +assign dbg_bus_wreq_arb = dbg_signal_wreq_arb >> {dbg_sel_wreq_arb, 5'd0}; + +// Debug signal for wreq arbiter +assign dbg_bus_req_arb = dbg_signal_req_arb >> {dbg_sel_req_arb, 5'd0}; + +assign dbg_signal_dma_top = { // 17275 + init_done, // 1 + dma_rd_req_valid, dma_rd_req_last, dma_rd_req_data, dma_rd_req_head, dma_rd_req_ready, // 3483 = 9*387 + dma_rd_rsp_valid, dma_rd_rsp_last, dma_rd_rsp_data, dma_rd_rsp_head, dma_rd_rsp_ready, // 3483 = 9*387 + dma_wr_req_valid, dma_wr_req_last, dma_wr_req_data, dma_wr_req_head, dma_wr_req_ready, // 3096 = 8*387 + s_axis_rq_tvalid, s_axis_rq_tlast, s_axis_rq_tdata, s_axis_rq_tuser, s_axis_rq_tkeep , s_axis_rq_tready, // 327 + m_axis_rc_tvalid, m_axis_rc_tlast, m_axis_rc_tdata, m_axis_rc_tuser, m_axis_rc_tkeep , m_axis_rc_tready, // 342 + + cfg_interrupt_msix_enable , + cfg_interrupt_msix_mask , + cfg_interrupt_msix_data , + cfg_interrupt_msix_address , + cfg_interrupt_msix_int , + cfg_interrupt_msix_sent , + cfg_interrupt_msix_fail , + cfg_interrupt_msi_function_number, // 106 + + max_pyld_sz,max_rd_req_sz, // 6 + axis_wr_req_tvalid, axis_wr_req_tlast, axis_wr_req_tdata, axis_wr_req_tuser, axis_wr_req_tkeep, axis_wr_req_tready, // 3160=395*8 + axis_wreq_tvalid, axis_wreq_tlast, axis_wreq_tdata, axis_wreq_tuser, axis_wreq_tkeep, axis_wreq_tready, // 395 + axis_rreq_tvalid, axis_rreq_tlast, axis_rreq_tdata, axis_rreq_tuser, axis_rreq_tkeep, axis_rreq_tready, // 395 + axis_req_tvalid, axis_req_tlast, axis_req_tdata, axis_req_tuser, axis_req_tkeep, axis_req_tready, // 395 + pcie_axis_rrsp_tvalid, pcie_axis_rrsp_tlast, pcie_axis_rrsp_tdata, pcie_axis_rrsp_tuser, pcie_axis_rrsp_tkeep, pcie_axis_rrsp_tready, // 395 + dma_axis_rrsp_tvalid, dma_axis_rrsp_tlast, dma_axis_rrsp_tdata, dma_axis_rrsp_tuser, dma_axis_rrsp_tkeep, dma_axis_rrsp_tready, // 395 + dma_axis_rq_tvalid, dma_axis_rq_tlast, dma_axis_rq_tdata, dma_axis_rq_tuser, dma_axis_rq_tkeep, dma_axis_rq_tready, // 327 + // dma_axis_rc_tvalid, dma_axis_rc_tlast, dma_axis_rc_tdata, dma_axis_rc_tuser, dma_axis_rc_tkeep, dma_axis_rc_tready, // 342 + + dbg_signal_rq_async, // 885 + // dbg_signal_rc_async // 34 + dbg_signal_rrsp_async // 84 +}; +/* -------APB reated signal{end}------- */ +`endif + +read_req_rsp #( + +) rd_req_rsp ( + .dma_clk ( dma_clk ), // i, 1 + .rst_n ( rst_n ), // i, 1 + .init_done ( init_done ), // o, 1 + + /* ------- Read Request from RDMA{begin}------- */ + /* dma_*_head (interact with RDMA modules), valid only in first beat of a packet + * | Reserved | address | Reserved | Byte length | + * | 127:96 | 95:32 | 31:13 | 12:0 | + */ + .dma_rd_req_valid ( dma_rd_req_valid ), // i, `DMA_RD_CHNL_NUM * 1 + .dma_rd_req_last ( dma_rd_req_last ), // i, `DMA_RD_CHNL_NUM * 1 + .dma_rd_req_data ( dma_rd_req_data ), // i, `DMA_RD_CHNL_NUM * `DMA_DATA_W + .dma_rd_req_head ( dma_rd_req_head ), // i, `DMA_RD_CHNL_NUM * `DMA_HEAD_W + .dma_rd_req_ready ( dma_rd_req_ready ), // o, `DMA_RD_CHNL_NUM * 1 + /* ------- Read Request from RDMA{end}------- */ + + /* ------- Read Response to RDMA{begin} ------- */ + /* dma_*_head (interact with RDMA modules), valid only in first beat of a packet + * | Reserved | address | Reserved | Byte length | + * | 127:96 | 95:32 | 31:13 | 12:0 | + */ + .dma_rd_rsp_valid ( dma_rd_rsp_valid ), // o, `DMA_RD_CHNL_NUM * 1 + .dma_rd_rsp_last ( dma_rd_rsp_last ), // o, `DMA_RD_CHNL_NUM * 1 + .dma_rd_rsp_data ( dma_rd_rsp_data ), // o, `DMA_RD_CHNL_NUM * `DMA_DATA_W + .dma_rd_rsp_head ( dma_rd_rsp_head ), // o, `DMA_RD_CHNL_NUM * `DMA_HEAD_W + .dma_rd_rsp_ready ( dma_rd_rsp_ready ), // i, `DMA_RD_CHNL_NUM * 1 + /* ------- Read Response to RDMA{end} ------- */ + + /* -------axis read request interface{begin}------- */ + /* AXI-Stream read request tuser, interact with read request arbiter. + * Only valid in first beat of a packet + * | Reserved | REQ_TYPE | Tag | address | Reserved | DW length | first BE | last BE | + * | 127:108 | 107:104 | 103:96 | 95:32 | 31:19 | 18:8 | 7:4 | 3:0 | + */ + .axis_rd_req_tvalid ( axis_rreq_tvalid ), // o, 1 + .axis_rd_req_tlast ( axis_rreq_tlast ), // o, 1 + .axis_rd_req_tdata ( axis_rreq_tdata ), // o, `DMA_DATA_W + .axis_rd_req_tuser ( axis_rreq_tuser ), // o, `AXIS_TUSER_W + .axis_rd_req_tkeep ( axis_rreq_tkeep ), // o, `DMA_KEEP_W + .axis_rd_req_tready ( axis_rreq_tready ), // i, 1 + /* -------axis read request interface{end}------- */ + + /* -------axis read response interface{begin}------- */ + /* AXI-Stream read response tuser, interact with read response distributor. + * Only valid in first beat of a packet + * | Reserved | REQ CPL | Tag | address | Reserved | DW length | first BE | last BE | + * | 119:105 | 104 | 103:96 | 95:32 | 31:19 | 18:8 | 7:4 | 3:0 | + */ + .axis_rd_rsp_tvalid ( dma_axis_rrsp_tvalid ), // i, 1 + .axis_rd_rsp_tlast ( dma_axis_rrsp_tlast ), // i, 1 + .axis_rd_rsp_tdata ( dma_axis_rrsp_tdata ), // i, `DMA_DATA_W + .axis_rd_rsp_tuser ( dma_axis_rrsp_tuser ), // i, `AXIS_TUSER_W + .axis_rd_rsp_tkeep ( dma_axis_rrsp_tkeep ), // i, `DMA_KEEP_W + .axis_rd_rsp_tready ( dma_axis_rrsp_tready ), // o, 1 + /* -------axis read response interface{end}------- */ + + /* -------PCIe fragment property{begin}------- */ + /* This signal indicates the (max payload size & max read request size) agreed in the communication + * 3'b000 -- 128 B + * 3'b001 -- 256 B + * 3'b010 -- 512 B + * 3'b011 -- 1024B + * 3'b100 -- 2048B + * 3'b101 -- 4096B + */ + .max_pyld_sz ( max_pyld_sz ), // i, 3 + .max_rd_req_sz ( max_rd_req_sz ) // i, 3 + /* -------PCIe fragment property{end}------- */ + +`ifdef PCIEI_APB_DBG + /* -------APB reated signal{begin}------- */ + ,.rw_data ( rw_data_rd_req_rsp ) // i, (2*`DMA_RD_CHNL_NUM+3)*`SRAM_RW_DATA_W + ,.dbg_sel ( dbg_sel_rd_req_rsp ) // i, 32 + ,.dbg_bus ( dbg_bus_rd_req_rsp ) // o, 32 + /* -------APB reated signal{end}------- */ +`endif + +`ifdef SIMULATION + /* ------- Debug interface {begin}------- */ + /* | reserved | idx | end | out | + * | 255:CHNL_NUM_LOG+2 | CHNL_NUM_LOG+2-1:2 | 1 | 0 | + */ + ,.debug_rd ( debug_rd ) + + /* | reserved | tag_num | chnl_num | valid | + * | 255:17 | 16:9 | 8:1 | 0 | + */ + ,.debug_tag( debug_tag) + /* ------- Debug interface {end}------- */ +`endif +); + +genvar i; +generate +for (i = 0; i < `DMA_WR_CHNL_NUM; i = i + 1) begin:DMA_WR_CHNL + + write_request #( + + ) wr_req ( + .clk ( dma_clk ), // i, 1 + .rst_n ( rst_n ), // i, 1 + + /* -------dma write request interface{begin}------- */ + /* *_head of DMA interface (interact with RDMA modules), + * valid only in first beat of a packet. + * When Transmiting msi-x interrupt message, 'Byte length' + * should be 0, 'address' means the address of msi-x, and + * msi-x data locates in *_data[31:0]. + * | Resvd | Req Type | address | Reserved | Byte length | + * | | (wr,int) | (msi-x addr) | | (0 for int) | + * |-------|----------|--------------|----------|-------------| + * |127:100| 99:96 | 95:32 | 31:13 | 12:0 | + */ + .dma_wr_req_valid ( dma_wr_req_valid[(i + 1) * 1 - 1 : i * 1 ] ), // i, 1 + .dma_wr_req_last ( dma_wr_req_last [(i + 1) * 1 - 1 : i * 1 ] ), // i, 1 + .dma_wr_req_data ( dma_wr_req_data [(i + 1) * `DMA_DATA_W - 1 : i * `DMA_DATA_W] ), // i, `DMA_DATA_W + .dma_wr_req_head ( dma_wr_req_head [(i + 1) * `DMA_HEAD_W - 1 : i * `DMA_HEAD_W] ), // i, `DMA_HEAD_W + .dma_wr_req_ready ( dma_wr_req_ready[(i + 1) * 1 - 1 : i * 1 ] ), // o, 1 + /* -------dma write request interface{end}------- */ + + /* -------axis write request interface{begin}------- */ + /* AXI-Stream write request tuser, only valid in first beat of a packet + * | Reserved | REQ_TYPE | Tag | address | Reserved | DW length | first BE | last BE | + * | 127:108 | 107:104 | 103:96 | 95:32 | 31:19 | 18:8 | 7:4 | 3:0 | + * or + * AXI-Stream interrupt request tuser, only valid in first beat of a packet + * | Reserved | REQ_TYPE | Resv | address | Reserved | + * | 127:108 | 107:104 | 103:96 | 95:32 | 31:0 | + */ + .axis_wr_req_tvalid ( axis_wr_req_tvalid[(i+1) * 1 - 1 : i * 1 ] ), // o, 1 + .axis_wr_req_tlast ( axis_wr_req_tlast [(i+1) * 1 - 1 : i * 1 ] ), // o, 1 + .axis_wr_req_tdata ( axis_wr_req_tdata [(i+1) * `DMA_DATA_W - 1 : i * `DMA_DATA_W ] ), // o, `DMA_DATA_W + .axis_wr_req_tuser ( axis_wr_req_tuser [(i+1) * `AXIS_TUSER_W - 1 : i * `AXIS_TUSER_W] ), // o, `AXIS_TUSER_W ;The field contents are different from dma_*_tuser interface + .axis_wr_req_tkeep ( axis_wr_req_tkeep [(i+1) * `DMA_KEEP_W - 1 : i * `DMA_KEEP_W ] ), // o, `DMA_KEEP_W + .axis_wr_req_tready ( axis_wr_req_tready[(i+1) * 1 - 1 : i * 1 ] ), // i, 1 + /* -------axis write request interface{end}------- */ + + + /* -------PCIe fragment property{begin}------- */ + /* This signal indicates the (max payload size & max read request size) agreed in the communication + * 3'b000 -- 128 B + * 3'b001 -- 256 B + * 3'b010 -- 512 B + * 3'b011 -- 1024B + * 3'b100 -- 2048B + * 3'b101 -- 4096B + */ + .max_pyld_sz ( max_pyld_sz ), + .max_rd_req_sz ( max_rd_req_sz ) // max read request size + /* -------PCIe fragment property{end}------- */ + + `ifdef PCIEI_APB_DBG + /* -------APB reated signal{begin}------- */ + ,.rw_data ( rw_data_wr_req[(i+1)*`SRAM_RW_DATA_W-1:i*`SRAM_RW_DATA_W] ) // i, `SRAM_RW_DATA_W + ,.dbg_signal ( dbg_signal_wr_req[(i+1)*`WR_REQ_SIGNAL_W-1:i*`WR_REQ_SIGNAL_W] ) // o, `WR_REQ_SIGNAL_W + /* -------APB reated signal{end}------- */ + `endif + ); + +end +endgenerate + +req_arbiter #( + .CHNL_NUM_LOG ( `DMA_WR_CHNL_NUM_LOG ), + .CHANNEL_NUM ( `DMA_WR_CHNL_NUM ) // number of slave signals to arbit +) wr_req_arbiter ( + + .dma_clk ( dma_clk ), // i, 1 + .rst_n ( rst_n ), // i, 1 + + /* -------Slave AXIS Interface(Connect to Module){begin}------- */ + /* AXI-Stream write request tuser, only valid in first beat of a packet + * | Reserved | REQ_TYPE | Tag | address | Reserved | DW length | first BE | last BE | + * | 127:108 | 107:104 | 103:96 | 95:32 | 31:19 | 18:8 | 7:4 | 3:0 | + * or + * AXI-Stream interrupt request tuser, only valid in first beat of a packet + * | Reserved | REQ_TYPE | Resv | address | Reserved | + * | 127:108 | 107:104 | 103:96 | 95:32 | 31:0 | + */ + .s_axis_req_tvalid ( axis_wr_req_tvalid ), // i, 1 * CHANNEL_NUM + .s_axis_req_tlast ( axis_wr_req_tlast ), // i, 1 * CHANNEL_NUM + .s_axis_req_tdata ( axis_wr_req_tdata ), // i, `DMA_DATA_W * CHANNEL_NUM + .s_axis_req_tuser ( axis_wr_req_tuser ), // i, `AXIS_TUSER_W * CHANNEL_NUM ;The field contents are different from dma_*_tuser interface + .s_axis_req_tkeep ( axis_wr_req_tkeep ), // i, `DMA_KEEP_W * CHANNEL_NUM + .s_axis_req_tready ( axis_wr_req_tready ), // o, 1 * CHANNEL_NUM + /* -------Slave AXIS Interface(Connect to Module){end}------- */ + + + /* ------- Master AXIS Interface(Connect to PCIe or converter){begin} ------- */ + /* AXI-Stream write request tuser, only valid in first beat of a packet + * | Reserved | REQ_TYPE | Tag | address | Reserved | DW length | first BE | last BE | + * | 127:108 | 107:104 | 103:96 | 95:32 | 31:19 | 18:8 | 7:4 | 3:0 | + * or + * AXI-Stream interrupt request tuser, only valid in first beat of a packet + * | Reserved | REQ_TYPE | Resv | address | Reserved | + * | 127:108 | 107:104 | 103:96 | 95:32 | 31:0 | + */ + .m_axis_req_tvalid ( axis_wreq_tvalid ), // o, 1 + .m_axis_req_tlast ( axis_wreq_tlast ), // o, 1 + .m_axis_req_tdata ( axis_wreq_tdata ), // o, `DMA_DATA_W + .m_axis_req_tuser ( axis_wreq_tuser ), // o, `AXIS_TUSER_W ;The field contents are different from dma_*_head interface + .m_axis_req_tkeep ( axis_wreq_tkeep ), // o, `DMA_KEEP_W + .m_axis_req_tready ( axis_wreq_tready ) // i, 1 + /* ------- Master AXIS Interface(Connect to PCIe or converter){end} ------- */ + +`ifdef PCIEI_APB_DBG + /* -------APB reated signal{begin}------- */ + ,.dbg_signal ( dbg_signal_wreq_arb ) // o, `WREQ_ARB_SIGNAL_W + /* -------APB reated signal{end}------- */ +`endif + +`ifdef SIMULATION + /* ------- Debug interface {begin}------- */ + /* | reserved | idx | end | out | + * | 255:CHNL_NUM_LOG+2 | CHNL_NUM_LOG+2-1:2 | 1 | 0 | + */ + ,.debug ( debug_wr ) + /* ------- Debug interface {end}------- */ +`endif +); + +req_arbiter #( + .CHNL_NUM_LOG ( 1 ), + .CHANNEL_NUM ( 2 ) // number of slave signals to arbit + +) req_arbiter ( + .dma_clk ( dma_clk ), // i, 1 + .rst_n ( rst_n ), // i, 1 + + /* -------Slave AXIS Interface(Connect to Module){begin}------- */ + /* AXI-Stream request tuser, only valid in first beat of a packet + * | Reserved | REQ_TYPE | Tag | address | Reserved | DW length | first BE | last BE | + * | 127:108 | 107:104 | 103:96 | 95:32 | 31:19 | 18:8 | 7:4 | 3:0 | + * or + * AXI-Stream interrupt request tuser, only valid in first beat of a packet + * | Reserved | REQ_TYPE | Resv | address | Reserved | + * | 127:108 | 107:104 | 103:96 | 95:32 | 31:0 | + */ + .s_axis_req_tvalid ( {axis_wreq_tvalid, axis_rreq_tvalid} ), // i, 1 * CHANNEL_NUM + .s_axis_req_tlast ( {axis_wreq_tlast , axis_rreq_tlast } ), // i, 1 * CHANNEL_NUM + .s_axis_req_tdata ( {axis_wreq_tdata , axis_rreq_tdata } ), // i, `DMA_DATA_W * CHANNEL_NUM + .s_axis_req_tuser ( {axis_wreq_tuser , axis_rreq_tuser } ), // i, `AXIS_TUSER_W * CHANNEL_NUM ;The field contents are different from dma_*_tuser interface + .s_axis_req_tkeep ( {axis_wreq_tkeep , axis_rreq_tkeep } ), // i, `DMA_KEEP_W * CHANNEL_NUM + .s_axis_req_tready ( {axis_wreq_tready, axis_rreq_tready} ), // o, 1 * CHANNEL_NUM + /* -------Slave AXIS Interface(Connect to Module){end}------- */ + + /* ------- Master AXIS Interface(Connect to PCIe or converter){begin} ------- */ + /* AXI-Stream request tuser, only valid in first beat of a packet + * | Reserved | REQ_TYPE | Tag | address | Reserved | DW length | first BE | last BE | + * | 127:108 | 107:104 | 103:96 | 95:32 | 31:19 | 18:8 | 7:4 | 3:0 | + * or + * AXI-Stream interrupt request tuser, only valid in first beat of a packet + * | Reserved | REQ_TYPE | Resv | address | Reserved | + * | 127:108 | 107:104 | 103:96 | 95:32 | 31:0 | + */ + .m_axis_req_tvalid ( axis_req_tvalid ), // o, 1 + .m_axis_req_tlast ( axis_req_tlast ), // o, 1 + .m_axis_req_tdata ( axis_req_tdata ), // o, `DMA_DATA_W + .m_axis_req_tuser ( axis_req_tuser ), // o, `AXIS_TUSER_W ;The field contents are different from dma_*_head interface + .m_axis_req_tkeep ( axis_req_tkeep ), // o, `DMA_KEEP_W + .m_axis_req_tready ( axis_req_tready ) // i, 1 + /* ------- Master AXIS Interface(Connect to PCIe or converter){end} ------- */ + +`ifdef PCIEI_APB_DBG + /* -------APB reated signal{begin}------- */ + ,.dbg_signal ( dbg_signal_req_arb ) // o, `REQ_ARB_SIGNAL_W + /* -------APB reated signal{end}------- */ +`endif + +`ifdef SIMULATION + /* ------- Debug interface {begin}------- */ + /* | reserved | idx | end | out | + * | 255:CHNL_NUM_LOG+2 | CHNL_NUM_LOG+2-1:2 | 1 | 0 | + */ + ,.debug (debug_top) + /* ------- Debug interface {end}------- */ +`endif +); + + +req_converter #( + +) req_converter ( + .pcie_clk ( pcie_clk ), // i, 1 + .pcie_rst_n ( pcie_rst_n ), // i, 1 + .dma_clk ( dma_clk ), // i, 1 + .rst_n ( rst_n ), // i, 1 + + + /* ------- Interface with Request Arbiter{begin} ------- */ + /* AXI-Stream request tuser, only valid in first beat of a packet + * | Reserved | REQ_TYPE | Tag | address | Reserved | DW length | first BE | last BE | + * | 127:108 | 107:104 | 103:96 | 95:32 | 31:19 | 18:8 | 7:4 | 3:0 | + * or + * AXI-Stream interrupt request tuser, only valid in first beat of a packet + * | Reserved | REQ_TYPE | Resv | address | Reserved | + * | 127:108 | 107:104 | 103:96 | 95:32 | 31:0 | + */ + .axis_req_tvalid ( axis_req_tvalid ), // i, 1 + .axis_req_tlast ( axis_req_tlast ), // i, 1 + .axis_req_tdata ( axis_req_tdata ), // i, `DMA_DATA_W + .axis_req_tuser ( axis_req_tuser ), // i, `AXIS_TUSER_W + .axis_req_tkeep ( axis_req_tkeep ), // i, `DMA_KEEP_W + .axis_req_tready ( axis_req_tready ), // o, 1 + /* ------- Interface with Request Arbiter{end} ------- */ + + /* -------dma --> pcie interface{begin}------- */ + // Requester request + /* RQ tuser + * | 59:28 | 27:24 | 23:16 | 15 | 14:13 | 12 | 11 | 10:8 | 7:4 | 3:0 | + * | parity | seq_num | tph_st_tag | tph_indirect_tag_en | tph_type | tph_present | discontinue | addr_offset | last_be | first_be | + * | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | | + */ + .s_axis_rq_tvalid ( dma_axis_rq_tvalid ), // o, 1 + .s_axis_rq_tlast ( dma_axis_rq_tlast ), // o, 1 + .s_axis_rq_tdata ( dma_axis_rq_tdata ), // o, `DMA_DATA_W + .s_axis_rq_tuser ( dma_axis_rq_tuser ), // o, 60 + .s_axis_rq_tkeep ( dma_axis_rq_tkeep ), // o, `DMA_KEEP_W + .s_axis_rq_tready ( dma_axis_rq_tready ), // i, 1 + /* -------dma --> pcie interface{end}------- */ + + .req_id_in ( req_id ), // i, 16 + + /* -------Interrupt Interface Signals{begin}------- */ + .cfg_interrupt_msix_enable ( cfg_interrupt_msix_enable ), // i, 2 + .cfg_interrupt_msix_mask ( cfg_interrupt_msix_mask ), // i, 2 + .cfg_interrupt_msix_data ( cfg_interrupt_msix_data ), // o, 32 + .cfg_interrupt_msix_address ( cfg_interrupt_msix_address ), // o, 64 + .cfg_interrupt_msix_int ( cfg_interrupt_msix_int ), // o, 1 + .cfg_interrupt_msix_sent ( cfg_interrupt_msix_sent ), // i, 1 + .cfg_interrupt_msix_fail ( cfg_interrupt_msix_fail ), // i, 1 + .cfg_interrupt_msi_function_number ( cfg_interrupt_msi_function_number ) // o, 3 + /* -------Interrupt Interface Signals{end}------- */ + +`ifdef PCIEI_APB_DBG + /* -------APB reated signal{begin}------- */ + ,.rw_data ( rw_data_int ) // i, `SRAM_RW_DATA_W + ,.dbg_sel ( dbg_sel_req_convert ) // i, 32 + ,.dbg_bus ( dbg_bus_req_convert ) // o, 32 + /* -------APB reated signal{end}------- */ +`endif +); + +rsp_converter #( + +) rsp_converter ( + .dma_clk ( pcie_clk ), // i, 1 + .rst_n ( rst_n ), // i, 1 + + /* ------- pcie --> dma interface{begin}------- */ + // Requester Completion + /* RC tuser + * | 74:43 | 42 | 41:38 | 37:34 | 33 | 32 | 31:0 | + * | parity | discontinue | is_eof_1 | is_eof_0 | is_sof_1 | is_sof_0 | byte_en | + * | ignore | ignore | ignore | ignore | ignore | ignore | | + */ + .m_axis_rc_tvalid ( m_axis_rc_tvalid ), // i, 1 + .m_axis_rc_tlast ( m_axis_rc_tlast ), // i, 1 + .m_axis_rc_tdata ( m_axis_rc_tdata ), // i, `DMA_DATA_W + .m_axis_rc_tuser ( m_axis_rc_tuser ), // i, 75 + .m_axis_rc_tkeep ( m_axis_rc_tkeep ), // i, `DMA_KEEP_W + .m_axis_rc_tready ( m_axis_rc_tready ), // o, 1 + /* ------- pcie --> dma interface{end}------- */ + + + /* ------- Interface with dma read module{begin}------- */ + /* AXI-Stream read response tuser, interact with read response distributor. + * Only valid in first beat of a packet + * | Reserved | REQ CPL | Tag | address | Reserved | DW length | first BE | last BE | + * | 119:105 | 104 | 103:96 | 95:32 | 31:19 | 18:8 | 7:4 | 3:0 | + */ + .axis_rd_rsp_tvalid ( pcie_axis_rrsp_tvalid ), // o, 1 + .axis_rd_rsp_tlast ( pcie_axis_rrsp_tlast ), // o, 1 + .axis_rd_rsp_tdata ( pcie_axis_rrsp_tdata ), // o, `DMA_DATA_W + .axis_rd_rsp_tuser ( pcie_axis_rrsp_tuser ), // o, `AXIS_TUSER_W + .axis_rd_rsp_tkeep ( pcie_axis_rrsp_tkeep ), // o, `DMA_KEEP_W + .axis_rd_rsp_tready ( pcie_axis_rrsp_tready ) // i, 1 + /* ------- Interface with dma read module{end}------- */ + +`ifdef PCIEI_APB_DBG + /* -------APB reated signal{begin}------- */ + ,.dbg_sel ( dbg_sel_rsp_convert ) // i, 32 + ,.dbg_bus ( dbg_bus_rsp_convert ) // o, 32 + /* -------APB reated signal{end}------- */ +`endif +); + + +rq_async_fifos #( + +) rq_async_fifos ( + .dma_clk ( dma_clk ), + .pcie_clk ( pcie_clk ), + .dma_rst_n ( rst_n ), + .pcie_rst_n ( pcie_rst_n ), + + /* -------rdma write request interface{begin}------- */ + + /* -------dma --> pcie interface, dma part{begin}------- */ + // Requester request + /* RQ tuser + * | 59:28 | 27:24 | 23:16 | 15 | 14:13 | 12 | 11 | 10:8 | 7:4 | 3:0 | + * | parity | seq_num | tph_st_tag | tph_indirect_tag_en | tph_type | tph_present | discontinue | addr_offset | last_be | first_be | + * | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | | + */ + .dma_axis_rq_tvalid ( dma_axis_rq_tvalid ), // i, 1 + .dma_axis_rq_tlast ( dma_axis_rq_tlast ), // i, 1 + .dma_axis_rq_tdata ( dma_axis_rq_tdata ), // i, `DMA_DATA_W + .dma_axis_rq_tuser ( dma_axis_rq_tuser ), // i, 60 + .dma_axis_rq_tkeep ( dma_axis_rq_tkeep ), // i, `DMA_KEEP_W + .dma_axis_rq_tready ( dma_axis_rq_tready ), // o, 1 + /* -------dma --> pcie interface, dma part{end}------- */ + + /* -------dma --> pcie interface, pcie part{begin}------- */ + // Requester request + /* RQ tuser + * | 59:28 | 27:24 | 23:16 | 15 | 14:13 | 12 | 11 | 10:8 | 7:4 | 3:0 | + * | parity | seq_num | tph_st_tag | tph_indirect_tag_en | tph_type | tph_present | discontinue | addr_offset | last_be | first_be | + * | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | | + */ + .st_pcie_axis_rq_tvalid ( s_axis_rq_tvalid ), // o, 1 + .st_pcie_axis_rq_tlast ( s_axis_rq_tlast ), // o, 1 + .st_pcie_axis_rq_tdata ( s_axis_rq_tdata ), // o, `DMA_DATA_W + .st_pcie_axis_rq_tuser ( s_axis_rq_tuser ), // o, 60 + .st_pcie_axis_rq_tkeep ( s_axis_rq_tkeep ), // o, `DMA_KEEP_W + .st_pcie_axis_rq_tready ( s_axis_rq_tready ) // i, 1 + /* -------dma --> pcie interface, pcie part{begin}------- */ + +`ifdef PCIEI_APB_DBG + /* -------APB reated signal{begin}------- */ + ,.rw_data ( rw_data_rq ) // i, `SRAM_RW_DATA_W + ,.dbg_signal ( dbg_signal_rq_async ) // o, `RQ_ASYNC_SIGNAL_W + /* -------APB reated signal{end}------- */ +`endif +); + + +// rc_async_fifos #( + +// ) rc_async_fifos ( +// .dma_clk ( dma_clk ), +// .pcie_clk ( pcie_clk ), +// .dma_rst_n ( rst_n ), +// .pcie_rst_n ( pcie_rst_n ), + +// /* ------- pcie --> dma interface, pcie part{begin}------- */ +// // Requester Completion +// /* RC tuser +// * | 74:43 | 42 | 41:38 | 37:34 | 33 | 32 | 31:0 | +// * | parity | discontinue | is_eof_1 | is_eof_0 | is_sof_1 | is_sof_0 | byte_en | +// * | ignore | ignore | ignore | ignore | ignore | ignore | | +// */ +// .pcie_axis_rc_tvalid ( m_axis_rc_tvalid ), // i, 1 +// .pcie_axis_rc_tlast ( m_axis_rc_tlast ), // i, 1 +// .pcie_axis_rc_tdata ( m_axis_rc_tdata ), // i, `DMA_DATA_W +// .pcie_axis_rc_tuser ( m_axis_rc_tuser ), // i, 75 +// .pcie_axis_rc_tkeep ( m_axis_rc_tkeep ), // i, `DMA_KEEP_W +// .pcie_axis_rc_tready ( m_axis_rc_tready ), // o, 1 +// /* ------- pcie --> dma interface, pcie part{end}------- */ + +// /* ------- pcie --> dma interface, dma part{begin}------- */ +// // Requester Completion +// /* RC tuser +// * | 74:43 | 42 | 41:38 | 37:34 | 33 | 32 | 31:0 | +// * | parity | discontinue | is_eof_1 | is_eof_0 | is_sof_1 | is_sof_0 | byte_en | +// * | ignore | ignore | ignore | ignore | ignore | ignore | | +// */ +// .dma_axis_rc_tvalid ( dma_axis_rc_tvalid ), // o, 1 +// .dma_axis_rc_tlast ( dma_axis_rc_tlast ), // o, 1 +// .dma_axis_rc_tdata ( dma_axis_rc_tdata ), // o, `DMA_DATA_W +// .dma_axis_rc_tuser ( dma_axis_rc_tuser ), // o, 75 +// .dma_axis_rc_tkeep ( dma_axis_rc_tkeep ), // o, `DMA_KEEP_W +// .dma_axis_rc_tready ( dma_axis_rc_tready ) // i, 1 +// /* ------- pcie --> dma interface, dma part{end}------- */ + +// `ifdef PCIEI_APB_DBG +// /* -------APB reated signal{begin}------- */ +// ,.rw_data ( rw_data_rc ) // i, `SRAM_RW_DATA_W +// ,.dbg_signal ( dbg_signal_rc_async ) // o, `RC_ASYNC_SIGNAL_W +// /* -------APB reated signal{end}------- */ +// `endif +// ); + +rrsp_async_fifos #( + +) rrsp_async_fifos ( + .dma_clk ( dma_clk ), + .pcie_clk ( pcie_clk ), + .dma_rst_n ( rst_n ), + .pcie_rst_n ( pcie_rst_n ), + + /* ------- pcie clock domain{begin}------- */ + /* AXI-Stream read response tuser, interact with read response distributor. + * Only valid in first beat of a packet + * | Reserved | REQ CPL | Tag | address | Reserved | DW length | first BE | last BE | + * | 119:105 | 104 | 103:96 | 95:32 | 31:19 | 18:8 | 7:4 | 3:0 | + */ + .pcie_axis_rrsp_tvalid ( pcie_axis_rrsp_tvalid ), // i, 1 + .pcie_axis_rrsp_tlast ( pcie_axis_rrsp_tlast ), // i, 1 + .pcie_axis_rrsp_tdata ( pcie_axis_rrsp_tdata ), // i, `DMA_DATA_W + .pcie_axis_rrsp_tuser ( pcie_axis_rrsp_tuser ), // i, `AXIS_TUSER_W + .pcie_axis_rrsp_tkeep ( pcie_axis_rrsp_tkeep ), // i, `DMA_KEEP_W + .pcie_axis_rrsp_tready ( pcie_axis_rrsp_tready ), // o, 1 + /* ------- pcie clock domain{end}------- */ + + /* ------- dma clock domain{begin}------- */ + /* AXI-Stream read response tuser, interact with read response distributor. + * Only valid in first beat of a packet + * | Reserved | REQ CPL | Tag | address | Reserved | DW length | first BE | last BE | + * | 119:105 | 104 | 103:96 | 95:32 | 31:19 | 18:8 | 7:4 | 3:0 | + */ + .dma_axis_rrsp_tvalid ( dma_axis_rrsp_tvalid ), // o, 1 + .dma_axis_rrsp_tlast ( dma_axis_rrsp_tlast ), // o, 1 + .dma_axis_rrsp_tdata ( dma_axis_rrsp_tdata ), // o, `DMA_DATA_W + .dma_axis_rrsp_tuser ( dma_axis_rrsp_tuser ), // o, `AXIS_TUSER_W + .dma_axis_rrsp_tkeep ( dma_axis_rrsp_tkeep ), // o, `DMA_KEEP_W + .dma_axis_rrsp_tready ( dma_axis_rrsp_tready ) // i, 1 + /* ------- dma clock domain{end}------- */ + +`ifdef PCIEI_APB_DBG + /* -------APB reated signal{begin}------- */ + ,.rw_data ( rw_data_rc ) // i, `SRAM_RW_DATA_W + ,.dbg_signal ( dbg_signal_rrsp_async ) // o, `RRSP_ASYNC_SIGNAL_W + /* -------APB reated signal{end}------- */ +`endif +); + +endmodule diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/DMA/DMA_Read/dma_demux.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/DMA/DMA_Read/dma_demux.v new file mode 100644 index 0000000000000000000000000000000000000000..d4dda85623ea181907e82c871a056e8b35eddd34 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/DMA/DMA_Read/dma_demux.v @@ -0,0 +1,347 @@ +`timescale 1ns / 100ps +//************************************************************************* +// > File : dma_demux.v +// > Author : Kangning +// > Date : 2022-06-29 +// > Note : demux module for pio, used for read & write request. +// > V1.1 2022-06-08: Now, It only support 2 or 3 output channels. +// > V1.2 2022-06-29: Suppports up to 16 channels +//************************************************************************* + +module dma_demux #( + parameter CHANNEL_NUM = 2 // number of channels for output +) ( + input wire clk , // i, 1 + input wire rst_n, // i, 1 + + input wire nxt_demux_vld, // i, 1 + input wire [7:0] nxt_demux_sel, // i, 8 + + /* --------PIO Write Request interface{begin}-------- */ + /* head + * | 130:128 | 127:96 | 95:0 | + * | bar_id | addr | cc_head | + */ + input wire s_axis_req_valid, // i, 1 + input wire s_axis_req_last , // i, 1 + input wire [`DMA_HEAD_W-1:0] s_axis_req_head , // i, `DMA_HEAD_W + input wire [`DMA_DATA_W-1:0] s_axis_req_data , // i, `DMA_DATA_W + output wire s_axis_req_ready, // o, 1 + + output wire [CHANNEL_NUM * 1 -1:0] m_axis_req_valid, // o, CHANNEL_NUM * 1 + output wire [CHANNEL_NUM * 1 -1:0] m_axis_req_last , // o, CHANNEL_NUM * 1 + output wire [CHANNEL_NUM * `DMA_HEAD_W-1:0] m_axis_req_head , // o, CHANNEL_NUM * `DMA_HEAD_W + output wire [CHANNEL_NUM * `DMA_DATA_W-1:0] m_axis_req_data , // o, CHANNEL_NUM * `DMA_DATA_W + input wire [CHANNEL_NUM * 1 -1:0] m_axis_req_ready // i, CHANNEL_NUM * 1 + /* --------PIO Write Request interface{end}-------- */ + +`ifdef PCIEI_APB_DBG + /* -------APB reated signal{begin}------- */ + ,output wire [`DMA_DEMUX_SIGNAL_W-1:0] dbg_signal // o, `DMA_DEMUX_SIGNAL_W + /* -------APB reated signal{end}------- */ +`endif +); + +reg [7:0] sel; + +/* -------State relevant in FSM{begin}------- */ +localparam IDLE = 2'b01, + TRANS = 2'b10; + +reg [1:0] cur_state; +reg [1:0] nxt_state; + +wire is_idle, is_trans; +/* -------State relevant in FSM{end}------- */ + +//--------------------------------------------------------------------------------------------------------------------------- + +`ifdef PCIEI_APB_DBG +/* -------APB reated signal{begin}------- */ +assign dbg_signal = { // 14 + sel, // 8 + cur_state, nxt_state, // 4 + is_idle, is_trans // 2 +}; +/* -------APB reated signal{end}------- */ +`endif + +/* -------{Read Response Distributor FSM}begin------- */ +/******************** Stage 1: State Register **********************/ + +assign is_idle = (cur_state == IDLE ); +assign is_trans = (cur_state == TRANS); + +always @(posedge clk, negedge rst_n) begin + if(~rst_n) + cur_state <= `TD IDLE; + else + cur_state <= `TD nxt_state; +end + +always @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + sel <= `TD 8'd0; + end + else if ((is_idle & nxt_demux_vld) || + (is_trans & s_axis_req_last & s_axis_req_valid & s_axis_req_ready & nxt_demux_vld)) begin + sel <= `TD nxt_demux_sel; + end +end + +/* -------Generate block{begin}------- */ +/* This is used for different Channel Numbers, the default Number is 4 + */ +generate +if (CHANNEL_NUM == 16) begin:CHNL_DEMUX_16 + +assign s_axis_req_ready = ((sel == 0) & is_trans & m_axis_req_ready[0]) | + ((sel == 1) & is_trans & m_axis_req_ready[1]) | + ((sel == 2) & is_trans & m_axis_req_ready[2]) | + ((sel == 3) & is_trans & m_axis_req_ready[3]) | + ((sel == 4) & is_trans & m_axis_req_ready[4]) | + ((sel == 5) & is_trans & m_axis_req_ready[5]) | + ((sel == 6) & is_trans & m_axis_req_ready[6]) | + ((sel == 7) & is_trans & m_axis_req_ready[7]) | + ((sel == 8) & is_trans & m_axis_req_ready[8]) | + ((sel == 9) & is_trans & m_axis_req_ready[9]) | + ((sel == 10) & is_trans & m_axis_req_ready[10])| + ((sel == 11) & is_trans & m_axis_req_ready[11])| + ((sel == 12) & is_trans & m_axis_req_ready[12])| + ((sel == 13) & is_trans & m_axis_req_ready[13])| + ((sel == 14) & is_trans & m_axis_req_ready[14])| + ((sel == 15) & is_trans & m_axis_req_ready[15]); + +end // CHNL_DEMUX_16 +else if (CHANNEL_NUM == 15) begin:CHNL_DEMUX_15 + +assign s_axis_req_ready = ((sel == 0) & is_trans & m_axis_req_ready[0]) | + ((sel == 1) & is_trans & m_axis_req_ready[1]) | + ((sel == 2) & is_trans & m_axis_req_ready[2]) | + ((sel == 3) & is_trans & m_axis_req_ready[3]) | + ((sel == 4) & is_trans & m_axis_req_ready[4]) | + ((sel == 5) & is_trans & m_axis_req_ready[5]) | + ((sel == 6) & is_trans & m_axis_req_ready[6]) | + ((sel == 7) & is_trans & m_axis_req_ready[7]) | + ((sel == 8) & is_trans & m_axis_req_ready[8]) | + ((sel == 9) & is_trans & m_axis_req_ready[9]) | + ((sel == 10) & is_trans & m_axis_req_ready[10])| + ((sel == 11) & is_trans & m_axis_req_ready[11])| + ((sel == 12) & is_trans & m_axis_req_ready[12])| + ((sel == 13) & is_trans & m_axis_req_ready[13])| + ((sel == 14) & is_trans & m_axis_req_ready[14]); + +end // CHNL_DEMUX_15 +else if (CHANNEL_NUM == 14) begin:CHNL_DEMUX_14 + +assign s_axis_req_ready = ((sel == 0) & is_trans & m_axis_req_ready[0]) | + ((sel == 1) & is_trans & m_axis_req_ready[1]) | + ((sel == 2) & is_trans & m_axis_req_ready[2]) | + ((sel == 3) & is_trans & m_axis_req_ready[3]) | + ((sel == 4) & is_trans & m_axis_req_ready[4]) | + ((sel == 5) & is_trans & m_axis_req_ready[5]) | + ((sel == 6) & is_trans & m_axis_req_ready[6]) | + ((sel == 7) & is_trans & m_axis_req_ready[7]) | + ((sel == 8) & is_trans & m_axis_req_ready[8]) | + ((sel == 9) & is_trans & m_axis_req_ready[9]) | + ((sel == 10) & is_trans & m_axis_req_ready[10])| + ((sel == 11) & is_trans & m_axis_req_ready[11])| + ((sel == 12) & is_trans & m_axis_req_ready[12])| + ((sel == 13) & is_trans & m_axis_req_ready[13]); + +end // CHNL_DEMUX_14 +else if (CHANNEL_NUM == 13) begin:CHNL_DEMUX_13 + +assign s_axis_req_ready = ((sel == 0) & is_trans & m_axis_req_ready[0]) | + ((sel == 1) & is_trans & m_axis_req_ready[1]) | + ((sel == 2) & is_trans & m_axis_req_ready[2]) | + ((sel == 3) & is_trans & m_axis_req_ready[3]) | + ((sel == 4) & is_trans & m_axis_req_ready[4]) | + ((sel == 5) & is_trans & m_axis_req_ready[5]) | + ((sel == 6) & is_trans & m_axis_req_ready[6]) | + ((sel == 7) & is_trans & m_axis_req_ready[7]) | + ((sel == 8) & is_trans & m_axis_req_ready[8]) | + ((sel == 9) & is_trans & m_axis_req_ready[9]) | + ((sel == 10) & is_trans & m_axis_req_ready[10])| + ((sel == 11) & is_trans & m_axis_req_ready[11])| + ((sel == 12) & is_trans & m_axis_req_ready[12]); + +end // CHNL_DEMUX_13 +else if (CHANNEL_NUM == 12) begin:CHNL_DEMUX_12 + +assign s_axis_req_ready = ((sel == 0) & is_trans & m_axis_req_ready[0]) | + ((sel == 1) & is_trans & m_axis_req_ready[1]) | + ((sel == 2) & is_trans & m_axis_req_ready[2]) | + ((sel == 3) & is_trans & m_axis_req_ready[3]) | + ((sel == 4) & is_trans & m_axis_req_ready[4]) | + ((sel == 5) & is_trans & m_axis_req_ready[5]) | + ((sel == 6) & is_trans & m_axis_req_ready[6]) | + ((sel == 7) & is_trans & m_axis_req_ready[7]) | + ((sel == 8) & is_trans & m_axis_req_ready[8]) | + ((sel == 9) & is_trans & m_axis_req_ready[9]) | + ((sel == 10) & is_trans & m_axis_req_ready[10])| + ((sel == 11) & is_trans & m_axis_req_ready[11]); + +end // CHNL_DEMUX_12 +else if (CHANNEL_NUM == 11) begin:CHNL_DEMUX_11 + +assign s_axis_req_ready = ((sel == 0) & is_trans & m_axis_req_ready[0]) | + ((sel == 1) & is_trans & m_axis_req_ready[1]) | + ((sel == 2) & is_trans & m_axis_req_ready[2]) | + ((sel == 3) & is_trans & m_axis_req_ready[3]) | + ((sel == 4) & is_trans & m_axis_req_ready[4]) | + ((sel == 5) & is_trans & m_axis_req_ready[5]) | + ((sel == 6) & is_trans & m_axis_req_ready[6]) | + ((sel == 7) & is_trans & m_axis_req_ready[7]) | + ((sel == 8) & is_trans & m_axis_req_ready[8]) | + ((sel == 9) & is_trans & m_axis_req_ready[9]) | + ((sel == 10) & is_trans & m_axis_req_ready[10]); + +end // CHNL_DEMUX_11 +else if (CHANNEL_NUM == 10) begin:CHNL_DEMUX_10 + +assign s_axis_req_ready = ((sel == 0) & is_trans & m_axis_req_ready[0]) | + ((sel == 1) & is_trans & m_axis_req_ready[1]) | + ((sel == 2) & is_trans & m_axis_req_ready[2]) | + ((sel == 3) & is_trans & m_axis_req_ready[3]) | + ((sel == 4) & is_trans & m_axis_req_ready[4]) | + ((sel == 5) & is_trans & m_axis_req_ready[5]) | + ((sel == 6) & is_trans & m_axis_req_ready[6]) | + ((sel == 7) & is_trans & m_axis_req_ready[7]) | + ((sel == 8) & is_trans & m_axis_req_ready[8]) | + ((sel == 9) & is_trans & m_axis_req_ready[9]); + +end // CHNL_DEMUX_10 +else if (CHANNEL_NUM == 9) begin:CHNL_DEMUX_9 + +assign s_axis_req_ready = ((sel == 0) & is_trans & m_axis_req_ready[0]) | + ((sel == 1) & is_trans & m_axis_req_ready[1]) | + ((sel == 2) & is_trans & m_axis_req_ready[2]) | + ((sel == 3) & is_trans & m_axis_req_ready[3]) | + ((sel == 4) & is_trans & m_axis_req_ready[4]) | + ((sel == 5) & is_trans & m_axis_req_ready[5]) | + ((sel == 6) & is_trans & m_axis_req_ready[6]) | + ((sel == 7) & is_trans & m_axis_req_ready[7]) | + ((sel == 8) & is_trans & m_axis_req_ready[8]); + +end // CHNL_DEMUX_9 +else if (CHANNEL_NUM == 8) begin:CHNL_DEMUX_8 + +assign s_axis_req_ready = ((sel == 0) & is_trans & m_axis_req_ready[0]) | + ((sel == 1) & is_trans & m_axis_req_ready[1]) | + ((sel == 2) & is_trans & m_axis_req_ready[2]) | + ((sel == 3) & is_trans & m_axis_req_ready[3]) | + ((sel == 4) & is_trans & m_axis_req_ready[4]) | + ((sel == 5) & is_trans & m_axis_req_ready[5]) | + ((sel == 6) & is_trans & m_axis_req_ready[6]) | + ((sel == 7) & is_trans & m_axis_req_ready[7]); + +end // CHNL_DEMUX_8 +else if (CHANNEL_NUM == 7) begin:CHNL_DEMUX_7 + +assign s_axis_req_ready = ((sel == 0) & is_trans & m_axis_req_ready[0]) | + ((sel == 1) & is_trans & m_axis_req_ready[1]) | + ((sel == 2) & is_trans & m_axis_req_ready[2]) | + ((sel == 3) & is_trans & m_axis_req_ready[3]) | + ((sel == 4) & is_trans & m_axis_req_ready[4]) | + ((sel == 5) & is_trans & m_axis_req_ready[5]) | + ((sel == 6) & is_trans & m_axis_req_ready[6]); + +end // CHNL_DEMUX_7 +else if (CHANNEL_NUM == 6) begin:CHNL_DEMUX_6 + +assign s_axis_req_ready = ((sel == 0) & is_trans & m_axis_req_ready[0]) | + ((sel == 1) & is_trans & m_axis_req_ready[1]) | + ((sel == 2) & is_trans & m_axis_req_ready[2]) | + ((sel == 3) & is_trans & m_axis_req_ready[3]) | + ((sel == 4) & is_trans & m_axis_req_ready[4]) | + ((sel == 5) & is_trans & m_axis_req_ready[5]); + +end // CHNL_DEMUX_6 +else if (CHANNEL_NUM == 5) begin:CHNL_DEMUX_5 + +assign s_axis_req_ready = ((sel == 0) & is_trans & m_axis_req_ready[0]) | + ((sel == 1) & is_trans & m_axis_req_ready[1]) | + ((sel == 2) & is_trans & m_axis_req_ready[2]) | + ((sel == 3) & is_trans & m_axis_req_ready[3]) | + ((sel == 4) & is_trans & m_axis_req_ready[4]); + +end // CHNL_DEMUX_5 +else if (CHANNEL_NUM == 4) begin:CHNL_DEMUX_4 + +assign s_axis_req_ready = ((sel == 0) & is_trans & m_axis_req_ready[0]) | + ((sel == 1) & is_trans & m_axis_req_ready[1]) | + ((sel == 2) & is_trans & m_axis_req_ready[2]) | + ((sel == 3) & is_trans & m_axis_req_ready[3]); + +end // CHNL_DEMUX_4 +else if (CHANNEL_NUM == 3) begin:CHNL_DEMUX_3 + +assign s_axis_req_ready = ((sel == 0) & is_trans & m_axis_req_ready[0]) | + ((sel == 1) & is_trans & m_axis_req_ready[1]) | + ((sel == 2) & is_trans & m_axis_req_ready[2]); + +end // CHNL_DEMUX_3 +else if (CHANNEL_NUM == 2) begin:CHNL_DEMUX_2 + +assign s_axis_req_ready = ((sel == 0) & is_trans & m_axis_req_ready[0]) | + ((sel == 1) & is_trans & m_axis_req_ready[1]); + +end // CHNL_DEMUX_2 +endgenerate +/* + This is used for different Channel Numbers, the default Number is 4 */ +/* -------Generate block{end}------- */ + +/******************** Stage 2: State Transition **********************/ + +always @(*) begin + case(cur_state) + IDLE: begin + if (nxt_demux_vld) begin + nxt_state = TRANS; + end + else begin + nxt_state = IDLE; + end + end + TRANS: begin + if (s_axis_req_last & s_axis_req_valid & s_axis_req_ready & nxt_demux_vld) begin + nxt_state = TRANS; + end + else if (s_axis_req_last & s_axis_req_valid & s_axis_req_ready) begin + nxt_state = IDLE; + end + else begin + nxt_state = TRANS; + end + end + default: begin + nxt_state = IDLE; + end + endcase +end +/******************** Stage 3: Output **********************/ + +/* -------Generate block{begin}------- */ +/* This is used for different Channel Numbers, the default Number is 4 + */ +genvar i; +generate +for (i = 0; i < CHANNEL_NUM; i = i + 1) begin:CHNL_DEMUX_ASSIGN + +assign m_axis_req_valid[(i+1)*1 -1:i*1 ] = ((i == sel) & is_trans) ? s_axis_req_valid : 0; +assign m_axis_req_last [(i+1)*1 -1:i*1 ] = ((i == sel) & is_trans) ? s_axis_req_last : 0; +assign m_axis_req_data [(i+1)*`DMA_DATA_W -1:i*`DMA_DATA_W] = ((i == sel) & is_trans) ? s_axis_req_data : 0; +assign m_axis_req_head [(i+1)*`DMA_HEAD_W -1:i*`DMA_HEAD_W] = ((i == sel) & is_trans) ? s_axis_req_head : 0; + +end +endgenerate +/* + This is used for different Channel Numbers, the default Number is 4 */ +/* -------Generate block{end}------- */ + + +/* -------{Read Response Distributor FSM}end------- */ + +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/DMA/DMA_Read/np_tag_mgmt.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/DMA/DMA_Read/np_tag_mgmt.v new file mode 100644 index 0000000000000000000000000000000000000000..4fd3fbf7fc05cae392e0b9dfd435073e3b521e43 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/DMA/DMA_Read/np_tag_mgmt.v @@ -0,0 +1,337 @@ +`timescale 1ns / 100ps +//************************************************************************* +// > File Name: np_tag_mgmt.v +// > Author : Kangning +// > Date : 2022-06-29 +// > Note : np_tag_mgmt, used for tag allocation of non-post request. +// > V1.1 2022-06-29 : Add tag_chnl field to store +// > V2.0 2022-11-03 : Add support for multi-channel tag fifo +//************************************************************************* + +module np_tag_mgmt #( + +) ( + input wire dma_clk , // i, 1 + input wire rst_n , // i, 1 + output reg init_done, // o, 1; assert at the end of initial state + + /* -------tag request{begin}------- */ + input wire tag_rreq_ready, // i, 1 + input wire tag_rreq_last , // i, 1 ; Indicate the last sub-req for rd req + input wire [`DW_LEN_WIDTH-1:0] tag_rreq_sz , // i, `DW_LEN_WIDTH ; Request size(in dw unit) of this tag + input wire [`TAG_MISC -1:0] tag_rreq_misc , // o, `TAG_MISC ; Including addr && dw empty info + input wire [8 -1:0] tag_rreq_chnl , // i, 8 ; channel number for this request + output wire [`TAG_NUM_LOG -1:0] tag_rreq_tag , // o, `TAG_NUM_LOG + output wire tag_rreq_valid, // o, 1 + /* -------tag request{end}------- */ + + /* -------tag release{begin}------- */ + // Note that only one channel is allowed to assert at the same time + input wire [`DMA_RD_CHNL_NUM * 1 - 1 : 0] tag_rrsp_ready, // i, 1 + output wire [`DMA_RD_CHNL_NUM * 1 - 1 : 0] tag_rrsp_last , // o, 1 + output wire [`DMA_RD_CHNL_NUM * `DW_LEN_WIDTH - 1 : 0] tag_rrsp_sz , // o, `DW_LEN_WIDTH + output wire [`DMA_RD_CHNL_NUM * `TAG_MISC - 1 : 0] tag_rrsp_misc , // o, `TAG_MISC ; Including addr && dw empty info + output wire [`DMA_RD_CHNL_NUM * `TAG_NUM_LOG - 1 : 0] tag_rrsp_tag , // o, `TAG_NUM_LOG + output wire [`DMA_RD_CHNL_NUM * 1 - 1 : 0] tag_rrsp_valid // o, 1 + /* -------tag release{end}------- */ + +`ifdef PCIEI_APB_DBG + /* -------APB reated signal{begin}------- */ + ,input wire [(`DMA_RD_CHNL_NUM+1)*`SRAM_RW_DATA_W-1:0] rw_data // i, (`DMA_RD_CHNL_NUM+1)*`SRAM_RW_DATA_W + ,output wire [`TAG_MGMT_SIGNAL_W-1:0] dbg_signal // o, `TAG_MGMT_SIGNAL_W + /* -------APB reated signal{end}------- */ +`endif + +`ifdef SIMULATION + /* | reserved | tag_num | chnl_num | valid | + * | 255:17 | 16:9 | 8:1 | 0 | + */ + ,output wire [255:0] debug + /* ------- Debug interface {end}------- */ +`endif +); + +/* --------Debug signal{begin}-------- */ +`ifdef SIMULATION + +wire [7:0] dbug_tag_num, dbug_tag_chnl; +wire dbug_tag_valid; + +`endif +/* --------Debug signal{end}-------- */ + +reg [`TAG_NUM_LOG-1:0] init_cnt; + +/* --------Free tag management{begin}-------- */ +wire free_tag_wen ; +wire [`TAG_NUM_LOG-1:0] free_tag_din ; +wire free_tag_full ; +wire free_tag_ren ; +wire [`TAG_NUM_LOG-1:0] free_tag_dout ; +wire free_tag_empty; +/* --------Free tag management{end}-------- */ + +/* --------Free tag management{begin}-------- */ +wire alloced_tag_wen [`DMA_RD_CHNL_NUM-1:0]; +wire [`TAG_NUM_LOG+`DW_LEN_WIDTH+1+`TAG_MISC-1:0] alloced_tag_din [`DMA_RD_CHNL_NUM-1:0]; +wire alloced_tag_full [`DMA_RD_CHNL_NUM-1:0]; +wire alloced_tag_ren [`DMA_RD_CHNL_NUM-1:0]; +wire [`TAG_NUM_LOG+`DW_LEN_WIDTH+1+`TAG_MISC-1:0] alloced_tag_dout [`DMA_RD_CHNL_NUM-1:0]; +wire alloced_tag_empty[`DMA_RD_CHNL_NUM-1:0]; +/* --------Free tag management{end}-------- */ + +/* --------Arbiter logic{begin}-------- */ +wire arb_tag_wen; +wire [`TAG_NUM_LOG-1:0] arb_tag_din; +/* --------Arbiter logic{end}-------- */ + +`ifdef PCIEI_APB_DBG +/* -------APB reated signal{begin}------- */ +wire [1:0] free_rtsel; +wire [1:0] free_wtsel; +wire [1:0] free_ptsel; +wire free_vg ; +wire free_vs ; +wire [`DMA_RD_CHNL_NUM*2-1:0] alloced_rtsel; +wire [`DMA_RD_CHNL_NUM*2-1:0] alloced_wtsel; +wire [`DMA_RD_CHNL_NUM*2-1:0] alloced_ptsel; +wire [`DMA_RD_CHNL_NUM*1-1:0] alloced_vg ; +wire [`DMA_RD_CHNL_NUM*1-1:0] alloced_vs ; +/* -------APB reated signal{end}------- */ +`endif + +//--------------------------------------------------------------------------------------------------------------------------- + +`ifdef PCIEI_APB_DBG +/* -------APB reated signal{begin}------- */ +assign { + free_rtsel, free_wtsel, free_ptsel, free_vg, free_vs, + alloced_rtsel, alloced_wtsel, alloced_ptsel, alloced_vg, alloced_vs} = rw_data; +assign dbg_signal = { // 605 + init_cnt, // 6 + free_tag_wen , free_tag_din , free_tag_full , free_tag_ren , free_tag_dout , free_tag_empty, // 16 + + alloced_tag_wen [0], alloced_tag_wen [1], alloced_tag_wen [2], alloced_tag_wen [3], + alloced_tag_wen [4], alloced_tag_wen [5], alloced_tag_wen [6], alloced_tag_wen [7], alloced_tag_wen [8], + alloced_tag_din [0], alloced_tag_din [1], alloced_tag_din [2], alloced_tag_din [3], + alloced_tag_din [4], alloced_tag_din [5], alloced_tag_din [6], alloced_tag_din [7], alloced_tag_din [8], + alloced_tag_full [0], alloced_tag_full [1], alloced_tag_full [2], alloced_tag_full [3], + alloced_tag_full [4], alloced_tag_full [5], alloced_tag_full [6], alloced_tag_full [7], alloced_tag_full [8], + alloced_tag_ren [0], alloced_tag_ren [1], alloced_tag_ren [2], alloced_tag_ren [3], + alloced_tag_ren [4], alloced_tag_ren [5], alloced_tag_ren [6], alloced_tag_ren [7], alloced_tag_ren [8], + alloced_tag_dout [0], alloced_tag_dout [1], alloced_tag_dout [2], alloced_tag_dout [3], + alloced_tag_dout [4], alloced_tag_dout [5], alloced_tag_dout [6], alloced_tag_dout [7], alloced_tag_dout [8], + alloced_tag_empty[0], alloced_tag_empty[1], alloced_tag_empty[2], alloced_tag_empty[3], + alloced_tag_empty[4], alloced_tag_empty[5], alloced_tag_empty[6], alloced_tag_empty[7], alloced_tag_empty[8], // 64 * 9 + + arb_tag_wen, arb_tag_din // 7 +}; +/* -------APB reated signal{end}------- */ +`endif + +/* --------Debug signal{begin}-------- */ +`ifdef SIMULATION + +/* | reserved | tag_num | chnl_num | valid | + * | 255:9 | 8:1 | 8:1 | 1 | + */ +assign debug = {dbug_tag_num, dbug_tag_chnl, dbug_tag_valid}; + +generate +if (`DMA_RD_CHNL_NUM == 9) begin:DBUG_TAG_CHNL9 + + assign dbug_tag_chnl = (tag_rrsp_valid[0] & tag_rrsp_ready[0]) ? 8'd0 : + (tag_rrsp_valid[1] & tag_rrsp_ready[1]) ? 8'd1 : + (tag_rrsp_valid[2] & tag_rrsp_ready[2]) ? 8'd2 : + (tag_rrsp_valid[3] & tag_rrsp_ready[3]) ? 8'd3 : + (tag_rrsp_valid[4] & tag_rrsp_ready[4]) ? 8'd4 : + (tag_rrsp_valid[5] & tag_rrsp_ready[5]) ? 8'd5 : + (tag_rrsp_valid[6] & tag_rrsp_ready[6]) ? 8'd6 : + (tag_rrsp_valid[7] & tag_rrsp_ready[7]) ? 8'd7 : + (tag_rrsp_valid[8] & tag_rrsp_ready[8]) ? 8'd8 : 8'd0; + + assign dbug_tag_num = (tag_rrsp_valid[0] & tag_rrsp_ready[0]) ? tag_rrsp_tag[1*`TAG_NUM_LOG-1:0*`TAG_NUM_LOG] : + (tag_rrsp_valid[1] & tag_rrsp_ready[1]) ? tag_rrsp_tag[2*`TAG_NUM_LOG-1:1*`TAG_NUM_LOG] : + (tag_rrsp_valid[2] & tag_rrsp_ready[2]) ? tag_rrsp_tag[3*`TAG_NUM_LOG-1:2*`TAG_NUM_LOG] : + (tag_rrsp_valid[3] & tag_rrsp_ready[3]) ? tag_rrsp_tag[4*`TAG_NUM_LOG-1:3*`TAG_NUM_LOG] : + (tag_rrsp_valid[4] & tag_rrsp_ready[4]) ? tag_rrsp_tag[5*`TAG_NUM_LOG-1:4*`TAG_NUM_LOG] : + (tag_rrsp_valid[5] & tag_rrsp_ready[5]) ? tag_rrsp_tag[6*`TAG_NUM_LOG-1:5*`TAG_NUM_LOG] : + (tag_rrsp_valid[6] & tag_rrsp_ready[6]) ? tag_rrsp_tag[7*`TAG_NUM_LOG-1:6*`TAG_NUM_LOG] : + (tag_rrsp_valid[7] & tag_rrsp_ready[7]) ? tag_rrsp_tag[8*`TAG_NUM_LOG-1:7*`TAG_NUM_LOG] : + (tag_rrsp_valid[8] & tag_rrsp_ready[8]) ? tag_rrsp_tag[9*`TAG_NUM_LOG-1:8*`TAG_NUM_LOG] : 8'd0; +end +endgenerate + +assign dbug_tag_valid = |(tag_rrsp_valid & tag_rrsp_ready); + +`endif +/* --------Debug signal{end}-------- */ + +/* --------Init logic{begin}-------- */ +always @(posedge dma_clk, negedge rst_n) begin + if (~rst_n) begin + init_cnt <= `TD 0; + end + else if (init_cnt < `TAG_NUM - 1'd1) begin + init_cnt <= `TD init_cnt + 1; + end +end + +always @(posedge dma_clk, negedge rst_n) begin + if (~rst_n) begin + init_done <= `TD 0; + end + else if (init_cnt == `TAG_NUM - 1'd1) begin + init_done <= `TD 1; + end +end +/* --------Init logic{end}-------- */ + +/* -------Free tag management{begin}------- */ + +assign free_tag_wen = (init_done ? arb_tag_wen : 1'd1) & !free_tag_full; +assign free_tag_din = init_done ? arb_tag_din : (init_cnt + `TAG_BASE); + +pcieifc_sync_fifo #( + .DSIZE ( `TAG_NUM_LOG ), // 6 + .ASIZE ( `TAG_NUM_LOG ) // 6 +) free_tag_fifo ( + + .clk ( dma_clk ), // i, i + .rst_n ( rst_n ), // i, i + .clr ( 1'd0 ), // i, 1 + + .wen ( free_tag_wen ), // i, 1 + .din ( free_tag_din ), // i, `TAG_NUM_LOG + .full ( free_tag_full ), // o, 1 + + .ren ( free_tag_ren ), // i, 1 + .dout ( free_tag_dout ), // o, `TAG_NUM_LOG + .empty( free_tag_empty ) // o, 1 + +`ifdef PCIEI_APB_DBG + ,.rtsel ( free_rtsel ) // i, 2 + ,.wtsel ( free_wtsel ) // i, 2 + ,.ptsel ( free_ptsel ) // i, 2 + ,.vg ( free_vg ) // i, 1 + ,.vs ( free_vs ) // i, 1 +`endif +); +assign free_tag_ren = tag_rreq_valid & tag_rreq_ready; +/* -------Free tag management{end}------- */ + +/* --------Tag rreq logic{begin}-------- */ +assign tag_rreq_valid = !free_tag_empty; +assign tag_rreq_tag = free_tag_dout; +/* --------Tag rreq logic{end}-------- */ + +genvar i; +generate +for (i = 0; i < `DMA_RD_CHNL_NUM; i = i + 1) begin:TAG_CHNL + +/* -------Alloced FIFO logic{begin}------- */ + assign alloced_tag_wen[i] = (tag_rreq_chnl == i) & tag_rreq_valid & tag_rreq_ready; // alloced_tag_full never asserted + assign alloced_tag_din[i] = {tag_rreq_tag, tag_rreq_sz, tag_rreq_last, tag_rreq_misc}; + pcieifc_sync_fifo #( + .DSIZE ( `TAG_NUM_LOG + `DW_LEN_WIDTH + 1 + `TAG_MISC ), // Stores tag & sz & last & misc. (30) + .ASIZE ( `TAG_NUM_LOG ) // (6) + ) alloced_tag_fifo ( + + .clk ( dma_clk ), // i, i + .rst_n ( rst_n ), // i, i + .clr ( 1'd0 ), // i, 1 + + .wen ( alloced_tag_wen [i] ), // i, 1 + .din ( alloced_tag_din [i] ), // i, `TAG_NUM_LOG + `DW_LEN_WIDTH + 1 + .full ( alloced_tag_full[i] ), // o, 1 + + .ren ( alloced_tag_ren [i] ), // i, 1 + .dout ( alloced_tag_dout [i] ), // o, `TAG_NUM_LOG + `DW_LEN_WIDTH + 1 + .empty( alloced_tag_empty[i] ) // o, 1 + + `ifdef PCIEI_APB_DBG + ,.rtsel ( alloced_rtsel[(i+1)*2-1:i*2] ) // i, 2 + ,.wtsel ( alloced_wtsel[(i+1)*2-1:i*2] ) // i, 2 + ,.ptsel ( alloced_ptsel[(i+1)*2-1:i*2] ) // i, 2 + ,.vg ( alloced_vg [i] ) // i, 1 + ,.vs ( alloced_vs [i] ) // i, 1 + `endif + ); + assign alloced_tag_ren [i] = (tag_rrsp_ready[i] == 1); +/* -------Alloced FIFO logic{end}------- */ + +/* --------Tag rrsp logic{begin}-------- */ + assign {tag_rrsp_tag [(i+1) * `TAG_NUM_LOG - 1 : i * `TAG_NUM_LOG ], + tag_rrsp_sz [(i+1) * `DW_LEN_WIDTH - 1 : i * `DW_LEN_WIDTH], + tag_rrsp_last[(i+1) * 1 - 1 : i * 1 ], + tag_rrsp_misc[(i+1) * `TAG_MISC - 1 : i * `TAG_MISC ]} = alloced_tag_dout[i]; + + assign tag_rrsp_valid[i] = !alloced_tag_empty[i]; +/* --------Tag rrsp logic{end}-------- */ + +end +endgenerate + +/* --------arbiter logic{begin}-------- */ +generate +if (`DMA_RD_CHNL_NUM == 2) begin:TAG_CHNL2 + + assign arb_tag_din = tag_rrsp_valid[0] & tag_rrsp_ready[0] ? tag_rrsp_tag[1*`TAG_NUM_LOG-1:0*`TAG_NUM_LOG] : + tag_rrsp_valid[1] & tag_rrsp_ready[1] ? tag_rrsp_tag[2*`TAG_NUM_LOG-1:1*`TAG_NUM_LOG] : 0; + + assign arb_tag_wen = tag_rrsp_valid[0] & tag_rrsp_ready[0] | + tag_rrsp_valid[1] & tag_rrsp_ready[1]; + +end +else if (`DMA_RD_CHNL_NUM == 9) begin:TAG_CHNL9 + + assign arb_tag_din = (tag_rrsp_valid[0] & tag_rrsp_ready[0]) ? tag_rrsp_tag[1*`TAG_NUM_LOG-1:0*`TAG_NUM_LOG] : + (tag_rrsp_valid[1] & tag_rrsp_ready[1]) ? tag_rrsp_tag[2*`TAG_NUM_LOG-1:1*`TAG_NUM_LOG] : + (tag_rrsp_valid[2] & tag_rrsp_ready[2]) ? tag_rrsp_tag[3*`TAG_NUM_LOG-1:2*`TAG_NUM_LOG] : + (tag_rrsp_valid[3] & tag_rrsp_ready[3]) ? tag_rrsp_tag[4*`TAG_NUM_LOG-1:3*`TAG_NUM_LOG] : + (tag_rrsp_valid[4] & tag_rrsp_ready[4]) ? tag_rrsp_tag[5*`TAG_NUM_LOG-1:4*`TAG_NUM_LOG] : + (tag_rrsp_valid[5] & tag_rrsp_ready[5]) ? tag_rrsp_tag[6*`TAG_NUM_LOG-1:5*`TAG_NUM_LOG] : + (tag_rrsp_valid[6] & tag_rrsp_ready[6]) ? tag_rrsp_tag[7*`TAG_NUM_LOG-1:6*`TAG_NUM_LOG] : + (tag_rrsp_valid[7] & tag_rrsp_ready[7]) ? tag_rrsp_tag[8*`TAG_NUM_LOG-1:7*`TAG_NUM_LOG] : + (tag_rrsp_valid[8] & tag_rrsp_ready[8]) ? tag_rrsp_tag[9*`TAG_NUM_LOG-1:8*`TAG_NUM_LOG] : 0; + + assign arb_tag_wen = (tag_rrsp_valid[0] & tag_rrsp_ready[0]) | + (tag_rrsp_valid[1] & tag_rrsp_ready[1]) | + (tag_rrsp_valid[2] & tag_rrsp_ready[2]) | + (tag_rrsp_valid[3] & tag_rrsp_ready[3]) | + (tag_rrsp_valid[4] & tag_rrsp_ready[4]) | + (tag_rrsp_valid[5] & tag_rrsp_ready[5]) | + (tag_rrsp_valid[6] & tag_rrsp_ready[6]) | + (tag_rrsp_valid[7] & tag_rrsp_ready[7]) | + (tag_rrsp_valid[8] & tag_rrsp_ready[8]); + +end +else if (`DMA_RD_CHNL_NUM == 10) begin:TAG_CHNL10 + + assign arb_tag_din = (tag_rrsp_valid[0] & tag_rrsp_ready[0]) ? tag_rrsp_tag[1*`TAG_NUM_LOG-1:0*`TAG_NUM_LOG] : + (tag_rrsp_valid[1] & tag_rrsp_ready[1]) ? tag_rrsp_tag[2*`TAG_NUM_LOG-1:1*`TAG_NUM_LOG] : + (tag_rrsp_valid[2] & tag_rrsp_ready[2]) ? tag_rrsp_tag[3*`TAG_NUM_LOG-1:2*`TAG_NUM_LOG] : + (tag_rrsp_valid[3] & tag_rrsp_ready[3]) ? tag_rrsp_tag[4*`TAG_NUM_LOG-1:3*`TAG_NUM_LOG] : + (tag_rrsp_valid[4] & tag_rrsp_ready[4]) ? tag_rrsp_tag[5*`TAG_NUM_LOG-1:4*`TAG_NUM_LOG] : + (tag_rrsp_valid[5] & tag_rrsp_ready[5]) ? tag_rrsp_tag[6*`TAG_NUM_LOG-1:5*`TAG_NUM_LOG] : + (tag_rrsp_valid[6] & tag_rrsp_ready[6]) ? tag_rrsp_tag[7*`TAG_NUM_LOG-1:6*`TAG_NUM_LOG] : + (tag_rrsp_valid[7] & tag_rrsp_ready[7]) ? tag_rrsp_tag[8*`TAG_NUM_LOG-1:7*`TAG_NUM_LOG] : + (tag_rrsp_valid[8] & tag_rrsp_ready[8]) ? tag_rrsp_tag[9*`TAG_NUM_LOG-1:8*`TAG_NUM_LOG] : + (tag_rrsp_valid[9] & tag_rrsp_ready[9]) ? tag_rrsp_tag[10*`TAG_NUM_LOG-1:9*`TAG_NUM_LOG] : 0; + + assign arb_tag_wen = (tag_rrsp_valid[0] & tag_rrsp_ready[0]) | + (tag_rrsp_valid[1] & tag_rrsp_ready[1]) | + (tag_rrsp_valid[2] & tag_rrsp_ready[2]) | + (tag_rrsp_valid[3] & tag_rrsp_ready[3]) | + (tag_rrsp_valid[4] & tag_rrsp_ready[4]) | + (tag_rrsp_valid[5] & tag_rrsp_ready[5]) | + (tag_rrsp_valid[6] & tag_rrsp_ready[6]) | + (tag_rrsp_valid[7] & tag_rrsp_ready[7]) | + (tag_rrsp_valid[8] & tag_rrsp_ready[8]) | + (tag_rrsp_valid[9] & tag_rrsp_ready[9]); + +end +endgenerate +/* --------Tag rrsp logic{end}-------- */ + +endmodule diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/DMA/DMA_Read/read_req_rsp.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/DMA/DMA_Read/read_req_rsp.v new file mode 100644 index 0000000000000000000000000000000000000000..1f2f25eb5a111fa55edd16dbbadbfb00a6e26785 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/DMA/DMA_Read/read_req_rsp.v @@ -0,0 +1,709 @@ +`timescale 1ns / 100ps +//************************************************************************* +// > File Name: read_req_rsp.v +// > Author : Kangning +// > Date : 2020-08-26 +// > Note : read_req_rsp, used to process read request and read response. +//************************************************************************* + +//`include "../lib/dma_def_h.v" + +module read_req_rsp #( + parameter [8 * `DMA_RD_CHNL_NUM - 1 : 0] CHNL_NUM_TAB = { + 8'd9, + 8'd8, + 8'd7, + 8'd6, + 8'd5, + 8'd4, + 8'd3, + 8'd2, + 8'd1, + 8'd0 + } +) ( + input wire dma_clk , + input wire rst_n , + output wire init_done, // o, 1 + + + /* ------- Read Request from RDMA{begin}------- */ + /* dma_*_head, valid only in first beat of a packet + * | Reserved | address | Reserved | Byte length | + * | 127:96 | 95:32 | 31:13 | 12:0 | + */ + input wire [`DMA_RD_CHNL_NUM * 1 -1 : 0] dma_rd_req_valid, // i, `DMA_RD_CHNL_NUM * 1 + input wire [`DMA_RD_CHNL_NUM * 1 -1 : 0] dma_rd_req_last , // i, `DMA_RD_CHNL_NUM * 1 + input wire [`DMA_RD_CHNL_NUM * `DMA_DATA_W-1 : 0] dma_rd_req_data , // i, `DMA_RD_CHNL_NUM * `DMA_DATA_W + input wire [`DMA_RD_CHNL_NUM * `DMA_HEAD_W-1 : 0] dma_rd_req_head , // i, `DMA_RD_CHNL_NUM * `DMA_HEAD_W + output wire [`DMA_RD_CHNL_NUM * 1 -1 : 0] dma_rd_req_ready, // o, `DMA_RD_CHNL_NUM * 1 + /* ------- Read Request from RDMA{end}------- */ + + /* ------- Read Response to RDMA{begin} ------- */ + /* dma_*_head , valid only in first beat of a packet + * | Reserved | address | Reserved | Byte length | + * | 127:96 | 95:32 | 31:13 | 12:0 | + */ + output wire [`DMA_RD_CHNL_NUM * 1 -1 : 0] dma_rd_rsp_valid, // o, `DMA_RD_CHNL_NUM * 1 + output wire [`DMA_RD_CHNL_NUM * 1 -1 : 0] dma_rd_rsp_last , // o, `DMA_RD_CHNL_NUM * 1 + output wire [`DMA_RD_CHNL_NUM * `DMA_DATA_W-1 : 0] dma_rd_rsp_data , // o, `DMA_RD_CHNL_NUM * `DMA_DATA_W + output wire [`DMA_RD_CHNL_NUM * `DMA_HEAD_W-1 : 0] dma_rd_rsp_head , // o, `DMA_RD_CHNL_NUM * `DMA_HEAD_W + input wire [`DMA_RD_CHNL_NUM * 1 -1 : 0] dma_rd_rsp_ready, // i, `DMA_RD_CHNL_NUM * 1 + /* ------- Read Response to RDMA{end} ------- */ + + /* -------axis read request interface{begin}------- */ + /* AXI-Stream read request tuser. + * Only valid in first beat of a packet + * | Reserved | REQ_TYPE | Tag | address | Reserved | DW length | first BE | last BE | + * | 127:108 | 107:104 | 103:96 | 95:32 | 31:19 | 18:8 | 7:4 | 3:0 | + */ + output wire axis_rd_req_tvalid , // o, 1 + output wire axis_rd_req_tlast , // o, 1 + output wire [`DMA_DATA_W -1:0] axis_rd_req_tdata , // o, `DMA_DATA_W + output wire [`AXIS_TUSER_W-1:0] axis_rd_req_tuser , // o, `AXIS_TUSER_W + output wire [`DMA_KEEP_W -1:0] axis_rd_req_tkeep , // o, `DMA_KEEP_W + input wire axis_rd_req_tready , // i, 1 + /* -------axis read request interface{end}------- */ + + /* -------axis read response interface{begin}------- */ + /* AXI-Stream read response tuser, interact with read response distributor. + * Only valid in first beat of a packet + * | Reserved | REQ CPL | Tag | address | Reserved | DW length | first BE | last BE | + * | 119:105 | 104 | 103:96 | 95:32 | 31:19 | 18:8 | 7:4 | 3:0 | + */ + input wire axis_rd_rsp_tvalid, // i, 1 + input wire axis_rd_rsp_tlast , // i, 1 + input wire [`DMA_DATA_W -1:0] axis_rd_rsp_tdata , // i, `DMA_DATA_W + input wire [`AXIS_TUSER_W-1:0] axis_rd_rsp_tuser , // i, `AXIS_TUSER_W + input wire [`DMA_KEEP_W -1:0] axis_rd_rsp_tkeep , // i, `DMA_KEEP_W + output wire axis_rd_rsp_tready, // o, 1 + /* -------axis read response interface{end}------- */ + + /* -------PCIe fragment property{begin}------- */ + /* This signal indicates the (max payload size & max read request size) agreed in the communication + * 3'b000 -- 128 B + * 3'b001 -- 256 B + * 3'b010 -- 512 B + * 3'b011 -- 1024B + * 3'b100 -- 2048B + * 3'b101 -- 4096B + */ + input wire [2:0] max_pyld_sz , + input wire [2:0] max_rd_req_sz // max read request size + /* -------PCIe fragment property{end}------- */ + +`ifdef PCIEI_APB_DBG + /* -------APB reated signal{begin}------- */ + ,input wire [(2*`DMA_RD_CHNL_NUM+3)*`SRAM_RW_DATA_W-1:0] rw_data // i, (2*`DMA_RD_CHNL_NUM+3)*`SRAM_RW_DATA_W + ,input wire [31:0] dbg_sel // debug bus select + ,output wire [31:0] dbg_bus // debug bus data + /* -------APB reated signal{end}------- */ +`endif + + +`ifdef SIMULATION + /* ------- Debug interface {begin}------- */ + /* | reserved | idx | end | out | + * | 255:CHNL_NUM_LOG+2 | CHNL_NUM_LOG+2-1:2 | 1 | 0 | + */ + ,output wire [255:0] debug_rd + + /* | reserved | tag_num | chnl_num | valid | + * | 255:17 | 16:9 | 8:1 | 0 | + */ + ,output wire [255:0] debug_tag + /* ------- Debug interface {end}------- */ +`endif +); + +wire init_done_tag_mgmt, init_done_rd_rsp; + +/* -------Request FIFO relevant{begin}------- */ +wire [`DMA_RD_CHNL_NUM * 1 -1 : 0] st_rd_req_valid; +wire [`DMA_RD_CHNL_NUM * 1 -1 : 0] st_rd_req_ready; +wire [`DMA_RD_CHNL_NUM * `DMA_HEAD_W-1 : 0] st_rd_req_head ; +/* -------Request FIFO relevant{end}------- */ + +/* -------axis read request interface{begin}------- */ +wire [`DMA_RD_CHNL_NUM * 1 -1:0] axis_rd_request_tvalid; +wire [`DMA_RD_CHNL_NUM * 1 -1:0] axis_rd_request_tlast ; +wire [`DMA_RD_CHNL_NUM * `DMA_DATA_W -1:0] axis_rd_request_tdata ; +wire [`DMA_RD_CHNL_NUM * `AXIS_TUSER_W-1:0] axis_rd_request_tuser ; +wire [`DMA_RD_CHNL_NUM * `DMA_KEEP_W -1:0] axis_rd_request_tkeep ; +wire [`DMA_RD_CHNL_NUM * 1 -1:0] axis_rd_request_tready; +/* -------axis read request interface{end}------- */ + +/* -------axis rd req arbiter interface{begin}------- */ +wire [1 -1:0] axis_rd_req_arb_tvalid; +wire [1 -1:0] axis_rd_req_arb_tlast ; +wire [`DMA_DATA_W -1:0] axis_rd_req_arb_tdata ; +wire [`AXIS_TUSER_W-1:0] axis_rd_req_arb_tuser ; +wire [`DMA_KEEP_W -1:0] axis_rd_req_arb_tkeep ; +wire [1 -1:0] axis_rd_req_arb_tready; +/* -------axis rd req arbiter interface{end}------- */ + +/* -------Tag Management relevant{begin}------- */ +wire tag_rreq_ready; +wire tag_rreq_last ; +wire [`DW_LEN_WIDTH-1:0] tag_rreq_sz ; +wire [`TAG_MISC -1:0] tag_rreq_misc ; +wire [8 -1:0] tag_rreq_chnl ; +wire [`TAG_NUM_LOG -1:0] tag_rreq_tag ; +wire tag_rreq_valid; + +wire [`DMA_RD_CHNL_NUM * 1 - 1 : 0] tag_rrsp_ready; +wire [`DMA_RD_CHNL_NUM * 1 - 1 : 0] tag_rrsp_last ; +wire [`DMA_RD_CHNL_NUM * `DW_LEN_WIDTH - 1 : 0] tag_rrsp_sz ; +wire [`DMA_RD_CHNL_NUM * `TAG_MISC - 1 : 0] tag_rrsp_misc ; +wire [`DMA_RD_CHNL_NUM * `TAG_NUM_LOG - 1 : 0] tag_rrsp_tag ; +wire [`DMA_RD_CHNL_NUM * 1 - 1 : 0] tag_rrsp_valid; +/* -------Tag Management relevant{end}------- */ + +/* ------- Read sub-req response{begin} ------- */ +/* dma_*_head + * | emit | chnl_num | Reserved | address | Reserved | Byte length | + * | 127 | 126:120 | 119:96 | 95:32 | 31:13 | 12:0 | + */ +wire rd_rsp_demux_valid; +wire rd_rsp_demux_last ; +wire [`DMA_DATA_W-1:0] rd_rsp_demux_data ; +wire [`DMA_HEAD_W-1:0] rd_rsp_demux_head ; +wire rd_rsp_demux_ready; + +wire st_rd_rsp_demux_valid; +wire st_rd_rsp_demux_last ; +wire [`DMA_DATA_W-1:0] st_rd_rsp_demux_data ; +wire [`DMA_HEAD_W-1:0] st_rd_rsp_demux_head ; +wire st_rd_rsp_demux_ready; +/* ------- Read sub-req response{end} ------- */ + +/* ------- Read sub-req response{begin} ------- */ +/* dma_*_head + * | emit | chnl_num | Reserved | address | Reserved | Byte length | + * | 127 | 126:120 | 119:96 | 95:32 | 31:13 | 12:0 | + */ +wire [`DMA_RD_CHNL_NUM * 1 - 1 : 0] rd_rsp_concat_valid; // o, 1 +wire [`DMA_RD_CHNL_NUM * 1 - 1 : 0] rd_rsp_concat_last ; // o, 1 +wire [`DMA_RD_CHNL_NUM * `DMA_DATA_W- 1 : 0] rd_rsp_concat_data ; // o, `DMA_DATA_W +wire [`DMA_RD_CHNL_NUM * `DMA_HEAD_W- 1 : 0] rd_rsp_concat_head ; // o, `DMA_HEAD_W +wire [`DMA_RD_CHNL_NUM * 1 - 1 : 0] rd_rsp_concat_ready; // i, 1 + +/* Indicate that the rsp chnl is available. + * This signal is deasserted when : + * 1. rsp output chnl signl dma_rd_rsp_ready is deasserted; && + * 2. There is (part of) rsp pkt in sub_req_rsp_concat module. + */ +wire [`DMA_RD_CHNL_NUM * 1 - 1 : 0] is_rsp_chnl_avail; +/* ------- Read sub-req response{end} ------- */ + +`ifdef PCIEI_APB_DBG +/* -------APB reated signal{begin}------- */ +wire [(`DMA_RD_CHNL_NUM+1)*`SRAM_RW_DATA_W-1:0] rw_data_tag; +wire [2*`SRAM_RW_DATA_W -1:0] rw_data_rsp; +wire [`DMA_RD_CHNL_NUM*`SRAM_RW_DATA_W -1:0] rw_data_concat; + +wire [32-1:0] dbg_sel_rd_top, dbg_sel_rd_req, dbg_sel_rreq_arb, dbg_sel_tag_req, dbg_sel_tag_mgmt, dbg_sel_rd_rsp, + dbg_sel_dma_demux, dbg_sel_rsp_concat; +wire [32-1:0] dbg_bus_rd_top, dbg_bus_rd_req, dbg_bus_rreq_arb, dbg_bus_tag_req, dbg_bus_tag_mgmt, dbg_bus_rd_rsp, + dbg_bus_dma_demux, dbg_bus_rsp_concat; + +wire [`RD_TOP_SIGNAL_W-1:0] dbg_signal_rd_top; +wire [`DMA_RD_CHNL_NUM*`RD_REQ_SIGNAL_W-1:0] dbg_signal_rd_req; +wire [`RREQ_ARB_SIGNAL_W -1:0] dbg_signal_rreq_arb; +wire [`TAG_REQ_SIGNAL_W -1:0] dbg_signal_tag_req; +wire [`TAG_MGMT_SIGNAL_W -1:0] dbg_signal_tag_mgmt; +wire [`DMA_DEMUX_SIGNAL_W-1:0] dbg_signal_dma_demux; +wire [`DMA_RD_CHNL_NUM*`RSP_CONCAT_SIGNAL_W-1:0] dbg_signal_rsp_concat; +/* -------APB reated signal{end}------- */ +`endif + +//--------------------------------------------------------------------------------------------------------------------------- + +`ifdef PCIEI_APB_DBG +/* -------APB reated signal{begin}------- */ +assign {rw_data_tag, rw_data_rsp, rw_data_concat} = rw_data; +assign dbg_bus = (`RD_TOP_DBG_B <= dbg_sel && dbg_sel < `RD_REQ_DBG_B ) ? dbg_bus_rd_top : + (`RD_REQ_DBG_B <= dbg_sel && dbg_sel < `RREQ_ARB_DBG_B ) ? dbg_bus_rd_req : + (`RREQ_ARB_DBG_B <= dbg_sel && dbg_sel < `TAG_REQ_DBG_B ) ? dbg_bus_rreq_arb : + (`TAG_REQ_DBG_B <= dbg_sel && dbg_sel < `TAG_MGMT_DBG_B ) ? dbg_bus_tag_req : + (`TAG_MGMT_DBG_B <= dbg_sel && dbg_sel < `RD_RSP_DBG_B ) ? dbg_bus_tag_mgmt : + (`RD_RSP_DBG_B <= dbg_sel && dbg_sel < `DMA_DEMUX_DBG_B ) ? dbg_bus_rd_rsp : + (`DMA_DEMUX_DBG_B <= dbg_sel && dbg_sel < `RSP_CONCAT_DBG_B ) ? dbg_bus_dma_demux : + (`RSP_CONCAT_DBG_B <= dbg_sel && dbg_sel < `RD_REQ_RSP_DBG_SIZE) ? dbg_bus_rsp_concat : 32'd0; + +assign dbg_sel_rd_top = (`RD_TOP_DBG_B <= dbg_sel && dbg_sel < `RD_REQ_DBG_B ) ? (dbg_sel - `RD_TOP_DBG_B ) : 32'd0; +assign dbg_sel_rd_req = (`RD_REQ_DBG_B <= dbg_sel && dbg_sel < `RREQ_ARB_DBG_B ) ? (dbg_sel - `RD_REQ_DBG_B ) : 32'd0; +assign dbg_sel_rreq_arb = (`RREQ_ARB_DBG_B <= dbg_sel && dbg_sel < `TAG_REQ_DBG_B ) ? (dbg_sel - `RREQ_ARB_DBG_B ) : 32'd0; +assign dbg_sel_tag_req = (`TAG_REQ_DBG_B <= dbg_sel && dbg_sel < `TAG_MGMT_DBG_B ) ? (dbg_sel - `TAG_REQ_DBG_B ) : 32'd0; +assign dbg_sel_tag_mgmt = (`TAG_MGMT_DBG_B <= dbg_sel && dbg_sel < `RD_RSP_DBG_B ) ? (dbg_sel - `TAG_MGMT_DBG_B ) : 32'd0; +assign dbg_sel_rd_rsp = (`RD_RSP_DBG_B <= dbg_sel && dbg_sel < `DMA_DEMUX_DBG_B ) ? (dbg_sel - `RD_RSP_DBG_B ) : 32'd0; +assign dbg_sel_dma_demux = (`DMA_DEMUX_DBG_B <= dbg_sel && dbg_sel < `RSP_CONCAT_DBG_B ) ? (dbg_sel - `DMA_DEMUX_DBG_B ) : 32'd0; +assign dbg_sel_rsp_concat = (`RSP_CONCAT_DBG_B <= dbg_sel && dbg_sel < `RD_REQ_RSP_DBG_SIZE) ? (dbg_sel - `RSP_CONCAT_DBG_B) : 32'd0; + +// Debug bus for read top +assign dbg_bus_rd_top = dbg_signal_rd_top >> {dbg_sel_rd_top, 5'd0}; + +// Debug bus for read request +assign dbg_bus_rd_req = dbg_signal_rd_req >> {dbg_sel_rd_req, 5'd0}; + +// Debug bus for read arbiter +assign dbg_bus_rreq_arb = dbg_signal_rreq_arb >> {dbg_sel_rreq_arb, 5'd0}; + +// Debug bus for tag request +assign dbg_bus_tag_req = dbg_signal_tag_req >> {dbg_sel_tag_req, 5'd0}; + +// Debug bus for tag request +assign dbg_bus_tag_mgmt = dbg_signal_tag_mgmt >> {dbg_sel_tag_mgmt, 5'd0}; + +// Debug bus for tag request +assign dbg_bus_dma_demux = dbg_signal_dma_demux >> {dbg_sel_dma_demux, 5'd0}; + +// Debug bus for tag request +assign dbg_bus_rsp_concat = dbg_signal_rsp_concat >> {dbg_sel_rsp_concat, 5'd0}; + +assign dbg_signal_rd_top = { // 9716 + init_done_tag_mgmt, init_done_rd_rsp, // 2 + st_rd_req_valid, st_rd_req_ready, st_rd_req_head , // 1170 + axis_rd_request_tvalid, axis_rd_request_tlast , axis_rd_request_tdata , axis_rd_request_tuser , axis_rd_request_tkeep , axis_rd_request_tready, // 3555 + axis_rd_req_arb_tvalid, axis_rd_req_arb_tlast , axis_rd_req_arb_tdata , axis_rd_req_arb_tuser , axis_rd_req_arb_tkeep , axis_rd_req_arb_tready, // 395 + tag_rreq_ready, tag_rreq_last, tag_rreq_sz, tag_rreq_misc, tag_rreq_chnl, tag_rreq_tag, tag_rreq_valid, // 40 + tag_rrsp_ready, tag_rrsp_last, tag_rrsp_sz, tag_rrsp_misc, tag_rrsp_tag, tag_rrsp_valid, // 288 + rd_rsp_demux_valid, rd_rsp_demux_last , rd_rsp_demux_data , rd_rsp_demux_head , rd_rsp_demux_ready, // 387 + st_rd_rsp_demux_valid, st_rd_rsp_demux_last , st_rd_rsp_demux_data , st_rd_rsp_demux_head , st_rd_rsp_demux_ready, // 387 + rd_rsp_concat_valid, rd_rsp_concat_last , rd_rsp_concat_data , rd_rsp_concat_head , rd_rsp_concat_ready, // 3483 + is_rsp_chnl_avail // 9 +}; +/* -------APB reated signal{end}------- */ +`endif + +assign init_done = init_done_tag_mgmt & init_done_rd_rsp; + +genvar i; +generate +for (i = 0; i < `DMA_RD_CHNL_NUM; i = i + 1) begin:DMA_RD_CHNL + + /* -------Read Request FIFO{begin}------- */ + st_reg #( + .TUSER_WIDTH ( 1 ), + .TDATA_WIDTH ( `DMA_HEAD_W ) + ) st_rd_req ( + .clk ( dma_clk ), // i, 1 + .rst_n ( rst_n ), // i, 1 + + /* -------input axis-like interface{begin}------- */ + .axis_tvalid ( dma_rd_req_valid[i] ), // i, 1 + .axis_tlast ( 1'd0 ), // i, 1 + .axis_tuser ( 1'd0 ), // i, TUSER_WIDTH + .axis_tdata ( {CHNL_NUM_TAB[(i+1)*8-1 : i*8], dma_rd_req_head[(i+1)*`DMA_HEAD_W-1-8 : i*`DMA_HEAD_W]} ), // i, TDATA_WIDTH + .axis_tready ( dma_rd_req_ready[i] ), // o, 1 + /* -------input axis-like interface{end}------- */ + + /* -------output in_reg inteface{begin}------- */ + .axis_reg_tvalid ( st_rd_req_valid[i] ), // o, 1 + .axis_reg_tlast ( ), // o, 1 + .axis_reg_tuser ( ), // o, TUSER_WIDTH + .axis_reg_tdata ( st_rd_req_head[(i+1)*`DMA_HEAD_W-1 : i*`DMA_HEAD_W] ), // o, TDATA_WIDTH + .axis_reg_tready ( st_rd_req_ready[i] ) // i, 1 + /* -------output in_reg inteface{end}------- */ + ); + /* -------Read Request FIFO{end}------- */ + + /* -------Read request handling(align && split req){begin}-------- */ + read_request #( + + ) read_request ( + .dma_clk ( dma_clk ), // i, 1 + .rst_n ( rst_n ), // i, 1 + + /* ------- Read Request input{begin} ------- */ + /* dma_*_head (interact with RDMA modules), valid only in first beat of a packet + * | chnl_num | Reserved | address | Reserved | Byte length | + * | 127:120 | 119:96 | 95:32 | 31:13 | 12:0 | + */ + .rd_req_valid ( st_rd_req_valid[i] ), // i, 1 + .rd_req_head ( st_rd_req_head[(i+1)*`DMA_HEAD_W-1 : i*`DMA_HEAD_W] ), // i, `DMA_HEAD_W + .rd_req_ready ( st_rd_req_ready[i] ), // o, 1 + /* ------- Read Request input{end} ------- */ + + /* -------axis read request interface{begin}------- */ + /* AXI-Stream read request tuser, every read request contains only one beat. + * | chnl_num |last_sub_req | Reserved | REQ_TYPE |Tag(inv)| address | Reserved | DW length | first BE | last BE | + * | 127:120 | 119 | 118:108 | 107:104 | 103:96 | 95:32 | 31:19 | 18:8 | 7:4 | 3:0 | + */ + .axis_rd_request_tvalid ( axis_rd_request_tvalid[(i+1) * 1 - 1 : i * 1 ] ), // o, 1 + .axis_rd_request_tlast ( axis_rd_request_tlast [(i+1) * 1 - 1 : i * 1 ] ), // o, 1 + .axis_rd_request_tdata ( axis_rd_request_tdata [(i+1) * `DMA_DATA_W - 1 : i * `DMA_DATA_W ] ), // o, `DMA_DATA_W + .axis_rd_request_tuser ( axis_rd_request_tuser [(i+1) * `AXIS_TUSER_W - 1 : i * `AXIS_TUSER_W] ), // o, `AXIS_TUSER_W + .axis_rd_request_tkeep ( axis_rd_request_tkeep [(i+1) * `DMA_KEEP_W - 1 : i * `DMA_KEEP_W ] ), // o, `DMA_KEEP_W + .axis_rd_request_tready ( axis_rd_request_tready[(i+1) * 1 - 1 : i * 1 ] ), // i, 1 + /* -------axis read request interface{end}------- */ + + /* --------read request blocking detection{begin}-------- */ + .chnl_avail ( dma_rd_rsp_ready[i] ), // i, 1 + .chnl_valid ( tag_rrsp_valid [i] ), // i, 1 + /* --------read request blocking detection{end}-------- */ + + /* -------PCIe fragment property{begin}------- */ + /* This signal indicates the (max payload size & max read request size) agreed in the communication + * 3'b000 -- 128 B + * 3'b001 -- 256 B + * 3'b010 -- 512 B + * 3'b011 -- 1024B + * 3'b100 -- 2048B + * 3'b101 -- 4096B + */ + .max_pyld_sz ( max_pyld_sz ), // i, 3 + .max_rd_req_sz ( max_rd_req_sz ) // i, 3 + /* -------PCIe fragment property{end}------- */ + + `ifdef PCIEI_APB_DBG + /* -------APB reated signal{begin}------- */ + ,.dbg_signal ( dbg_signal_rd_req[(i+1)*`RD_REQ_SIGNAL_W-1:i*`RD_REQ_SIGNAL_W] ) // o, `RD_REQ_SIGNAL_W + /* -------APB reated signal{end}------- */ + `endif + ); + /* -------Read request handling(align && split req){end}-------- */ + +end +endgenerate + +req_arbiter #( + .CHNL_NUM_LOG ( `DMA_RD_CHNL_NUM_LOG ), + .CHANNEL_NUM ( `DMA_RD_CHNL_NUM ) // number of slave signals to arbit +) rd_req_arbiter ( + + .dma_clk ( dma_clk ), // i, 1 + .rst_n ( rst_n ), // i, 1 + + /* -------Slave AXIS Interface(Connect to Read Request Module){begin}------- */ + /* AXI-Stream read request tuser, every read request contains only one beat. + * | chnl_num |last_sub_req | Reserved | REQ_TYPE |Tag(inv)| address | Reserved | DW length | first BE | last BE | + * | 127:120 | 119 | 118:108 | 107:104 | 103:96 | 95:32 | 31:19 | 18:8 | 7:4 | 3:0 | + */ + .s_axis_req_tvalid ( axis_rd_request_tvalid ), // i, CHANNEL_NUM * 1 + .s_axis_req_tlast ( axis_rd_request_tlast ), // i, CHANNEL_NUM * 1 + .s_axis_req_tdata ( axis_rd_request_tdata ), // i, CHANNEL_NUM * `DMA_DATA_W + .s_axis_req_tuser ( axis_rd_request_tuser ), // i, CHANNEL_NUM * `AXIS_TUSER_W ;The field contents are different from dma_*_head interface + .s_axis_req_tkeep ( axis_rd_request_tkeep ), // i, CHANNEL_NUM * `DMA_KEEP_W + .s_axis_req_tready ( axis_rd_request_tready ), // o, CHANNEL_NUM * 1 + /* -------Slave AXIS Interface(Connect to Read Request Module){end}------- */ + + + /* ------- Master AXIS Interface(Connect to tag_alloc module){begin} ------- */ + /* AXI-Stream read request tuser, every read request contains only one beat. + * | chnl_num |last_sub_req | Reserved | REQ_TYPE |Tag(inv)| address | Reserved | DW length | first BE | last BE | + * | 127:120 | 119 | 118:108 | 107:104 | 103:96 | 95:32 | 31:19 | 18:8 | 7:4 | 3:0 | + */ + .m_axis_req_tvalid ( axis_rd_req_arb_tvalid ), // o, 1 + .m_axis_req_tlast ( axis_rd_req_arb_tlast ), // o, 1 + .m_axis_req_tdata ( axis_rd_req_arb_tdata ), // o, `DMA_DATA_W + .m_axis_req_tuser ( axis_rd_req_arb_tuser ), // o, `AXIS_TUSER_W ;The field contents are different from dma_*_tuser interface + .m_axis_req_tkeep ( axis_rd_req_arb_tkeep ), // o, `DMA_KEEP_W + .m_axis_req_tready ( axis_rd_req_arb_tready ) // i, 1 + /* ------- Master AXIS Interface(Connect to tag_alloc module){end} ------- */ + +`ifdef PCIEI_APB_DBG + /* -------APB reated signal{begin}------- */ + ,.dbg_signal ( dbg_signal_rreq_arb ) // o, `RREQ_ARB_SIGNAL_W + /* -------APB reated signal{end}------- */ +`endif + +`ifdef SIMULATION + /* ------- Debug interface {begin}------- */ + /* | reserved | idx | end | out | + * | 255:CHNL_NUM_LOG+2 | CHNL_NUM_LOG+2-1:2 | 1 | 0 | + */ + ,.debug ( debug_rd ) + /* ------- Debug interface {end}------- */ +`endif +); + +tag_request #( + +) tag_request ( + .dma_clk ( dma_clk ), // i, 1 + .rst_n ( rst_n ), // i, 1 + + /* ------- Connect to rd_req_arbiter module{begin} ------- */ + /* AXI-Stream read request tuser, every read request contains only one beat. + * | chnl_num |last_sub_req | Reserved | REQ_TYPE |Tag(inv)| address | Reserved | DW length | first BE | last BE | + * | 127:120 | 119 | 118:108 | 107:104 | 103:96 | 95:32 | 31:19 | 18:8 | 7:4 | 3:0 | + */ + .axis_rreq_tvalid ( axis_rd_req_arb_tvalid ), // i, 1 + .axis_rreq_tlast ( axis_rd_req_arb_tlast ), // i, 1 + .axis_rreq_tdata ( axis_rd_req_arb_tdata ), // i, `DMA_DATA_W + .axis_rreq_tuser ( axis_rd_req_arb_tuser ), // i, `AXIS_TUSER_W ;The field contents are different from dma_*_tuser interface + .axis_rreq_tkeep ( axis_rd_req_arb_tkeep ), // i, `DMA_KEEP_W + .axis_rreq_tready ( axis_rd_req_arb_tready ), // o, 1 + /* ------- Connect to rd_req_arbiter module{end} ------- */ + + /* -------tag request{begin}------- */ + .tag_rreq_ready ( tag_rreq_ready ), // o, 1 + .tag_rreq_last ( tag_rreq_last ), // o, 1 ; Indicate the last sub-req for rd req + .tag_rreq_sz ( tag_rreq_sz ), // o, `DW_LEN_WIDTH ; Request size(in dw unit) of this tag + .tag_rreq_misc ( tag_rreq_misc ), // o, `TAG_MISC ; Including addr && dw empty info + .tag_rreq_chnl ( tag_rreq_chnl ), // o, 8 ; channel number for this request + .tag_rreq_tag ( tag_rreq_tag ), // i, `TAG_NUM_LOG + .tag_rreq_valid ( tag_rreq_valid ), // i, 1 + /* -------tag request{end}------- */ + + /* -------axis read request interface{begin}------- */ + /* AXI-Stream read request tuser, interact with read request arbiter. + * Only valid in first beat of a packet + * | Reserved | REQ_TYPE | Tag | address | Reserved | DW length | first BE | last BE | + * | 127:108 | 107:104 | 103:96 | 95:32 | 31:19 | 18:8 | 7:4 | 3:0 | + */ + .axis_rreq_tag_tvalid ( axis_rd_req_tvalid ), // o, 1 + .axis_rreq_tag_tlast ( axis_rd_req_tlast ), // o, 1 + .axis_rreq_tag_tdata ( axis_rd_req_tdata ), // o, `DMA_DATA_W + .axis_rreq_tag_tuser ( axis_rd_req_tuser ), // o, `AXIS_TUSER_W + .axis_rreq_tag_tkeep ( axis_rd_req_tkeep ), // o, `DMA_KEEP_W + .axis_rreq_tag_tready ( axis_rd_req_tready ) // i, 1 + /* -------axis read request interface{end}------- */ + +`ifdef PCIEI_APB_DBG + /* -------APB reated signal{begin}------- */ + ,.dbg_signal ( dbg_signal_tag_req ) // o, `TAG_REQ_SIGNAL_W + /* -------APB reated signal{end}------- */ +`endif +); + +np_tag_mgmt #( + +) np_tag_mgmt ( + + .dma_clk ( dma_clk ), // i, 1 + .rst_n ( rst_n ), // i, 1 + .init_done ( init_done_tag_mgmt ), // o, 1 + + /* -------tag request{begin}------- */ + .tag_rreq_ready ( tag_rreq_ready ), // i, 1 + .tag_rreq_last ( tag_rreq_last ), // i, 1 ; Indicate the last sub-req for rd req + .tag_rreq_sz ( tag_rreq_sz ), // i, `DW_LEN_WIDTH ; Request size(in dw unit) of this tag + .tag_rreq_misc ( tag_rreq_misc ), // i, `TAG_MISC ; Including addr && dw empty info + .tag_rreq_chnl ( tag_rreq_chnl ), // i, 8 ; channel number for this request + .tag_rreq_tag ( tag_rreq_tag ), // o, `TAG_NUM_LOG + .tag_rreq_valid ( tag_rreq_valid ), // o, 1 + /* -------tag request{end}------- */ + + /* -------tag release{begin}------- */ + // Note that only one channel is allowed to assert at the same time + .tag_rrsp_ready ( tag_rrsp_ready ), // i, `DMA_RD_CHNL_NUM * 1 + .tag_rrsp_last ( tag_rrsp_last ), // o, `DMA_RD_CHNL_NUM * 1 + .tag_rrsp_sz ( tag_rrsp_sz ), // o, `DMA_RD_CHNL_NUM * `DW_LEN_WIDTH + .tag_rrsp_misc ( tag_rrsp_misc ), // o, `DMA_RD_CHNL_NUM * `TAG_MISC ; Including addr && dw empty info + .tag_rrsp_tag ( tag_rrsp_tag ), // o, `DMA_RD_CHNL_NUM * `TAG_NUM_LOG + .tag_rrsp_valid ( tag_rrsp_valid ) // o, `DMA_RD_CHNL_NUM * 1 + /* -------tag release{end}------- */ + +`ifdef PCIEI_APB_DBG + /* -------APB reated signal{begin}------- */ + ,.rw_data ( rw_data_tag ) // i, (`DMA_RD_CHNL_NUM+1)*`SRAM_RW_DATA_W + ,.dbg_signal ( dbg_signal_tag_mgmt ) // o, `TAG_MGMT_SIGNAL_W + /* -------APB reated signal{end}------- */ +`endif + +`ifdef SIMULATION + /* ------- Debug interface {begin}------- */ + /* | reserved | tag_num | chnl_num | valid | + * | 255:17 | 16:9 | 8:1 | 0 | + */ + ,.debug ( debug_tag ) + /* ------- Debug interface {end}------- */ +`endif +); + +read_response #( + +) read_response ( + + .dma_clk ( dma_clk ), // i, 1 + .rst_n ( rst_n ), // i, 1 + .init_done ( init_done_rd_rsp ), // o, 1 + + /* -------axis read response interface{begin}------- */ + /* AXI-Stream read response tuser, interact with read response distributor. + * Only valid in first beat of a packet + * | Reserved | REQ CPL | Tag | address | Reserved | DW length | first BE | last BE | + * | 119:105 | 104 | 103:96 | 95:32 | 31:19 | 18:8 | 7:4 | 3:0 | + */ + .axis_rd_rsp_tvalid ( axis_rd_rsp_tvalid ), // i, 1 + .axis_rd_rsp_tlast ( axis_rd_rsp_tlast ), // i, 1 + .axis_rd_rsp_tdata ( axis_rd_rsp_tdata ), // i, `DMA_DATA_W + .axis_rd_rsp_tuser ( axis_rd_rsp_tuser ), // i, `AXIS_TUSER_W + .axis_rd_rsp_tkeep ( axis_rd_rsp_tkeep ), // i, `DMA_KEEP_W + .axis_rd_rsp_tready ( axis_rd_rsp_tready ), // o, 1 + /* -------axis read response interface{end}------- */ + + /* -------tag release{begin}------- */ + // Note that only one channel is allowed to assert at the same time + .tag_rrsp_ready ( tag_rrsp_ready ), // o, `DMA_RD_CHNL_NUM * 1 + .tag_rrsp_last ( tag_rrsp_last ), // i, `DMA_RD_CHNL_NUM * 1 + .tag_rrsp_sz ( tag_rrsp_sz ), // i, `DMA_RD_CHNL_NUM * `DW_LEN_WIDTH + .tag_rrsp_misc ( tag_rrsp_misc ), // i, `DMA_RD_CHNL_NUM * `TAG_MISC ; Including addr && dw empty info + .tag_rrsp_tag ( tag_rrsp_tag ), // i, `DMA_RD_CHNL_NUM * `TAG_NUM_LOG + .tag_rrsp_valid ( tag_rrsp_valid ), // i, `DMA_RD_CHNL_NUM * 1 + /* -------tag release{end}------- */ + + /* ------- Read Response to RDMA{begin} ------- */ + /* dma_*_head + * | emit | chnl_num | Reserved | address | Reserved | Byte length | + * | 127 | 126:120 | 119:96 | 95:32 | 31:13 | 12:0 | + */ + .sub_req_rsp_valid ( rd_rsp_demux_valid ), // o, 1 + .sub_req_rsp_last ( rd_rsp_demux_last ), // o, 1 + .sub_req_rsp_head ( rd_rsp_demux_head ), // o, `DMA_HEAD_W + .sub_req_rsp_data ( rd_rsp_demux_data ), // o, `DMA_DATA_W + .sub_req_rsp_ready ( rd_rsp_demux_ready ), // i, 1 + /* ------- Read Response to RDMA{end} ------- */ + + /* --------chnl_stall{begin}-------- */ + /* Indicate that the rsp chnl is available. + * This signal is deasserted when : + * 1. rsp output chnl signl dma_rd_rsp_ready is deasserted; && + * 2. There is (part of) rsp pkt in sub_req_rsp_concat module. + * In this way, + */ + .chnl_avail ( is_rsp_chnl_avail ) // i, `DMA_RD_CHNL_NUM; + /* --------chnl_stall{end}-------- */ + +`ifdef PCIEI_APB_DBG + /* -------APB reated signal{begin}------- */ + ,.rw_data ( rw_data_rsp ) // i, `SRAM_RW_DATA_W*2 + ,.dbg_sel ( dbg_sel_rd_rsp ) // i, 32 + ,.dbg_bus ( dbg_bus_rd_rsp ) // o, 32 + /* -------APB reated signal{end}------- */ +`endif +); + +/* -------output reg{begin}------- */ +st_reg #( + .TUSER_WIDTH ( `DMA_HEAD_W ), + .TDATA_WIDTH ( `DMA_DATA_W ), + .MODE( 1 ) +) out_st_reg ( + .clk ( dma_clk ), // i, 1 + .rst_n ( rst_n ), // i, 1 + + /* -------input axis-like interface{begin}------- */ + .axis_tvalid ( rd_rsp_demux_valid ), // i, 1 + .axis_tlast ( rd_rsp_demux_last ), // i, 1 + .axis_tuser ( rd_rsp_demux_head ), // i, TUSER_WIDTH + .axis_tdata ( rd_rsp_demux_data ), // i, TDATA_WIDTH + .axis_tready ( rd_rsp_demux_ready ), // o, 1 + /* -------input axis-like interface{end}------- */ + + /* -------output in_reg inteface{begin}------- */ + .axis_reg_tvalid ( st_rd_rsp_demux_valid ), // o, 1 + .axis_reg_tlast ( st_rd_rsp_demux_last ), // o, 1 + .axis_reg_tuser ( st_rd_rsp_demux_head ), // o, TUSER_WIDTH + .axis_reg_tdata ( st_rd_rsp_demux_data ), // o, TDATA_WIDTH + .axis_reg_tready ( st_rd_rsp_demux_ready ) // i, 1 + /* -------output in_reg inteface{end}------- */ +); +/* -------output reg{end}------- */ + +dma_demux #( + .CHANNEL_NUM ( `DMA_RD_CHNL_NUM ) +) dma_demux ( + .clk ( dma_clk ), // i, 1 + .rst_n ( rst_n ), // i, 1 + + .nxt_demux_vld ( rd_rsp_demux_valid ), // i, 1 + .nxt_demux_sel ( {1'd0, rd_rsp_demux_head[126:120]} ), // i, 8 + + /* --------DMA Write Request interface{begin}-------- */ + /* dma_*_head + * | emit | chnl_num | Reserved | address | Reserved | Byte length | + * | 127 | 126:120 | 119:96 | 95:32 | 31:13 | 12:0 | + */ + .s_axis_req_valid ( st_rd_rsp_demux_valid ), // i, 1 + .s_axis_req_last ( st_rd_rsp_demux_last ), // i, 1 + .s_axis_req_head ( st_rd_rsp_demux_head ), // i, `DMA_HEAD_W + .s_axis_req_data ( st_rd_rsp_demux_data ), // i, `DMA_DATA_W + .s_axis_req_ready ( st_rd_rsp_demux_ready ), // o, 1 + + /* dma_*_head + * | emit | chnl_num | Reserved | address | Reserved | Byte length | + * | 127 | 126:120 | 119:96 | 95:32 | 31:13 | 12:0 | + */ + .m_axis_req_valid ( rd_rsp_concat_valid ), // o, CHANNEL_NUM * 1 + .m_axis_req_last ( rd_rsp_concat_last ), // o, CHANNEL_NUM * 1 + .m_axis_req_head ( rd_rsp_concat_head ), // o, CHANNEL_NUM * `DMA_HEAD_W + .m_axis_req_data ( rd_rsp_concat_data ), // o, CHANNEL_NUM * `DMA_DATA_W + .m_axis_req_ready ( rd_rsp_concat_ready ) // i, CHANNEL_NUM * 1 + /* --------DMA Write Request interface{end}-------- */ + +`ifdef PCIEI_APB_DBG + /* -------APB reated signal{begin}------- */ + ,.dbg_signal ( dbg_signal_dma_demux ) // o, `DMA_DEMUX_SIGNAL_W + /* -------APB reated signal{end}------- */ +`endif +); + +generate +for (i = 0; i < `DMA_RD_CHNL_NUM; i = i + 1) begin:SUB_REQ_CONCAT + + /* -------Sub-req rsp concat{begin}------- */ + sub_req_rsp_concat #( + + ) sub_req_rsp_concat ( + .dma_clk ( dma_clk ), // i, 1 + .rst_n ( rst_n ), // i, 1 + + /* -------response emission{begin}------- */ + .emit ( rd_rsp_concat_head[(i + 1) * `DMA_HEAD_W - 1 : i * `DMA_HEAD_W + `DMA_HEAD_W - 1] ), // i, 1 ; high active + /* -------response emission{end}------- */ + + /* ------- Read Response to RDMA{begin} ------- */ + /* dma_*_head + * | emit | chnl_num | Reserved | address | Reserved | Byte length | + * | 127 | 126:120 | 119:96 | 95:32 | 31:13 | 12:0 | + */ + .rd_sub_req_rsp_valid ( rd_rsp_concat_valid[(i + 1) * 1 - 1 : i * 1 ] ), // i, 1 + .rd_sub_req_rsp_last ( rd_rsp_concat_last [(i + 1) * 1 - 1 : i * 1 ] ), // i, 1 + .rd_sub_req_rsp_head ( rd_rsp_concat_head [(i + 1) * `DMA_HEAD_W - 1 : i * `DMA_HEAD_W] ), // i, `DMA_HEAD_W + .rd_sub_req_rsp_data ( rd_rsp_concat_data [(i + 1) * `DMA_DATA_W - 1 : i * `DMA_DATA_W] ), // i, `DMA_DATA_W + .rd_sub_req_rsp_ready ( rd_rsp_concat_ready[(i + 1) * 1 - 1 : i * 1 ] ), // o, 1 + + .is_avail ( is_rsp_chnl_avail[(i + 1) * 1 - 1 : i * 1 ] ), // o, 1 + /* ------- Read Response to RDMA{end} ------- */ + + /* ------- Read Response to RDMA{begin} ------- */ + /* *_head + * | Reserved | address | Reserved | Byte length | + * | 127:96 | 95:32 | 31:13 | 12:0 | + */ + .rd_rsp_valid ( dma_rd_rsp_valid [(i + 1) * 1 - 1 : i * 1 ] ), // o, 1 + .rd_rsp_last ( dma_rd_rsp_last [(i + 1) * 1 - 1 : i * 1 ] ), // o, 1 + .rd_rsp_head ( dma_rd_rsp_head [(i + 1) * `DMA_HEAD_W - 1 : i * `DMA_HEAD_W] ), // o, `DMA_HEAD_W + .rd_rsp_data ( dma_rd_rsp_data [(i + 1) * `DMA_DATA_W - 1 : i * `DMA_DATA_W] ), // o, `DMA_DATA_W + .rd_rsp_ready ( dma_rd_rsp_ready [(i + 1) * 1 - 1 : i * 1 ] ), // i, 1 + /* ------- Read Response to RDMA{end} ------- */ + + /* -------PCIe fragment property{begin}------- */ + /* This signal indicates the (max payload size & max read request size) agreed in the communication + * 3'b000 -- 128 B + * 3'b001 -- 256 B + * 3'b010 -- 512 B + * 3'b011 -- 1024B + * 3'b100 -- 2048B + * 3'b101 -- 4096B + */ + .max_pyld_sz ( max_pyld_sz ), // i, 3 + .max_rd_req_sz ( max_rd_req_sz ) // i, 3 + /* -------PCIe fragment property{end}------- */ + + `ifdef PCIEI_APB_DBG + /* -------APB reated signal{begin}------- */ + ,.rw_data ( rw_data_concat[(i+1)*`SRAM_RW_DATA_W-1:i*`SRAM_RW_DATA_W] ) // i, `SRAM_RW_DATA_W + ,.dbg_signal ( dbg_signal_rsp_concat[(i+1)*`RSP_CONCAT_SIGNAL_W-1:i*`RSP_CONCAT_SIGNAL_W] ) // o, `RSP_CONCAT_SIGNAL_W + /* -------APB reated signal{end}------- */ + `endif + ); + /* -------Sub-req rsp concat{end}------- */ + +end +endgenerate + +endmodule diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/DMA/DMA_Read/read_request.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/DMA/DMA_Read/read_request.v new file mode 100644 index 0000000000000000000000000000000000000000..a9f912d26fce1749db2a5fff7fed0ebc35957f72 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/DMA/DMA_Read/read_request.v @@ -0,0 +1,306 @@ +`timescale 1ns / 100ps +//************************************************************************* +// > File Name: read_request.v +// > Author : Kangning +// > Date : 2022-06-29 +// > Note : read_request, used to generate read request. +// > Note the request must aligned by 4KB. +// > V1.1 -- 2020-09-24: Add support for various Max_Read_Request_Size +// > V1.2 -- 2022-06-29: Add chnl_num field to store +//************************************************************************* + +//`include "../lib/global_include_h.v" +//`include "../lib/dma_def_h.v" + +module read_request #( + +) ( + input wire dma_clk, // i, 1 + input wire rst_n , // i, 1 + + /* ------- Read Request From RDMA{begin} ------- */ + /* dma_*_head, valid only in first beat of a packet + * | chnl_num | Reserved | address | Reserved | Byte length | + * | 127:120 | 119:96 | 95:32 | 31:13 | 12:0 | + */ + output wire rd_req_ready, // o, 1 + input wire [`DMA_HEAD_W-1:0] rd_req_head , // i, `DMA_HEAD_W + input wire rd_req_valid, // i, 1 + /* ------- Read Request From RDMA{end} ------- */ + + /* -------axis read request interface{begin}------- */ + /* AXI-Stream read request tuser, every read request contains only one beat. + * | chnl_num |last_sub_req | Reserved | REQ_TYPE |Tag(inv)| address | Reserved | DW length | first BE | last BE | + * | 127:120 | 119 | 118:108 | 107:104 | 103:96 | 95:32 | 31:19 | 18:8 | 7:4 | 3:0 | + */ + output wire axis_rd_request_tvalid , // o, 1 + output wire axis_rd_request_tlast , // o, 1 + output wire [`DMA_DATA_W -1:0] axis_rd_request_tdata , // o, `DMA_DATA_W + output wire [`AXIS_TUSER_W-1:0] axis_rd_request_tuser , // o, `AXIS_TUSER_W + output wire [`DMA_KEEP_W -1:0] axis_rd_request_tkeep , // o, `DMA_KEEP_W + input wire axis_rd_request_tready , // i, 1 + /* -------axis read request interface{end}------- */ + + /* --------read request blocking detection{begin}-------- */ + input wire chnl_avail, // i, 1 + input wire chnl_valid, // i, 1 + /* --------read request blocking detection{end}-------- */ + + /* -------PCIe fragment property{begin}------- */ + /* This signal indicates the (max payload size & max read request size) agreed in the communication + * 3'b000 -- 128 B + * 3'b001 -- 256 B + * 3'b010 -- 512 B + * 3'b011 -- 1024B + * 3'b100 -- 2048B + * 3'b101 -- 4096B + */ + input wire [2:0] max_pyld_sz , + input wire [2:0] max_rd_req_sz // max read request size + /* -------PCIe fragment property{end}------- */ + +`ifdef PCIEI_APB_DBG + /* -------APB reated signal{begin}------- */ + ,output wire [`RD_REQ_SIGNAL_W-1:0] dbg_signal // o, `RD_REQ_SIGNAL_W + /* -------APB reated signal{end}------- */ +`endif +); + +/* -------State relevant in FSM{begin}------- */ +localparam IDLE = 3'b001, // When there's incomming read req, store the req, and jump to GET_TAG. + GET_TAG = 3'b010, // Jump to FORWARD directly, we do not get tag at this time. + FORWARD = 3'b100; // Forward the read request(only one beat). If there is other requests + // for the dma rd req, jump to GET_TAG. Or jump to IDLE to end tx of the + // dma rd req. + +reg [2:0] cur_state; +reg [2:0] nxt_state; + + +wire is_idle, is_get_tag, is_forward; +wire j_idle; + +reg [`DMA_HEAD_W-1:0] reg_head; +/* -------State relevant in FSM{end}------- */ + +/* -------Head decode{begin}------- */ +// relate to output +wire [`DMA_LEN_WIDTH -1:0] byte_len_align; +wire [`DMA_ADDR_WIDTH-1:0] addr_unalign; +wire [8 -1:0] chnl_num; + + +wire [`DMA_ADDR_WIDTH-1:0] addr_align; +wire [`DW_LEN_WIDTH -1:0] dw_len ; +wire [`FIRST_BE_WIDTH-1:0] first_be ; +wire [`LAST_BE_WIDTH -1:0] last_be ; + +/* -------Head decode{end}------- */ + +/* -------Read request fragment{begin}------- */ +// fragment info +wire [`DW_LEN_WIDTH-1:0] max_rd_req_dw; // The maximum read request in dw unit +reg [`DW_LEN_WIDTH-1:0] dw_sent ; // The number of dw read request has been sent in a dma read request +wire [`DW_LEN_WIDTH-1:0] dw_req ; // read request size of a sub request +wire is_only_req ; +wire is_first_req ; +wire is_middle_req; +wire is_last_req ; +wire has_rd_req ; // There's still has read request to be sent in the dma rd request + + +// axis tuser field +wire [`TAG_WIDTH+`TAG_EMPTY-1:0] tag ; +wire [`DMA_ADDR_WIDTH -1:0] axis_addr_align; +wire [`DW_LEN_WIDTH -1:0] axis_dw_len ; +wire [`FIRST_BE_WIDTH -1:0] axis_first_be ; +wire [`LAST_BE_WIDTH -1:0] axis_last_be ; +/* -------Read Request Fragment{end}------- */ + +/* --------read request blocking detection{begin}-------- */ +reg chnl_avail_reg; +reg chnl_valid_reg; +wire is_chnl_blocked; +wire is_chnl_avail; +reg is_nxt_req_blocked; +/* --------read request blocking detection{end}-------- */ + +//--------------------------------------------------------------------------------------------------------------------------- + +`ifdef PCIEI_APB_DBG +/* -------APB reated signal{begin}------- */ +assign dbg_signal = { // 440 + cur_state, nxt_state, // 6 + is_idle, is_get_tag, is_forward, // 3 + j_idle, // 1 + reg_head, // 128 + byte_len_align, addr_unalign, chnl_num, // 85 + addr_align, dw_len, first_be, last_be, // 83 + max_rd_req_dw, dw_sent, dw_req, is_only_req, is_first_req, is_middle_req, is_last_req, has_rd_req, // 38 + tag, axis_addr_align, axis_dw_len, axis_first_be, axis_last_be, // 91 + chnl_avail_reg, chnl_valid_reg, is_chnl_blocked, is_chnl_avail, is_nxt_req_blocked // 5 +}; +/* -------APB reated signal{end}------- */ +`endif + +/* --------read request blocking detection{begin}-------- */ +assign is_chnl_avail = (~is_chnl_blocked) | (~is_nxt_req_blocked); +assign is_chnl_blocked = chnl_valid_reg & (!chnl_avail_reg); +always @(posedge dma_clk, negedge rst_n) begin + if (~rst_n) begin + chnl_avail_reg <= `TD 0; + chnl_valid_reg <= `TD 0; + end + else begin + chnl_avail_reg <= `TD chnl_avail; + chnl_valid_reg <= `TD chnl_valid; + end +end + +always @(posedge dma_clk, negedge rst_n) begin + if (~rst_n) begin + is_nxt_req_blocked <= `TD 1'b0; + end + else if (!is_chnl_blocked) begin + is_nxt_req_blocked <= `TD 1'b0; + end + else if (is_chnl_blocked & axis_rd_request_tvalid & axis_rd_request_tready) begin + is_nxt_req_blocked <= `TD 1'b1; + end +end +/* --------read request blocking detection{end}-------- */ + +/* -------Head decode{begin}------- */ +// Head storage +always @(posedge dma_clk, negedge rst_n) begin + if (~rst_n) begin + reg_head <= `TD 0; + end + else if (is_idle && rd_req_valid && rd_req_ready) begin + reg_head <= `TD rd_req_head; + end + else if (j_idle) begin + reg_head <= `TD 0; + end +end + +// Head decode +assign chnl_num = reg_head[127:120]; +assign byte_len_align = reg_head[12:0] + addr_unalign[1:0]; +assign addr_unalign = reg_head[95:32]; +assign addr_align = {addr_unalign[63:2], 2'd0}; +assign dw_len = (byte_len_align>>2) + |byte_len_align[1:0]; +assign first_be = ({4{addr_unalign[1:0] == 2'b00}} & 4'b1111) | + ({4{addr_unalign[1:0] == 2'b01}} & 4'b1110) | + ({4{addr_unalign[1:0] == 2'b10}} & 4'b1100) | + ({4{addr_unalign[1:0] == 2'b11}} & 4'b1000); +assign last_be = ({4{byte_len_align[1:0] == 2'b00}} & 4'b1111) | + ({4{byte_len_align[1:0] == 2'b01}} & 4'b0001) | + ({4{byte_len_align[1:0] == 2'b10}} & 4'b0011) | + ({4{byte_len_align[1:0] == 2'b11}} & 4'b0111); +/* -------Head decode{end}------- */ + +/* -------Read request fragment{begin}------- */ +// fragment info +assign max_rd_req_dw = (11'd1 << (5 + max_rd_req_sz)); +assign dw_req = dw_len - dw_sent; +assign is_only_req = (is_get_tag | is_forward) & (max_rd_req_dw >= dw_len); +assign is_first_req = (is_get_tag | is_forward) & (max_rd_req_dw < dw_len) & (dw_sent == 0); +assign is_middle_req = (is_get_tag | is_forward) & (max_rd_req_dw < dw_req) & (!is_first_req); +assign is_last_req = (is_get_tag | is_forward) & (max_rd_req_dw >= dw_req) & (!is_only_req); +assign has_rd_req = is_first_req | is_middle_req; +always @(posedge dma_clk, negedge rst_n) begin + if (~rst_n) begin + dw_sent <= `TD 0; + end + else if (is_forward & axis_rd_request_tvalid & axis_rd_request_tready & has_rd_req) begin + dw_sent <= `TD dw_sent + max_rd_req_dw; + end + else if (j_idle) begin + dw_sent <= `TD 0; + end +end + + +// axis tuser field +assign tag = {`TAG_EMPTY+`TAG_WIDTH{1'd0}}; +assign axis_addr_align = addr_align + (dw_sent << 2); +assign axis_dw_len = ({`DW_LEN_WIDTH{is_only_req }} & dw_len ) | + ({`DW_LEN_WIDTH{is_first_req }} & max_rd_req_dw) | + ({`DW_LEN_WIDTH{is_middle_req}} & max_rd_req_dw) | + ({`DW_LEN_WIDTH{is_last_req }} & dw_req ); +assign axis_first_be = (is_only_req & (dw_req == 1)) ? (first_be & last_be) : + (is_last_req & (dw_req == 1)) ? last_be : + (is_only_req | is_first_req ) ? first_be : 4'b1111; + +assign axis_last_be = (is_only_req & (dw_req == 1)) ? 4'b0000 : + (is_last_req & (dw_req == 1)) ? 4'b0000 : + (is_only_req | is_last_req ) ? last_be : 4'b1111; +/* -------Read Request Fragment{end}------- */ + +/* -------{Read Request FSM}begin------- */ +/******************** Stage 1: State Register **********************/ +assign is_idle = (cur_state == IDLE ); +assign is_get_tag = (cur_state == GET_TAG); +assign is_forward = (cur_state == FORWARD); +assign j_idle = (cur_state == FORWARD) & axis_rd_request_tvalid & axis_rd_request_tready & !has_rd_req; + +always @(posedge dma_clk, negedge rst_n) begin + if(~rst_n) + cur_state <= `TD IDLE; + else + cur_state <= `TD nxt_state; +end + +/******************** Stage 2: State Transition **********************/ + +always @(*) begin + case(cur_state) + IDLE: begin + if (rd_req_valid & rd_req_ready) begin + nxt_state = GET_TAG; + end + else begin + nxt_state = IDLE; + end + end + GET_TAG: begin + nxt_state = FORWARD; + end + FORWARD: begin + if (axis_rd_request_tvalid & axis_rd_request_tready & has_rd_req) begin + nxt_state = GET_TAG; + end + else if (axis_rd_request_tvalid & axis_rd_request_tready & !has_rd_req) begin + nxt_state = IDLE; + end + else begin + nxt_state = FORWARD; + end + end + default: begin + nxt_state = IDLE; + end + endcase +end +/******************** Stage 3: Output **********************/ +// The module will not receive read req from the channel +// if the channel is blocked. +assign rd_req_ready = is_idle & is_chnl_avail; + +/* AXI-Stream read request tuser, every read request contains only one beat. + * | chnl_num |last_sub_req | Reserved | REQ_TYPE |Tag(inv)| address | Reserved | DW length | first BE | last BE | + * | 127:120 | 119 | 118:108 | 107:104 | 103:96 | 95:32 | 31:19 | 18:8 | 7:4 | 3:0 | + */ +// The module will not output sub_req if the channel id blocked +assign axis_rd_request_tvalid = is_forward & is_chnl_avail; +assign axis_rd_request_tlast = is_forward; +assign axis_rd_request_tdata = {`DMA_DATA_W{1'd0}}; +assign axis_rd_request_tuser = is_forward ? {chnl_num, !has_rd_req, 11'd0, `DMA_READ_REQ, tag, axis_addr_align, {24-`DW_LEN_WIDTH{1'd0}}, + axis_dw_len, axis_first_be, axis_last_be} : 0; +assign axis_rd_request_tkeep = {`DMA_KEEP_W{1'd0}}; + +/* -------{Read Request FSM}end------- */ + + +endmodule diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/DMA/DMA_Read/read_response.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/DMA/DMA_Read/read_response.v new file mode 100644 index 0000000000000000000000000000000000000000..9bcf6b0df29078319a418ec4853878009956d7f3 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/DMA/DMA_Read/read_response.v @@ -0,0 +1,351 @@ +`timescale 1ns / 100ps +//************************************************************************* +// > File Name: read_response.v +// > Author : Kangning +// > Date : V1.0 -- 2020-08-27 +// > Note : read_response, used to get read response from PCIe, and +// > reorder the out-of-order packet. +// > V1.1 -- 2020-09-27: Add support for sub-request recombination +// > and response recombination +// > V1.2 -- 2021-04-14: Reconstruct the file with the following structure. +// > |------------|------------------|------------|------------| +// > | input axis | transfrom to | FSM | rsp data | +// > | data | dma_head type | processing | reassemble | +// > | | (dw dealignment) | (reorder) | | +// > |------------|------------------|------------|------------| +// > V1.3 -- 2022-06-29: Rebuild the read response channel. +// > |------------|------------------|------------|-------------| +// > | input axis | transfrom to | push to | ifc warpper | +// > | data | dma_head type | reorder | sub_req_rsp | +// > | | (dw dealignment) | buffer | | +// > |------------|------------------|------------|-------------| +//************************************************************************* + +//`include "../lib/global_include_h.v" +//`include "../lib/dma_def_h.v" + +module read_response #( + +) ( + input wire dma_clk, // i, 1 + input wire rst_n , // i, 1 + output wire init_done, // o, 1 + + /* -------axis read response interface{begin}------- */ + /* AXI-Stream read response tuser, interact with read response distributor. + * Only valid in first beat of a packet + * | Reserved | REQ CPL | Tag | address | Reserved | DW length | first BE | last BE | + * | 119:105 | 104 | 103:96 | 95:32 | 31:19 | 18:8 | 7:4 | 3:0 | + */ + input wire axis_rd_rsp_tvalid, // i, 1 + input wire axis_rd_rsp_tlast , // i, 1 + input wire [`DMA_DATA_W -1:0] axis_rd_rsp_tdata , // i, `DMA_DATA_W + input wire [`AXIS_TUSER_W-1:0] axis_rd_rsp_tuser , // i, `AXIS_TUSER_W + input wire [`DMA_KEEP_W -1:0] axis_rd_rsp_tkeep , // i, `DMA_KEEP_W + output wire axis_rd_rsp_tready, // o, 1 + /* -------axis read response interface{end}------- */ + + /* -------tag release{begin}------- */ + // Note that only one channel is allowed to assert at the same time + output wire [`DMA_RD_CHNL_NUM * 1 - 1 : 0] tag_rrsp_ready, // o, 1 + input wire [`DMA_RD_CHNL_NUM * 1 - 1 : 0] tag_rrsp_last , // i, 1 + input wire [`DMA_RD_CHNL_NUM * `DW_LEN_WIDTH - 1 : 0] tag_rrsp_sz , // i, `DW_LEN_WIDTH + input wire [`DMA_RD_CHNL_NUM * `TAG_MISC - 1 : 0] tag_rrsp_misc , // i, `TAG_MISC ; Including addr && dw empty info + input wire [`DMA_RD_CHNL_NUM * `TAG_NUM_LOG - 1 : 0] tag_rrsp_tag , // i, `TAG_NUM_LOG + input wire [`DMA_RD_CHNL_NUM * 1 - 1 : 0] tag_rrsp_valid, // i, 1 + /* -------tag release{end}------- */ + + /* ------- Read sub-req response{begin} ------- */ + /* dma_*_head + * | emit | chnl_num | Reserved | address | Reserved | Byte length | + * | 127 | 126:120 | 119:96 | 95:32 | 31:13 | 12:0 | + */ + output wire sub_req_rsp_valid, // o, 1 + output wire sub_req_rsp_last , // o, 1 + output wire [`DMA_DATA_W-1:0] sub_req_rsp_data , // o, `DMA_DATA_W + output wire [`DMA_HEAD_W-1:0] sub_req_rsp_head , // o, `DMA_HEAD_W + input wire sub_req_rsp_ready, // i, 1 + /* ------- Read sub-req response{end} ------- */ + + /* --------chnl_stall{begin}-------- */ + input wire [`DMA_RD_CHNL_NUM - 1 : 0] chnl_avail // i, `DMA_RD_CHNL_NUM + /* --------chnl_stall{end}-------- */ + +`ifdef PCIEI_APB_DBG + /* -------APB reated signal{begin}------- */ + ,input wire [`SRAM_RW_DATA_W*2-1:0] rw_data // i, `SRAM_RW_DATA_W*2 + ,input wire [31:0] dbg_sel // i, 32 + ,output wire [31:0] dbg_bus // o, 32 + /* -------APB reated signal{end}------- */ +`endif +); + +/* -------tag release{begin}------- */ +wire nxt_match_ready; +wire nxt_match_last ; +wire [`DW_LEN_WIDTH-1:0] nxt_match_sz ; +wire [`TAG_MISC -1:0] nxt_match_misc ; +wire [8 -1:0] nxt_match_chnl ; +wire [`TAG_NUM_LOG -1:0] nxt_match_tag ; +wire nxt_match_valid; + +wire is_begin_ft; // begin fetch pkt in reorder buffer and forward it to the concat module + +// wire st_nxt_match_ready; +// wire st_nxt_match_last ; +// wire [`DW_LEN_WIDTH-1:0] st_nxt_match_sz ; +// wire [8 -1:0] st_nxt_match_chnl ; +// wire [`TAG_NUM_LOG -1:0] st_nxt_match_tag ; +// wire st_nxt_match_valid; +/* -------tag release{end}------- */ + +/* ------- Related to Reorder Buffer{begin} ------- */ +wire st_rd_rsp_wen ; +wire st_rd_rsp_last; +wire st_rd_rsp_eop ; +wire [`DMA_HEAD_W -1:0] st_rd_rsp_head; +wire [`DW_LEN_WIDTH-1:0] st_rd_rsp_dlen; +wire [`TAG_NUM_LOG -1:0] st_rd_rsp_tag ; +wire [`DMA_DATA_W -1:0] st_rd_rsp_data; +wire st_rd_rsp_rdy ; + +wire ft_rd_rsp_ren ; +wire [`TAG_NUM_LOG-1:0] ft_rd_rsp_tag ; +wire [`DMA_HEAD_W -1:0] ft_rd_rsp_head; +wire [`DMA_DATA_W -1:0] ft_rd_rsp_data; +wire ft_rd_rsp_last; +wire ft_rd_rsp_vld ; +/* ------- Related to Reorder Buffer{end} ------- */ + +`ifdef PCIEI_APB_DBG +/* -------APB reated signal{begin}------- */ +wire [32-1:0] dbg_sel_rd_rsp_top, dbg_sel_rsp_dealign, dbg_sel_reorder_buf, dbg_sel_tag_matching, dbg_sel_wrapper; +wire [32-1:0] dbg_bus_rd_rsp_top, dbg_bus_rsp_dealign, dbg_bus_reorder_buf, dbg_bus_tag_matching, dbg_bus_wrapper; + +wire [`RD_RSP_TOP_SIGNAL_W -1:0] dbg_signal_rd_rsp_top; +wire [`RSP_DEALIGN_SIGNAL_W -1:0] dbg_signal_rsp_dealign; +/* -------APB reated signal{end}------- */ +`endif + +//--------------------------------------------------------------------------------------------------------------------------- + +`ifdef PCIEI_APB_DBG +/* -------APB reated signal{begin}------- */ +assign dbg_bus = (`RD_RSP_TOP_DBG_B <= dbg_sel && dbg_sel < `RSP_DEALIGN_DBG_B ) ? dbg_bus_rd_rsp_top : + (`RSP_DEALIGN_DBG_B <= dbg_sel && dbg_sel < `REORDER_BUF_DBG_B ) ? dbg_bus_rsp_dealign : + (`REORDER_BUF_DBG_B <= dbg_sel && dbg_sel < `TAG_MATCHING_DBG_B) ? dbg_bus_reorder_buf : + (`TAG_MATCHING_DBG_B <= dbg_sel && dbg_sel < `WRAPPER_DBG_B ) ? dbg_bus_tag_matching : + (`WRAPPER_DBG_B <= dbg_sel && dbg_sel < `RD_RSP_DBG_SIZE ) ? dbg_bus_wrapper : 32'd0; + +assign dbg_sel_rd_rsp_top = (`RD_RSP_TOP_DBG_B <= dbg_sel && dbg_sel < `RSP_DEALIGN_DBG_B ) ? (dbg_sel - `RD_RSP_TOP_DBG_B ) : 32'd0; +assign dbg_sel_rsp_dealign = (`RSP_DEALIGN_DBG_B <= dbg_sel && dbg_sel < `REORDER_BUF_DBG_B ) ? (dbg_sel - `RSP_DEALIGN_DBG_B ) : 32'd0; +assign dbg_sel_reorder_buf = (`REORDER_BUF_DBG_B <= dbg_sel && dbg_sel < `TAG_MATCHING_DBG_B) ? (dbg_sel - `REORDER_BUF_DBG_B ) : 32'd0; +assign dbg_sel_tag_matching = (`TAG_MATCHING_DBG_B <= dbg_sel && dbg_sel < `WRAPPER_DBG_B ) ? (dbg_sel - `TAG_MATCHING_DBG_B) : 32'd0; +assign dbg_sel_wrapper = (`WRAPPER_DBG_B <= dbg_sel && dbg_sel < `RD_RSP_DBG_SIZE ) ? (dbg_sel - `WRAPPER_DBG_B ) : 32'd0; + +// Debug bus for read rsp top +assign dbg_bus_rd_rsp_top = dbg_signal_rd_rsp_top >> {dbg_sel_rd_rsp_top, 5'd0}; + +// Debug bus for rrsp dealign +assign dbg_bus_rsp_dealign = dbg_signal_rsp_dealign >> {dbg_sel_rsp_dealign, 5'd0}; + +assign dbg_signal_rd_rsp_top = { // 827 + nxt_match_ready, nxt_match_last, nxt_match_sz, nxt_match_misc, nxt_match_chnl, nxt_match_tag , nxt_match_valid, // 28 + is_begin_ft, // 1 + st_rd_rsp_wen , st_rd_rsp_last, st_rd_rsp_eop , st_rd_rsp_head, st_rd_rsp_dlen, st_rd_rsp_tag , st_rd_rsp_data, st_rd_rsp_rdy, // 405 + ft_rd_rsp_ren , ft_rd_rsp_tag, ft_rd_rsp_head, ft_rd_rsp_data, ft_rd_rsp_last, ft_rd_rsp_vld // 393 +}; +/* -------APB reated signal{end}------- */ +`endif + + +/* -------Double word dealignment{begin}------- */ +rrsp_dealign #( + +) rrsp_dealign ( + .dma_clk ( dma_clk ), // i, 1 + .rst_n ( rst_n ), // i, 1 + + + /* -------axis read response interface{begin}------- */ + /* AXI-Stream read response tuser, interact with read response distributor. + * Only valid in first beat of a packet + * | Reserved | REQ CPL | Tag | address | Reserved | DW length | first BE | last BE | + * | 119:105 | 104 | 103:96 | 95:32 | 31:19 | 18:8 | 7:4 | 3:0 | + */ + .axis_rd_rsp_tvalid ( axis_rd_rsp_tvalid ), // i, 1 + .axis_rd_rsp_tlast ( axis_rd_rsp_tlast ), // i, 1 + .axis_rd_rsp_tdata ( axis_rd_rsp_tdata ), // i, `DMA_DATA_W + .axis_rd_rsp_tuser ( axis_rd_rsp_tuser ), // i, `AXIS_TUSER_W + .axis_rd_rsp_tkeep ( axis_rd_rsp_tkeep ), // i, `DMA_KEEP_W + .axis_rd_rsp_tready ( axis_rd_rsp_tready ), // o, 1 + /* -------axis read response interface{end}------- */ + + + /* ------- Read Response store to Reorder Buffer{begin} ------- */ + /* *_head (interact with module, valid only in first beat of a packet + * | Reserved | address | Reserved | Byte length | + * | 127:96 | 95:32 | 31:13 | 12:0 | + */ + .rd_rsp_dealign_valid ( st_rd_rsp_wen ), // o, 1 + .rd_rsp_dealign_last ( st_rd_rsp_last ), // o, 1 ; assert in every last beat of sub-rsp pkt + .rd_rsp_dealign_eop ( st_rd_rsp_eop ), // o, 1 ; assert when this is the last sub-rsp pkt + .rd_rsp_dealign_dlen ( st_rd_rsp_dlen ), // o, `DW_LEN_WIDTH ; part of head field in "store channel" + .rd_rsp_dealign_tag ( st_rd_rsp_tag ), // o, `TAG_NUM_LOG ; part of head field in "store channel" + .rd_rsp_dealign_head ( st_rd_rsp_head ), // o, `DMA_HEAD_W + .rd_rsp_dealign_data ( st_rd_rsp_data ), // o, `DMA_DATA_W + .rd_rsp_dealign_ready ( st_rd_rsp_rdy ) // i, 1 + /* ------- Read Response store to Reorder Buffer{end} ------- */ + +`ifdef PCIEI_APB_DBG + /* -------APB reated signal{begin}------- */ + ,.dbg_signal ( dbg_signal_rsp_dealign ) // o, `RSP_DEALIGN_SIGNAL_W + /* -------APB reated signal{end}------- */ +`endif +); +/* -------Double word dealignment{end}------- */ + +/* -------Reorder Buffer{begin}------- */ +reorder_buf #( + +) reorder_buffer ( + .dma_clk ( dma_clk ), // i, 1 + .rst_n ( rst_n ), // i, 1 + .init_done ( init_done ), // o, 1 + + /* ------- Read Response input{begin} ------- */ + /* *_head, valid only in first beat of a packet + * | Reserved | address | Reserved | Byte length | + * | 127:96 | 95:32 | 31:13 | 12:0 | + */ + .st_rd_rsp_wen ( st_rd_rsp_wen ), // i, 1 + .st_rd_rsp_last ( st_rd_rsp_last ), // i, 1 ; assert in every last beat of sub-rsp pkt + .st_rd_rsp_eop ( st_rd_rsp_eop ), // i, 1 ; assert when this is the last sub-rsp pkt + .st_rd_rsp_tag ( st_rd_rsp_tag ), // i, `TAG_NUM_LOG + .st_rd_rsp_head ( st_rd_rsp_head ), // i, `DMA_HEAD_W + .st_rd_rsp_data ( st_rd_rsp_data ), // i, `DMA_DATA_W + .st_rd_rsp_rdy ( st_rd_rsp_rdy ), // o, 1 + /* ------- Read Response input{end} ------- */ + + + /* ------- Read Response output{begin} ------- */ + /* *_head, valid only in first beat of a packet + * | Reserved | address | Reserved | Byte length | + * | 127:96 | 95:32 | 31:13 | 12:0 | + */ + .ft_rd_rsp_ren ( ft_rd_rsp_ren ), // i, 1 + .ft_rd_rsp_tag ( ft_rd_rsp_tag ), // i, `TAG_NUM_LOG + .ft_rd_rsp_head ( ft_rd_rsp_head ), // o, `DMA_HEAD_W + .ft_rd_rsp_data ( ft_rd_rsp_data ), // o, `DMA_DATA_W + .ft_rd_rsp_last ( ft_rd_rsp_last ), // o, 1 + .ft_rd_rsp_vld ( ft_rd_rsp_vld ) // o, 1 + /* ------- Read Response output{end} ------- */ + +`ifdef PCIEI_APB_DBG + /* -------APB reated signal{begin}------- */ + ,.rw_data ( rw_data ) // i, `SRAM_RW_DATA_W*2 + ,.dbg_sel ( dbg_sel_reorder_buf ) // i, 32 + ,.dbg_bus ( dbg_bus_reorder_buf ) // o, 32 + /* -------APB reated signal{end}------- */ +`endif +); +/* -------Reorder Buffer{end}------- */ + +assign is_begin_ft = ft_rd_rsp_ren; +tag_matching #( + +) tag_matching ( + + .dma_clk ( dma_clk ), // i, 1 + .rst_n ( rst_n ), // i, 1 + + /* -------tag release{begin}------- */ + // Note that only one channel is allowed to assert at the same time + .tag_rrsp_ready ( tag_rrsp_ready ), // o, `DMA_RD_CHNL_NUM * 1 + .tag_rrsp_last ( tag_rrsp_last ), // i, `DMA_RD_CHNL_NUM * 1 + .tag_rrsp_sz ( tag_rrsp_sz ), // i, `DMA_RD_CHNL_NUM * `DW_LEN_WIDTH + .tag_rrsp_misc ( tag_rrsp_misc ), // i, `DMA_RD_CHNL_NUM * `TAG_MISC ; Including addr && dw empty info + .tag_rrsp_tag ( tag_rrsp_tag ), // i, `DMA_RD_CHNL_NUM * `TAG_NUM_LOG + .tag_rrsp_valid ( tag_rrsp_valid ), // i, `DMA_RD_CHNL_NUM * 1 + /* -------tag release{end}------- */ + + /* ------- Store input{begin} ------- */ + .st_rd_rsp_wen ( st_rd_rsp_wen ), // i, 1 + .st_rd_rsp_last ( st_rd_rsp_last ), // i, 1 ; assert in every last beat of sub-rsp pkt + .st_rd_rsp_dlen ( st_rd_rsp_dlen ), // i, `DW_LEN_WIDTH ; part of head field in "store channel" + .st_rd_rsp_tag ( st_rd_rsp_tag ), // i, `TAG_NUM_LOG ; part of head field in "store channel" + .st_rd_rsp_rdy ( st_rd_rsp_rdy ), // i, 1 + /* ------- Store input{end} ------- */ + + /* --------chnl_stall{begin}-------- */ + .chnl_avail ( chnl_avail | {`DMA_RD_CHNL_NUM{is_begin_ft}} ), // i, `DMA_RD_CHNL_NUM + /* --------chnl_stall{end}-------- */ + + /* -------tag release{begin}------- */ + .nxt_match_ready ( nxt_match_ready ), // i, 1 + .nxt_match_last ( nxt_match_last ), // o, 1 + .nxt_match_sz ( nxt_match_sz ), // o, `DW_LEN_WIDTH + .nxt_match_misc ( nxt_match_misc ), // o, `TAG_MISC ; Including addr && dw empty info + .nxt_match_chnl ( nxt_match_chnl ), // o, 8 + .nxt_match_tag ( nxt_match_tag ), // o, `TAG_NUM_LOG + .nxt_match_valid ( nxt_match_valid ) // o, 1 + /* -------tag release{end}------- */ + +`ifdef PCIEI_APB_DBG + /* -------APB reated signal{begin}------- */ + ,.dbg_sel ( dbg_sel_tag_matching ) // i, 32 + ,.dbg_bus ( dbg_bus_tag_matching ) // o, 32 + /* -------APB reated signal{end}------- */ +`endif +); + +sub_req_rsp_wrapper #( + +) sub_req_rsp_wrapper ( + .dma_clk ( dma_clk ), // i, 1 + .rst_n ( rst_n ), // i, 1 + + /* ------- Read Response output{begin} ------- */ + /* *_head (interact with module, valid only in first beat of a packet + * | Reserved | address | Reserved | Byte length | + * | 127:96 | 95:32 | 31:13 | 12:0 | + */ + .ft_rd_rsp_ren ( ft_rd_rsp_ren ), // o, 1 + .ft_rd_rsp_tag ( ft_rd_rsp_tag ), // o, `TAG_NUM_LOG + .ft_rd_rsp_head ( ft_rd_rsp_head ), // i, `DMA_HEAD_W + .ft_rd_rsp_data ( ft_rd_rsp_data ), // i, `DMA_DATA_W + .ft_rd_rsp_last ( ft_rd_rsp_last ), // i, 1 + .ft_rd_rsp_vld ( ft_rd_rsp_vld ), // i, 1 + /* ------- Read Response output{end} ------- */ + + /* -------tag release{begin}------- */ + .nxt_match_ready ( nxt_match_ready ), // o, 1 + .nxt_match_last ( nxt_match_last ), // i, 1 + .nxt_match_sz ( nxt_match_sz ), // i, `DW_LEN_WIDTH + .nxt_match_misc ( nxt_match_misc ), // i, `TAG_MISC ; Including addr && dw empty info + .nxt_match_chnl ( nxt_match_chnl ), // i, 8 + .nxt_match_tag ( nxt_match_tag ), // i, `TAG_NUM_LOG + .nxt_match_valid ( nxt_match_valid ), // i, 1 + /* -------tag release{end}------- */ + + /* ------- Read sub-req response{begin} ------- */ + /* dma_*_head + * | emit | chnl_num | Reserved | address | Reserved | Byte length | + * | 127 | 126:120 | 119:96 | 95:32 | 31:13 | 12:0 | + */ + .st_sub_req_rsp_valid ( sub_req_rsp_valid ), // o, 1 + .st_sub_req_rsp_last ( sub_req_rsp_last ), // o, 1 + .st_sub_req_rsp_data ( sub_req_rsp_data ), // o, `DMA_DATA_W + .st_sub_req_rsp_head ( sub_req_rsp_head ), // o, `DMA_HEAD_W + .st_sub_req_rsp_ready ( sub_req_rsp_ready ) // i, 1 + /* ------- Read sub-req response{end} ------- */ + +`ifdef PCIEI_APB_DBG + /* -------APB reated signal{begin}------- */ + ,.dbg_sel ( dbg_sel_wrapper ) // i, 32 + ,.dbg_bus ( dbg_bus_wrapper ) // o, 32 + /* -------APB reated signal{end}------- */ +`endif +); + +endmodule diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/DMA/DMA_Read/reorder_buf.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/DMA/DMA_Read/reorder_buf.v new file mode 100644 index 0000000000000000000000000000000000000000..c714525b70c971a6f4cafafaf9444530ab24a655 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/DMA/DMA_Read/reorder_buf.v @@ -0,0 +1,220 @@ +`timescale 1ns / 100ps +//************************************************************************* +// > File Name: reorder_buf.v +// > Author : Kangning +// > Date : 2023-02-27 +// > Note : reorder_buf, which acts as a reorder buffer +//************************************************************************* + +//`include "../lib/dma_def_h.v" + +module reorder_buf #( + +) ( + input wire dma_clk , // i, 1 + input wire rst_n , // i, 1 + output wire init_done, // o, 1 + + /* ------- Reorder buf input{begin} ------- */ + /* *_head (interact with module, valid only in first beat of a packet + * | Reserved | address | Reserved | Byte length | + * | 127:96 | 95:32 | 31:13 | 12:0 | + */ + input wire st_rd_rsp_wen , // i, 1 + input wire st_rd_rsp_last, // i, 1 ; assert in every last beat of sub-rsp pkt + input wire st_rd_rsp_eop , // i, 1 ; assert when this is the last sub-rsp pkt + input wire [`TAG_NUM_LOG-1:0] st_rd_rsp_tag , // i, `TAG_NUM_LOG + input wire [`DMA_HEAD_W -1:0] st_rd_rsp_head, // i, `DMA_HEAD_W + input wire [`DMA_DATA_W -1:0] st_rd_rsp_data, // i, `DMA_DATA_W + output wire st_rd_rsp_rdy , // o, 1 + /* ------- Reorder buf input{end} ------- */ + + + /* ------- Reorder buf output{begin} ------- */ + /* *_head (interact with module, valid only in first beat of a packet + * | Reserved | address | Reserved | Byte length | + * | 127:96 | 95:32 | 31:13 | 12:0 | + */ + input wire ft_rd_rsp_ren , // i, 1 + input wire [`TAG_NUM_LOG-1:0] ft_rd_rsp_tag , // i, `TAG_NUM_LOG + output wire [`DMA_HEAD_W -1:0] ft_rd_rsp_head, // o, `DMA_HEAD_W + output wire [`DMA_DATA_W -1:0] ft_rd_rsp_data, // o, `DMA_DATA_W + output wire ft_rd_rsp_last, // o, 1 + output wire ft_rd_rsp_vld // o, 1 + /* ------- Reorder buf output{end} ------- */ + +`ifdef PCIEI_APB_DBG + /* -------APB reated signal{begin}------- */ + ,input wire [`SRAM_RW_DATA_W*2-1:0] rw_data // i, `SRAM_RW_DATA_W*2 + ,input wire [31:0] dbg_sel // i, 32 + ,output wire [31:0] dbg_bus // o, 32 + /* -------APB reated signal{end}------- */ +`endif +); + +/* ------- Reorder buf input{begin} ------- */ +/* *_head (interact with module, valid only in first beat of a packet + * | Reserved | address | Reserved | Byte length | + * | 127:96 | 95:32 | 31:13 | 12:0 | + */ +wire st_store_rd_rsp_wen ; +wire st_store_rd_rsp_last; +wire st_store_rd_rsp_eop ; +wire [`DMA_LEN_WIDTH-1:0] st_store_rd_rsp_blen; +wire [`TAG_NUM_LOG -1:0] st_store_rd_rsp_tag ; +wire [`DMA_HEAD_W -1:0] st_store_rd_rsp_head; +wire [`DMA_DATA_W -1:0] st_store_rd_rsp_data; +wire st_store_rd_rsp_rdy ; +/* ------- Reorder buf input{end} ------- */ + +wire [`DMA_LEN_WIDTH -1:0] sub_blen_total ; +wire [`DMA_LEN_WIDTH -1:0] sub_blen_left ; +reg [`DMA_LEN_WIDTH -1:0] store_trans_cnt; + + +wire store_wen ; +wire [`TAG_NUM_LOG-1:0] store_tag ; +wire store_last; +wire [`DMA_DATA_W -1:0] store_data; +wire store_rdy; + +`ifdef PCIEI_APB_DBG +/* -------APB reated signal{begin}------- */ +wire [`SRAM_RW_DATA_W-1:0] concat_rw_data; +wire [`SRAM_RW_DATA_W-1:0] tag_buf_rw_data; + +wire [`SUB_RSP_CONCAT_SIGNAL_W-1:0] dbg_signal_sub_rsp_concat; +wire [`TAG_BUF_SIGNAL_W -1:0] dbg_signal_tag_buf; +wire [`REBUF_TOP_SIGNAL_W -1:0] dbg_signal_rebuf_top; +/* -------APB reated signal{end}------- */ +`endif + +//--------------------------------------------------------------------------------------------------------------------------- + +`ifdef PCIEI_APB_DBG +/* -------APB reated signal{begin}------- */ +assign {tag_buf_rw_data, concat_rw_data} = rw_data; + +assign dbg_bus = {dbg_signal_rebuf_top, dbg_signal_sub_rsp_concat, dbg_signal_tag_buf} >> {dbg_sel, 5'd0}; + +assign dbg_signal_rebuf_top = { // 711 + st_store_rd_rsp_wen , st_store_rd_rsp_last, st_store_rd_rsp_eop , st_store_rd_rsp_blen, + st_store_rd_rsp_tag , st_store_rd_rsp_head, st_store_rd_rsp_data, st_store_rd_rsp_rdy, // 407 + + sub_blen_total , sub_blen_left , store_trans_cnt, // 39 + + store_wen , store_tag , store_last, store_data, store_rdy // 265 +}; +/* -------APB reated signal{end}------- */ +`endif + +/* -------Stream reg for st channel signal{begin}-------- */ +st_reg #( + .TUSER_WIDTH ( `TAG_NUM_LOG + `DMA_HEAD_W ), + .TDATA_WIDTH ( 1 + `DMA_DATA_W ) +) in_st_reg ( + .clk ( dma_clk ), // i, 1 + .rst_n ( rst_n ), // i, 1 + + /* -------input axis-like interface{begin}------- */ + .axis_tvalid ( st_rd_rsp_wen ), // i, 1 + .axis_tlast ( st_rd_rsp_last ), // i, 1 + .axis_tuser ( {st_rd_rsp_tag, st_rd_rsp_head} ), // i, TUSER_WIDTH + .axis_tdata ( {st_rd_rsp_eop, st_rd_rsp_data} ), // i, TDATA_WIDTH + .axis_tready ( st_rd_rsp_rdy ), // o, 1 + /* -------input axis-like interface{end}------- */ + + /* -------output inteface{begin}------- */ + .axis_reg_tvalid ( st_store_rd_rsp_wen ), // o, 1 + .axis_reg_tlast ( st_store_rd_rsp_last ), // o, 1 + .axis_reg_tuser ( {st_store_rd_rsp_tag, st_store_rd_rsp_head} ), // o, TUSER_WIDTH + .axis_reg_tdata ( {st_store_rd_rsp_eop, st_store_rd_rsp_data} ), // o, TDATA_WIDTH + .axis_reg_tready ( st_store_rd_rsp_rdy ) // i, 1 + /* -------output inteface{end}------- */ +); +/* -------Stream reg for st channel signal{end}-------- */ + +/* --------Generate byte length in every cycle{begin}-------- */ +assign st_store_rd_rsp_blen = (sub_blen_left >= `DMA_W_BCNT) ? `DMA_W_BCNT : sub_blen_left; +assign sub_blen_left = sub_blen_total - store_trans_cnt; +assign sub_blen_total = st_store_rd_rsp_head[12:0]; +always @(posedge dma_clk, negedge rst_n) begin + if (~rst_n) begin + store_trans_cnt <= `TD 0; + end + else if (st_store_rd_rsp_wen & st_store_rd_rsp_rdy & st_store_rd_rsp_last) begin + store_trans_cnt <= `TD 0; + end + else if (st_store_rd_rsp_wen & st_store_rd_rsp_rdy) begin + store_trans_cnt <= `TD store_trans_cnt + `DMA_W_BCNT; + end +end +/* --------Generate byte length in every cycle{end}-------- */ + +/* --------concat sub-rsp data{begin}-------- */ +sub_rsp_concat sub_rsp_concat ( + .dma_clk ( dma_clk ), // i, 1 + .rst_n ( rst_n ), // i, 1 + .init_done ( init_done ), // o, 1 + + /* ------- Store Interface input{begin} ------- */ + .st_rd_rsp_valid ( st_store_rd_rsp_wen ), // i, 1 + .st_rd_rsp_last ( st_store_rd_rsp_last ), // i, 1 ; assert in every last beat of sub-rsp pkt + .st_rd_rsp_eop ( st_store_rd_rsp_eop ), // i, 1 ; assert when this is the last sub-rsp pkt + .st_rd_rsp_tag ( st_store_rd_rsp_tag ), // i, `TAG_NUM_LOG + .st_rd_rsp_blen ( st_store_rd_rsp_blen ), // i, `DMA_LEN_WIDTH + .st_rd_rsp_data ( st_store_rd_rsp_data ), // i, `DMA_DATA_W + .st_rd_rsp_ready ( st_store_rd_rsp_rdy ), // o, 1 + /* ------- Store Interface input{end} ------- */ + + /* --------Store Interface Output{begin}-------- */ + .store_fifo_wen ( store_wen ), // o, 1 + .store_fifo_tag ( store_tag ), // o, `TAG_NUM_LOG + .store_fifo_last ( store_last ), // o, 1 ; assert when this is the last sub-rsp pkt + .store_fifo_data ( store_data ), // o, `DMA_DATA_W + .store_fifo_rdy ( store_rdy ) // i, 1 + /* --------Store Interface Output{end}-------- */ + +`ifdef PCIEI_APB_DBG + /* -------APB reated signal{begin}------- */ + ,.rw_data ( concat_rw_data ) // i, `SRAM_RW_DATA_W + ,.dbg_signal ( dbg_signal_sub_rsp_concat ) // o, `DATA_FIFO_SIGNAL_W + /* -------APB reated signal{end}------- */ +`endif +); +/* --------concat sub-rsp data{end}-------- */ + + +/* -------data stroage{begin}------- */ +tag_buf tag_buf ( + .dma_clk ( dma_clk ), // i, 1 + .rst_n ( rst_n ), // i, 1 + + /* -------- Store related channel {begin}-------- */ + .store_wen ( store_wen ), // i, 1 + .store_tag ( store_tag ), // i, `TAG_NUM_LOG + .store_last ( store_last ), // i, 1 ; assert when this is the last sub-rsp pkt + .store_data ( store_data ), // i, `DMA_DATA_W + .store_rdy ( store_rdy ), // o, 1 + /* -------- Store related channel {end}-------- */ + + /* -------- Fetch related channel {begin}-------- */ + .fetch_ren ( ft_rd_rsp_ren ), // i, 1 + .fetch_tag ( ft_rd_rsp_tag ), // i, `TAG_NUM_LOG + .fetch_last ( ft_rd_rsp_last ), // o, 1 ; assert when this is the last sub-rsp pkt + .fetch_data ( ft_rd_rsp_data ), // o, `DMA_DATA_W + .fetch_vld ( ft_rd_rsp_vld ) // o, 1 + /* -------- Fetch related channel {end}-------- */ + +`ifdef PCIEI_APB_DBG + /* -------APB reated signal{begin}------- */ + ,.rw_data ( tag_buf_rw_data ) // i, `SRAM_RW_DATA_W + ,.dbg_signal ( dbg_signal_tag_buf ) // o, `DATA_FIFO_SIGNAL_W + /* -------APB reated signal{end}------- */ +`endif +); +/* -------data stroage{end}------- */ + +assign ft_rd_rsp_head = {`DMA_HEAD_W{1'd0}}; + +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/DMA/DMA_Read/rrsp_dealign.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/DMA/DMA_Read/rrsp_dealign.v new file mode 100644 index 0000000000000000000000000000000000000000..58ee4129fb94c3b38791977ff64aaed4c5ae1085 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/DMA/DMA_Read/rrsp_dealign.v @@ -0,0 +1,343 @@ +`timescale 1ns / 100ps +//************************************************************************* +// > File Name: rrsp_dealign.v +// > Author : Kangning +// > Date : V1.0 -- 2021-04-14 +// > Note : double word dealignment, transfrom data from double word +// > alignment into address alignment. +// > V1.0 -- 2021-04-14: Transfrom data from double word +// > alignment into address alignment. The structure +// > is as follows: +// > ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +// > ^ ^ +// > ^ ########## ########### ^ +// > ^ # #------># tmp_reg # ########### ^ +// > ^ ------># in_reg # ###########-----># # ^ +// > ^ # # # out_reg #----> ^ +// > ^ ##########-----------------------># # ^ +// > ^ ########### ^ +// > ^ ^ +// > ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +//************************************************************************* +//`include "../lib/global_include_h.v" +//`include "../lib/dma_def_h.v" + +module rrsp_dealign #( + +) ( + input wire dma_clk, // i, 1 + input wire rst_n , // i, 1 + + + /* -------axis read response interface{begin}------- */ + /* AXI-Stream read response tuser, interact with read response distributor. + * Only valid in first beat of a packet + * | Reserved | REQ CPL | Tag | address | Reserved | DW length | first BE | last BE | + * | 119:105 | 104 | 103:96 | 95:32 | 31:19 | 18:8 | 7:4 | 3:0 | + */ + input wire axis_rd_rsp_tvalid, // i, 1 + input wire axis_rd_rsp_tlast , // i, 1 + input wire [`DMA_DATA_W -1:0] axis_rd_rsp_tdata , // i, `DMA_DATA_W + input wire [`AXIS_TUSER_W-1:0] axis_rd_rsp_tuser , // i, `AXIS_TUSER_W + input wire [`DMA_KEEP_W -1:0] axis_rd_rsp_tkeep , // i, `DMA_KEEP_W + output wire axis_rd_rsp_tready, // o, 1 + /* -------axis read response interface{end}------- */ + + + /* ------- Read Response store to Reorder Buffer{begin} ------- */ + /* *_head (interact with module, valid only in first beat of a packet + * | Reserved | address | Reserved | Byte length | + * | 127:96 | 95:32 | 31:13 | 12:0 | + */ + output wire rd_rsp_dealign_valid, // o, 1 + output wire rd_rsp_dealign_last , // o, 1 ; assert in every last beat of sub-rsp pkt + output wire rd_rsp_dealign_eop , // o, 1 ; assert when this is the last sub-rsp pkt + output wire[`DW_LEN_WIDTH-1:0] rd_rsp_dealign_dlen , // o, `DW_LEN_WIDTH + output wire[`TAG_NUM_LOG -1:0] rd_rsp_dealign_tag , // o, `TAG_NUM_LOG + output wire[`DMA_HEAD_W -1:0] rd_rsp_dealign_head , // o, `DMA_HEAD_W + output wire[`DMA_DATA_W -1:0] rd_rsp_dealign_data , // o, `DMA_DATA_W + input wire rd_rsp_dealign_ready // i, 1 + /* ------- Read Response store to Reorder Buffer{end} ------- */ + +`ifdef PCIEI_APB_DBG + /* -------APB reated signal{begin}------- */ + ,output wire [`RSP_DEALIGN_SIGNAL_W-1:0] dbg_signal // o, `RSP_DEALIGN_SIGNAL_W + /* -------APB reated signal{end}------- */ +`endif +); + +/* -------DW Dealignment FSM{begin}------- */ +localparam IDLE = 3'b001, // This state wait for the first beat of the packet, + // and store its header. + RSP_BEAT = 3'b010, // This state caches middle beat of packet. + LAST_BEAT = 3'b100; // This state caches last beat of packet, in this state, + // caching new packet beat is not allowed. + +reg [4:0] cur_state; +reg [4:0] nxt_state; + +wire is_idle, is_rsp_beat, is_last_beat; +/* -------DW Dealignment FSM{end}------- */ + +/* -------Relate to head generation{begin}------- */ +wire [`AXIS_TUSER_W-1:0] axis_rd_rsp_thead; + +// axis axis_rd_rsp_tuser +// wire [`TAG_WIDTH -1:0] tag ; +wire [`DMA_ADDR_WIDTH-1:0] addr_align ; +wire [`DW_LEN_WIDTH -1:0] axis_dw_len; +wire [`FIRST_BE_WIDTH-1:0] first_be ; +wire [`LAST_BE_WIDTH -1:0] last_be ; + +// relate to sub_req_rsp_head +wire [1:0] first_empty ; // Number of invalid bytes in first Double word +wire [1:0] last_empty ; // Number of invalid bytes in last Double word + +wire [`DMA_ADDR_WIDTH-1:0] addr_unalign; +wire [`DMA_LEN_WIDTH -1:0] byte_len ; + +wire rd_rsp_dealign_next_last; // Indicate that in next cycle, rd_rsp_dealign_last asserted + +wire [5:0] axis_beats_total; +wire [5:0] dealign_beats_total; +reg [5:0] dealign_beats_left; // The number of beats left to trans (not including the beat of this cycle) + +reg is_aligned_last; // Indicate that this pkt is a aligned pkt, whose out_last (rd_rsp_dealigned_*) + // asserts at the same time when in_last (axis_rd_rsp_*) asserts +/* -------Relate to head generation{end}------- */ + +// in reg is used to cache input axis data. +/* -------relate to in_reg{begin}------- */ +wire in_reg_tvalid; // read valid from input register +wire in_reg_tlast; +wire [`AXIS_TUSER_W-1:0] in_reg_tuser; +wire [`DMA_DATA_W -1:0] in_reg_tdata; +wire in_reg_tready; +/* -------relate to in_reg{end}------- */ + +/* -------relate to out_reg{begin}------- */ +// reg [`DMA_LEN_WIDTH-1:0] byte_cnt_down; + +reg [`DMA_DATA_W-1:0] in_out_data; // transform data between tmp_reg and out_reg +/* -------relate to tmp_reg{end}------- */ + +/* All these signals are valid in the entire trans peroid of packet */ +wire is_eop; +wire [`DW_LEN_WIDTH-1:0] dw_len; +wire [`TAG_WIDTH -1:0] tag ; + +/* --------------------------------------------------------------------------------------- */ + +`ifdef PCIEI_APB_DBG +/* -------APB reated signal{begin}------- */ +assign dbg_signal = { // 988 + cur_state, nxt_state, // 10 + is_idle, is_rsp_beat, is_last_beat, // 3 + axis_rd_rsp_thead, // 128 + is_eop, addr_align , axis_dw_len, first_be, last_be, // 83 + first_empty, last_empty, // 4 + addr_unalign, byte_len, // 77 + rd_rsp_dealign_next_last, // 1 + axis_beats_total, dealign_beats_total, dealign_beats_left, // 18 + is_aligned_last, // 1 + in_reg_tvalid, in_reg_tlast, in_reg_tuser, in_reg_tdata, in_reg_tready, // 387 + in_out_data, // 256 + is_eop, dw_len, tag // 20 +}; +/* -------APB reated signal{end}------- */ +`endif + +st_reg #( + .TUSER_WIDTH ( `AXIS_TUSER_W ), + .TDATA_WIDTH ( `DMA_DATA_W ), + .MODE ( 1 ) +) in_reg ( + .clk ( dma_clk ), // i, 1 + .rst_n ( rst_n ), // i, 1 + + /* -------input axis-like interface{begin}------- */ + .axis_tvalid ( axis_rd_rsp_tvalid ), // i, 1 + .axis_tlast ( axis_rd_rsp_tlast ), // i, 1 + .axis_tuser ( axis_rd_rsp_thead ), // i, TUSER_WIDTH + .axis_tdata ( axis_rd_rsp_tdata ), // i, `DMA_DATA_W + .axis_tready ( axis_rd_rsp_tready ), // o, 1 + /* -------input axis-like interface{end}------- */ + + /* -------output in_reg inteface{begin}------- */ + .axis_reg_tvalid ( in_reg_tvalid ), // o, 1 + .axis_reg_tlast ( in_reg_tlast ), // o, 1 + .axis_reg_tuser ( in_reg_tuser ), // o, TUSER_WIDTH + .axis_reg_tdata ( in_reg_tdata ), // o, `DMA_DATA_W + .axis_reg_tready ( in_reg_tready ) // i, 1 + /* -------output in_reg inteface{end}------- */ +); + +/* -------DW Dealignment FSM{begin}------- */ +/******************** Stage 1: State Register **********************/ + +assign is_idle = (cur_state == IDLE ); +assign is_rsp_beat = (cur_state == RSP_BEAT ); +assign is_last_beat = (cur_state == LAST_BEAT); + +always @(posedge dma_clk, negedge rst_n) begin + if(~rst_n) + cur_state <= `TD IDLE; + else + cur_state <= `TD nxt_state; +end + +/******************** Stage 2: State Transition **********************/ + +always @(*) begin + case(cur_state) + IDLE: begin + if (axis_rd_rsp_tvalid & rd_rsp_dealign_next_last) begin + nxt_state = LAST_BEAT; + end + else if (axis_rd_rsp_tvalid) begin + nxt_state = RSP_BEAT; + end + else begin + nxt_state = IDLE; + end + end + RSP_BEAT: begin + if (axis_rd_rsp_tvalid && axis_rd_rsp_tready && rd_rsp_dealign_next_last) begin + nxt_state = LAST_BEAT; + end + else begin + nxt_state = RSP_BEAT; + end + end + LAST_BEAT: begin + if (rd_rsp_dealign_valid & rd_rsp_dealign_ready & rd_rsp_dealign_last) begin + if (axis_rd_rsp_tvalid & axis_rd_rsp_tready & is_aligned_last) begin + nxt_state = IDLE; + end + else if (axis_rd_rsp_tvalid & axis_rd_rsp_tready & rd_rsp_dealign_next_last) begin + nxt_state = LAST_BEAT; + end + else if (axis_rd_rsp_tvalid & axis_rd_rsp_tready) begin + nxt_state = RSP_BEAT; + end + else begin + nxt_state = IDLE; + end + end + else begin + nxt_state = LAST_BEAT; + end + end + default: begin + nxt_state = IDLE; + end + endcase +end +/******************** Stage 3: Output **********************/ + +assign in_reg_tready = (rd_rsp_dealign_valid & rd_rsp_dealign_ready) | is_idle; + +/* -------DW Dealignment FSM{end}------- */ + + +/* -------next_last{begin}------- */ +assign rd_rsp_dealign_next_last = (is_idle & (dealign_beats_total == 1)) | // Asserts when next pkt has only one beat + (is_rsp_beat & (dealign_beats_left == 1)) | // Asserts when this pkt forward last beat next cycle. + (is_last_beat & !is_aligned_last & (dealign_beats_total == 1)); // Asserts when next pkt has only one beat + + +/* -------next_last{end}------- */ + +/* -------Head generation{begin}------- */ + +assign addr_align = axis_rd_rsp_tuser[95 :32]; +assign axis_dw_len = axis_rd_rsp_tuser[18 : 8]; +assign first_be = axis_rd_rsp_tuser[7 : 4]; +assign last_be = axis_rd_rsp_tuser[3 : 0]; + +assign first_empty = first_be[0] ? 2'd0 : + first_be[1] ? 2'd1 : + first_be[2] ? 2'd2 : + first_be[3] ? 2'd3 : + 2'd0; // unlikely +assign last_empty = (axis_dw_len == 1) ? + (first_be[3] ? 2'd0 : + first_be[2] ? 2'd1 : + first_be[1] ? 2'd2 : 2'd3) : + ({2{(last_be == 4'b1111)}} & 2'd0 | + {2{(last_be == 4'b0001)}} & 2'd3 | + {2{(last_be == 4'b0011)}} & 2'd2 | + {2{(last_be == 4'b0111)}} & 2'd1); + +assign addr_unalign = {addr_align[`DMA_ADDR_WIDTH-1:2], first_empty}; +assign byte_len = (axis_dw_len << 2) - first_empty - last_empty; + +assign dealign_beats_total = byte_len[`DMA_LEN_WIDTH-1:5] + (|byte_len[4:0]); +assign axis_beats_total = axis_dw_len[`DW_LEN_WIDTH-1:3] + (|axis_dw_len[2:0]); + +always @(posedge dma_clk, negedge rst_n) begin + if (~rst_n) begin + dealign_beats_left <= `TD 0; + is_aligned_last <= `TD 0; + end + else if (is_idle & axis_rd_rsp_tvalid & axis_rd_rsp_tready) begin + dealign_beats_left <= `TD dealign_beats_total - 1; + is_aligned_last <= `TD axis_beats_total > dealign_beats_total; // (first_empty > 0) & (first_empty + byte_len[4:0] > 0) & (first_empty + byte_len[4:0] <= 3); + end + else if (is_rsp_beat & axis_rd_rsp_tvalid & axis_rd_rsp_tready) begin + dealign_beats_left <= `TD dealign_beats_left - 1; + end + else if (is_last_beat & axis_rd_rsp_tvalid & axis_rd_rsp_tready & !is_aligned_last) begin + dealign_beats_left <= `TD dealign_beats_total - 1; + is_aligned_last <= `TD axis_beats_total > dealign_beats_total; + end + else if (is_last_beat & axis_rd_rsp_tvalid & axis_rd_rsp_tready & is_aligned_last) begin + dealign_beats_left <= `TD 0; + is_aligned_last <= `TD 0; + end +end + +/* AXI-Stream read response tuser + * | Reserved | REQ CPL | first_empty | Tag | address | Reserved | DW length | byte length | + * | 127:107 | 106 | 105:104 | 103:96 | 95:32 | 31:24 | 23:13 | 12:0 | + */ +assign axis_rd_rsp_thead = {22'd0, axis_rd_rsp_tuser[104], first_empty, axis_rd_rsp_tuser[103:96], addr_unalign, 8'd0, axis_dw_len, byte_len}; +/* -------Head Generation{end}------- */ + +/* -------out_reg logic{begin}------- */ +assign rd_rsp_dealign_valid = (is_rsp_beat & axis_rd_rsp_tvalid & in_reg_tvalid) | + (is_last_beat & !is_aligned_last & in_reg_tvalid) | + (is_last_beat & is_aligned_last & axis_rd_rsp_tvalid & in_reg_tvalid); +assign rd_rsp_dealign_head = rd_rsp_dealign_valid ? {32'd0, in_reg_tuser[95:32], {32-`DMA_LEN_WIDTH{1'd0}}, in_reg_tuser[12:0]} : 0; +assign rd_rsp_dealign_dlen = dw_len; +assign rd_rsp_dealign_tag = tag; +assign rd_rsp_dealign_data = in_out_data; +assign rd_rsp_dealign_last = rd_rsp_dealign_valid & is_last_beat; +assign rd_rsp_dealign_eop = rd_rsp_dealign_last & is_eop; + +// Refers to axis_rd_rsp_thead +assign is_eop = in_reg_tuser[106]; +assign dw_len = in_reg_tuser[23:13]; +assign tag = in_reg_tuser[103:96]; + + +always @(*) begin + if (is_last_beat & !is_aligned_last) begin + in_out_data = (in_reg_tdata >> {in_reg_tuser[105:104], 3'd0}); + end + else if (is_rsp_beat | (is_last_beat & is_aligned_last)) begin + case (in_reg_tuser[105:104]) + 2'd0: in_out_data = in_reg_tdata; // pkt_aligned + 2'd1: in_out_data = {axis_rd_rsp_tdata[8 * 1 - 1 : 0], in_reg_tdata[`DMA_DATA_W-1 : 8 * 1]}; + 2'd2: in_out_data = {axis_rd_rsp_tdata[8 * 2 - 1 : 0], in_reg_tdata[`DMA_DATA_W-1 : 8 * 2]}; + 2'd3: in_out_data = {axis_rd_rsp_tdata[8 * 3 - 1 : 0], in_reg_tdata[`DMA_DATA_W-1 : 8 * 3]}; + endcase + end + else begin + in_out_data = 0; + end +end +/* -------out_reg logic{end}------- */ + + +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/DMA/DMA_Read/rsp_data_fifo.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/DMA/DMA_Read/rsp_data_fifo.v new file mode 100644 index 0000000000000000000000000000000000000000..954bad5cfcf94189344b1f42370986e9635675b0 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/DMA/DMA_Read/rsp_data_fifo.v @@ -0,0 +1,222 @@ +`timescale 1ns / 100ps +//************************************************************************* +// > File Name: rsp_data_fifo.v +// > Author : Kangning +// > Date : 2020-11-15 +// > Note : rsp_data_fifo, store and concat multi-pkts into one message. +// Note that the fifo could store more than one message. +// > ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +// > ^ ^ +// > ^ ########## ########### ^ +// > ^ # #------># tmp_reg # ########### ^ +// > ^ ------># in_reg # ###########-----># # ^ +// > ^ # # #data_fifo#----> ^ +// > ^ ##########-----------------------># # ^ +// > ^ ########### ^ +// > ^ ^ +// > ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +//************************************************************************* + +module rsp_data_fifo #( + +) ( + input wire dma_clk, // i, 1 + input wire rst_n , // i, 1 + + /* ------- sub_req rsp input{begin} ------- */ + input wire sub_req_rsp_valid, // i, 1 + input wire sub_req_rsp_last , // i, 1; indicate the last cycle of the whole req rsp + input wire [`DMA_LEN_WIDTH-1:0] sub_req_rsp_blen , // i, `DMA_LEN_WIDTH; blen for every cycle + input wire [`DMA_DATA_W -1:0] sub_req_rsp_data , // i, `DMA_DATA_W + output wire sub_req_rsp_ready, // o, 1 + /* ------- sub_req rsp input{end} ------- */ + + /* ------- rsp output{begin} ------- */ + output wire req_rsp_valid, // o, 1 + output wire [`DMA_DATA_W-1:0] req_rsp_data , // o, `DMA_DATA_W + input wire req_rsp_ready // i, 1 + /* ------- rsp output{end} ------- */ + +`ifdef PCIEI_APB_DBG + /* -------APB reated signal{begin}------- */ + ,input wire [`SRAM_RW_DATA_W-1:0] rw_data// i, `SRAM_RW_DATA_W + ,output wire [`DATA_FIFO_SIGNAL_W-1:0] dbg_signal // o, `DATA_FIFO_SIGNAL_W + /* -------APB reated signal{end}------- */ +`endif +); + +/* -------in_reg{begin}------- */ +wire in_reg_valid; +wire in_reg_last ; +wire [`DMA_LEN_WIDTH-1:0] in_reg_blen ; +wire [`DMA_DATA_W -1:0] in_reg_data ; +wire in_reg_ready; +/* -------in_reg{end}------- */ + +/* -------tmp_reg{begin}------- */ +wire in_tmp_valid; +wire in_tmp_last ; +wire [`DMA_LEN_WIDTH-1:0] in_tmp_blen ; +wire [`DMA_DATA_W -1:0] in_tmp_data ; +wire in_tmp_ready; + +wire [`DMA_LEN_WIDTH :0] avail_bytes; +wire [`DMA_DATA_W -1:0] concat_tmp_data; + +wire tmp_reg_valid; +wire tmp_reg_last ; +wire [`DMA_LEN_WIDTH-1:0] tmp_reg_blen ; +wire [`DMA_DATA_W -1:0] tmp_reg_data ; +wire tmp_reg_ready; +/* -------tmp_reg{end}------- */ + +/* -------data fifo{begin}------- */ +wire is_msg_eop; + +wire in_fifo_wen ; +wire [`DMA_DATA_W-1:0] in_fifo_data; +wire in_fifo_full; + +wire out_fifo_ren ; +wire [`DMA_DATA_W-1:0] out_fifo_data ; +wire out_fifo_empty; +/* -------data fifo{end}------- */ + +`ifdef PCIEI_APB_DBG +/* -------APB reated signal{begin}------- */ +wire [1:0] rtsel; +wire [1:0] wtsel; +wire [1:0] ptsel; +wire vg ; +wire vs ; +/* -------APB reated signal{end}------- */ +`endif + +//--------------------------------------------------------------------------------------------------------------------------- + +`ifdef PCIEI_APB_DBG +/* -------APB reated signal{begin}------- */ +assign {rtsel, wtsel, ptsel, vg, vs} = rw_data; +assign dbg_signal = { // 1602 + in_reg_valid, in_reg_last , in_reg_blen , in_reg_data , in_reg_ready, // 272 + in_tmp_valid, in_tmp_last , in_tmp_blen , in_tmp_data , in_tmp_ready, // 272 + avail_bytes, concat_tmp_data, // 269 + tmp_reg_valid, tmp_reg_last, tmp_reg_blen, tmp_reg_data, tmp_reg_ready, // 272 + is_msg_eop, // 1 + in_fifo_wen, in_fifo_data, in_fifo_full, // 258 + out_fifo_ren, out_fifo_data, out_fifo_empty // 258 +}; +/* -------APB reated signal{end}------- */ +`endif + +/* -------in_reg{begin}------- */ +st_reg #( + .TUSER_WIDTH ( 1 ), + .TDATA_WIDTH ( `DMA_DATA_W + `DMA_LEN_WIDTH ) +) in_st_reg ( + .clk ( dma_clk ), // i, 1 + .rst_n ( rst_n ), // i, 1 + + /* -------input axis-like interface{begin}------- */ + .axis_tvalid ( sub_req_rsp_valid ), // i, 1 + .axis_tlast ( sub_req_rsp_last ), // i, 1 + .axis_tuser ( 1'd0 ), // i, TUSER_WIDTH + .axis_tdata ( {sub_req_rsp_blen, sub_req_rsp_data} ), // i, TDATA_WIDTH + .axis_tready ( sub_req_rsp_ready ), // o, 1 + /* -------input axis-like interface{end}------- */ + + /* -------output in_reg inteface{begin}------- */ + .axis_reg_tvalid ( in_reg_valid ), // o, 1 + .axis_reg_tlast ( in_reg_last ), // o, 1 + .axis_reg_tuser ( ), // o, TUSER_WIDTH + .axis_reg_tdata ( {in_reg_blen, in_reg_data} ), // o, TDATA_WIDTH + .axis_reg_tready ( in_reg_ready ) // i, 1 + /* -------output in_reg inteface{end}------- */ +); + +assign in_reg_ready = !in_fifo_full & !is_msg_eop; // & tmp_reg_valid +/* -------in_reg{end}------- */ + +/* -------tmp_reg{begin}------- */ +assign in_tmp_valid = in_reg_valid & in_reg_ready & (avail_bytes != `DMA_W_BCNT); +assign in_tmp_last = in_reg_last & (avail_bytes != `DMA_W_BCNT); +assign in_tmp_blen = (avail_bytes < `DMA_W_BCNT) ? avail_bytes : + (avail_bytes == `DMA_W_BCNT) ? {`DMA_LEN_WIDTH{1'b0}} : + (avail_bytes > `DMA_W_BCNT) ? (avail_bytes - `DMA_W_BCNT) : {`DMA_LEN_WIDTH{1'b0}}; +assign in_tmp_data = (avail_bytes < `DMA_W_BCNT) ? concat_tmp_data : + (avail_bytes == `DMA_W_BCNT) ? {`DMA_DATA_W{1'b0}} : + (avail_bytes > `DMA_W_BCNT) ? (in_reg_data >> ((`DMA_W_BCNT - tmp_reg_blen) << 3)) : {`DMA_DATA_W{1'b0}}; + +assign avail_bytes = (is_msg_eop ? {`DMA_LEN_WIDTH{1'b0}} : tmp_reg_blen) + in_reg_blen; +assign concat_tmp_data = (in_reg_data << (tmp_reg_blen << 3)) | (tmp_reg_data); // & ((1 << (tmp_reg_blen << 3))-1) + +st_reg #( + .TUSER_WIDTH ( 1 ), + .TDATA_WIDTH ( `DMA_LEN_WIDTH + `DMA_DATA_W ) +) tmp_st_reg ( + .clk ( dma_clk ), // i, 1 + .rst_n ( rst_n ), // i, 1 + + /* -------input axis-like interface{begin}------- */ + .axis_tvalid ( in_tmp_valid ), // i, 1 + .axis_tlast ( in_tmp_last ), // i, 1 + .axis_tuser ( 1'd0 ), // i, TUSER_WIDTH + .axis_tdata ( {in_tmp_blen, in_tmp_data} ), // i, TDATA_WIDTH + .axis_tready ( in_tmp_ready ), // o, 1 + /* -------input axis-like interface{end}------- */ + + /* -------output st_reg inteface{begin}------- */ + .axis_reg_tvalid ( tmp_reg_valid ), // o, 1 + .axis_reg_tlast ( tmp_reg_last ), // o, 1 + .axis_reg_tuser ( ), // o, TUSER_WIDTH + .axis_reg_tdata ( {tmp_reg_blen, tmp_reg_data} ), // o, TDATA_WIDTH + .axis_reg_tready ( tmp_reg_ready ) // i, 1 + /* -------output st_reg inteface{end}------- */ +); +/* + * Assert when fifo is not full && there's bytes in tem_reg (tem_reg_blen != 0) && ( + * 1. in_reg data is valid || + * 2. The last cycle of the message, draining the last cycle + * ) + */ +assign tmp_reg_ready = !in_fifo_full & (in_reg_valid | is_msg_eop); +/* -------tmp_reg{end}------- */ + +/* -------data fifo{begin}------- */ +assign is_msg_eop = (tmp_reg_valid & tmp_reg_last & tmp_reg_blen != 0); + +assign in_fifo_wen = (in_reg_valid & (avail_bytes >= `DMA_W_BCNT))| is_msg_eop; +assign in_fifo_data = is_msg_eop ? tmp_reg_data : concat_tmp_data; +pcieifc_sync_fifo #( + .DSIZE ( `DMA_DATA_W ), // 256 + .ASIZE ( `RSP_FIFO_DEPTH_LOG ) // 4KB payload capacity +) data_fifo ( + .clk ( dma_clk ), // i, 1 + .rst_n ( rst_n ), // i, 1 + .clr ( 1'd0 ), // i, 1 + + .wen ( in_fifo_wen ), // i, 1 + .din ( in_fifo_data ), // i, DSIZE + .full ( in_fifo_full ), // o, 1 + + .ren ( out_fifo_ren ), // i, 1 + .dout ( out_fifo_data ), // o, DSIZE + .empty ( out_fifo_empty ) // o, 1 + +`ifdef PCIEI_APB_DBG + ,.rtsel ( rtsel ) // i, 2 + ,.wtsel ( wtsel ) // i, 2 + ,.ptsel ( ptsel ) // i, 2 + ,.vg ( vg ) // i, 1 + ,.vs ( vs ) // i, 1 +`endif +); +assign out_fifo_ren = req_rsp_valid & req_rsp_ready; +/* -------data fifo{end}------- */ + +/* ------- rsp output{begin} ------- */ +assign req_rsp_valid = !out_fifo_empty; +assign req_rsp_data = out_fifo_data; +/* ------- rsp output{end} ------- */ + +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/DMA/DMA_Read/sub_req_rsp_concat.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/DMA/DMA_Read/sub_req_rsp_concat.v new file mode 100644 index 0000000000000000000000000000000000000000..92c7b5b6b1884ab4bf1d831252b2094c6f59c677 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/DMA/DMA_Read/sub_req_rsp_concat.v @@ -0,0 +1,363 @@ +`timescale 1ns / 100ps +//************************************************************************* +// > File Name: sub_req_rsp_concat.v +// > Author : Kangning +// > Date : 2020-09-24 +// > Note : sub_req_rsp_concat, used to reassemble sub-request according +// > to Max_Read_Request_Size. +//************************************************************************* + +module sub_req_rsp_concat #( + parameter HEAD_DEPTH_LOG = 6 +) ( + input wire dma_clk, // i, 1 + input wire rst_n , // i, 1 + + /* -------response emission{begin}------- */ + input wire emit, // i, 1 ; high active + /* -------response emission{end}------- */ + + /* ------- Read Response from module{begin} ------- */ + /* *_head (interact with RDMA modules, through an async fifo), valid only in first beat of a packet + * | Reserved | address | Reserved | Byte length | + * | 127:96 | 95:32 | 31:13 | 12:0 | + */ + input wire rd_sub_req_rsp_valid, // i, 1 + input wire rd_sub_req_rsp_last , // i, 1 + input wire [`DMA_DATA_W-1:0] rd_sub_req_rsp_data , // i, `DMA_DATA_W + input wire [`DMA_HEAD_W-1:0] rd_sub_req_rsp_head , // i, `DMA_HEAD_W + output wire rd_sub_req_rsp_ready, // o, 1 + + output reg is_avail, // o, 1 + /* ------- Read Response from module{end} ------- */ + + /* ------- Read Response to RDMA Engine{begin} ------- */ + /* *_head (interact with RDMA modules, through an async fifo), valid only in first beat of a packet + * | Reserved | address | Reserved | Byte length | + * | 127:96 | 95:32 | 31:13 | 12:0 | + */ + output wire rd_rsp_valid, // o, 1 + output wire rd_rsp_last , // o, 1 + output wire [`DMA_DATA_W-1:0] rd_rsp_data , // o, `DMA_DATA_W + output wire [`DMA_HEAD_W-1:0] rd_rsp_head , // o, `DMA_HEAD_W + input wire rd_rsp_ready, // i, 1 + /* ------- Read Response to RDMA Engine{end} ------- */ + + /* -------PCIe fragment property{begin}------- */ + /* This signal indicates the (max payload size & max read request size) agreed in the communication + * 3'b000 -- 128 B + * 3'b001 -- 256 B + * 3'b010 -- 512 B + * 3'b011 -- 1024B + * 3'b100 -- 2048B + * 3'b101 -- 4096B + */ + input wire [2:0] max_pyld_sz , + input wire [2:0] max_rd_req_sz // max read request size + /* -------PCIe fragment property{end}------- */ + +`ifdef PCIEI_APB_DBG + /* -------APB reated signal{begin}------- */ + ,input wire [`SRAM_RW_DATA_W-1:0] rw_data // i, `SRAM_RW_DATA_W + ,output wire [`RSP_CONCAT_SIGNAL_W-1:0] dbg_signal // o, `RSP_CONCAT_SIGNAL_W + /* -------APB reated signal{end}------- */ +`endif +); + +/* --------Head FIFO{begin}-------- */ +reg is_sub_head_sop; +reg is_head_sop; +reg [`DMA_ADDR_WIDTH-1:0] hd_addr; +reg [`DMA_LEN_WIDTH -1:0] hd_byte_len; +wire [`DMA_LEN_WIDTH -1:0] nxt_byte_len; + +wire only_req_rsp_sop ; +wire last_sub_req_rsp_sop; // sop of last sub_req rsp +wire last_sub_req_rsp_eop; // eop of last sub_req rsp + +wire head_in_valid; +wire [`DMA_HEAD_W-1:0] head_in_head ; +wire head_in_ready; +wire head_in_full ; + +wire head_out_valid; +wire [`DMA_HEAD_W-1:0] head_out_head ; +wire head_out_ready; +wire head_out_empty; +/* --------Head FIFO{end}-------- */ + +/* --------prog_full{begin}--------- */ +/* The inputt is blocked caused by : + * 1. data_rsp_fifo cannot accept new pkt; + * 2. head_store_fifo cannot store new head. */ +wire is_input_blocked; +wire fifo_prog_full; +wire [`DW_LEN_WIDTH-1:0] max_rd_req_cycle_num; // The maximum read request in dw unit +wire [`DMA_LEN_WIDTH-5-1:0] fifo_cycle_cnt; +reg [`DMA_LEN_WIDTH -1:0] fifo_byte_cnt; +wire [`DMA_LEN_WIDTH -1:0] nxt_fifo_byte_cnt, fifo_in_inc, fifo_out_dec; +/* --------prog_full{end}--------- */ + +/* --------Data FIFO{begin}-------- */ +wire sub_req_rsp_valid; +wire sub_req_rsp_last ; +wire sub_req_rsp_eop ; // End of the req rsp msg +wire [`DMA_DATA_W -1:0] sub_req_rsp_data ; +wire [`DMA_LEN_WIDTH-1:0] sub_req_rsp_blen ; +wire [`DMA_HEAD_W -1:0] sub_req_rsp_head ; +wire sub_req_rsp_ready; + +wire [`DMA_LEN_WIDTH -1:0] sub_blen_total; +wire [`DMA_LEN_WIDTH -1:0] sub_blen_left ; +reg [`DMA_LEN_WIDTH -1:0] in_trans_cnt ; + +wire [`DMA_LEN_WIDTH -1:0] out_blen_total; +wire [`DMA_LEN_WIDTH -1:0] out_blen_left ; +reg [`DMA_LEN_WIDTH -1:0] out_trans_cnt ; + +wire req_rsp_valid; +wire req_rsp_last ; +wire [`DMA_DATA_W-1:0] req_rsp_data ; +wire req_rsp_ready; +/* --------Data FIFO{end}-------- */ + +`ifdef PCIEI_APB_DBG +/* -------APB reated signal{begin}------- */ +wire [`DATA_FIFO_SIGNAL_W-1:0] dbg_signal_data_fifo; +/* -------APB reated signal{end}------- */ +`endif + +//----------------------------------------------------------------------------------------------------------------- + +`ifdef PCIEI_APB_DBG +/* -------APB reated signal{begin}------- */ +assign dbg_signal = { // 2770 + is_sub_head_sop, is_head_sop, // 2 + hd_addr, hd_byte_len, nxt_byte_len, // 90 + only_req_rsp_sop, last_sub_req_rsp_sop, last_sub_req_rsp_eop, // 3 + head_in_valid, head_in_head , head_in_ready, head_in_full , // 131 + head_out_valid, head_out_head , head_out_ready, head_out_empty, // 131 + is_input_blocked, fifo_prog_full, // 2 + max_rd_req_cycle_num, // 11 + fifo_cycle_cnt, // 8 + fifo_byte_cnt, // 13 + nxt_fifo_byte_cnt, fifo_in_inc, fifo_out_dec, // 39 + sub_req_rsp_valid, sub_req_rsp_last, sub_req_rsp_eop, sub_req_rsp_data, sub_req_rsp_blen, sub_req_rsp_head, sub_req_rsp_ready, // 401 + sub_blen_total, sub_blen_left , in_trans_cnt , // 39 + out_blen_total, out_blen_left , out_trans_cnt , // 39 + req_rsp_valid, req_rsp_last , req_rsp_data , req_rsp_ready, // 259 + dbg_signal_data_fifo // 1602 +}; +/* -------APB reated signal{end}------- */ +`endif + +/* --------Head FIFO{begin}-------- */ +// start of sub_req rsp pkt +always @(posedge dma_clk, negedge rst_n) begin + if (~rst_n) begin + is_sub_head_sop <= `TD 1'b1; + end + else if (sub_req_rsp_valid & sub_req_rsp_ready & sub_req_rsp_last) begin + is_sub_head_sop <= `TD 1'b1; + end + else if (sub_req_rsp_valid & sub_req_rsp_ready) begin // invalid after the first cycle + is_sub_head_sop <= `TD 1'b0; + end +end + +// start of req rsp pkt +always @(posedge dma_clk, negedge rst_n) begin + if (~rst_n) begin + is_head_sop <= `TD 1'b1; + end + else if (sub_req_rsp_valid & sub_req_rsp_ready & sub_req_rsp_last & emit) begin + is_head_sop <= `TD 1'b1; + end + else if (sub_req_rsp_valid & sub_req_rsp_ready) begin // invalid after the first cycle + is_head_sop <= `TD 1'b0; + end +end + +always @(posedge dma_clk, negedge rst_n) begin + if (~rst_n) begin + hd_addr <= `TD 0; + end + else if (sub_req_rsp_valid & sub_req_rsp_ready & is_head_sop) begin // first cycle of req rsp + hd_addr <= `TD sub_req_rsp_head[95:32]; + end + else if (last_sub_req_rsp_eop) begin // last cycle of last sub_req rsp + hd_addr <= `TD 0; + end +end + +always @(posedge dma_clk, negedge rst_n) begin + if (~rst_n) begin + hd_byte_len <= `TD 0; + end + else if (sub_req_rsp_valid & sub_req_rsp_ready & is_head_sop) begin // first cycle of req rsp + hd_byte_len <= `TD sub_req_rsp_head[12:0]; + end + else if (sub_req_rsp_valid & sub_req_rsp_ready & is_sub_head_sop) begin // first cycle of middle & last sub_req rsp + hd_byte_len <= `TD nxt_byte_len; + end + else if (last_sub_req_rsp_eop) begin // last cycle of last sub_req rsp + hd_byte_len <= `TD 0; + end +end +assign nxt_byte_len = hd_byte_len + sub_req_rsp_head[12:0]; + +assign only_req_rsp_sop = emit & sub_req_rsp_valid & sub_req_rsp_ready & is_head_sop ; +assign last_sub_req_rsp_sop = emit & sub_req_rsp_valid & sub_req_rsp_ready & is_sub_head_sop ; +assign last_sub_req_rsp_eop = emit & sub_req_rsp_valid & sub_req_rsp_ready & sub_req_rsp_last; + + +// -----------------------------------------Store the head------------------------------------------ +assign head_in_valid = last_sub_req_rsp_sop | only_req_rsp_sop; +assign head_in_head = only_req_rsp_sop ? + {32'd0, sub_req_rsp_head[95:32], {32-`DMA_LEN_WIDTH{1'b0}}, sub_req_rsp_head[12:0]} : // if only has one sub_req rsp for a rsp + {32'd0, hd_addr, {32-`DMA_LEN_WIDTH{1'b0}}, nxt_byte_len}; +assign head_in_ready = !head_in_full; + +assign head_out_ready = rd_rsp_valid & rd_rsp_ready & req_rsp_last; +assign head_out_valid = !head_out_empty; +pcieifc_sync_fifo #( + .DSIZE ( `DMA_HEAD_W ), // 128 + .ASIZE ( HEAD_DEPTH_LOG ) // 2 +) head_store_fifo ( + + .clk ( dma_clk ), // i, i + .rst_n ( rst_n ), // i, i + .clr ( 1'd0 ), // i, 1 + + .wen ( head_in_valid & head_in_ready ), // i, 1 + .din ( head_in_head ), // i, `DMA_HEAD_W + .full ( head_in_full ), // o, 1 + + .ren ( head_out_valid & head_out_ready ), // i, 1 + .dout ( head_out_head ), // o, `DMA_HEAD_W + .empty( head_out_empty ) // o, 1 + +`ifdef PCIEI_APB_DBG + ,.rtsel ( 2'b0 ) // i, 2 + ,.wtsel ( 2'b0 ) // i, 2 + ,.ptsel ( 2'b0 ) // i, 2 + ,.vg ( 1'b0 ) // i, 1 + ,.vs ( 1'b0 ) // i, 1 +`endif +); +/* --------Head FIFO{end}-------- */ + +/* --------is available{begin}-------- */ +always @(posedge dma_clk, negedge rst_n) begin + if (~rst_n) begin + is_avail <= `TD 1'd0; + end + else if (rd_rsp_ready) begin + is_avail <= `TD 1'd1; + end + else begin + is_avail <= `TD 1'd0; + end +end +/* --------is available{end}-------- */ + +/* --------prog_full{begin}--------- */ +assign rd_sub_req_rsp_ready = sub_req_rsp_ready & !is_input_blocked; + +assign max_rd_req_cycle_num = 8'd4 << max_rd_req_sz; +assign is_input_blocked = is_sub_head_sop & (fifo_prog_full | !head_in_ready); +assign fifo_prog_full = (fifo_cycle_cnt + max_rd_req_cycle_num) > (8'd1 << `RSP_FIFO_DEPTH_LOG); +assign fifo_cycle_cnt = (|fifo_byte_cnt[4:0] + fifo_byte_cnt[`DMA_LEN_WIDTH-1:5]); + +assign nxt_fifo_byte_cnt = fifo_byte_cnt + sub_req_rsp_blen; +assign fifo_in_inc = last_sub_req_rsp_eop ? ((|nxt_fifo_byte_cnt[4:0] + nxt_fifo_byte_cnt[`DMA_LEN_WIDTH-1:5]) << 5) : + (sub_req_rsp_valid & sub_req_rsp_ready) ? (fifo_byte_cnt + sub_req_rsp_blen) : fifo_byte_cnt; +assign fifo_out_dec = (req_rsp_valid & req_rsp_ready) ? `DMA_W_BCNT : {`DMA_LEN_WIDTH{1'd0}}; +always @(posedge dma_clk, negedge rst_n) begin + if (~rst_n) begin + fifo_byte_cnt <= `TD 0; + end + else begin + fifo_byte_cnt <= `TD fifo_in_inc - fifo_out_dec; + end +end +/* --------prog_full{end}--------- */ + +/* --------Data FIFO{begin}-------- */ +assign sub_req_rsp_valid = rd_sub_req_rsp_valid & !is_input_blocked; +assign sub_req_rsp_last = rd_sub_req_rsp_last ; +assign sub_req_rsp_eop = rd_sub_req_rsp_last & emit; +assign sub_req_rsp_data = rd_sub_req_rsp_data ; +assign sub_req_rsp_head = rd_sub_req_rsp_head ; + +assign sub_req_rsp_blen = (sub_blen_left >= `DMA_W_BCNT) ? `DMA_W_BCNT : sub_blen_left; +assign sub_blen_left = sub_blen_total - in_trans_cnt; +assign sub_blen_total = sub_req_rsp_head[12:0]; +always @(posedge dma_clk, negedge rst_n) begin + if (~rst_n) begin + in_trans_cnt <= `TD 0; + end + else if (sub_req_rsp_valid & sub_req_rsp_ready & sub_req_rsp_last) begin + in_trans_cnt <= `TD 0; + end + else if (sub_req_rsp_valid & sub_req_rsp_ready) begin + in_trans_cnt <= `TD in_trans_cnt + `DMA_W_BCNT; + end +end + +rsp_data_fifo #( + +) rsp_data_fifo ( + + .dma_clk ( dma_clk ), // i, 1 + .rst_n ( rst_n ), // i, 1 + + /* ------- sub_req rsp input{begin} ------- */ + .sub_req_rsp_valid ( sub_req_rsp_valid ), // i, 1 + .sub_req_rsp_last ( sub_req_rsp_last & emit ), // i, 1 + .sub_req_rsp_blen ( sub_req_rsp_blen ), // i, `DMA_LEN_WIDTH; blen for every cycle + .sub_req_rsp_data ( sub_req_rsp_data ), // i, `DMA_DATA_W + .sub_req_rsp_ready ( sub_req_rsp_ready ), // o, 1 + /* ------- sub_req rsp input{end} ------- */ + + /* ------- rsp output{begin} ------- */ + .req_rsp_valid ( req_rsp_valid ), // o, 1 + .req_rsp_data ( req_rsp_data ), // o, `DMA_DATA_W + .req_rsp_ready ( req_rsp_ready ) // i, 1 + /* ------- rsp output{end} ------- */ + +`ifdef PCIEI_APB_DBG + /* -------APB reated signal{begin}------- */ + ,.rw_data ( rw_data ) // i, `SRAM_RW_DATA_W + ,.dbg_signal ( dbg_signal_data_fifo ) // o, `DATA_FIFO_SIGNAL_W + /* -------APB reated signal{end}------- */ +`endif +); + +assign out_blen_total = head_out_head[12:0]; +assign out_blen_left = out_blen_total - out_trans_cnt; +always @(posedge dma_clk, negedge rst_n) begin + if (~rst_n) begin + out_trans_cnt <= `TD 0; + end + else if (rd_rsp_valid & rd_rsp_ready & rd_rsp_last) begin + out_trans_cnt <= `TD 0; + end + else if (rd_rsp_valid & rd_rsp_ready) begin + out_trans_cnt <= `TD out_trans_cnt + `DMA_W_BCNT; + end +end + +assign req_rsp_last = (out_blen_left <= `DMA_W_BCNT); +/* --------Data FIFO{end}-------- */ + +/* --------Output {begin}-------- */ +assign rd_rsp_valid = req_rsp_valid & head_out_valid; +assign rd_rsp_last = req_rsp_valid & req_rsp_last ; +assign rd_rsp_data = req_rsp_data ; +assign rd_rsp_head = head_out_head; + +assign req_rsp_ready = head_out_valid & rd_rsp_ready; +/* --------Output {end}-------- */ + +endmodule diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/DMA/DMA_Read/sub_req_rsp_wrapper.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/DMA/DMA_Read/sub_req_rsp_wrapper.v new file mode 100644 index 0000000000000000000000000000000000000000..35754197c2a029e394f4de440260a94b9f599dc0 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/DMA/DMA_Read/sub_req_rsp_wrapper.v @@ -0,0 +1,239 @@ +`timescale 1ns / 100ps +//************************************************************************* +// > File : sub_req_rsp_wrapper.v +// > Author : Kangning +// > Date : 2022-06-29 +// > Note : Wrapper for sub_req_rsp interface +//************************************************************************* + +module sub_req_rsp_wrapper #( + +) ( + input wire dma_clk, // i, 1 + input wire rst_n , // i, 1 + + /* ------- Read Response output{begin} ------- */ + /* *_head + * | Reserved | address | Reserved | Byte length | + * | 127:96 | 95:32 | 31:13 | 12:0 | + */ + output wire ft_rd_rsp_ren , // o, 1 + output wire [`TAG_NUM_LOG-1:0] ft_rd_rsp_tag , // o, `TAG_NUM_LOG + input wire [`DMA_HEAD_W -1:0] ft_rd_rsp_head, // i, `DMA_HEAD_W + input wire [`DMA_DATA_W -1:0] ft_rd_rsp_data, // i, `DMA_DATA_W + input wire ft_rd_rsp_last, // i, 1 + input wire ft_rd_rsp_vld , // i, 1 + /* ------- Read Response output{end} ------- */ + + /* -------tag release{begin}------- */ + output wire nxt_match_ready, // o, 1 + input wire nxt_match_last , // i, 1 + input wire [`DW_LEN_WIDTH-1:0] nxt_match_sz , // i, `DW_LEN_WIDTH + input wire [`TAG_MISC -1:0] nxt_match_misc , // i, `TAG_MISC ; Including addr && dw empty info + input wire [8 -1:0] nxt_match_chnl , // i, `DMA_RD_CHNL_NUM_LOG + input wire [`TAG_NUM_LOG -1:0] nxt_match_tag , // i, `TAG_NUM_LOG + input wire nxt_match_valid, // i, 1 + /* -------tag release{end}------- */ + + /* ------- Read sub-req response{begin} ------- */ + /* dma_*_head + * | emit | chnl_num | Reserved | address | Reserved | Byte length | + * | 127 | 126:120 | 119:96 | 95:32 | 31:13 | 12:0 | + */ + output wire st_sub_req_rsp_valid, // o, 1 + output wire st_sub_req_rsp_last , // o, 1 + output wire [`DMA_DATA_W-1:0] st_sub_req_rsp_data , // o, `DMA_DATA_W + output wire [`DMA_HEAD_W-1:0] st_sub_req_rsp_head , // o, `DMA_HEAD_W + input wire st_sub_req_rsp_ready // i, 1 + /* ------- Read sub-req response{end} ------- */ + +`ifdef PCIEI_APB_DBG + /* -------APB reated signal{begin}------- */ + ,input wire [31:0] dbg_sel // i, 32 + ,output wire [31:0] dbg_bus // o, 32 + /* -------APB reated signal{end}------- */ +`endif +); + + +/* -------sub_req_rsp_head generation {begin}------- */ +reg [0 :0] last ; +reg [12 :0] size ; +reg [`TAG_NUM_LOG-1:0] tag ; +reg [7 :0] chnl_num; +reg [6 :0] addr ; +reg [`DMA_LEN_WIDTH-1:0] byte_len; +/* ------- sub_req_rsp_head generation{end}------- */ + +/* -------State relevant to FSM{begin}------- */ +localparam IDLE = 2'b01, // Wait for the the release of tag fifo + FORWARD = 2'b10; // Store the the response to reorder buffer till the out_reg send its + // last beat. Then jump to IDLE. + +reg [1:0] cur_state; +reg [1:0] nxt_state; + +wire is_idle, is_forward; +wire j_forward, j_idle; +wire nxt_forward; +/* -------State relevant to FSM{end}------- */ + +/* ------- Read sub-req response{begin} ------- */ +/* dma_*_head + * | emit | chnl_num | Reserved | address | Reserved | Byte length | + * | 127 | 126:120 | 119:96 | 95:32 | 31:13 | 12:0 | + */ +wire sub_req_rsp_valid; +wire sub_req_rsp_last ; +wire [`DMA_DATA_W-1:0] sub_req_rsp_data ; +wire [`DMA_HEAD_W-1:0] sub_req_rsp_head ; +wire sub_req_rsp_ready; +/* ------- Read sub-req response{end} ------- */ + +`ifdef PCIEI_APB_DBG +/* -------APB reated signal{begin}------- */ +wire [`WRAPPER_SIGNAL_W-1:0] dbg_signal; +/* -------APB reated signal{end}------- */ +`endif + +// ---------------------------------------------------------------------------------------------------------------------------------------------------------------- // + +`ifdef PCIEI_APB_DBG +/* -------APB reated signal{begin}------- */ +assign dbg_bus = dbg_signal >> {dbg_sel, 5'd0}; + +assign dbg_signal = { // 444 + last, size, tag, chnl_num, addr, byte_len, // 48 + cur_state, nxt_state, // 4 + is_idle, is_forward, // 2 + j_forward, j_idle, // 2 + nxt_forward, // 1 + sub_req_rsp_valid, sub_req_rsp_last , sub_req_rsp_data , sub_req_rsp_head , sub_req_rsp_ready // 387 +}; +/* -------APB reated signal{end}------- */ +`endif + +/* -------{Read Response FSM}begin------- */ +/******************** Stage 1: State Register **********************/ +assign is_idle = (cur_state == IDLE ); +assign is_forward = (cur_state == FORWARD); + +assign j_forward = (cur_state == IDLE) & nxt_match_valid; +assign nxt_forward = (cur_state == IDLE) & nxt_match_valid; + +assign j_idle = (cur_state == FORWARD) & (sub_req_rsp_valid & sub_req_rsp_ready & sub_req_rsp_last); + +always @(posedge dma_clk, negedge rst_n) begin + if(~rst_n) + cur_state <= `TD IDLE; + else + cur_state <= `TD nxt_state; +end + +/******************** Stage 2: State Transition **********************/ + +always @(*) begin + case(cur_state) + IDLE: begin + if (nxt_match_valid) begin + nxt_state = FORWARD; + end + else begin + nxt_state = IDLE; + end + end + FORWARD: begin + if (sub_req_rsp_valid & sub_req_rsp_ready & sub_req_rsp_last) begin + nxt_state = IDLE; + end + else begin + nxt_state = FORWARD; + end + end + default: begin + nxt_state = IDLE; + end + endcase +end +/******************** Stage 3: Output **********************/ + +// interface with Reorder buffer Fetch +assign ft_rd_rsp_ren = is_forward & sub_req_rsp_ready; +assign ft_rd_rsp_tag = tag; + +// interface with Non-posted Tag Management +assign nxt_match_ready = is_forward & sub_req_rsp_valid & sub_req_rsp_ready & sub_req_rsp_last; // j_forward | nxt_forward; + +// sub_req_rsp interface +/* dma_*_head + * | emit | chnl_num | Reserved | address | Reserved | Byte length | + * | 127 | 126:120 | 119:96 | 95:32 | 31:13 | 12:0 | + */ +assign sub_req_rsp_valid = ft_rd_rsp_vld & is_forward; +assign sub_req_rsp_last = sub_req_rsp_valid ? ft_rd_rsp_last : 0; +assign sub_req_rsp_head = sub_req_rsp_valid ? {((last << 7) | chnl_num), 81'd0, addr, 19'd0, byte_len} : 0; +assign sub_req_rsp_data = sub_req_rsp_valid ? ft_rd_rsp_data : 0; +/* -------{Read Response FSM}end------- */ + + +/* -------Sub req rsp signal generation{begin}------- */ +always @(posedge dma_clk, negedge rst_n) begin + if (~rst_n) begin + last <= `TD 0; + size <= `TD 0; + tag <= `TD 0; + chnl_num <= `TD 0; + addr <= `TD 0; + byte_len <= `TD 0; + end + else if (j_idle) begin + last <= `TD 0; + size <= `TD 0; + tag <= `TD 0; + chnl_num <= `TD 0; + addr <= `TD 0; + byte_len <= `TD 0; + end + else if (j_forward) begin // j_forward | nxt_forward + last <= `TD nxt_match_last; + size <= `TD nxt_match_sz ; + tag <= `TD nxt_match_tag ; + chnl_num <= `TD nxt_match_chnl; + addr <= `TD nxt_match_misc[11:5]; + byte_len <= `TD (nxt_match_sz << 2) - nxt_match_misc[4:0]; + end +end +/* -------Sub req rsp signal generation{end}------- */ + +/* -------output reg{begin}------- */ +assign st_sub_req_rsp_valid = sub_req_rsp_valid; +assign st_sub_req_rsp_last = sub_req_rsp_last ; +assign st_sub_req_rsp_head = sub_req_rsp_head ; +assign st_sub_req_rsp_data = sub_req_rsp_data ; +assign sub_req_rsp_ready = st_sub_req_rsp_ready; +// st_reg #( +// .TUSER_WIDTH ( `DMA_HEAD_W ), +// .TDATA_WIDTH ( `DMA_DATA_W ) +// ) out_st_reg ( +// .clk ( dma_clk ), // i, 1 +// .rst_n ( rst_n ), // i, 1 + +// /* -------input axis-like interface{begin}------- */ +// .axis_tvalid ( sub_req_rsp_valid ), // i, 1 +// .axis_tlast ( sub_req_rsp_last ), // i, 1 +// .axis_tuser ( sub_req_rsp_head ), // i, TUSER_WIDTH +// .axis_tdata ( sub_req_rsp_data ), // i, TDATA_WIDTH +// .axis_tready ( sub_req_rsp_ready ), // o, 1 +// /* -------input axis-like interface{end}------- */ + +// /* -------output in_reg inteface{begin}------- */ +// .axis_reg_tvalid ( st_sub_req_rsp_valid ), // o, 1 +// .axis_reg_tlast ( st_sub_req_rsp_last ), // o, 1 +// .axis_reg_tuser ( st_sub_req_rsp_head ), // o, TUSER_WIDTH +// .axis_reg_tdata ( st_sub_req_rsp_data ), // o, TDATA_WIDTH +// .axis_reg_tready ( st_sub_req_rsp_ready ) // i, 1 +// /* -------output in_reg inteface{end}------- */ +// ); +/* -------output reg{end}------- */ + +endmodule diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/DMA/DMA_Read/sub_rsp_concat.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/DMA/DMA_Read/sub_rsp_concat.v new file mode 100644 index 0000000000000000000000000000000000000000..f72748a4b1032684022bfd145d25f28e85eae635 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/DMA/DMA_Read/sub_rsp_concat.v @@ -0,0 +1,485 @@ +`timescale 1ns / 100ps +//************************************************************************* +// > File Name: sub_rsp_concat.v +// > Author : Kangning +// > Date : 2020-11-15 +// > Note : sub_rsp_concat, store and concat multi-pkts into one message. +// Note that the fifo could store more than one message. +// > ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +// > ^ ^ +// > ^ ########## ########### ^ +// > ^ # #------># tmp_reg # ########### ^ +// > ^ ------># in_reg # ###########-----># # ^ +// > ^ # # #data_fifo#----> ^ +// > ^ ##########-----------------------># # ^ +// > ^ ########### ^ +// > ^ ^ +// > ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +//************************************************************************* + +module sub_rsp_concat #( + +) ( + input wire dma_clk, // i, 1 + input wire rst_n , // i, 1 + output reg init_done, // o, 1 + + /* ------- sub-rsp input{begin} ------- */ + input wire st_rd_rsp_valid, // i, 1 + input wire st_rd_rsp_last , // i, 1; indicate the last cycle of the whole req rsp + input wire st_rd_rsp_eop , // i, 1; indicate the last cycle of the whole req rsp + input wire [`TAG_NUM_LOG -1:0] st_rd_rsp_tag , // i, `TAG_NUM_LOG + input wire [`DMA_LEN_WIDTH-1:0] st_rd_rsp_blen , // i, `DMA_LEN_WIDTH; blen for every cycle + input wire [`DMA_DATA_W -1:0] st_rd_rsp_data , // i, `DMA_DATA_W + output wire st_rd_rsp_ready, // o, 1 + /* ------- sub-rsp input{end} ------- */ + + /* ------- rsp output{begin} ------- */ + output wire store_fifo_wen , // o, 1 + output wire [`TAG_NUM_LOG-1:0] store_fifo_tag , // o, `TAG_NUM_LOG + output wire store_fifo_last, // o, 1 + output wire [`DMA_DATA_W -1:0] store_fifo_data, // o, `DMA_DATA_W + input wire store_fifo_rdy // i, 1 + /* ------- rsp output{end} ------- */ + +`ifdef PCIEI_APB_DBG + /* -------APB reated signal{begin}------- */ + ,input wire [`SRAM_RW_DATA_W-1:0] rw_data// i, `SRAM_RW_DATA_W + ,output wire [`SUB_RSP_CONCAT_SIGNAL_W-1:0] dbg_signal // o, `SUB_RSP_CONCAT_SIGNAL_W + /* -------APB reated signal{end}------- */ +`endif +); + +/* --------Init related signal{begin}-------- */ +reg [`TAG_NUM_LOG -1:0] init_waddr ; +/* --------Init related signal{end}-------- */ + +/* -------in_reg{begin}------- */ +wire st_valid; +wire st_last ; +wire [`TAG_NUM_LOG -1:0] st_tag ; +wire [1+`DMA_LEN_WIDTH+`DMA_DATA_W-1:0] st_pyld ; +wire st_ready; + +wire in_reg_valid; +wire in_reg_last ; +wire in_reg_eop ; +wire [`TAG_NUM_LOG -1:0] in_reg_tag ; +wire [`DMA_LEN_WIDTH-1:0] in_reg_blen ; +wire [`DMA_DATA_W -1:0] in_reg_data ; +wire in_reg_ready; + +reg in_reg_first; // First packet of in_reg +/* -------in_reg{end}------- */ + +/* -------Temp data get FSM{begin}------- */ +localparam IDLE = 3'b001, // Wait for the comming of the data; At this state, we read + // the temp data in sram and get it in the next cycle. + FORWARD = 3'b010, // Forward to store the data. + TMP_CYCLE = 3'b100; // This is the last cycle (eop) with only tmp data outputs + +reg [2:0] cur_state; +reg [2:0] nxt_state; + +wire is_idle, is_forward, is_tmp_cycle; +wire j_forward, j_tmp_cycle; + +wire is_forward_last ; // last cycle in forward state +wire is_tmp_cycle_last; // last cycle in tmp_cycle state + +wire is_trans_last; // last cycle to trans this pkt (not eop) +wire is_trans_eop ; // last cycle to trans this pkt (eop) + + +wire [`DMA_LEN_WIDTH-1:0] tmp_blen; +wire [`DMA_DATA_W -1:0] tmp_data; + +wire [`DMA_LEN_WIDTH-1:0] tmp_sram_blen; +wire [`DMA_DATA_W -1:0] tmp_sram_data; +/* -------Temp data get FSM{end}------- */ + +/* --------Temp data SRAM{begin}-------- */ +wire temp_wen ; +wire [`TAG_NUM_LOG -1:0] temp_waddr ; +wire [`DMA_LEN_WIDTH+`DMA_DATA_W-1:0] temp_din ; +wire temp_ren ; +wire [`TAG_NUM_LOG -1:0] temp_raddr ; +wire [`DMA_LEN_WIDTH+`DMA_DATA_W-1:0] temp_dout ; + +// Fast forward related +wire is_fast_forward; + +wire tmp_ff_valid; +wire [`DMA_LEN_WIDTH-1:0] tmp_ff_blen ; +wire [`DMA_DATA_W -1:0] tmp_ff_data ; +wire tmp_ff_ready; +/* --------Temp data SRAM{end}-------- */ + +/* --------Tep reg related{begin}-------- */ +wire con_tmp_valid; +wire con_tmp_last ; +wire [`TAG_NUM_LOG -1:0] con_tmp_tag ; +wire [`DMA_LEN_WIDTH-1:0] con_tmp_blen ; +wire [`DMA_DATA_W -1:0] con_tmp_data ; +wire con_tmp_eop ; +wire con_tmp_ready; + +wire tmp_reg_valid; // We assume tmp_reg is always valid when we use it +wire tmp_reg_last ; +wire [`TAG_NUM_LOG -1:0] tmp_reg_tag ; +wire [`DMA_LEN_WIDTH-1:0] tmp_reg_blen ; +wire [`DMA_DATA_W -1:0] tmp_reg_data ; +wire tmp_reg_eop ; +wire tmp_reg_ready; +/* --------Tep reg related{end}-------- */ + +/* ---------Concat temp & in_reg{begin}-------- */ +wire concat_valid; +wire concat_eop ; +wire [`TAG_NUM_LOG -1:0] concat_tag ; +wire [`DMA_LEN_WIDTH :0] concat_blen ; +wire [2*`DMA_DATA_W -1:0] concat_data ; +/* ---------Concat temp & in_reg{end}-------- */ + +/* -------out_reg{begin}------- */ + +wire con_out_valid; +wire con_out_last ; +wire [`TAG_NUM_LOG -1:0] con_out_tag ; +wire [`DMA_LEN_WIDTH-1:0] con_out_blen ; +wire [`DMA_DATA_W -1:0] con_out_data ; +wire con_out_ready; +/* -------out_reg{end}------- */ + + +`ifdef PCIEI_APB_DBG +/* -------APB reated signal{begin}------- */ +wire [1:0] rtsel; +wire [1:0] wtsel; +wire [1:0] ptsel; +wire vg ; +wire vs ; +/* -------APB reated signal{end}------- */ +`endif + +//--------------------------------------------------------------------------------------------------------------------------- + +`ifdef PCIEI_APB_DBG +/* -------APB reated signal{begin}------- */ +assign {rtsel, wtsel, ptsel, vg, vs} = rw_data; +assign dbg_signal = { // 3311 + init_waddr, // 6 + st_valid, st_last , st_tag , st_pyld , st_ready, // 279 + in_reg_valid, in_reg_last , in_reg_eop , in_reg_tag , in_reg_blen , in_reg_data , in_reg_ready, // 279 + in_reg_first, // 1 + cur_state, nxt_state, // 6 + is_idle, is_forward, is_tmp_cycle, j_forward, j_tmp_cycle, // 5 + is_forward_last , is_tmp_cycle_last, is_trans_last, is_trans_eop , // 4 + tmp_blen, tmp_data, tmp_sram_blen, tmp_sram_data, // 538 + temp_wen , temp_waddr , temp_din , temp_ren , temp_raddr , temp_dout , // 552 + is_fast_forward, // 1 + tmp_ff_valid, tmp_ff_blen , tmp_ff_data , tmp_ff_ready, // 271 + con_tmp_valid, con_tmp_last , con_tmp_tag , con_tmp_blen , con_tmp_data , con_tmp_eop , con_tmp_ready, // 279 + tmp_reg_valid, tmp_reg_last , tmp_reg_tag , tmp_reg_blen , tmp_reg_data , tmp_reg_eop , tmp_reg_ready, // 279 + concat_valid, concat_eop , concat_tag , concat_blen , concat_data , // 533 + con_out_valid, con_out_last , con_out_tag , con_out_blen , con_out_data , con_out_ready // 278 +}; +/* -------APB reated signal{end}------- */ +`endif + +/* --------Init related signal{begin}-------- */ +always @(posedge dma_clk, negedge rst_n) begin + if (~rst_n) begin + init_done <= `TD 1'd0; + end + else if (init_waddr == `TAG_NUM - 1) begin + init_done <= `TD 1'd1; + end +end + +always @(posedge dma_clk, negedge rst_n) begin + if (~rst_n) begin + init_waddr <= `TD {`TAG_NUM_LOG{1'd0}}; + end + else if (init_waddr != `TAG_NUM - 1) begin + init_waddr <= init_waddr + 1; + end +end +/* --------Init related signal{end}-------- */ + +/* -------in_reg{begin}------- */ +assign st_rd_rsp_ready = st_ready & (!j_tmp_cycle); + +assign st_valid = st_rd_rsp_valid & (!j_tmp_cycle); +assign st_last = st_rd_rsp_last; +assign st_tag = st_rd_rsp_tag ; +assign st_pyld = {st_rd_rsp_eop, st_rd_rsp_blen, st_rd_rsp_data}; + +st_reg #( + .TUSER_WIDTH ( `TAG_NUM_LOG ), + .TDATA_WIDTH ( 1 + `DMA_LEN_WIDTH + `DMA_DATA_W ), + .MODE ( 1 ) // Allow only one cycle storage +) in_st_reg ( + .clk ( dma_clk ), // i, 1 + .rst_n ( rst_n ), // i, 1 + + /* -------input axis-like interface{begin}------- */ + .axis_tvalid ( st_valid ), // i, 1 + .axis_tlast ( st_last ), // i, 1 + .axis_tuser ( st_tag ), // i, TUSER_WIDTH + .axis_tdata ( st_pyld ), // i, TDATA_WIDTH + .axis_tready ( st_ready ), // o, 1 + /* -------input axis-like interface{end}------- */ + + /* -------output in_reg inteface{begin}------- */ + .axis_reg_tvalid ( in_reg_valid ), // o, 1 + .axis_reg_tlast ( in_reg_last ), // o, 1 + .axis_reg_tuser ( in_reg_tag ), // o, TUSER_WIDTH + .axis_reg_tdata ( {in_reg_eop, in_reg_blen, in_reg_data} ), // o, TDATA_WIDTH + .axis_reg_tready ( in_reg_ready ) // i, 1 + /* -------output in_reg inteface{end}------- */ +); + +assign in_reg_ready = con_out_ready; // in tmp_cycle state, it is still controlled by con_out_ready, + // cause we need to drain the input stream reg + +always @(posedge dma_clk, negedge rst_n) begin + if (~rst_n) begin + in_reg_first <= `TD 1'd0; + end + else if (j_forward) begin + in_reg_first <= `TD 1'd1; + end + else begin + in_reg_first <= `TD 1'd0; + end +end +/* -------in_reg{end}------- */ + +/* -------{Temp data get FSM}begin------- */ +/******************** Stage 1: State Register **********************/ +assign is_idle = (cur_state == IDLE ); +assign is_forward = (cur_state == FORWARD ); +assign is_tmp_cycle = (cur_state == TMP_CYCLE); + +// Last cycle (not eop) to forward +assign is_forward_last = is_forward & in_reg_valid & in_reg_ready & in_reg_last; +assign is_tmp_cycle_last = is_tmp_cycle & con_out_valid & con_out_ready & con_out_last; + +assign is_trans_last = !j_tmp_cycle & is_forward_last & !in_reg_eop; +assign is_trans_eop = (!j_tmp_cycle & is_forward_last & in_reg_eop) | is_tmp_cycle_last; + +assign j_forward = (is_idle & st_valid & st_ready) || + (is_forward_last & st_valid & st_ready) || + (is_tmp_cycle_last & st_valid & st_ready); + +assign j_tmp_cycle = in_reg_eop & (concat_blen > `DMA_W_BCNT); + +always @(posedge dma_clk, negedge rst_n) begin + if(~rst_n) + cur_state <= `TD IDLE; + else + cur_state <= `TD nxt_state; +end + +/******************** Stage 2: State Transition **********************/ +always @(*) begin + case(cur_state) + IDLE: begin + if (st_valid & st_ready) begin + nxt_state = FORWARD; + end + else begin + nxt_state = IDLE; + end + end + FORWARD: begin + if (in_reg_valid & in_reg_ready & in_reg_last) begin + if (in_reg_eop & (concat_blen > `DMA_W_BCNT)) begin + nxt_state = TMP_CYCLE; + end + else if (st_valid & st_ready) begin + nxt_state = FORWARD; + end + else begin + nxt_state = IDLE; + end + end + else begin + nxt_state = FORWARD; + end + end + TMP_CYCLE: begin + if (con_out_valid & con_out_ready & con_out_last) begin + if (st_valid & st_ready) begin + nxt_state = FORWARD; + end + else begin + nxt_state = IDLE; + end + end + else begin + nxt_state = TMP_CYCLE; + end + end + default: begin + nxt_state = IDLE; + end + endcase +end +/******************** Stage 3: Output **********************/ + +assign tmp_data = in_reg_first ? tmp_sram_data : tmp_reg_data; +assign tmp_blen = in_reg_first ? tmp_sram_blen : tmp_reg_blen; +/* -------{Temp data get FSM}end------- */ + +/* --------temp data storge{begin}-------- */ +assign temp_wen = !is_fast_forward & ( + is_trans_last | // When it is not the eop pkt, write back the remained tmp data + is_trans_eop // When it is the eop pkt, clear the tmp sram entry + ); +assign temp_waddr = concat_tag; +assign temp_din = is_trans_last ? + ((concat_blen >= `DMA_W_BCNT) ? {con_tmp_blen, con_tmp_data} : {con_out_blen, con_out_data}) : + {`DMA_LEN_WIDTH + `DMA_DATA_W{1'd0}}; // trans_eop is included in this branch + +assign temp_ren = !is_fast_forward & j_forward; +assign temp_raddr = st_rd_rsp_tag; + +pcieifc_sd_sram #( + .DATAWIDTH ( `DMA_LEN_WIDTH + `DMA_DATA_W ), // 269 + .ADDRWIDTH ( `TAG_NUM_LOG ) // 64 depth +) temp_data_sram ( + .clk ( dma_clk ), // i, 1 + .rst_n ( rst_n ), // i, 1 + + .wea ( init_done ? temp_wen : 1'd1 ), // i, 1 + .addra ( init_done ? temp_waddr : init_waddr ), // i, ADDRWIDTH + .dina ( init_done ? temp_din : {`DMA_LEN_WIDTH+`DMA_DATA_W{1'd0}} ), // i, DATAWIDTH + + .reb ( temp_ren ), // i, 1 + .addrb ( temp_raddr ), // i, ADDRWIDTH + .doutb ( temp_dout ) // o, DATAWIDTH + +`ifdef PCIEI_APB_DBG + ,.rtsel ( rtsel ) + ,.wtsel ( wtsel ) + ,.ptsel ( ptsel ) + ,.vg ( vg ) + ,.vs ( vs ) +`endif +); + + +assign is_fast_forward = (is_trans_last | is_trans_eop) & // Need write temp data + j_forward & // Need read temp data + (temp_waddr == temp_raddr); // wr & rd the same addr +st_reg #( + .TUSER_WIDTH ( 1 ), + .TDATA_WIDTH ( `DMA_LEN_WIDTH + `DMA_DATA_W ), + .MODE ( 1 ) +) tmp_ff_st_reg ( + .clk ( dma_clk ), // i, 1 + .rst_n ( rst_n ), // i, 1 + + /* -------input axis-like interface{begin}------- */ + .axis_tvalid ( is_fast_forward ), // i, 1 + .axis_tlast ( 1'd0 ), // i, 1 + .axis_tuser ( 1'd0 ), // i, TUSER_WIDTH + .axis_tdata ( temp_din ), // i, TDATA_WIDTH + .axis_tready ( ), // o, 1 + /* -------input axis-like interface{end}------- */ + + /* -------output in_reg inteface{begin}------- */ + .axis_reg_tvalid ( tmp_ff_valid ), // o, 1 + .axis_reg_tlast ( ), // o, 1 + .axis_reg_tuser ( ), // o, TUSER_WIDTH + .axis_reg_tdata ( {tmp_ff_blen, tmp_ff_data} ), // o, TDATA_WIDTH + .axis_reg_tready ( tmp_ff_ready ) // i, 1 + /* -------output in_reg inteface{end}------- */ +); +assign tmp_ff_ready = con_out_ready & in_reg_valid; + +assign tmp_sram_blen = tmp_ff_valid ? tmp_ff_blen : temp_dout[`DMA_LEN_WIDTH+`DMA_DATA_W-1:`DMA_DATA_W]; +assign tmp_sram_data = tmp_ff_valid ? tmp_ff_data : temp_dout[`DMA_DATA_W-1:0]; +/* --------temp data storge{end}-------- */ + +/* ---------Concat temp & in_reg{begin}-------- */ +assign concat_valid = is_tmp_cycle | in_reg_valid; +assign concat_eop = is_tmp_cycle ? tmp_reg_eop : + is_forward ? (in_reg_valid & in_reg_eop & !j_tmp_cycle) : 0; +assign concat_tag = is_tmp_cycle ? tmp_reg_tag : + is_forward ? ({`TAG_NUM_LOG{in_reg_valid}} & in_reg_tag) : 0; +assign concat_blen = in_reg_blen + tmp_blen; +assign concat_data = (in_reg_data << (tmp_blen << 3)) | tmp_data; +/* ---------Concat temp & in_reg{end}-------- */ + +/* -------tmp_reg{begin}------- */ +assign con_tmp_valid = in_reg_valid & in_reg_ready; +assign con_tmp_last = in_reg_last; +assign con_tmp_tag = in_reg_tag ; +assign con_tmp_data = concat_data[2*`DMA_DATA_W-1:`DMA_DATA_W]; +assign con_tmp_blen = (concat_blen >= `DMA_W_BCNT) ? (concat_blen - `DMA_W_BCNT) : 0; +assign con_tmp_eop = in_reg_eop; + +st_reg #( + .TUSER_WIDTH ( `TAG_NUM_LOG ), + .TDATA_WIDTH ( 1 + `DMA_LEN_WIDTH + `DMA_DATA_W ), + .MODE ( 1 ) +) tmp_st_reg ( + .clk ( dma_clk ), // i, 1 + .rst_n ( rst_n ), // i, 1 + + /* -------input axis-like interface{begin}------- */ + .axis_tvalid ( con_tmp_valid ), // i, 1 + .axis_tlast ( con_tmp_last ), // i, 1 + .axis_tuser ( con_tmp_tag ), // i, TUSER_WIDTH + .axis_tdata ( {con_tmp_eop, con_tmp_blen, con_tmp_data} ), // i, TDATA_WIDTH + .axis_tready ( con_tmp_ready ), // o, 1 + /* -------input axis-like interface{end}------- */ + + /* -------output in_reg inteface{begin}------- */ + .axis_reg_tvalid ( tmp_reg_valid ), // o, 1 + .axis_reg_tlast ( tmp_reg_last ), // o, 1 + .axis_reg_tuser ( tmp_reg_tag ), // o, TUSER_WIDTH + .axis_reg_tdata ( {tmp_reg_eop, tmp_reg_blen, tmp_reg_data} ), // o, TDATA_WIDTH + .axis_reg_tready ( tmp_reg_ready ) // i, 1 + /* -------output in_reg inteface{end}------- */ +); +assign tmp_reg_ready = con_out_ready & concat_valid; +/* -------tmp_reg{end}------- */ + +/* -------out_reg{begin}------- */ +assign con_out_valid = concat_valid & + ((concat_blen >= `DMA_W_BCNT) | concat_eop); // don't write out if beat size is less than 32 & not eop cycle +assign con_out_last = concat_eop; +assign con_out_tag = concat_tag; +assign con_out_data = concat_data[`DMA_DATA_W-1:0]; +assign con_out_blen = concat_blen; + +st_reg #( + .TUSER_WIDTH ( `TAG_NUM_LOG ), + .TDATA_WIDTH ( `DMA_DATA_W ) +) out_st_reg ( + .clk ( dma_clk ), // i, 1 + .rst_n ( rst_n ), // i, 1 + + /* -------input axis-like interface{begin}------- */ + .axis_tvalid ( con_out_valid ), // i, 1 + .axis_tlast ( con_out_last ), // i, 1 + .axis_tuser ( con_out_tag ), // i, TUSER_WIDTH + .axis_tdata ( con_out_data ), // i, TDATA_WIDTH + .axis_tready ( con_out_ready ), // o, 1 + /* -------input axis-like interface{end}------- */ + + /* -------output in_reg inteface{begin}------- */ + .axis_reg_tvalid ( store_fifo_wen ), // o, 1 + .axis_reg_tlast ( store_fifo_last ), // o, 1 + .axis_reg_tuser ( store_fifo_tag ), // o, TUSER_WIDTH + .axis_reg_tdata ( store_fifo_data ), // o, TDATA_WIDTH + .axis_reg_tready ( store_fifo_rdy ) // i, 1 + /* -------output in_reg inteface{end}------- */ +); +/* -------out_reg{end}------- */ + +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/DMA/DMA_Read/tag_buf.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/DMA/DMA_Read/tag_buf.v new file mode 100644 index 0000000000000000000000000000000000000000..25b530ae6babc111d70d7f3a7834545f6d64720f --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/DMA/DMA_Read/tag_buf.v @@ -0,0 +1,192 @@ +`timescale 1ns / 100ps +//************************************************************************* +// > File Name: tag_buf.v +// > Author : Kangning +// > Date : 2023-02-28 +// > Note : tag_buf, store reordered rsp pkt. +//************************************************************************* + +module tag_buf #( + +) ( + input wire dma_clk, // i, 1 + input wire rst_n , // i, 1 + + /* -------- Store related channel {begin}-------- */ + input wire store_wen , // o, 1 + input wire [`TAG_NUM_LOG-1:0] store_tag , // o, `TAG_NUM_LOG + input wire store_last, // o, 1 + input wire [`DMA_DATA_W -1:0] store_data, // o, `DMA_DATA_W + output wire store_rdy , // i, 1 + /* -------- Store related channel {end}-------- */ + + /* -------- Fetch related channel {begin}-------- */ + input wire fetch_ren , // i, 1 + input wire [`TAG_NUM_LOG-1:0] fetch_tag , // i, `TAG_NUM_LOG + output wire fetch_last , // o, 1 ; assert when this is the last sub-rsp pkt + output wire [`DMA_DATA_W -1:0] fetch_data , // o, `DMA_DATA_W + output wire fetch_vld // o, 1 + /* -------- Fetch related channel {end}-------- */ + +`ifdef PCIEI_APB_DBG + /* -------APB reated signal{begin}------- */ + ,input wire [`SRAM_RW_DATA_W-1:0] rw_data// i, `SRAM_RW_DATA_W + ,output wire [`TAG_BUF_SIGNAL_W-1:0] dbg_signal // o, `TAG_BUF_SIGNAL_W + /* -------APB reated signal{end}------- */ +`endif +); + +/* -------Index file{begin}------- */ +reg [2:0] rd_idx[`TAG_NUM-1:0]; +reg [2:0] wr_idx[`TAG_NUM-1:0]; +reg [3:0] cnt [`TAG_NUM-1:0]; + +reg rd_data_vld; +wire full, empty; +/* -------Index file{end}------- */ + +/* --------reordered rsp pkt storge{begin}-------- */ +wire buf_wen ; +wire [`TAG_NUM_LOG+3-1:0] buf_waddr ; +wire [1+`DMA_DATA_W -1:0] buf_din ; + +wire buf_ren ; +wire [`TAG_NUM_LOG+3-1:0] buf_raddr ; +wire [1+`DMA_DATA_W -1:0] buf_dout ; +/* --------reordered rsp pkt storge{end}-------- */ + + +`ifdef PCIEI_APB_DBG +/* -------APB reated signal{begin}------- */ +wire [1:0] rtsel; +wire [1:0] wtsel; +wire [1:0] ptsel; +wire vg ; +wire vs ; +/* -------APB reated signal{end}------- */ +`endif + +//--------------------------------------------------------------------------------------------------------------------------- + +`ifdef PCIEI_APB_DBG +/* -------APB reated signal{begin}------- */ +assign {rtsel, wtsel, ptsel, vg, vs} = rw_data; +assign dbg_signal = { // 537 + rd_data_vld, full, empty, // 3 + buf_wen, buf_waddr, buf_din , // 267 + buf_ren, buf_raddr, buf_dout // 267 +}; +/* -------APB reated signal{end}------- */ +`endif + +/* -------- Index file update{begin}-------- */ +integer i; +always @(posedge dma_clk, negedge rst_n) begin + if (~rst_n) begin + for (i = 0; i < `TAG_NUM; i = i + 1) begin + rd_idx[i] <= `TD 0; + end + end + else if (fetch_ren) begin + rd_idx[fetch_tag] <= `TD rd_idx[fetch_tag] + !empty; + end +end + +integer j; +always @(posedge dma_clk, negedge rst_n) begin + if (~rst_n) begin + for (j = 0; j < `TAG_NUM; j = j + 1) begin + wr_idx[j] <= `TD 0; + end + end + else if (store_wen) begin + wr_idx[store_tag] <= `TD wr_idx[store_tag] + !full; + end +end + +integer k; +always @(posedge dma_clk, negedge rst_n) begin + if (~rst_n) begin + for (k = 0; k < `TAG_NUM; k = k + 1) begin + cnt[k] <= `TD 0; + end + end + else if ((store_tag == fetch_tag) & + store_wen & fetch_ren) begin // store and fetch the same buffer + cnt[store_tag] <= `TD cnt[store_tag] + !full - !empty; + end + else if (store_wen & fetch_ren) begin + cnt[store_tag] <= `TD cnt[store_tag] + !full; + cnt[fetch_tag] <= `TD cnt[fetch_tag] - !empty; + end + else if (store_wen) begin + cnt[store_tag] <= `TD cnt[store_tag] + !full; + end + else if (fetch_ren) begin + cnt[fetch_tag] <= `TD cnt[fetch_tag] - !empty; + end +end +/* -------- Index file update{end}-------- */ + +/* --------Store related logic{begin}-------- */ +assign full = (cnt[store_tag] == 16); + +assign store_rdy = !full; +/* --------Store related logic{end}-------- */ + +/* --------Fetch related logic{begin}-------- */ +assign empty = (cnt[fetch_tag] == 0); + +assign {fetch_last, fetch_data} = fetch_vld ? buf_dout : {1+`DMA_DATA_W{1'd0}}; + +always @(posedge dma_clk, negedge rst_n) begin + if (~rst_n) begin + rd_data_vld <= `TD 1'd0; + end + else if (fetch_last) begin + rd_data_vld <= `TD 1'd0; + end + else if (fetch_ren) begin + rd_data_vld <= `TD buf_ren; + end +end +assign fetch_vld = rd_data_vld; +/* --------Fetch related logic{end}-------- */ + +/* --------reordered rsp pkt storge{begin}-------- */ +assign buf_wen = store_wen & store_rdy; +assign buf_waddr = (store_tag << 3) + wr_idx[store_tag]; +assign buf_din = {store_last, store_data}; + +assign buf_ren = fetch_ren & !empty; +assign buf_raddr = (fetch_tag << 3) + rd_idx[fetch_tag]; + +pcieifc_sd_sram #( + .DATAWIDTH ( 1 + `DMA_DATA_W ), // 257 + .ADDRWIDTH ( `TAG_NUM_LOG + 3 ) // 512 depth +) reorder_buf ( + .clk ( dma_clk ), // i, 1 + .rst_n ( rst_n ), // i, 1 + + .wea ( buf_wen ), // i, 1 + .addra ( buf_waddr ), // i, ADDRWIDTH + .dina ( buf_din ), // i, DATAWIDTH + + .reb ( buf_ren ), // i, 1 + .addrb ( buf_raddr ), // i, ADDRWIDTH + .doutb ( buf_dout ) // o, DATAWIDTH + +`ifdef PCIEI_APB_DBG + ,.rtsel ( rtsel ) + ,.wtsel ( wtsel ) + ,.ptsel ( ptsel ) + ,.vg ( vg ) + ,.vs ( vs ) +`endif +); + +/* --------reordered rsp pkt storge{end}-------- */ + + + +endmodule diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/DMA/DMA_Read/tag_matching.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/DMA/DMA_Read/tag_matching.v new file mode 100644 index 0000000000000000000000000000000000000000..5e9c9f97159e4633af1356b3eec9a02d86b59062 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/DMA/DMA_Read/tag_matching.v @@ -0,0 +1,199 @@ +`timescale 1ns / 100ps +//************************************************************************* +// > File : tag_matching.v +// > Author : Kangning +// > Date : 2022-11-03 +// > Note : Match tags for different channels. +// Note that : +// 1. The channel is under comparsion only when it is not stalled; +// 2. +//************************************************************************* + +module tag_matching #( + +) ( + input wire dma_clk, // i, 1 + input wire rst_n , // i, 1 + + /* -------tag release{begin}------- */ + // Note that only one channel is allowed to assert at the same time + output wire [`DMA_RD_CHNL_NUM * 1 - 1 : 0] tag_rrsp_ready, // o, 1 + input wire [`DMA_RD_CHNL_NUM * 1 - 1 : 0] tag_rrsp_last , // i, 1 + input wire [`DMA_RD_CHNL_NUM * `DW_LEN_WIDTH - 1 : 0] tag_rrsp_sz , // i, `DW_LEN_WIDTH + input wire [`DMA_RD_CHNL_NUM * `TAG_MISC - 1 : 0] tag_rrsp_misc , // i, `TAG_MISC ; Including addr && dw empty info + input wire [`DMA_RD_CHNL_NUM * `TAG_NUM_LOG - 1 : 0] tag_rrsp_tag , // i, `TAG_NUM_LOG + input wire [`DMA_RD_CHNL_NUM * 1 - 1 : 0] tag_rrsp_valid, // i, 1 + /* -------tag release{end}------- */ + + /* ------- Read Response input{begin} ------- */ + input wire st_rd_rsp_wen , // i, 1 + input wire st_rd_rsp_last, // i, 1 ; assert in every last beat of sub-rsp pkt + input wire [`DW_LEN_WIDTH-1:0] st_rd_rsp_dlen, // i, `DW_LEN_WIDTH ; part of head field in "store channel" + input wire [`TAG_NUM_LOG -1:0] st_rd_rsp_tag , // i, `TAG_NUM_LOG ; part of head field in "store channel" + input wire st_rd_rsp_rdy , // i, 1 + /* ------- Read Response input{end} ------- */ + + /* --------chnl_stall{begin}-------- */ + input wire [`DMA_RD_CHNL_NUM - 1 : 0] chnl_avail, // i, `DMA_RD_CHNL_NUM + /* --------chnl_stall{end}-------- */ + + /* -------tag release{begin}------- */ + input wire nxt_match_ready, // i, 1 + output wire nxt_match_last , // o, 1 + output wire [`DW_LEN_WIDTH-1:0] nxt_match_sz , // o, `DW_LEN_WIDTH + output wire [`TAG_MISC -1:0] nxt_match_misc , // o, `TAG_MISC ; Including addr && dw empty info + output wire [8 -1:0] nxt_match_chnl , // o, 8 + output wire [`TAG_NUM_LOG -1:0] nxt_match_tag , // o, `TAG_NUM_LOG + output wire nxt_match_valid // o, 1 + /* -------tag release{end}------- */ + +`ifdef PCIEI_APB_DBG + /* -------APB reated signal{begin}------- */ + ,input wire [31:0] dbg_sel // i, 32 + ,output wire [31:0] dbg_bus // o, 32 + /* -------APB reated signal{end}------- */ +`endif +); + +localparam CHNL_DATA_W = (`TAG_NUM_LOG + 8 + `DW_LEN_WIDTH + 1 + `TAG_MISC); + +/* -------rebuf log SRAM{begin}------- */ +reg rebuf_log_sram_tag [`TAG_NUM-1:0]; // store all the tags in reorder buffer. +reg [`DW_LEN_WIDTH-1:0] rebuf_log_sram_len [`TAG_NUM-1:0]; // Store all the accumulate len stored + // in reorder buffer (in dw unit). +/* -------rebuf log SRAM{end}------- */ + +/* -------tag release{begin}------- */ +// Note that only one channel is allowed to assert at the same time +wire [1 - 1 : 0] tag_chnl_last [`DMA_RD_CHNL_NUM-1:0]; +wire [`DW_LEN_WIDTH - 1 : 0] tag_chnl_sz [`DMA_RD_CHNL_NUM-1:0]; +wire [`TAG_MISC - 1 : 0] tag_chnl_misc [`DMA_RD_CHNL_NUM-1:0]; +wire [8 - 1 : 0] tag_chnl_chnl [`DMA_RD_CHNL_NUM-1:0]; +wire [`TAG_NUM_LOG - 1 : 0] tag_chnl_tag [`DMA_RD_CHNL_NUM-1:0]; +wire [1 - 1 : 0] is_chnl_match [`DMA_RD_CHNL_NUM-1:0]; +wire [`DMA_RD_CHNL_NUM * 1 - 1 : 0] tag_chnl_valid; +wire [`DMA_RD_CHNL_NUM * CHNL_DATA_W - 1 : 0] tag_chnl_data ; +wire [`DMA_RD_CHNL_NUM * 1 - 1 : 0] tag_chnl_ready; +/* -------tag release{end}------- */ + +`ifdef PCIEI_APB_DBG +/* -------APB reated signal{begin}------- */ +wire [`TAG_MATCHING_SIGNAL_W-1:0] dbg_signal; +/* -------APB reated signal{end}------- */ +`endif + +//---------------------------------------------------------------------------------------------------------------------- + +`ifdef PCIEI_APB_DBG +/* -------APB reated signal{begin}------- */ +generate +if (`DMA_RD_CHNL_NUM == 9) begin: CHNL_NUM9 + +assign dbg_bus = dbg_signal >> {dbg_sel, 5'd0}; + +assign dbg_signal = { // 693 + tag_chnl_last[0], tag_chnl_sz[0], tag_chnl_misc[0], tag_chnl_chnl[0], tag_chnl_tag[0], is_chnl_match[0], + tag_chnl_last[1], tag_chnl_sz[1], tag_chnl_misc[1], tag_chnl_chnl[1], tag_chnl_tag[1], is_chnl_match[1], + tag_chnl_last[2], tag_chnl_sz[2], tag_chnl_misc[2], tag_chnl_chnl[2], tag_chnl_tag[2], is_chnl_match[2], + tag_chnl_last[3], tag_chnl_sz[3], tag_chnl_misc[3], tag_chnl_chnl[3], tag_chnl_tag[3], is_chnl_match[3], + tag_chnl_last[4], tag_chnl_sz[4], tag_chnl_misc[4], tag_chnl_chnl[4], tag_chnl_tag[4], is_chnl_match[4], + tag_chnl_last[5], tag_chnl_sz[5], tag_chnl_misc[5], tag_chnl_chnl[5], tag_chnl_tag[5], is_chnl_match[5], + tag_chnl_last[6], tag_chnl_sz[6], tag_chnl_misc[6], tag_chnl_chnl[6], tag_chnl_tag[6], is_chnl_match[6], + tag_chnl_last[7], tag_chnl_sz[7], tag_chnl_misc[7], tag_chnl_chnl[7], tag_chnl_tag[7], is_chnl_match[7], + tag_chnl_last[8], tag_chnl_sz[8], tag_chnl_misc[8], tag_chnl_chnl[8], tag_chnl_tag[8], is_chnl_match[8], // 9 * 39 + tag_chnl_valid, tag_chnl_data, tag_chnl_ready // 9 * 38 +}; +end +endgenerate +/* -------APB reated signal{end}------- */ +`endif + +/* -------Generate block{begin}------- */ +genvar i; +generate +for (i = 0; i < `DMA_RD_CHNL_NUM; i = i + 1) begin:TAG_CHNL + + assign tag_chnl_last [i] = tag_rrsp_last [(i+1) * 1 - 1 : i * 1 ]; + assign tag_chnl_sz [i] = tag_rrsp_sz [(i+1) * `DW_LEN_WIDTH - 1 : i * `DW_LEN_WIDTH]; + assign tag_chnl_misc [i] = tag_rrsp_misc [(i+1) * `TAG_MISC - 1 : i * `TAG_MISC ]; + assign tag_chnl_chnl [i] = i; + assign tag_chnl_tag [i] = tag_rrsp_tag [(i+1) * `TAG_NUM_LOG - 1 : i * `TAG_NUM_LOG ]; + assign is_chnl_match [i] = rebuf_log_sram_tag[tag_chnl_tag[i]] & // has returned rsp for this tag + (rebuf_log_sram_len[tag_chnl_tag[i]] == tag_chnl_sz[i]) & // all sub_rsp has returned + chnl_avail[i]; // the channel is not blocked + + assign tag_chnl_valid[i] = tag_rrsp_valid[i] & // The channel tag is valid + is_chnl_match[i]; // Choose the ready channel + assign tag_chnl_data[(i+1)*CHNL_DATA_W-1:i*CHNL_DATA_W] = {tag_chnl_tag[i], tag_chnl_chnl[i], tag_chnl_sz[i], tag_chnl_last[i], tag_chnl_misc[i]}; + assign tag_rrsp_ready[i] = tag_chnl_ready[i]; + +end +endgenerate +/* -------Generate block{end}------- */ + +/* -------Reordered TAG info stored in RAM{begin}------- */ +integer j; +always @(posedge dma_clk, negedge rst_n) begin + if (~rst_n) begin + for (j = 0; j < `TAG_NUM; j = j+1) begin + rebuf_log_sram_tag[j] <= `TD 1'd0; + rebuf_log_sram_len[j] <= `TD {`DW_LEN_WIDTH{1'd0}}; + end + end + else begin + if (nxt_match_valid & nxt_match_ready & (st_rd_rsp_wen & st_rd_rsp_rdy & st_rd_rsp_last)) begin + rebuf_log_sram_tag[nxt_match_tag] <= `TD 1'd0; + rebuf_log_sram_len[nxt_match_tag] <= `TD {`DW_LEN_WIDTH{1'd0}}; + rebuf_log_sram_tag[st_rd_rsp_tag] <= `TD 1'd1; + rebuf_log_sram_len[st_rd_rsp_tag] <= `TD rebuf_log_sram_len[st_rd_rsp_tag] + st_rd_rsp_dlen; + end + else if (nxt_match_valid & nxt_match_ready) begin /* clear the info before entering the forward state */ + rebuf_log_sram_tag[nxt_match_tag] <= `TD 1'd0; + rebuf_log_sram_len[nxt_match_tag] <= `TD {`DW_LEN_WIDTH{1'd0}}; + end + else if (st_rd_rsp_wen & st_rd_rsp_rdy & st_rd_rsp_last) begin /* store the info only when the last cycle of the storage */ + rebuf_log_sram_tag[st_rd_rsp_tag] <= `TD 1'd1; + rebuf_log_sram_len[st_rd_rsp_tag] <= `TD rebuf_log_sram_len[st_rd_rsp_tag] + st_rd_rsp_dlen; + end + end +end +/* -------Reordered TAG info stored in RAM{end}------- */ + +/* --------Next rsp channel{begin}-------- */ +st_mux #( + .CHNL_NUM ( `DMA_RD_CHNL_NUM ), // number of slave signals to arbit + .CHNL_NUM_LOG ( `DMA_RD_CHNL_NUM_LOG ), + .TUSER_WIDTH ( 1 ), + .TDATA_WIDTH ( CHNL_DATA_W ) +) st_mux_tag_chnl ( + .clk ( dma_clk ), // i, 1 + .rst_n ( rst_n ), // i, 1 + + /* -------Slave AXIS Interface{begin}------- */ + .s_axis_mux_tvalid ( tag_chnl_valid ), + .s_axis_mux_tlast ( tag_chnl_valid ), + .s_axis_mux_tdata ( tag_chnl_data ), + .s_axis_mux_tuser ( {`DMA_RD_CHNL_NUM{1'b0}} ), // i, CHNL_NUM + .s_axis_mux_tready ( tag_chnl_ready ), + /* -------Slave AXIS Interface{end}------- */ + + /* ------- Master AXIS Interface{begin} ------- */ + .m_axis_mux_tvalid ( nxt_match_valid ), + .m_axis_mux_tlast ( ), + .m_axis_mux_tdata ( {nxt_match_tag, nxt_match_chnl, nxt_match_sz, nxt_match_last, nxt_match_misc} ), + .m_axis_mux_tuser ( ), + .m_axis_mux_tready ( nxt_match_ready ) + /* ------- Master AXIS Interface{end} ------- */ + +`ifdef SIMULATION + /* ------- Debug interface {begin}------- */ + /* | reserved | idx | end | out | + * | 255:CHNL_NUM_LOG+2 | CHNL_NUM_LOG+2-1:2 | 1 | 0 | + */ + ,.debug ( ) + /* ------- Debug interface {end}------- */ +`endif +); +/* --------Next rsp channel{end}-------- */ + +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/DMA/DMA_Read/tag_request.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/DMA/DMA_Read/tag_request.v new file mode 100644 index 0000000000000000000000000000000000000000..6be3dad0fbf442c224db843e8af4e03e8a223cf6 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/DMA/DMA_Read/tag_request.v @@ -0,0 +1,180 @@ +`timescale 1ns / 100ps +//************************************************************************* +// > File Name: tag_request.v +// > Author : Kangning +// > Date : 2022-11-07 +// > Note : tag_request, add tag to the read request. +//************************************************************************* + +module tag_request #( + +) ( + input wire dma_clk, // i, 1 + input wire rst_n , // i, 1 + + /* ------- Connect to rd_req_arbiter module{begin} ------- */ + /* AXI-Stream read request tuser, every read request contains only one beat. + * | chnl_num | Reserved | REQ_TYPE |Tag(inv)| address | Reserved | DW length | first BE | last BE | + * | 127:120 | 119:108 | 107:104 | 103:96 | 95:32 | 31:19 | 18:8 | 7:4 | 3:0 | + */ + input wire axis_rreq_tvalid, // i, 1 + input wire axis_rreq_tlast , // i, 1 + input wire [`DMA_DATA_W -1:0] axis_rreq_tdata , // i, `DMA_DATA_W + input wire [`AXIS_TUSER_W-1:0] axis_rreq_tuser , // i, `AXIS_TUSER_W + input wire [`DMA_KEEP_W -1:0] axis_rreq_tkeep , // i, `DMA_KEEP_W + output wire axis_rreq_tready, // o, 1 + /* ------- Connect to rd_req_arbiter module{end} ------- */ + + /* -------tag request{begin}------- */ + output wire tag_rreq_ready, // o, 1 + output wire tag_rreq_last , // o, 1 ; Indicate the last sub-req for rd req + output wire [`DW_LEN_WIDTH-1:0] tag_rreq_sz , // o, `DW_LEN_WIDTH ; Request size(in dw unit) of this tag + output wire [8 -1:0] tag_rreq_chnl , // o, 8 ; channel number for this request + output wire [`TAG_MISC -1:0] tag_rreq_misc , // o, `TAG_MISC ; Including addr && dw empty info + input wire [`TAG_NUM_LOG -1:0] tag_rreq_tag , // i, `TAG_NUM_LOG + input wire tag_rreq_valid, // i, 1 + /* -------tag request{end}------- */ + + /* -------axis read request interface{begin}------- */ + /* AXI-Stream read request tuser, interact with read request arbiter. + * Only valid in first beat of a packet + * | Reserved | REQ_TYPE | Tag | address | Reserved | DW length | first BE | last BE | + * | 127:108 | 107:104 | 103:96 | 95:32 | 31:19 | 18:8 | 7:4 | 3:0 | + */ + output wire axis_rreq_tag_tvalid, // o, 1 + output wire axis_rreq_tag_tlast , // o, 1 + output wire [`DMA_DATA_W -1:0] axis_rreq_tag_tdata , // o, `DMA_DATA_W + output wire [`AXIS_TUSER_W-1:0] axis_rreq_tag_tuser , // o, `AXIS_TUSER_W + output wire [`DMA_KEEP_W -1:0] axis_rreq_tag_tkeep , // o, `DMA_KEEP_W + input wire axis_rreq_tag_tready // i, 1 + /* -------axis read request interface{end}------- */ + +`ifdef PCIEI_APB_DBG + /* -------APB reated signal{begin}------- */ + ,output wire [`TAG_REQ_SIGNAL_W-1:0] dbg_signal // o, `TAG_REQ_SIGNAL_W + /* -------APB reated signal{end}------- */ +`endif +); + +/* -------State relevant in FSM{begin}------- */ +wire rreq_taged_tvalid; +wire rreq_taged_tlast ; +wire [`AXIS_TUSER_W-1:0] rreq_taged_tuser ; +wire [`DMA_DATA_W -1:0] rreq_taged_tdata ; +wire rreq_taged_tready; +/* -------State relevant in FSM{end}------- */ + +/* -------Head decode{begin}------- */ +wire [8 -1:0] chnl_num ; +wire last_sub_req; +wire [`DW_LEN_WIDTH-1:0] dw_len ; +wire [4 -1:0] req_type ; +wire [`DMA_ADDR_WIDTH-1:0] addr_align; + +wire [`FIRST_BE_WIDTH-1:0] first_be ; +wire [`LAST_BE_WIDTH -1:0] last_be ; +wire [1:0] first_empty ; // Number of invalid bytes in first Double word +wire [1:0] last_empty ; // Number of invalid bytes in last Double word + +wire [`DMA_ADDR_WIDTH-1:0] addr_unalign; +wire [5 -1:0] empty ; +/* -------Head decode{end}------- */ + +/* -------------------------------------------------------------------------------------------------- */ + +`ifdef PCIEI_APB_DBG +/* -------APB reated signal{begin}------- */ +assign dbg_signal = { // 556 + rreq_taged_tvalid, rreq_taged_tlast, rreq_taged_tuser, rreq_taged_tdata, rreq_taged_tready, // 387 + chnl_num, last_sub_req, dw_len, req_type, addr_align, // 88 + first_be, last_be, first_empty, last_empty, // 12 + addr_unalign, empty // 69 +/* -------Head decode{end}------- */ +}; +/* -------APB reated signal{end}------- */ +`endif + +/* -------Head decode{begin}------- */ +/* AXI-Stream read request tuser, every read request contains only one beat. + * | chnl_num | Reserved | REQ_TYPE |Tag(inv)| address | Reserved | DW length | first BE | last BE | + * | 127:120 | 119:108 | 107:104 | 103:96 | 95:32 | 31:19 | 18:8 | 7:4 | 3:0 | + */ +assign chnl_num = axis_rreq_tuser[127:120]; +assign last_sub_req = axis_rreq_tuser[119]; +assign dw_len = axis_rreq_tuser[18 :8 ]; +assign req_type = axis_rreq_tuser[107:104]; +assign addr_align = axis_rreq_tuser[95:32]; +assign first_be = axis_rreq_tuser[7:4]; +assign last_be = axis_rreq_tuser[3:0]; + +assign first_empty = first_be[0] ? 2'd0 : + first_be[1] ? 2'd1 : + first_be[2] ? 2'd2 : + first_be[3] ? 2'd3 : + 2'd0; // unlikely +assign last_empty = (dw_len == 1) ? + (first_be[3] ? 2'd0 : + first_be[2] ? 2'd1 : + first_be[1] ? 2'd2 : 2'd3) : + ({2{(last_be == 4'b1111)}} & 2'd0 | + {2{(last_be == 4'b0001)}} & 2'd3 | + {2{(last_be == 4'b0011)}} & 2'd2 | + {2{(last_be == 4'b0111)}} & 2'd1); + +assign addr_unalign = {addr_align[`DMA_ADDR_WIDTH-1:2], first_empty}; +assign empty = first_empty + last_empty; +// assign byte_len = (dw_len << 2) - first_empty - last_empty; +/* -------Head decode{end}------- */ + +/* --------input request{begin}-------- */ +assign axis_rreq_tready = tag_rreq_valid & rreq_taged_tready; +/* --------input request{end}-------- */ + +/* --------Tag request{begin}-------- */ +assign tag_rreq_ready = axis_rreq_tvalid & rreq_taged_tready; +assign tag_rreq_last = last_sub_req; +assign tag_rreq_sz = dw_len ; +assign tag_rreq_chnl = chnl_num ; +assign tag_rreq_misc = {addr_unalign[6:0], empty}; +/* --------Tag request{end}-------- */ + +/* --------read request output {begin}-------- */ +/* AXI-Stream read request tuser, every read request contains only one beat. + * | Reserved | REQ_TYPE | Tag | address | Reserved | DW length | first BE | last BE | + * | 127:108 | 107:104 | 103:96 | 95:32 | 31:19 | 18:8 | 7:4 | 3:0 | + */ +assign rreq_taged_tvalid = tag_rreq_valid & axis_rreq_tvalid; +assign rreq_taged_tlast = 1'd1; +assign rreq_taged_tdata = {`DMA_DATA_W{1'd0}}; +assign rreq_taged_tuser = {20'd0, req_type, {`TAG_EMPTY+`TAG_WIDTH-`TAG_NUM_LOG{1'd0}}, tag_rreq_tag, axis_rreq_tuser[95:0]}; +/* --------read request output {end}-------- */ + + +/* -------Read Request FIFO{begin}------- */ +st_reg #( + .TUSER_WIDTH ( `AXIS_TUSER_W ), + .TDATA_WIDTH ( `DMA_DATA_W ) +) st_rd_req ( + .clk ( dma_clk ), // i, 1 + .rst_n ( rst_n ), // i, 1 + + /* -------input axis-like interface{begin}------- */ + .axis_tvalid ( rreq_taged_tvalid ), // i, 1 + .axis_tlast ( rreq_taged_tlast ), // i, 1 + .axis_tuser ( rreq_taged_tuser ), // i, TUSER_WIDTH + .axis_tdata ( rreq_taged_tdata ), // i, TDATA_WIDTH + .axis_tready ( rreq_taged_tready ), // o, 1 + /* -------input axis-like interface{end}------- */ + + /* -------output in_reg inteface{begin}------- */ + .axis_reg_tvalid ( axis_rreq_tag_tvalid ), // o, 1 + .axis_reg_tlast ( axis_rreq_tag_tlast ), // o, 1 + .axis_reg_tuser ( axis_rreq_tag_tuser ), // o, TUSER_WIDTH + .axis_reg_tdata ( axis_rreq_tag_tdata ), // o, TDATA_WIDTH + .axis_reg_tready ( axis_rreq_tag_tready ) // i, 1 + /* -------output in_reg inteface{end}------- */ +); +assign axis_rreq_tag_tkeep = {`DMA_KEEP_W{1'd0}}; +/* -------Read Request FIFO{end}------- */ + +endmodule diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/DMA/DMA_Write/wreq_align.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/DMA/DMA_Write/wreq_align.v new file mode 100644 index 0000000000000000000000000000000000000000..ac3aa592b38494152fbacd72129056d7f3e9849f --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/DMA/DMA_Write/wreq_align.v @@ -0,0 +1,357 @@ +`timescale 1ns / 100ps +//************************************************************************* +// > File Name : wreq_align.v +// > Author : Kangning +// > Date : 2021-09-16 +// > Note : transform pkt to dw aligned +// > ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +// > ^ ^ +// > ^ ########## ########### ^ +// > ^ # #------># tmp_reg # ############ ^ +// > ^ ------># in_reg # ###########-----># # ^ +// > ^ # # # out_wire #----> ^ +// > ^ ##########-----------------------># # ^ +// > ^ ############ ^ +// > ^ ^ +// > ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +//************************************************************************* + + +module wreq_align #( + +) ( + input wire clk , // i, 1 + input wire rst_n , // i, 1 + + /* -------dma write request interface{begin}------- */ + /* *_head of DMA interface (interact with RDMA modules), + * valid only in first beat of a packet. + * When Transmiting msi-x interrupt message, 'Byte length' + * should be 0, 'address' means the address of msi-x, and + * msi-x data locates in *_data[31:0]. + * | Resvd | Req Type | address | Reserved | Byte length | + * | | (wr,int) | (msi-x addr) | | (0 for int) | + * |-------|----------|--------------|----------|-------------| + * |127:100| 99:96 | 95:32 | 31:13 | 12:0 | + */ + input wire dma_valid , // i, 1 + input wire dma_last , // i, 1 + input wire [`DMA_HEAD_W-1:0] dma_head , // i, `DMA_HEAD_W + input wire [`DMA_DATA_W-1:0] dma_data , // i, `DMA_DATA_W + output wire dma_ready , // o, 1 + /* -------dma write request interface{end}------- */ + + /* -------aligned write request intrface{begin}------- */ + /* AXI-Stream write request tuser, only valid in first beat of a packet + * | Reserved | REQ_TYPE | Tag | address | Reserved | DW length | first BE | last BE | + * | 127:108 | 107:104 | 103:96 | 95:32 | 31:19 | 18:8 | 7:4 | 3:0 | + * or + * AXI-Stream interrupt request tuser, only valid in first beat of a packet + * | Reserved | REQ_TYPE | Resv | address | Reserved | + * | 127:108 | 107:104 | 103:96 | 95:32 | 31:0 | + */ + output wire align_valid, // o, 1 + output wire align_last , // o, 1 + output wire [`AXIS_TUSER_W-1:0] align_user , // o, `AXIS_TUSER_W + output wire [`DMA_DATA_W -1:0] align_data , // o, `DMA_DATA_W + input wire align_ready // i, 1 + /* -------aligned write request intrface{end}------- */ + +`ifdef PCIEI_APB_DBG + /* -------APB reated signal{begin}------- */ + ,output wire [`WREQ_ALIGN_SIGNAL_W-1:0] dbg_signal // o, `WREQ_ALIGN_SIGNAL_W + /* -------APB reated signal{end}------- */ +`endif +); + +/* -------relate to in_reg{begin}------- */ +reg in_reg_vld ; // read valid from input register +reg [`DMA_HEAD_W-1:0] in_reg_head; +reg [`DMA_DATA_W-1:0] in_reg_data; +wire in_reg_rdy ; + +reg in_reg_sop ; // Indicate the start of a pkt +/* -------relate to in_reg{end}------- */ + +/* -------DW Dealignment FSM{begin}------- */ +localparam FIRST_BEAT = 3'b001, // This state emits first beat (or only bits) of packet. + MID_BEAT = 3'b010, // This state emits middle beat of packet. + LAST_BEAT = 3'b100; // This state emits last beat of packet, in this state, + // in_reg_rdy is not asserted if all data comes from tmp_reg. + +reg [2:0] cur_state; +reg [2:0] nxt_state; + +wire is_first_beat, is_mid_beat, is_last_beat; + +/* Fake last beat for align_* signal. If + * not aligned, this beat should have been + * the last beat. But actually, it's not. + * Note that this signal is different + * from 'in_reg_last' + */ +wire fake_align_last; + +/* + * indicate that next beat is the last beat. + * only valid in 'FIRST_BEAT' and 'MID_BEAT' + * state. */ +wire next_align_last; + +/* Indicate that data in last beat is all from tmp_reg. + * This wire is valid in the whole req. */ +wire is_all_from_tmp; + +/* dw size for last beat. This wire is valid in + * the whole req. */ +wire [$clog2(`DMA_KEEP_W)-1:0] dw_for_last_beat; + +/* Packet trans finished, and req_clear all relevant + * regs. */ +wire req_clear; + +/* align_* signal goes out one beat */ +wire req_go_out; +/* -------DW Dealignment FSM{end}------- */ + +/* -------Head gennerator{begin}------- */ +wire [3:0] req_type; +wire [`DMA_ADDR_WIDTH-1:0] addr ; +wire [`DMA_LEN_WIDTH -1:0] byte_len; +wire [`DMA_ADDR_WIDTH-1:0] aligned_addr ; +wire [`DMA_LEN_WIDTH -1:0] aligned_byte_len; +wire [`DW_LEN_WIDTH -1:0] dw_len ; +wire [`FIRST_BE_WIDTH-1:0] first_be; +wire [`LAST_BE_WIDTH -1:0] last_be ; +wire [2:0] last_bytes; +wire [`AXIS_TUSER_W-1:0] wreq_user; +wire [`AXIS_TUSER_W-1:0] int_user ; + +reg [`DW_LEN_WIDTH-1:0] dw_cnt ; +wire [`DW_LEN_WIDTH-1:0] dw_left; +/* -------Head generator{end}------- */ + +/* -------tmp_reg logic{begin}------- */ +reg [31:0] tmp_reg_data; +/* -------tmp_reg logic{end}------- */ + +/* -------relate to out_reg{begin}------- */ +reg [`DMA_DATA_W-1:0] in_out_data; // transform data between tmp_reg and out_reg +/* -------relate to tmp_reg{end}------- */ + +//--------------------------------------------------------------------------------------------------------------------------- + +`ifdef PCIEI_APB_DBG +/* -------APB reated signal{begin}------- */ +assign dbg_signal = { // 1150 + in_reg_vld, in_reg_head, in_reg_data, in_reg_rdy, // 386 + in_reg_sop, // 1 + cur_state, nxt_state, // 6 + is_first_beat, is_mid_beat, is_last_beat, // 3 + fake_align_last, // 1 + next_align_last, // 1 + is_all_from_tmp, // 1 + dw_for_last_beat, // 3 + req_clear, // 1 + req_go_out, // 1 + + req_type, addr, byte_len, aligned_addr, aligned_byte_len, + dw_len, first_be, last_be, last_bytes, wreq_user, int_user, // 436 + + dw_cnt, dw_left, // 22 + tmp_reg_data, // 32 + in_out_data // 256 +}; +/* -------APB reated signal{end}------- */ +`endif + +/* -------in_reg logic{begin}------- */ +always @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + in_reg_sop <= `TD 1; + end + else if (dma_valid & dma_ready & dma_last) begin + in_reg_sop <= `TD 1; + end + else if (dma_valid & dma_ready & in_reg_sop) begin + in_reg_sop <= `TD 0; + end +end + +always @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + in_reg_head <= `TD 0; + end + else if (dma_valid & dma_ready & in_reg_sop) begin + in_reg_head <= `TD dma_head; + end + else if (req_clear) begin // after trans finished, in_reg_head is set to 0 + in_reg_head <= `TD 0; + end +end + +always @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + in_reg_vld <= `TD 0; + in_reg_data <= `TD 0; + end + else if (dma_valid & dma_ready) begin // write en & not full + in_reg_vld <= `TD 1; + in_reg_data <= `TD dma_data; + end + else if (in_reg_rdy & in_reg_vld) begin // read en & not empty + in_reg_vld <= `TD 0; + in_reg_data <= `TD 0; + end +end + +assign dma_ready = !in_reg_vld | in_reg_rdy; // empty | going to empty +/* -------in_reg logic{end}------- */ + +/* -------Head generator{begin}------ */ +assign req_type = in_reg_head[99:96]; +assign addr = in_reg_head[95:32]; +assign byte_len = in_reg_head[12:0]; +assign aligned_addr = {addr[`DMA_ADDR_WIDTH-1:2], 2'd0}; +assign aligned_byte_len = byte_len + addr[1:0]; +assign dw_len = (aligned_byte_len >> 2) + | aligned_byte_len[1:0]; + +// In our implementation, uncontinuous first_be and last_be are forbidden. +// In our implementation, zero-payload are not allowed, first_be would never be 4'b0000. +assign first_be = ({4{addr[1:0] == 2'b00}} & 4'b1111) | + ({4{addr[1:0] == 2'b01}} & 4'b1110) | + ({4{addr[1:0] == 2'b10}} & 4'b1100) | + ({4{addr[1:0] == 2'b11}} & 4'b1000); +assign last_be = ({4{aligned_byte_len[1:0] == 2'b00}} & 4'b1111) | + ({4{aligned_byte_len[1:0] == 2'b01}} & 4'b0001) | + ({4{aligned_byte_len[1:0] == 2'b10}} & 4'b0011) | + ({4{aligned_byte_len[1:0] == 2'b11}} & 4'b0111); +assign last_bytes = (aligned_byte_len[1:0] == 2'b00) ? 3'b100 : {1'b0, aligned_byte_len[1:0]}; +/* AXI-Stream write request tuser, only valid in first beat of a packet + * | Reserved | REQ_TYPE | Tag | address | Reserved | DW length | first BE | last BE | + * | 127:108 | 107:104 | 103:96 | 95:32 | 31:19 | 18:8 | 7:4 | 3:0 | + */ +assign wreq_user = {20'd0, `DMA_WRITE_REQ, 8'd0, aligned_addr, 13'd0, dw_len, first_be, last_be}; + +/* AXI-Stream interrupt request tuser, only valid in first beat of a packet + * | Reserved | REQ_TYPE | Resv | address | Reserved | + * | 127:108 | 107:104 | 103:96 | 95:32 | 31:0 | + */ +assign int_user = {20'd0, req_type, 8'd0, addr, 32'd0}; + +assign dw_left = dw_len - dw_cnt; +always @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + dw_cnt <= `TD 0; + end + else if (req_clear) begin + dw_cnt <= `TD 0; + end + else if (req_go_out) begin + dw_cnt <= `TD dw_cnt + `DMA_KEEP_W; + end +end +/* -------Head generator{end}------ */ + +/* -------tmp_reg logic{begin}------- */ +always @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + tmp_reg_data <= `TD 0; + end + else if (req_clear) begin // Clear tmp_reg, in case + // next pkt contains invalid data. + tmp_reg_data <= `TD 0; + end + else if (req_go_out) begin // Update tmp_reg when it goes out + tmp_reg_data <= `TD in_reg_data[(`DMA_DATA_W-1)-:32]; + end +end +/* -------tmp_reg logic{end}------- */ + +/* -------out_reg logic{begin}------- */ +assign in_reg_rdy = (is_first_beat | is_mid_beat) & align_ready & !fake_align_last | + (is_last_beat & align_ready); + +assign align_valid = in_reg_vld | + !in_reg_vld & is_last_beat & is_all_from_tmp; +assign align_last = align_valid & (dw_left <= `DMA_KEEP_W); +assign align_user = (req_type == `DMA_INT_REQ) ? int_user : wreq_user; +assign align_data = (req_type == `DMA_INT_REQ) ? in_reg_data : in_out_data; +always @(*) begin + if (is_last_beat & is_all_from_tmp) begin + case (addr[1:0]) + 2'd0: in_out_data = in_reg_data; + 2'd1: in_out_data = {{`DMA_DATA_W - 8 * 1{1'd0}}, tmp_reg_data[(32 - 1)-:(8 * 1)]}; + 2'd2: in_out_data = {{`DMA_DATA_W - 8 * 2{1'd0}}, tmp_reg_data[(32 - 1)-:(8 * 2)]}; + 2'd3: in_out_data = {{`DMA_DATA_W - 8 * 3{1'd0}}, tmp_reg_data[(32 - 1)-:(8 * 3)]}; + endcase + end + else if (is_first_beat | is_mid_beat | is_last_beat) begin + case (addr[1:0]) + 2'd0: in_out_data = in_reg_data; + 2'd1: in_out_data = {in_reg_data[`DMA_DATA_W - 8 * 1 - 1: 0], tmp_reg_data[(32 - 1)-:(8 * 1)]}; + 2'd2: in_out_data = {in_reg_data[`DMA_DATA_W - 8 * 2 - 1: 0], tmp_reg_data[(32 - 1)-:(8 * 2)]}; + 2'd3: in_out_data = {in_reg_data[`DMA_DATA_W - 8 * 3 - 1: 0], tmp_reg_data[(32 - 1)-:(8 * 3)]}; + endcase + end + else begin + in_out_data = 0; + end +end +/* -------out_reg logic{end}------- */ + +/* -------DW Dealignment FSM{begin}------- */ +/******************** Stage 1: State Register **********************/ +assign fake_align_last = is_all_from_tmp & next_align_last; +assign next_align_last = (dw_left <= `DMA_KEEP_W * 2) & (dw_left > `DMA_KEEP_W); +assign is_all_from_tmp = (dw_for_last_beat == 1) & (last_bytes <= addr[1:0]); +assign dw_for_last_beat = dw_len[$clog2(`DMA_KEEP_W)-1:0]; +assign req_clear = req_go_out & align_last; +assign req_go_out = align_valid & align_ready; + +assign is_first_beat = (cur_state == FIRST_BEAT); +assign is_mid_beat = (cur_state == MID_BEAT ); +assign is_last_beat = (cur_state == LAST_BEAT ); + +always @(posedge clk, negedge rst_n) begin + if(~rst_n) + cur_state <= `TD FIRST_BEAT; + else + cur_state <= `TD nxt_state; +end + +/******************** Stage 2: State Transition **********************/ + +always @(*) begin + case(cur_state) + FIRST_BEAT: begin + if (req_clear) // Imlying the only beat + nxt_state = FIRST_BEAT; + else if (req_go_out & next_align_last) + nxt_state = LAST_BEAT; + else if (req_go_out) + nxt_state = MID_BEAT; + else + nxt_state = FIRST_BEAT; + end + MID_BEAT: begin + if (req_go_out & next_align_last) + nxt_state = LAST_BEAT; + else + nxt_state = MID_BEAT; + end + LAST_BEAT: begin + if (req_clear) + nxt_state = FIRST_BEAT; + else + nxt_state = LAST_BEAT; + end + default: begin + nxt_state = FIRST_BEAT; + end + endcase +end +/******************** Stage 3: Output **********************/ +/* -------DW Dealignment FSM{end}------- */ + +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/DMA/DMA_Write/wreq_split.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/DMA/DMA_Write/wreq_split.v new file mode 100644 index 0000000000000000000000000000000000000000..62dced53050b4ce8d48b8d46332f961c0b7433ef --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/DMA/DMA_Write/wreq_split.v @@ -0,0 +1,319 @@ +`timescale 1ns / 100ps +//************************************************************************* +// > File Name : wreq_split.v +// > Author : Kangning +// > Date : 2021-09-16 +// > Note : split one wr req into multiply small subreq +//************************************************************************* +`define DMA_KEEP_MASK {`DMA_KEEP_W{1'd1}} + +module wreq_split #( + +) ( + input wire clk , // i, 1 + input wire rst_n, // i, 1 + + input wire [2:0] max_pyld_sz, // i, 3 + + /* -------aligned write request intrface{begin}------- */ + /* AXI-Stream write request tuser, only valid in first beat of a packet + * | Reserved | REQ_TYPE | Tag | address | Reserved | DW length | first BE | last BE | + * | 127:108 | 107:104 | 103:96 | 95:32 | 31:19 | 18:8 | 7:4 | 3:0 | + * or + * AXI-Stream interrupt request tuser, only valid in first beat of a packet + * | Reserved | REQ_TYPE | Resv | address | Reserved | + * | 127:108 | 107:104 | 103:96 | 95:32 | 31:0 | + */ + input wire align_valid, // i, 1 + input wire align_last , // i, 1 + input wire [`AXIS_TUSER_W-1:0] align_user , // i, `AXIS_TUSER_W + input wire [`DMA_DATA_W -1:0] align_data , // i, `DMA_DATA_W + output wire align_ready, // o, 1 + /* -------aligned write request intrface{end}------- */ + + /* -------axis write request interface{begin}------- */ + /* AXI-Stream write request tuser, only valid in first beat of a packet + * | Reserved | REQ_TYPE | Tag | address | Reserved | DW length | first BE | last BE | + * | 127:108 | 107:104 | 103:96 | 95:32 | 31:19 | 18:8 | 7:4 | 3:0 | + * or + * AXI-Stream interrupt request tuser, only valid in first beat of a packet + * | Reserved | REQ_TYPE | Resv | address | Reserved | + * | 127:108 | 107:104 | 103:96 | 95:32 | 31:0 | + */ + output wire axis_wr_req_tvalid, + output wire axis_wr_req_tlast , + output wire [`DMA_DATA_W -1:0] axis_wr_req_tdata , + output wire [`AXIS_TUSER_W-1:0] axis_wr_req_tuser , + output wire [`DMA_KEEP_W -1:0] axis_wr_req_tkeep , + input wire axis_wr_req_tready + /* -------axis write request interface{end}------- */ + +`ifdef PCIEI_APB_DBG + /* -------APB reated signal{begin}------- */ + ,output wire [`WREQ_SPLIT_SIGNAL_W-1:0] dbg_signal // o, `WREQ_SPLIT_SIGNAL_W + /* -------APB reated signal{end}------- */ +`endif +); + +/* -------Constant Value{begin}------- */ +localparam MIN_DWORD_SZ_LOG = 5; // min dwords size for 128B axis packet (2 ^ 5 Dword) +wire [`DW_LEN_WIDTH-1:0] max_pyld_dw; // Maximum payload size in dw (in one sub req) +/* -------Constant Value{end}------- */ + +/* -------relate to in_reg{begin}------- */ +reg in_reg_vld ; // read valid from input register +reg [`AXIS_TUSER_W-1:0] in_reg_user; +reg [`DMA_DATA_W -1:0] in_reg_data; +wire [`DMA_KEEP_W -1:0] in_reg_keep; +wire in_reg_rdy ; + +reg in_reg_sop ; // Indicate the start of a pkt +/* -------relate to in_reg{end}------- */ + +/* -------Head relevant{begin}------- */ +// align user decode +wire [`DW_LEN_WIDTH -1:0] dw_len ; +wire [`FIRST_BE_WIDTH-1:0] first_be; +wire [`LAST_BE_WIDTH -1:0] last_be ; +wire [`DMA_ADDR_WIDTH-1:0] addr ; +wire [3:0] req_type; + +// axis_tuser decode +wire [`DW_LEN_WIDTH -1:0] sub_dw_len ; +wire [`FIRST_BE_WIDTH-1:0] sub_first_be; +wire [`LAST_BE_WIDTH -1:0] sub_last_be ; +wire [`DMA_ADDR_WIDTH-1:0] sub_addr ; + +reg [`DW_LEN_WIDTH -1:0] dw_cnt , sub_dw_cnt ; +wire [`DW_LEN_WIDTH -1:0] dw_left, sub_dw_left; +wire [`DW_LEN_WIDTH -1:0] dw_left_dyn; // how many dw left, count down in dynamically + +wire [`AXIS_TUSER_W-1:0] int_tuser, wreq_tuser; +/* -------Head relevant{end}------- */ + +/* -------Split packet{begin}------- */ +wire first_sub_req, last_sub_req; +wire next_req_last, next_sub_last; +/* -------Split packet{end}------- */ + +/* -------State relevant in FSM{begin}------- */ +localparam IDLE = 4'b0001, + TX = 4'b0010, // Transmit normal beat. + SUB_LAST = 4'b0100, // TX the last beat of sub req. + REQ_LAST = 4'b1000; // TX the last beat of the enire req +reg [3:0] cur_state; +reg [3:0] nxt_state; +wire is_idle, is_tx, is_sub_last, is_req_last; + +wire beat_go ; // When asserted, one beat go out of axis_* interface +wire sub_clear; // When asserted, last beat of sub req are forwarded +wire req_clear; // When asserted, last beat of entire req are forwarded +/* -------State relevant in FSM{end}------- */ + +//--------------------------------------------------------------------------------------------------------------------------- + +`ifdef PCIEI_APB_DBG +/* -------APB reated signal{begin}------- */ +assign dbg_signal = { // 906 + max_pyld_dw, // 11 + in_reg_vld, in_reg_user, in_reg_data, in_reg_keep, in_reg_rdy, // 394 + in_reg_sop, // 1 + dw_len, first_be, last_be, addr, req_type, // 87 + sub_dw_len, sub_first_be, sub_last_be, sub_addr, // 83 + dw_cnt, sub_dw_cnt, // 22 + dw_left, sub_dw_left, // 22 + dw_left_dyn, // 11 + int_tuser, wreq_tuser, // 256 + first_sub_req, last_sub_req, // 2 + next_req_last, next_sub_last, // 2 + cur_state, nxt_state, // 8 + is_idle, is_tx, is_sub_last, is_req_last, // 4 + beat_go, sub_clear, req_clear // 3 +}; +/* -------APB reated signal{end}------- */ +`endif + +/* -------Constant Value{begin}------- */ +assign max_pyld_dw = 1'd1 << (MIN_DWORD_SZ_LOG + max_pyld_sz); +/* -------Constant Value{end}------- */ + +/* -------in_reg logic{begin}------- */ +always @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + in_reg_sop <= `TD 1; + end + else if (align_valid & align_ready & align_last) begin + in_reg_sop <= `TD 1; + end + else if (align_valid & align_ready & in_reg_sop) begin + in_reg_sop <= `TD 0; + end +end + +always @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + in_reg_user <= `TD 0; + end + else if (align_valid & align_ready & in_reg_sop) begin + in_reg_user <= `TD align_user; + end + else if (req_clear) begin // after trans finished, in_reg_user is set to 0 + in_reg_user <= `TD 0; + end +end + +always @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + in_reg_vld <= `TD 0; + in_reg_data <= `TD 0; + end + else if (align_valid & align_ready) begin // write en & not full + in_reg_vld <= `TD 1; + in_reg_data <= `TD align_data; + end + else if (in_reg_rdy & in_reg_vld) begin // read en & not empty + in_reg_vld <= `TD 0; + in_reg_data <= `TD 0; + end +end + +assign align_ready = !in_reg_vld | in_reg_rdy; // empty | going to empty +/* -------in_reg logic{end}------- */ + +/* -------tuser logic{begin}------- */ +assign dw_len = in_reg_user[18:8 ]; +assign first_be = in_reg_user[7 :4 ]; +assign last_be = in_reg_user[3 :0 ]; +assign addr = in_reg_user[95:32]; +assign req_type = in_reg_user[107:104]; + +assign sub_dw_len = last_sub_req ? dw_left : max_pyld_dw; +// assign sub_first_be = ? first_be : 4'b1111; +// assign sub_last_be = last_sub_req ? last_be : 4'b1111; +assign sub_addr = addr + (dw_cnt << 2); + +assign sub_first_be = (dw_len == 1) ? (first_be & last_be) : // when the req only has one DW + (sub_dw_len == 1) ? (4'b1111 & last_be) : // when the sub_req has one DW. + first_sub_req ? first_be : 4'b1111; +assign sub_last_be = (sub_dw_len == 1) ? 4'b0000 : // when the payload has one DW, last_be should be 0. + last_sub_req ? last_be : 4'b1111; + +assign wreq_tuser = {20'd0, req_type, 8'd0, sub_addr, 13'd0, sub_dw_len, sub_first_be, sub_last_be}; +assign int_tuser = {20'd0, req_type, 8'd0, sub_addr, 32'd0}; +/* -------tuser logic{end}------- */ + +/* -------Split packet{begin}------- */ +assign first_sub_req = dw_cnt == 0; +assign last_sub_req = dw_left <= max_pyld_dw; +assign next_req_last = (dw_left_dyn <= `DMA_KEEP_W * 2) & (dw_left_dyn > `DMA_KEEP_W); +assign next_sub_last = (sub_dw_left > `DMA_KEEP_W) & (sub_dw_left <= (`DMA_KEEP_W * 2)); + +assign dw_left_dyn = dw_left - sub_dw_cnt; +assign dw_left = dw_len - dw_cnt; +always @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + dw_cnt <= `TD 0; + end + else if (req_clear) begin + dw_cnt <= `TD 0; + end + else if (sub_clear) begin // beat_go & is_sub_last + dw_cnt <= `TD dw_cnt + max_pyld_dw; + end +end + +assign sub_dw_left = sub_dw_len - sub_dw_cnt; +always @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + sub_dw_cnt <= `TD 0; + end + else if (sub_clear) begin + sub_dw_cnt <= `TD 0; + end + else if (beat_go) begin + sub_dw_cnt <= `TD sub_dw_cnt + `DMA_KEEP_W; + end +end + +/* -------Split packet{end}------- */ + +/* -------{DMA Write Request FSM}begin------- */ +/******************** Stage 1: State Register **********************/ +assign is_idle = (cur_state == IDLE ); +assign is_tx = (cur_state == TX ); +assign is_sub_last = (cur_state == SUB_LAST); +assign is_req_last = (cur_state == REQ_LAST); + +assign beat_go = axis_wr_req_tvalid & axis_wr_req_tready; +assign sub_clear = axis_wr_req_tvalid & axis_wr_req_tready & axis_wr_req_tlast; +assign req_clear = sub_clear & in_reg_sop; + +always @(posedge clk, negedge rst_n) begin + if(~rst_n) + cur_state <= `TD IDLE; + else + cur_state <= `TD nxt_state; +end + +/******************** Stage 2: State Transition **********************/ +always @(*) begin + case(cur_state) + IDLE: begin + if (align_valid & align_ready & align_last) + nxt_state = REQ_LAST; + else if (align_valid & align_ready) + nxt_state = TX; + else + nxt_state = IDLE; + end + TX: begin + if (beat_go & next_req_last) + nxt_state = REQ_LAST; + else if (beat_go & next_sub_last) + nxt_state = SUB_LAST; + else + nxt_state = TX; + end + SUB_LAST: begin + if (sub_clear & next_req_last) + nxt_state = REQ_LAST; + else if (sub_clear) + nxt_state = TX; + else + nxt_state = SUB_LAST; + end + REQ_LAST: begin + if (sub_clear) begin + if (align_valid & align_ready & align_last) // Next req's comming and + // is a one-beat req + nxt_state = REQ_LAST; + else if (align_valid & align_ready) // Next req is comming + nxt_state = TX; + else // No incomming next req + nxt_state = IDLE; + end + else + nxt_state = REQ_LAST; + end + default: begin + nxt_state = IDLE; + end + endcase +end +/******************** Stage 3: Output **********************/ +assign axis_wr_req_tvalid = in_reg_vld; +assign axis_wr_req_tlast = is_req_last | is_sub_last; +assign axis_wr_req_tuser = req_type == `DMA_INT_REQ ? int_tuser : wreq_tuser; +assign axis_wr_req_tdata = in_reg_data; +assign axis_wr_req_tkeep = in_reg_keep; + +assign in_reg_rdy = axis_wr_req_tready; + + +assign in_reg_keep = (sub_dw_left >= 8) ? + `DMA_KEEP_MASK : + (`DMA_KEEP_MASK >> (`DMA_KEEP_W - sub_dw_left)); + +/* -------{DMA Write Request FSM}end------- */ + +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/DMA/DMA_Write/write_request.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/DMA/DMA_Write/write_request.v new file mode 100644 index 0000000000000000000000000000000000000000..99eabb31cd90e14b625acf1b9353045064c06a09 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/DMA/DMA_Write/write_request.v @@ -0,0 +1,209 @@ +`timescale 1ns / 100ps +//************************************************************************* +// > File Name: write_request.v +// > Author : Kangning +// > Date : 2020-08-25 +// > Note : write_request, used to transform DMA write request. +// > Note that the packet must be 4KB aligned. +//************************************************************************* + +//`include "../lib/global_include_h.v" +//`include "../lib/dma_def_h.v" + +module write_request #( + +) ( + input wire clk , + input wire rst_n, + + /* -------dma write request interface{begin}------- */ + /* *_head of DMA interface (interact with RDMA modules), + * valid only in first beat of a packet. + * When Transmiting msi-x interrupt message, 'Byte length' + * should be 0, 'address' means the address of msi-x, and + * msi-x data locates in *_data[31:0]. + * | Resvd | Req Type | address | Reserved | Byte length | + * | | (wr,int) | (msi-x addr) | | (0 for int) | + * |-------|----------|--------------|----------|-------------| + * |127:100| 99:96 | 95:32 | 31:13 | 12:0 | + */ + input wire dma_wr_req_valid, + input wire dma_wr_req_last , + input wire [`DMA_HEAD_W-1:0] dma_wr_req_head , + input wire [`DMA_DATA_W-1:0] dma_wr_req_data , + output wire dma_wr_req_ready, + /* -------dma write request interface{end}------- */ + + /* -------axis write request interface{begin}------- */ + /* AXI-Stream write request tuser, only valid in first beat of a packet + * | Reserved | REQ_TYPE | Tag | address | Reserved | DW length | first BE | last BE | + * | 127:108 | 107:104 | 103:96 | 95:32 | 31:19 | 18:8 | 7:4 | 3:0 | + * or + * AXI-Stream interrupt request tuser, only valid in first beat of a packet + * | Reserved | REQ_TYPE | Resv | address | Reserved | + * | 127:108 | 107:104 | 103:96 | 95:32 | 31:0 | + */ + output wire axis_wr_req_tvalid, + output wire axis_wr_req_tlast , + output wire [`DMA_DATA_W -1:0] axis_wr_req_tdata , // contain only payload + output wire [`AXIS_TUSER_W-1:0] axis_wr_req_tuser , // The field contents are different from dma_*_tuser interface + output wire [`DMA_KEEP_W -1:0] axis_wr_req_tkeep , + input wire axis_wr_req_tready, + /* -------axis write request interface{end}------- */ + + /* -------PCIe fragment property{begin}------- */ + /* This signal indicates the (max payload size & max read request size) agreed in the communication + * 3'b000 -- 128 B + * 3'b001 -- 256 B + * 3'b010 -- 512 B + * 3'b011 -- 1024B + * 3'b100 -- 2048B + * 3'b101 -- 4096B + */ + input wire [2:0] max_pyld_sz , + input wire [2:0] max_rd_req_sz // max read request size + /* -------PCIe fragment property{end}------- */ + +`ifdef PCIEI_APB_DBG + /* -------APB reated signal{begin}------- */ + ,input wire [`SRAM_RW_DATA_W -1:0] rw_data // i, `SRAM_RW_DATA_W + ,output wire [`WR_REQ_SIGNAL_W-1:0] dbg_signal // o, `WR_REQ_SIGNAL_W + /* -------APB reated signal{end}------- */ +`endif +); + +/* -------FIFO -> pkt align{begin}------- */ +wire dma_valid; +wire dma_last ; +wire [`DMA_HEAD_W-1:0] dma_head ; +wire [`DMA_DATA_W-1:0] dma_data ; +wire dma_ready; + +wire dma_empty, dma_full; +/* -------FIFO -> pkt align{end}------- */ + +/* -------FIFO -> pkt align{begin}------- */ +wire align_valid; +wire align_last ; +wire [`DMA_HEAD_W-1:0] align_user ; +wire [`DMA_DATA_W-1:0] align_data ; +wire align_ready; +/* -------FIFO -> pkt align{end}------- */ + +`ifdef PCIEI_APB_DBG +/* -------APB reated signal{begin}------- */ +wire [1:0] rtsel; +wire [1:0] wtsel; +wire [1:0] ptsel; +wire vg ; +wire vs ; + +wire [`WREQ_TOP_SIGNAL_W -1:0] wreq_top_dbg_signal ; +wire [`WREQ_ALIGN_SIGNAL_W-1:0] wreq_align_dbg_signal; +wire [`WREQ_SPLIT_SIGNAL_W-1:0] wreq_split_dbg_signal; +/* -------APB reated signal{end}------- */ +`endif + +//--------------------------------------------------------------------------------------------------------------------------- + +`ifdef PCIEI_APB_DBG +/* -------APB reated signal{begin}------- */ +assign {rtsel, wtsel, ptsel, vg, vs} = rw_data; +assign dbg_signal = {wreq_top_dbg_signal, wreq_align_dbg_signal, wreq_split_dbg_signal}; + +assign wreq_top_dbg_signal = { // 776 + dma_valid, dma_last, dma_head, dma_data, dma_ready, // 387 + dma_empty, dma_full, // 2 + align_valid, align_last, align_user, align_data, align_ready // 387 +}; +/* -------APB reated signal{end}------- */ +`endif + +/* ------- Write Request FIFO{begin}------- */ +pcieifc_sync_fifo #( + .DSIZE ( 1 + `DMA_HEAD_W + `DMA_DATA_W ), // 1 + 128 + 256=385 + .ASIZE ( 7 ) // 128 beats +) data_sync_fifo ( + .clk ( clk ), // i, i + .rst_n ( rst_n ), // i, i + .clr ( 1'd0 ), // i, 1 + + .wen ( dma_wr_req_valid & dma_wr_req_ready ), // i, 1 + .din ( {dma_wr_req_last, dma_wr_req_head, dma_wr_req_data} ), // i, (1 + `DMA_HEAD_W + `DMA_DATA_W) + .full ( dma_full ), // o, 1 + + .ren ( dma_valid & dma_ready ), // i, 1 + .dout ( {dma_last, dma_head, dma_data} ), // o, (1 + `DMA_HEAD_W + `DMA_DATA_W) + .empty( dma_empty ) // o, 1 + +`ifdef PCIEI_APB_DBG + ,.rtsel ( rtsel ) // i, 2 + ,.wtsel ( wtsel ) // i, 2 + ,.ptsel ( ptsel ) // i, 2 + ,.vg ( vg ) // i, 1 + ,.vs ( vs ) // i, 1 +`endif +); +assign dma_wr_req_ready = !dma_full; +assign dma_valid = !dma_empty; +/* ------- Write Request FIFO{end}------- */ + + +/* ------- Align data to DW aligned{begin}------- */ +wreq_align #( + +) wreq_align ( + .clk ( clk ), // i, 1 + .rst_n ( rst_n ), // i, 1 + + .dma_valid ( dma_valid ), // i, 1 + .dma_last ( dma_last ), // i, 1 + .dma_head ( dma_head ), // i, `DMA_HEAD_W + .dma_data ( dma_data ), // i, `DMA_DATA_W + .dma_ready ( dma_ready ), // o, 1 + + .align_valid ( align_valid ), // o, 1 + .align_last ( align_last ), // o, 1 + .align_user ( align_user ), // o, `AXIS_TUSER_W + .align_data ( align_data ), // o, `DMA_DATA_W + .align_ready ( align_ready ) // i, 1 + +`ifdef PCIEI_APB_DBG + /* -------APB reated signal{begin}------- */ + ,.dbg_signal ( wreq_align_dbg_signal ) // o, `WREQ_ALIGN_SIGNAL_W + /* -------APB reated signal{end}------- */ +`endif +); +/* ------- Align data to DW aligned{end}------- */ + +/* ------- Split pkt to fit max_pyld_sz{begin}------- */ +wreq_split #( + +) wreq_split ( + .clk ( clk ), // i, 1 + .rst_n ( rst_n ), // i, 1 + + .max_pyld_sz ( max_pyld_sz ), // i, 3 + + .align_valid ( align_valid ), // i, 1 + .align_last ( align_last ), // i, 1 + .align_user ( align_user ), // i, `AXIS_TUSER_W + .align_data ( align_data ), // i, `DMA_DATA_W + .align_ready ( align_ready ), // o, 1 + + .axis_wr_req_tvalid ( axis_wr_req_tvalid ), // o, 1 + .axis_wr_req_tlast ( axis_wr_req_tlast ), // o, 1 + .axis_wr_req_tdata ( axis_wr_req_tdata ), // o, `DMA_DATA_W + .axis_wr_req_tuser ( axis_wr_req_tuser ), // o, `AXIS_TUSER_W + .axis_wr_req_tkeep ( axis_wr_req_tkeep ), // o, `DMA_KEEP_W + .axis_wr_req_tready ( axis_wr_req_tready ) // i, 1 + +`ifdef PCIEI_APB_DBG + /* -------APB reated signal{begin}------- */ + ,.dbg_signal ( wreq_split_dbg_signal ) // o, `WREQ_SPLIT_SIGNAL_W + /* -------APB reated signal{end}------- */ +`endif +); +/* ------- Split pkt to fit max_pyld_sz{end}------- */ + +endmodule diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/DMA/int_proc.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/DMA/int_proc.v new file mode 100644 index 0000000000000000000000000000000000000000..6d486501cb9aad18904d783cdcfdabfab74e6a49 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/DMA/int_proc.v @@ -0,0 +1,171 @@ +`timescale 1ns / 100ps +//************************************************************************* +// > File Name: int_proc.v +// > Author : Kangning +// > Date : 2021-09-17 +// > Note : Process interrupt request +//************************************************************************* + +module int_proc #( + +) ( + input wire pcie_clk , + input wire pcie_rst_n, + input wire dma_clk , + input wire rst_n , + + input wire int_req_valid, + input wire [31:0] int_req_data , + input wire [63:0] int_req_addr , + output wire int_req_ready, + + /* -------Interrupt Interface Signals{begin}------- */ + input [1:0] cfg_interrupt_msix_enable , + input [1:0] cfg_interrupt_msix_mask , + output [31:0] cfg_interrupt_msix_data , + output [63:0] cfg_interrupt_msix_address , + output cfg_interrupt_msix_int , + input cfg_interrupt_msix_sent , + input cfg_interrupt_msix_fail , + output wire [2:0] cfg_interrupt_msi_function_number + /* -------Interrupt Interface Signals{end}------- */ + +`ifdef PCIEI_APB_DBG + /* -------APB reated signal{begin}------- */ + ,input wire [`SRAM_RW_DATA_W-1:0] rw_data // i, `SRAM_RW_DATA_W + ,output wire [`INT_PROC_SIGNAL_W-1:0] dbg_signal // o, `INT_PROC_SIGNAL_W + /* -------APB reated signal{end}------- */ +`endif +); + +/*-------Interrupt related logic{begin}------- */ +wire int_req_full; + +wire [31:0] int_out_data ; +wire [63:0] int_out_addr ; +wire int_out_empty; +/*-------Interrupt related logic{end}------- */ + +/* -------State relevant in FSM{begin}------- */ +localparam WAIT_SEND = 2'b01, // idle, or send the interrupt + WAIT_RESP = 2'b10; // Wait for the rsp of interrupt +reg [1:0] cur_state; +reg [1:0] nxt_state; +wire is_wait_send, is_wait_resp; +wire j_wait_send, j_wait_resp; + +reg msix_enable; +/* -------State relevant in FSM{end}------- */ + +`ifdef PCIEI_APB_DBG +/* -------APB reated signal{begin}------- */ +wire [1:0] rtsel; +wire [1:0] wtsel; +wire [1:0] ptsel; +wire vg ; +wire vs ; +/* -------APB reated signal{end}------- */ +`endif + +//--------------------------------------------------------------------------------------------------------------------------- + +`ifdef PCIEI_APB_DBG +/* -------APB reated signal{begin}------- */ +assign {rtsel, wtsel, ptsel, vg, vs} = rw_data; +assign dbg_signal = { // 107 + int_req_full, // 1 + int_out_data, int_out_addr, int_out_empty, // 97 + cur_state, nxt_state, // 4 + is_wait_send, is_wait_resp, // 2 + j_wait_send, j_wait_resp, // 2 + msix_enable // 1 +}; +/* -------APB reated signal{end}------- */ +`endif + +/*-------Interrupt related logic{begin}------- */ +assign int_req_ready = ~int_req_full; + +pcieifc_async_fifo #( + .DATA_WIDTH ( (64 + 32) ), + .ADDR_WIDTH ( 4 ) +) async_fifo_int ( + .wr_clk ( dma_clk ), // i, 1 + .rd_clk ( pcie_clk ), // i, 1 + .wrst_n ( rst_n ), // i, 1 + .rrst_n ( pcie_rst_n ), // i, 1 + + .wen ( int_req_valid & int_req_ready), // i, 1 + .din ( {int_req_addr, int_req_data} ), // i, (64 + 32) + .full ( int_req_full ), // o, 1 + + .ren ( j_wait_send & cfg_interrupt_msix_sent & (!int_out_empty) ), // i, 1 + .dout ( {int_out_addr, int_out_data} ), // o, (64 + 32) + .empty ( int_out_empty ) // o, 1 + +`ifdef PCIEI_APB_DBG + ,.rtsel ( rtsel ) // i, 2 + ,.wtsel ( wtsel ) // i, 2 + ,.ptsel ( ptsel ) // i, 2 + ,.vg ( vg ) // i, 1 + ,.vs ( vs ) // i, 1 +`endif +); + +/*-------Interrupt related logic{end}------- */ + +/* -------{DMA Write Request FSM}begin------- */ +/******************** Stage 1: State Register **********************/ +assign is_wait_send = cur_state == WAIT_SEND; +assign is_wait_resp = cur_state == WAIT_RESP; + +assign j_wait_send = is_wait_resp & (cfg_interrupt_msix_sent | + cfg_interrupt_msix_fail | + !msix_enable); +assign j_wait_resp = is_wait_send & msix_enable & !int_out_empty; + +always @(posedge pcie_clk, negedge pcie_rst_n) begin + if(~pcie_rst_n) + msix_enable <= `TD 1'd0; + else + msix_enable <= `TD cfg_interrupt_msix_enable[0]; +end + +always @(posedge pcie_clk, negedge pcie_rst_n) begin + if(~pcie_rst_n) + cur_state <= `TD WAIT_SEND; + else + cur_state <= `TD nxt_state; +end + +/******************** Stage 2: State Transition **********************/ +always @(*) begin + case(cur_state) + WAIT_SEND: begin + if (msix_enable & !int_out_empty) + nxt_state = WAIT_RESP; + else + nxt_state = WAIT_SEND; + end + WAIT_RESP: begin + if (cfg_interrupt_msix_sent | + cfg_interrupt_msix_fail | !msix_enable) + nxt_state = WAIT_SEND; + else + nxt_state = WAIT_RESP; + end + default: begin + nxt_state = WAIT_SEND; + end + endcase +end +/******************** Stage 3: Output **********************/ + +assign cfg_interrupt_msix_data = int_out_data; +assign cfg_interrupt_msix_address = int_out_addr; +assign cfg_interrupt_msix_int = j_wait_resp; +assign cfg_interrupt_msi_function_number = 0; +/* -------{DMA Write Request FSM}end------- */ + + +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/DMA/rc_async_fifos.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/DMA/rc_async_fifos.v new file mode 100644 index 0000000000000000000000000000000000000000..582964965acb59e19ce0284594ca2b2cc3d780f2 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/DMA/rc_async_fifos.v @@ -0,0 +1,114 @@ +`timescale 1ns / 100ps +//************************************************************************* +// > File Name: rc_async_fifos.v +// > Author : Kangning +// > Date : 2021-08-16 +// > Note : rc_async_fifos, used to separate rdma and pcie clock domain, +// > in RC (Requester Completion Channel). +//************************************************************************* + +//`include "../lib/global_include_h.v" + +module rc_async_fifos #( + +) ( + input wire dma_clk , + input wire pcie_clk , + input wire dma_rst_n , + input wire pcie_rst_n, + + /* ------- pcie --> dma interface, pcie part{begin}------- */ + // Requester Completion + /* RC tuser + * | 74:43 | 42 | 41:38 | 37:34 | 33 | 32 | 31:0 | + * | parity | discontinue | is_eof_1 | is_eof_0 | is_sof_1 | is_sof_0 | byte_en | + * | ignore | ignore | ignore | ignore | ignore | ignore | | + */ + input wire pcie_axis_rc_tvalid, // i, 1 + input wire pcie_axis_rc_tlast , // i, 1 + input wire [`DMA_DATA_W-1:0] pcie_axis_rc_tdata , // i, `DMA_DATA_W + input wire [74 :0] pcie_axis_rc_tuser , // i, 75 + input wire [`DMA_KEEP_W-1:0] pcie_axis_rc_tkeep , // i, `DMA_KEEP_W + output wire pcie_axis_rc_tready, // o, 1 + /* ------- pcie --> dma interface, pcie part{end}------- */ + + /* ------- pcie --> dma interface, dma part{begin}------- */ + // Requester Completion + /* RC tuser + * | 74:43 | 42 | 41:38 | 37:34 | 33 | 32 | 31:0 | + * | parity | discontinue | is_eof_1 | is_eof_0 | is_sof_1 | is_sof_0 | byte_en | + * | ignore | ignore | ignore | ignore | ignore | ignore | | + */ + output wire dma_axis_rc_tvalid, // i, 1 + output wire dma_axis_rc_tlast , // i, 1 + output wire [`DMA_DATA_W-1:0] dma_axis_rc_tdata , // i, `DMA_DATA_W + output wire [74 :0] dma_axis_rc_tuser , // i, 75 + output wire [`DMA_KEEP_W-1:0] dma_axis_rc_tkeep , // i, `DMA_KEEP_W + input wire dma_axis_rc_tready // o, 1 + /* ------- pcie --> dma interface, dma part{end}------- */ + +`ifdef PCIEI_APB_DBG + /* -------APB reated signal{begin}------- */ + ,input wire [`SRAM_RW_DATA_W -1:0] rw_data // i, `SRAM_RW_DATA_W + ,output wire [`RC_ASYNC_SIGNAL_W-1:0] dbg_signal // o, `RC_ASYNC_SIGNAL_W + /* -------APB reated signal{end}------- */ +`endif +); +wire pcie_axis_rc_full, dma_axis_rc_empty; +wire [31:0] rc_tuser; + +`ifdef PCIEI_APB_DBG +/* -------APB reated signal{begin}------- */ +wire [1:0] rtsel; +wire [1:0] wtsel; +wire [1:0] ptsel; +wire vg ; +wire vs ; +/* -------APB reated signal{end}------- */ +`endif + +//--------------------------------------------------------------------------------------------------------------------------- + +`ifdef PCIEI_APB_DBG +/* -------APB reated signal{begin}------- */ +assign {rtsel, wtsel, ptsel, vg, vs} = rw_data; +assign dbg_signal = { + pcie_axis_rc_full, dma_axis_rc_empty, + rc_tuser +}; +/* -------APB reated signal{end}------- */ +`endif + +pcieifc_async_fifo #( + .DATA_WIDTH ( (1 + `DMA_KEEP_W + 32 + `DMA_DATA_W) ), + .ADDR_WIDTH ( 6 ) +) pcieifc_async_fifo ( + .wr_clk ( pcie_clk ), // i, 1 + .rd_clk ( dma_clk ), // i, 1 + .wrst_n ( pcie_rst_n ), // i, 1 + .rrst_n ( dma_rst_n ), // i, 1 + + .wen ( pcie_axis_rc_tvalid & pcie_axis_rc_tready ), // i, 1 + .din ( {pcie_axis_rc_tlast, pcie_axis_rc_tkeep, pcie_axis_rc_tuser[31:0], pcie_axis_rc_tdata} ), // i, (1 + `DMA_KEEP_W + 32 + `DMA_DATA_W) + .full ( pcie_axis_rc_full ), // o, 1 + + .ren ( dma_axis_rc_tvalid & dma_axis_rc_tready ), // i, 1 + .dout ( {dma_axis_rc_tlast, dma_axis_rc_tkeep, rc_tuser, dma_axis_rc_tdata} ), // o, (1 + `DMA_KEEP_W + 32 + `DMA_DATA_W) + .empty ( dma_axis_rc_empty ) // o, 1 + +`ifdef PCIEI_APB_DBG + ,.rtsel ( rtsel ) // i, 2 + ,.wtsel ( wtsel ) // i, 2 + ,.ptsel ( ptsel ) // i, 2 + ,.vg ( vg ) // i, 1 + ,.vs ( vs ) // i, 1 +`endif +); + +assign pcie_axis_rc_tready = !pcie_axis_rc_full; +assign dma_axis_rc_tvalid = !dma_axis_rc_empty; + + +assign dma_axis_rc_tuser = {43'd0, rc_tuser}; + +endmodule diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/DMA/req_arbiter.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/DMA/req_arbiter.v new file mode 100644 index 0000000000000000000000000000000000000000..60215933b04ac32ca6b384655291a96ef66573a3 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/DMA/req_arbiter.v @@ -0,0 +1,937 @@ +`timescale 1ns / 100ps +//************************************************************************* +// > File Name: req_arbiter.v +// > Author : Kangning +// > Date : 2020-08-27 +// > Note : req_arbiter is used to arbiter different channels for data transmission +// > V1.1 - 2021-02-04 : Add supporting for five channels +// > V1.5 - 2022-04-24 : Parameterized arbiter, supports arbitrary number of channels +//************************************************************************* + +//`include "../lib/global_include_h.v" + +module req_arbiter #( + parameter CHANNEL_NUM = 8 , // number of slave signals to arbit + parameter CHNL_NUM_LOG = 3 +) ( + input wire dma_clk , + input wire rst_n , + + /* -------Slave AXIS Interface{begin}------- */ + /* AXI-Stream request tuser, only valid in first beat of a packet + * | Reserved | REQ_TYPE | Tag | address | Reserved | DW length | first BE | last BE | + * | 127:108 | 107:104 | 103:96 | 95:32 | 31:19 | 18:8 | 7:4 | 3:0 | + * or + * AXI-Stream interrupt request tuser, only valid in first beat of a packet + * | Reserved | REQ_TYPE | Resv | address | Reserved | + * | 127:108 | 107:104 | 103:96 | 95:32 | 31:0 | + */ + input wire [CHANNEL_NUM * 1 -1:0] s_axis_req_tvalid, + input wire [CHANNEL_NUM * 1 -1:0] s_axis_req_tlast , + input wire [CHANNEL_NUM * `DMA_DATA_W -1:0] s_axis_req_tdata , + input wire [CHANNEL_NUM * `AXIS_TUSER_W-1:0] s_axis_req_tuser , + input wire [CHANNEL_NUM * `DMA_KEEP_W -1:0] s_axis_req_tkeep , + output wire [CHANNEL_NUM * 1 -1:0] s_axis_req_tready, + /* -------Slave AXIS Interface{end}------- */ + + /* ------- Master AXIS Interface{begin} ------- */ + /* AXI-Stream request tuser, only valid in first beat of a packet + * | Reserved | REQ_TYPE | Tag | address | Reserved | DW length | first BE | last BE | + * | 127:108 | 107:104 | 103:96 | 95:32 | 31:19 | 18:8 | 7:4 | 3:0 | + * or + * AXI-Stream interrupt request tuser, only valid in first beat of a packet + * | Reserved | REQ_TYPE | Resv | address | Reserved | + * | 127:108 | 107:104 | 103:96 | 95:32 | 31:0 | + */ + output wire m_axis_req_tvalid, + output wire m_axis_req_tlast , + output wire [`DMA_DATA_W -1:0] m_axis_req_tdata , // contain only payload + output wire [`AXIS_TUSER_W-1:0] m_axis_req_tuser , // The field contents are different from dma_*_tuser interface + output wire [`DMA_KEEP_W -1:0] m_axis_req_tkeep , + input wire m_axis_req_tready + /* ------- Master AXIS Interface{end} ------- */ + +`ifdef PCIEI_APB_DBG + /* -------APB reated signal{begin}------- */ + ,output wire [`ARB_BASE_SIGNAL_W+CHANNEL_NUM*CHNL_NUM_LOG+CHNL_NUM_LOG*3+CHANNEL_NUM-1:0] dbg_signal // o, `WREQ_ALIGN_SIGNAL_W + /* -------APB reated signal{end}------- */ +`endif + +`ifdef SIMULATION + /* ------- Debug interface {begin}------- */ + /* | reserved | idx | end | out | + * | 255:CHNL_NUM_LOG+2 | CHNL_NUM_LOG+2-1:2 | 1 | 0 | + */ + ,output wire [255:0] debug + /* ------- Debug interface {end}------- */ +`endif + +); + +/* ------- Next scheduled channel{begin}------- */ +reg [CHNL_NUM_LOG-1:0] chnl_idx_reg; // Index of channel to be scheduled next time, valid only in REQ_TRANS state. +reg [CHNL_NUM_LOG-1:0] chnl_idx; // Index of channel to be scheduled next time, valid all the time. +reg [CHNL_NUM_LOG-1:0] last_chnl; // Index of last selected channel. + + +/** + * hit relevant channel is hit (hit_priority[3] == 1 means that last + * selected channel is still valid. + */ +wire [CHANNEL_NUM-1:0] hit_priority; + +/** + * index of channel priority in next time, e.g. nxt_priority[1] + * indicates the index of next next channel; while nxt_priority[0] + * indicates the index of next channel. + */ +wire [CHNL_NUM_LOG-1:0] nxt_priority[CHANNEL_NUM-1:0]; + +wire s_channel_tvalid[CHANNEL_NUM-1:0]; +wire s_channel_tlast [CHANNEL_NUM-1:0]; +wire [`DMA_DATA_W -1:0] s_channel_tdata [CHANNEL_NUM-1:0]; +wire [`AXIS_TUSER_W-1:0] s_channel_tuser [CHANNEL_NUM-1:0]; +wire [`DMA_KEEP_W -1:0] s_channel_tkeep [CHANNEL_NUM-1:0]; + + +wire req_last; // last beat of the request +/* ------- Next scheduled channel{end}------- */ + +/* -------State relevant in FSM{begin}------- */ +localparam IDLE = 3'b001, + SCHEDULE = 3'b010, + REQ_TRANS = 3'b100; + +reg [2:0] cur_state; +reg [2:0] nxt_state; + +wire is_idle, is_schedule, is_req_trans; +wire j_req_trans; +// wire j_schedule; +/* -------State relevant in FSM{end}------- */ + +//--------------------------------------------------------------------------------------------------------------------------- + +`ifdef PCIEI_APB_DBG +/* -------APB reated signal{begin}------- */ +generate +if (CHANNEL_NUM == 10) begin:CHNL_DBG_10 + +assign dbg_signal = { + chnl_idx_reg, chnl_idx, last_chnl, hit_priority, + req_last, + cur_state, nxt_state, + is_idle, is_schedule, is_req_trans, + j_req_trans, + nxt_priority[0], nxt_priority[1], nxt_priority[2], nxt_priority[3], nxt_priority[4], + nxt_priority[5], nxt_priority[6], nxt_priority[7], nxt_priority[8], nxt_priority[9] +}; + +end +else if (CHANNEL_NUM == 9) begin:CHNL_DBG_9 + +assign dbg_signal = { + chnl_idx_reg, chnl_idx, last_chnl, hit_priority, + req_last, + cur_state, nxt_state, + is_idle, is_schedule, is_req_trans, + j_req_trans, + nxt_priority[0], nxt_priority[1], nxt_priority[2], nxt_priority[3], nxt_priority[4], + nxt_priority[5], nxt_priority[6], nxt_priority[7], nxt_priority[8] +}; + +end +else if (CHANNEL_NUM == 8) begin:CHNL_DBG_8 + +assign dbg_signal = { + chnl_idx_reg, chnl_idx, last_chnl, hit_priority, + req_last, + cur_state, nxt_state, + is_idle, is_schedule, is_req_trans, + j_req_trans, + nxt_priority[0], nxt_priority[1], nxt_priority[2], nxt_priority[3], nxt_priority[4], + nxt_priority[5], nxt_priority[6], nxt_priority[7] +}; + +end +else if (CHANNEL_NUM == 7) begin:CHNL_DBG_7 + +assign dbg_signal = { + chnl_idx_reg, chnl_idx, last_chnl, hit_priority, + req_last, + cur_state, nxt_state, + is_idle, is_schedule, is_req_trans, + j_req_trans, + nxt_priority[0], nxt_priority[1], nxt_priority[2], nxt_priority[3], nxt_priority[4], + nxt_priority[5], nxt_priority[6] +}; + +end +else if (CHANNEL_NUM == 6) begin:CHNL_DBG_6 + +assign dbg_signal = { + chnl_idx_reg, chnl_idx, last_chnl, hit_priority, + req_last, + cur_state, nxt_state, + is_idle, is_schedule, is_req_trans, + j_req_trans, + nxt_priority[0], nxt_priority[1], nxt_priority[2], nxt_priority[3], nxt_priority[4], + nxt_priority[5] +}; + +end +else if (CHANNEL_NUM == 5) begin:CHNL_DBG_5 + +assign dbg_signal = { + chnl_idx_reg, chnl_idx, last_chnl, hit_priority, + req_last, + cur_state, nxt_state, + is_idle, is_schedule, is_req_trans, + j_req_trans, + nxt_priority[0], nxt_priority[1], nxt_priority[2], nxt_priority[3], nxt_priority[4] +}; + +end +else if (CHANNEL_NUM == 4) begin:CHNL_DBG_4 + +assign dbg_signal = { + chnl_idx_reg, chnl_idx, last_chnl, hit_priority, + req_last, + cur_state, nxt_state, + is_idle, is_schedule, is_req_trans, + j_req_trans, + nxt_priority[0], nxt_priority[1], nxt_priority[2], nxt_priority[3] +}; + +end +else if (CHANNEL_NUM == 3) begin:CHNL_DBG_3 + +assign dbg_signal = { + chnl_idx_reg, chnl_idx, last_chnl, hit_priority, + req_last, + cur_state, nxt_state, + is_idle, is_schedule, is_req_trans, + j_req_trans, + nxt_priority[0], nxt_priority[1], nxt_priority[2] +}; + +end +else if (CHANNEL_NUM == 2) begin:CHNL_DBG_2 + +assign dbg_signal = { + chnl_idx_reg, chnl_idx, last_chnl, hit_priority, + req_last, + cur_state, nxt_state, + is_idle, is_schedule, is_req_trans, + j_req_trans, + nxt_priority[0], nxt_priority[1] +}; + +end +endgenerate +/* -------APB reated signal{end}------- */ +`endif + +`ifdef SIMULATION + /* ------- Debug interface {begin}------- */ + /* | reserved | idx | end | out | + * | 255:CHNL_NUM_LOG+2 | CHNL_NUM_LOG+2-1:2 | 1 | 0 | + */ + assign debug = {{254-CHNL_NUM_LOG{1'd0}}, + chnl_idx, + m_axis_req_tvalid & m_axis_req_tready & m_axis_req_tlast, + m_axis_req_tvalid & m_axis_req_tready}; + /* ------- Debug interface {end}------- */ +`endif + + + +/* -------Find next channel{begin}------- */ + +always @(posedge dma_clk, negedge rst_n) begin + if (~rst_n) begin + last_chnl <= `TD {CHNL_NUM_LOG{1'd0}}; + end + else if (req_last) begin + last_chnl <= `TD chnl_idx; + end +end + +always @(posedge dma_clk, negedge rst_n) begin + if (~rst_n) begin + chnl_idx_reg <= `TD {CHNL_NUM_LOG{1'd0}}; + end + else if (j_req_trans) begin + chnl_idx_reg <= `TD chnl_idx; + end +end + +/* -------Generate block{begin}------- */ +genvar k; +generate +for (k = 0; k < CHANNEL_NUM; k = k + 1) begin:CHNL_PRIORITY + +assign nxt_priority[k] = ((last_chnl + k + 1) >= CHANNEL_NUM) ? + (last_chnl + k + 1 - CHANNEL_NUM) : (last_chnl + k + 1); + +end +endgenerate +/* -------Generate block{end}------- */ + + +/* -------Generate block{begin}------- */ +/* This is used for different Channel Numbers, the default Number is 5 + */ +generate +if (CHANNEL_NUM == 10) begin:CHNL_SEL_10 + +always @(*) begin + if (is_schedule) begin + case (last_chnl) + 0: chnl_idx = hit_priority[0] ? 1 : + hit_priority[1] ? 2 : + hit_priority[2] ? 3 : + hit_priority[3] ? 4 : + hit_priority[4] ? 5 : + hit_priority[5] ? 6 : + hit_priority[6] ? 7 : + hit_priority[7] ? 8 : + hit_priority[8] ? 9 : + hit_priority[9] ? 0 : 1 ; // last branch is chosen when no channel is valid. + 1: chnl_idx = hit_priority[0] ? 2 : + hit_priority[1] ? 3 : + hit_priority[2] ? 4 : + hit_priority[3] ? 5 : + hit_priority[4] ? 6 : + hit_priority[5] ? 7 : + hit_priority[6] ? 8 : + hit_priority[7] ? 9 : + hit_priority[8] ? 0 : + hit_priority[9] ? 1 : 2 ; // last branch is chosen when no channel is valid. + 2: chnl_idx = hit_priority[0] ? 3 : + hit_priority[1] ? 4 : + hit_priority[2] ? 5 : + hit_priority[3] ? 6 : + hit_priority[4] ? 7 : + hit_priority[5] ? 8 : + hit_priority[6] ? 9 : + hit_priority[7] ? 0 : + hit_priority[8] ? 1 : + hit_priority[9] ? 2 : 3 ; // last branch is chosen when no channel is valid. + 3: chnl_idx = hit_priority[0] ? 4 : + hit_priority[1] ? 5 : + hit_priority[2] ? 6 : + hit_priority[3] ? 7 : + hit_priority[4] ? 8 : + hit_priority[5] ? 9 : + hit_priority[6] ? 0 : + hit_priority[7] ? 1 : + hit_priority[8] ? 2 : + hit_priority[9] ? 3 : 4 ; // last branch is chosen when no channel is valid. + 4: chnl_idx = hit_priority[0] ? 5 : + hit_priority[1] ? 6 : + hit_priority[2] ? 7 : + hit_priority[3] ? 8 : + hit_priority[4] ? 9 : + hit_priority[5] ? 0 : + hit_priority[6] ? 1 : + hit_priority[7] ? 2 : + hit_priority[8] ? 3 : + hit_priority[9] ? 4 : 5 ; // last branch is chosen when no channel is valid. + 5: chnl_idx = hit_priority[0] ? 6 : + hit_priority[1] ? 7 : + hit_priority[2] ? 8 : + hit_priority[3] ? 9 : + hit_priority[4] ? 0 : + hit_priority[5] ? 1 : + hit_priority[6] ? 2 : + hit_priority[7] ? 3 : + hit_priority[8] ? 4 : + hit_priority[9] ? 5 : 6 ; // last branch is chosen when no channel is valid. + 6: chnl_idx = hit_priority[0] ? 7 : + hit_priority[1] ? 8 : + hit_priority[2] ? 9 : + hit_priority[3] ? 0 : + hit_priority[4] ? 1 : + hit_priority[5] ? 2 : + hit_priority[6] ? 3 : + hit_priority[7] ? 4 : + hit_priority[8] ? 5 : + hit_priority[9] ? 6 : 7 ; // last branch is chosen when no channel is valid. + 7: chnl_idx = hit_priority[0] ? 8 : + hit_priority[1] ? 9 : + hit_priority[2] ? 0 : + hit_priority[3] ? 1 : + hit_priority[4] ? 2 : + hit_priority[5] ? 3 : + hit_priority[6] ? 4 : + hit_priority[7] ? 5 : + hit_priority[8] ? 6 : + hit_priority[9] ? 7 : 8 ; // last branch is chosen when no channel is valid. + 8: chnl_idx = hit_priority[0] ? 9 : + hit_priority[1] ? 0 : + hit_priority[2] ? 1 : + hit_priority[3] ? 2 : + hit_priority[4] ? 3 : + hit_priority[5] ? 4 : + hit_priority[6] ? 5 : + hit_priority[7] ? 6 : + hit_priority[8] ? 7 : + hit_priority[9] ? 8 : 9 ; // last branch is chosen when no channel is valid. + 9: chnl_idx = hit_priority[0] ? 0 : + hit_priority[1] ? 1 : + hit_priority[2] ? 2 : + hit_priority[3] ? 3 : + hit_priority[4] ? 4 : + hit_priority[5] ? 5 : + hit_priority[6] ? 6 : + hit_priority[7] ? 7 : + hit_priority[8] ? 8 : + hit_priority[9] ? 9 : 0 ; // last branch is chosen when no channel is valid. + default: chnl_idx = {CHNL_NUM_LOG{1'd0}}; + endcase + end + else begin + chnl_idx = chnl_idx_reg; // chosen in REQ_TRANS state + end +end + +end // CHANNEL_NUM == 10 +else if (CHANNEL_NUM == 9) begin:CHNL_SEL_9 + +always @(*) begin + if (is_schedule) begin + case (last_chnl) + 4'd0: chnl_idx = hit_priority[0] ? 4'd1 : + hit_priority[1] ? 4'd2 : + hit_priority[2] ? 4'd3 : + hit_priority[3] ? 4'd4 : + hit_priority[4] ? 4'd5 : + hit_priority[5] ? 4'd6 : + hit_priority[6] ? 4'd7 : + hit_priority[7] ? 4'd8 : + hit_priority[8] ? 4'd0 : 4'd1 ; // last branch is chosen when no channel is valid. + 4'd1: chnl_idx = hit_priority[0] ? 4'd2 : + hit_priority[1] ? 4'd3 : + hit_priority[2] ? 4'd4 : + hit_priority[3] ? 4'd5 : + hit_priority[4] ? 4'd6 : + hit_priority[5] ? 4'd7 : + hit_priority[6] ? 4'd8 : + hit_priority[7] ? 4'd0 : + hit_priority[8] ? 4'd1 : 4'd2 ; // last branch is chosen when no channel is valid. + 4'd2: chnl_idx = hit_priority[0] ? 4'd3 : + hit_priority[1] ? 4'd4 : + hit_priority[2] ? 4'd5 : + hit_priority[3] ? 4'd6 : + hit_priority[4] ? 4'd7 : + hit_priority[5] ? 4'd8 : + hit_priority[6] ? 4'd0 : + hit_priority[7] ? 4'd1 : + hit_priority[8] ? 4'd2 : 4'd3 ; // last branch is chosen when no channel is valid. + 4'd3: chnl_idx = hit_priority[0] ? 4'd4 : + hit_priority[1] ? 4'd5 : + hit_priority[2] ? 4'd6 : + hit_priority[3] ? 4'd7 : + hit_priority[4] ? 4'd8 : + hit_priority[5] ? 4'd0 : + hit_priority[6] ? 4'd1 : + hit_priority[7] ? 4'd2 : + hit_priority[8] ? 4'd3 : 4'd4 ; // last branch is chosen when no channel is valid. + 4'd4: chnl_idx = hit_priority[0] ? 4'd5 : + hit_priority[1] ? 4'd6 : + hit_priority[2] ? 4'd7 : + hit_priority[3] ? 4'd8 : + hit_priority[4] ? 4'd0 : + hit_priority[5] ? 4'd1 : + hit_priority[6] ? 4'd2 : + hit_priority[7] ? 4'd3 : + hit_priority[8] ? 4'd4 : 4'd5 ; // last branch is chosen when no channel is valid. + 4'd5: chnl_idx = hit_priority[0] ? 4'd6 : + hit_priority[1] ? 4'd7 : + hit_priority[2] ? 4'd8 : + hit_priority[3] ? 4'd0 : + hit_priority[4] ? 4'd1 : + hit_priority[5] ? 4'd2 : + hit_priority[6] ? 4'd3 : + hit_priority[7] ? 4'd4 : + hit_priority[8] ? 4'd5 : 4'd6 ; // last branch is chosen when no channel is valid. + 4'd6: chnl_idx = hit_priority[0] ? 4'd7 : + hit_priority[1] ? 4'd8 : + hit_priority[2] ? 4'd0 : + hit_priority[3] ? 4'd1 : + hit_priority[4] ? 4'd2 : + hit_priority[5] ? 4'd3 : + hit_priority[6] ? 4'd4 : + hit_priority[7] ? 4'd5 : + hit_priority[8] ? 4'd6 : 4'd7 ; // last branch is chosen when no channel is valid. + 4'd7: chnl_idx = hit_priority[0] ? 4'd8 : + hit_priority[1] ? 4'd0 : + hit_priority[2] ? 4'd1 : + hit_priority[3] ? 4'd2 : + hit_priority[4] ? 4'd3 : + hit_priority[5] ? 4'd4 : + hit_priority[6] ? 4'd5 : + hit_priority[7] ? 4'd6 : + hit_priority[8] ? 4'd7 : 4'd8 ; // last branch is chosen when no channel is valid. + 4'd8: chnl_idx = hit_priority[0] ? 4'd0 : + hit_priority[1] ? 4'd1 : + hit_priority[2] ? 4'd2 : + hit_priority[3] ? 4'd3 : + hit_priority[4] ? 4'd4 : + hit_priority[5] ? 4'd5 : + hit_priority[6] ? 4'd6 : + hit_priority[7] ? 4'd7 : + hit_priority[8] ? 4'd8 : 4'd0 ; // last branch is chosen when no channel is valid. + default: chnl_idx = {CHNL_NUM_LOG{1'd0}}; + endcase + end + else begin + chnl_idx = chnl_idx_reg; // chosen in REQ_TRANS state + end +end + +end // CHANNEL_NUM == 9 +else if (CHANNEL_NUM == 8) begin:CHNL_SEL_8 + +always @(*) begin + if (is_schedule) begin + case (last_chnl) + 3'd0: chnl_idx = hit_priority[0] ? 3'd1 : + hit_priority[1] ? 3'd2 : + hit_priority[2] ? 3'd3 : + hit_priority[3] ? 3'd4 : + hit_priority[4] ? 3'd5 : + hit_priority[5] ? 3'd6 : + hit_priority[6] ? 3'd7 : + hit_priority[7] ? 3'd0 : 3'd1 ; // last branch is chosen when no channel is valid. + 3'd1: chnl_idx = hit_priority[0] ? 3'd2 : + hit_priority[1] ? 3'd3 : + hit_priority[2] ? 3'd4 : + hit_priority[3] ? 3'd5 : + hit_priority[4] ? 3'd6 : + hit_priority[5] ? 3'd7 : + hit_priority[6] ? 3'd0 : + hit_priority[7] ? 3'd1 : 3'd2 ; // last branch is chosen when no channel is valid. + 3'd2: chnl_idx = hit_priority[0] ? 3'd3 : + hit_priority[1] ? 3'd4 : + hit_priority[2] ? 3'd5 : + hit_priority[3] ? 3'd6 : + hit_priority[4] ? 3'd7 : + hit_priority[5] ? 3'd0 : + hit_priority[6] ? 3'd1 : + hit_priority[7] ? 3'd2 : 3'd3 ; // last branch is chosen when no channel is valid. + 3'd3: chnl_idx = hit_priority[0] ? 3'd4 : + hit_priority[1] ? 3'd5 : + hit_priority[2] ? 3'd6 : + hit_priority[3] ? 3'd7 : + hit_priority[4] ? 3'd0 : + hit_priority[5] ? 3'd1 : + hit_priority[6] ? 3'd2 : + hit_priority[7] ? 3'd3 : 3'd4 ; // last branch is chosen when no channel is valid. + 3'd4: chnl_idx = hit_priority[0] ? 3'd5 : + hit_priority[1] ? 3'd6 : + hit_priority[2] ? 3'd7 : + hit_priority[3] ? 3'd0 : + hit_priority[4] ? 3'd1 : + hit_priority[5] ? 3'd2 : + hit_priority[6] ? 3'd3 : + hit_priority[7] ? 3'd4 : 3'd5 ; // last branch is chosen when no channel is valid. + 3'd5: chnl_idx = hit_priority[0] ? 3'd6 : + hit_priority[1] ? 3'd7 : + hit_priority[2] ? 3'd0 : + hit_priority[3] ? 3'd1 : + hit_priority[4] ? 3'd2 : + hit_priority[5] ? 3'd3 : + hit_priority[6] ? 3'd4 : + hit_priority[7] ? 3'd5 : 3'd6 ; // last branch is chosen when no channel is valid. + 3'd6: chnl_idx = hit_priority[0] ? 3'd7 : + hit_priority[1] ? 3'd0 : + hit_priority[2] ? 3'd1 : + hit_priority[3] ? 3'd2 : + hit_priority[4] ? 3'd3 : + hit_priority[5] ? 3'd4 : + hit_priority[6] ? 3'd5 : + hit_priority[7] ? 3'd6 : 3'd7 ; // last branch is chosen when no channel is valid. + 3'd7: chnl_idx = hit_priority[0] ? 3'd0 : + hit_priority[1] ? 3'd1 : + hit_priority[2] ? 3'd2 : + hit_priority[3] ? 3'd3 : + hit_priority[4] ? 3'd4 : + hit_priority[5] ? 3'd5 : + hit_priority[6] ? 3'd6 : + hit_priority[7] ? 3'd7 : 3'd0 ; // last branch is chosen when no channel is valid. + default: chnl_idx = {CHNL_NUM_LOG{1'd0}}; + endcase + end + else begin + chnl_idx = chnl_idx_reg; // chosen in REQ_TRANS state + end +end + +end // CHANNEL_NUM == 8 +else if (CHANNEL_NUM == 7) begin:CHNL_SEL_7 + +always @(*) begin + if (is_schedule) begin + case (last_chnl) + 0: chnl_idx = hit_priority[0] ? 1 : + hit_priority[1] ? 2 : + hit_priority[2] ? 3 : + hit_priority[3] ? 4 : + hit_priority[4] ? 5 : + hit_priority[5] ? 6 : + hit_priority[6] ? 0 : 1 ; // last branch is chosen when no channel is valid. + 1: chnl_idx = hit_priority[0] ? 2 : + hit_priority[1] ? 3 : + hit_priority[2] ? 4 : + hit_priority[3] ? 5 : + hit_priority[4] ? 6 : + hit_priority[5] ? 0 : + hit_priority[6] ? 1 : 2 ; // last branch is chosen when no channel is valid. + 2: chnl_idx = hit_priority[0] ? 3 : + hit_priority[1] ? 4 : + hit_priority[2] ? 5 : + hit_priority[3] ? 6 : + hit_priority[4] ? 0 : + hit_priority[5] ? 1 : + hit_priority[6] ? 2 : 3 ; // last branch is chosen when no channel is valid. + 3: chnl_idx = hit_priority[0] ? 4 : + hit_priority[1] ? 5 : + hit_priority[2] ? 6 : + hit_priority[3] ? 0 : + hit_priority[4] ? 1 : + hit_priority[5] ? 2 : + hit_priority[6] ? 3 : 4 ; // last branch is chosen when no channel is valid. + 4: chnl_idx = hit_priority[0] ? 5 : + hit_priority[1] ? 6 : + hit_priority[2] ? 0 : + hit_priority[3] ? 1 : + hit_priority[4] ? 2 : + hit_priority[5] ? 3 : + hit_priority[6] ? 4 : 5 ; // last branch is chosen when no channel is valid. + 5: chnl_idx = hit_priority[0] ? 6 : + hit_priority[1] ? 0 : + hit_priority[2] ? 1 : + hit_priority[3] ? 2 : + hit_priority[4] ? 3 : + hit_priority[5] ? 4 : + hit_priority[6] ? 5 : 6 ; // last branch is chosen when no channel is valid. + 6: chnl_idx = hit_priority[0] ? 0 : + hit_priority[1] ? 1 : + hit_priority[2] ? 2 : + hit_priority[3] ? 3 : + hit_priority[4] ? 4 : + hit_priority[5] ? 5 : + hit_priority[6] ? 6 : 0 ; // last branch is chosen when no channel is valid. + default: chnl_idx = {CHNL_NUM_LOG{1'd0}}; + endcase + end + else begin + chnl_idx = chnl_idx_reg; // chosen in REQ_TRANS state + end +end + +end // CHANNEL_NUM == 7 +else if (CHANNEL_NUM == 6) begin:CHNL_SEL_6 + +always @(*) begin + if (is_schedule) begin + case (last_chnl) + 0: chnl_idx = hit_priority[0] ? 1 : + hit_priority[1] ? 2 : + hit_priority[2] ? 3 : + hit_priority[3] ? 4 : + hit_priority[4] ? 5 : + hit_priority[5] ? 0 : 1 ; // last branch is chosen when no channel is valid. + 1: chnl_idx = hit_priority[0] ? 2 : + hit_priority[1] ? 3 : + hit_priority[2] ? 4 : + hit_priority[3] ? 5 : + hit_priority[4] ? 0 : + hit_priority[5] ? 1 : 2 ; // last branch is chosen when no channel is valid. + 2: chnl_idx = hit_priority[0] ? 3 : + hit_priority[1] ? 4 : + hit_priority[2] ? 5 : + hit_priority[3] ? 0 : + hit_priority[4] ? 1 : + hit_priority[5] ? 2 : 3 ; // last branch is chosen when no channel is valid. + 3: chnl_idx = hit_priority[0] ? 4 : + hit_priority[1] ? 5 : + hit_priority[2] ? 0 : + hit_priority[3] ? 1 : + hit_priority[4] ? 2 : + hit_priority[5] ? 3 : 4 ; // last branch is chosen when no channel is valid. + 4: chnl_idx = hit_priority[0] ? 5 : + hit_priority[1] ? 0 : + hit_priority[2] ? 1 : + hit_priority[3] ? 2 : + hit_priority[4] ? 3 : + hit_priority[5] ? 4 : 5 ; // last branch is chosen when no channel is valid. + 5: chnl_idx = hit_priority[0] ? 0 : + hit_priority[1] ? 1 : + hit_priority[2] ? 2 : + hit_priority[3] ? 3 : + hit_priority[4] ? 4 : + hit_priority[5] ? 5 : 0 ; // last branch is chosen when no channel is valid. + default: chnl_idx = {CHNL_NUM_LOG{1'd0}}; + endcase + end + else begin + chnl_idx = chnl_idx_reg; // chosen in REQ_TRANS state + end +end + +end // CHANNEL_NUM == 6 +else if (CHANNEL_NUM == 5) begin:CHNL_SEL_5 + +always @(*) begin + if (is_schedule) begin + case (last_chnl) + 0: chnl_idx = hit_priority[0] ? 1 : + hit_priority[1] ? 2 : + hit_priority[2] ? 3 : + hit_priority[3] ? 4 : + hit_priority[4] ? 0 : 1 ; // last branch is chosen when no channel is valid. + 1: chnl_idx = hit_priority[0] ? 2 : + hit_priority[1] ? 3 : + hit_priority[2] ? 4 : + hit_priority[3] ? 0 : + hit_priority[4] ? 1 : 2 ; // last branch is chosen when no channel is valid. + 2: chnl_idx = hit_priority[0] ? 3 : + hit_priority[1] ? 4 : + hit_priority[2] ? 0 : + hit_priority[3] ? 1 : + hit_priority[4] ? 2 : 3 ; // last branch is chosen when no channel is valid. + 3: chnl_idx = hit_priority[0] ? 4 : + hit_priority[1] ? 0 : + hit_priority[2] ? 1 : + hit_priority[3] ? 2 : + hit_priority[4] ? 3 : 4 ; // last branch is chosen when no channel is valid. + 4: chnl_idx = hit_priority[0] ? 0 : + hit_priority[1] ? 1 : + hit_priority[2] ? 2 : + hit_priority[3] ? 3 : + hit_priority[4] ? 4 : 0 ; // last branch is chosen when no channel is valid. + default: chnl_idx = {CHNL_NUM_LOG{1'd0}}; + endcase + end + else begin + chnl_idx = chnl_idx_reg; // chosen in REQ_TRANS state + end +end + +end // CHANNEL_NUM == 5 +else if (CHANNEL_NUM == 4) begin:CHNL_SEL_4 + +always @(*) begin + if (is_schedule) begin + case (last_chnl) + 0: chnl_idx = hit_priority[0] ? 1 : + hit_priority[1] ? 2 : + hit_priority[2] ? 3 : + hit_priority[3] ? 0 : 1 ; // last branch is chosen when no channel is valid. + 1: chnl_idx = hit_priority[0] ? 2 : + hit_priority[1] ? 3 : + hit_priority[2] ? 0 : + hit_priority[3] ? 1 : 2 ; // last branch is chosen when no channel is valid. + 2: chnl_idx = hit_priority[0] ? 3 : + hit_priority[1] ? 0 : + hit_priority[2] ? 1 : + hit_priority[3] ? 2 : 3 ; // last branch is chosen when no channel is valid. + 3: chnl_idx = hit_priority[0] ? 0 : + hit_priority[1] ? 1 : + hit_priority[2] ? 2 : + hit_priority[3] ? 3 : 0 ; // last branch is chosen when no channel is valid. + default: chnl_idx = {CHNL_NUM_LOG{1'd0}}; + endcase + end + else begin + chnl_idx = chnl_idx_reg; // chosen in REQ_TRANS state + end +end + +end // CHANNEL_NUM == 4 +else if (CHANNEL_NUM == 3) begin:CHNL_SEL_3 + +always @(*) begin + if (is_schedule) begin + case (last_chnl) + 0: chnl_idx = hit_priority[0] ? 1 : + hit_priority[1] ? 2 : + hit_priority[2] ? 0 : 1; // last branch is chosen when no channel is valid. + 1: chnl_idx = hit_priority[0] ? 2 : + hit_priority[1] ? 0 : + hit_priority[2] ? 1 : 2; // last branch is chosen when no channel is valid. + 2: chnl_idx = hit_priority[0] ? 0 : + hit_priority[1] ? 1 : + hit_priority[2] ? 2 : 0; // last branch is chosen when no channel is valid. + default: chnl_idx = {CHNL_NUM_LOG{1'd0}}; + endcase + end + else begin + chnl_idx = chnl_idx_reg; // chosen in REQ_TRANS state + end +end + +end // CHANNEL_NUM == 3 +else if (CHANNEL_NUM == 2) begin:CHNL_SEL_2 + +always @(*) begin + if (is_schedule) begin + case (last_chnl) + 1'd0: chnl_idx = hit_priority[0] ? 1'd1 : + hit_priority[1] ? 1'd0 : 1'd1 ; // last branch is chosen when no channel is valid. + 1'd1: chnl_idx = hit_priority[0] ? 1'd0 : + hit_priority[1] ? 1'd1 : 1'd0 ; // last branch is chosen when no channel is valid. + default: chnl_idx = {CHNL_NUM_LOG{1'd0}}; + endcase + end + else begin + chnl_idx = chnl_idx_reg; // chosen in REQ_TRANS state + end +end + +end // CHANNEL_NUM == 2 +endgenerate +/* + This is used for different Channel Numbers, the default Number is 4 */ +/* -------Generate block{end}------- */ + +// /* -------Core logic to arbit, a parameterized arbiter{begin}------- */ +// function [CHNL_NUM_LOG-1:0] find_chnl_num; +// input [CHNL_NUM_LOG-1:0] prio_level; +// input [CHNL_NUM_LOG-1:0] last_c; +// begin +// find_chnl_num = ((last_c+prio_level+1) >= CHANNEL_NUM) ? last_c+prio_level+1-CHANNEL_NUM : last_c+prio_level+1; +// end +// endfunction + +// function [CHANNEL_NUM-1:0] sel_prio; +// input [CHANNEL_NUM-1:0] sel; +// reg tmp; +// integer i, j; +// begin +// sel_prio[0] = sel[0]; +// for (i = 1; i < CHANNEL_NUM; i = i + 1) begin +// tmp = 0; +// for (j = 0; j < i; j = j + 1) begin +// tmp = tmp | sel[j]; +// end +// sel_prio[i] = !tmp & sel[i]; +// end +// end +// endfunction + +// function [CHNL_NUM_LOG-1:0] find_nxt_chnl; +// input [CHNL_NUM_LOG-1:0] last_c; +// input [CHANNEL_NUM-1:0] hit_prio; +// integer i; +// begin +// find_nxt_chnl = {CHNL_NUM_LOG{hit_prio[0]}} & find_chnl_num(0, last_c); +// for (i = 1; i < CHANNEL_NUM; i = i + 1) begin +// find_nxt_chnl = find_nxt_chnl | {CHNL_NUM_LOG{hit_prio[i]}} & find_chnl_num(i, last_c);; +// end +// end +// endfunction + +// always @(*) begin +// if (is_schedule) begin +// chnl_idx = find_nxt_chnl(last_chnl, sel_prio(hit_priority)); +// end +// else begin +// chnl_idx = chnl_idx_reg; // chosen in REQ_TRANS state +// end +// end +// /* -------Core logic to arbit, a parameterized arbiter{end}------- */ + +// state transform signal +assign req_last = m_axis_req_tvalid & m_axis_req_tready & m_axis_req_tlast; + +/* -------Find next channel{end}------- */ + +/* -------{Read Request Arbiter FSM}begin------- */ +/******************** Stage 1: State Register **********************/ +assign is_idle = (cur_state == IDLE ); +assign is_schedule = (cur_state == SCHEDULE ); +assign is_req_trans = (cur_state == REQ_TRANS); +assign j_req_trans = is_schedule & (!req_last) & (|s_axis_req_tvalid); +// assign j_schedule = is_schedule & (req_last) | +// is_req_trans & (req_last); + +always @(posedge dma_clk, negedge rst_n) begin + if(~rst_n) + cur_state <= `TD IDLE; + else + cur_state <= `TD nxt_state; +end + +/******************** Stage 2: State Transition **********************/ + +always @(*) begin + case(cur_state) + IDLE: begin + if (|s_axis_req_tvalid) begin + nxt_state = SCHEDULE; + end + else begin + nxt_state = IDLE; + end + end + SCHEDULE: begin + if (req_last) begin // one beat request has already been transmited in + // schedule state. + nxt_state = SCHEDULE; + end + else if (|s_axis_req_tvalid) begin // There's valid channel, and not the last beat. + nxt_state = REQ_TRANS; + end + else begin + nxt_state = IDLE; + end + end + REQ_TRANS: begin + if (req_last) begin // request has already been transmited in + // req_trans state. + nxt_state = SCHEDULE; + end + else begin + nxt_state = REQ_TRANS; + end + end + default: begin + nxt_state = IDLE; + end + endcase +end +/******************** Stage 3: Output **********************/ + +/* -------Generate block{begin}------- */ +genvar n; +generate +for (n = 0; n < CHANNEL_NUM; n = n + 1) begin:CHNL_ASSIGN + +assign s_axis_req_tready[n] = (is_schedule | is_req_trans) & (n == chnl_idx) & m_axis_req_tready; + +assign s_channel_tvalid[n] = s_axis_req_tvalid[((n+1) * 1 -1):(n * 1 )]; +assign s_channel_tlast [n] = s_axis_req_tlast [((n+1) * 1 -1):(n * 1 )]; +assign s_channel_tdata [n] = s_axis_req_tdata [((n+1) * `DMA_DATA_W -1):(n * `DMA_DATA_W )]; +assign s_channel_tuser [n] = s_axis_req_tuser [((n+1) * `AXIS_TUSER_W-1):(n * `AXIS_TUSER_W)]; +assign s_channel_tkeep [n] = s_axis_req_tkeep [((n+1) * `DMA_KEEP_W -1):(n * `DMA_KEEP_W )]; + +assign hit_priority[n] = s_channel_tvalid[nxt_priority[n]]; + +end +endgenerate +/* -------Generate block{end}------- */ + +assign m_axis_req_tvalid = (is_schedule | is_req_trans) ? s_channel_tvalid[chnl_idx] : 1'd0; +assign m_axis_req_tlast = (is_schedule | is_req_trans) ? s_channel_tlast [chnl_idx] : 1'd0; +assign m_axis_req_tdata = (is_schedule | is_req_trans) ? s_channel_tdata [chnl_idx] : {`DMA_DATA_W{1'd0}}; +assign m_axis_req_tuser = (is_schedule | is_req_trans) ? s_channel_tuser [chnl_idx] : {`AXIS_TUSER_W{1'd0}}; +assign m_axis_req_tkeep = (is_schedule | is_req_trans) ? s_channel_tkeep [chnl_idx] : {`DMA_KEEP_W{1'd0}}; + +/* -------{Read Request Arbiter FSM}end------- */ + + +endmodule diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/DMA/req_converter.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/DMA/req_converter.v new file mode 100644 index 0000000000000000000000000000000000000000..547ac8157589c1467be0961033006c85e874b3d4 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/DMA/req_converter.v @@ -0,0 +1,290 @@ +`timescale 1ns / 100ps +//************************************************************************* +// > File Name: req_converter.v +// > Author : Kangning +// > Date : 2020-08-25 +// > Note : req_converter used to convert AXI-Stream into +// > Xilinx PCIe compatible interface. +//************************************************************************* + +//`include "../lib/global_include_h.v" + +module req_converter #( + +) ( + input wire pcie_clk , + input wire pcie_rst_n, + input wire dma_clk , + input wire rst_n , + + + /* ------- Interface with Request Arbiter{begin} ------- */ + /* AXI-Stream request tuser, only valid in first beat of a packet + * | Reserved | REQ_TYPE | Tag | address | Reserved | DW length | first BE | last BE | + * | 127:108 | 107:104 | 103:96 | 95:32 | 31:19 | 18:8 | 7:4 | 3:0 | + * or + * AXI-Stream interrupt request tuser, only valid in first beat of a packet + * | Reserved | REQ_TYPE | Resv | address | Reserved | + * | 127:108 | 107:104 | 103:96 | 95:32 | 31:0 | + */ + input wire axis_req_tvalid, // i, 1 + input wire axis_req_tlast , // i, 1 + input wire [`DMA_DATA_W -1:0] axis_req_tdata , // i, `DMA_DATA_W + input wire [`AXIS_TUSER_W-1:0] axis_req_tuser , // i, `AXIS_TUSER_W + input wire [`DMA_KEEP_W -1:0] axis_req_tkeep , // i, `DMA_KEEP_W + output wire axis_req_tready, // o, 1 + /* ------- Interface with Request Arbiter{end} ------- */ + + + /* -------dma --> pcie interface{begin}------- */ + // Requester request + /* RQ tuser + * | 59:28 | 27:24 | 23:16 | 15 | 14:13 | 12 | 11 | 10:8 | 7:4 | 3:0 | + * | parity | seq_num | tph_st_tag | tph_indirect_tag_en | tph_type | tph_present | discontinue | addr_offset | last_be | first_be | + * | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | | + */ + output wire s_axis_rq_tvalid, // o, 1 + output wire s_axis_rq_tlast , // o, 1 + output wire [`DMA_DATA_W-1:0] s_axis_rq_tdata , // o, `DMA_DATA_W + output wire [59 :0] s_axis_rq_tuser , // o, 60 + output wire [`DMA_KEEP_W-1:0] s_axis_rq_tkeep , // o, `DMA_KEEP_W + input wire s_axis_rq_tready, // i, 1 + /* -------dma --> pcie interface{end}------- */ + + input wire [15:0] req_id_in, // i, 16 + + /* -------Interrupt Interface Signals{begin}------- */ + input [1:0] cfg_interrupt_msix_enable , + input [1:0] cfg_interrupt_msix_mask , + output [31:0] cfg_interrupt_msix_data , + output [63:0] cfg_interrupt_msix_address , + output cfg_interrupt_msix_int , + input cfg_interrupt_msix_sent , + input cfg_interrupt_msix_fail , + output wire [2:0] cfg_interrupt_msi_function_number + /* -------Interrupt Interface Signals{end}------- */ + +`ifdef PCIEI_APB_DBG + /* -------APB reated signal{begin}------- */ + ,input wire [`SRAM_RW_DATA_W-1:0] rw_data // i, `SRAM_RW_DATA_W + ,input wire [31:0] dbg_sel // debug bus select + ,output wire [31:0] dbg_bus // debug bus data + /* -------APB reated signal{end}------- */ +`endif +); + +/*-------Interrupt related logic{begin}------- */ +wire int_req_valid; +wire [31:0] int_req_data ; +wire [63:0] int_req_addr ; +wire int_req_ready; +/*-------Interrupt related logic{end}------- */ + +/* -------related to input regs{begin}------- */ +wire input_tready; + +wire in_reg_tvalid; +wire in_reg_tlast ; +wire [`DMA_DATA_W -1:0] in_reg_tdata ; +wire [`AXIS_TUSER_W-1:0] in_reg_tuser ; +wire [`DMA_KEEP_W -1:0] in_reg_tkeep ; +wire in_reg_tready; +/* -------related to input regs{end}------- */ + +/* -------RQ head{begin}------- */ +wire [2 :0] attr; +wire [2 :0] tc; +wire [15:0] cpl_id; +wire [7 :0] tag; +reg [15:0] req_id; +wire [10:0] dw_cnt; +wire [3 :0] req_type; +wire [127:0] rq_head; +/* -------RQ head{end}------- */ + +/* -------data realignment{begin}------- */ +reg [127:0] tmp_reg_data; +reg [3 :0] tmp_reg_keep; + +reg head_beat; // first beat of an s_axis_rq_* packet +reg tmp_beat; // data in tmp_reg as the last beat of s_axis_rq_* interface for output + +wire st_tmp; // store tmp_reg in the last beat of axis_req_* interface +/* -------data realignment{end}------- */ + +`ifdef PCIEI_APB_DBG +/* -------APB reated signal{begin}------- */ +wire [`REQ_CONVERT_TOP_SIGNAL_W-1:0] req_convert_top_dbg_signal; +wire [`INT_PROC_SIGNAL_W-1:0] int_proc_dbg_signal; +/* -------APB reated signal{end}------- */ +`endif + +//--------------------------------------------------------------------------------------------------------------------------- + +`ifdef PCIEI_APB_DBG +/* -------APB reated signal{begin}------- */ +assign dbg_bus = {req_convert_top_dbg_signal, int_proc_dbg_signal} >> {dbg_sel, 5'd0}; // 924 + +assign req_convert_top_dbg_signal = { // 818 + int_req_valid, int_req_data, int_req_addr, int_req_ready, // 98 + input_tready, // 1 + in_reg_tvalid, in_reg_tlast, in_reg_tdata, in_reg_tuser, in_reg_tkeep, in_reg_tready, // 395 + attr, tc, cpl_id, tag, req_id, dw_cnt, req_type, rq_head, // 189 + tmp_reg_data, tmp_reg_keep, // 132 + head_beat, tmp_beat, // 2 + st_tmp // 1 +}; +/* -------APB reated signal{end}------- */ +`endif + +/*-------Interrupt related logic{begin}------- */ +assign int_req_valid = axis_req_tuser[107:104] == `DMA_INT_REQ; +assign int_req_data = axis_req_tdata[31:0]; +assign int_req_addr = axis_req_tuser[95:32]; + +int_proc int_proc ( + .pcie_clk ( pcie_clk ), // i, 1 + .pcie_rst_n ( pcie_rst_n ), // i, 1 + .dma_clk ( dma_clk ), // i, 1 + .rst_n ( rst_n ), // i, 1 + + .int_req_valid ( int_req_valid ), // i,, 1 + .int_req_data ( int_req_data ), // i,, 32 + .int_req_addr ( int_req_addr ), // i,, 64 + .int_req_ready ( int_req_ready ), // o,, 1 + + /* -------Interrupt Interface Signals{begin}------- */ + .cfg_interrupt_msix_enable ( cfg_interrupt_msix_enable ), // i, 2 + .cfg_interrupt_msix_mask ( cfg_interrupt_msix_mask ), // i, 2 + .cfg_interrupt_msix_data ( cfg_interrupt_msix_data ), // o, 32 + .cfg_interrupt_msix_address ( cfg_interrupt_msix_address ), // o, 64 + .cfg_interrupt_msix_int ( cfg_interrupt_msix_int ), // o, 1 + .cfg_interrupt_msix_sent ( cfg_interrupt_msix_sent ), // i, 1 + .cfg_interrupt_msix_fail ( cfg_interrupt_msix_fail ), // i, 1 + .cfg_interrupt_msi_function_number ( cfg_interrupt_msi_function_number ) // o, 3 + /* -------Interrupt Interface Signals{end}------- */ + +`ifdef PCIEI_APB_DBG + /* -------APB reated signal{begin}------- */ + ,.rw_data ( rw_data ) // i, `SRAM_RW_DATA_W + ,.dbg_signal ( int_proc_dbg_signal ) // o, `INT_PROC_SIGNAL_W + /* -------APB reated signal{end}------- */ +`endif +); +/*-------Interrupt related logic{end}------- */ + +/* -------related to in_reg{begin}------- */ +assign axis_req_tready = int_req_valid ? int_req_ready : input_tready; +st_reg #( + .TUSER_WIDTH ( `AXIS_TUSER_W ), + .TDATA_WIDTH ( `DMA_KEEP_W + `DMA_DATA_W ) +) in_reg ( + .clk ( dma_clk ), // i, 1 + .rst_n ( rst_n ), // i, 1 + + /* -------input axis-like interface{begin}------- */ + .axis_tvalid ( axis_req_tvalid & (~int_req_valid)), // i, 1 + .axis_tlast ( axis_req_tlast ), // i, 1 + .axis_tuser ( axis_req_tuser ), // i, TUSER_WIDTH + .axis_tdata ( {axis_req_tkeep, axis_req_tdata} ), // i, TDATA_WIDTH + .axis_tready ( input_tready ), // o, 1 + /* -------input axis-like interface{end}------- */ + + /* -------output in_reg inteface{begin}------- */ + .axis_reg_tvalid ( in_reg_tvalid ), // o, 1 + .axis_reg_tlast ( in_reg_tlast ), // o, 1 + .axis_reg_tuser ( in_reg_tuser ), // o, TUSER_WIDTH + .axis_reg_tdata ( {in_reg_tkeep, in_reg_tdata} ), // o, TDATA_WIDTH + .axis_reg_tready ( in_reg_tready ) // i, 1 + /* -------output in_reg inteface{end}------- */ +); +/* -------related to in_reg{end}------- */ + +/* -------RQ head{begin}------- */ +always @(posedge dma_clk, negedge rst_n) begin + if (~rst_n) begin + req_id <= `TD 0; + end + else begin + req_id <= req_id_in; + end +end + +assign attr = 3'd0; +assign tc = 3'd0; +assign cpl_id = 16'd0; +assign tag = in_reg_tuser[103:96]; +// assign req_id = 16'd0; +assign dw_cnt = in_reg_tuser[18:8]; +assign req_type = in_reg_tuser[107:104]; +assign rq_head = {1'd0, attr, tc, 1'd0, cpl_id, tag, req_id, 1'd0, req_type, dw_cnt, + in_reg_tuser[95:34], 2'd0}; +/* -------RQ head{end}------- */ + + +/* -------data realignment{begin}------- */ +always @(posedge dma_clk, negedge rst_n) begin + if (~rst_n) begin + tmp_reg_data <= `TD 128'd0; + tmp_reg_keep <= `TD 4'd0; + end + else if (in_reg_tvalid & in_reg_tready) begin + tmp_reg_data <= `TD in_reg_tdata[255:128]; + tmp_reg_keep <= `TD in_reg_tkeep[7:4]; + end +end + +always @(posedge dma_clk, negedge rst_n) begin + if (~rst_n) begin + head_beat <= `TD 1; + end + else if (s_axis_rq_tvalid & s_axis_rq_tready & s_axis_rq_tlast) begin + head_beat <= `TD 1; + end + else if (s_axis_rq_tvalid & s_axis_rq_tready) begin + head_beat <= `TD 0; + end +end + +always @(posedge dma_clk, negedge rst_n) begin + if (~rst_n) begin + tmp_beat <= `TD 0; + end + else if (in_reg_tvalid & in_reg_tready & in_reg_tlast & st_tmp) begin + tmp_beat <= `TD 1; + end + else if (tmp_beat & s_axis_rq_tready) begin + tmp_beat <= `TD 0; + end +end + +assign st_tmp = |in_reg_tkeep[7:4]; +/* -------data realignment{end}------- */ + + +/* -------output {begin}------- */ +assign in_reg_tready = s_axis_rq_tready & !tmp_beat; + + +assign s_axis_rq_tvalid = in_reg_tvalid | tmp_beat; +assign s_axis_rq_tlast = (in_reg_tlast & !st_tmp) | + tmp_beat; + + +assign s_axis_rq_tdata = head_beat&in_reg_tvalid ? {in_reg_tdata[127:0], rq_head} : + tmp_beat ? {128'd0, tmp_reg_data} : + in_reg_tvalid ? {in_reg_tdata[127:0], tmp_reg_data} : + 256'd0; +assign s_axis_rq_tkeep = head_beat&in_reg_tvalid ? {in_reg_tkeep[3:0], 4'hf} : + tmp_beat ? {4'd0, tmp_reg_keep} : + in_reg_tvalid ? {in_reg_tkeep[3:0], tmp_reg_keep} : + 8'd0; + + +assign s_axis_rq_tuser = head_beat ? {32'd0, 4'd0, 8'd0, 1'd0, 2'd0, 1'd0, 1'd0, 3'd0, + in_reg_tuser[3:0], in_reg_tuser[7:4]} : 0; +/* -------output {end}------- */ + +/* -------{Read Request Arbiter FSM}end------- */ + +endmodule diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/DMA/rq_async_fifos.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/DMA/rq_async_fifos.v new file mode 100644 index 0000000000000000000000000000000000000000..ba977eb93df6cab3bf10348803ab06bac8a292a6 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/DMA/rq_async_fifos.v @@ -0,0 +1,221 @@ +`timescale 1ns / 100ps +//************************************************************************* +// > File Name: rq_async_fifos.v +// > Author : Kangning +// > Date : 2021-08-16 +// > Note : rq_async_fifos, used to separate rdma and pcie clock domain, +// > in RQ (Requester request channel). +//************************************************************************* + +//`include "../lib/global_include_h.v" + +module rq_async_fifos #( + +) ( + input wire dma_clk , + input wire pcie_clk , + input wire dma_rst_n , + input wire pcie_rst_n, + + + /* -------dma --> pcie interface, dma part{begin}------- */ + // Requester request + /* RQ tuser + * | 59:28 | 27:24 | 23:16 | 15 | 14:13 | 12 | 11 | 10:8 | 7:4 | 3:0 | + * | parity | seq_num | tph_st_tag | tph_indirect_tag_en | tph_type | tph_present | discontinue | addr_offset | last_be | first_be | + * | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | | + */ + input wire dma_axis_rq_tvalid, // o, 1 + input wire dma_axis_rq_tlast , // o, 1 + input wire [`DMA_DATA_W-1:0] dma_axis_rq_tdata , // o, `DMA_DATA_W + input wire [59 :0] dma_axis_rq_tuser , // o, 60 + input wire [`DMA_KEEP_W-1:0] dma_axis_rq_tkeep , // o, `DMA_KEEP_W + output wire dma_axis_rq_tready, // i, 1 + /* -------dma --> pcie interface, dma part{end}------- */ + + /* -------dma --> pcie interface, pcie part{begin}------- */ + // Requester request + /* RQ tuser + * | 59:28 | 27:24 | 23:16 | 15 | 14:13 | 12 | 11 | 10:8 | 7:4 | 3:0 | + * | parity | seq_num | tph_st_tag | tph_indirect_tag_en | tph_type | tph_present | discontinue | addr_offset | last_be | first_be | + * | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | | + */ + output wire st_pcie_axis_rq_tvalid, // o, 1 + output wire st_pcie_axis_rq_tlast , // o, 1 + output wire [`DMA_DATA_W-1:0] st_pcie_axis_rq_tdata , // o, `DMA_DATA_W + output wire [59 :0] st_pcie_axis_rq_tuser , // o, 60 + output wire [`DMA_KEEP_W-1:0] st_pcie_axis_rq_tkeep , // o, `DMA_KEEP_W + input wire st_pcie_axis_rq_tready // i, 1 + /* -------dma --> pcie interface, pcie part{begin}------- */ + +`ifdef PCIEI_APB_DBG + /* -------APB reated signal{begin}------- */ + ,input wire [`SRAM_RW_DATA_W -1:0] rw_data // i, `SRAM_RW_DATA_W + ,output wire [`RQ_ASYNC_SIGNAL_W-1:0] dbg_signal // o, `RQ_ASYNC_SIGNAL_W + /* -------APB reated signal{end}------- */ +`endif +); +wire dma_axis_rq_full; + +/* -------tmp store the whole rq pkt{begin}------- */ +wire fifo_out_ren ; +wire [1 + `DMA_KEEP_W + 8 + `DMA_DATA_W-1:0] fifo_out_tdata; +wire fifo_out_empty; + +wire pkt_store_wen ; +wire pkt_store_full ; +wire pkt_store_ren ; +wire [1 + `DMA_KEEP_W + 8 + `DMA_DATA_W-1:0] pkt_store_tdata; +wire pkt_store_empty; + +reg [4:0] pkt_cnt; // +/* -------tmp store the whole rq pkt{begin}------- */ + +/* -------dma --> pcie interface, pcie part{begin}------- */ +// Requester request +/* RQ tuser + * | 59:28 | 27:24 | 23:16 | 15 | 14:13 | 12 | 11 | 10:8 | 7:4 | 3:0 | + * | parity | seq_num | tph_st_tag | tph_indirect_tag_en | tph_type | tph_present | discontinue | addr_offset | last_be | first_be | + * | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | | + */ +wire pcie_axis_rq_tvalid; +wire pcie_axis_rq_tlast ; +wire [`DMA_DATA_W-1:0] pcie_axis_rq_tdata ; +wire [59 :0] pcie_axis_rq_tuser ; +wire [`DMA_KEEP_W-1:0] pcie_axis_rq_tkeep ; +wire pcie_axis_rq_tready; +/* -------dma --> pcie interface, pcie part{begin}------- */ + +`ifdef PCIEI_APB_DBG +/* -------APB reated signal{begin}------- */ +wire [1:0] rtsel; +wire [1:0] wtsel; +wire [1:0] ptsel; +wire vg ; +wire vs ; +/* -------APB reated signal{end}------- */ +`endif + +//--------------------------------------------------------------------------------------------------------------------------- + +`ifdef PCIEI_APB_DBG +/* -------APB reated signal{begin}------- */ +assign {rtsel, wtsel, ptsel, vg, vs} = rw_data; + +assign dbg_signal = { // 885 + dma_axis_rq_full, // 1 + fifo_out_ren, fifo_out_tdata, fifo_out_empty, // 275 + pkt_store_wen, pkt_store_full, pkt_store_ren, pkt_store_tdata, pkt_store_empty, // 277 + pkt_cnt, // 5 + pcie_axis_rq_tvalid, pcie_axis_rq_tlast , pcie_axis_rq_tdata , pcie_axis_rq_tuser , pcie_axis_rq_tkeep , pcie_axis_rq_tready // 327 +}; +/* -------APB reated signal{end}------- */ +`endif + +pcieifc_async_fifo #( + .DATA_WIDTH ( 1 + `DMA_KEEP_W + 8 + `DMA_DATA_W ), + .ADDR_WIDTH ( 4 ) +) pcieifc_async_fifo ( + .wr_clk ( dma_clk ), // i, 1 + .rd_clk ( pcie_clk ), // i, 1 + .wrst_n ( dma_rst_n ), // i, 1 + .rrst_n ( pcie_rst_n ), // i, 1 + + .wen ( dma_axis_rq_tvalid & dma_axis_rq_tready ), // i, 1 + .din ( {dma_axis_rq_tlast, dma_axis_rq_tkeep, dma_axis_rq_tuser[7:0], dma_axis_rq_tdata} ), // i, (`DMA_KEEP_W + 8 + 1 + `DMA_DATA_W) + .full ( dma_axis_rq_full ), // o, 1 + + .ren ( fifo_out_ren ), // i, 1 + .dout ( fifo_out_tdata ), // o, (1 + `DMA_KEEP_W + 8 + `DMA_DATA_W) + .empty ( fifo_out_empty ) // o, 1 + +`ifdef PCIEI_APB_DBG + ,.rtsel ( rtsel ) // i, 2 + ,.wtsel ( wtsel ) // i, 2 + ,.ptsel ( ptsel ) // i, 2 + ,.vg ( vg ) // i, 1 + ,.vs ( vs ) // i, 1 +`endif +); +assign dma_axis_rq_tready = !dma_axis_rq_full; + +/* --------tmp store the whole rq pkt{begin}------- */ +assign fifo_out_ren = !pkt_store_full; +assign pkt_store_wen = !fifo_out_empty & !pkt_store_full; +pcieifc_sync_fifo #( + .DSIZE ( 1 + `DMA_KEEP_W + 8 + `DMA_DATA_W ), // 1 + 8 + 8 + 256 = 273 + .ASIZE ( 4 ) // 16 depth +) pkt_store_fifo ( + + .clk ( pcie_clk ), // i, i + .rst_n ( pcie_rst_n ), // i, i + .clr ( 1'd0 ), // i, 1 + + .wen ( pkt_store_wen ), // i, 1 + .din ( fifo_out_tdata ), // i, 1 + `DMA_KEEP_W + 8 + `DMA_DATA_W + .full ( pkt_store_full ), // o, 1 + + .ren ( pkt_store_ren ), // i, 1 + .dout ( pkt_store_tdata ), // o, 1 + `DMA_KEEP_W + 8 + `DMA_DATA_W + .empty( pkt_store_empty ) // o, 1 + +`ifdef PCIEI_APB_DBG + ,.rtsel ( 2'b0 ) // i, 2 + ,.wtsel ( 2'b0 ) // i, 2 + ,.ptsel ( 2'b0 ) // i, 2 + ,.vg ( 1'b0 ) // i, 1 + ,.vs ( 1'b0 ) // i, 1 +`endif +); + +always @(posedge pcie_clk, negedge pcie_rst_n) begin + if (~pcie_rst_n) begin + pkt_cnt <= `TD 5'd0; + end + else if (pkt_store_tdata[272] & pkt_store_ren & fifo_out_tdata[272] & pkt_store_wen) begin + pkt_cnt <= `TD pkt_cnt; + end + else if (pkt_store_tdata[272] & pkt_store_ren) begin + pkt_cnt <= `TD pkt_cnt - 5'd1; + end + else if (fifo_out_tdata[272] & pkt_store_wen) begin + pkt_cnt <= `TD pkt_cnt + 5'd1; + end +end + +assign pcie_axis_rq_tvalid = !pkt_store_empty & (pkt_cnt > 0); +assign pcie_axis_rq_tlast = pcie_axis_rq_tvalid ? pkt_store_tdata[272] : 1'd0; +assign pcie_axis_rq_tdata = pcie_axis_rq_tvalid ? pkt_store_tdata[255:0] : 256'd0; +assign pcie_axis_rq_tuser = {52'd0, pkt_store_tdata[263:256]}; +assign pcie_axis_rq_tkeep = pcie_axis_rq_tvalid ? pkt_store_tdata[271:264] : 8'd0; + +assign pkt_store_ren = pcie_axis_rq_tvalid & pcie_axis_rq_tready; +/* --------tmp store the whole rq pkt{end}------- */ + +/* -------Read Request FIFO{begin}------- */ +st_reg #( + .TUSER_WIDTH ( 60 ), + .TDATA_WIDTH ( `DMA_DATA_W + `DMA_KEEP_W ) +) st_rq ( + .clk ( pcie_clk ), // i, 1 + .rst_n ( pcie_rst_n ), // i, 1 + + /* -------input axis-like interface{begin}------- */ + .axis_tvalid ( pcie_axis_rq_tvalid ), // i, 1 + .axis_tlast ( pcie_axis_rq_tlast ), // i, 1 + .axis_tuser ( pcie_axis_rq_tuser ), // i, TUSER_WIDTH + .axis_tdata ( {pcie_axis_rq_tdata, pcie_axis_rq_tkeep} ), // i, TDATA_WIDTH + .axis_tready ( pcie_axis_rq_tready ), // o, 1 + /* -------input axis-like interface{end}------- */ + + /* -------output in_reg inteface{begin}------- */ + .axis_reg_tvalid ( st_pcie_axis_rq_tvalid ), // o, 1 + .axis_reg_tlast ( st_pcie_axis_rq_tlast ), // o, 1 + .axis_reg_tuser ( st_pcie_axis_rq_tuser ), // o, TUSER_WIDTH + .axis_reg_tdata ( {st_pcie_axis_rq_tdata, st_pcie_axis_rq_tkeep} ), // o, TDATA_WIDTH + .axis_reg_tready ( st_pcie_axis_rq_tready ) //` i, 1 + /* -------output in_reg inteface{end}------- */ +); +/* -------Read Request FIFO{end}------- */ + +endmodule diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/DMA/rrsp_async_fifo.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/DMA/rrsp_async_fifo.v new file mode 100644 index 0000000000000000000000000000000000000000..e032305cb66649c0a5e7996962c181131c963457 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/DMA/rrsp_async_fifo.v @@ -0,0 +1,142 @@ +`timescale 1ns / 100ps +//************************************************************************* +// > File Name: rrsp_async_fifos.v +// > Author : Kangning +// > Date : 2023-04-23 +// > Note : rrsp_async_fifos, used to separate rdma and pcie clock domain, +// > in RC (Requester Completion Channel). +//************************************************************************* + +//`include "../lib/global_include_h.v" + +module rrsp_async_fifos #( + +) ( + input wire dma_clk , + input wire pcie_clk , + input wire dma_rst_n , + input wire pcie_rst_n, + + /* ------- pcie clock domain{begin}------- */ + /* AXI-Stream read response tuser, interact with read response distributor. + * Only valid in first beat of a packet + * | Reserved | REQ CPL | Tag | address | Reserved | DW length | first BE | last BE | + * | 119:105 | 104 | 103:96 | 95:32 | 31:19 | 18:8 | 7:4 | 3:0 | + */ + input wire pcie_axis_rrsp_tvalid, // i, 1 + input wire pcie_axis_rrsp_tlast , // i, 1 + input wire [`DMA_DATA_W -1:0] pcie_axis_rrsp_tdata , // i, `DMA_DATA_W + input wire [`AXIS_TUSER_W-1:0] pcie_axis_rrsp_tuser , // i, `AXIS_TUSER_W + input wire [`DMA_KEEP_W -1:0] pcie_axis_rrsp_tkeep , // i, `DMA_KEEP_W + output wire pcie_axis_rrsp_tready, // o, 1 + /* ------- pcie clock domain{end}------- */ + + /* ------- dma clock domain{begin}------- */ + /* AXI-Stream read response tuser, interact with read response distributor. + * Only valid in first beat of a packet + * | Reserved | REQ CPL | Tag | address | Reserved | DW length | first BE | last BE | + * | 119:105 | 104 | 103:96 | 95:32 | 31:19 | 18:8 | 7:4 | 3:0 | + */ + output wire dma_axis_rrsp_tvalid, // o, 1 + output wire dma_axis_rrsp_tlast , // o, 1 + output wire [`DMA_DATA_W -1:0] dma_axis_rrsp_tdata , // o, `DMA_DATA_W + output wire [`AXIS_TUSER_W-1:0] dma_axis_rrsp_tuser , // o, `AXIS_TUSER_W + output wire [`DMA_KEEP_W -1:0] dma_axis_rrsp_tkeep , // o, `DMA_KEEP_W + input wire dma_axis_rrsp_tready // i, 1 + /* ------- dma clock domain{end}------- */ + +`ifdef PCIEI_APB_DBG + /* -------APB reated signal{begin}------- */ + ,input wire [`SRAM_RW_DATA_W -1:0] rw_data // i, `SRAM_RW_DATA_W + ,output wire [`RRSP_ASYNC_SIGNAL_W-1:0] dbg_signal // o, `RRSP_ASYNC_SIGNAL_W + /* -------APB reated signal{end}------- */ +`endif +); +wire pcie_axis_rrsp_full, dma_axis_rrsp_empty; + + +// | addr | last | keep | tag | req_cpl | dw_len | first BE | last BE | +// | 12 bit | 1 bit| 8 bit | 8 bit | 1 bit | 11 bit | 4 bit | 4 bit | +// | 48:37 | 36 | 35:28 | 27:20 | 19 | 18:8 | 7 : 4 | 3 : 0 | +wire [40:0] pcie_header, dma_header; + +`ifdef PCIEI_APB_DBG +/* -------APB reated signal{begin}------- */ +wire [1:0] rtsel; +wire [1:0] wtsel; +wire [1:0] ptsel; +wire vg ; +wire vs ; +/* -------APB reated signal{end}------- */ +`endif + +//--------------------------------------------------------------------------------------------------------------------------- + +`ifdef PCIEI_APB_DBG +/* -------APB reated signal{begin}------- */ +assign {rtsel, wtsel, ptsel, vg, vs} = rw_data; +assign dbg_signal = { // 84 + pcie_axis_rrsp_full, dma_axis_rrsp_empty, + dma_header, + pcie_header +}; +/* -------APB reated signal{end}------- */ +`endif + +assign pcie_header = { pcie_axis_rrsp_tuser[35:32], // addr, 4 bit + pcie_axis_rrsp_tlast, + pcie_axis_rrsp_tkeep, + pcie_axis_rrsp_tuser[103:96], // tag,, 8 bit + pcie_axis_rrsp_tuser[104], // req cpl, 1 bit + pcie_axis_rrsp_tuser[18:0]}; + +pcieifc_async_fifo #( + .DATA_WIDTH ( (41 + `DMA_DATA_W) ), + .ADDR_WIDTH ( 4 ) +) pcieifc_async_fifo ( + .wr_clk ( pcie_clk ), // i, 1 + .rd_clk ( dma_clk ), // i, 1 + .wrst_n ( pcie_rst_n ), // i, 1 + .rrst_n ( dma_rst_n ), // i, 1 + + .wen ( pcie_axis_rrsp_tvalid & pcie_axis_rrsp_tready ), // i, 1 + .din ( {pcie_header, pcie_axis_rrsp_tdata} ), // i, (1 + `DMA_KEEP_W + 32 + `DMA_DATA_W) + .full ( pcie_axis_rrsp_full ), // o, 1 + + .ren ( dma_axis_rrsp_tvalid & dma_axis_rrsp_tready ), // i, 1 + .dout ( {dma_header, dma_axis_rrsp_tdata} ), // o, (1 + `DMA_KEEP_W + 32 + `DMA_DATA_W) + .empty ( dma_axis_rrsp_empty ) // o, 1 + +`ifdef PCIEI_APB_DBG + ,.rtsel ( rtsel ) // i, 2 + ,.wtsel ( wtsel ) // i, 2 + ,.ptsel ( ptsel ) // i, 2 + ,.vg ( vg ) // i, 1 + ,.vs ( vs ) // i, 1 +`endif +); + +assign pcie_axis_rrsp_tready = !pcie_axis_rrsp_full; +assign dma_axis_rrsp_tvalid = !dma_axis_rrsp_empty; + + +// | addr | last | keep | tag | req_cpl | dw_len | first BE | last BE | +// | 12 bit | 1 bit| 8 bit | 8 bit | 1 bit | 11 bit | 4 bit | 4 bit | +// | 48:37 | 36 | 35:28 | 27:20 | 19 | 18:8 | 7 : 4 | 3 : 0 | +assign dma_axis_rrsp_tkeep = dma_header[35:28]; +assign dma_axis_rrsp_tlast = dma_header[36]; + + +/* AXI-Stream read response tuser, interact with read response distributor. + * Only valid in first beat of a packet + * | Reserved | REQ CPL | Tag | address | Reserved | DW length | first BE | last BE | + * | 119:105 | 104 | 103:96 | 95:32 | 31:19 | 18:8 | 7:4 | 3:0 | + */ +assign dma_axis_rrsp_tuser = { + 24'd0, + dma_header[19], + dma_header[27:20], + 32'd0, 28'd0, dma_header[40:37], // addr, 64 bit + 13'd0, dma_header[18:0]}; + +endmodule diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/DMA/rsp_converter.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/DMA/rsp_converter.v new file mode 100644 index 0000000000000000000000000000000000000000..539fb1ed737f6d3d7be6db73c14cc5fe164ca656 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/DMA/rsp_converter.v @@ -0,0 +1,300 @@ +`timescale 1ns / 100ps +//************************************************************************* +// > File Name: rsp_converter.v +// > Author : Kangning +// > Date : 2020-08-25 +// > Note : rsp_converter, used to convert Xilinx PCIe compatible +// > interface into AXI-Stream +//************************************************************************* + +//`include "../lib/global_include_h.v" +//`include "../lib/dma_def_h.v" + +module rsp_converter #( + +) ( + input wire dma_clk , + input wire rst_n , + + /* ------- pcie --> dma interface{begin}------- */ + // Requester Completion + /* RC tuser + * | 74:43 | 42 | 41:38 | 37:34 | 33 | 32 | 31:0 | + * | parity | discontinue | is_eof_1 | is_eof_0 | is_sof_1 | is_sof_0 | byte_en | + * | ignore | ignore | ignore | ignore | ignore | ignore | | + */ + input wire m_axis_rc_tvalid, // i, 1 + input wire m_axis_rc_tlast , // i, 1 + input wire [`DMA_DATA_W-1:0] m_axis_rc_tdata , // i, `DMA_DATA_W + input wire [74 :0] m_axis_rc_tuser , // i, 75 + input wire [`DMA_KEEP_W-1:0] m_axis_rc_tkeep , // i, `DMA_KEEP_W + output wire m_axis_rc_tready, // o, 1 + /* ------- pcie --> dma interface{end}------- */ + + + /* ------- Interface with dma read module{begin}------- */ + /* AXI-Stream read response tuser, interact with read response distributor. + * Only valid in first beat of a packet + * | Reserved | REQ CPL | Tag | address | Reserved | DW length | first BE | last BE | + * | 119:105 | 104 | 103:96 | 95:32 | 31:19 | 18:8 | 7:4 | 3:0 | + */ + output wire axis_rd_rsp_tvalid, // o, 1 + output wire axis_rd_rsp_tlast , // o, 1 + output wire [`DMA_DATA_W -1:0] axis_rd_rsp_tdata , // o, `DMA_DATA_W + output wire [`AXIS_TUSER_W-1:0] axis_rd_rsp_tuser , // o, `AXIS_TUSER_W + output wire [`DMA_KEEP_W -1:0] axis_rd_rsp_tkeep , // o, `DMA_KEEP_W + input wire axis_rd_rsp_tready // i, 1 + /* ------- Interface with dma read module{end}------- */ + +`ifdef PCIEI_APB_DBG + /* -------APB reated signal{begin}------- */ + ,input wire [31:0] dbg_sel // i, 32 + ,output wire [31:0] dbg_bus // o, 32 + /* -------APB reated signal{end}------- */ +`endif +); + +// Generate last signal of m_axis_rc_tlast, cause it doesn't work in FPGA V7 series +/* -------last generate {begin}------- */ +// reg [`DW_LEN_WIDTH-1:0] dw_left; +/* -------last generate {end}------- */ + +/* -------axis_dw_left{begin}------- */ +wire axis_next_last; // indicate that next cycle is axis_rd_rsp_last +wire [`DMA_KEEP_W -1:0] axis_keep ; +reg [`DW_LEN_WIDTH-1:0] axis_dw_left ; +/* -------axis_dw_last{end}------- */ + +/* -------tuser generation{begin}------- */ +wire [1 :0] last_dw; + +wire is_req_cpl; +wire [`TAG_WIDTH+`TAG_EMPTY-1:0] tag ; +wire [`DMA_ADDR_WIDTH -1:0] addr ; +wire [`DW_LEN_WIDTH -1:0] dw_len ; +wire [`FIRST_BE_WIDTH -1:0] first_be; +wire [`LAST_BE_WIDTH -1:0] last_be ; + +wire [`DW_LEN_WIDTH :0] total_dw; + +reg is_aligned_last; +reg [`AXIS_TUSER_W-1:0] axis_tuser; // tuser signal output in RX_IDLE state +/* -------tuser generation{end}------- */ + +/* -------data generation{begin}------- */ + +reg [159:0] tmp_reg_data; + +wire [`DMA_DATA_W-1:0] axis_tdata_rsp ; +wire [`DMA_DATA_W-1:0] axis_tdata_last; +/* -------data generation{end}------- */ + +/* -------State relevant in FSM{begin}------- */ +localparam RX_IDLE = 3'b001, // This State is used to generate tuser for other stage use, + // this state do not output, but input one beat. When input vld & rdy + // asserted at the same time (one beat data in), jump to RX_RSP; + // and if this beat is last beat, jump to RX_LAST state. + RX_RSP = 3'b010, // This state is used to output & input data, when it is last beat and + // there's data in temp register, jump to RX_LAST state. + RX_LAST = 3'b100; // Output data in temp, and jump to RX_IDLE state. Note that this state + // don't assert ready. + +reg [2:0] cur_state; +reg [2:0] nxt_state; + +wire is_rx_idle, is_rx_rsp, is_rx_last; +/* -------State relevant in FSM{end}------- */ + +`ifdef PCIEI_APB_DBG +/* -------APB reated signal{begin}------- */ +wire [`RSP_CONVERT_TOP_SIGNAL_W-1:0] dbg_signal; +/* -------APB reated signal{end}------- */ +`endif + +//--------------------------------------------------------------------------------------------------------------------------- + +`ifdef PCIEI_APB_DBG +/* -------APB reated signal{begin}------- */ +assign dbg_bus = dbg_signal >> {dbg_sel, 5'd0}; + +assign dbg_signal = { // 936 + axis_next_last, axis_keep, axis_dw_left, // 20 + last_dw, // 2 + is_req_cpl, tag, addr, dw_len, first_be, last_be, // 92 + total_dw, // 12 + is_aligned_last, // 1 + axis_tuser, // 128 + tmp_reg_data, // 160 + axis_tdata_rsp, axis_tdata_last, // 512 + cur_state, nxt_state, // 6 + is_rx_idle, is_rx_rsp, is_rx_last // 3 +}; +/* -------APB reated signal{end}------- */ +`endif + +/* -------axis_dw_left{begin}------- */ +assign axis_next_last = ( is_rx_rsp & ((8 < axis_dw_left) & (axis_dw_left <= 16))) | + ( is_rx_idle & (dw_len <= 8)) | + ((is_rx_last & m_axis_rc_tvalid & m_axis_rc_tready) & (dw_len <= 8)); +always @(posedge dma_clk, negedge rst_n) begin + if (~rst_n) begin + axis_dw_left <= `TD 0; + end + else if ((is_rx_idle & m_axis_rc_tvalid & m_axis_rc_tready) | + (is_rx_last & m_axis_rc_tvalid & m_axis_rc_tready & !is_aligned_last)) begin + axis_dw_left <= `TD dw_len; + end + else if (axis_rd_rsp_tvalid & axis_rd_rsp_tready) begin + axis_dw_left <= `TD axis_dw_left - 8; + end +end +assign axis_keep = ({`DMA_KEEP_W{axis_dw_left >= 8}} & 8'hFF) | + ({`DMA_KEEP_W{axis_dw_left == 7}} & 8'h7F) | + ({`DMA_KEEP_W{axis_dw_left == 6}} & 8'h3F) | + ({`DMA_KEEP_W{axis_dw_left == 5}} & 8'h1F) | + ({`DMA_KEEP_W{axis_dw_left == 4}} & 8'h0F) | + ({`DMA_KEEP_W{axis_dw_left == 3}} & 8'h07) | + ({`DMA_KEEP_W{axis_dw_left == 2}} & 8'h03) | + ({`DMA_KEEP_W{axis_dw_left == 1}} & 8'h01); +/* -------axis_dw_left{end}------- */ + +/* -------tuser generation{begin}------- */ +assign last_dw = m_axis_rc_tdata[17:16] + m_axis_rc_tdata[1:0]; + +assign is_req_cpl = m_axis_rc_tdata[30]; +assign tag = m_axis_rc_tdata[71:64]; +assign addr = {52'd0, m_axis_rc_tdata[11:2], 2'd0}; +assign dw_len = m_axis_rc_tdata[42:32]; +assign first_be = ({4{m_axis_rc_tdata[1:0] == 2'b00}} & 4'b1111) | + ({4{m_axis_rc_tdata[1:0] == 2'b01}} & 4'b1110) | + ({4{m_axis_rc_tdata[1:0] == 2'b10}} & 4'b1100) | + ({4{m_axis_rc_tdata[1:0] == 2'b11}} & 4'b1000); +assign last_be = m_axis_rc_tdata[30] ? + (({4{last_dw == 2'b00}} & 4'b1111) | + ({4{last_dw == 2'b01}} & 4'b0001) | + ({4{last_dw == 2'b10}} & 4'b0011) | + ({4{last_dw == 2'b11}} & 4'b0111)) : 4'b1111; + +assign total_dw = dw_len + 3; +always @(posedge dma_clk, negedge rst_n) begin + if (~rst_n) begin + axis_tuser <= `TD {`AXIS_TUSER_W{1'd0}}; + is_aligned_last <= `TD 0; + end + else if ((is_rx_idle & m_axis_rc_tvalid & m_axis_rc_tready) || // jump from idle to RX_RSP || RX_LAST + (is_rx_last & m_axis_rc_tvalid & m_axis_rc_tready & !is_aligned_last)) begin // jump from RX_LAST to RX_RSP || RX_LAST + axis_tuser <= `TD {23'd0, is_req_cpl, tag, addr, 13'd0, dw_len, + (dw_len == 1) ? (first_be & last_be) : first_be, + (dw_len == 1) ? 4'b0000 : last_be}; + is_aligned_last <= `TD ((0 == dw_len[2:0]) || (dw_len[2:0] >= 6)); + end + else if (is_rx_last & m_axis_rc_tvalid & m_axis_rc_tready & is_aligned_last) begin + axis_tuser <= `TD {`AXIS_TUSER_W{1'd0}}; + is_aligned_last <= `TD 0; + end +end +/* -------tuser generation{end}------- */ + +/* -------data & keep generation{begin}------- */ +always @(posedge dma_clk, negedge rst_n) begin + if (~rst_n) begin + tmp_reg_data <= `TD 160'd0; + end + else if ((is_rx_last & axis_rd_rsp_tready & is_aligned_last) & (m_axis_rc_tvalid & m_axis_rc_tready)) begin + tmp_reg_data <= `TD 160'd0; + end + else if ((is_rx_last & axis_rd_rsp_tready & !is_aligned_last) & (m_axis_rc_tvalid & m_axis_rc_tready)) begin + tmp_reg_data <= `TD m_axis_rc_tdata[255:96]; + end + else if (is_rx_last & axis_rd_rsp_tready & !is_aligned_last) begin + tmp_reg_data <= `TD 160'd0; + end + else if (m_axis_rc_tvalid & m_axis_rc_tready) begin + tmp_reg_data <= `TD m_axis_rc_tdata[255:96]; + end +end + + +assign axis_tdata_rsp = {m_axis_rc_tdata[95:0], tmp_reg_data}; +assign axis_tdata_last = {96'd0, tmp_reg_data}; +/* -------data & keep generation{end}------- */ + + +/* -------{RSP converter FSM}begin------- */ +/******************** Stage 1: State Register **********************/ + +assign is_rx_idle = (cur_state == RX_IDLE); +assign is_rx_rsp = (cur_state == RX_RSP ); +assign is_rx_last = (cur_state == RX_LAST); + +always @(posedge dma_clk, negedge rst_n) begin + if(~rst_n) + cur_state <= `TD RX_IDLE; + else + cur_state <= `TD nxt_state; +end + +/******************** Stage 2: State Transition **********************/ + +always @(*) begin + case(cur_state) + RX_IDLE: begin + if (m_axis_rc_tvalid & m_axis_rc_tready & axis_next_last) begin + nxt_state = RX_LAST; + end + else if (m_axis_rc_tvalid & m_axis_rc_tready & !axis_next_last) begin + nxt_state = RX_RSP; + end + else begin + nxt_state = RX_IDLE; + end + end + RX_RSP: begin + if (m_axis_rc_tvalid & m_axis_rc_tready & axis_next_last) begin + nxt_state = RX_LAST; + end + else begin + nxt_state = RX_RSP; + end + end + RX_LAST: begin + if (axis_rd_rsp_tvalid & axis_rd_rsp_tready) begin + if (m_axis_rc_tvalid & m_axis_rc_tready & is_aligned_last) begin // prevsious pkt hasn't finished yet. + nxt_state = RX_IDLE; + end + else if (m_axis_rc_tvalid & m_axis_rc_tready & axis_next_last) begin + nxt_state = RX_LAST; + end + else if (m_axis_rc_tvalid & m_axis_rc_tready & !axis_next_last) begin + nxt_state = RX_RSP; + end + else begin + nxt_state = RX_IDLE; + end + end + else begin + nxt_state = RX_LAST; + end + end + default: begin + nxt_state = RX_IDLE; + end + endcase +end + + +/******************** Stage 3: Output **********************/ + +assign m_axis_rc_tready = is_rx_idle | ((is_rx_rsp | is_rx_last) & axis_rd_rsp_tready); + +assign axis_rd_rsp_tvalid = (is_rx_rsp & m_axis_rc_tvalid) | (is_rx_last & is_aligned_last & m_axis_rc_tvalid) | (is_rx_last & !is_aligned_last); +assign axis_rd_rsp_tlast = axis_rd_rsp_tvalid & is_rx_last; +assign axis_rd_rsp_tuser = axis_rd_rsp_tvalid ? axis_tuser : 0; +assign axis_rd_rsp_tdata = ({`DMA_DATA_W{is_rx_rsp }} & axis_tdata_rsp ) | + ({`DMA_DATA_W{is_rx_last & is_aligned_last}} & axis_tdata_rsp ) | + ({`DMA_DATA_W{is_rx_last & !is_aligned_last}} & axis_tdata_last); +assign axis_rd_rsp_tkeep = axis_keep; + +/* -------{RSP converter FSM}end------- */ + +endmodule diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/P2P/P2P.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/P2P/P2P.v new file mode 100644 index 0000000000000000000000000000000000000000..77d997513d192a356c491a32e65513d6f52a81d8 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/P2P/P2P.v @@ -0,0 +1,349 @@ +`timescale 1ns / 100ps +//************************************************************************* +// > File : P2P.v +// > Author : Kangning +// > Date : 2022-06-10 +// > Note : DMA P2P initiator and target +//************************************************************************* + +module P2P #( + +) ( + input wire clk , // i, 1 + input wire rst_n , // i, 1 + output wire init_done, // o, 1 + + /* --------P2P Configuration Channel{begin}-------- */ + /* p2p_req head + * | 127 | 126:64 | 63:32 | 31:13 | 12:0 | + * | is_wr | Reserved | addr | Reserved | byte_len | + */ + input wire [1 - 1 : 0] p2p_cfg_req_valid, // i, 1 + input wire [1 - 1 : 0] p2p_cfg_req_last , // i, 1 + input wire [`P2P_HEAD_W - 1 : 0] p2p_cfg_req_head , // i, `P2P_HEAD_W + input wire [`P2P_DATA_W - 1 : 0] p2p_cfg_req_data , // i, `P2P_DATA_W + output wire [1 - 1 : 0] p2p_cfg_req_ready, // o, 1 + + output wire [1 - 1 : 0] p2p_cfg_rrsp_valid, // o, 1 + output wire [1 - 1 : 0] p2p_cfg_rrsp_last , // o, 1 + output wire [`P2P_DATA_W - 1 : 0] p2p_cfg_rrsp_data , // o, `P2P_DATA_W + input wire [1 - 1 : 0] p2p_cfg_rrsp_ready, // i, 1 + /* --------P2P Configuration Channel{end}-------- */ + + /* -------P2P Memory Access Channel{begin}-------- */ + /* p2p_req head + * | 127 | 126:64 | 63:32 | 31:13 | 12:0 | + * | is_wr | Reserved | addr | Reserved | byte_len | + */ + input wire [1 - 1 : 0] p2p_mem_req_valid, // i, 1 + input wire [1 - 1 : 0] p2p_mem_req_last , // i, 1 + input wire [`P2P_HEAD_W - 1 : 0] p2p_mem_req_head , // i, `P2P_HEAD_W + input wire [`P2P_DATA_W - 1 : 0] p2p_mem_req_data , // i, `P2P_DATA_W + output wire [1 - 1 : 0] p2p_mem_req_ready, // , 1 + /* -------P2P Memory Access Channel{end}-------- */ + + /* --------P2P DMA Write Req{begin}-------- */ + /* dma_*_head, valid only in first beat of a packet + * | Reserved | address | Reserved | Byte length | + * | 127:96 | 95:32 | 31:13 | 12:0 | + */ + output wire [1 - 1 : 0] p2p_dma_wr_req_valid, // o, 1 + output wire [1 - 1 : 0] p2p_dma_wr_req_last , // o, 1 + output wire [`DMA_HEAD_W - 1 : 0] p2p_dma_wr_req_head , // o, `DMA_HEAD_W + output wire [`P2P_DATA_W - 1 : 0] p2p_dma_wr_req_data , // o, `P2P_DATA_W + input wire [1 - 1 : 0] p2p_dma_wr_req_ready, // i, 1 + /* --------P2P DMA Write Req{end}-------- */ + + /* --------p2p forward up channel{begin}-------- */ + /* *_head, valid only in first beat of a packet + * | Reserved |dst_dev| src_dev | Reserved | Byte length | + * | 63:- | 47:40 | 39:32 | 31:16 | 15:0 | + */ + input wire [1 - 1 : 0] p2p_upper_valid, // i, 1 + input wire [1 - 1 : 0] p2p_upper_last , // i, 1 + input wire [`P2P_UHEAD_W - 1 : 0] p2p_upper_head , // i, `P2P_UHEAD_W + input wire [`P2P_DATA_W - 1 : 0] p2p_upper_data , // i, `P2P_DATA_W + output wire [1 - 1 : 0] p2p_upper_ready, // o, 1 + /* --------p2p forward up channel{end}-------- */ + + /* --------p2p forward down channel{begin}-------- */ + /* *_head, valid only in first beat of a packet + * | Reserved |dst_dev| src_dev | Reserved | Byte length | + * | 63:- | 47:40 | 39:32 | 31:16 | 15:0 | + */ + output wire [1 - 1 : 0] p2p_down_valid, // o, 1 + output wire [1 - 1 : 0] p2p_down_last , // o, 1 + output wire [`P2P_DHEAD_W - 1 : 0] p2p_down_head , // o, `P2P_DHEAD_W + output wire [`P2P_DATA_W - 1 : 0] p2p_down_data , // o, `P2P_DATA_W + input wire [1 - 1 : 0] p2p_down_ready // i, 1 + /* --------p2p forward down channel{end}-------- */ + +`ifdef PCIEI_APB_DBG + /* -------APB reated signal{begin}------- */ + ,input wire [(2*`QUEUE_NUM+4)*`SRAM_RW_DATA_W-1:0] rw_data // i, (2*`QUEUE_NUM+4)*`SRAM_RW_DATA_W + ,input wire [31:0] dbg_sel // debug bus select + ,output wire [31:0] dbg_bus // debug bus data + /* -------APB reated signal{end}------- */ +`endif + +); + +/* --------P2P Configuration Channel{begin}-------- */ +/* p2p_req head + * | 127 | 126:64 | 63:32 | 31:13 | 12:0 | + * | is_wr | Reserved | addr | Reserved | byte_len | + */ +wire [1 - 1 : 0] st_reg_p2p_cfg_req_valid; +wire [1 - 1 : 0] st_reg_p2p_cfg_req_last ; +wire [`P2P_HEAD_W - 1 : 0] st_reg_p2p_cfg_req_head ; +wire [`P2P_DATA_W - 1 : 0] st_reg_p2p_cfg_req_data ; +wire [1 - 1 : 0] st_reg_p2p_cfg_req_ready; + +wire [31:0] mem_addr; +wire [7 :0] nxt_chnl_sel; +/* --------P2P Configuration Channel{end}-------- */ + +/* --------P2P Configuration Channel{begin}-------- */ +/* p2p_req head + * | 127 | 126:64 | 63:32 | 31:13 | 12:0 | + * | is_wr | Reserved | addr | Reserved | byte_len | + */ +wire [1 - 1 : 0] p2p_tgt_req_valid, p2p_ini_req_valid; // i, 1 +wire [1 - 1 : 0] p2p_tgt_req_last , p2p_ini_req_last ; // i, 1 +wire [`P2P_DATA_W - 1 : 0] p2p_tgt_req_data , p2p_ini_req_data ; // i, `P2P_DATA_W +wire [`P2P_HEAD_W - 1 : 0] p2p_tgt_req_head , p2p_ini_req_head ; // i, `P2P_HEAD_W +wire [1 - 1 : 0] p2p_tgt_req_ready, p2p_ini_req_ready; // o, 1 +/* --------P2P Configuration Channel{end}-------- */ + +`ifdef PCIEI_APB_DBG +/* -------APB reated signal{begin}------- */ +wire [(2*`QUEUE_NUM+3)*`SRAM_RW_DATA_W-1:0] tgt_rw_data; +wire [`SRAM_RW_DATA_W-1:0] ini_rw_data; + +wire [31:0] dbg_sel_p2p_top, dbg_sel_ini, dbg_sel_tgt; +wire [31:0] dbg_bus_p2p_top, dbg_bus_ini, dbg_bus_tgt; +wire [`P2P_TOP_SIGNAL_W-1:0] dbg_signal_p2p_top; +/* -------APB reated signal{end}------- */ +`endif + +//------------------------------------------------------------------------------------------------------------------- + +`ifdef PCIEI_APB_DBG +/* -------APB reated signal{begin}------- */ +assign {ini_rw_data, tgt_rw_data} = rw_data; + +assign dbg_sel_p2p_top = (`P2P_TOP_DBG_B <= dbg_sel && dbg_sel < `INI_DBG_B ) ? (dbg_sel - `P2P_TOP_DBG_B) : 32'd0; +assign dbg_sel_ini = (`INI_DBG_B <= dbg_sel && dbg_sel < `TGT_DBG_B ) ? (dbg_sel - `INI_DBG_B ) : 32'd0; +assign dbg_sel_tgt = (`TGT_DBG_B <= dbg_sel && dbg_sel < `P2P_DBG_SIZE ) ? (dbg_sel - `TGT_DBG_B ) : 32'd0; +assign dbg_bus = (`P2P_TOP_DBG_B <= dbg_sel && dbg_sel < `INI_DBG_B ) ? dbg_bus_p2p_top : + (`INI_DBG_B <= dbg_sel && dbg_sel < `TGT_DBG_B ) ? dbg_bus_ini : + (`TGT_DBG_B <= dbg_sel && dbg_sel < `P2P_DBG_SIZE ) ? dbg_bus_tgt : 32'd0; + +// Debug bus for p2p top +assign dbg_bus_p2p_top = dbg_signal_p2p_top >> {dbg_sel_p2p_top, 5'd0}; + +// Debug signal for p2p top +assign dbg_signal_p2p_top = { // 3268 + + init_done, // 1 + p2p_cfg_req_valid, p2p_cfg_req_last , p2p_cfg_req_head , p2p_cfg_req_data , p2p_cfg_req_ready, // 387 + p2p_cfg_rrsp_valid, p2p_cfg_rrsp_last , p2p_cfg_rrsp_data , p2p_cfg_rrsp_ready, // 259 + p2p_mem_req_valid, p2p_mem_req_last , p2p_mem_req_head , p2p_mem_req_data , p2p_mem_req_ready, // 387 + p2p_dma_wr_req_valid, p2p_dma_wr_req_last , p2p_dma_wr_req_head , p2p_dma_wr_req_data , p2p_dma_wr_req_ready, // 387 + p2p_upper_valid, p2p_upper_last , p2p_upper_head , p2p_upper_data , p2p_upper_ready, // 323 + p2p_down_valid, p2p_down_last , p2p_down_head , p2p_down_data , p2p_down_ready, // 323 + st_reg_p2p_cfg_req_valid, st_reg_p2p_cfg_req_last , st_reg_p2p_cfg_req_head , st_reg_p2p_cfg_req_data , st_reg_p2p_cfg_req_ready, // 387 + mem_addr, nxt_chnl_sel, // 40 + + p2p_tgt_req_valid, p2p_ini_req_valid, + p2p_tgt_req_last , p2p_ini_req_last , + p2p_tgt_req_data , p2p_ini_req_data , + p2p_tgt_req_head , p2p_ini_req_head , + p2p_tgt_req_ready, p2p_ini_req_ready // 774 +}; +/* -------APB reated signal{end}------- */ +`endif + +/* -------- Related to demux {begin}-------- */ +assign p2p_cfg_rrsp_valid = 0; +assign p2p_cfg_rrsp_last = 0; +assign p2p_cfg_rrsp_data = 0; + +st_reg #( + .TUSER_WIDTH ( `P2P_HEAD_W ), + .TDATA_WIDTH ( `P2P_DATA_W ), + .MODE ( 1 ) +) st_reg2demux ( + .clk ( clk ), // i, 1 + .rst_n ( rst_n ), // i, 1 + + /* -------input axis-like interface{begin}------- */ + /* p2p_req head + * | 127 | 126:64 | 63:32 | 31:13 | 12:0 | + * | is_wr | Reserved | addr | Reserved | byte_len | + */ + .axis_tvalid ( p2p_cfg_req_valid ), // i, 1 + .axis_tlast ( p2p_cfg_req_last ), // i, 1 + .axis_tuser ( p2p_cfg_req_head ), // i, TUSER_WIDTH + .axis_tdata ( p2p_cfg_req_data ), // i, TDATA_WIDTH + .axis_tready ( p2p_cfg_req_ready ), // o, 1 + /* -------input axis-like interface{end}------- */ + + /* -------output in_reg inteface{begin}------- */ + /* p2p_req head + * | 127 | 126:64 | 63:32 | 31:13 | 12:0 | + * | is_wr | Reserved | addr | Reserved | byte_len | + */ + .axis_reg_tvalid ( st_reg_p2p_cfg_req_valid ), // o, 1 // read valid from input register + .axis_reg_tlast ( st_reg_p2p_cfg_req_last ), // o, 1 + .axis_reg_tuser ( st_reg_p2p_cfg_req_head ), // o, TUSER_WIDTH + .axis_reg_tdata ( st_reg_p2p_cfg_req_data ), // o, TDATA_WIDTH + .axis_reg_tready ( st_reg_p2p_cfg_req_ready ) // i, 1 + /* -------output in_reg inteface{end}------- */ +); + +assign mem_addr = p2p_cfg_req_head[63:32]; +assign nxt_chnl_sel = p2p_cfg_req_valid ? (mem_addr >= `CFG_BAR_TGT_ADDR_BASE) : 0; +st_demux #( + .CHNL_NUM ( 2 ), // number of slave signals to arbit + .CHNL_NUM_LOG ( 1 ), + .TUSER_WIDTH ( `P2P_HEAD_W ), + .TDATA_WIDTH ( `P2P_DATA_W ) +) tgt_mem_demux ( + .clk ( clk ), // i, 1 + .rst_n ( rst_n ), // i, 1 + + .nxt_chnl_vld ( p2p_cfg_req_valid ), // i, 1 + .nxt_chnl_sel ( nxt_chnl_sel ), // i, 8 + + /* --------P2P Memory Access Channel In{begin}-------- */ + /* p2p_req head + * | 127 | 126:64 | 63:32 | 31:13 | 12:0 | + * | is_wr | Reserved | addr | Reserved | byte_len | + */ + .s_axis_demux_valid ( st_reg_p2p_cfg_req_valid ), // i, 1 + .s_axis_demux_last ( st_reg_p2p_cfg_req_last ), // i, 1 + .s_axis_demux_head ( st_reg_p2p_cfg_req_head ), // i, `P2P_HEAD_W + .s_axis_demux_data ( st_reg_p2p_cfg_req_data ), // i, `P2P_DATA_W + .s_axis_demux_ready ( st_reg_p2p_cfg_req_ready ), // o, 1 + /* --------P2P Memory Access Channel In{end}-------- */ + + /* --------P2P Memory Access Channel Out{begin}-------- */ + /* p2p_req head + * | 127 | 126:64 | 63:32 | 31:13 | 12:0 | + * | is_wr | Reserved | addr | Reserved | byte_len | + */ + .m_axis_demux_valid ( {p2p_tgt_req_valid, p2p_ini_req_valid} ), // o, 2 * 1 + .m_axis_demux_last ( {p2p_tgt_req_last , p2p_ini_req_last } ), // o, 2 * 1 + .m_axis_demux_head ( {p2p_tgt_req_head , p2p_ini_req_head } ), // o, 2 * `P2P_HEAD_W + .m_axis_demux_data ( {p2p_tgt_req_data , p2p_ini_req_data } ), // o, 2 * `P2P_DATA_W + .m_axis_demux_ready ( {p2p_tgt_req_ready, p2p_ini_req_ready} ) // i, 2 * 1 + /* --------P2P Memory Access Channel Out{end}-------- */ +); +/* -------- Related to demux {end}-------- */ + +p2p_initiator #( + +) p2p_initiator ( + .clk ( clk ), // i, 1 + .rst_n ( rst_n ), // i, 1 + + /* --------P2P Configuration Channel{begin}-------- */ + /* p2p_req head + * | 127 | 126:64 | 63:32 | 31:13 | 12:0 | + * | is_wr | Reserved | addr | Reserved | byte_len | + */ + .p2p_cfg_req_valid ( p2p_ini_req_valid ), // i, 1 + .p2p_cfg_req_last ( p2p_ini_req_last ), // i, 1 + .p2p_cfg_req_data ( p2p_ini_req_data ), // i, `P2P_DATA_W + .p2p_cfg_req_head ( p2p_ini_req_head ), // i, `P2P_HEAD_W + .p2p_cfg_req_ready ( p2p_ini_req_ready ), // o, 1 + /* --------P2P Configuration Channel{end}-------- */ + + /* --------P2P DMA Write Req{begin}-------- */ + /* dma_*_head, valid only in first beat of a packet + * | Reserved | address | Reserved | Byte length | + * | 127:96 | 95:32 | 31:13 | 12:0 | + */ + .p2p_dma_wr_req_valid ( p2p_dma_wr_req_valid ), // o, 1 + .p2p_dma_wr_req_last ( p2p_dma_wr_req_last ), // o, 1 + .p2p_dma_wr_req_data ( p2p_dma_wr_req_data ), // o, `P2P_DATA_W + .p2p_dma_wr_req_head ( p2p_dma_wr_req_head ), // o, `DMA_HEAD_W + .p2p_dma_wr_req_ready ( p2p_dma_wr_req_ready ), // i, 1 + /* --------P2P DMA Write Req{end}-------- */ + + /* --------p2p forward up channel{begin}-------- */ + /* *_head, valid only in first beat of a packet + * | Reserved |dst_dev| src_dev | Reserved | Byte length | + * | 63:- | 47:40 | 39:32 | 31:16 | 15:0 | + */ + .p2p_upper_valid ( p2p_upper_valid ), // i, 1 + .p2p_upper_last ( p2p_upper_last ), // i, 1 + .p2p_upper_data ( p2p_upper_data ), // i, `P2P_DATA_W + .p2p_upper_head ( p2p_upper_head ), // i, `P2P_UHEAD_W + .p2p_upper_ready ( p2p_upper_ready ) // o, 1 + /* --------p2p forward up channel{end}-------- */ + +`ifdef PCIEI_APB_DBG + /* -------APB reated signal{begin}------- */ + ,.rw_data ( ini_rw_data ) // i, `SRAM_RW_DATA_W + ,.dbg_sel ( dbg_sel_ini ) // i, 32 + ,.dbg_bus ( dbg_bus_ini ) // o, 32 + /* -------APB reated signal{end}------- */ +`endif +); + +p2p_target #( + +) p2p_target ( + + .clk ( clk ), // i, 1 + .rst_n ( rst_n ), // i, 1 + .init_end ( init_done ), // o, 1 + + /* --------P2P Configuration Channel{begin}-------- */ + /* p2p_req head + * | 127 | 126:64 | 63:32 | 31:13 | 12:0 | + * | is_wr | Reserved | addr | Reserved | byte_len | + */ + .p2p_cfg_req_valid ( p2p_tgt_req_valid ), // i, 1 + .p2p_cfg_req_last ( p2p_tgt_req_last ), // i, 1 + .p2p_cfg_req_data ( p2p_tgt_req_data ), // i, `P2P_DATA_W + .p2p_cfg_req_head ( p2p_tgt_req_head ), // i, `P2P_HEAD_W + .p2p_cfg_req_ready ( p2p_tgt_req_ready ), // o, 1 + /* --------P2P Configuration Channel{end}-------- */ + + /* -------P2P Stream Channel{begin}-------- */ + /* p2p_req head + * | 127 | 126:64 | 63:32 | 31:13 | 12:0 | + * | is_wr | Reserved | addr | Reserved | byte_len | + */ + .p2p_mem_req_valid ( p2p_mem_req_valid ), // i, 1 + .p2p_mem_req_last ( p2p_mem_req_last ), // i, 1 + .p2p_mem_req_data ( p2p_mem_req_data ), // i, `P2P_DATA_W + .p2p_mem_req_head ( p2p_mem_req_head ), // i, `P2P_HEAD_W + .p2p_mem_req_ready ( p2p_mem_req_ready ), // o, 1 + /* -------P2P Stream Channel{end}-------- */ + + /* --------p2p forward down channel{begin}-------- */ + /* *_head, valid only in first beat of a packet + * | Reserved |dst_dev| src_dev | Reserved | Byte length | + * | 63:- | 47:40 | 39:32 | 31:16 | 15:0 | + */ + .p2p_down_valid ( p2p_down_valid ), // o, 1 + .p2p_down_last ( p2p_down_last ), // o, 1 + .p2p_down_data ( p2p_down_data ), // o, `P2P_DATA_W + .p2p_down_head ( p2p_down_head ), // o, `P2P_DHEAD_W + .p2p_down_ready ( p2p_down_ready ) // i, 1 + /* --------p2p forward down channel{end}-------- */ + +`ifdef PCIEI_APB_DBG + /* -------APB reated signal{begin}------- */ + ,.rw_data ( tgt_rw_data ) // i, (2*`QUEUE_NUM+3)*`SRAM_RW_DATA_W + ,.dbg_sel ( dbg_sel_tgt ) // i, 32 + ,.dbg_bus ( dbg_bus_tgt ) // o, 32 + /* -------APB reated signal{end}------- */ +`endif +); + +endmodule // P2P diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/P2P/ini_dev2addr_table.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/P2P/ini_dev2addr_table.v new file mode 100644 index 0000000000000000000000000000000000000000..3d56546a9e5b64350329bb5a3d8e0ae87c76122b --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/P2P/ini_dev2addr_table.v @@ -0,0 +1,181 @@ +`timescale 1ns / 100ps +//************************************************************************* +// > File Name: ini_dev2addr_table.v +// > Author : Kangning +// > Date : 2022-07-19 +// > Note : dev -> addr table that translate dev number into address. +//************************************************************************* + + +module ini_dev2addr_table #( + +) ( + input wire clk , // i, 1 + input wire rst_n , // i, 1 + + /* --------P2P Configuration Channel In{begin}-------- */ + /* p2p_req head + * | 127 | 126:64 | 63:32 | 31:13 | 12:0 | + * | is_wr | Reserved | addr | Reserved | byte_len | + */ + input wire [1 - 1 : 0] p2p_cfg_req_valid, // i, 1 + input wire [1 - 1 : 0] p2p_cfg_req_last , // i, 1 + input wire [`P2P_DATA_W - 1 : 0] p2p_cfg_req_data , // i, `P2P_DATA_W + input wire [`P2P_HEAD_W - 1 : 0] p2p_cfg_req_head , // i, `P2P_HEAD_W + output wire [1 - 1 : 0] p2p_cfg_req_ready, // o, 1 + + // output wire [1 - 1 : 0] p2p_cfg_rrsp_valid, // o, 1 + // output wire [1 - 1 : 0] p2p_cfg_rrsp_last , // o, 1 + // output wire [`P2P_DATA_W - 1 : 0] p2p_cfg_rrsp_data , // o, `P2P_DATA_W + // input wire [1 - 1 : 0] p2p_cfg_rrsp_ready, // i, 1 + /* --------P2P Configuration Channel In{end}-------- */ + + /* --------p2p forward up channel{begin}-------- */ + /* *_head, valid only in first beat of a packet + * | Reserved |dst_dev| src_dev | Reserved | Byte length | + * | 63:- | 47:40 | 39:32 | 31:16 | 15:0 | + */ + input wire [1 - 1 : 0] p2p_upper_valid, // i, 1 + input wire [1 - 1 : 0] p2p_upper_last , // i, 1 + input wire [`P2P_UHEAD_W - 1 : 0] p2p_upper_head , // i, `P2P_UHEAD_W + input wire [1 - 1 : 0] p2p_upper_ready, // i, 1 + /* --------p2p forward up channel{end}-------- */ + + /* --------Output to dst_***_proc{begin}-------- */ + output wire [1 - 1 : 0] is_valid , // o, 1 + output wire [`DEV_TYPE_WIDTH - 1 : 0] dev_type , // o, `DEV_TYPE_WIDTH + output wire [`BAR_ADDR_BASE_WIDTH - 1 : 0] bar_pyld_addr, // o, `BAR_ADDR_BASE_WIDTH, lower 14 bit is invaliid + input wire is_ready // i, 1 + /* --------Output to dst_***_proc{end}-------- */ + +`ifdef PCIEI_APB_DBG + /* -------APB reated signal{begin}------- */ + ,input wire [`SRAM_RW_DATA_W-1:0] rw_data // i, `SRAM_RW_DATA_W + ,output wire [`INI_DEV2ADDR_SIGNAL_W-1:0] dbg_signal // o, `INI_DEV2ADDR_SIGNAL_W + /* -------APB reated signal{end}------- */ +`endif +); + +localparam DEV2ADDR_TAB_WIDTH = 1 + `BAR_ADDR_BASE_WIDTH + `DEV_TYPE_WIDTH + `DEV_NUM_WIDTH; // 63 + +/* -------- related write interface{begin}-------- */ +wire wr_en; + +wire cfg_wr; + +wire [31:0] bar0_addr; +wire [`D2A_TAB_DEPTH -1: 0] wr_addr; +wire [DEV2ADDR_TAB_WIDTH-1: 0] wr_data; +wire [`BAR_ADDR_BASE_WIDTH-1:0] wr_bar_pyld_addr; +wire [`DEV_TYPE_WIDTH -1:0] wr_dev_type; +wire [`DEV_NUM_WIDTH -1:0] wr_dev_num ; +/* -------- related write interface{end}-------- */ + +/* -------- related read interface{begin}-------- */ +reg p2p_upper_sop; + +wire rd_en; +// reg rd_en_reg; +wire [`DEV_TYPE_WIDTH-1:0] dst_dev; +wire [`DEV_NUM_WIDTH -1:0] dev_num; +wire [DEV2ADDR_TAB_WIDTH-1:0] rd_data; +/* -------- related to read interface{end}-------- */ + +`ifdef PCIEI_APB_DBG +/* -------APB reated signal{begin}------- */ +wire [1:0] rtsel; +wire [1:0] wtsel; +wire [1:0] ptsel; +wire vg ; +wire vs ; +/* -------APB reated signal{end}------- */ +`endif + +//--------------------------------------------------------------------------------------------------------------------------- + +`ifdef PCIEI_APB_DBG +/* -------APB reated signal{begin}------- */ +assign {rtsel, wtsel, ptsel, vg, vs} = rw_data; +assign dbg_signal = { // 240 + wr_en, cfg_wr, bar0_addr, // 34 + wr_addr, wr_data, wr_bar_pyld_addr, wr_dev_type, wr_dev_num , // 129 + p2p_upper_sop, rd_en, dst_dev, dev_num, rd_data // 77 +}; +/* -------APB reated signal{end}------- */ +`endif + +/* -------- related write interface{begin}-------- */ +assign bar0_addr = p2p_cfg_req_head[63:32]; +assign cfg_wr = p2p_cfg_req_head[127]; + +assign wr_en = p2p_cfg_req_valid & p2p_cfg_req_ready & cfg_wr & (bar0_addr[19:`D2A_TAB_DEPTH + 4] == (`CFG_BAR_INI_ADDR_BASE >> (4 + `D2A_TAB_DEPTH))); +assign wr_addr = wr_en ? bar0_addr[`D2A_TAB_DEPTH + 4 - 1 : 4] : 0; +assign wr_dev_num = p2p_cfg_req_data[7:0]; +assign wr_dev_type = p2p_cfg_req_data[11:8]; +assign wr_bar_pyld_addr = p2p_cfg_req_data[63:14]; +assign wr_data = {1'd1, wr_bar_pyld_addr, wr_dev_type, wr_dev_num}; +/* -------- related write interface{end}-------- */ + +/* -------- related read interface{begin}-------- */ +assign dst_dev = p2p_upper_head[32+2*`DEV_NUM_WIDTH-1:32+`DEV_NUM_WIDTH]; +assign rd_en = p2p_upper_sop & p2p_upper_valid & p2p_upper_ready; +always @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + p2p_upper_sop <= `TD 1'd1; + end + else if (p2p_upper_valid & p2p_upper_ready & p2p_upper_last) begin + p2p_upper_sop <= `TD 1'd1; + end + else if (p2p_upper_valid & p2p_upper_ready) begin + p2p_upper_sop <= `TD 1'd0; + end +end + +// always @(posedge clk, negedge rst_n) begin +// if (~rst_n) begin +// rd_en_reg <= `TD 1'd0; +// end +// else if (rd_en) begin +// rd_en_reg <= `TD 1'd1; +// end +// else if (is_ready) begin +// rd_en_reg <= `TD 1'd0; +// end +// end +/* -------- related to read interface{end}-------- */ + +pcieifc_sd_sram #( + .DATAWIDTH ( DEV2ADDR_TAB_WIDTH ), // Memory data word width, 63 + .ADDRWIDTH ( `D2A_TAB_DEPTH ) // Number of mem address bits, 4 +) dev2addr_tab ( + .clk ( clk ), // i, 1 + .rst_n ( rst_n ), // i, 1 + + .wea ( wr_en ), // i, 1; high active + .addra ( wr_addr ), // i, ADDRWIDTH + .dina ( wr_data ), // i, DATAWIDTH + + .reb ( rd_en ), // i, 1 + .addrb ( dst_dev ), // i, ADDRWIDTH + .doutb ( rd_data ) // o, DATAWIDTH + +`ifdef PCIEI_APB_DBG + ,.rtsel ( rtsel ) // i, 2 + ,.wtsel ( wtsel ) // i, 2 + ,.ptsel ( ptsel ) // i, 2 + ,.vg ( vg ) // i, 1 + ,.vs ( vs ) // i, 1 +`endif +); + +assign {is_valid, bar_pyld_addr, dev_type, dev_num} = rd_data; // rd_en_reg ? rd_data : 0; +/* --------CFG interface{begin}-------- */ +assign p2p_cfg_req_ready = !rd_en; + +// We don't support cfg space read. +// assign p2p_cfg_rrsp_valid = 0; +// assign p2p_cfg_rrsp_last = 0; +// assign p2p_cfg_rrsp_data = 0; +/* --------CFG interface{end}-------- */ + +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/P2P/ini_dst_nic_proc.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/P2P/ini_dst_nic_proc.v new file mode 100644 index 0000000000000000000000000000000000000000..410a03638373a648f9468ba36399f258f3e799cc --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/P2P/ini_dst_nic_proc.v @@ -0,0 +1,170 @@ +`timescale 1ns / 100ps +//************************************************************************* +// > File Name: ini_dst_nic_proc.v +// > Author : Kangning +// > Date : 2022-07-25 +// > Note : Related processing if destination address is belongs to NIC. +//************************************************************************* + + +module ini_dst_nic_proc #( + +) ( + + input wire clk , // i, 1 + input wire rst_n , // i, 1 + + /* -------next pkt information{begin}-------- */ + input wire nxt_is_valid, // i, 1 + input wire [`DEV_TYPE_WIDTH - 1 : 0] nxt_dev_type, // i, `DEV_TYPE_WIDTH + input wire [`BAR_ADDR_BASE_WIDTH - 1 : 0] nxt_bar_addr, // i, `BAR_ADDR_BASE_WIDTH + /* -------next pkt information{end}-------- */ + + /* --------p2p forward up channel{begin}-------- */ + /* *_head, valid only in first beat of a packet + * | Reserved |dst_dev| src_dev | Reserved | Byte length | + * | 63:- | 47:40 | 39:32 | 31:16 | 15:0 | + */ + input wire p2p_upper_valid, // i, 1 + input wire p2p_upper_last , // i, 1 + input wire [`P2P_UHEAD_W - 1 : 0] p2p_upper_head , // i, `P2P_UHEAD_W + input wire [`P2P_DATA_W - 1 : 0] p2p_upper_data , // i, `P2P_DATA_W + output wire p2p_upper_ready, // o, 1 + /* --------p2p forward up channel{end}-------- */ + + /* --------current pkt information{begin}-------- */ + input wire is_valid, // i, 1 + input wire [`DEV_TYPE_WIDTH - 1 : 0] dev_type, // i, `DEV_TYPE_WIDTH + input wire [`BAR_ADDR_BASE_WIDTH - 1 : 0] bar_addr, // i, `BAR_ADDR_BASE_WIDTH + /* --------current pkt information{end}-------- */ + + /* -------output inteface{begin}------- */ + /* dma_*_head + * | Reserved | address | Reserved | Byte length | + * | 127:96 | 95:32 | 31:16 | 15:0 | + */ + output wire axis_nic_valid, // o, 1 + output wire axis_nic_last , // o, 1 + output wire [`DMA_HEAD_W - 1 : 0] axis_nic_head , // o, `DMA_HEAD_W + output wire [`P2P_DATA_W - 1 : 0] axis_nic_data , // o, `P2P_DATA_W + input wire axis_nic_ready // i, 1 + /* -------output inteface{end}------- */ +); + +localparam P2P_BYTE_NUM = `P2P_DATA_W / 8; // byte num in one beat + +/* -------- FSM when Destination is NIC{begin}-------- */ +localparam IDLE = 3'b001, + TX_DESC = 3'b010, + TX_PYLD = 3'b100; + +reg [2:0] cur_state, nxt_state; +wire is_idle, is_tx_desc, is_tx_pyld; +/* -------- FSM when Destination is NIC{end}-------- */ + +/* -------- Output head generation {begin} -------- */ +reg [15:0] byte_left; + +wire [`DEV_NUM_WIDTH-1:0] pyld_dst_dev, pyld_src_dev; +wire [15:0] pyld_byte_len; +wire [63:0] pyld_addr; + +wire [15:0] desc_byte_len; +wire [63:0] desc_addr; + +wire [`P2P_DATA_W-1:0] pyld_data_w, desc_data_w; +wire [`DMA_HEAD_W-1:0] pyld_head_w, desc_head_w; +/* -------- Output head generation {end} -------- */ + +//----------------------------------------------------------------------------------------------------------------------------------------------// + +/* -------- Output head generation {begin} -------- */ +always @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + byte_left <= `TD 0; + end + else if (is_tx_pyld & axis_nic_valid & axis_nic_ready & axis_nic_last) begin + byte_left <= `TD 0; + end + else if (is_tx_desc & axis_nic_valid & axis_nic_ready) begin + byte_left <= `TD pyld_byte_len; + end + else if (is_tx_pyld & axis_nic_valid & axis_nic_ready) begin + byte_left <= `TD byte_left - P2P_BYTE_NUM; + end +end + +assign pyld_head_w = {32'd0, pyld_addr, 16'd0, pyld_byte_len}; +assign pyld_data_w = p2p_upper_data; + +assign desc_head_w = {32'd0, desc_addr, 16'd0, desc_byte_len}; +assign desc_data_w = {192'd0, pyld_dst_dev, pyld_src_dev, pyld_byte_len, 32'd0}; + +assign pyld_dst_dev = p2p_upper_head[32+2*`DEV_NUM_WIDTH-1:32+`DEV_NUM_WIDTH]; +assign pyld_src_dev = p2p_upper_head[32+`DEV_NUM_WIDTH-1:32]; +assign pyld_byte_len = p2p_upper_head[15:0]; +assign pyld_addr = {bar_addr, 14'd0}; + +assign desc_byte_len = 16'd16; +assign desc_addr = {bar_addr, 14'h0} + `BAR_DESC_OFFSET; +/* -------- Output head generation {end} -------- */ + +/* -------Destinstaion NIC processing FSM{begin}------- */ +/******************** Stage 1: State Register **********************/ +assign is_idle = (cur_state == IDLE ); +assign is_tx_desc = (cur_state == TX_DESC); +assign is_tx_pyld = (cur_state == TX_PYLD); + +always @(posedge clk, negedge rst_n) begin + if(~rst_n) + cur_state <= `TD IDLE; + else + cur_state <= `TD nxt_state; +end + +/******************** Stage 2: State Transition **********************/ + +always @(*) begin + case(cur_state) + IDLE: begin + if (nxt_dev_type == `DEV_NIC & nxt_is_valid) // Imlying the only beat + nxt_state = TX_DESC; + else + nxt_state = IDLE; + end + TX_DESC: begin + if (axis_nic_valid & axis_nic_ready) + nxt_state = TX_PYLD; + else + nxt_state = TX_DESC; + end + TX_PYLD: begin + if (axis_nic_valid & axis_nic_ready & axis_nic_last) begin + if (nxt_dev_type == `DEV_NIC & nxt_is_valid) + nxt_state = TX_DESC; + else + nxt_state = IDLE; + end + else + nxt_state = TX_PYLD; + end + default: begin + nxt_state = IDLE; + end + endcase +end +/******************** Stage 3: Output **********************/ + +assign axis_nic_valid = is_tx_desc | + (is_tx_pyld & p2p_upper_valid); +assign axis_nic_last = is_tx_desc | + (is_tx_pyld & (byte_left <= 16'd32)); +assign axis_nic_head = ({`DMA_HEAD_W{is_tx_desc}} & desc_head_w) | + ({`DMA_HEAD_W{is_tx_pyld}} & pyld_head_w); +assign axis_nic_data = ({`P2P_DATA_W{is_tx_desc}} & desc_data_w) | + ({`P2P_DATA_W{is_tx_pyld}} & pyld_data_w); + +assign p2p_upper_ready = is_tx_pyld & axis_nic_ready; +/* -------Destinstaion NIC processing FSM{end}------- */ + +endmodule diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/P2P/ini_pyld_split_proc.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/P2P/ini_pyld_split_proc.v new file mode 100644 index 0000000000000000000000000000000000000000..7c4be9eb8f5aafa6b555d4b03c7b8b2ab72a9e02 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/P2P/ini_pyld_split_proc.v @@ -0,0 +1,48 @@ +`timescale 1ns / 100ps +//************************************************************************* +// > File Name: ini_pyld_split_proc.v +// > Author : Kangning +// > Date : 2022-07-27 +// > Note : split payload into 4KB aligned packet +//************************************************************************* + + +module ini_pyld_split_proc #( + +) ( + + input wire clk , // i, 1 + input wire rst_n , // i, 1 + + /* --------raw pyld{begin}-------- */ + /* dma_*_head + * | Reserved | address | Reserved | Byte length | + * | 127:96 | 95:32 | 31:16 | 15:0 | + */ + input wire axis_raw_valid, // i, 1 + input wire axis_raw_last , // i, 1 + input wire [`DMA_HEAD_W - 1 : 0] axis_raw_head , // i, `DMA_HEAD_W + input wire [`P2P_DATA_W - 1 : 0] axis_raw_data , // i, `P2P_DATA_W + output wire axis_raw_ready, // o, 1 + /* --------raw pyld{end}-------- */ + + /* -------splited_pyld{begin}------- */ + /* dma_*_head + * | Reserved | address | Reserved | Byte length | + * | 127:96 | 95:32 | 31:16 | 15:0 | + */ + output wire axis_splited_valid, // o, 1 + output wire axis_splited_last , // o, 1 + output wire [`DMA_HEAD_W - 1 : 0] axis_splited_head , // o, `DMA_HEAD_W + output wire [`P2P_DATA_W - 1 : 0] axis_splited_data , // o, `P2P_DATA_W + input wire axis_splited_ready // i, 1 + /* -------splited_pyld{end}------- */ +); + +assign axis_splited_valid = axis_raw_valid; +assign axis_splited_last = axis_raw_last ; +assign axis_splited_head = axis_raw_head ; +assign axis_splited_data = axis_raw_data ; +assign axis_raw_ready = axis_splited_ready; + +endmodule diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/P2P/p2p_initiator.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/P2P/p2p_initiator.v new file mode 100644 index 0000000000000000000000000000000000000000..918cb011b40d0cb76643ed78ad6fdd193ba7ff82 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/P2P/p2p_initiator.v @@ -0,0 +1,312 @@ +`timescale 1ns / 100ps +//************************************************************************* +// > File : p2p_initiator.v +// > Author : Kangning +// > Date : 2022-06-10 +// > Note : DMA P2P initiator +//************************************************************************* + +module p2p_initiator #( + +) ( + input wire clk , // i, 1 + input wire rst_n , // i, 1 + + /* --------P2P Configuration Channel{begin}-------- */ + /* p2p_req head + * | 127 | 126:64 | 63:32 | 31:13 | 12:0 | + * | is_wr | Reserved | addr | Reserved | byte_len | + */ + input wire [1 - 1 : 0] p2p_cfg_req_valid, // i, 1 + input wire [1 - 1 : 0] p2p_cfg_req_last , // i, 1 + input wire [`P2P_HEAD_W - 1 : 0] p2p_cfg_req_head , // i, `P2P_HEAD_W + input wire [`P2P_DATA_W - 1 : 0] p2p_cfg_req_data , // i, `P2P_DATA_W + output wire [1 - 1 : 0] p2p_cfg_req_ready, // o, 1 + + // output wire [1 - 1 : 0] p2p_cfg_rrsp_valid, // o, 1 + // output wire [1 - 1 : 0] p2p_cfg_rrsp_last , // o, 1 + // output wire [`P2P_DATA_W - 1 : 0] p2p_cfg_rrsp_data , // o, `P2P_DATA_W + // input wire [1 - 1 : 0] p2p_cfg_rrsp_ready, // i, 1 + /* --------P2P Configuration Channel{end}-------- */ + + /* --------P2P DMA Write Req{begin}-------- */ + /* dma_*_head + * | Reserved | address | Reserved | Byte length | + * | 127:96 | 95:32 | 31:13 | 12:0 | + */ + output wire [1 - 1 : 0] p2p_dma_wr_req_valid, // o, 1 + output wire [1 - 1 : 0] p2p_dma_wr_req_last , // o, 1 + output wire [`DMA_HEAD_W - 1 : 0] p2p_dma_wr_req_head , // o, `DMA_HEAD_W + output wire [`P2P_DATA_W - 1 : 0] p2p_dma_wr_req_data , // o, `P2P_DATA_W + input wire [1 - 1 : 0] p2p_dma_wr_req_ready, // i, 1 + /* --------P2P DMA Write Req{end}-------- */ + + /* --------p2p forward up channel{begin}-------- */ + /* *_head, valid only in first beat of a packet + * | Reserved |dst_dev| src_dev | Reserved | Byte length | + * | 63:- | 47:40 | 39:32 | 31:16 | 15:0 | + */ + input wire [1 - 1 : 0] p2p_upper_valid, // i, 1 + input wire [1 - 1 : 0] p2p_upper_last , // i, 1 + input wire [`P2P_UHEAD_W - 1 : 0] p2p_upper_head , // i, `P2P_UHEAD_W + input wire [`P2P_DATA_W - 1 : 0] p2p_upper_data , // i, `P2P_DATA_W + output wire [1 - 1 : 0] p2p_upper_ready // o, 1 + /* --------p2p forward up channel{end}-------- */ + +`ifdef PCIEI_APB_DBG + /* -------APB reated signal{begin}------- */ + ,input wire [`SRAM_RW_DATA_W-1:0] rw_data // i, `SRAM_RW_DATA_W + ,input wire [31:0] dbg_sel // i, 32 + ,output wire [31:0] dbg_bus // o, 32 + /* -------APB reated signal{end}------- */ +`endif +); + +// /* -------next pkt information{begin}-------- */ +// wire nxt_is_valid; // i, 1 +// wire [`DEV_TYPE_WIDTH - 1 : 0] nxt_dev_type; // i, `DEV_TYPE_WIDTH +// wire [`BAR_ADDR_BASE_WIDTH - 1 : 0] nxt_bar_addr; // i, `BAR_ADDR_BASE_WIDTH +// /* -------next pkt information{end}-------- */ + +/* --------current pkt information{begin}-------- */ +wire is_valid; // i, 1 +wire [`DEV_TYPE_WIDTH - 1 : 0] dev_type; // i, `DEV_TYPE_WIDTH +wire [`BAR_ADDR_BASE_WIDTH - 1 : 0] bar_addr; // i, `BAR_ADDR_BASE_WIDTH +/* --------current pkt information{end}-------- */ + +/* --------current pkt information{begin}-------- */ +wire st1_is_valid; // i, 1 +wire [`DEV_TYPE_WIDTH - 1 : 0] st1_dev_type; // i, `DEV_TYPE_WIDTH +wire [`BAR_ADDR_BASE_WIDTH - 1 : 0] st1_bar_addr; // i, `BAR_ADDR_BASE_WIDTH +/* --------current pkt information{end}-------- */ + +/* -------Related to NIC and DSA module{begin}-------- */ +wire st0_upper_valid; +wire st0_upper_last ; +wire [`P2P_UHEAD_W - 1 : 0] st0_upper_head ; +wire [`P2P_DATA_W - 1 : 0] st0_upper_data ; +wire st0_upper_ready; + +wire st1_upper_valid; +wire st1_upper_last ; +wire [`P2P_UHEAD_W - 1 : 0] st1_upper_head ; +wire [`P2P_DATA_W - 1 : 0] st1_upper_data ; +wire st1_upper_ready; +/* -------Related to NIC and DSA module{end}-------- */ + +/* -------MUX -> pyld_split_proc{begin}------- */ +/* dma_*_head + * | Reserved | address | Reserved | Byte length | + * | 127:96 | 95:32 | 31:16 | 15:0 | + */ +wire axis_proc_out_valid; // o, 1 +wire axis_proc_out_last ; // o, 1 +wire [`DMA_HEAD_W - 1 : 0] axis_proc_out_head ; // o, `DMA_HEAD_W +wire [`P2P_DATA_W - 1 : 0] axis_proc_out_data ; // o, `P2P_DATA_W +wire axis_proc_out_ready; // i, 1 +/* -------MUX -> pyld_split_proc{end}------- */ + +`ifdef PCIEI_APB_DBG +/* -------APB reated signal{begin}------- */ +wire [`INI_TOP_SIGNAL_W-1:0] dbg_signal_ini_top; +wire [`INI_DEV2ADDR_SIGNAL_W-1:0] dbg_signal_ini_dev2addr; +/* -------APB reated signal{end}------- */ +`endif + +//------------------------------------------------------------------------------------------------------------------- + +`ifdef PCIEI_APB_DBG +/* -------APB reated signal{begin}------- */ + +// Debug bus for p2p ini +assign dbg_bus = {dbg_signal_ini_top, dbg_signal_ini_dev2addr} >> {dbg_sel, 5'd0}; + +// Debug signal for p2p ini top +assign dbg_signal_ini_top = { // 1143 + + is_valid, dev_type, bar_addr, // 55 + st1_is_valid, st1_dev_type, st1_bar_addr, // 55 + st0_upper_valid, st0_upper_last , st0_upper_head , st0_upper_data , st0_upper_ready, // 323 + st1_upper_valid, st1_upper_last , st1_upper_head , st1_upper_data , st1_upper_ready, // 323 + axis_proc_out_valid, axis_proc_out_last , axis_proc_out_head , axis_proc_out_data , axis_proc_out_ready // 387 +}; +/* -------APB reated signal{end}------- */ +`endif + +ini_dev2addr_table #( + +) ini_dev2addr_table ( + .clk ( clk ), // i, 1 + .rst_n ( rst_n ), // i, 1 + + /* --------P2P Configuration Channel In{begin}-------- */ + /* p2p_req head + * | 127 | 126:64 | 63:32 | 31:13 | 12:0 | + * | is_wr | Reserved | addr | Reserved | byte_len | + */ + .p2p_cfg_req_valid ( p2p_cfg_req_valid ), // i, 1 + .p2p_cfg_req_last ( p2p_cfg_req_last ), // i, 1 + .p2p_cfg_req_data ( p2p_cfg_req_data ), // i, `P2P_DATA_W + .p2p_cfg_req_head ( p2p_cfg_req_head ), // i, `P2P_HEAD_W + .p2p_cfg_req_ready ( p2p_cfg_req_ready ), // o, 1 + + // .p2p_cfg_rrsp_valid ( p2p_cfg_rrsp_valid ), // o, 1 + // .p2p_cfg_rrsp_last ( p2p_cfg_rrsp_last ), // o, 1 + // .p2p_cfg_rrsp_data ( p2p_cfg_rrsp_data ), // o, `P2P_DATA_W + // .p2p_cfg_rrsp_ready ( p2p_cfg_rrsp_ready ), // i, 1 + /* --------P2P Configuration Channel In{end}-------- */ + + /* --------p2p forward up channel{begin}-------- */ + /* *_head, valid only in first beat of a packet + * | Reserved |dst_dev| src_dev | Reserved | Byte length | + * | 63:- | 47:40 | 39:32 | 31:16 | 15:0 | + */ + .p2p_upper_valid ( p2p_upper_valid ), // i, 1 + .p2p_upper_last ( p2p_upper_last ), // i, 1 + .p2p_upper_head ( p2p_upper_head ), // i, `P2P_UHEAD_W + .p2p_upper_ready ( p2p_upper_ready ), // i, 1 + /* --------p2p forward up channel{end}-------- */ + + /* --------Output to dst_***_proc{begin}-------- */ + .is_valid ( is_valid ), // o, 1 + .dev_type ( dev_type ), // o, 4 + .bar_pyld_addr ( bar_addr ), // o, 64, lower 14 bit is invaliid + .is_ready ( st0_upper_ready ) // i, 1 + /* --------Output to dst_***_proc{end}-------- */ + +`ifdef PCIEI_APB_DBG + /* -------APB reated signal{begin}------- */ + ,.rw_data ( rw_data ) // i, `SRAM_RW_DATA_W + ,.dbg_signal ( dbg_signal_ini_dev2addr ) // o, `INI_DEV2ADDR_SIGNAL_W + /* -------APB reated signal{end}------- */ +`endif +); + +/* + * This reg is used to stall for looking up the dev2addr table + */ +st_reg #( + .TUSER_WIDTH ( `P2P_UHEAD_W ), + .TDATA_WIDTH ( `P2P_DATA_W ), + .MODE ( 1 ) +) st_reg0 ( + .clk ( clk ), // i, 1 + .rst_n ( rst_n ), // i, 1 + + /* -------input axis-like interface{begin}------- */ + .axis_tvalid ( p2p_upper_valid ), // i, 1 + .axis_tlast ( p2p_upper_last ), // i, 1 + .axis_tuser ( p2p_upper_head ), // i, TUSER_WIDTH + .axis_tdata ( p2p_upper_data ), // i, TDATA_WIDTH + .axis_tready ( p2p_upper_ready ), // o, 1 + /* -------input axis-like interface{end}------- */ + + /* -------output in_reg inteface{begin}------- */ + .axis_reg_tvalid ( st0_upper_valid ), // o, 1 // read valid from input register + .axis_reg_tlast ( st0_upper_last ), // o, 1 + .axis_reg_tuser ( st0_upper_head ), // o, TUSER_WIDTH + .axis_reg_tdata ( st0_upper_data ), // o, TDATA_WIDTH + .axis_reg_tready ( st0_upper_ready ) // i, 1 + /* -------output in_reg inteface{end}------- */ +); + +st_reg #( + .TUSER_WIDTH ( 1 + `DEV_TYPE_WIDTH + `BAR_ADDR_BASE_WIDTH + `P2P_UHEAD_W ), + .TDATA_WIDTH ( `P2P_DATA_W ), + .MODE ( 1 ) +) st_reg1 ( + .clk ( clk ), // i, 1 + .rst_n ( rst_n ), // i, 1 + + /* -------input axis-like interface{begin}------- */ + .axis_tvalid ( st0_upper_valid ), // i, 1 + .axis_tlast ( st0_upper_last ), // i, 1 + .axis_tuser ( {is_valid, dev_type, bar_addr, st0_upper_head} ), // i, TUSER_WIDTH + .axis_tdata ( st0_upper_data ), // i, TDATA_WIDTH + .axis_tready ( st0_upper_ready ), // o, 1 + /* -------input axis-like interface{end}------- */ + + /* -------output in_reg inteface{begin}------- */ + .axis_reg_tvalid ( st1_upper_valid ), // o, 1 // read valid from input register + .axis_reg_tlast ( st1_upper_last ), // o, 1 + .axis_reg_tuser ( {st1_is_valid, st1_dev_type, st1_bar_addr, st1_upper_head} ), // o, TUSER_WIDTH + .axis_reg_tdata ( st1_upper_data ), // o, TDATA_WIDTH + .axis_reg_tready ( st1_upper_ready ) // i, 1 + /* -------output in_reg inteface{end}------- */ +); + +ini_dst_nic_proc #( + +) ini_dst_nic_proc ( + .clk ( clk ), // i, 1 + .rst_n ( rst_n ), // i, 1 + + /* -------next pkt information{begin}-------- */ + .nxt_is_valid ( is_valid & st0_upper_valid ), // i, 1 + .nxt_dev_type ( dev_type ), // i, `DEV_TYPE_WIDTH + .nxt_bar_addr ( bar_addr ), // i, `BAR_ADDR_BASE_WIDTH + /* -------next pkt information{end}-------- */ + + /* --------p2p forward up channel{begin}-------- */ + /* *_head, valid only in first beat of a packet + * | Reserved |dst_dev| src_dev | Reserved | Byte length | + * | 63:- | 47:40 | 39:32 | 31:16 | 15:0 | + */ + .p2p_upper_valid ( st1_upper_valid ), // i, 1 + .p2p_upper_last ( st1_upper_last ), // i, 1 + .p2p_upper_head ( st1_upper_head ), // i, `P2P_UHEAD_W + .p2p_upper_data ( st1_upper_data ), // i, `P2P_DATA_W + .p2p_upper_ready ( st1_upper_ready ), // o, 1 + /* --------p2p forward up channel{end}-------- */ + + /* --------current pkt information{begin}-------- */ + .is_valid ( st1_is_valid ), // i, 1 + .dev_type ( st1_dev_type ), // i, `DEV_TYPE_WIDTH + .bar_addr ( st1_bar_addr ), // i, `BAR_ADDR_BASE_WIDTH + /* --------current pkt information{end}-------- */ + + /* -------output inteface{begin}------- */ + /* dma_*_head + * | Reserved | address | Reserved | Byte length | + * | 127:96 | 95:32 | 31:16 | 15:0 | + */ + .axis_nic_valid ( axis_proc_out_valid ), // o, 1 + .axis_nic_last ( axis_proc_out_last ), // o, 1 + .axis_nic_head ( axis_proc_out_head ), // o, `DMA_HEAD_W + .axis_nic_data ( axis_proc_out_data ), // o, `P2P_DATA_W + .axis_nic_ready ( axis_proc_out_ready ) // i, 1 + /* -------output inteface{end}------- */ +); + +ini_pyld_split_proc #( + +) ini_pyld_split_proc ( + .clk ( clk ), // i, 1 + .rst_n ( rst_n ), // i, 1 + + /* --------raw pyld{begin}-------- */ + /* dma_*_head + * | Reserved | address | Reserved | Byte length | + * | 127:96 | 95:32 | 31:16 | 15:0 | + */ + .axis_raw_valid ( axis_proc_out_valid ), // o, 1 + .axis_raw_last ( axis_proc_out_last ), // o, 1 + .axis_raw_head ( axis_proc_out_head ), // o, `DMA_HEAD_W + .axis_raw_data ( axis_proc_out_data ), // o, `P2P_DATA_W + .axis_raw_ready ( axis_proc_out_ready ), // i, 1 + /* --------raw pyld{end}-------- */ + + /* --------splited_pyld{begin}-------- */ + /* dma_*_head + * | Reserved | address | Reserved | Byte length | + * | 127:96 | 95:32 | 31:13 | 12:0 | + */ + .axis_splited_valid ( p2p_dma_wr_req_valid ), // o, 1 + .axis_splited_last ( p2p_dma_wr_req_last ), // o, 1 + .axis_splited_head ( p2p_dma_wr_req_head ), // o, `DMA_HEAD_W + .axis_splited_data ( p2p_dma_wr_req_data ), // o, `P2P_DATA_W + .axis_splited_ready ( p2p_dma_wr_req_ready ) // i, 1 + /* --------splited_pyld{end}-------- */ +); + +endmodule // p2p_initiator diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/P2P/p2p_target.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/P2P/p2p_target.v new file mode 100644 index 0000000000000000000000000000000000000000..c9633ff98b866cfc987603aa486cfd43c9ee9144 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/P2P/p2p_target.v @@ -0,0 +1,601 @@ +`timescale 1ns / 100ps +//************************************************************************* +// > File : p2p_target.v +// > Author : Kangning +// > Date : 2022-06-10 +// > Note : DMA P2P target +//************************************************************************* + + +module p2p_target #( + +) ( + input wire clk , // i, 1 + input wire rst_n , // i, 1 + output wire init_end, // o, 1 + + /* --------P2P Configuration Channel{begin}-------- */ + /* p2p_req head + * | 127 | 126:64 | 63:32 | 31:13 | 12:0 | + * | is_wr | Reserved | addr | Reserved | byte_len | + */ + input wire p2p_cfg_req_valid, // i, 1 + input wire p2p_cfg_req_last , // i, 1 + input wire [`P2P_DATA_W - 1 : 0] p2p_cfg_req_data , // i, `P2P_DATA_W + input wire [`P2P_HEAD_W - 1 : 0] p2p_cfg_req_head , // i, `P2P_HEAD_W + output wire p2p_cfg_req_ready, // o, 1 + + // output wire p2p_cfg_rrsp_valid, // o, 1 + // output wire p2p_cfg_rrsp_last , // o, 1 + // output wire [`P2P_DATA_W - 1 : 0] p2p_cfg_rrsp_data , // o, `P2P_DATA_W + // input wire p2p_cfg_rrsp_ready, // i, 1 + /* --------P2P Configuration Channel{end}-------- */ + + /* -------P2P Stream Channel{begin}-------- */ + /* p2p_req head + * | 127 | 126:64 | 63:32 | 31:13 | 12:0 | + * | is_wr | Reserved | addr | Reserved | byte_len | + */ + input wire p2p_mem_req_valid, // i, 1 + input wire p2p_mem_req_last , // i, 1 + input wire [`P2P_DATA_W - 1 : 0] p2p_mem_req_data , // i, `P2P_DATA_W + input wire [`P2P_HEAD_W - 1 : 0] p2p_mem_req_head , // i, `P2P_HEAD_W + output wire p2p_mem_req_ready, // o, 1 + /* -------P2P Stream Channel{end}-------- */ + + /* --------p2p forward down channel{begin}-------- */ + /* *_head, valid only in first beat of a packet + * | Reserved |dst_dev| src_dev | Reserved | Byte length | + * | 63:- | 47:40 | 39:32 | 31:16 | 15:0 | + */ + output wire p2p_down_valid, // o, 1 + output wire p2p_down_last , // o, 1 + output wire [`P2P_DATA_W - 1 : 0] p2p_down_data , // o, `P2P_DATA_W + output wire [`P2P_DHEAD_W - 1 : 0] p2p_down_head , // o, `P2P_DHEAD_W + input wire p2p_down_ready // i, 1 + /* --------p2p forward down channel{end}-------- */ + +`ifdef PCIEI_APB_DBG + /* -------APB reated signal{begin}------- */ + ,input wire [(2*`QUEUE_NUM+3)*`SRAM_RW_DATA_W-1:0] rw_data // i, (2*`QUEUE_NUM+3)*`SRAM_RW_DATA_W + ,input wire [31:0] dbg_sel // i, 32 + ,output wire [31:0] dbg_bus // o, 32 + /* -------APB reated signal{end}------- */ +`endif +); + +/* -------- Related to demux {begin}-------- */ +/* p2p_req head + * | 127 | 126:64 | 63:32 | 31:13 | 12:0 | + * | is_wr | Reserved | addr | Reserved | byte_len | + */ +wire st_reg_p2p_mem_req_valid; +wire st_reg_p2p_mem_req_last ; +wire [`P2P_HEAD_W - 1 : 0] st_reg_p2p_mem_req_head ; +wire [`P2P_DATA_W - 1 : 0] st_reg_p2p_mem_req_data ; +wire st_reg_p2p_mem_req_ready; + +wire [31:0] mem_addr; +wire [7 :0] nxt_chnl_sel; +/* -------- Related to demux {end}-------- */ + +wire p2p_mem_desc_req_valid, p2p_mem_pyld_req_valid, st0_p2p_pyld_req_valid; +wire p2p_mem_desc_req_last , p2p_mem_pyld_req_last , st0_p2p_pyld_req_last ; +wire [`P2P_HEAD_W-1:0] p2p_mem_desc_req_head , p2p_mem_pyld_req_head , st0_p2p_pyld_req_head ; +wire [`P2P_DATA_W-1:0] p2p_mem_desc_req_data , p2p_mem_pyld_req_data , st0_p2p_pyld_req_data ; +wire p2p_mem_desc_req_ready, p2p_mem_pyld_req_ready, st0_p2p_pyld_req_ready; + +/* --------Next mem payload{begin}-------- */ +wire nxt_valid; +wire [7:0] nxt_qnum ; +/* --------Next mem payload{end}-------- */ + +/* --------dropped queue{begin}-------- */ +wire dropped_wen ; +wire [`QUEUE_NUM_LOG-1:0] dropped_qnum; +/* --------dropped queue{end}-------- */ + +/* --------p2p mem payload store{begin}-------- */ +wire st_pyld_req_valid ; +wire st_pyld_req_last ; +wire [`MSG_BLEN_WIDTH-1:0] st_pyld_req_blen ; +wire [8 -1:0] st_pyld_req_qnum ; +wire [`P2P_DATA_W -1:0] st_pyld_req_data ; +wire st_pyld_req_ready ; +/* --------p2p mem payload store{begin}-------- */ + +/* --------allocated buffer address{begin}-------- */ +wire pbuf_alloc_valid ; +wire pbuf_alloc_last ; +wire [`BUF_ADDR_WIDTH-1:0] pbuf_alloc_buf_addr; +wire [8 -1:0] pbuf_alloc_qnum ; +wire pbuf_alloc_ready ; +/* --------allocated buffer address{end}-------- */ + +/* --------Info from queue struct{begin}-------- */ +wire qstruct_valid ; +wire qstruct_last ; +wire [`QUEUE_CONTEXT_WIDTH-1:0] qstruct_head_ctx ; +wire [`QUEUE_DESC_WIDTH -1:0] qstruct_head_desc; +wire [`BUF_ADDR_WIDTH -1:0] qstruct_buf_addr ; +wire qstruct_ready ; +/* --------Info from queue struct{end}-------- */ + +/* --------Info from queue struct{begin}-------- */ +wire st_qstruct_valid ; +wire st_qstruct_last ; +wire [`QUEUE_CONTEXT_WIDTH-1:0] st_qstruct_head_ctx ; +wire [`QUEUE_DESC_WIDTH -1:0] st_qstruct_head_desc; +wire [`BUF_ADDR_WIDTH -1:0] st_qstruct_buf_addr ; +wire st_qstruct_ready ; +/* --------Info from queue struct{end}-------- */ + +/* --------Ctrl Info to pyld_buf{begin}-------- */ +wire pbuf_free_valid ; +wire pbuf_free_last ; +wire [`P2P_DHEAD_W -1:0] pbuf_free_head ; +wire [1:0] pbuf_free_buf_offset; +wire [`BUF_ADDR_WIDTH-1:0] pbuf_free_buf_addr ; +wire pbuf_free_ready ; +/* --------Ctrl Info to pyld_buf{begin}-------- */ + +/* --------Ctrl Info to pyld_buf{begin}-------- */ +wire st_pbuf_free_valid ; +wire st_pbuf_free_last ; +wire [`P2P_DHEAD_W -1:0] st_pbuf_free_head ; +wire [1:0] st_pbuf_free_buf_offset; +wire [`BUF_ADDR_WIDTH-1:0] st_pbuf_free_buf_addr ; +wire st_pbuf_free_ready ; +/* --------Ctrl Info to pyld_buf{begin}-------- */ + +/* --------p2p mem payload out{begin}-------- */ +wire ft_pyld_req_valid; +wire ft_pyld_req_last ; +wire [`P2P_DHEAD_W -1:0] ft_pyld_req_head ; +wire [`P2P_DATA_W -1:0] ft_pyld_req_data ; +wire ft_pyld_req_ready; +/* --------p2p mem payload out{end}-------- */ + +wire prp_init_end, pb_init_end; + + +`ifdef PCIEI_APB_DBG +/* -------APB reated signal{begin}------- */ +wire [`SRAM_RW_DATA_W*2-1:0] pbuf_rw_data; +wire [(2*`QUEUE_NUM+1)*`SRAM_RW_DATA_W-1:0] qstruct_rw_data; + +wire [`TGT_TOP_SIGNAL_W-1:0] dbg_signal_tgt_top; +wire [`TGT_RECV_SIGNAL_W-1:0] dbg_signal_tgt_recv; +wire [`TGT_QSTRUCT_SIGNAL_W-1:0] dbg_signal_tgt_qstruct; +wire [`TGT_PBUF_SIGNAL_W-1:0] dbg_signal_tgt_pbuf; +wire [`TGT_SEND_SIGNAL_W-1:0] dbg_signal_tgt_send; +/* -------APB reated signal{end}------- */ +`endif + +//------------------------------------------------------------------------------------------------------------------- + +`ifdef PCIEI_APB_DBG +/* -------APB reated signal{begin}------- */ +assign {pbuf_rw_data, qstruct_rw_data} = rw_data; + +// Debug bus for p2p ini +assign dbg_bus = {dbg_signal_tgt_top, dbg_signal_tgt_recv, + dbg_signal_tgt_qstruct, dbg_signal_tgt_pbuf, dbg_signal_tgt_send} >> {dbg_sel, 5'd0}; + +// Debug signal for p2p ini top +assign dbg_signal_tgt_top = { // 2703 + + st_reg_p2p_mem_req_valid, st_reg_p2p_mem_req_last , st_reg_p2p_mem_req_head , st_reg_p2p_mem_req_data , st_reg_p2p_mem_req_ready, // 387 + mem_addr, nxt_chnl_sel, // 40 + + p2p_mem_desc_req_valid, p2p_mem_pyld_req_valid, st0_p2p_pyld_req_valid, + p2p_mem_desc_req_last , p2p_mem_pyld_req_last , st0_p2p_pyld_req_last , + p2p_mem_desc_req_head , p2p_mem_pyld_req_head , st0_p2p_pyld_req_head , + p2p_mem_desc_req_data , p2p_mem_pyld_req_data , st0_p2p_pyld_req_data , + p2p_mem_desc_req_ready, p2p_mem_pyld_req_ready, st0_p2p_pyld_req_ready, // 1161 + + nxt_valid, nxt_qnum , // 9 + dropped_wen , dropped_qnum, // 5 + st_pyld_req_valid, st_pyld_req_last , st_pyld_req_blen , st_pyld_req_qnum, st_pyld_req_data, st_pyld_req_ready, // 283 + pbuf_alloc_valid, pbuf_alloc_last, pbuf_alloc_buf_addr, pbuf_alloc_qnum, pbuf_alloc_ready, // 21 + qstruct_valid, qstruct_last, qstruct_head_ctx, qstruct_head_desc, qstruct_buf_addr, qstruct_ready, // 157 + st_qstruct_valid, st_qstruct_last, st_qstruct_head_ctx, st_qstruct_head_desc, st_qstruct_buf_addr, st_qstruct_ready, // 157 + pbuf_free_valid, pbuf_free_last, pbuf_free_head, pbuf_free_buf_offset, pbuf_free_buf_addr, pbuf_free_ready, // 79 + st_pbuf_free_valid, st_pbuf_free_last, st_pbuf_free_head, st_pbuf_free_buf_offset, st_pbuf_free_buf_addr, st_pbuf_free_ready, // 79 + + ft_pyld_req_valid, ft_pyld_req_last , ft_pyld_req_head , ft_pyld_req_data , ft_pyld_req_ready, // 323 + prp_init_end, pb_init_end // 2 +}; +/* -------APB reated signal{end}------- */ +`endif + +/* -------- Related to demux {begin}-------- */ +st_reg #( + .TUSER_WIDTH ( `P2P_HEAD_W ), + .TDATA_WIDTH ( `P2P_DATA_W ), + .MODE ( 1 ) +) st_reg2demux ( + .clk ( clk ), // i, 1 + .rst_n ( rst_n ), // i, 1 + + /* -------input axis-like interface{begin}------- */ + /* p2p_req head + * | 127 | 126:64 | 63:32 | 31:13 | 12:0 | + * | is_wr | Reserved | addr | Reserved | byte_len | + */ + .axis_tvalid ( p2p_mem_req_valid ), // i, 1 + .axis_tlast ( p2p_mem_req_last ), // i, 1 + .axis_tuser ( p2p_mem_req_head ), // i, TUSER_WIDTH + .axis_tdata ( p2p_mem_req_data ), // i, TDATA_WIDTH + .axis_tready ( p2p_mem_req_ready ), // o, 1 + /* -------input axis-like interface{end}------- */ + + /* -------output in_reg inteface{begin}------- */ + /* p2p_req head + * | 127 | 126:64 | 63:32 | 31:13 | 12:0 | + * | is_wr | Reserved | addr | Reserved | byte_len | + */ + .axis_reg_tvalid ( st_reg_p2p_mem_req_valid ), // o, 1 // read valid from input register + .axis_reg_tlast ( st_reg_p2p_mem_req_last ), // o, 1 + .axis_reg_tuser ( st_reg_p2p_mem_req_head ), // o, TUSER_WIDTH + .axis_reg_tdata ( st_reg_p2p_mem_req_data ), // o, TDATA_WIDTH + .axis_reg_tready ( st_reg_p2p_mem_req_ready ) // i, 1 + /* -------output in_reg inteface{end}------- */ +); + +assign mem_addr = p2p_mem_req_head[63:32]; +assign nxt_chnl_sel = p2p_mem_req_valid ? (mem_addr[13:12] == 2'b11) : 0; +st_demux #( + .CHNL_NUM ( 2 ), // number of slave signals to arbit + .CHNL_NUM_LOG ( 1 ), + .TUSER_WIDTH ( `P2P_HEAD_W ), + .TDATA_WIDTH ( `P2P_DATA_W ) +) tgt_mem_demux ( + .clk ( clk ), // i, 1 + .rst_n ( rst_n ), // i, 1 + + .nxt_chnl_vld ( p2p_mem_req_valid ), // i, 1 + .nxt_chnl_sel ( nxt_chnl_sel ), // i, 8 + + /* --------P2P Memory Access Channel In{begin}-------- */ + /* p2p_req head + * | 127 | 126:64 | 63:32 | 31:13 | 12:0 | + * | is_wr | Reserved | addr | Reserved | byte_len | + */ + .s_axis_demux_valid ( st_reg_p2p_mem_req_valid ), // i, 1 + .s_axis_demux_last ( st_reg_p2p_mem_req_last ), // i, 1 + .s_axis_demux_head ( st_reg_p2p_mem_req_head ), // i, `P2P_HEAD_W + .s_axis_demux_data ( st_reg_p2p_mem_req_data ), // i, `P2P_DATA_W + .s_axis_demux_ready ( st_reg_p2p_mem_req_ready ), // o, 1 + /* --------P2P Memory Access Channel In{end}-------- */ + + /* --------P2P Memory Access Channel Out{begin}-------- */ + /* p2p_req head + * | 127 | 126:64 | 63:32 | 31:13 | 12:0 | + * | is_wr | Reserved | addr | Reserved | byte_len | + */ + .m_axis_demux_valid ( {p2p_mem_desc_req_valid, p2p_mem_pyld_req_valid} ), // o, 2 * 1 + .m_axis_demux_last ( {p2p_mem_desc_req_last , p2p_mem_pyld_req_last } ), // o, 2 * 1 + .m_axis_demux_head ( {p2p_mem_desc_req_head , p2p_mem_pyld_req_head } ), // o, 2 * `P2P_HEAD_W + .m_axis_demux_data ( {p2p_mem_desc_req_data , p2p_mem_pyld_req_data } ), // o, 2 * `P2P_DATA_W + .m_axis_demux_ready ( {p2p_mem_desc_req_ready, p2p_mem_pyld_req_ready} ) // i, 2 * 1 + /* --------P2P Memory Access Channel Out{end}-------- */ +); +/* -------- Related to demux {end}-------- */ + +/* -------- Payload receive procedure{begin}-------- */ +st_reg #( + .TUSER_WIDTH ( `P2P_HEAD_W ), + .TDATA_WIDTH ( `P2P_DATA_W ), + .MODE ( 1 ) +) st_reg0 ( + .clk ( clk ), // i, 1 + .rst_n ( rst_n ), // i, 1 + + /* -------input axis-like interface{begin}------- */ + /* p2p_req head + * | 127 | 126:64 | 63:32 | 31:13 | 12:0 | + * | is_wr | Reserved | addr | Reserved | byte_len | + */ + .axis_tvalid ( p2p_mem_pyld_req_valid ), // i, 1 + .axis_tlast ( p2p_mem_pyld_req_last ), // i, 1 + .axis_tuser ( p2p_mem_pyld_req_head ), // i, TUSER_WIDTH + .axis_tdata ( p2p_mem_pyld_req_data ), // i, TDATA_WIDTH + .axis_tready ( p2p_mem_pyld_req_ready ), // o, 1 + /* -------input axis-like interface{end}------- */ + + /* -------output in_reg inteface{begin}------- */ + /* p2p_req head + * | 127 | 126:64 | 63:32 | 31:13 | 12:0 | + * | is_wr | Reserved | addr | Reserved | byte_len | + */ + .axis_reg_tvalid ( st0_p2p_pyld_req_valid ), // o, 1 // read valid from input register + .axis_reg_tlast ( st0_p2p_pyld_req_last ), // o, 1 + .axis_reg_tuser ( st0_p2p_pyld_req_head ), // o, TUSER_WIDTH + .axis_reg_tdata ( st0_p2p_pyld_req_data ), // o, TDATA_WIDTH + .axis_reg_tready ( st0_p2p_pyld_req_ready ) // i, 1 + /* -------output in_reg inteface{end}------- */ +); + +assign nxt_valid = p2p_mem_pyld_req_valid; +assign nxt_qnum = (p2p_mem_pyld_req_head[63:32] >> 14) & 4'hf; +tgt_pyld_recv_proc #( + +) tgt_pyld_recv_proc ( + + .clk ( clk ), // i, 1 + .rst_n ( rst_n ), // i, 1 + .init_end ( prp_init_end ), // o, 1 + + /* --------Next mem payload{begin}-------- */ + .nxt_vaild ( nxt_valid ), // i, 1 + .nxt_qnum ( nxt_qnum ), // i, 8 + /* --------Next mem payload{end}-------- */ + + /* --------p2p mem payload in{begin}-------- */ + /* p2p_req head + * | 127 | 126:64 | 63:32 | 31:13 | 12:0 | + * | is_wr | Reserved | addr | Reserved | byte_len | + */ + .st0_p2p_pyld_req_valid ( st0_p2p_pyld_req_valid ), // i, 1 + .st0_p2p_pyld_req_last ( st0_p2p_pyld_req_last ), // i, 1 + .st0_p2p_pyld_req_head ( st0_p2p_pyld_req_head ), // i, `P2P_HEAD_W + .st0_p2p_pyld_req_data ( st0_p2p_pyld_req_data ), // i, `P2P_DATA_W + .st0_p2p_pyld_req_ready ( st0_p2p_pyld_req_ready ), // o, 1 + /* --------p2p mem payload in{end}-------- */ + + /* --------p2p mem payload out{begin}-------- */ + .st_pyld_req_valid ( st_pyld_req_valid ), // o, 1 + .st_pyld_req_last ( st_pyld_req_last ), // o, 1 + .st_pyld_req_blen ( st_pyld_req_blen ), // o, `MSG_BLEN_WIDTH + .st_pyld_req_qnum ( st_pyld_req_qnum ), // o, 8 + .st_pyld_req_data ( st_pyld_req_data ), // o, `P2P_DATA_W + .st_pyld_req_ready ( st_pyld_req_ready ), // i, 1 + /* --------p2p mem payload out{end}-------- */ + + /* --------dropped queue{begin}-------- */ + .dropped_wen ( dropped_wen ), // i, 1 + .dropped_qnum ( dropped_qnum ), // i, `QUEUE_NUM_LOG + .dropped_data ( 1'd0 ) // i, 1; we assume no dropped desc + /* --------dropped queue{end}-------- */ + +`ifdef PCIEI_APB_DBG + /* -------APB reated signal{begin}------- */ + ,.dbg_signal ( dbg_signal_tgt_recv ) // o, `TGT_RECV_SIGNAL_W + /* -------APB reated signal{end}------- */ +`endif +); +/* -------- Payload receive procedure{end}-------- */ + +tgt_queue_struct #( + +) tgt_queue_struct ( + + .clk ( clk ), // i, 1 + .rst_n ( rst_n ), // i, 1 + + /* --------P2P Configuration Channel{begin}-------- */ + /* p2p_req head + * | 127 | 126:64 | 63:32 | 31:13 | 12:0 | + * | is_wr | Reserved | addr | Reserved | byte_len | + */ + .p2p_cfg_req_valid ( p2p_cfg_req_valid ), // i, 1 + .p2p_cfg_req_last ( p2p_cfg_req_last ), // i, 1 + .p2p_cfg_req_data ( p2p_cfg_req_data ), // i, `P2P_DATA_W + .p2p_cfg_req_head ( p2p_cfg_req_head ), // i, `P2P_HEAD_W + .p2p_cfg_req_ready ( p2p_cfg_req_ready ), // o, 1 + + // .p2p_cfg_rrsp_valid ( p2p_cfg_rrsp_valid ), // o, 1 + // .p2p_cfg_rrsp_last ( p2p_cfg_rrsp_last ), // o, 1 + // .p2p_cfg_rrsp_data ( p2p_cfg_rrsp_data ), // o, `P2P_DATA_W + // .p2p_cfg_rrsp_ready ( p2p_cfg_rrsp_ready ), // i, 1 + /* --------P2P Configuration Channel{end}-------- */ + + /* --------p2p mem descriptor in{begin}-------- */ + .p2p_mem_desc_req_valid ( p2p_mem_desc_req_valid ), // i, 1 + .p2p_mem_desc_req_last ( p2p_mem_desc_req_last ), // i, 1 + .p2p_mem_desc_req_data ( p2p_mem_desc_req_data ), // i, `P2P_DATA_W + .p2p_mem_desc_req_head ( p2p_mem_desc_req_head ), // i, `P2P_HEAD_W + .p2p_mem_desc_req_ready ( p2p_mem_desc_req_ready ), // o, 1 + /* --------p2p mem descriptor in{end}-------- */ + + /* --------allocated buffer address{begin}-------- */ + .pbuf_alloc_valid ( pbuf_alloc_valid ), // i, 1 + .pbuf_alloc_last ( pbuf_alloc_last ), // i, 1 + .pbuf_alloc_buf_addr ( pbuf_alloc_buf_addr ), // i, 32 + .pbuf_alloc_qnum ( pbuf_alloc_qnum ), // i, 8 + .pbuf_alloc_ready ( pbuf_alloc_ready ), // o, 1 + /* --------allocated buffer address{end}-------- */ + + /* --------dropped queue{begin}-------- */ + .dropped_wen ( dropped_wen ), // o, 1 + .dropped_qnum ( dropped_qnum ), // o, `QUEUE_NUM_LOG + /* --------dropped queue{end}-------- */ + + /* --------queue struct output for send processing{begin}-------- */ + /* st_qstruct_head_ctx : qcontext of prepared queue + * st_qstruct_head_desc: payload descriptor + * st_qstruct_buf_addr : allocated buffer base address in P2P pyld_buf, + * this is an array. A valid addr outputs when valid + * and ready assert at the same time. + * st_qstruct_last : assert when the last st_qstruct_buf_addr is asserted + */ + .st_qstruct_valid ( qstruct_valid ), // o, 1 + .st_qstruct_last ( qstruct_last ), // o, 1 + .st_qstruct_head_ctx ( qstruct_head_ctx ), // o, `QUEUE_CONTEXT_WIDTH + .st_qstruct_head_desc ( qstruct_head_desc ), // o, `QUEUE_DESC_WIDTH + .st_qstruct_buf_addr ( qstruct_buf_addr ), // o, `BUF_ADDR_WIDTH + .st_qstruct_ready ( qstruct_ready ) // i, 1 + /* --------queue struct output for send processing{end}-------- */ + +`ifdef PCIEI_APB_DBG + /* -------APB reated signal{begin}------- */ + ,.rw_data ( qstruct_rw_data ) // i, (2*`QUEUE_NUM+1)*`SRAM_RW_DATA_W + ,.dbg_signal ( dbg_signal_tgt_qstruct ) // o, `TGT_QSTRUCT_SIGNAL_W + /* -------APB reated signal{end}------- */ +`endif +); + +st_reg #( + .TUSER_WIDTH ( `P2P_DHEAD_W ), + .TDATA_WIDTH ( `BUF_ADDR_WIDTH + 2 ), + .MODE ( 1 ) +) st_pbuf ( + .clk ( clk ), // i, 1 + .rst_n ( rst_n ), // i, 1 + + /* -------input axis-like interface{begin}------- */ + .axis_tvalid ( pbuf_free_valid ), // i, 1 + .axis_tlast ( pbuf_free_last ), // i, 1 + .axis_tuser ( pbuf_free_head ), // i, TUSER_WIDTH + .axis_tdata ( {pbuf_free_buf_addr, pbuf_free_buf_offset} ), // i, TDATA_WIDTH + .axis_tready ( pbuf_free_ready ), // o, 1 + /* -------input axis-like interface{end}------- */ + + /* -------output in_reg inteface{begin}------- */ + .axis_reg_tvalid ( st_pbuf_free_valid ), // o, 1 // read valid from input register + .axis_reg_tlast ( st_pbuf_free_last ), // o, 1 + .axis_reg_tuser ( st_pbuf_free_head ), // o, TUSER_WIDTH + .axis_reg_tdata ( {st_pbuf_free_buf_addr, st_pbuf_free_buf_offset} ), // o, TDATA_WIDTH + .axis_reg_tready ( st_pbuf_free_ready ) // i, 1 + /* -------output in_reg inteface{end}------- */ +); + +tgt_pyld_buf #( + +) tgt_pyld_buf ( + + .clk ( clk ), // i, 1 + .rst_n ( rst_n ), // i, 1 + .init_end ( pb_init_end ), // o, 1 + + /* --------allocated buffer address{begin}-------- */ + .pbuf_alloc_valid ( pbuf_alloc_valid ), // o, 1 + .pbuf_alloc_last ( pbuf_alloc_last ), // o, 1 + .pbuf_alloc_buf_addr ( pbuf_alloc_buf_addr ), // o, 32 + .pbuf_alloc_qnum ( pbuf_alloc_qnum ), // o, 8 + .pbuf_alloc_ready ( pbuf_alloc_ready ), // i, 1 + /* --------allocated buffer address{end}-------- */ + + /* --------p2p mem payload in{begin}-------- */ + .st_pyld_req_valid ( st_pyld_req_valid ), // i, 1 + .st_pyld_req_last ( st_pyld_req_last ), // i, 1 + .st_pyld_req_blen ( st_pyld_req_blen ), // i, `MSG_BLEN_WIDTH + .st_pyld_req_qnum ( st_pyld_req_qnum ), // i, 8 + .st_pyld_req_data ( st_pyld_req_data ), // i, `P2P_DATA_W + .st_pyld_req_ready ( st_pyld_req_ready ), // o, 1 + /* --------p2p mem payload in{end}-------- */ + + /* --------Ctrl Info to pyld_buf{begin}-------- */ + .pbuf_free_valid ( st_pbuf_free_valid ), // i, 1 + .pbuf_free_last ( st_pbuf_free_last ), // i, 1 + .pbuf_free_head ( st_pbuf_free_head ), // i, `P2P_DHEAD_W + .pbuf_free_buf_offset ( st_pbuf_free_buf_offset ), // i, 2 + .pbuf_free_buf_addr ( st_pbuf_free_buf_addr ), // i, `BUF_ADDR_WIDTH + .pbuf_free_ready ( st_pbuf_free_ready ), // o, 1 + /* --------Ctrl Info to pyld_buf{begin}-------- */ + + /* --------p2p mem payload out{begin}-------- */ + .ft_pyld_req_valid ( ft_pyld_req_valid ), // o, 1 + .ft_pyld_req_last ( ft_pyld_req_last ), // o, 1 + .ft_pyld_req_head ( ft_pyld_req_head ), // o, `P2P_DHEAD_W + .ft_pyld_req_data ( ft_pyld_req_data ), // o, `P2P_DATA_W + .ft_pyld_req_ready ( ft_pyld_req_ready ) // i, 1 + /* --------p2p mem payload out{end}-------- */ + +`ifdef PCIEI_APB_DBG + /* -------APB reated signal{begin}------- */ + ,.rw_data ( pbuf_rw_data ) // i, `SRAM_RW_DATA_W*2 + ,.dbg_signal ( dbg_signal_tgt_pbuf ) // o, `TGT_PBUF_SIGNAL_W + /* -------APB reated signal{end}------- */ +`endif + +); + +st_reg #( + .TUSER_WIDTH ( `QUEUE_CONTEXT_WIDTH + `QUEUE_DESC_WIDTH ), + .TDATA_WIDTH ( `BUF_ADDR_WIDTH ), + .MODE ( 1 ) +) st_qstruct ( + .clk ( clk ), // i, 1 + .rst_n ( rst_n ), // i, 1 + + /* -------input axis-like interface{begin}------- */ + .axis_tvalid ( qstruct_valid ), // i, 1 + .axis_tlast ( qstruct_last ), // i, 1 + .axis_tuser ( {qstruct_head_ctx, qstruct_head_desc} ), // i, TUSER_WIDTH + .axis_tdata ( qstruct_buf_addr ), // i, TDATA_WIDTH + .axis_tready ( qstruct_ready ), // o, 1 + /* -------input axis-like interface{end}------- */ + + /* -------output in_reg inteface{begin}------- */ + .axis_reg_tvalid ( st_qstruct_valid ), // o, 1 // read valid from input register + .axis_reg_tlast ( st_qstruct_last ), // o, 1 + .axis_reg_tuser ( {st_qstruct_head_ctx, st_qstruct_head_desc} ), // o, TUSER_WIDTH + .axis_reg_tdata ( st_qstruct_buf_addr ), // o, TDATA_WIDTH + .axis_reg_tready ( st_qstruct_ready ) // i, 1 + /* -------output in_reg inteface{end}------- */ +); + +tgt_pyld_send_proc #( + +) tgt_pyld_send_proc ( + + .clk ( clk ), // i, 1 + .rst_n ( rst_n ), // i, 1 + + /* --------Info from queue struct{begin}-------- */ + /* qstruct_head_ctx : qcontext of prepared queue + * qstruct_head_desc: payload descriptor + * qstruct_buf_addr : allocated buffer base address in P2P pyld_buf, + * this is an array. A valid addr outputs when valid + * and ready assert at the same time. + * qstruct_last : assert when the last qstruct_buf_addr is asserted + */ + .qstruct_valid ( st_qstruct_valid ), // i, 1 + .qstruct_last ( st_qstruct_last ), // i, 1 + .qstruct_head_ctx ( st_qstruct_head_ctx ), // i, `QUEUE_CONTEXT_WIDTH + .qstruct_head_desc ( st_qstruct_head_desc ), // i, `QUEUE_DESC_WIDTH + .qstruct_buf_addr ( st_qstruct_buf_addr ), // i, `BUF_ADDR_WIDTH + .qstruct_ready ( st_qstruct_ready ), // o, 1 + /* --------Info from queue struct{end}-------- */ + + /* --------Ctrl Info to pyld_buf{begin}-------- */ + .pbuf_free_valid ( pbuf_free_valid ), // o, 1 + .pbuf_free_last ( pbuf_free_last ), // o, 1 + .pbuf_free_head ( pbuf_free_head ), // o, `P2P_DHEAD_W + .pbuf_free_buf_offset ( pbuf_free_buf_offset ), // o, 2 + .pbuf_free_buf_addr ( pbuf_free_buf_addr ), // o, `BUF_ADDR_WIDTH + .pbuf_free_ready ( pbuf_free_ready ), // i, 1 + /* --------Ctrl Info to pyld_buf{begin}-------- */ + + /* --------p2p mem payload out{begin}-------- */ + .ft_pyld_req_valid ( ft_pyld_req_valid ), // i, 1 + .ft_pyld_req_last ( ft_pyld_req_last ), // i, 1 + .ft_pyld_req_head ( ft_pyld_req_head ), // i, `P2P_DHEAD_W + .ft_pyld_req_data ( ft_pyld_req_data ), // i, `P2P_DATA_W + .ft_pyld_req_ready ( ft_pyld_req_ready ), // o, 1 + /* --------p2p mem payload out{end}-------- */ + + /* --------p2p forward down channel{begin}-------- */ + /* *_head, valid only in first beat of a packet + * | Reserved |dst_dev| src_dev | Reserved | Byte length | + * | 63:- | 47:40 | 39:32 | 31:16 | 15:0 | + */ + .st_p2p_down_valid ( p2p_down_valid ), // o, 1 + .st_p2p_down_last ( p2p_down_last ), // o, 1 + .st_p2p_down_data ( p2p_down_data ), // o, `P2P_DATA_W + .st_p2p_down_head ( p2p_down_head ), // o, `P2P_DHEAD_W + .st_p2p_down_ready ( p2p_down_ready ) // i, 1 + /* --------p2p forward down channel{end}-------- */ + +`ifdef PCIEI_APB_DBG + /* -------APB reated signal{begin}------- */ + ,.dbg_signal ( dbg_signal_tgt_send ) // o, `TGT_SEND_SIGNAL_W + /* -------APB reated signal{end}------- */ +`endif +); + +assign init_end = prp_init_end & pb_init_end; + +endmodule // p2p_target diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/P2P/tgt_desc_queue.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/P2P/tgt_desc_queue.v new file mode 100644 index 0000000000000000000000000000000000000000..d0f99eb51b34f54ff4813d1155fc40b007578e1e --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/P2P/tgt_desc_queue.v @@ -0,0 +1,504 @@ +`timescale 1ns / 100ps +//************************************************************************* +// > File : tgt_desc_queue.v +// > Author : Kangning +// > Date : 2022-08-31 +// > Note : descriptor queue, includes descriptor queue && pbuf allocated +// > address. +//************************************************************************* + +module tgt_desc_queue #( + +) ( + + input wire clk , // i, 1 + input wire rst_n, // i, 1 + + /* --------p2p mem descriptor in{begin}-------- */ + /* p2p_req head. We just write mem descriptor space, and the byte_len is 8 byte aligned + * | 127 | 126:64 | 63:32 | 31:13 | 12:0 | + * | is_wr | Reserved | addr | Reserved | byte_len | + */ + input wire p2p_mem_desc_req_valid, // i, 1 + input wire p2p_mem_desc_req_last , // i, 1 + input wire [`P2P_HEAD_W-1:0] p2p_mem_desc_req_head , // i, `P2P_HEAD_W + input wire [`P2P_DATA_W-1:0] p2p_mem_desc_req_data , // i, `P2P_DATA_W + output wire p2p_mem_desc_req_ready, // o, 1 + /* --------p2p mem descriptor in{end}-------- */ + + /* --------allocated buffer address{begin}-------- */ + input wire pbuf_alloc_valid , // i, 1 + input wire pbuf_alloc_last , // i, 1 + input wire [`BUF_ADDR_WIDTH-1:0] pbuf_alloc_buf_addr, // i, `BUF_ADDR_WIDTH + input wire [8 -1:0] pbuf_alloc_qnum , // i, 8 + output wire pbuf_alloc_ready , // o, 1 ; assume it always asserts + /* --------allocated buffer address{end}-------- */ + + /* --------dropped queue{begin}-------- */ + output wire dropped_wen , // o, 1 + output wire [`QUEUE_NUM_LOG-1:0] dropped_qnum, // o, `QUEUE_NUM_LOG + /* --------dropped queue{end}-------- */ + + /* --------queue struct output for send processing{begin}-------- */ + /* desc_out_head_desc: payload descriptor + * desc_out_buf_addr : allocated buffer base address in P2P pyld_buf, + * this is an array. A valid addr outputs when valid + * and ready assert at the same time. + * desc_out_last : assert when the last desc_out_buf_addr is asserted + */ + output wire desc_out_valid , // o, 1 + output wire desc_out_last , // o, 1 + output reg [`QUEUE_DESC_WIDTH-1:0] desc_out_head_desc, // o, `QUEUE_DESC_WIDTH + output wire [`QUEUE_NUM_LOG -1:0] desc_out_head_qnum, // o, `QUEUE_NUM_LOG + output wire [`BUF_ADDR_WIDTH -1:0] desc_out_buf_addr , // o, `BUF_ADDR_WIDTH + input wire desc_out_ready // i, 1 + /* --------queue struct output for send processing{end}-------- */ + +`ifdef PCIEI_APB_DBG + /* -------APB reated signal{begin}------- */ + ,input wire [2*`QUEUE_NUM*`SRAM_RW_DATA_W-1:0] rw_data // i, 2*`QUEUE_NUM*`SRAM_RW_DATA_W + ,output wire [`DESC_QUEUE_SIGNAL_W-1:0] dbg_signal // o, `DESC_QUEUE_SIGNAL_W + /* -------APB reated signal{end}------- */ +`endif +); + +/* --------p2p mem descriptor write{begin}-------- */ +wire [`QUEUE_DESC_WIDTH-1:0] desc_data; +wire [`QUEUE_NUM_LOG -1:0] desc_qnum; +/* --------p2p mem descriptor write{end}-------- */ + +/* --------queue descriptor{begin}-------- */ +wire qdesc_0_wen [`QUEUE_NUM-1:0]; +wire [`QUEUE_DESC_WIDTH-1:0] qdesc_0_din [`QUEUE_NUM-1:0]; +wire qdesc_0_ren [`QUEUE_NUM-1:0]; +wire [`QUEUE_DESC_WIDTH-1:0] qdesc_0_dout [`QUEUE_NUM-1:0]; +wire qdesc_0_full [`QUEUE_NUM-1:0]; +wire qdesc_0_empty[`QUEUE_NUM-1:0]; + +// queue receive matching +wire [`MSG_BLEN_WIDTH-1:0] byte_len[`QUEUE_NUM-1:0]; +reg [`MSG_BLEN_WIDTH:0] byte_cnt[`QUEUE_NUM-1:0]; // This reg may exceed the length of byte_len +wire is_recved[`QUEUE_NUM-1:0]; + +wire qdesc_1_wen [`QUEUE_NUM-1:0]; +wire [`QUEUE_DESC_WIDTH-1:0] qdesc_1_din [`QUEUE_NUM-1:0]; +wire qdesc_1_ren [`QUEUE_NUM-1:0]; +wire [`QUEUE_DESC_WIDTH-1:0] qdesc_1_dout [`QUEUE_NUM-1:0]; +wire qdesc_1_full [`QUEUE_NUM-1:0]; +wire qdesc_1_empty[`QUEUE_NUM-1:0]; + +wire alloced_buf_wen [`QUEUE_NUM-1:0]; +wire [`BUF_ADDR_WIDTH-1:0] alloced_buf_din [`QUEUE_NUM-1:0]; +wire alloced_buf_ren [`QUEUE_NUM-1:0]; +wire [`BUF_ADDR_WIDTH-1:0] alloced_buf_dout [`QUEUE_NUM-1:0]; +wire alloced_buf_full [`QUEUE_NUM-1:0]; +wire alloced_buf_empty[`QUEUE_NUM-1:0]; + +wire is_que_rdy[`QUEUE_NUM-1:0]; + +wire is_match_succ; +wire [`QUEUE_NUM_LOG-1:0] match_qnum; // Used only when is_nxt_desc_que_out +reg [`QUEUE_NUM_LOG-1:0] match_qnum_reg; // It is used only in DESC_QUE_OUT state +reg [`QUEUE_NUM_LOG-1:0] pri_chnl; // The prior selected channel +/* --------queue descriptor{end}-------- */ + +/* --------queue struct output FSM{begin}-------- */ +localparam IDLE = 2'b01, + DESC_QUE_OUT = 2'b10; + +reg [1:0] nxt_state; +reg [1:0] cur_state; + +wire is_idle, is_desc_que_out; +wire is_nxt_desc_que_out; + +reg [`MSG_BLEN_WIDTH-1:0] desc_out_byte_left; +/* --------queue struct output FSM{end}-------- */ + +`ifdef PCIEI_APB_DBG +/* -------APB reated signal{begin}------- */ +wire [2*`QUEUE_NUM-1:0] desc_que_rtsel, alloced_buf_rtsel; +wire [2*`QUEUE_NUM-1:0] desc_que_wtsel, alloced_buf_wtsel; +wire [2*`QUEUE_NUM-1:0] desc_que_ptsel, alloced_buf_ptsel; +wire [1*`QUEUE_NUM-1:0] desc_que_vg , alloced_buf_vg ; +wire [1*`QUEUE_NUM-1:0] desc_que_vs , alloced_buf_vs ; +wire [2-1:0] qcontext_rtsel; +wire [2-1:0] qcontext_wtsel; +wire [2-1:0] qcontext_ptsel; +wire [1-1:0] qcontext_vg ; +wire [1-1:0] qcontext_vs ; +/* -------APB reated signal{end}------- */ +`endif + +//--------------------------------------------------------------------------------------------------------------------------- + +`ifdef PCIEI_APB_DBG +/* -------APB reated signal{begin}------- */ +assign { + desc_que_rtsel , + desc_que_wtsel , + desc_que_ptsel , + desc_que_vg , + desc_que_vs , + alloced_buf_rtsel, + alloced_buf_wtsel, + alloced_buf_ptsel, + alloced_buf_vg , + alloced_buf_vs +} = rw_data; + +assign dbg_signal = { // 6312 + + desc_data, desc_qnum, // 84 + + qdesc_0_wen [0 ], qdesc_0_wen [1 ], qdesc_0_wen [2 ], qdesc_0_wen [3 ], + qdesc_0_wen [4 ], qdesc_0_wen [5 ], qdesc_0_wen [6 ], qdesc_0_wen [7 ], + qdesc_0_wen [8 ], qdesc_0_wen [9 ], qdesc_0_wen [10], qdesc_0_wen [11], + qdesc_0_wen [12], qdesc_0_wen [13], qdesc_0_wen [14], qdesc_0_wen [15], + qdesc_0_din [0 ], qdesc_0_din [1 ], qdesc_0_din [2 ], qdesc_0_din [3 ], + qdesc_0_din [4 ], qdesc_0_din [5 ], qdesc_0_din [6 ], qdesc_0_din [7 ], + qdesc_0_din [8 ], qdesc_0_din [9 ], qdesc_0_din [10], qdesc_0_din [11], + qdesc_0_din [12], qdesc_0_din [13], qdesc_0_din [14], qdesc_0_din [15], + qdesc_0_ren [0 ], qdesc_0_ren [1 ], qdesc_0_ren [2 ], qdesc_0_ren [3 ], + qdesc_0_ren [4 ], qdesc_0_ren [5 ], qdesc_0_ren [6 ], qdesc_0_ren [7 ], + qdesc_0_ren [8 ], qdesc_0_ren [9 ], qdesc_0_ren [10], qdesc_0_ren [11], + qdesc_0_ren [12], qdesc_0_ren [13], qdesc_0_ren [14], qdesc_0_ren [15], + qdesc_0_dout [0 ], qdesc_0_dout [1 ], qdesc_0_dout [2 ], qdesc_0_dout [3 ], + qdesc_0_dout [4 ], qdesc_0_dout [5 ], qdesc_0_dout [6 ], qdesc_0_dout [7 ], + qdesc_0_dout [8 ], qdesc_0_dout [9 ], qdesc_0_dout [10], qdesc_0_dout [11], + qdesc_0_dout [12], qdesc_0_dout [13], qdesc_0_dout [14], qdesc_0_dout [15], + qdesc_0_full [0 ], qdesc_0_full [1 ], qdesc_0_full [2 ], qdesc_0_full [3 ], + qdesc_0_full [4 ], qdesc_0_full [5 ], qdesc_0_full [6 ], qdesc_0_full [7 ], + qdesc_0_full [8 ], qdesc_0_full [9 ], qdesc_0_full [10], qdesc_0_full [11], + qdesc_0_full [12], qdesc_0_full [13], qdesc_0_full [14], qdesc_0_full [15], + qdesc_0_empty[0 ], qdesc_0_empty[1 ], qdesc_0_empty[2 ], qdesc_0_empty[3 ], + qdesc_0_empty[4 ], qdesc_0_empty[5 ], qdesc_0_empty[6 ], qdesc_0_empty[7 ], + qdesc_0_empty[8 ], qdesc_0_empty[9 ], qdesc_0_empty[10], qdesc_0_empty[11], + qdesc_0_empty[12], qdesc_0_empty[13], qdesc_0_empty[14], qdesc_0_empty[15], // 2624 + + byte_len[0 ], byte_len[1 ], byte_len[2 ], byte_len[3 ], + byte_len[4 ], byte_len[5 ], byte_len[6 ], byte_len[7 ], + byte_len[8 ], byte_len[9 ], byte_len[10], byte_len[11], + byte_len[12], byte_len[13], byte_len[14], byte_len[15], + byte_cnt[0 ], byte_cnt[1 ], byte_cnt[2 ], byte_cnt[3 ], + byte_cnt[4 ], byte_cnt[5 ], byte_cnt[6 ], byte_cnt[7 ], + byte_cnt[8 ], byte_cnt[9 ], byte_cnt[10], byte_cnt[11], + byte_cnt[12], byte_cnt[13], byte_cnt[14], byte_cnt[15], // 528 + + is_recved[0], is_recved[0], is_recved[0], is_recved[0], + is_recved[0], is_recved[0], is_recved[0], is_recved[0], + is_recved[0], is_recved[0], is_recved[0], is_recved[0], + is_recved[0], is_recved[0], is_recved[0], is_recved[0], // 16 + + qdesc_1_wen [0 ], qdesc_1_wen [1 ], qdesc_1_wen [2 ], qdesc_1_wen [3 ], + qdesc_1_wen [4 ], qdesc_1_wen [5 ], qdesc_1_wen [6 ], qdesc_1_wen [7 ], + qdesc_1_wen [8 ], qdesc_1_wen [9 ], qdesc_1_wen [10], qdesc_1_wen [11], + qdesc_1_wen [12], qdesc_1_wen [13], qdesc_1_wen [14], qdesc_1_wen [15], + qdesc_1_din [0 ], qdesc_1_din [1 ], qdesc_1_din [2 ], qdesc_1_din [3 ], + qdesc_1_din [4 ], qdesc_1_din [5 ], qdesc_1_din [6 ], qdesc_1_din [7 ], + qdesc_1_din [8 ], qdesc_1_din [9 ], qdesc_1_din [10], qdesc_1_din [11], + qdesc_1_din [12], qdesc_1_din [13], qdesc_1_din [14], qdesc_1_din [15], + qdesc_1_ren [0 ], qdesc_1_ren [1 ], qdesc_1_ren [2 ], qdesc_1_ren [3 ], + qdesc_1_ren [4 ], qdesc_1_ren [5 ], qdesc_1_ren [6 ], qdesc_1_ren [7 ], + qdesc_1_ren [8 ], qdesc_1_ren [9 ], qdesc_1_ren [10], qdesc_1_ren [11], + qdesc_1_ren [12], qdesc_1_ren [13], qdesc_1_ren [14], qdesc_1_ren [15], + qdesc_1_dout [0 ], qdesc_1_dout [1 ], qdesc_1_dout [2 ], qdesc_1_dout [3 ], + qdesc_1_dout [4 ], qdesc_1_dout [5 ], qdesc_1_dout [6 ], qdesc_1_dout [7 ], + qdesc_1_dout [8 ], qdesc_1_dout [9 ], qdesc_1_dout [10], qdesc_1_dout [11], + qdesc_1_dout [12], qdesc_1_dout [13], qdesc_1_dout [14], qdesc_1_dout [15], + qdesc_1_full [0 ], qdesc_1_full [1 ], qdesc_1_full [2 ], qdesc_1_full [3 ], + qdesc_1_full [4 ], qdesc_1_full [5 ], qdesc_1_full [6 ], qdesc_1_full [7 ], + qdesc_1_full [8 ], qdesc_1_full [9 ], qdesc_1_full [10], qdesc_1_full [11], + qdesc_1_full [12], qdesc_1_full [13], qdesc_1_full [14], qdesc_1_full [15], + qdesc_1_empty[0 ], qdesc_1_empty[1 ], qdesc_1_empty[2 ], qdesc_1_empty[3 ], + qdesc_1_empty[4 ], qdesc_1_empty[5 ], qdesc_1_empty[6 ], qdesc_1_empty[7 ], + qdesc_1_empty[8 ], qdesc_1_empty[9 ], qdesc_1_empty[10], qdesc_1_empty[11], + qdesc_1_empty[12], qdesc_1_empty[13], qdesc_1_empty[14], qdesc_1_empty[15], // 2624 + + alloced_buf_wen [0 ], alloced_buf_wen [1 ], alloced_buf_wen [2 ], alloced_buf_wen [3 ], + alloced_buf_wen [4 ], alloced_buf_wen [5 ], alloced_buf_wen [6 ], alloced_buf_wen [7 ], + alloced_buf_wen [8 ], alloced_buf_wen [9 ], alloced_buf_wen [10], alloced_buf_wen [11], + alloced_buf_wen [12], alloced_buf_wen [13], alloced_buf_wen [14], alloced_buf_wen [15], + alloced_buf_din [0 ], alloced_buf_din [1 ], alloced_buf_din [2 ], alloced_buf_din [3 ], + alloced_buf_din [4 ], alloced_buf_din [5 ], alloced_buf_din [6 ], alloced_buf_din [7 ], + alloced_buf_din [8 ], alloced_buf_din [9 ], alloced_buf_din [10], alloced_buf_din [11], + alloced_buf_din [12], alloced_buf_din [13], alloced_buf_din [14], alloced_buf_din [15], + alloced_buf_ren [0 ], alloced_buf_ren [1 ], alloced_buf_ren [2 ], alloced_buf_ren [3 ], + alloced_buf_ren [4 ], alloced_buf_ren [5 ], alloced_buf_ren [6 ], alloced_buf_ren [7 ], + alloced_buf_ren [8 ], alloced_buf_ren [9 ], alloced_buf_ren [10], alloced_buf_ren [11], + alloced_buf_ren [12], alloced_buf_ren [13], alloced_buf_ren [14], alloced_buf_ren [15], + alloced_buf_dout [0 ], alloced_buf_dout [1 ], alloced_buf_dout [2 ], alloced_buf_dout [3 ], + alloced_buf_dout [4 ], alloced_buf_dout [5 ], alloced_buf_dout [6 ], alloced_buf_dout [7 ], + alloced_buf_dout [8 ], alloced_buf_dout [9 ], alloced_buf_dout [10], alloced_buf_dout [11], + alloced_buf_dout [12], alloced_buf_dout [13], alloced_buf_dout [14], alloced_buf_dout [15], + alloced_buf_full [0 ], alloced_buf_full [1 ], alloced_buf_full [2 ], alloced_buf_full [3 ], + alloced_buf_full [4 ], alloced_buf_full [5 ], alloced_buf_full [6 ], alloced_buf_full [7 ], + alloced_buf_full [8 ], alloced_buf_full [9 ], alloced_buf_full [10], alloced_buf_full [11], + alloced_buf_full [12], alloced_buf_full [13], alloced_buf_full [14], alloced_buf_full [15], + alloced_buf_empty[0 ], alloced_buf_empty[1 ], alloced_buf_empty[2 ], alloced_buf_empty[3 ], + alloced_buf_empty[4 ], alloced_buf_empty[5 ], alloced_buf_empty[6 ], alloced_buf_empty[7 ], + alloced_buf_empty[8 ], alloced_buf_empty[9 ], alloced_buf_empty[10], alloced_buf_empty[11], + alloced_buf_empty[12], alloced_buf_empty[13], alloced_buf_empty[14], alloced_buf_empty[15], // 384 + + is_que_rdy[0 ], is_que_rdy[1 ], is_que_rdy[2 ], is_que_rdy[3 ], + is_que_rdy[4 ], is_que_rdy[5 ], is_que_rdy[6 ], is_que_rdy[7 ], + is_que_rdy[8 ], is_que_rdy[9 ], is_que_rdy[10], is_que_rdy[11], + is_que_rdy[12], is_que_rdy[13], is_que_rdy[14], is_que_rdy[15], // 16 + + is_match_succ, match_qnum, match_qnum_reg, pri_chnl, // 13 + + nxt_state, cur_state, // 4 + is_idle, is_desc_que_out, is_nxt_desc_que_out, // 3 + desc_out_byte_left // 16 +}; +/* -------APB reated signal{end}------- */ +`endif + +/* --------queue descriptor{begin}-------- */ +assign p2p_mem_desc_req_ready = !qdesc_0_full[desc_qnum]; + +genvar i; +generate +for (i = 0; i < `QUEUE_NUM; i = i + 1) begin: DESC_QUE // 16 pass + + // -------------------Input descriptor queue------------------------------- // + pcieifc_sync_fifo #( + .DSIZE ( `QUEUE_DESC_WIDTH ), // 80 + .ASIZE ( `PBUF_NUM_LOG - 1 ) // 9 + ) desc_que_0 ( + .clk ( clk ), + .rst_n ( rst_n ), + .clr ( 1'd0 ), + + .wen ( qdesc_0_wen [i] ), + .din ( qdesc_0_din [i] ), + + .ren ( qdesc_0_ren [i] ), + .dout ( qdesc_0_dout[i] ), + + .full ( qdesc_0_full [i] ), + .empty ( qdesc_0_empty[i] ) + + `ifdef PCIEI_APB_DBG + ,.rtsel ( desc_que_rtsel[(i+1)*2-1:i*2] ) // i, 2 + ,.wtsel ( desc_que_wtsel[(i+1)*2-1:i*2] ) // i, 2 + ,.ptsel ( desc_que_ptsel[(i+1)*2-1:i*2] ) // i, 2 + ,.vg ( desc_que_vg [i] ) // i, 1 + ,.vs ( desc_que_vs [i] ) // i, 1 + `endif + ); + assign qdesc_0_wen[i] = (desc_qnum == i) & p2p_mem_desc_req_valid & p2p_mem_desc_req_ready; + assign qdesc_0_din[i] = qdesc_0_wen[i] ? desc_data : 0; + + assign qdesc_0_ren[i] = is_recved[i] & !qdesc_1_full[i]; + // ---------------------------------------------------------- // + + // ---------------------receive matching-------------------------------- // + assign byte_len[i] = (qdesc_0_dout[i] >> 32) & 16'hFFFF; + always @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + byte_cnt[i] <= `TD 0; + end + else if ((byte_cnt[i] >= byte_len[i]) & (!qdesc_1_full[i])) begin + byte_cnt[i] <= `TD 0; + end + else if (pbuf_alloc_valid & pbuf_alloc_ready) begin + byte_cnt[i] <= `TD byte_cnt[i] + ((pbuf_alloc_qnum == i) ? `PBUF_BLOCK_SZ : 0); + end + end + + assign is_recved[i] = (byte_cnt[i] >= byte_len[i]) & !qdesc_0_empty[i]; + // --------------------------------------------------------------------- // + + // ---------------------Input descriptor queue {begin}-------------------------- // + pcieifc_sync_fifo #( + .DSIZE ( `QUEUE_DESC_WIDTH ), // 80 + .ASIZE ( `PBUF_NUM_LOG - 1 ) // 9 + ) desc_que_1 ( + .clk ( clk ), + .rst_n ( rst_n ), + .clr ( 1'd0 ), + + .wen ( qdesc_1_wen [i] ), + .din ( qdesc_1_din [i] ), + + .ren ( qdesc_1_ren [i] ), + .dout ( qdesc_1_dout[i] ), + + .full ( qdesc_1_full [i] ), + .empty ( qdesc_1_empty[i] ) + + `ifdef PCIEI_APB_DBG + ,.rtsel ( desc_que_rtsel[(i+1)*2-1:i*2] ) // i, 2 + ,.wtsel ( desc_que_wtsel[(i+1)*2-1:i*2] ) // i, 2 + ,.ptsel ( desc_que_ptsel[(i+1)*2-1:i*2] ) // i, 2 + ,.vg ( desc_que_vg [i] ) // i, 1 + ,.vs ( desc_que_vs [i] ) // i, 1 + `endif + ); + assign qdesc_1_wen[i] = qdesc_0_ren[i]; + assign qdesc_1_din[i] = qdesc_0_dout[i]; + + assign qdesc_1_ren[i] = (match_qnum == i) & is_nxt_desc_que_out; + // ---------------------Input descriptor queue {end}-------------------------- // + + pcieifc_sync_fifo #( + .DSIZE ( `BUF_ADDR_WIDTH ), // 10 + .ASIZE ( `PBUF_NUM_LOG ) // 10 + ) alloced_buf_list ( + .clk ( clk ), + .rst_n ( rst_n ), + .clr ( 1'd0 ), + + .wen ( alloced_buf_wen[i] ), + .din ( alloced_buf_din[i] ), + + .ren ( alloced_buf_ren [i] ), + .dout ( alloced_buf_dout[i] ), + + .full ( alloced_buf_full [i] ), + .empty ( alloced_buf_empty[i] ) + + `ifdef PCIEI_APB_DBG + ,.rtsel ( alloced_buf_rtsel[(i+1)*2-1:i*2] ) // i, 2 + ,.wtsel ( alloced_buf_wtsel[(i+1)*2-1:i*2] ) // i, 2 + ,.ptsel ( alloced_buf_ptsel[(i+1)*2-1:i*2] ) // i, 2 + ,.vg ( alloced_buf_vg [i] ) // i, 1 + ,.vs ( alloced_buf_vs [i] ) // i, 1 + `endif + ); + assign alloced_buf_wen[i] = (pbuf_alloc_qnum == i) & pbuf_alloc_valid; + assign alloced_buf_din[i] = pbuf_alloc_buf_addr; + + assign alloced_buf_ren[i] = (match_qnum_reg == i) & is_desc_que_out & desc_out_valid & desc_out_ready; + + assign is_que_rdy[i] = !qdesc_1_empty[i] & !alloced_buf_empty[i]; + +end +endgenerate + +// -> input descriptor queue +assign desc_data = p2p_mem_desc_req_data[127:0]; +assign desc_qnum = (p2p_mem_desc_req_head[63:32] & 18'h3FFFF) >> 14; + +// input descriptor -> output descriptor queue +assign pbuf_alloc_ready = !alloced_buf_full[pbuf_alloc_qnum] & !qdesc_1_full[pbuf_alloc_qnum]; + +// output descriptor queue -> +generate +if (`QUEUE_NUM_LOG == 4) begin: QUEUE16 // 16 queue + assign is_match_succ = is_que_rdy[0 ] | is_que_rdy[1 ] | is_que_rdy[2 ] | is_que_rdy[3 ] | + is_que_rdy[4 ] | is_que_rdy[5 ] | is_que_rdy[6 ] | is_que_rdy[7 ] | + is_que_rdy[8 ] | is_que_rdy[9 ] | is_que_rdy[10] | is_que_rdy[11] | + is_que_rdy[12] | is_que_rdy[13] | is_que_rdy[14] | is_que_rdy[15]; + + assign match_qnum = is_que_rdy[(pri_chnl ) & 4'hF] ? (pri_chnl ) & 4'hF: is_que_rdy[(pri_chnl+4'd1 ) & 4'hF] ? (pri_chnl+4'd1 ) & 4'hF: + is_que_rdy[(pri_chnl+4'd2 ) & 4'hF] ? (pri_chnl+4'd2 ) & 4'hF: is_que_rdy[(pri_chnl+4'd3 ) & 4'hF] ? (pri_chnl+4'd3 ) & 4'hF: + is_que_rdy[(pri_chnl+4'd4 ) & 4'hF] ? (pri_chnl+4'd4 ) & 4'hF: is_que_rdy[(pri_chnl+4'd5 ) & 4'hF] ? (pri_chnl+4'd5 ) & 4'hF: + is_que_rdy[(pri_chnl+4'd6 ) & 4'hF] ? (pri_chnl+4'd6 ) & 4'hF: is_que_rdy[(pri_chnl+4'd7 ) & 4'hF] ? (pri_chnl+4'd7 ) & 4'hF: + is_que_rdy[(pri_chnl+4'd8 ) & 4'hF] ? (pri_chnl+4'd8 ) & 4'hF: is_que_rdy[(pri_chnl+4'd9 ) & 4'hF] ? (pri_chnl+4'd9 ) & 4'hF: + is_que_rdy[(pri_chnl+4'd10) & 4'hF] ? (pri_chnl+4'd10) & 4'hF: is_que_rdy[(pri_chnl+4'd11) & 4'hF] ? (pri_chnl+4'd11) & 4'hF: + is_que_rdy[(pri_chnl+4'd12) & 4'hF] ? (pri_chnl+4'd12) & 4'hF: is_que_rdy[(pri_chnl+4'd13) & 4'hF] ? (pri_chnl+4'd13) & 4'hF: + is_que_rdy[(pri_chnl+4'd14) & 4'hF] ? (pri_chnl+4'd14) & 4'hF: is_que_rdy[(pri_chnl+4'd15) & 4'hF] ? (pri_chnl+4'd15) & 4'hF: 0; +end +endgenerate +always @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + match_qnum_reg <= `TD 0; + end + else if (is_match_succ & is_nxt_desc_que_out) begin + match_qnum_reg <= `TD match_qnum; + end +end + +always @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + pri_chnl <= `TD 0; + end + else if (is_match_succ & is_nxt_desc_que_out) begin + pri_chnl <= `TD pri_chnl + 1; + end +end + +// dropped queue +assign dropped_wen = p2p_mem_desc_req_valid & p2p_mem_desc_req_ready; +assign dropped_qnum = (p2p_mem_desc_req_head[63:32] & 18'h3FFFF) >> 14; +/* --------queue descriptor{end}-------- */ + +/* --------descriptor queue output FSM{begin}-------- */ +/******************** Stage 1: State Register **********************/ +assign is_idle = (cur_state == IDLE ); +assign is_desc_que_out = (cur_state == DESC_QUE_OUT); +assign is_nxt_desc_que_out = (is_idle || (is_desc_que_out & desc_out_valid & desc_out_ready & desc_out_last)) & is_match_succ; + +always @(posedge clk, negedge rst_n) begin + if(~rst_n) + cur_state <= `TD IDLE; + else + cur_state <= `TD nxt_state; +end + +/******************** Stage 2: State Transition **********************/ +always @(*) begin + case(cur_state) + IDLE: begin + if (is_match_succ) begin + nxt_state = DESC_QUE_OUT; + end + else begin + nxt_state = IDLE; + end + end + DESC_QUE_OUT: begin + if (desc_out_valid & desc_out_ready & desc_out_last) begin + if (is_match_succ) begin + nxt_state = DESC_QUE_OUT; + end + else begin + nxt_state = IDLE; + end + end + else begin + nxt_state = DESC_QUE_OUT; + end + end + default: begin + nxt_state = IDLE; + end + endcase +end +/******************** Stage 3: Output **********************/ +always @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + desc_out_byte_left <= `TD 0; + end + else if (is_nxt_desc_que_out) begin + desc_out_byte_left <= `TD (qdesc_1_dout[match_qnum] >> 32) & 16'hFFFF; + end + else if (is_desc_que_out & desc_out_valid & desc_out_ready & desc_out_last) begin + desc_out_byte_left <= `TD 0; + end + else if (is_desc_que_out & desc_out_valid & desc_out_ready) begin + desc_out_byte_left <= `TD desc_out_byte_left - `PBUF_BLOCK_SZ; + end +end + +always @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + desc_out_head_desc <= `TD 0; + end + else if (is_nxt_desc_que_out) begin + desc_out_head_desc <= `TD qdesc_1_dout[match_qnum]; + end + else if (is_idle) begin + desc_out_head_desc <= `TD 0; + end +end + +assign desc_out_valid = is_desc_que_out & !alloced_buf_empty[match_qnum_reg]; +assign desc_out_last = desc_out_valid ? (desc_out_byte_left <= `PBUF_BLOCK_SZ) : 1'd0; +assign desc_out_head_qnum = match_qnum_reg; +assign desc_out_buf_addr = alloced_buf_dout[match_qnum_reg]; +/* --------descriptor queue output FSM{begin}-------- */ + +endmodule diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/P2P/tgt_pyld_buf.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/P2P/tgt_pyld_buf.v new file mode 100644 index 0000000000000000000000000000000000000000..264598cdb17d7928ba30d7b5a5be3f4d435d8520 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/P2P/tgt_pyld_buf.v @@ -0,0 +1,264 @@ +`timescale 1ns / 100ps +//************************************************************************* +// > File : tgt_pyld_buf.v +// > Author : Kangning +// > Date : 2022-08-29 +// > Note : Payload buffer for payload temp store +//************************************************************************* + +module tgt_pyld_buf #( + +) ( + + input wire clk , // i, 1 + input wire rst_n , // i, 1 + output reg init_end, // o, 1 + + /* --------allocated buffer address{begin}-------- */ + output wire pbuf_alloc_valid , // o, 1 + output wire pbuf_alloc_last , // o, 1 + output wire [`BUF_ADDR_WIDTH-1:0] pbuf_alloc_buf_addr, // o, `BUF_ADDR_WIDTH + output wire [8 -1:0] pbuf_alloc_qnum , // o, 8 + input wire pbuf_alloc_ready , // i, 1 ; assume it always asserts + /* --------allocated buffer address{end}-------- */ + + /* --------p2p mem payload in{begin}-------- */ + input wire st_pyld_req_valid, // i, 1 + input wire st_pyld_req_last , // i, 1 + input wire [`MSG_BLEN_WIDTH-1:0] st_pyld_req_blen , // i, `MSG_BLEN_WIDTH + input wire [8 -1:0] st_pyld_req_qnum , // i, 8 + input wire [`P2P_DATA_W -1:0] st_pyld_req_data , // i, `P2P_DATA_W + output wire st_pyld_req_ready, // o, 1 + /* --------p2p mem payload in{end}-------- */ + + /* --------Ctrl Info to pyld_buf{begin}-------- */ + input wire pbuf_free_valid , // i, 1 + input wire pbuf_free_last , // i, 1 + input wire [`P2P_DHEAD_W -1:0] pbuf_free_head , // i, `P2P_DHEAD_W + input wire [1 :0] pbuf_free_buf_offset, // i, 2 + input wire [`BUF_ADDR_WIDTH-1:0] pbuf_free_buf_addr , // i, `BUF_ADDR_WIDTH + output wire pbuf_free_ready , // o, 1 + /* --------Ctrl Info to pyld_buf{begin}-------- */ + + /* --------p2p mem payload out{begin}-------- */ + output reg ft_pyld_req_valid, // o, 1 + output reg ft_pyld_req_last , // o, 1 + output reg [`P2P_DHEAD_W -1:0] ft_pyld_req_head , // o, `P2P_DHEAD_W + output wire [`P2P_DATA_W -1:0] ft_pyld_req_data , // o, `P2P_DATA_W + input wire ft_pyld_req_ready // i, 1 + /* --------p2p mem payload out{end}-------- */ + +`ifdef PCIEI_APB_DBG + /* -------APB reated signal{begin}------- */ + ,input wire [`SRAM_RW_DATA_W*2-1:0] rw_data // i, `SRAM_RW_DATA_W*2 + ,output wire [`TGT_PBUF_SIGNAL_W-1:0] dbg_signal // o, `TGT_PBUF_SIGNAL_W + /* -------APB reated signal{end}------- */ +`endif +); + +localparam BEAT_BYTE_NUM = `P2P_DATA_W / 8; // 32 +localparam P2P_DATA_W_LOG = $clog2(`P2P_DATA_W); // 8 +localparam PBUF_BLOCK_WIDTH = `PBUF_SZ_LOG + 3 - P2P_DATA_W_LOG; // 2 +localparam PBUF_ADDR_WIDTH = `PBUF_NUM_LOG + PBUF_BLOCK_WIDTH; // 12 + +/* --------free buffer list{begin}-------- */ +wire free_buf_wen , free_buf_ren ; +wire [`PBUF_NUM_LOG-1:0] free_buf_din , free_buf_dout ; +wire free_buf_full, free_buf_empty; + +wire init_stat; +reg [`PBUF_NUM_LOG-1:0] init_din; +/* --------free buffer list{end}-------- */ + +/* --------payload buffer{begin}-------- */ +wire is_st_last_pbuf_beat; // the last beat to store payload buffer block + +wire pbuf_st_wen ; +wire [PBUF_ADDR_WIDTH-1:0] pbuf_st_addr; +wire [`P2P_DATA_W -1:0] pbuf_st_din ; + +wire pbuf_ft_ren ; +wire [PBUF_ADDR_WIDTH-1:0] pbuf_ft_addr; +wire [`P2P_DATA_W -1:0] pbuf_ft_dout; + +reg [PBUF_BLOCK_WIDTH-1:0] st_offset ; +/* --------payload buffer{end}-------- */ + +`ifdef PCIEI_APB_DBG +/* -------APB reated signal{begin}------- */ +wire [1:0] pyld_buf_rtsel, free_buf_fifo_rtsel; +wire [1:0] pyld_buf_wtsel, free_buf_fifo_wtsel; +wire [1:0] pyld_buf_ptsel, free_buf_fifo_ptsel; +wire pyld_buf_vg , free_buf_fifo_vg ; +wire pyld_buf_vs , free_buf_fifo_vs ; +/* -------APB reated signal{end}------- */ +`endif + +//--------------------------------------------------------------------------------------------------------------------------- + +`ifdef PCIEI_APB_DBG +/* -------APB reated signal{begin}------- */ +assign { + free_buf_fifo_rtsel, + free_buf_fifo_wtsel, + free_buf_fifo_ptsel, + free_buf_fifo_vg , + free_buf_fifo_vs , + pyld_buf_rtsel , + pyld_buf_wtsel , + pyld_buf_ptsel , + pyld_buf_vg , + pyld_buf_vs +} = rw_data; + +assign dbg_signal = { // 576 + + free_buf_wen , free_buf_ren , + free_buf_din , free_buf_dout , + free_buf_full, free_buf_empty, // 24 + + init_stat, init_din, // 11 + is_st_last_pbuf_beat, // 1 + + pbuf_st_wen, pbuf_st_addr, pbuf_st_din , // 269 + pbuf_ft_ren, pbuf_ft_addr, pbuf_ft_dout, // 269 + + st_offset // 2 +}; +/* -------APB reated signal{end}------- */ +`endif + +/* --------free buffer list{begin}-------- */ +pcieifc_sync_fifo #( + .DSIZE ( `PBUF_NUM_LOG ), // 10 + .ASIZE ( `PBUF_NUM_LOG ) // 10 +) free_buf_fifo ( + .clk ( clk ), + .rst_n ( rst_n ), + .clr ( 1'd0 ), + + .wen ( free_buf_wen ), + .din ( free_buf_din ), + + .ren ( free_buf_ren ), + .dout ( free_buf_dout ), + + .full ( free_buf_full ), + .empty ( free_buf_empty ) + +`ifdef PCIEI_APB_DBG + ,.rtsel ( free_buf_fifo_rtsel ) // i, 2 + ,.wtsel ( free_buf_fifo_wtsel ) // i, 2 + ,.ptsel ( free_buf_fifo_ptsel ) // i, 2 + ,.vg ( free_buf_fifo_vg ) // i, 1 + ,.vs ( free_buf_fifo_vs ) // i, 1 +`endif +); + +assign free_buf_wen = init_stat ? 1 : (pbuf_free_valid & pbuf_free_ready & (pbuf_free_last || pbuf_free_buf_offset == 3)); +assign free_buf_din = init_stat ? init_din : pbuf_free_buf_addr; + +assign free_buf_ren = pbuf_alloc_valid & pbuf_alloc_ready; + +// Initialization related signal +assign init_stat = (~init_end & rst_n); +always @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + init_din <= `TD 0; + end + else if (~init_end) begin + init_din <= `TD init_din + 1; + end +end +always @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + init_end <= `TD 0; + end + else if (init_din == 10'd1023) begin + init_end <= `TD 1; + end +end +/* --------free buffer list{end}-------- */ + +/* --------payload buffer{begin}-------- */ +assign is_st_last_pbuf_beat = (st_offset == 3) || st_pyld_req_last; + +//pcieifc_sd_sram #( +// .DATAWIDTH ( `P2P_DATA_W ), // Memory data word width, 256 +// .ADDRWIDTH ( PBUF_ADDR_WIDTH ) // Number of mem address bits, 12 +//) pyld_buf ( +// .clk ( clk ), // i, 1 +// .rst_n ( rst_n ), // i, 1 + +// .wea ( pbuf_st_wen ), // i, 1 +// .addra ( pbuf_st_addr ), // i, ADDRWIDTH +// .dina ( pbuf_st_din ), // i, DATAWIDTH + +// .reb ( pbuf_ft_ren ), // i, 1 +// .addrb ( pbuf_ft_addr ), // i, ADDRWIDTH +// .doutb ( pbuf_ft_dout ) // o, DATAWIDTH + +//`ifdef PCIEI_APB_DBG +// ,.rtsel ( pyld_buf_rtsel ) // i, 2 +// ,.wtsel ( pyld_buf_wtsel ) // i, 2 +// ,.ptsel ( pyld_buf_ptsel ) // i, 2 +// ,.vg ( pyld_buf_vg ) // i, 1 +// ,.vs ( pyld_buf_vs ) // i, 1 +//`endif +//); + +// payload buffer related signal +assign pbuf_st_wen = st_pyld_req_valid & st_pyld_req_ready; +assign pbuf_st_addr = {free_buf_dout, st_offset}; +assign pbuf_st_din = st_pyld_req_data; + +assign pbuf_ft_ren = pbuf_free_valid & pbuf_free_ready; +assign pbuf_ft_addr = {pbuf_free_buf_addr, pbuf_free_buf_offset}; + +// store address generation +always @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + st_offset <= `TD 0; + end + else if (is_st_last_pbuf_beat & (st_pyld_req_valid & st_pyld_req_ready)) begin + st_offset <= `TD 0; + end + else if (st_pyld_req_valid & st_pyld_req_ready) begin + st_offset <= `TD st_offset + 1; + end +end +/* --------payload buffer{end}-------- */ + +/* --------store related output{begin}-------- */ +assign st_pyld_req_ready = (is_st_last_pbuf_beat ? pbuf_alloc_ready : 1) & !free_buf_empty; + +assign pbuf_alloc_valid = is_st_last_pbuf_beat & st_pyld_req_valid & !free_buf_empty; +assign pbuf_alloc_last = pbuf_alloc_valid & st_pyld_req_last; +assign pbuf_alloc_buf_addr = free_buf_dout ; +assign pbuf_alloc_qnum = st_pyld_req_qnum; +/* --------store related output{end}-------- */ + +/* --------fetch related output{begin}-------- */ +assign pbuf_free_ready = !ft_pyld_req_valid | ft_pyld_req_ready; + +assign ft_pyld_req_data = pbuf_ft_dout; +always @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + ft_pyld_req_valid <= `TD 1'd0; + ft_pyld_req_last <= `TD 1'd0; + ft_pyld_req_head <= `TD {`P2P_DHEAD_W{1'd0}}; + end + else if (pbuf_free_valid & pbuf_free_ready) begin + ft_pyld_req_valid <= `TD 1'd1; + ft_pyld_req_last <= `TD pbuf_free_last; + ft_pyld_req_head <= `TD pbuf_free_head; + end + else if (ft_pyld_req_valid & ft_pyld_req_ready) begin + ft_pyld_req_valid <= `TD 1'd0; + ft_pyld_req_last <= `TD 1'd0; + ft_pyld_req_head <= `TD {`P2P_DHEAD_W{1'd0}}; + end +end +/* --------fetch related output{end}-------- */ + +endmodule diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/P2P/tgt_pyld_recv_proc.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/P2P/tgt_pyld_recv_proc.v new file mode 100644 index 0000000000000000000000000000000000000000..549e0f2d741c556ab6aa5a2bfb9a267d5d95ea77 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/P2P/tgt_pyld_recv_proc.v @@ -0,0 +1,236 @@ +`timescale 1ns / 100ps +//************************************************************************* +// > File : tgt_pyld_recv_proc.v +// > Author : Kangning +// > Date : 2022-08-25 +// > Note : target payload recvive processing +//************************************************************************* + +module tgt_pyld_recv_proc #( + +) ( + + input wire clk , // i, 1 + input wire rst_n , // i, 1 + output reg init_end, // o, 1 + + /* --------Next mem payload{begin}-------- */ + input wire nxt_vaild, // i, 1 + input wire [7:0] nxt_qnum , // i, 8 + /* --------Next mem payload{end}-------- */ + + /* --------p2p mem payload in{begin}-------- */ + /* p2p_req head + * | 127 | 126:64 | 63:32 | 31:13 | 12:0 | + * | is_wr | Reserved | addr | Reserved | byte_len | + */ + input wire st0_p2p_pyld_req_valid, // i, 1 + input wire st0_p2p_pyld_req_last , // i, 1 + input wire [`P2P_HEAD_W-1:0] st0_p2p_pyld_req_head , // i, `P2P_HEAD_W + input wire [`P2P_DATA_W-1:0] st0_p2p_pyld_req_data , // i, `P2P_DATA_W + output wire st0_p2p_pyld_req_ready, // o, 1 + /* --------p2p mem payload in{end}-------- */ + + /* --------p2p mem payload out{begin}-------- */ + output wire st_pyld_req_valid, // o, 1 + output wire st_pyld_req_last , // o, 1 + output wire [`MSG_BLEN_WIDTH-1:0] st_pyld_req_blen , // o, `MSG_BLEN_WIDTH + output wire [8 -1:0] st_pyld_req_qnum , // o, 8 + output wire [`P2P_DATA_W -1:0] st_pyld_req_data , // o, `P2P_DATA_W + input wire st_pyld_req_ready, // i, 1 + /* --------p2p mem payload out{end}-------- */ + + /* --------dropped queue{begin}-------- */ + input wire dropped_wen , // i, 1 + input wire [`QUEUE_NUM_LOG-1:0] dropped_qnum, // i, `QUEUE_NUM_LOG + input wire dropped_data // i, 1 + /* --------dropped queue{end}-------- */ + +`ifdef PCIEI_APB_DBG + /* -------APB reated signal{begin}------- */ + ,output wire [`TGT_RECV_SIGNAL_W-1:0] dbg_signal + /* -------APB reated signal{end}------- */ +`endif +); + +/* --------Dropped Register{begin}-------- */ +// reg init_end; +reg [`QUEUE_NUM_LOG-1:0] tab_index; +reg dropped_tab[`QUEUE_NUM-1:0]; +reg [7:0] pass_qnum; +/* --------Dropped Register{end}-------- */ + +/* --------Payload Receiving FSM{begin}-------- */ +localparam IDLE = 3'b001, + PYLD_DROP = 3'b010, + PYLD_PASS = 3'b100; + +reg [2:0] cur_state; +reg [2:0] nxt_state; + +wire is_idle, is_pyld_drop, is_pyld_pass; +// wire j_pyld_pass; +wire is_nxt_pass; // process next pkt in the next cycle +/* --------Payload Receiving FSM{end}-------- */ + +// ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------- // + +`ifdef PCIEI_APB_DBG +/* -------APB reated signal{begin}------- */ + +assign dbg_signal = { // 38 + + tab_index, // 4 + + dropped_tab[0 ], dropped_tab[1 ], dropped_tab[2 ], dropped_tab[3 ], + dropped_tab[4 ], dropped_tab[5 ], dropped_tab[6 ], dropped_tab[7 ], + dropped_tab[8 ], dropped_tab[9 ], dropped_tab[10], dropped_tab[11], + dropped_tab[12], dropped_tab[13], dropped_tab[14], dropped_tab[15], // 16 + + pass_qnum, cur_state, nxt_state, is_idle, is_pyld_drop, is_pyld_pass, is_nxt_pass // 18 +}; +/* -------APB reated signal{end}------- */ +`endif + +/* --------Dropped Register{begin}-------- */ + +// Init state end +always @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + init_end <= `TD 0; + end + else if (tab_index == (1'h1 << `QUEUE_NUM_LOG) - 1) begin + init_end <= `TD 1; + end +end + +// drop table index calculation +always @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + tab_index <= `TD 0; + end + else if (~init_end) begin + tab_index <= `TD tab_index + 1; + end +end + +// drop table update +integer i; +always @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + for (i = 0; i < `QUEUE_NUM; i=i+1) begin + dropped_tab[i] <= `TD 0; + end + end + else if (~init_end) begin // Initialize queue drop table + dropped_tab[tab_index] <= `TD 1; + end + else if (dropped_wen) begin + dropped_tab[dropped_qnum] <= `TD dropped_data; + end + // else if (is_nxt_pass) begin // if next state is pass (pass new payload), + // // set accordingly queue to dropped state + // dropped_tab[tab_index] <= `TD 1; + // end +end + +always @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + pass_qnum <= `TD 0; + end + else if (is_nxt_pass) begin + pass_qnum <= `TD nxt_qnum; + end +end +/* --------Dropped Register{end}-------- */ + + +/* -------Payload Receiving FSM{begin}------- */ +/******************** Stage 1: State Register **********************/ +assign is_idle = (cur_state == IDLE ); +assign is_pyld_drop = (cur_state == PYLD_DROP); +assign is_pyld_pass = (cur_state == PYLD_PASS); + +// assign j_pyld_pass = (nxt_state == IDLE) & (cur_state == PYLD_PASS); + +assign is_nxt_pass = ((cur_state == IDLE ) & (nxt_state == PYLD_PASS)) | + ((cur_state == PYLD_DROP) & (nxt_state == PYLD_PASS)) | + ((cur_state == PYLD_PASS) & (nxt_state == PYLD_PASS) & st0_p2p_pyld_req_valid & st0_p2p_pyld_req_ready & st0_p2p_pyld_req_last); + +always @(posedge clk, negedge rst_n) begin + if(~rst_n) + cur_state <= `TD IDLE; + else + cur_state <= `TD nxt_state; +end + +/******************** Stage 2: State Transition **********************/ + +always @(*) begin + case(cur_state) + IDLE: begin + if (nxt_vaild) begin + if (dropped_tab[nxt_qnum]) begin + nxt_state = PYLD_DROP; + end + else begin + nxt_state = PYLD_PASS; + end + end + else begin + nxt_state = IDLE; + end + end + PYLD_DROP: begin + if (st0_p2p_pyld_req_valid & st0_p2p_pyld_req_last) begin + if (nxt_vaild) begin + if (dropped_tab[nxt_qnum]) begin + nxt_state = PYLD_DROP; + end + else begin + nxt_state = PYLD_PASS; + end + end + else begin + nxt_state = IDLE; + end + end + else begin + nxt_state = PYLD_DROP; + end + end + PYLD_PASS: begin + if (st0_p2p_pyld_req_valid & st0_p2p_pyld_req_ready & st0_p2p_pyld_req_last) begin + if (nxt_vaild) begin + if (dropped_tab[nxt_qnum]) begin + nxt_state = PYLD_DROP; + end + else begin + nxt_state = PYLD_PASS; + end + end + else begin + nxt_state = IDLE; + end + end + else begin + nxt_state = PYLD_PASS; + end + end + default: begin + nxt_state = IDLE; + end + endcase +end +/******************** Stage 3: Output **********************/ + +assign st0_p2p_pyld_req_ready = is_pyld_drop | (is_pyld_pass & st_pyld_req_ready); + +assign st_pyld_req_valid = is_pyld_pass ? st0_p2p_pyld_req_valid : 0; +assign st_pyld_req_last = is_pyld_pass ? st0_p2p_pyld_req_last : 0; +assign st_pyld_req_blen = is_pyld_pass ? st0_p2p_pyld_req_head[`MSG_BLEN_WIDTH-1:0] : 0; +assign st_pyld_req_qnum = is_pyld_pass ? pass_qnum : 0; +assign st_pyld_req_data = is_pyld_pass ? st0_p2p_pyld_req_data : 0; +/* -------Destinstaion NIC processing FSM{end}------- */ + +endmodule diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/P2P/tgt_pyld_send_proc.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/P2P/tgt_pyld_send_proc.v new file mode 100644 index 0000000000000000000000000000000000000000..439245ac8811a9623996ee70561c684da1aba9b3 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/P2P/tgt_pyld_send_proc.v @@ -0,0 +1,247 @@ +`timescale 1ns / 100ps +//************************************************************************* +// > File : tgt_pyld_send_proc.v +// > Author : Kangning +// > Date : 2022-08-28 +// > Note : DMA P2P target payload send processing +//************************************************************************* + + +`define stat_trans if (qstruct_valid) begin \ + nxt_state = DESC_PARSE; \ + end \ + else begin \ + nxt_state = IDLE; \ + end + +module tgt_pyld_send_proc #( + +) ( + + input wire clk , // i, 1 + input wire rst_n, // i, 1 + + /* --------Info from queue struct{begin}-------- */ + /* qstruct_head_ctx : qcontext of prepared queue + * qstruct_head_desc: payload descriptor + * qstruct_buf_addr : allocated buffer base address in P2P pyld_buf, + * this is an array. A valid addr outputs when valid + * and ready assert at the same time. + * qstruct_last : assert when the last qstruct_buf_addr is asserted + */ + input wire qstruct_valid , // i, 1 + input wire qstruct_last , // i, 1 + input wire [`QUEUE_CONTEXT_WIDTH-1:0] qstruct_head_ctx , // i, `QUEUE_CONTEXT_WIDTH + input wire [`QUEUE_DESC_WIDTH -1:0] qstruct_head_desc, // i, `QUEUE_DESC_WIDTH + input wire [`BUF_ADDR_WIDTH -1:0] qstruct_buf_addr , // i, `BUF_ADDR_WIDTH + output wire qstruct_ready , // o, 1 + /* --------Info from queue struct{end}-------- */ + + /* --------Ctrl Info to pyld_buf{begin}-------- */ + /* *_head, valid only in first beat of a packet + * | Reserved |dst_dev| src_dev | Reserved | Byte length | + * | 63:- | 47:40 | 39:32 | 31:16 | 15:0 | + */ + output wire pbuf_free_valid , // o, 1 + output wire pbuf_free_last , // o, 1 + output wire [`P2P_DHEAD_W -1:0] pbuf_free_head , // o, `P2P_DHEAD_W + output wire [1:0] pbuf_free_buf_offset, // o, 2 + output wire [`BUF_ADDR_WIDTH-1:0] pbuf_free_buf_addr , // o, `BUF_ADDR_WIDTH + input wire pbuf_free_ready , // i, 1 + /* --------Ctrl Info to pyld_buf{begin}-------- */ + + /* --------p2p mem payload out{begin}-------- */ + /* *_head, valid only in first beat of a packet + * | Reserved |dst_dev| src_dev | Reserved | Byte length | + * | 63:- | 47:40 | 39:32 | 31:16 | 15:0 | + */ + input wire ft_pyld_req_valid, // i, 1 + input wire ft_pyld_req_last , // i, 1 + input wire [`P2P_DHEAD_W-1:0] ft_pyld_req_head , // i, `P2P_DHEAD_W + input wire [`P2P_DATA_W -1:0] ft_pyld_req_data , // i, `P2P_DATA_W + output wire ft_pyld_req_ready, // o, 1 + /* --------p2p mem payload out{end}-------- */ + + /* --------p2p forward down channel{begin}-------- */ + /* *_head, valid only in first beat of a packet + * | Reserved |dst_dev| src_dev | Reserved | Byte length | + * | 63:- | 47:40 | 39:32 | 31:16 | 15:0 | + */ + output wire st_p2p_down_valid, // o, 1 + output wire st_p2p_down_last , // o, 1 + output wire [`P2P_DHEAD_W-1:0] st_p2p_down_head , // o, `P2P_DHEAD_W + output wire [`P2P_DATA_W -1:0] st_p2p_down_data , // o, `P2P_DATA_W + input wire st_p2p_down_ready // i, 1 + /* --------p2p forward down channel{end}-------- */ + +`ifdef PCIEI_APB_DBG + /* -------APB reated signal{begin}------- */ + ,output wire [`TGT_SEND_SIGNAL_W-1:0] dbg_signal // o, `TGT_SEND_SIGNAL_W + /* -------APB reated signal{end}------- */ +`endif +); + +localparam BEAT_BYTE_NUM = `P2P_DATA_W / 8; + +/* --------Payload Sending FSM{begin}-------- */ +localparam IDLE = 2'b01, + DESC_PARSE = 2'b10; + +reg [1:0] cur_state; +reg [1:0] nxt_state; + +wire [47 :0] qctx_slid ; +wire [47 :0] qdesc_dlid; +wire [`MSG_BLEN_WIDTH-1:0] qdesc_blen; +wire [`DEV_NUM_WIDTH -1:0] qdesc_sdev; +wire [`DEV_NUM_WIDTH -1:0] qdesc_ddev; + +wire [1:0] last_offset; +reg [1:0] ft_offset ; + +wire is_idle, is_desc_parse; +wire is_nxt_desc_parse; +/* --------Payload Sending FSM{end}-------- */ + +/* --------p2p forward down channel{begin}-------- */ +/* *_head, valid only in first beat of a packet + * | Reserved |dst_dev| src_dev | Reserved | Byte length | + * | 63:- | 47:40 | 39:32 | 31:16 | 15:0 | + */ +wire p2p_down_valid; +wire p2p_down_last ; +wire [`P2P_DATA_W -1:0] p2p_down_data ; +wire [`P2P_DHEAD_W-1:0] p2p_down_head ; +wire p2p_down_ready; +/* --------p2p forward down channel{end}-------- */ + +//-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------// + +`ifdef PCIEI_APB_DBG +/* -------APB reated signal{begin}------- */ +assign dbg_signal = { // 462 + + cur_state, nxt_state, // 4 + qctx_slid , qdesc_dlid, qdesc_blen, qdesc_sdev, qdesc_ddev, // 128 + last_offset, ft_offset , // 4 + is_idle, is_desc_parse, is_nxt_desc_parse, // 3 + p2p_down_valid, p2p_down_last , p2p_down_data , p2p_down_head , p2p_down_ready // 323 +}; +/* -------APB reated signal{end}------- */ +`endif + +/* -------Payload Sending FSM{begin}------- */ +/******************** Stage 1: State Register **********************/ +assign is_idle = (cur_state == IDLE ); +assign is_desc_parse = (cur_state == DESC_PARSE); + +assign is_nxt_desc_parse = ((nxt_state == DESC_PARSE) & (cur_state == IDLE )) | + ((nxt_state == DESC_PARSE) & (cur_state == DESC_PARSE) & p2p_down_valid & p2p_down_ready & p2p_down_last); + +// assign last_offset = qdesc_blen[`PBUF_SZ_LOG-1:`PBUF_SZ_LOG-2] + |qdesc_blen[`PBUF_SZ_LOG-3:0] - 2'b1; +assign qctx_slid = qstruct_head_ctx[47:0]; +assign qdesc_dlid = {qstruct_head_desc[79:64], qstruct_head_desc[31:0]}; +assign qdesc_blen = qstruct_head_desc[47:32]; +assign qdesc_sdev = qstruct_head_desc[55:48]; +assign qdesc_ddev = qstruct_head_desc[63:56]; +assign last_offset = qdesc_blen[`PBUF_SZ_LOG-1:`PBUF_SZ_LOG-2] + |qdesc_blen[`PBUF_SZ_LOG-3:0] - 2'b1; + +always @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + ft_offset <= `TD 2'd0; + end + else if (is_desc_parse & pbuf_free_valid & pbuf_free_ready & pbuf_free_last) begin + ft_offset <= `TD 2'd0; + end + else if (is_desc_parse & pbuf_free_valid & pbuf_free_ready) begin + ft_offset <= `TD ft_offset + 2'd1; + end +end + +always @(posedge clk, negedge rst_n) begin + if(~rst_n) + cur_state <= `TD IDLE; + else + cur_state <= `TD nxt_state; +end +/******************** Stage 2: State Transition **********************/ + +always @(*) begin + case(cur_state) + IDLE: begin + `stat_trans + // if (qstruct_valid) begin + // nxt_state = DESC_PARSE; + // end + // else begin + // nxt_state = IDLE; + // end + end + DESC_PARSE: begin + if (p2p_down_valid & p2p_down_ready & p2p_down_last) begin + `stat_trans + end + else begin + nxt_state = DESC_PARSE; + end + end + default: begin + nxt_state = IDLE; + end + endcase +end +/******************** Stage 3: Output **********************/ + +assign qstruct_ready = ((ft_offset == 3) || pbuf_free_last) & pbuf_free_ready & is_desc_parse; + +assign pbuf_free_valid = qstruct_valid & is_desc_parse; +assign pbuf_free_last = qstruct_last & (ft_offset == last_offset); +assign pbuf_free_head = {{32-2*`DEV_NUM_WIDTH{1'd0}}, qdesc_ddev, qdesc_sdev, 16'd0, qdesc_blen}; +assign pbuf_free_buf_offset = ft_offset ; +assign pbuf_free_buf_addr = qstruct_buf_addr; + + +/* *_head, valid only in first beat of a packet + * | Reserved |dst_dev| src_dev | Reserved | Byte length | + * | 63:- | 47:40 | 39:32 | 31:16 | 15:0 | + */ +assign p2p_down_valid = ft_pyld_req_valid; +assign p2p_down_last = ft_pyld_req_last; +assign p2p_down_head = ft_pyld_req_head; +assign p2p_down_data = ft_pyld_req_data; +assign ft_pyld_req_ready = p2p_down_ready; + +st_reg #( + .TUSER_WIDTH ( `P2P_DHEAD_W ), + .TDATA_WIDTH ( `P2P_DATA_W ) +) st_reg2down ( + .clk ( clk ), // i, 1 + .rst_n ( rst_n ), // i, 1 + + /* -------input axis-like interface{begin}------- */ + /* *_head, valid only in first beat of a packet + * | Reserved |dst_dev| src_dev | Reserved | Byte length | + * | 63:- | 47:40 | 39:32 | 31:16 | 15:0 | + */ + .axis_tvalid ( p2p_down_valid ), // i, 1 + .axis_tlast ( p2p_down_last ), // i, 1 + .axis_tuser ( p2p_down_head ), // i, TUSER_WIDTH + .axis_tdata ( p2p_down_data ), // i, TDATA_WIDTH + .axis_tready ( p2p_down_ready ), // o, 1 + /* -------input axis-like interface{end}------- */ + + /* -------output in_reg inteface{begin}------- */ + /* *_head, valid only in first beat of a packet + * | Reserved |dst_dev| src_dev | Reserved | Byte length | + * | 63:- | 47:40 | 39:32 | 31:16 | 15:0 | + */ + .axis_reg_tvalid ( st_p2p_down_valid ), // o, 1 // read valid from input register + .axis_reg_tlast ( st_p2p_down_last ), // o, 1 + .axis_reg_tuser ( st_p2p_down_head ), // o, TUSER_WIDTH + .axis_reg_tdata ( st_p2p_down_data ), // o, TDATA_WIDTH + .axis_reg_tready ( st_p2p_down_ready ) // i, 1 + /* -------output in_reg inteface{end}------- */ +); +/* -------Payload Sending FSM{end}------- */ + +endmodule diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/P2P/tgt_queue_struct.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/P2P/tgt_queue_struct.v new file mode 100644 index 0000000000000000000000000000000000000000..70bf6b7c487e35326936b98b38c7dff0ab6f0f1f --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/P2P/tgt_queue_struct.v @@ -0,0 +1,293 @@ +`timescale 1ns / 100ps +//************************************************************************* +// > File : tgt_queue_struct.v +// > Author : Kangning +// > Date : 2022-08-31 +// > Note : queue structure +//************************************************************************* + +module tgt_queue_struct #( + +) ( + + input wire clk , // i, 1 + input wire rst_n , // i, 1 + // output reg init_end, // o, 1 + + /* --------P2P Configuration Channel{begin}-------- */ + /* p2p_req head. We just write configuration space, and the byte_len is fixed to 8 bytes + * | 127 | 126:64 | 63:32 | 31:13 | 12:0 | + * | is_wr | Reserved | addr | Reserved | byte_len | + */ + input wire p2p_cfg_req_valid, // i, 1 + input wire p2p_cfg_req_last , // i, 1 + input wire [`P2P_HEAD_W - 1 : 0] p2p_cfg_req_head , // i, `P2P_HEAD_W + input wire [`P2P_DATA_W - 1 : 0] p2p_cfg_req_data , // i, `P2P_DATA_W + output wire p2p_cfg_req_ready, // o, 1 + + // output wire p2p_cfg_rrsp_valid, // o, 1 + // output wire p2p_cfg_rrsp_last , // o, 1 + // output wire [`P2P_DATA_W - 1 : 0] p2p_cfg_rrsp_data , // o, `P2P_DATA_W + // input wire p2p_cfg_rrsp_ready, // i, 1 + /* --------P2P Configuration Channel{end}-------- */ + + /* --------p2p mem descriptor in{begin}-------- */ + /* p2p_req head. We just write mem descriptor space, and the byte_len is 8 byte aligned + * | 127 | 126:64 | 63:32 | 31:13 | 12:0 | + * | is_wr | Reserved | addr | Reserved | byte_len | + */ + input wire p2p_mem_desc_req_valid, // i, 1 + input wire p2p_mem_desc_req_last , // i, 1 + input wire [`P2P_HEAD_W-1:0] p2p_mem_desc_req_head , // i, `P2P_HEAD_W + input wire [`P2P_DATA_W-1:0] p2p_mem_desc_req_data , // i, `P2P_DATA_W + output wire p2p_mem_desc_req_ready, // o, 1 + /* --------p2p mem descriptor in{end}-------- */ + + /* --------allocated buffer address{begin}-------- */ + input wire pbuf_alloc_valid , // i, 1 + input wire pbuf_alloc_last , // i, 1 + input wire [`BUF_ADDR_WIDTH-1:0] pbuf_alloc_buf_addr, // i, `BUF_ADDR_WIDTH + input wire [8 -1:0] pbuf_alloc_qnum , // i, 8 + output wire pbuf_alloc_ready , // o, 1 ; assume it always asserts + /* --------allocated buffer address{end}-------- */ + + /* --------dropped queue{begin}-------- */ + output wire dropped_wen , // o, 1 + output wire [`QUEUE_NUM_LOG-1:0] dropped_qnum, // o, `QUEUE_NUM_LOG + /* --------dropped queue{end}-------- */ + + /* --------queue struct output for send processing{begin}-------- */ + /* st_qstruct_head_ctx : qcontext of prepared queue + * st_qstruct_head_desc: payload descriptor + * st_qstruct_buf_addr : allocated buffer base address in P2P pyld_buf, + * this is an array. A valid addr outputs when valid + * and ready assert at the same time. + * st_qstruct_last : assert when the last st_qstruct_buf_addr is asserted + */ + output wire st_qstruct_valid , // o, 1 + output wire st_qstruct_last , // o, 1 + output wire [`QUEUE_CONTEXT_WIDTH-1:0] st_qstruct_head_ctx , // o, `QUEUE_CONTEXT_WIDTH + output wire [`QUEUE_DESC_WIDTH -1:0] st_qstruct_head_desc, // o, `QUEUE_DESC_WIDTH + output wire [`BUF_ADDR_WIDTH -1:0] st_qstruct_buf_addr , // o, `BUF_ADDR_WIDTH + input wire st_qstruct_ready // i, 1 + /* --------queue struct output for send processing{end}-------- */ + +`ifdef PCIEI_APB_DBG + /* -------APB reated signal{begin}------- */ + ,input wire [(2*`QUEUE_NUM+1)*`SRAM_RW_DATA_W-1:0] rw_data // i, (2*`QUEUE_NUM+1)*`SRAM_RW_DATA_W + ,output wire [`TGT_QSTRUCT_SIGNAL_W-1:0] dbg_signal // o, `TGT_QSTRUCT_SIGNAL_W + /* -------APB reated signal{end}------- */ +`endif +); + +localparam QCTX_BYTE_LEN_LOG = 4; // byte len of one entry of target configure bar space, in log format + +/* --------Queue context, cfg BAR space{begin}-------- */ +wire [31:0] bar_cfg_addr; + +wire qcontext_wen ; +wire [`QUEUE_NUM_LOG -1:0] qcontext_waddr; +wire [`QUEUE_CONTEXT_WIDTH-1:0] qcontext_din ; +wire qcontext_ren ; +wire [`QUEUE_NUM_LOG -1:0] qcontext_raddr; +wire [`QUEUE_CONTEXT_WIDTH-1:0] qcontext_dout ; +/* --------Queue context, cfg BAR space{end}-------- */ + +/* --------qstruct out{end}-------- */ +reg qstruct_sop; + +wire qstruct_valid ; +wire qstruct_last ; +wire [`QUEUE_DESC_WIDTH-1:0] qstruct_head_desc; +wire [`QUEUE_NUM_LOG -1:0] qstruct_head_qnum; +wire [`BUF_ADDR_WIDTH -1:0] qstruct_buf_addr ; +wire qstruct_ready ; +/* --------qstruct out{end}-------- */ + +`ifdef PCIEI_APB_DBG +/* -------APB reated signal{begin}------- */ +wire [2*`QUEUE_NUM*`SRAM_RW_DATA_W-1:0] desc_que_rw_data; +wire [2-1:0] qcontext_rtsel; +wire [2-1:0] qcontext_wtsel; +wire [2-1:0] qcontext_ptsel; +wire [1-1:0] qcontext_vg ; +wire [1-1:0] qcontext_vs ; + +wire [`QSTRUCT_TOP_SIGNAL_W-1:0] dbg_signal_qstruct_top; +wire [`DESC_QUEUE_SIGNAL_W -1:0] dbg_signal_desc_queue; +/* -------APB reated signal{end}------- */ +`endif + +//--------------------------------------------------------------------------------------------------------------------------- + +`ifdef PCIEI_APB_DBG +/* -------APB reated signal{begin}------- */ +assign { + desc_que_rw_data, + qcontext_rtsel , + qcontext_wtsel , + qcontext_ptsel , + qcontext_vg , + qcontext_vs +} = rw_data; + +assign dbg_signal = { + dbg_signal_qstruct_top, + dbg_signal_desc_queue +}; + +assign dbg_signal_qstruct_top = { // 268 + + bar_cfg_addr, // 32 + qcontext_wen, qcontext_waddr, qcontext_din, qcontext_ren, qcontext_raddr, qcontext_dout, // 138 + qstruct_sop, // 1 + qstruct_valid, qstruct_last, qstruct_head_desc, qstruct_head_qnum, qstruct_buf_addr, qstruct_ready // 97 +}; +/* -------APB reated signal{end}------- */ +`endif + +/* --------Queue context, cfg BAR space{begin}-------- */ +assign bar_cfg_addr = p2p_cfg_req_head[63:32]; + +pcieifc_sd_sram #( + .DATAWIDTH ( `QUEUE_CONTEXT_WIDTH ), // Memory data word width, 64 + .ADDRWIDTH ( `QUEUE_NUM_LOG ) // Number of mem address bits, 4 +) qcontext ( + .clk ( clk ), // i, 1 + .rst_n ( rst_n ), // i, 1 + + .wea ( qcontext_wen ), // i, 1 + .addra ( qcontext_waddr ), // i, ADDRWIDTH + .dina ( qcontext_din ), // i, DATAWIDTH + + .reb ( qcontext_ren ), // i, 1 + .addrb ( qcontext_raddr ), // i, ADDRWIDTH + .doutb ( qcontext_dout ) // o, DATAWIDTH + +`ifdef PCIEI_APB_DBG + ,.rtsel ( 2'b0 ) // i, 2 + ,.wtsel ( 2'b0 ) // i, 2 + ,.ptsel ( 2'b0 ) // i, 2 + ,.vg ( 1'b0 ) // i, 1 + ,.vs ( 1'b0 ) // i, 1 +`endif +); + +assign qcontext_wen = p2p_cfg_req_valid; +assign qcontext_waddr = (bar_cfg_addr[19:0] - `CFG_BAR_TGT_ADDR_BASE) >> QCTX_BYTE_LEN_LOG; +assign qcontext_din = p2p_cfg_req_data; + +assign qcontext_ren = qstruct_sop & qstruct_valid & qstruct_ready; +assign qcontext_raddr = qcontext_ren ? qstruct_head_qnum : 0; +/* --------Queue context, cfg BAR space{end}-------- */ + +/* --------Descriptor queue{begin}-------- */ +tgt_desc_queue #( + +) tgt_desc_queue ( + + .clk ( clk ), // i, 1 + .rst_n ( rst_n ), // i, 1 + + /* --------p2p mem descriptor in{begin}-------- */ + .p2p_mem_desc_req_valid ( p2p_mem_desc_req_valid ), // i, 1 + .p2p_mem_desc_req_last ( p2p_mem_desc_req_last ), // i, 1 + .p2p_mem_desc_req_data ( p2p_mem_desc_req_data ), // i, `P2P_DATA_W + .p2p_mem_desc_req_head ( p2p_mem_desc_req_head ), // i, `P2P_HEAD_W + .p2p_mem_desc_req_ready ( p2p_mem_desc_req_ready ), // o, 1 + /* --------p2p mem descriptor in{end}-------- */ + + /* --------allocated buffer address{begin}-------- */ + .pbuf_alloc_valid ( pbuf_alloc_valid ), // i, 1 + .pbuf_alloc_last ( pbuf_alloc_last ), // i, 1 + .pbuf_alloc_buf_addr ( pbuf_alloc_buf_addr ), // i, 32 + .pbuf_alloc_qnum ( pbuf_alloc_qnum ), // i, 8 + .pbuf_alloc_ready ( pbuf_alloc_ready ), // o, 1 + /* --------allocated buffer address{end}-------- */ + + /* --------dropped queue{begin}-------- */ + .dropped_wen ( dropped_wen ), // o, 1 + .dropped_qnum ( dropped_qnum ), // o, `QUEUE_NUM_LOG + /* --------dropped queue{end}-------- */ + + /* --------queue struct output for send processing{begin}-------- */ + /* st_qstruct_head_desc: payload descriptor + * st_qstruct_buf_addr : allocated buffer base address in P2P pyld_buf, + * this is an array. A valid addr outputs when valid + * and ready assert at the same time. + * st_qstruct_last : assert when the last st_qstruct_buf_addr is asserted + */ + .desc_out_valid ( qstruct_valid ), // o, 1 + .desc_out_last ( qstruct_last ), // o, 1 + .desc_out_head_desc ( qstruct_head_desc ), // o, `QUEUE_DESC_WIDTH + .desc_out_head_qnum ( qstruct_head_qnum ), // o, `QUEUE_NUM_LOG + .desc_out_buf_addr ( qstruct_buf_addr ), // o, `BUF_ADDR_WIDTH + .desc_out_ready ( qstruct_ready ) // i, 1 + /* --------queue struct output for send processing{end}-------- */ + +`ifdef PCIEI_APB_DBG + /* -------APB reated signal{begin}------- */ + ,.rw_data ( desc_que_rw_data ) // i, 2*`QUEUE_NUM*`SRAM_RW_DATA_W + ,.dbg_signal ( dbg_signal_desc_queue ) // o, `DESC_QUEUE_SIGNAL_W + /* -------APB reated signal{end}------- */ +`endif +); +/* --------Descriptor queue{end}-------- */ + +/* --------P2P Configuration Channel{begin}-------- */ +assign p2p_cfg_req_ready = 1; +/* --------P2P Configuration Channel{end}-------- */ + +/* --------qstruct out{begin}-------- */ +always @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + qstruct_sop <= `TD 1'd1; + end + else if (qstruct_valid & qstruct_ready & qstruct_last) begin + qstruct_sop <= `TD 1'd0; + end + else if (qstruct_valid & qstruct_ready) begin + qstruct_sop <= `TD 1'd1; + end +end + +// read queue context +assign st_qstruct_head_ctx = qcontext_dout; +st_reg #( + .TUSER_WIDTH ( `QUEUE_DESC_WIDTH ), + .TDATA_WIDTH ( `BUF_ADDR_WIDTH ) +) st_reg2send ( + .clk ( clk ), // i, 1 + .rst_n ( rst_n ), // i, 1 + + /* -------input axis-like interface{begin}------- */ + /* qstruct_head_desc: payload descriptor + * qstruct_buf_addr : allocated buffer base address in P2P pyld_buf, + * this is an array. A valid addr outputs when valid + * and ready assert at the same time. + * qstruct_last : assert when the last qstruct_buf_addr is asserted + */ + .axis_tvalid ( qstruct_valid ), // i, 1 + .axis_tlast ( qstruct_last ), // i, 1 + .axis_tuser ( qstruct_head_desc ), // i, TUSER_WIDTH + .axis_tdata ( qstruct_buf_addr ), // i, TDATA_WIDTH + .axis_tready ( qstruct_ready ), // o, 1 + /* -------input axis-like interface{end}------- */ + + /* -------output in_reg inteface{begin}------- */ + /* qstruct_head_desc: payload descriptor + * qstruct_buf_addr : allocated buffer base address in P2P pyld_buf, + * this is an array. A valid addr outputs when valid + * and ready assert at the same time. + * qstruct_last : assert when the last qstruct_buf_addr is asserted + */ + .axis_reg_tvalid ( st_qstruct_valid ), // o, 1 // read valid from input register + .axis_reg_tlast ( st_qstruct_last ), // o, 1 + .axis_reg_tuser ( st_qstruct_head_desc ), // o, TUSER_WIDTH + .axis_reg_tdata ( st_qstruct_buf_addr ), // o, TDATA_WIDTH + .axis_reg_tready ( st_qstruct_ready ) // i, 1 + /* -------output in_reg inteface{end}------- */ +); +/* --------qstruct out{end}-------- */ + +endmodule diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/PCIe_Interface.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/PCIe_Interface.v new file mode 100644 index 0000000000000000000000000000000000000000..058b8067007b55a79a4ec976d86bdc104cd24384 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/PCIe_Interface.v @@ -0,0 +1,730 @@ +`timescale 1ns / 100ps +//************************************************************************* +// > File Name : PCIe_Interface.v +// > Description : PCIe_Interface, Top modulle for DMA and PIO interface +// > Author : Kangning +// > Date : 2021-09-07 +//************************************************************************* + +module PCIe_Interface #( + parameter AXIL_DATA_WIDTH = 32 , + parameter AXIL_ADDR_WIDTH = 24 , + + // not visable from other module + parameter AXIL_STRB_WIDTH = (AXIL_DATA_WIDTH/8) +)( + + input pcie_clk , // i, 1 + input pcie_rst_n , // i, 1 + input user_clk , // i, 1 + input user_rst_n , // i, 1 + + input ist_mbist_rstn , + output ist_mbist_done , + output ist_mbist_pass , + + /* --------rdma_init_done{begin}-------- */ + input rdma_init_done, // i, 1 + /* --------rdma_init_done{end}-------- */ + + /* ------- AXI Interface{begin}------- */ + output s_axis_rq_tvalid, + output s_axis_rq_tlast , + output [`PCIEI_KEEP_W-1:0] s_axis_rq_tkeep , + output [59:0] s_axis_rq_tuser , + output [`PCIEI_DATA_W-1:0] s_axis_rq_tdata , + input [3:0] s_axis_rq_tready, + + input m_axis_rc_tvalid, + input m_axis_rc_tlast , + input [`PCIEI_KEEP_W-1:0] m_axis_rc_tkeep , + input [74:0] m_axis_rc_tuser , + input [`PCIEI_DATA_W-1:0] m_axis_rc_tdata , + output m_axis_rc_tready, + + input m_axis_cq_tvalid, + input m_axis_cq_tlast , + input [`PCIEI_KEEP_W-1:0] m_axis_cq_tkeep , + input [84:0] m_axis_cq_tuser , + input [`PCIEI_DATA_W-1:0] m_axis_cq_tdata , + output m_axis_cq_tready, + + output s_axis_cc_tvalid, + output s_axis_cc_tlast , + output [`PCIEI_KEEP_W-1:0] s_axis_cc_tkeep , + output [32:0] s_axis_cc_tuser , + output [`PCIEI_DATA_W-1:0] s_axis_cc_tdata , + input [3:0] s_axis_cc_tready, + /* ------- AXI Interface{end}------- */ + + // Configuration (CFG) Interface + input [2:0] cfg_max_payload , + input [2:0] cfg_max_read_req, + input [12:0] tl_cfg_busdev, + + // Interrupt Interface Signals + input [1:0] cfg_interrupt_msix_enable , + input [1:0] cfg_interrupt_msix_mask , + output [31:0] cfg_interrupt_msix_data , + output [63:0] cfg_interrupt_msix_address , + output cfg_interrupt_msix_int , + input cfg_interrupt_msix_sent , + input cfg_interrupt_msix_fail , + output wire [2:0] cfg_interrupt_msi_function_number, + + /* -------pio interface{begin}------- */ + output wire [63:0] pio_hcr_in_param , + output wire [31:0] pio_hcr_in_modifier , + output wire [63:0] pio_hcr_out_dma_addr , + input wire [63:0] pio_hcr_out_param , + output wire [15:0] pio_hcr_token , + input wire [ 7:0] pio_hcr_status , + output wire pio_hcr_go , + input wire pio_hcr_clear , + output wire pio_hcr_event , + output wire [ 7:0] pio_hcr_op_modifier , + output wire [11:0] pio_hcr_op , + /* -------pio interface{end}------- */ + + /* -------Reset signal{begin}------- */ + output wire cmd_rst, + /* -------Reset signal{end}------- */ + + /* --------SQ Doorbell{begin}-------- */ + output wire pio_uar_db_valid, // o, 1 + output wire [63:0] pio_uar_db_data , // o, 64 + input wire pio_uar_db_ready, // i, 1 + /* --------SQ Doorbell{end}-------- */ + + /* --------ARM CQ interface{begin}-------- */ + input wire cq_ren , // i, 1 + input wire [31:0] cq_num , // i, 32 + output wire cq_dout, // o, 1 + /* --------ARM CQ interface{end}-------- */ + + /* --------ARM EQ interface{begin}-------- */ + input wire eq_ren , // i, 1 + input wire [31:0] eq_num , // i, 31 + output wire eq_dout, // o, 1 + /* --------ARM EQ interface{end}-------- */ + + /* --------Interrupt Vector entry request & response{begin}-------- */ + input wire pio_eq_int_req_valid, // i, 1 + input wire [64 -1:0] pio_eq_int_req_num , // i, 64 + output wire pio_eq_int_req_ready, // o, 1 + + output wire pio_eq_int_rsp_valid, // o, 1 + output wire [`RDMA_MSIX_DATA_W -1:0] pio_eq_int_rsp_data , // o, 128 + input wire pio_eq_int_rsp_ready, // i, 1 + /* -------Interrupt Vector entry request & response{end}-------- */ + + /* --------Interact with Ethernet BAR{begin}------- */ + output wire [AXIL_ADDR_WIDTH-1:0] m_axi_awaddr , + output wire m_axi_awvalid, + input wire m_axi_awready, + + output wire [AXIL_DATA_WIDTH-1:0] m_axi_wdata , + output wire [AXIL_STRB_WIDTH-1:0] m_axi_wstrb , // byte select + output wire m_axi_wvalid, + input wire m_axi_wready, + + input wire m_axi_bvalid, + output wire m_axi_bready, + + output wire [AXIL_ADDR_WIDTH-1:0] m_axi_araddr , + output wire m_axi_arvalid, + input wire m_axi_arready, + + input wire [AXIL_DATA_WIDTH-1:0] m_axi_rdata , + input wire m_axi_rvalid, + output wire m_axi_rready, + /* --------Interact with Ethernet BAR{end}------- */ + + /* -------dma interface{begin}------- */ + /* dma_*_head(interact with RDMA modules), valid only in first beat of a packet + * | Reserved | address | Reserved | Byte length | + * | 127:96 | 95:32 | 31:13 | 12:0 | + */ + // Read Req + input wire [`DMA_RD_CHNL_NUM * 1 -1:0] dma_rd_req_valid, + input wire [`DMA_RD_CHNL_NUM * 1 -1:0] dma_rd_req_last , + input wire [`DMA_RD_CHNL_NUM * `PCIEI_DATA_W-1:0] dma_rd_req_data , + input wire [`DMA_RD_CHNL_NUM * `DMA_HEAD_W -1:0] dma_rd_req_head , + output wire [`DMA_RD_CHNL_NUM * 1 -1:0] dma_rd_req_ready, + + // DMA Read Resp + output wire [`DMA_RD_CHNL_NUM * 1 -1:0] dma_rd_rsp_valid, + output wire [`DMA_RD_CHNL_NUM * 1 -1:0] dma_rd_rsp_last , + output wire [`DMA_RD_CHNL_NUM * `PCIEI_DATA_W-1:0] dma_rd_rsp_data , + output wire [`DMA_RD_CHNL_NUM * `DMA_HEAD_W -1:0] dma_rd_rsp_head , + input wire [`DMA_RD_CHNL_NUM * 1 -1:0] dma_rd_rsp_ready, + + // DMA Write Req. + // Note that PCIe Interface owns an extra channel for P2P uses. + input wire [(`DMA_WR_CHNL_NUM - 1) * 1 -1:0] dma_wr_req_valid, + input wire [(`DMA_WR_CHNL_NUM - 1) * 1 -1:0] dma_wr_req_last , + input wire [(`DMA_WR_CHNL_NUM - 1) * `PCIEI_DATA_W-1:0] dma_wr_req_data , + input wire [(`DMA_WR_CHNL_NUM - 1) * `DMA_HEAD_W -1:0] dma_wr_req_head , + output wire [(`DMA_WR_CHNL_NUM - 1) * 1 -1:0] dma_wr_req_ready, + /* -------dma interface{end}------- */ + + /* --------p2p forward up channel{begin}-------- */ + /* *_head, valid only in first beat of a packet + * | Reserved | dst_dev | src_dev | Reserved | Byte length | + * | 63:35 | 37:35 | 34:32 | 31:16 | 15:0 | + */ + input wire [1 - 1 : 0] p2p_upper_valid, // i, 1 + input wire [1 - 1 : 0] p2p_upper_last , // i, 1 + input wire [`PCIEI_DATA_W - 1 : 0] p2p_upper_data , // i, `PCIEI_DATA_W + input wire [`P2P_UHEAD_W - 1 : 0] p2p_upper_head , // i, `P2P_UHEAD_W + output wire [1 - 1 : 0] p2p_upper_ready, // o, 1 + /* --------p2p forward up channel{end}-------- */ + + /* --------p2p forward down channel{begin}-------- */ + /* *_head, valid only in first beat of a packet + * | Reserved | dst_dev | src_dev | Reserved | Byte length | + * | 63:35 | 37:35 | 34:32 | 31:16 | 15:0 | + */ + output wire [1 - 1 : 0] p2p_down_valid, // o, 1 + output wire [1 - 1 : 0] p2p_down_last , // o, 1 + output wire [`PCIEI_DATA_W - 1 : 0] p2p_down_data , // o, `PCIEI_DATA_W + output wire [`P2P_DHEAD_W - 1 : 0] p2p_down_head , // o, `P2P_DHEAD_W + input wire [1 - 1 : 0] p2p_down_ready // i, 1 + /* --------p2p forward down channel{end}-------- */ + +`ifdef PCIEI_APB_DBG + /* -------APB reated signal{begin}------- */ + ,input wire [(2*`DMA_RD_CHNL_NUM+`DMA_WR_CHNL_NUM+2*`QUEUE_NUM+18)*`SRAM_RW_DATA_W-1:0] rw_data // i, (2*`DMA_RD_CHNL_NUM+`DMA_WR_CHNL_NUM+2*`QUEUE_NUM+18)*`SRAM_RW_DATA_W + ,input wire [31:0] dbg_sel // debug bus select + ,output wire [31:0] dbg_bus // debug bus data + /* -------APB reated signal{end}------- */ +`endif +); + +wire pcie_syn_rstn; +/* --------Init_done{begin}--------- */ +wire dma_init_done, p2p_init_done; +/* --------Init_done{end}--------- */ + +/* -------input reg{begin} -------- */ +wire [2:0] cfg_max_payload_rdma ; +wire [2:0] cfg_max_read_req_rdma; +wire [12:0] tl_cfg_busdev_rdma; +/* -------input reg{end} -------- */ + +/* --------DMA Engine{begin}-------- */ +wire [59:0] rq_tuser; + +/* --------DMA Engine{end}-------- */ + +/* --------STD_PIO Engine{begin}-------- */ +/* --------P2P Configuration Channel{begin}-------- */ +wire [1 - 1 : 0] p2p_cfg_req_valid; // o, 1 +wire [1 - 1 : 0] p2p_cfg_req_last ; // o, 1 +wire [`P2P_DATA_W - 1 : 0] p2p_cfg_req_data ; // o, `P2P_DATA_W +wire [`P2P_HEAD_W - 1 : 0] p2p_cfg_req_head ; // o, `P2P_HEAD_W +wire [1 - 1 : 0] p2p_cfg_req_ready; // i, 1 + +wire [1 - 1 : 0] p2p_cfg_rrsp_valid; // i, 1 +wire [1 - 1 : 0] p2p_cfg_rrsp_last ; // i, 1 +wire [`P2P_DATA_W - 1 : 0] p2p_cfg_rrsp_data ; // i, `P2P_DATA_W +wire [1 - 1 : 0] p2p_cfg_rrsp_ready; // o, 1 +/* --------P2P Configuration Channel{end}-------- */ + +/* -------P2P Memory Access Channel{begin}-------- */ +wire [1 - 1 : 0] p2p_mem_req_valid; // o, 1 +wire [1 - 1 : 0] p2p_mem_req_last ; // o, 1 +wire [`P2P_DATA_W - 1 : 0] p2p_mem_req_data ; // o, `P2P_DATA_W +wire [`P2P_HEAD_W - 1 : 0] p2p_mem_req_head ; // o, `P2P_HEAD_W +wire [1 - 1 : 0] p2p_mem_req_ready; // i, 1 +/* -------P2P Memory Access Channel{end}-------- */ +/* --------STD_PIO Engine{end}-------- */ + +/* --------P2P DMA Write Req{begin}-------- */ +/* dma_*_head, valid only in first beat of a packet + * | Reserved | address | Reserved | Byte length | + * | 127:96 | 95:32 | 31:13 | 12:0 | + */ +wire [1 - 1 : 0] p2p_dma_wr_req_valid; // o, 1 +wire [1 - 1 : 0] p2p_dma_wr_req_last ; // o, 1 +wire [`PCIEI_DATA_W - 1 : 0] p2p_dma_wr_req_data ; // o, `PCIEI_DATA_W +wire [`DMA_HEAD_W - 1 : 0] p2p_dma_wr_req_head ; // o, `DMA_HEAD_W +wire [1 - 1 : 0] p2p_dma_wr_req_ready; // i, 1 +/* --------P2P DMA Write Req{end}-------- */ + +/* -------Odd Parity function definition{begin}------- */ +function odd_bit; + input [7:0] bytes; + begin + odd_bit = ~(^bytes); + end +endfunction +/* -------Odd Parity function definition{end}------- */ + +`ifdef PCIEI_APB_DBG +/* -------APB reated signal{begin}------- */ +wire [(2*`DMA_RD_CHNL_NUM+`DMA_WR_CHNL_NUM+6)*`SRAM_RW_DATA_W-1:0] dma_rw_data; +wire [`SRAM_RW_DATA_W*8-1:0] pio_rw_data; +wire [(2*`QUEUE_NUM+4)*`SRAM_RW_DATA_W-1:0] p2p_rw_data; +wire [32 - 1 : 0] dma_dbg_sel, pio_dbg_sel, p2p_dbg_sel; +wire [32 - 1 : 0] dma_dbg_bus, pio_dbg_bus, p2p_dbg_bus; +/* -------APB reated signal{end}------- */ +`endif + +//------------------------------------------------------------------------------------------------------------------------------------------------------------- + +`ifdef PCIEI_APB_DBG +/* -------APB reated signal{begin}------- */ +assign {dma_rw_data, pio_rw_data, p2p_rw_data} = rw_data; +assign dma_dbg_sel = (`DMA_DBG_BASE <= dbg_sel && dbg_sel < `PIO_DBG_BASE ) ? (dbg_sel - `DMA_DBG_BASE) : 0; +assign pio_dbg_sel = (`PIO_DBG_BASE <= dbg_sel && dbg_sel < `P2P_DBG_BASE ) ? (dbg_sel - `PIO_DBG_BASE) : 0; +assign p2p_dbg_sel = (`P2P_DBG_BASE <= dbg_sel && dbg_sel < `PCIEI_DBG_SIZE) ? (dbg_sel - `P2P_DBG_BASE) : 0; +assign dbg_bus = (`DMA_DBG_BASE <= dbg_sel && dbg_sel < `PIO_DBG_BASE ) ? p2p_dbg_bus : + (`PIO_DBG_BASE <= dbg_sel && dbg_sel < `P2P_DBG_BASE ) ? pio_dbg_bus : + (`P2P_DBG_BASE <= dbg_sel && dbg_sel < `PCIEI_DBG_SIZE) ? dma_dbg_bus : 32'd0; +/* -------APB reated signal{end}------- */ +`endif + +`ifdef PCIEI_SIM + +assign pcie_syn_rstn = pcie_rst_n; + +`else + +macro_reset_sync2 u_syn_pcie_rstn( + .test_en (1'b0 ), + .reset_n (pcie_rst_n ), + .ck (pcie_clk ), + .reset_sync_n (pcie_syn_rstn ) +); + +`endif + +cdc_syncff #( + .DATA_WIDTH ( 6 + 13 ), + .RST_VALUE ( 0 ), + .SYNC_LEVELS ( 2 ) +) u_ptr_sync_w2r ( + // Inputs + .data_s ( {cfg_max_payload, cfg_max_read_req, tl_cfg_busdev} ), + .clk_d ( user_clk ), + .rstn_d ( user_rst_n ), + // Output + .data_d({cfg_max_payload_rdma, cfg_max_read_req_rdma, tl_cfg_busdev_rdma}) +); + +assign ist_mbist_done = 1'b1; +assign ist_mbist_pass = 1'b1; +/* --------DMA Engine{begin}-------- */ +DMA #( + +) DMA_inst ( + .pcie_clk ( pcie_clk ), // i, 1 + .pcie_rst_n ( pcie_syn_rstn ), // i, 1 + .dma_clk ( user_clk ), // i, 1 + .rst_n ( user_rst_n ), // i, 1 + .init_done ( dma_init_done ), // o, 1 + + /* -------pcie <--> dma interface{begin}------- */ + // Requester request + /* RQ tuser + * | 59:28 | 27:24 | 23:16 | 15 | 14:13 | 12 | 11 | 10:8 | 7:4 | 3:0 | + * | parity | seq_num | tph_st_tag | tph_indirect_tag_en | tph_type | tph_present | discontinue | addr_offset | last_be | first_be | + * | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | | + */ + .s_axis_rq_tvalid ( s_axis_rq_tvalid ), // o, 1 + .s_axis_rq_tlast ( s_axis_rq_tlast ), // o, 1 + .s_axis_rq_tdata ( s_axis_rq_tdata ), // o, `DMA_DATA_W + .s_axis_rq_tuser ( rq_tuser ), // o, 60 + .s_axis_rq_tkeep ( s_axis_rq_tkeep ), // o, `DMA_KEEP_W + .s_axis_rq_tready ( s_axis_rq_tready[0] ), // i, 1 + + // Requester Completion + /* RC tuser + * | 74:43 | 42 | 41:38 | 37:34 | 33 | 32 | 31:0 | + * | parity | discontinue | is_eof_1 | is_eof_0 | is_sof_1 | is_sof_0 | byte_en | + * | ignore | ignore | ignore | ignore | ignore | ignore | | + */ + .m_axis_rc_tvalid ( m_axis_rc_tvalid ), // i, 1 + .m_axis_rc_tlast ( m_axis_rc_tlast ), // i, 1 + .m_axis_rc_tdata ( m_axis_rc_tdata ), // i, `DMA_DATA_W + .m_axis_rc_tuser ( m_axis_rc_tuser ), // i, 75 + .m_axis_rc_tkeep ( m_axis_rc_tkeep ), // i, `DMA_KEEP_W + .m_axis_rc_tready ( m_axis_rc_tready ), // o, 1 + /* -------pcie <--> dma interface{end}------- */ + + /* -------Interrupt Interface Signals{begin}------- */ + .cfg_interrupt_msix_enable ( cfg_interrupt_msix_enable ), // i, 2 + .cfg_interrupt_msix_mask ( cfg_interrupt_msix_mask ), // i, 2 + .cfg_interrupt_msix_data ( cfg_interrupt_msix_data ), // o, 32 + .cfg_interrupt_msix_address ( cfg_interrupt_msix_address ), // o, 64 + .cfg_interrupt_msix_int ( cfg_interrupt_msix_int ), // o, 1 + .cfg_interrupt_msix_sent ( cfg_interrupt_msix_sent ), // i, 1 + .cfg_interrupt_msix_fail ( cfg_interrupt_msix_fail ), // i, 1 + .cfg_interrupt_msi_function_number ( cfg_interrupt_msi_function_number ), // o, 3 + /* -------Interrupt Interface Signals{end}------- */ + + /* -------PCIe fragment property{begin}------- */ + /* This signal indicates the (max payload size & max read request size) agreed in the communication + * 3'b000 -- 128 B + * 3'b001 -- 256 B + * 3'b010 -- 512 B + * 3'b011 -- 1024B + * 3'b100 -- 2048B + * 3'b101 -- 4096B + */ + .max_pyld_sz ( cfg_max_payload_rdma ), + .max_rd_req_sz ( cfg_max_read_req_rdma ), // max read request size + .req_id ( {tl_cfg_busdev_rdma, 3'd0} ), + /* -------PCIe fragment property{end}------- */ + + /* -------dma <--> RDMA interface{begin}------- */ + /* dma_*_head(interact with RDMA modules), valid only in first beat of a packet + * | Reserved | address | Reserved | Byte length | + * | 127:96 | 95:32 | 31:13 | 12:0 | + */ + // CEU Read Req + .dma_rd_req_valid ( dma_rd_req_valid ), // i, `DMA_RD_CHNL_NUM * 1 + .dma_rd_req_last ( dma_rd_req_last ), // i, `DMA_RD_CHNL_NUM * 1 + .dma_rd_req_data ( dma_rd_req_data ), // i, `DMA_RD_CHNL_NUM * `DMA_DATA_W + .dma_rd_req_head ( dma_rd_req_head ), // i, `DMA_RD_CHNL_NUM * `DMA_HEAD_W + .dma_rd_req_ready ( dma_rd_req_ready ), // o, `DMA_RD_CHNL_NUM * 1 + + // CEU DMA Read Resp + .dma_rd_rsp_valid ( dma_rd_rsp_valid ), // o, `DMA_RD_CHNL_NUM * 1 + .dma_rd_rsp_last ( dma_rd_rsp_last ), // o, `DMA_RD_CHNL_NUM * 1 + .dma_rd_rsp_data ( dma_rd_rsp_data ), // o, `DMA_RD_CHNL_NUM * `DMA_DATA_W + .dma_rd_rsp_head ( dma_rd_rsp_head ), // o, `DMA_RD_CHNL_NUM * `DMA_HEAD_W + .dma_rd_rsp_ready ( dma_rd_rsp_ready ), // i, `DMA_RD_CHNL_NUM * 1 + + // CEU DMA Write Req + .dma_wr_req_valid ( {p2p_dma_wr_req_valid, dma_wr_req_valid} ), // i, `DMA_WR_CHNL_NUM * 1 + .dma_wr_req_last ( {p2p_dma_wr_req_last , dma_wr_req_last } ), // i, `DMA_WR_CHNL_NUM * 1 + .dma_wr_req_data ( {p2p_dma_wr_req_data , dma_wr_req_data } ), // i, `DMA_WR_CHNL_NUM * `DMA_DATA_W + .dma_wr_req_head ( {p2p_dma_wr_req_head , dma_wr_req_head } ), // i, `DMA_WR_CHNL_NUM * `DMA_HEAD_W + .dma_wr_req_ready ( {p2p_dma_wr_req_ready, dma_wr_req_ready} ) // o, `DMA_WR_CHNL_NUM * 1 + /* -------dma <--> RDMA interface{end}------- */ + +`ifdef PCIEI_APB_DBG + /* -------APB reated signal{begin}------- */ + ,.rw_data ( dma_rw_data ) // i, (2*`DMA_RD_CHNL_NUM+`DMA_WR_CHNL_NUM+6)*`SRAM_RW_DATA_W + ,.dbg_sel ( dma_dbg_sel ) // debug bus select + ,.dbg_bus ( dma_dbg_bus ) // debug bus data + /* -------APB reated signal{end}------- */ +`endif +); + +assign s_axis_rq_tuser = {odd_bit(s_axis_rq_tdata[8 * 32 - 1: 8 * 31]), + odd_bit(s_axis_rq_tdata[8 * 31 - 1: 8 * 30]), + odd_bit(s_axis_rq_tdata[8 * 30 - 1: 8 * 29]), + odd_bit(s_axis_rq_tdata[8 * 29 - 1: 8 * 28]), + odd_bit(s_axis_rq_tdata[8 * 28 - 1: 8 * 27]), + odd_bit(s_axis_rq_tdata[8 * 27 - 1: 8 * 26]), + odd_bit(s_axis_rq_tdata[8 * 26 - 1: 8 * 25]), + odd_bit(s_axis_rq_tdata[8 * 25 - 1: 8 * 24]), + odd_bit(s_axis_rq_tdata[8 * 24 - 1: 8 * 23]), + odd_bit(s_axis_rq_tdata[8 * 23 - 1: 8 * 22]), + odd_bit(s_axis_rq_tdata[8 * 22 - 1: 8 * 21]), + odd_bit(s_axis_rq_tdata[8 * 21 - 1: 8 * 20]), + odd_bit(s_axis_rq_tdata[8 * 20 - 1: 8 * 19]), + odd_bit(s_axis_rq_tdata[8 * 19 - 1: 8 * 18]), + odd_bit(s_axis_rq_tdata[8 * 18 - 1: 8 * 17]), + odd_bit(s_axis_rq_tdata[8 * 17 - 1: 8 * 16]), + odd_bit(s_axis_rq_tdata[8 * 16 - 1: 8 * 15]), + odd_bit(s_axis_rq_tdata[8 * 15 - 1: 8 * 14]), + odd_bit(s_axis_rq_tdata[8 * 14 - 1: 8 * 13]), + odd_bit(s_axis_rq_tdata[8 * 13 - 1: 8 * 12]), + odd_bit(s_axis_rq_tdata[8 * 12 - 1: 8 * 11]), + odd_bit(s_axis_rq_tdata[8 * 11 - 1: 8 * 10]), + odd_bit(s_axis_rq_tdata[8 * 10 - 1: 8 * 9 ]), + odd_bit(s_axis_rq_tdata[8 * 9 - 1: 8 * 8 ]), + odd_bit(s_axis_rq_tdata[8 * 8 - 1: 8 * 7 ]), + odd_bit(s_axis_rq_tdata[8 * 7 - 1: 8 * 6 ]), + odd_bit(s_axis_rq_tdata[8 * 6 - 1: 8 * 5 ]), + odd_bit(s_axis_rq_tdata[8 * 5 - 1: 8 * 4 ]), + odd_bit(s_axis_rq_tdata[8 * 4 - 1: 8 * 3 ]), + odd_bit(s_axis_rq_tdata[8 * 3 - 1: 8 * 2 ]), + odd_bit(s_axis_rq_tdata[8 * 2 - 1: 8 * 1 ]), + odd_bit(s_axis_rq_tdata[8 * 1 - 1: 8 * 0 ]), + rq_tuser[27:0]}; +/* --------DMA Engine{end}-------- */ + +/* --------STD_PIO Engine{begin}-------- */ +STD_PIO #( + .AXIL_DATA_WIDTH ( AXIL_DATA_WIDTH ), + .AXIL_ADDR_WIDTH ( AXIL_ADDR_WIDTH ) +) STD_PIO_inst ( + + .pcie_clk ( pcie_clk ), // i, 1 + .pcie_rst_n ( pcie_syn_rstn ), // i, 1 + .user_clk ( user_clk ), // i, 1 + .rst_n ( user_rst_n ), // i, 1 + + .init_done ( rdma_init_done & dma_init_done & p2p_init_done ), // i, 1 + + /* -------Completer Requester{begin}------- */ + /* CQ tuser + * | 84:53 | 52:45 | 44:43 | 42 | 41 | 40 | 39:8 | 7:4 | 3:0 | + * | parity | tph_st_tag | tph_type | tph_present | discontinue | sop | byte_en | last_be | first_be | + * | 0 | 0 | 0 | | | | ignore | | | + */ + .m_axis_cq_tvalid ( m_axis_cq_tvalid ), // i, 1 + .m_axis_cq_tlast ( m_axis_cq_tlast ), // i, 1 + .m_axis_cq_tuser ( m_axis_cq_tuser ), // i, 85 + .m_axis_cq_tdata ( m_axis_cq_tdata ), // i, `PIO_DATA_W + .m_axis_cq_tkeep ( m_axis_cq_tkeep ), // i, `DMA_KEEP_W + .m_axis_cq_tready ( m_axis_cq_tready ), // o, 1 + /* -------Completer Requester{end}------- */ + + /* -------Completer Completion{begin}------- */ + /* CC tuser + * | 32:1 | 0 | + * | parity | discontinue | + * | ignore | ignore | + */ + .s_axis_cc_tvalid ( s_axis_cc_tvalid ), // o, 1 + .s_axis_cc_tlast ( s_axis_cc_tlast ), // o, 1 + .s_axis_cc_tuser ( ), // o, 33 + .s_axis_cc_tdata ( s_axis_cc_tdata ), // o, `PIO_DATA_W + .s_axis_cc_tkeep ( s_axis_cc_tkeep ), // o, `DMA_KEEP_W + .s_axis_cc_tready ( s_axis_cc_tready[0] ), // i, 1 + /* -------Completer Completion{end}------- */ + + /* -------PCIe fragment property{begin}------- */ + /* This signal indicates the (max payload size & max read request size) agreed in the communication + * 3'b000 -- 128 B + * 3'b001 -- 256 B + * 3'b010 -- 512 B + * 3'b011 -- 1024B + * 3'b100 -- 2048B + * 3'b101 -- 4096B + */ + .max_pyld_sz ( cfg_max_payload_rdma ), + .max_rd_req_sz ( cfg_max_read_req_rdma ), // max read request size + /* -------PCIe fragment property{end}------- */ + + /* -------pio <--> RDMA interface{begin}------- */ + .pio_hcr_in_param ( pio_hcr_in_param ), // o, 64 + .pio_hcr_in_modifier ( pio_hcr_in_modifier ), // o, 32 + .pio_hcr_out_dma_addr ( pio_hcr_out_dma_addr ), // o, 64 + .pio_hcr_out_param ( pio_hcr_out_param ), // i, 64 + .pio_hcr_token ( pio_hcr_token ), // o, 16 + .pio_hcr_status ( pio_hcr_status ), // i, 8 + .pio_hcr_go ( pio_hcr_go ), // o, 1 + .pio_hcr_clear ( pio_hcr_clear ), // i, 1 + .pio_hcr_event ( pio_hcr_event ), // o, 1 + .pio_hcr_op_modifier ( pio_hcr_op_modifier ), // o, 8 + .pio_hcr_op ( pio_hcr_op ), // o, 12 + /* -------pio <--> RDMA interface{end}------- */ + + /* --------SQ Doorbell{begin}-------- */ + .pio_uar_db_valid ( pio_uar_db_valid ), // o, 1 + .pio_uar_db_data ( pio_uar_db_data ), // o, 64 + .pio_uar_db_ready ( pio_uar_db_ready ), // i, 1 + /* --------SQ Doorbell{end}-------- */ + + /* --------ARM CQ interface{begin}-------- */ + .cq_ren ( cq_ren ), // i, 1 + .cq_num ( cq_num ), // i, 32 + .cq_dout ( cq_dout ), // o, 1 + /* --------ARM CQ interface{end}-------- */ + + /* --------ARM EQ interface{begin}-------- */ + .eq_ren ( eq_ren ), // i, 1 + .eq_num ( eq_num ), // i, 31 + .eq_dout ( eq_dout ), // o, 1 + /* --------ARM EQ interface{end}-------- */ + + /* --------Interrupt Vector entry request & response{begin}-------- */ + .pio_eq_int_req_valid ( pio_eq_int_req_valid ), // i, 1 + .pio_eq_int_req_num ( pio_eq_int_req_num[`RDMA_MSIX_NUM_LOG-1:0] ), // i, `RDMA_MSIX_NUM_LOG + .pio_eq_int_req_ready ( pio_eq_int_req_ready ), // o, 1 + + .pio_eq_int_rsp_valid ( pio_eq_int_rsp_valid ), // i, 1 + .pio_eq_int_rsp_data ( pio_eq_int_rsp_data ), // i, `RDMA_MSIX_DATA_W + .pio_eq_int_rsp_ready ( pio_eq_int_rsp_ready ), // o, 1 + /* -------Interrupt Vector entry request & response{end}-------- */ + + /* -------Reset signal{begin}------- */ + .cmd_rst ( cmd_rst ), // o, 1 + /* -------Reset signal{end}------- */ + + /* --------Interact with Ethernet BAR{begin}------- */ + .m_axil_awaddr ( m_axi_awaddr ) , // o, AXIL_ADDR_WIDTH + .m_axil_awvalid ( m_axi_awvalid ) , // o, 1 + .m_axil_awready ( m_axi_awready ) , // i, 1 + + .m_axil_wdata ( m_axi_wdata ), // o, AXIL_DATA_WIDTH + .m_axil_wstrb ( m_axi_wstrb ), // o, AXIL_STRB_WIDTH + .m_axil_wvalid ( m_axi_wvalid ), // o, 1 + .m_axil_wready ( m_axi_wready ), // i, 1 + + .m_axil_bvalid ( m_axi_bvalid ), // i, 1 + .m_axil_bready ( m_axi_bready ), // o, 1 + + .m_axil_araddr ( m_axi_araddr ), // o, AXIL_ADDR_WIDTH + .m_axil_arvalid ( m_axi_arvalid ), // o, 1 + .m_axil_arready ( m_axi_arready ), // i, 1 + + .m_axil_rdata ( m_axi_rdata ), // i, AXIL_DATA_WIDTH + .m_axil_rvalid ( m_axi_rvalid ), // i, 1 + .m_axil_rready ( m_axi_rready ), // o, 1 + /* --------Interact with Ethernet BAR{end}------- */ + + /* --------P2P Configuration Channel{begin}-------- */ + /* p2p_req head + * | 127 | 126:64 | 63:32 | 31:13 | 12:0 | + * | is_wr | Reserved | addr | Reserved | byte_len | + */ + .p2p_cfg_req_valid ( p2p_cfg_req_valid ), // o, 1 + .p2p_cfg_req_last ( p2p_cfg_req_last ), // o, 1 + .p2p_cfg_req_data ( p2p_cfg_req_data ), // o, `PIO_DATA_W + .p2p_cfg_req_head ( p2p_cfg_req_head ), // o, `P2P_HEAD_W + .p2p_cfg_req_ready ( p2p_cfg_req_ready ), // i, 1 + + .p2p_cfg_rrsp_valid ( p2p_cfg_rrsp_valid ), // i, 1 + .p2p_cfg_rrsp_last ( p2p_cfg_rrsp_last ), // i, 1 + .p2p_cfg_rrsp_data ( p2p_cfg_rrsp_data ), // i, `PIO_DATA_W + .p2p_cfg_rrsp_ready ( p2p_cfg_rrsp_ready ), // o, 1 + /* --------P2P Configuration Channel{end}-------- */ + + /* -------P2P Memory Access Channel{begin}-------- */ + /* p2p_req head + * | 127 | 126:64 | 63:32 | 31:13 | 12:0 | + * | is_wr | Reserved | addr | Reserved | byte_len | + */ + .p2p_mem_req_valid ( p2p_mem_req_valid ), // o, 1 + .p2p_mem_req_last ( p2p_mem_req_last ), // o, 1 + .p2p_mem_req_data ( p2p_mem_req_data ), // o, `PIO_DATA_W + .p2p_mem_req_head ( p2p_mem_req_head ), // o, `P2P_HEAD_W + .p2p_mem_req_ready ( p2p_mem_req_ready ) // i, 1 + /* -------P2P Memory Access Channel{end}-------- */ + +`ifdef PCIEI_APB_DBG + /* -------APB reated signal{begin}------- */ + ,.rw_data ( pio_rw_data ) // i, `SRAM_RW_DATA_W*8 + ,.dbg_sel ( pio_dbg_sel ) // i, 32; debug bus select + ,.dbg_bus ( pio_dbg_bus ) // o, 32; debug bus data + /* -------APB reated signal{end}------- */ +`endif +); + +assign s_axis_cc_tuser = s_axis_cc_tvalid ? + {odd_bit(s_axis_cc_tdata[8 * 32 - 1: 8 * 31]), + odd_bit(s_axis_cc_tdata[8 * 31 - 1: 8 * 30]), + odd_bit(s_axis_cc_tdata[8 * 30 - 1: 8 * 29]), + odd_bit(s_axis_cc_tdata[8 * 29 - 1: 8 * 28]), + odd_bit(s_axis_cc_tdata[8 * 28 - 1: 8 * 27]), + odd_bit(s_axis_cc_tdata[8 * 27 - 1: 8 * 26]), + odd_bit(s_axis_cc_tdata[8 * 26 - 1: 8 * 25]), + odd_bit(s_axis_cc_tdata[8 * 25 - 1: 8 * 24]), + odd_bit(s_axis_cc_tdata[8 * 24 - 1: 8 * 23]), + odd_bit(s_axis_cc_tdata[8 * 23 - 1: 8 * 22]), + odd_bit(s_axis_cc_tdata[8 * 22 - 1: 8 * 21]), + odd_bit(s_axis_cc_tdata[8 * 21 - 1: 8 * 20]), + odd_bit(s_axis_cc_tdata[8 * 20 - 1: 8 * 19]), + odd_bit(s_axis_cc_tdata[8 * 19 - 1: 8 * 18]), + odd_bit(s_axis_cc_tdata[8 * 18 - 1: 8 * 17]), + odd_bit(s_axis_cc_tdata[8 * 17 - 1: 8 * 16]), + odd_bit(s_axis_cc_tdata[8 * 16 - 1: 8 * 15]), + odd_bit(s_axis_cc_tdata[8 * 15 - 1: 8 * 14]), + odd_bit(s_axis_cc_tdata[8 * 14 - 1: 8 * 13]), + odd_bit(s_axis_cc_tdata[8 * 13 - 1: 8 * 12]), + odd_bit(s_axis_cc_tdata[8 * 12 - 1: 8 * 11]), + odd_bit(s_axis_cc_tdata[8 * 11 - 1: 8 * 10]), + odd_bit(s_axis_cc_tdata[8 * 10 - 1: 8 * 9 ]), + odd_bit(s_axis_cc_tdata[8 * 9 - 1: 8 * 8 ]), + odd_bit(s_axis_cc_tdata[8 * 8 - 1: 8 * 7 ]), + odd_bit(s_axis_cc_tdata[8 * 7 - 1: 8 * 6 ]), + odd_bit(s_axis_cc_tdata[8 * 6 - 1: 8 * 5 ]), + odd_bit(s_axis_cc_tdata[8 * 5 - 1: 8 * 4 ]), + odd_bit(s_axis_cc_tdata[8 * 4 - 1: 8 * 3 ]), + odd_bit(s_axis_cc_tdata[8 * 3 - 1: 8 * 2 ]), + odd_bit(s_axis_cc_tdata[8 * 2 - 1: 8 * 1 ]), + odd_bit(s_axis_cc_tdata[8 * 1 - 1: 8 * 0 ]), + 1'b0} : 33'd0; +/* --------STD_PIO Engine{end}-------- */ + + +//P2P #( +// +//) P2P_inst ( +// .clk ( user_clk ), // i, 1 +// .rst_n ( user_rst_n ), // i, 1 +// .init_done ( p2p_init_done ), // o, 1 +// +// /* --------P2P Configuration Channel{begin}-------- */ +// /* p2p_req head +// * | 127 | 126:64 | 63:32 | 31:13 | 12:0 | +// * | is_wr | Reserved | addr | Reserved | byte_len | +// */ +// .p2p_cfg_req_valid ( p2p_cfg_req_valid ), // i, 1 +// .p2p_cfg_req_last ( p2p_cfg_req_last ), // i, 1 +// .p2p_cfg_req_data ( p2p_cfg_req_data ), // i, `P2P_DATA_W +// .p2p_cfg_req_head ( p2p_cfg_req_head ), // i, `P2P_HEAD_W +// .p2p_cfg_req_ready ( p2p_cfg_req_ready ), // o, 1 +// +// .p2p_cfg_rrsp_valid ( p2p_cfg_rrsp_valid ), // o, 1 +// .p2p_cfg_rrsp_last ( p2p_cfg_rrsp_last ), // o, 1 +// .p2p_cfg_rrsp_data ( p2p_cfg_rrsp_data ), // o, `P2P_DATA_W +// .p2p_cfg_rrsp_ready ( p2p_cfg_rrsp_ready ), // i, 1 +// /* --------P2P Configuration Channel{end}-------- */ +// +// /* -------P2P Memory Access Channel{begin}-------- */ +// /* p2p_req head +// * | 127 | 126:64 | 63:32 | 31:13 | 12:0 | +// * | is_wr | Reserved | addr | Reserved | byte_len | +// */ +// .p2p_mem_req_valid ( p2p_mem_req_valid ), // i, 1 +// .p2p_mem_req_last ( p2p_mem_req_last ), // i, 1 +// .p2p_mem_req_data ( p2p_mem_req_data ), // i, `P2P_DATA_W +// .p2p_mem_req_head ( p2p_mem_req_head ), // i, `P2P_HEAD_W +// .p2p_mem_req_ready ( p2p_mem_req_ready ), // o, 1 +// /* -------P2P Memory Access Channel{end}-------- */ +// +// /* --------P2P DMA Write Req{begin}-------- */ +// /* dma_*_head, valid only in first beat of a packet +// * | Reserved | address | Reserved | Byte length | +// * | 127:96 | 95:32 | 31:13 | 12:0 | +// */ +// .p2p_dma_wr_req_valid ( p2p_dma_wr_req_valid ), // o, 1 +// .p2p_dma_wr_req_last ( p2p_dma_wr_req_last ), // o, 1 +// .p2p_dma_wr_req_data ( p2p_dma_wr_req_data ), // o, `P2P_DATA_W +// .p2p_dma_wr_req_head ( p2p_dma_wr_req_head ), // o, `DMA_HEAD_W +// .p2p_dma_wr_req_ready ( p2p_dma_wr_req_ready ), // i, 1 +// /* --------P2P DMA Write Req{end}-------- */ +// +// /* --------p2p forward up channel{begin}-------- */ +// /* *_head, valid only in first beat of a packet +// * | Reserved | dst_dev | src_dev | Reserved | Byte length | +// * | 63:35 | 37:35 | 34:32 | 31:16 | 15:0 | +// */ +// .p2p_upper_valid ( p2p_upper_valid ), // i, 1 +// .p2p_upper_last ( p2p_upper_last ), // i, 1 +// .p2p_upper_data ( p2p_upper_data ), // i, `P2P_DATA_W +// .p2p_upper_head ( p2p_upper_head ), // i, `P2P_UHEAD_W +// .p2p_upper_ready ( p2p_upper_ready ), // o, 1 +// /* --------p2p forward up channel{end}-------- */ +// +// /* --------p2p forward down channel{begin}-------- */ +// /* *_head, valid only in first beat of a packet +// * | Reserved | dst_dev | src_dev | Reserved | Byte length | +// * | 63:35 | 37:35 | 34:32 | 31:16 | 15:0 | +// */ +// .p2p_down_valid ( p2p_down_valid ), // o, 1 +// .p2p_down_last ( p2p_down_last ), // o, 1 +// .p2p_down_data ( p2p_down_data ), // o, `P2P_DATA_W +// .p2p_down_head ( p2p_down_head ), // o, `P2P_DHEAD_W +// .p2p_down_ready ( p2p_down_ready ) // i, 1 +// /* --------p2p forward down channel{end}-------- */ +// +//`ifdef PCIEI_APB_DBG +// /* -------APB reated signal{begin}------- */ +// ,.rw_data ( p2p_rw_data ) // i, (2*`QUEUE_NUM+4)*`SRAM_RW_DATA_W +// ,.dbg_sel ( p2p_dbg_sel ) // i, 32; debug bus select +// ,.dbg_bus ( p2p_dbg_bus ) // o, 32; debug bus data +// /* -------APB reated signal{end}------- */ +//`endif +//); + +endmodule diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/README.md b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/README.md new file mode 100644 index 0000000000000000000000000000000000000000..d1e82cddfa04f36ac401c9aa7e0d0c6713c051cc --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/README.md @@ -0,0 +1 @@ +PCIeInterface diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/STD_PIO/README.md b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/STD_PIO/README.md new file mode 100644 index 0000000000000000000000000000000000000000..54e1fc56087f16bb708cbeda34cb5c14002cb43b --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/STD_PIO/README.md @@ -0,0 +1 @@ +Handle PCIe Read/Write issued from host CPU. diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/STD_PIO/STD_PIO.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/STD_PIO/STD_PIO.v new file mode 100644 index 0000000000000000000000000000000000000000..1572f9fdbabcdb382a2d6a661d79a12b58f3c003 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/STD_PIO/STD_PIO.v @@ -0,0 +1,893 @@ +`timescale 1ns / 100ps +//************************************************************************* +// > File : STD_PIO.v +// > Author : Kangning +// > Date : 2022-03-11 +// > Note : Interface for pio access. +// > V1.0 -- An standard PIO module, Top module of PIO. +// > Note that: +// > 1. we sassume the packet must be 4KB aligned. +//************************************************************************* + + +module STD_PIO #( + parameter AXIL_DATA_WIDTH = 32 , + parameter AXIL_ADDR_WIDTH = 24 , + + parameter AXIL_STRB_WIDTH = (AXIL_DATA_WIDTH/8) +)( + input wire pcie_clk , + input wire pcie_rst_n, + input wire user_clk , + input wire rst_n , + + input wire init_done , // i, 1 + + /* -------Completer Requester{begin}------- */ + /* CQ tuser + * | 84:53 | 52:45 | 44:43 | 42 | 41 | 40 | 39:8 | 7:4 | 3:0 | + * | parity | tph_st_tag | tph_type | tph_present | discontinue | sop | byte_en | last_be | first_be | + * | 0 | 0 | 0 | | | | ignore | | | + */ + input wire m_axis_cq_tvalid, + input wire m_axis_cq_tlast , + input wire [84 :0] m_axis_cq_tuser , + input wire [`PIO_KEEP_W-1:0] m_axis_cq_tkeep , + input wire [`PIO_DATA_W-1:0] m_axis_cq_tdata , + output wire m_axis_cq_tready, + /* -------Completer Requester{end}------- */ + + /* -------Completer Completion{begin}------- */ + /* CC tuser + * | 32:1 | 0 | + * | parity | discontinue | + * | ignore | ignore | + */ + output wire [`PIO_DATA_W-1:0] s_axis_cc_tdata , + output wire s_axis_cc_tlast , + output wire [32 :0] s_axis_cc_tuser , + output wire [`PIO_KEEP_W-1:0] s_axis_cc_tkeep , + output wire s_axis_cc_tvalid, + input wire s_axis_cc_tready, + /* -------Completer Completion{end}------- */ + + /* -------PCIe fragment property{begin}------- */ + /* This signal indicates the (max payload size & max read request size) agreed in the communication + * 3'b000 -- 128 B + * 3'b001 -- 256 B + * 3'b010 -- 512 B + * 3'b011 -- 1024B + * 3'b100 -- 2048B + * 3'b101 -- 4096B + */ + input wire [2:0] max_pyld_sz , + input wire [2:0] max_rd_req_sz, // max read request size + /* -------PCIe fragment property{end}------- */ + + /* -------pio <--> RDMA interface{begin}------- */ + output wire [63:0] pio_hcr_in_param , + output wire [31:0] pio_hcr_in_modifier , + output wire [63:0] pio_hcr_out_dma_addr , + input wire [63:0] pio_hcr_out_param , + output wire [15:0] pio_hcr_token , + input wire [ 7:0] pio_hcr_status , + output wire pio_hcr_go , + input wire pio_hcr_clear , + output wire pio_hcr_event , + output wire [ 7:0] pio_hcr_op_modifier , + output wire [11:0] pio_hcr_op , + /* -------pio <-->RDMA interface{end}------- */ + + /* --------SQ Doorbell{begin}-------- */ + output wire pio_uar_db_valid, // o, 1 + output wire [63:0] pio_uar_db_data , // o, 64 + input wire pio_uar_db_ready, // i, 1 + /* --------SQ Doorbell{end}-------- */ + + /* --------ARM CQ interface{begin}-------- */ + input wire cq_ren , // i, 1 + input wire [31:0] cq_num , // i, 32 + output wire cq_dout, // o, 1 + /* --------ARM CQ interface{end}-------- */ + + /* --------ARM EQ interface{begin}-------- */ + input wire eq_ren , // i, 1 + input wire [31:0] eq_num , // i, 31 + output wire eq_dout, // o, 1 + /* --------ARM EQ interface{end}-------- */ + + /* --------Interrupt Vector entry request & response{begin}-------- */ + input wire pio_eq_int_req_valid, // i, 1 + input wire [`RDMA_MSIX_NUM_LOG-1:0] pio_eq_int_req_num , // i, `RDMA_MSIX_NUM_LOG + output wire pio_eq_int_req_ready, // o, 1 + + output wire pio_eq_int_rsp_valid, // o, 1 + output wire [`RDMA_MSIX_DATA_W -1:0] pio_eq_int_rsp_data , // o, `RDMA_MSIX_DATA_W + input wire pio_eq_int_rsp_ready, // i, 1 + /* -------Interrupt Vector entry request & response{end}-------- */ + + /* -------Reset signal{begin}------- */ + output wire cmd_rst, + /* -------Reset signal{end}------- */ + + /* --------Interact with Ethernet BAR{begin}------- */ + output wire [AXIL_ADDR_WIDTH-1:0] m_axil_awaddr , + output wire m_axil_awvalid, + input wire m_axil_awready, + + output wire [AXIL_DATA_WIDTH-1:0] m_axil_wdata , + output wire [AXIL_STRB_WIDTH-1:0] m_axil_wstrb , // byte select + output wire m_axil_wvalid, + input wire m_axil_wready, + + input wire m_axil_bvalid, + output wire m_axil_bready, + + output wire [AXIL_ADDR_WIDTH-1:0] m_axil_araddr , + output wire m_axil_arvalid, + input wire m_axil_arready, + + input wire [AXIL_DATA_WIDTH-1:0] m_axil_rdata , + input wire m_axil_rvalid, + output wire m_axil_rready, + /* --------Interact with Ethernet BAR{end}------- */ + + /* --------P2P Configuration Channel{begin}-------- */ + /* p2p_req head + * | 127 | 126:64 | 63:32 | 31:13 | 12:0 | + * | is_wr | Reserved | addr | Reserved | byte_len | + */ + output wire [1 - 1 : 0] p2p_cfg_req_valid, // o, 1 + output wire [1 - 1 : 0] p2p_cfg_req_last , // o, 1 + output wire [`PIO_DATA_W - 1 : 0] p2p_cfg_req_data , // o, `PIO_DATA_W + output wire [`P2P_HEAD_W - 1 : 0] p2p_cfg_req_head , // o, `P2P_HEAD_W + input wire [1 - 1 : 0] p2p_cfg_req_ready, // i, 1 + + input wire [1 - 1 : 0] p2p_cfg_rrsp_valid, // i, 1 + input wire [1 - 1 : 0] p2p_cfg_rrsp_last , // i, 1 + input wire [`PIO_DATA_W - 1 : 0] p2p_cfg_rrsp_data , // i, `PIO_DATA_W + output wire [1 - 1 : 0] p2p_cfg_rrsp_ready, // o, 1 + /* --------P2P Configuration Channel{end}-------- */ + + /* -------P2P Memory Access Channel{begin}-------- */ + /* p2p_req head + * | 127 | 126:64 | 63:32 | 31:13 | 12:0 | + * | is_wr | Reserved | addr | Reserved | byte_len | + */ + output wire [1 - 1 : 0] p2p_mem_req_valid, // o, 1 + output wire [1 - 1 : 0] p2p_mem_req_last , // o, 1 + output wire [`PIO_DATA_W - 1 : 0] p2p_mem_req_data , // o, `PIO_DATA_W + output wire [`P2P_HEAD_W - 1 : 0] p2p_mem_req_head , // o, `P2P_HEAD_W + input wire [1 - 1 : 0] p2p_mem_req_ready // i, 1 + /* -------P2P Memory Access Channel{end}-------- */ + +`ifdef PCIEI_APB_DBG + /* -------APB reated signal{begin}------- */ + ,input wire [`SRAM_RW_DATA_W*8-1:0] rw_data // i, `SRAM_RW_DATA_W*8 + ,input wire [31:0] dbg_sel // i, 32 + ,output wire [31:0] dbg_bus // o, 32 + /* -------APB reated signal{end}------- */ +`endif + +`ifdef SIMULATION + /* ------- Debug interface {begin}------- */ + /* | reserved | reserved | idx | end | out | + * | 255:10 | 9:5 | 4:2 | 1 | 0 | + */ + ,output wire [255:0] debug + /* ------- Debug interface {end}------- */ +`endif +); + +/* -------Async fifo{begin}------- */ +wire cq_tvalid; +wire cq_tlast ; +wire [84 :0] cq_tuser ; +wire [`PIO_DATA_W-1:0] cq_tdata ; +wire cq_tready; + +wire cc_tvalid; +wire cc_tlast ; +wire [`PIO_KEEP_W-1:0] cc_tkeep ; +wire [`PIO_DATA_W-1:0] cc_tdata ; +wire cc_tready; + +wire cq_full, cq_empty; +/* -------Async fifo{end}------- */ + +/* --------PIO Request interface{begin}-------- */ +wire [`PIO_DATA_W-1:0] axis_req_tdata ; +wire [`PIO_USER_W-1:0] axis_req_tuser ; +wire axis_req_tlast ; +wire axis_req_tvalid; +wire axis_req_tready; +/* --------PIO Request interface{end}-------- */ + +/* ---------PIO Response interface{begin}-------- */ +wire [`PIO_DATA_W-1:0] axis_rrsp_tdata ; +wire [`PIO_USER_W-1:0] axis_rrsp_tuser ; +wire axis_rrsp_tlast ; +wire axis_rrsp_tvalid; +wire axis_rrsp_tready; +/* ---------PIO Response interface{end}-------- */ + + +/* ---------Splited PIO Interface{begin}-------- */ +// register request +wire [`PIO_DATA_W-1:0] pio_uar_req_data , pio_p2p_mem_req_data , pio_p2p_cfg_req_data , pio_int_req_data , pio_eth_req_data , pio_hcr_req_data ; +wire [`PIO_HEAD_W-1:0] pio_uar_req_head , pio_p2p_mem_req_head , pio_p2p_cfg_req_head , pio_int_req_head , pio_eth_req_head , pio_hcr_req_head ; +wire [1 -1:0] pio_uar_req_last , pio_p2p_mem_req_last , pio_p2p_cfg_req_last , pio_int_req_last , pio_eth_req_last , pio_hcr_req_last ; +wire [1 -1:0] pio_uar_req_valid, pio_p2p_mem_req_valid, pio_p2p_cfg_req_valid, pio_int_req_valid, pio_eth_req_valid, pio_hcr_req_valid; +wire [1 -1:0] pio_uar_req_ready, pio_p2p_mem_req_ready, pio_p2p_cfg_req_ready, pio_int_req_ready, pio_eth_req_ready, pio_hcr_req_ready; + +// register read response +wire [`PIO_DATA_W-1:0] pio_p2p_rrsp_data , pio_int_rrsp_data , pio_eth_rrsp_data , pio_hcr_rrsp_data ; +wire [`PIO_HEAD_W-1:0] pio_p2p_rrsp_head , pio_int_rrsp_head , pio_eth_rrsp_head , pio_hcr_rrsp_head ; +wire [1 -1:0] pio_p2p_rrsp_last , pio_int_rrsp_last , pio_eth_rrsp_last , pio_hcr_rrsp_last ; +wire [1 -1:0] pio_p2p_rrsp_valid, pio_int_rrsp_valid, pio_eth_rrsp_valid, pio_hcr_rrsp_valid; +wire [1 -1:0] pio_p2p_rrsp_ready, pio_int_rrsp_ready, pio_eth_rrsp_ready, pio_hcr_rrsp_ready; +/* --------Splited PIO Interface{end}-------- */ + + +`ifdef PCIEI_APB_DBG +/* -------APB reated signal{begin}------- */ +wire [1:0] cq_rtsel; +wire [1:0] cq_wtsel; +wire [1:0] cq_ptsel; +wire cq_vg ; +wire cq_vs ; +wire [`SRAM_RW_DATA_W-1:0] rw_data_cq, rw_data_cc; +wire [2*`SRAM_RW_DATA_W-1:0] rw_data_rdma_uar; +wire [4*`SRAM_RW_DATA_W-1:0] rw_data_rdma_int; +wire [31:0] dbg_sel_std_pio_top, dbg_sel_cq_parser, dbg_sel_cc_composer, dbg_sel_pio_req, + dbg_sel_pio_rrsp, dbg_sel_rdma_uar, dbg_sel_rdma_int, dbg_sel_rdma_hcr, + dbg_sel_eth_cfg, dbg_sel_p2p_access; +wire [31:0] dbg_bus_std_pio_top, dbg_bus_cq_parser, dbg_bus_cc_composer, dbg_bus_pio_req, + dbg_bus_pio_rrsp, dbg_bus_rdma_uar, dbg_bus_rdma_int, dbg_bus_rdma_hcr, + dbg_bus_eth_cfg, dbg_bus_p2p_access; +wire [`STD_PIO_TOP_SIGNAL_W-1:0] dbg_signal_std_pio_top; +wire [`CC_ASYNC_SIGNAL_W-1:0] dbg_signal_cc; +/* -------APB reated signal{end}------- */ +`endif + +//---------------------------------------------------------------------------------------------------------------- + +`ifdef PCIEI_APB_DBG +/* -------APB reated signal{begin}------- */ +assign {cq_rtsel, cq_wtsel, cq_ptsel, cq_vg, cq_vs} = rw_data_cq; +assign {rw_data_cq, rw_data_cc, rw_data_rdma_uar, rw_data_rdma_int} = rw_data; + +assign dbg_sel_std_pio_top = (`PIO_TOP_DBG_B <= dbg_sel && dbg_sel < `CQ_PARSER_DBG_B ) ? (dbg_sel - `PIO_TOP_DBG_B ) : 32'd0; +assign dbg_sel_cq_parser = (`CQ_PARSER_DBG_B <= dbg_sel && dbg_sel < `CC_COMPOSER_DBG_B) ? (dbg_sel - `CQ_PARSER_DBG_B ) : 32'd0; +assign dbg_sel_cc_composer = (`CC_COMPOSER_DBG_B <= dbg_sel && dbg_sel < `PIO_REQ_DBG_B ) ? (dbg_sel - `CC_COMPOSER_DBG_B) : 32'd0; +assign dbg_sel_pio_req = (`PIO_REQ_DBG_B <= dbg_sel && dbg_sel < `PIO_RRSP_DBG_B ) ? (dbg_sel - `PIO_REQ_DBG_B ) : 32'd0; +assign dbg_sel_pio_rrsp = (`PIO_RRSP_DBG_B <= dbg_sel && dbg_sel < `RDMA_UAR_DBG_B ) ? (dbg_sel - `PIO_RRSP_DBG_B ) : 32'd0; +assign dbg_sel_rdma_uar = (`RDMA_UAR_DBG_B <= dbg_sel && dbg_sel < `RDMA_INT_DBG_B ) ? (dbg_sel - `RDMA_UAR_DBG_B ) : 32'd0; +assign dbg_sel_rdma_int = (`RDMA_INT_DBG_B <= dbg_sel && dbg_sel < `RDMA_HCR_DBG_B ) ? (dbg_sel - `RDMA_INT_DBG_B ) : 32'd0; +assign dbg_sel_rdma_hcr = (`RDMA_HCR_DBG_B <= dbg_sel && dbg_sel < `ETH_CFG_DBG_B ) ? (dbg_sel - `RDMA_HCR_DBG_B ) : 32'd0; +assign dbg_sel_eth_cfg = (`ETH_CFG_DBG_B <= dbg_sel && dbg_sel < `P2P_ACCESS_DBG_B ) ? (dbg_sel - `ETH_CFG_DBG_B ) : 32'd0; +assign dbg_sel_p2p_access = (`P2P_ACCESS_DBG_B <= dbg_sel && dbg_sel < `STD_PIO_DBG_SIZE ) ? (dbg_sel - `P2P_ACCESS_DBG_B ) : 32'd0; +assign dbg_bus = (`PIO_TOP_DBG_B <= dbg_sel && dbg_sel < `CQ_PARSER_DBG_B ) ? dbg_bus_std_pio_top : + (`CQ_PARSER_DBG_B <= dbg_sel && dbg_sel < `CC_COMPOSER_DBG_B) ? dbg_bus_cq_parser : + (`CC_COMPOSER_DBG_B <= dbg_sel && dbg_sel < `PIO_REQ_DBG_B ) ? dbg_bus_cc_composer : + (`PIO_REQ_DBG_B <= dbg_sel && dbg_sel < `PIO_RRSP_DBG_B ) ? dbg_bus_pio_req : + (`PIO_RRSP_DBG_B <= dbg_sel && dbg_sel < `RDMA_UAR_DBG_B ) ? dbg_bus_pio_rrsp : + (`RDMA_UAR_DBG_B <= dbg_sel && dbg_sel < `RDMA_INT_DBG_B ) ? dbg_bus_rdma_uar : + (`RDMA_INT_DBG_B <= dbg_sel && dbg_sel < `RDMA_HCR_DBG_B ) ? dbg_bus_rdma_int : + (`RDMA_HCR_DBG_B <= dbg_sel && dbg_sel < `ETH_CFG_DBG_B ) ? dbg_bus_rdma_hcr : + (`ETH_CFG_DBG_B <= dbg_sel && dbg_sel < `P2P_ACCESS_DBG_B ) ? dbg_bus_eth_cfg : + (`P2P_ACCESS_DBG_B <= dbg_sel && dbg_sel < `STD_PIO_DBG_SIZE ) ? dbg_bus_p2p_access : 32'd0; + +// Debug signal for pio_top +assign dbg_bus_std_pio_top = dbg_signal_std_pio_top >> {dbg_sel_std_pio_top, 5'd0}; + +assign dbg_signal_std_pio_top = { // 8323 + init_done, // 1 + m_axis_cq_tvalid, m_axis_cq_tlast, m_axis_cq_tuser, m_axis_cq_tkeep, m_axis_cq_tdata, m_axis_cq_tready, // 352 + s_axis_cc_tdata, s_axis_cc_tlast, s_axis_cc_tuser, s_axis_cc_tkeep, s_axis_cc_tvalid, s_axis_cc_tready, // 300 + max_pyld_sz, max_rd_req_sz, // 6 + + pio_hcr_in_param, pio_hcr_in_modifier, pio_hcr_out_dma_addr, pio_hcr_out_param, + pio_hcr_token, pio_hcr_status, pio_hcr_go, pio_hcr_clear, pio_hcr_event, pio_hcr_op_modifier, pio_hcr_op, // 271 + + pio_uar_db_valid, pio_uar_db_data, pio_uar_db_ready, // 66 + cq_ren, cq_num, cq_dout, eq_ren, eq_num, eq_dout, // 68 + + pio_eq_int_req_valid, pio_eq_int_req_num, pio_eq_int_req_ready, + pio_eq_int_rsp_valid, pio_eq_int_rsp_data, pio_eq_int_rsp_ready, // 138 + + cmd_rst, // 1 + + m_axil_awaddr, m_axil_awvalid, m_axil_awready, + m_axil_wdata, m_axil_wstrb, m_axil_wvalid, m_axil_wready, + m_axil_bvalid, m_axil_bready, // 66 + + m_axil_araddr, m_axil_arvalid, m_axil_arready, m_axil_rdata, m_axil_rvalid, m_axil_rready, // 60 + p2p_cfg_req_valid, p2p_cfg_req_last, p2p_cfg_req_data, p2p_cfg_req_head, p2p_cfg_req_ready, // 387 + p2p_cfg_rrsp_valid, p2p_cfg_rrsp_last, p2p_cfg_rrsp_data, p2p_cfg_rrsp_ready, // 259 + p2p_mem_req_valid, p2p_mem_req_last, p2p_mem_req_data, p2p_mem_req_head, p2p_mem_req_ready, // 387 + cq_tvalid, cq_tlast, cq_tuser, cq_tdata, cq_tready, // 344 + cc_tvalid, cc_tlast, cc_tkeep, cc_tdata, cc_tready, // 267 + cq_full, cq_empty, // 2 + + axis_req_tdata, axis_req_tuser, axis_req_tlast, axis_req_tvalid, axis_req_tready, + axis_rrsp_tdata, axis_rrsp_tuser, axis_rrsp_tlast, axis_rrsp_tvalid, axis_rrsp_tready, // 798 + + pio_uar_req_data, pio_p2p_mem_req_data, pio_p2p_cfg_req_data, pio_int_req_data, pio_eth_req_data, pio_hcr_req_data, + pio_uar_req_head, pio_p2p_mem_req_head, pio_p2p_cfg_req_head, pio_int_req_head, pio_eth_req_head, pio_hcr_req_head, + pio_uar_req_last, pio_p2p_mem_req_last, pio_p2p_cfg_req_last, pio_int_req_last, pio_eth_req_last, pio_hcr_req_last, + pio_uar_req_valid, pio_p2p_mem_req_valid, pio_p2p_cfg_req_valid, pio_int_req_valid, pio_eth_req_valid, pio_hcr_req_valid, + pio_uar_req_ready, pio_p2p_mem_req_ready, pio_p2p_cfg_req_ready, pio_int_req_ready, pio_eth_req_ready, pio_hcr_req_ready, // 2346 + + pio_p2p_rrsp_data, pio_int_rrsp_data, pio_eth_rrsp_data, pio_hcr_rrsp_data, + pio_p2p_rrsp_head, pio_int_rrsp_head, pio_eth_rrsp_head, pio_hcr_rrsp_head, + pio_p2p_rrsp_last, pio_int_rrsp_last, pio_eth_rrsp_last, pio_hcr_rrsp_last, + pio_p2p_rrsp_valid, pio_int_rrsp_valid, pio_eth_rrsp_valid, pio_hcr_rrsp_valid, + pio_p2p_rrsp_ready, pio_int_rrsp_ready, pio_eth_rrsp_ready, pio_hcr_rrsp_ready, // 1564 + + dbg_signal_cc // CC_ASYNC_SIGNAL_W (640) +}; +/* -------APB reated signal{end}------- */ +`endif + +assign m_axis_cq_tready = !cq_full; +assign cq_tvalid = !cq_empty; +pcieifc_async_fifo #( + .DATA_WIDTH ( 1 + 8 + 1 + `PIO_DATA_W ), // sop + first_be + last_be + last + data + .ADDR_WIDTH ( 5 ) +) cq_async_fifo ( + .wr_clk ( pcie_clk ), // i, 1 + .rd_clk ( user_clk ), // i, 1 + .wrst_n ( pcie_rst_n ), // i, 1 + .rrst_n ( rst_n ), // i, 1 + + .wen ( m_axis_cq_tvalid & m_axis_cq_tready ), // i, 1 + .din ( {m_axis_cq_tuser[40], m_axis_cq_tuser[7:0], m_axis_cq_tlast, m_axis_cq_tdata} ), // i, DATA_WIDTH + .full ( cq_full ), // o, 1 + + .ren ( cq_tready & cq_tvalid ), // i, 1 + .dout ( {cq_tuser[40], cq_tuser[7:0], cq_tlast, cq_tdata} ), // o, DATA_WIDTH + .empty ( cq_empty ) // o, 1 + +`ifdef PCIEI_APB_DBG + ,.rtsel ( cq_rtsel ) // i, 2 + ,.wtsel ( cq_wtsel ) // i, 2 + ,.ptsel ( cq_ptsel ) // i, 2 + ,.vg ( cq_vg ) // i, 1 + ,.vs ( cq_vs ) // i, 1 +`endif +); +assign cq_tuser[84:41] = 0; +assign cq_tuser[39:8] = 0; + +cc_async_fifos cc_async_fifos ( + .user_clk ( user_clk ), + .pcie_clk ( pcie_clk ), + .user_rst_n ( rst_n ), + .pcie_rst_n ( pcie_rst_n ), + + /* -------std_pio --> pcie interface, pio part{begin}------- */ + .pio_axis_cc_tvalid ( cc_tvalid ), // i, 1 + .pio_axis_cc_tlast ( cc_tlast ), // i, 1 + .pio_axis_cc_tdata ( cc_tdata ), // i, `PIO_DATA_W + .pio_axis_cc_tuser ( 33'd0 ), // i, 33 + .pio_axis_cc_tkeep ( cc_tkeep ), // i, `PIO_KEEP_W + .pio_axis_cc_tready ( cc_tready ), // o, 1 + /* -------std_pio --> pcie interface, pio part{end}------- */ + + /* -------std_pio --> pcie interface, pcie part{begin}------- */ + /* CC tuser + * | 32:1 | 0 | + * | parity | discontinue | + * | ignore | ignore | + */ + .st_pcie_axis_cc_tvalid ( s_axis_cc_tvalid ), // o, 1 + .st_pcie_axis_cc_tlast ( s_axis_cc_tlast ), // o, 1 + .st_pcie_axis_cc_tdata ( s_axis_cc_tdata ), // o, `PIO_DATA_W + .st_pcie_axis_cc_tuser ( s_axis_cc_tuser ), // o, 33 + .st_pcie_axis_cc_tkeep ( s_axis_cc_tkeep ), // o, `PIO_KEEP_W + .st_pcie_axis_cc_tready ( s_axis_cc_tready ) // i, 1 + /* -------std_pio --> pcie interface, pcie part{begin}------- */ + +`ifdef PCIEI_APB_DBG + /* -------APB reated signal{begin}------- */ + ,.rw_data ( rw_data_cc ) // i, `SRAM_RW_DATA_W + ,.dbg_signal ( dbg_signal_cc ) // o, `CC_ASYNC_SIGNAL_W + /* -------APB reated signal{end}------- */ +`endif +); + +cq_parser #( + +) cq_parser ( + .clk ( user_clk ), // i, 1 + .rst_n ( rst_n ), // i, 1 + + /* -------Completer Requester{begin}------- */ + /* CQ tuser + * | 84:53 | 52:45 | 44:43 | 42 | 41 | 40 | 39:8 | 7:4 | 3:0 | + * | parity | tph_st_tag | tph_type | tph_present | discontinue | sop | byte_en | last_be | first_be | + * | 0 | 0 | 0 | | | | ignore | | | + */ + .cq_tuser ( cq_tuser ), // i , 85 + .cq_tdata ( cq_tdata ), // i, `PIO_DATA_W + .cq_tlast ( cq_tlast ), // i, 1 + .cq_tvalid ( cq_tvalid ), // i, 1 + .cq_tready ( cq_tready ), // o, 1 + /* -------Completer Requester{end}------- */ + + /* --------PIO Request intterface{begin}-------- */ + /* tuser + * | 139 | 138:136 | 135:132 | 131:128 | 127:96 | 95:0 | + * | is_wr | bar_id | first_be | last_be | aligned_addr | cc_head | + * | | | | | | | + */ + .m_axis_req_tdata ( axis_req_tdata ), // o, `PIO_DATA_W + .m_axis_req_tuser ( axis_req_tuser ), // o, `PIO_USER_W + .m_axis_req_tlast ( axis_req_tlast ), // o, 1 + .m_axis_req_tvalid ( axis_req_tvalid ), // o, 1 + .m_axis_req_tready ( axis_req_tready ) // i, 1 + /* --------PIO Request intterface{end}-------- */ + +`ifdef PCIEI_APB_DBG + /* -------APB reated signal{begin}------- */ + ,.dbg_sel ( dbg_sel_cq_parser ) // i, 32; debug bus select + ,.dbg_bus ( dbg_bus_cq_parser ) // o, 32; debug bus data + /* -------APB reated signal{end}------- */ +`endif +); + +cc_composer #( + +) cc_composer ( + .clk ( user_clk ), // i, 1 + .rst_n ( rst_n ), // i, 1 + + /* -------Completer Completion{begin}------- */ + /* CC tuser + * | 32:1 | 0 | + * | parity | discontinue | + * | ignore | ignore | + */ + .cc_tdata ( cc_tdata ), // o, `PIO_DATA_W + .cc_tlast ( cc_tlast ), // o, 1 + .cc_tkeep ( cc_tkeep ), // o, `PIO_KEEP_W + .cc_tvalid ( cc_tvalid ), // o, 1 + .cc_tready ( cc_tready ), // i, 1 + /* -------Completer Completion{end}------- */ + + /* --------PIO Response interface{begin}-------- */ + /* tuser + * | 139 | 138:136 | 135:132 | 131:128 | 127:96 | 95:0 | + * | is_wr | bar_id | first_be | last_be | aligned_addr | cc_head | + * | | | | | | | + */ + .s_axis_rrsp_tdata ( axis_rrsp_tdata ), // i, `PIO_DATA_W + .s_axis_rrsp_tuser ( axis_rrsp_tuser ), // i, `PIO_USER_W + .s_axis_rrsp_tlast ( axis_rrsp_tlast ), // i, 1 + .s_axis_rrsp_tvalid ( axis_rrsp_tvalid ), // i, 1 + .s_axis_rrsp_tready ( axis_rrsp_tready ) // o, 1 + /* --------PIO Response interface{end}-------- */ + +`ifdef PCIEI_APB_DBG + /* -------APB reated signal{begin}------- */ + ,.dbg_sel ( dbg_sel_cc_composer ) // i, 32; debug bus select + ,.dbg_bus ( dbg_bus_cc_composer ) // o, 32; debug bus data + /* -------APB reated signal{end}------- */ +`endif +); + +pio_req #( + .CHANNEL_NUM ( 6 ) +) pio_req ( + .clk ( user_clk ), // i, 1 + .rst_n ( rst_n ), // i, 1 + + /* --------PIO Request interface{begin}-------- */ + /* pio_tuser + * | 139 | 138:136 | 135:132 | 131:128 | 127:96 | 95:0 | + * | is_wr | bar_id | first_be | last_be | aligned_addr | cc_head | + * | | | | | | | + */ + .s_axis_req_tdata ( axis_req_tdata ), // i, `PIO_DATA_W + .s_axis_req_tuser ( axis_req_tuser ), // i, `PIO_USER_W + .s_axis_req_tlast ( axis_req_tlast ), // i, 1 + .s_axis_req_tvalid ( axis_req_tvalid ), // i, 1 + .s_axis_req_tready ( axis_req_tready ), // o, 1 + + /* pio_head + * | 131 | 130:128 | 127:96 | 95:0 | + * | is_wr | bar_id | addr | cc_head | + */ + .m_axis_req_data ( {pio_uar_req_data , pio_p2p_mem_req_data , pio_p2p_cfg_req_data , pio_int_req_data , pio_eth_req_data , pio_hcr_req_data } ), // o, CHANNEL_NUM * `PIO_DATA_W + .m_axis_req_head ( {pio_uar_req_head , pio_p2p_mem_req_head , pio_p2p_cfg_req_head , pio_int_req_head , pio_eth_req_head , pio_hcr_req_head } ), // o, CHANNEL_NUM * `PIO_HEAD_W + .m_axis_req_last ( {pio_uar_req_last , pio_p2p_mem_req_last , pio_p2p_cfg_req_last , pio_int_req_last , pio_eth_req_last , pio_hcr_req_last } ), // o, CHANNEL_NUM * 1 + .m_axis_req_valid ( {pio_uar_req_valid, pio_p2p_mem_req_valid, pio_p2p_cfg_req_valid, pio_int_req_valid, pio_eth_req_valid, pio_hcr_req_valid} ), // o, CHANNEL_NUM * 1 + .m_axis_req_ready ( {pio_uar_req_ready, pio_p2p_mem_req_ready, pio_p2p_cfg_req_ready, pio_int_req_ready, pio_eth_req_ready, pio_hcr_req_ready} ) // i, CHANNEL_NUM * 1 + /* --------PIO Request interface{end}-------- */ + +`ifdef PCIEI_APB_DBG + /* -------APB reated signal{begin}------- */ + ,.dbg_sel ( dbg_sel_pio_req ) // i, 32; debug bus select + ,.dbg_bus ( dbg_bus_pio_req ) // o, 32; debug bus data + /* -------APB reated signal{end}------- */ +`endif +); + +pio_rrsp #( + .CHANNEL_NUM ( 4 ) +) pio_rrsp ( + .clk ( user_clk ), // i, 1 + .rst_n ( rst_n ), // i, 1 + + /* --------PIO Request interface{begin}-------- */ + /* pio_tuser + * | 139 | 138:136 | 135:132 | 131:128 | 127:96 | 95:0 | + * | is_wr | bar_id | first_be | last_be | aligned_addr | cc_head | + * | | | | | | | + */ + .m_axis_rrsp_tdata ( axis_rrsp_tdata ), // o, `PIO_DATA_W + .m_axis_rrsp_tuser ( axis_rrsp_tuser ), // o, `PIO_USER_W + .m_axis_rrsp_tlast ( axis_rrsp_tlast ), // o, 1 + .m_axis_rrsp_tvalid ( axis_rrsp_tvalid ), // o, 1 + .m_axis_rrsp_tready ( axis_rrsp_tready ), // i, 1 + /* --------PIO Request interface{end}-------- */ + + /* --------PIO Request interface{begin}-------- */ + /* pio_head + * | 131 | 130:128 | 127:96 | 95:0 | + * | is_wr | bar_id | addr | cc_head | + */ + .s_axis_rrsp_data ( {pio_p2p_rrsp_data , pio_int_rrsp_data , pio_eth_rrsp_data , pio_hcr_rrsp_data } ), // i, CHANNEL_NUM * `PIO_DATA_W + .s_axis_rrsp_head ( {pio_p2p_rrsp_head , pio_int_rrsp_head , pio_eth_rrsp_head , pio_hcr_rrsp_head } ), // i, CHANNEL_NUM * `PIO_HEAD_W + .s_axis_rrsp_last ( {pio_p2p_rrsp_last , pio_int_rrsp_last , pio_eth_rrsp_last , pio_hcr_rrsp_last } ), // i, CHANNEL_NUM * 1 + .s_axis_rrsp_valid ( {pio_p2p_rrsp_valid, pio_int_rrsp_valid, pio_eth_rrsp_valid, pio_hcr_rrsp_valid} ), // i, CHANNEL_NUM * 1 + .s_axis_rrsp_ready ( {pio_p2p_rrsp_ready, pio_int_rrsp_ready, pio_eth_rrsp_ready, pio_hcr_rrsp_ready} ), // o, CHANNEL_NUM * 1 + /* --------PIO Request interface{end}-------- */ + + /* -------PCIe fragment property{begin}------- */ + /* This signal indicates the (max payload size & max read request size) agreed in the communication + * 3'b000 -- 128 B + * 3'b001 -- 256 B + * 3'b010 -- 512 B + * 3'b011 -- 1024B + * 3'b100 -- 2048B + * 3'b101 -- 4096B + */ + .max_pyld_sz ( max_pyld_sz ), // i, 3 + .max_rd_req_sz ( max_rd_req_sz ) // i, 3 ;max read request size + /* -------PCIe fragment property{end}------- */ + +`ifdef PCIEI_APB_DBG + /* -------APB reated signal{begin}------- */ + ,.dbg_sel ( dbg_sel_pio_rrsp ) // i, 32; debug bus select + ,.dbg_bus ( dbg_bus_pio_rrsp ) // o, 32; debug bus data + /* -------APB reated signal{end}------- */ +`endif + +`ifdef SIMULATION + /* ------- Debug interface {begin}------- */ + /* | reserved | reserved | top_idx | top_end | top_out | + * | 255:10 | 9:5 | 4:2 | 1 | 0 | + */ + ,.debug (debug) + /* ------- Debug interface {end}------- */ +`endif +); + +rdma_uar #( + +) rdma_uar ( + .clk ( user_clk ), // i, 1 + .rst_n ( rst_n ), // i, 1 + + /* --------Req Channel{begin}-------- */ + /* pio_head + * | 131 | 130:128 | 127:96 | 95:0 | + * | is_wr | bar_id | addr | cc_head | + */ + .pio_uar_req_data ( pio_uar_req_data ), // i, `PIO_DATA_W + .pio_uar_req_head ( pio_uar_req_head ), // i, `PIO_HEAD_W + .pio_uar_req_last ( pio_uar_req_last ), // i, 1 + .pio_uar_req_valid ( pio_uar_req_valid ), // i, 1 + .pio_uar_req_ready ( pio_uar_req_ready ), // o, 1 + /* --------Req Channel{end}-------- */ + + /* --------SQ Doorbell{begin}-------- */ + .pio_uar_db_valid ( pio_uar_db_valid ), // o, 1 + .pio_uar_db_data ( pio_uar_db_data ), // o, 64 + .pio_uar_db_ready ( pio_uar_db_ready ), // i, 1 + /* --------SQ Doorbell{end}-------- */ + + /* --------ARM CQ interface{begin}-------- */ + .cq_ren ( cq_ren ), // i, 1 + .cq_num ( cq_num ), // i, 31 + .cq_dout_reg ( cq_dout ), // o, 1 + /* --------ARM CQ interface{end}-------- */ + + /* --------ARM EQ interface{begin}-------- */ + .eq_ren ( eq_ren ), // i, 1 + .eq_num ( eq_num ), // i, 31 + .eq_dout_reg ( eq_dout ) // o, 1 + /* --------ARM EQ interface{end}-------- */ + +`ifdef PCIEI_APB_DBG + /* -------APB reated signal{begin}------- */ + ,.rw_data ( rw_data_rdma_uar ) // i, 2*`SRAM_RW_DATA_W + ,.dbg_sel ( dbg_sel_rdma_uar ) // i, 32; debug bus select + ,.dbg_bus ( dbg_bus_rdma_uar ) // o, 32; debug bus data + /* -------APB reated signal{end}------- */ +`endif +); + +rdma_int #( + +) rdma_int ( + .clk ( user_clk ), // i, 1 + .rst_n ( rst_n ), // i, 1 + + /* --------Req Channel{begin}-------- */ + /* pio_head + * | 131 | 130:128 | 127:96 | 95:0 | + * | is_wr | bar_id | addr | cc_head | + */ + .pio_int_req_data ( pio_int_req_data ), // i, `PIO_DATA_W + .pio_int_req_head ( pio_int_req_head ), // i, `PIO_HEAD_W + .pio_int_req_last ( pio_int_req_last ), // i, 1 + .pio_int_req_valid ( pio_int_req_valid ), // i, 1 + .pio_int_req_ready ( pio_int_req_ready ), // o, 1 + /* --------Req Channel{end}-------- */ + + /* --------Rsp Channel{begin}-------- */ + /* pio_head + * | 131 | 130:128 | 127:96 | 95:0 | + * | is_wr | bar_id | addr | cc_head | + */ + .pio_int_rrsp_data ( pio_int_rrsp_data ), // o, `PIO_DATA_W + .pio_int_rrsp_head ( pio_int_rrsp_head ), // o, `PIO_HEAD_W + .pio_int_rrsp_last ( pio_int_rrsp_last ), // o, 1 + .pio_int_rrsp_valid ( pio_int_rrsp_valid ), // o, 1 + .pio_int_rrsp_ready ( pio_int_rrsp_ready ), // i, 1 + /* -------Rsp Channel{end}-------- */ + + /* --------Rsp Channel{begin}-------- */ + .in_pio_eq_int_req_valid ( pio_eq_int_req_valid ), // i, 1 + .in_pio_eq_int_req_num ( pio_eq_int_req_num ), // i, `RDMA_MSIX_NUM_LOG + .in_pio_eq_int_req_ready ( pio_eq_int_req_ready ), // o, 1 + + .out_pio_eq_int_rsp_valid ( pio_eq_int_rsp_valid ), // o, 1 + .out_pio_eq_int_rsp_data ( pio_eq_int_rsp_data ), // o, `RDMA_MSIX_DATA_W + .out_pio_eq_int_rsp_ready ( pio_eq_int_rsp_ready ) // i, 1 + /* -------Rsp Channel{end}-------- */ + +`ifdef PCIEI_APB_DBG + /* -------APB reated signal{begin}------- */ + ,.rw_data ( rw_data_rdma_int ) // i, 4*`SRAM_RW_DATA_W + ,.dbg_sel ( dbg_sel_rdma_int ) // i, 32; debug bus select + ,.dbg_bus ( dbg_bus_rdma_int ) // o, 32; debug bus data + /* -------APB reated signal{end}------- */ +`endif +); + +rdma_hcr #( + +) rdma_hcr ( + + .clk ( user_clk ), // i, 1 + .rst_n ( rst_n ), // i, 1 + + /* --------Req Channel{begin}-------- */ + /* pio_head + * | 131 | 130:128 | 127:96 | 95:0 | + * | is_wr | bar_id | addr | cc_head | + */ + .pio_hcr_req_data ( pio_hcr_req_data ), // i, `PIO_DATA_W + .pio_hcr_req_head ( pio_hcr_req_head ), // i, `PIO_HEAD_W + .pio_hcr_req_last ( pio_hcr_req_last ), // i, 1 + .pio_hcr_req_valid ( pio_hcr_req_valid ), // i, 1 + .pio_hcr_req_ready ( pio_hcr_req_ready ), // o, 1 + /* --------Req Channel{end}-------- */ + + /* --------Rsp Channel{begin}-------- */ + /* pio_head + * | 131 | 130:128 | 127:96 | 95:0 | + * | is_wr | bar_id | addr | cc_head | + */ + .pio_hcr_rrsp_data ( pio_hcr_rrsp_data ), // o, `PIO_DATA_W + .pio_hcr_rrsp_head ( pio_hcr_rrsp_head ), // o, `PIO_HEAD_W + .pio_hcr_rrsp_last ( pio_hcr_rrsp_last ), // o, 1 + .pio_hcr_rrsp_valid ( pio_hcr_rrsp_valid ), // o, 1 + .pio_hcr_rrsp_ready ( pio_hcr_rrsp_ready ), // i, 1 + /* -------Rsp Channel{end}-------- */ + + /* -------pio <--> RDMA interface{begin}------- */ + .pio_hcr_in_param ( pio_hcr_in_param ), // o, 64 + .pio_hcr_in_modifier ( pio_hcr_in_modifier ), // o, 32 + .pio_hcr_out_dma_addr ( pio_hcr_out_dma_addr ), // o, 64 + .pio_hcr_out_param ( pio_hcr_out_param ), // i, 64 + .pio_hcr_token ( pio_hcr_token ), // o, 16 + .pio_hcr_status ( pio_hcr_status ), // i, 8 + .pio_hcr_go ( pio_hcr_go ), // o, 1 + .pio_hcr_clear ( pio_hcr_clear ), // i, 1 + .pio_hcr_event ( pio_hcr_event ), // o, 1 + .pio_hcr_op_modifier ( pio_hcr_op_modifier ), // o, 8 + .pio_hcr_op ( pio_hcr_op ), // o, 12 + /* -------pio <--> RDMA interface{end}------- */ + + /* -------Reset signal{begin}------- */ + .cmd_rst ( cmd_rst ), // o, 1 + .init_done ( init_done ) // i, 1 + /* -------Reset signal{end}------- */ + +`ifdef PCIEI_APB_DBG + /* -------APB reated signal{begin}------- */ + ,.dbg_sel ( dbg_sel_rdma_hcr ) // i, 32; debug bus select + ,.dbg_bus ( dbg_bus_rdma_hcr ) // o, 32; debug bus data + /* -------APB reated signal{end}------- */ +`endif +); + +eth_cfg #( + .AXIL_DATA_WIDTH ( AXIL_DATA_WIDTH ), + .AXIL_ADDR_WIDTH ( AXIL_ADDR_WIDTH ) +) eth_cfg ( + + .clk ( user_clk ), // i, 1 + .rst_n ( rst_n ), // i, 1 + + /* --------Req Channel{begin}-------- */ + /* pio_head + * | 131 | 130:128 | 127:96 | 95:0 | + * | is_wr | bar_id | addr | cc_head | + */ + .pio_eth_req_data ( pio_eth_req_data ), // i, `PIO_DATA_W + .pio_eth_req_head ( pio_eth_req_head ), // i, `PIO_HEAD_W + .pio_eth_req_last ( pio_eth_req_last ), // i, 1 + .pio_eth_req_valid ( pio_eth_req_valid ), // i, 1 + .pio_eth_req_ready ( pio_eth_req_ready ), // o, 1 + /* --------Req Channel{end}-------- */ + + /* --------Rsp Channel{begin}-------- */ + /* pio_head + * | 131 | 130:128 | 127:96 | 95:0 | + * | is_wr | bar_id | addr | cc_head | + */ + .st_pio_eth_rrsp_data ( pio_eth_rrsp_data ), // o, `PIO_DATA_W + .st_pio_eth_rrsp_head ( pio_eth_rrsp_head ), // o, `PIO_HEAD_W + .st_pio_eth_rrsp_last ( pio_eth_rrsp_last ), // o, 1 + .st_pio_eth_rrsp_valid ( pio_eth_rrsp_valid ), // o, 1 + .st_pio_eth_rrsp_ready ( pio_eth_rrsp_ready ), // i, 1 + /* -------Rsp Channel{end}-------- */ + + /* --------Interact with Ethernet BAR{begin}------- */ + .m_axil_awaddr ( m_axil_awaddr ) , // o, AXIL_ADDR_WIDTH + .m_axil_awvalid ( m_axil_awvalid ) , // o, 1 + .m_axil_awready ( m_axil_awready ) , // i, 1 + + .m_axil_wdata ( m_axil_wdata ), // o, AXIL_DATA_WIDTH + .m_axil_wstrb ( m_axil_wstrb ), // o, AXIL_STRB_WIDTH + .m_axil_wvalid ( m_axil_wvalid ), // o, 1 + .m_axil_wready ( m_axil_wready ), // i, 1 + + .m_axil_bvalid ( m_axil_bvalid ), // i, 1 + .m_axil_bready ( m_axil_bready ), // o, 1 + + .m_axil_araddr ( m_axil_araddr ), // o, AXIL_ADDR_WIDTH + .m_axil_arvalid ( m_axil_arvalid ), // o, 1 + .m_axil_arready ( m_axil_arready ), // i, 1 + + .m_axil_rdata ( m_axil_rdata ), // i, AXIL_DATA_WIDTH + .m_axil_rvalid ( m_axil_rvalid ), // i, 1 + .m_axil_rready ( m_axil_rready ) // o, 1 + /* --------Interact with Ethernet BAR{end}------- */ + +`ifdef PCIEI_APB_DBG + /* -------APB reated signal{begin}------- */ + ,.dbg_sel ( dbg_sel_eth_cfg ) // i, 32; debug bus select + ,.dbg_bus ( dbg_bus_eth_cfg ) // o, 32; debug bus data + /* -------APB reated signal{end}------- */ +`endif +); + +p2p_access #( + +) p2p_access ( + .clk ( user_clk ), // i, 1 + .rst_n ( rst_n ), // i, 1 + + /* --------Req Channel{begin}-------- */ + /* pio_head + * | 131 | 130:128 | 127:96 | 95:0 | + * | is_wr | bar_id | addr | cc_head | + */ + .pio_p2p_mem_req_valid ( pio_p2p_mem_req_valid ), // i, 1 + .pio_p2p_mem_req_last ( pio_p2p_mem_req_last ), // i, 1 + .pio_p2p_mem_req_data ( pio_p2p_mem_req_data ), // i, `PIO_DATA_W + .pio_p2p_mem_req_head ( pio_p2p_mem_req_head ), // i, `PIO_HEAD_W + .pio_p2p_mem_req_ready ( pio_p2p_mem_req_ready ), // o, 1 + /* --------Req Channel{end}-------- */ + + /* --------Req Channel{begin}-------- */ + /* pio_head + * | 131 | 130:128 | 127:96 | 95:0 | + * | is_wr | bar_id | addr | cc_head | + */ + .pio_p2p_cfg_req_valid ( pio_p2p_cfg_req_valid ), // i, 1 + .pio_p2p_cfg_req_last ( pio_p2p_cfg_req_last ), // i, 1 + .pio_p2p_cfg_req_data ( pio_p2p_cfg_req_data ), // i, `PIO_DATA_W + .pio_p2p_cfg_req_head ( pio_p2p_cfg_req_head ), // i, `PIO_HEAD_W + .pio_p2p_cfg_req_ready ( pio_p2p_cfg_req_ready ), // o, 1 + /* --------Req Channel{end}-------- */ + + /* --------Rsp Channel{begin}-------- */ + /* pio_head + * | 131 | 130:128 | 127:96 | 95:0 | + * | is_wr | bar_id | addr | cc_head | + */ + .pio_p2p_rrsp_valid ( pio_p2p_rrsp_valid ), // o, 1 + .pio_p2p_rrsp_last ( pio_p2p_rrsp_last ), // o, 1 + .pio_p2p_rrsp_data ( pio_p2p_rrsp_data ), // o, `PIO_DATA_W + .pio_p2p_rrsp_head ( pio_p2p_rrsp_head ), // o, `PIO_HEAD_W + .pio_p2p_rrsp_ready ( pio_p2p_rrsp_ready ), // i, 1 + /* -------Rsp Channel{end}-------- */ + + /* --------P2P Configuration Channel{begin}-------- */ + /* p2p_req head + * | 127 | 126:64 | 63:32 | 31:13 | 12:0 | + * | is_wr | Reserved | addr | Reserved | byte_len | + */ + .p2p_cfg_req_valid ( p2p_cfg_req_valid ), // o, 1 + .p2p_cfg_req_last ( p2p_cfg_req_last ), // o, 1 + .p2p_cfg_req_data ( p2p_cfg_req_data ), // o, `PIO_DATA_W + .p2p_cfg_req_head ( p2p_cfg_req_head ), // o, `P2P_HEAD_W + .p2p_cfg_req_ready ( p2p_cfg_req_ready ), // i, 1 + + .p2p_cfg_rrsp_valid ( p2p_cfg_rrsp_valid ), // i, 1 + .p2p_cfg_rrsp_last ( p2p_cfg_rrsp_last ), // i, 1 + .p2p_cfg_rrsp_data ( p2p_cfg_rrsp_data ), // i, `PIO_DATA_W + .p2p_cfg_rrsp_ready ( p2p_cfg_rrsp_ready ), // o, 1 + /* --------P2P Configuration Channel{end}-------- */ + + /* -------P2P Memory Access Channel{begin}-------- */ + /* p2p_req head + * | 127 | 126:64 | 63:32 | 31:13 | 12:0 | + * | is_wr | Reserved | addr | Reserved | byte_len | + */ + .p2p_mem_req_valid ( p2p_mem_req_valid ), // o, 1 + .p2p_mem_req_last ( p2p_mem_req_last ), // o, 1 + .p2p_mem_req_data ( p2p_mem_req_data ), // o, `PIO_DATA_W + .p2p_mem_req_head ( p2p_mem_req_head ), // o, `P2P_HEAD_W + .p2p_mem_req_ready ( p2p_mem_req_ready ) // i, 1 + /* -------P2P Memory Access Channel{end}-------- */ + +`ifdef PCIEI_APB_DBG + /* -------APB reated signal{begin}------- */ + ,.dbg_sel ( dbg_sel_p2p_access ) // i, 32; debug bus select + ,.dbg_bus ( dbg_bus_p2p_access ) // o, 32; debug bus data + /* -------APB reated signal{end}------- */ +`endif +); + + +`ifdef ILA_ON +//ila_cq_async_fifo_wr( +// .clk(pcie_clk), + +// .probe0( m_axis_cq_tvalid ), // i, 1 +// .probe1( cq_full ), // i, DATA_WIDTH +// .probe2( {m_axis_cq_tuser[40], m_axis_cq_tuser[7:0], m_axis_cq_tlast, m_axis_cq_tdata} ) +//); + +//ila_cq_async_fifo_rd ila_cq_async_fifo_rd_inst( +// .clk(user_clk), + +// .probe0 ( cq_tvalid ), // i, 1 +// .probe1 ( cq_empty ), // o, DATA_WIDTH +// .probe2 ( {cq_tuser[40], cq_tuser[7:0], cq_tlast, cq_tdata} ) // o, 1 +//); + +`endif + + +endmodule // PIO + diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/STD_PIO/cc_async_fifos.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/STD_PIO/cc_async_fifos.v new file mode 100644 index 0000000000000000000000000000000000000000..0b5fd984e323126ed7c54426b6fce84b47246701 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/STD_PIO/cc_async_fifos.v @@ -0,0 +1,211 @@ +`timescale 1ns / 100ps +//************************************************************************* +// > File Name: cc_async_fifos.v +// > Author : Kangning +// > Date : 2023-02-24 +// > Note : cc_async_fifos, used to separate rdma and pcie clock domain, +// > in Completion Completer Channel. +//************************************************************************* + +//`include "../lib/global_include_h.v" + +module cc_async_fifos #( + +) ( + input wire user_clk , + input wire pcie_clk , + input wire user_rst_n, + input wire pcie_rst_n, + + /* -------std_pio --> pcie interface, pio part{begin}------- */ + /* CC tuser + * | 32:1 | 0 | + * | parity | discontinue | + * | ignore | ignore | + */ + input wire pio_axis_cc_tvalid, // i, 1 + input wire pio_axis_cc_tlast , // i, 1 + input wire [`PIO_DATA_W-1:0] pio_axis_cc_tdata , // i, `PIO_DATA_W + input wire [32 :0] pio_axis_cc_tuser , // i, 33 + input wire [`PIO_KEEP_W-1:0] pio_axis_cc_tkeep , // i, `PIO_KEEP_W + output wire pio_axis_cc_tready, // o, 1 + /* -------std_pio --> pcie interface, pio part{end}------- */ + + /* -------std_pio --> pcie interface, pcie part{begin}------- */ + /* CC tuser + * | 32:1 | 0 | + * | parity | discontinue | + * | ignore | ignore | + */ + output wire st_pcie_axis_cc_tvalid, // o, 1 + output wire st_pcie_axis_cc_tlast , // o, 1 + output wire [`PIO_DATA_W-1:0] st_pcie_axis_cc_tdata , // o, `PIO_DATA_W + output wire [32 :0] st_pcie_axis_cc_tuser , // o, 33 + output wire [`PIO_KEEP_W-1:0] st_pcie_axis_cc_tkeep , // o, `PIO_KEEP_W + input wire st_pcie_axis_cc_tready // i, 1 + /* -------std_pio --> pcie interface, pcie part{begin}------- */ + +`ifdef PCIEI_APB_DBG + /* -------APB reated signal{begin}------- */ + ,input wire [`SRAM_RW_DATA_W -1:0] rw_data // i, `SRAM_RW_DATA_W + ,output wire [`CC_ASYNC_SIGNAL_W-1:0] dbg_signal // o, `CC_ASYNC_SIGNAL_W + /* -------APB reated signal{end}------- */ +`endif +); +wire pio_axis_cc_full; + +/* -------tmp store the whole rq pkt{begin}------- */ +wire fifo_out_ren ; +wire [1 + `PIO_KEEP_W + `PIO_DATA_W-1:0] fifo_out_tdata; +wire fifo_out_empty; + +wire pkt_store_wen ; +wire pkt_store_full ; +wire pkt_store_ren ; +wire [1 + `PIO_KEEP_W + `PIO_DATA_W-1:0] pkt_store_tdata; +wire pkt_store_empty; + +reg [4:0] pkt_cnt; // +/* -------tmp store the whole rq pkt{begin}------- */ + +/* -------std_pio --> pcie interface, pcie part{begin}------- */ +wire pcie_axis_cc_tvalid; +wire pcie_axis_cc_tlast ; +wire [`PIO_DATA_W-1:0] pcie_axis_cc_tdata ; +wire [`PIO_KEEP_W-1:0] pcie_axis_cc_tkeep ; +wire pcie_axis_cc_tready; +/* -------std_pio --> pcie interface, pcie part{begin}------- */ + +`ifdef PCIEI_APB_DBG +/* -------APB reated signal{begin}------- */ +wire [1:0] rtsel; +wire [1:0] wtsel; +wire [1:0] ptsel; +wire vg ; +wire vs ; +/* -------APB reated signal{end}------- */ +`endif + +//--------------------------------------------------------------------------------------------------------------------------- + +`ifdef PCIEI_APB_DBG +/* -------APB reated signal{begin}------- */ +assign {rtsel, wtsel, ptsel, vg, vs} = rw_data; + +assign dbg_signal = { // 809 + pio_axis_cc_full, // 1 + fifo_out_ren, fifo_out_tdata, fifo_out_empty, // 267 + pkt_store_wen, pkt_store_full, pkt_store_ren, pkt_store_tdata, pkt_store_empty, // 269 + pkt_cnt, // 5 + pcie_axis_cc_tvalid, pcie_axis_cc_tlast , pcie_axis_cc_tdata , pcie_axis_cc_tkeep , pcie_axis_cc_tready // 267 +}; +/* -------APB reated signal{end}------- */ +`endif + +pcieifc_async_fifo #( + .DATA_WIDTH ( 1 + `PIO_KEEP_W + `PIO_DATA_W ), + .ADDR_WIDTH ( 5 ) +) pcieifc_async_fifo ( + .wr_clk ( user_clk ), // i, 1 + .rd_clk ( pcie_clk ), // i, 1 + .wrst_n ( user_rst_n ), // i, 1 + .rrst_n ( pcie_rst_n ), // i, 1 + + .wen ( pio_axis_cc_tvalid & pio_axis_cc_tready ), // i, 1 + .din ( {pio_axis_cc_tlast, pio_axis_cc_tkeep, pio_axis_cc_tdata} ), // i, (1 + `PIO_KEEP_W + `PIO_DATA_W) + .full ( pio_axis_cc_full ), // o, 1 + + .ren ( fifo_out_ren ), // i, 1 + .dout ( fifo_out_tdata ), // o, (1 + `PIO_KEEP_W + `PIO_DATA_W) + .empty ( fifo_out_empty ) // o, 1 + +`ifdef PCIEI_APB_DBG + ,.rtsel ( rtsel ) // i, 2 + ,.wtsel ( wtsel ) // i, 2 + ,.ptsel ( ptsel ) // i, 2 + ,.vg ( vg ) // i, 1 + ,.vs ( vs ) // i, 1 +`endif +); +assign pio_axis_cc_tready = !pio_axis_cc_full; + +/* --------tmp store the whole rq pkt{begin}------- */ +assign fifo_out_ren = !pkt_store_full; +assign pkt_store_wen = !fifo_out_empty & !pkt_store_full; +pcieifc_sync_fifo #( + .DSIZE ( 1 + `PIO_KEEP_W + `PIO_DATA_W ), // 1 + 8 + 256 = 265 + .ASIZE ( 5 ) // 32 depth +) pkt_store_fifo ( + + .clk ( pcie_clk ), // i, i + .rst_n ( pcie_rst_n ), // i, i + .clr ( 1'd0 ), // i, 1 + + .wen ( pkt_store_wen ), // i, 1 + .din ( fifo_out_tdata ), // i, 1 + `PIO_KEEP_W + `PIO_DATA_W + .full ( pkt_store_full ), // o, 1 + + .ren ( pkt_store_ren ), // i, 1 + .dout ( pkt_store_tdata ), // o, 1 + `PIO_KEEP_W + `PIO_DATA_W + .empty( pkt_store_empty ) // o, 1 + +`ifdef PCIEI_APB_DBG + ,.rtsel ( 2'b0 ) // i, 2 + ,.wtsel ( 2'b0 ) // i, 2 + ,.ptsel ( 2'b0 ) // i, 2 + ,.vg ( 1'b0 ) // i, 1 + ,.vs ( 1'b0 ) // i, 1 +`endif +); + +always @(posedge pcie_clk, negedge pcie_rst_n) begin + if (~pcie_rst_n) begin + pkt_cnt <= `TD 5'd0; + end + else if (pkt_store_tdata[264] & pkt_store_ren & fifo_out_tdata[264] & pkt_store_wen) begin + pkt_cnt <= `TD pkt_cnt; + end + else if (pkt_store_tdata[264] & pkt_store_ren) begin + pkt_cnt <= `TD pkt_cnt - 5'd1; + end + else if (fifo_out_tdata[264] & pkt_store_wen) begin + pkt_cnt <= `TD pkt_cnt + 5'd1; + end +end + +assign pcie_axis_cc_tvalid = !pkt_store_empty & (pkt_cnt > 0); +assign pcie_axis_cc_tlast = pcie_axis_cc_tvalid ? pkt_store_tdata[264] : 1'd0; +assign pcie_axis_cc_tdata = pcie_axis_cc_tvalid ? pkt_store_tdata[255:0] : 256'd0; +assign pcie_axis_cc_tkeep = pcie_axis_cc_tvalid ? pkt_store_tdata[263:256] : 8'd0; + +assign pkt_store_ren = pcie_axis_cc_tvalid & pcie_axis_cc_tready; +/* --------tmp store the whole rq pkt{end}------- */ + +/* -------Read Request FIFO{begin}------- */ +st_reg #( + .TUSER_WIDTH ( 1 ), + .TDATA_WIDTH ( `PIO_DATA_W + `PIO_KEEP_W ) +) st_cc ( + .clk ( pcie_clk ), // i, 1 + .rst_n ( pcie_rst_n ), // i, 1 + + /* -------input axis-like interface{begin}------- */ + .axis_tvalid ( pcie_axis_cc_tvalid ), // i, 1 + .axis_tlast ( pcie_axis_cc_tlast ), // i, 1 + .axis_tuser ( 1'd0 ), // i, TUSER_WIDTH + .axis_tdata ( {pcie_axis_cc_tdata, pcie_axis_cc_tkeep} ), // i, TDATA_WIDTH + .axis_tready ( pcie_axis_cc_tready ), // o, 1 + /* -------input axis-like interface{end}------- */ + + /* -------output in_reg inteface{begin}------- */ + .axis_reg_tvalid ( st_pcie_axis_cc_tvalid ), // o, 1 + .axis_reg_tlast ( st_pcie_axis_cc_tlast ), // o, 1 + .axis_reg_tuser ( ), // o, TUSER_WIDTH + .axis_reg_tdata ( {st_pcie_axis_cc_tdata, st_pcie_axis_cc_tkeep} ), // o, TDATA_WIDTH + .axis_reg_tready ( st_pcie_axis_cc_tready ) //` i, 1 + /* -------output in_reg inteface{end}------- */ +); +assign st_pcie_axis_cc_tuser = 33'd0; +/* -------Read Request FIFO{end}------- */ + +endmodule diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/STD_PIO/cc_composer.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/STD_PIO/cc_composer.v new file mode 100644 index 0000000000000000000000000000000000000000..f85732c2b0d63502c153948799498c3b5588b8c6 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/STD_PIO/cc_composer.v @@ -0,0 +1,227 @@ +`timescale 1ns / 100ps +//************************************************************************* +// > File : cc_composer.v +// > Author : Kangning +// > Date : 2022-03-12 +// > Note : Interface between PCIe core and BAR space +// > Commpose AXIS interface into CC interface +//************************************************************************* + +module cc_composer #( + +) ( + + input wire clk, + input wire rst_n, + + /* -------Completer Completion{begin}------- */ + /* CC tuser + * | 32:1 | 0 | + * | parity | discontinue | + * | ignore | ignore | + */ + output wire [`PIO_DATA_W-1:0] cc_tdata , // o, `PIO_DATA_W + output wire cc_tlast , // o, 1 + output wire [`PIO_KEEP_W-1:0] cc_tkeep , // o, `PIO_KEEP_W + output wire cc_tvalid, // o, 1 + input wire cc_tready, // i, 1 + /* -------Completer Completion{end}------- */ + + /* --------PIO Response interface{begin}-------- */ + /* tuser + * | 139 | 138:136 | 135:132 | 131:128 | 127:96 | 95:0 | + * | is_wr | bar_id | first_be | last_be | aligned_addr | cc_head | + * | | | | | | | + */ + input wire [`PIO_DATA_W-1:0] s_axis_rrsp_tdata , // i, `PIO_DATA_W + input wire [`PIO_USER_W-1:0] s_axis_rrsp_tuser , // i, `PIO_USER_W + input wire s_axis_rrsp_tlast , // i, 1 + input wire s_axis_rrsp_tvalid, // i, 1 + output wire s_axis_rrsp_tready // o, 1 + /* --------PIO Response interface{end}-------- */ + +`ifdef PCIEI_APB_DBG + /* -------APB reated signal{begin}------- */ + ,input wire [31:0] dbg_sel // debug bus select + ,output wire [31:0] dbg_bus // debug bus data + /* -------APB reated signal{end}------- */ +`endif +); + +/* -------FSM relevant{begin}------- */ +localparam IDLE = 2'b01, // Wait for CQ input; store the head at this time + TRANS = 2'b10; // Input Write|Read Request; assert cq ready only in this time + +reg [1:0] cur_state; +reg [1:0] nxt_state; + +wire is_idle, is_trans; +wire j_trans, j_idle; +/* -------FSM relevant{end}------- */ + + +/* -------CC data{begin}------- */ +wire [`PIO_DATA_W-1:0] data; +reg [95:0] tmp_data; // PIO rsp data (including head) +reg is_sop; +/* -------CC data{end}------- */ + +/* -------CC Head{begin}------- */ +wire is_extra_beat; // indicate that this is the extra beat +reg has_extra_beat; // indicate that this packet has extra beat +reg [95:0] cc_head; +/* -------CC Head{end}------- */ + +/* -------Last gennerate{begin}-------- */ +wire last; +wire [`PIO_KEEP_W-1:0] keep; +reg [12 :0] dw_left; // should be larger, cause head also be added in this reg +/* -------Last gennerate{end}-------- */ + +`ifdef PCIEI_APB_DBG +/* -------APB reated signal{begin}------- */ +wire [`CC_COMPOSER_SIGNAL_W-1:0] dbg_signal_cc_composer; +/* -------APB reated signal{end}------- */ +`endif + +//--------------------------------------------------------------------------------------------------------------------------- + +`ifdef PCIEI_APB_DBG +/* -------APB reated signal{begin}------- */ + +assign dbg_bus = dbg_signal_cc_composer >> {dbg_sel, 5'd0}; + +assign dbg_signal_cc_composer = { // 481 + cur_state, nxt_state, is_idle, is_trans, j_trans, j_idle, // 8 + data, tmp_data, is_sop, // 353 + is_extra_beat, has_extra_beat, cc_head, // 98 + last, keep, dw_left // 22 +}; +/* -------APB reated signal{end}------- */ +`endif + +/* -------CC data{begin}------- */ +assign data = is_sop ? {s_axis_rrsp_tdata[159:0], cc_head} : {s_axis_rrsp_tdata[159:0], tmp_data}; +always @(posedge clk, negedge rst_n) begin + if(~rst_n) begin + tmp_data <= `TD 96'd0; + end + else if (is_trans & cc_tvalid & cc_tready & cc_tlast) begin + tmp_data <= `TD 96'd0; + end + else if (is_trans & cc_tvalid & cc_tready) begin + tmp_data <= `TD s_axis_rrsp_tdata[255:160]; + end +end +always @(posedge clk, negedge rst_n) begin + if(~rst_n) begin + is_sop <= `TD 1'd0; + end + else if (j_trans) begin + is_sop <= `TD 1'd1; + end + else if (is_trans & s_axis_rrsp_tvalid & s_axis_rrsp_tready) begin + is_sop <= `TD 1'd0; + end +end +/* -------CC data{end}------- */ + +/* -------CC head{begin}------- */ +assign is_extra_beat = has_extra_beat & cc_tlast; +/* CC head + * | Force ECRC | Attr | TC | Completer ID en | Cpl Bus | Cpl Func | Tag | Req ID | + * | 95 | 94:92 | 91:89 | 88 | 87:80 | 79:72 | 71:64 | 63:48 | + * ---------------------------------------------------------------------------------------------------- + * | R | Poisioned Cpl | Cpl Status | DW cnt | R | Locked Rd Cpl | Byte Cnt | R | AT | R | Addr[6:0] | + * | 47 | 46 | 45:43 | 42:32 |31:30| 29 | 28:16 |15:10| 9:8| 7 | 6:0 | + */ +always @(posedge clk, negedge rst_n) begin + if(~rst_n) begin + cc_head <= `TD 96'd0; + has_extra_beat <= `TD 1'd0; + end + else if (j_trans) begin + cc_head <= `TD s_axis_rrsp_tuser[95:0]; + has_extra_beat <= `TD (s_axis_rrsp_tuser[34:32] > 5); + end + else if (j_idle) begin + cc_head <= `TD 96'd0; + has_extra_beat <= `TD 1'd0; + end +end +/* -------CC head{end}------- */ + +/* -------Last gennerate{begin}-------- */ +assign last = (dw_left <= 13'd8); +assign keep = (dw_left >= 13'd8) ? 8'hFF : + (dw_left == 13'd7) ? 8'h7F : + (dw_left == 13'd6) ? 8'h3F : + (dw_left == 13'd5) ? 8'h1F : + (dw_left == 13'd4) ? 8'h0F : + (dw_left == 13'd3) ? 8'h07 : + (dw_left == 13'd2) ? 8'h03 : + (dw_left == 13'd1) ? 8'h01 : 8'h00; +always @(posedge clk, negedge rst_n) begin + if(~rst_n) begin + dw_left <= `TD 13'd0; + end + else if (j_trans) begin + dw_left <= `TD {2'd0, s_axis_rrsp_tuser[42:32]} + 13'd3; + end + else if (is_trans) begin + dw_left <= `TD dw_left - 13'd8; + end +end +/* -------Last gennerate{end}-------- */ + +/* -------{CC Composer FSM}begin------- */ +/******************** Stage 1: State Register **********************/ + +assign is_idle = ( cur_state == IDLE ); +assign is_trans = ( cur_state == TRANS ); +assign j_trans = is_idle & s_axis_rrsp_tvalid; +assign j_idle = is_trans & cc_tvalid & cc_tready & cc_tlast; + +always @(posedge clk, negedge rst_n) begin + if(~rst_n) + cur_state <= `TD IDLE; + else + cur_state <= `TD nxt_state; +end + +/******************** Stage 2: State Transition **********************/ +always @(*) begin + case(cur_state) + IDLE: begin + if (s_axis_rrsp_tvalid) begin + nxt_state = TRANS; + end + else begin + nxt_state = IDLE; + end + end + TRANS: begin + if (cc_tvalid & cc_tready & cc_tlast) begin + nxt_state = IDLE; + end + else begin + nxt_state = TRANS; + end + end + default: begin + nxt_state = IDLE; + end + endcase +end +/******************** Stage 3: Output **********************/ + +/* -------CC Interface{begin}------- */ +assign cc_tdata = is_trans ? data : {`PIO_DATA_W{1'd0}}; +assign cc_tlast = is_trans ? last : 1'd0; +assign cc_tkeep = is_trans ? keep : {`PIO_KEEP_W{1'd0}}; +assign cc_tvalid = is_trans ? s_axis_rrsp_tvalid : 1'd0; + +assign s_axis_rrsp_tready = is_trans ? (is_extra_beat ? 1'd0 : cc_tready) : 1'd0; +/* -------CC Interface{end}------- */ +//------------------------------{CC Composer FSM}end------------------------------// +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/STD_PIO/cq_parser.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/STD_PIO/cq_parser.v new file mode 100644 index 0000000000000000000000000000000000000000..7cad4caf754a65a9d21d8fe7f531f16854348c2d --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/STD_PIO/cq_parser.v @@ -0,0 +1,354 @@ +`timescale 1ns / 100ps +//************************************************************************* +// > File : cq_parser.v +// > Author : Kangning +// > Date : 2022-03-11 +// > Note : Parser CQ interface into AXIS interface +//************************************************************************* + +module cq_parser #( + +) ( + input wire clk, + input wire rst_n, + + /* -------Completer Requester{begin}------- */ + /* CQ tuser + * | 84:53 | 52:45 | 44:43 | 42 | 41 | 40 | 39:8 | 7:4 | 3:0 | + * | parity | tph_st_tag | tph_type | tph_present | discontinue | sop | byte_en | last_be | first_be | + * | 0 | 0 | 0 | | | | ignore | | | + */ + input wire [84 :0] cq_tuser , // i, 85 + input wire [`PIO_DATA_W-1:0] cq_tdata , // i, `PIO_DATA_W + input wire cq_tlast , // i, 1 + input wire cq_tvalid, // i, 1 + output wire cq_tready, // o, 1 + /* -------Completer Requester{end}------- */ + + /* --------PIO Request intterface{begin}-------- */ + /* tuser + * | 139 | 138:136 | 135:132 | 131:128 | 127:96 | 95:0 | + * | is_wr | bar_id | first_be | last_be | aligned_addr | cc_head | + * | | | | | | | + */ + output wire m_axis_req_tvalid, // o, 1 + output wire m_axis_req_tlast , // o, 1 + output wire [`PIO_DATA_W-1:0] m_axis_req_tdata , // o, `PIO_DATA_W + output wire [`PIO_USER_W-1:0] m_axis_req_tuser , // o, `PIO_USER_W + input wire m_axis_req_tready // i, 1 + /* --------PIO Request intterface{end}-------- */ + +`ifdef PCIEI_APB_DBG + /* -------APB reated signal{begin}------- */ + ,input wire [31:0] dbg_sel // debug bus select + ,output wire [31:0] dbg_bus // debug bus data + /* -------APB reated signal{end}------- */ +`endif +); + +/* -------FSM relevant{begin}------- */ +localparam IDLE = 4'b0001, // Idle state + TRANS = 4'b0010, // Trans state + DEALIGNED_LAST = 4'b0100, // axis_req_last and cq_last assert at different time + ALIGNED_LAST = 4'b1000; // axis_req_last assert when cq_last asserts + +reg [3:0] cur_state; +reg [3:0] nxt_state; + +wire is_idle, is_trans, is_dealigned_last, is_aligned_last; + +wire is_recv_next_pkt ; // next pkt head is received in next cycle +wire is_clear_this_pkt; // clear this pkt head in next cycle +wire is_trans_this_pkt; // trans one beat of this pkt in next cycle +/* -------FSM relevant{end}------- */ + +/* --------CQ REQ tmp data{begin}-------- */ +reg [127:0] tmp_data; +/* --------CQ REQ tmp data{end}-------- */ + +/* -------Head Gen{begin}------- */ +wire [ 2:0] cq_bar_id; +wire cq_is_wr; +wire [10:0] cq_dw_len; +wire [63:0] cq_addr; +wire [ 3:0] cq_first_be, cq_last_be; +wire [ 2:0] last_empty; + +reg [ 2:0] bar_id; +reg [ 3:0] first_be; +reg [ 3:0] last_be; + +reg [ 2:0] attrs; +reg [ 2:0] tc; +reg [ 7:0] trgt_func; +reg [ 7:0] tag; +reg [15:0] req_id; +reg [12:0] byte_cnt; +reg [ 1:0] at; +reg is_wr; +reg [63:0] addr; // address of bar space + +wire [95:0] cc_head; + +wire [`PIO_USER_W-1:0] axis_tuser; +wire [`PIO_USER_W-1:0] demux_tuser; // axis_tuser, only used for channel selection +/* -------Head Gen{end}------- */ + +/* -------axis_dw_left calc{begin}------- */ +reg [10:0] axis_dw_left; +/* -------axis_dw_left calc{end}------- */ + +`ifdef PCIEI_APB_DBG +/* -------APB reated signal{begin}------- */ +wire [`CQ_PARSER_SIGNAL_W-1:0] dbg_signal_cq_parser; +/* -------APB reated signal{end}------- */ +`endif + +//--------------------------------------------------------------------------------------------------------------------------- + +`ifdef PCIEI_APB_DBG +/* -------APB reated signal{begin}------- */ + +assign dbg_bus = dbg_signal_cq_parser >> {dbg_sel, 5'd0}; + +assign dbg_signal_cq_parser = { // 745 + cur_state, nxt_state, // 8 + is_idle, is_trans, is_dealigned_last, is_aligned_last, // 4 + is_recv_next_pkt , is_clear_this_pkt, is_trans_this_pkt, // 3 + tmp_data, // 128 + cq_bar_id, cq_is_wr , cq_dw_len, cq_addr, cq_first_be, cq_last_be, last_empty, // 86 + bar_id, first_be, last_be, // 11 + attrs, tc, trgt_func, tag, req_id, byte_cnt, at, is_wr, addr, // 118 + cc_head, // 96 + axis_tuser, demux_tuser, // 280 + axis_dw_left // 11 +}; +/* -------APB reated signal{end}------- */ +`endif + +/* -------CQ REQ tmp data{begin}------- */ +always @(posedge clk, negedge rst_n) begin + if(~rst_n) begin + tmp_data <= `TD 128'd0; + end + else if (is_clear_this_pkt) begin + tmp_data <= `TD 128'd0; + end + else if (is_recv_next_pkt | is_trans_this_pkt) begin + tmp_data <= `TD cq_tdata[255:128]; + end +end +/* -------CQ tmp data{end}------- */ + +/* -------Head Gen{begin}------- */ + +assign cq_is_wr = cq_tdata[78:75] == 4'b0001; +assign cq_dw_len = cq_tdata[74:64]; +assign cq_addr = {cq_tdata[63:2], 2'b0}; +assign cq_bar_id = cq_tdata[114:112]; +assign cq_first_be = cq_tuser[3:0]; +assign cq_last_be = cq_tuser[7:4]; + +assign last_empty = (cq_dw_len == 1) ? + (cq_first_be[3] ? 0 : + cq_first_be[2] ? 1 : + cq_first_be[1] ? 2 : 3) + : + (cq_last_be[3] ? 0 : + cq_last_be[2] ? 1 : + cq_last_be[1] ? 2 : 3); + +/* | Force ECRC | Attr | TC | Completer ID en | Cpl Bus | Cpl Func | Tag | Req ID | + * | 95 | 94:92 | 91:89 | 88 | 87:80 | 79:72 | 71:64 | 63:48 | + * ---------------------------------------------------------------------------------------------------- + * | R | Poisioned Cpl | Cpl Status | DW cnt | R | Locked Rd Cpl | Byte Cnt | R | AT | R | Addr[6:0] | + * | 47 | 46 | 45:43 | 42:32 |31:30| 29 | 28:16 |15:10| 9:8| 7 | 6:0 | + */ +assign cc_head = {1'b0, attrs, tc, 1'b0, 8'b0, trgt_func, tag, req_id, + 1'b0, 1'b0, 3'b0, byte_cnt[12:2], 2'b0, 1'b0, byte_cnt, 6'b0, at, 1'b0, addr[6:0]}; + +/* tuser + * | 139 | 138:136 | 135:132 | 131:128 | 127:96 | 95:0 | + * | is_wr | bar_id | first_be | last_be | aligned_addr | cc_head | + * | | | | | | | + */ +assign axis_tuser = {is_wr, bar_id, first_be, last_be, addr[31:0], cc_head}; +assign demux_tuser = {cq_is_wr, cq_bar_id, 4'd0, 4'd0, cq_addr[31:0], 96'd0}; + +always @(posedge clk, negedge rst_n) begin + if(~rst_n) begin + bar_id <= `TD 0; + first_be <= `TD 0; + last_be <= `TD 0; + + attrs <= `TD 0; + tc <= `TD 0; + trgt_func <= `TD 0; + tag <= `TD 0; + req_id <= `TD 0; + byte_cnt <= `TD 0; + at <= `TD 0; + is_wr <= `TD 0; + + addr <= `TD 64'd0; + end + else if (is_clear_this_pkt) begin + bar_id <= `TD 0; + first_be <= `TD 0; + last_be <= `TD 0; + + attrs <= `TD 0; + tc <= `TD 0; + trgt_func <= `TD 0; + tag <= `TD 0; + req_id <= `TD 0; + byte_cnt <= `TD 0; + at <= `TD 0; + is_wr <= `TD 0; + + addr <= `TD 64'd0; + end + else if (is_recv_next_pkt) begin + bar_id <= `TD cq_bar_id; + first_be <= `TD cq_tuser[3:0]; + last_be <= `TD cq_tuser[7:4]; + + attrs <= `TD cq_tdata[126:124]; + tc <= `TD cq_tdata[123:121]; + trgt_func <= `TD {5'b0, cq_tdata[106:104]}; + tag <= `TD cq_tdata[103:96]; + req_id <= `TD cq_tdata[95:80]; + byte_cnt <= `TD {cq_dw_len, 2'd0} - last_empty; + at <= `TD cq_tdata[1:0]; + is_wr <= `TD cq_is_wr; + + addr <= `TD cq_addr; + end +end +/* ------Head Gen{end}------- */ + +/* -------axis_dw_left calc{begin}------- */ +always @(posedge clk, negedge rst_n) begin + if(~rst_n) begin + axis_dw_left <= `TD 0; + end + else if (is_clear_this_pkt) begin // clear the info related to the pkt + axis_dw_left <= `TD 0; + end + else if (is_recv_next_pkt & cq_is_wr) begin // recv next pkt in dealigned_last && in idle + axis_dw_left <= `TD cq_dw_len; + end + else if (is_trans & m_axis_req_tvalid & m_axis_req_tready) begin + axis_dw_left <= `TD axis_dw_left - 8; + end +end +/* -------axis_dw_left calc{end}------- */ + +/* -------{CQ Parser FSM}begin------- */ +/******************** Stage 1: State Register **********************/ + +assign is_idle = (cur_state == IDLE ); +assign is_trans = (cur_state == TRANS ); +assign is_dealigned_last = (cur_state == DEALIGNED_LAST); +assign is_aligned_last = (cur_state == ALIGNED_LAST ); + +assign is_recv_next_pkt = (is_idle & cq_tvalid ) | + (is_dealigned_last & m_axis_req_tvalid & m_axis_req_tready & cq_tvalid); +assign is_clear_this_pkt = (is_dealigned_last & m_axis_req_tvalid & m_axis_req_tready & !cq_tvalid) | + (is_aligned_last & m_axis_req_tvalid & m_axis_req_tready ); +assign is_trans_this_pkt = (is_trans & m_axis_req_tvalid & m_axis_req_tready); + +always @(posedge clk, negedge rst_n) begin + if(~rst_n) + cur_state <= `TD IDLE; + else + cur_state <= `TD nxt_state; +end + +/******************** Stage 2: State Transition **********************/ +always @(*) begin + case(cur_state) + IDLE: begin + if (cq_tvalid & cq_tlast) begin + nxt_state = DEALIGNED_LAST; + end + else if (cq_tvalid & cq_is_wr & (cq_dw_len <= 8)) begin + nxt_state = ALIGNED_LAST; + end + else if (cq_tvalid) begin + nxt_state = TRANS; + end + else begin + nxt_state = IDLE; + end + end + TRANS: begin + if (m_axis_req_tvalid & m_axis_req_tready) begin + if ((8 < axis_dw_left) & (axis_dw_left <= 12)) begin + nxt_state = DEALIGNED_LAST; + end + else if ((12 < axis_dw_left) & (axis_dw_left <= 16)) begin + nxt_state = ALIGNED_LAST; + end + else begin + nxt_state = TRANS; + end + end + else begin + nxt_state = TRANS; + end + end + DEALIGNED_LAST: begin + if (m_axis_req_tvalid & m_axis_req_tready) begin + + // Same as the procedure in IDLE + if (cq_tvalid & cq_tlast) begin + nxt_state = DEALIGNED_LAST; + end + else if (cq_tvalid & cq_is_wr & (cq_dw_len <= 8)) begin + nxt_state = ALIGNED_LAST; + end + else if (cq_tvalid) begin + nxt_state = TRANS; + end + else begin + nxt_state = IDLE; + end + end + else begin + nxt_state = DEALIGNED_LAST; + end + end + ALIGNED_LAST: begin + if (m_axis_req_tvalid & m_axis_req_tready) begin + nxt_state = IDLE; + end + else begin + nxt_state = ALIGNED_LAST; + end + end + default: begin + nxt_state = IDLE; + end + endcase +end +/******************** Stage 3: Output **********************/ + +assign m_axis_req_tvalid = (is_idle & cq_tvalid) | // valid is asserted in idle state, but only demux_tuser is valid to choose correct channel + (is_trans & cq_tvalid) | + (is_dealigned_last ) | + (is_aligned_last & cq_tvalid); +assign m_axis_req_tlast = m_axis_req_tvalid & (is_dealigned_last | is_aligned_last); +assign m_axis_req_tdata = ({`PIO_DATA_W{is_dealigned_last}} & {128'd0, tmp_data} ) | + ({`PIO_DATA_W{is_aligned_last }} & {cq_tdata[127:0], tmp_data}) | + ({`PIO_DATA_W{is_trans }} & {cq_tdata[127:0], tmp_data}); +assign m_axis_req_tuser = ({`PIO_USER_W{is_idle }} & demux_tuser) | + ({`PIO_USER_W{is_trans | is_dealigned_last | is_aligned_last}} & axis_tuser ); + +assign cq_tready = is_idle | + (is_trans & m_axis_req_tready) | + (is_dealigned_last & m_axis_req_tready) | + (is_aligned_last & m_axis_req_tready); + +/* -------{CQ Parser FSM}end------- */ +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/STD_PIO/eth_cfg.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/STD_PIO/eth_cfg.v new file mode 100644 index 0000000000000000000000000000000000000000..33dd7aa9088ce8e175596ff60bd40ecabffe44fe --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/STD_PIO/eth_cfg.v @@ -0,0 +1,321 @@ +`timescale 1ns / 100ps +//************************************************************************* +// > File : eth_cfg.v +// > Author : Kangning +// > Date : 2022-06-10 +// > Note : eth_cfg, Provide interface for Ethernet bar space access. +//************************************************************************* + + +module eth_cfg #( + parameter AXIL_DATA_WIDTH = 32 , + parameter AXIL_ADDR_WIDTH = 24 , + + parameter AXIL_STRB_WIDTH = (AXIL_DATA_WIDTH/8) +) ( + + input wire clk , // i, 1 + input wire rst_n , // i, 1 + + /* --------Req Channel{begin}-------- */ + /* pio_head + * | 131 | 130:128 | 127:96 | 95:0 | + * | is_wr | bar_id | addr | cc_head | + */ + input wire [`PIO_DATA_W-1:0] pio_eth_req_data , // i, `PIO_DATA_W + input wire [`PIO_HEAD_W-1:0] pio_eth_req_head , // i, `PIO_HEAD_W + input wire [1 -1:0] pio_eth_req_last , // i, 1 + input wire [1 -1:0] pio_eth_req_valid , // i, 1 + output wire [1 -1:0] pio_eth_req_ready , // o, 1 + /* --------Req Channel{end}-------- */ + + /* --------Rsp Channel{begin}-------- */ + /* pio_head + * | 131 | 130:128 | 127:96 | 95:0 | + * | is_wr | bar_id | addr | cc_head | + */ + output wire [`PIO_DATA_W-1:0] st_pio_eth_rrsp_data , // o, `PIO_DATA_W + output wire [`PIO_HEAD_W-1:0] st_pio_eth_rrsp_head , // o, `PIO_HEAD_W + output wire [1 -1:0] st_pio_eth_rrsp_last , // o, 1 + output wire [1 -1:0] st_pio_eth_rrsp_valid, // o, 1 + input wire [1 -1:0] st_pio_eth_rrsp_ready, // i, 1 + /* -------Rsp Channel{end}-------- */ + + /* --------Interact with Ethernet BAR{begin}------- */ + output wire [AXIL_ADDR_WIDTH-1:0] m_axil_awaddr , + output wire m_axil_awvalid, + input wire m_axil_awready, + + output wire [AXIL_DATA_WIDTH-1:0] m_axil_wdata , + output wire [AXIL_STRB_WIDTH-1:0] m_axil_wstrb , // byte select + output wire m_axil_wvalid, + input wire m_axil_wready, + + input wire m_axil_bvalid, + output wire m_axil_bready, + + output wire [AXIL_ADDR_WIDTH-1:0] m_axil_araddr , + output wire m_axil_arvalid, + input wire m_axil_arready, + + input wire [AXIL_DATA_WIDTH-1:0] m_axil_rdata , + input wire m_axil_rvalid, + output wire m_axil_rready + /* --------Interact with Ethernet BAR{end}------- */ + +`ifdef PCIEI_APB_DBG + /* -------APB reated signal{begin}------- */ + ,input wire [31:0] dbg_sel // debug bus select + ,output wire [31:0] dbg_bus // debug bus data + /* -------APB reated signal{end}------- */ +`endif +); + +/* --------Related to FIFO{begin}-------- */ +/* pio_head + * | 131 | 130:128 | 127:96 | 95:0 | + * | is_wr | bar_id | addr | cc_head | + */ +wire req_valid, req_ready; +wire [`PIO_DATA_W-1:0] req_data; // `PIO_DATA_W +wire [`PIO_HEAD_W-1:0] req_head; // `PIO_HEAD_W + +wire eth_full, eth_empty; +wire is_wr; +wire [31:0] addr; +wire [2 :0] bar_id; +wire [13-1:0] byte_len; +/* --------Related to FIFO{end}-------- */ + +/* -------FSM relevant{begin}------- */ +localparam IDLE = 6'b00_0001, // Wait for input + EN_AWRSP = 6'b00_0010, // Wait for Ethernet Addr Write rsp + EN_WRSP = 6'b00_0100, // Wait for Ethernet Write rsp + EN_WBRSP = 6'b00_1000, // Wait for Ethernet Write back rsp + EN_ARRSP = 6'b01_0000, // Wait for Ethernet Addr Read rsp + EN_RRSP = 6'b10_0000; // Wait for Ethernet Read rsp + +reg [5:0] cur_state; +reg [5:0] nxt_state; + +wire is_idle, is_en_awrsp, is_en_wrsp, is_en_wbrsp, is_en_arrsp, is_en_rrsp; +/* -------FSM relevant{end}------- */ + +/* --------Rsp Channel{begin}-------- */ +/* pio_head + * | 131 | 130:128 | 127:96 | 95:0 | + * | is_wr | bar_id | addr | cc_head | + */ +wire [`PIO_DATA_W-1:0] pio_eth_rrsp_data ; +wire [`PIO_HEAD_W-1:0] pio_eth_rrsp_head ; +wire [1 -1:0] pio_eth_rrsp_last ; +wire [1 -1:0] pio_eth_rrsp_valid; +wire [1 -1:0] pio_eth_rrsp_ready; +/* -------Rsp Channel{end}-------- */ + +`ifdef PCIEI_APB_DBG +/* -------APB reated signal{begin}------- */ +wire [`ETH_CFG_SIGNAL_W-1:0] dbg_signal_eth_cfg; +/* -------APB reated signal{end}------- */ +`endif + +//--------------------------------------------------------------------------------------------------------------------------- + +`ifdef PCIEI_APB_DBG +/* -------APB reated signal{begin}------- */ + +assign dbg_bus = dbg_signal_eth_cfg >> {dbg_sel, 5'd0}; + +assign dbg_signal_eth_cfg = { // 850 + req_valid, req_ready, req_data, req_head, // 390 + eth_full, eth_empty, is_wr, addr, bar_id, byte_len, // 51 + cur_state, nxt_state, // 12 + is_idle, is_en_awrsp, is_en_wrsp, is_en_wbrsp, is_en_arrsp, is_en_rrsp, // 6 + pio_eth_rrsp_data , pio_eth_rrsp_head , pio_eth_rrsp_last , pio_eth_rrsp_valid, pio_eth_rrsp_ready // 391 +}; +/* -------APB reated signal{end}------- */ +`endif + +/* -------ETH CFG Fifo{begin}------- */ +pcieifc_sync_fifo #( + .DSIZE ( `PIO_HEAD_W + `PIO_DATA_W ), // 132+256=388 + .ASIZE ( 2 ) // 4 depth +) eth_cfg_sync_fifo ( + .clk ( clk ), // i, 1 + .rst_n ( rst_n ), // i, 1 + .clr ( 1'd0 ), // i, 1 + + .wen ( pio_eth_req_valid & pio_eth_req_ready ), // i, 1 + .din ( {pio_eth_req_head, pio_eth_req_data} ), // i, DSIZE + .full ( eth_full ), // o, 1 + + .ren ( req_ready ), // i, 1 + .dout ( {req_head, req_data} ), // o, DSIZE + .empty ( eth_empty ) // o, 1 + +`ifdef PCIEI_APB_DBG + ,.rtsel ( 2'b0 ) // i, 2 + ,.wtsel ( 2'b0 ) // i, 2 + ,.ptsel ( 2'b0 ) // i, 2 + ,.vg ( 1'b0 ) // i, 1 + ,.vs ( 1'b0 ) // i, 1 +`endif +); +assign req_valid = !eth_empty; +assign pio_eth_req_ready = !eth_full; + +assign is_wr = req_head[131]; +assign addr = req_head[127:96]; +assign bar_id = req_head[130:128]; +assign byte_len = req_head[28:16]; +/* --------ETH CFG Fifo{end}-------- */ + +//------------------------------{ETH BAR Space Access Engine FSM}begin------------------------------// +/******************** Stage 1: State Register **********************/ + +assign is_idle = ( cur_state == IDLE ); +assign is_en_awrsp = ( cur_state == EN_AWRSP ); +assign is_en_wrsp = ( cur_state == EN_WRSP ); +assign is_en_wbrsp = ( cur_state == EN_WBRSP ); +assign is_en_arrsp = ( cur_state == EN_ARRSP ); +assign is_en_rrsp = ( cur_state == EN_RRSP ); + +always @(posedge clk, negedge rst_n) begin + if(~rst_n) + cur_state <= `TD IDLE; + else + cur_state <= `TD nxt_state; +end + +/******************** Stage 2: State Transition **********************/ +always @(*) begin + case(cur_state) + IDLE: begin + if (req_valid & is_wr) begin + nxt_state = EN_AWRSP; + end + else if (req_valid & !is_wr) begin + nxt_state = EN_ARRSP; + end + else begin + nxt_state = IDLE; + end + end + EN_AWRSP: begin + if (m_axil_awvalid & m_axil_awready) begin + nxt_state = EN_WRSP; + end + else begin + nxt_state = EN_AWRSP; + end + end + EN_WRSP: begin + if (m_axil_wvalid & m_axil_wready) begin + nxt_state = EN_WBRSP; + end + else begin + nxt_state = EN_WRSP; + end + end + EN_WBRSP: begin + if (m_axil_bvalid & m_axil_bready) begin + nxt_state = IDLE; + end + else begin + nxt_state = EN_WBRSP; + end + end + EN_ARRSP: begin + if (m_axil_arvalid & m_axil_arready) begin + nxt_state = EN_RRSP; + end + else begin + nxt_state = EN_ARRSP; + end + end + EN_RRSP: begin + if (m_axil_rvalid & m_axil_rready) begin + nxt_state = IDLE; + end + else begin + nxt_state = EN_RRSP; + end + end + default: begin + nxt_state = IDLE; + end + endcase +end +/******************** Stage 3: Output **********************/ + +// Ethernet BAR Space Access Interface +assign m_axil_awvalid = is_en_awrsp; +assign m_axil_awaddr = addr[23:0] ; + +assign m_axil_wvalid = is_en_wrsp; +assign m_axil_wdata = req_data ; +assign m_axil_wstrb = (byte_len == 1) ? 4'h1 : + (byte_len == 2) ? 4'h3 : + (byte_len == 3) ? 4'h7 : 4'hF; + +assign m_axil_bready = is_en_wbrsp; + +assign m_axil_arvalid = is_en_arrsp; +assign m_axil_araddr = addr[23:0] ; + +assign m_axil_rready = pio_eth_rrsp_ready; + +// Req Channel +assign req_ready = (is_en_rrsp & pio_eth_rrsp_valid & pio_eth_rrsp_ready) | + (is_en_wrsp & m_axil_wvalid & m_axil_wready ); + +// Rsp Channel +/* pio_head + * | 131 | 130:128 | 127:96 | 95:0 | + * | is_wr | bar_id | addr | cc_head | + */ +assign pio_eth_rrsp_valid = is_en_rrsp & m_axil_rvalid; +assign pio_eth_rrsp_last = pio_eth_rrsp_valid; +assign pio_eth_rrsp_head = pio_eth_rrsp_valid ? req_head : 0; +assign pio_eth_rrsp_data = pio_eth_rrsp_valid ? m_axil_rdata : 0; +//------------------------------{ETH BAR Space Access Engine FSM}end------------------------------// + +st_reg #( + .TUSER_WIDTH ( `PIO_HEAD_W ), + .TDATA_WIDTH ( `PIO_DATA_W ) +) uar_db_st_reg ( + .clk ( clk ), // i, 1 + .rst_n ( rst_n ), // i, 1 + + /* -------input axis-like interface{begin}------- */ + .axis_tvalid ( pio_eth_rrsp_valid ), // i, 1 + .axis_tlast ( pio_eth_rrsp_last ), // i, 1 + .axis_tuser ( pio_eth_rrsp_head ), // i, TUSER_WIDTH + .axis_tdata ( pio_eth_rrsp_data ), // i, TDATA_WIDTH + .axis_tready ( pio_eth_rrsp_ready ), // o, 1 + /* -------input axis-like interface{end}------- */ + + /* -------output st_reg inteface{begin}------- */ + .axis_reg_tvalid ( st_pio_eth_rrsp_valid ), // o, 1 + .axis_reg_tlast ( st_pio_eth_rrsp_last ), // o, 1 + .axis_reg_tuser ( st_pio_eth_rrsp_head ), // o, TUSER_WIDTH + .axis_reg_tdata ( st_pio_eth_rrsp_data ), // o, TDATA_WIDTH + .axis_reg_tready ( st_pio_eth_rrsp_ready ) // i, 1 + /* -------output st_reg inteface{end}------- */ +); + +`ifdef ILA_ON +// ila_eth_cfg_ncsg_rd ila_eth_cfg_ncsg_rd_inst( +// .clk(clk), +// .probe0(m_axil_araddr) , +// .probe1(m_axil_arvalid), +// .probe2(m_axil_arready), + +// .probe3(m_axil_rdata) , +// .probe4(m_axil_rvalid), +// .probe5(m_axil_rready) + +// ); +`endif + +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/STD_PIO/p2p_access.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/STD_PIO/p2p_access.v new file mode 100644 index 0000000000000000000000000000000000000000..ed3ab36be4dcd8740498298f4c9bd5e0a9665ec4 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/STD_PIO/p2p_access.v @@ -0,0 +1,360 @@ +`timescale 1ns / 100ps +//************************************************************************* +// > File : p2p_access.v +// > Author : Kangning +// > Date : 2022-06-10 +// > Note : Interface for p2p access. +//************************************************************************* + +module p2p_access #( + +) ( + input wire clk , // i, 1 + input wire rst_n, // i, 1 + + /* --------Req Channel{begin}-------- */ + /* req_head + * | 131 | 130:128 | 127:96 | 95:0 | + * | is_wr | bar_id | addr | cc_head | + */ + input wire [1 -1:0] pio_p2p_mem_req_valid, // i, 1 + input wire [1 -1:0] pio_p2p_mem_req_last , // i, 1 + input wire [`PIO_DATA_W-1:0] pio_p2p_mem_req_data , // i, `PIO_DATA_W + input wire [`PIO_HEAD_W-1:0] pio_p2p_mem_req_head , // i, `PIO_HEAD_W + output wire [1 -1:0] pio_p2p_mem_req_ready, // o, 1 + /* --------Req Channel{end}-------- */ + + /* --------Req Channel{begin}-------- */ + /* req_head + * | 131 | 130:128 | 127:96 | 95:0 | + * | is_wr | bar_id | addr | cc_head | + */ + input wire [1 -1:0] pio_p2p_cfg_req_valid, // i, 1 + input wire [1 -1:0] pio_p2p_cfg_req_last , // i, 1 + input wire [`PIO_DATA_W-1:0] pio_p2p_cfg_req_data , // i, `PIO_DATA_W + input wire [`PIO_HEAD_W-1:0] pio_p2p_cfg_req_head , // i, `PIO_HEAD_W + output wire [1 -1:0] pio_p2p_cfg_req_ready, // o, 1 + /* --------Req Channel{end}-------- */ + + /* --------Rsp Channel{begin}-------- */ + /* req_head + * | 131 | 130:128 | 127:96 | 95:0 | + * | is_wr | bar_id | addr | cc_head | + */ + output wire [1 -1:0] pio_p2p_rrsp_valid, // o, 1 + output wire [1 -1:0] pio_p2p_rrsp_last , // o, 1 + output wire [`PIO_DATA_W-1:0] pio_p2p_rrsp_data , // o, `PIO_DATA_W + output wire [`PIO_HEAD_W-1:0] pio_p2p_rrsp_head , // o, `PIO_HEAD_W + input wire [1 -1:0] pio_p2p_rrsp_ready, // 1, 1 + /* --------Rsp Channel{end}-------- */ + + /* --------P2P Configuration Channel{begin}-------- */ + /* p2p_req head + * | 127 | 126:64 | 63:32 | 31:13 | 12:0 | + * | is_wr | Reserved | addr | Reserved | byte_len | + */ + output wire [1 -1:0] p2p_cfg_req_valid, // o, 1 + output wire [1 -1:0] p2p_cfg_req_last , // o, 1 + output wire [`PIO_DATA_W-1:0] p2p_cfg_req_data , // o, `PIO_DATA_W + output wire [`P2P_HEAD_W-1:0] p2p_cfg_req_head , // o, `P2P_HEAD_W + input wire [1 -1:0] p2p_cfg_req_ready, // i, 1 + + input wire [1 -1:0] p2p_cfg_rrsp_valid, // i, 1 + input wire [1 -1:0] p2p_cfg_rrsp_last , // i, 1 + input wire [`PIO_DATA_W-1:0] p2p_cfg_rrsp_data , // i, `PIO_DATA_W + output wire [1 -1:0] p2p_cfg_rrsp_ready, // o, 1 + /* --------P2P Configuration Channel{end}-------- */ + + /* -------P2P Memory Access Channel{begin}-------- */ + /* p2p_req head + * | 127 | 126:64 | 63:32 | 31:13 | 12:0 | + * | is_wr | Reserved | addr | Reserved | byte_len | + */ + output wire [1 -1:0] p2p_mem_req_valid, // o, 1 + output wire [1 -1:0] p2p_mem_req_last , // o, 1 + output wire [`PIO_DATA_W-1:0] p2p_mem_req_data , // o, `PIO_DATA_W + output wire [`P2P_HEAD_W-1:0] p2p_mem_req_head , // o, `P2P_HEAD_W + input wire [1 -1:0] p2p_mem_req_ready // i, 1 + /* -------P2P Memory Access Channel{end}-------- */ + +`ifdef PCIEI_APB_DBG + /* -------APB reated signal{begin}------- */ + ,input wire [31:0] dbg_sel // debug bus select + ,output wire [31:0] dbg_bus // debug bus data + /* -------APB reated signal{end}------- */ +`endif +); + +wire p2p_full, p2p_empty; + +/* --------Input Head parser{begin}-------- */ +wire [12:0] p2p_mem_byte_cnt; +wire [31:0] p2p_mem_addr; + +wire p2p_cfg_is_wr; // Valid even in idle state + +wire [12:0] p2p_cfg_byte_cnt; +wire [31:0] p2p_cfg_addr; +reg [`PIO_HEAD_W-1:0] cfg_req_head; +wire [`PIO_HEAD_W-1:0] cfg_rrsp_head; +/* --------Input Head parser{end}-------- */ + +/* -------Generated stream signal{begin}------- */ +wire [1 -1:0] in_cfg_req_valid; +wire [1 -1:0] in_cfg_req_last ; +wire [`P2P_HEAD_W-1:0] in_cfg_req_head ; +wire [`PIO_DATA_W-1:0] in_cfg_req_data ; +wire [1 -1:0] in_cfg_req_ready; + +wire [1 -1:0] in_mem_req_valid; +wire [1 -1:0] in_mem_req_last ; +wire [`P2P_HEAD_W-1:0] in_mem_req_head ; +wire [`PIO_DATA_W-1:0] in_mem_req_data ; +wire [1 -1:0] in_mem_req_ready; +/* -------Generated stream signal{end}------- */ + + +/* --------Related to FSM{begin}-------- */ +localparam IDLE = 4'b0001, + TRANS_WREQ_CFG = 4'b0010, // Supports arbitrary write size + TRANS_RREQ_CFG = 4'b0100, // Supports only 64-bit read + TRANS_RRSP_CFG = 4'b1000; // Supports only 64-bit read + +reg [3:0] cur_state; +reg [3:0] nxt_state; + +wire is_idle, is_trans_wreq_cfg, is_trans_rreq_cfg, is_trans_rrsp_cfg; +wire j_idle, j_trans_wreq_cfg, j_trans_rreq_cfg, j_trans_rrsp_cfg; +/* --------Related to FSM{end}-------- */ + +`ifdef PCIEI_APB_DBG +/* -------APB reated signal{begin}------- */ +wire [`P2P_ACCESS_SIGNAL_W-1:0] dbg_signal_p2p_access; +/* -------APB reated signal{end}------- */ +`endif + +//--------------------------------------------------------------------------------------------------------------------------- + +`ifdef PCIEI_APB_DBG +/* -------APB reated signal{begin}------- */ + +assign dbg_bus = dbg_signal_p2p_access >> {dbg_sel, 5'd0}; + +assign dbg_signal_p2p_access = { // 1147 + p2p_full, p2p_empty, // 2 + p2p_mem_byte_cnt, p2p_mem_addr, // 45 + p2p_cfg_is_wr, // 1 + p2p_cfg_byte_cnt, p2p_cfg_addr, cfg_req_head, cfg_rrsp_head, // 309 + in_cfg_req_valid, in_cfg_req_last , in_cfg_req_head , in_cfg_req_data , in_cfg_req_ready, // 387 + in_mem_req_valid, in_mem_req_last , in_mem_req_head , in_mem_req_data , in_mem_req_ready, // 387 + cur_state, nxt_state, // 8 + is_idle, is_trans_wreq_cfg, is_trans_rreq_cfg, is_trans_rrsp_cfg, // 4 + j_idle, j_trans_wreq_cfg, j_trans_rreq_cfg, j_trans_rrsp_cfg // 4 +}; +/* -------APB reated signal{end}------- */ +`endif + +/* -------P2P CFG Fifo{begin}------- */ +pcieifc_sync_fifo #( + .DSIZE ( `PIO_HEAD_W ), // 132 + .ASIZE ( 2 ) // 4 depth +) p2p_cfg_sync_fifo ( + .clk ( clk ), // i, 1 + .rst_n ( rst_n ), // i, 1 + .clr ( 1'd0 ), // i, 1 + + .wen ( is_trans_rreq_cfg & in_cfg_req_valid & in_cfg_req_ready ), // i, 1 + .din ( cfg_req_head ), // i, DSIZE + .full ( p2p_full ), // o, 1 + + .ren ( is_trans_rrsp_cfg & pio_p2p_rrsp_valid & pio_p2p_rrsp_ready ), // i, 1 + .dout ( cfg_rrsp_head ), // o, DSIZE + .empty ( p2p_empty ) // o, 1 + +`ifdef PCIEI_APB_DBG + ,.rtsel ( 2'b0 ) // i, 2 + ,.wtsel ( 2'b0 ) // i, 2 + ,.ptsel ( 2'b0 ) // i, 2 + ,.vg ( 1'b0 ) // i, 1 + ,.vs ( 1'b0 ) // i, 1 +`endif +); +/* --------P2P CFG Fifo{end}-------- */ + +/* --------Input Head parser{begin}-------- */ +assign p2p_mem_byte_cnt = pio_p2p_mem_req_head[28:16]; +assign p2p_mem_addr = pio_p2p_mem_req_head[127:96]; + +assign p2p_cfg_is_wr = is_idle ? pio_p2p_cfg_req_head[131] : cfg_req_head[131]; +assign p2p_cfg_byte_cnt = cfg_req_head[28:16]; +assign p2p_cfg_addr = cfg_req_head[127:96]; +always @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + cfg_req_head <= `TD 0; + end + else if (j_idle) begin + cfg_req_head <= `TD 0; + end + else if (pio_p2p_cfg_req_valid & is_idle) begin + cfg_req_head <= `TD pio_p2p_cfg_req_head; + end +end +/* --------Input Head parser{end}-------- */ + +/* -------{P2P space access FSM}begin------- */ +/******************** Stage 1: State Register **********************/ +assign is_idle = (cur_state == IDLE ); +assign is_trans_wreq_cfg = (cur_state == TRANS_WREQ_CFG); +assign is_trans_rreq_cfg = (cur_state == TRANS_RREQ_CFG); +assign is_trans_rrsp_cfg = (cur_state == TRANS_RRSP_CFG); + +assign j_idle = (is_trans_wreq_cfg & in_cfg_req_valid & in_cfg_req_ready & in_cfg_req_last) | + (is_trans_rreq_cfg & in_cfg_req_valid & in_cfg_req_ready & in_cfg_req_last) | + (is_trans_rrsp_cfg & pio_p2p_rrsp_valid & pio_p2p_rrsp_ready & pio_p2p_rrsp_last); +assign j_trans_wreq_cfg = is_idle & (pio_p2p_cfg_req_valid & p2p_cfg_is_wr); +assign j_trans_rreq_cfg = is_idle & (pio_p2p_cfg_req_valid & (!p2p_cfg_is_wr) & (!p2p_full)); +assign j_trans_rrsp_cfg = is_idle & (p2p_cfg_rrsp_valid & (!p2p_empty)); + +always @(posedge clk, negedge rst_n) begin + if(~rst_n) + cur_state <= `TD IDLE; + else + cur_state <= `TD nxt_state; +end + +/******************** Stage 2: State Transition **********************/ +always @(*) begin + case(cur_state) + IDLE: begin + if (p2p_cfg_rrsp_valid & (!p2p_empty)) begin + nxt_state = TRANS_RRSP_CFG; + end + else if (pio_p2p_cfg_req_valid & p2p_cfg_is_wr) begin + nxt_state = TRANS_WREQ_CFG; + end + else if (pio_p2p_cfg_req_valid & (!p2p_cfg_is_wr) & (!p2p_full)) begin + nxt_state = TRANS_RREQ_CFG; + end + else begin + nxt_state = IDLE; + end + end + TRANS_WREQ_CFG: begin + if (in_cfg_req_valid & in_cfg_req_ready & in_cfg_req_last) begin // write last beat of p2p cfg + nxt_state = IDLE; + end + else begin + nxt_state = TRANS_WREQ_CFG; + end + end + TRANS_RREQ_CFG: begin + if (in_cfg_req_valid & in_cfg_req_ready & in_cfg_req_last) begin + nxt_state = IDLE; + end + else begin + nxt_state = TRANS_RREQ_CFG; + end + end + TRANS_RRSP_CFG: begin + if (pio_p2p_rrsp_valid & pio_p2p_rrsp_ready & pio_p2p_rrsp_last) begin + nxt_state = IDLE; + end + else begin + nxt_state = TRANS_RRSP_CFG; + end + end + default: begin + nxt_state = IDLE; + end + endcase +end +/******************** Stage 3: Output **********************/ + +// Rsp Channel +assign pio_p2p_rrsp_valid = is_trans_rrsp_cfg & p2p_cfg_rrsp_valid; +assign pio_p2p_rrsp_last = pio_p2p_rrsp_valid; +assign pio_p2p_rrsp_data = pio_p2p_rrsp_valid ? p2p_cfg_rrsp_data : 0; +assign pio_p2p_rrsp_head = pio_p2p_rrsp_valid ? cfg_rrsp_head : 0; + +assign p2p_cfg_rrsp_ready = is_trans_rrsp_cfg & pio_p2p_rrsp_ready; + +// P2P Configuration Req Channel +/* p2p_req head + * | 127 | 126:64 | 63:32 | 31:13 | 12:0 | + * | is_wr | Reserved | addr | Reserved | byte_len | + */ +assign in_cfg_req_valid = (is_trans_wreq_cfg & pio_p2p_cfg_req_valid) | + (is_trans_rreq_cfg & pio_p2p_cfg_req_valid); +assign in_cfg_req_last = in_cfg_req_valid & pio_p2p_cfg_req_last; +assign in_cfg_req_data = (in_cfg_req_valid & is_trans_wreq_cfg) ? pio_p2p_cfg_req_data : 0; +assign in_cfg_req_head = {is_trans_wreq_cfg, 31'd0, 32'd0, 12'd0, p2p_cfg_addr[`BAR0_WIDTH-1:0], 19'd0, p2p_cfg_byte_cnt}; + +assign pio_p2p_cfg_req_ready = (is_trans_wreq_cfg & in_cfg_req_ready) | + (is_trans_rreq_cfg & in_cfg_req_ready); + +// P2P MEM Stream Channel +/* p2p_req head + * | 127 | 126:64 | 63:32 | 31:13 | 12:0 | + * | is_wr | Reserved | addr | Reserved | byte_len | + */ +assign in_mem_req_valid = pio_p2p_mem_req_valid; +assign in_mem_req_last = pio_p2p_mem_req_last ; +assign in_mem_req_data = pio_p2p_mem_req_data ; +assign in_mem_req_head = {1'd1, 31'd0, 32'd0, {32-`BAR0_WIDTH{1'd0}}, p2p_mem_addr[`BAR0_WIDTH-1:0], 19'd0, p2p_mem_byte_cnt}; + +assign pio_p2p_mem_req_ready = in_mem_req_ready; +/* -------{P2P space access FSM}end------- */ + +/* -------P2P CFG Stream Channel{begin}------- */ +st_reg #( + .TUSER_WIDTH ( `P2P_HEAD_W ), + .TDATA_WIDTH ( `PIO_DATA_W ) +) cfg_st_reg ( + .clk ( clk ), // i, 1 + .rst_n ( rst_n ), // i, 1 + + /* -------input axis-like interface{begin}------- */ + .axis_tvalid ( in_cfg_req_valid ), // i, 1 + .axis_tlast ( in_cfg_req_last ), // i, 1 + .axis_tuser ( in_cfg_req_head ), // i, TUSER_WIDTH + .axis_tdata ( in_cfg_req_data ), // i, TDATA_WIDTH + .axis_tready ( in_cfg_req_ready ), // o, 1 + /* -------input axis-like interface{end}------- */ + + /* -------output in_reg inteface{begin}------- */ + .axis_reg_tvalid ( p2p_cfg_req_valid ), // o, 1 + .axis_reg_tlast ( p2p_cfg_req_last ), // o, 1 + .axis_reg_tuser ( p2p_cfg_req_head ), // o, TUSER_WIDTH + .axis_reg_tdata ( p2p_cfg_req_data ), // o, TDATA_WIDTH + .axis_reg_tready ( p2p_cfg_req_ready ) // i, 1 + /* -------output in_reg inteface{end}------- */ +); +/* -------P2P CFG Stream Channel{end}------- */ + +/* -------P2P MEM Stream Channel{begin}------- */ +st_reg #( + .TUSER_WIDTH ( `P2P_HEAD_W ), + .TDATA_WIDTH ( `PIO_DATA_W ) +) mem_st_reg ( + .clk ( clk ), // i, 1 + .rst_n ( rst_n ), // i, 1 + + /* -------input axis-like interface{begin}------- */ + .axis_tvalid ( in_mem_req_valid ), // i, 1 + .axis_tlast ( in_mem_req_last ), // i, 1 + .axis_tuser ( in_mem_req_head ), // i, TUSER_WIDTH + .axis_tdata ( in_mem_req_data ), // i, TDATA_WIDTH + .axis_tready ( in_mem_req_ready ), // o, 1 + /* -------input axis-like interface{end}------- */ + + /* -------output in_reg inteface{begin}------- */ + .axis_reg_tvalid ( p2p_mem_req_valid ), // o, 1 + .axis_reg_tlast ( p2p_mem_req_last ), // o, 1 + .axis_reg_tuser ( p2p_mem_req_head ), // o, TUSER_WIDTH + .axis_reg_tdata ( p2p_mem_req_data ), // o, TDATA_WIDTH + .axis_reg_tready ( p2p_mem_req_ready ) // i, 1 + /* -------output in_reg inteface{end}------- */ +); +/* -------P2P MEM Stream Channel{end}------- */ + +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/STD_PIO/pio_demux.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/STD_PIO/pio_demux.v new file mode 100644 index 0000000000000000000000000000000000000000..302f6d19e744930b2f91755b44b269a073e09a9e --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/STD_PIO/pio_demux.v @@ -0,0 +1,206 @@ +`timescale 1ns / 100ps +//************************************************************************* +// > File : pio_demux.v +// > Author : Kangning +// > Date : 2022-03-12 +// > Note : demux module for pio, used for read & write request. +// > V1.1 2022-06-08: Now, It only support 4 output channels. +// > V1.2 2022-08-11: Now, it supports 8 output channels. +//************************************************************************* + +module pio_demux #( + parameter OUT_CHNL_NUM = 2 // number of channels for output +) ( + input wire clk , // i, 1 + input wire rst_n, // i, 1 + + input wire [2:0] demux_sel, // i, 3 + + /* --------PIO Write Request interface{begin}-------- */ + /* head + * | 131 | 130:128 | 127:96 | 95:0 | + * | is_wr | bar_id | addr | cc_head | + */ + input wire [`PIO_DATA_W-1:0] s_axis_req_data , // i, `PIO_DATA_W + input wire [`PIO_HEAD_W-1:0] s_axis_req_head , // i, `PIO_HEAD_W + input wire s_axis_req_last , // i, 1 + input wire s_axis_req_valid, // i, 1 + output wire s_axis_req_ready, // o, 1 + + /* head + * | 131 | 130:128 | 127:96 | 95:0 | + * | is_wr | bar_id | addr | cc_head | + */ + output wire [OUT_CHNL_NUM * `PIO_DATA_W-1:0] m_axis_req_data , // o, OUT_CHNL_NUM * `PIO_DATA_W + output wire [OUT_CHNL_NUM * `PIO_HEAD_W-1:0] m_axis_req_head , // o, OUT_CHNL_NUM * `PIO_HEAD_W + output wire [OUT_CHNL_NUM * 1 -1:0] m_axis_req_last , // o, OUT_CHNL_NUM * 1 + output wire [OUT_CHNL_NUM * 1 -1:0] m_axis_req_valid, // o, OUT_CHNL_NUM * 1 + input wire [OUT_CHNL_NUM * 1 -1:0] m_axis_req_ready // i, OUT_CHNL_NUM * 1 + /* --------PIO Write Request interface{end}-------- */ + +`ifdef PCIEI_APB_DBG + /* -------APB reated signal{begin}------- */ + ,output wire [`PIO_DEMUX_SIGNAL_W-1:0] dbg_signal // o, debug bus select + /* -------APB reated signal{end}------- */ +`endif +); + +reg [2:0] sel; + +/* -------State relevant in FSM{begin}------- */ +localparam IDLE = 2'b01, + TRANS = 2'b10; + +reg [1:0] cur_state; +reg [1:0] nxt_state; + +wire is_idle, is_trans; +/* -------State relevant in FSM{end}------- */ + +//---------------------------------------------------------------------------------------------------- + +`ifdef PCIEI_APB_DBG +/* -------APB reated signal{begin}------- */ +assign dbg_signal = {sel, cur_state, nxt_state, is_idle, is_trans}; // 9 +/* -------APB reated signal{end}------- */ +`endif + +/* -------{Read Response Distributor FSM}begin------- */ +/******************** Stage 1: State Register **********************/ + +assign is_idle = (cur_state == IDLE ); +assign is_trans = (cur_state == TRANS); + +always @(posedge clk, negedge rst_n) begin + if(~rst_n) + cur_state <= `TD IDLE; + else + cur_state <= `TD nxt_state; +end + +always @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + sel <= `TD 3'd0; + end + else if (is_idle & s_axis_req_valid) begin + sel <= `TD demux_sel; + end +end + + + +generate + if (OUT_CHNL_NUM == 2) begin:CHNL_NUM2 + + assign s_axis_req_ready = ((sel == 0) & is_trans & m_axis_req_ready[0]) | + ((sel == 1) & is_trans & m_axis_req_ready[1]); + + end + else if (OUT_CHNL_NUM == 3) begin:CHNL_NUM3 + + assign s_axis_req_ready = ((sel == 0) & is_trans & m_axis_req_ready[0]) | + ((sel == 1) & is_trans & m_axis_req_ready[1]) | + ((sel == 2) & is_trans & m_axis_req_ready[2]); + + end + else if (OUT_CHNL_NUM == 4) begin:CHNL_NUM4 + + assign s_axis_req_ready = ((sel == 0) & is_trans & m_axis_req_ready[0]) | + ((sel == 1) & is_trans & m_axis_req_ready[1]) | + ((sel == 2) & is_trans & m_axis_req_ready[2]) | + ((sel == 3) & is_trans & m_axis_req_ready[3]); + + end + else if (OUT_CHNL_NUM == 5) begin:CHNL_NUM5 + + assign s_axis_req_ready = ((sel == 0) & is_trans & m_axis_req_ready[0]) | + ((sel == 1) & is_trans & m_axis_req_ready[1]) | + ((sel == 2) & is_trans & m_axis_req_ready[2]) | + ((sel == 3) & is_trans & m_axis_req_ready[3]) | + ((sel == 4) & is_trans & m_axis_req_ready[4]); + + end + else if (OUT_CHNL_NUM == 6) begin:CHNL_NUM6 + + assign s_axis_req_ready = ((sel == 0) & is_trans & m_axis_req_ready[0]) | + ((sel == 1) & is_trans & m_axis_req_ready[1]) | + ((sel == 2) & is_trans & m_axis_req_ready[2]) | + ((sel == 3) & is_trans & m_axis_req_ready[3]) | + ((sel == 4) & is_trans & m_axis_req_ready[4]) | + ((sel == 5) & is_trans & m_axis_req_ready[5]); + + end + else if (OUT_CHNL_NUM == 7) begin:CHNL_NUM7 + + assign s_axis_req_ready = ((sel == 0) & is_trans & m_axis_req_ready[0]) | + ((sel == 1) & is_trans & m_axis_req_ready[1]) | + ((sel == 2) & is_trans & m_axis_req_ready[2]) | + ((sel == 3) & is_trans & m_axis_req_ready[3]) | + ((sel == 4) & is_trans & m_axis_req_ready[4]) | + ((sel == 5) & is_trans & m_axis_req_ready[5]) | + ((sel == 6) & is_trans & m_axis_req_ready[6]); + + end + else if (OUT_CHNL_NUM == 8) begin:CHNL_NUM8 + + assign s_axis_req_ready = ((sel == 0) & is_trans & m_axis_req_ready[0]) | + ((sel == 1) & is_trans & m_axis_req_ready[1]) | + ((sel == 2) & is_trans & m_axis_req_ready[2]) | + ((sel == 3) & is_trans & m_axis_req_ready[3]) | + ((sel == 4) & is_trans & m_axis_req_ready[4]) | + ((sel == 5) & is_trans & m_axis_req_ready[5]) | + ((sel == 6) & is_trans & m_axis_req_ready[6]) | + ((sel == 7) & is_trans & m_axis_req_ready[7]); + + end +endgenerate + +/******************** Stage 2: State Transition **********************/ + +always @(*) begin + case(cur_state) + IDLE: begin + if (s_axis_req_valid) begin + nxt_state = TRANS; + end + else begin + nxt_state = IDLE; + end + end + TRANS: begin + if (s_axis_req_last & s_axis_req_valid & s_axis_req_ready) begin + nxt_state = IDLE; + end + else begin + nxt_state = TRANS; + end + end + default: begin + nxt_state = IDLE; + end + endcase +end +/******************** Stage 3: Output **********************/ + +/* -------Generate block{begin}------- */ +/* This is used for different Channel Numbers, the default Number is 4 + */ +genvar i; +generate +for (i = 0; i < OUT_CHNL_NUM; i = i + 1) begin:CHNL_DEMUX_ASSIGN + +assign m_axis_req_valid[(i+1)*1 -1:i*1 ] = ((i == sel) & is_trans) ? s_axis_req_valid : 0; +assign m_axis_req_last [(i+1)*1 -1:i*1 ] = ((i == sel) & is_trans) ? s_axis_req_last : 0; +assign m_axis_req_data [(i+1)*`PIO_DATA_W-1:i*`PIO_DATA_W] = ((i == sel) & is_trans) ? s_axis_req_data : 0; +assign m_axis_req_head [(i+1)*`PIO_HEAD_W-1:i*`PIO_HEAD_W] = ((i == sel) & is_trans) ? s_axis_req_head : 0; + +end +endgenerate +/* + This is used for different Channel Numbers, the default Number is 4 */ +/* -------Generate block{end}------- */ + + +/* -------{Read Response Distributor FSM}end------- */ + +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/STD_PIO/pio_dw_align.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/STD_PIO/pio_dw_align.v new file mode 100644 index 0000000000000000000000000000000000000000..a40e8a64c000e9edefe58bc5f4b731818b9c42e4 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/STD_PIO/pio_dw_align.v @@ -0,0 +1,348 @@ +`timescale 1ns / 100ps +//************************************************************************* +// > File Name : pio_dw_align.v +// > Author : Kangning +// > Date : 2022-03-12 +// > Note : transform pkt to dw aligned +// > V1.1 - 2022-03-12 : Copied from wreq_align.v +// > ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +// > ^ ^ +// > ^ ########## ########### ^ +// > ^ # #------># tmp_reg # ############ ^ +// > ^ ------># in_reg # ###########-----># # ^ +// > ^ # # # out_wire #----> ^ +// > ^ ##########-----------------------># # ^ +// > ^ ############ ^ +// > ^ ^ +// > ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +//************************************************************************* + + +module pio_dw_align #( + parameter USER_WIDTH = `ALIGN_HEAD_W, + parameter HEAD_WIDTH = `ALIGN_HEAD_W +) ( + input wire clk , // i, 1 + input wire rst_n , // i, 1 + + /* -------unaligned input interface{begin}------- */ + /* *_head of DMA interface (interact with RDMA modules), + * valid only in first beat of a packet. + * When Transmiting msi-x interrupt message, 'Byte length' + * should be 0, 'address' means the address of msi-x, and + * msi-x data locates in *_data[31:0]. + * | Extra tuser | Resvd | Req Type | address | Reserved | Byte length | + * |------------------------------|-------|----------|--------------|----------|-------------| + * |HEAD_WIDTH-`ALIGN_HEAD_W|127:100| 99:96 | 95:32 | 31:13 | 12:0 | + */ + input wire unalign_valid , // i, 1 + input wire unalign_last , // i, 1 + input wire [HEAD_WIDTH -1:0] unalign_head , // i, HEAD_WIDTH + input wire [`PIO_DATA_W-1:0] unalign_data , // i, `PIO_DATA_W + output wire unalign_ready , // o, 1 + /* -------unaligned input interface{end}------- */ + + /* -------aligned output intrface{begin}------- */ + /* AXI-Stream write request tuser, only valid in first beat of a packet + * | Extra tuser | Reserved | REQ_TYPE | Tag | address | Reserved | DW length | first BE | last BE | + * |HEAD_WIDTH-`ALIGN_HEAD_W| 127:108 | 107:104 | 103:96 | 95:32 | 31:19 | 18:8 | 7:4 | 3:0 | + */ + output wire align_valid, // o, 1 + output wire align_last , // o, 1 + output wire [USER_WIDTH -1:0] align_user , // o, USER_WIDTH + output wire [`PIO_DATA_W-1:0] align_data , // o, `PIO_DATA_W + input wire align_ready // i, 1 + /* -------aligned output intrface{end}------- */ + +`ifdef PCIEI_APB_DBG + /* -------APB reated signal{begin}------- */ + ,output wire [`PIO_DW_ALIGN_SIGNAL_W-1:0] dbg_signal // o, `PIO_DW_ALIGN_SIGNAL_W + /* -------APB reated signal{end}------- */ +`endif +); + +/* -------relate to in_reg{begin}------- */ +reg in_reg_vld ; // read valid from input register +reg [HEAD_WIDTH -1:0] in_reg_head; +reg [`PIO_DATA_W-1:0] in_reg_data; +wire in_reg_rdy ; + +reg in_reg_sop ; // Indicate the start of a pkt +/* -------relate to in_reg{end}------- */ + +/* -------DW Dealignment FSM{begin}------- */ +localparam FIRST_BEAT = 3'b001, // This state emits first beat (or only bits) of packet. + MID_BEAT = 3'b010, // This state emits middle beat of packet. + LAST_BEAT = 3'b100; // This state emits last beat of packet, in this state, + // in_reg_rdy is not asserted if all data comes from tmp_reg. + +reg [2:0] cur_state; +reg [2:0] nxt_state; + +wire is_first_beat, is_mid_beat, is_last_beat; + +/* Fake last beat for align_* signal. If + * not aligned, this beat should have been + * the last beat. But actually, it's not. + * Note that this signal is different + * from 'in_reg_last' + */ +wire fake_align_last; + +/* + * indicate that next beat is the last beat. + * only valid in 'FIRST_BEAT' and 'MID_BEAT' + * state. */ +wire next_align_last; + +/* Indicate that data in last beat is all from tmp_reg. + * This wire is valid in the whole req. */ +wire is_all_from_tmp; + +/* dw size for last beat. This wire is valid in + * the whole req. */ +wire [$clog2(`PIO_KEEP_W)-1:0] dw_for_last_beat; + +/* Packet trans finished, and req_clear all relevant + * regs. */ +wire req_clear; + +/* align_* signal goes out one beat */ +wire req_go_out; +/* -------DW Dealignment FSM{end}------- */ + +/* -------Head gennerator{begin}------- */ +wire [3:0] req_type; +wire [64-1:0] addr ; +wire [13-1:0] byte_len; +wire [64-1:0] aligned_addr ; +wire [13-1:0] aligned_byte_len; +wire [11-1:0] dw_len ; +wire [4-1:0] first_be; +wire [4-1:0] last_be ; +wire [2:0] last_bytes; +wire [USER_WIDTH-1:0] wreq_user; + +reg [11-1:0] dw_cnt ; +wire [11-1:0] dw_left; +/* -------Head generator{end}------- */ + +/* -------tmp_reg logic{begin}------- */ +reg [31:0] tmp_reg_data; +/* -------tmp_reg logic{end}------- */ + +/* -------relate to out_reg{begin}------- */ +reg [`PIO_DATA_W-1:0] in_out_data; // transform data between tmp_reg and out_reg +/* -------relate to tmp_reg{end}------- */ + + +/* --------------------------------------------------------------------------------------- */ + +`ifdef PCIEI_APB_DBG +/* -------APB reated signal{begin}------- */ + +assign dbg_signal = { // 1286 + in_reg_vld, in_reg_head, in_reg_data, in_reg_rdy, in_reg_sop, // 519 + cur_state, nxt_state, // 6 + is_first_beat, is_mid_beat, is_last_beat, // 3 + fake_align_last, // 1 + next_align_last, // 1 + is_all_from_tmp, // 1 + dw_for_last_beat, // 3 + req_clear, // 1 + req_go_out, // 1 + req_type, addr, byte_len, aligned_addr, aligned_byte_len, dw_len, first_be, last_be, last_bytes, // 180 + wreq_user, // 260 + dw_cnt, dw_left, // 22 + tmp_reg_data, // 32 + in_out_data // 256 +}; + +/* -------APB reated signal{end}------- */ +`endif + +/* -------in_reg logic{begin}------- */ +always @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + in_reg_sop <= `TD 1; + end + else if (unalign_valid & unalign_ready & unalign_last) begin + in_reg_sop <= `TD 1; + end + else if (unalign_valid & unalign_ready & in_reg_sop) begin + in_reg_sop <= `TD 0; + end +end + +always @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + in_reg_head <= `TD 0; + end + else if (unalign_valid & unalign_ready & in_reg_sop) begin + in_reg_head <= `TD unalign_head; + end + else if (req_clear) begin // after trans finished, in_reg_head is set to 0 + in_reg_head <= `TD 0; + end +end + +always @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + in_reg_vld <= `TD 0; + in_reg_data <= `TD 0; + end + else if (unalign_valid & unalign_ready) begin // write en & not full + in_reg_vld <= `TD 1; + in_reg_data <= `TD unalign_data; + end + else if (in_reg_rdy & in_reg_vld) begin // read en & not empty + in_reg_vld <= `TD 0; + in_reg_data <= `TD 0; + end +end + +assign unalign_ready = !in_reg_vld | in_reg_rdy; // empty | going to empty +/* -------in_reg logic{end}------- */ + +/* -------Head generator{begin}------ */ +assign req_type = in_reg_head[99:96]; +assign addr = in_reg_head[95:32]; +assign byte_len = in_reg_head[12:0]; +assign aligned_addr = {addr[64-1:2], 2'd0}; +assign aligned_byte_len = byte_len + addr[1:0]; +assign dw_len = (aligned_byte_len >> 2) + | aligned_byte_len[1:0]; + +// In our implementation, uncontinuous first_be and last_be are forbidden. +// In our implementation, zero-payload are not allowed, first_be would never be 4'b0000. +assign first_be = ({4{addr[1:0] == 2'b00}} & 4'b1111) | + ({4{addr[1:0] == 2'b01}} & 4'b1110) | + ({4{addr[1:0] == 2'b10}} & 4'b1100) | + ({4{addr[1:0] == 2'b11}} & 4'b1000); +assign last_be = ({4{aligned_byte_len[1:0] == 2'b00}} & 4'b1111) | + ({4{aligned_byte_len[1:0] == 2'b01}} & 4'b0001) | + ({4{aligned_byte_len[1:0] == 2'b10}} & 4'b0011) | + ({4{aligned_byte_len[1:0] == 2'b11}} & 4'b0111); +assign last_bytes = (aligned_byte_len[1:0] == 2'b00) ? 3'b100 : {1'b0, aligned_byte_len[1:0]}; +/* AXI-Stream write request tuser, only valid in first beat of a packet + * | Extra tuser | Reserved | REQ_TYPE | Tag | address | Reserved | DW length | first BE | last BE | + * |HEAD_WIDTH-`ALIGN_HEAD_W| 127:108 | 107:104 | 103:96 | 95:32 | 31:19 | 18:8 | 7:4 | 3:0 | + */ +assign wreq_user = {in_reg_head[HEAD_WIDTH-1:`ALIGN_HEAD_W], + 20'd0, 4'h1, 8'd0, aligned_addr, 13'd0, dw_len, first_be, last_be}; + +assign dw_left = dw_len - dw_cnt; +always @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + dw_cnt <= `TD 0; + end + else if (req_clear) begin + dw_cnt <= `TD 0; + end + else if (req_go_out) begin + dw_cnt <= `TD dw_cnt + `PIO_KEEP_W; + end +end +/* -------Head generator{end}------ */ + +/* -------tmp_reg logic{begin}------- */ +always @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + tmp_reg_data <= `TD 0; + end + else if (req_clear) begin // Clear tmp_reg, in case + // next pkt contains invalid data. + tmp_reg_data <= `TD 0; + end + else if (req_go_out) begin // Update tmp_reg when it goes out + tmp_reg_data <= `TD in_reg_data[(`PIO_DATA_W-1)-:32]; + end +end +/* -------tmp_reg logic{end}------- */ + +/* -------out_reg logic{begin}------- */ +assign in_reg_rdy = (is_first_beat | is_mid_beat) & align_ready & !fake_align_last | + (is_last_beat & align_ready); + +assign align_valid = in_reg_vld | + !in_reg_vld & is_last_beat & is_all_from_tmp; +assign align_last = align_valid & (dw_left <= `PIO_KEEP_W); +assign align_user = wreq_user; +assign align_data = in_out_data; +always @(*) begin + if (is_last_beat & is_all_from_tmp) begin + case (addr[1:0]) + 2'd0: in_out_data = in_reg_data; + 2'd1: in_out_data = {{`PIO_DATA_W - 8 * 1{1'd0}}, tmp_reg_data[(32 - 1)-:(8 * 1)]}; + 2'd2: in_out_data = {{`PIO_DATA_W - 8 * 2{1'd0}}, tmp_reg_data[(32 - 1)-:(8 * 2)]}; + 2'd3: in_out_data = {{`PIO_DATA_W - 8 * 3{1'd0}}, tmp_reg_data[(32 - 1)-:(8 * 3)]}; + endcase + end + else if (is_first_beat | is_mid_beat | is_last_beat) begin + case (addr[1:0]) + 2'd0: in_out_data = in_reg_data; + 2'd1: in_out_data = {in_reg_data[`PIO_DATA_W - 8 * 1 - 1: 0], tmp_reg_data[(32 - 1)-:(8 * 1)]}; + 2'd2: in_out_data = {in_reg_data[`PIO_DATA_W - 8 * 2 - 1: 0], tmp_reg_data[(32 - 1)-:(8 * 2)]}; + 2'd3: in_out_data = {in_reg_data[`PIO_DATA_W - 8 * 3 - 1: 0], tmp_reg_data[(32 - 1)-:(8 * 3)]}; + endcase + end + else begin + in_out_data = 0; + end +end +/* -------out_reg logic{end}------- */ + +/* -------DW Dealignment FSM{begin}------- */ +/******************** Stage 1: State Register **********************/ +assign fake_align_last = is_all_from_tmp & next_align_last; +assign next_align_last = (dw_left <= `PIO_KEEP_W * 2) & (dw_left > `PIO_KEEP_W); +assign is_all_from_tmp = (dw_for_last_beat == 1) & (last_bytes <= addr[1:0]); +assign dw_for_last_beat = dw_len[$clog2(`PIO_KEEP_W)-1:0]; +assign req_clear = req_go_out & align_last; +assign req_go_out = align_valid & align_ready; + +assign is_first_beat = (cur_state == FIRST_BEAT); +assign is_mid_beat = (cur_state == MID_BEAT ); +assign is_last_beat = (cur_state == LAST_BEAT ); + +always @(posedge clk, negedge rst_n) begin + if(~rst_n) + cur_state <= `TD FIRST_BEAT; + else + cur_state <= `TD nxt_state; +end + +/******************** Stage 2: State Transition **********************/ + +always @(*) begin + case(cur_state) + FIRST_BEAT: begin + if (req_clear) // Imlying the only beat + nxt_state = FIRST_BEAT; + else if (req_go_out & next_align_last) + nxt_state = LAST_BEAT; + else if (req_go_out) + nxt_state = MID_BEAT; + else + nxt_state = FIRST_BEAT; + end + MID_BEAT: begin + if (req_go_out & next_align_last) + nxt_state = LAST_BEAT; + else + nxt_state = MID_BEAT; + end + LAST_BEAT: begin + if (req_clear) + nxt_state = FIRST_BEAT; + else + nxt_state = LAST_BEAT; + end + default: begin + nxt_state = FIRST_BEAT; + end + endcase +end +/******************** Stage 3: Output **********************/ +/* -------DW Dealignment FSM{end}------- */ + +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/STD_PIO/pio_mux.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/STD_PIO/pio_mux.v new file mode 100644 index 0000000000000000000000000000000000000000..1d3665453acbc15482a26dc9ce7a2b026f7883c4 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/STD_PIO/pio_mux.v @@ -0,0 +1,776 @@ +`timescale 1ns / 100ps +//************************************************************************* +// > File Name: pio_mux.v +// > Author : Kangning +// > Date : 2022-03-12 +// > Note : pio_mux is used to arbiter different channels for data transmission +// > V1.1 - 2021-02-04 : Add supporting for five channels +// > V1.2 - 2022-03-12 : Copy from req_arbiter.v +//************************************************************************* + +module pio_mux #( + parameter CHANNEL_NUM = 2 , // number of slave signals to arbit + parameter CHNL_NUM_LOG = 1 +) ( + input wire clk, + input wire rst_n , + + /* -------Slave AXIS Interface{begin}------- */ + input wire [CHANNEL_NUM * 1 -1:0] s_axis_ifc_tvalid, + input wire [CHANNEL_NUM * 1 -1:0] s_axis_ifc_tlast , + input wire [CHANNEL_NUM * `PIO_DATA_W-1:0] s_axis_ifc_tdata , + input wire [CHANNEL_NUM * `PIO_HEAD_W-1:0] s_axis_ifc_thead , + input wire [CHANNEL_NUM * `PIO_KEEP_W-1:0] s_axis_ifc_tkeep , + output wire [CHANNEL_NUM * 1 -1:0] s_axis_ifc_tready, + /* -------Slave AXIS Interface{end}------- */ + + /* ------- Master AXIS Interface{begin} ------- */ + output wire m_axis_ifc_tvalid, + output wire m_axis_ifc_tlast , + output wire [`PIO_DATA_W-1:0] m_axis_ifc_tdata , // contain only payload + output wire [`PIO_HEAD_W-1:0] m_axis_ifc_thead , // The field contents are different from dma_*_tuser interface + output wire [`PIO_KEEP_W-1:0] m_axis_ifc_tkeep , + input wire m_axis_ifc_tready + /* ------- Master AXIS Interface{end} ------- */ + +`ifdef PCIEI_APB_DBG + /* -------APB reated signal{begin}------- */ + ,output wire [`PIO_MUX_SIGNAL_W-1:0] dbg_signal // o, debug bus select + /* -------APB reated signal{end}------- */ +`endif + +`ifdef SIMULATION + /* ------- Debug interface {begin}------- */ + /* | reserved | reserved | idx | end | out | + * | 255:10 | 9:5 | 4:2 | 1 | 0 | + */ + ,output wire [255:0] debug + /* ------- Debug interface {end}------- */ +`endif + +); + +/* ------- Next scheduled channel{begin}------- */ +reg [CHNL_NUM_LOG-1:0] chnl_idx_reg; // Index of channel to be scheduled next time, valid only in REQ_TRANS state. +reg [CHNL_NUM_LOG-1:0] chnl_idx; // Index of channel to be scheduled next time, valid all the time. +reg [CHNL_NUM_LOG-1:0] last_chnl; // Index of last selected channel. + + +/** + * hit relevant channel is hit (hit_priority[3] == 1 means that last + * selected channel is still valid. + */ +wire hit_priority[CHANNEL_NUM-1:0]; + +/** + * index of channel priority in next time, e.g. nxt_priority[1] + * indicates the index of next next channel; while nxt_priority[0] + * indicates the index of next channel. + */ +wire [CHNL_NUM_LOG-1:0] nxt_priority[CHANNEL_NUM-1:0]; + +wire s_channel_tvalid[CHANNEL_NUM-1:0]; +wire s_channel_tlast [CHANNEL_NUM-1:0]; +wire [`PIO_DATA_W-1:0] s_channel_tdata [CHANNEL_NUM-1:0]; +wire [`PIO_HEAD_W-1:0] s_channel_tuser [CHANNEL_NUM-1:0]; +wire [`PIO_KEEP_W-1:0] s_channel_tkeep [CHANNEL_NUM-1:0]; + + +wire req_last; // last beat of the request +/* ------- Next scheduled channel{end}------- */ + +/* -------State relevant in FSM{begin}------- */ +localparam IDLE = 3'b001, + SCHEDULE = 3'b010, + REQ_TRANS = 3'b100; + +reg [2:0] cur_state; +reg [2:0] nxt_state; + +wire is_idle, is_schedule, is_req_trans; +wire j_req_trans; +// wire j_schedule; +/* -------State relevant in FSM{end}------- */ + +/* ------------------------------------------------------------------------ */ + +`ifdef PCIEI_APB_DBG +/* -------APB reated signal{begin}------- */ + +generate +if (CHANNEL_NUM == 4) begin:DBG_CHNL4 + +assign dbg_signal = { // 1621 + chnl_idx_reg, chnl_idx, last_chnl, // 6 + + hit_priority[3], nxt_priority[3], s_channel_tvalid[3], s_channel_tlast [3], s_channel_tdata [3], s_channel_tuser [3], s_channel_tkeep [3], + hit_priority[2], nxt_priority[2], s_channel_tvalid[2], s_channel_tlast [2], s_channel_tdata [2], s_channel_tuser [2], s_channel_tkeep [2], + hit_priority[1], nxt_priority[1], s_channel_tvalid[1], s_channel_tlast [1], s_channel_tdata [1], s_channel_tuser [1], s_channel_tkeep [1], + hit_priority[0], nxt_priority[0], s_channel_tvalid[0], s_channel_tlast [0], s_channel_tdata [0], s_channel_tuser [0], s_channel_tkeep [0], // 401*4=1604 + + req_last, // 1 + cur_state, nxt_state, // 6 + is_idle, is_schedule, is_req_trans, j_req_trans // 4 +}; + +end +endgenerate + +/* -------APB reated signal{end}------- */ +`endif + +`ifdef SIMULATION + /* ------- Debug interface {begin}------- */ + /* | reserved | reserved | idx | end | out | + * | 255:10 | 9:5 | 4:2 | 1 | 0 | + */ + assign debug = {{252+2-CHNL_NUM_LOG{1'd0}}, + chnl_idx, + m_axis_ifc_tvalid & m_axis_ifc_tready & m_axis_ifc_tlast, + m_axis_ifc_tvalid & m_axis_ifc_tready}; + /* ------- Debug interface {end}------- */ +`endif + + + +/* -------Find next channel{begin}------- */ + +always @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + last_chnl <= `TD {CHNL_NUM_LOG{1'd0}}; + end + else if (req_last) begin + last_chnl <= `TD chnl_idx; + end +end + +always @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + chnl_idx_reg <= `TD {CHNL_NUM_LOG{1'd0}}; + end + else if (j_req_trans) begin + chnl_idx_reg <= `TD chnl_idx; + end +end + +/* -------Generate block{begin}------- */ +genvar k; +generate +for (k = 0; k < CHANNEL_NUM; k = k + 1) begin:CHNL_PRIORITY + +assign nxt_priority[k] = ((last_chnl + k + 1) >= CHANNEL_NUM) ? + (last_chnl + k + 1 - CHANNEL_NUM) : (last_chnl + k + 1); + +end +endgenerate +/* -------Generate block{end}------- */ + +/* -------Generate block{begin}------- */ +/* This is used for different Channel Numbers, the default Number is 5 + */ +generate +if (CHANNEL_NUM == 10) begin:CHNL_SEL_10 + +always @(*) begin + if (is_schedule) begin + case (last_chnl) + 0: chnl_idx = hit_priority[0] ? 1 : + hit_priority[1] ? 2 : + hit_priority[2] ? 3 : + hit_priority[3] ? 4 : + hit_priority[4] ? 5 : + hit_priority[5] ? 6 : + hit_priority[6] ? 7 : + hit_priority[7] ? 8 : + hit_priority[8] ? 9 : + hit_priority[9] ? 0 : 1 ; // last branch is chosen when no channel is valid. + 1: chnl_idx = hit_priority[0] ? 2 : + hit_priority[1] ? 3 : + hit_priority[2] ? 4 : + hit_priority[3] ? 5 : + hit_priority[4] ? 6 : + hit_priority[5] ? 7 : + hit_priority[6] ? 8 : + hit_priority[7] ? 9 : + hit_priority[8] ? 0 : + hit_priority[9] ? 1 : 2 ; // last branch is chosen when no channel is valid. + 2: chnl_idx = hit_priority[0] ? 3 : + hit_priority[1] ? 4 : + hit_priority[2] ? 5 : + hit_priority[3] ? 6 : + hit_priority[4] ? 7 : + hit_priority[5] ? 8 : + hit_priority[6] ? 9 : + hit_priority[7] ? 0 : + hit_priority[8] ? 1 : + hit_priority[9] ? 2 : 3 ; // last branch is chosen when no channel is valid. + 3: chnl_idx = hit_priority[0] ? 4 : + hit_priority[1] ? 5 : + hit_priority[2] ? 6 : + hit_priority[3] ? 7 : + hit_priority[4] ? 8 : + hit_priority[5] ? 9 : + hit_priority[6] ? 0 : + hit_priority[7] ? 1 : + hit_priority[8] ? 2 : + hit_priority[9] ? 3 : 4 ; // last branch is chosen when no channel is valid. + 4: chnl_idx = hit_priority[0] ? 5 : + hit_priority[1] ? 6 : + hit_priority[2] ? 7 : + hit_priority[3] ? 8 : + hit_priority[4] ? 9 : + hit_priority[5] ? 0 : + hit_priority[6] ? 1 : + hit_priority[7] ? 2 : + hit_priority[8] ? 3 : + hit_priority[9] ? 4 : 5 ; // last branch is chosen when no channel is valid. + 5: chnl_idx = hit_priority[0] ? 6 : + hit_priority[1] ? 7 : + hit_priority[2] ? 8 : + hit_priority[3] ? 9 : + hit_priority[4] ? 0 : + hit_priority[5] ? 1 : + hit_priority[6] ? 2 : + hit_priority[7] ? 3 : + hit_priority[8] ? 4 : + hit_priority[9] ? 5 : 6 ; // last branch is chosen when no channel is valid. + 6: chnl_idx = hit_priority[0] ? 7 : + hit_priority[1] ? 8 : + hit_priority[2] ? 9 : + hit_priority[3] ? 0 : + hit_priority[4] ? 1 : + hit_priority[5] ? 2 : + hit_priority[6] ? 3 : + hit_priority[7] ? 4 : + hit_priority[8] ? 5 : + hit_priority[9] ? 6 : 7 ; // last branch is chosen when no channel is valid. + 7: chnl_idx = hit_priority[0] ? 8 : + hit_priority[1] ? 9 : + hit_priority[2] ? 0 : + hit_priority[3] ? 1 : + hit_priority[4] ? 2 : + hit_priority[5] ? 3 : + hit_priority[6] ? 4 : + hit_priority[7] ? 5 : + hit_priority[8] ? 6 : + hit_priority[9] ? 7 : 8 ; // last branch is chosen when no channel is valid. + 8: chnl_idx = hit_priority[0] ? 9 : + hit_priority[1] ? 0 : + hit_priority[2] ? 1 : + hit_priority[3] ? 2 : + hit_priority[4] ? 3 : + hit_priority[5] ? 4 : + hit_priority[6] ? 5 : + hit_priority[7] ? 6 : + hit_priority[8] ? 7 : + hit_priority[9] ? 8 : 9 ; // last branch is chosen when no channel is valid. + 9: chnl_idx = hit_priority[0] ? 0 : + hit_priority[1] ? 1 : + hit_priority[2] ? 2 : + hit_priority[3] ? 3 : + hit_priority[4] ? 4 : + hit_priority[5] ? 5 : + hit_priority[6] ? 6 : + hit_priority[7] ? 7 : + hit_priority[8] ? 8 : + hit_priority[9] ? 9 : 0 ; // last branch is chosen when no channel is valid. + default: chnl_idx = {CHNL_NUM_LOG{1'd0}}; + endcase + end + else begin + chnl_idx = chnl_idx_reg; // chosen in REQ_TRANS state + end +end + +end // CHANNEL_NUM == 10 +else if (CHANNEL_NUM == 9) begin:CHNL_SEL_9 + +always @(*) begin + if (is_schedule) begin + case (last_chnl) + 0: chnl_idx = hit_priority[0] ? 1 : + hit_priority[1] ? 2 : + hit_priority[2] ? 3 : + hit_priority[3] ? 4 : + hit_priority[4] ? 5 : + hit_priority[5] ? 6 : + hit_priority[6] ? 7 : + hit_priority[7] ? 8 : + hit_priority[8] ? 0 : 1 ; // last branch is chosen when no channel is valid. + 1: chnl_idx = hit_priority[0] ? 2 : + hit_priority[1] ? 3 : + hit_priority[2] ? 4 : + hit_priority[3] ? 5 : + hit_priority[4] ? 6 : + hit_priority[5] ? 7 : + hit_priority[6] ? 8 : + hit_priority[7] ? 0 : + hit_priority[8] ? 1 : 2 ; // last branch is chosen when no channel is valid. + 2: chnl_idx = hit_priority[0] ? 3 : + hit_priority[1] ? 4 : + hit_priority[2] ? 5 : + hit_priority[3] ? 6 : + hit_priority[4] ? 7 : + hit_priority[5] ? 8 : + hit_priority[6] ? 0 : + hit_priority[7] ? 1 : + hit_priority[8] ? 2 : 3 ; // last branch is chosen when no channel is valid. + 3: chnl_idx = hit_priority[0] ? 4 : + hit_priority[1] ? 5 : + hit_priority[2] ? 6 : + hit_priority[3] ? 7 : + hit_priority[4] ? 8 : + hit_priority[5] ? 0 : + hit_priority[6] ? 1 : + hit_priority[7] ? 2 : + hit_priority[8] ? 3 : 4 ; // last branch is chosen when no channel is valid. + 4: chnl_idx = hit_priority[0] ? 5 : + hit_priority[1] ? 6 : + hit_priority[2] ? 7 : + hit_priority[3] ? 8 : + hit_priority[4] ? 0 : + hit_priority[5] ? 1 : + hit_priority[6] ? 2 : + hit_priority[7] ? 3 : + hit_priority[8] ? 4 : 5 ; // last branch is chosen when no channel is valid. + 5: chnl_idx = hit_priority[0] ? 6 : + hit_priority[1] ? 7 : + hit_priority[2] ? 8 : + hit_priority[3] ? 0 : + hit_priority[4] ? 1 : + hit_priority[5] ? 2 : + hit_priority[6] ? 3 : + hit_priority[7] ? 4 : + hit_priority[8] ? 5 : 6 ; // last branch is chosen when no channel is valid. + 6: chnl_idx = hit_priority[0] ? 7 : + hit_priority[1] ? 8 : + hit_priority[2] ? 0 : + hit_priority[3] ? 1 : + hit_priority[4] ? 2 : + hit_priority[5] ? 3 : + hit_priority[6] ? 4 : + hit_priority[7] ? 5 : + hit_priority[8] ? 6 : 7 ; // last branch is chosen when no channel is valid. + 7: chnl_idx = hit_priority[0] ? 8 : + hit_priority[1] ? 0 : + hit_priority[2] ? 1 : + hit_priority[3] ? 2 : + hit_priority[4] ? 3 : + hit_priority[5] ? 4 : + hit_priority[6] ? 5 : + hit_priority[7] ? 6 : + hit_priority[8] ? 7 : 8 ; // last branch is chosen when no channel is valid. + 8: chnl_idx = hit_priority[0] ? 0 : + hit_priority[1] ? 1 : + hit_priority[2] ? 2 : + hit_priority[3] ? 3 : + hit_priority[4] ? 4 : + hit_priority[5] ? 5 : + hit_priority[6] ? 6 : + hit_priority[7] ? 7 : + hit_priority[8] ? 8 : 0 ; // last branch is chosen when no channel is valid. + default: chnl_idx = {CHNL_NUM_LOG{1'd0}}; + endcase + end + else begin + chnl_idx = chnl_idx_reg; // chosen in REQ_TRANS state + end +end + +end // CHANNEL_NUM == 9 +else if (CHANNEL_NUM == 8) begin:CHNL_SEL_8 + +always @(*) begin + if (is_schedule) begin + case (last_chnl) + 0: chnl_idx = hit_priority[0] ? 1 : + hit_priority[1] ? 2 : + hit_priority[2] ? 3 : + hit_priority[3] ? 4 : + hit_priority[4] ? 5 : + hit_priority[5] ? 6 : + hit_priority[6] ? 7 : + hit_priority[7] ? 0 : 1 ; // last branch is chosen when no channel is valid. + 1: chnl_idx = hit_priority[0] ? 2 : + hit_priority[1] ? 3 : + hit_priority[2] ? 4 : + hit_priority[3] ? 5 : + hit_priority[4] ? 6 : + hit_priority[5] ? 7 : + hit_priority[6] ? 0 : + hit_priority[7] ? 1 : 2 ; // last branch is chosen when no channel is valid. + 2: chnl_idx = hit_priority[0] ? 3 : + hit_priority[1] ? 4 : + hit_priority[2] ? 5 : + hit_priority[3] ? 6 : + hit_priority[4] ? 7 : + hit_priority[5] ? 0 : + hit_priority[6] ? 1 : + hit_priority[7] ? 2 : 3 ; // last branch is chosen when no channel is valid. + 3: chnl_idx = hit_priority[0] ? 4 : + hit_priority[1] ? 5 : + hit_priority[2] ? 6 : + hit_priority[3] ? 7 : + hit_priority[4] ? 0 : + hit_priority[5] ? 1 : + hit_priority[6] ? 2 : + hit_priority[7] ? 3 : 4 ; // last branch is chosen when no channel is valid. + 4: chnl_idx = hit_priority[0] ? 5 : + hit_priority[1] ? 6 : + hit_priority[2] ? 7 : + hit_priority[3] ? 0 : + hit_priority[4] ? 1 : + hit_priority[5] ? 2 : + hit_priority[6] ? 3 : + hit_priority[7] ? 4 : 5 ; // last branch is chosen when no channel is valid. + 5: chnl_idx = hit_priority[0] ? 6 : + hit_priority[1] ? 7 : + hit_priority[2] ? 0 : + hit_priority[3] ? 1 : + hit_priority[4] ? 2 : + hit_priority[5] ? 3 : + hit_priority[6] ? 4 : + hit_priority[7] ? 5 : 6 ; // last branch is chosen when no channel is valid. + 6: chnl_idx = hit_priority[0] ? 7 : + hit_priority[1] ? 0 : + hit_priority[2] ? 1 : + hit_priority[3] ? 2 : + hit_priority[4] ? 3 : + hit_priority[5] ? 4 : + hit_priority[6] ? 5 : + hit_priority[7] ? 6 : 7 ; // last branch is chosen when no channel is valid. + 7: chnl_idx = hit_priority[0] ? 0 : + hit_priority[1] ? 1 : + hit_priority[2] ? 2 : + hit_priority[3] ? 3 : + hit_priority[4] ? 4 : + hit_priority[5] ? 5 : + hit_priority[6] ? 6 : + hit_priority[7] ? 7 : 0 ; // last branch is chosen when no channel is valid. + default: chnl_idx = {CHNL_NUM_LOG{1'd0}}; + endcase + end + else begin + chnl_idx = chnl_idx_reg; // chosen in REQ_TRANS state + end +end + +end // CHANNEL_NUM == 8 +else if (CHANNEL_NUM == 7) begin:CHNL_SEL_7 + +always @(*) begin + if (is_schedule) begin + case (last_chnl) + 0: chnl_idx = hit_priority[0] ? 1 : + hit_priority[1] ? 2 : + hit_priority[2] ? 3 : + hit_priority[3] ? 4 : + hit_priority[4] ? 5 : + hit_priority[5] ? 6 : + hit_priority[6] ? 0 : 1 ; // last branch is chosen when no channel is valid. + 1: chnl_idx = hit_priority[0] ? 2 : + hit_priority[1] ? 3 : + hit_priority[2] ? 4 : + hit_priority[3] ? 5 : + hit_priority[4] ? 6 : + hit_priority[5] ? 0 : + hit_priority[6] ? 1 : 2 ; // last branch is chosen when no channel is valid. + 2: chnl_idx = hit_priority[0] ? 3 : + hit_priority[1] ? 4 : + hit_priority[2] ? 5 : + hit_priority[3] ? 6 : + hit_priority[4] ? 0 : + hit_priority[5] ? 1 : + hit_priority[6] ? 2 : 3 ; // last branch is chosen when no channel is valid. + 3: chnl_idx = hit_priority[0] ? 4 : + hit_priority[1] ? 5 : + hit_priority[2] ? 6 : + hit_priority[3] ? 0 : + hit_priority[4] ? 1 : + hit_priority[5] ? 2 : + hit_priority[6] ? 3 : 4 ; // last branch is chosen when no channel is valid. + 4: chnl_idx = hit_priority[0] ? 5 : + hit_priority[1] ? 6 : + hit_priority[2] ? 0 : + hit_priority[3] ? 1 : + hit_priority[4] ? 2 : + hit_priority[5] ? 3 : + hit_priority[6] ? 4 : 5 ; // last branch is chosen when no channel is valid. + 5: chnl_idx = hit_priority[0] ? 6 : + hit_priority[1] ? 0 : + hit_priority[2] ? 1 : + hit_priority[3] ? 2 : + hit_priority[4] ? 3 : + hit_priority[5] ? 4 : + hit_priority[6] ? 5 : 6 ; // last branch is chosen when no channel is valid. + 6: chnl_idx = hit_priority[0] ? 0 : + hit_priority[1] ? 1 : + hit_priority[2] ? 2 : + hit_priority[3] ? 3 : + hit_priority[4] ? 4 : + hit_priority[5] ? 5 : + hit_priority[6] ? 6 : 0 ; // last branch is chosen when no channel is valid. + default: chnl_idx = {CHNL_NUM_LOG{1'd0}}; + endcase + end + else begin + chnl_idx = chnl_idx_reg; // chosen in REQ_TRANS state + end +end + +end // CHANNEL_NUM == 7 +else if (CHANNEL_NUM == 6) begin:CHNL_SEL_6 + +always @(*) begin + if (is_schedule) begin + case (last_chnl) + 0: chnl_idx = hit_priority[0] ? 1 : + hit_priority[1] ? 2 : + hit_priority[2] ? 3 : + hit_priority[3] ? 4 : + hit_priority[4] ? 5 : + hit_priority[5] ? 0 : 1 ; // last branch is chosen when no channel is valid. + 1: chnl_idx = hit_priority[0] ? 2 : + hit_priority[1] ? 3 : + hit_priority[2] ? 4 : + hit_priority[3] ? 5 : + hit_priority[4] ? 0 : + hit_priority[5] ? 1 : 2 ; // last branch is chosen when no channel is valid. + 2: chnl_idx = hit_priority[0] ? 3 : + hit_priority[1] ? 4 : + hit_priority[2] ? 5 : + hit_priority[3] ? 0 : + hit_priority[4] ? 1 : + hit_priority[5] ? 2 : 3 ; // last branch is chosen when no channel is valid. + 3: chnl_idx = hit_priority[0] ? 4 : + hit_priority[1] ? 5 : + hit_priority[2] ? 0 : + hit_priority[3] ? 1 : + hit_priority[4] ? 2 : + hit_priority[5] ? 3 : 4 ; // last branch is chosen when no channel is valid. + 4: chnl_idx = hit_priority[0] ? 5 : + hit_priority[1] ? 0 : + hit_priority[2] ? 1 : + hit_priority[3] ? 2 : + hit_priority[4] ? 3 : + hit_priority[5] ? 4 : 5 ; // last branch is chosen when no channel is valid. + 5: chnl_idx = hit_priority[0] ? 0 : + hit_priority[1] ? 1 : + hit_priority[2] ? 2 : + hit_priority[3] ? 3 : + hit_priority[4] ? 4 : + hit_priority[5] ? 5 : 0 ; // last branch is chosen when no channel is valid. + default: chnl_idx = {CHNL_NUM_LOG{1'd0}}; + endcase + end + else begin + chnl_idx = chnl_idx_reg; // chosen in REQ_TRANS state + end +end + +end // CHANNEL_NUM == 6 +else if (CHANNEL_NUM == 5) begin:CHNL_SEL_5 + +always @(*) begin + if (is_schedule) begin + case (last_chnl) + 0: chnl_idx = hit_priority[0] ? 1 : + hit_priority[1] ? 2 : + hit_priority[2] ? 3 : + hit_priority[3] ? 4 : + hit_priority[4] ? 0 : 1 ; // last branch is chosen when no channel is valid. + 1: chnl_idx = hit_priority[0] ? 2 : + hit_priority[1] ? 3 : + hit_priority[2] ? 4 : + hit_priority[3] ? 0 : + hit_priority[4] ? 1 : 2 ; // last branch is chosen when no channel is valid. + 2: chnl_idx = hit_priority[0] ? 3 : + hit_priority[1] ? 4 : + hit_priority[2] ? 0 : + hit_priority[3] ? 1 : + hit_priority[4] ? 2 : 3 ; // last branch is chosen when no channel is valid. + 3: chnl_idx = hit_priority[0] ? 4 : + hit_priority[1] ? 0 : + hit_priority[2] ? 1 : + hit_priority[3] ? 2 : + hit_priority[4] ? 3 : 4 ; // last branch is chosen when no channel is valid. + 4: chnl_idx = hit_priority[0] ? 0 : + hit_priority[1] ? 1 : + hit_priority[2] ? 2 : + hit_priority[3] ? 3 : + hit_priority[4] ? 4 : 0 ; // last branch is chosen when no channel is valid. + default: chnl_idx = {CHNL_NUM_LOG{1'd0}}; + endcase + end + else begin + chnl_idx = chnl_idx_reg; // chosen in REQ_TRANS state + end +end + +end // CHANNEL_NUM == 5 +else if (CHANNEL_NUM == 4) begin:CHNL_SEL_4 + +always @(*) begin + if (is_schedule) begin + case (last_chnl) + 0: chnl_idx = hit_priority[0] ? 1 : + hit_priority[1] ? 2 : + hit_priority[2] ? 3 : + hit_priority[3] ? 0 : 1 ; // last branch is chosen when no channel is valid. + 1: chnl_idx = hit_priority[0] ? 2 : + hit_priority[1] ? 3 : + hit_priority[2] ? 0 : + hit_priority[3] ? 1 : 2 ; // last branch is chosen when no channel is valid. + 2: chnl_idx = hit_priority[0] ? 3 : + hit_priority[1] ? 0 : + hit_priority[2] ? 1 : + hit_priority[3] ? 2 : 3 ; // last branch is chosen when no channel is valid. + 3: chnl_idx = hit_priority[0] ? 0 : + hit_priority[1] ? 1 : + hit_priority[2] ? 2 : + hit_priority[3] ? 3 : 0 ; // last branch is chosen when no channel is valid. + default: chnl_idx = {CHNL_NUM_LOG{1'd0}}; + endcase + end + else begin + chnl_idx = chnl_idx_reg; // chosen in REQ_TRANS state + end +end + +end // CHANNEL_NUM == 4 +else if (CHANNEL_NUM == 3) begin:CHNL_SEL_3 + +always @(*) begin + if (is_schedule) begin + case (last_chnl) + 0: chnl_idx = hit_priority[0] ? 1 : + hit_priority[1] ? 2 : + hit_priority[2] ? 0 : 1; // last branch is chosen when no channel is valid. + 1: chnl_idx = hit_priority[0] ? 2 : + hit_priority[1] ? 0 : + hit_priority[2] ? 1 : 2; // last branch is chosen when no channel is valid. + 2: chnl_idx = hit_priority[0] ? 0 : + hit_priority[1] ? 1 : + hit_priority[2] ? 2 : 0; // last branch is chosen when no channel is valid. + default: chnl_idx = {CHNL_NUM_LOG{1'd0}}; + endcase + end + else begin + chnl_idx = chnl_idx_reg; // chosen in REQ_TRANS state + end +end + +end // CHANNEL_NUM == 3 +else if (CHANNEL_NUM == 2) begin:CHNL_SEL_2 + +always @(*) begin + if (is_schedule) begin + case (last_chnl) + 0: chnl_idx = hit_priority[0] ? 1 : + hit_priority[1] ? 0 : 1 ; // last branch is chosen when no channel is valid. + 1: chnl_idx = hit_priority[0] ? 0 : + hit_priority[1] ? 1 : 0 ; // last branch is chosen when no channel is valid. + default: chnl_idx = {CHNL_NUM_LOG{1'd0}}; + endcase + end + else begin + chnl_idx = chnl_idx_reg; // chosen in REQ_TRANS state + end +end + +end // CHANNEL_NUM == 2 +endgenerate +/* + This is used for different Channel Numbers, the default Number is 4 */ +/* -------Generate block{end}------- */ + +// state transform signal +assign req_last = m_axis_ifc_tvalid & m_axis_ifc_tready & m_axis_ifc_tlast; + +/* -------Find next channel{end}------- */ + +/* -------{Read Request Arbiter FSM}begin------- */ +/******************** Stage 1: State Register **********************/ +assign is_idle = (cur_state == IDLE ); +assign is_schedule = (cur_state == SCHEDULE ); +assign is_req_trans = (cur_state == REQ_TRANS); +assign j_req_trans = is_schedule & (!req_last) & (|s_axis_ifc_tvalid); +// assign j_schedule = is_schedule & (req_last) | +// is_req_trans & (req_last); + +always @(posedge clk, negedge rst_n) begin + if(~rst_n) + cur_state <= `TD IDLE; + else + cur_state <= `TD nxt_state; +end + +/******************** Stage 2: State Transition **********************/ + +always @(*) begin + case(cur_state) + IDLE: begin + if (|s_axis_ifc_tvalid) begin + nxt_state = SCHEDULE; + end + else begin + nxt_state = IDLE; + end + end + SCHEDULE: begin + if (req_last) begin // one beat request has already been transmited in + // schedule state. + nxt_state = SCHEDULE; + end + else if (|s_axis_ifc_tvalid) begin // There's valid channel, and not the last beat. + nxt_state = REQ_TRANS; + end + else begin + nxt_state = IDLE; + end + end + REQ_TRANS: begin + if (req_last) begin // request has already been transmited in + // req_trans state. + nxt_state = SCHEDULE; + end + else begin + nxt_state = REQ_TRANS; + end + end + default: begin + nxt_state = IDLE; + end + endcase +end +/******************** Stage 3: Output **********************/ + +/* -------Generate block{begin}------- */ +genvar n; +generate +for (n = 0; n < CHANNEL_NUM; n = n + 1) begin:CHNL_ASSIGN + +assign s_axis_ifc_tready[n] = (is_schedule | is_req_trans) & (n == chnl_idx) & m_axis_ifc_tready; + +assign s_channel_tvalid[n] = s_axis_ifc_tvalid[((n+1) * 1 -1):(n * 1 )]; +assign s_channel_tlast [n] = s_axis_ifc_tlast [((n+1) * 1 -1):(n * 1 )]; +assign s_channel_tdata [n] = s_axis_ifc_tdata [((n+1) * `PIO_DATA_W-1):(n * `PIO_DATA_W)]; +assign s_channel_tuser [n] = s_axis_ifc_thead [((n+1) * `PIO_HEAD_W-1):(n * `PIO_HEAD_W)]; +assign s_channel_tkeep [n] = s_axis_ifc_tkeep [((n+1) * `PIO_KEEP_W-1):(n * `PIO_KEEP_W)]; + +assign hit_priority[n] = s_channel_tvalid[nxt_priority[n]]; + +end +endgenerate +/* -------Generate block{end}------- */ + +assign m_axis_ifc_tvalid = (is_schedule | is_req_trans) ? s_channel_tvalid[chnl_idx] : 1'd0; +assign m_axis_ifc_tlast = (is_schedule | is_req_trans) ? s_channel_tlast [chnl_idx] : 1'd0; +assign m_axis_ifc_tdata = (is_schedule | is_req_trans) ? s_channel_tdata [chnl_idx] : {`PIO_DATA_W{1'd0}}; +assign m_axis_ifc_thead = (is_schedule | is_req_trans) ? s_channel_tuser [chnl_idx] : {`PIO_HEAD_W{1'd0}}; +assign m_axis_ifc_tkeep = (is_schedule | is_req_trans) ? s_channel_tkeep [chnl_idx] : {`PIO_KEEP_W{1'd0}}; + +/* -------{Read Request Arbiter FSM}end------- */ + + +endmodule diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/STD_PIO/pio_req.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/STD_PIO/pio_req.v new file mode 100644 index 0000000000000000000000000000000000000000..ebfdb9f3eb6bbc3b9664820b5e2fa786471049ed --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/STD_PIO/pio_req.v @@ -0,0 +1,141 @@ +`timescale 1ns / 100ps +//************************************************************************* +// > File : pio_req.v +// > Author : Kangning +// > Date : 2022-03-12 +// > Note : Distributor for write request. +// > V1.1 2022-06-08: Now, It demux the channel by the address information +//************************************************************************* + +module pio_req #( + parameter CHANNEL_NUM = 6 +) ( + input wire clk , // i, 1 + input wire rst_n, // i, 1 + + /* --------PIO Request interface{begin}-------- */ + /* pio_tuser + * | 139 | 138:136 | 135:132 | 131:128 | 127:96 | 95:0 | + * | is_wr | bar_id | first_be | last_be | aligned_addr | cc_head | + * | | | | | | | + */ + input wire [`PIO_DATA_W-1:0] s_axis_req_tdata , // i, `PIO_DATA_W + input wire [`PIO_USER_W-1:0] s_axis_req_tuser , // i, `PIO_USER_W + input wire s_axis_req_tlast , // i, 1 + input wire s_axis_req_tvalid, // i, 1 + output wire s_axis_req_tready, // o, 1 + + /* pio_head + * | 131 | 130:128 | 127:96 | 95:0 | + * | is_wr | bar_id | addr | cc_head | + */ + output wire [CHANNEL_NUM * `PIO_DATA_W-1:0] m_axis_req_data , // o, CHANNEL_NUM * `PIO_DATA_W + output wire [CHANNEL_NUM * `PIO_HEAD_W-1:0] m_axis_req_head , // o, CHANNEL_NUM * `PIO_HEAD_W + output wire [CHANNEL_NUM * 1 -1:0] m_axis_req_last , // o, CHANNEL_NUM * 1 + output wire [CHANNEL_NUM * 1 -1:0] m_axis_req_valid, // o, CHANNEL_NUM * 1 + input wire [CHANNEL_NUM * 1 -1:0] m_axis_req_ready // i, CHANNEL_NUM * 1 + /* --------PIO Request interface{end}-------- */ + +`ifdef PCIEI_APB_DBG + /* -------APB reated signal{begin}------- */ + ,input wire [31:0] dbg_sel // debug bus select + ,output wire [31:0] dbg_bus // debug bus data + /* -------APB reated signal{end}------- */ +`endif +); + +wire is_wr; +wire [2:0] bar_id; +wire [31:0] addr; +wire [95:0] cc_head; +wire [`PIO_HEAD_W-1:0] s_axis_req_thead; + +wire [2:0] chnl_sel; + +`ifdef PCIEI_APB_DBG +/* -------APB reated signal{begin}------- */ +wire [`PIO_REQ_SIGNAL_W -1:0] dbg_signal_pio_req; +wire [`PIO_DEMUX_SIGNAL_W-1:0] dbg_signal_pio_demux; +/* -------APB reated signal{end}------- */ +`endif + +//--------------------------------------------------------------------------------------------------------------------------- + +`ifdef PCIEI_APB_DBG +/* -------APB reated signal{begin}------- */ + +assign dbg_bus = dbg_signal_pio_req >> {dbg_sel, 5'd0}; + +assign dbg_signal_pio_req = { // 276 + is_wr, bar_id, addr, cc_head, // 132 + s_axis_req_thead, // 132 + chnl_sel, // 3 + dbg_signal_pio_demux // 9 +}; +/* -------APB reated signal{end}------- */ +`endif + +assign is_wr = s_axis_req_tuser[139]; +assign bar_id = s_axis_req_tuser[138:136]; +assign addr = s_axis_req_tuser[127:96]; +assign cc_head = s_axis_req_tuser[95:0]; +assign s_axis_req_thead = {is_wr, bar_id, addr[31:0], cc_head}; + +// Channel 5 : UAR Space +// Channel 4 : P2P MEM Space +// Channel 3 : P2P CFG Space +// Channel 2 : HCA MSI-X Interrupt Vector Table +// Channel 1 : Ethernet Interface +// Channel 0 : HCR CFG Space +assign chnl_sel = (bar_id[1] == 1'd1) ? + ( + 3'd5 // UAR(BAR2-3) Space + ) + : + ( + ((`P2P_MEM_BASE <= addr[`BAR0_WIDTH-1:0]) & (addr[`BAR0_WIDTH-1:0] < `P2P_MEM_BASE + `P2P_MEM_LEN)) ? 3'd4 : // P2P MEM Space + ((`P2P_CFG_BASE <= addr[`BAR0_WIDTH-1:0]) & (addr[`BAR0_WIDTH-1:0] < `P2P_CFG_BASE + `P2P_CFG_LEN)) ? 3'd3 : // P2P CFG Space + ((`HCA_INT_BASE <= addr[`BAR0_WIDTH-1:0]) & (addr[`BAR0_WIDTH-1:0] < `HCA_INT_BASE + `HCA_INT_LEN)) ? 3'd2 : // HCA MSI-X Interrupt Vector Table + ((`ETH_INT_BASE <= addr[`BAR0_WIDTH-1:0]) & (addr[`BAR0_WIDTH-1:0] < `ETH_INT_BASE + `ETH_INT_LEN)) ? 3'd1 : // Ethernet Interface + ((`ETH_BASE <= addr[`BAR0_WIDTH-1:0]) & (addr[`BAR0_WIDTH-1:0] < `ETH_BASE + `ETH_LEN )) ? 3'd1 : // Ethernet Interface + 3'd0 // HCR CFG Space && space not hit channels above + ); + +pio_demux #( + .OUT_CHNL_NUM ( CHANNEL_NUM ) +) pio_demux ( + .clk ( clk ), // i, 1 + .rst_n ( rst_n ), // i, 1 + + .demux_sel ( chnl_sel ), // i, 3 + + /* --------PIO Write Request interface{begin}-------- */ + /* head + * | 131 | 130:128 | 127:96 | 95:0 | + * | is_wr | bar_id | addr | cc_head | + */ + .s_axis_req_data ( s_axis_req_tdata ), // i, `PIO_DATA_W + .s_axis_req_head ( s_axis_req_thead ), // i, `PIO_HEAD_W + .s_axis_req_last ( s_axis_req_tlast ), // i, 1 + .s_axis_req_valid ( s_axis_req_tvalid ), // i, 1 + .s_axis_req_ready ( s_axis_req_tready ), // o, 1 + + /* head + * | 131 | 130:128 | 127:96 | 95:0 | + * | is_wr | bar_id | addr | cc_head | + */ + .m_axis_req_data ( m_axis_req_data ), // o, CHANNEL_NUM * `PIO_DATA_W + .m_axis_req_head ( m_axis_req_head ), // o, CHANNEL_NUM * `PIO_HEAD_W + .m_axis_req_last ( m_axis_req_last ), // o, CHANNEL_NUM * 1 + .m_axis_req_valid ( m_axis_req_valid ), // o, CHANNEL_NUM * 1 + .m_axis_req_ready ( m_axis_req_ready ) // i, CHANNEL_NUM * 1 + /* --------PIO Write Request interface{end}-------- */ + +`ifdef PCIEI_APB_DBG + /* -------APB reated signal{begin}------- */ + ,.dbg_signal ( dbg_signal_pio_demux ) // o, `PIO_DEMUX_SIGNAL_W + /* -------APB reated signal{end}------- */ +`endif +); + +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/STD_PIO/pio_rrsp.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/STD_PIO/pio_rrsp.v new file mode 100644 index 0000000000000000000000000000000000000000..e76e514f055b2febf2e0dbe4b80b0cccd9c09f0e --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/STD_PIO/pio_rrsp.v @@ -0,0 +1,295 @@ +`timescale 1ns / 100ps +//************************************************************************* +// > File Name: pio_rrsp.v +// > Author : Kangning +// > Date : 2020-08-25 +// > Note : pio_rrsp, used to transform DMA read response. +// > Note that the packet is 4KB aligned. +//************************************************************************* + +module pio_rrsp #( + + parameter CHANNEL_NUM = 4 +) ( + input wire clk , // i, 1 + input wire rst_n, // i, 1 + + /* --------PIO Read response interface{begin}-------- */ + /* pio_tuser + * | 139 | 138:136 | 135:132 | 131:128 | 127:96 | 95:0 | + * | is_wr | bar_id | first_be | last_be | aligned_addr | cc_head | + * | | | | | | | + */ + output wire [`PIO_DATA_W-1:0] m_axis_rrsp_tdata , // o, `PIO_DATA_W + output wire [`PIO_USER_W-1:0] m_axis_rrsp_tuser , // o, `PIO_USER_W + output wire m_axis_rrsp_tlast , // o, 1 + output wire m_axis_rrsp_tvalid, // o, 1 + input wire m_axis_rrsp_tready, // i, 1 + /* --------PIO Read response interface{end}-------- */ + + /* --------PIO Read response interface{begin}-------- */ + /* pio_head + * | 131 | 130:128 | 127:96 | 95:0 | + * | is_wr | bar_id | addr | cc_head | + */ + input wire [CHANNEL_NUM * `PIO_DATA_W-1:0] s_axis_rrsp_data , // i, CHANNEL_NUM * `PIO_DATA_W + input wire [CHANNEL_NUM * `PIO_HEAD_W-1:0] s_axis_rrsp_head , // i, CHANNEL_NUM * `PIO_HEAD_W + input wire [CHANNEL_NUM * 1 -1:0] s_axis_rrsp_last , // i, CHANNEL_NUM * 1 + input wire [CHANNEL_NUM * 1 -1:0] s_axis_rrsp_valid, // i, CHANNEL_NUM * 1 + output wire [CHANNEL_NUM * 1 -1:0] s_axis_rrsp_ready, // o, CHANNEL_NUM * 1 + /* --------PIO Read responses interface{end}-------- */ + + /* -------PCIe fragment property{begin}------- */ + /* This signal indicates the (max payload size & max read request size) agreed in the communication + * 3'b000 -- 128 B + * 3'b001 -- 256 B + * 3'b010 -- 512 B + * 3'b011 -- 1024B + * 3'b100 -- 2048B + * 3'b101 -- 4096B + */ + input wire [2:0] max_pyld_sz , + input wire [2:0] max_rd_req_sz // max read request size + /* -------PCIe fragment property{end}------- */ + +`ifdef PCIEI_APB_DBG + /* -------APB reated signal{begin}------- */ + ,input wire [31:0] dbg_sel // debug bus select + ,output wire [31:0] dbg_bus // debug bus data + /* -------APB reated signal{end}------- */ +`endif + +`ifdef SIMULATION + /* ------- Debug interface {begin}------- */ + /* | reserved | reserved | idx | end | out | + * | 255:10 | 9:5 | 4:2 | 1 | 0 | + */ + ,output wire [255:0] debug + /* ------- Debug interface {end}------- */ +`endif +); + +/* -------output for arbiter{begin}-------- */ +wire [`PIO_DATA_W-1:0] axis_out_rsp_tdata ; +wire [`PIO_HEAD_W-1:0] axis_out_rsp_thead ; +wire axis_out_rsp_tlast ; +wire axis_out_rsp_tvalid; +wire axis_out_rsp_tready; +/* -------output for arbiter{end}-------- */ + +/* -------arbiter -> pkt align{begin}------- */ +wire unalign_valid; +wire unalign_last ; +wire [`PIO_HEAD_W+`ALIGN_HEAD_W-1:0] unalign_head ; +wire [`PIO_DATA_W -1:0] unalign_data ; +wire unalign_ready; +/* -------arbiter -> pkt align{end}------- */ + +/* -------pkt align -> split{begin}------- */ +wire [`PIO_DATA_W -1:0] align_tdata ; +wire [`PIO_HEAD_W+`ALIGN_HEAD_W-1:0] align_tuser ; +wire align_tlast ; +wire align_tvalid; +wire align_tready; +/* -------pkt align -> split{end}------- */ + +/* --------signal from tuser{begin}--------- */ +wire [95:0] cc_head_old; +wire [31:0] aligned_addr; +wire [10:0] dw_cnt; +wire [3 :0] first_be, last_be; +/* --------signal from tuser{end}--------- */ + +/* --------signal from calculation{begin}--------- */ +wire [95:0] cc_head_new ; +wire [31:0] unaligned_addr; +wire [1 :0] first_empty ; // Number of invalid bytes in first Double word +/* --------signal from calculation{end}--------- */ + +/* -------split -> out{begin}------- */ +wire [`PIO_DATA_W -1:0] splited_tdata ; +wire [`PIO_KEEP_W -1:0] splited_tkeep ; +wire [`PIO_HEAD_W+`ALIGN_HEAD_W-1:0] splited_tuser ; +wire splited_tlast ; +wire splited_tvalid; +wire splited_tready; +/* -------split -> out{end}------- */ + +`ifdef PCIEI_APB_DBG +/* -------APB reated signal{begin}------- */ +wire [`PIO_RRSP_SIGNAL_W -1:0] dbg_signal_pio_rrsp; +wire [`PIO_MUX_SIGNAL_W -1:0] dbg_signal_pio_mux; +wire [`PIO_DW_ALIGN_SIGNAL_W -1:0] dbg_signal_pio_dw_align; +wire [`PIO_RSP_SPLIT_SIGNAL_W-1:0] dbg_signal_pio_rsp_split; +/* -------APB reated signal{end}------- */ +`endif + +//--------------------------------------------------------------------------------------------------------------------------- + +`ifdef PCIEI_APB_DBG +/* -------APB reated signal{begin}------- */ + +assign dbg_bus = dbg_signal_pio_rrsp >> {dbg_sel, 5'd0}; + +assign dbg_signal_pio_rrsp = { // 6442 + axis_out_rsp_tdata, axis_out_rsp_thead, axis_out_rsp_tlast, axis_out_rsp_tvalid, axis_out_rsp_tready, // 391 + unalign_valid, unalign_last, unalign_head, unalign_data, unalign_ready, // 519 + align_tdata, align_tuser, align_tlast, align_tvalid, align_tready, // 519 + cc_head_old, aligned_addr, dw_cnt, first_be, last_be, // 147 + cc_head_new, unaligned_addr, first_empty, // 130 + splited_tdata, splited_tkeep, splited_tuser, splited_tlast, splited_tvalid, splited_tready, // 527 + dbg_signal_pio_mux, // 1621 + dbg_signal_pio_dw_align, // 1286 + dbg_signal_pio_rsp_split // 1302 +}; +/* -------APB reated signal{end}------- */ +`endif + +pio_mux #( + .CHNL_NUM_LOG ( 2 ), + .CHANNEL_NUM ( CHANNEL_NUM ) // number of slave signals to arbit +) pio_mux ( + .clk ( clk ), // i, 1 + .rst_n ( rst_n ), // i, 1 + + /* -------Slave AXIS Interface{begin}------- */ + /* pio_head + * | 131 | 130:128 | 127:96 | 95:0 | + * | is_wr | bar_id | addr | cc_head | + */ + .s_axis_ifc_tdata ( s_axis_rrsp_data ), // i, CHANNEL_NUM * `PIO_DATA_W + .s_axis_ifc_tkeep ( {CHANNEL_NUM * `PIO_KEEP_W{1'd0}}), // i, CHANNEL_NUM * `PIO_KEEP_W + .s_axis_ifc_thead ( s_axis_rrsp_head ), // i, CHANNEL_NUM * `PIO_HEAD_W ;The field contents are different from dma_*_tuser interface + .s_axis_ifc_tlast ( s_axis_rrsp_last ), // i, CHANNEL_NUM * 1 + .s_axis_ifc_tvalid ( s_axis_rrsp_valid ), // i, CHANNEL_NUM * 1 + .s_axis_ifc_tready ( s_axis_rrsp_ready ), // o, CHANNEL_NUM * 1 + /* -------Slave AXIS Interface{end}------- */ + + /* ------- Master AXIS Interface{begin} ------- */ + /* pio_head + * | 131 | 130:128 | 127:96 | 95:0 | + * | is_wr | bar_id | addr | cc_head | + */ + .m_axis_ifc_tdata ( axis_out_rsp_tdata ), // o, `PIO_DATA_W + .m_axis_ifc_tkeep ( ), // o, `PIO_KEEP_W + .m_axis_ifc_thead ( axis_out_rsp_thead ), // o, `PIO_HEAD_W ;The field contents are different from dma_*_head interface + .m_axis_ifc_tlast ( axis_out_rsp_tlast ), // o, 1 + .m_axis_ifc_tvalid ( axis_out_rsp_tvalid ), // o, 1 + .m_axis_ifc_tready ( axis_out_rsp_tready ) // i, 1 + /* ------- Master AXIS Interface{end} ------- */ + +`ifdef PCIEI_APB_DBG + /* -------APB reated signal{begin}------- */ + ,.dbg_signal ( dbg_signal_pio_mux ) // o, `PIO_MUX_SIGNAL_W + /* -------APB reated signal{end}------- */ +`endif + +`ifdef SIMULATION + /* ------- Debug interface {begin}------- */ + /* | reserved | reserved | top_idx | top_end | top_out | + * | 255:10 | 9:5 | 4:2 | 1 | 0 | + */ + ,.debug (debug) + /* ------- Debug interface {end}------- */ +`endif +); + +assign unalign_data = axis_out_rsp_tdata ; +assign unalign_head = {axis_out_rsp_thead, 64'd0, axis_out_rsp_thead[127:96], 19'd0, axis_out_rsp_thead[28:16]}; +assign unalign_last = axis_out_rsp_tlast ; +assign unalign_valid = axis_out_rsp_tvalid; +assign axis_out_rsp_tready = unalign_ready; + +/* ------- Align data to DW aligned{begin}------- */ +pio_dw_align #( + .USER_WIDTH ( `PIO_HEAD_W + `ALIGN_HEAD_W ), + .HEAD_WIDTH ( `PIO_HEAD_W + `ALIGN_HEAD_W ) +) pio_dw_align ( + .clk ( clk ), // i, 1 + .rst_n ( rst_n ), // i, 1 + + .unalign_data ( unalign_data ), // i, `PIO_DATA_W + .unalign_head ( unalign_head ), // i, HEAD_WIDTH + .unalign_last ( unalign_last ), // i, 1 + .unalign_valid ( unalign_valid ), // i, 1 + .unalign_ready ( unalign_ready ), // o, 1 + + .align_data ( align_tdata ), // o, `PIO_DATA_W + .align_user ( align_tuser ), // o, USER_WIDTH + .align_last ( align_tlast ), // o, 1 + .align_valid ( align_tvalid ), // o, 1 + .align_ready ( align_tready ) // i, 1 + +`ifdef PCIEI_APB_DBG + /* -------APB reated signal{begin}------- */ + ,.dbg_signal ( dbg_signal_pio_dw_align ) // o, `PIO_DW_ALIGN_SIGNAL_W + /* -------APB reated signal{end}------- */ +`endif +); +/* ------- Align data to DW aligned{end}------- */ + +/* ------- Split pkt to fit max_pyld_sz{begin}------- */ +pio_rsp_split #( + .USER_WIDTH ( `PIO_HEAD_W + `ALIGN_HEAD_W ) +) pio_rsp_split ( + .clk ( clk ), // i, 1 + .rst_n ( rst_n ), // i, 1 + + .max_pyld_sz ( max_pyld_sz ), // i, 3 + + .align_valid ( align_tvalid ), // i, 1 + .align_last ( align_tlast ), // i, 1 + .align_user ( align_tuser ), // i, USER_WIDTH + .align_data ( align_tdata ), // i, `PIO_DATA_W + .align_ready ( align_tready ), // o, 1 + + .splited_tdata ( splited_tdata ), // o, `PIO_DATA_W + .splited_tkeep ( splited_tkeep ), // o, `PIO_KEEP_W + .splited_tuser ( splited_tuser ), // o, USER_WIDTH + .splited_tlast ( splited_tlast ), // o, 1 + .splited_tvalid ( splited_tvalid ), // o, 1 + .splited_tready ( splited_tready ) // i, 1 + +`ifdef PCIEI_APB_DBG + /* -------APB reated signal{begin}------- */ + ,.dbg_signal ( dbg_signal_pio_rsp_split ) // o, `PIO_RSP_SPLIT_SIGNAL_W + /* -------APB reated signal{end}------- */ +`endif +); +/* ------- Split pkt to fit max_pyld_sz{end}------- */ + +/* --------signal from tuser{begin}--------- */ +/* AXI-Stream splited interface tuser, only valid in first beat of a packet + * | Extra tuser | Reserved | REQ_TYPE | Tag | address | Reserved | DW length | first BE | last BE | + * |`PIO_HEAD_W+`ALIGN_HEAD_W-1:`ALIGN_HEAD_W| 127:108 | 107:104 | 103:96 | 95:32 | 31:19 | 18:8 | 7:4 | 3:0 | + */ +assign cc_head_old = splited_tuser[`PIO_HEAD_W+`ALIGN_HEAD_W-1:`ALIGN_HEAD_W]; +assign first_be = splited_tuser[7:4]; +assign last_be = splited_tuser[3:0]; +assign aligned_addr = splited_tuser[63:32]; +assign dw_cnt = splited_tuser[18:8]; +/* --------signal from tuser{end}--------- */ + +/* --------signal from calculation{begin}--------- */ +assign cc_head_new = {cc_head_old[95:43], dw_cnt, cc_head_old[31:7], unaligned_addr[6:0]}; +assign first_empty = first_be[0] ? 2'd0 : + first_be[1] ? 2'd1 : + first_be[2] ? 2'd2 : + first_be[3] ? 2'd3 : + 2'd0; // unlikely +assign unaligned_addr = {aligned_addr[31:2], first_empty}; +/* --------signal from calculation{end}--------- */ + +/* --------output interface{begin}-------- */ +/* pio_tuser + * | 139 | 138:136 | 135:132 | 131:128 | 127:96 | 95:0 | + * | is_wr | bar_id | first_be | last_be | aligned_addr | cc_head | + * | | | | | | | + */ +assign m_axis_rrsp_tdata = splited_tdata ; +assign m_axis_rrsp_tuser = {1'd0, 3'd0, first_be, last_be, aligned_addr, cc_head_new}; +assign m_axis_rrsp_tlast = splited_tlast ; +assign m_axis_rrsp_tvalid = splited_tvalid; +assign splited_tready = m_axis_rrsp_tready; +/* --------output interface{end}-------- */ +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/STD_PIO/pio_rsp_split.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/STD_PIO/pio_rsp_split.v new file mode 100644 index 0000000000000000000000000000000000000000..c936e5df673cc0ccda877a4d74f46a0472025fe1 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/STD_PIO/pio_rsp_split.v @@ -0,0 +1,313 @@ +`timescale 1ns / 100ps +//************************************************************************* +// > File Name : pio_rsp_split.v +// > Author : Kangning +// > Date : 2022-03-12 +// > Note : split one wr req into multiply small subreq +// > V1.1 - 2022-03-12 : Copied from wreq_split.v +//************************************************************************* +`define PIO_KEEP_MASK {`PIO_KEEP_W{1'd1}} + +module pio_rsp_split #( + parameter USER_WIDTH = `ALIGN_HEAD_W +) ( + input wire clk , // i, 1 + input wire rst_n, // i, 1 + + input wire [2:0] max_pyld_sz, // i, 3 + + /* -------aligned intrface{begin}------- */ + /* AXI-Stream aligned interface tuser, only valid in first beat of a packet + * | Extra tuser | Reserved | REQ_TYPE | Tag | address | Reserved | DW length | first BE | last BE | + * |USER_WIDTH-`ALIGN_HEAD_W| 127:108 | 107:104 | 103:96 | 95:32 | 31:19 | 18:8 | 7:4 | 3:0 | + */ + input wire align_valid, // i, 1 + input wire align_last , // i, 1 + input wire [USER_WIDTH -1:0] align_user , // i, USER_WIDTH + input wire [`PIO_DATA_W-1:0] align_data , // i, `PIO_DATA_W + output wire align_ready, // o, 1 + /* -------aligned intrface{end}------- */ + + /* -------splited interface{begin}------- */ + /* AXI-Stream splited interface tuser, only valid in first beat of a packet + * | Extra tuser | Reserved | REQ_TYPE | Tag | address | Reserved | DW length | first BE | last BE | + * |USER_WIDTH-`ALIGN_HEAD_W| 127:108 | 107:104 | 103:96 | 95:32 | 31:19 | 18:8 | 7:4 | 3:0 | + */ + output wire [`PIO_DATA_W-1:0] splited_tdata , + output wire [`PIO_KEEP_W-1:0] splited_tkeep , + output wire [USER_WIDTH -1:0] splited_tuser , + output wire splited_tlast , + output wire splited_tvalid, + input wire splited_tready + /* -------axis splited interface{end}------- */ + +`ifdef PCIEI_APB_DBG + /* -------APB reated signal{begin}------- */ + ,output wire [`PIO_RSP_SPLIT_SIGNAL_W-1:0] dbg_signal // o, `PIO_RSP_SPLIT_SIGNAL_W + /* -------APB reated signal{end}------- */ +`endif +); + +/* -------Constant Value{begin}------- */ +localparam MIN_DWORD_SZ_LOG = 5; // min dwords size for 128B axis packet (2 ^ 5 Dword) +wire [11-1:0] max_pyld_dw; // Maximum payload size in dw (in one sub req) +/* -------Constant Value{end}------- */ + +/* -------relate to in_reg{begin}------- */ +reg in_reg_vld ; // read valid from input register +reg [USER_WIDTH -1:0] in_reg_user; +reg [`PIO_DATA_W-1:0] in_reg_data; +wire [`PIO_KEEP_W-1:0] in_reg_keep; +wire in_reg_rdy ; + +reg in_reg_sop ; // Indicate the start of a pkt +/* -------relate to in_reg{end}------- */ + +/* -------Head relevant{begin}------- */ +// align user decode +wire [11-1:0] dw_len ; +wire [4 -1:0] first_be; +wire [4 -1:0] last_be ; +wire [64-1:0] addr ; +wire [3:0] req_type; + +// axis_tuser decode +wire [11-1:0] sub_dw_len ; +wire [4 -1:0] sub_first_be; +wire [4 -1:0] sub_last_be ; +wire [64-1:0] sub_addr ; + +reg [11-1:0] dw_cnt , sub_dw_cnt ; +wire [11-1:0] dw_left, sub_dw_left; +wire [11-1:0] dw_left_dyn; // how many dw left, count down in dynamically + +wire [USER_WIDTH-1:0] int_tuser, wreq_tuser; +/* -------Head relevant{end}------- */ + +/* -------Split packet{begin}------- */ +wire first_sub_req, last_sub_req; +wire next_req_last, next_sub_last; +/* -------Split packet{end}------- */ + +/* -------State relevant in FSM{begin}------- */ +localparam IDLE = 4'b0001, + TX = 4'b0010, // Transmit normal beat. + SUB_LAST = 4'b0100, // TX the last beat of sub req. + REQ_LAST = 4'b1000; // TX the last beat of the enire req +reg [3:0] cur_state; +reg [3:0] nxt_state; +wire is_idle, is_tx, is_sub_last, is_req_last; + +wire beat_go ; // When asserted, one beat go out of axis_* interface +wire sub_clear; // When asserted, last beat of sub req are forwarded +wire req_clear; // When asserted, last beat of entire req are forwarded +/* -------State relevant in FSM{end}------- */ + +/* --------------------------------------------------------------------------------------- */ + +`ifdef PCIEI_APB_DBG +/* -------APB reated signal{begin}------- */ + +assign dbg_signal = { // 1302 + max_pyld_dw, // 11 + in_reg_vld, in_reg_user, in_reg_data, in_reg_keep, in_reg_rdy, in_reg_sop, // 527 + dw_len, first_be, last_be, addr, req_type, // 87 + sub_dw_len, sub_first_be, sub_last_be, sub_addr, // 83 + dw_cnt, sub_dw_cnt, dw_left, sub_dw_left, dw_left_dyn, // 55 + int_tuser, wreq_tuser, // 520 + first_sub_req, last_sub_req, next_req_last, next_sub_last, // 4 + cur_state, nxt_state, // 8 + is_idle, is_tx, is_sub_last, is_req_last, // 4 + beat_go, sub_clear, req_clear // 3 +}; + +/* -------APB reated signal{end}------- */ +`endif + + +/* -------Constant Value{begin}------- */ +assign max_pyld_dw = 1'd1 << (MIN_DWORD_SZ_LOG + max_pyld_sz); +/* -------Constant Value{end}------- */ + +/* -------in_reg logic{begin}------- */ +always @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + in_reg_sop <= `TD 1; + end + else if (align_valid & align_ready & align_last) begin + in_reg_sop <= `TD 1; + end + else if (align_valid & align_ready & in_reg_sop) begin + in_reg_sop <= `TD 0; + end +end + +always @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + in_reg_user <= `TD 0; + end + else if (align_valid & align_ready & in_reg_sop) begin + in_reg_user <= `TD align_user; + end + else if (req_clear) begin // after trans finished, in_reg_user is set to 0 + in_reg_user <= `TD 0; + end +end + +always @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + in_reg_vld <= `TD 0; + in_reg_data <= `TD 0; + end + else if (align_valid & align_ready) begin // write en & not full + in_reg_vld <= `TD 1; + in_reg_data <= `TD align_data; + end + else if (in_reg_rdy & in_reg_vld) begin // read en & not empty + in_reg_vld <= `TD 0; + in_reg_data <= `TD 0; + end +end + +assign align_ready = !in_reg_vld | in_reg_rdy; // empty | going to empty +/* -------in_reg logic{end}------- */ + +/* -------tuser logic{begin}------- */ +assign dw_len = in_reg_user[18:8 ]; +assign first_be = in_reg_user[7 :4 ]; +assign last_be = in_reg_user[3 :0 ]; +assign addr = in_reg_user[95:32]; +assign req_type = in_reg_user[107:104]; + +assign sub_dw_len = last_sub_req ? dw_left : max_pyld_dw; +// assign sub_first_be = ? first_be : 4'b1111; +// assign sub_last_be = last_sub_req ? last_be : 4'b1111; +assign sub_addr = addr + (dw_cnt << 2); + +assign sub_first_be = (dw_len == 1) ? (first_be & last_be) : // when the req only has one DW + (sub_dw_len == 1) ? (4'b1111 & last_be) : // when the sub_req has one DW. + first_sub_req ? first_be : 4'b1111; +assign sub_last_be = (sub_dw_len == 1) ? 4'b0000 : // when the payload has one DW, last_be should be 0. + last_sub_req ? last_be : 4'b1111; + +assign wreq_tuser = {in_reg_user[USER_WIDTH-1:`ALIGN_HEAD_W], + 20'd0, req_type, 8'd0, sub_addr, 13'd0, sub_dw_len, sub_first_be, sub_last_be}; +assign int_tuser = {in_reg_user[USER_WIDTH-1:`ALIGN_HEAD_W], + 20'd0, req_type, 8'd0, sub_addr, 32'd0}; +/* -------tuser logic{end}------- */ + +/* -------Split packet{begin}------- */ +assign first_sub_req = dw_cnt == 0; +assign last_sub_req = dw_left <= max_pyld_dw; +assign next_req_last = (dw_left_dyn <= (`PIO_KEEP_W << 1)) & (dw_left_dyn > `PIO_KEEP_W); +assign next_sub_last = (sub_dw_left > `PIO_KEEP_W) & (sub_dw_left <= (`PIO_KEEP_W << 1)); + +assign dw_left_dyn = dw_left - sub_dw_cnt; +assign dw_left = dw_len - dw_cnt; +always @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + dw_cnt <= `TD 0; + end + else if (req_clear) begin + dw_cnt <= `TD 0; + end + else if (sub_clear) begin // beat_go & is_sub_last + dw_cnt <= `TD dw_cnt + max_pyld_dw; + end +end + +assign sub_dw_left = sub_dw_len - sub_dw_cnt; +always @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + sub_dw_cnt <= `TD 0; + end + else if (sub_clear) begin + sub_dw_cnt <= `TD 0; + end + else if (beat_go) begin + sub_dw_cnt <= `TD sub_dw_cnt + `PIO_KEEP_W; + end +end + +/* -------Split packet{end}------- */ + +/* -------{DMA Write Request FSM}begin------- */ +/******************** Stage 1: State Register **********************/ +assign is_idle = (cur_state == IDLE ); +assign is_tx = (cur_state == TX ); +assign is_sub_last = (cur_state == SUB_LAST); +assign is_req_last = (cur_state == REQ_LAST); + +assign beat_go = splited_tvalid & splited_tready; +assign sub_clear = splited_tvalid & splited_tready & splited_tlast; +assign req_clear = sub_clear & in_reg_sop; + +always @(posedge clk, negedge rst_n) begin + if(~rst_n) + cur_state <= `TD IDLE; + else + cur_state <= `TD nxt_state; +end + +/******************** Stage 2: State Transition **********************/ +always @(*) begin + case(cur_state) + IDLE: begin + if (align_valid & align_ready & align_last) + nxt_state = REQ_LAST; + else if (align_valid & align_ready) + nxt_state = TX; + else + nxt_state = IDLE; + end + TX: begin + if (beat_go & next_req_last) + nxt_state = REQ_LAST; + else if (beat_go & next_sub_last) + nxt_state = SUB_LAST; + else + nxt_state = TX; + end + SUB_LAST: begin + if (sub_clear & next_req_last) + nxt_state = REQ_LAST; + else if (sub_clear) + nxt_state = TX; + else + nxt_state = SUB_LAST; + end + REQ_LAST: begin + if (sub_clear) begin + if (align_valid & align_ready & align_last) // Next req's comming and + // is a one-beat req + nxt_state = REQ_LAST; + else if (align_valid & align_ready) // Next req is comming + nxt_state = TX; + else // No incomming next req + nxt_state = IDLE; + end + else + nxt_state = REQ_LAST; + end + default: begin + nxt_state = IDLE; + end + endcase +end +/******************** Stage 3: Output **********************/ +assign splited_tvalid = in_reg_vld; +assign splited_tlast = is_req_last | is_sub_last; +assign splited_tuser = req_type == 4'h2 ? int_tuser : wreq_tuser; +assign splited_tdata = in_reg_data; +assign splited_tkeep = in_reg_keep; + +assign in_reg_rdy = splited_tready; + + +assign in_reg_keep = (sub_dw_left >= 8) ? + `PIO_KEEP_MASK : + (`PIO_KEEP_MASK >> (`PIO_KEEP_W - sub_dw_left)); + +/* -------{DMA Write Request FSM}end------- */ + +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/STD_PIO/rdma_hcr.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/STD_PIO/rdma_hcr.v new file mode 100644 index 0000000000000000000000000000000000000000..9244ae0d08efa47280aea3201e27d6c8f6cca890 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/STD_PIO/rdma_hcr.v @@ -0,0 +1,228 @@ +`timescale 1ns / 100ps +//************************************************************************* +// > File Name: rdma_hcr.v +// > Author : Kangning +// > Date : 2022-06-08 +// > Note : rdma_hcr, Generate configurations for RDMA bar space. +//************************************************************************* + +module rdma_hcr #( + +) ( + + input wire clk , // i, 1 + input wire rst_n, // i, 1 + + /* --------Req Channel{begin}-------- */ + /* pio_head + * | 131 | 130:128 | 127:96 | 95:0 | + * | is_wr | bar_id | addr | cc_head | + */ + input wire pio_hcr_req_valid, // i, 1 + input wire pio_hcr_req_last , // i, 1 + input wire [`PIO_DATA_W-1:0] pio_hcr_req_data , // i, `PIO_DATA_W + input wire [`PIO_HEAD_W-1:0] pio_hcr_req_head , // i, `PIO_HEAD_W + output wire pio_hcr_req_ready, // o, 1 + /* --------Req Channel{end}-------- */ + + /* --------Rsp Channel{begin}-------- */ + /* pio_head + * | 131 | 130:128 | 127:96 | 95:0 | + * | is_wr | bar_id | addr | cc_head | + */ + output wire pio_hcr_rrsp_valid, // o, 1 + output wire pio_hcr_rrsp_last , // o, 1 + output wire [`PIO_DATA_W-1:0] pio_hcr_rrsp_data , // o, `PIO_DATA_W + output wire [`PIO_HEAD_W-1:0] pio_hcr_rrsp_head , // o, `PIO_HEAD_W + input wire pio_hcr_rrsp_ready, // i, 1 + /* -------Rsp Channel{end}-------- */ + + /* -------pio <--> RDMA interface{begin}------- */ + output wire [63:0] pio_hcr_in_param , + output wire [31:0] pio_hcr_in_modifier , + output wire [63:0] pio_hcr_out_dma_addr , + input wire [63:0] pio_hcr_out_param , + output wire [15:0] pio_hcr_token , + input wire [ 7:0] pio_hcr_status , + output wire pio_hcr_go , + input wire pio_hcr_clear , + output wire pio_hcr_event , + output wire [ 7:0] pio_hcr_op_modifier , + output wire [11:0] pio_hcr_op , + /* -------pio <-->RDMA interface{end}------- */ + + /* -------Reset signal{begin}------- */ + output wire cmd_rst , + input wire init_done + /* -------Reset signal{end}------- */ + +`ifdef PCIEI_APB_DBG + /* -------APB reated signal{begin}------- */ + ,input wire [31:0] dbg_sel // debug bus select + ,output wire [31:0] dbg_bus // debug bus data + /* -------APB reated signal{end}------- */ +`endif +); + +/* --------RDMA Bar access FSM{begin}-------- */ +reg [1:0] cur_state, nxt_state; +localparam TRANS = 2'b01, + STALL = 2'b10; +wire is_trans, is_stall; +/* --------RDMA Bar access FSM{end}-------- */ + +/* --------interal logic{begin}-------- */ +wire [10:0] dw_len; +wire is_wr, is_rd; +reg [`PIO_HEAD_W-1:0] head_reg; +/* --------interal logic{end}-------- */ + +/* --------BAR access interface{begin}-------- */ +wire req_vld ; +wire [7 :0] req_wen ; +wire [63:0] req_addr ; +wire [63:0] req_wdata; + +wire [31:0] rrsp_data; +/* --------BAR access interface{end}-------- */ + +`ifdef PCIEI_APB_DBG +/* -------APB reated signal{begin}------- */ +wire [`RDMA_HCR_SIGNAL_W-1:0] dbg_signal_rdma_hcr; +wire [`RDMA_HCR_SPACE_SIGNAL_W-1:0] dbg_signal_space; +/* -------APB reated signal{end}------- */ +`endif + +//--------------------------------------------------------------------------------------------------------------------------- + +`ifdef PCIEI_APB_DBG +/* -------APB reated signal{begin}------- */ + +assign dbg_bus = dbg_signal_rdma_hcr >> {dbg_sel, 5'd0}; + +assign dbg_signal_rdma_hcr = { // 538 + cur_state, nxt_state, // 4 + is_trans, is_stall, // 2 + dw_len, // 11 + is_wr, is_rd, // 2 + head_reg, // 132 + req_vld, req_wen, req_addr, req_wdata, // 137 + rrsp_data, // 32 + dbg_signal_space // 218 +}; +/* -------APB reated signal{end}------- */ +`endif + +/* -------{RDMA Bar access FSM}begin------- */ +/******************** Stage 1: State Register **********************/ +assign is_trans = (cur_state == TRANS); +assign is_stall = (cur_state == STALL); + +always @(posedge clk, negedge rst_n) begin + if(~rst_n) + cur_state <= `TD TRANS; + else + cur_state <= `TD nxt_state; +end + +/******************** Stage 2: State Transition **********************/ +always @(*) begin + case(cur_state) + TRANS: begin + if (pio_hcr_req_valid & pio_hcr_req_ready & pio_hcr_req_last & is_rd) begin + nxt_state = STALL; + end + else begin + nxt_state = TRANS; + end + end + STALL: begin + if (pio_hcr_rrsp_valid & pio_hcr_rrsp_ready & pio_hcr_rrsp_last) begin + nxt_state = TRANS; + end + else begin + nxt_state = STALL; + end + end + default: begin + nxt_state = TRANS; + end + endcase +end + +/******************** Stage 3: Output **********************/ + +// Interal logic +assign dw_len = pio_hcr_req_head[42:32]; +assign is_wr = pio_hcr_req_head[131]; +assign is_rd = !is_wr; +always @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + head_reg <= `TD 0; + end + else if (pio_hcr_req_valid & pio_hcr_req_ready & pio_hcr_req_last & is_rd) begin + head_reg <= `TD pio_hcr_req_head; + end +end + +// Rsp channel +assign pio_hcr_rrsp_head = head_reg; +assign pio_hcr_rrsp_data = {192'd0, 32'd0, rrsp_data}; +assign pio_hcr_rrsp_last = pio_hcr_rrsp_valid; + +// Req channel +assign pio_hcr_req_ready = is_trans; + +// BAR access interface +assign req_vld = is_trans & pio_hcr_req_valid; +assign req_wen = ((dw_len == 1) & is_trans & is_wr) ? 8'h0f : + ((dw_len == 2) & is_trans & is_wr) ? 8'hff : 0; +assign req_addr = pio_hcr_req_valid ? pio_hcr_req_head[127:96] : 0; +assign req_wdata = is_wr ? pio_hcr_req_data[63:0] : 0; +/* -------{RDMA bar access FSM}end------- */ + +rdma_hcr_space #( + +) rdma_hcr_space ( + + .clk ( clk ), + .rst_n ( rst_n ), + + /* -------pio <--> RDMA interface{begin}------- */ + .pio_hcr_in_param ( pio_hcr_in_param ), // o, 64 + .pio_hcr_in_modifier ( pio_hcr_in_modifier ), // o, 32 + .pio_hcr_out_dma_addr ( pio_hcr_out_dma_addr ), // o, 64 + .pio_hcr_out_param ( pio_hcr_out_param ), // i, 64 + .pio_hcr_token ( pio_hcr_token ), // o, 16 + .pio_hcr_status ( pio_hcr_status ), // i, 8 + .pio_hcr_go ( pio_hcr_go ), // o, 1 + .pio_hcr_clear ( pio_hcr_clear ), // i, 1 + .pio_hcr_event ( pio_hcr_event ), // o, 1 + .pio_hcr_op_modifier ( pio_hcr_op_modifier ), // o, 8 + .pio_hcr_op ( pio_hcr_op ), // o, 12 + /* -------pio <--> RDMA interface{end}------- */ + + /* -------Reset signal{begin}------- */ + .is_rst ( cmd_rst ), // o, 1 + .init_done ( init_done ), // i, 1 + /* -------Reset signal{end}------- */ + + /* -------Access BAR space Interface{begin}------- */ + .req_vld ( req_vld ), // i, 1 + .req_wen ( req_wen ), // i, 8 + .req_addr ( req_addr ), // i, 64 + .req_wdata ( req_wdata ), // i, 64 + + .rsp_valid ( pio_hcr_rrsp_valid ), // o, 1 + .rsp_rdata ( rrsp_data ), // o, 32 + .rsp_ready ( pio_hcr_rrsp_ready ) // i, 1 + /* -------Access BAR space Interface{end}------- */ + +`ifdef PCIEI_APB_DBG + /* -------APB reated signal{begin}------- */ + ,.dbg_signal ( dbg_signal_space ) // o, `RDMA_HCR_SPACE_SIGNAL_W + /* -------APB reated signal{end}------- */ +`endif +); + +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/STD_PIO/rdma_hcr_space.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/STD_PIO/rdma_hcr_space.v new file mode 100644 index 0000000000000000000000000000000000000000..65cf42c4cbafd7f3fd5e4d3058836c6eb0dd574c --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/STD_PIO/rdma_hcr_space.v @@ -0,0 +1,259 @@ +`timescale 1ns / 100ps +//************************************************************************* +// > File : rdma_hcr_space.v +// > Author : Kangning +// > Date : 2020-08-17 +// > Note : Store the content of RDMA BAR space +// > V0.5 -- Only support BAR0-1 space (HCR) +// > V1.0 -- Support BAR0-1 and BAR 2-3 +// > V1.1 -- Divide clock domain between PCIe and RDMA +// > V1.2 -- Put async fifo behind the module. HCR register can interact +// > with CEU directly. +// > V1.3 -- Remove BAR 2-3 related logic +//************************************************************************* + +module rdma_hcr_space #( + +) ( + input wire clk, + input wire rst_n, + + + /* -------pio <--> RDMA interface (in clk domain){begin}------- */ + output wire [63:0] pio_hcr_in_param , + output wire [31:0] pio_hcr_in_modifier , + output wire [63:0] pio_hcr_out_dma_addr , + input wire [63:0] pio_hcr_out_param , + output wire [15:0] pio_hcr_token , + input wire [ 7:0] pio_hcr_status , + output wire pio_hcr_go , + input wire pio_hcr_clear , + output wire pio_hcr_event , + output wire [ 7:0] pio_hcr_op_modifier , + output wire [11:0] pio_hcr_op , + /* -------pio <-->RDMA interface (in clk domain){end}------- */ + + /* -------Reset signal{begin}------- */ + output reg is_rst, + input wire init_done, + /* -------Reset signal{end}------- */ + + /* -------Access BAR space Interface{begin}------- */ + input wire req_vld , // i, 1 + input wire [7 :0] req_wen , // i, 8 + input wire [63:0] req_addr , // i, 64 + input wire [63:0] req_wdata, // i, 64 + + output reg rsp_valid, // o, 1 + output reg [31:0] rsp_rdata, // o, 64 + input wire rsp_ready // i, 1 + /* -------Access BAR space Interface{end}------- */ + +`ifdef PCIEI_APB_DBG + /* -------APB reated signal{begin}------- */ + ,output wire [`RDMA_HCR_SPACE_SIGNAL_W-1:0] dbg_signal // o, `RDMA_HCR_SPACE_SIGNAL_W + /* -------APB reated signal{end}------- */ +`endif +); +/* ------- BAR irrelevant{begin}------- */ +// bar rd || wr +wire req_ren; + +// BAR address selection, write of less than 32 bits to BAR space don't work. +wire bar0_0_hit ; +wire bar0_1_hit ; +wire bar0_2_hit ; +wire bar0_3_hit ; +wire bar0_4_hit ; +wire bar0_5_hit ; +wire bar0_6_hit ; +wire bar0_init_done_hit; +wire bar0_rst_hit ; +/* ------- BAR irrelevant{end}------- */ + +/* -------BAR0 variable{begin}------- */ + +wire set_rst; + +reg [63:0] reg_in_param ; +reg [31:0] reg_in_modifier; +reg [63:0] reg_out_param ; +reg [15:0] reg_token ; +reg [ 7:0] reg_status ; +reg reg_go ; +reg reg_event ; +reg [ 7:0] reg_op_modifier; +reg [11:0] reg_op ; + +wire bar0_en; +/* -------BAR0 variable{end}------- */ + +//---------------------------------------------------------------------------------------------------------------------- + +`ifdef PCIEI_APB_DBG +/* -------APB reated signal{begin}------- */ + +assign dbg_signal = { // 218 + req_ren, // 1 + bar0_0_hit, bar0_1_hit, bar0_2_hit, bar0_3_hit, bar0_4_hit, bar0_5_hit, bar0_6_hit, bar0_init_done_hit, bar0_rst_hit, // 9 + set_rst, // 1 + reg_in_param, reg_in_modifier, reg_out_param, reg_token, reg_status, reg_go, reg_event, reg_op_modifier, reg_op, // 206 + bar0_en // 1 +}; + +/* -------APB reated signal{end}------- */ +`endif + +/* -------BAR irrelevant{bagin}------- */ +// BAR rd || wr +assign req_ren = req_vld & !(|req_wen); + +// BAR address selection +assign bar0_0_hit = req_addr[19:0] == 20'h00 + `HCR_BASE; +assign bar0_1_hit = req_addr[19:0] == 20'h04 + `HCR_BASE; +assign bar0_2_hit = req_addr[19:0] == 20'h08 + `HCR_BASE; +assign bar0_3_hit = req_addr[19:0] == 20'h0C + `HCR_BASE; +assign bar0_4_hit = req_addr[19:0] == 20'h10 + `HCR_BASE; +assign bar0_5_hit = req_addr[19:0] == 20'h14 + `HCR_BASE; +assign bar0_6_hit = req_addr[19:0] == 20'h18 + `HCR_BASE; + +assign bar0_init_done_hit = req_addr[19:0] == `INIT_DONE_OFFSET; +assign bar0_rst_hit = req_addr[19:0] == `CMD_RST_OFFSET; // BAR0-1 has 1MB space, which is 20 bits +/* -------BAR irrelevant{end}------- */ + + +/* -------BAR0 logic{begin}------- */ +assign bar0_en = req_vld; + +always @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + reg_in_param <= `TD 0; + end + else if ((req_wen == 8'hf) && bar0_en && bar0_0_hit) begin + reg_in_param <= `TD {req_wdata[31:0], reg_in_param[31:0]}; + end + else if ((req_wen == 8'hf) && bar0_en && bar0_1_hit) begin + reg_in_param <= `TD {reg_in_param[63:32], req_wdata[31:0]}; + end +end + +always @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + reg_in_modifier <= `TD 0; + end + else if ((req_wen == 8'hf) && bar0_en && bar0_2_hit) begin + reg_in_modifier <= `TD req_wdata[31:0]; + end +end + +always @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + reg_out_param <= `TD 64'h0; + end + else if (pio_hcr_clear) begin + reg_out_param <= `TD pio_hcr_out_param; + end + else if ((req_wen == 8'hf) && bar0_en && bar0_3_hit) begin + reg_out_param <= `TD {req_wdata[31:0], reg_out_param[31:0]}; + end + else if ((req_wen == 8'hf) && bar0_en && bar0_4_hit) begin + reg_out_param <= `TD {reg_out_param[63:32], req_wdata[31:0]}; + end +end + +always @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + reg_token <= `TD 16'd0; + end + else if ((req_wen == 8'hf) && bar0_en && bar0_5_hit) begin + reg_token <= `TD req_wdata[31:16]; + end +end + +always @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + reg_status <= `TD 8'd0; + reg_go <= `TD 1'd0; + reg_event <= `TD 1'd0; + reg_op_modifier <= `TD 8'd0; + reg_op <= `TD 12'd0; + end + else if (pio_hcr_clear) begin + reg_status <= `TD pio_hcr_status; + reg_go <= `TD 1'd0; + end + else if ((req_wen == 8'hf) && bar0_en && bar0_6_hit) begin + reg_status <= `TD req_wdata[31:24]; + reg_go <= `TD req_wdata[23]; + reg_event <= `TD req_wdata[22]; + reg_op_modifier <= `TD req_wdata[19:12]; + reg_op <= `TD req_wdata[11:0]; + end +end + +assign set_rst = bar0_rst_hit & (req_wen[3:0] == 8'hf) & req_wdata[0]; +always @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + is_rst <= `TD 0; + end + else if (bar0_en & set_rst) begin + is_rst <= `TD 1; + end + else begin + is_rst <= `TD 1'b0; + end +end + +always @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + rsp_rdata <= `TD 32'd0; + rsp_valid <= `TD 1'd0 ; + end + else if (req_ren && bar0_en) begin + if (bar0_0_hit) begin + rsp_rdata <= `TD reg_in_param[63:32]; + end + else if (bar0_1_hit) begin + rsp_rdata <= `TD reg_in_param[31:0]; + end + else if (bar0_2_hit) begin + rsp_rdata <= `TD reg_in_modifier; + end + else if (bar0_3_hit) begin + rsp_rdata <= `TD reg_out_param[63:32]; + end + else if (bar0_4_hit) begin + rsp_rdata <= `TD reg_out_param[31:0]; + end + else if (bar0_5_hit) begin + rsp_rdata <= `TD {reg_token, 16'd0}; + end + else if (bar0_6_hit) begin + rsp_rdata <= `TD {reg_status, reg_go, reg_event, 2'd0, reg_op_modifier, reg_op}; + end + else if (bar0_init_done_hit) begin + rsp_rdata <= `TD init_done; + end + else begin + rsp_rdata <= `TD 32'd0; + end + rsp_valid <= `TD 1'd1 ; + end + else if (rsp_valid & rsp_ready) begin + rsp_rdata <= `TD 32'd0; + rsp_valid <= `TD 1'd0 ; + end +end + +// in clk domain +assign pio_hcr_in_param = reg_in_param ; +assign pio_hcr_in_modifier = reg_in_modifier; +assign pio_hcr_out_dma_addr= reg_out_param ; +assign pio_hcr_token = reg_token ; +assign pio_hcr_go = reg_go ; +assign pio_hcr_event = reg_event ; +assign pio_hcr_op_modifier = reg_op_modifier; +assign pio_hcr_op = reg_op ; +/* -------BAR0 logic in clk domain{end}------- */ + +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/STD_PIO/rdma_int.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/STD_PIO/rdma_int.v new file mode 100644 index 0000000000000000000000000000000000000000..0a9c85d6712d678ec39c71d34cd0055acb895245 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/STD_PIO/rdma_int.v @@ -0,0 +1,388 @@ +`timescale 1ns / 100ps +//************************************************************************* +// > File Name: rdma_int.v +// > Author : Kangning +// > Date : 2022-08-11 +// > Note : rdma_int, Generate configurations for RDMA MSI-X interrupt vector. +//************************************************************************* + +module rdma_int #( + parameter HCA_INT_LEN = 20'h400 +) ( + input wire clk , // i, 1 + input wire rst_n, // i, 1 + + /* --------Req Channel{begin}-------- */ + /* pio_head + * | 131 | 130:128 | 127:96 | 95:0 | + * | is_wr | bar_id | addr | cc_head | + */ + input wire [`PIO_DATA_W-1:0] pio_int_req_data , // i, `PIO_DATA_W + input wire [`PIO_HEAD_W-1:0] pio_int_req_head , // i, `PIO_HEAD_W + input wire pio_int_req_last , // i, 1 + input wire pio_int_req_valid , // i, 1 + output wire pio_int_req_ready , // o, 1 + /* --------Req Channel{end}-------- */ + + /* --------Rsp Channel{begin}-------- */ + /* pio_head + * | 131 | 130:128 | 127:96 | 95:0 | + * | is_wr | bar_id | addr | cc_head | + */ + output wire [`PIO_DATA_W-1:0] pio_int_rrsp_data , // o, `PIO_DATA_W + output wire [`PIO_HEAD_W-1:0] pio_int_rrsp_head , // o, `PIO_HEAD_W + output wire pio_int_rrsp_last , // o, 1 + output wire pio_int_rrsp_valid, // o, 1 + input wire pio_int_rrsp_ready, // i, 1 + /* -------Rsp Channel{end}-------- */ + + /* --------Rsp Channel{begin}-------- */ + input wire in_pio_eq_int_req_valid, // i, 1 + input wire [`RDMA_MSIX_NUM_LOG-1:0] in_pio_eq_int_req_num , // i, `RDMA_MSIX_NUM_LOG + output wire in_pio_eq_int_req_ready, // o, 1 + + output wire out_pio_eq_int_rsp_valid, // o, 1 + output wire [`RDMA_MSIX_DATA_W -1:0] out_pio_eq_int_rsp_data , // o, `RDMA_MSIX_DATA_W + input wire out_pio_eq_int_rsp_ready // i, 1 + /* -------Rsp Channel{end}-------- */ + +`ifdef PCIEI_APB_DBG + /* -------APB reated signal{begin}------- */ + ,input wire [4*`SRAM_RW_DATA_W-1:0] rw_data // i, 4*`SRAM_RW_DATA_W + ,input wire [31:0] dbg_sel // i, 32 + ,output wire [31:0] dbg_bus // o, 32 + /* -------APB reated signal{end}------- */ +`endif +); + +localparam ENTRY_DW_WIDTH = 32; +localparam ENTRY_DW_NUM = 4; +localparam MSIX_TABLE_SZ = (ENTRY_DW_WIDTH * ENTRY_DW_NUM / 8) << `RDMA_MSIX_NUM_LOG; + +/* --------Stream reg in&out{begin}-------- */ +wire pio_eq_int_req_valid; +wire [`RDMA_MSIX_NUM_LOG-1:0] pio_eq_int_req_num ; +wire pio_eq_int_req_ready; + +wire pio_eq_int_rsp_valid; +wire [`RDMA_MSIX_DATA_W -1:0] pio_eq_int_rsp_data ; +wire pio_eq_int_rsp_ready; +/* --------Stream reg in&out{end}-------- */ + +/* --------Upper State Machine{begin}-------- */ +localparam UPPER_REQ = 3'b001, + UPPER_READ = 3'b010, + UPPER_RSP = 3'b100; + +reg [2:0] upper_cur_state, upper_nxt_state; +wire is_upper_req, is_upper_read, is_upper_rsp; + +wire is_wr ; +wire [31:0] req_addr; +wire [95:0] cc_head ; +wire [1 :0] offset ; + +reg [95:0] cc_head_reg ; +reg [31:0] addr_reg ; +reg [1 :0] offset_reg ; +reg [31:0] upper_dout_reg; +/* --------Upper State Machine{end}-------- */ + +/* --------Down State Machine{begin}-------- */ +localparam DOWN_REQ = 3'b001, + DOWN_READ = 3'b010, + DOWN_RSP = 3'b100; + +reg [2:0] down_cur_state, down_nxt_state; +wire is_down_req, is_down_read, is_down_rsp; + +reg [127:0] down_dout_reg; +/* --------Down State Machine{end}-------- */ + +/* --------Signals related to SRAM{begin}-------- */ +wire upper_we [ENTRY_DW_NUM-1:0]; +wire [`RDMA_MSIX_NUM_LOG -1:0] upper_addr[ENTRY_DW_NUM-1:0]; +wire [ENTRY_DW_WIDTH-1:0] upper_din [ENTRY_DW_NUM-1:0]; +wire [ENTRY_DW_WIDTH-1:0] upper_dout[ENTRY_DW_NUM-1:0]; + +// wire down_we [ENTRY_DW_NUM-1:0]; +wire [`RDMA_MSIX_NUM_LOG -1:0] down_addr[ENTRY_DW_NUM-1:0]; +// wire [ENTRY_DW_WIDTH-1:0] down_din [ENTRY_DW_NUM-1:0]; +wire [ENTRY_DW_WIDTH-1:0] down_dout[ENTRY_DW_NUM-1:0]; +/* --------Signals related to SRAM{end}-------- */ + +`ifdef PCIEI_APB_DBG +/* -------APB reated signal{begin}------- */ +wire [`RDMA_INT_SIGNAL_W-1:0] dbg_signal_rdma_int; +wire [ENTRY_DW_NUM*2-1:0] rtsel; +wire [ENTRY_DW_NUM*2-1:0] wtsel; +wire [ENTRY_DW_NUM*2-1:0] ptsel; +wire [ENTRY_DW_NUM*1-1:0] vg ; +wire [ENTRY_DW_NUM*1-1:0] vs ; +/* -------APB reated signal{end}------- */ +`endif + +//--------------------------------------------------------------------------------------------------------------------------- + +`ifdef PCIEI_APB_DBG +/* -------APB reated signal{begin}------- */ +assign {rtsel, wtsel, ptsel, vg, vs} = rw_data; +assign dbg_bus = dbg_signal_rdma_int >> {dbg_sel, 5'd0}; + +generate +if (ENTRY_DW_NUM == 4) begin:DBG_CHNL4 + + assign dbg_signal_rdma_int = { // 1013 + pio_eq_int_req_valid, pio_eq_int_req_num, pio_eq_int_req_ready, // 8 + pio_eq_int_rsp_valid, pio_eq_int_rsp_data , pio_eq_int_rsp_ready, // 130 + upper_cur_state, upper_nxt_state, // 6 + is_upper_req, is_upper_read, is_upper_rsp, // 3 + is_wr, req_addr, cc_head, offset, // 131 + cc_head_reg, addr_reg, offset_reg, upper_dout_reg, // 162 + down_cur_state, down_nxt_state, // 6 + is_down_req, is_down_read, is_down_rsp, // 3 + down_dout_reg, // 128 + + upper_we[3], upper_addr[3], upper_din[3], upper_dout[3], down_addr[3], down_dout[3], + upper_we[2], upper_addr[2], upper_din[2], upper_dout[2], down_addr[2], down_dout[2], + upper_we[1], upper_addr[1], upper_din[1], upper_dout[1], down_addr[1], down_dout[1], + upper_we[0], upper_addr[0], upper_din[0], upper_dout[0], down_addr[0], down_dout[0] // 109*4 = 436 + }; + +end +endgenerate + +/* -------APB reated signal{end}------- */ +`endif + +/* --------Stream reg in&out{begin}-------- */ +st_reg #( + .TUSER_WIDTH ( 1 ), // unused + .TDATA_WIDTH ( `RDMA_MSIX_NUM_LOG ) // 6 +) int_req_st_reg ( + .clk ( clk ), // i, 1 + .rst_n ( rst_n ), // i, 1 + + /* -------input axis-like interface{begin}------- */ + .axis_tvalid ( in_pio_eq_int_req_valid ), // i, 1 + .axis_tlast ( 1'b1 ), // i, 1 + .axis_tuser ( 1'b0 ), // i, TUSER_WIDTH + .axis_tdata ( in_pio_eq_int_req_num ), // i, TDATA_WIDTH + .axis_tready ( in_pio_eq_int_req_ready ), // o, 1 + /* -------input axis-like interface{end}------- */ + + /* -------output st_reg inteface{begin}------- */ + .axis_reg_tvalid ( pio_eq_int_req_valid ), // o, 1 + .axis_reg_tlast ( ), // o, 1 + .axis_reg_tuser ( ), // o, TUSER_WIDTH + .axis_reg_tdata ( pio_eq_int_req_num ), // o, TDATA_WIDTH + .axis_reg_tready ( pio_eq_int_req_ready ) // i, 1 + /* -------output st_reg inteface{end}------- */ +); + +st_reg #( + .TUSER_WIDTH ( 1 ), // unused + .TDATA_WIDTH ( 128 ) +) int_rsp_st_reg ( + .clk ( clk ), // i, 1 + .rst_n ( rst_n ), // i, 1 + + /* -------input axis-like interface{begin}------- */ + .axis_tvalid ( pio_eq_int_rsp_valid ), // i, 1 + .axis_tlast ( 1'b1 ), // i, 1 + .axis_tuser ( 1'b0 ), // i, TUSER_WIDTH + .axis_tdata ( pio_eq_int_rsp_data ), // i, TDATA_WIDTH + .axis_tready ( pio_eq_int_rsp_ready ), // o, 1 + /* -------input axis-like interface{end}------- */ + + /* -------output st_reg inteface{begin}------- */ + .axis_reg_tvalid ( out_pio_eq_int_rsp_valid ), // o, 1 + .axis_reg_tlast ( ), // o, 1 + .axis_reg_tuser ( ), // o, TUSER_WIDTH + .axis_reg_tdata ( out_pio_eq_int_rsp_data ), // o, TDATA_WIDTH + .axis_reg_tready ( out_pio_eq_int_rsp_ready ) // i, 1 + /* -------output st_reg inteface{end}------- */ +); +/* --------Stream reg in&out{end}-------- */ + +/* -------{Upper Interrupt table access FSM}begin------- */ +assign is_wr = pio_int_req_head[131]; +assign req_addr = pio_int_req_head[127:96]; +assign cc_head = pio_int_req_head[95:0]; +assign offset = req_addr[3:2]; + +assign is_upper_req = upper_cur_state == UPPER_REQ; +assign is_upper_read = upper_cur_state == UPPER_READ; +assign is_upper_rsp = upper_cur_state == UPPER_RSP; +/******************** Stage 1: State Register **********************/ + +always @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + cc_head_reg <= `TD 0; + addr_reg <= `TD 0; + offset_reg <= `TD 0; + end + else if (is_upper_req & pio_int_req_valid & !is_wr) begin + cc_head_reg <= `TD cc_head ; + addr_reg <= `TD req_addr; + offset_reg <= `TD offset ; + end +end + +always @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + upper_dout_reg <= `TD 0; + end + else if (is_upper_read) begin + upper_dout_reg <= `TD upper_dout[offset_reg]; + end +end + +always @(posedge clk, negedge rst_n) begin + if(~rst_n) + upper_cur_state <= `TD UPPER_REQ; + else + upper_cur_state <= `TD upper_nxt_state; +end + +/******************** Stage 2: State Transition **********************/ +always @(*) begin + case(upper_cur_state) + UPPER_REQ: begin + if (pio_int_req_valid & !is_wr) begin + upper_nxt_state = UPPER_READ; + end + else begin + upper_nxt_state = UPPER_REQ; + end + end + UPPER_READ: begin + upper_nxt_state = UPPER_RSP; + end + UPPER_RSP: begin + if (pio_int_rrsp_ready) begin + upper_nxt_state = UPPER_REQ; + end + else begin + upper_nxt_state = UPPER_RSP; + end + end + default: begin + upper_nxt_state = UPPER_REQ; + end + endcase +end +/******************** Stage 3: Output **********************/ +assign pio_int_req_ready = is_upper_req; + +assign pio_int_rrsp_data = upper_dout_reg; +assign pio_int_rrsp_head = {4'd0, addr_reg, cc_head_reg}; +assign pio_int_rrsp_last = is_upper_rsp; +assign pio_int_rrsp_valid = is_upper_rsp; +/* -------{Upper Interrupt table access FSM}end------- */ + + +/* --------MSI-X Interruptt Table{begin}-------- */ +genvar i; +generate +for (i = 0; i < ENTRY_DW_NUM; i = i + 1) begin:ENTRY_DW + +assign upper_we [i] = (offset == i) & is_wr; +assign upper_addr[i] = req_addr[`RDMA_MSIX_NUM_LOG-1+4:4]; +assign upper_din [i] = pio_int_req_data[ENTRY_DW_WIDTH-1:0]; + +assign down_addr[i] = pio_eq_int_req_num; + +pcieifc_td_sram #( + .DATAWIDTH ( ENTRY_DW_WIDTH ), // Memory data word width, 32 + .ADDRWIDTH ( `RDMA_MSIX_NUM_LOG ) // 64 entries +) entry_dw ( + .clk ( clk ), // i, 1 + .rst_n ( rst_n ), // i, 1 + + .wea ( upper_we [i] ), // i, 1 + .addra ( upper_addr[i] ), // i, ADDRWIDTH + .dina ( upper_din [i] ), // i, DATAWIDTH + .douta ( upper_dout[i] ), // o, DATAWIDTH + + .web ( 1'd0 ), // i, 1 + .addrb ( down_addr[i] ), // i, ADDRWIDTH + .dinb ({ENTRY_DW_WIDTH{1'b0}}), // i, DATAWIDTH + .doutb ( down_dout[i] ) // o, DATAWIDTH + +`ifdef PCIEI_APB_DBG + ,.rtsel ( rtsel[(i+1)*2-1:i*2] ) // i, 2 + ,.wtsel ( wtsel[(i+1)*2-1:i*2] ) // i, 2 + ,.ptsel ( ptsel[(i+1)*2-1:i*2] ) // i, 2 + ,.vg ( vg [i] ) // i, 1 + ,.vs ( vs [i] ) // i, 1 +`endif +); + +end +endgenerate +/* --------MSI-X Interruptt Table{end}-------- */ + +/* -------{Down Interrupt table access FSM}begin------- */ +assign is_down_req = down_cur_state == DOWN_REQ; +assign is_down_read = down_cur_state == DOWN_READ; +assign is_down_rsp = down_cur_state == DOWN_RSP; + +/******************** Stage 1: State Register **********************/ +always @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + down_dout_reg <= `TD 0; + end + else if (is_down_read) begin + down_dout_reg <= `TD {down_dout[3], down_dout[2], down_dout[1], down_dout[0]}; + end +end + +always @(posedge clk, negedge rst_n) begin + if(~rst_n) + down_cur_state <= `TD DOWN_REQ; + else + down_cur_state <= `TD down_nxt_state; +end + +/******************** Stage 2: State Transition **********************/ +always @(*) begin + case(down_cur_state) + DOWN_REQ: begin + if (pio_eq_int_req_valid) begin + down_nxt_state = DOWN_READ; + end + else begin + down_nxt_state = DOWN_REQ; + end + end + DOWN_READ: begin + if (pio_eq_int_rsp_ready) begin + down_nxt_state = DOWN_REQ; + end + else begin + down_nxt_state = DOWN_RSP; + end + end + DOWN_RSP: begin + if (pio_eq_int_rsp_ready) begin + down_nxt_state = DOWN_REQ; + end + else begin + down_nxt_state = DOWN_RSP; + end + end + default: begin + down_nxt_state = DOWN_REQ; + end + endcase +end +/******************** Stage 3: Output **********************/ +assign pio_eq_int_req_ready = is_down_req; // o, 1 + +assign pio_eq_int_rsp_valid = is_down_read | is_down_rsp; // o, 1 +assign pio_eq_int_rsp_data = is_down_read ? {down_dout[3], down_dout[2], down_dout[1], down_dout[0]} : down_dout_reg; // o, 128 + +/* -------{Down Interrupt table access FSM}end------- */ + +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/STD_PIO/rdma_uar.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/STD_PIO/rdma_uar.v new file mode 100644 index 0000000000000000000000000000000000000000..8ac9b30b95c3b59d62d75783813bf027c83f5ee4 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/STD_PIO/rdma_uar.v @@ -0,0 +1,321 @@ +`timescale 1ns / 100ps +//************************************************************************* +// > File Name: rdma_uar.v +// > Author : Kangning +// > Date : 2022-08-11 +// > Note : rdma_uar, Generate configurations for RDMA uar space. +// > 1. This space is accessed in 64-bit. +// > 2. This space is write only for driver. +//************************************************************************* + +module rdma_uar #( + +) ( + input wire clk , // i, 1 + input wire rst_n, // i, 1 + + /* --------Req Channel{begin}-------- */ + /* pio_head + * | 131 | 130:128 | 127:96 | 95:0 | + * | is_wr | bar_id | addr | cc_head | + */ + input wire [`PIO_DATA_W-1:0] pio_uar_req_data , // i, `PIO_DATA_W + input wire [`PIO_HEAD_W-1:0] pio_uar_req_head , // i, `PIO_HEAD_W + input wire pio_uar_req_last , // i, 1 + input wire pio_uar_req_valid , // i, 1 + output wire pio_uar_req_ready , // o, 1 + /* --------Req Channel{end}-------- */ + + /* --------SQ Doorbell{begin}-------- */ + output wire pio_uar_db_valid, // o, 1 + output wire [63:0] pio_uar_db_data , // o, 64 + input wire pio_uar_db_ready, // i, 1 + /* --------SQ Doorbell{end}-------- */ + + /* --------ARM CQ interface{begin}-------- */ + input wire cq_ren , // i, 1 + input wire [31:0] cq_num , // i, 32 + output reg cq_dout_reg, // o, 1 + /* --------ARM CQ interface{end}-------- */ + + /* --------ARM EQ interface{begin}-------- */ + input wire eq_ren , // i, 1 + input wire [31:0] eq_num , // i, 31 + output reg eq_dout_reg // o, 1 + /* --------ARM EQ interface{end}-------- */ + +`ifdef PCIEI_APB_DBG + /* -------APB reated signal{begin}------- */ + ,input wire [2*`SRAM_RW_DATA_W-1:0] rw_data // i, 2*`SRAM_RW_DATA_W + ,input wire [31:0] dbg_sel // debug bus select + ,output wire [31:0] dbg_bus // debug bus data + /* -------APB reated signal{end}------- */ +`endif +); + +localparam CQ_NUM_LOG = 13; +localparam EQ_NUM_LOG = 5 ; + +/* --------requet parse{begin}-------- */ +wire [31:0] req_addr; +wire is_set_sq_db, is_arm_cq, is_arm_eq; +/* --------requet parse{end}-------- */ + + +/* -------SQ Doorbell{begin}------- */ +reg db_wen ; +reg [63:0] db_din ; +wire db_full; + +wire db_ren ; +wire [63:0] db_dout ; +wire db_empty; +/* -------SQ Doorbell{end}------- */ + +/* -------ARM CQ{begin}------- */ +reg cq_update_reg; +reg [CQ_NUM_LOG-1:0] cq_addr_reg; + +wire arm_cq_we ; +wire [CQ_NUM_LOG-1:0] arm_cq_addr; +wire arm_cq_din ; + +wire cq_dout; +/* -------ARM CQ{end}------- */ + +/* -------ARM EQ{begin}------- */ +reg eq_update_reg; +reg [EQ_NUM_LOG-1:0] eq_addr_reg; + +wire arm_eq_we ; +wire [EQ_NUM_LOG-1:0] arm_eq_addr; +wire arm_eq_din ; + +wire eq_dout; +/* -------ARM EQ{end}------- */ + +`ifdef PCIEI_APB_DBG +/* -------APB reated signal{begin}------- */ +wire [`RDMA_UAR_SIGNAL_W-1:0] dbg_signal_rdma_uar; +wire [1:0] db_rtsel, cq_rtsel; +wire [1:0] db_wtsel, cq_wtsel; +wire [1:0] db_ptsel, cq_ptsel; +wire db_vg , cq_vg ; +wire db_vs , cq_vs ; +/* -------APB reated signal{end}------- */ +`endif + +//--------------------------------------------------------------------------------------------------------------------------- + +`ifdef PCIEI_APB_DBG +/* -------APB reated signal{begin}------- */ +assign {db_rtsel, db_wtsel, db_ptsel, db_vg, db_vs, + cq_rtsel, cq_wtsel, cq_ptsel, cq_vg, cq_vs} = rw_data; +assign dbg_bus = dbg_signal_rdma_uar >> {dbg_sel, 5'd0}; + +assign dbg_signal_rdma_uar = { // 211 + req_addr, is_set_sq_db, is_arm_cq, is_arm_eq, // 35 + db_wen, db_din, db_full, // 66 + db_ren, db_dout, db_empty, // 66 + cq_update_reg, cq_addr_reg, // 14 + arm_cq_we, arm_cq_addr, arm_cq_din, // 15 + cq_dout, // 1 + eq_update_reg, eq_addr_reg, // 6 + arm_eq_we, arm_eq_addr, arm_eq_din, // 7 + eq_dout // 1 +}; +/* -------APB reated signal{end}------- */ +`endif + +/* --------requet parse{begin}-------- */ +assign req_addr = pio_uar_req_head[127:96]; + +assign is_set_sq_db = (req_addr[11:0] == `DOORBELL_BASE) & pio_uar_req_valid; +assign is_arm_cq = (req_addr[11:0] == `ARM_CQ_BASE ) & pio_uar_req_valid; +assign is_arm_eq = (req_addr[11:0] == `ARM_EQ_BASE ) & pio_uar_req_valid; + +assign pio_uar_req_ready = 1; +/* --------requet parse{end}-------- */ + + +/* -------BAR2 logic{begin}------- */ +// Write Doorbell to FIFO +always @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + db_wen <= `TD 0; + db_din <= `TD 0; + end + else if (db_wen & !db_full) begin + db_wen <= `TD 0; + db_din <= `TD 0; + end + else if (is_set_sq_db) begin + db_wen <= `TD 1; + db_din <= `TD pio_uar_req_data[63:0]; + end +end + +pcieifc_sync_fifo #( + .DSIZE ( 64 ), + .ASIZE ( 6 ) // 64 depth +) doobell_sync_fifo ( + .clk ( clk ), // i, 1 + .rst_n ( rst_n ), // i, 1 + .clr ( 1'd0 ), // i, 1 + + .wen ( db_wen ), // i, 1 + .din ( db_din ), // i, 64 + .full ( db_full ), // o, 1 + + .ren ( db_ren ), // i, 1; pio_uar_db_ready + .dout ( db_dout ), // o, 64 + .empty ( db_empty ) // o, 1 + +`ifdef PCIEI_APB_DBG + ,.rtsel ( db_rtsel ) // i, 2 + ,.wtsel ( db_wtsel ) // i, 2 + ,.ptsel ( db_ptsel ) // i, 2 + ,.vg ( db_vg ) // i, 1 + ,.vs ( db_vs ) // i, 1 +`endif +); + +st_reg #( + .TUSER_WIDTH ( 1 ), // unused + .TDATA_WIDTH ( 64 ) +) uar_db_st_reg ( + .clk ( clk ), // i, 1 + .rst_n ( rst_n ), // i, 1 + + /* -------input axis-like interface{begin}------- */ + .axis_tvalid ( !db_empty ), // i, 1 + .axis_tlast ( 1'b1 ), // i, 1 + .axis_tuser ( 1'b0 ), // i, TUSER_WIDTH + .axis_tdata ( db_dout ), // i, TDATA_WIDTH + .axis_tready ( db_ren ), // o, 1 + /* -------input axis-like interface{end}------- */ + + /* -------output st_reg inteface{begin}------- */ + .axis_reg_tvalid ( pio_uar_db_valid ), // o, 1 + .axis_reg_tlast ( ), // o, 1 + .axis_reg_tuser ( ), // o, TUSER_WIDTH + .axis_reg_tdata ( pio_uar_db_data ), // o, TDATA_WIDTH + .axis_reg_tready ( pio_uar_db_ready ) // i, 1 + /* -------output st_reg inteface{end}------- */ +); +/* -------SQ Doorbell Logic{end}------- */ + + +/* -------ARM CQ Logic{begin}------- */ +always @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + cq_update_reg <= `TD 0; + cq_addr_reg <= `TD 0; + end + else if (cq_update_reg & (!is_arm_cq | !cq_dout)) begin // 1. clear when armed cq is not written + // 2. clear when cq is not armed + cq_update_reg <= `TD 0; + cq_addr_reg <= `TD 0; + end + else if (cq_ren) begin + cq_update_reg <= `TD 1; + cq_addr_reg <= `TD cq_num; + end +end + +assign arm_cq_we = is_arm_cq | cq_update_reg; +assign arm_cq_addr = is_arm_cq ? pio_uar_req_data[CQ_NUM_LOG-1:0] : + cq_update_reg ? cq_addr_reg : 0; +assign arm_cq_din = is_arm_cq; + +pcieifc_sd_sram #( + .DATAWIDTH ( 1 ), // Memory data word width + .ADDRWIDTH ( CQ_NUM_LOG ) // 8192 entries +) armed_cq_table ( + .clk ( clk ), // i, 1 + .rst_n ( rst_n ), // i, 1 + + .wea ( arm_cq_we ), // i, 1 + .addra ( arm_cq_addr ), // i, ADDRWIDTH + .dina ( arm_cq_din ), // i, DATAWIDTH + + .reb ( 1'd1 ), // i, 1 + .addrb ( cq_ren ? cq_num[CQ_NUM_LOG-1:0] : {CQ_NUM_LOG{1'd0}} ), // i, ADDRWIDTH + .doutb ( cq_dout ) // o, DATAWIDTH + +`ifdef PCIEI_APB_DBG + ,.rtsel ( cq_rtsel ) // i, 2 + ,.wtsel ( cq_wtsel ) // i, 2 + ,.ptsel ( cq_ptsel ) // i, 2 + ,.vg ( cq_vg ) // i, 1 + ,.vs ( cq_vs ) // i, 1 +`endif +); + +always @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + cq_dout_reg <= `TD 0; + end + else begin + cq_dout_reg <= `TD cq_dout; + end +end +/* -------ARM CQ Logic{begin}------- */ + + +/* -------ARM EQ Logic{begin}------- */ +always @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + eq_update_reg <= `TD 0; + eq_addr_reg <= `TD 0; + end + else if (eq_update_reg & (!is_arm_eq | !eq_dout)) begin // 1. clear when armed eq is not written + // 2. clear when eq is not armed + eq_update_reg <= `TD 0; + eq_addr_reg <= `TD 0; + end + else if (eq_ren) begin + eq_update_reg <= `TD 1; + eq_addr_reg <= `TD eq_num; + end +end + +assign arm_eq_we = is_arm_eq | eq_update_reg; +assign arm_eq_addr = is_arm_eq ? pio_uar_req_data[EQ_NUM_LOG-1:0] : + eq_update_reg ? eq_addr_reg : 0; +assign arm_eq_din = is_arm_eq; + +pcieifc_sd_sram #( + .DATAWIDTH ( 1 ), // Memory data word width + .ADDRWIDTH ( EQ_NUM_LOG ) // 32 entries +) armed_eq_table ( + .clk ( clk ), // i, 1 + .rst_n ( rst_n ), // i, 1 + + .wea ( arm_eq_we ), // i, 1 + .addra ( arm_eq_addr ), // i, ADDRWIDTH + .dina ( arm_eq_din ), // i, DATAWIDTH + + .reb ( 1'd1 ), // i, 1 + .addrb ( eq_ren ? eq_num[EQ_NUM_LOG-1:0] : {EQ_NUM_LOG{1'd0}} ), // i, ADDRWIDTH + .doutb ( eq_dout ) // o, DATAWIDTH + +`ifdef PCIEI_APB_DBG + ,.rtsel ( 2'b0 ) // i, 2 + ,.wtsel ( 2'b0 ) // i, 2 + ,.ptsel ( 2'b0 ) // i, 2 + ,.vg ( 1'b0 ) // i, 1 + ,.vs ( 1'b0 ) // i, 1 +`endif +); + +always @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + eq_dout_reg <= `TD 0; + end + else begin + eq_dout_reg <= `TD eq_dout; + end +end +/* -------ARM EQ Logic{begin}------- */ +endmodule diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/macro_reset_sync2.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/macro_reset_sync2.v new file mode 100644 index 0000000000000000000000000000000000000000..cff2595aa4e3976da0f251728da6be20bcfdd98b --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/PCIeInterface/macro_reset_sync2.v @@ -0,0 +1,21 @@ +module macro_reset_sync2( + input test_en, + input reset_n, + input ck, + output reset_sync_n +); + +reg d1, d2; + +always @(posedge ck or negedge reset_n) begin + if(~reset_n) begin + {d2, d1} <= 2'b0; + end + else begin + {d2, d1} <= {d1, 1'b1}; + end +end + +assign reset_sync_n = test_en ? reset_n : d2; + +endmodule diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Peripherals/DMARdChannel.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Peripherals/DMARdChannel.v new file mode 100644 index 0000000000000000000000000000000000000000..106693afb42281d0297fc84d58e44d09f5f812bc --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Peripherals/DMARdChannel.v @@ -0,0 +1,151 @@ +module DMARdRspChannel ( //512 to 256 + input wire clk, + input wire rst, + + input wire dma_rd_rsp_in_valid, + input wire [127:0] dma_rd_rsp_in_head, + input wire [255:0] dma_rd_rsp_in_data, + input wire dma_rd_rsp_in_last, + output wire dma_rd_rsp_in_ready, + + output wire dma_rd_rsp_out_valid, + output wire [127:0] dma_rd_rsp_out_head, + output wire [511:0] dma_rd_rsp_out_data, + output wire dma_rd_rsp_out_last, + input wire dma_rd_rsp_out_ready +); + +wire st_dma_rd_rsp_in_valid; +wire [127:0] st_dma_rd_rsp_in_head; +wire [511:0] st_dma_rd_rsp_in_data; +wire st_dma_rd_rsp_in_last; +wire st_dma_rd_rsp_in_ready; + +stream_reg #( + .TUSER_WIDTH ( 128 ), + .TDATA_WIDTH ( 256 ) +) +rd_chanl_st +( + .clk ( clk ), + .rst_n ( !rst ), + + .axis_tvalid ( dma_rd_rsp_in_valid ), + .axis_tlast ( dma_rd_rsp_in_last ), + .axis_tuser ( dma_rd_rsp_in_head ), + .axis_tdata ( dma_rd_rsp_in_data ), + .axis_tready ( dma_rd_rsp_in_ready ), + .axis_tstart ( 'd0 ), + .axis_tkeep ( 'd0 ), + + .in_reg_tvalid ( st_dma_rd_rsp_in_valid ), + .in_reg_tlast ( st_dma_rd_rsp_in_last ), + .in_reg_tuser ( st_dma_rd_rsp_in_head ), + .in_reg_tdata ( st_dma_rd_rsp_in_data ), + .in_reg_tready ( st_dma_rd_rsp_in_ready ), + .in_reg_tkeep ( ), + .in_reg_tstart ( ), + + + .tuser_clear ( ) +); + + +reg [255:0] data_piece; +reg [31:0] length_left; + +reg [1:0] cur_state; +reg [1:0] next_state; + +parameter [1:0] IDLE_s = 2'd1, + LOW_s = 2'd2, + HIGH_s = 2'd3; + +always @(posedge clk or posedge rst) begin + if (rst) begin + cur_state <= IDLE_s; + end + else begin + cur_state <= next_state; + end +end + +always @(*) begin + case(cur_state) + IDLE_s: if(st_dma_rd_rsp_in_valid) begin + next_state = LOW_s; + end + else begin + next_state = IDLE_s; + end + LOW_s: if(length_left <= 32 && st_dma_rd_rsp_in_valid && dma_rd_rsp_out_ready) begin + next_state = IDLE_s; + end + else if(length_left > 32 && st_dma_rd_rsp_in_valid) begin + next_state = HIGH_s; + end + else begin + next_state = LOW_s; + end + HIGH_s: if(length_left <= 32 && st_dma_rd_rsp_in_valid && dma_rd_rsp_out_ready) begin + next_state = IDLE_s; + end + else if(length_left > 32 && st_dma_rd_rsp_in_valid && dma_rd_rsp_out_ready) begin + next_state = LOW_s; + end + else begin + next_state = HIGH_s; + end + default: next_state = IDLE_s; + endcase +end + +always @(posedge clk or posedge rst) begin + if (rst) begin + length_left <= 'd0; + end + else if (cur_state == IDLE_s && st_dma_rd_rsp_in_valid) begin + length_left <= st_dma_rd_rsp_in_head[31:0]; + end + else if(cur_state == LOW_s && length_left <= 32 && st_dma_rd_rsp_in_valid && dma_rd_rsp_out_ready) begin + length_left <= 'd0; + end + else if(cur_state == LOW_s && length_left > 32 && st_dma_rd_rsp_in_valid) begin + length_left <= length_left - 32; + end + else if(cur_state == HIGH_s && length_left <= 32 && st_dma_rd_rsp_in_valid && dma_rd_rsp_out_ready) begin + length_left <= 'd0; + end + else if(cur_state == HIGH_s && length_left > 32 && st_dma_rd_rsp_in_valid && dma_rd_rsp_out_ready) begin + length_left <= length_left - 32; + end + else begin + length_left <= length_left; + end +end + +always @(posedge clk or posedge rst) begin + if (rst) begin + data_piece <= 'd0; + end + else if (cur_state == LOW_s && length_left > 32 && st_dma_rd_rsp_in_valid) begin + data_piece <= st_dma_rd_rsp_in_data; + end + else begin + data_piece <= data_piece; + end +end + +assign st_dma_rd_rsp_in_ready = (cur_state == LOW_s && length_left <= 32) ? dma_rd_rsp_out_ready : + (cur_state == LOW_s && length_left > 32) ? 'd1 : + (cur_state == HIGH_s) ? dma_rd_rsp_out_ready : 'd0; + +assign dma_rd_rsp_out_valid = (cur_state == LOW_s && length_left <= 32 && st_dma_rd_rsp_in_valid) ? 'd1 : + (cur_state == HIGH_s && st_dma_rd_rsp_in_valid) ? 'd1 : 'd0; +assign dma_rd_rsp_out_head = (cur_state == LOW_s || cur_state == HIGH_s) ? st_dma_rd_rsp_in_head : 'd0; +assign dma_rd_rsp_out_data = (cur_state == LOW_s && length_left <= 32 && st_dma_rd_rsp_in_valid) ? {256'd0, st_dma_rd_rsp_in_data} : + (cur_state == HIGH_s && st_dma_rd_rsp_in_valid) ? {st_dma_rd_rsp_in_data, data_piece} : 'd0; +assign dma_rd_rsp_out_last = (cur_state == LOW_s && length_left <= 32 && st_dma_rd_rsp_in_valid) ? 'd1 : + (cur_state == HIGH_s && length_left <= 32 && st_dma_rd_rsp_in_valid) ? 'd1 : 'd0; + +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Peripherals/DMAWrChannel.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Peripherals/DMAWrChannel.v new file mode 100644 index 0000000000000000000000000000000000000000..dbab5e1964a915e1d3b32c4c715bfcc90f94c03c --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Peripherals/DMAWrChannel.v @@ -0,0 +1,104 @@ +module DMAWrReqChannel ( //512 to 256 + input wire clk, + input wire rst, + + input wire dma_wr_req_in_valid, + input wire [127:0] dma_wr_req_in_head, + input wire [511:0] dma_wr_req_in_data, + input wire dma_wr_req_in_last, + output wire dma_wr_req_in_ready, + + output wire dma_wr_req_out_valid, + output wire [127:0] dma_wr_req_out_head, + output wire [255:0] dma_wr_req_out_data, + output wire dma_wr_req_out_last, + input wire dma_wr_req_out_ready +); + +reg [31:0] length_left; + +reg [1:0] cur_state; +reg [1:0] next_state; + +parameter [1:0] IDLE_s = 2'd1, + LOW_s = 2'd2, + HIGH_s = 2'd3; + +always @(posedge clk or posedge rst) begin + if (rst) begin + cur_state <= IDLE_s; + end + else begin + cur_state <= next_state; + end +end + +always @(*) begin + case(cur_state) + IDLE_s: if(dma_wr_req_in_valid) begin + next_state = LOW_s; + end + else begin + next_state = IDLE_s; + end + LOW_s: if(length_left <= 32 && dma_wr_req_in_valid && dma_wr_req_out_ready) begin + next_state = IDLE_s; + end + else if(length_left > 32 && dma_wr_req_in_valid && dma_wr_req_out_ready) begin + next_state = HIGH_s; + end + else begin + next_state = LOW_s; + end + HIGH_s: if(length_left <= 32 && dma_wr_req_in_valid && dma_wr_req_out_ready) begin + next_state = IDLE_s; + end + else if(length_left > 32 && dma_wr_req_in_valid && dma_wr_req_out_ready) begin + next_state = LOW_s; + end + else begin + next_state = HIGH_s; + end + default: next_state = IDLE_s; + endcase +end + +always @(posedge clk or posedge rst) begin + if (rst) begin + length_left <= 'd0; + end + else if (cur_state == IDLE_s && dma_wr_req_in_valid) begin + length_left <= dma_wr_req_in_head[31:0]; + end + else if(cur_state == LOW_s && dma_wr_req_in_valid && dma_wr_req_out_ready) begin + if(length_left <= 32) begin + length_left <= 'd0; + end + else begin + length_left <= length_left - 32; + end + end + else if(cur_state == HIGH_s && dma_wr_req_in_valid && dma_wr_req_out_ready) begin + if(length_left <= 32) begin + length_left <= 'd0; + end + else begin + length_left <= length_left - 32; + end + end + else begin + length_left <= length_left; + end +end + +assign dma_wr_req_in_ready = (cur_state == LOW_s && length_left <= 32) ? dma_wr_req_out_ready : + (cur_state == HIGH_s) ? dma_wr_req_out_ready : 'd0; + +assign dma_wr_req_out_valid = (cur_state == LOW_s || cur_state == HIGH_s) ? dma_wr_req_in_valid : 'd0; +assign dma_wr_req_out_head = (cur_state == LOW_s || cur_state == HIGH_s) ? dma_wr_req_in_head : 'd0; +assign dma_wr_req_out_data = (cur_state == LOW_s) ? dma_wr_req_in_data[255:0] : + (cur_state == HIGH_s) ? dma_wr_req_in_data[511:256] : 'd0; +assign dma_wr_req_out_last = (cur_state == LOW_s && length_left <= 32 && dma_wr_req_in_valid) ? 'd1 : + (cur_state == HIGH_s && length_left <= 32 && dma_wr_req_in_valid) ? 'd1 : 'd0; + +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Peripherals/DynamicBuffer.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Peripherals/DynamicBuffer.v new file mode 100644 index 0000000000000000000000000000000000000000..6fdb2235d942e2cd9651404da05ac50061cedd35 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Peripherals/DynamicBuffer.v @@ -0,0 +1,641 @@ +/*------------------------------------------- Module Description : Begin ---------------------------------------------- +Name: DynamicBuffer +Author: YangFan +Function: Store packet in a fine-grained granularity. + Each packet is splitted into SLOT_WIDTH-sized flit, and each slot is allocated and recycled dynamically. +--------------------------------------------- Module Decription : End -----------------------------------------------*/ + + +/*------------------------------------------- Timescale Definition : Begin ------------------------------------------*/ +`timescale 1ns / 1ps +/*------------------------------------------- Timescale Definition : End --------------------------------------------*/ + +/*------------------------------------------- Included Files : Begin ------------------------------------------------*/ +`include "protocol_engine_def.vh" +/*------------------------------------------- Included Files : End --------------------------------------------------*/ + +/*------------------------------------------- Input/Output Definition : Begin ---------------------------------------*/ +module DynamicBuffer #( + //Queue Buffer is comprised of numbers of slots, slot is the basic unit that DB operates on. Default SLOT_WIDTH is aligned with Data Bus Width. + parameter SLOT_WIDTH = 512, + parameter SLOT_NUM = 512, + parameter SLOT_NUM_LOG = log2b(SLOT_NUM - 1), + + parameter NULL_PTR = {(SLOT_NUM_LOG){1'b0}} +)( + input wire clk, + input wire rst, + +//Queue state interface, indicates how many slots are available. Users should ensure that there are enough slots for the items to be stored. + output wire [`MAX_DB_SLOT_NUM_LOG : 0] ov_available_slot_num, + +//Insert Interface +//Head format: +//{slot number} + input wire i_insert_req_valid, + input wire i_insert_req_start, + input wire i_insert_req_last, + input wire [`MAX_DB_SLOT_NUM_LOG - 1 : 0] iv_insert_req_head, + input wire [SLOT_WIDTH - 1 : 0] iv_insert_req_data, + output wire o_insert_req_ready, +//Return the address of each element + output wire o_insert_resp_valid, + output wire [`MAX_DB_SLOT_NUM_LOG - 1 : 0] ov_insert_resp_data, //Address of data inserted. + +//Get Interface +//Head format: +//{slot number + addr} + input wire i_get_req_valid, + input wire [`MAX_DB_SLOT_NUM_LOG * 2 - 1 : 0] iv_get_req_head, + output wire o_get_req_ready, + output wire o_get_resp_valid, + output wire o_get_resp_start, + output wire o_get_resp_last, + output wire [SLOT_WIDTH - 1 : 0] ov_get_resp_data, + input wire i_get_resp_ready, + +//Delete Interface +//Head format: +//{slot number + addr} + input wire i_delete_req_valid, + input wire [`MAX_DB_SLOT_NUM_LOG * 2 - 1 : 0] iv_delete_req_head, + output wire o_delete_req_ready, + + output wire o_delete_resp_valid, + output wire o_delete_resp_start, + output wire o_delete_resp_last, + output wire [SLOT_WIDTH - 1 : 0] ov_delete_resp_data, + input wire i_delete_resp_ready + +); +/*------------------------------------------- Input/Output Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Variables Definition : Begin ------------------------------------*/ +reg [31:0] qv_get_count; +reg [31:0] qv_get_total; +reg [31:0] qv_delete_count; +reg [31:0] qv_delete_total; + +reg first_delete; + +reg content_table_wea; +reg [SLOT_NUM_LOG - 1 : 0] content_table_addra; +reg [SLOT_WIDTH - 1 : 0] content_table_dina; +wire [SLOT_WIDTH - 1 : 0] content_table_douta; +reg content_table_web; +reg [SLOT_NUM_LOG - 1 : 0] content_table_addrb; +reg [SLOT_NUM_LOG - 1 : 0] content_table_addrb_diff; +reg [SLOT_WIDTH - 1 : 0] content_table_dinb; +wire [SLOT_WIDTH - 1 : 0] content_table_doutb; + +reg [SLOT_NUM_LOG - 1 : 0] qv_content_table_addrb_prev; +reg [SLOT_NUM_LOG - 1 : 0] qv_content_table_addra_prev; + +reg next_table_wea; +reg [SLOT_NUM_LOG - 1 : 0] next_table_addra; +reg [SLOT_NUM_LOG - 1 : 0] next_table_dina; +wire [SLOT_NUM_LOG - 1 : 0] next_table_douta; +reg next_table_web; +reg [SLOT_NUM_LOG - 1 : 0] next_table_addrb; +reg [SLOT_NUM_LOG - 1 : 0] next_table_addrb_diff; +reg [SLOT_NUM_LOG - 1 : 0] next_table_dinb; +wire [SLOT_NUM_LOG - 1 : 0] next_table_doutb; + +reg free_wr_en; +reg [SLOT_NUM_LOG - 1 : 0] free_din; +wire free_prog_full; +reg free_rd_en; +wire [SLOT_NUM_LOG - 1 : 0] free_dout; +wire free_empty; +wire [SLOT_NUM_LOG : 0] free_data_count; + +reg [SLOT_NUM_LOG : 0] init_counter; +wire init_finish; + +reg q_first_flit; + +reg [SLOT_NUM_LOG - 1 : 0] qv_last_insert_addr; + +/*------------------------------------------- Local Variables Definition : End --------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : Begin ---------------------------------------*/ +SRAM_TDP_Template +#( + .RAM_WIDTH ( SLOT_WIDTH ), + .RAM_DEPTH ( SLOT_NUM ) +) +DB_ContentTable( + .clk ( clk ), + .rst ( rst ), + + .wea ( content_table_wea ), + .addra ( content_table_addra ), + .dina ( content_table_dina ), + .douta ( content_table_douta ), + + .web ( content_table_web ), + .addrb ( content_table_addrb ), + .dinb ( content_table_dinb ), + .doutb ( content_table_doutb ) +); + +//Next Table +SRAM_TDP_Template +#( + .RAM_WIDTH ( SLOT_NUM_LOG ), + .RAM_DEPTH ( SLOT_NUM ) +) +DB_NextTable( + .clk ( clk ), + .rst ( rst ), + + .wea ( next_table_wea ), + .addra ( next_table_addra ), + .dina ( next_table_dina ), + .douta ( next_table_douta ), + + .web ( next_table_web ), + .addrb ( next_table_addrb ), + .dinb ( next_table_dinb ), + .doutb ( next_table_doutb ) +); + +//FreeList +SyncFIFO_Template +#( + .FIFO_WIDTH ( SLOT_NUM_LOG ), + .FIFO_DEPTH ( SLOT_NUM ) +) +FreeListFIFO +( + .clk ( clk ), + .rst ( rst ), + + .wr_en ( free_wr_en ), + .din ( free_din ), + .prog_full ( free_prog_full ), + .rd_en ( free_rd_en ), + .dout ( free_dout ), + .empty ( free_empty ), + .data_count ( free_data_count ) +); +/*------------------------------------------- Submodules Instatiation : End -----------------------------------------*/ + +/*------------------------------------------- State Machine Definition : Begin --------------------------------------*/ +//Producer state machine +reg [1:0] producer_cur_state; +reg [1:0] producer_next_state; + +parameter [1:0] PRODUCER_INIT_s = 'd0, + PRODUCER_IDLE_s = 'd1, + PRODUCER_INSERT_s = 'd2; + +always @(posedge clk or posedge rst) begin + if(rst) begin + producer_cur_state <= PRODUCER_INIT_s; + end + else begin + producer_cur_state <= producer_next_state; + end +end + +always @(*) begin + case(producer_cur_state) + PRODUCER_INIT_s: if(init_finish) begin + producer_next_state = PRODUCER_IDLE_s; + end + else begin + producer_next_state = PRODUCER_INIT_s; + end + PRODUCER_IDLE_s: if(i_insert_req_valid) begin + producer_next_state = PRODUCER_INSERT_s; + end + else begin + producer_next_state = PRODUCER_IDLE_s; + end + PRODUCER_INSERT_s: if(i_insert_req_valid && i_insert_req_last && o_insert_req_ready) begin + producer_next_state = PRODUCER_IDLE_s; + end + else begin + producer_next_state = PRODUCER_INSERT_s; + end + default: producer_next_state = PRODUCER_IDLE_s; + endcase +end + +//Consumer state machine +reg [2:0] consumer_cur_state; +reg [2:0] consumer_next_state; + +parameter [2:0] CONSUMER_IDLE_s = 3'd1, + CONSUMER_GET_s = 3'd2, + CONSUMER_NULL_s = 3'd3, + CONSUMER_DELETE_s = 3'd4; + +always @(posedge clk or posedge rst) begin + if(rst) begin + consumer_cur_state <= CONSUMER_IDLE_s; + end + else begin + consumer_cur_state <= consumer_next_state; + end +end + +always @(*) begin + case(consumer_cur_state) + CONSUMER_IDLE_s: if(i_get_req_valid) begin + consumer_next_state = CONSUMER_GET_s; + end + else if(i_delete_req_valid) begin + if(iv_delete_req_head == 0) begin + consumer_next_state = CONSUMER_NULL_s; + end + else begin + consumer_next_state = CONSUMER_DELETE_s; + end + end + else begin + consumer_next_state = CONSUMER_IDLE_s; + end + CONSUMER_GET_s: if(qv_get_count == 1 && i_get_resp_ready) begin + consumer_next_state = CONSUMER_IDLE_s; + end + else begin + consumer_next_state = CONSUMER_GET_s; + end + CONSUMER_NULL_s: consumer_next_state = CONSUMER_IDLE_s; + CONSUMER_DELETE_s: if(qv_delete_count == 1 && i_delete_resp_ready) begin + consumer_next_state = CONSUMER_IDLE_s; + end + else begin + consumer_next_state = CONSUMER_DELETE_s; + end + default: consumer_next_state = CONSUMER_IDLE_s; + endcase +end + +/*------------------------------------------- State Machine Definition : End ----------------------------------------*/ + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ +//-- init_finish -- +assign init_finish = (init_counter == SLOT_NUM); + +//-- init_counter -- +always @(posedge clk or posedge rst) begin + if(rst) begin + init_counter <= 'd0; + end + else if(init_counter < SLOT_NUM) begin + init_counter <= init_counter + 'd1; + end + else begin + init_counter <= init_counter; + end +end + +//-- q_first_flit -- +always @(posedge clk or posedge rst) begin + if(rst) begin + q_first_flit <= 'd0; + end + else if(producer_cur_state == PRODUCER_IDLE_s && i_insert_req_valid) begin + q_first_flit <= 'd1; + end + else if(producer_cur_state == PRODUCER_INSERT_s && q_first_flit) begin + q_first_flit <= 'd0; + end + else begin + q_first_flit <= q_first_flit; + end +end + +//-- qv_last_insert_addr -- +always @(posedge clk or posedge rst) begin + if(rst) begin + qv_last_insert_addr <= 'd0; + end + else if(producer_cur_state == PRODUCER_INSERT_s && i_insert_req_valid && o_insert_req_ready) begin + qv_last_insert_addr <= free_dout; + end + else begin + qv_last_insert_addr <= qv_last_insert_addr; + end +end + +//-- qv_get_count -- +always @(posedge clk or posedge rst) begin + if(rst) begin + qv_get_count <= 'd0; + end + else if(consumer_cur_state == CONSUMER_IDLE_s) begin + qv_get_count <= i_get_req_valid ? iv_get_req_head[`MAX_DB_SLOT_NUM_LOG * 2 - 1 : `MAX_DB_SLOT_NUM_LOG] : 'd0; + end + else if(consumer_cur_state == CONSUMER_GET_s && i_get_resp_ready) begin + qv_get_count <= qv_get_count - 'd1; + end + else begin + qv_get_count <= qv_get_count; + end +end + +//-- qv_get_total -- +always @(posedge clk or posedge rst) begin + if(rst) begin + qv_get_total <= 'd0; + end + else if(consumer_cur_state == CONSUMER_IDLE_s) begin + qv_get_total <= i_get_req_valid ? iv_get_req_head[`MAX_DB_SLOT_NUM_LOG * 2 - 1 : `MAX_DB_SLOT_NUM_LOG] : 'd0; + end + else begin + qv_get_total <= qv_get_total; + end +end + +//-- qv_delete_count -- +always @(posedge clk or posedge rst) begin + if(rst) begin + qv_delete_count <= 'd0; + end + else if(consumer_cur_state == CONSUMER_IDLE_s) begin + qv_delete_count <= i_delete_req_valid ? iv_delete_req_head[`MAX_DB_SLOT_NUM_LOG * 2 - 1 : `MAX_DB_SLOT_NUM_LOG] : 'd0; + end + else if(consumer_cur_state == CONSUMER_DELETE_s && i_delete_resp_ready) begin + qv_delete_count <= qv_delete_count - 'd1; + end + else begin + qv_delete_count <= qv_delete_count; + end +end + +//-- qv_delete_total -- +always @(posedge clk or posedge rst) begin + if(rst) begin + qv_delete_total <= 'd0; + end + else if(consumer_cur_state == CONSUMER_IDLE_s) begin + qv_delete_total <= i_delete_req_valid ? iv_delete_req_head[`MAX_DB_SLOT_NUM_LOG * 2 - 1 : `MAX_DB_SLOT_NUM_LOG] : 'd0; + end + else begin + qv_delete_total <= qv_delete_total; + end +end + +//-- free_wr_en -- +//-- free_din -- +always @(*) begin + if(rst) begin + free_wr_en = 'd0; + free_din = 'd0; + end + else if(!init_finish && init_counter != 0) begin //Address 0 is unused + free_wr_en = 'd1; + free_din = init_counter; + end + else if(consumer_cur_state == CONSUMER_DELETE_s && o_delete_resp_valid && i_delete_resp_ready) begin + free_wr_en = 'd1; + free_din = qv_content_table_addrb_prev; + end + else begin + free_wr_en = 'd0; + free_din = 'd0; + end +end + +//-- free_rd_en -- +always @(*) begin + if(rst) begin + free_rd_en = 'd0; + end + else if(producer_cur_state == PRODUCER_INSERT_s && i_insert_req_valid && o_insert_req_ready) begin + free_rd_en = 'd1; + end + else begin + free_rd_en = 'd0; + end +end + +//-- content_table_wea -- +//-- content_table_addra -- +//-- content_table_dina -- +always @(*) begin + if(rst) begin + content_table_wea = 'd0; + content_table_addra = 'd0; + content_table_dina = 'd0; + end + else if(producer_cur_state == PRODUCER_INSERT_s && i_insert_req_valid && o_insert_req_ready) begin + content_table_wea = 'd1; + content_table_addra = free_dout; + content_table_dina = iv_insert_req_data; + end + else begin + content_table_wea = 'd0; + content_table_addra = 'd0; + content_table_dina = 'd0; + end +end + +//-- content_table_web -- +//-- content_table_addrb -- +//-- content_table_dinb -- +always @(*) begin + if(rst) begin + content_table_web = 'd0; + content_table_addrb = 'd0; + content_table_dinb = 'd0; + end + else if((consumer_cur_state == CONSUMER_IDLE_s) && i_get_req_valid) begin + content_table_web = 'd0; + content_table_addrb = iv_get_req_head[SLOT_NUM_LOG - 1 : 0]; + content_table_dinb = 'd0; + end + else if((consumer_cur_state == CONSUMER_IDLE_s) && i_delete_req_valid) begin + content_table_web = 'd0; + content_table_addrb = iv_delete_req_head[SLOT_NUM_LOG - 1 : 0]; + content_table_dinb = 'd0; + end + else if((consumer_cur_state == CONSUMER_GET_s && i_get_resp_ready) || (consumer_cur_state == CONSUMER_DELETE_s && i_delete_resp_ready)) begin + content_table_web = 'd0; + content_table_addrb = next_table_doutb; + content_table_dinb = 'd0; + end + else begin + content_table_web = 'd0; + content_table_addrb = content_table_addrb_diff; + content_table_dinb = 'd0; + end +end + +//-- content_table_addrb_diff -- +always @(posedge clk or posedge rst) begin + if(rst) begin + content_table_addrb_diff <= 'd0; + end + else begin + content_table_addrb_diff <= content_table_addrb; + end +end + +//-- next_table_wea -- +//-- next_table_addra -- +//-- next_table_dina -- +always @(*) begin + if(rst) begin + next_table_wea = 'd0; + next_table_addra = 'd0; + next_table_dina = 'd0; + end + else if(producer_cur_state == PRODUCER_IDLE_s) begin + next_table_wea = 'd0; + next_table_addra = 'd0; + next_table_dina = 'd0; + end + else if(producer_cur_state == PRODUCER_INSERT_s && i_insert_req_valid && o_insert_req_ready) begin + if(q_first_flit) begin //First-time insert, no need to modify next and prev + next_table_wea = 'd0; + next_table_addra = 'd0; + next_table_dina = 'd0; + end + else begin + next_table_wea = 'd1; + next_table_addra = qv_last_insert_addr; + next_table_dina = free_dout; + end + end + else begin + next_table_wea = 'd0; + next_table_addra = 'd0; + next_table_dina = 'd0; + end +end + +//-- next_table_web -- +//-- next_table_addrb -- +//-- next_table_dinb -- +always @(*) begin + if(rst) begin + next_table_web = 'd0; + next_table_addrb = 'd0; + next_table_dinb = 'd0; + end + else if(consumer_cur_state == CONSUMER_IDLE_s && i_delete_req_valid) begin + next_table_web = 'd0; + next_table_addrb = iv_delete_req_head[SLOT_NUM_LOG - 1 : 0]; + next_table_dinb = 'd0; + end + else if(consumer_cur_state == CONSUMER_IDLE_s && i_get_req_valid) begin + next_table_web = 'd0; + next_table_addrb = iv_get_req_head[SLOT_NUM_LOG - 1 : 0]; + next_table_dinb = 'd0; + end + else if((consumer_cur_state == CONSUMER_GET_s && i_get_resp_ready) || (consumer_cur_state == CONSUMER_DELETE_s && i_delete_resp_ready))begin + next_table_web = 'd0; + next_table_addrb = next_table_doutb; + next_table_dinb = 'd0; + end + else begin + next_table_web = 'd0; + next_table_addrb = next_table_addrb_diff; + next_table_dinb = 'd0; + end +end + +//-- next_table_addrb_diff -- +always @(posedge clk or posedge rst) begin + if(rst) begin + next_table_addrb_diff <= 'd0; + end + else begin + next_table_addrb_diff <= next_table_addrb; + end +end + +//-- first_delete -- +always @(posedge clk or posedge rst) begin + if(rst) begin + first_delete <= 'd0; + end + else if(consumer_cur_state == CONSUMER_IDLE_s && i_delete_req_valid) begin + first_delete <= 'd1; + end + else if(consumer_cur_state == CONSUMER_DELETE_s && o_delete_resp_valid && i_delete_resp_ready) begin + first_delete <= 'd0; + end + else begin + first_delete <= first_delete; + end +end + +//-- qv_content_table_addra_prev -- +always @(posedge clk or posedge rst) begin + if(rst) begin + qv_content_table_addra_prev <= 'd0; + end + else if(content_table_wea) begin + qv_content_table_addra_prev <= content_table_addra; + end + else begin + qv_content_table_addra_prev <= qv_content_table_addra_prev; + end +end + +//-- qv_content_table_addrb_prev -- +always @(posedge clk or posedge rst) begin + if(rst) begin + qv_content_table_addrb_prev <= 'd0; + end + else if((consumer_cur_state == CONSUMER_IDLE_s) && i_delete_req_valid) begin + qv_content_table_addrb_prev <= iv_delete_req_head[SLOT_NUM_LOG - 1 : 0]; + end + else if(o_delete_resp_valid && i_delete_resp_ready) begin + qv_content_table_addrb_prev <= content_table_addrb; + end + else begin + qv_content_table_addrb_prev <= qv_content_table_addrb_prev; + end +end + +//-- ov_available_slot_num +assign ov_available_slot_num = free_data_count; + +//-- o_insert_req_ready -- +assign o_insert_req_ready = (producer_cur_state == PRODUCER_INSERT_s); + +//-- o_insert_resp_valid -- +assign o_insert_resp_valid = (producer_cur_state == PRODUCER_INSERT_s && i_insert_req_valid); + +//-- ov_insert_resp_data -- +assign ov_insert_resp_data = (producer_cur_state == PRODUCER_INSERT_s && o_insert_resp_valid) ? content_table_addra : 'd0; + +//-- o_get_req_ready -- +assign o_get_req_ready = (consumer_cur_state == CONSUMER_IDLE_s); + +//-- o_get_resp_valid -- +assign o_get_resp_valid = (consumer_cur_state == CONSUMER_GET_s); + +//-- o_get_resp_start -- +assign o_get_resp_start = (consumer_cur_state == CONSUMER_GET_s) && (qv_get_total == qv_get_count); + +//-- o_get_resp_last -- +assign o_get_resp_last = (consumer_cur_state == CONSUMER_GET_s) && (qv_get_count == 'd1); + +//-- ov_get_resp_data -- +assign ov_get_resp_data = (consumer_cur_state == CONSUMER_GET_s) ? content_table_doutb : 'd0; + +//-- o_delete_req_ready -- +assign o_delete_req_ready = (consumer_cur_state == CONSUMER_IDLE_s); + +//-- o_delete_resp_valid -- +assign o_delete_resp_valid = (consumer_cur_state == CONSUMER_DELETE_s) || (consumer_cur_state == CONSUMER_NULL_s); + +//-- o_delete_resp_start -- +assign o_delete_resp_start = ((consumer_cur_state == CONSUMER_DELETE_s) && (qv_delete_total == qv_delete_count)) || (consumer_cur_state == CONSUMER_NULL_s); + +//-- o_delete_resp_last -- +assign o_delete_resp_last = ((consumer_cur_state == CONSUMER_DELETE_s) && (qv_delete_count == 'd1)) || (consumer_cur_state == CONSUMER_NULL_s); + +//-- ov_delete_resp_data -- +assign ov_delete_resp_data = (consumer_cur_state == CONSUMER_DELETE_s) ? content_table_doutb : 'd0; + +/*------------------------------------------- Variables Decode : End ------------------------------------------------*/ +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Peripherals/DynamicBufferDeleteArbiter.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Peripherals/DynamicBufferDeleteArbiter.v new file mode 100644 index 0000000000000000000000000000000000000000..252a62f0636d475b2be2b6432c186ede0b3c00ea --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Peripherals/DynamicBufferDeleteArbiter.v @@ -0,0 +1,174 @@ +/*------------------------------------------- Module Description : Begin ---------------------------------------------- +Name: DynamicBufferDeleteArbiter +Author: YangFan +Function: 1.Arbitrate delete Request. +--------------------------------------------- Module Decription : End -----------------------------------------------*/ + +/*------------------------------------------- Timescale Definition : Begin ------------------------------------------*/ +`timescale 1ns / 1ps +/*------------------------------------------- Timescale Definition : End --------------------------------------------*/ + +/*------------------------------------------- Included Files : Begin ------------------------------------------------*/ +`include "protocol_engine_def.vh" +/*------------------------------------------- Included Files : End --------------------------------------------------*/ + +/*------------------------------------------- Input/Output Definition : Begin ---------------------------------------*/ +module DynamicBufferDeleteArbiter +( + input wire clk, + input wire rst, + + input wire chnl_0_req_valid, + input wire [`MAX_DB_SLOT_NUM_LOG * 2 - 1 : 0] chnl_0_req_head, + output wire chnl_0_req_ready, + + output wire chnl_0_resp_valid, + output wire chnl_0_resp_start, + output wire chnl_0_resp_last, + output wire [`PACKET_BUFFER_SLOT_WIDTH - 1 : 0] chnl_0_resp_data, + input wire chnl_0_resp_ready, + + input wire chnl_1_req_valid, + input wire [`MAX_DB_SLOT_NUM_LOG * 2 - 1 : 0] chnl_1_req_head, + output wire chnl_1_req_ready, + + output wire chnl_1_resp_valid, + output wire chnl_1_resp_start, + output wire chnl_1_resp_last, + output wire [`PACKET_BUFFER_SLOT_WIDTH - 1 : 0] chnl_1_resp_data, + input wire chnl_1_resp_ready, + + output wire delete_req_valid, + output wire [`MAX_DB_SLOT_NUM_LOG * 2 - 1 : 0] delete_req_head, + input wire delete_req_ready, + + input wire delete_resp_valid, + input wire delete_resp_start, + input wire delete_resp_last, + input wire [`PACKET_BUFFER_SLOT_WIDTH - 1 : 0] delete_resp_data, + output wire delete_resp_ready +); + +/*------------------------------------------- Input/Output Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Macros Definition : Begin ---------------------------------------*/ +`define CHNL_0 0 +`define CHNL_1 1 +/*------------------------------------------- Local Macros Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Variables Definition : Begin ------------------------------------*/ +reg [0:0] last_sch_chnl; +/*------------------------------------------- Local Variables Definition : End --------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : Begin ---------------------------------------*/ +/*------------------------------------------- Submodules Instatiation : End -----------------------------------------*/ + +/*------------------------------------------- State Machine Definition : Begin --------------------------------------*/ +reg [1:0] cur_state; +reg [1:0] next_state; + +parameter [1:0] IDLE_s = 2'd1, + CHNL_0_s = 2'd2, + CHNL_1_s = 2'd3; + +always @(posedge clk or posedge rst) begin + if (rst) begin + cur_state <= IDLE_s; + end + else begin + cur_state <= next_state; + end +end + +always @(*) begin + case(cur_state) + IDLE_s: if(last_sch_chnl == `CHNL_0 && chnl_1_req_valid) begin + next_state = CHNL_1_s; + end + else if(last_sch_chnl == `CHNL_1 && chnl_0_req_valid) begin + next_state = CHNL_0_s; + end + else if(last_sch_chnl == `CHNL_1 && !chnl_0_req_valid && chnl_1_req_valid) begin + next_state = CHNL_1_s; + end + else if(last_sch_chnl == `CHNL_0 && !chnl_1_req_valid && chnl_0_req_valid) begin + next_state = CHNL_0_s; + end + else begin + next_state = IDLE_s; + end + CHNL_0_s: if(chnl_0_resp_last && chnl_0_resp_ready) begin + next_state = IDLE_s; + end + else begin + next_state = CHNL_0_s; + end + CHNL_1_s: if(chnl_1_resp_last && chnl_1_resp_ready) begin + next_state = IDLE_s; + end + else begin + next_state = CHNL_1_s; + end + default: next_state = IDLE_s; + endcase +end +/*------------------------------------------- State Machine Definition : End ----------------------------------------*/ + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ +//-- last_sch_chnl -- +always @(posedge clk or posedge rst) begin + if (rst) begin + last_sch_chnl <= `CHNL_0; + end + else if (cur_state == CHNL_0_s && chnl_0_resp_last && chnl_0_resp_ready) begin + last_sch_chnl <= `CHNL_0; + end + else if (cur_state == CHNL_1_s && chnl_1_resp_last && chnl_1_resp_ready) begin + last_sch_chnl <= `CHNL_1; + end + else begin + last_sch_chnl <= last_sch_chnl; + end +end + +//-- chnl_0_req_ready -- +assign chnl_0_req_ready = (cur_state == CHNL_0_s) ? delete_req_ready : 'd0; + +//-- chnl_1_req_ready -- +assign chnl_1_req_ready = (cur_state == CHNL_1_s) ? delete_req_ready : 'd0; + +//-- chnl_0_resp_valid -- +//-- chnl_0_resp_start -- +//-- chnl_0_resp_last -- +//-- chnl_0_resp_data -- +assign chnl_0_resp_valid = (cur_state == CHNL_0_s) ? delete_resp_valid : 'd0; +assign chnl_0_resp_start = (cur_state == CHNL_0_s) ? delete_resp_start : 'd0; +assign chnl_0_resp_last = (cur_state == CHNL_0_s) ? delete_resp_last : 'd0; +assign chnl_0_resp_data = (cur_state == CHNL_0_s) ? delete_resp_data : 'd0; + +//-- chnl_1_resp_valid -- +//-- chnl_1_resp_start -- +//-- chnl_1_resp_last -- +//-- chnl_1_resp_data -- +assign chnl_1_resp_valid = (cur_state == CHNL_1_s) ? delete_resp_valid : 'd0; +assign chnl_1_resp_start = (cur_state == CHNL_1_s) ? delete_resp_start : 'd0; +assign chnl_1_resp_last = (cur_state == CHNL_1_s) ? delete_resp_last : 'd0; +assign chnl_1_resp_data = (cur_state == CHNL_1_s) ? delete_resp_data : 'd0; + +//-- delete_req_valid -- +//-- delete_req_head -- +assign delete_req_valid = (cur_state == CHNL_0_s) ? chnl_0_req_valid : + (cur_state == CHNL_1_s) ? chnl_1_req_valid : 'd0; +assign delete_req_head = (cur_state == CHNL_0_s) ? chnl_0_req_head : + (cur_state == CHNL_1_s) ? chnl_1_req_head : 'd0; + +//-- delete_resp_ready -- +assign delete_resp_ready = (cur_state == CHNL_0_s) ? chnl_0_resp_ready : + (cur_state == CHNL_1_s) ? chnl_1_resp_ready : 'd0; +/*------------------------------------------- Variables Decode : End ----------------------------------------------*/ + +/*------------------------------------------- Local Macros Undef : Begin --------------------------------------------*/ + +/*------------------------------------------- Local Macros Undef : End ----------------------------------------------*/ + +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Peripherals/DynamicBufferInsertArbiter.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Peripherals/DynamicBufferInsertArbiter.v new file mode 100644 index 0000000000000000000000000000000000000000..9e2788191338122d8660f7d3bab68b493e0af1b7 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Peripherals/DynamicBufferInsertArbiter.v @@ -0,0 +1,171 @@ +/*------------------------------------------- Module Description : Begin ---------------------------------------------- +Name: DynamicBufferInsertArbiter +Author: YangFan +Function: 1.Arbitrate Insert Request. +--------------------------------------------- Module Decription : End -----------------------------------------------*/ + +/*------------------------------------------- Timescale Definition : Begin ------------------------------------------*/ +`timescale 1ns / 1ps +/*------------------------------------------- Timescale Definition : End --------------------------------------------*/ + +/*------------------------------------------- Included Files : Begin ------------------------------------------------*/ +`include "protocol_engine_def.vh" +/*------------------------------------------- Included Files : End --------------------------------------------------*/ + +/*------------------------------------------- Input/Output Definition : Begin ---------------------------------------*/ +module DynamicBufferInsertArbiter +( + input wire clk, + input wire rst, + + input wire chnl_0_req_valid, + input wire chnl_0_req_start, + input wire chnl_0_req_last, + input wire [`MAX_DB_SLOT_NUM_LOG - 1 : 0] chnl_0_req_head, + input wire [`PACKET_BUFFER_SLOT_WIDTH - 1 : 0] chnl_0_req_data, + output wire chnl_0_req_ready, + + output wire chnl_0_resp_valid, + output wire [`MAX_DB_SLOT_NUM_LOG - 1 : 0] chnl_0_resp_data, + + input wire chnl_1_req_valid, + input wire chnl_1_req_start, + input wire chnl_1_req_last, + input wire [`MAX_DB_SLOT_NUM_LOG - 1 : 0] chnl_1_req_head, + input wire [`PACKET_BUFFER_SLOT_WIDTH - 1 : 0] chnl_1_req_data, + output wire chnl_1_req_ready, + + output wire chnl_1_resp_valid, + output wire [`MAX_DB_SLOT_NUM_LOG - 1 : 0] chnl_1_resp_data, + + output wire insert_req_valid, + output wire insert_req_start, + output wire insert_req_last, + output wire [`MAX_DB_SLOT_NUM_LOG - 1 : 0] insert_req_head, + output wire [`PACKET_BUFFER_SLOT_WIDTH - 1 : 0] insert_req_data, + input wire insert_req_ready, + + input wire insert_resp_valid, + input wire [`MAX_DB_SLOT_NUM_LOG - 1 : 0] insert_resp_data +); + +/*------------------------------------------- Input/Output Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Macros Definition : Begin ---------------------------------------*/ +`define CHNL_0 0 +`define CHNL_1 1 +/*------------------------------------------- Local Macros Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Variables Definition : Begin ------------------------------------*/ +reg [0:0] last_sch_chnl; +/*------------------------------------------- Local Variables Definition : End --------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : Begin ---------------------------------------*/ +/*------------------------------------------- Submodules Instatiation : End -----------------------------------------*/ + +/*------------------------------------------- State Machine Definition : Begin --------------------------------------*/ +reg [1:0] cur_state; +reg [1:0] next_state; + +parameter [1:0] IDLE_s = 2'd1, + CHNL_0_s = 2'd2, + CHNL_1_s = 2'd3; + +always @(posedge clk or posedge rst) begin + if (rst) begin + cur_state <= IDLE_s; + end + else begin + cur_state <= next_state; + end +end + +always @(*) begin + case(cur_state) + IDLE_s: if(last_sch_chnl == `CHNL_0 && chnl_1_req_valid) begin + next_state = CHNL_1_s; + end + else if(last_sch_chnl == `CHNL_1 && chnl_0_req_valid) begin + next_state = CHNL_0_s; + end + else if(last_sch_chnl == `CHNL_1 && !chnl_0_req_valid && chnl_1_req_valid) begin + next_state = CHNL_1_s; + end + else if(last_sch_chnl == `CHNL_0 && !chnl_1_req_valid && chnl_0_req_valid) begin + next_state = CHNL_0_s; + end + else begin + next_state = IDLE_s; + end + CHNL_0_s: if(chnl_0_req_last && chnl_0_req_last && chnl_0_req_ready) begin + next_state = IDLE_s; + end + else begin + next_state = CHNL_0_s; + end + CHNL_1_s: if(chnl_1_req_last && chnl_1_req_last && chnl_1_req_ready) begin + next_state = IDLE_s; + end + else begin + next_state = CHNL_1_s; + end + default: next_state = IDLE_s; + endcase +end +/*------------------------------------------- State Machine Definition : End ----------------------------------------*/ + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ +//-- last_sch_chnl -- +always @(posedge clk or posedge rst) begin + if (rst) begin + last_sch_chnl <= `CHNL_0; + end + else if (cur_state == CHNL_0_s && chnl_0_req_last && chnl_0_req_ready) begin + last_sch_chnl <= `CHNL_0; + end + else if (cur_state == CHNL_1_s && chnl_1_req_last && chnl_1_req_ready) begin + last_sch_chnl <= `CHNL_1; + end + else begin + last_sch_chnl <= last_sch_chnl; + end +end + +//-- chnl_0_req_ready -- +assign chnl_0_req_ready = (cur_state == CHNL_0_s) ? insert_req_ready : 'd0; + +//-- chnl_1_req_ready -- +assign chnl_1_req_ready = (cur_state == CHNL_1_s) ? insert_req_ready : 'd0; + +//-- chnl_0_resp_valid -- +//-- chnl_0_resp_data -- +assign chnl_0_resp_valid = (cur_state == CHNL_0_s) ? insert_resp_valid : 'd0; +assign chnl_0_resp_data = (cur_state == CHNL_0_s) ? insert_resp_data : 'd0; + +//-- chnl_1_resp_valid -- +//-- chnl_1_resp_data -- +assign chnl_1_resp_valid = (cur_state == CHNL_1_s) ? insert_resp_valid : 'd0; +assign chnl_1_resp_data = (cur_state == CHNL_1_s) ? insert_resp_data : 'd0; + +//-- insert_req_valid -- +//-- insert_req_start -- +//-- insert_req_last -- +//-- insert_req_head -- +//-- insert_req_data -- +assign insert_req_valid = (cur_state == CHNL_0_s) ? chnl_0_req_valid : + (cur_state == CHNL_1_s) ? chnl_1_req_valid : 'd0; +assign insert_req_start = (cur_state == CHNL_0_s) ? chnl_0_req_start : + (cur_state == CHNL_1_s) ? chnl_1_req_start : 'd0; +assign insert_req_last = (cur_state == CHNL_0_s) ? chnl_0_req_last : + (cur_state == CHNL_1_s) ? chnl_1_req_last : 'd0; +assign insert_req_head = (cur_state == CHNL_0_s) ? chnl_0_req_head : + (cur_state == CHNL_1_s) ? chnl_1_req_head : 'd0; +assign insert_req_data = (cur_state == CHNL_0_s) ? chnl_0_req_data : + (cur_state == CHNL_1_s) ? chnl_1_req_data : 'd0; +/*------------------------------------------- Variables Decode : End ----------------------------------------------*/ + +/*------------------------------------------- Local Macros Undef : Begin --------------------------------------------*/ + +/*------------------------------------------- Local Macros Undef : End ----------------------------------------------*/ + +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Peripherals/DynamicMultiQueue.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Peripherals/DynamicMultiQueue.v new file mode 100644 index 0000000000000000000000000000000000000000..d19e8b4186e47d81dee6341814bacc1f210a7a81 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Peripherals/DynamicMultiQueue.v @@ -0,0 +1,1058 @@ +/*------------------------------------------- Module Description : Begin ---------------------------------------------- +Name: DynamicMultiQueue +Author: YangFan +Function: A buffer abstraction, dynamically allocates buffer space for various queues. + Provides 4 interfaces: Enqueue, Dequeue, Modify Head and Get Head. + Total buffer space and queue number can be configured. +--------------------------------------------- Module Decription : End -----------------------------------------------*/ + +/*------------------------------------------- Timescale Definition : Begin ------------------------------------------*/ +`timescale 1ns / 1ps +/*------------------------------------------- Timescale Definition : End --------------------------------------------*/ + +/*------------------------------------------- Included Files : Begin ------------------------------------------------*/ +`include "common_function_def.vh" +/*------------------------------------------- Included Files : End --------------------------------------------------*/ + +/*------------------------------------------- Local Macros Definition : Begin ---------------------------------------*/ +//None +/*------------------------------------------- Local Macros Definition : End -----------------------------------------*/ + +/*------------------------------------------- Input/Output Definition : Begin ---------------------------------------*/ +module DynamicMultiQueue #( + //Queue Buffer is comprised of numbers of slots, slot is the basic unit that DMQ operates on. Default SLOT_WIDTH is aligned with Data Bus Width. + parameter SLOT_WIDTH = 512, + parameter SLOT_NUM = 512, + //Queue Buffer is shared by numbers of queues, each queue occupies contiguous or non-contiguous space in a True-Dual-Port SRAM. + parameter QUEUE_NUM = 32, + parameter SLOT_NUM_LOG = log2b(SLOT_NUM - 1), + parameter QUEUE_NUM_LOG = log2b(QUEUE_NUM - 1) +)( + input wire clk, + input wire rst, + +//Queue state interface, indicates how many slots are available. Users should ensure that there are enough slots for the items to be stored. + output wire [`MAX_OOO_SLOT_NUM_LOG : 0] ov_available_slot_num, + +//Enqueue interface +//Head format: +//{slot number, queue index} + input wire i_enqueue_req_valid, + input wire [`MAX_QP_NUM_LOG + `MAX_OOO_SLOT_NUM_LOG - 1 : 0] iv_enqueue_req_head, + input wire [SLOT_WIDTH - 1 : 0] iv_enqueue_req_data, + input wire i_enqueue_req_start, + input wire i_enqueue_req_last, + output wire o_enqueue_req_ready, + + input wire i_empty_req_valid, + input wire [`MAX_QP_NUM_LOG - 1 : 0] iv_empty_req_head, + output reg o_empty_req_ready, + + output reg o_empty_resp_valid, + output reg [`MAX_QP_NUM_LOG : 0] ov_empty_resp_head, + input wire i_empty_resp_ready, + +//Dequeue interface +//Head format: +//{slot number, queue index} + input wire i_dequeue_req_valid, + input wire [`MAX_QP_NUM_LOG + `MAX_OOO_SLOT_NUM_LOG - 1 : 0] iv_dequeue_req_head, + output wire o_dequeue_req_ready, + + output wire o_dequeue_resp_valid, + output wire [`MAX_QP_NUM_LOG + `MAX_OOO_SLOT_NUM_LOG - 1 : 0] ov_dequeue_resp_head, + output wire o_dequeue_resp_start, + output wire o_dequeue_resp_last, + input wire i_dequeue_resp_ready, + output wire [SLOT_WIDTH - 1 : 0] ov_dequeue_resp_data, + +//Modify queue head interface +//Head format: +//{queue index} + input wire i_modify_head_req_valid, + input wire [`MAX_QP_NUM_LOG - 1 : 0] iv_modify_head_req_head, + input wire [SLOT_WIDTH - 1 : 0] iv_modify_head_req_data, + output wire o_modify_head_req_ready, + +//Obtain queue head interface +//Head format: +//{queue index} + input wire i_get_req_valid, + input wire [`MAX_QP_NUM_LOG + `MAX_OOO_SLOT_NUM_LOG - 1 : 0] iv_get_req_head, + output wire o_get_req_ready, + + output wire o_get_resp_valid, + output wire [`MAX_QP_NUM_LOG + `MAX_OOO_SLOT_NUM_LOG - 1 : 0] ov_get_resp_head, + output wire o_get_resp_start, + output wire o_get_resp_last, + output wire [SLOT_WIDTH - 1 : 0] ov_get_resp_data, + output wire o_get_resp_empty, + input wire i_get_resp_ready +); +/*------------------------------------------- Input/Output Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Variables Definition : Begin ------------------------------------*/ +reg [`MAX_QP_NUM_LOG + `MAX_OOO_SLOT_NUM_LOG - 1 : 0] qv_enqueue_req_head; +reg [`MAX_QP_NUM_LOG + `MAX_OOO_SLOT_NUM_LOG - 1 : 0] qv_empty_req_head; +reg [`MAX_QP_NUM_LOG + `MAX_OOO_SLOT_NUM_LOG - 1 : 0] qv_dequeue_req_head; + +reg [QUEUE_NUM_LOG - 1 : 0] qv_consumer_queue_index; + +reg head_table_wea; +reg [QUEUE_NUM_LOG - 1 : 0] head_table_addra; +reg [SLOT_NUM_LOG : 0] head_table_dina; +wire [SLOT_NUM_LOG : 0] head_table_douta; +reg head_table_web; +reg [QUEUE_NUM_LOG - 1 : 0] head_table_addrb; +reg [QUEUE_NUM_LOG - 1 : 0] head_table_addrb_diff; +reg [SLOT_NUM_LOG : 0] head_table_dinb; +wire [SLOT_NUM_LOG : 0] head_table_doutb; + +reg tail_table_wea; +reg [QUEUE_NUM_LOG - 1 : 0] tail_table_addra; +reg [SLOT_NUM_LOG - 1 : 0] tail_table_dina; +wire [SLOT_NUM_LOG - 1 : 0] tail_table_douta; +reg tail_table_web; +reg [QUEUE_NUM_LOG - 1 : 0] tail_table_addrb; +reg [QUEUE_NUM_LOG - 1 : 0] tail_table_addrb_diff; +reg [SLOT_NUM_LOG - 1 : 0] tail_table_dinb; +wire [SLOT_NUM_LOG - 1 : 0] tail_table_doutb; + +reg empty_table_wea; +reg [QUEUE_NUM_LOG - 1 : 0] empty_table_addra; +reg [0 : 0] empty_table_dina; +wire [0 : 0] empty_table_douta; +reg empty_table_web; +reg [QUEUE_NUM_LOG - 1 : 0] empty_table_addrb; +reg [QUEUE_NUM_LOG - 1 : 0] empty_table_addrb_diff; +reg [0 : 0] empty_table_dinb; +wire [0 : 0] empty_table_doutb; + +reg content_table_wea; +reg [SLOT_NUM_LOG - 1 : 0] content_table_addra; +reg [SLOT_WIDTH - 1 : 0] content_table_dina; +wire [SLOT_WIDTH - 1 : 0] content_table_douta; +reg content_table_web; +reg [SLOT_NUM_LOG - 1 : 0] content_table_addrb; +reg [SLOT_NUM_LOG - 1 : 0] content_table_addrb_diff; +reg [SLOT_WIDTH - 1 : 0] content_table_dinb; +wire [SLOT_WIDTH - 1 : 0] content_table_doutb; + +reg next_table_wea; +reg [SLOT_NUM_LOG - 1 : 0] next_table_addra; +reg [SLOT_NUM_LOG - 1 : 0] next_table_dina; +wire [SLOT_NUM_LOG - 1 : 0] next_table_douta; +reg next_table_web; +reg [SLOT_NUM_LOG - 1 : 0] next_table_addrb; +reg [SLOT_NUM_LOG - 1 : 0] next_table_addrb_diff; +reg [SLOT_NUM_LOG - 1 : 0] next_table_dinb; +wire [SLOT_NUM_LOG - 1 : 0] next_table_doutb; + +reg free_wr_en; +reg [SLOT_NUM_LOG - 1 : 0] free_din; +wire free_prog_full; +reg free_rd_en; +wire [SLOT_NUM_LOG - 1 : 0] free_dout; +wire free_empty; +wire [SLOT_NUM_LOG : 0] free_data_count; + +reg [QUEUE_NUM_LOG : 0] metadata_init_counter; +wire metadata_init_finish; +reg [SLOT_NUM_LOG : 0] slot_init_counter; +wire slot_init_finish; + +reg [SLOT_NUM_LOG : 0] qv_enqueue_left_num; +reg [SLOT_NUM_LOG : 0] qv_dequeue_left_num; + +reg q_dequeue_resp_valid; +reg [SLOT_WIDTH - 1 : 0] qv_dequeue_resp_data; +reg q_get_resp_valid; +reg [SLOT_WIDTH - 1 : 0] qv_get_resp_data; +reg q_get_resp_empty; + +reg [SLOT_WIDTH - 1 : 0] qv_modify_head_data; + +reg q_dequeue_req_valid_diff; +reg q_modify_head_req_valid_diff; +reg q_get_req_valid_diff; +/*------------------------------------------- Local Variables Definition : End --------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : Begin ---------------------------------------*/ +//Head Table +SRAM_TDP_Template +#( + .RAM_WIDTH ( SLOT_NUM_LOG ), + .RAM_DEPTH ( QUEUE_NUM ) +) +MQ_HeadTable( + .clk ( clk ), + .rst ( rst ), + + .wea ( head_table_wea ), + .addra ( head_table_addra ), + .dina ( head_table_dina ), + .douta ( head_table_douta ), + + .web ( head_table_web ), + .addrb ( head_table_addrb ), + .dinb ( head_table_dinb ), + .doutb ( head_table_doutb ) +); + +//Tail Table +SRAM_TDP_Template +#( + .RAM_WIDTH ( SLOT_NUM_LOG ), + .RAM_DEPTH ( QUEUE_NUM ) +) +MQ_TailTable( + .clk ( clk ), + .rst ( rst ), + + .wea ( tail_table_wea ), + .addra ( tail_table_addra ), + .dina ( tail_table_dina ), + .douta ( tail_table_douta ), + + .web ( tail_table_web ), + .addrb ( tail_table_addrb ), + .dinb ( tail_table_dinb ), + .doutb ( tail_table_doutb ) +); + +//Empty Table +SRAM_TDP_Template +#( + .RAM_WIDTH ( 1 ), + .RAM_DEPTH ( QUEUE_NUM ) +) +MQ_EmptyTable( + .clk ( clk ), + .rst ( rst ), + + .wea ( empty_table_wea ), + .addra ( empty_table_addra ), + .dina ( empty_table_dina ), + .douta ( empty_table_douta ), + + .web ( empty_table_web ), + .addrb ( empty_table_addrb ), + .dinb ( empty_table_dinb ), + .doutb ( empty_table_doutb ) +); + +//Content Table +SRAM_TDP_Template +#( + .RAM_WIDTH ( SLOT_WIDTH ), + .RAM_DEPTH ( SLOT_NUM ) +) +MQ_ContentTable( + .clk ( clk ), + .rst ( rst ), + + .wea ( content_table_wea ), + .addra ( content_table_addra ), + .dina ( content_table_dina ), + .douta ( content_table_douta ), + + .web ( content_table_web ), + .addrb ( content_table_addrb ), + .dinb ( content_table_dinb ), + .doutb ( content_table_doutb ) +); + +//Next Table +SRAM_TDP_Template +#( + .RAM_WIDTH ( SLOT_NUM_LOG ), + .RAM_DEPTH ( SLOT_NUM ) +) +MQ_NextTable( + .clk ( clk ), + .rst ( rst ), + + .wea ( next_table_wea ), + .addra ( next_table_addra ), + .dina ( next_table_dina ), + .douta ( next_table_douta ), + + .web ( next_table_web ), + .addrb ( next_table_addrb ), + .dinb ( next_table_dinb ), + .doutb ( next_table_doutb ) +); + +//FreeList +SyncFIFO_Template +#( + .FIFO_WIDTH ( SLOT_NUM_LOG ), + .FIFO_DEPTH ( SLOT_NUM ) +) +FreeListFIFO +( + .clk ( clk ), + .rst ( rst ), + + .wr_en ( free_wr_en ), + .din ( free_din ), + .prog_full ( free_prog_full ), + .rd_en ( free_rd_en ), + .dout ( free_dout ), + .empty ( free_empty ), + .data_count ( free_data_count ) +); +/*------------------------------------------- Submodules Instatiation : End -----------------------------------------*/ + +/*------------------------------------------- State Machine Definition : Begin --------------------------------------*/ +//Producer state machine +reg [1:0] Producer_cur_state; +reg [1:0] Producer_next_state; + +parameter PRODUCER_IDLE_s = 2'd1, + PRODUCER_ENQUEUE_s = 2'd2, + PRODUCER_EMPTY_s = 2'd3; + +always @(posedge clk or posedge rst) begin + if(rst) begin + Producer_cur_state <= PRODUCER_IDLE_s; + end + else begin + Producer_cur_state <= Producer_next_state; + end +end + +always @(*) begin + case(Producer_cur_state) + PRODUCER_IDLE_s: if(metadata_init_finish && slot_init_finish) begin + if(i_enqueue_req_valid) begin + Producer_next_state = PRODUCER_ENQUEUE_s; + end + else if(i_empty_req_valid) begin + Producer_next_state = PRODUCER_EMPTY_s; + end + else begin + Producer_next_state = PRODUCER_IDLE_s; + end + end + else begin + Producer_next_state = PRODUCER_IDLE_s; + end + PRODUCER_ENQUEUE_s: if(i_enqueue_req_valid && qv_enqueue_left_num == 1 && !free_empty) begin + Producer_next_state = PRODUCER_IDLE_s; + end + else begin + Producer_next_state = PRODUCER_ENQUEUE_s; + end + PRODUCER_EMPTY_s: if(o_empty_resp_valid && i_empty_resp_ready) begin + Producer_next_state = PRODUCER_IDLE_s; + end + else begin + Producer_next_state = PRODUCER_EMPTY_s; + end + default: Producer_next_state = PRODUCER_IDLE_s; + endcase +end + +//Consumer state machine +reg [2:0] Consumer_cur_state; +reg [2:0] Consumer_next_state; + +parameter CONSUMER_IDLE_s = 3'd1, + CONSUMER_PREPARE_s = 3'd2, + CONSUMER_DEQUEUE_s = 3'd3, + CONSUMER_MODIFY_HEAD_s = 3'd4, + CONSUMER_GET_s = 3'd5; + +always @(posedge clk or posedge rst) begin + if(rst) begin + Consumer_cur_state <= CONSUMER_IDLE_s; + end + else begin + Consumer_cur_state <= Consumer_next_state; + end +end + +always @(*) begin + case(Consumer_cur_state) + CONSUMER_IDLE_s: if(metadata_init_finish && slot_init_finish) begin + if(i_dequeue_req_valid || i_modify_head_req_valid || i_get_req_valid) begin + Consumer_next_state = CONSUMER_PREPARE_s; + end + else begin + Consumer_next_state = CONSUMER_IDLE_s; + end + end + else begin + Consumer_next_state = CONSUMER_IDLE_s; + end + CONSUMER_PREPARE_s: if(q_dequeue_req_valid_diff) begin + Consumer_next_state = CONSUMER_DEQUEUE_s; + end + else if(q_modify_head_req_valid_diff) begin + Consumer_next_state = CONSUMER_MODIFY_HEAD_s; + end + else if(q_get_req_valid_diff) begin + Consumer_next_state = CONSUMER_GET_s; + end + else begin + Consumer_next_state = CONSUMER_PREPARE_s; + end + CONSUMER_DEQUEUE_s: if(o_dequeue_resp_valid && i_dequeue_resp_ready && qv_dequeue_left_num == 'd1) begin + Consumer_next_state = CONSUMER_IDLE_s; + end + else begin + Consumer_next_state = CONSUMER_DEQUEUE_s; + end + CONSUMER_MODIFY_HEAD_s: Consumer_next_state = CONSUMER_IDLE_s; + CONSUMER_GET_s: if(i_get_resp_ready) begin + Consumer_next_state = CONSUMER_IDLE_s; + end + else begin + Consumer_next_state = CONSUMER_GET_s; + end + default: Consumer_next_state = CONSUMER_IDLE_s; + endcase +end + +/*------------------------------------------- State Machine Definition : End ----------------------------------------*/ + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ +//-- metadata_init_finish -- +assign metadata_init_finish = (metadata_init_counter == QUEUE_NUM); + +//-- o_enqueue_req_ready -- +assign o_enqueue_req_ready = (Producer_cur_state == PRODUCER_ENQUEUE_s) && !free_empty; + +//-- slot_init_finish -- +assign slot_init_finish = (slot_init_counter == SLOT_NUM); + +//-- ov_available-slot_num -- +assign ov_available_slot_num = free_data_count; + +//-- o_dequeue_resp_valid -- +assign o_dequeue_resp_valid = q_dequeue_resp_valid; + +//-- ov_dequeue_resp_data -- +assign ov_dequeue_resp_data = qv_dequeue_resp_data; + +//-- ov_dequeue_resp_head -- +//-- o_dequeue_resp_start -- +//-- o_dequeue_resp_last -- +assign ov_dequeue_resp_head = (Consumer_cur_state == CONSUMER_DEQUEUE_s) ? qv_dequeue_req_head : 'd0; +assign o_dequeue_resp_start = (Consumer_cur_state == CONSUMER_DEQUEUE_s) ? (qv_dequeue_left_num == qv_dequeue_req_head[`MAX_OOO_SLOT_NUM_LOG + `MAX_QP_NUM_LOG - 1 : `MAX_QP_NUM_LOG]) : 'd0; +assign o_dequeue_resp_last = (Consumer_cur_state == CONSUMER_DEQUEUE_s) ? (qv_dequeue_left_num == 'd1) : 'd0; + +//-- o_get_resp_valid -- +assign o_get_resp_valid = q_get_resp_valid; + +//-- ov_get_resp_data -- +assign ov_get_resp_data = qv_get_resp_data; + +//-- o_get_resp_empty -- +assign o_get_resp_empty = q_get_resp_empty; + +//-- ov_get_resp_head -- +//-- o_get_resp_start -- +//-- o_get_resp_last -- +assign ov_get_resp_head = (Consumer_cur_state == CONSUMER_GET_s) ? iv_get_req_head : 'd0; +assign o_get_resp_start = (Consumer_cur_state == CONSUMER_GET_s) ? 'd1 : 'd0; +assign o_get_resp_last = (Consumer_cur_state == CONSUMER_GET_s) ? 'd1 : 'd0; + +//-- o_dequeue_req_ready -- +assign o_dequeue_req_ready = (Consumer_cur_state == CONSUMER_IDLE_s); + +//-- o_modify_head_req_ready -- +assign o_modify_head_req_ready = (Consumer_cur_state == CONSUMER_IDLE_s); + +//-- o_get_req_ready -- +assign o_get_req_ready = (Consumer_cur_state == CONSUMER_IDLE_s); + +//-- q_dequeue_req_valid_diff -- +//-- q_modify_head_req_valid_diff -- +//-- q_get_req_valid_diff -- +always @(posedge clk or posedge rst) begin + if(rst) begin + q_dequeue_req_valid_diff <= 'd0; + q_modify_head_req_valid_diff <= 'd0; + q_get_req_valid_diff <= 'd0; + end + else begin + q_dequeue_req_valid_diff <= i_dequeue_req_valid; + q_modify_head_req_valid_diff <= i_modify_head_req_valid; + q_get_req_valid_diff <= i_get_req_valid; + end +end + +//-- meta_data_init_counter -- +always @(posedge clk or posedge rst) begin + if(rst) begin + metadata_init_counter <= 'd0; + end + else if(metadata_init_counter < QUEUE_NUM) begin + metadata_init_counter <= metadata_init_counter + 'd1; + end + else begin + metadata_init_counter <= metadata_init_counter; + end +end + +//-- slot_init_counter -- +always @(posedge clk or posedge rst) begin + if(rst) begin + slot_init_counter <= 'd0; + end + else if(slot_init_counter < SLOT_NUM) begin + slot_init_counter <= slot_init_counter + 'd1; + end + else begin + slot_init_counter <= slot_init_counter; + end +end + + +//-- qv_enqueue_left_num -- +always @(posedge clk or posedge rst) begin + if(rst) begin + qv_enqueue_left_num <= 'd0; + end + else if(Producer_cur_state == PRODUCER_IDLE_s && i_enqueue_req_valid) begin + qv_enqueue_left_num <= iv_enqueue_req_head[`MAX_OOO_SLOT_NUM_LOG + `MAX_QP_NUM_LOG - 1 : `MAX_QP_NUM_LOG]; + end + else if(Producer_cur_state == PRODUCER_ENQUEUE_s && i_enqueue_req_valid && o_enqueue_req_ready) begin + qv_enqueue_left_num <= qv_enqueue_left_num - 'd1; + end + else begin + qv_enqueue_left_num <= qv_enqueue_left_num; + end +end + +//-- qv_dequeue_left_num -- +always @(posedge clk or posedge rst) begin + if(rst) begin + qv_dequeue_left_num <= 'd0; + end + else if(Consumer_cur_state == CONSUMER_IDLE_s && i_dequeue_req_valid) begin + qv_dequeue_left_num <= iv_dequeue_req_head[`MAX_OOO_SLOT_NUM_LOG + `MAX_QP_NUM_LOG - 1 : `MAX_QP_NUM_LOG]; + end + else if(Consumer_cur_state == CONSUMER_DEQUEUE_s && o_dequeue_resp_valid && i_dequeue_resp_ready) begin + qv_dequeue_left_num <= qv_dequeue_left_num - 'd1; + end + else begin + qv_dequeue_left_num <= qv_dequeue_left_num; + end +end + +//-- head_table_wea -- +//-- head_table_addra -- +//-- head_table_dina -- +always @(*) begin + if(!metadata_init_finish) begin + head_table_wea = 'd1; + head_table_addra = metadata_init_counter; + head_table_dina = 'd0; + end + else if(Producer_cur_state == PRODUCER_IDLE_s && i_enqueue_req_valid) begin + head_table_wea = 'd0; + head_table_addra = iv_enqueue_req_head[`MAX_QP_NUM_LOG - 1 : 0]; + head_table_dina = 'd0; + end + else if(Producer_cur_state == PRODUCER_ENQUEUE_s && i_enqueue_req_valid && o_enqueue_req_ready) begin + if(empty_table_douta) begin //First enqueue, update head + head_table_wea = 'd1; + head_table_addra = qv_enqueue_req_head[`MAX_QP_NUM_LOG - 1 : 0]; + head_table_dina = free_dout; + end + else if(!empty_table_douta && (head_table_douta == tail_table_douta) && (Consumer_cur_state == CONSUMER_DEQUEUE_s) && (qv_enqueue_req_head[`MAX_QP_NUM_LOG - 1 : 0] == qv_dequeue_req_head[`MAX_QP_NUM_LOG - 1 : 0]) + && o_dequeue_resp_valid && i_dequeue_resp_ready) begin + head_table_wea = 'd1; //Last element is being dequeued, modify head + head_table_addra = qv_enqueue_req_head[`MAX_QP_NUM_LOG - 1 : 0]; + head_table_dina = free_dout; + end + else begin + head_table_wea = 'd0; + head_table_addra = qv_enqueue_req_head[`MAX_QP_NUM_LOG - 1 : 0]; + head_table_dina = 'd0; + end + end + else begin + head_table_wea = 'd0; + head_table_addra = qv_enqueue_req_head[`MAX_QP_NUM_LOG - 1 : 0]; + head_table_dina = 'd0; + end +end + +//-- head_table_web -- +//-- head_table_addrb -- +//-- head_table_dinb -- +always @(*) begin + if(Consumer_cur_state == CONSUMER_IDLE_s && i_dequeue_req_valid) begin + head_table_web = 'd0; + head_table_addrb = iv_dequeue_req_head[`MAX_QP_NUM_LOG - 1 : 0]; + head_table_dinb = 'd0; + end + else if(Consumer_cur_state == CONSUMER_IDLE_s && i_modify_head_req_valid) begin + head_table_web = 'd0; + head_table_addrb = iv_modify_head_req_head[`MAX_QP_NUM_LOG - 1 : 0]; + head_table_dinb = 'd0; + end + else if(Consumer_cur_state == CONSUMER_IDLE_s && i_get_req_valid) begin + head_table_web = 'd0; + head_table_addrb = iv_get_req_head[`MAX_QP_NUM_LOG - 1 : 0]; + head_table_dinb = 'd0; + end + else if(Consumer_cur_state == CONSUMER_PREPARE_s) begin + head_table_web = 'd0; + head_table_addrb = qv_consumer_queue_index; + head_table_dinb = 'd0; + end + else if(Consumer_cur_state == CONSUMER_DEQUEUE_s && o_dequeue_resp_valid && i_dequeue_resp_ready) begin + if(head_table_doutb == tail_table_doutb) begin //Last element, no need to modify queue head + head_table_web = 'd0; + head_table_addrb = qv_consumer_queue_index; + head_table_dinb = 'd0; + end + else begin + head_table_web = 'd1; + head_table_addrb = qv_consumer_queue_index; + head_table_dinb = next_table_doutb; + end + end + else begin + head_table_web = 'd0; + head_table_addrb = qv_consumer_queue_index; + head_table_dinb = 'd0; + end +end + +//-- tail_table_wea -- +//-- tail_table_addra -- +//-- tail_table_dina -- +always @(*) begin + if(!metadata_init_finish) begin + tail_table_wea = 'd1; + tail_table_addra = metadata_init_counter; + tail_table_dina = 'd0; + end + else if(Producer_cur_state == PRODUCER_IDLE_s && i_enqueue_req_valid) begin + tail_table_wea = 'd0; + tail_table_addra = iv_enqueue_req_head[`MAX_QP_NUM_LOG - 1 : 0]; + tail_table_dina = 'd0; + end + else if(Producer_cur_state == PRODUCER_ENQUEUE_s && i_enqueue_req_valid && o_enqueue_req_ready) begin + tail_table_wea = 'd1; + tail_table_addra = qv_enqueue_req_head[`MAX_QP_NUM_LOG - 1 : 0]; + tail_table_dina = free_dout; + end + else begin + tail_table_wea = 'd0; + tail_table_addra = qv_enqueue_req_head[`MAX_QP_NUM_LOG - 1 : 0]; + tail_table_dina = 'd0; + end +end + +//-- tail_table_web -- +//-- tail_table_addrb -- +//-- tail_table_dinb -- +always @(*) begin + if(Consumer_cur_state == CONSUMER_IDLE_s && i_dequeue_req_valid) begin + tail_table_web = 'd0; + tail_table_addrb = iv_dequeue_req_head[`MAX_QP_NUM_LOG - 1 : 0]; + tail_table_dinb = 'd0; + end + else if(Consumer_cur_state == CONSUMER_IDLE_s && i_modify_head_req_valid) begin + tail_table_web = 'd0; + tail_table_addrb = iv_modify_head_req_head[`MAX_QP_NUM_LOG - 1 : 0]; + tail_table_dinb = 'd0; + end + else if(Consumer_cur_state == CONSUMER_IDLE_s && i_get_req_valid) begin + tail_table_web = 'd0; + tail_table_addrb = iv_get_req_head[`MAX_QP_NUM_LOG - 1 : 0]; + tail_table_dinb = 'd0; + end + else if(Consumer_cur_state == CONSUMER_PREPARE_s) begin + tail_table_web = 'd0; + tail_table_addrb = qv_consumer_queue_index; + tail_table_dinb = 'd0; + end + else begin + tail_table_web = 'd0; + tail_table_addrb = qv_dequeue_req_head[`MAX_QP_NUM_LOG - 1 : 0]; + tail_table_dinb = 'd0; + end +end + +//-- empty_table_wea -- +//-- empty_table_addra -- +//-- empty_table_dina -- +always @(*) begin + if(!metadata_init_finish) begin + empty_table_wea = 'd1; + empty_table_addra = metadata_init_counter; + empty_table_dina = 'd1; + end + else if(Producer_cur_state == PRODUCER_IDLE_s && i_enqueue_req_valid) begin + empty_table_wea = 'd0; + empty_table_addra = iv_enqueue_req_head[`MAX_QP_NUM_LOG - 1 : 0]; + empty_table_dina = 'd0; + end + else if(Producer_cur_state == PRODUCER_IDLE_s && i_empty_req_valid) begin + empty_table_wea = 'd0; + empty_table_addra = iv_empty_req_head[`MAX_QP_NUM_LOG - 1 : 0]; + empty_table_dina = 'd0; + end + else if(Producer_cur_state == PRODUCER_ENQUEUE_s && i_enqueue_req_valid && o_enqueue_req_ready) begin + if(empty_table_douta) begin + empty_table_wea = 'd1; + empty_table_addra = qv_enqueue_req_head[`MAX_QP_NUM_LOG - 1 : 0]; + empty_table_dina = 'd0; + end + else if(!empty_table_douta && (head_table_douta == tail_table_douta) && (Consumer_cur_state == CONSUMER_DEQUEUE_s) && (qv_enqueue_req_head[`MAX_QP_NUM_LOG - 1 : 0] == qv_dequeue_req_head[`MAX_QP_NUM_LOG - 1 : 0]) + && o_dequeue_resp_valid && i_dequeue_resp_ready) begin + empty_table_wea = 'd1; + empty_table_addra = qv_enqueue_req_head[`MAX_QP_NUM_LOG - 1 : 0]; + empty_table_dina = 'd0; + end + else begin + empty_table_wea = 'd0; + empty_table_addra = qv_enqueue_req_head[`MAX_QP_NUM_LOG - 1 : 0]; + empty_table_dina = 'd0; + end + end + else if(Producer_cur_state == PRODUCER_EMPTY_s) begin + empty_table_wea = 'd0; + empty_table_addra = qv_empty_req_head[`MAX_QP_NUM_LOG - 1 : 0]; + empty_table_dina = 'd0; + end + else begin + empty_table_wea = 'd0; + empty_table_addra = qv_enqueue_req_head[`MAX_QP_NUM_LOG - 1 : 0]; + empty_table_dina = 'd0; + end +end + +//-- empty_table_web -- +//-- empty_table_addrb -- +//-- empty_table_dinb -- +always @(*) begin + if(Consumer_cur_state == CONSUMER_IDLE_s && i_dequeue_req_valid) begin + empty_table_web = 'd0; + empty_table_addrb = iv_dequeue_req_head[`MAX_QP_NUM_LOG - 1 : 0]; + empty_table_dinb = 'd0; + end + else if(Consumer_cur_state == CONSUMER_IDLE_s && i_modify_head_req_valid) begin + empty_table_web = 'd0; + empty_table_addrb = iv_modify_head_req_head[`MAX_QP_NUM_LOG - 1 : 0]; + empty_table_dinb = 'd0; + end + else if(Consumer_cur_state == CONSUMER_IDLE_s && i_get_req_valid) begin + empty_table_web = 'd0; + empty_table_addrb = iv_get_req_head[`MAX_QP_NUM_LOG - 1 : 0]; + empty_table_dinb = 'd0; + end + else if(Consumer_cur_state == CONSUMER_DEQUEUE_s && o_dequeue_resp_valid && i_dequeue_resp_ready && (head_table_doutb == tail_table_doutb)) begin //Dequeue last elment + if((Producer_cur_state != PRODUCER_ENQUEUE_s) || (qv_enqueue_req_head[`MAX_QP_NUM_LOG - 1 : 0] != qv_dequeue_req_head[`MAX_QP_NUM_LOG - 1 : 0])) begin //No concurrent enqueue + empty_table_web = 'd1; + empty_table_addrb = qv_consumer_queue_index; + empty_table_dinb = 'd1; + end + else begin + empty_table_web = 'd0; + empty_table_addrb = qv_consumer_queue_index; + empty_table_dinb = 'd0; + end + end + else begin + empty_table_web = 'd0; + empty_table_addrb = qv_consumer_queue_index; + empty_table_dinb = 'd0; + end +end + +//-- next_table_wea -- +//-- next_table_addra -- +//-- next_table_dina -- +always @(*) begin + if(!slot_init_finish) begin + next_table_wea = 'd1; + next_table_addra = slot_init_counter; + next_table_dina = 'd0; + end + else if(Producer_cur_state == PRODUCER_ENQUEUE_s && !empty_table_douta && i_enqueue_req_valid && o_enqueue_req_ready) begin + //Only when table and available slot not empty should we update next pointer + next_table_wea = 'd1; + next_table_addra = tail_table_douta; + next_table_dina = free_dout; + end + else begin + next_table_wea = 'd0; + next_table_addra = tail_table_douta; + next_table_dina = 'd0; + end +end + +//-- next_table_web -- +//-- next_table_addrb -- +//-- next_table_dinb -- +always @(*) begin + if(Consumer_cur_state == CONSUMER_PREPARE_s) begin + next_table_web = 'd0; + next_table_addrb = head_table_doutb; + next_table_dinb = 'd0; + end + else if(Consumer_cur_state == CONSUMER_DEQUEUE_s && o_dequeue_resp_valid && i_dequeue_resp_ready) begin + next_table_web = 'd0; + next_table_addrb = next_table_doutb; + next_table_dinb = 'd0; + end + else begin + next_table_web = 'd0; + next_table_addrb = next_table_addrb_diff; + next_table_dinb = 'd0; + end +end + +//-- content_table_wea -- +//-- content_table_addra -- +//-- content_table_dina -- +always @(*) begin + if(!slot_init_finish) begin + content_table_wea = 'd1; + content_table_addra = slot_init_counter; + content_table_dina = 'd0; + end + else if(Producer_cur_state == PRODUCER_ENQUEUE_s && i_enqueue_req_valid && o_enqueue_req_ready) begin + content_table_wea = 'd1; + content_table_addra = free_dout; + content_table_dina = iv_enqueue_req_data; + end + else begin + content_table_wea = 'd0; + content_table_addra = 'd0; + content_table_dina = 'd0; + end +end + +//-- content_table_web -- +//-- content_table_addrb -- +//-- content_table_dinb -- +always @(*) begin + if(Consumer_cur_state == CONSUMER_PREPARE_s) begin + content_table_web = 'd0; + content_table_addrb = head_table_doutb; + content_table_dinb = 'd0; + end + else if(Consumer_cur_state == CONSUMER_DEQUEUE_s && i_dequeue_resp_ready && o_dequeue_resp_valid) begin + content_table_web = 'd0; + content_table_addrb = next_table_doutb; + content_table_dinb = 'd0; + end + else if(Consumer_cur_state == CONSUMER_MODIFY_HEAD_s && !empty_table_doutb) begin + content_table_web = 'd1; + content_table_addrb = head_table_doutb; + content_table_dinb = qv_modify_head_data; + end + else begin + content_table_web = 'd0; + content_table_addrb = content_table_addrb_diff; + content_table_dinb = 'd0; + end +end + +//-- free_wr_en -- +//-- free_din -- +always @(posedge clk or posedge rst) begin + if(rst) begin + free_wr_en <= 'd0; + free_din <= 'd0; + end + else if(!slot_init_finish) begin + free_wr_en <= 'd1; + free_din <= slot_init_counter; + end + else if(Consumer_cur_state == CONSUMER_DEQUEUE_s && i_dequeue_resp_ready && o_dequeue_resp_valid) begin + free_wr_en <= 'd1; + free_din <= head_table_doutb; + end + else begin + free_wr_en <= 'd0; + free_din <= 'd0; + end +end + +//-- free_rd_en -- +always @(*) begin + if(rst) begin + free_rd_en = 'd0; + end + else if(Producer_cur_state == PRODUCER_ENQUEUE_s && i_enqueue_req_valid && o_enqueue_req_ready) begin + free_rd_en = 'd1; + end + else begin + free_rd_en = 'd0; + end +end + +//-- qv_enqueue_req_head -- +always @(posedge clk or posedge rst) begin + if(rst) begin + qv_enqueue_req_head <= 'd0; + end + else if(Producer_cur_state == PRODUCER_IDLE_s && i_enqueue_req_valid) begin + qv_enqueue_req_head <= iv_enqueue_req_head; + end + else begin + qv_enqueue_req_head <= qv_enqueue_req_head; + end +end + +//-- qv_empty_req_head -- +always @(posedge clk or posedge rst) begin + if(rst) begin + qv_empty_req_head <= 'd0; + end + else if(Producer_cur_state == PRODUCER_IDLE_s && i_empty_req_valid) begin + qv_empty_req_head <= iv_empty_req_head; + end + else begin + qv_empty_req_head <= qv_empty_req_head; + end +end + +//-- qv_modify_head_data -- +always @(posedge clk or posedge rst) begin + if(rst) begin + qv_modify_head_data <= 'd0; + end + else if(Consumer_cur_state == CONSUMER_IDLE_s && i_modify_head_req_valid) begin + qv_modify_head_data <= iv_modify_head_req_data; + end + else begin + qv_modify_head_data <= qv_modify_head_data; + end +end + +//-- qv_dequeue_req_head -- +always @(posedge clk or posedge rst) begin + if (rst) begin + qv_dequeue_req_head <= 'd0; + end + else if (Consumer_cur_state == CONSUMER_IDLE_s && i_dequeue_req_valid) begin + qv_dequeue_req_head <= iv_dequeue_req_head; + end + else begin + qv_dequeue_req_head <= qv_dequeue_req_head; + end +end + +//-- qv_consumer_queue_index -- +always @(posedge clk or posedge rst) begin + if(rst) begin + qv_consumer_queue_index <= 'd0; + end + else if(Consumer_cur_state == CONSUMER_IDLE_s && i_dequeue_req_valid) begin + qv_consumer_queue_index <= iv_dequeue_req_head; + end + else if(Consumer_cur_state == CONSUMER_IDLE_s && i_modify_head_req_valid) begin + qv_consumer_queue_index <= iv_modify_head_req_head; + end + else if(Consumer_cur_state == CONSUMER_IDLE_s && i_get_req_valid) begin + qv_consumer_queue_index <= iv_get_req_head; + end + else begin + qv_consumer_queue_index <= qv_consumer_queue_index; + end +end + +//-- q_dequeue_resp_valid -- +//-- qv_dequeue_resp_data -- +always @(*) begin + if(rst) begin + q_dequeue_resp_valid = 'd0; + qv_dequeue_resp_data = 'd0; + end + else if(Consumer_cur_state == CONSUMER_DEQUEUE_s) begin + q_dequeue_resp_valid = 'd1; + qv_dequeue_resp_data = content_table_doutb; + end + else begin + q_dequeue_resp_valid = 'd0; + qv_dequeue_resp_data = 'd0; + end +end + +//-- q_get_resp_valid -- +//-- qv_get_resp_data -- +always @(*) begin + if(rst) begin + q_get_resp_valid = 'd0; + qv_get_resp_data = 'd0; + q_get_resp_empty = 'd1; + end + else if(Consumer_cur_state == CONSUMER_GET_s) begin + q_get_resp_valid = 'd1; + qv_get_resp_data = content_table_doutb; + q_get_resp_empty = empty_table_doutb; + end + else begin + q_get_resp_valid = 'd0; + qv_get_resp_data = 'd0; + q_get_resp_empty = 'd1; + end +end + +//-- o_empty_req_ready -- +always @(*) begin + if(rst) begin + o_empty_req_ready = 'd0; + end + else if(Producer_cur_state == PRODUCER_IDLE_s) begin + o_empty_req_ready = 'd1; + end + else begin + o_empty_req_ready = 'd0; + end +end + +//-- o_empty_resp_valid -- +//-- ov_empty_resp_head -- +always @(*) begin + if(rst) begin + o_empty_resp_valid = 'd0; + ov_empty_resp_head = 'd0; + end + else if(Producer_cur_state == PRODUCER_EMPTY_s) begin + o_empty_resp_valid = 'd1; + ov_empty_resp_head = {empty_table_douta, qv_empty_req_head[`MAX_QP_NUM_LOG - 1 : 0]}; + end + else begin + o_empty_resp_valid = 'd0; + ov_empty_resp_head = 'd0; + end +end + + +//-- next_table_addrb_diff -- +//-- content_table_addrb_diff -- +//-- empty_table_addrb_diff -- +//-- tail_table_addrb_diff -- +//-- head_table_addrb_diff -- +always @(posedge clk or posedge rst) begin + if (rst) begin + next_table_addrb_diff <= 'd0; + content_table_addrb_diff <= 'd0; + empty_table_addrb_diff <= 'd0; + tail_table_addrb_diff <= 'd0; + head_table_addrb_diff <= 'd0; + end + else begin + next_table_addrb_diff <= next_table_addrb; + content_table_addrb_diff <= content_table_addrb; + empty_table_addrb_diff <= empty_table_addrb; + tail_table_addrb_diff <= tail_table_addrb; + head_table_addrb_diff <= head_table_addrb; + end +end +/*------------------------------------------- Variables Decode : End ------------------------------------------------*/ + +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Peripherals/EgressArbiter.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Peripherals/EgressArbiter.v new file mode 100644 index 0000000000000000000000000000000000000000..1f3d21d4b079f81da9795f456059af3282046747 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Peripherals/EgressArbiter.v @@ -0,0 +1,62 @@ +/*------------------------------------------- Module Description : Begin ---------------------------------------------- +Name: EgressArbiter +Author: YangFan +Function: In NIC/Switch processing pipeline, protocol processing requires frequent appending and removing header. + This module abstracts the append process. +--------------------------------------------- Module Decription : End -----------------------------------------------*/ + +/*------------------------------------------- Timescale Definition : Begin ------------------------------------------*/ +`timescale 1ns / 1ps +/*------------------------------------------- Timescale Definition : End --------------------------------------------*/ + +/*------------------------------------------- Included Files : Begin ------------------------------------------------*/ +`include "protocol_engine_def.vh" +/*------------------------------------------- Included Files : End --------------------------------------------------*/ + +/*------------------------------------------- Local Macros Definition : Begin ---------------------------------------*/ +/*------------------------------------------- Local Macros Definition : End -----------------------------------------*/ + +/*------------------------------------------- Input/Output Definition : Begin ---------------------------------------*/ +module EgressArbiter +( + input wire clk, + input wire rst, + + input wire req_trans_pkt_out_valid, + input wire [`PKT_HEAD_BUS_WIDTH - 1 : 0] req_trans_pkt_out_head, + input wire [`PKT_DATA_BUS_WIDTH - 1 : 0] req_trans_pkt_out_data, + input wire req_trans_pkt_out_start, + input wire req_trans_pkt_out_last, + output wire req_trans_pkt_out_ready, + + input wire resp_trans_pkt_out_valid, + input wire [`PKT_HEAD_BUS_WIDTH - 1 : 0] resp_trans_pkt_out_head, + input wire [`PKT_DATA_BUS_WIDTH - 1 : 0] resp_trans_pkt_out_data, + input wire resp_trans_pkt_out_start, + input wire resp_trans_pkt_out_last, + output wire resp_trans_pkt_out_ready, + + input wire egress_pkt_valid, + input wire [`PKT_HEAD_BUS_WIDTH - 1 : 0] egress_pkt_head, + input wire [`PKT_DATA_BUS_WIDTH - 1 : 0] egress_pkt_data, + input wire egress_pkt_start, + input wire egress_pkt_last, + output wire egress_pkt_ready +); +/*------------------------------------------- Input/Output Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Variables Definition : Begin ------------------------------------*/ +/*------------------------------------------- Local Variables Definition : End --------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : Begin ---------------------------------------*/ +/*------------------------------------------- Submodules Instatiation : End -----------------------------------------*/ + +/*------------------------------------------- State Machine Definition : Begin --------------------------------------*/ + +/*------------------------------------------- State Machine Definition : End ----------------------------------------*/ + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ + +/*------------------------------------------- Variables Decode : End ------------------------------------------------*/ + +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Peripherals/EgressPacketGen.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Peripherals/EgressPacketGen.v new file mode 100644 index 0000000000000000000000000000000000000000..c70e7381c8f4841e583a6011af0fa7d63ee73fc6 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Peripherals/EgressPacketGen.v @@ -0,0 +1,122 @@ +/*------------------------------------------- Module Description : Begin ---------------------------------------------- +Name: EgressPacketGen +Author: YangFan +Function: In NIC/Switch processing pipeline, protocol processing requires frequent appending and removing header. + This module abstracts the append process. +--------------------------------------------- Module Decription : End -----------------------------------------------*/ + +/*------------------------------------------- Timescale Definition : Begin ------------------------------------------*/ +`timescale 1ns / 1ps +/*------------------------------------------- Timescale Definition : End --------------------------------------------*/ + +/*------------------------------------------- Included Files : Begin ------------------------------------------------*/ +`include "protocol_engine_def.vh" +/*------------------------------------------- Included Files : End --------------------------------------------------*/ + +/*------------------------------------------- Local Macros Definition : Begin ---------------------------------------*/ +/*------------------------------------------- Local Macros Definition : End -----------------------------------------*/ + +/*------------------------------------------- Input/Output Definition : Begin ---------------------------------------*/ +module EgressPacketGen +( + input wire clk, + input wire rst, + + input wire req_trans_pkt_out_valid, + input wire [`PKT_HEAD_BUS_WIDTH - 1 : 0] req_trans_pkt_out_head, + input wire [`PKT_DATA_BUS_WIDTH - 1 : 0] req_trans_pkt_out_data, + input wire req_trans_pkt_out_start, + input wire req_trans_pkt_out_last, + output wire req_trans_pkt_out_ready, + + input wire resp_trans_pkt_out_valid, + input wire [`PKT_HEAD_BUS_WIDTH - 1 : 0] resp_trans_pkt_out_head, + input wire [`PKT_DATA_BUS_WIDTH - 1 : 0] resp_trans_pkt_out_data, + input wire resp_trans_pkt_out_start, + input wire resp_trans_pkt_out_last, + output wire resp_trans_pkt_out_ready, + + output wire mac_axis_tx_valid, + output wire [511:0] mac_axis_tx_data, + output wire [63:0] mac_axis_tx_keep, + output wire mac_axis_tx_user, + output wire mac_axis_tx_last, + input wire mac_axis_tx_ready +); +/*------------------------------------------- Input/Output Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Variables Definition : Begin ------------------------------------*/ +wire egress_pkt_valid; +wire [`PKT_HEAD_BUS_WIDTH - 1 : 0] egress_pkt_head; +wire [`PKT_DATA_BUS_WIDTH - 1 : 0] egress_pkt_data; +wire [`PKT_KEEP_BUS_WIDTH - 1 : 0] egress_pkt_keep; +wire egress_pkt_start; +wire egress_pkt_last; +wire egress_pkt_ready; + +/*------------------------------------------- Local Variables Definition : End --------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : Begin ---------------------------------------*/ +EgressArbiter EgressArbiter_Inst( + .clk ( clk ), + .rst ( rst ), + + .req_trans_pkt_out_valid ( req_trans_pkt_out_valid ), + .req_trans_pkt_out_head ( req_trans_pkt_out_head ), + .req_trans_pkt_out_data ( req_trans_pkt_out_data ), + .req_trans_pkt_out_start ( req_trans_pkt_out_start ), + .req_trans_pkt_out_last ( req_trans_pkt_out_last ), + .req_trans_pkt_out_ready ( req_trans_pkt_out_ready ), + + .resp_trans_pkt_out_valid ( resp_trans_pkt_out_valid ), + .resp_trans_pkt_out_head ( resp_trans_pkt_out_head ), + .resp_trans_pkt_out_data ( resp_trans_pkt_out_data ), + .resp_trans_pkt_out_start ( resp_trans_pkt_out_start ), + .resp_trans_pkt_out_last ( resp_trans_pkt_out_last ), + .resp_trans_pkt_out_ready ( resp_trans_pkt_out_ready ), + + .egress_pkt_valid ( egress_pkt_valid ), + .egress_pkt_head ( egress_pkt_head ), + .egress_pkt_data ( egress_pkt_data ), + .egress_pkt_start ( egress_pkt_start ), + .egress_pkt_last ( egress_pkt_last ), + .egress_pkt_ready ( egress_pkt_ready ) +); + +PacketEncap +#( + .HEADER_BUS_WIDTH ( `PKT_HEAD_BUS_WIDTH ), + .PAYLOAD_BUS_WIDTH ( `PKT_DATA_BUS_WIDTH ) +) +PacketEncap_Inst( + .clk ( clk ), + .rst ( rst ), + + .i_packet_in_valid ( egress_pkt_valid ), + .iv_packet_in_head ( egress_pkt_head ), + .iv_packet_in_data ( egress_pkt_data ), + .i_packet_in_start ( egress_pkt_start ), + .i_packet_in_last ( egress_pkt_last ), + .iv_packet_in_keep ( egress_pkt_keep ), + .o_packet_in_ready ( egress_pkt_ready ), + + .o_packet_out_valid ( mac_axis_tx_valid ), + .ov_packet_out_head ( ), + .ov_packet_out_keep ( mac_axis_tx_keep ), + .ov_packet_out_data ( mac_axis_tx_data ), + .o_packet_out_start ( ), + .o_packet_out_last ( mac_axis_tx_last ), + .i_packet_out_ready ( mac_axis_tx_ready ) +); + +/*------------------------------------------- Submodules Instatiation : End -----------------------------------------*/ + +/*------------------------------------------- State Machine Definition : Begin --------------------------------------*/ + +/*------------------------------------------- State Machine Definition : End ----------------------------------------*/ + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ + +/*------------------------------------------- Variables Decode : End ------------------------------------------------*/ + +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Peripherals/EnDecap.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Peripherals/EnDecap.v new file mode 100644 index 0000000000000000000000000000000000000000..2c2a277582dfca7ce7baa4d45f14433d306c79be --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Peripherals/EnDecap.v @@ -0,0 +1,120 @@ +/*------------------------------------------- Module Description : Begin ---------------------------------------------- +Name: EnDecap +Author: YangFan +Function: Used to verify PacketEncap and PacketDecap +--------------------------------------------- Module Decription : End -----------------------------------------------*/ + +/*------------------------------------------- Timescale Definition : Begin ------------------------------------------*/ +`timescale 1ns / 1ps +/*------------------------------------------- Timescale Definition : End --------------------------------------------*/ + +/*------------------------------------------- Included Files : Begin ------------------------------------------------*/ +`include "common_function_def.vh" +/*------------------------------------------- Included Files : End --------------------------------------------------*/ + +/*------------------------------------------- Local Macros Definition : Begin ---------------------------------------*/ +/*------------------------------------------- Local Macros Definition : End -----------------------------------------*/ + +/*------------------------------------------- Input/Output Definition : Begin ---------------------------------------*/ +module EnDecap #( + parameter HEADER_BUS_WIDTH = 512, + parameter PAYLOAD_BUS_WIDTH = 512 +) +( + input wire clk, + input wire rst, + + input wire i_packet_in_valid, + input wire [HEADER_BUS_WIDTH - 1 : 0] iv_packet_in_head, + input wire [PAYLOAD_BUS_WIDTH - 1 : 0] iv_packet_in_data, + input wire i_packet_in_start, + input wire i_packet_in_last, + output wire o_packet_in_ready, + + output wire o_packet_out_valid, + output wire [HEADER_BUS_WIDTH - 1 : 0] ov_packet_out_head, + output wire [PAYLOAD_BUS_WIDTH - 1 : 0] ov_packet_out_data, + output wire o_packet_out_start, + output wire o_packet_out_last, + input wire i_packet_out_ready +); + +wire w_packet_encap_valid; +wire [HEADER_BUS_WIDTH - 1 : 0] wv_packet_encap_head; +wire [PAYLOAD_BUS_WIDTH - 1 : 0] wv_packet_encap_data; +wire w_packet_encap_start; +wire w_packet_encap_last; +wire w_packet_encap_ready; + +wire w_packet_decap_valid; +wire [HEADER_BUS_WIDTH - 1 : 0] wv_packet_decap_head; +wire [PAYLOAD_BUS_WIDTH - 1 : 0] wv_packet_decap_data; +wire w_packet_decap_start; +wire w_packet_decap_last; +wire w_packet_decap_ready; + +PacketEncap PacketEncap_Inst( + .clk(clk), + .rst(rst), + + .i_packet_in_valid(i_packet_in_valid), + .iv_packet_in_head(iv_packet_in_head), + .iv_packet_in_data(iv_packet_in_data), + .i_packet_in_start(i_packet_in_start), + .i_packet_in_last(i_packet_in_last), + .o_packet_in_ready(o_packet_in_ready), + + .o_packet_out_valid(w_packet_encap_valid), + .ov_packet_out_head(wv_packet_encap_head), + .ov_packet_out_data(wv_packet_encap_data), + .o_packet_out_start(w_packet_encap_start), + .o_packet_out_last(w_packet_encap_last), + .i_packet_out_ready(w_packet_encap_ready) +); + +PacketDecap PacketDecap_Inst( + .clk(clk), + .rst(rst), + + .i_packet_in_valid(w_packet_decap_valid), + .iv_packet_in_head(wv_packet_decap_head), + .iv_packet_in_data(wv_packet_decap_data), + .i_packet_in_start(w_packet_decap_start), + .i_packet_in_last(w_packet_decap_last), + .o_packet_in_ready(w_packet_decap_ready), + + .o_packet_out_valid(o_packet_out_valid), + .ov_packet_out_head(ov_packet_out_head), + .ov_packet_out_data(ov_packet_out_data), + .o_packet_out_start(o_packet_out_start), + .o_packet_out_last(o_packet_out_last), + .i_packet_out_ready(i_packet_out_ready) +); + +stream_reg +#( + .TUSER_WIDTH(512), + .TDATA_WIDTH(512) +) +stream_reg_inst( + .clk(clk), + .rst_n(~rst), + + .axis_tvalid(w_packet_encap_valid), + .axis_tlast(w_packet_encap_last), + .axis_tuser(wv_packet_encap_head), + .axis_tdata(wv_packet_encap_data), + .axis_tready(w_packet_encap_ready), + .axis_tstart(w_packet_encap_start), + .axis_tkeep('d0), + + .in_reg_tvalid(w_packet_decap_valid), + .in_reg_tlast(w_packet_decap_last), + .in_reg_tuser(wv_packet_decap_head), + .in_reg_tdata(wv_packet_decap_data), + .in_reg_tkeep(), + .in_reg_tstart(w_packet_decap_start), + .in_reg_tready(w_packet_decap_ready) +); + +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Peripherals/GatherData.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Peripherals/GatherData.v new file mode 100644 index 0000000000000000000000000000000000000000..0fee617ff1dc8e770f64e1b48f741fab018a2c10 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Peripherals/GatherData.v @@ -0,0 +1,645 @@ +/*------------------------------------------- Module Description : Begin ---------------------------------------------- +Name: GatherData +Author: YangFan +Function: Gather data from non-contiguous memory page and merge into continuous network stream. +--------------------------------------------- Module Decription : End -----------------------------------------------*/ + +/*------------------------------------------- Timescale Definition : Begin ------------------------------------------*/ +`timescale 1ns / 1ps +/*------------------------------------------- Timescale Definition : End --------------------------------------------*/ + +/*------------------------------------------- Included Files : Begin ------------------------------------------------*/ +`include "protocol_engine_def.vh" +/*------------------------------------------- Included Files : End --------------------------------------------------*/ + +/*------------------------------------------- Local Macros Definition : Begin ---------------------------------------*/ +/*------------------------------------------- Local Macros Definition : End -----------------------------------------*/ + +/*------------------------------------------- Input/Output Definition : Begin ---------------------------------------*/ +module GatherData +( + input wire clk, + input wire rst, + + input wire gather_req_wr_en, + input wire [`DMA_LENGTH_WIDTH * 2 + `DMA_ADDR_WIDTH - 1 : 0] gather_req_din, + output wire gather_req_prog_full, + + output wire dma_rd_req_valid, + output wire [`DMA_HEAD_WIDTH - 1 : 0] dma_rd_req_head, + output wire [`DMA_DATA_WIDTH - 1 : 0] dma_rd_req_data, + output wire dma_rd_req_last, + input wire dma_rd_req_ready, + + input wire dma_rd_rsp_valid, + input wire [`DMA_HEAD_WIDTH - 1 : 0] dma_rd_rsp_head, + input wire [`DMA_DATA_WIDTH - 1 : 0] dma_rd_rsp_data, + input wire dma_rd_rsp_last, + output wire dma_rd_rsp_ready, + + input wire gather_resp_rd_en, + output wire gather_resp_empty, + output wire [`DMA_DATA_WIDTH - 1 : 0] gather_resp_dout +); +/*------------------------------------------- Input/Output Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Variables Definition : Begin ------------------------------------*/ +wire gather_req_rd_en; +wire [`DMA_LENGTH_WIDTH * 2 + `DMA_ADDR_WIDTH - 1 : 0] gather_req_dout; +wire gather_req_empty; + +wire dma_rd_req_wr_en; +wire [`DMA_LENGTH_WIDTH * 2 + `DMA_ADDR_WIDTH - 1 : 0] dma_rd_req_din; +wire dma_rd_req_prog_full; +wire dma_rd_req_rd_en; +wire [`DMA_LENGTH_WIDTH * 2 + `DMA_ADDR_WIDTH - 1 : 0] dma_rd_req_dout; +wire dma_rd_req_empty; + +reg [31:0] qv_total_length_left; +reg [31:0] qv_page_length_left; +reg [31:0] qv_unwritten_len; +reg [511:0] qv_unwritten_data; +wire w_last_page_of_req; + +reg gather_resp_wr_en; +reg [`DMA_DATA_WIDTH - 1 : 0] gather_resp_din; +wire gather_resp_prog_full; +/*------------------------------------------- Local Variables Definition : End --------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : Begin ---------------------------------------*/ +SyncFIFO_Template #( + .FIFO_TYPE (0), + .FIFO_WIDTH (`DMA_LENGTH_WIDTH * 2 + `DMA_ADDR_WIDTH), + .FIFO_DEPTH (64) +) +gather_req_fifo +( + .clk(clk), + .rst(rst), + + .wr_en(gather_req_wr_en), + .din(gather_req_din), + .prog_full(gather_req_prog_full), + .rd_en(gather_req_rd_en), + .dout(gather_req_dout), + .empty(gather_req_empty), + .data_count() +); + +SyncFIFO_Template #( + .FIFO_TYPE (0), + .FIFO_WIDTH (`DMA_LENGTH_WIDTH * 2 + `DMA_ADDR_WIDTH), + .FIFO_DEPTH (64) +) +dma_rd_req_fifo +( + .clk(clk), + .rst(rst), + + .wr_en(dma_rd_req_wr_en), + .din(dma_rd_req_din), + .prog_full(dma_rd_req_prog_full), + .rd_en(dma_rd_req_rd_en), + .dout(dma_rd_req_dout), + .empty(dma_rd_req_empty), + .data_count() +); + +SyncFIFO_Template #( + .FIFO_TYPE (0), + .FIFO_WIDTH (`DMA_DATA_WIDTH), + .FIFO_DEPTH (64) +) +gather_resp_fifo +( + .clk(clk), + .rst(rst), + + .wr_en(gather_resp_wr_en), + .din(gather_resp_din), + .prog_full(gather_resp_prog_full), + .rd_en(gather_resp_rd_en), + .dout(gather_resp_dout), + .empty(gather_resp_empty), + .data_count() +); +/*------------------------------------------- Submodules Instatiation : End -----------------------------------------*/ + + +/*------------------------------------------- State Machine Definition : Begin --------------------------------------*/ + +/*DMA Read Response State Machine */ +parameter RESP_IDLE_s = 2'b01, + RESP_DOWNLOAD_s = 2'b10; + +reg [1:0] resp_cur_state; +reg [1:0] resp_next_state; + +always @(posedge clk or posedge rst) begin + if(rst) begin + resp_cur_state <= RESP_IDLE_s; + end + else begin + resp_cur_state <= resp_next_state; + end +end + +always @(*) begin + case(resp_cur_state) + RESP_IDLE_s: if(!dma_rd_req_empty) begin + resp_next_state = RESP_DOWNLOAD_s; + end + else begin + resp_next_state = RESP_IDLE_s; + end + RESP_DOWNLOAD_s: if(qv_page_length_left + qv_unwritten_len > 64) begin + resp_next_state = RESP_DOWNLOAD_s; + end + else begin // <=64, judge whether need valid signal + if(qv_page_length_left > 0 && dma_rd_rsp_valid && !gather_resp_prog_full) begin //Need valid indicator + resp_next_state = RESP_IDLE_s; + end + else if(qv_page_length_left == 0 && !gather_resp_prog_full) begin + resp_next_state = RESP_IDLE_s; + end + else begin + resp_next_state = RESP_DOWNLOAD_s; + end + end + default: resp_next_state = RESP_IDLE_s; + endcase +end +/*------------------------------------------- State Machine Definition : End ----------------------------------------*/ + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ + +//-- dma_rd_req_wr_en -- +assign dma_rd_req_wr_en = gather_req_rd_en; + +//-- dma_rd_req_din -- +assign dma_rd_req_din = gather_req_rd_en ? gather_req_dout : 0; + +//-- dma_rd_req_valid -- +assign dma_rd_req_valid = !gather_req_empty; +//-- dma_rd_req_head -- +assign dma_rd_req_head = {'d0, gather_req_dout[63:0], gather_req_dout[95:64]}; //64-bit Addr, 32-bit Size +//-- dma_rd_req_last -- +assign dma_rd_req_last = dma_rd_req_valid; +//-- dma_rd_req_data -- +assign dma_rd_req_data = 'd0; + +//-- gather_req_rd_en -- +assign gather_req_rd_en = !gather_req_empty && dma_rd_req_ready && !dma_rd_req_prog_full; + +//-- w_last_page_of_req -- +assign w_last_page_of_req = (qv_total_length_left == qv_page_length_left); + +//-- dma_rd_req_rd_en -- +assign dma_rd_req_rd_en = (resp_cur_state == RESP_DOWNLOAD_s) && (qv_page_length_left + qv_unwritten_len <= 64) && !gather_resp_prog_full && + ((qv_page_length_left > 0 && dma_rd_rsp_valid) || (qv_page_length_left == 0)); + +//-- dma_rd_rsp_ready -- +assign dma_rd_rsp_ready = (resp_cur_state == RESP_DOWNLOAD_s) && !gather_resp_prog_full && (qv_page_length_left > 0); + +//-- qv_page_length_left -- +always @(posedge clk or posedge rst) begin + if(rst) begin + qv_page_length_left <= 'd0; + end + else if(resp_cur_state == RESP_IDLE_s && !dma_rd_req_empty) begin + qv_page_length_left <= dma_rd_req_dout[95:64]; + end + else if(resp_cur_state == RESP_DOWNLOAD_s) begin + if(qv_page_length_left > 0 && dma_rd_rsp_valid && !gather_resp_prog_full) begin + if(qv_page_length_left > 64) begin + qv_page_length_left <= qv_page_length_left - 64; + end + else begin + qv_page_length_left <= 'd0; + end + end + else begin + qv_page_length_left <= qv_page_length_left; + end + end + else begin + qv_page_length_left <= qv_page_length_left; + end +end + +//-- qv_total_length_left -- +always @(posedge clk or posedge rst) begin + if(rst) begin + qv_total_length_left <= 'd0; + end + else if(resp_cur_state == RESP_IDLE_s && !dma_rd_req_empty) begin + if(qv_total_length_left == 0) begin + qv_total_length_left <= dma_rd_req_dout[127:96]; + end + else begin + qv_total_length_left <= qv_total_length_left; + end + end + else if(resp_cur_state == RESP_DOWNLOAD_s) begin + if(qv_page_length_left > 0 && dma_rd_rsp_valid && !gather_resp_prog_full) begin + if(qv_page_length_left > 64) begin + qv_total_length_left <= qv_total_length_left - 64; + end + else begin + qv_total_length_left <= qv_total_length_left - qv_page_length_left; + end + end + else begin + qv_total_length_left <= qv_total_length_left; + end + end + else begin + qv_total_length_left <= qv_total_length_left; + end +end + +//-- qv_unwritten_len -- +always @(posedge clk or posedge rst) begin + if(rst) begin + qv_unwritten_len <= 'd0; + end + else if(resp_cur_state == RESP_IDLE_s) begin + qv_unwritten_len <= qv_unwritten_len; + end + else if(resp_cur_state == RESP_DOWNLOAD_s) begin //qv_unwritten_len need to consider wthether is the last mtt + if(qv_page_length_left > 0 && dma_rd_rsp_valid && !gather_resp_prog_full) begin + if(qv_page_length_left >= 64) begin + qv_unwritten_len <= qv_unwritten_len; + end + else if(qv_page_length_left + qv_unwritten_len >= 64)begin + qv_unwritten_len <= qv_page_length_left + qv_unwritten_len - 64; + end + else begin + qv_unwritten_len <= w_last_page_of_req ? 'd0 : (qv_page_length_left + qv_unwritten_len); + end + end + else if(qv_page_length_left == 0 && !gather_resp_prog_full) begin + qv_unwritten_len <= w_last_page_of_req ? 'd0 : qv_unwritten_len; + end + end + else begin + qv_unwritten_len <= qv_unwritten_len; + end +end + +//-- qv_unwritten_data -- +always @(posedge clk or posedge rst) begin + if(rst) begin + qv_unwritten_data <= 'd0; + end + else if(resp_cur_state == RESP_DOWNLOAD_s) begin + if(qv_page_length_left > 0 && dma_rd_rsp_valid && !gather_resp_prog_full) begin + if((qv_page_length_left >= 64) || (qv_page_length_left + qv_unwritten_len >= 64)) begin + case(qv_unwritten_len) + 0 : qv_unwritten_data <= 'd0; + 1 : qv_unwritten_data <= {{((64 - 1 ) * 8){1'b0}}, dma_rd_rsp_data[511 : (64 - 1 ) * 8]}; + 2 : qv_unwritten_data <= {{((64 - 2 ) * 8){1'b0}}, dma_rd_rsp_data[511 : (64 - 2 ) * 8]}; + 3 : qv_unwritten_data <= {{((64 - 3 ) * 8){1'b0}}, dma_rd_rsp_data[511 : (64 - 3 ) * 8]}; + 4 : qv_unwritten_data <= {{((64 - 4 ) * 8){1'b0}}, dma_rd_rsp_data[511 : (64 - 4 ) * 8]}; + 5 : qv_unwritten_data <= {{((64 - 5 ) * 8){1'b0}}, dma_rd_rsp_data[511 : (64 - 5 ) * 8]}; + 6 : qv_unwritten_data <= {{((64 - 6 ) * 8){1'b0}}, dma_rd_rsp_data[511 : (64 - 6 ) * 8]}; + 7 : qv_unwritten_data <= {{((64 - 7 ) * 8){1'b0}}, dma_rd_rsp_data[511 : (64 - 7 ) * 8]}; + 8 : qv_unwritten_data <= {{((64 - 8 ) * 8){1'b0}}, dma_rd_rsp_data[511 : (64 - 8 ) * 8]}; + 9 : qv_unwritten_data <= {{((64 - 9 ) * 8){1'b0}}, dma_rd_rsp_data[511 : (64 - 9 ) * 8]}; + 10 : qv_unwritten_data <= {{((64 - 10) * 8){1'b0}}, dma_rd_rsp_data[511 : (64 - 10) * 8]}; + 11 : qv_unwritten_data <= {{((64 - 11) * 8){1'b0}}, dma_rd_rsp_data[511 : (64 - 11) * 8]}; + 12 : qv_unwritten_data <= {{((64 - 12) * 8){1'b0}}, dma_rd_rsp_data[511 : (64 - 12) * 8]}; + 13 : qv_unwritten_data <= {{((64 - 13) * 8){1'b0}}, dma_rd_rsp_data[511 : (64 - 13) * 8]}; + 14 : qv_unwritten_data <= {{((64 - 14) * 8){1'b0}}, dma_rd_rsp_data[511 : (64 - 14) * 8]}; + 15 : qv_unwritten_data <= {{((64 - 15) * 8){1'b0}}, dma_rd_rsp_data[511 : (64 - 15) * 8]}; + 16 : qv_unwritten_data <= {{((64 - 16) * 8){1'b0}}, dma_rd_rsp_data[511 : (64 - 16) * 8]}; + 17 : qv_unwritten_data <= {{((64 - 17) * 8){1'b0}}, dma_rd_rsp_data[511 : (64 - 17) * 8]}; + 18 : qv_unwritten_data <= {{((64 - 18) * 8){1'b0}}, dma_rd_rsp_data[511 : (64 - 18) * 8]}; + 19 : qv_unwritten_data <= {{((64 - 19) * 8){1'b0}}, dma_rd_rsp_data[511 : (64 - 19) * 8]}; + 20 : qv_unwritten_data <= {{((64 - 20) * 8){1'b0}}, dma_rd_rsp_data[511 : (64 - 20) * 8]}; + 21 : qv_unwritten_data <= {{((64 - 21) * 8){1'b0}}, dma_rd_rsp_data[511 : (64 - 21) * 8]}; + 22 : qv_unwritten_data <= {{((64 - 22) * 8){1'b0}}, dma_rd_rsp_data[511 : (64 - 22) * 8]}; + 23 : qv_unwritten_data <= {{((64 - 23) * 8){1'b0}}, dma_rd_rsp_data[511 : (64 - 23) * 8]}; + 24 : qv_unwritten_data <= {{((64 - 24) * 8){1'b0}}, dma_rd_rsp_data[511 : (64 - 24) * 8]}; + 25 : qv_unwritten_data <= {{((64 - 25) * 8){1'b0}}, dma_rd_rsp_data[511 : (64 - 25) * 8]}; + 26 : qv_unwritten_data <= {{((64 - 26) * 8){1'b0}}, dma_rd_rsp_data[511 : (64 - 26) * 8]}; + 27 : qv_unwritten_data <= {{((64 - 27) * 8){1'b0}}, dma_rd_rsp_data[511 : (64 - 27) * 8]}; + 28 : qv_unwritten_data <= {{((64 - 28) * 8){1'b0}}, dma_rd_rsp_data[511 : (64 - 28) * 8]}; + 29 : qv_unwritten_data <= {{((64 - 29) * 8){1'b0}}, dma_rd_rsp_data[511 : (64 - 29) * 8]}; + 30 : qv_unwritten_data <= {{((64 - 30) * 8){1'b0}}, dma_rd_rsp_data[511 : (64 - 30) * 8]}; + 31 : qv_unwritten_data <= {{((64 - 31) * 8){1'b0}}, dma_rd_rsp_data[511 : (64 - 31) * 8]}; + 32 : qv_unwritten_data <= {{((64 - 32) * 8){1'b0}}, dma_rd_rsp_data[511 : (64 - 32) * 8]}; + 33 : qv_unwritten_data <= {{((64 - 33) * 8){1'b0}}, dma_rd_rsp_data[511 : (64 - 33) * 8]}; + 34 : qv_unwritten_data <= {{((64 - 34) * 8){1'b0}}, dma_rd_rsp_data[511 : (64 - 34) * 8]}; + 35 : qv_unwritten_data <= {{((64 - 35) * 8){1'b0}}, dma_rd_rsp_data[511 : (64 - 35) * 8]}; + 36 : qv_unwritten_data <= {{((64 - 36) * 8){1'b0}}, dma_rd_rsp_data[511 : (64 - 36) * 8]}; + 37 : qv_unwritten_data <= {{((64 - 37) * 8){1'b0}}, dma_rd_rsp_data[511 : (64 - 37) * 8]}; + 38 : qv_unwritten_data <= {{((64 - 38) * 8){1'b0}}, dma_rd_rsp_data[511 : (64 - 38) * 8]}; + 39 : qv_unwritten_data <= {{((64 - 39) * 8){1'b0}}, dma_rd_rsp_data[511 : (64 - 39) * 8]}; + 40 : qv_unwritten_data <= {{((64 - 40) * 8){1'b0}}, dma_rd_rsp_data[511 : (64 - 40) * 8]}; + 41 : qv_unwritten_data <= {{((64 - 41) * 8){1'b0}}, dma_rd_rsp_data[511 : (64 - 41) * 8]}; + 42 : qv_unwritten_data <= {{((64 - 42) * 8){1'b0}}, dma_rd_rsp_data[511 : (64 - 42) * 8]}; + 43 : qv_unwritten_data <= {{((64 - 43) * 8){1'b0}}, dma_rd_rsp_data[511 : (64 - 43) * 8]}; + 44 : qv_unwritten_data <= {{((64 - 44) * 8){1'b0}}, dma_rd_rsp_data[511 : (64 - 44) * 8]}; + 45 : qv_unwritten_data <= {{((64 - 45) * 8){1'b0}}, dma_rd_rsp_data[511 : (64 - 45) * 8]}; + 46 : qv_unwritten_data <= {{((64 - 46) * 8){1'b0}}, dma_rd_rsp_data[511 : (64 - 46) * 8]}; + 47 : qv_unwritten_data <= {{((64 - 47) * 8){1'b0}}, dma_rd_rsp_data[511 : (64 - 47) * 8]}; + 48 : qv_unwritten_data <= {{((64 - 48) * 8){1'b0}}, dma_rd_rsp_data[511 : (64 - 48) * 8]}; + 49 : qv_unwritten_data <= {{((64 - 49) * 8){1'b0}}, dma_rd_rsp_data[511 : (64 - 49) * 8]}; + 50 : qv_unwritten_data <= {{((64 - 50) * 8){1'b0}}, dma_rd_rsp_data[511 : (64 - 50) * 8]}; + 51 : qv_unwritten_data <= {{((64 - 51) * 8){1'b0}}, dma_rd_rsp_data[511 : (64 - 51) * 8]}; + 52 : qv_unwritten_data <= {{((64 - 52) * 8){1'b0}}, dma_rd_rsp_data[511 : (64 - 52) * 8]}; + 53 : qv_unwritten_data <= {{((64 - 53) * 8){1'b0}}, dma_rd_rsp_data[511 : (64 - 53) * 8]}; + 54 : qv_unwritten_data <= {{((64 - 54) * 8){1'b0}}, dma_rd_rsp_data[511 : (64 - 54) * 8]}; + 55 : qv_unwritten_data <= {{((64 - 55) * 8){1'b0}}, dma_rd_rsp_data[511 : (64 - 55) * 8]}; + 56 : qv_unwritten_data <= {{((64 - 56) * 8){1'b0}}, dma_rd_rsp_data[511 : (64 - 56) * 8]}; + 57 : qv_unwritten_data <= {{((64 - 57) * 8){1'b0}}, dma_rd_rsp_data[511 : (64 - 57) * 8]}; + 58 : qv_unwritten_data <= {{((64 - 58) * 8){1'b0}}, dma_rd_rsp_data[511 : (64 - 58) * 8]}; + 59 : qv_unwritten_data <= {{((64 - 59) * 8){1'b0}}, dma_rd_rsp_data[511 : (64 - 59) * 8]}; + 60 : qv_unwritten_data <= {{((64 - 60) * 8){1'b0}}, dma_rd_rsp_data[511 : (64 - 60) * 8]}; + 61 : qv_unwritten_data <= {{((64 - 61) * 8){1'b0}}, dma_rd_rsp_data[511 : (64 - 61) * 8]}; + 62 : qv_unwritten_data <= {{((64 - 62) * 8){1'b0}}, dma_rd_rsp_data[511 : (64 - 62) * 8]}; + 63 : qv_unwritten_data <= {{((64 - 63) * 8){1'b0}}, dma_rd_rsp_data[511 : (64 - 63) * 8]}; + default: qv_unwritten_data <= qv_unwritten_data; + endcase + end + else if(qv_page_length_left + qv_unwritten_len < 64) begin + if(w_last_page_of_req) begin + qv_unwritten_data <= 'd0; + end + else begin //piece together and wait for next ntt data + case(qv_unwritten_len) + 0 : qv_unwritten_data <= dma_rd_rsp_data; + 1 : qv_unwritten_data <= {dma_rd_rsp_data[(64 - 1 ) * 8 - 1 : 0], qv_unwritten_data[1 * 8 - 1 : 0]}; + 2 : qv_unwritten_data <= {dma_rd_rsp_data[(64 - 2 ) * 8 - 1 : 0], qv_unwritten_data[2 * 8 - 1 : 0]}; + 3 : qv_unwritten_data <= {dma_rd_rsp_data[(64 - 3 ) * 8 - 1 : 0], qv_unwritten_data[3 * 8 - 1 : 0]}; + 4 : qv_unwritten_data <= {dma_rd_rsp_data[(64 - 4 ) * 8 - 1 : 0], qv_unwritten_data[4 * 8 - 1 : 0]}; + 5 : qv_unwritten_data <= {dma_rd_rsp_data[(64 - 5 ) * 8 - 1 : 0], qv_unwritten_data[5 * 8 - 1 : 0]}; + 6 : qv_unwritten_data <= {dma_rd_rsp_data[(64 - 6 ) * 8 - 1 : 0], qv_unwritten_data[6 * 8 - 1 : 0]}; + 7 : qv_unwritten_data <= {dma_rd_rsp_data[(64 - 7 ) * 8 - 1 : 0], qv_unwritten_data[7 * 8 - 1 : 0]}; + 8 : qv_unwritten_data <= {dma_rd_rsp_data[(64 - 8 ) * 8 - 1 : 0], qv_unwritten_data[8 * 8 - 1 : 0]}; + 9 : qv_unwritten_data <= {dma_rd_rsp_data[(64 - 9 ) * 8 - 1 : 0], qv_unwritten_data[9 * 8 - 1 : 0]}; + 10 : qv_unwritten_data <= {dma_rd_rsp_data[(64 - 10) * 8 - 1 : 0], qv_unwritten_data[10 * 8 - 1 : 0]}; + 11 : qv_unwritten_data <= {dma_rd_rsp_data[(64 - 11) * 8 - 1 : 0], qv_unwritten_data[11 * 8 - 1 : 0]}; + 12 : qv_unwritten_data <= {dma_rd_rsp_data[(64 - 12) * 8 - 1 : 0], qv_unwritten_data[12 * 8 - 1 : 0]}; + 13 : qv_unwritten_data <= {dma_rd_rsp_data[(64 - 13) * 8 - 1 : 0], qv_unwritten_data[13 * 8 - 1 : 0]}; + 14 : qv_unwritten_data <= {dma_rd_rsp_data[(64 - 14) * 8 - 1 : 0], qv_unwritten_data[14 * 8 - 1 : 0]}; + 15 : qv_unwritten_data <= {dma_rd_rsp_data[(64 - 15) * 8 - 1 : 0], qv_unwritten_data[15 * 8 - 1 : 0]}; + 16 : qv_unwritten_data <= {dma_rd_rsp_data[(64 - 16) * 8 - 1 : 0], qv_unwritten_data[16 * 8 - 1 : 0]}; + 17 : qv_unwritten_data <= {dma_rd_rsp_data[(64 - 17) * 8 - 1 : 0], qv_unwritten_data[17 * 8 - 1 : 0]}; + 18 : qv_unwritten_data <= {dma_rd_rsp_data[(64 - 18) * 8 - 1 : 0], qv_unwritten_data[18 * 8 - 1 : 0]}; + 19 : qv_unwritten_data <= {dma_rd_rsp_data[(64 - 19) * 8 - 1 : 0], qv_unwritten_data[19 * 8 - 1 : 0]}; + 20 : qv_unwritten_data <= {dma_rd_rsp_data[(64 - 20) * 8 - 1 : 0], qv_unwritten_data[20 * 8 - 1 : 0]}; + 21 : qv_unwritten_data <= {dma_rd_rsp_data[(64 - 21) * 8 - 1 : 0], qv_unwritten_data[21 * 8 - 1 : 0]}; + 22 : qv_unwritten_data <= {dma_rd_rsp_data[(64 - 22) * 8 - 1 : 0], qv_unwritten_data[22 * 8 - 1 : 0]}; + 23 : qv_unwritten_data <= {dma_rd_rsp_data[(64 - 23) * 8 - 1 : 0], qv_unwritten_data[23 * 8 - 1 : 0]}; + 24 : qv_unwritten_data <= {dma_rd_rsp_data[(64 - 24) * 8 - 1 : 0], qv_unwritten_data[24 * 8 - 1 : 0]}; + 25 : qv_unwritten_data <= {dma_rd_rsp_data[(64 - 25) * 8 - 1 : 0], qv_unwritten_data[25 * 8 - 1 : 0]}; + 26 : qv_unwritten_data <= {dma_rd_rsp_data[(64 - 26) * 8 - 1 : 0], qv_unwritten_data[26 * 8 - 1 : 0]}; + 27 : qv_unwritten_data <= {dma_rd_rsp_data[(64 - 27) * 8 - 1 : 0], qv_unwritten_data[27 * 8 - 1 : 0]}; + 28 : qv_unwritten_data <= {dma_rd_rsp_data[(64 - 28) * 8 - 1 : 0], qv_unwritten_data[28 * 8 - 1 : 0]}; + 29 : qv_unwritten_data <= {dma_rd_rsp_data[(64 - 29) * 8 - 1 : 0], qv_unwritten_data[29 * 8 - 1 : 0]}; + 30 : qv_unwritten_data <= {dma_rd_rsp_data[(64 - 30) * 8 - 1 : 0], qv_unwritten_data[30 * 8 - 1 : 0]}; + 31 : qv_unwritten_data <= {dma_rd_rsp_data[(64 - 31) * 8 - 1 : 0], qv_unwritten_data[31 * 8 - 1 : 0]}; + 32 : qv_unwritten_data <= {dma_rd_rsp_data[(64 - 32) * 8 - 1 : 0], qv_unwritten_data[32 * 8 - 1 : 0]}; + 33 : qv_unwritten_data <= {dma_rd_rsp_data[(64 - 33) * 8 - 1 : 0], qv_unwritten_data[33 * 8 - 1 : 0]}; + 34 : qv_unwritten_data <= {dma_rd_rsp_data[(64 - 34) * 8 - 1 : 0], qv_unwritten_data[34 * 8 - 1 : 0]}; + 35 : qv_unwritten_data <= {dma_rd_rsp_data[(64 - 35) * 8 - 1 : 0], qv_unwritten_data[35 * 8 - 1 : 0]}; + 36 : qv_unwritten_data <= {dma_rd_rsp_data[(64 - 36) * 8 - 1 : 0], qv_unwritten_data[36 * 8 - 1 : 0]}; + 37 : qv_unwritten_data <= {dma_rd_rsp_data[(64 - 37) * 8 - 1 : 0], qv_unwritten_data[37 * 8 - 1 : 0]}; + 38 : qv_unwritten_data <= {dma_rd_rsp_data[(64 - 38) * 8 - 1 : 0], qv_unwritten_data[38 * 8 - 1 : 0]}; + 39 : qv_unwritten_data <= {dma_rd_rsp_data[(64 - 39) * 8 - 1 : 0], qv_unwritten_data[39 * 8 - 1 : 0]}; + 40 : qv_unwritten_data <= {dma_rd_rsp_data[(64 - 40) * 8 - 1 : 0], qv_unwritten_data[40 * 8 - 1 : 0]}; + 41 : qv_unwritten_data <= {dma_rd_rsp_data[(64 - 41) * 8 - 1 : 0], qv_unwritten_data[41 * 8 - 1 : 0]}; + 42 : qv_unwritten_data <= {dma_rd_rsp_data[(64 - 42) * 8 - 1 : 0], qv_unwritten_data[42 * 8 - 1 : 0]}; + 43 : qv_unwritten_data <= {dma_rd_rsp_data[(64 - 43) * 8 - 1 : 0], qv_unwritten_data[43 * 8 - 1 : 0]}; + 44 : qv_unwritten_data <= {dma_rd_rsp_data[(64 - 44) * 8 - 1 : 0], qv_unwritten_data[44 * 8 - 1 : 0]}; + 45 : qv_unwritten_data <= {dma_rd_rsp_data[(64 - 45) * 8 - 1 : 0], qv_unwritten_data[45 * 8 - 1 : 0]}; + 46 : qv_unwritten_data <= {dma_rd_rsp_data[(64 - 46) * 8 - 1 : 0], qv_unwritten_data[46 * 8 - 1 : 0]}; + 47 : qv_unwritten_data <= {dma_rd_rsp_data[(64 - 47) * 8 - 1 : 0], qv_unwritten_data[47 * 8 - 1 : 0]}; + 48 : qv_unwritten_data <= {dma_rd_rsp_data[(64 - 48) * 8 - 1 : 0], qv_unwritten_data[48 * 8 - 1 : 0]}; + 49 : qv_unwritten_data <= {dma_rd_rsp_data[(64 - 49) * 8 - 1 : 0], qv_unwritten_data[49 * 8 - 1 : 0]}; + 50 : qv_unwritten_data <= {dma_rd_rsp_data[(64 - 50) * 8 - 1 : 0], qv_unwritten_data[50 * 8 - 1 : 0]}; + 51 : qv_unwritten_data <= {dma_rd_rsp_data[(64 - 51) * 8 - 1 : 0], qv_unwritten_data[51 * 8 - 1 : 0]}; + 52 : qv_unwritten_data <= {dma_rd_rsp_data[(64 - 52) * 8 - 1 : 0], qv_unwritten_data[52 * 8 - 1 : 0]}; + 53 : qv_unwritten_data <= {dma_rd_rsp_data[(64 - 53) * 8 - 1 : 0], qv_unwritten_data[53 * 8 - 1 : 0]}; + 54 : qv_unwritten_data <= {dma_rd_rsp_data[(64 - 54) * 8 - 1 : 0], qv_unwritten_data[54 * 8 - 1 : 0]}; + 55 : qv_unwritten_data <= {dma_rd_rsp_data[(64 - 55) * 8 - 1 : 0], qv_unwritten_data[55 * 8 - 1 : 0]}; + 56 : qv_unwritten_data <= {dma_rd_rsp_data[(64 - 56) * 8 - 1 : 0], qv_unwritten_data[56 * 8 - 1 : 0]}; + 57 : qv_unwritten_data <= {dma_rd_rsp_data[(64 - 57) * 8 - 1 : 0], qv_unwritten_data[57 * 8 - 1 : 0]}; + 58 : qv_unwritten_data <= {dma_rd_rsp_data[(64 - 58) * 8 - 1 : 0], qv_unwritten_data[58 * 8 - 1 : 0]}; + 59 : qv_unwritten_data <= {dma_rd_rsp_data[(64 - 59) * 8 - 1 : 0], qv_unwritten_data[59 * 8 - 1 : 0]}; + 60 : qv_unwritten_data <= {dma_rd_rsp_data[(64 - 60) * 8 - 1 : 0], qv_unwritten_data[60 * 8 - 1 : 0]}; + 61 : qv_unwritten_data <= {dma_rd_rsp_data[(64 - 61) * 8 - 1 : 0], qv_unwritten_data[61 * 8 - 1 : 0]}; + 62 : qv_unwritten_data <= {dma_rd_rsp_data[(64 - 62) * 8 - 1 : 0], qv_unwritten_data[62 * 8 - 1 : 0]}; + 63 : qv_unwritten_data <= {dma_rd_rsp_data[(64 - 63) * 8 - 1 : 0], qv_unwritten_data[63 * 8 - 1 : 0]}; + default: qv_unwritten_data <= qv_unwritten_data; + endcase + end + end + else begin + qv_unwritten_data <= qv_unwritten_data; + end + end + else if(qv_page_length_left == 0 && !gather_resp_prog_full) begin + qv_unwritten_data <= w_last_page_of_req ? 'd0 : qv_unwritten_data; + end + else begin + qv_unwritten_data <= qv_unwritten_data; + end + end + else begin + qv_unwritten_data <= qv_unwritten_data; + end +end + +//-- gather_resp_wr_en -- +always @(posedge clk or posedge rst) begin + if(rst) begin + gather_resp_wr_en <= 'd0; + end + else if(resp_cur_state == RESP_DOWNLOAD_s) begin + if(qv_page_length_left > 0 && dma_rd_rsp_valid && !gather_resp_prog_full) begin + if((qv_page_length_left >= 64) || (qv_page_length_left + qv_unwritten_len >= 64)) begin + gather_resp_wr_en <= 'd1; + end + else if(qv_page_length_left + qv_unwritten_len < 64) begin + gather_resp_wr_en <= w_last_page_of_req ? 'd1 : 'd0; + end + else begin + gather_resp_wr_en <= 'd0; + end + end + else if(qv_page_length_left == 0 && !gather_resp_prog_full) begin + gather_resp_wr_en <= w_last_page_of_req ? 'd1 : 'd0; + end + else begin + gather_resp_wr_en <= 'd0; + end + end + else begin + gather_resp_wr_en <= 'd0; + end +end + +//-- gather_resp_din -- +always @(posedge clk or posedge rst) begin + if(rst) begin + gather_resp_din <= 'd0; + end + else if(resp_cur_state == RESP_DOWNLOAD_s) begin + if(qv_page_length_left > 0 && dma_rd_rsp_valid && !gather_resp_prog_full) begin + if((qv_page_length_left >= 64) || (qv_page_length_left + qv_unwritten_len >= 64)) begin + case(qv_unwritten_len) + 0 : gather_resp_din <= dma_rd_rsp_data; + 1 : gather_resp_din <= {dma_rd_rsp_data[(64 - 1 ) * 8 - 1 : 0], qv_unwritten_data[1 * 8 - 1 : 0]}; + 2 : gather_resp_din <= {dma_rd_rsp_data[(64 - 2 ) * 8 - 1 : 0], qv_unwritten_data[2 * 8 - 1 : 0]}; + 3 : gather_resp_din <= {dma_rd_rsp_data[(64 - 3 ) * 8 - 1 : 0], qv_unwritten_data[3 * 8 - 1 : 0]}; + 4 : gather_resp_din <= {dma_rd_rsp_data[(64 - 4 ) * 8 - 1 : 0], qv_unwritten_data[4 * 8 - 1 : 0]}; + 5 : gather_resp_din <= {dma_rd_rsp_data[(64 - 5 ) * 8 - 1 : 0], qv_unwritten_data[5 * 8 - 1 : 0]}; + 6 : gather_resp_din <= {dma_rd_rsp_data[(64 - 6 ) * 8 - 1 : 0], qv_unwritten_data[6 * 8 - 1 : 0]}; + 7 : gather_resp_din <= {dma_rd_rsp_data[(64 - 7 ) * 8 - 1 : 0], qv_unwritten_data[7 * 8 - 1 : 0]}; + 8 : gather_resp_din <= {dma_rd_rsp_data[(64 - 8 ) * 8 - 1 : 0], qv_unwritten_data[8 * 8 - 1 : 0]}; + 9 : gather_resp_din <= {dma_rd_rsp_data[(64 - 9 ) * 8 - 1 : 0], qv_unwritten_data[9 * 8 - 1 : 0]}; + 10 : gather_resp_din <= {dma_rd_rsp_data[(64 - 10) * 8 - 1 : 0], qv_unwritten_data[10 * 8 - 1 : 0]}; + 11 : gather_resp_din <= {dma_rd_rsp_data[(64 - 11) * 8 - 1 : 0], qv_unwritten_data[11 * 8 - 1 : 0]}; + 12 : gather_resp_din <= {dma_rd_rsp_data[(64 - 12) * 8 - 1 : 0], qv_unwritten_data[12 * 8 - 1 : 0]}; + 13 : gather_resp_din <= {dma_rd_rsp_data[(64 - 13) * 8 - 1 : 0], qv_unwritten_data[13 * 8 - 1 : 0]}; + 14 : gather_resp_din <= {dma_rd_rsp_data[(64 - 14) * 8 - 1 : 0], qv_unwritten_data[14 * 8 - 1 : 0]}; + 15 : gather_resp_din <= {dma_rd_rsp_data[(64 - 15) * 8 - 1 : 0], qv_unwritten_data[15 * 8 - 1 : 0]}; + 16 : gather_resp_din <= {dma_rd_rsp_data[(64 - 16) * 8 - 1 : 0], qv_unwritten_data[16 * 8 - 1 : 0]}; + 17 : gather_resp_din <= {dma_rd_rsp_data[(64 - 17) * 8 - 1 : 0], qv_unwritten_data[17 * 8 - 1 : 0]}; + 18 : gather_resp_din <= {dma_rd_rsp_data[(64 - 18) * 8 - 1 : 0], qv_unwritten_data[18 * 8 - 1 : 0]}; + 19 : gather_resp_din <= {dma_rd_rsp_data[(64 - 19) * 8 - 1 : 0], qv_unwritten_data[19 * 8 - 1 : 0]}; + 20 : gather_resp_din <= {dma_rd_rsp_data[(64 - 20) * 8 - 1 : 0], qv_unwritten_data[20 * 8 - 1 : 0]}; + 21 : gather_resp_din <= {dma_rd_rsp_data[(64 - 21) * 8 - 1 : 0], qv_unwritten_data[21 * 8 - 1 : 0]}; + 22 : gather_resp_din <= {dma_rd_rsp_data[(64 - 22) * 8 - 1 : 0], qv_unwritten_data[22 * 8 - 1 : 0]}; + 23 : gather_resp_din <= {dma_rd_rsp_data[(64 - 23) * 8 - 1 : 0], qv_unwritten_data[23 * 8 - 1 : 0]}; + 24 : gather_resp_din <= {dma_rd_rsp_data[(64 - 24) * 8 - 1 : 0], qv_unwritten_data[24 * 8 - 1 : 0]}; + 25 : gather_resp_din <= {dma_rd_rsp_data[(64 - 25) * 8 - 1 : 0], qv_unwritten_data[25 * 8 - 1 : 0]}; + 26 : gather_resp_din <= {dma_rd_rsp_data[(64 - 26) * 8 - 1 : 0], qv_unwritten_data[26 * 8 - 1 : 0]}; + 27 : gather_resp_din <= {dma_rd_rsp_data[(64 - 27) * 8 - 1 : 0], qv_unwritten_data[27 * 8 - 1 : 0]}; + 28 : gather_resp_din <= {dma_rd_rsp_data[(64 - 28) * 8 - 1 : 0], qv_unwritten_data[28 * 8 - 1 : 0]}; + 29 : gather_resp_din <= {dma_rd_rsp_data[(64 - 29) * 8 - 1 : 0], qv_unwritten_data[29 * 8 - 1 : 0]}; + 30 : gather_resp_din <= {dma_rd_rsp_data[(64 - 30) * 8 - 1 : 0], qv_unwritten_data[30 * 8 - 1 : 0]}; + 31 : gather_resp_din <= {dma_rd_rsp_data[(64 - 31) * 8 - 1 : 0], qv_unwritten_data[31 * 8 - 1 : 0]}; + 32 : gather_resp_din <= {dma_rd_rsp_data[(64 - 32) * 8 - 1 : 0], qv_unwritten_data[32 * 8 - 1 : 0]}; + 33 : gather_resp_din <= {dma_rd_rsp_data[(64 - 33) * 8 - 1 : 0], qv_unwritten_data[33 * 8 - 1 : 0]}; + 34 : gather_resp_din <= {dma_rd_rsp_data[(64 - 34) * 8 - 1 : 0], qv_unwritten_data[34 * 8 - 1 : 0]}; + 35 : gather_resp_din <= {dma_rd_rsp_data[(64 - 35) * 8 - 1 : 0], qv_unwritten_data[35 * 8 - 1 : 0]}; + 36 : gather_resp_din <= {dma_rd_rsp_data[(64 - 36) * 8 - 1 : 0], qv_unwritten_data[36 * 8 - 1 : 0]}; + 37 : gather_resp_din <= {dma_rd_rsp_data[(64 - 37) * 8 - 1 : 0], qv_unwritten_data[37 * 8 - 1 : 0]}; + 38 : gather_resp_din <= {dma_rd_rsp_data[(64 - 38) * 8 - 1 : 0], qv_unwritten_data[38 * 8 - 1 : 0]}; + 39 : gather_resp_din <= {dma_rd_rsp_data[(64 - 39) * 8 - 1 : 0], qv_unwritten_data[39 * 8 - 1 : 0]}; + 40 : gather_resp_din <= {dma_rd_rsp_data[(64 - 40) * 8 - 1 : 0], qv_unwritten_data[40 * 8 - 1 : 0]}; + 41 : gather_resp_din <= {dma_rd_rsp_data[(64 - 41) * 8 - 1 : 0], qv_unwritten_data[41 * 8 - 1 : 0]}; + 42 : gather_resp_din <= {dma_rd_rsp_data[(64 - 42) * 8 - 1 : 0], qv_unwritten_data[42 * 8 - 1 : 0]}; + 43 : gather_resp_din <= {dma_rd_rsp_data[(64 - 43) * 8 - 1 : 0], qv_unwritten_data[43 * 8 - 1 : 0]}; + 44 : gather_resp_din <= {dma_rd_rsp_data[(64 - 44) * 8 - 1 : 0], qv_unwritten_data[44 * 8 - 1 : 0]}; + 45 : gather_resp_din <= {dma_rd_rsp_data[(64 - 45) * 8 - 1 : 0], qv_unwritten_data[45 * 8 - 1 : 0]}; + 46 : gather_resp_din <= {dma_rd_rsp_data[(64 - 46) * 8 - 1 : 0], qv_unwritten_data[46 * 8 - 1 : 0]}; + 47 : gather_resp_din <= {dma_rd_rsp_data[(64 - 47) * 8 - 1 : 0], qv_unwritten_data[47 * 8 - 1 : 0]}; + 48 : gather_resp_din <= {dma_rd_rsp_data[(64 - 48) * 8 - 1 : 0], qv_unwritten_data[48 * 8 - 1 : 0]}; + 49 : gather_resp_din <= {dma_rd_rsp_data[(64 - 49) * 8 - 1 : 0], qv_unwritten_data[49 * 8 - 1 : 0]}; + 50 : gather_resp_din <= {dma_rd_rsp_data[(64 - 50) * 8 - 1 : 0], qv_unwritten_data[50 * 8 - 1 : 0]}; + 51 : gather_resp_din <= {dma_rd_rsp_data[(64 - 51) * 8 - 1 : 0], qv_unwritten_data[51 * 8 - 1 : 0]}; + 52 : gather_resp_din <= {dma_rd_rsp_data[(64 - 52) * 8 - 1 : 0], qv_unwritten_data[52 * 8 - 1 : 0]}; + 53 : gather_resp_din <= {dma_rd_rsp_data[(64 - 53) * 8 - 1 : 0], qv_unwritten_data[53 * 8 - 1 : 0]}; + 54 : gather_resp_din <= {dma_rd_rsp_data[(64 - 54) * 8 - 1 : 0], qv_unwritten_data[54 * 8 - 1 : 0]}; + 55 : gather_resp_din <= {dma_rd_rsp_data[(64 - 55) * 8 - 1 : 0], qv_unwritten_data[55 * 8 - 1 : 0]}; + 56 : gather_resp_din <= {dma_rd_rsp_data[(64 - 56) * 8 - 1 : 0], qv_unwritten_data[56 * 8 - 1 : 0]}; + 57 : gather_resp_din <= {dma_rd_rsp_data[(64 - 57) * 8 - 1 : 0], qv_unwritten_data[57 * 8 - 1 : 0]}; + 58 : gather_resp_din <= {dma_rd_rsp_data[(64 - 58) * 8 - 1 : 0], qv_unwritten_data[58 * 8 - 1 : 0]}; + 59 : gather_resp_din <= {dma_rd_rsp_data[(64 - 59) * 8 - 1 : 0], qv_unwritten_data[59 * 8 - 1 : 0]}; + 60 : gather_resp_din <= {dma_rd_rsp_data[(64 - 60) * 8 - 1 : 0], qv_unwritten_data[60 * 8 - 1 : 0]}; + 61 : gather_resp_din <= {dma_rd_rsp_data[(64 - 61) * 8 - 1 : 0], qv_unwritten_data[61 * 8 - 1 : 0]}; + 62 : gather_resp_din <= {dma_rd_rsp_data[(64 - 62) * 8 - 1 : 0], qv_unwritten_data[62 * 8 - 1 : 0]}; + 63 : gather_resp_din <= {dma_rd_rsp_data[(64 - 63) * 8 - 1 : 0], qv_unwritten_data[63 * 8 - 1 : 0]}; + default: gather_resp_din <= gather_resp_din; + endcase + end + else if(qv_page_length_left + qv_unwritten_len < 64) begin + case(qv_unwritten_len) + 0 : gather_resp_din <= dma_rd_rsp_data; + 1 : gather_resp_din <= {dma_rd_rsp_data[(64 - 1 ) * 8 - 1 : 0], qv_unwritten_data[1 * 8 - 1 : 0]}; + 2 : gather_resp_din <= {dma_rd_rsp_data[(64 - 2 ) * 8 - 1 : 0], qv_unwritten_data[2 * 8 - 1 : 0]}; + 3 : gather_resp_din <= {dma_rd_rsp_data[(64 - 3 ) * 8 - 1 : 0], qv_unwritten_data[3 * 8 - 1 : 0]}; + 4 : gather_resp_din <= {dma_rd_rsp_data[(64 - 4 ) * 8 - 1 : 0], qv_unwritten_data[4 * 8 - 1 : 0]}; + 5 : gather_resp_din <= {dma_rd_rsp_data[(64 - 5 ) * 8 - 1 : 0], qv_unwritten_data[5 * 8 - 1 : 0]}; + 6 : gather_resp_din <= {dma_rd_rsp_data[(64 - 6 ) * 8 - 1 : 0], qv_unwritten_data[6 * 8 - 1 : 0]}; + 7 : gather_resp_din <= {dma_rd_rsp_data[(64 - 7 ) * 8 - 1 : 0], qv_unwritten_data[7 * 8 - 1 : 0]}; + 8 : gather_resp_din <= {dma_rd_rsp_data[(64 - 8 ) * 8 - 1 : 0], qv_unwritten_data[8 * 8 - 1 : 0]}; + 9 : gather_resp_din <= {dma_rd_rsp_data[(64 - 9 ) * 8 - 1 : 0], qv_unwritten_data[9 * 8 - 1 : 0]}; + 10 : gather_resp_din <= {dma_rd_rsp_data[(64 - 10) * 8 - 1 : 0], qv_unwritten_data[10 * 8 - 1 : 0]}; + 11 : gather_resp_din <= {dma_rd_rsp_data[(64 - 11) * 8 - 1 : 0], qv_unwritten_data[11 * 8 - 1 : 0]}; + 12 : gather_resp_din <= {dma_rd_rsp_data[(64 - 12) * 8 - 1 : 0], qv_unwritten_data[12 * 8 - 1 : 0]}; + 13 : gather_resp_din <= {dma_rd_rsp_data[(64 - 13) * 8 - 1 : 0], qv_unwritten_data[13 * 8 - 1 : 0]}; + 14 : gather_resp_din <= {dma_rd_rsp_data[(64 - 14) * 8 - 1 : 0], qv_unwritten_data[14 * 8 - 1 : 0]}; + 15 : gather_resp_din <= {dma_rd_rsp_data[(64 - 15) * 8 - 1 : 0], qv_unwritten_data[15 * 8 - 1 : 0]}; + 16 : gather_resp_din <= {dma_rd_rsp_data[(64 - 16) * 8 - 1 : 0], qv_unwritten_data[16 * 8 - 1 : 0]}; + 17 : gather_resp_din <= {dma_rd_rsp_data[(64 - 17) * 8 - 1 : 0], qv_unwritten_data[17 * 8 - 1 : 0]}; + 18 : gather_resp_din <= {dma_rd_rsp_data[(64 - 18) * 8 - 1 : 0], qv_unwritten_data[18 * 8 - 1 : 0]}; + 19 : gather_resp_din <= {dma_rd_rsp_data[(64 - 19) * 8 - 1 : 0], qv_unwritten_data[19 * 8 - 1 : 0]}; + 20 : gather_resp_din <= {dma_rd_rsp_data[(64 - 20) * 8 - 1 : 0], qv_unwritten_data[20 * 8 - 1 : 0]}; + 21 : gather_resp_din <= {dma_rd_rsp_data[(64 - 21) * 8 - 1 : 0], qv_unwritten_data[21 * 8 - 1 : 0]}; + 22 : gather_resp_din <= {dma_rd_rsp_data[(64 - 22) * 8 - 1 : 0], qv_unwritten_data[22 * 8 - 1 : 0]}; + 23 : gather_resp_din <= {dma_rd_rsp_data[(64 - 23) * 8 - 1 : 0], qv_unwritten_data[23 * 8 - 1 : 0]}; + 24 : gather_resp_din <= {dma_rd_rsp_data[(64 - 24) * 8 - 1 : 0], qv_unwritten_data[24 * 8 - 1 : 0]}; + 25 : gather_resp_din <= {dma_rd_rsp_data[(64 - 25) * 8 - 1 : 0], qv_unwritten_data[25 * 8 - 1 : 0]}; + 26 : gather_resp_din <= {dma_rd_rsp_data[(64 - 26) * 8 - 1 : 0], qv_unwritten_data[26 * 8 - 1 : 0]}; + 27 : gather_resp_din <= {dma_rd_rsp_data[(64 - 27) * 8 - 1 : 0], qv_unwritten_data[27 * 8 - 1 : 0]}; + 28 : gather_resp_din <= {dma_rd_rsp_data[(64 - 28) * 8 - 1 : 0], qv_unwritten_data[28 * 8 - 1 : 0]}; + 29 : gather_resp_din <= {dma_rd_rsp_data[(64 - 29) * 8 - 1 : 0], qv_unwritten_data[29 * 8 - 1 : 0]}; + 30 : gather_resp_din <= {dma_rd_rsp_data[(64 - 30) * 8 - 1 : 0], qv_unwritten_data[30 * 8 - 1 : 0]}; + 31 : gather_resp_din <= {dma_rd_rsp_data[(64 - 31) * 8 - 1 : 0], qv_unwritten_data[31 * 8 - 1 : 0]}; + 32 : gather_resp_din <= {dma_rd_rsp_data[(64 - 32) * 8 - 1 : 0], qv_unwritten_data[32 * 8 - 1 : 0]}; + 33 : gather_resp_din <= {dma_rd_rsp_data[(64 - 33) * 8 - 1 : 0], qv_unwritten_data[33 * 8 - 1 : 0]}; + 34 : gather_resp_din <= {dma_rd_rsp_data[(64 - 34) * 8 - 1 : 0], qv_unwritten_data[34 * 8 - 1 : 0]}; + 35 : gather_resp_din <= {dma_rd_rsp_data[(64 - 35) * 8 - 1 : 0], qv_unwritten_data[35 * 8 - 1 : 0]}; + 36 : gather_resp_din <= {dma_rd_rsp_data[(64 - 36) * 8 - 1 : 0], qv_unwritten_data[36 * 8 - 1 : 0]}; + 37 : gather_resp_din <= {dma_rd_rsp_data[(64 - 37) * 8 - 1 : 0], qv_unwritten_data[37 * 8 - 1 : 0]}; + 38 : gather_resp_din <= {dma_rd_rsp_data[(64 - 38) * 8 - 1 : 0], qv_unwritten_data[38 * 8 - 1 : 0]}; + 39 : gather_resp_din <= {dma_rd_rsp_data[(64 - 39) * 8 - 1 : 0], qv_unwritten_data[39 * 8 - 1 : 0]}; + 40 : gather_resp_din <= {dma_rd_rsp_data[(64 - 40) * 8 - 1 : 0], qv_unwritten_data[40 * 8 - 1 : 0]}; + 41 : gather_resp_din <= {dma_rd_rsp_data[(64 - 41) * 8 - 1 : 0], qv_unwritten_data[41 * 8 - 1 : 0]}; + 42 : gather_resp_din <= {dma_rd_rsp_data[(64 - 42) * 8 - 1 : 0], qv_unwritten_data[42 * 8 - 1 : 0]}; + 43 : gather_resp_din <= {dma_rd_rsp_data[(64 - 43) * 8 - 1 : 0], qv_unwritten_data[43 * 8 - 1 : 0]}; + 44 : gather_resp_din <= {dma_rd_rsp_data[(64 - 44) * 8 - 1 : 0], qv_unwritten_data[44 * 8 - 1 : 0]}; + 45 : gather_resp_din <= {dma_rd_rsp_data[(64 - 45) * 8 - 1 : 0], qv_unwritten_data[45 * 8 - 1 : 0]}; + 46 : gather_resp_din <= {dma_rd_rsp_data[(64 - 46) * 8 - 1 : 0], qv_unwritten_data[46 * 8 - 1 : 0]}; + 47 : gather_resp_din <= {dma_rd_rsp_data[(64 - 47) * 8 - 1 : 0], qv_unwritten_data[47 * 8 - 1 : 0]}; + 48 : gather_resp_din <= {dma_rd_rsp_data[(64 - 48) * 8 - 1 : 0], qv_unwritten_data[48 * 8 - 1 : 0]}; + 49 : gather_resp_din <= {dma_rd_rsp_data[(64 - 49) * 8 - 1 : 0], qv_unwritten_data[49 * 8 - 1 : 0]}; + 50 : gather_resp_din <= {dma_rd_rsp_data[(64 - 50) * 8 - 1 : 0], qv_unwritten_data[50 * 8 - 1 : 0]}; + 51 : gather_resp_din <= {dma_rd_rsp_data[(64 - 51) * 8 - 1 : 0], qv_unwritten_data[51 * 8 - 1 : 0]}; + 52 : gather_resp_din <= {dma_rd_rsp_data[(64 - 52) * 8 - 1 : 0], qv_unwritten_data[52 * 8 - 1 : 0]}; + 53 : gather_resp_din <= {dma_rd_rsp_data[(64 - 53) * 8 - 1 : 0], qv_unwritten_data[53 * 8 - 1 : 0]}; + 54 : gather_resp_din <= {dma_rd_rsp_data[(64 - 54) * 8 - 1 : 0], qv_unwritten_data[54 * 8 - 1 : 0]}; + 55 : gather_resp_din <= {dma_rd_rsp_data[(64 - 55) * 8 - 1 : 0], qv_unwritten_data[55 * 8 - 1 : 0]}; + 56 : gather_resp_din <= {dma_rd_rsp_data[(64 - 56) * 8 - 1 : 0], qv_unwritten_data[56 * 8 - 1 : 0]}; + 57 : gather_resp_din <= {dma_rd_rsp_data[(64 - 57) * 8 - 1 : 0], qv_unwritten_data[57 * 8 - 1 : 0]}; + 58 : gather_resp_din <= {dma_rd_rsp_data[(64 - 58) * 8 - 1 : 0], qv_unwritten_data[58 * 8 - 1 : 0]}; + 59 : gather_resp_din <= {dma_rd_rsp_data[(64 - 59) * 8 - 1 : 0], qv_unwritten_data[59 * 8 - 1 : 0]}; + 60 : gather_resp_din <= {dma_rd_rsp_data[(64 - 60) * 8 - 1 : 0], qv_unwritten_data[60 * 8 - 1 : 0]}; + 61 : gather_resp_din <= {dma_rd_rsp_data[(64 - 61) * 8 - 1 : 0], qv_unwritten_data[61 * 8 - 1 : 0]}; + 62 : gather_resp_din <= {dma_rd_rsp_data[(64 - 62) * 8 - 1 : 0], qv_unwritten_data[62 * 8 - 1 : 0]}; + 63 : gather_resp_din <= {dma_rd_rsp_data[(64 - 63) * 8 - 1 : 0], qv_unwritten_data[63 * 8 - 1 : 0]}; + default: gather_resp_din <= gather_resp_din; + endcase + end + else begin + gather_resp_din <= gather_resp_din; + end + end + else if(qv_page_length_left == 0 && !gather_resp_prog_full) begin + gather_resp_din <= qv_unwritten_data; + end + end + else begin + gather_resp_din <= gather_resp_din; + end +end + +/*------------------------------------------- Variables Decode : End ------------------------------------------------*/ + +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Peripherals/IngressDispatcher.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Peripherals/IngressDispatcher.v new file mode 100644 index 0000000000000000000000000000000000000000..503df95bd7d9a8a0e5e37b18333eb7da8829fde7 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Peripherals/IngressDispatcher.v @@ -0,0 +1,79 @@ +/*------------------------------------------- Module Description : Begin ---------------------------------------------- +Name: EgressPacketGen +Author: YangFan +Function: Dispatch ingress packet to ReqRecvEngine or RespRecvEngine. +--------------------------------------------- Module Decription : End -----------------------------------------------*/ + +/*------------------------------------------- Timescale Definition : Begin ------------------------------------------*/ +`timescale 1ns / 1ps +/*------------------------------------------- Timescale Definition : End --------------------------------------------*/ + +/*------------------------------------------- Included Files : Begin ------------------------------------------------*/ +`include "protocol_engine_def.vh" +/*------------------------------------------- Included Files : End --------------------------------------------------*/ + +/*------------------------------------------- Local Macros Definition : Begin ---------------------------------------*/ +/*------------------------------------------- Local Macros Definition : End -----------------------------------------*/ + +/*------------------------------------------- Input/Output Definition : Begin ---------------------------------------*/ +module IngressDispatcher +( + input wire clk, + input wire rst, + + input wire ingress_packet_valid, + input wire [`PKT_HEAD_BUS_WIDTH - 1 : 0] ingress_packet_head, + input wire [`PKT_DATA_BUS_WIDTH - 1 : 0] ingress_packet_data, + input wire ingress_packet_start, + input wire ingress_packet_last, + output wire ingress_packet_ready, + + output wire req_recv_pkt_meta_valid, + output wire [`PKT_HEAD_BUS_WIDTH - 1 : 0] req_recv_pkt_meta_data, + input wire req_recv_pkt_meta_ready, + + output wire req_recv_insert_req_valid, + output wire [`REQ_RECV_SLOT_NUM_LOG + `QP_NUM_LOG - 1 : 0] req_recv_insert_req_head, + output wire [`REQ_RECV_SLOT_WIDTH - 1 : 0] req_recv_insert_req_data, + output wire req_recv_insert_req_start, + output wire req_recv_insert_req_last, + input wire req_recv_insert_req_ready, + + input wire req_recv_insert_resp_valid, + input wire [`REQ_RECV_SLOT_NUM_LOG - 1 : 0] req_recv_insert_resp_data, + + output wire resp_recv_pkt_meta_valid, + output wire [`PKT_HEAD_BUS_WIDTH - 1 : 0] resp_recv_pkt_meta_data, + input wire resp_recv_pkt_meta_ready, + + output wire resp_recv_insert_req_valid, + output wire [`RESP_RECV_SLOT_NUM_LOG + `QP_NUM_LOG - 1 : 0] resp_recv_insert_req_head, + output wire [`RESP_RECV_SLOT_WIDTH - 1 : 0] resp_recv_insert_req_data, + output wire resp_recv_insert_req_start, + output wire resp_recv_insert_req_last, + input wire resp_recv_insert_req_ready, + + input wire resp_recv_insert_resp_valid, + input wire [`RESP_RECV_SLOT_NUM_LOG - 1 : 0] resp_recv_insert_resp_data +); +/*------------------------------------------- Input/Output Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Variables Definition : Begin ------------------------------------*/ + + +/*------------------------------------------- Local Variables Definition : End --------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : Begin ---------------------------------------*/ + + +/*------------------------------------------- Submodules Instatiation : End -----------------------------------------*/ + +/*------------------------------------------- State Machine Definition : Begin --------------------------------------*/ + +/*------------------------------------------- State Machine Definition : End ----------------------------------------*/ + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ + +/*------------------------------------------- Variables Decode : End ------------------------------------------------*/ + +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Peripherals/IngressPacketGen.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Peripherals/IngressPacketGen.v new file mode 100644 index 0000000000000000000000000000000000000000..810c5c517fa0c79039a0677fb46ac475c25c934f --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Peripherals/IngressPacketGen.v @@ -0,0 +1,255 @@ +/*------------------------------------------- Module Description : Begin ---------------------------------------------- +Name: IngressPacketGen +Author: YangFan +Function: In NIC/Switch processing pipeline, protocol processing requires frequent appending and removing header. + This module abstracts the append process. +--------------------------------------------- Module Decription : End -----------------------------------------------*/ + +/*------------------------------------------- Timescale Definition : Begin ------------------------------------------*/ +`timescale 1ns / 1ps +/*------------------------------------------- Timescale Definition : End --------------------------------------------*/ + +/*------------------------------------------- Included Files : Begin ------------------------------------------------*/ +`include "protocol_engine_def.vh" +/*------------------------------------------- Included Files : End --------------------------------------------------*/ + +/*------------------------------------------- Local Macros Definition : Begin ---------------------------------------*/ +/*------------------------------------------- Local Macros Definition : End -----------------------------------------*/ + +/*------------------------------------------- Input/Output Definition : Begin ---------------------------------------*/ +module IngressPacketGen +( + input wire clk, + input wire rst, + + input wire mac_axis_rx_valid, + input wire [511:0] mac_axis_rx_data, + input wire [63:0] mac_axis_rx_keep, + input wire mac_axis_rx_last, + input wire mac_axis_rx_user, + + output wire req_recv_pkt_meta_valid, + output wire [`PKT_HEAD_BUS_WIDTH - 1 : 0] req_recv_pkt_meta_data, + input wire req_recv_pkt_meta_ready, + + input wire req_recv_pkt_dequeue_req_valid, + input wire [`REQ_RECV_SLOT_NUM_LOG + `QP_NUM_LOG - 1 : 0] req_recv_pkt_dequeue_req_head, + output wire req_recv_pkt_dequeue_req_ready, + + output wire req_recv_pkt_dequeue_resp_valid, + output wire [`REQ_RECV_SLOT_NUM_LOG + `QP_NUM_LOG - 1 : 0] req_recv_pkt_dequeue_resp_head, + output wire [`REQ_RECV_SLOT_WIDTH - 1 : 0] req_recv_pkt_dequeue_resp_data, + output wire req_recv_pkt_dequeue_resp_start, + output wire req_recv_pkt_dequeue_resp_last, + input wire req_recv_pkt_dequeue_resp_ready, + + output wire resp_recv_pkt_meta_valid, + output wire [`PKT_HEAD_BUS_WIDTH - 1 : 0] resp_recv_pkt_meta_data, + input wire resp_recv_pkt_meta_ready, + + input wire resp_recv_pkt_dequeue_req_valid, + input wire [`RESP_RECV_SLOT_NUM_LOG + `QP_NUM_LOG - 1 : 0] resp_recv_pkt_dequeue_req_head, + output wire resp_recv_pkt_dequeue_req_ready, + + output wire resp_recv_pkt_dequeue_resp_valid, + output wire [`RESP_RECV_SLOT_NUM_LOG + `QP_NUM_LOG - 1 : 0] resp_recv_pkt_dequeue_resp_head, + output wire [`RESP_RECV_SLOT_WIDTH - 1 : 0] resp_recv_pkt_dequeue_resp_data, + output wire resp_recv_pkt_dequeue_resp_start, + output wire resp_recv_pkt_dequeue_resp_last, + input wire resp_recv_pkt_dequeue_resp_ready +); +/*------------------------------------------- Input/Output Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Variables Definition : Begin ------------------------------------*/ +//Gen Packet Header Length for PacketDecap +wire [`PKT_HEAD_BUS_WIDTH - 1 : 0] mac_axis_rx_head; + +wire ingress_packet_valid; +wire [`PKT_HEAD_BUS_WIDTH - 1 : 0] ingress_packet_head; +wire [`PKT_DATA_BUS_WIDTH - 1 : 0] ingress_packet_data; +wire ingress_packet_start; +wire ingress_packet_last; +wire ingress_packet_ready; + +wire req_recv_insert_req_valid; +wire req_recv_insert_req_start; +wire req_recv_insert_req_last; +wire [`REQ_RECV_SLOT_NUM_LOG - 1 : 0] req_recv_insert_req_head; +wire [`REQ_RECV_SLOT_WIDTH - 1 : 0] req_recv_insert_req_data; +wire req_recv_insert_req_ready; + +wire req_recv_insert_resp_valid; +wire [`REQ_RECV_SLOT_WIDTH - 1 : 0] req_recv_insert_resp_data; + +wire resp_recv_insert_req_valid; +wire resp_recv_insert_req_start; +wire resp_recv_insert_req_last; +wire [`RESP_RECV_SLOT_NUM_LOG - 1 : 0] resp_recv_insert_req_head; +wire [`RESP_RECV_SLOT_WIDTH - 1 : 0] resp_recv_insert_req_data; +wire resp_recv_insert_req_ready; + +wire resp_recv_insert_resp_valid; +wire [`RESP_RECV_SLOT_WIDTH - 1 : 0] resp_recv_insert_resp_data; +/*------------------------------------------- Local Variables Definition : End --------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : Begin ---------------------------------------*/ + +assign mac_axis_rx_head = `TODO; + + +PacketDecap +#( + .HEADER_BUS_WIDTH ( `PKT_HEAD_BUS_WIDTH ), + .PAYLOAD_BUS_WIDTH ( `PKT_DATA_BUS_WIDTH ) +) +PacketDecap_Inst( + .clk ( clk ), + .rst ( rst ), + + .i_packet_in_valid ( mac_axis_rx_valid ), + .iv_packet_in_head ( mac_axis_rx_head ), + .iv_packet_in_data ( mac_axis_rx_data ), + .i_packet_in_start ( 'd0 ), + .i_packet_in_last ( mac_axis_rx_last ), + .o_packet_in_ready ( ), + + .o_packet_out_valid ( ingress_packet_valid ), + .ov_packet_out_head ( ingress_packet_head ), + .ov_packet_out_data ( ingress_packet_data ), + .o_packet_out_start ( ingress_packet_start ), + .o_packet_out_last ( ingress_packet_last ), + .i_packet_out_ready ( ingress_packet_ready ) +); + +IngressDispatcher IngressDispatcher_Inst( + .clk ( clk ), + .rst ( rst ), + + .ingress_packet_valid ( ingress_packet_valid ), + .ingress_packet_head ( ingress_packet_head ), + .ingress_packet_data ( ingress_packet_data ), + .ingress_packet_start ( ingress_packet_start ), + .ingress_packet_last ( ingress_packet_last ), + .ingress_packet_ready ( ingress_packet_ready ), + + .req_recv_insert_req_valid ( req_recv_insert_req_valid ), + .req_recv_insert_req_start ( req_recv_insert_req_start ), + .req_recv_insert_req_last ( req_recv_insert_req_last ), + .req_recv_insert_req_head ( req_recv_insert_req_head ), + .req_recv_insert_req_data ( req_recv_insert_req_data ), + .req_recv_insert_req_ready ( req_recv_insert_req_ready ), + + .req_recv_insert_resp_valid ( req_recv_insert_resp_valid ), + .req_recv_insert_resp_data ( req_recv_insert_resp_data ), + + .req_recv_pkt_meta_valid ( req_recv_pkt_meta_valid ), + .req_recv_pkt_meta_data ( req_recv_pkt_meta_data ), + .req_recv_pkt_meta_ready ( req_recv_pkt_meta_ready ), + + .resp_recv_insert_req_valid ( resp_recv_insert_req_valid ), + .resp_recv_insert_req_start ( resp_recv_insert_req_start ), + .resp_recv_insert_req_last ( resp_recv_insert_req_last ), + .resp_recv_insert_req_head ( resp_recv_insert_req_head ), + .resp_recv_insert_req_data ( resp_recv_insert_req_data ), + .resp_recv_insert_req_ready ( resp_recv_insert_req_ready ), + + .resp_recv_insert_resp_valid ( resp_recv_insert_resp_valid ), + .resp_recv_insert_resp_data ( resp_recv_insert_resp_data ), + + .resp_recv_pkt_meta_valid ( resp_recv_pkt_meta_valid ), + .resp_recv_pkt_meta_data ( resp_recv_pkt_meta_data ), + .resp_recv_pkt_meta_ready ( resp_recv_pkt_meta_ready ) +); + +DynamicBuffer +#( + .SLOT_NUM ( `REQ_RECV_SLOT_NUM ), + .SLOT_WIDTH ( `REQ_RECV_SLOT_WIDTH ) +) +ReqRecvBuffer_Inst( + .clk ( clk ), + .rst ( rst ), + + .ov_available_slot_num ( ), + + .i_insert_req_valid ( req_recv_insert_req_valid ), + .i_insert_req_start ( req_recv_insert_req_start ), + .i_insert_req_last ( req_recv_insert_req_last ), + .iv_insert_req_head ( req_recv_insert_req_head ), + .iv_insert_req_data ( req_recv_insert_req_data ), + .o_insert_req_ready ( req_recv_insert_req_ready ), + + .o_insert_resp_valid ( req_recv_insert_resp_valid ), + .ov_insert_resp_data ( req_recv_insert_resp_data ), + + .i_get_req_valid ( 'd0 ), + .iv_get_req_head ( 'd0 ), + .o_get_req_ready ( ), + .o_get_resp_valid ( ), + .o_get_resp_start ( ), + .o_get_resp_last ( ), + .ov_get_resp_data ( ), + .i_get_resp_ready ( 'd1 ), + + .i_delete_req_valid ( req_recv_pkt_dequeue_req_valid ), + .iv_delete_req_head ( req_recv_pkt_dequeue_req_head ), + .o_delete_req_ready ( req_recv_pkt_dequeue_req_ready ), + + .o_delete_resp_valid ( req_recv_pkt_dequeue_resp_valid ), + .o_delete_resp_start ( req_recv_pkt_dequeue_resp_start ), + .o_delete_resp_last ( req_recv_pkt_dequeue_resp_last ), + .ov_delete_resp_data ( req_recv_pkt_dequeue_resp_data ), + .i_delete_resp_ready ( req_recv_pkt_dequeue_resp_read ) +); + +DynamicBuffer +#( + .SLOT_NUM ( `RESP_RECV_SLOT_NUM ), + .SLOT_WIDTH ( `RESP_RECV_SLOT_WIDTH ) +) +RespRecvBuffer_Inst( + .clk ( clk ), + .rst ( rst ), + + .ov_available_slot_num ( ), + + .i_insert_req_valid ( resp_recv_insert_req_valid ), + .i_insert_req_start ( resp_recv_insert_req_start ), + .i_insert_req_last ( resp_recv_insert_req_last ), + .iv_insert_req_head ( resp_recv_insert_req_head ), + .iv_insert_req_data ( resp_recv_insert_req_data ), + .o_insert_req_ready ( resp_recv_insert_req_ready ), + + .o_insert_resp_valid ( resp_recv_insert_resp_valid ), + .ov_insert_resp_data ( resp_recv_insert_resp_data ), + + .i_get_req_valid ( 'd0 ), + .iv_get_req_head ( 'd0 ), + .o_get_req_ready ( ), + .o_get_resp_valid ( ), + .o_get_resp_start ( ), + .o_get_resp_last ( ), + .ov_get_resp_data ( ), + .i_get_resp_ready ( 'd1 ), + + .i_delete_req_valid ( resp_recv_pkt_dequeue_req_valid ), + .iv_delete_req_head ( resp_recv_pkt_dequeue_req_head ), + .o_delete_req_ready ( resp_recv_pkt_dequeue_req_ready ), + + .o_delete_resp_valid ( resp_recv_pkt_dequeue_resp_valid ), + .o_delete_resp_start ( resp_recv_pkt_dequeue_resp_start ), + .o_delete_resp_last ( resp_recv_pkt_dequeue_resp_last ), + .ov_delete_resp_data ( resp_recv_pkt_dequeue_resp_data ), + .i_delete_resp_ready ( resp_recv_pkt_dequeue_resp_read ) +); +/*------------------------------------------- Submodules Instatiation : End -----------------------------------------*/ + +/*------------------------------------------- State Machine Definition : Begin --------------------------------------*/ + +/*------------------------------------------- State Machine Definition : End ----------------------------------------*/ + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ + +/*------------------------------------------- Variables Decode : End ------------------------------------------------*/ + +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Peripherals/MACDecap.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Peripherals/MACDecap.v new file mode 100644 index 0000000000000000000000000000000000000000..fe59a4df33755bee52c635e921574b1c4ea2fcf7 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Peripherals/MACDecap.v @@ -0,0 +1,677 @@ +/*------------------------------------------- Module Description : Begin ---------------------------------------------- +Name: PacketEncap +Author: YangFan +Function: In NIC/Switch processing pipeline, protocol processing requires frequent appending and removing header. + This module abstracts the append process. +--------------------------------------------- Module Decription : End -----------------------------------------------*/ + +/*------------------------------------------- Timescale Definition : Begin ------------------------------------------*/ +`timescale 1ns / 1ps +/*------------------------------------------- Timescale Definition : End --------------------------------------------*/ + +/*------------------------------------------- Included Files : Begin ------------------------------------------------*/ +`include "common_function_def.vh" +/*------------------------------------------- Included Files : End --------------------------------------------------*/ + +/*------------------------------------------- Local Macros Definition : Begin ---------------------------------------*/ +/*------------------------------------------- Local Macros Definition : End -----------------------------------------*/ + +/*------------------------------------------- Input/Output Definition : Begin ---------------------------------------*/ +module MACDecap +( + input wire clk, + input wire rst, + + output wire insert_req_valid, + output wire insert_req_start, + output wire insert_req_last, + output wire [`MAX_DB_SLOT_NUM_LOG - 1 : 0] insert_req_head, + output reg [`PACKET_BUFFER_SLOT_WIDTH - 1 : 0] insert_req_data, + input wire insert_req_ready, + + output wire insert_resp_valid, + output wire [`MAX_DB_SLOT_NUM_LOG - 1 : 0] insert_resp_data, + + input wire mac_rx_valid, + output wire mac_rx_ready, + input wire mac_rx_start, + input wire mac_rx_last, + input wire [`MAC_KEEP_WIDTH - 1 : 0] mac_rx_keep, + input wire mac_rx_user, + input wire [`MAC_DATA_WIDTH - 1 : 0] mac_rx_data, + + output wire ingress_pkt_valid, + output wire [`PKT_META_BUS_WIDTH - 1 : 0] ingress_pkt_head, + input wire ingress_pkt_ready +); +/*------------------------------------------- Input/Output Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Macros Definition : Begin ---------------------------------------*/ +`define DMAC_OFFSET 63 : 16 +`define SMAC_OFFSET 111 : 64 + +`define SRC_QPN_OFFSET 23 + `MAC_HEADER_LENGTH * 8 : 0 + `MAC_HEADER_LENGTH * 8 +`define SERVICE_TYPE_OFFSET 26 + `MAC_HEADER_LENGTH * 8 : 24 + `MAC_HEADER_LENGTH * 8 +`define OPCODE_OFFSET 31 + `MAC_HEADER_LENGTH * 8 : 27 + `MAC_HEADER_LENGTH * 8 +`define DST_QPN_OFFSET 55 + `MAC_HEADER_LENGTH * 8 : 32 + `MAC_HEADER_LENGTH * 8 +`define PAYLOAD_LENGTH_OFFSET 71 + `MAC_HEADER_LENGTH * 8 : 56 + `MAC_HEADER_LENGTH * 8 + +`define RADDR_OFFSET 63 + `MAC_HEADER_LENGTH * 8 + `BTH_LENGTH * 8 : 0 + `MAC_HEADER_LENGTH * 8 + `BTH_LENGTH * 8 +`define RKEY_OFFSET 95 + `MAC_HEADER_LENGTH * 8 + `BTH_LENGTH * 8 : 64 + `MAC_HEADER_LENGTH * 8 + `BTH_LENGTH * 8 +`define DMA_LENGTH_OFFSET 127 + `MAC_HEADER_LENGTH * 8 + `BTH_LENGTH * 8 : 96 + `MAC_HEADER_LENGTH * 8 + `BTH_LENGTH * 8 +/*------------------------------------------- Local Macros Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Macros Definition : Begin ---------------------------------------*/ +reg [23:0] local_qpn; +reg [23:0] remote_qpn; +reg [4:0] opcode; +reg [2:0] service_type; +reg [7:0] syndrome; +reg [31:0] rkey; +reg [63:0] raddr; +reg [31:0] immediate; +reg [47:0] dmac; +reg [47:0] smac; +reg [31:0] dip; +reg [31:0] sip; +reg [15:0] payload_start_addr; +reg [15:0] payload_length; +/*------------------------------------------- Local Macros Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Variables Definition : Begin ------------------------------------*/ +reg [31:0] payload_left_length; +reg [31:0] unwritten_len; +reg [511:0] unwritten_data; + +reg [31:0] insert_count; +/*------------------------------------------- Local Variables Definition : End --------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : Begin ---------------------------------------*/ +//Null +/*------------------------------------------- Submodules Instatiation : End -----------------------------------------*/ + +/*------------------------------------------- State Machine Definition : Begin --------------------------------------*/ +reg [2:0] cur_state; +reg [2:0] next_state; + +parameter [2:0] IDLE_s = 3'd1, + BUFFER_PAYLOAD_s = 3'd2, + GEN_META_s = 3'd3; + +always @(posedge clk or posedge rst) begin + if (rst) begin + cur_state <= IDLE_s; + end + else begin + cur_state <= next_state; + end +end + +always @(*) begin + case(cur_state) + IDLE_s: if(mac_rx_valid) begin + if(mac_rx_data[`OPCODE_OFFSET] == `ACKNOWLEDGE || + mac_rx_data[`OPCODE_OFFSET] == `RDMA_READ_REQUEST_FIRST || + mac_rx_data[`OPCODE_OFFSET] == `RDMA_READ_REQUEST_MIDDLE || + mac_rx_data[`OPCODE_OFFSET] == `RDMA_READ_REQUEST_LAST || + mac_rx_data[`OPCODE_OFFSET] == `RDMA_READ_REQUEST_ONLY) begin + next_state = GEN_META_s; + end + else begin + next_state = BUFFER_PAYLOAD_s; + end + end + else begin + next_state = IDLE_s; + end + BUFFER_PAYLOAD_s: if(payload_left_length + unwritten_len <= 64) begin + if(payload_left_length == 0 && insert_req_ready) begin + next_state = GEN_META_s; + end + else if(payload_left_length > 0 && mac_rx_valid && insert_req_ready) begin + next_state = GEN_META_s; + end + else begin + next_state = BUFFER_PAYLOAD_s; + end + end + else begin + next_state = BUFFER_PAYLOAD_s; + end + GEN_META_s: if(ingress_pkt_valid && ingress_pkt_ready) begin + next_state = IDLE_s; + end + else begin + next_state = GEN_META_s; + end + default: next_state = IDLE_s; + endcase +end +/*------------------------------------------- State Machine Definition : End ----------------------------------------*/ + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ +//-- local_qpn -- +//-- remote_qpn -- +//-- opcode -- +//-- service_type -- +//-- syndrome -- +//-- rkey -- +//-- raddr -- +//-- immediate -- +//-- dmac -- +//-- smac -- +//-- dip -- +//-- sip -- +//-- payload_start_addr -- +//-- payload_length -- +always @(posedge clk or posedge rst) begin + if (rst) begin + local_qpn <= 'd0; + remote_qpn <= 'd0; + opcode <= 'd0; + service_type <= 'd0; + syndrome <= 'd0; + rkey <= 'd0; + raddr <= 'd0; + immediate <= 'd0; + dmac <= 'd0; + smac <= 'd0; + dip <= 'd0; + sip <= 'd0; + payload_length <= 'd0; + end + else if (cur_state == IDLE_s && mac_rx_valid) begin + local_qpn <= mac_rx_data[`SRC_QPN_OFFSET]; + remote_qpn <= mac_rx_data[`DST_QPN_OFFSET]; + opcode <= mac_rx_data[`OPCODE_OFFSET]; + service_type <= mac_rx_data[`SERVICE_TYPE_OFFSET]; + syndrome <= 'd0; + rkey <= mac_rx_data[`RKEY_OFFSET]; + raddr <= mac_rx_data[`RADDR_OFFSET]; + immediate <= 'd0; + dmac <= mac_rx_data[`DMAC_OFFSET]; + smac <= mac_rx_data[`SMAC_OFFSET]; + dip <= 'd0; + sip <= 'd0; + payload_length <= mac_rx_data[`PAYLOAD_LENGTH_OFFSET]; + end +end + +//-- payload_start_addr -- +always @(posedge clk or posedge rst) begin + if (rst) begin + payload_start_addr <= 'd0; + end + else if(cur_state == IDLE_s) begin + payload_start_addr <= 'd0; + end + else if (cur_state == BUFFER_PAYLOAD_s && insert_req_valid && insert_req_start && insert_req_ready && insert_resp_valid) begin + payload_start_addr <= insert_resp_data; + end + else begin + payload_start_addr <= payload_start_addr; + end +end + +//-- payload_left_length -- +always @(posedge clk or posedge rst) begin + if (rst) begin + payload_left_length <= 'd0; + end + else if (cur_state == IDLE_s && mac_rx_valid) begin + if(mac_rx_data[`PAYLOAD_LENGTH_OFFSET] == 0) begin + payload_left_length <= 'd0; + end + else begin + case(mac_rx_data[`OPCODE_OFFSET]) + `SEND_FIRST: payload_left_length <= mac_rx_data[`PAYLOAD_LENGTH_OFFSET] > (64 - `BTH_LENGTH - `MAC_HEADER_LENGTH) ? + mac_rx_data[`PAYLOAD_LENGTH_OFFSET] - (64 - `BTH_LENGTH - `MAC_HEADER_LENGTH) : 'd0; + `SEND_MIDDLE: payload_left_length <= mac_rx_data[`PAYLOAD_LENGTH_OFFSET] > (64 - `BTH_LENGTH - `MAC_HEADER_LENGTH) ? + mac_rx_data[`PAYLOAD_LENGTH_OFFSET] - (64 - `BTH_LENGTH - `MAC_HEADER_LENGTH) : 'd0; + `SEND_ONLY: payload_left_length <= mac_rx_data[`PAYLOAD_LENGTH_OFFSET] > (64 - `BTH_LENGTH - `MAC_HEADER_LENGTH) ? + mac_rx_data[`PAYLOAD_LENGTH_OFFSET] - (64 - `BTH_LENGTH - `MAC_HEADER_LENGTH) : 'd0; + `SEND_LAST: payload_left_length <= mac_rx_data[`PAYLOAD_LENGTH_OFFSET] > (64 - `BTH_LENGTH - `MAC_HEADER_LENGTH) ? + mac_rx_data[`PAYLOAD_LENGTH_OFFSET] - (64 - `BTH_LENGTH - `MAC_HEADER_LENGTH) : 'd0; + `SEND_ONLY_WITH_IMM: payload_left_length <= mac_rx_data[`PAYLOAD_LENGTH_OFFSET] > (64 - `IMMETH_LENGTH - `BTH_LENGTH - `MAC_HEADER_LENGTH) ? + mac_rx_data[`PAYLOAD_LENGTH_OFFSET] - (64 - `IMMETH_LENGTH - `BTH_LENGTH - `MAC_HEADER_LENGTH) : 'd0; + `SEND_LAST_WITH_IMM: payload_left_length <= mac_rx_data[`PAYLOAD_LENGTH_OFFSET] > (64 - `IMMETH_LENGTH - `BTH_LENGTH - `MAC_HEADER_LENGTH) ? + mac_rx_data[`PAYLOAD_LENGTH_OFFSET] - (64 - `IMMETH_LENGTH - `BTH_LENGTH - `MAC_HEADER_LENGTH) : 'd0; + `RDMA_WRITE_FIRST: payload_left_length <= mac_rx_data[`PAYLOAD_LENGTH_OFFSET] > (64 - `RETH_LENGTH - `BTH_LENGTH - `MAC_HEADER_LENGTH) ? + mac_rx_data[`PAYLOAD_LENGTH_OFFSET] - (64 - `RETH_LENGTH - `BTH_LENGTH - `MAC_HEADER_LENGTH) : 'd0; + `RDMA_WRITE_MIDDLE: payload_left_length <= mac_rx_data[`PAYLOAD_LENGTH_OFFSET] > (64 - `RETH_LENGTH - `BTH_LENGTH - `MAC_HEADER_LENGTH) ? + mac_rx_data[`PAYLOAD_LENGTH_OFFSET] - (64 - `RETH_LENGTH - `BTH_LENGTH - `MAC_HEADER_LENGTH) : 'd0; + `RDMA_WRITE_LAST: payload_left_length <= mac_rx_data[`PAYLOAD_LENGTH_OFFSET] > (64 - `RETH_LENGTH - `BTH_LENGTH - `MAC_HEADER_LENGTH) ? + mac_rx_data[`PAYLOAD_LENGTH_OFFSET] - (64 - `RETH_LENGTH - `BTH_LENGTH - `MAC_HEADER_LENGTH) : 'd0; + `RDMA_WRITE_ONLY: payload_left_length <= mac_rx_data[`PAYLOAD_LENGTH_OFFSET] > (64 - `RETH_LENGTH - `BTH_LENGTH - `MAC_HEADER_LENGTH) ? + mac_rx_data[`PAYLOAD_LENGTH_OFFSET] - (64 - `RETH_LENGTH - `BTH_LENGTH - `MAC_HEADER_LENGTH) : 'd0; + `RDMA_WRITE_LAST_WITH_IMM: payload_left_length <= mac_rx_data[`PAYLOAD_LENGTH_OFFSET] > (64 - `IMMETH_LENGTH - `RETH_LENGTH - `BTH_LENGTH - `MAC_HEADER_LENGTH) ? + mac_rx_data[`PAYLOAD_LENGTH_OFFSET] - (64 - `IMMETH_LENGTH - `RETH_LENGTH - `BTH_LENGTH - `MAC_HEADER_LENGTH) : 'd0; + `RDMA_WRITE_ONLY_WITH_IMM: payload_left_length <= mac_rx_data[`PAYLOAD_LENGTH_OFFSET] > (64 - `IMMETH_LENGTH - `RETH_LENGTH - `BTH_LENGTH - `MAC_HEADER_LENGTH) ? + mac_rx_data[`PAYLOAD_LENGTH_OFFSET] - (64 - `IMMETH_LENGTH - `RETH_LENGTH - `BTH_LENGTH - `MAC_HEADER_LENGTH) : 'd0; + `RDMA_READ_REQUEST_FIRST: payload_left_length <= 'd0; + `RDMA_READ_REQUEST_MIDDLE: payload_left_length <= 'd0; + `RDMA_READ_REQUEST_LAST: payload_left_length <= 'd0; + `RDMA_READ_REQUEST_ONLY: payload_left_length <= 'd0; + `RDMA_READ_RESPONSE_FIRST: payload_left_length <= mac_rx_data[`PAYLOAD_LENGTH_OFFSET] > (64 - `BTH_LENGTH - `MAC_HEADER_LENGTH) ? + mac_rx_data[`PAYLOAD_LENGTH_OFFSET] - (64 - `BTH_LENGTH - `MAC_HEADER_LENGTH) : 'd0; + `RDMA_READ_RESPONSE_MIDDLE: payload_left_length <= mac_rx_data[`PAYLOAD_LENGTH_OFFSET] > (64 - `BTH_LENGTH - `MAC_HEADER_LENGTH) ? + mac_rx_data[`PAYLOAD_LENGTH_OFFSET] - (64 - `BTH_LENGTH - `MAC_HEADER_LENGTH) : 'd0; + `RDMA_READ_RESPONSE_LAST: payload_left_length <= mac_rx_data[`PAYLOAD_LENGTH_OFFSET] > (64 - `BTH_LENGTH - `MAC_HEADER_LENGTH) ? + mac_rx_data[`PAYLOAD_LENGTH_OFFSET] - (64 - `BTH_LENGTH - `MAC_HEADER_LENGTH) : 'd0; + `RDMA_READ_RESPONSE_ONLY: payload_left_length <= mac_rx_data[`PAYLOAD_LENGTH_OFFSET] > (64 - `BTH_LENGTH - `MAC_HEADER_LENGTH) ? + mac_rx_data[`PAYLOAD_LENGTH_OFFSET] - (64 - `BTH_LENGTH - `MAC_HEADER_LENGTH) : 'd0; + `ACKNOWLEDGE: payload_left_length <= 'd0; + default: payload_left_length <= 'd0; + endcase + end + end + else if(cur_state == BUFFER_PAYLOAD_s) begin + if(payload_left_length == 0) begin //Only unwritten_len left + payload_left_length <= 'd0; + end + else if(payload_left_length > 0 && mac_rx_valid && insert_req_ready) begin + payload_left_length <= payload_left_length > 64 ? payload_left_length - 'd64 : 'd0; + end + else begin + payload_left_length <= payload_left_length; + end + end + else begin + payload_left_length <= payload_left_length; + end +end + +//-- unwritten_len -- +always @(posedge clk or posedge rst) begin + if (rst) begin + unwritten_len <= 'd0; + end + else if (cur_state == IDLE_s && mac_rx_valid) begin + case(mac_rx_data[`OPCODE_OFFSET]) + `SEND_FIRST: unwritten_len <= 64 - (`BTH_LENGTH + `MAC_HEADER_LENGTH); + `SEND_MIDDLE: unwritten_len <= 64 - (`BTH_LENGTH + `MAC_HEADER_LENGTH); + `SEND_ONLY: unwritten_len <= 64 - (`BTH_LENGTH + `MAC_HEADER_LENGTH); + `SEND_LAST: unwritten_len <= 64 - (`BTH_LENGTH + `MAC_HEADER_LENGTH); + `SEND_ONLY_WITH_IMM: unwritten_len <= 64 - (`BTH_LENGTH + `IMMETH_LENGTH + `MAC_HEADER_LENGTH); + `SEND_LAST_WITH_IMM: unwritten_len <= 64 - (`BTH_LENGTH + `MAC_HEADER_LENGTH); + `RDMA_WRITE_FIRST: unwritten_len <= 64 - (`BTH_LENGTH + `RETH_LENGTH + `MAC_HEADER_LENGTH); + `RDMA_WRITE_MIDDLE: unwritten_len <= 64 - (`BTH_LENGTH + `RETH_LENGTH + `MAC_HEADER_LENGTH); + `RDMA_WRITE_LAST: unwritten_len <= 64 - (`BTH_LENGTH + `RETH_LENGTH + `MAC_HEADER_LENGTH); + `RDMA_WRITE_ONLY: unwritten_len <= 64 - (`BTH_LENGTH + `RETH_LENGTH + `MAC_HEADER_LENGTH); + `RDMA_WRITE_LAST_WITH_IMM: unwritten_len <= 64 - (`BTH_LENGTH + `RETH_LENGTH +`IMMETH_LENGTH + `MAC_HEADER_LENGTH); + `RDMA_WRITE_ONLY_WITH_IMM: unwritten_len <= 64 - (`BTH_LENGTH + `RETH_LENGTH +`IMMETH_LENGTH + `MAC_HEADER_LENGTH); + `RDMA_READ_REQUEST_FIRST: unwritten_len <= 64 - (`BTH_LENGTH + `RETH_LENGTH + `MAC_HEADER_LENGTH); + `RDMA_READ_REQUEST_MIDDLE: unwritten_len <= 64 - (`BTH_LENGTH + `RETH_LENGTH + `MAC_HEADER_LENGTH); + `RDMA_READ_REQUEST_LAST: unwritten_len <= 64 - (`BTH_LENGTH + `RETH_LENGTH + `MAC_HEADER_LENGTH); + `RDMA_READ_REQUEST_ONLY: unwritten_len <= 64 - (`BTH_LENGTH + `RETH_LENGTH + `MAC_HEADER_LENGTH); + `RDMA_READ_RESPONSE_FIRST: unwritten_len <= 64 - (`BTH_LENGTH + `MAC_HEADER_LENGTH); + `RDMA_READ_RESPONSE_MIDDLE: unwritten_len <= 64 - (`BTH_LENGTH + `MAC_HEADER_LENGTH); + `RDMA_READ_RESPONSE_LAST: unwritten_len <= 64 - (`BTH_LENGTH + `MAC_HEADER_LENGTH); + `RDMA_READ_RESPONSE_ONLY: unwritten_len <= 64 - (`BTH_LENGTH + `MAC_HEADER_LENGTH); + `ACKNOWLEDGE: unwritten_len <= 64 - (`BTH_LENGTH + `AETH_LENGTH + `MAC_HEADER_LENGTH); + default: unwritten_len <= 'd0; + endcase + end + else if(cur_state == BUFFER_PAYLOAD_s) begin + if(payload_left_length == 0) begin //Last cycle insert + unwritten_len <= insert_req_ready ? 'd0 : unwritten_len; + end + else if(payload_left_length > 0 && mac_rx_valid && insert_req_ready) begin + if(payload_left_length + unwritten_len <= 64) begin //Last cycle transmit + unwritten_len <= 'd0; + end + else if(payload_left_length + unwritten_len > 64) begin + if(payload_left_length > 64) begin + unwritten_len <= unwritten_len; + end + else begin + unwritten_len <= payload_left_length + unwritten_len - 'd64; + end + end + else begin + unwritten_len <= unwritten_len; + end + end + else begin + unwritten_len <= unwritten_len; + end + end +end + +//-- unwritten_data -- +always @(posedge clk or posedge rst) begin + if (rst) begin + unwritten_data <= 'd0; + end + else if (cur_state == IDLE_s && mac_rx_valid) begin + case(mac_rx_data[`OPCODE_OFFSET]) + `SEND_FIRST: unwritten_data <= mac_rx_data[511 : (`BTH_LENGTH + `MAC_HEADER_LENGTH) * 8]; + `SEND_MIDDLE: unwritten_data <= mac_rx_data[511 : (`BTH_LENGTH + `MAC_HEADER_LENGTH) * 8]; + `SEND_ONLY: unwritten_data <= mac_rx_data[511 : (`BTH_LENGTH + `MAC_HEADER_LENGTH) * 8]; + `SEND_LAST: unwritten_data <= mac_rx_data[511 : (`BTH_LENGTH + `MAC_HEADER_LENGTH) * 8]; + `SEND_ONLY_WITH_IMM: unwritten_data <= mac_rx_data[511 : (`BTH_LENGTH + `IMMETH_LENGTH + `MAC_HEADER_LENGTH) * 8]; + `SEND_LAST_WITH_IMM: unwritten_data <= mac_rx_data[511 : (`BTH_LENGTH + `MAC_HEADER_LENGTH) * 8]; + `RDMA_WRITE_FIRST: unwritten_data <= mac_rx_data[511 : (`BTH_LENGTH + `RETH_LENGTH + `MAC_HEADER_LENGTH) * 8]; + `RDMA_WRITE_MIDDLE: unwritten_data <= mac_rx_data[511 : (`BTH_LENGTH + `RETH_LENGTH + `MAC_HEADER_LENGTH) * 8]; + `RDMA_WRITE_LAST: unwritten_data <= mac_rx_data[511 : (`BTH_LENGTH + `RETH_LENGTH + `MAC_HEADER_LENGTH) * 8]; + `RDMA_WRITE_ONLY: unwritten_data <= mac_rx_data[511 : (`BTH_LENGTH + `RETH_LENGTH + `MAC_HEADER_LENGTH) * 8]; + `RDMA_WRITE_LAST_WITH_IMM: unwritten_data <= mac_rx_data[511 : (`BTH_LENGTH + `RETH_LENGTH +`IMMETH_LENGTH + `MAC_HEADER_LENGTH) * 8]; + `RDMA_WRITE_ONLY_WITH_IMM: unwritten_data <= mac_rx_data[511 : (`BTH_LENGTH + `RETH_LENGTH +`IMMETH_LENGTH + `MAC_HEADER_LENGTH) * 8]; + `RDMA_READ_REQUEST_FIRST: unwritten_data <= mac_rx_data[511 : (`BTH_LENGTH + `RETH_LENGTH + `MAC_HEADER_LENGTH) * 8]; + `RDMA_READ_REQUEST_MIDDLE: unwritten_data <= mac_rx_data[511 : (`BTH_LENGTH + `RETH_LENGTH + `MAC_HEADER_LENGTH) * 8]; + `RDMA_READ_REQUEST_LAST: unwritten_data <= mac_rx_data[511 : (`BTH_LENGTH + `RETH_LENGTH + `MAC_HEADER_LENGTH) * 8]; + `RDMA_READ_REQUEST_ONLY: unwritten_data <= mac_rx_data[511 : (`BTH_LENGTH + `RETH_LENGTH + `MAC_HEADER_LENGTH) * 8]; + `RDMA_READ_RESPONSE_FIRST: unwritten_data <= mac_rx_data[511 : (`BTH_LENGTH + `MAC_HEADER_LENGTH) * 8]; + `RDMA_READ_RESPONSE_MIDDLE: unwritten_data <= mac_rx_data[511 : (`BTH_LENGTH + `MAC_HEADER_LENGTH) * 8]; + `RDMA_READ_RESPONSE_LAST: unwritten_data <= mac_rx_data[511 : (`BTH_LENGTH + `MAC_HEADER_LENGTH) * 8]; + `RDMA_READ_RESPONSE_ONLY: unwritten_data <= mac_rx_data[511 : (`BTH_LENGTH + `MAC_HEADER_LENGTH) * 8]; + `ACKNOWLEDGE: unwritten_data <= mac_rx_data[511 : (`BTH_LENGTH + `AETH_LENGTH + `MAC_HEADER_LENGTH) * 8]; + default: unwritten_data <= 'd0; + endcase + end + else if(cur_state == BUFFER_PAYLOAD_s) begin + if(payload_left_length == 0) begin + unwritten_data <= insert_req_ready ? 'd0 : unwritten_data; + end + else if(payload_left_length > 0 && mac_rx_valid && insert_req_ready) begin + if(payload_left_length + unwritten_len <= 64) begin + unwritten_data <= 'd0; + end + else if(payload_left_length > 64 || payload_left_length + unwritten_len > 64) begin + case(unwritten_len) + 0 : unwritten_data <= 'd0; + 1 : unwritten_data <= {{((64 - 1 ) * 8){1'b0}}, mac_rx_data[511 : (64 - 1 ) * 8]}; + 2 : unwritten_data <= {{((64 - 2 ) * 8){1'b0}}, mac_rx_data[511 : (64 - 2 ) * 8]}; + 3 : unwritten_data <= {{((64 - 3 ) * 8){1'b0}}, mac_rx_data[511 : (64 - 3 ) * 8]}; + 4 : unwritten_data <= {{((64 - 4 ) * 8){1'b0}}, mac_rx_data[511 : (64 - 4 ) * 8]}; + 5 : unwritten_data <= {{((64 - 5 ) * 8){1'b0}}, mac_rx_data[511 : (64 - 5 ) * 8]}; + 6 : unwritten_data <= {{((64 - 6 ) * 8){1'b0}}, mac_rx_data[511 : (64 - 6 ) * 8]}; + 7 : unwritten_data <= {{((64 - 7 ) * 8){1'b0}}, mac_rx_data[511 : (64 - 7 ) * 8]}; + 8 : unwritten_data <= {{((64 - 8 ) * 8){1'b0}}, mac_rx_data[511 : (64 - 8 ) * 8]}; + 9 : unwritten_data <= {{((64 - 9 ) * 8){1'b0}}, mac_rx_data[511 : (64 - 9 ) * 8]}; + 10 : unwritten_data <= {{((64 - 10) * 8){1'b0}}, mac_rx_data[511 : (64 - 10) * 8]}; + 11 : unwritten_data <= {{((64 - 11) * 8){1'b0}}, mac_rx_data[511 : (64 - 11) * 8]}; + 12 : unwritten_data <= {{((64 - 12) * 8){1'b0}}, mac_rx_data[511 : (64 - 12) * 8]}; + 13 : unwritten_data <= {{((64 - 13) * 8){1'b0}}, mac_rx_data[511 : (64 - 13) * 8]}; + 14 : unwritten_data <= {{((64 - 14) * 8){1'b0}}, mac_rx_data[511 : (64 - 14) * 8]}; + 15 : unwritten_data <= {{((64 - 15) * 8){1'b0}}, mac_rx_data[511 : (64 - 15) * 8]}; + 16 : unwritten_data <= {{((64 - 16) * 8){1'b0}}, mac_rx_data[511 : (64 - 16) * 8]}; + 17 : unwritten_data <= {{((64 - 17) * 8){1'b0}}, mac_rx_data[511 : (64 - 17) * 8]}; + 18 : unwritten_data <= {{((64 - 18) * 8){1'b0}}, mac_rx_data[511 : (64 - 18) * 8]}; + 19 : unwritten_data <= {{((64 - 19) * 8){1'b0}}, mac_rx_data[511 : (64 - 19) * 8]}; + 20 : unwritten_data <= {{((64 - 20) * 8){1'b0}}, mac_rx_data[511 : (64 - 20) * 8]}; + 21 : unwritten_data <= {{((64 - 21) * 8){1'b0}}, mac_rx_data[511 : (64 - 21) * 8]}; + 22 : unwritten_data <= {{((64 - 22) * 8){1'b0}}, mac_rx_data[511 : (64 - 22) * 8]}; + 23 : unwritten_data <= {{((64 - 23) * 8){1'b0}}, mac_rx_data[511 : (64 - 23) * 8]}; + 24 : unwritten_data <= {{((64 - 24) * 8){1'b0}}, mac_rx_data[511 : (64 - 24) * 8]}; + 25 : unwritten_data <= {{((64 - 25) * 8){1'b0}}, mac_rx_data[511 : (64 - 25) * 8]}; + 26 : unwritten_data <= {{((64 - 26) * 8){1'b0}}, mac_rx_data[511 : (64 - 26) * 8]}; + 27 : unwritten_data <= {{((64 - 27) * 8){1'b0}}, mac_rx_data[511 : (64 - 27) * 8]}; + 28 : unwritten_data <= {{((64 - 28) * 8){1'b0}}, mac_rx_data[511 : (64 - 28) * 8]}; + 29 : unwritten_data <= {{((64 - 29) * 8){1'b0}}, mac_rx_data[511 : (64 - 29) * 8]}; + 30 : unwritten_data <= {{((64 - 30) * 8){1'b0}}, mac_rx_data[511 : (64 - 30) * 8]}; + 31 : unwritten_data <= {{((64 - 31) * 8){1'b0}}, mac_rx_data[511 : (64 - 31) * 8]}; + 32 : unwritten_data <= {{((64 - 32) * 8){1'b0}}, mac_rx_data[511 : (64 - 32) * 8]}; + 33 : unwritten_data <= {{((64 - 33) * 8){1'b0}}, mac_rx_data[511 : (64 - 33) * 8]}; + 34 : unwritten_data <= {{((64 - 34) * 8){1'b0}}, mac_rx_data[511 : (64 - 34) * 8]}; + 35 : unwritten_data <= {{((64 - 35) * 8){1'b0}}, mac_rx_data[511 : (64 - 35) * 8]}; + 36 : unwritten_data <= {{((64 - 36) * 8){1'b0}}, mac_rx_data[511 : (64 - 36) * 8]}; + 37 : unwritten_data <= {{((64 - 37) * 8){1'b0}}, mac_rx_data[511 : (64 - 37) * 8]}; + 38 : unwritten_data <= {{((64 - 38) * 8){1'b0}}, mac_rx_data[511 : (64 - 38) * 8]}; + 39 : unwritten_data <= {{((64 - 39) * 8){1'b0}}, mac_rx_data[511 : (64 - 39) * 8]}; + 40 : unwritten_data <= {{((64 - 40) * 8){1'b0}}, mac_rx_data[511 : (64 - 40) * 8]}; + 41 : unwritten_data <= {{((64 - 41) * 8){1'b0}}, mac_rx_data[511 : (64 - 41) * 8]}; + 42 : unwritten_data <= {{((64 - 42) * 8){1'b0}}, mac_rx_data[511 : (64 - 42) * 8]}; + 43 : unwritten_data <= {{((64 - 43) * 8){1'b0}}, mac_rx_data[511 : (64 - 43) * 8]}; + 44 : unwritten_data <= {{((64 - 44) * 8){1'b0}}, mac_rx_data[511 : (64 - 44) * 8]}; + 45 : unwritten_data <= {{((64 - 45) * 8){1'b0}}, mac_rx_data[511 : (64 - 45) * 8]}; + 46 : unwritten_data <= {{((64 - 46) * 8){1'b0}}, mac_rx_data[511 : (64 - 46) * 8]}; + 47 : unwritten_data <= {{((64 - 47) * 8){1'b0}}, mac_rx_data[511 : (64 - 47) * 8]}; + 48 : unwritten_data <= {{((64 - 48) * 8){1'b0}}, mac_rx_data[511 : (64 - 48) * 8]}; + 49 : unwritten_data <= {{((64 - 49) * 8){1'b0}}, mac_rx_data[511 : (64 - 49) * 8]}; + 50 : unwritten_data <= {{((64 - 50) * 8){1'b0}}, mac_rx_data[511 : (64 - 50) * 8]}; + 51 : unwritten_data <= {{((64 - 51) * 8){1'b0}}, mac_rx_data[511 : (64 - 51) * 8]}; + 52 : unwritten_data <= {{((64 - 52) * 8){1'b0}}, mac_rx_data[511 : (64 - 52) * 8]}; + 53 : unwritten_data <= {{((64 - 53) * 8){1'b0}}, mac_rx_data[511 : (64 - 53) * 8]}; + 54 : unwritten_data <= {{((64 - 54) * 8){1'b0}}, mac_rx_data[511 : (64 - 54) * 8]}; + 55 : unwritten_data <= {{((64 - 55) * 8){1'b0}}, mac_rx_data[511 : (64 - 55) * 8]}; + 56 : unwritten_data <= {{((64 - 56) * 8){1'b0}}, mac_rx_data[511 : (64 - 56) * 8]}; + 57 : unwritten_data <= {{((64 - 57) * 8){1'b0}}, mac_rx_data[511 : (64 - 57) * 8]}; + 58 : unwritten_data <= {{((64 - 58) * 8){1'b0}}, mac_rx_data[511 : (64 - 58) * 8]}; + 59 : unwritten_data <= {{((64 - 59) * 8){1'b0}}, mac_rx_data[511 : (64 - 59) * 8]}; + 60 : unwritten_data <= {{((64 - 60) * 8){1'b0}}, mac_rx_data[511 : (64 - 60) * 8]}; + 61 : unwritten_data <= {{((64 - 61) * 8){1'b0}}, mac_rx_data[511 : (64 - 61) * 8]}; + 62 : unwritten_data <= {{((64 - 62) * 8){1'b0}}, mac_rx_data[511 : (64 - 62) * 8]}; + 63 : unwritten_data <= {{((64 - 63) * 8){1'b0}}, mac_rx_data[511 : (64 - 63) * 8]}; + default: unwritten_data <= unwritten_data; + endcase + end + else if(payload_left_length + unwritten_len <= 64) begin + unwritten_data <= 'd0; + end + else begin + unwritten_data <= unwritten_data; + end + end + else begin + unwritten_data <= unwritten_data; + end + end + else begin + unwritten_data <= unwritten_data; + end +end + +//-- insert_req_valid -- +//-- insert_req_start -- +//-- insert_req_last -- +//-- insert_req_head -- +assign insert_req_valid = (cur_state == BUFFER_PAYLOAD_s && payload_left_length == 0) ? 'd1 : + (cur_state == BUFFER_PAYLOAD_s && payload_left_length > 0) ? 'd1 : 'd0; +assign insert_req_start = (cur_state == BUFFER_PAYLOAD_s && (insert_count == 'd1)) ? 'd1 : 'd0; +assign insert_req_last = (cur_state == BUFFER_PAYLOAD_s && payload_left_length == 0) ? 'd1 : + (cur_state == BUFFER_PAYLOAD_s && payload_left_length > 0 && payload_left_length + unwritten_len <= 64) ? 'd1 : 'd0; +assign insert_req_head = (cur_state == BUFFER_PAYLOAD_s && insert_req_start) ? (mac_rx_data[`PAYLOAD_LENGTH_OFFSET] % 64 ? (mac_rx_data[`PAYLOAD_LENGTH_OFFSET] >> 6) + 1 : mac_rx_data[`PAYLOAD_LENGTH_OFFSET] >> 6) : 'd0; + +//-- insert_count -- +always @(posedge clk or posedge rst) begin + if (rst) begin + insert_count <= 'd0; + end + else if (cur_state == IDLE_s && next_state == BUFFER_PAYLOAD_s) begin + insert_count <= 'd1; + end + else if(cur_state == BUFFER_PAYLOAD_s && insert_req_valid && insert_req_ready) begin + insert_count <= insert_count + 'd1; + end + else begin + insert_count <= insert_count; + end +end + +//-- insert_req_data -- +always @(*) begin + if (rst) begin + insert_req_data = 'd0; + end + else if(cur_state == BUFFER_PAYLOAD_s) begin + if(payload_left_length == 0) begin + insert_req_data = unwritten_data; + end + else if(payload_left_length > 64 || payload_left_length + unwritten_len > 64) begin + case(unwritten_len) + 0 : insert_req_data = mac_rx_data; + 1 : insert_req_data = {mac_rx_data[(64 - 1 ) * 8 - 1 : 0], unwritten_data[1 * 8 - 1 : 0]}; + 2 : insert_req_data = {mac_rx_data[(64 - 2 ) * 8 - 1 : 0], unwritten_data[2 * 8 - 1 : 0]}; + 3 : insert_req_data = {mac_rx_data[(64 - 3 ) * 8 - 1 : 0], unwritten_data[3 * 8 - 1 : 0]}; + 4 : insert_req_data = {mac_rx_data[(64 - 4 ) * 8 - 1 : 0], unwritten_data[4 * 8 - 1 : 0]}; + 5 : insert_req_data = {mac_rx_data[(64 - 5 ) * 8 - 1 : 0], unwritten_data[5 * 8 - 1 : 0]}; + 6 : insert_req_data = {mac_rx_data[(64 - 6 ) * 8 - 1 : 0], unwritten_data[6 * 8 - 1 : 0]}; + 7 : insert_req_data = {mac_rx_data[(64 - 7 ) * 8 - 1 : 0], unwritten_data[7 * 8 - 1 : 0]}; + 8 : insert_req_data = {mac_rx_data[(64 - 8 ) * 8 - 1 : 0], unwritten_data[8 * 8 - 1 : 0]}; + 9 : insert_req_data = {mac_rx_data[(64 - 9 ) * 8 - 1 : 0], unwritten_data[9 * 8 - 1 : 0]}; + 10 : insert_req_data = {mac_rx_data[(64 - 10) * 8 - 1 : 0], unwritten_data[10 * 8 - 1 : 0]}; + 11 : insert_req_data = {mac_rx_data[(64 - 11) * 8 - 1 : 0], unwritten_data[11 * 8 - 1 : 0]}; + 12 : insert_req_data = {mac_rx_data[(64 - 12) * 8 - 1 : 0], unwritten_data[12 * 8 - 1 : 0]}; + 13 : insert_req_data = {mac_rx_data[(64 - 13) * 8 - 1 : 0], unwritten_data[13 * 8 - 1 : 0]}; + 14 : insert_req_data = {mac_rx_data[(64 - 14) * 8 - 1 : 0], unwritten_data[14 * 8 - 1 : 0]}; + 15 : insert_req_data = {mac_rx_data[(64 - 15) * 8 - 1 : 0], unwritten_data[15 * 8 - 1 : 0]}; + 16 : insert_req_data = {mac_rx_data[(64 - 16) * 8 - 1 : 0], unwritten_data[16 * 8 - 1 : 0]}; + 17 : insert_req_data = {mac_rx_data[(64 - 17) * 8 - 1 : 0], unwritten_data[17 * 8 - 1 : 0]}; + 18 : insert_req_data = {mac_rx_data[(64 - 18) * 8 - 1 : 0], unwritten_data[18 * 8 - 1 : 0]}; + 19 : insert_req_data = {mac_rx_data[(64 - 19) * 8 - 1 : 0], unwritten_data[19 * 8 - 1 : 0]}; + 20 : insert_req_data = {mac_rx_data[(64 - 20) * 8 - 1 : 0], unwritten_data[20 * 8 - 1 : 0]}; + 21 : insert_req_data = {mac_rx_data[(64 - 21) * 8 - 1 : 0], unwritten_data[21 * 8 - 1 : 0]}; + 22 : insert_req_data = {mac_rx_data[(64 - 22) * 8 - 1 : 0], unwritten_data[22 * 8 - 1 : 0]}; + 23 : insert_req_data = {mac_rx_data[(64 - 23) * 8 - 1 : 0], unwritten_data[23 * 8 - 1 : 0]}; + 24 : insert_req_data = {mac_rx_data[(64 - 24) * 8 - 1 : 0], unwritten_data[24 * 8 - 1 : 0]}; + 25 : insert_req_data = {mac_rx_data[(64 - 25) * 8 - 1 : 0], unwritten_data[25 * 8 - 1 : 0]}; + 26 : insert_req_data = {mac_rx_data[(64 - 26) * 8 - 1 : 0], unwritten_data[26 * 8 - 1 : 0]}; + 27 : insert_req_data = {mac_rx_data[(64 - 27) * 8 - 1 : 0], unwritten_data[27 * 8 - 1 : 0]}; + 28 : insert_req_data = {mac_rx_data[(64 - 28) * 8 - 1 : 0], unwritten_data[28 * 8 - 1 : 0]}; + 29 : insert_req_data = {mac_rx_data[(64 - 29) * 8 - 1 : 0], unwritten_data[29 * 8 - 1 : 0]}; + 30 : insert_req_data = {mac_rx_data[(64 - 30) * 8 - 1 : 0], unwritten_data[30 * 8 - 1 : 0]}; + 31 : insert_req_data = {mac_rx_data[(64 - 31) * 8 - 1 : 0], unwritten_data[31 * 8 - 1 : 0]}; + 32 : insert_req_data = {mac_rx_data[(64 - 32) * 8 - 1 : 0], unwritten_data[32 * 8 - 1 : 0]}; + 33 : insert_req_data = {mac_rx_data[(64 - 33) * 8 - 1 : 0], unwritten_data[33 * 8 - 1 : 0]}; + 34 : insert_req_data = {mac_rx_data[(64 - 34) * 8 - 1 : 0], unwritten_data[34 * 8 - 1 : 0]}; + 35 : insert_req_data = {mac_rx_data[(64 - 35) * 8 - 1 : 0], unwritten_data[35 * 8 - 1 : 0]}; + 36 : insert_req_data = {mac_rx_data[(64 - 36) * 8 - 1 : 0], unwritten_data[36 * 8 - 1 : 0]}; + 37 : insert_req_data = {mac_rx_data[(64 - 37) * 8 - 1 : 0], unwritten_data[37 * 8 - 1 : 0]}; + 38 : insert_req_data = {mac_rx_data[(64 - 38) * 8 - 1 : 0], unwritten_data[38 * 8 - 1 : 0]}; + 39 : insert_req_data = {mac_rx_data[(64 - 39) * 8 - 1 : 0], unwritten_data[39 * 8 - 1 : 0]}; + 40 : insert_req_data = {mac_rx_data[(64 - 40) * 8 - 1 : 0], unwritten_data[40 * 8 - 1 : 0]}; + 41 : insert_req_data = {mac_rx_data[(64 - 41) * 8 - 1 : 0], unwritten_data[41 * 8 - 1 : 0]}; + 42 : insert_req_data = {mac_rx_data[(64 - 42) * 8 - 1 : 0], unwritten_data[42 * 8 - 1 : 0]}; + 43 : insert_req_data = {mac_rx_data[(64 - 43) * 8 - 1 : 0], unwritten_data[43 * 8 - 1 : 0]}; + 44 : insert_req_data = {mac_rx_data[(64 - 44) * 8 - 1 : 0], unwritten_data[44 * 8 - 1 : 0]}; + 45 : insert_req_data = {mac_rx_data[(64 - 45) * 8 - 1 : 0], unwritten_data[45 * 8 - 1 : 0]}; + 46 : insert_req_data = {mac_rx_data[(64 - 46) * 8 - 1 : 0], unwritten_data[46 * 8 - 1 : 0]}; + 47 : insert_req_data = {mac_rx_data[(64 - 47) * 8 - 1 : 0], unwritten_data[47 * 8 - 1 : 0]}; + 48 : insert_req_data = {mac_rx_data[(64 - 48) * 8 - 1 : 0], unwritten_data[48 * 8 - 1 : 0]}; + 49 : insert_req_data = {mac_rx_data[(64 - 49) * 8 - 1 : 0], unwritten_data[49 * 8 - 1 : 0]}; + 50 : insert_req_data = {mac_rx_data[(64 - 50) * 8 - 1 : 0], unwritten_data[50 * 8 - 1 : 0]}; + 51 : insert_req_data = {mac_rx_data[(64 - 51) * 8 - 1 : 0], unwritten_data[51 * 8 - 1 : 0]}; + 52 : insert_req_data = {mac_rx_data[(64 - 52) * 8 - 1 : 0], unwritten_data[52 * 8 - 1 : 0]}; + 53 : insert_req_data = {mac_rx_data[(64 - 53) * 8 - 1 : 0], unwritten_data[53 * 8 - 1 : 0]}; + 54 : insert_req_data = {mac_rx_data[(64 - 54) * 8 - 1 : 0], unwritten_data[54 * 8 - 1 : 0]}; + 55 : insert_req_data = {mac_rx_data[(64 - 55) * 8 - 1 : 0], unwritten_data[55 * 8 - 1 : 0]}; + 56 : insert_req_data = {mac_rx_data[(64 - 56) * 8 - 1 : 0], unwritten_data[56 * 8 - 1 : 0]}; + 57 : insert_req_data = {mac_rx_data[(64 - 57) * 8 - 1 : 0], unwritten_data[57 * 8 - 1 : 0]}; + 58 : insert_req_data = {mac_rx_data[(64 - 58) * 8 - 1 : 0], unwritten_data[58 * 8 - 1 : 0]}; + 59 : insert_req_data = {mac_rx_data[(64 - 59) * 8 - 1 : 0], unwritten_data[59 * 8 - 1 : 0]}; + 60 : insert_req_data = {mac_rx_data[(64 - 60) * 8 - 1 : 0], unwritten_data[60 * 8 - 1 : 0]}; + 61 : insert_req_data = {mac_rx_data[(64 - 61) * 8 - 1 : 0], unwritten_data[61 * 8 - 1 : 0]}; + 62 : insert_req_data = {mac_rx_data[(64 - 62) * 8 - 1 : 0], unwritten_data[62 * 8 - 1 : 0]}; + 63 : insert_req_data = {mac_rx_data[(64 - 63) * 8 - 1 : 0], unwritten_data[63 * 8 - 1 : 0]}; + default: insert_req_data = 'd0; + endcase + end + else if(payload_left_length + unwritten_len <= 64) begin + case(unwritten_len) + 0 : insert_req_data = mac_rx_data; + 1 : insert_req_data = {mac_rx_data[(64 - 1 ) * 8 - 1 : 0], unwritten_data[1 * 8 - 1 : 0]}; + 2 : insert_req_data = {mac_rx_data[(64 - 2 ) * 8 - 1 : 0], unwritten_data[2 * 8 - 1 : 0]}; + 3 : insert_req_data = {mac_rx_data[(64 - 3 ) * 8 - 1 : 0], unwritten_data[3 * 8 - 1 : 0]}; + 4 : insert_req_data = {mac_rx_data[(64 - 4 ) * 8 - 1 : 0], unwritten_data[4 * 8 - 1 : 0]}; + 5 : insert_req_data = {mac_rx_data[(64 - 5 ) * 8 - 1 : 0], unwritten_data[5 * 8 - 1 : 0]}; + 6 : insert_req_data = {mac_rx_data[(64 - 6 ) * 8 - 1 : 0], unwritten_data[6 * 8 - 1 : 0]}; + 7 : insert_req_data = {mac_rx_data[(64 - 7 ) * 8 - 1 : 0], unwritten_data[7 * 8 - 1 : 0]}; + 8 : insert_req_data = {mac_rx_data[(64 - 8 ) * 8 - 1 : 0], unwritten_data[8 * 8 - 1 : 0]}; + 9 : insert_req_data = {mac_rx_data[(64 - 9 ) * 8 - 1 : 0], unwritten_data[9 * 8 - 1 : 0]}; + 10 : insert_req_data = {mac_rx_data[(64 - 10) * 8 - 1 : 0], unwritten_data[10 * 8 - 1 : 0]}; + 11 : insert_req_data = {mac_rx_data[(64 - 11) * 8 - 1 : 0], unwritten_data[11 * 8 - 1 : 0]}; + 12 : insert_req_data = {mac_rx_data[(64 - 12) * 8 - 1 : 0], unwritten_data[12 * 8 - 1 : 0]}; + 13 : insert_req_data = {mac_rx_data[(64 - 13) * 8 - 1 : 0], unwritten_data[13 * 8 - 1 : 0]}; + 14 : insert_req_data = {mac_rx_data[(64 - 14) * 8 - 1 : 0], unwritten_data[14 * 8 - 1 : 0]}; + 15 : insert_req_data = {mac_rx_data[(64 - 15) * 8 - 1 : 0], unwritten_data[15 * 8 - 1 : 0]}; + 16 : insert_req_data = {mac_rx_data[(64 - 16) * 8 - 1 : 0], unwritten_data[16 * 8 - 1 : 0]}; + 17 : insert_req_data = {mac_rx_data[(64 - 17) * 8 - 1 : 0], unwritten_data[17 * 8 - 1 : 0]}; + 18 : insert_req_data = {mac_rx_data[(64 - 18) * 8 - 1 : 0], unwritten_data[18 * 8 - 1 : 0]}; + 19 : insert_req_data = {mac_rx_data[(64 - 19) * 8 - 1 : 0], unwritten_data[19 * 8 - 1 : 0]}; + 20 : insert_req_data = {mac_rx_data[(64 - 20) * 8 - 1 : 0], unwritten_data[20 * 8 - 1 : 0]}; + 21 : insert_req_data = {mac_rx_data[(64 - 21) * 8 - 1 : 0], unwritten_data[21 * 8 - 1 : 0]}; + 22 : insert_req_data = {mac_rx_data[(64 - 22) * 8 - 1 : 0], unwritten_data[22 * 8 - 1 : 0]}; + 23 : insert_req_data = {mac_rx_data[(64 - 23) * 8 - 1 : 0], unwritten_data[23 * 8 - 1 : 0]}; + 24 : insert_req_data = {mac_rx_data[(64 - 24) * 8 - 1 : 0], unwritten_data[24 * 8 - 1 : 0]}; + 25 : insert_req_data = {mac_rx_data[(64 - 25) * 8 - 1 : 0], unwritten_data[25 * 8 - 1 : 0]}; + 26 : insert_req_data = {mac_rx_data[(64 - 26) * 8 - 1 : 0], unwritten_data[26 * 8 - 1 : 0]}; + 27 : insert_req_data = {mac_rx_data[(64 - 27) * 8 - 1 : 0], unwritten_data[27 * 8 - 1 : 0]}; + 28 : insert_req_data = {mac_rx_data[(64 - 28) * 8 - 1 : 0], unwritten_data[28 * 8 - 1 : 0]}; + 29 : insert_req_data = {mac_rx_data[(64 - 29) * 8 - 1 : 0], unwritten_data[29 * 8 - 1 : 0]}; + 30 : insert_req_data = {mac_rx_data[(64 - 30) * 8 - 1 : 0], unwritten_data[30 * 8 - 1 : 0]}; + 31 : insert_req_data = {mac_rx_data[(64 - 31) * 8 - 1 : 0], unwritten_data[31 * 8 - 1 : 0]}; + 32 : insert_req_data = {mac_rx_data[(64 - 32) * 8 - 1 : 0], unwritten_data[32 * 8 - 1 : 0]}; + 33 : insert_req_data = {mac_rx_data[(64 - 33) * 8 - 1 : 0], unwritten_data[33 * 8 - 1 : 0]}; + 34 : insert_req_data = {mac_rx_data[(64 - 34) * 8 - 1 : 0], unwritten_data[34 * 8 - 1 : 0]}; + 35 : insert_req_data = {mac_rx_data[(64 - 35) * 8 - 1 : 0], unwritten_data[35 * 8 - 1 : 0]}; + 36 : insert_req_data = {mac_rx_data[(64 - 36) * 8 - 1 : 0], unwritten_data[36 * 8 - 1 : 0]}; + 37 : insert_req_data = {mac_rx_data[(64 - 37) * 8 - 1 : 0], unwritten_data[37 * 8 - 1 : 0]}; + 38 : insert_req_data = {mac_rx_data[(64 - 38) * 8 - 1 : 0], unwritten_data[38 * 8 - 1 : 0]}; + 39 : insert_req_data = {mac_rx_data[(64 - 39) * 8 - 1 : 0], unwritten_data[39 * 8 - 1 : 0]}; + 40 : insert_req_data = {mac_rx_data[(64 - 40) * 8 - 1 : 0], unwritten_data[40 * 8 - 1 : 0]}; + 41 : insert_req_data = {mac_rx_data[(64 - 41) * 8 - 1 : 0], unwritten_data[41 * 8 - 1 : 0]}; + 42 : insert_req_data = {mac_rx_data[(64 - 42) * 8 - 1 : 0], unwritten_data[42 * 8 - 1 : 0]}; + 43 : insert_req_data = {mac_rx_data[(64 - 43) * 8 - 1 : 0], unwritten_data[43 * 8 - 1 : 0]}; + 44 : insert_req_data = {mac_rx_data[(64 - 44) * 8 - 1 : 0], unwritten_data[44 * 8 - 1 : 0]}; + 45 : insert_req_data = {mac_rx_data[(64 - 45) * 8 - 1 : 0], unwritten_data[45 * 8 - 1 : 0]}; + 46 : insert_req_data = {mac_rx_data[(64 - 46) * 8 - 1 : 0], unwritten_data[46 * 8 - 1 : 0]}; + 47 : insert_req_data = {mac_rx_data[(64 - 47) * 8 - 1 : 0], unwritten_data[47 * 8 - 1 : 0]}; + 48 : insert_req_data = {mac_rx_data[(64 - 48) * 8 - 1 : 0], unwritten_data[48 * 8 - 1 : 0]}; + 49 : insert_req_data = {mac_rx_data[(64 - 49) * 8 - 1 : 0], unwritten_data[49 * 8 - 1 : 0]}; + 50 : insert_req_data = {mac_rx_data[(64 - 50) * 8 - 1 : 0], unwritten_data[50 * 8 - 1 : 0]}; + 51 : insert_req_data = {mac_rx_data[(64 - 51) * 8 - 1 : 0], unwritten_data[51 * 8 - 1 : 0]}; + 52 : insert_req_data = {mac_rx_data[(64 - 52) * 8 - 1 : 0], unwritten_data[52 * 8 - 1 : 0]}; + 53 : insert_req_data = {mac_rx_data[(64 - 53) * 8 - 1 : 0], unwritten_data[53 * 8 - 1 : 0]}; + 54 : insert_req_data = {mac_rx_data[(64 - 54) * 8 - 1 : 0], unwritten_data[54 * 8 - 1 : 0]}; + 55 : insert_req_data = {mac_rx_data[(64 - 55) * 8 - 1 : 0], unwritten_data[55 * 8 - 1 : 0]}; + 56 : insert_req_data = {mac_rx_data[(64 - 56) * 8 - 1 : 0], unwritten_data[56 * 8 - 1 : 0]}; + 57 : insert_req_data = {mac_rx_data[(64 - 57) * 8 - 1 : 0], unwritten_data[57 * 8 - 1 : 0]}; + 58 : insert_req_data = {mac_rx_data[(64 - 58) * 8 - 1 : 0], unwritten_data[58 * 8 - 1 : 0]}; + 59 : insert_req_data = {mac_rx_data[(64 - 59) * 8 - 1 : 0], unwritten_data[59 * 8 - 1 : 0]}; + 60 : insert_req_data = {mac_rx_data[(64 - 60) * 8 - 1 : 0], unwritten_data[60 * 8 - 1 : 0]}; + 61 : insert_req_data = {mac_rx_data[(64 - 61) * 8 - 1 : 0], unwritten_data[61 * 8 - 1 : 0]}; + 62 : insert_req_data = {mac_rx_data[(64 - 62) * 8 - 1 : 0], unwritten_data[62 * 8 - 1 : 0]}; + 63 : insert_req_data = {mac_rx_data[(64 - 63) * 8 - 1 : 0], unwritten_data[63 * 8 - 1 : 0]}; + default: insert_req_data = 'd0; + endcase + end + else begin + insert_req_data = 'd0; + end + end + else begin + insert_req_data = 'd0; + end +end + +//-- mac_rx_ready -- +assign mac_rx_ready = (cur_state == IDLE_s) ? 'd1 : + (cur_state == BUFFER_PAYLOAD_s && payload_left_length > 0) ? insert_req_ready : 'd0; + +//-- ingress_pkt_valid -- +//-- ingress_pkt_head -- +assign ingress_pkt_valid = (cur_state == GEN_META_s) ? 'd1 : 'd0; +assign ingress_pkt_head = (cur_state == GEN_META_s) ? { + payload_length, payload_start_addr, sip, dip, smac, dmac, + immediate, raddr, rkey, 8'd0, remote_qpn, service_type, opcode, local_qpn + } : 'd0; +/*------------------------------------------- Variables Decode : End ------------------------------------------------*/ + +/*------------------------------------------- Local Macros Undef : Begin --------------------------------------------*/ +`undef DMAC_OFFSET +`undef SMAC_OFFSET + +`undef SRC_QPN_OFFSET +`undef SERVICE_TYPE_OFFSET +`undef OPCODE_OFFSET +`undef DST_QPN_OFFSET +`undef PAYLOAD_LENGTH_OFFSET + +`undef RADDR_OFFSET +`undef RKEY_OFFSET +`undef DMA_LENGTH_OFFSET +/*------------------------------------------- Local Macros Undef : End ----------------------------------------------*/ + + +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Peripherals/MACEncap.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Peripherals/MACEncap.v new file mode 100644 index 0000000000000000000000000000000000000000..f2068271e10a11f642354e469fedac82e8df47df --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Peripherals/MACEncap.v @@ -0,0 +1,628 @@ +/*------------------------------------------- Module Description : Begin ---------------------------------------------- +Name: PacketEncap +Author: YangFan +Function: In NIC/Switch processing pipeline, protocol processing requires frequent appending and removing header. + This module abstracts the append process. +--------------------------------------------- Module Decription : End -----------------------------------------------*/ + +/*------------------------------------------- Timescale Definition : Begin ------------------------------------------*/ +`timescale 1ns / 1ps +/*------------------------------------------- Timescale Definition : End --------------------------------------------*/ + +/*------------------------------------------- Included Files : Begin ------------------------------------------------*/ +`include "common_function_def.vh" +/*------------------------------------------- Included Files : End --------------------------------------------------*/ + +/*------------------------------------------- Local Macros Definition : Begin ---------------------------------------*/ +/*------------------------------------------- Local Macros Definition : End -----------------------------------------*/ + +/*------------------------------------------- Input/Output Definition : Begin ---------------------------------------*/ +module MACEncap +( + input wire clk, + input wire rst, + + input wire egress_pkt_valid, + input wire [`PKT_META_BUS_WIDTH - 1 : 0] egress_pkt_head, + output wire egress_pkt_ready, + + output wire delete_req_valid, + output wire [`MAX_DB_SLOT_NUM_LOG * 2 - 1 : 0] delete_req_head, + input wire delete_req_ready, + + input wire delete_resp_valid, + input wire delete_resp_start, + input wire delete_resp_last, + input wire [`PACKET_BUFFER_SLOT_WIDTH - 1 : 0] delete_resp_data, + output wire delete_resp_ready, + + output wire mac_tx_valid, + input wire mac_tx_ready, + output wire mac_tx_start, + output wire mac_tx_last, + output wire [`MAC_KEEP_WIDTH - 1 : 0] mac_tx_keep, + output wire mac_tx_user, + output reg [`MAC_DATA_WIDTH - 1 : 0] mac_tx_data +); +/*------------------------------------------- Input/Output Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Macros Definition : Begin ---------------------------------------*/ +`define LOCAL_QPN_OFFSET 23:0 +`define OPCODE_OFFSET 28:24 +`define SERVICE_TYPE_OFFSET 31:29 +`define REMOTE_QPN_OFFSET 55:32 +`define RKEY_OFFSET 95:64 +`define RADDR_OFFSET 159:96 +`define IMMEDIATE_OFFSET 191:160 +`define DMAC_OFFSET 239:192 +`define SMAC_OFFSET 287:240 +`define DIP_OFFSET 319:288 +`define SIP_OFFSET 351:320 +`define PAYLOAD_ADDR_OFFSET 367:352 +`define PAYLOAD_LENGTH_OFFSET 383:368 +/*------------------------------------------- Local Macros Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Variables Definition : Begin ------------------------------------*/ +wire [`MAC_HEADER_LENGTH * 8 - 1 : 0] mac_header; +wire [`BTH_LENGTH * 8 - 1 : 0] bth; +wire [`RETH_LENGTH * 8 - 1 : 0] reth; +wire [`IMMETH_LENGTH * 8 - 1 : 0] immeth; +wire [`AETH_LENGTH * 8 - 1 : 0] aeth; + +wire [23:0] bth_local_qpn; +wire [23:0] bth_dst_qpn; +wire [2:0] bth_service_type; +wire [4:0] bth_opcode; +wire [15:0] bth_pkt_length; + +wire [63:0] reth_raddr; +wire [31:0] reth_rkey; +wire [31:0] reth_dma_length; + +wire [23:0] aeth_msn; +wire [7:0] aeth_syndrome; + +reg [`PKT_META_BUS_WIDTH - 1 : 0] pkt_header_bus; + +reg [15:0] payload_left_length; +reg [15:0] unwritten_len; +reg [511:0] unwritten_data; +/*------------------------------------------- Local Variables Definition : End --------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : Begin ---------------------------------------*/ +/*------------------------------------------- Submodules Instatiation : End -----------------------------------------*/ + +/*------------------------------------------- State Machine Definition : Begin --------------------------------------*/ +reg [2:0] cur_state; +reg [2:0] next_state; + +parameter [2:0] IDLE_s = 3'd1, + DEL_s = 3'd2, + ZERO_PAYLOAD_ENCAP_s = 3'd3, + NON_ZERO_PAYLOAD_ENCAP_s = 3'd4; + + +always @(posedge clk or posedge rst) begin + if (rst) begin + cur_state <= IDLE_s; + end + else begin + cur_state <= next_state; + end +end + +always @(*) begin + case(cur_state) + IDLE_s: if(egress_pkt_valid) begin + if( egress_pkt_head[`OPCODE_OFFSET] == `RDMA_READ_REQUEST_FIRST || + egress_pkt_head[`OPCODE_OFFSET] == `RDMA_READ_REQUEST_MIDDLE || + egress_pkt_head[`OPCODE_OFFSET] == `RDMA_READ_REQUEST_LAST || + egress_pkt_head[`OPCODE_OFFSET] == `RDMA_READ_REQUEST_ONLY || egress_pkt_head[`OPCODE_OFFSET] == `ACKNOWLEDGE) begin + next_state = ZERO_PAYLOAD_ENCAP_s; + end + else begin + next_state = DEL_s; + end + end + else begin + next_state = IDLE_s; + end + DEL_s: if(delete_req_valid && delete_req_ready) begin + next_state = NON_ZERO_PAYLOAD_ENCAP_s; + end + else begin + next_state = ZERO_PAYLOAD_ENCAP_s; + end + ZERO_PAYLOAD_ENCAP_s: if(mac_tx_valid && mac_tx_ready) begin //Only one cycle + next_state = IDLE_s; + end + else begin + next_state = ZERO_PAYLOAD_ENCAP_s; + end + NON_ZERO_PAYLOAD_ENCAP_s: if(payload_left_length + unwritten_len > 64) begin //Still need more cycles + next_state = NON_ZERO_PAYLOAD_ENCAP_s; + end + else if(payload_left_length > 0 && delete_resp_valid && mac_tx_ready) begin + next_state = IDLE_s; + end + else if(payload_left_length == 0 && mac_tx_ready) begin + next_state = IDLE_s; + end + else begin + next_state = NON_ZERO_PAYLOAD_ENCAP_s; + end + default: next_state = IDLE_s; + endcase +end +/*------------------------------------------- State Machine Definition : End ----------------------------------------*/ + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ +//-- pkt_header_bus -- +always @(posedge clk or posedge rst) begin + if (rst) begin + pkt_header_bus <= 'd0; + end + else if (cur_state == IDLE_s && egress_pkt_valid) begin + pkt_header_bus <= egress_pkt_head; + end + else begin + pkt_header_bus <= pkt_header_bus; + end +end + +//-- bth -- +assign bth = {bth_pkt_length, bth_dst_qpn, bth_opcode, bth_service_type, bth_local_qpn}; + +//-- reth -- +assign reth = {reth_dma_length, reth_rkey, reth_raddr}; + +//-- immeth -- +assign immeth = (cur_state == IDLE_s) ? egress_pkt_head[`IMMEDIATE_OFFSET] : pkt_header_bus[`IMMEDIATE_OFFSET]; + +//-- aeth -- +assign aeth = 'd0; + +//-- bth_local_qpn -- +//-- bth_dst_qpn -- +//-- bth_service_type -- +//-- bth_opcode -- +//-- bth_pkt_length -- +assign bth_local_qpn = (cur_state == IDLE_s) ? egress_pkt_head[`LOCAL_QPN_OFFSET] : pkt_header_bus[`LOCAL_QPN_OFFSET]; +assign bth_dst_qpn = (cur_state == IDLE_s) ? egress_pkt_head[`REMOTE_QPN_OFFSET] : pkt_header_bus[`REMOTE_QPN_OFFSET]; +assign bth_service_type = (cur_state == IDLE_s) ? egress_pkt_head[`SERVICE_TYPE_OFFSET] : pkt_header_bus[`SERVICE_TYPE_OFFSET]; +assign bth_opcode = (cur_state == IDLE_s) ? egress_pkt_head[`OPCODE_OFFSET] : pkt_header_bus[`OPCODE_OFFSET]; +assign bth_pkt_length = (cur_state == IDLE_s) ? egress_pkt_head[`PAYLOAD_LENGTH_OFFSET] : pkt_header_bus[`PAYLOAD_LENGTH_OFFSET]; + +//-- reth_raddr -- +//-- reth_rkey -- +//-- reth_dma_length -- +assign reth_raddr = (cur_state == IDLE_s) ? egress_pkt_head[`RADDR_OFFSET] : pkt_header_bus[`RADDR_OFFSET]; +assign reth_rkey = (cur_state == IDLE_s) ? egress_pkt_head[`RKEY_OFFSET] : pkt_header_bus[`RKEY_OFFSET]; +assign reth_dma_length = (cur_state == IDLE_s) ? egress_pkt_head[`PAYLOAD_LENGTH_OFFSET] : pkt_header_bus[`PAYLOAD_LENGTH_OFFSET]; + +//-- mac_header -- +// assign mac_header = (cur_state == IDLE_s) ? {16'h0008, egress_pkt_head[`SMAC_OFFSET], egress_pkt_head[`DMAC_OFFSET]} : +// {16'h0800, pkt_header_bus[`SMAC_OFFSET], pkt_header_bus[`DMAC_OFFSET]}; + +assign mac_header = (cur_state == IDLE_s) ? {16'h0008, 48'haabbccddeeff, 48'h112233445566} : + {16'h0008, 48'haabbccddeeff, 48'h112233445566}; + +//-- payload_left_length -- +always @(posedge clk or posedge rst) begin + if (rst) begin + payload_left_length <= 'd0; + end + else if (cur_state == IDLE_s && egress_pkt_valid) begin + payload_left_length <= egress_pkt_head[`PAYLOAD_LENGTH_OFFSET]; + end + else if(cur_state == ZERO_PAYLOAD_ENCAP_s) begin + payload_left_length <= 'd0; + end + else if(cur_state == NON_ZERO_PAYLOAD_ENCAP_s) begin + if(payload_left_length == 0) begin //Only unwritten_len left + payload_left_length <= 'd0; + end + else if(payload_left_length > 0 && delete_resp_valid && mac_tx_ready) begin + payload_left_length <= payload_left_length > 64 ? payload_left_length - 'd64 : 'd0; + end + else begin + payload_left_length <= payload_left_length; + end + end + else begin + payload_left_length <= payload_left_length; + end +end + +//-- unwritten_len -- +always @(posedge clk or posedge rst) begin + if (rst) begin + unwritten_len <= 'd0; + end + else if (cur_state == IDLE_s && egress_pkt_valid) begin + case(egress_pkt_head[`OPCODE_OFFSET]) + `SEND_FIRST: unwritten_len <= `BTH_LENGTH + `MAC_HEADER_LENGTH; + `SEND_MIDDLE: unwritten_len <= `BTH_LENGTH + `MAC_HEADER_LENGTH; + `SEND_ONLY: unwritten_len <= `BTH_LENGTH + `MAC_HEADER_LENGTH; + `SEND_LAST: unwritten_len <= `BTH_LENGTH + `MAC_HEADER_LENGTH; + `SEND_ONLY_WITH_IMM: unwritten_len <= `BTH_LENGTH + `IMMETH_LENGTH + `MAC_HEADER_LENGTH; + `SEND_LAST_WITH_IMM: unwritten_len <= `BTH_LENGTH + `MAC_HEADER_LENGTH; + `RDMA_WRITE_FIRST: unwritten_len <= `BTH_LENGTH + `RETH_LENGTH + `MAC_HEADER_LENGTH; + `RDMA_WRITE_MIDDLE: unwritten_len <= `BTH_LENGTH + `RETH_LENGTH + `MAC_HEADER_LENGTH; + `RDMA_WRITE_LAST: unwritten_len <= `BTH_LENGTH + `RETH_LENGTH + `MAC_HEADER_LENGTH; + `RDMA_WRITE_ONLY: unwritten_len <= `BTH_LENGTH + `RETH_LENGTH + `MAC_HEADER_LENGTH; + `RDMA_WRITE_LAST_WITH_IMM: unwritten_len <= `BTH_LENGTH + `RETH_LENGTH +`IMMETH_LENGTH + `MAC_HEADER_LENGTH; + `RDMA_WRITE_ONLY_WITH_IMM: unwritten_len <= `BTH_LENGTH + `RETH_LENGTH +`IMMETH_LENGTH + `MAC_HEADER_LENGTH; + `RDMA_READ_REQUEST_FIRST: unwritten_len <= `BTH_LENGTH + `RETH_LENGTH + `MAC_HEADER_LENGTH; + `RDMA_READ_REQUEST_MIDDLE: unwritten_len <= `BTH_LENGTH + `RETH_LENGTH + `MAC_HEADER_LENGTH; + `RDMA_READ_REQUEST_LAST: unwritten_len <= `BTH_LENGTH + `RETH_LENGTH + `MAC_HEADER_LENGTH; + `RDMA_READ_REQUEST_ONLY: unwritten_len <= `BTH_LENGTH + `RETH_LENGTH + `MAC_HEADER_LENGTH; + `RDMA_READ_RESPONSE_FIRST: unwritten_len <= `BTH_LENGTH + `MAC_HEADER_LENGTH; + `RDMA_READ_RESPONSE_MIDDLE: unwritten_len <= `BTH_LENGTH + `MAC_HEADER_LENGTH; + `RDMA_READ_RESPONSE_LAST: unwritten_len <= `BTH_LENGTH + `MAC_HEADER_LENGTH; + `RDMA_READ_RESPONSE_ONLY: unwritten_len <= `BTH_LENGTH + `MAC_HEADER_LENGTH; + `ACKNOWLEDGE: unwritten_len <= `BTH_LENGTH + `AETH_LENGTH + `MAC_HEADER_LENGTH; + default: unwritten_len <= 'd0; + endcase + end + else if(cur_state == ZERO_PAYLOAD_ENCAP_s && mac_tx_ready) begin + unwritten_len <= 'd0; + end + else if(cur_state == NON_ZERO_PAYLOAD_ENCAP_s) begin + if(payload_left_length == 0) begin //Last cycle transmit + unwritten_len <= mac_tx_ready ? 'd0 : unwritten_len; + end + else if(payload_left_length > 0 && delete_resp_valid && mac_tx_ready) begin + if(payload_left_length + unwritten_len <= 64) begin //Last cycle transmit + unwritten_len <= 'd0; + end + else if(payload_left_length + unwritten_len > 64) begin + if(payload_left_length > 64) begin + unwritten_len <= unwritten_len; + end + else begin + unwritten_len <= payload_left_length + unwritten_len - 'd64; + end + end + else begin + unwritten_len <= unwritten_len; + end + end + else begin + unwritten_len <= unwritten_len; + end + end + else begin + unwritten_len <= unwritten_len; + end +end + +//-- unwritten_data -- +always @(posedge clk or posedge rst) begin + if (rst) begin + unwritten_data <= 'd0; + end + else if (cur_state == IDLE_s && egress_pkt_valid) begin + case(egress_pkt_head[`OPCODE_OFFSET]) + `SEND_FIRST: unwritten_data <= {bth, mac_header}; + `SEND_MIDDLE: unwritten_data <= {bth, mac_header}; + `SEND_ONLY: unwritten_data <= {bth, mac_header}; + `SEND_LAST: unwritten_data <= {bth, mac_header}; + `SEND_ONLY_WITH_IMM: unwritten_data <= {immeth, bth, mac_header}; + `SEND_LAST_WITH_IMM: unwritten_data <= {immeth, bth, mac_header}; + `RDMA_WRITE_FIRST: unwritten_data <= {reth, bth, mac_header}; + `RDMA_WRITE_MIDDLE: unwritten_data <= {reth, bth, mac_header}; + `RDMA_WRITE_LAST: unwritten_data <= {reth, bth, mac_header}; + `RDMA_WRITE_ONLY: unwritten_data <= {reth, bth, mac_header}; + `RDMA_WRITE_LAST_WITH_IMM: unwritten_data <= {immeth, reth, bth, mac_header}; + `RDMA_WRITE_ONLY_WITH_IMM: unwritten_data <= {immeth, reth, bth, mac_header}; + `RDMA_READ_REQUEST_FIRST: unwritten_data <= {reth, bth, mac_header}; + `RDMA_READ_REQUEST_MIDDLE: unwritten_data <= {reth, bth, mac_header}; + `RDMA_READ_REQUEST_LAST: unwritten_data <= {reth, bth, mac_header}; + `RDMA_READ_REQUEST_ONLY: unwritten_data <= {reth, bth, mac_header}; + `RDMA_READ_RESPONSE_FIRST: unwritten_data <= {bth, mac_header}; + `RDMA_READ_RESPONSE_MIDDLE: unwritten_data <= {bth, mac_header}; + `RDMA_READ_RESPONSE_LAST: unwritten_data <= {bth, mac_header}; + `RDMA_READ_RESPONSE_ONLY: unwritten_data <= {bth, mac_header}; + `ACKNOWLEDGE: unwritten_data <= {aeth, bth, mac_header}; + default: unwritten_data <= 'd0; + endcase + end + else if(cur_state == ZERO_PAYLOAD_ENCAP_s && mac_tx_ready) begin + unwritten_data <= 'd0; + end + else if(cur_state == NON_ZERO_PAYLOAD_ENCAP_s) begin + if(payload_left_length == 0) begin + unwritten_data <= mac_tx_ready ? 'd0 : unwritten_data; + end + else if(payload_left_length > 0 && delete_resp_valid && mac_tx_ready) begin + if(payload_left_length + unwritten_len <= 64) begin + unwritten_data <= 'd0; + end + else if(payload_left_length > 64 || payload_left_length + unwritten_len > 64) begin + case(unwritten_len) + 0 : unwritten_data <= 'd0; + 1 : unwritten_data <= {{((64 - 1 ) * 8){1'b0}}, delete_resp_data[511 : (64 - 1 ) * 8]}; + 2 : unwritten_data <= {{((64 - 2 ) * 8){1'b0}}, delete_resp_data[511 : (64 - 2 ) * 8]}; + 3 : unwritten_data <= {{((64 - 3 ) * 8){1'b0}}, delete_resp_data[511 : (64 - 3 ) * 8]}; + 4 : unwritten_data <= {{((64 - 4 ) * 8){1'b0}}, delete_resp_data[511 : (64 - 4 ) * 8]}; + 5 : unwritten_data <= {{((64 - 5 ) * 8){1'b0}}, delete_resp_data[511 : (64 - 5 ) * 8]}; + 6 : unwritten_data <= {{((64 - 6 ) * 8){1'b0}}, delete_resp_data[511 : (64 - 6 ) * 8]}; + 7 : unwritten_data <= {{((64 - 7 ) * 8){1'b0}}, delete_resp_data[511 : (64 - 7 ) * 8]}; + 8 : unwritten_data <= {{((64 - 8 ) * 8){1'b0}}, delete_resp_data[511 : (64 - 8 ) * 8]}; + 9 : unwritten_data <= {{((64 - 9 ) * 8){1'b0}}, delete_resp_data[511 : (64 - 9 ) * 8]}; + 10 : unwritten_data <= {{((64 - 10) * 8){1'b0}}, delete_resp_data[511 : (64 - 10) * 8]}; + 11 : unwritten_data <= {{((64 - 11) * 8){1'b0}}, delete_resp_data[511 : (64 - 11) * 8]}; + 12 : unwritten_data <= {{((64 - 12) * 8){1'b0}}, delete_resp_data[511 : (64 - 12) * 8]}; + 13 : unwritten_data <= {{((64 - 13) * 8){1'b0}}, delete_resp_data[511 : (64 - 13) * 8]}; + 14 : unwritten_data <= {{((64 - 14) * 8){1'b0}}, delete_resp_data[511 : (64 - 14) * 8]}; + 15 : unwritten_data <= {{((64 - 15) * 8){1'b0}}, delete_resp_data[511 : (64 - 15) * 8]}; + 16 : unwritten_data <= {{((64 - 16) * 8){1'b0}}, delete_resp_data[511 : (64 - 16) * 8]}; + 17 : unwritten_data <= {{((64 - 17) * 8){1'b0}}, delete_resp_data[511 : (64 - 17) * 8]}; + 18 : unwritten_data <= {{((64 - 18) * 8){1'b0}}, delete_resp_data[511 : (64 - 18) * 8]}; + 19 : unwritten_data <= {{((64 - 19) * 8){1'b0}}, delete_resp_data[511 : (64 - 19) * 8]}; + 20 : unwritten_data <= {{((64 - 20) * 8){1'b0}}, delete_resp_data[511 : (64 - 20) * 8]}; + 21 : unwritten_data <= {{((64 - 21) * 8){1'b0}}, delete_resp_data[511 : (64 - 21) * 8]}; + 22 : unwritten_data <= {{((64 - 22) * 8){1'b0}}, delete_resp_data[511 : (64 - 22) * 8]}; + 23 : unwritten_data <= {{((64 - 23) * 8){1'b0}}, delete_resp_data[511 : (64 - 23) * 8]}; + 24 : unwritten_data <= {{((64 - 24) * 8){1'b0}}, delete_resp_data[511 : (64 - 24) * 8]}; + 25 : unwritten_data <= {{((64 - 25) * 8){1'b0}}, delete_resp_data[511 : (64 - 25) * 8]}; + 26 : unwritten_data <= {{((64 - 26) * 8){1'b0}}, delete_resp_data[511 : (64 - 26) * 8]}; + 27 : unwritten_data <= {{((64 - 27) * 8){1'b0}}, delete_resp_data[511 : (64 - 27) * 8]}; + 28 : unwritten_data <= {{((64 - 28) * 8){1'b0}}, delete_resp_data[511 : (64 - 28) * 8]}; + 29 : unwritten_data <= {{((64 - 29) * 8){1'b0}}, delete_resp_data[511 : (64 - 29) * 8]}; + 30 : unwritten_data <= {{((64 - 30) * 8){1'b0}}, delete_resp_data[511 : (64 - 30) * 8]}; + 31 : unwritten_data <= {{((64 - 31) * 8){1'b0}}, delete_resp_data[511 : (64 - 31) * 8]}; + 32 : unwritten_data <= {{((64 - 32) * 8){1'b0}}, delete_resp_data[511 : (64 - 32) * 8]}; + 33 : unwritten_data <= {{((64 - 33) * 8){1'b0}}, delete_resp_data[511 : (64 - 33) * 8]}; + 34 : unwritten_data <= {{((64 - 34) * 8){1'b0}}, delete_resp_data[511 : (64 - 34) * 8]}; + 35 : unwritten_data <= {{((64 - 35) * 8){1'b0}}, delete_resp_data[511 : (64 - 35) * 8]}; + 36 : unwritten_data <= {{((64 - 36) * 8){1'b0}}, delete_resp_data[511 : (64 - 36) * 8]}; + 37 : unwritten_data <= {{((64 - 37) * 8){1'b0}}, delete_resp_data[511 : (64 - 37) * 8]}; + 38 : unwritten_data <= {{((64 - 38) * 8){1'b0}}, delete_resp_data[511 : (64 - 38) * 8]}; + 39 : unwritten_data <= {{((64 - 39) * 8){1'b0}}, delete_resp_data[511 : (64 - 39) * 8]}; + 40 : unwritten_data <= {{((64 - 40) * 8){1'b0}}, delete_resp_data[511 : (64 - 40) * 8]}; + 41 : unwritten_data <= {{((64 - 41) * 8){1'b0}}, delete_resp_data[511 : (64 - 41) * 8]}; + 42 : unwritten_data <= {{((64 - 42) * 8){1'b0}}, delete_resp_data[511 : (64 - 42) * 8]}; + 43 : unwritten_data <= {{((64 - 43) * 8){1'b0}}, delete_resp_data[511 : (64 - 43) * 8]}; + 44 : unwritten_data <= {{((64 - 44) * 8){1'b0}}, delete_resp_data[511 : (64 - 44) * 8]}; + 45 : unwritten_data <= {{((64 - 45) * 8){1'b0}}, delete_resp_data[511 : (64 - 45) * 8]}; + 46 : unwritten_data <= {{((64 - 46) * 8){1'b0}}, delete_resp_data[511 : (64 - 46) * 8]}; + 47 : unwritten_data <= {{((64 - 47) * 8){1'b0}}, delete_resp_data[511 : (64 - 47) * 8]}; + 48 : unwritten_data <= {{((64 - 48) * 8){1'b0}}, delete_resp_data[511 : (64 - 48) * 8]}; + 49 : unwritten_data <= {{((64 - 49) * 8){1'b0}}, delete_resp_data[511 : (64 - 49) * 8]}; + 50 : unwritten_data <= {{((64 - 50) * 8){1'b0}}, delete_resp_data[511 : (64 - 50) * 8]}; + 51 : unwritten_data <= {{((64 - 51) * 8){1'b0}}, delete_resp_data[511 : (64 - 51) * 8]}; + 52 : unwritten_data <= {{((64 - 52) * 8){1'b0}}, delete_resp_data[511 : (64 - 52) * 8]}; + 53 : unwritten_data <= {{((64 - 53) * 8){1'b0}}, delete_resp_data[511 : (64 - 53) * 8]}; + 54 : unwritten_data <= {{((64 - 54) * 8){1'b0}}, delete_resp_data[511 : (64 - 54) * 8]}; + 55 : unwritten_data <= {{((64 - 55) * 8){1'b0}}, delete_resp_data[511 : (64 - 55) * 8]}; + 56 : unwritten_data <= {{((64 - 56) * 8){1'b0}}, delete_resp_data[511 : (64 - 56) * 8]}; + 57 : unwritten_data <= {{((64 - 57) * 8){1'b0}}, delete_resp_data[511 : (64 - 57) * 8]}; + 58 : unwritten_data <= {{((64 - 58) * 8){1'b0}}, delete_resp_data[511 : (64 - 58) * 8]}; + 59 : unwritten_data <= {{((64 - 59) * 8){1'b0}}, delete_resp_data[511 : (64 - 59) * 8]}; + 60 : unwritten_data <= {{((64 - 60) * 8){1'b0}}, delete_resp_data[511 : (64 - 60) * 8]}; + 61 : unwritten_data <= {{((64 - 61) * 8){1'b0}}, delete_resp_data[511 : (64 - 61) * 8]}; + 62 : unwritten_data <= {{((64 - 62) * 8){1'b0}}, delete_resp_data[511 : (64 - 62) * 8]}; + 63 : unwritten_data <= {{((64 - 63) * 8){1'b0}}, delete_resp_data[511 : (64 - 63) * 8]}; + default: unwritten_data <= unwritten_data; + endcase + end + else if(payload_left_length + unwritten_len <= 64) begin + unwritten_data <= 'd0; + end + else begin + unwritten_data <= unwritten_data; + end + end + else begin + unwritten_data <= unwritten_data; + end + end + else begin + unwritten_data <= unwritten_data; + end +end + +//-- mac_tx_data -- +always @(*) begin + if (rst) begin + mac_tx_data = 'd0; + end + else if (cur_state == ZERO_PAYLOAD_ENCAP_s) begin + mac_tx_data = unwritten_data; + end + else if(cur_state == NON_ZERO_PAYLOAD_ENCAP_s) begin + if(payload_left_length == 0) begin + mac_tx_data = unwritten_data; + end + else if(payload_left_length > 64 || payload_left_length + unwritten_len > 64) begin + case(unwritten_len) + 0 : mac_tx_data = delete_resp_data; + 1 : mac_tx_data = {delete_resp_data[(64 - 1 ) * 8 - 1 : 0], unwritten_data[1 * 8 - 1 : 0]}; + 2 : mac_tx_data = {delete_resp_data[(64 - 2 ) * 8 - 1 : 0], unwritten_data[2 * 8 - 1 : 0]}; + 3 : mac_tx_data = {delete_resp_data[(64 - 3 ) * 8 - 1 : 0], unwritten_data[3 * 8 - 1 : 0]}; + 4 : mac_tx_data = {delete_resp_data[(64 - 4 ) * 8 - 1 : 0], unwritten_data[4 * 8 - 1 : 0]}; + 5 : mac_tx_data = {delete_resp_data[(64 - 5 ) * 8 - 1 : 0], unwritten_data[5 * 8 - 1 : 0]}; + 6 : mac_tx_data = {delete_resp_data[(64 - 6 ) * 8 - 1 : 0], unwritten_data[6 * 8 - 1 : 0]}; + 7 : mac_tx_data = {delete_resp_data[(64 - 7 ) * 8 - 1 : 0], unwritten_data[7 * 8 - 1 : 0]}; + 8 : mac_tx_data = {delete_resp_data[(64 - 8 ) * 8 - 1 : 0], unwritten_data[8 * 8 - 1 : 0]}; + 9 : mac_tx_data = {delete_resp_data[(64 - 9 ) * 8 - 1 : 0], unwritten_data[9 * 8 - 1 : 0]}; + 10 : mac_tx_data = {delete_resp_data[(64 - 10) * 8 - 1 : 0], unwritten_data[10 * 8 - 1 : 0]}; + 11 : mac_tx_data = {delete_resp_data[(64 - 11) * 8 - 1 : 0], unwritten_data[11 * 8 - 1 : 0]}; + 12 : mac_tx_data = {delete_resp_data[(64 - 12) * 8 - 1 : 0], unwritten_data[12 * 8 - 1 : 0]}; + 13 : mac_tx_data = {delete_resp_data[(64 - 13) * 8 - 1 : 0], unwritten_data[13 * 8 - 1 : 0]}; + 14 : mac_tx_data = {delete_resp_data[(64 - 14) * 8 - 1 : 0], unwritten_data[14 * 8 - 1 : 0]}; + 15 : mac_tx_data = {delete_resp_data[(64 - 15) * 8 - 1 : 0], unwritten_data[15 * 8 - 1 : 0]}; + 16 : mac_tx_data = {delete_resp_data[(64 - 16) * 8 - 1 : 0], unwritten_data[16 * 8 - 1 : 0]}; + 17 : mac_tx_data = {delete_resp_data[(64 - 17) * 8 - 1 : 0], unwritten_data[17 * 8 - 1 : 0]}; + 18 : mac_tx_data = {delete_resp_data[(64 - 18) * 8 - 1 : 0], unwritten_data[18 * 8 - 1 : 0]}; + 19 : mac_tx_data = {delete_resp_data[(64 - 19) * 8 - 1 : 0], unwritten_data[19 * 8 - 1 : 0]}; + 20 : mac_tx_data = {delete_resp_data[(64 - 20) * 8 - 1 : 0], unwritten_data[20 * 8 - 1 : 0]}; + 21 : mac_tx_data = {delete_resp_data[(64 - 21) * 8 - 1 : 0], unwritten_data[21 * 8 - 1 : 0]}; + 22 : mac_tx_data = {delete_resp_data[(64 - 22) * 8 - 1 : 0], unwritten_data[22 * 8 - 1 : 0]}; + 23 : mac_tx_data = {delete_resp_data[(64 - 23) * 8 - 1 : 0], unwritten_data[23 * 8 - 1 : 0]}; + 24 : mac_tx_data = {delete_resp_data[(64 - 24) * 8 - 1 : 0], unwritten_data[24 * 8 - 1 : 0]}; + 25 : mac_tx_data = {delete_resp_data[(64 - 25) * 8 - 1 : 0], unwritten_data[25 * 8 - 1 : 0]}; + 26 : mac_tx_data = {delete_resp_data[(64 - 26) * 8 - 1 : 0], unwritten_data[26 * 8 - 1 : 0]}; + 27 : mac_tx_data = {delete_resp_data[(64 - 27) * 8 - 1 : 0], unwritten_data[27 * 8 - 1 : 0]}; + 28 : mac_tx_data = {delete_resp_data[(64 - 28) * 8 - 1 : 0], unwritten_data[28 * 8 - 1 : 0]}; + 29 : mac_tx_data = {delete_resp_data[(64 - 29) * 8 - 1 : 0], unwritten_data[29 * 8 - 1 : 0]}; + 30 : mac_tx_data = {delete_resp_data[(64 - 30) * 8 - 1 : 0], unwritten_data[30 * 8 - 1 : 0]}; + 31 : mac_tx_data = {delete_resp_data[(64 - 31) * 8 - 1 : 0], unwritten_data[31 * 8 - 1 : 0]}; + 32 : mac_tx_data = {delete_resp_data[(64 - 32) * 8 - 1 : 0], unwritten_data[32 * 8 - 1 : 0]}; + 33 : mac_tx_data = {delete_resp_data[(64 - 33) * 8 - 1 : 0], unwritten_data[33 * 8 - 1 : 0]}; + 34 : mac_tx_data = {delete_resp_data[(64 - 34) * 8 - 1 : 0], unwritten_data[34 * 8 - 1 : 0]}; + 35 : mac_tx_data = {delete_resp_data[(64 - 35) * 8 - 1 : 0], unwritten_data[35 * 8 - 1 : 0]}; + 36 : mac_tx_data = {delete_resp_data[(64 - 36) * 8 - 1 : 0], unwritten_data[36 * 8 - 1 : 0]}; + 37 : mac_tx_data = {delete_resp_data[(64 - 37) * 8 - 1 : 0], unwritten_data[37 * 8 - 1 : 0]}; + 38 : mac_tx_data = {delete_resp_data[(64 - 38) * 8 - 1 : 0], unwritten_data[38 * 8 - 1 : 0]}; + 39 : mac_tx_data = {delete_resp_data[(64 - 39) * 8 - 1 : 0], unwritten_data[39 * 8 - 1 : 0]}; + 40 : mac_tx_data = {delete_resp_data[(64 - 40) * 8 - 1 : 0], unwritten_data[40 * 8 - 1 : 0]}; + 41 : mac_tx_data = {delete_resp_data[(64 - 41) * 8 - 1 : 0], unwritten_data[41 * 8 - 1 : 0]}; + 42 : mac_tx_data = {delete_resp_data[(64 - 42) * 8 - 1 : 0], unwritten_data[42 * 8 - 1 : 0]}; + 43 : mac_tx_data = {delete_resp_data[(64 - 43) * 8 - 1 : 0], unwritten_data[43 * 8 - 1 : 0]}; + 44 : mac_tx_data = {delete_resp_data[(64 - 44) * 8 - 1 : 0], unwritten_data[44 * 8 - 1 : 0]}; + 45 : mac_tx_data = {delete_resp_data[(64 - 45) * 8 - 1 : 0], unwritten_data[45 * 8 - 1 : 0]}; + 46 : mac_tx_data = {delete_resp_data[(64 - 46) * 8 - 1 : 0], unwritten_data[46 * 8 - 1 : 0]}; + 47 : mac_tx_data = {delete_resp_data[(64 - 47) * 8 - 1 : 0], unwritten_data[47 * 8 - 1 : 0]}; + 48 : mac_tx_data = {delete_resp_data[(64 - 48) * 8 - 1 : 0], unwritten_data[48 * 8 - 1 : 0]}; + 49 : mac_tx_data = {delete_resp_data[(64 - 49) * 8 - 1 : 0], unwritten_data[49 * 8 - 1 : 0]}; + 50 : mac_tx_data = {delete_resp_data[(64 - 50) * 8 - 1 : 0], unwritten_data[50 * 8 - 1 : 0]}; + 51 : mac_tx_data = {delete_resp_data[(64 - 51) * 8 - 1 : 0], unwritten_data[51 * 8 - 1 : 0]}; + 52 : mac_tx_data = {delete_resp_data[(64 - 52) * 8 - 1 : 0], unwritten_data[52 * 8 - 1 : 0]}; + 53 : mac_tx_data = {delete_resp_data[(64 - 53) * 8 - 1 : 0], unwritten_data[53 * 8 - 1 : 0]}; + 54 : mac_tx_data = {delete_resp_data[(64 - 54) * 8 - 1 : 0], unwritten_data[54 * 8 - 1 : 0]}; + 55 : mac_tx_data = {delete_resp_data[(64 - 55) * 8 - 1 : 0], unwritten_data[55 * 8 - 1 : 0]}; + 56 : mac_tx_data = {delete_resp_data[(64 - 56) * 8 - 1 : 0], unwritten_data[56 * 8 - 1 : 0]}; + 57 : mac_tx_data = {delete_resp_data[(64 - 57) * 8 - 1 : 0], unwritten_data[57 * 8 - 1 : 0]}; + 58 : mac_tx_data = {delete_resp_data[(64 - 58) * 8 - 1 : 0], unwritten_data[58 * 8 - 1 : 0]}; + 59 : mac_tx_data = {delete_resp_data[(64 - 59) * 8 - 1 : 0], unwritten_data[59 * 8 - 1 : 0]}; + 60 : mac_tx_data = {delete_resp_data[(64 - 60) * 8 - 1 : 0], unwritten_data[60 * 8 - 1 : 0]}; + 61 : mac_tx_data = {delete_resp_data[(64 - 61) * 8 - 1 : 0], unwritten_data[61 * 8 - 1 : 0]}; + 62 : mac_tx_data = {delete_resp_data[(64 - 62) * 8 - 1 : 0], unwritten_data[62 * 8 - 1 : 0]}; + 63 : mac_tx_data = {delete_resp_data[(64 - 63) * 8 - 1 : 0], unwritten_data[63 * 8 - 1 : 0]}; + default: mac_tx_data = 'd0; + endcase + end + else if(payload_left_length + unwritten_len <= 64) begin + case(unwritten_len) + 0 : mac_tx_data = delete_resp_data; + 1 : mac_tx_data = {delete_resp_data[(64 - 1 ) * 8 - 1 : 0], unwritten_data[1 * 8 - 1 : 0]}; + 2 : mac_tx_data = {delete_resp_data[(64 - 2 ) * 8 - 1 : 0], unwritten_data[2 * 8 - 1 : 0]}; + 3 : mac_tx_data = {delete_resp_data[(64 - 3 ) * 8 - 1 : 0], unwritten_data[3 * 8 - 1 : 0]}; + 4 : mac_tx_data = {delete_resp_data[(64 - 4 ) * 8 - 1 : 0], unwritten_data[4 * 8 - 1 : 0]}; + 5 : mac_tx_data = {delete_resp_data[(64 - 5 ) * 8 - 1 : 0], unwritten_data[5 * 8 - 1 : 0]}; + 6 : mac_tx_data = {delete_resp_data[(64 - 6 ) * 8 - 1 : 0], unwritten_data[6 * 8 - 1 : 0]}; + 7 : mac_tx_data = {delete_resp_data[(64 - 7 ) * 8 - 1 : 0], unwritten_data[7 * 8 - 1 : 0]}; + 8 : mac_tx_data = {delete_resp_data[(64 - 8 ) * 8 - 1 : 0], unwritten_data[8 * 8 - 1 : 0]}; + 9 : mac_tx_data = {delete_resp_data[(64 - 9 ) * 8 - 1 : 0], unwritten_data[9 * 8 - 1 : 0]}; + 10 : mac_tx_data = {delete_resp_data[(64 - 10) * 8 - 1 : 0], unwritten_data[10 * 8 - 1 : 0]}; + 11 : mac_tx_data = {delete_resp_data[(64 - 11) * 8 - 1 : 0], unwritten_data[11 * 8 - 1 : 0]}; + 12 : mac_tx_data = {delete_resp_data[(64 - 12) * 8 - 1 : 0], unwritten_data[12 * 8 - 1 : 0]}; + 13 : mac_tx_data = {delete_resp_data[(64 - 13) * 8 - 1 : 0], unwritten_data[13 * 8 - 1 : 0]}; + 14 : mac_tx_data = {delete_resp_data[(64 - 14) * 8 - 1 : 0], unwritten_data[14 * 8 - 1 : 0]}; + 15 : mac_tx_data = {delete_resp_data[(64 - 15) * 8 - 1 : 0], unwritten_data[15 * 8 - 1 : 0]}; + 16 : mac_tx_data = {delete_resp_data[(64 - 16) * 8 - 1 : 0], unwritten_data[16 * 8 - 1 : 0]}; + 17 : mac_tx_data = {delete_resp_data[(64 - 17) * 8 - 1 : 0], unwritten_data[17 * 8 - 1 : 0]}; + 18 : mac_tx_data = {delete_resp_data[(64 - 18) * 8 - 1 : 0], unwritten_data[18 * 8 - 1 : 0]}; + 19 : mac_tx_data = {delete_resp_data[(64 - 19) * 8 - 1 : 0], unwritten_data[19 * 8 - 1 : 0]}; + 20 : mac_tx_data = {delete_resp_data[(64 - 20) * 8 - 1 : 0], unwritten_data[20 * 8 - 1 : 0]}; + 21 : mac_tx_data = {delete_resp_data[(64 - 21) * 8 - 1 : 0], unwritten_data[21 * 8 - 1 : 0]}; + 22 : mac_tx_data = {delete_resp_data[(64 - 22) * 8 - 1 : 0], unwritten_data[22 * 8 - 1 : 0]}; + 23 : mac_tx_data = {delete_resp_data[(64 - 23) * 8 - 1 : 0], unwritten_data[23 * 8 - 1 : 0]}; + 24 : mac_tx_data = {delete_resp_data[(64 - 24) * 8 - 1 : 0], unwritten_data[24 * 8 - 1 : 0]}; + 25 : mac_tx_data = {delete_resp_data[(64 - 25) * 8 - 1 : 0], unwritten_data[25 * 8 - 1 : 0]}; + 26 : mac_tx_data = {delete_resp_data[(64 - 26) * 8 - 1 : 0], unwritten_data[26 * 8 - 1 : 0]}; + 27 : mac_tx_data = {delete_resp_data[(64 - 27) * 8 - 1 : 0], unwritten_data[27 * 8 - 1 : 0]}; + 28 : mac_tx_data = {delete_resp_data[(64 - 28) * 8 - 1 : 0], unwritten_data[28 * 8 - 1 : 0]}; + 29 : mac_tx_data = {delete_resp_data[(64 - 29) * 8 - 1 : 0], unwritten_data[29 * 8 - 1 : 0]}; + 30 : mac_tx_data = {delete_resp_data[(64 - 30) * 8 - 1 : 0], unwritten_data[30 * 8 - 1 : 0]}; + 31 : mac_tx_data = {delete_resp_data[(64 - 31) * 8 - 1 : 0], unwritten_data[31 * 8 - 1 : 0]}; + 32 : mac_tx_data = {delete_resp_data[(64 - 32) * 8 - 1 : 0], unwritten_data[32 * 8 - 1 : 0]}; + 33 : mac_tx_data = {delete_resp_data[(64 - 33) * 8 - 1 : 0], unwritten_data[33 * 8 - 1 : 0]}; + 34 : mac_tx_data = {delete_resp_data[(64 - 34) * 8 - 1 : 0], unwritten_data[34 * 8 - 1 : 0]}; + 35 : mac_tx_data = {delete_resp_data[(64 - 35) * 8 - 1 : 0], unwritten_data[35 * 8 - 1 : 0]}; + 36 : mac_tx_data = {delete_resp_data[(64 - 36) * 8 - 1 : 0], unwritten_data[36 * 8 - 1 : 0]}; + 37 : mac_tx_data = {delete_resp_data[(64 - 37) * 8 - 1 : 0], unwritten_data[37 * 8 - 1 : 0]}; + 38 : mac_tx_data = {delete_resp_data[(64 - 38) * 8 - 1 : 0], unwritten_data[38 * 8 - 1 : 0]}; + 39 : mac_tx_data = {delete_resp_data[(64 - 39) * 8 - 1 : 0], unwritten_data[39 * 8 - 1 : 0]}; + 40 : mac_tx_data = {delete_resp_data[(64 - 40) * 8 - 1 : 0], unwritten_data[40 * 8 - 1 : 0]}; + 41 : mac_tx_data = {delete_resp_data[(64 - 41) * 8 - 1 : 0], unwritten_data[41 * 8 - 1 : 0]}; + 42 : mac_tx_data = {delete_resp_data[(64 - 42) * 8 - 1 : 0], unwritten_data[42 * 8 - 1 : 0]}; + 43 : mac_tx_data = {delete_resp_data[(64 - 43) * 8 - 1 : 0], unwritten_data[43 * 8 - 1 : 0]}; + 44 : mac_tx_data = {delete_resp_data[(64 - 44) * 8 - 1 : 0], unwritten_data[44 * 8 - 1 : 0]}; + 45 : mac_tx_data = {delete_resp_data[(64 - 45) * 8 - 1 : 0], unwritten_data[45 * 8 - 1 : 0]}; + 46 : mac_tx_data = {delete_resp_data[(64 - 46) * 8 - 1 : 0], unwritten_data[46 * 8 - 1 : 0]}; + 47 : mac_tx_data = {delete_resp_data[(64 - 47) * 8 - 1 : 0], unwritten_data[47 * 8 - 1 : 0]}; + 48 : mac_tx_data = {delete_resp_data[(64 - 48) * 8 - 1 : 0], unwritten_data[48 * 8 - 1 : 0]}; + 49 : mac_tx_data = {delete_resp_data[(64 - 49) * 8 - 1 : 0], unwritten_data[49 * 8 - 1 : 0]}; + 50 : mac_tx_data = {delete_resp_data[(64 - 50) * 8 - 1 : 0], unwritten_data[50 * 8 - 1 : 0]}; + 51 : mac_tx_data = {delete_resp_data[(64 - 51) * 8 - 1 : 0], unwritten_data[51 * 8 - 1 : 0]}; + 52 : mac_tx_data = {delete_resp_data[(64 - 52) * 8 - 1 : 0], unwritten_data[52 * 8 - 1 : 0]}; + 53 : mac_tx_data = {delete_resp_data[(64 - 53) * 8 - 1 : 0], unwritten_data[53 * 8 - 1 : 0]}; + 54 : mac_tx_data = {delete_resp_data[(64 - 54) * 8 - 1 : 0], unwritten_data[54 * 8 - 1 : 0]}; + 55 : mac_tx_data = {delete_resp_data[(64 - 55) * 8 - 1 : 0], unwritten_data[55 * 8 - 1 : 0]}; + 56 : mac_tx_data = {delete_resp_data[(64 - 56) * 8 - 1 : 0], unwritten_data[56 * 8 - 1 : 0]}; + 57 : mac_tx_data = {delete_resp_data[(64 - 57) * 8 - 1 : 0], unwritten_data[57 * 8 - 1 : 0]}; + 58 : mac_tx_data = {delete_resp_data[(64 - 58) * 8 - 1 : 0], unwritten_data[58 * 8 - 1 : 0]}; + 59 : mac_tx_data = {delete_resp_data[(64 - 59) * 8 - 1 : 0], unwritten_data[59 * 8 - 1 : 0]}; + 60 : mac_tx_data = {delete_resp_data[(64 - 60) * 8 - 1 : 0], unwritten_data[60 * 8 - 1 : 0]}; + 61 : mac_tx_data = {delete_resp_data[(64 - 61) * 8 - 1 : 0], unwritten_data[61 * 8 - 1 : 0]}; + 62 : mac_tx_data = {delete_resp_data[(64 - 62) * 8 - 1 : 0], unwritten_data[62 * 8 - 1 : 0]}; + 63 : mac_tx_data = {delete_resp_data[(64 - 63) * 8 - 1 : 0], unwritten_data[63 * 8 - 1 : 0]}; + default: mac_tx_data = 'd0; + endcase + end + else begin + mac_tx_data = 'd0; + end + end + else begin + mac_tx_data = 'd0; + end +end + +//-- mac_tx_valid -- +//-- mac_tx_start -- +//-- mac_tx_last -- +//-- mac_tx_keep -- +//-- mac_tx_user -- +assign mac_tx_valid = (cur_state == ZERO_PAYLOAD_ENCAP_s) ? 'd1 : + (cur_state == NON_ZERO_PAYLOAD_ENCAP_s && payload_left_length > 0 && delete_resp_valid) ? 'd1 : + (cur_state == NON_ZERO_PAYLOAD_ENCAP_s && payload_left_length == 0) ? 'd1 : 'd0; +assign mac_tx_start = (cur_state == ZERO_PAYLOAD_ENCAP_s) ? 'd1 : + (cur_state == NON_ZERO_PAYLOAD_ENCAP_s && payload_left_length == bth_pkt_length) ? 'd1 : 'd0; +assign mac_tx_last = (cur_state == ZERO_PAYLOAD_ENCAP_s) ? 'd1 : + (cur_state == NON_ZERO_PAYLOAD_ENCAP_s && mac_tx_valid && payload_left_length + unwritten_len <= 64) ? 'd1 : 'd0; +assign mac_tx_keep = 64'hFFFFFFFFFFFFFFFF; //We don't use keep, juse keep all valid +assign mac_tx_user = 'd0; //Always good packet + +//-- egress_pkt_ready -- +assign egress_pkt_ready = (cur_state == IDLE_s) ? 'd1 : 'd0; + +//-- delete_req_valid -- +//-- delete_req_head -- +assign delete_req_valid = (cur_state == DEL_s) ? 'd1 : 'd0; +assign delete_req_head = (cur_state == DEL_s) ? {bth_pkt_length[5:0] ? (bth_pkt_length >> 6) + 1 : bth_pkt_length >> 6, pkt_header_bus[`PAYLOAD_ADDR_OFFSET]} : 'd0; + +//-- delete_resp_ready -- +assign delete_resp_ready = (cur_state == NON_ZERO_PAYLOAD_ENCAP_s) ? mac_tx_ready : 'd0; +/*------------------------------------------- Variables Decode : End ------------------------------------------------*/ + +/*------------------------------------------- Local Macros Undef : Begin --------------------------------------------*/ +`undef LOCAL_QPN_OFFSET +`undef OPCODE_OFFSET +`undef SERVICE_TYPE_OFFSET +`undef REMOTE_QPN_OFFSET +`undef RKEY_OFFSET +`undef RADDR_OFFSET +`undef IMMEDIATE_OFFSET +`undef DMAC_OFFSET +`undef SMAC_OFFSET +`undef DIP_OFFSET +`undef SIP_OFFSET +`undef PAYLOAD_ADDR_OFFSET +`undef PAYLOAD_LENGTH_OFFSET +/*------------------------------------------- Local Macros Undef : End ----------------------------------------------*/ +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Peripherals/OoOStation/OoOBalancer.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Peripherals/OoOStation/OoOBalancer.v new file mode 100644 index 0000000000000000000000000000000000000000..513f4766997d6d13b0a03695616e269a277a99fd --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Peripherals/OoOStation/OoOBalancer.v @@ -0,0 +1,427 @@ +/*------------------------------------------- Module Description : Begin ---------------------------------------------- +Name: OoOStation +Author: YangFan +Function: OoOStation is short for Out-of-Order station. + This module is a special abstraction aimed at solving Head-Of-Line Problem in Stateful Pipeline. + OoOStation accepts resources request and manages out-of-order request and resposne. + User can carry user-defined data with request, when desired resource is available, OoOStation will return resources with user-defined data. + For example, as for ReqTransEngine, the request is accompanied with WQE metadata, as for RespRecvControl, the request is accompanied with packet. + OoOStation does not care about what the req and resource are, it just handles out-of-order execution. + Typically, OoOStation interacts with two three threads: ingress thread, egress thread and resource mgt thread. + Ingress thread: Asynchronously issues resource request to OoOStation. + Egress thread: Accept resources from OoOStation and triggers next pipeline stage. + Resource mgt thread: Manage resources and respond to resource request. +--------------------------------------------- Module Decription : End -----------------------------------------------*/ + +/*------------------------------------------- Timescale Definition : Begin ------------------------------------------*/ +`timescale 1ns / 1ps +/*------------------------------------------- Timescale Definition : End --------------------------------------------*/ + +/*------------------------------------------- Included Files : Begin ------------------------------------------------*/ +`include "common_function_def.vh" +/*------------------------------------------- Included Files : End --------------------------------------------------*/ + +/*------------------------------------------- Local Macros Definition : Begin ---------------------------------------*/ +/*------------------------------------------- Local Macros Definition : End -----------------------------------------*/ + +/*------------------------------------------- Input/Output Definition : Begin ---------------------------------------*/ +module OoOBalancer #( + parameter OOO_STATION_NUM = 1, //1, 2, 4 + parameter OOO_STATION_NUM_LOG = log2b(OOO_STATION_NUM - 1), + + //TAG_NUM is not equal to SLOT_NUM, since each resource req consumes 1 tag, and it may require more than 1 slot. + parameter TAG_NUM = 32, + parameter TAG_NUM_LOG = log2b(TAG_NUM - 1), + + + //RESOURCE_CMD/RESP_WIDTH is resource-specific + //For example, MR resource cmd format is {PD, LKey, Lengtg, Addr}, MR resource reply format is {PTE-1, PTE-0, indicator} + parameter RESOURCE_CMD_HEAD_WIDTH = 128, + parameter RESOURCE_CMD_DATA_WIDTH = 256, + parameter RESOURCE_RESP_HEAD_WIDTH = 128, + parameter RESOURCE_RESP_DATA_WIDTH = 128, + + parameter SLOT_NUM = 512, + parameter QUEUE_NUM = 32, + parameter SLOT_NUM_LOG = log2b(SLOT_NUM - 1), + parameter QUEUE_NUM_LOG = log2b(QUEUE_NUM - 1), + + //When issuing cmd to Resource Manager, add tag index + parameter OOO_CMD_HEAD_WIDTH = `MAX_REQ_TAG_NUM_LOG + RESOURCE_CMD_HEAD_WIDTH, + parameter OOO_CMD_DATA_WIDTH = RESOURCE_CMD_DATA_WIDTH, + parameter OOO_RESP_HEAD_WIDTH = `MAX_REQ_TAG_NUM_LOG + RESOURCE_RESP_HEAD_WIDTH, + parameter OOO_RESP_DATA_WIDTH = RESOURCE_RESP_DATA_WIDTH, + + parameter INGRESS_HEAD_WIDTH = RESOURCE_CMD_HEAD_WIDTH + `INGRESS_COMMON_HEAD_WIDTH, + //INGRESS_DATA_WIDTH is ingress-thread-specific + parameter INGRESS_DATA_WIDTH = 512, + + parameter SLOT_WIDTH = INGRESS_DATA_WIDTH, + + + //Egress thread + parameter EGRESS_HEAD_WIDTH = RESOURCE_RESP_HEAD_WIDTH + `EGRESS_COMMON_HEAD_WIDTH, + parameter EGRESS_DATA_WIDTH = INGRESS_DATA_WIDTH +) +( + input wire clk, + input wire rst, + + input wire ingress_valid, + input wire [INGRESS_HEAD_WIDTH - 1 : 0] ingress_head, + input wire [SLOT_WIDTH - 1 : 0] ingress_data, + input wire ingress_start, + input wire ingress_last, + output wire ingress_ready, + + output wire [SLOT_NUM_LOG : 0] available_slot_num, + + output wire resource_req_valid, + output wire [OOO_CMD_HEAD_WIDTH - 1 : 0] resource_req_head, + output wire [OOO_CMD_DATA_WIDTH - 1 : 0] resource_req_data, + output wire resource_req_start, + output wire resource_req_last, + input wire resource_req_ready, + + input wire resource_resp_valid, + input wire [OOO_RESP_HEAD_WIDTH - 1 : 0] resource_resp_head, + input wire [OOO_RESP_DATA_WIDTH - 1 : 0] resource_resp_data, + input wire resource_resp_start, + input wire resource_resp_last, + output wire resource_resp_ready, + + output wire egress_valid, + output wire [EGRESS_HEAD_WIDTH - 1 : 0] egress_head, + output wire [EGRESS_DATA_WIDTH - 1 : 0] egress_data, + output wire egress_start, + output wire egress_last, + input wire egress_ready +); +/*------------------------------------------- Input/Output Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Variables Definition : Begin ------------------------------------*/ +wire [OOO_STATION_NUM - 1 : 0] st_ingress_valid; +wire [INGRESS_HEAD_WIDTH * OOO_STATION_NUM - 1 : 0] st_ingress_head; +wire [SLOT_WIDTH * OOO_STATION_NUM - 1 : 0] st_ingress_data; +wire [OOO_STATION_NUM - 1 : 0] st_ingress_start; +wire [OOO_STATION_NUM - 1 : 0] st_ingress_last; +wire [OOO_STATION_NUM - 1 : 0] st_ingress_ready; + + +wire [OOO_STATION_NUM - 1 : 0] balancer_ingress_valid; +wire [INGRESS_HEAD_WIDTH * OOO_STATION_NUM - 1 : 0] balancer_ingress_head; +wire [SLOT_WIDTH * OOO_STATION_NUM - 1 : 0] balancer_ingress_data; +wire [OOO_STATION_NUM - 1 : 0] balancer_ingress_start; +wire [OOO_STATION_NUM - 1 : 0] balancer_ingress_last; +wire [OOO_STATION_NUM - 1 : 0] balancer_ingress_ready; + +wire [OOO_STATION_NUM - 1 : 0] balancer_resource_req_valid; +wire [OOO_CMD_HEAD_WIDTH * OOO_STATION_NUM - 1 : 0] balancer_resource_req_head; +wire [OOO_CMD_DATA_WIDTH * OOO_STATION_NUM - 1 : 0] balancer_resource_req_data; +wire [OOO_STATION_NUM - 1 : 0] balancer_resource_req_start; +wire [OOO_STATION_NUM - 1 : 0] balancer_resource_req_last; +wire [OOO_STATION_NUM - 1 : 0] balancer_resource_req_ready; + +wire [OOO_STATION_NUM - 1 : 0] balancer_resource_resp_valid; +wire [OOO_RESP_HEAD_WIDTH * OOO_STATION_NUM - 1 : 0] balancer_resource_resp_head; +wire [OOO_RESP_DATA_WIDTH * OOO_STATION_NUM - 1 : 0] balancer_resource_resp_data; +wire [OOO_STATION_NUM - 1 : 0] balancer_resource_resp_start; +wire [OOO_STATION_NUM - 1 : 0] balancer_resource_resp_last; +wire [OOO_STATION_NUM - 1 : 0] balancer_resource_resp_ready; + +wire [OOO_STATION_NUM - 1 : 0] balancer_egress_valid; +wire [EGRESS_HEAD_WIDTH * OOO_STATION_NUM - 1 : 0] balancer_egress_head; +wire [EGRESS_DATA_WIDTH * OOO_STATION_NUM - 1 : 0] balancer_egress_data; +wire [OOO_STATION_NUM - 1 : 0] balancer_egress_start; +wire [OOO_STATION_NUM - 1 : 0] balancer_egress_last; +wire [OOO_STATION_NUM - 1 : 0] balancer_egress_ready; + + +/*------------------------------------------- Local Variables Definition : End --------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : Begin ---------------------------------------*/ +generate + if (OOO_STATION_NUM == 1) begin + assign ingress_ready = balancer_ingress_ready[0]; + + assign resource_resp_ready = balancer_resource_resp_ready[0]; + end + else if(OOO_STATION_NUM == 2) begin + assign ingress_ready = ingress_head[0] == 0 ? balancer_ingress_ready[0] : + ingress_head[0] == 1 ? balancer_ingress_ready[1] : 'd0; + + assign resource_resp_ready = (resource_resp_head[TAG_NUM_LOG - 1 : TAG_NUM_LOG - OOO_STATION_NUM_LOG] == 0) ? balancer_resource_resp_ready[0] : + (resource_resp_head[TAG_NUM_LOG - 1 : TAG_NUM_LOG - OOO_STATION_NUM_LOG] == 1) ? balancer_resource_resp_ready[1] : 'd0; + end + else if(OOO_STATION_NUM == 4) begin + assign ingress_ready = ingress_head[1:0] == 0 ? balancer_ingress_ready[0] : + ingress_head[1:0] == 1 ? balancer_ingress_ready[1] : + ingress_head[1:0] == 2 ? balancer_ingress_ready[2] : + ingress_head[1:0] == 3 ? balancer_ingress_ready[3] : 'd0; + + assign resource_resp_ready = (resource_resp_head[TAG_NUM_LOG - 1 : TAG_NUM_LOG - OOO_STATION_NUM_LOG] == 0) ? balancer_resource_resp_ready[0] : + (resource_resp_head[TAG_NUM_LOG - 1 : TAG_NUM_LOG - OOO_STATION_NUM_LOG] == 1) ? balancer_resource_resp_ready[1] : + (resource_resp_head[TAG_NUM_LOG - 1 : TAG_NUM_LOG - OOO_STATION_NUM_LOG] == 2) ? balancer_resource_resp_ready[2] : + (resource_resp_head[TAG_NUM_LOG - 1 : TAG_NUM_LOG - OOO_STATION_NUM_LOG] == 3) ? balancer_resource_resp_ready[3] :'d0; + end +endgenerate + +generate + if(OOO_STATION_NUM == 1) begin + assign resource_req_valid = balancer_resource_req_valid[0]; + assign resource_req_head = balancer_resource_req_head[OOO_CMD_HEAD_WIDTH * (0 + 1) - 1 : OOO_CMD_HEAD_WIDTH * 0]; + assign resource_req_data = balancer_resource_req_data[OOO_CMD_DATA_WIDTH * (0 + 1) - 1 : OOO_CMD_DATA_WIDTH * 0]; + assign resource_req_start = balancer_resource_req_start[0]; + assign resource_req_last = balancer_resource_req_last[0]; + + assign egress_valid = balancer_egress_valid[0]; + assign egress_head = balancer_egress_head[EGRESS_HEAD_WIDTH * (0 + 1) - 1 : EGRESS_HEAD_WIDTH * 0]; + assign egress_data = balancer_egress_data[EGRESS_DATA_WIDTH * (0 + 1) - 1 : EGRESS_DATA_WIDTH * 0]; + assign egress_start = balancer_egress_start[0]; + assign egress_last = balancer_egress_last[0]; + + assign balancer_resource_req_ready = resource_req_ready; + + assign balancer_egress_ready = egress_ready; + end + else if(OOO_STATION_NUM == 2) begin + assign resource_req_valid = balancer_resource_req_valid[0] ? balancer_resource_req_valid[0] : + balancer_resource_req_valid[1] ? balancer_resource_req_valid[1] : 'd0; + assign resource_req_head = balancer_resource_req_valid[0] ? balancer_resource_req_head[OOO_CMD_HEAD_WIDTH * (0 + 1) - 1 : OOO_CMD_HEAD_WIDTH * 0] : + balancer_resource_req_valid[1] ? balancer_resource_req_head[OOO_CMD_HEAD_WIDTH * (1 + 1) - 1 : OOO_CMD_HEAD_WIDTH * 1] : 'd0; + assign resource_req_data = balancer_resource_req_valid[0] ? balancer_resource_req_data[OOO_CMD_DATA_WIDTH * (0 + 1) - 1 : OOO_CMD_DATA_WIDTH * 0] : + balancer_resource_req_valid[1] ? balancer_resource_req_data[OOO_CMD_DATA_WIDTH * (1 + 1) - 1 : OOO_CMD_DATA_WIDTH * 1] : 'd0; + assign resource_req_start = balancer_resource_req_start[0] ? balancer_resource_req_start[0] : + balancer_resource_req_start[1] ? balancer_resource_req_start[1] : 'd0; + assign resource_req_last = balancer_resource_req_last[0] ? balancer_resource_req_last[0] : + balancer_resource_req_last[1] ? balancer_resource_req_last[1] : 'd0; + + + assign egress_valid = balancer_egress_valid[0] ? balancer_egress_valid[0] : + balancer_egress_valid[1] ? balancer_egress_valid[1] : 'd0; + assign egress_head = balancer_egress_valid[0] ? balancer_egress_head[EGRESS_HEAD_WIDTH * (0 + 1) - 1 : EGRESS_HEAD_WIDTH * 0] : + balancer_egress_valid[1] ? balancer_egress_head[EGRESS_HEAD_WIDTH * (1 + 1) - 1 : EGRESS_HEAD_WIDTH * 1] : 'd0; + assign egress_data = balancer_egress_valid[0] ? balancer_egress_data[EGRESS_DATA_WIDTH * (0 + 1) - 1 : EGRESS_DATA_WIDTH * 0] : + balancer_egress_valid[1] ? balancer_egress_data[EGRESS_DATA_WIDTH * (1 + 1) - 1 : EGRESS_DATA_WIDTH * 1] : 'd0; + assign egress_start = balancer_egress_start[0] ? balancer_egress_start[0] : + balancer_egress_start[1] ? balancer_egress_start[1] : 'd0; + assign egress_last = balancer_egress_last[0] ? balancer_egress_last[0] : + balancer_egress_last[1] ? balancer_egress_last[1] : 'd0; + + + + assign balancer_resource_req_ready[0] = balancer_resource_req_valid[0] ? resource_req_ready : 'd0; + assign balancer_resource_req_ready[1] = balancer_resource_req_valid[0] ? 'd0 : + balancer_resource_req_valid[1] ? resource_req_ready : 'd0; + + assign balancer_egress_ready[0] = balancer_egress_valid[0] ? egress_ready : 'd0; + assign balancer_egress_ready[1] = balancer_egress_valid[0] ? 'd0 : + balancer_egress_valid[1] ? egress_ready : 'd0; + end + else if(OOO_STATION_NUM == 4) begin + assign resource_req_valid = balancer_resource_req_valid[0] ? balancer_resource_req_valid[0] : + balancer_resource_req_valid[1] ? balancer_resource_req_valid[1] : + balancer_resource_req_valid[2] ? balancer_resource_req_valid[2] : + balancer_resource_req_valid[3] ? balancer_resource_req_valid[3] : 'd0; + assign resource_req_head = balancer_resource_req_valid[0] ? balancer_resource_req_head[OOO_CMD_HEAD_WIDTH * (0 + 1) - 1 : OOO_CMD_HEAD_WIDTH * 0] : + balancer_resource_req_valid[1] ? balancer_resource_req_head[OOO_CMD_HEAD_WIDTH * (1 + 1) - 1 : OOO_CMD_HEAD_WIDTH * 1] : + balancer_resource_req_valid[2] ? balancer_resource_req_head[OOO_CMD_HEAD_WIDTH * (2 + 1) - 1 : OOO_CMD_HEAD_WIDTH * 2] : + balancer_resource_req_valid[3] ? balancer_resource_req_head[OOO_CMD_HEAD_WIDTH * (3 + 1) - 1 : OOO_CMD_HEAD_WIDTH * 3] : 'd0; + assign resource_req_data = balancer_resource_req_valid[0] ? balancer_resource_req_data[OOO_CMD_DATA_WIDTH * (0 + 1) - 1 : OOO_CMD_DATA_WIDTH * 0] : + balancer_resource_req_valid[1] ? balancer_resource_req_data[OOO_CMD_DATA_WIDTH * (1 + 1) - 1 : OOO_CMD_DATA_WIDTH * 1] : + balancer_resource_req_valid[2] ? balancer_resource_req_data[OOO_CMD_DATA_WIDTH * (2 + 1) - 1 : OOO_CMD_DATA_WIDTH * 2] : + balancer_resource_req_valid[3] ? balancer_resource_req_data[OOO_CMD_DATA_WIDTH * (3 + 1) - 1 : OOO_CMD_DATA_WIDTH * 3] : 'd0; + assign resource_req_start = balancer_resource_req_start[0] ? balancer_resource_req_start[0] : + balancer_resource_req_start[1] ? balancer_resource_req_start[1] : + balancer_resource_req_start[2] ? balancer_resource_req_start[2] : + balancer_resource_req_start[3] ? balancer_resource_req_start[3] : 'd0; + assign resource_req_last = balancer_resource_req_last[0] ? balancer_resource_req_last[0] : + balancer_resource_req_last[1] ? balancer_resource_req_last[1] : + balancer_resource_req_last[2] ? balancer_resource_req_last[2] : + balancer_resource_req_last[3] ? balancer_resource_req_last[3] : 'd0; + + + assign egress_valid = balancer_egress_valid[0] ? balancer_egress_valid[0] : + balancer_egress_valid[1] ? balancer_egress_valid[1] : + balancer_egress_valid[2] ? balancer_egress_valid[2] : + balancer_egress_valid[3] ? balancer_egress_valid[3] : 'd0; + assign egress_head = balancer_egress_valid[0] ? balancer_egress_head[EGRESS_HEAD_WIDTH * (0 + 1) - 1 : EGRESS_HEAD_WIDTH * 0] : + balancer_egress_valid[1] ? balancer_egress_head[EGRESS_HEAD_WIDTH * (1 + 1) - 1 : EGRESS_HEAD_WIDTH * 1] : + balancer_egress_valid[2] ? balancer_egress_head[EGRESS_HEAD_WIDTH * (2 + 1) - 1 : EGRESS_HEAD_WIDTH * 2] : + balancer_egress_valid[3] ? balancer_egress_head[EGRESS_HEAD_WIDTH * (3 + 1) - 1 : EGRESS_HEAD_WIDTH * 3] : 'd0; + assign egress_data = balancer_egress_valid[0] ? balancer_egress_data[EGRESS_DATA_WIDTH * (0 + 1) - 1 : EGRESS_DATA_WIDTH * 0] : + balancer_egress_valid[1] ? balancer_egress_data[EGRESS_DATA_WIDTH * (1 + 1) - 1 : EGRESS_DATA_WIDTH * 1] : + balancer_egress_valid[2] ? balancer_egress_data[EGRESS_DATA_WIDTH * (2 + 1) - 1 : EGRESS_DATA_WIDTH * 2] : + balancer_egress_valid[3] ? balancer_egress_data[EGRESS_DATA_WIDTH * (3 + 1) - 1 : EGRESS_DATA_WIDTH * 3] : 'd0; + assign egress_start = balancer_egress_start[0] ? balancer_egress_start[0] : + balancer_egress_start[1] ? balancer_egress_start[1] : + balancer_egress_start[2] ? balancer_egress_start[2] : + balancer_egress_start[3] ? balancer_egress_start[3] : 'd0; + assign egress_last = balancer_egress_last[0] ? balancer_egress_last[0] : + balancer_egress_last[1] ? balancer_egress_last[1] : + balancer_egress_last[2] ? balancer_egress_last[2] : + balancer_egress_last[3] ? balancer_egress_last[3] : 'd0; + + + + + + assign balancer_resource_req_ready[0] = balancer_resource_req_valid[0] ? resource_req_ready : 'd0; + assign balancer_resource_req_ready[1] = balancer_resource_req_valid[0] ? 'd0 : + balancer_resource_req_valid[1] ? resource_req_ready : 'd0; + assign balancer_resource_req_ready[2] = balancer_resource_req_valid[0] ? 'd0 : + balancer_resource_req_valid[1] ? 'd0 : + balancer_resource_req_valid[2] ? resource_req_ready : 'd0; + assign balancer_resource_req_ready[3] = balancer_resource_req_valid[0] ? 'd0 : + balancer_resource_req_valid[1] ? 'd0 : + balancer_resource_req_valid[2] ? 'd0 : + balancer_resource_req_valid[3] ? resource_req_ready : 'd0; + + + + assign balancer_egress_ready[0] = balancer_egress_valid[0] ? egress_ready : 'd0; + assign balancer_egress_ready[1] = balancer_egress_valid[0] ? 'd0 : + balancer_egress_valid[1] ? egress_ready : 'd0; + assign balancer_egress_ready[2] = balancer_egress_valid[0] ? 'd0 : + balancer_egress_valid[1] ? 'd0 : + balancer_egress_valid[2] ? egress_ready : 'd0; + assign balancer_egress_ready[3] = balancer_egress_valid[0] ? 'd0 : + balancer_egress_valid[1] ? 'd0 : + balancer_egress_valid[2] ? 'd0 : + balancer_egress_valid[3] ? egress_ready : 'd0; + end +endgenerate + +generate + genvar i; + for(i = 0; i < OOO_STATION_NUM; i++) begin + if(OOO_STATION_NUM == 1) begin + assign balancer_ingress_valid[i] = ingress_valid; + assign balancer_ingress_head[INGRESS_HEAD_WIDTH * (i + 1) - 1 : INGRESS_HEAD_WIDTH * i] = ingress_head; + assign balancer_ingress_data[SLOT_WIDTH * (i + 1) - 1 : SLOT_WIDTH * i] = ingress_data; + assign balancer_ingress_start[i] = ingress_start; + assign balancer_ingress_last[i] = ingress_last; + end + else begin + assign balancer_ingress_valid[i] = (ingress_valid && (ingress_head[OOO_STATION_NUM_LOG - 1 : 0] == i)) ? ingress_valid : 'd0; + assign balancer_ingress_head[INGRESS_HEAD_WIDTH * (i + 1) - 1 : INGRESS_HEAD_WIDTH * i] = (ingress_valid && (ingress_head[OOO_STATION_NUM_LOG - 1 : 0] == i)) ? ingress_head : 'd0; + assign balancer_ingress_data[SLOT_WIDTH * (i + 1) - 1 : SLOT_WIDTH * i] = (ingress_valid && (ingress_head[OOO_STATION_NUM_LOG - 1 : 0] == i)) ? ingress_data : 'd0; + assign balancer_ingress_start[i] = (ingress_valid && (ingress_head[OOO_STATION_NUM_LOG - 1 : 0] == i)) ? ingress_start : 'd0; + assign balancer_ingress_last[i] = (ingress_valid && (ingress_head[OOO_STATION_NUM_LOG - 1 : 0] == i)) ? ingress_last : 'd0; + end + + if(OOO_STATION_NUM == 1) begin + assign balancer_resource_resp_valid[i] = resource_resp_valid; + assign balancer_resource_resp_head[OOO_RESP_HEAD_WIDTH * (i + 1) - 1 : OOO_RESP_HEAD_WIDTH * i] = resource_resp_head; + assign balancer_resource_resp_data[OOO_RESP_DATA_WIDTH * (i + 1) - 1 : OOO_RESP_DATA_WIDTH * i] = resource_resp_data; + assign balancer_resource_resp_start[i] = resource_resp_start; + assign balancer_resource_resp_last[i] = resource_resp_last; + end + else begin + assign balancer_resource_resp_valid[i] = (resource_resp_valid && (resource_resp_head[TAG_NUM_LOG - 1 : TAG_NUM_LOG - OOO_STATION_NUM_LOG] == i)) ? resource_resp_valid : 'd0; + assign balancer_resource_resp_head[OOO_RESP_HEAD_WIDTH * (i + 1) - 1 : OOO_RESP_HEAD_WIDTH * i] = (resource_resp_valid && (resource_resp_head[TAG_NUM_LOG - 1 : TAG_NUM_LOG - OOO_STATION_NUM_LOG] == i)) ? resource_resp_head : 'd0; + assign balancer_resource_resp_data[OOO_RESP_DATA_WIDTH * (i + 1) - 1 : OOO_RESP_DATA_WIDTH * i] = (resource_resp_valid && (resource_resp_head[TAG_NUM_LOG - 1 : TAG_NUM_LOG - OOO_STATION_NUM_LOG] == i)) ? resource_resp_data : 'd0; + assign balancer_resource_resp_start[i] = (resource_resp_valid && (resource_resp_head[TAG_NUM_LOG - 1 : TAG_NUM_LOG - OOO_STATION_NUM_LOG] == i)) ? resource_resp_start : 'd0; + assign balancer_resource_resp_last[i] = (resource_resp_valid && (resource_resp_head[TAG_NUM_LOG - 1 : TAG_NUM_LOG - OOO_STATION_NUM_LOG] == i)) ? resource_resp_last : 'd0; + end + + stream_reg #( + .TUSER_WIDTH( INGRESS_HEAD_WIDTH ), + .TDATA_WIDTH( SLOT_WIDTH ) + ) + ( + .clk ( clk ), + .rst_n ( ~rst ), + + .axis_tvalid ( balancer_ingress_valid[i] ), + .axis_tlast ( balancer_ingress_last[i] ), + .axis_tuser ( balancer_ingress_head[INGRESS_HEAD_WIDTH * (i + 1) - 1 : INGRESS_HEAD_WIDTH * i] ), + .axis_tdata ( balancer_ingress_data[SLOT_WIDTH * (i + 1) - 1 : SLOT_WIDTH * i] ), + .axis_tready ( balancer_ingress_ready[i] ), + .axis_tstart ( balancer_ingress_start[i] ), + .axis_tkeep ( 'd0 ), + + .in_reg_tvalid ( st_ingress_valid[i] ), + .in_reg_tlast ( st_ingress_last[i] ), + .in_reg_tuser ( st_ingress_head[INGRESS_HEAD_WIDTH * (i + 1) - 1 : INGRESS_HEAD_WIDTH * i] ), + .in_reg_tdata ( st_ingress_data[SLOT_WIDTH * (i + 1) - 1 : SLOT_WIDTH * i] ), + .in_reg_tkeep ( ), + .in_reg_tstart ( st_ingress_start[i] ), + .in_reg_tready ( st_ingress_ready[i] ) + ); + + OoOStation #( + .ID ( i ), + + .TAG_NUM ( TAG_NUM / OOO_STATION_NUM ), + .TAG_NUM_LOG ( log2b(TAG_NUM / OOO_STATION_NUM - 1) ), + + .RESOURCE_CMD_HEAD_WIDTH ( RESOURCE_CMD_HEAD_WIDTH ), + .RESOURCE_CMD_DATA_WIDTH ( RESOURCE_CMD_DATA_WIDTH ), + .RESOURCE_RESP_HEAD_WIDTH ( RESOURCE_RESP_HEAD_WIDTH ), + .RESOURCE_RESP_DATA_WIDTH ( RESOURCE_RESP_DATA_WIDTH ), + + .SLOT_NUM ( SLOT_NUM ), + .QUEUE_NUM ( QUEUE_NUM ), + .SLOT_NUM_LOG ( SLOT_NUM_LOG ), + .QUEUE_NUM_LOG ( QUEUE_NUM_LOG ), + + .OOO_CMD_HEAD_WIDTH ( OOO_CMD_HEAD_WIDTH ), + .OOO_CMD_DATA_WIDTH ( OOO_CMD_DATA_WIDTH ), + .OOO_RESP_HEAD_WIDTH ( OOO_RESP_HEAD_WIDTH ), + .OOO_RESP_DATA_WIDTH ( OOO_RESP_DATA_WIDTH ), + + .INGRESS_HEAD_WIDTH ( INGRESS_HEAD_WIDTH ), + .INGRESS_DATA_WIDTH ( INGRESS_DATA_WIDTH ), + + .SLOT_WIDTH ( SLOT_WIDTH ), + + .EGRESS_HEAD_WIDTH ( EGRESS_HEAD_WIDTH ), + .EGRESS_DATA_WIDTH ( EGRESS_DATA_WIDTH ) + ) + ( + .clk ( clk ), + .rst ( rst ), + + .ingress_valid ( st_ingress_valid[i] ), + .ingress_head ( st_ingress_head[INGRESS_HEAD_WIDTH * (i + 1) - 1 : INGRESS_HEAD_WIDTH * i] ), + .ingress_data ( st_ingress_data[SLOT_WIDTH * (i + 1) - 1 : SLOT_WIDTH * i] ), + .ingress_start ( st_ingress_start[i] ), + .ingress_last ( st_ingress_last[i] ), + .ingress_ready ( st_ingress_ready[i] ), + + .resource_req_valid ( balancer_resource_req_valid[i] ), + .resource_req_head ( balancer_resource_req_head[OOO_CMD_HEAD_WIDTH * (i + 1) - 1 : OOO_CMD_HEAD_WIDTH * i] ), + .resource_req_data ( balancer_resource_req_data[OOO_CMD_DATA_WIDTH * (i + 1) - 1 : OOO_CMD_DATA_WIDTH * i] ), + .resource_req_start ( balancer_resource_req_start[i] ), + .resource_req_last ( balancer_resource_req_last[i] ), + .resource_req_ready ( balancer_resource_req_ready[i] ), + + .resource_resp_valid ( balancer_resource_resp_valid[i] ), + .resource_resp_head ( balancer_resource_resp_head[OOO_RESP_HEAD_WIDTH * (i + 1) - 1 : OOO_RESP_HEAD_WIDTH * i] ), + .resource_resp_data ( balancer_resource_resp_data[OOO_RESP_DATA_WIDTH * (i + 1) - 1 : OOO_RESP_DATA_WIDTH * i] ), + .resource_resp_start ( balancer_resource_resp_start[i] ), + .resource_resp_last ( balancer_resource_resp_last[i] ), + .resource_resp_ready ( balancer_resource_resp_ready[i] ), + + .egress_valid ( balancer_egress_valid[i] ), + .egress_head ( balancer_egress_head[EGRESS_HEAD_WIDTH * (i + 1) - 1 : EGRESS_HEAD_WIDTH * i] ), + .egress_data ( balancer_egress_data[EGRESS_DATA_WIDTH * (i + 1) - 1 : EGRESS_DATA_WIDTH * i] ), + .egress_start ( balancer_egress_start[i] ), + .egress_last ( balancer_egress_last[i] ), + .egress_ready ( balancer_egress_ready[i] ) + ); + end +endgenerate + +/*------------------------------------------- Submodules Instatiation : End -----------------------------------------*/ + +/*------------------------------------------- State Machine Definition : Begin --------------------------------------*/ +/*------------------------------------------- State Machine Definition : End ----------------------------------------*/ + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ + + +/*------------------------------------------- Variables Decode : End ------------------------------------------------*/ + +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Peripherals/OoOStation/OoOStation.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Peripherals/OoOStation/OoOStation.v new file mode 100644 index 0000000000000000000000000000000000000000..99df086096eb52003046d576957fae0a4a1817a0 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Peripherals/OoOStation/OoOStation.v @@ -0,0 +1,549 @@ +/*------------------------------------------- Module Description : Begin ---------------------------------------------- +Name: OoOStation +Author: YangFan +Function: OoOStation is short for Out-of-Order station. + This module is a special abstraction aimed at solving Head-Of-Line Problem in Stateful Pipeline. + OoOStation accepts resources request and manages out-of-order request and resposne. + User can carry user-defined data with request, when desired resource is available, OoOStation will return resources with user-defined data. + For example, as for ReqTransEngine, the request is accompanied with WQE metadata, as for RespRecvControl, the request is accompanied with packet. + OoOStation does not care about what the req and resource are, it just handles out-of-order execution. + Typically, OoOStation interacts with two three threads: ingress thread, egress thread and resource mgt thread. + Ingress thread: Asynchronously issues resource request to OoOStation. + Egress thread: Accept resources from OoOStation and triggers next pipeline stage. + Resource mgt thread: Manage resources and respond to resource request. +--------------------------------------------- Module Decription : End -----------------------------------------------*/ + +/*------------------------------------------- Timescale Definition : Begin ------------------------------------------*/ +`timescale 1ns / 1ps +/*------------------------------------------- Timescale Definition : End --------------------------------------------*/ + +/*------------------------------------------- Included Files : Begin ------------------------------------------------*/ +`include "common_function_def.vh" +/*------------------------------------------- Included Files : End --------------------------------------------------*/ + +/*------------------------------------------- Local Macros Definition : Begin ---------------------------------------*/ +/*------------------------------------------- Local Macros Definition : End -----------------------------------------*/ + +/*------------------------------------------- Input/Output Definition : Begin ---------------------------------------*/ +module OoOStation #( + parameter ID = 1, + + //TAG_NUM is not equal to SLOT_NUM, since each resource req consumes 1 tag, and it may require more than 1 slot. + parameter TAG_NUM = 32, + parameter TAG_NUM_LOG = log2b(TAG_NUM - 1), + + + //RESOURCE_CMD/RESP_WIDTH is resource-specific + //For example, MR resource cmd format is {PD, LKey, Lengtg, Addr}, MR resource reply format is {PTE-1, PTE-0, indicator} + parameter RESOURCE_CMD_HEAD_WIDTH = 128, + parameter RESOURCE_CMD_DATA_WIDTH = 256, + parameter RESOURCE_RESP_HEAD_WIDTH = 128, + parameter RESOURCE_RESP_DATA_WIDTH = 128, + + parameter SLOT_NUM = 512, + parameter QUEUE_NUM = 32, + parameter SLOT_NUM_LOG = log2b(SLOT_NUM - 1), + parameter QUEUE_NUM_LOG = log2b(QUEUE_NUM - 1), + + //When issuing cmd to Resource Manager, add tag index + parameter OOO_CMD_HEAD_WIDTH = `MAX_REQ_TAG_NUM_LOG + RESOURCE_CMD_HEAD_WIDTH, + parameter OOO_CMD_DATA_WIDTH = RESOURCE_CMD_DATA_WIDTH, + parameter OOO_RESP_HEAD_WIDTH = `MAX_REQ_TAG_NUM_LOG + RESOURCE_RESP_HEAD_WIDTH, + parameter OOO_RESP_DATA_WIDTH = RESOURCE_RESP_DATA_WIDTH, + + parameter INGRESS_HEAD_WIDTH = RESOURCE_CMD_HEAD_WIDTH + `INGRESS_COMMON_HEAD_WIDTH, + //INGRESS_DATA_WIDTH is ingress-thread-specific + parameter INGRESS_DATA_WIDTH = 512, + + parameter SLOT_WIDTH = INGRESS_DATA_WIDTH, + + + //Egress thread + parameter EGRESS_HEAD_WIDTH = RESOURCE_RESP_HEAD_WIDTH + `EGRESS_COMMON_HEAD_WIDTH, + parameter EGRESS_DATA_WIDTH = INGRESS_DATA_WIDTH +) +( + input wire clk, + input wire rst, + + input wire ingress_valid, + //Head format: + //{tag index, required slot number, queue index} + input wire [INGRESS_HEAD_WIDTH - 1 : 0] ingress_head, + //Data format: + //This is defined by Ingress thread, OoOStation doesn't care about it. + //Typically ingress_data represents the Metadata/Packet associated with current resource request + input wire [SLOT_WIDTH - 1 : 0] ingress_data, + input wire ingress_start, + input wire ingress_last, + output wire ingress_ready, + + output wire [SLOT_NUM_LOG : 0] available_slot_num, + + output wire resource_req_valid, + //Head format: + //{resource cmd, tag index} + output wire [OOO_CMD_HEAD_WIDTH - 1 : 0] resource_req_head, + //Typically null + output wire [OOO_CMD_DATA_WIDTH - 1 : 0] resource_req_data, + output wire resource_req_start, + output wire resource_req_last, + input wire resource_req_ready, + + input wire resource_resp_valid, + //Head format: + //{tag index} + input wire [OOO_RESP_HEAD_WIDTH - 1 : 0] resource_resp_head, + //Data form ： + //Defined by resource mgt + input wire [OOO_RESP_DATA_WIDTH - 1 : 0] resource_resp_data, + input wire resource_resp_start, + input wire resource_resp_last, + output wire resource_resp_ready, + + output wire egress_valid, + //Head format: + //{resource, queue index} + output wire [EGRESS_HEAD_WIDTH - 1 : 0] egress_head, + //Data format: + //Same as ingress data + output wire [EGRESS_DATA_WIDTH - 1 : 0] egress_data, + output wire egress_start, + output wire egress_last, + input wire egress_ready +); +/*------------------------------------------- Input/Output Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Variables Definition : Begin ------------------------------------*/ +wire [OOO_CMD_HEAD_WIDTH - 1 : 0] resource_req_head_balancer; +wire [OOO_RESP_HEAD_WIDTH - 1 : 0] resource_resp_head_balancer; + +wire [`MAX_REQ_TAG_NUM_LOG - 1 : 0] req_tag; +wire [`MAX_REQ_TAG_NUM_LOG - 1 : 0] resp_tag; + +wire [`MAX_REQ_TAG_NUM_LOG - 1 : 0] req_tag_balancer; +wire [`MAX_REQ_TAG_NUM_LOG - 1 : 0] resp_tag_balancer; + +assign req_tag = resource_req_head_balancer[`MAX_REQ_TAG_NUM_LOG - 1 : 0]; +assign resp_tag = resource_resp_head[`MAX_REQ_TAG_NUM_LOG - 1 : 0]; + +assign req_tag_balancer = (ID == 0) ? req_tag : + (ID == 1) ? {'d0, 1'b1, req_tag[TAG_NUM_LOG - 1 : 0]} : + (ID == 2) ? {'d0, 2'b10, req_tag[TAG_NUM_LOG - 1 : 0]} : + (ID == 3) ? {'d0, 3'b11, req_tag[TAG_NUM_LOG - 1 : 0]} : req_tag; +assign resp_tag_balancer = (ID == 0) ? resp_tag : + (ID == 1) ? {'d0, resp_tag[TAG_NUM_LOG - 1 : 0]} : + (ID == 2) ? {'d0, resp_tag[TAG_NUM_LOG - 1 : 0]} : + (ID ==3) ? {'d0, resp_tag[TAG_NUM_LOG - 1 : 0]} : resp_tag; + + + +assign resource_req_head = {resource_req_head_balancer[OOO_CMD_HEAD_WIDTH - 1 : `MAX_REQ_TAG_NUM_LOG], req_tag_balancer}; +assign resource_resp_head_balancer = {resource_resp_head[OOO_RESP_HEAD_WIDTH - 1 : `MAX_REQ_TAG_NUM_LOG], resp_tag_balancer}; + + +wire tag_fifo_wr_en; +wire [TAG_NUM_LOG - 1 : 0] tag_fifo_din; +wire tag_fifo_prog_full; +wire tag_fifo_empty; +wire [TAG_NUM_LOG - 1 : 0] tag_fifo_dout; +wire tag_fifo_rd_en; + +wire reorder_buffer_wea; +wire [TAG_NUM_LOG - 1 : 0] reorder_buffer_addra; +wire [RESOURCE_RESP_DATA_WIDTH + 1 - 1 : 0] reorder_buffer_dina; + +wire [TAG_NUM_LOG - 1 : 0] reorder_buffer_addrb; +wire [RESOURCE_RESP_DATA_WIDTH + 1 - 1 : 0] reorder_buffer_doutb; + +wire tag_mapping_wea; +wire [TAG_NUM_LOG - 1 : 0] tag_mapping_addra; +wire [QUEUE_NUM_LOG + 1 - 1 : 0] tag_mapping_dina; + +wire [TAG_NUM_LOG - 1 : 0] tag_mapping_addrb; +wire [QUEUE_NUM_LOG + 1 - 1 : 0] tag_mapping_doutb; + +wire enqueue_req_valid; +wire [`MAX_QP_NUM_LOG + `MAX_OOO_SLOT_NUM_LOG - 1 : 0] enqueue_req_head; +wire enqueue_req_start; +wire enqueue_req_last; +wire [SLOT_WIDTH - 1 : 0] enqueue_req_data; +wire enqueue_req_ready; + +wire empty_req_valid; +wire [`MAX_QP_NUM_LOG - 1 : 0] empty_req_head; +wire empty_req_ready; +wire empty_resp_valid; +wire [`MAX_QP_NUM_LOG : 0] empty_resp_head; +wire empty_resp_ready; + +wire dequeue_req_valid; +wire [`MAX_QP_NUM_LOG + `MAX_OOO_SLOT_NUM_LOG - 1 : 0] dequeue_req_head; +wire dequeue_req_ready; +wire dequeue_resp_valid; +wire dequeue_resp_ready; +wire [SLOT_WIDTH - 1 : 0] dequeue_resp_data; + +wire get_req_valid; +wire [`MAX_OOO_SLOT_NUM_LOG + `MAX_QP_NUM_LOG - 1 : 0] get_req_head; +wire get_req_ready; +wire get_resp_valid; +wire get_resp_empty; +wire [`MAX_OOO_SLOT_NUM_LOG + `MAX_QP_NUM_LOG - 1 : 0] get_resp_head; +wire get_resp_ready; +wire [SLOT_WIDTH - 1 : 0] get_resp_data; + +wire bypass_egress_valid; +wire [EGRESS_HEAD_WIDTH - 1 : 0] bypass_egress_head; +wire [EGRESS_DATA_WIDTH - 1 : 0] bypass_egress_data; +wire bypass_egress_start; +wire bypass_egress_last; +wire bypass_egress_ready; + +wire normal_egress_valid; +wire [EGRESS_HEAD_WIDTH - 1 : 0] normal_egress_head; +wire [EGRESS_DATA_WIDTH - 1 : 0] normal_egress_data; +wire normal_egress_start; +wire normal_egress_last; +wire normal_egress_ready; +/*------------------------------------------- Local Variables Definition : End --------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : Begin ---------------------------------------*/ +SyncFIFO_Template #( + .FIFO_TYPE ( 0 ), + .FIFO_WIDTH ( `DEFAULT_REQ_TAG_NUM_LOG ), + .FIFO_DEPTH ( `DEFAULT_REQ_TAG_NUM ) +) +ooo_tag_fifo +( + .clk ( clk ), + .rst ( rst ), + + .wr_en ( tag_fifo_wr_en ), + .din ( tag_fifo_din ), + .prog_full ( tag_fifo_prog_full ), + .rd_en ( tag_fifo_rd_en ), + .dout ( tag_fifo_dout ), + .empty ( tag_fifo_empty ), + .data_count ( ) +); + +SRAM_SDP_Template #( + .RAM_WIDTH ( RESOURCE_RESP_DATA_WIDTH + 1 ), //1-bit to indicate whether this slot is valid. + .RAM_DEPTH ( `DEFAULT_REQ_TAG_NUM ) +) +ReorderBuffer +( + .clk ( clk ), + .rst ( rst ), + + .wea ( reorder_buffer_wea ), + .addra ( reorder_buffer_addra ), + .dina ( reorder_buffer_dina ), + + .addrb ( reorder_buffer_addrb ), + .doutb ( reorder_buffer_doutb ) +); + +SRAM_SDP_Template #( + .RAM_WIDTH ( QUEUE_NUM_LOG ), //Each tag is mapped to a QP + .RAM_DEPTH ( `DEFAULT_REQ_TAG_NUM ) +) +TagMappingTable +( + .clk ( clk ), + .rst ( rst ), + + .wea ( tag_mapping_wea ), + .addra ( tag_mapping_addra ), + .dina ( tag_mapping_dina ), + + .addrb ( tag_mapping_addrb ), + .doutb ( tag_mapping_doutb ) +); + +DynamicMultiQueue #( + .SLOT_WIDTH ( SLOT_WIDTH ), + .SLOT_NUM ( SLOT_NUM ), + .QUEUE_NUM ( QUEUE_NUM ) +) +ReservationStation +( + .clk ( clk ), + .rst ( rst ), + + .ov_available_slot_num ( available_slot_num ), + + .i_enqueue_req_valid ( enqueue_req_valid ), + .iv_enqueue_req_head ( enqueue_req_head ), + .iv_enqueue_req_data ( enqueue_req_data ), + .i_enqueue_req_start ( enqueue_req_start ), + .i_enqueue_req_last ( enqueue_req_last ), + .o_enqueue_req_ready ( enqueue_req_ready ), + + .i_empty_req_valid ( empty_req_valid ), + .iv_empty_req_head ( empty_req_head ), + .o_empty_req_ready ( empty_req_ready ), + + .o_empty_resp_valid ( empty_resp_valid ), + .ov_empty_resp_head ( empty_resp_head ), + .i_empty_resp_ready ( empty_resp_ready ), + + .i_dequeue_req_valid ( dequeue_req_valid ), + .iv_dequeue_req_head ( dequeue_req_head ), + .o_dequeue_req_ready ( dequeue_req_ready ), + + .o_dequeue_resp_valid ( dequeue_resp_valid ), + .ov_dequeue_resp_head ( dequeue_resp_head ), + .o_dequeue_resp_start ( dequeue_resp_start ), + .o_dequeue_resp_last ( dequeue_resp_last ), + .i_dequeue_resp_ready ( dequeue_resp_ready ), + .ov_dequeue_resp_data ( dequeue_resp_data ), + + .i_modify_head_req_valid ( 1'b0 ), + .iv_modify_head_req_head ( {QUEUE_NUM_LOG{1'b0}} ), + .iv_modify_head_req_data ( {SLOT_WIDTH{1'b0}} ), + .o_modify_head_req_ready ( ), + + .i_get_req_valid ( get_req_valid ), + .iv_get_req_head ( get_req_head ), + .o_get_req_ready ( get_req_ready ), + + .o_get_resp_valid ( get_resp_valid ), + .ov_get_resp_head ( get_resp_head ), + .o_get_resp_start ( ), + .o_get_resp_last ( ), + .o_get_resp_empty ( get_resp_empty ), + .i_get_resp_ready ( get_resp_ready ), + .ov_get_resp_data ( get_resp_data ) +); + +OoOStation_Thread_1 #( + .ID ( ID ), + + .TAG_NUM ( TAG_NUM ), + .TAG_NUM_LOG ( TAG_NUM_LOG ), + + .RESOURCE_CMD_HEAD_WIDTH ( RESOURCE_CMD_HEAD_WIDTH ), + .RESOURCE_CMD_DATA_WIDTH ( RESOURCE_CMD_DATA_WIDTH ), + .RESOURCE_RESP_HEAD_WIDTH ( RESOURCE_RESP_HEAD_WIDTH ), + .RESOURCE_RESP_DATA_WIDTH ( RESOURCE_RESP_DATA_WIDTH ), + + .SLOT_NUM ( SLOT_NUM ), + .QUEUE_NUM ( QUEUE_NUM ), + .SLOT_NUM_LOG ( SLOT_NUM_LOG ), + .QUEUE_NUM_LOG ( QUEUE_NUM_LOG ), + + .OOO_CMD_HEAD_WIDTH ( OOO_CMD_HEAD_WIDTH ), + .OOO_CMD_DATA_WIDTH ( OOO_CMD_DATA_WIDTH ), + .OOO_RESP_HEAD_WIDTH ( OOO_RESP_HEAD_WIDTH ), + .OOO_RESP_DATA_WIDTH ( OOO_RESP_DATA_WIDTH ), + + .INGRESS_HEAD_WIDTH ( INGRESS_HEAD_WIDTH ), + .INGRESS_DATA_WIDTH ( INGRESS_DATA_WIDTH ), + + .SLOT_WIDTH ( SLOT_WIDTH ), + + .EGRESS_HEAD_WIDTH ( EGRESS_HEAD_WIDTH ), + .EGRESS_DATA_WIDTH ( EGRESS_DATA_WIDTH ) +) +OoOStation_Thread_1_Inst +( + .clk ( clk ), + .rst ( rst ), + + .ingress_valid ( ingress_valid ), + .ingress_head ( ingress_head ), + .ingress_data ( ingress_data ), + .ingress_start ( ingress_start ), + .ingress_last ( ingress_last ), + .ingress_ready ( ingress_ready ), + + .resource_req_valid ( resource_req_valid ), + .resource_req_head ( resource_req_head_balancer ), + .resource_req_data ( resource_req_data ), + .resource_req_start ( resource_req_start ), + .resource_req_last ( resource_req_last ), + .resource_req_ready ( resource_req_ready ), + + .tag_fifo_empty ( tag_fifo_empty ), + .tag_fifo_dout ( tag_fifo_dout ), + .tag_fifo_rd_en ( tag_fifo_rd_en ), + + .tag_mapping_wea ( tag_mapping_wea ), + .tag_mapping_addra ( tag_mapping_addra ), + .tag_mapping_dina ( tag_mapping_dina ), + + .available_slot_num ( available_slot_num ), + + .empty_req_valid ( empty_req_valid ), + .empty_req_head ( empty_req_head ), + .empty_req_ready ( empty_req_ready ), + + .empty_resp_valid ( empty_resp_valid ), + .empty_resp_head ( empty_resp_head ), + .empty_resp_ready ( empty_resp_ready ), + + .enqueue_req_valid ( enqueue_req_valid ), + .enqueue_req_head ( enqueue_req_head ), + .enqueue_req_start ( enqueue_req_start ), + .enqueue_req_last ( enqueue_req_last ), + .enqueue_req_data ( enqueue_req_data ), + .enqueue_req_ready ( enqueue_req_ready ), + + .egress_valid ( bypass_egress_valid ), + .egress_head ( bypass_egress_head ), + .egress_data ( bypass_egress_data ), + .egress_start ( bypass_egress_start ), + .egress_last ( bypass_egress_last ), + .egress_ready ( bypass_egress_ready ) +); + +OoOStation_Thread_2 #( + .ID ( ID ), + + .TAG_NUM ( TAG_NUM ), + .TAG_NUM_LOG ( TAG_NUM_LOG ), + + .RESOURCE_CMD_HEAD_WIDTH ( RESOURCE_CMD_HEAD_WIDTH ), + .RESOURCE_CMD_DATA_WIDTH ( RESOURCE_CMD_DATA_WIDTH ), + .RESOURCE_RESP_HEAD_WIDTH ( RESOURCE_RESP_HEAD_WIDTH ), + .RESOURCE_RESP_DATA_WIDTH ( RESOURCE_RESP_DATA_WIDTH ), + + .SLOT_NUM ( SLOT_NUM ), + .QUEUE_NUM ( QUEUE_NUM ), + .SLOT_NUM_LOG ( SLOT_NUM_LOG ), + .QUEUE_NUM_LOG ( QUEUE_NUM_LOG ), + + .OOO_CMD_HEAD_WIDTH ( OOO_CMD_HEAD_WIDTH ), + .OOO_CMD_DATA_WIDTH ( OOO_CMD_DATA_WIDTH ), + .OOO_RESP_HEAD_WIDTH ( OOO_RESP_HEAD_WIDTH ), + .OOO_RESP_DATA_WIDTH ( OOO_RESP_DATA_WIDTH ), + + .INGRESS_HEAD_WIDTH ( INGRESS_HEAD_WIDTH ), + .INGRESS_DATA_WIDTH ( INGRESS_DATA_WIDTH ), + + .SLOT_WIDTH ( SLOT_WIDTH ), + + .EGRESS_HEAD_WIDTH ( EGRESS_HEAD_WIDTH ), + .EGRESS_DATA_WIDTH ( EGRESS_DATA_WIDTH ) +) +OoOStation_Thread_2_Inst +( + .clk ( clk ), + .rst ( rst ), + + .resource_resp_valid ( resource_resp_valid ), + .resource_resp_head ( resource_resp_head_balancer ), + .resource_resp_data ( resource_resp_data ), + .resource_resp_start ( resource_resp_start ), + .resource_resp_last ( resource_resp_last ), + .resource_resp_ready ( resource_resp_ready ), + + .get_req_valid ( get_req_valid ), + .get_req_head ( get_req_head ), + .get_req_ready ( get_req_ready ), + + .get_resp_valid ( get_resp_valid ), + .get_resp_empty ( get_resp_empty ), + .get_resp_data ( get_resp_data ), + .get_resp_ready ( get_resp_ready ), + + .dequeue_req_valid ( dequeue_req_valid ), + .dequeue_req_head ( dequeue_req_head ), + .dequeue_req_ready ( dequeue_req_ready ), + + .dequeue_resp_valid ( dequeue_resp_valid ), + .dequeue_resp_head ( dequeue_resp_head ), + .dequeue_resp_start ( dequeue_resp_start ), + .dequeue_resp_last ( dequeue_resp_last ), + .dequeue_resp_data ( dequeue_resp_data ), + .dequeue_resp_ready ( dequeue_resp_ready ), + + .reorder_buffer_wea ( reorder_buffer_wea ), + .reorder_buffer_addra ( reorder_buffer_addra ), + .reorder_buffer_dina ( reorder_buffer_dina ), + + .reorder_buffer_addrb ( reorder_buffer_addrb ), + .reorder_buffer_doutb ( reorder_buffer_doutb ), + + .tag_fifo_wr_en ( tag_fifo_wr_en ), + .tag_fifo_din ( tag_fifo_din ), + .tag_fifo_prog_full ( tag_fifo_prog_full ), + + .tag_mapping_addrb ( tag_mapping_addrb ), + .tag_mapping_doutb ( tag_mapping_doutb ), + + .egress_valid ( normal_egress_valid ), + .egress_head ( normal_egress_head ), + .egress_data ( normal_egress_data ), + .egress_start ( normal_egress_start ), + .egress_last ( normal_egress_last ), + .egress_ready ( normal_egress_ready ) +); + +OoOStation_Thread_3 #( + .ID ( ID ), + + .TAG_NUM ( TAG_NUM ), + .TAG_NUM_LOG ( TAG_NUM_LOG ), + + .RESOURCE_CMD_HEAD_WIDTH ( RESOURCE_CMD_HEAD_WIDTH ), + .RESOURCE_CMD_DATA_WIDTH ( RESOURCE_CMD_DATA_WIDTH ), + .RESOURCE_RESP_HEAD_WIDTH ( RESOURCE_RESP_HEAD_WIDTH ), + .RESOURCE_RESP_DATA_WIDTH ( RESOURCE_RESP_DATA_WIDTH ), + + .SLOT_NUM ( SLOT_NUM ), + .QUEUE_NUM ( QUEUE_NUM ), + .SLOT_NUM_LOG ( SLOT_NUM_LOG ), + .QUEUE_NUM_LOG ( QUEUE_NUM_LOG ), + + .OOO_CMD_HEAD_WIDTH ( OOO_CMD_HEAD_WIDTH ), + .OOO_CMD_DATA_WIDTH ( OOO_CMD_DATA_WIDTH ), + .OOO_RESP_HEAD_WIDTH ( OOO_RESP_HEAD_WIDTH ), + .OOO_RESP_DATA_WIDTH ( OOO_RESP_DATA_WIDTH ), + + .INGRESS_HEAD_WIDTH ( INGRESS_HEAD_WIDTH ), + .INGRESS_DATA_WIDTH ( INGRESS_DATA_WIDTH ), + + .SLOT_WIDTH ( SLOT_WIDTH ), + + .EGRESS_HEAD_WIDTH ( EGRESS_HEAD_WIDTH ), + .EGRESS_DATA_WIDTH ( EGRESS_DATA_WIDTH ) +) +OoOStation_Thread_3_Inst +( + .clk ( clk ), + .rst ( rst ), + + .bypass_egress_valid ( bypass_egress_valid ), + .bypass_egress_head ( bypass_egress_head ), + .bypass_egress_data ( bypass_egress_data ), + .bypass_egress_start ( bypass_egress_start ), + .bypass_egress_last ( bypass_egress_last ), + .bypass_egress_ready ( bypass_egress_ready ), + + .normal_egress_valid ( normal_egress_valid ), + .normal_egress_head ( normal_egress_head ), + .normal_egress_data ( normal_egress_data ), + .normal_egress_start ( normal_egress_start ), + .normal_egress_last ( normal_egress_last ), + .normal_egress_ready ( normal_egress_ready ), + + .egress_valid ( egress_valid ), + .egress_head ( egress_head ), + .egress_data ( egress_data ), + .egress_start ( egress_start ), + .egress_last ( egress_last ), + .egress_ready ( egress_ready ) +); + +/*------------------------------------------- Submodules Instatiation : End -----------------------------------------*/ + +/*------------------------------------------- State Machine Definition : Begin --------------------------------------*/ +/*------------------------------------------- State Machine Definition : End ----------------------------------------*/ + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ +/*------------------------------------------- Variables Decode : End ------------------------------------------------*/ + +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Peripherals/OoOStation/OoOStation_Thread_1.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Peripherals/OoOStation/OoOStation_Thread_1.v new file mode 100644 index 0000000000000000000000000000000000000000..5f734224bcd9181b41e74d57ee9694ac44b8fa3f --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Peripherals/OoOStation/OoOStation_Thread_1.v @@ -0,0 +1,359 @@ +/*------------------------------------------- Module Description : Begin ---------------------------------------------- +Name: OoOStation_Thread_1 +Author: YangFan +Function: Handles Ingress Request. Enqueue Request to ReservationStation and issue resource command. +--------------------------------------------- Module Decription : End -----------------------------------------------*/ + +/*------------------------------------------- Timescale Definition : Begin ------------------------------------------*/ +`timescale 1ns / 1ps +/*------------------------------------------- Timescale Definition : End --------------------------------------------*/ + +/*------------------------------------------- Included Files : Begin ------------------------------------------------*/ +`include "common_function_def.vh" +/*------------------------------------------- Included Files : End --------------------------------------------------*/ + +/*------------------------------------------- Local Macros Definition : Begin ---------------------------------------*/ +/*------------------------------------------- Local Macros Definition : End -----------------------------------------*/ + +/*------------------------------------------- Input/Output Definition : Begin ---------------------------------------*/ +module OoOStation_Thread_1 #( + parameter ID = 1, + + //TAG_NUM is not equal to SLOT_NUM, since each resource req consumes 1 tag, and it may require more than 1 slot. + parameter TAG_NUM = 64, + parameter TAG_NUM_LOG = log2b(TAG_NUM - 1), + + + //RESOURCE_CMD/RESP_WIDTH is resource-specific + //For example, MR resource cmd format is {PD, LKey, Lengtg, Addr}, MR resource reply format is {PTE-1, PTE-0, indicator} + parameter RESOURCE_CMD_HEAD_WIDTH = 128, + parameter RESOURCE_CMD_DATA_WIDTH = 256, + parameter RESOURCE_RESP_HEAD_WIDTH = 128, + parameter RESOURCE_RESP_DATA_WIDTH = 128, + + parameter SLOT_NUM = 512, + parameter QUEUE_NUM = 32, + parameter SLOT_NUM_LOG = log2b(SLOT_NUM - 1), + parameter QUEUE_NUM_LOG = log2b(QUEUE_NUM - 1), + + //When issuing cmd to Resource Manager, add tag index + parameter OOO_CMD_HEAD_WIDTH = TAG_NUM_LOG + RESOURCE_CMD_HEAD_WIDTH, + parameter OOO_CMD_DATA_WIDTH = RESOURCE_CMD_DATA_WIDTH, + parameter OOO_RESP_HEAD_WIDTH = TAG_NUM_LOG + RESOURCE_RESP_HEAD_WIDTH, + parameter OOO_RESP_DATA_WIDTH = RESOURCE_RESP_DATA_WIDTH, + + parameter INGRESS_HEAD_WIDTH = RESOURCE_CMD_HEAD_WIDTH + SLOT_NUM_LOG + QUEUE_NUM_LOG + 1, + //INGRESS_DATA_WIDTH is ingress-thread-specific + parameter INGRESS_DATA_WIDTH = 512, + + parameter SLOT_WIDTH = INGRESS_DATA_WIDTH, + + + //Egress thread + parameter EGRESS_HEAD_WIDTH = RESOURCE_RESP_HEAD_WIDTH + SLOT_NUM_LOG + QUEUE_NUM_LOG, + parameter EGRESS_DATA_WIDTH = INGRESS_DATA_WIDTH +) +( + input wire clk, + input wire rst, + +//Interface with resource requester + input wire ingress_valid, + input wire [INGRESS_HEAD_WIDTH - 1 : 0] ingress_head, + input wire [SLOT_WIDTH - 1 : 0] ingress_data, + input wire ingress_start, + input wire ingress_last, + output wire ingress_ready, + +//Interface with Resource Manager + output wire resource_req_valid, + output wire [OOO_CMD_HEAD_WIDTH - 1 : 0] resource_req_head, + output wire [OOO_CMD_DATA_WIDTH - 1 : 0] resource_req_data, + output wire resource_req_start, + output wire resource_req_last, + input wire resource_req_ready, + +//Interface with Tag FIFO + input wire tag_fifo_empty, + input wire [TAG_NUM_LOG - 1 : 0] tag_fifo_dout, + output wire tag_fifo_rd_en, + +//Interface with Tag-QP mapping table + output wire tag_mapping_wea, + output wire [TAG_NUM_LOG - 1 : 0] tag_mapping_addra, + output wire [QUEUE_NUM_LOG + 1 - 1 : 0] tag_mapping_dina, + +//Interface with ReservationStation + input wire [`MAX_OOO_SLOT_NUM_LOG : 0] available_slot_num, + + output wire empty_req_valid, + output wire [`MAX_QP_NUM_LOG - 1 : 0] empty_req_head, + input wire empty_req_ready, + + input wire empty_resp_valid, + input wire [`MAX_QP_NUM_LOG : 0] empty_resp_head, + output wire empty_resp_ready, + + + output wire enqueue_req_valid, + output wire [`MAX_QP_NUM_LOG + `MAX_OOO_SLOT_NUM_LOG - 1 : 0] enqueue_req_head, + output wire enqueue_req_start, + output wire enqueue_req_last, + output wire [SLOT_WIDTH - 1 : 0] enqueue_req_data, + input wire enqueue_req_ready, + +//Interface with the following pipeline stage, used for bypass mode + output wire egress_valid, + output wire [EGRESS_HEAD_WIDTH - 1 : 0] egress_head, + output wire [EGRESS_DATA_WIDTH - 1 : 0] egress_data, + output wire egress_start, + output wire egress_last, + input wire egress_ready +); +/*------------------------------------------- Input/Output Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Macros Definition : Begin ---------------------------------------*/ +`define QUEUE_INDEX_OFFSET `MAX_QP_NUM_LOG - 1:0 +`define SLOT_NUM_OFFSET `MAX_OOO_SLOT_NUM_LOG + `MAX_QP_NUM_LOG - 1: `MAX_QP_NUM_LOG +`define BYPASS_OFFSET `MAX_OOO_SLOT_NUM_LOG + `MAX_QP_NUM_LOG +`define RESOURCE_REQ_OFFSET INGRESS_HEAD_WIDTH - 1 : `INGRESS_COMMON_HEAD_WIDTH +`define EMPTY_INDICATOR_OFFSET `MAX_QP_NUM_LOG +/*------------------------------------------- Local Macros Definition : End -----------------------------------------*/ + + +/*------------------------------------------- Local Variables Definition : Begin ------------------------------------*/ +reg [`MAX_QP_NUM_LOG - 1 : 0] queue_index; +reg [`MAX_OOO_SLOT_NUM_LOG - 1 : 0] slot_num; +reg [0:0] bypass_mode; +reg [RESOURCE_CMD_HEAD_WIDTH - 1 : 0] resource_req; + +wire queue_empty; + +wire [`MAX_REQ_TAG_NUM_LOG - 1 : 0] req_tag; +/*------------------------------------------- Local Variables Definition : End --------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : Begin ---------------------------------------*/ +/*------------------------------------------- Submodules Instatiation : End -----------------------------------------*/ + +/*------------------------------------------- State Machine Definition : Begin --------------------------------------*/ +reg [2:0] cur_state; +reg [2:0] next_state; + +parameter [2:0] IDLE_s = 3'd1, + JUDGE_s = 3'd2, + ENQUEUE_META_s = 3'd3, + ENQUEUE_DATA_s = 3'd4, + RESOURCE_REQ_s = 3'd5, + BYPASS_s = 3'd6; + +always @(posedge clk or posedge rst) begin + if(rst) begin + cur_state <= IDLE_s; + end + else begin + cur_state <= next_state; + end +end + +always @(*) begin + case(cur_state) + IDLE_s: if(ingress_valid && ingress_head[`SLOT_NUM_OFFSET] <= available_slot_num && !tag_fifo_empty) begin + if(empty_req_valid && empty_req_ready) begin + next_state = JUDGE_s; + end + else begin + next_state = IDLE_s; + end + end + else begin + next_state = IDLE_s; + end + JUDGE_s: if(empty_resp_valid) begin + if(!bypass_mode) begin + next_state = ENQUEUE_META_s; + end + else if(bypass_mode && !queue_empty) begin + next_state = ENQUEUE_META_s; + end + else if(bypass_mode && queue_empty) begin + next_state = BYPASS_s; + end + else begin + next_state = IDLE_s; + end + end + else begin + next_state = JUDGE_s; + end + ENQUEUE_META_s: if(enqueue_req_valid && enqueue_req_ready) begin + next_state = ENQUEUE_DATA_s; + end + else begin + next_state = ENQUEUE_META_s; + end + ENQUEUE_DATA_s: if(enqueue_req_valid && enqueue_req_ready && ingress_last) begin + if(!bypass_mode) begin + next_state = RESOURCE_REQ_s; + end + else begin + next_state = IDLE_s; + end + end + else begin + next_state = ENQUEUE_DATA_s; + end + RESOURCE_REQ_s: if(resource_req_valid && resource_req_ready) begin + next_state = IDLE_s; + end + else begin + next_state = RESOURCE_REQ_s; + end + BYPASS_s: if(ingress_valid && ingress_last && egress_valid && egress_ready) begin + next_state = IDLE_s; + end + else begin + next_state = BYPASS_s; + end + default: next_state = IDLE_s; + endcase +end +/*------------------------------------------- State Machine Definition : End ----------------------------------------*/ + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ +//-- queue_empty -- +assign queue_empty = empty_resp_head[`EMPTY_INDICATOR_OFFSET]; + +//-- queue_index -- +//-- slot_num -- +//-- bypass_mode -- +//-- resource_req -- +always @(posedge clk or posedge rst) begin + if(rst) begin + queue_index <= 'd0; + slot_num <= 'd0; + bypass_mode <= 'd0; + resource_req <= 'd0; + end + else if(cur_state == IDLE_s && next_state == JUDGE_s) begin + queue_index <= ingress_head[`QUEUE_INDEX_OFFSET]; + slot_num <= ingress_head[`SLOT_NUM_OFFSET]; + bypass_mode <= ingress_head[`BYPASS_OFFSET]; + resource_req <= ingress_head[`RESOURCE_REQ_OFFSET]; + end + else begin + queue_index <= queue_index; + slot_num <= slot_num; + bypass_mode <= bypass_mode; + resource_req <= resource_req; + end +end + +//-- ingress_ready -- +assign ingress_ready = (cur_state == ENQUEUE_META_s) ? 'd0 : + (cur_state == ENQUEUE_DATA_s) ? enqueue_req_ready : + (cur_state == BYPASS_s) ? egress_ready : 'd0; + +//-- req_tag -- +assign req_tag = {'d0, tag_fifo_dout}; + +//-- resource_req_valid -- +//-- resource_req_head -- +//-- resource_req_data -- +//-- resource_req_start -- +//-- resource_req_last -- +assign resource_req_valid = (cur_state == RESOURCE_REQ_s) ? 'd1 : 'd0; +assign resource_req_head = (cur_state == RESOURCE_REQ_s) ? {resource_req, req_tag} : 'd0; +assign resource_req_data = 'd0; //Currently we do not support resource req with data +assign resource_req_start = (cur_state == RESOURCE_REQ_s) ? 'd1 : 'd0; +assign resource_req_last = (cur_state == RESOURCE_REQ_s) ? 'd1 : 'd0; + +//-- tag_fifo_rd_en -- +assign tag_fifo_rd_en = (cur_state == RESOURCE_REQ_s && resource_req_valid && resource_req_ready) ? 'd1 : 'd0; + +//-- tag_mapping_wea -- +//-- tag_mapping_addra -- +//-- tag_mapping_dina -- +assign tag_mapping_wea = (cur_state == ENQUEUE_META_s) ? 'd1 : 'd0; +assign tag_mapping_addra = (cur_state == ENQUEUE_META_s) ? tag_fifo_dout : 'd0; +assign tag_mapping_dina = (cur_state == ENQUEUE_META_s) ? queue_index : 'd0; + + +//-- empty_req_valid -- +//-- empty_req_head -- +assign empty_req_valid = (cur_state == IDLE_s && ingress_valid && ingress_head[`SLOT_NUM_OFFSET] <= available_slot_num && !tag_fifo_empty) ? 'd1 : 'd0; +assign empty_req_head = (cur_state == IDLE_s && ingress_valid && ingress_head[`SLOT_NUM_OFFSET] <= available_slot_num && !tag_fifo_empty) ? {ingress_head[`QUEUE_INDEX_OFFSET]} : 'd0; + +//-- empty_resp_ready -- +assign empty_resp_ready = (cur_state == JUDGE_s) ? 'd1 : 'd0; + +//-- enqueue_req_valid -- +//-- enqueue_req_head -- +//-- enqueue_req_start -- +//-- enqueue_req_last -- +//-- enqueue_req_data -- +assign enqueue_req_valid = (cur_state == ENQUEUE_META_s) ? 'd1 : + (cur_state == ENQUEUE_DATA_s && ingress_valid) ? 'd1 : 'd0; +assign enqueue_req_head = (cur_state == ENQUEUE_META_s) ? {slot_num + 15'd1, queue_index} : 'd0; +assign enqueue_req_start = (cur_state == ENQUEUE_META_s) ? 'd1 : 'd0; +assign enqueue_req_last = (cur_state == ENQUEUE_DATA_s) ? ingress_last : 'd0; +assign enqueue_req_data = (cur_state == ENQUEUE_META_s) ? {bypass_mode, slot_num + 15'd1, req_tag} : + (cur_state == ENQUEUE_DATA_s) ? ingress_data : 'd0; + +//-- egress_valid -- +//-- egress_head -- +//-- egress_data -- +//-- egress_start -- +//-- egress_last -- +assign egress_valid = (cur_state == BYPASS_s) ? 'd1 : 'd0; +assign egress_head = (cur_state == BYPASS_s) ? {'d0, slot_num, queue_index} : 'd0; +assign egress_data = (cur_state == BYPASS_s) ? ingress_data : 'd0; +assign egress_start = (cur_state == BYPASS_s) ? ingress_start : 'd0; +assign egress_last = (cur_state == BYPASS_s) ? ingress_last : 'd0; +/*------------------------------------------- Variables Decode : End ------------------------------------------------*/ + +// `ifdef ILA_ON +// generate +// if(ID == 1) begin +// ila_ooo ila_ooo_inst( +// .clk(clk), + +// .probe0(ingress_valid), +// .probe1(ingress_head), +// .probe2(ingress_data), +// .probe3(ingress_start), +// .probe4(ingress_last), +// .probe5(ingress_ready), + +// .probe6(resource_req_valid), +// .probe7(resource_req_head), +// .probe8(resource_req_data), +// .probe9(resource_req_start), +// .probe10(resource_req_last), +// .probe11(resource_req_ready), + +// .probe12(available_slot_num), + +// .probe13(tag_fifo_empty), +// .probe14(tag_fifo_dout), +// .probe15(tag_fifo_rd_en), + +// .probe16(empty_req_valid), +// .probe17(empty_req_head), +// .probe18(empty_req_ready), + +// .probe19(empty_resp_valid), +// .probe20(empty_resp_head), +// .probe21(empty_resp_ready) +// ); +// end +// endgenerate +// `endif + + +/*------------------------------------------- Local Macros Undef : Begin --------------------------------------------*/ +`undef QUEUE_INDEX_OFFSET +`undef SLOT_NUM_OFFSET +`undef BYPASS_OFFSET +`undef RESOURCE_REQ_OFFSET +/*------------------------------------------- Local Macros Undef : End ----------------------------------------------*/ +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Peripherals/OoOStation/OoOStation_Thread_2.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Peripherals/OoOStation/OoOStation_Thread_2.v new file mode 100644 index 0000000000000000000000000000000000000000..0bc007549ec681a315710be7e6b9a2ffc4831791 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Peripherals/OoOStation/OoOStation_Thread_2.v @@ -0,0 +1,485 @@ +/*------------------------------------------- Module Description : Begin ---------------------------------------------- +Name: OoOStation_Thread_2 +Author: YangFan +Function: Handle out-of-order response. +--------------------------------------------- Module Decription : End -----------------------------------------------*/ + +/*------------------------------------------- Timescale Definition : Begin ------------------------------------------*/ +`timescale 1ns / 1ps +/*------------------------------------------- Timescale Definition : End --------------------------------------------*/ + +/*------------------------------------------- Included Files : Begin ------------------------------------------------*/ +`include "common_function_def.vh" +/*------------------------------------------- Included Files : End --------------------------------------------------*/ + +/*------------------------------------------- Local Macros Definition : Begin ---------------------------------------*/ +/*------------------------------------------- Local Macros Definition : End -----------------------------------------*/ + +/*------------------------------------------- Input/Output Definition : Begin ---------------------------------------*/ +module OoOStation_Thread_2 #( + parameter ID = 1, + + //TAG_NUM is not equal to SLOT_NUM, since each resource req consumes 1 tag, and it may require more than 1 slot. + parameter TAG_NUM = 64 + 1, //+1 since tag 0 is left unused(for special purpose in Resource Manager) + parameter TAG_NUM_LOG = log2b(TAG_NUM - 1), + + + //RESOURCE_CMD/RESP_WIDTH is resource-specific + //For example, MR resource cmd format is {PD, LKey, Lengtg, Addr}, MR resource reply format is {PTE-1, PTE-0, indicator} + parameter RESOURCE_CMD_HEAD_WIDTH = 128, + parameter RESOURCE_CMD_DATA_WIDTH = 256, + parameter RESOURCE_RESP_HEAD_WIDTH = 128, + parameter RESOURCE_RESP_DATA_WIDTH = 128, + + parameter SLOT_NUM = 512, + parameter QUEUE_NUM = 32, + parameter SLOT_NUM_LOG = log2b(SLOT_NUM - 1), + parameter QUEUE_NUM_LOG = log2b(QUEUE_NUM - 1), + + //When issuing cmd to Resource Manager, add tag index + parameter OOO_CMD_HEAD_WIDTH = TAG_NUM_LOG + RESOURCE_CMD_HEAD_WIDTH, + parameter OOO_CMD_DATA_WIDTH = RESOURCE_CMD_DATA_WIDTH, + parameter OOO_RESP_HEAD_WIDTH = TAG_NUM_LOG + RESOURCE_RESP_HEAD_WIDTH, + parameter OOO_RESP_DATA_WIDTH = RESOURCE_RESP_DATA_WIDTH, + + parameter INGRESS_HEAD_WIDTH = RESOURCE_CMD_HEAD_WIDTH + SLOT_NUM_LOG + QUEUE_NUM_LOG + 1, + //INGRESS_DATA_WIDTH is ingress-thread-specific + parameter INGRESS_DATA_WIDTH = 512, + + parameter SLOT_WIDTH = INGRESS_DATA_WIDTH, + + + //Egress thread + parameter EGRESS_HEAD_WIDTH = RESOURCE_RESP_HEAD_WIDTH + SLOT_NUM_LOG + QUEUE_NUM_LOG, + parameter EGRESS_DATA_WIDTH = INGRESS_DATA_WIDTH +) +( + input wire clk, + input wire rst, + +//Interface with Resource Manager + input wire resource_resp_valid, + input wire [OOO_RESP_HEAD_WIDTH - 1 : 0] resource_resp_head, + input wire [OOO_RESP_DATA_WIDTH - 1 : 0] resource_resp_data, + input wire resource_resp_start, + input wire resource_resp_last, + output wire resource_resp_ready, + +//Interface with Reservation Station + output wire get_req_valid, + output wire [`MAX_QP_NUM_LOG - 1 : 0] get_req_head, + input wire get_req_ready, + + input wire get_resp_valid, + input wire get_resp_empty, + input wire [SLOT_WIDTH - 1 : 0] get_resp_data, + output wire get_resp_ready, + + output wire dequeue_req_valid, + output wire [`MAX_QP_NUM_LOG + `MAX_OOO_SLOT_NUM_LOG - 1 : 0] dequeue_req_head, + input wire dequeue_req_ready, + + input wire dequeue_resp_valid, + input wire [`MAX_QP_NUM_LOG + `MAX_OOO_SLOT_NUM_LOG - 1 : 0] dequeue_resp_head, + input wire dequeue_resp_start, + input wire dequeue_resp_last, + input wire [SLOT_WIDTH - 1 : 0] dequeue_resp_data, + output wire dequeue_resp_ready, + +//Interface with Reorder Buffer + output wire reorder_buffer_wea, + output wire [TAG_NUM_LOG - 1 : 0] reorder_buffer_addra, + output wire [RESOURCE_RESP_DATA_WIDTH + 1 - 1 : 0] reorder_buffer_dina, //+1 for valid + + output wire [TAG_NUM_LOG - 1 : 0] reorder_buffer_addrb, + input wire [RESOURCE_RESP_DATA_WIDTH + 1 - 1 : 0] reorder_buffer_doutb, + +//Interface with Tag FIFO + output reg tag_fifo_wr_en, + output reg [TAG_NUM_LOG - 1 : 0] tag_fifo_din, + input wire tag_fifo_prog_full, + +//Interface with Tag-QP mapping table + output wire [TAG_NUM_LOG - 1 : 0] tag_mapping_addrb, + input wire [QUEUE_NUM_LOG - 1 : 0] tag_mapping_doutb, + + output wire egress_valid, + output wire [EGRESS_HEAD_WIDTH - 1 : 0] egress_head, + output wire [EGRESS_DATA_WIDTH - 1 : 0] egress_data, + output wire egress_start, + output wire egress_last, + input wire egress_ready +); +/*------------------------------------------- Input/Output Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Macros Definition : Begin ---------------------------------------*/ +`define TAG_OFFSET `MAX_REQ_TAG_NUM_LOG - 1:0 +`define VALID_OFFSET RESOURCE_RESP_DATA_WIDTH +`define SLOT_NUM_OFFSET `MAX_OOO_SLOT_NUM_LOG + `MAX_REQ_TAG_NUM_LOG:`MAX_REQ_TAG_NUM_LOG +/*------------------------------------------- Local Macros Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Variables Definition : Begin ------------------------------------*/ +reg [`MAX_REQ_TAG_NUM_LOG : 0] tag_init_counter; +reg [`MAX_QP_NUM_LOG - 1 : 0] queue_index; +reg [`MAX_REQ_TAG_NUM_LOG - 1 : 0] queue_head_tag; +wire resource_available; +reg [`MAX_OOO_SLOT_NUM_LOG - 1 : 0] slot_num; + +reg [`MAX_REQ_TAG_NUM_LOG - 1 : 0] tag_mapping_addrb_diff; + +reg [RESOURCE_RESP_DATA_WIDTH - 1 : 0] resource_data; +reg start_flag; + +wire [`EGRESS_COMMON_HEAD_WIDTH - 1 : 0] egress_common_head; + +reg bypass_mode; +/*------------------------------------------- Local Variables Definition : End --------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : Begin ---------------------------------------*/ +wire st_resource_resp_valid; +wire [OOO_RESP_HEAD_WIDTH - 1 : 0] st_resource_resp_head; +wire [OOO_RESP_DATA_WIDTH - 1 : 0] st_resource_resp_data; +wire st_resource_resp_start; +wire st_resource_resp_last; +wire st_resource_resp_ready; + +stream_reg #( + .TUSER_WIDTH ( OOO_RESP_HEAD_WIDTH ), + .TDATA_WIDTH ( OOO_RESP_DATA_WIDTH ), + + .MODE ( 0 ), + .NUM_LEVELS ( 4 ) +) st_resource_resp( + .clk ( clk ), + .rst_n ( ~rst ), + + + .axis_tvalid ( resource_resp_valid ), + .axis_tlast ( resource_resp_last ), + .axis_tuser ( resource_resp_head ), + .axis_tdata ( resource_resp_data ), + .axis_tready ( resource_resp_ready ), + .axis_tstart ( resource_resp_valid ), + .axis_tkeep ( 'd0 ), + + .in_reg_tvalid ( st_resource_resp_valid ), + .in_reg_tlast ( st_resource_resp_last ), + .in_reg_tuser ( st_resource_resp_head ), + .in_reg_tdata ( st_resource_resp_data ), + .in_reg_tkeep ( ), + .in_reg_tstart ( ), + .in_reg_tready ( st_resource_resp_ready ) +); +/*------------------------------------------- Submodules Instatiation : End -----------------------------------------*/ + +/*------------------------------------------- State Machine Definition : Begin --------------------------------------*/ +reg [3:0] cur_state; +reg [3:0] next_state; + +parameter INIT_s = 4'd1, + IDLE_s = 4'd2, + GET_CMD_s = 4'd3, + GET_RESP_s = 4'd4, + JUDGE_s = 4'd5, + DEQUEUE_REQ_s = 4'd6, + DEQUEUE_META_s = 4'd7, + DEQUEUE_DATA_s = 4'd8; + +always @(posedge clk or posedge rst) begin + if(rst) begin + cur_state <= INIT_s; + end + else begin + cur_state <= next_state; + end +end + +always @(*) begin + case(cur_state) + INIT_s: if(tag_init_counter + 1 == TAG_NUM) begin + next_state = IDLE_s; + end + else begin + next_state = INIT_s; + end + IDLE_s: if(st_resource_resp_valid) begin + next_state = GET_CMD_s; + end + else begin + next_state = IDLE_s; + end + GET_CMD_s: if(get_req_valid && get_req_ready) begin + next_state = GET_RESP_s; + end + else begin + next_state = GET_CMD_s; + end + GET_RESP_s: if(get_resp_valid && get_resp_ready) begin + if(!get_resp_empty) begin + next_state = JUDGE_s; + end + else begin + next_state = IDLE_s; + end + end + else begin + next_state = GET_RESP_s; + end + JUDGE_s: if(bypass_mode) begin + next_state = DEQUEUE_REQ_s; + end + else if(resource_available) begin + next_state = DEQUEUE_REQ_s; + end + else begin + next_state = IDLE_s; + end + DEQUEUE_REQ_s: if(dequeue_req_valid && dequeue_req_ready) begin + next_state = DEQUEUE_META_s; + end + else begin + next_state = DEQUEUE_REQ_s; + end + DEQUEUE_META_s: if(dequeue_resp_valid && dequeue_resp_ready) begin + next_state = DEQUEUE_DATA_s; + end + else begin + next_state = DEQUEUE_META_s; + end + DEQUEUE_DATA_s: if(dequeue_resp_valid && dequeue_resp_last && dequeue_resp_ready) begin + next_state = GET_CMD_s; + end + else begin + next_state = DEQUEUE_DATA_s; + end + default: next_state = IDLE_s; + endcase +end +/*------------------------------------------- State Machine Definition : End ----------------------------------------*/ + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ +reg [31:0] get_cnt; //Used to deal with a corner case, since tag_mapping_dout is only valid in first get cmd, after dequeuing, tag is freed, tag_mapping may be changed by thread_1 +//-- dequeue_cnt -- +always @(posedge clk or posedge rst) begin + if (rst) begin + get_cnt <= 'd0; + end + else if (cur_state == IDLE_s && st_resource_resp_valid) begin + get_cnt <= 'd0; + end + else if(cur_state == GET_CMD_s && get_req_valid && get_req_ready) begin + get_cnt <= get_cnt + 'd1; + end + else begin + get_cnt <= get_cnt; + end +end + +//-- tag_init_counter -- +always @(posedge clk or posedge rst) begin + if(rst) begin + tag_init_counter <= 'd1; + end + else if(cur_state == INIT_s && tag_init_counter < TAG_NUM) begin + tag_init_counter <= tag_init_counter + 'd1; + end + else begin + tag_init_counter <= tag_init_counter; + end +end + +//-- queue_index -- +always @(posedge clk or posedge rst) begin + if(rst) begin + queue_index <= 'd0; + end + else if(cur_state == GET_CMD_s && get_cnt == 'd0) begin + queue_index <= {'d0, tag_mapping_doutb}; + end + else begin + queue_index <= queue_index; + end +end + +//-- slot_num -- +always @(posedge clk or posedge rst) begin + if (rst) begin + slot_num <= 'd0; + end + else if (cur_state == GET_RESP_s && get_resp_valid) begin + slot_num <= get_resp_data[`SLOT_NUM_OFFSET]; + end + else begin + slot_num <= slot_num; + end +end + +//-- queue_head_tag -- +always @(posedge clk or posedge rst) begin + if (rst) begin + queue_head_tag <= 'd0; + end + else if (cur_state == GET_RESP_s && get_resp_valid) begin + queue_head_tag <= get_resp_data[`TAG_OFFSET]; + end + else begin + queue_head_tag <= queue_head_tag; + end +end + +//-- resource_data -- +always @(posedge clk or posedge rst) begin + if(rst) begin + resource_data <= 'd0; + end + else if(cur_state == JUDGE_s) begin + resource_data <= reorder_buffer_doutb[RESOURCE_RESP_DATA_WIDTH - 1 : 0]; + end + else begin + resource_data <= resource_data; + end +end + +//-- start_flag -- +always @(posedge clk or posedge rst) begin + if (rst) begin + start_flag <= 'd0; + end + else if (cur_state == DEQUEUE_META_s && next_state == DEQUEUE_DATA_s) begin + start_flag <= 'd1; + end + else if(cur_state == DEQUEUE_DATA_s && egress_valid && egress_ready) begin + start_flag <= 'd0; + end + else begin + start_flag <= start_flag; + end +end + +//-- resource_available -- +assign resource_available = (cur_state == JUDGE_s) ? reorder_buffer_doutb[`VALID_OFFSET] : 'd0; + +//-- st_resource_resp_ready -- +assign st_resource_resp_ready = (cur_state == IDLE_s) ? 'd1 : 'd0; + +wire [`MAX_QP_NUM_LOG - 1 : 0] get_cmd_queue_index; +assign get_cmd_queue_index = (cur_state == GET_CMD_s && get_cnt == 'd0) ? tag_mapping_doutb : queue_index; + +//--get_req_valid -- +//--get_req_head -- +assign get_req_valid = (cur_state == GET_CMD_s) ? 'd1 : 'd0; +assign get_req_head = (cur_state == GET_CMD_s) ? {'d1, get_cmd_queue_index} : 'd0; + +//-- get_resp_ready -- +assign get_resp_ready = (cur_state == GET_RESP_s) ? 'd1 : 'd0; + +//-- dequeue_req_valid -- +//-- dequeue_req_head -- +assign dequeue_req_valid = (cur_state == DEQUEUE_REQ_s) ? 'd1 : 'd0; +assign dequeue_req_head = (cur_state == DEQUEUE_REQ_s) ? {slot_num, queue_index} : 'd0; + +//--dequeue_resp_ready -- +assign dequeue_resp_ready = (cur_state == DEQUEUE_META_s) ? 'd1 : + (cur_state == DEQUEUE_DATA_s) ? egress_ready : 'd0; + +//-- reorder_buffer_wea -- +//-- reorder_buffer_addra -- +//-- reorder_buffer_dina -- +assign reorder_buffer_wea = (cur_state == INIT_s) ? 'd1 : + (cur_state == IDLE_s && st_resource_resp_valid) ? 'd1 : + (cur_state == DEQUEUE_REQ_s && dequeue_req_valid && !bypass_mode) ? 'd1 : 'd0; +assign reorder_buffer_addra = (cur_state == INIT_s) ? tag_init_counter : + (cur_state == IDLE_s && st_resource_resp_valid) ? st_resource_resp_head[`TAG_OFFSET] : + (cur_state == DEQUEUE_REQ_s && dequeue_req_valid) ? queue_head_tag : 'd0; +assign reorder_buffer_dina = (cur_state == INIT_s) ? 'd0 : + (cur_state == IDLE_s && st_resource_resp_valid) ? {1'b1, st_resource_resp_data} : + (cur_state == DEQUEUE_REQ_s && dequeue_req_valid) ? 'd0 : 'd0; + +//-- reorder_buffer_addrb -- +assign reorder_buffer_addrb = (cur_state == GET_RESP_s && get_resp_valid) ? get_resp_data[`TAG_OFFSET] : 'd0; + +reg [TAG_NUM_LOG - 1 : 0] free_tag; +always @(posedge clk or posedge rst) begin + if (rst) begin + free_tag <= 'd0; + end + else if (cur_state == GET_RESP_s && get_resp_valid) begin + free_tag <= get_resp_data[`TAG_OFFSET]; + end + else begin + free_tag <= free_tag; + end + end + +//-- tag_fifo_wr_en -- +//-- tag_fifo_din -- +always @(posedge clk or posedge rst) begin + if (rst) begin + tag_fifo_wr_en <= 'd0; + tag_fifo_din <= 'd0; + end + else if (cur_state == INIT_s) begin + tag_fifo_wr_en <= 'd1; + tag_fifo_din <= tag_init_counter; + end + else if(cur_state == DEQUEUE_REQ_s && dequeue_req_valid && dequeue_req_ready && !bypass_mode) begin + tag_fifo_wr_en <= 'd1; + tag_fifo_din <= free_tag; + end + else begin + tag_fifo_wr_en <= 'd0; + tag_fifo_din <= 'd0; + end +end + +//-- tag_mapping_addrb -- +assign tag_mapping_addrb = (cur_state == IDLE_s && st_resource_resp_valid) ? st_resource_resp_head[`TAG_OFFSET] : tag_mapping_addrb_diff; + +//-- tag_mapping_addrb_diff -- +always @(posedge clk or posedge rst) begin + if(rst) begin + tag_mapping_addrb_diff <= 'd0; + end + else if(cur_state == IDLE_s && st_resource_resp_valid) begin + tag_mapping_addrb_diff <= tag_mapping_addrb; + end + else begin + tag_mapping_addrb_diff <= tag_mapping_addrb_diff; + end +end + +//-- egress_common_head -- +assign egress_common_head = {'d0, queue_index}; + +//-- egress_valid -- +//-- egress_head -- +//-- egress_data -- +//-- egress_start -- +//-- egress_last -- +assign egress_valid = (cur_state == DEQUEUE_DATA_s && dequeue_resp_valid) ? 'd1 : 'd0; +assign egress_head = (cur_state == DEQUEUE_DATA_s && start_flag) ? {resource_data, egress_common_head} : 'd0; +assign egress_data = (cur_state == DEQUEUE_DATA_s && dequeue_resp_valid) ? dequeue_resp_data : 'd0; +assign egress_start = (cur_state == DEQUEUE_DATA_s && dequeue_resp_valid && start_flag) ? 'd1 : 'd0; +assign egress_last = (cur_state == DEQUEUE_DATA_s && dequeue_resp_valid && dequeue_resp_last) ? 'd1 : 'd0; + +//-- bypass_mode -- +always @(posedge clk or posedge rst) begin + if (rst) begin + bypass_mode <= 'd0; + end + else if (cur_state == GET_RESP_s && get_resp_valid) begin + bypass_mode <= get_resp_data[`MAX_OOO_SLOT_NUM_LOG + `MAX_REQ_TAG_NUM_LOG]; + end + else begin + bypass_mode <= bypass_mode; + end +end +/*------------------------------------------- Variables Decode : End ------------------------------------------------*/ + + +/*------------------------------------------- Local Macros Undef : Begin --------------------------------------------*/ +`undef TAG_OFFSET +`undef VALID_OFFSET +`undef SLOT_NUM_OFFSET +/*------------------------------------------- Local Macros Undef : End ----------------------------------------------*/ +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Peripherals/OoOStation/OoOStation_Thread_3.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Peripherals/OoOStation/OoOStation_Thread_3.v new file mode 100644 index 0000000000000000000000000000000000000000..16e21d7b20e03344fd05621203381555475bb9a0 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Peripherals/OoOStation/OoOStation_Thread_3.v @@ -0,0 +1,166 @@ +/*------------------------------------------- Module Description : Begin ---------------------------------------------- +Name: OoOStation_Thread_3 +Author: YangFan +Function: Arbitrate different egress response. Bypass mode has highest priority. +--------------------------------------------- Module Decription : End -----------------------------------------------*/ + +/*------------------------------------------- Timescale Definition : Begin ------------------------------------------*/ +`timescale 1ns / 1ps +/*------------------------------------------- Timescale Definition : End --------------------------------------------*/ + +/*------------------------------------------- Included Files : Begin ------------------------------------------------*/ +`include "common_function_def.vh" +/*------------------------------------------- Included Files : End --------------------------------------------------*/ + +/*------------------------------------------- Local Macros Definition : Begin ---------------------------------------*/ +/*------------------------------------------- Local Macros Definition : End -----------------------------------------*/ + +/*------------------------------------------- Input/Output Definition : Begin ---------------------------------------*/ +module OoOStation_Thread_3 #( + parameter ID = 1, + + //TAG_NUM is not equal to SLOT_NUM, since each resource req consumes 1 tag, and it may require more than 1 slot. + parameter TAG_NUM = 64 + 1, //+1 since tag 0 is left unused(for special purpose in Resource Manager) + parameter TAG_NUM_LOG = log2b(TAG_NUM - 1), + + + //RESOURCE_CMD/RESP_WIDTH is resource-specific + //For example, MR resource cmd format is {PD, LKey, Lengtg, Addr}, MR resource reply format is {PTE-1, PTE-0, indicator} + parameter RESOURCE_CMD_HEAD_WIDTH = 128, + parameter RESOURCE_CMD_DATA_WIDTH = 256, + parameter RESOURCE_RESP_HEAD_WIDTH = 128, + parameter RESOURCE_RESP_DATA_WIDTH = 128, + + parameter SLOT_NUM = 512, + parameter QUEUE_NUM = 32, + parameter SLOT_NUM_LOG = log2b(SLOT_NUM - 1), + parameter QUEUE_NUM_LOG = log2b(QUEUE_NUM - 1), + + //When issuing cmd to Resource Manager, add tag index + parameter OOO_CMD_HEAD_WIDTH = TAG_NUM_LOG + RESOURCE_CMD_HEAD_WIDTH, + parameter OOO_CMD_DATA_WIDTH = RESOURCE_CMD_DATA_WIDTH, + parameter OOO_RESP_HEAD_WIDTH = TAG_NUM_LOG + RESOURCE_RESP_HEAD_WIDTH, + parameter OOO_RESP_DATA_WIDTH = RESOURCE_RESP_DATA_WIDTH, + + parameter INGRESS_HEAD_WIDTH = RESOURCE_CMD_HEAD_WIDTH + SLOT_NUM_LOG + QUEUE_NUM_LOG + 1, + //INGRESS_DATA_WIDTH is ingress-thread-specific + parameter INGRESS_DATA_WIDTH = 512, + + parameter SLOT_WIDTH = INGRESS_DATA_WIDTH, + + + //Egress thread + parameter EGRESS_HEAD_WIDTH = RESOURCE_RESP_HEAD_WIDTH + SLOT_NUM_LOG + QUEUE_NUM_LOG, + parameter EGRESS_DATA_WIDTH = INGRESS_DATA_WIDTH +) +( + input wire clk, + input wire rst, + + input wire bypass_egress_valid, + input wire [EGRESS_HEAD_WIDTH - 1 : 0] bypass_egress_head, + input wire [EGRESS_DATA_WIDTH - 1 : 0] bypass_egress_data, + input wire bypass_egress_start, + input wire bypass_egress_last, + output wire bypass_egress_ready, + + input wire normal_egress_valid, + input wire [EGRESS_HEAD_WIDTH - 1 : 0] normal_egress_head, + input wire [EGRESS_DATA_WIDTH - 1 : 0] normal_egress_data, + input wire normal_egress_start, + input wire normal_egress_last, + output wire normal_egress_ready, + + output wire egress_valid, + output wire [EGRESS_HEAD_WIDTH - 1 : 0] egress_head, + output wire [EGRESS_DATA_WIDTH - 1 : 0] egress_data, + output wire egress_start, + output wire egress_last, + input wire egress_ready +); +/*------------------------------------------- Input/Output Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Macros Definition : Begin ---------------------------------------*/ +/*------------------------------------------- Local Macros Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Variables Definition : Begin ------------------------------------*/ +/*------------------------------------------- Local Variables Definition : End --------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : Begin ---------------------------------------*/ +/*------------------------------------------- Submodules Instatiation : End -----------------------------------------*/ + +/*------------------------------------------- State Machine Definition : Begin --------------------------------------*/ +reg [1:0] cur_state; +reg [1:0] next_state; + +parameter [1:0] IDLE_s = 2'd1, + BYPASS_s = 2'd2, + NORMAL_s = 2'd3; + +always @(posedge clk or posedge rst) begin + if(rst) begin + cur_state <= IDLE_s; + end + else begin + cur_state <= next_state; + end +end + +always @(*) begin + case(cur_state) + IDLE_s: if(bypass_egress_valid) begin + next_state = BYPASS_s; + end + else if(normal_egress_valid) begin + next_state = NORMAL_s; + end + else begin + next_state = IDLE_s; + end + BYPASS_s: if(egress_valid && egress_ready) begin + next_state = IDLE_s; + end + else begin + next_state = BYPASS_s; + end + NORMAL_s: if(egress_valid && egress_ready) begin + next_state = IDLE_s; + end + else begin + next_state = NORMAL_s; + end + default: next_state = IDLE_s; + endcase +end + +/*------------------------------------------- State Machine Definition : End ----------------------------------------*/ + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ +//-- bypass_egress_ready -- +assign bypass_egress_ready = (cur_state == BYPASS_s) ? egress_ready : 'd0; + +//-- normal_egress_ready -- +assign normal_egress_ready = (cur_state == NORMAL_s) ? egress_ready : 'd0; + +//-- egress_valid -- +//-- egress_head -- +//-- egress_data -- +//-- egress_start -- +//-- egress_last -- +assign egress_valid = (cur_state == BYPASS_s) ? bypass_egress_valid : + (cur_state == NORMAL_s) ? normal_egress_valid : 'd0; +assign egress_head = (cur_state == BYPASS_s) ? bypass_egress_head : + (cur_state == NORMAL_s) ? normal_egress_head : 'd0; +assign egress_data = (cur_state == BYPASS_s) ? bypass_egress_data : + (cur_state == NORMAL_s) ? normal_egress_data : 'd0; +assign egress_start = (cur_state == BYPASS_s) ? bypass_egress_start : + (cur_state == NORMAL_s) ? normal_egress_start : 'd0; +assign egress_last = (cur_state == BYPASS_s) ? bypass_egress_last : + (cur_state == NORMAL_s) ? normal_egress_last : 'd0; +/*------------------------------------------- Variables Decode : End ------------------------------------------------*/ + + +/*------------------------------------------- Local Macros Undef : Begin --------------------------------------------*/ + +/*------------------------------------------- Local Macros Undef : End ----------------------------------------------*/ +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Peripherals/PacketDecap.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Peripherals/PacketDecap.v new file mode 100644 index 0000000000000000000000000000000000000000..42764f4e3deba0f387553ea5d7b9e7e00fffd118 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Peripherals/PacketDecap.v @@ -0,0 +1,655 @@ +/*------------------------------------------- Module Description : Begin ---------------------------------------------- +Name: PacketDecap +Author: YangFan +Function: In NIC/Switch processing pipeline, protocol processing requires frequent appending and removing header. + This module abstracts the remove process. +--------------------------------------------- Module Decription : End -----------------------------------------------*/ + +/*------------------------------------------- Timescale Definition : Begin ------------------------------------------*/ +`timescale 1ns / 1ps +/*------------------------------------------- Timescale Definition : End --------------------------------------------*/ + +/*------------------------------------------- Included Files : Begin ------------------------------------------------*/ +`include "common_function_def.vh" +/*------------------------------------------- Included Files : End --------------------------------------------------*/ + +/*------------------------------------------- Local Macros Definition : Begin ---------------------------------------*/ +/*------------------------------------------- Local Macros Definition : End -----------------------------------------*/ + +/*------------------------------------------- Input/Output Definition : Begin ---------------------------------------*/ +module PacketDecap #( + parameter HEADER_BUS_WIDTH = 512, + parameter PAYLOAD_BUS_WIDTH = 512 +) +( + input wire clk, + input wire rst, + + input wire i_packet_in_valid, + //Head Format + //{2B Payload Length + 1B Header Length} + input wire [HEADER_BUS_WIDTH - 1 : 0] iv_packet_in_head, + input wire [PAYLOAD_BUS_WIDTH - 1 : 0] iv_packet_in_data, + input wire i_packet_in_start, + input wire i_packet_in_last, + output reg o_packet_in_ready, + + output wire o_packet_out_valid, + //Head Format + //{31B Header + 1B Header Length} + output wire [HEADER_BUS_WIDTH - 1 : 0] ov_packet_out_head, + output wire [PAYLOAD_BUS_WIDTH - 1 : 0] ov_packet_out_data, + output wire o_packet_out_start, + output wire o_packet_out_last, + input wire i_packet_out_ready +); +/*------------------------------------------- Input/Output Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Variables Definition : Begin ------------------------------------*/ +reg [31:0] qv_total_len; +reg [31:0] qv_left_len; +reg [31:0] qv_unwritten_len; +reg [511:0] qv_unwritten_data; + + +reg q_packet_out_valid; +reg [511:0] qv_packet_out_data; +reg [511:0] qv_packet_out_data_diff; + +reg [511:0] qv_packet_in_head; +/*------------------------------------------- Local Variables Definition : End --------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : Begin ---------------------------------------*/ +//None +/*------------------------------------------- Submodules Instatiation : End -----------------------------------------*/ + +/*------------------------------------------- State Machine Definition : Begin --------------------------------------*/ +reg [2:0] decap_cur_state; +reg [2:0] decap_next_state; + +parameter [2:0] DECAP_IDLE_s = 3'd1, + DECAP_HEADER_s = 3'd2, + DECAP_TRANS_s = 3'd3; + +always @(posedge clk or posedge rst) begin + if(rst) begin + decap_cur_state <= DECAP_IDLE_s; + end + else begin + decap_cur_state <= decap_next_state; + end +end + +always @(*) begin + case(decap_cur_state) + DECAP_IDLE_s: if(i_packet_in_valid) begin + decap_next_state = DECAP_HEADER_s; + end + else begin + decap_next_state = DECAP_IDLE_s; + end + DECAP_HEADER_s: if(qv_left_len <= 64 && i_packet_out_ready) begin + decap_next_state = DECAP_IDLE_s; + end + else if(qv_left_len > 64) begin + decap_next_state = DECAP_TRANS_s; + end + else begin + decap_next_state = DECAP_HEADER_s; + end + DECAP_TRANS_s: if(qv_unwritten_len + qv_left_len <= 64 && i_packet_out_ready) begin + if(qv_left_len == 0) begin + decap_next_state = DECAP_IDLE_s; + end + else if(qv_left_len > 0 && i_packet_in_valid) begin + decap_next_state = DECAP_IDLE_s; + end + else begin + decap_next_state = DECAP_TRANS_s; + end + end + else begin + decap_next_state = DECAP_TRANS_s; + end + default: decap_next_state = DECAP_IDLE_s; + endcase +end +/*------------------------------------------- State Machine Definition : End ----------------------------------------*/ + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ +//-- o_packet_in_ready -- +always @(*) begin + if(rst) begin + o_packet_in_ready = 'd0; + end + else if(decap_cur_state == DECAP_IDLE_s) begin + o_packet_in_ready = 'd0; + end + else if(decap_cur_state == DECAP_HEADER_s) begin + if(qv_left_len <= 64 && i_packet_out_ready) begin + o_packet_in_ready = 'd1; + end + else if(qv_left_len > 64) begin + o_packet_in_ready = 'd1; + end + else begin + o_packet_in_ready = 'd0; + end + end + else if(decap_cur_state == DECAP_TRANS_s) begin + o_packet_in_ready = i_packet_out_ready; + end + else begin + o_packet_in_ready = 'd0; + end +end + +//-- o_packet_out_valid -- +assign o_packet_out_valid = q_packet_out_valid; + +//-- ov_packet_out_head -- +assign ov_packet_out_head = (decap_cur_state == DECAP_HEADER_s) ? iv_packet_in_head : + (decap_cur_state == DECAP_TRANS_s) && o_packet_out_start ? qv_packet_in_head : 'd0; + +//-- ov_packet_out_data -- +assign ov_packet_out_data = qv_packet_out_data; + +//-- o_packet_out_start -- +assign o_packet_out_start = (decap_cur_state == DECAP_HEADER_s && qv_left_len <= 64) || + (decap_cur_state == DECAP_TRANS_s && o_packet_out_valid && (64 + qv_left_len == qv_total_len)); + +//-- qv_total_len -- +always @(posedge clk or posedge rst) begin + if(rst) begin + qv_total_len <= 'd0; + end + else if(decap_cur_state == DECAP_IDLE_s) begin + if(i_packet_in_valid) begin + qv_total_len <= iv_packet_in_head[23:8] + iv_packet_in_head[7:0]; + end + else begin + qv_total_len <= 'd0; + end + end + else begin + qv_total_len <= qv_total_len; + end +end + +//-- qv_packet_in_head -- +always @(posedge clk or posedge rst) begin + if(rst) begin + qv_packet_in_head <= 'd0; + end + else if(decap_cur_state == DECAP_IDLE_s) begin + qv_packet_in_head <= i_packet_in_valid ? iv_packet_in_head : 'd0; + end + else begin + qv_packet_in_head <= qv_packet_in_head; + end +end + +//-- o_packet_out_last -- +assign o_packet_out_last = (decap_cur_state == DECAP_HEADER_s && qv_left_len <= 64) || + (decap_cur_state == DECAP_TRANS_s && (qv_unwritten_len + qv_left_len <= 64) && + ((qv_left_len == 0) || (qv_left_len > 0 && i_packet_in_valid))); + +//-- q_packet_out_valid -- +always @(*) begin + if(rst) begin + q_packet_out_valid = 'd0; + end + else if(decap_cur_state == DECAP_IDLE_s) begin + q_packet_out_valid = 'd0; + end + else if(decap_cur_state == DECAP_HEADER_s) begin + if(qv_left_len <= 64) begin + q_packet_out_valid = 'd1; + end + else begin + q_packet_out_valid = 'd0; + end + end + else if(decap_cur_state == DECAP_TRANS_s) begin + if(qv_unwritten_len + qv_left_len <= 64) begin + if(qv_left_len == 0) begin + q_packet_out_valid = 'd1; + end + else if(qv_left_len > 0 && i_packet_in_valid) begin + q_packet_out_valid = 'd1; + end + else begin + q_packet_out_valid = 'd0; + end + end + else begin + q_packet_out_valid = i_packet_in_valid; + end + end + else begin + q_packet_out_valid = 'd0; + end +end + +//-- qv_left_len -- +always @(posedge clk or posedge rst) begin + if(rst) begin + qv_left_len <= 'd0; + end + else if(decap_cur_state == DECAP_IDLE_s && i_packet_in_valid) begin + qv_left_len <= iv_packet_in_head[7:0] + iv_packet_in_head[23:8]; + end + else if(decap_cur_state == DECAP_HEADER_s) begin + if(qv_left_len <= 64 && i_packet_out_ready) begin + qv_left_len <= 'd0; + end + else if(qv_left_len > 64) begin + qv_left_len <= qv_left_len - 'd64; + end + else begin + qv_left_len <= qv_left_len; + end + end + else if(decap_cur_state == DECAP_TRANS_s) begin + if(qv_left_len == 0) begin + qv_left_len <= 'd0; + end + else if(qv_left_len > 64 && i_packet_in_valid && i_packet_out_ready) begin + qv_left_len <= qv_left_len - 64; + end + else if(qv_left_len < 64 && i_packet_in_valid && i_packet_out_ready) begin + qv_left_len <= 'd0; + end + else begin + qv_left_len <= qv_left_len; + end + end + else begin + qv_left_len <= qv_left_len; + end +end + +//-- qv_unwritten_len -- +always @(posedge clk or posedge rst) begin + if(rst) begin + qv_unwritten_len <= 'd0; + end + else if(decap_cur_state == DECAP_IDLE_s) begin + qv_unwritten_len <= 'd0; + end + else if(decap_cur_state == DECAP_HEADER_s) begin + qv_unwritten_len <= 'd64 - iv_packet_in_head[7:0]; + end + else if(decap_cur_state == DECAP_TRANS_s) begin + if(qv_unwritten_len + qv_left_len <= 64 && i_packet_out_ready) begin + if(qv_left_len == 0) begin + qv_unwritten_len <= 'd0; + end + else if(qv_left_len > 0 && i_packet_in_valid) begin + qv_unwritten_len <= 'd0; + end + else begin + qv_unwritten_len <= qv_unwritten_len; + end + end + else if(qv_unwritten_len + qv_left_len > 64 && i_packet_in_valid && i_packet_out_ready) begin + if(qv_left_len > 64) begin + qv_unwritten_len <= qv_unwritten_len; + end + else begin + qv_unwritten_len <= qv_left_len - (64 - qv_unwritten_len); + end + end + else begin + qv_unwritten_len <= qv_unwritten_len; + end + end + else begin + qv_unwritten_len <= qv_unwritten_len; + end +end + +//-- qv_unwritten_data -- +always @(posedge clk or posedge rst) begin + if(rst) begin + qv_unwritten_data <= 'd0; + end + else if(decap_cur_state == DECAP_IDLE_s) begin + qv_unwritten_data <= 'd0; + end + else if(decap_cur_state == DECAP_HEADER_s) begin + if(qv_left_len <= 64) begin + qv_unwritten_data <= 'd0; + end + else if(qv_left_len > 64) begin + case(iv_packet_in_head[7:0]) + 0 : qv_unwritten_data <= iv_packet_in_data; + 1 : qv_unwritten_data <= {{((64 - 1 ) * 8){1'b0}}, iv_packet_in_data[511 : (1 * 8)]}; + 2 : qv_unwritten_data <= {{((64 - 2 ) * 8){1'b0}}, iv_packet_in_data[511 : (2 * 8)]}; + 3 : qv_unwritten_data <= {{((64 - 3 ) * 8){1'b0}}, iv_packet_in_data[511 : (3 * 8)]}; + 4 : qv_unwritten_data <= {{((64 - 4 ) * 8){1'b0}}, iv_packet_in_data[511 : (4 * 8)]}; + 5 : qv_unwritten_data <= {{((64 - 5 ) * 8){1'b0}}, iv_packet_in_data[511 : (5 * 8)]}; + 6 : qv_unwritten_data <= {{((64 - 6 ) * 8){1'b0}}, iv_packet_in_data[511 : (6 * 8)]}; + 7 : qv_unwritten_data <= {{((64 - 7 ) * 8){1'b0}}, iv_packet_in_data[511 : (7 * 8)]}; + 8 : qv_unwritten_data <= {{((64 - 8 ) * 8){1'b0}}, iv_packet_in_data[511 : (8 * 8)]}; + 9 : qv_unwritten_data <= {{((64 - 9 ) * 8){1'b0}}, iv_packet_in_data[511 : (9 * 8)]}; + 10 : qv_unwritten_data <= {{((64 - 10) * 8){1'b0}}, iv_packet_in_data[511 : (10 * 8)]}; + 11 : qv_unwritten_data <= {{((64 - 11) * 8){1'b0}}, iv_packet_in_data[511 : (11 * 8)]}; + 12 : qv_unwritten_data <= {{((64 - 12) * 8){1'b0}}, iv_packet_in_data[511 : (12 * 8)]}; + 13 : qv_unwritten_data <= {{((64 - 13) * 8){1'b0}}, iv_packet_in_data[511 : (13 * 8)]}; + 14 : qv_unwritten_data <= {{((64 - 14) * 8){1'b0}}, iv_packet_in_data[511 : (14 * 8)]}; + 15 : qv_unwritten_data <= {{((64 - 15) * 8){1'b0}}, iv_packet_in_data[511 : (15 * 8)]}; + 16 : qv_unwritten_data <= {{((64 - 16) * 8){1'b0}}, iv_packet_in_data[511 : (16 * 8)]}; + 17 : qv_unwritten_data <= {{((64 - 17) * 8){1'b0}}, iv_packet_in_data[511 : (17 * 8)]}; + 18 : qv_unwritten_data <= {{((64 - 18) * 8){1'b0}}, iv_packet_in_data[511 : (18 * 8)]}; + 19 : qv_unwritten_data <= {{((64 - 19) * 8){1'b0}}, iv_packet_in_data[511 : (19 * 8)]}; + 20 : qv_unwritten_data <= {{((64 - 20) * 8){1'b0}}, iv_packet_in_data[511 : (20 * 8)]}; + 21 : qv_unwritten_data <= {{((64 - 21) * 8){1'b0}}, iv_packet_in_data[511 : (21 * 8)]}; + 22 : qv_unwritten_data <= {{((64 - 22) * 8){1'b0}}, iv_packet_in_data[511 : (22 * 8)]}; + 23 : qv_unwritten_data <= {{((64 - 23) * 8){1'b0}}, iv_packet_in_data[511 : (23 * 8)]}; + 24 : qv_unwritten_data <= {{((64 - 24) * 8){1'b0}}, iv_packet_in_data[511 : (24 * 8)]}; + 25 : qv_unwritten_data <= {{((64 - 25) * 8){1'b0}}, iv_packet_in_data[511 : (25 * 8)]}; + 26 : qv_unwritten_data <= {{((64 - 26) * 8){1'b0}}, iv_packet_in_data[511 : (26 * 8)]}; + 27 : qv_unwritten_data <= {{((64 - 27) * 8){1'b0}}, iv_packet_in_data[511 : (27 * 8)]}; + 28 : qv_unwritten_data <= {{((64 - 28) * 8){1'b0}}, iv_packet_in_data[511 : (28 * 8)]}; + 29 : qv_unwritten_data <= {{((64 - 29) * 8){1'b0}}, iv_packet_in_data[511 : (29 * 8)]}; + 30 : qv_unwritten_data <= {{((64 - 30) * 8){1'b0}}, iv_packet_in_data[511 : (30 * 8)]}; + 31 : qv_unwritten_data <= {{((64 - 31) * 8){1'b0}}, iv_packet_in_data[511 : (31 * 8)]}; + 32 : qv_unwritten_data <= {{((64 - 32) * 8){1'b0}}, iv_packet_in_data[511 : (32 * 8)]}; + 33 : qv_unwritten_data <= {{((64 - 33) * 8){1'b0}}, iv_packet_in_data[511 : (33 * 8)]}; + 34 : qv_unwritten_data <= {{((64 - 34) * 8){1'b0}}, iv_packet_in_data[511 : (34 * 8)]}; + 35 : qv_unwritten_data <= {{((64 - 35) * 8){1'b0}}, iv_packet_in_data[511 : (35 * 8)]}; + 36 : qv_unwritten_data <= {{((64 - 36) * 8){1'b0}}, iv_packet_in_data[511 : (36 * 8)]}; + 37 : qv_unwritten_data <= {{((64 - 37) * 8){1'b0}}, iv_packet_in_data[511 : (37 * 8)]}; + 38 : qv_unwritten_data <= {{((64 - 38) * 8){1'b0}}, iv_packet_in_data[511 : (38 * 8)]}; + 39 : qv_unwritten_data <= {{((64 - 39) * 8){1'b0}}, iv_packet_in_data[511 : (39 * 8)]}; + 40 : qv_unwritten_data <= {{((64 - 40) * 8){1'b0}}, iv_packet_in_data[511 : (40 * 8)]}; + 41 : qv_unwritten_data <= {{((64 - 41) * 8){1'b0}}, iv_packet_in_data[511 : (41 * 8)]}; + 42 : qv_unwritten_data <= {{((64 - 42) * 8){1'b0}}, iv_packet_in_data[511 : (42 * 8)]}; + 43 : qv_unwritten_data <= {{((64 - 43) * 8){1'b0}}, iv_packet_in_data[511 : (43 * 8)]}; + 44 : qv_unwritten_data <= {{((64 - 44) * 8){1'b0}}, iv_packet_in_data[511 : (44 * 8)]}; + 45 : qv_unwritten_data <= {{((64 - 45) * 8){1'b0}}, iv_packet_in_data[511 : (45 * 8)]}; + 46 : qv_unwritten_data <= {{((64 - 46) * 8){1'b0}}, iv_packet_in_data[511 : (46 * 8)]}; + 47 : qv_unwritten_data <= {{((64 - 47) * 8){1'b0}}, iv_packet_in_data[511 : (47 * 8)]}; + 48 : qv_unwritten_data <= {{((64 - 48) * 8){1'b0}}, iv_packet_in_data[511 : (48 * 8)]}; + 49 : qv_unwritten_data <= {{((64 - 49) * 8){1'b0}}, iv_packet_in_data[511 : (49 * 8)]}; + 50 : qv_unwritten_data <= {{((64 - 50) * 8){1'b0}}, iv_packet_in_data[511 : (50 * 8)]}; + 51 : qv_unwritten_data <= {{((64 - 51) * 8){1'b0}}, iv_packet_in_data[511 : (51 * 8)]}; + 52 : qv_unwritten_data <= {{((64 - 52) * 8){1'b0}}, iv_packet_in_data[511 : (52 * 8)]}; + 53 : qv_unwritten_data <= {{((64 - 53) * 8){1'b0}}, iv_packet_in_data[511 : (53 * 8)]}; + 54 : qv_unwritten_data <= {{((64 - 54) * 8){1'b0}}, iv_packet_in_data[511 : (54 * 8)]}; + 55 : qv_unwritten_data <= {{((64 - 55) * 8){1'b0}}, iv_packet_in_data[511 : (55 * 8)]}; + 56 : qv_unwritten_data <= {{((64 - 56) * 8){1'b0}}, iv_packet_in_data[511 : (56 * 8)]}; + 57 : qv_unwritten_data <= {{((64 - 57) * 8){1'b0}}, iv_packet_in_data[511 : (57 * 8)]}; + 58 : qv_unwritten_data <= {{((64 - 58) * 8){1'b0}}, iv_packet_in_data[511 : (58 * 8)]}; + 59 : qv_unwritten_data <= {{((64 - 59) * 8){1'b0}}, iv_packet_in_data[511 : (59 * 8)]}; + 60 : qv_unwritten_data <= {{((64 - 60) * 8){1'b0}}, iv_packet_in_data[511 : (60 * 8)]}; + 61 : qv_unwritten_data <= {{((64 - 61) * 8){1'b0}}, iv_packet_in_data[511 : (61 * 8)]}; + 62 : qv_unwritten_data <= {{((64 - 62) * 8){1'b0}}, iv_packet_in_data[511 : (62 * 8)]}; + 63 : qv_unwritten_data <= {{((64 - 63) * 8){1'b0}}, iv_packet_in_data[511 : (63 * 8)]}; + default: qv_unwritten_data <= qv_unwritten_data; + endcase + end + end + else if(decap_cur_state == DECAP_TRANS_s) begin + if(qv_unwritten_len + qv_left_len <= 64 && i_packet_out_ready) begin + if(qv_left_len == 0) begin + qv_unwritten_data <= 'd0; + end + else if(qv_left_len > 0 && i_packet_in_valid) begin + qv_unwritten_data <= 'd0; + end + else begin + qv_unwritten_data <= qv_unwritten_data; + end + end + else if(qv_unwritten_len + qv_left_len > 64 && i_packet_in_valid && i_packet_out_ready) begin + case(qv_unwritten_len) + 0 : qv_unwritten_data <= 'd0; + 1 : qv_unwritten_data <= { {((64 - 1 ) * 8){1'b0}}, iv_packet_in_data[511 : 512 - 1 * 8]}; + 2 : qv_unwritten_data <= { {((64 - 2 ) * 8){1'b0}}, iv_packet_in_data[511 : 512 - 2 * 8]}; + 3 : qv_unwritten_data <= { {((64 - 3 ) * 8){1'b0}}, iv_packet_in_data[511 : 512 - 3 * 8]}; + 4 : qv_unwritten_data <= { {((64 - 4 ) * 8){1'b0}}, iv_packet_in_data[511 : 512 - 4 * 8]}; + 5 : qv_unwritten_data <= { {((64 - 5 ) * 8){1'b0}}, iv_packet_in_data[511 : 512 - 5 * 8]}; + 6 : qv_unwritten_data <= { {((64 - 6 ) * 8){1'b0}}, iv_packet_in_data[511 : 512 - 6 * 8]}; + 7 : qv_unwritten_data <= { {((64 - 7 ) * 8){1'b0}}, iv_packet_in_data[511 : 512 - 7 * 8]}; + 8 : qv_unwritten_data <= { {((64 - 8 ) * 8){1'b0}}, iv_packet_in_data[511 : 512 - 8 * 8]}; + 9 : qv_unwritten_data <= { {((64 - 9 ) * 8){1'b0}}, iv_packet_in_data[511 : 512 - 9 * 8]}; + 10 : qv_unwritten_data <= { {((64 - 10) * 8){1'b0}}, iv_packet_in_data[511 : 512 - 10 * 8]}; + 11 : qv_unwritten_data <= { {((64 - 11) * 8){1'b0}}, iv_packet_in_data[511 : 512 - 11 * 8]}; + 12 : qv_unwritten_data <= { {((64 - 12) * 8){1'b0}}, iv_packet_in_data[511 : 512 - 12 * 8]}; + 13 : qv_unwritten_data <= { {((64 - 13) * 8){1'b0}}, iv_packet_in_data[511 : 512 - 13 * 8]}; + 14 : qv_unwritten_data <= { {((64 - 14) * 8){1'b0}}, iv_packet_in_data[511 : 512 - 14 * 8]}; + 15 : qv_unwritten_data <= { {((64 - 15) * 8){1'b0}}, iv_packet_in_data[511 : 512 - 15 * 8]}; + 16 : qv_unwritten_data <= { {((64 - 16) * 8){1'b0}}, iv_packet_in_data[511 : 512 - 16 * 8]}; + 17 : qv_unwritten_data <= { {((64 - 17) * 8){1'b0}}, iv_packet_in_data[511 : 512 - 17 * 8]}; + 18 : qv_unwritten_data <= { {((64 - 18) * 8){1'b0}}, iv_packet_in_data[511 : 512 - 18 * 8]}; + 19 : qv_unwritten_data <= { {((64 - 19) * 8){1'b0}}, iv_packet_in_data[511 : 512 - 19 * 8]}; + 20 : qv_unwritten_data <= { {((64 - 20) * 8){1'b0}}, iv_packet_in_data[511 : 512 - 20 * 8]}; + 21 : qv_unwritten_data <= { {((64 - 21) * 8){1'b0}}, iv_packet_in_data[511 : 512 - 21 * 8]}; + 22 : qv_unwritten_data <= { {((64 - 22) * 8){1'b0}}, iv_packet_in_data[511 : 512 - 22 * 8]}; + 23 : qv_unwritten_data <= { {((64 - 23) * 8){1'b0}}, iv_packet_in_data[511 : 512 - 23 * 8]}; + 24 : qv_unwritten_data <= { {((64 - 24) * 8){1'b0}}, iv_packet_in_data[511 : 512 - 24 * 8]}; + 25 : qv_unwritten_data <= { {((64 - 25) * 8){1'b0}}, iv_packet_in_data[511 : 512 - 25 * 8]}; + 26 : qv_unwritten_data <= { {((64 - 26) * 8){1'b0}}, iv_packet_in_data[511 : 512 - 26 * 8]}; + 27 : qv_unwritten_data <= { {((64 - 27) * 8){1'b0}}, iv_packet_in_data[511 : 512 - 27 * 8]}; + 28 : qv_unwritten_data <= { {((64 - 28) * 8){1'b0}}, iv_packet_in_data[511 : 512 - 28 * 8]}; + 29 : qv_unwritten_data <= { {((64 - 29) * 8){1'b0}}, iv_packet_in_data[511 : 512 - 29 * 8]}; + 30 : qv_unwritten_data <= { {((64 - 30) * 8){1'b0}}, iv_packet_in_data[511 : 512 - 30 * 8]}; + 31 : qv_unwritten_data <= { {((64 - 31) * 8){1'b0}}, iv_packet_in_data[511 : 512 - 31 * 8]}; + 32 : qv_unwritten_data <= { {((64 - 32) * 8){1'b0}}, iv_packet_in_data[511 : 512 - 32 * 8]}; + 33 : qv_unwritten_data <= { {((64 - 33) * 8){1'b0}}, iv_packet_in_data[511 : 512 - 33 * 8]}; + 34 : qv_unwritten_data <= { {((64 - 34) * 8){1'b0}}, iv_packet_in_data[511 : 512 - 34 * 8]}; + 35 : qv_unwritten_data <= { {((64 - 35) * 8){1'b0}}, iv_packet_in_data[511 : 512 - 35 * 8]}; + 36 : qv_unwritten_data <= { {((64 - 36) * 8){1'b0}}, iv_packet_in_data[511 : 512 - 36 * 8]}; + 37 : qv_unwritten_data <= { {((64 - 37) * 8){1'b0}}, iv_packet_in_data[511 : 512 - 37 * 8]}; + 38 : qv_unwritten_data <= { {((64 - 38) * 8){1'b0}}, iv_packet_in_data[511 : 512 - 38 * 8]}; + 39 : qv_unwritten_data <= { {((64 - 39) * 8){1'b0}}, iv_packet_in_data[511 : 512 - 39 * 8]}; + 40 : qv_unwritten_data <= { {((64 - 40) * 8){1'b0}}, iv_packet_in_data[511 : 512 - 40 * 8]}; + 41 : qv_unwritten_data <= { {((64 - 41) * 8){1'b0}}, iv_packet_in_data[511 : 512 - 41 * 8]}; + 42 : qv_unwritten_data <= { {((64 - 42) * 8){1'b0}}, iv_packet_in_data[511 : 512 - 42 * 8]}; + 43 : qv_unwritten_data <= { {((64 - 43) * 8){1'b0}}, iv_packet_in_data[511 : 512 - 43 * 8]}; + 44 : qv_unwritten_data <= { {((64 - 44) * 8){1'b0}}, iv_packet_in_data[511 : 512 - 44 * 8]}; + 45 : qv_unwritten_data <= { {((64 - 45) * 8){1'b0}}, iv_packet_in_data[511 : 512 - 45 * 8]}; + 46 : qv_unwritten_data <= { {((64 - 46) * 8){1'b0}}, iv_packet_in_data[511 : 512 - 46 * 8]}; + 47 : qv_unwritten_data <= { {((64 - 47) * 8){1'b0}}, iv_packet_in_data[511 : 512 - 47 * 8]}; + 48 : qv_unwritten_data <= { {((64 - 48) * 8){1'b0}}, iv_packet_in_data[511 : 512 - 48 * 8]}; + 49 : qv_unwritten_data <= { {((64 - 49) * 8){1'b0}}, iv_packet_in_data[511 : 512 - 49 * 8]}; + 50 : qv_unwritten_data <= { {((64 - 50) * 8){1'b0}}, iv_packet_in_data[511 : 512 - 50 * 8]}; + 51 : qv_unwritten_data <= { {((64 - 51) * 8){1'b0}}, iv_packet_in_data[511 : 512 - 51 * 8]}; + 52 : qv_unwritten_data <= { {((64 - 52) * 8){1'b0}}, iv_packet_in_data[511 : 512 - 52 * 8]}; + 53 : qv_unwritten_data <= { {((64 - 53) * 8){1'b0}}, iv_packet_in_data[511 : 512 - 53 * 8]}; + 54 : qv_unwritten_data <= { {((64 - 54) * 8){1'b0}}, iv_packet_in_data[511 : 512 - 54 * 8]}; + 55 : qv_unwritten_data <= { {((64 - 55) * 8){1'b0}}, iv_packet_in_data[511 : 512 - 55 * 8]}; + 56 : qv_unwritten_data <= { {((64 - 56) * 8){1'b0}}, iv_packet_in_data[511 : 512 - 56 * 8]}; + 57 : qv_unwritten_data <= { {((64 - 57) * 8){1'b0}}, iv_packet_in_data[511 : 512 - 57 * 8]}; + 58 : qv_unwritten_data <= { {((64 - 58) * 8){1'b0}}, iv_packet_in_data[511 : 512 - 58 * 8]}; + 59 : qv_unwritten_data <= { {((64 - 59) * 8){1'b0}}, iv_packet_in_data[511 : 512 - 59 * 8]}; + 60 : qv_unwritten_data <= { {((64 - 60) * 8){1'b0}}, iv_packet_in_data[511 : 512 - 60 * 8]}; + 61 : qv_unwritten_data <= { {((64 - 61) * 8){1'b0}}, iv_packet_in_data[511 : 512 - 61 * 8]}; + 62 : qv_unwritten_data <= { {((64 - 62) * 8){1'b0}}, iv_packet_in_data[511 : 512 - 62 * 8]}; + 63 : qv_unwritten_data <= { {((64 - 63) * 8){1'b0}}, iv_packet_in_data[511 : 512 - 63 * 8]}; + default: qv_unwritten_data <= qv_unwritten_data; + endcase + end + else begin + qv_unwritten_data <= qv_unwritten_data; + end + end + else begin + qv_unwritten_data <= qv_unwritten_data; + end +end + +//-- qv_packet_out_data -- +always @(*) begin + if(rst) begin + qv_packet_out_data = 'd0; + end + else if(decap_cur_state == DECAP_IDLE_s) begin + qv_packet_out_data = 'd0; + end + else if(decap_cur_state == DECAP_HEADER_s) begin + case(iv_packet_in_head[7:0]) + 0 : qv_packet_out_data = 'd0; + 1 : qv_packet_out_data = { {(1 * 8){1'b0}}, iv_packet_in_data[511 : 1 * 8]}; + 2 : qv_packet_out_data = { {(2 * 8){1'b0}}, iv_packet_in_data[511 : 2 * 8]}; + 3 : qv_packet_out_data = { {(3 * 8){1'b0}}, iv_packet_in_data[511 : 3 * 8]}; + 4 : qv_packet_out_data = { {(4 * 8){1'b0}}, iv_packet_in_data[511 : 4 * 8]}; + 5 : qv_packet_out_data = { {(5 * 8){1'b0}}, iv_packet_in_data[511 : 5 * 8]}; + 6 : qv_packet_out_data = { {(6 * 8){1'b0}}, iv_packet_in_data[511 : 6 * 8]}; + 7 : qv_packet_out_data = { {(7 * 8){1'b0}}, iv_packet_in_data[511 : 7 * 8]}; + 8 : qv_packet_out_data = { {(8 * 8){1'b0}}, iv_packet_in_data[511 : 8 * 8]}; + 9 : qv_packet_out_data = { {(9 * 8){1'b0}}, iv_packet_in_data[511 : 9 * 8]}; + 10 : qv_packet_out_data = { {(10 * 8){1'b0}}, iv_packet_in_data[511 : 10 * 8]}; + 11 : qv_packet_out_data = { {(11 * 8){1'b0}}, iv_packet_in_data[511 : 11 * 8]}; + 12 : qv_packet_out_data = { {(12 * 8){1'b0}}, iv_packet_in_data[511 : 12 * 8]}; + 13 : qv_packet_out_data = { {(13 * 8){1'b0}}, iv_packet_in_data[511 : 13 * 8]}; + 14 : qv_packet_out_data = { {(14 * 8){1'b0}}, iv_packet_in_data[511 : 14 * 8]}; + 15 : qv_packet_out_data = { {(15 * 8){1'b0}}, iv_packet_in_data[511 : 15 * 8]}; + 16 : qv_packet_out_data = { {(16 * 8){1'b0}}, iv_packet_in_data[511 : 16 * 8]}; + 17 : qv_packet_out_data = { {(17 * 8){1'b0}}, iv_packet_in_data[511 : 17 * 8]}; + 18 : qv_packet_out_data = { {(18 * 8){1'b0}}, iv_packet_in_data[511 : 18 * 8]}; + 19 : qv_packet_out_data = { {(19 * 8){1'b0}}, iv_packet_in_data[511 : 19 * 8]}; + 20 : qv_packet_out_data = { {(20 * 8){1'b0}}, iv_packet_in_data[511 : 20 * 8]}; + 21 : qv_packet_out_data = { {(21 * 8){1'b0}}, iv_packet_in_data[511 : 21 * 8]}; + 22 : qv_packet_out_data = { {(22 * 8){1'b0}}, iv_packet_in_data[511 : 22 * 8]}; + 23 : qv_packet_out_data = { {(23 * 8){1'b0}}, iv_packet_in_data[511 : 23 * 8]}; + 24 : qv_packet_out_data = { {(24 * 8){1'b0}}, iv_packet_in_data[511 : 24 * 8]}; + 25 : qv_packet_out_data = { {(25 * 8){1'b0}}, iv_packet_in_data[511 : 25 * 8]}; + 26 : qv_packet_out_data = { {(26 * 8){1'b0}}, iv_packet_in_data[511 : 26 * 8]}; + 27 : qv_packet_out_data = { {(27 * 8){1'b0}}, iv_packet_in_data[511 : 27 * 8]}; + 28 : qv_packet_out_data = { {(28 * 8){1'b0}}, iv_packet_in_data[511 : 28 * 8]}; + 29 : qv_packet_out_data = { {(29 * 8){1'b0}}, iv_packet_in_data[511 : 29 * 8]}; + 30 : qv_packet_out_data = { {(30 * 8){1'b0}}, iv_packet_in_data[511 : 30 * 8]}; + 31 : qv_packet_out_data = { {(31 * 8){1'b0}}, iv_packet_in_data[511 : 31 * 8]}; + 32 : qv_packet_out_data = { {(32 * 8){1'b0}}, iv_packet_in_data[511 : 32 * 8]}; + 33 : qv_packet_out_data = { {(33 * 8){1'b0}}, iv_packet_in_data[511 : 33 * 8]}; + 34 : qv_packet_out_data = { {(34 * 8){1'b0}}, iv_packet_in_data[511 : 34 * 8]}; + 35 : qv_packet_out_data = { {(35 * 8){1'b0}}, iv_packet_in_data[511 : 35 * 8]}; + 36 : qv_packet_out_data = { {(36 * 8){1'b0}}, iv_packet_in_data[511 : 36 * 8]}; + 37 : qv_packet_out_data = { {(37 * 8){1'b0}}, iv_packet_in_data[511 : 37 * 8]}; + 38 : qv_packet_out_data = { {(38 * 8){1'b0}}, iv_packet_in_data[511 : 38 * 8]}; + 39 : qv_packet_out_data = { {(39 * 8){1'b0}}, iv_packet_in_data[511 : 39 * 8]}; + 40 : qv_packet_out_data = { {(40 * 8){1'b0}}, iv_packet_in_data[511 : 40 * 8]}; + 41 : qv_packet_out_data = { {(41 * 8){1'b0}}, iv_packet_in_data[511 : 41 * 8]}; + 42 : qv_packet_out_data = { {(42 * 8){1'b0}}, iv_packet_in_data[511 : 42 * 8]}; + 43 : qv_packet_out_data = { {(43 * 8){1'b0}}, iv_packet_in_data[511 : 43 * 8]}; + 44 : qv_packet_out_data = { {(44 * 8){1'b0}}, iv_packet_in_data[511 : 44 * 8]}; + 45 : qv_packet_out_data = { {(45 * 8){1'b0}}, iv_packet_in_data[511 : 45 * 8]}; + 46 : qv_packet_out_data = { {(46 * 8){1'b0}}, iv_packet_in_data[511 : 46 * 8]}; + 47 : qv_packet_out_data = { {(47 * 8){1'b0}}, iv_packet_in_data[511 : 47 * 8]}; + 48 : qv_packet_out_data = { {(48 * 8){1'b0}}, iv_packet_in_data[511 : 48 * 8]}; + 49 : qv_packet_out_data = { {(49 * 8){1'b0}}, iv_packet_in_data[511 : 49 * 8]}; + 50 : qv_packet_out_data = { {(50 * 8){1'b0}}, iv_packet_in_data[511 : 50 * 8]}; + 51 : qv_packet_out_data = { {(51 * 8){1'b0}}, iv_packet_in_data[511 : 51 * 8]}; + 52 : qv_packet_out_data = { {(52 * 8){1'b0}}, iv_packet_in_data[511 : 52 * 8]}; + 53 : qv_packet_out_data = { {(53 * 8){1'b0}}, iv_packet_in_data[511 : 53 * 8]}; + 54 : qv_packet_out_data = { {(54 * 8){1'b0}}, iv_packet_in_data[511 : 54 * 8]}; + 55 : qv_packet_out_data = { {(55 * 8){1'b0}}, iv_packet_in_data[511 : 55 * 8]}; + 56 : qv_packet_out_data = { {(56 * 8){1'b0}}, iv_packet_in_data[511 : 56 * 8]}; + 57 : qv_packet_out_data = { {(57 * 8){1'b0}}, iv_packet_in_data[511 : 57 * 8]}; + 58 : qv_packet_out_data = { {(58 * 8){1'b0}}, iv_packet_in_data[511 : 58 * 8]}; + 59 : qv_packet_out_data = { {(59 * 8){1'b0}}, iv_packet_in_data[511 : 59 * 8]}; + 60 : qv_packet_out_data = { {(60 * 8){1'b0}}, iv_packet_in_data[511 : 60 * 8]}; + 61 : qv_packet_out_data = { {(61 * 8){1'b0}}, iv_packet_in_data[511 : 61 * 8]}; + 62 : qv_packet_out_data = { {(62 * 8){1'b0}}, iv_packet_in_data[511 : 62 * 8]}; + 63 : qv_packet_out_data = { {(63 * 8){1'b0}}, iv_packet_in_data[511 : 63 * 8]}; + default: qv_packet_out_data = qv_packet_out_data; + endcase + end + else if(decap_cur_state == DECAP_TRANS_s) begin + if(qv_left_len == 0) begin + qv_packet_out_data = qv_unwritten_data; + end + else if(i_packet_in_valid) begin + case(qv_unwritten_len) + 0 : qv_packet_out_data = 'd0; + 1 : qv_packet_out_data = {iv_packet_in_data[(64 - 1 ) * 8 - 1 : 0], qv_unwritten_data[1 * 8 - 1 : 0]}; + 2 : qv_packet_out_data = {iv_packet_in_data[(64 - 2 ) * 8 - 1 : 0], qv_unwritten_data[2 * 8 - 1 : 0]}; + 3 : qv_packet_out_data = {iv_packet_in_data[(64 - 3 ) * 8 - 1 : 0], qv_unwritten_data[3 * 8 - 1 : 0]}; + 4 : qv_packet_out_data = {iv_packet_in_data[(64 - 4 ) * 8 - 1 : 0], qv_unwritten_data[4 * 8 - 1 : 0]}; + 5 : qv_packet_out_data = {iv_packet_in_data[(64 - 5 ) * 8 - 1 : 0], qv_unwritten_data[5 * 8 - 1 : 0]}; + 6 : qv_packet_out_data = {iv_packet_in_data[(64 - 6 ) * 8 - 1 : 0], qv_unwritten_data[6 * 8 - 1 : 0]}; + 7 : qv_packet_out_data = {iv_packet_in_data[(64 - 7 ) * 8 - 1 : 0], qv_unwritten_data[7 * 8 - 1 : 0]}; + 8 : qv_packet_out_data = {iv_packet_in_data[(64 - 8 ) * 8 - 1 : 0], qv_unwritten_data[8 * 8 - 1 : 0]}; + 9 : qv_packet_out_data = {iv_packet_in_data[(64 - 9 ) * 8 - 1 : 0], qv_unwritten_data[9 * 8 - 1 : 0]}; + 10 : qv_packet_out_data = {iv_packet_in_data[(64 - 10) * 8 - 1 : 0], qv_unwritten_data[10 * 8 - 1 : 0]}; + 11 : qv_packet_out_data = {iv_packet_in_data[(64 - 11) * 8 - 1 : 0], qv_unwritten_data[11 * 8 - 1 : 0]}; + 12 : qv_packet_out_data = {iv_packet_in_data[(64 - 12) * 8 - 1 : 0], qv_unwritten_data[12 * 8 - 1 : 0]}; + 13 : qv_packet_out_data = {iv_packet_in_data[(64 - 13) * 8 - 1 : 0], qv_unwritten_data[13 * 8 - 1 : 0]}; + 14 : qv_packet_out_data = {iv_packet_in_data[(64 - 14) * 8 - 1 : 0], qv_unwritten_data[14 * 8 - 1 : 0]}; + 15 : qv_packet_out_data = {iv_packet_in_data[(64 - 15) * 8 - 1 : 0], qv_unwritten_data[15 * 8 - 1 : 0]}; + 16 : qv_packet_out_data = {iv_packet_in_data[(64 - 16) * 8 - 1 : 0], qv_unwritten_data[16 * 8 - 1 : 0]}; + 17 : qv_packet_out_data = {iv_packet_in_data[(64 - 17) * 8 - 1 : 0], qv_unwritten_data[17 * 8 - 1 : 0]}; + 18 : qv_packet_out_data = {iv_packet_in_data[(64 - 18) * 8 - 1 : 0], qv_unwritten_data[18 * 8 - 1 : 0]}; + 19 : qv_packet_out_data = {iv_packet_in_data[(64 - 19) * 8 - 1 : 0], qv_unwritten_data[19 * 8 - 1 : 0]}; + 20 : qv_packet_out_data = {iv_packet_in_data[(64 - 20) * 8 - 1 : 0], qv_unwritten_data[20 * 8 - 1 : 0]}; + 21 : qv_packet_out_data = {iv_packet_in_data[(64 - 21) * 8 - 1 : 0], qv_unwritten_data[21 * 8 - 1 : 0]}; + 22 : qv_packet_out_data = {iv_packet_in_data[(64 - 22) * 8 - 1 : 0], qv_unwritten_data[22 * 8 - 1 : 0]}; + 23 : qv_packet_out_data = {iv_packet_in_data[(64 - 23) * 8 - 1 : 0], qv_unwritten_data[23 * 8 - 1 : 0]}; + 24 : qv_packet_out_data = {iv_packet_in_data[(64 - 24) * 8 - 1 : 0], qv_unwritten_data[24 * 8 - 1 : 0]}; + 25 : qv_packet_out_data = {iv_packet_in_data[(64 - 25) * 8 - 1 : 0], qv_unwritten_data[25 * 8 - 1 : 0]}; + 26 : qv_packet_out_data = {iv_packet_in_data[(64 - 26) * 8 - 1 : 0], qv_unwritten_data[26 * 8 - 1 : 0]}; + 27 : qv_packet_out_data = {iv_packet_in_data[(64 - 27) * 8 - 1 : 0], qv_unwritten_data[27 * 8 - 1 : 0]}; + 28 : qv_packet_out_data = {iv_packet_in_data[(64 - 28) * 8 - 1 : 0], qv_unwritten_data[28 * 8 - 1 : 0]}; + 29 : qv_packet_out_data = {iv_packet_in_data[(64 - 29) * 8 - 1 : 0], qv_unwritten_data[29 * 8 - 1 : 0]}; + 30 : qv_packet_out_data = {iv_packet_in_data[(64 - 30) * 8 - 1 : 0], qv_unwritten_data[30 * 8 - 1 : 0]}; + 31 : qv_packet_out_data = {iv_packet_in_data[(64 - 31) * 8 - 1 : 0], qv_unwritten_data[31 * 8 - 1 : 0]}; + 32 : qv_packet_out_data = {iv_packet_in_data[(64 - 32) * 8 - 1 : 0], qv_unwritten_data[32 * 8 - 1 : 0]}; + 33 : qv_packet_out_data = {iv_packet_in_data[(64 - 33) * 8 - 1 : 0], qv_unwritten_data[33 * 8 - 1 : 0]}; + 34 : qv_packet_out_data = {iv_packet_in_data[(64 - 34) * 8 - 1 : 0], qv_unwritten_data[34 * 8 - 1 : 0]}; + 35 : qv_packet_out_data = {iv_packet_in_data[(64 - 35) * 8 - 1 : 0], qv_unwritten_data[35 * 8 - 1 : 0]}; + 36 : qv_packet_out_data = {iv_packet_in_data[(64 - 36) * 8 - 1 : 0], qv_unwritten_data[36 * 8 - 1 : 0]}; + 37 : qv_packet_out_data = {iv_packet_in_data[(64 - 37) * 8 - 1 : 0], qv_unwritten_data[37 * 8 - 1 : 0]}; + 38 : qv_packet_out_data = {iv_packet_in_data[(64 - 38) * 8 - 1 : 0], qv_unwritten_data[38 * 8 - 1 : 0]}; + 39 : qv_packet_out_data = {iv_packet_in_data[(64 - 39) * 8 - 1 : 0], qv_unwritten_data[39 * 8 - 1 : 0]}; + 40 : qv_packet_out_data = {iv_packet_in_data[(64 - 40) * 8 - 1 : 0], qv_unwritten_data[40 * 8 - 1 : 0]}; + 41 : qv_packet_out_data = {iv_packet_in_data[(64 - 41) * 8 - 1 : 0], qv_unwritten_data[41 * 8 - 1 : 0]}; + 42 : qv_packet_out_data = {iv_packet_in_data[(64 - 42) * 8 - 1 : 0], qv_unwritten_data[42 * 8 - 1 : 0]}; + 43 : qv_packet_out_data = {iv_packet_in_data[(64 - 43) * 8 - 1 : 0], qv_unwritten_data[43 * 8 - 1 : 0]}; + 44 : qv_packet_out_data = {iv_packet_in_data[(64 - 44) * 8 - 1 : 0], qv_unwritten_data[44 * 8 - 1 : 0]}; + 45 : qv_packet_out_data = {iv_packet_in_data[(64 - 45) * 8 - 1 : 0], qv_unwritten_data[45 * 8 - 1 : 0]}; + 46 : qv_packet_out_data = {iv_packet_in_data[(64 - 46) * 8 - 1 : 0], qv_unwritten_data[46 * 8 - 1 : 0]}; + 47 : qv_packet_out_data = {iv_packet_in_data[(64 - 47) * 8 - 1 : 0], qv_unwritten_data[47 * 8 - 1 : 0]}; + 48 : qv_packet_out_data = {iv_packet_in_data[(64 - 48) * 8 - 1 : 0], qv_unwritten_data[48 * 8 - 1 : 0]}; + 49 : qv_packet_out_data = {iv_packet_in_data[(64 - 49) * 8 - 1 : 0], qv_unwritten_data[49 * 8 - 1 : 0]}; + 50 : qv_packet_out_data = {iv_packet_in_data[(64 - 50) * 8 - 1 : 0], qv_unwritten_data[50 * 8 - 1 : 0]}; + 51 : qv_packet_out_data = {iv_packet_in_data[(64 - 51) * 8 - 1 : 0], qv_unwritten_data[51 * 8 - 1 : 0]}; + 52 : qv_packet_out_data = {iv_packet_in_data[(64 - 52) * 8 - 1 : 0], qv_unwritten_data[52 * 8 - 1 : 0]}; + 53 : qv_packet_out_data = {iv_packet_in_data[(64 - 53) * 8 - 1 : 0], qv_unwritten_data[53 * 8 - 1 : 0]}; + 54 : qv_packet_out_data = {iv_packet_in_data[(64 - 54) * 8 - 1 : 0], qv_unwritten_data[54 * 8 - 1 : 0]}; + 55 : qv_packet_out_data = {iv_packet_in_data[(64 - 55) * 8 - 1 : 0], qv_unwritten_data[55 * 8 - 1 : 0]}; + 56 : qv_packet_out_data = {iv_packet_in_data[(64 - 56) * 8 - 1 : 0], qv_unwritten_data[56 * 8 - 1 : 0]}; + 57 : qv_packet_out_data = {iv_packet_in_data[(64 - 57) * 8 - 1 : 0], qv_unwritten_data[57 * 8 - 1 : 0]}; + 58 : qv_packet_out_data = {iv_packet_in_data[(64 - 58) * 8 - 1 : 0], qv_unwritten_data[58 * 8 - 1 : 0]}; + 59 : qv_packet_out_data = {iv_packet_in_data[(64 - 59) * 8 - 1 : 0], qv_unwritten_data[59 * 8 - 1 : 0]}; + 60 : qv_packet_out_data = {iv_packet_in_data[(64 - 60) * 8 - 1 : 0], qv_unwritten_data[60 * 8 - 1 : 0]}; + 61 : qv_packet_out_data = {iv_packet_in_data[(64 - 61) * 8 - 1 : 0], qv_unwritten_data[61 * 8 - 1 : 0]}; + 62 : qv_packet_out_data = {iv_packet_in_data[(64 - 62) * 8 - 1 : 0], qv_unwritten_data[62 * 8 - 1 : 0]}; + 63 : qv_packet_out_data = {iv_packet_in_data[(64 - 63) * 8 - 1 : 0], qv_unwritten_data[63 * 8 - 1 : 0]}; + default: qv_packet_out_data = iv_packet_in_data; + endcase + end + else begin + qv_packet_out_data = qv_packet_out_data_diff; + end + end + else begin + qv_packet_out_data = qv_packet_out_data_diff; + end +end + +//-- qv_packet_out_data_diff -- +always @(posedge clk or posedge rst) begin + if(rst) begin + qv_packet_out_data_diff <= 'd0; + end + else begin + qv_packet_out_data_diff <= qv_packet_out_data; + end +end + +/*------------------------------------------- Variables Decode : End ------------------------------------------------*/ + +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Peripherals/PacketEncap.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Peripherals/PacketEncap.v new file mode 100644 index 0000000000000000000000000000000000000000..584c03f369acaa93e9372e509d8cf5e331ce4f06 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Peripherals/PacketEncap.v @@ -0,0 +1,387 @@ +/*------------------------------------------- Module Description : Begin ---------------------------------------------- +Name: PacketEncap +Author: YangFan +Function: In NIC/Switch processing pipeline, protocol processing requires frequent appending and removing header. + This module abstracts the append process. +--------------------------------------------- Module Decription : End -----------------------------------------------*/ + +/*------------------------------------------- Timescale Definition : Begin ------------------------------------------*/ +`timescale 1ns / 1ps +/*------------------------------------------- Timescale Definition : End --------------------------------------------*/ + +/*------------------------------------------- Included Files : Begin ------------------------------------------------*/ +`include "common_function_def.vh" +/*------------------------------------------- Included Files : End --------------------------------------------------*/ + +/*------------------------------------------- Local Macros Definition : Begin ---------------------------------------*/ +/*------------------------------------------- Local Macros Definition : End -----------------------------------------*/ + +/*------------------------------------------- Input/Output Definition : Begin ---------------------------------------*/ +module PacketEncap #( + parameter HEADER_BUS_WIDTH = 512, + parameter PAYLOAD_BUS_WIDTH = 512, + parameter KEEP_BUS_WIDTH = 64 +) +( + input wire clk, + input wire rst, + + input wire i_packet_in_valid, + //Head Format + //{31B Header + 2B Payload Length + 1B Header Length} + input wire [HEADER_BUS_WIDTH - 1 : 0] iv_packet_in_head, + input wire [PAYLOAD_BUS_WIDTH - 1 : 0] iv_packet_in_data, + input wire [KEEP_BUS_WIDTH - 1 : 0] iv_packet_in_keep, + input wire i_packet_in_start, + input wire i_packet_in_last, + output wire o_packet_in_ready, + + output wire o_packet_out_valid, + output wire [HEADER_BUS_WIDTH - 1 : 0] ov_packet_out_head, + output wire [PAYLOAD_BUS_WIDTH - 1 : 0] ov_packet_out_data, + output wire [KEEP_BUS_WIDTH - 1 : 0] ov_packet_out_keep, + output wire o_packet_out_start, + output wire o_packet_out_last, + input wire i_packet_out_ready +); +/*------------------------------------------- Input/Output Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Variables Definition : Begin ------------------------------------*/ +reg [31:0] qv_unwritten_len; +reg [31:0] qv_total_len; +reg [31:0] qv_left_len; +reg [511:0] qv_unwritten_data; + +reg [HEADER_BUS_WIDTH - 1 : 0] qv_packet_in_head; + +reg [511:0] qv_packet_out_data; +/*------------------------------------------- Local Variables Definition : End --------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : Begin ---------------------------------------*/ +//Null +/*------------------------------------------- Submodules Instatiation : End -----------------------------------------*/ + +/*------------------------------------------- State Machine Definition : Begin --------------------------------------*/ +reg [2:0] encap_cur_state; +reg [2:0] encap_next_state; + +parameter [2:0] ENCAP_IDLE_s = 3'd1, + ENCAP_TRANS_s = 3'd2; + +always @(posedge clk or posedge rst) begin + if(rst) begin + encap_cur_state <= ENCAP_IDLE_s; + end + else begin + encap_cur_state <= encap_next_state; + end +end + +always @(*) begin + case(encap_cur_state) + ENCAP_IDLE_s: if(i_packet_in_valid) begin + encap_next_state = ENCAP_TRANS_s; + end + else begin + encap_next_state = ENCAP_IDLE_s; + end + ENCAP_TRANS_s: if(qv_unwritten_len + qv_left_len <= 64) begin + if(qv_left_len == 0 && i_packet_out_ready) begin + encap_next_state = ENCAP_IDLE_s; + end + else if(qv_left_len > 0 && i_packet_in_valid && i_packet_out_ready) begin + encap_next_state = ENCAP_IDLE_s; + end + else begin + encap_next_state = ENCAP_TRANS_s; + end + end + default: encap_next_state = ENCAP_IDLE_s; + endcase +end +/*------------------------------------------- State Machine Definition : End ----------------------------------------*/ + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ +//-- qv_total_len -- +always @(posedge clk or posedge rst) begin + if(rst) begin + qv_total_len <= 'd0; + end + else if(encap_cur_state == ENCAP_IDLE_s && i_packet_in_valid) begin + qv_total_len <= i_packet_in_valid ? iv_packet_in_head[23:8] + iv_packet_in_head[7:0] : 'd0; + end + else begin + qv_total_len <= qv_total_len; + end +end + +//-- qv_packet_in_head -- +always @(posedge clk or posedge rst) begin + if(rst) begin + qv_packet_in_head <= 'd0; + end + else if(encap_cur_state == ENCAP_IDLE_s) begin + qv_packet_in_head <= i_packet_in_valid ? iv_packet_in_head : 'd0; + end + else begin + qv_packet_in_head <= qv_packet_in_head; + end +end + +//-- qv_left_len -- +always @(posedge clk or posedge rst) begin + if(rst) begin + qv_left_len <= 'd0; + end + else if(encap_cur_state == ENCAP_IDLE_s && i_packet_in_valid) begin + qv_left_len <= iv_packet_in_head[23:8]; + end + else if(encap_cur_state == ENCAP_TRANS_s && i_packet_in_valid && i_packet_out_ready) begin + if(qv_left_len > 64) begin + qv_left_len <= qv_left_len - 'd64; + end + else begin + qv_left_len <= 'd0; + end + end + else begin + qv_left_len <= qv_left_len; + end +end + +//-- qv_unwritten_len -- +always @(posedge clk or posedge rst) begin + if(rst) begin + qv_unwritten_len <= 'd0; + end + else if(encap_cur_state == ENCAP_IDLE_s && i_packet_in_valid) begin + qv_unwritten_len <= iv_packet_in_head[7:0]; + end + else if(encap_cur_state == ENCAP_TRANS_s) begin + if(qv_unwritten_len + qv_left_len <= 64) begin + if(qv_left_len == 0 && i_packet_out_ready) begin + qv_unwritten_len <= 'd0; + end + else if(qv_left_len > 0 && i_packet_in_valid && i_packet_out_ready) begin + qv_unwritten_len <= 'd0; + end + else begin + qv_unwritten_len <= qv_unwritten_len; + end + end + else begin + if(qv_left_len > 64 && i_packet_in_valid && i_packet_out_ready) begin + qv_unwritten_len <= qv_unwritten_len; + end + else if(qv_left_len <= 64 && i_packet_in_valid && i_packet_out_ready) begin + qv_unwritten_len <= (qv_unwritten_len + qv_left_len) - 64; + end + else begin + qv_unwritten_len <= qv_unwritten_len; + end + end + end + else begin + qv_unwritten_len <= qv_unwritten_len; + end +end + +//-- qv_unwritten_data -- +always @(posedge clk or posedge rst) begin + if(rst) begin + qv_unwritten_data <= 'd0; + end + else if(encap_cur_state == ENCAP_IDLE_s && i_packet_in_valid) begin + qv_unwritten_data <= iv_packet_in_head[511:0]; + end + else if(encap_cur_state == ENCAP_TRANS_s) begin + if(qv_unwritten_len + qv_left_len <= 64) begin + if(qv_left_len == 0 && i_packet_out_ready) begin + qv_unwritten_data <= 'd0; + end + else if(qv_left_len > 0 && i_packet_in_valid && i_packet_out_ready) begin + qv_unwritten_data <= 'd0; + end + else begin + qv_unwritten_data <= qv_unwritten_data; + end + end + else if(i_packet_out_ready) begin + case(qv_unwritten_len) + 0 : qv_unwritten_data <= 'd0; + 1 : qv_unwritten_data <= { {((64 - 1 ) * 8){1'b0}}, iv_packet_in_data[511 : 512 - 1 * 8]}; + 2 : qv_unwritten_data <= { {((64 - 2 ) * 8){1'b0}}, iv_packet_in_data[511 : 512 - 2 * 8]}; + 3 : qv_unwritten_data <= { {((64 - 3 ) * 8){1'b0}}, iv_packet_in_data[511 : 512 - 3 * 8]}; + 4 : qv_unwritten_data <= { {((64 - 4 ) * 8){1'b0}}, iv_packet_in_data[511 : 512 - 4 * 8]}; + 5 : qv_unwritten_data <= { {((64 - 5 ) * 8){1'b0}}, iv_packet_in_data[511 : 512 - 5 * 8]}; + 6 : qv_unwritten_data <= { {((64 - 6 ) * 8){1'b0}}, iv_packet_in_data[511 : 512 - 6 * 8]}; + 7 : qv_unwritten_data <= { {((64 - 7 ) * 8){1'b0}}, iv_packet_in_data[511 : 512 - 7 * 8]}; + 8 : qv_unwritten_data <= { {((64 - 8 ) * 8){1'b0}}, iv_packet_in_data[511 : 512 - 8 * 8]}; + 9 : qv_unwritten_data <= { {((64 - 9 ) * 8){1'b0}}, iv_packet_in_data[511 : 512 - 9 * 8]}; + 10 : qv_unwritten_data <= { {((64 - 10) * 8){1'b0}}, iv_packet_in_data[511 : 512 - 10 * 8]}; + 11 : qv_unwritten_data <= { {((64 - 11) * 8){1'b0}}, iv_packet_in_data[511 : 512 - 11 * 8]}; + 12 : qv_unwritten_data <= { {((64 - 12) * 8){1'b0}}, iv_packet_in_data[511 : 512 - 12 * 8]}; + 13 : qv_unwritten_data <= { {((64 - 13) * 8){1'b0}}, iv_packet_in_data[511 : 512 - 13 * 8]}; + 14 : qv_unwritten_data <= { {((64 - 14) * 8){1'b0}}, iv_packet_in_data[511 : 512 - 14 * 8]}; + 15 : qv_unwritten_data <= { {((64 - 15) * 8){1'b0}}, iv_packet_in_data[511 : 512 - 15 * 8]}; + 16 : qv_unwritten_data <= { {((64 - 16) * 8){1'b0}}, iv_packet_in_data[511 : 512 - 16 * 8]}; + 17 : qv_unwritten_data <= { {((64 - 17) * 8){1'b0}}, iv_packet_in_data[511 : 512 - 17 * 8]}; + 18 : qv_unwritten_data <= { {((64 - 18) * 8){1'b0}}, iv_packet_in_data[511 : 512 - 18 * 8]}; + 19 : qv_unwritten_data <= { {((64 - 19) * 8){1'b0}}, iv_packet_in_data[511 : 512 - 19 * 8]}; + 20 : qv_unwritten_data <= { {((64 - 20) * 8){1'b0}}, iv_packet_in_data[511 : 512 - 20 * 8]}; + 21 : qv_unwritten_data <= { {((64 - 21) * 8){1'b0}}, iv_packet_in_data[511 : 512 - 21 * 8]}; + 22 : qv_unwritten_data <= { {((64 - 22) * 8){1'b0}}, iv_packet_in_data[511 : 512 - 22 * 8]}; + 23 : qv_unwritten_data <= { {((64 - 23) * 8){1'b0}}, iv_packet_in_data[511 : 512 - 23 * 8]}; + 24 : qv_unwritten_data <= { {((64 - 24) * 8){1'b0}}, iv_packet_in_data[511 : 512 - 24 * 8]}; + 25 : qv_unwritten_data <= { {((64 - 25) * 8){1'b0}}, iv_packet_in_data[511 : 512 - 25 * 8]}; + 26 : qv_unwritten_data <= { {((64 - 26) * 8){1'b0}}, iv_packet_in_data[511 : 512 - 26 * 8]}; + 27 : qv_unwritten_data <= { {((64 - 27) * 8){1'b0}}, iv_packet_in_data[511 : 512 - 27 * 8]}; + 28 : qv_unwritten_data <= { {((64 - 28) * 8){1'b0}}, iv_packet_in_data[511 : 512 - 28 * 8]}; + 29 : qv_unwritten_data <= { {((64 - 29) * 8){1'b0}}, iv_packet_in_data[511 : 512 - 29 * 8]}; + 30 : qv_unwritten_data <= { {((64 - 30) * 8){1'b0}}, iv_packet_in_data[511 : 512 - 30 * 8]}; + 31 : qv_unwritten_data <= { {((64 - 31) * 8){1'b0}}, iv_packet_in_data[511 : 512 - 31 * 8]}; + 32 : qv_unwritten_data <= { {((64 - 32) * 8){1'b0}}, iv_packet_in_data[511 : 512 - 32 * 8]}; + 33 : qv_unwritten_data <= { {((64 - 33) * 8){1'b0}}, iv_packet_in_data[511 : 512 - 33 * 8]}; + 34 : qv_unwritten_data <= { {((64 - 34) * 8){1'b0}}, iv_packet_in_data[511 : 512 - 34 * 8]}; + 35 : qv_unwritten_data <= { {((64 - 35) * 8){1'b0}}, iv_packet_in_data[511 : 512 - 35 * 8]}; + 36 : qv_unwritten_data <= { {((64 - 36) * 8){1'b0}}, iv_packet_in_data[511 : 512 - 36 * 8]}; + 37 : qv_unwritten_data <= { {((64 - 37) * 8){1'b0}}, iv_packet_in_data[511 : 512 - 37 * 8]}; + 38 : qv_unwritten_data <= { {((64 - 38) * 8){1'b0}}, iv_packet_in_data[511 : 512 - 38 * 8]}; + 39 : qv_unwritten_data <= { {((64 - 39) * 8){1'b0}}, iv_packet_in_data[511 : 512 - 39 * 8]}; + 40 : qv_unwritten_data <= { {((64 - 40) * 8){1'b0}}, iv_packet_in_data[511 : 512 - 40 * 8]}; + 41 : qv_unwritten_data <= { {((64 - 41) * 8){1'b0}}, iv_packet_in_data[511 : 512 - 41 * 8]}; + 42 : qv_unwritten_data <= { {((64 - 42) * 8){1'b0}}, iv_packet_in_data[511 : 512 - 42 * 8]}; + 43 : qv_unwritten_data <= { {((64 - 43) * 8){1'b0}}, iv_packet_in_data[511 : 512 - 43 * 8]}; + 44 : qv_unwritten_data <= { {((64 - 44) * 8){1'b0}}, iv_packet_in_data[511 : 512 - 44 * 8]}; + 45 : qv_unwritten_data <= { {((64 - 45) * 8){1'b0}}, iv_packet_in_data[511 : 512 - 45 * 8]}; + 46 : qv_unwritten_data <= { {((64 - 46) * 8){1'b0}}, iv_packet_in_data[511 : 512 - 46 * 8]}; + 47 : qv_unwritten_data <= { {((64 - 47) * 8){1'b0}}, iv_packet_in_data[511 : 512 - 47 * 8]}; + 48 : qv_unwritten_data <= { {((64 - 48) * 8){1'b0}}, iv_packet_in_data[511 : 512 - 48 * 8]}; + 49 : qv_unwritten_data <= { {((64 - 49) * 8){1'b0}}, iv_packet_in_data[511 : 512 - 49 * 8]}; + 50 : qv_unwritten_data <= { {((64 - 50) * 8){1'b0}}, iv_packet_in_data[511 : 512 - 50 * 8]}; + 51 : qv_unwritten_data <= { {((64 - 51) * 8){1'b0}}, iv_packet_in_data[511 : 512 - 51 * 8]}; + 52 : qv_unwritten_data <= { {((64 - 52) * 8){1'b0}}, iv_packet_in_data[511 : 512 - 52 * 8]}; + 53 : qv_unwritten_data <= { {((64 - 53) * 8){1'b0}}, iv_packet_in_data[511 : 512 - 53 * 8]}; + 54 : qv_unwritten_data <= { {((64 - 54) * 8){1'b0}}, iv_packet_in_data[511 : 512 - 54 * 8]}; + 55 : qv_unwritten_data <= { {((64 - 55) * 8){1'b0}}, iv_packet_in_data[511 : 512 - 55 * 8]}; + 56 : qv_unwritten_data <= { {((64 - 56) * 8){1'b0}}, iv_packet_in_data[511 : 512 - 56 * 8]}; + 57 : qv_unwritten_data <= { {((64 - 57) * 8){1'b0}}, iv_packet_in_data[511 : 512 - 57 * 8]}; + 58 : qv_unwritten_data <= { {((64 - 58) * 8){1'b0}}, iv_packet_in_data[511 : 512 - 58 * 8]}; + 59 : qv_unwritten_data <= { {((64 - 59) * 8){1'b0}}, iv_packet_in_data[511 : 512 - 59 * 8]}; + 60 : qv_unwritten_data <= { {((64 - 60) * 8){1'b0}}, iv_packet_in_data[511 : 512 - 60 * 8]}; + 61 : qv_unwritten_data <= { {((64 - 61) * 8){1'b0}}, iv_packet_in_data[511 : 512 - 61 * 8]}; + 62 : qv_unwritten_data <= { {((64 - 62) * 8){1'b0}}, iv_packet_in_data[511 : 512 - 62 * 8]}; + 63 : qv_unwritten_data <= { {((64 - 63) * 8){1'b0}}, iv_packet_in_data[511 : 512 - 63 * 8]}; + default: qv_unwritten_data <= qv_unwritten_data; + endcase + end + else begin + qv_unwritten_data <= qv_unwritten_data; + end + end + else begin + qv_unwritten_data <= qv_unwritten_data; + end +end + +//-- o_packet_in_ready -- +assign o_packet_in_ready = (encap_cur_state == ENCAP_TRANS_s) && i_packet_out_ready; + +//-- o_packet_out_valid -- +assign o_packet_out_valid = (encap_cur_state == ENCAP_TRANS_s) && ((qv_left_len > 0 && i_packet_in_valid) || (qv_left_len == 'd0)); + +//-- ov_packet_out_head -- +assign ov_packet_out_head = ((encap_cur_state == ENCAP_TRANS_s) && o_packet_out_start) ? iv_packet_in_head : 'd0; + +//-- o_packet_out_start -- +assign o_packet_out_start = (encap_cur_state == ENCAP_TRANS_s) && (qv_unwritten_len + qv_left_len == qv_total_len); + +//-- o_packet_out_last -- +assign o_packet_out_last = (encap_cur_state == ENCAP_TRANS_s) && (qv_unwritten_len + qv_left_len <= 64) && + ((qv_left_len == 0) || (qv_left_len > 0 && i_packet_in_valid)); + +//-- ov_packet_out_data -- +assign ov_packet_out_data = qv_packet_out_data; + +//-- qv_packet_out_data -- +always @(*) begin + if(rst) begin + qv_packet_out_data = 'd0; + end + else if(encap_cur_state == ENCAP_TRANS_s) begin + case(qv_unwritten_len) + 0 : qv_packet_out_data = iv_packet_in_data; + 1 : qv_packet_out_data = {iv_packet_in_data, qv_unwritten_data[1 * 8 - 1 : 0]}; + 2 : qv_packet_out_data = {iv_packet_in_data, qv_unwritten_data[2 * 8 - 1 : 0]}; + 3 : qv_packet_out_data = {iv_packet_in_data, qv_unwritten_data[3 * 8 - 1 : 0]}; + 4 : qv_packet_out_data = {iv_packet_in_data, qv_unwritten_data[4 * 8 - 1 : 0]}; + 5 : qv_packet_out_data = {iv_packet_in_data, qv_unwritten_data[5 * 8 - 1 : 0]}; + 6 : qv_packet_out_data = {iv_packet_in_data, qv_unwritten_data[6 * 8 - 1 : 0]}; + 7 : qv_packet_out_data = {iv_packet_in_data, qv_unwritten_data[7 * 8 - 1 : 0]}; + 8 : qv_packet_out_data = {iv_packet_in_data, qv_unwritten_data[8 * 8 - 1 : 0]}; + 9 : qv_packet_out_data = {iv_packet_in_data, qv_unwritten_data[9 * 8 - 1 : 0]}; + 10 : qv_packet_out_data = {iv_packet_in_data, qv_unwritten_data[10 * 8 - 1 : 0]}; + 11 : qv_packet_out_data = {iv_packet_in_data, qv_unwritten_data[11 * 8 - 1 : 0]}; + 12 : qv_packet_out_data = {iv_packet_in_data, qv_unwritten_data[12 * 8 - 1 : 0]}; + 13 : qv_packet_out_data = {iv_packet_in_data, qv_unwritten_data[13 * 8 - 1 : 0]}; + 14 : qv_packet_out_data = {iv_packet_in_data, qv_unwritten_data[14 * 8 - 1 : 0]}; + 15 : qv_packet_out_data = {iv_packet_in_data, qv_unwritten_data[15 * 8 - 1 : 0]}; + 16 : qv_packet_out_data = {iv_packet_in_data, qv_unwritten_data[16 * 8 - 1 : 0]}; + 17 : qv_packet_out_data = {iv_packet_in_data, qv_unwritten_data[17 * 8 - 1 : 0]}; + 18 : qv_packet_out_data = {iv_packet_in_data, qv_unwritten_data[18 * 8 - 1 : 0]}; + 19 : qv_packet_out_data = {iv_packet_in_data, qv_unwritten_data[19 * 8 - 1 : 0]}; + 20 : qv_packet_out_data = {iv_packet_in_data, qv_unwritten_data[20 * 8 - 1 : 0]}; + 21 : qv_packet_out_data = {iv_packet_in_data, qv_unwritten_data[21 * 8 - 1 : 0]}; + 22 : qv_packet_out_data = {iv_packet_in_data, qv_unwritten_data[22 * 8 - 1 : 0]}; + 23 : qv_packet_out_data = {iv_packet_in_data, qv_unwritten_data[23 * 8 - 1 : 0]}; + 24 : qv_packet_out_data = {iv_packet_in_data, qv_unwritten_data[24 * 8 - 1 : 0]}; + 25 : qv_packet_out_data = {iv_packet_in_data, qv_unwritten_data[25 * 8 - 1 : 0]}; + 26 : qv_packet_out_data = {iv_packet_in_data, qv_unwritten_data[26 * 8 - 1 : 0]}; + 27 : qv_packet_out_data = {iv_packet_in_data, qv_unwritten_data[27 * 8 - 1 : 0]}; + 28 : qv_packet_out_data = {iv_packet_in_data, qv_unwritten_data[28 * 8 - 1 : 0]}; + 29 : qv_packet_out_data = {iv_packet_in_data, qv_unwritten_data[29 * 8 - 1 : 0]}; + 30 : qv_packet_out_data = {iv_packet_in_data, qv_unwritten_data[30 * 8 - 1 : 0]}; + 31 : qv_packet_out_data = {iv_packet_in_data, qv_unwritten_data[31 * 8 - 1 : 0]}; + 32 : qv_packet_out_data = {iv_packet_in_data, qv_unwritten_data[32 * 8 - 1 : 0]}; + 33 : qv_packet_out_data = {iv_packet_in_data, qv_unwritten_data[33 * 8 - 1 : 0]}; + 34 : qv_packet_out_data = {iv_packet_in_data, qv_unwritten_data[34 * 8 - 1 : 0]}; + 35 : qv_packet_out_data = {iv_packet_in_data, qv_unwritten_data[35 * 8 - 1 : 0]}; + 36 : qv_packet_out_data = {iv_packet_in_data, qv_unwritten_data[36 * 8 - 1 : 0]}; + 37 : qv_packet_out_data = {iv_packet_in_data, qv_unwritten_data[37 * 8 - 1 : 0]}; + 38 : qv_packet_out_data = {iv_packet_in_data, qv_unwritten_data[38 * 8 - 1 : 0]}; + 39 : qv_packet_out_data = {iv_packet_in_data, qv_unwritten_data[39 * 8 - 1 : 0]}; + 40 : qv_packet_out_data = {iv_packet_in_data, qv_unwritten_data[40 * 8 - 1 : 0]}; + 41 : qv_packet_out_data = {iv_packet_in_data, qv_unwritten_data[41 * 8 - 1 : 0]}; + 42 : qv_packet_out_data = {iv_packet_in_data, qv_unwritten_data[42 * 8 - 1 : 0]}; + 43 : qv_packet_out_data = {iv_packet_in_data, qv_unwritten_data[43 * 8 - 1 : 0]}; + 44 : qv_packet_out_data = {iv_packet_in_data, qv_unwritten_data[44 * 8 - 1 : 0]}; + 45 : qv_packet_out_data = {iv_packet_in_data, qv_unwritten_data[45 * 8 - 1 : 0]}; + 46 : qv_packet_out_data = {iv_packet_in_data, qv_unwritten_data[46 * 8 - 1 : 0]}; + 47 : qv_packet_out_data = {iv_packet_in_data, qv_unwritten_data[47 * 8 - 1 : 0]}; + 48 : qv_packet_out_data = {iv_packet_in_data, qv_unwritten_data[48 * 8 - 1 : 0]}; + 49 : qv_packet_out_data = {iv_packet_in_data, qv_unwritten_data[49 * 8 - 1 : 0]}; + 50 : qv_packet_out_data = {iv_packet_in_data, qv_unwritten_data[50 * 8 - 1 : 0]}; + 51 : qv_packet_out_data = {iv_packet_in_data, qv_unwritten_data[51 * 8 - 1 : 0]}; + 52 : qv_packet_out_data = {iv_packet_in_data, qv_unwritten_data[52 * 8 - 1 : 0]}; + 53 : qv_packet_out_data = {iv_packet_in_data, qv_unwritten_data[53 * 8 - 1 : 0]}; + 54 : qv_packet_out_data = {iv_packet_in_data, qv_unwritten_data[54 * 8 - 1 : 0]}; + 55 : qv_packet_out_data = {iv_packet_in_data, qv_unwritten_data[55 * 8 - 1 : 0]}; + 56 : qv_packet_out_data = {iv_packet_in_data, qv_unwritten_data[56 * 8 - 1 : 0]}; + 57 : qv_packet_out_data = {iv_packet_in_data, qv_unwritten_data[57 * 8 - 1 : 0]}; + 58 : qv_packet_out_data = {iv_packet_in_data, qv_unwritten_data[58 * 8 - 1 : 0]}; + 59 : qv_packet_out_data = {iv_packet_in_data, qv_unwritten_data[59 * 8 - 1 : 0]}; + 60 : qv_packet_out_data = {iv_packet_in_data, qv_unwritten_data[60 * 8 - 1 : 0]}; + 61 : qv_packet_out_data = {iv_packet_in_data, qv_unwritten_data[61 * 8 - 1 : 0]}; + 62 : qv_packet_out_data = {iv_packet_in_data, qv_unwritten_data[62 * 8 - 1 : 0]}; + 63 : qv_packet_out_data = {iv_packet_in_data, qv_unwritten_data[63 * 8 - 1 : 0]}; + default: qv_packet_out_data = qv_packet_out_data; + endcase + end + else begin + qv_packet_out_data = qv_packet_out_data; + end +end + +/*------------------------------------------- Variables Decode : End ------------------------------------------------*/ + +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Peripherals/RXDispatcher.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Peripherals/RXDispatcher.v new file mode 100644 index 0000000000000000000000000000000000000000..fa3d1256b0ee0be79a8c156b0edbd01b21f2edc7 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Peripherals/RXDispatcher.v @@ -0,0 +1,90 @@ +/*------------------------------------------- Module Description : Begin ---------------------------------------------- +Name: RXDispatcher +Author: YangFan +Function: 1.Dispatch RX packet. +--------------------------------------------- Module Decription : End -----------------------------------------------*/ + +/*------------------------------------------- Timescale Definition : Begin ------------------------------------------*/ +`timescale 1ns / 1ps +/*------------------------------------------- Timescale Definition : End --------------------------------------------*/ + +/*------------------------------------------- Included Files : Begin ------------------------------------------------*/ +`include "protocol_engine_def.vh" +/*------------------------------------------- Included Files : End --------------------------------------------------*/ + +/*------------------------------------------- Input/Output Definition : Begin ---------------------------------------*/ +module RXDispatcher +( + input wire clk, + input wire rst, + + input wire ingress_pkt_valid, + input wire [`PKT_META_BUS_WIDTH - 1 : 0] ingress_pkt_head, + output wire ingress_pkt_ready, + + output wire req_recv_pkt_valid, + output wire [`PKT_META_BUS_WIDTH - 1 : 0] req_recv_pkt_head, + input wire req_recv_pkt_ready, + + output wire resp_recv_pkt_valid, + output wire [`PKT_META_BUS_WIDTH - 1 : 0] resp_recv_pkt_head, + input wire resp_recv_pkt_ready +); + +/*------------------------------------------- Input/Output Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Macros Definition : Begin ---------------------------------------*/ +`define OPCODE_OFFSET 28:24 +/*------------------------------------------- Local Macros Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Variables Definition : Begin ------------------------------------*/ +/*------------------------------------------- Local Variables Definition : End --------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : Begin ---------------------------------------*/ +/*------------------------------------------- Submodules Instatiation : End -----------------------------------------*/ + +/*------------------------------------------- State Machine Definition : Begin --------------------------------------*/ +/*------------------------------------------- State Machine Definition : End ----------------------------------------*/ + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ +//-- req_recv_pkt_valid -- +//-- req_recv_pkt_head -- +assign req_recv_pkt_valid = (ingress_pkt_head[`OPCODE_OFFSET] == `SEND_FIRST || ingress_pkt_head[`OPCODE_OFFSET] == `SEND_MIDDLE || ingress_pkt_head[`OPCODE_OFFSET] == `SEND_LAST || + ingress_pkt_head[`OPCODE_OFFSET] == `SEND_ONLY || ingress_pkt_head[`OPCODE_OFFSET] == `SEND_LAST_WITH_IMM || ingress_pkt_head[`OPCODE_OFFSET] == `SEND_ONLY_WITH_IMM || + ingress_pkt_head[`OPCODE_OFFSET] == `RDMA_WRITE_FIRST || ingress_pkt_head[`OPCODE_OFFSET] == `RDMA_WRITE_MIDDLE || ingress_pkt_head[`OPCODE_OFFSET] == `RDMA_WRITE_LAST || + ingress_pkt_head[`OPCODE_OFFSET] == `RDMA_WRITE_ONLY || ingress_pkt_head[`OPCODE_OFFSET] == `RDMA_WRITE_LAST_WITH_IMM || ingress_pkt_head[`OPCODE_OFFSET] == `RDMA_WRITE_ONLY_WITH_IMM || + ingress_pkt_head[`OPCODE_OFFSET] == `RDMA_READ_REQUEST_FIRST || ingress_pkt_head[`OPCODE_OFFSET] == `RDMA_READ_REQUEST_MIDDLE || ingress_pkt_head[`OPCODE_OFFSET] == `RDMA_READ_REQUEST_LAST || + ingress_pkt_head[`OPCODE_OFFSET] == `RDMA_READ_REQUEST_ONLY) ? ingress_pkt_valid : 'd0; +assign req_recv_pkt_head = (ingress_pkt_head[`OPCODE_OFFSET] == `SEND_FIRST || ingress_pkt_head[`OPCODE_OFFSET] == `SEND_MIDDLE || ingress_pkt_head[`OPCODE_OFFSET] == `SEND_LAST || + ingress_pkt_head[`OPCODE_OFFSET] == `SEND_ONLY || ingress_pkt_head[`OPCODE_OFFSET] == `SEND_LAST_WITH_IMM || ingress_pkt_head[`OPCODE_OFFSET] == `SEND_ONLY_WITH_IMM || + ingress_pkt_head[`OPCODE_OFFSET] == `RDMA_WRITE_FIRST || ingress_pkt_head[`OPCODE_OFFSET] == `RDMA_WRITE_MIDDLE || ingress_pkt_head[`OPCODE_OFFSET] == `RDMA_WRITE_LAST || + ingress_pkt_head[`OPCODE_OFFSET] == `RDMA_WRITE_ONLY || ingress_pkt_head[`OPCODE_OFFSET] == `RDMA_WRITE_LAST_WITH_IMM || ingress_pkt_head[`OPCODE_OFFSET] == `RDMA_WRITE_ONLY_WITH_IMM || + ingress_pkt_head[`OPCODE_OFFSET] == `RDMA_READ_REQUEST_FIRST || ingress_pkt_head[`OPCODE_OFFSET] == `RDMA_READ_REQUEST_MIDDLE || ingress_pkt_head[`OPCODE_OFFSET] == `RDMA_READ_REQUEST_LAST || + ingress_pkt_head[`OPCODE_OFFSET] == `RDMA_READ_REQUEST_ONLY) ? ingress_pkt_head : 'd0; + +//-- resp_recv_pkt_valid -- +//-- resp_recv_pkt_head -- +assign resp_recv_pkt_valid = (ingress_pkt_head[`OPCODE_OFFSET] == `RDMA_READ_RESPONSE_FIRST || ingress_pkt_head[`OPCODE_OFFSET] == `RDMA_READ_RESPONSE_MIDDLE || + ingress_pkt_head[`OPCODE_OFFSET] == `RDMA_READ_RESPONSE_LAST || ingress_pkt_head[`OPCODE_OFFSET] == `RDMA_READ_RESPONSE_ONLY || + ingress_pkt_head[`OPCODE_OFFSET] == `ACKNOWLEDGE) ? ingress_pkt_valid : 'd0; +assign resp_recv_pkt_head = (ingress_pkt_head[`OPCODE_OFFSET] == `RDMA_READ_RESPONSE_FIRST || ingress_pkt_head[`OPCODE_OFFSET] == `RDMA_READ_RESPONSE_MIDDLE || + ingress_pkt_head[`OPCODE_OFFSET] == `RDMA_READ_RESPONSE_LAST || ingress_pkt_head[`OPCODE_OFFSET] == `RDMA_READ_RESPONSE_ONLY || + ingress_pkt_head[`OPCODE_OFFSET] == `ACKNOWLEDGE) ? ingress_pkt_head : 'd0; + +//-- ingress_pkt_ready -- +assign ingress_pkt_ready = (ingress_pkt_head[`OPCODE_OFFSET] == `SEND_FIRST || ingress_pkt_head[`OPCODE_OFFSET] == `SEND_MIDDLE || ingress_pkt_head[`OPCODE_OFFSET] == `SEND_LAST || + ingress_pkt_head[`OPCODE_OFFSET] == `SEND_ONLY || ingress_pkt_head[`OPCODE_OFFSET] == `SEND_LAST_WITH_IMM || ingress_pkt_head[`OPCODE_OFFSET] == `SEND_ONLY_WITH_IMM || + ingress_pkt_head[`OPCODE_OFFSET] == `RDMA_WRITE_FIRST || ingress_pkt_head[`OPCODE_OFFSET] == `RDMA_WRITE_MIDDLE || ingress_pkt_head[`OPCODE_OFFSET] == `RDMA_WRITE_LAST || + ingress_pkt_head[`OPCODE_OFFSET] == `RDMA_WRITE_ONLY || ingress_pkt_head[`OPCODE_OFFSET] == `RDMA_WRITE_LAST_WITH_IMM || ingress_pkt_head[`OPCODE_OFFSET] == `RDMA_WRITE_ONLY_WITH_IMM || + ingress_pkt_head[`OPCODE_OFFSET] == `RDMA_READ_REQUEST_FIRST || ingress_pkt_head[`OPCODE_OFFSET] == `RDMA_READ_REQUEST_MIDDLE || ingress_pkt_head[`OPCODE_OFFSET] == `RDMA_READ_REQUEST_LAST || + ingress_pkt_head[`OPCODE_OFFSET] == `RDMA_READ_REQUEST_ONLY) ? req_recv_pkt_ready : + (ingress_pkt_head[`OPCODE_OFFSET] == `RDMA_READ_RESPONSE_FIRST || ingress_pkt_head[`OPCODE_OFFSET] == `RDMA_READ_RESPONSE_MIDDLE || + ingress_pkt_head[`OPCODE_OFFSET] == `RDMA_READ_RESPONSE_LAST || ingress_pkt_head[`OPCODE_OFFSET] == `RDMA_READ_RESPONSE_ONLY || + ingress_pkt_head[`OPCODE_OFFSET] == `ACKNOWLEDGE) ? resp_recv_pkt_ready : 'd0; +/*------------------------------------------- Variables Decode : End ----------------------------------------------*/ + +/*------------------------------------------- Local Macros Undef : Begin --------------------------------------------*/ +`undef OPCODE_OFFSET +/*------------------------------------------- Local Macros Undef : End ----------------------------------------------*/ + +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Peripherals/ScatterData.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Peripherals/ScatterData.v new file mode 100644 index 0000000000000000000000000000000000000000..a84b4b601c365604a8c44e1e2b160ab50c2e79e9 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Peripherals/ScatterData.v @@ -0,0 +1,801 @@ +/*------------------------------------------- Module Description : Begin ---------------------------------------------- +Name: ScatterData +Author: YangFan +Function: Scatters continous stream to non-contiguous memory page. +--------------------------------------------- Module Decription : End -----------------------------------------------*/ + +/*------------------------------------------- Timescale Definition : Begin ------------------------------------------*/ +`timescale 1ns / 1ps +/*------------------------------------------- Timescale Definition : End --------------------------------------------*/ + +/*------------------------------------------- Included Files : Begin ------------------------------------------------*/ +`include "protocol_engine_def.vh" +/*------------------------------------------- Included Files : End --------------------------------------------------*/ + +/*------------------------------------------- Local Macros Definition : Begin ---------------------------------------*/ +/*------------------------------------------- Local Macros Definition : End -----------------------------------------*/ + +/*------------------------------------------- Input/Output Definition : Begin ---------------------------------------*/ +module ScatterData +( + input wire clk, + input wire rst, + + input wire scatter_req_wr_en, + input wire [`DMA_LENGTH_WIDTH * 2 + `DMA_ADDR_WIDTH - 1 : 0] scatter_req_din, + output wire scatter_req_prog_full, + + input wire scatter_data_wr_en, + input wire [`DMA_DATA_WIDTH - 1 : 0] scatter_data_din, + output wire scatter_data_prog_full, + + output wire dma_wr_req_valid, + output wire dma_wr_req_last , + output wire [`DMA_HEAD_WIDTH - 1 : 0] dma_wr_req_head , + output wire [`DMA_DATA_WIDTH - 1 : 0] dma_wr_req_data , + input wire dma_wr_req_ready +); +/*------------------------------------------- Input/Output Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Variables Definition : Begin ------------------------------------*/ +wire scatter_req_rd_en; +wire [`DMA_LENGTH_WIDTH * 2 + `DMA_ADDR_WIDTH - 1 : 0] scatter_req_dout; +wire scatter_req_empty; + +reg q_dma_wr_req_valid; +reg q_dma_wr_req_last; +reg [(`DMA_DATA_WIDTH - 1) : 0] qv_dma_wr_req_data; +reg [(`DMA_HEAD_WIDTH - 1) : 0] qv_dma_wr_req_head; + +reg q_dma_wr_req_valid_diff; +reg q_dma_wr_req_last_diff; +reg [(`DMA_DATA_WIDTH -1):0] qv_dma_wr_req_data_diff; +reg [(`DMA_HEAD_WIDTH -1):0] qv_dma_wr_req_head_diff; + +wire scatter_data_rd_en; +wire [`DMA_DATA_WIDTH - 1 : 0] scatter_data_dout; +wire scatter_data_empty; + +wire [`DMA_LENGTH_WIDTH - 1 : 0] wv_cur_req_length; +wire [`DMA_LENGTH_WIDTH - 1 : 0] wv_cur_page_length; +wire w_channel_empty; +wire [`DMA_DATA_WIDTH - 1 : 0] wv_channel_dout; + +reg q_channel_rd_en; + +reg [`DMA_LENGTH_WIDTH - 1 : 0] qv_req_length_left; +reg [`DMA_LENGTH_WIDTH - 1 : 0] qv_page_length_left; + +reg [`DMA_LENGTH_WIDTH - 1 : 0] qv_unwritten_len; +reg [`DMA_DATA_WIDTH - 1 : 0] qv_unwritten_data; + +wire w_last_page_of_req; +reg [`DMA_LENGTH_WIDTH - 1 : 0] qv_offset; +/*------------------------------------------- Local Variables Definition : End --------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : Begin ---------------------------------------*/ +SyncFIFO_Template #( + .FIFO_TYPE (0), + .FIFO_WIDTH (`DMA_LENGTH_WIDTH * 2 + `DMA_ADDR_WIDTH), + .FIFO_DEPTH (64) +) +scatter_req_fifo +( + .clk(clk), + .rst(rst), + + .wr_en(scatter_req_wr_en), + .din(scatter_req_din), + .prog_full(scatter_req_prog_full), + .rd_en(scatter_req_rd_en), + .dout(scatter_req_dout), + .empty(scatter_req_empty), + .data_count() +); + + +SyncFIFO_Template #( + .FIFO_TYPE (0), + .FIFO_WIDTH (`DMA_DATA_WIDTH), + .FIFO_DEPTH (64) +) +scatter_data_fifo +( + .clk(clk), + .rst(rst), + + .wr_en(scatter_data_wr_en), + .din(scatter_data_din), + .prog_full(scatter_data_prog_full), + .rd_en(scatter_data_rd_en), + .dout(scatter_data_dout), + .empty(scatter_data_empty), + .data_count() +); + +/*------------------------------------------- Submodules Instatiation : End -----------------------------------------*/ + +/*------------------------------------------- State Machine Definition : Begin --------------------------------------*/ +parameter REQ_IDLE_s = 2'b01, + REQ_UPLOAD_s = 2'b10; + +reg [1:0] req_cur_state; +reg [1:0] req_next_state; +reg [1:0] req_pre_state; + +always @(posedge clk or posedge rst) begin + if(rst) begin + req_pre_state <= REQ_IDLE_s; + end + else begin + req_pre_state <= req_cur_state; + end +end + +always @(posedge clk or posedge rst) begin + if(rst) begin + req_cur_state <= REQ_IDLE_s; + end + else begin + req_cur_state <= req_next_state; + end +end + +always @(*) begin + case(req_cur_state) + REQ_IDLE_s: if(!scatter_req_empty && !w_channel_empty) begin + req_next_state = REQ_UPLOAD_s; + end + else begin + req_next_state = REQ_IDLE_s; + end + REQ_UPLOAD_s: if(qv_page_length_left + qv_unwritten_len > 64) begin + req_next_state = REQ_UPLOAD_s; + end + else begin // <=64, judge whether need valid signal + if(qv_page_length_left > 0 && !w_channel_empty && dma_wr_req_ready) begin //Need valid indicator + req_next_state = REQ_IDLE_s; + end + else if(qv_page_length_left == 0 && dma_wr_req_ready) begin + req_next_state = REQ_IDLE_s; + end + else begin + req_next_state = REQ_UPLOAD_s; + end + end + default: req_next_state = REQ_IDLE_s; + endcase +end +/*------------------------------------------- State Machine Definition : End ----------------------------------------*/ + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ +//-- scatter_req_rd_en -- +assign scatter_req_rd_en = (req_cur_state == REQ_UPLOAD_s) && (req_next_state == REQ_IDLE_s); + + +//-- dma_wr_req_valid -- +assign dma_wr_req_valid = q_dma_wr_req_valid; +//-- dma_wr_req_last -- +assign dma_wr_req_last = q_dma_wr_req_last ; +//-- dma_wr_req_data -- +assign dma_wr_req_data = qv_dma_wr_req_data; +//-- dma_wr_req_head -- +assign dma_wr_req_head = qv_dma_wr_req_head; + +//-- wv_cur_req_length -- +assign wv_cur_req_length = scatter_req_dout[127:96]; +//-- wv_cur_page_length -- +assign wv_cur_page_length = scatter_req_dout[95:64]; + +//-- w_channel_empty -- +assign w_channel_empty = scatter_data_empty; + +//-- wv_channel_dout -- +assign wv_channel_dout = scatter_data_dout; + +//-- scatter_data_rd_en -- +assign scatter_data_rd_en = q_channel_rd_en; + +//-- w_last_page_of_req -- +assign w_last_page_of_req = (qv_req_length_left == qv_page_length_left); + +//-- q_dma_wr_req_valid_diff -- +//-- q_dma_wr_req_last_diff -- +//-- qv_dma_wr_req_data_diff -- +//-- qv_dma_wr_req_head_diff -- +always @(posedge clk or posedge rst) begin + if(rst) begin + q_dma_wr_req_valid_diff <= 'd0; + q_dma_wr_req_last_diff <= 'd0; + qv_dma_wr_req_data_diff <= 'd0; + qv_dma_wr_req_head_diff <= 'd0; + end + else begin + q_dma_wr_req_valid_diff <= q_dma_wr_req_valid; + q_dma_wr_req_last_diff <= q_dma_wr_req_last; + qv_dma_wr_req_data_diff <= qv_dma_wr_req_data; + qv_dma_wr_req_head_diff <= qv_dma_wr_req_head; + end +end + +//-- qv_page_length_left -- +always @(posedge clk or posedge rst) begin + if(rst) begin + qv_page_length_left <= 'd0; + end + else if(req_cur_state == REQ_IDLE_s && !scatter_req_empty && !w_channel_empty) begin + qv_page_length_left <= wv_cur_page_length - qv_unwritten_len; + end + else if(req_cur_state == REQ_UPLOAD_s) begin + if(qv_page_length_left > 0 && !w_channel_empty && dma_wr_req_ready) begin + if(qv_page_length_left > 64) begin + qv_page_length_left <= qv_page_length_left - 64; + end + else begin + qv_page_length_left <= 'd0; + end + end + else begin + qv_page_length_left <= qv_page_length_left; + end + end + else begin + qv_page_length_left <= qv_page_length_left; + end +end + +//-- qv_req_length_left -- +always @(posedge clk or posedge rst) begin + if(rst) begin + qv_req_length_left <= 'd0; + end + else if(req_cur_state == REQ_IDLE_s && !scatter_req_empty && !w_channel_empty) begin + if(qv_req_length_left == 0) begin + qv_req_length_left <= wv_cur_req_length - qv_unwritten_len; + end + else begin + qv_req_length_left <= qv_req_length_left - qv_unwritten_len; + end + end + else if(req_cur_state == REQ_UPLOAD_s) begin + if(qv_page_length_left > 0 && !w_channel_empty && dma_wr_req_ready) begin + if(qv_page_length_left > 64) begin + qv_req_length_left <= qv_req_length_left - 64; + end + else begin + qv_req_length_left <= qv_req_length_left - qv_page_length_left; + end + end + else begin + qv_req_length_left <= qv_req_length_left; + end + end + else begin + qv_req_length_left <= qv_req_length_left; + end +end + +//-- qv_offset -- +always @(posedge clk or posedge rst) begin + if(rst) begin + qv_offset <= 'd0; + end + else if((qv_page_length_left + qv_unwritten_len >= 64) && !w_channel_empty && dma_wr_req_ready) begin + qv_offset <= 64 - qv_unwritten_len; + end + else begin + qv_offset <= qv_offset; + end +end + +//-- qv_unwritten_len -- +always @(posedge clk or posedge rst) begin + if(rst) begin + qv_unwritten_len <= 'd0; + end + else if(req_cur_state == REQ_IDLE_s) begin + qv_unwritten_len <= qv_unwritten_len; + end + else if(req_cur_state == REQ_UPLOAD_s) begin //qv_unwritten_len need to consider wthether is the last mtt + if(qv_page_length_left > 0 && !w_channel_empty && dma_wr_req_ready) begin + if(qv_page_length_left >= 64) begin + qv_unwritten_len <= qv_unwritten_len; + end + else if(qv_page_length_left + qv_unwritten_len >= 64)begin + qv_unwritten_len <= qv_page_length_left + qv_unwritten_len - 64; + end + else begin + qv_unwritten_len <= w_last_page_of_req ? 'd0 : (64 - qv_page_length_left); + end + end + else if(qv_page_length_left == 0 && dma_wr_req_ready) begin + qv_unwritten_len <= w_last_page_of_req ? 'd0 : (64 - qv_unwritten_len - qv_offset); + end + else begin + qv_unwritten_len <= qv_unwritten_len; + end + end + else begin + qv_unwritten_len <= qv_unwritten_len; + end +end + +//-- qv_unwritten_data -- +always @(posedge clk or posedge rst) begin + if(rst) begin + qv_unwritten_data <= 'd0; + end + else if(req_cur_state == REQ_UPLOAD_s) begin + if(qv_page_length_left > 0 && !w_channel_empty && dma_wr_req_ready) begin + if((qv_page_length_left >= 64) || (qv_page_length_left + qv_unwritten_len >= 64)) begin + case(qv_unwritten_len) + 0 : qv_unwritten_data <= 'd0; + 1 : qv_unwritten_data <= {{((64 - 1 ) * 8){1'b0}}, wv_channel_dout[511 : (64 - 1 ) * 8]}; + 2 : qv_unwritten_data <= {{((64 - 2 ) * 8){1'b0}}, wv_channel_dout[511 : (64 - 2 ) * 8]}; + 3 : qv_unwritten_data <= {{((64 - 3 ) * 8){1'b0}}, wv_channel_dout[511 : (64 - 3 ) * 8]}; + 4 : qv_unwritten_data <= {{((64 - 4 ) * 8){1'b0}}, wv_channel_dout[511 : (64 - 4 ) * 8]}; + 5 : qv_unwritten_data <= {{((64 - 5 ) * 8){1'b0}}, wv_channel_dout[511 : (64 - 5 ) * 8]}; + 6 : qv_unwritten_data <= {{((64 - 6 ) * 8){1'b0}}, wv_channel_dout[511 : (64 - 6 ) * 8]}; + 7 : qv_unwritten_data <= {{((64 - 7 ) * 8){1'b0}}, wv_channel_dout[511 : (64 - 7 ) * 8]}; + 8 : qv_unwritten_data <= {{((64 - 8 ) * 8){1'b0}}, wv_channel_dout[511 : (64 - 8 ) * 8]}; + 9 : qv_unwritten_data <= {{((64 - 9 ) * 8){1'b0}}, wv_channel_dout[511 : (64 - 9 ) * 8]}; + 10 : qv_unwritten_data <= {{((64 - 10) * 8){1'b0}}, wv_channel_dout[511 : (64 - 10) * 8]}; + 11 : qv_unwritten_data <= {{((64 - 11) * 8){1'b0}}, wv_channel_dout[511 : (64 - 11) * 8]}; + 12 : qv_unwritten_data <= {{((64 - 12) * 8){1'b0}}, wv_channel_dout[511 : (64 - 12) * 8]}; + 13 : qv_unwritten_data <= {{((64 - 13) * 8){1'b0}}, wv_channel_dout[511 : (64 - 13) * 8]}; + 14 : qv_unwritten_data <= {{((64 - 14) * 8){1'b0}}, wv_channel_dout[511 : (64 - 14) * 8]}; + 15 : qv_unwritten_data <= {{((64 - 15) * 8){1'b0}}, wv_channel_dout[511 : (64 - 15) * 8]}; + 16 : qv_unwritten_data <= {{((64 - 16) * 8){1'b0}}, wv_channel_dout[511 : (64 - 16) * 8]}; + 17 : qv_unwritten_data <= {{((64 - 17) * 8){1'b0}}, wv_channel_dout[511 : (64 - 17) * 8]}; + 18 : qv_unwritten_data <= {{((64 - 18) * 8){1'b0}}, wv_channel_dout[511 : (64 - 18) * 8]}; + 19 : qv_unwritten_data <= {{((64 - 19) * 8){1'b0}}, wv_channel_dout[511 : (64 - 19) * 8]}; + 20 : qv_unwritten_data <= {{((64 - 20) * 8){1'b0}}, wv_channel_dout[511 : (64 - 20) * 8]}; + 21 : qv_unwritten_data <= {{((64 - 21) * 8){1'b0}}, wv_channel_dout[511 : (64 - 21) * 8]}; + 22 : qv_unwritten_data <= {{((64 - 22) * 8){1'b0}}, wv_channel_dout[511 : (64 - 22) * 8]}; + 23 : qv_unwritten_data <= {{((64 - 23) * 8){1'b0}}, wv_channel_dout[511 : (64 - 23) * 8]}; + 24 : qv_unwritten_data <= {{((64 - 24) * 8){1'b0}}, wv_channel_dout[511 : (64 - 24) * 8]}; + 25 : qv_unwritten_data <= {{((64 - 25) * 8){1'b0}}, wv_channel_dout[511 : (64 - 25) * 8]}; + 26 : qv_unwritten_data <= {{((64 - 26) * 8){1'b0}}, wv_channel_dout[511 : (64 - 26) * 8]}; + 27 : qv_unwritten_data <= {{((64 - 27) * 8){1'b0}}, wv_channel_dout[511 : (64 - 27) * 8]}; + 28 : qv_unwritten_data <= {{((64 - 28) * 8){1'b0}}, wv_channel_dout[511 : (64 - 28) * 8]}; + 29 : qv_unwritten_data <= {{((64 - 29) * 8){1'b0}}, wv_channel_dout[511 : (64 - 29) * 8]}; + 30 : qv_unwritten_data <= {{((64 - 30) * 8){1'b0}}, wv_channel_dout[511 : (64 - 30) * 8]}; + 31 : qv_unwritten_data <= {{((64 - 31) * 8){1'b0}}, wv_channel_dout[511 : (64 - 31) * 8]}; + 32 : qv_unwritten_data <= {{((64 - 32) * 8){1'b0}}, wv_channel_dout[511 : (64 - 32) * 8]}; + 33 : qv_unwritten_data <= {{((64 - 33) * 8){1'b0}}, wv_channel_dout[511 : (64 - 33) * 8]}; + 34 : qv_unwritten_data <= {{((64 - 34) * 8){1'b0}}, wv_channel_dout[511 : (64 - 34) * 8]}; + 35 : qv_unwritten_data <= {{((64 - 35) * 8){1'b0}}, wv_channel_dout[511 : (64 - 35) * 8]}; + 36 : qv_unwritten_data <= {{((64 - 36) * 8){1'b0}}, wv_channel_dout[511 : (64 - 36) * 8]}; + 37 : qv_unwritten_data <= {{((64 - 37) * 8){1'b0}}, wv_channel_dout[511 : (64 - 37) * 8]}; + 38 : qv_unwritten_data <= {{((64 - 38) * 8){1'b0}}, wv_channel_dout[511 : (64 - 38) * 8]}; + 39 : qv_unwritten_data <= {{((64 - 39) * 8){1'b0}}, wv_channel_dout[511 : (64 - 39) * 8]}; + 40 : qv_unwritten_data <= {{((64 - 40) * 8){1'b0}}, wv_channel_dout[511 : (64 - 40) * 8]}; + 41 : qv_unwritten_data <= {{((64 - 41) * 8){1'b0}}, wv_channel_dout[511 : (64 - 41) * 8]}; + 42 : qv_unwritten_data <= {{((64 - 42) * 8){1'b0}}, wv_channel_dout[511 : (64 - 42) * 8]}; + 43 : qv_unwritten_data <= {{((64 - 43) * 8){1'b0}}, wv_channel_dout[511 : (64 - 43) * 8]}; + 44 : qv_unwritten_data <= {{((64 - 44) * 8){1'b0}}, wv_channel_dout[511 : (64 - 44) * 8]}; + 45 : qv_unwritten_data <= {{((64 - 45) * 8){1'b0}}, wv_channel_dout[511 : (64 - 45) * 8]}; + 46 : qv_unwritten_data <= {{((64 - 46) * 8){1'b0}}, wv_channel_dout[511 : (64 - 46) * 8]}; + 47 : qv_unwritten_data <= {{((64 - 47) * 8){1'b0}}, wv_channel_dout[511 : (64 - 47) * 8]}; + 48 : qv_unwritten_data <= {{((64 - 48) * 8){1'b0}}, wv_channel_dout[511 : (64 - 48) * 8]}; + 49 : qv_unwritten_data <= {{((64 - 49) * 8){1'b0}}, wv_channel_dout[511 : (64 - 49) * 8]}; + 50 : qv_unwritten_data <= {{((64 - 50) * 8){1'b0}}, wv_channel_dout[511 : (64 - 50) * 8]}; + 51 : qv_unwritten_data <= {{((64 - 51) * 8){1'b0}}, wv_channel_dout[511 : (64 - 51) * 8]}; + 52 : qv_unwritten_data <= {{((64 - 52) * 8){1'b0}}, wv_channel_dout[511 : (64 - 52) * 8]}; + 53 : qv_unwritten_data <= {{((64 - 53) * 8){1'b0}}, wv_channel_dout[511 : (64 - 53) * 8]}; + 54 : qv_unwritten_data <= {{((64 - 54) * 8){1'b0}}, wv_channel_dout[511 : (64 - 54) * 8]}; + 55 : qv_unwritten_data <= {{((64 - 55) * 8){1'b0}}, wv_channel_dout[511 : (64 - 55) * 8]}; + 56 : qv_unwritten_data <= {{((64 - 56) * 8){1'b0}}, wv_channel_dout[511 : (64 - 56) * 8]}; + 57 : qv_unwritten_data <= {{((64 - 57) * 8){1'b0}}, wv_channel_dout[511 : (64 - 57) * 8]}; + 58 : qv_unwritten_data <= {{((64 - 58) * 8){1'b0}}, wv_channel_dout[511 : (64 - 58) * 8]}; + 59 : qv_unwritten_data <= {{((64 - 59) * 8){1'b0}}, wv_channel_dout[511 : (64 - 59) * 8]}; + 60 : qv_unwritten_data <= {{((64 - 60) * 8){1'b0}}, wv_channel_dout[511 : (64 - 60) * 8]}; + 61 : qv_unwritten_data <= {{((64 - 61) * 8){1'b0}}, wv_channel_dout[511 : (64 - 61) * 8]}; + 62 : qv_unwritten_data <= {{((64 - 62) * 8){1'b0}}, wv_channel_dout[511 : (64 - 62) * 8]}; + 63 : qv_unwritten_data <= {{((64 - 63) * 8){1'b0}}, wv_channel_dout[511 : (64 - 63) * 8]}; + default: qv_unwritten_data <= qv_unwritten_data; + endcase + end + else if(qv_page_length_left + qv_unwritten_len < 64) begin + if(w_last_page_of_req) begin + qv_unwritten_data <= 'd0; + end + else begin //piece together and wait for next ntt data + case(qv_page_length_left) + 0 : qv_unwritten_data <= wv_channel_dout; + 1 : qv_unwritten_data <= {{(64 - 1 )* 8{1'b0}}, wv_channel_dout[511 : 1 * 8]}; + 2 : qv_unwritten_data <= {{(64 - 2 )* 8{1'b0}}, wv_channel_dout[511 : 2 * 8]}; + 3 : qv_unwritten_data <= {{(64 - 3 )* 8{1'b0}}, wv_channel_dout[511 : 3 * 8]}; + 4 : qv_unwritten_data <= {{(64 - 4 )* 8{1'b0}}, wv_channel_dout[511 : 4 * 8]}; + 5 : qv_unwritten_data <= {{(64 - 5 )* 8{1'b0}}, wv_channel_dout[511 : 5 * 8]}; + 6 : qv_unwritten_data <= {{(64 - 6 )* 8{1'b0}}, wv_channel_dout[511 : 6 * 8]}; + 7 : qv_unwritten_data <= {{(64 - 7 )* 8{1'b0}}, wv_channel_dout[511 : 7 * 8]}; + 8 : qv_unwritten_data <= {{(64 - 8 )* 8{1'b0}}, wv_channel_dout[511 : 8 * 8]}; + 9 : qv_unwritten_data <= {{(64 - 9 )* 8{1'b0}}, wv_channel_dout[511 : 9 * 8]}; + 10 : qv_unwritten_data <= {{(64 - 10)* 8{1'b0}}, wv_channel_dout[511 : 10 * 8]}; + 11 : qv_unwritten_data <= {{(64 - 11)* 8{1'b0}}, wv_channel_dout[511 : 11 * 8]}; + 12 : qv_unwritten_data <= {{(64 - 12)* 8{1'b0}}, wv_channel_dout[511 : 12 * 8]}; + 13 : qv_unwritten_data <= {{(64 - 13)* 8{1'b0}}, wv_channel_dout[511 : 13 * 8]}; + 14 : qv_unwritten_data <= {{(64 - 14)* 8{1'b0}}, wv_channel_dout[511 : 14 * 8]}; + 15 : qv_unwritten_data <= {{(64 - 15)* 8{1'b0}}, wv_channel_dout[511 : 15 * 8]}; + 16 : qv_unwritten_data <= {{(64 - 16)* 8{1'b0}}, wv_channel_dout[511 : 16 * 8]}; + 17 : qv_unwritten_data <= {{(64 - 17)* 8{1'b0}}, wv_channel_dout[511 : 17 * 8]}; + 18 : qv_unwritten_data <= {{(64 - 18)* 8{1'b0}}, wv_channel_dout[511 : 18 * 8]}; + 19 : qv_unwritten_data <= {{(64 - 19)* 8{1'b0}}, wv_channel_dout[511 : 19 * 8]}; + 20 : qv_unwritten_data <= {{(64 - 20)* 8{1'b0}}, wv_channel_dout[511 : 20 * 8]}; + 21 : qv_unwritten_data <= {{(64 - 21)* 8{1'b0}}, wv_channel_dout[511 : 21 * 8]}; + 22 : qv_unwritten_data <= {{(64 - 22)* 8{1'b0}}, wv_channel_dout[511 : 22 * 8]}; + 23 : qv_unwritten_data <= {{(64 - 23)* 8{1'b0}}, wv_channel_dout[511 : 23 * 8]}; + 24 : qv_unwritten_data <= {{(64 - 24)* 8{1'b0}}, wv_channel_dout[511 : 24 * 8]}; + 25 : qv_unwritten_data <= {{(64 - 25)* 8{1'b0}}, wv_channel_dout[511 : 25 * 8]}; + 26 : qv_unwritten_data <= {{(64 - 26)* 8{1'b0}}, wv_channel_dout[511 : 26 * 8]}; + 27 : qv_unwritten_data <= {{(64 - 27)* 8{1'b0}}, wv_channel_dout[511 : 27 * 8]}; + 28 : qv_unwritten_data <= {{(64 - 28)* 8{1'b0}}, wv_channel_dout[511 : 28 * 8]}; + 29 : qv_unwritten_data <= {{(64 - 29)* 8{1'b0}}, wv_channel_dout[511 : 29 * 8]}; + 30 : qv_unwritten_data <= {{(64 - 30) * 8{1'b0}}, wv_channel_dout[511 : 30 * 8]}; + 31 : qv_unwritten_data <= {{(64 - 31) * 8{1'b0}}, wv_channel_dout[511 : 31 * 8]}; + 32 : qv_unwritten_data <= {{((64 - 32) * 8){1'b0}}, wv_channel_dout[511 : 32 * 8]}; + 33 : qv_unwritten_data <= {{((64 - 33) * 8){1'b0}}, wv_channel_dout[511 : 33 * 8]}; + 34 : qv_unwritten_data <= {{((64 - 34) * 8){1'b0}}, wv_channel_dout[511 : 34 * 8]}; + 35 : qv_unwritten_data <= {{((64 - 35) * 8){1'b0}}, wv_channel_dout[511 : 35 * 8]}; + 36 : qv_unwritten_data <= {{((64 - 36) * 8){1'b0}}, wv_channel_dout[511 : 36 * 8]}; + 37 : qv_unwritten_data <= {{((64 - 37) * 8){1'b0}}, wv_channel_dout[511 : 37 * 8]}; + 38 : qv_unwritten_data <= {{((64 - 38) * 8){1'b0}}, wv_channel_dout[511 : 38 * 8]}; + 39 : qv_unwritten_data <= {{((64 - 39) * 8){1'b0}}, wv_channel_dout[511 : 39 * 8]}; + 40 : qv_unwritten_data <= {{((64 - 40) * 8){1'b0}}, wv_channel_dout[511 : 40 * 8]}; + 41 : qv_unwritten_data <= {{((64 - 41) * 8){1'b0}}, wv_channel_dout[511 : 41 * 8]}; + 42 : qv_unwritten_data <= {{((64 - 42) * 8){1'b0}}, wv_channel_dout[511 : 42 * 8]}; + 43 : qv_unwritten_data <= {{((64 - 43) * 8){1'b0}}, wv_channel_dout[511 : 43 * 8]}; + 44 : qv_unwritten_data <= {{((64 - 44) * 8){1'b0}}, wv_channel_dout[511 : 44 * 8]}; + 45 : qv_unwritten_data <= {{((64 - 45) * 8){1'b0}}, wv_channel_dout[511 : 45 * 8]}; + 46 : qv_unwritten_data <= {{((64 - 46) * 8){1'b0}}, wv_channel_dout[511 : 46 * 8]}; + 47 : qv_unwritten_data <= {{((64 - 47) * 8){1'b0}}, wv_channel_dout[511 : 47 * 8]}; + 48 : qv_unwritten_data <= {{((64 - 48) * 8){1'b0}}, wv_channel_dout[511 : 48 * 8]}; + 49 : qv_unwritten_data <= {{((64 - 49) * 8){1'b0}}, wv_channel_dout[511 : 49 * 8]}; + 50 : qv_unwritten_data <= {{((64 - 50) * 8){1'b0}}, wv_channel_dout[511 : 50 * 8]}; + 51 : qv_unwritten_data <= {{((64 - 51) * 8){1'b0}}, wv_channel_dout[511 : 51 * 8]}; + 52 : qv_unwritten_data <= {{((64 - 52) * 8){1'b0}}, wv_channel_dout[511 : 52 * 8]}; + 53 : qv_unwritten_data <= {{((64 - 53) * 8){1'b0}}, wv_channel_dout[511 : 53 * 8]}; + 54 : qv_unwritten_data <= {{((64 - 54) * 8){1'b0}}, wv_channel_dout[511 : 54 * 8]}; + 55 : qv_unwritten_data <= {{((64 - 55) * 8){1'b0}}, wv_channel_dout[511 : 55 * 8]}; + 56 : qv_unwritten_data <= {{((64 - 56) * 8){1'b0}}, wv_channel_dout[511 : 56 * 8]}; + 57 : qv_unwritten_data <= {{((64 - 57) * 8){1'b0}}, wv_channel_dout[511 : 57 * 8]}; + 58 : qv_unwritten_data <= {{((64 - 58) * 8){1'b0}}, wv_channel_dout[511 : 58 * 8]}; + 59 : qv_unwritten_data <= {{((64 - 59) * 8){1'b0}}, wv_channel_dout[511 : 59 * 8]}; + 60 : qv_unwritten_data <= {{((64 - 60) * 8){1'b0}}, wv_channel_dout[511 : 60 * 8]}; + 61 : qv_unwritten_data <= {{((64 - 61) * 8){1'b0}}, wv_channel_dout[511 : 61 * 8]}; + 62 : qv_unwritten_data <= {{((64 - 62) * 8){1'b0}}, wv_channel_dout[511 : 62 * 8]}; + 63 : qv_unwritten_data <= {{((64 - 63) * 8){1'b0}}, wv_channel_dout[511 : 63 * 8]}; + default: qv_unwritten_data <= qv_unwritten_data; + endcase + end + end + else begin + qv_unwritten_data <= qv_unwritten_data; + end + end + else if(qv_page_length_left == 0 && dma_wr_req_ready) begin + if(w_last_page_of_req) begin + qv_unwritten_data <= 'd0; + end + else begin + case(qv_unwritten_len + qv_offset) + 0 : qv_unwritten_data <= wv_channel_dout; + 1 : qv_unwritten_data <= {{(64 - 1 )* 8{1'b0}}, wv_channel_dout[511 : 1 * 8]}; + 2 : qv_unwritten_data <= {{(64 - 2 )* 8{1'b0}}, wv_channel_dout[511 : 2 * 8]}; + 3 : qv_unwritten_data <= {{(64 - 3 )* 8{1'b0}}, wv_channel_dout[511 : 3 * 8]}; + 4 : qv_unwritten_data <= {{(64 - 4 )* 8{1'b0}}, wv_channel_dout[511 : 4 * 8]}; + 5 : qv_unwritten_data <= {{(64 - 5 )* 8{1'b0}}, wv_channel_dout[511 : 5 * 8]}; + 6 : qv_unwritten_data <= {{(64 - 6 )* 8{1'b0}}, wv_channel_dout[511 : 6 * 8]}; + 7 : qv_unwritten_data <= {{(64 - 7 )* 8{1'b0}}, wv_channel_dout[511 : 7 * 8]}; + 8 : qv_unwritten_data <= {{(64 - 8 )* 8{1'b0}}, wv_channel_dout[511 : 8 * 8]}; + 9 : qv_unwritten_data <= {{(64 - 9 )* 8{1'b0}}, wv_channel_dout[511 : 9 * 8]}; + 10 : qv_unwritten_data <= {{(64 - 10)* 8{1'b0}}, wv_channel_dout[511 : 10 * 8]}; + 11 : qv_unwritten_data <= {{(64 - 11)* 8{1'b0}}, wv_channel_dout[511 : 11 * 8]}; + 12 : qv_unwritten_data <= {{(64 - 12)* 8{1'b0}}, wv_channel_dout[511 : 12 * 8]}; + 13 : qv_unwritten_data <= {{(64 - 13)* 8{1'b0}}, wv_channel_dout[511 : 13 * 8]}; + 14 : qv_unwritten_data <= {{(64 - 14)* 8{1'b0}}, wv_channel_dout[511 : 14 * 8]}; + 15 : qv_unwritten_data <= {{(64 - 15)* 8{1'b0}}, wv_channel_dout[511 : 15 * 8]}; + 16 : qv_unwritten_data <= {{(64 - 16)* 8{1'b0}}, wv_channel_dout[511 : 16 * 8]}; + 17 : qv_unwritten_data <= {{(64 - 17)* 8{1'b0}}, wv_channel_dout[511 : 17 * 8]}; + 18 : qv_unwritten_data <= {{(64 - 18)* 8{1'b0}}, wv_channel_dout[511 : 18 * 8]}; + 19 : qv_unwritten_data <= {{(64 - 19)* 8{1'b0}}, wv_channel_dout[511 : 19 * 8]}; + 20 : qv_unwritten_data <= {{(64 - 20)* 8{1'b0}}, wv_channel_dout[511 : 20 * 8]}; + 21 : qv_unwritten_data <= {{(64 - 21)* 8{1'b0}}, wv_channel_dout[511 : 21 * 8]}; + 22 : qv_unwritten_data <= {{(64 - 22)* 8{1'b0}}, wv_channel_dout[511 : 22 * 8]}; + 23 : qv_unwritten_data <= {{(64 - 23)* 8{1'b0}}, wv_channel_dout[511 : 23 * 8]}; + 24 : qv_unwritten_data <= {{(64 - 24)* 8{1'b0}}, wv_channel_dout[511 : 24 * 8]}; + 25 : qv_unwritten_data <= {{(64 - 25)* 8{1'b0}}, wv_channel_dout[511 : 25 * 8]}; + 26 : qv_unwritten_data <= {{(64 - 26)* 8{1'b0}}, wv_channel_dout[511 : 26 * 8]}; + 27 : qv_unwritten_data <= {{(64 - 27)* 8{1'b0}}, wv_channel_dout[511 : 27 * 8]}; + 28 : qv_unwritten_data <= {{(64 - 28)* 8{1'b0}}, wv_channel_dout[511 : 28 * 8]}; + 29 : qv_unwritten_data <= {{(64 - 29)* 8{1'b0}}, wv_channel_dout[511 : 29 * 8]}; + 30 : qv_unwritten_data <= {{(64 - 30) * 8{1'b0}}, wv_channel_dout[511 : 30 * 8]}; + 31 : qv_unwritten_data <= {{(64 - 31) * 8{1'b0}}, wv_channel_dout[511 : 31 * 8]}; + 32 : qv_unwritten_data <= {{(64 - 32)* 8{1'b0}}, wv_channel_dout[511 : 32 * 8]}; + 33 : qv_unwritten_data <= {{(64 - 33)* 8{1'b0}}, wv_channel_dout[511 : 33 * 8]}; + 34 : qv_unwritten_data <= {{(64 - 34)* 8{1'b0}}, wv_channel_dout[511 : 34 * 8]}; + 35 : qv_unwritten_data <= {{(64 - 35)* 8{1'b0}}, wv_channel_dout[511 : 35 * 8]}; + 36 : qv_unwritten_data <= {{(64 - 36)* 8{1'b0}}, wv_channel_dout[511 : 36 * 8]}; + 37 : qv_unwritten_data <= {{(64 - 37)* 8{1'b0}}, wv_channel_dout[511 : 37 * 8]}; + 38 : qv_unwritten_data <= {{(64 - 38)* 8{1'b0}}, wv_channel_dout[511 : 38 * 8]}; + 39 : qv_unwritten_data <= {{(64 - 39)* 8{1'b0}}, wv_channel_dout[511 : 39 * 8]}; + 40 : qv_unwritten_data <= {{(64 - 40)* 8{1'b0}}, wv_channel_dout[511 : 40 * 8]}; + 41 : qv_unwritten_data <= {{(64 - 41)* 8{1'b0}}, wv_channel_dout[511 : 41 * 8]}; + 42 : qv_unwritten_data <= {{(64 - 42)* 8{1'b0}}, wv_channel_dout[511 : 42 * 8]}; + 43 : qv_unwritten_data <= {{(64 - 43)* 8{1'b0}}, wv_channel_dout[511 : 43 * 8]}; + 44 : qv_unwritten_data <= {{(64 - 44)* 8{1'b0}}, wv_channel_dout[511 : 44 * 8]}; + 45 : qv_unwritten_data <= {{(64 - 45)* 8{1'b0}}, wv_channel_dout[511 : 45 * 8]}; + 46 : qv_unwritten_data <= {{(64 - 46)* 8{1'b0}}, wv_channel_dout[511 : 46 * 8]}; + 47 : qv_unwritten_data <= {{(64 - 47)* 8{1'b0}}, wv_channel_dout[511 : 47 * 8]}; + 48 : qv_unwritten_data <= {{(64 - 48)* 8{1'b0}}, wv_channel_dout[511 : 48 * 8]}; + 49 : qv_unwritten_data <= {{(64 - 49)* 8{1'b0}}, wv_channel_dout[511 : 49 * 8]}; + 50 : qv_unwritten_data <= {{(64 - 50)* 8{1'b0}}, wv_channel_dout[511 : 50 * 8]}; + 51 : qv_unwritten_data <= {{(64 - 51)* 8{1'b0}}, wv_channel_dout[511 : 51 * 8]}; + 52 : qv_unwritten_data <= {{(64 - 52)* 8{1'b0}}, wv_channel_dout[511 : 52 * 8]}; + 53 : qv_unwritten_data <= {{(64 - 53)* 8{1'b0}}, wv_channel_dout[511 : 53 * 8]}; + 54 : qv_unwritten_data <= {{(64 - 54)* 8{1'b0}}, wv_channel_dout[511 : 54 * 8]}; + 55 : qv_unwritten_data <= {{(64 - 55)* 8{1'b0}}, wv_channel_dout[511 : 55 * 8]}; + 56 : qv_unwritten_data <= {{(64 - 56)* 8{1'b0}}, wv_channel_dout[511 : 56 * 8]}; + 57 : qv_unwritten_data <= {{(64 - 57)* 8{1'b0}}, wv_channel_dout[511 : 57 * 8]}; + 58 : qv_unwritten_data <= {{(64 - 58)* 8{1'b0}}, wv_channel_dout[511 : 58 * 8]}; + 59 : qv_unwritten_data <= {{(64 - 59)* 8{1'b0}}, wv_channel_dout[511 : 59 * 8]}; + 60 : qv_unwritten_data <= {{(64 - 60)* 8{1'b0}}, wv_channel_dout[511 : 60 * 8]}; + 61 : qv_unwritten_data <= {{(64 - 61)* 8{1'b0}}, wv_channel_dout[511 : 61 * 8]}; + 62 : qv_unwritten_data <= {{(64 - 62) * 8{1'b0}}, wv_channel_dout[511 : 62 * 8]}; + 63 : qv_unwritten_data <= {{(64 - 63) * 8{1'b0}}, wv_channel_dout[511 : 63 * 8]}; + default: qv_unwritten_data <= qv_unwritten_data; + endcase + end + end + else begin + qv_unwritten_data <= qv_unwritten_data; + end + end + else begin + qv_unwritten_data <= qv_unwritten_data; + end +end + +//-- q_dma_wr_req_valid -- +always @(*) begin + if(rst) begin + q_dma_wr_req_valid = 'd0; + end + else if(req_cur_state == REQ_UPLOAD_s) begin + if(qv_page_length_left > 0 && !w_channel_empty) begin + q_dma_wr_req_valid = 'd1; + end + else if(qv_page_length_left == 0) begin + q_dma_wr_req_valid = 'd1; + end + else begin + q_dma_wr_req_valid = 'd0; + end + end + else begin + q_dma_wr_req_valid = 'd0; + end +end + +//-- dma_wr_req_data -- +always @(*) begin + if(rst) begin + qv_dma_wr_req_data = 'd0; + end + else if(req_cur_state == REQ_UPLOAD_s) begin + if(qv_page_length_left > 0 && !w_channel_empty) begin + if((qv_page_length_left >= 64) || (qv_page_length_left + qv_unwritten_len >= 64)) begin + case(qv_unwritten_len) + 0 : qv_dma_wr_req_data = wv_channel_dout; + 1 : qv_dma_wr_req_data = {wv_channel_dout[(64 - 1 ) * 8 - 1 : 0], qv_unwritten_data[1 * 8 - 1 : 0]}; + 2 : qv_dma_wr_req_data = {wv_channel_dout[(64 - 2 ) * 8 - 1 : 0], qv_unwritten_data[2 * 8 - 1 : 0]}; + 3 : qv_dma_wr_req_data = {wv_channel_dout[(64 - 3 ) * 8 - 1 : 0], qv_unwritten_data[3 * 8 - 1 : 0]}; + 4 : qv_dma_wr_req_data = {wv_channel_dout[(64 - 4 ) * 8 - 1 : 0], qv_unwritten_data[4 * 8 - 1 : 0]}; + 5 : qv_dma_wr_req_data = {wv_channel_dout[(64 - 5 ) * 8 - 1 : 0], qv_unwritten_data[5 * 8 - 1 : 0]}; + 6 : qv_dma_wr_req_data = {wv_channel_dout[(64 - 6 ) * 8 - 1 : 0], qv_unwritten_data[6 * 8 - 1 : 0]}; + 7 : qv_dma_wr_req_data = {wv_channel_dout[(64 - 7 ) * 8 - 1 : 0], qv_unwritten_data[7 * 8 - 1 : 0]}; + 8 : qv_dma_wr_req_data = {wv_channel_dout[(64 - 8 ) * 8 - 1 : 0], qv_unwritten_data[8 * 8 - 1 : 0]}; + 9 : qv_dma_wr_req_data = {wv_channel_dout[(64 - 9 ) * 8 - 1 : 0], qv_unwritten_data[9 * 8 - 1 : 0]}; + 10 : qv_dma_wr_req_data = {wv_channel_dout[(64 - 10) * 8 - 1 : 0], qv_unwritten_data[10 * 8 - 1 : 0]}; + 11 : qv_dma_wr_req_data = {wv_channel_dout[(64 - 11) * 8 - 1 : 0], qv_unwritten_data[11 * 8 - 1 : 0]}; + 12 : qv_dma_wr_req_data = {wv_channel_dout[(64 - 12) * 8 - 1 : 0], qv_unwritten_data[12 * 8 - 1 : 0]}; + 13 : qv_dma_wr_req_data = {wv_channel_dout[(64 - 13) * 8 - 1 : 0], qv_unwritten_data[13 * 8 - 1 : 0]}; + 14 : qv_dma_wr_req_data = {wv_channel_dout[(64 - 14) * 8 - 1 : 0], qv_unwritten_data[14 * 8 - 1 : 0]}; + 15 : qv_dma_wr_req_data = {wv_channel_dout[(64 - 15) * 8 - 1 : 0], qv_unwritten_data[15 * 8 - 1 : 0]}; + 16 : qv_dma_wr_req_data = {wv_channel_dout[(64 - 16) * 8 - 1 : 0], qv_unwritten_data[16 * 8 - 1 : 0]}; + 17 : qv_dma_wr_req_data = {wv_channel_dout[(64 - 17) * 8 - 1 : 0], qv_unwritten_data[17 * 8 - 1 : 0]}; + 18 : qv_dma_wr_req_data = {wv_channel_dout[(64 - 18) * 8 - 1 : 0], qv_unwritten_data[18 * 8 - 1 : 0]}; + 19 : qv_dma_wr_req_data = {wv_channel_dout[(64 - 19) * 8 - 1 : 0], qv_unwritten_data[19 * 8 - 1 : 0]}; + 20 : qv_dma_wr_req_data = {wv_channel_dout[(64 - 20) * 8 - 1 : 0], qv_unwritten_data[20 * 8 - 1 : 0]}; + 21 : qv_dma_wr_req_data = {wv_channel_dout[(64 - 21) * 8 - 1 : 0], qv_unwritten_data[21 * 8 - 1 : 0]}; + 22 : qv_dma_wr_req_data = {wv_channel_dout[(64 - 22) * 8 - 1 : 0], qv_unwritten_data[22 * 8 - 1 : 0]}; + 23 : qv_dma_wr_req_data = {wv_channel_dout[(64 - 23) * 8 - 1 : 0], qv_unwritten_data[23 * 8 - 1 : 0]}; + 24 : qv_dma_wr_req_data = {wv_channel_dout[(64 - 24) * 8 - 1 : 0], qv_unwritten_data[24 * 8 - 1 : 0]}; + 25 : qv_dma_wr_req_data = {wv_channel_dout[(64 - 25) * 8 - 1 : 0], qv_unwritten_data[25 * 8 - 1 : 0]}; + 26 : qv_dma_wr_req_data = {wv_channel_dout[(64 - 26) * 8 - 1 : 0], qv_unwritten_data[26 * 8 - 1 : 0]}; + 27 : qv_dma_wr_req_data = {wv_channel_dout[(64 - 27) * 8 - 1 : 0], qv_unwritten_data[27 * 8 - 1 : 0]}; + 28 : qv_dma_wr_req_data = {wv_channel_dout[(64 - 28) * 8 - 1 : 0], qv_unwritten_data[28 * 8 - 1 : 0]}; + 29 : qv_dma_wr_req_data = {wv_channel_dout[(64 - 29) * 8 - 1 : 0], qv_unwritten_data[29 * 8 - 1 : 0]}; + 30 : qv_dma_wr_req_data = {wv_channel_dout[(64 - 30) * 8 - 1 : 0], qv_unwritten_data[30 * 8 - 1 : 0]}; + 31 : qv_dma_wr_req_data = {wv_channel_dout[(64 - 31) * 8 - 1 : 0], qv_unwritten_data[31 * 8 - 1 : 0]}; + 32 : qv_dma_wr_req_data = {wv_channel_dout[(64 - 32) * 8 - 1 : 0], qv_unwritten_data[32 * 8 - 1 : 0]}; + 33 : qv_dma_wr_req_data = {wv_channel_dout[(64 - 33) * 8 - 1 : 0], qv_unwritten_data[33 * 8 - 1 : 0]}; + 34 : qv_dma_wr_req_data = {wv_channel_dout[(64 - 34) * 8 - 1 : 0], qv_unwritten_data[34 * 8 - 1 : 0]}; + 35 : qv_dma_wr_req_data = {wv_channel_dout[(64 - 35) * 8 - 1 : 0], qv_unwritten_data[35 * 8 - 1 : 0]}; + 36 : qv_dma_wr_req_data = {wv_channel_dout[(64 - 36) * 8 - 1 : 0], qv_unwritten_data[36 * 8 - 1 : 0]}; + 37 : qv_dma_wr_req_data = {wv_channel_dout[(64 - 37) * 8 - 1 : 0], qv_unwritten_data[37 * 8 - 1 : 0]}; + 38 : qv_dma_wr_req_data = {wv_channel_dout[(64 - 38) * 8 - 1 : 0], qv_unwritten_data[38 * 8 - 1 : 0]}; + 39 : qv_dma_wr_req_data = {wv_channel_dout[(64 - 39) * 8 - 1 : 0], qv_unwritten_data[39 * 8 - 1 : 0]}; + 40 : qv_dma_wr_req_data = {wv_channel_dout[(64 - 40) * 8 - 1 : 0], qv_unwritten_data[40 * 8 - 1 : 0]}; + 41 : qv_dma_wr_req_data = {wv_channel_dout[(64 - 41) * 8 - 1 : 0], qv_unwritten_data[41 * 8 - 1 : 0]}; + 42 : qv_dma_wr_req_data = {wv_channel_dout[(64 - 42) * 8 - 1 : 0], qv_unwritten_data[42 * 8 - 1 : 0]}; + 43 : qv_dma_wr_req_data = {wv_channel_dout[(64 - 43) * 8 - 1 : 0], qv_unwritten_data[43 * 8 - 1 : 0]}; + 44 : qv_dma_wr_req_data = {wv_channel_dout[(64 - 44) * 8 - 1 : 0], qv_unwritten_data[44 * 8 - 1 : 0]}; + 45 : qv_dma_wr_req_data = {wv_channel_dout[(64 - 45) * 8 - 1 : 0], qv_unwritten_data[45 * 8 - 1 : 0]}; + 46 : qv_dma_wr_req_data = {wv_channel_dout[(64 - 46) * 8 - 1 : 0], qv_unwritten_data[46 * 8 - 1 : 0]}; + 47 : qv_dma_wr_req_data = {wv_channel_dout[(64 - 47) * 8 - 1 : 0], qv_unwritten_data[47 * 8 - 1 : 0]}; + 48 : qv_dma_wr_req_data = {wv_channel_dout[(64 - 48) * 8 - 1 : 0], qv_unwritten_data[48 * 8 - 1 : 0]}; + 49 : qv_dma_wr_req_data = {wv_channel_dout[(64 - 49) * 8 - 1 : 0], qv_unwritten_data[49 * 8 - 1 : 0]}; + 50 : qv_dma_wr_req_data = {wv_channel_dout[(64 - 50) * 8 - 1 : 0], qv_unwritten_data[50 * 8 - 1 : 0]}; + 51 : qv_dma_wr_req_data = {wv_channel_dout[(64 - 51) * 8 - 1 : 0], qv_unwritten_data[51 * 8 - 1 : 0]}; + 52 : qv_dma_wr_req_data = {wv_channel_dout[(64 - 52) * 8 - 1 : 0], qv_unwritten_data[52 * 8 - 1 : 0]}; + 53 : qv_dma_wr_req_data = {wv_channel_dout[(64 - 53) * 8 - 1 : 0], qv_unwritten_data[53 * 8 - 1 : 0]}; + 54 : qv_dma_wr_req_data = {wv_channel_dout[(64 - 54) * 8 - 1 : 0], qv_unwritten_data[54 * 8 - 1 : 0]}; + 55 : qv_dma_wr_req_data = {wv_channel_dout[(64 - 55) * 8 - 1 : 0], qv_unwritten_data[55 * 8 - 1 : 0]}; + 56 : qv_dma_wr_req_data = {wv_channel_dout[(64 - 56) * 8 - 1 : 0], qv_unwritten_data[56 * 8 - 1 : 0]}; + 57 : qv_dma_wr_req_data = {wv_channel_dout[(64 - 57) * 8 - 1 : 0], qv_unwritten_data[57 * 8 - 1 : 0]}; + 58 : qv_dma_wr_req_data = {wv_channel_dout[(64 - 58) * 8 - 1 : 0], qv_unwritten_data[58 * 8 - 1 : 0]}; + 59 : qv_dma_wr_req_data = {wv_channel_dout[(64 - 59) * 8 - 1 : 0], qv_unwritten_data[59 * 8 - 1 : 0]}; + 60 : qv_dma_wr_req_data = {wv_channel_dout[(64 - 60) * 8 - 1 : 0], qv_unwritten_data[60 * 8 - 1 : 0]}; + 61 : qv_dma_wr_req_data = {wv_channel_dout[(64 - 61) * 8 - 1 : 0], qv_unwritten_data[61 * 8 - 1 : 0]}; + 62 : qv_dma_wr_req_data = {wv_channel_dout[(64 - 62) * 8 - 1 : 0], qv_unwritten_data[62 * 8 - 1 : 0]}; + 63 : qv_dma_wr_req_data = {wv_channel_dout[(64 - 63) * 8 - 1 : 0], qv_unwritten_data[63 * 8 - 1 : 0]}; + default: qv_dma_wr_req_data = qv_dma_wr_req_data_diff; + endcase + end + else if(qv_page_length_left + qv_unwritten_len < 64) begin + case(qv_unwritten_len) + 0 : qv_dma_wr_req_data = wv_channel_dout; + 1 : qv_dma_wr_req_data = {wv_channel_dout[(64 - 1 ) * 8 - 1 : 0], qv_unwritten_data[1 * 8 - 1 : 0]}; + 2 : qv_dma_wr_req_data = {wv_channel_dout[(64 - 2 ) * 8 - 1 : 0], qv_unwritten_data[2 * 8 - 1 : 0]}; + 3 : qv_dma_wr_req_data = {wv_channel_dout[(64 - 3 ) * 8 - 1 : 0], qv_unwritten_data[3 * 8 - 1 : 0]}; + 4 : qv_dma_wr_req_data = {wv_channel_dout[(64 - 4 ) * 8 - 1 : 0], qv_unwritten_data[4 * 8 - 1 : 0]}; + 5 : qv_dma_wr_req_data = {wv_channel_dout[(64 - 5 ) * 8 - 1 : 0], qv_unwritten_data[5 * 8 - 1 : 0]}; + 6 : qv_dma_wr_req_data = {wv_channel_dout[(64 - 6 ) * 8 - 1 : 0], qv_unwritten_data[6 * 8 - 1 : 0]}; + 7 : qv_dma_wr_req_data = {wv_channel_dout[(64 - 7 ) * 8 - 1 : 0], qv_unwritten_data[7 * 8 - 1 : 0]}; + 8 : qv_dma_wr_req_data = {wv_channel_dout[(64 - 8 ) * 8 - 1 : 0], qv_unwritten_data[8 * 8 - 1 : 0]}; + 9 : qv_dma_wr_req_data = {wv_channel_dout[(64 - 9 ) * 8 - 1 : 0], qv_unwritten_data[9 * 8 - 1 : 0]}; + 10 : qv_dma_wr_req_data = {wv_channel_dout[(64 - 10) * 8 - 1 : 0], qv_unwritten_data[10 * 8 - 1 : 0]}; + 11 : qv_dma_wr_req_data = {wv_channel_dout[(64 - 11) * 8 - 1 : 0], qv_unwritten_data[11 * 8 - 1 : 0]}; + 12 : qv_dma_wr_req_data = {wv_channel_dout[(64 - 12) * 8 - 1 : 0], qv_unwritten_data[12 * 8 - 1 : 0]}; + 13 : qv_dma_wr_req_data = {wv_channel_dout[(64 - 13) * 8 - 1 : 0], qv_unwritten_data[13 * 8 - 1 : 0]}; + 14 : qv_dma_wr_req_data = {wv_channel_dout[(64 - 14) * 8 - 1 : 0], qv_unwritten_data[14 * 8 - 1 : 0]}; + 15 : qv_dma_wr_req_data = {wv_channel_dout[(64 - 15) * 8 - 1 : 0], qv_unwritten_data[15 * 8 - 1 : 0]}; + 16 : qv_dma_wr_req_data = {wv_channel_dout[(64 - 16) * 8 - 1 : 0], qv_unwritten_data[16 * 8 - 1 : 0]}; + 17 : qv_dma_wr_req_data = {wv_channel_dout[(64 - 17) * 8 - 1 : 0], qv_unwritten_data[17 * 8 - 1 : 0]}; + 18 : qv_dma_wr_req_data = {wv_channel_dout[(64 - 18) * 8 - 1 : 0], qv_unwritten_data[18 * 8 - 1 : 0]}; + 19 : qv_dma_wr_req_data = {wv_channel_dout[(64 - 19) * 8 - 1 : 0], qv_unwritten_data[19 * 8 - 1 : 0]}; + 20 : qv_dma_wr_req_data = {wv_channel_dout[(64 - 20) * 8 - 1 : 0], qv_unwritten_data[20 * 8 - 1 : 0]}; + 21 : qv_dma_wr_req_data = {wv_channel_dout[(64 - 21) * 8 - 1 : 0], qv_unwritten_data[21 * 8 - 1 : 0]}; + 22 : qv_dma_wr_req_data = {wv_channel_dout[(64 - 22) * 8 - 1 : 0], qv_unwritten_data[22 * 8 - 1 : 0]}; + 23 : qv_dma_wr_req_data = {wv_channel_dout[(64 - 23) * 8 - 1 : 0], qv_unwritten_data[23 * 8 - 1 : 0]}; + 24 : qv_dma_wr_req_data = {wv_channel_dout[(64 - 24) * 8 - 1 : 0], qv_unwritten_data[24 * 8 - 1 : 0]}; + 25 : qv_dma_wr_req_data = {wv_channel_dout[(64 - 25) * 8 - 1 : 0], qv_unwritten_data[25 * 8 - 1 : 0]}; + 26 : qv_dma_wr_req_data = {wv_channel_dout[(64 - 26) * 8 - 1 : 0], qv_unwritten_data[26 * 8 - 1 : 0]}; + 27 : qv_dma_wr_req_data = {wv_channel_dout[(64 - 27) * 8 - 1 : 0], qv_unwritten_data[27 * 8 - 1 : 0]}; + 28 : qv_dma_wr_req_data = {wv_channel_dout[(64 - 28) * 8 - 1 : 0], qv_unwritten_data[28 * 8 - 1 : 0]}; + 29 : qv_dma_wr_req_data = {wv_channel_dout[(64 - 29) * 8 - 1 : 0], qv_unwritten_data[29 * 8 - 1 : 0]}; + 30 : qv_dma_wr_req_data = {wv_channel_dout[(64 - 30) * 8 - 1 : 0], qv_unwritten_data[30 * 8 - 1 : 0]}; + 31 : qv_dma_wr_req_data = {wv_channel_dout[(64 - 31) * 8 - 1 : 0], qv_unwritten_data[31 * 8 - 1 : 0]}; + 32 : qv_dma_wr_req_data = {wv_channel_dout[(64 - 32) * 8 - 1 : 0], qv_unwritten_data[32 * 8 - 1 : 0]}; + 33 : qv_dma_wr_req_data = {wv_channel_dout[(64 - 33) * 8 - 1 : 0], qv_unwritten_data[33 * 8 - 1 : 0]}; + 34 : qv_dma_wr_req_data = {wv_channel_dout[(64 - 34) * 8 - 1 : 0], qv_unwritten_data[34 * 8 - 1 : 0]}; + 35 : qv_dma_wr_req_data = {wv_channel_dout[(64 - 35) * 8 - 1 : 0], qv_unwritten_data[35 * 8 - 1 : 0]}; + 36 : qv_dma_wr_req_data = {wv_channel_dout[(64 - 36) * 8 - 1 : 0], qv_unwritten_data[36 * 8 - 1 : 0]}; + 37 : qv_dma_wr_req_data = {wv_channel_dout[(64 - 37) * 8 - 1 : 0], qv_unwritten_data[37 * 8 - 1 : 0]}; + 38 : qv_dma_wr_req_data = {wv_channel_dout[(64 - 38) * 8 - 1 : 0], qv_unwritten_data[38 * 8 - 1 : 0]}; + 39 : qv_dma_wr_req_data = {wv_channel_dout[(64 - 39) * 8 - 1 : 0], qv_unwritten_data[39 * 8 - 1 : 0]}; + 40 : qv_dma_wr_req_data = {wv_channel_dout[(64 - 40) * 8 - 1 : 0], qv_unwritten_data[40 * 8 - 1 : 0]}; + 41 : qv_dma_wr_req_data = {wv_channel_dout[(64 - 41) * 8 - 1 : 0], qv_unwritten_data[41 * 8 - 1 : 0]}; + 42 : qv_dma_wr_req_data = {wv_channel_dout[(64 - 42) * 8 - 1 : 0], qv_unwritten_data[42 * 8 - 1 : 0]}; + 43 : qv_dma_wr_req_data = {wv_channel_dout[(64 - 43) * 8 - 1 : 0], qv_unwritten_data[43 * 8 - 1 : 0]}; + 44 : qv_dma_wr_req_data = {wv_channel_dout[(64 - 44) * 8 - 1 : 0], qv_unwritten_data[44 * 8 - 1 : 0]}; + 45 : qv_dma_wr_req_data = {wv_channel_dout[(64 - 45) * 8 - 1 : 0], qv_unwritten_data[45 * 8 - 1 : 0]}; + 46 : qv_dma_wr_req_data = {wv_channel_dout[(64 - 46) * 8 - 1 : 0], qv_unwritten_data[46 * 8 - 1 : 0]}; + 47 : qv_dma_wr_req_data = {wv_channel_dout[(64 - 47) * 8 - 1 : 0], qv_unwritten_data[47 * 8 - 1 : 0]}; + 48 : qv_dma_wr_req_data = {wv_channel_dout[(64 - 48) * 8 - 1 : 0], qv_unwritten_data[48 * 8 - 1 : 0]}; + 49 : qv_dma_wr_req_data = {wv_channel_dout[(64 - 49) * 8 - 1 : 0], qv_unwritten_data[49 * 8 - 1 : 0]}; + 50 : qv_dma_wr_req_data = {wv_channel_dout[(64 - 50) * 8 - 1 : 0], qv_unwritten_data[50 * 8 - 1 : 0]}; + 51 : qv_dma_wr_req_data = {wv_channel_dout[(64 - 51) * 8 - 1 : 0], qv_unwritten_data[51 * 8 - 1 : 0]}; + 52 : qv_dma_wr_req_data = {wv_channel_dout[(64 - 52) * 8 - 1 : 0], qv_unwritten_data[52 * 8 - 1 : 0]}; + 53 : qv_dma_wr_req_data = {wv_channel_dout[(64 - 53) * 8 - 1 : 0], qv_unwritten_data[53 * 8 - 1 : 0]}; + 54 : qv_dma_wr_req_data = {wv_channel_dout[(64 - 54) * 8 - 1 : 0], qv_unwritten_data[54 * 8 - 1 : 0]}; + 55 : qv_dma_wr_req_data = {wv_channel_dout[(64 - 55) * 8 - 1 : 0], qv_unwritten_data[55 * 8 - 1 : 0]}; + 56 : qv_dma_wr_req_data = {wv_channel_dout[(64 - 56) * 8 - 1 : 0], qv_unwritten_data[56 * 8 - 1 : 0]}; + 57 : qv_dma_wr_req_data = {wv_channel_dout[(64 - 57) * 8 - 1 : 0], qv_unwritten_data[57 * 8 - 1 : 0]}; + 58 : qv_dma_wr_req_data = {wv_channel_dout[(64 - 58) * 8 - 1 : 0], qv_unwritten_data[58 * 8 - 1 : 0]}; + 59 : qv_dma_wr_req_data = {wv_channel_dout[(64 - 59) * 8 - 1 : 0], qv_unwritten_data[59 * 8 - 1 : 0]}; + 60 : qv_dma_wr_req_data = {wv_channel_dout[(64 - 60) * 8 - 1 : 0], qv_unwritten_data[60 * 8 - 1 : 0]}; + 61 : qv_dma_wr_req_data = {wv_channel_dout[(64 - 61) * 8 - 1 : 0], qv_unwritten_data[61 * 8 - 1 : 0]}; + 62 : qv_dma_wr_req_data = {wv_channel_dout[(64 - 62) * 8 - 1 : 0], qv_unwritten_data[62 * 8 - 1 : 0]}; + 63 : qv_dma_wr_req_data = {wv_channel_dout[(64 - 63) * 8 - 1 : 0], qv_unwritten_data[63 * 8 - 1 : 0]}; + default: qv_dma_wr_req_data = qv_dma_wr_req_data_diff; + endcase + end + else begin + qv_dma_wr_req_data = qv_dma_wr_req_data_diff; + end + end + else if(qv_page_length_left == 0) begin + qv_dma_wr_req_data = qv_unwritten_data; + end + else begin + qv_dma_wr_req_data = qv_dma_wr_req_data_diff; + end + end + else begin + qv_dma_wr_req_data = qv_dma_wr_req_data_diff; + end +end + +//-- dma_wr_req_head -- +always @(*) begin + if(rst) begin + qv_dma_wr_req_head = 'd0; + end + else if(req_pre_state == REQ_IDLE_s && req_cur_state == REQ_UPLOAD_s) begin + qv_dma_wr_req_head = {scatter_req_dout[63:0], scatter_req_dout[95:64]}; + end + else begin + qv_dma_wr_req_head = qv_dma_wr_req_head_diff; + end +end + +//-- q_dma_wr_req_last -- +always @(*) begin + if(rst) begin + q_dma_wr_req_last = 'd0; + end + else if(req_cur_state == REQ_UPLOAD_s) begin + if(qv_page_length_left + qv_unwritten_len <= 64) begin + if(qv_page_length_left > 0 && !w_channel_empty) begin + q_dma_wr_req_last = 'd1; + end + else if(qv_page_length_left == 0) begin + q_dma_wr_req_last = 'd1; + end + else begin + q_dma_wr_req_last = 'd0; + end + end + else begin + q_dma_wr_req_last = 'd0; + end + end + else begin + q_dma_wr_req_last = 'd0; + end +end + +//-- q_channel_rd_en -- +always @(*) begin + if(rst) begin + q_channel_rd_en = 'd0; + end + else if(req_cur_state == REQ_UPLOAD_s) begin + if(qv_page_length_left > 0 && !w_channel_empty && dma_wr_req_ready) begin + q_channel_rd_en = 'd1; + end + else begin + q_channel_rd_en = 'd0; + end + end + else begin + q_channel_rd_en = 'd0; + end +end + +/*------------------------------------------- Variables Decode : End ------------------------------------------------*/ + +endmodule diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Peripherals/TXArbiter.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Peripherals/TXArbiter.v new file mode 100644 index 0000000000000000000000000000000000000000..43278c6f48e7dd015719f69cf182fc776359abe0 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Peripherals/TXArbiter.v @@ -0,0 +1,55 @@ +/*------------------------------------------- Module Description : Begin ---------------------------------------------- +Name: TXArbiter +Author: YangFan +Function: 1.Arbitrate TX packet. +--------------------------------------------- Module Decription : End -----------------------------------------------*/ + +/*------------------------------------------- Timescale Definition : Begin ------------------------------------------*/ +`timescale 1ns / 1ps +/*------------------------------------------- Timescale Definition : End --------------------------------------------*/ + +/*------------------------------------------- Included Files : Begin ------------------------------------------------*/ +`include "protocol_engine_def.vh" +/*------------------------------------------- Included Files : End --------------------------------------------------*/ + +/*------------------------------------------- Input/Output Definition : Begin ---------------------------------------*/ +module TXArbiter +( + input wire clk, + input wire rst, + + input wire chnl_0_pkt_valid, + input wire [`PKT_META_BUS_WIDTH - 1 : 0] chnl_0_pkt_head, + output wire chnl_0_pkt_ready, + + input wire chnl_1_pkt_valid, + input wire [`PKT_META_BUS_WIDTH - 1 : 0] chnl_1_pkt_head, + output wire chnl_1_pkt_ready, + + output wire egress_pkt_valid, + output wire [`PKT_META_BUS_WIDTH - 1 : 0] egress_pkt_head, + input wire egress_pkt_ready +); + +/*------------------------------------------- Input/Output Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Macros Definition : Begin ---------------------------------------*/ +/*------------------------------------------- Local Macros Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Variables Definition : Begin ------------------------------------*/ +/*------------------------------------------- Local Variables Definition : End --------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : Begin ---------------------------------------*/ +/*------------------------------------------- Submodules Instatiation : End -----------------------------------------*/ + +/*------------------------------------------- State Machine Definition : Begin --------------------------------------*/ +/*------------------------------------------- State Machine Definition : End ----------------------------------------*/ + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ +/*------------------------------------------- Variables Decode : End ----------------------------------------------*/ + +/*------------------------------------------- Local Macros Undef : Begin --------------------------------------------*/ + +/*------------------------------------------- Local Macros Undef : End ----------------------------------------------*/ + +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/QueueSubsystem/CQMgt/CQMgt.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/QueueSubsystem/CQMgt/CQMgt.v new file mode 100644 index 0000000000000000000000000000000000000000..755393ad12bdb8aac4025c950be670c81ced3382 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/QueueSubsystem/CQMgt/CQMgt.v @@ -0,0 +1,277 @@ +/*------------------------------------------- Module Description : Begin ---------------------------------------------- +Name: CQMgt +Author: YangFan +Function: 1.Manage CQ. +--------------------------------------------- Module Decription : End -----------------------------------------------*/ + +/*------------------------------------------- Timescale Definition : Begin ------------------------------------------*/ +`timescale 1ns / 1ps +/*------------------------------------------- Timescale Definition : End --------------------------------------------*/ + +/*------------------------------------------- Included Files : Begin ------------------------------------------------*/ +`include "protocol_engine_def.vh" +/*------------------------------------------- Included Files : End --------------------------------------------------*/ + +/*------------------------------------------- Input/Output Definition : Begin ---------------------------------------*/ +module CQMgt +( + input wire clk, + input wire rst, + +//Interface with ReqTransCore + input wire TX_REQ_cq_req_valid, + input wire [`CQ_REQ_HEAD_WIDTH - 1 : 0] TX_REQ_cq_req_head, + output wire TX_REQ_cq_req_ready, + + output wire TX_REQ_cq_resp_valid, + output wire [`CQ_RESP_HEAD_WIDTH - 1 : 0] TX_REQ_cq_resp_head, + input wire TX_REQ_cq_resp_ready, + +//Interface with ReqRecvCore + input wire RX_REQ_cq_req_valid, + input wire [`CQ_REQ_HEAD_WIDTH - 1 : 0] RX_REQ_cq_req_head, + output wire RX_REQ_cq_req_ready, + + output wire RX_REQ_cq_resp_valid, + output wire [`CQ_RESP_HEAD_WIDTH - 1 : 0] RX_REQ_cq_resp_head, + input wire RX_REQ_cq_resp_ready, + +//Interface with RespRecvCore + input wire RX_RESP_cq_req_valid, + input wire [`CQ_REQ_HEAD_WIDTH - 1 : 0] RX_RESP_cq_req_head, + output wire RX_RESP_cq_req_ready, + + output wire RX_RESP_cq_resp_valid, + output wire [`CQ_RESP_HEAD_WIDTH - 1 : 0] RX_RESP_cq_resp_head, + input wire RX_RESP_cq_resp_ready +); + +/*------------------------------------------- Input/Output Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Macros Definition : Begin ---------------------------------------*/ +`define CQN_OFFSET 23:0 +`define CQ_LENGTH_OFFSET 63:32 + +`define CHNL_TX_REQ 0 +`define CHNL_RX_REQ 1 +`define CHNL_RX_RESP 2 +/*------------------------------------------- Local Macros Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Variables Definition : Begin ------------------------------------*/ +wire [0:0] cq_offset_record_wea; +wire [`CQ_NUM_LOG - 1 : 0] cq_offset_record_addra; +wire [23:0] cq_offset_record_dina; + +wire [`CQ_NUM_LOG - 1 : 0] cq_offset_record_addrb; +wire [23:0] cq_offset_record_doutb; + +reg [2:0] last_sch; + +reg [`CQ_NUM_LOG - 1 : 0] cqn; +reg [31:0] cq_length; +/*------------------------------------------- Local Variables Definition : End --------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : Begin ---------------------------------------*/ +SRAM_SDP_Template #( + .RAM_WIDTH ( 24 ), + .RAM_DEPTH ( `CQ_NUM ) +) +CQOffsetRecordTable +( + .clk ( clk ), + .rst ( rst ), + + .wea ( cq_offset_record_wea ), + .addra ( cq_offset_record_addra ), + .dina ( cq_offset_record_dina ), + + .addrb ( cq_offset_record_addrb ), + .doutb ( cq_offset_record_doutb ) +); +/*------------------------------------------- Submodules Instatiation : End -----------------------------------------*/ + +/*------------------------------------------- State Machine Definition : Begin --------------------------------------*/ +reg [2:0] cur_state; +reg [2:0] next_state; + +parameter IDLE_s = 3'd1, + TX_REQ_s = 3'd2, + RX_REQ_s = 3'd3, + RX_RESP_s = 3'd4; + +always @(posedge clk or posedge rst) begin + if (rst) begin + cur_state <= IDLE_s; + end + else begin + cur_state <= next_state; + end +end + +always @(*) begin + case(cur_state) + IDLE_s: if(last_sch == `CHNL_TX_REQ) begin + if(RX_REQ_cq_req_valid) begin + next_state = RX_REQ_s; + end + else if(RX_RESP_cq_req_valid) begin + next_state = RX_RESP_s; + end + else if(TX_REQ_cq_req_valid) begin + next_state = TX_REQ_s; + end + else begin + next_state = IDLE_s; + end + end + else if(last_sch == `CHNL_RX_REQ) begin + if(RX_RESP_cq_req_valid) begin + next_state = RX_RESP_s; + end + else if(TX_REQ_cq_req_valid) begin + next_state = TX_REQ_s; + end + else if(RX_REQ_cq_req_valid) begin + next_state = RX_REQ_s; + end + else begin + next_state = IDLE_s; + end + end + else if(last_sch == `CHNL_RX_RESP) begin + if(TX_REQ_cq_req_valid) begin + next_state = TX_REQ_s; + end + else if(RX_REQ_cq_req_valid) begin + next_state = RX_REQ_s; + end + else if(RX_RESP_cq_req_valid) begin + next_state = RX_RESP_s; + end + else begin + next_state = IDLE_s; + end + end + else begin + next_state = IDLE_s; + end + TX_REQ_s: if(TX_REQ_cq_resp_ready) begin + next_state = IDLE_s; + end + else begin + next_state = TX_REQ_s; + end + RX_REQ_s: if(RX_REQ_cq_resp_ready) begin + next_state = IDLE_s; + end + else begin + next_state = RX_REQ_s; + end + RX_RESP_s: if(RX_RESP_cq_resp_ready) begin + next_state = IDLE_s; + end + else begin + next_state = RX_RESP_s; + end + default: next_state = IDLE_s; + endcase +end +/*------------------------------------------- State Machine Definition : End ----------------------------------------*/ + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ +//-- cqn -- +//-- cq_length -- +always @(posedge clk or posedge rst) begin + if (rst) begin + cqn <= 'd0; + cq_length <= 'd0; + end + else if (cur_state == IDLE_s && next_state == TX_REQ_s) begin + cqn <= TX_REQ_cq_req_head[`CQN_OFFSET]; + cq_length <= TX_REQ_cq_req_head[`CQ_LENGTH_OFFSET]; + end + else if (cur_state == IDLE_s && next_state == RX_REQ_s) begin + cqn <= RX_REQ_cq_req_head[`CQN_OFFSET]; + cq_length <= RX_REQ_cq_req_head[`CQ_LENGTH_OFFSET]; + end + else if (cur_state == IDLE_s && next_state == RX_RESP_s) begin + cqn <= RX_RESP_cq_req_head[`CQN_OFFSET]; + cq_length <= RX_RESP_cq_req_head[`CQ_LENGTH_OFFSET]; + end + else begin + cqn <= cqn; + cq_length <= cq_length; + end +end + +//-- last_sch -- +always @(posedge clk or posedge rst) begin + if (rst) begin + last_sch <= 'd0; + end + else if (cur_state == TX_REQ_s && TX_REQ_cq_resp_ready) begin + last_sch <= `CHNL_TX_REQ; + end + else if (cur_state == RX_REQ_s && RX_REQ_cq_resp_ready) begin + last_sch <= `CHNL_RX_REQ; + end + else if (cur_state == RX_RESP_s && RX_RESP_cq_resp_ready) begin + last_sch <= `CHNL_RX_RESP; + end + else begin + last_sch <= last_sch; + end +end + +//-- cq_offset_record_wea -- +//-- cq_offset_record_addra -- +//-- cq_offset_record_dina -- +assign cq_offset_record_wea = (cur_state == TX_REQ_s && TX_REQ_cq_resp_ready) ? 'd1 : + (cur_state == RX_REQ_s && RX_REQ_cq_resp_ready) ? 'd1 : + (cur_state == RX_RESP_s && RX_RESP_cq_resp_ready) ? 'd1 : 'd0; +assign cq_offset_record_addra = (cur_state == TX_REQ_s && TX_REQ_cq_resp_ready) ? cqn : + (cur_state == RX_REQ_s && RX_REQ_cq_resp_ready) ? cqn : + (cur_state == RX_RESP_s && RX_RESP_cq_resp_ready) ? cqn : 'd0; +assign cq_offset_record_dina = (cur_state == TX_REQ_s && TX_REQ_cq_resp_ready)? (cq_offset_record_doutb + `CQE_LENGTH == cq_length ? 'd0 : cq_offset_record_doutb + `CQE_LENGTH) : + (cur_state == RX_REQ_s && RX_REQ_cq_resp_ready) ? (cq_offset_record_doutb + `CQE_LENGTH == cq_length ? 'd0 : cq_offset_record_doutb + `CQE_LENGTH) : + (cur_state == RX_RESP_s && RX_RESP_cq_resp_ready) ? (cq_offset_record_doutb + `CQE_LENGTH == cq_length ? 'd0 : cq_offset_record_doutb + `CQE_LENGTH) : 'd0; + +//-- cq_offset_record_addrb -- +assign cq_offset_record_addrb = (cur_state == IDLE_s && next_state == TX_REQ_s) ? TX_REQ_cq_req_head[`CQN_OFFSET] : + (cur_state == IDLE_s && next_state == RX_REQ_s) ? RX_REQ_cq_req_head[`CQN_OFFSET] : + (cur_state == IDLE_s && next_state == RX_RESP_s) ? RX_RESP_cq_req_head[`CQN_OFFSET] : cqn; + + +//-- TX_REQ_cq_req_ready -- +assign TX_REQ_cq_req_ready = (cur_state == TX_REQ_s) ? 'd1 : 'd0; + +wire [31:0] cqn_resp; +assign cqn_resp = {'d0, cqn}; + +//-- TX_REQ_cq_resp_valid -- +//-- TX_REQ_cq_resp_head -- +assign TX_REQ_cq_resp_valid = (cur_state == TX_REQ_s) ? 'd1 : 'd0; +assign TX_REQ_cq_resp_head = (cur_state == TX_REQ_s) ? {cq_offset_record_doutb, cqn_resp}: 'd0; + +//-- RX_REQ_cq_req_ready -- +assign RX_REQ_cq_req_ready = (cur_state == RX_REQ_s) ? 'd1 : 'd0; + +//-- RX_REQ_cq_resp_valid -- +//-- RX_REQ_cq_resp_head -- +assign RX_REQ_cq_resp_valid = (cur_state == RX_REQ_s) ? 'd1 : 'd0; +assign RX_REQ_cq_resp_head = (cur_state == RX_REQ_s) ? {cq_offset_record_doutb, cqn_resp}: 'd0; + +//-- RX_RESP_cq_req_ready -- +assign RX_RESP_cq_req_ready = (cur_state == RX_RESP_s) ? 'd1 : 'd0; + +//-- RX_RESP_cq_resp_valid -- +//-- RX_RESP_cq_resp_head -- +assign RX_RESP_cq_resp_valid = (cur_state == RX_RESP_s) ? 'd1 : 'd0; +assign RX_RESP_cq_resp_head = (cur_state == RX_RESP_s) ? {cq_offset_record_doutb, cqn_resp}: 'd0; +/*------------------------------------------- Variables Decode : End ----------------------------------------------*/ + +/*------------------------------------------- Local Macros Undef : Begin --------------------------------------------*/ + +/*------------------------------------------- Local Macros Undef : End ----------------------------------------------*/ + +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/QueueSubsystem/Common/BitWidthTrans_512To128.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/QueueSubsystem/Common/BitWidthTrans_512To128.v new file mode 100644 index 0000000000000000000000000000000000000000..be5b0f29411bfc8388f984a56d65f18d5e3b763d --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/QueueSubsystem/Common/BitWidthTrans_512To128.v @@ -0,0 +1,159 @@ +/*------------------------------------------- Module Description : Begin ---------------------------------------------- +Name: BitWidthTrans_512To128 +Author: YangFan +Function: 512 bit dma data to 128 bit WQE seg, to facilitate decoding. +--------------------------------------------- Module Decription : End -----------------------------------------------*/ + +/*------------------------------------------- Timescale Definition : Begin ------------------------------------------*/ +`timescale 1ns / 1ps +/*------------------------------------------- Timescale Definition : End --------------------------------------------*/ + +/*------------------------------------------- Included Files : Begin ------------------------------------------------*/ +`include "protocol_engine_def.vh" +/*------------------------------------------- Included Files : End --------------------------------------------------*/ + +/*------------------------------------------- Input/Output Definition : Begin ---------------------------------------*/ +module BitWidthTrans_512To128 +( + input wire clk, + input wire rst, + + input wire size_valid, + input wire [31:0] block_size, + + output wire gather_resp_rd_en, + input wire gather_resp_empty, + input wire [511:0] gather_resp_dout, + + output wire wqe_seg_valid, + output wire [127:0] wqe_seg_data, + input wire wqe_seg_ready +); +/*------------------------------------------- Input/Output Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Macros Definition : Begin ---------------------------------------*/ +/*------------------------------------------- Local Macros Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Variables Definition : Begin ------------------------------------*/ +reg [31:0] data_left; +/*------------------------------------------- Local Variables Definition : End --------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : Begin ---------------------------------------*/ +/*------------------------------------------- Submodules Instatiation : End -----------------------------------------*/ + +/*------------------------------------------- State Machine Definition : Begin --------------------------------------*/ +reg [2:0] cur_state; +reg [2:0] next_state; + +parameter [2:0] IDLE_s = 3'd1, + PIECE_0_s = 3'd2, + PIECE_1_s = 3'd3, + PIECE_2_s = 3'd4, + PIECE_3_s = 3'd5; + +always @(posedge clk or posedge rst) begin + if(rst) begin + cur_state <= IDLE_s; + end + else begin + cur_state <= next_state; + end +end + +always @(*) begin + case(cur_state) + IDLE_s: if(!gather_resp_empty && size_valid) begin + next_state = PIECE_0_s; + end + else begin + next_state = IDLE_s; + end + PIECE_0_s: if(wqe_seg_ready && data_left <= 16) begin + next_state = IDLE_s; + end + else if(wqe_seg_ready && data_left > 16) begin + next_state = PIECE_1_s; + end + else begin + next_state = PIECE_0_s; + end + PIECE_1_s: if(wqe_seg_ready && data_left <= 16) begin + next_state = IDLE_s; + end + else if(wqe_seg_ready && data_left > 16) begin + next_state = PIECE_2_s; + end + else begin + next_state = PIECE_1_s; + end + PIECE_2_s: if(wqe_seg_ready && data_left <= 16) begin + next_state = IDLE_s; + end + else if(wqe_seg_ready && data_left > 16) begin + next_state = PIECE_3_s; + end + else begin + next_state = PIECE_2_s; + end + PIECE_3_s: if(wqe_seg_ready && data_left <= 16) begin + next_state = IDLE_s; + end + else if(wqe_seg_ready && data_left > 16) begin + next_state = PIECE_0_s; + end + else begin + next_state = PIECE_3_s; + end + default: next_state = IDLE_s; + endcase +end +/*------------------------------------------- State Machine Definition : End ----------------------------------------*/ + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ +//-- data_left -- +always @(posedge clk or posedge rst) begin + if (rst) begin + data_left <= 'd0; + end + else if (cur_state == IDLE_s && !gather_resp_empty) begin + data_left <= block_size; + end + else if(cur_state == PIECE_0_s && !gather_resp_empty && wqe_seg_ready) begin + data_left <= (data_left <= 16) ? 'd0 : data_left - 16; + end + else if(cur_state == PIECE_1_s && wqe_seg_ready) begin + data_left <= (data_left <= 16) ? 'd0 : data_left - 16; + end + else if(cur_state == PIECE_2_s && wqe_seg_ready) begin + data_left <= (data_left <= 16) ? 'd0 : data_left - 16; + end + else if(cur_state == PIECE_3_s && wqe_seg_ready) begin + data_left <= (data_left <= 16) ? 'd0 : data_left - 16; + end + else begin + data_left <= data_left; + end +end + +//-- gather_resp_rd_en -- +assign gather_resp_rd_en = (cur_state == PIECE_0_s && data_left <= 16 && wqe_seg_ready) ? 'd1 : + (cur_state == PIECE_1_s && data_left <= 16 && wqe_seg_ready) ? 'd1 : + (cur_state == PIECE_2_s && data_left <= 16 && wqe_seg_ready) ? 'd1 : + (cur_state == PIECE_3_s && wqe_seg_ready) ? 'd1 : 'd0; + +//-- wqe_seg_valid -- +//-- wqe_seg_data -- +assign wqe_seg_valid = (cur_state == PIECE_0_s && !gather_resp_empty) ? 'd1 : + (cur_state == PIECE_1_s) ? 'd1 : + (cur_state == PIECE_2_s) ? 'd1 : + (cur_state == PIECE_3_s) ? 'd1 : 'd0; +assign wqe_seg_data = (cur_state == PIECE_0_s) ? gather_resp_dout[128 * 1 - 1 : 128 * 0] : + (cur_state == PIECE_1_s) ? gather_resp_dout[128 * 2 - 1 : 128 * 1] : + (cur_state == PIECE_2_s) ? gather_resp_dout[128 * 3 - 1 : 128 * 2] : + (cur_state == PIECE_3_s) ? gather_resp_dout[128 * 4 - 1 : 128 * 3] : 'd0; +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ + +/*------------------------------------------- Local Macros Undef : Begin --------------------------------------------*/ +/*------------------------------------------- Local Macros Undef : End ----------------------------------------------*/ + +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/QueueSubsystem/Common/WQECache.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/QueueSubsystem/Common/WQECache.v new file mode 100644 index 0000000000000000000000000000000000000000..e21f655617e5b024a6bb02612cb037d839d32b0e --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/QueueSubsystem/Common/WQECache.v @@ -0,0 +1,132 @@ +/*------------------------------------------- Module Description : Begin ---------------------------------------------- +Name: WQECache +Author: YangFan +Function: Fetch WQE from WQECache or Host Memory. +--------------------------------------------- Module Decription : End -----------------------------------------------*/ + +/*------------------------------------------- Timescale Definition : Begin ------------------------------------------*/ +`timescale 1ns / 1ps +/*------------------------------------------- Timescale Definition : End --------------------------------------------*/ + +/*------------------------------------------- Included Files : Begin ------------------------------------------------*/ +`include "protocol_engine_def.vh" +/*------------------------------------------- Included Files : End --------------------------------------------------*/ + +/*------------------------------------------- Input/Output Definition : Begin ---------------------------------------*/ +module WQECache +#( + parameter CACHE_SLOT_NUM = 256, + parameter CACHE_SLOT_NUM_LOG = log2b(CACHE_SLOT_NUM - 1), + + parameter CACHE_CELL_NUM = 256, + parameter CACHE_CELL_NUM_LOG = log2b(CACHE_CELL_NUM - 1) +) +( + input wire clk, + input wire rst, + + input wire cache_buffer_wea, + input wire [log2b(CACHE_SLOT_NUM * CACHE_CELL_NUM - 1) - 1 : 0] cache_buffer_addra, + input wire [`WQE_SEG_WIDTH - 1 : 0] cache_buffer_dina, + + input wire [log2b(CACHE_SLOT_NUM * CACHE_CELL_NUM - 1) - 1 : 0] cache_buffer_addrb, + output wire [`WQE_SEG_WIDTH - 1 : 0] cache_buffer_doutb, + + input wire cache_owned_wea, + input wire [CACHE_CELL_NUM_LOG - 1 : 0] cache_owned_addra, + input wire [`QP_NUM_LOG - 1 : 0] cache_owned_dina, + output wire [`QP_NUM_LOG - 1 : 0] cache_owned_douta, + + input wire cache_owned_web, + input wire [CACHE_CELL_NUM_LOG - 1 : 0] cache_owned_addrb, + input wire [`QP_NUM_LOG - 1 : 0] cache_owned_dinb, + output wire [`QP_NUM_LOG - 1 : 0] cache_owned_doutb, + + input wire cache_offset_wea, + input wire [`QP_NUM_LOG - 1 : 0] cache_offset_addra, + input wire [CACHE_SLOT_NUM_LOG - 1:0] cache_offset_dina, + output wire [CACHE_SLOT_NUM_LOG - 1:0] cache_offset_douta, + + input wire cache_offset_web, + input wire [`QP_NUM_LOG - 1 : 0] cache_offset_addrb, + input wire [CACHE_SLOT_NUM_LOG - 1:0] cache_offset_dinb, + output wire [CACHE_SLOT_NUM_LOG - 1:0] cache_offset_doutb + +); +/*------------------------------------------- Input/Output Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Macros Definition : Begin ---------------------------------------*/ +/*------------------------------------------- Local Macros Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Variables Definition : Begin ------------------------------------*/ +/*------------------------------------------- Local Variables Definition : End --------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : Begin ---------------------------------------*/ +SRAM_TDP_Template #( + .RAM_WIDTH ( `QP_NUM_LOG - CACHE_CELL_NUM_LOG + 1 ), //+1 for valid bit + .RAM_DEPTH ( CACHE_CELL_NUM ) +) +CacheOwnedTable +( + .clk ( clk ), + .rst ( rst ), + + .wea ( cache_owned_wea ), + .addra ( cache_owned_addra ), + .dina ( cache_owned_dina ), + .douta ( cache_owned_douta ), + + .web ( cache_owned_web ), + .addrb ( cache_owned_addrb ), + .dinb ( cache_owned_dinb ), + .doutb ( cache_owned_doutb ) +); + +SRAM_TDP_Template #( + .RAM_WIDTH ( CACHE_SLOT_NUM_LOG ), //Record each cell offset(in unit of slot) + .RAM_DEPTH ( CACHE_CELL_NUM ) +) +CacheOffsetTable +( + .clk ( clk ), + .rst ( rst ), + + .wea ( cache_offset_wea ), + .addra ( cache_offset_addra ), + .dina ( cache_offset_dina ), + .douta ( cache_offset_douta ), + + .web ( cache_offset_web ), + .addrb ( cache_offset_addrb ), + .dinb ( cache_offset_dinb ), + .doutb ( cache_offset_doutb ) +); + +SRAM_SDP_Template #( + .RAM_WIDTH ( `WQE_SEG_WIDTH ), + .RAM_DEPTH ( CACHE_CELL_NUM * CACHE_SLOT_NUM ) +) +CacheBuffer +( + .clk ( clk ), + .rst ( rst ), + + .wea ( cache_buffer_wea ), + .addra ( cache_buffer_addra ), + .dina ( cache_buffer_dina ), + + .addrb ( cache_buffer_addrb ), + .doutb ( cache_buffer_doutb ) +); +/*------------------------------------------- Submodules Instatiation : End -----------------------------------------*/ + +/*------------------------------------------- State Machine Definition : Begin --------------------------------------*/ +/*------------------------------------------- State Machine Definition : End ----------------------------------------*/ + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ + +/*------------------------------------------- Local Macros Undef : Begin --------------------------------------------*/ +/*------------------------------------------- Local Macros Undef : End ----------------------------------------------*/ + +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/QueueSubsystem/Common/WQEFetch.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/QueueSubsystem/Common/WQEFetch.v new file mode 100644 index 0000000000000000000000000000000000000000..6df345f44856f9356acd972b1a0b377b0ca961d5 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/QueueSubsystem/Common/WQEFetch.v @@ -0,0 +1,616 @@ +/*------------------------------------------- Module Description : Begin ---------------------------------------------- +Name: WQEFetch +Author: YangFan +Function: Fetch WQE from WQECache or Host Memory. +--------------------------------------------- Module Decription : End -----------------------------------------------*/ + +/*------------------------------------------- Timescale Definition : Begin ------------------------------------------*/ +`timescale 1ns / 1ps +/*------------------------------------------- Timescale Definition : End --------------------------------------------*/ + +/*------------------------------------------- Included Files : Begin ------------------------------------------------*/ +`include "protocol_engine_def.vh" +/*------------------------------------------- Included Files : End --------------------------------------------------*/ + +/*------------------------------------------- Input/Output Definition : Begin ---------------------------------------*/ +module WQEFetch +#( + parameter CACHE_SLOT_NUM = 256, + parameter CACHE_SLOT_NUM_LOG = log2b(CACHE_SLOT_NUM), + + parameter CACHE_CELL_NUM = 256, + parameter CACHE_CELL_NUM_LOG = log2b(CACHE_CELL_NUM) +) +( + input wire clk, + input wire rst, + +//Interface with SQMetaProc(Send) or RDMACore(Recv) + input wire meta_valid, + input wire [`SQ_META_WIDTH - 1 : 0] meta_data, + output wire meta_ready, + +//Interface with WQECache + //Interface with Cache Buffer + output reg cache_buffer_wea, + output reg [log2b(CACHE_CELL_NUM * CACHE_SLOT_NUM - 1) - 1 : 0] cache_buffer_addra, + output reg [`WQE_SEG_WIDTH - 1 : 0] cache_buffer_dina, + + output wire [log2b(CACHE_CELL_NUM * CACHE_SLOT_NUM - 1) - 1 : 0] cache_buffer_addrb, + input wire [`WQE_SEG_WIDTH - 1 : 0] cache_buffer_doutb, + + //Interface with Cache Owned Table + output reg cache_owned_wen, + output reg [CACHE_CELL_NUM_LOG - 1 : 0] cache_owned_addr, + output reg [`QP_NUM_LOG - CACHE_CELL_NUM_LOG + 1 - 1 : 0] cache_owned_din, + input wire [`QP_NUM_LOG - CACHE_CELL_NUM_LOG + 1 - 1 : 0] cache_owned_dout, + +//Interface with DMA Read Channel + output wire dma_rd_req_valid, + output wire [`DMA_HEAD_WIDTH - 1 : 0] dma_rd_req_head, + output wire [`DMA_DATA_WIDTH - 1 : 0] dma_rd_req_data, + output wire dma_rd_req_last, + input wire dma_rd_req_ready, + + input wire dma_rd_rsp_valid, + input wire [`DMA_HEAD_WIDTH - 1 : 0] dma_rd_rsp_head, + input wire [`DMA_DATA_WIDTH - 1 : 0] dma_rd_rsp_data, + input wire dma_rd_rsp_last, + output wire dma_rd_rsp_ready, + +//-- Interface with Cache Offset + output wire cache_offset_wen, + output wire [`QP_NUM_LOG - 1 : 0] cache_offset_addr, + output wire [CACHE_SLOT_NUM_LOG - 1:0] cache_offset_din, + input wire [CACHE_SLOT_NUM_LOG - 1:0] cache_offset_dout, + +//Interface with WQEParser or RDMACore + output wire wqe_valid, + output wire [`WQE_PARSER_META_WIDTH - 1 : 0] wqe_head, + output wire [`WQE_SEG_WIDTH - 1 : 0] wqe_data, + output wire wqe_start, + output wire wqe_last, + input wire wqe_ready + +); +/*------------------------------------------- Input/Output Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Macros Definition : Begin ---------------------------------------*/ +//Cell Index is lower bits of QPN +`define CELL_INDEX_OFFSET CACHE_CELL_NUM_LOG-1:0 + +`define LOCAL_QPN_OFFSET 15:0 + +`define MR_VALID_0_OFFSET 3+288:0+288 +`define MR_VALID_1_OFFSET 7+288:4+288 +`define MR_SIZE_0_OFFSET 63+288:32+288 +`define MR_SIZE_1_OFFSET 95+288:64+288 +`define MR_PTE_0_OFFSET 159+288:96+288 +`define MR_PTE_1_OFFSET 223+288:160+288 + +//NextUnit filed offset +`define CUR_WQE_SIZE_OFFSET 77:70 +`define NEXT_WQE_SIZE_OFFSET 37:32 +`define NEXT_WQE_ADDR_OFFSET 31:6 +`define NEXT_WQE_VALID_OFFSET 5 +/*------------------------------------------- Local Macros Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Variables Definition : Begin ------------------------------------*/ +wire meta_valid_out; +wire [`SQ_META_WIDTH - 1 : 0] meta_data_out; +wire meta_ready_out; + + +reg [`SQ_META_WIDTH - 1 : 0] meta_data_out_diff; + +reg gather_req_wr_en; +reg [`DMA_LENGTH_WIDTH * 2 + `DMA_ADDR_WIDTH - 1 : 0] gather_req_din; +wire gather_req_prog_full; + +wire gather_resp_rd_en; +wire gather_resp_empty; +wire [`DMA_DATA_WIDTH - 1 : 0] gather_resp_dout; + +reg [log2b(CACHE_CELL_NUM * CACHE_SLOT_NUM - 1) - 1 : 0] cache_buffer_addra_diff; +reg [log2b(CACHE_CELL_NUM * CACHE_SLOT_NUM - 1) - 1 : 0] cache_buffer_addrb_diff; + +//SQ Metadata +reg [CACHE_CELL_NUM_LOG - 1 : 0] cell_index; +reg [23:0] local_qpn; + +reg [3:0] mr_valid_0; +reg [3:0] mr_valid_1; +reg [31:0] mr_size_0; +reg [63:0] mr_pte_0; +reg [31:0] mr_size_1; +reg [63:0] mr_pte_1; + +reg [31:0] wqe_fetch_total; +reg [31:0] wqe_fetch_count; + +wire cache_valid; + +reg [31:0] dma_req_count; +reg [31:0] dma_req_total; + +reg [31:0] cache_slot_wr_count; +reg [31:0] cache_slot_wr_total; + +wire wqe_seg_valid; +wire [`WQE_SEG_WIDTH - 1 : 0] wqe_seg_data; +wire wqe_seg_ready; + +wire [5:0] next_wqe_size; +wire [25:0] next_wqe_addr; +wire [0:0] next_wqe_valid; + +wire size_valid; + +reg judge_count; +/*------------------------------------------- Local Variables Definition : End --------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : Begin ---------------------------------------*/ +wire meta_prog_full; +wire meta_empty; + +assign meta_ready = !meta_prog_full; +assign meta_valid_out = !meta_empty; + +SyncFIFO_Template #( + .FIFO_TYPE (1), + .FIFO_WIDTH (`SQ_META_WIDTH), + .FIFO_DEPTH (4096) +) +SQMetaFIFO_Inst +( + .clk(clk), + .rst(rst), + + .wr_en(meta_valid), + .din(meta_data), + .prog_full(meta_prog_full), + .rd_en(meta_ready_out), + .dout(meta_data_out), + .empty(meta_empty) +); + + + +GatherData GatherData_Inst( + .clk ( clk ), + .rst ( rst ), + + .gather_req_wr_en ( gather_req_wr_en ), + .gather_req_din ( gather_req_din ), + .gather_req_prog_full ( gather_req_prog_full ), + + .dma_rd_req_valid ( dma_rd_req_valid ), + .dma_rd_req_head ( dma_rd_req_head ), + .dma_rd_req_data ( dma_rd_req_data ), + .dma_rd_req_last ( dma_rd_req_last ), + .dma_rd_req_ready ( dma_rd_req_ready ), + + .dma_rd_rsp_valid ( dma_rd_rsp_valid ), + .dma_rd_rsp_head ( dma_rd_rsp_head ), + .dma_rd_rsp_data ( dma_rd_rsp_data ), + .dma_rd_rsp_last ( dma_rd_rsp_last ), + .dma_rd_rsp_ready ( dma_rd_rsp_ready ), + + .gather_resp_rd_en ( gather_resp_rd_en ), + .gather_resp_empty ( gather_resp_empty ), + .gather_resp_dout ( gather_resp_dout ) +); + +BitWidthTrans_512To128 WQEBlockBitTrans_Inst( + .clk ( clk ), + .rst ( rst ), + + .size_valid ( size_valid ), + .block_size ( mr_size_0 + mr_size_1 ), + + .gather_resp_rd_en ( gather_resp_rd_en ), + .gather_resp_empty ( gather_resp_empty ), + .gather_resp_dout ( gather_resp_dout ), + + .wqe_seg_valid ( wqe_seg_valid ), + .wqe_seg_data ( wqe_seg_data ), + .wqe_seg_ready ( wqe_seg_ready ) +); + +/*------------------------------------------- Submodules Instatiation : End -----------------------------------------*/ + +/*------------------------------------------- State Machine Definition : Begin --------------------------------------*/ +reg [2:0] cur_state; +reg [2:0] next_state; + +parameter [2:0] IDLE_s = 3'd1, + JUDGE_s = 3'd2, //Decide whether we need to DMA from Host Memory + DMA_REQ_s = 3'd4, + DMA_RSP_s = 3'd5, + FETCH_WQE_s = 3'd6; + +always @(posedge clk or posedge rst) begin + if(rst) begin + cur_state <= IDLE_s; + end + else begin + cur_state <= next_state; + end +end + +always @(*) begin + case(cur_state) + IDLE_s: if(meta_valid_out) begin + next_state = JUDGE_s; + end + else begin + next_state = IDLE_s; + end + JUDGE_s: if(!cache_valid && judge_count == 'd1) begin //Current QP is not cached. + next_state = DMA_REQ_s; + end + else if(cache_valid && judge_count == 'd1) begin //Current WQE Cache Buffer is available + next_state = FETCH_WQE_s; + end + else begin + next_state = JUDGE_s; + end + DMA_REQ_s: if(dma_req_count == dma_req_total && !gather_req_prog_full) begin + next_state = DMA_RSP_s; + end + else begin + next_state = DMA_REQ_s; + end + DMA_RSP_s: if(cache_slot_wr_count == cache_slot_wr_total && wqe_seg_valid) begin + next_state = FETCH_WQE_s; + end + else begin + next_state = DMA_RSP_s; + end + FETCH_WQE_s: if((wqe_fetch_count == wqe_fetch_total) && wqe_valid && wqe_ready) begin + next_state = IDLE_s; + end + else begin + next_state = FETCH_WQE_s; + end + default: next_state = IDLE_s; + endcase +end +/*------------------------------------------- State Machine Definition : End ----------------------------------------*/ + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ +//-- next_wqe_size -- +//-- next_wqe_addr -- +//-- next_wqe_valid -- +assign next_wqe_size = cache_buffer_doutb[`NEXT_WQE_SIZE_OFFSET]; +assign next_wqe_addr = cache_buffer_doutb[`NEXT_WQE_ADDR_OFFSET]; +assign next_wqe_valid = cache_buffer_doutb[`NEXT_WQE_VALID_OFFSET]; + +//-- meta_data_out_diff -- +always @(posedge clk or posedge rst) begin + if (rst) begin + meta_data_out_diff <= 'd0; + end + else if (cur_state == IDLE_s && meta_valid_out) begin + meta_data_out_diff <= meta_data_out; + end + else begin + meta_data_out_diff <= meta_data_out_diff; + end +end + +//-- cell_index -- +//-- local_qpn -- +//-- mr_valid_0 -- +//-- mr_valid_1 -- +//-- mr_size_0 -- +//-- mr_pte_0 -- +//-- mr_size_1 -- +//-- mr_pte_1 -- +always @(posedge clk or posedge rst) begin + if(rst) begin + cell_index <= 'd0; + local_qpn <= 'd0; + + mr_valid_0 <= 'd0; + mr_valid_1 <= 'd0; + mr_size_0 <= 'd0; + mr_pte_0 <= 'd0; + mr_size_1 <= 'd0; + mr_pte_1 <= 'd0; + end + else if(cur_state == IDLE_s && meta_valid_out) begin + cell_index <= meta_data_out[`CELL_INDEX_OFFSET]; + local_qpn <= meta_data_out[`LOCAL_QPN_OFFSET]; + + mr_valid_0 <= meta_data_out[`MR_VALID_0_OFFSET]; + mr_valid_1 <= meta_data_out[`MR_VALID_1_OFFSET]; + mr_size_0 <= meta_data_out[`MR_SIZE_0_OFFSET]; + mr_pte_0 <= meta_data_out[`MR_PTE_0_OFFSET]; + mr_size_1 <= meta_data_out[`MR_SIZE_1_OFFSET]; + mr_pte_1 <= meta_data_out[`MR_PTE_1_OFFSET]; + end + else begin + cell_index <= cell_index; + local_qpn <= local_qpn; + + mr_valid_0 <= mr_valid_0; + mr_valid_1 <= mr_valid_1; + mr_size_0 <= mr_size_0; + mr_pte_0 <= mr_pte_0; + mr_size_1 <= mr_size_1; + mr_pte_1 <= mr_pte_1; + end +end + +//-- dma_req_count -- +always @(posedge clk or posedge rst) begin + if (rst) begin + dma_req_count <= 'd0; + end + else if (cur_state == IDLE_s && meta_valid_out) begin + dma_req_count <= 'd1; + end + else if(cur_state == DMA_REQ_s && !gather_req_prog_full) begin + dma_req_count <= dma_req_count + 'd1; + end + else begin + dma_req_count <= dma_req_count; + end +end + +//-- dma_req_total -- +always @(posedge clk or posedge rst) begin + if (rst) begin + dma_req_total <= 'd0; + end + else if (cur_state == IDLE_s && meta_valid_out) begin + if(meta_data_out[`MR_RESP_VALID_0_OFFSET] == `PAGE_VALID && meta_data_out[`MR_RESP_VALID_1_OFFSET] == `PAGE_VALID) begin + dma_req_total <= 'd2; + end + else begin + dma_req_total <= 'd1; + end + end + else begin + dma_req_total <= dma_req_total; + end +end + +//-- gather_req_wr_en -- +//-- gather_req_din -- +always @(posedge clk or posedge rst) begin + if (rst) begin + gather_req_wr_en <= 'd0; + gather_req_din <= 'd0; + end + else if (cur_state == DMA_REQ_s && !gather_req_prog_full) begin + if(dma_req_count == 'd1) begin + gather_req_wr_en <= 'd1; + gather_req_din <= {mr_size_0 + mr_size_1, mr_size_0, mr_pte_0}; + end + else if(dma_req_count == 'd2) begin + gather_req_wr_en <= 'd1; + gather_req_din <= {mr_size_0 + mr_size_1, mr_size_1, mr_pte_1}; + end + else begin + gather_req_wr_en <= 'd0; + gather_req_din <= 'd0; + end + end + else begin + gather_req_wr_en <= 'd0; + gather_req_din <= 'd0; + end +end + +//-- cache_valid -- Cahce entry is valid and current cache entry is owned by current qp. CACHE_CELL_NUM must be less than QP_NUM +assign cache_valid = cache_owned_dout[`QP_NUM_LOG - CACHE_CELL_NUM_LOG] && (cache_owned_dout[`QP_NUM_LOG - CACHE_CELL_NUM_LOG - 1 : 0] == local_qpn[`QP_NUM_LOG - 1 : CACHE_CELL_NUM_LOG]); + +//-- cache_slot_wr_count -- +always @(posedge clk or posedge rst) begin + if (rst) begin + cache_slot_wr_count <= 'd0; + end + else if (cur_state == DMA_REQ_s && next_state == DMA_RSP_s) begin + cache_slot_wr_count <= 'd1; + end + else if (cur_state == DMA_RSP_s && wqe_seg_valid) begin + cache_slot_wr_count <= cache_slot_wr_count + 'd1; + end + else begin + cache_slot_wr_count <= cache_slot_wr_count; + end +end + +//-- cache_slot_wr_total -- +always @(posedge clk or posedge rst) begin + if (rst) begin + cache_slot_wr_total <= 'd0; + end + else if (cur_state == DMA_REQ_s && next_state == DMA_RSP_s) begin + cache_slot_wr_total <= (mr_size_0 + mr_size_1) >> 4; //Each cycle is 16B WQE Seg + end + else begin + cache_slot_wr_total <= cache_slot_wr_total; + end +end + +//-- cache_buffer_addra_diff -- +always @(posedge clk or posedge rst) begin + if (rst) begin + cache_buffer_addra_diff <= 'd0; + end + else if (cur_state == DMA_REQ_s) begin + cache_buffer_addra_diff <= local_qpn[CACHE_CELL_NUM_LOG - 1 : 0] << CACHE_SLOT_NUM_LOG; + end + else if (cur_state == DMA_RSP_s && wqe_seg_valid) begin + cache_buffer_addra_diff <= cache_buffer_addra_diff + 'd1; + end + else begin + cache_buffer_addra_diff <= cache_buffer_addra_diff; + end +end + +//-- cache_buffer_wea -- +//-- cache_buffer_addra -- +//-- cache_buffer_dina -- +always @(*) begin + if (rst) begin + cache_buffer_wea = 'd0; + cache_buffer_addra = 'd0; + cache_buffer_dina = 'd0; + end + else if (cur_state == DMA_RSP_s && wqe_seg_valid) begin + cache_buffer_wea = 'd1; + cache_buffer_addra = cache_buffer_addra_diff; + cache_buffer_dina = wqe_seg_data; + end + else begin + cache_buffer_wea = 'd0; + cache_buffer_addra = 'd0; + cache_buffer_dina = 'd0; + end +end + +//-- cache_buffer_addrb -- +assign cache_buffer_addrb = (cur_state == JUDGE_s && cache_valid) ? ((local_qpn[`CELL_INDEX_OFFSET] << CACHE_SLOT_NUM_LOG) + cache_offset_dout) : + (cur_state == JUDGE_s && !cache_valid) ? ((local_qpn[`CELL_INDEX_OFFSET] << CACHE_SLOT_NUM_LOG) + 'd0) : //If a cache cell is valid, it must be processed in WQEParser, cache offset cannot be 0 + (cur_state == FETCH_WQE_s && wqe_ready) ? cache_buffer_addrb_diff + 'd1 : cache_buffer_addrb_diff; + +//-- cache_buffer_addrb_diff -- +always @(posedge clk or posedge rst) begin + if (rst) begin + cache_buffer_addrb_diff <= 'd0; + end + else begin + cache_buffer_addrb_diff <= cache_buffer_addrb; + end +end + +//-- cache_owned_wen -- +//-- cache_owned_addr -- +//-- cache_owned_din -- +always @(*) begin + if(rst) begin + cache_owned_wen = 'd0; + cache_owned_addr = 'd0; + cache_owned_din = 'd0; + end + else if(cur_state == IDLE_s && meta_valid_out) begin + cache_owned_wen = 'd0; + cache_owned_addr = meta_data_out[`CELL_INDEX_OFFSET]; + cache_owned_din = 'd0; + end + else if(cur_state == DMA_RSP_s && cache_slot_wr_count == cache_slot_wr_total && wqe_seg_valid) begin + cache_owned_wen = 'd1; + cache_owned_addr = cell_index; + cache_owned_din = {'d1, local_qpn[`QP_NUM_LOG - 1 : CACHE_CELL_NUM_LOG]}; + end + else begin + cache_owned_wen = 'd0; + cache_owned_addr = cell_index; + cache_owned_din = 'd0; + end +end + +//-- cache_offset_wen -- +//-- cache_offset_addr -- +//-- cache_offset_din -- +assign cache_offset_wen = (cur_state == DMA_REQ_s) ? 'd1 : 'd0; +assign cache_offset_addr = (cur_state == IDLE_s && meta_valid_out) ? meta_data_out[`CELL_INDEX_OFFSET] : + (cur_state == DMA_REQ_s) ? local_qpn[`CELL_INDEX_OFFSET] : local_qpn[`CELL_INDEX_OFFSET]; +assign cache_offset_din = (cur_state == DMA_REQ_s) ? 'd0 : 'd0; + +//-- wqe_fetch_total -- +always @(posedge clk or posedge rst) begin + if(rst) begin + wqe_fetch_total <= 'd0; + end + else if(cur_state == IDLE_s) begin + wqe_fetch_total <= 'd0; + end + else if(cur_state == JUDGE_s && judge_count == 'd1) begin + wqe_fetch_total <= cache_buffer_doutb[`CUR_WQE_SIZE_OFFSET]; + end + else if(cur_state == DMA_RSP_s && cache_slot_wr_count == 'd1) begin + wqe_fetch_total <= wqe_seg_data[`CUR_WQE_SIZE_OFFSET]; //WQE size is in unit of 16B, hence cur_wqe_size is 16B count + end + else begin + wqe_fetch_total <= wqe_fetch_total; + end +end + +//-- wqe_fetch_count -- +always @(posedge clk or posedge rst) begin + if(rst) begin + wqe_fetch_count <= 'd0; + end + else if(cur_state == IDLE_s) begin + wqe_fetch_count <= 'd0; + end + else if(cur_state != FETCH_WQE_s && next_state == FETCH_WQE_s) begin + wqe_fetch_count <= 'd1; + end + else if(cur_state == FETCH_WQE_s && wqe_valid && wqe_ready) begin + wqe_fetch_count <= wqe_fetch_count + 'd1; + end + else begin + wqe_fetch_count <= wqe_fetch_count; + end +end + +//-- wqe_valid -- +//-- wqe_head -- +//-- wqe_data -- +//-- wqe_start -- +//-- wqe_last -- +assign wqe_valid = (cur_state == FETCH_WQE_s) ? 'd1 : 'd0; +assign wqe_head = (cur_state == FETCH_WQE_s) ? meta_data_out_diff[`WQE_PARSER_META_WIDTH - 1 : 0] : 'd0; +assign wqe_data = (cur_state == FETCH_WQE_s) ? cache_buffer_doutb : 'd0; +assign wqe_start = (cur_state == FETCH_WQE_s) ? (wqe_fetch_count == 'd1) : 'd0; +assign wqe_last = (cur_state == FETCH_WQE_s) ? (wqe_fetch_count == wqe_fetch_total) : 'd0; + + +//-- meta_ready_out -- +assign meta_ready_out = (cur_state == IDLE_s) ? 'd1 : 'd0; + +//-- size_valid -- +assign size_valid = (cur_state != IDLE_s); + +//-- wqe_seg_ready -- +assign wqe_seg_ready = 'd1; + +//-- judge_count -- +always @(posedge clk or posedge rst) begin + if (rst) begin + judge_count <= 'd0; + end + else if (cur_state == JUDGE_s) begin + judge_count <= judge_count + 'd1; + end + else begin + judge_count <= 'd0; + end +end +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ + +/*------------------------------------------- Local Macros Undef : Begin --------------------------------------------*/ +`undef CELL_INDEX_OFFSET + +`undef LOCAL_QPN_OFFSET + +`undef MR_VALID_0_OFFSET +`undef MR_VALID_1_OFFSET +`undef MR_SIZE_0_OFFSET +`undef MR_SIZE_1_OFFSET +`undef MR_PTE_0_OFFSET +`undef MR_PTE_1_OFFSET + +`undef CUR_WQE_SIZE_OFFSET +`undef NEXT_WQE_SIZE_OFFSET +`undef NEXT_WQE_ADDR_OFFSET +`undef NEXT_WQE_VALID_OFFSET +/*------------------------------------------- Local Macros Undef : End ----------------------------------------------*/ + +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/QueueSubsystem/EQMgt/EQMgt.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/QueueSubsystem/EQMgt/EQMgt.v new file mode 100644 index 0000000000000000000000000000000000000000..4d890f64fb130677036f83119dc48df9666e1f9f --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/QueueSubsystem/EQMgt/EQMgt.v @@ -0,0 +1,97 @@ +/*------------------------------------------- Module Description : Begin ---------------------------------------------- +Name: CQMgt +Author: YangFan +Function: 1.Manage CQ. +--------------------------------------------- Module Decription : End -----------------------------------------------*/ + +/*------------------------------------------- Timescale Definition : Begin ------------------------------------------*/ +`timescale 1ns / 1ps +/*------------------------------------------- Timescale Definition : End --------------------------------------------*/ + +/*------------------------------------------- Included Files : Begin ------------------------------------------------*/ +`include "protocol_engine_def.vh" +/*------------------------------------------- Included Files : End --------------------------------------------------*/ + +/*------------------------------------------- Input/Output Definition : Begin ---------------------------------------*/ +module EQMgt +( + input wire clk, + input wire rst, + +//Interface with ReqTransCore + input wire TX_REQ_eq_req_valid, + input wire [`EQ_REQ_HEAD_WIDTH - 1 : 0] TX_REQ_eq_req_head, + output wire TX_REQ_eq_req_ready, + + output wire TX_REQ_eq_resp_valid, + output wire [`EQ_RESP_HEAD_WIDTH - 1 : 0] TX_REQ_eq_resp_head, + input wire TX_REQ_eq_resp_ready, + +//Interface with ReqRecvCore + input wire RX_REQ_eq_req_valid, + input wire [`EQ_REQ_HEAD_WIDTH - 1 : 0] RX_REQ_eq_req_head, + output wire RX_REQ_eq_req_ready, + + output wire RX_REQ_eq_resp_valid, + output wire [`EQ_RESP_HEAD_WIDTH - 1 : 0] RX_REQ_eq_resp_head, + input wire RX_REQ_eq_resp_ready, + +//Interface with RespRecvCore + input wire RX_RESP_eq_req_valid, + input wire [`EQ_REQ_HEAD_WIDTH - 1 : 0] RX_RESP_eq_req_head, + output wire RX_RESP_eq_req_ready, + + output wire RX_RESP_eq_resp_valid, + output wire [`EQ_RESP_HEAD_WIDTH - 1 : 0] RX_RESP_eq_resp_head, + input wire RX_RESP_eq_resp_ready +); + +/*------------------------------------------- Input/Output Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Macros Definition : Begin ---------------------------------------*/ +/*------------------------------------------- Local Macros Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Variables Definition : Begin ------------------------------------*/ +/*------------------------------------------- Local Variables Definition : End --------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : Begin ---------------------------------------*/ +/*------------------------------------------- Submodules Instatiation : End -----------------------------------------*/ + +/*------------------------------------------- State Machine Definition : Begin --------------------------------------*/ +/*------------------------------------------- State Machine Definition : End ----------------------------------------*/ + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ +reg counter; + +always @(posedge clk or posedge rst) begin + if (rst) begin + counter <= 'd1; + end + else begin + counter <= counter; + end +end + +assign TX_REQ_eq_req_ready = 'd1; + +assign TX_REQ_eq_resp_valid = 'd1; +assign TX_REQ_eq_resp_head = 'd1; + +assign RX_REQ_eq_req_ready = 'd1; + +assign RX_REQ_eq_resp_valid = 'd1; +assign RX_REQ_eq_resp_head = 'd1; + +assign RX_RESP_eq_req_ready = 'd1; + +assign RX_RESP_eq_resp_valid = 'd1; +assign RX_RESP_eq_resp_head = 'd1; + + +/*------------------------------------------- Variables Decode : End ----------------------------------------------*/ + +/*------------------------------------------- Local Macros Undef : Begin --------------------------------------------*/ + +/*------------------------------------------- Local Macros Undef : End ----------------------------------------------*/ + +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/QueueSubsystem/QueueSubsystem.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/QueueSubsystem/QueueSubsystem.v new file mode 100644 index 0000000000000000000000000000000000000000..e99a5871ac548907b42abe83208801377435c22d --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/QueueSubsystem/QueueSubsystem.v @@ -0,0 +1,440 @@ +/*------------------------------------------- Module Description : Begin ---------------------------------------------- +Name: CQMgt +Author: YangFan +Function: 1.Manage SQ/RQ/CQ/EQ. +--------------------------------------------- Module Decription : End -----------------------------------------------*/ + +/*------------------------------------------- Timescale Definition : Begin ------------------------------------------*/ +`timescale 1ns / 1ps +/*------------------------------------------- Timescale Definition : End --------------------------------------------*/ + +/*------------------------------------------- Included Files : Begin ------------------------------------------------*/ +`include "protocol_engine_def.vh" +/*------------------------------------------- Included Files : End --------------------------------------------------*/ + +/*------------------------------------------- Input/Output Definition : Begin ---------------------------------------*/ +module QueueSubsystem +#( + parameter INGRESS_CXT_HEAD_WIDTH = 128, + parameter INGRESS_CXT_DATA_WIDTH = 256, + parameter EGRESS_CXT_HEAD_WIDTH = 128, + parameter EGRESS_CXT_DATA_WIDTH = 256, + + parameter INGRESS_MR_HEAD_WIDTH = 128, + parameter INGRESS_MR_DATA_WIDTH = 256, + parameter EGRESS_MR_HEAD_WIDTH = 128, + parameter EGRESS_MR_DATA_WIDTH = 256 +) +( + input wire clk, + input wire rst, + +//Interface with PIO + input wire db_fifo_empty, + input wire [63:0] db_fifo_dout, + output wire db_fifo_rd_en, + +//Interface with CxtMgt + output wire SQ_fetch_cxt_ingress_valid, + output wire [`SQ_OOO_CXT_INGRESS_HEAD_WIDTH - 1 : 0] SQ_fetch_cxt_ingress_head, + output wire [`SQ_OOO_CXT_INGRESS_DATA_WIDTH - 1 : 0] SQ_fetch_cxt_ingress_data, + output wire SQ_fetch_cxt_ingress_start, + output wire SQ_fetch_cxt_ingress_last, + input wire SQ_fetch_cxt_ingress_ready, + + input wire SQ_fetch_cxt_egress_valid, + input wire [`SQ_OOO_CXT_EGRESS_HEAD_WIDTH - 1 : 0] SQ_fetch_cxt_egress_head, + input wire [`SQ_OOO_CXT_EGRESS_DATA_WIDTH - 1 : 0] SQ_fetch_cxt_egress_data, + input wire SQ_fetch_cxt_egress_start, + input wire SQ_fetch_cxt_egress_last, + output wire SQ_fetch_cxt_egress_ready, + +//Interface with MRMgt + output wire SQ_fetch_mr_ingress_valid, + output wire [`SQ_OOO_MR_INGRESS_HEAD_WIDTH - 1 : 0] SQ_fetch_mr_ingress_head, + output wire [`SQ_OOO_MR_INGRESS_DATA_WIDTH - 1 : 0] SQ_fetch_mr_ingress_data, + output wire SQ_fetch_mr_ingress_start, + output wire SQ_fetch_mr_ingress_last, + input wire SQ_fetch_mr_ingress_ready, + + input wire SQ_fetch_mr_egress_valid, + input wire [`SQ_OOO_MR_EGRESS_HEAD_WIDTH - 1 : 0] SQ_fetch_mr_egress_head, + input wire [`SQ_OOO_MR_EGRESS_DATA_WIDTH - 1 : 0] SQ_fetch_mr_egress_data, + input wire SQ_fetch_mr_egress_start, + input wire SQ_fetch_mr_egress_last, + output wire SQ_fetch_mr_egress_ready, + + +//Interface with DMA Read Channel + output wire SQ_dma_rd_req_valid, + output wire [`DMA_HEAD_WIDTH - 1 : 0] SQ_dma_rd_req_head, + output wire [`DMA_DATA_WIDTH - 1 : 0] SQ_dma_rd_req_data, + output wire SQ_dma_rd_req_last, + input wire SQ_dma_rd_req_ready, + + input wire SQ_dma_rd_rsp_valid, + input wire [`DMA_HEAD_WIDTH - 1 : 0] SQ_dma_rd_rsp_head, + input wire [`DMA_DATA_WIDTH - 1 : 0] SQ_dma_rd_rsp_data, + input wire SQ_dma_rd_rsp_last, + output wire SQ_dma_rd_rsp_ready, + +//Interface with RDMACore + output wire sub_wqe_valid, + output wire [`WQE_META_WIDTH - 1 : 0] sub_wqe_meta, + input wire sub_wqe_ready, + +//Interface with DynamicBuffer(Payload Buffer) + output wire insert_req_valid, + output wire insert_req_start, + output wire insert_req_last, + output wire [`INLINE_PAYLOAD_BUFFER_SLOT_NUM_LOG - 1 : 0] insert_req_head, + output wire [`INLINE_PAYLOAD_BUFFER_SLOT_WIDTH - 1 : 0] insert_req_data, + input wire insert_req_ready, + + input wire insert_resp_valid, + input wire [`INLINE_PAYLOAD_BUFFER_SLOT_WIDTH - 1 : 0] insert_resp_data, + + +//Interface with RDMACore/ReqRecvCore + input wire RQ_wqe_req_valid, + input wire [`WQE_META_WIDTH - 1 : 0] RQ_wqe_req_head, + input wire RQ_wqe_req_start, + input wire RQ_wqe_req_last, + output wire RQ_wqe_req_ready, + + output wire RQ_wqe_resp_valid, + output wire [`WQE_META_WIDTH - 1 : 0] RQ_wqe_resp_head, + output wire [`WQE_SEG_WIDTH - 1 : 0] RQ_wqe_resp_data, + output wire RQ_wqe_resp_start, + output wire RQ_wqe_resp_last, + input wire RQ_wqe_resp_ready, + + input wire RQ_cache_offset_wen, + input wire [`QP_NUM_LOG - 1 : 0] RQ_cache_offset_addr, + input wire [`RQ_CACHE_SLOT_NUM_LOG - 1:0] RQ_cache_offset_din, + output wire [`RQ_CACHE_SLOT_NUM_LOG - 1:0] RQ_cache_offset_dout, + + input wire RQ_offset_wen, + input wire [`QP_NUM_LOG - 1 : 0] RQ_offset_addr, + input wire [23:0] RQ_offset_din, + output wire [23:0] RQ_offset_dout, + + input wire RQ_cache_owned_wen, + input wire [`RQ_CACHE_CELL_NUM_LOG - 1 : 0] RQ_cache_owned_addr, + input wire [`QP_NUM_LOG - 1 : 0] RQ_cache_owned_din, + output wire [`QP_NUM_LOG - 1 : 0] RQ_cache_owned_dout, + +//Interface with MRMgt + output wire RQ_fetch_mr_ingress_valid, + output wire [`RQ_OOO_MR_INGRESS_HEAD_WIDTH - 1 : 0] RQ_fetch_mr_ingress_head, + output wire [`RQ_OOO_MR_INGRESS_DATA_WIDTH - 1 : 0] RQ_fetch_mr_ingress_data, + output wire RQ_fetch_mr_ingress_start, + output wire RQ_fetch_mr_ingress_last, + input wire RQ_fetch_mr_ingress_ready, + + input wire RQ_fetch_mr_egress_valid, + input wire [`RQ_OOO_MR_EGRESS_HEAD_WIDTH - 1 : 0] RQ_fetch_mr_egress_head, + input wire [`RQ_OOO_MR_EGRESS_DATA_WIDTH - 1 : 0] RQ_fetch_mr_egress_data, + input wire RQ_fetch_mr_egress_start, + input wire RQ_fetch_mr_egress_last, + output wire RQ_fetch_mr_egress_ready, + +//Interface with DMA Read Channel + output wire RQ_dma_rd_req_valid, + output wire [`DMA_HEAD_WIDTH - 1 : 0] RQ_dma_rd_req_head, + output wire [`DMA_DATA_WIDTH - 1 : 0] RQ_dma_rd_req_data, + output wire RQ_dma_rd_req_last, + input wire RQ_dma_rd_req_ready, + + input wire RQ_dma_rd_rsp_valid, + input wire [`DMA_HEAD_WIDTH - 1 : 0] RQ_dma_rd_rsp_head, + input wire [`DMA_DATA_WIDTH - 1 : 0] RQ_dma_rd_rsp_data, + input wire RQ_dma_rd_rsp_last, + output wire RQ_dma_rd_rsp_ready, + +//Interface with ReqTransCore + input wire TX_REQ_cq_req_valid, + input wire [`CQ_REQ_HEAD_WIDTH - 1 : 0] TX_REQ_cq_req_head, + output wire TX_REQ_cq_req_ready, + + output wire TX_REQ_cq_resp_valid, + output wire [`CQ_RESP_HEAD_WIDTH - 1 : 0] TX_REQ_cq_resp_head, + input wire TX_REQ_cq_resp_ready, + +//Interface with ReqRecvCore + input wire RX_REQ_cq_req_valid, + input wire [`CQ_REQ_HEAD_WIDTH - 1 : 0] RX_REQ_cq_req_head, + output wire RX_REQ_cq_req_ready, + + output wire RX_REQ_cq_resp_valid, + output wire [`CQ_RESP_HEAD_WIDTH - 1 : 0] RX_REQ_cq_resp_head, + input wire RX_REQ_cq_resp_ready, + +//Interface with RespRecvCore + input wire RX_RESP_cq_req_valid, + input wire [`CQ_REQ_HEAD_WIDTH - 1 : 0] RX_RESP_cq_req_head, + output wire RX_RESP_cq_req_ready, + + output wire RX_RESP_cq_resp_valid, + output wire [`CQ_RESP_HEAD_WIDTH - 1 : 0] RX_RESP_cq_resp_head, + input wire RX_RESP_cq_resp_ready, + +//Interface with ReqTransCore + input wire TX_REQ_eq_req_valid, + input wire [`EQ_REQ_HEAD_WIDTH - 1 : 0] TX_REQ_eq_req_head, + output wire TX_REQ_eq_req_ready, + + output wire TX_REQ_eq_resp_valid, + output wire [`EQ_RESP_HEAD_WIDTH - 1 : 0] TX_REQ_eq_resp_head, + input wire TX_REQ_eq_resp_ready, + +//Interface with ReqRecvCore + input wire RX_REQ_eq_req_valid, + input wire [`EQ_REQ_HEAD_WIDTH - 1 : 0] RX_REQ_eq_req_head, + output wire RX_REQ_eq_req_ready, + + output wire RX_REQ_eq_resp_valid, + output wire [`EQ_RESP_HEAD_WIDTH - 1 : 0] RX_REQ_eq_resp_head, + input wire RX_REQ_eq_resp_ready, + +//Interface with RespRecvCore + input wire RX_RESP_eq_req_valid, + input wire [`EQ_REQ_HEAD_WIDTH - 1 : 0] RX_RESP_eq_req_head, + output wire RX_RESP_eq_req_ready, + + output wire RX_RESP_eq_resp_valid, + output wire [`EQ_RESP_HEAD_WIDTH - 1 : 0] RX_RESP_eq_resp_head, + input wire RX_RESP_eq_resp_ready +); + +/*------------------------------------------- Input/Output Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Macros Definition : Begin ---------------------------------------*/ +/*------------------------------------------- Local Macros Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Variables Definition : Begin ------------------------------------*/ +/*------------------------------------------- Local Variables Definition : End --------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : Begin ---------------------------------------*/ +SQMgt +#( + .CACHE_SLOT_NUM ( `SQ_CACHE_SLOT_NUM ), + .CACHE_CELL_NUM ( `SQ_CACHE_CELL_NUM ), + + .INGRESS_CXT_HEAD_WIDTH ( 128 ), + .INGRESS_CXT_DATA_WIDTH ( 256 ), + .EGRESS_CXT_HEAD_WIDTH ( 128 ), + .EGRESS_CXT_DATA_WIDTH ( 256 ), + + .INGRESS_MR_HEAD_WIDTH ( 128 ), + .INGRESS_MR_DATA_WIDTH ( 256 ), + .EGRESS_MR_HEAD_WIDTH ( 128 ), + .EGRESS_MR_DATA_WIDTH ( 256 ) +) +SQMgt_Inst( + .clk ( clk ), + .rst ( rst ), + + .db_fifo_empty ( db_fifo_empty ), + .db_fifo_dout ( db_fifo_dout ), + .db_fifo_rd_en ( db_fifo_rd_en ), + + .fetch_cxt_ingress_valid ( SQ_fetch_cxt_ingress_valid ), + .fetch_cxt_ingress_head ( SQ_fetch_cxt_ingress_head ), + .fetch_cxt_ingress_data ( SQ_fetch_cxt_ingress_data ), + .fetch_cxt_ingress_start ( SQ_fetch_cxt_ingress_start ), + .fetch_cxt_ingress_last ( SQ_fetch_cxt_ingress_last ), + .fetch_cxt_ingress_ready ( SQ_fetch_cxt_ingress_ready ), + + .fetch_cxt_egress_valid ( SQ_fetch_cxt_egress_valid ), + .fetch_cxt_egress_head ( SQ_fetch_cxt_egress_head ), + .fetch_cxt_egress_data ( SQ_fetch_cxt_egress_data ), + .fetch_cxt_egress_start ( SQ_fetch_cxt_egress_start ), + .fetch_cxt_egress_last ( SQ_fetch_cxt_egress_last ), + .fetch_cxt_egress_ready ( SQ_fetch_cxt_egress_ready ), + + .fetch_mr_ingress_valid ( SQ_fetch_mr_ingress_valid ), + .fetch_mr_ingress_head ( SQ_fetch_mr_ingress_head ), + .fetch_mr_ingress_data ( SQ_fetch_mr_ingress_data ), + .fetch_mr_ingress_start ( SQ_fetch_mr_ingress_start ), + .fetch_mr_ingress_last ( SQ_fetch_mr_ingress_last ), + .fetch_mr_ingress_ready ( SQ_fetch_mr_ingress_ready ), + + .fetch_mr_egress_valid ( SQ_fetch_mr_egress_valid ), + .fetch_mr_egress_head ( SQ_fetch_mr_egress_head ), + .fetch_mr_egress_data ( SQ_fetch_mr_egress_data ), + .fetch_mr_egress_start ( SQ_fetch_mr_egress_start ), + .fetch_mr_egress_last ( SQ_fetch_mr_egress_last ), + .fetch_mr_egress_ready ( SQ_fetch_mr_egress_ready ), + + .SQ_dma_rd_req_valid ( SQ_dma_rd_req_valid ), + .SQ_dma_rd_req_head ( SQ_dma_rd_req_head ), + .SQ_dma_rd_req_data ( SQ_dma_rd_req_data ), + .SQ_dma_rd_req_last ( SQ_dma_rd_req_last ), + .SQ_dma_rd_req_ready ( SQ_dma_rd_req_ready ), + + .SQ_dma_rd_rsp_valid ( SQ_dma_rd_rsp_valid ), + .SQ_dma_rd_rsp_head ( SQ_dma_rd_rsp_head ), + .SQ_dma_rd_rsp_data ( SQ_dma_rd_rsp_data ), + .SQ_dma_rd_rsp_last ( SQ_dma_rd_rsp_last ), + .SQ_dma_rd_rsp_ready ( SQ_dma_rd_rsp_ready ), + + .sub_wqe_valid ( sub_wqe_valid ), + .sub_wqe_meta ( sub_wqe_meta ), + .sub_wqe_ready ( sub_wqe_ready ), + + .insert_req_valid ( insert_req_valid ), + .insert_req_start ( insert_req_start ), + .insert_req_last ( insert_req_last ), + .insert_req_head ( insert_req_head ), + .insert_req_data ( insert_req_data ), + .insert_req_ready ( insert_req_ready ), + + .insert_resp_valid ( insert_resp_valid ), + .insert_resp_data ( insert_resp_data ) +); + +RQMgt +#( + .CACHE_SLOT_NUM ( `RQ_CACHE_SLOT_NUM ), + .CACHE_CELL_NUM ( `RQ_CACHE_CELL_NUM ), + + .INGRESS_CXT_HEAD_WIDTH ( 128 ), + .INGRESS_CXT_DATA_WIDTH ( 256 ), + .EGRESS_CXT_HEAD_WIDTH ( 128 ), + .EGRESS_CXT_DATA_WIDTH ( 256 ), + + .INGRESS_MR_HEAD_WIDTH ( 128 ), + .INGRESS_MR_DATA_WIDTH ( 256 ), + .EGRESS_MR_HEAD_WIDTH ( 128 ), + .EGRESS_MR_DATA_WIDTH ( 256 ) +) +RQMgt_Inst( + .clk ( clk ), + .rst ( rst ), + + .wqe_req_valid ( RQ_wqe_req_valid ), + .wqe_req_head ( RQ_wqe_req_head ), + .wqe_req_start ( RQ_wqe_req_start ), + .wqe_req_last ( RQ_wqe_req_last ), + .wqe_req_ready ( RQ_wqe_req_ready ), + + .wqe_resp_valid ( RQ_wqe_resp_valid ), + .wqe_resp_head ( RQ_wqe_resp_head ), + .wqe_resp_data ( RQ_wqe_resp_data ), + .wqe_resp_start ( RQ_wqe_resp_start ), + .wqe_resp_last ( RQ_wqe_resp_last ), + .wqe_resp_ready ( RQ_wqe_resp_ready ), + + .RQ_cache_offset_wen ( RQ_cache_offset_wen ), + .RQ_cache_offset_addr ( RQ_cache_offset_addr ), + .RQ_cache_offset_din ( RQ_cache_offset_din ), + .RQ_cache_offset_dout ( RQ_cache_offset_dout ), + + .RQ_offset_wen ( RQ_offset_wen ), + .RQ_offset_addr ( RQ_offset_addr ), + .RQ_offset_din ( RQ_offset_din ), + .RQ_offset_dout ( RQ_offset_dout ), + + .RQ_cache_owned_wen ( RQ_cache_owned_wen ), + .RQ_cache_owned_addr ( RQ_cache_owned_addr ), + .RQ_cache_owned_din ( RQ_cache_owned_din ), + .RQ_cache_owned_dout ( RQ_cache_owned_dout ), + + .fetch_mr_ingress_valid ( RQ_fetch_mr_ingress_valid ), + .fetch_mr_ingress_head ( RQ_fetch_mr_ingress_head ), + .fetch_mr_ingress_data ( RQ_fetch_mr_ingress_data ), + .fetch_mr_ingress_start ( RQ_fetch_mr_ingress_start ), + .fetch_mr_ingress_last ( RQ_fetch_mr_ingress_last ), + .fetch_mr_ingress_ready ( RQ_fetch_mr_ingress_ready ), + + .fetch_mr_egress_valid ( RQ_fetch_mr_egress_valid ), + .fetch_mr_egress_head ( RQ_fetch_mr_egress_head ), + .fetch_mr_egress_data ( RQ_fetch_mr_egress_data ), + .fetch_mr_egress_start ( RQ_fetch_mr_egress_start ), + .fetch_mr_egress_last ( RQ_fetch_mr_egress_last ), + .fetch_mr_egress_ready ( RQ_fetch_mr_egress_ready ), + + .RQ_dma_rd_req_valid ( RQ_dma_rd_req_valid ), + .RQ_dma_rd_req_head ( RQ_dma_rd_req_head ), + .RQ_dma_rd_req_data ( RQ_dma_rd_req_data ), + .RQ_dma_rd_req_last ( RQ_dma_rd_req_last ), + .RQ_dma_rd_req_ready ( RQ_dma_rd_req_ready ), + + .RQ_dma_rd_rsp_valid ( RQ_dma_rd_rsp_valid ), + .RQ_dma_rd_rsp_head ( RQ_dma_rd_rsp_head ), + .RQ_dma_rd_rsp_data ( RQ_dma_rd_rsp_data ), + .RQ_dma_rd_rsp_last ( RQ_dma_rd_rsp_last ), + .RQ_dma_rd_rsp_ready ( RQ_dma_rd_rsp_ready ) +); + +CQMgt CQMgt_Inst( + .clk ( clk ), + .rst ( rst ), + + .TX_REQ_cq_req_valid ( TX_REQ_cq_req_valid ), + .TX_REQ_cq_req_head ( TX_REQ_cq_req_head ), + .TX_REQ_cq_req_ready ( TX_REQ_cq_req_ready ), + + .TX_REQ_cq_resp_valid ( TX_REQ_cq_resp_valid ), + .TX_REQ_cq_resp_head ( TX_REQ_cq_resp_head ), + .TX_REQ_cq_resp_ready ( TX_REQ_cq_resp_ready ), + + .RX_REQ_cq_req_valid ( RX_REQ_cq_req_valid ), + .RX_REQ_cq_req_head ( RX_REQ_cq_req_head ), + .RX_REQ_cq_req_ready ( RX_REQ_cq_req_ready ), + + .RX_REQ_cq_resp_valid ( RX_REQ_cq_resp_valid ), + .RX_REQ_cq_resp_head ( RX_REQ_cq_resp_head ), + .RX_REQ_cq_resp_ready ( RX_REQ_cq_resp_ready ), + + .RX_RESP_cq_req_valid ( RX_RESP_cq_req_valid ), + .RX_RESP_cq_req_head ( RX_RESP_cq_req_head ), + .RX_RESP_cq_req_ready ( RX_RESP_cq_req_ready ), + + .RX_RESP_cq_resp_valid ( RX_RESP_cq_resp_valid ), + .RX_RESP_cq_resp_head ( RX_RESP_cq_resp_head ), + .RX_RESP_cq_resp_ready ( RX_RESP_cq_resp_ready ) +); + +EQMgt EQMgt_Inst( + .clk ( clk ), + .rst ( rst ), + + .TX_REQ_eq_req_valid ( TX_REQ_eq_req_valid ), + .TX_REQ_eq_req_head ( TX_REQ_eq_req_head ), + .TX_REQ_eq_req_ready ( TX_REQ_eq_req_ready ), + + .TX_REQ_eq_resp_valid ( TX_REQ_eq_resp_valid ), + .TX_REQ_eq_resp_head ( TX_REQ_eq_resp_head ), + .TX_REQ_eq_resp_ready ( TX_REQ_eq_resp_ready ), + + .RX_REQ_eq_req_valid ( RX_REQ_eq_req_valid ), + .RX_REQ_eq_req_head ( RX_REQ_eq_req_head ), + .RX_REQ_eq_req_ready ( RX_REQ_eq_req_ready ), + + .RX_REQ_eq_resp_valid ( RX_REQ_eq_resp_valid ), + .RX_REQ_eq_resp_head ( RX_REQ_eq_resp_head ), + .RX_REQ_eq_resp_ready ( RX_REQ_eq_resp_ready ), + + .RX_RESP_eq_req_valid ( RX_RESP_eq_req_valid ), + .RX_RESP_eq_req_head ( RX_RESP_eq_req_head ), + .RX_RESP_eq_req_ready ( RX_RESP_eq_req_ready ), + + .RX_RESP_eq_resp_valid ( RX_RESP_eq_resp_valid ), + .RX_RESP_eq_resp_head ( RX_RESP_eq_resp_head ), + .RX_RESP_eq_resp_ready ( RX_RESP_eq_resp_ready ) +); +/*------------------------------------------- Submodules Instatiation : End -----------------------------------------*/ + +/*------------------------------------------- State Machine Definition : Begin --------------------------------------*/ +/*------------------------------------------- State Machine Definition : End ----------------------------------------*/ + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ +/*------------------------------------------- Variables Decode : End ----------------------------------------------*/ + +/*------------------------------------------- Local Macros Undef : Begin --------------------------------------------*/ + +/*------------------------------------------- Local Macros Undef : End ----------------------------------------------*/ + +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/QueueSubsystem/RQMgt/RQMetaProc.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/QueueSubsystem/RQMgt/RQMetaProc.v new file mode 100644 index 0000000000000000000000000000000000000000..ce5d14512f46d24c0b6704f74df8dcf62679c0ed --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/QueueSubsystem/RQMgt/RQMetaProc.v @@ -0,0 +1,334 @@ +/*------------------------------------------- Module Description : Begin ---------------------------------------------- +Name: RQMetaProc +Author: YangFan +Function: Fetch RQ Memory Region. +--------------------------------------------- Module Decription : End -----------------------------------------------*/ + +/*------------------------------------------- Timescale Definition : Begin ------------------------------------------*/ +`timescale 1ns / 1ps +/*------------------------------------------- Timescale Definition : End --------------------------------------------*/ + +/*------------------------------------------- Included Files : Begin ------------------------------------------------*/ +`include "protocol_engine_def.vh" +/*------------------------------------------- Included Files : End --------------------------------------------------*/ + +/*------------------------------------------- Input/Output Definition : Begin ---------------------------------------*/ +module RQMetaProc +#( + parameter INGRESS_CXT_HEAD_WIDTH = 128, + parameter INGRESS_CXT_DATA_WIDTH = 256, + parameter EGRESS_CXT_HEAD_WIDTH = 128, + parameter EGRESS_CXT_DATA_WIDTH = 256, + + parameter INGRESS_MR_HEAD_WIDTH = 128, + parameter INGRESS_MR_DATA_WIDTH = 256, + parameter EGRESS_MR_HEAD_WIDTH = 128, + parameter EGRESS_MR_DATA_WIDTH = 256 + + +) +( + input wire clk, + input wire rst, + +//Interface with ReqRecvCore + input wire wqe_req_valid, + input wire [`WQE_META_WIDTH - 1 : 0] wqe_req_head, + input wire wqe_req_start, + input wire wqe_req_last, + output wire wqe_req_ready, + +//Interface with RQOffsetRecord + output wire rq_offset_wen, + output wire [23:0] rq_offset_din, + output wire [`QP_NUM_LOG - 1 : 0] rq_offset_addr, + input wire [23:0] rq_offset_dout, + +//Interface with MRMgt + output wire fetch_mr_ingress_valid, + output wire [`RQ_OOO_MR_INGRESS_HEAD_WIDTH - 1 : 0] fetch_mr_ingress_head, + output wire [`RQ_OOO_MR_INGRESS_DATA_WIDTH - 1 : 0] fetch_mr_ingress_data, + output wire fetch_mr_ingress_start, + output wire fetch_mr_ingress_last, + input wire fetch_mr_ingress_ready, + + input wire fetch_mr_egress_valid, + input wire [`RQ_OOO_MR_EGRESS_HEAD_WIDTH - 1 : 0] fetch_mr_egress_head, + input wire [`RQ_OOO_MR_EGRESS_DATA_WIDTH - 1 : 0] fetch_mr_egress_data, + input wire fetch_mr_egress_start, + input wire fetch_mr_egress_last, + output wire fetch_mr_egress_ready, + +//Interface with WQEFetch + output wire rq_meta_valid, + output wire [`SQ_META_WIDTH - 1 : 0] rq_meta_data, + input wire rq_meta_ready + +); +/*------------------------------------------- Input/Output Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Macros Definition : Begin ---------------------------------------*/ +`define LOCAL_QPN_OFFSET 23:0 +`define RQ_ENTRY_SZ_LOG_OFFSET 31:24 +`define RQ_LKEY_OFFSET 63:32 +`define RQ_LENGTH_OFFSET 95:64 +`define QP_PD_OFFSET 127:96 +/*------------------------------------------- Local Macros Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Variables Definition : Begin ------------------------------------*/ +wire [`INGRESS_COMMON_HEAD_WIDTH - 1 : 0] ingress_common_head; +wire [`MAX_OOO_SLOT_NUM_LOG - 1 :0] ingress_slot_count; + +reg [`WQE_META_WIDTH - 1 : 0] wqe_req_head_diff; + +wire [15:0] local_qpn; +wire [7:0] rq_entry_sz_log; +wire [31:0] rq_length; +wire [31:0] rq_lkey; +wire [31:0] qp_pd; + +reg [31:0] mr_flags; +reg [3:0] mr_flag_sw_owns; +reg mr_flag_absolute_addr; +reg mr_flag_relative_addr; +reg mr_flag_mio; +reg mr_flag_bind_enable; +reg mr_flag_physical; +reg mr_flag_region; +reg mr_flag_on_demand; +reg mr_flag_zero_based; +reg mr_flag_mw_bind; +reg mr_remote_read; +reg mr_remote_write; +reg mr_local_write; + +wire [31:0] mr_length; +wire [63:0] mr_laddr; +wire [31:0] mr_lkey; +wire [31:0] mr_pd; +/*------------------------------------------- Local Variables Definition : End --------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : Begin ---------------------------------------*/ +/*------------------------------------------- Submodules Instatiation : End -----------------------------------------*/ + +/*------------------------------------------- State Machine Definition : Begin --------------------------------------*/ +reg [1:0] cur_state; +reg [1:0] next_state; + +parameter [1:0] IDLE_s = 2'd1, + STAGED_s = 2'd2, + FETCH_MR_s = 2'd3; + +always @(posedge clk or posedge rst) begin + if(rst) begin + cur_state <= IDLE_s; + end + else begin + cur_state <= next_state; + end +end + +always @(*) begin + case(cur_state) + IDLE_s: if(wqe_req_valid) begin + next_state = FETCH_MR_s; + end + else begin + next_state = IDLE_s; + end + STAGED_s: next_state = FETCH_MR_s; + FETCH_MR_s: if(fetch_mr_ingress_valid && fetch_mr_ingress_ready) begin + next_state = IDLE_s; + end + else begin + next_state = FETCH_MR_s; + end + default: next_state = IDLE_s; + endcase +end +/*------------------------------------------- State Machine Definition : End ----------------------------------------*/ + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ +//-- wqe_req_head_diff -- +always @(posedge clk or posedge rst) begin + if (rst) begin + wqe_req_head_diff <= 'd0; + end + else if (cur_state == IDLE_s && wqe_req_valid) begin + wqe_req_head_diff <= wqe_req_head; + end + else begin + wqe_req_head_diff <= wqe_req_head_diff; + end +end + +//-- local_qpn -- +//-- rq_entry_sz_log -- +//-- rq_length -- +//-- rq_lkey -- +//-- qp_pd -- +assign local_qpn = wqe_req_head_diff[`LOCAL_QPN_OFFSET]; +assign rq_entry_sz_log = wqe_req_head_diff[`RQ_ENTRY_SZ_LOG_OFFSET]; +assign rq_length = wqe_req_head_diff[`RQ_LENGTH_OFFSET]; +assign rq_lkey = wqe_req_head_diff[`RQ_LKEY_OFFSET]; +assign qp_pd = wqe_req_head_diff[`QP_PD_OFFSET]; + +//-- ingress_common_head -- +//-- ingress_slot_count -- +assign ingress_slot_count = (cur_state == FETCH_MR_s) ? 'd1 : 'd0; +assign ingress_common_head = (cur_state == FETCH_MR_s) ? {`NO_BYPASS, ingress_slot_count, local_qpn[`MAX_QP_NUM_LOG - 1 : 0]} : 'd0; + +//-- mr_length -- +//-- mr_laddr -- +//-- mr_lkey -- +//-- mr_pd -- +assign mr_length = (cur_state == FETCH_MR_s && (rq_offset_dout * 16) + `RQ_PREFETCH_LENGTH > rq_length) ? (rq_length - (rq_offset_dout * 16)) : + (cur_state == FETCH_MR_s && (rq_offset_dout * 16) + `RQ_PREFETCH_LENGTH <= rq_length) ? `RQ_PREFETCH_LENGTH : 'd0; +assign mr_laddr = (cur_state == FETCH_MR_s) ? (rq_offset_dout * 16) : 'd0; +assign mr_lkey = rq_lkey; +assign mr_pd = qp_pd; + +//-- mr_flag_sw_owns -- +//-- mr_flag_absolute_addr -- +//-- mr_flag_relative_addr -- +//-- mr_flag_mio -- +//-- mr_flag_bind_enable -- +//-- mr_flag_physical -- +//-- mr_flag_on_demand -- +//-- mr_flag_zero_based -- +//-- mr_flag_mw_bind -- +//-- mr_remote_read -- +//-- mr_remote_write -- +//-- mr_local_write -- +always @(*) begin + if(rst) begin + mr_flag_sw_owns = 'd0; + mr_flag_absolute_addr = 'd0; + mr_flag_relative_addr = 'd0; + mr_flag_mio = 'd0; + mr_flag_bind_enable = 'd0; + mr_flag_physical = 'd0; + mr_flag_region = 'd0; + mr_flag_on_demand = 'd0; + mr_flag_zero_based = 'd0; + mr_flag_mw_bind = 'd0; + mr_remote_read = 'd0; + mr_remote_write = 'd0; + mr_local_write = 'd0; + end + else if(cur_state == FETCH_MR_s) begin + mr_flag_sw_owns = 'd0; + mr_flag_absolute_addr = 'd0; + mr_flag_relative_addr = 'd1; + mr_flag_mio = 'd0; + mr_flag_bind_enable = 'd0; + mr_flag_physical = 'd0; + mr_flag_region = 'd0; + mr_flag_on_demand = 'd0; + mr_flag_zero_based = 'd0; + mr_flag_mw_bind = 'd0; + mr_remote_read = 'd0; + mr_remote_write = 'd0; + mr_local_write = 'd0; + end + else begin + mr_flag_sw_owns = 'd0; + mr_flag_absolute_addr = 'd0; + mr_flag_relative_addr = 'd1; + mr_flag_mio = 'd0; + mr_flag_bind_enable = 'd0; + mr_flag_physical = 'd0; + mr_flag_region = 'd0; + mr_flag_on_demand = 'd0; + mr_flag_zero_based = 'd0; + mr_flag_mw_bind = 'd0; + mr_remote_read = 'd0; + mr_remote_write = 'd0; + mr_local_write = 'd0; + end +end + +//-- mr_flags -- +always @(*) begin + if(rst) begin + mr_flags = 'd0; + end + else if(cur_state == FETCH_MR_s) begin + mr_flags = { + mr_flag_sw_owns, + mr_flag_absolute_addr, + mr_flag_relative_addr, + 8'd0, + mr_flag_mio, + 1'd0, + mr_flag_bind_enable, + 5'd0, + mr_flag_physical, + mr_flag_region, + 1'd0, + mr_flag_on_demand, + mr_flag_zero_based, + mr_flag_mw_bind, + mr_remote_read, + mr_remote_write, + mr_local_write + }; + end + else begin + mr_flags = 'd0; + end +end + +//-- wqe_req_ready -- +assign wqe_req_ready = (cur_state == IDLE_s) ? 'd1 : 'd0; + +//-- rq_offset_wen -- +assign rq_offset_wen = 'd0; + +//-- rq_offset_din -- +assign rq_offset_din = 'd0; + +//-- rq_offset_addr -- +assign rq_offset_addr = (cur_state == IDLE_s) ? wqe_req_head[`LOCAL_QPN_OFFSET] : local_qpn; + +//-- fetch_mr_ingress_valid -- +//-- fetch_mr_ingress_head -- +//-- fetch_mr_ingress_data -- +//-- fetch_mr_ingress_start -- +//-- fetch_mr_ingress_last -- +assign fetch_mr_ingress_valid = (cur_state == FETCH_MR_s) ? 'd1 : 'd0; +assign fetch_mr_ingress_head = (cur_state == FETCH_MR_s) ? {mr_length, mr_laddr, mr_lkey, mr_pd, mr_flags, ingress_common_head} : 'd0; +assign fetch_mr_ingress_data = (cur_state == FETCH_MR_s) ? wqe_req_head_diff : 'd0; +assign fetch_mr_ingress_start = (cur_state == FETCH_MR_s) ? 'd1 : 'd0; +assign fetch_mr_ingress_last = (cur_state == FETCH_MR_s) ? 'd1 : 'd0; + +//-- fetch_mr_egress_ready -- +assign fetch_mr_egress_ready = rq_meta_ready; + +//-- rq_meta_valid -- +//-- rq_meta_data -- +assign rq_meta_valid = fetch_mr_egress_valid; +assign rq_meta_data = { fetch_mr_egress_head[`MR_RESP_HEAD_WIDTH + `EGRESS_COMMON_HEAD_WIDTH - 1 : `EGRESS_COMMON_HEAD_WIDTH], + 32'd0, + 32'd0, + 48'd0, + 48'd0, + qp_pd, + rq_length, + 16'd0, + rq_entry_sz_log, + 8'd0, + 16'd0, + local_qpn + }; +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ + +/*------------------------------------------- Local Macros Undef : Begin --------------------------------------------*/ +`undef LOCAL_QPN_OFFSET +`undef RQ_ENTRY_SZ_LOG_OFFSET +`undef RQ_LKEY_OFFSET +`undef RQ_LENGTH_OFFSET +`undef QP_PD_OFFSET +/*------------------------------------------- Local Macros Undef : End ----------------------------------------------*/ + +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/QueueSubsystem/RQMgt/RQMgt.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/QueueSubsystem/RQMgt/RQMgt.v new file mode 100644 index 0000000000000000000000000000000000000000..69a77787ffefac583c0ff2a789e892ea89464685 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/QueueSubsystem/RQMgt/RQMgt.v @@ -0,0 +1,309 @@ +/*------------------------------------------- Module Description : Begin ---------------------------------------------- +Name: RQMgt +Author: YangFan +Function: Manage Recv Queue. +--------------------------------------------- Module Decription : End -----------------------------------------------*/ + +/*------------------------------------------- Timescale Definition : Begin ------------------------------------------*/ +`timescale 1ns / 1ps +/*------------------------------------------- Timescale Definition : End --------------------------------------------*/ + +/*------------------------------------------- Included Files : Begin ------------------------------------------------*/ +`include "protocol_engine_def.vh" +/*------------------------------------------- Included Files : End --------------------------------------------------*/ + +/*------------------------------------------- Input/Output Definition : Begin ---------------------------------------*/ +module RQMgt +#( + parameter CACHE_SLOT_NUM = 256, + parameter CACHE_SLOT_NUM_LOG = log2b(CACHE_SLOT_NUM - 1), + + parameter CACHE_CELL_NUM = 256, + parameter CACHE_CELL_NUM_LOG = log2b(CACHE_CELL_NUM - 1), + + parameter INGRESS_CXT_HEAD_WIDTH = 128, + parameter INGRESS_CXT_DATA_WIDTH = 256, + parameter EGRESS_CXT_HEAD_WIDTH = 128, + parameter EGRESS_CXT_DATA_WIDTH = 256, + + parameter INGRESS_MR_HEAD_WIDTH = 128, + parameter INGRESS_MR_DATA_WIDTH = 256, + parameter EGRESS_MR_HEAD_WIDTH = 128, + parameter EGRESS_MR_DATA_WIDTH = 256 +) +( + input wire clk, + input wire rst, + +//Interface with RDMACore/ReqRecvCore + input wire wqe_req_valid, + input wire [`WQE_META_WIDTH - 1 : 0] wqe_req_head, + input wire wqe_req_start, + input wire wqe_req_last, + output wire wqe_req_ready, + + output wire wqe_resp_valid, + output wire [`WQE_META_WIDTH - 1 : 0] wqe_resp_head, + output wire [`WQE_SEG_WIDTH - 1 : 0] wqe_resp_data, + output wire wqe_resp_start, + output wire wqe_resp_last, + input wire wqe_resp_ready, + + input wire RQ_cache_offset_wen, + input wire [`QP_NUM_LOG - 1 : 0] RQ_cache_offset_addr, + input wire [`RQ_CACHE_SLOT_NUM_LOG - 1:0] RQ_cache_offset_din, + output wire [`RQ_CACHE_SLOT_NUM_LOG - 1:0] RQ_cache_offset_dout, + + input wire RQ_offset_wen, + input wire [`QP_NUM_LOG - 1 : 0] RQ_offset_addr, + input wire [23:0] RQ_offset_din, + output wire [23:0] RQ_offset_dout, + + input wire RQ_cache_owned_wen, + input wire [`RQ_CACHE_CELL_NUM_LOG - 1 : 0] RQ_cache_owned_addr, + input wire [`QP_NUM_LOG - 1 : 0] RQ_cache_owned_din, + output wire [`QP_NUM_LOG - 1 : 0] RQ_cache_owned_dout, + +//Interface with MRMgt + output wire fetch_mr_ingress_valid, + output wire [`RQ_OOO_MR_INGRESS_HEAD_WIDTH - 1 : 0] fetch_mr_ingress_head, + output wire [`RQ_OOO_MR_INGRESS_DATA_WIDTH - 1 : 0] fetch_mr_ingress_data, + output wire fetch_mr_ingress_start, + output wire fetch_mr_ingress_last, + input wire fetch_mr_ingress_ready, + + input wire fetch_mr_egress_valid, + input wire [`RQ_OOO_MR_EGRESS_HEAD_WIDTH - 1 : 0] fetch_mr_egress_head, + input wire [`RQ_OOO_MR_EGRESS_DATA_WIDTH - 1 : 0] fetch_mr_egress_data, + input wire fetch_mr_egress_start, + input wire fetch_mr_egress_last, + output wire fetch_mr_egress_ready, + +//Interface with DMA Read Channel + output wire RQ_dma_rd_req_valid, + output wire [`DMA_HEAD_WIDTH - 1 : 0] RQ_dma_rd_req_head, + output wire [`DMA_DATA_WIDTH - 1 : 0] RQ_dma_rd_req_data, + output wire RQ_dma_rd_req_last, + input wire RQ_dma_rd_req_ready, + + input wire RQ_dma_rd_rsp_valid, + input wire [`DMA_HEAD_WIDTH - 1 : 0] RQ_dma_rd_rsp_head, + input wire [`DMA_DATA_WIDTH - 1 : 0] RQ_dma_rd_rsp_data, + input wire RQ_dma_rd_rsp_last, + output wire RQ_dma_rd_rsp_ready +); +/*------------------------------------------- Input/Output Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Macros Definition : Begin ---------------------------------------*/ +/*------------------------------------------- Local Macros Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Variables Definition : Begin ------------------------------------*/ +wire [0:0] rq_offset_record_wea; +wire [`QP_NUM_LOG - 1 : 0] rq_offset_record_addra; +wire [23:0] rq_offset_record_dina; +wire [23:0] rq_offset_record_douta; + +wire cache_owned_wea; +wire [CACHE_CELL_NUM_LOG - 1 : 0] cache_owned_addra; +wire [`QP_NUM_LOG - 1 : 0] cache_owned_dina; +wire [`QP_NUM_LOG - 1 : 0] cache_owned_douta; + +wire cache_offset_wea; +wire [`QP_NUM_LOG - 1 : 0] cache_offset_addra; +wire [`SQ_CACHE_SLOT_NUM_LOG - 1:0] cache_offset_dina; +wire [`SQ_CACHE_SLOT_NUM_LOG - 1:0] cache_offset_douta; + +wire cache_buffer_wea; +wire [log2b(`RQ_CACHE_SLOT_NUM * `RQ_CACHE_CELL_NUM - 1) - 1 : 0] cache_buffer_addra; +wire [`WQE_SEG_WIDTH - 1 : 0] cache_buffer_dina; + +wire [log2b(`SQ_CACHE_SLOT_NUM * `SQ_CACHE_CELL_NUM - 1) - 1 : 0] cache_buffer_addrb; +wire [`WQE_SEG_WIDTH - 1 : 0] cache_buffer_doutb; + +wire wqe_valid; +wire [`WQE_META_WIDTH - 1 : 0] wqe_head; +wire [`WQE_SEG_WIDTH - 1 : 0] wqe_data; +wire wqe_start; +wire wqe_last; +wire wqe_ready; + +wire rq_meta_valid; +wire [`SQ_META_WIDTH - 1 : 0] rq_meta_data; +wire rq_meta_ready; +/*------------------------------------------- Local Variables Definition : End --------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : Begin ---------------------------------------*/ +RQMetaProc +#( + .INGRESS_CXT_HEAD_WIDTH ( INGRESS_CXT_HEAD_WIDTH ), + .INGRESS_CXT_DATA_WIDTH ( INGRESS_CXT_DATA_WIDTH ), + .EGRESS_CXT_HEAD_WIDTH ( EGRESS_CXT_HEAD_WIDTH ), + .EGRESS_CXT_DATA_WIDTH ( EGRESS_CXT_DATA_WIDTH ), + + .INGRESS_MR_HEAD_WIDTH ( INGRESS_MR_HEAD_WIDTH ), + .INGRESS_MR_DATA_WIDTH ( INGRESS_MR_DATA_WIDTH ), + .EGRESS_MR_HEAD_WIDTH ( EGRESS_MR_HEAD_WIDTH ), + .EGRESS_MR_DATA_WIDTH ( EGRESS_MR_DATA_WIDTH ) +) +RQMetaProc_Inst +( + .clk ( clk ), + .rst ( rst ), + + .wqe_req_valid ( wqe_req_valid ), + .wqe_req_head ( wqe_req_head ), + .wqe_req_start ( wqe_req_start ), + .wqe_req_last ( wqe_req_last ), + .wqe_req_ready ( wqe_req_ready ), + + .rq_offset_wen ( rq_offset_record_wea ), + .rq_offset_din ( rq_offset_record_dina ), + .rq_offset_addr ( rq_offset_record_addra ), + .rq_offset_dout ( rq_offset_record_douta ), + + .fetch_mr_ingress_valid ( fetch_mr_ingress_valid ), + .fetch_mr_ingress_head ( fetch_mr_ingress_head ), + .fetch_mr_ingress_data ( fetch_mr_ingress_data ), + .fetch_mr_ingress_start ( fetch_mr_ingress_start ), + .fetch_mr_ingress_last ( fetch_mr_ingress_last ), + .fetch_mr_ingress_ready ( fetch_mr_ingress_ready ), + + .fetch_mr_egress_valid ( fetch_mr_egress_valid ), + .fetch_mr_egress_head ( fetch_mr_egress_head ), + .fetch_mr_egress_data ( fetch_mr_egress_data ), + .fetch_mr_egress_start ( fetch_mr_egress_start ), + .fetch_mr_egress_last ( fetch_mr_egress_last ), + .fetch_mr_egress_ready ( fetch_mr_egress_ready ), + + .rq_meta_valid ( rq_meta_valid ), + .rq_meta_data ( rq_meta_data ), + .rq_meta_ready ( rq_meta_ready ) + +); + +WQECache +#( + .CACHE_SLOT_NUM ( CACHE_SLOT_NUM ), + .CACHE_SLOT_NUM_LOG ( CACHE_SLOT_NUM_LOG ), + + .CACHE_CELL_NUM ( CACHE_CELL_NUM ), + .CACHE_CELL_NUM_LOG ( CACHE_CELL_NUM_LOG ) +) +RQCache_Inst +( + .clk ( clk ), + .rst ( rst ), + + .cache_buffer_wea ( cache_buffer_wea ), + .cache_buffer_addra ( cache_buffer_addra ), + .cache_buffer_dina ( cache_buffer_dina ), + + .cache_buffer_addrb ( cache_buffer_addrb ), + .cache_buffer_doutb ( cache_buffer_doutb ), + + .cache_owned_wea ( cache_owned_wea ), + .cache_owned_addra ( cache_owned_addra ), + .cache_owned_dina ( cache_owned_dina ), + .cache_owned_douta ( cache_owned_douta ), + + .cache_owned_web ( RQ_cache_owned_wen ), + .cache_owned_addrb ( RQ_cache_owned_addr ), + .cache_owned_dinb ( RQ_cache_owned_din ), + .cache_owned_doutb ( RQ_cache_owned_dout ), + + .cache_offset_wea ( cache_offset_wea ), + .cache_offset_addra ( cache_offset_addra ), + .cache_offset_dina ( cache_offset_dina ), + .cache_offset_douta ( cache_offset_douta ), + + .cache_offset_web ( RQ_cache_offset_wen ), + .cache_offset_addrb ( RQ_cache_offset_addr ), + .cache_offset_dinb ( RQ_cache_offset_din ), + .cache_offset_doutb ( RQ_cache_offset_dout ) +); + +WQEFetch +#( + .CACHE_SLOT_NUM ( CACHE_SLOT_NUM ), + .CACHE_SLOT_NUM_LOG ( CACHE_SLOT_NUM_LOG ), + + .CACHE_CELL_NUM ( CACHE_CELL_NUM ), + .CACHE_CELL_NUM_LOG ( CACHE_CELL_NUM_LOG ) +) +WQEFetch_Inst +( + .clk ( clk ), + .rst ( rst ), + + .meta_valid ( rq_meta_valid ), + .meta_data ( rq_meta_data ), + .meta_ready ( rq_meta_ready ), + + .cache_buffer_wea ( cache_buffer_wea ), + .cache_buffer_addra ( cache_buffer_addra ), + .cache_buffer_dina ( cache_buffer_dina ), + + .cache_buffer_addrb ( cache_buffer_addrb ), + .cache_buffer_doutb ( cache_buffer_doutb ), + + .cache_owned_wen ( cache_owned_wea ), + .cache_owned_addr ( cache_owned_addra ), + .cache_owned_din ( cache_owned_dina ), + .cache_owned_dout ( cache_owned_douta ), + + .dma_rd_req_valid ( RQ_dma_rd_req_valid ), + .dma_rd_req_head ( RQ_dma_rd_req_head ), + .dma_rd_req_data ( RQ_dma_rd_req_data ), + .dma_rd_req_last ( RQ_dma_rd_req_last ), + .dma_rd_req_ready ( RQ_dma_rd_req_ready ), + + .dma_rd_rsp_valid ( RQ_dma_rd_rsp_valid ), + .dma_rd_rsp_head ( RQ_dma_rd_rsp_head ), + .dma_rd_rsp_data ( RQ_dma_rd_rsp_data ), + .dma_rd_rsp_last ( RQ_dma_rd_rsp_last ), + .dma_rd_rsp_ready ( RQ_dma_rd_rsp_ready ), + + .cache_offset_wen ( cache_offset_wea ), + .cache_offset_addr ( cache_offset_addra ), + .cache_offset_din ( cache_offset_dina ), + .cache_offset_dout ( cache_offset_douta ), + + .wqe_valid ( wqe_resp_valid ), + .wqe_head ( wqe_resp_head ), + .wqe_data ( wqe_resp_data ), + .wqe_start ( wqe_resp_start ), + .wqe_last ( wqe_resp_last ), + .wqe_ready ( wqe_resp_ready ) +); + +SRAM_TDP_Template #( + .RAM_WIDTH ( 24 ), + .RAM_DEPTH ( `QP_NUM ) +) +RQOffsetRecordTable +( + .clk ( clk ), + .rst ( rst ), + + .wea ( rq_offset_record_wea ), + .addra ( rq_offset_record_addra ), + .dina ( rq_offset_record_dina ), + .douta ( rq_offset_record_douta ), + + .web ( RQ_offset_wen ), + .addrb ( RQ_offset_addr ), + .dinb ( RQ_offset_din ), + .doutb ( RQ_offset_dout ) +); +/*------------------------------------------- Submodules Instatiation : End -----------------------------------------*/ + +/*------------------------------------------- State Machine Definition : Begin --------------------------------------*/ +/*------------------------------------------- State Machine Definition : End ----------------------------------------*/ + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ + +/*------------------------------------------- Local Macros Undef : Begin --------------------------------------------*/ +/*------------------------------------------- Local Macros Undef : End ----------------------------------------------*/ + +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/QueueSubsystem/SQMgt/DBProc.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/QueueSubsystem/SQMgt/DBProc.v new file mode 100644 index 0000000000000000000000000000000000000000..d1b2d1141cb9950d13511edd94d70443d6819bd4 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/QueueSubsystem/SQMgt/DBProc.v @@ -0,0 +1,115 @@ +/*------------------------------------------- Module Description : Begin ---------------------------------------------- +Name: DBProc +Author: YangFan +Function: Parse doorbell and update SQ Head. +--------------------------------------------- Module Decription : End -----------------------------------------------*/ + +/*------------------------------------------- Timescale Definition : Begin ------------------------------------------*/ +`timescale 1ns / 1ps +/*------------------------------------------- Timescale Definition : End --------------------------------------------*/ + +/*------------------------------------------- Included Files : Begin ------------------------------------------------*/ +`include "protocol_engine_def.vh" +/*------------------------------------------- Included Files : End --------------------------------------------------*/ + +/*------------------------------------------- Input/Output Definition : Begin ---------------------------------------*/ +module DBProc +( + input wire clk, + input wire rst, + +//Interface with PIO + input wire db_fifo_empty, + input wire [63:0] db_fifo_dout, + output wire db_fifo_rd_en, + +//Interface with QPNArbiter + output wire qpn_fifo_valid, + output wire [23:0] qpn_fifo_data, + input wire qpn_fifo_ready, + +//Interface with OnScheduleRecord + output wire [23:0] on_schedule_addr, + input wire [0:0] on_schedule_dout, + +//Interface with SQHeadRecord + output wire [0:0] sq_head_record_wen, + output wire [`QP_NUM_LOG - 1 : 0] sq_head_record_addr, + output wire [23:0] sq_head_record_din, + input wire [23:0] sq_head_record_dout +); +/*------------------------------------------- Input/Output Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Macros Definition : Begin ---------------------------------------*/ +`define SQ_HEAD_OFFSET 31:8 +`define QPN_OFFSET 63:40 +/*------------------------------------------- Local Macros Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Variables Definition : Begin ------------------------------------*/ +/*------------------------------------------- Local Variables Definition : End --------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : Begin ---------------------------------------*/ +/*------------------------------------------- Submodules Instatiation : End -----------------------------------------*/ + +/*------------------------------------------- State Machine Definition : Begin --------------------------------------*/ +reg [2:0] cur_state; +reg [2:0] next_state; + +parameter IDLE_s = 2'd1, + UPDATE_s = 2'd2; + +always @(posedge clk or posedge rst) begin + if(rst) begin + cur_state <= IDLE_s; + end + else begin + cur_state <= next_state; + end +end + +always @(*) begin + case(cur_state) + IDLE_s: if(!db_fifo_empty) begin + next_state = UPDATE_s; + end + else begin + next_state = IDLE_s; + end + UPDATE_s: if(!on_schedule_dout && qpn_fifo_ready) begin + next_state = IDLE_s; + end + else if(on_schedule_dout) begin + next_state = IDLE_s; + end + else begin + next_state = UPDATE_s; + end + default: next_state = IDLE_s; + endcase +end +/*------------------------------------------- State Machine Definition : End ----------------------------------------*/ + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ +//-- db_fifo_rd_en -- +assign db_fifo_rd_en = (cur_state == UPDATE_s) && ((!on_schedule_dout && qpn_fifo_ready) || on_schedule_dout) ? 'd1 : 'd0; + +//-- qpn_fifo_valid -- +//-- qpn_fifo_data -- +assign qpn_fifo_valid = ((cur_state == UPDATE_s) && !on_schedule_dout) ? 'd1 : 'd0; +assign qpn_fifo_data = ((cur_state == UPDATE_s) && !on_schedule_dout) ? db_fifo_dout[`QPN_OFFSET] : 'd0; + +//Interface with OnScheduleRecord +assign on_schedule_addr = db_fifo_dout[`QPN_OFFSET]; + +//Interface with SQHeadRecord +assign sq_head_record_wen = (cur_state == UPDATE_s) ? 'd1 : 'd0; +assign sq_head_record_addr = (cur_state == UPDATE_s) ? db_fifo_dout[`QPN_OFFSET] : 'd0; +assign sq_head_record_din = (cur_state == UPDATE_s) ? db_fifo_dout[`SQ_HEAD_OFFSET] : 'd0; +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ + +/*------------------------------------------- Local Macros Undef : Begin --------------------------------------------*/ +`undef SQ_HEAD_OFFSET +`undef QPN_OFFSET +/*------------------------------------------- Local Macros Undef : End ----------------------------------------------*/ + +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/QueueSubsystem/SQMgt/QPNArbiter.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/QueueSubsystem/SQMgt/QPNArbiter.v new file mode 100644 index 0000000000000000000000000000000000000000..9f5e9903b58faf0cdaecb464aa6ea2fd6534de3e --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/QueueSubsystem/SQMgt/QPNArbiter.v @@ -0,0 +1,56 @@ +/*------------------------------------------- Module Description : Begin ---------------------------------------------- +Name: QPNArbiter +Author: YangFan +Function: 1.Arbitrate QPN from DBProc and WQEParser. +--------------------------------------------- Module Decription : End -----------------------------------------------*/ + +/*------------------------------------------- Timescale Definition : Begin ------------------------------------------*/ +`timescale 1ns / 1ps +/*------------------------------------------- Timescale Definition : End --------------------------------------------*/ + +/*------------------------------------------- Included Files : Begin ------------------------------------------------*/ +`include "protocol_engine_def.vh" +/*------------------------------------------- Included Files : End --------------------------------------------------*/ + +/*------------------------------------------- Input/Output Definition : Begin ---------------------------------------*/ +module QPNArbiter +( + input wire clk, + input wire rst, + + input wire chnl_0_qpn_valid, + input wire [`QP_NUM_LOG - 1 : 0] chnl_0_qpn_data, + output wire chnl_0_qpn_ready, + + input wire chnl_1_qpn_valid, + input wire [`QP_NUM_LOG - 1 : 0] chnl_1_qpn_data, + output wire chnl_1_qpn_ready, + + output wire qpn_valid, + output wire [`QP_NUM_LOG - 1 : 0] qpn_data, + input wire qpn_ready +); + +/*------------------------------------------- Input/Output Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Macros Definition : Begin ---------------------------------------*/ +/*------------------------------------------- Local Macros Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Variables Definition : Begin ------------------------------------*/ +/*------------------------------------------- Local Variables Definition : End --------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : Begin ---------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : End -----------------------------------------*/ + +/*------------------------------------------- State Machine Definition : Begin --------------------------------------*/ +/*------------------------------------------- State Machine Definition : End ----------------------------------------*/ + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ +/*------------------------------------------- Variables Decode : End ----------------------------------------------*/ + +/*------------------------------------------- Local Macros Undef : Begin --------------------------------------------*/ + +/*------------------------------------------- Local Macros Undef : End ----------------------------------------------*/ + +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/QueueSubsystem/SQMgt/SQMetaProc/SQMetaProc.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/QueueSubsystem/SQMgt/SQMetaProc/SQMetaProc.v new file mode 100644 index 0000000000000000000000000000000000000000..7141404f1e2b8c067b02a6e1954df5cc6b8b13f6 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/QueueSubsystem/SQMgt/SQMetaProc/SQMetaProc.v @@ -0,0 +1,142 @@ +/*------------------------------------------- Module Description : Begin ---------------------------------------------- +Name: SQMetaProc +Author: YangFan +Function: Fetch SQ context and page info. +--------------------------------------------- Module Decription : End -----------------------------------------------*/ + +/*------------------------------------------- Timescale Definition : Begin ------------------------------------------*/ +`timescale 1ns / 1ps +/*------------------------------------------- Timescale Definition : End --------------------------------------------*/ + +/*------------------------------------------- Included Files : Begin ------------------------------------------------*/ +`include "protocol_engine_def.vh" +/*------------------------------------------- Included Files : End --------------------------------------------------*/ + +/*------------------------------------------- Input/Output Definition : Begin ---------------------------------------*/ +module SQMetaProc +( + input wire clk, + input wire rst, + +//Interface with QPNArbiter + input wire qpn_valid, + input wire [23:0] qpn_data, + output wire qpn_ready, + +//Interface with CxtMgt + output wire fetch_cxt_ingress_valid, + output wire [`SQ_OOO_CXT_INGRESS_HEAD_WIDTH - 1 : 0] fetch_cxt_ingress_head, + output wire [`SQ_OOO_CXT_INGRESS_DATA_WIDTH - 1 : 0] fetch_cxt_ingress_data, + output wire fetch_cxt_ingress_start, + output wire fetch_cxt_ingress_last, + input wire fetch_cxt_ingress_ready, + + input wire fetch_cxt_egress_valid, + input wire [`SQ_OOO_CXT_EGRESS_HEAD_WIDTH - 1 : 0] fetch_cxt_egress_head, + input wire [`SQ_OOO_CXT_EGRESS_DATA_WIDTH - 1 : 0] fetch_cxt_egress_data, + input wire fetch_cxt_egress_start, + input wire fetch_cxt_egress_last, + output wire fetch_cxt_egress_ready, + +//Interface with MRMgt + output wire fetch_mr_ingress_valid, + output wire [`SQ_OOO_MR_INGRESS_HEAD_WIDTH - 1 : 0] fetch_mr_ingress_head, + output wire [`SQ_OOO_MR_INGRESS_DATA_WIDTH - 1 : 0] fetch_mr_ingress_data, + output wire fetch_mr_ingress_start, + output wire fetch_mr_ingress_last, + input wire fetch_mr_ingress_ready, + + input wire fetch_mr_egress_valid, + input wire [`SQ_OOO_MR_EGRESS_HEAD_WIDTH - 1 : 0] fetch_mr_egress_head, + input wire [`SQ_OOO_MR_EGRESS_DATA_WIDTH - 1 : 0] fetch_mr_egress_data, + input wire fetch_mr_egress_start, + input wire fetch_mr_egress_last, + output wire fetch_mr_egress_ready, + +//Interface with SQOffsetRecord + output wire [0:0] sq_offset_wen, + output wire [`QP_NUM_LOG - 1 : 0] sq_offset_addr, + output wire [23:0] sq_offset_din, + input wire [23:0] sq_offset_dout, + +//Interface with WQEFetch + output wire sq_meta_valid, + output wire [`SQ_META_WIDTH - 1 : 0] sq_meta_data, + input wire sq_meta_ready +); +/*------------------------------------------- Input/Output Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Macros Definition : Begin ---------------------------------------*/ + +/*------------------------------------------- Local Macros Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Variables Definition : Begin ------------------------------------*/ +/*------------------------------------------- Local Variables Definition : End --------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : Begin ---------------------------------------*/ +SQMetaProc_Thread_1 SQMetaProc_Thread_1_Inst +( + .clk ( clk ), + .rst ( rst ), + + .qpn_valid ( qpn_valid ), + .qpn_data ( qpn_data ), + .qpn_ready ( qpn_ready ), + + .fetch_cxt_ingress_valid ( fetch_cxt_ingress_valid ), + .fetch_cxt_ingress_head ( fetch_cxt_ingress_head ), + .fetch_cxt_ingress_data ( fetch_cxt_ingress_data ), + .fetch_cxt_ingress_start ( fetch_cxt_ingress_start ), + .fetch_cxt_ingress_last ( fetch_cxt_ingress_last ), + .fetch_cxt_ingress_ready ( fetch_cxt_ingress_ready ) +); + +SQMetaProc_Thread_2 SQMetaProc_Thread_2_Inst +( + .clk ( clk ), + .rst ( rst ), + + .fetch_cxt_egress_valid ( fetch_cxt_egress_valid ), + .fetch_cxt_egress_head ( fetch_cxt_egress_head ), + .fetch_cxt_egress_data ( fetch_cxt_egress_data ), + .fetch_cxt_egress_start ( fetch_cxt_egress_start ), + .fetch_cxt_egress_last ( fetch_cxt_egress_last ), + .fetch_cxt_egress_ready ( fetch_cxt_egress_ready ), + + .sq_offset_wen ( sq_offset_wen ), + .sq_offset_addr ( sq_offset_addr ), + .sq_offset_din ( sq_offset_din ), + .sq_offset_dout ( sq_offset_dout ), + + .fetch_mr_ingress_valid ( fetch_mr_ingress_valid ), + .fetch_mr_ingress_head ( fetch_mr_ingress_head ), + .fetch_mr_ingress_data ( fetch_mr_ingress_data ), + .fetch_mr_ingress_start ( fetch_mr_ingress_start ), + .fetch_mr_ingress_last ( fetch_mr_ingress_last ), + .fetch_mr_ingress_ready ( fetch_mr_ingress_ready ), + + .fetch_mr_egress_valid ( fetch_mr_egress_valid ), + .fetch_mr_egress_head ( fetch_mr_egress_head ), + .fetch_mr_egress_data ( fetch_mr_egress_data ), + .fetch_mr_egress_start ( fetch_mr_egress_start ), + .fetch_mr_egress_last ( fetch_mr_egress_last ), + .fetch_mr_egress_ready ( fetch_mr_egress_ready ), + + .sq_meta_valid ( sq_meta_valid ), + .sq_meta_data ( sq_meta_data ), + .sq_meta_ready ( sq_meta_ready ) +); +/*------------------------------------------- Submodules Instatiation : End -----------------------------------------*/ + +/*------------------------------------------- State Machine Definition : Begin --------------------------------------*/ +/*------------------------------------------- State Machine Definition : End ----------------------------------------*/ + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ + +/*------------------------------------------- Local Macros Undef : Begin --------------------------------------------*/ + +/*------------------------------------------- Local Macros Undef : End ----------------------------------------------*/ + +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/QueueSubsystem/SQMgt/SQMetaProc/SQMetaProc_Thread_1.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/QueueSubsystem/SQMgt/SQMetaProc/SQMetaProc_Thread_1.v new file mode 100644 index 0000000000000000000000000000000000000000..7c50cf629f9c967fc5e99c43b43a3ac546e91223 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/QueueSubsystem/SQMgt/SQMetaProc/SQMetaProc_Thread_1.v @@ -0,0 +1,107 @@ +/*------------------------------------------- Module Description : Begin ---------------------------------------------- +Name: SQMetaProc_Thread_1 +Author: YangFan +Function: Fetch SQ Context. +--------------------------------------------- Module Decription : End -----------------------------------------------*/ + +/*------------------------------------------- Timescale Definition : Begin ------------------------------------------*/ +`timescale 1ns / 1ps +/*------------------------------------------- Timescale Definition : End --------------------------------------------*/ + +/*------------------------------------------- Included Files : Begin ------------------------------------------------*/ +`include "protocol_engine_def.vh" +/*------------------------------------------- Included Files : End --------------------------------------------------*/ + +/*------------------------------------------- Input/Output Definition : Begin ---------------------------------------*/ +module SQMetaProc_Thread_1 +( + input wire clk, + input wire rst, + +//Interface with QPNArbiter + input wire qpn_valid, + input wire [23:0] qpn_data, + output wire qpn_ready, + + output wire fetch_cxt_ingress_valid, + output wire [`SQ_OOO_CXT_INGRESS_HEAD_WIDTH - 1 : 0] fetch_cxt_ingress_head, + output wire [`SQ_OOO_CXT_INGRESS_DATA_WIDTH - 1 : 0] fetch_cxt_ingress_data, + output wire fetch_cxt_ingress_start, + output wire fetch_cxt_ingress_last, + input wire fetch_cxt_ingress_ready +); +/*------------------------------------------- Input/Output Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Macros Definition : Begin ---------------------------------------*/ + +/*------------------------------------------- Local Macros Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Variables Definition : Begin ------------------------------------*/ +wire [`INGRESS_COMMON_HEAD_WIDTH - 1 : 0] ingress_common_head; +wire [`MAX_OOO_SLOT_NUM_LOG - 1 :0] ingress_slot_count; +/*------------------------------------------- Local Variables Definition : End --------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : Begin ---------------------------------------*/ +/*------------------------------------------- Submodules Instatiation : End -----------------------------------------*/ + +/*------------------------------------------- State Machine Definition : Begin --------------------------------------*/ +reg [1:0] cur_state; +reg [1:0] next_state; + +parameter [1:0] IDLE_s = 2'd1, + FETCH_CXT_s = 2'd2; + +always @(posedge clk or posedge rst) begin + if(rst) begin + cur_state <= IDLE_s; + end + else begin + cur_state <= next_state; + end +end + +always @(*) begin + case(cur_state) + IDLE_s: if(qpn_valid) begin + next_state = FETCH_CXT_s; + end + else begin + next_state = IDLE_s; + end + FETCH_CXT_s: if(fetch_cxt_ingress_valid && fetch_cxt_ingress_ready) begin + next_state = IDLE_s; + end + else begin + next_state = FETCH_CXT_s; + end + default: next_state = IDLE_s; + endcase +end +/*------------------------------------------- State Machine Definition : End ----------------------------------------*/ + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ +//-- qpn_ready -- +assign qpn_ready = (cur_state == FETCH_CXT_s && fetch_cxt_ingress_valid && fetch_cxt_ingress_ready) ? 'd1 : 'd0; + +wire [`MAX_QP_NUM_LOG - 1 : 0] queue_index; +assign queue_index = {'d0, qpn_data[`QP_NUM_LOG - 1 : 0]}; + +//-- ingress_common_head -- +//-- ingress_slot_count -- +assign ingress_common_head = {`NO_BYPASS, ingress_slot_count, queue_index}; +assign ingress_slot_count = 'd1; + +//-- fetch_cxt_ingress_valid -- +//-- fetch_cxt_ingress_head -- +//-- fetch_cxt_ingress_data -- +assign fetch_cxt_ingress_valid = (cur_state == FETCH_CXT_s) ? 'd1 : 'd0; +assign fetch_cxt_ingress_head = (cur_state == FETCH_CXT_s) ? {qpn_data[`QP_NUM_LOG - 1 : 0], `CXT_READ, ingress_common_head} : 'd0; +assign fetch_cxt_ingress_data = (cur_state == FETCH_CXT_s) ? 'd0 : 'd0; //No extra data +assign fetch_cxt_ingress_start = (cur_state == FETCH_CXT_s) ? 'd1 : 'd0; +assign fetch_cxt_ingress_last = (cur_state == FETCH_CXT_s) ? 'd1 : 'd0; +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ + +/*------------------------------------------- Local Macros Undef : Begin --------------------------------------------*/ +/*------------------------------------------- Local Macros Undef : End ----------------------------------------------*/ + +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/QueueSubsystem/SQMgt/SQMetaProc/SQMetaProc_Thread_2.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/QueueSubsystem/SQMgt/SQMetaProc/SQMetaProc_Thread_2.v new file mode 100644 index 0000000000000000000000000000000000000000..2a601d6c8cd07ce08ba965368d2eb7af5acb19b6 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/QueueSubsystem/SQMgt/SQMetaProc/SQMetaProc_Thread_2.v @@ -0,0 +1,370 @@ +/*------------------------------------------- Module Description : Begin ---------------------------------------------- +Name: SQMetaProc_Thread_2 +Author: YangFan +Function: Fetch SQ Memory Region. +--------------------------------------------- Module Decription : End -----------------------------------------------*/ + +/*------------------------------------------- Timescale Definition : Begin ------------------------------------------*/ +`timescale 1ns / 1ps +/*------------------------------------------- Timescale Definition : End --------------------------------------------*/ + +/*------------------------------------------- Included Files : Begin ------------------------------------------------*/ +`include "protocol_engine_def.vh" +/*------------------------------------------- Included Files : End --------------------------------------------------*/ + +/*------------------------------------------- Input/Output Definition : Begin ---------------------------------------*/ +module SQMetaProc_Thread_2 +( + input wire clk, + input wire rst, + +//Interface with SQMetaProc_Thread_1 + input wire fetch_cxt_egress_valid, + input wire [`SQ_OOO_CXT_EGRESS_HEAD_WIDTH - 1 : 0] fetch_cxt_egress_head, + input wire [`SQ_OOO_CXT_EGRESS_DATA_WIDTH - 1 : 0] fetch_cxt_egress_data, + input wire fetch_cxt_egress_start, + input wire fetch_cxt_egress_last, + output wire fetch_cxt_egress_ready, + +//Interface with SQOffsetRecord + output wire [0:0] sq_offset_wen, + output wire [`QP_NUM_LOG - 1 : 0] sq_offset_addr, + output wire [23:0] sq_offset_din, + input wire [23:0] sq_offset_dout, + +//Interface with MRMgt + output wire fetch_mr_ingress_valid, + output wire [`SQ_OOO_MR_INGRESS_HEAD_WIDTH - 1 : 0] fetch_mr_ingress_head, + output wire [`SQ_OOO_MR_INGRESS_DATA_WIDTH - 1 : 0] fetch_mr_ingress_data, + output wire fetch_mr_ingress_start, + output wire fetch_mr_ingress_last, + input wire fetch_mr_ingress_ready, + + input wire fetch_mr_egress_valid, + input wire [`SQ_OOO_MR_EGRESS_HEAD_WIDTH - 1 : 0] fetch_mr_egress_head, + input wire [`SQ_OOO_MR_EGRESS_DATA_WIDTH - 1 : 0] fetch_mr_egress_data, + input wire fetch_mr_egress_start, + input wire fetch_mr_egress_last, + output wire fetch_mr_egress_ready, + +//Interface with WQEFetch + output wire sq_meta_valid, + output wire [`SQ_META_WIDTH - 1 : 0] sq_meta_data, + input wire sq_meta_ready + +); +/*------------------------------------------- Input/Output Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Macros Definition : Begin ---------------------------------------*/ + +/*------------------------------------------- Local Macros Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Variables Definition : Begin ------------------------------------*/ +wire [`INGRESS_COMMON_HEAD_WIDTH - 1 : 0] ingress_common_head; +wire [`MAX_OOO_SLOT_NUM_LOG - 1 :0] ingress_slot_count; + +reg [`SQ_OOO_CXT_EGRESS_HEAD_WIDTH - 1 : 0] cxt_head_diff; +reg [`SQ_OOO_CXT_EGRESS_DATA_WIDTH - 1 : 0] cxt_data_diff; + + + +wire [15:0] local_qpn; +wire [15:0] remote_qpn; +wire [2:0] service_type; +wire [47:0] smac; +wire [47:0] dmac; +wire [31:0] sip; +wire [31:0] dip; +wire [7:0] sq_entry_sz_log; +wire [31:0] sq_length; +wire [15:0] pmtu; +wire [31:0] sq_lkey; +wire [31:0] qp_pd; + +reg [31:0] mr_flags; +reg [3:0] mr_flag_sw_owns; +reg mr_flag_absolute_addr; +reg mr_flag_relative_addr; +reg mr_flag_mio; +reg mr_flag_bind_enable; +reg mr_flag_physical; +reg mr_flag_region; +reg mr_flag_on_demand; +reg mr_flag_zero_based; +reg mr_flag_mw_bind; +reg mr_remote_read; +reg mr_remote_write; +reg mr_local_write; + +wire [31:0] mr_length; +wire [63:0] mr_laddr; +wire [31:0] mr_lkey; +wire [31:0] mr_pd; + +wire [`CACHE_ENTRY_WIDTH_QPC - 1 : 0] qp_cxt; +/*------------------------------------------- Local Variables Definition : End --------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : Begin ---------------------------------------*/ +/*------------------------------------------- Submodules Instatiation : End -----------------------------------------*/ + +/*------------------------------------------- State Machine Definition : Begin --------------------------------------*/ +reg [1:0] cur_state; +reg [1:0] next_state; + +parameter [1:0] IDLE_s = 2'd1, + STAGED_s = 2'd2, + FETCH_MR_s = 2'd3; + +always @(posedge clk or posedge rst) begin + if(rst) begin + cur_state <= IDLE_s; + end + else begin + cur_state <= next_state; + end +end + +always @(*) begin + case(cur_state) + IDLE_s: if(fetch_cxt_egress_valid) begin + next_state = STAGED_s; + end + else begin + next_state = IDLE_s; + end + STAGED_s: next_state = FETCH_MR_s; + FETCH_MR_s: if(fetch_mr_ingress_valid && fetch_mr_ingress_ready) begin + next_state = IDLE_s; + end + else begin + next_state = FETCH_MR_s; + end + default: next_state = IDLE_s; + endcase +end +/*------------------------------------------- State Machine Definition : End ----------------------------------------*/ + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ +//-- cxt_head_diff -- +//-- cxt_data_diff -- +always @(posedge clk or posedge rst) begin + if(rst) begin + cxt_head_diff <= 'd0; + cxt_data_diff <= 'd0; + end + else if(cur_state == IDLE_s && fetch_cxt_egress_valid) begin + cxt_head_diff <= fetch_cxt_egress_head; + cxt_data_diff <= fetch_cxt_egress_data; + end + else begin + cxt_head_diff <= cxt_head_diff; + cxt_data_diff <= cxt_data_diff; + end +end + +//-- qp_cxt -- +assign qp_cxt = cxt_head_diff[`CACHE_ENTRY_WIDTH_QPC + `EGRESS_COMMON_HEAD_WIDTH - 1 : `EGRESS_COMMON_HEAD_WIDTH]; + +//-- local_qpn -- +//-- remote_qpn -- +//-- service_type -- +//-- smac -- +//-- dmac -- +//-- sip -- +//-- dip -- +//-- sq_entry_sz_log -- +//-- sq_length -- +//-- pmtu -- +//-- sq_lkey -- +//-- qp_pd -- +assign local_qpn = cxt_head_diff[`QP_NUM_LOG - 1:0]; +assign remote_qpn = qp_cxt[`QP_CXT_DST_QPN_OFFSET]; +assign service_type = qp_cxt[`QP_CXT_SERVICE_TYPE_OFFSET]; +assign smac = qp_cxt[`QP_CXT_SMAC_OFFSET]; +assign dmac = qp_cxt[`QP_CXT_DMAC_OFFSET]; +assign sip = qp_cxt[`QP_CXT_SIP_OFFSET]; +assign dip = qp_cxt[`QP_CXT_DIP_OFFSET]; +assign sq_entry_sz_log = qp_cxt[`QP_CXT_SQ_ENTRY_SZ_LOG_OFFSET]; +assign sq_length = qp_cxt[`QP_CXT_SQ_LENGTH_OFFSET]; +assign pmtu = qp_cxt[`QP_CXT_PMTU_OFFSET]; +assign qp_pd = qp_cxt[`QP_CXT_PD_OFFSET]; +assign sq_lkey = qp_cxt[`QP_CXT_SQ_LKEY_OFFSET]; + +//-- ingress_common_head -- +//-- ingress_slot_count -- +assign ingress_slot_count = (cur_state == FETCH_MR_s) ? 'd1 : 'd0; +assign ingress_common_head = (cur_state == FETCH_MR_s) ? {`NO_BYPASS, ingress_slot_count, local_qpn[`MAX_QP_NUM_LOG - 1 : 0]} : 'd0; + +//-- mr_length -- +//-- mr_laddr -- +//-- mr_lkey -- +//-- mr_pd -- +assign mr_length = (cur_state == FETCH_MR_s && (sq_offset_dout * 16) + `SQ_PREFETCH_LENGTH > sq_length) ? (sq_length - (sq_offset_dout * 16)) : + (cur_state == FETCH_MR_s && (sq_offset_dout * 16) + `SQ_PREFETCH_LENGTH <= sq_length) ? `SQ_PREFETCH_LENGTH : 'd0; +assign mr_laddr = (cur_state == FETCH_MR_s) ? (sq_offset_dout * 16) : 'd0; +assign mr_lkey = sq_lkey; +assign mr_pd = qp_pd; + +//-- mr_flag_sw_owns -- +//-- mr_flag_absolute_addr -- +//-- mr_flag_relative_addr -- +//-- mr_flag_mio -- +//-- mr_flag_bind_enable -- +//-- mr_flag_physical -- +//-- mr_flag_on_demand -- +//-- mr_flag_zero_based -- +//-- mr_flag_mw_bind -- +//-- mr_remote_read -- +//-- mr_remote_write -- +//-- mr_local_write -- +always @(*) begin + if(rst) begin + mr_flag_sw_owns = 'd0; + mr_flag_absolute_addr = 'd0; + mr_flag_relative_addr = 'd0; + mr_flag_mio = 'd0; + mr_flag_bind_enable = 'd0; + mr_flag_physical = 'd0; + mr_flag_region = 'd0; + mr_flag_on_demand = 'd0; + mr_flag_zero_based = 'd0; + mr_flag_mw_bind = 'd0; + mr_remote_read = 'd0; + mr_remote_write = 'd0; + mr_local_write = 'd0; + end + else if(cur_state == FETCH_MR_s) begin + mr_flag_sw_owns = 'd0; + mr_flag_absolute_addr = 'd0; + mr_flag_relative_addr = 'd1; + mr_flag_mio = 'd0; + mr_flag_bind_enable = 'd0; + mr_flag_physical = 'd0; + mr_flag_region = 'd0; + mr_flag_on_demand = 'd0; + mr_flag_zero_based = 'd0; + mr_flag_mw_bind = 'd0; + mr_remote_read = 'd0; + mr_remote_write = 'd0; + mr_local_write = 'd0; + end + else begin + mr_flag_sw_owns = 'd0; + mr_flag_absolute_addr = 'd0; + mr_flag_relative_addr = 'd1; + mr_flag_mio = 'd0; + mr_flag_bind_enable = 'd0; + mr_flag_physical = 'd0; + mr_flag_region = 'd0; + mr_flag_on_demand = 'd0; + mr_flag_zero_based = 'd0; + mr_flag_mw_bind = 'd0; + mr_remote_read = 'd0; + mr_remote_write = 'd0; + mr_local_write = 'd0; + end +end + +//-- mr_flags -- +always @(*) begin + if(rst) begin + mr_flags = 'd0; + end + else if(cur_state == FETCH_MR_s) begin + mr_flags = { + mr_flag_sw_owns, + mr_flag_absolute_addr, + mr_flag_relative_addr, + 8'd0, + mr_flag_mio, + 1'd0, + mr_flag_bind_enable, + 5'd0, + mr_flag_physical, + mr_flag_region, + 1'd0, + mr_flag_on_demand, + mr_flag_zero_based, + mr_flag_mw_bind, + mr_remote_read, + mr_remote_write, + mr_local_write + }; + end + else begin + mr_flags = 'd0; + end +end + +//-- fetch_cxt_egress_ready -- +assign fetch_cxt_egress_ready = (cur_state == IDLE_s) ? 'd1 : 'd0; + +//-- sq_offset_addr -- +assign sq_offset_addr = local_qpn; + +//-- sq_offset_wen -- +assign sq_offset_wen = 'd0; + +//-- sq_offset_din -- +assign sq_offset_din = 'd0; + +//-- fetch_mr_ingress_valid -- +//-- fetch_mr_ingress_head -- +//-- fetch_mr_ingress_data -- +//-- fetch_mr_ingress_start -- +//-- fetch_mr_ingress_last -- +assign fetch_mr_ingress_valid = (cur_state == FETCH_MR_s) ? 'd1 : 'd0; +assign fetch_mr_ingress_head = (cur_state == FETCH_MR_s) ? {mr_length, mr_laddr, mr_lkey, mr_pd, mr_flags, ingress_common_head} : 'd0; +assign fetch_mr_ingress_data = (cur_state == FETCH_MR_s) ? cxt_head_diff[`SQ_OOO_CXT_EGRESS_HEAD_WIDTH - 1 : `EGRESS_COMMON_HEAD_WIDTH] : 'd0; +assign fetch_mr_ingress_start = (cur_state == FETCH_MR_s) ? 'd1 : 'd0; +assign fetch_mr_ingress_last = (cur_state == FETCH_MR_s) ? 'd1 : 'd0; + +//-- fetch_mr_egress_ready -- +assign fetch_mr_egress_ready = sq_meta_ready; + +wire [15:0] meta_local_qpn; +wire [15:0] meta_remote_qpn; +wire [7:0] meta_service_type; +wire [47:0] meta_smac; +wire [47:0] meta_dmac; +wire [31:0] meta_sip; +wire [31:0] meta_dip; +wire [7:0] meta_sq_entry_sz_log; +wire [15:0] meta_pmtu; +wire [31:0] meta_qp_pd; +wire [31:0] meta_sq_length; + +assign meta_local_qpn = {'d0, fetch_mr_egress_head[`QP_NUM_LOG - 1 : 0]}; +assign meta_remote_qpn = {'d0, fetch_mr_egress_data[`QP_CXT_DST_QPN_OFFSET]}; +assign meta_service_type = {'d0, fetch_mr_egress_data[`QP_CXT_SERVICE_TYPE_OFFSET]}; +assign meta_smac = fetch_mr_egress_data[`QP_CXT_SMAC_OFFSET]; +assign meta_dmac = fetch_mr_egress_data[`QP_CXT_DMAC_OFFSET]; +assign meta_sip = fetch_mr_egress_data[`QP_CXT_SIP_OFFSET]; +assign meta_dip = fetch_mr_egress_data[`QP_CXT_DIP_OFFSET]; +assign meta_sq_entry_sz_log = fetch_mr_egress_data[`QP_CXT_SQ_ENTRY_SZ_LOG_OFFSET]; +assign meta_pmtu = 128 << fetch_mr_egress_data[`QP_CXT_PMTU_OFFSET]; +assign meta_qp_pd = fetch_mr_egress_data[`QP_CXT_PD_OFFSET]; +assign meta_sq_length = fetch_mr_egress_data[`QP_CXT_SQ_LENGTH_OFFSET]; + +//-- sq_meta_valid -- +//-- sq_meta_data -- +assign sq_meta_valid = fetch_mr_egress_valid; +assign sq_meta_data = { fetch_mr_egress_head[`MR_RESP_HEAD_WIDTH + `EGRESS_COMMON_HEAD_WIDTH - 1 : `EGRESS_COMMON_HEAD_WIDTH], + meta_sip, + meta_dip, + meta_smac, + meta_dmac, + meta_qp_pd, + meta_sq_length, + meta_pmtu, + meta_sq_entry_sz_log, + meta_service_type, + meta_remote_qpn, + meta_local_qpn + }; //Piece MR info, Context info together +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ + +/*------------------------------------------- Local Macros Undef : Begin --------------------------------------------*/ +/*------------------------------------------- Local Macros Undef : End ----------------------------------------------*/ + +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/QueueSubsystem/SQMgt/SQMgt.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/QueueSubsystem/SQMgt/SQMgt.v new file mode 100644 index 0000000000000000000000000000000000000000..9bda4290cfe60b5dd207df7ae35588ac311db0b4 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/QueueSubsystem/SQMgt/SQMgt.v @@ -0,0 +1,540 @@ +/*------------------------------------------- Module Description : Begin ---------------------------------------------- +Name: SQMgt +Author: YangFan +Function: Manage Send Queue. +--------------------------------------------- Module Decription : End -----------------------------------------------*/ + +/*------------------------------------------- Timescale Definition : Begin ------------------------------------------*/ +`timescale 1ns / 1ps +/*------------------------------------------- Timescale Definition : End --------------------------------------------*/ + +/*------------------------------------------- Included Files : Begin ------------------------------------------------*/ +`include "protocol_engine_def.vh" +/*------------------------------------------- Included Files : End --------------------------------------------------*/ + +/*------------------------------------------- Input/Output Definition : Begin ---------------------------------------*/ +module SQMgt +#( + parameter CACHE_SLOT_NUM = 256, + parameter CACHE_SLOT_NUM_LOG = log2b(CACHE_SLOT_NUM - 1), + + parameter CACHE_CELL_NUM = 256, + parameter CACHE_CELL_NUM_LOG = log2b(CACHE_CELL_NUM - 1), + + parameter INGRESS_CXT_HEAD_WIDTH = 128, + parameter INGRESS_CXT_DATA_WIDTH = 256, + parameter EGRESS_CXT_HEAD_WIDTH = 128, + parameter EGRESS_CXT_DATA_WIDTH = 256, + + parameter INGRESS_MR_HEAD_WIDTH = 128, + parameter INGRESS_MR_DATA_WIDTH = 256, + parameter EGRESS_MR_HEAD_WIDTH = 128, + parameter EGRESS_MR_DATA_WIDTH = 256 +) +( + input wire clk, + input wire rst, + +//Interface with PIO + input wire db_fifo_empty, + input wire [63:0] db_fifo_dout, + output wire db_fifo_rd_en, + +//Interface with CxtMgt + output wire fetch_cxt_ingress_valid, + output wire [`SQ_OOO_CXT_INGRESS_HEAD_WIDTH - 1 : 0] fetch_cxt_ingress_head, + output wire [`SQ_OOO_CXT_INGRESS_DATA_WIDTH - 1 : 0] fetch_cxt_ingress_data, + output wire fetch_cxt_ingress_start, + output wire fetch_cxt_ingress_last, + input wire fetch_cxt_ingress_ready, + + input wire fetch_cxt_egress_valid, + input wire [`SQ_OOO_CXT_EGRESS_HEAD_WIDTH - 1 : 0] fetch_cxt_egress_head, + input wire [`SQ_OOO_CXT_EGRESS_DATA_WIDTH - 1 : 0] fetch_cxt_egress_data, + input wire fetch_cxt_egress_start, + input wire fetch_cxt_egress_last, + output wire fetch_cxt_egress_ready, + +//Interface with MRMgt + output wire fetch_mr_ingress_valid, + output wire [`SQ_OOO_MR_INGRESS_HEAD_WIDTH - 1 : 0] fetch_mr_ingress_head, + output wire [`SQ_OOO_MR_INGRESS_DATA_WIDTH - 1 : 0] fetch_mr_ingress_data, + output wire fetch_mr_ingress_start, + output wire fetch_mr_ingress_last, + input wire fetch_mr_ingress_ready, + + input wire fetch_mr_egress_valid, + input wire [`SQ_OOO_MR_EGRESS_HEAD_WIDTH - 1 : 0] fetch_mr_egress_head, + input wire [`SQ_OOO_MR_EGRESS_DATA_WIDTH - 1 : 0] fetch_mr_egress_data, + input wire fetch_mr_egress_start, + input wire fetch_mr_egress_last, + output wire fetch_mr_egress_ready, + +//Interface with DMA Read Channel + output wire SQ_dma_rd_req_valid, + output wire [`DMA_HEAD_WIDTH - 1 : 0] SQ_dma_rd_req_head, + output wire [`DMA_DATA_WIDTH - 1 : 0] SQ_dma_rd_req_data, + output wire SQ_dma_rd_req_last, + input wire SQ_dma_rd_req_ready, + + input wire SQ_dma_rd_rsp_valid, + input wire [`DMA_HEAD_WIDTH - 1 : 0] SQ_dma_rd_rsp_head, + input wire [`DMA_DATA_WIDTH - 1 : 0] SQ_dma_rd_rsp_data, + input wire SQ_dma_rd_rsp_last, + output wire SQ_dma_rd_rsp_ready, + +//Interface with RDMACore + output wire sub_wqe_valid, + output wire [`WQE_META_WIDTH - 1 : 0] sub_wqe_meta, + input wire sub_wqe_ready, + +//Interface with DynamicBuffer(Payload Buffer) + output wire insert_req_valid, + output wire insert_req_start, + output wire insert_req_last, + output wire [`INLINE_PAYLOAD_BUFFER_SLOT_NUM_LOG - 1 : 0] insert_req_head, + output wire [`INLINE_PAYLOAD_BUFFER_SLOT_WIDTH - 1 : 0] insert_req_data, + input wire insert_req_ready, + + input wire insert_resp_valid, + input wire [`INLINE_PAYLOAD_BUFFER_SLOT_WIDTH - 1 : 0] insert_resp_data +); +/*------------------------------------------- Input/Output Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Macros Definition : Begin ---------------------------------------*/ +/*------------------------------------------- Local Macros Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Variables Definition : Begin ------------------------------------*/ +wire chnl_0_qpn_valid; +wire [`QP_NUM_LOG - 1 : 0] chnl_0_qpn_data; +wire chnl_0_qpn_ready; + +wire chnl_1_qpn_valid; +wire [`QP_NUM_LOG - 1 : 0] chnl_1_qpn_data; +wire chnl_1_qpn_ready; + +wire qpn_in_valid; +wire [23:0] qpn_in_data; +wire qpn_in_ready; +wire qpn_in_prog_full; + +wire qpn_out_valid; +wire [23:0] qpn_out_data; +wire qpn_out_ready; +wire qpn_out_empty; + +wire on_schedule_wea; +wire [23:0] on_schedule_addra; +wire [0:0] on_schedule_dina; +wire [23:0] on_schedule_addrb; +wire [0:0] on_schedule_doutb; + +wire [0:0] sq_head_record_wea; +wire [`QP_NUM_LOG - 1 : 0] sq_head_record_addra; +wire [23:0] sq_head_record_dina; +wire [23:0] sq_head_record_douta; + +wire [0:0] sq_head_record_web; +wire [`QP_NUM_LOG - 1 : 0] sq_head_record_addrb; +wire [23:0] sq_head_record_dinb; +wire [23:0] sq_head_record_doutb; + +wire [0:0] sq_offset_record_wea; +wire [`QP_NUM_LOG - 1 : 0] sq_offset_record_addra; +wire [23:0] sq_offset_record_dina; +wire [23:0] sq_offset_record_douta; + +wire [0:0] sq_offset_record_web; +wire [`QP_NUM_LOG - 1 : 0] sq_offset_record_addrb; +wire [23:0] sq_offset_record_dinb; +wire [23:0] sq_offset_record_doutb; + +wire cache_owned_wea; +wire [CACHE_CELL_NUM_LOG - 1 : 0] cache_owned_addra; +wire [`QP_NUM_LOG - 1 : 0] cache_owned_dina; +wire [`QP_NUM_LOG - 1 : 0] cache_owned_douta; + +wire cache_owned_web; +wire [CACHE_CELL_NUM_LOG - 1 : 0] cache_owned_addrb; +wire [`QP_NUM_LOG - 1 : 0] cache_owned_dinb; +wire [`QP_NUM_LOG - 1 : 0] cache_owned_doutb; + +wire cache_offset_wea; +wire [`QP_NUM_LOG - 1 : 0] cache_offset_addra; +wire [`SQ_CACHE_SLOT_NUM_LOG - 1:0] cache_offset_dina; +wire [`SQ_CACHE_SLOT_NUM_LOG - 1:0] cache_offset_douta; + +wire cache_offset_web; +wire [`QP_NUM_LOG - 1 : 0] cache_offset_addrb; +wire [`SQ_CACHE_SLOT_NUM_LOG - 1:0] cache_offset_dinb; +wire [`SQ_CACHE_SLOT_NUM_LOG - 1:0] cache_offset_doutb; + +wire cache_buffer_wea; +wire [log2b(`SQ_CACHE_SLOT_NUM * `SQ_CACHE_CELL_NUM - 1) - 1 : 0] cache_buffer_addra; +wire [`WQE_SEG_WIDTH - 1 : 0] cache_buffer_dina; + +wire [log2b(`SQ_CACHE_SLOT_NUM * `SQ_CACHE_CELL_NUM - 1) - 1 : 0] cache_buffer_addrb; +wire [`WQE_SEG_WIDTH - 1 : 0] cache_buffer_doutb; + +wire wqe_valid; +wire [`WQE_PARSER_META_WIDTH - 1 : 0] wqe_head; +wire [`WQE_SEG_WIDTH - 1 : 0] wqe_data; +wire wqe_start; +wire wqe_last; +wire wqe_ready; + +wire sq_meta_valid; +wire [`SQ_META_WIDTH - 1 : 0] sq_meta_data; +wire sq_meta_ready; +/*------------------------------------------- Local Variables Definition : End --------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : Begin ---------------------------------------*/ +DBProc DBProc_Inst( + .clk ( clk ), + .rst ( rst ), + + .db_fifo_empty ( db_fifo_empty ), + .db_fifo_dout ( db_fifo_dout ), + .db_fifo_rd_en ( db_fifo_rd_en ), + + .qpn_fifo_valid ( chnl_0_qpn_valid ), + .qpn_fifo_data ( chnl_0_qpn_data ), + .qpn_fifo_ready ( chnl_0_qpn_ready ), + + .on_schedule_addr ( on_schedule_addrb ), + .on_schedule_dout ( on_schedule_doutb ), + + .sq_head_record_wen ( sq_head_record_wea ), + .sq_head_record_addr ( sq_head_record_addra ), + .sq_head_record_din ( sq_head_record_dina ), + .sq_head_record_dout ( sq_head_record_douta ) +); + +SQMetaProc SQMetaProc_Inst( + .clk ( clk ), + .rst ( rst ), + + .qpn_valid ( qpn_out_valid ), + .qpn_data ( qpn_out_data ), + .qpn_ready ( qpn_out_ready ), + + .fetch_cxt_ingress_valid ( fetch_cxt_ingress_valid ), + .fetch_cxt_ingress_head ( fetch_cxt_ingress_head ), + .fetch_cxt_ingress_data ( fetch_cxt_ingress_data ), + .fetch_cxt_ingress_start ( fetch_cxt_ingress_start ), + .fetch_cxt_ingress_last ( fetch_cxt_ingress_last ), + .fetch_cxt_ingress_ready ( fetch_cxt_ingress_ready ), + + .fetch_cxt_egress_valid ( fetch_cxt_egress_valid ), + .fetch_cxt_egress_head ( fetch_cxt_egress_head ), + .fetch_cxt_egress_data ( fetch_cxt_egress_data ), + .fetch_cxt_egress_start ( fetch_cxt_egress_start ), + .fetch_cxt_egress_last ( fetch_cxt_egress_last ), + .fetch_cxt_egress_ready ( fetch_cxt_egress_ready ), + + .fetch_mr_ingress_valid ( fetch_mr_ingress_valid ), + .fetch_mr_ingress_head ( fetch_mr_ingress_head ), + .fetch_mr_ingress_data ( fetch_mr_ingress_data ), + .fetch_mr_ingress_start ( fetch_mr_ingress_start ), + .fetch_mr_ingress_last ( fetch_mr_ingress_last ), + .fetch_mr_ingress_ready ( fetch_mr_ingress_ready ), + + .fetch_mr_egress_valid ( fetch_mr_egress_valid ), + .fetch_mr_egress_head ( fetch_mr_egress_head ), + .fetch_mr_egress_data ( fetch_mr_egress_data ), + .fetch_mr_egress_start ( fetch_mr_egress_start ), + .fetch_mr_egress_last ( fetch_mr_egress_last ), + .fetch_mr_egress_ready ( fetch_mr_egress_ready ), + + .sq_offset_wen ( sq_offset_record_wea ), + .sq_offset_addr ( sq_offset_record_addra ), + .sq_offset_din ( sq_offset_record_dina ), + .sq_offset_dout ( sq_offset_record_douta ), + + .sq_meta_valid ( sq_meta_valid ), + .sq_meta_data ( sq_meta_data ), + .sq_meta_ready ( sq_meta_ready ) +); + +WQECache +#( + .CACHE_SLOT_NUM ( CACHE_SLOT_NUM ), + .CACHE_SLOT_NUM_LOG ( CACHE_SLOT_NUM_LOG ), + + .CACHE_CELL_NUM ( CACHE_CELL_NUM ), + .CACHE_CELL_NUM_LOG ( CACHE_CELL_NUM_LOG ) +) +SQCache_Inst +( + .clk ( clk ), + .rst ( rst ), + + .cache_buffer_wea ( cache_buffer_wea ), + .cache_buffer_addra ( cache_buffer_addra ), + .cache_buffer_dina ( cache_buffer_dina ), + + .cache_buffer_addrb ( cache_buffer_addrb ), + .cache_buffer_doutb ( cache_buffer_doutb ), + + .cache_owned_wea ( cache_owned_wea ), + .cache_owned_addra ( cache_owned_addra ), + .cache_owned_dina ( cache_owned_dina ), + .cache_owned_douta ( cache_owned_douta ), + + .cache_owned_web ( cache_owned_web ), + .cache_owned_addrb ( cache_owned_addrb ), + .cache_owned_dinb ( cache_owned_dinb ), + .cache_owned_doutb ( cache_owned_doutb ), + + .cache_offset_wea ( cache_offset_wea ), + .cache_offset_addra ( cache_offset_addra ), + .cache_offset_dina ( cache_offset_dina ), + .cache_offset_douta ( cache_offset_douta ), + + .cache_offset_web ( cache_offset_web ), + .cache_offset_addrb ( cache_offset_addrb ), + .cache_offset_dinb ( cache_offset_dinb ), + .cache_offset_doutb ( cache_offset_doutb ) +); + +WQEFetch +#( + .CACHE_SLOT_NUM ( CACHE_SLOT_NUM ), + .CACHE_SLOT_NUM_LOG ( CACHE_SLOT_NUM_LOG ), + + .CACHE_CELL_NUM ( CACHE_CELL_NUM ), + .CACHE_CELL_NUM_LOG ( CACHE_CELL_NUM_LOG ) +) +WQEFetch_Inst +( + .clk ( clk ), + .rst ( rst ), + + .meta_valid ( sq_meta_valid ), + .meta_data ( sq_meta_data ), + .meta_ready ( sq_meta_ready ), + + .cache_buffer_wea ( cache_buffer_wea ), + .cache_buffer_addra ( cache_buffer_addra ), + .cache_buffer_dina ( cache_buffer_dina ), + + .cache_buffer_addrb ( cache_buffer_addrb ), + .cache_buffer_doutb ( cache_buffer_doutb ), + + .cache_owned_wen ( cache_owned_wea ), + .cache_owned_addr ( cache_owned_addra ), + .cache_owned_din ( cache_owned_dina ), + .cache_owned_dout ( cache_owned_douta ), + + .dma_rd_req_valid ( SQ_dma_rd_req_valid ), + .dma_rd_req_head ( SQ_dma_rd_req_head ), + .dma_rd_req_data ( SQ_dma_rd_req_data ), + .dma_rd_req_last ( SQ_dma_rd_req_last ), + .dma_rd_req_ready ( SQ_dma_rd_req_ready ), + + .dma_rd_rsp_valid ( SQ_dma_rd_rsp_valid ), + .dma_rd_rsp_head ( SQ_dma_rd_rsp_head ), + .dma_rd_rsp_data ( SQ_dma_rd_rsp_data ), + .dma_rd_rsp_last ( SQ_dma_rd_rsp_last ), + .dma_rd_rsp_ready ( SQ_dma_rd_rsp_ready ), + + .cache_offset_wen ( cache_offset_wea ), + .cache_offset_addr ( cache_offset_addra ), + .cache_offset_din ( cache_offset_dina ), + .cache_offset_dout ( cache_offset_douta ), + + .wqe_valid ( wqe_valid ), + .wqe_head ( wqe_head ), + .wqe_data ( wqe_data ), + .wqe_start ( wqe_start ), + .wqe_last ( wqe_last ), + .wqe_ready ( wqe_ready ) +); + +WQEParser +#( + .CACHE_SLOT_NUM ( CACHE_SLOT_NUM ), + .CACHE_SLOT_NUM_LOG ( CACHE_SLOT_NUM_LOG ), + + .CACHE_CELL_NUM ( CACHE_CELL_NUM ), + .CACHE_CELL_NUM_LOG ( CACHE_CELL_NUM_LOG ) +) +WQEParser_Inst +( + .clk ( clk ), + .rst ( rst ), + + .wqe_valid ( wqe_valid ), + .wqe_head ( wqe_head ), + .wqe_data ( wqe_data ), + .wqe_start ( wqe_start ), + .wqe_last ( wqe_last ), + .wqe_ready ( wqe_ready ), + + .cache_offset_wen ( cache_offset_web ), + .cache_offset_addr ( cache_offset_addrb ), + .cache_offset_din ( cache_offset_dinb ), + .cache_offset_dout ( cache_offset_doutb ), + + .on_schedule_wen ( on_schedule_wea ), + .on_schedule_addr ( on_schedule_addra ), + .on_schedule_din ( on_schedule_dina ), + + .sq_head_record_wen ( sq_head_record_web ), + .sq_head_record_addr ( sq_head_record_addrb ), + .sq_head_record_din ( sq_head_record_dinb ), + .sq_head_record_dout ( sq_head_record_doutb ), + + .sq_offset_wen ( sq_offset_record_web ), + .sq_offset_addr ( sq_offset_record_addrb ), + .sq_offset_din ( sq_offset_record_dinb ), + .sq_offset_dout ( sq_offset_record_doutb ), + + .cache_owned_wen ( cache_owned_web ), + .cache_owned_addr ( cache_owned_addrb ), + .cache_owned_din ( cache_owned_dinb ), + .cache_owned_dout ( cache_owned_doutb ), + + .sub_wqe_valid ( sub_wqe_valid ), + .sub_wqe_meta ( sub_wqe_meta ), + .sub_wqe_ready ( sub_wqe_ready ), + + .qpn_fifo_valid ( chnl_1_qpn_valid ), + .qpn_fifo_data ( chnl_1_qpn_data ), + .qpn_fifo_ready ( chnl_1_qpn_ready ), + + .ov_available_slot_num ( ov_available_slot_num ), + + .insert_req_valid ( insert_req_valid ), + .insert_req_start ( insert_req_start ), + .insert_req_last ( insert_req_last ), + .insert_req_head ( insert_req_head ), + .insert_req_data ( insert_req_data ), + .insert_req_ready ( insert_req_ready ), + + .insert_resp_valid ( insert_resp_valid ), + .insert_resp_data ( insert_resp_data ) +); + +SRAM_TDP_Template #( + .RAM_WIDTH ( 24 ), + .RAM_DEPTH ( `QP_NUM ) +) +SQOffsetRecordTable +( + .clk ( clk ), + .rst ( rst ), + + .wea ( sq_offset_record_wea ), + .addra ( sq_offset_record_addra ), + .dina ( sq_offset_record_dina ), + .douta ( sq_offset_record_douta ), + + .web ( sq_offset_record_web ), + .addrb ( sq_offset_record_addrb ), + .dinb ( sq_offset_record_dinb ), + .doutb ( sq_offset_record_doutb ) +); + +SRAM_TDP_Template #( + .RAM_WIDTH ( 24 ), + .RAM_DEPTH ( `QP_NUM ) +) +SQHeadRecordTable +( + .clk ( clk ), + .rst ( rst ), + + .wea ( sq_head_record_wea ), + .addra ( sq_head_record_addra ), + .dina ( sq_head_record_dina ), + .douta ( sq_head_record_douta ), + + .web ( sq_head_record_web ), + .addrb ( sq_head_record_addrb ), + .dinb ( sq_head_record_dinb ), + .doutb ( sq_head_record_doutb ) +); + +SRAM_SDP_Template #( + .RAM_WIDTH ( 1 ), + .RAM_DEPTH ( `QP_NUM ) +) +OnScheduleRecordTable +( + .clk ( clk ), + .rst ( rst ), + + .wea ( on_schedule_wea ), + .addra ( on_schedule_addra ), + .dina ( on_schedule_dina ), + + .addrb ( on_schedule_addrb ), + .doutb ( on_schedule_doutb ) +); + +AXISArbiter +#( + .HEAD_WIDTH ( 16 ), + .DATA_WIDTH ( 24 ) +) +QPNArbiter_Inst +( + .clk, + .rst, + + .in_axis_valid_a ( chnl_0_qpn_valid ), + .in_axis_head_a ( 'd0 ), + .in_axis_data_a ( chnl_0_qpn_data ), + .in_axis_start_a ( chnl_0_qpn_valid ), + .in_axis_last_a ( chnl_0_qpn_valid ), + .in_axis_ready_a ( chnl_0_qpn_ready ), + + .in_axis_valid_b ( chnl_1_qpn_valid ), + .in_axis_head_b ( 'd0 ), + .in_axis_data_b ( chnl_1_qpn_data ), + .in_axis_start_b ( chnl_1_qpn_valid ), + .in_axis_last_b ( chnl_1_qpn_valid ), + .in_axis_ready_b ( chnl_1_qpn_ready ), + + .out_axis_valid ( qpn_in_valid ), + .out_axis_head ( ), + .out_axis_data ( qpn_in_data ), + .out_axis_start ( ), + .out_axis_last ( ), + .out_axis_ready ( qpn_in_ready ) +); + +SyncFIFO_Template #( + .FIFO_TYPE ( 0 ), + .FIFO_WIDTH ( 24 ), + .FIFO_DEPTH ( `QP_NUM ) +) +QPNFIFO_Inst +( + .clk ( clk ), + .rst ( rst ), + + .wr_en ( qpn_in_valid ), + .din ( qpn_in_data ), + .prog_full ( qpn_in_prog_full ), + + .rd_en ( qpn_out_ready ), + .dout ( qpn_out_data ), + .empty ( qpn_out_empty ) +); + +assign qpn_in_ready = !qpn_in_prog_full; +assign qpn_out_valid = !qpn_out_empty; +/*------------------------------------------- Submodules Instatiation : End -----------------------------------------*/ + +/*------------------------------------------- State Machine Definition : Begin --------------------------------------*/ +/*------------------------------------------- State Machine Definition : End ----------------------------------------*/ + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ + +/*------------------------------------------- Local Macros Undef : Begin --------------------------------------------*/ +/*------------------------------------------- Local Macros Undef : End ----------------------------------------------*/ + +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/QueueSubsystem/SQMgt/WQEParser.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/QueueSubsystem/SQMgt/WQEParser.v new file mode 100644 index 0000000000000000000000000000000000000000..87501dc4aa9df5e5bcdb866537cc23ced6427c85 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/QueueSubsystem/SQMgt/WQEParser.v @@ -0,0 +1,1496 @@ +/*------------------------------------------- Module Description : Begin ---------------------------------------------- +Name: WQEParser +Author: YangFan +Function: 1.Parse Send WQE, split a WQE into sub-WQEs, which carries MTU-less data. + 2.Synchronize with WQECache(update cache offset table and cache owned table), which helps WQEFetch decide how to fetch WQE. + 3.Update SQ Offset Status(Each time finish a WQE, move SQ offset pointer forward). +--------------------------------------------- Module Decription : End -----------------------------------------------*/ + +/*------------------------------------------- Timescale Definition : Begin ------------------------------------------*/ +`timescale 1ns / 1ps +/*------------------------------------------- Timescale Definition : End --------------------------------------------*/ + +/*------------------------------------------- Included Files : Begin ------------------------------------------------*/ +`include "protocol_engine_def.vh" +/*------------------------------------------- Included Files : End --------------------------------------------------*/ + +/*------------------------------------------- Input/Output Definition : Begin ---------------------------------------*/ +module WQEParser +#( + parameter CACHE_SLOT_NUM = 256, + parameter CACHE_SLOT_NUM_LOG = log2b(CACHE_SLOT_NUM), + + parameter CACHE_CELL_NUM = 256, + parameter CACHE_CELL_NUM_LOG = log2b(CACHE_CELL_NUM) +) +( + input wire clk, + input wire rst, + +//Interface with WQEFetch + input wire wqe_valid, + input wire [`WQE_PARSER_META_WIDTH - 1 : 0] wqe_head, + input wire [`WQE_SEG_WIDTH - 1 : 0] wqe_data, + input wire wqe_start, + input wire wqe_last, + output wire wqe_ready, + +//Interface with Cache Offset + output reg cache_offset_wen, + output reg [`QP_NUM_LOG - 1 : 0] cache_offset_addr, + output reg [CACHE_SLOT_NUM_LOG - 1:0] cache_offset_din, + input wire [CACHE_SLOT_NUM_LOG - 1:0] cache_offset_dout, + + +//Interface with OnScheduleRecord + output reg on_schedule_wen, + output reg [23:0] on_schedule_addr, + output reg [0:0] on_schedule_din, + +//Interface with SQHeadRecord + output reg sq_head_record_wen, + output reg [`QP_NUM_LOG - 1 : 0] sq_head_record_addr, + output reg [23:0] sq_head_record_din, + input wire [23:0] sq_head_record_dout, + +//Interface with SQOffsetTable + output reg [0:0] sq_offset_wen, + output reg [`QP_NUM_LOG - 1 : 0] sq_offset_addr, + output reg [23:0] sq_offset_din, + input wire [23:0] sq_offset_dout, + +//Interface with CacheOwnedTable + output reg cache_owned_wen, + output reg [CACHE_CELL_NUM_LOG - 1 : 0] cache_owned_addr, + output reg [`QP_NUM_LOG - 1 : 0] cache_owned_din, + input wire [`QP_NUM_LOG - 1 : 0] cache_owned_dout, + +//Interface with QPNArbiter + output wire qpn_fifo_valid, + output wire [23:0] qpn_fifo_data, + input wire qpn_fifo_ready, + +//Interface with RDMACore + output wire sub_wqe_valid, + output wire [`WQE_META_WIDTH - 1 : 0] sub_wqe_meta, + input wire sub_wqe_ready, + +//Interface with DynamicBuffer(Payload Buffer) + input wire [`INLINE_PAYLOAD_BUFFER_SLOT_NUM_LOG : 0] ov_available_slot_num, + + output wire insert_req_valid, + output wire insert_req_start, + output wire insert_req_last, + output wire [`INLINE_PAYLOAD_BUFFER_SLOT_NUM_LOG - 1 : 0] insert_req_head, + output wire [`INLINE_PAYLOAD_BUFFER_SLOT_WIDTH - 1 : 0] insert_req_data, + input wire insert_req_ready, + + input wire insert_resp_valid, + input wire [`INLINE_PAYLOAD_BUFFER_SLOT_WIDTH - 1 : 0] insert_resp_data +); +/*------------------------------------------- Input/Output Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Macros Definition : Begin ---------------------------------------*/ +`define LOCAL_QPN_OFFSET 15:0 +`define REMOTE_QPN_OFFSET 31:16 +`define DMAC_OFFSET 175:128 +`define SMAC_OFFSET 223:176 +`define DIP_OFFSET 255:224 +`define SIP_OFFSET 287:256 +`define SQ_ENTRY_SZ_LOG_OFFSET 47:40 +`define SERVICE_TYPE_OFFSET 34:32 +`define PMTU_OFFSET 63:48 +`define SQ_LENGTH_OFFSET 95:64 + +/*------------------------------------------- Local Macros Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Variables Definition : Begin ------------------------------------*/ +//Passed from WQEFetch +reg [23:0] meta_local_qpn; +reg [23:0] meta_remote_qpn; +reg [2:0] meta_service_type; +reg [15:0] meta_pmtu; +reg [7:0] meta_sq_entry_sz_log; +reg [31:0] meta_sq_length; +reg [47:0] meta_dmac; +reg [47:0] meta_smac; +reg [31:0] meta_dip; +reg [31:0] meta_sip; + +//Next Unit Field +reg [4:0] NextUnit_next_wqe_opcode; +reg [0:0] NextUnit_next_wqe_valid; +reg [25:0] NextUnit_next_wqe_addr; +reg [5:0] NextUnit_next_wqe_size; +reg [7:0] NextUnit_next_wqe_size_aligned; +reg [0:0] NextUnit_next_wqe_dbd; +reg [23:0] NextUnit_next_wqe_ee; +reg [0:0] NextUnit_cur_wqe_fence; +reg [7:0] NextUnit_cur_wqe_size; +reg [7:0] NextUnit_cur_wqe_size_aligned; +reg [4:0] NextUnit_cur_wqe_opcode; +reg [31:0] NextUnit_cur_wqe_imm; + +//Raddr Unit field +wire [63:0] RaddrUnit_raddr; +wire [31:0] RaddrUnit_rkey; + +//UD Unit field +wire [7:0] UDUnit_port; +wire [15:0] UDUnit_dmac_low; +wire [31:0] UDUnit_dmac_high; +wire [15:0] UDUnit_smac_low; +wire [31:0] UDUnit_smac_high; +wire [31:0] UDUnit_dip; +wire [31:0] UDUnit_sip; +wire [31:0] UDUnit_dqpn; +wire [31:0] UDUnit_qkey; + +//Inline Unit field +wire [0:0] InlineUnit_inline_flag; +wire [30:0] InlineUnit_length; + +//DataUnit +wire [31:0] DataUnit_byte_cnt; +wire [31:0] DataUnit_lkey; +wire [63:0] DataUnit_laddr; + +//Passed to RDMACore +reg [23:0] SubWQE_local_qpn; +reg [23:0] SubWQE_remote_qpn; +reg [4:0] SubWQE_verbs_opcode; +reg [4:0] SubWQE_net_opcode; +reg [2:0] SubWQE_service_type; +reg [0:0] SubWQE_fence; +reg [0:0] SubWQE_solicited_event; +reg [0:0] SubWQE_wqe_head; +reg [0:0] SubWQE_wqe_tail; +reg [0:0] SubWQE_inline; +reg [23:0] SubWQE_ori_wqe_offset; +reg [47:0] SubWQE_dmac; +reg [47:0] SubWQE_smac; +reg [31:0] SubWQE_dip; +reg [31:0] SubWQE_sip; +reg [31:0] SubWQE_immediate; +reg [31:0] SubWQE_lkey; +reg [63:0] SubWQE_laddr; +reg [31:0] SubWQE_rkey; +reg [63:0] SubWQE_raddr; +reg [31:0] SubWQE_msg_length; +reg [15:0] SubWQE_packet_length; + +reg msg_offset_wea; +reg [`QP_NUM_LOG - 1 : 0] msg_offset_addra; +reg [31:0] msg_offset_dina; +wire [`QP_NUM_LOG - 1 : 0] msg_offset_addrb; +wire [31:0] msg_offset_doutb; + +reg [31:0] inline_payload_start_addr; + +reg [31:0] parsed_msg_length; +reg data_unit_parse_finish; + +reg [15:0] insert_count; +reg [15:0] insert_total; + +reg [0:0] reschedule_flag; +/*------------------------------------------- Local Variables Definition : End --------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : Begin ---------------------------------------*/ +SRAM_SDP_Template #( + .RAM_WIDTH ( 32 ), //Record msg offset of each WQE + .RAM_DEPTH ( `QP_NUM ) +) +MsgOffsetTable +( + .clk ( clk ), + .rst ( rst ), + + .wea ( msg_offset_wea ), + .addra ( msg_offset_addra ), + .dina ( msg_offset_dina ), + + .addrb ( msg_offset_addrb ), + .doutb ( msg_offset_doutb ) +); + +/*------------------------------------------- Submodules Instatiation : End -----------------------------------------*/ + +/*------------------------------------------- State Machine Definition : Begin --------------------------------------*/ +reg [3:0] cur_state; +reg [3:0] next_state; + +parameter [3:0] IDLE_s = 4'd1, + NEXT_UNIT_s = 4'd2, + RADDR_UNIT_s = 4'd3, + UD_UNIT_1_s = 4'd4, + UD_UNIT_2_s = 4'd5, + UD_UNIT_3_s = 4'd6, + JUDGE_s = 4'd7, + INLINE_JUDGE_s = 4'd8, + INLINE_UNIT_s = 4'd9, + INLINE_DATA_s = 4'd10, + DATA_UNIT_s = 4'd11, + INJECT_s = 4'd12, + RESCHEDULE_s = 4'd13; + +always @(posedge clk or posedge rst) begin + if(rst) begin + cur_state <= IDLE_s; + end + else begin + cur_state <= next_state; + end +end + +always @(*) begin + case(cur_state) + IDLE_s: if(wqe_valid) begin + next_state = NEXT_UNIT_s; + end + else begin + next_state = IDLE_s; + end + NEXT_UNIT_s: if(meta_service_type == `RC || meta_service_type == `UC) begin + if(wqe_data[`NEXT_UNIT_CUR_WQE_OPCODE_OFFSET] == `VERBS_SEND || wqe_data[`NEXT_UNIT_CUR_WQE_OPCODE_OFFSET] == `VERBS_SEND_WITH_IMM) begin + next_state = INLINE_JUDGE_s; + end + else if(wqe_data[`NEXT_UNIT_CUR_WQE_OPCODE_OFFSET] == `VERBS_RDMA_WRITE || wqe_data[`NEXT_UNIT_CUR_WQE_OPCODE_OFFSET] == `VERBS_RDMA_WRITE_WITH_IMM || wqe_data[`NEXT_UNIT_CUR_WQE_OPCODE_OFFSET] == `VERBS_RDMA_READ) begin + next_state = RADDR_UNIT_s; + end + else begin + next_state = IDLE_s; + end + end + else if(meta_service_type == `UD) begin + next_state = UD_UNIT_1_s; + end + else begin + next_state = IDLE_s; + end + RADDR_UNIT_s: if(wqe_valid) begin + next_state = INLINE_JUDGE_s; + end + else begin + next_state = RADDR_UNIT_s; + end + UD_UNIT_1_s: if(wqe_valid) begin + next_state = UD_UNIT_2_s; + end + else begin + next_state = UD_UNIT_1_s; + end + UD_UNIT_2_s: if(wqe_valid) begin + next_state = UD_UNIT_3_s; + end + else begin + next_state = UD_UNIT_2_s; + end + UD_UNIT_3_s: if(wqe_valid) begin + next_state = DATA_UNIT_s; + end + else begin + next_state = UD_UNIT_3_s; + end + INLINE_JUDGE_s: if(wqe_valid) begin + if(InlineUnit_inline_flag) begin + next_state = INLINE_UNIT_s; + end + else begin + next_state = DATA_UNIT_s; + end + end + else begin + next_state = INLINE_JUDGE_s; + end + INLINE_UNIT_s: if(wqe_valid) begin + next_state = INLINE_DATA_s; + end + else begin + next_state = INLINE_UNIT_s; + end + INLINE_DATA_s: if(wqe_valid && insert_req_valid && insert_req_ready) begin + if(wqe_last) begin + next_state = INJECT_s; + end + else begin + next_state = INLINE_DATA_s; + end + end + else begin + next_state = INLINE_DATA_s; + end + DATA_UNIT_s: if(wqe_valid && wqe_last) begin + next_state = INJECT_s; + end + else begin + next_state = DATA_UNIT_s; + end + INJECT_s: if(sub_wqe_valid && sub_wqe_ready) begin + if(reschedule_flag) begin + next_state = RESCHEDULE_s; + end + else begin + next_state = IDLE_s; + end + end + else begin + next_state = INJECT_s; + end + RESCHEDULE_s: if(qpn_fifo_ready) begin + next_state = IDLE_s; + end + else begin + next_state = RESCHEDULE_s; + end + default: next_state = IDLE_s; + endcase +end +/*------------------------------------------- State Machine Definition : End ----------------------------------------*/ + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ +//-- meta_local_qpn -- +//-- meta_remote_qpn -- +//-- meta_service_type -- +//-- meta_sq_entry_sz_log -- +//-- meta_sq_length -- +//-- meta_dmac -- +//-- meta_smac -- +//-- meta_dip -- +//-- meta_sip -- +always @(posedge clk or posedge rst) begin + if(rst) begin + meta_local_qpn <= 'd0; + meta_remote_qpn <= 'd0; + meta_service_type <= 'd0; + meta_sq_entry_sz_log <= 'd0; + meta_sq_length <= 'd0; + meta_dmac <= 'd0; + meta_smac <= 'd0; + meta_dip <= 'd0; + meta_sip <= 'd0; + meta_pmtu <= 'd0; + end + else if(cur_state == IDLE_s && wqe_valid) begin + meta_local_qpn <= wqe_head[`LOCAL_QPN_OFFSET]; + meta_remote_qpn <= wqe_head[`REMOTE_QPN_OFFSET]; + meta_service_type <= wqe_head[`SERVICE_TYPE_OFFSET]; + meta_sq_entry_sz_log <= wqe_head[`SQ_ENTRY_SZ_LOG_OFFSET]; + meta_sq_length <= wqe_head[`SQ_LENGTH_OFFSET]; + meta_dmac <= wqe_head[`DMAC_OFFSET]; + meta_smac <= wqe_head[`SMAC_OFFSET]; + meta_dip <= wqe_head[`DIP_OFFSET]; + meta_sip <= wqe_head[`SIP_OFFSET]; + meta_pmtu <= wqe_head[`PMTU_OFFSET]; + end + else begin + meta_local_qpn <= meta_local_qpn; + meta_remote_qpn <= meta_remote_qpn; + meta_service_type <= meta_service_type; + meta_sq_entry_sz_log <= meta_sq_entry_sz_log; + meta_sq_length <= meta_sq_length; + meta_dmac <= meta_dmac; + meta_smac <= meta_smac; + meta_dip <= meta_dip; + meta_sip <= meta_sip; + meta_pmtu <= meta_pmtu; + end +end + +wire [31:0] cur_wqe_size; +wire [31:0] next_wqe_size; +assign cur_wqe_size = wqe_data[`NEXT_UNIT_CUR_WQE_SIZE_OFFSET]; +assign next_wqe_size = wqe_data[`NEXT_UNIT_NEXT_WQE_SIZE_OFFSET]; + +//Next Unit Field +//-- NextUnit_next_wqe_opcode -- +//-- NextUnit_next_wqe_valid -- +//-- NextUnit_next_wqe_addr -- +//-- NextUnit_next_wqe_size -- +//-- NextUnit_next_wqe_size_aligned -- +//-- NextUnit_next_wqe_dbd -- +//-- NextUnit_next_wqe_ee -- +//-- NextUnit_cur_wqe_fence -- +//-- NextUnit_cur_wqe_size -- +//-- NextUnit_cur_wqe_size_aligned -- +//-- NextUnit_cur_wqe_opcode -- +//-- NextUnit_cur_wqe_imm -- +always @(posedge clk or posedge rst) begin + if(rst) begin + NextUnit_next_wqe_opcode <= 'd0; + NextUnit_next_wqe_valid <= 'd0; + NextUnit_next_wqe_addr <= 'd0; + NextUnit_next_wqe_size <= 'd0; + NextUnit_next_wqe_size_aligned <= 'd0; + NextUnit_next_wqe_dbd <= 'd0; + NextUnit_next_wqe_ee <= 'd0; + NextUnit_cur_wqe_fence <= 'd0; + NextUnit_cur_wqe_size <= 'd0; + NextUnit_cur_wqe_size_aligned <= 'd0; + NextUnit_cur_wqe_opcode <= 'd0; + NextUnit_cur_wqe_imm <= 'd0; + end + else if(cur_state == NEXT_UNIT_s && wqe_valid) begin + NextUnit_next_wqe_opcode <= wqe_data[`NEXT_UNIT_NEXT_WQE_OPCODE_OFFSET]; + NextUnit_next_wqe_valid <= (wqe_data[`NEXT_UNIT_NEXT_WQE_SIZE_OFFSET] != 0); + NextUnit_next_wqe_addr <= wqe_data[`NEXT_UNIT_NEXT_WQE_ADDR_OFFSET]; + NextUnit_next_wqe_size <= wqe_data[`NEXT_UNIT_NEXT_WQE_SIZE_OFFSET]; + + case(meta_sq_entry_sz_log) //minimum 64, maximum 1024 + 6: NextUnit_next_wqe_size_aligned <= (next_wqe_size % 4) ? (next_wqe_size[31:2] + 32'd1) * 4 : next_wqe_size[31:2] * 4; + 7: NextUnit_next_wqe_size_aligned <= (next_wqe_size % 8) ? (next_wqe_size[31:3] + 32'd1) * 8 : next_wqe_size[31:3] * 8; + 8: NextUnit_next_wqe_size_aligned <= (next_wqe_size % 16) ? (next_wqe_size[31:4] + 32'd1) * 16 : next_wqe_size[31:4] * 16; + 9: NextUnit_next_wqe_size_aligned <= (next_wqe_size % 32) ? (next_wqe_size[31:5] + 32'd1) * 32 : next_wqe_size[31:5] * 32; + 10: NextUnit_next_wqe_size_aligned <= (next_wqe_size % 64) ? (next_wqe_size[31:6] + 32'd1) * 64 : next_wqe_size[31:6] * 64; + default: NextUnit_next_wqe_size_aligned <= 'd0; + endcase + + NextUnit_next_wqe_dbd <= wqe_data[`NEXT_UNIT_NEXT_WQE_DBD_OFFSET]; + NextUnit_next_wqe_ee <= wqe_data[`NEXT_UNIT_NEXT_WQE_EE_OFFSET]; + NextUnit_cur_wqe_fence <= wqe_data[`NEXT_UNIT_CUR_WQE_FENCE_OFFSET]; + NextUnit_cur_wqe_size <= wqe_data[`NEXT_UNIT_CUR_WQE_SIZE_OFFSET]; + + case(meta_sq_entry_sz_log) //minimum 64, maximum 1024 + 6: NextUnit_cur_wqe_size_aligned <= (cur_wqe_size % 4) ? (cur_wqe_size[31:2] + 32'd1) * 4 : cur_wqe_size[31:2] * 4; + 7: NextUnit_cur_wqe_size_aligned <= (cur_wqe_size % 8) ? (cur_wqe_size[31:3] + 32'd1) * 8 : cur_wqe_size[31:3] * 8; + 8: NextUnit_cur_wqe_size_aligned <= (cur_wqe_size % 16) ? (cur_wqe_size[31:4] + 32'd1) * 16 : cur_wqe_size[31:4] * 16; + 9: NextUnit_cur_wqe_size_aligned <= (cur_wqe_size % 32) ? (cur_wqe_size[31:5] + 32'd1) * 32 : cur_wqe_size[31:5] * 32; + 10: NextUnit_cur_wqe_size_aligned <= (cur_wqe_size % 64) ? (cur_wqe_size[31:6] + 32'd1) * 64 : cur_wqe_size[31:6] * 64; + default: NextUnit_cur_wqe_size_aligned <= 'd0; + endcase + NextUnit_cur_wqe_opcode <= wqe_data[`NEXT_UNIT_CUR_WQE_OPCODE_OFFSET]; + NextUnit_cur_wqe_imm <= wqe_data[`NEXT_UNIT_CUR_WQE_IMM_OFFSET]; + end + else begin + NextUnit_next_wqe_opcode <= NextUnit_next_wqe_opcode; + NextUnit_next_wqe_valid <= NextUnit_next_wqe_valid; + NextUnit_next_wqe_addr <= NextUnit_next_wqe_addr; + NextUnit_next_wqe_size <= NextUnit_next_wqe_size; + NextUnit_next_wqe_size_aligned <= NextUnit_next_wqe_size_aligned; + NextUnit_next_wqe_dbd <= NextUnit_next_wqe_dbd; + NextUnit_next_wqe_ee <= NextUnit_next_wqe_ee; + NextUnit_cur_wqe_fence <= NextUnit_cur_wqe_fence; + NextUnit_cur_wqe_size <= NextUnit_cur_wqe_size; + NextUnit_cur_wqe_size_aligned <= NextUnit_cur_wqe_size_aligned; + NextUnit_cur_wqe_opcode <= NextUnit_cur_wqe_opcode; + NextUnit_cur_wqe_imm <= NextUnit_cur_wqe_imm; + end +end + +//Raddr Unit field +//-- RaddrUnit_raddr -- +//-- RaddrUnit_rkey -- +assign RaddrUnit_raddr = (cur_state == RADDR_UNIT_s && wqe_valid) ? wqe_data[`RADDR_UNIT_RADDR_OFFSET] : 'd0; +assign RaddrUnit_rkey = (cur_state == RADDR_UNIT_s && wqe_valid) ? wqe_data[`RADDR_UNIT_RKEY_OFFSET] : 'd0; + +//UD Unit field +//-- UDUnit_port -- +//-- UDUnit_dmac_low -- +//-- UDUnit_dmac_high -- +//-- UDUnit_smac_low -- +//-- UDUnit_smac_high -- +//-- UDUnit_dip -- +//-- UDUnit_sip -- +//-- UDUnit_dqpn -- +//-- UDUnit_qkey -- +assign UDUnit_port = (cur_state == UD_UNIT_1_s && wqe_valid) ? wqe_data[`UD_UNIT_PORT_OFFSET] : 'd0; +assign UDUnit_dmac_low = (cur_state == UD_UNIT_1_s && wqe_valid) ? wqe_data[`UD_UNIT_DMAC_LOW_OFFSET] : 'd0; +assign UDUnit_dmac_high = (cur_state == UD_UNIT_1_s && wqe_valid) ? wqe_data[`UD_UNIT_DMAC_HIGH_OFFSET] : 'd0; +assign UDUnit_smac_low = (cur_state == UD_UNIT_1_s && wqe_valid) ? wqe_data[`UD_UNIT_SMAC_LOW_OFFSET] : 'd0; +assign UDUnit_smac_high = (cur_state == UD_UNIT_1_s && wqe_valid) ? wqe_data[`UD_UNIT_SMAC_HIGH_OFFSET] : 'd0; +assign UDUnit_dip = (cur_state == UD_UNIT_2_s && wqe_valid) ? wqe_data[`UD_UNIT_DIP_OFFSET] : 'd0; +assign UDUnit_sip = (cur_state == UD_UNIT_2_s && wqe_valid) ? wqe_data[`UD_UNIT_SIP_OFFSET] : 'd0; +assign UDUnit_dqpn = (cur_state == UD_UNIT_3_s && wqe_valid) ? wqe_data[`UD_UNIT_REMOTE_QPN_OFFSET] : 'd0; +assign UDUnit_qkey = (cur_state == UD_UNIT_3_s && wqe_valid) ? wqe_data[`UD_UNIT_QKEY_OFFSET] : 'd0; + +//Inline Unit field +//-- InlineUnit_inline_flag -- +//-- InlineUnit_length -- +assign InlineUnit_inline_flag = ((cur_state == JUDGE_s || cur_state == INLINE_UNIT_s) && wqe_valid) ? wqe_data[`DATA_UNIT_INLINE_OFFSET] : 'd0; +assign InlineUnit_length = ((cur_state == JUDGE_s || cur_state == INLINE_UNIT_s) && wqe_valid) ? wqe_data[`DATA_UNIT_INLINE_OFFSET] : 'd0; + +//DataUnit +//-- DataUnit_byte_cnt -- +//-- DataUnit_lkey -- +//-- DataUnit_laddr -- +assign DataUnit_byte_cnt = ((cur_state == JUDGE_s || cur_state == DATA_UNIT_s) && wqe_valid) ? wqe_data[`DATA_UNIT_BYTE_CNT_OFFSET] : 'd0; +assign DataUnit_lkey = ((cur_state == JUDGE_s || cur_state == DATA_UNIT_s) && wqe_valid) ? wqe_data[`DATA_UNIT_LKEY_OFFSET] : 'd0; +assign DataUnit_laddr = ((cur_state == JUDGE_s || cur_state == DATA_UNIT_s) && wqe_valid) ? wqe_data[`DATA_UNIT_LADDR_OFFSET] : 'd0; + +//-- inline_payload_start_addr -- +always @(posedge clk or posedge rst) begin + if(rst) begin + inline_payload_start_addr <= 'd0; + end + else if(cur_state == IDLE_s) begin + inline_payload_start_addr <= 'd0; + end + else if(cur_state == INLINE_DATA_s && wqe_valid && insert_req_valid && insert_req_start && insert_req_ready && insert_resp_valid) begin + inline_payload_start_addr <= insert_resp_data; //Address of first flit of inline data + end + else begin + inline_payload_start_addr <= inline_payload_start_addr; + end +end + +//-- msg_offset_wea -- +//-- msg_offset_addra -- +//-- msg_offset_dina -- +always @(*) begin + if (rst) begin + msg_offset_wea = 'd0; + msg_offset_addra = 'd0; + msg_offset_dina = 'd0; + end + else if (cur_state == INLINE_UNIT_s) begin + msg_offset_wea = 'd1; + msg_offset_addra = meta_local_qpn; + msg_offset_dina = 'd0; + end + else if (cur_state == DATA_UNIT_s && wqe_valid && !data_unit_parse_finish) begin + if(parsed_msg_length + DataUnit_byte_cnt <= msg_offset_doutb) begin + msg_offset_wea = 'd0; + msg_offset_addra = meta_local_qpn; + msg_offset_dina = 'd0; + end + else if(wqe_last && (parsed_msg_length + DataUnit_byte_cnt - msg_offset_doutb <= meta_pmtu)) begin //Current WQE is finished, clean MSG offset for next WQE. + msg_offset_wea = 'd1; + msg_offset_addra = meta_local_qpn; + msg_offset_dina = 'd0; + end + else if(wqe_last && (parsed_msg_length + DataUnit_byte_cnt - msg_offset_doutb > meta_pmtu)) begin + msg_offset_wea = 'd1; + msg_offset_addra = meta_local_qpn; + msg_offset_dina = msg_offset_doutb + meta_pmtu; + end + else if(!wqe_last && (parsed_msg_length + DataUnit_byte_cnt - msg_offset_doutb <= meta_pmtu)) begin + msg_offset_wea = 'd1; + msg_offset_addra = meta_local_qpn; + msg_offset_dina = msg_offset_doutb + (parsed_msg_length + DataUnit_byte_cnt - msg_offset_doutb); + end + else if(!wqe_last && (parsed_msg_length + DataUnit_byte_cnt - msg_offset_doutb > meta_pmtu)) begin + msg_offset_wea = 'd1; + msg_offset_addra = meta_local_qpn; + msg_offset_dina = msg_offset_doutb + meta_pmtu; + end + else begin + msg_offset_wea = 'd0; + msg_offset_addra = meta_local_qpn; + msg_offset_dina = 'd0; + end + end + else begin + msg_offset_wea = 'd0; + msg_offset_addra = meta_local_qpn; + msg_offset_dina = 'd0; + end +end + +//-- msg_offset_addrb -- +assign msg_offset_addrb = meta_local_qpn; + +//-- cache_offset_wen -- +//-- cache_offset_addr -- +//-- cache_offset_din -- +always @(*) begin + if(rst) begin + cache_offset_wen = 'd0; + cache_offset_addr = 'd0; + cache_offset_din = 'd0; + end + else if(cur_state == NEXT_UNIT_s) begin + cache_offset_wen = 'd0; + cache_offset_addr = meta_local_qpn; + cache_offset_din = 'd0; + end + else if(cur_state == INLINE_UNIT_s && wqe_valid) begin //Current WQE is finished, update cache offset + if(!NextUnit_next_wqe_valid) begin + cache_offset_wen = 'd1; + cache_offset_addr = meta_local_qpn; + cache_offset_din = 'd0; + end + else if(NextUnit_next_wqe_addr < sq_offset_dout) begin //SQ wrap back + cache_offset_wen = 'd1; + cache_offset_addr = meta_local_qpn; + cache_offset_din = 'd0; + end + else if(cache_offset_dout + (NextUnit_next_wqe_addr - sq_offset_dout) + NextUnit_next_wqe_size > CACHE_SLOT_NUM) begin //Next WQE cross Cache Block boundary + cache_offset_wen = 'd1; + cache_offset_addr = meta_local_qpn; + cache_offset_din = 'd0; + end + else begin //Next WQE is in cache + cache_offset_wen = 'd1; + cache_offset_addr = meta_local_qpn; + cache_offset_din = cache_offset_dout + (NextUnit_next_wqe_addr - sq_offset_dout); + end + end + else if(cur_state == DATA_UNIT_s && wqe_valid && wqe_last && (parsed_msg_length + DataUnit_byte_cnt - msg_offset_doutb <= meta_pmtu) && !data_unit_parse_finish) begin + if(!NextUnit_next_wqe_valid) begin + cache_offset_wen = 'd1; + cache_offset_addr = meta_local_qpn; + cache_offset_din = 'd0; + end + else if(NextUnit_next_wqe_addr < sq_offset_dout) begin //SQ wrap back + cache_offset_wen = 'd1; + cache_offset_addr = meta_local_qpn; + cache_offset_din = 'd0; + end + else if(cache_offset_dout + (NextUnit_next_wqe_addr - sq_offset_dout) + NextUnit_next_wqe_size > CACHE_SLOT_NUM) begin //Next WQE cross Cache Block boundary + cache_offset_wen = 'd1; + cache_offset_addr = meta_local_qpn; + cache_offset_din = 'd0; + end + else begin //Next WQE is in cache + cache_offset_wen = 'd1; + cache_offset_addr = meta_local_qpn; + cache_offset_din = cache_offset_dout + (NextUnit_next_wqe_addr - sq_offset_dout); + end + end + else begin + cache_offset_wen = 'd0; + cache_offset_addr = meta_local_qpn; + cache_offset_din = 'd0; + end +end + +//-- on_schedule_wen -- +//-- on_schedule_addr -- +//-- on_schedule_din -- +always @(*) begin + if(rst) begin + on_schedule_wen = 'd0; + on_schedule_addr = 'd0; + on_schedule_din = 'd0; + end + else if(cur_state == INLINE_UNIT_s && wqe_valid) begin + if(NextUnit_next_wqe_valid) begin //Still got WQE to be scheduled + on_schedule_wen = 'd1; + on_schedule_addr = meta_local_qpn; + on_schedule_din = 'd1; + end + else if(!NextUnit_next_wqe_valid && (sq_head_record_dout == sq_offset_dout)) begin //No sq_head update through doorbell ringing + on_schedule_wen = 'd1; + on_schedule_addr = meta_local_qpn; + on_schedule_din = 'd0; + end + else if(!NextUnit_next_wqe_valid && (sq_head_record_dout != sq_offset_dout)) begin //SQ_Head is updated through doorbell ringing, new WQE list is available + on_schedule_wen = 'd1; + on_schedule_addr = meta_local_qpn; + on_schedule_din = 'd1; + end + else begin + on_schedule_wen = 'd0; + on_schedule_addr = 'd0; + on_schedule_din = 'd0; + end + end + else if(cur_state == DATA_UNIT_s && wqe_valid) begin + if(wqe_last && (parsed_msg_length + DataUnit_byte_cnt - msg_offset_doutb) <= meta_pmtu) begin //Current WQE is finished + if(NextUnit_next_wqe_valid) begin //Still got WQE to be scheduled + on_schedule_wen = 'd1; + on_schedule_addr = meta_local_qpn; + on_schedule_din = 'd1; + end + else if(!NextUnit_next_wqe_valid && (sq_head_record_dout != sq_offset_dout)) begin //SQ_Head is updated through doorbell ringing, new WQE list is available + on_schedule_wen = 'd1; + on_schedule_addr = meta_local_qpn; + on_schedule_din = 'd1; + end + else if(!NextUnit_next_wqe_valid && (sq_head_record_dout == sq_offset_dout)) begin //No sq_head update through doorbell ringing + on_schedule_wen = 'd1; + on_schedule_addr = meta_local_qpn; + on_schedule_din = 'd0; + end + else begin + on_schedule_wen = 'd0; + on_schedule_addr = 'd0; + on_schedule_din = 'd0; + end + end + else if(parsed_msg_length + DataUnit_byte_cnt > msg_offset_doutb) begin + on_schedule_wen = 'd1; + on_schedule_addr = meta_local_qpn; + on_schedule_din = 'd1; + end + else begin + on_schedule_wen = 'd0; + on_schedule_addr = 'd0; + on_schedule_din = 'd0; + end + end + else begin + on_schedule_wen = 'd0; + on_schedule_addr = 'd0; + on_schedule_din = 'd0; + end +end + +//-- reschedule_flag -- +always @(posedge clk or posedge rst) begin + if (rst) begin + reschedule_flag <= 'd0; + end + else if (cur_state == IDLE_s) begin + reschedule_flag <= 'd0; + end + else if (on_schedule_wen && on_schedule_din == 1) begin + reschedule_flag <= 'd1; + end + else begin + reschedule_flag <= reschedule_flag; + end +end + +// //-- sq_head_record_wen -- +// //-- sq_head_record_addr -- +// //-- sq_head_record_din -- +// always @(*) begin +// if(rst) begin +// sq_head_record_wen = 'd0; +// sq_head_record_addr = 'd0; +// sq_head_record_din = 'd0; +// end +// else if(cur_state == IDLE_s) begin +// sq_head_record_wen = 'd0; +// sq_head_record_addr = 'd0; +// sq_head_record_din = 'd0; +// end +// else if(cur_state == NEXT_UNIT_s) begin +// sq_head_record_wen = 'd0; +// sq_head_record_addr = meta_local_qpn; +// sq_head_record_din = 'd0; +// end +// else if(cur_state == INLINE_UNIT_s && wqe_valid) begin +// if(sq_offset_dout == sq_head_record_dout) begin //No Doorbell ringing during WQEParsing +// sq_head_record_wen = 'd1; +// sq_head_record_addr = meta_local_qpn; +// sq_head_record_din = sq_offset_dout + NextUnit_cur_wqe_size_aligned; +// end +// else begin //SQ head is updated through doorbell ringing, do not touch SQ head. +// sq_head_record_wen = 'd0; +// sq_head_record_addr = meta_local_qpn; +// sq_head_record_din = 'd0; +// end +// end +// else if(cur_state == DATA_UNIT_s && wqe_last && (parsed_msg_length + DataUnit_byte_cnt - msg_offset_doutb <= meta_pmtu)) begin +// if(sq_offset_dout == sq_head_record_dout) begin //No Doorbell ringing during WQEParsing +// sq_head_record_wen = 'd1; +// sq_head_record_addr = meta_local_qpn; +// sq_head_record_din = sq_offset_dout + NextUnit_cur_wqe_size_aligned; +// end +// else begin //SQ head is updated through doorbell ringing, do not touch SQ head. +// sq_head_record_wen = 'd0; +// sq_head_record_addr = meta_local_qpn; +// sq_head_record_din = 'd0; +// end +// end +// else begin +// sq_head_record_wen = 'd0; +// sq_head_record_addr = meta_local_qpn; +// sq_head_record_din = 'd0; +// end +// end + +//-- sq_offset_wen -- +//-- sq_offset_addr -- +//-- sq_offset_din -- +//-- sq_head_record_wen -- +//-- sq_head_record_addr -- +//-- sq_head_record_din -- +always @(*) begin + if(rst) begin + sq_offset_wen = 'd0; + sq_offset_addr = 'd0; + sq_offset_din = 'd0; + + sq_head_record_wen = 'd0; + sq_head_record_addr = 'd0; + sq_head_record_din = 'd0; + end + else if(cur_state == IDLE_s) begin + sq_offset_wen = 'd0; + sq_offset_addr = 'd0; + sq_offset_din = 'd0; + + sq_head_record_wen = 'd0; + sq_head_record_addr = 'd0; + sq_head_record_din = 'd0; + end + else if(cur_state == NEXT_UNIT_s) begin + sq_offset_wen = 'd0; + sq_offset_addr = meta_local_qpn; + sq_offset_din = 'd0; + + sq_head_record_wen = 'd0; + sq_head_record_addr = meta_local_qpn; + sq_head_record_din = 'd0; + end + else if(cur_state == INLINE_UNIT_s && wqe_valid) begin + sq_offset_wen = 'd1; + sq_offset_addr = meta_local_qpn; + sq_offset_din = meta_sq_length - (sq_offset_dout + NextUnit_cur_wqe_size_aligned) * 16 <= (32'd1 << meta_sq_entry_sz_log) ? 'd0 : sq_offset_dout + NextUnit_cur_wqe_size_aligned; + + if(sq_head_record_dout == sq_offset_dout) begin + sq_head_record_wen = 'd1; + sq_head_record_addr = meta_local_qpn; + sq_head_record_din = meta_sq_length - (sq_offset_dout + NextUnit_cur_wqe_size_aligned) * 16 <= (32'd1 << meta_sq_entry_sz_log) ? 'd0 : sq_offset_dout + NextUnit_cur_wqe_size_aligned; + end + else begin + sq_head_record_wen = 'd0; + sq_head_record_addr = 'd0; + sq_head_record_din = 'd0; + end + end + else if(cur_state == DATA_UNIT_s && wqe_last && (parsed_msg_length + DataUnit_byte_cnt - msg_offset_doutb <= meta_pmtu) && !data_unit_parse_finish) begin + sq_offset_wen = 'd1; + sq_offset_addr = meta_local_qpn; + sq_offset_din = meta_sq_length - (sq_offset_dout + NextUnit_cur_wqe_size_aligned) * 16 < (32'd1 << meta_sq_entry_sz_log) ? 'd0 : sq_offset_dout + NextUnit_cur_wqe_size_aligned; + + if(sq_head_record_dout == sq_offset_dout) begin + sq_head_record_wen = 'd1; + sq_head_record_addr = meta_local_qpn; + sq_head_record_din = meta_sq_length - (sq_offset_dout + NextUnit_cur_wqe_size_aligned) * 16 < (32'd1 << meta_sq_entry_sz_log) ? 'd0 : sq_offset_dout + NextUnit_cur_wqe_size_aligned; + end + else begin + sq_head_record_wen = 'd0; + sq_head_record_addr = 'd0; + sq_head_record_din = 'd0; + end + end + else begin + sq_offset_wen = 'd0; + sq_offset_addr = meta_local_qpn; + sq_offset_din = 'd0; + + sq_head_record_wen = 'd0; + sq_head_record_addr = meta_local_qpn; + sq_head_record_din = 'd0; + end +end + +// TODO, need to synchronize with WQEFetcher, helping it distinguish whether WQE cache buffer is valid +// cache_owned_wen -- +// cache_owned_addr -- +// cache_owned_din -- +always @(*) begin + if(rst) begin + cache_owned_wen = 'd0; + cache_owned_addr = 'd0; + cache_owned_din = 'd0; + end + else if(cur_state == IDLE_s) begin + cache_owned_wen = 'd0; + cache_owned_addr = 'd0; + cache_owned_din = 'd0; + end + else if(cur_state == NEXT_UNIT_s) begin + cache_owned_wen = 'd0; + cache_owned_addr = meta_local_qpn; + cache_owned_din = 'd0; + end + else if(cur_state == DATA_UNIT_s && wqe_last && (parsed_msg_length + DataUnit_byte_cnt - msg_offset_doutb <= meta_pmtu) && !data_unit_parse_finish) begin //Current WQE has been finished + if(cache_owned_dout[`QP_NUM_LOG - CACHE_CELL_NUM_LOG - 1 : 0] != meta_local_qpn[`QP_NUM_LOG - 1 : 4]) begin //Curretn cell is already been replaced by another QP, do not touch it + cache_owned_wen = 'd0; + cache_owned_addr = meta_local_qpn; + cache_owned_din = 'd0; + end + else if(!NextUnit_next_wqe_valid) begin //No valid WQE in current DB ringing, clear cache cell state + cache_owned_wen = 'd1; + cache_owned_addr = meta_local_qpn; + cache_owned_din = 'd0; + end + else if(NextUnit_next_wqe_valid && NextUnit_next_wqe_addr == 0) begin //Wrap back to SQ head, clear cache cell state + cache_owned_wen = 'd1; + cache_owned_addr = meta_local_qpn; + cache_owned_din = 'd0; + end + else if(NextUnit_next_wqe_valid && (cache_offset_dout + NextUnit_cur_wqe_size_aligned + NextUnit_next_wqe_size_aligned > CACHE_SLOT_NUM)) begin //Cross Cache cell boundary + cache_owned_wen = 'd1; + cache_owned_addr = meta_local_qpn; + cache_owned_din = 'd0; + end + else begin + cache_owned_wen = 'd0; + cache_owned_addr = meta_local_qpn; + cache_owned_din = 'd0; + end + end + else begin + cache_owned_wen = 'd0; + cache_owned_addr = meta_local_qpn; + cache_owned_din = 'd0; + end +end + +//-- parsed_msg_length -- +always @(posedge clk or posedge rst) begin + if(rst) begin + parsed_msg_length <= 'd0; + end + else if(cur_state == IDLE_s) begin + parsed_msg_length <= 'd0; + end + else if(cur_state == DATA_UNIT_s && wqe_valid) begin + if(parsed_msg_length + DataUnit_byte_cnt <= msg_offset_doutb) begin + parsed_msg_length <= parsed_msg_length + DataUnit_byte_cnt; + end + else if(parsed_msg_length + DataUnit_byte_cnt > msg_offset_doutb) begin + if(parsed_msg_length + DataUnit_byte_cnt - msg_offset_doutb >= meta_pmtu) begin + parsed_msg_length <= parsed_msg_length + meta_pmtu; + end + else begin + parsed_msg_length <= parsed_msg_length + DataUnit_byte_cnt - msg_offset_doutb; + end + end + else begin + parsed_msg_length <= parsed_msg_length; + end + end + else begin + parsed_msg_length <= parsed_msg_length; + end +end + +//-- insert_count -- +always @(posedge clk or posedge rst) begin + if (rst) begin + insert_count <= 'd0; + end + else if (cur_state == INLINE_UNIT_s && wqe_valid) begin + insert_count <= 'd1; + end + else if(cur_state == INLINE_DATA_s && wqe_valid && insert_req_ready) begin + insert_count <= insert_count + 'd1; + end + else begin + insert_count <= insert_count; + end +end + +//-- insert_total -- +always @(posedge clk or posedge rst) begin + if (rst) begin + insert_total <= 'd0; + end + else if(cur_state == IDLE_s) begin + insert_total <= 'd0; + end + else if (cur_state == INLINE_UNIT_s && wqe_valid) begin + insert_total <= SubWQE_msg_length[3:0] ? (SubWQE_msg_length >> 4) + 1 : SubWQE_msg_length >> 4; + end + else begin + insert_total <= insert_total; + end +end + +//-- insert_req_valid -- +//-- insert_req_start -- +//-- insert_req_last -- +//-- insert_req_head -- +//-- insert_req_data -- +assign insert_req_valid = (cur_state == INLINE_DATA_s && wqe_valid) ? 'd1 : 'd0; +assign insert_req_start = (cur_state == INLINE_DATA_s && wqe_valid) ? (insert_count == 'd1) : 'd0; +assign insert_req_last = (cur_state == INLINE_DATA_s && wqe_valid) ? (insert_count == insert_total) : 'd0; +assign insert_req_head = (cur_state == INLINE_DATA_s && wqe_valid) ? {SubWQE_msg_length[3:0] ? (SubWQE_msg_length >> 4) + 1 : SubWQE_msg_length >> 4, meta_local_qpn} : 'd0; +assign insert_req_data = (cur_state == INLINE_DATA_s && wqe_valid) ? wqe_data : 'd0; + +assign wqe_ready = (cur_state == NEXT_UNIT_s) ? 'd1 : + (cur_state == INLINE_UNIT_s) ? 'd1 : + (cur_state == INLINE_DATA_s) ? insert_req_ready : + (cur_state == UD_UNIT_1_s) ? 'd1 : + (cur_state == UD_UNIT_2_s) ? 'd1 : + (cur_state == UD_UNIT_3_s) ? 'd1 : + (cur_state == RADDR_UNIT_s) ? 'd1 : + (cur_state == DATA_UNIT_s) ? 'd1 : 'd0; + +/*********************************************************** Sub-WQE Field Decode : Begin**********************************************************/ +//-- SubWQE_local_qpn -- +always @(posedge clk or posedge rst) begin + if(rst) begin + SubWQE_local_qpn <= 'd0; + end + else if(cur_state == NEXT_UNIT_s && wqe_valid) begin + SubWQE_local_qpn <= meta_local_qpn; + end + else begin + SubWQE_local_qpn <= SubWQE_local_qpn; + end +end + +//-- SubWQE_remote_qpn -- +always @(posedge clk or posedge rst) begin + if(rst) begin + SubWQE_remote_qpn <= 'd0; + end + else if(cur_state == NEXT_UNIT_s && wqe_valid) begin + SubWQE_remote_qpn <= meta_remote_qpn; + end + else if(cur_state == UD_UNIT_1_s) begin + SubWQE_remote_qpn <= UDUnit_dqpn; + end + else begin + SubWQE_remote_qpn <= SubWQE_remote_qpn; + end +end + +//-- SubWQE_verbs_opcode -- +always @(posedge clk or posedge rst) begin + if (rst) begin + SubWQE_verbs_opcode <= 'd0; + end + else if (cur_state == NEXT_UNIT_s && wqe_valid) begin + SubWQE_verbs_opcode <= wqe_data[`NEXT_UNIT_CUR_WQE_OPCODE_OFFSET];; + end + else begin + SubWQE_verbs_opcode <= SubWQE_verbs_opcode; + end +end + +//-- SubWQE_net_opcode -- +always @(posedge clk or posedge rst) begin + if(rst) begin + SubWQE_net_opcode <= 'd0; + end + else if(cur_state == IDLE_s) begin + SubWQE_net_opcode <= `NONE_OPCODE; + end + else if(cur_state == INLINE_UNIT_s) begin //Inline data length is less than PMTU + if(NextUnit_cur_wqe_opcode == `VERBS_SEND) begin + SubWQE_net_opcode <= `SEND_ONLY; + end + else if(NextUnit_cur_wqe_opcode == `VERBS_SEND_WITH_IMM) begin + SubWQE_net_opcode <= `SEND_ONLY_WITH_IMM; + end + else if(NextUnit_cur_wqe_opcode == `RDMA_WRITE_ONLY) begin + SubWQE_net_opcode <= `RDMA_WRITE_ONLY; + end + else if(NextUnit_cur_wqe_opcode == `RDMA_WRITE_ONLY_WITH_IMM) begin + SubWQE_net_opcode <= `RDMA_WRITE_ONLY_WITH_IMM; + end + else begin + SubWQE_net_opcode <= `NONE_OPCODE; + end + end + else if(cur_state == DATA_UNIT_s && !data_unit_parse_finish) begin + if(msg_offset_doutb == 'd0) begin //First packet, need to decide whether it is last packet + if(wqe_last && (parsed_msg_length + DataUnit_byte_cnt <= meta_pmtu)) begin //XXX-Only + if(NextUnit_cur_wqe_opcode == `VERBS_SEND) begin + SubWQE_net_opcode <= `SEND_ONLY; + end + else if(NextUnit_cur_wqe_opcode == `VERBS_SEND_WITH_IMM) begin + SubWQE_net_opcode <= `SEND_ONLY_WITH_IMM; + end + else if(NextUnit_cur_wqe_opcode == `VERBS_RDMA_WRITE) begin + SubWQE_net_opcode <= `RDMA_WRITE_ONLY; + end + else if(NextUnit_cur_wqe_opcode == `VERBS_RDMA_WRITE_WITH_IMM) begin + SubWQE_net_opcode <= `RDMA_WRITE_ONLY_WITH_IMM; + end + else if(NextUnit_cur_wqe_opcode == `VERBS_RDMA_READ) begin + SubWQE_net_opcode <= `RDMA_READ_REQUEST_ONLY; + end + else begin + SubWQE_net_opcode <= `NONE_OPCODE; + end + end + else begin + if(NextUnit_cur_wqe_opcode == `VERBS_SEND) begin + SubWQE_net_opcode <= `SEND_FIRST; + end + else if(NextUnit_cur_wqe_opcode == `VERBS_SEND_WITH_IMM) begin + SubWQE_net_opcode <= `SEND_FIRST; + end + else if(NextUnit_cur_wqe_opcode == `VERBS_RDMA_WRITE) begin + SubWQE_net_opcode <= `RDMA_WRITE_FIRST; + end + else if(NextUnit_cur_wqe_opcode == `VERBS_RDMA_WRITE_WITH_IMM) begin + SubWQE_net_opcode <= `RDMA_WRITE_FIRST; + end + else if(NextUnit_cur_wqe_opcode == `VERBS_RDMA_READ) begin + SubWQE_net_opcode <= `RDMA_READ_REQUEST_FIRST; + end + else begin + SubWQE_net_opcode <= `NONE_OPCODE; + end + end + end + else begin + if(wqe_last && (parsed_msg_length + DataUnit_byte_cnt - msg_offset_doutb <= meta_pmtu)) begin + if(NextUnit_cur_wqe_opcode == `VERBS_SEND) begin + SubWQE_net_opcode <= `SEND_LAST; + end + else if(NextUnit_cur_wqe_opcode == `VERBS_SEND_WITH_IMM) begin + SubWQE_net_opcode <= `SEND_LAST_WITH_IMM; + end + else if(NextUnit_cur_wqe_opcode == `VERBS_RDMA_WRITE) begin + SubWQE_net_opcode <= `RDMA_WRITE_LAST; + end + else if(NextUnit_cur_wqe_opcode == `VERBS_RDMA_WRITE_WITH_IMM) begin + SubWQE_net_opcode <= `RDMA_WRITE_LAST_WITH_IMM; + end + else if(NextUnit_cur_wqe_opcode == `VERBS_RDMA_READ) begin + SubWQE_net_opcode <= `RDMA_READ_REQUEST_LAST; + end + else begin + SubWQE_net_opcode <= `NONE_OPCODE; + end + end + else begin + if(NextUnit_cur_wqe_opcode == `VERBS_SEND) begin + SubWQE_net_opcode <= `SEND_MIDDLE; + end + else if(NextUnit_cur_wqe_opcode == `VERBS_SEND_WITH_IMM) begin + SubWQE_net_opcode <= `SEND_MIDDLE; + end + else if(NextUnit_cur_wqe_opcode == `VERBS_RDMA_WRITE) begin + SubWQE_net_opcode <= `RDMA_WRITE_MIDDLE; + end + else if(NextUnit_cur_wqe_opcode == `VERBS_RDMA_WRITE_WITH_IMM) begin + SubWQE_net_opcode <= `RDMA_WRITE_MIDDLE; + end + else if(NextUnit_cur_wqe_opcode == `VERBS_RDMA_READ) begin + SubWQE_net_opcode <= `RDMA_READ_REQUEST_MIDDLE; + end + else begin + SubWQE_net_opcode <= `NONE_OPCODE; + end + end + end + end + else begin + SubWQE_net_opcode <= SubWQE_net_opcode; + end +end + +//-- SubWQE_service_type -- +always @(posedge clk or posedge rst) begin + if(rst) begin + SubWQE_service_type <= 'd0; + end + else if(cur_state == NEXT_UNIT_s && wqe_valid) begin + SubWQE_service_type <= meta_service_type; + end + else begin + SubWQE_service_type <= SubWQE_service_type; + end +end + +//-- SubWQE_wqe_head -- +always @(posedge clk or posedge rst) begin + if (rst) begin + SubWQE_wqe_head <= 'd0; + end + else if (cur_state == IDLE_s) begin + SubWQE_wqe_head <= 'd0; + end + else if (cur_state == UD_UNIT_1_s || cur_state == INLINE_UNIT_s) begin + SubWQE_wqe_head <= 'd1; + end + else if (cur_state == DATA_UNIT_s && wqe_valid && msg_offset_doutb == 'd0) begin + SubWQE_wqe_head <= 'd1; + end + else begin + SubWQE_wqe_head <= SubWQE_wqe_head; + end +end + +//-- SubWQE_wqe_tail -- +always @(posedge clk or posedge rst) begin + if (rst) begin + SubWQE_wqe_tail <= 'd0; + end + else if (cur_state == IDLE_s) begin + SubWQE_wqe_tail <= 'd0; + end + else if (cur_state == UD_UNIT_1_s || cur_state == INLINE_UNIT_s) begin + SubWQE_wqe_tail <= 'd1; + end + else if (cur_state == DATA_UNIT_s && wqe_valid && !data_unit_parse_finish) begin + if(wqe_last && (parsed_msg_length + DataUnit_byte_cnt > msg_offset_doutb)) begin + if(parsed_msg_length + DataUnit_byte_cnt - msg_offset_doutb <= meta_pmtu) begin + SubWQE_wqe_tail <= 'd1; + end + else begin + SubWQE_wqe_tail <= 'd0; + end + end + else begin + SubWQE_wqe_tail <= SubWQE_wqe_tail; + end + end + else begin + SubWQE_wqe_tail <= SubWQE_wqe_tail; + end +end + +//-- SubWQE_inline -- +always @(posedge clk or posedge rst) begin + if (rst) begin + SubWQE_inline <= 'd0; + end + else if (cur_state == IDLE_s) begin + SubWQE_inline <= 'd0; + end + else if(cur_state == INLINE_UNIT_s && wqe_valid) begin + SubWQE_inline <= 'd1; + end + else begin + SubWQE_inline <= SubWQE_inline; + end +end + +//-- SubWQE_ori_wqe_offset -- +always @(posedge clk or posedge rst) begin + if(rst) begin + SubWQE_ori_wqe_offset <= 'd0; + end + else if(cur_state == IDLE_s) begin + SubWQE_ori_wqe_offset <= 'd0; + end + else if(cur_state == NEXT_UNIT_s && wqe_valid) begin + SubWQE_ori_wqe_offset <= sq_offset_dout; + end + else begin + SubWQE_ori_wqe_offset <= SubWQE_ori_wqe_offset; + end +end + +//-- SubWQE_dmac -- +//-- SubWQE_smac -- +always @(posedge clk or posedge rst) begin + if (rst) begin + SubWQE_dmac <= 'd0; + SubWQE_smac <= 'd0; + end + else if (cur_state == IDLE_s) begin + SubWQE_dmac <= 'd0; + SubWQE_smac <= 'd0; + end + else if(cur_state == NEXT_UNIT_s && wqe_valid) begin + SubWQE_dmac <= meta_dmac; + SubWQE_smac <= meta_smac; + end + else if(cur_state == UD_UNIT_1_s && wqe_valid) begin + SubWQE_dmac <= {UDUnit_dmac_high, UDUnit_dmac_low}; + SubWQE_smac <= {UDUnit_smac_high, UDUnit_smac_low}; + end + else begin + SubWQE_dmac <= SubWQE_dmac; + SubWQE_smac <= SubWQE_smac; + end +end + +//-- SubWQE_dip -- +//-- SubWQE_sip -- +always @(posedge clk or posedge rst) begin + if (rst) begin + SubWQE_dip <= 'd0; + SubWQE_sip <= 'd0; + end + else if (cur_state == IDLE_s) begin + SubWQE_dip <= 'd0; + SubWQE_sip <= 'd0; + end + else if(cur_state == NEXT_UNIT_s && wqe_valid) begin + SubWQE_dip <= meta_dip; + SubWQE_sip <= meta_sip; + end + else if(cur_state == UD_UNIT_2_s && wqe_valid) begin + SubWQE_dip <= UDUnit_dip; + SubWQE_sip <= UDUnit_sip; + end + else begin + SubWQE_dip <= SubWQE_dip; + SubWQE_sip <= SubWQE_sip; + end +end + +//-- SubWQE_immediate -- +always @(posedge clk or posedge rst) begin + if(rst) begin + SubWQE_immediate <= 'd0; + end + else if(cur_state == IDLE_s) begin + SubWQE_immediate <= 'd0; + end + else if(cur_state == NEXT_UNIT_s && wqe_valid) begin + SubWQE_immediate <= NextUnit_cur_wqe_imm; + end + else begin + SubWQE_immediate <= SubWQE_immediate; + end +end + +//-- SubWQE_lkey -- +//-- SubWQE_laddr -- +always @(posedge clk or posedge rst) begin + if(rst) begin + SubWQE_lkey <= 'd0; + SubWQE_laddr <= 'd0; + end + else if(cur_state == IDLE_s) begin + SubWQE_lkey <= 'd0; + SubWQE_laddr <= 'd0; + end + else if(cur_state == DATA_UNIT_s && wqe_valid && !data_unit_parse_finish) begin + if(parsed_msg_length + DataUnit_byte_cnt <= msg_offset_doutb) begin + SubWQE_lkey <= 'd0; + SubWQE_laddr <= 'd0; + end + else if(parsed_msg_length + DataUnit_byte_cnt > msg_offset_doutb) begin + SubWQE_lkey <= DataUnit_lkey; + SubWQE_laddr <= DataUnit_laddr + (msg_offset_doutb - parsed_msg_length); + end + else begin + SubWQE_lkey <= 'd0; + SubWQE_laddr <= 'd0; + end + end + else begin + SubWQE_lkey <= SubWQE_lkey; + SubWQE_laddr <= SubWQE_laddr; + end +end + +//-- SubWQE_rkey -- +//-- SubWQE_raddr -- +always @(posedge clk or posedge rst) begin + if(rst) begin + SubWQE_rkey <= 'd0; + SubWQE_raddr <= 'd0; + end + else if(cur_state == IDLE_s) begin + SubWQE_rkey <= 'd0; + SubWQE_raddr <= 'd0; + end + else if(cur_state == RADDR_UNIT_s && wqe_valid) begin + SubWQE_rkey <= RaddrUnit_rkey; + SubWQE_raddr <= RaddrUnit_raddr; + end + else if(cur_state == DATA_UNIT_s && wqe_valid && !data_unit_parse_finish) begin + if(parsed_msg_length + DataUnit_byte_cnt <= msg_offset_doutb) begin + SubWQE_rkey <= SubWQE_rkey; + SubWQE_raddr <= SubWQE_raddr; + end + else if(parsed_msg_length + DataUnit_byte_cnt > msg_offset_doutb) begin + SubWQE_rkey <= SubWQE_rkey; + SubWQE_raddr <= SubWQE_raddr + msg_offset_doutb; + end + else begin + SubWQE_rkey <= 'd0; + SubWQE_raddr <= 'd0; + end + end + else begin + SubWQE_rkey <= SubWQE_rkey; + SubWQE_raddr <= SubWQE_raddr; + end +end + +//-- SubWQE_fence -- +//-- SubWQE_solicited_event -- +always @(posedge clk or posedge rst) begin + if (rst) begin + SubWQE_fence <= 'd0; + SubWQE_solicited_event <= 'd0; + end + else begin + SubWQE_fence <= 'd0; + SubWQE_solicited_event <= 'd0; + end +end + +//-- SubWQE_msg_length -- +always @(posedge clk or posedge rst) begin + if (rst) begin + SubWQE_msg_length <= 'd0; + end + else if (cur_state == IDLE_s) begin + SubWQE_msg_length <= 'd0; + end + else if(cur_state == DATA_UNIT_s && wqe_valid) begin + SubWQE_msg_length <= SubWQE_msg_length + DataUnit_byte_cnt; + end + else if(cur_state == INLINE_UNIT_s && wqe_valid) begin + SubWQE_msg_length <= InlineUnit_length; + end + else begin + SubWQE_msg_length <= SubWQE_msg_length; + end +end + +//-- SubWQE_packet_length -- +always @(posedge clk or posedge rst) begin + if (rst) begin + SubWQE_packet_length <= 'd0; + end + else if (cur_state == IDLE_s) begin + SubWQE_packet_length <= 'd0; + end + else if(cur_state == DATA_UNIT_s && wqe_valid && !data_unit_parse_finish) begin + if(parsed_msg_length + DataUnit_byte_cnt <= msg_offset_doutb) begin + SubWQE_packet_length <= 'd0; + end + else if(parsed_msg_length + DataUnit_byte_cnt > msg_offset_doutb) begin + if(parsed_msg_length + DataUnit_byte_cnt - msg_offset_doutb >= meta_pmtu) begin + SubWQE_packet_length <= meta_pmtu; + end + else begin + SubWQE_packet_length <= parsed_msg_length + DataUnit_byte_cnt - msg_offset_doutb; + end + end + else begin + SubWQE_packet_length <= SubWQE_packet_length; + end + end + else begin + SubWQE_packet_length <= SubWQE_packet_length; + end +end + +//-- data_unit_parse_finish -- +always @(posedge clk or posedge rst) begin + if(rst) begin + data_unit_parse_finish <= 'd0; + end + else if(cur_state == IDLE_s) begin + data_unit_parse_finish <= 'd0; + end + else if(cur_state == DATA_UNIT_s && wqe_valid && (parsed_msg_length + DataUnit_byte_cnt > msg_offset_doutb)) begin + data_unit_parse_finish <= 'd1; + end + else begin + data_unit_parse_finish <= data_unit_parse_finish; + end +end + +//-- sub_wqe_valid -- +//-- sub_wqe_meta -- +assign sub_wqe_valid = (cur_state == INJECT_s) ? 'd1 : 'd0; +assign sub_wqe_meta = (cur_state == INJECT_s) ? {inline_payload_start_addr, 16'd0, SubWQE_packet_length, SubWQE_msg_length, + SubWQE_raddr, SubWQE_rkey, SubWQE_laddr, SubWQE_lkey, SubWQE_immediate, + SubWQE_sip, SubWQE_dip, SubWQE_smac, SubWQE_dmac, SubWQE_ori_wqe_offset, 3'd0, SubWQE_inline, + SubWQE_wqe_tail, SubWQE_wqe_head, 1'b0, SubWQE_fence, SubWQE_service_type, + SubWQE_net_opcode, SubWQE_remote_qpn, 3'd0, SubWQE_verbs_opcode, SubWQE_local_qpn} : 'd0; + +//-- qpn_fifo_valid -- +//-- qpn_fifo_data -- +assign qpn_fifo_valid = (cur_state == RESCHEDULE_s) ? 'd1 : 'd0; +assign qpn_fifo_data = (cur_state == RESCHEDULE_s) ? meta_local_qpn : 'd0; + +/*********************************************************** Sub-WQE Field Decode : End**********************************************************/ +/*------------------------------------------- Variables Decode : End ----------------------------------------------*/ + +/*------------------------------------------- Local Macros Undef : Begin --------------------------------------------*/ +`undef LOCAL_QPN_OFFSET +`undef REMOTE_QPN_OFFSET +`undef DMAC_OFFSET +`undef SMAC_OFFSET +`undef DIP_OFFSET +`undef SIP_OFFSET +`undef SQ_ENTRY_SZ_LOG_OFFSET +`undef SQ_LENGTH_OFFSET +/*------------------------------------------- Local Macros Undef : End ----------------------------------------------*/ + +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/README.md b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/README.md new file mode 100644 index 0000000000000000000000000000000000000000..ae4076554590d874ed8bab60de5f4d19e951d236 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/README.md @@ -0,0 +1 @@ +Subsystem RTL. diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/RPCSubsystem/RDMACore/RDMACore.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/RPCSubsystem/RDMACore/RDMACore.v new file mode 100644 index 0000000000000000000000000000000000000000..e8a6dde3db4eb79a96740485303ca4f63770d35c --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/RPCSubsystem/RDMACore/RDMACore.v @@ -0,0 +1,944 @@ +/*------------------------------------------- Module Description : Begin ---------------------------------------------- +Name: RequesterCore +Author: YangFan +Function: 1.Deal with RDMA Semantics. +--------------------------------------------- Module Decription : End -----------------------------------------------*/ + +/*------------------------------------------- Timescale Definition : Begin ------------------------------------------*/ +`timescale 1ns / 1ps +/*------------------------------------------- Timescale Definition : End --------------------------------------------*/ + +/*------------------------------------------- Included Files : Begin ------------------------------------------------*/ +`include "protocol_engine_def.vh" +/*------------------------------------------- Included Files : End --------------------------------------------------*/ + +/*------------------------------------------- Input/Output Definition : Begin ---------------------------------------*/ +module RDMACore +#( + parameter INGRESS_CXT_HEAD_WIDTH = 128, + parameter INGRESS_CXT_DATA_WIDTH = 256, + parameter EGRESS_CXT_HEAD_WIDTH = 128, + parameter EGRESS_CXT_DATA_WIDTH = 256, + + parameter INGRESS_MR_HEAD_WIDTH = 128, + parameter INGRESS_MR_DATA_WIDTH = 256, + parameter EGRESS_MR_HEAD_WIDTH = 128, + parameter EGRESS_MR_DATA_WIDTH = 256 +) +( + input wire clk, + input wire rst, + +/*************************** Interface with QueueSubsystem ****************************************/ +//TX : SQ Interface + input wire TX_REQ_sub_wqe_valid, + input wire [`WQE_META_WIDTH - 1 : 0] TX_REQ_sub_wqe_meta, + output wire TX_REQ_sub_wqe_ready, + +//TX : SCQ Interface + output wire TX_REQ_cq_req_valid, + output wire [`CQ_REQ_HEAD_WIDTH - 1 : 0] TX_REQ_cq_req_head, + input wire TX_REQ_cq_req_ready, + + input wire TX_REQ_cq_resp_valid, + input wire [`CQ_RESP_HEAD_WIDTH - 1 : 0] TX_REQ_cq_resp_head, + output wire TX_REQ_cq_resp_ready, + +//TX : EQ Interface + output wire TX_REQ_eq_req_valid, + output wire [`EQ_REQ_HEAD_WIDTH - 1 : 0] TX_REQ_eq_req_head, + input wire TX_REQ_eq_req_ready, + + input wire TX_REQ_eq_resp_valid, + input wire [`EQ_RESP_HEAD_WIDTH - 1 : 0] TX_REQ_eq_resp_head, + output wire TX_REQ_eq_resp_ready, + +//RX : RQ Interface + output wire RQ_wqe_req_valid, + output wire [`WQE_META_WIDTH - 1 : 0] RQ_wqe_req_head, + output wire RQ_wqe_req_start, + output wire RQ_wqe_req_last, + input wire RQ_wqe_req_ready, + + input wire RQ_wqe_resp_valid, + input wire [`WQE_META_WIDTH - 1 : 0] RQ_wqe_resp_head, + input wire [`WQE_SEG_WIDTH - 1 : 0] RQ_wqe_resp_data, + input wire RQ_wqe_resp_start, + input wire RQ_wqe_resp_last, + output wire RQ_wqe_resp_ready, + + output wire RQ_cache_offset_wen, + output wire [`QP_NUM_LOG - 1 : 0] RQ_cache_offset_addr, + output wire [`RQ_CACHE_SLOT_NUM_LOG - 1:0] RQ_cache_offset_din, + input wire [`RQ_CACHE_SLOT_NUM_LOG - 1:0] RQ_cache_offset_dout, + + output wire RQ_offset_wen, + output wire [`QP_NUM_LOG - 1 : 0] RQ_offset_addr, + output wire [23:0] RQ_offset_din, + input wire [23:0] RQ_offset_dout, + + output wire RQ_cache_owned_wen, + output wire [`RQ_CACHE_CELL_NUM_LOG - 1 : 0] RQ_cache_owned_addr, + output wire [`QP_NUM_LOG - 1 : 0] RQ_cache_owned_din, + input wire [`QP_NUM_LOG - 1 : 0] RQ_cache_owned_dout, + +//RX : RCQ Interface + output wire RX_REQ_cq_req_valid, + output wire [`CQ_REQ_HEAD_WIDTH - 1 : 0] RX_REQ_cq_req_head, + input wire RX_REQ_cq_req_ready, + + input wire RX_REQ_cq_resp_valid, + input wire [`CQ_RESP_HEAD_WIDTH - 1 : 0] RX_REQ_cq_resp_head, + output wire RX_REQ_cq_resp_ready, + +//RX : EQ Interface + output wire RX_REQ_eq_req_valid, + output wire [`EQ_REQ_HEAD_WIDTH - 1 : 0] RX_REQ_eq_req_head, + input wire RX_REQ_eq_req_ready, + + input wire RX_REQ_eq_resp_valid, + input wire [`EQ_RESP_HEAD_WIDTH - 1 : 0] RX_REQ_eq_resp_head, + output wire RX_REQ_eq_resp_ready, + +//RX : SCQ Interface + output wire RX_RESP_cq_req_valid, + output wire [`CQ_REQ_HEAD_WIDTH - 1 : 0] RX_RESP_cq_req_head, + input wire RX_RESP_cq_req_ready, + + input wire RX_RESP_cq_resp_valid, + input wire [`CQ_RESP_HEAD_WIDTH - 1 : 0] RX_RESP_cq_resp_head, + output wire RX_RESP_cq_resp_ready, + +//RX : EQ Interface + output wire RX_RESP_eq_req_valid, + output wire [`EQ_REQ_HEAD_WIDTH - 1 : 0] RX_RESP_eq_req_head, + input wire RX_RESP_eq_req_ready, + + input wire RX_RESP_eq_resp_valid, + input wire [`EQ_RESP_HEAD_WIDTH - 1 : 0] RX_RESP_eq_resp_head, + output wire RX_RESP_eq_resp_ready, + +/*************************** Interface with ICMMgt(CxtMgt) ****************************************/ +//TX : Cxt for transmit REQ + output wire TX_REQ_fetch_cxt_ingress_valid, + output wire [`TX_REQ_OOO_CXT_INGRESS_HEAD_WIDTH - 1 : 0] TX_REQ_fetch_cxt_ingress_head, + output wire [`TX_REQ_OOO_CXT_INGRESS_DATA_WIDTH - 1 : 0] TX_REQ_fetch_cxt_ingress_data, + output wire TX_REQ_fetch_cxt_ingress_start, + output wire TX_REQ_fetch_cxt_ingress_last, + input wire TX_REQ_fetch_cxt_ingress_ready, + + input wire TX_REQ_fetch_cxt_egress_valid, + input wire [`TX_REQ_OOO_CXT_EGRESS_HEAD_WIDTH - 1 : 0] TX_REQ_fetch_cxt_egress_head, + input wire [`TX_REQ_OOO_CXT_EGRESS_DATA_WIDTH - 1 : 0] TX_REQ_fetch_cxt_egress_data, + input wire TX_REQ_fetch_cxt_egress_start, + input wire TX_REQ_fetch_cxt_egress_last, + output wire TX_REQ_fetch_cxt_egress_ready, + +//RX : Cxt for receive REQ + output wire RX_REQ_fetch_cxt_ingress_valid, + output wire [`RX_REQ_OOO_CXT_INGRESS_HEAD_WIDTH - 1 : 0] RX_REQ_fetch_cxt_ingress_head, + output wire [`RX_REQ_OOO_CXT_INGRESS_DATA_WIDTH - 1 : 0] RX_REQ_fetch_cxt_ingress_data, + output wire RX_REQ_fetch_cxt_ingress_start, + output wire RX_REQ_fetch_cxt_ingress_last, + input wire RX_REQ_fetch_cxt_ingress_ready, + + input wire RX_REQ_fetch_cxt_egress_valid, + input wire [`RX_REQ_OOO_CXT_EGRESS_HEAD_WIDTH - 1 : 0] RX_REQ_fetch_cxt_egress_head, + input wire [`RX_REQ_OOO_CXT_EGRESS_DATA_WIDTH - 1 : 0] RX_REQ_fetch_cxt_egress_data, + input wire RX_REQ_fetch_cxt_egress_start, + input wire RX_REQ_fetch_cxt_egress_last, + output wire RX_REQ_fetch_cxt_egress_ready, + +//RX : Cxt for receive RESP + output wire RX_RESP_fetch_cxt_ingress_valid, + output wire [`RX_RESP_OOO_CXT_INGRESS_HEAD_WIDTH - 1 : 0] RX_RESP_fetch_cxt_ingress_head, + output wire [`RX_RESP_OOO_CXT_INGRESS_DATA_WIDTH - 1 : 0] RX_RESP_fetch_cxt_ingress_data, + output wire RX_RESP_fetch_cxt_ingress_start, + output wire RX_RESP_fetch_cxt_ingress_last, + input wire RX_RESP_fetch_cxt_ingress_ready, + + input wire RX_RESP_fetch_cxt_egress_valid, + input wire [`RX_RESP_OOO_CXT_EGRESS_HEAD_WIDTH - 1 : 0] RX_RESP_fetch_cxt_egress_head, + input wire [`RX_RESP_OOO_CXT_EGRESS_DATA_WIDTH - 1 : 0] RX_RESP_fetch_cxt_egress_data, + input wire RX_RESP_fetch_cxt_egress_start, + input wire RX_RESP_fetch_cxt_egress_last, + output wire RX_RESP_fetch_cxt_egress_ready, + +/*************************** Interface with ICMMgt(MRMgt) ****************************************/ +//TX : Cxt for transmit REQ + output wire TX_REQ_fetch_mr_ingress_valid, + output wire [`TX_REQ_OOO_MR_INGRESS_HEAD_WIDTH - 1 : 0] TX_REQ_fetch_mr_ingress_head, + output wire [`TX_REQ_OOO_MR_INGRESS_DATA_WIDTH - 1 : 0] TX_REQ_fetch_mr_ingress_data, + output wire TX_REQ_fetch_mr_ingress_start, + output wire TX_REQ_fetch_mr_ingress_last, + input wire TX_REQ_fetch_mr_ingress_ready, + + input wire TX_REQ_fetch_mr_egress_valid, + input wire [`TX_REQ_OOO_MR_EGRESS_HEAD_WIDTH - 1 : 0] TX_REQ_fetch_mr_egress_head, + input wire [`TX_REQ_OOO_MR_EGRESS_DATA_WIDTH - 1 : 0] TX_REQ_fetch_mr_egress_data, + input wire TX_REQ_fetch_mr_egress_start, + input wire TX_REQ_fetch_mr_egress_last, + output wire TX_REQ_fetch_mr_egress_ready, + +//RX : Cxt for receive REQ + output wire RX_RESP_fetch_mr_ingress_valid, + output wire [`RX_RESP_OOO_MR_INGRESS_HEAD_WIDTH - 1 : 0] RX_RESP_fetch_mr_ingress_head, + output wire [`RX_RESP_OOO_MR_INGRESS_DATA_WIDTH - 1 : 0] RX_RESP_fetch_mr_ingress_data, + output wire RX_RESP_fetch_mr_ingress_start, + output wire RX_RESP_fetch_mr_ingress_last, + input wire RX_RESP_fetch_mr_ingress_ready, + + input wire RX_RESP_fetch_mr_egress_valid, + input wire [`RX_RESP_OOO_MR_EGRESS_HEAD_WIDTH - 1 : 0] RX_RESP_fetch_mr_egress_head, + input wire [`RX_RESP_OOO_MR_EGRESS_DATA_WIDTH - 1 : 0] RX_RESP_fetch_mr_egress_data, + input wire RX_RESP_fetch_mr_egress_start, + input wire RX_RESP_fetch_mr_egress_last, + output wire RX_RESP_fetch_mr_egress_ready, + +//RX : Cxt for receive RESP + output wire RX_REQ_fetch_mr_ingress_valid, + output wire [`RX_REQ_OOO_MR_INGRESS_HEAD_WIDTH - 1 : 0] RX_REQ_fetch_mr_ingress_head, + output wire [`RX_REQ_OOO_MR_INGRESS_DATA_WIDTH - 1 : 0] RX_REQ_fetch_mr_ingress_data, + output wire RX_REQ_fetch_mr_ingress_start, + output wire RX_REQ_fetch_mr_ingress_last, + input wire RX_REQ_fetch_mr_ingress_ready, + + input wire RX_REQ_fetch_mr_egress_valid, + input wire [`RX_REQ_OOO_MR_EGRESS_HEAD_WIDTH - 1 : 0] RX_REQ_fetch_mr_egress_head, + input wire [`RX_REQ_OOO_MR_EGRESS_DATA_WIDTH - 1 : 0] RX_REQ_fetch_mr_egress_data, + input wire RX_REQ_fetch_mr_egress_start, + input wire RX_REQ_fetch_mr_egress_last, + output wire RX_REQ_fetch_mr_egress_ready, + +/*************************** Interface with DMASubsystem **********************************************/ + output wire TX_REQ_dma_wr_req_valid, + output wire TX_REQ_dma_wr_req_last, + output wire [`DMA_HEAD_WIDTH - 1 : 0] TX_REQ_dma_wr_req_head, + output wire [`DMA_DATA_WIDTH - 1 : 0] TX_REQ_dma_wr_req_data, + input wire TX_REQ_dma_wr_req_ready, + + output wire RX_REQ_dma_wr_req_valid, + output wire RX_REQ_dma_wr_req_last, + output wire [`DMA_HEAD_WIDTH - 1 : 0] RX_REQ_dma_wr_req_head, + output wire [`DMA_DATA_WIDTH - 1 : 0] RX_REQ_dma_wr_req_data, + input wire RX_REQ_dma_wr_req_ready, + + output wire RX_RESP_dma_wr_req_valid, + output wire RX_RESP_dma_wr_req_last, + output wire [`DMA_HEAD_WIDTH - 1 : 0] RX_RESP_dma_wr_req_head, + output wire [`DMA_DATA_WIDTH - 1 : 0] RX_RESP_dma_wr_req_data, + input wire RX_RESP_dma_wr_req_ready, + + output wire TX_REQ_dma_rd_req_valid, + output wire [`DMA_HEAD_WIDTH - 1 : 0] TX_REQ_dma_rd_req_head, + output wire [`DMA_DATA_WIDTH - 1 : 0] TX_REQ_dma_rd_req_data, + output wire TX_REQ_dma_rd_req_last, + input wire TX_REQ_dma_rd_req_ready, + + input wire TX_REQ_dma_rd_rsp_valid, + input wire [`DMA_HEAD_WIDTH - 1 : 0] TX_REQ_dma_rd_rsp_head, + input wire [`DMA_DATA_WIDTH - 1 : 0] TX_REQ_dma_rd_rsp_data, + input wire TX_REQ_dma_rd_rsp_last, + output wire TX_REQ_dma_rd_rsp_ready, + + output wire TX_RESP_dma_rd_req_valid, + output wire [`DMA_HEAD_WIDTH - 1 : 0] TX_RESP_dma_rd_req_head, + output wire [`DMA_DATA_WIDTH - 1 : 0] TX_RESP_dma_rd_req_data, + output wire TX_RESP_dma_rd_req_last, + input wire TX_RESP_dma_rd_req_ready, + + input wire TX_RESP_dma_rd_rsp_valid, + input wire [`DMA_HEAD_WIDTH - 1 : 0] TX_RESP_dma_rd_rsp_head, + input wire [`DMA_DATA_WIDTH - 1 : 0] TX_RESP_dma_rd_rsp_data, + input wire TX_RESP_dma_rd_rsp_last, + output wire TX_RESP_dma_rd_rsp_ready, +/*************************** Interface with TransportSubsystem ****************************************/ +//TX : Inject pkt header + output wire TX_egress_pkt_valid, + output wire [`PKT_META_BUS_WIDTH - 1 : 0] TX_egress_pkt_head, + input wire TX_egress_pkt_ready, + +//TX : Insert REQ payload + output wire TX_insert_req_valid, + output wire TX_insert_req_start, + output wire TX_insert_req_last, + output wire [`MAX_DB_SLOT_NUM_LOG - 1 : 0] TX_insert_req_head, + output wire [`PACKET_BUFFER_SLOT_WIDTH - 1 : 0] TX_insert_req_data, + input wire TX_insert_req_ready, + + input wire TX_insert_resp_valid, + input wire [`MAX_DB_SLOT_NUM_LOG - 1 : 0] TX_insert_resp_data, + +//RX Interfaces + input wire RX_ingress_pkt_valid, + input wire [`PKT_META_BUS_WIDTH - 1 : 0] RX_ingress_pkt_head, + output wire RX_ingress_pkt_ready, + +//RX : Delete REQ payload + output wire RX_delete_req_valid, + output wire [`MAX_DB_SLOT_NUM_LOG * 2 - 1 : 0] RX_delete_req_head, + input wire RX_delete_req_ready, + + input wire RX_delete_resp_valid, + input wire RX_delete_resp_start, + input wire RX_delete_resp_last, + input wire [`PACKET_BUFFER_SLOT_WIDTH - 1 : 0] RX_delete_resp_data, + output wire RX_delete_resp_ready + +); + +/*------------------------------------------- Input/Output Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Macros Definition : Begin ---------------------------------------*/ +/*------------------------------------------- Local Macros Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Variables Definition : Begin ------------------------------------*/ +wire TX_REQ_gather_req_wr_en; +wire [`DMA_LENGTH_WIDTH * 2 + `DMA_ADDR_WIDTH - 1 : 0] TX_REQ_gather_req_din; +wire TX_REQ_gather_req_prog_full; + +wire TX_REQ_net_data_rd_en; +wire [`DMA_DATA_WIDTH - 1 : 0] TX_REQ_net_data_dout; +wire TX_REQ_net_data_empty; + +wire TX_RESP_gather_req_wr_en; +wire [`DMA_LENGTH_WIDTH * 2 + `DMA_ADDR_WIDTH - 1 : 0] TX_RESP_gather_req_din; +wire TX_RESP_gather_req_prog_full; + +wire TX_RESP_payload_empty; +wire [511:0] TX_RESP_payload_dout; +wire TX_RESP_payload_rd_en; + +wire TX_REQ_scatter_req_wr_en; +wire [`DMA_LENGTH_WIDTH * 2 + `DMA_ADDR_WIDTH - 1 : 0] TX_REQ_scatter_req_din; +wire TX_REQ_scatter_req_prog_full; + +wire TX_REQ_scatter_data_wr_en; +wire [`DMA_DATA_WIDTH - 1 : 0] TX_REQ_scatter_data_din; +wire TX_REQ_scatter_data_prog_full; + +wire RX_REQ_scatter_req_wr_en; +wire [`DMA_LENGTH_WIDTH * 2 + `DMA_ADDR_WIDTH - 1 : 0] RX_REQ_scatter_req_din; +wire RX_REQ_scatter_req_prog_full; + +wire RX_REQ_scatter_data_wr_en; +wire [`DMA_DATA_WIDTH - 1: 0] RX_REQ_scatter_data_din; +wire RX_REQ_scatter_data_prog_full; + +wire RX_RESP_scatter_req_wr_en; +wire [`DMA_LENGTH_WIDTH * 2 + `DMA_ADDR_WIDTH - 1 : 0] RX_RESP_scatter_req_din; +wire RX_RESP_scatter_req_prog_full; + +wire RX_RESP_scatter_data_wr_en; +wire [`DMA_DATA_WIDTH - 1 : 0] RX_RESP_scatter_data_din; +wire RX_RESP_scatter_data_prog_full; + +wire TX_REQ_insert_req_valid; +wire TX_REQ_insert_req_start; +wire TX_REQ_insert_req_last; +wire [`MAX_DB_SLOT_NUM_LOG - 1 : 0] TX_REQ_insert_req_head; +wire [`PACKET_BUFFER_SLOT_WIDTH - 1 : 0] TX_REQ_insert_req_data; +wire TX_REQ_insert_req_ready; + +wire TX_REQ_insert_resp_valid; +wire [`MAX_DB_SLOT_NUM_LOG - 1 : 0] TX_REQ_insert_resp_data; + +wire TX_RESP_insert_req_valid; +wire TX_RESP_insert_req_start; +wire TX_RESP_insert_req_last; +wire [`MAX_DB_SLOT_NUM_LOG - 1 : 0] TX_RESP_insert_req_head; +wire [`PACKET_BUFFER_SLOT_WIDTH - 1 : 0] TX_RESP_insert_req_data; +wire TX_RESP_insert_req_ready; + +wire TX_RESP_insert_resp_valid; +wire [`MAX_DB_SLOT_NUM_LOG - 1 : 0] TX_RESP_insert_resp_data; + +wire RX_REQ_delete_req_valid; +wire [`MAX_DB_SLOT_NUM_LOG * 2 - 1 : 0] RX_REQ_delete_req_head; +wire RX_REQ_delete_req_ready; + +wire RX_REQ_delete_resp_valid; +wire RX_REQ_delete_resp_start; +wire RX_REQ_delete_resp_last; +wire [`PACKET_BUFFER_SLOT_WIDTH - 1 : 0] RX_REQ_delete_resp_data; +wire RX_REQ_delete_resp_ready; + +wire RX_RESP_delete_req_valid; +wire [`MAX_DB_SLOT_NUM_LOG * 2 - 1 : 0] RX_RESP_delete_req_head; +wire RX_RESP_delete_req_ready; + +wire RX_RESP_delete_resp_valid; +wire RX_RESP_delete_resp_start; +wire RX_RESP_delete_resp_last; +wire [`PACKET_BUFFER_SLOT_WIDTH - 1 : 0] RX_RESP_delete_resp_data; +wire RX_RESP_delete_resp_ready; + +wire RX_REQ_ingress_pkt_valid; +wire [`PKT_META_BUS_WIDTH - 1 : 0] RX_REQ_ingress_pkt_head; +wire RX_REQ_ingress_pkt_ready; + +wire RX_RESP_ingress_pkt_valid; +wire [`PKT_META_BUS_WIDTH - 1 : 0] RX_RESP_ingress_pkt_head; +wire RX_RESP_ingress_pkt_ready; + +wire TX_REQ_egress_pkt_valid; +wire [`PKT_META_BUS_WIDTH - 1 : 0] TX_REQ_egress_pkt_head; +wire TX_REQ_egress_pkt_ready; + +wire TX_RESP_egress_pkt_valid; +wire [`PKT_META_BUS_WIDTH - 1 : 0] TX_RESP_egress_pkt_head; +wire TX_RESP_egress_pkt_ready; +/*------------------------------------------- Local Variables Definition : End --------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : Begin ---------------------------------------*/ +RequesterCore +#( + .INGRESS_CXT_HEAD_WIDTH ( INGRESS_CXT_HEAD_WIDTH ), + .INGRESS_CXT_DATA_WIDTH ( INGRESS_CXT_DATA_WIDTH ), + .EGRESS_CXT_HEAD_WIDTH ( EGRESS_CXT_HEAD_WIDTH ), + .EGRESS_CXT_DATA_WIDTH ( EGRESS_CXT_DATA_WIDTH ), + + + .INGRESS_MR_HEAD_WIDTH ( INGRESS_MR_HEAD_WIDTH ), + .INGRESS_MR_DATA_WIDTH ( INGRESS_MR_DATA_WIDTH ), + .EGRESS_MR_HEAD_WIDTH ( EGRESS_MR_HEAD_WIDTH ), + .EGRESS_MR_DATA_WIDTH ( EGRESS_MR_DATA_WIDTH ) +) +RequesterCore_Inst +( + .clk ( clk ), + .rst ( rst ), + + .TX_REQ_sub_wqe_valid ( TX_REQ_sub_wqe_valid ), + .TX_REQ_sub_wqe_meta ( TX_REQ_sub_wqe_meta ), + .TX_REQ_sub_wqe_ready ( TX_REQ_sub_wqe_ready ), + + .TX_REQ_fetch_cxt_ingress_valid ( TX_REQ_fetch_cxt_ingress_valid ), + .TX_REQ_fetch_cxt_ingress_head ( TX_REQ_fetch_cxt_ingress_head ), + .TX_REQ_fetch_cxt_ingress_data ( TX_REQ_fetch_cxt_ingress_data ), + .TX_REQ_fetch_cxt_ingress_start ( TX_REQ_fetch_cxt_ingress_start ), + .TX_REQ_fetch_cxt_ingress_last ( TX_REQ_fetch_cxt_ingress_last ), + .TX_REQ_fetch_cxt_ingress_ready ( TX_REQ_fetch_cxt_ingress_ready ), + + .TX_REQ_fetch_cxt_egress_valid ( TX_REQ_fetch_cxt_egress_valid ), + .TX_REQ_fetch_cxt_egress_head ( TX_REQ_fetch_cxt_egress_head ), + .TX_REQ_fetch_cxt_egress_data ( TX_REQ_fetch_cxt_egress_data ), + .TX_REQ_fetch_cxt_egress_start ( TX_REQ_fetch_cxt_egress_start ), + .TX_REQ_fetch_cxt_egress_last ( TX_REQ_fetch_cxt_egress_last ), + .TX_REQ_fetch_cxt_egress_ready ( TX_REQ_fetch_cxt_egress_ready ), + + .TX_REQ_fetch_mr_ingress_valid ( TX_REQ_fetch_mr_ingress_valid ), + .TX_REQ_fetch_mr_ingress_head ( TX_REQ_fetch_mr_ingress_head ), + .TX_REQ_fetch_mr_ingress_data ( TX_REQ_fetch_mr_ingress_data ), + .TX_REQ_fetch_mr_ingress_start ( TX_REQ_fetch_mr_ingress_start ), + .TX_REQ_fetch_mr_ingress_last ( TX_REQ_fetch_mr_ingress_last ), + .TX_REQ_fetch_mr_ingress_ready ( TX_REQ_fetch_mr_ingress_ready ), + + .TX_REQ_fetch_mr_egress_valid ( TX_REQ_fetch_mr_egress_valid ), + .TX_REQ_fetch_mr_egress_head ( TX_REQ_fetch_mr_egress_head ), + .TX_REQ_fetch_mr_egress_data ( TX_REQ_fetch_mr_egress_data ), + .TX_REQ_fetch_mr_egress_start ( TX_REQ_fetch_mr_egress_start ), + .TX_REQ_fetch_mr_egress_last ( TX_REQ_fetch_mr_egress_last ), + .TX_REQ_fetch_mr_egress_ready ( TX_REQ_fetch_mr_egress_ready ), + + .TX_REQ_cq_req_valid ( TX_REQ_cq_req_valid ), + .TX_REQ_cq_req_head ( TX_REQ_cq_req_head ), + .TX_REQ_cq_req_ready ( TX_REQ_cq_req_ready ), + + .TX_REQ_cq_resp_valid ( TX_REQ_cq_resp_valid ), + .TX_REQ_cq_resp_head ( TX_REQ_cq_resp_head ), + .TX_REQ_cq_resp_ready ( TX_REQ_cq_resp_ready ), + + .TX_REQ_eq_req_valid ( TX_REQ_eq_req_valid ), + .TX_REQ_eq_req_head ( TX_REQ_eq_req_head ), + .TX_REQ_eq_req_ready ( TX_REQ_eq_req_ready ), + + .TX_REQ_eq_resp_valid ( TX_REQ_eq_resp_valid ), + .TX_REQ_eq_resp_head ( TX_REQ_eq_resp_head ), + .TX_REQ_eq_resp_ready ( TX_REQ_eq_resp_ready ), + + .TX_REQ_gather_req_wr_en ( TX_REQ_gather_req_wr_en ), + .TX_REQ_gather_req_din ( TX_REQ_gather_req_din ), + .TX_REQ_gather_req_prog_full ( TX_REQ_gather_req_prog_full ), + + .TX_REQ_net_data_rd_en ( TX_REQ_net_data_rd_en ), + .TX_REQ_net_data_dout ( TX_REQ_net_data_dout ), + .TX_REQ_net_data_empty ( TX_REQ_net_data_empty ), + + .TX_REQ_scatter_req_wen ( TX_REQ_scatter_req_wr_en ), + .TX_REQ_scatter_req_din ( TX_REQ_scatter_req_din ), + .TX_REQ_scatter_req_prog_full ( TX_REQ_scatter_req_prog_full ), + + .TX_REQ_scatter_data_wen ( TX_REQ_scatter_data_wr_en ), + .TX_REQ_scatter_data_din ( TX_REQ_scatter_data_din ), + .TX_REQ_scatter_data_prog_full ( TX_REQ_scatter_data_prog_full ), + + .TX_REQ_insert_req_valid ( TX_REQ_insert_req_valid ), + .TX_REQ_insert_req_start ( TX_REQ_insert_req_start ), + .TX_REQ_insert_req_last ( TX_REQ_insert_req_last ), + .TX_REQ_insert_req_head ( TX_REQ_insert_req_head ), + .TX_REQ_insert_req_data ( TX_REQ_insert_req_data ), + .TX_REQ_insert_req_ready ( TX_REQ_insert_req_ready ), + + .TX_REQ_insert_resp_valid ( TX_REQ_insert_resp_valid ), + .TX_REQ_insert_resp_data ( TX_REQ_insert_resp_data ), + + .TX_REQ_egress_pkt_valid ( TX_REQ_egress_pkt_valid ), + .TX_REQ_egress_pkt_head ( TX_REQ_egress_pkt_head ), + .TX_REQ_egress_pkt_ready ( TX_REQ_egress_pkt_ready ), + + .RX_RESP_ingress_pkt_valid ( RX_RESP_ingress_pkt_valid ), + .RX_RESP_ingress_pkt_head ( RX_RESP_ingress_pkt_head ), + .RX_RESP_ingress_pkt_ready ( RX_RESP_ingress_pkt_ready ), + + .RX_RESP_fetch_cxt_ingress_valid ( RX_RESP_fetch_cxt_ingress_valid ), + .RX_RESP_fetch_cxt_ingress_head ( RX_RESP_fetch_cxt_ingress_head ), + .RX_RESP_fetch_cxt_ingress_data ( RX_RESP_fetch_cxt_ingress_data ), + .RX_RESP_fetch_cxt_ingress_start ( RX_RESP_fetch_cxt_ingress_start ), + .RX_RESP_fetch_cxt_ingress_last ( RX_RESP_fetch_cxt_ingress_last ), + .RX_RESP_fetch_cxt_ingress_ready ( RX_RESP_fetch_cxt_ingress_ready ), + + .RX_RESP_fetch_cxt_egress_valid ( RX_RESP_fetch_cxt_egress_valid ), + .RX_RESP_fetch_cxt_egress_head ( RX_RESP_fetch_cxt_egress_head ), + .RX_RESP_fetch_cxt_egress_data ( RX_RESP_fetch_cxt_egress_data ), + .RX_RESP_fetch_cxt_egress_start ( RX_RESP_fetch_cxt_egress_start ), + .RX_RESP_fetch_cxt_egress_last ( RX_RESP_fetch_cxt_egress_last ), + .RX_RESP_fetch_cxt_egress_ready ( RX_RESP_fetch_cxt_egress_ready ), + + .RX_RESP_fetch_mr_ingress_valid ( RX_RESP_fetch_mr_ingress_valid ), + .RX_RESP_fetch_mr_ingress_head ( RX_RESP_fetch_mr_ingress_head ), + .RX_RESP_fetch_mr_ingress_data ( RX_RESP_fetch_mr_ingress_data ), + .RX_RESP_fetch_mr_ingress_start ( RX_RESP_fetch_mr_ingress_start ), + .RX_RESP_fetch_mr_ingress_last ( RX_RESP_fetch_mr_ingress_last ), + .RX_RESP_fetch_mr_ingress_ready ( RX_RESP_fetch_mr_ingress_ready ), + + .RX_RESP_fetch_mr_egress_valid ( RX_RESP_fetch_mr_egress_valid ), + .RX_RESP_fetch_mr_egress_head ( RX_RESP_fetch_mr_egress_head ), + .RX_RESP_fetch_mr_egress_data ( RX_RESP_fetch_mr_egress_data ), + .RX_RESP_fetch_mr_egress_start ( RX_RESP_fetch_mr_egress_start ), + .RX_RESP_fetch_mr_egress_last ( RX_RESP_fetch_mr_egress_last ), + .RX_RESP_fetch_mr_egress_ready ( RX_RESP_fetch_mr_egress_ready ), + + .RX_RESP_cq_req_valid ( RX_RESP_cq_req_valid ), + .RX_RESP_cq_req_head ( RX_RESP_cq_req_head ), + .RX_RESP_cq_req_ready ( RX_RESP_cq_req_ready ), + + .RX_RESP_cq_resp_valid ( RX_RESP_cq_resp_valid ), + .RX_RESP_cq_resp_head ( RX_RESP_cq_resp_head ), + .RX_RESP_cq_resp_ready ( RX_RESP_cq_resp_ready ), + + .RX_RESP_eq_req_valid ( RX_RESP_eq_req_valid ), + .RX_RESP_eq_req_head ( RX_RESP_eq_req_head ), + .RX_RESP_eq_req_ready ( RX_RESP_eq_req_ready ), + + .RX_RESP_eq_resp_valid ( RX_RESP_eq_resp_valid ), + .RX_RESP_eq_resp_head ( RX_RESP_eq_resp_head ), + .RX_RESP_eq_resp_ready ( RX_RESP_eq_resp_ready ), + + .RX_RESP_scatter_req_wen ( RX_RESP_scatter_req_wr_en ), + .RX_RESP_scatter_req_din ( RX_RESP_scatter_req_din ), + .RX_RESP_scatter_req_prog_full ( RX_RESP_scatter_req_prog_full ), + + .RX_RESP_scatter_data_wen ( RX_RESP_scatter_data_wr_en ), + .RX_RESP_scatter_data_din ( RX_RESP_scatter_data_din ), + .RX_RESP_scatter_data_prog_full ( RX_RESP_scatter_data_prog_full ), + + .RX_RESP_delete_req_valid ( RX_RESP_delete_req_valid ), + .RX_RESP_delete_req_head ( RX_RESP_delete_req_head ), + .RX_RESP_delete_req_ready ( RX_RESP_delete_req_ready ), + + .RX_RESP_delete_resp_valid ( RX_RESP_delete_resp_valid ), + .RX_RESP_delete_resp_start ( RX_RESP_delete_resp_start ), + .RX_RESP_delete_resp_last ( RX_RESP_delete_resp_last ), + .RX_RESP_delete_resp_data ( RX_RESP_delete_resp_data ), + .RX_RESP_delete_resp_ready ( RX_RESP_delete_resp_ready ) +); + +ResponderCore +#( + .INGRESS_CXT_HEAD_WIDTH ( INGRESS_CXT_HEAD_WIDTH ), + .INGRESS_CXT_DATA_WIDTH ( INGRESS_CXT_DATA_WIDTH ), + .EGRESS_CXT_HEAD_WIDTH ( EGRESS_CXT_HEAD_WIDTH ), + .EGRESS_CXT_DATA_WIDTH ( EGRESS_CXT_DATA_WIDTH ), + + .INGRESS_MR_HEAD_WIDTH ( INGRESS_MR_HEAD_WIDTH ), + .INGRESS_MR_DATA_WIDTH ( INGRESS_MR_DATA_WIDTH ), + .EGRESS_MR_HEAD_WIDTH ( EGRESS_MR_HEAD_WIDTH ), + .EGRESS_MR_DATA_WIDTH ( EGRESS_MR_DATA_WIDTH ) +) +ResponderCore_Inst +( + .clk ( clk ), + .rst ( rst ), + + .RX_REQ_ingress_pkt_valid ( RX_REQ_ingress_pkt_valid ), + .RX_REQ_ingress_pkt_head ( RX_REQ_ingress_pkt_head ), + .RX_REQ_ingress_pkt_ready ( RX_REQ_ingress_pkt_ready ), + + .RX_REQ_fetch_cxt_ingress_valid ( RX_REQ_fetch_cxt_ingress_valid ), + .RX_REQ_fetch_cxt_ingress_head ( RX_REQ_fetch_cxt_ingress_head ), + .RX_REQ_fetch_cxt_ingress_data ( RX_REQ_fetch_cxt_ingress_data ), + .RX_REQ_fetch_cxt_ingress_start ( RX_REQ_fetch_cxt_ingress_start ), + .RX_REQ_fetch_cxt_ingress_last ( RX_REQ_fetch_cxt_ingress_last ), + .RX_REQ_fetch_cxt_ingress_ready ( RX_REQ_fetch_cxt_ingress_ready ), + + .RX_REQ_fetch_cxt_egress_valid ( RX_REQ_fetch_cxt_egress_valid ), + .RX_REQ_fetch_cxt_egress_head ( RX_REQ_fetch_cxt_egress_head ), + .RX_REQ_fetch_cxt_egress_data ( RX_REQ_fetch_cxt_egress_data ), + .RX_REQ_fetch_cxt_egress_start ( RX_REQ_fetch_cxt_egress_start ), + .RX_REQ_fetch_cxt_egress_last ( RX_REQ_fetch_cxt_egress_last ), + .RX_REQ_fetch_cxt_egress_ready ( RX_REQ_fetch_cxt_egress_ready ), + + .RX_REQ_fetch_mr_ingress_valid ( RX_REQ_fetch_mr_ingress_valid ), + .RX_REQ_fetch_mr_ingress_head ( RX_REQ_fetch_mr_ingress_head ), + .RX_REQ_fetch_mr_ingress_data ( RX_REQ_fetch_mr_ingress_data ), + .RX_REQ_fetch_mr_ingress_start ( RX_REQ_fetch_mr_ingress_start ), + .RX_REQ_fetch_mr_ingress_last ( RX_REQ_fetch_mr_ingress_last ), + .RX_REQ_fetch_mr_ingress_ready ( RX_REQ_fetch_mr_ingress_ready ), + + .RX_REQ_fetch_mr_egress_valid ( RX_REQ_fetch_mr_egress_valid ), + .RX_REQ_fetch_mr_egress_head ( RX_REQ_fetch_mr_egress_head ), + .RX_REQ_fetch_mr_egress_data ( RX_REQ_fetch_mr_egress_data ), + .RX_REQ_fetch_mr_egress_start ( RX_REQ_fetch_mr_egress_start ), + .RX_REQ_fetch_mr_egress_last ( RX_REQ_fetch_mr_egress_last ), + .RX_REQ_fetch_mr_egress_ready ( RX_REQ_fetch_mr_egress_ready ), + + .RQ_wqe_req_valid ( RQ_wqe_req_valid ), + .RQ_wqe_req_head ( RQ_wqe_req_head ), + .RQ_wqe_req_start ( RQ_wqe_req_start ), + .RQ_wqe_req_last ( RQ_wqe_req_last ), + .RQ_wqe_req_ready ( RQ_wqe_req_ready ), + + .RQ_wqe_resp_valid ( RQ_wqe_resp_valid ), + .RQ_wqe_resp_head ( RQ_wqe_resp_head ), + .RQ_wqe_resp_data ( RQ_wqe_resp_data ), + .RQ_wqe_resp_start ( RQ_wqe_resp_start ), + .RQ_wqe_resp_last ( RQ_wqe_resp_last ), + .RQ_wqe_resp_ready ( RQ_wqe_resp_ready ), + + .RQ_cache_offset_wen ( RQ_cache_offset_wen ), + .RQ_cache_offset_addr ( RQ_cache_offset_addr ), + .RQ_cache_offset_din ( RQ_cache_offset_din ), + .RQ_cache_offset_dout ( RQ_cache_offset_dout ), + + .RQ_offset_wen ( RQ_offset_wen ), + .RQ_offset_addr ( RQ_offset_addr ), + .RQ_offset_din ( RQ_offset_din ), + .RQ_offset_dout ( RQ_offset_dout ), + + .RQ_cache_owned_wen ( RQ_cache_owned_wen ), + .RQ_cache_owned_addr ( RQ_cache_owned_addr ), + .RQ_cache_owned_din ( RQ_cache_owned_din ), + .RQ_cache_owned_dout ( RQ_cache_owned_dout ), + + .RX_REQ_cq_req_valid ( RX_REQ_cq_req_valid ), + .RX_REQ_cq_req_head ( RX_REQ_cq_req_head ), + .RX_REQ_cq_req_ready ( RX_REQ_cq_req_ready ), + + .RX_REQ_cq_resp_valid ( RX_REQ_cq_resp_valid ), + .RX_REQ_cq_resp_head ( RX_REQ_cq_resp_head ), + .RX_REQ_cq_resp_ready ( RX_REQ_cq_resp_ready ), + + .RX_REQ_eq_req_valid ( RX_REQ_eq_req_valid ), + .RX_REQ_eq_req_head ( RX_REQ_eq_req_head ), + .RX_REQ_eq_req_ready ( RX_REQ_eq_req_ready ), + + .RX_REQ_eq_resp_valid ( RX_REQ_eq_resp_valid ), + .RX_REQ_eq_resp_head ( RX_REQ_eq_resp_head ), + .RX_REQ_eq_resp_ready ( RX_REQ_eq_resp_ready ), + + .RX_REQ_delete_req_valid ( RX_REQ_delete_req_valid ), + .RX_REQ_delete_req_head ( RX_REQ_delete_req_head ), + .RX_REQ_delete_req_ready ( RX_REQ_delete_req_ready ), + + .RX_REQ_delete_resp_valid ( RX_REQ_delete_resp_valid ), + .RX_REQ_delete_resp_start ( RX_REQ_delete_resp_start ), + .RX_REQ_delete_resp_last ( RX_REQ_delete_resp_last ), + .RX_REQ_delete_resp_data ( RX_REQ_delete_resp_data ), + .RX_REQ_delete_resp_ready ( RX_REQ_delete_resp_ready ), + + .RX_REQ_scatter_req_wr_en ( RX_REQ_scatter_req_wr_en ), + .RX_REQ_scatter_req_din ( RX_REQ_scatter_req_din ), + .RX_REQ_scatter_req_prog_full ( RX_REQ_scatter_req_prog_full ), + + .RX_REQ_scatter_data_wr_en ( RX_REQ_scatter_data_wr_en ), + .RX_REQ_scatter_data_din ( RX_REQ_scatter_data_din ), + .RX_REQ_scatter_data_prog_full ( RX_REQ_scatter_data_prog_full ), + + .TX_RESP_gather_req_wr_en ( TX_RESP_gather_req_wr_en ), + .TX_RESP_gather_req_din ( TX_RESP_gather_req_din ), + .TX_RESP_gather_req_prog_full ( TX_RESP_gather_req_prog_full ), + + .TX_RESP_payload_empty ( TX_RESP_payload_empty ), + .TX_RESP_payload_data ( TX_RESP_payload_dout ), + .TX_RESP_payload_rd_en ( TX_RESP_payload_rd_en ), + + .TX_RESP_insert_req_valid ( TX_RESP_insert_req_valid ), + .TX_RESP_insert_req_start ( TX_RESP_insert_req_start ), + .TX_RESP_insert_req_last ( TX_RESP_insert_req_last ), + .TX_RESP_insert_req_head ( TX_RESP_insert_req_head ), + .TX_RESP_insert_req_data ( TX_RESP_insert_req_data ), + .TX_RESP_insert_req_ready ( TX_RESP_insert_req_ready ), + + .TX_RESP_insert_resp_valid ( TX_RESP_insert_resp_valid ), + .TX_RESP_insert_resp_data ( TX_RESP_insert_resp_data ), + + .TX_RESP_egress_pkt_valid ( TX_RESP_egress_pkt_valid ), + .TX_RESP_egress_pkt_head ( TX_RESP_egress_pkt_head ), + .TX_RESP_egress_pkt_ready ( TX_RESP_egress_pkt_ready ) +); + +GatherData TX_GatherData_Inst( + .clk ( clk ), + .rst ( rst ), + + .gather_req_wr_en ( TX_REQ_gather_req_wr_en ), + .gather_req_din ( TX_REQ_gather_req_din ), + .gather_req_prog_full ( TX_REQ_gather_req_prog_full ), + + .dma_rd_req_valid ( TX_REQ_dma_rd_req_valid ), + .dma_rd_req_head ( TX_REQ_dma_rd_req_head ), + .dma_rd_req_data ( TX_REQ_dma_rd_req_data ), + .dma_rd_req_last ( TX_REQ_dma_rd_req_last ), + .dma_rd_req_ready ( TX_REQ_dma_rd_req_ready ), + + .dma_rd_rsp_valid ( TX_REQ_dma_rd_rsp_valid ), + .dma_rd_rsp_head ( TX_REQ_dma_rd_rsp_head ), + .dma_rd_rsp_data ( TX_REQ_dma_rd_rsp_data ), + .dma_rd_rsp_last ( TX_REQ_dma_rd_rsp_last ), + .dma_rd_rsp_ready ( TX_REQ_dma_rd_rsp_ready ), + + .gather_resp_rd_en ( TX_REQ_net_data_rd_en ), + .gather_resp_empty ( TX_REQ_net_data_empty ), + .gather_resp_dout ( TX_REQ_net_data_dout ) +); + +GatherData RX_GatherData_Inst( + .clk ( clk ), + .rst ( rst ), + + .gather_req_wr_en ( TX_RESP_gather_req_wr_en ), + .gather_req_din ( TX_RESP_gather_req_din ), + .gather_req_prog_full ( TX_RESP_gather_req_prog_full ), + + .dma_rd_req_valid ( TX_RESP_dma_rd_req_valid ), + .dma_rd_req_head ( TX_RESP_dma_rd_req_head ), + .dma_rd_req_data ( TX_RESP_dma_rd_req_data ), + .dma_rd_req_last ( TX_RESP_dma_rd_req_last ), + .dma_rd_req_ready ( TX_RESP_dma_rd_req_ready ), + + .dma_rd_rsp_valid ( TX_RESP_dma_rd_rsp_valid ), + .dma_rd_rsp_head ( TX_RESP_dma_rd_rsp_head ), + .dma_rd_rsp_data ( TX_RESP_dma_rd_rsp_data ), + .dma_rd_rsp_last ( TX_RESP_dma_rd_rsp_last ), + .dma_rd_rsp_ready ( TX_RESP_dma_rd_rsp_ready ), + + .gather_resp_rd_en ( TX_RESP_payload_rd_en ), + .gather_resp_empty ( TX_RESP_payload_empty ), + .gather_resp_dout ( TX_RESP_payload_dout ) +); + +ScatterData TX_REQ_ScatterData_Inst( + .clk ( clk ), + .rst ( rst ), + + .scatter_req_wr_en ( TX_REQ_scatter_req_wr_en ), + .scatter_req_din ( TX_REQ_scatter_req_din ), + .scatter_req_prog_full ( TX_REQ_scatter_req_prog_full ), + + .scatter_data_wr_en ( TX_REQ_scatter_data_wr_en ), + .scatter_data_din ( TX_REQ_scatter_data_din ), + .scatter_data_prog_full ( TX_REQ_scatter_data_prog_full ), + + .dma_wr_req_valid ( TX_REQ_dma_wr_req_valid ), + .dma_wr_req_last ( TX_REQ_dma_wr_req_last ), + .dma_wr_req_head ( TX_REQ_dma_wr_req_head ), + .dma_wr_req_data ( TX_REQ_dma_wr_req_data ), + .dma_wr_req_ready ( TX_REQ_dma_wr_req_ready ) +); + +ScatterData RX_REQ_ScatterData_Inst( + .clk ( clk ), + .rst ( rst ), + + .scatter_req_wr_en ( RX_REQ_scatter_req_wr_en ), + .scatter_req_din ( RX_REQ_scatter_req_din ), + .scatter_req_prog_full ( RX_REQ_scatter_req_prog_full ), + + .scatter_data_wr_en ( RX_REQ_scatter_data_wr_en ), + .scatter_data_din ( RX_REQ_scatter_data_din ), + .scatter_data_prog_full ( RX_REQ_scatter_data_prog_full ), + + .dma_wr_req_valid ( RX_REQ_dma_wr_req_valid ), + .dma_wr_req_last ( RX_REQ_dma_wr_req_last ), + .dma_wr_req_head ( RX_REQ_dma_wr_req_head ), + .dma_wr_req_data ( RX_REQ_dma_wr_req_data ), + .dma_wr_req_ready ( RX_REQ_dma_wr_req_ready ) +); + +ScatterData RX_RESP_ScatterData_Inst( + .clk ( clk ), + .rst ( rst ), + + .scatter_req_wr_en ( RX_RESP_scatter_req_wr_en ), + .scatter_req_din ( RX_RESP_scatter_req_din ), + .scatter_req_prog_full ( RX_RESP_scatter_req_prog_full ), + + .scatter_data_wr_en ( RX_RESP_scatter_data_wr_en ), + .scatter_data_din ( RX_RESP_scatter_data_din ), + .scatter_data_prog_full ( RX_RESP_scatter_data_prog_full ), + + .dma_wr_req_valid ( RX_RESP_dma_wr_req_valid ), + .dma_wr_req_last ( RX_RESP_dma_wr_req_last ), + .dma_wr_req_head ( RX_RESP_dma_wr_req_head ), + .dma_wr_req_data ( RX_RESP_dma_wr_req_data ), + .dma_wr_req_ready ( RX_RESP_dma_wr_req_ready ) +); + +AXISArbiter +#( + .HEAD_WIDTH ( `PKT_META_BUS_WIDTH ), + .DATA_WIDTH ( 64 ) //Unused +) +TX_Arbiter_Inst +( + .clk ( clk ), + .rst ( rst ), + + .in_axis_valid_a ( TX_REQ_egress_pkt_valid ), + .in_axis_head_a ( TX_REQ_egress_pkt_head ), + .in_axis_data_a ( 'd0 ), + .in_axis_start_a ( TX_REQ_egress_pkt_valid ), + .in_axis_last_a ( TX_REQ_egress_pkt_valid ), + .in_axis_ready_a ( TX_REQ_egress_pkt_ready ), + + .in_axis_valid_b ( TX_RESP_egress_pkt_valid ), + .in_axis_head_b ( TX_RESP_egress_pkt_head ), + .in_axis_data_b ( 'd0 ), + .in_axis_start_b ( TX_RESP_egress_pkt_valid ), + .in_axis_last_b ( TX_RESP_egress_pkt_valid ), + .in_axis_ready_b ( TX_RESP_egress_pkt_ready ), + + .out_axis_valid ( TX_egress_pkt_valid ), + .out_axis_head ( TX_egress_pkt_head ), + .out_axis_data ( ), + .out_axis_start ( ), + .out_axis_last ( ), + .out_axis_ready ( TX_egress_pkt_ready ) +); + +// TXArbiter TX_Arbiter_Inst( +// .clk ( clk ), +// .rst ( rst ), + +// .chnl_0_pkt_valid ( TX_REQ_egress_pkt_valid ), +// .chnl_0_pkt_head ( TX_REQ_egress_pkt_head ), +// .chnl_0_pkt_ready ( TX_REQ_egress_pkt_ready ), + +// .chnl_1_pkt_valid ( TX_RESP_egress_pkt_valid ), +// .chnl_1_pkt_head ( TX_RESP_egress_pkt_head ), +// .chnl_1_pkt_ready ( TX_RESP_egress_pkt_ready ), + +// .egress_pkt_valid ( TX_egress_pkt_valid ), +// .egress_pkt_head ( TX_egress_pkt_head ), +// .egress_pkt_ready ( TX_egress_pkt_ready ) +// ); + +RXDispatcher RX_Dispatcher_Inst( + .clk ( clk ), + .rst ( rst ), + + .ingress_pkt_valid ( RX_ingress_pkt_valid ), + .ingress_pkt_head ( RX_ingress_pkt_head ), + .ingress_pkt_ready ( RX_ingress_pkt_ready ), + + .req_recv_pkt_valid ( RX_REQ_ingress_pkt_valid ), + .req_recv_pkt_head ( RX_REQ_ingress_pkt_head ), + .req_recv_pkt_ready ( RX_REQ_ingress_pkt_ready ), + + .resp_recv_pkt_valid ( RX_RESP_ingress_pkt_valid ), + .resp_recv_pkt_head ( RX_RESP_ingress_pkt_head ), + .resp_recv_pkt_ready ( RX_RESP_ingress_pkt_ready ) +); + +DynamicBufferInsertArbiter PacketBufferInsertArbiter_Inst( + .clk ( clk ), + .rst ( rst ), + + .chnl_0_req_valid ( TX_REQ_insert_req_valid ), + .chnl_0_req_start ( TX_REQ_insert_req_start ), + .chnl_0_req_last ( TX_REQ_insert_req_last ), + .chnl_0_req_head ( TX_REQ_insert_req_head ), + .chnl_0_req_data ( TX_REQ_insert_req_data ), + .chnl_0_req_ready ( TX_REQ_insert_req_ready ), + + .chnl_0_resp_valid ( TX_REQ_insert_resp_valid ), + .chnl_0_resp_data ( TX_REQ_insert_resp_data ), + + .chnl_1_req_valid ( TX_RESP_insert_req_valid ), + .chnl_1_req_start ( TX_RESP_insert_req_start ), + .chnl_1_req_last ( TX_RESP_insert_req_last ), + .chnl_1_req_head ( TX_RESP_insert_req_head ), + .chnl_1_req_data ( TX_RESP_insert_req_data ), + .chnl_1_req_ready ( TX_RESP_insert_req_ready ), + + .chnl_1_resp_valid ( TX_RESP_insert_resp_valid ), + .chnl_1_resp_data ( TX_RESP_insert_resp_data ), + + .insert_req_valid ( TX_insert_req_valid ), + .insert_req_start ( TX_insert_req_start ), + .insert_req_last ( TX_insert_req_last ), + .insert_req_head ( TX_insert_req_head ), + .insert_req_data ( TX_insert_req_data ), + .insert_req_ready ( TX_insert_req_ready ), + + .insert_resp_valid ( TX_insert_resp_valid ), + .insert_resp_data ( TX_insert_resp_data ) +); + +DynamicBufferDeleteArbiter PacketBufferDeleteArbiter_Inst( + .clk ( clk ), + .rst ( rst ), + + .chnl_0_req_valid ( RX_REQ_delete_req_valid ), + .chnl_0_req_head ( RX_REQ_delete_req_head ), + .chnl_0_req_ready ( RX_REQ_delete_req_ready ), + + .chnl_0_resp_valid ( RX_REQ_delete_resp_valid ), + .chnl_0_resp_start ( RX_REQ_delete_resp_start ), + .chnl_0_resp_last ( RX_REQ_delete_resp_last ), + .chnl_0_resp_data ( RX_REQ_delete_resp_data ), + .chnl_0_resp_ready ( RX_REQ_delete_resp_ready ), + + .chnl_1_req_valid ( RX_RESP_delete_req_valid ), + .chnl_1_req_head ( RX_RESP_delete_req_head ), + .chnl_1_req_ready ( RX_RESP_delete_req_ready ), + + .chnl_1_resp_valid ( RX_RESP_delete_resp_valid ), + .chnl_1_resp_start ( RX_RESP_delete_resp_start ), + .chnl_1_resp_last ( RX_RESP_delete_resp_last ), + .chnl_1_resp_data ( RX_RESP_delete_resp_data ), + .chnl_1_resp_ready ( RX_RESP_delete_resp_ready ), + + .delete_req_valid ( RX_delete_req_valid ), + .delete_req_head ( RX_delete_req_head ), + .delete_req_ready ( RX_delete_req_ready ), + + .delete_resp_valid ( RX_delete_resp_valid ), + .delete_resp_start ( RX_delete_resp_start ), + .delete_resp_last ( RX_delete_resp_last ), + .delete_resp_data ( RX_delete_resp_data ), + .delete_resp_ready ( RX_delete_resp_ready ) +); +/*------------------------------------------- Submodules Instatiation : End -----------------------------------------*/ + +/*------------------------------------------- State Machine Definition : Begin --------------------------------------*/ +/*------------------------------------------- State Machine Definition : End ----------------------------------------*/ + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ +/*------------------------------------------- Variables Decode : End ----------------------------------------------*/ + +/*------------------------------------------- Local Macros Undef : Begin --------------------------------------------*/ +/*------------------------------------------- Local Macros Undef : End ----------------------------------------------*/ + +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/RPCSubsystem/RDMACore/RequesterCore/ReqTransCore/ReqTransCore.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/RPCSubsystem/RDMACore/RequesterCore/ReqTransCore/ReqTransCore.v new file mode 100644 index 0000000000000000000000000000000000000000..64a1b36257225c6f226ff0f67d1f9e1244019532 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/RPCSubsystem/RDMACore/RequesterCore/ReqTransCore/ReqTransCore.v @@ -0,0 +1,310 @@ +/*------------------------------------------- Module Description : Begin ---------------------------------------------- +Name: ReqTransCore +Author: YangFan +Function: 1.Emit Sub-WQEs. +--------------------------------------------- Module Decription : End -----------------------------------------------*/ + +/*------------------------------------------- Timescale Definition : Begin ------------------------------------------*/ +`timescale 1ns / 1ps +/*------------------------------------------- Timescale Definition : End --------------------------------------------*/ + +/*------------------------------------------- Included Files : Begin ------------------------------------------------*/ +`include "protocol_engine_def.vh" +/*------------------------------------------- Included Files : End --------------------------------------------------*/ + +/*------------------------------------------- Input/Output Definition : Begin ---------------------------------------*/ +module ReqTransCore +#( + parameter INGRESS_CXT_HEAD_WIDTH = 128, + parameter INGRESS_CXT_DATA_WIDTH = 256, + parameter EGRESS_CXT_HEAD_WIDTH = 128, + parameter EGRESS_CXT_DATA_WIDTH = 256, + + + parameter INGRESS_MR_HEAD_WIDTH = 128, + parameter INGRESS_MR_DATA_WIDTH = 256, + parameter EGRESS_MR_HEAD_WIDTH = 128, + parameter EGRESS_MR_DATA_WIDTH = 256 +) +( + input wire clk, + input wire rst, + +//Interface with WQEParser + input wire sub_wqe_valid, + input wire [`WQE_META_WIDTH - 1 : 0] sub_wqe_meta, + output wire sub_wqe_ready, + +//Interface with OoOStation(For CxtMgt) + output wire fetch_cxt_ingress_valid, + output wire [`TX_REQ_OOO_CXT_INGRESS_HEAD_WIDTH - 1 : 0] fetch_cxt_ingress_head, + output wire [`TX_REQ_OOO_CXT_INGRESS_DATA_WIDTH - 1 : 0] fetch_cxt_ingress_data, + output wire fetch_cxt_ingress_start, + output wire fetch_cxt_ingress_last, + input wire fetch_cxt_ingress_ready, + + input wire fetch_cxt_egress_valid, + input wire [`TX_REQ_OOO_CXT_EGRESS_HEAD_WIDTH - 1 : 0] fetch_cxt_egress_head, + input wire [`TX_REQ_OOO_CXT_EGRESS_DATA_WIDTH - 1 : 0] fetch_cxt_egress_data, + input wire fetch_cxt_egress_start, + input wire fetch_cxt_egress_last, + output wire fetch_cxt_egress_ready, + +//Interface with OoOStation(For MRMgt) + output wire fetch_mr_ingress_valid, + output wire [`TX_REQ_OOO_MR_INGRESS_HEAD_WIDTH - 1 : 0] fetch_mr_ingress_head, + output wire [`TX_REQ_OOO_MR_INGRESS_DATA_WIDTH - 1 : 0] fetch_mr_ingress_data, + output wire fetch_mr_ingress_start, + output wire fetch_mr_ingress_last, + input wire fetch_mr_ingress_ready, + + input wire fetch_mr_egress_valid, + input wire [`TX_REQ_OOO_MR_EGRESS_HEAD_WIDTH - 1 : 0] fetch_mr_egress_head, + input wire [`TX_REQ_OOO_MR_EGRESS_DATA_WIDTH - 1 : 0] fetch_mr_egress_data, + input wire fetch_mr_egress_start, + input wire fetch_mr_egress_last, + output wire fetch_mr_egress_ready, + +//Interface with CompletionQueueMgt + output wire cq_req_valid, + output wire [`CQ_REQ_HEAD_WIDTH - 1 : 0] cq_req_head, + input wire cq_req_ready, + + input wire cq_resp_valid, + input wire [`CQ_RESP_HEAD_WIDTH - 1 : 0] cq_resp_head, + output wire cq_resp_ready, + +//Interface with EventQueueMgt + output wire eq_req_valid, + output wire [`EQ_REQ_HEAD_WIDTH - 1 : 0] eq_req_head, + input wire eq_req_ready, + + input wire eq_resp_valid, + input wire [`EQ_RESP_HEAD_WIDTH - 1 : 0] eq_resp_head, + output wire eq_resp_ready, + +//DMA Read Interface + output wire gather_req_wr_en, + output wire [`DMA_LENGTH_WIDTH * 2 + `DMA_ADDR_WIDTH - 1 : 0] gather_req_din, + input wire gather_req_prog_full, + +//Interface with GatherData + output wire net_data_rd_en, + input wire [`DMA_DATA_WIDTH - 1 : 0] net_data_dout, + input wire net_data_empty, + +//ScatterData Req Interface + output wire scatter_req_wen, + output wire [`DMA_LENGTH_WIDTH * 2 + `DMA_ADDR_WIDTH - 1 : 0] scatter_req_din, + input wire scatter_req_prog_full, + + output wire scatter_data_wen, + output wire [`DMA_DATA_WIDTH - 1 : 0] scatter_data_din, + input wire scatter_data_prog_full, + +//Interface WQEBuffer + output wire enqueue_req_valid, + output wire [`MAX_QP_NUM_LOG + `MAX_DMQ_SLOT_NUM_LOG - 1 : 0] enqueue_req_head, + output wire [`RC_WQE_BUFFER_SLOT_WIDTH - 1 : 0] enqueue_req_data, + output wire enqueue_req_start, + output wire enqueue_req_last, + input wire enqueue_req_ready, + +//Interface with PacketBuffer + output wire insert_req_valid, + output wire insert_req_start, + output wire insert_req_last, + output wire [`MAX_DB_SLOT_NUM_LOG - 1 : 0] insert_req_head, + output wire [`PACKET_BUFFER_SLOT_WIDTH - 1 : 0] insert_req_data, + input wire insert_req_ready, + + input wire insert_resp_valid, + input wire [`MAX_DB_SLOT_NUM_LOG - 1 : 0] insert_resp_data, + +//Interface with TransportSubsystem + output wire egress_pkt_valid, + output wire [`PKT_META_BUS_WIDTH - 1 : 0] egress_pkt_head, + input wire egress_pkt_ready +); + +/*------------------------------------------- Input/Output Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Macros Definition : Begin ---------------------------------------*/ +/*------------------------------------------- Local Macros Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Variables Definition : Begin ------------------------------------*/ +wire net_req_wen; +wire [`WQE_META_WIDTH - 1 : 0] net_req_din; +wire net_req_prog_full; + +wire net_req_ren; +wire [`WQE_META_WIDTH - 1 : 0] net_req_dout; +wire net_req_empty; +/*------------------------------------------- Local Variables Definition : End --------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : Begin ---------------------------------------*/ +ReqTransCore_Thread_1 #( + .INGRESS_CXT_HEAD_WIDTH ( INGRESS_CXT_HEAD_WIDTH ), + .INGRESS_CXT_DATA_WIDTH ( INGRESS_CXT_DATA_WIDTH ) +) +ReqTransCore_Thread_1_Inst +( + .clk ( clk ), + .rst ( rst ), + + .sub_wqe_valid ( sub_wqe_valid ), + .sub_wqe_meta ( sub_wqe_meta ), + .sub_wqe_ready ( sub_wqe_ready ), + + .fetch_cxt_ingress_valid ( fetch_cxt_ingress_valid ), + .fetch_cxt_ingress_head ( fetch_cxt_ingress_head ), + .fetch_cxt_ingress_data ( fetch_cxt_ingress_data ), + .fetch_cxt_ingress_start ( fetch_cxt_ingress_start ), + .fetch_cxt_ingress_last ( fetch_cxt_ingress_last ), + .fetch_cxt_ingress_ready ( fetch_cxt_ingress_ready ) +); + +ReqTransCore_Thread_2 #( + .EGRESS_CXT_HEAD_WIDTH ( EGRESS_CXT_HEAD_WIDTH ), + .EGRESS_CXT_DATA_WIDTH ( EGRESS_CXT_DATA_WIDTH ), + + + .INGRESS_MR_HEAD_WIDTH ( INGRESS_MR_HEAD_WIDTH ), + .INGRESS_MR_DATA_WIDTH ( INGRESS_MR_DATA_WIDTH ) +) +ReqTransCore_Thread_2_Inst +( + .clk ( clk ), + .rst ( rst ), + + .fetch_cxt_egress_valid ( fetch_cxt_egress_valid ), + .fetch_cxt_egress_head ( fetch_cxt_egress_head ), + .fetch_cxt_egress_data ( fetch_cxt_egress_data ), + .fetch_cxt_egress_start ( fetch_cxt_egress_start ), + .fetch_cxt_egress_last ( fetch_cxt_egress_last ), + .fetch_cxt_egress_ready ( fetch_cxt_egress_ready ), + + .fetch_mr_ingress_valid ( fetch_mr_ingress_valid ), + .fetch_mr_ingress_head ( fetch_mr_ingress_head ), + .fetch_mr_ingress_data ( fetch_mr_ingress_data ), + .fetch_mr_ingress_start ( fetch_mr_ingress_start ), + .fetch_mr_ingress_last ( fetch_mr_ingress_last ), + .fetch_mr_ingress_ready ( fetch_mr_ingress_ready ), + + .cq_req_valid ( cq_req_valid ), + .cq_req_head ( cq_req_head ), + .cq_req_ready ( cq_req_ready ), + + .cq_resp_valid ( cq_resp_valid ), + .cq_resp_head ( cq_resp_head ), + .cq_resp_ready ( cq_resp_ready ), + + .eq_req_valid ( eq_req_valid ), + .eq_req_head ( eq_req_head ), + .eq_req_ready ( eq_req_ready ), + + .eq_resp_valid ( eq_resp_valid ), + .eq_resp_head ( eq_resp_head ), + .eq_resp_ready ( eq_resp_ready ) +); + +ReqTransCore_Thread_3 #( + .EGRESS_MR_HEAD_WIDTH ( EGRESS_MR_HEAD_WIDTH ), + .EGRESS_MR_DATA_WIDTH ( EGRESS_MR_DATA_WIDTH ) +) +ReqTransCore_Thread_3_Inst +( + .clk ( clk ), + .rst ( rst ), + + .fetch_mr_egress_valid ( fetch_mr_egress_valid ), + .fetch_mr_egress_head ( fetch_mr_egress_head ), + .fetch_mr_egress_data ( fetch_mr_egress_data ), + .fetch_mr_egress_start ( fetch_mr_egress_start ), + .fetch_mr_egress_last ( fetch_mr_egress_last ), + .fetch_mr_egress_ready ( fetch_mr_egress_ready ), + + .net_req_wen ( net_req_wen ), + .net_req_din ( net_req_din ), + .net_req_prog_full ( net_req_prog_full ), + + .gather_req_wr_en ( gather_req_wr_en ), + .gather_req_din ( gather_req_din ), + .gather_req_prog_full ( gather_req_prog_full ) +); + +ReqTransCore_Thread_4 ReqTransCore_Thread_4_Inst( + .clk ( clk ), + .rst ( rst ), + + .net_req_ren ( net_req_ren ), + .net_req_dout ( net_req_dout ), + .net_req_empty ( net_req_empty ), + + .net_data_rd_en ( net_data_rd_en ), + .net_data_dout ( net_data_dout ), + .net_data_empty ( net_data_empty ), + + .scatter_req_wen ( scatter_req_wen ), + .scatter_req_din ( scatter_req_din ), + .scatter_req_prog_full ( scatter_req_prog_full ), + + .scatter_data_wen ( scatter_data_wen ), + .scatter_data_din ( scatter_data_din ), + .scatter_data_prog_full ( scatter_data_prog_full ), + + .enqueue_req_valid ( enqueue_req_valid ), + .enqueue_req_head ( enqueue_req_head ), + .enqueue_req_data ( enqueue_req_data ), + .enqueue_req_start ( enqueue_req_start ), + .enqueue_req_last ( enqueue_req_last ), + .enqueue_req_ready ( enqueue_req_ready ), + + .insert_req_valid ( insert_req_valid ), + .insert_req_start ( insert_req_start ), + .insert_req_last ( insert_req_last ), + .insert_req_head ( insert_req_head ), + .insert_req_data ( insert_req_data ), + .insert_req_ready ( insert_req_ready ), + + .insert_resp_valid ( insert_resp_valid ), + .insert_resp_data ( insert_resp_data ), + + .egress_pkt_valid ( egress_pkt_valid ), + .egress_pkt_head ( egress_pkt_head ), + .egress_pkt_ready ( egress_pkt_ready ) +); + +SyncFIFO_Template #( + .FIFO_WIDTH ( `WQE_META_WIDTH ), + .FIFO_DEPTH ( 32 ) +) +NetReqFIFO_Inst +( + .clk ( clk ), + .rst ( rst ), + + .wr_en ( net_req_wen ), + .din ( net_req_din ), + .prog_full ( net_req_prog_full ), + + .rd_en ( net_req_ren ), + .dout ( net_req_dout ), + .empty ( net_req_empty ), + + .data_count ( ) +); + +/*------------------------------------------- Submodules Instatiation : End -----------------------------------------*/ + +/*------------------------------------------- State Machine Definition : Begin --------------------------------------*/ +/*------------------------------------------- State Machine Definition : End ----------------------------------------*/ + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ +/*------------------------------------------- Variables Decode : End ----------------------------------------------*/ + +/*------------------------------------------- Local Macros Undef : Begin --------------------------------------------*/ + +/*------------------------------------------- Local Macros Undef : End ----------------------------------------------*/ + +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/RPCSubsystem/RDMACore/RequesterCore/ReqTransCore/ReqTransCore_Thread_1.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/RPCSubsystem/RDMACore/RequesterCore/ReqTransCore/ReqTransCore_Thread_1.v new file mode 100644 index 0000000000000000000000000000000000000000..b60beb40a01eed4a2ef70264820a4f2593107961 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/RPCSubsystem/RDMACore/RequesterCore/ReqTransCore/ReqTransCore_Thread_1.v @@ -0,0 +1,135 @@ +/*------------------------------------------- Module Description : Begin ---------------------------------------------- +Name: ReqTransCore_Thread_1 +Author: YangFan +Function: 1.Fetch Cxt and generate Net Meta. +--------------------------------------------- Module Decription : End -----------------------------------------------*/ + +/*------------------------------------------- Timescale Definition : Begin ------------------------------------------*/ +`timescale 1ns / 1ps +/*------------------------------------------- Timescale Definition : End --------------------------------------------*/ + +/*------------------------------------------- Included Files : Begin ------------------------------------------------*/ +`include "protocol_engine_def.vh" +/*------------------------------------------- Included Files : End --------------------------------------------------*/ + +/*------------------------------------------- Input/Output Definition : Begin ---------------------------------------*/ +module ReqTransCore_Thread_1 +#( + parameter INGRESS_CXT_HEAD_WIDTH = 128, + parameter INGRESS_CXT_DATA_WIDTH = 256 +) +( + input wire clk, + input wire rst, + +//Interface with WQEParser + input wire sub_wqe_valid, + input wire [`WQE_META_WIDTH - 1 : 0] sub_wqe_meta, + output wire sub_wqe_ready, + +//Interface with OoOStation(For CxtMgt) + output wire fetch_cxt_ingress_valid, + output wire [`TX_REQ_OOO_CXT_INGRESS_HEAD_WIDTH - 1 : 0] fetch_cxt_ingress_head, + output wire [`TX_REQ_OOO_CXT_INGRESS_DATA_WIDTH - 1 : 0] fetch_cxt_ingress_data, + output wire fetch_cxt_ingress_start, + output wire fetch_cxt_ingress_last, + input wire fetch_cxt_ingress_ready +); +/*------------------------------------------- Input/Output Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Macros Definition : Begin ---------------------------------------*/ +`define LOCAL_QPN_OFFSET 15:0 + +/*------------------------------------------- Local Macros Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Variables Definition : Begin ------------------------------------*/ +wire [`INGRESS_COMMON_HEAD_WIDTH - 1 : 0] ingress_common_head; +wire [`MAX_OOO_SLOT_NUM_LOG - 1 :0] ingress_slot_count; + +reg [`WQE_META_WIDTH - 1 : 0] sub_wqe_meta_diff; +/*------------------------------------------- Local Variables Definition : End --------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : Begin ---------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : End -----------------------------------------*/ + +/*------------------------------------------- State Machine Definition : Begin --------------------------------------*/ +reg [1:0] cur_state; +reg [1:0] next_state; + +parameter [1:0] IDLE_s = 2'd1, + FETCH_CXT_s = 2'd2; + +always @(posedge clk or posedge rst) begin + if(rst) begin + cur_state <= IDLE_s; + end + else begin + cur_state <= next_state; + end +end + +always @(*) begin + case(cur_state) + IDLE_s: if(sub_wqe_valid) begin + next_state = FETCH_CXT_s; + end + else begin + next_state = IDLE_s; + end + FETCH_CXT_s: if(fetch_cxt_ingress_valid && fetch_cxt_ingress_ready) begin + next_state = IDLE_s; + end + else begin + next_state = FETCH_CXT_s; + end + default: next_state = IDLE_s; + endcase +end +/*------------------------------------------- State Machine Definition : End ----------------------------------------*/ + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ +//-- sub_wqe_meta_diff -- +always @(posedge clk or posedge rst) begin + if (rst) begin + sub_wqe_meta_diff <= 'd0; + end + else if (cur_state == IDLE_s && sub_wqe_valid) begin + sub_wqe_meta_diff <= sub_wqe_meta; + end + else begin + sub_wqe_meta_diff <= sub_wqe_meta_diff; + end +end + +wire [`QP_NUM_LOG - 1 : 0] qpn_data; +assign qpn_data = (cur_state == IDLE_s && sub_wqe_valid) ? sub_wqe_meta[`LOCAL_QPN_OFFSET] : sub_wqe_meta_diff[`LOCAL_QPN_OFFSET]; + +wire [`MAX_QP_NUM_LOG - 1 : 0] queue_index; +assign queue_index = {'d0, qpn_data[`QP_NUM_LOG - 1 : 0]}; + +//-- ingress_common_head -- +//-- ingress_slot_count -- +assign ingress_common_head = {`NO_BYPASS, ingress_slot_count, queue_index}; +assign ingress_slot_count = 'd1; + +//-- fetch_cxt_ingress_valid -- +//-- fetch_cxt_ingress_head -- +//-- fetch_cxt_ingress_data -- +//-- fetch_cxt_ingress_start -- +//-- fetch_cxt_ingress_last -- +assign fetch_cxt_ingress_valid = (cur_state == FETCH_CXT_s) ? 'd1 : 'd0; +assign fetch_cxt_ingress_head = (cur_state == FETCH_CXT_s) ? {qpn_data[`QP_NUM_LOG - 1 : 0], `CXT_READ, ingress_common_head} : 'd0; +assign fetch_cxt_ingress_data = (cur_state == FETCH_CXT_s) ? sub_wqe_meta_diff : 'd0; +assign fetch_cxt_ingress_start = (cur_state == FETCH_CXT_s) ? 'd1 : 'd0; +assign fetch_cxt_ingress_last = (cur_state == FETCH_CXT_s) ? 'd1 : 'd0; + +//-- sub_wqe_ready -- +assign sub_wqe_ready = (cur_state == IDLE_s) ? 'd1 : 'd0; +/*------------------------------------------- Variables Decode : End ----------------------------------------------*/ + +/*------------------------------------------- Local Macros Undef : Begin --------------------------------------------*/ + +/*------------------------------------------- Local Macros Undef : End ----------------------------------------------*/ + +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/RPCSubsystem/RDMACore/RequesterCore/ReqTransCore/ReqTransCore_Thread_2.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/RPCSubsystem/RDMACore/RequesterCore/ReqTransCore/ReqTransCore_Thread_2.v new file mode 100644 index 0000000000000000000000000000000000000000..75405c2eced0b730c96eb9445f586806a98ff96a --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/RPCSubsystem/RDMACore/RequesterCore/ReqTransCore/ReqTransCore_Thread_2.v @@ -0,0 +1,593 @@ +/*------------------------------------------- Module Description : Begin ---------------------------------------------- +Name: ReqTransCore_Thread_2 +Author: YangFan +Function: 1.Parse Sub-WQE and generate MR request. +--------------------------------------------- Module Decription : End -----------------------------------------------*/ + +/*------------------------------------------- Timescale Definition : Begin ------------------------------------------*/ +`timescale 1ns / 1ps +/*------------------------------------------- Timescale Definition : End --------------------------------------------*/ + +/*------------------------------------------- Included Files : Begin ------------------------------------------------*/ +`include "protocol_engine_def.vh" +/*------------------------------------------- Included Files : End --------------------------------------------------*/ + +/*------------------------------------------- Input/Output Definition : Begin ---------------------------------------*/ +module ReqTransCore_Thread_2 +#( + parameter EGRESS_CXT_HEAD_WIDTH = 128, + parameter EGRESS_CXT_DATA_WIDTH = 256, + + + parameter INGRESS_MR_HEAD_WIDTH = 128, + parameter INGRESS_MR_DATA_WIDTH = 256 +) +( + input wire clk, + input wire rst, + +//Interface with OoOStation(For CxtMgt) + input wire fetch_cxt_egress_valid, + input wire [`TX_REQ_OOO_CXT_EGRESS_HEAD_WIDTH - 1 : 0] fetch_cxt_egress_head, + input wire [`TX_REQ_OOO_CXT_EGRESS_DATA_WIDTH - 1 : 0] fetch_cxt_egress_data, + input wire fetch_cxt_egress_start, + input wire fetch_cxt_egress_last, + output wire fetch_cxt_egress_ready, + +//Interface with OoOStation(For MRMgt) + output wire fetch_mr_ingress_valid, + output wire [`TX_REQ_OOO_MR_INGRESS_HEAD_WIDTH - 1 : 0] fetch_mr_ingress_head, + output wire [`TX_REQ_OOO_MR_INGRESS_DATA_WIDTH - 1 : 0] fetch_mr_ingress_data, + output wire fetch_mr_ingress_start, + output wire fetch_mr_ingress_last, + input wire fetch_mr_ingress_ready, + +//Interface with CompletionQueueMgt + output wire cq_req_valid, + output wire [`CQ_REQ_HEAD_WIDTH - 1 : 0] cq_req_head, + input wire cq_req_ready, + + input wire cq_resp_valid, + input wire [`CQ_RESP_HEAD_WIDTH - 1 : 0] cq_resp_head, + output wire cq_resp_ready, + +//Interface with EventQueueMgt + output wire eq_req_valid, + output wire [`EQ_REQ_HEAD_WIDTH - 1 : 0] eq_req_head, + input wire eq_req_ready, + + input wire eq_resp_valid, + input wire [`EQ_RESP_HEAD_WIDTH - 1 : 0] eq_resp_head, + output wire eq_resp_ready +); +/*------------------------------------------- Input/Output Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Macros Definition : Begin ---------------------------------------*/ +`define SUB_WQE_LOCAL_QPN_OFFSET 23:0 +`define SUB_WQE_VERBS_OPCODE_OFFSET 28:24 +`define SUB_WQE_REMOTE_QPN_OFFSET 55:32 +`define SUB_WQE_NET_OPCODE_OFFSET 60:56 +`define SUB_WQE_SERVICE_TYPE_OFFSET 63:61 +`define SUB_WQE_FENCE_OFFSET 64 +`define SUB_WQE_SOLICITED_EVENT_OFFSET 65 +`define SUB_WQE_HEAD_OFFSET 66 +`define SUB_WQE_TAIL_OFFSET 67 +`define SUB_WQE_INLINE_OFFSET 68 +`define SUB_WQE_WQE_OFFSET 95:72 +`define SUB_WQE_DMAC_OFFSET 143:96 +`define SUB_WQE_SMAC_OFFSET 191:144 +`define SUB_WQE_DIP_OFFSET 223:192 +`define SUB_WQE_SIP_OFFSET 255:224 +`define SUB_WQE_IMMEDIATE_OFFSET 287:256 +`define SUB_WQE_LKEY_OFFSET 319:288 +`define SUB_WQE_LADDR_OFFSET 383:320 +`define SUB_WQE_RKEY_OFFSET 415:384 +`define SUB_WQE_RADDR_OFFSET 479:416 +`define SUB_WQE_MSG_LENGTH_OFFSET 511:480 +`define SUB_WQE_PKT_LENGTH_OFFSET 527:512 +`define SUB_WQE_PAYLOAD_BUFFER_ADDR_OFFSET 575:544 +/*------------------------------------------- Local Macros Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Variables Definition : Begin ------------------------------------*/ +reg [`QP_CONTEXT_BIT_SIZE + `CQ_CONTEXT_BIT_SIZE + `EQ_CONTEXT_BIT_SIZE - 1 : 0] cxt_bus; +reg [`WQE_META_WIDTH - 1 : 0] wqe_bus; + +wire [`INGRESS_COMMON_HEAD_WIDTH - 1 : 0] ingress_common_head; +wire [`MAX_OOO_SLOT_NUM_LOG - 1 :0] ingress_slot_count; + +wire [23:0] SubWQE_local_qpn; +wire [4:0] SubWQE_verbs_opcode; +wire [23:0] SubWQE_remote_qpn; +wire [4:0] SubWQE_net_opcode; +wire [2:0] SubWQE_service_type; +wire [0:0] SubWQE_fence; +wire [0:0] SubWQE_solicted_event; +wire [0:0] SubWQE_wqe_head; +wire [0:0] SubWQE_wqe_tail; +wire [0:0] SubWQE_inline; +wire [23:0] SubWQE_ori_wqe_offset; +wire [47:0] SubWQE_dmac; +wire [47:0] SubWQE_smac; +wire [31:0] SubWQE_dip; +wire [31:0] SubWQE_sip; +wire [31:0] SubWQE_immediate; +wire [31:0] SubWQE_lkey; +wire [63:0] SubWQE_laddr; +wire [31:0] SubWQE_rkey; +wire [63:0] SubWQE_raddr; +wire [31:0] SubWQE_msg_length; +wire [15:0] SubWQE_packet_length; +wire [31:0] SubWQE_payload_buffer_addr; + +reg [0:0] need_cpl; +reg [0:0] need_event; + +wire [0:0] is_inline; +wire [0:0] is_rdma_read; + +wire [31:0] mr_length; +wire [63:0] mr_laddr; +wire [31:0] mr_lkey; +wire [31:0] mr_pd; + +wire [31:0] mr_flags; +reg [3:0] mr_flag_sw_owns; +reg mr_flag_absolute_addr; +reg mr_flag_relative_addr; +reg mr_flag_mio; +reg mr_flag_bind_enable; +reg mr_flag_physical; +reg mr_flag_region; +reg mr_flag_on_demand; +reg mr_flag_zero_based; +reg mr_flag_mw_bind; +reg mr_flag_remote_read; +reg mr_flag_remote_write; +reg mr_flag_local_write; +/*------------------------------------------- Local Variables Definition : End --------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : Begin ---------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : End -----------------------------------------*/ + +/*------------------------------------------- State Machine Definition : Begin --------------------------------------*/ +reg [3:0] cur_state; +reg [3:0] next_state; + +parameter [3:0] IDLE_s = 4'd1, + JUDGE_s = 4'd2, + BYPASS_s = 4'd3, + FETCH_DATA_MR_s = 4'd4, + CQ_REQ_s = 4'd5, + CQ_RESP_s = 4'd6, + FETCH_CQ_MR_s = 4'd7, + FETCH_EQ_MR_s = 4'd8, + EQ_REQ_s = 4'd9, + EQ_RESP_s = 4'd10; + +always @(posedge clk or posedge rst) begin + if(rst) begin + cur_state <= IDLE_s; + end + else begin + cur_state <= next_state; + end +end + +always @(*) begin + case(cur_state) + IDLE_s: if(fetch_cxt_egress_start) begin + next_state = JUDGE_s; + end + else begin + next_state = IDLE_s; + end + JUDGE_s: if(is_inline || is_rdma_read) begin //No need to fetch data mr + next_state = BYPASS_s; + end + else begin + next_state = FETCH_DATA_MR_s; + end + BYPASS_s: if(fetch_mr_ingress_valid && fetch_mr_ingress_ready) begin + if(is_rdma_read) begin + next_state = IDLE_s; + end + else if(is_inline) begin + next_state = CQ_REQ_s; + end + else begin + next_state = IDLE_s; + end + end + else begin + next_state = BYPASS_s; + end + FETCH_DATA_MR_s: if(fetch_mr_ingress_valid && fetch_mr_ingress_ready) begin + if(need_cpl) begin + next_state = CQ_REQ_s; + end + else begin + next_state = IDLE_s; + end + end + else begin + next_state = FETCH_DATA_MR_s; + end + CQ_REQ_s: if(cq_req_valid && cq_req_ready) begin + next_state = CQ_RESP_s; + end + else begin + next_state = CQ_REQ_s; + end + CQ_RESP_s: if(cq_resp_valid && cq_resp_ready) begin + next_state = FETCH_CQ_MR_s; + end + else begin + next_state = CQ_RESP_s; + end + FETCH_CQ_MR_s: if(fetch_mr_ingress_valid && fetch_mr_ingress_ready) begin + if(need_event) begin + next_state = EQ_REQ_s; + end + else begin + next_state = IDLE_s; + end + end + else begin + next_state = FETCH_CQ_MR_s; + end + EQ_REQ_s: if(eq_req_valid && eq_req_ready) begin + next_state = EQ_RESP_s; + end + else begin + next_state = EQ_REQ_s; + end + EQ_RESP_s: if(eq_resp_valid && eq_resp_ready) begin + next_state = FETCH_EQ_MR_s; + end + else begin + next_state = EQ_RESP_s; + end + FETCH_EQ_MR_s: if(fetch_mr_ingress_valid && fetch_mr_ingress_ready) begin + next_state = IDLE_s; + end + else begin + next_state = FETCH_EQ_MR_s; + end + default: next_state = IDLE_s; + endcase +end +/*------------------------------------------- State Machine Definition : End ----------------------------------------*/ + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ +//-- cxt_bus -- +//-- wqe_bus -- +always @(posedge clk or posedge rst) begin + if(rst) begin + cxt_bus <= 'd0; + wqe_bus <= 'd0; + end + else if(cur_state == IDLE_s && fetch_cxt_egress_valid) begin + cxt_bus <= fetch_cxt_egress_head[`QP_CONTEXT_BIT_SIZE + `CQ_CONTEXT_BIT_SIZE + `EQ_CONTEXT_BIT_SIZE + `INGRESS_COMMON_HEAD_WIDTH - 1 : `EGRESS_COMMON_HEAD_WIDTH]; + wqe_bus <= fetch_cxt_egress_data; + end + else begin + cxt_bus <= cxt_bus; + wqe_bus <= wqe_bus; + end +end + +//-- SubWQE_local_qpn -- +//-- SubWQE_remote_qpn -- +//-- SubWQE_verbs_opcode -- +//-- SubWQE_net_opcode -- +//-- SubWQE_service_type -- +//-- SubWQE_fence -- +//-- SubWQE_solicted_event -- +//-- SubWQE_wqe_head -- +//-- SubWQE_wqe_tail -- +//-- SubWQE_inline -- +//-- SubWQE_ori_wqe_offset -- +//-- SubWQE_dmac -- +//-- SubWQE_smac -- +//-- SubWQE_dip -- +//-- SubWQE_sip -- +//-- SubWQE_immediate -- +//-- SubWQE_lkey -- +//-- SubWQE_laddr -- +//-- SubWQE_rkey -- +//-- SubWQE_raddr -- +//-- SubWQE_msg_length -- +//-- SubWQE_packet_length -- +//-- SubWQE_payload_buffer_addr -- +assign SubWQE_local_qpn = wqe_bus[`SUB_WQE_LOCAL_QPN_OFFSET]; +assign SubWQE_verbs_opcode = wqe_bus[`SUB_WQE_VERBS_OPCODE_OFFSET]; +assign SubWQE_remote_qpn = wqe_bus[`SUB_WQE_REMOTE_QPN_OFFSET]; +assign SubWQE_net_opcode = wqe_bus[`SUB_WQE_NET_OPCODE_OFFSET]; +assign SubWQE_service_type = wqe_bus[`SUB_WQE_SERVICE_TYPE_OFFSET]; +assign SubWQE_fence = wqe_bus[`SUB_WQE_FENCE_OFFSET]; +assign SubWQE_solicted_event = wqe_bus[`SUB_WQE_SOLICITED_EVENT_OFFSET]; +assign SubWQE_wqe_head = wqe_bus[`SUB_WQE_HEAD_OFFSET]; +assign SubWQE_wqe_tail = wqe_bus[`SUB_WQE_TAIL_OFFSET]; +assign SubWQE_inline = wqe_bus[`SUB_WQE_INLINE_OFFSET]; +assign SubWQE_ori_wqe_offset = wqe_bus[`SUB_WQE_WQE_OFFSET]; +assign SubWQE_dmac = wqe_bus[`SUB_WQE_DMAC_OFFSET]; +assign SubWQE_smac = wqe_bus[`SUB_WQE_SMAC_OFFSET]; +assign SubWQE_dip = wqe_bus[`SUB_WQE_DIP_OFFSET]; +assign SubWQE_sip = wqe_bus[`SUB_WQE_SIP_OFFSET]; +assign SubWQE_immediate = wqe_bus[`SUB_WQE_IMMEDIATE_OFFSET]; +assign SubWQE_lkey = wqe_bus[`SUB_WQE_LKEY_OFFSET]; +assign SubWQE_laddr = wqe_bus[`SUB_WQE_LADDR_OFFSET]; +assign SubWQE_rkey = wqe_bus[`SUB_WQE_RKEY_OFFSET]; +assign SubWQE_raddr = wqe_bus[`SUB_WQE_RADDR_OFFSET]; +assign SubWQE_msg_length = wqe_bus[`SUB_WQE_MSG_LENGTH_OFFSET]; +assign SubWQE_packet_length = wqe_bus[`SUB_WQE_PKT_LENGTH_OFFSET]; +assign SubWQE_payload_buffer_addr = wqe_bus[`SUB_WQE_PAYLOAD_BUFFER_ADDR_OFFSET]; + +//-- is_inline -- +assign is_inline = SubWQE_inline; + +//-- is_rdma_read -- +assign is_rdma_read = (SubWQE_net_opcode == `RDMA_READ_REQUEST_FIRST || SubWQE_net_opcode == `RDMA_READ_REQUEST_MIDDLE || + SubWQE_net_opcode == `RDMA_READ_REQUEST_LAST || SubWQE_net_opcode == `RDMA_READ_REQUEST_ONLY); + +//-- need_cpl -- +always @(posedge clk or posedge rst) begin + if(rst) begin + need_cpl <= 'd0; + end + else if(cur_state == IDLE_s && !fetch_cxt_egress_valid) begin + need_cpl <= 'd0; + end + else if(cur_state == IDLE_s && fetch_cxt_egress_valid) begin + need_cpl <= ( SubWQE_service_type == `UC || SubWQE_service_type == `UD) && + ( SubWQE_net_opcode == `SEND_LAST || SubWQE_net_opcode == `SEND_LAST_WITH_IMM || SubWQE_net_opcode == `SEND_ONLY || SubWQE_net_opcode == `SEND_ONLY_WITH_IMM || + SubWQE_net_opcode == `RDMA_WRITE_LAST || SubWQE_net_opcode == `RDMA_WRITE_LAST_WITH_IMM || SubWQE_net_opcode == `RDMA_WRITE_ONLY || SubWQE_net_opcode == `RDMA_WRITE_ONLY_WITH_IMM); + end + else begin + need_cpl <= need_cpl; + end +end + +//-- need_event -- +always @(posedge clk or posedge rst) begin + if(rst) begin + need_event <= 'd0; + end + else if(cur_state == IDLE_s && fetch_cxt_egress_valid) begin //TODO, generate Event. + need_event <= 'd0; + end + else begin + need_event <= need_event; + end +end + +//-- fetch_cxt_egress_ready -- +assign fetch_cxt_egress_ready = (cur_state == IDLE_s) ? 'd1 : 'd0; + +//-- fetch_mr_ingress_valid -- +assign fetch_mr_ingress_valid = (cur_state == BYPASS_s) ? 'd1 : + (cur_state == FETCH_DATA_MR_s) ? 'd1 : + (cur_state == FETCH_CQ_MR_s) ? 'd1 : + (cur_state == FETCH_EQ_MR_s) ? 'd1 : 'd0; + +wire [`MAX_QP_NUM_LOG - 1 : 0] queue_index; +assign queue_index = {'d0, SubWQE_local_qpn[`QP_NUM_LOG - 1 : 0]}; + +//-- ingress_slot_count -- +//-- ingress_common_head -- +assign ingress_slot_count = (cur_state == BYPASS_s) ? 'd1 : + (cur_state == FETCH_DATA_MR_s) ? 'd1 : + (cur_state == FETCH_CQ_MR_s) ? 'd1 : + (cur_state == FETCH_EQ_MR_s) ? 'd1 : 'd0; + +assign ingress_common_head = (cur_state == BYPASS_s) ? {`BYPASS_MODE, ingress_slot_count, queue_index} : //inline or rdma_read does not need MT translation + (cur_state == FETCH_DATA_MR_s) ? {`NO_BYPASS, ingress_slot_count, queue_index} : + (cur_state == FETCH_CQ_MR_s) ? {`NO_BYPASS, ingress_slot_count, queue_index} : + (cur_state == FETCH_EQ_MR_s) ? {`NO_BYPASS, ingress_slot_count, queue_index} : 'd0; + + + +//-- fetch_mr_ingress_head -- +assign fetch_mr_ingress_head = (cur_state == BYPASS_s) ? {'d0, ingress_common_head} : + (cur_state == FETCH_DATA_MR_s) ? {mr_length, mr_laddr, mr_lkey, mr_pd, mr_flags, ingress_common_head} : + (cur_state == FETCH_CQ_MR_s) ? {mr_length, mr_laddr, mr_lkey, mr_pd, mr_flags, ingress_common_head} : + (cur_state == FETCH_EQ_MR_s) ? {mr_length, mr_laddr, mr_lkey, mr_pd, mr_flags, ingress_common_head} : 'd0; + + +//-- fetch_mr_ingress_data -- +assign fetch_mr_ingress_data = {SubWQE_payload_buffer_addr, 16'd0, SubWQE_packet_length, SubWQE_msg_length, + SubWQE_raddr, SubWQE_rkey, SubWQE_laddr, SubWQE_lkey, SubWQE_immediate, + SubWQE_sip, SubWQE_dip, SubWQE_smac, SubWQE_dmac, SubWQE_ori_wqe_offset, 3'd0, SubWQE_inline, + SubWQE_wqe_tail, SubWQE_wqe_head, 1'b0, SubWQE_fence, SubWQE_service_type, + ( cur_state == BYPASS_s ? SubWQE_net_opcode : + cur_state == FETCH_DATA_MR_s ? SubWQE_net_opcode : + cur_state == FETCH_CQ_MR_s ? `GEN_CQE : + cur_state == FETCH_EQ_MR_s ? `GEN_EVENT : 5'd0), + SubWQE_remote_qpn, 3'd0, SubWQE_verbs_opcode, SubWQE_local_qpn}; + +//-- fetch_mr_ingress_start -- +assign fetch_mr_ingress_start = (cur_state == BYPASS_s) ? 'd1 : + (cur_state == FETCH_DATA_MR_s) ? 'd1 : + (cur_state == FETCH_CQ_MR_s) ? 'd1 : + (cur_state == FETCH_EQ_MR_s) ? 'd1 : 'd0; + +//-- fetch_mr_ingress_last -- +assign fetch_mr_ingress_last = (cur_state == BYPASS_s) ? 'd1 : + (cur_state == FETCH_DATA_MR_s) ? 'd1 : + (cur_state == FETCH_CQ_MR_s) ? 'd1 : + (cur_state == FETCH_EQ_MR_s) ? 'd1 : 'd0; + +//-- cq_req_valid -- +//-- cq_req_head -- +assign cq_req_valid = (cur_state == CQ_REQ_s) ? 'd1 : 'd0; +assign cq_req_head = (cur_state == CQ_REQ_s) ? {`CQE_LENGTH * (1 << cxt_bus[`CQ_CXT_LOG_SIZE_OFFSET]), 8'd0, cxt_bus[`QP_CXT_CQN_SND_OFFSET]} : 'd0; + +//-- eq_req_valid -- +//-- eq_req_head -- +assign eq_req_valid = (cur_state == EQ_REQ_s) ? 'd1 : 'd0; +assign eq_req_head = (cur_state == EQ_REQ_s) ? {`EVENT_LENGTH * (1 << cxt_bus[`EQ_CXT_LOG_SIZE_OFFSET]), 8'd0, cxt_bus[`CQ_CXT_COMP_EQN_OFFSET]} : 'd0; + +/********************************************************* MR Request Decode : Begin ***********************************************************/ +//-- mr_length -- +assign mr_length = (cur_state == FETCH_DATA_MR_s) ? SubWQE_packet_length : + (cur_state == FETCH_CQ_MR_s) ? `CQE_LENGTH : + (cur_state == FETCH_EQ_MR_s) ? `EVENT_LENGTH : 'd0; + +//-- mr_laddr -- +assign mr_laddr = (cur_state == FETCH_DATA_MR_s) ? SubWQE_laddr : + (cur_state == FETCH_CQ_MR_s) ? cq_resp_head[`CQ_LADDR_OFFSET] : + (cur_state == FETCH_EQ_MR_s) ? eq_resp_head[`EQ_LADDR_OFFSET] : 'd0; + +//-- mr_lkey -- +assign mr_lkey = (cur_state == FETCH_DATA_MR_s) ? SubWQE_lkey : + (cur_state == FETCH_CQ_MR_s) ? cxt_bus[`CQ_CXT_LKEY_OFFSET] : + (cur_state == FETCH_EQ_MR_s) ? cxt_bus[`EQ_CXT_LKEY_OFFSET] : 'd0; + +//-- mr_pd -- +assign mr_pd = (cur_state == FETCH_DATA_MR_s) ? cxt_bus[`QP_CXT_PD_OFFSET] : + (cur_state == FETCH_CQ_MR_s) ? cxt_bus[`CQ_CXT_PD_OFFSET] : + (cur_state == FETCH_EQ_MR_s) ? cxt_bus[`EQ_CXT_PD_OFFSET] : 'd0; + +//-- mr_flag_sw_owns -- +//-- mr_flag_absolute_addr -- +//-- mr_flag_relative_addr -- +//-- mr_flag_mio -- +//-- mr_flag_bind_enable -- +//-- mr_flag_physical -- +//-- mr_flag_on_demand -- +//-- mr_flag_zero_based -- +//-- mr_flag_mw_bind -- +//-- mr_remote_read -- +//-- mr_remote_write -- +//-- mr_local_write -- +always @(*) begin + if(rst) begin + mr_flag_sw_owns = 'd0; + mr_flag_absolute_addr = 'd0; + mr_flag_relative_addr = 'd0; + mr_flag_mio = 'd0; + mr_flag_bind_enable = 'd0; + mr_flag_physical = 'd0; + mr_flag_region = 'd0; + mr_flag_on_demand = 'd0; + mr_flag_zero_based = 'd0; + mr_flag_mw_bind = 'd0; + mr_flag_remote_read = 'd0; + mr_flag_remote_write = 'd0; + mr_flag_local_write = 'd0; + end + else if(cur_state == FETCH_DATA_MR_s) begin + mr_flag_sw_owns = 'd0; + mr_flag_absolute_addr = 'd1; + mr_flag_relative_addr = 'd0; + mr_flag_mio = 'd0; + mr_flag_bind_enable = 'd0; + mr_flag_physical = 'd0; + mr_flag_region = 'd0; + mr_flag_on_demand = 'd0; + mr_flag_zero_based = 'd0; + mr_flag_mw_bind = 'd0; + mr_flag_remote_read = 'd0; + mr_flag_remote_write = 'd0; + mr_flag_local_write = 'd0; + end + else if(cur_state == FETCH_CQ_MR_s) begin + mr_flag_sw_owns = 'd0; + mr_flag_absolute_addr = 'd0; + mr_flag_relative_addr = 'd1; + mr_flag_mio = 'd0; + mr_flag_bind_enable = 'd0; + mr_flag_physical = 'd0; + mr_flag_region = 'd0; + mr_flag_on_demand = 'd0; + mr_flag_zero_based = 'd0; + mr_flag_mw_bind = 'd0; + mr_flag_remote_read = 'd0; + mr_flag_remote_write = 'd0; + mr_flag_local_write = 'd1; + end + else if(cur_state == FETCH_EQ_MR_s) begin + mr_flag_sw_owns = 'd0; + mr_flag_absolute_addr = 'd0; + mr_flag_relative_addr = 'd1; + mr_flag_mio = 'd0; + mr_flag_bind_enable = 'd0; + mr_flag_physical = 'd0; + mr_flag_region = 'd0; + mr_flag_on_demand = 'd0; + mr_flag_zero_based = 'd0; + mr_flag_mw_bind = 'd0; + mr_flag_remote_read = 'd0; + mr_flag_remote_write = 'd0; + mr_flag_local_write = 'd1; + end + else begin + mr_flag_sw_owns = 'd0; + mr_flag_absolute_addr = 'd0; + mr_flag_relative_addr = 'd1; + mr_flag_mio = 'd0; + mr_flag_bind_enable = 'd0; + mr_flag_physical = 'd0; + mr_flag_region = 'd0; + mr_flag_on_demand = 'd0; + mr_flag_zero_based = 'd0; + mr_flag_mw_bind = 'd0; + mr_flag_remote_read = 'd0; + mr_flag_remote_write = 'd0; + mr_flag_local_write = 'd0; + end +end + +//-- mr_flags -- +assign mr_flags = (cur_state == FETCH_DATA_MR_s || cur_state == FETCH_CQ_MR_s || cur_state == FETCH_EQ_MR_s) ? + { + mr_flag_sw_owns, + mr_flag_absolute_addr, + mr_flag_relative_addr, + 8'd0, + mr_flag_mio, + 1'd0, + mr_flag_bind_enable, + 5'd0, + mr_flag_physical, + mr_flag_region, + 1'd0, + mr_flag_on_demand, + mr_flag_zero_based, + mr_flag_mw_bind, + mr_flag_remote_read, + mr_flag_remote_write, + mr_flag_local_write + } : 'd0; +/********************************************************* MR Request Decode : End *************************************************************/ + +/*------------------------------------------- Variables Decode : End ----------------------------------------------*/ + +/*------------------------------------------- Local Macros Undef : Begin --------------------------------------------*/ +`undef SUB_WQE_LOCAL_QPN_OFFSET +`undef SUB_WQE_VERBS_OPCODE_OFFSET +`undef SUB_WQE_REMOTE_QPN_OFFSET +`undef SUB_WQE_NET_OPCODE_OFFSET +`undef SUB_WQE_SERVICE_TYPE_OFFSET +`undef SUB_WQE_FENCE_OFFSET +`undef SUB_WQE_SOLICITED_EVENT_OFFSET +`undef SUB_WQE_HEAD_OFFSET +`undef SUB_WQE_TAIL_OFFSET +`undef SUB_WQE_INLINE_OFFSET +`undef SUB_WQE_WQE_OFFSET +`undef SUB_WQE_DMAC_OFFSET +`undef SUB_WQE_SMAC_OFFSET +`undef SUB_WQE_DIP_OFFSET +`undef SUB_WQE_SIP_OFFSET +`undef SUB_WQE_IMMEDIATE_OFFSET +`undef SUB_WQE_LKEY_OFFSET +`undef SUB_WQE_LADDR_OFFSET +`undef SUB_WQE_RKEY_OFFSET +`undef SUB_WQE_RADDR_OFFSET +`undef SUB_WQE_MSG_LENGTH_OFFSET +`undef SUB_WQE_PKT_LENGTH_OFFSET +`undef SUB_WQE_PAYLOAD_BUFFER_ADDR_OFFSET +/*------------------------------------------- Local Macros Undef : End ----------------------------------------------*/ + +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/RPCSubsystem/RDMACore/RequesterCore/ReqTransCore/ReqTransCore_Thread_3.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/RPCSubsystem/RDMACore/RequesterCore/ReqTransCore/ReqTransCore_Thread_3.v new file mode 100644 index 0000000000000000000000000000000000000000..775f5817c3a03d6ccfe21bb8f6159337564724a5 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/RPCSubsystem/RDMACore/RequesterCore/ReqTransCore/ReqTransCore_Thread_3.v @@ -0,0 +1,243 @@ +/*------------------------------------------- Module Description : Begin ---------------------------------------------- +Name: ReqTransCore_Thread_3 +Author: YangFan +Function: 1.Generate DMA Read Request (Read payload from memory). +--------------------------------------------- Module Decription : End -----------------------------------------------*/ + +/*------------------------------------------- Timescale Definition : Begin ------------------------------------------*/ +`timescale 1ns / 1ps +/*------------------------------------------- Timescale Definition : End --------------------------------------------*/ + +/*------------------------------------------- Included Files : Begin ------------------------------------------------*/ +`include "protocol_engine_def.vh" +/*------------------------------------------- Included Files : End --------------------------------------------------*/ + +/*------------------------------------------- Input/Output Definition : Begin ---------------------------------------*/ +module ReqTransCore_Thread_3 +#( + parameter EGRESS_MR_HEAD_WIDTH = 128, + parameter EGRESS_MR_DATA_WIDTH = 256 +) +( + input wire clk, + input wire rst, + +//Interface with OoOStation(For MRMgt) + input wire fetch_mr_egress_valid, + input wire [`TX_REQ_OOO_MR_EGRESS_HEAD_WIDTH - 1 : 0] fetch_mr_egress_head, + input wire [`TX_REQ_OOO_MR_EGRESS_DATA_WIDTH - 1 : 0] fetch_mr_egress_data, + input wire fetch_mr_egress_start, + input wire fetch_mr_egress_last, + output wire fetch_mr_egress_ready, + +//Interface with ReqTransCore_Thread_4 + output wire net_req_wen, + output wire [`WQE_META_WIDTH - 1 : 0] net_req_din, + input wire net_req_prog_full, + +//DMA Read Interface + output reg gather_req_wr_en, + output reg [`DMA_LENGTH_WIDTH * 2 + `DMA_ADDR_WIDTH - 1 : 0] gather_req_din, + input wire gather_req_prog_full +); +/*------------------------------------------- Input/Output Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Macros Definition : Begin ---------------------------------------*/ +`define SUB_WQE_NET_OPCODE_OFFSET 60:56 +`define SUB_WQE_INLINE_OFFSET 68 +`define SUB_WQE_PACKET_LENGTH_OFFSET 527:512 +/*------------------------------------------- Local Macros Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Variables Definition : Begin ------------------------------------*/ +reg [`MR_RESP_WIDTH - 1 : 0] mr_resp_bus; +reg [`WQE_META_WIDTH - 1 : 0] wqe_bus; + +wire [4:0] SubWQE_net_opcode; +wire [0:0] SubWQE_inline; +wire [15:0] SubWQE_packet_length; + +wire [0:0] no_gather; + +reg [1:0] data_piece_left; +reg [1:0] data_piece_total; + +wire [3:0] mr_resp_state; +wire [3:0] mr_resp_valid_0; +wire [3:0] mr_resp_valid_1; +wire [31:0] mr_resp_size_0; +wire [31:0] mr_resp_size_1; +wire [63:0] mr_resp_phy_addr_0; +wire [63:0] mr_resp_phy_addr_1; +/*------------------------------------------- Local Variables Definition : End --------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : Begin ---------------------------------------*/ +/*------------------------------------------- Submodules Instatiation : End -----------------------------------------*/ + +/*------------------------------------------- State Machine Definition : Begin --------------------------------------*/ +reg [2:0] cur_state; +reg [2:0] next_state; + +parameter [2:0] IDLE_s = 3'd1, + JUDGE_s = 3'd2, + GATHER_s = 3'd3, + FWD_s = 3'd4; + +always @(posedge clk or posedge rst) begin + if(rst) begin + cur_state <= IDLE_s; + end + else begin + cur_state <= next_state; + end +end + +always @(*) begin + case(cur_state) + IDLE_s: if(fetch_mr_egress_valid) begin + next_state = JUDGE_s; + end + else begin + next_state = IDLE_s; + end + JUDGE_s: if(no_gather) begin + next_state = FWD_s; + end + else begin + next_state = GATHER_s; + end + GATHER_s: if(data_piece_left == 'd1 && !gather_req_prog_full) begin + next_state = FWD_s; + end + else begin + next_state = GATHER_s; + end + FWD_s: if(!net_req_prog_full) begin + next_state = IDLE_s; + end + else begin + next_state = FWD_s; + end + default: next_state = IDLE_s; + endcase +end +/*------------------------------------------- State Machine Definition : End ----------------------------------------*/ + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ +//-- wqe_bus -- +always @(posedge clk or posedge rst) begin + if (rst) begin + wqe_bus <= 'd0; + mr_resp_bus <= 'd0; + end + else if (cur_state == IDLE_s && fetch_mr_egress_valid) begin + wqe_bus <= fetch_mr_egress_data; + mr_resp_bus <= fetch_mr_egress_head[`MR_RESP_WIDTH + `EGRESS_COMMON_HEAD_WIDTH - 1 : `EGRESS_COMMON_HEAD_WIDTH]; + end + else begin + wqe_bus <= wqe_bus; + mr_resp_bus <= mr_resp_bus; + end +end + +//-- SubWQE_net_opcode -- +//-- SubWQE_inline -- +//-- SubWQE_packet_length -- +assign SubWQE_net_opcode = wqe_bus[`SUB_WQE_NET_OPCODE_OFFSET]; +assign SubWQE_inline = wqe_bus[`SUB_WQE_INLINE_OFFSET]; +assign SubWQE_packet_length = wqe_bus[`SUB_WQE_PACKET_LENGTH_OFFSET]; + +//-- no_gather -- +assign no_gather = (SubWQE_inline || (SubWQE_net_opcode == `RDMA_READ_REQUEST_FIRST || SubWQE_net_opcode == `RDMA_READ_REQUEST_MIDDLE || + SubWQE_net_opcode == `RDMA_READ_REQUEST_LAST || SubWQE_net_opcode == `RDMA_READ_REQUEST_ONLY || + SubWQE_net_opcode == `GEN_CQE || SubWQE_net_opcode == `GEN_EVENT)); + +//-- mr_resp_state -- +//-- mr_resp_valid_0 -- +//-- mr_resp_valid_1 -- +//-- mr_resp_size_0 -- +//-- mr_resp_size_1 -- +//-- mr_resp_phy_addr_0 -- +//-- mr_resp_phy_addr_1 -- +assign mr_resp_state = mr_resp_bus[`MR_RESP_STATE_OFFSET]; +assign mr_resp_valid_0 = mr_resp_bus[`MR_RESP_VALID_0_OFFSET]; +assign mr_resp_valid_1 = mr_resp_bus[`MR_RESP_VALID_1_OFFSET]; +assign mr_resp_size_0 = mr_resp_bus[`MR_RESP_SIZE_0_OFFSET]; +assign mr_resp_size_1 = mr_resp_bus[`MR_RESP_SIZE_1_OFFSET]; +assign mr_resp_phy_addr_0 = mr_resp_bus[`MR_RESP_ADDR_0_OFFSET]; +assign mr_resp_phy_addr_1 = mr_resp_bus[`MR_RESP_ADDR_1_OFFSET]; + +//-- data_piece_left -- +always @(posedge clk or posedge rst) begin + if(rst) begin + data_piece_left <= 'd0; + end + else if(cur_state == IDLE_s) begin + data_piece_left <= data_piece_left; + end + else if(cur_state == JUDGE_s) begin + data_piece_left <= mr_resp_valid_1 ? 'd2 : 'd1; + end + else if(cur_state == GATHER_s && !gather_req_prog_full) begin + data_piece_left <= data_piece_left - 'd1; + end + else begin + data_piece_left <= data_piece_left; + end +end + +//-- data_piece_total -- +always @(posedge clk or posedge rst) begin + if (rst) begin + data_piece_total <= 'd0; + end + else if (cur_state == IDLE_s) begin + data_piece_total <= data_piece_total; + end + else if(cur_state == JUDGE_s) begin + data_piece_total <= mr_resp_valid_1 ? 'd2 : 'd1; + end + else begin + data_piece_total <= data_piece_total; + end +end + +//-- fetch_mr_egress_ready -- +assign fetch_mr_egress_ready = (cur_state == IDLE_s) ? 'd1 : 'd0; + +//-- net_req_wen -- +//-- net_req_din -- +assign net_req_wen = (cur_state == FWD_s && !net_req_prog_full) ? 'd1 : 'd0; +assign net_req_din = (cur_state == FWD_s && (SubWQE_net_opcode != `GEN_CQE && SubWQE_net_opcode != `GEN_EVENT)) ? wqe_bus : + (cur_state == FWD_s && (SubWQE_net_opcode == `GEN_CQE || SubWQE_net_opcode == `GEN_EVENT)) ? {wqe_bus[575:384], 64'd0, mr_resp_phy_addr_0, wqe_bus[255:0]} : 'd0; + +//-- gather_req_wr_en -- +//-- gather_req_din -- +always @(posedge clk or posedge rst) begin + if(rst) begin + gather_req_wr_en <= 'd0; + gather_req_din <= 'd0; + end + else if(cur_state == GATHER_s && !gather_req_prog_full) begin + if(data_piece_total == 'd2) begin + gather_req_wr_en <= 'd1; + gather_req_din <= (data_piece_left == 'd2) ? {SubWQE_packet_length, mr_resp_size_0, mr_resp_phy_addr_0} : {SubWQE_packet_length, mr_resp_size_1, mr_resp_phy_addr_1}; + end + else begin + gather_req_wr_en <= 'd1; + gather_req_din <= {SubWQE_packet_length, mr_resp_size_0, mr_resp_phy_addr_0}; + end + end + else begin + gather_req_wr_en <= 'd0; + gather_req_din <= 'd0; + end +end +/*------------------------------------------- Variables Decode : End ----------------------------------------------*/ + +/*------------------------------------------- Local Macros Undef : Begin --------------------------------------------*/ +`undef SUB_WQE_NET_OPCODE_OFFSET +`undef SUB_WQE_INLINE_OFFSET +`undef SUB_WQE_PACKET_LENGTH_OFFSET +/*------------------------------------------- Local Macros Undef : End ----------------------------------------------*/ + +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/RPCSubsystem/RDMACore/RequesterCore/ReqTransCore/ReqTransCore_Thread_4.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/RPCSubsystem/RDMACore/RequesterCore/ReqTransCore/ReqTransCore_Thread_4.v new file mode 100644 index 0000000000000000000000000000000000000000..7c1bbe4567d674cc62ff3a511f5f39026d319dbc --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/RPCSubsystem/RDMACore/RequesterCore/ReqTransCore/ReqTransCore_Thread_4.v @@ -0,0 +1,492 @@ +/*------------------------------------------- Module Description : Begin ---------------------------------------------- +Name: ReqTransCore_Thread_4 +Author: YangFan +Function: 1.Push network payload to Payload Buffer. + 2.Generate Completion, Event and Interrupt. +--------------------------------------------- Module Decription : End -----------------------------------------------*/ + +/*------------------------------------------- Timescale Definition : Begin ------------------------------------------*/ +`timescale 1ns / 1ps +/*------------------------------------------- Timescale Definition : End --------------------------------------------*/ + +/*------------------------------------------- Included Files : Begin ------------------------------------------------*/ +`include "protocol_engine_def.vh" +/*------------------------------------------- Included Files : End --------------------------------------------------*/ + +/*------------------------------------------- Input/Output Definition : Begin ---------------------------------------*/ +module ReqTransCore_Thread_4 +( + input wire clk, + input wire rst, + +//Interface with ReqTransCore_Thread_3 + output wire net_req_ren, + input wire [`WQE_META_WIDTH - 1 : 0] net_req_dout, + input wire net_req_empty, + +//Interface with GatherData + output wire net_data_rd_en, + input wire [`DMA_DATA_WIDTH - 1 : 0] net_data_dout, + input wire net_data_empty, + +//ScatterData Req Interface + output reg scatter_req_wen, + output reg [`DMA_LENGTH_WIDTH * 2 + `DMA_ADDR_WIDTH - 1 : 0] scatter_req_din, + input wire scatter_req_prog_full, + + output reg scatter_data_wen, + output reg [`DMA_DATA_WIDTH - 1 : 0] scatter_data_din, + input wire scatter_data_prog_full, + +//Interface WQEBuffer + output wire enqueue_req_valid, + output wire [`MAX_QP_NUM_LOG + `MAX_DMQ_SLOT_NUM_LOG - 1 : 0] enqueue_req_head, + output wire [`RC_WQE_BUFFER_SLOT_WIDTH - 1 : 0] enqueue_req_data, + output wire enqueue_req_start, + output wire enqueue_req_last, + input wire enqueue_req_ready, + + output wire insert_req_valid, + output wire insert_req_start, + output wire insert_req_last, + output wire [`MAX_DB_SLOT_NUM_LOG - 1 : 0] insert_req_head, + output wire [`PACKET_BUFFER_SLOT_WIDTH - 1 : 0] insert_req_data, + input wire insert_req_ready, + + input wire insert_resp_valid, + input wire [`MAX_DB_SLOT_NUM_LOG - 1 : 0] insert_resp_data, + +//Interface with TransportSubsystem + output wire egress_pkt_valid, + output wire [`PKT_META_BUS_WIDTH - 1 : 0] egress_pkt_head, + input wire egress_pkt_ready +); +/*------------------------------------------- Input/Output Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Macros Definition : Begin ---------------------------------------*/ +`define NET_REQ_LOCAL_QPN_OFFSET 23:0 +`define NET_REQ_VERBS_OPCODE_OFFSET 28:24 +`define NET_REQ_REMOTE_QPN_OFFSET 55:32 +`define NET_REQ_NET_OPCODE_OFFSET 60:56 +`define NET_REQ_SERVICE_TYPE_OFFSET 63:61 +`define NET_REQ_FENCE_OFFSET 64 +`define NET_REQ_SOLICITED_EVENT_OFFSET 65 +`define NET_REQ_HEAD_OFFSET 66 +`define NET_REQ_TAIL_OFFSET 67 +`define NET_REQ_INLINE_OFFSET 68 +`define NET_REQ_WQE_ADDR_OFFSET 95:72 +`define NET_REQ_DMAC_OFFSET 143:96 +`define NET_REQ_SMAC_OFFSET 191:144 +`define NET_REQ_DIP_OFFSET 223:192 +`define NET_REQ_SIP_OFFSET 255:224 +`define NET_REQ_IMMEDIATE_OFFSET 287:256 +`define NET_REQ_LKEY_OFFSET 319:288 +`define NET_REQ_LADDR_OFFSET 383:320 +`define NET_REQ_RKEY_OFFSET 415:384 +`define NET_REQ_RADDR_OFFSET 479:416 +`define NET_REQ_CPL_EVENT_ADDR_OFFSET 479:416 +`define NET_REQ_MSG_LENGTH_OFFSET 511:480 +`define NET_REQ_PKT_LENGTH_OFFSET 527:512 +`define NET_REQ_PAYLOAD_BUFFER_ADDR_OFFSET 575:544 + +/*------------------------------------------- Local Macros Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Variables Definition : Begin ------------------------------------*/ +reg [`WQE_META_WIDTH - 1 : 0] net_req_bus; + +wire [23:0] NetReq_local_qpn; +wire [23:0] NetReq_remote_qpn; +wire [4:0] NetReq_net_opcode; +wire [4:0] NetReq_verbs_opcode; +wire [2:0] NetReq_service_type; +wire [0:0] NetReq_fence; +wire [0:0] NetReq_solicted_event; +wire [0:0] NetReq_wqe_head; +wire [0:0] NetReq_wqe_tail; +wire [0:0] NetReq_inline; +wire [23:0] NetReq_ori_wqe_addr; +wire [47:0] NetReq_dmac; +wire [47:0] NetReq_smac; +wire [31:0] NetReq_dip; +wire [31:0] NetReq_sip; +wire [31:0] NetReq_immediate; +wire [31:0] NetReq_lkey; +wire [63:0] NetReq_laddr; +wire [31:0] NetReq_rkey; +wire [63:0] NetReq_raddr; +wire [63:0] NetReq_cpl_event_addr; +wire [31:0] NetReq_msg_length; +wire [`MAX_DB_SLOT_NUM_LOG - 1:0] NetReq_packet_length; +wire [`MAX_DB_SLOT_NUM_LOG - 1:0] NetReq_payload_buffer_addr; +reg [`MAX_DB_SLOT_NUM_LOG - 1:0] NetReq_payload_buffer_addr_diff; + +reg [31:0] payload_piece_count; +reg [31:0] payload_piece_total; + +wire [255:0] cqe_data; +reg [31:0] cqe_my_qpn; +reg [31:0] cqe_my_ee; +reg [31:0] cqe_rqpn; +reg [7:0] cqe_sl_ipok; +reg [7:0] cqe_g_mlpath; +reg [15:0] cqe_rlid; +reg [31:0] cqe_imm_etype_pkey_eec; +reg [31:0] cqe_byte_cnt; +reg [31:0] cqe_wqe; +reg [7:0] cqe_opcode; +reg [7:0] cqe_is_send; +reg [7:0] cqe_owner; + +wire is_rdma_read; +/*------------------------------------------- Local Variables Definition : End --------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : Begin ---------------------------------------*/ +/*------------------------------------------- Submodules Instatiation : End -----------------------------------------*/ + +/*------------------------------------------- State Machine Definition : Begin --------------------------------------*/ +reg [3:0] cur_state; +reg [3:0] next_state; + +parameter [3:0] IDLE_s = 4'd1, + JUDGE_s = 4'd2, + WQE_ENQUEUE_s = 4'd3, + PAYLOAD_INSERT_s = 4'd4, + GEN_CQE_s = 4'd5, + GEN_EVENT_s = 4'd6, + INJECT_s = 4'd7; + +always @(posedge clk or posedge rst) begin + if(rst) begin + cur_state <= IDLE_s; + end + else begin + cur_state <= next_state; + end +end + +always @(*) begin + case(cur_state) + IDLE_s: if(!net_req_empty) begin + next_state = JUDGE_s; + end + else begin + next_state = IDLE_s; + end + JUDGE_s: if(NetReq_net_opcode == `GEN_CQE) begin + next_state = GEN_CQE_s; + end + else if(NetReq_net_opcode == `GEN_EVENT) begin + next_state = GEN_EVENT_s; + end + else if(NetReq_service_type == `RC) begin + next_state = WQE_ENQUEUE_s; + end + else if(NetReq_service_type == `UD || NetReq_service_type == `UC) begin + if(NetReq_inline) begin + next_state = INJECT_s; + end + else begin + next_state = PAYLOAD_INSERT_s; + end + end + else begin + next_state = JUDGE_s; + end + WQE_ENQUEUE_s: if(enqueue_req_valid && enqueue_req_ready) begin + if(NetReq_inline || is_rdma_read) begin + next_state = INJECT_s; + end + else begin + next_state = PAYLOAD_INSERT_s; + end + end + else begin + next_state = WQE_ENQUEUE_s; + end + PAYLOAD_INSERT_s: if(!net_data_empty && insert_req_valid && insert_req_ready && insert_resp_valid && (payload_piece_count == payload_piece_total)) begin + next_state = INJECT_s; + end + else begin + next_state = PAYLOAD_INSERT_s; + end + GEN_CQE_s: if(!scatter_req_prog_full && !scatter_data_prog_full) begin + next_state = IDLE_s; + end + else begin + next_state = GEN_CQE_s; + end + GEN_EVENT_s: if(!scatter_req_prog_full && !scatter_data_prog_full) begin + next_state = IDLE_s; + end + else begin + next_state = GEN_EVENT_s; + end + INJECT_s: if(egress_pkt_valid && egress_pkt_ready) begin + next_state = IDLE_s; + end + else begin + next_state = INJECT_s; + end + default: next_state = IDLE_s; + endcase +end +/*------------------------------------------- State Machine Definition : End ----------------------------------------*/ + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ +//-- is_rdma_read -- +assign is_rdma_read = (NetReq_net_opcode == `RDMA_READ_REQUEST_FIRST || NetReq_net_opcode == `RDMA_READ_REQUEST_MIDDLE || + NetReq_net_opcode == `RDMA_READ_REQUEST_LAST || NetReq_net_opcode == `RDMA_READ_REQUEST_ONLY); + +//-- net_req_bus -- +always @(posedge clk or posedge rst) begin + if(rst) begin + net_req_bus <= 'd0; + end + else if(cur_state == IDLE_s && !net_req_empty) begin + net_req_bus <= net_req_dout; + end + else begin + net_req_bus <= net_req_bus; + end +end + +//-- NetReq_local_qpn -- +//-- NetReq_remote_qpn -- +//-- NetReq_net_opcode -- +//-- NetReq_verbs_opcode -- +//-- NetReq_service_type -- +//-- NetReq_fence -- +//-- NetReq_solicted_event -- +//-- NetReq_wqe_head -- +//-- NetReq_wqe_tail -- +//-- NetReq_inline -- +//-- NetReq_ori_wqe_addr -- +//-- NetReq_dmac -- +//-- NetReq_smac -- +//-- NetReq_dip -- +//-- NetReq_sip -- +//-- NetReq_immediate -- +//-- NetReq_cpl_event_addr -- +//-- NetReq_rkey -- +//-- NetReq_raddr -- +//-- NetReq_msg_length -- +//-- NetReq_packet_length -- +//-- NetReq_payload_buffer_addr -- +assign NetReq_local_qpn = net_req_bus[`NET_REQ_LOCAL_QPN_OFFSET]; +assign NetReq_remote_qpn = net_req_bus[`NET_REQ_REMOTE_QPN_OFFSET]; +assign NetReq_net_opcode = net_req_bus[`NET_REQ_NET_OPCODE_OFFSET]; +assign NetReq_verbs_opcode = net_req_bus[`NET_REQ_VERBS_OPCODE_OFFSET]; +assign NetReq_service_type = net_req_bus[`NET_REQ_SERVICE_TYPE_OFFSET]; +assign NetReq_fence = net_req_bus[`NET_REQ_FENCE_OFFSET]; +assign NetReq_solicted_event = net_req_bus[`NET_REQ_SOLICITED_EVENT_OFFSET]; +assign NetReq_wqe_head = net_req_bus[`NET_REQ_HEAD_OFFSET]; +assign NetReq_wqe_tail = net_req_bus[`NET_REQ_TAIL_OFFSET]; +assign NetReq_inline = net_req_bus[`NET_REQ_INLINE_OFFSET]; +assign NetReq_ori_wqe_addr = net_req_bus[`NET_REQ_WQE_ADDR_OFFSET]; +assign NetReq_dmac = net_req_bus[`NET_REQ_DMAC_OFFSET]; +assign NetReq_smac = net_req_bus[`NET_REQ_SMAC_OFFSET]; +assign NetReq_dip = net_req_bus[`NET_REQ_DIP_OFFSET]; +assign NetReq_sip = net_req_bus[`NET_REQ_SIP_OFFSET]; +assign NetReq_cpl_event_addr = net_req_bus[`NET_REQ_CPL_EVENT_ADDR_OFFSET]; +assign NetReq_immediate = net_req_bus[`NET_REQ_IMMEDIATE_OFFSET]; +assign NetReq_lkey = net_req_bus[`NET_REQ_LKEY_OFFSET]; +assign NetReq_laddr = net_req_bus[`NET_REQ_LADDR_OFFSET]; +assign NetReq_rkey = net_req_bus[`NET_REQ_RKEY_OFFSET]; +assign NetReq_raddr = net_req_bus[`NET_REQ_RADDR_OFFSET]; +assign NetReq_msg_length = net_req_bus[`NET_REQ_MSG_LENGTH_OFFSET]; +assign NetReq_packet_length = net_req_bus[`NET_REQ_PKT_LENGTH_OFFSET]; +assign NetReq_payload_buffer_addr = net_req_bus[`NET_REQ_PAYLOAD_BUFFER_ADDR_OFFSET]; + +//-- NetReq_payload_buffer_addr_diff -- +always @(posedge clk or posedge rst) begin + if (rst) begin + NetReq_payload_buffer_addr_diff <= 'd0; + end + else if(cur_state == IDLE_s) begin + NetReq_payload_buffer_addr_diff <= 'd0; + end + else if (cur_state == JUDGE_s) begin //Inline Payload Start Addr + NetReq_payload_buffer_addr_diff <= NetReq_payload_buffer_addr; + end + else if(cur_state == PAYLOAD_INSERT_s && !net_data_empty && insert_req_valid && insert_req_start && insert_resp_valid) begin + NetReq_payload_buffer_addr_diff <= insert_resp_data; //Non-Inline Payload Start Addr + end + else begin + NetReq_payload_buffer_addr_diff <= NetReq_payload_buffer_addr_diff; + end +end + + +//-- payload_piece_count -- +always @(posedge clk or posedge rst) begin + if(rst) begin + payload_piece_count <= 'd0; + end + else if(cur_state == JUDGE_s) begin + payload_piece_count <= 'd1; + end + else if(cur_state == PAYLOAD_INSERT_s && insert_req_valid && insert_req_ready) begin + payload_piece_count <= payload_piece_count + 'd1; + end + else if(cur_state == INJECT_s) begin + payload_piece_count <= 'd0; + end + else begin + payload_piece_count <= payload_piece_count; + end +end + +//-- payload_piece_total -- +always @(posedge clk or posedge rst) begin + if(rst) begin + payload_piece_total <= 'd0; + end + else if(cur_state == JUDGE_s) begin + payload_piece_total <= NetReq_packet_length[5:0] ? (NetReq_packet_length >> 6) + 1 : NetReq_packet_length >> 6; + end + else if(cur_state == INJECT_s) begin + payload_piece_total <= 'd0; + end + else begin + payload_piece_total <= payload_piece_total; + end +end + +//-- net_req_ren -- +assign net_req_ren = (cur_state == IDLE_s) ? !net_req_empty : 'd0; + +//-- net_data_rd_en -- +assign net_data_rd_en = (cur_state == PAYLOAD_INSERT_s) && !net_data_empty && insert_req_valid && insert_req_ready; + +//-- enqueue_req_valid -- +//-- enqueue_req_head -- +//-- enqueue_req_data -- +//-- enqueue_req_start -- +//-- enqueue_req_last -- +assign enqueue_req_valid = (cur_state == WQE_ENQUEUE_s) ? 'd1 : 'd0; +assign enqueue_req_head = (cur_state == WQE_ENQUEUE_s) ? {'d1, NetReq_local_qpn[`MAX_QP_NUM_LOG - 1 : 0]} : 'd0; +assign enqueue_req_data = (cur_state == WQE_ENQUEUE_s) ? { NetReq_ori_wqe_addr, NetReq_msg_length, NetReq_laddr, NetReq_lkey, NetReq_packet_length, NetReq_dmac[15:0], + NetReq_service_type, NetReq_net_opcode, NetReq_remote_qpn, 3'd0, NetReq_verbs_opcode, NetReq_local_qpn} : 'd0; +assign enqueue_req_start = (cur_state == WQE_ENQUEUE_s) ? 'd1 : 'd0; +assign enqueue_req_last = (cur_state == WQE_ENQUEUE_s) ? 'd1 : 'd0; + +//-- insert_req_valid -- +//-- insert_req_start -- +//-- insert_req_last -- +//-- insert_req_head -- +//-- insert_req_data -- +assign insert_req_valid = (cur_state == PAYLOAD_INSERT_s && !net_data_empty) ? 'd1 : 'd0; +assign insert_req_start = (cur_state == PAYLOAD_INSERT_s && !net_data_empty) ? (payload_piece_count == 'd1) : 'd0; +assign insert_req_last = (cur_state == PAYLOAD_INSERT_s && !net_data_empty) ? (payload_piece_count == payload_piece_total) : 'd0; +assign insert_req_head = (cur_state == PAYLOAD_INSERT_s && insert_req_start && !net_data_empty) ? {NetReq_packet_length[5:0] ? (NetReq_packet_length >> 6) + 1 : NetReq_packet_length >> 6} : 'd0; +assign insert_req_data = (cur_state == PAYLOAD_INSERT_s) ? net_data_dout : 'd0; + +//-- scatter_data_wen -- +//-- scatter_data_din -- +always @(posedge clk or posedge rst) begin + if(rst) begin + scatter_req_wen <= 'd0; + scatter_req_din <= 'd0; + + scatter_data_wen <= 'd0; + scatter_data_din <= 'd0; + end + else if(cur_state == GEN_CQE_s && !scatter_req_prog_full && !scatter_data_prog_full) begin + scatter_req_wen <= 'd1; + scatter_req_din <= {`CQE_LENGTH, `CQE_LENGTH, NetReq_cpl_event_addr}; + + scatter_data_wen <= 'd1; + scatter_data_din <= cqe_data; + end + else if(cur_state == GEN_EVENT_s && !scatter_req_prog_full && !scatter_data_prog_full) begin + scatter_req_wen <= 'd0; + scatter_req_din <='d0; + + scatter_data_wen <= 'd0; + scatter_data_din <= 'd0; + end + else begin + scatter_req_wen <= 'd0; + scatter_req_din <='d0; + + scatter_data_wen <= 'd0; + scatter_data_din <= 'd0; + end +end + +//-- egress_pkt_valid -- +//-- egress_pkt_head -- +assign egress_pkt_valid = (cur_state == INJECT_s) ? 'd1 : 'd0; +assign egress_pkt_head = (cur_state == INJECT_s) ? { 'd0, NetReq_packet_length, NetReq_payload_buffer_addr_diff, NetReq_sip, NetReq_dip, NetReq_smac, NetReq_dmac, + NetReq_immediate, NetReq_raddr, NetReq_rkey, 8'd0, NetReq_remote_qpn, NetReq_service_type, + NetReq_net_opcode, NetReq_local_qpn} : 'd0; +/********************************************** CQE Field Gen : Begin ******************************************************/ +//-- cqe_my_qpn -- +//-- cqe_my_ee -- +//-- cqe_rqpn -- +//-- cqe_sl_ipok -- +//-- cqe_g_mlpath -- +//-- cqe_rlid -- +//-- cqe_imm_etype_pkey_eec -- +//-- cqe_byte_cnt -- +//-- cqe_wqe -- +//-- cqe_opcode -- +//-- cqe_is_send -- +//-- cqe_owner -- +always @(posedge clk or posedge rst) begin + if(rst) begin + cqe_my_qpn <= 'd0; + cqe_my_ee <= 'd0; + cqe_rqpn <= 'd0; + cqe_sl_ipok <= 'd0; + cqe_g_mlpath <= 'd0; + cqe_rlid <= 'd0; + cqe_imm_etype_pkey_eec <= 'd0; + cqe_byte_cnt <= 'd0; + cqe_wqe <= 'd0; + cqe_opcode <= 'd0; + cqe_is_send <= 'd0; + cqe_owner <= 'd0; + end + else if(cur_state == JUDGE_s && next_state == GEN_CQE_s) begin + cqe_my_qpn <= net_req_bus[`NET_REQ_LOCAL_QPN_OFFSET]; + cqe_my_ee <= 'd0; + cqe_rqpn <= net_req_bus[`NET_REQ_REMOTE_QPN_OFFSET]; + cqe_sl_ipok <= 'd0; + cqe_g_mlpath <= 'd0; + cqe_rlid <= net_req_bus[`NET_REQ_DMAC_OFFSET]; + cqe_imm_etype_pkey_eec <= 'd0; + cqe_byte_cnt <= net_req_bus[`NET_REQ_MSG_LENGTH_OFFSET]; + cqe_wqe <= net_req_bus[`NET_REQ_WQE_ADDR_OFFSET]; + cqe_opcode <= net_req_bus[`NET_REQ_VERBS_OPCODE_OFFSET]; + cqe_is_send <= 'd1; + cqe_owner <= `HGHCA_CQ_ENTRY_OWNER_HW; + end + else begin + cqe_my_qpn <= cqe_my_qpn; + cqe_my_ee <= cqe_my_ee; + cqe_rqpn <= cqe_rqpn; + cqe_sl_ipok <= cqe_sl_ipok; + cqe_g_mlpath <= cqe_g_mlpath; + cqe_rlid <= cqe_rlid; + cqe_imm_etype_pkey_eec <= cqe_imm_etype_pkey_eec; + cqe_byte_cnt <= cqe_byte_cnt; + cqe_wqe <= cqe_wqe; + cqe_opcode <= cqe_opcode; + cqe_is_send <= cqe_is_send; + cqe_owner <= cqe_owner; + end +end + +//-- cqe_data -- +assign cqe_data = (cur_state == GEN_CQE_s) ? { cqe_owner, 8'd0, cqe_is_send, cqe_opcode, cqe_wqe, cqe_byte_cnt, cqe_imm_etype_pkey_eec, + cqe_rlid, cqe_g_mlpath, cqe_sl_ipok, cqe_rqpn, cqe_my_ee, cqe_my_qpn} : 'd0; + +/********************************************** CQE Field Gen : End ********************************************************/ + +/*------------------------------------------- Variables Decode : End ----------------------------------------------*/ + +/*------------------------------------------- Local Macros Undef : Begin --------------------------------------------*/ +/*------------------------------------------- Local Macros Undef : End ----------------------------------------------*/ + +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/RPCSubsystem/RDMACore/RequesterCore/RequesterCore.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/RPCSubsystem/RDMACore/RequesterCore/RequesterCore.v new file mode 100644 index 0000000000000000000000000000000000000000..3e348b049a0a5a47c75eef7f8fb19accdfb25520 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/RPCSubsystem/RDMACore/RequesterCore/RequesterCore.v @@ -0,0 +1,487 @@ +/*------------------------------------------- Module Description : Begin ---------------------------------------------- +Name: RequesterCore +Author: YangFan +Function: 1.Requester. +--------------------------------------------- Module Decription : End -----------------------------------------------*/ + +/*------------------------------------------- Timescale Definition : Begin ------------------------------------------*/ +`timescale 1ns / 1ps +/*------------------------------------------- Timescale Definition : End --------------------------------------------*/ + +/*------------------------------------------- Included Files : Begin ------------------------------------------------*/ +`include "protocol_engine_def.vh" +/*------------------------------------------- Included Files : End --------------------------------------------------*/ + +/*------------------------------------------- Input/Output Definition : Begin ---------------------------------------*/ +module RequesterCore +#( + parameter INGRESS_CXT_HEAD_WIDTH = 128, + parameter INGRESS_CXT_DATA_WIDTH = 256, + parameter EGRESS_CXT_HEAD_WIDTH = 128, + parameter EGRESS_CXT_DATA_WIDTH = 256, + + + parameter INGRESS_MR_HEAD_WIDTH = 128, + parameter INGRESS_MR_DATA_WIDTH = 256, + parameter EGRESS_MR_HEAD_WIDTH = 128, + parameter EGRESS_MR_DATA_WIDTH = 256 +) +( + input wire clk, + input wire rst, + +//Interface with WQEParser + input wire TX_REQ_sub_wqe_valid, + input wire [`WQE_META_WIDTH - 1 : 0] TX_REQ_sub_wqe_meta, + output wire TX_REQ_sub_wqe_ready, + +//Interface with OoOStation(For CxtMgt) + output wire TX_REQ_fetch_cxt_ingress_valid, + output wire [`TX_REQ_OOO_CXT_INGRESS_HEAD_WIDTH - 1 : 0] TX_REQ_fetch_cxt_ingress_head, + output wire [`TX_REQ_OOO_CXT_INGRESS_DATA_WIDTH - 1 : 0] TX_REQ_fetch_cxt_ingress_data, + output wire TX_REQ_fetch_cxt_ingress_start, + output wire TX_REQ_fetch_cxt_ingress_last, + input wire TX_REQ_fetch_cxt_ingress_ready, + + input wire TX_REQ_fetch_cxt_egress_valid, + input wire [`TX_REQ_OOO_CXT_EGRESS_HEAD_WIDTH - 1 : 0] TX_REQ_fetch_cxt_egress_head, + input wire [`TX_REQ_OOO_CXT_EGRESS_DATA_WIDTH - 1 : 0] TX_REQ_fetch_cxt_egress_data, + input wire TX_REQ_fetch_cxt_egress_start, + input wire TX_REQ_fetch_cxt_egress_last, + output wire TX_REQ_fetch_cxt_egress_ready, + +//Interface with OoOStation(For MRMgt) + output wire TX_REQ_fetch_mr_ingress_valid, + output wire [`TX_REQ_OOO_MR_INGRESS_HEAD_WIDTH - 1 : 0] TX_REQ_fetch_mr_ingress_head, + output wire [`TX_REQ_OOO_MR_INGRESS_DATA_WIDTH - 1 : 0] TX_REQ_fetch_mr_ingress_data, + output wire TX_REQ_fetch_mr_ingress_start, + output wire TX_REQ_fetch_mr_ingress_last, + input wire TX_REQ_fetch_mr_ingress_ready, + + input wire TX_REQ_fetch_mr_egress_valid, + input wire [`TX_REQ_OOO_MR_EGRESS_HEAD_WIDTH - 1 : 0] TX_REQ_fetch_mr_egress_head, + input wire [`TX_REQ_OOO_MR_EGRESS_DATA_WIDTH - 1 : 0] TX_REQ_fetch_mr_egress_data, + input wire TX_REQ_fetch_mr_egress_start, + input wire TX_REQ_fetch_mr_egress_last, + output wire TX_REQ_fetch_mr_egress_ready, + +//Interface with CompletionQueueMgt + output wire TX_REQ_cq_req_valid, + output wire [`CQ_REQ_HEAD_WIDTH - 1 : 0] TX_REQ_cq_req_head, + input wire TX_REQ_cq_req_ready, + + input wire TX_REQ_cq_resp_valid, + input wire [`CQ_RESP_HEAD_WIDTH - 1 : 0] TX_REQ_cq_resp_head, + output wire TX_REQ_cq_resp_ready, + +//Interface with EventQueueMgt + output wire TX_REQ_eq_req_valid, + output wire [`EQ_REQ_HEAD_WIDTH - 1 : 0] TX_REQ_eq_req_head, + input wire TX_REQ_eq_req_ready, + + input wire TX_REQ_eq_resp_valid, + input wire [`EQ_RESP_HEAD_WIDTH - 1 : 0] TX_REQ_eq_resp_head, + output wire TX_REQ_eq_resp_ready, + +//DMA Read Interface + output wire TX_REQ_gather_req_wr_en, + output wire [`DMA_LENGTH_WIDTH * 2 + `DMA_ADDR_WIDTH - 1 : 0] TX_REQ_gather_req_din, + input wire TX_REQ_gather_req_prog_full, + +//Interface with GatherData + output wire TX_REQ_net_data_rd_en, + input wire [`DMA_DATA_WIDTH - 1 : 0] TX_REQ_net_data_dout, + input wire TX_REQ_net_data_empty, + +//ScatterData Req Interface + output wire TX_REQ_scatter_req_wen, + output wire [`DMA_LENGTH_WIDTH * 2 + `DMA_ADDR_WIDTH - 1 : 0] TX_REQ_scatter_req_din, + input wire TX_REQ_scatter_req_prog_full, + + output wire TX_REQ_scatter_data_wen, + output wire [`DMA_DATA_WIDTH - 1 : 0] TX_REQ_scatter_data_din, + input wire TX_REQ_scatter_data_prog_full, + +//Interface with PacketBuffer + output wire TX_REQ_insert_req_valid, + output wire TX_REQ_insert_req_start, + output wire TX_REQ_insert_req_last, + output wire [`MAX_DB_SLOT_NUM_LOG - 1 : 0] TX_REQ_insert_req_head, + output wire [`PACKET_BUFFER_SLOT_WIDTH - 1 : 0] TX_REQ_insert_req_data, + input wire TX_REQ_insert_req_ready, + + input wire TX_REQ_insert_resp_valid, + input wire [`MAX_DB_SLOT_NUM_LOG - 1 : 0] TX_REQ_insert_resp_data, + +//Interface with TransportSubsystem + output wire TX_REQ_egress_pkt_valid, + output wire [`PKT_META_BUS_WIDTH - 1 : 0] TX_REQ_egress_pkt_head, + input wire TX_REQ_egress_pkt_ready, + +//Interface with PacketDeparser + input wire RX_RESP_ingress_pkt_valid, + input wire [`PKT_META_BUS_WIDTH - 1 : 0] RX_RESP_ingress_pkt_head, + output wire RX_RESP_ingress_pkt_ready, + +//Interface with OoOStation(For CxtMgt) + output wire RX_RESP_fetch_cxt_ingress_valid, + output wire [`RX_RESP_OOO_CXT_INGRESS_HEAD_WIDTH - 1 : 0] RX_RESP_fetch_cxt_ingress_head, + output wire [`RX_RESP_OOO_CXT_INGRESS_DATA_WIDTH - 1 : 0] RX_RESP_fetch_cxt_ingress_data, + output wire RX_RESP_fetch_cxt_ingress_start, + output wire RX_RESP_fetch_cxt_ingress_last, + input wire RX_RESP_fetch_cxt_ingress_ready, + + input wire RX_RESP_fetch_cxt_egress_valid, + input wire [`RX_RESP_OOO_CXT_EGRESS_HEAD_WIDTH - 1 : 0] RX_RESP_fetch_cxt_egress_head, + input wire [`RX_RESP_OOO_CXT_EGRESS_DATA_WIDTH - 1 : 0] RX_RESP_fetch_cxt_egress_data, + input wire RX_RESP_fetch_cxt_egress_start, + input wire RX_RESP_fetch_cxt_egress_last, + output wire RX_RESP_fetch_cxt_egress_ready, + +//Interface with OoOStation(For MRMgt) + output wire RX_RESP_fetch_mr_ingress_valid, + output wire [`RX_RESP_OOO_MR_INGRESS_HEAD_WIDTH - 1 : 0] RX_RESP_fetch_mr_ingress_head, + output wire [`RX_RESP_OOO_MR_INGRESS_DATA_WIDTH - 1 : 0] RX_RESP_fetch_mr_ingress_data, + output wire RX_RESP_fetch_mr_ingress_start, + output wire RX_RESP_fetch_mr_ingress_last, + input wire RX_RESP_fetch_mr_ingress_ready, + + input wire RX_RESP_fetch_mr_egress_valid, + input wire [`RX_RESP_OOO_MR_EGRESS_HEAD_WIDTH - 1 : 0] RX_RESP_fetch_mr_egress_head, + input wire [`RX_RESP_OOO_MR_EGRESS_DATA_WIDTH - 1 : 0] RX_RESP_fetch_mr_egress_data, + input wire RX_RESP_fetch_mr_egress_start, + input wire RX_RESP_fetch_mr_egress_last, + output wire RX_RESP_fetch_mr_egress_ready, + +//Interface with CompletionQueueMgt + output wire RX_RESP_cq_req_valid, + output wire [`CQ_REQ_HEAD_WIDTH - 1 : 0] RX_RESP_cq_req_head, + input wire RX_RESP_cq_req_ready, + + input wire RX_RESP_cq_resp_valid, + input wire [`CQ_RESP_HEAD_WIDTH - 1 : 0] RX_RESP_cq_resp_head, + output wire RX_RESP_cq_resp_ready, + +//Interface with EventQueueMgt + output wire RX_RESP_eq_req_valid, + output wire [`EQ_REQ_HEAD_WIDTH - 1 : 0] RX_RESP_eq_req_head, + input wire RX_RESP_eq_req_ready, + + input wire RX_RESP_eq_resp_valid, + input wire [`EQ_RESP_HEAD_WIDTH - 1 : 0] RX_RESP_eq_resp_head, + output wire RX_RESP_eq_resp_ready, + +//ScatterData Req Interface + output wire RX_RESP_scatter_req_wen, + output wire [`DMA_LENGTH_WIDTH * 2 + `DMA_ADDR_WIDTH - 1 : 0] RX_RESP_scatter_req_din, + input wire RX_RESP_scatter_req_prog_full, + + output wire RX_RESP_scatter_data_wen, + output wire [`DMA_DATA_WIDTH - 1 : 0] RX_RESP_scatter_data_din, + input wire RX_RESP_scatter_data_prog_full, + +//Interface with PacketBuffer + output wire RX_RESP_delete_req_valid, + output wire [`RECV_BUFFER_SLOT_NUM_LOG * 2 - 1 : 0] RX_RESP_delete_req_head, + input wire RX_RESP_delete_req_ready, + + input wire RX_RESP_delete_resp_valid, + input wire RX_RESP_delete_resp_start, + input wire RX_RESP_delete_resp_last, + input wire [`RECV_BUFFER_SLOT_WIDTH - 1 : 0] RX_RESP_delete_resp_data, + output wire RX_RESP_delete_resp_ready +); + +/*------------------------------------------- Input/Output Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Macros Definition : Begin ---------------------------------------*/ +/*------------------------------------------- Local Macros Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Variables Definition : Begin ------------------------------------*/ +wire wqe_enqueue_req_valid; +wire [`MAX_QP_NUM_LOG + `MAX_DMQ_SLOT_NUM_LOG - 1 : 0] wqe_enqueue_req_head; +wire [`RC_WQE_BUFFER_SLOT_WIDTH - 1 : 0] wqe_enqueue_req_data; +wire wqe_enqueue_req_start; +wire wqe_enqueue_req_last; +wire wqe_enqueue_req_ready; + +wire wqe_dequeue_req_valid; +wire [`MAX_QP_NUM_LOG + `MAX_DMQ_SLOT_NUM_LOG - 1 : 0] wqe_dequeue_req_head; +wire wqe_dequeue_req_ready; + +wire wqe_dequeue_resp_valid; +wire [`MAX_QP_NUM_LOG + `MAX_DMQ_SLOT_NUM_LOG - 1 : 0] wqe_dequeue_resp_head; +wire wqe_dequeue_resp_start; +wire wqe_dequeue_resp_last; +wire wqe_dequeue_resp_ready; +wire [`RC_WQE_BUFFER_SLOT_WIDTH - 1 : 0] wqe_dequeue_resp_data; + +/*------------------------------------------- Local Variables Definition : End --------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : Begin ---------------------------------------*/ +ReqTransCore #( + .INGRESS_CXT_HEAD_WIDTH ( INGRESS_CXT_HEAD_WIDTH ), + .INGRESS_CXT_DATA_WIDTH ( INGRESS_CXT_DATA_WIDTH ), + .EGRESS_CXT_HEAD_WIDTH ( EGRESS_CXT_HEAD_WIDTH ), + .EGRESS_CXT_DATA_WIDTH ( EGRESS_CXT_DATA_WIDTH ), + + + .INGRESS_MR_HEAD_WIDTH ( INGRESS_MR_HEAD_WIDTH ), + .INGRESS_MR_DATA_WIDTH ( INGRESS_MR_DATA_WIDTH ), + .EGRESS_MR_HEAD_WIDTH ( EGRESS_MR_HEAD_WIDTH ), + .EGRESS_MR_DATA_WIDTH ( EGRESS_MR_DATA_WIDTH ) +) +ReqTransCore_Inst +( + .clk ( clk ), + .rst ( rst ), + + .sub_wqe_valid ( TX_REQ_sub_wqe_valid ), + .sub_wqe_meta ( TX_REQ_sub_wqe_meta ), + .sub_wqe_ready ( TX_REQ_sub_wqe_ready ), + + .fetch_cxt_ingress_valid ( TX_REQ_fetch_cxt_ingress_valid ), + .fetch_cxt_ingress_head ( TX_REQ_fetch_cxt_ingress_head ), + .fetch_cxt_ingress_data ( TX_REQ_fetch_cxt_ingress_data ), + .fetch_cxt_ingress_start ( TX_REQ_fetch_cxt_ingress_start ), + .fetch_cxt_ingress_last ( TX_REQ_fetch_cxt_ingress_last ), + .fetch_cxt_ingress_ready ( TX_REQ_fetch_cxt_ingress_ready ), + + .fetch_cxt_egress_valid ( TX_REQ_fetch_cxt_egress_valid ), + .fetch_cxt_egress_head ( TX_REQ_fetch_cxt_egress_head ), + .fetch_cxt_egress_data ( TX_REQ_fetch_cxt_egress_data ), + .fetch_cxt_egress_start ( TX_REQ_fetch_cxt_egress_start ), + .fetch_cxt_egress_last ( TX_REQ_fetch_cxt_egress_last ), + .fetch_cxt_egress_ready ( TX_REQ_fetch_cxt_egress_ready ), + + .fetch_mr_ingress_valid ( TX_REQ_fetch_mr_ingress_valid ), + .fetch_mr_ingress_head ( TX_REQ_fetch_mr_ingress_head ), + .fetch_mr_ingress_data ( TX_REQ_fetch_mr_ingress_data ), + .fetch_mr_ingress_start ( TX_REQ_fetch_mr_ingress_start ), + .fetch_mr_ingress_last ( TX_REQ_fetch_mr_ingress_last ), + .fetch_mr_ingress_ready ( TX_REQ_fetch_mr_ingress_ready ), + + .fetch_mr_egress_valid ( TX_REQ_fetch_mr_egress_valid ), + .fetch_mr_egress_head ( TX_REQ_fetch_mr_egress_head ), + .fetch_mr_egress_data ( TX_REQ_fetch_mr_egress_data ), + .fetch_mr_egress_start ( TX_REQ_fetch_mr_egress_start ), + .fetch_mr_egress_last ( TX_REQ_fetch_mr_egress_last ), + .fetch_mr_egress_ready ( TX_REQ_fetch_mr_egress_ready ), + + .cq_req_valid ( TX_REQ_cq_req_valid ), + .cq_req_head ( TX_REQ_cq_req_head ), + .cq_req_ready ( TX_REQ_cq_req_ready ), + + .cq_resp_valid ( TX_REQ_cq_resp_valid ), + .cq_resp_head ( TX_REQ_cq_resp_head ), + .cq_resp_ready ( TX_REQ_cq_resp_ready ), + + .eq_req_valid ( TX_REQ_eq_req_valid ), + .eq_req_head ( TX_REQ_eq_req_head ), + .eq_req_ready ( TX_REQ_eq_req_ready ), + + .eq_resp_valid ( TX_REQ_eq_resp_valid ), + .eq_resp_head ( TX_REQ_eq_resp_head ), + .eq_resp_ready ( TX_REQ_eq_resp_ready ), + + .gather_req_wr_en ( TX_REQ_gather_req_wr_en ), + .gather_req_din ( TX_REQ_gather_req_din ), + .gather_req_prog_full ( TX_REQ_gather_req_prog_full ), + + .net_data_rd_en ( TX_REQ_net_data_rd_en ), + .net_data_dout ( TX_REQ_net_data_dout ), + .net_data_empty ( TX_REQ_net_data_empty ), + + .scatter_req_wen ( TX_REQ_scatter_req_wen ), + .scatter_req_din ( TX_REQ_scatter_req_din ), + .scatter_req_prog_full ( TX_REQ_scatter_req_prog_full ), + + .scatter_data_wen ( TX_REQ_scatter_data_wen ), + .scatter_data_din ( TX_REQ_scatter_data_din ), + .scatter_data_prog_full ( TX_REQ_scatter_data_prog_full ), + + .enqueue_req_valid ( wqe_enqueue_req_valid ), + .enqueue_req_head ( wqe_enqueue_req_head ), + .enqueue_req_data ( wqe_enqueue_req_data ), + .enqueue_req_start ( wqe_enqueue_req_start ), + .enqueue_req_last ( wqe_enqueue_req_last ), + .enqueue_req_ready ( wqe_enqueue_req_ready ), + + .insert_req_valid ( TX_REQ_insert_req_valid ), + .insert_req_start ( TX_REQ_insert_req_start ), + .insert_req_last ( TX_REQ_insert_req_last ), + .insert_req_head ( TX_REQ_insert_req_head ), + .insert_req_data ( TX_REQ_insert_req_data ), + .insert_req_ready ( TX_REQ_insert_req_ready ), + + .insert_resp_valid ( TX_REQ_insert_resp_valid ), + .insert_resp_data ( TX_REQ_insert_resp_data ), + + .egress_pkt_valid ( TX_REQ_egress_pkt_valid ), + .egress_pkt_head ( TX_REQ_egress_pkt_head ), + .egress_pkt_ready ( TX_REQ_egress_pkt_ready ) +); + +RespRecvCore +#( + .INGRESS_CXT_HEAD_WIDTH ( INGRESS_CXT_HEAD_WIDTH ), + .INGRESS_CXT_DATA_WIDTH ( INGRESS_CXT_DATA_WIDTH ), + .EGRESS_CXT_HEAD_WIDTH ( EGRESS_CXT_HEAD_WIDTH ), + .EGRESS_CXT_DATA_WIDTH ( EGRESS_CXT_DATA_WIDTH ), + + .INGRESS_MR_HEAD_WIDTH ( INGRESS_MR_HEAD_WIDTH ), + .INGRESS_MR_DATA_WIDTH ( INGRESS_MR_DATA_WIDTH ), + .EGRESS_MR_HEAD_WIDTH ( EGRESS_MR_HEAD_WIDTH ), + .EGRESS_MR_DATA_WIDTH ( EGRESS_MR_DATA_WIDTH ) +) +RespRecvCore_Inst +( + .clk ( clk ), + .rst ( rst ), + + .ingress_pkt_valid ( RX_RESP_ingress_pkt_valid ), + .ingress_pkt_head ( RX_RESP_ingress_pkt_head ), + .ingress_pkt_ready ( RX_RESP_ingress_pkt_ready ), + + .fetch_cxt_ingress_valid ( RX_RESP_fetch_cxt_ingress_valid ), + .fetch_cxt_ingress_head ( RX_RESP_fetch_cxt_ingress_head ), + .fetch_cxt_ingress_data ( RX_RESP_fetch_cxt_ingress_data ), + .fetch_cxt_ingress_start ( RX_RESP_fetch_cxt_ingress_start ), + .fetch_cxt_ingress_last ( RX_RESP_fetch_cxt_ingress_last ), + .fetch_cxt_ingress_ready ( RX_RESP_fetch_cxt_ingress_ready ), + + .fetch_cxt_egress_valid ( RX_RESP_fetch_cxt_egress_valid ), + .fetch_cxt_egress_head ( RX_RESP_fetch_cxt_egress_head ), + .fetch_cxt_egress_data ( RX_RESP_fetch_cxt_egress_data ), + .fetch_cxt_egress_start ( RX_RESP_fetch_cxt_egress_start ), + .fetch_cxt_egress_last ( RX_RESP_fetch_cxt_egress_last ), + .fetch_cxt_egress_ready ( RX_RESP_fetch_cxt_egress_ready ), + + .fetch_mr_ingress_valid ( RX_RESP_fetch_mr_ingress_valid ), + .fetch_mr_ingress_head ( RX_RESP_fetch_mr_ingress_head ), + .fetch_mr_ingress_data ( RX_RESP_fetch_mr_ingress_data ), + .fetch_mr_ingress_start ( RX_RESP_fetch_mr_ingress_start ), + .fetch_mr_ingress_last ( RX_RESP_fetch_mr_ingress_last ), + .fetch_mr_ingress_ready ( RX_RESP_fetch_mr_ingress_ready ), + + .fetch_mr_egress_valid ( RX_RESP_fetch_mr_egress_valid ), + .fetch_mr_egress_head ( RX_RESP_fetch_mr_egress_head ), + .fetch_mr_egress_data ( RX_RESP_fetch_mr_egress_data ), + .fetch_mr_egress_start ( RX_RESP_fetch_mr_egress_start ), + .fetch_mr_egress_last ( RX_RESP_fetch_mr_egress_last ), + .fetch_mr_egress_ready ( RX_RESP_fetch_mr_egress_ready ), + + .dequeue_req_valid ( wqe_dequeue_req_valid ), + .dequeue_req_head ( wqe_dequeue_req_head ), + .dequeue_req_ready ( wqe_dequeue_req_ready ), + + .dequeue_resp_valid ( wqe_dequeue_resp_valid ), + .dequeue_resp_head ( wqe_dequeue_resp_head ), + .dequeue_resp_start ( wqe_dequeue_resp_start ), + .dequeue_resp_last ( wqe_dequeue_resp_last ), + .dequeue_resp_ready ( wqe_dequeue_resp_ready ), + .dequeue_resp_data ( wqe_dequeue_resp_data ), + + .cq_req_valid ( RX_RESP_cq_req_valid ), + .cq_req_head ( RX_RESP_cq_req_head ), + .cq_req_ready ( RX_RESP_cq_req_ready ), + + .cq_resp_valid ( RX_RESP_cq_resp_valid ), + .cq_resp_head ( RX_RESP_cq_resp_head ), + .cq_resp_ready ( RX_RESP_cq_resp_ready ), + + .eq_req_valid ( RX_RESP_eq_req_valid ), + .eq_req_head ( RX_RESP_eq_req_head ), + .eq_req_ready ( RX_RESP_eq_req_ready ), + + .eq_resp_valid ( RX_RESP_eq_resp_valid ), + .eq_resp_head ( RX_RESP_eq_resp_head ), + .eq_resp_ready ( RX_RESP_eq_resp_ready ), + + .scatter_req_wen ( RX_RESP_scatter_req_wen ), + .scatter_req_din ( RX_RESP_scatter_req_din ), + .scatter_req_prog_full ( RX_RESP_scatter_req_prog_full ), + + .scatter_data_wen ( RX_RESP_scatter_data_wen ), + .scatter_data_din ( RX_RESP_scatter_data_din ), + .scatter_data_prog_full ( RX_RESP_scatter_data_prog_full ), + + .delete_req_valid ( RX_RESP_delete_req_valid ), + .delete_req_head ( RX_RESP_delete_req_head ), + .delete_req_ready ( RX_RESP_delete_req_ready ), + + .delete_resp_valid ( RX_RESP_delete_resp_valid ), + .delete_resp_start ( RX_RESP_delete_resp_start ), + .delete_resp_last ( RX_RESP_delete_resp_last ), + .delete_resp_data ( RX_RESP_delete_resp_data ), + .delete_resp_ready ( RX_RESP_delete_resp_ready ) +); + +DynamicMultiQueue #( + .SLOT_WIDTH ( `RC_WQE_BUFFER_SLOT_WIDTH ), + .SLOT_NUM ( `RC_WQE_BUFFER_SLOT_NUM ), + .QUEUE_NUM ( `QP_NUM ) +) +WQEBuffer_Inst +( + .clk ( clk ), + .rst ( rst ), + + .ov_available_slot_num ( ), + + .i_enqueue_req_valid ( wqe_enqueue_req_valid ), + .iv_enqueue_req_head ( wqe_enqueue_req_head ), + .iv_enqueue_req_data ( wqe_enqueue_req_data ), + .i_enqueue_req_start ( wqe_enqueue_req_start ), + .i_enqueue_req_last ( wqe_enqueue_req_last ), + .o_enqueue_req_ready ( wqe_enqueue_req_ready ), + + .i_empty_req_valid ( 'd0 ), + .iv_empty_req_head ( 'd0 ), + .o_empty_req_ready ( ), + + .o_empty_resp_valid ( ), + .ov_empty_resp_head ( ), + .i_empty_resp_ready ( 'd0 ), + + .i_dequeue_req_valid ( wqe_dequeue_req_valid ), + .iv_dequeue_req_head ( wqe_dequeue_req_head ), + .o_dequeue_req_ready ( wqe_dequeue_req_ready ), + + .o_dequeue_resp_valid ( wqe_dequeue_resp_valid ), + .ov_dequeue_resp_head ( wqe_dequeue_resp_head ), + .o_dequeue_resp_start ( wqe_dequeue_resp_start ), + .o_dequeue_resp_last ( wqe_dequeue_resp_last ), + .i_dequeue_resp_ready ( wqe_dequeue_resp_ready ), + .ov_dequeue_resp_data ( wqe_dequeue_resp_data ), + + .i_modify_head_req_valid ( 'd0 ), + .iv_modify_head_req_head ( 'd0 ), + .iv_modify_head_req_data ( 'd0 ), + .o_modify_head_req_ready ( ), + + .i_get_req_valid ( 'd0 ), + .iv_get_req_head ( 'd0 ), + .o_get_req_ready ( ), + + .o_get_resp_valid ( ), + .ov_get_resp_head ( ), + .o_get_resp_start ( ), + .o_get_resp_last ( ), + .ov_get_resp_data ( ), + .o_get_resp_empty ( ), + .i_get_resp_ready ( 'd0 ) +); +/*------------------------------------------- Submodules Instatiation : End -----------------------------------------*/ + +/*------------------------------------------- State Machine Definition : Begin --------------------------------------*/ +/*------------------------------------------- State Machine Definition : End ----------------------------------------*/ + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ +/*------------------------------------------- Variables Decode : End ----------------------------------------------*/ + +/*------------------------------------------- Local Macros Undef : Begin --------------------------------------------*/ + +/*------------------------------------------- Local Macros Undef : End ----------------------------------------------*/ + +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/RPCSubsystem/RDMACore/RequesterCore/RespRecvCore/RespRecvCore.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/RPCSubsystem/RDMACore/RequesterCore/RespRecvCore/RespRecvCore.v new file mode 100644 index 0000000000000000000000000000000000000000..672d9a75e3d0bcf747c1a37c47c05acb1a620560 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/RPCSubsystem/RDMACore/RequesterCore/RespRecvCore/RespRecvCore.v @@ -0,0 +1,245 @@ +/*------------------------------------------- Module Description : Begin ---------------------------------------------- +Name: RespRecvCore +Author: YangFan +Function: 1.Handle response from network. +--------------------------------------------- Module Decription : End -----------------------------------------------*/ + +/*------------------------------------------- Timescale Definition : Begin ------------------------------------------*/ +`timescale 1ns / 1ps +/*------------------------------------------- Timescale Definition : End --------------------------------------------*/ + +/*------------------------------------------- Included Files : Begin ------------------------------------------------*/ +`include "protocol_engine_def.vh" +/*------------------------------------------- Included Files : End --------------------------------------------------*/ + +/*------------------------------------------- Input/Output Definition : Begin ---------------------------------------*/ +module RespRecvCore +#( + parameter INGRESS_CXT_HEAD_WIDTH = 128, + parameter INGRESS_CXT_DATA_WIDTH = 256, + parameter EGRESS_CXT_HEAD_WIDTH = 128, + parameter EGRESS_CXT_DATA_WIDTH = 256, + + parameter INGRESS_MR_HEAD_WIDTH = 128, + parameter INGRESS_MR_DATA_WIDTH = 256, + parameter EGRESS_MR_HEAD_WIDTH = 128, + parameter EGRESS_MR_DATA_WIDTH = 256 +) +( + input wire clk, + input wire rst, + +//Interface with PacketDeparser + input wire ingress_pkt_valid, + input wire [`PKT_META_BUS_WIDTH - 1 : 0] ingress_pkt_head, + output wire ingress_pkt_ready, + +//Interface with OoOStation(For CxtMgt) + output wire fetch_cxt_ingress_valid, + output wire [`RX_RESP_OOO_CXT_INGRESS_HEAD_WIDTH - 1 : 0] fetch_cxt_ingress_head, + output wire [`RX_RESP_OOO_CXT_INGRESS_DATA_WIDTH - 1 : 0] fetch_cxt_ingress_data, + output wire fetch_cxt_ingress_start, + output wire fetch_cxt_ingress_last, + input wire fetch_cxt_ingress_ready, + + input wire fetch_cxt_egress_valid, + input wire [`RX_RESP_OOO_CXT_EGRESS_HEAD_WIDTH - 1 : 0] fetch_cxt_egress_head, + input wire [`RX_RESP_OOO_CXT_EGRESS_DATA_WIDTH - 1 : 0] fetch_cxt_egress_data, + input wire fetch_cxt_egress_start, + input wire fetch_cxt_egress_last, + output wire fetch_cxt_egress_ready, + +//Interface with OoOStation(For MRMgt) + output wire fetch_mr_ingress_valid, + output wire [`RX_RESP_OOO_MR_INGRESS_HEAD_WIDTH - 1 : 0] fetch_mr_ingress_head, + output wire [`RX_RESP_OOO_MR_INGRESS_DATA_WIDTH - 1 : 0] fetch_mr_ingress_data, + output wire fetch_mr_ingress_start, + output wire fetch_mr_ingress_last, + input wire fetch_mr_ingress_ready, + + input wire fetch_mr_egress_valid, + input wire [`RX_RESP_OOO_MR_EGRESS_HEAD_WIDTH - 1 : 0] fetch_mr_egress_head, + input wire [`RX_RESP_OOO_MR_EGRESS_DATA_WIDTH - 1 : 0] fetch_mr_egress_data, + input wire fetch_mr_egress_start, + input wire fetch_mr_egress_last, + output wire fetch_mr_egress_ready, + +//Interface with WQEBuffer + output wire dequeue_req_valid, + output wire [`QP_NUM_LOG + `WQE_BUFFER_SLOT_NUM_LOG - 1 : 0] dequeue_req_head, + input wire dequeue_req_ready, + + input wire dequeue_resp_valid, + input wire [`QP_NUM_LOG + `WQE_BUFFER_SLOT_NUM_LOG - 1 : 0] dequeue_resp_head, + input wire dequeue_resp_start, + input wire dequeue_resp_last, + output wire dequeue_resp_ready, + input wire [`RC_WQE_BUFFER_SLOT_WIDTH - 1 : 0] dequeue_resp_data, + +//Interface with CompletionQueueMgt + output wire cq_req_valid, + output wire [`CQ_REQ_HEAD_WIDTH - 1 : 0] cq_req_head, + input wire cq_req_ready, + + input wire cq_resp_valid, + input wire [`CQ_RESP_HEAD_WIDTH - 1 : 0] cq_resp_head, + output wire cq_resp_ready, + +//Interface with EventQueueMgt + output wire eq_req_valid, + output wire [`EQ_REQ_HEAD_WIDTH - 1 : 0] eq_req_head, + input wire eq_req_ready, + + input wire eq_resp_valid, + input wire [`EQ_RESP_HEAD_WIDTH - 1 : 0] eq_resp_head, + output wire eq_resp_ready, + +//ScatterData Req Interface + output wire scatter_req_wen, + output wire [`DMA_LENGTH_WIDTH * 2 + `DMA_ADDR_WIDTH - 1 : 0] scatter_req_din, + input wire scatter_req_prog_full, + + output wire scatter_data_wen, + output wire [`DMA_DATA_WIDTH - 1 : 0] scatter_data_din, + input wire scatter_data_prog_full, + +//Interface with PacketBuffer + output wire delete_req_valid, + output wire [`RECV_BUFFER_SLOT_NUM_LOG * 2 - 1 : 0] delete_req_head, + input wire delete_req_ready, + + input wire delete_resp_valid, + input wire delete_resp_start, + input wire delete_resp_last, + input wire [`RECV_BUFFER_SLOT_WIDTH - 1 : 0] delete_resp_data, + output wire delete_resp_ready +); +/*------------------------------------------- Input/Output Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Macros Definition : Begin ---------------------------------------*/ +/*------------------------------------------- Local Macros Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Variables Definition : Begin ------------------------------------*/ +/*------------------------------------------- Local Variables Definition : End --------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : Begin ---------------------------------------*/ +RespRecvCore_Thread_1 #( + .INGRESS_CXT_HEAD_WIDTH ( INGRESS_CXT_HEAD_WIDTH ), + .INGRESS_CXT_DATA_WIDTH ( INGRESS_CXT_DATA_WIDTH ) +) +RespRecvCore_Thread_1_Inst +( + .clk ( clk ), + .rst ( rst ), + + .ingress_pkt_valid ( ingress_pkt_valid ), + .ingress_pkt_head ( ingress_pkt_head ), + .ingress_pkt_ready ( ingress_pkt_ready ), + + .fetch_cxt_ingress_valid ( fetch_cxt_ingress_valid ), + .fetch_cxt_ingress_head ( fetch_cxt_ingress_head ), + .fetch_cxt_ingress_data ( fetch_cxt_ingress_data ), + .fetch_cxt_ingress_start ( fetch_cxt_ingress_start ), + .fetch_cxt_ingress_last ( fetch_cxt_ingress_last ), + .fetch_cxt_ingress_ready ( fetch_cxt_ingress_ready ) +); + +RespRecvCore_Thread_2 #( + .INGRESS_MR_HEAD_WIDTH ( INGRESS_MR_HEAD_WIDTH ), + .INGRESS_MR_DATA_WIDTH ( INGRESS_MR_DATA_WIDTH ), + .EGRESS_CXT_HEAD_WIDTH ( EGRESS_CXT_HEAD_WIDTH ), + .EGRESS_CXT_DATA_WIDTH ( EGRESS_CXT_DATA_WIDTH ) +) +RespRecvCore_Thread_2_Inst +( + .clk ( clk ), + .rst ( rst ), + + .fetch_cxt_egress_valid ( fetch_cxt_egress_valid ), + .fetch_cxt_egress_head ( fetch_cxt_egress_head ), + .fetch_cxt_egress_data ( fetch_cxt_egress_data ), + .fetch_cxt_egress_start ( fetch_cxt_egress_start ), + .fetch_cxt_egress_last ( fetch_cxt_egress_last ), + .fetch_cxt_egress_ready ( fetch_cxt_egress_ready ), + + .fetch_mr_ingress_valid ( fetch_mr_ingress_valid ), + .fetch_mr_ingress_head ( fetch_mr_ingress_head ), + .fetch_mr_ingress_data ( fetch_mr_ingress_data ), + .fetch_mr_ingress_start ( fetch_mr_ingress_start ), + .fetch_mr_ingress_last ( fetch_mr_ingress_last ), + .fetch_mr_ingress_ready ( fetch_mr_ingress_ready ), + + .dequeue_req_valid ( dequeue_req_valid ), + .dequeue_req_head ( dequeue_req_head ), + .dequeue_req_ready ( dequeue_req_ready ), + + .dequeue_resp_valid ( dequeue_resp_valid ), + .dequeue_resp_head ( dequeue_resp_head ), + .dequeue_resp_start ( dequeue_resp_start ), + .dequeue_resp_last ( dequeue_resp_last ), + .dequeue_resp_ready ( dequeue_resp_ready ), + .dequeue_resp_data ( dequeue_resp_data ), + + .cq_req_valid ( cq_req_valid ), + .cq_req_head ( cq_req_head ), + .cq_req_ready ( cq_req_ready ), + + .cq_resp_valid ( cq_resp_valid ), + .cq_resp_head ( cq_resp_head ), + .cq_resp_ready ( cq_resp_ready ), + + .eq_req_valid ( eq_req_valid ), + .eq_req_head ( eq_req_head ), + .eq_req_ready ( eq_req_ready ), + + .eq_resp_valid ( eq_resp_valid ), + .eq_resp_head ( eq_resp_head ), + .eq_resp_ready ( eq_resp_ready ) +); + +RespRecvCore_Thread_3 #( + .EGRESS_MR_HEAD_WIDTH ( EGRESS_MR_HEAD_WIDTH ), + .EGRESS_MR_DATA_WIDTH ( EGRESS_MR_DATA_WIDTH ) +) +RespRecvCore_Thread_3_Inst +( + .clk ( clk ), + .rst ( rst ), + + .fetch_mr_egress_valid ( fetch_mr_egress_valid ), + .fetch_mr_egress_head ( fetch_mr_egress_head ), + .fetch_mr_egress_data ( fetch_mr_egress_data ), + .fetch_mr_egress_start ( fetch_mr_egress_start ), + .fetch_mr_egress_last ( fetch_mr_egress_last ), + .fetch_mr_egress_ready ( fetch_mr_egress_ready ), + + .scatter_req_wen ( scatter_req_wen ), + .scatter_req_din ( scatter_req_din ), + .scatter_req_prog_full ( scatter_req_prog_full ), + + .scatter_data_wen ( scatter_data_wen ), + .scatter_data_din ( scatter_data_din ), + .scatter_data_prog_full ( scatter_data_prog_full ), + + .delete_req_valid ( delete_req_valid ), + .delete_req_head ( delete_req_head ), + .delete_req_ready ( delete_req_ready ), + + .delete_resp_valid ( delete_resp_valid ), + .delete_resp_start ( delete_resp_start ), + .delete_resp_last ( delete_resp_last ), + .delete_resp_data ( delete_resp_data ), + .delete_resp_ready ( delete_resp_ready ) +); +/*------------------------------------------- Submodules Instatiation : End -----------------------------------------*/ + +/*------------------------------------------- State Machine Definition : Begin --------------------------------------*/ +/*------------------------------------------- State Machine Definition : End ----------------------------------------*/ + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ +/*------------------------------------------- Variables Decode : End ------------------------------------------------*/ + +/*------------------------------------------- Local Macros Undef : Begin --------------------------------------------*/ +/*------------------------------------------- Local Macros Undef : End ----------------------------------------------*/ + +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/RPCSubsystem/RDMACore/RequesterCore/RespRecvCore/RespRecvCore_Thread_1.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/RPCSubsystem/RDMACore/RequesterCore/RespRecvCore/RespRecvCore_Thread_1.v new file mode 100644 index 0000000000000000000000000000000000000000..2a30731759c23211e280d27193571e14703c4927 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/RPCSubsystem/RDMACore/RequesterCore/RespRecvCore/RespRecvCore_Thread_1.v @@ -0,0 +1,184 @@ +/*------------------------------------------- Module Description : Begin ---------------------------------------------- +Name: RespRecvCore_Thread_1 +Author: YangFan +Function: 1.Fetch Cxt and generate Net Meta. +--------------------------------------------- Module Decription : End -----------------------------------------------*/ + +/*------------------------------------------- Timescale Definition : Begin ------------------------------------------*/ +`timescale 1ns / 1ps +/*------------------------------------------- Timescale Definition : End --------------------------------------------*/ + +/*------------------------------------------- Included Files : Begin ------------------------------------------------*/ +`include "protocol_engine_def.vh" +/*------------------------------------------- Included Files : End --------------------------------------------------*/ + +/*------------------------------------------- Input/Output Definition : Begin ---------------------------------------*/ +module RespRecvCore_Thread_1 +#( + parameter INGRESS_CXT_HEAD_WIDTH = 128, + parameter INGRESS_CXT_DATA_WIDTH = 256 +) +( + input wire clk, + input wire rst, + +//Interface with PacketDeparser + input wire ingress_pkt_valid, + input wire [`PKT_META_BUS_WIDTH - 1 : 0] ingress_pkt_head, + output wire ingress_pkt_ready, + +//Interface with OoOStation(For CxtMgt) + output wire fetch_cxt_ingress_valid, + output wire [`RX_RESP_OOO_CXT_INGRESS_HEAD_WIDTH - 1 : 0] fetch_cxt_ingress_head, + output wire [`RX_RESP_OOO_CXT_INGRESS_DATA_WIDTH - 1 : 0] fetch_cxt_ingress_data, + output wire fetch_cxt_ingress_start, + output wire fetch_cxt_ingress_last, + input wire fetch_cxt_ingress_ready +); +/*------------------------------------------- Input/Output Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Macros Definition : Begin ---------------------------------------*/ +`define HEADER_LOCAL_QPN_OFFSET 55:32 +`define HEADER_REMOTE_QPN_OFFSET 23:0 +`define HEADER_NET_OPCODE_OFFSET 28:24 +`define HEADER_SERVICE_TYPE_OFFSET 31:29 +`define HEADER_PKT_LENGTH_OFFSET 383:368 +`define HEADER_PAYLOAD_ADDR_OFFSET 367:352 +`define HEADER_DMAC_OFFSET 239:192 +`define HEADER_SMAC_OFFSET 287:240 +`define HEADER_DIP_OFFSET 319:288 +`define HEADER_SIP_OFFSET 351:320 +/*------------------------------------------- Local Macros Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Variables Definition : Begin ------------------------------------*/ +reg [`PKT_META_BUS_WIDTH : 0] pkt_header_bus; + +wire [23:0] PktHeader_local_qpn; +wire [23:0] PktHeader_remote_qpn; +wire [4:0] PktHeader_net_opcode; +wire [2:0] PktHeader_service_type; +wire [47:0] PktHeader_dmac; +wire [47:0] PktHeader_smac; +wire [31:0] PktHeader_dip; +wire [31:0] PktHeader_sip; +wire [31:0] PktHeader_pkt_length; + +wire [`INGRESS_COMMON_HEAD_WIDTH - 1 : 0] ingress_common_head; +wire [15:0] ingress_slot_count; +/*------------------------------------------- Local Variables Definition : End --------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : Begin ---------------------------------------*/ +/*------------------------------------------- Submodules Instatiation : End -----------------------------------------*/ + +/*------------------------------------------- State Machine Definition : Begin --------------------------------------*/ +reg [2:0] cur_state; +reg [2:0] next_state; + +parameter [2:0] IDLE_s = 3'd1, + JUDGE_s = 3'd2, + FETCH_CXT_s = 3'd3; + +always @(posedge clk or posedge rst) begin + if(rst) begin + cur_state <= IDLE_s; + end + else begin + cur_state <= next_state; + end +end + +always @(*) begin + case(cur_state) + IDLE_s: if(ingress_pkt_valid) begin + next_state = JUDGE_s; + end + else begin + next_state = IDLE_s; + end + JUDGE_s: next_state = FETCH_CXT_s; + FETCH_CXT_s: if(fetch_cxt_ingress_valid && fetch_cxt_ingress_ready) begin + next_state = IDLE_s; + end + else begin + next_state = FETCH_CXT_s; + end + default: next_state = IDLE_s; + endcase +end +/*------------------------------------------- State Machine Definition : End ----------------------------------------*/ + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ +wire [`QP_NUM_LOG - 1 : 0] qpn_data; +assign qpn_data = PktHeader_local_qpn; + +wire [`MAX_QP_NUM_LOG - 1 : 0] queue_index; +assign queue_index = {'d0, qpn_data[`QP_NUM_LOG - 1 : 0]}; + +//-- pkt_header_bus -- +always @(posedge clk or posedge rst) begin + if(rst) begin + pkt_header_bus <= 'd0; + end + else if(cur_state == IDLE_s && ingress_pkt_valid) begin + pkt_header_bus <= ingress_pkt_head; + end + else begin + pkt_header_bus <= pkt_header_bus; + end +end + +//-- PktHeader_local_qpn -- +//-- PktHeader_remote_qpn -- +//-- PktHeader_net_opcode -- +//-- PktHeader_service_type -- +//-- PktHeader_dmac -- +//-- PktHeader_smac -- +//-- PktHeader_dip -- +//-- PktHeader_sip -- +//-- PktHeader_immediate -- +//-- PktHeader_rkey -- +//-- PktHeader_raddr -- +//-- PktHeader_pkt_length -- +assign PktHeader_local_qpn = pkt_header_bus[`HEADER_LOCAL_QPN_OFFSET]; +assign PktHeader_remote_qpn = pkt_header_bus[`HEADER_REMOTE_QPN_OFFSET]; +assign PktHeader_net_opcode = pkt_header_bus[`HEADER_NET_OPCODE_OFFSET]; +assign PktHeader_service_type = pkt_header_bus[`HEADER_SERVICE_TYPE_OFFSET]; +assign PktHeader_dmac = pkt_header_bus[`HEADER_DMAC_OFFSET]; +assign PktHeader_smac = pkt_header_bus[`HEADER_SMAC_OFFSET]; +assign PktHeader_dip = pkt_header_bus[`HEADER_DIP_OFFSET]; +assign PktHeader_sip = pkt_header_bus[`HEADER_SIP_OFFSET]; +assign PktHeader_pkt_length = pkt_header_bus[`HEADER_PKT_LENGTH_OFFSET]; + +//-- ingress_common_head -- +//-- ingress_slot_count -- +assign ingress_common_head = {`NO_BYPASS, ingress_slot_count, queue_index}; +assign ingress_slot_count = 'd1; + +//-- fetch_cxt_ingress_valid -- +//-- fetch_cxt_ingress_head -- +//-- fetch_cxt_ingress_data -- +//-- fetch_cxt_ingress_start -- +//-- fetch_cxt_ingress_last -- +assign fetch_cxt_ingress_valid = (cur_state == FETCH_CXT_s) ? 'd1 : 'd0; +assign fetch_cxt_ingress_head = (cur_state == FETCH_CXT_s) ? {qpn_data[`QP_NUM_LOG - 1 : 0], `CXT_READ, ingress_common_head} : 'd0; +assign fetch_cxt_ingress_data = (cur_state == FETCH_CXT_s) ? pkt_header_bus : 'd0; +assign fetch_cxt_ingress_start = (cur_state == FETCH_CXT_s) ? 'd1 : 'd0; +assign fetch_cxt_ingress_last = (cur_state == FETCH_CXT_s) ? 'd1 : 'd0; + +//-- ingress_pkt_ready -- +assign ingress_pkt_ready = (cur_state == IDLE_s) ? 'd1 : 'd0; +/*------------------------------------------- Variables Decode : End ----------------------------------------------***/ + +/*------------------------------------------- Local Macros Undef : Begin --------------------------------------------*/ +`undef HEADER_LOCAL_QPN_OFFSET +`undef HEADER_REMOTE_QPN_OFFSET +`undef HEADER_NET_OPCODE_OFFSET +`undef HEADER_SERVICE_TYPE_OFFSET +`undef HEADER_PKT_LENGTH_OFFSET +`undef HEADER_DMAC_OFFSET +`undef HEADER_SMAC_OFFSET +`undef HEADER_DIP_OFFSET +`undef HEADER_SIP_OFFSET +/*------------------------------------------- Local Macros Undef : End ----------------------------------------------*/ + +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/RPCSubsystem/RDMACore/RequesterCore/RespRecvCore/RespRecvCore_Thread_2.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/RPCSubsystem/RDMACore/RequesterCore/RespRecvCore/RespRecvCore_Thread_2.v new file mode 100644 index 0000000000000000000000000000000000000000..4e8a47f3a76a69a53fb5585065bfd56c84bb5f76 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/RPCSubsystem/RDMACore/RequesterCore/RespRecvCore/RespRecvCore_Thread_2.v @@ -0,0 +1,608 @@ + +/*------------------------------------------- Module Description : Begin ---------------------------------------------- +Name: RespRecvCore_Thread_2 +Author: YangFan +Function: 1.Fetch MR. +--------------------------------------------- Module Decription : End -----------------------------------------------*/ + +/*------------------------------------------- Timescale Definition : Begin ------------------------------------------*/ +`timescale 1ns / 1ps +/*------------------------------------------- Timescale Definition : End --------------------------------------------*/ + +/*------------------------------------------- Included Files : Begin ------------------------------------------------*/ +`include "protocol_engine_def.vh" +/*------------------------------------------- Included Files : End --------------------------------------------------*/ + +/*------------------------------------------- Input/Output Definition : Begin ---------------------------------------*/ +module RespRecvCore_Thread_2 +#( + parameter INGRESS_MR_HEAD_WIDTH = 128, + parameter INGRESS_MR_DATA_WIDTH = 256, + parameter EGRESS_CXT_HEAD_WIDTH = 128, + parameter EGRESS_CXT_DATA_WIDTH = 256 +) +( + input wire clk, + input wire rst, + +//Interface with OoOStation(For CxtMgt) + input wire fetch_cxt_egress_valid, + input wire [`RX_RESP_OOO_CXT_EGRESS_HEAD_WIDTH - 1 : 0] fetch_cxt_egress_head, + input wire [`RX_RESP_OOO_CXT_EGRESS_DATA_WIDTH - 1 : 0] fetch_cxt_egress_data, + input wire fetch_cxt_egress_start, + input wire fetch_cxt_egress_last, + output wire fetch_cxt_egress_ready, + +//Interface with OoOStation(For MRMgt) + output wire fetch_mr_ingress_valid, + output wire [`RX_RESP_OOO_MR_INGRESS_HEAD_WIDTH - 1 : 0] fetch_mr_ingress_head, + output wire [`RX_RESP_OOO_MR_INGRESS_DATA_WIDTH - 1 : 0] fetch_mr_ingress_data, + output wire fetch_mr_ingress_start, + output wire fetch_mr_ingress_last, + input wire fetch_mr_ingress_ready, + +//Interface with WQEBuffer + output wire dequeue_req_valid, + output wire [`MAX_QP_NUM_LOG + `MAX_OOO_SLOT_NUM_LOG - 1 : 0] dequeue_req_head, + input wire dequeue_req_ready, + + input wire dequeue_resp_valid, + input wire [`MAX_QP_NUM_LOG + `MAX_OOO_SLOT_NUM_LOG - 1 : 0] dequeue_resp_head, + input wire dequeue_resp_start, + input wire dequeue_resp_last, + output wire dequeue_resp_ready, + input wire [`RC_WQE_BUFFER_SLOT_WIDTH - 1 : 0] dequeue_resp_data, + +//Interface with CompletionQueueMgt + output wire cq_req_valid, + output wire [`CQ_REQ_HEAD_WIDTH - 1 : 0] cq_req_head, + input wire cq_req_ready, + + input wire cq_resp_valid, + input wire [`CQ_RESP_HEAD_WIDTH - 1 : 0] cq_resp_head, + output wire cq_resp_ready, + +//Interface with EventQueueMgt + output wire eq_req_valid, + output wire [`EQ_REQ_HEAD_WIDTH - 1 : 0] eq_req_head, + input wire eq_req_ready, + + input wire eq_resp_valid, + input wire [`EQ_RESP_HEAD_WIDTH - 1 : 0] eq_resp_head, + output wire eq_resp_ready +); +/*------------------------------------------- Input/Output Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Macros Definition : Begin ---------------------------------------*/ +`define SUB_WQE_LOCAL_QPN_OFFSET 23:0 +`define SUB_WQE_VERBS_OPCODE_OFFSET 28:24 +`define SUB_WQE_REMOTE_QPN_OFFSET 55:32 +`define SUB_WQE_NET_OPCODE_OFFSET 60:56 +`define SUB_WQE_SERVICE_TYPE_OFFSET 63:61 +`define SUB_WQE_DLID_OPCODE_OFFSET 79:64 +`define SUB_WQE_PKT_LENGTH_OFFSET 95:80 +`define SUB_WQE_LKEY_OFFSET 127:96 +`define SUB_WQE_LADDR_OFFSET 191:128 +`define SUB_WQE_MSG_LENGTH_OFFSET 223:192 +`define SUB_WQE_ORI_WQE_ADDR_OFFSET 247:224 + +`define HEADER_LOCAL_QPN_OFFSET 55:32 +`define HEADER_REMOTE_QPN_OFFSET 23:0 +`define HEADER_NET_OPCODE_OFFSET 28:24 +`define HEADER_SERVICE_TYPE_OFFSET 31:29 +`define HEADER_PKT_LENGTH_OFFSET 383:368 +`define HEADER_PAYLOAD_ADDR_OFFSET 383:368 +`define HEADER_PKT_START_ADDR_OFFSET 367:352 +`define HEADER_DMAC_OFFSET 239:192 +`define HEADER_SMAC_OFFSET 287:240 +`define HEADER_DIP_OFFSET 319:288 +`define HEADER_SIP_OFFSET 351:320 +/*------------------------------------------- Local Macros Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Variables Definition : Begin ------------------------------------*/ +reg [`WQE_BUFFER_SLOT_WIDTH - 1 : 0] wqe_meta_bus; +reg [`RX_RESP_OOO_CXT_EGRESS_HEAD_WIDTH - 1 : 0] cxt_head_bus; +reg [`RX_RESP_OOO_CXT_EGRESS_DATA_WIDTH - 1 : 0] pkt_header_bus; + +wire [23:0] WQE_local_qpn; +wire [4:0] WQE_verbs_opcode; +wire [23:0] WQE_remote_qpn; +wire [4:0] WQE_net_opcode; +wire [2:0] WQE_service_type; +wire [15:0] WQE_dlid; +wire [15:0] WQE_pkt_length; +wire [31:0] WQE_lkey; +wire [63:0] WQE_laddr; +wire [31:0] WQE_msg_length; +wire [23:0] WQE_ori_wqe_addr; + +wire [31:0] Cxt_qp_pd; +wire [23:0] Cxt_cqn; +wire [31:0] Cxt_cq_lkey; +wire [31:0] Cxt_cq_pd; +wire [31:0] Cxt_cq_length; +wire [31:0] Cxt_eqn; +wire [31:0] Cxt_eq_lkey; +wire [31:0] Cxt_eq_pd; +wire [31:0] Cxt_eq_length; + +wire [31:0] PktHeader_pkt_start_addr; +wire [23:0] PktHeader_local_qpn; + +wire [31:0] mr_length; +wire [63:0] mr_laddr; +wire [31:0] mr_lkey; +wire [31:0] mr_pd; + +wire [31:0] mr_flags; +reg [3:0] mr_flag_sw_owns; +reg mr_flag_absolute_addr; +reg mr_flag_relative_addr; +reg mr_flag_mio; +reg mr_flag_bind_enable; +reg mr_flag_physical; +reg mr_flag_region; +reg mr_flag_on_demand; +reg mr_flag_zero_based; +reg mr_flag_mw_bind; +reg mr_flag_remote_read; +reg mr_flag_remote_write; +reg mr_flag_local_write; + +reg [63:0] cq_offset; +reg [63:0] eq_offset; + +wire [`MAX_QP_NUM_LOG - 1 : 0] queue_index; +/*------------------------------------------- Local Variables Definition : End --------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : Begin ---------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : End -----------------------------------------*/ + +/*------------------------------------------- State Machine Definition : Begin --------------------------------------*/ +reg [3:0] cur_state; +reg [3:0] next_state; + +parameter [3:0] IDLE_s = 4'd1, + DEQUEUE_REQ_s = 4'd2, + DEQUEUE_RESP_s = 4'd3, + JUDGE_s = 4'd4, + CQ_REQ_s = 4'd5, + CQ_RESP_s = 4'd6, + EQ_REQ_s = 4'd7, + EQ_RESP_s = 4'd8, + MR_FOR_DATA_s = 4'd9, + MR_FOR_CQ_s = 4'd10, + MR_FOR_EQ_s = 4'd11; + +always @(posedge clk or posedge rst) begin + if (rst) begin + cur_state <= IDLE_s; + end + else begin + cur_state <= next_state; + end +end + +always @(*) begin + case(cur_state) + IDLE_s: if(fetch_cxt_egress_valid) begin + next_state = DEQUEUE_REQ_s; + end + else begin + next_state = IDLE_s; + end + DEQUEUE_REQ_s: if(dequeue_req_valid && dequeue_req_ready) begin + next_state = DEQUEUE_RESP_s; + end + else begin + next_state = DEQUEUE_RESP_s; + end + DEQUEUE_RESP_s: if(dequeue_resp_valid) begin + next_state = JUDGE_s; + end + else begin + next_state = DEQUEUE_RESP_s; + end + JUDGE_s: if(WQE_net_opcode == `SEND_LAST || WQE_net_opcode == `SEND_LAST_WITH_IMM || WQE_net_opcode == `SEND_ONLY || WQE_net_opcode == `SEND_ONLY_WITH_IMM || + WQE_net_opcode == `RDMA_WRITE_LAST || WQE_net_opcode == `RDMA_WRITE_LAST_WITH_IMM || WQE_net_opcode == `RDMA_WRITE_ONLY || WQE_net_opcode == `RDMA_WRITE_ONLY_WITH_IMM) begin + next_state = CQ_REQ_s; + end + else if(WQE_net_opcode == `SEND_FIRST || WQE_net_opcode == `SEND_MIDDLE || WQE_net_opcode == `RDMA_WRITE_FIRST || WQE_net_opcode == `RDMA_WRITE_MIDDLE) begin + next_state = IDLE_s; + end + else if(WQE_net_opcode == `RDMA_READ_REQUEST_FIRST || WQE_net_opcode == `RDMA_READ_REQUEST_MIDDLE || WQE_net_opcode == `RDMA_READ_REQUEST_LAST || WQE_net_opcode == `RDMA_READ_REQUEST_ONLY) begin + next_state = MR_FOR_DATA_s; + end + else begin + next_state = IDLE_s; + end + CQ_REQ_s: if(cq_req_valid && cq_req_ready) begin + next_state = CQ_RESP_s; + end + else begin + next_state = CQ_REQ_s; + end + CQ_RESP_s: if(cq_resp_valid && cq_resp_ready) begin + next_state = MR_FOR_CQ_s; + end + else begin + next_state = CQ_RESP_s; + end + EQ_REQ_s: if(eq_req_valid && eq_req_ready) begin + next_state = EQ_RESP_s; + end + else begin + next_state = EQ_REQ_s; + end + EQ_RESP_s: if(eq_resp_valid && eq_resp_ready) begin + next_state = MR_FOR_EQ_s; + end + else begin + next_state = EQ_RESP_s; + end + MR_FOR_DATA_s: if(fetch_mr_ingress_valid && fetch_mr_ingress_ready) begin + if(WQE_net_opcode == `RDMA_READ_REQUEST_LAST || WQE_net_opcode == `RDMA_READ_REQUEST_ONLY) begin + next_state = CQ_REQ_s; + end + else begin + next_state = IDLE_s; + end + end + else begin + next_state = MR_FOR_DATA_s; + end + MR_FOR_CQ_s: if(fetch_mr_ingress_valid && fetch_mr_ingress_ready) begin + next_state = IDLE_s; + end + else begin + next_state = MR_FOR_CQ_s; + end + MR_FOR_EQ_s: if(fetch_mr_ingress_valid && fetch_mr_ingress_ready) begin + next_state = IDLE_s; + end + else begin + next_state = MR_FOR_EQ_s; + end + default: next_state = IDLE_s; + endcase +end +/*------------------------------------------- State Machine Definition : End ----------------------------------------*/ + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ +//-- wqe_meta_bus -- +always @(posedge clk or posedge rst) begin + if(rst) begin + wqe_meta_bus <= 'd0; + end + else if(cur_state == IDLE_s) begin + wqe_meta_bus <= 'd0; + end + else if(cur_state == DEQUEUE_RESP_s && dequeue_resp_valid) begin + wqe_meta_bus <= dequeue_resp_data; + end + else begin + wqe_meta_bus <= wqe_meta_bus; + end +end + +//-- cxt_head_bus -- +//-- pkt_header_bus -- +always @(posedge clk or posedge rst) begin + if (rst) begin + cxt_head_bus <= 'd0; + pkt_header_bus <= 'd0; + end + else if (cur_state == IDLE_s && fetch_cxt_egress_valid) begin + cxt_head_bus <= fetch_cxt_egress_head[`RX_RESP_OOO_CXT_EGRESS_HEAD_WIDTH - 1 : `EGRESS_COMMON_HEAD_WIDTH]; + pkt_header_bus <= fetch_cxt_egress_data; + end + else begin + cxt_head_bus <= cxt_head_bus; + pkt_header_bus <= pkt_header_bus; + end +end + +//-- WQE_local_qpn -- +//-- WQE_verbs_opcode -- +//-- WQE_remote_qpn -- +//-- WQE_net_opcode -- +//-- WQE_service_type -- +//-- WQE_dlid -- +//-- WQE_pkt_length -- +//-- WQE_lkey -- +//-- WQE_laddr -- +//-- WQE_msg_length -- +//-- WQE_ori_wqe_addr -- +assign WQE_local_qpn = wqe_meta_bus[`SUB_WQE_LOCAL_QPN_OFFSET]; +assign WQE_verbs_opcode = wqe_meta_bus[`SUB_WQE_VERBS_OPCODE_OFFSET]; +assign WQE_remote_qpn = wqe_meta_bus[`SUB_WQE_REMOTE_QPN_OFFSET]; +assign WQE_net_opcode = wqe_meta_bus[`SUB_WQE_NET_OPCODE_OFFSET]; +assign WQE_service_type = wqe_meta_bus[`SUB_WQE_SERVICE_TYPE_OFFSET]; +assign WQE_dlid = wqe_meta_bus[`SUB_WQE_DLID_OPCODE_OFFSET]; +assign WQE_pkt_length = wqe_meta_bus[`SUB_WQE_PKT_LENGTH_OFFSET]; +assign WQE_lkey = wqe_meta_bus[`SUB_WQE_LKEY_OFFSET]; +assign WQE_laddr = wqe_meta_bus[`SUB_WQE_LADDR_OFFSET]; +assign WQE_msg_length = wqe_meta_bus[`SUB_WQE_MSG_LENGTH_OFFSET]; +assign WQE_ori_wqe_addr = wqe_meta_bus[`SUB_WQE_ORI_WQE_ADDR_OFFSET]; + +//-- PktHeader_pkt_start_addr -- +//-- PktHeader_local_qpn -- +assign PktHeader_pkt_start_addr = pkt_header_bus[`HEADER_PKT_START_ADDR_OFFSET]; +assign PktHeader_local_qpn = pkt_header_bus[`HEADER_LOCAL_QPN_OFFSET]; + +//-- Cxt_qp_pd -- +//-- Cxt_cqn -- +//-- Cxt_cq_lkey -- +//-- Cxt_cq_pd -- +//-- Cxt_cq_length -- +//-- Cxt_eqn -- +//-- Cxt_eq_lkey -- +//-- Cxt_eq_pd -- +//-- Cxt_eq_length -- +assign Cxt_qp_pd = cxt_head_bus[`QP_CXT_PD_OFFSET]; +assign Cxt_cqn = cxt_head_bus[`QP_CXT_CQN_RCV_OFFSET]; +assign Cxt_cq_lkey = cxt_head_bus[`CQ_CXT_LKEY_OFFSET]; +assign Cxt_cq_pd = cxt_head_bus[`CQ_CXT_PD_OFFSET]; +assign Cxt_cq_length = (1 << cxt_head_bus[`CQ_CXT_LOG_SIZE_OFFSET]) * `CQE_LENGTH; +assign Cxt_eqn = cxt_head_bus[`CQ_CXT_COMP_EQN_OFFSET]; +assign Cxt_eq_lkey = cxt_head_bus[`EQ_CXT_LKEY_OFFSET]; +assign Cxt_eq_pd = cxt_head_bus[`EQ_CXT_PD_OFFSET]; +assign Cxt_eq_length = (1 << cxt_head_bus[`EQ_CXT_LOG_SIZE_OFFSET]) * `EVENT_LENGTH; + +//-- queue_index -- +assign queue_index = PktHeader_local_qpn[`MAX_QP_NUM_LOG - 1 : 0]; + +//-- dequeue_req_valid -- +//-- dequeue_req_head -- +assign dequeue_req_valid = (cur_state == DEQUEUE_REQ_s) ? 'd1 : 'd0; +assign dequeue_req_head = (cur_state == DEQUEUE_REQ_s) ? {'d1, queue_index} : 'd0; + +//-- dequeue_resp_ready -- +assign dequeue_resp_ready = (cur_state == DEQUEUE_RESP_s) ? 'd1 : 'd0; + +//-- cq_req_valid -- +//-- cq_req_head -- +assign cq_req_valid = (cur_state == CQ_REQ_s) ? 'd1 : 'd0; +assign cq_req_head = (cur_state == CQ_REQ_s) ? {Cxt_cq_length, 8'd0, Cxt_cqn} : 'd0; + +//-- cq_resp_ready -- +assign cq_resp_ready = (cur_state == CQ_RESP_s) ? 'd1 : 'd0; + +//-- eq_req_valid -- +//-- eq_req_head -- +assign eq_req_valid = (cur_state == EQ_REQ_s) ? 'd1 : 'd0; +assign eq_req_head = (cur_state == EQ_REQ_s) ? {Cxt_eq_length, 8'd0, Cxt_eqn} : 'd0; + +//-- eq_resp_ready -- +assign eq_resp_ready = (cur_state == EQ_RESP_s) ? 'd1 : 'd0; + +//-- fetch_cxt_egress_ready -- +assign fetch_cxt_egress_ready = (cur_state == IDLE_s) ? 'd1 : 'd0; + +//-- cq_offset -- +always @(posedge clk or posedge rst) begin + if (rst) begin + cq_offset <= 'd0; + end + else if (cur_state == CQ_RESP_s && cq_resp_valid) begin + cq_offset <= cq_resp_head[95:32]; + end + else begin + cq_offset <= cq_offset; + end +end + +//-- eq_offset -- +always @(posedge clk or posedge rst) begin + if (rst) begin + eq_offset <= 'd0; + end + else if (cur_state == EQ_RESP_s && eq_resp_valid) begin + eq_offset <= eq_resp_head[95:32]; + end + else begin + eq_offset <= eq_offset; + end +end +/********************************************************* MR Request Decode : Begin ***********************************************************/ +wire [`INGRESS_COMMON_HEAD_WIDTH - 1 : 0] ingress_common_head; +wire [`MAX_OOO_SLOT_NUM_LOG - 1 :0] ingress_slot_count; + +//-- ingress_slot_count -- +//-- ingress_common_head -- +assign ingress_slot_count = (cur_state == MR_FOR_DATA_s) ? 'd1 : + (cur_state == MR_FOR_CQ_s) ? 'd1 : + (cur_state == MR_FOR_EQ_s) ? 'd1 : 'd0; + +assign ingress_common_head = (cur_state == MR_FOR_DATA_s) ? {`NO_BYPASS, ingress_slot_count, queue_index} : + (cur_state == MR_FOR_CQ_s) ? {`NO_BYPASS, ingress_slot_count, queue_index} : + (cur_state == MR_FOR_EQ_s) ? {`NO_BYPASS, ingress_slot_count, queue_index} : 'd0; + +//-- fetch_mr_ingress_valid -- +assign fetch_mr_ingress_valid = (cur_state == MR_FOR_DATA_s) ? 'd1 : + (cur_state == MR_FOR_CQ_s) ? 'd1 : + (cur_state == MR_FOR_EQ_s) ? 'd1 : 'd0; + +//-- fetch_mr_ingress_head -- +assign fetch_mr_ingress_head = (cur_state == MR_FOR_DATA_s) ? {mr_length, mr_laddr, mr_lkey, mr_pd, mr_flags, ingress_common_head} : + (cur_state == MR_FOR_CQ_s) ? {mr_length, mr_laddr, mr_lkey, mr_pd, mr_flags, ingress_common_head} : + (cur_state == MR_FOR_EQ_s) ? {mr_length, mr_laddr, mr_lkey, mr_pd, mr_flags, ingress_common_head} : 'd0; + +//-- fetch_mr_ingress_data -- +assign fetch_mr_ingress_data = (cur_state == MR_FOR_DATA_s) ? {16'd0, PktHeader_pkt_start_addr, 32'd0, 16'd0, WQE_pkt_length, WQE_msg_length, 3'd0, WQE_net_opcode, WQE_remote_qpn, 8'd0, WQE_local_qpn} : + (cur_state == MR_FOR_CQ_s) ? {32'd0, 8'd0, WQE_ori_wqe_addr, WQE_dlid, WQE_msg_length, 3'd0, `GEN_CQE, WQE_remote_qpn, 3'd0, WQE_verbs_opcode, WQE_local_qpn} : + (cur_state == MR_FOR_EQ_s) ? {32'd0, 32'd0, 16'd0, 16'd0, 32'd0, 8'd0, WQE_remote_qpn, 8'd0, WQE_local_qpn} : 'd0; + + +//-- fetch_mr_ingress_start -- +assign fetch_mr_ingress_start = (cur_state == MR_FOR_DATA_s) ? 'd1 : + (cur_state == MR_FOR_CQ_s) ? 'd1 : + (cur_state == MR_FOR_EQ_s) ? 'd1 : 'd0; + +//-- fetch_mr_ingress_last -- +assign fetch_mr_ingress_last = (cur_state == MR_FOR_DATA_s) ? 'd1 : + (cur_state == MR_FOR_CQ_s) ? 'd1 : + (cur_state == MR_FOR_EQ_s) ? 'd1 : 'd0; + +//-- mr_length -- +assign mr_length = (cur_state == MR_FOR_DATA_s) ? WQE_pkt_length : + (cur_state == MR_FOR_CQ_s) ? `CQE_LENGTH : + (cur_state == MR_FOR_EQ_s) ? `EVENT_LENGTH : 'd0; + +//-- mr_laddr -- +assign mr_laddr = (cur_state == MR_FOR_DATA_s) ? WQE_laddr : + (cur_state == MR_FOR_CQ_s) ? cq_offset : + (cur_state == MR_FOR_EQ_s) ? eq_offset : 'd0; + +//-- mr_lkey -- +assign mr_lkey = (cur_state == MR_FOR_DATA_s) ? WQE_lkey : + (cur_state == MR_FOR_CQ_s) ? Cxt_cq_lkey : + (cur_state == MR_FOR_EQ_s) ? Cxt_eq_lkey : 'd0;; + +//-- mr_pd -- +assign mr_pd = (cur_state == MR_FOR_DATA_s) ? Cxt_qp_pd : + (cur_state == MR_FOR_CQ_s) ? Cxt_cq_pd : + (cur_state == MR_FOR_EQ_s) ? Cxt_eq_pd : 'd0; + +//-- mr_flag_sw_owns -- +//-- mr_flag_absolute_addr -- +//-- mr_flag_relative_addr -- +//-- mr_flag_mio -- +//-- mr_flag_bind_enable -- +//-- mr_flag_physical -- +//-- mr_flag_on_demand -- +//-- mr_flag_zero_based -- +//-- mr_flag_mw_bind -- +//-- mr_remote_read -- +//-- mr_remote_write -- +//-- mr_local_write -- +always @(*) begin + if(rst) begin + mr_flag_sw_owns = 'd0; + mr_flag_absolute_addr = 'd0; + mr_flag_relative_addr = 'd0; + mr_flag_mio = 'd0; + mr_flag_bind_enable = 'd0; + mr_flag_physical = 'd0; + mr_flag_region = 'd0; + mr_flag_on_demand = 'd0; + mr_flag_zero_based = 'd0; + mr_flag_mw_bind = 'd0; + mr_flag_remote_read = 'd0; + mr_flag_remote_write = 'd0; + mr_flag_local_write = 'd0; + end + else if(cur_state == MR_FOR_DATA_s) begin + mr_flag_sw_owns = 'd0; + mr_flag_absolute_addr = 'd1; + mr_flag_relative_addr = 'd0; + mr_flag_mio = 'd0; + mr_flag_bind_enable = 'd0; + mr_flag_physical = 'd0; + mr_flag_region = 'd0; + mr_flag_on_demand = 'd0; + mr_flag_zero_based = 'd0; + mr_flag_mw_bind = 'd0; + mr_flag_remote_read = 'd0; + mr_flag_remote_write = 'd0; + mr_flag_local_write = 'd1; + end + else if(cur_state == MR_FOR_CQ_s) begin + mr_flag_sw_owns = 'd0; + mr_flag_absolute_addr = 'd0; + mr_flag_relative_addr = 'd1; + mr_flag_mio = 'd0; + mr_flag_bind_enable = 'd0; + mr_flag_physical = 'd0; + mr_flag_region = 'd0; + mr_flag_on_demand = 'd0; + mr_flag_zero_based = 'd0; + mr_flag_mw_bind = 'd0; + mr_flag_remote_read = 'd0; + mr_flag_remote_write = 'd0; + mr_flag_local_write = 'd1; + end + else if(cur_state == MR_FOR_EQ_s) begin + mr_flag_sw_owns = 'd0; + mr_flag_absolute_addr = 'd0; + mr_flag_relative_addr = 'd1; + mr_flag_mio = 'd0; + mr_flag_bind_enable = 'd0; + mr_flag_physical = 'd0; + mr_flag_region = 'd0; + mr_flag_on_demand = 'd0; + mr_flag_zero_based = 'd0; + mr_flag_mw_bind = 'd0; + mr_flag_remote_read = 'd0; + mr_flag_remote_write = 'd0; + mr_flag_local_write = 'd1; + end + else begin + mr_flag_sw_owns = 'd0; + mr_flag_absolute_addr = 'd0; + mr_flag_relative_addr = 'd1; + mr_flag_mio = 'd0; + mr_flag_bind_enable = 'd0; + mr_flag_physical = 'd0; + mr_flag_region = 'd0; + mr_flag_on_demand = 'd0; + mr_flag_zero_based = 'd0; + mr_flag_mw_bind = 'd0; + mr_flag_remote_read = 'd0; + mr_flag_remote_write = 'd0; + mr_flag_local_write = 'd0; + end +end + +//-- mr_flags -- +assign mr_flags = (cur_state == MR_FOR_DATA_s || cur_state == MR_FOR_DATA_s || cur_state == MR_FOR_CQ_s || cur_state == MR_FOR_EQ_s) ? + { + mr_flag_sw_owns, + mr_flag_absolute_addr, + mr_flag_relative_addr, + 8'd0, + mr_flag_mio, + 1'd0, + mr_flag_bind_enable, + 5'd0, + mr_flag_physical, + mr_flag_region, + 1'd0, + mr_flag_on_demand, + mr_flag_zero_based, + mr_flag_mw_bind, + mr_flag_remote_read, + mr_flag_remote_write, + mr_flag_local_write + } : 'd0; +/********************************************************* MR Request Decode : End *************************************************************/ +/*------------------------------------------- Variables Decode : End ----------------------------------------------***/ + +/*------------------------------------------- Local Macros Undef : Begin --------------------------------------------*/ +`undef SUB_WQE_LOCAL_QPN_OFFSET +`undef SUB_WQE_VERBS_OPCODE_OFFSET +`undef SUB_WQE_REMOTE_QPN_OFFSET +`undef SUB_WQE_NET_OPCODE_OFFSET +`undef SUB_WQE_SERVICE_TYPE_OFFSET +`undef SUB_WQE_DLID_OPCODE_OFFSET +`undef SUB_WQE_PKT_LENGTH_OFFSET +`undef SUB_WQE_LKEY_OFFSET +`undef SUB_WQE_LADDR_OFFSET +`undef SUB_WQE_MSG_LENGTH_OFFSET +`undef SUB_WQE_ORI_WQE_ADDR_OFFSET + +`undef HEADER_LOCAL_QPN_OFFSET +`undef HEADER_REMOTE_QPN_OFFSET +`undef HEADER_NET_OPCODE_OFFSET +`undef HEADER_SERVICE_TYPE_OFFSET +`undef HEADER_PKT_LENGTH_OFFSET +`undef HEADER_PAYLOAD_ADDR_OFFSET +`undef HEADER_PKT_START_ADDR_OFFSET +`undef HEADER_DMAC_OFFSET +`undef HEADER_SMAC_OFFSET +`undef HEADER_DIP_OFFSET +`undef HEADER_SIP_OFFSET +/*------------------------------------------- Local Macros Undef : End ----------------------------------------------*/ + +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/RPCSubsystem/RDMACore/RequesterCore/RespRecvCore/RespRecvCore_Thread_3.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/RPCSubsystem/RDMACore/RequesterCore/RespRecvCore/RespRecvCore_Thread_3.v new file mode 100644 index 0000000000000000000000000000000000000000..992d58a3b4e59e90744df222f5bb34a096d98456 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/RPCSubsystem/RDMACore/RequesterCore/RespRecvCore/RespRecvCore_Thread_3.v @@ -0,0 +1,403 @@ +/*------------------------------------------- Module Description : Begin ---------------------------------------------- +Name: RespRecvCore_Thread_3 +Author: YangFan +Function: 1.Scatter RDMA Read Response data. + 2.Generate Completion, Event and Interrupt. +--------------------------------------------- Module Decription : End -----------------------------------------------*/ + +/*------------------------------------------- Timescale Definition : Begin ------------------------------------------*/ +`timescale 1ns / 1ps +/*------------------------------------------- Timescale Definition : End --------------------------------------------*/ + +/*------------------------------------------- Included Files : Begin ------------------------------------------------*/ +`include "protocol_engine_def.vh" +/*------------------------------------------- Included Files : End --------------------------------------------------*/ + +/*------------------------------------------- Input/Output Definition : Begin ---------------------------------------*/ +module RespRecvCore_Thread_3 +#( + parameter EGRESS_MR_HEAD_WIDTH = 128, + parameter EGRESS_MR_DATA_WIDTH = 256 +) +( + input wire clk, + input wire rst, + +//Interface with OoOStation(For MRMgt) + input wire fetch_mr_egress_valid, + input wire [`RX_RESP_OOO_MR_EGRESS_HEAD_WIDTH - 1 : 0] fetch_mr_egress_head, + input wire [`RX_RESP_OOO_MR_EGRESS_DATA_WIDTH - 1 : 0] fetch_mr_egress_data, + input wire fetch_mr_egress_start, + input wire fetch_mr_egress_last, + output wire fetch_mr_egress_ready, + +//ScatterData Req Interface + output reg scatter_req_wen, + output reg [`DMA_LENGTH_WIDTH * 2 + `DMA_ADDR_WIDTH - 1 : 0] scatter_req_din, + input wire scatter_req_prog_full, + + output reg scatter_data_wen, + output reg [`DMA_DATA_WIDTH - 1 : 0] scatter_data_din, + input wire scatter_data_prog_full, + +//Interface with PacketBuffer + //Interface with Packet Buffer + output wire delete_req_valid, + output wire [`MAX_DB_SLOT_NUM_LOG * 2 - 1 : 0] delete_req_head, + input wire delete_req_ready, + + input wire delete_resp_valid, + input wire delete_resp_start, + input wire delete_resp_last, + input wire [`PACKET_BUFFER_SLOT_WIDTH - 1 : 0] delete_resp_data, + output wire delete_resp_ready +); +/*------------------------------------------- Input/Output Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Macros Definition : Begin ---------------------------------------*/ +`define META_BUS_LOCAL_QPN_OFFSET 23:0 +`define META_BUS_VERBS_OPCODE_OFFSET 28:24 +`define META_BUS_REMOTE_QPN_OFFSET 55:32 +`define META_BUS_NET_OPCODE_OFFSET 60:56 +`define META_BUS_MSG_LENGTH_OFFSET 95:64 +`define META_BUS_PKT_LENGTH_OFFSET 111:96 +`define META_BUS_DLID_OFFSET 127:112 +`define META_BUS_ORI_WQE_ADDR_OFFSET 159:128 +`define META_BUS_PKT_START_ADDR_OFFSET 175:160 + +/*------------------------------------------- Local Macros Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Variables Definition : Begin ------------------------------------*/ +reg [`MR_RESP_WIDTH - 1 : 0] mr_resp_bus; +reg [`PKT_META_BUS_WIDTH - 1 : 0] meta_bus; + +wire [23:0] meta_local_qpn; +wire [23:0] meta_remote_qpn; +wire [4:0] meta_verbs_opcode; +wire [4:0] meta_net_opcode; +wire [31:0] meta_msg_length; +wire [15:0] meta_pkt_length; +wire [15:0] meta_dlid; +wire [31:0] meta_wqe_addr; +wire [15:0] meta_pkt_start_addr; + +wire [3:0] mr_resp_state; +wire [3:0] mr_resp_valid_0; +wire [3:0] mr_resp_valid_1; +wire [31:0] mr_resp_size_0; +wire [31:0] mr_resp_size_1; +wire [63:0] mr_resp_phy_addr_0; +wire [63:0] mr_resp_phy_addr_1; + +wire [255:0] cqe_data; +reg [31:0] cqe_my_qpn; +reg [31:0] cqe_my_ee; +reg [31:0] cqe_rqpn; +reg [7:0] cqe_sl_ipok; +reg [7:0] cqe_g_mlpath; +reg [15:0] cqe_rlid; +reg [31:0] cqe_imm_etype_pkey_eec; +reg [31:0] cqe_byte_cnt; +reg [31:0] cqe_wqe; +reg [7:0] cqe_opcode; +reg [7:0] cqe_is_send; +reg [7:0] cqe_owner; +/*------------------------------------------- Local Variables Definition : End --------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : Begin ---------------------------------------*/ +/*------------------------------------------- Submodules Instatiation : End -----------------------------------------*/ + +/*------------------------------------------- State Machine Definition : Begin --------------------------------------*/ +reg [3:0] cur_state; +reg [3:0] next_state; + +parameter [3:0] IDLE_s = 4'd1, + JUDGE_s = 4'd2, + GET_PAYLOAD_s = 4'd3, + DMA_PAYLOAD_PAGE_0_REQ_s = 4'd4, + DMA_PAYLOAD_PAGE_1_REQ_s = 4'd5, + DMA_PAYLOAD_DATA_s = 4'd6, + DMA_CQE_s = 4'd7, + DMA_EVENT_s = 4'd8, + DMA_INT_s = 4'd9; + +always @(posedge clk or posedge rst) begin + if(rst) begin + cur_state <= IDLE_s; + end + else begin + cur_state <= next_state; + end +end + +always @(*) begin + case(cur_state) + IDLE_s: if(fetch_mr_egress_valid) begin + next_state = JUDGE_s; + end + else begin + next_state = IDLE_s; + end + JUDGE_s: if(meta_net_opcode == `RDMA_READ_REQUEST_FIRST || meta_net_opcode == `RDMA_READ_REQUEST_MIDDLE || meta_net_opcode == `RDMA_READ_REQUEST_LAST || + meta_net_opcode == `RDMA_READ_REQUEST_ONLY) begin + next_state = GET_PAYLOAD_s; + end + else if(meta_net_opcode == `GEN_CQE) begin + next_state = DMA_CQE_s; + end + else if(meta_net_opcode == `GEN_EVENT) begin + next_state = DMA_EVENT_s; + end + else begin + next_state = IDLE_s; + end + GET_PAYLOAD_s: if(delete_req_valid && delete_req_ready) begin + next_state = DMA_PAYLOAD_PAGE_0_REQ_s; + end + else begin + next_state = GET_PAYLOAD_s; + end + DMA_PAYLOAD_PAGE_0_REQ_s: if(!scatter_req_prog_full) begin + if(mr_resp_valid_1) begin + next_state = DMA_PAYLOAD_PAGE_1_REQ_s; + end + else begin + next_state = DMA_PAYLOAD_DATA_s; + end + end + else begin + next_state = DMA_PAYLOAD_PAGE_0_REQ_s; + end + DMA_PAYLOAD_PAGE_1_REQ_s: if(!scatter_req_prog_full) begin + next_state = DMA_PAYLOAD_DATA_s; + end + else begin + next_state = DMA_PAYLOAD_PAGE_1_REQ_s; + end + DMA_PAYLOAD_DATA_s: if(delete_resp_last && !scatter_data_prog_full) begin + next_state = IDLE_s; + end + else begin + next_state = DMA_PAYLOAD_DATA_s; + end + DMA_CQE_s: if(!scatter_req_prog_full && !scatter_data_prog_full) begin + next_state = IDLE_s; + end + else begin + next_state = DMA_CQE_s; + end + DMA_EVENT_s: if(!scatter_req_prog_full && !scatter_data_prog_full) begin + next_state = DMA_INT_s; + end + else begin + next_state = DMA_EVENT_s; + end + DMA_INT_s: if(!scatter_req_prog_full && !scatter_data_prog_full) begin + next_state = IDLE_s; + end + else begin + next_state = DMA_INT_s; + end + default: next_state = IDLE_s; + endcase +end +/*------------------------------------------- State Machine Definition : End ----------------------------------------*/ + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ +//-- meta_bus -- +//-- mr_resp_bus -- +always @(posedge clk or posedge rst) begin + if (rst) begin + meta_bus <= 'd0; + mr_resp_bus <= 'd0; + end + else if (cur_state == IDLE_s && fetch_mr_egress_valid) begin + meta_bus <= fetch_mr_egress_data; + mr_resp_bus <= fetch_mr_egress_head[`MR_RESP_WIDTH + `EGRESS_COMMON_HEAD_WIDTH - 1 : `EGRESS_COMMON_HEAD_WIDTH]; + end + else begin + meta_bus <= meta_bus; + mr_resp_bus <= mr_resp_bus; + end +end + +//-- meta_local_qpn -- +//-- meta_remote_qpn -- +//-- meta_verbs_opcode -- +//-- meta_net_opcode -- +//-- meta_msg_length -- +//-- meta_pkt_length -- +//-- meta_dlid -- +//-- meta_wqe_addr -- +//-- meta_pkt_start_addr -- +assign meta_local_qpn = meta_bus[`META_BUS_LOCAL_QPN_OFFSET]; +assign meta_remote_qpn = meta_bus[`META_BUS_REMOTE_QPN_OFFSET]; +assign meta_verbs_opcode = meta_bus[`META_BUS_VERBS_OPCODE_OFFSET]; +assign meta_net_opcode = meta_bus[`META_BUS_NET_OPCODE_OFFSET]; +assign meta_msg_length = meta_bus[`META_BUS_MSG_LENGTH_OFFSET]; +assign meta_pkt_length = meta_bus[`META_BUS_PKT_LENGTH_OFFSET]; +assign meta_dlid = meta_bus[`META_BUS_DLID_OFFSET]; +assign meta_wqe_addr = meta_bus[`META_BUS_ORI_WQE_ADDR_OFFSET]; +assign meta_pkt_start_addr = meta_bus[`META_BUS_PKT_START_ADDR_OFFSET]; + +//-- mr_resp_state -- +//-- mr_resp_valid_0 -- +//-- mr_resp_valid_1 -- +//-- mr_resp_size_0 -- +//-- mr_resp_size_1 -- +//-- mr_resp_phy_addr_0 -- +//-- mr_resp_phy_addr_1 -- +assign mr_resp_state = mr_resp_bus[`MR_RESP_STATE_OFFSET]; +assign mr_resp_valid_0 = mr_resp_bus[`MR_RESP_VALID_0_OFFSET]; +assign mr_resp_valid_1 = mr_resp_bus[`MR_RESP_VALID_1_OFFSET]; +assign mr_resp_size_0 = mr_resp_bus[`MR_RESP_SIZE_0_OFFSET]; +assign mr_resp_size_1 = mr_resp_bus[`MR_RESP_SIZE_1_OFFSET]; +assign mr_resp_phy_addr_0 = mr_resp_bus[`MR_RESP_ADDR_0_OFFSET]; +assign mr_resp_phy_addr_1 = mr_resp_bus[`MR_RESP_ADDR_1_OFFSET]; + +//-- fetch_mr_egress_ready -- +assign fetch_mr_egress_ready = (cur_state == IDLE_s) ? 'd1 : 'd0; + +//-- scatter_req_wen -- +//-- scatter_req_din -- +always @(posedge clk or posedge rst) begin + if(rst) begin + scatter_req_wen <= 'd0; + scatter_req_din <= 'd0; + end + else if(cur_state == IDLE_s) begin + scatter_req_wen <= 'd0; + scatter_req_din <= 'd0; + end + else if(cur_state == DMA_PAYLOAD_PAGE_0_REQ_s && !scatter_req_prog_full) begin + scatter_req_wen <= 'd1; + scatter_req_din <= {meta_pkt_length, mr_resp_size_0, mr_resp_phy_addr_0}; + end + else if(cur_state == DMA_PAYLOAD_PAGE_1_REQ_s && !scatter_req_prog_full) begin + scatter_req_wen <= 'd1; + scatter_req_din <= {meta_pkt_length, mr_resp_size_1, mr_resp_phy_addr_1}; + end + else if(cur_state == DMA_CQE_s && !scatter_req_prog_full && !scatter_req_prog_full) begin + scatter_req_wen <= 'd1; + scatter_req_din <= {`CQE_LENGTH, `CQE_LENGTH, mr_resp_phy_addr_0}; + end + else if(cur_state == DMA_EVENT_s && !scatter_req_prog_full && !scatter_req_prog_full) begin + scatter_req_wen <= 'd0; //TODO + scatter_req_din <= 'd0; + end + else if(cur_state == DMA_INT_s && !scatter_req_prog_full && !scatter_req_prog_full) begin + scatter_req_wen <= 'd0; + scatter_req_din <= 'd0; + end + else begin + scatter_req_wen <= 'd0; + scatter_req_din <= 'd0; + end +end + +//-- scatter_data_wen -- +//-- scatter_data_din -- +always @(posedge clk or posedge rst) begin + if(rst) begin + scatter_data_wen <= 'd0; + scatter_data_din <= 'd0; + end + else if(cur_state == DMA_PAYLOAD_DATA_s && !scatter_data_prog_full && delete_resp_valid) begin + scatter_data_wen <= 'd1; + scatter_data_din <= delete_resp_data; + end + else if(cur_state == DMA_CQE_s && !scatter_req_prog_full && !scatter_data_prog_full) begin + scatter_data_wen <= 'd1; + scatter_data_din <= cqe_data; + end + else if(cur_state == DMA_EVENT_s && !scatter_req_prog_full && !scatter_data_prog_full) begin + scatter_data_wen <= 'd0; //TODO + scatter_data_din <= 'd0; + end + else if(cur_state == DMA_INT_s && !scatter_req_prog_full && !scatter_data_prog_full) begin + scatter_data_wen <= 'd0; //TODO + scatter_data_din <= 'd0; + end + else begin + scatter_data_wen <= 'd0; + scatter_data_din <= 'd0; + end +end + +//-- delete_req_valid -- +//-- delete_req_head -- +assign delete_req_valid = (cur_state == GET_PAYLOAD_s) ? 'd1 : 'd0; +assign delete_req_head = (cur_state == GET_PAYLOAD_s) ? {(meta_pkt_length[5:0] ? (meta_pkt_length >> 6) + 1 : meta_pkt_length >> 6), meta_pkt_start_addr} : 'd0; + +//-- delete_resp_ready -- +assign delete_resp_ready = (cur_state == DMA_PAYLOAD_DATA_s && !scatter_data_prog_full) ? 'd1 : 'd0; + +/********************************************** CQE Field Gen : Begin ******************************************************/ +//-- cqe_my_qpn -- +//-- cqe_my_ee -- +//-- cqe_rqpn -- +//-- cqe_sl_ipok -- +//-- cqe_g_mlpath -- +//-- cqe_rlid -- +//-- cqe_imm_etype_pkey_eec -- +//-- cqe_byte_cnt -- +//-- cqe_wqe -- +//-- cqe_opcode -- +//-- cqe_is_send -- +//-- cqe_owner -- +always @(posedge clk or posedge rst) begin + if(rst) begin + cqe_my_qpn <= 'd0; + cqe_my_ee <= 'd0; + cqe_rqpn <= 'd0; + cqe_sl_ipok <= 'd0; + cqe_g_mlpath <= 'd0; + cqe_rlid <= 'd0; + cqe_imm_etype_pkey_eec <= 'd0; + cqe_byte_cnt <= 'd0; + cqe_wqe <= 'd0; + cqe_opcode <= 'd0; + cqe_is_send <= 'd0; + cqe_owner <= 'd0; + end + else if(cur_state == JUDGE_s && next_state == DMA_CQE_s) begin + cqe_my_qpn <= meta_local_qpn; + cqe_my_ee <= 'd0; + cqe_rqpn <= meta_remote_qpn; + cqe_sl_ipok <= 'd0; + cqe_g_mlpath <= 'd0; + cqe_rlid <= meta_dlid; + cqe_imm_etype_pkey_eec <= 'd0; + cqe_byte_cnt <= meta_msg_length; + cqe_wqe <= meta_wqe_addr; + cqe_opcode <= meta_verbs_opcode; + cqe_is_send <= 'd1; + cqe_owner <= `HGHCA_CQ_ENTRY_OWNER_HW; + end + else begin + cqe_my_qpn <= cqe_my_qpn; + cqe_my_ee <= cqe_my_ee; + cqe_rqpn <= cqe_rqpn; + cqe_sl_ipok <= cqe_sl_ipok; + cqe_g_mlpath <= cqe_g_mlpath; + cqe_rlid <= cqe_rlid; + cqe_imm_etype_pkey_eec <= cqe_imm_etype_pkey_eec; + cqe_byte_cnt <= cqe_byte_cnt; + cqe_wqe <= cqe_wqe; + cqe_opcode <= cqe_opcode; + cqe_is_send <= cqe_is_send; + cqe_owner <= cqe_owner; + end +end + +//-- cqe_data -- +assign cqe_data = (cur_state == DMA_CQE_s) ? { cqe_owner, 8'd0, cqe_is_send, cqe_opcode, cqe_wqe, cqe_byte_cnt, cqe_imm_etype_pkey_eec, + cqe_rlid, cqe_g_mlpath, cqe_sl_ipok, cqe_rqpn, cqe_my_ee, cqe_my_qpn} : 'd0; +/********************************************** CQE Field Gen : End ********************************************************/ + +/*------------------------------------------- Variables Decode : End ----------------------------------------------*/ + +/*------------------------------------------- Local Macros Undef : Begin --------------------------------------------*/ +/*------------------------------------------- Local Macros Undef : End ----------------------------------------------*/ + +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/RPCSubsystem/RDMACore/ResponderCore/ReqRecvCore/ReqRecvCore.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/RPCSubsystem/RDMACore/ResponderCore/ReqRecvCore/ReqRecvCore.v new file mode 100644 index 0000000000000000000000000000000000000000..b6dc79d4c94bb7cf03c9cbd5d3d603522a6af687 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/RPCSubsystem/RDMACore/ResponderCore/ReqRecvCore/ReqRecvCore.v @@ -0,0 +1,301 @@ +/*------------------------------------------- Module Description : Begin ---------------------------------------------- +Name: ReqRecvCore +Author: YangFan +Function: 1.Handle Network Request. +--------------------------------------------- Module Decription : End -----------------------------------------------*/ + +/*------------------------------------------- Timescale Definition : Begin ------------------------------------------*/ +`timescale 1ns / 1ps +/*------------------------------------------- Timescale Definition : End --------------------------------------------*/ + +/*------------------------------------------- Included Files : Begin ------------------------------------------------*/ +`include "protocol_engine_def.vh" +/*------------------------------------------- Included Files : End --------------------------------------------------*/ + +/*------------------------------------------- Input/Output Definition : Begin ---------------------------------------*/ +module ReqRecvCore +#( + parameter INGRESS_CXT_HEAD_WIDTH = 128, + parameter INGRESS_CXT_DATA_WIDTH = 256, + parameter EGRESS_CXT_HEAD_WIDTH = 128, + parameter EGRESS_CXT_DATA_WIDTH = 256, + + parameter INGRESS_MR_HEAD_WIDTH = 128, + parameter INGRESS_MR_DATA_WIDTH = 256, + parameter EGRESS_MR_HEAD_WIDTH = 128, + parameter EGRESS_MR_DATA_WIDTH = 256 +) +( + input wire clk, + input wire rst, + +//Interface with WQEParser + input wire ingress_pkt_valid, + input wire [`PKT_META_BUS_WIDTH - 1 : 0] ingress_pkt_head, + output wire ingress_pkt_ready, + +//Interface with OoOStation(For CxtMgt) + output wire fetch_cxt_ingress_valid, + output wire [`RX_REQ_OOO_CXT_INGRESS_HEAD_WIDTH - 1 : 0] fetch_cxt_ingress_head, + output wire [`RX_REQ_OOO_CXT_INGRESS_DATA_WIDTH - 1 : 0] fetch_cxt_ingress_data, + output wire fetch_cxt_ingress_start, + output wire fetch_cxt_ingress_last, + input wire fetch_cxt_ingress_ready, + + input wire fetch_cxt_egress_valid, + input wire [`RX_REQ_OOO_CXT_EGRESS_HEAD_WIDTH - 1 : 0 ] fetch_cxt_egress_head, + input wire [`RX_REQ_OOO_CXT_EGRESS_DATA_WIDTH - 1 : 0 ] fetch_cxt_egress_data, + input wire fetch_cxt_egress_start, + input wire fetch_cxt_egress_last, + output wire fetch_cxt_egress_ready, + +//Interface with OoOStation(For MRMgt) + output wire fetch_mr_ingress_valid, + output wire [`RX_REQ_OOO_MR_INGRESS_HEAD_WIDTH - 1 : 0] fetch_mr_ingress_head, + output wire [`RX_REQ_OOO_MR_INGRESS_DATA_WIDTH - 1 : 0] fetch_mr_ingress_data, + output wire fetch_mr_ingress_start, + output wire fetch_mr_ingress_last, + input wire fetch_mr_ingress_ready, + + input wire fetch_mr_egress_valid, + input wire [`RX_REQ_OOO_MR_EGRESS_HEAD_WIDTH - 1 : 0] fetch_mr_egress_head, + input wire [`RX_REQ_OOO_MR_EGRESS_DATA_WIDTH - 1 : 0] fetch_mr_egress_data, + input wire fetch_mr_egress_start, + input wire fetch_mr_egress_last, + output wire fetch_mr_egress_ready, + +//Interface with RecvQueueMgt + output wire wqe_req_valid, + output wire [`WQE_META_WIDTH - 1 : 0] wqe_req_head, + output wire wqe_req_start, + output wire wqe_req_last, + input wire wqe_req_ready, + + input wire wqe_resp_valid, + input wire [`WQE_META_WIDTH - 1 : 0] wqe_resp_head, + input wire [`WQE_SEG_WIDTH - 1 : 0] wqe_resp_data, + input wire wqe_resp_start, + input wire wqe_resp_last, + output wire wqe_resp_ready, + +//Interface with cache offset table + output wire cache_offset_wen, + output wire [`QP_NUM_LOG - 1 : 0] cache_offset_addr, + output wire [`RQ_CACHE_SLOT_NUM_LOG - 1:0] cache_offset_din, + input wire [`RQ_CACHE_SLOT_NUM_LOG - 1:0] cache_offset_dout, + +//Interface with RQHeadRecord + output wire rq_offset_wen, + output wire [`QP_NUM_LOG - 1 : 0] rq_offset_addr, + output wire [23:0] rq_offset_din, + input wire [23:0] rq_offset_dout, + + output wire RQ_cache_owned_wen, + output wire [`RQ_CACHE_CELL_NUM_LOG - 1 : 0] RQ_cache_owned_addr, + output wire [`QP_NUM_LOG - 1 : 0] RQ_cache_owned_din, + input wire [`QP_NUM_LOG - 1 : 0] RQ_cache_owned_dout, + +//Interface with CompletionQueueMgt + output wire cq_req_valid, + output wire [`CQ_REQ_HEAD_WIDTH - 1 : 0] cq_req_head, + input wire cq_req_ready, + + input wire cq_resp_valid, + input wire [`CQ_RESP_HEAD_WIDTH - 1 : 0] cq_resp_head, + output wire cq_resp_ready, + +//Interface with EventQueueMgt + output wire eq_req_valid, + output wire [`EQ_REQ_HEAD_WIDTH - 1 : 0] eq_req_head, + input wire eq_req_ready, + + input wire eq_resp_valid, + input wire [`EQ_RESP_HEAD_WIDTH - 1 : 0] eq_resp_head, + output wire eq_resp_ready, + +//Interface with Packet Buffer + output wire delete_req_valid, + output wire [`MAX_DB_SLOT_NUM_LOG * 2 - 1 : 0] delete_req_head, + input wire delete_req_ready, + + input wire delete_resp_valid, + input wire delete_resp_start, + input wire delete_resp_last, + input wire [`PACKET_BUFFER_SLOT_WIDTH - 1 : 0] delete_resp_data, + output wire delete_resp_ready, + +//DMA Write Interface + output wire scatter_req_wr_en, + output wire [`DMA_LENGTH_WIDTH * 2 + `DMA_ADDR_WIDTH - 1 : 0] scatter_req_din, + input wire scatter_req_prog_full, + + output wire scatter_data_wr_en, + output wire [`DMA_DATA_WIDTH - 1: 0] scatter_data_din, + input wire scatter_data_prog_full, + +//DMA Read Interface + output wire gather_req_wr_en, + output wire [`DMA_LENGTH_WIDTH * 2 + `DMA_ADDR_WIDTH - 1 : 0] gather_req_din, + input wire gather_req_prog_full, + +//Interface with RespTransCore + output wire net_resp_wen, + output wire [`NET_REQ_META_WIDTH - 1 : 0] net_resp_din, + input wire net_resp_prog_full +); +/*------------------------------------------- Input/Output Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Macros Definition : Begin ---------------------------------------*/ +/*------------------------------------------- Local Macros Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Variables Definition : Begin ------------------------------------*/ + +/*------------------------------------------- Local Variables Definition : End --------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : Begin ---------------------------------------*/ +ReqRecvCore_Thread_1 #( + .INGRESS_CXT_HEAD_WIDTH ( INGRESS_CXT_HEAD_WIDTH ), + .INGRESS_CXT_DATA_WIDTH ( INGRESS_CXT_DATA_WIDTH ) +) +ReqRecvCore_Thread_1_Inst +( + .clk ( clk ), + .rst ( rst ), + + .ingress_pkt_valid ( ingress_pkt_valid ), + .ingress_pkt_head ( ingress_pkt_head ), + .ingress_pkt_ready ( ingress_pkt_ready ), + + .fetch_cxt_ingress_valid ( fetch_cxt_ingress_valid ), + .fetch_cxt_ingress_head ( fetch_cxt_ingress_head ), + .fetch_cxt_ingress_data ( fetch_cxt_ingress_data ), + .fetch_cxt_ingress_start ( fetch_cxt_ingress_start ), + .fetch_cxt_ingress_last ( fetch_cxt_ingress_last ), + .fetch_cxt_ingress_ready ( fetch_cxt_ingress_ready ) +); + +ReqRecvCore_Thread_2 #( + .INGRESS_MR_HEAD_WIDTH ( INGRESS_MR_HEAD_WIDTH ), + .INGRESS_MR_DATA_WIDTH ( INGRESS_MR_DATA_WIDTH ), + .EGRESS_CXT_HEAD_WIDTH ( EGRESS_CXT_HEAD_WIDTH ), + .EGRESS_CXT_DATA_WIDTH ( EGRESS_CXT_DATA_WIDTH ) +) +ReqRecvCore_Thread_2_Inst +( + .clk ( clk ), + .rst ( rst ), + + .fetch_cxt_egress_valid ( fetch_cxt_egress_valid ), + .fetch_cxt_egress_head ( fetch_cxt_egress_head ), + .fetch_cxt_egress_data ( fetch_cxt_egress_data ), + .fetch_cxt_egress_start ( fetch_cxt_egress_start ), + .fetch_cxt_egress_last ( fetch_cxt_egress_last ), + .fetch_cxt_egress_ready ( fetch_cxt_egress_ready ), + + .fetch_mr_ingress_valid ( fetch_mr_ingress_valid ), + .fetch_mr_ingress_head ( fetch_mr_ingress_head ), + .fetch_mr_ingress_data ( fetch_mr_ingress_data ), + .fetch_mr_ingress_start ( fetch_mr_ingress_start ), + .fetch_mr_ingress_last ( fetch_mr_ingress_last ), + .fetch_mr_ingress_ready ( fetch_mr_ingress_ready ), + + .wqe_req_valid ( wqe_req_valid ), + .wqe_req_head ( wqe_req_head ), + .wqe_req_start ( wqe_req_start ), + .wqe_req_last ( wqe_req_last ), + .wqe_req_ready ( wqe_req_ready ), + + .wqe_resp_valid ( wqe_resp_valid ), + .wqe_resp_head ( wqe_resp_head ), + .wqe_resp_data ( wqe_resp_data ), + .wqe_resp_start ( wqe_resp_start ), + .wqe_resp_last ( wqe_resp_last ), + .wqe_resp_ready ( wqe_resp_ready ), + + .cache_offset_wen ( cache_offset_wen ), + .cache_offset_addr ( cache_offset_addr ), + .cache_offset_din ( cache_offset_din ), + .cache_offset_dout ( cache_offset_dout ), + + .rq_offset_wen ( rq_offset_wen ), + .rq_offset_addr ( rq_offset_addr ), + .rq_offset_din ( rq_offset_din ), + .rq_offset_dout ( rq_offset_dout ), + + .cache_owned_wen ( RQ_cache_owned_wen ), + .cache_owned_addr ( RQ_cache_owned_addr ), + .cache_owned_din ( RQ_cache_owned_din ), + .cache_owned_dout ( RQ_cache_owned_dout ), + + .cq_req_valid ( cq_req_valid ), + .cq_req_head ( cq_req_head ), + .cq_req_ready ( cq_req_ready ), + + .cq_resp_valid ( cq_resp_valid ), + .cq_resp_head ( cq_resp_head ), + .cq_resp_ready ( cq_resp_ready ), + + .eq_req_valid ( eq_req_valid ), + .eq_req_head ( eq_req_head ), + .eq_req_ready ( eq_req_ready ), + + .eq_resp_valid ( eq_resp_valid ), + .eq_resp_head ( eq_resp_head ), + .eq_resp_ready ( eq_resp_ready ) +); + +ReqRecvCore_Thread_3 +#( + .EGRESS_MR_HEAD_WIDTH ( EGRESS_MR_HEAD_WIDTH ), + .EGRESS_MR_DATA_WIDTH ( EGRESS_MR_DATA_WIDTH ) +) +ReqRecvCore_Thread_3_Inst +( + .clk ( clk ), + .rst ( rst ), + + .fetch_mr_egress_valid ( fetch_mr_egress_valid ), + .fetch_mr_egress_head ( fetch_mr_egress_head ), + .fetch_mr_egress_data ( fetch_mr_egress_data ), + .fetch_mr_egress_start ( fetch_mr_egress_start ), + .fetch_mr_egress_last ( fetch_mr_egress_last ), + .fetch_mr_egress_ready ( fetch_mr_egress_ready ), + + .delete_req_valid ( delete_req_valid ), + .delete_req_head ( delete_req_head ), + .delete_req_ready ( delete_req_ready ), + + .delete_resp_valid ( delete_resp_valid ), + .delete_resp_start ( delete_resp_start ), + .delete_resp_last ( delete_resp_last ), + .delete_resp_data ( delete_resp_data ), + .delete_resp_ready ( delete_resp_ready ), + + .scatter_req_wr_en ( scatter_req_wr_en ), + .scatter_req_din ( scatter_req_din ), + .scatter_req_prog_full ( scatter_req_prog_full ), + + .scatter_data_wr_en ( scatter_data_wr_en ), + .scatter_data_din ( scatter_data_din ), + .scatter_data_prog_full ( scatter_data_prog_full ), + + .gather_req_wr_en ( gather_req_wr_en ), + .gather_req_din ( gather_req_din ), + .gather_req_prog_full ( gather_req_prog_full ), + + .net_resp_wen ( net_resp_wen ), + .net_resp_din ( net_resp_din ), + .net_resp_prog_full ( net_resp_prog_full ) +); +/*------------------------------------------- Submodules Instatiation : End -----------------------------------------*/ + +/*------------------------------------------- State Machine Definition : Begin --------------------------------------*/ +/*------------------------------------------- State Machine Definition : End ----------------------------------------*/ + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ +/*------------------------------------------- Variables Decode : End ----------------------------------------------***/ + +/*------------------------------------------- Local Macros Undef : Begin --------------------------------------------*/ +/*------------------------------------------- Local Macros Undef : End ----------------------------------------------*/ + +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/RPCSubsystem/RDMACore/ResponderCore/ReqRecvCore/ReqRecvCore_Thread_1.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/RPCSubsystem/RDMACore/ResponderCore/ReqRecvCore/ReqRecvCore_Thread_1.v new file mode 100644 index 0000000000000000000000000000000000000000..3371e518ee3762ec56c87b6add8850b580395d69 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/RPCSubsystem/RDMACore/ResponderCore/ReqRecvCore/ReqRecvCore_Thread_1.v @@ -0,0 +1,141 @@ +/*------------------------------------------- Module Description : Begin ---------------------------------------------- +Name: ReqRecvCore_Thread_1 +Author: YangFan +Function: 1.Fetch Cxt and generate Net Meta. +--------------------------------------------- Module Decription : End -----------------------------------------------*/ + +/*------------------------------------------- Timescale Definition : Begin ------------------------------------------*/ +`timescale 1ns / 1ps +/*------------------------------------------- Timescale Definition : End --------------------------------------------*/ + +/*------------------------------------------- Included Files : Begin ------------------------------------------------*/ +`include "protocol_engine_def.vh" +/*------------------------------------------- Included Files : End --------------------------------------------------*/ + +/*------------------------------------------- Input/Output Definition : Begin ---------------------------------------*/ +module ReqRecvCore_Thread_1 +#( + parameter INGRESS_CXT_HEAD_WIDTH = 128, + parameter INGRESS_CXT_DATA_WIDTH = 256 +) +( + input wire clk, + input wire rst, + +//Interface with MACDecap + input wire ingress_pkt_valid, + input wire [`PKT_META_BUS_WIDTH - 1 : 0] ingress_pkt_head, + output wire ingress_pkt_ready, + +//Interface with OoOStation(For CxtMgt) + output wire fetch_cxt_ingress_valid, + output wire [`RX_REQ_OOO_CXT_INGRESS_HEAD_WIDTH - 1 : 0] fetch_cxt_ingress_head, + output wire [`RX_REQ_OOO_CXT_INGRESS_DATA_WIDTH - 1 : 0] fetch_cxt_ingress_data, + output wire fetch_cxt_ingress_start, + output wire fetch_cxt_ingress_last, + input wire fetch_cxt_ingress_ready +); +/*------------------------------------------- Input/Output Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Macros Definition : Begin ---------------------------------------*/ +`define REMOTE_QPN_OFFSET 55:32 +/*------------------------------------------- Local Macros Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Variables Definition : Begin ------------------------------------*/ +wire [`INGRESS_COMMON_HEAD_WIDTH - 1 : 0] ingress_common_head; +wire [`MAX_OOO_SLOT_NUM_LOG - 1 :0] ingress_slot_count; + +reg [`PKT_META_BUS_WIDTH - 1 : 0] pkt_header_bus; + +wire [23:0] PktHeader_remote_qpn; +/*------------------------------------------- Local Variables Definition : End --------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : Begin ---------------------------------------*/ +/*------------------------------------------- Submodules Instatiation : End -----------------------------------------*/ + +/*------------------------------------------- State Machine Definition : Begin --------------------------------------*/ +reg [2:0] cur_state; +reg [2:0] next_state; + +parameter [2:0] IDLE_s = 3'd1, + JUDGE_s = 3'd2, + FETCH_CXT_s = 3'd3; + +always @(posedge clk or posedge rst) begin + if(rst) begin + cur_state <= IDLE_s; + end + else begin + cur_state <= next_state; + end +end + +always @(*) begin + case(cur_state) + IDLE_s: if(ingress_pkt_valid) begin + next_state = JUDGE_s; + end + else begin + next_state = IDLE_s; + end + JUDGE_s: next_state = FETCH_CXT_s; + FETCH_CXT_s: if(fetch_cxt_ingress_valid && fetch_cxt_ingress_ready) begin + next_state = IDLE_s; + end + else begin + next_state = FETCH_CXT_s; + end + default: next_state = IDLE_s; + endcase +end +/*------------------------------------------- State Machine Definition : End ----------------------------------------*/ + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ +wire [`QP_NUM_LOG - 1 : 0] qpn_data; +assign qpn_data = PktHeader_remote_qpn; + +wire [`MAX_QP_NUM_LOG - 1 : 0] queue_index; +assign queue_index = {'d0, qpn_data[`QP_NUM_LOG - 1 : 0]}; + +//-- pkt_header_bus -- +always @(posedge clk or posedge rst) begin + if(rst) begin + pkt_header_bus <= 'd0; + end + else if(cur_state == IDLE_s && ingress_pkt_valid) begin + pkt_header_bus <= ingress_pkt_head; + end + else begin + pkt_header_bus <= pkt_header_bus; + end +end + +//-- PktHeader_remote_qpn -- +assign PktHeader_remote_qpn = pkt_header_bus[`REMOTE_QPN_OFFSET]; + + +//-- ingress_common_head -- +//-- ingress_slot_count -- +assign ingress_common_head = {`NO_BYPASS, ingress_slot_count, queue_index}; +assign ingress_slot_count = 'd1; + +//-- fetch_cxt_ingress_valid -- +//-- fetch_cxt_ingress_head -- +//-- fetch_cxt_ingress_data -- +//-- fetch_cxt_ingress_start -- +//-- fetch_cxt_ingress_last -- +assign fetch_cxt_ingress_valid = (cur_state == FETCH_CXT_s) ? 'd1 : 'd0; +assign fetch_cxt_ingress_head = (cur_state == FETCH_CXT_s) ? {qpn_data[`QP_NUM_LOG - 1 : 0], `CXT_READ, ingress_common_head} : 'd0; +assign fetch_cxt_ingress_data = (cur_state == FETCH_CXT_s) ? pkt_header_bus : 'd0; +assign fetch_cxt_ingress_start = (cur_state == FETCH_CXT_s) ? 'd1 : 'd0; +assign fetch_cxt_ingress_last = (cur_state == FETCH_CXT_s) ? 'd1 : 'd0; + +//-- ingress_pkt_ready -- +assign ingress_pkt_ready = (cur_state == IDLE_s) ? 'd1 : 'd0; +/*------------------------------------------- Variables Decode : End ----------------------------------------------***/ + +/*------------------------------------------- Local Macros Undef : Begin --------------------------------------------*/ +`undef REMOTE_QPN_OFFSET +/*------------------------------------------- Local Macros Undef : End ----------------------------------------------*/ + +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/RPCSubsystem/RDMACore/ResponderCore/ReqRecvCore/ReqRecvCore_Thread_2.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/RPCSubsystem/RDMACore/ResponderCore/ReqRecvCore/ReqRecvCore_Thread_2.v new file mode 100644 index 0000000000000000000000000000000000000000..95da7f245ff5b0f3cacf11f0aa136dc15b368b71 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/RPCSubsystem/RDMACore/ResponderCore/ReqRecvCore/ReqRecvCore_Thread_2.v @@ -0,0 +1,1151 @@ + +/*------------------------------------------- Module Description : Begin ---------------------------------------------- +Name: ReqRecvCore_Thread_2 +Author: YangFan +Function: 1.Fetch MR. +--------------------------------------------- Module Decription : End -----------------------------------------------*/ + +/*------------------------------------------- Timescale Definition : Begin ------------------------------------------*/ +`timescale 1ns / 1ps +/*------------------------------------------- Timescale Definition : End --------------------------------------------*/ + +/*------------------------------------------- Included Files : Begin ------------------------------------------------*/ +`include "protocol_engine_def.vh" +/*------------------------------------------- Included Files : End --------------------------------------------------*/ + +/*------------------------------------------- Input/Output Definition : Begin ---------------------------------------*/ +module ReqRecvCore_Thread_2 +#( + parameter INGRESS_MR_HEAD_WIDTH = 128, + parameter INGRESS_MR_DATA_WIDTH = 256, + parameter EGRESS_CXT_HEAD_WIDTH = 128, + parameter EGRESS_CXT_DATA_WIDTH = 256 +) +( + input wire clk, + input wire rst, + +//Interface with OoOStation(For CxtMgt) + input wire fetch_cxt_egress_valid, + input wire [`RX_REQ_OOO_CXT_EGRESS_HEAD_WIDTH - 1 : 0] fetch_cxt_egress_head, + input wire [`RX_REQ_OOO_CXT_EGRESS_DATA_WIDTH - 1 : 0] fetch_cxt_egress_data, + input wire fetch_cxt_egress_start, + input wire fetch_cxt_egress_last, + output wire fetch_cxt_egress_ready, + +//Interface with OoOStation(For MRMgt) + output wire fetch_mr_ingress_valid, + output wire [`RX_REQ_OOO_MR_INGRESS_HEAD_WIDTH - 1 : 0] fetch_mr_ingress_head, + output wire [`RX_REQ_OOO_MR_INGRESS_DATA_WIDTH - 1 : 0] fetch_mr_ingress_data, + output wire fetch_mr_ingress_start, + output wire fetch_mr_ingress_last, + input wire fetch_mr_ingress_ready, + +//Interface with RecvQueueMgt + output wire wqe_req_valid, + output wire [`WQE_META_WIDTH - 1 : 0] wqe_req_head, + output wire wqe_req_start, + output wire wqe_req_last, + input wire wqe_req_ready, + + input wire wqe_resp_valid, + input wire [`WQE_META_WIDTH - 1 : 0] wqe_resp_head, + input wire [`WQE_SEG_WIDTH - 1 : 0] wqe_resp_data, + input wire wqe_resp_start, + input wire wqe_resp_last, + output reg wqe_resp_ready, + +//Interface with cache offset table + output reg cache_offset_wen, + output reg [`QP_NUM_LOG - 1 : 0] cache_offset_addr, + output reg [`RQ_CACHE_SLOT_NUM_LOG - 1:0] cache_offset_din, + input wire [`RQ_CACHE_SLOT_NUM_LOG - 1:0] cache_offset_dout, + +//Interface with CacheOwnedTable + output reg cache_owned_wen, + output reg [`RQ_CACHE_CELL_NUM_LOG - 1 : 0] cache_owned_addr, + output reg [`QP_NUM_LOG - 1 : 0] cache_owned_din, + input wire [`QP_NUM_LOG - 1 : 0] cache_owned_dout, + +//Interface with RQHeadRecord + output reg rq_offset_wen, + output reg [`QP_NUM_LOG - 1 : 0] rq_offset_addr, + output reg [23:0] rq_offset_din, + input wire [23:0] rq_offset_dout, + +//Interface with CompletionQueueMgt + output wire cq_req_valid, + output wire [`CQ_REQ_HEAD_WIDTH - 1 : 0] cq_req_head, + input wire cq_req_ready, + + input wire cq_resp_valid, + input wire [`CQ_RESP_HEAD_WIDTH - 1 : 0] cq_resp_head, + output wire cq_resp_ready, + +//Interface with EventQueueMgt + output wire eq_req_valid, + output wire [`EQ_REQ_HEAD_WIDTH - 1 : 0] eq_req_head, + input wire eq_req_ready, + + input wire eq_resp_valid, + input wire [`EQ_RESP_HEAD_WIDTH - 1 : 0] eq_resp_head, + output wire eq_resp_ready +); +/*------------------------------------------- Input/Output Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Macros Definition : Begin ---------------------------------------*/ +`define HEADER_LOCAL_QPN_OFFSET 55:32 +`define HEADER_REMOTE_QPN_OFFSET 23:0 +`define HEADER_NET_OPCODE_OFFSET 28:24 +`define HEADER_SERVICE_TYPE_OFFSET 31:29 +`define HEADER_IMMEDIATE_OFFSET 191:160 +`define HEADER_RKEY_OFFSET 95:64 +`define HEADER_RADDR_OFFSET 159:96 +`define HEADER_DMAC_OFFSET 239:192 +`define HEADER_SMAC_OFFSET 287:240 +`define HEADER_DIP_OFFSET 319:288 +`define HEADER_SIP_OFFSET 351:320 +`define HEADER_PKT_START_ADDR_OFFSET 367:352 +`define HEADER_PKT_LENGTH_OFFSET 383:368 +/*------------------------------------------- Local Macros Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Variables Definition : Begin ------------------------------------*/ +reg [`RX_REQ_OOO_CXT_EGRESS_HEAD_WIDTH - 1 : 0] cxt_head_bus; +reg [`PKT_META_BUS_WIDTH : 0] pkt_header_bus; + +wire [23:0] PktHeader_local_qpn; +wire [23:0] PktHeader_remote_qpn; +wire [4:0] PktHeader_net_opcode; +wire [4:0] PktHeader_resp_opcode; +wire [2:0] PktHeader_service_type; +wire [47:0] PktHeader_dmac; +wire [47:0] PktHeader_smac; +wire [31:0] PktHeader_dip; +wire [31:0] PktHeader_sip; +wire [31:0] PktHeader_immediate; +wire [31:0] PktHeader_rkey; +wire [63:0] PktHeader_raddr; +wire [15:0] PktHeader_pkt_length; +wire [15:0] PktHeader_pkt_start_addr; + +reg [31:0] ori_wqe_addr; + +wire [7:0] Cxt_rq_entry_sz_log; +wire [31:0] Cxt_rq_length; +wire [31:0] Cxt_rq_lkey; +wire [31:0] Cxt_qp_pd; +wire [23:0] Cxt_cqn; +wire [31:0] Cxt_cq_lkey; +wire [31:0] Cxt_cq_pd; +wire [31:0] Cxt_cq_length; +wire [31:0] Cxt_eqn; +wire [31:0] Cxt_eq_lkey; +wire [31:0] Cxt_eq_pd; +wire [31:0] Cxt_eq_length; + +//NextUnit +reg [4:0] NextUnit_next_wqe_opcode; +reg [0:0] NextUnit_next_wqe_valid; +reg [25:0] NextUnit_next_wqe_addr; +reg [5:0] NextUnit_next_wqe_size; +reg [7:0] NextUnit_cur_wqe_size; +reg [7:0] NextUnit_cur_wqe_size_aligned; +reg [7:0] NextUnit_next_wqe_size_aligned; + +//DataUnit +wire [31:0] DataUnit_byte_cnt; +wire [31:0] DataUnit_lkey; +wire [63:0] DataUnit_laddr; + +wire [`INGRESS_COMMON_HEAD_WIDTH - 1 : 0] ingress_common_head; +wire [`MAX_OOO_SLOT_NUM_LOG - 1:0] ingress_slot_count; + +reg [31:0] parsed_msg_length; +reg [31:0] pkt_length_left; +reg [7:0] tail_indicator; + +reg [63:0] cq_offset; +reg [63:0] eq_offset; + +wire [31:0] mr_length; +wire [63:0] mr_laddr; +wire [31:0] mr_lkey; +wire [31:0] mr_pd; + +wire [31:0] mr_flags; +reg [3:0] mr_flag_sw_owns; +reg mr_flag_absolute_addr; +reg mr_flag_relative_addr; +reg mr_flag_mio; +reg mr_flag_bind_enable; +reg mr_flag_physical; +reg mr_flag_region; +reg mr_flag_on_demand; +reg mr_flag_zero_based; +reg mr_flag_mw_bind; +reg mr_flag_remote_read; +reg mr_flag_remote_write; +reg mr_flag_local_write; + +reg msg_offset_wea; +reg [`QP_NUM_LOG - 1 : 0] msg_offset_addra; +reg [31:0] msg_offset_dina; +wire [`QP_NUM_LOG - 1 : 0] msg_offset_addrb; +wire [31:0] msg_offset_doutb; +/*------------------------------------------- Local Variables Definition : End --------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : Begin ---------------------------------------*/ +SRAM_SDP_Template #( + .RAM_WIDTH ( 32 ), //Record each cell offset(in unit of slot) + .RAM_DEPTH ( `QP_NUM ) +) +MsgOffsetTable +( + .clk ( clk ), + .rst ( rst ), + + .wea ( msg_offset_wea ), + .addra ( msg_offset_addra ), + .dina ( msg_offset_dina ), + + .addrb ( msg_offset_addrb ), + .doutb ( msg_offset_doutb ) +); +/*------------------------------------------- Submodules Instatiation : End -----------------------------------------*/ + +/*------------------------------------------- State Machine Definition : Begin --------------------------------------*/ +reg [5:0] cur_state; +reg [5:0] next_state; + +parameter [5:0] IDLE_s = 5'd1, + JUDGE_s = 5'd2, + WQE_REQ_s = 5'd3, + NEXT_UNIT_s = 5'd4, + DATA_UNIT_s = 5'd5, + CQ_REQ_s = 5'd6, + CQ_RESP_s = 5'd7, + EQ_REQ_s = 5'd8, + EQ_RESP_s = 5'd9, + UPDATE_RQ_s = 5'd10, + MR_FOR_SEND_s = 5'd11, + MR_FOR_WRITE_s = 5'd12, + MR_FOR_READ_s = 5'd13, + MR_FOR_CQ_s = 5'd14, + MR_FOR_EQ_s = 5'd15, + GEN_ACK_s = 5'd16; + +always @(posedge clk or posedge rst) begin + if(rst) begin + cur_state <= IDLE_s; + end + else begin + cur_state <= next_state; + end +end + +always @(*) begin + case(cur_state) + IDLE_s: if(fetch_cxt_egress_valid) begin + next_state = JUDGE_s; + end + else begin + next_state = IDLE_s; + end + JUDGE_s: if( PktHeader_net_opcode == `SEND_FIRST || PktHeader_net_opcode == `SEND_MIDDLE || PktHeader_net_opcode == `SEND_LAST || + PktHeader_net_opcode == `SEND_ONLY || PktHeader_net_opcode == `SEND_LAST_WITH_IMM || PktHeader_net_opcode == `SEND_ONLY_WITH_IMM || + PktHeader_net_opcode == `RDMA_WRITE_LAST_WITH_IMM || PktHeader_net_opcode == `RDMA_WRITE_ONLY_WITH_IMM) begin + next_state = WQE_REQ_s; + end + else if( PktHeader_net_opcode == `RDMA_WRITE_FIRST || PktHeader_net_opcode == `RDMA_WRITE_MIDDLE || PktHeader_net_opcode == `RDMA_WRITE_LAST + || PktHeader_net_opcode == `RDMA_WRITE_ONLY) begin + next_state = MR_FOR_WRITE_s; + end + else if( PktHeader_net_opcode == `RDMA_READ_REQUEST_FIRST || PktHeader_net_opcode == `RDMA_READ_REQUEST_MIDDLE || PktHeader_net_opcode == `RDMA_READ_REQUEST_LAST + || PktHeader_net_opcode == `RDMA_READ_REQUEST_ONLY) begin + next_state = MR_FOR_READ_s; + end + else begin + next_state = IDLE_s; + end + WQE_REQ_s: if(wqe_req_valid && wqe_req_ready) begin + next_state = NEXT_UNIT_s; + end + else begin + next_state = IDLE_s; + end + NEXT_UNIT_s: if(wqe_resp_valid && wqe_resp_ready) begin + next_state = DATA_UNIT_s; + end + else begin + next_state = NEXT_UNIT_s; + end + DATA_UNIT_s: if(PktHeader_net_opcode == `RDMA_WRITE_LAST_WITH_IMM || PktHeader_net_opcode == `RDMA_WRITE_ONLY_WITH_IMM) begin + if(wqe_resp_valid && wqe_resp_last && wqe_resp_ready) begin //RDMA_Write_With_Imm does not need to parse Recv WQE, just consume one + next_state = UPDATE_RQ_s; + end + else begin + next_state = DATA_UNIT_s; + end + end + else if(wqe_resp_valid) begin //Send/Send with Imm, must parse DataUnit, The situation is complex, need careful control. + // if(parsed_msg_length + DataUnit_byte_cnt > msg_offset_doutb) begin + // if(pkt_length_left == 0) begin + // if(wqe_resp_last) begin //When pkt length is exhausted and meet wqe_resp_last, update RQ + // next_state = UPDATE_RQ_s; + // end + // else begin + // next_state = DATA_UNIT_s; + // end + // end + // else begin + // next_state = MR_FOR_SEND_s; + // end + // end + // else if(parsed_msg_length + DataUnit_byte_cnt <= msg_offset_doutb) begin //Previous DataUnits have been consumed, continue parsing new DataUnit + // next_state = DATA_UNIT_s; + // end + // else begin //Unexepeted + // next_state = IDLE_s; + // end + if(pkt_length_left == 0) begin //All payload has been scattered + if(wqe_resp_last) begin + if(PktHeader_net_opcode == `SEND_LAST || PktHeader_net_opcode == `SEND_ONLY || PktHeader_net_opcode == `SEND_LAST_WITH_IMM || + PktHeader_net_opcode == `SEND_ONLY_WITH_IMM) begin + next_state = UPDATE_RQ_s; + end + else begin + next_state = GEN_ACK_s; + end + end + else begin + next_state = DATA_UNIT_s; + end + end + else begin + if(parsed_msg_length + DataUnit_byte_cnt <= msg_offset_doutb) begin + next_state = DATA_UNIT_s; + end + else begin + next_state = MR_FOR_SEND_s; + end + end + end + else begin + next_state = DATA_UNIT_s; + end + CQ_REQ_s: if(cq_req_valid && cq_req_ready) begin + next_state = CQ_RESP_s; + end + else begin + next_state = CQ_REQ_s; + end + CQ_RESP_s: if(cq_resp_valid && cq_resp_ready) begin + next_state = MR_FOR_CQ_s; + end + else begin + next_state = CQ_RESP_s; + end + EQ_REQ_s: if(eq_req_valid && eq_req_ready) begin + next_state = EQ_RESP_s; + end + else begin + next_state = EQ_REQ_s; + end + EQ_RESP_s: if(eq_resp_valid && eq_resp_ready) begin + next_state = MR_FOR_EQ_s; + end + else begin + next_state = EQ_RESP_s; + end + UPDATE_RQ_s: if(PktHeader_net_opcode == `SEND_LAST || PktHeader_net_opcode == `SEND_ONLY || PktHeader_net_opcode == `SEND_LAST_WITH_IMM || PktHeader_net_opcode == `SEND_ONLY_WITH_IMM) begin + next_state = CQ_REQ_s; + end + else if(PktHeader_net_opcode == `RDMA_WRITE_LAST_WITH_IMM || PktHeader_net_opcode == `RDMA_WRITE_ONLY_WITH_IMM) begin + next_state = MR_FOR_WRITE_s; + end + else begin + next_state = IDLE_s; + end + MR_FOR_SEND_s: if(fetch_mr_ingress_valid && fetch_mr_ingress_ready) begin + next_state = DATA_UNIT_s; + end + else begin + next_state = MR_FOR_SEND_s; + end + MR_FOR_WRITE_s: if(fetch_mr_ingress_valid && fetch_mr_ingress_ready) begin + if( PktHeader_net_opcode == `RDMA_WRITE_FIRST || PktHeader_net_opcode == `RDMA_WRITE_MIDDLE || + PktHeader_net_opcode == `RDMA_WRITE_LAST || PktHeader_net_opcode == `RDMA_WRITE_LAST_WITH_IMM || + PktHeader_net_opcode == `RDMA_WRITE_ONLY || PktHeader_net_opcode == `RDMA_WRITE_ONLY_WITH_IMM) begin + next_state = GEN_ACK_s; + end + else begin + next_state = IDLE_s; + end + end + else begin + next_state = MR_FOR_WRITE_s; + end + MR_FOR_READ_s: if(fetch_mr_ingress_valid && fetch_mr_ingress_ready) begin + next_state = IDLE_s; + end + else begin + next_state = MR_FOR_READ_s; + end + MR_FOR_CQ_s: if(fetch_mr_ingress_valid && fetch_mr_ingress_ready) begin + next_state = GEN_ACK_s; + end + else begin + next_state = MR_FOR_CQ_s; + end + MR_FOR_EQ_s: if(fetch_mr_ingress_valid && fetch_mr_ingress_ready) begin + next_state = GEN_ACK_s; + end + else begin + next_state = MR_FOR_CQ_s; + end + GEN_ACK_s: if(fetch_mr_ingress_valid && fetch_mr_ingress_ready) begin + next_state = IDLE_s; + end + else begin + next_state = GEN_ACK_s; + end + default: next_state = IDLE_s; + endcase +end +/*------------------------------------------- State Machine Definition : End ----------------------------------------*/ + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ +//-- cxt_head_bus -- +//-- pkt_header_bus -- +always @(posedge clk or posedge rst) begin + if(rst) begin + cxt_head_bus <= 'd0; + pkt_header_bus <= 'd0; + end + else if(cur_state == IDLE_s && fetch_cxt_egress_valid) begin + cxt_head_bus <= fetch_cxt_egress_head[`RX_REQ_OOO_CXT_EGRESS_HEAD_WIDTH - 1 : `EGRESS_COMMON_HEAD_WIDTH]; + pkt_header_bus <= fetch_cxt_egress_data; + end + else begin + cxt_head_bus <= cxt_head_bus; + pkt_header_bus <= pkt_header_bus; + end +end + +//-- Cxt_rq_entry_sz_log -- +//-- Cxt_rq_length -- +//-- Cxt_rq_lkey -- +//-- Cxt_qp_pd -- +//-- Cxt_cqn -- +//-- Cxt_cq_lkey -- +//-- Cxt_cq_pd -- +//-- Cxt_cq_length -- +//-- Cxt_eqn -- +//-- Cxt_eq_lkey -- +//-- Cxt_eq_pd -- +//-- Cxt_eq_length -- +assign Cxt_rq_entry_sz_log = cxt_head_bus[`QP_CXT_RQ_ENTRY_SZ_LOG_OFFSET]; +assign Cxt_rq_length = cxt_head_bus[`QP_CXT_RQ_LENGTH_OFFSET]; +assign Cxt_rq_lkey = cxt_head_bus[`QP_CXT_RQ_LKEY_OFFSET]; +assign Cxt_qp_pd = cxt_head_bus[`QP_CXT_PD_OFFSET]; +assign Cxt_cqn = cxt_head_bus[`QP_CXT_CQN_RCV_OFFSET]; +assign Cxt_cq_lkey = cxt_head_bus[`CQ_CXT_LKEY_OFFSET]; +assign Cxt_cq_pd = cxt_head_bus[`CQ_CXT_PD_OFFSET]; +assign Cxt_cq_length = (1 << cxt_head_bus[`CQ_CXT_LOG_SIZE_OFFSET]) * `CQE_LENGTH; +assign Cxt_eqn = cxt_head_bus[`CQ_CXT_COMP_EQN_OFFSET]; +assign Cxt_eq_lkey = cxt_head_bus[`EQ_CXT_LKEY_OFFSET]; +assign Cxt_eq_pd = cxt_head_bus[`EQ_CXT_PD_OFFSET]; +assign Cxt_eq_length = (1 << cxt_head_bus[`EQ_CXT_LOG_SIZE_OFFSET]) * `EVENT_LENGTH; + +//-- PktHeader_local_qpn -- +//-- PktHeader_remote_qpn -- +//-- PktHeader_net_opcode -- +//-- PktHeader_service_type -- +//-- PktHeader_dmac -- +//-- PktHeader_smac -- +//-- PktHeader_dip -- +//-- PktHeader_sip -- +//-- PktHeader_immediate -- +//-- PktHeader_rkey -- +//-- PktHeader_raddr -- +//-- PktHeader_pkt_length -- +//-- PktHeader_pkt_start_addr -- +assign PktHeader_local_qpn = pkt_header_bus[`HEADER_LOCAL_QPN_OFFSET]; +assign PktHeader_remote_qpn = pkt_header_bus[`HEADER_REMOTE_QPN_OFFSET]; +assign PktHeader_net_opcode = pkt_header_bus[`HEADER_NET_OPCODE_OFFSET]; +assign PktHeader_service_type = pkt_header_bus[`HEADER_SERVICE_TYPE_OFFSET]; +assign PktHeader_dmac = pkt_header_bus[`HEADER_DMAC_OFFSET]; +assign PktHeader_smac = pkt_header_bus[`HEADER_SMAC_OFFSET]; +assign PktHeader_dip = pkt_header_bus[`HEADER_DIP_OFFSET]; +assign PktHeader_sip = pkt_header_bus[`HEADER_SIP_OFFSET]; +assign PktHeader_immediate = pkt_header_bus[`HEADER_IMMEDIATE_OFFSET]; +assign PktHeader_rkey = pkt_header_bus[`HEADER_RKEY_OFFSET]; +assign PktHeader_raddr = pkt_header_bus[`HEADER_RADDR_OFFSET]; +assign PktHeader_pkt_length = pkt_header_bus[`HEADER_PKT_LENGTH_OFFSET]; +assign PktHeader_pkt_start_addr = pkt_header_bus[`HEADER_PKT_START_ADDR_OFFSET]; + +//-- PktHeader_resp_opcode -- +assign PktHeader_resp_opcode = (PktHeader_net_opcode == `RDMA_READ_REQUEST_FIRST) ? `RDMA_READ_RESPONSE_FIRST : + (PktHeader_net_opcode == `RDMA_READ_REQUEST_MIDDLE) ? `RDMA_READ_RESPONSE_MIDDLE : + (PktHeader_net_opcode == `RDMA_READ_REQUEST_LAST) ? `RDMA_READ_RESPONSE_LAST : + (PktHeader_net_opcode == `RDMA_READ_REQUEST_ONLY) ? `RDMA_READ_RESPONSE_ONLY : 'd0; + +wire [31:0] cur_wqe_size; +wire [31:0] next_wqe_size; +assign cur_wqe_size = wqe_resp_data[`NEXT_UNIT_CUR_WQE_SIZE_OFFSET]; +assign next_wqe_size = wqe_resp_data[`NEXT_UNIT_NEXT_WQE_SIZE_OFFSET]; + +//Next Unit Field +//-- NextUnit_next_wqe_opcode -- +//-- NextUnit_next_wqe_valid -- +//-- NextUnit_next_wqe_addr -- +//-- NextUnit_next_wqe_size -- +//-- NextUnit_cur_wqe_size -- +//-- NextUnit_cur_wqe_size_aligned -- +always @(posedge clk or posedge rst) begin + if(rst) begin + NextUnit_next_wqe_opcode <= 'd0; + NextUnit_next_wqe_valid <= 'd0; + NextUnit_next_wqe_addr <= 'd0; + NextUnit_next_wqe_size <= 'd0; + NextUnit_next_wqe_size_aligned <= 'd0; + NextUnit_cur_wqe_size <= 'd0; + NextUnit_cur_wqe_size_aligned <= 'd0; + end + else if(cur_state == NEXT_UNIT_s && wqe_resp_valid) begin + NextUnit_next_wqe_opcode <= wqe_resp_data[`NEXT_UNIT_NEXT_WQE_OPCODE_OFFSET]; + NextUnit_next_wqe_valid <= (wqe_resp_data[`NEXT_UNIT_NEXT_WQE_SIZE_OFFSET] != 0); + NextUnit_next_wqe_addr <= wqe_resp_data[`NEXT_UNIT_NEXT_WQE_ADDR_OFFSET]; + NextUnit_next_wqe_size <= wqe_resp_data[`NEXT_UNIT_NEXT_WQE_SIZE_OFFSET]; + NextUnit_cur_wqe_size <= wqe_resp_data[`NEXT_UNIT_CUR_WQE_SIZE_OFFSET]; + + case(Cxt_rq_entry_sz_log) //minimum 64, maximum 1024 + 6: NextUnit_next_wqe_size_aligned <= (next_wqe_size % 4) ? (next_wqe_size[31:2] + 32'd1) * 4 : next_wqe_size[31:2] * 4; + 7: NextUnit_next_wqe_size_aligned <= (next_wqe_size % 8) ? (next_wqe_size[31:3] + 32'd1) * 8 : next_wqe_size[31:3] * 8; + 8: NextUnit_next_wqe_size_aligned <= (next_wqe_size % 16) ? (next_wqe_size[31:4] + 32'd1) * 16 : next_wqe_size[31:4] * 16; + 9: NextUnit_next_wqe_size_aligned <= (next_wqe_size % 32) ? (next_wqe_size[31:5] + 32'd1) * 32 : next_wqe_size[31:5] * 32; + 10: NextUnit_next_wqe_size_aligned <= (next_wqe_size % 64) ? (next_wqe_size[31:6] + 32'd1) * 64 : next_wqe_size[31:6] * 64; + default: NextUnit_next_wqe_size_aligned <= 'd0; + endcase + + case(Cxt_rq_entry_sz_log) //minimum 64, maximum 1024 + 6: NextUnit_cur_wqe_size_aligned <= (cur_wqe_size % 4) ? (cur_wqe_size[31:2] + 32'd1) * 4 : cur_wqe_size[31:2] * 4; + 7: NextUnit_cur_wqe_size_aligned <= (cur_wqe_size % 8) ? (cur_wqe_size[31:3] + 32'd1) * 8 : cur_wqe_size[31:3] * 8; + 8: NextUnit_cur_wqe_size_aligned <= (cur_wqe_size % 16) ? (cur_wqe_size[31:4] + 32'd1) * 16 : cur_wqe_size[31:4] * 16; + 9: NextUnit_cur_wqe_size_aligned <= (cur_wqe_size % 32) ? (cur_wqe_size[31:5] + 32'd1) * 32 : cur_wqe_size[31:5] * 32; + 10: NextUnit_cur_wqe_size_aligned <= (cur_wqe_size % 64) ? (cur_wqe_size[31:6] + 32'd1) * 64 : cur_wqe_size[31:6] * 64; + default: NextUnit_cur_wqe_size_aligned <= 'd0; + endcase + + end + else begin + NextUnit_next_wqe_opcode <= NextUnit_next_wqe_opcode; + NextUnit_next_wqe_valid <= NextUnit_next_wqe_valid; + NextUnit_next_wqe_addr <= NextUnit_next_wqe_addr; + NextUnit_next_wqe_size <= NextUnit_next_wqe_size; + NextUnit_next_wqe_size_aligned <= NextUnit_next_wqe_size_aligned; + NextUnit_cur_wqe_size <= NextUnit_cur_wqe_size; + NextUnit_cur_wqe_size_aligned <= NextUnit_cur_wqe_size_aligned; + end +end + +//-- DataUnit_byte_cnt -- +//-- DataUnit_lkey -- +//-- DataUnit_laddr -- +assign DataUnit_byte_cnt = (cur_state == DATA_UNIT_s || cur_state == MR_FOR_SEND_s) && wqe_resp_valid ? wqe_resp_data[`DATA_UNIT_BYTE_CNT_OFFSET] : 'd0; +assign DataUnit_lkey = (cur_state == DATA_UNIT_s || cur_state == MR_FOR_SEND_s) && wqe_resp_valid ? wqe_resp_data[`DATA_UNIT_LKEY_OFFSET] : 'd0; +assign DataUnit_laddr = (cur_state == DATA_UNIT_s || cur_state == MR_FOR_SEND_s) && wqe_resp_valid ? wqe_resp_data[`DATA_UNIT_LADDR_OFFSET] : 'd0; + +//-- parsed_msg_length -- +always @(posedge clk or posedge rst) begin + if(rst) begin + parsed_msg_length <= 'd0; + end + else if(cur_state == IDLE_s) begin + parsed_msg_length <= 'd0; + end + else if(cur_state == DATA_UNIT_s && wqe_resp_valid && pkt_length_left > 0) begin //MR_FOR_SEND_s will use this variable + if(parsed_msg_length + DataUnit_byte_cnt <= msg_offset_doutb) begin + parsed_msg_length <= parsed_msg_length + DataUnit_byte_cnt; + end + else begin + parsed_msg_length <= parsed_msg_length; + end + end + else if(cur_state == MR_FOR_SEND_s && fetch_mr_ingress_valid && fetch_mr_ingress_ready) begin + parsed_msg_length <= parsed_msg_length + DataUnit_byte_cnt; + end + else begin + parsed_msg_length <= parsed_msg_length; + end +end + +//-- pkt_length_left -- +always @(posedge clk or posedge rst) begin + if(rst) begin + pkt_length_left <= 'd0; + end + else if(cur_state == JUDGE_s) begin + pkt_length_left <= PktHeader_pkt_length; + end + else if(cur_state == MR_FOR_SEND_s && fetch_mr_ingress_valid && fetch_mr_ingress_ready) begin + if(pkt_length_left > parsed_msg_length + DataUnit_byte_cnt - msg_offset_doutb) begin + pkt_length_left <= pkt_length_left - (parsed_msg_length + DataUnit_byte_cnt - msg_offset_doutb); + end + else begin + pkt_length_left <= 'd0; + end + end + else begin + pkt_length_left <= pkt_length_left; + end +end + +//-- cq_offset -- +always @(posedge clk or posedge rst) begin + if (rst) begin + cq_offset <= 'd0; + end + else if (cur_state == CQ_RESP_s && cq_resp_valid) begin + cq_offset <= cq_resp_head[95:32]; + end + else begin + cq_offset <= cq_offset; + end +end + + +//-- eq_offset -- +always @(posedge clk or posedge rst) begin + if (rst) begin + eq_offset <= 'd0; + end + else if (cur_state == EQ_RESP_s && eq_resp_valid) begin + eq_offset <= eq_resp_head[95:32]; + end + else begin + eq_offset <= eq_offset; + end +end + +//-- ori_wqe_addr -- +always @(posedge clk or posedge rst) begin + if (rst) begin + ori_wqe_addr <= 'd0; + end + else if (cur_state == NEXT_UNIT_s && wqe_resp_valid) begin + ori_wqe_addr <= rq_offset_dout; + end + else begin + ori_wqe_addr <= ori_wqe_addr; + end +end + +//-- tail_indicator -- +always @(posedge clk or posedge rst) begin + if(rst) begin + tail_indicator <= 'd0; + end + else if(cur_state == DATA_UNIT_s) begin + if((parsed_msg_length + DataUnit_byte_cnt > msg_offset_doutb) && (pkt_length_left <= parsed_msg_length + DataUnit_byte_cnt - msg_offset_doutb)) begin + tail_indicator <= `TAIL_FLAG; + end + else begin + tail_indicator <= 'd0; + end + end + else begin + tail_indicator <= tail_indicator; + end +end + +//-- fetch_cxt_egress_ready -- +assign fetch_cxt_egress_ready = (cur_state == IDLE_s) ? 'd1 : 'd0; + +//-- wqe_req_valid -- +//-- wqe_req_head -- +//-- wqe_req_start -- +//-- wqe_req_last -- +assign wqe_req_valid = (cur_state == WQE_REQ_s) ? 'd1 : 'd0; +assign wqe_req_head = (cur_state == WQE_REQ_s) ? { 'd0, + Cxt_qp_pd, + Cxt_rq_length, + Cxt_rq_lkey, + Cxt_rq_entry_sz_log, + PktHeader_local_qpn} : 'd0; +assign wqe_req_start = (cur_state == WQE_REQ_s) ? 'd1 : 'd0; +assign wqe_req_last = (cur_state == WQE_REQ_s) ? 'd1 : 'd0; + +//-- wqe_resp_ready -- +always @(*) begin + if(rst) begin + wqe_resp_ready = 'd0; + end + else if(cur_state == NEXT_UNIT_s) begin + wqe_resp_ready = 'd1; + end + else if(cur_state == DATA_UNIT_s && (PktHeader_net_opcode == `RDMA_WRITE_LAST_WITH_IMM || PktHeader_net_opcode == `RDMA_WRITE_ONLY_WITH_IMM)) begin + wqe_resp_ready = 'd1; + end + else if(cur_state == DATA_UNIT_s && (PktHeader_net_opcode != `RDMA_WRITE_LAST_WITH_IMM && PktHeader_net_opcode != `RDMA_WRITE_ONLY_WITH_IMM)) begin + if(pkt_length_left == 0) begin + wqe_resp_ready = 'd1; + end + else if(parsed_msg_length + DataUnit_byte_cnt <= msg_offset_doutb) begin + wqe_resp_ready = 'd1; + end + else begin + wqe_resp_ready = 'd0; + end + end + else if(cur_state == MR_FOR_SEND_s && fetch_mr_ingress_valid && fetch_mr_ingress_ready) begin + wqe_resp_ready = 'd1; + end + else begin + wqe_resp_ready = 'd0; + end +end + +//-- cache_offset_wen -- +//-- cache_offset_addr -- +//-- cache_offset_din -- +always @(*) begin + if(rst) begin + cache_offset_wen = 'd0; + cache_offset_addr = 'd0; + cache_offset_din = 'd0; + end + else if(cur_state == NEXT_UNIT_s) begin + cache_offset_wen = 'd0; + cache_offset_addr = PktHeader_local_qpn; + cache_offset_din = 'd0; + end + else if(cur_state == UPDATE_RQ_s) begin //Current WQE is finished + if(!NextUnit_next_wqe_valid) begin + cache_offset_wen = 'd1; + cache_offset_addr = PktHeader_local_qpn; + cache_offset_din = 'd0; + end + else if(NextUnit_next_wqe_addr < rq_offset_dout) begin //SQ wrap back + cache_offset_wen = 'd1; + cache_offset_addr = PktHeader_local_qpn; + cache_offset_din = 'd0; + end + else if(cache_offset_dout + (NextUnit_next_wqe_addr - rq_offset_dout) + NextUnit_next_wqe_size > `RQ_CACHE_SLOT_NUM) begin //Next WQE cross Cache Block boundary + cache_offset_wen = 'd1; + cache_offset_addr = PktHeader_local_qpn; + cache_offset_din = 'd0; + end + else begin //Next WQE is in cache + cache_offset_wen = 'd1; + cache_offset_addr = PktHeader_local_qpn; + cache_offset_din = cache_offset_dout + (NextUnit_next_wqe_addr - rq_offset_dout); + end + end + else begin + cache_offset_wen = 'd0; + cache_offset_addr = PktHeader_local_qpn; + cache_offset_din = 'd0; + end +end + +//-- rq_offset_wen -- +//-- rq_offset_addr -- +//-- rq_offset_din -- +always @(*) begin + if(rst) begin + rq_offset_wen = 'd0; + rq_offset_addr = 'd0; + rq_offset_din = 'd0; + end + else if(cur_state == IDLE_s) begin + rq_offset_wen = 'd0; + rq_offset_addr = 'd0; + rq_offset_din = 'd0; + end + else if(cur_state == NEXT_UNIT_s) begin + rq_offset_wen = 'd0; + rq_offset_addr = PktHeader_local_qpn; + rq_offset_din = 'd0; + end + else if(cur_state == UPDATE_RQ_s) begin + rq_offset_wen = 'd1; + rq_offset_addr = PktHeader_local_qpn; + rq_offset_din = Cxt_rq_length - (rq_offset_dout + NextUnit_cur_wqe_size_aligned) * 16 < (32'd1 << Cxt_rq_entry_sz_log) ? 'd0 : rq_offset_dout + NextUnit_cur_wqe_size_aligned; + end + else begin + rq_offset_wen = 'd0; + rq_offset_addr = PktHeader_local_qpn; + rq_offset_din = 'd0; + end +end + +// TODO, need to synchronize with WQEFetcher, helping it distinguish whether WQE cache buffer is valid +// cache_owned_wen -- +// cache_owned_addr -- +// cache_owned_din -- +always @(*) begin + if(rst) begin + cache_owned_wen = 'd0; + cache_owned_addr = 'd0; + cache_owned_din = 'd0; + end + else if(cur_state == IDLE_s) begin + cache_owned_wen = 'd0; + cache_owned_addr = 'd0; + cache_owned_din = 'd0; + end + else if(cur_state == NEXT_UNIT_s) begin + cache_owned_wen = 'd0; + cache_owned_addr = PktHeader_local_qpn; + cache_owned_din = 'd0; + end + else if(cur_state == UPDATE_RQ_s) begin //Current WQE has been finished + if(cache_owned_dout[`QP_NUM_LOG - `RQ_CACHE_CELL_NUM_LOG - 1 : 0] != PktHeader_local_qpn[`QP_NUM_LOG - 1 : 4]) begin //Curretn cell is already been replaced by another QP, do not touch it + cache_owned_wen = 'd0; + cache_owned_addr = PktHeader_local_qpn; + cache_owned_din = 'd0; + end + else if(!NextUnit_next_wqe_valid) begin + cache_owned_wen = 'd1; + cache_owned_addr = PktHeader_local_qpn; + cache_owned_din = 'd0; + end + else if(NextUnit_next_wqe_valid && NextUnit_next_wqe_addr == 0) begin //Wrap back to SQ head, clear cache cell state + cache_owned_wen = 'd1; + cache_owned_addr = PktHeader_local_qpn; + cache_owned_din = 'd0; + end + else if(NextUnit_next_wqe_valid && (cache_offset_dout + NextUnit_cur_wqe_size_aligned + NextUnit_next_wqe_size_aligned > `RQ_CACHE_SLOT_NUM)) begin //Cross Cache cell boundary + cache_owned_wen = 'd1; + cache_owned_addr = PktHeader_local_qpn; + cache_owned_din = 'd0; + end + else begin + cache_owned_wen = 'd0; + cache_owned_addr = PktHeader_local_qpn; + cache_owned_din = 'd0; + end + end + else begin + cache_owned_wen = 'd0; + cache_owned_addr = PktHeader_local_qpn; + cache_owned_din = 'd0; + end +end + + +//-- msg_offset_wea -- +//-- msg_offset_addra -- +//-- msg_offset_dina -- +always @(*) begin + if (rst) begin + msg_offset_wea = 'd0; + msg_offset_addra = 'd0; + msg_offset_dina = 'd0; + end + else if (cur_state == DATA_UNIT_s && wqe_resp_valid) begin + if(msg_offset_doutb >= parsed_msg_length + DataUnit_byte_cnt) begin + msg_offset_wea = 'd0; + msg_offset_addra = PktHeader_local_qpn; + msg_offset_dina = 'd0; + end + else begin + msg_offset_wea = 'd0; + msg_offset_addra = PktHeader_local_qpn; + msg_offset_dina = 'd0; + end + end + else if(cur_state == MR_FOR_SEND_s && fetch_mr_ingress_valid && fetch_mr_ingress_ready) begin + if(pkt_length_left <= parsed_msg_length + DataUnit_byte_cnt - msg_offset_doutb) begin + msg_offset_wea = 'd1; + msg_offset_addra = PktHeader_local_qpn; + msg_offset_dina = msg_offset_doutb + pkt_length_left; + end + else begin + msg_offset_wea = 'd1; + msg_offset_addra = PktHeader_local_qpn; + msg_offset_dina = parsed_msg_length + DataUnit_byte_cnt - msg_offset_doutb; + end + end + else if(cur_state == UPDATE_RQ_s) begin + msg_offset_wea = 'd1; + msg_offset_addra = PktHeader_local_qpn; + msg_offset_dina = 'd0; + end + else begin + msg_offset_wea = 'd0; + msg_offset_addra = 'd0; + msg_offset_dina = 'd0; + end +end + +//-- msg_offset_addrb -- +assign msg_offset_addrb = PktHeader_local_qpn; + +//-- cq_req_valid -- +//-- cq_req_head -- +assign cq_req_valid = (cur_state == CQ_REQ_s) ? 'd1 : 'd0; +assign cq_req_head = (cur_state == CQ_REQ_s) ? {Cxt_cq_length, 8'd0, Cxt_cqn} : 'd0; + +//-- cq_resp_ready -- +assign cq_resp_ready = (cur_state == CQ_RESP_s) ? 'd1 : 'd0; + +//-- eq_req_valid -- +//-- eq_req_head -- +assign eq_req_valid = (cur_state == EQ_REQ_s) ? 'd1 : 'd0; +assign eq_req_head = (cur_state == EQ_REQ_s) ? {Cxt_eq_length, 8'd0, Cxt_eqn} : 'd0; + +//-- eq_resp_ready -- +assign eq_resp_ready = (cur_state == EQ_RESP_s) ? 'd1 : 'd0; + +/********************************************************* MR Request Decode : Begin ***********************************************************/ +wire [`MAX_QP_NUM_LOG - 1 : 0] queue_index; +assign queue_index = {'d0, PktHeader_local_qpn[`QP_NUM_LOG - 1 : 0]}; + +//-- ingress_slot_count -- +//-- ingress_common_head -- +assign ingress_slot_count = (cur_state == MR_FOR_SEND_s) ? 'd1 : + (cur_state ==MR_FOR_WRITE_s) ? 'd1 : + (cur_state == MR_FOR_READ_s) ? 'd1 : + (cur_state == MR_FOR_CQ_s) ? 'd1 : + (cur_state == MR_FOR_EQ_s) ? 'd1 : + (cur_state == GEN_ACK_s) ? 'd1 : 'd0; + +assign ingress_common_head = (cur_state == MR_FOR_SEND_s) ? {`NO_BYPASS, ingress_slot_count, queue_index} : + (cur_state == MR_FOR_WRITE_s) ? {`NO_BYPASS, ingress_slot_count, queue_index} : + (cur_state == MR_FOR_READ_s) ? {`NO_BYPASS, ingress_slot_count, queue_index} : + (cur_state == MR_FOR_CQ_s) ? {`NO_BYPASS, ingress_slot_count, queue_index} : + (cur_state == MR_FOR_EQ_s) ? {`NO_BYPASS, ingress_slot_count, queue_index} : + (cur_state == GEN_ACK_s) ? {`BYPASS_MODE, ingress_slot_count, queue_index} : 'd0; + +//-- fetch_mr_ingress_valid -- +assign fetch_mr_ingress_valid = (cur_state == MR_FOR_SEND_s) ? 'd1 : + (cur_state == MR_FOR_WRITE_s) ? 'd1 : + (cur_state == MR_FOR_READ_s) ? 'd1 : + (cur_state == MR_FOR_CQ_s) ? 'd1 : + (cur_state == MR_FOR_EQ_s) ? 'd1 : + (cur_state == GEN_ACK_s) ? 'd1 : 'd0; + +//-- fetch_mr_ingress_head -- +assign fetch_mr_ingress_head = (cur_state == MR_FOR_SEND_s) ? {mr_length, mr_laddr, mr_lkey, mr_pd, mr_flags, ingress_common_head} : + (cur_state == MR_FOR_WRITE_s) ? {mr_length, mr_laddr, mr_lkey, mr_pd, mr_flags, ingress_common_head} : + (cur_state == MR_FOR_READ_s) ? {mr_length, mr_laddr, mr_lkey, mr_pd, mr_flags, ingress_common_head} : + (cur_state == MR_FOR_CQ_s) ? {mr_length, mr_laddr, mr_lkey, mr_pd, mr_flags, ingress_common_head} : + (cur_state == MR_FOR_EQ_s) ? {mr_length, mr_laddr, mr_lkey, mr_pd, mr_flags, ingress_common_head} : + (cur_state == GEN_ACK_s) ? {'d0, ingress_common_head} : 'd0; + +//-- fetch_mr_ingress_data -- //Metadata passed to next pipeline stage +assign fetch_mr_ingress_data = (cur_state == MR_FOR_SEND_s) ? {32'd0, PktHeader_pkt_start_addr, PktHeader_sip, PktHeader_dip, PktHeader_smac, PktHeader_dmac, 16'd0, PktHeader_pkt_length, PktHeader_immediate, PktHeader_service_type, PktHeader_net_opcode, PktHeader_remote_qpn, tail_indicator, PktHeader_local_qpn} : + (cur_state == MR_FOR_WRITE_s) ? {32'd0, PktHeader_pkt_start_addr, PktHeader_sip, PktHeader_dip, PktHeader_smac, PktHeader_dmac, 16'd0, PktHeader_pkt_length, PktHeader_immediate, PktHeader_service_type, PktHeader_net_opcode, PktHeader_remote_qpn, `TAIL_FLAG, PktHeader_local_qpn} : + (cur_state == MR_FOR_READ_s) ? {32'd0, PktHeader_pkt_start_addr, PktHeader_sip, PktHeader_dip, PktHeader_smac, PktHeader_dmac, 16'd0, PktHeader_pkt_length, PktHeader_immediate, PktHeader_service_type, PktHeader_resp_opcode, PktHeader_remote_qpn, `TAIL_FLAG, PktHeader_local_qpn} : + (cur_state == MR_FOR_CQ_s) ? {ori_wqe_addr, PktHeader_pkt_start_addr, PktHeader_sip, PktHeader_dip, PktHeader_smac, PktHeader_dmac, 11'd0, PktHeader_net_opcode, PktHeader_pkt_length, PktHeader_immediate, PktHeader_service_type, `GEN_CQE, PktHeader_remote_qpn, `TAIL_FLAG, PktHeader_local_qpn} : + (cur_state == MR_FOR_EQ_s) ? {32'd0, PktHeader_pkt_start_addr, PktHeader_sip, PktHeader_dip, PktHeader_smac, PktHeader_dmac, 16'd0, PktHeader_pkt_length, PktHeader_immediate, PktHeader_service_type, `GEN_EVENT, PktHeader_remote_qpn, `TAIL_FLAG, PktHeader_local_qpn} : + (cur_state == GEN_ACK_s) ? {32'd0, PktHeader_pkt_start_addr, PktHeader_sip, PktHeader_dip, PktHeader_smac, PktHeader_dmac, 16'd0, PktHeader_pkt_length, PktHeader_immediate, PktHeader_service_type, `ACKNOWLEDGE, PktHeader_remote_qpn, `TAIL_FLAG, PktHeader_local_qpn} : 'd0; + +//-- fetch_mr_ingress_start -- +assign fetch_mr_ingress_start = (cur_state == MR_FOR_SEND_s) ? 'd1 : + (cur_state == MR_FOR_WRITE_s) ? 'd1 : + (cur_state == MR_FOR_READ_s) ? 'd1 : + (cur_state == MR_FOR_CQ_s) ? 'd1 : + (cur_state == MR_FOR_EQ_s) ? 'd1 : + (cur_state == GEN_ACK_s) ? 'd1 : 'd0; + +//-- fetch_mr_ingress_last -- +assign fetch_mr_ingress_last = (cur_state == MR_FOR_SEND_s) ? 'd1 : + (cur_state == MR_FOR_WRITE_s) ? 'd1 : + (cur_state == MR_FOR_READ_s) ? 'd1 : + (cur_state == MR_FOR_CQ_s) ? 'd1 : + (cur_state == MR_FOR_EQ_s) ? 'd1 : + (cur_state == GEN_ACK_s) ? 'd1 : 'd0; + +//-- mr_length -- +assign mr_length = (cur_state == MR_FOR_SEND_s) ? (pkt_length_left < parsed_msg_length + DataUnit_byte_cnt - msg_offset_doutb ? pkt_length_left : parsed_msg_length + DataUnit_byte_cnt - msg_offset_doutb) : + (cur_state == MR_FOR_WRITE_s) ? PktHeader_pkt_length : + (cur_state == MR_FOR_READ_s) ? PktHeader_pkt_length : + (cur_state == MR_FOR_CQ_s) ? `CQE_LENGTH : + (cur_state == MR_FOR_EQ_s) ? `EVENT_LENGTH : 'd0; + +//-- mr_laddr -- +assign mr_laddr = (cur_state == MR_FOR_SEND_s) ? DataUnit_laddr + (msg_offset_doutb - parsed_msg_length) : + (cur_state == MR_FOR_WRITE_s) ? PktHeader_raddr : + (cur_state == MR_FOR_READ_s) ? PktHeader_raddr : + (cur_state == MR_FOR_CQ_s) ? cq_offset : + (cur_state == MR_FOR_EQ_s) ? eq_offset : 'd0; + +//-- mr_lkey -- +assign mr_lkey = (cur_state == MR_FOR_SEND_s) ? DataUnit_lkey : + (cur_state == MR_FOR_WRITE_s) ? PktHeader_rkey : + (cur_state == MR_FOR_READ_s) ? PktHeader_rkey : + (cur_state == MR_FOR_CQ_s) ? Cxt_cq_lkey : + (cur_state == MR_FOR_EQ_s) ? Cxt_eq_lkey : 'd0;; + +//-- mr_pd -- +assign mr_pd = (cur_state == MR_FOR_SEND_s) ? Cxt_qp_pd : + (cur_state == MR_FOR_WRITE_s) ? Cxt_qp_pd : + (cur_state == MR_FOR_READ_s) ? Cxt_qp_pd : + (cur_state == MR_FOR_CQ_s) ? Cxt_cq_pd : + (cur_state == MR_FOR_EQ_s) ? Cxt_eq_pd : 'd0; + +//-- mr_flag_sw_owns -- +//-- mr_flag_absolute_addr -- +//-- mr_flag_relative_addr -- +//-- mr_flag_mio -- +//-- mr_flag_bind_enable -- +//-- mr_flag_physical -- +//-- mr_flag_on_demand -- +//-- mr_flag_zero_based -- +//-- mr_flag_mw_bind -- +//-- mr_remote_read -- +//-- mr_remote_write -- +//-- mr_local_write -- +always @(*) begin + if(rst) begin + mr_flag_sw_owns = 'd0; + mr_flag_absolute_addr = 'd0; + mr_flag_relative_addr = 'd0; + mr_flag_mio = 'd0; + mr_flag_bind_enable = 'd0; + mr_flag_physical = 'd0; + mr_flag_region = 'd0; + mr_flag_on_demand = 'd0; + mr_flag_zero_based = 'd0; + mr_flag_mw_bind = 'd0; + mr_flag_remote_read = 'd0; + mr_flag_remote_write = 'd0; + mr_flag_local_write = 'd0; + end + else if(cur_state == MR_FOR_SEND_s) begin + mr_flag_sw_owns = 'd0; + mr_flag_absolute_addr = 'd1; + mr_flag_relative_addr = 'd0; + mr_flag_mio = 'd0; + mr_flag_bind_enable = 'd0; + mr_flag_physical = 'd0; + mr_flag_region = 'd0; + mr_flag_on_demand = 'd0; + mr_flag_zero_based = 'd0; + mr_flag_mw_bind = 'd0; + mr_flag_remote_read = 'd0; + mr_flag_remote_write = 'd0; + mr_flag_local_write = 'd1; + end + else if(cur_state == MR_FOR_WRITE_s) begin + mr_flag_sw_owns = 'd0; + mr_flag_absolute_addr = 'd1; + mr_flag_relative_addr = 'd0; + mr_flag_mio = 'd0; + mr_flag_bind_enable = 'd0; + mr_flag_physical = 'd0; + mr_flag_region = 'd0; + mr_flag_on_demand = 'd0; + mr_flag_zero_based = 'd0; + mr_flag_mw_bind = 'd0; + mr_flag_remote_read = 'd0; + mr_flag_remote_write = 'd1; + mr_flag_local_write = 'd0; + end + else if(cur_state == MR_FOR_READ_s) begin + mr_flag_sw_owns = 'd0; + mr_flag_absolute_addr = 'd1; + mr_flag_relative_addr = 'd0; + mr_flag_mio = 'd0; + mr_flag_bind_enable = 'd0; + mr_flag_physical = 'd0; + mr_flag_region = 'd0; + mr_flag_on_demand = 'd0; + mr_flag_zero_based = 'd0; + mr_flag_mw_bind = 'd0; + mr_flag_remote_read = 'd1; + mr_flag_remote_write = 'd0; + mr_flag_local_write = 'd0; + end + else if(cur_state == MR_FOR_CQ_s) begin + mr_flag_sw_owns = 'd0; + mr_flag_absolute_addr = 'd0; + mr_flag_relative_addr = 'd1; + mr_flag_mio = 'd0; + mr_flag_bind_enable = 'd0; + mr_flag_physical = 'd0; + mr_flag_region = 'd0; + mr_flag_on_demand = 'd0; + mr_flag_zero_based = 'd0; + mr_flag_mw_bind = 'd0; + mr_flag_remote_read = 'd0; + mr_flag_remote_write = 'd0; + mr_flag_local_write = 'd1; + end + else if(cur_state == MR_FOR_EQ_s) begin + mr_flag_sw_owns = 'd0; + mr_flag_absolute_addr = 'd0; + mr_flag_relative_addr = 'd1; + mr_flag_mio = 'd0; + mr_flag_bind_enable = 'd0; + mr_flag_physical = 'd0; + mr_flag_region = 'd0; + mr_flag_on_demand = 'd0; + mr_flag_zero_based = 'd0; + mr_flag_mw_bind = 'd0; + mr_flag_remote_read = 'd0; + mr_flag_remote_write = 'd0; + mr_flag_local_write = 'd1; + end + else begin + mr_flag_sw_owns = 'd0; + mr_flag_absolute_addr = 'd0; + mr_flag_relative_addr = 'd1; + mr_flag_mio = 'd0; + mr_flag_bind_enable = 'd0; + mr_flag_physical = 'd0; + mr_flag_region = 'd0; + mr_flag_on_demand = 'd0; + mr_flag_zero_based = 'd0; + mr_flag_mw_bind = 'd0; + mr_flag_remote_read = 'd0; + mr_flag_remote_write = 'd0; + mr_flag_local_write = 'd0; + end +end + +//-- mr_flags -- +assign mr_flags = (cur_state == MR_FOR_SEND_s || cur_state == MR_FOR_WRITE_s || cur_state == MR_FOR_READ_s || cur_state == MR_FOR_CQ_s || cur_state == MR_FOR_EQ_s) ? + { + mr_flag_sw_owns, + mr_flag_absolute_addr, + mr_flag_relative_addr, + 8'd0, + mr_flag_mio, + 1'd0, + mr_flag_bind_enable, + 5'd0, + mr_flag_physical, + mr_flag_region, + 1'd0, + mr_flag_on_demand, + mr_flag_zero_based, + mr_flag_mw_bind, + mr_flag_remote_read, + mr_flag_remote_write, + mr_flag_local_write + } : 'd0; +/********************************************************* MR Request Decode : End *************************************************************/ + +/*------------------------------------------- Variables Decode : End ----------------------------------------------***/ + +/*------------------------------------------- Local Macros Undef : Begin --------------------------------------------*/ +`undef HEADER_LOCAL_QPN_OFFSET +`undef HEADER_REMOTE_QPN_OFFSET +`undef HEADER_NET_OPCODE_OFFSET +`undef HEADER_SERVICE_TYPE_OFFSET +`undef HEADER_IMMEDIATE_OFFSET +`undef HEADER_RKEY_OFFSET +`undef HEADER_RADDR_OFFSET +`undef HEADER_DMAC_OFFSET +`undef HEADER_SMAC_OFFSET +`undef HEADER_DIP_OFFSET +`undef HEADER_SIP_OFFSET +`undef HEADER_PKT_START_ADDR_OFFSET +`undef HEADER_PKT_LENGTH_OFFSET +/*------------------------------------------- Local Macros Undef : End ----------------------------------------------*/ + +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/RPCSubsystem/RDMACore/ResponderCore/ReqRecvCore/ReqRecvCore_Thread_3.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/RPCSubsystem/RDMACore/ResponderCore/ReqRecvCore/ReqRecvCore_Thread_3.v new file mode 100644 index 0000000000000000000000000000000000000000..3a65c43ae8e5633fd3bcc520769d27e01c56a0b0 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/RPCSubsystem/RDMACore/ResponderCore/ReqRecvCore/ReqRecvCore_Thread_3.v @@ -0,0 +1,785 @@ + /*------------------------------------------- Module Description : Begin ---------------------------------------------- +Name: ReqRecvCore_Thread_3 +Author: YangFan +Function: 1.Generate DMA Write. +--------------------------------------------- Module Decription : End -----------------------------------------------*/ + +/*------------------------------------------- Timescale Definition : Begin ------------------------------------------*/ +`timescale 1ns / 1ps +/*------------------------------------------- Timescale Definition : End --------------------------------------------*/ + +/*------------------------------------------- Included Files : Begin ------------------------------------------------*/ +`include "protocol_engine_def.vh" +/*------------------------------------------- Included Files : End --------------------------------------------------*/ + +/*------------------------------------------- Input/Output Definition : Begin ---------------------------------------*/ +module ReqRecvCore_Thread_3 +#( + parameter EGRESS_MR_HEAD_WIDTH = 128, + parameter EGRESS_MR_DATA_WIDTH = 256 +) +( + input wire clk, + input wire rst, + +//Interface with OoOStation(For MRMgt) + input wire fetch_mr_egress_valid, + input wire [`RX_REQ_OOO_MR_EGRESS_HEAD_WIDTH - 1 : 0] fetch_mr_egress_head, + input wire [`RX_REQ_OOO_MR_EGRESS_DATA_WIDTH - 1 : 0] fetch_mr_egress_data, + input wire fetch_mr_egress_start, + input wire fetch_mr_egress_last, + output wire fetch_mr_egress_ready, + +//Interface with Packet Buffer + output wire delete_req_valid, + output wire [`MAX_DB_SLOT_NUM_LOG * 2 - 1 : 0] delete_req_head, + input wire delete_req_ready, + + input wire delete_resp_valid, + input wire delete_resp_start, + input wire delete_resp_last, + input wire [`PACKET_BUFFER_SLOT_WIDTH - 1 : 0] delete_resp_data, + output wire delete_resp_ready, + +//DMA Write Interface + output reg scatter_req_wr_en, + output reg [`DMA_LENGTH_WIDTH * 2 + `DMA_ADDR_WIDTH - 1 : 0] scatter_req_din, + input wire scatter_req_prog_full, + + output reg scatter_data_wr_en, + output reg [`DMA_DATA_WIDTH - 1: 0] scatter_data_din, + input wire scatter_data_prog_full, + +//DMA Read Interface + output reg gather_req_wr_en, + output reg [`DMA_LENGTH_WIDTH * 2 + `DMA_ADDR_WIDTH - 1 : 0] gather_req_din, + input wire gather_req_prog_full, + + +//Interface with RespTransCore + output reg net_resp_wen, + output reg [`NET_REQ_META_WIDTH - 1 : 0] net_resp_din, + input wire net_resp_prog_full +); +/*------------------------------------------- Input/Output Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Macros Definition : Begin ---------------------------------------*/ +`define HEADER_LOCAL_QPN_OFFSET 23:0 +`define HEADER_TAIL_INDICATOR_OFFSET 31:24 +`define HEADER_REMOTE_QPN_OFFSET 55:32 +`define HEADER_NET_OPCODE_OFFSET 60:56 +`define HEADER_SERVICE_TYPE_OFFSET 63:61 +`define HEADER_IMMEDIATE_OFFSET 95:64 +`define HEADER_PKT_LENGTH_OFFSET 111:96 +`define HEADER_DMAC_OFFSET 175:128 +`define HEADER_SMAC_OFFSET 223:176 +`define HEADER_DIP_OFFSET 255:224 +`define HEADER_SIP_OFFSET 287:256 +`define HEADER_CQE_OPCODE_OFFSET 116:112 +`define HEADER_PKT_START_ADDR_OFFSET 303:288 +`define HEADER_ORI_WQE_ADDR_OFFSET 351:320 + +`define MCB_STATE_OFFSET 3:0 +`define MCB_VALID_0_OFFSET 27:24 +`define MCB_VALID_1_OFFSET 31:28 +`define MCB_PAGE_0_SIZE_OFFSET 63:32 +`define MCB_PAGE_0_ADDR_OFFSET 127:64 +`define MCB_PAGE_1_SIZE_OFFSET 159:128 +`define MCB_PAGE_1_ADDR_OFFSET 223:160 +`define MCB_TAIL_INDICATOR_OFFSET 231:224 +`define MCB_PKT_LENGTH_OFFSET 247:232 +`define MCB_PKT_START_ADDR_OFFSET 287:256 +/*------------------------------------------- Local Macros Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Variables Definition : Begin ------------------------------------*/ +reg [`MR_RESP_WIDTH - 1 : 0] mr_resp_bus; +reg [`PKT_META_BUS_WIDTH - 1 : 0] pkt_header_bus; +reg [`MCB_META_WIDTH - 1 : 0] mcb_meta_bus; + +wire [23:0] PktHeader_local_qpn; +wire [23:0] PktHeader_remote_qpn; +wire [7:0] PktHeader_tail_indicator; +wire [4:0] PktHeader_net_opcode; +wire [4:0] PktHeader_cqe_opcode; +wire [2:0] PktHeader_service_type; +wire [47:0] PktHeader_dmac; +wire [47:0] PktHeader_smac; +wire [31:0] PktHeader_dip; +wire [31:0] PktHeader_sip; +wire [31:0] PktHeader_immediate; +wire [15:0] PktHeader_pkt_length; +wire [15:0] PktHeader_pkt_start_addr; +wire [31:0] PktHeader_ori_wqe_addr; + +wire [3:0] mr_resp_state; +wire [3:0] mr_resp_valid_0; +wire [3:0] mr_resp_valid_1; +wire [31:0] mr_resp_size_0; +wire [31:0] mr_resp_size_1; +wire [63:0] mr_resp_phy_addr_0; +wire [63:0] mr_resp_phy_addr_1; + +wire [3:0] mcb_mr_state; +wire [3:0] mcb_mr_valid_0; +wire [3:0] mcb_mr_valid_1; +wire [31:0] mcb_mr_size_0; +wire [31:0] mcb_mr_size_1; +wire [63:0] mcb_mr_phy_addr_0; +wire [63:0] mcb_mr_phy_addr_1; +wire [7:0] mcb_tail_indicator; +wire [15:0] mcb_pkt_start_addr; +wire [15:0] mcb_pkt_length; + +wire mcb_enqueue_req_valid; +wire [`QP_NUM_LOG + `MAX_DMQ_SLOT_NUM_LOG - 1 : 0] mcb_enqueue_req_head; +wire [`MCB_SLOT_WIDTH - 1 : 0] mcb_enqueue_req_data; +wire mcb_enqueue_req_start; +wire mcb_enqueue_req_last; +wire mcb_enqueue_req_ready; + +wire mcb_dequeue_req_valid; +wire [`QP_NUM_LOG + `MAX_DMQ_SLOT_NUM_LOG - 1 : 0] mcb_dequeue_req_head; +wire mcb_dequeue_req_ready; + +wire mcb_dequeue_resp_valid; +wire [`QP_NUM_LOG + `MAX_DMQ_SLOT_NUM_LOG - 1 : 0] mcb_dequeue_resp_head; +wire mcb_dequeue_resp_start; +wire mcb_dequeue_resp_last; +wire mcb_dequeue_resp_ready; +wire [`MCB_SLOT_WIDTH - 1 : 0] mcb_dequeue_resp_data; + +wire [255:0] cqe_data; +reg [31:0] cqe_my_qpn; +reg [31:0] cqe_my_ee; +reg [31:0] cqe_rqpn; +reg [7:0] cqe_sl_ipok; +reg [7:0] cqe_g_mlpath; +reg [15:0] cqe_rlid; +reg [31:0] cqe_imm_etype_pkey_eec; +reg [31:0] cqe_byte_cnt; +reg [31:0] cqe_wqe; +reg [7:0] cqe_opcode; +reg [7:0] cqe_is_send; +reg [7:0] cqe_owner; + +wire [0:0] byte_cnt_buffer_wea; +wire [`QP_NUM_LOG - 1 : 0] byte_cnt_buffer_addra; +wire [31:0] byte_cnt_buffer_dina; + +wire [`QP_NUM_LOG - 1 : 0] byte_cnt_buffer_addrb; +wire [31:0] byte_cnt_buffer_doutb; +/*------------------------------------------- Local Variables Definition : End --------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : Begin ---------------------------------------*/ +/* Why we need this DMQ? + The reason is that a send packet may be mapped to different SGL. In ReqRecvCore_Thread_2, we have issued multiple MR reqs for a Send, these MRs will be returned + in order for the same QP, but may be interweaved with MR reqs of other QPs. Since a Send pkt should be DMAed atomicly, we use this DMQ to ensure that a Send will be + executed when multiple MRs are collected entirely. +*/ + +DynamicMultiQueue #( + .SLOT_WIDTH ( 512 ), + .SLOT_NUM ( 32 ), + .QUEUE_NUM ( `QP_NUM ) +) MetaCollectionBuffer_Inst ( + .clk ( clk ), + .rst ( rst ), + + .i_enqueue_req_valid ( mcb_enqueue_req_valid ), + .iv_enqueue_req_head ( mcb_enqueue_req_head ), + .iv_enqueue_req_data ( mcb_enqueue_req_data ), + .i_enqueue_req_start ( mcb_enqueue_req_start ), + .i_enqueue_req_last ( mcb_enqueue_req_last ), + .o_enqueue_req_ready ( mcb_enqueue_req_ready ), + + .i_empty_req_valid ( mcb_empty_req_valid ), + .iv_empty_req_head ( mcb_empty_req_head ), + .o_empty_req_ready ( mcb_empty_req_ready ), + + .o_empty_resp_valid ( mcb_empty_resp_valid ), + .ov_empty_resp_head ( mcb_empty_resp_head ), + .i_empty_resp_ready ( mcb_empty_resp_ready ), + + .i_dequeue_req_valid ( mcb_dequeue_req_valid ), + .iv_dequeue_req_head ( mcb_dequeue_req_head ), + .o_dequeue_req_ready ( mcb_dequeue_req_ready ), + + .o_dequeue_resp_valid ( mcb_dequeue_resp_valid ), + .ov_dequeue_resp_head ( mcb_dequeue_resp_head ), + .o_dequeue_resp_start ( mcb_dequeue_resp_start ), + .o_dequeue_resp_last ( mcb_dequeue_resp_last ), + .i_dequeue_resp_ready ( mcb_dequeue_resp_ready ), + .ov_dequeue_resp_data ( mcb_dequeue_resp_data ), + + .i_modify_head_req_valid ( 'd0 ), + .iv_modify_head_req_head ( 'd0 ), + .iv_modify_head_req_data ( 'd0 ), + .o_modify_head_req_ready ( ), + + .i_get_req_valid ( 'd0 ), + .iv_get_req_head ( 'd0 ), + .o_get_req_ready ( ), + + .o_get_resp_valid ( ), + .ov_get_resp_head ( ), + .o_get_resp_start ( ), + .o_get_resp_last ( ), + .ov_get_resp_data ( ), + .o_get_resp_empty ( ), + .i_get_resp_ready ( 'd0 ) +); + + +SRAM_SDP_Template #( + .RAM_WIDTH ( 32 ), + .RAM_DEPTH ( `QP_NUM ) +) +CacheBuffer +( + .clk ( clk ), + .rst ( rst ), + + .wea ( byte_cnt_buffer_wea ), + .addra ( byte_cnt_buffer_addra ), + .dina ( byte_cnt_buffer_dina ), + + .addrb ( byte_cnt_buffer_addrb ), + .doutb ( byte_cnt_buffer_doutb ) +); +/*------------------------------------------- Submodules Instatiation : End -----------------------------------------*/ + +/*------------------------------------------- State Machine Definition : Begin --------------------------------------*/ +reg [4:0] cur_state; +reg [4:0] next_state; + +parameter [4:0] IDLE_s = 5'd1, + JUDGE_s = 5'd2, + ENQUEUE_META_REQ_s = 5'd3, + DEQUEUE_META_REQ_s = 5'd4, + DEQUEUE_META_RESP_s = 5'd5, + GET_SEND_PAYLOAD_s = 5'd6, + GET_WRITE_PAYLOAD_s = 5'd7, + DMA_SEND_PAGE_0_REQ_s = 5'd8, + DMA_SEND_PAGE_1_REQ_s = 5'd9, + DMA_SEND_DATA_s = 5'd10, + DMA_WRITE_PAGE_0_REQ_s = 5'd11, + DMA_WRITE_PAGE_1_REQ_s = 5'd12, + DMA_WRITE_DATA_s = 5'd13, + DMA_CQE_s = 5'd14, + DMA_EVENT_s = 5'd15, + DMA_INT_s = 5'd16, + DMA_READ_PAGE_0_REQ_s = 5'd17, + DMA_READ_PAGE_1_REQ_s = 5'd18, + GEN_RESP_s = 5'd19; + +always @(posedge clk or posedge rst) begin + if(rst) begin + cur_state <= IDLE_s; + end + else begin + cur_state <= next_state; + end +end + +always @(*) begin + case(cur_state) + IDLE_s: if(fetch_mr_egress_valid) begin + next_state = JUDGE_s; + end + else begin + next_state = IDLE_s; + end + JUDGE_s: if(PktHeader_net_opcode == `SEND_FIRST || PktHeader_net_opcode == `SEND_MIDDLE || PktHeader_net_opcode == `SEND_LAST || + PktHeader_net_opcode == `SEND_ONLY || PktHeader_net_opcode == `SEND_LAST_WITH_IMM || PktHeader_net_opcode == `SEND_ONLY_WITH_IMM) begin //Not empty, need to enqueue current REQ, current Req must be Send. If current Req is not send DMQ must be empty + next_state = ENQUEUE_META_REQ_s; + end + else if(PktHeader_net_opcode == `RDMA_WRITE_FIRST || PktHeader_net_opcode == `RDMA_WRITE_MIDDLE || PktHeader_net_opcode == `RDMA_WRITE_LAST || + PktHeader_net_opcode == `RDMA_WRITE_ONLY || PktHeader_net_opcode == `RDMA_WRITE_LAST_WITH_IMM || PktHeader_net_opcode == `RDMA_WRITE_ONLY_WITH_IMM) begin + next_state = GET_WRITE_PAYLOAD_s; + end + else if(PktHeader_net_opcode == `RDMA_READ_RESPONSE_FIRST || PktHeader_net_opcode == `RDMA_READ_RESPONSE_MIDDLE || PktHeader_net_opcode == `RDMA_READ_RESPONSE_LAST || + PktHeader_net_opcode == `RDMA_READ_RESPONSE_ONLY) begin + next_state = DMA_READ_PAGE_0_REQ_s; + end + else if(PktHeader_net_opcode == `ACKNOWLEDGE) begin + next_state = GEN_RESP_s; + end + else if(PktHeader_net_opcode == `GEN_CQE) begin + next_state = DMA_CQE_s; + end + else if(PktHeader_net_opcode == `GEN_EVENT) begin + next_state = DMA_EVENT_s; + end + else if(PktHeader_net_opcode == `GEN_INT) begin + next_state = DMA_INT_s; + end + else begin //Unexpected state + next_state = IDLE_s; + end + ENQUEUE_META_REQ_s: if(mcb_enqueue_req_valid && mcb_enqueue_req_ready) begin + if(PktHeader_tail_indicator == `TAIL_FLAG) begin + next_state = DEQUEUE_META_REQ_s; + end + else begin + next_state = IDLE_s; + end + end + else begin + next_state = ENQUEUE_META_REQ_s; + end + DEQUEUE_META_REQ_s: if(mcb_dequeue_req_valid && mcb_dequeue_req_ready) begin + next_state = DEQUEUE_META_RESP_s; + end + else begin + next_state = DEQUEUE_META_REQ_s; + end + DEQUEUE_META_RESP_s: if(mcb_dequeue_resp_valid && mcb_dequeue_resp_ready) begin + next_state = DMA_SEND_PAGE_0_REQ_s; + end + else begin + next_state = DEQUEUE_META_RESP_s; + end + DMA_SEND_PAGE_0_REQ_s: if(!scatter_req_prog_full) begin + if(mcb_mr_valid_1) begin + next_state = DMA_SEND_PAGE_1_REQ_s; + end + else if(mcb_tail_indicator == `TAIL_FLAG) begin + next_state = GET_SEND_PAYLOAD_s; + end + else begin + next_state = DEQUEUE_META_REQ_s; + end + end + else begin + next_state = DMA_SEND_PAGE_0_REQ_s; + end + DMA_SEND_PAGE_1_REQ_s: if(!scatter_req_prog_full) begin + if(mcb_tail_indicator == `TAIL_FLAG) begin + next_state = GET_SEND_PAYLOAD_s; + end + else begin + next_state = DEQUEUE_META_REQ_s; + end + end + else begin + next_state = DMA_SEND_PAGE_1_REQ_s; + end + GET_SEND_PAYLOAD_s: if(delete_req_valid && delete_req_ready) begin + next_state = DMA_SEND_DATA_s; + end + else begin + next_state = GET_SEND_PAYLOAD_s; + end + GET_WRITE_PAYLOAD_s: if(delete_req_valid && delete_req_ready) begin + next_state = DMA_WRITE_PAGE_0_REQ_s; + end + else begin + next_state = GET_WRITE_PAYLOAD_s; + end + DMA_SEND_DATA_s: if(delete_resp_valid && delete_resp_last && !scatter_data_prog_full) begin + next_state = IDLE_s; + end + else begin + next_state = DMA_SEND_DATA_s; + end + DMA_WRITE_PAGE_0_REQ_s: if(!scatter_req_prog_full) begin + if(mr_resp_valid_1) begin + next_state = DMA_WRITE_PAGE_1_REQ_s; + end + else begin + next_state = DMA_WRITE_DATA_s; + end + end + else begin + next_state = DMA_WRITE_PAGE_0_REQ_s; + end + DMA_WRITE_PAGE_1_REQ_s: if(!scatter_req_prog_full) begin + next_state = DMA_WRITE_DATA_s; + end + else begin + next_state = DMA_WRITE_PAGE_1_REQ_s; + end + DMA_WRITE_DATA_s: if(delete_resp_valid && delete_resp_last && !scatter_data_prog_full) begin + next_state = IDLE_s; + end + else begin + next_state = DMA_WRITE_DATA_s; + end + DMA_CQE_s: if(!scatter_req_prog_full && !scatter_data_prog_full) begin + next_state = IDLE_s; + end + else begin + next_state = DMA_CQE_s; + end + DMA_EVENT_s: if(!scatter_req_prog_full && !scatter_data_prog_full) begin + next_state = IDLE_s; + end + else begin + next_state = DMA_EVENT_s; + end + DMA_INT_s: if(!scatter_req_prog_full && !scatter_data_prog_full) begin + next_state = IDLE_s; + end + else begin + next_state = DMA_INT_s; + end + DMA_READ_PAGE_0_REQ_s: if(!gather_req_prog_full) begin + if(mr_resp_valid_1) begin + next_state = DMA_READ_PAGE_1_REQ_s; + end + else begin + next_state = GEN_RESP_s; + end + end + else begin + next_state = DMA_READ_PAGE_0_REQ_s; + end + DMA_READ_PAGE_1_REQ_s: if(!gather_req_prog_full) begin + next_state = GEN_RESP_s; + end + else begin + next_state = DMA_READ_PAGE_1_REQ_s; + end + GEN_RESP_s: if(!net_resp_prog_full) begin + next_state = IDLE_s; + end + else begin + next_state = GEN_RESP_s; + end + default: next_state = IDLE_s; + endcase +end +/*------------------------------------------- State Machine Definition : End ----------------------------------------*/ + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ +//-- pkt_header_bus -- +//-- mr_resp_bus -- +always @(posedge clk or posedge rst) begin + if (rst) begin + pkt_header_bus <= 'd0; + mr_resp_bus <= 'd0; + end + else if (cur_state == IDLE_s && fetch_mr_egress_valid) begin + pkt_header_bus <= fetch_mr_egress_data; + mr_resp_bus <= fetch_mr_egress_head[`MR_RESP_WIDTH + `EGRESS_COMMON_HEAD_WIDTH - 1 : `EGRESS_COMMON_HEAD_WIDTH]; + end + else begin + pkt_header_bus <= pkt_header_bus; + mr_resp_bus <= mr_resp_bus; + end +end + +//-- PktHeader_local_qpn -- +//-- PktHeader_remote_qpn -- +//-- PktHeader_tail_indicator -- +//-- PktHeader_net_opcode -- +//-- PktHeader_service_type -- +//-- PktHeader_dmac -- +//-- PktHeader_smac -- +//-- PktHeader_dip -- +//-- PktHeader_sip -- +//-- PktHeader_immediate -- +//-- PktHeader_pkt_length -- +//-- PktHeader_ori_wqe_addr -- +//-- PktHeader_pkt_start_addr -- +assign PktHeader_local_qpn = pkt_header_bus[`HEADER_LOCAL_QPN_OFFSET]; +assign PktHeader_remote_qpn = pkt_header_bus[`HEADER_REMOTE_QPN_OFFSET]; +assign PktHeader_tail_indicator = pkt_header_bus[`HEADER_TAIL_INDICATOR_OFFSET]; +assign PktHeader_net_opcode = pkt_header_bus[`HEADER_NET_OPCODE_OFFSET]; +assign PktHeader_cqe_opcode = pkt_header_bus[`HEADER_CQE_OPCODE_OFFSET]; +assign PktHeader_service_type = pkt_header_bus[`HEADER_SERVICE_TYPE_OFFSET]; +assign PktHeader_dmac = pkt_header_bus[`HEADER_DMAC_OFFSET]; +assign PktHeader_smac = pkt_header_bus[`HEADER_SMAC_OFFSET]; +assign PktHeader_dip = pkt_header_bus[`HEADER_DIP_OFFSET]; +assign PktHeader_sip = pkt_header_bus[`HEADER_SIP_OFFSET]; +assign PktHeader_immediate = pkt_header_bus[`HEADER_IMMEDIATE_OFFSET]; +assign PktHeader_pkt_length = pkt_header_bus[`HEADER_PKT_LENGTH_OFFSET]; +assign PktHeader_ori_wqe_addr = pkt_header_bus[`HEADER_ORI_WQE_ADDR_OFFSET]; +assign PktHeader_pkt_start_addr = pkt_header_bus[`HEADER_PKT_START_ADDR_OFFSET]; + +//-- mr_resp_state -- +//-- mr_resp_valid_0 -- +//-- mr_resp_valid_1 -- +//-- mr_resp_size_0 -- +//-- mr_resp_size_1 -- +//-- mr_resp_phy_addr_0 -- +//-- mr_resp_phy_addr_1 -- +assign mr_resp_state = mr_resp_bus[`MR_RESP_STATE_OFFSET]; +assign mr_resp_valid_0 = mr_resp_bus[`MR_RESP_VALID_0_OFFSET]; +assign mr_resp_valid_1 = mr_resp_bus[`MR_RESP_VALID_1_OFFSET]; +assign mr_resp_size_0 = mr_resp_bus[`MR_RESP_SIZE_0_OFFSET]; +assign mr_resp_size_1 = mr_resp_bus[`MR_RESP_SIZE_1_OFFSET]; +assign mr_resp_phy_addr_0 = mr_resp_bus[`MR_RESP_ADDR_0_OFFSET]; +assign mr_resp_phy_addr_1 = mr_resp_bus[`MR_RESP_ADDR_1_OFFSET]; + +//-- mcb_meta_bus -- +always @(posedge clk or posedge rst) begin + if(rst) begin + mcb_meta_bus <= 'd0; + end + else if(cur_state == DEQUEUE_META_RESP_s && mcb_dequeue_resp_valid) begin + mcb_meta_bus <= mcb_dequeue_resp_data; + end + else begin + mcb_meta_bus <= mcb_meta_bus; + end +end + +//-- mcb_mr_state -- +//-- mcb_mr_valid_0 -- +//-- mcb_mr_valid_1 -- +//-- mcb_mr_size_0 -- +//-- mcb_mr_size_1 -- +//-- mcb_mr_phy_addr_0 -- +//-- mcb_mr_phy_addr_1 -- +//-- mcb_tail_indicator -- +//-- mcb_pkt_start_addr -- +//-- mcb_pkt_length -- +assign mcb_mr_state = mcb_meta_bus[`MCB_STATE_OFFSET]; +assign mcb_mr_valid_0 = mcb_meta_bus[`MCB_VALID_0_OFFSET]; +assign mcb_mr_valid_1 = mcb_meta_bus[`MCB_VALID_1_OFFSET]; +assign mcb_mr_size_0 = mcb_meta_bus[`MCB_PAGE_0_SIZE_OFFSET]; +assign mcb_mr_size_1 = mcb_meta_bus[`MCB_PAGE_1_SIZE_OFFSET]; +assign mcb_mr_phy_addr_0 = mcb_meta_bus[`MCB_PAGE_0_ADDR_OFFSET]; +assign mcb_mr_phy_addr_1 = mcb_meta_bus[`MCB_PAGE_1_ADDR_OFFSET]; +assign mcb_tail_indicator = mcb_meta_bus[`MCB_TAIL_INDICATOR_OFFSET]; +assign mcb_pkt_start_addr = mcb_meta_bus[`MCB_PKT_START_ADDR_OFFSET]; +assign mcb_pkt_length = mcb_meta_bus[`MCB_PKT_LENGTH_OFFSET]; + +//-- mcb_enqueue_req_valid -- +//-- mcb_enqueue_req_head -- +//-- mcb_enqueue_req_data -- +//-- mcb_enqueue_req_start -- +//-- mcb_enqueue_req_last -- +assign mcb_enqueue_req_valid = (cur_state == ENQUEUE_META_REQ_s) ? 'd1 : 'd0; +assign mcb_enqueue_req_head = (cur_state == ENQUEUE_META_REQ_s) ? {'d1, PktHeader_local_qpn[`MAX_QP_NUM_LOG - 1 : 0]} : 'd0; +assign mcb_enqueue_req_data = (cur_state == ENQUEUE_META_REQ_s) ? {PktHeader_pkt_start_addr, 8'd0, PktHeader_pkt_length, PktHeader_tail_indicator, mr_resp_phy_addr_1, mr_resp_size_1, mr_resp_phy_addr_0, mr_resp_size_0, mr_resp_valid_1, mr_resp_valid_0, 20'd0, mr_resp_state} : 'd0; +assign mcb_enqueue_req_start = (cur_state == ENQUEUE_META_REQ_s) ? 'd1 : 'd0; +assign mcb_enqueue_req_last = (cur_state == ENQUEUE_META_REQ_s) ? 'd1 : 'd0; + +//-- mcb_dequeue_req_valid -- +//-- mcb_dequeue_req_head -- +assign mcb_dequeue_req_valid = (cur_state == DEQUEUE_META_REQ_s) ? 'd1 : 'd0; +assign mcb_dequeue_req_head = (cur_state == DEQUEUE_META_REQ_s) ? {'d1, PktHeader_local_qpn[`MAX_QP_NUM_LOG - 1 : 0]} : 'd0; + +//-- mcb_dequeue_resp_ready -- +assign mcb_dequeue_resp_ready = (cur_state == DEQUEUE_META_RESP_s) ? 'd1 : 'd0; + + + +//-- fetch_mr_egress_ready -- +assign fetch_mr_egress_ready = (cur_state == IDLE_s) ? 'd1 : 'd0; + +//-- delete_req_valid -- +//-- delete_req_head -- +assign delete_req_valid = (cur_state == GET_SEND_PAYLOAD_s) ? 'd1 : + (cur_state == GET_WRITE_PAYLOAD_s) ? 'd1 : 'd0; +assign delete_req_head = (cur_state == GET_SEND_PAYLOAD_s) ? {(mcb_pkt_length[5:0] ? (mcb_pkt_length >> 6) + 1 : mcb_pkt_length >> 6), mcb_pkt_start_addr} : + (cur_state == GET_WRITE_PAYLOAD_s) ? {(PktHeader_pkt_length[5:0] ? (PktHeader_pkt_length >> 6) + 1 : PktHeader_pkt_length >> 6), PktHeader_pkt_start_addr} : 'd0; + +//-- delete_resp_ready -- +assign delete_resp_ready = (cur_state == DMA_SEND_DATA_s || cur_state == DMA_WRITE_DATA_s) ? !scatter_data_prog_full : 'd0; + +//-- scatter_req_wr_en -- +//-- scatter_req_din -- +always @(posedge clk or posedge rst) begin + if (rst) begin + scatter_req_wr_en <= 'd0; + scatter_req_din <= 'd0; + end + else if (cur_state == DMA_SEND_PAGE_0_REQ_s && !scatter_req_prog_full) begin + scatter_req_wr_en <= 'd1; + scatter_req_din <= {mcb_pkt_length, mcb_mr_size_0, mcb_mr_phy_addr_0}; + end + else if (cur_state == DMA_SEND_PAGE_1_REQ_s && !scatter_req_prog_full) begin + scatter_req_wr_en <= 'd1; + scatter_req_din <= {mcb_pkt_length, mcb_mr_size_1, mcb_mr_phy_addr_1}; + end + else if (cur_state == DMA_WRITE_PAGE_0_REQ_s && !scatter_req_prog_full) begin + scatter_req_wr_en <= 'd1; + scatter_req_din <= {PktHeader_pkt_length, mr_resp_size_0, mr_resp_phy_addr_0}; + end + else if (cur_state == DMA_WRITE_PAGE_1_REQ_s && !scatter_req_prog_full) begin + scatter_req_wr_en <= 'd1; + scatter_req_din <= {PktHeader_pkt_length, mr_resp_size_1, mr_resp_phy_addr_1}; + end + else if (cur_state == DMA_CQE_s && !scatter_req_prog_full && !scatter_data_prog_full) begin + scatter_req_wr_en <= 'd1; + scatter_req_din <= {`CQE_LENGTH, mr_resp_size_0, mr_resp_phy_addr_0}; + end + else begin + scatter_req_wr_en <= 'd0; + scatter_req_din <= 'd0; + end +end + +//-- scatter_data_wr_en -- +//-- scatter_data_din -- +always @(posedge clk or posedge rst) begin + if (rst) begin + scatter_data_wr_en <= 'd0; + scatter_data_din <= 'd0; + end + else if ((cur_state == DMA_SEND_DATA_s || cur_state == DMA_WRITE_DATA_s) && delete_resp_valid && !scatter_data_prog_full) begin + scatter_data_wr_en <= 'd1; + scatter_data_din <= delete_resp_data; + end + else if (cur_state == DMA_CQE_s && !scatter_req_prog_full && !scatter_data_prog_full) begin + scatter_data_wr_en <= 'd1; + scatter_data_din <= cqe_data; + end + else begin + scatter_data_wr_en <= 'd0; + scatter_data_din <= 'd0; + end +end + +//-- gather_req_wr_en -- +//-- gather_req_din -- +always @(posedge clk or posedge rst) begin + if (rst) begin + gather_req_wr_en <= 'd0; + gather_req_din <= 'd0; + end + else if (cur_state == DMA_READ_PAGE_0_REQ_s && !gather_req_prog_full) begin + gather_req_wr_en <= 'd1; + gather_req_din <= {PktHeader_pkt_length, mr_resp_size_0, mr_resp_phy_addr_0}; + end + else if (cur_state == DMA_READ_PAGE_1_REQ_s && !gather_req_prog_full) begin + gather_req_wr_en <= 'd1; + gather_req_din <= {PktHeader_pkt_length, mr_resp_size_1, mr_resp_phy_addr_1}; + end + else begin + gather_req_wr_en <= 'd0; + gather_req_din <= 'd0; + end +end + +//-- cqe_my_qpn -- +//-- cqe_my_ee -- +//-- cqe_rqpn -- +//-- cqe_sl_ipok -- +//-- cqe_g_mlpath -- +//-- cqe_rlid -- +//-- cqe_imm_etype_pkey_eec -- +//-- cqe_byte_cnt -- +//-- cqe_wqe -- +//-- cqe_opcode -- +//-- cqe_is_send -- +//-- cqe_owner -- +always @(posedge clk or posedge rst) begin + if (rst) begin + cqe_my_qpn <= 'd0; + cqe_my_ee <= 'd0; + cqe_rqpn <= 'd0; + cqe_sl_ipok <= 'd0; + cqe_g_mlpath <= 'd0; + cqe_rlid <= 'd0; + cqe_imm_etype_pkey_eec <= 'd0; + cqe_byte_cnt <= 'd0; + cqe_wqe <= 'd0; + cqe_opcode <= 'd0; + cqe_is_send <= 'd0; + cqe_owner <= 'd0; + end + else if (cur_state == JUDGE_s && PktHeader_net_opcode == `GEN_CQE) begin + cqe_my_qpn <= PktHeader_local_qpn; + cqe_my_ee <= 'd0; + cqe_rqpn <= PktHeader_remote_qpn; + cqe_sl_ipok <= 'd0; + cqe_g_mlpath <= 'd0; + cqe_rlid <= PktHeader_dmac[15:0]; + cqe_imm_etype_pkey_eec <= 'd0; + cqe_byte_cnt <= byte_cnt_buffer_doutb; + cqe_wqe <= PktHeader_ori_wqe_addr; + cqe_opcode <= PktHeader_cqe_opcode; + cqe_is_send <= 'd0; + cqe_owner <= `HGHCA_CQ_ENTRY_OWNER_HW; + end + else begin + cqe_my_qpn <= cqe_my_qpn; + cqe_my_ee <= cqe_my_ee; + cqe_rqpn <= cqe_rqpn; + cqe_sl_ipok <= cqe_sl_ipok; + cqe_g_mlpath <= cqe_g_mlpath; + cqe_rlid <= cqe_rlid; + cqe_imm_etype_pkey_eec <= cqe_imm_etype_pkey_eec; + cqe_byte_cnt <= cqe_byte_cnt; + cqe_wqe <= cqe_wqe; + cqe_opcode <= cqe_opcode; + cqe_is_send <= cqe_is_send; + cqe_owner <= cqe_owner; + end +end + +//-- cqe_data -- +assign cqe_data = (cur_state == DMA_CQE_s) ? { cqe_owner, 8'd0, cqe_is_send, cqe_opcode, cqe_wqe, cqe_byte_cnt, cqe_imm_etype_pkey_eec, + cqe_rlid, cqe_g_mlpath, cqe_sl_ipok, cqe_rqpn, cqe_my_ee, cqe_my_qpn} : 'd0; + +//-- byte_cnt_buffer_wea -- +//-- byte_cnt_buffer_addra -- +//-- byte_cnt_buffer_dina -- +assign byte_cnt_buffer_wea = (cur_state == DMA_SEND_DATA_s && next_state != DMA_SEND_DATA_s) || (cur_state == DMA_WRITE_DATA_s && next_state != DMA_WRITE_DATA_s) ? 'd1 : 'd0; +assign byte_cnt_buffer_addra = PktHeader_local_qpn; +assign byte_cnt_buffer_dina = (cur_state == DMA_SEND_DATA_s && next_state != DMA_SEND_DATA_s) ? mcb_pkt_length + byte_cnt_buffer_doutb : + (cur_state == DMA_WRITE_DATA_s && next_state != DMA_WRITE_DATA_s) ? PktHeader_pkt_length + byte_cnt_buffer_doutb : 'd0; + +//-- byte_cnt_buffer_addrb -- +assign byte_cnt_buffer_addrb = PktHeader_local_qpn; + +//-- net_resp_wen -- +always @(posedge clk or posedge rst) begin + if (rst) begin + net_resp_wen <= 'd0; + end + else if (cur_state == GEN_RESP_s && !net_resp_prog_full) begin + net_resp_wen <= 'd1; + end + else begin + net_resp_wen <= 'd0; + end +end + +//-- net_resp_din -- +always @(posedge clk or posedge rst) begin + if(rst) begin + net_resp_din <= 'd0; + end + else if(cur_state == GEN_RESP_s) begin + net_resp_din <= {'d0, PktHeader_pkt_length, PktHeader_sip, PktHeader_dip, PktHeader_smac, PktHeader_dmac, PktHeader_service_type, PktHeader_net_opcode, PktHeader_remote_qpn, 8'd0, PktHeader_local_qpn}; + end + else begin + net_resp_din <= net_resp_din; + end +end +/*------------------------------------------- Variables Decode : End ----------------------------------------------***/ + +/*------------------------------------------- Local Macros Undef : Begin --------------------------------------------*/ +`undef HEADER_LOCAL_QPN_OFFSET +`undef HEADER_TAIL_INDICATOR_OFFSET +`undef HEADER_REMOTE_QPN_OFFSET +`undef HEADER_NET_OPCODE_OFFSET +`undef HEADER_SERVICE_TYPE_OFFSET +`undef HEADER_IMMEDIATE_OFFSET +`undef HEADER_PKT_LENGTH_OFFSET +`undef HEADER_DMAC_OFFSET +`undef HEADER_SMAC_OFFSET +`undef HEADER_DIP_OFFSET +`undef HEADER_SIP_OFFSET +`undef HEADER_CQE_OPCODE_OFFSET +`undef HEADER_PKT_START_ADDR_OFFSET +`undef HEADER_ORI_WQE_ADDR_OFFSET + +`undef MCB_STATE_OFFSET +`undef MCB_VALID_0_OFFSET +`undef MCB_VALID_1_OFFSET +`undef MCB_PAGE_0_SIZE_OFFSET +`undef MCB_PAGE_0_ADDR_OFFSET +`undef MCB_PAGE_1_SIZE_OFFSET +`undef MCB_PAGE_1_ADDR_OFFSET +`undef MCB_TAIL_INDICATOR_OFFSET +`undef MCB_PKT_LENGTH_OFFSET +`undef MCB_PKT_START_ADDR_OFFSET +/*------------------------------------------- Local Macros Undef : End ----------------------------------------------*/ + +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/RPCSubsystem/RDMACore/ResponderCore/RespTransCore/RespTransCore.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/RPCSubsystem/RDMACore/ResponderCore/RespTransCore/RespTransCore.v new file mode 100644 index 0000000000000000000000000000000000000000..e54554441bbe2b87424b8c7799752452c95e04a5 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/RPCSubsystem/RDMACore/ResponderCore/RespTransCore/RespTransCore.v @@ -0,0 +1,94 @@ + /*------------------------------------------- Module Description : Begin ---------------------------------------------- +Name: RespTransCore +Author: YangFan +Function: 1.Generate network resp +--------------------------------------------- Module Decription : End -----------------------------------------------*/ + +/*------------------------------------------- Timescale Definition : Begin ------------------------------------------*/ +`timescale 1ns / 1ps +/*------------------------------------------- Timescale Definition : End --------------------------------------------*/ + +/*------------------------------------------- Included Files : Begin ------------------------------------------------*/ +`include "protocol_engine_def.vh" +/*------------------------------------------- Included Files : End --------------------------------------------------*/ + +/*------------------------------------------- Input/Output Definition : Begin ---------------------------------------*/ +module RespTransCore +( + input wire clk, + input wire rst, + +//Interface with ReqRecvCore + output wire net_resp_ren, + input wire net_resp_empty, + input wire [`NET_REQ_META_WIDTH - 1 : 0] net_resp_dout, + +//Interface with Gather Data + input wire payload_empty, + input wire [511:0] payload_data, + output wire payload_ren, + +//Interface with Payload Buffer + output wire insert_req_valid, + output wire insert_req_start, + output wire insert_req_last, + output wire [`PACKET_BUFFER_SLOT_NUM_LOG - 1 : 0] insert_req_head, + output wire [`PACKET_BUFFER_SLOT_WIDTH - 1 : 0] insert_req_data, + input wire insert_req_ready, + + input wire insert_resp_valid, + input wire [`PACKET_BUFFER_SLOT_NUM_LOG - 1 : 0] insert_resp_data, + +//Interface with TransportSubsystem + output wire egress_pkt_valid, + output wire [`PKT_META_BUS_WIDTH - 1 : 0] egress_pkt_head, + input wire egress_pkt_ready +); +/*------------------------------------------- Input/Output Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Macros Definition : Begin ---------------------------------------*/ +/*------------------------------------------- Local Macros Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Variables Definition : Begin ------------------------------------*/ +/*------------------------------------------- Local Variables Definition : End --------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : Begin ---------------------------------------*/ +RespTransCore_Thread_1 RespTransCore_Thread_1_Inst( + .clk ( clk ), + .rst ( rst ), + + .net_resp_ren ( net_resp_ren ), + .net_resp_empty ( net_resp_empty ), + .net_resp_dout ( net_resp_dout ), + + .payload_empty ( payload_empty ), + .payload_data ( payload_data ), + .payload_ren ( payload_ren ), + + .insert_req_valid ( insert_req_valid ), + .insert_req_start ( insert_req_start ), + .insert_req_last ( insert_req_last ), + .insert_req_head ( insert_req_head ), + .insert_req_data ( insert_req_data ), + .insert_req_ready ( insert_req_ready ), + + .insert_resp_valid ( insert_resp_valid ), + .insert_resp_data ( insert_resp_data ), + + .egress_pkt_valid ( egress_pkt_valid ), + .egress_pkt_head ( egress_pkt_head ), + .egress_pkt_ready ( egress_pkt_ready ) +); + +/*------------------------------------------- Submodules Instatiation : End -----------------------------------------*/ + +/*------------------------------------------- State Machine Definition : Begin --------------------------------------*/ +/*------------------------------------------- State Machine Definition : End ----------------------------------------*/ + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ +/*------------------------------------------- Variables Decode : End ----------------------------------------------***/ + +/*------------------------------------------- Local Macros Undef : Begin --------------------------------------------*/ +/*------------------------------------------- Local Macros Undef : End ----------------------------------------------*/ + +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/RPCSubsystem/RDMACore/ResponderCore/RespTransCore/RespTransCore_Thread_1.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/RPCSubsystem/RDMACore/ResponderCore/RespTransCore/RespTransCore_Thread_1.v new file mode 100644 index 0000000000000000000000000000000000000000..d1760d0916d3afda08b87bb7369db7e95356a9a0 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/RPCSubsystem/RDMACore/ResponderCore/RespTransCore/RespTransCore_Thread_1.v @@ -0,0 +1,229 @@ + /*------------------------------------------- Module Description : Begin ---------------------------------------------- +Name: RespTransCore_Thread_1 +Author: YangFan +Function: 1.Generate DMA Read for RDMA Read Resp. +--------------------------------------------- Module Decription : End -----------------------------------------------*/ + +/*------------------------------------------- Timescale Definition : Begin ------------------------------------------*/ +`timescale 1ns / 1ps +/*------------------------------------------- Timescale Definition : End --------------------------------------------*/ + +/*------------------------------------------- Included Files : Begin ------------------------------------------------*/ +`include "protocol_engine_def.vh" +/*------------------------------------------- Included Files : End --------------------------------------------------*/ + +/*------------------------------------------- Input/Output Definition : Begin ---------------------------------------*/ +module RespTransCore_Thread_1 +( + input wire clk, + input wire rst, + +//Interface with ReqRecvCore + output wire net_resp_ren, + input wire net_resp_empty, + input wire [`NET_REQ_META_WIDTH - 1 : 0] net_resp_dout, + +//Interface with Gather Data + input wire payload_empty, + input wire [511:0] payload_data, + output wire payload_ren, + +//Interface with Payload Buffer + output wire insert_req_valid, + output wire insert_req_start, + output wire insert_req_last, + output wire [`PACKET_BUFFER_SLOT_NUM_LOG - 1 : 0] insert_req_head, + output wire [`PACKET_BUFFER_SLOT_WIDTH - 1 : 0] insert_req_data, + input wire insert_req_ready, + + input wire insert_resp_valid, + input wire [`PACKET_BUFFER_SLOT_NUM_LOG - 1 : 0] insert_resp_data, + +//Interface with TransportSubsystem + output wire egress_pkt_valid, + output wire [`PKT_META_BUS_WIDTH - 1 : 0] egress_pkt_head, + input wire egress_pkt_ready +); +/*------------------------------------------- Input/Output Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Macros Definition : Begin ---------------------------------------*/ +`define NET_LOCAL_QPN_OFFSET 23:0 +`define NET_REMOTE_QPN_OFFSET 55:32 +`define NET_OPCODE_OFFSET 60:56 +`define NET_SERVICE_TYPE_OFFSET 63:61 +`define NET_DMAC_OFFSET 111:64 +`define NET_SMAC_OFFSET 159:112 +`define NET_DIP_OFFSET 191:160 +`define NET_SIP_OFFSET 223:192 +`define NET_PKT_LENGTH_OFFSET 255:224 +/*------------------------------------------- Local Macros Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Variables Definition : Begin ------------------------------------*/ +reg [`NET_REQ_META_WIDTH - 1 : 0] net_resp_bus; + +wire [4:0] net_opcode; +wire [15:0] net_pkt_length; + +reg [31:0] payload_piece_count; +reg [31:0] payload_piece_total; + +reg [`MAX_DB_SLOT_NUM_LOG - 1:0] pkt_start_addr; +/*------------------------------------------- Local Variables Definition : End --------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : Begin ---------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : End -----------------------------------------*/ + +/*------------------------------------------- State Machine Definition : Begin --------------------------------------*/ +reg [2:0] cur_state; +reg [2:0] next_state; + +parameter [2:0] IDLE_s = 3'd1, + JUDGE_s = 3'd2, + INSERT_s = 3'd3, + INJECT_s = 3'd4; + +always @(posedge clk or posedge rst) begin + if(rst) begin + cur_state <= IDLE_s; + end + else begin + cur_state <= next_state; + end +end + +always @(*) begin + case(cur_state) + IDLE_s: if(!net_resp_empty) begin + next_state = JUDGE_s; + end + else begin + next_state = IDLE_s; + end + JUDGE_s: if(net_opcode == `ACKNOWLEDGE) begin + next_state = INJECT_s; + end + else if(net_opcode == `RDMA_READ_RESPONSE_FIRST || net_opcode == `RDMA_READ_RESPONSE_MIDDLE || net_opcode == `RDMA_READ_RESPONSE_LAST || + net_opcode == `RDMA_READ_RESPONSE_ONLY) begin + next_state = INSERT_s; + end + else begin + next_state = IDLE_s; + end + INSERT_s: if(!payload_empty && payload_piece_count == 'd1 && insert_req_valid && insert_req_ready && insert_resp_valid) begin + next_state = INJECT_s; + end + else begin + next_state = INSERT_s; + end + INJECT_s: if(egress_pkt_valid && egress_pkt_ready) begin + next_state = IDLE_s; + end + else begin + next_state = INJECT_s; + end + default: next_state = IDLE_s; + endcase +end +/*------------------------------------------- State Machine Definition : End ----------------------------------------*/ + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ +//-- net_resp_bus -- +always @(posedge clk or posedge rst) begin + if (rst) begin + net_resp_bus <= 'd0; + end + else if (cur_state == IDLE_s && !net_resp_empty) begin + net_resp_bus <= net_resp_dout; + end + else begin + net_resp_bus <= net_resp_bus; + end +end + +//-- net_opcode -- +//-- net_pkt_length -- +assign net_opcode = net_resp_bus[`NET_OPCODE_OFFSET]; +assign net_pkt_length = net_resp_bus[`NET_PKT_LENGTH_OFFSET]; + +//-- payload_piece_count -- +always @(posedge clk or posedge rst) begin + if (rst) begin + payload_piece_count <= 'd0; + end + else if (cur_state == IDLE_s) begin + payload_piece_count <= 'd0; + end + else if(cur_state == JUDGE_s) begin + payload_piece_count <= net_pkt_length[5:0] ? (net_pkt_length >> 6) + 1 : net_pkt_length >> 6; + end + else if(cur_state == INSERT_s && !payload_empty && insert_req_valid && insert_req_ready) begin + payload_piece_count <= payload_piece_count - 'd1; + end + else begin + payload_piece_count <= payload_piece_count; + end +end + +//-- payload_piece_total -- +always @(posedge clk or posedge rst) begin + if (rst) begin + payload_piece_total <= 'd0; + end + else if (cur_state == IDLE_s) begin + payload_piece_total <= 'd0; + end + else if(cur_state == JUDGE_s) begin + payload_piece_total <= net_pkt_length[5:0] ? (net_pkt_length >> 6) + 1 : net_pkt_length >> 6; + end + else begin + payload_piece_total <= payload_piece_total; + end +end + +//-- pkt_start_addr -- +always @(posedge clk or posedge rst) begin + if(rst) begin + pkt_start_addr <= 'd0; + end + else if(cur_state == IDLE_s) begin + pkt_start_addr <= 'd0; + end + else if(cur_state == INSERT_s && insert_req_start && insert_resp_valid) begin + pkt_start_addr <= insert_resp_data; + end + else begin + pkt_start_addr <= pkt_start_addr; + end +end + +//-- net_resp_ren -- +assign net_resp_ren = (cur_state == IDLE_s) ? !net_resp_empty : 'd0; + +//-- payload_ren -- +assign payload_ren = (cur_state == INSERT_s) ? !payload_empty && insert_req_valid && insert_req_ready : 'd0; + +//-- insert_req_valid -- +//-- insert_req_start -- +//-- insert_req_last -- +//-- insert_req_head -- +//-- insert_req_data -- +assign insert_req_valid = (cur_state == INSERT_s && !payload_empty) ? 'd1 : 'd0; +assign insert_req_start = (cur_state == INSERT_s && !payload_empty) ? (payload_piece_total == payload_piece_count) : 'd0; +assign insert_req_last = (cur_state == INSERT_s && !payload_empty) ? (payload_piece_count == 'd1) : 'd0; +assign insert_req_head = (cur_state == INSERT_s && !payload_empty) ? (payload_piece_total) : 'd0; +assign insert_req_data = (cur_state == INSERT_s && !payload_empty) ? payload_data : 'd0; + +//-- egress_pkt_valid -- +//-- egress_pkt_head -- +assign egress_pkt_valid = (cur_state == INJECT_s) ? 'd1 : 'd0; +assign egress_pkt_head = (cur_state == INJECT_s) ? {net_pkt_length, pkt_start_addr, net_resp_bus[`NET_SIP_OFFSET], net_resp_bus[`NET_DIP_OFFSET], net_resp_bus[`NET_SMAC_OFFSET], + net_resp_bus[`NET_DMAC_OFFSET], 136'd0, net_resp_bus[`NET_REMOTE_QPN_OFFSET], net_resp_bus[`NET_SERVICE_TYPE_OFFSET], + net_resp_bus[`NET_OPCODE_OFFSET], net_resp_bus[`NET_LOCAL_QPN_OFFSET]} : 'd0; +/*------------------------------------------- Variables Decode : End ----------------------------------------------***/ + +/*------------------------------------------- Local Macros Undef : Begin --------------------------------------------*/ + +/*------------------------------------------- Local Macros Undef : End ----------------------------------------------*/ + +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/RPCSubsystem/RDMACore/ResponderCore/ResponderCore.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/RPCSubsystem/RDMACore/ResponderCore/ResponderCore.v new file mode 100644 index 0000000000000000000000000000000000000000..dfdc800971ea35b98c649b7d9d212d07432dd58a --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/RPCSubsystem/RDMACore/ResponderCore/ResponderCore.v @@ -0,0 +1,355 @@ +/*------------------------------------------- Module Description : Begin ---------------------------------------------- +Name: ReqRecvCore +Author: YangFan +Function: Responder. +--------------------------------------------- Module Decription : End -----------------------------------------------*/ + +/*------------------------------------------- Timescale Definition : Begin ------------------------------------------*/ +`timescale 1ns / 1ps +/*------------------------------------------- Timescale Definition : End --------------------------------------------*/ + +/*------------------------------------------- Included Files : Begin ------------------------------------------------*/ +`include "protocol_engine_def.vh" +/*------------------------------------------- Included Files : End --------------------------------------------------*/ + +/*------------------------------------------- Input/Output Definition : Begin ---------------------------------------*/ +module ResponderCore +#( + parameter INGRESS_CXT_HEAD_WIDTH = 128, + parameter INGRESS_CXT_DATA_WIDTH = 256, + parameter EGRESS_CXT_HEAD_WIDTH = 128, + parameter EGRESS_CXT_DATA_WIDTH = 256, + + parameter INGRESS_MR_HEAD_WIDTH = 128, + parameter INGRESS_MR_DATA_WIDTH = 256, + parameter EGRESS_MR_HEAD_WIDTH = 128, + parameter EGRESS_MR_DATA_WIDTH = 256 +) +( + input wire clk, + input wire rst, + +//Interface with WQEParser + input wire RX_REQ_ingress_pkt_valid, + input wire [`PKT_META_BUS_WIDTH - 1 : 0] RX_REQ_ingress_pkt_head, + output wire RX_REQ_ingress_pkt_ready, + +//Interface with OoOStation(For CxtMgt) + output wire RX_REQ_fetch_cxt_ingress_valid, + output wire [`RX_REQ_OOO_CXT_INGRESS_HEAD_WIDTH - 1 : 0] RX_REQ_fetch_cxt_ingress_head, + output wire [`RX_REQ_OOO_CXT_INGRESS_DATA_WIDTH - 1 : 0] RX_REQ_fetch_cxt_ingress_data, + output wire RX_REQ_fetch_cxt_ingress_start, + output wire RX_REQ_fetch_cxt_ingress_last, + input wire RX_REQ_fetch_cxt_ingress_ready, + + input wire RX_REQ_fetch_cxt_egress_valid, + input wire [`RX_REQ_OOO_CXT_EGRESS_HEAD_WIDTH - 1 : 0] RX_REQ_fetch_cxt_egress_head, + input wire [`RX_REQ_OOO_CXT_EGRESS_DATA_WIDTH - 1 : 0] RX_REQ_fetch_cxt_egress_data, + input wire RX_REQ_fetch_cxt_egress_start, + input wire RX_REQ_fetch_cxt_egress_last, + output wire RX_REQ_fetch_cxt_egress_ready, + +//Interface with OoOStation(For MRMgt) + output wire RX_REQ_fetch_mr_ingress_valid, + output wire [`RX_REQ_OOO_MR_INGRESS_HEAD_WIDTH - 1 : 0] RX_REQ_fetch_mr_ingress_head, + output wire [`RX_REQ_OOO_MR_INGRESS_DATA_WIDTH - 1 : 0] RX_REQ_fetch_mr_ingress_data, + output wire RX_REQ_fetch_mr_ingress_start, + output wire RX_REQ_fetch_mr_ingress_last, + input wire RX_REQ_fetch_mr_ingress_ready, + + input wire RX_REQ_fetch_mr_egress_valid, + input wire [`RX_REQ_OOO_MR_EGRESS_HEAD_WIDTH - 1 : 0] RX_REQ_fetch_mr_egress_head, + input wire [`RX_REQ_OOO_MR_EGRESS_DATA_WIDTH - 1 : 0] RX_REQ_fetch_mr_egress_data, + input wire RX_REQ_fetch_mr_egress_start, + input wire RX_REQ_fetch_mr_egress_last, + output wire RX_REQ_fetch_mr_egress_ready, + +//Interface with RecvQueueMgt + output wire RQ_wqe_req_valid, + output wire [`WQE_META_WIDTH - 1 : 0] RQ_wqe_req_head, + output wire RQ_wqe_req_start, + output wire RQ_wqe_req_last, + input wire RQ_wqe_req_ready, + + input wire RQ_wqe_resp_valid, + input wire [`WQE_META_WIDTH - 1 : 0] RQ_wqe_resp_head, + input wire [`WQE_SEG_WIDTH - 1 : 0] RQ_wqe_resp_data, + input wire RQ_wqe_resp_start, + input wire RQ_wqe_resp_last, + output wire RQ_wqe_resp_ready, + +//Interface with cache offset table + output wire RQ_cache_offset_wen, + output wire [`QP_NUM_LOG - 1 : 0] RQ_cache_offset_addr, + output wire [`RQ_CACHE_SLOT_NUM_LOG - 1:0] RQ_cache_offset_din, + input wire [`RQ_CACHE_SLOT_NUM_LOG - 1:0] RQ_cache_offset_dout, + +//Interface with RQHeadRecord + output wire RQ_offset_wen, + output wire [`QP_NUM_LOG - 1 : 0] RQ_offset_addr, + output wire [23:0] RQ_offset_din, + input wire [23:0] RQ_offset_dout, + + output wire RQ_cache_owned_wen, + output wire [`RQ_CACHE_CELL_NUM_LOG - 1 : 0] RQ_cache_owned_addr, + output wire [`QP_NUM_LOG - 1 : 0] RQ_cache_owned_din, + input wire [`QP_NUM_LOG - 1 : 0] RQ_cache_owned_dout, + +//Interface with CompletionQueueMgt + output wire RX_REQ_cq_req_valid, + output wire [`CQ_REQ_HEAD_WIDTH - 1 : 0] RX_REQ_cq_req_head, + input wire RX_REQ_cq_req_ready, + + input wire RX_REQ_cq_resp_valid, + input wire [`CQ_RESP_HEAD_WIDTH - 1 : 0] RX_REQ_cq_resp_head, + output wire RX_REQ_cq_resp_ready, + +//Interface with EventQueueMgt + output wire RX_REQ_eq_req_valid, + output wire [`EQ_REQ_HEAD_WIDTH - 1 : 0] RX_REQ_eq_req_head, + input wire RX_REQ_eq_req_ready, + + input wire RX_REQ_eq_resp_valid, + input wire [`EQ_RESP_HEAD_WIDTH - 1 : 0] RX_REQ_eq_resp_head, + output wire RX_REQ_eq_resp_ready, + +//Interface with Packet Buffer + output wire RX_REQ_delete_req_valid, + output wire [`MAX_DB_SLOT_NUM_LOG * 2 - 1 : 0] RX_REQ_delete_req_head, + input wire RX_REQ_delete_req_ready, + + input wire RX_REQ_delete_resp_valid, + input wire RX_REQ_delete_resp_start, + input wire RX_REQ_delete_resp_last, + input wire [`PACKET_BUFFER_SLOT_WIDTH - 1 : 0] RX_REQ_delete_resp_data, + output wire RX_REQ_delete_resp_ready, + +//DMA Write Interface + output wire RX_REQ_scatter_req_wr_en, + output wire [`DMA_LENGTH_WIDTH * 2 + `DMA_ADDR_WIDTH - 1 : 0] RX_REQ_scatter_req_din, + input wire RX_REQ_scatter_req_prog_full, + + output wire RX_REQ_scatter_data_wr_en, + output wire [`DMA_DATA_WIDTH - 1: 0] RX_REQ_scatter_data_din, + input wire RX_REQ_scatter_data_prog_full, + +//DMA Read Interface + output wire TX_RESP_gather_req_wr_en, + output wire [`DMA_LENGTH_WIDTH * 2 + `DMA_ADDR_WIDTH - 1 : 0] TX_RESP_gather_req_din, + input wire TX_RESP_gather_req_prog_full, + +//Interface with Gather Data + input wire TX_RESP_payload_empty, + input wire [511:0] TX_RESP_payload_data, + output wire TX_RESP_payload_rd_en, + +//Interface with Payload Buffer + output wire TX_RESP_insert_req_valid, + output wire TX_RESP_insert_req_start, + output wire TX_RESP_insert_req_last, + output wire [`PACKET_BUFFER_SLOT_NUM_LOG - 1 : 0] TX_RESP_insert_req_head, + output wire [`PACKET_BUFFER_SLOT_WIDTH - 1 : 0] TX_RESP_insert_req_data, + input wire TX_RESP_insert_req_ready, + + input wire TX_RESP_insert_resp_valid, + input wire [`PACKET_BUFFER_SLOT_NUM_LOG - 1 : 0] TX_RESP_insert_resp_data, + +//Interface with TransportSubsystem + output wire TX_RESP_egress_pkt_valid, + output wire [`PKT_META_BUS_WIDTH - 1 : 0] TX_RESP_egress_pkt_head, + input wire TX_RESP_egress_pkt_ready +); +/*------------------------------------------- Input/Output Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Macros Definition : Begin ---------------------------------------*/ +/*------------------------------------------- Local Macros Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Variables Definition : Begin ------------------------------------*/ +wire TX_RESP_net_resp_wen; +wire [`NET_REQ_META_WIDTH - 1 : 0] TX_RESP_net_resp_din; +wire TX_RESP_net_resp_prog_full; + +wire TX_RESP_net_resp_ren; +wire [`NET_REQ_META_WIDTH - 1 : 0] TX_RESP_net_resp_dout; +wire TX_RESP_net_resp_empty; +/*------------------------------------------- Local Variables Definition : End --------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : Begin ---------------------------------------*/ +ReqRecvCore #( + .INGRESS_CXT_HEAD_WIDTH ( INGRESS_CXT_HEAD_WIDTH ), + .INGRESS_CXT_DATA_WIDTH ( INGRESS_CXT_DATA_WIDTH ), + .EGRESS_CXT_HEAD_WIDTH ( EGRESS_CXT_HEAD_WIDTH ), + .EGRESS_CXT_DATA_WIDTH ( EGRESS_CXT_DATA_WIDTH ), + + .INGRESS_MR_HEAD_WIDTH ( INGRESS_MR_HEAD_WIDTH ), + .INGRESS_MR_DATA_WIDTH ( INGRESS_MR_DATA_WIDTH ), + .EGRESS_MR_HEAD_WIDTH ( EGRESS_MR_HEAD_WIDTH ), + .EGRESS_MR_DATA_WIDTH ( EGRESS_MR_DATA_WIDTH ) +) +ReqRecvCore_Inst +( + .clk ( clk ), + .rst ( rst ), + + .ingress_pkt_valid ( RX_REQ_ingress_pkt_valid ), + .ingress_pkt_head ( RX_REQ_ingress_pkt_head ), + .ingress_pkt_ready ( RX_REQ_ingress_pkt_ready ), + + .fetch_cxt_ingress_valid ( RX_REQ_fetch_cxt_ingress_valid ), + .fetch_cxt_ingress_head ( RX_REQ_fetch_cxt_ingress_head ), + .fetch_cxt_ingress_data ( RX_REQ_fetch_cxt_ingress_data ), + .fetch_cxt_ingress_start ( RX_REQ_fetch_cxt_ingress_start ), + .fetch_cxt_ingress_last ( RX_REQ_fetch_cxt_ingress_last ), + .fetch_cxt_ingress_ready ( RX_REQ_fetch_cxt_ingress_ready ), + + .fetch_cxt_egress_valid ( RX_REQ_fetch_cxt_egress_valid ), + .fetch_cxt_egress_head ( RX_REQ_fetch_cxt_egress_head ), + .fetch_cxt_egress_data ( RX_REQ_fetch_cxt_egress_data ), + .fetch_cxt_egress_start ( RX_REQ_fetch_cxt_egress_start ), + .fetch_cxt_egress_last ( RX_REQ_fetch_cxt_egress_last ), + .fetch_cxt_egress_ready ( RX_REQ_fetch_cxt_egress_ready ), + + .fetch_mr_ingress_valid ( RX_REQ_fetch_mr_ingress_valid ), + .fetch_mr_ingress_head ( RX_REQ_fetch_mr_ingress_head ), + .fetch_mr_ingress_data ( RX_REQ_fetch_mr_ingress_data ), + .fetch_mr_ingress_start ( RX_REQ_fetch_mr_ingress_start ), + .fetch_mr_ingress_last ( RX_REQ_fetch_mr_ingress_last ), + .fetch_mr_ingress_ready ( RX_REQ_fetch_mr_ingress_ready ), + + .fetch_mr_egress_valid ( RX_REQ_fetch_mr_egress_valid ), + .fetch_mr_egress_head ( RX_REQ_fetch_mr_egress_head ), + .fetch_mr_egress_data ( RX_REQ_fetch_mr_egress_data ), + .fetch_mr_egress_start ( RX_REQ_fetch_mr_egress_start ), + .fetch_mr_egress_last ( RX_REQ_fetch_mr_egress_last ), + .fetch_mr_egress_ready ( RX_REQ_fetch_mr_egress_ready ), + + .wqe_req_valid ( RQ_wqe_req_valid ), + .wqe_req_head ( RQ_wqe_req_head ), + .wqe_req_start ( RQ_wqe_req_start ), + .wqe_req_last ( RQ_wqe_req_last ), + .wqe_req_ready ( RQ_wqe_req_ready ), + + .wqe_resp_valid ( RQ_wqe_resp_valid ), + .wqe_resp_head ( RQ_wqe_resp_head ), + .wqe_resp_data ( RQ_wqe_resp_data ), + .wqe_resp_start ( RQ_wqe_resp_start ), + .wqe_resp_last ( RQ_wqe_resp_last ), + .wqe_resp_ready ( RQ_wqe_resp_ready ), + + .cache_offset_wen ( RQ_cache_offset_wen ), + .cache_offset_addr ( RQ_cache_offset_addr ), + .cache_offset_din ( RQ_cache_offset_din ), + .cache_offset_dout ( RQ_cache_offset_dout ), + + .rq_offset_wen ( RQ_offset_wen ), + .rq_offset_addr ( RQ_offset_addr ), + .rq_offset_din ( RQ_offset_din ), + .rq_offset_dout ( RQ_offset_dout ), + + .RQ_cache_owned_wen ( RQ_cache_owned_wen ), + .RQ_cache_owned_addr ( RQ_cache_owned_addr ), + .RQ_cache_owned_din ( RQ_cache_owned_din ), + .RQ_cache_owned_dout ( RQ_cache_owned_dout ), + + .cq_req_valid ( RX_REQ_cq_req_valid ), + .cq_req_head ( RX_REQ_cq_req_head ), + .cq_req_ready ( RX_REQ_cq_req_ready ), + + .cq_resp_valid ( RX_REQ_cq_resp_valid ), + .cq_resp_head ( RX_REQ_cq_resp_head ), + .cq_resp_ready ( RX_REQ_cq_resp_ready ), + + .eq_req_valid ( RX_REQ_eq_req_valid ), + .eq_req_head ( RX_REQ_eq_req_head ), + .eq_req_ready ( RX_REQ_eq_req_ready ), + + .eq_resp_valid ( RX_REQ_eq_resp_valid ), + .eq_resp_head ( RX_REQ_eq_resp_head ), + .eq_resp_ready ( RX_REQ_eq_resp_ready ), + + .delete_req_valid ( RX_REQ_delete_req_valid ), + .delete_req_head ( RX_REQ_delete_req_head ), + .delete_req_ready ( RX_REQ_delete_req_ready ), + + .delete_resp_valid ( RX_REQ_delete_resp_valid ), + .delete_resp_start ( RX_REQ_delete_resp_start ), + .delete_resp_last ( RX_REQ_delete_resp_last ), + .delete_resp_data ( RX_REQ_delete_resp_data ), + .delete_resp_ready ( RX_REQ_delete_resp_ready ), + + .scatter_req_wr_en ( RX_REQ_scatter_req_wr_en ), + .scatter_req_din ( RX_REQ_scatter_req_din ), + .scatter_req_prog_full ( RX_REQ_scatter_req_prog_full ), + + .scatter_data_wr_en ( RX_REQ_scatter_data_wr_en ), + .scatter_data_din ( RX_REQ_scatter_data_din ), + .scatter_data_prog_full ( RX_REQ_scatter_data_prog_full ), + + .gather_req_wr_en ( TX_RESP_gather_req_wr_en ), + .gather_req_din ( TX_RESP_gather_req_din ), + .gather_req_prog_full ( TX_RESP_gather_req_prog_full ), + + .net_resp_wen ( TX_RESP_net_resp_wen ), + .net_resp_din ( TX_RESP_net_resp_din ), + .net_resp_prog_full ( TX_RESP_net_resp_prog_full ) +); + +RespTransCore RespTransCore_Inst( + .clk ( clk ), + .rst ( rst ), + + .net_resp_ren ( TX_RESP_net_resp_ren ), + .net_resp_empty ( TX_RESP_net_resp_empty ), + .net_resp_dout ( TX_RESP_net_resp_dout ), + + .payload_empty ( TX_RESP_payload_empty ), + .payload_data ( TX_RESP_payload_data ), + .payload_ren ( TX_RESP_payload_rd_en ), + + .insert_req_valid ( TX_RESP_insert_req_valid ), + .insert_req_start ( TX_RESP_insert_req_start ), + .insert_req_last ( TX_RESP_insert_req_last ), + .insert_req_head ( TX_RESP_insert_req_head ), + .insert_req_data ( TX_RESP_insert_req_data ), + .insert_req_ready ( TX_RESP_insert_req_ready ), + + .insert_resp_valid ( TX_RESP_insert_resp_valid ), + .insert_resp_data ( TX_RESP_insert_resp_data ), + + .egress_pkt_valid ( TX_RESP_egress_pkt_valid ), + .egress_pkt_head ( TX_RESP_egress_pkt_head ), + .egress_pkt_ready ( TX_RESP_egress_pkt_ready ) +); + +SyncFIFO_Template #( + .FIFO_WIDTH ( `NET_REQ_META_WIDTH ), + .FIFO_DEPTH ( 64 ) +) +NetReqFIFO_Inst +( + .clk ( clk ), + .rst ( rst ), + + .wr_en ( TX_RESP_net_resp_wen ), + .din ( TX_RESP_net_resp_din ), + .prog_full ( TX_RESP_net_resp_prog_full ), + + .rd_en ( TX_RESP_net_resp_ren ), + .dout ( TX_RESP_net_resp_dout ), + .empty ( TX_RESP_net_resp_empty ), + + .data_count ( ) +); + +/*------------------------------------------- Submodules Instatiation : End -----------------------------------------*/ + +/*------------------------------------------- State Machine Definition : Begin --------------------------------------*/ +/*------------------------------------------- State Machine Definition : End ----------------------------------------*/ + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ +/*------------------------------------------- Variables Decode : End ----------------------------------------------***/ + +/*------------------------------------------- Local Macros Undef : Begin --------------------------------------------*/ +/*------------------------------------------- Local Macros Undef : End ----------------------------------------------*/ + +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/RPCSubsystem/README.md b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/RPCSubsystem/README.md new file mode 100644 index 0000000000000000000000000000000000000000..9ab043885c9822a735c5408e22d6416e4d6c6b8f --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/RPCSubsystem/README.md @@ -0,0 +1,2 @@ +Implement self-defined RPC Core. +RDMACore is an example design. diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/RPCSubsystem/RPCSubsystem.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/RPCSubsystem/RPCSubsystem.v new file mode 100644 index 0000000000000000000000000000000000000000..5f8a27b728db8b5ab1e7df92c605eee7335f0898 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/RPCSubsystem/RPCSubsystem.v @@ -0,0 +1,548 @@ +/*------------------------------------------- Module Description : Begin ---------------------------------------------- +Name: RequesterCore +Author: YangFan +Function: 1.Deal with RDMA Semantics. +--------------------------------------------- Module Decription : End -----------------------------------------------*/ + +/*------------------------------------------- Timescale Definition : Begin ------------------------------------------*/ +`timescale 1ns / 1ps +/*------------------------------------------- Timescale Definition : End --------------------------------------------*/ + +/*------------------------------------------- Included Files : Begin ------------------------------------------------*/ +`include "protocol_engine_def.vh" +/*------------------------------------------- Included Files : End --------------------------------------------------*/ + +/*------------------------------------------- Input/Output Definition : Begin ---------------------------------------*/ +module RPCSubsystem +#( + parameter INGRESS_CXT_HEAD_WIDTH = 128, + parameter INGRESS_CXT_DATA_WIDTH = 256, + parameter EGRESS_CXT_HEAD_WIDTH = 128, + parameter EGRESS_CXT_DATA_WIDTH = 256, + + parameter INGRESS_MR_HEAD_WIDTH = 128, + parameter INGRESS_MR_DATA_WIDTH = 256, + parameter EGRESS_MR_HEAD_WIDTH = 128, + parameter EGRESS_MR_DATA_WIDTH = 256 +) +( + input wire clk, + input wire rst, + +/*************************** Interface with QueueSubsystem ****************************************/ +//TX : SQ Interface + input wire TX_REQ_sub_wqe_valid, + input wire [`WQE_META_WIDTH - 1 : 0] TX_REQ_sub_wqe_meta, + output wire TX_REQ_sub_wqe_ready, + +//TX : SCQ Interface + output wire TX_REQ_cq_req_valid, + output wire [`CQ_REQ_HEAD_WIDTH - 1 : 0] TX_REQ_cq_req_head, + input wire TX_REQ_cq_req_ready, + + input wire TX_REQ_cq_resp_valid, + input wire [`CQ_RESP_HEAD_WIDTH - 1 : 0] TX_REQ_cq_resp_head, + output wire TX_REQ_cq_resp_ready, + +//TX : EQ Interface + output wire TX_REQ_eq_req_valid, + output wire [`EQ_REQ_HEAD_WIDTH - 1 : 0] TX_REQ_eq_req_head, + input wire TX_REQ_eq_req_ready, + + input wire TX_REQ_eq_resp_valid, + input wire [`EQ_RESP_HEAD_WIDTH - 1 : 0] TX_REQ_eq_resp_head, + output wire TX_REQ_eq_resp_ready, + +//RX : RQ Interface + output wire RQ_wqe_req_valid, + output wire [`WQE_META_WIDTH - 1 : 0] RQ_wqe_req_head, + output wire RQ_wqe_req_start, + output wire RQ_wqe_req_last, + input wire RQ_wqe_req_ready, + + input wire RQ_wqe_resp_valid, + input wire [`WQE_META_WIDTH - 1 : 0] RQ_wqe_resp_head, + input wire [`WQE_SEG_WIDTH - 1 : 0] RQ_wqe_resp_data, + input wire RQ_wqe_resp_start, + input wire RQ_wqe_resp_last, + output wire RQ_wqe_resp_ready, + + output wire RQ_cache_offset_wen, + output wire [`QP_NUM_LOG - 1 : 0] RQ_cache_offset_addr, + output wire [`RQ_CACHE_SLOT_NUM_LOG - 1:0] RQ_cache_offset_din, + input wire [`RQ_CACHE_SLOT_NUM_LOG - 1:0] RQ_cache_offset_dout, + + output wire RQ_offset_wen, + output wire [`QP_NUM_LOG - 1 : 0] RQ_offset_addr, + output wire [23:0] RQ_offset_din, + input wire [23:0] RQ_offset_dout, + + output wire RQ_cache_owned_wen, + output wire [`RQ_CACHE_CELL_NUM_LOG - 1 : 0] RQ_cache_owned_addr, + output wire [`QP_NUM_LOG - 1 : 0] RQ_cache_owned_din, + input wire [`QP_NUM_LOG - 1 : 0] RQ_cache_owned_dout, + +//RX : RCQ Interface + output wire RX_REQ_cq_req_valid, + output wire [`CQ_REQ_HEAD_WIDTH - 1 : 0] RX_REQ_cq_req_head, + input wire RX_REQ_cq_req_ready, + + input wire RX_REQ_cq_resp_valid, + input wire [`CQ_RESP_HEAD_WIDTH - 1 : 0] RX_REQ_cq_resp_head, + output wire RX_REQ_cq_resp_ready, + +//RX : EQ Interface + output wire RX_REQ_eq_req_valid, + output wire [`EQ_REQ_HEAD_WIDTH - 1 : 0] RX_REQ_eq_req_head, + input wire RX_REQ_eq_req_ready, + + input wire RX_REQ_eq_resp_valid, + input wire [`EQ_RESP_HEAD_WIDTH - 1 : 0] RX_REQ_eq_resp_head, + output wire RX_REQ_eq_resp_ready, + +//RX : SCQ Interface + output wire RX_RESP_cq_req_valid, + output wire [`CQ_REQ_HEAD_WIDTH - 1 : 0] RX_RESP_cq_req_head, + input wire RX_RESP_cq_req_ready, + + input wire RX_RESP_cq_resp_valid, + input wire [`CQ_RESP_HEAD_WIDTH - 1 : 0] RX_RESP_cq_resp_head, + output wire RX_RESP_cq_resp_ready, + +//RX : EQ Interface + output wire RX_RESP_eq_req_valid, + output wire [`EQ_REQ_HEAD_WIDTH - 1 : 0] RX_RESP_eq_req_head, + input wire RX_RESP_eq_req_ready, + + input wire RX_RESP_eq_resp_valid, + input wire [`EQ_RESP_HEAD_WIDTH - 1 : 0] RX_RESP_eq_resp_head, + output wire RX_RESP_eq_resp_ready, + +/*************************** Interface with ICMMgt(CxtMgt) ****************************************/ +//TX : Cxt for transmit REQ + output wire TX_REQ_fetch_cxt_ingress_valid, + output wire [`TX_REQ_OOO_CXT_INGRESS_HEAD_WIDTH - 1 : 0] TX_REQ_fetch_cxt_ingress_head, + output wire [`TX_REQ_OOO_CXT_INGRESS_DATA_WIDTH - 1 : 0] TX_REQ_fetch_cxt_ingress_data, + output wire TX_REQ_fetch_cxt_ingress_start, + output wire TX_REQ_fetch_cxt_ingress_last, + input wire TX_REQ_fetch_cxt_ingress_ready, + + input wire TX_REQ_fetch_cxt_egress_valid, + input wire [`TX_REQ_OOO_CXT_EGRESS_HEAD_WIDTH - 1 : 0] TX_REQ_fetch_cxt_egress_head, + input wire [`TX_REQ_OOO_CXT_EGRESS_DATA_WIDTH - 1 : 0] TX_REQ_fetch_cxt_egress_data, + input wire TX_REQ_fetch_cxt_egress_start, + input wire TX_REQ_fetch_cxt_egress_last, + output wire TX_REQ_fetch_cxt_egress_ready, + +//RX : Cxt for receive REQ + output wire RX_REQ_fetch_cxt_ingress_valid, + output wire [`RX_REQ_OOO_CXT_INGRESS_HEAD_WIDTH - 1 : 0] RX_REQ_fetch_cxt_ingress_head, + output wire [`RX_REQ_OOO_CXT_INGRESS_DATA_WIDTH - 1 : 0] RX_REQ_fetch_cxt_ingress_data, + output wire RX_REQ_fetch_cxt_ingress_start, + output wire RX_REQ_fetch_cxt_ingress_last, + input wire RX_REQ_fetch_cxt_ingress_ready, + + input wire RX_REQ_fetch_cxt_egress_valid, + input wire [`RX_REQ_OOO_CXT_EGRESS_HEAD_WIDTH - 1 : 0] RX_REQ_fetch_cxt_egress_head, + input wire [`RX_REQ_OOO_CXT_EGRESS_DATA_WIDTH - 1 : 0] RX_REQ_fetch_cxt_egress_data, + input wire RX_REQ_fetch_cxt_egress_start, + input wire RX_REQ_fetch_cxt_egress_last, + output wire RX_REQ_fetch_cxt_egress_ready, + +//RX : Cxt for receive RESP + output wire RX_RESP_fetch_cxt_ingress_valid, + output wire [`RX_RESP_OOO_CXT_INGRESS_HEAD_WIDTH - 1 : 0] RX_RESP_fetch_cxt_ingress_head, + output wire [`RX_RESP_OOO_CXT_INGRESS_DATA_WIDTH - 1 : 0] RX_RESP_fetch_cxt_ingress_data, + output wire RX_RESP_fetch_cxt_ingress_start, + output wire RX_RESP_fetch_cxt_ingress_last, + input wire RX_RESP_fetch_cxt_ingress_ready, + + input wire RX_RESP_fetch_cxt_egress_valid, + input wire [`RX_RESP_OOO_CXT_EGRESS_HEAD_WIDTH - 1 : 0] RX_RESP_fetch_cxt_egress_head, + input wire [`RX_RESP_OOO_CXT_EGRESS_DATA_WIDTH - 1 : 0] RX_RESP_fetch_cxt_egress_data, + input wire RX_RESP_fetch_cxt_egress_start, + input wire RX_RESP_fetch_cxt_egress_last, + output wire RX_RESP_fetch_cxt_egress_ready, + +/*************************** Interface with ICMMgt(MRMgt) ****************************************/ +//TX : Cxt for transmit REQ + output wire TX_REQ_fetch_mr_ingress_valid, + output wire [`TX_REQ_OOO_MR_INGRESS_HEAD_WIDTH - 1 : 0] TX_REQ_fetch_mr_ingress_head, + output wire [`TX_REQ_OOO_MR_INGRESS_DATA_WIDTH - 1 : 0] TX_REQ_fetch_mr_ingress_data, + output wire TX_REQ_fetch_mr_ingress_start, + output wire TX_REQ_fetch_mr_ingress_last, + input wire TX_REQ_fetch_mr_ingress_ready, + + input wire TX_REQ_fetch_mr_egress_valid, + input wire [`TX_REQ_OOO_MR_EGRESS_HEAD_WIDTH - 1 : 0] TX_REQ_fetch_mr_egress_head, + input wire [`TX_REQ_OOO_MR_EGRESS_DATA_WIDTH - 1 : 0] TX_REQ_fetch_mr_egress_data, + input wire TX_REQ_fetch_mr_egress_start, + input wire TX_REQ_fetch_mr_egress_last, + output wire TX_REQ_fetch_mr_egress_ready, + +//RX : Cxt for receive REQ + output wire RX_RESP_fetch_mr_ingress_valid, + output wire [`RX_RESP_OOO_MR_INGRESS_HEAD_WIDTH - 1 : 0] RX_RESP_fetch_mr_ingress_head, + output wire [`RX_RESP_OOO_MR_INGRESS_DATA_WIDTH - 1 : 0] RX_RESP_fetch_mr_ingress_data, + output wire RX_RESP_fetch_mr_ingress_start, + output wire RX_RESP_fetch_mr_ingress_last, + input wire RX_RESP_fetch_mr_ingress_ready, + + input wire RX_RESP_fetch_mr_egress_valid, + input wire [`RX_RESP_OOO_MR_EGRESS_HEAD_WIDTH - 1 : 0] RX_RESP_fetch_mr_egress_head, + input wire [`RX_RESP_OOO_MR_EGRESS_DATA_WIDTH - 1 : 0] RX_RESP_fetch_mr_egress_data, + input wire RX_RESP_fetch_mr_egress_start, + input wire RX_RESP_fetch_mr_egress_last, + output wire RX_RESP_fetch_mr_egress_ready, + +//RX : Cxt for receive RESP + output wire RX_REQ_fetch_mr_ingress_valid, + output wire [`RX_REQ_OOO_MR_INGRESS_HEAD_WIDTH - 1 : 0] RX_REQ_fetch_mr_ingress_head, + output wire [`RX_REQ_OOO_MR_INGRESS_DATA_WIDTH - 1 : 0] RX_REQ_fetch_mr_ingress_data, + output wire RX_REQ_fetch_mr_ingress_start, + output wire RX_REQ_fetch_mr_ingress_last, + input wire RX_REQ_fetch_mr_ingress_ready, + + input wire RX_REQ_fetch_mr_egress_valid, + input wire [`RX_REQ_OOO_MR_EGRESS_HEAD_WIDTH - 1 : 0] RX_REQ_fetch_mr_egress_head, + input wire [`RX_REQ_OOO_MR_EGRESS_DATA_WIDTH - 1 : 0] RX_REQ_fetch_mr_egress_data, + input wire RX_REQ_fetch_mr_egress_start, + input wire RX_REQ_fetch_mr_egress_last, + output wire RX_REQ_fetch_mr_egress_ready, + +/*************************** Interface with DMASubsystem **********************************************/ + output wire TX_REQ_dma_wr_req_valid, + output wire TX_REQ_dma_wr_req_last, + output wire [`DMA_HEAD_WIDTH - 1 : 0] TX_REQ_dma_wr_req_head, + output wire [`DMA_DATA_WIDTH - 1 : 0] TX_REQ_dma_wr_req_data, + input wire TX_REQ_dma_wr_req_ready, + + output wire RX_REQ_dma_wr_req_valid, + output wire RX_REQ_dma_wr_req_last, + output wire [`DMA_HEAD_WIDTH - 1 : 0] RX_REQ_dma_wr_req_head, + output wire [`DMA_DATA_WIDTH - 1 : 0] RX_REQ_dma_wr_req_data, + input wire RX_REQ_dma_wr_req_ready, + + output wire RX_RESP_dma_wr_req_valid, + output wire RX_RESP_dma_wr_req_last, + output wire [`DMA_HEAD_WIDTH - 1 : 0] RX_RESP_dma_wr_req_head, + output wire [`DMA_DATA_WIDTH - 1 : 0] RX_RESP_dma_wr_req_data, + input wire RX_RESP_dma_wr_req_ready, + + output wire TX_REQ_dma_rd_req_valid, + output wire [`DMA_HEAD_WIDTH - 1 : 0] TX_REQ_dma_rd_req_head, + output wire [`DMA_DATA_WIDTH - 1 : 0] TX_REQ_dma_rd_req_data, + output wire TX_REQ_dma_rd_req_last, + input wire TX_REQ_dma_rd_req_ready, + + input wire TX_REQ_dma_rd_rsp_valid, + input wire [`DMA_HEAD_WIDTH - 1 : 0] TX_REQ_dma_rd_rsp_head, + input wire [`DMA_DATA_WIDTH - 1 : 0] TX_REQ_dma_rd_rsp_data, + input wire TX_REQ_dma_rd_rsp_last, + output wire TX_REQ_dma_rd_rsp_ready, + + output wire TX_RESP_dma_rd_req_valid, + output wire [`DMA_HEAD_WIDTH - 1 : 0] TX_RESP_dma_rd_req_head, + output wire [`DMA_DATA_WIDTH - 1 : 0] TX_RESP_dma_rd_req_data, + output wire TX_RESP_dma_rd_req_last, + input wire TX_RESP_dma_rd_req_ready, + + input wire TX_RESP_dma_rd_rsp_valid, + input wire [`DMA_HEAD_WIDTH - 1 : 0] TX_RESP_dma_rd_rsp_head, + input wire [`DMA_DATA_WIDTH - 1 : 0] TX_RESP_dma_rd_rsp_data, + input wire TX_RESP_dma_rd_rsp_last, + output wire TX_RESP_dma_rd_rsp_ready, +/*************************** Interface with TransportSubsystem ****************************************/ +//TX : Inject pkt header + output wire TX_egress_pkt_valid, + output wire [`PKT_META_BUS_WIDTH - 1 : 0] TX_egress_pkt_head, + input wire TX_egress_pkt_ready, + +//TX : Insert REQ payload + output wire TX_insert_req_valid, + output wire TX_insert_req_start, + output wire TX_insert_req_last, + output wire [`MAX_DB_SLOT_NUM_LOG - 1 : 0] TX_insert_req_head, + output wire [`PACKET_BUFFER_SLOT_WIDTH - 1 : 0] TX_insert_req_data, + input wire TX_insert_req_ready, + + input wire TX_insert_resp_valid, + input wire [`PACKET_BUFFER_SLOT_WIDTH - 1 : 0] TX_insert_resp_data, + +//RX Interfaces + input wire RX_ingress_pkt_valid, + input wire [`PKT_META_BUS_WIDTH - 1 : 0] RX_ingress_pkt_head, + output wire RX_ingress_pkt_ready, + +//RX : Delete REQ payload + output wire RX_delete_req_valid, + output wire [`MAX_DB_SLOT_NUM_LOG * 2- 1 : 0] RX_delete_req_head, + input wire RX_delete_req_ready, + + input wire RX_delete_resp_valid, + input wire RX_delete_resp_start, + input wire RX_delete_resp_last, + input wire [`PACKET_BUFFER_SLOT_WIDTH - 1 : 0] RX_delete_resp_data, + output wire RX_delete_resp_ready + +); + +/*------------------------------------------- Input/Output Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Macros Definition : Begin ---------------------------------------*/ +/*------------------------------------------- Local Macros Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Variables Definition : Begin ------------------------------------*/ +/*------------------------------------------- Local Variables Definition : End --------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : Begin ---------------------------------------*/ +RDMACore RDMACore_Inst( + .clk ( clk ), + .rst ( rst ), + + .TX_REQ_sub_wqe_valid ( TX_REQ_sub_wqe_valid ), + .TX_REQ_sub_wqe_meta ( TX_REQ_sub_wqe_meta ), + .TX_REQ_sub_wqe_ready ( TX_REQ_sub_wqe_ready ), + + .TX_REQ_cq_req_valid ( TX_REQ_cq_req_valid ), + .TX_REQ_cq_req_head ( TX_REQ_cq_req_head ), + .TX_REQ_cq_req_ready ( TX_REQ_cq_req_ready ), + + .TX_REQ_cq_resp_valid ( TX_REQ_cq_resp_valid ), + .TX_REQ_cq_resp_head ( TX_REQ_cq_resp_head ), + .TX_REQ_cq_resp_ready ( TX_REQ_cq_resp_ready ), + + .TX_REQ_eq_req_valid ( TX_REQ_eq_req_valid ), + .TX_REQ_eq_req_head ( TX_REQ_eq_req_head ), + .TX_REQ_eq_req_ready ( TX_REQ_eq_req_ready ), + + .TX_REQ_eq_resp_valid ( TX_REQ_eq_resp_valid ), + .TX_REQ_eq_resp_head ( TX_REQ_eq_resp_head ), + .TX_REQ_eq_resp_ready ( TX_REQ_eq_resp_ready ), + + .RQ_wqe_req_valid ( RQ_wqe_req_valid ), + .RQ_wqe_req_head ( RQ_wqe_req_head ), + .RQ_wqe_req_start ( RQ_wqe_req_start ), + .RQ_wqe_req_last ( RQ_wqe_req_last ), + .RQ_wqe_req_ready ( RQ_wqe_req_ready ), + + .RQ_wqe_resp_valid ( RQ_wqe_resp_valid ), + .RQ_wqe_resp_head ( RQ_wqe_resp_head ), + .RQ_wqe_resp_data ( RQ_wqe_resp_data ), + .RQ_wqe_resp_start ( RQ_wqe_resp_start ), + .RQ_wqe_resp_last ( RQ_wqe_resp_last ), + .RQ_wqe_resp_ready ( RQ_wqe_resp_ready ), + + .RQ_cache_offset_wen ( RQ_cache_offset_wen ), + .RQ_cache_offset_addr ( RQ_cache_offset_addr ), + .RQ_cache_offset_din ( RQ_cache_offset_din ), + .RQ_cache_offset_dout ( RQ_cache_offset_dout ), + + .RQ_offset_wen ( RQ_offset_wen ), + .RQ_offset_addr ( RQ_offset_addr ), + .RQ_offset_din ( RQ_offset_din ), + .RQ_offset_dout ( RQ_offset_dout ), + + .RQ_cache_owned_wen ( RQ_cache_owned_wen ), + .RQ_cache_owned_addr ( RQ_cache_owned_addr ), + .RQ_cache_owned_din ( RQ_cache_owned_din ), + .RQ_cache_owned_dout ( RQ_cache_owned_dout ), + + .RX_REQ_cq_req_valid ( RX_REQ_cq_req_valid ), + .RX_REQ_cq_req_head ( RX_REQ_cq_req_head ), + .RX_REQ_cq_req_ready ( RX_REQ_cq_req_ready ), + + .RX_REQ_cq_resp_valid ( RX_REQ_cq_resp_valid ), + .RX_REQ_cq_resp_head ( RX_REQ_cq_resp_head ), + .RX_REQ_cq_resp_ready ( RX_REQ_cq_resp_ready ), + + .RX_REQ_eq_req_valid ( RX_REQ_eq_req_valid ), + .RX_REQ_eq_req_head ( RX_REQ_eq_req_head ), + .RX_REQ_eq_req_ready ( RX_REQ_eq_req_ready ), + + .RX_REQ_eq_resp_valid ( RX_REQ_eq_resp_valid ), + .RX_REQ_eq_resp_head ( RX_REQ_eq_resp_head ), + .RX_REQ_eq_resp_ready ( RX_REQ_eq_resp_ready ), + + .RX_RESP_cq_req_valid ( RX_RESP_cq_req_valid ), + .RX_RESP_cq_req_head ( RX_RESP_cq_req_head ), + .RX_RESP_cq_req_ready ( RX_RESP_cq_req_ready ), + + .RX_RESP_cq_resp_valid ( RX_RESP_cq_resp_valid ), + .RX_RESP_cq_resp_head ( RX_RESP_cq_resp_head ), + .RX_RESP_cq_resp_ready ( RX_RESP_cq_resp_ready ), + + .RX_RESP_eq_req_valid ( RX_RESP_eq_req_valid ), + .RX_RESP_eq_req_head ( RX_RESP_eq_req_head ), + .RX_RESP_eq_req_ready ( RX_RESP_eq_req_ready ), + + .RX_RESP_eq_resp_valid ( RX_RESP_eq_resp_valid ), + .RX_RESP_eq_resp_head ( RX_RESP_eq_resp_head ), + .RX_RESP_eq_resp_ready ( RX_RESP_eq_resp_ready ), + + .TX_REQ_fetch_cxt_ingress_valid ( TX_REQ_fetch_cxt_ingress_valid ), + .TX_REQ_fetch_cxt_ingress_head ( TX_REQ_fetch_cxt_ingress_head ), + .TX_REQ_fetch_cxt_ingress_data ( TX_REQ_fetch_cxt_ingress_data ), + .TX_REQ_fetch_cxt_ingress_start ( TX_REQ_fetch_cxt_ingress_start ), + .TX_REQ_fetch_cxt_ingress_last ( TX_REQ_fetch_cxt_ingress_last ), + .TX_REQ_fetch_cxt_ingress_ready ( TX_REQ_fetch_cxt_ingress_ready ), + + .TX_REQ_fetch_cxt_egress_valid ( TX_REQ_fetch_cxt_egress_valid ), + .TX_REQ_fetch_cxt_egress_head ( TX_REQ_fetch_cxt_egress_head ), + .TX_REQ_fetch_cxt_egress_data ( TX_REQ_fetch_cxt_egress_data ), + .TX_REQ_fetch_cxt_egress_start ( TX_REQ_fetch_cxt_egress_start ), + .TX_REQ_fetch_cxt_egress_last ( TX_REQ_fetch_cxt_egress_last ), + .TX_REQ_fetch_cxt_egress_ready ( TX_REQ_fetch_cxt_egress_ready ), + + .RX_REQ_fetch_cxt_ingress_valid ( RX_REQ_fetch_cxt_ingress_valid ), + .RX_REQ_fetch_cxt_ingress_head ( RX_REQ_fetch_cxt_ingress_head ), + .RX_REQ_fetch_cxt_ingress_data ( RX_REQ_fetch_cxt_ingress_data ), + .RX_REQ_fetch_cxt_ingress_start ( RX_REQ_fetch_cxt_ingress_start ), + .RX_REQ_fetch_cxt_ingress_last ( RX_REQ_fetch_cxt_ingress_last ), + .RX_REQ_fetch_cxt_ingress_ready ( RX_REQ_fetch_cxt_ingress_ready ), + + .RX_REQ_fetch_cxt_egress_valid ( RX_REQ_fetch_cxt_egress_valid ), + .RX_REQ_fetch_cxt_egress_head ( RX_REQ_fetch_cxt_egress_head ), + .RX_REQ_fetch_cxt_egress_data ( RX_REQ_fetch_cxt_egress_data ), + .RX_REQ_fetch_cxt_egress_start ( RX_REQ_fetch_cxt_egress_start ), + .RX_REQ_fetch_cxt_egress_last ( RX_REQ_fetch_cxt_egress_last ), + .RX_REQ_fetch_cxt_egress_ready ( RX_REQ_fetch_cxt_egress_ready ), + + .RX_RESP_fetch_cxt_ingress_valid ( RX_RESP_fetch_cxt_ingress_valid ), + .RX_RESP_fetch_cxt_ingress_head ( RX_RESP_fetch_cxt_ingress_head ), + .RX_RESP_fetch_cxt_ingress_data ( RX_RESP_fetch_cxt_ingress_data ), + .RX_RESP_fetch_cxt_ingress_start ( RX_RESP_fetch_cxt_ingress_start ), + .RX_RESP_fetch_cxt_ingress_last ( RX_RESP_fetch_cxt_ingress_last ), + .RX_RESP_fetch_cxt_ingress_ready ( RX_RESP_fetch_cxt_ingress_ready ), + + .RX_RESP_fetch_cxt_egress_valid ( RX_RESP_fetch_cxt_egress_valid ), + .RX_RESP_fetch_cxt_egress_head ( RX_RESP_fetch_cxt_egress_head ), + .RX_RESP_fetch_cxt_egress_data ( RX_RESP_fetch_cxt_egress_data ), + .RX_RESP_fetch_cxt_egress_start ( RX_RESP_fetch_cxt_egress_start ), + .RX_RESP_fetch_cxt_egress_last ( RX_RESP_fetch_cxt_egress_last ), + .RX_RESP_fetch_cxt_egress_ready ( RX_RESP_fetch_cxt_egress_ready ), + + .TX_REQ_fetch_mr_ingress_valid ( TX_REQ_fetch_mr_ingress_valid ), + .TX_REQ_fetch_mr_ingress_head ( TX_REQ_fetch_mr_ingress_head ), + .TX_REQ_fetch_mr_ingress_data ( TX_REQ_fetch_mr_ingress_data ), + .TX_REQ_fetch_mr_ingress_start ( TX_REQ_fetch_mr_ingress_start ), + .TX_REQ_fetch_mr_ingress_last ( TX_REQ_fetch_mr_ingress_last ), + .TX_REQ_fetch_mr_ingress_ready ( TX_REQ_fetch_mr_ingress_ready ), + + .TX_REQ_fetch_mr_egress_valid ( TX_REQ_fetch_mr_egress_valid ), + .TX_REQ_fetch_mr_egress_head ( TX_REQ_fetch_mr_egress_head ), + .TX_REQ_fetch_mr_egress_data ( TX_REQ_fetch_mr_egress_data ), + .TX_REQ_fetch_mr_egress_start ( TX_REQ_fetch_mr_egress_start ), + .TX_REQ_fetch_mr_egress_last ( TX_REQ_fetch_mr_egress_last ), + .TX_REQ_fetch_mr_egress_ready ( TX_REQ_fetch_mr_egress_ready ), + + .RX_RESP_fetch_mr_ingress_valid ( RX_RESP_fetch_mr_ingress_valid ), + .RX_RESP_fetch_mr_ingress_head ( RX_RESP_fetch_mr_ingress_head ), + .RX_RESP_fetch_mr_ingress_data ( RX_RESP_fetch_mr_ingress_data ), + .RX_RESP_fetch_mr_ingress_start ( RX_RESP_fetch_mr_ingress_start ), + .RX_RESP_fetch_mr_ingress_last ( RX_RESP_fetch_mr_ingress_last ), + .RX_RESP_fetch_mr_ingress_ready ( RX_RESP_fetch_mr_ingress_ready ), + + .RX_RESP_fetch_mr_egress_valid ( RX_RESP_fetch_mr_egress_valid ), + .RX_RESP_fetch_mr_egress_head ( RX_RESP_fetch_mr_egress_head ), + .RX_RESP_fetch_mr_egress_data ( RX_RESP_fetch_mr_egress_data ), + .RX_RESP_fetch_mr_egress_start ( RX_RESP_fetch_mr_egress_start ), + .RX_RESP_fetch_mr_egress_last ( RX_RESP_fetch_mr_egress_last ), + .RX_RESP_fetch_mr_egress_ready ( RX_RESP_fetch_mr_egress_ready ), + + .RX_REQ_fetch_mr_ingress_valid ( RX_REQ_fetch_mr_ingress_valid ), + .RX_REQ_fetch_mr_ingress_head ( RX_REQ_fetch_mr_ingress_head ), + .RX_REQ_fetch_mr_ingress_data ( RX_REQ_fetch_mr_ingress_data ), + .RX_REQ_fetch_mr_ingress_start ( RX_REQ_fetch_mr_ingress_start ), + .RX_REQ_fetch_mr_ingress_last ( RX_REQ_fetch_mr_ingress_last ), + .RX_REQ_fetch_mr_ingress_ready ( RX_REQ_fetch_mr_ingress_ready ), + + .RX_REQ_fetch_mr_egress_valid ( RX_REQ_fetch_mr_egress_valid ), + .RX_REQ_fetch_mr_egress_head ( RX_REQ_fetch_mr_egress_head ), + .RX_REQ_fetch_mr_egress_data ( RX_REQ_fetch_mr_egress_data ), + .RX_REQ_fetch_mr_egress_start ( RX_REQ_fetch_mr_egress_start ), + .RX_REQ_fetch_mr_egress_last ( RX_REQ_fetch_mr_egress_last ), + .RX_REQ_fetch_mr_egress_ready ( RX_REQ_fetch_mr_egress_ready ), + + .TX_REQ_dma_wr_req_valid ( TX_REQ_dma_wr_req_valid ), + .TX_REQ_dma_wr_req_last ( TX_REQ_dma_wr_req_last ), + .TX_REQ_dma_wr_req_head ( TX_REQ_dma_wr_req_head ), + .TX_REQ_dma_wr_req_data ( TX_REQ_dma_wr_req_data ), + .TX_REQ_dma_wr_req_ready ( TX_REQ_dma_wr_req_ready ), + + .RX_REQ_dma_wr_req_valid ( RX_REQ_dma_wr_req_valid ), + .RX_REQ_dma_wr_req_last ( RX_REQ_dma_wr_req_last ), + .RX_REQ_dma_wr_req_head ( RX_REQ_dma_wr_req_head ), + .RX_REQ_dma_wr_req_data ( RX_REQ_dma_wr_req_data ), + .RX_REQ_dma_wr_req_ready ( RX_REQ_dma_wr_req_ready ), + + .RX_RESP_dma_wr_req_valid ( RX_RESP_dma_wr_req_valid ), + .RX_RESP_dma_wr_req_last ( RX_RESP_dma_wr_req_last ), + .RX_RESP_dma_wr_req_head ( RX_RESP_dma_wr_req_head ), + .RX_RESP_dma_wr_req_data ( RX_RESP_dma_wr_req_data ), + .RX_RESP_dma_wr_req_ready ( RX_RESP_dma_wr_req_ready ), + + .TX_REQ_dma_rd_req_valid ( TX_REQ_dma_rd_req_valid ), + .TX_REQ_dma_rd_req_head ( TX_REQ_dma_rd_req_head ), + .TX_REQ_dma_rd_req_data ( TX_REQ_dma_rd_req_data ), + .TX_REQ_dma_rd_req_last ( TX_REQ_dma_rd_req_last ), + .TX_REQ_dma_rd_req_ready ( TX_REQ_dma_rd_req_ready ), + + .TX_REQ_dma_rd_rsp_valid ( TX_REQ_dma_rd_rsp_valid ), + .TX_REQ_dma_rd_rsp_head ( TX_REQ_dma_rd_rsp_head ), + .TX_REQ_dma_rd_rsp_data ( TX_REQ_dma_rd_rsp_data ), + .TX_REQ_dma_rd_rsp_last ( TX_REQ_dma_rd_rsp_last ), + .TX_REQ_dma_rd_rsp_ready ( TX_REQ_dma_rd_rsp_ready ), + + .TX_RESP_dma_rd_req_valid ( TX_RESP_dma_rd_req_valid ), + .TX_RESP_dma_rd_req_head ( TX_RESP_dma_rd_req_head ), + .TX_RESP_dma_rd_req_data ( TX_RESP_dma_rd_req_data ), + .TX_RESP_dma_rd_req_last ( TX_RESP_dma_rd_req_last ), + .TX_RESP_dma_rd_req_ready ( TX_RESP_dma_rd_req_ready ), + + .TX_RESP_dma_rd_rsp_valid ( TX_RESP_dma_rd_rsp_valid ), + .TX_RESP_dma_rd_rsp_head ( TX_RESP_dma_rd_rsp_head ), + .TX_RESP_dma_rd_rsp_data ( TX_RESP_dma_rd_rsp_data ), + .TX_RESP_dma_rd_rsp_last ( TX_RESP_dma_rd_rsp_last ), + .TX_RESP_dma_rd_rsp_ready ( TX_RESP_dma_rd_rsp_ready ), + + .TX_egress_pkt_valid ( TX_egress_pkt_valid ), + .TX_egress_pkt_head ( TX_egress_pkt_head ), + .TX_egress_pkt_ready ( TX_egress_pkt_ready ), + + .TX_insert_req_valid ( TX_insert_req_valid ), + .TX_insert_req_start ( TX_insert_req_start ), + .TX_insert_req_last ( TX_insert_req_last ), + .TX_insert_req_head ( TX_insert_req_head ), + .TX_insert_req_data ( TX_insert_req_data ), + .TX_insert_req_ready ( TX_insert_req_ready ), + + .TX_insert_resp_valid ( TX_insert_resp_valid ), + .TX_insert_resp_data ( TX_insert_resp_data ), + + .RX_ingress_pkt_valid ( RX_ingress_pkt_valid ), + .RX_ingress_pkt_head ( RX_ingress_pkt_head ), + .RX_ingress_pkt_ready ( RX_ingress_pkt_ready ), + + .RX_delete_req_valid ( RX_delete_req_valid ), + .RX_delete_req_head ( RX_delete_req_head ), + .RX_delete_req_ready ( RX_delete_req_ready ), + + .RX_delete_resp_valid ( RX_delete_resp_valid ), + .RX_delete_resp_start ( RX_delete_resp_start ), + .RX_delete_resp_last ( RX_delete_resp_last ), + .RX_delete_resp_data ( RX_delete_resp_data ), + .RX_delete_resp_ready ( RX_delete_resp_ready ) +); +/*------------------------------------------- Submodules Instatiation : End -----------------------------------------*/ + +/*------------------------------------------- State Machine Definition : Begin --------------------------------------*/ +/*------------------------------------------- State Machine Definition : End ----------------------------------------*/ + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ +/*------------------------------------------- Variables Decode : End ----------------------------------------------*/ + +/*------------------------------------------- Local Macros Undef : Begin --------------------------------------------*/ +/*------------------------------------------- Local Macros Undef : End ----------------------------------------------*/ + +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/CEU/CEU.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/CEU/CEU.v new file mode 100644 index 0000000000000000000000000000000000000000..b7f1fa534755f902cc7bf4188b237b7666120644 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/CEU/CEU.v @@ -0,0 +1,833 @@ +`timescale 1ns / 100ps +//************************************************************************* +// > File Name : CEU.v +// > Description: CEU, passes host command to corresponding module. +// > Author : Corning +// > Date : 2020-07-04 +//************************************************************************* + +`include "ceu_def_h.vh" +`include "protocol_engine_def.vh" + + +module CEU #( + parameter DMA_HEAD_WIDTH = 128 // DMA Stream *_head width +) ( + input wire clk, + input wire rst_n, + + /* -------Interact with PIO Interface{begin}------- */ + input wire [63:0] hcr_in_param , + input wire [31:0] hcr_in_modifier , + input wire [63:0] hcr_out_dma_addr , + input wire [31:0] hcr_token , + input wire hcr_go , + input wire hcr_event , + input wire [ 7:0] hcr_op_modifier , + input wire [11:0] hcr_op , + + output wire [63:0] hcr_out_param , + output wire [ 7:0] hcr_status , + output wire hcr_clear , + /* -------Interact with PIO Interface{end}------- */ + + + /* -------Interact with DMA-engine module{begin}------- */ + /* dma_*_head(interact with RDMA modules), valid only in first beat of a packet + * | Reserved | address | Reserved | Byte length | + * | 127:96 | 95:32 | 31:13 | 12:0 | + */ + // DMA Read Request + output wire dma_rd_req_valid , + output wire dma_rd_req_last , + output wire [`DMA_DATA_WIDTH-1:0] dma_rd_req_data , + output wire [`DMA_HEAD_WIDTH-1:0] dma_rd_req_head , + input wire dma_rd_req_ready , + + // DMA Read Response + input wire dma_rd_rsp_valid, + input wire dma_rd_rsp_last , + input wire [`DMA_DATA_WIDTH-1:0] dma_rd_rsp_data , + input wire [`DMA_HEAD_WIDTH-1:0] dma_rd_rsp_head , + output wire dma_rd_rsp_ready, + + // DMA Write Request + output wire dma_wr_req_valid, + output wire dma_wr_req_last , + output wire [`DMA_DATA_WIDTH-1:0] dma_wr_req_data , + output wire [`DMA_HEAD_WIDTH-1:0] dma_wr_req_head , + input wire dma_wr_req_ready, + /* -------Interact with DMA-engine module{end}------- */ + + + //* -------Interact with Context Management Module{begin}------- */ + // CtxMgt (read & write) request + output wire cm_req_valid, + output wire cm_req_last , + output wire [`CEU_DATA_WIDTH-1 :0] cm_req_data , + output wire [`CEU_CM_HEAD_WIDTH-1:0] cm_req_head , + input wire cm_req_ready, + + // CtxMgt read response + input wire cm_rsp_valid, + input wire cm_rsp_last , + input wire [`CEU_DATA_WIDTH-1 :0] cm_rsp_data , + input wire [`CEU_CM_HEAD_WIDTH-1:0] cm_rsp_head , + output wire cm_rsp_ready, + /* -------Interact with Context Management Module{end}------- */ + + + /* -------Interact with virtual-to-physial Module{begin}------- */ + // VirtToPhys write request + output wire v2p_req_valid, + output wire v2p_req_last , + output wire [`CEU_DATA_WIDTH-1 :0] v2p_req_data , + output wire [`CEU_V2P_HEAD_WIDTH-1:0] v2p_req_head , + input wire v2p_req_ready//, + /* -------Interact with virtual-to-physial Module{end}------- */ + +`ifdef CEU_DBG_LOGIC + /* -------APB reated signal{begin}------- */ + ,input wire [`ACC_LOCAL_RW_WIDTH-1:0] rw_data // i, 32; read-writer register interface + ,output wire [`ACC_LOCAL_RW_WIDTH-1:0] rw_init_data // o, + ,output wire [`ACC_LOCAL_RW_WIDTH-1:0] ro_data // o, 32; read-only register interface + ,input wire [32-1:0] dbg_sel // i, 32; debug bus select + ,output wire [32-1:0] dbg_bus // o, 32; debug bus data + //,output wire [`CEU_DBG_WIDTH-1:0] dbg_bus // o, 32; debug bus data + /* -------APB reated signal{end}------- */ +`endif +); + +wire CEU_dma_wr_req_in_valid; +wire CEU_dma_wr_req_in_last; +wire [`DMA_HEAD_WIDTH - 1 : 0] CEU_dma_wr_req_in_head; +wire [256 - 1 : 0] CEU_dma_wr_req_in_data; +wire CEU_dma_wr_req_in_ready; + +wire CEU_dma_rd_rsp_out_valid; +wire [127:0] CEU_dma_rd_rsp_out_head; +wire [255:0] CEU_dma_rd_rsp_out_data; +wire CEU_dma_rd_rsp_out_last; +wire CEU_dma_rd_rsp_out_ready; + +DMAWrReqChannel DMARdRspChannel_CEU( //512 to 256 + .clk ( clk ), + .rst ( !rst_n ), + + .dma_wr_req_in_valid ( dma_rd_rsp_valid ), + .dma_wr_req_in_head ( dma_rd_rsp_head ), + .dma_wr_req_in_data ( dma_rd_rsp_data ), + .dma_wr_req_in_last ( dma_rd_rsp_last ), + .dma_wr_req_in_ready ( dma_rd_rsp_ready ), + + .dma_wr_req_out_valid ( CEU_dma_rd_rsp_out_valid ), + .dma_wr_req_out_head ( CEU_dma_rd_rsp_out_head ), + .dma_wr_req_out_data ( CEU_dma_rd_rsp_out_data ), + .dma_wr_req_out_last ( CEU_dma_rd_rsp_out_last ), + .dma_wr_req_out_ready ( CEU_dma_rd_rsp_out_ready ) +); + + +DMARdRspChannel DMAWrReqChannel_CEU( //256 to 512 + .clk ( clk ), + .rst ( !rst_n ), + + .dma_rd_rsp_in_valid ( CEU_dma_wr_req_in_valid ), + .dma_rd_rsp_in_head ( CEU_dma_wr_req_in_head ), + .dma_rd_rsp_in_data ( CEU_dma_wr_req_in_data ), + .dma_rd_rsp_in_last ( CEU_dma_wr_req_in_last ), + .dma_rd_rsp_in_ready ( CEU_dma_wr_req_in_ready ), + + .dma_rd_rsp_out_valid ( dma_wr_req_valid ), + .dma_rd_rsp_out_head ( dma_wr_req_head ), + .dma_rd_rsp_out_data ( dma_wr_req_data ), + .dma_rd_rsp_out_last ( dma_wr_req_last ), + .dma_rd_rsp_out_ready ( dma_wr_req_ready ) +); + + +/* -------CMD decode{begin}------- */ + +// identify cmd type +wire is_query_dev_lim, is_query_adapter, is_init_ib, is_close_ib, is_set_ib, is_conf_special_qp, is_mad_ifc; +wire is_sw2hw_cq, is_resize_cq, is_sw2hw_eq, is_map_eq, is_modify_qp, is_hw2sw_cq, is_hw2sw_eq, is_query_qp; +wire is_sw2hw_mpt, is_write_mtt, is_hw2sw_mpt; +wire is_init_hca, is_close_hca; +wire is_map_icm, is_unmap_icm; + +// If (`CMD_MAP_ICM | `CMD_UNMAP_ICM) cmd is in cm +wire is_in_cm, is_in_v2p; + +// the module cmd belongs to +wire is_acc_local; +// wire is_rd_local ; +// wire is_wr_local ; +wire is_acc_cm ; +// wire is_rd_cm ; +// wire is_wr_cm ; +wire is_wr_v2p ; +wire is_wr_both ; + + +// If the cmd has inbox / outbox +wire has_inbox; +wire has_outbox; + +/* -------CMD decode{end}------- */ + +/* -------Status encode{begin}------- */ +wire is_bad_op, is_bad_param, is_bad_sys_stat, is_bad_nvmem; + + +// EXECUTE state end (related module has finished execution). +// Assert one cycle to inform CEU_ctrl the end of cmd execution. +wire is_exe_end; +wire acc_local_end; +wire acc_cm_end; +wire wr_v2p_end; +wire wr_both_end; +/* -------Status encode{end}------- */ + + + +/* -------CEU_ctrl FSM relevant{begin}------- */ +localparam IDLE = 4'b0001, + DECODE = 4'b0010, + GET_INBOX = 4'b0100, + EXECUTE = 4'b1000; + +reg [3:0] cur_state; +reg [3:0] nxt_state; + +reg [63:0] reg_in_param ; +reg [31:0] reg_in_modifier ; +reg [63:0] reg_out_dma_addr; +reg [ 7:0] reg_op_modifier ; +reg [11:0] reg_op ; + + +wire is_idle, is_decode, is_get_inbox, is_execute; + + +// inbox relevant +wire [63:0] inbox_addr; +wire [11:0] inbox_len; // length in bytes + +wire [11:0] map_icm_len; +wire [11:0] write_mtt_len; +/* -------CEU_ctrl FSM relevant{end}------- */ + +/* -------MUX{begin}------- */ +wire dma_rrsp_local_ready, dma_rrsp_cm_ready, dma_rrsp_v2p_ready, dma_rrsp_both_ready; + +wire dma_wreq_local_valid, dma_wreq_cm_valid; +wire dma_wreq_local_last , dma_wreq_cm_last ; +wire [`CEU_DATA_WIDTH-1:0] dma_wreq_local_data , dma_wreq_cm_data ; +wire [DMA_HEAD_WIDTH -1:0] dma_wreq_local_head , dma_wreq_cm_head ; + +wire cm_req_cm_valid, cm_req_both_valid; +wire cm_req_cm_last , cm_req_both_last ; +wire [`CEU_DATA_WIDTH -1:0] cm_req_cm_data , cm_req_both_data ; +wire [`CEU_CM_HEAD_WIDTH-1:0] cm_req_cm_head , cm_req_both_head ; + +wire v2p_req_both_valid, v2p_req_v2p_valid; +wire v2p_req_both_last , v2p_req_v2p_last ; +wire [`CEU_DATA_WIDTH-1 :0] v2p_req_both_data , v2p_req_v2p_data ; +wire [`CEU_V2P_HEAD_WIDTH-1:0] v2p_req_both_head , v2p_req_v2p_head ; +/* -------MUX{end}------- */ + +/* -------- DMA Read Response{begin}-------- */ +wire st_dma_rd_rsp_valid; +wire st_dma_rd_rsp_last ; +wire [`CEU_DATA_WIDTH-1:0] st_dma_rd_rsp_data ; +wire [DMA_HEAD_WIDTH-1 :0] st_dma_rd_rsp_head ; +wire st_dma_rd_rsp_ready; +/* -------- DMA Read Response{end}-------- */ + +`ifdef CEU_DBG_LOGIC +/* -------APB reated signal{begin}------- */ +wire [`CEU_DBG_WIDTH -1:0] ceu_dbg ; +wire [`TOP_DBG_WIDTH -1:0] top_dbg ; +wire [`ACC_CM_DBG_WIDTH -1:0] acc_cm_dbg ; +wire [`ACC_LOCAL_DBG_WIDTH-1:0] acc_local_dbg; +wire [`WR_BOTH_DBG_WIDTH -1:0] wr_both_dbg ; +wire [`WR_V2P_DBG_WIDTH -1:0] wr_v2p_dbg ; +/* -------APB reated signal{end}------- */ +`endif + +/* -------CMD decode logic{begin}------- */ + + +// acc local cmd type +assign is_query_dev_lim = (reg_op == `CMD_QUERY_DEV_LIM ); +assign is_query_adapter = (reg_op == `CMD_QUERY_ADAPTER ); +assign is_init_ib = (reg_op == `CMD_INIT_IB ); // not realized +assign is_close_ib = (reg_op == `CMD_CLOSE_IB ); // not realized +assign is_set_ib = (reg_op == `CMD_SET_IB ); // not realized +assign is_conf_special_qp = (reg_op == `CMD_CONF_SPECIAL_QP); // not realized +assign is_mad_ifc = (reg_op == `CMD_MAD_IFC ); // not realized + +// acc cm cmd type +assign is_sw2hw_cq = (reg_op == `CMD_SW2HW_CQ ); +assign is_resize_cq = (reg_op == `CMD_RESIZE_CQ); +assign is_sw2hw_eq = (reg_op == `CMD_SW2HW_EQ ); +assign is_map_eq = (reg_op == `CMD_MAP_EQ ); +assign is_hw2sw_cq = (reg_op == `CMD_HW2SW_CQ ); +assign is_hw2sw_eq = (reg_op == `CMD_HW2SW_EQ ); +assign is_query_qp = (reg_op == `CMD_QUERY_QP ); +assign is_modify_qp = `IS_MODIFY_QP(reg_op); + +// wr v2p cmd type +assign is_sw2hw_mpt = (reg_op == `CMD_SW2HW_MPT); +assign is_write_mtt = (reg_op == `CMD_WRITE_MTT); +assign is_hw2sw_mpt = (reg_op == `CMD_HW2SW_MPT); + +// wr v2p & cm cmd type +assign is_init_hca = (reg_op == `CMD_INIT_HCA ); +assign is_close_hca = (reg_op == `CMD_CLOSE_HCA); + +// wr v2p || cm cmd type +assign is_map_icm = (reg_op == `CMD_MAP_ICM ); +assign is_unmap_icm = (reg_op == `CMD_UNMAP_ICM); + +// module selection for v2p || cm cmd type +assign is_in_cm = (reg_op_modifier == 1); +assign is_in_v2p = (reg_op_modifier == 2); + + +// +assign is_acc_local = is_query_dev_lim | is_query_adapter | is_init_ib | is_close_ib | + is_set_ib | is_conf_special_qp | is_mad_ifc; +// assign is_rd_local = is_query_dev_lim | is_query_adapter; +// assign is_wr_local = 0; +assign is_acc_cm = is_sw2hw_cq | is_resize_cq | is_sw2hw_eq | is_map_eq | + is_hw2sw_cq | is_hw2sw_eq | is_query_qp | is_modify_qp | + (is_map_icm & is_in_cm) | (is_unmap_icm & is_in_cm); +// assign is_rd_cm = is_query_qp; +// assign is_wr_cm = is_sw2hw_cq | is_resize_cq | is_sw2hw_eq | is_map_eq | +// is_hw2sw_cq | is_hw2sw_eq | is_modify_qp | +// (is_map_icm & is_in_cm) | (is_unmap_icm & is_in_cm); +assign is_wr_v2p = is_sw2hw_mpt | is_write_mtt | is_hw2sw_mpt | + (is_map_icm & is_in_v2p) | (is_unmap_icm & is_in_v2p); +assign is_wr_both = is_init_hca | is_close_hca; + +// if cmd has inbox or outbox +assign has_inbox = is_init_hca | is_map_icm | is_sw2hw_cq | is_resize_cq | + is_sw2hw_eq | is_sw2hw_mpt | is_write_mtt | is_init_ib | + is_set_ib | (is_modify_qp & (reg_op_modifier == 0)); +assign has_outbox = is_query_dev_lim | is_query_adapter | is_query_qp | is_mad_ifc; +/* -------CMD decode logic{end}------- */ + + + +/* -------Status encode{begin}------- */ + +// reasons for error +// FIXME: Adding cmd should fix this signal +assign is_bad_op = ~(is_map_icm | is_unmap_icm | is_init_hca | is_close_hca | + is_sw2hw_cq | is_resize_cq | is_sw2hw_eq | is_write_mtt | + is_hw2sw_cq | is_hw2sw_mpt | is_query_qp | is_query_adapter | + is_map_eq | is_modify_qp | is_hw2sw_eq | is_query_dev_lim | + is_sw2hw_mpt| is_mad_ifc); +assign is_bad_param = ((is_map_icm | is_unmap_icm) & (~(is_in_cm | is_in_v2p))) | // param in map_icm, unmap_icm + (has_inbox & (reg_in_param == 0)) | // there's inbox, but in_param is zero (no valid inbox addr) + (has_outbox & (reg_out_dma_addr == 0)) | // there's inbox, but in_param is zero (no valid inbox addr) + (is_modify_qp & !((reg_op_modifier == 0) | (reg_op_modifier == 2) | (reg_op_modifier == 3))) | + (is_mad_ifc & !(reg_op_modifier == 8'h1)); +assign is_bad_sys_stat = (rst_n == 0); + +// assign is_bad_nvmem = ; + + +// end of module execution +assign is_exe_end = (is_acc_local & acc_local_end) | + (is_wr_both & wr_both_end ) | + (is_acc_cm & acc_cm_end ) | + (is_wr_v2p & wr_v2p_end ); + +// output hcr register +assign hcr_out_param = 0; // in this version, out_param as an output is unused +assign hcr_status = !is_idle ? (({8{is_bad_op }} & `HGRNIC_CMD_STAT_BAD_OP ) | + ({8{is_bad_param }} & `HGRNIC_CMD_STAT_BAD_PARAM ) | + ({8{is_bad_sys_stat}} & `HGRNIC_CMD_STAT_BAD_SYS_STATE) | + ({8{is_bad_nvmem }} & `HGRNIC_CMD_STAT_BAD_NVMEM )) : 0; +assign hcr_clear = ((|hcr_status) && is_decode) || + (is_exe_end && is_execute); +/* -------Status encode{end}------- */ + +/* -------get inbox{begin}------- */ + +// inbox addr +assign inbox_addr = reg_in_param; + +// inbox length (in bytes) +assign map_icm_len = {reg_in_modifier[7:1] + reg_in_modifier[0], 5'b0}; +assign write_mtt_len = {reg_in_modifier[7:2] + (|reg_in_modifier[1:0]) + 7'd1, 5'b0}; + +assign inbox_len = ({12{is_init_hca }} & `INBOX_LEN_INIT_HCA ) | + ({12{is_sw2hw_cq }} & `INBOX_LEN_SW2HW_CQ ) | + ({12{is_resize_cq}} & `INBOX_LEN_RESIZE_CQ) | + ({12{is_sw2hw_eq }} & `INBOX_LEN_SW2HW_EQ ) | + ({12{is_sw2hw_mpt}} & `INBOX_LEN_SW2HW_MPT) | + ({12{is_modify_qp}} & `INBOX_LEN_MODIFY_QP) | + ({12{is_map_icm }} & map_icm_len ) | + ({12{is_write_mtt}} & write_mtt_len ); +/* -------get inbox{end}------- */ + + +//------------------------------{CEU_ctrl FSM}begin------------------------------// +/******************** Stage 1: State Register **********************/ + +always @(posedge clk or negedge rst_n) begin + if(~rst_n) + cur_state <= `TD IDLE; + else + cur_state <= `TD nxt_state; +end + + +always @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + reg_in_param <= `TD 0; + reg_in_modifier <= `TD 0; + reg_out_dma_addr <= `TD 0; + reg_op_modifier <= `TD 0; + reg_op <= `TD 0; + end + else if ((is_execute & is_exe_end) || (is_decode & (|hcr_status))) begin + reg_in_param <= `TD 0; + reg_in_modifier <= `TD 0; + reg_out_dma_addr <= `TD 0; + reg_op_modifier <= `TD 0; + reg_op <= `TD 0; + end + else if (is_idle & (hcr_go == 1)) begin + reg_in_param <= `TD hcr_in_param ; + reg_in_modifier <= `TD hcr_in_modifier ; + reg_out_dma_addr <= `TD hcr_out_dma_addr; + reg_op_modifier <= `TD hcr_op_modifier ; + reg_op <= `TD hcr_op ; + end +end + + +/******************** Stage 2: State Transition **********************/ +assign is_idle = (cur_state == IDLE ); +assign is_decode = (cur_state == DECODE ); +assign is_get_inbox = (cur_state == GET_INBOX); +assign is_execute = (cur_state == EXECUTE ); + +always @(*) begin + case(cur_state) + IDLE: begin + if (hcr_go == 1) begin // incomming HCR command + nxt_state = DECODE; + end + else begin + nxt_state = IDLE; + end + end + DECODE: begin + if (hcr_status != 0) begin + nxt_state = IDLE; + end + else if ((hcr_status == 0) & has_inbox) begin + nxt_state = GET_INBOX; + end + else begin // (hcr_status == 0) & (!has_inbox) + nxt_state = EXECUTE; + end + end + GET_INBOX: begin + if (dma_rd_req_valid & dma_rd_req_ready) begin // send DMA read request + nxt_state = EXECUTE; + end + else begin + nxt_state = GET_INBOX; + end + end + EXECUTE: begin + if (is_exe_end) begin + nxt_state = IDLE; + end + else begin + nxt_state = EXECUTE; + end + end + default: begin + nxt_state = IDLE; + end + endcase +end + + +/******************** Stage 3: Output **********************/ + +// output for dma read request +/*************************head********************************* +dma read inbox request head +|--------| --------------------64bit---------------------- | +| 127: | R | inbox_addr | +| 64 | (63:32) | (63:32 bit) | +|--------|-------------------------------------------------| +| 63: | inbox_addr | R | inbox_len | +| 0 | (31: 0 bit) | (31:12) | (11:0 bit) | +|--------|-------------------------------------------------| + *****************************************************************/ +assign dma_rd_req_valid = is_get_inbox; +assign dma_rd_req_last = is_get_inbox; +assign dma_rd_req_data = 0; // dma read request doesn't use data signal +assign dma_rd_req_head = is_get_inbox ? {32'd0, inbox_addr, 20'd0, inbox_len} : 0; + +//------------------------------{CEU_ctrl FSM}end------------------------------// + +/* --------stream reg{begin}-------- */ +st_reg #( + .TUSER_WIDTH ( DMA_HEAD_WIDTH ), + .TDATA_WIDTH ( `CEU_DATA_WIDTH ) +) ceu_st_reg ( + .clk ( clk ), // i, 1 + .rst_n ( rst_n ), // i, 1 + + /* -------input axis-like interface{begin}------- */ + .axis_tvalid ( CEU_dma_rd_rsp_out_valid ), // i, 1 + .axis_tlast ( CEU_dma_rd_rsp_out_last ), // i, 1 + .axis_tuser ( CEU_dma_rd_rsp_out_head ), // i, TUSER_WIDTH + .axis_tdata ( beat_trans(CEU_dma_rd_rsp_out_data) ), // i, `CEU_DATA_WIDTH + .axis_tready ( CEU_dma_rd_rsp_out_ready ), // o, 1 + /* -------input axis-like interface{end}------- */ + + /* -------output in_reg inteface{begin}------- */ + .axis_reg_tvalid ( st_dma_rd_rsp_valid ), // o, 1 + .axis_reg_tlast ( st_dma_rd_rsp_last ), // o, 1 + .axis_reg_tuser ( st_dma_rd_rsp_head ), // o, TUSER_WIDTH + .axis_reg_tdata ( st_dma_rd_rsp_data ), // o, `CEU_DATA_WIDTH + .axis_reg_tready ( st_dma_rd_rsp_ready ) // i, 1 + /* -------output in_reg inteface{end}------- */ +); +/* --------stream reg{end}-------- */ + +/* -------DMA Read Signal MUX{begin}------- */ +assign st_dma_rd_rsp_ready = (is_acc_local & dma_rrsp_local_ready) | + (is_acc_cm & dma_rrsp_cm_ready ) | + (is_wr_v2p & dma_rrsp_v2p_ready ) | + (is_wr_both & dma_rrsp_both_ready ); +/* -------DMA Read Signal MUX{end}------- */ + + +/* -------DMA Write Signal MUX{begin}------- */ +assign CEU_dma_wr_req_in_valid = (is_acc_local & dma_wreq_local_valid) | + (is_acc_cm & dma_wreq_cm_valid ); +assign CEU_dma_wr_req_in_last = (is_acc_local & dma_wreq_local_last) | + (is_acc_cm & dma_wreq_cm_last ); +assign CEU_dma_wr_req_in_data = beat_trans( + ({`CEU_DATA_WIDTH {is_acc_local}} & dma_wreq_local_data) | + ({`CEU_DATA_WIDTH {is_acc_cm }} & dma_wreq_cm_data ) + ); +assign CEU_dma_wr_req_in_head = ({DMA_HEAD_WIDTH{is_acc_local}} & dma_wreq_local_head) | + ({DMA_HEAD_WIDTH{is_acc_cm }} & dma_wreq_cm_head ); +/* -------DMA Write Signal MUX{end}------- */ + + +/* -------Context Management Request Signal MUX{begin}------- */ +assign cm_req_valid = (is_wr_both & cm_req_both_valid) | + (is_acc_cm & cm_req_cm_valid ); +assign cm_req_last = (is_wr_both & cm_req_both_last) | + (is_acc_cm & cm_req_cm_last ); +assign cm_req_data = ({`CEU_DATA_WIDTH {is_wr_both}} & cm_req_both_data) | + ({`CEU_DATA_WIDTH {is_acc_cm }} & cm_req_cm_data ); +assign cm_req_head = ({`CEU_CM_HEAD_WIDTH{is_wr_both}} & cm_req_both_head) | + ({`CEU_CM_HEAD_WIDTH{is_acc_cm }} & cm_req_cm_head ); +/* -------Context Management Request Signal MUX{end}------- */ + + +/* -------Virtual to physical write Request Signal MUX{begin}------- */ +assign v2p_req_valid = (is_wr_both & v2p_req_both_valid) | + (is_wr_v2p & v2p_req_v2p_valid ); +assign v2p_req_last = (is_wr_both & v2p_req_both_last) | + (is_wr_v2p & v2p_req_v2p_last ); +assign v2p_req_data = ({`CEU_DATA_WIDTH {is_wr_both}} & v2p_req_both_data) | + ({`CEU_DATA_WIDTH {is_wr_v2p }} & v2p_req_v2p_data ); +assign v2p_req_head = ({`CEU_V2P_HEAD_WIDTH{is_wr_both}} & v2p_req_both_head) | + ({`CEU_V2P_HEAD_WIDTH{is_wr_v2p }} & v2p_req_v2p_head ); +/* -------Virtual to physical write Request Signal MUX{end}------- */ +assign dma_rrsp_local_ready = 0; +acc_local #( + .DMA_HEAD_WIDTH ( DMA_HEAD_WIDTH ) // DMA Stream *_head width +) CEU_ACC_LOCAL ( + .clk ( clk ),// i, 1 + .rst_n ( rst_n ),// i, 1 + + /* -------DMA Interface{begin}------- */ + /* dma_*_head(interact with RDMA modules), valid only in first beat of a packet + * | Reserved | address | Reserved | Byte length | + * | 127:96 | 95:32 | 31:13 | 12:0 | + */ + // // DMA read response + // .dma_rd_rsp_valid ( st_dma_rd_rsp_valid ), // i, 1 + // .dma_rd_rsp_last ( st_dma_rd_rsp_last ), // i, 1 + // .dma_rd_rsp_data ( st_dma_rd_rsp_data ), // i, `CEU_DATA_WIDTH + // .dma_rd_rsp_head ( st_dma_rd_rsp_head ), // i, DMA_HEAD_WIDTH + // .dma_rd_rsp_ready ( dma_rrsp_local_ready ), // o, 1 + + // DMA write req + .dma_wr_req_valid ( dma_wreq_local_valid ), // o, 1 + .dma_wr_req_last ( dma_wreq_local_last ), // o, 1 + .dma_wr_req_data ( dma_wreq_local_data ), // o, `CEU_DATA_WIDTH + .dma_wr_req_head ( dma_wreq_local_head ), // o, DMA_HEAD_WIDTH + .dma_wr_req_ready ( CEU_dma_wr_req_in_ready ), // i, 1 + /* -------DMA Interface{end}------- */ + + /* -------CMD Information{begin}------- */ + .op ( reg_op ), // i, 12 + .outbox_addr ( reg_out_dma_addr ), // i, 64 + .op_modifier ( reg_op_modifier ), // i, 8 + .is_bad_nvmem ( is_bad_nvmem ), // o, 1 ; used to indicate if data of local ram is not ready + /* -------CMD Information{end}------- */ + + + .start ( is_acc_local & is_execute ), // i, 1 + .finish ( acc_local_end ) // o, 1 + +`ifdef CEU_DBG_LOGIC + ,.rw_data ( rw_data ) // i, `ACC_LOCAL_RW_WIDTH + ,.rw_init_data ( rw_init_data ) // o, `ACC_LOCAL_RW_WIDTH + ,.dbg_bus ( acc_local_dbg ) // o, `ACC_LOCAL_DBG_WIDTH +`endif +); + +acc_cm #( + .DMA_HEAD_WIDTH ( DMA_HEAD_WIDTH ) // DMA Stream *_head width +) CEU_ACC_CM ( + .clk ( clk ),// i, 1 + .rst_n ( rst_n ),// i, 1 + + /* -------DMA Interface{begin}------- */ + /* dma_*_head(interact with RDMA modules), valid only in first beat of a packet + * | Reserved | address | Reserved | Byte length | + * | 127:96 | 95:32 | 31:13 | 12:0 | + */ + // DMA read response + .dma_rd_rsp_valid ( st_dma_rd_rsp_valid ), // i, 1 + .dma_rd_rsp_last ( st_dma_rd_rsp_last ), // i, 1 + .dma_rd_rsp_data ( st_dma_rd_rsp_data ), // i, `CEU_DATA_WIDTH + .dma_rd_rsp_head ( st_dma_rd_rsp_head ), // i, DMA_HEAD_WIDTH + .dma_rd_rsp_ready ( dma_rrsp_cm_ready ), // o, 1 + + // DMA write req + .dma_wr_req_valid ( dma_wreq_cm_valid ), // o, 1 + .dma_wr_req_last ( dma_wreq_cm_last ), // o, 1 + .dma_wr_req_data ( dma_wreq_cm_data ), // o, `CEU_DATA_WIDTH + .dma_wr_req_head ( dma_wreq_cm_head ), // o, DMA_HEAD_WIDTH + .dma_wr_req_ready ( CEU_dma_wr_req_in_ready ), // i, 1 + /* -------DMA Interface{end}------- */ + + /* -------Context Management Interface{begin}------- */ + // CtxMgt req + .cm_req_valid ( cm_req_cm_valid ), // o, 1 + .cm_req_last ( cm_req_cm_last ), // o, 1 + .cm_req_data ( cm_req_cm_data ), // o, `CEU_DATA_WIDTH + .cm_req_head ( cm_req_cm_head ), // o, `CEU_CM_HEAD_WIDTH + .cm_req_ready ( cm_req_ready ), // i, 1 + + // CtxMgt read resp + .cm_rsp_valid ( cm_rsp_valid ), // i, 1 + .cm_rsp_last ( cm_rsp_last ), // i, 1 + .cm_rsp_data ( cm_rsp_data ), // i, `CEU_DATA_WIDTH + .cm_rsp_head ( cm_rsp_head ), // i, `CEU_CM_HEAD_WIDTH + .cm_rsp_ready ( cm_rsp_ready ), // o, 1 + /* -------Context Management Interface{end}------- */ + + /* -------CMD Information{begin}------- */ + .has_inbox ( has_inbox ), // i, 1 + .op ( reg_op ), // i, 12 + .in_param ( reg_in_param ), // i, 64 + .in_modifier ( reg_in_modifier ), // i, 32 + .outbox_addr ( reg_out_dma_addr ), // i, 64 + /* -------CMD Information{end}------- */ + + + .start ( is_acc_cm & is_execute ), // i, 1 + .finish ( acc_cm_end ) // o, 1 + +`ifdef CEU_DBG_LOGIC + ,.dbg_bus ( acc_cm_dbg ) // o, `ACC_CM_DBG_WIDTH +`endif +); + +wr_v2p #( + .DMA_HEAD_WIDTH ( DMA_HEAD_WIDTH ) // DMA Stream *_head width +) CEU_WR_V2P ( + .clk ( clk ),// i, 1 + .rst_n ( rst_n ),// i, 1 + + /* -------DMA Interface{begin}------- */ + /* dma_*_head(interact with RDMA modules), valid only in first beat of a packet + * | Reserved | address | Reserved | Byte length | + * | 127:96 | 95:32 | 31:13 | 12:0 | + */ + // DMA read response + .dma_rd_rsp_valid ( st_dma_rd_rsp_valid ), // i, 1 + .dma_rd_rsp_last ( st_dma_rd_rsp_last ), // i, 1 + .dma_rd_rsp_data ( st_dma_rd_rsp_data ), // i, `CEU_DATA_WIDTH + .dma_rd_rsp_head ( st_dma_rd_rsp_head ), // i, DMA_HEAD_WIDTH + .dma_rd_rsp_ready ( dma_rrsp_v2p_ready ), // o, 1 + /* -------DMA Interface{end}------- */ + + /* -------Virtual-to-physial Interface{begin}------- */ + // VirtToPhys write req + .v2p_req_valid ( v2p_req_v2p_valid ), // o, 1 + .v2p_req_last ( v2p_req_v2p_last ), // o, 1 + .v2p_req_data ( v2p_req_v2p_data ), // o, `CEU_DATA_WIDTH + .v2p_req_head ( v2p_req_v2p_head ), // o, `CEU_V2P_HEAD_WIDTH + .v2p_req_ready ( v2p_req_ready ), // i, 1 + /* -------Virtual-to-physial Interface{end}------- */ + + /* -------CMD Information{begin}------- */ + .has_inbox ( has_inbox ), // i, 1 + .op ( reg_op ), // i, 12 + .in_param ( reg_in_param ), // i, 64 + .in_modifier ( reg_in_modifier ), // i, 32 + /* -------CMD Information{end}------- */ + + .start ( is_wr_v2p & is_execute ), // i, 1 + .finish ( wr_v2p_end ) // o, 1 + +`ifdef CEU_DBG_LOGIC + ,.dbg_bus ( wr_v2p_dbg ) // o, `WR_V2P_DBG_WIDTH +`endif +); + +wr_both #( + .DMA_HEAD_WIDTH ( DMA_HEAD_WIDTH ) // DMA Stream *_head width +) CEU_WR_BOTH ( + .clk ( clk ), // i, 1 + .rst_n ( rst_n ), // i, 1 + + /* -------DMA Interface{begin}------- */ + /* dma_*_head(interact with RDMA modules), valid only in first beat of a packet + * | Reserved | address | Reserved | Byte length | + * | 127:96 | 95:32 | 31:13 | 12:0 | + */ + // DMA read response + .dma_rd_rsp_valid ( st_dma_rd_rsp_valid ), // i, 1 + // .dma_rd_rsp_last ( st_dma_rd_rsp_last ), // i, 1 + .dma_rd_rsp_data ( st_dma_rd_rsp_data ), // i, `CEU_DATA_WIDTH + // .dma_rd_rsp_head ( st_dma_rd_rsp_head ), // i, DMA_HEAD_WIDTH + .dma_rd_rsp_ready ( dma_rrsp_both_ready ), // o, 1 + /* -------DMA Interface{end}------- */ + + /* -------Virtual-to-physial Interface{begin}------- */ + // VirtToPhys write req + .v2p_req_valid ( v2p_req_both_valid ), // o, 1 + .v2p_req_last ( v2p_req_both_last ), // o, 1 + .v2p_req_data ( v2p_req_both_data ), // o, `CEU_DATA_WIDTH + .v2p_req_head ( v2p_req_both_head ), // o, `CEU_V2P_HEAD_WIDTH + .v2p_req_ready ( v2p_req_ready ), // i, 1 + /* -------Virtual-to-physial Interface{end}------- */ + + /* -------Context Management Interface{begin}------- */ + // CtxMgt req + .cm_req_valid ( cm_req_both_valid ), // o, 1 + .cm_req_last ( cm_req_both_last ), // o, 1 + .cm_req_data ( cm_req_both_data ), // o, `CEU_DATA_WIDTH + .cm_req_head ( cm_req_both_head ), // o, `CEU_CM_HEAD_WIDTH + .cm_req_ready ( cm_req_ready ), // i, 1 + /* -------Context Management Interface{end}------- */ + + /* -------CMD Information{begin}------- */ + .op ( reg_op ), // i, 12 + /* -------CMD Information{end}------- */ + + .start ( is_wr_both & is_execute ), // i, 1 + .finish ( wr_both_end ) // o, 1 + +`ifdef CEU_DBG_LOGIC + ,.dbg_bus ( wr_both_dbg ) // o, `WR_BOTH_DBG_WIDTH +`endif +); + +`ifdef CEU_DBG_LOGIC + +assign ceu_dbg = { top_dbg , + acc_cm_dbg , + acc_local_dbg, + wr_both_dbg , + wr_v2p_dbg }; +assign top_dbg = { cur_state , + nxt_state , + reg_in_param , + reg_in_modifier , + reg_out_dma_addr, + reg_op_modifier , + reg_op }; + +assign ro_data = rw_data; +assign dbg_bus = ceu_dbg >> {dbg_sel, 5'd0}; +//assign dbg_bus = ceu_dbg; + +`endif + +//ceu_ila_0 ceu_ila_0 ( +// .clk ( clk ), +// .probe0 ( cm_req_valid ), +// .probe1 ( cm_req_last ), +// .probe2 ( cm_req_data ), +// .probe3 ( cm_req_head ), +// .probe4 ( cm_req_ready ) +//); + + +//ceu_ila_1 ceu_ila_1 ( +// .clk ( clk ), +// .probe0 ( reg_op ), // i, 12 +// .probe1 ( inbox_len ), // i, 12 +// .probe2 ( hcr_clear ), // i, 1 +// .probe3 ( cur_state ) // i, 4 +//); + +// pio_ila_3 pio_ila_3_inst ( +// .clk (clk), +// .probe0 ( hcr_in_param ), // i, 64 +// .probe1 ( hcr_in_modifier ), // i, 32 +// .probe2 ( hcr_out_dma_addr ), // i, 64 +// .probe3 ( hcr_out_param ), // i, 64 +// .probe4 ( hcr_token ), // i, 32 +// .probe5 ( hcr_status ), // i, 8 +// .probe6 ( hcr_go ), // i, 1 +// .probe7 ( hcr_clear ), // i, 1 +// .probe8 ( hcr_event ), // i, 1 +// .probe9 ( hcr_op_modifier ), // i, 8 +// .probe10 ( hcr_op ) // i, 12 +// ); + +`ifdef ILA_ON +// ila_dma ceu_dma_wr ( +// .clk(clk), // input wire clk + + +// .probe0(dma_wr_req_valid), // input wire [0:0] probe0 +// .probe1(dma_wr_req_head), // input wire [127:0] probe1 +// .probe2(dma_wr_req_data), // input wire [255:0] probe2 +// .probe3(dma_wr_req_ready), // input wire [0:0] probe3 +// .probe4(dma_wr_req_last) // input wire [0:0] probe4 +// ); + +ila_ceu ila_ceu_inst ( + .clk(clk), // input wire clk + + .probe0(hcr_in_param), // input wire [63:0] probe0 + .probe1(hcr_in_modifier), // input wire [31:0] probe1 + .probe2(hcr_out_dma_addr), // input wire [63:0] probe2 + .probe3(hcr_token), // input wire [31:0] probe3 + .probe4(hcr_go), // input wire [0:0] probe4 + .probe5(hcr_event), // input wire [0:0] probe5 + .probe6(hcr_op_modifier), // input wire [7:0] probe6 + .probe7(hcr_op), // input wire [11:0] probe7 + .probe8(hcr_out_param), // input wire [63:0] probe8 + .probe9(hcr_status), // input wire [7:0] probe9 + .probe10(hcr_clear) // input wire [0:0] probe10 +); +`endif + +endmodule diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/CEU/README.md b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/CEU/README.md new file mode 100644 index 0000000000000000000000000000000000000000..28219d4b9505212a7de64cbc59c856e89e0007e3 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/CEU/README.md @@ -0,0 +1,2 @@ +Command Execution Unit. +Handle commands from Host CPU. diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/CEU/acc_cm.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/CEU/acc_cm.v new file mode 100644 index 0000000000000000000000000000000000000000..e36363635ad67a855d732115fa2154cbdd90a8dd --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/CEU/acc_cm.v @@ -0,0 +1,421 @@ +`timescale 1ns / 100ps +//************************************************************************* +// > File Name : acc_cm.v +// > Description: CEU_ACC_CM, Used to pass command to Context Management module. +// > The command includes: +// > inbox: Y, outbox: N: +// > CMD_MAP_ICM +// > CMD_SW2HW_CQ +// > CMD_RESIZE_CQ +// > CMD_SW2HW_EQ +// > inbox: N, outbox: N: +// > CMD_UNMAP_ICM +// > CMD_MAP_EQ +// > CMD_HW2SW_CQ +// > CMD_HW2SW_EQ +// > inbox: N, outbox: Y: +// > CMD_QUERY_QP +// > inbox: Y/N, outbox: N: +// > IS_MODIFY_QP +// > Author: Corning +// > Date : 2020-07-13 +//************************************************************************* + +`include "ceu_def_h.vh" +`include "protocol_engine_def.vh" + +module acc_cm #( + parameter DMA_HEAD_WIDTH = 128 // DMA Stream *_head width +) ( + input wire clk, + input wire rst_n, + + /* -------DMA Interface{begin}------- */ + /* dma_*_head(interact with RDMA modules), valid only in first beat of a packet + * | Reserved | address | Reserved | Byte length | + * | 127:96 | 95:32 | 31:13 | 12:0 | + */ + // DMA read response + input wire dma_rd_rsp_valid, // i, 1 + input wire dma_rd_rsp_last , // i, 1 + input wire [`CEU_DATA_WIDTH-1:0] dma_rd_rsp_data , // i, `CEU_DATA_WIDTH + input wire [DMA_HEAD_WIDTH -1:0] dma_rd_rsp_head , // i, DMA_HEAD_WIDTH + output wire dma_rd_rsp_ready, // o, 1 + + // DMA write req + output wire dma_wr_req_valid, // o, 1 + output wire dma_wr_req_last , // o, 1 + output wire [`CEU_DATA_WIDTH-1:0] dma_wr_req_data , // o, `CEU_DATA_WIDTH + output wire [DMA_HEAD_WIDTH -1:0] dma_wr_req_head , // o, DMA_HEAD_WIDTH + input wire dma_wr_req_ready, // i, 1 + /* -------DMA Interface{end}------- */ + + /* -------Context Management Interface{begin}------- */ + // CTXMgt req + output wire cm_req_valid, // o, 1 + output wire cm_req_last , // o, 1 + output wire [`CEU_DATA_WIDTH -1:0] cm_req_data , // o, `CEU_DATA_WIDTH + output wire [`CEU_CM_HEAD_WIDTH-1:0] cm_req_head , // o, `CEU_CM_HEAD_WIDTH + input wire cm_req_ready, // i, 1 + + // CTXMgt read resp + input wire cm_rsp_valid, // i, 1 + input wire cm_rsp_last , // i, 1 + input wire [`CEU_DATA_WIDTH -1:0] cm_rsp_data , // i, `CEU_DATA_WIDTH + input wire [`CEU_CM_HEAD_WIDTH-1:0] cm_rsp_head , // i, `CEU_CM_HEAD_WIDTH + output wire cm_rsp_ready, // o, 1 + /* -------Context Management Interface{end}------- */ + + /* -------CMD Information{begin}------- */ + input wire has_inbox , + input wire [11:0] op , + input wire [63:0] in_param , + input wire [31:0] in_modifier, + input wire [63:0] outbox_addr , + /* -------CMD Information{end}------- */ + + input wire start , + output wire finish + +`ifdef CEU_DBG_LOGIC + ,output wire [`ACC_CM_DBG_WIDTH-1:0] dbg_bus // o, `ACC_CM_DBG_WIDTH; +`endif +); +/* -------Decode & Head generation{begin}-------- */ +/*************************head********************************* +与上下文管理模块通信, 请求, 含payload: +Write Context Management request head (CMD_MAP_ICM), with payload +|--------| --------------------64bit----------------------- | +| 127: | type | opcode | R | chunk_num | +| 64 | (MAP_ICM_CTX) | (MAP_ICM_EN) | void | (32bit) | +|--------|--------------------------------------------------| +| 63: | R | +| 0 | void | +|--------|--------------------------------------------------| + +Write Context Management request head (CMD_SW2HW_CQ), with payload +|--------|----------------------64bit-----------------------| +| 127: | type | opcode | R | CQ_num | +| 64 | (WR_CQ_CTX) | (WR_CQ_ALL) | void | (32bit) | +|--------|--------------------------------------------------| +| 63: | R | +| 0 | void | +|--------|--------------------------------------------------| + +Write Context Management request head (CMD_RESIZE_CQ), with payload +|--------| --------------------64bit---------------------- | +| 127: | type | opcode | R | CQ_num | +| 64 | (WR_CQ_CTX) | (WR_CQ_MODIFY) | void | (32bit) | +|--------|-------------------------------------------------| +| 63: | R | +| 0 | void | +|--------|-------------------------------------------------| + +Write Context Management request head (CMD_SW2HW_EQ), with payload +|--------|----------------------64bit-----------------------| +| 127: | type | opcode | R | EQ_num | +| 64 | (WR_EQ_CTX) | (WR_EQ_ALL) | void | (32bit) | +|--------|--------------------------------------------------| +| 63: | R | +| 0 | void | +|--------|--------------------------------------------------| + +Communicate with CM module, request, without payload: + +Write Context Management request head (CMD_UNMAP_ICM), without payload +|--------| -------------------64bit----------------------- | +| 127: | type | opcode | R | page_cnt | +| 64 | (MAP_ICM_CTX) | (MAP_ICM_DIS) | void | (32bit) | +|--------|-------------------------------------------------| +| 63: | virt | +| 0 | (64bit) | +|--------|-------------------------------------------------| + +Read Context Management request head (CMD_QUERY_QP), without payload +|--------|----------------------64bit-----------------------| +| 127: | type | opcode | R | QP_num | +| 64 | (RD_QP_CTX) | (RD_QP_ALL) | void | (32bit) | +|--------|--------------------------------------------------| +| 63: | R | +| 0 | void | +|--------|--------------------------------------------------| + +Write Context Management request head (CMD_HW2SW_CQ), without payload +|--------|----------------------64bit-----------------------| +| 127: | type | opcode | R | CQ_num | +| 64 | (WR_CQ_CTX) |(WR_CQ_INVALID)| void | (32bit) | +|--------|--------------------------------------------------| +| 63: | R | +| 0 | void | +|--------|--------------------------------------------------| + +Write Context Managment request head (CMD_HW2SW_EQ), without payload +|--------|----------------------64bit-----------------------| +| 127: | type | opcode | R | EQ_num | +| 64 | (WR_EQ_CTX) |(WR_EQ_INVALID) | void | (32bit) | +|--------|--------------------------------------------------| +| 63: | R | +| 0 | void | +|--------|--------------------------------------------------| + +Write Context Management request head (CMD_MAP_EQ), without payload +|--------| --------------------64bit---------------------- | +| 127: | type | opcode | R | EQ_num | +| 64 | (WR_EQ_CTX) | (WR_EQ_FUNC) | void | (32bit) | +|--------|-------------------------------------------------| +| 63: | event_mask | +| 0 | (64bit) | +|--------|-------------------------------------------------| + +Communicate with CM, request, with/without payload: + +Write Context Management request head (CMD_MODIFY_QP), with/without payload +|--------|----------------------64bit-----------------------| +| 127: | type | opcode | R | QP_num | +| 64 | (WR_QP_CTX) | (WR_QP_ALL) | void | (32bit) | +|--------|--------------------------------------------------| +| 63: | R | +| 0 | void | +|--------|--------------------------------------------------| + +Communicate with CM module, response, with payload: + +Read Context Management response head (CMD_QUERY_QP), with payload +|--------|----------------------64bit-----------------------| +| 127: | type | opcode | R | QP_num | +| 64 | (RD_QP_CTX) | (RD_QP_ALL) | void | (32bit) | +|--------|--------------------------------------------------| +| 63: | R | +| 0 | void | +|--------|--------------------------------------------------| + +Communicate with DMA, write request, with payload: + +dma write outbox req head, with payload (only for CMD_QUERY_QP) +|--------| --------------------64bit---------------------- | +| 127: | R | outbox_addr | +| 64 | (63:32) | (63:32 bit) | +|--------|-------------------------------------------------| +| 63: | outbox_addr | R | outbox_len | +| 0 | (31: 0 bit) | (31:12) | (11:0 bit) | +|--------|-------------------------------------------------| +*****************************************************************/ +wire is_sw2hw_cq, is_resize_cq, is_sw2hw_eq, is_map_eq, is_modify_qp, is_hw2sw_cq, is_hw2sw_eq, is_query_qp; +wire is_map_icm, is_unmap_icm; + + +wire rd_cmd; +// wire wr_cmd; + + +wire [`AXIS_TYPE_WIDTH-1:0] typ; // modified by mazhenlong +wire [`AXIS_OPCODE_WIDTH-1:0] opcode; + +// -------CM req head------- +// EQ_num --> in_modifier; +// CQ_num --> in_modifier; +// QP_num --> in_modifier; +// page_cnt --> in_modifier; +// chunk_num --> in_modifier; +// event_mask--> in_param; +// virt --> in_param; +wire has_cm_head_low; +reg [63:0] cm_head_high; +reg [63:0] cm_head_low; + + + +// -------dma wr req head------- +reg [11:0] outbox_len; +/* -------Decode & Head generation{end}-------- */ + +/* ------- FSM relevant{begin}------- */ +localparam IDLE = 4'b0001, // Wait for start and inbox coming (if needed) + INBOX_CM_REQ = 4'b0010, // Forward last beat of inbox to CM request Interface + BARE_CM_REQ = 4'b0100, // Forward (Read/Write) request to CM request Interface + WR_OUTBOX = 4'b1000; // Wait for dma write request end + +reg [3:0] cur_state; +reg [3:0] nxt_state; + +wire is_idle, is_inbox_cm_req, is_bare_cm_req, is_wr_outbox; +wire j_inbox_cm_req, j_bare_cm_req; +/* ------- FSM relevant{end}------- */ + + +/* --------------------------------------------------------------------------------------------------- */ + +/* -------Decode & Head generation{begin}-------- */ +assign is_sw2hw_cq = (op == `CMD_SW2HW_CQ ); +assign is_resize_cq = (op == `CMD_RESIZE_CQ); +assign is_sw2hw_eq = (op == `CMD_SW2HW_EQ ); +assign is_map_eq = (op == `CMD_MAP_EQ ); +assign is_hw2sw_cq = (op == `CMD_HW2SW_CQ ); +assign is_hw2sw_eq = (op == `CMD_HW2SW_EQ ); +assign is_query_qp = (op == `CMD_QUERY_QP ); +assign is_modify_qp = `IS_MODIFY_QP(op); +assign is_map_icm = (op == `CMD_MAP_ICM ); +assign is_unmap_icm = (op == `CMD_UNMAP_ICM); + +assign rd_cmd = is_query_qp; +// assign wr_cmd = is_unmap_icm | is_map_icm | is_modify_qp | is_hw2sw_eq | is_hw2sw_cq | +// is_map_eq | is_sw2hw_eq | is_resize_cq | is_sw2hw_cq; + + +assign typ = ({`AXIS_TYPE_WIDTH{is_map_icm }} & `MAP_ICM_CTX) | // modified by mazhenlong + ({`AXIS_TYPE_WIDTH{is_unmap_icm}} & `MAP_ICM_CTX) | + ({`AXIS_TYPE_WIDTH{is_query_qp }} & `RD_QP_CTX ) | + ({`AXIS_TYPE_WIDTH{is_modify_qp}} & `WR_QP_CTX ) | + ({`AXIS_TYPE_WIDTH{is_sw2hw_cq }} & `WR_CQ_CTX ) | + ({`AXIS_TYPE_WIDTH{is_hw2sw_cq }} & `WR_CQ_CTX ) | + ({`AXIS_TYPE_WIDTH{is_resize_cq}} & `WR_CQ_CTX ) | + ({`AXIS_TYPE_WIDTH{is_sw2hw_eq }} & `WR_EQ_CTX ) | + ({`AXIS_TYPE_WIDTH{is_hw2sw_eq }} & `WR_EQ_CTX ) | + ({`AXIS_TYPE_WIDTH{is_map_eq }} & `WR_EQ_CTX ); + +assign opcode = ({`AXIS_OPCODE_WIDTH{is_map_icm }} & `WR_ICMMAP_EN ) | + ({`AXIS_OPCODE_WIDTH{is_unmap_icm}} & `WR_ICMMAP_DIS) | + ({`AXIS_OPCODE_WIDTH{is_query_qp }} & `RD_QP_ALL ) | + ({`AXIS_OPCODE_WIDTH{is_modify_qp & has_inbox }} & `WR_QP_ALL ) | + ({`AXIS_OPCODE_WIDTH{is_modify_qp & (!has_inbox)}} & `WR_QP_INVALID) | + ({`AXIS_OPCODE_WIDTH{is_sw2hw_cq }} & `WR_CQ_ALL ) | + ({`AXIS_OPCODE_WIDTH{is_hw2sw_cq }} & `WR_CQ_INVALID) | + ({`AXIS_OPCODE_WIDTH{is_resize_cq}} & `WR_CQ_MODIFY ) | + ({`AXIS_OPCODE_WIDTH{is_sw2hw_eq }} & `WR_EQ_ALL ) | + ({`AXIS_OPCODE_WIDTH{is_hw2sw_eq }} & `WR_EQ_INVALID) | + ({`AXIS_OPCODE_WIDTH{is_map_eq }} & `WR_EQ_FUNC ); + +assign has_cm_head_low = is_map_eq | is_unmap_icm; +always @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + cm_head_high <= `TD 0; + end + else if (j_inbox_cm_req | j_bare_cm_req) begin + cm_head_high <= `TD {typ, opcode, {32-`AXIS_TYPE_WIDTH-`AXIS_OPCODE_WIDTH{1'b0}}, in_modifier}; + end +end +always @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + cm_head_low <= `TD 0; + end + else if (has_cm_head_low) begin + cm_head_low <= `TD in_param; + end + else begin + cm_head_low <= `TD 0; + end +end +always @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + outbox_len <= `TD 0; + end + else if (is_query_qp) begin + outbox_len <= `TD `OUTBOX_LEN_QUERY_QP; + end + else begin + outbox_len <= `TD 0; + end +end +/* -------Decode & Head generation{end}-------- */ + + +//------------------------------{Access Context Management FSM}begin------------------------------// +/******************** Stage 1: State Register **********************/ +always @(posedge clk, negedge rst_n) begin + if(~rst_n) + cur_state <= `TD IDLE; + else + cur_state <= `TD nxt_state; +end + +/******************** Stage 2: State Transition **********************/ + +assign is_idle = (cur_state == IDLE ); +assign is_inbox_cm_req = (cur_state == INBOX_CM_REQ); +assign is_bare_cm_req = (cur_state == BARE_CM_REQ ); +assign is_wr_outbox = (cur_state == WR_OUTBOX ); + +assign j_inbox_cm_req = is_idle & start & has_inbox & dma_rd_rsp_valid; +assign j_bare_cm_req = is_idle & start & (!has_inbox); + +always @(*) begin + case(cur_state) + IDLE: begin + if (start & has_inbox & dma_rd_rsp_valid) begin + nxt_state = INBOX_CM_REQ; + end + else if (start & (!has_inbox)) begin + nxt_state = BARE_CM_REQ; + end + else begin + nxt_state = IDLE; + end + end + INBOX_CM_REQ: begin + if (cm_req_valid & cm_req_ready & cm_req_last) begin // cm write req data end + nxt_state = IDLE; + end + else begin + nxt_state = INBOX_CM_REQ; + end + end + BARE_CM_REQ: begin + if (cm_req_valid & cm_req_ready) begin + nxt_state = rd_cmd ? WR_OUTBOX : IDLE; + end + else begin + nxt_state = BARE_CM_REQ; + end + end + WR_OUTBOX: begin + if (dma_wr_req_valid & dma_wr_req_ready & dma_wr_req_last) begin // dma write request data end + nxt_state = IDLE; + end + else begin + nxt_state = WR_OUTBOX; + end + end + default: begin + nxt_state = IDLE; + end + endcase +end +/******************** Stage 3: Output **********************/ + + +/* ***** output ***** */ +// DMA Read Response +assign dma_rd_rsp_ready = is_inbox_cm_req ? cm_req_ready : 0; + +// DMA Write Request +assign dma_wr_req_valid = is_wr_outbox ? cm_rsp_valid : 0; +assign dma_wr_req_head = is_wr_outbox ? {32'd0, outbox_addr, 20'd0, outbox_len} : 0; +assign dma_wr_req_data = is_wr_outbox ? cm_rsp_data : 0; +assign dma_wr_req_last = is_wr_outbox ? cm_rsp_last : 0; + +// Context Management Request +assign cm_req_valid = (is_inbox_cm_req & dma_rd_rsp_valid) | + is_bare_cm_req; +assign cm_req_head = {cm_head_high, cm_head_low}; +assign cm_req_data = ({256{(is_inbox_cm_req & dma_rd_rsp_valid)}} & dma_rd_rsp_data); +assign cm_req_last = {is_inbox_cm_req & dma_rd_rsp_valid} & dma_rd_rsp_last | + is_bare_cm_req; + +// Context Management Response +assign cm_rsp_ready = is_wr_outbox ? dma_wr_req_ready : 0; + + +// finish +assign finish = (is_wr_outbox & dma_wr_req_valid & dma_wr_req_ready & dma_wr_req_last) | + (is_bare_cm_req & cm_req_valid & cm_req_ready & (!rd_cmd) ) | + (is_inbox_cm_req & cm_req_valid & cm_req_ready & cm_req_last ); +/* ***** output ***** */ +//------------------------------{Access Context Management FSM}end------------------------------// + + +`ifdef CEU_DBG_LOGIC +/* --------DBG signal{begin}-------- */ +assign dbg_bus = {cm_head_high, cm_head_low, outbox_len, cur_state, nxt_state}; +/* --------DBG signal{end}-------- */ +`endif +endmodule diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/CEU/acc_local.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/CEU/acc_local.v new file mode 100644 index 0000000000000000000000000000000000000000..3dc16608e1d9b5b0a10da9e2e0f56846d07da907 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/CEU/acc_local.v @@ -0,0 +1,309 @@ +`timescale 1ns / 100ps +//************************************************************************* +// > File Name : acc_local.v +// > Description: CEU_ACC_LOACL, used to parse command for CEU, the command incudes: +// > inbox: N, outbox: Y: +// > CMD_QUERY_DEV_LIM, +// > CMD_QUERY_ADAPTER +// > Author: Corning +// > Date : 2020-07-14 +//************************************************************************* + +`include "ceu_def_h.vh" +`include "protocol_engine_def.vh" + +module acc_local #( + parameter DMA_HEAD_WIDTH = 128 // DMA Stream *_head width +) ( + input wire clk, + input wire rst_n, + + + /* -------DMA Interface{begin}------- */ + /* dma_*_head(interact with RDMA modules), valid only in first beat of a packet + * | Reserved | address | Reserved | Byte length | + * | 127:96 | 95:32 | 31:13 | 12:0 | + */ + // DMA read response + // input wire dma_rd_rsp_valid, // i, 1 + // input wire dma_rd_rsp_last , // i, 1 + // input wire [`CEU_DATA_WIDTH-1 :0] dma_rd_rsp_data , // i, `CEU_DATA_WIDTH + // input wire [DMA_HEAD_WIDTH-1:0] dma_rd_rsp_head , // i, DMA_HEAD_WIDTH + // output wire dma_rd_rsp_ready, // o, 1 + + // DMA write req + output wire dma_wr_req_valid, // o, 1 + output wire dma_wr_req_last , // o, 1 + output wire [`CEU_DATA_WIDTH-1:0] dma_wr_req_data , // o, `CEU_DATA_WIDTH + output wire [DMA_HEAD_WIDTH -1:0] dma_wr_req_head , // o, DMA_HEAD_WIDTH + input wire dma_wr_req_ready, // i, 1 + /* -------DMA Interface{end}------- */ + + /* -------CMD Information{begin}------- */ + input wire [11:0] op , + input wire [63:0] outbox_addr, + input wire [7 :0] op_modifier, + output wire is_bad_nvmem, // indicate if firmware is ready, 1 means not ready. + /* -------CMD Information{end}------- */ + + + + input wire start , + output wire finish + +`ifdef CEU_DBG_LOGIC + /* -------APB reated signal{begin}------- */ + ,input wire [`ACC_LOCAL_RW_WIDTH -1:0] rw_data // i, `ACC_LOCAL_RW_WIDTH; read-writer register interface + ,output wire [`ACC_LOCAL_RW_WIDTH -1:0] rw_init_data // o, `ACC_LOCAL_RW_WIDTH + ,output wire [`ACC_LOCAL_DBG_WIDTH-1:0] dbg_bus // o, `ACC_LOCAL_DBG_WIDTH; debug bus data + /* -------APB reated signal{end}------- */ +`endif +); + +/* -------Store NIC Information{begin}------- */ +reg [`CEU_DATA_WIDTH-1:0] dev_lim_info[1:0]; +reg [`CEU_DATA_WIDTH-1:0] adapter_info; +reg [`CEU_DATA_WIDTH-1:0] mad_port_info; + +always @(posedge clk or negedge rst_n) begin + if(~rst_n) begin + dev_lim_info[0] <= `TD 0; + dev_lim_info[1] <= `TD 0; + adapter_info <= `TD 0; + mad_port_info <= `TD 0; + end +`ifdef CEU_DBG_LOGIC + else if (rw_data[`ACC_LOCAL_RW_WIDTH-1]) begin + {dev_lim_info[1], dev_lim_info[0], adapter_info, mad_port_info} <= `TD rw_data[`ACC_LOCAL_RW_WIDTH-2:0]; + end +`else + else begin + dev_lim_info[0] <= `TD { + `RESVED_QPS, `RESVED_CQS, `RESVED_EQS, `RESVED_MTTS, + 8'd0, `RESVED_PDS, 8'd0, `RESVED_LKEYS, + `MAX_QP_SZ, `MAX_CQ_SZ, + `MAX_QPS, `MAX_CQS, `MAX_EQS, `MAX_MPTS, + `MAX_PDS, 8'd0, `MAX_GIDS, `MAX_PKEYS, + 8'd0, `MAX_MTT_SEG, 16'd0, + `QPC_ENTRY_SZ, `CQC_ENTRY_SZ, + `EQC_ENTRY_SZ, `MPT_ENTRY_SZ + }; + dev_lim_info[1] <= `TD { + 4'd0, `ACK_DELAY, `MAX_MTU, `MAX_PORT_WIDTH, 8'd0, `MAX_VL, `NUM_PORTS, + 8'd0, `MIN_PAGE_SZ, 16'd0, + 8'd0, `MAX_SG, `MAX_DESC_SZ, + 8'd0, `MAX_SG_RQ, `MAX_DESC_SZ_RQ, + `MAX_ICM_SZ, + 32'd0, + 32'd0 + }; + adapter_info <= `TD { + 32'd0, + 32'd0, + 32'd0, + 32'd0, + 32'd0, + 32'd0, + `BOARD_ID + }; + mad_port_info <= `TD { + 16'd1, 8'd2, 8'd3, // lid, state, phy_state + 32'd0, // GUID + 32'd0, // GUID + 32'd0, // GUID + 32'd0, // GUID + 32'd0, + 32'd0, + 32'd0 + }; + end +`endif +end +/* -------Store NIC Information{end}------- */ + + +/* -------decode & head generation{begin}------- */ +/*************************head************************************* +dma write outbox req head +|--------| --------------------64bit---------------------- | +| 127: | R | outbox_addr | +| 64 | (63:32) | (63:32 bit) | +|--------|-------------------------------------------------| +| 63: | outbox_addr | R | outbox_len | +| 0 | (31: 0 bit) | (31:12) | (11:0 bit) | +|--------|-------------------------------------------------| + *****************************************************************/ +// wire is_cmd_valid; +wire is_query_dev_lim, is_query_adapter, is_mad_ifc; + +wire [DMA_HEAD_WIDTH-1:0] head; +wire [11:0] outbox_len; // in bytes + +/* -------decode & head generation{end}------- */ + +/* ------- FSM relevant{begin}------- */ +localparam IDLE = 3'b001, // Wait for start signal comming + SEND_0 = 3'b010, // Send first beat of data & head + SEND_1 = 3'b100; // Send second beat of data (only for dev_lim cmd) + +reg [2:0] cur_state; +reg [2:0] nxt_state; + +wire is_idle, is_send_0, is_send_1; +/* ------- FSM relevant{end}------- */ + + +/* --------------------------------------------------------------------------------------------------- */ + + +/* ------- decode & head generation{begin}------ */ + +// assign is_cmd_valid = is_query_dev_lim | is_query_adapter; +assign is_query_dev_lim = (op == `CMD_QUERY_DEV_LIM ); +assign is_query_adapter = (op == `CMD_QUERY_ADAPTER ); +assign is_mad_ifc = (op == `CMD_MAD_IFC ); + +assign outbox_len = ({12{is_query_dev_lim}} & (`OUTBOX_LEN_QUERY_DEV_LIM)) | + ({12{is_query_adapter}} & (`OUTBOX_LEN_QUERY_ADAPTER)) | + ({12{is_mad_ifc }} & (`OUTBOX_LEN_ATTR_PORT_INFO)); + +assign head = {32'd0, outbox_addr, 20'd0, outbox_len}; +/* ------- decode & head generation{end}------ */ + +//------------------------------{acc_local FSM}begin------------------------------// +/******************** Stage 1: State Register **********************/ + +assign is_idle = (cur_state == IDLE ); +assign is_send_0 = (cur_state == SEND_0); +assign is_send_1 = (cur_state == SEND_1); + +always @(posedge clk or negedge rst_n) begin + if(~rst_n) + cur_state <= `TD IDLE; + else + cur_state <= `TD nxt_state; +end + +/******************** Stage 2: State Transition **********************/ + +always @(*) begin + case(cur_state) + IDLE: begin + if (start) begin + nxt_state = SEND_0; + end + else begin + nxt_state = IDLE; + end + end + SEND_0: begin + if (dma_wr_req_valid & dma_wr_req_ready) begin + nxt_state = ({3{is_query_adapter}} & IDLE ) | + ({3{is_mad_ifc }} & IDLE ) | + ({3{is_query_dev_lim}} & SEND_1); + end + else begin + nxt_state = SEND_0; + end + end + SEND_1: begin + if (dma_wr_req_valid & dma_wr_req_ready) begin + nxt_state = IDLE; + end + else begin + nxt_state = SEND_1; + end + end + default: begin + nxt_state = IDLE; + end + endcase +end + +/******************** Stage 3: Output **********************/ + +/* -------output------- */ +assign dma_wr_req_valid = is_send_0 | is_send_1; +assign dma_wr_req_last = (is_query_adapter & is_send_0) | + (is_mad_ifc & is_send_0) | + (is_query_dev_lim & is_send_1); +assign dma_wr_req_data = ({`CEU_DATA_WIDTH{is_query_adapter & is_send_0}} & adapter_info ) | + ({`CEU_DATA_WIDTH{is_mad_ifc & is_send_0}} & mad_port_info) | + ({`CEU_DATA_WIDTH{is_query_dev_lim & is_send_0}} & dev_lim_info[0]) | + ({`CEU_DATA_WIDTH{is_query_dev_lim & is_send_1}} & dev_lim_info[1]); +assign dma_wr_req_head = (is_send_0 | is_send_1) ? head : {DMA_HEAD_WIDTH{1'd0}}; + + + +// status +assign is_bad_nvmem = 1'd0; + +// finish +assign finish = dma_wr_req_valid & dma_wr_req_ready & dma_wr_req_last; +/* ***** output ***** */ +//------------------------------{get_inbox FSM}end------------------------------// + +`ifdef CEU_DBG_LOGIC +/* --------DBG signal{begin}-------- */ +wire [`CEU_DATA_WIDTH-1:0] init_dev_lim_info_w0; +wire [`CEU_DATA_WIDTH-1:0] init_dev_lim_info_w1; +wire [`CEU_DATA_WIDTH-1:0] init_adapter_info_w ; +wire [`CEU_DATA_WIDTH-1:0] init_mad_port_info_w; + +assign init_dev_lim_info_w0 = { + `RESVED_QPS, `RESVED_CQS, `RESVED_EQS, `RESVED_MTTS, + 8'd0, `RESVED_PDS, 8'd0, `RESVED_LKEYS, + `MAX_QP_SZ, `MAX_CQ_SZ, + `MAX_QPS, `MAX_CQS, `MAX_EQS, `MAX_MPTS, + `MAX_PDS, 8'd0, `MAX_GIDS, `MAX_PKEYS, + 8'd0, `MAX_MTT_SEG, 16'd0, + `QPC_ENTRY_SZ, `CQC_ENTRY_SZ, + `EQC_ENTRY_SZ, `MPT_ENTRY_SZ +}; +assign init_dev_lim_info_w1 = { + 4'd0, `ACK_DELAY, `MAX_MTU, `MAX_PORT_WIDTH, 8'd0, `MAX_VL, `NUM_PORTS, + 8'd0, `MIN_PAGE_SZ, 16'd0, + 8'd0, `MAX_SG, `MAX_DESC_SZ, + 8'd0, `MAX_SG_RQ, `MAX_DESC_SZ_RQ, + `MAX_ICM_SZ, + 32'd0, + 32'd0 +}; +assign init_adapter_info_w = { + 32'd0, + 32'd0, + 32'd0, + 32'd0, + 32'd0, + 32'd0, + `BOARD_ID +}; +assign init_mad_port_info_w = { + 16'd1, 8'd2, 8'd3, // lid, state, phy_state + 32'd0, // GUID + 32'd0, // GUID + 32'd0, // GUID + 32'd0, // GUID + 32'd0, + 32'd0, + 32'd0 +}; +assign rw_init_data = { + 1'd1, // control signal + init_dev_lim_info_w1, + init_dev_lim_info_w0, + init_adapter_info_w , + init_mad_port_info_w +}; + +assign dbg_bus = { + dev_lim_info[1], + dev_lim_info[0], + adapter_info , + mad_port_info , + cur_state , + nxt_state +}; +/* --------DBG signal{end}-------- */ +`endif +endmodule diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/CEU/wr_both.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/CEU/wr_both.v new file mode 100644 index 0000000000000000000000000000000000000000..c36a2e34b714df9f0c02b1b0455b6e125e0414bf --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/CEU/wr_both.v @@ -0,0 +1,345 @@ +`timescale 1ns / 100ps +//************************************************************************* +// > File Name : wr_both.v +// > Description: CEU_WR_BOTH, used to pass comand to both Context Management +// > module and Virtual to Physical module. The command includes: +// > inbox: Y, outbox: N: +// > CMD_INIT_HCA +// > inbox: N, outbox: N: +// > CMD_CLOSE_HCA +// > Author : Corning +// > Date : 2020-07-09 +//************************************************************************* + +`include "ceu_def_h.vh" +`include "protocol_engine_def.vh" + +module wr_both #( + parameter DMA_HEAD_WIDTH = 128 // DMA Stream *_head width +) ( + input clk , + input rst_n, + + + /* -------DMA Interface{begin}------- */ + /* dma_*_head(interact with RDMA modules), valid only in first beat of a packet + * | Reserved | address | Reserved | Byte length | + * | 127:96 | 95:32 | 31:13 | 12:0 | + */ + // DMA read response + input wire dma_rd_rsp_valid, // i, 1 + // input wire dma_rd_rsp_last , // i, 1 + input wire [`CEU_DATA_WIDTH-1 :0] dma_rd_rsp_data , // i, `CEU_DATA_WIDTH + // input wire [DMA_HEAD_WIDTH-1:0] dma_rd_rsp_head , // i, DMA_HEAD_WIDTH + output wire dma_rd_rsp_ready, // o, 1 + /* -------DMA Interface{end}------- */ + + /* -------Virtual-to-physial Interface{begin}------- */ + // VirtToPhys write req + output wire v2p_req_valid, // o, 1 + output wire v2p_req_last , // o, 1 + output wire [`CEU_DATA_WIDTH -1:0] v2p_req_data , // o, `CEU_DATA_WIDTH + output wire [`CEU_V2P_HEAD_WIDTH-1:0] v2p_req_head , // o, CEU_V2P_HEAD_WIDTH + input wire v2p_req_ready, // i, 1 + /* -------Virtual-to-physial Interface{end}------- */ + + /* -------Context Management Interface{begin}------- */ + // CtxMgt req + output wire cm_req_valid, // o, 1 + output wire cm_req_last , // o, 1 + output wire [`CEU_DATA_WIDTH -1:0] cm_req_data , // o, `CEU_DATA_WIDTH + output wire [`CEU_CM_HEAD_WIDTH-1:0] cm_req_head , // o, CEU_CM_HEAD_WIDTH + input wire cm_req_ready, // i, 1 + /* -------Context Management Interface{end}------- */ + + /* -------CMD Information{begin}------- */ + input wire [11:0] op, + /* -------CMD Information{end}------- */ + + // module ctrl + input wire start, + output wire finish + +`ifdef CEU_DBG_LOGIC + ,output wire [`WR_BOTH_DBG_WIDTH-1:0] dbg_bus // o, `WR_BOTH_DBG_WIDTH; +`endif +); +/* -------Decode & Head generation{begin}-------- */ +/*************************Head & Data************************************ + +Write Context Management request head (CMD_INIT_HCA), with payload +|--------| --------------------64bit---------------------- | +| 127: | type | opcode | R | +| 64 | (WR_ICMMAP_CTX) | (WR_ICMMAP_EN) | (void) | +|--------|-------------------------------------------------| +| 63: | R | +| 0 | (void) | +|--------|-------------------------------------------------| + +Write Context Management request Data (CMD_INIT_HCA), only one beat +|--------| --------------------64bit---------------------- |------| +| 255: | R | 1Ch- | +| 192 | (void) | 18h | +|--------|-------------------------------------------------|------| +| 191: | eqc_base | log_num_eqs | 14h- | +| 128 | (63:8) | (7:0) | 10h | +|--------|-------------------------------------------------|------| +| 127: | cqc_base | log_num_cqs | 0Ch- | +| 64 | (63:8) | (7:0) | 08h | +|--------|-------------------------------------------------|------| +| 63: | qpc_base | log_num_qps | 04h- | +| 0 | (63:8) | (7:0) | 00h | +|--------|-------------------------------------------------|------| + + +Write Virtual-to-physical Request Head (CMD_INIT_HCA), with payload +|--------| --------------------64bit---------------------- | +| 127: | type | opcode | R | +| 64 | (WR_ICMMAP_TPT) | (WR_ICMMAP_EN) | (void) | +|--------|-------------------------------------------------| +| 63: | R | +| 0 | (void) | +|--------|-------------------------------------------------| + +Write Virtual-to-physical Request Data (CMD_INIT_HCA), only one beat +|--------|---------------------64bit-----------------------| +| 255: | R | +| 192 | (void) | +|--------|-------------------------------------------------| +| 191: | R | +| 128 | (void) | +|--------|-------------------------------------------------| +| 127: | mpt_base | log_mpt_sz | +| 64 | (63:8) | (7:0) | +|--------|-------------------------------------------------| +| 63: | mtt_base | +| 0 | (63:0) | +|--------|-------------------------------------------------| + +Write Virtual-to-physical & Context Management Request Head (CMD_CLOSE_HCA), without payload +|--------| --------------------64bit---------------------- | +| 127: | type | opcode | R | +| 64 | | (WR_ICMMAP_DIS) | (void) | +|--------|-------------------------------------------------| +| 63: | R | +| 0 | (void) | +|--------|-------------------------------------------------| + +DMA读响应通道: data signal(two beats in total) +First beat +|--------| --------------------64bit---------------------- |------| +| 255: | R | 1Ch- | +| 192 | (void) | 18h | +|--------|-------------------------------------------------|------| +| 191: | qpc_base | log_num_qps | 14h- | +| 128 | (63:8) | (7:0) | 10h | +|--------|-------------------------------------------------|------| +| 127: | cqc_base | log_num_cqs | 0Ch- | +| 64 | (63:8) | (7:0) | 08h | +|--------|-------------------------------------------------|------| +| 63: | eqc_base | log_num_eqs | 04h- | +| 0 | (63:8) | (7:0) | 00h | +|--------|-------------------------------------------------|------| + +Second beat +|--------|---------------------64bit-----------------------|------| +| 255: | R | 3Ch- | +| 192 | (void) | 38h | +|--------|-------------------------------------------------|------| +| 191: | R | 34h- | +| 128 | (void) | 30h | +|--------|-------------------------------------------------|------| +| 127: | mpt_base | log_mpt_sz | 2Ch- | +| 64 | (63:8) | (7:0) | 28h | +|--------|-------------------------------------------------|------| +| 63: | mtt_base | 24h- | +| 0 | (63:0) | 20h | +|--------|-------------------------------------------------|------| +******************************************************************/ + +wire is_init_hca, is_close_hca; + +// wire has_payload; // if the cmd has payload + + +// Context Management & Virtual to physical Write Request head +wire [`AXIS_TYPE_WIDTH-1:0] cm_type; +wire [`AXIS_TYPE_WIDTH-1:0] v2p_type; +wire [`AXIS_OPCODE_WIDTH-1:0] opcode; +reg [`CEU_CM_HEAD_WIDTH-1 :0] cm_head; +reg [`CEU_V2P_HEAD_WIDTH-1:0] v2p_head; + +/* -------Decode & Head generation{end}-------- */ + +/* -------FSM relevant{begin}------- */ +localparam IDLE = 4'b0001, // Wait until start asserted. + INBOX_CM_REQ = 4'b0010, // Forward first beat of DMA response to CM + INBOX_V2P_REQ = 4'b0100, // Forward second beat of DMA response to V2P + BARE_CM_V2P = 4'b1000; // Forward Head of non-payload Write Request to CM & V2P +reg [3:0] cur_state; +reg [3:0] nxt_state; + +wire is_idle, is_inbox_cm_req, is_inbox_v2p_req, is_bare_cm_v2p; + + +// In BARE_CM_V2P, these signals indicate that CM/V2P write request has finished. +reg cm_head_end; +reg v2p_head_end; + +/* -------FSM relevant{end}------- */ + +/* --------------------------------------------------------------------------------------------------- */ + +/* -------Decode & Head generation{begin}-------- */ +assign is_init_hca = (op == `CMD_INIT_HCA) ; +assign is_close_hca = (op == `CMD_CLOSE_HCA); + + +// assign has_payload = is_init_hca; + +assign cm_type = `WR_ICMMAP_CTX; +assign v2p_type = `WR_ICMMAP_TPT; +assign opcode = ({`AXIS_TYPE_WIDTH{is_init_hca }} & `WR_ICMMAP_EN ) | + ({`AXIS_TYPE_WIDTH{is_close_hca}} & `WR_ICMMAP_DIS); + +// Write Request Head +always @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + cm_head <= `TD 0; + v2p_head <= `TD 0; + end + // else if () begin + // cm_head <= `TD 0; + // v2p_head <= `TD 0; + // end + else if (start) begin + cm_head <= `TD {cm_type, opcode, {64-`AXIS_TYPE_WIDTH-`AXIS_OPCODE_WIDTH{1'b0}}, 64'b0}; + v2p_head <= `TD {v2p_type, opcode, {64-`AXIS_TYPE_WIDTH-`AXIS_OPCODE_WIDTH{1'b0}}, 64'b0}; + end +end +/* -------Decode & Head generation{end}-------- */ + +//------------------------------{Write both FSM}begin------------------------------// + + +/******************** Stage 1: State Register **********************/ +always @(posedge clk, negedge rst_n) begin + if(~rst_n) + cur_state <= `TD IDLE; + else + cur_state <= `TD nxt_state; +end + +/******************** Stage 2: State Transition **********************/ + +always @(*) begin + case(cur_state) + IDLE: begin + if (start & is_init_hca) begin // start write Request with payload to CM + nxt_state = INBOX_CM_REQ; + end + else if (start & is_close_hca) begin // start write Request without payload to CM & V2P + nxt_state = BARE_CM_V2P; + end + else begin + nxt_state = IDLE; + end + end + INBOX_CM_REQ: begin + if (cm_req_valid & cm_req_ready) begin // cm write req data end + nxt_state = INBOX_V2P_REQ; + end + else begin + nxt_state = INBOX_CM_REQ; + end + end + INBOX_V2P_REQ: begin + if (v2p_req_valid & v2p_req_ready) begin // v2p write req data end + nxt_state = IDLE; + end + else begin + nxt_state = INBOX_V2P_REQ; + end + end + BARE_CM_V2P: begin + if ((cm_head_end | cm_req_ready) & (v2p_head_end | v2p_req_ready)) begin // cm & v2p write request end + nxt_state = IDLE; + end + else begin + nxt_state = BARE_CM_V2P; + end + end + default: begin + nxt_state = IDLE; + end + endcase +end +/******************** Stage 3: Output **********************/ + +assign is_idle = (cur_state == IDLE ); +assign is_inbox_cm_req = (cur_state == INBOX_CM_REQ ); +assign is_inbox_v2p_req = (cur_state == INBOX_V2P_REQ); +assign is_bare_cm_v2p = (cur_state == BARE_CM_V2P ); + + + +always @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + cm_head_end <= `TD 0; + v2p_head_end <= `TD 0; + end + else if (is_idle) begin + cm_head_end <= `TD 0; + v2p_head_end <= `TD 0; + end + else if (is_bare_cm_v2p & cm_req_ready & !v2p_req_ready) begin + cm_head_end <= `TD 1; + end + else if (is_bare_cm_v2p & !cm_req_ready & v2p_req_ready) begin + v2p_head_end <= `TD 1; + end +end + + +/* ***** output ***** */ + +// Context Management write req +assign cm_req_valid = (is_bare_cm_v2p & !cm_head_end) | + (is_inbox_cm_req & dma_rd_rsp_valid); +assign cm_req_last = cm_req_valid; +assign cm_req_head = cm_req_valid ? cm_head : 0; +assign cm_req_data = (cm_req_valid & dma_rd_rsp_valid) ? dma_rd_rsp_data : 0; + +// Virtual to Physical write req +assign v2p_req_valid = (is_bare_cm_v2p & !v2p_head_end) | + (is_inbox_v2p_req & dma_rd_rsp_valid); +assign v2p_req_last = v2p_req_valid; +assign v2p_req_head = v2p_req_valid ? v2p_head : 0; +assign v2p_req_data = (v2p_req_valid & dma_rd_rsp_valid) ? dma_rd_rsp_data : 0; + + + +// dma read response +assign dma_rd_rsp_ready = (is_inbox_cm_req & cm_req_ready) | + (is_inbox_v2p_req & v2p_req_ready); + +// finish +assign finish = (is_bare_cm_v2p & (cm_head_end | cm_req_ready) & (v2p_head_end | v2p_req_ready)) | + (is_inbox_v2p_req & v2p_req_valid & v2p_req_ready); +/* ***** for output ***** */ +//------------------------------{Write Both FSM}end------------------------------// + +`ifdef CEU_DBG_LOGIC +/* --------DBG signal{begin}-------- */ +assign dbg_bus = {cm_head_end, v2p_head_end, cur_state, nxt_state}; +/* --------DBG signal{end}-------- */ +`endif + +//ceu_ila_4 ceu_ila_4 ( +// .clk ( clk ), +// .probe0 (cur_state ), // i, 4 +// .probe1 (v2p_req_valid ), // i, 1 +// .probe2 (v2p_req_ready ) // i, 1 + +//); +endmodule diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/CEU/wr_v2p.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/CEU/wr_v2p.v new file mode 100644 index 0000000000000000000000000000000000000000..246fc73642dc96ee2ca1a74397c5e81d6cdc011d --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/CEU/wr_v2p.v @@ -0,0 +1,326 @@ +`timescale 1ns / 100ps +//************************************************************************* +// > File Name : wr_v2p.v +// > Description: CEU_WR_V2P, used to pass command to Virtual to Physical module. +// > The command includes: +// > inbox: Y, outbox: N: +// > CMD_MAP_ICM +// > CMD_SW2HW_MPT +// > CMD_WRITE_MTT +// > inbox: N, outbox: N: +// > CMD_UNMAP_ICM +// > CMD_HW2SW_MPT +// > Author : Corning +// > Date : 2020-07-09 +//************************************************************************* + + +`include "ceu_def_h.vh" +`include "protocol_engine_def.vh" + +module wr_v2p #( + parameter DMA_HEAD_WIDTH = 128 // DMA Stream *_head width + +) ( + input wire clk, + input wire rst_n, + + /* -------DMA Interface{begin}------- */ + /* dma_*_head(interact with RDMA modules), valid only in first beat of a packet + * | Reserved | address | Reserved | Byte length | + * | 127:96 | 95:32 | 31:13 | 12:0 | + */ + // DMA read response + input wire dma_rd_rsp_valid, // i, 1 + input wire dma_rd_rsp_last , // i, 1 + input wire [`CEU_DATA_WIDTH-1:0] dma_rd_rsp_data , // i, `CEU_DATA_WIDTH + input wire [DMA_HEAD_WIDTH -1:0] dma_rd_rsp_head , // i, DMA_HEAD_WIDTH + output wire dma_rd_rsp_ready, // o, 1 + /* -------DMA Interface{end}------- */ + + /* -------Virtual-to-physial Interface{begin}------- */ + // VirtToPhys write req + output wire v2p_req_valid, // o, 1 + output wire v2p_req_last , // o, 1 + output wire [`CEU_DATA_WIDTH -1:0] v2p_req_data , // o, `CEU_DATA_WIDTH + output wire [`CEU_V2P_HEAD_WIDTH-1:0] v2p_req_head , // o, CEU_V2P_HEAD_WIDTH + input wire v2p_req_ready, // i, 1 + /* -------Virtual-to-physial Interface{end}------- */ + + /* -------CMD Information{begin}------- */ + input wire has_inbox , + input wire [11:0] op , + input wire [63:0] in_param , + input wire [31:0] in_modifier, + /* -------CMD Information{end}------- */ + + // module ctrl + input wire start , + output wire finish + +`ifdef CEU_DBG_LOGIC + ,output wire [`WR_V2P_DBG_WIDTH-1:0] dbg_bus // o, `WR_V2P_DBG_WIDTH; +`endif +); +//------------------------{Decode & Packet generation}begin---------------------------// +/*************************head************************************ +与虚实地址转换模块通信, 请求, 含payload: +Write Context Management request head (CMD_MAP_ICM), with payload +|--------| --------------------64bit----------------------- | +| 127: | type | opcode | R | chunk_num | +| 64 | (MAP_ICM_TPT) | (MAP_ICM_EN) | void | (32bit) | +|--------|--------------------------------------------------| +| 63: | R | +| 0 | void | +|--------|--------------------------------------------------| + +Write Context Management request head (CMD_SW2HW_MPT), with payload +|--------|----------------------64bit-----------------------| +| 127: | type | opcode | R | mpt_index | +| 64 | (WR_MPT_TPT) | (WR_MPT_WRITE) | void | (32bit) | +|--------|--------------------------------------------------| +| 63: | R | +| 0 | void | +|--------|--------------------------------------------------| + +Write Context Management request head (CMD_WRITE_MTT), with payload +|--------| --------------------64bit---------------------- | +| 127: | type | opcode | R | mtt_num | +| 64 | (WR_MTT_TPT) | (WR_MTT_WRITE) | void | (32bit) | +|--------|-------------------------------------------------| +| 63: | mtt_start_index | +| 0 | (64bit) | +|--------|-------------------------------------------------| + +Write Context Management request data (CMD_WRITE_MTT), only one beat +|--------|-------------------64bit-------------------------| +| 255: | mtt_phy_addr[3] | +| 192 | (64bit) | +|--------|-------------------------------------------------| +| 191: | mtt_phy_addr[2] | +| 128 | (64bit) | +|--------|-------------------------------------------------| +| 127: | mtt_phy_addr[1] | +| 64 | (64bit) | +|--------|-------------------------------------------------| +| 63: | mtt_phy_addr[0] | +| 0 | (64bit) | +|--------|-------------------------------------------------| + + +与虚实地址转换模块通信, 请求, 无payload: +Write Context Management request head (CMD_UNMAP_ICM), without payload +|--------| -------------------64bit----------------------- | +| 127: | type | opcode | R | page_cnt | +| 64 | (MAP_ICM_TPT) | (MAP_ICM_DIS) | void | (32bit) | +|--------|-------------------------------------------------| +| 63: | virt | +| 0 | (64bit) | +|--------|-------------------------------------------------| + +Write Context Management request head (CMD_HW2SW_MPT), without payload +|--------|----------------------64bit-------------------------| +| 127: | type | opcode | R | mpt_index | + input wire [63:0] uar_db_data , + output wire uar_db_ready, + input wire uar_db_valid, +| 64 | (WR_MPT_TPT) | (WR_MPT_INVALID) | void | (32bit) | +|--------|----------------------------------------------------| +| 63: | R | +| 0 | void | +|--------|----------------------------------------------------| + + +与DMA读模块通信, 响应, 含payload: +DMA read response data (CMD_WRITE_MTT), first & second beat +// first beat +|--------|-------------------64bit-------------------------|------| +| 255: | R | 1Ch- | +| 192 | (64bit) | 18h | +|--------|-------------------------------------------------|------| +| 191: | R | 14h- | +| 128 | (64bit) | 10h | +|--------|-------------------------------------------------|------| +| 127: | R | 0Ch- | +| 64 | (64bit) | 08h | +|--------|-------------------------------------------------|------| +| 63: | mtt_start_index | 04h- | +| 0 | (64bit) | 00h | +|--------|-------------------------------------------------|------| +// second beat +|--------|-------------------64bit-------------------------|------| +| 255: | mtt_phy_addr[3] | 3Ch- | +| 192 | (64bit) | 38h | +|--------|-------------------------------------------------|------| +| 191: | mtt_phy_addr[2] | 34h- | +| 128 | (64bit) | 30h | +|--------|-------------------------------------------------|------| +| 127: | mtt_phy_addr[1] | 2Ch- | +| 64 | (64bit) | 28h | +|--------|-------------------------------------------------|------| +| 63: | mtt_phy_addr[0] | 24h- | +| 0 | (64bit) | 20h | +|--------|-------------------------------------------------|------| +*****************************************************************/ +wire is_sw2hw_mpt, is_write_mtt, is_hw2sw_mpt, is_map_icm, is_unmap_icm; +reg is_write_mtt_reg; + +wire [`AXIS_TYPE_WIDTH-1:0] typ; +wire [`AXIS_OPCODE_WIDTH-1:0] opcode; + + +// mpt_index -> in_modifier; +// mtt_num -> in_modifier; +// chunk_num -> in_modifier; +// page_cnt -> in_modifier; +// virt -> in_param; +// mtt_start_index -> dma_rd_rsp_data[127:64]; +wire [63:0] mtt_start_index; +reg [63:0] v2p_head_high; +reg [63:0] v2p_head_low; +//------------------------{Decode & Packet generation}end---------------------------// + +/* -------FSM relevant{begin}------- */ +localparam IDLE = 3'b001, + INBOX_V2P_REQ = 3'b010, + BARE_V2P_REQ = 3'b100; +reg [2:0] cur_state; +reg [2:0] nxt_state; + +wire is_idle, is_inbox_v2p_req, is_bare_v2p_req; +wire j_inbox_v2p_req, j_bare_v2p_req; +/* -------FSM relevant{end}------- */ + +/* --------------------------------------------------------------------------------------------------- */ + +/* -------Decode & Packet generation{begin}------- */ +assign is_map_icm = (op == `CMD_MAP_ICM ); +assign is_unmap_icm = (op == `CMD_UNMAP_ICM); +assign is_sw2hw_mpt = (op == `CMD_SW2HW_MPT); +assign is_hw2sw_mpt = (op == `CMD_HW2SW_MPT); +assign is_write_mtt = (op == `CMD_WRITE_MTT); + +always @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + is_write_mtt_reg <= `TD 0; + end + else begin + is_write_mtt_reg <= `TD is_write_mtt; + end +end + +assign typ = ({`AXIS_TYPE_WIDTH {is_map_icm }} & `MAP_ICM_TPT) | + ({`AXIS_TYPE_WIDTH {is_unmap_icm}} & `MAP_ICM_TPT) | + ({`AXIS_TYPE_WIDTH {is_sw2hw_mpt}} & `WR_MPT_TPT ) | + ({`AXIS_TYPE_WIDTH {is_hw2sw_mpt}} & `WR_MPT_TPT ) | + ({`AXIS_TYPE_WIDTH {is_write_mtt}} & `WR_MTT_TPT ); +assign opcode = ({`AXIS_OPCODE_WIDTH{is_map_icm }} & `MAP_ICM_EN ) | + ({`AXIS_OPCODE_WIDTH{is_unmap_icm}} & `MAP_ICM_DIS ) | + ({`AXIS_OPCODE_WIDTH{is_sw2hw_mpt}} & `WR_MPT_WRITE ) | + ({`AXIS_OPCODE_WIDTH{is_hw2sw_mpt}} & `WR_MPT_INVALID) | + ({`AXIS_OPCODE_WIDTH{is_write_mtt}} & `WR_MTT_WRITE ); + +assign mtt_start_index = dma_rd_rsp_data[63:0]; +always @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + v2p_head_low <= `TD 0; + end + else if ((is_inbox_v2p_req | is_bare_v2p_req) & + v2p_req_valid & v2p_req_ready & v2p_req_last) begin + v2p_head_low <= `TD 0; + end + else if (is_idle & start & is_write_mtt & dma_rd_rsp_valid & dma_rd_rsp_ready) begin + v2p_head_low <= `TD mtt_start_index; + end + else if (is_idle & start & is_unmap_icm) begin + v2p_head_low <= `TD in_param; + end +end +always @(posedge clk, negedge rst_n) begin + if (~rst_n) begin + v2p_head_high <= `TD 0; + end + else if (j_inbox_v2p_req || j_bare_v2p_req) begin + v2p_head_high <= `TD {typ, opcode, {32-`AXIS_TYPE_WIDTH-`AXIS_OPCODE_WIDTH{1'b0}}, in_modifier}; + end +end +/* -------Decode & Packet generation{end}------- */ + +//------------------------------{write v2p FSM}begin------------------------------// + +/******************** Stage 1: State Register **********************/ +always @(posedge clk or negedge rst_n) begin + if(~rst_n) + cur_state <= `TD IDLE; + else + cur_state <= `TD nxt_state; +end + +/******************** Stage 2: State Transition **********************/ +assign is_idle = (cur_state == IDLE ); +assign is_inbox_v2p_req = (cur_state == INBOX_V2P_REQ); +assign is_bare_v2p_req = (cur_state == BARE_V2P_REQ ); + +assign j_inbox_v2p_req = is_idle & start & has_inbox & dma_rd_rsp_valid; +assign j_bare_v2p_req = is_idle & start & !has_inbox; + +always @(*) begin + case(cur_state) + IDLE: begin + if (start & has_inbox & dma_rd_rsp_valid) begin // DMA data is ready for transmission + nxt_state = INBOX_V2P_REQ; + end + else if (start & !has_inbox) begin // There's no need of data, so jump to BARE_V2P_REQ + nxt_state = BARE_V2P_REQ; + end + else begin + nxt_state = IDLE; + end + end + INBOX_V2P_REQ: begin + if (v2p_req_valid & v2p_req_ready & v2p_req_last) begin // v2p write req data end + nxt_state = IDLE; + end + else begin + nxt_state = INBOX_V2P_REQ; + end + end + BARE_V2P_REQ: begin + if (v2p_req_valid & v2p_req_ready & v2p_req_last) begin // v2p write req data end + nxt_state = IDLE; + end + else begin + nxt_state = BARE_V2P_REQ; + end + end + default: begin + nxt_state = IDLE; + end + endcase +end +/******************** Stage 3: Output **********************/ + + +/* ***** output ***** */ +// virtual to physical write request +assign v2p_req_valid = (is_inbox_v2p_req & dma_rd_rsp_valid) | is_bare_v2p_req; +assign v2p_req_head = v2p_req_valid ? {v2p_head_high, v2p_head_low} : 0; +assign v2p_req_data = is_inbox_v2p_req ? dma_rd_rsp_data : 0; +assign v2p_req_last = (is_inbox_v2p_req & dma_rd_rsp_last) | + (is_bare_v2p_req); + +// dma read response +assign dma_rd_rsp_ready = (is_idle & is_write_mtt_reg) | // drain the first rsp data + (is_inbox_v2p_req & v2p_req_ready); + +// finish +assign finish = (is_inbox_v2p_req | is_bare_v2p_req) & v2p_req_ready & v2p_req_last; +/* ***** for output ***** */ +//------------------------------{write v2p FSM}end------------------------------// + +`ifdef CEU_DBG_LOGIC +/* --------DBG signal{begin}-------- */ +assign dbg_bus = {mtt_start_index, cur_state, nxt_state}; +/* --------DBG signal{end}-------- */ +`endif +endmodule diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/ICMMgt/CxtMgt/CxtMgt.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/ICMMgt/CxtMgt/CxtMgt.v new file mode 100644 index 0000000000000000000000000000000000000000..878fb45d38868a6fdf128094c6d2ac0907db23a6 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/ICMMgt/CxtMgt/CxtMgt.v @@ -0,0 +1,854 @@ +/*------------------------------------------- Module Description : Begin ---------------------------------------------- +Name: CxtMgt +Author: YangFan +Function: Context Management. +--------------------------------------------- Module Decription : End -----------------------------------------------*/ + +/*------------------------------------------- Timescale Definition : Begin ------------------------------------------*/ +`timescale 1ns / 1ps +/*------------------------------------------- Timescale Definition : End --------------------------------------------*/ + +/*------------------------------------------- Included Files : Begin ------------------------------------------------*/ +`include "protocol_engine_def.vh" +/*------------------------------------------- Included Files : End --------------------------------------------------*/ + +/*------------------------------------------- Input/Output Definition : Begin ---------------------------------------*/ +module CxtMgt +( + input wire clk, + input wire rst, + +//CEU Request + input wire ceu_req_valid, + input wire [`CEU_CXT_HEAD_WIDTH - 1 : 0] ceu_req_head, + input wire ceu_req_last, + input wire [`CEU_CXT_DATA_WIDTH - 1 : 0] ceu_req_data, + output wire ceu_req_ready, + +//CEU Response + output wire qpc_rsp_valid, + output wire [`CEU_CXT_HEAD_WIDTH - 1 : 0] qpc_rsp_head, + output wire qpc_rsp_last, + output wire [`CEU_CXT_DATA_WIDTH - 1 : 0] qpc_rsp_data, + input wire qpc_rsp_ready, + +//Request channels + input wire SQ_cxt_req_valid, + input wire [`CXT_CMD_HEAD_WIDTH + `MAX_REQ_TAG_NUM_LOG - 1 : 0] SQ_cxt_req_head, + input wire [`CXT_CMD_DATA_WIDTH - 1 : 0] SQ_cxt_req_data, + output wire SQ_cxt_req_ready, + + input wire TX_REQ_cxt_req_valid, + input wire [`CXT_CMD_HEAD_WIDTH + `MAX_REQ_TAG_NUM_LOG - 1 : 0] TX_REQ_cxt_req_head, + input wire [`CXT_CMD_DATA_WIDTH - 1 : 0] TX_REQ_cxt_req_data, + output wire TX_REQ_cxt_req_ready, + + input wire RX_REQ_cxt_req_valid, + input wire [`CXT_CMD_HEAD_WIDTH + `MAX_REQ_TAG_NUM_LOG - 1 : 0] RX_REQ_cxt_req_head, + input wire [`CXT_CMD_DATA_WIDTH - 1 : 0] RX_REQ_cxt_req_data, + output wire RX_REQ_cxt_req_ready, + + input wire RX_RESP_cxt_req_valid, + input wire [`CXT_CMD_HEAD_WIDTH + `MAX_REQ_TAG_NUM_LOG - 1 : 0] RX_RESP_cxt_req_head, + input wire [`CXT_CMD_DATA_WIDTH - 1 : 0] RX_RESP_cxt_req_data, + output wire RX_RESP_cxt_req_ready, + +//Response channels + output wire SQ_cxt_rsp_valid, + output wire [`CXT_RESP_HEAD_WIDTH + `MAX_REQ_TAG_NUM_LOG - 1 : 0] SQ_cxt_rsp_head, + output wire [`CXT_RESP_DATA_WIDTH - 1 : 0] SQ_cxt_rsp_data, + input wire SQ_cxt_rsp_ready, + + output wire TX_REQ_cxt_rsp_valid, + output wire [`CXT_RESP_HEAD_WIDTH + `MAX_REQ_TAG_NUM_LOG - 1 : 0] TX_REQ_cxt_rsp_head, + output wire [`CXT_RESP_DATA_WIDTH - 1 : 0] TX_REQ_cxt_rsp_data, + input wire TX_REQ_cxt_rsp_ready, + + output wire RX_REQ_cxt_rsp_valid, + output wire [`CXT_RESP_HEAD_WIDTH + `MAX_REQ_TAG_NUM_LOG - 1 : 0] RX_REQ_cxt_rsp_head, + output wire [`CXT_RESP_DATA_WIDTH - 1 : 0] RX_REQ_cxt_rsp_data, + input wire RX_REQ_cxt_rsp_ready, + + output wire RX_RESP_cxt_rsp_valid, + output wire [`CXT_RESP_HEAD_WIDTH + `MAX_REQ_TAG_NUM_LOG - 1 : 0] RX_RESP_cxt_rsp_head, + output wire [`CXT_RESP_DATA_WIDTH - 1 : 0] RX_RESP_cxt_rsp_data, + input wire RX_RESP_cxt_rsp_ready, + +//Interface with DMA + output wire qpc_dma_rd_req_valid, + output wire [`DMA_HEAD_WIDTH - 1 : 0] qpc_dma_rd_req_head, + output wire [`DMA_DATA_WIDTH - 1 : 0] qpc_dma_rd_req_data, + output wire qpc_dma_rd_req_last, + input wire qpc_dma_rd_req_ready, + + input wire qpc_dma_rd_rsp_valid, + input wire [`DMA_HEAD_WIDTH - 1 : 0] qpc_dma_rd_rsp_head, + input wire [`DMA_DATA_WIDTH - 1 : 0] qpc_dma_rd_rsp_data, + input wire qpc_dma_rd_rsp_last, + output wire qpc_dma_rd_rsp_ready, + + output wire qpc_dma_wr_req_valid, + output wire [`DMA_HEAD_WIDTH - 1 : 0] qpc_dma_wr_req_head, + output wire [`DMA_DATA_WIDTH - 1 : 0] qpc_dma_wr_req_data, + output wire qpc_dma_wr_req_last, + input wire qpc_dma_wr_req_ready, + + output wire cqc_dma_rd_req_valid, + output wire [`DMA_HEAD_WIDTH - 1 : 0] cqc_dma_rd_req_head, + output wire [`DMA_DATA_WIDTH - 1 : 0] cqc_dma_rd_req_data, + output wire cqc_dma_rd_req_last, + input wire cqc_dma_rd_req_ready, + + input wire cqc_dma_rd_rsp_valid, + input wire [`DMA_HEAD_WIDTH - 1 : 0] cqc_dma_rd_rsp_head, + input wire [`DMA_DATA_WIDTH - 1 : 0] cqc_dma_rd_rsp_data, + input wire cqc_dma_rd_rsp_last, + output wire cqc_dma_rd_rsp_ready, + + output wire cqc_dma_wr_req_valid, + output wire [`DMA_HEAD_WIDTH - 1 : 0] cqc_dma_wr_req_head, + output wire [`DMA_DATA_WIDTH - 1 : 0] cqc_dma_wr_req_data, + output wire cqc_dma_wr_req_last, + input wire cqc_dma_wr_req_ready, + + output wire eqc_dma_rd_req_valid, + output wire [`DMA_HEAD_WIDTH - 1 : 0] eqc_dma_rd_req_head, + output wire [`DMA_DATA_WIDTH - 1 : 0] eqc_dma_rd_req_data, + output wire eqc_dma_rd_req_last, + input wire eqc_dma_rd_req_ready, + + input wire eqc_dma_rd_rsp_valid, + input wire [`DMA_HEAD_WIDTH - 1 : 0] eqc_dma_rd_rsp_head, + input wire [`DMA_DATA_WIDTH - 1 : 0] eqc_dma_rd_rsp_data, + input wire eqc_dma_rd_rsp_last, + output wire eqc_dma_rd_rsp_ready, + + output wire eqc_dma_wr_req_valid, + output wire [`DMA_HEAD_WIDTH - 1 : 0] eqc_dma_wr_req_head, + output wire [`DMA_DATA_WIDTH - 1 : 0] eqc_dma_wr_req_data, + output wire eqc_dma_wr_req_last, + input wire eqc_dma_wr_req_ready +); + +/*------------------------------------------- Input/Output Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Macros Definition : Begin ---------------------------------------*/ + +/*------------------------------------------- Local Macros Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Variables Definition : Begin ------------------------------------*/ +wire qpc_icm_mapping_set_valid; +wire [`PAGE_FRAME_WIDTH - 1 : 0] qpc_icm_mapping_set_head; +wire [`PAGE_FRAME_WIDTH - 1 : 0] qpc_icm_mapping_set_data; + +wire qpc_icm_mapping_lookup_valid; +wire [log2b(`ICM_ENTRY_NUM_MPT - 1) - 1 : 0] qpc_icm_mapping_lookup_head; + +wire qpc_icm_mapping_rsp_valid; +wire [`ICM_SPACE_ADDR_WIDTH - 1 : 0] qpc_icm_mapping_rsp_icm_addr; +wire [`PHY_SPACE_ADDR_WIDTH - 1 : 0] qpc_icm_mapping_rsp_phy_addr; + +wire sw_qpc_icm_mapping_lookup_valid; +wire [log2b(`ICM_ENTRY_NUM_QPC - 1) - 1 : 0] sw_qpc_icm_mapping_lookup_head; +wire sw_qpc_icm_mapping_lookup_ready; + +wire sw_qpc_icm_mapping_rsp_valid; +wire [`ICM_SPACE_ADDR_WIDTH - 1 : 0] sw_qpc_icm_mapping_rsp_icm_addr; +wire [`PHY_SPACE_ADDR_WIDTH - 1 : 0] sw_qpc_icm_mapping_rsp_phy_addr; +wire sw_qpc_icm_mapping_rsp_ready; + +wire hw_qpc_icm_mapping_lookup_valid; +wire [log2b(`ICM_ENTRY_NUM_QPC - 1) - 1 : 0] hw_qpc_icm_mapping_lookup_head; +wire hw_qpc_icm_mapping_lookup_ready; + +wire hw_qpc_icm_mapping_rsp_valid; +wire [`ICM_SPACE_ADDR_WIDTH - 1 : 0] hw_qpc_icm_mapping_rsp_icm_addr; +wire [`PHY_SPACE_ADDR_WIDTH - 1 : 0] hw_qpc_icm_mapping_rsp_phy_addr; +wire hw_qpc_icm_mapping_rsp_ready; + +wire qpc_icm_get_req_valid; +wire [`COUNT_MAX_LOG * 2 + `MAX_REQ_TAG_NUM_LOG + `PHY_SPACE_ADDR_WIDTH + `ICM_SPACE_ADDR_WIDTH - 1 : 0] qpc_icm_get_req_head; +wire qpc_icm_get_req_ready; + +wire qpc_icm_get_rsp_valid; +wire [`COUNT_MAX_LOG * 2 + `MAX_REQ_TAG_NUM_LOG + `PHY_SPACE_ADDR_WIDTH + `ICM_SPACE_ADDR_WIDTH - 1 : 0] qpc_icm_get_rsp_head; +wire [`CACHE_ENTRY_WIDTH_QPC - 1 : 0] qpc_icm_get_rsp_data; +wire qpc_icm_get_rsp_ready; + +wire sw_qpc_icm_get_req_valid; +wire [`COUNT_MAX_LOG * 2 + `MAX_REQ_TAG_NUM_LOG + `PHY_SPACE_ADDR_WIDTH + `ICM_SPACE_ADDR_WIDTH - 1 : 0] sw_qpc_icm_get_req_head; +wire sw_qpc_icm_get_req_ready; + +wire sw_qpc_icm_get_rsp_valid; +wire [`COUNT_MAX_LOG * 2 + `MAX_REQ_TAG_NUM_LOG + `PHY_SPACE_ADDR_WIDTH + `ICM_SPACE_ADDR_WIDTH - 1 : 0] sw_qpc_icm_get_rsp_head; +wire [`CACHE_ENTRY_WIDTH_QPC - 1 : 0] sw_qpc_icm_get_rsp_data; +wire sw_qpc_icm_get_rsp_ready; + +wire hw_qpc_icm_get_req_valid; +wire [`COUNT_MAX_LOG * 2 + `MAX_REQ_TAG_NUM_LOG + `PHY_SPACE_ADDR_WIDTH + `ICM_SPACE_ADDR_WIDTH - 1 : 0] hw_qpc_icm_get_req_head; +wire hw_qpc_icm_get_req_ready; + +wire hw_qpc_icm_get_rsp_valid; +wire [`COUNT_MAX_LOG * 2 + `MAX_REQ_TAG_NUM_LOG + `PHY_SPACE_ADDR_WIDTH + `ICM_SPACE_ADDR_WIDTH - 1 : 0] hw_qpc_icm_get_rsp_head; +wire [`CACHE_ENTRY_WIDTH_QPC - 1 : 0] hw_qpc_icm_get_rsp_data; +wire hw_qpc_icm_get_rsp_ready; + +wire qpc_icm_set_req_valid; +wire [`PHY_SPACE_ADDR_WIDTH + `ICM_SPACE_ADDR_WIDTH - 1 : 0] qpc_icm_set_req_head; +wire [`CACHE_ENTRY_WIDTH_QPC - 1 : 0] qpc_icm_set_req_data; +wire qpc_icm_set_req_ready; + +wire cqc_icm_mapping_set_valid; +wire [`PAGE_FRAME_WIDTH - 1 : 0] cqc_icm_mapping_set_head; +wire [`PAGE_FRAME_WIDTH - 1 : 0] cqc_icm_mapping_set_data; + +wire cqc_icm_mapping_lookup_valid; +wire [log2b(`ICM_ENTRY_NUM_CQC - 1) - 1 : 0] cqc_icm_mapping_lookup_head; + +wire cqc_icm_mapping_rsp_valid; +wire [`ICM_SPACE_ADDR_WIDTH - 1 : 0] cqc_icm_mapping_rsp_icm_addr; +wire [`PHY_SPACE_ADDR_WIDTH - 1 : 0] cqc_icm_mapping_rsp_phy_addr; + +wire sw_cqc_icm_mapping_lookup_valid; +wire [log2b(`ICM_ENTRY_NUM_CQC - 1) - 1 : 0] sw_cqc_icm_mapping_lookup_head; +wire sw_cqc_icm_mapping_lookup_ready; + +wire sw_cqc_icm_mapping_rsp_valid; +wire [`ICM_SPACE_ADDR_WIDTH - 1 : 0] sw_cqc_icm_mapping_rsp_icm_addr; +wire [`PHY_SPACE_ADDR_WIDTH - 1 : 0] sw_cqc_icm_mapping_rsp_phy_addr; +wire sw_cqc_icm_mapping_rsp_ready; + +wire hw_cqc_icm_mapping_lookup_valid; +wire [log2b(`ICM_ENTRY_NUM_CQC - 1) - 1 : 0] hw_cqc_icm_mapping_lookup_head; +wire hw_cqc_icm_mapping_lookup_ready; + +wire hw_cqc_icm_mapping_rsp_valid; +wire [`ICM_SPACE_ADDR_WIDTH - 1 : 0] hw_cqc_icm_mapping_rsp_icm_addr; +wire [`PHY_SPACE_ADDR_WIDTH - 1 : 0] hw_cqc_icm_mapping_rsp_phy_addr; +wire hw_cqc_icm_mapping_rsp_ready; + +wire cqc_icm_get_req_valid; +wire [`COUNT_MAX_LOG * 2 + `MAX_REQ_TAG_NUM_LOG + `PHY_SPACE_ADDR_WIDTH + `ICM_SPACE_ADDR_WIDTH - 1 : 0] cqc_icm_get_req_head; +wire cqc_icm_get_req_ready; + +wire cqc_icm_get_rsp_valid; +wire [`COUNT_MAX_LOG * 2 + `MAX_REQ_TAG_NUM_LOG + `PHY_SPACE_ADDR_WIDTH + `ICM_SPACE_ADDR_WIDTH - 1 : 0] cqc_icm_get_rsp_head; +wire [`CACHE_ENTRY_WIDTH_CQC - 1 : 0] cqc_icm_get_rsp_data; +wire cqc_icm_get_rsp_ready; + +wire cqc_icm_set_req_valid; +wire [`PHY_SPACE_ADDR_WIDTH + `ICM_SPACE_ADDR_WIDTH - 1 : 0] cqc_icm_set_req_head; +wire [`CACHE_ENTRY_WIDTH_CQC - 1 : 0] cqc_icm_set_req_data; +wire cqc_icm_set_req_ready; + +wire eqc_icm_mapping_set_valid; +wire [`PAGE_FRAME_WIDTH - 1 : 0] eqc_icm_mapping_set_head; +wire [`PAGE_FRAME_WIDTH - 1 : 0] eqc_icm_mapping_set_data; + +wire eqc_icm_mapping_lookup_valid; +wire [log2b(`ICM_ENTRY_NUM_MTT - 1) - 1 : 0] eqc_icm_mapping_lookup_head; + +wire eqc_icm_mapping_rsp_valid; +wire [`ICM_SPACE_ADDR_WIDTH - 1 : 0] eqc_icm_mapping_rsp_icm_addr; +wire [`PHY_SPACE_ADDR_WIDTH - 1 : 0] eqc_icm_mapping_rsp_phy_addr; + +wire sw_eqc_icm_mapping_lookup_valid; +wire [log2b(`ICM_ENTRY_NUM_EQC - 1) - 1 : 0] sw_eqc_icm_mapping_lookup_head; +wire sw_eqc_icm_mapping_lookup_ready; + +wire sw_eqc_icm_mapping_rsp_valid; +wire [`ICM_SPACE_ADDR_WIDTH - 1 : 0] sw_eqc_icm_mapping_rsp_icm_addr; +wire [`PHY_SPACE_ADDR_WIDTH - 1 : 0] sw_eqc_icm_mapping_rsp_phy_addr; +wire sw_eqc_icm_mapping_rsp_ready; + +wire hw_eqc_icm_mapping_lookup_valid; +wire [log2b(`ICM_ENTRY_NUM_EQC - 1) - 1 : 0] hw_eqc_icm_mapping_lookup_head; +wire hw_eqc_icm_mapping_lookup_ready; + +wire hw_eqc_icm_mapping_rsp_valid; +wire [`ICM_SPACE_ADDR_WIDTH - 1 : 0] hw_eqc_icm_mapping_rsp_icm_addr; +wire [`PHY_SPACE_ADDR_WIDTH - 1 : 0] hw_eqc_icm_mapping_rsp_phy_addr; +wire hw_eqc_icm_mapping_rsp_ready; + +wire eqc_icm_get_req_valid; +wire [`COUNT_MAX_LOG * 2 + `MAX_REQ_TAG_NUM_LOG + `PHY_SPACE_ADDR_WIDTH + `ICM_SPACE_ADDR_WIDTH - 1 : 0] eqc_icm_get_req_head; +wire eqc_icm_get_req_ready; + +wire eqc_icm_get_rsp_valid; +wire [`COUNT_MAX_LOG * 2 + `MAX_REQ_TAG_NUM_LOG + `PHY_SPACE_ADDR_WIDTH + `ICM_SPACE_ADDR_WIDTH - 1 : 0] eqc_icm_get_rsp_head; +wire [`CACHE_ENTRY_WIDTH_EQC - 1 : 0] eqc_icm_get_rsp_data; +wire eqc_icm_get_rsp_ready; + +wire eqc_icm_set_req_valid; +wire [`PHY_SPACE_ADDR_WIDTH + `ICM_SPACE_ADDR_WIDTH - 1 : 0] eqc_icm_set_req_head; +wire [`CACHE_ENTRY_WIDTH_EQC - 1 : 0] eqc_icm_set_req_data; +wire eqc_icm_set_req_ready; + +wire [`ICM_SPACE_ADDR_WIDTH - 1 : 0] qpc_base; +wire [`ICM_SPACE_ADDR_WIDTH - 1 : 0] cqc_base; +wire [`ICM_SPACE_ADDR_WIDTH - 1 : 0] eqc_base; +/*------------------------------------------- Local Variables Definition : End --------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : Begin ---------------------------------------*/ +SWAccCMCtl SWAccCMCtl_Inst( + .clk ( clk ), + .rst ( rst ), + + .ceu_req_valid ( ceu_req_valid ), + .ceu_req_head ( ceu_req_head ), + .ceu_req_last ( ceu_req_last ), + .ceu_req_data ( ceu_req_data ), + .ceu_req_ready ( ceu_req_ready ), + + .qpc_rsp_valid ( qpc_rsp_valid ), + .qpc_rsp_head ( qpc_rsp_head ), + .qpc_rsp_last ( qpc_rsp_last ), + .qpc_rsp_data ( qpc_rsp_data ), + .qpc_rsp_ready ( qpc_rsp_ready ), + + .qpc_mapping_set_valid ( qpc_icm_mapping_set_valid ), + .qpc_mapping_set_head ( qpc_icm_mapping_set_head ), + .qpc_mapping_set_data ( qpc_icm_mapping_set_data ), + + .qpc_cache_get_req_valid ( sw_qpc_icm_get_req_valid ), + .qpc_cache_get_req_head ( sw_qpc_icm_get_req_head ), + .qpc_cache_get_req_ready ( sw_qpc_icm_get_req_ready ), + + .qpc_cache_get_rsp_valid ( sw_qpc_icm_get_rsp_valid ), + .qpc_cache_get_rsp_head ( sw_qpc_icm_get_rsp_head ), + .qpc_cache_get_rsp_data ( sw_qpc_icm_get_rsp_data ), + .qpc_cache_get_rsp_ready ( sw_qpc_icm_get_rsp_ready ), + + .qpc_cache_set_req_valid ( qpc_icm_set_req_valid ), + .qpc_cache_set_req_head ( qpc_icm_set_req_head ), + .qpc_cache_set_req_data ( qpc_icm_set_req_data ), + .qpc_cache_set_req_ready ( qpc_icm_set_req_ready ), + + .qpc_icm_mapping_lookup_valid ( sw_qpc_icm_mapping_lookup_valid ), + .qpc_icm_mapping_lookup_head ( sw_qpc_icm_mapping_lookup_head ), + .qpc_icm_mapping_lookup_ready ( sw_qpc_icm_mapping_lookup_ready ), + + .qpc_icm_mapping_rsp_valid ( sw_qpc_icm_mapping_rsp_valid ), + .qpc_icm_mapping_rsp_icm_addr ( sw_qpc_icm_mapping_rsp_icm_addr ), + .qpc_icm_mapping_rsp_phy_addr ( sw_qpc_icm_mapping_rsp_phy_addr ), + .qpc_icm_mapping_rsp_ready ( sw_qpc_icm_mapping_rsp_ready ), + + .cqc_mapping_set_valid ( cqc_icm_mapping_set_valid ), + .cqc_mapping_set_head ( cqc_icm_mapping_set_head ), + .cqc_mapping_set_data ( cqc_icm_mapping_set_data ), + + .cqc_cache_set_req_valid ( cqc_icm_set_req_valid ), + .cqc_cache_set_req_head ( cqc_icm_set_req_head ), + .cqc_cache_set_req_data ( cqc_icm_set_req_data ), + .cqc_cache_set_req_ready ( cqc_icm_set_req_ready ), + + .cqc_icm_mapping_lookup_valid ( sw_cqc_icm_mapping_lookup_valid ), + .cqc_icm_mapping_lookup_head ( sw_cqc_icm_mapping_lookup_head ), + .cqc_icm_mapping_lookup_ready ( sw_cqc_icm_mapping_lookup_ready ), + + .cqc_icm_mapping_rsp_valid ( sw_cqc_icm_mapping_rsp_valid ), + .cqc_icm_mapping_rsp_icm_addr ( sw_cqc_icm_mapping_rsp_icm_addr ), + .cqc_icm_mapping_rsp_phy_addr ( sw_cqc_icm_mapping_rsp_phy_addr ), + .cqc_icm_mapping_rsp_ready ( sw_cqc_icm_mapping_rsp_ready ), + + .eqc_mapping_set_valid ( eqc_icm_mapping_set_valid ), + .eqc_mapping_set_head ( eqc_icm_mapping_set_head ), + .eqc_mapping_set_data ( eqc_icm_mapping_set_data ), + + .eqc_cache_set_req_valid ( eqc_icm_set_req_valid ), + .eqc_cache_set_req_head ( eqc_icm_set_req_head ), + .eqc_cache_set_req_data ( eqc_icm_set_req_data ), + .eqc_cache_set_req_ready ( eqc_icm_set_req_ready ), + + .eqc_icm_mapping_lookup_valid ( sw_eqc_icm_mapping_lookup_valid ), + .eqc_icm_mapping_lookup_head ( sw_eqc_icm_mapping_lookup_head ), + .eqc_icm_mapping_lookup_ready ( sw_eqc_icm_mapping_lookup_ready ), + + .eqc_icm_mapping_rsp_valid ( sw_eqc_icm_mapping_rsp_valid ), + .eqc_icm_mapping_rsp_icm_addr ( sw_eqc_icm_mapping_rsp_icm_addr ), + .eqc_icm_mapping_rsp_phy_addr ( sw_eqc_icm_mapping_rsp_phy_addr ), + .eqc_icm_mapping_rsp_ready ( sw_eqc_icm_mapping_rsp_ready ), + + .qpc_base ( qpc_base ), + .cqc_base ( cqc_base ), + .eqc_base ( eqc_base ) +); + +HWAccCMCtl HWAccCMCtl_Inst( + .clk ( clk ), + .rst ( rst ), + + .SQ_cxt_req_valid ( SQ_cxt_req_valid ), + .SQ_cxt_req_head ( SQ_cxt_req_head ), + .SQ_cxt_req_data ( SQ_cxt_req_data ), + .SQ_cxt_req_ready ( SQ_cxt_req_ready ), + + .TX_REQ_cxt_req_valid ( TX_REQ_cxt_req_valid ), + .TX_REQ_cxt_req_head ( TX_REQ_cxt_req_head ), + .TX_REQ_cxt_req_data ( TX_REQ_cxt_req_data ), + .TX_REQ_cxt_req_ready ( TX_REQ_cxt_req_ready ), + + .RX_REQ_cxt_req_valid ( RX_REQ_cxt_req_valid ), + .RX_REQ_cxt_req_head ( RX_REQ_cxt_req_head ), + .RX_REQ_cxt_req_data ( RX_REQ_cxt_req_data ), + .RX_REQ_cxt_req_ready ( RX_REQ_cxt_req_ready ), + + .RX_RESP_cxt_req_valid ( RX_RESP_cxt_req_valid ), + .RX_RESP_cxt_req_head ( RX_RESP_cxt_req_head ), + .RX_RESP_cxt_req_data ( RX_RESP_cxt_req_data ), + .RX_RESP_cxt_req_ready ( RX_RESP_cxt_req_ready ), + + .SQ_cxt_rsp_valid ( SQ_cxt_rsp_valid ), + .SQ_cxt_rsp_head ( SQ_cxt_rsp_head ), + .SQ_cxt_rsp_data ( SQ_cxt_rsp_data ), + .SQ_cxt_rsp_ready ( SQ_cxt_rsp_ready ), + + .TX_REQ_cxt_rsp_valid ( TX_REQ_cxt_rsp_valid ), + .TX_REQ_cxt_rsp_head ( TX_REQ_cxt_rsp_head ), + .TX_REQ_cxt_rsp_data ( TX_REQ_cxt_rsp_data ), + .TX_REQ_cxt_rsp_ready ( TX_REQ_cxt_rsp_ready ), + + .RX_REQ_cxt_rsp_valid ( RX_REQ_cxt_rsp_valid ), + .RX_REQ_cxt_rsp_head ( RX_REQ_cxt_rsp_head ), + .RX_REQ_cxt_rsp_data ( RX_REQ_cxt_rsp_data ), + .RX_REQ_cxt_rsp_ready ( RX_REQ_cxt_rsp_ready ), + + .RX_RESP_cxt_rsp_valid ( RX_RESP_cxt_rsp_valid ), + .RX_RESP_cxt_rsp_head ( RX_RESP_cxt_rsp_head ), + .RX_RESP_cxt_rsp_data ( RX_RESP_cxt_rsp_data ), + .RX_RESP_cxt_rsp_ready ( RX_RESP_cxt_rsp_ready ), + + .qpc_icm_mapping_lookup_valid ( hw_qpc_icm_mapping_lookup_valid ), + .qpc_icm_mapping_lookup_head ( hw_qpc_icm_mapping_lookup_head ), + .qpc_icm_mapping_lookup_ready ( hw_qpc_icm_mapping_lookup_ready ), + + .qpc_icm_mapping_rsp_valid ( hw_qpc_icm_mapping_rsp_valid ), + .qpc_icm_mapping_rsp_icm_addr ( hw_qpc_icm_mapping_rsp_icm_addr ), + .qpc_icm_mapping_rsp_phy_addr ( hw_qpc_icm_mapping_rsp_phy_addr ), + .qpc_icm_mapping_rsp_ready ( hw_qpc_icm_mapping_rsp_ready ), + + .qpc_get_req_valid ( hw_qpc_icm_get_req_valid ), + .qpc_get_req_head ( hw_qpc_icm_get_req_head ), + .qpc_get_req_ready ( hw_qpc_icm_get_req_ready ), + + .qpc_get_rsp_valid ( hw_qpc_icm_get_rsp_valid ), + .qpc_get_rsp_head ( hw_qpc_icm_get_rsp_head ), + .qpc_get_rsp_data ( hw_qpc_icm_get_rsp_data ), + .qpc_get_rsp_ready ( hw_qpc_icm_get_rsp_ready ), + + .cqc_icm_mapping_lookup_valid ( hw_cqc_icm_mapping_lookup_valid ), + .cqc_icm_mapping_lookup_head ( hw_cqc_icm_mapping_lookup_head ), + .cqc_icm_mapping_lookup_ready ( hw_cqc_icm_mapping_lookup_ready ), + + .cqc_icm_mapping_rsp_valid ( hw_cqc_icm_mapping_rsp_valid ), + .cqc_icm_mapping_rsp_icm_addr ( hw_cqc_icm_mapping_rsp_icm_addr ), + .cqc_icm_mapping_rsp_phy_addr ( hw_cqc_icm_mapping_rsp_phy_addr ), + .cqc_icm_mapping_rsp_ready ( hw_cqc_icm_mapping_rsp_ready ), + + .cqc_get_req_valid ( cqc_icm_get_req_valid ), + .cqc_get_req_head ( cqc_icm_get_req_head ), + .cqc_get_req_ready ( cqc_icm_get_req_ready ), + + .cqc_get_rsp_valid ( cqc_icm_get_rsp_valid ), + .cqc_get_rsp_head ( cqc_icm_get_rsp_head ), + .cqc_get_rsp_data ( cqc_icm_get_rsp_data ), + .cqc_get_rsp_ready ( cqc_icm_get_rsp_ready ), + + .eqc_icm_mapping_lookup_valid ( hw_eqc_icm_mapping_lookup_valid ), + .eqc_icm_mapping_lookup_head ( hw_eqc_icm_mapping_lookup_head ), + .eqc_icm_mapping_lookup_ready ( hw_eqc_icm_mapping_lookup_ready ), + + .eqc_icm_mapping_rsp_valid ( hw_eqc_icm_mapping_rsp_valid ), + .eqc_icm_mapping_rsp_icm_addr ( hw_eqc_icm_mapping_rsp_icm_addr ), + .eqc_icm_mapping_rsp_phy_addr ( hw_eqc_icm_mapping_rsp_phy_addr ), + .eqc_icm_mapping_rsp_ready ( hw_eqc_icm_mapping_rsp_ready ), + + .eqc_get_req_valid ( eqc_icm_get_req_valid ), + .eqc_get_req_head ( eqc_icm_get_req_head ), + .eqc_get_req_ready ( eqc_icm_get_req_ready ), + + .eqc_get_rsp_valid ( eqc_icm_get_rsp_valid ), + .eqc_get_rsp_head ( eqc_icm_get_rsp_head ), + .eqc_get_rsp_data ( eqc_icm_get_rsp_data ), + .eqc_get_rsp_ready ( eqc_icm_get_rsp_ready ) +); + +ICMCache #( + .ICM_CACHE_TYPE ( `CACHE_TYPE_QPC ), + .ICM_PAGE_NUM ( `ICM_PAGE_NUM_QPC ), + + .ICM_ENTRY_NUM ( `ICM_ENTRY_NUM_QPC ), + + .ICM_SLOT_SIZE ( `ICM_SLOT_SIZE_QPC ), + .ICM_ADDR_WIDTH ( `ICM_SPACE_ADDR_WIDTH ), + + .CACHE_ENTRY_WIDTH ( `CACHE_ENTRY_WIDTH_QPC ), + .CACHE_SET_NUM ( `CACHE_SET_NUM_QPC ) +) +QPCCache_Inst +( + .clk ( clk ), + .rst ( rst ), + + .icm_get_req_valid ( qpc_icm_get_req_valid ), + .icm_get_req_head ( qpc_icm_get_req_head ), + .icm_get_req_ready ( qpc_icm_get_req_ready ), + + .icm_get_rsp_valid ( qpc_icm_get_rsp_valid ), + .icm_get_rsp_head ( qpc_icm_get_rsp_head ), + .icm_get_rsp_data ( qpc_icm_get_rsp_data ), + .icm_get_rsp_ready ( qpc_icm_get_rsp_ready ), + + .icm_set_req_valid ( qpc_icm_set_req_valid ), + .icm_set_req_head ( qpc_icm_set_req_head ), + .icm_set_req_data ( qpc_icm_set_req_data ), + .icm_set_req_ready ( qpc_icm_set_req_ready ), + + .icm_del_req_valid ( 'd0 ), + .icm_del_req_head ( 'd0 ), + .icm_del_req_ready ( ), + + .dma_rd_req_valid ( qpc_dma_rd_req_valid ), + .dma_rd_req_head ( qpc_dma_rd_req_head ), + .dma_rd_req_data ( qpc_dma_rd_req_data ), + .dma_rd_req_last ( qpc_dma_rd_req_last ), + .dma_rd_req_ready ( qpc_dma_rd_req_ready ), + + .dma_rd_rsp_valid ( qpc_dma_rd_rsp_valid ), + .dma_rd_rsp_head ( qpc_dma_rd_rsp_head ), + .dma_rd_rsp_data ( qpc_dma_rd_rsp_data ), + .dma_rd_rsp_last ( qpc_dma_rd_rsp_last ), + .dma_rd_rsp_ready ( qpc_dma_rd_rsp_ready ), + + .dma_wr_req_valid ( qpc_dma_wr_req_valid ), + .dma_wr_req_head ( qpc_dma_wr_req_head ), + .dma_wr_req_data ( qpc_dma_wr_req_data ), + .dma_wr_req_last ( qpc_dma_wr_req_last ), + .dma_wr_req_ready ( qpc_dma_wr_req_ready ), + + .icm_mapping_set_valid ( qpc_icm_mapping_set_valid ), + .icm_mapping_set_head ( qpc_icm_mapping_set_head ), + .icm_mapping_set_data ( qpc_icm_mapping_set_data ), + + .icm_mapping_lookup_valid ( qpc_icm_mapping_lookup_valid ), + .icm_mapping_lookup_head ( qpc_icm_mapping_lookup_head ), + + .icm_mapping_rsp_valid ( qpc_icm_mapping_rsp_valid ), + .icm_mapping_rsp_icm_addr ( qpc_icm_mapping_rsp_icm_addr ), + .icm_mapping_rsp_phy_addr ( qpc_icm_mapping_rsp_phy_addr ), + + .icm_base ( qpc_base ) + ); + +ICMCache #( + .ICM_CACHE_TYPE ( `CACHE_TYPE_CQC ), + .ICM_PAGE_NUM ( `ICM_PAGE_NUM_CQC ), + + .ICM_ENTRY_NUM ( `ICM_ENTRY_NUM_CQC ), + + .ICM_SLOT_SIZE ( `ICM_SLOT_SIZE_CQC ), + .ICM_ADDR_WIDTH ( `ICM_SPACE_ADDR_WIDTH ), + + .CACHE_ENTRY_WIDTH ( `CACHE_ENTRY_WIDTH_CQC ), + .CACHE_SET_NUM ( `CACHE_SET_NUM_CQC ) +) +CQCCache_Inst +( + .clk ( clk ), + .rst ( rst ), + + .icm_get_req_valid ( cqc_icm_get_req_valid ), + .icm_get_req_head ( cqc_icm_get_req_head ), + .icm_get_req_ready ( cqc_icm_get_req_ready ), + + .icm_get_rsp_valid ( cqc_icm_get_rsp_valid ), + .icm_get_rsp_head ( cqc_icm_get_rsp_head ), + .icm_get_rsp_data ( cqc_icm_get_rsp_data ), + .icm_get_rsp_ready ( cqc_icm_get_rsp_ready ), + + .icm_set_req_valid ( cqc_icm_set_req_valid ), + .icm_set_req_head ( cqc_icm_set_req_head ), + .icm_set_req_data ( cqc_icm_set_req_data ), + .icm_set_req_ready ( cqc_icm_set_req_ready ), + + .icm_del_req_valid ( 'd0 ), + .icm_del_req_head ( 'd0 ), + .icm_del_req_ready ( ), + + .dma_rd_req_valid ( cqc_dma_rd_req_valid ), + .dma_rd_req_head ( cqc_dma_rd_req_head ), + .dma_rd_req_data ( cqc_dma_rd_req_data ), + .dma_rd_req_last ( cqc_dma_rd_req_last ), + .dma_rd_req_ready ( cqc_dma_rd_req_ready ), + + .dma_rd_rsp_valid ( cqc_dma_rd_rsp_valid ), + .dma_rd_rsp_head ( cqc_dma_rd_rsp_head ), + .dma_rd_rsp_data ( cqc_dma_rd_rsp_data ), + .dma_rd_rsp_last ( cqc_dma_rd_rsp_last ), + .dma_rd_rsp_ready ( cqc_dma_rd_rsp_ready ), + + .dma_wr_req_valid ( cqc_dma_wr_req_valid ), + .dma_wr_req_head ( cqc_dma_wr_req_head ), + .dma_wr_req_data ( cqc_dma_wr_req_data ), + .dma_wr_req_last ( cqc_dma_wr_req_last ), + .dma_wr_req_ready ( cqc_dma_wr_req_ready ), + + .icm_mapping_set_valid ( cqc_icm_mapping_set_valid ), + .icm_mapping_set_head ( cqc_icm_mapping_set_head ), + .icm_mapping_set_data ( cqc_icm_mapping_set_data ), + + .icm_mapping_lookup_valid ( cqc_icm_mapping_lookup_valid ), + .icm_mapping_lookup_head ( cqc_icm_mapping_lookup_head ), + + .icm_mapping_rsp_valid ( cqc_icm_mapping_rsp_valid ), + .icm_mapping_rsp_icm_addr ( cqc_icm_mapping_rsp_icm_addr ), + .icm_mapping_rsp_phy_addr ( cqc_icm_mapping_rsp_phy_addr ), + + .icm_base ( cqc_base ) + ); + +ICMCache #( + .ICM_CACHE_TYPE ( `CACHE_TYPE_EQC ), + .ICM_PAGE_NUM ( `ICM_PAGE_NUM_EQC ), + + .ICM_ENTRY_NUM ( `ICM_ENTRY_NUM_EQC ), + + .ICM_SLOT_SIZE ( `ICM_SLOT_SIZE_EQC ), + .ICM_ADDR_WIDTH ( `ICM_SPACE_ADDR_WIDTH ), + + .CACHE_ENTRY_WIDTH ( `CACHE_ENTRY_WIDTH_EQC ), + .CACHE_SET_NUM ( `CACHE_SET_NUM_EQC ) +) +EQCCache_Inst +( + .clk ( clk ), + .rst ( rst ), + + .icm_get_req_valid ( eqc_icm_get_req_valid ), + .icm_get_req_head ( eqc_icm_get_req_head ), + .icm_get_req_ready ( eqc_icm_get_req_ready ), + + .icm_get_rsp_valid ( eqc_icm_get_rsp_valid ), + .icm_get_rsp_head ( eqc_icm_get_rsp_head ), + .icm_get_rsp_data ( eqc_icm_get_rsp_data ), + .icm_get_rsp_ready ( eqc_icm_get_rsp_ready ), + + .icm_set_req_valid ( eqc_icm_set_req_valid ), + .icm_set_req_head ( eqc_icm_set_req_head ), + .icm_set_req_data ( eqc_icm_set_req_data ), + .icm_set_req_ready ( eqc_icm_set_req_ready ), + + .icm_del_req_valid ( 'd0 ), + .icm_del_req_head ( 'd0 ), + .icm_del_req_ready ( ), + + .dma_rd_req_valid ( eqc_dma_rd_req_valid ), + .dma_rd_req_head ( eqc_dma_rd_req_head ), + .dma_rd_req_data ( eqc_dma_rd_req_data ), + .dma_rd_req_last ( eqc_dma_rd_req_last ), + .dma_rd_req_ready ( eqc_dma_rd_req_ready ), + + .dma_rd_rsp_valid ( eqc_dma_rd_rsp_valid ), + .dma_rd_rsp_head ( eqc_dma_rd_rsp_head ), + .dma_rd_rsp_data ( eqc_dma_rd_rsp_data ), + .dma_rd_rsp_last ( eqc_dma_rd_rsp_last ), + .dma_rd_rsp_ready ( eqc_dma_rd_rsp_ready ), + + .dma_wr_req_valid ( eqc_dma_wr_req_valid ), + .dma_wr_req_head ( eqc_dma_wr_req_head ), + .dma_wr_req_data ( eqc_dma_wr_req_data ), + .dma_wr_req_last ( eqc_dma_wr_req_last ), + .dma_wr_req_ready ( eqc_dma_wr_req_ready ), + + .icm_mapping_set_valid ( eqc_icm_mapping_set_valid ), + .icm_mapping_set_head ( eqc_icm_mapping_set_head ), + .icm_mapping_set_data ( eqc_icm_mapping_set_data ), + + .icm_mapping_lookup_valid ( eqc_icm_mapping_lookup_valid ), + .icm_mapping_lookup_head ( eqc_icm_mapping_lookup_head ), + + .icm_mapping_rsp_valid ( eqc_icm_mapping_rsp_valid ), + .icm_mapping_rsp_icm_addr ( eqc_icm_mapping_rsp_icm_addr ), + .icm_mapping_rsp_phy_addr ( eqc_icm_mapping_rsp_phy_addr ), + + .icm_base ( eqc_base ) + ); + +ICMLookupArbiter +#( + .ICM_ENTRY_NUM ( `ICM_ENTRY_NUM_QPC ) +) +QPC_ICMLookupArbiter_Inst +( + .clk ( clk ), + .rst ( rst ), + + .chnl_0_lookup_valid ( sw_qpc_icm_mapping_lookup_valid ), + .chnl_0_lookup_head ( sw_qpc_icm_mapping_lookup_head ), + .chnl_0_lookup_ready ( sw_qpc_icm_mapping_lookup_ready ), + + .chnl_0_rsp_valid ( sw_qpc_icm_mapping_rsp_valid ), + .chnl_0_rsp_icm_addr ( sw_qpc_icm_mapping_rsp_icm_addr ), + .chnl_0_rsp_phy_addr ( sw_qpc_icm_mapping_rsp_phy_addr ), + .chnl_0_rsp_ready ( sw_qpc_icm_mapping_rsp_ready ), + + .chnl_1_lookup_valid ( hw_qpc_icm_mapping_lookup_valid ), + .chnl_1_lookup_head ( hw_qpc_icm_mapping_lookup_head ), + .chnl_1_lookup_ready ( hw_qpc_icm_mapping_lookup_ready ), + + .chnl_1_rsp_valid ( hw_qpc_icm_mapping_rsp_valid ), + .chnl_1_rsp_icm_addr ( hw_qpc_icm_mapping_rsp_icm_addr ), + .chnl_1_rsp_phy_addr ( hw_qpc_icm_mapping_rsp_phy_addr ), + .chnl_1_rsp_ready ( hw_qpc_icm_mapping_rsp_ready ), + + .lookup_valid ( qpc_icm_mapping_lookup_valid ), + .lookup_head ( qpc_icm_mapping_lookup_head ), + + .rsp_valid ( qpc_icm_mapping_rsp_valid ), + .rsp_icm_addr ( qpc_icm_mapping_rsp_icm_addr ), + .rsp_phy_addr ( qpc_icm_mapping_rsp_phy_addr ) +); + +ICMLookupArbiter +#( + .ICM_ENTRY_NUM ( `ICM_ENTRY_NUM_CQC ) +) +CQC_ICMLookupArbiter_Inst +( + .clk ( clk ), + .rst ( rst ), + + .chnl_0_lookup_valid ( sw_cqc_icm_mapping_lookup_valid ), + .chnl_0_lookup_head ( sw_cqc_icm_mapping_lookup_head ), + .chnl_0_lookup_ready ( sw_cqc_icm_mapping_lookup_ready ), + + .chnl_0_rsp_valid ( sw_cqc_icm_mapping_rsp_valid ), + .chnl_0_rsp_icm_addr ( sw_cqc_icm_mapping_rsp_icm_addr ), + .chnl_0_rsp_phy_addr ( sw_cqc_icm_mapping_rsp_phy_addr ), + .chnl_0_rsp_ready ( sw_cqc_icm_mapping_rsp_ready ), + + .chnl_1_lookup_valid ( hw_cqc_icm_mapping_lookup_valid ), + .chnl_1_lookup_head ( hw_cqc_icm_mapping_lookup_head ), + .chnl_1_lookup_ready ( hw_cqc_icm_mapping_lookup_ready ), + + .chnl_1_rsp_valid ( hw_cqc_icm_mapping_rsp_valid ), + .chnl_1_rsp_icm_addr ( hw_cqc_icm_mapping_rsp_icm_addr ), + .chnl_1_rsp_phy_addr ( hw_cqc_icm_mapping_rsp_phy_addr ), + .chnl_1_rsp_ready ( hw_cqc_icm_mapping_rsp_ready ), + + .lookup_valid ( cqc_icm_mapping_lookup_valid ), + .lookup_head ( cqc_icm_mapping_lookup_head ), + + .rsp_valid ( cqc_icm_mapping_rsp_valid ), + .rsp_icm_addr ( cqc_icm_mapping_rsp_icm_addr ), + .rsp_phy_addr ( cqc_icm_mapping_rsp_phy_addr ) +); + +ICMLookupArbiter +#( + .ICM_ENTRY_NUM ( `ICM_ENTRY_NUM_EQC ) +) +EQC_ICMLookupArbiter_Inst +( + .clk ( clk ), + .rst ( rst ), + + .chnl_0_lookup_valid ( sw_eqc_icm_mapping_lookup_valid ), + .chnl_0_lookup_head ( sw_eqc_icm_mapping_lookup_head ), + .chnl_0_lookup_ready ( sw_eqc_icm_mapping_lookup_ready ), + + .chnl_0_rsp_valid ( sw_eqc_icm_mapping_rsp_valid ), + .chnl_0_rsp_icm_addr ( sw_eqc_icm_mapping_rsp_icm_addr ), + .chnl_0_rsp_phy_addr ( sw_eqc_icm_mapping_rsp_phy_addr ), + .chnl_0_rsp_ready ( sw_eqc_icm_mapping_rsp_ready ), + + .chnl_1_lookup_valid ( hw_eqc_icm_mapping_lookup_valid ), + .chnl_1_lookup_head ( hw_eqc_icm_mapping_lookup_head ), + .chnl_1_lookup_ready ( hw_eqc_icm_mapping_lookup_ready ), + + .chnl_1_rsp_valid ( hw_eqc_icm_mapping_rsp_valid ), + .chnl_1_rsp_icm_addr ( hw_eqc_icm_mapping_rsp_icm_addr ), + .chnl_1_rsp_phy_addr ( hw_eqc_icm_mapping_rsp_phy_addr ), + .chnl_1_rsp_ready ( hw_eqc_icm_mapping_rsp_ready ), + + .lookup_valid ( eqc_icm_mapping_lookup_valid ), + .lookup_head ( eqc_icm_mapping_lookup_head ), + + .rsp_valid ( eqc_icm_mapping_rsp_valid ), + .rsp_icm_addr ( eqc_icm_mapping_rsp_icm_addr ), + .rsp_phy_addr ( eqc_icm_mapping_rsp_phy_addr ) +); + +AXISArbiter +#( + .HEAD_WIDTH ( `COUNT_MAX_LOG * 2 + `MAX_REQ_TAG_NUM_LOG + `PHY_SPACE_ADDR_WIDTH + `ICM_SPACE_ADDR_WIDTH ), + .DATA_WIDTH ( 8 ) +) +QPCGetReqArbiter_Inst +( + .clk ( clk ), + .rst ( rst ), + + .in_axis_valid_a ( sw_qpc_icm_get_req_valid ), + .in_axis_head_a ( sw_qpc_icm_get_req_head ), + .in_axis_data_a ( 'd0 ), + .in_axis_start_a ( sw_qpc_icm_get_req_valid ), + .in_axis_last_a ( sw_qpc_icm_get_req_valid ), + .in_axis_ready_a ( sw_qpc_icm_get_req_ready ), + + .in_axis_valid_b ( hw_qpc_icm_get_req_valid ), + .in_axis_head_b ( hw_qpc_icm_get_req_head ), + .in_axis_data_b ( 'd0 ), + .in_axis_start_b ( hw_qpc_icm_get_req_valid ), + .in_axis_last_b ( hw_qpc_icm_get_req_valid ), + .in_axis_ready_b ( hw_qpc_icm_get_req_ready ), + + .out_axis_valid ( qpc_icm_get_req_valid ), + .out_axis_head ( qpc_icm_get_req_head ), + .out_axis_data ( ), + .out_axis_start ( ), + .out_axis_last ( ), + .out_axis_ready ( qpc_icm_get_req_ready ) +); + +wire is_sw_qpc_rsp; +wire is_hw_qpc_rsp; + +assign is_sw_qpc_rsp = qpc_icm_get_rsp_head[`MAX_REQ_TAG_NUM_LOG + `PHY_SPACE_ADDR_WIDTH + `ICM_SPACE_ADDR_WIDTH : `PHY_SPACE_ADDR_WIDTH + `ICM_SPACE_ADDR_WIDTH] == 'd0; +assign is_hw_qpc_rsp = qpc_icm_get_rsp_head[`MAX_REQ_TAG_NUM_LOG + `PHY_SPACE_ADDR_WIDTH + `ICM_SPACE_ADDR_WIDTH : `PHY_SPACE_ADDR_WIDTH + `ICM_SPACE_ADDR_WIDTH] != 'd0; + +assign sw_qpc_icm_get_rsp_valid = is_sw_qpc_rsp ? qpc_icm_get_rsp_valid : 'd0; +assign sw_qpc_icm_get_rsp_head = is_sw_qpc_rsp ? qpc_icm_get_rsp_head : 'd0; +assign sw_qpc_icm_get_rsp_data = is_sw_qpc_rsp ? qpc_icm_get_rsp_data : 'd0; + +assign hw_qpc_icm_get_rsp_valid = is_hw_qpc_rsp ? qpc_icm_get_rsp_valid : 'd0; +assign hw_qpc_icm_get_rsp_head = is_hw_qpc_rsp ? qpc_icm_get_rsp_head : 'd0; +assign hw_qpc_icm_get_rsp_data = is_hw_qpc_rsp ? qpc_icm_get_rsp_data : 'd0; + +assign qpc_icm_get_rsp_ready = is_sw_qpc_rsp ? sw_qpc_icm_get_rsp_ready : + is_hw_qpc_rsp ? hw_qpc_icm_get_rsp_ready : 'd0; +/*------------------------------------------- Submodules Instatiation : End -----------------------------------------*/ + +/*------------------------------------------- State Machine Definition : Begin --------------------------------------*/ +/*------------------------------------------- State Machine Definition : End ----------------------------------------*/ + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ + +/*------------------------------------------- Local Macros Undef : Begin --------------------------------------------*/ +/*------------------------------------------- Local Macros Undef : End ----------------------------------------------*/ +// `ifdef ILA_ON +// ila_cxt_cache ila_cxt_cache_inst( +// .clk(clk), + +// .probe0(hw_qpc_icm_get_req_valid), +// .probe1(hw_qpc_icm_get_rsp_valid), +// .probe2(cqc_icm_get_req_valid), +// .probe3(cqc_icm_get_rsp_valid), +// .probe4(eqc_icm_get_req_valid), +// .probe5(eqc_icm_get_rsp_valid) +// ); +// `endif + +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/ICMMgt/CxtMgt/HWAccCMCtl/HWAccCMCtl.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/ICMMgt/CxtMgt/HWAccCMCtl/HWAccCMCtl.v new file mode 100644 index 0000000000000000000000000000000000000000..06e8a24991e214b5ddef22ddf6ccb2457f4e7edd --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/ICMMgt/CxtMgt/HWAccCMCtl/HWAccCMCtl.v @@ -0,0 +1,550 @@ +/*------------------------------------------- Module Description : Begin ---------------------------------------------- +Name: HWAccCMCtl +Author: YangFan +Function: Control Hardware to CxtMgt Access. +--------------------------------------------- Module Decription : End -----------------------------------------------*/ + +/*------------------------------------------- Timescale Definition : Begin ------------------------------------------*/ +`timescale 1ns / 1ps +/*------------------------------------------- Timescale Definition : End --------------------------------------------*/ + +/*------------------------------------------- Included Files : Begin ------------------------------------------------*/ +`include "protocol_engine_def.vh" +/*------------------------------------------- Included Files : End --------------------------------------------------*/ + +/*------------------------------------------- Input/Output Definition : Begin ---------------------------------------*/ +module HWAccCMCtl +#( + parameter ICM_CACHE_TYPE = `CACHE_TYPE_MTT, + parameter ICM_PAGE_NUM = `ICM_PAGE_NUM_MTT, + parameter ICM_PAGE_NUM_LOG = log2b(ICM_PAGE_NUM - 1), + parameter ICM_ENTRY_NUM = `ICM_ENTRY_NUM_MTT, + parameter ICM_ENTRY_NUM_LOG = log2b(ICM_ENTRY_NUM - 1), + parameter ICM_SLOT_SIZE = `ICM_SLOT_SIZE_MTT, + parameter ICM_ADDR_WIDTH = 64, + + parameter CACHE_ADDR_WIDTH = ICM_ADDR_WIDTH, + parameter CACHE_ENTRY_WIDTH = 256, + parameter CACHE_SET_NUM = 1024, + parameter CACHE_SET_NUM_LOG = log2b(CACHE_SET_NUM - 1), + parameter CACHE_OFFSET_WIDTH = log2b(CACHE_ENTRY_WIDTH / 8 - 1), + parameter CACHE_TAG_WIDTH = CACHE_ADDR_WIDTH - CACHE_OFFSET_WIDTH - CACHE_SET_NUM_LOG, + parameter PHYSICAL_ADDR_WIDTH = 64, + parameter COUNT_MAX = 2, + parameter COUNT_MAX_LOG = log2b(COUNT_MAX - 1) + 1, + parameter REQ_TAG_NUM = `REQ_TAG_NUM, + parameter REQ_TAG_NUM_LOG = log2b(REQ_TAG_NUM - 1), + parameter REORDER_BUFFER_WIDTH = (ICM_CACHE_TYPE == `CACHE_TYPE_MTT) ? CACHE_ENTRY_WIDTH * 2 + COUNT_MAX_LOG : CACHE_ENTRY_WIDTH + COUNT_MAX_LOG +) +( + input wire clk, + input wire rst, + +//Request channels + input wire SQ_cxt_req_valid, + input wire [`CXT_CMD_HEAD_WIDTH + `MAX_REQ_TAG_NUM_LOG - 1 : 0] SQ_cxt_req_head, + input wire [`CXT_CMD_DATA_WIDTH - 1 : 0] SQ_cxt_req_data, + output wire SQ_cxt_req_ready, + + input wire TX_REQ_cxt_req_valid, + input wire [`CXT_CMD_HEAD_WIDTH + `MAX_REQ_TAG_NUM_LOG - 1 : 0] TX_REQ_cxt_req_head, + input wire [`CXT_CMD_DATA_WIDTH - 1 : 0] TX_REQ_cxt_req_data, + output wire TX_REQ_cxt_req_ready, + + input wire RX_REQ_cxt_req_valid, + input wire [`CXT_CMD_HEAD_WIDTH + `MAX_REQ_TAG_NUM_LOG - 1 : 0] RX_REQ_cxt_req_head, + input wire [`CXT_CMD_DATA_WIDTH - 1 : 0] RX_REQ_cxt_req_data, + output wire RX_REQ_cxt_req_ready, + + input wire RX_RESP_cxt_req_valid, + input wire [`CXT_CMD_HEAD_WIDTH + `MAX_REQ_TAG_NUM_LOG - 1 : 0] RX_RESP_cxt_req_head, + input wire [`CXT_CMD_DATA_WIDTH - 1 : 0] RX_RESP_cxt_req_data, + output wire RX_RESP_cxt_req_ready, + +//Response channels + output wire SQ_cxt_rsp_valid, + output wire [`CXT_RESP_HEAD_WIDTH + `MAX_REQ_TAG_NUM_LOG - 1 : 0] SQ_cxt_rsp_head, + output wire [`CXT_RESP_DATA_WIDTH - 1 : 0] SQ_cxt_rsp_data, + input wire SQ_cxt_rsp_ready, + + output wire TX_REQ_cxt_rsp_valid, + output wire [`CXT_RESP_HEAD_WIDTH + `MAX_REQ_TAG_NUM_LOG - 1 : 0] TX_REQ_cxt_rsp_head, + output wire [`CXT_RESP_DATA_WIDTH - 1 : 0] TX_REQ_cxt_rsp_data, + input wire TX_REQ_cxt_rsp_ready, + + output wire RX_REQ_cxt_rsp_valid, + output wire [`CXT_RESP_HEAD_WIDTH + `MAX_REQ_TAG_NUM_LOG - 1 : 0] RX_REQ_cxt_rsp_head, + output wire [`CXT_RESP_DATA_WIDTH - 1 : 0] RX_REQ_cxt_rsp_data, + input wire RX_REQ_cxt_rsp_ready, + + output wire RX_RESP_cxt_rsp_valid, + output wire [`CXT_RESP_HEAD_WIDTH + `MAX_REQ_TAG_NUM_LOG - 1 : 0] RX_RESP_cxt_rsp_head, + output wire [`CXT_RESP_DATA_WIDTH - 1 : 0] RX_RESP_cxt_rsp_data, + input wire RX_RESP_cxt_rsp_ready, + +//Interface with QPCCache + output wire qpc_icm_mapping_lookup_valid, + output wire [log2b(`ICM_ENTRY_NUM_QPC - 1) - 1 : 0] qpc_icm_mapping_lookup_head, + input wire qpc_icm_mapping_lookup_ready, + + input wire qpc_icm_mapping_rsp_valid, + input wire [ICM_ADDR_WIDTH - 1 : 0] qpc_icm_mapping_rsp_icm_addr, + input wire [PHYSICAL_ADDR_WIDTH - 1 : 0] qpc_icm_mapping_rsp_phy_addr, + output wire qpc_icm_mapping_rsp_ready, + + output wire qpc_get_req_valid, + output wire [COUNT_MAX_LOG * 2 + `MAX_REQ_TAG_NUM_LOG + PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH - 1 : 0] qpc_get_req_head, + input wire qpc_get_req_ready, + + input wire qpc_get_rsp_valid, + input wire [COUNT_MAX_LOG * 2 + `MAX_REQ_TAG_NUM_LOG + PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH - 1 : 0] qpc_get_rsp_head, + input wire [`CACHE_ENTRY_WIDTH_QPC - 1 : 0] qpc_get_rsp_data, + output wire qpc_get_rsp_ready, + +//Interface with CQCCache + output wire cqc_icm_mapping_lookup_valid, + output wire [log2b(`ICM_ENTRY_NUM_CQC - 1) - 1 : 0] cqc_icm_mapping_lookup_head, + input wire cqc_icm_mapping_lookup_ready, + + input wire cqc_icm_mapping_rsp_valid, + input wire [ICM_ADDR_WIDTH - 1 : 0] cqc_icm_mapping_rsp_icm_addr, + input wire [PHYSICAL_ADDR_WIDTH - 1 : 0] cqc_icm_mapping_rsp_phy_addr, + output wire cqc_icm_mapping_rsp_ready, + + output wire cqc_get_req_valid, + output wire [COUNT_MAX_LOG * 2 + `MAX_REQ_TAG_NUM_LOG + PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH - 1 : 0] cqc_get_req_head, + input wire cqc_get_req_ready, + + input wire cqc_get_rsp_valid, + input wire [COUNT_MAX_LOG * 2 + `MAX_REQ_TAG_NUM_LOG + PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH - 1 : 0] cqc_get_rsp_head, + input wire [`CACHE_ENTRY_WIDTH_CQC - 1 : 0] cqc_get_rsp_data, + output wire cqc_get_rsp_ready, + +//Interface with EQCCache + output wire eqc_icm_mapping_lookup_valid, + output wire [log2b(`ICM_ENTRY_NUM_EQC - 1) - 1 : 0] eqc_icm_mapping_lookup_head, + input wire eqc_icm_mapping_lookup_ready, + + input wire eqc_icm_mapping_rsp_valid, + input wire [ICM_ADDR_WIDTH - 1 : 0] eqc_icm_mapping_rsp_icm_addr, + input wire [PHYSICAL_ADDR_WIDTH - 1 : 0] eqc_icm_mapping_rsp_phy_addr, + output wire eqc_icm_mapping_rsp_ready, + + output wire eqc_get_req_valid, + output wire [COUNT_MAX_LOG * 2 + `MAX_REQ_TAG_NUM_LOG + PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH - 1 : 0] eqc_get_req_head, + input wire eqc_get_req_ready, + + input wire eqc_get_rsp_valid, + input wire [COUNT_MAX_LOG * 2 + `MAX_REQ_TAG_NUM_LOG + PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH - 1 : 0] eqc_get_rsp_head, + input wire [`CACHE_ENTRY_WIDTH_EQC - 1 : 0] eqc_get_rsp_data, + output wire eqc_get_rsp_ready +); + +/*------------------------------------------- Input/Output Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Macros Definition : Begin ---------------------------------------*/ +/*------------------------------------------- Local Macros Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Variables Definition : Begin ------------------------------------*/ +wire cxt_req_valid; +wire [`CXT_CMD_HEAD_WIDTH + `MAX_REQ_TAG_NUM_LOG - 1 : 0] cxt_req_head; +wire [`CXT_CMD_DATA_WIDTH - 1 : 0] cxt_req_data; +wire cxt_req_ready; + +wire cxt_combine_valid; +wire [`CXT_RESP_HEAD_WIDTH + `MAX_REQ_TAG_NUM_LOG - 1 : 0] cxt_combine_head; +wire [`CXT_RESP_DATA_WIDTH - 1 : 0] cxt_combine_data; +wire cxt_combine_ready; + +wire qpc_staged_buffer_wea; +wire [`MAX_REQ_TAG_NUM_LOG - 1 : 0] qpc_staged_buffer_addra; +wire [`CACHE_ENTRY_WIDTH_QPC - 1 : 0] qpc_staged_buffer_dina; +wire [`MAX_REQ_TAG_NUM_LOG - 1 : 0] qpc_staged_buffer_addrb; +wire [`CACHE_ENTRY_WIDTH_QPC - 1 : 0] qpc_staged_buffer_doutb; + +wire cqc_staged_buffer_wea; +wire [`MAX_REQ_TAG_NUM_LOG - 1 : 0] cqc_staged_buffer_addra; +wire [`CACHE_ENTRY_WIDTH_CQC - 1 : 0] cqc_staged_buffer_dina; +wire [`MAX_REQ_TAG_NUM_LOG - 1 : 0] cqc_staged_buffer_addrb; +wire [`CACHE_ENTRY_WIDTH_CQC - 1 : 0] cqc_staged_buffer_doutb; + +wire tag_qpn_mapping_table_wea; +wire [`MAX_REQ_TAG_NUM_LOG - 1 : 0] tag_qpn_mapping_table_addra; +wire [`QP_NUM_LOG - 1 : 0] tag_qpn_mapping_table_dina; +wire [`MAX_REQ_TAG_NUM_LOG - 1 : 0] tag_qpn_mapping_table_addrb; +wire [`QP_NUM_LOG - 1 : 0] tag_qpn_mapping_table_doutb; +/*------------------------------------------- Local Variables Definition : End --------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : Begin ---------------------------------------*/ +HWAccCMCtl_Thread_1 +#( + .ICM_CACHE_TYPE ( ICM_CACHE_TYPE ), + .ICM_PAGE_NUM ( ICM_PAGE_NUM ), + + .ICM_ENTRY_NUM ( ICM_ENTRY_NUM ), + + .ICM_SLOT_SIZE ( ICM_SLOT_SIZE ), + .ICM_ADDR_WIDTH ( ICM_ADDR_WIDTH ), + + .CACHE_ADDR_WIDTH ( CACHE_ADDR_WIDTH ), + .CACHE_ENTRY_WIDTH ( CACHE_ENTRY_WIDTH ), + .CACHE_SET_NUM ( CACHE_SET_NUM ), + + .CACHE_OFFSET_WIDTH ( CACHE_OFFSET_WIDTH ), + .CACHE_TAG_WIDTH ( CACHE_TAG_WIDTH ), + .PHYSICAL_ADDR_WIDTH ( PHYSICAL_ADDR_WIDTH ), + .COUNT_MAX ( COUNT_MAX ), + + .REQ_TAG_NUM ( REQ_TAG_NUM ), + + .REORDER_BUFFER_WIDTH ( REORDER_BUFFER_WIDTH ) +) +HWAccCMCtl_Thread_1_Inst +( + .clk ( clk ), + .rst ( rst ), + + .SQ_cxt_req_valid ( SQ_cxt_req_valid ), + .SQ_cxt_req_head ( SQ_cxt_req_head ), + .SQ_cxt_req_data ( SQ_cxt_req_data ), + .SQ_cxt_req_ready ( SQ_cxt_req_ready ), + + .TX_REQ_cxt_req_valid ( TX_REQ_cxt_req_valid ), + .TX_REQ_cxt_req_head ( TX_REQ_cxt_req_head ), + .TX_REQ_cxt_req_data ( TX_REQ_cxt_req_data ), + .TX_REQ_cxt_req_ready ( TX_REQ_cxt_req_ready ), + + .RX_REQ_cxt_req_valid ( RX_REQ_cxt_req_valid ), + .RX_REQ_cxt_req_head ( RX_REQ_cxt_req_head ), + .RX_REQ_cxt_req_data ( RX_REQ_cxt_req_data ), + .RX_REQ_cxt_req_ready ( RX_REQ_cxt_req_ready ), + + .RX_RESP_cxt_req_valid ( RX_RESP_cxt_req_valid ), + .RX_RESP_cxt_req_head ( RX_RESP_cxt_req_head ), + .RX_RESP_cxt_req_data ( RX_RESP_cxt_req_data ), + .RX_RESP_cxt_req_ready ( RX_RESP_cxt_req_ready ), + + .cxt_req_valid ( cxt_req_valid ), + .cxt_req_head ( cxt_req_head ), + .cxt_req_data ( cxt_req_data ), + .cxt_req_ready ( cxt_req_ready ), + + .tag_qpn_mapping_table_wen ( tag_qpn_mapping_table_wea ), + .tag_qpn_mapping_table_addr ( tag_qpn_mapping_table_addra ), + .tag_qpn_mapping_table_din ( tag_qpn_mapping_table_dina ) +); + +HWAccCMCtl_Thread_2 +#( + .ICM_CACHE_TYPE ( ICM_CACHE_TYPE ), + .ICM_PAGE_NUM ( ICM_PAGE_NUM ), + + .ICM_ENTRY_NUM ( `ICM_ENTRY_NUM_QPC ), + + .ICM_SLOT_SIZE ( ICM_SLOT_SIZE ), + .ICM_ADDR_WIDTH ( ICM_ADDR_WIDTH ), + + .CACHE_ADDR_WIDTH ( CACHE_ADDR_WIDTH ), + .CACHE_ENTRY_WIDTH ( CACHE_ENTRY_WIDTH ), + .CACHE_SET_NUM ( CACHE_SET_NUM ), + + .CACHE_OFFSET_WIDTH ( CACHE_OFFSET_WIDTH ), + .CACHE_TAG_WIDTH ( CACHE_TAG_WIDTH ), + .PHYSICAL_ADDR_WIDTH ( PHYSICAL_ADDR_WIDTH ), + .COUNT_MAX ( COUNT_MAX ), + + .REQ_TAG_NUM ( REQ_TAG_NUM ), + + .REORDER_BUFFER_WIDTH ( REORDER_BUFFER_WIDTH ) +) +HWAccCMCtl_Thread_2_Inst +( + .clk ( clk ), + .rst ( rst ), + + .cxt_req_valid ( cxt_req_valid ), + .cxt_req_head ( cxt_req_head ), + .cxt_req_data ( cxt_req_data ), + .cxt_req_ready ( cxt_req_ready ), + + .icm_mapping_lookup_valid ( qpc_icm_mapping_lookup_valid ), + .icm_mapping_lookup_head ( qpc_icm_mapping_lookup_head ), + .icm_mapping_lookup_ready ( qpc_icm_mapping_lookup_ready ), + + .icm_mapping_rsp_valid ( qpc_icm_mapping_rsp_valid ), + .icm_mapping_rsp_icm_addr ( qpc_icm_mapping_rsp_icm_addr ), + .icm_mapping_rsp_phy_addr ( qpc_icm_mapping_rsp_phy_addr ), + .icm_mapping_rsp_ready ( qpc_icm_mapping_rsp_ready ), + + .qpc_get_req_valid ( qpc_get_req_valid ), + .qpc_get_req_head ( qpc_get_req_head ), + .qpc_get_req_ready ( qpc_get_req_ready ) +); + +HWAccCMCtl_Thread_3 +#( + .ICM_CACHE_TYPE ( ICM_CACHE_TYPE ), + .ICM_PAGE_NUM ( ICM_PAGE_NUM ), + + .ICM_ENTRY_NUM ( `ICM_ENTRY_NUM_CQC ), + + .ICM_SLOT_SIZE ( ICM_SLOT_SIZE ), + .ICM_ADDR_WIDTH ( ICM_ADDR_WIDTH ), + + .CACHE_ADDR_WIDTH ( CACHE_ADDR_WIDTH ), + .CACHE_ENTRY_WIDTH ( `CACHE_ENTRY_WIDTH_QPC ), + .CACHE_SET_NUM ( CACHE_SET_NUM ), + + .CACHE_OFFSET_WIDTH ( CACHE_OFFSET_WIDTH ), + .CACHE_TAG_WIDTH ( CACHE_TAG_WIDTH ), + .PHYSICAL_ADDR_WIDTH ( PHYSICAL_ADDR_WIDTH ), + .COUNT_MAX ( COUNT_MAX ), + + .REQ_TAG_NUM ( REQ_TAG_NUM ), + + .REORDER_BUFFER_WIDTH ( REORDER_BUFFER_WIDTH ) +) +HWAccCMCtl_Thread_3_Inst +( + .clk ( clk ), + .rst ( rst ), + + .qpc_get_rsp_valid ( qpc_get_rsp_valid ), + .qpc_get_rsp_head ( qpc_get_rsp_head ), + .qpc_get_rsp_data ( qpc_get_rsp_data ), + .qpc_get_rsp_ready ( qpc_get_rsp_ready ), + + .icm_mapping_lookup_valid ( cqc_icm_mapping_lookup_valid ), + .icm_mapping_lookup_head ( cqc_icm_mapping_lookup_head ), + .icm_mapping_lookup_ready ( cqc_icm_mapping_lookup_ready ), + + .icm_mapping_rsp_valid ( cqc_icm_mapping_rsp_valid ), + .icm_mapping_rsp_icm_addr ( cqc_icm_mapping_rsp_icm_addr ), + .icm_mapping_rsp_phy_addr ( cqc_icm_mapping_rsp_phy_addr ), + .icm_mapping_rsp_ready ( cqc_icm_mapping_rsp_ready ), + + .qpc_buffer_wen ( qpc_staged_buffer_wea ), + .qpc_buffer_addr ( qpc_staged_buffer_addra ), + .qpc_buffer_din ( qpc_staged_buffer_dina ), + + .cqc_get_req_valid ( cqc_get_req_valid ), + .cqc_get_req_head ( cqc_get_req_head ), + .cqc_get_req_ready ( cqc_get_req_ready ) +); + +HWAccCMCtl_Thread_4 +#( + .ICM_CACHE_TYPE ( ICM_CACHE_TYPE ), + .ICM_PAGE_NUM ( ICM_PAGE_NUM ), + + .ICM_ENTRY_NUM ( `ICM_ENTRY_NUM_EQC ), + + .ICM_SLOT_SIZE ( ICM_SLOT_SIZE ), + .ICM_ADDR_WIDTH ( ICM_ADDR_WIDTH ), + + .CACHE_ADDR_WIDTH ( CACHE_ADDR_WIDTH ), + .CACHE_ENTRY_WIDTH ( `CACHE_ENTRY_WIDTH_CQC ), + .CACHE_SET_NUM ( CACHE_SET_NUM ), + + .CACHE_OFFSET_WIDTH ( CACHE_OFFSET_WIDTH ), + .CACHE_TAG_WIDTH ( CACHE_TAG_WIDTH ), + .PHYSICAL_ADDR_WIDTH ( PHYSICAL_ADDR_WIDTH ), + .COUNT_MAX ( COUNT_MAX ), + + .REQ_TAG_NUM ( REQ_TAG_NUM ), + + .REORDER_BUFFER_WIDTH ( REORDER_BUFFER_WIDTH ) +) +HWAccCMCtl_Thread_4_Inst +( + .clk ( clk ), + .rst ( rst ), + + .cqc_get_rsp_valid ( cqc_get_rsp_valid ), + .cqc_get_rsp_head ( cqc_get_rsp_head ), + .cqc_get_rsp_data ( cqc_get_rsp_data ), + .cqc_get_rsp_ready ( cqc_get_rsp_ready ), + + .icm_mapping_lookup_valid ( eqc_icm_mapping_lookup_valid ), + .icm_mapping_lookup_head ( eqc_icm_mapping_lookup_head ), + .icm_mapping_lookup_ready ( eqc_icm_mapping_lookup_ready ), + + .icm_mapping_rsp_valid ( eqc_icm_mapping_rsp_valid ), + .icm_mapping_rsp_icm_addr ( eqc_icm_mapping_rsp_icm_addr ), + .icm_mapping_rsp_phy_addr ( eqc_icm_mapping_rsp_phy_addr ), + .icm_mapping_rsp_ready ( eqc_icm_mapping_rsp_ready ), + + .cqc_buffer_wen ( cqc_staged_buffer_wea ), + .cqc_buffer_addr ( cqc_staged_buffer_addra ), + .cqc_buffer_din ( cqc_staged_buffer_dina ), + + .eqc_get_req_valid ( eqc_get_req_valid ), + .eqc_get_req_head ( eqc_get_req_head ), + .eqc_get_req_ready ( eqc_get_req_ready ) +); + +HWAccCMCtl_Thread_5 +#( + .ICM_CACHE_TYPE ( ICM_CACHE_TYPE ), + .ICM_PAGE_NUM ( ICM_PAGE_NUM ), + + .ICM_ENTRY_NUM ( ICM_ENTRY_NUM ), + + .ICM_SLOT_SIZE ( ICM_SLOT_SIZE ), + .ICM_ADDR_WIDTH ( ICM_ADDR_WIDTH ), + + .CACHE_ADDR_WIDTH ( CACHE_ADDR_WIDTH ), + .CACHE_ENTRY_WIDTH ( `CACHE_ENTRY_WIDTH_CQC ), + .CACHE_SET_NUM ( CACHE_SET_NUM ), + + .CACHE_OFFSET_WIDTH ( CACHE_OFFSET_WIDTH ), + .CACHE_TAG_WIDTH ( CACHE_TAG_WIDTH ), + .PHYSICAL_ADDR_WIDTH ( PHYSICAL_ADDR_WIDTH ), + .COUNT_MAX ( COUNT_MAX ), + + .REQ_TAG_NUM ( REQ_TAG_NUM ), + + .REORDER_BUFFER_WIDTH ( REORDER_BUFFER_WIDTH ) +) +HWAccCMCtl_Thread_5_Inst +( + .clk ( clk ), + .rst ( rst ), + + .eqc_get_rsp_valid ( eqc_get_rsp_valid ), + .eqc_get_rsp_head ( eqc_get_rsp_head ), + .eqc_get_rsp_data ( eqc_get_rsp_data ), + .eqc_get_rsp_ready ( eqc_get_rsp_ready ), + + .qpc_buffer_addr ( qpc_staged_buffer_addrb ), + .qpc_buffer_dout ( qpc_staged_buffer_doutb ), + + .cqc_buffer_addr ( cqc_staged_buffer_addrb ), + .cqc_buffer_dout ( cqc_staged_buffer_doutb ), + + .cxt_combine_valid ( cxt_combine_valid ), + .cxt_combine_head ( cxt_combine_head ), + .cxt_combine_data ( cxt_combine_data ), + .cxt_combine_ready ( cxt_combine_ready ) +); + +HWAccCMCtl_Thread_6 +#( + .ICM_CACHE_TYPE ( ICM_CACHE_TYPE ), + .ICM_PAGE_NUM ( ICM_PAGE_NUM ), + + .ICM_ENTRY_NUM ( ICM_ENTRY_NUM ), + + .ICM_SLOT_SIZE ( ICM_SLOT_SIZE ), + .ICM_ADDR_WIDTH ( ICM_ADDR_WIDTH ), + + .CACHE_ADDR_WIDTH ( CACHE_ADDR_WIDTH ), + .CACHE_ENTRY_WIDTH ( CACHE_ENTRY_WIDTH ), + .CACHE_SET_NUM ( CACHE_SET_NUM ), + + .CACHE_OFFSET_WIDTH ( CACHE_OFFSET_WIDTH ), + .CACHE_TAG_WIDTH ( CACHE_TAG_WIDTH ), + .PHYSICAL_ADDR_WIDTH ( PHYSICAL_ADDR_WIDTH ), + .COUNT_MAX ( COUNT_MAX ), + + .REQ_TAG_NUM ( REQ_TAG_NUM ), + + .REORDER_BUFFER_WIDTH ( REORDER_BUFFER_WIDTH ) +) +HWAccCMCtl_Thread_6_Inst +( + .clk ( clk ), + .rst ( rst ), + + .cxt_combine_valid ( cxt_combine_valid ), + .cxt_combine_head ( cxt_combine_head ), + .cxt_combine_data ( cxt_combine_data ), + .cxt_combine_ready ( cxt_combine_ready ), + + .tag_qpn_mapping_table_addr ( tag_qpn_mapping_table_addrb ), + .tag_qpn_mapping_table_dout ( tag_qpn_mapping_table_doutb ), + + .SQ_cxt_rsp_valid ( SQ_cxt_rsp_valid ), + .SQ_cxt_rsp_head ( SQ_cxt_rsp_head ), + .SQ_cxt_rsp_data ( SQ_cxt_rsp_data ), + .SQ_cxt_rsp_ready ( SQ_cxt_rsp_ready ), + + .TX_REQ_cxt_rsp_valid ( TX_REQ_cxt_rsp_valid ), + .TX_REQ_cxt_rsp_head ( TX_REQ_cxt_rsp_head ), + .TX_REQ_cxt_rsp_data ( TX_REQ_cxt_rsp_data ), + .TX_REQ_cxt_rsp_ready ( TX_REQ_cxt_rsp_ready ), + + .RX_REQ_cxt_rsp_valid ( RX_REQ_cxt_rsp_valid ), + .RX_REQ_cxt_rsp_head ( RX_REQ_cxt_rsp_head ), + .RX_REQ_cxt_rsp_data ( RX_REQ_cxt_rsp_data ), + .RX_REQ_cxt_rsp_ready ( RX_REQ_cxt_rsp_ready ), + + .RX_RESP_cxt_rsp_valid ( RX_RESP_cxt_rsp_valid ), + .RX_RESP_cxt_rsp_head ( RX_RESP_cxt_rsp_head ), + .RX_RESP_cxt_rsp_data ( RX_RESP_cxt_rsp_data ), + .RX_RESP_cxt_rsp_ready ( RX_RESP_cxt_rsp_ready ) +); + +SRAM_SDP_Template #( + .RAM_WIDTH ( `CACHE_ENTRY_WIDTH_QPC ), + .RAM_DEPTH ( 256 ) +) +QPCStagedBuffer_Inst +( + .clk ( clk ), + .rst ( rst ), + + .wea ( qpc_staged_buffer_wea ), + .addra ( qpc_staged_buffer_addra ), + .dina ( qpc_staged_buffer_dina ), + + .addrb ( qpc_staged_buffer_addrb ), + .doutb ( qpc_staged_buffer_doutb ) +); + +SRAM_SDP_Template #( + .RAM_WIDTH ( `CACHE_ENTRY_WIDTH_CQC ), + .RAM_DEPTH ( 256 ) +) +CQCStagedBuffer_Inst +( + .clk ( clk ), + .rst ( rst ), + + .wea ( cqc_staged_buffer_wea ), + .addra ( cqc_staged_buffer_addra ), + .dina ( cqc_staged_buffer_dina ), + + .addrb ( cqc_staged_buffer_addrb ), + .doutb ( cqc_staged_buffer_doutb ) +); + +SRAM_SDP_Template #( + .RAM_WIDTH ( `QP_NUM_LOG ), + .RAM_DEPTH ( 256 ) //Tag per channel * 4 channels +) +TagQPNMappingTable_Inst +( + .clk ( clk ), + .rst ( rst ), + + .wea ( tag_qpn_mapping_table_wea ), + .addra ( tag_qpn_mapping_table_addra ), + .dina ( tag_qpn_mapping_table_dina ), + + .addrb ( tag_qpn_mapping_table_addrb ), + .doutb ( tag_qpn_mapping_table_doutb ) +); +/*------------------------------------------- Submodules Instatiation : End -----------------------------------------*/ + +/*------------------------------------------- State Machine Definition : Begin --------------------------------------*/ +/*------------------------------------------- State Machine Definition : End ----------------------------------------*/ + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ + +/*------------------------------------------- Local Macros Undef : Begin --------------------------------------------*/ +/*------------------------------------------- Local Macros Undef : End ----------------------------------------------*/ + +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/ICMMgt/CxtMgt/HWAccCMCtl/HWAccCMCtl_Thread_1.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/ICMMgt/CxtMgt/HWAccCMCtl/HWAccCMCtl_Thread_1.v new file mode 100644 index 0000000000000000000000000000000000000000..ee9187000317b2450fbf43372a1fe65f3097922f --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/ICMMgt/CxtMgt/HWAccCMCtl/HWAccCMCtl_Thread_1.v @@ -0,0 +1,292 @@ +/*------------------------------------------- Module Description : Begin ---------------------------------------------- +Name: HWAccCMCtl_Thread_1 +Author: YangFan +Function: Arbitrate from different Request Channels.. +--------------------------------------------- Module Decription : End -----------------------------------------------*/ + +/*------------------------------------------- Timescale Definition : Begin ------------------------------------------*/ +`timescale 1ns / 1ps +/*------------------------------------------- Timescale Definition : End --------------------------------------------*/ + +/*------------------------------------------- Included Files : Begin ------------------------------------------------*/ +`include "protocol_engine_def.vh" +/*------------------------------------------- Included Files : End --------------------------------------------------*/ + +/*------------------------------------------- Input/Output Definition : Begin ---------------------------------------*/ +module HWAccCMCtl_Thread_1 +#( + parameter ICM_CACHE_TYPE = `CACHE_TYPE_MTT, + parameter ICM_PAGE_NUM = `ICM_PAGE_NUM_MTT, + parameter ICM_PAGE_NUM_LOG = log2b(ICM_PAGE_NUM - 1), + parameter ICM_ENTRY_NUM = `ICM_ENTRY_NUM_MTT, + parameter ICM_ENTRY_NUM_LOG = log2b(ICM_ENTRY_NUM - 1), + parameter ICM_SLOT_SIZE = `ICM_SLOT_SIZE_MTT, + parameter ICM_ADDR_WIDTH = 64, + + parameter CACHE_ADDR_WIDTH = ICM_ADDR_WIDTH, + parameter CACHE_ENTRY_WIDTH = 256, + parameter CACHE_SET_NUM = 1024, + parameter CACHE_SET_NUM_LOG = log2b(CACHE_SET_NUM - 1), + parameter CACHE_OFFSET_WIDTH = log2b(CACHE_ENTRY_WIDTH / 8 - 1), + parameter CACHE_TAG_WIDTH = CACHE_ADDR_WIDTH - CACHE_OFFSET_WIDTH - CACHE_SET_NUM_LOG, + parameter PHYSICAL_ADDR_WIDTH = 64, + parameter COUNT_MAX = 2, + parameter COUNT_MAX_LOG = log2b(COUNT_MAX - 1) + 1, + parameter REQ_TAG_NUM = 32, + parameter REQ_TAG_NUM_LOG = log2b(REQ_TAG_NUM - 1), + parameter REORDER_BUFFER_WIDTH = (ICM_CACHE_TYPE == `CACHE_TYPE_MTT) ? CACHE_ENTRY_WIDTH * 2 + COUNT_MAX_LOG : CACHE_ENTRY_WIDTH + COUNT_MAX_LOG +) +( + input wire clk, + input wire rst, + +//Interface with RDMACore and QueueSubsystem + //Interface with SQMgt + input wire SQ_cxt_req_valid, + input wire [`CXT_CMD_HEAD_WIDTH + `MAX_REQ_TAG_NUM_LOG - 1 : 0] SQ_cxt_req_head, + input wire [`CXT_CMD_DATA_WIDTH - 1 : 0] SQ_cxt_req_data, + output wire SQ_cxt_req_ready, + + //Interface with RDMACore/RequesterCore/ReqTransCore + input wire TX_REQ_cxt_req_valid, + input wire [`CXT_CMD_HEAD_WIDTH + `MAX_REQ_TAG_NUM_LOG - 1 : 0] TX_REQ_cxt_req_head, + input wire [`CXT_CMD_DATA_WIDTH - 1 : 0] TX_REQ_cxt_req_data, + output wire TX_REQ_cxt_req_ready, + + //Interface with RDMACore/RequesterCore/RespRecvCore + input wire RX_REQ_cxt_req_valid, + input wire [`CXT_CMD_HEAD_WIDTH + `MAX_REQ_TAG_NUM_LOG - 1 : 0] RX_REQ_cxt_req_head, + input wire [`CXT_CMD_DATA_WIDTH - 1 : 0] RX_REQ_cxt_req_data, + output wire RX_REQ_cxt_req_ready, + + //Interface with RDMACore/ResponderCore/ReqRecvCore + input wire RX_RESP_cxt_req_valid, + input wire [`CXT_CMD_HEAD_WIDTH + `MAX_REQ_TAG_NUM_LOG - 1 : 0] RX_RESP_cxt_req_head, + input wire [`CXT_CMD_DATA_WIDTH - 1 : 0] RX_RESP_cxt_req_data, + output wire RX_RESP_cxt_req_ready, + +//Interface with HWAccCMCtl_Thread_2 + output wire cxt_req_valid, + output wire [`CXT_CMD_HEAD_WIDTH + `MAX_REQ_TAG_NUM_LOG - 1 : 0] cxt_req_head, + output wire [`CXT_CMD_DATA_WIDTH - 1 : 0] cxt_req_data, + input wire cxt_req_ready, + +//Interface with TagQPNMappingTable + output wire tag_qpn_mapping_table_wen, + output wire [`MAX_REQ_TAG_NUM_LOG - 1 : 0] tag_qpn_mapping_table_addr, + output wire [`QP_NUM_LOG - 1 : 0] tag_qpn_mapping_table_din +); +/*------------------------------------------- Input/Output Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Macros Definition : Begin ---------------------------------------*/ +`define SQ_CHNL 0 +`define TX_REQ_CHNL 1 +`define RX_REQ_CHNL 2 +`define RX_RESP_CHNL 3 + +`define REQ_TAG_OFFSET REQ_TAG_NUM_LOG - 1 : 0 +/*------------------------------------------- Local Macros Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Variables Definition : Begin ------------------------------------*/ +reg [2:0] last_sch_chnl; + +wire [`MAX_REQ_TAG_NUM_LOG - 1 : 0] req_tag; +/*------------------------------------------- Local Variables Definition : End --------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : Begin ---------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : End -----------------------------------------*/ + +/*------------------------------------------- State Machine Definition : Begin --------------------------------------*/ +reg [3:0] cur_state; +reg [3:0] next_state; + +parameter [3:0] IDLE_s = 4'd1, + SQ_s = 4'd2, + TX_REQ_s = 4'd3, + RX_REQ_s = 4'd4, + RX_RESP_s = 4'd5; + +always @(posedge clk or posedge rst) begin + if (rst) begin + cur_state <= IDLE_s; + end + else begin + cur_state <= next_state; + end +end + +always @(*) begin + case(cur_state) + IDLE_s: if(last_sch_chnl == `RX_RESP_CHNL) begin + if(SQ_cxt_req_valid) begin + next_state = SQ_s; + end + else if(TX_REQ_cxt_req_valid) begin + next_state = TX_REQ_s; + end + else if(RX_REQ_cxt_req_valid) begin + next_state = RX_REQ_s; + end + else if(RX_RESP_cxt_req_valid) begin + next_state = RX_RESP_s; + end + else begin + next_state = IDLE_s; + end + end + else if(last_sch_chnl == `SQ_CHNL) begin + if(TX_REQ_cxt_req_valid) begin + next_state = TX_REQ_s; + end + else if(RX_REQ_cxt_req_valid) begin + next_state = RX_REQ_s; + end + else if(RX_RESP_cxt_req_valid) begin + next_state = RX_RESP_s; + end + else if(SQ_cxt_req_valid) begin + next_state = SQ_s; + end + else begin + next_state = IDLE_s; + end + end + else if(last_sch_chnl == `TX_REQ_CHNL) begin + if(RX_REQ_cxt_req_valid) begin + next_state = RX_REQ_s; + end + else if(RX_RESP_cxt_req_valid) begin + next_state = RX_RESP_s; + end + else if(SQ_cxt_req_valid) begin + next_state = SQ_s; + end + else if(TX_REQ_cxt_req_valid) begin + next_state = TX_REQ_s; + end + else begin + next_state = IDLE_s; + end + end + else if(last_sch_chnl == `RX_REQ_CHNL) begin + if(RX_RESP_cxt_req_valid) begin + next_state = RX_RESP_s; + end + else if(SQ_cxt_req_valid) begin + next_state = SQ_s; + end + else if(TX_REQ_cxt_req_valid) begin + next_state = TX_REQ_s; + end + else if(RX_REQ_cxt_req_valid) begin + next_state = RX_REQ_s; + end + else begin + next_state = IDLE_s; + end + end + else begin + next_state = IDLE_s; + end + SQ_s: if(cxt_req_valid && cxt_req_ready) begin + next_state = IDLE_s; + end + else begin + next_state = SQ_s; + end + TX_REQ_s: if(cxt_req_valid && cxt_req_ready) begin + next_state = IDLE_s; + end + else begin + next_state = TX_REQ_s; + end + RX_REQ_s: if(cxt_req_valid && cxt_req_ready) begin + next_state = IDLE_s; + end + else begin + next_state = RX_REQ_s; + end + RX_RESP_s: if(cxt_req_valid && cxt_req_ready) begin + next_state = IDLE_s; + end + else begin + next_state = RX_RESP_s; + end + default: next_state = IDLE_s; + endcase +end +/*------------------------------------------- State Machine Definition : End ----------------------------------------*/ + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ +//-- last_sch_chnl -- +always @(posedge clk or posedge rst) begin + if (rst) begin + last_sch_chnl <= `RX_RESP_CHNL; + end + else if (cur_state == SQ_s && cxt_req_ready) begin + last_sch_chnl <= `SQ_CHNL; + end + else if (cur_state == TX_REQ_s && cxt_req_ready) begin + last_sch_chnl <= `TX_REQ_CHNL; + end + else if (cur_state == RX_REQ_s && cxt_req_ready) begin + last_sch_chnl <= `RX_REQ_CHNL; + end + else if (cur_state == RX_RESP_s && cxt_req_ready) begin + last_sch_chnl <= `RX_RESP_CHNL; + end + else begin + last_sch_chnl <= last_sch_chnl; + end +end + +//-- SQ_cxt_req_ready -- +assign SQ_cxt_req_ready = (cur_state == SQ_s) ? cxt_req_ready : 'd0; + +//-- TX_REQ_cxt_req_ready -- +assign TX_REQ_cxt_req_ready = (cur_state == TX_REQ_s) ? cxt_req_ready : 'd0; + +//-- RX_REQ_cxt_req_ready -- +assign RX_REQ_cxt_req_ready = (cur_state == RX_REQ_s) ? cxt_req_ready : 'd0; + +//-- RX_RESP_cxt_req_ready -- +assign RX_RESP_cxt_req_ready = (cur_state == RX_RESP_s) ? cxt_req_ready : 'd0; + +//-- req_tag -- +assign req_tag = (cur_state == SQ_s) ? {'d0, 2'b00, SQ_cxt_req_head[`REQ_TAG_OFFSET]} : + (cur_state == TX_REQ_s) ? {'d0, 2'b01, TX_REQ_cxt_req_head[`REQ_TAG_OFFSET]} : + (cur_state == RX_REQ_s) ? {'d0, 2'b10, RX_REQ_cxt_req_head[`REQ_TAG_OFFSET]} : + (cur_state == RX_RESP_s) ? {'d0, 2'b11, RX_RESP_cxt_req_head[`REQ_TAG_OFFSET]} : 'd0; + +//-- cxt_req_valid -- +//-- cxt_req_head -- +//-- cxt_req_data -- +assign cxt_req_valid = (cur_state == SQ_s) ? 'd1: + (cur_state == TX_REQ_s) ? 'd1 : + (cur_state == RX_REQ_s) ? 'd1 : + (cur_state == RX_RESP_s) ? 'd1 : 'd0; +assign cxt_req_head = (cur_state == SQ_s) ? {SQ_cxt_req_head[`CXT_CMD_HEAD_WIDTH + `MAX_REQ_TAG_NUM_LOG - 1 : `MAX_REQ_TAG_NUM_LOG], req_tag} : + (cur_state == TX_REQ_s) ? {TX_REQ_cxt_req_head[`CXT_CMD_HEAD_WIDTH + `MAX_REQ_TAG_NUM_LOG - 1 : `MAX_REQ_TAG_NUM_LOG], req_tag} : + (cur_state == RX_REQ_s) ? {RX_REQ_cxt_req_head[`CXT_CMD_HEAD_WIDTH + `MAX_REQ_TAG_NUM_LOG - 1 : `MAX_REQ_TAG_NUM_LOG], req_tag} : + (cur_state == RX_RESP_s) ? {RX_RESP_cxt_req_head[`CXT_CMD_HEAD_WIDTH + `MAX_REQ_TAG_NUM_LOG - 1 : `MAX_REQ_TAG_NUM_LOG], req_tag} : 'd0; +assign cxt_req_data = (cur_state == SQ_s) ? SQ_cxt_req_data : + (cur_state == TX_REQ_s) ? TX_REQ_cxt_req_data : + (cur_state == RX_REQ_s) ? RX_REQ_cxt_req_data : + (cur_state == RX_RESP_s) ? RX_RESP_cxt_req_data : 'd0; + +//-- tag_qpn_mapping_table_wen -- +//-- tag_qpn_mapping_table_addr -- +//-- tag_qpn_mapping_table_din -- +assign tag_qpn_mapping_table_wen = (cur_state == SQ_s || cur_state == TX_REQ_s || cur_state == RX_REQ_s || cur_state == RX_RESP_s) ? 'd1 : 'd0; +assign tag_qpn_mapping_table_addr = req_tag; +assign tag_qpn_mapping_table_din = (cur_state == SQ_s) ? SQ_cxt_req_head[`QP_NUM_LOG + 4 + `MAX_REQ_TAG_NUM_LOG - 1 : `MAX_REQ_TAG_NUM_LOG + 4] : + (cur_state == TX_REQ_s) ? TX_REQ_cxt_req_head[`QP_NUM_LOG + 4 + `MAX_REQ_TAG_NUM_LOG - 1 : `MAX_REQ_TAG_NUM_LOG + 4] : + (cur_state == RX_REQ_s) ? RX_REQ_cxt_req_head[`QP_NUM_LOG + 4 + `MAX_REQ_TAG_NUM_LOG - 1 : `MAX_REQ_TAG_NUM_LOG + 4] : + (cur_state == RX_RESP_s) ? RX_RESP_cxt_req_head[`QP_NUM_LOG + 4 + `MAX_REQ_TAG_NUM_LOG - 1 : `MAX_REQ_TAG_NUM_LOG + 4] : 'd0; +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ + +/*------------------------------------------- Local Macros Undef : Begin --------------------------------------------*/ +/*------------------------------------------- Local Macros Undef : End ----------------------------------------------*/ + +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/ICMMgt/CxtMgt/HWAccCMCtl/HWAccCMCtl_Thread_2.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/ICMMgt/CxtMgt/HWAccCMCtl/HWAccCMCtl_Thread_2.v new file mode 100644 index 0000000000000000000000000000000000000000..a5a967d1b5a3dc30bb07d9960f2ece85c200b459 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/ICMMgt/CxtMgt/HWAccCMCtl/HWAccCMCtl_Thread_2.v @@ -0,0 +1,216 @@ +/*------------------------------------------- Module Description : Begin ---------------------------------------------- +Name: HWAccCMCtl_Thread_2 +Author: YangFan +Function: Manage Hardware QPC access. +--------------------------------------------- Module Decription : End -----------------------------------------------*/ + +/*------------------------------------------- Timescale Definition : Begin ------------------------------------------*/ +`timescale 1ns / 1ps +/*------------------------------------------- Timescale Definition : End --------------------------------------------*/ + +/*------------------------------------------- Included Files : Begin ------------------------------------------------*/ +`include "protocol_engine_def.vh" +/*------------------------------------------- Included Files : End --------------------------------------------------*/ + +/*------------------------------------------- Input/Output Definition : Begin ---------------------------------------*/ +module HWAccCMCtl_Thread_2 +#( + parameter ICM_CACHE_TYPE = `CACHE_TYPE_MTT, + parameter ICM_PAGE_NUM = `ICM_PAGE_NUM_MTT, + parameter ICM_PAGE_NUM_LOG = log2b(ICM_PAGE_NUM - 1), + parameter ICM_ENTRY_NUM = `ICM_ENTRY_NUM_MTT, + parameter ICM_ENTRY_NUM_LOG = log2b(ICM_ENTRY_NUM - 1), + parameter ICM_SLOT_SIZE = `ICM_SLOT_SIZE_MTT, + parameter ICM_ADDR_WIDTH = 64, + + parameter CACHE_ADDR_WIDTH = ICM_ADDR_WIDTH, + parameter CACHE_ENTRY_WIDTH = 256, + parameter CACHE_SET_NUM = 1024, + parameter CACHE_SET_NUM_LOG = log2b(CACHE_SET_NUM - 1), + parameter CACHE_OFFSET_WIDTH = log2b(CACHE_ENTRY_WIDTH / 8 - 1), + parameter CACHE_TAG_WIDTH = CACHE_ADDR_WIDTH - CACHE_OFFSET_WIDTH - CACHE_SET_NUM_LOG, + parameter PHYSICAL_ADDR_WIDTH = 64, + parameter COUNT_MAX = 2, + parameter COUNT_MAX_LOG = log2b(COUNT_MAX - 1) + 1, + parameter REQ_TAG_NUM = 32, + parameter REQ_TAG_NUM_LOG = log2b(REQ_TAG_NUM - 1), + parameter REORDER_BUFFER_WIDTH = (ICM_CACHE_TYPE == `CACHE_TYPE_MTT) ? CACHE_ENTRY_WIDTH * 2 + COUNT_MAX_LOG : CACHE_ENTRY_WIDTH + COUNT_MAX_LOG +) +( + input wire clk, + input wire rst, + +//ICM Get Req Interface + input wire cxt_req_valid, + input wire [`CXT_CMD_HEAD_WIDTH + `MAX_REQ_TAG_NUM_LOG - 1 : 0] cxt_req_head, + input wire [`CXT_CMD_DATA_WIDTH - 1 : 0] cxt_req_data, + output wire cxt_req_ready, + +//Mapping Lookup Interface + output wire icm_mapping_lookup_valid, + output wire [ICM_ENTRY_NUM_LOG - 1 : 0] icm_mapping_lookup_head, + input wire icm_mapping_lookup_ready, + + input wire icm_mapping_rsp_valid, + input wire [ICM_ADDR_WIDTH - 1 : 0] icm_mapping_rsp_icm_addr, + input wire [PHYSICAL_ADDR_WIDTH - 1 : 0] icm_mapping_rsp_phy_addr, + output wire icm_mapping_rsp_ready, + +//ICM Get Interface + output wire qpc_get_req_valid, + output wire [COUNT_MAX_LOG * 2 + `MAX_REQ_TAG_NUM_LOG + PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH - 1 : 0] qpc_get_req_head, + input wire qpc_get_req_ready + +); +/*------------------------------------------- Input/Output Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Macros Definition : Begin ---------------------------------------*/ +`define CXT_CMD_TYPE_OFFSET 63:60 +`define CXT_CMD_OPCODE_OFFSET 59:56 +`define CXT_CMD_QPN_OFFSET 12+`QP_NUM_LOG-1:12 +`define CXT_CMD_TAG_OFFSET 7:0 +/*------------------------------------------- Local Macros Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Variables Definition : Begin ------------------------------------*/ +reg [`CXT_CMD_HEAD_WIDTH + `MAX_REQ_TAG_NUM_LOG - 1 : 0] cxt_req_head_diff; + +wire [COUNT_MAX_LOG - 1 : 0] count_total; +wire [COUNT_MAX_LOG - 1 : 0] count_index; + +reg [`MAX_REQ_TAG_NUM_LOG - 1 : 0] req_tag; +reg [PHYSICAL_ADDR_WIDTH - 1 : 0] phy_addr; +reg [ICM_ADDR_WIDTH - 1 : 0] icm_addr; +/*------------------------------------------- Local Variables Definition : End --------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : Begin ---------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : End -----------------------------------------*/ + +/*------------------------------------------- State Machine Definition : Begin --------------------------------------*/ +reg [2:0] cur_state; +reg [2:0] next_state; + +parameter [2:0] IDLE_s = 3'd1, + ADDR_REQ_s = 3'd2, + ADDR_RSP_s = 3'd3, + QPC_GET_s = 3'd4; + +always @(posedge clk or posedge rst) begin + if(rst) begin + cur_state <= IDLE_s; + end + else begin + cur_state <= next_state; + end +end + +always @(*) begin + case(cur_state) + IDLE_s: if(cxt_req_valid) begin + next_state = ADDR_REQ_s; + end + else begin + next_state = IDLE_s; + end + ADDR_REQ_s: if(icm_mapping_lookup_valid && icm_mapping_lookup_ready) begin + next_state = ADDR_RSP_s; + end + else begin + next_state = ADDR_REQ_s; + end + ADDR_RSP_s: if(icm_mapping_rsp_valid) begin + next_state = QPC_GET_s; + end + else begin + next_state = ADDR_RSP_s; + end + QPC_GET_s: if(qpc_get_req_valid && qpc_get_req_ready) begin + next_state = IDLE_s; + end + else begin + next_state = QPC_GET_s; + end + default: next_state = IDLE_s; + endcase +end + +/*------------------------------------------- State Machine Definition : End ----------------------------------------*/ + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ +//-- count_total -- +//-- count_index -- +assign count_total = {{(COUNT_MAX_LOG - 1){1'b0}}, 1'b1}; //For Cxt Req, only one sub-req +assign count_index = {{(COUNT_MAX_LOG - 1){1'b0}}, 1'b0}; + +//-- req_tag -- +//-- phy_addr -- +//-- icm_addr -- +always @(posedge clk or posedge rst) begin + if (rst) begin + req_tag <= 'd0; + phy_addr <= 'd0; + icm_addr <= 'd0; + end + else if (cur_state == ADDR_RSP_s && icm_mapping_rsp_valid) begin + req_tag <= {'d0, cxt_req_head_diff[`CXT_CMD_TAG_OFFSET]}; + phy_addr <= icm_mapping_rsp_phy_addr; + icm_addr <= icm_mapping_rsp_icm_addr; + end + else begin + req_tag <= req_tag; + phy_addr <= phy_addr; + icm_addr <= icm_addr; + end +end + +//-- cxt_req_ready -- +assign cxt_req_ready = (cur_state == IDLE_s) ? 'd1 : 'd0; + +//-- icm_mapping_rsp_ready -- +assign icm_mapping_rsp_ready = (cur_state == ADDR_RSP_s) ? 'd1 : 'd0; + +//-- icm_mapping_lookup_valid -- +//-- icm_mapping_lookup_head -- +assign icm_mapping_lookup_valid = (cur_state == ADDR_REQ_s) ? 'd1 : 'd0; +assign icm_mapping_lookup_head = (cur_state == ADDR_REQ_s) ? cxt_req_head_diff[`CXT_CMD_QPN_OFFSET] : 'd0; + +//-- qpc_get_req_valid -- +//-- qpc_get_req_head -- +assign qpc_get_req_valid = (cur_state == QPC_GET_s) ? 'd1 : 'd0; +assign qpc_get_req_head = (cur_state == QPC_GET_s) ? {count_total, count_index, req_tag, phy_addr, icm_addr} : 'd0; + +//-- cxt_req_head_diff -- +always @(posedge clk or posedge rst) begin + if (rst) begin + cxt_req_head_diff <= 'd0; + end + else if (cur_state == IDLE_s && cxt_req_valid) begin + cxt_req_head_diff <= cxt_req_head; + end + + else begin + cxt_req_head_diff <= cxt_req_head_diff; + end +end +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ + +/*------------------------------------------- Local Macros Undef : Begin --------------------------------------------*/ +`undef CXT_CMD_TYPE_OFFSET +`undef CXT_CMD_OPCODE_OFFSET +`undef CXT_CMD_QPN_OFFSET +`undef CXT_CMD_TAG_OFFSET +/*------------------------------------------- Local Macros Undef : End ----------------------------------------------*/ + +`ifdef ILA_ON + +ila_hw_acc_cm_thread_2 ila_hw_acc_cm_thread_2_inst( + .clk(clk), + + .probe0(qpc_get_req_valid), + .probe1(qpc_get_req_head), + .probe2(qpc_get_req_ready) +); + +`endif + +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/ICMMgt/CxtMgt/HWAccCMCtl/HWAccCMCtl_Thread_3.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/ICMMgt/CxtMgt/HWAccCMCtl/HWAccCMCtl_Thread_3.v new file mode 100644 index 0000000000000000000000000000000000000000..ed71bbf0426eaad7267be2d268fa87240f2565e3 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/ICMMgt/CxtMgt/HWAccCMCtl/HWAccCMCtl_Thread_3.v @@ -0,0 +1,265 @@ +/*------------------------------------------- Module Description : Begin ---------------------------------------------- +Name: HWAccCMCtl_Thread_3 +Author: YangFan +Function: Deal with QPC Rsp and Read CQC. +--------------------------------------------- Module Decription : End -----------------------------------------------*/ + +/*------------------------------------------- Timescale Definition : Begin ------------------------------------------*/ +`timescale 1ns / 1ps +/*------------------------------------------- Timescale Definition : End --------------------------------------------*/ + +/*------------------------------------------- Included Files : Begin ------------------------------------------------*/ +`include "protocol_engine_def.vh" +/*------------------------------------------- Included Files : End --------------------------------------------------*/ + +/*------------------------------------------- Input/Output Definition : Begin ---------------------------------------*/ +module HWAccCMCtl_Thread_3 +#( + parameter ICM_CACHE_TYPE = `CACHE_TYPE_MTT, + parameter ICM_PAGE_NUM = `ICM_PAGE_NUM_MTT, + parameter ICM_PAGE_NUM_LOG = log2b(ICM_PAGE_NUM - 1), + parameter ICM_ENTRY_NUM = `ICM_ENTRY_NUM_MTT, + parameter ICM_ENTRY_NUM_LOG = log2b(ICM_ENTRY_NUM - 1), + parameter ICM_SLOT_SIZE = `ICM_SLOT_SIZE_MTT, + parameter ICM_ADDR_WIDTH = 64, + + parameter CACHE_ADDR_WIDTH = ICM_ADDR_WIDTH, + parameter CACHE_ENTRY_WIDTH = 256, + parameter CACHE_SET_NUM = 1024, + parameter CACHE_SET_NUM_LOG = log2b(CACHE_SET_NUM - 1), + parameter CACHE_OFFSET_WIDTH = log2b(CACHE_ENTRY_WIDTH / 8 - 1), + parameter CACHE_TAG_WIDTH = CACHE_ADDR_WIDTH - CACHE_OFFSET_WIDTH - CACHE_SET_NUM_LOG, + parameter PHYSICAL_ADDR_WIDTH = 64, + parameter COUNT_MAX = 2, + parameter COUNT_MAX_LOG = log2b(COUNT_MAX - 1) + 1, + parameter REQ_TAG_NUM = 256, + parameter REQ_TAG_NUM_LOG = log2b(REQ_TAG_NUM - 1), + parameter REORDER_BUFFER_WIDTH = (ICM_CACHE_TYPE == `CACHE_TYPE_MTT) ? CACHE_ENTRY_WIDTH * 2 + COUNT_MAX_LOG : CACHE_ENTRY_WIDTH + COUNT_MAX_LOG, + + parameter CQN_NUM = `ICM_ENTRY_NUM_CQC, + parameter CQN_NUM_LOG = log2b(CQN_NUM - 1) +) +( + input wire clk, + input wire rst, + +//Interface with QPCCache + input wire qpc_get_rsp_valid, + input wire [COUNT_MAX_LOG * 2 + `MAX_REQ_TAG_NUM_LOG + PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH - 1 : 0] qpc_get_rsp_head, + input wire [CACHE_ENTRY_WIDTH - 1 : 0] qpc_get_rsp_data, + output wire qpc_get_rsp_ready, + +//Mapping Lookup Interface + output wire icm_mapping_lookup_valid, + output wire [ICM_ENTRY_NUM_LOG - 1 : 0] icm_mapping_lookup_head, + input wire icm_mapping_lookup_ready, + + input wire icm_mapping_rsp_valid, + input wire [ICM_ADDR_WIDTH - 1 : 0] icm_mapping_rsp_icm_addr, + input wire [PHYSICAL_ADDR_WIDTH - 1 : 0] icm_mapping_rsp_phy_addr, + output wire icm_mapping_rsp_ready, + +//Interface with QPCStagedBuffer + output wire qpc_buffer_wen, + output wire [`MAX_REQ_TAG_NUM_LOG - 1 : 0] qpc_buffer_addr, + output wire [`CACHE_ENTRY_WIDTH_QPC - 1 : 0] qpc_buffer_din, + +//Interface with CQCCache + output wire cqc_get_req_valid, + output wire [COUNT_MAX_LOG * 2 + `MAX_REQ_TAG_NUM_LOG + PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH - 1 : 0] cqc_get_req_head, + input wire cqc_get_req_ready +); +/*------------------------------------------- Input/Output Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Macros Definition : Begin ---------------------------------------*/ +`define CQN_SEND_OFFSET 79:64 +`define CQN_RECV_OFFSET 95:80 + +`define SQ_CHNL 0 +`define TX_REQ_CHNL 1 +`define RX_REQ_CHNL 2 +`define RX_RESP_CHNL 3 +/*------------------------------------------- Local Macros Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Variables Definition : Begin ------------------------------------*/ +reg [COUNT_MAX_LOG * 2 + `MAX_REQ_TAG_NUM_LOG + PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH - 1 : 0] qpc_get_rsp_head_diff; +reg [CACHE_ENTRY_WIDTH - 1 : 0] qpc_get_rsp_data_diff; + +wire [COUNT_MAX_LOG - 1 : 0] count_total; +wire [COUNT_MAX_LOG - 1 : 0] count_index; +wire [`MAX_REQ_TAG_NUM_LOG - 1 : 0] req_tag; + +reg [PHYSICAL_ADDR_WIDTH - 1 : 0] phy_addr; +reg [ICM_ADDR_WIDTH - 1 : 0] icm_addr; + +wire [CQN_NUM_LOG - 1 : 0] cqn; + +wire [2:0] chnl_index; +/*------------------------------------------- Local Variables Definition : End --------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : Begin ---------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : End -----------------------------------------*/ + +/*------------------------------------------- State Machine Definition : Begin --------------------------------------*/ +reg [2:0] cur_state; +reg [2:0] next_state; + +parameter [2:0] IDLE_s = 3'd1, + ADDR_REQ_s = 3'd2, + ADDR_RSP_s = 3'd3, + CQC_REQ_s = 3'd4; + +always @(posedge clk or posedge rst) begin + if(rst) begin + cur_state <= IDLE_s; + end + else begin + cur_state <= next_state; + end +end + +always @(*) begin + case(cur_state) + IDLE_s: if(qpc_get_rsp_valid) begin + next_state = ADDR_REQ_s; + end + else begin + next_state = IDLE_s; + end + ADDR_REQ_s: if(icm_mapping_lookup_valid && icm_mapping_lookup_ready) begin + next_state = ADDR_RSP_s; + end + else begin + next_state = ADDR_REQ_s; + end + ADDR_RSP_s: if(icm_mapping_rsp_valid) begin + next_state = CQC_REQ_s; + end + else begin + next_state = ADDR_RSP_s; + end + CQC_REQ_s: if(cqc_get_req_valid && cqc_get_req_valid) begin + next_state = IDLE_s; + end + else begin + next_state = CQC_REQ_s; + end + default: next_state = IDLE_s; + endcase +end +/*------------------------------------------- State Machine Definition : End ----------------------------------------*/ + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ +//-- qpc_get_rsp_head_diff -- +always @(posedge clk or posedge rst) begin + if(rst) begin + qpc_get_rsp_head_diff <= 'd0; + qpc_get_rsp_data_diff <= 'd0; + end + else if(cur_state == IDLE_s && qpc_get_rsp_valid) begin + qpc_get_rsp_head_diff <= qpc_get_rsp_head; + qpc_get_rsp_data_diff <= qpc_get_rsp_data; + end + else begin + qpc_get_rsp_head_diff <= qpc_get_rsp_head_diff; + qpc_get_rsp_data_diff <= qpc_get_rsp_data_diff; + end +end + +//-- chnl_index -- +assign chnl_index = req_tag[REQ_TAG_NUM_LOG - 1 : REQ_TAG_NUM_LOG - 2]; //HW has 4 chnls + +//-- count_total -- +//-- count_index -- +//-- req_tag -- +assign count_total = qpc_get_rsp_head_diff[COUNT_MAX_LOG * 2 + `MAX_REQ_TAG_NUM_LOG + PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH - 1 : COUNT_MAX_LOG + `MAX_REQ_TAG_NUM_LOG + PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH]; +assign count_index = qpc_get_rsp_head_diff[COUNT_MAX_LOG + `MAX_REQ_TAG_NUM_LOG + PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH - 1 : `MAX_REQ_TAG_NUM_LOG + PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH]; +assign req_tag = qpc_get_rsp_head_diff[`MAX_REQ_TAG_NUM_LOG + PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH - 1 : PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH]; + +//-- req_tag -- +//-- phy_addr -- +//-- icm_addr -- +always @(posedge clk or posedge rst) begin + if (rst) begin + phy_addr <= 'd0; + icm_addr <= 'd0; + end + else if (cur_state == ADDR_RSP_s && icm_mapping_rsp_valid) begin + phy_addr <= icm_mapping_rsp_phy_addr; + icm_addr <= icm_mapping_rsp_icm_addr; + end + else begin + phy_addr <= phy_addr; + icm_addr <= icm_addr; + end +end + +//-- cqn -- //Decide whether to require CQN-Send or CQN-Recv +assign cqn = (cur_state == ADDR_REQ_s && chnl_index == `SQ_CHNL) ? qpc_get_rsp_data_diff[`CQN_SEND_OFFSET] : + (cur_state == ADDR_REQ_s && chnl_index == `TX_REQ_CHNL) ? qpc_get_rsp_data_diff[`CQN_SEND_OFFSET] : + (cur_state == ADDR_REQ_s && chnl_index == `RX_REQ_CHNL) ? qpc_get_rsp_data_diff[`CQN_RECV_OFFSET] : + (cur_state == ADDR_REQ_s && chnl_index == `RX_RESP_CHNL) ? qpc_get_rsp_data_diff[`CQN_SEND_OFFSET] : 'd0; + +//-- icm_mapping_lookup_valid -- +//-- icm_mapping_lookup_head -- +assign icm_mapping_lookup_valid = (cur_state == ADDR_REQ_s) ? 'd1 : 'd0; +assign icm_mapping_lookup_head = (cur_state == ADDR_REQ_s) ? cqn : 'd0; + +//-- icm_mapping_rsp_ready -- +assign icm_mapping_rsp_ready = (cur_state == ADDR_RSP_s) ? 'd1 : 'd0; +//-- qpc_buffer_wen -- +//-- qpc_buffer_addr -- +//-- qpc_buffer_din -- +assign qpc_buffer_wen = (cur_state == CQC_REQ_s) ? 'd1 : 'd0; +assign qpc_buffer_addr = (cur_state == CQC_REQ_s) ? req_tag : 'd0; +assign qpc_buffer_din = (cur_state == CQC_REQ_s) ? qpc_get_rsp_data_diff : 'd0; + +//-- cqc_get_req_valid -- +//-- cqc_get_req_head -- +assign cqc_get_req_valid = (cur_state == CQC_REQ_s) ? 'd1 : 'd0; +assign cqc_get_req_head = (cur_state == CQC_REQ_s) ? {count_total, count_index, req_tag, phy_addr, icm_addr} : 'd0; + +//-- qpc_get_rsp_ready -- +assign qpc_get_rsp_ready = (cur_state == IDLE_s); +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ + +/*------------------------------------------- Local Macros Undef : Begin --------------------------------------------*/ +`undef CQN_SEND_OFFSET +`undef CQN_RECV_OFFSET + +`undef SQ_CHNL +`undef TX_REQ_CHNL +`undef RX_REQ_CHNL +`undef RX_RESP_CHNL +/*------------------------------------------- Local Macros Undef : End ----------------------------------------------*/ +`ifdef ILA_ON + +ila_hw_acc_cm_thread_3 ila_hw_acc_cm_thread_3_inst( + .clk(clk), + + .probe0(qpc_get_rsp_valid), + .probe1(qpc_get_rsp_head), + .probe2(qpc_get_rsp_data), + .probe3(qpc_get_rsp_ready), + + .probe4(icm_mapping_lookup_valid), + .probe5(icm_mapping_lookup_head), + .probe6(icm_mapping_lookup_ready), + + .probe7(icm_mapping_rsp_valid), + .probe8(icm_mapping_rsp_icm_addr), + .probe9(icm_mapping_rsp_phy_addr), + .probe10(icm_mapping_rsp_ready), + + .probe11(qpc_buffer_wen), + .probe12(qpc_buffer_addr), + .probe13(qpc_buffer_din), + + .probe14(cqc_get_req_valid), + .probe15(cqc_get_req_head), + .probe16(cqc_get_req_ready) +); +`endif + +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/ICMMgt/CxtMgt/HWAccCMCtl/HWAccCMCtl_Thread_4.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/ICMMgt/CxtMgt/HWAccCMCtl/HWAccCMCtl_Thread_4.v new file mode 100644 index 0000000000000000000000000000000000000000..8685685685c18dc110d077324a26aedeaeacbb6c --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/ICMMgt/CxtMgt/HWAccCMCtl/HWAccCMCtl_Thread_4.v @@ -0,0 +1,253 @@ +/*------------------------------------------- Module Description : Begin ---------------------------------------------- +Name: HWAccCMCtl_Thread_4 +Author: YangFan +Function: Deal with CQC Rsp and Read EQC. +--------------------------------------------- Module Decription : End -----------------------------------------------*/ + +/*------------------------------------------- Timescale Definition : Begin ------------------------------------------*/ +`timescale 1ns / 1ps +/*------------------------------------------- Timescale Definition : End --------------------------------------------*/ + +/*------------------------------------------- Included Files : Begin ------------------------------------------------*/ +`include "protocol_engine_def.vh" +/*------------------------------------------- Included Files : End --------------------------------------------------*/ + +/*------------------------------------------- Input/Output Definition : Begin ---------------------------------------*/ +module HWAccCMCtl_Thread_4 +#( + parameter ICM_CACHE_TYPE = `CACHE_TYPE_MTT, + parameter ICM_PAGE_NUM = `ICM_PAGE_NUM_MTT, + parameter ICM_PAGE_NUM_LOG = log2b(ICM_PAGE_NUM - 1), + parameter ICM_ENTRY_NUM = `ICM_ENTRY_NUM_MTT, + parameter ICM_ENTRY_NUM_LOG = log2b(ICM_ENTRY_NUM - 1), + parameter ICM_SLOT_SIZE = `ICM_SLOT_SIZE_MTT, + parameter ICM_ADDR_WIDTH = 64, + + parameter CACHE_ADDR_WIDTH = ICM_ADDR_WIDTH, + parameter CACHE_ENTRY_WIDTH = 256, + parameter CACHE_SET_NUM = 1024, + parameter CACHE_SET_NUM_LOG = log2b(CACHE_SET_NUM - 1), + parameter CACHE_OFFSET_WIDTH = log2b(CACHE_ENTRY_WIDTH / 8 - 1), + parameter CACHE_TAG_WIDTH = CACHE_ADDR_WIDTH - CACHE_OFFSET_WIDTH - CACHE_SET_NUM_LOG, + parameter PHYSICAL_ADDR_WIDTH = 64, + parameter COUNT_MAX = 2, + parameter COUNT_MAX_LOG = log2b(COUNT_MAX - 1) + 1, + parameter REQ_TAG_NUM = 64, + parameter REQ_TAG_NUM_LOG = log2b(REQ_TAG_NUM - 1), + parameter REORDER_BUFFER_WIDTH = (ICM_CACHE_TYPE == `CACHE_TYPE_MTT) ? CACHE_ENTRY_WIDTH * 2 + COUNT_MAX_LOG : CACHE_ENTRY_WIDTH + COUNT_MAX_LOG, + + parameter CQN_NUM = `ICM_ENTRY_NUM_CQC, + parameter CQN_NUM_LOG = log2b(CQN_NUM - 1) +) +( + input wire clk, + input wire rst, + +//Interface with CQCCache + input wire cqc_get_rsp_valid, + input wire [COUNT_MAX_LOG * 2 + `MAX_REQ_TAG_NUM_LOG + PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH - 1 : 0] cqc_get_rsp_head, + input wire [CACHE_ENTRY_WIDTH - 1 : 0] cqc_get_rsp_data, + output wire cqc_get_rsp_ready, + +//Mapping Lookup Interface + output wire icm_mapping_lookup_valid, + output wire [ICM_ENTRY_NUM_LOG - 1 : 0] icm_mapping_lookup_head, + input wire icm_mapping_lookup_ready, + + input wire icm_mapping_rsp_valid, + input wire [ICM_ADDR_WIDTH - 1 : 0] icm_mapping_rsp_icm_addr, + input wire [PHYSICAL_ADDR_WIDTH - 1 : 0] icm_mapping_rsp_phy_addr, + output wire icm_mapping_rsp_ready, + +//Interface with CQCStagedBuffer + output wire cqc_buffer_wen, + output wire [`MAX_REQ_TAG_NUM_LOG - 1 : 0] cqc_buffer_addr, + output wire [`CACHE_ENTRY_WIDTH_CQC - 1 : 0] cqc_buffer_din, + +//Interface with EQCCache + output wire eqc_get_req_valid, + output wire [COUNT_MAX_LOG * 2 + `MAX_REQ_TAG_NUM_LOG + PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH - 1 : 0] eqc_get_req_head, + input wire eqc_get_req_ready +); +/*------------------------------------------- Input/Output Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Macros Definition : Begin ---------------------------------------*/ +`define CXT_CMD_TAG_OFFSET 39:32 +`define COMP_EQN_OFFSET 63:32 + +/*------------------------------------------- Local Macros Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Variables Definition : Begin ------------------------------------*/ +reg [COUNT_MAX_LOG * 2 + `MAX_REQ_TAG_NUM_LOG + PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH - 1 : 0] cqc_get_rsp_head_diff; +reg [CACHE_ENTRY_WIDTH - 1 : 0] cqc_get_rsp_data_diff; + +wire [COUNT_MAX_LOG - 1 : 0] count_total; +wire [COUNT_MAX_LOG - 1 : 0] count_index; + +wire [`MAX_REQ_TAG_NUM_LOG - 1 : 0] req_tag; +reg [PHYSICAL_ADDR_WIDTH - 1 : 0] phy_addr; +reg [ICM_ADDR_WIDTH - 1 : 0] icm_addr; + +wire [CQN_NUM_LOG - 1 : 0] eqn; + +wire [2:0] chnl_index; +/*------------------------------------------- Local Variables Definition : End --------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : Begin ---------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : End -----------------------------------------*/ + +/*------------------------------------------- State Machine Definition : Begin --------------------------------------*/ +reg [2:0] cur_state; +reg [2:0] next_state; + +parameter [2:0] IDLE_s = 3'd1, + ADDR_REQ_s = 3'd2, + ADDR_RSP_s = 3'd3, + EQC_REQ_s = 3'd4; + +always @(posedge clk or posedge rst) begin + if(rst) begin + cur_state <= IDLE_s; + end + else begin + cur_state <= next_state; + end +end + +always @(*) begin + case(cur_state) + IDLE_s: if(cqc_get_rsp_valid) begin + next_state = ADDR_REQ_s; + end + else begin + next_state = IDLE_s; + end + ADDR_REQ_s: if(icm_mapping_lookup_valid && icm_mapping_lookup_ready) begin + next_state = ADDR_RSP_s; + end + else begin + next_state = ADDR_REQ_s; + end + ADDR_RSP_s: if(icm_mapping_rsp_valid) begin + next_state = EQC_REQ_s; + end + else begin + next_state = ADDR_RSP_s; + end + EQC_REQ_s: if(eqc_get_req_valid && eqc_get_req_valid) begin + next_state = IDLE_s; + end + else begin + next_state = EQC_REQ_s; + end + default: next_state = IDLE_s; + endcase +end +/*------------------------------------------- State Machine Definition : End ----------------------------------------*/ + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ +//-- cqc_get_rsp_head_diff -- +always @(posedge clk or posedge rst) begin + if(rst) begin + cqc_get_rsp_head_diff <= 'd0; + cqc_get_rsp_data_diff <= 'd0; + end + else if(cur_state == IDLE_s && cqc_get_rsp_valid) begin + cqc_get_rsp_head_diff <= cqc_get_rsp_head; + cqc_get_rsp_data_diff <= cqc_get_rsp_data; + end + else begin + cqc_get_rsp_head_diff <= cqc_get_rsp_head_diff; + cqc_get_rsp_data_diff <= cqc_get_rsp_data_diff; + end +end + +//-- chnl_index -- +assign chnl_index = req_tag[7:5]; + +//-- count_total -- +//-- count_index -- +assign count_total = cqc_get_rsp_head_diff[COUNT_MAX_LOG * 2 + `MAX_REQ_TAG_NUM_LOG + PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH - 1 : COUNT_MAX_LOG + `MAX_REQ_TAG_NUM_LOG + PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH]; +assign count_index = cqc_get_rsp_head_diff[COUNT_MAX_LOG + `MAX_REQ_TAG_NUM_LOG + PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH - 1 : `MAX_REQ_TAG_NUM_LOG + PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH]; +assign req_tag = cqc_get_rsp_head_diff[`MAX_REQ_TAG_NUM_LOG + PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH - 1 : PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH]; + +//-- req_tag -- +//-- phy_addr -- +//-- icm_addr -- +always @(posedge clk or posedge rst) begin + if (rst) begin + phy_addr <= 'd0; + icm_addr <= 'd0; + end + else if (cur_state == ADDR_RSP_s && icm_mapping_rsp_valid) begin + phy_addr <= icm_mapping_rsp_phy_addr; + icm_addr <= icm_mapping_rsp_icm_addr; + end + else begin + phy_addr <= phy_addr; + icm_addr <= icm_addr; + end +end + +//-- eqn -- +assign eqn = (cur_state == ADDR_REQ_s) ? cqc_get_rsp_data_diff[`COMP_EQN_OFFSET] : 'd0; + +//-- icm_mapping_lookup_valid -- +//-- icm_mapping_lookup_head -- +assign icm_mapping_lookup_valid = (cur_state == ADDR_REQ_s) ? 'd1 : 'd0; +assign icm_mapping_lookup_head = (cur_state == ADDR_REQ_s) ? eqn : 'd0; + +//-- icm_mapping_rsp_ready -- +assign icm_mapping_rsp_ready = (cur_state == ADDR_RSP_s) ? 'd1 : 'd0; + +//-- cqc_buffer_wen -- +//-- cqc_buffer_addr -- +//-- cqc_buffer_din -- +assign cqc_buffer_wen = (cur_state == EQC_REQ_s) ? 'd1 : 'd0; +assign cqc_buffer_addr = (cur_state == EQC_REQ_s) ? req_tag : 'd0; +assign cqc_buffer_din = (cur_state == EQC_REQ_s) ? cqc_get_rsp_data_diff : 'd0; + +//Interface with EQCCache +assign eqc_get_req_valid = (cur_state == EQC_REQ_s) ? 'd1 : 'd0; +assign eqc_get_req_head = (cur_state == EQC_REQ_s) ? {count_total, count_index, req_tag, phy_addr, icm_addr} : 'd0; + +//== cqc_get_rsp_ready -- +assign cqc_get_rsp_ready = (cur_state == IDLE_s); +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ + +/*------------------------------------------- Local Macros Undef : Begin --------------------------------------------*/ +`undef CXT_CMD_TAG_OFFSET +`undef COMP_EQN_OFFSET +/*------------------------------------------- Local Macros Undef : End ----------------------------------------------*/ + +`ifdef ILA_ON + +ila_hw_acc_cm_thread_4 ila_hw_acc_cm_thread_4_inst( + .clk(clk), + + .probe0(cqc_get_rsp_valid), + .probe1(cqc_get_rsp_head), + .probe2(cqc_get_rsp_data), + .probe3(cqc_get_rsp_ready), + + .probe4(icm_mapping_lookup_valid), + .probe5(icm_mapping_lookup_head), + .probe6(icm_mapping_lookup_ready), + + .probe7(icm_mapping_rsp_valid), + .probe8(icm_mapping_rsp_icm_addr), + .probe9(icm_mapping_rsp_phy_addr), + .probe10(icm_mapping_rsp_ready), + + .probe11(cqc_buffer_wen), + .probe12(cqc_buffer_addr), + .probe13(cqc_buffer_din), + + .probe14(eqc_get_req_valid), + .probe15(eqc_get_req_head), + .probe16(eqc_get_req_ready) +); +`endif + +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/ICMMgt/CxtMgt/HWAccCMCtl/HWAccCMCtl_Thread_5.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/ICMMgt/CxtMgt/HWAccCMCtl/HWAccCMCtl_Thread_5.v new file mode 100644 index 0000000000000000000000000000000000000000..260cffd399646abf7b94f09fff933cda8c390982 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/ICMMgt/CxtMgt/HWAccCMCtl/HWAccCMCtl_Thread_5.v @@ -0,0 +1,194 @@ +/*------------------------------------------- Module Description : Begin ---------------------------------------------- +Name: HWAccCMCtl_Thread_5 +Author: YangFan +Function: Deal with EQC rsp and piece QPC-CQC-EQC together. +--------------------------------------------- Module Decription : End -----------------------------------------------*/ + +/*------------------------------------------- Timescale Definition : Begin ------------------------------------------*/ +`timescale 1ns / 1ps +/*------------------------------------------- Timescale Definition : End --------------------------------------------*/ + +/*------------------------------------------- Included Files : Begin ------------------------------------------------*/ +`include "protocol_engine_def.vh" +/*------------------------------------------- Included Files : End --------------------------------------------------*/ + +/*------------------------------------------- Input/Output Definition : Begin ---------------------------------------*/ +module HWAccCMCtl_Thread_5 +#( + parameter ICM_CACHE_TYPE = `CACHE_TYPE_MTT, + parameter ICM_PAGE_NUM = `ICM_PAGE_NUM_MTT, + parameter ICM_PAGE_NUM_LOG = log2b(ICM_PAGE_NUM - 1), + parameter ICM_ENTRY_NUM = `ICM_ENTRY_NUM_MTT, + parameter ICM_ENTRY_NUM_LOG = log2b(ICM_ENTRY_NUM - 1), + parameter ICM_SLOT_SIZE = `ICM_SLOT_SIZE_MTT, + parameter ICM_ADDR_WIDTH = 64, + + parameter CACHE_ADDR_WIDTH = ICM_ADDR_WIDTH, + parameter CACHE_ENTRY_WIDTH = 256, + parameter CACHE_SET_NUM = 1024, + parameter CACHE_SET_NUM_LOG = log2b(CACHE_SET_NUM - 1), + parameter CACHE_OFFSET_WIDTH = log2b(CACHE_ENTRY_WIDTH / 8 - 1), + parameter CACHE_TAG_WIDTH = CACHE_ADDR_WIDTH - CACHE_OFFSET_WIDTH - CACHE_SET_NUM_LOG, + parameter PHYSICAL_ADDR_WIDTH = 64, + parameter COUNT_MAX = 2, + parameter COUNT_MAX_LOG = log2b(COUNT_MAX - 1) + 1, + parameter REQ_TAG_NUM = 32, + parameter REQ_TAG_NUM_LOG = log2b(REQ_TAG_NUM - 1), + parameter REORDER_BUFFER_WIDTH = (ICM_CACHE_TYPE == `CACHE_TYPE_MTT) ? CACHE_ENTRY_WIDTH * 2 + COUNT_MAX_LOG : CACHE_ENTRY_WIDTH + COUNT_MAX_LOG, + + parameter CQN_NUM = `ICM_ENTRY_NUM_CQC, + parameter CQN_NUM_LOG = log2b(CQN_NUM - 1) +) +( + input wire clk, + input wire rst, + +//Interface with EQCCache + input wire eqc_get_rsp_valid, + input wire [COUNT_MAX_LOG * 2 + `MAX_REQ_TAG_NUM_LOG + PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH - 1 : 0] eqc_get_rsp_head, + input wire [CACHE_ENTRY_WIDTH - 1 : 0] eqc_get_rsp_data, + output wire eqc_get_rsp_ready, + +//Interface with QPCStagedBuffer + output wire [`MAX_REQ_TAG_NUM_LOG - 1 : 0] qpc_buffer_addr, + input wire [`CACHE_ENTRY_WIDTH_QPC - 1 : 0] qpc_buffer_dout, + +//Interface with CQCStagedBuffer + output wire [`MAX_REQ_TAG_NUM_LOG - 1 : 0] cqc_buffer_addr, + input wire [`CACHE_ENTRY_WIDTH_CQC - 1 : 0] cqc_buffer_dout, + +//Interface with HWAccessCtl_Thread_6 + output wire cxt_combine_valid, + output wire [`MAX_REQ_TAG_NUM_LOG - 1 : 0] cxt_combine_head, + output wire [`CXT_RESP_DATA_WIDTH - 1 : 0] cxt_combine_data, + input wire cxt_combine_ready +); +/*------------------------------------------- Input/Output Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Macros Definition : Begin ---------------------------------------*/ +/*------------------------------------------- Local Macros Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Variables Definition : Begin ------------------------------------*/ +reg [COUNT_MAX_LOG * 2 + `MAX_REQ_TAG_NUM_LOG + PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH - 1 : 0] eqc_get_rsp_head_diff; +reg [CACHE_ENTRY_WIDTH - 1 : 0] eqc_get_rsp_data_diff; + +reg [`MAX_REQ_TAG_NUM_LOG - 1 : 0] req_tag; +/*------------------------------------------- Local Variables Definition : End --------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : Begin ---------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : End -----------------------------------------*/ + +/*------------------------------------------- State Machine Definition : Begin --------------------------------------*/ +reg [1:0] cur_state; +reg [1:0] next_state; + +parameter [1:0] IDLE_s = 2'd1, + COMBINE_s = 2'd2, + RSP_s = 2'd3; + +always @(posedge clk or posedge rst) begin + if(rst) begin + cur_state <= IDLE_s; + end + else begin + cur_state <= next_state; + end +end + +always @(*) begin + case(cur_state) + IDLE_s: if(eqc_get_rsp_valid) begin + next_state = COMBINE_s; + end + else begin + next_state = IDLE_s; + end + COMBINE_s: next_state = RSP_s; + RSP_s: if(cxt_combine_valid && cxt_combine_ready) begin + next_state = IDLE_s; + end + else begin + next_state = RSP_s; + end + default: next_state = IDLE_s; + endcase +end +/*------------------------------------------- State Machine Definition : End ----------------------------------------*/ + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ +//-- eqc_get_rsp_head_diff -- +//-- eqc_get_rsp_data_diff -- +always @(posedge clk or posedge rst) begin + if(rst) begin + eqc_get_rsp_head_diff <= 'd0; + eqc_get_rsp_data_diff <= 'd0; + end + else if(cur_state == IDLE_s && eqc_get_rsp_valid) begin + eqc_get_rsp_head_diff <= eqc_get_rsp_head; + eqc_get_rsp_data_diff <= eqc_get_rsp_data; + end + else begin + eqc_get_rsp_head_diff <= eqc_get_rsp_head_diff; + eqc_get_rsp_data_diff <= eqc_get_rsp_data_diff; + end +end + +//-- req_tag -- +always @(posedge clk or posedge rst) begin + if(rst) begin + req_tag <= 'd0; + end + else if(cur_state == IDLE_s && eqc_get_rsp_valid) begin + req_tag <= eqc_get_rsp_head[`MAX_REQ_TAG_NUM_LOG + PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH - 1 : PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH]; + end + else begin + req_tag <= req_tag; + end +end + +//-- qpc_buffer_addr -- +assign qpc_buffer_addr = req_tag; + +//-- cqc_buffer_addr -- +assign cqc_buffer_addr = req_tag; + +//-- cxt_combine_valid -- +//-- cxt_combine_head -- +//-- cxt_combine_data -- +assign cxt_combine_valid = (cur_state == RSP_s) ? 'd1 : 'd0; +assign cxt_combine_head = (cur_state == RSP_s) ? req_tag : 'd0; +assign cxt_combine_data = (cur_state == RSP_s) ? {eqc_get_rsp_data_diff, cqc_buffer_dout, qpc_buffer_dout} : 'd0; + + +//-- eqc_get_rsp_ready -- +assign eqc_get_rsp_ready = (cur_state == IDLE_s); +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ + +/*------------------------------------------- Local Macros Undef : Begin --------------------------------------------*/ +/*------------------------------------------- Local Macros Undef : End ----------------------------------------------*/ +`ifdef ILA_ON + +ila_hw_acc_cm_thread_5 ila_hw_acc_cm_thread_5_inst( + .clk(clk), + + .probe0(eqc_get_rsp_valid), + .probe1(eqc_get_rsp_head), + .probe2(eqc_get_rsp_data), + .probe3(eqc_get_rsp_ready), + + .probe4(qpc_buffer_addr), + .probe5(qpc_buffer_dout), + + .probe6(cqc_buffer_addr), + .probe7(cqc_buffer_dout), + + .probe8(cxt_combine_valid), + .probe9(cxt_combine_head), + .probe10(cxt_combine_data), + .probe11(cxt_combine_ready) +); + +`endif + +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/ICMMgt/CxtMgt/HWAccCMCtl/HWAccCMCtl_Thread_6.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/ICMMgt/CxtMgt/HWAccCMCtl/HWAccCMCtl_Thread_6.v new file mode 100644 index 0000000000000000000000000000000000000000..127d24b1a657b8ed1a2a5cd0faf5b6c414c3769b --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/ICMMgt/CxtMgt/HWAccCMCtl/HWAccCMCtl_Thread_6.v @@ -0,0 +1,227 @@ +/*------------------------------------------- Module Description : Begin ---------------------------------------------- +Name: HWAccCMCtl_Thread_1 +Author: YangFan +Function: Arbitrate from different Request Channels.. +--------------------------------------------- Module Decription : End -----------------------------------------------*/ + +/*------------------------------------------- Timescale Definition : Begin ------------------------------------------*/ +`timescale 1ns / 1ps +/*------------------------------------------- Timescale Definition : End --------------------------------------------*/ + +/*------------------------------------------- Included Files : Begin ------------------------------------------------*/ +`include "protocol_engine_def.vh" +/*------------------------------------------- Included Files : End --------------------------------------------------*/ + +/*------------------------------------------- Input/Output Definition : Begin ---------------------------------------*/ +module HWAccCMCtl_Thread_6 +#( + parameter ICM_CACHE_TYPE = `CACHE_TYPE_MTT, + parameter ICM_PAGE_NUM = `ICM_PAGE_NUM_MTT, + parameter ICM_PAGE_NUM_LOG = log2b(ICM_PAGE_NUM - 1), + parameter ICM_ENTRY_NUM = `ICM_ENTRY_NUM_MTT, + parameter ICM_ENTRY_NUM_LOG = log2b(ICM_ENTRY_NUM - 1), + parameter ICM_SLOT_SIZE = `ICM_SLOT_SIZE_MTT, + parameter ICM_ADDR_WIDTH = 64, + + parameter CACHE_ADDR_WIDTH = ICM_ADDR_WIDTH, + parameter CACHE_ENTRY_WIDTH = 256, + parameter CACHE_SET_NUM = 1024, + parameter CACHE_SET_NUM_LOG = log2b(CACHE_SET_NUM - 1), + parameter CACHE_OFFSET_WIDTH = log2b(CACHE_ENTRY_WIDTH / 8 - 1), + parameter CACHE_TAG_WIDTH = CACHE_ADDR_WIDTH - CACHE_OFFSET_WIDTH - CACHE_SET_NUM_LOG, + parameter PHYSICAL_ADDR_WIDTH = 64, + parameter COUNT_MAX = 2, + parameter COUNT_MAX_LOG = log2b(COUNT_MAX - 1) + 1, + parameter REQ_TAG_NUM = 32, + parameter REQ_TAG_NUM_LOG = log2b(REQ_TAG_NUM - 1), + parameter REORDER_BUFFER_WIDTH = (ICM_CACHE_TYPE == `CACHE_TYPE_MTT) ? CACHE_ENTRY_WIDTH * 2 + COUNT_MAX_LOG : CACHE_ENTRY_WIDTH + COUNT_MAX_LOG +) +( + input wire clk, + input wire rst, + +//Interface with HWAccCMCtl_Thread_5 + input wire cxt_combine_valid, + input wire [`CXT_RESP_HEAD_WIDTH + `MAX_REQ_TAG_NUM_LOG - 1 : 0] cxt_combine_head, + input wire [`CXT_RESP_DATA_WIDTH - 1 : 0] cxt_combine_data, + output wire cxt_combine_ready, + +//Interface with TagQPNMappingTable + output wire [`MAX_REQ_TAG_NUM_LOG - 1 : 0] tag_qpn_mapping_table_addr, + input wire [`QP_NUM_LOG - 1 : 0] tag_qpn_mapping_table_dout, + +//Interface with RDMACore and QueueSubsystem + //Interface with SQMgt + output wire SQ_cxt_rsp_valid, + output wire [`CXT_RESP_HEAD_WIDTH + `MAX_REQ_TAG_NUM_LOG - 1 : 0] SQ_cxt_rsp_head, + output wire [`CXT_RESP_DATA_WIDTH - 1 : 0] SQ_cxt_rsp_data, + input wire SQ_cxt_rsp_ready, + + //Interface with RDMACore/RequesterCore/ReqTransCore + output wire TX_REQ_cxt_rsp_valid, + output wire [`CXT_RESP_HEAD_WIDTH + `MAX_REQ_TAG_NUM_LOG - 1 : 0] TX_REQ_cxt_rsp_head, + output wire [`CXT_RESP_DATA_WIDTH - 1 : 0] TX_REQ_cxt_rsp_data, + input wire TX_REQ_cxt_rsp_ready, + + //Interface with RDMACore/RequesterCore/RespRecvCore + output wire RX_REQ_cxt_rsp_valid, + output wire [`CXT_RESP_HEAD_WIDTH + `MAX_REQ_TAG_NUM_LOG - 1 : 0] RX_REQ_cxt_rsp_head, + output wire [`CXT_RESP_DATA_WIDTH - 1 : 0] RX_REQ_cxt_rsp_data, + input wire RX_REQ_cxt_rsp_ready, + + //Interface with RDMACore/ResponderCore/ReqRecvCore + output wire RX_RESP_cxt_rsp_valid, + output wire [`CXT_RESP_HEAD_WIDTH + `MAX_REQ_TAG_NUM_LOG - 1 : 0] RX_RESP_cxt_rsp_head, + output wire [`CXT_RESP_DATA_WIDTH - 1 : 0] RX_RESP_cxt_rsp_data, + input wire RX_RESP_cxt_rsp_ready +); +/*------------------------------------------- Input/Output Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Macros Definition : Begin ---------------------------------------*/ + +/*------------------------------------------- Local Macros Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Variables Definition : Begin ------------------------------------*/ +wire [1:0] chnl_index; + +reg [`CXT_RESP_HEAD_WIDTH + `MAX_REQ_TAG_NUM_LOG - 1 : 0] cxt_combine_head_diff; +reg [`CXT_RESP_DATA_WIDTH - 1 : 0] cxt_combine_data_diff; +/*------------------------------------------- Local Variables Definition : End --------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : Begin ---------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : End -----------------------------------------*/ + +/*------------------------------------------- State Machine Definition : Begin --------------------------------------*/ +reg [2:0] cur_state; +reg [2:0] next_state; + +parameter [2:0] IDLE_s = 3'd1, + CHNL_0_RSP_s = 3'd2, + CHNL_1_RSP_s = 3'd3, + CHNL_2_RSP_s = 3'd4, + CHNL_3_RSP_s = 3'd5; + +always @(posedge clk or posedge rst) begin + if (rst) begin + cur_state <= IDLE_s; + end + else begin + cur_state <= next_state; + end +end + +always @(*) begin + case(cur_state) + IDLE_s: if(cxt_combine_valid) begin + if(chnl_index == 0) begin + next_state = CHNL_0_RSP_s; + end + else if(chnl_index == 1) begin + next_state = CHNL_1_RSP_s; + end + else if(chnl_index == 2) begin + next_state = CHNL_2_RSP_s; + end + else if(chnl_index == 3) begin + next_state = CHNL_3_RSP_s; + end + else begin + next_state = IDLE_s; + end + end + else begin + next_state = IDLE_s; + end + CHNL_0_RSP_s: if(SQ_cxt_rsp_valid && SQ_cxt_rsp_ready) begin + next_state = IDLE_s; + end + else begin + next_state = CHNL_0_RSP_s; + end + CHNL_1_RSP_s: if(TX_REQ_cxt_rsp_valid && TX_REQ_cxt_rsp_ready) begin + next_state = IDLE_s; + end + else begin + next_state = CHNL_1_RSP_s; + end + CHNL_2_RSP_s: if(RX_REQ_cxt_rsp_valid && RX_REQ_cxt_rsp_ready) begin + next_state = IDLE_s; + end + else begin + next_state = CHNL_2_RSP_s; + end + CHNL_3_RSP_s: if(RX_RESP_cxt_rsp_valid && RX_RESP_cxt_rsp_ready) begin + next_state = IDLE_s; + end + else begin + next_state = CHNL_3_RSP_s; + end + default: next_state = IDLE_s; + endcase +end +/*------------------------------------------- State Machine Definition : End ----------------------------------------*/ + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ +//-- chnl_index -- +assign chnl_index = (cur_state == IDLE_s && cxt_combine_valid) ? cxt_combine_head[REQ_TAG_NUM_LOG + 2 - 1 : REQ_TAG_NUM_LOG] : 'd0; + +//-- cxt_combine_head_diff -- +//-- cxt_combine_data_diff -- +always @(posedge clk or posedge rst) begin + if (rst) begin + cxt_combine_head_diff <= 'd0; + cxt_combine_data_diff <= 'd0; + end + else if (cur_state == IDLE_s && cxt_combine_valid) begin + cxt_combine_head_diff <= cxt_combine_head; + cxt_combine_data_diff <= cxt_combine_data; + end + else begin + cxt_combine_head_diff <= cxt_combine_head_diff; + cxt_combine_data_diff <= cxt_combine_data_diff; + end +end + +//-- tag_qpn_mapping_table_addr -- +assign tag_qpn_mapping_table_addr = (cur_state == IDLE_s && cxt_combine_valid) ? cxt_combine_head[`MAX_REQ_TAG_NUM_LOG - 1 : 0] : cxt_combine_head_diff[`MAX_REQ_TAG_NUM_LOG - 1 : 0]; + +wire [`MAX_REQ_TAG_NUM_LOG - 1 : 0] rsp_tag; +assign rsp_tag = {'d0, cxt_combine_head_diff[REQ_TAG_NUM_LOG - 1 : 0]}; + +//-- SQ_cxt_rsp_valid -- +//-- SQ_cxt_rsp_head -- +//-- SQ_cxt_rsp_data -- +assign SQ_cxt_rsp_valid = (cur_state == CHNL_0_RSP_s) ? 'd1 : 'd0; +assign SQ_cxt_rsp_head = (cur_state == CHNL_0_RSP_s) ? {tag_qpn_mapping_table_dout, rsp_tag} : 'd0; +assign SQ_cxt_rsp_data = (cur_state == CHNL_0_RSP_s) ? cxt_combine_data_diff : 'd0; + +//-- TX_REQ_cxt_rsp_valid -- +//-- TX_REQ_cxt_rsp_head -- +//-- TX_REQ_cxt_rsp_data -- +assign TX_REQ_cxt_rsp_valid = (cur_state == CHNL_1_RSP_s) ? 'd1 : 'd0; +assign TX_REQ_cxt_rsp_head = (cur_state == CHNL_1_RSP_s) ? {tag_qpn_mapping_table_dout, rsp_tag} : 'd0; +assign TX_REQ_cxt_rsp_data = (cur_state == CHNL_1_RSP_s) ? cxt_combine_data_diff : 'd0; + +//-- RX_REQ_cxt_rsp_valid -- +//-- RX_REQ_cxt_rsp_head -- +//-- RX_REQ_cxt_rsp_data -- +assign RX_REQ_cxt_rsp_valid = (cur_state == CHNL_2_RSP_s) ? 'd1 : 'd0; +assign RX_REQ_cxt_rsp_head = (cur_state == CHNL_2_RSP_s) ? {tag_qpn_mapping_table_dout, rsp_tag} : 'd0; +assign RX_REQ_cxt_rsp_data = (cur_state == CHNL_2_RSP_s) ? cxt_combine_data_diff : 'd0; + +//-- RX_RESP_cxt_rsp_valid -- +//-- RX_RESP_cxt_rsp_head -- +//-- RX_RESP_cxt_rsp_data -- +assign RX_RESP_cxt_rsp_valid = (cur_state == CHNL_3_RSP_s) ? 'd1 : 'd0; +assign RX_RESP_cxt_rsp_head = (cur_state == CHNL_3_RSP_s) ? {tag_qpn_mapping_table_dout, rsp_tag} : 'd0; +assign RX_RESP_cxt_rsp_data = (cur_state == CHNL_3_RSP_s) ? cxt_combine_data_diff : 'd0; + +//-- cxt_combine_ready -- +assign cxt_combine_ready = (cur_state == IDLE_s); +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ + +/*------------------------------------------- Local Macros Undef : Begin --------------------------------------------*/ +/*------------------------------------------- Local Macros Undef : End ----------------------------------------------*/ + +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/ICMMgt/CxtMgt/SWAccCMCtl/SWAccCMCtl.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/ICMMgt/CxtMgt/SWAccCMCtl/SWAccCMCtl.v new file mode 100644 index 0000000000000000000000000000000000000000..6fa308edc1f48245ad53095df8bf3a352c31fc03 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/ICMMgt/CxtMgt/SWAccCMCtl/SWAccCMCtl.v @@ -0,0 +1,344 @@ +/*------------------------------------------- Module Description : Begin ---------------------------------------------- +Name: SWAccCMCtl +Author: YangFan +Function: Control Software to CxtMgt Access. +--------------------------------------------- Module Decription : End -----------------------------------------------*/ + +/*------------------------------------------- Timescale Definition : Begin ------------------------------------------*/ +`timescale 1ns / 1ps +/*------------------------------------------- Timescale Definition : End --------------------------------------------*/ + +/*------------------------------------------- Included Files : Begin ------------------------------------------------*/ +`include "protocol_engine_def.vh" +/*------------------------------------------- Included Files : End --------------------------------------------------*/ + +/*------------------------------------------- Input/Output Definition : Begin ---------------------------------------*/ +module SWAccCMCtl +#( + parameter ICM_CACHE_TYPE = `CACHE_TYPE_QPC, + parameter ICM_PAGE_NUM = `ICM_PAGE_NUM_QPC, + parameter ICM_PAGE_NUM_LOG = log2b(ICM_PAGE_NUM - 1), + parameter ICM_ENTRY_NUM = `ICM_ENTRY_NUM_QPC, + parameter ICM_ENTRY_NUM_LOG = log2b(ICM_ENTRY_NUM - 1), + parameter ICM_SLOT_SIZE = `ICM_SLOT_SIZE_QPC, + parameter ICM_ADDR_WIDTH = 64, + + parameter CACHE_ADDR_WIDTH = 64, + parameter CACHE_ENTRY_WIDTH = `CACHE_ENTRY_WIDTH_QPC, + parameter CACHE_SET_NUM = 1024, + parameter CACHE_SET_NUM_LOG = log2b(CACHE_SET_NUM - 1), + parameter CACHE_OFFSET_WIDTH = log2b(CACHE_ENTRY_WIDTH / 8 - 1), + parameter CACHE_TAG_WIDTH = CACHE_ADDR_WIDTH - CACHE_OFFSET_WIDTH - CACHE_SET_NUM_LOG, + parameter PHYSICAL_ADDR_WIDTH = 64, + parameter COUNT_MAX = 2, + parameter COUNT_MAX_LOG = log2b(COUNT_MAX - 1) + 1, + parameter REQ_TAG_NUM = 32, + parameter REQ_TAG_NUM_LOG = log2b(REQ_TAG_NUM - 1), + parameter REORDER_BUFFER_WIDTH = (ICM_CACHE_TYPE == `CACHE_TYPE_QPC) ? CACHE_ENTRY_WIDTH * 2 + COUNT_MAX_LOG : CACHE_ENTRY_WIDTH + COUNT_MAX_LOG +) +( + input wire clk, + input wire rst, + +/***************************************** Interface with CEU *******************************************/ +//CEU Request + input wire ceu_req_valid, + input wire [`CEU_CXT_HEAD_WIDTH - 1 : 0] ceu_req_head, + input wire ceu_req_last, + input wire [`CEU_CXT_DATA_WIDTH - 1 : 0] ceu_req_data, + output wire ceu_req_ready, + +//CEU Response + output wire qpc_rsp_valid, + output wire [`CEU_CXT_HEAD_WIDTH - 1 : 0] qpc_rsp_head, + output wire qpc_rsp_last, + output wire [`CEU_CXT_DATA_WIDTH - 1 : 0] qpc_rsp_data, + input wire qpc_rsp_ready, + +/***************************************** Interface with QPCCache *******************************************/ +//Set QPC ICM Mapping Table Entry + output wire qpc_mapping_set_valid, + output wire [`PAGE_FRAME_WIDTH - 1 : 0] qpc_mapping_set_head, + output wire [`PAGE_FRAME_WIDTH - 1 : 0] qpc_mapping_set_data, + +//ICM Get Req Interface + output wire qpc_cache_get_req_valid, + output wire [`MAX_REQ_TAG_NUM_LOG + `COUNT_MAX_LOG * 2 + `ICM_SPACE_ADDR_WIDTH + `PHY_SPACE_ADDR_WIDTH - 1 : 0] qpc_cache_get_req_head, + input wire qpc_cache_get_req_ready, + +//ICM Get Resp Interface + input wire qpc_cache_get_rsp_valid, + input wire [`MAX_REQ_TAG_NUM_LOG + `COUNT_MAX_LOG * 2 + `ICM_SPACE_ADDR_WIDTH + `PHY_SPACE_ADDR_WIDTH - 1 : 0] qpc_cache_get_rsp_head, + input wire [`CACHE_ENTRY_WIDTH_QPC - 1 : 0] qpc_cache_get_rsp_data, + output wire qpc_cache_get_rsp_ready, + +//Cache Set Req Interface + output wire qpc_cache_set_req_valid, + output wire [`MAX_REQ_TAG_NUM_LOG + `COUNT_MAX_LOG * 2 + `ICM_SPACE_ADDR_WIDTH + `PHY_SPACE_ADDR_WIDTH - 1 : 0] qpc_cache_set_req_head, + output wire [`CACHE_ENTRY_WIDTH_QPC - 1 : 0] qpc_cache_set_req_data, + input wire qpc_cache_set_req_ready, + +//ICM Address Translation Interface + output wire qpc_icm_mapping_lookup_valid, + output wire [log2b(`ICM_ENTRY_NUM_QPC - 1) - 1 : 0] qpc_icm_mapping_lookup_head, + input wire qpc_icm_mapping_lookup_ready, + + input wire qpc_icm_mapping_rsp_valid, + input wire [`ICM_SPACE_ADDR_WIDTH - 1 : 0] qpc_icm_mapping_rsp_icm_addr, + input wire [`PHY_SPACE_ADDR_WIDTH - 1 : 0] qpc_icm_mapping_rsp_phy_addr, + output wire qpc_icm_mapping_rsp_ready, + + output wire [`ICM_SPACE_ADDR_WIDTH - 1 : 0] qpc_base, + +/***************************************** Interface with CQCCache *******************************************/ +//Set CQC ICM Mapping Table Entry + output wire cqc_mapping_set_valid, + output wire [`PAGE_FRAME_WIDTH - 1 : 0] cqc_mapping_set_head, + output wire [`PAGE_FRAME_WIDTH - 1 : 0] cqc_mapping_set_data, + +//Cache Set Req Interface + output wire cqc_cache_set_req_valid, + output wire [`MAX_REQ_TAG_NUM_LOG + `COUNT_MAX_LOG * 2 + `ICM_SPACE_ADDR_WIDTH + `PHY_SPACE_ADDR_WIDTH - 1 : 0] cqc_cache_set_req_head, + output wire [`CACHE_ENTRY_WIDTH_CQC - 1 : 0] cqc_cache_set_req_data, + input wire cqc_cache_set_req_ready, + +//ICM Address Translation Interface + output wire cqc_icm_mapping_lookup_valid, + output wire [log2b(`ICM_ENTRY_NUM_CQC - 1) - 1 : 0] cqc_icm_mapping_lookup_head, + input wire cqc_icm_mapping_lookup_ready, + + input wire cqc_icm_mapping_rsp_valid, + input wire [`ICM_SPACE_ADDR_WIDTH - 1 : 0] cqc_icm_mapping_rsp_icm_addr, + input wire [`PHY_SPACE_ADDR_WIDTH - 1 : 0] cqc_icm_mapping_rsp_phy_addr, + output wire cqc_icm_mapping_rsp_ready, + + output wire [`ICM_SPACE_ADDR_WIDTH - 1 : 0] cqc_base, + +/***************************************** Interface with EQCCache *******************************************/ +//Set CQC ICM Mapping Table Entry + output wire eqc_mapping_set_valid, + output wire [`PAGE_FRAME_WIDTH - 1 : 0] eqc_mapping_set_head, + output wire [`PAGE_FRAME_WIDTH - 1 : 0] eqc_mapping_set_data, + +//Cache Set Req Interface + output wire eqc_cache_set_req_valid, + output wire [`MAX_REQ_TAG_NUM_LOG + `COUNT_MAX_LOG * 2 + `ICM_SPACE_ADDR_WIDTH + `PHY_SPACE_ADDR_WIDTH - 1 : 0] eqc_cache_set_req_head, + output wire [`CACHE_ENTRY_WIDTH_EQC - 1 : 0] eqc_cache_set_req_data, + input wire eqc_cache_set_req_ready, + +//ICM Address Translation Interface + output wire eqc_icm_mapping_lookup_valid, + output wire [log2b(`ICM_ENTRY_NUM_EQC - 1) - 1 : 0] eqc_icm_mapping_lookup_head, + input wire eqc_icm_mapping_lookup_ready, + + input wire eqc_icm_mapping_rsp_valid, + input wire [`ICM_SPACE_ADDR_WIDTH - 1 : 0] eqc_icm_mapping_rsp_icm_addr, + input wire [`PHY_SPACE_ADDR_WIDTH - 1 : 0] eqc_icm_mapping_rsp_phy_addr, + output wire eqc_icm_mapping_rsp_ready, + + output wire [`ICM_SPACE_ADDR_WIDTH - 1 : 0] eqc_base + + +); + +/*------------------------------------------- Input/Output Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Macros Definition : Begin ---------------------------------------*/ + +/*------------------------------------------- Local Macros Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Variables Definition : Begin ------------------------------------*/ +wire qpc_req_valid; +wire [`CEU_CXT_HEAD_WIDTH - 1 : 0] qpc_req_head; +wire qpc_req_last; +wire [`CEU_CXT_DATA_WIDTH - 1 : 0] qpc_req_data; +wire qpc_req_ready; + +wire cqc_req_valid; +wire [`CEU_CXT_HEAD_WIDTH - 1 : 0] cqc_req_head; +wire cqc_req_last; +wire [`CEU_CXT_DATA_WIDTH - 1 : 0] cqc_req_data; +wire cqc_req_ready; + +wire eqc_req_valid; +wire [`CEU_CXT_HEAD_WIDTH - 1 : 0] eqc_req_head; +wire eqc_req_last; +wire [`CEU_CXT_DATA_WIDTH - 1 : 0] eqc_req_data; +wire eqc_req_ready; + +wire mapping_req_valid; +wire [`CEU_CXT_HEAD_WIDTH - 1 : 0] mapping_req_head; +wire mapping_req_last; +wire [`CEU_CXT_DATA_WIDTH - 1 : 0] mapping_req_data; +wire mapping_req_ready; +/*------------------------------------------- Local Variables Definition : End --------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : Begin ---------------------------------------*/ +SWAccCMCtl_Thread_1 SWAccCMCtl_Thread_1_Inst( + .clk ( clk ), + .rst ( rst ), + + .ceu_req_valid ( ceu_req_valid ), + .ceu_req_head ( ceu_req_head ), + .ceu_req_last ( ceu_req_last ), + .ceu_req_data ( ceu_req_data ), + .ceu_req_ready ( ceu_req_ready ), + + .qpc_req_valid ( qpc_req_valid ), + .qpc_req_head ( qpc_req_head ), + .qpc_req_last ( qpc_req_last ), + .qpc_req_data ( qpc_req_data ), + .qpc_req_ready ( qpc_req_ready ), + + .cqc_req_valid ( cqc_req_valid ), + .cqc_req_head ( cqc_req_head ), + .cqc_req_last ( cqc_req_last ), + .cqc_req_data ( cqc_req_data ), + .cqc_req_ready ( cqc_req_ready ), + + .eqc_req_valid ( eqc_req_valid ), + .eqc_req_head ( eqc_req_head ), + .eqc_req_last ( eqc_req_last ), + .eqc_req_data ( eqc_req_data ), + .eqc_req_ready ( eqc_req_ready ), + + .mapping_req_valid ( mapping_req_valid ), + .mapping_req_head ( mapping_req_head ), + .mapping_req_last ( mapping_req_last ), + .mapping_req_data ( mapping_req_data ), + .mapping_req_ready ( mapping_req_ready ) +); + +SWAccCMCtl_Thread_2 SWAccCMCtl_Thread_2_Inst ( + .clk ( clk ), + .rst ( rst ), + + .qpc_req_valid ( qpc_req_valid ), + .qpc_req_head ( qpc_req_head ), + .qpc_req_last ( qpc_req_last ), + .qpc_req_data ( qpc_req_data ), + .qpc_req_ready ( qpc_req_ready ), + + .icm_get_req_valid ( qpc_cache_get_req_valid ), + .icm_get_req_head ( qpc_cache_get_req_head ), + .icm_get_req_ready ( qpc_cache_get_req_ready ), + + .icm_get_rsp_valid ( qpc_cache_get_rsp_valid ), + .icm_get_rsp_head ( qpc_cache_get_rsp_head ), + .icm_get_rsp_data ( qpc_cache_get_rsp_data ), + .icm_get_rsp_ready ( qpc_cache_get_rsp_ready ), + + .icm_set_req_valid ( qpc_cache_set_req_valid ), + .icm_set_req_head ( qpc_cache_set_req_head ), + .icm_set_req_data ( qpc_cache_set_req_data ), + .icm_set_req_ready ( qpc_cache_set_req_ready ), + + .icm_mapping_lookup_valid ( qpc_icm_mapping_lookup_valid ), + .icm_mapping_lookup_head ( qpc_icm_mapping_lookup_head ), + .icm_mapping_lookup_ready ( qpc_icm_mapping_lookup_ready ), + + .icm_mapping_rsp_valid ( qpc_icm_mapping_rsp_valid ), + .icm_mapping_rsp_icm_addr ( qpc_icm_mapping_rsp_icm_addr ), + .icm_mapping_rsp_phy_addr ( qpc_icm_mapping_rsp_phy_addr ), + .icm_mapping_rsp_ready ( qpc_icm_mapping_rsp_ready ), + + .qpc_rsp_valid ( qpc_rsp_valid ), + .qpc_rsp_head ( qpc_rsp_head ), + .qpc_rsp_last ( qpc_rsp_last ), + .qpc_rsp_data ( qpc_rsp_data ), + .qpc_rsp_ready ( qpc_rsp_ready ) +); + +SWAccCMCtl_Thread_3 SWAccCMCtl_Thread_3_Inst( + .clk ( clk ), + .rst ( rst ), + + .cqc_req_valid ( cqc_req_valid ), + .cqc_req_head ( cqc_req_head ), + .cqc_req_last ( cqc_req_last ), + .cqc_req_data ( cqc_req_data ), + .cqc_req_ready ( cqc_req_ready ), + + .cache_set_req_valid ( cqc_cache_set_req_valid ), + .cache_set_req_head ( cqc_cache_set_req_head ), + .cache_set_req_data ( cqc_cache_set_req_data ), + .cache_set_req_ready ( cqc_cache_set_req_ready ), + + .icm_mapping_lookup_valid ( cqc_icm_mapping_lookup_valid ), + .icm_mapping_lookup_head ( cqc_icm_mapping_lookup_head ), + .icm_mapping_lookup_ready ( cqc_icm_mapping_lookup_ready ), + + .icm_mapping_rsp_valid ( cqc_icm_mapping_rsp_valid ), + .icm_mapping_rsp_icm_addr ( cqc_icm_mapping_rsp_icm_addr ), + .icm_mapping_rsp_phy_addr ( cqc_icm_mapping_rsp_phy_addr ), + .icm_mapping_rsp_ready ( cqc_icm_mapping_rsp_ready ) +); + +SWAccCMCtl_Thread_4 SWAccCMCtl_Thread_4_Inst ( + .clk ( clk ), + .rst ( rst ), + + .eqc_req_valid ( eqc_req_valid ), + .eqc_req_head ( eqc_req_head ), + .eqc_req_last ( eqc_req_last ), + .eqc_req_data ( eqc_req_data ), + .eqc_req_ready ( eqc_req_ready ), + + .cache_set_req_valid ( eqc_cache_set_req_valid ), + .cache_set_req_head ( eqc_cache_set_req_head ), + .cache_set_req_data ( eqc_cache_set_req_data ), + .cache_set_req_ready ( eqc_cache_set_req_ready ), + + .icm_mapping_lookup_valid ( eqc_icm_mapping_lookup_valid ), + .icm_mapping_lookup_head ( eqc_icm_mapping_lookup_head ), + .icm_mapping_lookup_ready ( eqc_icm_mapping_lookup_ready ), + + .icm_mapping_rsp_valid ( eqc_icm_mapping_rsp_valid ), + .icm_mapping_rsp_icm_addr ( eqc_icm_mapping_rsp_icm_addr ), + .icm_mapping_rsp_phy_addr ( eqc_icm_mapping_rsp_phy_addr ), + .icm_mapping_rsp_ready ( eqc_icm_mapping_rsp_ready ) +); + +SWAccCMCtl_Thread_5 +#( + .ICM_PAGE_NUM ( ICM_PAGE_NUM ) +) +SWAccCMCtl_Thread_5_Inst( + .clk ( clk ), + .rst ( rst ), + + .map_req_valid ( mapping_req_valid ), + .map_req_head ( mapping_req_head ), + .map_req_last ( mapping_req_last ), + .map_req_data ( mapping_req_data ), + .map_req_ready ( mapping_req_ready ), + + .qpc_mapping_set_valid ( qpc_mapping_set_valid ), + .qpc_mapping_set_head ( qpc_mapping_set_head ), + .qpc_mapping_set_data ( qpc_mapping_set_data ), + + .cqc_mapping_set_valid ( cqc_mapping_set_valid ), + .cqc_mapping_set_head ( cqc_mapping_set_head ), + .cqc_mapping_set_data ( cqc_mapping_set_data ), + + .eqc_mapping_set_valid ( eqc_mapping_set_valid ), + .eqc_mapping_set_head ( eqc_mapping_set_head ), + .eqc_mapping_set_data ( eqc_mapping_set_data ), + + .qpc_base ( qpc_base ), + .cqc_base ( cqc_base ), + .eqc_base ( eqc_base ) +); +/*------------------------------------------- Submodules Instatiation : End -----------------------------------------*/ + +/*------------------------------------------- State Machine Definition : Begin --------------------------------------*/ +/*------------------------------------------- State Machine Definition : End ----------------------------------------*/ + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ + +/*------------------------------------------- Local Macros Undef : Begin --------------------------------------------*/ +/*------------------------------------------- Local Macros Undef : End ----------------------------------------------*/ + +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/ICMMgt/CxtMgt/SWAccCMCtl/SWAccCMCtl_Thread_1.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/ICMMgt/CxtMgt/SWAccCMCtl/SWAccCMCtl_Thread_1.v new file mode 100644 index 0000000000000000000000000000000000000000..2067cedc2ac1fa87fa5bc51c3b27b57098527619 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/ICMMgt/CxtMgt/SWAccCMCtl/SWAccCMCtl_Thread_1.v @@ -0,0 +1,194 @@ +/*------------------------------------------- Module Description : Begin ---------------------------------------------- +Name: SWAccCMCtl_Thread_1 +Author: YangFan +Function: Demux CEU command to thread_2(QPC processing), thread_3(CQC processing), thread_4(EQC processing), thread_5(Cxt ICM Mapping). +--------------------------------------------- Module Decription : End -----------------------------------------------*/ + +/*------------------------------------------- Timescale Definition : Begin ------------------------------------------*/ +`timescale 1ns / 1ps +/*------------------------------------------- Timescale Definition : End --------------------------------------------*/ + +/*------------------------------------------- Included Files : Begin ------------------------------------------------*/ +`include "protocol_engine_def.vh" +/*------------------------------------------- Included Files : End --------------------------------------------------*/ + +/*------------------------------------------- Input/Output Definition : Begin ---------------------------------------*/ +module SWAccCMCtl_Thread_1 +( + input wire clk, + input wire rst, + +//Interface with CEU + input wire ceu_req_valid, + input wire [`CEU_CXT_HEAD_WIDTH - 1 : 0] ceu_req_head, + input wire ceu_req_last, + input wire [`CEU_CXT_DATA_WIDTH - 1 : 0] ceu_req_data, + output wire ceu_req_ready, + +//Interface with SWAccCMCtl_Thread_2 + output wire qpc_req_valid, + output wire [`CEU_CXT_HEAD_WIDTH - 1 : 0] qpc_req_head, + output wire qpc_req_last, + output wire [`CEU_CXT_DATA_WIDTH - 1 : 0] qpc_req_data, + input wire qpc_req_ready, + +//Interface with SWAccCMCtl_Thread_3 + output wire cqc_req_valid, + output wire [`CEU_CXT_HEAD_WIDTH - 1 : 0] cqc_req_head, + output wire cqc_req_last, + output wire [`CEU_CXT_DATA_WIDTH - 1 : 0] cqc_req_data, + input wire cqc_req_ready, + +//Interface with SWAccCMCtl_Thread_4 + output wire eqc_req_valid, + output wire [`CEU_CXT_HEAD_WIDTH - 1 : 0] eqc_req_head, + output wire eqc_req_last, + output wire [`CEU_CXT_DATA_WIDTH - 1 : 0] eqc_req_data, + input wire eqc_req_ready, + +//Interface with SWAccCMCtl_Thread_5 + output wire mapping_req_valid, + output wire [`CEU_CXT_HEAD_WIDTH - 1 : 0] mapping_req_head, + output wire mapping_req_last, + output wire [`CEU_CXT_DATA_WIDTH - 1 : 0] mapping_req_data, + input wire mapping_req_ready + +); +/*------------------------------------------- Input/Output Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Macros Definition : Begin ---------------------------------------*/ +`define CEU_CMD_TYPE_OFFSET 127:124 +/*------------------------------------------- Local Macros Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Variables Definition : Begin ------------------------------------*/ +wire dispatch_req_valid; +wire [`CEU_CXT_HEAD_WIDTH - 1 : 0] dispatch_req_head; +wire dispatch_req_last; +wire [`CEU_CXT_DATA_WIDTH - 1 : 0] dispatch_req_data; +wire dispatch_req_ready; +/*------------------------------------------- Local Variables Definition : End --------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : Begin ---------------------------------------*/ +stream_fifo #( + .TUSER_WIDTH (`CEU_CXT_HEAD_WIDTH ), + .TDATA_WIDTH (`CEU_CXT_DATA_WIDTH ) +) +ceu_req_st +( + .clk (clk ), + .rst (rst ), + + .axis_tvalid (ceu_req_valid ), + .axis_tlast (ceu_req_last ), + .axis_tuser (ceu_req_head ), + .axis_tdata (ceu_req_data ), + .axis_tready (ceu_req_ready ), + .axis_tstart (1'b0 ), + .axis_tkeep ('d0 ), + + .in_reg_tvalid (dispatch_req_valid ), + .in_reg_tlast (dispatch_req_last ), + .in_reg_tuser (dispatch_req_head ), + .in_reg_tdata (dispatch_req_data ), + .in_reg_tkeep ( ), + .in_reg_tstart ( ), + .in_reg_tready (dispatch_req_ready ) + /* -------output in_reg inteface{end}------- */ +); +/*------------------------------------------- Submodules Instatiation : End -----------------------------------------*/ + +/*------------------------------------------- State Machine Definition : Begin --------------------------------------*/ +reg [2:0] cur_state; +reg [2:0] next_state; + +parameter [2:0] IDLE_s = 3'd1, + QPC_s = 3'd2, + CQC_s = 3'd3, + EQC_s = 3'd4, + MAPPING_s = 3'd5; + +always @(posedge clk or posedge rst) begin + if (rst) begin + cur_state <= IDLE_s; + end + else begin + cur_state <= next_state; + end +end + +always @(*) begin + case(cur_state) + IDLE_s: if(dispatch_req_valid && (dispatch_req_head[`CEU_CMD_TYPE_OFFSET] == `RD_QP_CXT || dispatch_req_head[`CEU_CMD_TYPE_OFFSET] == `WR_QP_CXT)) begin + next_state = QPC_s; + end + else if(dispatch_req_valid && dispatch_req_head[`CEU_CMD_TYPE_OFFSET] == `WR_CQ_CXT) begin + next_state = CQC_s; + end + else if(dispatch_req_valid && dispatch_req_head[`CEU_CMD_TYPE_OFFSET] == `WR_EQ_CXT) begin + next_state = EQC_s; + end + else if(dispatch_req_valid && (dispatch_req_head[`CEU_CMD_TYPE_OFFSET] == `WR_ICMMAP_CXT || dispatch_req_head[`CEU_CMD_TYPE_OFFSET] == `MAP_ICM_CXT)) begin + next_state = MAPPING_s; + end + else begin + next_state = IDLE_s; + end + QPC_s: next_state = (dispatch_req_last && dispatch_req_ready) ? IDLE_s : QPC_s; + CQC_s: next_state = (dispatch_req_last && dispatch_req_ready) ? IDLE_s : CQC_s; + EQC_s: next_state = (dispatch_req_last && dispatch_req_ready) ? IDLE_s : EQC_s; + MAPPING_s: next_state = (dispatch_req_last && dispatch_req_ready) ? IDLE_s : MAPPING_s; + default: next_state = IDLE_s; + endcase +end +/*------------------------------------------- State Machine Definition : End ----------------------------------------*/ + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ +assign dispatch_req_ready = (cur_state == QPC_s) ? qpc_req_ready : + (cur_state == CQC_s) ? cqc_req_ready : + (cur_state == EQC_s) ? eqc_req_ready : + (cur_state == MAPPING_s) ? mapping_req_ready : 'd0; + +assign qpc_req_valid = (cur_state == QPC_s) ? dispatch_req_valid : 'd0; +assign qpc_req_head = (cur_state == QPC_s) ? dispatch_req_head : 'd0; +assign qpc_req_last = (cur_state == QPC_s) ? dispatch_req_last : 'd0; +assign qpc_req_data = (cur_state == QPC_s) ? dispatch_req_data : 'd0; + +assign cqc_req_valid = (cur_state == CQC_s) ? dispatch_req_valid : 'd0; +assign cqc_req_head = (cur_state == CQC_s) ? dispatch_req_head : 'd0; +assign cqc_req_last = (cur_state == CQC_s) ? dispatch_req_last : 'd0; +assign cqc_req_data = (cur_state == CQC_s) ? dispatch_req_data : 'd0; + +assign eqc_req_valid = (cur_state == EQC_s) ? dispatch_req_valid : 'd0; +assign eqc_req_head = (cur_state == EQC_s) ? dispatch_req_head : 'd0; +assign eqc_req_last = (cur_state == EQC_s) ? dispatch_req_last : 'd0; +assign eqc_req_data = (cur_state == EQC_s) ? dispatch_req_data : 'd0; + +assign mapping_req_valid = (cur_state == MAPPING_s) ? dispatch_req_valid : 'd0; +assign mapping_req_head = (cur_state == MAPPING_s) ? dispatch_req_head : 'd0; +assign mapping_req_last = (cur_state == MAPPING_s) ? dispatch_req_last : 'd0; +assign mapping_req_data = (cur_state == MAPPING_s) ? dispatch_req_data : 'd0; +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ + +/*------------------------------------------- Local Macros Undef : Begin --------------------------------------------*/ +`undef CEU_CMD_TYPE_OFFSET +/*------------------------------------------- Local Macros Undef : End ----------------------------------------------*/ + +`ifdef ILA_ON + ila_ceu_req ila_cxt_req_inst( + .clk (clk), + + .probe0(ceu_req_valid), + .probe1(ceu_req_head), + .probe2(ceu_req_data), + .probe3(ceu_req_last), + .probe4(ceu_req_ready), + + .probe5(dispatch_req_valid), + .probe6(dispatch_req_head), + .probe7(dispatch_req_data), + .probe8(dispatch_req_last), + .probe9(dispatch_req_ready) + ); +`endif + +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/ICMMgt/CxtMgt/SWAccCMCtl/SWAccCMCtl_Thread_2.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/ICMMgt/CxtMgt/SWAccCMCtl/SWAccCMCtl_Thread_2.v new file mode 100644 index 0000000000000000000000000000000000000000..cc3bd078fa201ad0ef828c5ec7d03e47a0091147 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/ICMMgt/CxtMgt/SWAccCMCtl/SWAccCMCtl_Thread_2.v @@ -0,0 +1,572 @@ +/*------------------------------------------- Module Description : Begin ---------------------------------------------- +Name: SWAccCMCtl_Thread_2 +Author: YangFan +Function: Handle QPC Rd/Wr Command from CEU. +--------------------------------------------- Module Decription : End -----------------------------------------------*/ + +/*------------------------------------------- Timescale Definition : Begin ------------------------------------------*/ +`timescale 1ns / 1ps +/*------------------------------------------- Timescale Definition : End --------------------------------------------*/ + +/*------------------------------------------- Included Files : Begin ------------------------------------------------*/ +`include "protocol_engine_def.vh" +/*------------------------------------------- Included Files : End --------------------------------------------------*/ + + + +/*------------------------------------------- Input/Output Definition : Begin ---------------------------------------*/ +module SWAccCMCtl_Thread_2 ( + input wire clk, + input wire rst, + +//Interface with SWAccCMCtl_Thread_0 + input wire qpc_req_valid, + input wire [`CEU_CXT_HEAD_WIDTH - 1 : 0] qpc_req_head, + input wire qpc_req_last, + input wire [`CEU_CXT_DATA_WIDTH - 1 : 0] qpc_req_data, + output wire qpc_req_ready, + +//Interface with QPCCache(ICMCache) +//ICM Get Req Interface + output wire icm_get_req_valid, + output wire [`COUNT_MAX_LOG * 2 + `MAX_REQ_TAG_NUM_LOG + `ICM_SPACE_ADDR_WIDTH + `PHY_SPACE_ADDR_WIDTH - 1 : 0] icm_get_req_head, + input wire icm_get_req_ready, + +//ICM Get Resp Interface + input wire icm_get_rsp_valid, + input wire [`COUNT_MAX_LOG * 2 + `MAX_REQ_TAG_NUM_LOG + `ICM_SPACE_ADDR_WIDTH + `PHY_SPACE_ADDR_WIDTH - 1 : 0] icm_get_rsp_head, + input wire [`CACHE_ENTRY_WIDTH_QPC - 1 : 0] icm_get_rsp_data, + output wire icm_get_rsp_ready, + +//Cache Set Req Interface + output wire icm_set_req_valid, + output wire [`COUNT_MAX_LOG * 2 + `MAX_REQ_TAG_NUM_LOG + `ICM_SPACE_ADDR_WIDTH + `PHY_SPACE_ADDR_WIDTH - 1 : 0] icm_set_req_head, + output wire [`CACHE_ENTRY_WIDTH_QPC - 1 : 0] icm_set_req_data, + input wire icm_set_req_ready, + +//ICM Address Translation Interface + output wire icm_mapping_lookup_valid, + output wire [log2b(`ICM_ENTRY_NUM_QPC - 1) - 1 : 0] icm_mapping_lookup_head, + input wire icm_mapping_lookup_ready, + + input wire icm_mapping_rsp_valid, + input wire [`ICM_SPACE_ADDR_WIDTH - 1 : 0] icm_mapping_rsp_icm_addr, + input wire [`PHY_SPACE_ADDR_WIDTH - 1 : 0] icm_mapping_rsp_phy_addr, + output wire icm_mapping_rsp_ready, + +//Interface with CEU(Rd QPC Response) + output wire qpc_rsp_valid, + output wire [`CEU_CXT_HEAD_WIDTH - 1 : 0] qpc_rsp_head, + output wire qpc_rsp_last, + output wire [`CEU_CXT_DATA_WIDTH - 1 : 0] qpc_rsp_data, + input wire qpc_rsp_ready +); +/*------------------------------------------- Input/Output Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Macros Definition : Begin ---------------------------------------*/ +`define CEU_CMD_TYPE_OFFSET 127:124 +`define CEU_CMD_OPCODE_OFFSET 123:120 +`define CEU_CMD_INDEX_OFFSET 95:64 +`define QPC_PIECE_NUM 6 //192B / 32B(256bit data width) + +`define WR_QPC_SERVICE_TYPE_OFFSET 32 * 6 - 8 - 1 : 32 * 6 - 16 +`define WR_QPC_STATE_OFFSET 32 * 6 - 1 : 32 * 6 - 4 +`define WR_QPC_MTU_MSGMAX_OFFSET 32 * 5 - 1 : 32 * 5 - 8 +`define WR_QPC_SQ_ENTRY_SZ_LOG_OFFSET 32 * 5 - 16 - 1 : 32 * 5 - 24 +`define WR_QPC_RQ_ENTRY_SZ_LOG_OFFSET 32 * 5 - 8 - 1 : 32 * 5 - 16 +`define WR_QPC_DST_QPN_OFFSET 32 * 2 - 1 : 32 * 1 +`define WR_QPC_PKEY_INDEX_OFFSET 32 * 1 - 6 - 1 : 32 * 1 - 8 +`define WR_QPC_PORT_INDEX_OFFSET 32 * 1 - 26 - 1 : 32 * 1 - 32 +`define WR_QPC_CQN_SND_OFFSET 32 * 4 - 1 : 32 * 3 +`define WR_QPC_CQN_RCV_OFFSET 32 * 5 - 1 : 32 * 4 +`define WR_QPC_QP_PD_OFFSET 32 * 1 - 1 : 32 * 0 +`define WR_QPC_SQ_LKEY_OFFSET 32 * 3 - 1 : 32 * 2 +`define WR_QPC_SQ_LENGTH_OFFSET 32 * 2 - 1 : 32 * 1 +`define WR_QPC_RQ_LKEY_OFFSET 32 * 4 - 1 : 32 * 3 +`define WR_QPC_RQ_LENGTH_OFFSET 32 * 3 - 1 : 32 * 2 +`define WR_QPC_DMAC_LOW_DLID_OFFSET 32 * 1 - 1 : 32 * 1 - 16 +`define WR_QPC_SMAC_LOW_SLID_OFFSET 32 * 1 - 16 - 1 : 32 * 0 +`define WR_QPC_DMAC_HIGH_OFFSET 32 * 7 - 1 : 32 * 6 +`define WR_QPC_SMAC_HIGH_OFFSET 32 * 8 - 1 : 32 * 7 +`define WR_QPC_DIP_OFFSET 32 * 5 - 1 : 32 * 4 +`define WR_QPC_SIP_OFFSET 32 * 6 - 1 : 32 * 5 +/*------------------------------------------- Local Macros Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Variables Definition : Begin ------------------------------------*/ +reg [3:0] qpc_rd_piece_count; +reg [3:0] qpc_wr_piece_count; + +reg [`CEU_CXT_HEAD_WIDTH - 1 : 0] qpc_req_head_diff; + +reg [`CACHE_ENTRY_WIDTH_QPC - 1 : 0] cache_entry; + +reg [`ICM_SPACE_ADDR_WIDTH - 1 : 0] icm_addr; +reg [`PHY_SPACE_ADDR_WIDTH - 1 : 0] phy_addr; + +wire [`COUNT_MAX_LOG - 1 : 0] count_max; +wire [`COUNT_MAX_LOG - 1 : 0] count_index; + +wire [`MAX_REQ_TAG_NUM_LOG - 1 : 0] req_tag; + +//QPC Info +reg [2:0] wr_service_type; +reg [2:0] wr_state; +reg [7:0] wr_mtu_msgmax; +reg [7:0] wr_sq_entry_sz_log; +reg [7:0] wr_rq_entry_sz_log; +reg [15:0] wr_dst_qpn; +reg [7:0] wr_pkey_index; +reg [7:0] wr_port_index; +reg [15:0] wr_cqn_snd; +reg [15:0] wr_cqn_rcv; +reg [31:0] wr_qp_pd; +reg [31:0] wr_sq_lkey; +reg [31:0] wr_sq_length; +reg [31:0] wr_rq_lkey; +reg [31:0] wr_rq_length; +reg [15:0] wr_dmac_low_dlid; +reg [15:0] wr_smac_low_slid; +reg [31:0] wr_dmac_high; +reg [31:0] wr_smac_high; +reg [31:0] wr_dip; +reg [31:0] wr_sip; + +wire [2:0] rd_service_type; +wire [3:0] rd_state; +wire [7:0] rd_mtu_msgmax; +wire [7:0] rd_sq_entry_sz_log; +wire [7:0] rd_rq_entry_sz_log; +wire [15:0] rd_dst_qpn; +wire [7:0] rd_pkey_index; +wire [7:0] rd_port_index; +wire [15:0] rd_cqn_snd; +wire [15:0] rd_cqn_rcv; +wire [31:0] rd_qp_pd; +wire [31:0] rd_sq_lkey; +wire [31:0] rd_sq_length; +wire [31:0] rd_rq_lkey; +wire [31:0] rd_rq_length; +wire [15:0] rd_dmac_low_dlid; +wire [15:0] rd_smac_low_slid; +wire [31:0] rd_dmac_high; +wire [31:0] rd_smac_high; +wire [31:0] rd_dip; +wire [31:0] rd_sip; +/*------------------------------------------- Local Variables Definition : End --------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : Begin ---------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : End -----------------------------------------*/ + +/*------------------------------------------- State Machine Definition : Begin --------------------------------------*/ +reg [3:0] cur_state; +reg [3:0] next_state; + +parameter [3:0] IDLE_s = 4'd1, + ADDR_REQ_s = 4'd2, + ADDR_RSP_s = 4'd3, + CACHE_GET_s = 4'd4, + CACHE_RSP_s = 4'd5, + CEU_RSP_s = 4'd6, + QPC_COLLECT_s = 4'd7, + CACHE_SET_s = 4'd8; + +always @(posedge clk or posedge rst) begin + if(rst) begin + cur_state <= IDLE_s; + end + else begin + cur_state <= next_state; + end +end + +always @(*) begin + case(cur_state) + IDLE_s: if(qpc_req_valid) begin + next_state = ADDR_REQ_s; + end + else begin + next_state = IDLE_s; + end + ADDR_REQ_s: if(icm_mapping_lookup_valid && icm_mapping_lookup_ready) begin + next_state = ADDR_RSP_s; + end + else begin + next_state = ADDR_REQ_s; + end + ADDR_RSP_s: if(icm_mapping_rsp_valid) begin + if(qpc_req_valid && qpc_req_head_diff[`CEU_CMD_TYPE_OFFSET] == `RD_QP_CXT) begin + next_state = CACHE_GET_s; + end + else if(qpc_req_valid && qpc_req_head_diff[`CEU_CMD_TYPE_OFFSET] == `WR_QP_CXT) begin + next_state = QPC_COLLECT_s; + end + else begin + next_state = IDLE_s; + end + end + else begin + next_state = ADDR_RSP_s; + end + CACHE_GET_s: if(icm_get_req_valid && icm_get_req_ready) begin + next_state = CACHE_RSP_s; + end + else begin + next_state = CACHE_GET_s; + end + CACHE_RSP_s: if(icm_get_rsp_valid && icm_get_rsp_ready) begin + next_state = CEU_RSP_s; + end + else begin + next_state = CACHE_RSP_s; + end + CEU_RSP_s: if(qpc_rd_piece_count == `QPC_PIECE_NUM && qpc_rsp_valid && qpc_rsp_ready) begin + next_state = IDLE_s; + end + else begin + next_state = CEU_RSP_s; + end + QPC_COLLECT_s: if(qpc_wr_piece_count == `QPC_PIECE_NUM && qpc_req_valid && qpc_req_ready) begin + next_state = CACHE_SET_s; + end + else begin + next_state = QPC_COLLECT_s; + end + CACHE_SET_s: if(icm_set_req_valid && icm_set_req_ready) begin + next_state = IDLE_s; + end + else begin + next_state = CACHE_SET_s; + end + default: next_state = IDLE_s; + endcase +end +/*------------------------------------------- State Machine Definition : End ----------------------------------------*/ + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ +//-- Wr QPC Info -- +always @(posedge clk or posedge rst) begin + if(rst) begin + wr_service_type <= 'd0; + wr_state <= 'd0; + wr_mtu_msgmax <= 'd0; + wr_sq_entry_sz_log <= 'd0; + wr_rq_entry_sz_log <= 'd0; + wr_dst_qpn <= 'd0; + wr_pkey_index <= 'd0; + wr_port_index <= 'd0; + wr_cqn_snd <= 'd0; + wr_cqn_rcv <= 'd0; + wr_qp_pd <= 'd0; + wr_sq_lkey <= 'd0; + wr_sq_length <= 'd0; + wr_rq_lkey <= 'd0; + wr_rq_length <= 'd0; + wr_dmac_low_dlid <= 'd0; + wr_smac_low_slid <= 'd0; + wr_dmac_high <= 'd0; + wr_smac_high <= 'd0; + wr_dip <= 'd0; + wr_sip <= 'd0; + end + else if(cur_state == IDLE_s) begin + wr_service_type <= 'd0; + wr_state <= 'd0; + wr_mtu_msgmax <= 'd0; + wr_sq_entry_sz_log <= 'd0; + wr_rq_entry_sz_log <= 'd0; + wr_dst_qpn <= 'd0; + wr_pkey_index <= 'd0; + wr_port_index <= 'd0; + wr_cqn_snd <= 'd0; + wr_cqn_rcv <= 'd0; + wr_qp_pd <= 'd0; + wr_sq_lkey <= 'd0; + wr_sq_length <= 'd0; + wr_rq_lkey <= 'd0; + wr_rq_length <= 'd0; + wr_dmac_low_dlid <= 'd0; + wr_smac_low_slid <= 'd0; + wr_dmac_high <= 'd0; + wr_smac_high <= 'd0; + wr_dip <= 'd0; + wr_sip <= 'd0; + end + else if(cur_state == QPC_COLLECT_s && qpc_req_valid) begin + wr_service_type <= (qpc_wr_piece_count == 1) ? qpc_req_data[`WR_QPC_SERVICE_TYPE_OFFSET] : wr_service_type; + wr_state <= (qpc_wr_piece_count == 1) ? qpc_req_data[`WR_QPC_STATE_OFFSET] : wr_state; + wr_mtu_msgmax <= (qpc_wr_piece_count == 1) ? qpc_req_data[`WR_QPC_MTU_MSGMAX_OFFSET] : wr_mtu_msgmax; + wr_sq_entry_sz_log <= (qpc_wr_piece_count == 1) ? qpc_req_data[`WR_QPC_SQ_ENTRY_SZ_LOG_OFFSET] : wr_sq_entry_sz_log; + wr_rq_entry_sz_log <= (qpc_wr_piece_count == 1) ? qpc_req_data[`WR_QPC_RQ_ENTRY_SZ_LOG_OFFSET] : wr_rq_entry_sz_log; + wr_dst_qpn <= (qpc_wr_piece_count == 1) ? qpc_req_data[`WR_QPC_DST_QPN_OFFSET] : wr_dst_qpn; + wr_pkey_index <= (qpc_wr_piece_count == 2) ? qpc_req_data[`WR_QPC_PKEY_INDEX_OFFSET] : wr_pkey_index; + wr_port_index <= (qpc_wr_piece_count == 2) ? qpc_req_data[`WR_QPC_PORT_INDEX_OFFSET] : wr_port_index; + wr_cqn_snd <= (qpc_wr_piece_count == 4) ? qpc_req_data[`WR_QPC_CQN_SND_OFFSET] : wr_cqn_snd; + wr_cqn_rcv <= (qpc_wr_piece_count == 5) ? qpc_req_data[`WR_QPC_CQN_RCV_OFFSET] : wr_cqn_rcv; + wr_qp_pd <= (qpc_wr_piece_count == 3) ? qpc_req_data[`WR_QPC_QP_PD_OFFSET] : wr_qp_pd; + wr_sq_lkey <= (qpc_wr_piece_count == 4) ? qpc_req_data[`WR_QPC_SQ_LKEY_OFFSET] : wr_sq_lkey; + wr_sq_length <= (qpc_wr_piece_count == 4) ? qpc_req_data[`WR_QPC_SQ_LENGTH_OFFSET] : wr_sq_length; + wr_rq_lkey <= (qpc_wr_piece_count == 5) ? qpc_req_data[`WR_QPC_RQ_LKEY_OFFSET] : wr_rq_lkey; + wr_rq_length <= (qpc_wr_piece_count == 5) ? qpc_req_data[`WR_QPC_RQ_LENGTH_OFFSET] : wr_rq_length; + wr_dmac_low_dlid <= (qpc_wr_piece_count == 2) ? qpc_req_data[`WR_QPC_DMAC_LOW_DLID_OFFSET] : wr_dmac_low_dlid; + wr_smac_low_slid <= (qpc_wr_piece_count == 2) ? qpc_req_data[`WR_QPC_SMAC_LOW_SLID_OFFSET] : wr_smac_low_slid; + wr_dmac_high <= (qpc_wr_piece_count == 3) ? qpc_req_data[`WR_QPC_DMAC_HIGH_OFFSET] : wr_dmac_high; + wr_smac_high <= (qpc_wr_piece_count == 3) ? qpc_req_data[`WR_QPC_SMAC_HIGH_OFFSET] : wr_smac_high; + wr_dip <= (qpc_wr_piece_count == 3) ? qpc_req_data[`WR_QPC_DIP_OFFSET] : wr_dip; + wr_sip <= (qpc_wr_piece_count == 3) ? qpc_req_data[`WR_QPC_SIP_OFFSET] : wr_sip; + end + else begin + wr_service_type <= wr_service_type; + wr_state <= wr_state; + wr_mtu_msgmax <= wr_mtu_msgmax; + wr_sq_entry_sz_log <= wr_sq_entry_sz_log; + wr_rq_entry_sz_log <= wr_rq_entry_sz_log; + wr_dst_qpn <= wr_dst_qpn; + wr_pkey_index <= wr_pkey_index; + wr_port_index <= wr_port_index; + wr_cqn_snd <= wr_cqn_snd; + wr_cqn_rcv <= wr_cqn_rcv; + wr_qp_pd <= wr_qp_pd; + wr_sq_lkey <= wr_sq_lkey; + wr_sq_length <= wr_sq_length; + wr_rq_lkey <= wr_rq_lkey; + wr_rq_length <= wr_rq_length; + wr_dmac_low_dlid <= wr_dmac_low_dlid; + wr_smac_low_slid <= wr_smac_low_slid; + wr_dmac_high <= wr_dmac_high; + wr_smac_high <= wr_smac_high; + wr_dip <= wr_dip; + wr_sip <= wr_sip; + end +end + +//-- Rd QPC Info -- +assign rd_service_type = cache_entry[2:0]; +assign rd_state = cache_entry[5:3]; +assign rd_mtu_msgmax = cache_entry[15:8]; +assign rd_sq_entry_sz_log = cache_entry[23:16]; +assign rd_rq_entry_sz_log = cache_entry[31:24]; +assign rd_dst_qpn = cache_entry[47:32]; +assign rd_pkey_index = cache_entry[55:48]; +assign rd_port_index = cache_entry[63:56]; +assign rd_cqn_snd = cache_entry[79:64]; +assign rd_cqn_rcv = cache_entry[95:80]; +assign rd_qp_pd = cache_entry[127:96]; +assign rd_sq_lkey = cache_entry[159:128]; +assign rd_sq_length = cache_entry[191:160]; +assign rd_rq_lkey = cache_entry[223:192]; +assign rd_rq_length = cache_entry[255:224]; +assign rd_dmac_low_dlid = cache_entry[31+256:16+256]; +assign rd_smac_low_slid = cache_entry[15+256:0+256]; +assign rd_dmac_high = cache_entry[95+256:64+256]; +assign rd_smac_high = cache_entry[63+256:32+256]; +assign rd_dip = cache_entry[159+256:128+256]; +assign rd_sip = cache_entry[127+256:96+256]; + +//-- count_max -- +//-- count_index -- +assign count_max = 'd1; //Specific for QPC/EQC/CQC/MPT, 2 for MTT +assign count_index = 'd0; //Specific for QPC/EQC/CQC/MPT, 0, 1 for MTT + +//-- req_tag -- +assign req_tag = 'd0; //Specific for CEU request, RPCCore will use tag start from 1. + +//-- qpc_rd_piece_count -- +always @(posedge clk or posedge rst) begin + if (rst) begin + qpc_rd_piece_count <= 'd0; + end + else if (cur_state == IDLE_s) begin + qpc_rd_piece_count <= 'd0; + end + else if (cur_state == CACHE_RSP_s && icm_get_rsp_valid && icm_get_rsp_ready) begin + qpc_rd_piece_count <= 'd1; + end + else if (cur_state == CEU_RSP_s && qpc_rsp_valid && qpc_rsp_ready) begin + qpc_rd_piece_count <= qpc_rd_piece_count + 'd1; + end + else begin + qpc_rd_piece_count <= qpc_rd_piece_count; + end +end + +//-- qpc_wr_piece_count -- +always @(posedge clk or posedge rst) begin + if(rst) begin + qpc_wr_piece_count <= 'd0; + end + else if(cur_state == IDLE_s) begin + qpc_wr_piece_count <= 'd0; + end + else if(cur_state == ADDR_RSP_s && next_state == QPC_COLLECT_s) begin + qpc_wr_piece_count <= 'd1; + end + else if(cur_state == QPC_COLLECT_s && qpc_req_valid && qpc_req_ready) begin + qpc_wr_piece_count <= qpc_wr_piece_count + 'd1; + end + else begin + qpc_wr_piece_count <= qpc_wr_piece_count; + end +end + +//-- qpc_req_head_diff -- +always @(posedge clk or posedge rst) begin + if(rst) begin + qpc_req_head_diff <= 'd0; + end + else if(cur_state == IDLE_s && qpc_req_valid) begin + qpc_req_head_diff <= qpc_req_head; + end + else begin + qpc_req_head_diff <= qpc_req_head_diff; + end +end + +//-- icm_addr -- +//-- phy_addr -- +always @(posedge clk or posedge rst) begin + if(rst) begin + icm_addr <= 'd0; + phy_addr <= 'd0; + end + else if(cur_state == IDLE_s) begin + icm_addr <= 'd0; + phy_addr <= 'd0; + end + else if(cur_state == ADDR_RSP_s && icm_mapping_rsp_valid) begin + icm_addr <= icm_mapping_rsp_icm_addr; + phy_addr <= icm_mapping_rsp_phy_addr; + end + else begin + icm_addr <= icm_addr; + phy_addr <= phy_addr; + end +end + +wire [31:0] ceu_cmd_index; +wire [`QP_NUM_LOG - 1 : 0] qpn; +assign ceu_cmd_index = qpc_req_head_diff[`CEU_CMD_INDEX_OFFSET]; +assign qpn = ceu_cmd_index[`QP_NUM_LOG - 1 : 0]; + +//-- icm_mapping_lookup_valid -- +//-- icm_mapping_lookup_head -- +assign icm_mapping_lookup_valid = (cur_state == ADDR_REQ_s) ? 'd1 : 'd0; +assign icm_mapping_lookup_head = (cur_state == ADDR_REQ_s) ? qpn : 'd0; //Notice CEU_CMD_INDEX_OFFSET is 32bit, may exceed actual index length, it does not matter + +//-- icm_mapping_rsp_ready -- +assign icm_mapping_rsp_ready = (cur_state == ADDR_RSP_s) ? 'd1 : 'd0; + +//-- icm_get_req_valid -- +//-- icm_get_req_head -- +assign icm_get_req_valid = (cur_state == CACHE_GET_s) ? 'd1 : 'd0; +assign icm_get_req_head = (cur_state == CACHE_GET_s) ? {count_max, count_index, req_tag, phy_addr, icm_addr} : 'd0; + +//-- icm_set_req_valid -- +//-- icm_set_req_head -- +//-- icm_set_req_data -- +assign icm_set_req_valid = (cur_state == CACHE_SET_s) ? 'd1 : 'd0; +assign icm_set_req_head = (cur_state == CACHE_SET_s) ? {req_tag, count_max, count_index, phy_addr, icm_addr} : 'd0; +assign icm_set_req_data = {wr_sip, wr_dip, wr_dmac_high, wr_dmac_low_dlid, wr_smac_high, wr_smac_low_slid, wr_rq_length, wr_rq_lkey, wr_sq_length, wr_sq_lkey, wr_qp_pd, wr_cqn_rcv, wr_cqn_snd, wr_port_index, + wr_pkey_index, wr_dst_qpn, wr_rq_entry_sz_log, wr_sq_entry_sz_log, wr_mtu_msgmax, 2'd0, wr_state, wr_service_type}; + +//-- cache_entry -- +always @(posedge clk or posedge rst) begin + if (rst) begin + cache_entry <= 'd0; + end + else if (cur_state == IDLE_s) begin + cache_entry <= 'd0; + end + else if (cur_state == CACHE_RSP_s && icm_get_rsp_valid) begin + cache_entry <= icm_get_rsp_data; + end + else begin + cache_entry <= cache_entry; + end +end + +//-- qpc_req_ready -- +//Break timing loop +// assign qpc_req_ready = (cur_state == ADDR_RSP_s && next_state == CACHE_GET_s) ? 'd1 : +// (cur_state == QPC_COLLECT_s) ? 'd1 : 'd0; +assign qpc_req_ready = (cur_state == ADDR_RSP_s && ((icm_mapping_rsp_valid) && (qpc_req_head_diff[`CEU_CMD_TYPE_OFFSET] == `RD_QP_CXT))) ? 'd1 : + (cur_state == QPC_COLLECT_s) ? 'd1 : 'd0; + +//-- icm_get_rsp_ready -- +assign icm_get_rsp_ready = (cur_state == CACHE_RSP_s) ? 'd1 : 'd0; + +//-- icm_mapping_rsp_ready -- +assign icm_mapping_rsp_ready = (cur_state == ADDR_RSP_s) ? 'd1 : 'd0; + +//-- qpc_rsp_valid -- +//-- qpc_rsp_head -- +//-- qpc_rsp_last -- +assign qpc_rsp_valid = (cur_state == CEU_RSP_s) ? 'd1 : 'd0; +assign qpc_rsp_head = (cur_state == CEU_RSP_s) ? qpc_req_head_diff : 'd0; +assign qpc_rsp_last = (cur_state == CEU_RSP_s && qpc_rd_piece_count == 6) ? 'd1 : 'd0; + +//-- qpc_rsp_data -- +assign qpc_rsp_data = (cur_state == CEU_RSP_s && qpc_rd_piece_count == 1) ? {rd_port_index, rd_pkey_index, rd_dst_qpn, qpc_req_head_diff[`CEU_CMD_INDEX_OFFSET], 32'd0, rd_mtu_msgmax, + rd_rq_entry_sz_log, rd_sq_entry_sz_log, 8'd0, {2'd0, rd_state}, 3'd0, {5'd0, rd_service_type}, 80'd0} : + (cur_state == CEU_RSP_s && qpc_rd_piece_count == 2) ? {rd_dmac_low_dlid, rd_smac_low_slid, 192'd0, rd_port_index, 16'd0, rd_pkey_index} : + (cur_state == CEU_RSP_s && qpc_rd_piece_count == 3) ? {rd_qp_pd, 96'd0, rd_dip, rd_sip, rd_dmac_high, rd_smac_high} : + (cur_state == CEU_RSP_s && qpc_rd_piece_count == 4) ? {32'd0, rd_sq_length, rd_sq_lkey, rd_cqn_snd, 128'd0} : + (cur_state == CEU_RSP_s && qpc_rd_piece_count == 5) ? {32'd0, 32'd0, rd_rq_length, rd_rq_lkey, rd_cqn_rcv, 96'd0} : + (cur_state == CEU_RSP_s && qpc_rd_piece_count == 6) ? {256'd0} : 'd0; + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ + +/*------------------------------------------- Local Macros Undef : Begin --------------------------------------------*/ +`undef CEU_CMD_OPCODE_OFFSET +`undef QPC_PIECE_NUM + +`undef WR_QPC_SERVICE_TYPE_OFFSET +`undef WR_QPC_STATE_OFFSET +`undef WR_QPC_MTU_MSGMAX_OFFSET +`undef WR_QPC_SQ_ENTRY_SZ_LOG_OFFSET +`undef WR_QPC_RQ_ENTRY_SZ_LOG_OFFSET +`undef WR_QPC_DST_QPN_OFFSET +`undef WR_QPC_PKEY_INDEX_OFFSET +`undef WR_QPC_PORT_INDEX_OFFSET +`undef WR_QPC_CQN_SND_OFFSET +`undef WR_QPC_CQN_RCV_OFFSET +`undef WR_QPC_QP_PD_OFFSET +`undef WR_QPC_SQ_LKEY_OFFSET +`undef WR_QPC_SQ_LENGTH_OFFSET +`undef WR_QPC_RQ_LKEY_OFFSET +`undef WR_QPC_RQ_LENGTH_OFFSET +`undef WR_QPC_DMAC_LOW_DLID_OFFSET +`undef WR_QPC_SMAC_LOW_SLID_OFFSET +`undef WR_QPC_DMAC_HIGH_OFFSET +`undef WR_QPC_SMAC_HIGH_OFFSET +`undef WR_QPC_DIP_OFFSET +`undef WR_QPC_SIP_OFFSET +/*------------------------------------------- Local Macros Undef : End ----------------------------------------------*/ + +`ifdef ILA_ON + ila_sw_acc_cm_thread_2 ila_sw_acc_cm_thread_2_inst( + .clk(clk), + + .probe0(qpc_req_valid), + .probe1(qpc_req_head), + .probe2(qpc_req_data), + .probe3(qpc_req_last), + .probe4(qpc_req_ready), + + .probe5(icm_set_req_valid), + .probe6(icm_set_req_head), + .probe7(icm_set_req_data), + .probe8(icm_set_req_ready), + + .probe9(icm_mapping_lookup_valid), + .probe10(icm_mapping_lookup_head), + .probe11(icm_mapping_lookup_ready), + + .probe12(icm_mapping_rsp_valid), + .probe13(icm_mapping_rsp_icm_addr), + .probe14(icm_mapping_rsp_phy_addr), + .probe15(icm_mapping_rsp_ready) + ); +`endif + +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/ICMMgt/CxtMgt/SWAccCMCtl/SWAccCMCtl_Thread_3.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/ICMMgt/CxtMgt/SWAccCMCtl/SWAccCMCtl_Thread_3.v new file mode 100644 index 0000000000000000000000000000000000000000..fbc1c0fb5fa8ef876e09b92b866da20f7b88374b --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/ICMMgt/CxtMgt/SWAccCMCtl/SWAccCMCtl_Thread_3.v @@ -0,0 +1,277 @@ +/*------------------------------------------- Module Description : Begin ---------------------------------------------- +Name: SWAccCMCtl_Thread_3 +Author: YangFan +Function: Handle CQC Wr Command from CEU. +--------------------------------------------- Module Decription : End -----------------------------------------------*/ + +/*------------------------------------------- Timescale Definition : Begin ------------------------------------------*/ +`timescale 1ns / 1ps +/*------------------------------------------- Timescale Definition : End --------------------------------------------*/ + +/*------------------------------------------- Included Files : Begin ------------------------------------------------*/ +`include "protocol_engine_def.vh" +/*------------------------------------------- Included Files : End --------------------------------------------------*/ + + + +/*------------------------------------------- Input/Output Definition : Begin ---------------------------------------*/ +module SWAccCMCtl_Thread_3 ( + input wire clk, + input wire rst, + +//Interface with SWAccCMCtl_Thread_0 + input wire cqc_req_valid, + input wire [`CEU_CXT_HEAD_WIDTH - 1 : 0] cqc_req_head, + input wire cqc_req_last, + input wire [`CEU_CXT_DATA_WIDTH - 1 : 0] cqc_req_data, + output wire cqc_req_ready, + +//Interface with CQCCache(ICMCache) +//Cache Set Req Interface + output wire cache_set_req_valid, + output wire [`REQ_TAG_NUM_LOG + `COUNT_MAX_LOG * 2 + `ICM_SPACE_ADDR_WIDTH + `PHY_SPACE_ADDR_WIDTH - 1 : 0] cache_set_req_head, + output wire [`CACHE_ENTRY_WIDTH_CQC - 1 : 0] cache_set_req_data, + input wire cache_set_req_ready, + +//ICM Address Translation Interface + output wire icm_mapping_lookup_valid, + output wire [log2b(`ICM_ENTRY_NUM_CQC - 1) - 1 : 0] icm_mapping_lookup_head, + input wire icm_mapping_lookup_ready, + + input wire icm_mapping_rsp_valid, + input wire [`ICM_SPACE_ADDR_WIDTH - 1 : 0] icm_mapping_rsp_icm_addr, + input wire [`PHY_SPACE_ADDR_WIDTH - 1 : 0] icm_mapping_rsp_phy_addr, + output wire icm_mapping_rsp_ready +); +/*------------------------------------------- Input/Output Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Macros Definition : Begin ---------------------------------------*/ +`define CEU_CMD_OPCODE_OFFSET 123:120 +`define CEU_CMD_INDEX_OFFSET 95:64 +`define CQC_PIECE_NUM 2 //64B / 32B(256bit data width) + +`define WR_CQC_LKEY_OFFSET 32 * 2 - 1 : 32 * 1 +`define WR_CQC_PD_OFFSET 32 * 3 - 1 : 32 * 2 +`define WR_CQC_EQN_OFFSET 32 * 4 - 1 : 32 * 3 +`define WR_CQC_LOG_SIZE_OFFSET 32 * 5 - 1 : 32 * 4 + 24 +/*------------------------------------------- Local Macros Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Variables Definition : Begin ------------------------------------*/ +reg [3:0] cqc_wr_piece_count; + +reg [`CEU_CXT_HEAD_WIDTH - 1 : 0] cqc_req_head_diff; + +reg [`ICM_SPACE_ADDR_WIDTH - 1 : 0] icm_addr; +reg [`PHY_SPACE_ADDR_WIDTH - 1 : 0] phy_addr; + +wire [`COUNT_MAX_LOG - 1 : 0] count_max; +wire [`COUNT_MAX_LOG - 1 : 0] count_index; + +wire [`REQ_TAG_NUM_LOG - 1 : 0] req_tag; + +//QPC Info +reg [7:0] wr_log_size; +reg [31:0] wr_comp_eqn; +reg [31:0] wr_cq_pd; +reg [31:0] wr_cq_lkey; +/*------------------------------------------- Local Variables Definition : End --------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : Begin ---------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : End -----------------------------------------*/ + +/*------------------------------------------- State Machine Definition : Begin --------------------------------------*/ +reg [2:0] cur_state; +reg [2:0] next_state; + +parameter [2:0] IDLE_s = 3'd1, + ADDR_REQ_s = 3'd2, + ADDR_RSP_s = 3'd3, + CQC_COLLECT_s = 3'd4, + CQC_INVALID_s = 3'd5, + CACHE_SET_s = 3'd6; + +always @(posedge clk or posedge rst) begin + if(rst) begin + cur_state <= IDLE_s; + end + else begin + cur_state <= next_state; + end +end + +always @(*) begin + case(cur_state) + IDLE_s: if(cqc_req_valid) begin + next_state = ADDR_REQ_s; + end + else begin + next_state = IDLE_s; + end + ADDR_REQ_s: if(icm_mapping_lookup_valid && icm_mapping_lookup_ready) begin + next_state = ADDR_RSP_s; + end + else begin + next_state = ADDR_REQ_s; + end + ADDR_RSP_s: if(icm_mapping_rsp_valid) begin + if(cqc_req_valid && cqc_req_head_diff[`CEU_CMD_OPCODE_OFFSET] == `WR_CQ_ALL) begin + next_state = CQC_COLLECT_s; + end + else if(cqc_req_valid && cqc_req_head_diff[`CEU_CMD_OPCODE_OFFSET] == `WR_CQ_MODIFY) begin + next_state = CQC_COLLECT_s; + end + else if(cqc_req_valid && cqc_req_head_diff[`CEU_CMD_OPCODE_OFFSET] == `WR_CQ_INVALID) begin + next_state = CQC_INVALID_s; + end + else begin + next_state = IDLE_s; + end + end + else begin + next_state = ADDR_RSP_s; + end + CQC_COLLECT_s: if(cqc_wr_piece_count == `CQC_PIECE_NUM && cqc_req_valid && cqc_req_ready) begin + next_state = CACHE_SET_s; + end + else begin + next_state = CQC_COLLECT_s; + end + CQC_INVALID_s: next_state = IDLE_s; + CACHE_SET_s: if(cache_set_req_valid && cache_set_req_ready) begin + next_state = IDLE_s; + end + else begin + next_state = CACHE_SET_s; + end + default: next_state = IDLE_s; + endcase +end +/*------------------------------------------- State Machine Definition : End ----------------------------------------*/ + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ +//-- Wr QPC Info -- +always @(posedge clk or posedge rst) begin + if(rst) begin + wr_log_size <= 'd0; + wr_comp_eqn <= 'd0; + wr_cq_pd <= 'd0; + wr_cq_lkey <= 'd0; + end + else if(cur_state == IDLE_s) begin + wr_log_size <= 'd0; + wr_comp_eqn <= 'd0; + wr_cq_pd <= 'd0; + wr_cq_lkey <= 'd0; + end + else if(cur_state == CQC_COLLECT_s && cqc_req_valid) begin + wr_log_size <= (cqc_wr_piece_count == 1) ? cqc_req_data[`WR_CQC_LOG_SIZE_OFFSET] : wr_log_size; + wr_comp_eqn <= (cqc_wr_piece_count == 1) ? cqc_req_data[`WR_CQC_EQN_OFFSET] : wr_comp_eqn; + wr_cq_pd <= (cqc_wr_piece_count == 1) ? cqc_req_data[`WR_CQC_PD_OFFSET] : wr_cq_pd; + wr_cq_lkey <= (cqc_wr_piece_count == 1) ? cqc_req_data[`WR_CQC_LKEY_OFFSET] : wr_cq_lkey; + end + else begin + wr_log_size <= wr_log_size; + wr_comp_eqn <= wr_comp_eqn; + wr_cq_pd <= wr_cq_pd; + wr_cq_lkey <= wr_cq_lkey; + end +end + +//-- count_max -- +//-- count_index -- +assign count_max = 'd1; //Specific for QPC/EQC/CQC/MPT, 2 for MTT +assign count_index = 'd0; //Specific for QPC/EQC/CQC/MPT, 0, 1 for MTT + +//-- req_tag -- +assign req_tag = 'd0; //Specific for CEU request, RPCCore will use tag start from 1. + +//-- cqc_wr_piece_count -- +always @(posedge clk or posedge rst) begin + if(rst) begin + cqc_wr_piece_count <= 'd0; + end + else if(cur_state == IDLE_s) begin + cqc_wr_piece_count <= 'd0; + end + else if(cur_state == ADDR_RSP_s && next_state == CQC_COLLECT_s) begin + cqc_wr_piece_count <= 'd1; + end + else if(cur_state == CQC_COLLECT_s && cqc_req_valid && cqc_req_ready) begin + cqc_wr_piece_count <= cqc_wr_piece_count + 'd1; + end + else begin + cqc_wr_piece_count <= cqc_wr_piece_count; + end +end + +//-- cqc_req_head_diff -- +always @(posedge clk or posedge rst) begin + if(rst) begin + cqc_req_head_diff <= 'd0; + end + else if(cur_state == IDLE_s && cqc_req_valid) begin + cqc_req_head_diff <= cqc_req_head; + end + else begin + cqc_req_head_diff <= cqc_req_head_diff; + end +end + +//-- icm_addr -- +//-- phy_addr -- +always @(posedge clk or posedge rst) begin + if(rst) begin + icm_addr <= 'd0; + phy_addr <= 'd0; + end + else if(cur_state == IDLE_s) begin + icm_addr <= 'd0; + phy_addr <= 'd0; + end + else if(cur_state == ADDR_RSP_s && icm_mapping_rsp_valid) begin + icm_addr <= icm_mapping_rsp_icm_addr; + phy_addr <= icm_mapping_rsp_phy_addr; + end + else begin + icm_addr <= icm_addr; + phy_addr <= phy_addr; + end +end + +wire [31:0] ceu_cmd_index; +wire [`CQ_NUM_LOG - 1 : 0] cqn; +assign ceu_cmd_index = cqc_req_head_diff[`CEU_CMD_INDEX_OFFSET]; +assign cqn = ceu_cmd_index[`CQ_NUM_LOG - 1 : 0]; + +//-- icm_mapping_lookup_valid -- +//-- icm_mapping_lookup_head -- +assign icm_mapping_lookup_valid = (cur_state == ADDR_REQ_s) ? 'd1 : 'd0; +assign icm_mapping_lookup_head = (cur_state == ADDR_REQ_s) ? cqn : 'd0; //Notice CEU_CMD_INDEX_OFFSET is 32bit, may exceed actual index length, it does not matter + +//-- icm_mapping_rsp_ready -- +assign icm_mapping_rsp_ready = (cur_state == ADDR_RSP_s) ? 'd1 : 'd0; + + +//-- cache_set_req_valid -- +//-- cache_set_req_head -- +//-- cache_set_req_data -- +assign cache_set_req_valid = (cur_state == CACHE_SET_s) ? 'd1 : 'd0; +assign cache_set_req_head = (cur_state == CACHE_SET_s) ? {req_tag, count_max, count_index, phy_addr, icm_addr} : 'd0; +assign cache_set_req_data = {wr_cq_lkey, wr_cq_pd, wr_comp_eqn, 24'd0, wr_log_size}; + +//-- cqc_req_ready -- +assign cqc_req_ready = (cur_state == CQC_COLLECT_s || cur_state == CQC_INVALID_s) ? 'd1 : 'd0; + + +//-- icm_mapping_rsp_ready -- +assign icm_mapping_rsp_ready = (cur_state == ADDR_RSP_s) ? 'd1 : 'd0; + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ + +/*------------------------------------------- Local Macros Undef : Begin --------------------------------------------*/ +`undef CEU_CMD_OPCODE_OFFSET +`undef CQC_PIECE_NUM +/*------------------------------------------- Local Macros Undef : End ----------------------------------------------*/ + +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/ICMMgt/CxtMgt/SWAccCMCtl/SWAccCMCtl_Thread_4.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/ICMMgt/CxtMgt/SWAccCMCtl/SWAccCMCtl_Thread_4.v new file mode 100644 index 0000000000000000000000000000000000000000..efa6ee675aba95ca0fd16fe8eea62b66896603a7 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/ICMMgt/CxtMgt/SWAccCMCtl/SWAccCMCtl_Thread_4.v @@ -0,0 +1,259 @@ +/*------------------------------------------- Module Description : Begin ---------------------------------------------- +Name: SWAccCMCtl_Thread_4 +Author: YangFan +Function: Handle EQC Wr Command from CEU. +--------------------------------------------- Module Decription : End -----------------------------------------------*/ + +/*------------------------------------------- Timescale Definition : Begin ------------------------------------------*/ +`timescale 1ns / 1ps +/*------------------------------------------- Timescale Definition : End --------------------------------------------*/ + +/*------------------------------------------- Included Files : Begin ------------------------------------------------*/ +`include "protocol_engine_def.vh" +/*------------------------------------------- Included Files : End --------------------------------------------------*/ + + + +/*------------------------------------------- Input/Output Definition : Begin ---------------------------------------*/ +module SWAccCMCtl_Thread_4 ( + input wire clk, + input wire rst, + +//Interface with SWAccCMCtl_Thread_0 + input wire eqc_req_valid, + input wire [`CEU_CXT_HEAD_WIDTH - 1 : 0] eqc_req_head, + input wire eqc_req_last, + input wire [`CEU_CXT_DATA_WIDTH - 1 : 0] eqc_req_data, + output wire eqc_req_ready, + +//Interface with EQCCache(ICMCache) +//Cache Set Req Interface + output wire cache_set_req_valid, + output wire [`REQ_TAG_NUM_LOG + `COUNT_MAX_LOG * 2 + `ICM_SPACE_ADDR_WIDTH + `PHY_SPACE_ADDR_WIDTH - 1 : 0] cache_set_req_head, + output wire [`CACHE_ENTRY_WIDTH_EQC - 1 : 0] cache_set_req_data, + input wire cache_set_req_ready, + +//ICM Address Translation Interface + output wire icm_mapping_lookup_valid, + output wire [log2b(`ICM_ENTRY_NUM_EQC - 1) - 1 : 0] icm_mapping_lookup_head, + input wire icm_mapping_lookup_ready, + + input wire icm_mapping_rsp_valid, + input wire [`ICM_SPACE_ADDR_WIDTH - 1 : 0] icm_mapping_rsp_icm_addr, + input wire [`PHY_SPACE_ADDR_WIDTH - 1 : 0] icm_mapping_rsp_phy_addr, + output wire icm_mapping_rsp_ready +); +/*------------------------------------------- Input/Output Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Macros Definition : Begin ---------------------------------------*/ +`define CEU_CMD_OPCODE_OFFSET 123:120 +`define CEU_CMD_INDEX_OFFSET 95:64 +`define EQC_PIECE_NUM 2 //64B / 32B(256bit data width) +/*------------------------------------------- Local Macros Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Variables Definition : Begin ------------------------------------*/ +reg [3:0] eqc_wr_piece_count; + +reg [`CEU_CXT_HEAD_WIDTH - 1 : 0] eqc_req_head_diff; + +reg [`ICM_SPACE_ADDR_WIDTH - 1 : 0] icm_addr; +reg [`PHY_SPACE_ADDR_WIDTH - 1 : 0] phy_addr; + +wire [`COUNT_MAX_LOG - 1 : 0] count_max; +wire [`COUNT_MAX_LOG - 1 : 0] count_index; + +wire [`REQ_TAG_NUM_LOG - 1 : 0] req_tag; + +//EPC Info +reg [7:0] wr_log_size; +reg [31:0] wr_msix_interrupt; +reg [31:0] wr_eq_pd; +reg [31:0] wr_eq_lkey; +/*------------------------------------------- Local Variables Definition : End --------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : Begin ---------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : End -----------------------------------------*/ + +/*------------------------------------------- State Machine Definition : Begin --------------------------------------*/ +reg [2:0] cur_state; +reg [2:0] next_state; + +parameter [2:0] IDLE_s = 3'd1, + ADDR_REQ_s = 3'd2, + ADDR_RSP_s = 3'd3, + EQC_COLLECT_s = 3'd4, + CACHE_SET_s = 3'd5; + +always @(posedge clk or posedge rst) begin + if(rst) begin + cur_state <= IDLE_s; + end + else begin + cur_state <= next_state; + end +end + +always @(*) begin + case(cur_state) + IDLE_s: if(eqc_req_valid) begin + next_state = ADDR_REQ_s; + end + else begin + next_state = IDLE_s; + end + ADDR_REQ_s: if(icm_mapping_lookup_valid && icm_mapping_lookup_ready) begin + next_state = ADDR_RSP_s; + end + else begin + next_state = ADDR_REQ_s; + end + ADDR_RSP_s: if(icm_mapping_rsp_valid) begin + if(eqc_req_valid && eqc_req_head_diff[`CEU_CMD_OPCODE_OFFSET] == `WR_CQ_ALL) begin + next_state = EQC_COLLECT_s; + end + else begin + next_state = IDLE_s; + end + end + else begin + next_state = ADDR_RSP_s; + end + EQC_COLLECT_s: if(eqc_wr_piece_count == `EQC_PIECE_NUM && eqc_req_valid && eqc_req_ready) begin + next_state = CACHE_SET_s; + end + else begin + next_state = EQC_COLLECT_s; + end + CACHE_SET_s: if(cache_set_req_valid && cache_set_req_ready) begin + next_state = IDLE_s; + end + else begin + next_state = CACHE_SET_s; + end + default: next_state = IDLE_s; + endcase +end +/*------------------------------------------- State Machine Definition : End ----------------------------------------*/ + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ +//-- Wr QPC Info -- +always @(posedge clk or posedge rst) begin + if(rst) begin + wr_log_size <= 'd0; + wr_msix_interrupt <= 'd0; + wr_eq_pd <= 'd0; + wr_eq_lkey <= 'd0; + end + else if(cur_state == IDLE_s) begin + wr_log_size <= 'd0; + wr_msix_interrupt <= 'd0; + wr_eq_pd <= 'd0; + wr_eq_lkey <= 'd0; + end + else if(cur_state == EQC_COLLECT_s && eqc_req_valid) begin + wr_log_size <= (eqc_wr_piece_count == 1) ? eqc_req_data[127:120] : wr_log_size; + wr_msix_interrupt <= (eqc_wr_piece_count == 1) ? eqc_req_data[167:160] : wr_msix_interrupt; + wr_eq_pd <= (eqc_wr_piece_count == 1) ? eqc_req_data[191:160] : wr_eq_pd; + wr_eq_lkey <= (eqc_wr_piece_count == 1) ? eqc_req_data[223:192] : wr_eq_lkey; + end + else begin + wr_log_size <= wr_log_size; + wr_msix_interrupt <= wr_msix_interrupt; + wr_eq_pd <= wr_eq_pd; + wr_eq_lkey <= wr_eq_lkey; + end +end + +//-- count_max -- +//-- count_index -- +assign count_max = 'd1; //Specific for QPC/EQC/CQC/MPT, 2 for MTT +assign count_index = 'd0; //Specific for QPC/EQC/CQC/MPT, 0, 1 for MTT + +//-- req_tag -- +assign req_tag = 'd0; //Specific for CEU request, RPCCore will use tag start from 1. + +//-- eqc_wr_piece_count -- +always @(posedge clk or posedge rst) begin + if(rst) begin + eqc_wr_piece_count <= 'd0; + end + else if(cur_state == IDLE_s) begin + eqc_wr_piece_count <= 'd0; + end + else if(cur_state == ADDR_RSP_s && next_state == EQC_COLLECT_s) begin + eqc_wr_piece_count <= 'd1; + end + else if(cur_state == EQC_COLLECT_s && eqc_req_valid && eqc_req_ready) begin + eqc_wr_piece_count <= eqc_wr_piece_count + 'd1; + end + else begin + eqc_wr_piece_count <= eqc_wr_piece_count; + end +end + +//-- eqc_req_head_diff -- +always @(posedge clk or posedge rst) begin + if(rst) begin + eqc_req_head_diff <= 'd0; + end + else if(cur_state == IDLE_s && eqc_req_valid) begin + eqc_req_head_diff <= eqc_req_head; + end + else begin + eqc_req_head_diff <= eqc_req_head_diff; + end +end + +//-- icm_addr -- +//-- phy_addr -- +always @(posedge clk or posedge rst) begin + if(rst) begin + icm_addr <= 'd0; + phy_addr <= 'd0; + end + else if(cur_state == IDLE_s) begin + icm_addr <= 'd0; + phy_addr <= 'd0; + end + else if(cur_state == ADDR_RSP_s && icm_mapping_rsp_valid) begin + icm_addr <= icm_mapping_rsp_icm_addr; + phy_addr <= icm_mapping_rsp_phy_addr; + end + else begin + icm_addr <= icm_addr; + phy_addr <= phy_addr; + end +end + +//-- icm_mapping_lookup_valid -- +//-- icm_mapping_lookup_head -- +assign icm_mapping_lookup_valid = (cur_state == ADDR_REQ_s) ? 'd1 : 'd0; +assign icm_mapping_lookup_head = (cur_state == ADDR_REQ_s) ? eqc_req_head_diff[`CEU_CMD_INDEX_OFFSET] : 'd0; //Notice CEU_CMD_INDEX_OFFSET is 32bit, may exceed actual index length, it does not matter + +//-- icm_mapping_rsp_ready -- +assign icm_mapping_rsp_ready = (cur_state == ADDR_RSP_s) ? 'd1 : 'd0; + + +//-- cache_set_req_valid -- +//-- cache_set_req_head -- +//-- cache_set_req_data -- +assign cache_set_req_valid = (cur_state == CACHE_SET_s && eqc_wr_piece_count == `EQC_PIECE_NUM && eqc_req_valid) ? 'd1 : 'd0; +assign cache_set_req_head = (cur_state == CACHE_SET_s && eqc_wr_piece_count == `EQC_PIECE_NUM && eqc_req_valid) ? {phy_addr, icm_addr} : 'd0; +assign cache_set_req_data = {wr_eq_lkey, wr_eq_pd, wr_msix_interrupt, 24'd0, wr_log_size}; + +//-- eqc_req_ready -- +assign eqc_req_ready = (cur_state == EQC_COLLECT_s) ? 'd1 : 'd0; + + +//-- icm_mapping_rsp_ready -- +assign icm_mapping_rsp_ready = (cur_state == ADDR_RSP_s) ? 'd1 : 'd0; + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ + +/*------------------------------------------- Local Macros Undef : Begin --------------------------------------------*/ +`undef CEU_CMD_OPCODE_OFFSET +`undef EQC_PIECE_NUM +/*------------------------------------------- Local Macros Undef : End ----------------------------------------------*/ + +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/ICMMgt/CxtMgt/SWAccCMCtl/SWAccCMCtl_Thread_5.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/ICMMgt/CxtMgt/SWAccCMCtl/SWAccCMCtl_Thread_5.v new file mode 100644 index 0000000000000000000000000000000000000000..435cc6417c25f5f53c09463a8824d455bdb11b37 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/ICMMgt/CxtMgt/SWAccCMCtl/SWAccCMCtl_Thread_5.v @@ -0,0 +1,379 @@ +/*------------------------------------------- Module Description : Begin ---------------------------------------------- +Name: SWAccCMCtl_Thread_5 +Author: YangFan +Function: Handle ICMMapping Command from CEU. +--------------------------------------------- Module Decription : End -----------------------------------------------*/ + +/*------------------------------------------- Timescale Definition : Begin ------------------------------------------*/ +`timescale 1ns / 1ps +/*------------------------------------------- Timescale Definition : End --------------------------------------------*/ + +/*------------------------------------------- Included Files : Begin ------------------------------------------------*/ +`include "protocol_engine_def.vh" +/*------------------------------------------- Included Files : End --------------------------------------------------*/ + + +/*------------------------------------------- Input/Output Definition : Begin ---------------------------------------*/ +module SWAccCMCtl_Thread_5 +#( + parameter ICM_PAGE_NUM = `ICM_PAGE_NUM_EQC, + parameter ICM_PAGE_NUM_LOG = log2b(ICM_PAGE_NUM - 1) +) +( + input wire clk, + input wire rst, + +//Interface with SWAccCMCtl_Thread_0 + input wire map_req_valid, + input wire [`CEU_CXT_HEAD_WIDTH - 1 : 0] map_req_head, + input wire map_req_last, + input wire [`CEU_CXT_DATA_WIDTH - 1 : 0] map_req_data, + output wire map_req_ready, + +//Set QPC ICM Mapping Table Entry + output reg qpc_mapping_set_valid, + output reg [`PAGE_FRAME_WIDTH - 1 : 0] qpc_mapping_set_head, + output reg [`PAGE_FRAME_WIDTH - 1 : 0] qpc_mapping_set_data, + +//Set CQC ICM Mapping Table Entry + output reg cqc_mapping_set_valid, + output reg [`PAGE_FRAME_WIDTH - 1 : 0] cqc_mapping_set_head, + output reg [`PAGE_FRAME_WIDTH - 1 : 0] cqc_mapping_set_data, + +//Set EQC ICM Mapping Table Entry + output reg eqc_mapping_set_valid, + output reg [`PAGE_FRAME_WIDTH - 1 : 0] eqc_mapping_set_head, + output reg [`PAGE_FRAME_WIDTH - 1 : 0] eqc_mapping_set_data, + + output reg [`ICM_SPACE_ADDR_WIDTH - 1 : 0] qpc_base, + output reg [`ICM_SPACE_ADDR_WIDTH - 1 : 0] cqc_base, + output reg [`ICM_SPACE_ADDR_WIDTH - 1 : 0] eqc_base + +); +/*------------------------------------------- Input/Output Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Macros Definition : Begin ---------------------------------------*/ +`define CEU_CMD_TYPE_OFFSET 127:124 +`define CEU_CMD_OPCODE_OFFSET 123:120 +`define CEU_CMD_CHUNK_NUM_OFFSET 95:64 + +`define EQC_BASE_OFFSET 63:8 +`define EQC_NUM_LOG_OFFSET 7:0 +`define CQC_BASE_OFFSET 63+64:8+64 +`define CQC_NUM_LOG_OFFSET 7+64:0+64 +`define QPC_BASE_OFFSET 63+128:8+128 +`define QPC_NUM_LOG_OFFSET 7+128:0+128 + +`define HIGH_ENTRY_ICM_ADDR_OFFSET 255:192 +`define LOW_ENTRY_ICM_ADDR_OFFSET 127:64 +`define HIGH_ENTRY_PHY_ADDR_OFFSET 191:140 +`define LOW_ENTRY_PHY_ADDR_OFFSET 63:12 +/*------------------------------------------- Local Macros Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Variables Definition : Begin ------------------------------------*/ + +reg [31:0] qpc_num; +reg [63:0] qpc_end; + +reg [31:0] cqc_num; +reg [63:0] cqc_end; + +reg [31:0] eqc_num; +reg [63:0] eqc_end; + +reg [31:0] chunk_num_left; + + +wire [63:0] icm_addr; +wire [51:0] phy_addr; +wire [63:0] qpc_addr; +wire [63:0] cqc_addr; +wire [63:0] eqc_addr; + +wire is_qpc_mapping; +wire is_cqc_mapping; +wire is_eqc_mapping; + + +/*------------------------------------------- Local Variables Definition : End --------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : Begin ---------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : End -----------------------------------------*/ + +/*------------------------------------------- State Machine Definition : Begin --------------------------------------*/ +reg [2:0] cur_state; +reg [2:0] next_state; + +parameter [2:0] IDLE_s = 3'd1, + MAP_BASE_s = 3'd2, + MAP_HIGH_s = 3'd3, + MAP_LOW_s = 3'd4, + MAP_DIS_s = 3'd5, + ICM_DIS_s = 3'd6; + +always @(posedge clk or posedge rst) begin + if (rst) begin + cur_state <= IDLE_s; + end + else begin + cur_state <= next_state; + end +end + +always @(*) begin + case(cur_state) + IDLE_s: if(map_req_valid) begin + if(map_req_head[`CEU_CMD_TYPE_OFFSET] == `WR_ICMMAP_CXT && map_req_head[`CEU_CMD_OPCODE_OFFSET] == `WR_ICMMAP_EN) begin + next_state = MAP_BASE_s; + end + else if(map_req_head[`CEU_CMD_TYPE_OFFSET] == `WR_ICMMAP_CXT && map_req_head[`CEU_CMD_OPCODE_OFFSET] == `WR_ICMMAP_DIS) begin + next_state = MAP_DIS_s; + end + else if(map_req_head[`CEU_CMD_TYPE_OFFSET] == `MAP_ICM_CXT && map_req_head[`CEU_CMD_OPCODE_OFFSET] == `MAP_ICM_EN) begin + next_state = MAP_LOW_s; + end + else if(map_req_head[`CEU_CMD_TYPE_OFFSET] == `MAP_ICM_CXT && map_req_head[`CEU_CMD_OPCODE_OFFSET] == `MAP_ICM_DIS) begin + next_state = ICM_DIS_s; + end + else begin + next_state = IDLE_s; + end + end + else begin + next_state = IDLE_s; + end + MAP_BASE_s: next_state = IDLE_s; + MAP_HIGH_s: if(map_req_valid && chunk_num_left == 1) begin + next_state = IDLE_s; + end + else if(map_req_valid && chunk_num_left > 1) begin + next_state = MAP_LOW_s; + end + else begin + next_state = MAP_HIGH_s; + end + MAP_LOW_s: if(map_req_valid && chunk_num_left == 1) begin + next_state = IDLE_s; + end + else if(map_req_valid && chunk_num_left > 1) begin + next_state = MAP_HIGH_s; + end + else begin + next_state = MAP_LOW_s; + end + default: next_state = IDLE_s; + endcase +end +/*------------------------------------------- State Machine Definition : End ----------------------------------------*/ + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ +//-- icm_addr -- +assign icm_addr = (cur_state == MAP_HIGH_s && map_req_valid) ? map_req_data[`HIGH_ENTRY_ICM_ADDR_OFFSET] : + (cur_state == MAP_LOW_s && map_req_valid) ? map_req_data[`LOW_ENTRY_ICM_ADDR_OFFSET] : 'd0; + +//-- phy_addr -- +assign phy_addr = (cur_state == MAP_HIGH_s && map_req_valid) ? map_req_data[`HIGH_ENTRY_PHY_ADDR_OFFSET] : + (cur_state == MAP_LOW_s && map_req_valid) ? map_req_data[`LOW_ENTRY_PHY_ADDR_OFFSET] : 'd0; + +//-- is_qpc_mapping -- +//-- is_cqc_mapping -- +//-- is_eqc_mapping -- +assign is_qpc_mapping = (cur_state == MAP_HIGH_s || cur_state == MAP_LOW_s) && map_req_valid && (icm_addr >= qpc_base && icm_addr < qpc_end) ? 'd1 : 'd0; +assign is_cqc_mapping = (cur_state == MAP_HIGH_s || cur_state == MAP_LOW_s) && map_req_valid && (icm_addr >= cqc_base && icm_addr < cqc_end) ? 'd1 : 'd0; +assign is_eqc_mapping = (cur_state == MAP_HIGH_s || cur_state == MAP_LOW_s) && map_req_valid && (icm_addr >= eqc_base && icm_addr < eqc_end) ? 'd1 : 'd0; + +//-- qpc_addr -- +//-- cqc_addr -- +//-- eqc_addr -- +assign qpc_addr = is_qpc_mapping ? icm_addr[63:12] : 'd0; //Only need ICM Page Frame +assign cqc_addr = is_cqc_mapping ? icm_addr[63:12] : 'd0; +assign eqc_addr = is_eqc_mapping ? icm_addr[63:12] : 'd0; + +//-- chunk_num_left -- +always @(posedge clk or posedge rst) begin + if(rst) begin + chunk_num_left <= 'd0; + end + else if(cur_state == IDLE_s && map_req_valid && map_req_head[`CEU_CMD_TYPE_OFFSET == `MAP_ICM_CXT] && map_req_head[`CEU_CMD_OPCODE_OFFSET] == `MAP_ICM_EN) begin + chunk_num_left <= map_req_head[`CEU_CMD_CHUNK_NUM_OFFSET]; + end + else if(cur_state == MAP_HIGH_s && map_req_valid) begin + chunk_num_left <= chunk_num_left - 'd1; + end + else if(cur_state == MAP_LOW_s && map_req_valid) begin + chunk_num_left <= chunk_num_left - 'd1; + end + else begin + chunk_num_left <= chunk_num_left; + end +end + +//-- qpc_base -- +//-- qpc_num -- +//-- qpc_end -- +//-- cqc_base -- +//-- cqc_num -- +//-- cqc_end -- +//-- eqc_base -- +//-- eqc_num -- +//-- eqc_end -- +always @(posedge clk or posedge rst) begin + if(rst) begin + qpc_base <= 'd0; + qpc_num <= 'd0; + qpc_end <= 'd0; + + cqc_base <= 'd0; + cqc_num <= 'd0; + cqc_end <= 'd0; + + eqc_base <= 'd0; + eqc_num <= 'd0; + eqc_end <= 'd0; + end + else if(cur_state == MAP_BASE_s) begin + qpc_base <= {map_req_data[`QPC_BASE_OFFSET], 8'd0}; + qpc_num <= 1 << map_req_data[`QPC_NUM_LOG_OFFSET]; + qpc_end <= {map_req_data[`QPC_BASE_OFFSET], 8'd0} + (1 << map_req_data[`QPC_NUM_LOG_OFFSET]) * `ICM_SLOT_SIZE_QPC; + + cqc_base <= {map_req_data[`CQC_BASE_OFFSET], 8'd0}; + cqc_num <= 1 << map_req_data[`CQC_NUM_LOG_OFFSET]; + cqc_end <= {map_req_data[`CQC_BASE_OFFSET], 8'd0} + (1 << map_req_data[`CQC_NUM_LOG_OFFSET]) * `ICM_SLOT_SIZE_CQC; + + eqc_base <= {map_req_data[`EQC_BASE_OFFSET], 8'd0}; + eqc_num <= 1 << map_req_data[`EQC_NUM_LOG_OFFSET]; + eqc_end <= {map_req_data[`EQC_BASE_OFFSET], 8'd0} + (1 << map_req_data[`EQC_NUM_LOG_OFFSET]) * `ICM_SLOT_SIZE_EQC; + end + else begin + qpc_base <= qpc_base; + qpc_num <= qpc_num; + qpc_end <= qpc_end; + + cqc_base <= cqc_base; + cqc_num <= cqc_num; + cqc_end <= cqc_end; + + eqc_base <= eqc_base; + eqc_num <= eqc_num; + eqc_end <= eqc_end; + end +end + + +//-- qpc_mapping_set_valid -- +//-- qpc_mapping_set_head -- +//-- qpc_mapping_set_data -- +//-- cqc_mapping_set_valid -- +//-- cqc_mapping_set_head -- +//-- cqc_mapping_set_data -- +//-- eqc_mapping_set_valid -- +//-- eqc_mapping_set_head -- +//-- eqc_mapping_set_data -- +always @(posedge clk or posedge rst) begin + if(rst) begin + qpc_mapping_set_valid <= 'd0; + qpc_mapping_set_head <= 'd0; + qpc_mapping_set_data <= 'd0; + + cqc_mapping_set_valid <= 'd0; + cqc_mapping_set_head <= 'd0; + cqc_mapping_set_data <= 'd0; + + eqc_mapping_set_valid <= 'd0; + eqc_mapping_set_head <= 'd0; + eqc_mapping_set_data <= 'd0; + end + else if(cur_state == MAP_HIGH_s && map_req_valid) begin + qpc_mapping_set_valid <= is_qpc_mapping ? 'd1 : 'd0; + qpc_mapping_set_head <= is_qpc_mapping ? qpc_addr : 'd0; + qpc_mapping_set_data <= is_qpc_mapping ? phy_addr : 'd0; + + cqc_mapping_set_valid <= is_cqc_mapping ? 'd1 : 'd0; + cqc_mapping_set_head <= is_cqc_mapping ? cqc_addr : 'd0; + cqc_mapping_set_data <= is_cqc_mapping ? phy_addr : 'd0; + + eqc_mapping_set_valid <= is_eqc_mapping ? 'd1 : 'd0; + eqc_mapping_set_head <= is_eqc_mapping ? eqc_addr : 'd0; + eqc_mapping_set_data <= is_eqc_mapping ? phy_addr : 'd0; + end + else if(cur_state == MAP_LOW_s && map_req_valid) begin + qpc_mapping_set_valid <= is_qpc_mapping ? 'd1 : 'd0; + qpc_mapping_set_head <= is_qpc_mapping ? qpc_addr : 'd0; + qpc_mapping_set_data <= is_qpc_mapping ? phy_addr : 'd0; + + cqc_mapping_set_valid <= is_cqc_mapping ? 'd1 : 'd0; + cqc_mapping_set_head <= is_cqc_mapping ? cqc_addr : 'd0; + cqc_mapping_set_data <= is_cqc_mapping ? phy_addr : 'd0; + + eqc_mapping_set_valid <= is_eqc_mapping ? 'd1 : 'd0; + eqc_mapping_set_head <= is_eqc_mapping ? eqc_addr : 'd0; + eqc_mapping_set_data <= is_eqc_mapping ? phy_addr : 'd0; + end + else begin + qpc_mapping_set_valid <= 'd0; + qpc_mapping_set_head <= 'd0; + qpc_mapping_set_data <= 'd0; + + cqc_mapping_set_valid <= 'd0; + cqc_mapping_set_head <= 'd0; + cqc_mapping_set_data <= 'd0; + + eqc_mapping_set_valid <= 'd0; + eqc_mapping_set_head <= 'd0; + eqc_mapping_set_data <= 'd0; + end +end + +//-- map_req_ready -- +assign map_req_ready = (cur_state == MAP_BASE_s) ? 'd1 : + (cur_state == MAP_LOW_s) ? 'd1 : + (cur_state == MAP_HIGH_s && chunk_num_left == 1) ? 'd1 : + (cur_state == MAP_DIS_s) ? 'd1 : + (cur_state == ICM_DIS_s) ? 'd1 : 'd0; +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ + +`ifdef ILA_ON + +ila_sw_acc_cm_thread_5 ila_sw_acc_cm_thread_5_inst( + .clk(clk), + + .probe0(map_req_valid), + .probe1(map_req_head), + .probe2(map_req_data), + .probe3(map_req_last), + .probe4(map_req_ready), + + .probe5(qpc_mapping_set_valid), + .probe6(qpc_mapping_set_head), + .probe7(qpc_mapping_set_data), + + .probe8(cqc_mapping_set_valid), + .probe9(cqc_mapping_set_head), + .probe10(cqc_mapping_set_data), + + .probe11(eqc_mapping_set_valid), + .probe12(eqc_mapping_set_head), + .probe13(eqc_mapping_set_data), + + .probe14(qpc_base), + .probe15(cqc_base), + .probe16(eqc_base) +); + +`endif + +/*------------------------------------------- Local Macros Undef : Begin --------------------------------------------*/ +`undef CEU_CMD_TYPE_OFFSET +`undef CEU_CMD_OPCODE_OFFSET +`undef CEU_CMD_CHUNK_NUM_OFFSET + +`undef EQC_BASE_OFFSET +`undef EQC_NUM_LOG_OFFSET +`undef CQC_BASE_OFFSET +`undef CQC_NUM_LOG_OFFSET +`undef QPC_BASE_OFFSET +`undef QPC_NUM_LOG_OFFSET +/*------------------------------------------- Local Macros Undef : End ----------------------------------------------*/ + +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/ICMMgt/ICMCache/ICMBuffer/ICMBuffer.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/ICMMgt/ICMCache/ICMBuffer/ICMBuffer.v new file mode 100644 index 0000000000000000000000000000000000000000..86fe443f92433cdd2c476b43010ec7132c10c4c8 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/ICMMgt/ICMCache/ICMBuffer/ICMBuffer.v @@ -0,0 +1,290 @@ +/*------------------------------------------- Module Description : Begin ---------------------------------------------- +Name: ICMBuffer +Author: YangFan +Function: 2-Way-Associate Cache Buffer, provide generalized Get/Set/Del Interface. +--------------------------------------------- Module Decription : End -----------------------------------------------*/ + +/*------------------------------------------- Timescale Definition : Begin ------------------------------------------*/ +`timescale 1ns / 1ps +/*------------------------------------------- Timescale Definition : End --------------------------------------------*/ + +/*------------------------------------------- Included Files : Begin ------------------------------------------------*/ +`include "protocol_engine_def.vh" +/*------------------------------------------- Included Files : End --------------------------------------------------*/ + +/*------------------------------------------- Input/Output Definition : Begin ---------------------------------------*/ +module ICMBuffer +#( + parameter ICM_CACHE_TYPE = `CACHE_TYPE_MTT, + parameter ICM_PAGE_NUM = `ICM_PAGE_NUM_MTT, + parameter ICM_PAGE_NUM_LOG = log2b(ICM_PAGE_NUM - 1), + parameter ICM_ENTRY_NUM = `ICM_ENTRY_NUM_MTT, + parameter ICM_ENTRY_NUM_LOG = log2b(ICM_ENTRY_NUM - 1), + parameter ICM_SLOT_SIZE = `ICM_SLOT_SIZE_MTT, + parameter ICM_ADDR_WIDTH = 64, + + parameter CACHE_ADDR_WIDTH = log2b(ICM_ENTRY_NUM * ICM_SLOT_SIZE), + parameter CACHE_ENTRY_WIDTH = 256, + parameter CACHE_SET_NUM = 1024, + parameter CACHE_SET_NUM_LOG = log2b(CACHE_SET_NUM - 1), + parameter CACHE_OFFSET_WIDTH = log2b(ICM_SLOT_SIZE - 1), + parameter CACHE_TAG_WIDTH = CACHE_ADDR_WIDTH - CACHE_OFFSET_WIDTH - CACHE_SET_NUM_LOG, + parameter PHYSICAL_ADDR_WIDTH = `PHY_SPACE_ADDR_WIDTH, + parameter COUNT_MAX = 2, + parameter COUNT_MAX_LOG = log2b(COUNT_MAX - 1) + 1, + parameter REQ_TAG_NUM = 32, + parameter REQ_TAG_NUM_LOG = log2b(REQ_TAG_NUM - 1), + parameter REORDER_BUFFER_WIDTH = (ICM_CACHE_TYPE == `CACHE_TYPE_MTT) ? CACHE_ENTRY_WIDTH * 2 + COUNT_MAX_LOG : CACHE_ENTRY_WIDTH + COUNT_MAX_LOG +) +( + input wire clk, + input wire rst, + +//Cache Get Req Interface + input wire get_req_valid, + input wire [COUNT_MAX_LOG * 2 + `MAX_REQ_TAG_NUM_LOG + PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH - 1 : 0] get_req_head, + output wire get_req_ready, + +//Cache Get Resp Interface + output wire get_rsp_valid, + output wire [COUNT_MAX_LOG * 2 + `MAX_REQ_TAG_NUM_LOG + PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH + 1 - 1 : 0] get_rsp_head, + output wire [CACHE_ENTRY_WIDTH - 1 : 0] get_rsp_data, + input wire get_rsp_ready, + +//Cache Set Req Interface + input wire set_req_valid, + input wire [CACHE_ADDR_WIDTH - 1 : 0] set_req_head, + input wire [CACHE_ENTRY_WIDTH - 1 : 0] set_req_data, + output wire set_req_ready, + +//Cache Del Req Interface + input wire del_req_valid, + input wire [CACHE_ADDR_WIDTH - 1 : 0] del_req_head, + output wire del_req_ready +); +/*------------------------------------------- Input/Output Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Macros Definition : Begin ---------------------------------------*/ +/*------------------------------------------- Local Macros Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Variables Definition : Begin ------------------------------------*/ +wire [0:0] way_0_get_wen; +wire [CACHE_SET_NUM_LOG - 1 : 0] way_0_get_addr; +wire [CACHE_ENTRY_WIDTH + CACHE_TAG_WIDTH + 1 - 1 : 0] way_0_get_din; +wire [CACHE_ENTRY_WIDTH + CACHE_TAG_WIDTH + 1 - 1 : 0] way_0_get_dout; + +wire [0:0] way_0_set_del_wen; +wire [CACHE_SET_NUM_LOG - 1 : 0] way_0_set_del_addr; +wire [CACHE_ENTRY_WIDTH + CACHE_TAG_WIDTH + 1 - 1 : 0] way_0_set_del_din; +wire [CACHE_ENTRY_WIDTH + CACHE_TAG_WIDTH + 1 - 1 : 0] way_0_set_del_dout; + +wire [0:0] way_1_get_wen; +wire [CACHE_SET_NUM_LOG - 1 : 0] way_1_get_addr; +wire [CACHE_ENTRY_WIDTH + CACHE_TAG_WIDTH + 1 - 1 : 0] way_1_get_din; +wire [CACHE_ENTRY_WIDTH + CACHE_TAG_WIDTH + 1 - 1 : 0] way_1_get_dout; + +wire [0:0] way_1_set_del_wen; +wire [CACHE_SET_NUM_LOG - 1 : 0] way_1_set_del_addr; +wire [CACHE_ENTRY_WIDTH + CACHE_TAG_WIDTH + 1 - 1 : 0] way_1_set_del_din; +wire [CACHE_ENTRY_WIDTH + CACHE_TAG_WIDTH + 1 - 1 : 0] way_1_set_del_dout; + +wire [0:0] lru_get_wen; +wire [CACHE_SET_NUM_LOG - 1 : 0] lru_get_addr; +wire [0:0] lru_get_din; +wire [0:0] lru_get_dout; + +wire [0:0] lru_set_del_wen; +wire [CACHE_SET_NUM_LOG - 1 : 0] lru_set_del_addr; +wire [0:0] lru_set_del_din; +wire [0:0] lru_set_del_dout; + +/*------------------------------------------- Local Variables Definition : End --------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : Begin ---------------------------------------*/ +SRAM_TDP_Template #( + .RAM_WIDTH ( CACHE_ENTRY_WIDTH + CACHE_TAG_WIDTH + 1 ), + .RAM_DEPTH ( CACHE_SET_NUM ) +) +Cache_Way_0 +( + .clk ( clk ), + .rst ( rst ), + + .wea ( way_0_get_wen ), + .addra ( way_0_get_addr ), + .dina ( way_0_get_din ), + .douta ( way_0_get_dout ), + + .web ( way_0_set_del_wen ), + .addrb ( way_0_set_del_addr ), + .dinb ( way_0_set_del_din ), + .doutb ( way_0_set_del_dout ) +); + +SRAM_TDP_Template #( + .RAM_WIDTH ( CACHE_ENTRY_WIDTH + CACHE_TAG_WIDTH + 1 ), + .RAM_DEPTH ( CACHE_SET_NUM ) +) +Cache_Way_1 +( + .clk ( clk ), + .rst ( rst ), + + .wea ( way_1_get_wen ), + .addra ( way_1_get_addr ), + .dina ( way_1_get_din ), + .douta ( way_1_get_dout ), + + .web ( way_1_set_del_wen ), + .addrb ( way_1_set_del_addr ), + .dinb ( way_1_set_del_din ), + .doutb ( way_1_set_del_dout ) +); + +SRAM_TDP_Template #( + .RAM_WIDTH ( 1 ), + .RAM_DEPTH ( CACHE_SET_NUM ) +) +LRU_Table +( + .clk ( clk ), + .rst ( rst ), + + .wea ( lru_get_wen ), + .addra ( lru_get_addr ), + .dina ( lru_get_din ), + .douta ( lru_get_dout ), + + .web ( lru_set_del_wen ), + .addrb ( lru_set_del_addr ), + .dinb ( lru_set_del_din ), + .doutb ( lru_set_del_dout ) +); + +ICMBuffer_Get_Thread +#( + .ICM_CACHE_TYPE ( ICM_CACHE_TYPE ), + .CACHE_ADDR_WIDTH ( CACHE_ADDR_WIDTH ), + .CACHE_ENTRY_WIDTH ( CACHE_ENTRY_WIDTH ), + .CACHE_OFFSET_WIDTH ( CACHE_OFFSET_WIDTH ), + .CACHE_TAG_WIDTH ( CACHE_TAG_WIDTH ), + .CACHE_SET_NUM ( CACHE_SET_NUM ), + .CACHE_SET_NUM_LOG ( CACHE_SET_NUM_LOG ), + .PHYSICAL_ADDR_WIDTH ( PHYSICAL_ADDR_WIDTH ), + .COUNT_MAX ( COUNT_MAX ), + .COUNT_MAX_LOG ( COUNT_MAX_LOG ), + .REQ_TAG_NUM ( REQ_TAG_NUM ), + .REQ_TAG_NUM_LOG ( REQ_TAG_NUM_LOG ) +) +ICMBuffer_Get_Thread_Inst +( + .clk ( clk ), + .rst ( rst ), + + .get_req_valid ( get_req_valid ), + .get_req_head ( get_req_head ), + .get_req_ready ( get_req_ready ), + + .get_rsp_valid ( get_rsp_valid ), + .get_rsp_head ( get_rsp_head ), + .get_rsp_data ( get_rsp_data ), + .get_rsp_ready ( get_rsp_ready ), + + .way_0_wen ( way_0_get_wen ), + .way_0_addr ( way_0_get_addr ), + .way_0_din ( way_0_get_din ), + .way_0_dout ( way_0_get_dout ), + + .way_1_wen ( way_1_get_wen ), + .way_1_addr ( way_1_get_addr ), + .way_1_din ( way_1_get_din ), + .way_1_dout ( way_1_get_dout ), + + .lru_wen ( lru_get_wen ), + .lru_addr ( lru_get_addr ), + .lru_din ( lru_get_din ), + .lru_dout ( lru_get_dout ) +); + +ICMBuffer_Set_Del_Thread +#( + .ICM_CACHE_TYPE ( ICM_CACHE_TYPE ), + .CACHE_ADDR_WIDTH ( CACHE_ADDR_WIDTH ), + .CACHE_ENTRY_WIDTH ( CACHE_ENTRY_WIDTH ), + .CACHE_OFFSET_WIDTH ( CACHE_OFFSET_WIDTH ), + .CACHE_TAG_WIDTH ( CACHE_TAG_WIDTH ), + .CACHE_SET_NUM ( CACHE_SET_NUM ), + .CACHE_SET_NUM_LOG ( CACHE_SET_NUM_LOG ), + .PHYSICAL_ADDR_WIDTH ( PHYSICAL_ADDR_WIDTH ), + .COUNT_MAX ( COUNT_MAX ), + .COUNT_MAX_LOG ( COUNT_MAX_LOG ), + .REQ_TAG_NUM ( REQ_TAG_NUM ), + .REQ_TAG_NUM_LOG ( REQ_TAG_NUM_LOG ) +) +ICMBuffer_Set_Del_Thread_Inst +( + .clk ( clk ), + .rst ( rst ), + + .set_req_valid ( set_req_valid ), + .set_req_head ( set_req_head ), + .set_req_data ( set_req_data ), + .set_req_ready ( set_req_ready ), + + .del_req_valid ( del_req_valid ), + .del_req_head ( del_req_head ), + .del_req_ready ( del_req_ready ), + + .way_0_wen ( way_0_set_del_wen ), + .way_0_addr ( way_0_set_del_addr ), + .way_0_din ( way_0_set_del_din ), + .way_0_dout ( way_0_set_del_dout ), + + .way_1_wen ( way_1_set_del_wen ), + .way_1_addr ( way_1_set_del_addr ), + .way_1_din ( way_1_set_del_din ), + .way_1_dout ( way_1_set_del_dout ), + + .lru_wen ( lru_set_del_wen ), + .lru_addr ( lru_set_del_addr ), + .lru_din ( lru_set_del_din ), + .lru_dout ( lru_set_del_dout ) +); +/*------------------------------------------- Submodules Instatiation : End -----------------------------------------*/ + +/*------------------------------------------- State Machine Definition : Begin --------------------------------------*/ +/*------------------------------------------- State Machine Definition : End ----------------------------------------*/ + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ + +`ifdef ILA_ON + + generate + + if(ICM_CACHE_TYPE == `CACHE_TYPE_QPC) begin + ila_icm_buffer ila_icm_buffer_inst( + .clk(clk), + + .probe0(get_req_valid), + .probe1(get_req_head), + .probe2(get_req_ready), + + .probe3(get_rsp_valid), + .probe4(get_rsp_head), + .probe5(get_rsp_data), + .probe6(get_rsp_ready), + + .probe7(set_req_valid), + .probe8(set_req_head), + .probe9(set_req_data), + .probe10(set_req_ready) + ); + end + endgenerate +`endif + +/*------------------------------------------- Local Macros Undef : Begin --------------------------------------------*/ +/*------------------------------------------- Local Macros Undef : End ----------------------------------------------*/ + +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/ICMMgt/ICMCache/ICMBuffer/ICMBuffer_Get_Thread.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/ICMMgt/ICMCache/ICMBuffer/ICMBuffer_Get_Thread.v new file mode 100644 index 0000000000000000000000000000000000000000..f4fd47ebdc11d3240e82ce4cb0a7ac1da08cff5e --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/ICMMgt/ICMCache/ICMBuffer/ICMBuffer_Get_Thread.v @@ -0,0 +1,222 @@ +/*------------------------------------------- Module Description : Begin ---------------------------------------------- +Name: ICMBuffer_Get_Thread +Author: YangFan +Function: Get entry from SRAM. +--------------------------------------------- Module Decription : End -----------------------------------------------*/ + +/*------------------------------------------- Timescale Definition : Begin ------------------------------------------*/ +`timescale 1ns / 1ps +/*------------------------------------------- Timescale Definition : End --------------------------------------------*/ + +/*------------------------------------------- Included Files : Begin ------------------------------------------------*/ +`include "protocol_engine_def.vh" +/*------------------------------------------- Included Files : End --------------------------------------------------*/ + +/*------------------------------------------- Input/Output Definition : Begin ---------------------------------------*/ +module ICMBuffer_Get_Thread +#( + parameter ICM_CACHE_TYPE = `CACHE_TYPE_MTT, + parameter ICM_PAGE_NUM = `ICM_PAGE_NUM_MTT, + parameter ICM_PAGE_NUM_LOG = log2b(ICM_PAGE_NUM - 1), + parameter ICM_ENTRY_NUM = `ICM_ENTRY_NUM_MTT, + parameter ICM_ENTRY_NUM_LOG = log2b(ICM_ENTRY_NUM - 1), + parameter ICM_SLOT_SIZE = `ICM_SLOT_SIZE_MTT, + parameter ICM_ADDR_WIDTH = 64, + + parameter CACHE_ADDR_WIDTH = log2b(ICM_ENTRY_NUM * ICM_SLOT_SIZE - 1), + parameter CACHE_ENTRY_WIDTH = 256, + parameter CACHE_SET_NUM = 1024, + parameter CACHE_SET_NUM_LOG = log2b(CACHE_SET_NUM - 1), + parameter CACHE_OFFSET_WIDTH = log2b(ICM_SLOT_SIZE - 1), + parameter CACHE_TAG_WIDTH = CACHE_ADDR_WIDTH - CACHE_OFFSET_WIDTH - CACHE_SET_NUM_LOG, + parameter PHYSICAL_ADDR_WIDTH = `PHY_SPACE_ADDR_WIDTH, + parameter COUNT_MAX = 2, + parameter COUNT_MAX_LOG = log2b(COUNT_MAX - 1) + 1, + parameter REQ_TAG_NUM = 32, + parameter REQ_TAG_NUM_LOG = log2b(REQ_TAG_NUM - 1), + parameter REORDER_BUFFER_WIDTH = (ICM_CACHE_TYPE == `CACHE_TYPE_MTT) ? CACHE_ENTRY_WIDTH * 2 + COUNT_MAX_LOG : CACHE_ENTRY_WIDTH + COUNT_MAX_LOG +) +( + input wire clk, + input wire rst, + +//Cache Get Req Interface + input wire get_req_valid, + input wire [COUNT_MAX_LOG * 2 + `MAX_REQ_TAG_NUM_LOG + PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH - 1 : 0] get_req_head, + output wire get_req_ready, + +//Cache Get Resp Interface + output wire get_rsp_valid, + output wire [COUNT_MAX_LOG * 2 + `MAX_REQ_TAG_NUM_LOG + PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH + 1 - 1 : 0] get_rsp_head, + output wire [CACHE_ENTRY_WIDTH - 1 : 0] get_rsp_data, + input wire get_rsp_ready, + +//SRAM operation + output wire [0:0] way_0_wen, + output wire [CACHE_SET_NUM_LOG - 1 : 0] way_0_addr, + output wire [CACHE_ENTRY_WIDTH + CACHE_TAG_WIDTH + 1 - 1 : 0] way_0_din, + input wire [CACHE_ENTRY_WIDTH + CACHE_TAG_WIDTH + 1 - 1 : 0] way_0_dout, + + + output wire [0:0] way_1_wen, + output wire [CACHE_SET_NUM_LOG - 1 : 0] way_1_addr, + output wire [CACHE_ENTRY_WIDTH + CACHE_TAG_WIDTH + 1 - 1 : 0] way_1_din, + input wire [CACHE_ENTRY_WIDTH + CACHE_TAG_WIDTH + 1 - 1 : 0] way_1_dout, + + output wire [0:0] lru_wen, + output wire [CACHE_SET_NUM_LOG - 1 : 0] lru_addr, + output wire [0:0] lru_din, + input wire [0:0] lru_dout +); +/*------------------------------------------- Input/Output Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Macros Definition : Begin ---------------------------------------*/ +`define VALID 1'b1 +`define WAY_0 1'b0 +`define WAY_1 1'b1 +/*------------------------------------------- Local Macros Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Variables Definition : Begin ------------------------------------*/ +reg [COUNT_MAX_LOG * 2 + `MAX_REQ_TAG_NUM_LOG + PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH - 1 : 0] get_req_head_diff; +wire [CACHE_ADDR_WIDTH - 1 : 0] cache_addr; +wire [CACHE_TAG_WIDTH - 1 : 0] cache_tag; +wire [CACHE_SET_NUM_LOG - 1 : 0] cache_set; + +wire [CACHE_TAG_WIDTH - 1 : 0] way_0_cache_tag; +wire [CACHE_TAG_WIDTH - 1 : 0] way_1_cache_tag; +wire way_0_valid; +wire way_1_valid; + +wire cache_hit; +wire way_0_hit; +wire way_1_hit; + +/*------------------------------------------- Local Variables Definition : End --------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : Begin ---------------------------------------*/ +/*------------------------------------------- Submodules Instatiation : End -----------------------------------------*/ + +/*------------------------------------------- State Machine Definition : Begin --------------------------------------*/ +reg [1:0] cur_state; +reg [1:0] next_state; + +parameter [1:0] IDLE_s = 2'd1, + RSP_s = 2'd2; + +always @(posedge clk or posedge rst) begin + if(rst) begin + cur_state <= IDLE_s; + end + else begin + cur_state <= next_state; + end +end + +always @(*) begin + case(cur_state) + IDLE_s: if(get_req_valid) begin + next_state = RSP_s; + end + else begin + next_state = IDLE_s; + end + RSP_s: if(get_rsp_valid && get_rsp_ready) begin + next_state = IDLE_s; + end + else begin + next_state = RSP_s; + end + default: next_state = IDLE_s; + endcase +end +/*------------------------------------------- State Machine Definition : End ----------------------------------------*/ + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ +//-- get_req_head_diff -- +always @(posedge clk or posedge rst) begin + if(rst) begin + get_req_head_diff <= 'd0; + end + else if(cur_state == IDLE_s && get_req_valid) begin + get_req_head_diff <= get_req_head; + end + else if(cur_state == RSP_s && get_rsp_valid && get_rsp_ready) begin + get_req_head_diff <= 'd0; + end + else begin + get_req_head_diff <= get_req_head_diff; + end +end + +//-- cache_addr -- +assign cache_addr = (cur_state == IDLE_s && get_req_valid) ? get_req_head[CACHE_ADDR_WIDTH - 1 : 0] : + (cur_state == RSP_s) ? get_req_head_diff[CACHE_ADDR_WIDTH - 1 : 0] : 'd0; + +//-- cache_tag -- +assign cache_tag = cache_addr[CACHE_TAG_WIDTH + CACHE_SET_NUM_LOG + CACHE_OFFSET_WIDTH - 1 : CACHE_SET_NUM_LOG + CACHE_OFFSET_WIDTH]; + + +//-- cache_set -- +assign cache_set = cache_addr[CACHE_SET_NUM_LOG + CACHE_OFFSET_WIDTH - 1 : CACHE_OFFSET_WIDTH]; + +//-- get_req_ready -- +assign get_req_ready = (cur_state == IDLE_s) ? 'd1 : 'd0; + +//-- get_rsp_valid -- +//-- get_rsp_head -- +//-- get_rsp_data -- +assign get_rsp_valid = (cur_state == RSP_s) ? 'd1 : 'd0; +assign get_rsp_head = (cur_state == RSP_s) ? {cache_hit, get_req_head_diff} : 'd0; +assign get_rsp_data = (cur_state == RSP_s && way_0_hit) ? way_0_dout : + (cur_state == RSP_s && way_1_hit) ? way_1_dout : 'd0; + + +//-- cache_hit -- +assign cache_hit = (way_0_hit || way_1_hit); + +//-- way_0_hit -- +assign way_0_hit = (cache_tag == way_0_cache_tag) && (way_0_valid == `VALID); + +//-- way_1_hit -- +assign way_1_hit = (cache_tag == way_1_cache_tag) && (way_1_valid == `VALID); + +//-- way_0_cache_tag -- +//-- way_1_cache_tag -- +//-- way_0_valid -- +//-- way_1_valid -- +assign way_0_cache_tag = way_0_dout[CACHE_TAG_WIDTH + CACHE_ENTRY_WIDTH - 1 : CACHE_ENTRY_WIDTH]; +assign way_1_cache_tag = way_1_dout[CACHE_TAG_WIDTH + CACHE_ENTRY_WIDTH - 1 : CACHE_ENTRY_WIDTH]; +assign way_0_valid = way_0_dout[CACHE_TAG_WIDTH + CACHE_ENTRY_WIDTH]; +assign way_1_valid = way_1_dout[CACHE_TAG_WIDTH + CACHE_ENTRY_WIDTH]; + +//-- way_0_wen -- +//-- way_0_addr -- +//-- way_0_din -- +assign way_0_wen = 'd0; //Always read +assign way_0_addr = ((cur_state == IDLE_s && get_req_valid) || (cur_state == RSP_s)) ? cache_set : 'd0; +assign way_0_din = 'd0; + +//-- way_1_wen -- +//-- way_1_addr -- +//-- way_1_din -- +assign way_1_wen = 'd0; //Always read +assign way_1_addr = ((cur_state == IDLE_s && get_req_valid) || (cur_state == RSP_s)) ? cache_set : 'd0; +assign way_1_din = 'd0; + +//-- lru_wen -- +//-- lru_addr -- +//-- lru_din -- +assign lru_wen = (cur_state == RSP_s && cache_hit) ? 'd1 : 'd0; +assign lru_addr = (cur_state == RSP_s && cache_hit) ? cache_set : 'd0; +assign lru_din = (cur_state == RSP_s && way_0_hit) ? `WAY_0 : + (cur_state == RSP_s && way_1_hit) ? `WAY_1 : 'd0; + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ + +/*------------------------------------------- Local Macros Undef : Begin --------------------------------------------*/ +`undef VALID +`undef WAY_0 +`undef WAY_1 +/*------------------------------------------- Local Macros Undef : End ----------------------------------------------*/ + +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/ICMMgt/ICMCache/ICMBuffer/ICMBuffer_Set_Del_Thread.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/ICMMgt/ICMCache/ICMBuffer/ICMBuffer_Set_Del_Thread.v new file mode 100644 index 0000000000000000000000000000000000000000..739760504526cb7a47edd52ab0d7470543956f92 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/ICMMgt/ICMCache/ICMBuffer/ICMBuffer_Set_Del_Thread.v @@ -0,0 +1,306 @@ +/*------------------------------------------- Module Description : Begin ---------------------------------------------- +Name: ICMBuffer_Set_Del_Thread +Author: YangFan +Function: Set/Del entry from SRAM. +--------------------------------------------- Module Decription : End -----------------------------------------------*/ + +/*------------------------------------------- Timescale Definition : Begin ------------------------------------------*/ +`timescale 1ns / 1ps +/*------------------------------------------- Timescale Definition : End --------------------------------------------*/ + +/*------------------------------------------- Included Files : Begin ------------------------------------------------*/ +`include "protocol_engine_def.vh" +/*------------------------------------------- Included Files : End --------------------------------------------------*/ + +/*------------------------------------------- Input/Output Definition : Begin ---------------------------------------*/ +module ICMBuffer_Set_Del_Thread +#( + parameter ICM_CACHE_TYPE = `CACHE_TYPE_MTT, + parameter ICM_PAGE_NUM = `ICM_PAGE_NUM_MTT, + parameter ICM_PAGE_NUM_LOG = log2b(ICM_PAGE_NUM - 1), + parameter ICM_ENTRY_NUM = `ICM_ENTRY_NUM_MTT, + parameter ICM_ENTRY_NUM_LOG = log2b(ICM_ENTRY_NUM - 1), + parameter ICM_SLOT_SIZE = `ICM_SLOT_SIZE_MTT, + parameter ICM_ADDR_WIDTH = 64, + + parameter CACHE_ADDR_WIDTH = log2b(ICM_ENTRY_NUM * ICM_SLOT_SIZE - 1), + parameter CACHE_ENTRY_WIDTH = 256, + parameter CACHE_SET_NUM = 1024, + parameter CACHE_SET_NUM_LOG = log2b(CACHE_SET_NUM - 1), + parameter CACHE_OFFSET_WIDTH = log2b(ICM_SLOT_SIZE - 1), + parameter CACHE_TAG_WIDTH = CACHE_ADDR_WIDTH - CACHE_OFFSET_WIDTH - CACHE_SET_NUM_LOG, + parameter PHYSICAL_ADDR_WIDTH = `PHY_SPACE_ADDR_WIDTH, + parameter COUNT_MAX = 2, + parameter COUNT_MAX_LOG = log2b(COUNT_MAX - 1) + 1, + parameter REQ_TAG_NUM = 32, + parameter REQ_TAG_NUM_LOG = log2b(REQ_TAG_NUM - 1), + parameter REORDER_BUFFER_WIDTH = (ICM_CACHE_TYPE == `CACHE_TYPE_MTT) ? CACHE_ENTRY_WIDTH * 2 + COUNT_MAX_LOG : CACHE_ENTRY_WIDTH + COUNT_MAX_LOG +) +( + input wire clk, + input wire rst, + +//Cache Set Req Interface + input wire set_req_valid, + input wire [ICM_ADDR_WIDTH - 1 : 0] set_req_head, + input wire [CACHE_ENTRY_WIDTH - 1 : 0] set_req_data, + output wire set_req_ready, + +//Cache Del Req Interface + input wire del_req_valid, + input wire [ICM_ADDR_WIDTH - 1 : 0] del_req_head, + output wire del_req_ready, + +//SRAM operation + output reg [0:0] way_0_wen, + output reg [CACHE_SET_NUM_LOG - 1 : 0] way_0_addr, + output reg [CACHE_ENTRY_WIDTH + CACHE_TAG_WIDTH + 1 - 1 : 0] way_0_din, + input wire [CACHE_ENTRY_WIDTH + CACHE_TAG_WIDTH + 1 - 1 : 0] way_0_dout, + + + output reg [0:0] way_1_wen, + output reg [CACHE_SET_NUM_LOG - 1 : 0] way_1_addr, + output reg [CACHE_ENTRY_WIDTH + CACHE_TAG_WIDTH + 1 - 1 : 0] way_1_din, + input wire [CACHE_ENTRY_WIDTH + CACHE_TAG_WIDTH + 1 - 1 : 0] way_1_dout, + + output reg [0:0] lru_wen, + output reg [CACHE_SET_NUM_LOG - 1 : 0] lru_addr, + output reg [0:0] lru_din, + input wire [0:0] lru_dout +); +/*------------------------------------------- Input/Output Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Macros Definition : Begin ---------------------------------------*/ +`define VALID 1'b1 +`define INVALID 1'b0 +`define WAY_0 1'b0 +`define WAY_1 1'b1 +/*------------------------------------------- Local Macros Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Variables Definition : Begin ------------------------------------*/ +reg [COUNT_MAX_LOG * 2 + REQ_TAG_NUM_LOG + PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH - 1 : 0] set_req_head_diff; +reg [COUNT_MAX_LOG * 2 + REQ_TAG_NUM_LOG + PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH - 1 : 0] del_req_head_diff; +reg [CACHE_ENTRY_WIDTH - 1 : 0] set_req_data_diff; +wire [CACHE_ADDR_WIDTH - 1 : 0] cache_addr; +wire [CACHE_TAG_WIDTH - 1 : 0] cache_tag; +wire [CACHE_SET_NUM_LOG - 1 : 0] cache_set; +wire [CACHE_ENTRY_WIDTH - 1 : 0] cache_data; + +wire way_0_hit; +wire way_1_hit; + +/*------------------------------------------- Local Variables Definition : End --------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : Begin ---------------------------------------*/ +/*------------------------------------------- Submodules Instatiation : End -----------------------------------------*/ + +/*------------------------------------------- State Machine Definition : Begin --------------------------------------*/ +reg [1:0] cur_state; +reg [1:0] next_state; + +parameter [1:0] IDLE_s = 2'd1, + SET_s = 2'd2, + DEL_s = 2'd3; + +always @(posedge clk or posedge rst) begin + if(rst) begin + cur_state <= IDLE_s; + end + else begin + cur_state <= next_state; + end +end + +always @(*) begin + case(cur_state) + IDLE_s: if(set_req_valid) begin + next_state = SET_s; + end + else if(del_req_valid) begin + next_state = DEL_s; + end + else begin + next_state = IDLE_s; + end + SET_s: next_state = IDLE_s; + DEL_s: next_state = IDLE_s; + default: next_state = IDLE_s; + endcase +end +/*------------------------------------------- State Machine Definition : End ----------------------------------------*/ + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ +//-- set_req_head_diff -- +always @(posedge clk or posedge rst) begin + if(rst) begin + set_req_head_diff <= 'd0; + end + else if(cur_state == IDLE_s && set_req_valid) begin + set_req_head_diff <= set_req_head; + end + else if(cur_state == SET_s) begin + set_req_head_diff <= 'd0; + end + else begin + set_req_head_diff <= set_req_head_diff; + end +end + +//-- del_req_head_diff -- +always @(posedge clk or posedge rst) begin + if(rst) begin + del_req_head_diff <= 'd0; + end + else if(cur_state == IDLE_s && del_req_valid) begin + del_req_head_diff <= del_req_head; + end + else if(cur_state == DEL_s) begin + del_req_head_diff <= 'd0; + end + else begin + del_req_head_diff <= del_req_head_diff; + end +end + +//-- set_req_data_diff -- +always @(posedge clk or posedge rst) begin + if(rst) begin + set_req_data_diff <= 'd0; + end + else if(cur_state == IDLE_s && set_req_valid) begin + set_req_data_diff <= set_req_data; + end + else if(cur_state == SET_s) begin + set_req_data_diff <= 'd0; + end + else begin + set_req_data_diff <= set_req_data_diff; + end +end + +//-- cache_addr -- +assign cache_addr = (cur_state == IDLE_s && set_req_valid) ? set_req_head[CACHE_ADDR_WIDTH - 1 : 0] : + (cur_state == IDLE_s && del_req_valid) ? del_req_head[CACHE_ADDR_WIDTH - 1 : 0] : + (cur_state == SET_s) ? set_req_head_diff[CACHE_ADDR_WIDTH - 1 : 0] : + (cur_state == DEL_s) ? del_req_head_diff[CACHE_ADDR_WIDTH - 1 : 0] : 'd0; + +//-- cache_tag -- +assign cache_tag = cache_addr[CACHE_TAG_WIDTH + CACHE_SET_NUM_LOG + CACHE_OFFSET_WIDTH - 1 : CACHE_SET_NUM_LOG + CACHE_OFFSET_WIDTH]; + + +//-- cache_set -- +assign cache_set = cache_addr[CACHE_SET_NUM_LOG + CACHE_OFFSET_WIDTH - 1 : CACHE_OFFSET_WIDTH]; + +//-- cache_data -- +assign cache_data = (cur_state == IDLE_s && set_req_valid) ? set_req_data : + (cur_state == SET_s) ? set_req_data_diff : 'd0; + +//-- way_0_hit -- +assign way_0_hit = (cache_tag == way_0_dout[CACHE_TAG_WIDTH + CACHE_ENTRY_WIDTH - 1 : CACHE_ENTRY_WIDTH]) && (way_0_dout[CACHE_TAG_WIDTH + CACHE_ENTRY_WIDTH] == `VALID); + +//-- way_1_hit -- +assign way_1_hit = (cache_tag == way_1_dout[CACHE_TAG_WIDTH + CACHE_ENTRY_WIDTH - 1 : CACHE_ENTRY_WIDTH]) && (way_1_dout[CACHE_TAG_WIDTH + CACHE_ENTRY_WIDTH] == `VALID); + +//-- way_0_wen -- +//-- way_0_addr -- +//-- way_0_din -- +always @(*) begin + if(rst) begin + way_0_wen = 'd0; + way_0_addr = 'd0; + way_0_din = 'd0; + end + else if(cur_state == IDLE_s && (set_req_valid || del_req_valid)) begin + way_0_wen = 'd0; + way_0_addr = cache_set; + way_0_din = 'd0; + end + else if(cur_state == SET_s) begin + way_0_wen = (lru_dout == `WAY_1) ? 'd1 : 'd0; + way_0_addr = (lru_dout == `WAY_1) ? cache_set : 'd0; + way_0_din = (lru_dout == `WAY_1) ? {`VALID, cache_tag, cache_data} : 'd0; + end + else if(cur_state == DEL_s) begin + way_0_wen = way_0_hit ? 'd1 : 'd0; + way_0_addr = way_0_hit ? cache_set : 'd0; + way_0_din = way_0_hit ? {`VALID, {CACHE_TAG_WIDTH{1'b0}}, {CACHE_ENTRY_WIDTH{1'b0}}} : 'd0; + end + else begin + way_0_wen = 'd0; + way_0_addr = 'd0; + way_0_din = 'd0; + end +end + +//-- way_1_wen -- +//-- way_1_addr -- +//-- way_1_din -- +always @(*) begin + if(rst) begin + way_1_wen = 'd0; + way_1_addr = 'd0; + way_1_din = 'd0; + end + else if(cur_state == IDLE_s && (set_req_valid || del_req_valid)) begin + way_1_wen = 'd0; + way_1_addr = cache_set; + way_1_din = 'd0; + end + else if(cur_state == SET_s) begin + way_1_wen = (lru_dout == `WAY_0) ? 'd1 : 'd0; + way_1_addr = (lru_dout == `WAY_0) ? cache_set : 'd0; + way_1_din = (lru_dout == `WAY_0) ? {`VALID, cache_tag, cache_data} : 'd0; + end + else if(cur_state == DEL_s) begin + way_1_wen = way_1_hit ? 'd1 : 'd0; + way_1_addr = way_1_hit ? cache_set : 'd0; + way_1_din = way_1_hit ? {`VALID, {CACHE_TAG_WIDTH{1'b0}}, {CACHE_ENTRY_WIDTH{1'b0}}} : 'd0; + end + else begin + way_1_wen = 'd0; + way_1_addr = 'd0; + way_1_din = 'd0; + end +end + +//-- lru_wen -- +//-- lru_addr -- +//-- lru_din -- +always @(*) begin + if(rst) begin + lru_wen = 'd0; + lru_addr = 'd0; + lru_din = 'd0; + end + else if(cur_state == IDLE_s && set_req_valid) begin + lru_wen = 'd0; + lru_addr = cache_set; + lru_din = 'd0; + end + else if(cur_state == SET_s) begin + lru_wen = 'd1; + lru_addr = cache_set; + lru_din = (lru_dout == `WAY_0) ? `WAY_1 : `WAY_0; + end + else begin + lru_wen = 'd0; + lru_addr = 'd0; + lru_din = 'd0; + end +end + +//-- set_req_ready -- +assign set_req_ready = (cur_state == SET_s); + +//-- del_req_ready -- +assign del_req_ready = (cur_state == DEL_s); +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ + +/*------------------------------------------- Local Macros Undef : Begin --------------------------------------------*/ +`undef VALID +`undef INVALID +`undef WAY_0 +`undef WAY_1 +/*------------------------------------------- Local Macros Undef : End ----------------------------------------------*/ + +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/ICMMgt/ICMCache/ICMCache.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/ICMMgt/ICMCache/ICMCache.v new file mode 100644 index 0000000000000000000000000000000000000000..6afae3fa3e55ca31a5accde312556d5881804be3 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/ICMMgt/ICMCache/ICMCache.v @@ -0,0 +1,340 @@ +/*------------------------------------------- Module Description : Begin ---------------------------------------------- +Name: ICMCache +Author: YangFan +Function: Manage ICM Data and Provides ICM Access Interface. +--------------------------------------------- Module Decription : End -----------------------------------------------*/ + +/*------------------------------------------- Timescale Definition : Begin ------------------------------------------*/ +`timescale 1ns / 1ps +/*------------------------------------------- Timescale Definition : End --------------------------------------------*/ + +/*------------------------------------------- Included Files : Begin ------------------------------------------------*/ +`include "protocol_engine_def.vh" +/*------------------------------------------- Included Files : End --------------------------------------------------*/ + +/*------------------------------------------- Input/Output Definition : Begin ---------------------------------------*/ +module ICMCache +#( + parameter ICM_CACHE_TYPE = `CACHE_TYPE_MTT, + parameter ICM_PAGE_NUM = `ICM_PAGE_NUM_MTT, + parameter ICM_PAGE_NUM_LOG = log2b(ICM_PAGE_NUM - 1), + parameter ICM_ENTRY_NUM = `ICM_ENTRY_NUM_MTT, + parameter ICM_ENTRY_NUM_LOG = log2b(ICM_ENTRY_NUM - 1), + parameter ICM_SLOT_SIZE = `ICM_SLOT_SIZE_MTT, + parameter ICM_ADDR_WIDTH = `ICM_SPACE_ADDR_WIDTH, + + parameter CACHE_ADDR_WIDTH = log2b(ICM_ENTRY_NUM * ICM_SLOT_SIZE), + parameter CACHE_ENTRY_WIDTH = 256, + parameter CACHE_SET_NUM = 1024, + parameter CACHE_SET_NUM_LOG = log2b(CACHE_SET_NUM - 1), + parameter CACHE_OFFSET_WIDTH = log2b(ICM_SLOT_SIZE - 1), + parameter CACHE_TAG_WIDTH = CACHE_ADDR_WIDTH - CACHE_OFFSET_WIDTH - CACHE_SET_NUM_LOG, + parameter PHYSICAL_ADDR_WIDTH = `PHY_SPACE_ADDR_WIDTH, + parameter COUNT_MAX = 2, + parameter COUNT_MAX_LOG = log2b(COUNT_MAX - 1) + 1, + parameter REQ_TAG_NUM = `REQ_TAG_NUM, + parameter REQ_TAG_NUM_LOG = log2b(REQ_TAG_NUM - 1), + parameter REORDER_BUFFER_WIDTH = (ICM_CACHE_TYPE == `CACHE_TYPE_MTT) ? CACHE_ENTRY_WIDTH * 2 + COUNT_MAX_LOG : CACHE_ENTRY_WIDTH + COUNT_MAX_LOG +) +( + input wire clk, + input wire rst, + +//ICM Get Req Interface + input wire icm_get_req_valid, + input wire [COUNT_MAX_LOG * 2 + `MAX_REQ_TAG_NUM_LOG + PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH - 1 : 0] icm_get_req_head, + output wire icm_get_req_ready, + +//ICM Get Resp Interface + output wire icm_get_rsp_valid, + output wire [COUNT_MAX_LOG * 2 + `MAX_REQ_TAG_NUM_LOG + PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH - 1 : 0] icm_get_rsp_head, + output wire [CACHE_ENTRY_WIDTH - 1 : 0] icm_get_rsp_data, + input wire icm_get_rsp_ready, + +//Cache Set Req Interface + input wire icm_set_req_valid, + input wire [COUNT_MAX_LOG * 2 + `MAX_REQ_TAG_NUM_LOG + PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH - 1 : 0] icm_set_req_head, + input wire [CACHE_ENTRY_WIDTH - 1 : 0] icm_set_req_data, + output wire icm_set_req_ready, + +//Cache Del Req Interface + input wire icm_del_req_valid, + input wire [CACHE_ADDR_WIDTH - 1 : 0] icm_del_req_head, + output wire icm_del_req_ready, + +//DMA Read Req Interface + output wire dma_rd_req_valid, + output wire [`DMA_HEAD_WIDTH - 1 : 0] dma_rd_req_head, + output wire [`DMA_DATA_WIDTH - 1 : 0] dma_rd_req_data, + output wire dma_rd_req_last, + input wire dma_rd_req_ready, + +//DMA Read Rsp Interface + input wire dma_rd_rsp_valid, + input wire [`DMA_HEAD_WIDTH - 1 : 0] dma_rd_rsp_head, + input wire [`DMA_DATA_WIDTH - 1 : 0] dma_rd_rsp_data, + input wire dma_rd_rsp_last, + output wire dma_rd_rsp_ready, + +//DMA Write Req Interface + output wire dma_wr_req_valid, + output wire [`DMA_HEAD_WIDTH - 1 : 0] dma_wr_req_head, + output wire [`DMA_DATA_WIDTH - 1 : 0] dma_wr_req_data, + output wire dma_wr_req_last, + input wire dma_wr_req_ready, + +//Set ICM Mapping Table Entry + input wire icm_mapping_set_valid, + input wire [`PAGE_FRAME_WIDTH - 1 : 0] icm_mapping_set_head, + input wire [`PAGE_FRAME_WIDTH - 1 : 0] icm_mapping_set_data, + +//Mapping Lookup Interface + input wire icm_mapping_lookup_valid, + input wire [ICM_ENTRY_NUM_LOG - 1 : 0] icm_mapping_lookup_head, + + output wire icm_mapping_rsp_valid, + output wire [ICM_ADDR_WIDTH - 1 : 0] icm_mapping_rsp_icm_addr, + output wire [PHYSICAL_ADDR_WIDTH - 1 : 0] icm_mapping_rsp_phy_addr, + + input wire [ICM_ADDR_WIDTH - 1 : 0] icm_base +); +/*------------------------------------------- Input/Output Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Macros Definition : Begin ---------------------------------------*/ + +/*------------------------------------------- Local Macros Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Variables Definition : Begin ------------------------------------*/ +wire cache_get_req_valid; +wire [COUNT_MAX_LOG * 2 + `MAX_REQ_TAG_NUM_LOG + PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH - 1 : 0] cache_get_req_head ; +wire cache_get_req_ready; + +wire cache_get_rsp_valid; +wire [COUNT_MAX_LOG * 2 + `MAX_REQ_TAG_NUM_LOG + PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH + 1 - 1 : 0] cache_get_rsp_head ; +wire [CACHE_ENTRY_WIDTH - 1 : 0] cache_get_rsp_data ; +wire cache_get_rsp_ready; + +wire cache_set_req_valid; +wire [ICM_ADDR_WIDTH - 1 : 0] cache_set_req_head ; +wire [CACHE_ENTRY_WIDTH - 1 : 0] cache_set_req_data ; +wire cache_set_req_ready; + +wire cache_del_req_valid; +wire [ICM_ADDR_WIDTH - 1 : 0] cache_del_req_head ; +wire cache_del_req_ready; + +//From ICMGetProc to ICMSetDelProc, update cache entry +wire replace_req_valid; +wire [ICM_ADDR_WIDTH - 1 : 0] replace_req_head ; +wire [CACHE_ENTRY_WIDTH - 1 : 0] replace_req_data ; +wire replace_req_ready; + +/*------------------------------------------- Local Variables Definition : End --------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : Begin ---------------------------------------*/ +ICMGetProc +#( + .ICM_CACHE_TYPE ( ICM_CACHE_TYPE ), + .ICM_PAGE_NUM ( ICM_PAGE_NUM ), + .ICM_PAGE_NUM_LOG ( ICM_PAGE_NUM_LOG ), + .ICM_ENTRY_NUM ( ICM_ENTRY_NUM ), + .ICM_ENTRY_NUM_LOG ( ICM_ENTRY_NUM_LOG ), + .ICM_SLOT_SIZE ( ICM_SLOT_SIZE ), + .ICM_ADDR_WIDTH ( ICM_ADDR_WIDTH ), + + .CACHE_ADDR_WIDTH ( CACHE_ADDR_WIDTH ), + .CACHE_ENTRY_WIDTH ( CACHE_ENTRY_WIDTH ), + .CACHE_SET_NUM ( CACHE_SET_NUM ), + .CACHE_SET_NUM_LOG ( CACHE_SET_NUM_LOG ), + .CACHE_OFFSET_WIDTH ( CACHE_OFFSET_WIDTH ), + .CACHE_TAG_WIDTH ( CACHE_TAG_WIDTH ), + .PHYSICAL_ADDR_WIDTH ( PHYSICAL_ADDR_WIDTH ), + .COUNT_MAX ( COUNT_MAX ), + .COUNT_MAX_LOG ( COUNT_MAX_LOG ), + .REQ_TAG_NUM ( REQ_TAG_NUM ), + .REQ_TAG_NUM_LOG ( REQ_TAG_NUM_LOG ), + .REORDER_BUFFER_WIDTH ( REORDER_BUFFER_WIDTH ) +) +ICMGetProc_Inst +( + .clk ( clk ), + .rst ( rst ), + + .icm_get_req_valid ( icm_get_req_valid ), + .icm_get_req_head ( icm_get_req_head ), + .icm_get_req_ready ( icm_get_req_ready ), + + .icm_get_rsp_valid ( icm_get_rsp_valid ), + .icm_get_rsp_head ( icm_get_rsp_head ), + .icm_get_rsp_data ( icm_get_rsp_data ), + .icm_get_rsp_ready ( icm_get_rsp_ready ), + + .cache_get_req_valid ( cache_get_req_valid ), + .cache_get_req_head ( cache_get_req_head ), + .cache_get_req_ready ( cache_get_req_ready ), + + .cache_get_rsp_valid ( cache_get_rsp_valid ), + .cache_get_rsp_head ( cache_get_rsp_head ), + .cache_get_rsp_data ( cache_get_rsp_data ), + .cache_get_rsp_ready ( cache_get_rsp_ready ), + + .cache_set_req_valid ( replace_req_valid ), + .cache_set_req_head ( replace_req_head ), + .cache_set_req_data ( replace_req_data ), + .cache_set_req_ready ( replace_req_ready ), + + .dma_rd_req_valid ( dma_rd_req_valid ), + .dma_rd_req_head ( dma_rd_req_head ), + .dma_rd_req_data ( dma_rd_req_data ), + .dma_rd_req_last ( dma_rd_req_last ), + .dma_rd_req_ready ( dma_rd_req_ready ), + + .dma_rd_rsp_valid ( dma_rd_rsp_valid ), + .dma_rd_rsp_head ( dma_rd_rsp_head ), + .dma_rd_rsp_data ( dma_rd_rsp_data ), + .dma_rd_rsp_last ( dma_rd_rsp_last ), + .dma_rd_rsp_ready ( dma_rd_rsp_ready ) +); + +ICMSetDelProc +#( + .ICM_CACHE_TYPE ( ICM_CACHE_TYPE ), + .ICM_PAGE_NUM ( ICM_PAGE_NUM ), + .ICM_PAGE_NUM_LOG ( ICM_PAGE_NUM_LOG ), + .ICM_ENTRY_NUM ( ICM_ENTRY_NUM ), + .ICM_ENTRY_NUM_LOG ( ICM_ENTRY_NUM_LOG ), + .ICM_SLOT_SIZE ( ICM_SLOT_SIZE ), + .ICM_ADDR_WIDTH ( ICM_ADDR_WIDTH ), + + .CACHE_ADDR_WIDTH ( CACHE_ADDR_WIDTH ), + .CACHE_ENTRY_WIDTH ( CACHE_ENTRY_WIDTH ), + .CACHE_SET_NUM ( CACHE_SET_NUM ), + .CACHE_SET_NUM_LOG ( CACHE_SET_NUM_LOG ), + .CACHE_OFFSET_WIDTH ( CACHE_OFFSET_WIDTH ), + .CACHE_TAG_WIDTH ( CACHE_TAG_WIDTH ), + .PHYSICAL_ADDR_WIDTH ( PHYSICAL_ADDR_WIDTH ), + .COUNT_MAX ( COUNT_MAX ), + .COUNT_MAX_LOG ( COUNT_MAX_LOG ), + .REQ_TAG_NUM ( REQ_TAG_NUM ), + .REQ_TAG_NUM_LOG ( REQ_TAG_NUM_LOG ), + .REORDER_BUFFER_WIDTH ( REORDER_BUFFER_WIDTH ) +) +ICMSetDelProc_Inst +( + .clk ( clk ), + .rst ( rst ), + + .set_req_valid_chnl_0 ( replace_req_valid ), + .set_req_head_chnl_0 ( replace_req_head ), + .set_req_data_chnl_0 ( replace_req_data ), + .set_req_ready_chnl_0 ( replace_req_ready ), + + .set_req_valid_chnl_1 ( icm_set_req_valid ), + .set_req_head_chnl_1 ( icm_set_req_head ), + .set_req_data_chnl_1 ( icm_set_req_data ), + .set_req_ready_chnl_1 ( icm_set_req_ready ), + + .del_req_valid ( icm_del_req_valid ), + .del_req_head ( icm_del_req_head ), + .del_req_ready ( icm_del_req_ready ), + + .cache_set_req_valid ( cache_set_req_valid ), + .cache_set_req_head ( cache_set_req_head ), + .cache_set_req_data ( cache_set_req_data ), + .cache_set_req_ready ( cache_set_req_ready ), + + .cache_del_req_valid ( cache_del_req_valid ), + .cache_del_req_head ( cache_del_req_head ), + .cache_del_req_ready ( cache_del_req_ready ), + + .dma_wr_req_valid ( dma_wr_req_valid ), + .dma_wr_req_head ( dma_wr_req_head ), + .dma_wr_req_data ( dma_wr_req_data ), + .dma_wr_req_last ( dma_wr_req_last ), + .dma_wr_req_ready ( dma_wr_req_ready ) +); + +ICMBuffer +#( + .ICM_CACHE_TYPE ( ICM_CACHE_TYPE ), + .ICM_PAGE_NUM ( ICM_PAGE_NUM ), + .ICM_PAGE_NUM_LOG ( ICM_PAGE_NUM_LOG ), + .ICM_ENTRY_NUM ( ICM_ENTRY_NUM ), + .ICM_ENTRY_NUM_LOG ( ICM_ENTRY_NUM_LOG ), + .ICM_SLOT_SIZE ( ICM_SLOT_SIZE ), + .ICM_ADDR_WIDTH ( ICM_ADDR_WIDTH ), + + .CACHE_ADDR_WIDTH ( CACHE_ADDR_WIDTH ), + .CACHE_ENTRY_WIDTH ( CACHE_ENTRY_WIDTH ), + .CACHE_SET_NUM ( CACHE_SET_NUM ), + .CACHE_SET_NUM_LOG ( CACHE_SET_NUM_LOG ), + .CACHE_OFFSET_WIDTH ( CACHE_OFFSET_WIDTH ), + .CACHE_TAG_WIDTH ( CACHE_TAG_WIDTH ), + .PHYSICAL_ADDR_WIDTH ( PHYSICAL_ADDR_WIDTH ), + .COUNT_MAX ( COUNT_MAX ), + .COUNT_MAX_LOG ( COUNT_MAX_LOG ), + .REQ_TAG_NUM ( REQ_TAG_NUM ), + .REQ_TAG_NUM_LOG ( REQ_TAG_NUM_LOG ) +) +ICMBuffer_Inst +( + .clk ( clk ), + .rst ( rst ), + + .get_req_valid ( cache_get_req_valid ), + .get_req_head ( cache_get_req_head ), + .get_req_ready ( cache_get_req_ready ), + + .get_rsp_valid ( cache_get_rsp_valid ), + .get_rsp_head ( cache_get_rsp_head ), + .get_rsp_data ( cache_get_rsp_data ), + .get_rsp_ready ( cache_get_rsp_ready ), + + .set_req_valid ( cache_set_req_valid ), + .set_req_head ( cache_set_req_head ), + .set_req_data ( cache_set_req_data ), + .set_req_ready ( cache_set_req_ready ), + + .del_req_valid ( cache_del_req_valid ), + .del_req_head ( cache_del_req_head ), + .del_req_ready ( cache_del_req_ready ) +); + +ICMMetaProc +#( + .ICM_CACHE_TYPE ( ICM_CACHE_TYPE ), + .ICM_PAGE_NUM ( ICM_PAGE_NUM ), + .ICM_ENTRY_NUM ( ICM_ENTRY_NUM ), + .ICM_SLOT_SIZE ( ICM_SLOT_SIZE ) +) +ICMMetaProc_Inst +( + .clk ( clk ), + .rst ( rst ), + + .icm_mapping_set_valid ( icm_mapping_set_valid ), + .icm_mapping_set_head ( icm_mapping_set_head ), + .icm_mapping_set_data ( icm_mapping_set_data ), + + .icm_mapping_lookup_valid ( icm_mapping_lookup_valid ), + .icm_mapping_lookup_head ( icm_mapping_lookup_head ), + + .icm_mapping_rsp_valid ( icm_mapping_rsp_valid ), + .icm_mapping_rsp_icm_addr ( icm_mapping_rsp_icm_addr ), + .icm_mapping_rsp_phy_addr ( icm_mapping_rsp_phy_addr ), + + .icm_base ( icm_base ) +); +/*------------------------------------------- Submodules Instatiation : End -----------------------------------------*/ + +/*------------------------------------------- State Machine Definition : Begin --------------------------------------*/ +/*------------------------------------------- State Machine Definition : End ----------------------------------------*/ + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ + +/*------------------------------------------- Local Macros Undef : Begin --------------------------------------------*/ +/*------------------------------------------- Local Macros Undef : End ----------------------------------------------*/ + +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/ICMMgt/ICMCache/ICMGetProc/ICMGetProc.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/ICMMgt/ICMCache/ICMGetProc/ICMGetProc.v new file mode 100644 index 0000000000000000000000000000000000000000..72195045dbe2e4c6c0a7885d2046f08c1a24c7bb --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/ICMMgt/ICMCache/ICMGetProc/ICMGetProc.v @@ -0,0 +1,412 @@ +/*------------------------------------------- Module Description : Begin ---------------------------------------------- +Name: ICMGetProc +Author: YangFan +Function: Handle ICM Get Request. When ICM Cache Miss happens, DMA cache entry from host memory and update cache. +--------------------------------------------- Module Decription : End -----------------------------------------------*/ + +/*------------------------------------------- Timescale Definition : Begin ------------------------------------------*/ +`timescale 1ns / 1ps +/*------------------------------------------- Timescale Definition : End --------------------------------------------*/ + +/*------------------------------------------- Included Files : Begin ------------------------------------------------*/ +`include "protocol_engine_def.vh" +/*------------------------------------------- Included Files : End --------------------------------------------------*/ + +/*------------------------------------------- Input/Output Definition : Begin ---------------------------------------*/ +module ICMGetProc +#( + parameter ICM_CACHE_TYPE = `CACHE_TYPE_MTT, + parameter ICM_PAGE_NUM = `ICM_PAGE_NUM_MTT, + parameter ICM_PAGE_NUM_LOG = log2b(ICM_PAGE_NUM - 1), + parameter ICM_ENTRY_NUM = `ICM_ENTRY_NUM_MTT, + parameter ICM_ENTRY_NUM_LOG = log2b(ICM_ENTRY_NUM - 1), + parameter ICM_SLOT_SIZE = `ICM_SLOT_SIZE_MTT, + parameter ICM_ADDR_WIDTH = 64, + + parameter CACHE_ADDR_WIDTH = log2b(ICM_ENTRY_NUM * ICM_SLOT_SIZE - 1), + parameter CACHE_ENTRY_WIDTH = 256, + parameter CACHE_SET_NUM = 1024, + parameter CACHE_SET_NUM_LOG = log2b(CACHE_SET_NUM - 1), + parameter CACHE_OFFSET_WIDTH = log2b(ICM_SLOT_SIZE - 1), + parameter CACHE_TAG_WIDTH = CACHE_ADDR_WIDTH - CACHE_OFFSET_WIDTH - CACHE_SET_NUM_LOG, + parameter PHYSICAL_ADDR_WIDTH = `PHY_SPACE_ADDR_WIDTH, + parameter COUNT_MAX = 2, + parameter COUNT_MAX_LOG = log2b(COUNT_MAX - 1) + 1, + parameter REQ_TAG_NUM = 32, + parameter REQ_TAG_NUM_LOG = log2b(REQ_TAG_NUM - 1), + parameter REORDER_BUFFER_WIDTH = (ICM_CACHE_TYPE == `CACHE_TYPE_MTT) ? CACHE_ENTRY_WIDTH * 2 + COUNT_MAX_LOG : CACHE_ENTRY_WIDTH + COUNT_MAX_LOG +) +( + input wire clk, + input wire rst, + +//ICM Get Req Interface + input wire icm_get_req_valid, + input wire [COUNT_MAX_LOG * 2 + `MAX_REQ_TAG_NUM_LOG + PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH - 1 : 0] icm_get_req_head, + output wire icm_get_req_ready, + +//ICM Get Resp Interface + output wire icm_get_rsp_valid, + output wire [COUNT_MAX_LOG * 2 + `MAX_REQ_TAG_NUM_LOG + PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH - 1 : 0] icm_get_rsp_head, + output wire [CACHE_ENTRY_WIDTH - 1 : 0] icm_get_rsp_data, + input wire icm_get_rsp_ready, + +//Cache Get Req Interface + output wire cache_get_req_valid, + output wire [COUNT_MAX_LOG * 2 + `MAX_REQ_TAG_NUM_LOG + PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH - 1 : 0] cache_get_req_head, + input wire cache_get_req_ready, + +//Cache Get Resp Interface + input wire cache_get_rsp_valid, + input wire [COUNT_MAX_LOG * 2 + `MAX_REQ_TAG_NUM_LOG + PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH + 1 - 1 : 0] cache_get_rsp_head, + input wire [CACHE_ENTRY_WIDTH - 1 : 0] cache_get_rsp_data, + output wire cache_get_rsp_ready, + +//Cache Set Req Interface + output wire cache_set_req_valid, + output wire [ICM_ADDR_WIDTH - 1 : 0] cache_set_req_head, + output wire [CACHE_ENTRY_WIDTH - 1 : 0] cache_set_req_data, + input wire cache_set_req_ready, + +//DMA Read Req Interface + output wire dma_rd_req_valid, + output wire [`DMA_HEAD_WIDTH - 1 : 0] dma_rd_req_head, + output wire [`DMA_DATA_WIDTH - 1 : 0] dma_rd_req_data, + output wire dma_rd_req_last, + input wire dma_rd_req_ready, + +//DMA Read Rsp Interface + input wire dma_rd_rsp_valid, + input wire [`DMA_HEAD_WIDTH - 1 : 0] dma_rd_rsp_head, + input wire [`DMA_DATA_WIDTH - 1 : 0] dma_rd_rsp_data, + input wire dma_rd_rsp_last, + output wire dma_rd_rsp_ready +); +/*------------------------------------------- Input/Output Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Macros Definition : Begin ---------------------------------------*/ + +/*------------------------------------------- Local Macros Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Variables Definition : Begin ------------------------------------*/ +wire req_fifo_wr_en; +wire [COUNT_MAX_LOG * 2 + `MAX_REQ_TAG_NUM_LOG + PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH - 1 : 0] req_fifo_din; +wire req_fifo_prog_full; + +wire req_fifo_rd_en; +wire [COUNT_MAX_LOG * 2 + `MAX_REQ_TAG_NUM_LOG + PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH - 1 : 0] req_fifo_dout ; +wire req_fifo_empty; + +wire reorder_buffer_wea; +wire [`MAX_REQ_TAG_NUM_LOG - 1 : 0] reorder_buffer_addra; +wire [REORDER_BUFFER_WIDTH - 1 : 0] reorder_buffer_dina; +wire [REORDER_BUFFER_WIDTH - 1 : 0] reorder_buffer_douta; + +wire reorder_buffer_web; +wire [`MAX_REQ_TAG_NUM_LOG - 1 : 0] reorder_buffer_addrb; +wire [REORDER_BUFFER_WIDTH - 1 : 0] reorder_buffer_dinb; +wire [REORDER_BUFFER_WIDTH - 1 : 0] reorder_buffer_doutb; + +wire req_hit_wr_en; +wire [COUNT_MAX_LOG * 2 + `MAX_REQ_TAG_NUM_LOG + PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH - 1 : 0] req_hit_din; +wire req_hit_prog_full; + +wire req_hit_rd_en; +wire [COUNT_MAX_LOG * 2 + `MAX_REQ_TAG_NUM_LOG + PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH - 1 : 0] req_hit_dout ; +wire req_hit_empty; + +wire req_miss_wr_en; +wire [COUNT_MAX_LOG * 2 + `MAX_REQ_TAG_NUM_LOG + PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH - 1 : 0] req_miss_din; +wire req_miss_prog_full; + +wire req_miss_rd_en; +wire [COUNT_MAX_LOG * 2 + `MAX_REQ_TAG_NUM_LOG + PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH - 1 : 0] req_miss_dout ; +wire req_miss_empty; + +wire icm_entry_rsp_valid; +wire [CACHE_ENTRY_WIDTH - 1 : 0] icm_entry_rsp_data ; +wire icm_entry_rsp_ready; +/*------------------------------------------- Local Variables Definition : End --------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : Begin ---------------------------------------*/ +SyncFIFO_Template #( + .FIFO_WIDTH ( COUNT_MAX_LOG * 2 + `MAX_REQ_TAG_NUM_LOG + PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH ), + .FIFO_DEPTH ( 32 ) +) +ReqFIFO_Inst +( + .clk ( clk ), + .rst ( rst ), + .wr_en ( req_fifo_wr_en ), + .din ( req_fifo_din ), + .prog_full ( req_fifo_prog_full ), + .rd_en ( req_fifo_rd_en ), + .dout ( req_fifo_dout ), + .empty ( req_fifo_empty ), + .data_count ( ) +); + +SyncFIFO_Template #( + .FIFO_WIDTH ( COUNT_MAX_LOG * 2 + `MAX_REQ_TAG_NUM_LOG + PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH ), + .FIFO_DEPTH ( 32 ) +) +ReqHitFIFO_Inst +( + .clk ( clk ), + .rst ( rst ), + .wr_en ( req_hit_wr_en ), + .din ( req_hit_din ), + .prog_full ( req_hit_prog_full ), + .rd_en ( req_hit_rd_en ), + .dout ( req_hit_dout ), + .empty ( req_hit_empty ), + .data_count ( ) +); + +SyncFIFO_Template #( + .FIFO_WIDTH ( COUNT_MAX_LOG * 2 + `MAX_REQ_TAG_NUM_LOG + PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH ), + .FIFO_DEPTH ( 32 ) +) +ReqMissFIFO_Inst +( + .clk ( clk ), + .rst ( rst ), + .wr_en ( req_miss_wr_en ), + .din ( req_miss_din ), + .prog_full ( req_miss_prog_full ), + .rd_en ( req_miss_rd_en ), + .dout ( req_miss_dout ), + .empty ( req_miss_empty ), + .data_count ( ) +); + +SRAM_TDP_Template #( + .RAM_WIDTH ( REORDER_BUFFER_WIDTH ), + .RAM_DEPTH ( 256 ) +) +ReorderBuffer +( + .clk ( clk ), + .rst ( rst ), + + .wea ( reorder_buffer_wea ), + .addra ( reorder_buffer_addra ), + .dina ( reorder_buffer_dina ), + .douta ( reorder_buffer_douta ), + + .web ( reorder_buffer_web ), + .addrb ( reorder_buffer_addrb ), + .dinb ( reorder_buffer_dinb ), + .doutb ( reorder_buffer_doutb ) +); + +ICMGetProc_Thread_1 +#( + .ICM_CACHE_TYPE ( ICM_CACHE_TYPE ), + .ICM_SLOT_SIZE ( ICM_SLOT_SIZE ), + + .CACHE_ADDR_WIDTH ( CACHE_ADDR_WIDTH ), + .CACHE_ENTRY_WIDTH ( CACHE_ENTRY_WIDTH ), + .CACHE_SET_NUM ( CACHE_SET_NUM ), + .CACHE_SET_NUM_LOG ( CACHE_SET_NUM_LOG ), + .CACHE_OFFSET_WIDTH ( CACHE_OFFSET_WIDTH ), + .CACHE_TAG_WIDTH ( CACHE_TAG_WIDTH ), + .PHYSICAL_ADDR_WIDTH ( PHYSICAL_ADDR_WIDTH ), + .COUNT_MAX ( COUNT_MAX ), + .COUNT_MAX_LOG ( COUNT_MAX_LOG ), + .REQ_TAG_NUM ( REQ_TAG_NUM ), + .REQ_TAG_NUM_LOG ( REQ_TAG_NUM_LOG ), + .REORDER_BUFFER_WIDTH ( REORDER_BUFFER_WIDTH ) +) +ICMGetProc_Thread_1_Inst +( + .clk ( clk ), + .rst ( rst ), + + .icm_get_req_valid ( icm_get_req_valid ), + .icm_get_req_head ( icm_get_req_head ), + .icm_get_req_ready ( icm_get_req_ready ), + + .req_fifo_wr_en ( req_fifo_wr_en ), + .req_fifo_din ( req_fifo_din ), + .req_fifo_prog_full ( req_fifo_prog_full ) +); + +ICMGetProc_Thread_2 +#( + .ICM_CACHE_TYPE ( ICM_CACHE_TYPE ), + .ICM_SLOT_SIZE ( ICM_SLOT_SIZE ), + + .CACHE_ADDR_WIDTH ( CACHE_ADDR_WIDTH ), + .CACHE_ENTRY_WIDTH ( CACHE_ENTRY_WIDTH ), + .CACHE_SET_NUM ( CACHE_SET_NUM ), + .CACHE_SET_NUM_LOG ( CACHE_SET_NUM_LOG ), + .CACHE_OFFSET_WIDTH ( CACHE_OFFSET_WIDTH ), + .CACHE_TAG_WIDTH ( CACHE_TAG_WIDTH ), + .PHYSICAL_ADDR_WIDTH ( PHYSICAL_ADDR_WIDTH ), + .COUNT_MAX ( COUNT_MAX ), + .COUNT_MAX_LOG ( COUNT_MAX_LOG ), + .REQ_TAG_NUM ( REQ_TAG_NUM ), + .REQ_TAG_NUM_LOG ( REQ_TAG_NUM_LOG ), + .REORDER_BUFFER_WIDTH ( REORDER_BUFFER_WIDTH ) +) +ICMGetProc_Thread_2_Inst +( + .clk ( clk ), + .rst ( rst ), + + .req_fifo_rd_en ( req_fifo_rd_en ), + .req_fifo_dout ( req_fifo_dout ), + .req_fifo_empty ( req_fifo_empty ), + + .cache_get_req_valid ( cache_get_req_valid ), + .cache_get_req_head ( cache_get_req_head ), + .cache_get_req_ready ( cache_get_req_ready ) +); + +ICMGetProc_Thread_3 +#( + .ICM_CACHE_TYPE ( ICM_CACHE_TYPE ), + .ICM_SLOT_SIZE ( ICM_SLOT_SIZE ), + + .CACHE_ADDR_WIDTH ( CACHE_ADDR_WIDTH ), + .CACHE_ENTRY_WIDTH ( CACHE_ENTRY_WIDTH ), + .CACHE_SET_NUM ( CACHE_SET_NUM ), + .CACHE_SET_NUM_LOG ( CACHE_SET_NUM_LOG ), + .CACHE_OFFSET_WIDTH ( CACHE_OFFSET_WIDTH ), + .CACHE_TAG_WIDTH ( CACHE_TAG_WIDTH ), + .PHYSICAL_ADDR_WIDTH ( PHYSICAL_ADDR_WIDTH ), + .COUNT_MAX ( COUNT_MAX ), + .COUNT_MAX_LOG ( COUNT_MAX_LOG ), + .REQ_TAG_NUM ( REQ_TAG_NUM ), + .REQ_TAG_NUM_LOG ( REQ_TAG_NUM_LOG ), + .REORDER_BUFFER_WIDTH ( REORDER_BUFFER_WIDTH ) +) +ICMGetProc_Thread_3_Inst +( + .clk ( clk ), + .rst ( rst ), + + .get_rsp_valid ( cache_get_rsp_valid ), + .get_rsp_head ( cache_get_rsp_head ), + .get_rsp_data ( cache_get_rsp_data ), + .get_rsp_ready ( cache_get_rsp_ready ), + + .reorder_buffer_wen ( reorder_buffer_wea ), + .reorder_buffer_addr ( reorder_buffer_addra ), + .reorder_buffer_din ( reorder_buffer_dina ), + .reorder_buffer_dout ( reorder_buffer_douta ), + + .dma_rd_req_valid ( dma_rd_req_valid ), + .dma_rd_req_head ( dma_rd_req_head ), + .dma_rd_req_data ( dma_rd_req_data ), + .dma_rd_req_last ( dma_rd_req_last ), + .dma_rd_req_ready ( dma_rd_req_ready ), + + .req_hit_wr_en ( req_hit_wr_en ), + .req_hit_din ( req_hit_din ), + .req_hit_prog_full ( req_hit_prog_full ), + + .req_miss_wr_en ( req_miss_wr_en ), + .req_miss_din ( req_miss_din ), + .req_miss_prog_full ( req_miss_prog_full ) +); + +ICMGetProc_Thread_4 +#( + .ICM_CACHE_TYPE ( ICM_CACHE_TYPE ), + .ICM_SLOT_SIZE ( ICM_SLOT_SIZE ), + + .CACHE_ADDR_WIDTH ( CACHE_ADDR_WIDTH ), + .CACHE_ENTRY_WIDTH ( CACHE_ENTRY_WIDTH ), + .CACHE_SET_NUM ( CACHE_SET_NUM ), + .CACHE_SET_NUM_LOG ( CACHE_SET_NUM_LOG ), + .CACHE_OFFSET_WIDTH ( CACHE_OFFSET_WIDTH ), + .CACHE_TAG_WIDTH ( CACHE_TAG_WIDTH ), + .PHYSICAL_ADDR_WIDTH ( PHYSICAL_ADDR_WIDTH ), + .COUNT_MAX ( COUNT_MAX ), + .COUNT_MAX_LOG ( COUNT_MAX_LOG ), + .REQ_TAG_NUM ( REQ_TAG_NUM ), + .REQ_TAG_NUM_LOG ( REQ_TAG_NUM_LOG ), + .REORDER_BUFFER_WIDTH ( REORDER_BUFFER_WIDTH ) +) +ICMGetProc_Thread_4_Inst +( + .clk ( clk ), + .rst ( rst ), + + .req_hit_rd_en ( req_hit_rd_en ), + .req_hit_dout ( req_hit_dout ), + .req_hit_empty ( req_hit_empty ), + + .req_miss_rd_en ( req_miss_rd_en ), + .req_miss_dout ( req_miss_dout ), + .req_miss_empty ( req_miss_empty ), + + .reorder_buffer_wen ( reorder_buffer_web ), + .reorder_buffer_addr ( reorder_buffer_addrb ), + .reorder_buffer_din ( reorder_buffer_dinb ), + .reorder_buffer_dout ( reorder_buffer_doutb ), + + .icm_entry_rsp_valid ( icm_entry_rsp_valid ), + .icm_entry_rsp_data ( icm_entry_rsp_data ), + .icm_entry_rsp_ready ( icm_entry_rsp_ready ), + + .cache_set_req_valid ( cache_set_req_valid ), + .cache_set_req_head ( cache_set_req_head ), + .cache_set_req_data ( cache_set_req_data ), + .cache_set_req_ready ( cache_set_req_ready ), + + .icm_get_rsp_valid ( icm_get_rsp_valid ), + .icm_get_rsp_head ( icm_get_rsp_head ), + .icm_get_rsp_data ( icm_get_rsp_data ), + .icm_get_rsp_ready ( icm_get_rsp_ready ) +); + +ICMGetProc_Thread_5 +#( + .ICM_CACHE_TYPE ( ICM_CACHE_TYPE ), + .ICM_SLOT_SIZE ( ICM_SLOT_SIZE ), + + .CACHE_ADDR_WIDTH ( CACHE_ADDR_WIDTH ), + .CACHE_ENTRY_WIDTH ( CACHE_ENTRY_WIDTH ), + .CACHE_SET_NUM ( CACHE_SET_NUM ), + .CACHE_SET_NUM_LOG ( CACHE_SET_NUM_LOG ), + .CACHE_OFFSET_WIDTH ( CACHE_OFFSET_WIDTH ), + .CACHE_TAG_WIDTH ( CACHE_TAG_WIDTH ), + .PHYSICAL_ADDR_WIDTH ( PHYSICAL_ADDR_WIDTH ), + .COUNT_MAX ( COUNT_MAX ), + .COUNT_MAX_LOG ( COUNT_MAX_LOG ), + .REQ_TAG_NUM ( REQ_TAG_NUM ), + .REQ_TAG_NUM_LOG ( REQ_TAG_NUM_LOG ), + .REORDER_BUFFER_WIDTH ( REORDER_BUFFER_WIDTH ) +) +ICMGetProc_Thread_5_Inst +( + .clk ( clk ), + .rst ( rst ), + + .dma_rd_rsp_valid ( dma_rd_rsp_valid ), + .dma_rd_rsp_head ( dma_rd_rsp_head ), + .dma_rd_rsp_data ( dma_rd_rsp_data ), + .dma_rd_rsp_last ( dma_rd_rsp_last ), + .dma_rd_rsp_ready ( dma_rd_rsp_ready ), + + .icm_entry_rsp_valid ( icm_entry_rsp_valid ), + .icm_entry_rsp_data ( icm_entry_rsp_data ), + .icm_entry_rsp_ready ( icm_entry_rsp_ready ) +); + +/*------------------------------------------- Submodules Instatiation : End -----------------------------------------*/ + +/*------------------------------------------- State Machine Definition : Begin --------------------------------------*/ +/*------------------------------------------- State Machine Definition : End ----------------------------------------*/ + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ + +/*------------------------------------------- Local Macros Undef : Begin --------------------------------------------*/ +/*------------------------------------------- Local Macros Undef : End ----------------------------------------------*/ + +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/ICMMgt/ICMCache/ICMGetProc/ICMGetProc_Thread_1.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/ICMMgt/ICMCache/ICMGetProc/ICMGetProc_Thread_1.v new file mode 100644 index 0000000000000000000000000000000000000000..1c2ebfcb98308cde9fa1c883c183bf09213418b9 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/ICMMgt/ICMCache/ICMGetProc/ICMGetProc_Thread_1.v @@ -0,0 +1,79 @@ +/*------------------------------------------- Module Description : Begin ---------------------------------------------- +Name: ICMGetProc_Thread_1 +Author: YangFan +Function: Buffer ICMGet Request. +--------------------------------------------- Module Decription : End -----------------------------------------------*/ + +/*------------------------------------------- Timescale Definition : Begin ------------------------------------------*/ +`timescale 1ns / 1ps +/*------------------------------------------- Timescale Definition : End --------------------------------------------*/ + +/*------------------------------------------- Included Files : Begin ------------------------------------------------*/ +`include "protocol_engine_def.vh" +/*------------------------------------------- Included Files : End --------------------------------------------------*/ + +/*------------------------------------------- Input/Output Definition : Begin ---------------------------------------*/ +module ICMGetProc_Thread_1 +#( + parameter ICM_CACHE_TYPE = `CACHE_TYPE_MTT, + parameter ICM_PAGE_NUM = `ICM_PAGE_NUM_MTT, + parameter ICM_PAGE_NUM_LOG = log2b(ICM_PAGE_NUM - 1), + parameter ICM_ENTRY_NUM = `ICM_ENTRY_NUM_MTT, + parameter ICM_ENTRY_NUM_LOG = log2b(ICM_ENTRY_NUM - 1), + parameter ICM_SLOT_SIZE = `ICM_SLOT_SIZE_MTT, + parameter ICM_ADDR_WIDTH = 64, + + parameter CACHE_ADDR_WIDTH = log2b(ICM_ENTRY_NUM * ICM_SLOT_SIZE - 1), + parameter CACHE_ENTRY_WIDTH = 256, + parameter CACHE_SET_NUM = 1024, + parameter CACHE_SET_NUM_LOG = log2b(CACHE_SET_NUM - 1), + parameter CACHE_OFFSET_WIDTH = log2b(ICM_SLOT_SIZE - 1), + parameter CACHE_TAG_WIDTH = CACHE_ADDR_WIDTH - CACHE_OFFSET_WIDTH - CACHE_SET_NUM_LOG, + parameter PHYSICAL_ADDR_WIDTH = `PHY_SPACE_ADDR_WIDTH, + parameter COUNT_MAX = 2, + parameter COUNT_MAX_LOG = log2b(COUNT_MAX - 1) + 1, + parameter REQ_TAG_NUM = 32, + parameter REQ_TAG_NUM_LOG = log2b(REQ_TAG_NUM - 1), + parameter REORDER_BUFFER_WIDTH = (ICM_CACHE_TYPE == `CACHE_TYPE_MTT) ? CACHE_ENTRY_WIDTH * 2 + COUNT_MAX_LOG : CACHE_ENTRY_WIDTH + COUNT_MAX_LOG +) +( + input wire clk, + input wire rst, + +//ICM Get Req Interface + input wire icm_get_req_valid, + input wire [COUNT_MAX_LOG * 2 + `MAX_REQ_TAG_NUM_LOG + PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH - 1 : 0] icm_get_req_head, + output wire icm_get_req_ready, + +//ReqFIFO Interface + output wire req_fifo_wr_en, + output wire [COUNT_MAX_LOG * 2 + `MAX_REQ_TAG_NUM_LOG + PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH - 1 : 0] req_fifo_din, + input wire req_fifo_prog_full +); +/*------------------------------------------- Input/Output Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Macros Definition : Begin ---------------------------------------*/ +/*------------------------------------------- Local Macros Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Variables Definition : Begin ------------------------------------*/ + + +/*------------------------------------------- Local Variables Definition : End --------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : Begin ---------------------------------------*/ +/*------------------------------------------- Submodules Instatiation : End -----------------------------------------*/ + +/*------------------------------------------- State Machine Definition : Begin --------------------------------------*/ +/*------------------------------------------- State Machine Definition : End ----------------------------------------*/ + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ +assign req_fifo_wr_en = (icm_get_req_valid && !req_fifo_prog_full) ? 'd1 : 'd0; +assign req_fifo_din = (icm_get_req_valid && !req_fifo_prog_full) ? icm_get_req_head : 'd0; +assign icm_get_req_ready = !req_fifo_prog_full; + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ + +/*------------------------------------------- Local Macros Undef : Begin --------------------------------------------*/ +/*------------------------------------------- Local Macros Undef : End ----------------------------------------------*/ + +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/ICMMgt/ICMCache/ICMGetProc/ICMGetProc_Thread_2.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/ICMMgt/ICMCache/ICMGetProc/ICMGetProc_Thread_2.v new file mode 100644 index 0000000000000000000000000000000000000000..9dd0cf7eeb80086309894ed4c28de7c5c9bf6802 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/ICMMgt/ICMCache/ICMGetProc/ICMGetProc_Thread_2.v @@ -0,0 +1,79 @@ +/*------------------------------------------- Module Description : Begin ---------------------------------------------- +Name: ICMGetProc_Thread_2 +Author: YangFan +Function: Issue ICM Cache Get Reqeuest. +--------------------------------------------- Module Decription : End -----------------------------------------------*/ + +/*------------------------------------------- Timescale Definition : Begin ------------------------------------------*/ +`timescale 1ns / 1ps +/*------------------------------------------- Timescale Definition : End --------------------------------------------*/ + +/*------------------------------------------- Included Files : Begin ------------------------------------------------*/ +`include "protocol_engine_def.vh" +/*------------------------------------------- Included Files : End --------------------------------------------------*/ + +/*------------------------------------------- Input/Output Definition : Begin ---------------------------------------*/ +module ICMGetProc_Thread_2 +#( + parameter ICM_CACHE_TYPE = `CACHE_TYPE_MTT, + parameter ICM_PAGE_NUM = `ICM_PAGE_NUM_MTT, + parameter ICM_PAGE_NUM_LOG = log2b(ICM_PAGE_NUM - 1), + parameter ICM_ENTRY_NUM = `ICM_ENTRY_NUM_MTT, + parameter ICM_ENTRY_NUM_LOG = log2b(ICM_ENTRY_NUM - 1), + parameter ICM_SLOT_SIZE = `ICM_SLOT_SIZE_MTT, + parameter ICM_ADDR_WIDTH = 64, + + parameter CACHE_ADDR_WIDTH = log2b(ICM_ENTRY_NUM * ICM_SLOT_SIZE - 1), + parameter CACHE_ENTRY_WIDTH = 256, + parameter CACHE_SET_NUM = 1024, + parameter CACHE_SET_NUM_LOG = log2b(CACHE_SET_NUM - 1), + parameter CACHE_OFFSET_WIDTH = log2b(ICM_SLOT_SIZE - 1), + parameter CACHE_TAG_WIDTH = CACHE_ADDR_WIDTH - CACHE_OFFSET_WIDTH - CACHE_SET_NUM_LOG, + parameter PHYSICAL_ADDR_WIDTH = `PHY_SPACE_ADDR_WIDTH, + parameter COUNT_MAX = 2, + parameter COUNT_MAX_LOG = log2b(COUNT_MAX - 1) + 1, + parameter REQ_TAG_NUM = 32, + parameter REQ_TAG_NUM_LOG = log2b(REQ_TAG_NUM - 1), + parameter REORDER_BUFFER_WIDTH = (ICM_CACHE_TYPE == `CACHE_TYPE_MTT) ? CACHE_ENTRY_WIDTH * 2 + COUNT_MAX_LOG : CACHE_ENTRY_WIDTH + COUNT_MAX_LOG +) +( + input wire clk, + input wire rst, + +//ReqFIFO Interface + output wire req_fifo_rd_en, + input wire [COUNT_MAX_LOG * 2 + `MAX_REQ_TAG_NUM_LOG + PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH - 1 : 0] req_fifo_dout, + input wire req_fifo_empty, + +//Cache Get Req Interface + output wire cache_get_req_valid, + output wire [COUNT_MAX_LOG * 2 + `MAX_REQ_TAG_NUM_LOG + PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH - 1 : 0] cache_get_req_head, + input wire cache_get_req_ready +); +/*------------------------------------------- Input/Output Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Macros Definition : Begin ---------------------------------------*/ +/*------------------------------------------- Local Macros Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Variables Definition : Begin ------------------------------------*/ + + +/*------------------------------------------- Local Variables Definition : End --------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : Begin ---------------------------------------*/ +/*------------------------------------------- Submodules Instatiation : End -----------------------------------------*/ + +/*------------------------------------------- State Machine Definition : Begin --------------------------------------*/ +/*------------------------------------------- State Machine Definition : End ----------------------------------------*/ + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ +assign cache_get_req_valid = ~req_fifo_empty ? 'd1 : 'd0; +assign cache_get_req_head = ~req_fifo_empty ? req_fifo_dout : 'd0; +assign req_fifo_rd_en = cache_get_req_valid && cache_get_req_ready; + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ + +/*------------------------------------------- Local Macros Undef : Begin --------------------------------------------*/ +/*------------------------------------------- Local Macros Undef : End ----------------------------------------------*/ + +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/ICMMgt/ICMCache/ICMGetProc/ICMGetProc_Thread_3.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/ICMMgt/ICMCache/ICMGetProc/ICMGetProc_Thread_3.v new file mode 100644 index 0000000000000000000000000000000000000000..09ec4fbcb9ee2230309636ed9a5caf005168a696 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/ICMMgt/ICMCache/ICMGetProc/ICMGetProc_Thread_3.v @@ -0,0 +1,304 @@ +/*------------------------------------------- Module Description : Begin ---------------------------------------------- +Name: ICMGetProc_Thread_3 +Author: YangFan +Function: Deal with ICMBuffer response. +--------------------------------------------- Module Decription : End -----------------------------------------------*/ + +/*------------------------------------------- Timescale Definition : Begin ------------------------------------------*/ +`timescale 1ns / 1ps +/*------------------------------------------- Timescale Definition : End --------------------------------------------*/ + +/*------------------------------------------- Included Files : Begin ------------------------------------------------*/ +`include "protocol_engine_def.vh" +/*------------------------------------------- Included Files : End --------------------------------------------------*/ + +/*------------------------------------------- Input/Output Definition : Begin ---------------------------------------*/ +module ICMGetProc_Thread_3 +#( + parameter ICM_CACHE_TYPE = `CACHE_TYPE_MTT, + parameter ICM_PAGE_NUM = `ICM_PAGE_NUM_MTT, + parameter ICM_PAGE_NUM_LOG = log2b(ICM_PAGE_NUM - 1), + parameter ICM_ENTRY_NUM = `ICM_ENTRY_NUM_MTT, + parameter ICM_ENTRY_NUM_LOG = log2b(ICM_ENTRY_NUM - 1), + parameter ICM_SLOT_SIZE = `ICM_SLOT_SIZE_MTT, + parameter ICM_ADDR_WIDTH = 64, + + parameter CACHE_ADDR_WIDTH = log2b(ICM_ENTRY_NUM * ICM_SLOT_SIZE - 1), + parameter CACHE_ENTRY_WIDTH = 256, + parameter CACHE_SET_NUM = 1024, + parameter CACHE_SET_NUM_LOG = log2b(CACHE_SET_NUM - 1), + parameter CACHE_OFFSET_WIDTH = log2b(ICM_SLOT_SIZE - 1), + parameter CACHE_TAG_WIDTH = CACHE_ADDR_WIDTH - CACHE_OFFSET_WIDTH - CACHE_SET_NUM_LOG, + parameter PHYSICAL_ADDR_WIDTH = `PHY_SPACE_ADDR_WIDTH, + parameter COUNT_MAX = 2, + parameter COUNT_MAX_LOG = log2b(COUNT_MAX - 1) + 1, + parameter REQ_TAG_NUM = 32, + parameter REQ_TAG_NUM_LOG = log2b(REQ_TAG_NUM - 1), + parameter REORDER_BUFFER_WIDTH = (ICM_CACHE_TYPE == `CACHE_TYPE_MTT) ? CACHE_ENTRY_WIDTH * 2 + COUNT_MAX_LOG : CACHE_ENTRY_WIDTH + COUNT_MAX_LOG +) +( + input wire clk, + input wire rst, + +//ICMBuffer Get Response Interface + input wire get_rsp_valid, + input wire [COUNT_MAX_LOG * 2 + `MAX_REQ_TAG_NUM_LOG + PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH + 1 - 1 : 0] get_rsp_head, + input wire [CACHE_ENTRY_WIDTH - 1 : 0] get_rsp_data, + output wire get_rsp_ready, + +//ReorderBuffer Interface + output reg reorder_buffer_wen, + output reg [`MAX_REQ_TAG_NUM_LOG - 1 : 0] reorder_buffer_addr, + output reg [REORDER_BUFFER_WIDTH - 1 : 0] reorder_buffer_din, + input wire [REORDER_BUFFER_WIDTH - 1 : 0] reorder_buffer_dout, + +//DMA Read Req Interface + output wire dma_rd_req_valid, + output wire [`DMA_HEAD_WIDTH - 1 : 0] dma_rd_req_head, + output wire [`DMA_DATA_WIDTH - 1 : 0] dma_rd_req_data, + output wire dma_rd_req_last, + input wire dma_rd_req_ready, + +//ReqHitFIFO Interface + output wire req_hit_wr_en, + output wire [COUNT_MAX_LOG * 2 + `MAX_REQ_TAG_NUM_LOG + PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH - 1 : 0] req_hit_din, + input wire req_hit_prog_full, + +//ReqMissFIFO Interface + output wire req_miss_wr_en, + output wire [COUNT_MAX_LOG * 2 + `MAX_REQ_TAG_NUM_LOG + PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH - 1 : 0] req_miss_din, + input wire req_miss_prog_full +); +/*------------------------------------------- Input/Output Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Macros Definition : Begin ---------------------------------------*/ +/*------------------------------------------- Local Macros Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Variables Definition : Begin ------------------------------------*/ +wire cache_hit; +wire cache_miss; +wire [`MAX_REQ_TAG_NUM_LOG - 1 : 0] req_tag; +wire [31:0] dma_len; +wire [PHYSICAL_ADDR_WIDTH - 1 : 0] dma_addr; +wire [COUNT_MAX_LOG - 1 : 0] count_max; +wire [COUNT_MAX_LOG - 1 : 0] count_index; +wire [COUNT_MAX_LOG - 1 : 0] count_collected; + +reg [COUNT_MAX_LOG * 2 + `MAX_REQ_TAG_NUM_LOG + PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH + 1 - 1 : 0] get_rsp_head_diff; +reg [CACHE_ENTRY_WIDTH - 1 : 0] get_rsp_data_diff; +/*------------------------------------------- Local Variables Definition : End --------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : Begin ---------------------------------------*/ +/*------------------------------------------- Submodules Instatiation : End -----------------------------------------*/ + +/*------------------------------------------- State Machine Definition : Begin --------------------------------------*/ +reg [2:0] cur_state; +reg [2:0] next_state; + +parameter [2:0] IDLE_s = 3'd1, + HIT_s = 3'd2, + MISS_s = 3'd3, + DMA_s = 3'd4; + + +always @(posedge clk or posedge rst) begin + if(rst) begin + cur_state <= IDLE_s; + end + else begin + cur_state <= next_state; + end +end + +always @(*) begin + case(cur_state) + IDLE_s: if(get_rsp_valid && cache_hit) begin + next_state = HIT_s; + end + else if(get_rsp_valid && cache_miss) begin + next_state = MISS_s; + end + else begin + next_state = IDLE_s; + end + HIT_s: if(!req_hit_prog_full) begin + next_state = IDLE_s; + end + else begin + next_state = HIT_s; + end + MISS_s: if(!req_miss_prog_full) begin + next_state = DMA_s; + end + else begin + next_state = MISS_s; + end + DMA_s: if(dma_rd_req_valid && dma_rd_req_ready) begin + next_state = IDLE_s; + end + else begin + next_state = DMA_s; + end + default: next_state = IDLE_s; + endcase +end + +/*------------------------------------------- State Machine Definition : End ----------------------------------------*/ + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ +//-- cache_hit -- +assign cache_hit = (cur_state == IDLE_s && get_rsp_valid) ? get_rsp_head[COUNT_MAX_LOG * 2 + `MAX_REQ_TAG_NUM_LOG + PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH] == 1'b1 : + (cur_state != IDLE_s) ? get_rsp_head_diff[COUNT_MAX_LOG * 2 + `MAX_REQ_TAG_NUM_LOG + PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH] == 1'b1 : 'd0; + +//-- cache_miss -- +assign cache_miss = (cur_state == IDLE_s && get_rsp_valid) ? get_rsp_head[COUNT_MAX_LOG * 2 + `MAX_REQ_TAG_NUM_LOG + PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH] == 1'b0 : + (cur_state != IDLE_s) ? get_rsp_head_diff[COUNT_MAX_LOG * 2 + `MAX_REQ_TAG_NUM_LOG + PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH] == 1'b0 : 'd0; + +//-- dma_addr -- +assign dma_addr = (cur_state == DMA_s) ? get_rsp_head_diff[PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH - 1 : ICM_ADDR_WIDTH] : 'd0; + +//-- dma_len -- +assign dma_len = (cur_state == DMA_s) ? CACHE_ENTRY_WIDTH / 8 : 'd0; + +//-- req_tag -- +assign req_tag = (cur_state == IDLE_s && get_rsp_valid) ? get_rsp_head[`MAX_REQ_TAG_NUM_LOG + PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH - 1 : PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH] : + (cur_state != IDLE_s) ? get_rsp_head_diff[`MAX_REQ_TAG_NUM_LOG + PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH - 1 : PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH] : 'd0; + +//-- count_max -- +//-- count_index -- +//-- count_collected -- +assign count_index = (cur_state == IDLE_s && get_rsp_valid) ? get_rsp_head[COUNT_MAX_LOG + `MAX_REQ_TAG_NUM_LOG + PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH - 1 : `MAX_REQ_TAG_NUM_LOG + PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH] : + (cur_state != IDLE_s) ? get_rsp_head_diff[COUNT_MAX_LOG + `MAX_REQ_TAG_NUM_LOG + PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH - 1 : `MAX_REQ_TAG_NUM_LOG + PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH] : 'd0; +assign count_max = (cur_state == IDLE_s && get_rsp_valid) ? get_rsp_head[COUNT_MAX_LOG * 2 + `MAX_REQ_TAG_NUM_LOG + PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH - 1 : COUNT_MAX_LOG + `MAX_REQ_TAG_NUM_LOG + PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH] : + (cur_state != IDLE_s) ? get_rsp_head_diff[COUNT_MAX_LOG * 2 + `MAX_REQ_TAG_NUM_LOG + PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH - 1 : COUNT_MAX_LOG + `MAX_REQ_TAG_NUM_LOG + PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH] : 'd0; +assign count_collected = reorder_buffer_dout[REORDER_BUFFER_WIDTH - 1 : REORDER_BUFFER_WIDTH - COUNT_MAX_LOG]; + +//-- get_rsp_ready -- +// assign get_rsp_ready = (cur_state == HIT_s && !req_hit_prog_full) || (cur_state == MISS_s && !req_miss_prog_full); +assign get_rsp_ready = (cur_state == IDLE_s) ? 'd1 : 'd0; + +//-- reorder_buffer_wen -- +//-- reorder_buffer_addr -- +always @(*) begin + if(rst) begin + reorder_buffer_wen = 'd0; + reorder_buffer_addr = 'd0; + end + else if(cur_state == IDLE_s && get_rsp_valid) begin + reorder_buffer_wen = 'd0; + reorder_buffer_addr = req_tag; + end + else if(cur_state == HIT_s && !req_hit_prog_full) begin + reorder_buffer_wen = 'd1; + reorder_buffer_addr = req_tag; + end + else begin + reorder_buffer_wen = 'd0; + reorder_buffer_addr = 'd0; + end +end + +//-- reorder_buffer_din -- +always @(*) begin + if(rst) begin + reorder_buffer_din = 'd0; + end + else if(cur_state == HIT_s && !req_hit_prog_full) begin + if(ICM_CACHE_TYPE == `CACHE_TYPE_MTT) begin + if(count_index == 0) begin + reorder_buffer_din = {count_collected + 'd1, reorder_buffer_dout[CACHE_ENTRY_WIDTH * 2 - 1 : CACHE_ENTRY_WIDTH], get_rsp_data_diff}; + end + else if(count_index == 1) begin + reorder_buffer_din = {count_collected + 'd1, get_rsp_data_diff, reorder_buffer_dout[CACHE_ENTRY_WIDTH - 1 : 0]}; + end + else begin + reorder_buffer_din = 'd0; + end + end + else if(ICM_CACHE_TYPE == `CACHE_TYPE_QPC || ICM_CACHE_TYPE == `CACHE_TYPE_CQC || ICM_CACHE_TYPE == `CACHE_TYPE_EQC || ICM_CACHE_TYPE == `CACHE_TYPE_MPT) begin + reorder_buffer_din = {count_collected + 'd1, get_rsp_data_diff}; + end + else begin + reorder_buffer_din = 'd0; + end + end + else begin + reorder_buffer_din = 'd0; + end +end + +//-- dma_rd_req_valid -- +//-- dma_rd_req_head -- +//-- dma_rd_req_data -- +//-- dma_rd_req_last -- +assign dma_rd_req_valid = (cur_state == DMA_s) ? 'd1 : 'd0; +assign dma_rd_req_head = (cur_state == DMA_s) ? {dma_addr, dma_len}: 'd0; +assign dma_rd_req_data = 'd0; +assign dma_rd_req_last = (cur_state == DMA_s) ? 'd1 : 'd0; + +//-- req_hit_wr_en -- +//-- req_hit_din -- +assign req_hit_wr_en = (cur_state == HIT_s && !req_hit_prog_full) ? 'd1 : 'd0; +assign req_hit_din = (cur_state == HIT_s && !req_hit_prog_full) ? get_rsp_head_diff[COUNT_MAX_LOG * 2 + `MAX_REQ_TAG_NUM_LOG + PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH - 1 : 0] : 'd0; + +//-- req_miss_wr_en -- +//-- req_miss_din -- +assign req_miss_wr_en = (cur_state == MISS_s && !req_miss_prog_full) ? 'd1 : 'd0; +assign req_miss_din = (cur_state == MISS_s && !req_miss_prog_full) ? get_rsp_head_diff[COUNT_MAX_LOG * 2 + `MAX_REQ_TAG_NUM_LOG + PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH - 1 : 0] : 'd0; + +//-- get_rsp_head_diff -- +//-- get_rsp_data_diff -- +always @(posedge clk or posedge rst) begin + if (rst) begin + get_rsp_head_diff <= 'd0; + get_rsp_data_diff <= 'd0; + end + else if (cur_state == IDLE_s && get_rsp_valid) begin + get_rsp_head_diff <= get_rsp_head; + get_rsp_data_diff <= get_rsp_data; + end + else begin + get_rsp_head_diff <= get_rsp_head_diff; + get_rsp_data_diff <= get_rsp_data_diff; + end +end +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ + + +`ifdef ILA_ON + generate + if(ICM_CACHE_TYPE == `CACHE_TYPE_QPC) begin + ila_qpc_cache ila_qpc_cache_inst( + .clk(clk), + + .probe0(get_rsp_valid), + .probe1(get_rsp_head), + .probe2(get_rsp_data), + .probe3(get_rsp_ready), + + .probe4(reorder_buffer_wen), + .probe5(reorder_buffer_addr), + .probe6(reorder_buffer_din), + .probe7(reorder_buffer_dout), + + .probe8(dma_rd_req_valid), + .probe9(dma_rd_req_head), + .probe10(dma_rd_req_data), + .probe11(dma_rd_req_last), + .probe12(dma_rd_req_ready), + + .probe13(req_hit_wr_en), + .probe14(req_hit_din), + + .probe15(req_miss_wr_en), + .probe16(req_miss_din) + ); + + end + endgenerate +`endif + +/*------------------------------------------- Local Macros Undef : Begin --------------------------------------------*/ +/*------------------------------------------- Local Macros Undef : End ----------------------------------------------*/ + +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/ICMMgt/ICMCache/ICMGetProc/ICMGetProc_Thread_4.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/ICMMgt/ICMCache/ICMGetProc/ICMGetProc_Thread_4.v new file mode 100644 index 0000000000000000000000000000000000000000..933be0660c8813f57e4d7b5c554cf91d1a7f6699 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/ICMMgt/ICMCache/ICMGetProc/ICMGetProc_Thread_4.v @@ -0,0 +1,360 @@ +/*------------------------------------------- Module Description : Begin ---------------------------------------------- +Name: ICMGetProc_Thread_4 +Author: YangFan +Function: Deal with Cache Hit and Cache Miss. +--------------------------------------------- Module Decription : End -----------------------------------------------*/ + +/*------------------------------------------- Timescale Definition : Begin ------------------------------------------*/ +`timescale 1ns / 1ps +/*------------------------------------------- Timescale Definition : End --------------------------------------------*/ + +/*------------------------------------------- Included Files : Begin ------------------------------------------------*/ +`include "protocol_engine_def.vh" +/*------------------------------------------- Included Files : End --------------------------------------------------*/ + +/*------------------------------------------- Input/Output Definition : Begin ---------------------------------------*/ +module ICMGetProc_Thread_4 + #( + parameter ICM_CACHE_TYPE = `CACHE_TYPE_MTT, + parameter ICM_PAGE_NUM = `ICM_PAGE_NUM_MTT, + parameter ICM_PAGE_NUM_LOG = log2b(ICM_PAGE_NUM - 1), + parameter ICM_ENTRY_NUM = `ICM_ENTRY_NUM_MTT, + parameter ICM_ENTRY_NUM_LOG = log2b(ICM_ENTRY_NUM - 1), + parameter ICM_SLOT_SIZE = `ICM_SLOT_SIZE_MTT, + parameter ICM_ADDR_WIDTH = 64, + + parameter CACHE_ADDR_WIDTH = log2b(ICM_ENTRY_NUM * ICM_SLOT_SIZE - 1), + parameter CACHE_ENTRY_WIDTH = 256, + parameter CACHE_SET_NUM = 1024, + parameter CACHE_SET_NUM_LOG = log2b(CACHE_SET_NUM - 1), + parameter CACHE_OFFSET_WIDTH = log2b(ICM_SLOT_SIZE - 1), + parameter CACHE_TAG_WIDTH = CACHE_ADDR_WIDTH - CACHE_OFFSET_WIDTH - CACHE_SET_NUM_LOG, + parameter PHYSICAL_ADDR_WIDTH = `PHY_SPACE_ADDR_WIDTH, + parameter COUNT_MAX = 2, + parameter COUNT_MAX_LOG = log2b(COUNT_MAX - 1) + 1, + parameter REQ_TAG_NUM = 32, + parameter REQ_TAG_NUM_LOG = log2b(REQ_TAG_NUM - 1), + parameter REORDER_BUFFER_WIDTH = (ICM_CACHE_TYPE == `CACHE_TYPE_MTT) ? CACHE_ENTRY_WIDTH * 2 + COUNT_MAX_LOG : CACHE_ENTRY_WIDTH + COUNT_MAX_LOG +) +( + input wire clk, + input wire rst, + +//ReqHitFIFO Interface + output wire req_hit_rd_en, + input wire [COUNT_MAX_LOG * 2 + `MAX_REQ_TAG_NUM_LOG + PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH - 1 : 0] req_hit_dout, + input wire req_hit_empty, + +//ReqHitFIFO Interface + output wire req_miss_rd_en, + input wire [COUNT_MAX_LOG * 2 + `MAX_REQ_TAG_NUM_LOG + PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH - 1 : 0] req_miss_dout, + input wire req_miss_empty, + +//ReorderBuffer Interface + output reg reorder_buffer_wen, + output reg [`MAX_REQ_TAG_NUM_LOG - 1 : 0] reorder_buffer_addr, + output reg [REORDER_BUFFER_WIDTH - 1 : 0] reorder_buffer_din, + input wire [REORDER_BUFFER_WIDTH - 1 : 0] reorder_buffer_dout, + +//ICM Entry from Memory + input wire icm_entry_rsp_valid, + input wire [CACHE_ENTRY_WIDTH - 1 : 0] icm_entry_rsp_data, + output wire icm_entry_rsp_ready, + +//Cache Set Req + output wire cache_set_req_valid, + output wire [ICM_ADDR_WIDTH - 1 : 0] cache_set_req_head, + output wire [CACHE_ENTRY_WIDTH - 1 : 0] cache_set_req_data, + input wire cache_set_req_ready, + +//ICM Get Resp Interface + output wire icm_get_rsp_valid, + output wire [COUNT_MAX_LOG * 2 + `MAX_REQ_TAG_NUM_LOG + PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH - 1 : 0] icm_get_rsp_head, + output wire [CACHE_ENTRY_WIDTH - 1 : 0] icm_get_rsp_data, + input wire icm_get_rsp_ready +); +/*------------------------------------------- Input/Output Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Macros Definition : Begin ---------------------------------------*/ +/*------------------------------------------- Local Macros Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Variables Definition : Begin ------------------------------------*/ +reg is_hit_proc; +reg is_miss_proc; + +wire [COUNT_MAX_LOG - 1 : 0] count_collected; +wire [COUNT_MAX_LOG - 1 : 0] count_max; +wire [COUNT_MAX_LOG - 1 : 0] count_index; +wire [`MAX_REQ_TAG_NUM_LOG - 1 : 0] req_tag; + +reg [COUNT_MAX_LOG - 1 : 0] rsp_count; +reg [COUNT_MAX_LOG - 1 : 0] rsp_total; +/*------------------------------------------- Local Variables Definition : End --------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : Begin ---------------------------------------*/ +/*------------------------------------------- Submodules Instatiation : End -----------------------------------------*/ + +/*------------------------------------------- State Machine Definition : Begin --------------------------------------*/ +reg [2:0] cur_state; +reg [2:0] next_state; + +parameter [2:0] IDLE_s = 3'd1, + HIT_s = 3'd2, + MISS_s = 3'd3, + SET_s = 3'd4, + RSP_s = 3'd5; + +always @(posedge clk or posedge rst) begin + if(rst) begin + cur_state <= IDLE_s; + end + else begin + cur_state <= next_state; + end +end + +always @(*) begin + case(cur_state) + IDLE_s: if(!req_miss_empty && icm_entry_rsp_valid) begin //Miss Req has higher priority + next_state = MISS_s; + end + else if(!req_hit_empty) begin + next_state = HIT_s; + end + else begin + next_state = IDLE_s; + end + HIT_s: if(count_collected == count_max) begin + next_state = RSP_s; + end + else begin + next_state = IDLE_s; + end + MISS_s: next_state = SET_s; + SET_s: if(count_collected == count_max && cache_set_req_valid && cache_set_req_ready) begin + next_state = RSP_s; + end + else if(count_collected < count_max && cache_set_req_valid && cache_set_req_ready) begin + next_state = IDLE_s; //Finish curren miss req, wait ultil all request are collected + end + else begin + next_state = SET_s; + end + RSP_s: if(icm_get_rsp_valid && icm_get_rsp_ready && (rsp_count == rsp_total)) begin + next_state = IDLE_s; + end + else begin + next_state = RSP_s; + end + default: next_state = IDLE_s; + endcase +end + +/*------------------------------------------- State Machine Definition : End ----------------------------------------*/ + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ +//-- req_hit_rd_en -- +//Break timing loop +// assign req_hit_rd_en = (cur_state == HIT_s && next_state == IDLE_s) ? 'd1 : +// (cur_state == RSP_s && next_state == IDLE_s && is_hit_proc) ? 'd1 : 'd0; +assign req_hit_rd_en = (cur_state == HIT_s && (count_collected != count_max)) ? 'd1 : + (cur_state == RSP_s && (icm_get_rsp_valid && icm_get_rsp_ready && (rsp_count == rsp_total)) && is_hit_proc) ? 'd1 : 'd0; + +//-- req_miss_rd_en -- +// assign req_miss_rd_en = (cur_state == SET_s && next_state == IDLE_s) ? 'd1 : +// (cur_state == RSP_s && next_state == IDLE_s && is_miss_proc) ? 'd1 : 'd0; +assign req_miss_rd_en = (cur_state == SET_s && (count_collected < count_max && cache_set_req_valid && cache_set_req_ready)) ? 'd1 : + (cur_state == RSP_s && (icm_get_rsp_valid && icm_get_rsp_ready && (rsp_count == rsp_total)) && is_miss_proc) ? 'd1 : 'd0; + +//-- count_collected -- +assign count_collected = (cur_state != IDLE_s) ? reorder_buffer_dout[REORDER_BUFFER_WIDTH - 1 : REORDER_BUFFER_WIDTH - COUNT_MAX_LOG] : 'd0; + +//-- count_max -- +assign count_max = (cur_state == IDLE_s && !req_miss_empty && icm_entry_rsp_valid) ? req_miss_dout[COUNT_MAX_LOG * 2 + `MAX_REQ_TAG_NUM_LOG + PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH - 1 : COUNT_MAX_LOG + `MAX_REQ_TAG_NUM_LOG + PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH] : + (cur_state == IDLE_s && !req_hit_empty) ? req_hit_dout[COUNT_MAX_LOG * 2 + `MAX_REQ_TAG_NUM_LOG + PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH - 1 : COUNT_MAX_LOG + `MAX_REQ_TAG_NUM_LOG + PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH] : + is_miss_proc ? req_miss_dout[COUNT_MAX_LOG * 2+ `MAX_REQ_TAG_NUM_LOG + PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH - 1 : COUNT_MAX_LOG + `MAX_REQ_TAG_NUM_LOG + PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH] : + is_hit_proc ? req_hit_dout[COUNT_MAX_LOG * 2 + `MAX_REQ_TAG_NUM_LOG + PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH - 1 : COUNT_MAX_LOG + `MAX_REQ_TAG_NUM_LOG + PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH] : 'd0; + +//-- count_index =-- +assign count_index = (cur_state == IDLE_s && !req_miss_empty && icm_entry_rsp_valid) ? req_miss_dout[COUNT_MAX_LOG * 2 + `MAX_REQ_TAG_NUM_LOG + PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH - 1 : COUNT_MAX_LOG + `MAX_REQ_TAG_NUM_LOG + PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH] : + (cur_state == IDLE_s && !req_hit_empty) ? req_hit_dout[COUNT_MAX_LOG * 2 + `MAX_REQ_TAG_NUM_LOG + PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH - 1 : COUNT_MAX_LOG + `MAX_REQ_TAG_NUM_LOG + PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH] : + is_miss_proc ? req_miss_dout[COUNT_MAX_LOG + `MAX_REQ_TAG_NUM_LOG + PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH - 1 : `MAX_REQ_TAG_NUM_LOG + PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH] : + is_hit_proc ? req_hit_dout[COUNT_MAX_LOG + `MAX_REQ_TAG_NUM_LOG + PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH - 1 : `MAX_REQ_TAG_NUM_LOG + PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH] : 'd0; + +//-- req_tag -- +assign req_tag = (cur_state == IDLE_s && !req_miss_empty && icm_entry_rsp_valid) ? req_miss_dout[`MAX_REQ_TAG_NUM_LOG + PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH - 1 : PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH] : + (cur_state == IDLE_s && !req_hit_empty) ? req_hit_dout[`MAX_REQ_TAG_NUM_LOG + PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH - 1 : PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH] : + is_miss_proc ? req_miss_dout[`MAX_REQ_TAG_NUM_LOG + PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH - 1 : PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH] : + is_hit_proc ? req_hit_dout[`MAX_REQ_TAG_NUM_LOG + PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH - 1 : PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH] : 'd0; + +//-- is_hit_proc -- +always @(posedge clk or posedge rst) begin + if(rst) begin + is_hit_proc <= 'd0; + end + else if(cur_state == IDLE_s && !req_miss_empty && icm_entry_rsp_valid) begin //Miss Req has higher priority + is_hit_proc <= 'd0; + end + else if(cur_state == IDLE_s && !req_hit_empty) begin + is_hit_proc <= 'd1; + end + else begin + is_hit_proc <= is_hit_proc; + end +end + +//-- is_miss_proc -- +always @(posedge clk or posedge rst) begin + if(rst) begin + is_miss_proc <= 'd0; + end + else if(cur_state == IDLE_s && !req_miss_empty && icm_entry_rsp_valid) begin //Miss Req has higher priority + is_miss_proc <= 'd1; + end + else if(cur_state == IDLE_s && !req_hit_empty) begin + is_miss_proc <= 'd0; + end + else begin + is_miss_proc <= is_miss_proc; + end +end + +//-- rsp_count -- +always @(posedge clk or posedge rst) begin + if(rst) begin + rsp_count <= 'd0; + end + else if(cur_state == IDLE_s) begin + rsp_count <= 'd0; + end + // else if(cur_state != RSP_s && next_state == RSP_s) begin + // rsp_count <= 'd1; + // end + else if(cur_state == HIT_s && (count_collected == count_max)) begin + rsp_count <= 'd1; + end + else if(cur_state == SET_s && (count_collected == count_max) && cache_set_req_valid && cache_set_req_ready) begin + rsp_count <= 'd1; + end + else if(cur_state == RSP_s && icm_get_rsp_valid && icm_get_rsp_ready) begin + if(rsp_count < rsp_total) begin + rsp_count <= rsp_count + 'd1; + end + else begin + rsp_count <= 'd0; + end + end + else begin + rsp_count <= rsp_count; + end +end + +//-- rsp_total -- +always @(posedge clk or posedge rst) begin + if (rst) begin + rsp_total <= 'd0; + end + else if(cur_state == IDLE_s) begin + rsp_total <= 'd0; + end + // else if (cur_state != RSP_s && next_state == RSP_s) begin + // rsp_total <= count_max; + // end + else if(cur_state == HIT_s && (count_collected == count_max)) begin + rsp_total <= count_max; + end + else if(cur_state == SET_s && (count_collected == count_max) && cache_set_req_valid && cache_set_req_ready) begin + rsp_total <= count_max; + end + else begin + rsp_total <= rsp_total; + end +end + +//-- reorder_buffer_wen -- +//-- reorder_buffer_addr -- +//-- reorder_buffer_din -- +always @(*) begin + if(rst) begin + reorder_buffer_wen = 'd0; + reorder_buffer_addr = 'd0; + reorder_buffer_din = 'd0; + end + else if(cur_state == IDLE_s && icm_entry_rsp_valid && (!req_hit_empty || !req_miss_empty)) begin + reorder_buffer_wen = 'd0; + reorder_buffer_addr = req_tag; + reorder_buffer_din = 'd0; + end + else if(cur_state == HIT_s) begin + reorder_buffer_wen = 'd0; + reorder_buffer_addr = req_tag; + reorder_buffer_din = 'd0; + end + else if(cur_state == MISS_s) begin + if(ICM_CACHE_TYPE == `CACHE_TYPE_MTT) begin + if(count_index == 0) begin + reorder_buffer_wen = 'd1; + reorder_buffer_addr = req_tag; + reorder_buffer_din = {count_collected + 'd1, reorder_buffer_dout[CACHE_ENTRY_WIDTH * 2 - 1 : CACHE_ENTRY_WIDTH], icm_entry_rsp_data}; + end + else if(count_index == 1) begin + reorder_buffer_wen = 'd1; + reorder_buffer_addr = req_tag; + reorder_buffer_din = {count_collected + 'd1, icm_entry_rsp_data, reorder_buffer_dout[CACHE_ENTRY_WIDTH - 1 : 0]}; + end + else begin + reorder_buffer_wen = 'd0; + reorder_buffer_addr = req_tag; + reorder_buffer_din = 'd0; + end + end + else if(ICM_CACHE_TYPE == `CACHE_TYPE_QPC || ICM_CACHE_TYPE == `CACHE_TYPE_CQC || ICM_CACHE_TYPE == `CACHE_TYPE_EQC || ICM_CACHE_TYPE == `CACHE_TYPE_MPT) begin + reorder_buffer_wen = 'd1; + reorder_buffer_addr = req_tag; + reorder_buffer_din = {count_collected + 'd1, icm_entry_rsp_data}; + end + else begin + reorder_buffer_wen = 'd0; + reorder_buffer_addr = req_tag; + reorder_buffer_din = 'd0; + end + end + else if(cur_state == SET_s) begin + reorder_buffer_wen = 'd0; + reorder_buffer_addr = req_tag; + reorder_buffer_din = 'd0; + end + else if(cur_state == RSP_s && icm_get_rsp_valid && icm_get_rsp_ready && (rsp_count == rsp_total)) begin //Each time response, clear curretn slot + reorder_buffer_wen = 'd1; + reorder_buffer_addr = req_tag; + reorder_buffer_din = 'd0; + end + else begin + reorder_buffer_wen = 'd0; + reorder_buffer_addr = req_tag; + reorder_buffer_din = 'd0; + end +end + +//-- icm_entry_rsp_ready -- +assign icm_entry_rsp_ready = (cur_state == SET_s) && cache_set_req_ready; + +//-- cache_set_req_valid -- +//-- cache_set_req_head -- +//-- cache_set_req_data -- +assign cache_set_req_valid = (cur_state == SET_s) ? 'd1 : 'd0; +assign cache_set_req_head = (cur_state == SET_s) ? req_miss_dout[CACHE_ADDR_WIDTH - 1 : 0] : 'd0; +assign cache_set_req_data = (cur_state == SET_s) ? icm_entry_rsp_data : 'd0; + +//ICM Get Resp Interface +assign icm_get_rsp_valid = (cur_state == RSP_s) ? 'd1 : 'd0; +assign icm_get_rsp_head = (cur_state == RSP_s && is_miss_proc) ? req_miss_dout : + (cur_state == RSP_s && is_hit_proc) ? req_hit_dout : 'd0; +assign icm_get_rsp_data = (cur_state == RSP_s && rsp_count == 'd1) ? reorder_buffer_dout[CACHE_ENTRY_WIDTH - 1 : 0] : + (cur_state == RSP_s && rsp_count == 'd2 && ICM_CACHE_TYPE == `CACHE_TYPE_MTT) ? reorder_buffer_dout[CACHE_ENTRY_WIDTH * 2 - 1 : CACHE_ENTRY_WIDTH] : 'd0; +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ + +/*------------------------------------------- Local Macros Undef : Begin --------------------------------------------*/ +/*------------------------------------------- Local Macros Undef : End ----------------------------------------------*/ + +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/ICMMgt/ICMCache/ICMGetProc/ICMGetProc_Thread_5.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/ICMMgt/ICMCache/ICMGetProc/ICMGetProc_Thread_5.v new file mode 100644 index 0000000000000000000000000000000000000000..db5c825f2daac02b993a7e2cb8d144b54c2c11c3 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/ICMMgt/ICMCache/ICMGetProc/ICMGetProc_Thread_5.v @@ -0,0 +1,379 @@ +/*------------------------------------------- Module Description : Begin ---------------------------------------------- +Name: ICMGetProc_Thread_5 +Author: YangFan +Function: Extract needed ICM info from DMA Response. +--------------------------------------------- Module Decription : End -----------------------------------------------*/ + +/*------------------------------------------- Timescale Definition : Begin ------------------------------------------*/ +`timescale 1ns / 1ps +/*------------------------------------------- Timescale Definition : End --------------------------------------------*/ + +/*------------------------------------------- Included Files : Begin ------------------------------------------------*/ +`include "protocol_engine_def.vh" +/*------------------------------------------- Included Files : End --------------------------------------------------*/ + +/*------------------------------------------- Input/Output Definition : Begin ---------------------------------------*/ +module ICMGetProc_Thread_5 +#( + parameter ICM_CACHE_TYPE = `CACHE_TYPE_MTT, + parameter ICM_PAGE_NUM = `ICM_PAGE_NUM_MTT, + parameter ICM_PAGE_NUM_LOG = log2b(ICM_PAGE_NUM - 1), + parameter ICM_ENTRY_NUM = `ICM_ENTRY_NUM_MTT, + parameter ICM_ENTRY_NUM_LOG = log2b(ICM_ENTRY_NUM - 1), + parameter ICM_SLOT_SIZE = `ICM_SLOT_SIZE_MTT, + parameter ICM_ADDR_WIDTH = 64, + + parameter CACHE_ADDR_WIDTH = log2b(ICM_ENTRY_NUM * ICM_SLOT_SIZE - 1), + parameter CACHE_ENTRY_WIDTH = 256, + parameter CACHE_SET_NUM = 1024, + parameter CACHE_SET_NUM_LOG = log2b(CACHE_SET_NUM - 1), + parameter CACHE_OFFSET_WIDTH = log2b(ICM_SLOT_SIZE - 1), + parameter CACHE_TAG_WIDTH = CACHE_ADDR_WIDTH - CACHE_OFFSET_WIDTH - CACHE_SET_NUM_LOG, + parameter PHYSICAL_ADDR_WIDTH = `PHY_SPACE_ADDR_WIDTH, + parameter COUNT_MAX = 2, + parameter COUNT_MAX_LOG = log2b(COUNT_MAX - 1) + 1, + parameter REQ_TAG_NUM = 32, + parameter REQ_TAG_NUM_LOG = log2b(REQ_TAG_NUM - 1), + parameter REORDER_BUFFER_WIDTH = (ICM_CACHE_TYPE == `CACHE_TYPE_MTT) ? CACHE_ENTRY_WIDTH * 2 + COUNT_MAX_LOG : CACHE_ENTRY_WIDTH + COUNT_MAX_LOG +) +( + input wire clk, + input wire rst, + +//DMA Read Rsp Interface + input wire dma_rd_rsp_valid, + input wire [`DMA_HEAD_WIDTH - 1 : 0] dma_rd_rsp_head, + input wire [`DMA_DATA_WIDTH - 1 : 0] dma_rd_rsp_data, + input wire dma_rd_rsp_last, + output wire dma_rd_rsp_ready, + +//ICM Entry from Memory + output wire icm_entry_rsp_valid, + output reg [CACHE_ENTRY_WIDTH - 1 : 0] icm_entry_rsp_data, + input wire icm_entry_rsp_ready +); +/*------------------------------------------- Input/Output Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Macros Definition : Begin ---------------------------------------*/ +/*------------------------------------------- Local Macros Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Variables Definition : Begin ------------------------------------*/ +reg [2:0] piece_count; +reg [2:0] piece_num; + +//QPC Info +wire [2:0] service_type; +wire [3:0] state; +wire [7:0] mtu_msgmax; +wire [7:0] sq_entry_sz_log; +wire [7:0] rq_entry_sz_log; +wire [15:0] dst_qpn; +wire [7:0] pkey_index; +wire [7:0] port_index; +wire [15:0] cqn_snd; +wire [15:0] cqn_rcv; +wire [31:0] qp_pd; +wire [31:0] sq_lkey; +wire [31:0] sq_length; +wire [31:0] rq_lkey; +wire [31:0] rq_length; +wire [15:0] dmac_low_dlid; +wire [15:0] smac_low_slid; +wire [31:0] dmac_high; +wire [31:0] smac_high; +wire [31:0] dip; +wire [31:0] sip; + +//CQC Info +wire [7:0] cq_log_size; +wire [31:0] comp_eqn; +wire [31:0] cq_pd; +wire [31:0] cq_lkey; + +//EQC Info +wire [7:0] eq_log_size; +wire [7:0] msix_interrupt; +wire [31:0] eq_pd; +wire [31:0] eq_lkey; + +//MPT Info +wire [31:0] flags; +wire [31:0] page_size; +wire [31:0] mpt_key; +wire [31:0] mpt_pd; +wire [63:0] start_addr; +wire [63:0] mr_length; +wire [63:0] mtt_seg; + +//MTT Info +wire [63:0] physical_address; + +/*------------------------------------------- Local Variables Definition : End --------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : Begin ---------------------------------------*/ +/*------------------------------------------- Submodules Instatiation : End -----------------------------------------*/ + +/*------------------------------------------- State Machine Definition : Begin --------------------------------------*/ +reg [1:0] cur_state; +reg [1:0] next_state; + +parameter [1:0] IDLE_s = 2'd1, + COLLECT_s = 2'd2, + RSP_s = 2'd3; + +always @(posedge clk or posedge rst) begin + if(rst) begin + cur_state <= IDLE_s; + end + else begin + cur_state <= next_state; + end +end + +always @(*) begin + case(cur_state) + IDLE_s: if(dma_rd_rsp_valid) begin + // next_state = COLLECT_s; + next_state = RSP_s; + end + else begin + next_state = IDLE_s; + end + // COLLECT_s: if(dma_rd_rsp_valid && piece_count == piece_num) begin + // next_state = RSP_s; + // end + // else begin + // next_state = COLLECT_s; + // end + RSP_s: if(icm_entry_rsp_valid && icm_entry_rsp_ready) begin + next_state = IDLE_s; + end + else begin + next_state = RSP_s; + end + default: next_state = IDLE_s; + endcase +end +/*------------------------------------------- State Machine Definition : End ----------------------------------------*/ + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ +//-- piece_count -- +always @(posedge clk or posedge rst) begin + if(rst) begin + piece_count <= 'd0; + end + else if(cur_state == IDLE_s && dma_rd_rsp_valid) begin + piece_count <= 'd1; + end + else if(cur_state == COLLECT_s && dma_rd_rsp_valid) begin + piece_count <= piece_count + 'd1; + end + else if(cur_state == RSP_s) begin + piece_count <= 'd0; + end + else begin + piece_count <= piece_count; + end +end + +//-- piece_num -- +always @(posedge clk or posedge rst) begin + if (rst) begin + piece_num <= 'd0; + end + else if (cur_state == IDLE_s && dma_rd_rsp_valid) begin + case(ICM_CACHE_TYPE) + `CACHE_TYPE_QPC: piece_num <= 'd1; + `CACHE_TYPE_CQC: piece_num <= 'd1; + `CACHE_TYPE_EQC: piece_num <= 'd1; + `CACHE_TYPE_MPT: piece_num <= 'd1; + `CACHE_TYPE_MTT: piece_num <= 'd1; + default: piece_num <= 'd0; + endcase + end + else if(cur_state == RSP_s) begin + piece_num <= 'd0; + end + else begin + piece_num <= piece_num; + end +end + +//-- icm_entry_rsp_valid -- +assign icm_entry_rsp_valid = (cur_state == RSP_s) ? 'd1 : 'd0; + +//-- QPC Info -- +assign service_type = dma_rd_rsp_data[82:80]; +assign state = dma_rd_rsp_data[93:91]; +assign mtu_msgmax = dma_rd_rsp_data[127:120]; +assign sq_entry_sz_log = dma_rd_rsp_data[111:104]; +assign rq_entry_sz_log = dma_rd_rsp_data[119:112]; +assign dst_qpn = dma_rd_rsp_data[223:192]; +assign pkey_index = dma_rd_rsp_data[231:224]; +assign port_index = dma_rd_rsp_data[255:248]; +assign cqn_snd = dma_rd_rsp_data[159 + 256:128 + 256]; +assign cqn_rcv = dma_rd_rsp_data[127:96]; +assign qp_pd = dma_rd_rsp_data[255:224]; +assign sq_lkey = dma_rd_rsp_data[191 + 256:160 + 256]; +assign sq_length = dma_rd_rsp_data[223 + 256 : 192 + 256]; +assign rq_lkey = dma_rd_rsp_data[159:128]; +assign rq_length = dma_rd_rsp_data[191:160]; +assign dmac_low_dlid = dma_rd_rsp_data[255 + 256:240 + 256]; +assign smac_low_slid = dma_rd_rsp_data[239 + 256:224 + 256]; +assign dmac_high = dma_rd_rsp_data[63:32]; +assign smac_high = dma_rd_rsp_data[31:0]; +assign dip = dma_rd_rsp_data[127:96]; +assign sip = dma_rd_rsp_data[95:64]; + +//-- CQC Info -- +assign cq_log_size = dma_rd_rsp_data[127:120]; +assign comp_eqn = dma_rd_rsp_data[159:128]; +assign cq_pd = dma_rd_rsp_data[191:160]; +assign cq_lkey = dma_rd_rsp_data[223:192]; + +//-- EQC Info -- +assign eq_log_size = dma_rd_rsp_data[127:96]; +assign msix_interrupt = dma_rd_rsp_data[167:160]; +assign eq_pd = dma_rd_rsp_data[223:192]; +assign eq_lkey = dma_rd_rsp_data[255:224]; + +//-- MPT Info -- +assign flags = dma_rd_rsp_data[31:0]; +assign page_size = dma_rd_rsp_data[63:32]; +assign mpt_key = dma_rd_rsp_data[95:64]; +assign mpt_pd = dma_rd_rsp_data[127:96]; +assign start_addr = dma_rd_rsp_data[191:128]; +assign mr_length = dma_rd_rsp_data[255:192]; +assign mtt_seg = dma_rd_rsp_data[415:352]; + +//-- MTT Info -- +assign physical_address = dma_rd_rsp_data[63:0]; + +// generate +// if(ICM_CACHE_TYPE == `CACHE_TYPE_QPC) begin: EXTRACT_QPC +// //-- icm_entry_rsp_data -- +// always @(posedge clk or posedge rst) begin +// if(rst) begin +// icm_entry_rsp_data <= 'd0; +// end +// else if(cur_state == COLLECT_s && dma_rd_rsp_valid) begin +// if(piece_count == 1) begin +// icm_entry_rsp_data <= {128'd0, dmac_low_dlid, smac_low_slid, 192'd0, port_index, pkey_index, dst_qpn, rq_entry_sz_log, sq_entry_sz_log, mtu_msgmax, {2'd0, state, service_type}}; +// end +// else if(piece_count == 2) begin +// icm_entry_rsp_data <= {dip, sip, dmac_high, smac_high, icm_entry_rsp_data[283:256], 64'd0, sq_length, sq_lkey, qp_pd, cqn_snd, 16'd0, icm_entry_rsp_data[63:0]}; +// end +// else if(piece_count == 3) begin +// icm_entry_rsp_data <= {icm_entry_rsp_data[415:256], rq_length, rq_lkey, icm_entry_rsp_data[191:96], cqn_rcv, icm_entry_rsp_data[71:0]}; +// end +// else begin +// icm_entry_rsp_data <= icm_entry_rsp_data; +// end +// end +// else if(cur_state == RSP_s && icm_entry_rsp_valid && icm_entry_rsp_ready) begin +// icm_entry_rsp_data <= 'd0; +// end +// else begin +// icm_entry_rsp_data <= icm_entry_rsp_data; +// end +// end +// end +// else if(ICM_CACHE_TYPE == `CACHE_TYPE_CQC) begin: EXTRACT_CQC +// //-- icm_entry_rsp_data -- +// always @(posedge clk or posedge rst) begin +// if(rst) begin +// icm_entry_rsp_data <= 'd0; +// end +// else if(cur_state == COLLECT_s && dma_rd_rsp_valid) begin +// icm_entry_rsp_data <= {cq_lkey, cq_pd, comp_eqn, 24'd0, cq_log_size}; +// end +// else if(cur_state == RSP_s && icm_entry_rsp_valid && icm_entry_rsp_ready) begin +// icm_entry_rsp_data <= 'd0; +// end +// else begin +// icm_entry_rsp_data <= icm_entry_rsp_data; +// end +// end +// end +// else if(ICM_CACHE_TYPE == `CACHE_TYPE_EQC) begin: EXTRACT_EQC +// //-- icm_entry_rsp_data -- +// always @(posedge clk or posedge rst) begin +// if(rst) begin +// icm_entry_rsp_data <= 'd0; +// end +// else if(cur_state == COLLECT_s && dma_rd_rsp_valid) begin +// icm_entry_rsp_data <= {eq_lkey, eq_pd, 16'd0, msix_interrupt, eq_log_size}; +// end +// else if(cur_state == RSP_s && icm_entry_rsp_valid && icm_entry_rsp_ready) begin +// icm_entry_rsp_data <= 'd0; +// end +// else begin +// icm_entry_rsp_data <= icm_entry_rsp_data; +// end +// end +// end +// else if(ICM_CACHE_TYPE == `CACHE_TYPE_MPT) begin: EXTRACT_MPT +// //-- icm_entry_rsp_data -- +// always @(posedge clk or posedge rst) begin +// if(rst) begin +// icm_entry_rsp_data <= 'd0; +// end +// else if(cur_state == COLLECT_s && dma_rd_rsp_valid) begin +// icm_entry_rsp_data <= {mtt_seg, mr_length, start_addr, mpt_pd, mpt_key, page_size, flags}; +// end +// else if(cur_state == RSP_s && icm_entry_rsp_valid && icm_entry_rsp_ready) begin +// icm_entry_rsp_data <= 'd0; +// end +// else begin +// icm_entry_rsp_data <= icm_entry_rsp_data; +// end +// end +// end +// else if(ICM_CACHE_TYPE == `CACHE_TYPE_MTT) begin: EXTRACT_MTT +// //-- icm_entry_rsp_data -- +// always @(posedge clk or posedge rst) begin +// if(rst) begin +// icm_entry_rsp_data <= 'd0; +// end +// else if(cur_state == COLLECT_s && dma_rd_rsp_valid) begin +// icm_entry_rsp_data <= physical_address; +// end +// else if(cur_state == RSP_s && icm_entry_rsp_valid && icm_entry_rsp_ready) begin +// icm_entry_rsp_data <= 'd0; +// end +// else begin +// icm_entry_rsp_data <= icm_entry_rsp_data; +// end +// end +// end +// else begin + +// end +// endgenerate + +//-- dma_rd_rsp_ready -- +// assign dma_rd_rsp_ready = (cur_state == COLLECT_s) ? 'd1 : 'd0; +assign dma_rd_rsp_ready = (cur_state == IDLE_s) ? 'd1 : 'd0; + +//-- icm_entry_rsp_data -- +always @(posedge clk or posedge rst) begin + if (rst) begin + icm_entry_rsp_data <= 'd0; + end + // else if (cur_state == COLLECT_s && dma_rd_rsp_valid) begin + // icm_entry_rsp_data <= dma_rd_rsp_data; + // end + else if (cur_state == IDLE_s && dma_rd_rsp_valid) begin + icm_entry_rsp_data <= dma_rd_rsp_data; + end + else begin + icm_entry_rsp_data <= icm_entry_rsp_data; + end +end + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ + +/*------------------------------------------- Local Macros Undef : Begin --------------------------------------------*/ +/*------------------------------------------- Local Macros Undef : End ----------------------------------------------*/ + +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/ICMMgt/ICMCache/ICMMetaProc/ICMLookupArbiter.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/ICMMgt/ICMCache/ICMMetaProc/ICMLookupArbiter.v new file mode 100644 index 0000000000000000000000000000000000000000..70f6c80a8886434263e985fb74234d96b3728efc --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/ICMMgt/ICMCache/ICMMetaProc/ICMLookupArbiter.v @@ -0,0 +1,69 @@ +/*------------------------------------------- Module Description : Begin ---------------------------------------------- +Name: ICMLookupArbiter +Author: YangFan +Function: Schedule MR requests from different channels. + + We assume there is no access collision, just for performan optimization. +--------------------------------------------- Module Decription : End -----------------------------------------------*/ + +/*------------------------------------------- Timescale Definition : Begin ------------------------------------------*/ +`timescale 1ns / 1ps +/*------------------------------------------- Timescale Definition : End --------------------------------------------*/ + +/*------------------------------------------- Included Files : Begin ------------------------------------------------*/ +`include "protocol_engine_def.vh" +/*------------------------------------------- Included Files : End --------------------------------------------------*/ + +/*------------------------------------------- Input/Output Definition : Begin ---------------------------------------*/ +module ICMLookupArbiter +#( + parameter ICM_ENTRY_NUM = `ICM_ENTRY_NUM_MPT, + parameter ICM_ENTRY_NUM_LOG = log2b(ICM_ENTRY_NUM - 1) +) +( + input wire clk, + input wire rst, + + input wire chnl_0_lookup_valid, + input wire [ICM_ENTRY_NUM_LOG - 1 : 0] chnl_0_lookup_head, + output wire chnl_0_lookup_ready, + + output wire chnl_0_rsp_valid, + output wire [`ICM_SPACE_ADDR_WIDTH - 1 : 0] chnl_0_rsp_icm_addr, + output wire [`PHY_SPACE_ADDR_WIDTH - 1 : 0] chnl_0_rsp_phy_addr, + input wire chnl_0_rsp_ready, + + input wire chnl_1_lookup_valid, + input wire [ICM_ENTRY_NUM_LOG - 1 : 0] chnl_1_lookup_head, + output wire chnl_1_lookup_ready, + + output wire chnl_1_rsp_valid, + output wire [`ICM_SPACE_ADDR_WIDTH - 1 : 0] chnl_1_rsp_icm_addr, + output wire [`PHY_SPACE_ADDR_WIDTH - 1 : 0] chnl_1_rsp_phy_addr, + input wire chnl_1_rsp_ready, + + output wire lookup_valid, + output wire [ICM_ENTRY_NUM_LOG - 1 : 0] lookup_head, + + input wire rsp_valid, + input wire [`ICM_SPACE_ADDR_WIDTH - 1 : 0] rsp_icm_addr, + input wire [`PHY_SPACE_ADDR_WIDTH - 1 : 0] rsp_phy_addr +); + +assign chnl_0_lookup_ready = 'd1; +assign chnl_1_lookup_ready = 'd1; + +assign lookup_valid = chnl_0_lookup_valid ? chnl_0_lookup_valid : + chnl_1_lookup_valid ? chnl_1_lookup_valid : 'd0; +assign lookup_head = chnl_0_lookup_valid ? chnl_0_lookup_head : + chnl_1_lookup_valid ? chnl_1_lookup_head : 'd0; + +assign chnl_0_rsp_valid = rsp_valid; +assign chnl_0_rsp_icm_addr = rsp_icm_addr; +assign chnl_0_rsp_phy_addr = rsp_phy_addr; + +assign chnl_1_rsp_valid = rsp_valid; +assign chnl_1_rsp_icm_addr = rsp_icm_addr; +assign chnl_1_rsp_phy_addr = rsp_phy_addr; + +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/ICMMgt/ICMCache/ICMMetaProc/ICMMetaProc.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/ICMMgt/ICMCache/ICMMetaProc/ICMMetaProc.v new file mode 100644 index 0000000000000000000000000000000000000000..c601f39e38331bf73a549aa0ba2ec70744f2433f --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/ICMMgt/ICMCache/ICMMetaProc/ICMMetaProc.v @@ -0,0 +1,145 @@ +/*------------------------------------------- Module Description : Begin ---------------------------------------------- +Name: ICMMetaProc +Author: YangFan +Function: Store ICM space to Physical Address Mapping. +--------------------------------------------- Module Decription : End -----------------------------------------------*/ + +/*------------------------------------------- Timescale Definition : Begin ------------------------------------------*/ +`timescale 1ns / 1ps +/*------------------------------------------- Timescale Definition : End --------------------------------------------*/ + +/*------------------------------------------- Included Files : Begin ------------------------------------------------*/ +`include "protocol_engine_def.vh" +/*------------------------------------------- Included Files : End --------------------------------------------------*/ + +/*------------------------------------------- Input/Output Definition : Begin ---------------------------------------*/ +module ICMMetaProc +#( + parameter ICM_CACHE_TYPE = `CACHE_TYPE_MTT, + + parameter ICM_PAGE_NUM = `ICM_PAGE_NUM_MTT, + parameter ICM_PAGE_NUM_LOG = log2b(ICM_PAGE_NUM - 1), + parameter ICM_ENTRY_NUM = `ICM_ENTRY_NUM_MTT, + parameter ICM_ENTRY_NUM_LOG = log2b(ICM_ENTRY_NUM - 1), + parameter ICM_SLOT_SIZE = `ICM_SLOT_SIZE_MTT +) +( + input wire clk, + input wire rst, + +//Set ICM Mapping Table Entry + input wire icm_mapping_set_valid, + input wire [`PAGE_FRAME_WIDTH - 1 : 0] icm_mapping_set_head, + input wire [`PAGE_FRAME_WIDTH - 1 : 0] icm_mapping_set_data, + +//Mapping Lookup Interface + input wire icm_mapping_lookup_valid, + input wire [ICM_ENTRY_NUM_LOG - 1 : 0] icm_mapping_lookup_head, + + output reg icm_mapping_rsp_valid, + output reg [`ICM_SPACE_ADDR_WIDTH - 1 : 0] icm_mapping_rsp_icm_addr, + output wire [`PHY_SPACE_ADDR_WIDTH - 1 : 0] icm_mapping_rsp_phy_addr, + + input wire [`ICM_SPACE_ADDR_WIDTH - 1 : 0] icm_base +); +/*------------------------------------------- Input/Output Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Macros Definition : Begin ---------------------------------------*/ +/*------------------------------------------- Local Macros Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Variables Definition : Begin ------------------------------------*/ +wire mapping_wea; +wire [ICM_PAGE_NUM_LOG - 1 : 0] mapping_addra; +wire [`PAGE_FRAME_WIDTH - 1 : 0] mapping_dina; + +wire [ICM_PAGE_NUM_LOG - 1 : 0] mapping_addrb; +wire [`PAGE_FRAME_WIDTH - 1 : 0] mapping_doutb; + +wire [`ICM_SPACE_ADDR_WIDTH - 1 : 0] icm_lookup_relative_addr; +reg [11:0] icm_lookup_page_offset; +/*------------------------------------------- Local Variables Definition : End --------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : Begin ---------------------------------------*/ +SRAM_SDP_Template #( + .RAM_WIDTH ( `PAGE_FRAME_WIDTH ), + .RAM_DEPTH ( ICM_PAGE_NUM ) +) +ICMMappingTable +( + .clk ( clk ), + .rst ( rst ), + + .wea ( mapping_wea ), + .addra ( mapping_addra ), + .dina ( mapping_dina ), + + .addrb ( mapping_addrb ), + .doutb ( mapping_doutb ) +); +/*------------------------------------------- Submodules Instatiation : End -----------------------------------------*/ + +/*------------------------------------------- State Machine Definition : Begin --------------------------------------*/ +/*------------------------------------------- State Machine Definition : End ----------------------------------------*/ + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ +//-- icm_lookup_relative_addr -- +assign icm_lookup_relative_addr = icm_mapping_lookup_head * ICM_SLOT_SIZE; + +//-- mapping_wea -- +//-- mapping_addra -- +//-- mapping_dina -- +assign mapping_wea = icm_mapping_set_valid; +assign mapping_addra = icm_mapping_set_head - (icm_base >> 12); +assign mapping_dina = icm_mapping_set_data; + +//-- mapping_addrb -- +assign mapping_addrb = icm_mapping_lookup_valid ? icm_lookup_relative_addr[63:12] : 'd0; + +//-- icm_mapping_rsp_icm_addr -- +always @(posedge clk or posedge rst) begin + if(rst) begin + icm_mapping_rsp_icm_addr <= 'd0; + end + else if(icm_mapping_lookup_valid) begin + icm_mapping_rsp_icm_addr <= icm_lookup_relative_addr; + end + else if(icm_mapping_rsp_valid) begin + icm_mapping_rsp_icm_addr <= 'd0; + end + else begin + icm_mapping_rsp_icm_addr <= icm_mapping_rsp_icm_addr; + end +end + +//-- icm_lookup_page_offset -- +always @(posedge clk or posedge rst) begin + if (rst) begin + icm_lookup_page_offset <= 'd0; + end + else if (icm_mapping_lookup_valid) begin + icm_lookup_page_offset <= icm_lookup_relative_addr[11:0]; + end + else begin + icm_lookup_page_offset <= 'd0; + end +end + +//-- icm_mapping_rsp_valid -- +always @(posedge clk or posedge rst) begin + if(rst) begin + icm_mapping_rsp_valid <= 'd0; + end + else begin + icm_mapping_rsp_valid <= icm_mapping_lookup_valid; + end +end + +//-- icm_mapping_rsp_phy_addr -- +assign icm_mapping_rsp_phy_addr = {mapping_doutb, icm_lookup_page_offset}; + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ + +/*------------------------------------------- Local Macros Undef : Begin --------------------------------------------*/ +/*------------------------------------------- Local Macros Undef : End ----------------------------------------------*/ + +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/ICMMgt/ICMCache/ICMSetDelProc/ICMSetDelProc.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/ICMMgt/ICMCache/ICMSetDelProc/ICMSetDelProc.v new file mode 100644 index 0000000000000000000000000000000000000000..351f4d5bf510ba958da9989ae8a9a282899f541f --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/ICMMgt/ICMCache/ICMSetDelProc/ICMSetDelProc.v @@ -0,0 +1,238 @@ +/*------------------------------------------- Module Description : Begin ---------------------------------------------- +Name: ICMSetDel +Author: YangFan +Function: Handle ICM Set/Del Request. +--------------------------------------------- Module Decription : End -----------------------------------------------*/ + +/*------------------------------------------- Timescale Definition : Begin ------------------------------------------*/ +`timescale 1ns / 1ps +/*------------------------------------------- Timescale Definition : End --------------------------------------------*/ + +/*------------------------------------------- Included Files : Begin ------------------------------------------------*/ +`include "protocol_engine_def.vh" +/*------------------------------------------- Included Files : End --------------------------------------------------*/ + +/*------------------------------------------- Input/Output Definition : Begin ---------------------------------------*/ +module ICMSetDelProc +#( + parameter ICM_CACHE_TYPE = `CACHE_TYPE_MTT, + parameter ICM_PAGE_NUM = `ICM_PAGE_NUM_MTT, + parameter ICM_PAGE_NUM_LOG = log2b(ICM_PAGE_NUM - 1), + parameter ICM_ENTRY_NUM = `ICM_ENTRY_NUM_MTT, + parameter ICM_ENTRY_NUM_LOG = log2b(ICM_ENTRY_NUM - 1), + parameter ICM_SLOT_SIZE = `ICM_SLOT_SIZE_MTT, + parameter ICM_ADDR_WIDTH = 64, + + parameter CACHE_ADDR_WIDTH = log2b(ICM_ENTRY_NUM * ICM_SLOT_SIZE - 1), + parameter CACHE_ENTRY_WIDTH = 256, + parameter CACHE_SET_NUM = 1024, + parameter CACHE_SET_NUM_LOG = log2b(CACHE_SET_NUM - 1), + parameter CACHE_OFFSET_WIDTH = log2b(ICM_SLOT_SIZE - 1), + parameter CACHE_TAG_WIDTH = CACHE_ADDR_WIDTH - CACHE_OFFSET_WIDTH - CACHE_SET_NUM_LOG, + parameter PHYSICAL_ADDR_WIDTH = `PHY_SPACE_ADDR_WIDTH, + parameter COUNT_MAX = 2, + parameter COUNT_MAX_LOG = log2b(COUNT_MAX - 1) + 1, + parameter REQ_TAG_NUM = 32, + parameter REQ_TAG_NUM_LOG = log2b(REQ_TAG_NUM - 1), + parameter REORDER_BUFFER_WIDTH = (ICM_CACHE_TYPE == `CACHE_TYPE_MTT) ? CACHE_ENTRY_WIDTH * 2 + COUNT_MAX_LOG : CACHE_ENTRY_WIDTH + COUNT_MAX_LOG +) +( + input wire clk, + input wire rst, + +//Interface for ICMGetProc to update cache entry + input wire set_req_valid_chnl_0, + input wire [`REQ_TAG_NUM_LOG + `COUNT_MAX_LOG * 2 + PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH - 1 : 0] set_req_head_chnl_0, + input wire [CACHE_ENTRY_WIDTH - 1 : 0] set_req_data_chnl_0, + output wire set_req_ready_chnl_0, + +//Interface for SWAccCM/MRCtl to set cache entry + input wire set_req_valid_chnl_1, + input wire [`REQ_TAG_NUM_LOG + `COUNT_MAX_LOG * 2 + PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH - 1 : 0] set_req_head_chnl_1, + input wire [CACHE_ENTRY_WIDTH - 1 : 0] set_req_data_chnl_1, + output wire set_req_ready_chnl_1, + +//Interface for SWAccCM/MRCtl to invalidate cache entry + input wire del_req_valid, + input wire [ICM_ADDR_WIDTH - 1 : 0] del_req_head, + output wire del_req_ready, + +//ICMBuffer Set Req Interface + output wire cache_set_req_valid, + output wire [ICM_ADDR_WIDTH - 1 : 0] cache_set_req_head, + output wire [CACHE_ENTRY_WIDTH - 1 : 0] cache_set_req_data, + input wire cache_set_req_ready, + +//ICMBuffer Del Req Interface + output wire cache_del_req_valid, + output wire [ICM_ADDR_WIDTH - 1 : 0] cache_del_req_head, + input wire cache_del_req_ready, + +//Interface with DMA + output wire dma_wr_req_valid, + output wire [`DMA_HEAD_WIDTH - 1 : 0] dma_wr_req_head, + output wire [`DMA_DATA_WIDTH - 1 : 0] dma_wr_req_data, + output wire dma_wr_req_last, + input wire dma_wr_req_ready +); +/*------------------------------------------- Input/Output Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Macros Definition : Begin ---------------------------------------*/ +`define CHNL_0 0 +`define CHNL_1 1 + +`define DMA_ADDR_OFFSET 127:64 +/*------------------------------------------- Local Macros Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Variables Definition : Begin ------------------------------------*/ +reg last_scheduled_chnl; + +reg [31:0] dma_len; +reg [63:0] dma_addr; + +reg [CACHE_ENTRY_WIDTH - 1 : 0] set_req_data_chnl_1_diff; +/*------------------------------------------- Local Variables Definition : End --------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : Begin ---------------------------------------*/ +/*------------------------------------------- Submodules Instatiation : End -----------------------------------------*/ + +/*------------------------------------------- State Machine Definition : Begin --------------------------------------*/ +reg [2:0] cur_state; +reg [2:0] next_state; + +parameter [2:0] IDLE_s = 3'd1, + CHNL_0_s = 3'd2, + CHNL_1_s = 3'd3, + WT_s = 3'd4; //Cache Write Through + +always @(posedge clk or posedge rst) begin + if (rst) begin + cur_state <= IDLE_s; + end + else begin + cur_state <= next_state; + end +end + +always @(*) begin + case(cur_state) + IDLE_s: if(set_req_valid_chnl_0 && last_scheduled_chnl == `CHNL_1) begin + next_state = CHNL_0_s; + end + else if(set_req_valid_chnl_0 && !set_req_valid_chnl_1) begin + next_state = CHNL_0_s; + end + else if(set_req_valid_chnl_1 && last_scheduled_chnl == `CHNL_0) begin + next_state = CHNL_1_s; + end + else if(set_req_valid_chnl_1 && !set_req_valid_chnl_0) begin + next_state = CHNL_1_s; + end + else begin + next_state = IDLE_s; + end + CHNL_0_s: if(cache_set_req_valid && cache_set_req_ready) begin + next_state = IDLE_s; + end + else begin + next_state = CHNL_0_s; + end + CHNL_1_s: if(cache_set_req_valid && cache_set_req_ready) begin + next_state = WT_s; + end + else begin + next_state = CHNL_1_s; + end + WT_s: if(dma_wr_req_valid && dma_wr_req_ready) begin + next_state = IDLE_s; + end + else begin + next_state = WT_s; + end + default: next_state = IDLE_s; + endcase +end + +/*------------------------------------------- State Machine Definition : End ----------------------------------------*/ + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ +//-- last_scheduled_chnl -- +always @(posedge clk or posedge rst) begin + if (rst) begin + last_scheduled_chnl <= 'd0; + end + else if (cur_state == CHNL_0_s) begin + last_scheduled_chnl <= `CHNL_0; + end + else if (cur_state == CHNL_1_s) begin + last_scheduled_chnl <= `CHNL_1; + end + else begin + last_scheduled_chnl <= last_scheduled_chnl; + end +end + +//-- set_req_ready_chnl_0 -- +assign set_req_ready_chnl_0 = (cur_state == CHNL_0_s) ? cache_set_req_ready : 'd0; + +//-- set_req_ready_chnl_1 -- +assign set_req_ready_chnl_1 = (cur_state == CHNL_1_s) ? cache_set_req_ready : 'd0; + +//-- del_req_ready -- +assign del_req_ready = cache_del_req_ready; + +//-- cache_set_req_valid -- +//-- cache_set_req_head -- +//-- cache_set_req_data -- +assign cache_set_req_valid = (cur_state == CHNL_0_s) ? set_req_valid_chnl_0 : + (cur_state == CHNL_1_s) ? set_req_valid_chnl_1 : 'd0; +assign cache_set_req_head = (cur_state == CHNL_0_s) ? set_req_head_chnl_0[CACHE_ADDR_WIDTH - 1 : 0] : + (cur_state == CHNL_1_s) ? set_req_head_chnl_1[CACHE_ADDR_WIDTH - 1 : 0] : 'd0; +assign cache_set_req_data = (cur_state == CHNL_0_s) ? set_req_data_chnl_0 : + (cur_state == CHNL_1_s) ? set_req_data_chnl_1 : 'd0; + +//-- cache_del_req_valid -- +//-- cache_del_req_head -- +assign cache_del_req_valid = del_req_valid; +assign cache_del_req_head = del_req_head; + +//-- dma_len -- +//-- dma_addr -- +//-- set_req_data_chnl_1_diff -- +always @(posedge clk or posedge rst) begin + if (rst) begin + dma_len <= 'd0; + dma_addr <= 'd0; + set_req_data_chnl_1_diff <= 'd0; + end + else if (cur_state == CHNL_1_s) begin + dma_len <= CACHE_ENTRY_WIDTH / 8; + dma_addr <= set_req_head_chnl_1[`DMA_ADDR_OFFSET]; + set_req_data_chnl_1_diff <= set_req_data_chnl_1; + end + else begin + dma_len <= dma_len; + dma_addr <= dma_addr; + set_req_data_chnl_1_diff <= set_req_data_chnl_1_diff; + end +end + +//-- dma_wr_req_valid -- +//-- dma_wr_req_head -- +//-- dma_wr_req_data -- +//-- dma_wr_req_last -- +assign dma_wr_req_valid = (cur_state == WT_s) ? 'd1 : 'd0; +assign dma_wr_req_head = (cur_state == WT_s) ? {32'd0, dma_addr, dma_len} : 'd0; +assign dma_wr_req_data= (cur_state == WT_s) ? set_req_data_chnl_1_diff : 'd0; +assign dma_wr_req_last = (cur_state == WT_s) ? 'd1 : 'd0; + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ + +/*------------------------------------------- Local Macros Undef : Begin --------------------------------------------*/ +`undef CHNL_0 +`undef CHNL_1 + +`undef DMA_ADDR_OFFSET +/*------------------------------------------- Local Macros Undef : End ----------------------------------------------*/ + +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/ICMMgt/ICMMgt.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/ICMMgt/ICMMgt.v new file mode 100644 index 0000000000000000000000000000000000000000..c671117f909d625daca20d3d86526a1427731c19 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/ICMMgt/ICMMgt.v @@ -0,0 +1,461 @@ +/*------------------------------------------- Module Description : Begin ---------------------------------------------- +Name: ICMMgt +Author: YangFan +Function: Manage ICM Data and Provides ICM Access Interface. +--------------------------------------------- Module Decription : End -----------------------------------------------*/ + +/*------------------------------------------- Timescale Definition : Begin ------------------------------------------*/ +`timescale 1ns / 1ps +/*------------------------------------------- Timescale Definition : End --------------------------------------------*/ + +/*------------------------------------------- Included Files : Begin ------------------------------------------------*/ +`include "protocol_engine_def.vh" +/*------------------------------------------- Included Files : End --------------------------------------------------*/ + +/*------------------------------------------- Input/Output Definition : Begin ---------------------------------------*/ +module ICMMgt +( + input wire clk, + input wire rst, + +//CEU Request + input wire ceu_cxt_req_valid, + input wire [`CEU_CXT_HEAD_WIDTH - 1 : 0] ceu_cxt_req_head, + input wire ceu_cxt_req_last, + input wire [`CEU_CXT_DATA_WIDTH - 1 : 0] ceu_cxt_req_data, + output wire ceu_cxt_req_ready, + +//CEU Response + output wire ceu_cxt_rsp_valid, + output wire [`CEU_CXT_HEAD_WIDTH - 1 : 0] ceu_cxt_rsp_head, + output wire ceu_cxt_rsp_last, + output wire [`CEU_CXT_DATA_WIDTH - 1 : 0] ceu_cxt_rsp_data, + input wire ceu_cxt_rsp_ready, + +//Request channels + input wire SQ_cxt_req_valid, + input wire [`CXT_CMD_HEAD_WIDTH + `MAX_REQ_TAG_NUM_LOG - 1 : 0] SQ_cxt_req_head, + input wire [`CXT_CMD_DATA_WIDTH - 1 : 0] SQ_cxt_req_data, + output wire SQ_cxt_req_ready, + + input wire TX_REQ_cxt_req_valid, + input wire [`CXT_CMD_HEAD_WIDTH + `MAX_REQ_TAG_NUM_LOG - 1 : 0] TX_REQ_cxt_req_head, + input wire [`CXT_CMD_DATA_WIDTH - 1 : 0] TX_REQ_cxt_req_data, + output wire TX_REQ_cxt_req_ready, + + input wire RX_REQ_cxt_req_valid, + input wire [`CXT_CMD_HEAD_WIDTH + `MAX_REQ_TAG_NUM_LOG - 1 : 0] RX_REQ_cxt_req_head, + input wire [`CXT_CMD_DATA_WIDTH - 1 : 0] RX_REQ_cxt_req_data, + output wire RX_REQ_cxt_req_ready, + + input wire RX_RESP_cxt_req_valid, + input wire [`CXT_CMD_HEAD_WIDTH + `MAX_REQ_TAG_NUM_LOG - 1 : 0] RX_RESP_cxt_req_head, + input wire [`CXT_CMD_DATA_WIDTH - 1 : 0] RX_RESP_cxt_req_data, + output wire RX_RESP_cxt_req_ready, + +//Response channels + output wire SQ_cxt_rsp_valid, + output wire [`CXT_RESP_HEAD_WIDTH + `MAX_REQ_TAG_NUM_LOG - 1 : 0] SQ_cxt_rsp_head, + output wire [`CXT_RESP_DATA_WIDTH - 1 : 0] SQ_cxt_rsp_data, + input wire SQ_cxt_rsp_ready, + + output wire TX_REQ_cxt_rsp_valid, + output wire [`CXT_RESP_HEAD_WIDTH + `MAX_REQ_TAG_NUM_LOG - 1 : 0] TX_REQ_cxt_rsp_head, + output wire [`CXT_RESP_DATA_WIDTH - 1 : 0] TX_REQ_cxt_rsp_data, + input wire TX_REQ_cxt_rsp_ready, + + output wire RX_REQ_cxt_rsp_valid, + output wire [`CXT_RESP_HEAD_WIDTH + `MAX_REQ_TAG_NUM_LOG - 1 : 0] RX_REQ_cxt_rsp_head, + output wire [`CXT_RESP_DATA_WIDTH - 1 : 0] RX_REQ_cxt_rsp_data, + input wire RX_REQ_cxt_rsp_ready, + + output wire RX_RESP_cxt_rsp_valid, + output wire [`CXT_RESP_HEAD_WIDTH + `MAX_REQ_TAG_NUM_LOG - 1 : 0] RX_RESP_cxt_rsp_head, + output wire [`CXT_RESP_DATA_WIDTH - 1 : 0] RX_RESP_cxt_rsp_data, + input wire RX_RESP_cxt_rsp_ready, + +//Interface with DMA + output wire qpc_dma_rd_req_valid, + output wire [`DMA_HEAD_WIDTH - 1 : 0] qpc_dma_rd_req_head, + output wire [`DMA_DATA_WIDTH - 1 : 0] qpc_dma_rd_req_data, + output wire qpc_dma_rd_req_last, + input wire qpc_dma_rd_req_ready, + + input wire qpc_dma_rd_rsp_valid, + input wire [`DMA_HEAD_WIDTH - 1 : 0] qpc_dma_rd_rsp_head, + input wire [`DMA_DATA_WIDTH - 1 : 0] qpc_dma_rd_rsp_data, + input wire qpc_dma_rd_rsp_last, + output wire qpc_dma_rd_rsp_ready, + + output wire qpc_dma_wr_req_valid, + output wire [`DMA_HEAD_WIDTH - 1 : 0] qpc_dma_wr_req_head, + output wire [`DMA_DATA_WIDTH - 1 : 0] qpc_dma_wr_req_data, + output wire qpc_dma_wr_req_last, + input wire qpc_dma_wr_req_ready, + + output wire cqc_dma_rd_req_valid, + output wire [`DMA_HEAD_WIDTH - 1 : 0] cqc_dma_rd_req_head, + output wire [`DMA_DATA_WIDTH - 1 : 0] cqc_dma_rd_req_data, + output wire cqc_dma_rd_req_last, + input wire cqc_dma_rd_req_ready, + + input wire cqc_dma_rd_rsp_valid, + input wire [`DMA_HEAD_WIDTH - 1 : 0] cqc_dma_rd_rsp_head, + input wire [`DMA_DATA_WIDTH - 1 : 0] cqc_dma_rd_rsp_data, + input wire cqc_dma_rd_rsp_last, + output wire cqc_dma_rd_rsp_ready, + + output wire cqc_dma_wr_req_valid, + output wire [`DMA_HEAD_WIDTH - 1 : 0] cqc_dma_wr_req_head, + output wire [`DMA_DATA_WIDTH - 1 : 0] cqc_dma_wr_req_data, + output wire cqc_dma_wr_req_last, + input wire cqc_dma_wr_req_ready, + + output wire eqc_dma_rd_req_valid, + output wire [`DMA_HEAD_WIDTH - 1 : 0] eqc_dma_rd_req_head, + output wire [`DMA_DATA_WIDTH - 1 : 0] eqc_dma_rd_req_data, + output wire eqc_dma_rd_req_last, + input wire eqc_dma_rd_req_ready, + + input wire eqc_dma_rd_rsp_valid, + input wire [`DMA_HEAD_WIDTH - 1 : 0] eqc_dma_rd_rsp_head, + input wire [`DMA_DATA_WIDTH - 1 : 0] eqc_dma_rd_rsp_data, + input wire eqc_dma_rd_rsp_last, + output wire eqc_dma_rd_rsp_ready, + + output wire eqc_dma_wr_req_valid, + output wire [`DMA_HEAD_WIDTH - 1 : 0] eqc_dma_wr_req_head, + output wire [`DMA_DATA_WIDTH - 1 : 0] eqc_dma_wr_req_data, + output wire eqc_dma_wr_req_last, + input wire eqc_dma_wr_req_ready, + +//Interface with CEU + input wire ceu_mr_req_valid, + input wire [`CEU_MR_HEAD_WIDTH - 1 : 0] ceu_mr_req_head, + input wire ceu_mr_req_last, + input wire [`CEU_MR_DATA_WIDTH - 1 : 0] ceu_mr_req_data, + output wire ceu_mr_req_ready, + +//Interface with SQMgt + input wire SQ_mr_req_valid, + input wire [`MR_CMD_HEAD_WIDTH + `MAX_REQ_TAG_NUM_LOG - 1 : 0] SQ_mr_req_head, + input wire [`MR_CMD_DATA_WIDTH - 1 : 0] SQ_mr_req_data, + output wire SQ_mr_req_ready, + + output wire SQ_mr_rsp_valid, + output wire [`MR_CMD_HEAD_WIDTH + `MAX_REQ_TAG_NUM_LOG - 1 : 0] SQ_mr_rsp_head, + output wire [`MR_CMD_DATA_WIDTH - 1 : 0] SQ_mr_rsp_data, + input wire SQ_mr_rsp_ready, + +//INterface with RQMgt + input wire RQ_mr_req_valid, + input wire [`MR_CMD_HEAD_WIDTH + `MAX_REQ_TAG_NUM_LOG - 1 : 0] RQ_mr_req_head, + input wire [`MR_CMD_DATA_WIDTH - 1 : 0] RQ_mr_req_data, + output wire RQ_mr_req_ready, + + output wire RQ_mr_rsp_valid, + output wire [`MR_CMD_HEAD_WIDTH + `MAX_REQ_TAG_NUM_LOG - 1 : 0] RQ_mr_rsp_head, + output wire [`MR_CMD_DATA_WIDTH - 1 : 0] RQ_mr_rsp_data, + input wire RQ_mr_rsp_ready, + +//Interface with RDMACore/ReqTransCore + input wire TX_REQ_mr_req_valid, + input wire [`MR_CMD_HEAD_WIDTH + `MAX_REQ_TAG_NUM_LOG - 1 : 0] TX_REQ_mr_req_head, + input wire [`MR_CMD_DATA_WIDTH - 1 : 0] TX_REQ_mr_req_data, + output wire TX_REQ_mr_req_ready, + + output wire TX_REQ_mr_rsp_valid, + output wire [`MR_CMD_HEAD_WIDTH + `MAX_REQ_TAG_NUM_LOG - 1 : 0] TX_REQ_mr_rsp_head, + output wire [`MR_CMD_DATA_WIDTH - 1 : 0] TX_REQ_mr_rsp_data, + input wire TX_REQ_mr_rsp_ready, + +//Interface with RDMACore/ReqRecvCore + input wire RX_REQ_mr_req_valid, + input wire [`MR_CMD_HEAD_WIDTH + `MAX_REQ_TAG_NUM_LOG - 1 : 0] RX_REQ_mr_req_head, + input wire [`MR_CMD_DATA_WIDTH - 1 : 0] RX_REQ_mr_req_data, + output wire RX_REQ_mr_req_ready, + + output wire RX_REQ_mr_rsp_valid, + output wire [`MR_CMD_HEAD_WIDTH + `MAX_REQ_TAG_NUM_LOG - 1 : 0] RX_REQ_mr_rsp_head, + output wire [`MR_CMD_DATA_WIDTH - 1 : 0] RX_REQ_mr_rsp_data, + input wire RX_REQ_mr_rsp_ready, + +//Interface with RDMACore/RespRecvCore + input wire RX_RESP_mr_req_valid, + input wire [`MR_CMD_HEAD_WIDTH + `MAX_REQ_TAG_NUM_LOG - 1 : 0] RX_RESP_mr_req_head, + input wire [`MR_CMD_DATA_WIDTH - 1 : 0] RX_RESP_mr_req_data, + output wire RX_RESP_mr_req_ready, + + output wire RX_RESP_mr_rsp_valid, + output wire [`MR_CMD_HEAD_WIDTH + `MAX_REQ_TAG_NUM_LOG - 1 : 0] RX_RESP_mr_rsp_head, + output wire [`MR_CMD_DATA_WIDTH - 1 : 0] RX_RESP_mr_rsp_data, + input wire RX_RESP_mr_rsp_ready, + +//Interface with DMA + output wire mpt_dma_rd_req_valid, + output wire [`DMA_HEAD_WIDTH - 1 : 0] mpt_dma_rd_req_head, + output wire [`DMA_DATA_WIDTH - 1 : 0] mpt_dma_rd_req_data, + output wire mpt_dma_rd_req_last, + input wire mpt_dma_rd_req_ready, + + input wire mpt_dma_rd_rsp_valid, + input wire [`DMA_HEAD_WIDTH - 1 : 0] mpt_dma_rd_rsp_head, + input wire [`DMA_DATA_WIDTH - 1 : 0] mpt_dma_rd_rsp_data, + input wire mpt_dma_rd_rsp_last, + output wire mpt_dma_rd_rsp_ready, + + output wire mpt_dma_wr_req_valid, + output wire [`DMA_HEAD_WIDTH - 1 : 0] mpt_dma_wr_req_head, + output wire [`DMA_DATA_WIDTH - 1 : 0] mpt_dma_wr_req_data, + output wire mpt_dma_wr_req_last, + input wire mpt_dma_wr_req_ready, + + output wire mtt_dma_rd_req_valid, + output wire [`DMA_HEAD_WIDTH - 1 : 0] mtt_dma_rd_req_head, + output wire [`DMA_DATA_WIDTH - 1 : 0] mtt_dma_rd_req_data, + output wire mtt_dma_rd_req_last, + input wire mtt_dma_rd_req_ready, + + input wire mtt_dma_rd_rsp_valid, + input wire [`DMA_HEAD_WIDTH - 1 : 0] mtt_dma_rd_rsp_head, + input wire [`DMA_DATA_WIDTH - 1 : 0] mtt_dma_rd_rsp_data, + input wire mtt_dma_rd_rsp_last, + output wire mtt_dma_rd_rsp_ready, + + output wire mtt_dma_wr_req_valid, + output wire [`DMA_HEAD_WIDTH - 1 : 0] mtt_dma_wr_req_head, + output wire [`DMA_DATA_WIDTH - 1 : 0] mtt_dma_wr_req_data, + output wire mtt_dma_wr_req_last, + input wire mtt_dma_wr_req_ready +); +/*------------------------------------------- Input/Output Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Macros Definition : Begin ---------------------------------------*/ + +/*------------------------------------------- Local Macros Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Variables Definition : Begin ------------------------------------*/ + +/*------------------------------------------- Local Variables Definition : End --------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : Begin ---------------------------------------*/ +CxtMgt CxtMgt_Inst( + .clk ( clk ), + .rst ( rst ), + + .ceu_req_valid ( ceu_cxt_req_valid ), + .ceu_req_head ( ceu_cxt_req_head ), + .ceu_req_last ( ceu_cxt_req_last ), + .ceu_req_data ( ceu_cxt_req_data ), + .ceu_req_ready ( ceu_cxt_req_ready ), + + .qpc_rsp_valid ( ceu_cxt_rsp_valid ), + .qpc_rsp_head ( ceu_cxt_rsp_head ), + .qpc_rsp_last ( ceu_cxt_rsp_last ), + .qpc_rsp_data ( ceu_cxt_rsp_data ), + .qpc_rsp_ready ( ceu_cxt_rsp_ready ), + + .SQ_cxt_req_valid ( SQ_cxt_req_valid ), + .SQ_cxt_req_head ( SQ_cxt_req_head ), + .SQ_cxt_req_data ( SQ_cxt_req_data ), + .SQ_cxt_req_ready ( SQ_cxt_req_ready ), + + .TX_REQ_cxt_req_valid ( TX_REQ_cxt_req_valid ), + .TX_REQ_cxt_req_head ( TX_REQ_cxt_req_head ), + .TX_REQ_cxt_req_data ( TX_REQ_cxt_req_data ), + .TX_REQ_cxt_req_ready ( TX_REQ_cxt_req_ready ), + + .RX_REQ_cxt_req_valid ( RX_REQ_cxt_req_valid ), + .RX_REQ_cxt_req_head ( RX_REQ_cxt_req_head ), + .RX_REQ_cxt_req_data ( RX_REQ_cxt_req_data ), + .RX_REQ_cxt_req_ready ( RX_REQ_cxt_req_ready ), + + .RX_RESP_cxt_req_valid ( RX_RESP_cxt_req_valid ), + .RX_RESP_cxt_req_head ( RX_RESP_cxt_req_head ), + .RX_RESP_cxt_req_data ( RX_RESP_cxt_req_data ), + .RX_RESP_cxt_req_ready ( RX_RESP_cxt_req_ready ), + + .SQ_cxt_rsp_valid ( SQ_cxt_rsp_valid ), + .SQ_cxt_rsp_head ( SQ_cxt_rsp_head ), + .SQ_cxt_rsp_data ( SQ_cxt_rsp_data ), + .SQ_cxt_rsp_ready ( SQ_cxt_rsp_ready ), + + .TX_REQ_cxt_rsp_valid ( TX_REQ_cxt_rsp_valid ), + .TX_REQ_cxt_rsp_head ( TX_REQ_cxt_rsp_head ), + .TX_REQ_cxt_rsp_data ( TX_REQ_cxt_rsp_data ), + .TX_REQ_cxt_rsp_ready ( TX_REQ_cxt_rsp_ready ), + + .RX_REQ_cxt_rsp_valid ( RX_REQ_cxt_rsp_valid ), + .RX_REQ_cxt_rsp_head ( RX_REQ_cxt_rsp_head ), + .RX_REQ_cxt_rsp_data ( RX_REQ_cxt_rsp_data ), + .RX_REQ_cxt_rsp_ready ( RX_REQ_cxt_rsp_ready ), + + .RX_RESP_cxt_rsp_valid ( RX_RESP_cxt_rsp_valid ), + .RX_RESP_cxt_rsp_head ( RX_RESP_cxt_rsp_head ), + .RX_RESP_cxt_rsp_data ( RX_RESP_cxt_rsp_data ), + .RX_RESP_cxt_rsp_ready ( RX_RESP_cxt_rsp_ready ), + + .qpc_dma_rd_req_valid ( qpc_dma_rd_req_valid ), + .qpc_dma_rd_req_head ( qpc_dma_rd_req_head ), + .qpc_dma_rd_req_data ( qpc_dma_rd_req_data ), + .qpc_dma_rd_req_last ( qpc_dma_rd_req_last ), + .qpc_dma_rd_req_ready ( qpc_dma_rd_req_ready ), + + .qpc_dma_rd_rsp_valid ( qpc_dma_rd_rsp_valid ), + .qpc_dma_rd_rsp_head ( qpc_dma_rd_rsp_head ), + .qpc_dma_rd_rsp_data ( qpc_dma_rd_rsp_data ), + .qpc_dma_rd_rsp_last ( qpc_dma_rd_rsp_last ), + .qpc_dma_rd_rsp_ready ( qpc_dma_rd_rsp_ready ), + + .qpc_dma_wr_req_valid ( qpc_dma_wr_req_valid ), + .qpc_dma_wr_req_head ( qpc_dma_wr_req_head ), + .qpc_dma_wr_req_data ( qpc_dma_wr_req_data ), + .qpc_dma_wr_req_last ( qpc_dma_wr_req_last ), + .qpc_dma_wr_req_ready ( qpc_dma_wr_req_ready ), + + .cqc_dma_rd_req_valid ( cqc_dma_rd_req_valid ), + .cqc_dma_rd_req_head ( cqc_dma_rd_req_head ), + .cqc_dma_rd_req_data ( cqc_dma_rd_req_data ), + .cqc_dma_rd_req_last ( cqc_dma_rd_req_last ), + .cqc_dma_rd_req_ready ( cqc_dma_rd_req_ready ), + + .cqc_dma_rd_rsp_valid ( cqc_dma_rd_rsp_valid ), + .cqc_dma_rd_rsp_head ( cqc_dma_rd_rsp_head ), + .cqc_dma_rd_rsp_data ( cqc_dma_rd_rsp_data ), + .cqc_dma_rd_rsp_last ( cqc_dma_rd_rsp_last ), + .cqc_dma_rd_rsp_ready ( cqc_dma_rd_rsp_ready ), + + .cqc_dma_wr_req_valid ( cqc_dma_wr_req_valid ), + .cqc_dma_wr_req_head ( cqc_dma_wr_req_head ), + .cqc_dma_wr_req_data ( cqc_dma_wr_req_data ), + .cqc_dma_wr_req_last ( cqc_dma_wr_req_last ), + .cqc_dma_wr_req_ready ( cqc_dma_wr_req_ready ), + + .eqc_dma_rd_req_valid ( eqc_dma_rd_req_valid ), + .eqc_dma_rd_req_head ( eqc_dma_rd_req_head ), + .eqc_dma_rd_req_data ( eqc_dma_rd_req_data ), + .eqc_dma_rd_req_last ( eqc_dma_rd_req_last ), + .eqc_dma_rd_req_ready ( eqc_dma_rd_req_ready ), + + .eqc_dma_rd_rsp_valid ( eqc_dma_rd_rsp_valid ), + .eqc_dma_rd_rsp_head ( eqc_dma_rd_rsp_head ), + .eqc_dma_rd_rsp_data ( eqc_dma_rd_rsp_data ), + .eqc_dma_rd_rsp_last ( eqc_dma_rd_rsp_last ), + .eqc_dma_rd_rsp_ready ( eqc_dma_rd_rsp_ready ), + + .eqc_dma_wr_req_valid ( eqc_dma_wr_req_valid ), + .eqc_dma_wr_req_head ( eqc_dma_wr_req_head ), + .eqc_dma_wr_req_data ( eqc_dma_wr_req_data ), + .eqc_dma_wr_req_last ( eqc_dma_wr_req_last ), + .eqc_dma_wr_req_ready ( eqc_dma_wr_req_ready ) +); + +MRMgt MRMgt_Inst ( + .clk ( clk ), + .rst ( rst ), + + .ceu_req_valid ( ceu_mr_req_valid ), + .ceu_req_head ( ceu_mr_req_head ), + .ceu_req_last ( ceu_mr_req_last ), + .ceu_req_data ( ceu_mr_req_data ), + .ceu_req_ready ( ceu_mr_req_ready ), + + .SQ_mr_req_valid ( SQ_mr_req_valid ), + .SQ_mr_req_head ( SQ_mr_req_head ), + .SQ_mr_req_data ( SQ_mr_req_data ), + .SQ_mr_req_ready ( SQ_mr_req_ready ), + + .SQ_mr_rsp_valid ( SQ_mr_rsp_valid ), + .SQ_mr_rsp_head ( SQ_mr_rsp_head ), + .SQ_mr_rsp_data ( SQ_mr_rsp_data ), + .SQ_mr_rsp_ready ( SQ_mr_rsp_ready ), + + .RQ_mr_req_valid ( RQ_mr_req_valid ), + .RQ_mr_req_head ( RQ_mr_req_head ), + .RQ_mr_req_data ( RQ_mr_req_data ), + .RQ_mr_req_ready ( RQ_mr_req_ready ), + + .RQ_mr_rsp_valid ( RQ_mr_rsp_valid ), + .RQ_mr_rsp_head ( RQ_mr_rsp_head ), + .RQ_mr_rsp_data ( RQ_mr_rsp_data ), + .RQ_mr_rsp_ready ( RQ_mr_rsp_ready ), + + .TX_REQ_mr_req_valid ( TX_REQ_mr_req_valid ), + .TX_REQ_mr_req_head ( TX_REQ_mr_req_head ), + .TX_REQ_mr_req_data ( TX_REQ_mr_req_data ), + .TX_REQ_mr_req_ready ( TX_REQ_mr_req_ready ), + + .TX_REQ_mr_rsp_valid ( TX_REQ_mr_rsp_valid ), + .TX_REQ_mr_rsp_head ( TX_REQ_mr_rsp_head ), + .TX_REQ_mr_rsp_data ( TX_REQ_mr_rsp_data ), + .TX_REQ_mr_rsp_ready ( TX_REQ_mr_rsp_ready ), + + .RX_REQ_mr_req_valid ( RX_REQ_mr_req_valid ), + .RX_REQ_mr_req_head ( RX_REQ_mr_req_head ), + .RX_REQ_mr_req_data ( RX_REQ_mr_req_data ), + .RX_REQ_mr_req_ready ( RX_REQ_mr_req_ready ), + + .RX_REQ_mr_rsp_valid ( RX_REQ_mr_rsp_valid ), + .RX_REQ_mr_rsp_head ( RX_REQ_mr_rsp_head ), + .RX_REQ_mr_rsp_data ( RX_REQ_mr_rsp_data ), + .RX_REQ_mr_rsp_ready ( RX_REQ_mr_rsp_ready ), + + .RX_RESP_mr_req_valid ( RX_RESP_mr_req_valid ), + .RX_RESP_mr_req_head ( RX_RESP_mr_req_head ), + .RX_RESP_mr_req_data ( RX_RESP_mr_req_data ), + .RX_RESP_mr_req_ready ( RX_RESP_mr_req_ready ), + + .RX_RESP_mr_rsp_valid ( RX_RESP_mr_rsp_valid ), + .RX_RESP_mr_rsp_head ( RX_RESP_mr_rsp_head ), + .RX_RESP_mr_rsp_data ( RX_RESP_mr_rsp_data ), + .RX_RESP_mr_rsp_ready ( RX_RESP_mr_rsp_ready ), + + .mpt_dma_rd_req_valid ( mpt_dma_rd_req_valid ), + .mpt_dma_rd_req_head ( mpt_dma_rd_req_head ), + .mpt_dma_rd_req_data ( mpt_dma_rd_req_data ), + .mpt_dma_rd_req_last ( mpt_dma_rd_req_last ), + .mpt_dma_rd_req_ready ( mpt_dma_rd_req_ready ), + + .mpt_dma_rd_rsp_valid ( mpt_dma_rd_rsp_valid ), + .mpt_dma_rd_rsp_head ( mpt_dma_rd_rsp_head ), + .mpt_dma_rd_rsp_data ( mpt_dma_rd_rsp_data ), + .mpt_dma_rd_rsp_last ( mpt_dma_rd_rsp_last ), + .mpt_dma_rd_rsp_ready ( mpt_dma_rd_rsp_ready ), + + .mpt_dma_wr_req_valid ( mpt_dma_wr_req_valid ), + .mpt_dma_wr_req_head ( mpt_dma_wr_req_head ), + .mpt_dma_wr_req_data ( mpt_dma_wr_req_data ), + .mpt_dma_wr_req_last ( mpt_dma_wr_req_last ), + .mpt_dma_wr_req_ready ( mpt_dma_wr_req_ready ), + + .mtt_dma_rd_req_valid ( mtt_dma_rd_req_valid ), + .mtt_dma_rd_req_head ( mtt_dma_rd_req_head ), + .mtt_dma_rd_req_data ( mtt_dma_rd_req_data ), + .mtt_dma_rd_req_last ( mtt_dma_rd_req_last ), + .mtt_dma_rd_req_ready ( mtt_dma_rd_req_ready ), + + .mtt_dma_rd_rsp_valid ( mtt_dma_rd_rsp_valid ), + .mtt_dma_rd_rsp_head ( mtt_dma_rd_rsp_head ), + .mtt_dma_rd_rsp_data ( mtt_dma_rd_rsp_data ), + .mtt_dma_rd_rsp_last ( mtt_dma_rd_rsp_last ), + .mtt_dma_rd_rsp_ready ( mtt_dma_rd_rsp_ready ), + + .mtt_dma_wr_req_valid ( mtt_dma_wr_req_valid ), + .mtt_dma_wr_req_head ( mtt_dma_wr_req_head ), + .mtt_dma_wr_req_data ( mtt_dma_wr_req_data ), + .mtt_dma_wr_req_last ( mtt_dma_wr_req_last ), + .mtt_dma_wr_req_ready ( mtt_dma_wr_req_ready ) +); +/*------------------------------------------- Submodules Instatiation : End -----------------------------------------*/ + +/*------------------------------------------- State Machine Definition : Begin --------------------------------------*/ +/*------------------------------------------- State Machine Definition : End ----------------------------------------*/ + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ + +/*------------------------------------------- Local Macros Undef : Begin --------------------------------------------*/ +/*------------------------------------------- Local Macros Undef : End ----------------------------------------------*/ + +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/ICMMgt/MRMgt/HWAccMRCtl/HWAccMRCtl.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/ICMMgt/MRMgt/HWAccMRCtl/HWAccMRCtl.v new file mode 100644 index 0000000000000000000000000000000000000000..625f503da5ed022a9237bba4156c87cfd4f2ff3c --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/ICMMgt/MRMgt/HWAccMRCtl/HWAccMRCtl.v @@ -0,0 +1,533 @@ +/*------------------------------------------- Module Description : Begin ---------------------------------------------- +Name: HWAccMRCtl +Author: YangFan +Function: Control Hardware to MRMgt Access. +--------------------------------------------- Module Decription : End -----------------------------------------------*/ + +/*------------------------------------------- Timescale Definition : Begin ------------------------------------------*/ +`timescale 1ns / 1ps +/*------------------------------------------- Timescale Definition : End --------------------------------------------*/ + +/*------------------------------------------- Included Files : Begin ------------------------------------------------*/ +`include "protocol_engine_def.vh" +/*------------------------------------------- Included Files : End --------------------------------------------------*/ + +/*------------------------------------------- Input/Output Definition : Begin ---------------------------------------*/ +module HWAccMRCtl +#( + parameter ICM_CACHE_TYPE = `CACHE_TYPE_MTT, + parameter ICM_PAGE_NUM = `ICM_PAGE_NUM_MTT, + parameter ICM_PAGE_NUM_LOG = log2b(ICM_PAGE_NUM - 1), + parameter ICM_ENTRY_NUM = `ICM_ENTRY_NUM_MTT, + parameter ICM_ENTRY_NUM_LOG = log2b(ICM_ENTRY_NUM - 1), + parameter ICM_SLOT_SIZE = `ICM_SLOT_SIZE_MTT, + parameter ICM_ADDR_WIDTH = 64, + + parameter CACHE_ADDR_WIDTH = ICM_ADDR_WIDTH, + parameter CACHE_ENTRY_WIDTH = 256, + parameter CACHE_SET_NUM = 1024, + parameter CACHE_SET_NUM_LOG = log2b(CACHE_SET_NUM - 1), + parameter CACHE_OFFSET_WIDTH = log2b(CACHE_ENTRY_WIDTH / 8 - 1), + parameter CACHE_TAG_WIDTH = CACHE_ADDR_WIDTH - CACHE_OFFSET_WIDTH - CACHE_SET_NUM_LOG, + parameter PHYSICAL_ADDR_WIDTH = 64, + parameter COUNT_MAX = 2, + parameter COUNT_MAX_LOG = log2b(COUNT_MAX - 1) + 1, + parameter REQ_TAG_NUM = `REQ_TAG_NUM, + parameter REQ_TAG_NUM_LOG = log2b(REQ_TAG_NUM - 1), + parameter REORDER_BUFFER_WIDTH = (ICM_CACHE_TYPE == `CACHE_TYPE_MTT) ? CACHE_ENTRY_WIDTH * 2 + COUNT_MAX_LOG : CACHE_ENTRY_WIDTH + COUNT_MAX_LOG +) +( + input wire clk, + input wire rst, + + //Interface with SQMgt + input wire SQ_mr_req_valid, + input wire [`MR_CMD_HEAD_WIDTH + `MAX_REQ_TAG_NUM_LOG - 1 : 0] SQ_mr_req_head, + input wire [`MR_CMD_DATA_WIDTH - 1 : 0] SQ_mr_req_data, + output wire SQ_mr_req_ready, + + output wire SQ_mr_rsp_valid, + output wire [`MR_RESP_HEAD_WIDTH + `MAX_REQ_TAG_NUM_LOG - 1 : 0] SQ_mr_rsp_head, + output wire [`MR_RESP_DATA_WIDTH - 1 : 0] SQ_mr_rsp_data, + input wire SQ_mr_rsp_ready, + + //INterface with RQMgt + input wire RQ_mr_req_valid, + input wire [`MR_CMD_HEAD_WIDTH + `MAX_REQ_TAG_NUM_LOG - 1 : 0] RQ_mr_req_head, + input wire [`MR_CMD_DATA_WIDTH - 1 : 0] RQ_mr_req_data, + output wire RQ_mr_req_ready, + + output wire RQ_mr_rsp_valid, + output wire [`MR_RESP_HEAD_WIDTH + `MAX_REQ_TAG_NUM_LOG - 1 : 0] RQ_mr_rsp_head, + output wire [`MR_RESP_DATA_WIDTH - 1 : 0] RQ_mr_rsp_data, + input wire RQ_mr_rsp_ready, + + //Interface with RDMACore/ReqTransCore + input wire TX_REQ_mr_req_valid, + input wire [`MR_CMD_HEAD_WIDTH + `MAX_REQ_TAG_NUM_LOG - 1 : 0] TX_REQ_mr_req_head, + input wire [`MR_CMD_DATA_WIDTH - 1 : 0] TX_REQ_mr_req_data, + output wire TX_REQ_mr_req_ready, + + output wire TX_REQ_mr_rsp_valid, + output wire [`MR_RESP_HEAD_WIDTH + `MAX_REQ_TAG_NUM_LOG - 1 : 0] TX_REQ_mr_rsp_head, + output wire [`MR_RESP_DATA_WIDTH - 1 : 0] TX_REQ_mr_rsp_data, + input wire TX_REQ_mr_rsp_ready, + + //Interface with RDMACore/ReqRecvCore + input wire RX_REQ_mr_req_valid, + input wire [`MR_CMD_HEAD_WIDTH + `MAX_REQ_TAG_NUM_LOG - 1 : 0] RX_REQ_mr_req_head, + input wire [`MR_CMD_DATA_WIDTH - 1 : 0] RX_REQ_mr_req_data, + output wire RX_REQ_mr_req_ready, + + output wire RX_REQ_mr_rsp_valid, + output wire [`MR_RESP_HEAD_WIDTH + `MAX_REQ_TAG_NUM_LOG - 1 : 0] RX_REQ_mr_rsp_head, + output wire [`MR_RESP_DATA_WIDTH - 1 : 0] RX_REQ_mr_rsp_data, + input wire RX_REQ_mr_rsp_ready, + + //Interface with RDMACore/RespRecvCore + input wire RX_RESP_mr_req_valid, + input wire [`MR_CMD_HEAD_WIDTH + `MAX_REQ_TAG_NUM_LOG - 1 : 0] RX_RESP_mr_req_head, + input wire [`MR_CMD_DATA_WIDTH - 1 : 0] RX_RESP_mr_req_data, + output wire RX_RESP_mr_req_ready, + + output wire RX_RESP_mr_rsp_valid, + output wire [`MR_RESP_HEAD_WIDTH + `MAX_REQ_TAG_NUM_LOG - 1 : 0] RX_RESP_mr_rsp_head, + output wire [`MR_RESP_DATA_WIDTH - 1 : 0] RX_RESP_mr_rsp_data, + input wire RX_RESP_mr_rsp_ready, + +//MPT Mapping Lookup Interface + output wire mpt_icm_mapping_lookup_valid, + output wire [log2b(`ICM_ENTRY_NUM_MPT - 1) - 1 : 0] mpt_icm_mapping_lookup_head, + input wire mpt_icm_mapping_lookup_ready, + + input wire mpt_icm_mapping_rsp_valid, + input wire [ICM_ADDR_WIDTH - 1 : 0] mpt_icm_mapping_rsp_icm_addr, + input wire [PHYSICAL_ADDR_WIDTH - 1 : 0] mpt_icm_mapping_rsp_phy_addr, + output wire mpt_icm_mapping_rsp_ready, + +//ICM Get Interface + output wire mpt_icm_get_req_valid, + output wire [COUNT_MAX_LOG * 2 + `MAX_REQ_TAG_NUM_LOG + PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH - 1 : 0] mpt_icm_get_req_head, + input wire mpt_icm_get_req_ready, + + input wire mpt_icm_get_rsp_valid, + input wire [COUNT_MAX_LOG * 2 + `MAX_REQ_TAG_NUM_LOG + PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH - 1 : 0] mpt_icm_get_rsp_head, + input wire [`CACHE_ENTRY_WIDTH_MPT - 1 : 0] mpt_icm_get_rsp_data, + output wire mpt_icm_get_rsp_ready, + +//MPT Mapping Lookup Interface + output wire mtt_icm_mapping_lookup_valid, + output wire [log2b(`ICM_ENTRY_NUM_MTT - 1) - 1 : 0] mtt_icm_mapping_lookup_head, + input wire mtt_icm_mapping_lookup_ready, + + input wire mtt_icm_mapping_rsp_valid, + input wire [ICM_ADDR_WIDTH - 1 : 0] mtt_icm_mapping_rsp_icm_addr, + input wire [PHYSICAL_ADDR_WIDTH - 1 : 0] mtt_icm_mapping_rsp_phy_addr, + output wire mtt_icm_mapping_rsp_ready, + +//ICM/MPT Get Interface + output wire mtt_icm_get_req_valid, + output wire [COUNT_MAX_LOG * 2 + `MAX_REQ_TAG_NUM_LOG + PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH - 1 : 0] mtt_icm_get_req_head, + input wire mtt_icm_get_req_ready, + + input wire mtt_icm_get_rsp_valid, + input wire [COUNT_MAX_LOG * 2 + `MAX_REQ_TAG_NUM_LOG + PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH - 1 : 0] mtt_icm_get_rsp_head, + input wire [`CACHE_ENTRY_WIDTH_MTT - 1 : 0] mtt_icm_get_rsp_data, + output wire mtt_icm_get_rsp_ready +); + +/*------------------------------------------- Input/Output Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Macros Definition : Begin ---------------------------------------*/ +/*------------------------------------------- Local Macros Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Variables Definition : Begin ------------------------------------*/ +wire tag_qpn_mapping_table_wea; +wire [`MAX_REQ_TAG_NUM_LOG - 1 : 0] tag_qpn_mapping_table_addra; +wire [`QP_NUM_LOG - 1 : 0] tag_qpn_mapping_table_dina; +wire [`MAX_REQ_TAG_NUM_LOG - 1 : 0] tag_qpn_mapping_table_addrb; +wire [`QP_NUM_LOG - 1 : 0] tag_qpn_mapping_table_doutb; + +wire mr_req_buffer_wea; +wire [`MAX_REQ_TAG_NUM_LOG - 1 : 0] mr_req_buffer_addra; +wire [`MR_CMD_HEAD_WIDTH + `MAX_REQ_TAG_NUM_LOG - 1 : 0] mr_req_buffer_dina; +wire [`MR_CMD_HEAD_WIDTH + `MAX_REQ_TAG_NUM_LOG - 1 : 0] mr_req_buffer_douta; + +wire mr_req_buffer_web; +wire [`MAX_REQ_TAG_NUM_LOG - 1 : 0] mr_req_buffer_addrb; +wire [`MR_CMD_HEAD_WIDTH + `MAX_REQ_TAG_NUM_LOG - 1 : 0] mr_req_buffer_dinb; +wire [`MR_CMD_HEAD_WIDTH + `MAX_REQ_TAG_NUM_LOG - 1 : 0] mr_req_buffer_doutb; + +wire page_offset_buffer_wea; +wire [`MAX_REQ_TAG_NUM_LOG - 1 : 0] page_offset_buffer_addra; +wire [32 + 12 - 1 : 0] page_offset_buffer_dina; +wire [32 + 12 - 1 : 0] page_offset_buffer_douta; + +wire page_offset_buffer_web; +wire [`MAX_REQ_TAG_NUM_LOG - 1 : 0] page_offset_buffer_addrb; +wire [32 + 12 - 1 : 0] page_offset_buffer_dinb; +wire [32 + 12 - 1 : 0] page_offset_buffer_doutb; + +wire mr_req_valid; +wire [`MR_CMD_HEAD_WIDTH + `MAX_REQ_TAG_NUM_LOG - 1 : 0] mr_req_head; +wire [`MR_CMD_DATA_WIDTH - 1 : 0] mr_req_data; +wire mr_req_ready; + +wire mr_rsp_valid; +wire [`MR_RESP_HEAD_WIDTH + `MAX_REQ_TAG_NUM_LOG - 1 : 0] mr_rsp_head; +wire [`MR_RESP_DATA_WIDTH - 1 : 0] mr_rsp_data; +wire mr_rsp_ready; +/*------------------------------------------- Local Variables Definition : End --------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : Begin ---------------------------------------*/ +HWAccMRCtl_Thread_1 +#( + .ICM_CACHE_TYPE ( ICM_CACHE_TYPE ), + .ICM_PAGE_NUM ( ICM_PAGE_NUM ), + .ICM_PAGE_NUM_LOG ( ICM_PAGE_NUM_LOG ), + .ICM_ENTRY_NUM ( ICM_ENTRY_NUM ), + .ICM_ENTRY_NUM_LOG ( ICM_ENTRY_NUM_LOG ), + .ICM_SLOT_SIZE ( ICM_SLOT_SIZE ), + .ICM_ADDR_WIDTH ( ICM_ADDR_WIDTH ), + + .CACHE_ADDR_WIDTH ( CACHE_ADDR_WIDTH ), + .CACHE_ENTRY_WIDTH ( CACHE_ENTRY_WIDTH ), + .CACHE_SET_NUM ( CACHE_SET_NUM ), + .CACHE_SET_NUM_LOG ( CACHE_SET_NUM_LOG ), + .CACHE_OFFSET_WIDTH ( CACHE_OFFSET_WIDTH ), + .CACHE_TAG_WIDTH ( CACHE_TAG_WIDTH ), + .PHYSICAL_ADDR_WIDTH ( PHYSICAL_ADDR_WIDTH ), + .COUNT_MAX ( COUNT_MAX ), + .COUNT_MAX_LOG ( COUNT_MAX_LOG ), + .REQ_TAG_NUM ( REQ_TAG_NUM ), + .REQ_TAG_NUM_LOG ( REQ_TAG_NUM_LOG ), + .REORDER_BUFFER_WIDTH ( REORDER_BUFFER_WIDTH ) +) +HWAccMRCtl_Thread_1_Inst +( + .clk ( clk ), + .rst ( rst ), + + .SQ_mr_req_valid ( SQ_mr_req_valid ), + .SQ_mr_req_head ( SQ_mr_req_head ), + .SQ_mr_req_data ( SQ_mr_req_data ), + .SQ_mr_req_ready ( SQ_mr_req_ready ), + + + .RQ_mr_req_valid ( RQ_mr_req_valid ), + .RQ_mr_req_head ( RQ_mr_req_head ), + .RQ_mr_req_data ( RQ_mr_req_data ), + .RQ_mr_req_ready ( RQ_mr_req_ready ), + + + .TX_REQ_mr_req_valid ( TX_REQ_mr_req_valid ), + .TX_REQ_mr_req_head ( TX_REQ_mr_req_head ), + .TX_REQ_mr_req_data ( TX_REQ_mr_req_data ), + .TX_REQ_mr_req_ready ( TX_REQ_mr_req_ready ), + + + .RX_REQ_mr_req_valid ( RX_REQ_mr_req_valid ), + .RX_REQ_mr_req_head ( RX_REQ_mr_req_head ), + .RX_REQ_mr_req_data ( RX_REQ_mr_req_data ), + .RX_REQ_mr_req_ready ( RX_REQ_mr_req_ready ), + + + .RX_RESP_mr_req_valid ( RX_RESP_mr_req_valid ), + .RX_RESP_mr_req_head ( RX_RESP_mr_req_head ), + .RX_RESP_mr_req_data ( RX_RESP_mr_req_data ), + .RX_RESP_mr_req_ready ( RX_RESP_mr_req_ready ), + + .mr_req_valid ( mr_req_valid ), + .mr_req_head ( mr_req_head ), + .mr_req_data ( mr_req_data ), + .mr_req_ready ( mr_req_ready ), + + .tag_qpn_mapping_table_wen ( tag_qpn_mapping_table_wea ), + .tag_qpn_mapping_table_addr ( tag_qpn_mapping_table_addra ), + .tag_qpn_mapping_table_din ( tag_qpn_mapping_table_dina ) +); + +HWAccMRCtl_Thread_2 +#( + .ICM_CACHE_TYPE ( ICM_CACHE_TYPE ), + .ICM_PAGE_NUM ( ICM_PAGE_NUM ), + .ICM_PAGE_NUM_LOG ( ICM_PAGE_NUM_LOG ), + .ICM_ENTRY_NUM ( `ICM_ENTRY_NUM_MPT ), + + .ICM_SLOT_SIZE ( ICM_SLOT_SIZE ), + .ICM_ADDR_WIDTH ( ICM_ADDR_WIDTH ), + + .CACHE_ADDR_WIDTH ( CACHE_ADDR_WIDTH ), + .CACHE_ENTRY_WIDTH ( `CACHE_ENTRY_WIDTH_MPT ), + .CACHE_SET_NUM ( CACHE_SET_NUM ), + .CACHE_SET_NUM_LOG ( CACHE_SET_NUM_LOG ), + .CACHE_OFFSET_WIDTH ( CACHE_OFFSET_WIDTH ), + .CACHE_TAG_WIDTH ( CACHE_TAG_WIDTH ), + .PHYSICAL_ADDR_WIDTH ( PHYSICAL_ADDR_WIDTH ), + .COUNT_MAX ( COUNT_MAX ), + .COUNT_MAX_LOG ( COUNT_MAX_LOG ), + .REQ_TAG_NUM ( REQ_TAG_NUM ), + .REQ_TAG_NUM_LOG ( REQ_TAG_NUM_LOG ), + .REORDER_BUFFER_WIDTH ( REORDER_BUFFER_WIDTH ) +) +HWAccMRCtl_Thread_2_Inst +( + .clk ( clk ), + .rst ( rst ), + + .mr_req_valid ( mr_req_valid ), + .mr_req_head ( mr_req_head ), + .mr_req_data ( mr_req_data ), + .mr_req_ready ( mr_req_ready ), + + .icm_mapping_lookup_valid ( mpt_icm_mapping_lookup_valid ), + .icm_mapping_lookup_head ( mpt_icm_mapping_lookup_head ), + .icm_mapping_lookup_ready ( mpt_icm_mapping_lookup_ready ), + + .icm_mapping_rsp_valid ( mpt_icm_mapping_rsp_valid ), + .icm_mapping_rsp_icm_addr ( mpt_icm_mapping_rsp_icm_addr ), + .icm_mapping_rsp_phy_addr ( mpt_icm_mapping_rsp_phy_addr ), + .icm_mapping_rsp_ready ( mpt_icm_mapping_rsp_ready ), + + .icm_get_req_valid ( mpt_icm_get_req_valid ), + .icm_get_req_head ( mpt_icm_get_req_head ), + .icm_get_req_ready ( mpt_icm_get_req_ready ), + + .mr_req_buffer_wen ( mr_req_buffer_wea ), + .mr_req_buffer_addr ( mr_req_buffer_addra ), + .mr_req_buffer_din ( mr_req_buffer_dina ), + .mr_req_buffer_dout ( mr_req_buffer_douta ) +); + +HWAccMRCtl_Thread_3 +#( + .ICM_CACHE_TYPE ( ICM_CACHE_TYPE ), + .ICM_PAGE_NUM ( ICM_PAGE_NUM ), + .ICM_PAGE_NUM_LOG ( ICM_PAGE_NUM_LOG ), + .ICM_ENTRY_NUM ( `ICM_ENTRY_NUM_MTT ), + .ICM_ENTRY_NUM_LOG ( ICM_ENTRY_NUM_LOG ), + .ICM_SLOT_SIZE ( ICM_SLOT_SIZE ), + .ICM_ADDR_WIDTH ( ICM_ADDR_WIDTH ), + + .CACHE_ADDR_WIDTH ( CACHE_ADDR_WIDTH ), + .CACHE_ENTRY_WIDTH ( `CACHE_ENTRY_WIDTH_MPT ), + .CACHE_SET_NUM ( CACHE_SET_NUM ), + .CACHE_SET_NUM_LOG ( CACHE_SET_NUM_LOG ), + .CACHE_OFFSET_WIDTH ( CACHE_OFFSET_WIDTH ), + .CACHE_TAG_WIDTH ( CACHE_TAG_WIDTH ), + .PHYSICAL_ADDR_WIDTH ( PHYSICAL_ADDR_WIDTH ), + .COUNT_MAX ( COUNT_MAX ), + .COUNT_MAX_LOG ( COUNT_MAX_LOG ), + .REQ_TAG_NUM ( REQ_TAG_NUM ), + .REQ_TAG_NUM_LOG ( REQ_TAG_NUM_LOG ), + .REORDER_BUFFER_WIDTH ( REORDER_BUFFER_WIDTH ) +) +HWAccMRCtl_Thread_3_Inst +( + .clk ( clk ), + .rst ( rst ), + + .mpt_get_rsp_valid ( mpt_icm_get_rsp_valid ), + .mpt_get_rsp_head ( mpt_icm_get_rsp_head ), + .mpt_get_rsp_data ( mpt_icm_get_rsp_data ), + .mpt_get_rsp_ready ( mpt_icm_get_rsp_ready ), + + .icm_mapping_lookup_valid ( mtt_icm_mapping_lookup_valid ), + .icm_mapping_lookup_head ( mtt_icm_mapping_lookup_head ), + .icm_mapping_lookup_ready ( mtt_icm_mapping_lookup_ready ), + + .icm_mapping_rsp_valid ( mtt_icm_mapping_rsp_valid ), + .icm_mapping_rsp_icm_addr ( mtt_icm_mapping_rsp_icm_addr ), + .icm_mapping_rsp_phy_addr ( mtt_icm_mapping_rsp_phy_addr ), + .icm_mapping_rsp_ready ( mtt_icm_mapping_rsp_ready ), + + .mtt_get_req_valid ( mtt_icm_get_req_valid ), + .mtt_get_req_head ( mtt_icm_get_req_head ), + .mtt_get_req_ready ( mtt_icm_get_req_ready ), + + .mr_req_buffer_wen ( mr_req_buffer_web ), + .mr_req_buffer_addr ( mr_req_buffer_addrb ), + .mr_req_buffer_din ( mr_req_buffer_dinb ), + .mr_req_buffer_dout ( mr_req_buffer_doutb ), + + .page_offset_buffer_wen ( page_offset_buffer_wea ), + .page_offset_buffer_addr ( page_offset_buffer_addra ), + .page_offset_buffer_din ( page_offset_buffer_dina ), + .page_offset_buffer_dout ( page_offset_buffer_douta ) +); + +HWAccMRCtl_Thread_4 +#( + .ICM_CACHE_TYPE ( ICM_CACHE_TYPE ), + .ICM_PAGE_NUM ( ICM_PAGE_NUM ), + .ICM_PAGE_NUM_LOG ( ICM_PAGE_NUM_LOG ), + .ICM_ENTRY_NUM ( ICM_ENTRY_NUM ), + .ICM_ENTRY_NUM_LOG ( ICM_ENTRY_NUM_LOG ), + .ICM_SLOT_SIZE ( ICM_SLOT_SIZE ), + .ICM_ADDR_WIDTH ( ICM_ADDR_WIDTH ), + + .CACHE_ADDR_WIDTH ( CACHE_ADDR_WIDTH ), + .CACHE_ENTRY_WIDTH ( `CACHE_ENTRY_WIDTH_MTT ), + .CACHE_SET_NUM ( CACHE_SET_NUM ), + .CACHE_SET_NUM_LOG ( CACHE_SET_NUM_LOG ), + .CACHE_OFFSET_WIDTH ( CACHE_OFFSET_WIDTH ), + .CACHE_TAG_WIDTH ( CACHE_TAG_WIDTH ), + .PHYSICAL_ADDR_WIDTH ( PHYSICAL_ADDR_WIDTH ), + .COUNT_MAX ( COUNT_MAX ), + .COUNT_MAX_LOG ( COUNT_MAX_LOG ), + .REQ_TAG_NUM ( REQ_TAG_NUM ), + .REQ_TAG_NUM_LOG ( REQ_TAG_NUM_LOG ), + .REORDER_BUFFER_WIDTH ( REORDER_BUFFER_WIDTH ) +) +HWAccMRCtl_Thread_4_Inst +( + .clk ( clk ), + .rst ( rst ), + + .mtt_get_rsp_valid ( mtt_icm_get_rsp_valid ), + .mtt_get_rsp_head ( mtt_icm_get_rsp_head ), + .mtt_get_rsp_data ( mtt_icm_get_rsp_data ), + .mtt_get_rsp_ready ( mtt_icm_get_rsp_ready ), + + .mr_rsp_valid ( mr_rsp_valid ), + .mr_rsp_head ( mr_rsp_head ), + .mr_rsp_data ( mr_rsp_data ), + .mr_rsp_ready ( mr_rsp_ready ), + + .page_offset_buffer_wen ( page_offset_buffer_web ), + .page_offset_buffer_addr ( page_offset_buffer_addrb ), + .page_offset_buffer_din ( page_offset_buffer_dinb ), + .page_offset_buffer_dout ( page_offset_buffer_doutb ) +); + +HWAccMRCtl_Thread_5 +#( + .ICM_CACHE_TYPE ( ICM_CACHE_TYPE ), + .ICM_PAGE_NUM ( ICM_PAGE_NUM ), + .ICM_PAGE_NUM_LOG ( ICM_PAGE_NUM_LOG ), + .ICM_ENTRY_NUM ( ICM_ENTRY_NUM ), + .ICM_ENTRY_NUM_LOG ( ICM_ENTRY_NUM_LOG ), + .ICM_SLOT_SIZE ( ICM_SLOT_SIZE ), + .ICM_ADDR_WIDTH ( ICM_ADDR_WIDTH ), + + .CACHE_ADDR_WIDTH ( CACHE_ADDR_WIDTH ), + .CACHE_ENTRY_WIDTH ( CACHE_ENTRY_WIDTH ), + .CACHE_SET_NUM ( CACHE_SET_NUM ), + .CACHE_SET_NUM_LOG ( CACHE_SET_NUM_LOG ), + .CACHE_OFFSET_WIDTH ( CACHE_OFFSET_WIDTH ), + .CACHE_TAG_WIDTH ( CACHE_TAG_WIDTH ), + .PHYSICAL_ADDR_WIDTH ( PHYSICAL_ADDR_WIDTH ), + .COUNT_MAX ( COUNT_MAX ), + .COUNT_MAX_LOG ( COUNT_MAX_LOG ), + .REQ_TAG_NUM ( REQ_TAG_NUM ), + .REQ_TAG_NUM_LOG ( REQ_TAG_NUM_LOG ), + .REORDER_BUFFER_WIDTH ( REORDER_BUFFER_WIDTH ) +) +HWAccMRCtl_Thread_5_Inst +( + .clk ( clk ), + .rst ( rst ), + + .mr_rsp_valid ( mr_rsp_valid ), + .mr_rsp_head ( mr_rsp_head ), + .mr_rsp_data ( mr_rsp_data ), + .mr_rsp_ready ( mr_rsp_ready ), + + .tag_qpn_mapping_table_addr ( tag_qpn_mapping_table_addrb ), + .tag_qpn_mapping_table_dout ( tag_qpn_mapping_table_doutb ), + + .SQ_mr_rsp_valid ( SQ_mr_rsp_valid ), + .SQ_mr_rsp_head ( SQ_mr_rsp_head ), + .SQ_mr_rsp_data ( SQ_mr_rsp_data ), + .SQ_mr_rsp_ready ( SQ_mr_rsp_ready ), + + .RQ_mr_rsp_valid ( RQ_mr_rsp_valid ), + .RQ_mr_rsp_head ( RQ_mr_rsp_head ), + .RQ_mr_rsp_data ( RQ_mr_rsp_data ), + .RQ_mr_rsp_ready ( RQ_mr_rsp_ready ), + + .TX_REQ_mr_rsp_valid ( TX_REQ_mr_rsp_valid ), + .TX_REQ_mr_rsp_head ( TX_REQ_mr_rsp_head ), + .TX_REQ_mr_rsp_data ( TX_REQ_mr_rsp_data ), + .TX_REQ_mr_rsp_ready ( TX_REQ_mr_rsp_ready ), + + .RX_REQ_mr_rsp_valid ( RX_REQ_mr_rsp_valid ), + .RX_REQ_mr_rsp_head ( RX_REQ_mr_rsp_head ), + .RX_REQ_mr_rsp_data ( RX_REQ_mr_rsp_data ), + .RX_REQ_mr_rsp_ready ( RX_REQ_mr_rsp_ready ), + + .RX_RESP_mr_rsp_valid ( RX_RESP_mr_rsp_valid ), + .RX_RESP_mr_rsp_head ( RX_RESP_mr_rsp_head ), + .RX_RESP_mr_rsp_data ( RX_RESP_mr_rsp_data ), + .RX_RESP_mr_rsp_ready ( RX_RESP_mr_rsp_ready ) +); + +SRAM_SDP_Template #( + .RAM_WIDTH ( `QP_NUM_LOG ), + .RAM_DEPTH ( 256 ) +) +ChannelQPNMappingTable_Inst +( + .clk ( clk ), + .rst ( rst ), + + .wea ( tag_qpn_mapping_table_wea ), + .addra ( tag_qpn_mapping_table_addra ), + .dina ( tag_qpn_mapping_table_dina ), + + .addrb ( tag_qpn_mapping_table_addrb ), + .doutb ( tag_qpn_mapping_table_doutb ) +); + +SRAM_TDP_Template #( + .RAM_WIDTH ( 192 ), + .RAM_DEPTH ( 256 ) +) +MRReqStagedBuffer +( + .clk ( clk ), + .rst ( rst ), + + .wea ( mr_req_buffer_wea ), + .addra ( mr_req_buffer_addra ), + .dina ( mr_req_buffer_dina ), + .douta ( mr_req_buffer_douta ), + + .web ( mr_req_buffer_web ), + .addrb ( mr_req_buffer_addrb ), + .dinb ( mr_req_buffer_dinb ), + .doutb ( mr_req_buffer_doutb ) +); + +SRAM_TDP_Template #( + .RAM_WIDTH ( 32 + 12 ), //Size + Page offset + .RAM_DEPTH ( 256 ) +) +PageOffsetStagedBuffer +( + .clk ( clk ), + .rst ( rst ), + + .wea ( page_offset_buffer_wea ), + .addra ( page_offset_buffer_addra ), + .dina ( page_offset_buffer_dina ), + .douta ( page_offset_buffer_douta ), + + .web ( page_offset_buffer_web ), + .addrb ( page_offset_buffer_addrb ), + .dinb ( page_offset_buffer_dinb ), + .doutb ( page_offset_buffer_doutb ) +); +/*------------------------------------------- Submodules Instatiation : End -----------------------------------------*/ + +/*------------------------------------------- State Machine Definition : Begin --------------------------------------*/ +/*------------------------------------------- State Machine Definition : End ----------------------------------------*/ + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ + +/*------------------------------------------- Local Macros Undef : Begin --------------------------------------------*/ +/*------------------------------------------- Local Macros Undef : End ----------------------------------------------*/ + +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/ICMMgt/MRMgt/HWAccMRCtl/HWAccMRCtl_Thread_1.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/ICMMgt/MRMgt/HWAccMRCtl/HWAccMRCtl_Thread_1.v new file mode 100644 index 0000000000000000000000000000000000000000..4956341e15a66403f16758b9cf27746a322c01ca --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/ICMMgt/MRMgt/HWAccMRCtl/HWAccMRCtl_Thread_1.v @@ -0,0 +1,347 @@ +/*------------------------------------------- Module Description : Begin ---------------------------------------------- +Name: HWAccMRCtl_Thread_1 +Author: YangFan +Function: Schedule MR requests from different channels. +--------------------------------------------- Module Decription : End -----------------------------------------------*/ + +/*------------------------------------------- Timescale Definition : Begin ------------------------------------------*/ +`timescale 1ns / 1ps +/*------------------------------------------- Timescale Definition : End --------------------------------------------*/ + +/*------------------------------------------- Included Files : Begin ------------------------------------------------*/ +`include "protocol_engine_def.vh" +/*------------------------------------------- Included Files : End --------------------------------------------------*/ + +/*------------------------------------------- Input/Output Definition : Begin ---------------------------------------*/ +module HWAccMRCtl_Thread_1 +#( + parameter ICM_CACHE_TYPE = `CACHE_TYPE_MTT, + parameter ICM_PAGE_NUM = `ICM_PAGE_NUM_MTT, + parameter ICM_PAGE_NUM_LOG = log2b(ICM_PAGE_NUM - 1), + parameter ICM_ENTRY_NUM = `ICM_ENTRY_NUM_MTT, + parameter ICM_ENTRY_NUM_LOG = log2b(ICM_ENTRY_NUM - 1), + parameter ICM_SLOT_SIZE = `ICM_SLOT_SIZE_MTT, + parameter ICM_ADDR_WIDTH = 64, + + parameter CACHE_ADDR_WIDTH = ICM_ADDR_WIDTH, + parameter CACHE_ENTRY_WIDTH = 256, + parameter CACHE_SET_NUM = 1024, + parameter CACHE_SET_NUM_LOG = log2b(CACHE_SET_NUM - 1), + parameter CACHE_OFFSET_WIDTH = log2b(CACHE_ENTRY_WIDTH / 8 - 1), + parameter CACHE_TAG_WIDTH = CACHE_ADDR_WIDTH - CACHE_OFFSET_WIDTH - CACHE_SET_NUM_LOG, + parameter PHYSICAL_ADDR_WIDTH = 64, + parameter COUNT_MAX = 2, + parameter COUNT_MAX_LOG = log2b(COUNT_MAX - 1) + 1, + parameter REQ_TAG_NUM = 32, + parameter REQ_TAG_NUM_LOG = log2b(REQ_TAG_NUM - 1), + parameter REORDER_BUFFER_WIDTH = (ICM_CACHE_TYPE == `CACHE_TYPE_MTT) ? CACHE_ENTRY_WIDTH * 2 + COUNT_MAX_LOG : CACHE_ENTRY_WIDTH + COUNT_MAX_LOG +) +( + input wire clk, + input wire rst, + + //Interface with SQMgt + input wire SQ_mr_req_valid, + input wire [`MR_CMD_HEAD_WIDTH + `MAX_REQ_TAG_NUM_LOG - 1 : 0] SQ_mr_req_head, + input wire [`MR_CMD_DATA_WIDTH - 1 : 0] SQ_mr_req_data, + output wire SQ_mr_req_ready, + + //INterface with RQMgt + input wire RQ_mr_req_valid, + input wire [`MR_CMD_HEAD_WIDTH + `MAX_REQ_TAG_NUM_LOG - 1 : 0] RQ_mr_req_head, + input wire [`MR_CMD_DATA_WIDTH - 1 : 0] RQ_mr_req_data, + output wire RQ_mr_req_ready, + + //Interface with RDMACore/ReqTransCore + input wire TX_REQ_mr_req_valid, + input wire [`MR_CMD_HEAD_WIDTH + `MAX_REQ_TAG_NUM_LOG - 1 : 0] TX_REQ_mr_req_head, + input wire [`MR_CMD_DATA_WIDTH - 1 : 0] TX_REQ_mr_req_data, + output wire TX_REQ_mr_req_ready, + + //Interface with RDMACore/ReqRecvCore + input wire RX_REQ_mr_req_valid, + input wire [`MR_CMD_HEAD_WIDTH + `MAX_REQ_TAG_NUM_LOG - 1 : 0] RX_REQ_mr_req_head, + input wire [`MR_CMD_DATA_WIDTH - 1 : 0] RX_REQ_mr_req_data, + output wire RX_REQ_mr_req_ready, + + //Interface with RDMACore/RespRecvCore + input wire RX_RESP_mr_req_valid, + input wire [`MR_CMD_HEAD_WIDTH + `MAX_REQ_TAG_NUM_LOG - 1 : 0] RX_RESP_mr_req_head, + input wire [`MR_CMD_DATA_WIDTH - 1 : 0] RX_RESP_mr_req_data, + output wire RX_RESP_mr_req_ready, + +//Interface with HWAccMRCtl_Thread_2 + output wire mr_req_valid, + output wire [`MR_CMD_HEAD_WIDTH + `MAX_REQ_TAG_NUM_LOG - 1 : 0] mr_req_head, + output wire [`MR_CMD_DATA_WIDTH - 1 : 0] mr_req_data, + input wire mr_req_ready, + +//Interface with TagQPNMappingTable + output wire tag_qpn_mapping_table_wen, + output wire [`MAX_REQ_TAG_NUM_LOG - 1 : 0] tag_qpn_mapping_table_addr, + output wire [`QP_NUM_LOG - 1 : 0] tag_qpn_mapping_table_din +); + +/*------------------------------------------- Local Macros Definition : Begin ---------------------------------------*/ +`define SQ_CHNL 0 +`define RQ_CHNL 1 +`define TX_REQ_CHNL 2 +`define RX_REQ_CHNL 3 +`define RX_RESP_CHNL 4 + +`define REQ_TAG_OFFSET REQ_TAG_NUM_LOG - 1 : 0 +/*------------------------------------------- Local Macros Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Variables Definition : Begin ------------------------------------*/ +reg [2:0] last_sch_chnl; + +wire [`MAX_REQ_TAG_NUM_LOG - 1 : 0] req_tag; +/*------------------------------------------- Local Variables Definition : End --------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : Begin ---------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : End -----------------------------------------*/ + +/*------------------------------------------- State Machine Definition : Begin --------------------------------------*/ +reg [3:0] cur_state; +reg [3:0] next_state; + +parameter [3:0] IDLE_s = 4'd1, + SQ_s = 4'd2, + RQ_s = 4'd3, + TX_REQ_s = 4'd4, + RX_REQ_s = 4'd5, + RX_RESP_s = 4'd6; + +always @(posedge clk or posedge rst) begin + if (rst) begin + cur_state <= IDLE_s; + end + else begin + cur_state <= next_state; + end +end + +always @(*) begin + case(cur_state) + IDLE_s: if(last_sch_chnl == `RX_RESP_CHNL) begin + if(SQ_mr_req_valid) begin + next_state = SQ_s; + end + else if(RQ_mr_req_valid) begin + next_state = RQ_s; + end + else if(TX_REQ_mr_req_valid) begin + next_state = TX_REQ_s; + end + else if(RX_REQ_mr_req_valid) begin + next_state = RX_REQ_s; + end + else if(RX_RESP_mr_req_valid) begin + next_state = RX_RESP_s; + end + else begin + next_state = IDLE_s; + end + end + else if(last_sch_chnl == `SQ_CHNL) begin + if(RQ_mr_req_valid) begin + next_state = RQ_s; + end + else if(TX_REQ_mr_req_valid) begin + next_state = TX_REQ_s; + end + else if(RX_REQ_mr_req_valid) begin + next_state = RX_REQ_s; + end + else if(RX_RESP_mr_req_valid) begin + next_state = RX_RESP_s; + end + else if(SQ_mr_req_valid) begin + next_state = SQ_s; + end + else begin + next_state = IDLE_s; + end + end + else if(last_sch_chnl == `RQ_CHNL) begin + if(SQ_mr_req_valid) begin + next_state = SQ_s; + end + else if(RQ_mr_req_valid) begin + next_state = RQ_s; + end + else if(TX_REQ_mr_req_valid) begin + next_state = TX_REQ_s; + end + else if(RX_REQ_mr_req_valid) begin + next_state = RX_REQ_s; + end + else if(RX_RESP_mr_req_valid) begin + next_state = RX_RESP_s; + end + else begin + next_state = IDLE_s; + end + end + else if(last_sch_chnl == `TX_REQ_CHNL) begin + if(RX_REQ_mr_req_valid) begin + next_state = RX_REQ_s; + end + else if(RX_RESP_mr_req_valid) begin + next_state = RX_RESP_s; + end + else if(SQ_mr_req_valid) begin + next_state = SQ_s; + end + else if(RQ_mr_req_valid) begin + next_state = RQ_s; + end + else if(TX_REQ_mr_req_valid) begin + next_state = TX_REQ_s; + end + else begin + next_state = IDLE_s; + end + end + else if(last_sch_chnl == `RX_REQ_CHNL) begin + if(RX_RESP_mr_req_valid) begin + next_state = RX_RESP_s; + end + else if(SQ_mr_req_valid) begin + next_state = SQ_s; + end + else if(RQ_mr_req_valid) begin + next_state = RQ_s; + end + else if(TX_REQ_mr_req_valid) begin + next_state = TX_REQ_s; + end + else if(RX_REQ_mr_req_valid) begin + next_state = RX_REQ_s; + end + else begin + next_state = IDLE_s; + end + end + else begin + next_state = IDLE_s; + end + SQ_s: if(mr_req_valid && mr_req_ready) begin + next_state = IDLE_s; + end + else begin + next_state = SQ_s; + end + RQ_s: if(mr_req_valid && mr_req_ready) begin + next_state = IDLE_s; + end + else begin + next_state = RQ_s; + end + TX_REQ_s: if(mr_req_valid && mr_req_ready) begin + next_state = IDLE_s; + end + else begin + next_state = TX_REQ_s; + end + RX_REQ_s: if(mr_req_valid && mr_req_ready) begin + next_state = IDLE_s; + end + else begin + next_state = RX_REQ_s; + end + RX_RESP_s: if(mr_req_valid && mr_req_ready) begin + next_state = IDLE_s; + end + else begin + next_state = RX_RESP_s; + end + default: next_state = IDLE_s; + endcase +end +/*------------------------------------------- State Machine Definition : End ----------------------------------------*/ + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ +//-- last_sch_chnl -- +always @(posedge clk or posedge rst) begin + if (rst) begin + last_sch_chnl <= `RX_RESP_CHNL; + end + else if (cur_state == SQ_s && mr_req_ready) begin + last_sch_chnl <= `SQ_CHNL; + end + else if (cur_state == RQ_s && mr_req_ready) begin + last_sch_chnl <= `RQ_CHNL; + end + else if (cur_state == TX_REQ_s && mr_req_ready) begin + last_sch_chnl <= `TX_REQ_CHNL; + end + else if (cur_state == RX_REQ_s && mr_req_ready) begin + last_sch_chnl <= `RX_REQ_CHNL; + end + else if (cur_state == RX_RESP_s && mr_req_ready) begin + last_sch_chnl <= `RX_RESP_CHNL; + end + else begin + last_sch_chnl <= last_sch_chnl; + end +end + +//-- SQ_mr_req_ready -- +assign SQ_mr_req_ready = (cur_state == SQ_s) ? mr_req_ready : 'd0; + +//-- RQ_mr_req_ready -- +assign RQ_mr_req_ready = (cur_state == RQ_s) ? mr_req_ready : 'd0; + +//-- TX_REQ_mr_req_ready -- +assign TX_REQ_mr_req_ready = (cur_state == TX_REQ_s) ? mr_req_ready : 'd0; + +//-- RX_REQ_mr_req_ready -- +assign RX_REQ_mr_req_ready = (cur_state == RX_REQ_s) ? mr_req_ready : 'd0; + +//-- RX_RESP_mr_req_ready -- +assign RX_RESP_mr_req_ready = (cur_state == RX_RESP_s) ? mr_req_ready : 'd0; + +//-- req_tag -- +assign req_tag = (cur_state == SQ_s) ? {'d0, 3'b000, SQ_mr_req_head[`REQ_TAG_OFFSET]} : + (cur_state == RQ_s) ? {'d0, 3'b001, RQ_mr_req_head[`REQ_TAG_OFFSET]} : + (cur_state == TX_REQ_s) ? {'d0, 3'b010, TX_REQ_mr_req_head[`REQ_TAG_OFFSET]} : + (cur_state == RX_REQ_s) ? {'d0, 3'b011, RX_REQ_mr_req_head[`REQ_TAG_OFFSET]} : + (cur_state == RX_RESP_s) ? {'d0, 3'b100, RX_RESP_mr_req_head[`REQ_TAG_OFFSET]} : 'd0; + +//-- mr_req_valid -- +//-- mr_req_head -- +//-- mr_req_data -- +assign mr_req_valid = (cur_state == SQ_s) ? 'd1: + (cur_state == RQ_s) ? 'd1: + (cur_state == TX_REQ_s) ? 'd1 : + (cur_state == RX_REQ_s) ? 'd1 : + (cur_state == RX_RESP_s) ? 'd1 : 'd0; +assign mr_req_head = (cur_state == SQ_s) ? {SQ_mr_req_head[`MR_CMD_HEAD_WIDTH + `MAX_REQ_TAG_NUM_LOG - 1 : `MAX_REQ_TAG_NUM_LOG], req_tag} : + (cur_state == RQ_s) ? {RQ_mr_req_head[`MR_CMD_HEAD_WIDTH + `MAX_REQ_TAG_NUM_LOG - 1 : `MAX_REQ_TAG_NUM_LOG], req_tag} : + (cur_state == TX_REQ_s) ? {TX_REQ_mr_req_head[`MR_CMD_HEAD_WIDTH + `MAX_REQ_TAG_NUM_LOG - 1 : `MAX_REQ_TAG_NUM_LOG], req_tag} : + (cur_state == RX_REQ_s) ? {RX_REQ_mr_req_head[`MR_CMD_HEAD_WIDTH + `MAX_REQ_TAG_NUM_LOG - 1 : `MAX_REQ_TAG_NUM_LOG], req_tag} : + (cur_state == RX_RESP_s) ? {RX_RESP_mr_req_head[`MR_CMD_HEAD_WIDTH + `MAX_REQ_TAG_NUM_LOG - 1 : `MAX_REQ_TAG_NUM_LOG], req_tag} : 'd0; +assign mr_req_data = (cur_state == SQ_s) ? SQ_mr_req_data : + (cur_state == RQ_s) ? RQ_mr_req_data : + (cur_state == TX_REQ_s) ? TX_REQ_mr_req_data : + (cur_state == RX_REQ_s) ? RX_REQ_mr_req_data : + (cur_state == RX_RESP_s) ? RX_RESP_mr_req_data : 'd0; + +//-- tag_qpn_mapping_table_wen -- +//-- tag_qpn_mapping_table_addr -- +//-- tag_qpn_mapping_table_din -- +assign tag_qpn_mapping_table_wen = (cur_state == SQ_s || cur_state == RQ_s || cur_state == TX_REQ_s || cur_state == RX_REQ_s || cur_state == RX_RESP_s) ? 'd1 : 'd0; +assign tag_qpn_mapping_table_addr = req_tag; +assign tag_qpn_mapping_table_din = (cur_state == SQ_s) ? SQ_mr_req_head[`QP_NUM_LOG + `MAX_REQ_TAG_NUM_LOG - 1 : `MAX_REQ_TAG_NUM_LOG] : + (cur_state == RQ_s) ? RQ_mr_req_head[`QP_NUM_LOG + `MAX_REQ_TAG_NUM_LOG - 1 : `MAX_REQ_TAG_NUM_LOG] : + (cur_state == TX_REQ_s) ? TX_REQ_mr_req_head[`QP_NUM_LOG + `MAX_REQ_TAG_NUM_LOG - 1 : `MAX_REQ_TAG_NUM_LOG] : + (cur_state == RX_REQ_s) ? RX_REQ_mr_req_head[`QP_NUM_LOG + `MAX_REQ_TAG_NUM_LOG - 1 : `MAX_REQ_TAG_NUM_LOG] : + (cur_state == RX_RESP_s) ? RX_RESP_mr_req_head[`QP_NUM_LOG + `MAX_REQ_TAG_NUM_LOG - 1 : `MAX_REQ_TAG_NUM_LOG] : 'd0; +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ + +/*------------------------------------------- Local Macros Undef : Begin --------------------------------------------*/ +/*------------------------------------------- Local Macros Undef : End ----------------------------------------------*/ + +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/ICMMgt/MRMgt/HWAccMRCtl/HWAccMRCtl_Thread_2.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/ICMMgt/MRMgt/HWAccMRCtl/HWAccMRCtl_Thread_2.v new file mode 100644 index 0000000000000000000000000000000000000000..2a72eeb8348cc147f7430a8379eb7ac421543ff0 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/ICMMgt/MRMgt/HWAccMRCtl/HWAccMRCtl_Thread_2.v @@ -0,0 +1,216 @@ +/*------------------------------------------- Module Description : Begin ---------------------------------------------- +Name: HWAccMRCtl_Thread_2 +Author: YangFan +Function: Generate MPT requests. +--------------------------------------------- Module Decription : End -----------------------------------------------*/ + +/*------------------------------------------- Timescale Definition : Begin ------------------------------------------*/ +`timescale 1ns / 1ps +/*------------------------------------------- Timescale Definition : End --------------------------------------------*/ + +/*------------------------------------------- Included Files : Begin ------------------------------------------------*/ +`include "protocol_engine_def.vh" +/*------------------------------------------- Included Files : End --------------------------------------------------*/ + +/*------------------------------------------- Input/Output Definition : Begin ---------------------------------------*/ +module HWAccMRCtl_Thread_2 +#( + parameter ICM_CACHE_TYPE = `CACHE_TYPE_MTT, + parameter ICM_PAGE_NUM = `ICM_PAGE_NUM_MTT, + parameter ICM_PAGE_NUM_LOG = log2b(ICM_PAGE_NUM - 1), + parameter ICM_ENTRY_NUM = `ICM_ENTRY_NUM_MTT, + parameter ICM_ENTRY_NUM_LOG = log2b(ICM_ENTRY_NUM - 1), + parameter ICM_SLOT_SIZE = `ICM_SLOT_SIZE_MTT, + parameter ICM_ADDR_WIDTH = 64, + + parameter CACHE_ADDR_WIDTH = ICM_ADDR_WIDTH, + parameter CACHE_ENTRY_WIDTH = 256, + parameter CACHE_SET_NUM = 1024, + parameter CACHE_SET_NUM_LOG = log2b(CACHE_SET_NUM - 1), + parameter CACHE_OFFSET_WIDTH = log2b(CACHE_ENTRY_WIDTH / 8 - 1), + parameter CACHE_TAG_WIDTH = CACHE_ADDR_WIDTH - CACHE_OFFSET_WIDTH - CACHE_SET_NUM_LOG, + parameter PHYSICAL_ADDR_WIDTH = 64, + parameter COUNT_MAX = 2, + parameter COUNT_MAX_LOG = log2b(COUNT_MAX - 1) + 1, + parameter REQ_TAG_NUM = 32, + parameter REQ_TAG_NUM_LOG = log2b(REQ_TAG_NUM - 1), + parameter REORDER_BUFFER_WIDTH = (ICM_CACHE_TYPE == `CACHE_TYPE_MTT) ? CACHE_ENTRY_WIDTH * 2 + COUNT_MAX_LOG : CACHE_ENTRY_WIDTH + COUNT_MAX_LOG +) +( + input wire clk, + input wire rst, + +//ICM Get Req Interface + input wire mr_req_valid, + input wire [`MR_CMD_HEAD_WIDTH + `MAX_REQ_TAG_NUM_LOG - 1 : 0] mr_req_head, + input wire [`MR_CMD_DATA_WIDTH - 1 : 0] mr_req_data, + output wire mr_req_ready, + +//Mapping Lookup Interface + output wire icm_mapping_lookup_valid, + output wire [ICM_ENTRY_NUM_LOG - 1 : 0] icm_mapping_lookup_head, + input wire icm_mapping_lookup_ready, + + input wire icm_mapping_rsp_valid, + input wire [ICM_ADDR_WIDTH - 1 : 0] icm_mapping_rsp_icm_addr, + input wire [PHYSICAL_ADDR_WIDTH - 1 : 0] icm_mapping_rsp_phy_addr, + output wire icm_mapping_rsp_ready, + +//ICM Get Interface + output wire icm_get_req_valid, + output wire [COUNT_MAX_LOG * 2 + `MAX_REQ_TAG_NUM_LOG + PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH - 1 : 0] icm_get_req_head, + input wire icm_get_req_ready, + +//MR Req Buffer Interface + output wire mr_req_buffer_wen, + output wire [`MAX_REQ_TAG_NUM_LOG - 1 : 0] mr_req_buffer_addr, + output wire [`MR_CMD_HEAD_WIDTH - 1 : 0] mr_req_buffer_din, + input wire [`MR_CMD_HEAD_WIDTH - 1 : 0] mr_req_buffer_dout +); + +/*------------------------------------------- Input/Output Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Macros Definition : Begin ---------------------------------------*/ +`define MR_CMD_LKEY_OFFSET 95+8:64+8 +`define MR_CMD_TAG_OFFSET 7:0 +/*------------------------------------------- Local Macros Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Variables Definition : Begin ------------------------------------*/ +reg [`MR_CMD_HEAD_WIDTH + `MAX_REQ_TAG_NUM_LOG- 1 : 0] mr_req_head_diff; +reg [`MR_CMD_DATA_WIDTH - 1 : 0] mr_req_data_diff; + +wire [COUNT_MAX_LOG - 1 : 0] count_total; +wire [COUNT_MAX_LOG - 1 : 0] count_index; + +reg [`MAX_REQ_TAG_NUM_LOG - 1 : 0] req_tag; +reg [PHYSICAL_ADDR_WIDTH - 1 : 0] phy_addr; +reg [ICM_ADDR_WIDTH - 1 : 0] icm_addr; +/*------------------------------------------- Local Variables Definition : End --------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : Begin ---------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : End -----------------------------------------*/ + +/*------------------------------------------- State Machine Definition : Begin --------------------------------------*/ +reg [2:0] cur_state; +reg [2:0] next_state; + +parameter [2:0] IDLE_s = 3'd1, + ADDR_REQ_s = 3'd2, + ADDR_RSP_s = 3'd3, + MPT_GET_s = 3'd4; + +always @(posedge clk or posedge rst) begin + if(rst) begin + cur_state <= IDLE_s; + end + else begin + cur_state <= next_state; + end +end + +always @(*) begin + case(cur_state) + IDLE_s: if(mr_req_valid) begin + next_state = ADDR_REQ_s; + end + else begin + next_state = IDLE_s; + end + ADDR_REQ_s: if(icm_mapping_lookup_valid && icm_mapping_lookup_ready) begin + next_state = ADDR_RSP_s; + end + else begin + next_state = ADDR_REQ_s; + end + ADDR_RSP_s: if(icm_mapping_rsp_valid) begin + next_state = MPT_GET_s; + end + else begin + next_state = ADDR_RSP_s; + end + MPT_GET_s: if(icm_get_req_valid && icm_get_req_ready) begin + next_state = IDLE_s; + end + else begin + next_state = MPT_GET_s; + end + default: next_state = IDLE_s; + endcase +end +/*------------------------------------------- State Machine Definition : End ----------------------------------------*/ + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ +//-- mr_req_head_diff -- +//-- mr_req_data_diff -- +always @(posedge clk or posedge rst) begin + if(rst) begin + mr_req_head_diff <= 'd0; + mr_req_data_diff <= 'd0; + end + else if(cur_state == IDLE_s && mr_req_valid) begin + mr_req_head_diff <= mr_req_head; + mr_req_data_diff <= mr_req_data; + end + else begin + mr_req_head_diff <= mr_req_head_diff; + mr_req_data_diff <= mr_req_data_diff; + end +end + +//-- count_total -- +//-- count_index -- +assign count_total = {{(COUNT_MAX_LOG - 1){1'b0}}, 1'b1}; //For MPT Req, only one sub-req +assign count_index = {{(COUNT_MAX_LOG - 1){1'b0}}, 1'b0}; + +//-- mr_req_buffer_wen -- +//-- mr_req_buffer_addr -- +//-- mr_req_buffer_din -- +assign mr_req_buffer_wen = (cur_state == MPT_GET_s) ? 'd1 : 'd0; +assign mr_req_buffer_addr = (cur_state == MPT_GET_s) ? req_tag : 'd0; +assign mr_req_buffer_din = (cur_state == MPT_GET_s) ? mr_req_head_diff[`MR_CMD_HEAD_WIDTH + `MAX_REQ_TAG_NUM_LOG - 1 : `MAX_REQ_TAG_NUM_LOG] : 'd0; + +//-- req_tag -- +//-- phy_addr -- +//-- icm_addr -- +always @(posedge clk or posedge rst) begin + if (rst) begin + req_tag <= 'd0; + phy_addr <= 'd0; + icm_addr <= 'd0; + end + else if (cur_state == ADDR_RSP_s && icm_mapping_rsp_valid) begin + req_tag <= mr_req_head_diff[`MR_CMD_TAG_OFFSET]; + phy_addr <= icm_mapping_rsp_phy_addr; + icm_addr <= icm_mapping_rsp_icm_addr; + end + else begin + req_tag <= req_tag; + phy_addr <= phy_addr; + icm_addr <= icm_addr; + end +end + +//-- mr_req_ready -- +assign mr_req_ready = (cur_state == IDLE_s) ? 'd1 : 'd0; + +//-- icm_mapping_lookup_valid -- +//-- icm_mapping_lookup_head -- +assign icm_mapping_lookup_valid = (cur_state == ADDR_REQ_s) ? 'd1 : 'd0; +assign icm_mapping_lookup_head = (cur_state == ADDR_REQ_s) ? mr_req_head_diff[`MR_CMD_LKEY_OFFSET] : 'd0; + +//-- icm_get_req_valid -- +//-- icm_get_req_head -- +assign icm_get_req_valid = (cur_state == MPT_GET_s) ? 'd1 : 'd0; +assign icm_get_req_head = (cur_state == MPT_GET_s) ? {count_total, count_index, req_tag, phy_addr, icm_addr} : 'd0; + +// -- icm_mapping_rsp_ready -- +assign icm_mapping_rsp_ready = (cur_state == ADDR_RSP_s) ? 'd1 : 'd0; +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ + +/*------------------------------------------- Local Macros Undef : Begin --------------------------------------------*/ +`undef MR_CMD_LKEY_OFFSET +`undef MR_CMD_TAG_OFFSET +/*------------------------------------------- Local Macros Undef : End ----------------------------------------------*/ + +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/ICMMgt/MRMgt/HWAccMRCtl/HWAccMRCtl_Thread_3.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/ICMMgt/MRMgt/HWAccMRCtl/HWAccMRCtl_Thread_3.v new file mode 100644 index 0000000000000000000000000000000000000000..c0ea14ddd9d851cd67cc39754b271612fa3707ce --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/ICMMgt/MRMgt/HWAccMRCtl/HWAccMRCtl_Thread_3.v @@ -0,0 +1,403 @@ +/*------------------------------------------- Module Description : Begin ---------------------------------------------- +Name: HWAccMRCtl_Thread_3 +Author: YangFan +Function: Generate MTT requests. +--------------------------------------------- Module Decription : End -----------------------------------------------*/ + +/*------------------------------------------- Timescale Definition : Begin ------------------------------------------*/ +`timescale 1ns / 1ps +/*------------------------------------------- Timescale Definition : End --------------------------------------------*/ + +/*------------------------------------------- Included Files : Begin ------------------------------------------------*/ +`include "protocol_engine_def.vh" +/*------------------------------------------- Included Files : End --------------------------------------------------*/ + +/*------------------------------------------- Input/Output Definition : Begin ---------------------------------------*/ +module HWAccMRCtl_Thread_3 +#( + parameter ICM_CACHE_TYPE = `CACHE_TYPE_MTT, + parameter ICM_PAGE_NUM = `ICM_PAGE_NUM_MTT, + parameter ICM_PAGE_NUM_LOG = log2b(ICM_PAGE_NUM - 1), + parameter ICM_ENTRY_NUM = `ICM_ENTRY_NUM_MTT, + parameter ICM_ENTRY_NUM_LOG = log2b(ICM_ENTRY_NUM - 1), + parameter ICM_SLOT_SIZE = `ICM_SLOT_SIZE_MTT, + parameter ICM_ADDR_WIDTH = 64, + + parameter CACHE_ADDR_WIDTH = ICM_ADDR_WIDTH, + parameter CACHE_ENTRY_WIDTH = 256, + parameter CACHE_SET_NUM = 1024, + parameter CACHE_SET_NUM_LOG = log2b(CACHE_SET_NUM - 1), + parameter CACHE_OFFSET_WIDTH = log2b(CACHE_ENTRY_WIDTH / 8 - 1), + parameter CACHE_TAG_WIDTH = CACHE_ADDR_WIDTH - CACHE_OFFSET_WIDTH - CACHE_SET_NUM_LOG, + parameter PHYSICAL_ADDR_WIDTH = 64, + parameter COUNT_MAX = 2, + parameter COUNT_MAX_LOG = log2b(COUNT_MAX - 1) + 1, + parameter REQ_TAG_NUM = 32, + parameter REQ_TAG_NUM_LOG = log2b(REQ_TAG_NUM - 1), + parameter REORDER_BUFFER_WIDTH = (ICM_CACHE_TYPE == `CACHE_TYPE_MTT) ? CACHE_ENTRY_WIDTH * 2 + COUNT_MAX_LOG : CACHE_ENTRY_WIDTH + COUNT_MAX_LOG +) +( + input wire clk, + input wire rst, + +//Interface with MPTCache + input wire mpt_get_rsp_valid, + input wire [COUNT_MAX_LOG * 2 + `MAX_REQ_TAG_NUM_LOG + PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH - 1 : 0] mpt_get_rsp_head, + input wire [CACHE_ENTRY_WIDTH - 1 : 0] mpt_get_rsp_data, + output wire mpt_get_rsp_ready, + +//Mapping Lookup Interface + output wire icm_mapping_lookup_valid, + output wire [ICM_ENTRY_NUM_LOG - 1 : 0] icm_mapping_lookup_head, + input wire icm_mapping_lookup_ready, + + input wire icm_mapping_rsp_valid, + input wire [ICM_ADDR_WIDTH - 1 : 0] icm_mapping_rsp_icm_addr, + input wire [PHYSICAL_ADDR_WIDTH - 1 : 0] icm_mapping_rsp_phy_addr, + output wire icm_mapping_rsp_ready, + +//Interface with MTTCache + output wire mtt_get_req_valid, + output wire [COUNT_MAX_LOG * 2 + `MAX_REQ_TAG_NUM_LOG + PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH - 1 : 0] mtt_get_req_head, + input wire mtt_get_req_ready, + +//MR Req Buffer Interface + output wire mr_req_buffer_wen, + output wire [`MAX_REQ_TAG_NUM_LOG - 1 : 0] mr_req_buffer_addr, + output wire [`MR_CMD_HEAD_WIDTH - 1 : 0] mr_req_buffer_din, + input wire [`MR_CMD_HEAD_WIDTH - 1 : 0] mr_req_buffer_dout, + +//Page offset Buffer Interface + output wire page_offset_buffer_wen, + output wire [`MAX_REQ_TAG_NUM_LOG - 1 : 0] page_offset_buffer_addr, + output wire [32 + 12 - 1 : 0] page_offset_buffer_din, + input wire [32 + 12 - 1 : 0] page_offset_buffer_dout +); + +/*------------------------------------------- Input/Output Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Macros Definition : Begin ---------------------------------------*/ +`define MR_REQ_FLAGS_OFFSET 31:0 +`define MR_REQ_PD_OFFSET 63:32 +`define MR_REQ_KEY_OFFSET 95:64 +`define MR_REQ_VA_OFFSET 159:96 +`define MR_REQ_LENGTH_OFFSET 191:160 + +`define MPT_FLAGS_OFFSET 31:0 +`define MPT_PAGE_SIZE_OFFSET 63:32 +`define MPT_KEY_OFFSET 95:64 +`define MPT_PD_OFFSET 127:96 +`define MPT_START_OFFSET 191:128 +`define MPT_LENGTH_OFFSET 255:192 +`define MPT_MTT_SEG_OFFSET 319:256 +/*------------------------------------------- Local Macros Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Variables Definition : Begin ------------------------------------*/ +reg [COUNT_MAX_LOG * 2 + `MAX_REQ_TAG_NUM_LOG + PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH - 1: 0] mpt_get_rsp_head_diff; +reg [CACHE_ENTRY_WIDTH - 1 : 0] mpt_get_rsp_data_diff; + +reg [COUNT_MAX_LOG - 1 : 0] count_total; +reg [COUNT_MAX_LOG - 1 : 0] count_index; + +reg [`MAX_REQ_TAG_NUM_LOG - 1 : 0] req_tag; +reg [PHYSICAL_ADDR_WIDTH - 1 : 0] phy_addr; +reg [ICM_ADDR_WIDTH - 1 : 0] icm_addr; + +reg [31:0] mr_req_flags; +reg [31:0] mr_req_pd; +reg [31:0] mr_req_key; +reg [63:0] mr_req_va; +reg [31:0] mr_req_length; + +reg [31:0] mpt_flags; +reg [31:0] mpt_page_size; +reg [31:0] mpt_key; +reg [31:0] mpt_pd; +reg [63:0] mpt_start; +reg [63:0] mpt_length; +reg [63:0] mpt_mtt_seg; + +wire [ICM_ENTRY_NUM_LOG - 1 : 0] mtt_index; + +wire is_relative_addr; +/*------------------------------------------- Local Variables Definition : End --------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : Begin ---------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : End -----------------------------------------*/ + +/*------------------------------------------- State Machine Definition : Begin --------------------------------------*/ +reg [2:0] cur_state; +reg [2:0] next_state; + +parameter [2:0] IDLE_s = 3'd1, + MR_REQ_s = 3'd2, + ADDR_REQ_s = 3'd3, + ADDR_RSP_s = 3'd4, + MTT_GET_s = 3'd5; + +always @(posedge clk or posedge rst) begin + if(rst) begin + cur_state <= IDLE_s; + end + else begin + cur_state <= next_state; + end +end + +always @(*) begin + case(cur_state) + IDLE_s: if(mpt_get_rsp_valid) begin + next_state = MR_REQ_s; + end + else begin + next_state = IDLE_s; + end + MR_REQ_s: next_state = ADDR_REQ_s; + ADDR_REQ_s: if(icm_mapping_lookup_valid && icm_mapping_lookup_ready) begin + next_state = ADDR_RSP_s; + end + else begin + next_state = ADDR_REQ_s; + end + ADDR_RSP_s: if(icm_mapping_rsp_valid) begin + next_state = MTT_GET_s; + end + else begin + next_state = ADDR_RSP_s; + end + MTT_GET_s: if(mtt_get_req_valid && mtt_get_req_ready) begin + if(count_index + 1 == count_total) begin //All MTT requests have been issued + next_state = IDLE_s; + end + else begin + next_state = ADDR_REQ_s; + end + end + else begin + next_state = MTT_GET_s; + end + default: next_state = IDLE_s; + endcase +end +/*------------------------------------------- State Machine Definition : End ----------------------------------------*/ + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ +//-- mr_req_flags -- +//-- mr_req_pd -- +//-- mr_req_key -- +//-- mr_req_va -- +//-- mr_req_length -- +always @(posedge clk or posedge rst) begin + if(rst) begin + mr_req_flags <= 'd0; + mr_req_pd <= 'd0; + mr_req_key <= 'd0; + mr_req_va <= 'd0; + mr_req_length <= 'd0; + end + else if(cur_state == IDLE_s) begin + mr_req_flags <= 'd0; + mr_req_pd <= 'd0; + mr_req_key <= 'd0; + mr_req_va <= 'd0; + mr_req_length <= 'd0; + end + else if(cur_state == MR_REQ_s) begin + mr_req_flags <= mr_req_buffer_dout[`MR_REQ_FLAGS_OFFSET]; + mr_req_pd <= mr_req_buffer_dout[`MR_REQ_PD_OFFSET]; + mr_req_key <= mr_req_buffer_dout[`MR_REQ_KEY_OFFSET]; + mr_req_va <= mr_req_buffer_dout[`MR_REQ_VA_OFFSET]; + mr_req_length <= mr_req_buffer_dout[`MR_REQ_LENGTH_OFFSET]; + end + else begin + mr_req_flags <= mr_req_flags; + mr_req_pd <= mr_req_pd; + mr_req_key <= mr_req_key; + mr_req_va <= mr_req_va; + mr_req_length <= mr_req_length; + end +end + +//-- mpt_flags -- +//-- mpt_page_size -- +//-- mpt_key -- +//-- mpt_pd -- +//-- mpt_start -- +//-- mpt_length -- +//-- mpt_mtt_seg -- +always @(posedge clk or posedge rst) begin + if(rst) begin + mpt_flags <= 'd0; + mpt_page_size <= 'd0; + mpt_key <= 'd0; + mpt_pd <= 'd0; + mpt_start <= 'd0; + mpt_length <= 'd0; + mpt_mtt_seg <= 'd0; + end + else if(cur_state == IDLE_s && mpt_get_rsp_valid) begin + mpt_flags <= mpt_get_rsp_data[`MPT_FLAGS_OFFSET]; + mpt_page_size <= mpt_get_rsp_data[`MPT_PAGE_SIZE_OFFSET]; + mpt_key <= mpt_get_rsp_data[`MPT_KEY_OFFSET]; + mpt_pd <= mpt_get_rsp_data[`MPT_PD_OFFSET]; + mpt_start <= mpt_get_rsp_data[`MPT_START_OFFSET]; + mpt_length <= mpt_get_rsp_data[`MPT_LENGTH_OFFSET]; + mpt_mtt_seg <= mpt_get_rsp_data[`MPT_MTT_SEG_OFFSET]; + end + else begin + mpt_flags <= mpt_flags; + mpt_page_size <= mpt_page_size; + mpt_key <= mpt_key; + mpt_pd <= mpt_pd; + mpt_start <= mpt_start; + mpt_length <= mpt_length; + mpt_mtt_seg <= mpt_mtt_seg; + end +end + +//-- mpt_get_rsp_head_diff -- +//-- mpt_get_rsp_data_diff -- +always @(posedge clk or posedge rst) begin + if(rst) begin + mpt_get_rsp_head_diff <= 'd0; + mpt_get_rsp_data_diff <= 'd0; + end + else if(cur_state == IDLE_s && mpt_get_rsp_valid) begin + mpt_get_rsp_head_diff <= mpt_get_rsp_head; + mpt_get_rsp_data_diff <= mpt_get_rsp_data; + end + else begin + mpt_get_rsp_head_diff <= mpt_get_rsp_head_diff; + mpt_get_rsp_data_diff <= mpt_get_rsp_data_diff; + end +end + +wire [11:0] page_offset; + +//-- page_offset -- +assign page_offset = mr_req_buffer_dout[`MR_REQ_VA_OFFSET] & 64'h00000fff; + +//-- count_total -- +always @(posedge clk or posedge rst) begin + if(rst) begin + count_total <= 'd0; + end + else if(cur_state == IDLE_s) begin + count_total <= 'd0; + end + else if(cur_state == MR_REQ_s) begin + count_total <= page_offset + mr_req_buffer_dout[`MR_REQ_LENGTH_OFFSET] > `PAGE_SIZE ? 'd2 : 'd1; + end + else begin + count_total <= count_total; + end +end + +//-- count_index -- +always @(posedge clk or posedge rst) begin + if(rst) begin + count_index <= 'd0; + end + else if(cur_state == IDLE_s) begin + count_index <= 'd0; + end + else if(cur_state == MR_REQ_s) begin + count_index <= 'd0; + end + else if(cur_state == MTT_GET_s && mtt_get_req_valid && mtt_get_req_ready) begin + count_index <= (count_index + 1 == count_total) ? 'd0 : count_index + 'd1; + end + else begin + count_index <= count_index; + end +end + +//-- mr_req_buffer_wen -- +assign mr_req_buffer_wen = (cur_state == MTT_GET_s && next_state == IDLE_s) ? 'd1 : 'd0; + +//-- mr_req_buffer_din -- +assign mr_req_buffer_din = 'd0; + +//-- mr_req_buffer_addr -- +assign mr_req_buffer_addr = (cur_state == IDLE_s && mpt_get_rsp_valid) ? mpt_get_rsp_head[`MAX_REQ_TAG_NUM_LOG + PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH - 1 : PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH] : + (cur_state != IDLE_s) ? req_tag : 'd0; + +//-- req_tag -- +always @(posedge clk or posedge rst) begin + if(rst) begin + req_tag <= 'd0; + end + else if(cur_state == IDLE_s && mpt_get_rsp_valid) begin + req_tag <= mpt_get_rsp_head[`MAX_REQ_TAG_NUM_LOG + PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH - 1 : PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH]; + end + else begin + req_tag <= req_tag; + end +end + +//-- phy_addr -- +//-- icm_addr -- +always @(posedge clk or posedge rst) begin + if (rst) begin + phy_addr <= 'd0; + icm_addr <= 'd0; + end + else if (cur_state == ADDR_RSP_s && icm_mapping_rsp_valid) begin + phy_addr <= icm_mapping_rsp_phy_addr; + icm_addr <= icm_mapping_rsp_icm_addr; + end + else begin + phy_addr <= phy_addr; + icm_addr <= icm_addr; + end +end + +//-- mpt_get_rsp_ready -- +assign mpt_get_rsp_ready = (cur_state == IDLE_s) ? 'd1 : 'd0; + +//-- is_relative_addr -- +assign is_relative_addr = mr_req_flags[25]; + +//-- mtt_index -- +assign mtt_index = is_relative_addr ? (mr_req_va[ICM_ENTRY_NUM_LOG + 12 - 1 : 12] + mpt_mtt_seg[ICM_ENTRY_NUM_LOG - 1 : 0] + count_index) : //Use count index to distinguish first page and second page(4KB at most for one req) + (mr_req_va[ICM_ENTRY_NUM_LOG + 12 - 1 : 12] - mpt_start[ICM_ENTRY_NUM_LOG + 12 - 1 : 12] + mpt_mtt_seg + count_index); + +//-- icm_mapping_lookup_valid -- +//-- icm_mapping_lookup_head -- +assign icm_mapping_lookup_valid = (cur_state == ADDR_REQ_s) ? 'd1 : 'd0; +assign icm_mapping_lookup_head = (cur_state == ADDR_REQ_s) ? mtt_index : 'd0; + +//-- mtt_get_req_valid -- +//-- mtt_get_req_head -- +assign mtt_get_req_valid = (cur_state == MTT_GET_s) ? 'd1 : 'd0; +assign mtt_get_req_head = (cur_state == MTT_GET_s) ? {count_total, count_index, req_tag, phy_addr, icm_addr} : 'd0; + +// -- icm_mapping_rsp_ready -- +assign icm_mapping_rsp_ready = (cur_state == ADDR_RSP_s) ? 'd1 : 'd0; + +//-- page_offset_buffer_wen -- +//-- page_offset_buffer_addr -- +//-- page_offset_buffer_din -- +assign page_offset_buffer_wen = (cur_state == MR_REQ_s) ? 'd1 : 'd0; +assign page_offset_buffer_addr = (cur_state == MR_REQ_s) ? req_tag : 'd0; +assign page_offset_buffer_din = (cur_state == MR_REQ_s) ? {mr_req_buffer_dout[`MR_REQ_LENGTH_OFFSET], page_offset} : 'd0; +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ + +/*------------------------------------------- Local Macros Undef : Begin --------------------------------------------*/ +`undef MR_REQ_FLAGS_OFFSET +`undef MR_REQ_PD_OFFSET +`undef MR_REQ_KEY_OFFSET +`undef MR_REQ_VA_OFFSET +`undef MR_REQ_LENGTH_OFFSET + +`undef MPT_FLAGS_OFFSET +`undef MPT_PAGE_SIZE_OFFSET +`undef MPT_KEY_OFFSET +`undef MPT_PD_OFFSET +`undef MPT_START_OFFSET +`undef MPT_LENGTH_OFFSET +`undef MPT_MTT_SEG_OFFSET +/*------------------------------------------- Local Macros Undef : End ----------------------------------------------*/ + +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/ICMMgt/MRMgt/HWAccMRCtl/HWAccMRCtl_Thread_4.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/ICMMgt/MRMgt/HWAccMRCtl/HWAccMRCtl_Thread_4.v new file mode 100644 index 0000000000000000000000000000000000000000..dea9e8a7889c03f18a3f93a9804ab06c95ad06bc --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/ICMMgt/MRMgt/HWAccMRCtl/HWAccMRCtl_Thread_4.v @@ -0,0 +1,263 @@ +/*------------------------------------------- Module Description : Begin ---------------------------------------------- +Name: HWAccMRCtl_Thread_4 +Author: YangFan +Function: Handle MTT Resp. +--------------------------------------------- Module Decription : End -----------------------------------------------*/ + +/*------------------------------------------- Timescale Definition : Begin ------------------------------------------*/ +`timescale 1ns / 1ps +/*------------------------------------------- Timescale Definition : End --------------------------------------------*/ + +/*------------------------------------------- Included Files : Begin ------------------------------------------------*/ +`include "protocol_engine_def.vh" +/*------------------------------------------- Included Files : End --------------------------------------------------*/ + +/*------------------------------------------- Input/Output Definition : Begin ---------------------------------------*/ +module HWAccMRCtl_Thread_4 +#( + parameter ICM_CACHE_TYPE = `CACHE_TYPE_MTT, + parameter ICM_PAGE_NUM = `ICM_PAGE_NUM_MTT, + parameter ICM_PAGE_NUM_LOG = log2b(ICM_PAGE_NUM - 1), + parameter ICM_ENTRY_NUM = `ICM_ENTRY_NUM_MTT, + parameter ICM_ENTRY_NUM_LOG = log2b(ICM_ENTRY_NUM - 1), + parameter ICM_SLOT_SIZE = `ICM_SLOT_SIZE_MTT, + parameter ICM_ADDR_WIDTH = 64, + + parameter CACHE_ADDR_WIDTH = ICM_ADDR_WIDTH, + parameter CACHE_ENTRY_WIDTH = 256, + parameter CACHE_SET_NUM = 1024, + parameter CACHE_SET_NUM_LOG = log2b(CACHE_SET_NUM - 1), + parameter CACHE_OFFSET_WIDTH = log2b(CACHE_ENTRY_WIDTH / 8 - 1), + parameter CACHE_TAG_WIDTH = CACHE_ADDR_WIDTH - CACHE_OFFSET_WIDTH - CACHE_SET_NUM_LOG, + parameter PHYSICAL_ADDR_WIDTH = 64, + parameter COUNT_MAX = 2, + parameter COUNT_MAX_LOG = log2b(COUNT_MAX - 1) + 1, + parameter REQ_TAG_NUM = 32, + parameter REQ_TAG_NUM_LOG = log2b(REQ_TAG_NUM - 1), + parameter REORDER_BUFFER_WIDTH = (ICM_CACHE_TYPE == `CACHE_TYPE_MTT) ? CACHE_ENTRY_WIDTH * 2 + COUNT_MAX_LOG : CACHE_ENTRY_WIDTH + COUNT_MAX_LOG +) +( + input wire clk, + input wire rst, + +//Interface with MTTCache + input wire mtt_get_rsp_valid, + input wire [COUNT_MAX_LOG * 2 + `MAX_REQ_TAG_NUM_LOG + PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH - 1 : 0] mtt_get_rsp_head, + input wire [CACHE_ENTRY_WIDTH - 1 : 0] mtt_get_rsp_data, + output wire mtt_get_rsp_ready, + +//Interface with PageOffsetBuffer + output wire page_offset_buffer_wen, + output wire [`MAX_REQ_TAG_NUM_LOG - 1 : 0] page_offset_buffer_addr, + output wire [32 + 12 - 1 : 0] page_offset_buffer_din, + input wire [32 + 12 - 1 : 0] page_offset_buffer_dout, + +//Interface with HWAccMRCtl_Thread_5 + output wire mr_rsp_valid, + output wire [`MAX_REQ_TAG_NUM_LOG - 1 : 0] mr_rsp_head, + output wire [`MR_RESP_DATA_WIDTH - 1 : 0] mr_rsp_data, + input wire mr_rsp_ready +); +/*------------------------------------------- Input/Output Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Macros Definition : Begin ---------------------------------------*/ +/*------------------------------------------- Local Macros Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Variables Definition : Begin ------------------------------------*/ +reg [COUNT_MAX_LOG * 2 + `MAX_REQ_TAG_NUM_LOG + PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH - 1 : 0] mtt_get_rsp_head_diff; +reg [63 : 0] mtt_page_addr_0; +reg [63 : 0] mtt_page_addr_1; + +reg [31 : 0] mtt_page_size_0; +reg [31 : 0] mtt_page_size_1; + +reg [COUNT_MAX_LOG - 1 : 0] count_total; + +reg [`MAX_REQ_TAG_NUM_LOG - 1 : 0] req_tag; +/*------------------------------------------- Local Variables Definition : End --------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : Begin ---------------------------------------*/ +/*------------------------------------------- Submodules Instatiation : End -----------------------------------------*/ + +/*------------------------------------------- State Machine Definition : Begin --------------------------------------*/ +reg [2:0] cur_state; +reg [2:0] next_state; + +parameter [2:0] IDLE_s = 3'd1, + COLLECT_PAGE_0_s = 3'd2, + COLLECT_PAGE_1_s = 3'd3, + FWD_s = 3'd4; + +always @(posedge clk or posedge rst) begin + if(rst) begin + cur_state <= IDLE_s; + end + else begin + cur_state <= next_state; + end +end + +always @(*) begin + case(cur_state) + IDLE_s: if(mtt_get_rsp_valid) begin + next_state = COLLECT_PAGE_0_s; + end + else begin + next_state = IDLE_s; + end + COLLECT_PAGE_0_s: if(mtt_get_rsp_valid && count_total == 1) begin + next_state = FWD_s; + end + else if(mtt_get_rsp_valid && count_total == 2)begin + next_state = COLLECT_PAGE_1_s; + end + else begin + next_state = COLLECT_PAGE_0_s; + end + COLLECT_PAGE_1_s: if(mtt_get_rsp_valid) begin + next_state = FWD_s; + end + else begin + next_state = COLLECT_PAGE_1_s; + end + FWD_s: if(mr_rsp_valid && mr_rsp_ready) begin + next_state = IDLE_s; + end + else begin + next_state = FWD_s; + end + default: next_state = IDLE_s; + endcase +end +/*------------------------------------------- State Machine Definition : End ----------------------------------------*/ + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ +//-- count_total -- +always @(posedge clk or posedge rst) begin + if(rst) begin + count_total <= 'd0; + end + else if(cur_state == IDLE_s && mtt_get_rsp_valid) begin + count_total <= mtt_get_rsp_head[COUNT_MAX_LOG * 2 + `MAX_REQ_TAG_NUM_LOG + PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH - 1 : COUNT_MAX_LOG + `MAX_REQ_TAG_NUM_LOG + PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH]; + end + else begin + count_total <= count_total; + end +end + +//-- req_tag -- +always @(posedge clk or posedge rst) begin + if (rst) begin + req_tag <= 'd0; + end + else if (cur_state == IDLE_s && mtt_get_rsp_valid) begin + req_tag <= mtt_get_rsp_head[`MAX_REQ_TAG_NUM_LOG + PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH - 1 : PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH]; + end + else begin + req_tag <= req_tag; + end +end + +//-- mtt_get_rsp_head_diff -- +always @(posedge clk or posedge rst) begin + if(rst) begin + mtt_get_rsp_head_diff <= 'd0; + end + else if(cur_state == IDLE_s && mtt_get_rsp_valid) begin + mtt_get_rsp_head_diff <= mtt_get_rsp_head; + end + else begin + mtt_get_rsp_head_diff <= mtt_get_rsp_head_diff; + end +end + +//-- mtt_page_addr_0 -- +always @(posedge clk or posedge rst) begin + if(rst) begin + mtt_page_addr_0 <= 'd0; + end + else if(cur_state == COLLECT_PAGE_0_s && mtt_get_rsp_valid) begin + mtt_page_addr_0 <= {mtt_get_rsp_data[63:12], page_offset_buffer_dout[11:0]}; + end + else begin + mtt_page_addr_0 <= mtt_page_addr_0; + end +end + +//-- mtt_page_addr_1 -- +always @(posedge clk or posedge rst) begin + if (rst) begin + mtt_page_addr_1 <= 'd0; + end + else if (cur_state == COLLECT_PAGE_1_s && mtt_get_rsp_valid) begin + mtt_page_addr_1 <= {mtt_get_rsp_data[63:12], 12'd0}; //Second page addr is 4KB aligned + end + else begin + mtt_page_addr_1 <= mtt_page_addr_1; + end +end + +//-- mtt_page_size_0 -- +always @(posedge clk or posedge rst) begin + if (rst) begin + mtt_page_size_0 <= 'd0; + end + else if(cur_state == IDLE_s) begin + mtt_page_size_0 <= 'd0; + end + else if (cur_state == COLLECT_PAGE_0_s && mtt_get_rsp_valid) begin + if(page_offset_buffer_dout[11:0] + page_offset_buffer_dout[43:12] <= `PAGE_SIZE) begin + mtt_page_size_0 <= page_offset_buffer_dout[43:12]; + end + else begin + mtt_page_size_0 <= `PAGE_SIZE - page_offset_buffer_dout[11:0]; + end + end + else begin + mtt_page_size_0 <= mtt_page_size_0; + end +end + +//-- mtt_page_size_1 -- +always @(posedge clk or posedge rst) begin + if (rst) begin + mtt_page_size_1 <= 'd0; + end + else if(cur_state == IDLE_s) begin + mtt_page_size_1 <= 'd0; + end + else if (cur_state == COLLECT_PAGE_1_s && mtt_get_rsp_valid) begin + mtt_page_size_1 <= page_offset_buffer_dout[43:12] - (`PAGE_SIZE - page_offset_buffer_dout[11:0]); + end + else begin + mtt_page_size_1 <= mtt_page_size_1; + end +end + +//-- mtt_get_rsp_ready -- +assign mtt_get_rsp_ready = (cur_state == COLLECT_PAGE_0_s) ? 'd1 : + (cur_state == COLLECT_PAGE_1_s) ? 'd1 : 'd0; + +//-- mr_rsp_valid -- +assign mr_rsp_valid = (cur_state == FWD_s) ? 'd1 : 'd0; + +//-- mr_rsp_head -- +assign mr_rsp_head = (cur_state == FWD_s) ? req_tag : 'd0; + +//-- mr_rsp_data -- +assign mr_rsp_data = (cur_state == FWD_s && count_total == 2) ? {mtt_page_addr_1, mtt_page_addr_0, mtt_page_size_1, mtt_page_size_0, 24'd0, 4'b1111, 4'b1111} : + (cur_state == FWD_s && count_total == 1) ? {64'd0, mtt_page_addr_0, 32'd0, mtt_page_size_0, 24'd0, 4'b0000, 4'b1111} : 'd0; + + +//-- page_offset_buffer_wen -- +//-- page_offset_buffer_addr -- +//-- page_offset_buffer_din -- +assign page_offset_buffer_wen = (cur_state == FWD_s && mr_rsp_valid && mr_rsp_ready) ? 'd1 : 'd0; +assign page_offset_buffer_addr = (cur_state == IDLE_s && mtt_get_rsp_valid) ? mtt_get_rsp_head[`MAX_REQ_TAG_NUM_LOG + PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH - 1 : PHYSICAL_ADDR_WIDTH + ICM_ADDR_WIDTH] : req_tag; +assign page_offset_buffer_din = 'd0; +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ + +/*------------------------------------------- Local Macros Undef : Begin --------------------------------------------*/ +/*------------------------------------------- Local Macros Undef : End ----------------------------------------------*/ + +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/ICMMgt/MRMgt/HWAccMRCtl/HWAccMRCtl_Thread_5.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/ICMMgt/MRMgt/HWAccMRCtl/HWAccMRCtl_Thread_5.v new file mode 100644 index 0000000000000000000000000000000000000000..a13ffbf1b2535f8ebe52a3d962011a9e33dac461 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/ICMMgt/MRMgt/HWAccMRCtl/HWAccMRCtl_Thread_5.v @@ -0,0 +1,247 @@ +/*------------------------------------------- Module Description : Begin ---------------------------------------------- +Name: HWAccMRCtl_Thread_1 +Author: YangFan +Function: Schedule MR requests from different channels. +--------------------------------------------- Module Decription : End -----------------------------------------------*/ + +/*------------------------------------------- Timescale Definition : Begin ------------------------------------------*/ +`timescale 1ns / 1ps +/*------------------------------------------- Timescale Definition : End --------------------------------------------*/ + +/*------------------------------------------- Included Files : Begin ------------------------------------------------*/ +`include "protocol_engine_def.vh" +/*------------------------------------------- Included Files : End --------------------------------------------------*/ + +/*------------------------------------------- Input/Output Definition : Begin ---------------------------------------*/ +module HWAccMRCtl_Thread_5 +#( + parameter ICM_CACHE_TYPE = `CACHE_TYPE_MTT, + parameter ICM_PAGE_NUM = `ICM_PAGE_NUM_MTT, + parameter ICM_PAGE_NUM_LOG = log2b(ICM_PAGE_NUM - 1), + parameter ICM_ENTRY_NUM = `ICM_ENTRY_NUM_MTT, + parameter ICM_ENTRY_NUM_LOG = log2b(ICM_ENTRY_NUM - 1), + parameter ICM_SLOT_SIZE = `ICM_SLOT_SIZE_MTT, + parameter ICM_ADDR_WIDTH = 64, + + parameter CACHE_ADDR_WIDTH = ICM_ADDR_WIDTH, + parameter CACHE_ENTRY_WIDTH = 256, + parameter CACHE_SET_NUM = 1024, + parameter CACHE_SET_NUM_LOG = log2b(CACHE_SET_NUM - 1), + parameter CACHE_OFFSET_WIDTH = log2b(CACHE_ENTRY_WIDTH / 8 - 1), + parameter CACHE_TAG_WIDTH = CACHE_ADDR_WIDTH - CACHE_OFFSET_WIDTH - CACHE_SET_NUM_LOG, + parameter PHYSICAL_ADDR_WIDTH = 64, + parameter COUNT_MAX = 2, + parameter COUNT_MAX_LOG = log2b(COUNT_MAX - 1) + 1, + parameter REQ_TAG_NUM = 32, + parameter REQ_TAG_NUM_LOG = log2b(REQ_TAG_NUM - 1), + parameter REORDER_BUFFER_WIDTH = (ICM_CACHE_TYPE == `CACHE_TYPE_MTT) ? CACHE_ENTRY_WIDTH * 2 + COUNT_MAX_LOG : CACHE_ENTRY_WIDTH + COUNT_MAX_LOG +) +( + input wire clk, + input wire rst, + +//Interface with HWAccMRCtl_Thread_4 + input wire mr_rsp_valid, + input wire [`MAX_REQ_TAG_NUM_LOG - 1 : 0] mr_rsp_head, + input wire [`MR_RESP_DATA_WIDTH - 1 : 0] mr_rsp_data, + output wire mr_rsp_ready, + +//Interface with ChannelQPNMappingTable + output wire [`MAX_REQ_TAG_NUM_LOG - 1 : 0] tag_qpn_mapping_table_addr, + output wire [`QP_NUM_LOG - 1 : 0] tag_qpn_mapping_table_dout, + +//Interface with RDMACore and QueueSubsystem + //Interface with SQMgt + output wire SQ_mr_rsp_valid, + output wire [`MR_RESP_HEAD_WIDTH + `MAX_REQ_TAG_NUM_LOG - 1 : 0] SQ_mr_rsp_head, + output wire [`MR_RESP_DATA_WIDTH - 1 : 0] SQ_mr_rsp_data, + input wire SQ_mr_rsp_ready, + + //Interface with RQMgt + output wire RQ_mr_rsp_valid, + output wire [`MR_RESP_HEAD_WIDTH + `MAX_REQ_TAG_NUM_LOG - 1 : 0] RQ_mr_rsp_head, + output wire [`MR_RESP_DATA_WIDTH - 1 : 0] RQ_mr_rsp_data, + input wire RQ_mr_rsp_ready, + + //Interface with RDMACore/RequesterCore/ReqTransCore + output wire TX_REQ_mr_rsp_valid, + output wire [`MR_RESP_HEAD_WIDTH + `MAX_REQ_TAG_NUM_LOG - 1 : 0] TX_REQ_mr_rsp_head, + output wire [`MR_RESP_DATA_WIDTH - 1 : 0] TX_REQ_mr_rsp_data, + input wire TX_REQ_mr_rsp_ready, + + //Interface with RDMACore/ResponderCore/ReqRecvCore + output wire RX_REQ_mr_rsp_valid, + output wire [`MR_RESP_HEAD_WIDTH + `MAX_REQ_TAG_NUM_LOG - 1 : 0] RX_REQ_mr_rsp_head, + output wire [`MR_RESP_DATA_WIDTH - 1 : 0] RX_REQ_mr_rsp_data, + input wire RX_REQ_mr_rsp_ready, + + //Interface with RDMACore/RequesterCore/RespRecvCore + output wire RX_RESP_mr_rsp_valid, + output wire [`MR_RESP_HEAD_WIDTH + `MAX_REQ_TAG_NUM_LOG - 1 : 0] RX_RESP_mr_rsp_head, + output wire [`MR_RESP_DATA_WIDTH - 1 : 0] RX_RESP_mr_rsp_data, + input wire RX_RESP_mr_rsp_ready +); + +/*------------------------------------------- Input/Output Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Variables Definition : Begin ------------------------------------*/ +wire [2:0] chnl_index; + +reg [`MAX_REQ_TAG_NUM_LOG - 1 : 0] mr_rsp_head_diff; +reg [`MR_RESP_DATA_WIDTH - 1 : 0] mr_rsp_data_diff; +/*------------------------------------------- Local Variables Definition : End --------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : Begin ---------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : End -----------------------------------------*/ + +/*------------------------------------------- State Machine Definition : Begin --------------------------------------*/ +reg [2:0] cur_state; +reg [2:0] next_state; + +parameter [2:0] IDLE_s = 3'd1, + CHNL_0_RSP_s = 3'd2, + CHNL_1_RSP_s = 3'd3, + CHNL_2_RSP_s = 3'd4, + CHNL_3_RSP_s = 3'd6, + CHNL_4_RSP_s = 3'd7; + +always @(posedge clk or posedge rst) begin + if (rst) begin + cur_state <= IDLE_s; + end + else begin + cur_state <= next_state; + end +end + +always @(*) begin + case(cur_state) + IDLE_s: if(mr_rsp_valid) begin + if(chnl_index == 0) begin + next_state = CHNL_0_RSP_s; + end + else if(chnl_index == 1) begin + next_state = CHNL_1_RSP_s; + end + else if(chnl_index == 2) begin + next_state = CHNL_2_RSP_s; + end + else if(chnl_index == 3) begin + next_state = CHNL_3_RSP_s; + end + else if(chnl_index == 4) begin + next_state = CHNL_4_RSP_s; + end + else begin + next_state = IDLE_s; + end + end + else begin + next_state = IDLE_s; + end + CHNL_0_RSP_s: if(SQ_mr_rsp_valid && SQ_mr_rsp_ready) begin + next_state = IDLE_s; + end + else begin + next_state = CHNL_0_RSP_s; + end + CHNL_1_RSP_s: if(RQ_mr_rsp_valid && RQ_mr_rsp_ready) begin + next_state = IDLE_s; + end + else begin + next_state = CHNL_1_RSP_s; + end + CHNL_2_RSP_s: if(TX_REQ_mr_rsp_valid && TX_REQ_mr_rsp_ready) begin + next_state = IDLE_s; + end + else begin + next_state = CHNL_2_RSP_s; + end + CHNL_3_RSP_s: if(RX_REQ_mr_rsp_valid && RX_REQ_mr_rsp_ready) begin + next_state = IDLE_s; + end + else begin + next_state = CHNL_3_RSP_s; + end + CHNL_4_RSP_s: if(RX_RESP_mr_rsp_valid && RX_RESP_mr_rsp_ready) begin + next_state = IDLE_s; + end + else begin + next_state = CHNL_4_RSP_s; + end + default: next_state = IDLE_s; + endcase +end +/*------------------------------------------- State Machine Definition : End ----------------------------------------*/ + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ +//-- chnl_index -- +assign chnl_index = (cur_state == IDLE_s && mr_rsp_valid) ? mr_rsp_head[`REQ_TAG_NUM_LOG + 3 - 1 : `REQ_TAG_NUM_LOG] : 'd0; + +//-- mr_rsp_head_diff -- +//-- mr_rsp_data_diff -- +always @(posedge clk or posedge rst) begin + if (rst) begin + mr_rsp_head_diff <= 'd0; + mr_rsp_data_diff <= 'd0; + end + else if (cur_state == IDLE_s && mr_rsp_valid) begin + mr_rsp_head_diff <= mr_rsp_head; + mr_rsp_data_diff <= mr_rsp_data; + end + else begin + mr_rsp_head_diff <= mr_rsp_head_diff; + mr_rsp_data_diff <= mr_rsp_data_diff; + end +end + +//-- tag_qpn_mapping_table_addr -- +assign tag_qpn_mapping_table_addr = (cur_state == IDLE_s && mr_rsp_valid) ? mr_rsp_head[`MAX_REQ_TAG_NUM_LOG - 1 : 0] : mr_rsp_head_diff[`MAX_REQ_TAG_NUM_LOG - 1 : 0]; + +wire [`MAX_REQ_TAG_NUM_LOG - 1 : 0] rsp_tag; +assign rsp_tag = {'d0, mr_rsp_head_diff[REQ_TAG_NUM_LOG - 1 : 0]}; + +//-- SQ_mr_rsp_valid -- +//-- SQ_mr_rsp_head -- +//-- SQ_mr_rsp_data -- +assign SQ_mr_rsp_valid = (cur_state == CHNL_0_RSP_s) ? 'd1 : 'd0; +assign SQ_mr_rsp_head = (cur_state == CHNL_0_RSP_s) ? {tag_qpn_mapping_table_dout, rsp_tag} : 'd0; +assign SQ_mr_rsp_data = (cur_state == CHNL_0_RSP_s) ? mr_rsp_data_diff : 'd0; + +//-- RQ_mr_rsp_valid -- +//-- RQ_mr_rsp_head -- +//-- RQ_mr_rsp_data -- +assign RQ_mr_rsp_valid = (cur_state == CHNL_1_RSP_s) ? 'd1 : 'd0; +assign RQ_mr_rsp_head = (cur_state == CHNL_1_RSP_s) ? {tag_qpn_mapping_table_dout, rsp_tag} : 'd0; +assign RQ_mr_rsp_data = (cur_state == CHNL_1_RSP_s) ? mr_rsp_data_diff : 'd0; + +//-- TX_REQ_mr_rsp_valid -- +//-- TX_REQ_mr_rsp_head -- +//-- TX_REQ_mr_rsp_data -- +assign TX_REQ_mr_rsp_valid = (cur_state == CHNL_2_RSP_s) ? 'd1 : 'd0; +assign TX_REQ_mr_rsp_head = (cur_state == CHNL_2_RSP_s) ? {tag_qpn_mapping_table_dout, rsp_tag} : 'd0; +assign TX_REQ_mr_rsp_data = (cur_state == CHNL_2_RSP_s) ? mr_rsp_data_diff : 'd0; + +//-- RX_REQ_mr_rsp_valid -- +//-- RX_REQ_mr_rsp_head -- +//-- RX_REQ_mr_rsp_data -- +assign RX_REQ_mr_rsp_valid = (cur_state == CHNL_3_RSP_s) ? 'd1 : 'd0; +assign RX_REQ_mr_rsp_head = (cur_state == CHNL_3_RSP_s) ? {tag_qpn_mapping_table_dout, rsp_tag} : 'd0; +assign RX_REQ_mr_rsp_data = (cur_state == CHNL_3_RSP_s) ? mr_rsp_data_diff : 'd0; + +//-- RX_RESP_mr_rsp_valid -- +//-- RX_RESP_mr_rsp_head -- +//-- RX_RESP_mr_rsp_data -- +assign RX_RESP_mr_rsp_valid = (cur_state == CHNL_4_RSP_s) ? 'd1 : 'd0; +assign RX_RESP_mr_rsp_head = (cur_state == CHNL_4_RSP_s) ? {tag_qpn_mapping_table_dout, rsp_tag} : 'd0; +assign RX_RESP_mr_rsp_data = (cur_state == CHNL_4_RSP_s) ? mr_rsp_data_diff : 'd0; + +//-- mr_rsp_ready -- +assign mr_rsp_ready = (cur_state == IDLE_s); +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ + +/*------------------------------------------- Local Macros Undef : Begin --------------------------------------------*/ +/*------------------------------------------- Local Macros Undef : End ----------------------------------------------*/ + +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/ICMMgt/MRMgt/MRMgt.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/ICMMgt/MRMgt/MRMgt.v new file mode 100644 index 0000000000000000000000000000000000000000..f7f37171d1f47cdd0af212d4fab2633a131aff13 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/ICMMgt/MRMgt/MRMgt.v @@ -0,0 +1,580 @@ +/*------------------------------------------- Module Description : Begin ---------------------------------------------- +Name: MRMgt +Author: YangFan +Function: Memory Region Management. +--------------------------------------------- Module Decription : End -----------------------------------------------*/ + +/*------------------------------------------- Timescale Definition : Begin ------------------------------------------*/ +`timescale 1ns / 1ps +/*------------------------------------------- Timescale Definition : End --------------------------------------------*/ + +/*------------------------------------------- Included Files : Begin ------------------------------------------------*/ +`include "protocol_engine_def.vh" +/*------------------------------------------- Included Files : End --------------------------------------------------*/ + +/*------------------------------------------- Input/Output Definition : Begin ---------------------------------------*/ +module MRMgt +( + input wire clk, + input wire rst, + +//Interface with CEU + input wire ceu_req_valid, + input wire [`CEU_MR_HEAD_WIDTH - 1 : 0] ceu_req_head, + input wire ceu_req_last, + input wire [`CEU_MR_DATA_WIDTH - 1 : 0] ceu_req_data, + output wire ceu_req_ready, + +//Interface with SQMgt + input wire SQ_mr_req_valid, + input wire [`MR_CMD_HEAD_WIDTH + `MAX_REQ_TAG_NUM_LOG - 1 : 0] SQ_mr_req_head, + input wire [`MR_CMD_DATA_WIDTH - 1 : 0] SQ_mr_req_data, + output wire SQ_mr_req_ready, + + output wire SQ_mr_rsp_valid, + output wire [`MR_RESP_HEAD_WIDTH + `MAX_REQ_TAG_NUM_LOG - 1 : 0] SQ_mr_rsp_head, + output wire [`MR_RESP_DATA_WIDTH - 1 : 0] SQ_mr_rsp_data, + input wire SQ_mr_rsp_ready, + +//INterface with RQMgt + input wire RQ_mr_req_valid, + input wire [`MR_CMD_HEAD_WIDTH + `MAX_REQ_TAG_NUM_LOG - 1 : 0] RQ_mr_req_head, + input wire [`MR_CMD_DATA_WIDTH - 1 : 0] RQ_mr_req_data, + output wire RQ_mr_req_ready, + + output wire RQ_mr_rsp_valid, + output wire [`MR_RESP_HEAD_WIDTH + `MAX_REQ_TAG_NUM_LOG - 1 : 0] RQ_mr_rsp_head, + output wire [`MR_RESP_DATA_WIDTH - 1 : 0] RQ_mr_rsp_data, + input wire RQ_mr_rsp_ready, + +//Interface with RDMACore/ReqTransCore + input wire TX_REQ_mr_req_valid, + input wire [`MR_CMD_HEAD_WIDTH + `MAX_REQ_TAG_NUM_LOG - 1 : 0] TX_REQ_mr_req_head, + input wire [`MR_CMD_DATA_WIDTH - 1 : 0] TX_REQ_mr_req_data, + output wire TX_REQ_mr_req_ready, + + output wire TX_REQ_mr_rsp_valid, + output wire [`MR_RESP_HEAD_WIDTH + `MAX_REQ_TAG_NUM_LOG - 1 : 0] TX_REQ_mr_rsp_head, + output wire [`MR_RESP_DATA_WIDTH - 1 : 0] TX_REQ_mr_rsp_data, + input wire TX_REQ_mr_rsp_ready, + +//Interface with RDMACore/ReqRecvCore + input wire RX_REQ_mr_req_valid, + input wire [`MR_CMD_HEAD_WIDTH + `MAX_REQ_TAG_NUM_LOG - 1 : 0] RX_REQ_mr_req_head, + input wire [`MR_CMD_DATA_WIDTH - 1 : 0] RX_REQ_mr_req_data, + output wire RX_REQ_mr_req_ready, + + output wire RX_REQ_mr_rsp_valid, + output wire [`MR_RESP_HEAD_WIDTH + `MAX_REQ_TAG_NUM_LOG - 1 : 0] RX_REQ_mr_rsp_head, + output wire [`MR_RESP_DATA_WIDTH - 1 : 0] RX_REQ_mr_rsp_data, + input wire RX_REQ_mr_rsp_ready, + +//Interface with RDMACore/RespRecvCore + input wire RX_RESP_mr_req_valid, + input wire [`MR_CMD_HEAD_WIDTH + `MAX_REQ_TAG_NUM_LOG - 1 : 0] RX_RESP_mr_req_head, + input wire [`MR_CMD_DATA_WIDTH - 1 : 0] RX_RESP_mr_req_data, + output wire RX_RESP_mr_req_ready, + + output wire RX_RESP_mr_rsp_valid, + output wire [`MR_RESP_HEAD_WIDTH + `MAX_REQ_TAG_NUM_LOG - 1 : 0] RX_RESP_mr_rsp_head, + output wire [`MR_RESP_DATA_WIDTH - 1 : 0] RX_RESP_mr_rsp_data, + input wire RX_RESP_mr_rsp_ready, + +//Interface with DMA + output wire mpt_dma_rd_req_valid, + output wire [`DMA_HEAD_WIDTH - 1 : 0] mpt_dma_rd_req_head, + output wire [`DMA_DATA_WIDTH - 1 : 0] mpt_dma_rd_req_data, + output wire mpt_dma_rd_req_last, + input wire mpt_dma_rd_req_ready, + + input wire mpt_dma_rd_rsp_valid, + input wire [`DMA_HEAD_WIDTH - 1 : 0] mpt_dma_rd_rsp_head, + input wire [`DMA_DATA_WIDTH - 1 : 0] mpt_dma_rd_rsp_data, + input wire mpt_dma_rd_rsp_last, + output wire mpt_dma_rd_rsp_ready, + + output wire mpt_dma_wr_req_valid, + output wire [`DMA_HEAD_WIDTH - 1 : 0] mpt_dma_wr_req_head, + output wire [`DMA_DATA_WIDTH - 1 : 0] mpt_dma_wr_req_data, + output wire mpt_dma_wr_req_last, + input wire mpt_dma_wr_req_ready, + + output wire mtt_dma_rd_req_valid, + output wire [`DMA_HEAD_WIDTH - 1 : 0] mtt_dma_rd_req_head, + output wire [`DMA_DATA_WIDTH - 1 : 0] mtt_dma_rd_req_data, + output wire mtt_dma_rd_req_last, + input wire mtt_dma_rd_req_ready, + + input wire mtt_dma_rd_rsp_valid, + input wire [`DMA_HEAD_WIDTH - 1 : 0] mtt_dma_rd_rsp_head, + input wire [`DMA_DATA_WIDTH - 1 : 0] mtt_dma_rd_rsp_data, + input wire mtt_dma_rd_rsp_last, + output wire mtt_dma_rd_rsp_ready, + + output wire mtt_dma_wr_req_valid, + output wire [`DMA_HEAD_WIDTH - 1 : 0] mtt_dma_wr_req_head, + output wire [`DMA_DATA_WIDTH - 1 : 0] mtt_dma_wr_req_data, + output wire mtt_dma_wr_req_last, + input wire mtt_dma_wr_req_ready +); + +/*------------------------------------------- Input/Output Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Macros Definition : Begin ---------------------------------------*/ + +/*------------------------------------------- Local Macros Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Variables Definition : Begin ------------------------------------*/ +wire mpt_icm_set_req_valid; +wire [`PHY_SPACE_ADDR_WIDTH + `ICM_SPACE_ADDR_WIDTH - 1 : 0] mpt_icm_set_req_head; +wire [`CACHE_ENTRY_WIDTH_MPT - 1 : 0] mpt_icm_set_req_data; +wire mpt_icm_set_req_ready; + +wire sw_mpt_icm_mapping_lookup_valid; +wire [log2b(`ICM_ENTRY_NUM_MPT - 1) - 1 : 0] sw_mpt_icm_mapping_lookup_head; +wire sw_mpt_icm_mapping_lookup_ready; + +wire sw_mpt_icm_mapping_rsp_valid; +wire [`ICM_SPACE_ADDR_WIDTH - 1 : 0] sw_mpt_icm_mapping_rsp_icm_addr; +wire [`PHY_SPACE_ADDR_WIDTH - 1 : 0] sw_mpt_icm_mapping_rsp_phy_addr; +wire sw_mpt_icm_mapping_rsp_ready; + +wire hw_mpt_icm_mapping_lookup_valid; +wire [log2b(`ICM_ENTRY_NUM_MPT - 1) - 1 : 0] hw_mpt_icm_mapping_lookup_head; +wire hw_mpt_icm_mapping_lookup_ready; + +wire hw_mpt_icm_mapping_rsp_valid; +wire [`ICM_SPACE_ADDR_WIDTH - 1 : 0] hw_mpt_icm_mapping_rsp_icm_addr; +wire [`PHY_SPACE_ADDR_WIDTH - 1 : 0] hw_mpt_icm_mapping_rsp_phy_addr; +wire hw_mpt_icm_mapping_rsp_ready; + +wire mpt_icm_mapping_lookup_valid; +wire [log2b(`ICM_ENTRY_NUM_MPT - 1) - 1 : 0] mpt_icm_mapping_lookup_head; +wire mpt_icm_mapping_lookup_ready; + +wire mpt_icm_mapping_rsp_valid; +wire [`ICM_SPACE_ADDR_WIDTH - 1 : 0] mpt_icm_mapping_rsp_icm_addr; +wire [`PHY_SPACE_ADDR_WIDTH - 1 : 0] mpt_icm_mapping_rsp_phy_addr; +wire mpt_icm_mapping_rsp_ready; + +wire mpt_icm_mapping_set_valid; +wire [`PAGE_FRAME_WIDTH - 1 : 0] mpt_icm_mapping_set_head; +wire [`PAGE_FRAME_WIDTH - 1 : 0] mpt_icm_mapping_set_data; + +wire mpt_icm_get_req_valid; +wire [`COUNT_MAX_LOG * 2 + `MAX_REQ_TAG_NUM_LOG + `PHY_SPACE_ADDR_WIDTH + `ICM_SPACE_ADDR_WIDTH - 1 : 0] mpt_icm_get_req_head; +wire mpt_icm_get_req_ready; + +wire mpt_icm_get_rsp_valid; +wire [`COUNT_MAX_LOG * 2 + `MAX_REQ_TAG_NUM_LOG + `PHY_SPACE_ADDR_WIDTH + `ICM_SPACE_ADDR_WIDTH - 1 : 0] mpt_icm_get_rsp_head; +wire [`CACHE_ENTRY_WIDTH_MPT - 1 : 0] mpt_icm_get_rsp_data; +wire mpt_icm_get_rsp_ready; + +wire mtt_icm_set_req_valid; +wire [`PHY_SPACE_ADDR_WIDTH + `ICM_SPACE_ADDR_WIDTH - 1 : 0] mtt_icm_set_req_head; +wire [`CACHE_ENTRY_WIDTH_MTT - 1 : 0] mtt_icm_set_req_data; +wire mtt_icm_set_req_ready; + +wire sw_mtt_icm_mapping_lookup_valid; +wire [log2b(`ICM_ENTRY_NUM_MTT - 1) - 1 : 0] sw_mtt_icm_mapping_lookup_head; +wire sw_mtt_icm_mapping_lookup_ready; + +wire sw_mtt_icm_mapping_rsp_valid; +wire [`ICM_SPACE_ADDR_WIDTH - 1 : 0] sw_mtt_icm_mapping_rsp_icm_addr; +wire [`PHY_SPACE_ADDR_WIDTH - 1 : 0] sw_mtt_icm_mapping_rsp_phy_addr; +wire sw_mtt_icm_mapping_rsp_ready; + +wire hw_mtt_icm_mapping_lookup_valid; +wire [log2b(`ICM_ENTRY_NUM_MTT - 1) - 1 : 0] hw_mtt_icm_mapping_lookup_head; +wire hw_mtt_icm_mapping_lookup_ready; + +wire hw_mtt_icm_mapping_rsp_valid; +wire [`ICM_SPACE_ADDR_WIDTH - 1 : 0] hw_mtt_icm_mapping_rsp_icm_addr; +wire [`PHY_SPACE_ADDR_WIDTH - 1 : 0] hw_mtt_icm_mapping_rsp_phy_addr; +wire hw_mtt_icm_mapping_rsp_ready; + +wire mtt_icm_mapping_lookup_valid; +wire [log2b(`ICM_ENTRY_NUM_MTT - 1) - 1 : 0] mtt_icm_mapping_lookup_head; +wire mtt_icm_mapping_lookup_ready; + +wire mtt_icm_mapping_rsp_valid; +wire [`ICM_SPACE_ADDR_WIDTH - 1 : 0] mtt_icm_mapping_rsp_icm_addr; +wire [`PHY_SPACE_ADDR_WIDTH - 1 : 0] mtt_icm_mapping_rsp_phy_addr; +wire mtt_icm_mapping_rsp_ready; + +wire mtt_icm_mapping_set_valid; +wire [`PAGE_FRAME_WIDTH - 1 : 0] mtt_icm_mapping_set_head; +wire [`PAGE_FRAME_WIDTH - 1 : 0] mtt_icm_mapping_set_data; + +wire mtt_icm_get_req_valid; +wire [`COUNT_MAX_LOG * 2 + `MAX_REQ_TAG_NUM_LOG + `PHY_SPACE_ADDR_WIDTH + `ICM_SPACE_ADDR_WIDTH - 1 : 0] mtt_icm_get_req_head; +wire mtt_icm_get_req_ready; + +wire mtt_icm_get_rsp_valid; +wire [`COUNT_MAX_LOG * 2 + `MAX_REQ_TAG_NUM_LOG + `PHY_SPACE_ADDR_WIDTH + `ICM_SPACE_ADDR_WIDTH - 1 : 0] mtt_icm_get_rsp_head; +wire [`CACHE_ENTRY_WIDTH_MTT - 1 : 0] mtt_icm_get_rsp_data; +wire mtt_icm_get_rsp_ready; + + +wire [`ICM_SPACE_ADDR_WIDTH - 1 : 0] mpt_base; +wire [`ICM_SPACE_ADDR_WIDTH - 1 : 0] mtt_base; +/*------------------------------------------- Local Variables Definition : End --------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : Begin ---------------------------------------*/ +SWAccMRCtl SWAccMRCtl_Inst( + .clk ( clk ), + .rst ( rst ), + + .ceu_req_valid ( ceu_req_valid ), + .ceu_req_head ( ceu_req_head ), + .ceu_req_last ( ceu_req_last ), + .ceu_req_data ( ceu_req_data ), + .ceu_req_ready ( ceu_req_ready ), + + .mpt_icm_set_req_valid ( mpt_icm_set_req_valid ), + .mpt_icm_set_req_head ( mpt_icm_set_req_head ), + .mpt_icm_set_req_data ( mpt_icm_set_req_data ), + .mpt_icm_set_req_ready ( mpt_icm_set_req_ready ), + + .mpt_icm_mapping_lookup_valid ( sw_mpt_icm_mapping_lookup_valid ), + .mpt_icm_mapping_lookup_head ( sw_mpt_icm_mapping_lookup_head ), + .mpt_icm_mapping_lookup_ready ( sw_mpt_icm_mapping_lookup_ready ), + + .mpt_icm_mapping_rsp_valid ( sw_mpt_icm_mapping_rsp_valid ), + .mpt_icm_mapping_rsp_icm_addr ( sw_mpt_icm_mapping_rsp_icm_addr ), + .mpt_icm_mapping_rsp_phy_addr ( sw_mpt_icm_mapping_rsp_phy_addr ), + .mpt_icm_mapping_rsp_ready ( sw_mpt_icm_mapping_rsp_ready ), + + .mpt_icm_mapping_set_valid ( mpt_icm_mapping_set_valid ), + .mpt_icm_mapping_set_head ( mpt_icm_mapping_set_head ), + .mpt_icm_mapping_set_data ( mpt_icm_mapping_set_data ), + + .mtt_icm_set_req_valid ( mtt_icm_set_req_valid ), + .mtt_icm_set_req_head ( mtt_icm_set_req_head ), + .mtt_icm_set_req_data ( mtt_icm_set_req_data ), + .mtt_icm_set_req_ready ( mtt_icm_set_req_ready ), + + .mtt_icm_mapping_lookup_valid ( sw_mtt_icm_mapping_lookup_valid ), + .mtt_icm_mapping_lookup_head ( sw_mtt_icm_mapping_lookup_head ), + .mtt_icm_mapping_lookup_ready ( sw_mtt_icm_mapping_lookup_ready ), + + .mtt_icm_mapping_rsp_valid ( sw_mtt_icm_mapping_rsp_valid ), + .mtt_icm_mapping_rsp_icm_addr ( sw_mtt_icm_mapping_rsp_icm_addr ), + .mtt_icm_mapping_rsp_phy_addr ( sw_mtt_icm_mapping_rsp_phy_addr ), + .mtt_icm_mapping_rsp_ready ( sw_mtt_icm_mapping_rsp_ready ), + + .mtt_icm_mapping_set_valid ( mtt_icm_mapping_set_valid ), + .mtt_icm_mapping_set_head ( mtt_icm_mapping_set_head ), + .mtt_icm_mapping_set_data ( mtt_icm_mapping_set_data ), + + .mpt_base ( mpt_base ), + .mtt_base ( mtt_base ) +); + +HWAccMRCtl HWAccMRCtl_Inst( + .clk ( clk ), + .rst ( rst ), + + .SQ_mr_req_valid ( SQ_mr_req_valid ), + .SQ_mr_req_head ( SQ_mr_req_head ), + .SQ_mr_req_data ( SQ_mr_req_data ), + .SQ_mr_req_ready ( SQ_mr_req_ready ), + + .SQ_mr_rsp_valid ( SQ_mr_rsp_valid ), + .SQ_mr_rsp_head ( SQ_mr_rsp_head ), + .SQ_mr_rsp_data ( SQ_mr_rsp_data ), + .SQ_mr_rsp_ready ( SQ_mr_rsp_ready ), + + .RQ_mr_req_valid ( RQ_mr_req_valid ), + .RQ_mr_req_head ( RQ_mr_req_head ), + .RQ_mr_req_data ( RQ_mr_req_data ), + .RQ_mr_req_ready ( RQ_mr_req_ready ), + + .RQ_mr_rsp_valid ( RQ_mr_rsp_valid ), + .RQ_mr_rsp_head ( RQ_mr_rsp_head ), + .RQ_mr_rsp_data ( RQ_mr_rsp_data ), + .RQ_mr_rsp_ready ( RQ_mr_rsp_ready ), + + .TX_REQ_mr_req_valid ( TX_REQ_mr_req_valid ), + .TX_REQ_mr_req_head ( TX_REQ_mr_req_head ), + .TX_REQ_mr_req_data ( TX_REQ_mr_req_data ), + .TX_REQ_mr_req_ready ( TX_REQ_mr_req_ready ), + + .TX_REQ_mr_rsp_valid ( TX_REQ_mr_rsp_valid ), + .TX_REQ_mr_rsp_head ( TX_REQ_mr_rsp_head ), + .TX_REQ_mr_rsp_data ( TX_REQ_mr_rsp_data ), + .TX_REQ_mr_rsp_ready ( TX_REQ_mr_rsp_ready ), + + .RX_REQ_mr_req_valid ( RX_REQ_mr_req_valid ), + .RX_REQ_mr_req_head ( RX_REQ_mr_req_head ), + .RX_REQ_mr_req_data ( RX_REQ_mr_req_data ), + .RX_REQ_mr_req_ready ( RX_REQ_mr_req_ready ), + + .RX_REQ_mr_rsp_valid ( RX_REQ_mr_rsp_valid ), + .RX_REQ_mr_rsp_head ( RX_REQ_mr_rsp_head ), + .RX_REQ_mr_rsp_data ( RX_REQ_mr_rsp_data ), + .RX_REQ_mr_rsp_ready ( RX_REQ_mr_rsp_ready ), + + .RX_RESP_mr_req_valid ( RX_RESP_mr_req_valid ), + .RX_RESP_mr_req_head ( RX_RESP_mr_req_head ), + .RX_RESP_mr_req_data ( RX_RESP_mr_req_data ), + .RX_RESP_mr_req_ready ( RX_RESP_mr_req_ready ), + + .RX_RESP_mr_rsp_valid ( RX_RESP_mr_rsp_valid ), + .RX_RESP_mr_rsp_head ( RX_RESP_mr_rsp_head ), + .RX_RESP_mr_rsp_data ( RX_RESP_mr_rsp_data ), + .RX_RESP_mr_rsp_ready ( RX_RESP_mr_rsp_ready ), + + .mpt_icm_mapping_lookup_valid ( hw_mpt_icm_mapping_lookup_valid ), + .mpt_icm_mapping_lookup_head ( hw_mpt_icm_mapping_lookup_head ), + .mpt_icm_mapping_lookup_ready ( hw_mpt_icm_mapping_lookup_ready ), + + .mpt_icm_mapping_rsp_valid ( hw_mpt_icm_mapping_rsp_valid ), + .mpt_icm_mapping_rsp_icm_addr ( hw_mpt_icm_mapping_rsp_icm_addr ), + .mpt_icm_mapping_rsp_phy_addr ( hw_mpt_icm_mapping_rsp_phy_addr ), + .mpt_icm_mapping_rsp_ready ( hw_mpt_icm_mapping_rsp_ready ), + + .mpt_icm_get_req_valid ( mpt_icm_get_req_valid ), + .mpt_icm_get_req_head ( mpt_icm_get_req_head ), + .mpt_icm_get_req_ready ( mpt_icm_get_req_ready ), + + .mpt_icm_get_rsp_valid ( mpt_icm_get_rsp_valid ), + .mpt_icm_get_rsp_head ( mpt_icm_get_rsp_head ), + .mpt_icm_get_rsp_data ( mpt_icm_get_rsp_data ), + .mpt_icm_get_rsp_ready ( mpt_icm_get_rsp_ready ), + + .mtt_icm_mapping_lookup_valid ( hw_mtt_icm_mapping_lookup_valid ), + .mtt_icm_mapping_lookup_head ( hw_mtt_icm_mapping_lookup_head ), + .mtt_icm_mapping_lookup_ready ( hw_mtt_icm_mapping_lookup_ready ), + + .mtt_icm_mapping_rsp_valid ( hw_mtt_icm_mapping_rsp_valid ), + .mtt_icm_mapping_rsp_icm_addr ( hw_mtt_icm_mapping_rsp_icm_addr ), + .mtt_icm_mapping_rsp_phy_addr ( hw_mtt_icm_mapping_rsp_phy_addr ), + .mtt_icm_mapping_rsp_ready ( hw_mtt_icm_mapping_rsp_ready ), + + .mtt_icm_get_req_valid ( mtt_icm_get_req_valid ), + .mtt_icm_get_req_head ( mtt_icm_get_req_head ), + .mtt_icm_get_req_ready ( mtt_icm_get_req_ready ), + + .mtt_icm_get_rsp_valid ( mtt_icm_get_rsp_valid ), + .mtt_icm_get_rsp_head ( mtt_icm_get_rsp_head ), + .mtt_icm_get_rsp_data ( mtt_icm_get_rsp_data ), + .mtt_icm_get_rsp_ready ( mtt_icm_get_rsp_ready ) +); + +ICMCache #( + .ICM_CACHE_TYPE ( `CACHE_TYPE_MPT ), + .ICM_PAGE_NUM ( `ICM_PAGE_NUM_MPT ), + + .ICM_ENTRY_NUM ( `ICM_ENTRY_NUM_MPT ), + + .ICM_SLOT_SIZE ( `ICM_SLOT_SIZE_MPT ), + .ICM_ADDR_WIDTH ( `ICM_SPACE_ADDR_WIDTH ), + + .CACHE_ENTRY_WIDTH ( `CACHE_ENTRY_WIDTH_MPT ), + .CACHE_SET_NUM ( `CACHE_SET_NUM_MPT ) +) +MPTCache_Inst +( + .clk ( clk ), + .rst ( rst ), + + .icm_get_req_valid ( mpt_icm_get_req_valid ), + .icm_get_req_head ( mpt_icm_get_req_head ), + .icm_get_req_ready ( mpt_icm_get_req_ready ), + + .icm_get_rsp_valid ( mpt_icm_get_rsp_valid ), + .icm_get_rsp_head ( mpt_icm_get_rsp_head ), + .icm_get_rsp_data ( mpt_icm_get_rsp_data ), + .icm_get_rsp_ready ( mpt_icm_get_rsp_ready ), + + .icm_set_req_valid ( mpt_icm_set_req_valid ), + .icm_set_req_head ( mpt_icm_set_req_head ), + .icm_set_req_data ( mpt_icm_set_req_data ), + .icm_set_req_ready ( mpt_icm_set_req_ready ), + + .icm_del_req_valid ( 'd0 ), + .icm_del_req_head ( 'd0 ), + .icm_del_req_ready ( ), + + .dma_rd_req_valid ( mpt_dma_rd_req_valid ), + .dma_rd_req_head ( mpt_dma_rd_req_head ), + .dma_rd_req_data ( mpt_dma_rd_req_data ), + .dma_rd_req_last ( mpt_dma_rd_req_last ), + .dma_rd_req_ready ( mpt_dma_rd_req_ready ), + + .dma_rd_rsp_valid ( mpt_dma_rd_rsp_valid ), + .dma_rd_rsp_head ( mpt_dma_rd_rsp_head ), + .dma_rd_rsp_data ( mpt_dma_rd_rsp_data ), + .dma_rd_rsp_last ( mpt_dma_rd_rsp_last ), + .dma_rd_rsp_ready ( mpt_dma_rd_rsp_ready ), + + .dma_wr_req_valid ( mpt_dma_wr_req_valid ), + .dma_wr_req_head ( mpt_dma_wr_req_head ), + .dma_wr_req_data ( mpt_dma_wr_req_data ), + .dma_wr_req_last ( mpt_dma_wr_req_last ), + .dma_wr_req_ready ( mpt_dma_wr_req_ready ), + + .icm_mapping_set_valid ( mpt_icm_mapping_set_valid ), + .icm_mapping_set_head ( mpt_icm_mapping_set_head ), + .icm_mapping_set_data ( mpt_icm_mapping_set_data ), + + .icm_mapping_lookup_valid ( mpt_icm_mapping_lookup_valid ), + .icm_mapping_lookup_head ( mpt_icm_mapping_lookup_head ), + + .icm_mapping_rsp_valid ( mpt_icm_mapping_rsp_valid ), + .icm_mapping_rsp_icm_addr ( mpt_icm_mapping_rsp_icm_addr ), + .icm_mapping_rsp_phy_addr ( mpt_icm_mapping_rsp_phy_addr ), + + .icm_base ( mpt_base ) + ); + +ICMCache #( + .ICM_CACHE_TYPE ( `CACHE_TYPE_MTT ), + .ICM_PAGE_NUM ( `ICM_PAGE_NUM_MTT ), + + .ICM_ENTRY_NUM ( `ICM_ENTRY_NUM_MTT ), + + .ICM_SLOT_SIZE ( `ICM_SLOT_SIZE_MTT ), + .ICM_ADDR_WIDTH ( `ICM_SPACE_ADDR_WIDTH ), + + .CACHE_ENTRY_WIDTH ( `CACHE_ENTRY_WIDTH_MTT ), + .CACHE_SET_NUM ( `CACHE_SET_NUM_MTT ) +) +MTTCache_Inst +( + .clk ( clk ), + .rst ( rst ), + + .icm_get_req_valid ( mtt_icm_get_req_valid ), + .icm_get_req_head ( mtt_icm_get_req_head ), + .icm_get_req_ready ( mtt_icm_get_req_ready ), + + .icm_get_rsp_valid ( mtt_icm_get_rsp_valid ), + .icm_get_rsp_head ( mtt_icm_get_rsp_head ), + .icm_get_rsp_data ( mtt_icm_get_rsp_data ), + .icm_get_rsp_ready ( mtt_icm_get_rsp_ready ), + + .icm_set_req_valid ( mtt_icm_set_req_valid ), + .icm_set_req_head ( mtt_icm_set_req_head ), + .icm_set_req_data ( mtt_icm_set_req_data ), + .icm_set_req_ready ( mtt_icm_set_req_ready ), + + .icm_del_req_valid ( 'd0 ), + .icm_del_req_head ( 'd0 ), + .icm_del_req_ready ( ), + + .dma_rd_req_valid ( mtt_dma_rd_req_valid ), + .dma_rd_req_head ( mtt_dma_rd_req_head ), + .dma_rd_req_data ( mtt_dma_rd_req_data ), + .dma_rd_req_last ( mtt_dma_rd_req_last ), + .dma_rd_req_ready ( mtt_dma_rd_req_ready ), + + .dma_rd_rsp_valid ( mtt_dma_rd_rsp_valid ), + .dma_rd_rsp_head ( mtt_dma_rd_rsp_head ), + .dma_rd_rsp_data ( mtt_dma_rd_rsp_data ), + .dma_rd_rsp_last ( mtt_dma_rd_rsp_last ), + .dma_rd_rsp_ready ( mtt_dma_rd_rsp_ready ), + + .dma_wr_req_valid ( mtt_dma_wr_req_valid ), + .dma_wr_req_head ( mtt_dma_wr_req_head ), + .dma_wr_req_data ( mtt_dma_wr_req_data ), + .dma_wr_req_last ( mtt_dma_wr_req_last ), + .dma_wr_req_ready ( mtt_dma_wr_req_ready ), + + .icm_mapping_set_valid ( mtt_icm_mapping_set_valid ), + .icm_mapping_set_head ( mtt_icm_mapping_set_head ), + .icm_mapping_set_data ( mtt_icm_mapping_set_data ), + + .icm_mapping_lookup_valid ( mtt_icm_mapping_lookup_valid ), + .icm_mapping_lookup_head ( mtt_icm_mapping_lookup_head ), + + .icm_mapping_rsp_valid ( mtt_icm_mapping_rsp_valid ), + .icm_mapping_rsp_icm_addr ( mtt_icm_mapping_rsp_icm_addr ), + .icm_mapping_rsp_phy_addr ( mtt_icm_mapping_rsp_phy_addr ), + + .icm_base ( mtt_base ) + ); + +ICMLookupArbiter +#( + .ICM_ENTRY_NUM ( `ICM_ENTRY_NUM_MPT ) +) +MPT_ICMLookupArbiter_Inst +( + .clk ( clk ), + .rst ( rst ), + + .chnl_0_lookup_valid ( sw_mpt_icm_mapping_lookup_valid ), + .chnl_0_lookup_head ( sw_mpt_icm_mapping_lookup_head ), + .chnl_0_lookup_ready ( sw_mpt_icm_mapping_lookup_ready ), + + .chnl_0_rsp_valid ( sw_mpt_icm_mapping_rsp_valid ), + .chnl_0_rsp_icm_addr ( sw_mpt_icm_mapping_rsp_icm_addr ), + .chnl_0_rsp_phy_addr ( sw_mpt_icm_mapping_rsp_phy_addr ), + .chnl_0_rsp_ready ( sw_mpt_icm_mapping_rsp_ready ), + + .chnl_1_lookup_valid ( hw_mpt_icm_mapping_lookup_valid ), + .chnl_1_lookup_head ( hw_mpt_icm_mapping_lookup_head ), + .chnl_1_lookup_ready ( hw_mpt_icm_mapping_lookup_ready ), + + .chnl_1_rsp_valid ( hw_mpt_icm_mapping_rsp_valid ), + .chnl_1_rsp_icm_addr ( hw_mpt_icm_mapping_rsp_icm_addr ), + .chnl_1_rsp_phy_addr ( hw_mpt_icm_mapping_rsp_phy_addr ), + .chnl_1_rsp_ready ( hw_mpt_icm_mapping_rsp_ready ), + + .lookup_valid ( mpt_icm_mapping_lookup_valid ), + .lookup_head ( mpt_icm_mapping_lookup_head ), + + .rsp_valid ( mpt_icm_mapping_rsp_valid ), + .rsp_icm_addr ( mpt_icm_mapping_rsp_icm_addr ), + .rsp_phy_addr ( mpt_icm_mapping_rsp_phy_addr ) +); + +ICMLookupArbiter +#( + .ICM_ENTRY_NUM ( `ICM_ENTRY_NUM_MTT ) +) +MTT_ICMLookupArbiter_Inst +( + .clk ( clk ), + .rst ( rst ), + + .chnl_0_lookup_valid ( sw_mtt_icm_mapping_lookup_valid ), + .chnl_0_lookup_head ( sw_mtt_icm_mapping_lookup_head ), + .chnl_0_lookup_ready ( sw_mtt_icm_mapping_lookup_ready ), + + .chnl_0_rsp_valid ( sw_mtt_icm_mapping_rsp_valid ), + .chnl_0_rsp_icm_addr ( sw_mtt_icm_mapping_rsp_icm_addr ), + .chnl_0_rsp_phy_addr ( sw_mtt_icm_mapping_rsp_phy_addr ), + .chnl_0_rsp_ready ( sw_mtt_icm_mapping_rsp_ready ), + + .chnl_1_lookup_valid ( hw_mtt_icm_mapping_lookup_valid ), + .chnl_1_lookup_head ( hw_mtt_icm_mapping_lookup_head ), + .chnl_1_lookup_ready ( hw_mtt_icm_mapping_lookup_ready ), + + .chnl_1_rsp_valid ( hw_mtt_icm_mapping_rsp_valid ), + .chnl_1_rsp_icm_addr ( hw_mtt_icm_mapping_rsp_icm_addr ), + .chnl_1_rsp_phy_addr ( hw_mtt_icm_mapping_rsp_phy_addr ), + .chnl_1_rsp_ready ( hw_mtt_icm_mapping_rsp_ready ), + + .lookup_valid ( mtt_icm_mapping_lookup_valid ), + .lookup_head ( mtt_icm_mapping_lookup_head ), + + .rsp_valid ( mtt_icm_mapping_rsp_valid ), + .rsp_icm_addr ( mtt_icm_mapping_rsp_icm_addr ), + .rsp_phy_addr ( mtt_icm_mapping_rsp_phy_addr ) +); +/*------------------------------------------- Submodules Instatiation : End -----------------------------------------*/ + +/*------------------------------------------- State Machine Definition : Begin --------------------------------------*/ +/*------------------------------------------- State Machine Definition : End ----------------------------------------*/ + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ + +/*------------------------------------------- Local Macros Undef : Begin --------------------------------------------*/ +/*------------------------------------------- Local Macros Undef : End ----------------------------------------------*/ + +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/ICMMgt/MRMgt/SWAccMRCtl/SWAccMRCtl.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/ICMMgt/MRMgt/SWAccMRCtl/SWAccMRCtl.v new file mode 100644 index 0000000000000000000000000000000000000000..1f8ffb4ef15411e9cad585e15abca01a17ac8eee --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/ICMMgt/MRMgt/SWAccMRCtl/SWAccMRCtl.v @@ -0,0 +1,211 @@ +/*------------------------------------------- Module Description : Begin ---------------------------------------------- +Name: SWAccMRCtl +Author: YangFan +Function: Control Software to MRMgt Access. +--------------------------------------------- Module Decription : End -----------------------------------------------*/ + +/*------------------------------------------- Timescale Definition : Begin ------------------------------------------*/ +`timescale 1ns / 1ps +/*------------------------------------------- Timescale Definition : End --------------------------------------------*/ + +/*------------------------------------------- Included Files : Begin ------------------------------------------------*/ +`include "protocol_engine_def.vh" +/*------------------------------------------- Included Files : End --------------------------------------------------*/ + +/*------------------------------------------- Input/Output Definition : Begin ---------------------------------------*/ +module SWAccMRCtl +( + input wire clk, + input wire rst, + +//Interface with CEU + input wire ceu_req_valid, + input wire [`CEU_MR_HEAD_WIDTH - 1 : 0] ceu_req_head, + input wire ceu_req_last, + input wire [`CEU_MR_DATA_WIDTH - 1 : 0] ceu_req_data, + output wire ceu_req_ready, + +//Interface with MPTCache(ICMCache) + output wire mpt_icm_set_req_valid, + output wire [`REQ_TAG_NUM_LOG + `COUNT_MAX_LOG * 2 + `ICM_SPACE_ADDR_WIDTH + `PHY_SPACE_ADDR_WIDTH - 1 : 0] mpt_icm_set_req_head, + output wire [`CACHE_ENTRY_WIDTH_MPT - 1 : 0] mpt_icm_set_req_data, + input wire mpt_icm_set_req_ready, + + output wire mpt_icm_mapping_lookup_valid, + output wire [log2b(`ICM_ENTRY_NUM_MPT - 1) - 1 : 0] mpt_icm_mapping_lookup_head, + input wire mpt_icm_mapping_lookup_ready, + + input wire mpt_icm_mapping_rsp_valid, + input wire [`ICM_SPACE_ADDR_WIDTH - 1 : 0] mpt_icm_mapping_rsp_icm_addr, + input wire [`PHY_SPACE_ADDR_WIDTH - 1 : 0] mpt_icm_mapping_rsp_phy_addr, + output wire mpt_icm_mapping_rsp_ready, + + output wire mpt_icm_mapping_set_valid, + output wire [`PAGE_FRAME_WIDTH - 1 : 0] mpt_icm_mapping_set_head, + output wire [`PAGE_FRAME_WIDTH - 1 : 0] mpt_icm_mapping_set_data, + + output wire [`ICM_SPACE_ADDR_WIDTH - 1 : 0] mpt_base, + +//Interface with MPTCache(ICMCache) + output wire mtt_icm_set_req_valid, + output wire [`REQ_TAG_NUM_LOG + `COUNT_MAX_LOG * 2 + `ICM_SPACE_ADDR_WIDTH + `PHY_SPACE_ADDR_WIDTH - 1 : 0] mtt_icm_set_req_head, + output wire [`CACHE_ENTRY_WIDTH_MTT - 1 : 0] mtt_icm_set_req_data, + input wire mtt_icm_set_req_ready, + + output wire mtt_icm_mapping_lookup_valid, + output wire [log2b(`ICM_ENTRY_NUM_MTT - 1) - 1 : 0] mtt_icm_mapping_lookup_head, + input wire mtt_icm_mapping_lookup_ready, + + input wire mtt_icm_mapping_rsp_valid, + input wire [`ICM_SPACE_ADDR_WIDTH - 1 : 0] mtt_icm_mapping_rsp_icm_addr, + input wire [`PHY_SPACE_ADDR_WIDTH - 1 : 0] mtt_icm_mapping_rsp_phy_addr, + output wire mtt_icm_mapping_rsp_ready, + + output wire mtt_icm_mapping_set_valid, + output wire [`PAGE_FRAME_WIDTH - 1 : 0] mtt_icm_mapping_set_head, + output wire [`PAGE_FRAME_WIDTH - 1 : 0] mtt_icm_mapping_set_data, + + output wire [`ICM_SPACE_ADDR_WIDTH - 1 : 0] mtt_base +); + +/*------------------------------------------- Input/Output Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Macros Definition : Begin ---------------------------------------*/ + +/*------------------------------------------- Local Macros Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Variables Definition : Begin ------------------------------------*/ +wire mpt_req_valid; +wire [`CEU_MR_HEAD_WIDTH - 1 : 0] mpt_req_head; +wire mpt_req_last; +wire [`CEU_MR_DATA_WIDTH - 1 : 0] mpt_req_data; +wire mpt_req_ready; + +wire mtt_req_valid; +wire [`CEU_MR_HEAD_WIDTH - 1 : 0] mtt_req_head; +wire mtt_req_last; +wire [`CEU_MR_DATA_WIDTH - 1 : 0] mtt_req_data; +wire mtt_req_ready; + +wire mapping_req_valid; +wire [`CEU_MR_HEAD_WIDTH - 1 : 0] mapping_req_head; +wire mapping_req_last; +wire [`CEU_MR_DATA_WIDTH - 1 : 0] mapping_req_data; +wire mapping_req_ready; + +/*------------------------------------------- Local Variables Definition : End --------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : Begin ---------------------------------------*/ +SWAccMRCtl_Thread_1 SWAccMRCtl_Thread_1_Inst( + .clk ( clk ), + .rst ( rst ), + + .ceu_req_valid ( ceu_req_valid ), + .ceu_req_head ( ceu_req_head ), + .ceu_req_last ( ceu_req_last ), + .ceu_req_data ( ceu_req_data ), + .ceu_req_ready ( ceu_req_ready ), + + .mpt_req_valid ( mpt_req_valid ), + .mpt_req_head ( mpt_req_head ), + .mpt_req_last ( mpt_req_last ), + .mpt_req_data ( mpt_req_data ), + .mpt_req_ready ( mpt_req_ready ), + + .mtt_req_valid ( mtt_req_valid ), + .mtt_req_head ( mtt_req_head ), + .mtt_req_last ( mtt_req_last ), + .mtt_req_data ( mtt_req_data ), + .mtt_req_ready ( mtt_req_ready ), + + .mapping_req_valid ( mapping_req_valid ), + .mapping_req_head ( mapping_req_head ), + .mapping_req_last ( mapping_req_last ), + .mapping_req_data ( mapping_req_data ), + .mapping_req_ready ( mapping_req_ready ) +); + +SWAccMRCtl_Thread_2 SWAccMRCtl_Thread_2_Inst ( + .clk ( clk ), + .rst ( rst ), + + .mpt_req_valid ( mpt_req_valid ), + .mpt_req_head ( mpt_req_head ), + .mpt_req_last ( mpt_req_last ), + .mpt_req_data ( mpt_req_data ), + .mpt_req_ready ( mpt_req_ready ), + + .cache_set_req_valid ( mpt_icm_set_req_valid ), + .cache_set_req_head ( mpt_icm_set_req_head ), + .cache_set_req_data ( mpt_icm_set_req_data ), + .cache_set_req_ready ( mpt_icm_set_req_ready ), + + .icm_mapping_lookup_valid ( mpt_icm_mapping_lookup_valid ), + .icm_mapping_lookup_head ( mpt_icm_mapping_lookup_head ), + .icm_mapping_lookup_ready ( mpt_icm_mapping_lookup_ready ), + + .icm_mapping_rsp_valid ( mpt_icm_mapping_rsp_valid ), + .icm_mapping_rsp_icm_addr ( mpt_icm_mapping_rsp_icm_addr ), + .icm_mapping_rsp_phy_addr ( mpt_icm_mapping_rsp_phy_addr ), + .icm_mapping_rsp_ready ( mpt_icm_mapping_rsp_ready ) +); + +SWAccMRCtl_Thread_3 SWAccMRCtl_Thread_3_Inst ( + .clk ( clk ), + .rst ( rst ), + + .mtt_req_valid ( mtt_req_valid ), + .mtt_req_head ( mtt_req_head ), + .mtt_req_last ( mtt_req_last ), + .mtt_req_data ( mtt_req_data ), + .mtt_req_ready ( mtt_req_ready ), + + .cache_set_req_valid ( mtt_icm_set_req_valid ), + .cache_set_req_head ( mtt_icm_set_req_head ), + .cache_set_req_data ( mtt_icm_set_req_data ), + .cache_set_req_ready ( mtt_icm_set_req_ready ), + + .icm_mapping_lookup_valid ( mtt_icm_mapping_lookup_valid ), + .icm_mapping_lookup_head ( mtt_icm_mapping_lookup_head ), + .icm_mapping_lookup_ready ( mtt_icm_mapping_lookup_ready ), + + .icm_mapping_rsp_valid ( mtt_icm_mapping_rsp_valid ), + .icm_mapping_rsp_icm_addr ( mtt_icm_mapping_rsp_icm_addr ), + .icm_mapping_rsp_phy_addr ( mtt_icm_mapping_rsp_phy_addr ), + .icm_mapping_rsp_ready ( mtt_icm_mapping_rsp_ready ) +); + +SWAccMRCtl_Thread_4 SWAccMRCtl_Thread_4_Inst( + .clk ( clk ), + .rst ( rst ), + + .map_req_valid ( mapping_req_valid ), + .map_req_head ( mapping_req_head ), + .map_req_last ( mapping_req_last ), + .map_req_data ( mapping_req_data ), + .map_req_ready ( mapping_req_ready ), + + .mpt_mapping_set_valid ( mpt_icm_mapping_set_valid ), + .mpt_mapping_set_head ( mpt_icm_mapping_set_head ), + .mpt_mapping_set_data ( mpt_icm_mapping_set_data ), + + .mtt_mapping_set_valid ( mtt_icm_mapping_set_valid ), + .mtt_mapping_set_head ( mtt_icm_mapping_set_head ), + .mtt_mapping_set_data ( mtt_icm_mapping_set_data ), + + .mpt_base ( mpt_base ), + .mtt_base ( mtt_base ) +); +/*------------------------------------------- Submodules Instatiation : End -----------------------------------------*/ + +/*------------------------------------------- State Machine Definition : Begin --------------------------------------*/ +/*------------------------------------------- State Machine Definition : End ----------------------------------------*/ + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ + +/*------------------------------------------- Local Macros Undef : Begin --------------------------------------------*/ +/*------------------------------------------- Local Macros Undef : End ----------------------------------------------*/ + +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/ICMMgt/MRMgt/SWAccMRCtl/SWAccMRCtl_Thread_1.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/ICMMgt/MRMgt/SWAccMRCtl/SWAccMRCtl_Thread_1.v new file mode 100644 index 0000000000000000000000000000000000000000..03727c9b3ec00a96df2acf812f1ed5d9db8df96f --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/ICMMgt/MRMgt/SWAccMRCtl/SWAccMRCtl_Thread_1.v @@ -0,0 +1,178 @@ +/*------------------------------------------- Module Description : Begin ---------------------------------------------- +Name: SWAccMRCtl_Thread_1 +Author: YangFan +Function: Demux CEU command to thread_2(MPT processing), thread_3(MTT processing), thread_4(MPT/MTT ICM mapping). +--------------------------------------------- Module Decription : End -----------------------------------------------*/ + +/*------------------------------------------- Timescale Definition : Begin ------------------------------------------*/ +`timescale 1ns / 1ps +/*------------------------------------------- Timescale Definition : End --------------------------------------------*/ + +/*------------------------------------------- Included Files : Begin ------------------------------------------------*/ +`include "protocol_engine_def.vh" +/*------------------------------------------- Included Files : End --------------------------------------------------*/ + +/*------------------------------------------- Input/Output Definition : Begin ---------------------------------------*/ +module SWAccMRCtl_Thread_1 +( + input wire clk, + input wire rst, + +//Interface with CEU + input wire ceu_req_valid, + input wire [`CEU_MR_HEAD_WIDTH - 1 : 0] ceu_req_head, + input wire ceu_req_last, + input wire [`CEU_MR_DATA_WIDTH - 1 : 0] ceu_req_data, + output wire ceu_req_ready, + +//Interface with SWAccCMCtl_Thread_2 + output wire mpt_req_valid, + output wire [`CEU_MR_HEAD_WIDTH - 1 : 0] mpt_req_head, + output wire mpt_req_last, + output wire [`CEU_MR_DATA_WIDTH - 1 : 0] mpt_req_data, + input wire mpt_req_ready, + +//Interface with SWAccCMCtl_Thread_3 + output wire mtt_req_valid, + output wire [`CEU_MR_HEAD_WIDTH - 1 : 0] mtt_req_head, + output wire mtt_req_last, + output wire [`CEU_MR_DATA_WIDTH - 1 : 0] mtt_req_data, + input wire mtt_req_ready, + +//Interface with SWAccCMCtl_Thread_4 + output wire mapping_req_valid, + output wire [`CEU_MR_HEAD_WIDTH - 1 : 0] mapping_req_head, + output wire mapping_req_last, + output wire [`CEU_MR_DATA_WIDTH - 1 : 0] mapping_req_data, + input wire mapping_req_ready + +); +/*------------------------------------------- Input/Output Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Macros Definition : Begin ---------------------------------------*/ +`define CEU_CMD_TYPE_OFFSET 127:124 +/*------------------------------------------- Local Macros Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Variables Definition : Begin ------------------------------------*/ +wire dispatch_req_valid; +wire [`CEU_MR_HEAD_WIDTH - 1 : 0] dispatch_req_head; +wire dispatch_req_last; +wire [`CEU_MR_DATA_WIDTH - 1 : 0] dispatch_req_data; +wire dispatch_req_ready; + +/*------------------------------------------- Local Variables Definition : End --------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : Begin ---------------------------------------*/ +stream_fifo #( + .TUSER_WIDTH (`CEU_MR_HEAD_WIDTH ), + .TDATA_WIDTH (`CEU_MR_DATA_WIDTH ) +) +ceu_req_fifo +( + .clk (clk ), + .rst (rst ), + + .axis_tvalid (ceu_req_valid ), + .axis_tlast (ceu_req_last ), + .axis_tuser (ceu_req_head ), + .axis_tdata (ceu_req_data ), + .axis_tready (ceu_req_ready ), + .axis_tstart (1'b0 ), + .axis_tkeep ('d0 ), + + .in_reg_tvalid (dispatch_req_valid ), + .in_reg_tlast (dispatch_req_last ), + .in_reg_tuser (dispatch_req_head ), + .in_reg_tdata (dispatch_req_data ), + .in_reg_tkeep ( ), + .in_reg_tstart ( ), + .in_reg_tready (dispatch_req_ready ) + /* -------output in_reg inteface{end}------- */ +); + +/*------------------------------------------- Submodules Instatiation : End -----------------------------------------*/ + +/*------------------------------------------- State Machine Definition : Begin --------------------------------------*/ +reg [2:0] cur_state; +reg [2:0] next_state; + +parameter [2:0] IDLE_s = 3'd1, + MPT_s = 3'd2, + MTT_s = 3'd3, + MAPPING_s = 3'd4; + +always @(posedge clk or posedge rst) begin + if (rst) begin + cur_state <= IDLE_s; + end + else begin + cur_state <= next_state; + end +end + +always @(*) begin + case(cur_state) + IDLE_s: if(dispatch_req_valid && dispatch_req_head[`CEU_CMD_TYPE_OFFSET] == `WR_MPT_TPT) begin + next_state = MPT_s; + end + else if(dispatch_req_valid && dispatch_req_head[`CEU_CMD_TYPE_OFFSET] == `WR_MTT_TPT) begin + next_state = MTT_s; + end + else if(dispatch_req_valid && (dispatch_req_head[`CEU_CMD_TYPE_OFFSET] == `WR_ICMMAP_TPT || dispatch_req_head[`CEU_CMD_TYPE_OFFSET] == `MAP_ICM_TPT)) begin + next_state = MAPPING_s; + end + else begin + next_state = IDLE_s; + end + MPT_s: next_state = (dispatch_req_last && dispatch_req_ready) ? IDLE_s : MPT_s; + MTT_s: next_state = (dispatch_req_last && dispatch_req_ready) ? IDLE_s : MTT_s; + MAPPING_s: next_state = (dispatch_req_last && dispatch_req_ready) ? IDLE_s : MAPPING_s; + default: next_state = IDLE_s; + endcase +end +/*------------------------------------------- State Machine Definition : End ----------------------------------------*/ + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ +assign dispatch_req_ready = (cur_state == MPT_s) ? mpt_req_ready : + (cur_state == MTT_s) ? mtt_req_ready : + (cur_state == MAPPING_s) ? mapping_req_ready : 'd0; + +assign mpt_req_valid = (cur_state == MPT_s) ? dispatch_req_valid : 'd0; +assign mpt_req_head = (cur_state == MPT_s) ? dispatch_req_head : 'd0; +assign mpt_req_last = (cur_state == MPT_s) ? dispatch_req_last : 'd0; +assign mpt_req_data = (cur_state == MPT_s) ? dispatch_req_data : 'd0; + +assign mtt_req_valid = (cur_state == MTT_s) ? dispatch_req_valid : 'd0; +assign mtt_req_head = (cur_state == MTT_s) ? dispatch_req_head : 'd0; +assign mtt_req_last = (cur_state == MTT_s) ? dispatch_req_last : 'd0; +assign mtt_req_data = (cur_state == MTT_s) ? dispatch_req_data : 'd0; + +assign mapping_req_valid = (cur_state == MAPPING_s) ? dispatch_req_valid : 'd0; +assign mapping_req_head = (cur_state == MAPPING_s) ? dispatch_req_head : 'd0; +assign mapping_req_last = (cur_state == MAPPING_s) ? dispatch_req_last : 'd0; +assign mapping_req_data = (cur_state == MAPPING_s) ? dispatch_req_data : 'd0; +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ + +/*------------------------------------------- Local Macros Undef : Begin --------------------------------------------*/ +`undef CEU_CMD_TYPE_OFFSET +/*------------------------------------------- Local Macros Undef : End ----------------------------------------------*/ + +`ifdef ILA_ON + ila_ceu_req ila_mr_req_inst( + .clk (clk), + + .probe0(ceu_req_valid), + .probe1(ceu_req_head), + .probe2(ceu_req_data), + .probe3(ceu_req_last), + .probe4(ceu_req_ready), + + .probe5(dispatch_req_valid), + .probe6(dispatch_req_head), + .probe7(dispatch_req_data), + .probe8(dispatch_req_last), + .probe9(dispatch_req_ready) + ); +`endif + +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/ICMMgt/MRMgt/SWAccMRCtl/SWAccMRCtl_Thread_2.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/ICMMgt/MRMgt/SWAccMRCtl/SWAccMRCtl_Thread_2.v new file mode 100644 index 0000000000000000000000000000000000000000..9854056caa0820ee3cbb87c0b72dd3be718ee1ea --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/ICMMgt/MRMgt/SWAccMRCtl/SWAccMRCtl_Thread_2.v @@ -0,0 +1,302 @@ +/*------------------------------------------- Module Description : Begin ---------------------------------------------- +Name: SWAccMRCtl_Thread_2 +Author: YangFan +Function: Handle MPT Wr Command from CEU. +--------------------------------------------- Module Decription : End -----------------------------------------------*/ + +/*------------------------------------------- Timescale Definition : Begin ------------------------------------------*/ +`timescale 1ns / 1ps +/*------------------------------------------- Timescale Definition : End --------------------------------------------*/ + +/*------------------------------------------- Included Files : Begin ------------------------------------------------*/ +`include "protocol_engine_def.vh" +/*------------------------------------------- Included Files : End --------------------------------------------------*/ + + + +/*------------------------------------------- Input/Output Definition : Begin ---------------------------------------*/ +module SWAccMRCtl_Thread_2 +( + input wire clk, + input wire rst, + +//Interface with SWAccCMCtl_Thread_1 + input wire mpt_req_valid, + input wire [`CEU_MR_HEAD_WIDTH - 1 : 0] mpt_req_head, + input wire mpt_req_last, + input wire [`CEU_MR_DATA_WIDTH - 1 : 0] mpt_req_data, + output wire mpt_req_ready, + +//Interface with MPTCache(ICMCache) +//Cache Set Req Interface + output wire cache_set_req_valid, + output wire [`REQ_TAG_NUM_LOG + `COUNT_MAX_LOG * 2 + `ICM_SPACE_ADDR_WIDTH + `PHY_SPACE_ADDR_WIDTH - 1 : 0] cache_set_req_head, + output wire [`CACHE_ENTRY_WIDTH_MPT - 1 : 0] cache_set_req_data, + input wire cache_set_req_ready, + +//ICM Address Translation Interface + output wire icm_mapping_lookup_valid, + output wire [log2b(`ICM_ENTRY_NUM_MPT - 1) - 1 : 0] icm_mapping_lookup_head, + input wire icm_mapping_lookup_ready, + + input wire icm_mapping_rsp_valid, + input wire [`ICM_SPACE_ADDR_WIDTH - 1 : 0] icm_mapping_rsp_icm_addr, + input wire [`PHY_SPACE_ADDR_WIDTH - 1 : 0] icm_mapping_rsp_phy_addr, + output wire icm_mapping_rsp_ready +); + +/*------------------------------------------- Input/Output Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Macros Definition : Begin ---------------------------------------*/ +`define CEU_CMD_OPCODE_OFFSET 123:120 +`define CEU_CMD_INDEX_OFFSET 95:64 +`define MPT_PIECE_NUM 2 //64B (256bit data width) + +`define WR_MPT_CMD_LENGTH_OFFSET 32 * 2 - 1 : 32 * 0 +`define WR_MPT_CMD_START_OFFSET 32 * 4 - 1 : 32 * 2 +`define WR_MPT_CMD_PD_OFFSET 32 * 5 - 1 : 32 * 4 +`define WR_MPT_CMD_KEY_OFFSET 32 * 6 - 1 : 32 * 5 +`define WR_MPT_CMD_PAGE_SIZE_OFFSET 32 * 7 - 1 : 32 * 6 +`define WR_MPT_CMD_FLAGS_OFFSET 32 * 8 - 1 : 32 * 7 + +`define WR_MPT_CMD_MTT_SIZE_OFFSET 32 * 3 - 1 : 32 * 2 +`define WR_MPT_CMD_MTT_SEG_OFFSET 32 * 5 - 1 : 32 * 3 +`define WR_MPT_CMD_WINDOW_OFFSET 32 * 7 - 1 : 32 * 5 +`define WR_MPT_CMD_LKEY_OFFSET 32 * 8 - 1 : 32 * 7 +/*------------------------------------------- Local Macros Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Variables Definition : Begin ------------------------------------*/ +reg [3:0] mpt_piece_count; + +reg [`CEU_MR_HEAD_WIDTH - 1 : 0] mpt_req_head_diff; + +reg [`ICM_SPACE_ADDR_WIDTH - 1 : 0] icm_addr; +reg [`PHY_SPACE_ADDR_WIDTH - 1 : 0] phy_addr; + +wire [`COUNT_MAX_LOG - 1 : 0] count_max; +wire [`COUNT_MAX_LOG - 1 : 0] count_index; + +wire [5:0] req_tag; + +//MPT Info +reg [31:0] flags; +reg [31:0] page_size; +reg [31:0] key; +reg [31:0] pd; +reg [63:0] start; +reg [63:0] length; +reg [63:0] mtt_seg; +/*------------------------------------------- Local Variables Definition : End --------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : Begin ---------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : End -----------------------------------------*/ + +/*------------------------------------------- State Machine Definition : Begin --------------------------------------*/ +reg [2:0] cur_state; +reg [2:0] next_state; + +parameter [2:0] IDLE_s = 3'd1, + ADDR_REQ_s = 3'd2, + ADDR_RSP_s = 3'd3, + MPT_COLLECT_s = 3'd4, + CACHE_SET_s = 3'd5, + MPT_INVALID_s = 3'd6; + +always @(posedge clk or posedge rst) begin + if(rst) begin + cur_state <= IDLE_s; + end + else begin + cur_state <= next_state; + end +end + +always @(*) begin + case(cur_state) + IDLE_s: if(mpt_req_valid) begin + next_state = ADDR_REQ_s; + end + else begin + next_state = IDLE_s; + end + ADDR_REQ_s: if(icm_mapping_lookup_valid && icm_mapping_lookup_ready) begin + next_state = ADDR_RSP_s; + end + else begin + next_state = ADDR_REQ_s; + end + ADDR_RSP_s: if(icm_mapping_rsp_valid && mpt_req_head_diff[`CEU_CMD_OPCODE_OFFSET] == `WR_MPT_WRITE) begin + next_state = MPT_COLLECT_s; + end + else if(icm_mapping_rsp_valid && mpt_req_head_diff[`CEU_CMD_OPCODE_OFFSET] == `WR_MPT_INVALID) begin + next_state = MPT_INVALID_s; + end + else begin + next_state = ADDR_RSP_s; + end + MPT_COLLECT_s: if(mpt_piece_count == `MPT_PIECE_NUM && mpt_req_valid && mpt_req_ready) begin + next_state = CACHE_SET_s; + end + else begin + next_state = MPT_COLLECT_s; + end + CACHE_SET_s: if(cache_set_req_valid && cache_set_req_ready) begin + next_state = IDLE_s; + end + else begin + next_state = CACHE_SET_s; + end + MPT_INVALID_s: next_state = IDLE_s; + default: next_state = IDLE_s; + endcase +end +/*------------------------------------------- State Machine Definition : End ----------------------------------------*/ + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ + +//-- Wr MPT Info -- +always @(posedge clk or posedge rst) begin + if(rst) begin + flags <= 'd0; + page_size <= 'd0; + key <= 'd0; + pd <= 'd0; + start <= 'd0; + length <= 'd0; + mtt_seg <= 'd0; + end + else if(cur_state == IDLE_s) begin + flags <= 'd0; + page_size <= 'd0; + key <= 'd0; + pd <= 'd0; + start <= 'd0; + length <= 'd0; + mtt_seg <= 'd0; + end + else if(cur_state == MPT_COLLECT_s && mpt_req_valid) begin + flags <= (mpt_piece_count == 1) ? mpt_req_data[`WR_MPT_CMD_FLAGS_OFFSET] : flags; + page_size <= (mpt_piece_count == 1) ? mpt_req_data[`WR_MPT_CMD_PAGE_SIZE_OFFSET] : page_size; + key <= (mpt_piece_count == 1) ? mpt_req_data[`WR_MPT_CMD_KEY_OFFSET] : key; + pd <= (mpt_piece_count == 1) ? mpt_req_data[`WR_MPT_CMD_PD_OFFSET] : pd; + start <= (mpt_piece_count == 1) ? mpt_req_data[`WR_MPT_CMD_START_OFFSET] : start; + length <= (mpt_piece_count == 1) ? mpt_req_data[`WR_MPT_CMD_LENGTH_OFFSET] : length; + mtt_seg <= (mpt_piece_count == 2) ? mpt_req_data[`WR_MPT_CMD_MTT_SEG_OFFSET] : mtt_seg; + end + else begin + flags <= flags; + page_size <= page_size; + key <= key; + pd <= pd; + start <= start; + length <= length; + mtt_seg <= mtt_seg; + end +end + +//-- count_max -- +//-- count_index -- +assign count_max = 'd1; //Specific for QPC/EQC/CQC/MPT, 2 for MTT +assign count_index = 'd0; //Specific for QPC/EQC/CQC/MPT, 0, 1 for MTT + +//-- req_tag -- +assign req_tag = 'd0; //Specific for CEU request, RPCCore will use tag start from 1. + +//-- mpt_piece_count -- +always @(posedge clk or posedge rst) begin + if(rst) begin + mpt_piece_count <= 'd0; + end + else if(cur_state == IDLE_s) begin + mpt_piece_count <= 'd0; + end + else if(cur_state == ADDR_RSP_s && next_state == MPT_COLLECT_s) begin + mpt_piece_count <= 'd1; + end + else if(cur_state == MPT_COLLECT_s && mpt_req_valid && mpt_req_ready) begin + mpt_piece_count <= mpt_piece_count + 'd1; + end + else begin + mpt_piece_count <= mpt_piece_count; + end +end + +//-- mpt_req_head_diff -- +always @(posedge clk or posedge rst) begin + if(rst) begin + mpt_req_head_diff <= 'd0; + end + else if(cur_state == IDLE_s && mpt_req_valid) begin + mpt_req_head_diff <= mpt_req_head; + end + else begin + mpt_req_head_diff <= mpt_req_head_diff; + end +end + +//-- icm_addr -- +//-- phy_addr -- +always @(posedge clk or posedge rst) begin + if(rst) begin + icm_addr <= 'd0; + phy_addr <= 'd0; + end + else if(cur_state == IDLE_s) begin + icm_addr <= 'd0; + phy_addr <= 'd0; + end + else if(cur_state == ADDR_RSP_s && icm_mapping_rsp_valid) begin + icm_addr <= icm_mapping_rsp_icm_addr; + phy_addr <= icm_mapping_rsp_phy_addr; + end + else begin + icm_addr <= icm_addr; + phy_addr <= phy_addr; + end +end + +//-- icm_mapping_lookup_valid -- +//-- icm_mapping_lookup_head -- +assign icm_mapping_lookup_valid = (cur_state == ADDR_REQ_s) ? 'd1 : 'd0; +assign icm_mapping_lookup_head = (cur_state == ADDR_REQ_s) ? mpt_req_head_diff[`CEU_CMD_INDEX_OFFSET] : 'd0; //Notice CEU_CMD_INDEX_OFFSET is 32bit, may exceed actual index length, it does not matter + +//-- icm_mapping_rsp_ready -- +assign icm_mapping_rsp_ready = (cur_state == ADDR_RSP_s) ? 'd1 : 'd0; + +//-- cache_set_req_valid -- +//-- cache_set_req_head -- +//-- cache_set_req_data -- +assign cache_set_req_valid = (cur_state == CACHE_SET_s) ? 'd1 : 'd0; +assign cache_set_req_head = (cur_state == CACHE_SET_s) ? {req_tag, count_max, count_index, phy_addr, icm_addr} : 'd0; +assign cache_set_req_data = {mtt_seg, length, start, pd, key, page_size, flags}; + +//-- mpt_req_ready -- +assign mpt_req_ready = (cur_state == MPT_COLLECT_s) ? 'd1 : + (cur_state == MPT_INVALID_s) ? 'd1 : 'd0; + + +//-- icm_mapping_rsp_ready -- +assign icm_mapping_rsp_ready = (cur_state == ADDR_RSP_s) ? 'd1 : 'd0; + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ + +/*------------------------------------------- Local Macros Undef : Begin --------------------------------------------*/ +`undef CEU_CMD_OPCODE_OFFSET +`undef CEU_CMD_INDEX_OFFSET +`undef MPT_PIECE_NUM + +`undef WR_MTT_CMD_LENGTH_OFFSET +`undef WR_MTT_CMD_START_OFFSET +`undef WR_MTT_CMD_PD_OFFSET +`undef WR_MTT_CMD_KEY_OFFSET +`undef WR_MTT_CMD_PAGE_SIZE_OFFSET +`undef WR_MTT_CMD_FLAGS_OFFSET + +`undef WR_MTT_CMD_MTT_SIZE_OFFSET +`undef WR_MTT_CMD_MTT_SEG_OFFSET +`undef WR_MTT_CMD_WINDOW_OFFSET +`undef WR_MTT_CMD_LKEY_OFFSET +/*------------------------------------------- Local Macros Undef : End ----------------------------------------------*/ + +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/ICMMgt/MRMgt/SWAccMRCtl/SWAccMRCtl_Thread_3.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/ICMMgt/MRMgt/SWAccMRCtl/SWAccMRCtl_Thread_3.v new file mode 100644 index 0000000000000000000000000000000000000000..f909e7538e5a5297eb871d9d46ebd35c09ac0040 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/ICMMgt/MRMgt/SWAccMRCtl/SWAccMRCtl_Thread_3.v @@ -0,0 +1,250 @@ +/*------------------------------------------- Module Description : Begin ---------------------------------------------- +Name: SWAccMRCtl_Thread_3 +Author: YangFan +Function: Handle MTT Wr Command from CEU. +--------------------------------------------- Module Decription : End -----------------------------------------------*/ + +/*------------------------------------------- Timescale Definition : Begin ------------------------------------------*/ +`timescale 1ns / 1ps +/*------------------------------------------- Timescale Definition : End --------------------------------------------*/ + +/*------------------------------------------- Included Files : Begin ------------------------------------------------*/ +`include "protocol_engine_def.vh" +/*------------------------------------------- Included Files : End --------------------------------------------------*/ + + + +/*------------------------------------------- Input/Output Definition : Begin ---------------------------------------*/ +module SWAccMRCtl_Thread_3 +( + input wire clk, + input wire rst, + +//Interface with SWAccCMCtl_Thread_1 + input wire mtt_req_valid, + input wire [`CEU_MR_HEAD_WIDTH - 1 : 0] mtt_req_head, + input wire mtt_req_last, + input wire [`CEU_MR_DATA_WIDTH - 1 : 0] mtt_req_data, + output wire mtt_req_ready, + +//Interface with MPTCache(ICMCache) +//Cache Set Req Interface + output wire cache_set_req_valid, + output wire [10 + `ICM_SPACE_ADDR_WIDTH + `PHY_SPACE_ADDR_WIDTH - 1 : 0] cache_set_req_head, + output wire [`CACHE_ENTRY_WIDTH_MTT - 1 : 0] cache_set_req_data, + input wire cache_set_req_ready, + +//ICM Address Translation Interface + output wire icm_mapping_lookup_valid, + output wire [log2b(`ICM_ENTRY_NUM_MTT - 1) - 1 : 0] icm_mapping_lookup_head, + input wire icm_mapping_lookup_ready, + + input wire icm_mapping_rsp_valid, + input wire [`ICM_SPACE_ADDR_WIDTH - 1 : 0] icm_mapping_rsp_icm_addr, + input wire [`PHY_SPACE_ADDR_WIDTH - 1 : 0] icm_mapping_rsp_phy_addr, + output wire icm_mapping_rsp_ready +); + +/*------------------------------------------- Input/Output Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Macros Definition : Begin ---------------------------------------*/ +`define CEU_CMD_OPCODE_OFFSET 127:124 +`define CEU_CMD_MTT_NUM_OFFSET 95:64 +`define CEU_CMD_START_INDEX_OFFSET 63:0 + +/*------------------------------------------- Local Macros Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Variables Definition : Begin ------------------------------------*/ +reg [31:0] mtt_seg_num; +reg [31:0] mtt_write_count; +reg [63:0] mtt_start_index; + +reg [`CEU_MR_HEAD_WIDTH - 1 : 0] mtt_req_head_diff; + +reg [`ICM_SPACE_ADDR_WIDTH - 1 : 0] icm_addr; +reg [`PHY_SPACE_ADDR_WIDTH - 1 : 0] phy_addr; + +wire [1:0] count_max; +wire [1:0] count_index; + +wire [5:0] req_tag; +/*------------------------------------------- Local Variables Definition : End --------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : Begin ---------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : End -----------------------------------------*/ + +/*------------------------------------------- State Machine Definition : Begin --------------------------------------*/ +reg [2:0] cur_state; +reg [2:0] next_state; + +parameter [2:0] IDLE_s = 3'd1, + ADDR_REQ_s = 3'd2, + ADDR_RSP_s = 3'd3, + CACHE_SET_s = 3'd4; + +always @(posedge clk or posedge rst) begin + if(rst) begin + cur_state <= IDLE_s; + end + else begin + cur_state <= next_state; + end +end + +always @(*) begin + case(cur_state) + IDLE_s: if(mtt_req_valid) begin + next_state = ADDR_REQ_s; + end + else begin + next_state = IDLE_s; + end + ADDR_REQ_s: if(icm_mapping_lookup_valid && icm_mapping_lookup_ready) begin + next_state = ADDR_RSP_s; + end + else begin + next_state = ADDR_REQ_s; + end + ADDR_RSP_s: if(icm_mapping_rsp_valid) begin + next_state = CACHE_SET_s; + end + else begin + next_state = ADDR_RSP_s; + end + CACHE_SET_s: if(cache_set_req_valid && cache_set_req_ready) begin + if(mtt_write_count + 1 == mtt_seg_num) begin + next_state = IDLE_s; + end + else begin + next_state = ADDR_REQ_s; + end + end + else begin + next_state = CACHE_SET_s; + end + default: next_state = IDLE_s; + endcase +end +/*------------------------------------------- State Machine Definition : End ----------------------------------------*/ + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ +//-- mtt_seg_num -- +always @(posedge clk or posedge rst) begin + if(rst) begin + mtt_seg_num <= 'd0; + end + else if(cur_state == IDLE_s && mtt_req_valid) begin + mtt_seg_num <= mtt_req_head[`CEU_CMD_MTT_NUM_OFFSET]; + end + else begin + mtt_seg_num <= mtt_seg_num; + end +end + +//-- mtt_start_index -- +always @(posedge clk or posedge rst) begin + if (rst) begin + mtt_start_index <= 'd0; + end + else if (cur_state == IDLE_s && mtt_req_valid) begin + mtt_start_index <= mtt_req_head[`CEU_CMD_START_INDEX_OFFSET]; + end + else begin + mtt_start_index <= mtt_start_index; + end +end + +//-- mtt_write_count -- +always @(posedge clk or posedge rst) begin + if (rst) begin + mtt_write_count <= 'd0; + end + else if (cur_state == IDLE_s && mtt_req_valid) begin + mtt_write_count <= 'd0; + end + else if(cur_state == CACHE_SET_s && cache_set_req_valid && cache_set_req_ready) begin + mtt_write_count <= mtt_write_count + 'd1; + end + else begin + mtt_write_count <= mtt_write_count; + end +end + +//-- icm_addr -- +//-- phy_addr -- +always @(posedge clk or posedge rst) begin + if(rst) begin + icm_addr <= 'd0; + phy_addr <= 'd0; + end + else if(cur_state == IDLE_s) begin + icm_addr <= 'd0; + phy_addr <= 'd0; + end + else if(cur_state == ADDR_RSP_s && icm_mapping_rsp_valid) begin + icm_addr <= icm_mapping_rsp_icm_addr; + phy_addr <= icm_mapping_rsp_phy_addr; + end + else begin + icm_addr <= icm_addr; + phy_addr <= phy_addr; + end +end + +//-- count_max -- +//-- count_index -- +assign count_max = 'd1; //Specific for QPC/EQC/CQC/MPT, 2 for MTT Read +assign count_index = 'd0; //Specific for QPC/EQC/CQC/MPT, 0, 1 for MTT Read + +//-- req_tag -- +assign req_tag = 'd0; //Specific for CEU request, RPCCore will use tag start from 1. + +//-- mtt_req_head_diff -- +always @(posedge clk or posedge rst) begin + if(rst) begin + mtt_req_head_diff <= 'd0; + end + else if(cur_state == IDLE_s && mtt_req_valid) begin + mtt_req_head_diff <= mtt_req_head; + end + else begin + mtt_req_head_diff <= mtt_req_head_diff; + end +end + +//-- icm_mapping_lookup_valid -- +//-- icm_mapping_lookup_head -- +assign icm_mapping_lookup_valid = (cur_state == ADDR_REQ_s) ? 'd1 : 'd0; +assign icm_mapping_lookup_head = (cur_state == ADDR_REQ_s) ? mtt_start_index + mtt_write_count : 'd0; + +//-- icm_mapping_rsp_ready -- +assign icm_mapping_rsp_ready = (cur_state == ADDR_RSP_s) ? 'd1 : 'd0; + +//-- cache_set_req_valid -- +//-- cache_set_req_head -- +//-- cache_set_req_data -- +assign cache_set_req_valid = (cur_state == CACHE_SET_s) ? 'd1 : 'd0; +assign cache_set_req_head = (cur_state == CACHE_SET_s) ? {'d0, phy_addr, icm_addr} : 'd0; +assign cache_set_req_data = (cur_state == CACHE_SET_s && mtt_write_count[1:0] == 0) ? mtt_req_data[63 + 64 * 0 : 0 + 64 * 0] : + (cur_state == CACHE_SET_s && mtt_write_count[1:0] == 1) ? mtt_req_data[63 + 64 * 1 : 0 + 64 * 1] : + (cur_state == CACHE_SET_s && mtt_write_count[1:0] == 2) ? mtt_req_data[63 + 64 * 2 : 0 + 64 * 2] : + (cur_state == CACHE_SET_s && mtt_write_count[1:0] == 3) ? mtt_req_data[63 + 64 * 3 : 0 + 64 * 3] : 'd0; + +//-- mtt_req_ready -- +assign mtt_req_ready = ((cur_state == CACHE_SET_s && next_state == IDLE_s) || (cur_state == CACHE_SET_s && mtt_write_count[1:0] == 3 && cache_set_req_ready)) ? 'd1 : 'd0; + + +//-- icm_mapping_rsp_ready -- +assign icm_mapping_rsp_ready = (cur_state == ADDR_RSP_s) ? 'd1 : 'd0; + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ + +/*------------------------------------------- Local Macros Undef : Begin --------------------------------------------*/ +`undef CEU_CMD_OPCODE_OFFSET +`undef CEU_CMD_INDEX_OFFSET +`undef CEU_CMD_START_INDEX_OFFSET +`undef CEU_CMD_MTT_NUM_OFFSET +/*------------------------------------------- Local Macros Undef : End ----------------------------------------------*/ + +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/ICMMgt/MRMgt/SWAccMRCtl/SWAccMRCtl_Thread_4.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/ICMMgt/MRMgt/SWAccMRCtl/SWAccMRCtl_Thread_4.v new file mode 100644 index 0000000000000000000000000000000000000000..fa1884e2bd4c1f9268de910ae8520474b5a609c7 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/ICMMgt/MRMgt/SWAccMRCtl/SWAccMRCtl_Thread_4.v @@ -0,0 +1,276 @@ +/*------------------------------------------- Module Description : Begin ---------------------------------------------- +Name: SWAccCMCtl_Thread_4 +Author: YangFan +Function: Handle ICMMapping Command from CEU. +--------------------------------------------- Module Decription : End -----------------------------------------------*/ + +/*------------------------------------------- Timescale Definition : Begin ------------------------------------------*/ +`timescale 1ns / 1ps +/*------------------------------------------- Timescale Definition : End --------------------------------------------*/ + +/*------------------------------------------- Included Files : Begin ------------------------------------------------*/ +`include "protocol_engine_def.vh" +/*------------------------------------------- Included Files : End --------------------------------------------------*/ + + +/*------------------------------------------- Input/Output Definition : Begin ---------------------------------------*/ +module SWAccMRCtl_Thread_4 +( + input wire clk, + input wire rst, + +//Interface with SWAccCMCtl_Thread_1 + input wire map_req_valid, + input wire [`CEU_MR_HEAD_WIDTH - 1 : 0] map_req_head, + input wire map_req_last, + input wire [`CEU_MR_DATA_WIDTH - 1 : 0] map_req_data, + output wire map_req_ready, + +//Set MPT ICM Mapping Table Entry + output reg mpt_mapping_set_valid, + output reg [`PAGE_FRAME_WIDTH - 1 : 0] mpt_mapping_set_head, + output reg [`PAGE_FRAME_WIDTH - 1 : 0] mpt_mapping_set_data, + +//Set MTT ICM Mapping Table Entry + output reg mtt_mapping_set_valid, + output reg [`PAGE_FRAME_WIDTH - 1 : 0] mtt_mapping_set_head, + output reg [`PAGE_FRAME_WIDTH - 1 : 0] mtt_mapping_set_data, + + output reg [63:0] mpt_base, + output reg [63:0] mtt_base + +); +/*------------------------------------------- Input/Output Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Macros Definition : Begin ---------------------------------------*/ +`define CEU_CMD_TYPE_OFFSET 127:124 +`define CEU_CMD_OPCODE_OFFSET 123:120 +`define CEU_CMD_CHUNK_NUM_OFFSET 95:64 + +`define MTT_BASE_OFFSET 63:0 +`define MPT_NUM_LOG_OFFSET 71:64 +`define MPT_BASE_OFFSET 127:72 + +`define HIGH_ENTRY_ICM_ADDR_OFFSET 255:192 +`define LOW_ENTRY_ICM_ADDR_OFFSET 127:64 +`define HIGH_ENTRY_PHY_ADDR_OFFSET 191:140 +`define LOW_ENTRY_PHY_ADDR_OFFSET 63:12 +/*------------------------------------------- Local Macros Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Variables Definition : Begin ------------------------------------*/ +reg [31:0] mpt_num; + +reg [63:0] mpt_end; + + +reg [31:0] chunk_num_left; + + +wire [63:0] icm_addr; +wire [51:0] phy_addr; +wire [63:0] mpt_addr; +wire [63:0] mtt_addr; + +wire is_mpt_mapping; +wire is_mtt_mapping; + +/*------------------------------------------- Local Variables Definition : End --------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : Begin ---------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : End -----------------------------------------*/ + +/*------------------------------------------- State Machine Definition : Begin --------------------------------------*/ +reg [2:0] cur_state; +reg [2:0] next_state; + +parameter [2:0] IDLE_s = 3'd1, + MAP_BASE_s = 3'd2, + MAP_HIGH_s = 3'd3, + MAP_LOW_s = 3'd4, + MAP_DIS_s = 3'd5, + ICM_DIS_s = 3'd6; + +always @(posedge clk or posedge rst) begin + if (rst) begin + cur_state <= IDLE_s; + end + else begin + cur_state <= next_state; + end +end + +always @(*) begin + case(cur_state) + IDLE_s: if(map_req_valid) begin + if(map_req_head[`CEU_CMD_TYPE_OFFSET] == `WR_ICMMAP_TPT && map_req_head[`CEU_CMD_OPCODE_OFFSET] == `WR_ICMMAP_EN) begin + next_state = MAP_BASE_s; + end + else if(map_req_head[`CEU_CMD_TYPE_OFFSET] == `WR_ICMMAP_TPT && map_req_head[`CEU_CMD_OPCODE_OFFSET] == `WR_ICMMAP_DIS) begin + next_state = MAP_DIS_s; + end + else if(map_req_head[`CEU_CMD_TYPE_OFFSET] == `MAP_ICM_TPT && map_req_head[`CEU_CMD_OPCODE_OFFSET] == `MAP_ICM_EN) begin + next_state = MAP_LOW_s; + end + else if(map_req_head[`CEU_CMD_TYPE_OFFSET] == `MAP_ICM_TPT && map_req_head[`CEU_CMD_OPCODE_OFFSET] == `MAP_ICM_DIS) begin + next_state = ICM_DIS_s; + end + else begin + next_state = IDLE_s; + end + end + else begin + next_state = IDLE_s; + end + MAP_BASE_s: next_state = IDLE_s; + MAP_HIGH_s: if(map_req_valid && chunk_num_left == 1) begin + next_state = IDLE_s; + end + else if(map_req_valid && chunk_num_left > 1) begin + next_state = MAP_LOW_s; + end + else begin + next_state = MAP_HIGH_s; + end + MAP_LOW_s: if(map_req_valid && chunk_num_left == 1) begin + next_state = IDLE_s; + end + else if(map_req_valid && chunk_num_left > 1) begin + next_state = MAP_HIGH_s; + end + else begin + next_state = MAP_LOW_s; + end + default: next_state = IDLE_s; + endcase +end +/*------------------------------------------- State Machine Definition : End ----------------------------------------*/ + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ +//-- icm_addr -- +assign icm_addr = (cur_state == MAP_HIGH_s && map_req_valid) ? map_req_data[`HIGH_ENTRY_ICM_ADDR_OFFSET] : + (cur_state == MAP_LOW_s && map_req_valid) ? map_req_data[`LOW_ENTRY_ICM_ADDR_OFFSET] : 'd0; + +//-- phy_addr -- +assign phy_addr = (cur_state == MAP_HIGH_s && map_req_valid) ? map_req_data[`HIGH_ENTRY_PHY_ADDR_OFFSET] : + (cur_state == MAP_LOW_s && map_req_valid) ? map_req_data[`LOW_ENTRY_PHY_ADDR_OFFSET] : 'd0; + +//-- is_mpt_mapping -- +//-- is_mtt_mapping -- +assign is_mpt_mapping = ((cur_state == MAP_HIGH_s || cur_state == MAP_LOW_s) && map_req_valid) && (icm_addr >= mpt_base && icm_addr < mpt_end) ? 'd1 : 'd0; +assign is_mtt_mapping = ((cur_state == MAP_HIGH_s || cur_state == MAP_LOW_s) && map_req_valid) && (icm_addr < mpt_base || icm_addr >= mpt_end) ? 'd1 : 'd0; + +//-- mpt_addr -- +//-- mtt_addr -- +assign mpt_addr = is_mpt_mapping ? icm_addr[63:12] : 'd0; //Only need ICM Page Frame +assign mtt_addr = is_mtt_mapping ? icm_addr[63:12] : 'd0; + +//-- chunk_num_left -- +always @(posedge clk or posedge rst) begin + if(rst) begin + chunk_num_left <= 'd0; + end + else if(cur_state == IDLE_s && map_req_valid && map_req_head[`CEU_CMD_TYPE_OFFSET == `MAP_ICM_TPT] && map_req_head[`CEU_CMD_OPCODE_OFFSET] == `MAP_ICM_EN) begin + chunk_num_left <= map_req_head[`CEU_CMD_CHUNK_NUM_OFFSET]; + end + else if(cur_state == MAP_HIGH_s && map_req_valid) begin + chunk_num_left <= chunk_num_left - 'd1; + end + else if(cur_state == MAP_LOW_s && map_req_valid) begin + chunk_num_left <= chunk_num_left - 'd1; + end + else begin + chunk_num_left <= chunk_num_left; + end +end + +//-- mpt_base -- +//-- mpt_end -- +//-- mtt_base -- +always @(posedge clk or posedge rst) begin + if(rst) begin + mpt_base <= 'd0; + mpt_num <= 'd0; + mpt_end <= 'd0; + mtt_base <= 'd0; + end + else if(cur_state == MAP_BASE_s) begin + mpt_base <= {map_req_data[`MPT_BASE_OFFSET], 8'd0}; + mpt_num <= 1 << map_req_data[`MPT_NUM_LOG_OFFSET]; + mpt_end <= {map_req_data[`MPT_BASE_OFFSET], 8'd0} + (1 << map_req_data[`MPT_NUM_LOG_OFFSET]) * `ICM_SLOT_SIZE_MPT; + mtt_base <= map_req_data[`MTT_BASE_OFFSET]; + end + else begin + mpt_base <= mpt_base; + mpt_num <= mpt_num; + mpt_end <= mpt_end; + mtt_base <= mtt_base; + end +end + + +//-- mpt_mapping_set_valid -- +//-- mpt_mapping_set_head -- +//-- mpt_mapping_set_data -- +//-- mtt_mapping_set_valid -- +//-- mtt_mapping_set_head -- +//-- mtt_mapping_set_data -- +always @(posedge clk or posedge rst) begin + if(rst) begin + mpt_mapping_set_valid <= 'd0; + mpt_mapping_set_head <= 'd0; + mpt_mapping_set_data <= 'd0; + + mtt_mapping_set_valid <= 'd0; + mtt_mapping_set_head <= 'd0; + mtt_mapping_set_data <= 'd0; + end + else if(cur_state == MAP_HIGH_s && map_req_valid) begin + mpt_mapping_set_valid <= is_mpt_mapping ? 'd1 : 'd0; + mpt_mapping_set_head <= is_mpt_mapping ? mpt_addr : 'd0; + mpt_mapping_set_data <= is_mpt_mapping ? phy_addr : 'd0; + + mtt_mapping_set_valid <= is_mtt_mapping ? 'd1 : 'd0; + mtt_mapping_set_head <= is_mtt_mapping ? mtt_addr : 'd0; + mtt_mapping_set_data <= is_mtt_mapping ? phy_addr : 'd0; + end + else if(cur_state == MAP_LOW_s && map_req_valid) begin + mpt_mapping_set_valid <= is_mpt_mapping ? 'd1 : 'd0; + mpt_mapping_set_head <= is_mpt_mapping ? mpt_addr : 'd0; + mpt_mapping_set_data <= is_mpt_mapping ? phy_addr : 'd0; + + mtt_mapping_set_valid <= is_mtt_mapping ? 'd1 : 'd0; + mtt_mapping_set_head <= is_mtt_mapping ? mtt_addr : 'd0; + mtt_mapping_set_data <= is_mtt_mapping ? phy_addr : 'd0; + end + else begin + mpt_mapping_set_valid <= 'd0; + mpt_mapping_set_head <= 'd0; + mpt_mapping_set_data <= 'd0; + + mtt_mapping_set_valid <= 'd0; + mtt_mapping_set_head <= 'd0; + mtt_mapping_set_data <= 'd0; + end +end + +//-- map_req_ready -- +assign map_req_ready = (cur_state == MAP_BASE_s) ? 'd1 : + (cur_state == MAP_LOW_s) ? 'd1 : + (cur_state == MAP_HIGH_s && chunk_num_left == 1) ? 'd1 : + (cur_state == MAP_DIS_s) ? 'd1 : + (cur_state == ICM_DIS_s) ? 'd1 : 'd0; + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ + +/*------------------------------------------- Local Macros Undef : Begin --------------------------------------------*/ +`undef CEU_CMD_TYPE_OFFSET +`undef CEU_CMD_OPCODE_OFFSET +`undef CEU_CMD_CHUNK_NUM_OFFSET + +`undef MPT_BASE_OFFSET +`undef MTT_BASE_OFFSET +`undef MPT_NUM_LOG_OFFSET +/*------------------------------------------- Local Macros Undef : End ----------------------------------------------*/ + +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/ResMgtSubsystem.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/ResMgtSubsystem.v new file mode 100644 index 0000000000000000000000000000000000000000..67dc888018f9280f495201288d6899ec59372acc --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/ResMgtSubsystem/ResMgtSubsystem.v @@ -0,0 +1,1194 @@ +/*------------------------------------------- Module Description : Begin ---------------------------------------------- +Name: ResMgtSubsystem +Author: YangFan +Function: Manage various communication resources, controlled by both Sotware(CPU) and Hardware(RDMACore). +--------------------------------------------- Module Decription : End -----------------------------------------------*/ + +/*------------------------------------------- Timescale Definition : Begin ------------------------------------------*/ +`timescale 1ns / 1ps +/*------------------------------------------- Timescale Definition : End --------------------------------------------*/ + +/*------------------------------------------- Included Files : Begin ------------------------------------------------*/ +`include "protocol_engine_def.vh" +/*------------------------------------------- Included Files : End --------------------------------------------------*/ + +/*------------------------------------------- Local Macros Definition : Begin ---------------------------------------*/ +/*------------------------------------------- Local Macros Definition : End -----------------------------------------*/ + +/*------------------------------------------- Input/Output Definition : Begin ---------------------------------------*/ +module ResMgtSubsystem +#( + parameter INGRESS_CXT_HEAD_WIDTH = 128, + parameter INGRESS_CXT_DATA_WIDTH = 256, + parameter EGRESS_CXT_HEAD_WIDTH = 128, + parameter EGRESS_CXT_DATA_WIDTH = 256, + + parameter INGRESS_MR_HEAD_WIDTH = 128, + parameter INGRESS_MR_DATA_WIDTH = 256, + parameter EGRESS_MR_HEAD_WIDTH = 128, + parameter EGRESS_MR_DATA_WIDTH = 256 +) +( + input wire clk, + input wire rst, + +//Interface for CEU + input wire [63:0] ceu_hcr_in_param, + input wire [31:0] ceu_hcr_in_modifier, + input wire [63:0] ceu_hcr_out_dma_addr, + input wire [31:0] ceu_hcr_token, + input wire ceu_hcr_go, + input wire ceu_hcr_event, + input wire [7:0] ceu_hcr_op_modifier, + input wire [11:0] ceu_hcr_op, + + output wire [63:0] ceu_hcr_out_param, + output wire [7:0] ceu_hcr_status, + output wire ceu_hcr_clear, + + output wire CEU_dma_rd_req_valid, + output wire CEU_dma_rd_req_last, + output wire [`DMA_HEAD_WIDTH - 1 : 0] CEU_dma_rd_req_head, + output wire [`DMA_DATA_WIDTH - 1 : 0] CEU_dma_rd_req_data, + input wire CEU_dma_rd_req_ready, + + input wire CEU_dma_rd_rsp_valid, + input wire CEU_dma_rd_rsp_last, + input wire [`DMA_HEAD_WIDTH - 1 : 0] CEU_dma_rd_rsp_head, + input wire [`DMA_DATA_WIDTH - 1 : 0] CEU_dma_rd_rsp_data, + output wire CEU_dma_rd_rsp_ready, + + output wire CEU_dma_wr_req_valid, + output wire CEU_dma_wr_req_last, + output wire [`DMA_HEAD_WIDTH - 1 : 0] CEU_dma_wr_req_head, + output wire [`DMA_DATA_WIDTH - 1 : 0] CEU_dma_wr_req_data, + input wire CEU_dma_wr_req_ready, + + input wire SQ_fetch_cxt_ingress_valid, + input wire [`SQ_OOO_CXT_INGRESS_HEAD_WIDTH - 1 : 0] SQ_fetch_cxt_ingress_head, + input wire [`SQ_OOO_CXT_INGRESS_DATA_WIDTH - 1 : 0] SQ_fetch_cxt_ingress_data, + input wire SQ_fetch_cxt_ingress_start, + input wire SQ_fetch_cxt_ingress_last, + output wire SQ_fetch_cxt_ingress_ready, + + output wire SQ_fetch_cxt_egress_valid, + output wire [`SQ_OOO_CXT_EGRESS_HEAD_WIDTH - 1 : 0] SQ_fetch_cxt_egress_head, + output wire [`SQ_OOO_CXT_EGRESS_DATA_WIDTH - 1 : 0] SQ_fetch_cxt_egress_data, + output wire SQ_fetch_cxt_egress_start, + output wire SQ_fetch_cxt_egress_last, + input wire SQ_fetch_cxt_egress_ready, + + + + input wire TX_REQ_fetch_cxt_ingress_valid, + input wire [`TX_REQ_OOO_CXT_INGRESS_HEAD_WIDTH - 1 : 0] TX_REQ_fetch_cxt_ingress_head, + input wire [`TX_REQ_OOO_CXT_INGRESS_DATA_WIDTH - 1 : 0] TX_REQ_fetch_cxt_ingress_data, + input wire TX_REQ_fetch_cxt_ingress_start, + input wire TX_REQ_fetch_cxt_ingress_last, + output wire TX_REQ_fetch_cxt_ingress_ready, + + output wire TX_REQ_fetch_cxt_egress_valid, + output wire [`TX_REQ_OOO_CXT_EGRESS_HEAD_WIDTH - 1 : 0] TX_REQ_fetch_cxt_egress_head, + output wire [`TX_REQ_OOO_CXT_EGRESS_DATA_WIDTH - 1 : 0] TX_REQ_fetch_cxt_egress_data, + output wire TX_REQ_fetch_cxt_egress_start, + output wire TX_REQ_fetch_cxt_egress_last, + input wire TX_REQ_fetch_cxt_egress_ready, + + input wire RX_REQ_fetch_cxt_ingress_valid, + input wire [`RX_REQ_OOO_CXT_INGRESS_HEAD_WIDTH - 1 : 0] RX_REQ_fetch_cxt_ingress_head, + input wire [`RX_REQ_OOO_CXT_INGRESS_DATA_WIDTH - 1 : 0] RX_REQ_fetch_cxt_ingress_data, + input wire RX_REQ_fetch_cxt_ingress_start, + input wire RX_REQ_fetch_cxt_ingress_last, + output wire RX_REQ_fetch_cxt_ingress_ready, + + output wire RX_REQ_fetch_cxt_egress_valid, + output wire [`RX_REQ_OOO_CXT_EGRESS_HEAD_WIDTH - 1 : 0] RX_REQ_fetch_cxt_egress_head, + output wire [`RX_REQ_OOO_CXT_EGRESS_DATA_WIDTH - 1 : 0] RX_REQ_fetch_cxt_egress_data, + output wire RX_REQ_fetch_cxt_egress_start, + output wire RX_REQ_fetch_cxt_egress_last, + input wire RX_REQ_fetch_cxt_egress_ready, + + input wire RX_RESP_fetch_cxt_ingress_valid, + input wire [`RX_RESP_OOO_CXT_INGRESS_HEAD_WIDTH - 1 : 0] RX_RESP_fetch_cxt_ingress_head, + input wire [`RX_RESP_OOO_CXT_INGRESS_DATA_WIDTH - 1 : 0] RX_RESP_fetch_cxt_ingress_data, + input wire RX_RESP_fetch_cxt_ingress_start, + input wire RX_RESP_fetch_cxt_ingress_last, + output wire RX_RESP_fetch_cxt_ingress_ready, + + output wire RX_RESP_fetch_cxt_egress_valid, + output wire [`RX_RESP_OOO_CXT_EGRESS_HEAD_WIDTH - 1 : 0] RX_RESP_fetch_cxt_egress_head, + output wire [`RX_RESP_OOO_CXT_EGRESS_DATA_WIDTH - 1 : 0] RX_RESP_fetch_cxt_egress_data, + output wire RX_RESP_fetch_cxt_egress_start, + output wire RX_RESP_fetch_cxt_egress_last, + input wire RX_RESP_fetch_cxt_egress_ready, + + input wire SQ_fetch_mr_ingress_valid, + input wire [`SQ_OOO_MR_INGRESS_HEAD_WIDTH - 1 : 0] SQ_fetch_mr_ingress_head, + input wire [`SQ_OOO_MR_INGRESS_DATA_WIDTH - 1 : 0] SQ_fetch_mr_ingress_data, + input wire SQ_fetch_mr_ingress_start, + input wire SQ_fetch_mr_ingress_last, + output wire SQ_fetch_mr_ingress_ready, + + output wire SQ_fetch_mr_egress_valid, + output wire [`SQ_OOO_MR_EGRESS_HEAD_WIDTH - 1 : 0] SQ_fetch_mr_egress_head, + output wire [`SQ_OOO_MR_EGRESS_DATA_WIDTH - 1 : 0] SQ_fetch_mr_egress_data, + output wire SQ_fetch_mr_egress_start, + output wire SQ_fetch_mr_egress_last, + input wire SQ_fetch_mr_egress_ready, + + input wire RQ_fetch_mr_ingress_valid, + input wire [`RQ_OOO_MR_INGRESS_HEAD_WIDTH - 1 : 0] RQ_fetch_mr_ingress_head, + input wire [`RQ_OOO_MR_INGRESS_DATA_WIDTH - 1 : 0] RQ_fetch_mr_ingress_data, + input wire RQ_fetch_mr_ingress_start, + input wire RQ_fetch_mr_ingress_last, + output wire RQ_fetch_mr_ingress_ready, + + output wire RQ_fetch_mr_egress_valid, + output wire [`RQ_OOO_MR_EGRESS_HEAD_WIDTH - 1 : 0] RQ_fetch_mr_egress_head, + output wire [`RQ_OOO_MR_EGRESS_DATA_WIDTH - 1 : 0] RQ_fetch_mr_egress_data, + output wire RQ_fetch_mr_egress_start, + output wire RQ_fetch_mr_egress_last, + input wire RQ_fetch_mr_egress_ready, + + input wire TX_REQ_fetch_mr_ingress_valid, + input wire [`TX_REQ_OOO_MR_INGRESS_HEAD_WIDTH - 1 : 0] TX_REQ_fetch_mr_ingress_head, + input wire [`TX_REQ_OOO_MR_INGRESS_DATA_WIDTH - 1 : 0] TX_REQ_fetch_mr_ingress_data, + input wire TX_REQ_fetch_mr_ingress_start, + input wire TX_REQ_fetch_mr_ingress_last, + output wire TX_REQ_fetch_mr_ingress_ready, + + output wire TX_REQ_fetch_mr_egress_valid, + output wire [`TX_REQ_OOO_MR_EGRESS_HEAD_WIDTH - 1 : 0] TX_REQ_fetch_mr_egress_head, + output wire [`TX_REQ_OOO_MR_EGRESS_DATA_WIDTH - 1 : 0] TX_REQ_fetch_mr_egress_data, + output wire TX_REQ_fetch_mr_egress_start, + output wire TX_REQ_fetch_mr_egress_last, + input wire TX_REQ_fetch_mr_egress_ready, + + input wire RX_RESP_fetch_mr_ingress_valid, + input wire [`RX_RESP_OOO_MR_INGRESS_HEAD_WIDTH - 1 : 0] RX_RESP_fetch_mr_ingress_head, + input wire [`RX_RESP_OOO_MR_INGRESS_DATA_WIDTH - 1 : 0] RX_RESP_fetch_mr_ingress_data, + input wire RX_RESP_fetch_mr_ingress_start, + input wire RX_RESP_fetch_mr_ingress_last, + output wire RX_RESP_fetch_mr_ingress_ready, + + output wire RX_RESP_fetch_mr_egress_valid, + output wire [`RX_RESP_OOO_MR_EGRESS_HEAD_WIDTH - 1 : 0] RX_RESP_fetch_mr_egress_head, + output wire [`RX_RESP_OOO_MR_EGRESS_DATA_WIDTH - 1 : 0] RX_RESP_fetch_mr_egress_data, + output wire RX_RESP_fetch_mr_egress_start, + output wire RX_RESP_fetch_mr_egress_last, + input wire RX_RESP_fetch_mr_egress_ready, + + input wire RX_REQ_fetch_mr_ingress_valid, + input wire [`RX_REQ_OOO_MR_INGRESS_HEAD_WIDTH - 1 : 0] RX_REQ_fetch_mr_ingress_head, + input wire [`RX_REQ_OOO_MR_INGRESS_DATA_WIDTH - 1 : 0] RX_REQ_fetch_mr_ingress_data, + input wire RX_REQ_fetch_mr_ingress_start, + input wire RX_REQ_fetch_mr_ingress_last, + output wire RX_REQ_fetch_mr_ingress_ready, + + output wire RX_REQ_fetch_mr_egress_valid, + output wire [`RX_REQ_OOO_MR_EGRESS_HEAD_WIDTH - 1 : 0] RX_REQ_fetch_mr_egress_head, + output wire [`RX_REQ_OOO_MR_EGRESS_DATA_WIDTH - 1 : 0] RX_REQ_fetch_mr_egress_data, + output wire RX_REQ_fetch_mr_egress_start, + output wire RX_REQ_fetch_mr_egress_last, + input wire RX_REQ_fetch_mr_egress_ready, + +//Interface with DMA + output wire QPC_dma_rd_req_valid, + output wire [`DMA_HEAD_WIDTH - 1 : 0] QPC_dma_rd_req_head, + output wire [`DMA_DATA_WIDTH - 1 : 0] QPC_dma_rd_req_data, + output wire QPC_dma_rd_req_last, + input wire QPC_dma_rd_req_ready, + + input wire QPC_dma_rd_rsp_valid, + input wire [`DMA_HEAD_WIDTH - 1 : 0] QPC_dma_rd_rsp_head, + input wire [`DMA_DATA_WIDTH - 1 : 0] QPC_dma_rd_rsp_data, + input wire QPC_dma_rd_rsp_last, + output wire QPC_dma_rd_rsp_ready, + + output wire QPC_dma_wr_req_valid, + output wire [`DMA_HEAD_WIDTH - 1 : 0] QPC_dma_wr_req_head, + output wire [`DMA_DATA_WIDTH - 1 : 0] QPC_dma_wr_req_data, + output wire QPC_dma_wr_req_last, + input wire QPC_dma_wr_req_ready, + + output wire CQC_dma_rd_req_valid, + output wire [`DMA_HEAD_WIDTH - 1 : 0] CQC_dma_rd_req_head, + output wire [`DMA_DATA_WIDTH - 1 : 0] CQC_dma_rd_req_data, + output wire CQC_dma_rd_req_last, + input wire CQC_dma_rd_req_ready, + + input wire CQC_dma_rd_rsp_valid, + input wire [`DMA_HEAD_WIDTH - 1 : 0] CQC_dma_rd_rsp_head, + input wire [`DMA_DATA_WIDTH - 1 : 0] CQC_dma_rd_rsp_data, + input wire CQC_dma_rd_rsp_last, + output wire CQC_dma_rd_rsp_ready, + + output wire CQC_dma_wr_req_valid, + output wire [`DMA_HEAD_WIDTH - 1 : 0] CQC_dma_wr_req_head, + output wire [`DMA_DATA_WIDTH - 1 : 0] CQC_dma_wr_req_data, + output wire CQC_dma_wr_req_last, + input wire CQC_dma_wr_req_ready, + + output wire EQC_dma_rd_req_valid, + output wire [`DMA_HEAD_WIDTH - 1 : 0] EQC_dma_rd_req_head, + output wire [`DMA_DATA_WIDTH - 1 : 0] EQC_dma_rd_req_data, + output wire EQC_dma_rd_req_last, + input wire EQC_dma_rd_req_ready, + + input wire EQC_dma_rd_rsp_valid, + input wire [`DMA_HEAD_WIDTH - 1 : 0] EQC_dma_rd_rsp_head, + input wire [`DMA_DATA_WIDTH - 1 : 0] EQC_dma_rd_rsp_data, + input wire EQC_dma_rd_rsp_last, + output wire EQC_dma_rd_rsp_ready, + + output wire EQC_dma_wr_req_valid, + output wire [`DMA_HEAD_WIDTH - 1 : 0] EQC_dma_wr_req_head, + output wire [`DMA_DATA_WIDTH - 1 : 0] EQC_dma_wr_req_data, + output wire EQC_dma_wr_req_last, + input wire EQC_dma_wr_req_ready, + +//Interface with DMA + output wire MPT_dma_rd_req_valid, + output wire [`DMA_HEAD_WIDTH - 1 : 0] MPT_dma_rd_req_head, + output wire [`DMA_DATA_WIDTH - 1 : 0] MPT_dma_rd_req_data, + output wire MPT_dma_rd_req_last, + input wire MPT_dma_rd_req_ready, + + input wire MPT_dma_rd_rsp_valid, + input wire [`DMA_HEAD_WIDTH - 1 : 0] MPT_dma_rd_rsp_head, + input wire [`DMA_DATA_WIDTH - 1 : 0] MPT_dma_rd_rsp_data, + input wire MPT_dma_rd_rsp_last, + output wire MPT_dma_rd_rsp_ready, + + output wire MPT_dma_wr_req_valid, + output wire [`DMA_HEAD_WIDTH - 1 : 0] MPT_dma_wr_req_head, + output wire [`DMA_DATA_WIDTH - 1 : 0] MPT_dma_wr_req_data, + output wire MPT_dma_wr_req_last, + input wire MPT_dma_wr_req_ready, + + output wire MTT_dma_rd_req_valid, + output wire [`DMA_HEAD_WIDTH - 1 : 0] MTT_dma_rd_req_head, + output wire [`DMA_DATA_WIDTH - 1 : 0] MTT_dma_rd_req_data, + output wire MTT_dma_rd_req_last, + input wire MTT_dma_rd_req_ready, + + input wire MTT_dma_rd_rsp_valid, + input wire [`DMA_HEAD_WIDTH - 1 : 0] MTT_dma_rd_rsp_head, + input wire [`DMA_DATA_WIDTH - 1 : 0] MTT_dma_rd_rsp_data, + input wire MTT_dma_rd_rsp_last, + output wire MTT_dma_rd_rsp_ready, + + output wire MTT_dma_wr_req_valid, + output wire [`DMA_HEAD_WIDTH - 1 : 0] MTT_dma_wr_req_head, + output wire [`DMA_DATA_WIDTH - 1 : 0] MTT_dma_wr_req_data, + output wire MTT_dma_wr_req_last, + input wire MTT_dma_wr_req_ready +); + +/*------------------------------------------- Input/Output Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Variables Definition : Begin ------------------------------------*/ +wire ceu_cxt_req_valid; +wire [`CEU_CXT_HEAD_WIDTH - 1 : 0] ceu_cxt_req_head; +wire ceu_cxt_req_last; +wire [`CEU_CXT_DATA_WIDTH - 1 : 0] ceu_cxt_req_data; +wire ceu_cxt_req_ready; + +wire ceu_cxt_rsp_valid; +wire [`CEU_CXT_HEAD_WIDTH - 1 : 0] ceu_cxt_rsp_head; +wire ceu_cxt_rsp_last; +wire [`CEU_CXT_DATA_WIDTH - 1 : 0] ceu_cxt_rsp_data; +wire ceu_cxt_rsp_ready; + +wire ceu_mr_req_valid; +wire [`CEU_MR_HEAD_WIDTH - 1 : 0] ceu_mr_req_head; +wire ceu_mr_req_last; +wire [`CEU_MR_DATA_WIDTH - 1 : 0] ceu_mr_req_data; +wire ceu_mr_req_ready; + +wire SQ_mr_req_valid; +wire [`MR_CMD_HEAD_WIDTH + `MAX_REQ_TAG_NUM_LOG - 1 : 0] SQ_mr_req_head; +wire [`MR_CMD_DATA_WIDTH - 1 : 0] SQ_mr_req_data; +wire SQ_mr_req_ready; + +wire SQ_mr_rsp_valid; +wire [`MR_CMD_HEAD_WIDTH + `MAX_REQ_TAG_NUM_LOG - 1 : 0] SQ_mr_rsp_head; +wire [`MR_CMD_DATA_WIDTH - 1 : 0] SQ_mr_rsp_data; +wire SQ_mr_rsp_ready; + +wire RQ_mr_req_valid; +wire [`MR_CMD_HEAD_WIDTH + `MAX_REQ_TAG_NUM_LOG - 1 : 0] RQ_mr_req_head; +wire [`MR_CMD_DATA_WIDTH - 1 : 0] RQ_mr_req_data; +wire RQ_mr_req_ready; + +wire RQ_mr_rsp_valid; +wire [`MR_CMD_HEAD_WIDTH + `MAX_REQ_TAG_NUM_LOG - 1 : 0] RQ_mr_rsp_head; +wire [`MR_CMD_DATA_WIDTH - 1 : 0] RQ_mr_rsp_data; +wire RQ_mr_rsp_ready; + +wire TX_REQ_mr_req_valid; +wire [`MR_CMD_HEAD_WIDTH + `MAX_REQ_TAG_NUM_LOG - 1 : 0] TX_REQ_mr_req_head; +wire [`MR_CMD_DATA_WIDTH - 1 : 0] TX_REQ_mr_req_data; +wire TX_REQ_mr_req_ready; + +wire TX_REQ_mr_rsp_valid; +wire [`MR_CMD_HEAD_WIDTH + `MAX_REQ_TAG_NUM_LOG - 1 : 0] TX_REQ_mr_rsp_head; +wire [`MR_CMD_DATA_WIDTH - 1 : 0] TX_REQ_mr_rsp_data; +wire TX_REQ_mr_rsp_ready; + +wire RX_REQ_mr_req_valid; +wire [`MR_CMD_HEAD_WIDTH + `MAX_REQ_TAG_NUM_LOG - 1 : 0] RX_REQ_mr_req_head; +wire [`MR_CMD_DATA_WIDTH - 1 : 0] RX_REQ_mr_req_data; +wire RX_REQ_mr_req_ready; + +wire RX_REQ_mr_rsp_valid; +wire [`MR_CMD_HEAD_WIDTH + `MAX_REQ_TAG_NUM_LOG - 1 : 0] RX_REQ_mr_rsp_head; +wire [`MR_CMD_DATA_WIDTH - 1 : 0] RX_REQ_mr_rsp_data; +wire RX_REQ_mr_rsp_ready; + +wire RX_RESP_mr_req_valid; +wire [`MR_CMD_HEAD_WIDTH + `MAX_REQ_TAG_NUM_LOG - 1 : 0] RX_RESP_mr_req_head; +wire [`MR_CMD_DATA_WIDTH - 1 : 0] RX_RESP_mr_req_data; +wire RX_RESP_mr_req_ready; + +wire RX_RESP_mr_rsp_valid; +wire [`MR_CMD_HEAD_WIDTH + `MAX_REQ_TAG_NUM_LOG - 1 : 0] RX_RESP_mr_rsp_head; +wire [`MR_CMD_DATA_WIDTH - 1 : 0] RX_RESP_mr_rsp_data; +wire RX_RESP_mr_rsp_ready; + +wire SQ_cxt_req_valid; +wire [`CXT_CMD_HEAD_WIDTH + `MAX_REQ_TAG_NUM_LOG - 1 : 0] SQ_cxt_req_head; +wire [`CXT_CMD_DATA_WIDTH - 1 : 0] SQ_cxt_req_data; +wire SQ_cxt_req_ready; + +wire SQ_cxt_rsp_valid; +wire [`CXT_RESP_HEAD_WIDTH + `MAX_REQ_TAG_NUM_LOG - 1 : 0] SQ_cxt_rsp_head; +wire [`CXT_RESP_DATA_WIDTH - 1 : 0] SQ_cxt_rsp_data; +wire SQ_cxt_rsp_ready; + +wire TX_REQ_cxt_req_valid; +wire [`CXT_CMD_HEAD_WIDTH + `MAX_REQ_TAG_NUM_LOG - 1 : 0] TX_REQ_cxt_req_head; +wire [`CXT_CMD_DATA_WIDTH - 1 : 0] TX_REQ_cxt_req_data; +wire TX_REQ_cxt_req_ready; + +wire TX_REQ_cxt_rsp_valid; +wire [`CXT_RESP_HEAD_WIDTH + `MAX_REQ_TAG_NUM_LOG - 1 : 0] TX_REQ_cxt_rsp_head; +wire [`CXT_RESP_DATA_WIDTH - 1 : 0] TX_REQ_cxt_rsp_data; +wire TX_REQ_cxt_rsp_ready; + +wire RX_REQ_cxt_req_valid; +wire [`CXT_CMD_HEAD_WIDTH + `MAX_REQ_TAG_NUM_LOG - 1 : 0] RX_REQ_cxt_req_head; +wire [`CXT_CMD_DATA_WIDTH - 1 : 0] RX_REQ_cxt_req_data; +wire RX_REQ_cxt_req_ready; + +wire RX_REQ_cxt_rsp_valid; +wire [`CXT_RESP_HEAD_WIDTH + `MAX_REQ_TAG_NUM_LOG - 1 : 0] RX_REQ_cxt_rsp_head; +wire [`CXT_RESP_DATA_WIDTH - 1 : 0] RX_REQ_cxt_rsp_data; +wire RX_REQ_cxt_rsp_ready; + +wire RX_RESP_cxt_req_valid; +wire [`CXT_CMD_HEAD_WIDTH + `MAX_REQ_TAG_NUM_LOG - 1 : 0] RX_RESP_cxt_req_head; +wire [`CXT_CMD_DATA_WIDTH - 1 : 0] RX_RESP_cxt_req_data; +wire RX_RESP_cxt_req_ready; + +wire RX_RESP_cxt_rsp_valid; +wire [`CXT_RESP_HEAD_WIDTH + `MAX_REQ_TAG_NUM_LOG - 1 : 0] RX_RESP_cxt_rsp_head; +wire [`CXT_RESP_DATA_WIDTH - 1 : 0] RX_RESP_cxt_rsp_data; +wire RX_RESP_cxt_rsp_ready; +/*------------------------------------------- Local Variables Definition : End --------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : End : Begin ---------------------------------*/ +CEU CEU_Inst( + .clk ( clk ), + .rst_n ( !rst ), + + .hcr_in_param ( ceu_hcr_in_param ), + .hcr_in_modifier ( ceu_hcr_in_modifier ), + .hcr_out_dma_addr ( ceu_hcr_out_dma_addr ), + .hcr_token ( ceu_hcr_token ), + .hcr_go ( ceu_hcr_go ), + .hcr_event ( ceu_hcr_event ), + .hcr_op_modifier ( ceu_hcr_op_modifier ), + .hcr_op ( ceu_hcr_op ), + + .hcr_out_param ( ceu_hcr_out_param ), + .hcr_status ( ceu_hcr_status ), + .hcr_clear ( ceu_hcr_clear ), + + .dma_rd_req_valid ( CEU_dma_rd_req_valid ), + .dma_rd_req_last ( CEU_dma_rd_req_last ), + .dma_rd_req_head ( CEU_dma_rd_req_head ), + .dma_rd_req_data ( CEU_dma_rd_req_data ), + .dma_rd_req_ready ( CEU_dma_rd_req_ready ), + + .dma_rd_rsp_valid ( CEU_dma_rd_rsp_valid ), + .dma_rd_rsp_last ( CEU_dma_rd_rsp_last ), + .dma_rd_rsp_head ( CEU_dma_rd_rsp_head ), + .dma_rd_rsp_data ( CEU_dma_rd_rsp_data ), + .dma_rd_rsp_ready ( CEU_dma_rd_rsp_ready ), + + .dma_wr_req_valid ( CEU_dma_wr_req_valid ), + .dma_wr_req_last ( CEU_dma_wr_req_last ), + .dma_wr_req_head ( CEU_dma_wr_req_head ), + .dma_wr_req_data ( CEU_dma_wr_req_data ), + .dma_wr_req_ready ( CEU_dma_wr_req_ready ), + + .cm_req_valid ( ceu_cxt_req_valid ), + .cm_req_last ( ceu_cxt_req_last ), + .cm_req_head ( ceu_cxt_req_head ), + .cm_req_data ( ceu_cxt_req_data ), + .cm_req_ready ( ceu_cxt_req_ready ), + + .cm_rsp_valid ( ceu_cxt_rsp_valid ), + .cm_rsp_last ( ceu_cxt_rsp_last ), + .cm_rsp_head ( ceu_cxt_rsp_head ), + .cm_rsp_data ( ceu_cxt_rsp_data ), + .cm_rsp_ready ( ceu_cxt_rsp_ready ), + + .v2p_req_valid ( ceu_mr_req_valid ), + .v2p_req_last ( ceu_mr_req_last ), + .v2p_req_head ( ceu_mr_req_head ), + .v2p_req_data ( ceu_mr_req_data ), + .v2p_req_ready ( ceu_mr_req_ready ) +); + +ICMMgt ICMMgt_Inst( + .clk ( clk ), + .rst ( rst ), + + .ceu_cxt_req_valid ( ceu_cxt_req_valid ), + .ceu_cxt_req_head ( ceu_cxt_req_head ), + .ceu_cxt_req_last ( ceu_cxt_req_last ), + .ceu_cxt_req_data ( ceu_cxt_req_data ), + .ceu_cxt_req_ready ( ceu_cxt_req_ready ), + + .ceu_cxt_rsp_valid ( ceu_cxt_rsp_valid ), + .ceu_cxt_rsp_head ( ceu_cxt_rsp_head ), + .ceu_cxt_rsp_last ( ceu_cxt_rsp_last ), + .ceu_cxt_rsp_data ( ceu_cxt_rsp_data ), + .ceu_cxt_rsp_ready ( ceu_cxt_rsp_ready ), + + .SQ_cxt_req_valid ( SQ_cxt_req_valid ), + .SQ_cxt_req_head ( SQ_cxt_req_head ), + .SQ_cxt_req_data ( SQ_cxt_req_data ), + .SQ_cxt_req_ready ( SQ_cxt_req_ready ), + + .TX_REQ_cxt_req_valid ( TX_REQ_cxt_req_valid ), + .TX_REQ_cxt_req_head ( TX_REQ_cxt_req_head ), + .TX_REQ_cxt_req_data ( TX_REQ_cxt_req_data ), + .TX_REQ_cxt_req_ready ( TX_REQ_cxt_req_ready ), + + .RX_REQ_cxt_req_valid ( RX_REQ_cxt_req_valid ), + .RX_REQ_cxt_req_head ( RX_REQ_cxt_req_head ), + .RX_REQ_cxt_req_data ( RX_REQ_cxt_req_data ), + .RX_REQ_cxt_req_ready ( RX_REQ_cxt_req_ready ), + + .RX_RESP_cxt_req_valid ( RX_RESP_cxt_req_valid ), + .RX_RESP_cxt_req_head ( RX_RESP_cxt_req_head ), + .RX_RESP_cxt_req_data ( RX_RESP_cxt_req_data ), + .RX_RESP_cxt_req_ready ( RX_RESP_cxt_req_ready ), + + .SQ_cxt_rsp_valid ( SQ_cxt_rsp_valid ), + .SQ_cxt_rsp_head ( SQ_cxt_rsp_head ), + .SQ_cxt_rsp_data ( SQ_cxt_rsp_data ), + .SQ_cxt_rsp_ready ( SQ_cxt_rsp_ready ), + + .TX_REQ_cxt_rsp_valid ( TX_REQ_cxt_rsp_valid ), + .TX_REQ_cxt_rsp_head ( TX_REQ_cxt_rsp_head ), + .TX_REQ_cxt_rsp_data ( TX_REQ_cxt_rsp_data ), + .TX_REQ_cxt_rsp_ready ( TX_REQ_cxt_rsp_ready ), + + .RX_REQ_cxt_rsp_valid ( RX_REQ_cxt_rsp_valid ), + .RX_REQ_cxt_rsp_head ( RX_REQ_cxt_rsp_head ), + .RX_REQ_cxt_rsp_data ( RX_REQ_cxt_rsp_data ), + .RX_REQ_cxt_rsp_ready ( RX_REQ_cxt_rsp_ready ), + + .RX_RESP_cxt_rsp_valid ( RX_RESP_cxt_rsp_valid ), + .RX_RESP_cxt_rsp_head ( RX_RESP_cxt_rsp_head ), + .RX_RESP_cxt_rsp_data ( RX_RESP_cxt_rsp_data ), + .RX_RESP_cxt_rsp_ready ( RX_RESP_cxt_rsp_ready ), + + .qpc_dma_rd_req_valid ( QPC_dma_rd_req_valid ), + .qpc_dma_rd_req_head ( QPC_dma_rd_req_head ), + .qpc_dma_rd_req_data ( QPC_dma_rd_req_data ), + .qpc_dma_rd_req_last ( QPC_dma_rd_req_last ), + .qpc_dma_rd_req_ready ( QPC_dma_rd_req_ready ), + + .qpc_dma_rd_rsp_valid ( QPC_dma_rd_rsp_valid ), + .qpc_dma_rd_rsp_head ( QPC_dma_rd_rsp_head ), + .qpc_dma_rd_rsp_data ( QPC_dma_rd_rsp_data ), + .qpc_dma_rd_rsp_last ( QPC_dma_rd_rsp_last ), + .qpc_dma_rd_rsp_ready ( QPC_dma_rd_rsp_ready ), + + .qpc_dma_wr_req_valid ( QPC_dma_wr_req_valid ), + .qpc_dma_wr_req_head ( QPC_dma_wr_req_head ), + .qpc_dma_wr_req_data ( QPC_dma_wr_req_data ), + .qpc_dma_wr_req_last ( QPC_dma_wr_req_last ), + .qpc_dma_wr_req_ready ( QPC_dma_wr_req_ready ), + + .cqc_dma_rd_req_valid ( CQC_dma_rd_req_valid ), + .cqc_dma_rd_req_head ( CQC_dma_rd_req_head ), + .cqc_dma_rd_req_data ( CQC_dma_rd_req_data ), + .cqc_dma_rd_req_last ( CQC_dma_rd_req_last ), + .cqc_dma_rd_req_ready ( CQC_dma_rd_req_ready ), + + .cqc_dma_rd_rsp_valid ( CQC_dma_rd_rsp_valid ), + .cqc_dma_rd_rsp_head ( CQC_dma_rd_rsp_head ), + .cqc_dma_rd_rsp_data ( CQC_dma_rd_rsp_data ), + .cqc_dma_rd_rsp_last ( CQC_dma_rd_rsp_last ), + .cqc_dma_rd_rsp_ready ( CQC_dma_rd_rsp_ready ), + + .cqc_dma_wr_req_valid ( CQC_dma_wr_req_valid ), + .cqc_dma_wr_req_head ( CQC_dma_wr_req_head ), + .cqc_dma_wr_req_data ( CQC_dma_wr_req_data ), + .cqc_dma_wr_req_last ( CQC_dma_wr_req_last ), + .cqc_dma_wr_req_ready ( CQC_dma_wr_req_ready ), + + .eqc_dma_rd_req_valid ( EQC_dma_rd_req_valid ), + .eqc_dma_rd_req_head ( EQC_dma_rd_req_head ), + .eqc_dma_rd_req_data ( EQC_dma_rd_req_data ), + .eqc_dma_rd_req_last ( EQC_dma_rd_req_last ), + .eqc_dma_rd_req_ready ( EQC_dma_rd_req_ready ), + + .eqc_dma_rd_rsp_valid ( EQC_dma_rd_rsp_valid ), + .eqc_dma_rd_rsp_head ( EQC_dma_rd_rsp_head ), + .eqc_dma_rd_rsp_data ( EQC_dma_rd_rsp_data ), + .eqc_dma_rd_rsp_last ( EQC_dma_rd_rsp_last ), + .eqc_dma_rd_rsp_ready ( EQC_dma_rd_rsp_ready ), + + .eqc_dma_wr_req_valid ( EQC_dma_wr_req_valid ), + .eqc_dma_wr_req_head ( EQC_dma_wr_req_head ), + .eqc_dma_wr_req_data ( EQC_dma_wr_req_data ), + .eqc_dma_wr_req_last ( EQC_dma_wr_req_last ), + .eqc_dma_wr_req_ready ( EQC_dma_wr_req_ready ), + + .ceu_mr_req_valid ( ceu_mr_req_valid ), + .ceu_mr_req_head ( ceu_mr_req_head ), + .ceu_mr_req_last ( ceu_mr_req_last ), + .ceu_mr_req_data ( ceu_mr_req_data ), + .ceu_mr_req_ready ( ceu_mr_req_ready ), + + .SQ_mr_req_valid ( SQ_mr_req_valid ), + .SQ_mr_req_head ( SQ_mr_req_head ), + .SQ_mr_req_data ( SQ_mr_req_data ), + .SQ_mr_req_ready ( SQ_mr_req_ready ), + + .SQ_mr_rsp_valid ( SQ_mr_rsp_valid ), + .SQ_mr_rsp_head ( SQ_mr_rsp_head ), + .SQ_mr_rsp_data ( SQ_mr_rsp_data ), + .SQ_mr_rsp_ready ( SQ_mr_rsp_ready ), + + .RQ_mr_req_valid ( RQ_mr_req_valid ), + .RQ_mr_req_head ( RQ_mr_req_head ), + .RQ_mr_req_data ( RQ_mr_req_data ), + .RQ_mr_req_ready ( RQ_mr_req_ready ), + + .RQ_mr_rsp_valid ( RQ_mr_rsp_valid ), + .RQ_mr_rsp_head ( RQ_mr_rsp_head ), + .RQ_mr_rsp_data ( RQ_mr_rsp_data ), + .RQ_mr_rsp_ready ( RQ_mr_rsp_ready ), + + .TX_REQ_mr_req_valid ( TX_REQ_mr_req_valid ), + .TX_REQ_mr_req_head ( TX_REQ_mr_req_head ), + .TX_REQ_mr_req_data ( TX_REQ_mr_req_data ), + .TX_REQ_mr_req_ready ( TX_REQ_mr_req_ready ), + + .TX_REQ_mr_rsp_valid ( TX_REQ_mr_rsp_valid ), + .TX_REQ_mr_rsp_head ( TX_REQ_mr_rsp_head ), + .TX_REQ_mr_rsp_data ( TX_REQ_mr_rsp_data ), + .TX_REQ_mr_rsp_ready ( TX_REQ_mr_rsp_ready ), + + .RX_REQ_mr_req_valid ( RX_REQ_mr_req_valid ), + .RX_REQ_mr_req_head ( RX_REQ_mr_req_head ), + .RX_REQ_mr_req_data ( RX_REQ_mr_req_data ), + .RX_REQ_mr_req_ready ( RX_REQ_mr_req_ready ), + + .RX_REQ_mr_rsp_valid ( RX_REQ_mr_rsp_valid ), + .RX_REQ_mr_rsp_head ( RX_REQ_mr_rsp_head ), + .RX_REQ_mr_rsp_data ( RX_REQ_mr_rsp_data ), + .RX_REQ_mr_rsp_ready ( RX_REQ_mr_rsp_ready ), + + .RX_RESP_mr_req_valid ( RX_RESP_mr_req_valid ), + .RX_RESP_mr_req_head ( RX_RESP_mr_req_head ), + .RX_RESP_mr_req_data ( RX_RESP_mr_req_data ), + .RX_RESP_mr_req_ready ( RX_RESP_mr_req_ready ), + + .RX_RESP_mr_rsp_valid ( RX_RESP_mr_rsp_valid ), + .RX_RESP_mr_rsp_head ( RX_RESP_mr_rsp_head ), + .RX_RESP_mr_rsp_data ( RX_RESP_mr_rsp_data ), + .RX_RESP_mr_rsp_ready ( RX_RESP_mr_rsp_ready ), + + .mpt_dma_rd_req_valid ( MPT_dma_rd_req_valid ), + .mpt_dma_rd_req_head ( MPT_dma_rd_req_head ), + .mpt_dma_rd_req_data ( MPT_dma_rd_req_data ), + .mpt_dma_rd_req_last ( MPT_dma_rd_req_last ), + .mpt_dma_rd_req_ready ( MPT_dma_rd_req_ready ), + + .mpt_dma_rd_rsp_valid ( MPT_dma_rd_rsp_valid ), + .mpt_dma_rd_rsp_head ( MPT_dma_rd_rsp_head ), + .mpt_dma_rd_rsp_data ( MPT_dma_rd_rsp_data ), + .mpt_dma_rd_rsp_last ( MPT_dma_rd_rsp_last ), + .mpt_dma_rd_rsp_ready ( MPT_dma_rd_rsp_ready ), + + .mpt_dma_wr_req_valid ( MPT_dma_wr_req_valid ), + .mpt_dma_wr_req_head ( MPT_dma_wr_req_head ), + .mpt_dma_wr_req_data ( MPT_dma_wr_req_data ), + .mpt_dma_wr_req_last ( MPT_dma_wr_req_last ), + .mpt_dma_wr_req_ready ( MPT_dma_wr_req_ready ), + + .mtt_dma_rd_req_valid ( MTT_dma_rd_req_valid ), + .mtt_dma_rd_req_head ( MTT_dma_rd_req_head ), + .mtt_dma_rd_req_data ( MTT_dma_rd_req_data ), + .mtt_dma_rd_req_last ( MTT_dma_rd_req_last ), + .mtt_dma_rd_req_ready ( MTT_dma_rd_req_ready ), + + .mtt_dma_rd_rsp_valid ( MTT_dma_rd_rsp_valid ), + .mtt_dma_rd_rsp_head ( MTT_dma_rd_rsp_head ), + .mtt_dma_rd_rsp_data ( MTT_dma_rd_rsp_data ), + .mtt_dma_rd_rsp_last ( MTT_dma_rd_rsp_last ), + .mtt_dma_rd_rsp_ready ( MTT_dma_rd_rsp_ready ), + + .mtt_dma_wr_req_valid ( MTT_dma_wr_req_valid ), + .mtt_dma_wr_req_head ( MTT_dma_wr_req_head ), + .mtt_dma_wr_req_data ( MTT_dma_wr_req_data ), + .mtt_dma_wr_req_last ( MTT_dma_wr_req_last ), + .mtt_dma_wr_req_ready ( MTT_dma_wr_req_ready ) +); + +OoOBalancer + #( + + .ID ( 1 ), + + .OOO_STATION_NUM ( 4 ), + + .TAG_NUM ( `REQ_TAG_NUM ), + + .RESOURCE_CMD_HEAD_WIDTH ( `CXT_CMD_HEAD_WIDTH ), + .RESOURCE_CMD_DATA_WIDTH ( `CXT_CMD_DATA_WIDTH ), + .RESOURCE_RESP_HEAD_WIDTH ( `CXT_RESP_HEAD_WIDTH ), + .RESOURCE_RESP_DATA_WIDTH ( `CXT_RESP_DATA_WIDTH ), + + .SLOT_NUM ( `SQ_OOO_SLOT_NUM ), + .QUEUE_NUM ( `QP_NUM ), + + .INGRESS_HEAD_WIDTH ( `SQ_OOO_CXT_INGRESS_HEAD_WIDTH ), + .INGRESS_DATA_WIDTH ( `SQ_OOO_CXT_INGRESS_DATA_WIDTH ), + + .EGRESS_HEAD_WIDTH ( `SQ_OOO_CXT_EGRESS_HEAD_WIDTH ), + .EGRESS_DATA_WIDTH ( `SQ_OOO_CXT_EGRESS_DATA_WIDTH ) +) +SQ_Cxt_OoO_Inst( + .clk ( clk ), + .rst ( rst ), + + .ingress_valid ( SQ_fetch_cxt_ingress_valid ), + .ingress_head ( SQ_fetch_cxt_ingress_head ), + .ingress_data ( SQ_fetch_cxt_ingress_data ), + .ingress_start ( SQ_fetch_cxt_ingress_start ), + .ingress_last ( SQ_fetch_cxt_ingress_last ), + .ingress_ready ( SQ_fetch_cxt_ingress_ready ), + + .available_slot_num (), + + .resource_req_valid ( SQ_cxt_req_valid ), + .resource_req_head ( SQ_cxt_req_head ), + .resource_req_data ( SQ_cxt_req_data ), + .resource_req_start ( SQ_cxt_req_start ), + .resource_req_last ( SQ_cxt_req_last ), + .resource_req_ready ( SQ_cxt_req_ready ), + + .resource_resp_valid ( SQ_cxt_rsp_valid ), + .resource_resp_head ( SQ_cxt_rsp_head ), + .resource_resp_data ( SQ_cxt_rsp_data ), + .resource_resp_start ( SQ_cxt_rsp_valid ), + .resource_resp_last ( SQ_cxt_rsp_valid ), + .resource_resp_ready ( SQ_cxt_rsp_ready ), + + .egress_valid ( SQ_fetch_cxt_egress_valid ), + .egress_head ( SQ_fetch_cxt_egress_head ), + .egress_data ( SQ_fetch_cxt_egress_data ), + .egress_start ( SQ_fetch_cxt_egress_start ), + .egress_last ( SQ_fetch_cxt_egress_last ), + .egress_ready ( SQ_fetch_cxt_egress_ready ) +); + +OoOBalancer + #( + .ID ( 2 ), + + .OOO_STATION_NUM ( 4 ), + + .TAG_NUM ( `REQ_TAG_NUM ), + + .RESOURCE_CMD_HEAD_WIDTH ( `CXT_CMD_HEAD_WIDTH ), + .RESOURCE_CMD_DATA_WIDTH ( `CXT_CMD_DATA_WIDTH ), + .RESOURCE_RESP_HEAD_WIDTH ( `CXT_RESP_HEAD_WIDTH ), + .RESOURCE_RESP_DATA_WIDTH ( `CXT_RESP_DATA_WIDTH ), + + .SLOT_NUM ( `TX_REQ_OOO_SLOT_NUM ), + .QUEUE_NUM ( `QP_NUM ), + + .INGRESS_HEAD_WIDTH ( `TX_REQ_OOO_CXT_INGRESS_HEAD_WIDTH ), + .INGRESS_DATA_WIDTH ( `TX_REQ_OOO_CXT_INGRESS_DATA_WIDTH ), + + .EGRESS_HEAD_WIDTH ( `TX_REQ_OOO_CXT_EGRESS_HEAD_WIDTH ), + .EGRESS_DATA_WIDTH ( `TX_REQ_OOO_CXT_EGRESS_DATA_WIDTH ) +) +TX_REQ_Cxt_OoO_Inst( + .clk ( clk ), + .rst ( rst ), + + .ingress_valid ( TX_REQ_fetch_cxt_ingress_valid ), + .ingress_head ( TX_REQ_fetch_cxt_ingress_head ), + .ingress_data ( TX_REQ_fetch_cxt_ingress_data ), + .ingress_start ( TX_REQ_fetch_cxt_ingress_start ), + .ingress_last ( TX_REQ_fetch_cxt_ingress_last ), + .ingress_ready ( TX_REQ_fetch_cxt_ingress_ready ), + + .available_slot_num (), + + .resource_req_valid ( TX_REQ_cxt_req_valid ), + .resource_req_head ( TX_REQ_cxt_req_head ), + .resource_req_data ( TX_REQ_cxt_req_data ), + .resource_req_start ( TX_REQ_cxt_req_start ), + .resource_req_last ( TX_REQ_cxt_req_last ), + .resource_req_ready ( TX_REQ_cxt_req_ready ), + + .resource_resp_valid ( TX_REQ_cxt_rsp_valid ), + .resource_resp_head ( TX_REQ_cxt_rsp_head ), + .resource_resp_data ( TX_REQ_cxt_rsp_data ), + .resource_resp_start ( TX_REQ_cxt_rsp_valid ), + .resource_resp_last ( TX_REQ_cxt_rsp_valid ), + .resource_resp_ready ( TX_REQ_cxt_rsp_ready ), + + .egress_valid ( TX_REQ_fetch_cxt_egress_valid ), + .egress_head ( TX_REQ_fetch_cxt_egress_head ), + .egress_data ( TX_REQ_fetch_cxt_egress_data ), + .egress_start ( TX_REQ_fetch_cxt_egress_start ), + .egress_last ( TX_REQ_fetch_cxt_egress_last ), + .egress_ready ( TX_REQ_fetch_cxt_egress_ready ) +); + +OoOBalancer + #( + .ID ( 3 ), + + .OOO_STATION_NUM ( 4 ), + + .TAG_NUM ( `REQ_TAG_NUM ), + + .RESOURCE_CMD_HEAD_WIDTH ( `CXT_CMD_HEAD_WIDTH ), + .RESOURCE_CMD_DATA_WIDTH ( `CXT_CMD_DATA_WIDTH ), + .RESOURCE_RESP_HEAD_WIDTH ( `CXT_RESP_HEAD_WIDTH ), + .RESOURCE_RESP_DATA_WIDTH ( `CXT_RESP_DATA_WIDTH ), + + .SLOT_NUM ( `RX_REQ_OOO_SLOT_NUM ), + .QUEUE_NUM ( `QP_NUM ), + + .INGRESS_HEAD_WIDTH ( `RX_REQ_OOO_CXT_INGRESS_HEAD_WIDTH ), + .INGRESS_DATA_WIDTH ( `RX_REQ_OOO_CXT_INGRESS_DATA_WIDTH ), + + .EGRESS_HEAD_WIDTH ( `RX_REQ_OOO_CXT_EGRESS_HEAD_WIDTH ), + .EGRESS_DATA_WIDTH ( `RX_REQ_OOO_CXT_EGRESS_DATA_WIDTH ) +) +RX_REQ_Cxt_OoO_Inst( + .clk ( clk ), + .rst ( rst ), + + .ingress_valid ( RX_REQ_fetch_cxt_ingress_valid ), + .ingress_head ( RX_REQ_fetch_cxt_ingress_head ), + .ingress_data ( RX_REQ_fetch_cxt_ingress_data ), + .ingress_start ( RX_REQ_fetch_cxt_ingress_start ), + .ingress_last ( RX_REQ_fetch_cxt_ingress_last ), + .ingress_ready ( RX_REQ_fetch_cxt_ingress_ready ), + + .available_slot_num (), + + .resource_req_valid ( RX_REQ_cxt_req_valid ), + .resource_req_head ( RX_REQ_cxt_req_head ), + .resource_req_data ( RX_REQ_cxt_req_data ), + .resource_req_start ( RX_REQ_cxt_req_start ), + .resource_req_last ( RX_REQ_cxt_req_last ), + .resource_req_ready ( RX_REQ_cxt_req_ready ), + + .resource_resp_valid ( RX_REQ_cxt_rsp_valid ), + .resource_resp_head ( RX_REQ_cxt_rsp_head ), + .resource_resp_data ( RX_REQ_cxt_rsp_data ), + .resource_resp_start ( RX_REQ_cxt_rsp_valid ), + .resource_resp_last ( RX_REQ_cxt_rsp_valid ), + .resource_resp_ready ( RX_REQ_cxt_rsp_ready ), + + .egress_valid ( RX_REQ_fetch_cxt_egress_valid ), + .egress_head ( RX_REQ_fetch_cxt_egress_head ), + .egress_data ( RX_REQ_fetch_cxt_egress_data ), + .egress_start ( RX_REQ_fetch_cxt_egress_start ), + .egress_last ( RX_REQ_fetch_cxt_egress_last ), + .egress_ready ( RX_REQ_fetch_cxt_egress_ready ) +); + +OoOBalancer + #( + .ID ( 4 ), + + .OOO_STATION_NUM ( 4 ), + + .TAG_NUM ( `REQ_TAG_NUM ), + + .RESOURCE_CMD_HEAD_WIDTH ( `CXT_CMD_HEAD_WIDTH ), + .RESOURCE_CMD_DATA_WIDTH ( `CXT_CMD_DATA_WIDTH ), + .RESOURCE_RESP_HEAD_WIDTH ( `CXT_RESP_HEAD_WIDTH ), + .RESOURCE_RESP_DATA_WIDTH ( `CXT_RESP_DATA_WIDTH ), + + .SLOT_NUM ( `RX_RESP_OOO_SLOT_NUM ), + .QUEUE_NUM ( `QP_NUM ), + + .INGRESS_HEAD_WIDTH ( `RX_RESP_OOO_CXT_INGRESS_HEAD_WIDTH ), + .INGRESS_DATA_WIDTH ( `RX_RESP_OOO_CXT_INGRESS_DATA_WIDTH ), + + .EGRESS_HEAD_WIDTH ( `RX_RESP_OOO_CXT_EGRESS_HEAD_WIDTH ), + .EGRESS_DATA_WIDTH ( `RX_RESP_OOO_CXT_EGRESS_DATA_WIDTH ) +) +RX_RESP_Cxt_OoO_Inst( + .clk ( clk ), + .rst ( rst ), + + .ingress_valid ( RX_RESP_fetch_cxt_ingress_valid ), + .ingress_head ( RX_RESP_fetch_cxt_ingress_head ), + .ingress_data ( RX_RESP_fetch_cxt_ingress_data ), + .ingress_start ( RX_RESP_fetch_cxt_ingress_start ), + .ingress_last ( RX_RESP_fetch_cxt_ingress_last ), + .ingress_ready ( RX_RESP_fetch_cxt_ingress_ready ), + + .available_slot_num (), + + .resource_req_valid ( RX_RESP_cxt_req_valid ), + .resource_req_head ( RX_RESP_cxt_req_head ), + .resource_req_data ( RX_RESP_cxt_req_data ), + .resource_req_start ( RX_RESP_cxt_req_start ), + .resource_req_last ( RX_RESP_cxt_req_last ), + .resource_req_ready ( RX_RESP_cxt_req_ready ), + + .resource_resp_valid ( RX_RESP_cxt_rsp_valid ), + .resource_resp_head ( RX_RESP_cxt_rsp_head ), + .resource_resp_data ( RX_RESP_cxt_rsp_data ), + .resource_resp_start ( RX_RESP_cxt_rsp_valid ), + .resource_resp_last ( RX_RESP_cxt_rsp_valid ), + .resource_resp_ready ( RX_RESP_cxt_rsp_ready ), + + .egress_valid ( RX_RESP_fetch_cxt_egress_valid ), + .egress_head ( RX_RESP_fetch_cxt_egress_head ), + .egress_data ( RX_RESP_fetch_cxt_egress_data ), + .egress_start ( RX_RESP_fetch_cxt_egress_start ), + .egress_last ( RX_RESP_fetch_cxt_egress_last ), + .egress_ready ( RX_RESP_fetch_cxt_egress_ready ) +); + +OoOBalancer + #( + .ID ( 5 ), + + .OOO_STATION_NUM ( 4 ), + + .TAG_NUM ( `REQ_TAG_NUM ), + + .RESOURCE_CMD_HEAD_WIDTH ( `MR_CMD_HEAD_WIDTH ), + .RESOURCE_CMD_DATA_WIDTH ( `MR_CMD_DATA_WIDTH ), + .RESOURCE_RESP_HEAD_WIDTH ( `MR_RESP_HEAD_WIDTH ), + .RESOURCE_RESP_DATA_WIDTH ( `MR_RESP_DATA_WIDTH ), + + .SLOT_NUM ( `SQ_OOO_SLOT_NUM ), + .QUEUE_NUM ( `QP_NUM ), + + .INGRESS_HEAD_WIDTH ( `SQ_OOO_MR_INGRESS_HEAD_WIDTH ), + .INGRESS_DATA_WIDTH ( `SQ_OOO_MR_INGRESS_DATA_WIDTH ), + + .EGRESS_HEAD_WIDTH ( `SQ_OOO_MR_EGRESS_HEAD_WIDTH ), + .EGRESS_DATA_WIDTH ( `SQ_OOO_MR_EGRESS_DATA_WIDTH ) +) +SQ_MR_OoO_Inst( + .clk ( clk ), + .rst ( rst ), + + .ingress_valid ( SQ_fetch_mr_ingress_valid ), + .ingress_head ( SQ_fetch_mr_ingress_head ), + .ingress_data ( SQ_fetch_mr_ingress_data ), + .ingress_start ( SQ_fetch_mr_ingress_start ), + .ingress_last ( SQ_fetch_mr_ingress_last ), + .ingress_ready ( SQ_fetch_mr_ingress_ready ), + + .available_slot_num (), + + .resource_req_valid ( SQ_mr_req_valid ), + .resource_req_head ( SQ_mr_req_head ), + .resource_req_data ( SQ_mr_req_data ), + .resource_req_start ( SQ_mr_req_start ), + .resource_req_last ( SQ_mr_req_last ), + .resource_req_ready ( SQ_mr_req_ready ), + + .resource_resp_valid ( SQ_mr_rsp_valid ), + .resource_resp_head ( SQ_mr_rsp_head ), + .resource_resp_data ( SQ_mr_rsp_data ), + .resource_resp_start ( SQ_mr_rsp_valid ), + .resource_resp_last ( SQ_mr_rsp_valid ), + .resource_resp_ready ( SQ_mr_rsp_ready ), + + .egress_valid ( SQ_fetch_mr_egress_valid ), + .egress_head ( SQ_fetch_mr_egress_head ), + .egress_data ( SQ_fetch_mr_egress_data ), + .egress_start ( SQ_fetch_mr_egress_start ), + .egress_last ( SQ_fetch_mr_egress_last ), + .egress_ready ( SQ_fetch_mr_egress_ready ) +); + +OoOBalancer + #( + .ID ( 6 ), + + .OOO_STATION_NUM ( 4 ), + + .TAG_NUM ( `REQ_TAG_NUM ), + + .RESOURCE_CMD_HEAD_WIDTH ( `MR_CMD_HEAD_WIDTH ), + .RESOURCE_CMD_DATA_WIDTH ( `MR_CMD_DATA_WIDTH ), + .RESOURCE_RESP_HEAD_WIDTH ( `MR_RESP_HEAD_WIDTH ), + .RESOURCE_RESP_DATA_WIDTH ( `MR_RESP_DATA_WIDTH ), + + .SLOT_NUM ( `RQ_OOO_SLOT_NUM ), + .QUEUE_NUM ( `QP_NUM ), + + .INGRESS_HEAD_WIDTH ( `RQ_OOO_MR_INGRESS_HEAD_WIDTH ), + .INGRESS_DATA_WIDTH ( `RQ_OOO_MR_INGRESS_DATA_WIDTH ), + + .EGRESS_HEAD_WIDTH ( `RQ_OOO_MR_EGRESS_HEAD_WIDTH ), + .EGRESS_DATA_WIDTH ( `RQ_OOO_MR_EGRESS_DATA_WIDTH ) +) +RQ_MR_OoO_Inst( + .clk ( clk ), + .rst ( rst ), + + .ingress_valid ( RQ_fetch_mr_ingress_valid ), + .ingress_head ( RQ_fetch_mr_ingress_head ), + .ingress_data ( RQ_fetch_mr_ingress_data ), + .ingress_start ( RQ_fetch_mr_ingress_start ), + .ingress_last ( RQ_fetch_mr_ingress_last ), + .ingress_ready ( RQ_fetch_mr_ingress_ready ), + + .available_slot_num (), + + .resource_req_valid ( RQ_mr_req_valid ), + .resource_req_head ( RQ_mr_req_head ), + .resource_req_data ( RQ_mr_req_data ), + .resource_req_start ( RQ_mr_req_start ), + .resource_req_last ( RQ_mr_req_last ), + .resource_req_ready ( RQ_mr_req_ready ), + + .resource_resp_valid ( RQ_mr_rsp_valid ), + .resource_resp_head ( RQ_mr_rsp_head ), + .resource_resp_data ( RQ_mr_rsp_data ), + .resource_resp_start ( RQ_mr_rsp_valid ), + .resource_resp_last ( RQ_mr_rsp_valid ), + .resource_resp_ready ( RQ_mr_rsp_ready ), + + .egress_valid ( RQ_fetch_mr_egress_valid ), + .egress_head ( RQ_fetch_mr_egress_head ), + .egress_data ( RQ_fetch_mr_egress_data ), + .egress_start ( RQ_fetch_mr_egress_start ), + .egress_last ( RQ_fetch_mr_egress_last ), + .egress_ready ( RQ_fetch_mr_egress_ready ) +); + +OoOBalancer + #( + .ID ( 7 ), + + .OOO_STATION_NUM ( 4 ), + + .TAG_NUM ( `REQ_TAG_NUM ), + + .RESOURCE_CMD_HEAD_WIDTH ( `MR_CMD_HEAD_WIDTH ), + .RESOURCE_CMD_DATA_WIDTH ( `MR_CMD_DATA_WIDTH ), + .RESOURCE_RESP_HEAD_WIDTH ( `MR_RESP_HEAD_WIDTH ), + .RESOURCE_RESP_DATA_WIDTH ( `MR_RESP_DATA_WIDTH ), + + .SLOT_NUM ( `TX_REQ_OOO_SLOT_NUM ), + .QUEUE_NUM ( `QP_NUM ), + + .INGRESS_HEAD_WIDTH ( `TX_REQ_OOO_MR_INGRESS_HEAD_WIDTH ), + .INGRESS_DATA_WIDTH ( `TX_REQ_OOO_MR_INGRESS_DATA_WIDTH ), + + .EGRESS_HEAD_WIDTH ( `TX_REQ_OOO_MR_EGRESS_HEAD_WIDTH ), + .EGRESS_DATA_WIDTH ( `TX_REQ_OOO_MR_EGRESS_DATA_WIDTH ) +) +TX_REQ_MR_OoO_Inst( + .clk ( clk ), + .rst ( rst ), + + .ingress_valid ( TX_REQ_fetch_mr_ingress_valid ), + .ingress_head ( TX_REQ_fetch_mr_ingress_head ), + .ingress_data ( TX_REQ_fetch_mr_ingress_data ), + .ingress_start ( TX_REQ_fetch_mr_ingress_start ), + .ingress_last ( TX_REQ_fetch_mr_ingress_last ), + .ingress_ready ( TX_REQ_fetch_mr_ingress_ready ), + + .available_slot_num (), + + .resource_req_valid ( TX_REQ_mr_req_valid ), + .resource_req_head ( TX_REQ_mr_req_head ), + .resource_req_data ( TX_REQ_mr_req_data ), + .resource_req_start ( TX_REQ_mr_req_start ), + .resource_req_last ( TX_REQ_mr_req_last ), + .resource_req_ready ( TX_REQ_mr_req_ready ), + + .resource_resp_valid ( TX_REQ_mr_rsp_valid ), + .resource_resp_head ( TX_REQ_mr_rsp_head ), + .resource_resp_data ( TX_REQ_mr_rsp_data ), + .resource_resp_start ( TX_REQ_mr_rsp_valid ), + .resource_resp_last ( TX_REQ_mr_rsp_valid ), + .resource_resp_ready ( TX_REQ_mr_rsp_ready ), + + .egress_valid ( TX_REQ_fetch_mr_egress_valid ), + .egress_head ( TX_REQ_fetch_mr_egress_head ), + .egress_data ( TX_REQ_fetch_mr_egress_data ), + .egress_start ( TX_REQ_fetch_mr_egress_start ), + .egress_last ( TX_REQ_fetch_mr_egress_last ), + .egress_ready ( TX_REQ_fetch_mr_egress_ready ) +); + +OoOBalancer + #( + .ID ( 8 ), + + .OOO_STATION_NUM ( 4 ), + + .TAG_NUM ( `REQ_TAG_NUM ), + + .RESOURCE_CMD_HEAD_WIDTH ( `MR_CMD_HEAD_WIDTH ), + .RESOURCE_CMD_DATA_WIDTH ( `MR_CMD_DATA_WIDTH ), + .RESOURCE_RESP_HEAD_WIDTH ( `MR_RESP_HEAD_WIDTH ), + .RESOURCE_RESP_DATA_WIDTH ( `MR_RESP_DATA_WIDTH ), + + .SLOT_NUM ( `RX_REQ_OOO_SLOT_NUM ), + .QUEUE_NUM ( `QP_NUM ), + + .INGRESS_HEAD_WIDTH ( `RX_REQ_OOO_MR_INGRESS_HEAD_WIDTH ), + .INGRESS_DATA_WIDTH ( `RX_REQ_OOO_MR_INGRESS_DATA_WIDTH ), + + .EGRESS_HEAD_WIDTH ( `RX_REQ_OOO_MR_EGRESS_HEAD_WIDTH ), + .EGRESS_DATA_WIDTH ( `RX_REQ_OOO_MR_EGRESS_DATA_WIDTH ) +) +RX_REQ_MR_OoO_Inst( + .clk ( clk ), + .rst ( rst ), + + .ingress_valid ( RX_REQ_fetch_mr_ingress_valid ), + .ingress_head ( RX_REQ_fetch_mr_ingress_head ), + .ingress_data ( RX_REQ_fetch_mr_ingress_data ), + .ingress_start ( RX_REQ_fetch_mr_ingress_start ), + .ingress_last ( RX_REQ_fetch_mr_ingress_last ), + .ingress_ready ( RX_REQ_fetch_mr_ingress_ready ), + + .available_slot_num (), + + .resource_req_valid ( RX_REQ_mr_req_valid ), + .resource_req_head ( RX_REQ_mr_req_head ), + .resource_req_data ( RX_REQ_mr_req_data ), + .resource_req_start ( RX_REQ_mr_req_start ), + .resource_req_last ( RX_REQ_mr_req_last ), + .resource_req_ready ( RX_REQ_mr_req_ready ), + + .resource_resp_valid ( RX_REQ_mr_rsp_valid ), + .resource_resp_head ( RX_REQ_mr_rsp_head ), + .resource_resp_data ( RX_REQ_mr_rsp_data ), + .resource_resp_start ( RX_REQ_mr_rsp_valid ), + .resource_resp_last ( RX_REQ_mr_rsp_valid ), + .resource_resp_ready ( RX_REQ_mr_rsp_ready ), + + .egress_valid ( RX_REQ_fetch_mr_egress_valid ), + .egress_head ( RX_REQ_fetch_mr_egress_head ), + .egress_data ( RX_REQ_fetch_mr_egress_data ), + .egress_start ( RX_REQ_fetch_mr_egress_start ), + .egress_last ( RX_REQ_fetch_mr_egress_last ), + .egress_ready ( RX_REQ_fetch_mr_egress_ready ) +); + +OoOBalancer + #( + .ID ( 9 ), + + .OOO_STATION_NUM ( 4 ), + + .TAG_NUM ( `REQ_TAG_NUM ), + + .RESOURCE_CMD_HEAD_WIDTH ( `MR_CMD_HEAD_WIDTH ), + .RESOURCE_CMD_DATA_WIDTH ( `MR_CMD_DATA_WIDTH ), + .RESOURCE_RESP_HEAD_WIDTH ( `MR_RESP_HEAD_WIDTH ), + .RESOURCE_RESP_DATA_WIDTH ( `MR_RESP_DATA_WIDTH ), + + .SLOT_NUM ( `RX_RESP_OOO_SLOT_NUM ), + .QUEUE_NUM ( `QP_NUM ), + + .INGRESS_HEAD_WIDTH ( `RX_RESP_OOO_MR_INGRESS_HEAD_WIDTH ), + .INGRESS_DATA_WIDTH ( `RX_RESP_OOO_MR_INGRESS_DATA_WIDTH ), + + .EGRESS_HEAD_WIDTH ( `RX_RESP_OOO_MR_EGRESS_HEAD_WIDTH ), + .EGRESS_DATA_WIDTH ( `RX_RESP_OOO_MR_EGRESS_DATA_WIDTH ) +) +RX_RESP_MR_OoO_Inst( + .clk ( clk ), + .rst ( rst ), + + .ingress_valid ( RX_RESP_fetch_mr_ingress_valid ), + .ingress_head ( RX_RESP_fetch_mr_ingress_head ), + .ingress_data ( RX_RESP_fetch_mr_ingress_data ), + .ingress_start ( RX_RESP_fetch_mr_ingress_start ), + .ingress_last ( RX_RESP_fetch_mr_ingress_last ), + .ingress_ready ( RX_RESP_fetch_mr_ingress_ready ), + + .available_slot_num (), + + .resource_req_valid ( RX_RESP_mr_req_valid ), + .resource_req_head ( RX_RESP_mr_req_head ), + .resource_req_data ( RX_RESP_mr_req_data ), + .resource_req_start ( RX_RESP_mr_req_start ), + .resource_req_last ( RX_RESP_mr_req_last ), + .resource_req_ready ( RX_RESP_mr_req_ready ), + + .resource_resp_valid ( RX_RESP_mr_rsp_valid ), + .resource_resp_head ( RX_RESP_mr_rsp_head ), + .resource_resp_data ( RX_RESP_mr_rsp_data ), + .resource_resp_start ( RX_RESP_mr_rsp_valid ), + .resource_resp_last ( RX_RESP_mr_rsp_valid ), + .resource_resp_ready ( RX_RESP_mr_rsp_ready ), + + .egress_valid ( RX_RESP_fetch_mr_egress_valid ), + .egress_head ( RX_RESP_fetch_mr_egress_head ), + .egress_data ( RX_RESP_fetch_mr_egress_data ), + .egress_start ( RX_RESP_fetch_mr_egress_start ), + .egress_last ( RX_RESP_fetch_mr_egress_last ), + .egress_ready ( RX_RESP_fetch_mr_egress_ready ) +); + +// `ifdef ILA_ON +// ila_sq_ooo ila_sq_ooo_inst( +// .clk(clk), + +// .probe0(SQ_fetch_cxt_ingress_valid), +// .probe1(SQ_fetch_cxt_ingress_head), +// .probe2(SQ_fetch_cxt_ingress_data), +// .probe3(SQ_fetch_cxt_ingress_start), +// .probe4(SQ_fetch_cxt_ingress_last), +// .probe5(SQ_fetch_cxt_ingress_ready) +// ); + +// `endif + +/*------------------------------------------- Submodules Instatiation : End -----------------------------------------*/ + + +/*------------------------------------------- State Machine Definition : Begin --------------------------------------*/ +/*------------------------------------------- State Machine Definition : End ----------------------------------------*/ + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ +/*------------------------------------------- Variables Decode : End ------------------------------------------------*/ +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/SubnetAgent/README.md b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/SubnetAgent/README.md new file mode 100644 index 0000000000000000000000000000000000000000..46a4e998f325bb18a606058c5f61799d43df7a4a --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/SubnetAgent/README.md @@ -0,0 +1 @@ +SubnetSystem diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Top/DMA_Channel_Top.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Top/DMA_Channel_Top.v new file mode 100644 index 0000000000000000000000000000000000000000..032a18269b18978aa2f336588cc6a6e3ebad4c6d --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Top/DMA_Channel_Top.v @@ -0,0 +1,579 @@ +module DMA_Channel_Top +( + input wire clk, + input wire rst, + +//Wr Channel + //Channel 0 + input wire CEU_dma_wr_req_in_valid, + input wire [127:0] CEU_dma_wr_req_in_head, + input wire [511:0] CEU_dma_wr_req_in_data, + input wire CEU_dma_wr_req_in_last, + output wire CEU_dma_wr_req_in_ready, + + output wire CEU_dma_wr_req_out_valid, + output wire [127:0] CEU_dma_wr_req_out_head, + output wire [255:0] CEU_dma_wr_req_out_data, + output wire CEU_dma_wr_req_out_last, + input wire CEU_dma_wr_req_out_ready, + + //Channel 1 + input wire QPC_dma_wr_req_in_valid, + input wire [127:0] QPC_dma_wr_req_in_head, + input wire [511:0] QPC_dma_wr_req_in_data, + input wire QPC_dma_wr_req_in_last, + output wire QPC_dma_wr_req_in_ready, + + output wire QPC_dma_wr_req_out_valid, + output wire [127:0] QPC_dma_wr_req_out_head, + output wire [255:0] QPC_dma_wr_req_out_data, + output wire QPC_dma_wr_req_out_last, + input wire QPC_dma_wr_req_out_ready, + + //Channel 2 + input wire CQC_dma_wr_req_in_valid, + input wire [127:0] CQC_dma_wr_req_in_head, + input wire [511:0] CQC_dma_wr_req_in_data, + input wire CQC_dma_wr_req_in_last, + output wire CQC_dma_wr_req_in_ready, + + output wire CQC_dma_wr_req_out_valid, + output wire [127:0] CQC_dma_wr_req_out_head, + output wire [255:0] CQC_dma_wr_req_out_data, + output wire CQC_dma_wr_req_out_last, + input wire CQC_dma_wr_req_out_ready, + + //Channel 3 + input wire EQC_dma_wr_req_in_valid, + input wire [127:0] EQC_dma_wr_req_in_head, + input wire [511:0] EQC_dma_wr_req_in_data, + input wire EQC_dma_wr_req_in_last, + output wire EQC_dma_wr_req_in_ready, + + output wire EQC_dma_wr_req_out_valid, + output wire [127:0] EQC_dma_wr_req_out_head, + output wire [255:0] EQC_dma_wr_req_out_data, + output wire EQC_dma_wr_req_out_last, + input wire EQC_dma_wr_req_out_ready, + + //Channel 4 + input wire MPT_dma_wr_req_in_valid, + input wire [127:0] MPT_dma_wr_req_in_head, + input wire [511:0] MPT_dma_wr_req_in_data, + input wire MPT_dma_wr_req_in_last, + output wire MPT_dma_wr_req_in_ready, + + output wire MPT_dma_wr_req_out_valid, + output wire [127:0] MPT_dma_wr_req_out_head, + output wire [255:0] MPT_dma_wr_req_out_data, + output wire MPT_dma_wr_req_out_last, + input wire MPT_dma_wr_req_out_ready, + + //Channel 5 + input wire MTT_dma_wr_req_in_valid, + input wire [127:0] MTT_dma_wr_req_in_head, + input wire [511:0] MTT_dma_wr_req_in_data, + input wire MTT_dma_wr_req_in_last, + output wire MTT_dma_wr_req_in_ready, + + output wire MTT_dma_wr_req_out_valid, + output wire [127:0] MTT_dma_wr_req_out_head, + output wire [255:0] MTT_dma_wr_req_out_data, + output wire MTT_dma_wr_req_out_last, + input wire MTT_dma_wr_req_out_ready, + + //Channel 6 + input wire TX_REQ_dma_wr_req_in_valid, + input wire [127:0] TX_REQ_dma_wr_req_in_head, + input wire [511:0] TX_REQ_dma_wr_req_in_data, + input wire TX_REQ_dma_wr_req_in_last, + output wire TX_REQ_dma_wr_req_in_ready, + + output wire TX_REQ_dma_wr_req_out_valid, + output wire [127:0] TX_REQ_dma_wr_req_out_head, + output wire [255:0] TX_REQ_dma_wr_req_out_data, + output wire TX_REQ_dma_wr_req_out_last, + input wire TX_REQ_dma_wr_req_out_ready, + + //Channel 7 + input wire RX_REQ_dma_wr_req_in_valid, + input wire [127:0] RX_REQ_dma_wr_req_in_head, + input wire [511:0] RX_REQ_dma_wr_req_in_data, + input wire RX_REQ_dma_wr_req_in_last, + output wire RX_REQ_dma_wr_req_in_ready, + + output wire RX_REQ_dma_wr_req_out_valid, + output wire [127:0] RX_REQ_dma_wr_req_out_head, + output wire [255:0] RX_REQ_dma_wr_req_out_data, + output wire RX_REQ_dma_wr_req_out_last, + input wire RX_REQ_dma_wr_req_out_ready, + + //Channel 8 + input wire RX_RESP_dma_wr_req_in_valid, + input wire [127:0] RX_RESP_dma_wr_req_in_head, + input wire [511:0] RX_RESP_dma_wr_req_in_data, + input wire RX_RESP_dma_wr_req_in_last, + output wire RX_RESP_dma_wr_req_in_ready, + + output wire RX_RESP_dma_wr_req_out_valid, + output wire [127:0] RX_RESP_dma_wr_req_out_head, + output wire [255:0] RX_RESP_dma_wr_req_out_data, + output wire RX_RESP_dma_wr_req_out_last, + input wire RX_RESP_dma_wr_req_out_ready, + +//Rd Channel + //Channel 0 + input wire CEU_dma_rd_rsp_in_valid, + input wire [127:0] CEU_dma_rd_rsp_in_head, + input wire [255:0] CEU_dma_rd_rsp_in_data, + input wire CEU_dma_rd_rsp_in_last, + output wire CEU_dma_rd_rsp_in_ready, + + output wire CEU_dma_rd_rsp_out_valid, + output wire [127:0] CEU_dma_rd_rsp_out_head, + output wire [511:0] CEU_dma_rd_rsp_out_data, + output wire CEU_dma_rd_rsp_out_last, + input wire CEU_dma_rd_rsp_out_ready, + + //Channel 1 + input wire SQ_dma_rd_rsp_in_valid, + input wire [127:0] SQ_dma_rd_rsp_in_head, + input wire [255:0] SQ_dma_rd_rsp_in_data, + input wire SQ_dma_rd_rsp_in_last, + output wire SQ_dma_rd_rsp_in_ready, + + output wire SQ_dma_rd_rsp_out_valid, + output wire [127:0] SQ_dma_rd_rsp_out_head, + output wire [511:0] SQ_dma_rd_rsp_out_data, + output wire SQ_dma_rd_rsp_out_last, + input wire SQ_dma_rd_rsp_out_ready, + + //Channel 2 + input wire RQ_dma_rd_rsp_in_valid, + input wire [127:0] RQ_dma_rd_rsp_in_head, + input wire [255:0] RQ_dma_rd_rsp_in_data, + input wire RQ_dma_rd_rsp_in_last, + output wire RQ_dma_rd_rsp_in_ready, + + output wire RQ_dma_rd_rsp_out_valid, + output wire [127:0] RQ_dma_rd_rsp_out_head, + output wire [511:0] RQ_dma_rd_rsp_out_data, + output wire RQ_dma_rd_rsp_out_last, + input wire RQ_dma_rd_rsp_out_ready, + + //Channel 3 + input wire QPC_dma_rd_rsp_in_valid, + input wire [127:0] QPC_dma_rd_rsp_in_head, + input wire [255:0] QPC_dma_rd_rsp_in_data, + input wire QPC_dma_rd_rsp_in_last, + output wire QPC_dma_rd_rsp_in_ready, + + output wire QPC_dma_rd_rsp_out_valid, + output wire [127:0] QPC_dma_rd_rsp_out_head, + output wire [511:0] QPC_dma_rd_rsp_out_data, + output wire QPC_dma_rd_rsp_out_last, + input wire QPC_dma_rd_rsp_out_ready, + + //Channel 4 + input wire CQC_dma_rd_rsp_in_valid, + input wire [127:0] CQC_dma_rd_rsp_in_head, + input wire [255:0] CQC_dma_rd_rsp_in_data, + input wire CQC_dma_rd_rsp_in_last, + output wire CQC_dma_rd_rsp_in_ready, + + output wire CQC_dma_rd_rsp_out_valid, + output wire [127:0] CQC_dma_rd_rsp_out_head, + output wire [511:0] CQC_dma_rd_rsp_out_data, + output wire CQC_dma_rd_rsp_out_last, + input wire CQC_dma_rd_rsp_out_ready, + + //Channel 5 + input wire EQC_dma_rd_rsp_in_valid, + input wire [127:0] EQC_dma_rd_rsp_in_head, + input wire [255:0] EQC_dma_rd_rsp_in_data, + input wire EQC_dma_rd_rsp_in_last, + output wire EQC_dma_rd_rsp_in_ready, + + output wire EQC_dma_rd_rsp_out_valid, + output wire [127:0] EQC_dma_rd_rsp_out_head, + output wire [511:0] EQC_dma_rd_rsp_out_data, + output wire EQC_dma_rd_rsp_out_last, + input wire EQC_dma_rd_rsp_out_ready, + + //Channel 6 + input wire MPT_dma_rd_rsp_in_valid, + input wire [127:0] MPT_dma_rd_rsp_in_head, + input wire [255:0] MPT_dma_rd_rsp_in_data, + input wire MPT_dma_rd_rsp_in_last, + output wire MPT_dma_rd_rsp_in_ready, + + output wire MPT_dma_rd_rsp_out_valid, + output wire [127:0] MPT_dma_rd_rsp_out_head, + output wire [511:0] MPT_dma_rd_rsp_out_data, + output wire MPT_dma_rd_rsp_out_last, + input wire MPT_dma_rd_rsp_out_ready, + + //Channel 7 + input wire MTT_dma_rd_rsp_in_valid, + input wire [127:0] MTT_dma_rd_rsp_in_head, + input wire [255:0] MTT_dma_rd_rsp_in_data, + input wire MTT_dma_rd_rsp_in_last, + output wire MTT_dma_rd_rsp_in_ready, + + output wire MTT_dma_rd_rsp_out_valid, + output wire [127:0] MTT_dma_rd_rsp_out_head, + output wire [511:0] MTT_dma_rd_rsp_out_data, + output wire MTT_dma_rd_rsp_out_last, + input wire MTT_dma_rd_rsp_out_ready, + + //Channel 8 + input wire TX_REQ_dma_rd_rsp_in_valid, + input wire [127:0] TX_REQ_dma_rd_rsp_in_head, + input wire [255:0] TX_REQ_dma_rd_rsp_in_data, + input wire TX_REQ_dma_rd_rsp_in_last, + output wire TX_REQ_dma_rd_rsp_in_ready, + + output wire TX_REQ_dma_rd_rsp_out_valid, + output wire [127:0] TX_REQ_dma_rd_rsp_out_head, + output wire [511:0] TX_REQ_dma_rd_rsp_out_data, + output wire TX_REQ_dma_rd_rsp_out_last, + input wire TX_REQ_dma_rd_rsp_out_ready, + + //Channel 9 + input wire TX_RESP_dma_rd_rsp_in_valid, + input wire [127:0] TX_RESP_dma_rd_rsp_in_head, + input wire [255:0] TX_RESP_dma_rd_rsp_in_data, + input wire TX_RESP_dma_rd_rsp_in_last, + output wire TX_RESP_dma_rd_rsp_in_ready, + + output wire TX_RESP_dma_rd_rsp_out_valid, + output wire [127:0] TX_RESP_dma_rd_rsp_out_head, + output wire [511:0] TX_RESP_dma_rd_rsp_out_data, + output wire TX_RESP_dma_rd_rsp_out_last, + input wire TX_RESP_dma_rd_rsp_out_ready +); + +DMAWrReqChannel DMAWrReqChannel_CEU( //512 to 256 + .clk ( clk ), + .rst ( rst ), + + .dma_wr_req_in_valid ( CEU_dma_wr_req_in_valid ), + .dma_wr_req_in_head ( CEU_dma_wr_req_in_head ), + .dma_wr_req_in_data ( CEU_dma_wr_req_in_data ), + .dma_wr_req_in_last ( CEU_dma_wr_req_in_last ), + .dma_wr_req_in_ready ( CEU_dma_wr_req_in_ready ), + + .dma_wr_req_out_valid ( CEU_dma_wr_req_out_valid ), + .dma_wr_req_out_head ( CEU_dma_wr_req_out_head ), + .dma_wr_req_out_data ( CEU_dma_wr_req_out_data ), + .dma_wr_req_out_last ( CEU_dma_wr_req_out_last ), + .dma_wr_req_out_ready ( CEU_dma_wr_req_out_ready ) +); + +DMAWrReqChannel DMAWrReqChannel_QPC( //512 to 256 + .clk ( clk ), + .rst ( rst ), + + .dma_wr_req_in_valid ( QPC_dma_wr_req_in_valid ), + .dma_wr_req_in_head ( QPC_dma_wr_req_in_head ), + .dma_wr_req_in_data ( QPC_dma_wr_req_in_data ), + .dma_wr_req_in_last ( QPC_dma_wr_req_in_last ), + .dma_wr_req_in_ready ( QPC_dma_wr_req_in_ready ), + + .dma_wr_req_out_valid ( QPC_dma_wr_req_out_valid ), + .dma_wr_req_out_head ( QPC_dma_wr_req_out_head ), + .dma_wr_req_out_data ( QPC_dma_wr_req_out_data ), + .dma_wr_req_out_last ( QPC_dma_wr_req_out_last ), + .dma_wr_req_out_ready ( QPC_dma_wr_req_out_ready ) +); + +DMAWrReqChannel DMAWrReqChannel_CQC( //512 to 256 + .clk ( clk ), + .rst ( rst ), + + .dma_wr_req_in_valid ( CQC_dma_wr_req_in_valid ), + .dma_wr_req_in_head ( CQC_dma_wr_req_in_head ), + .dma_wr_req_in_data ( CQC_dma_wr_req_in_data ), + .dma_wr_req_in_last ( CQC_dma_wr_req_in_last ), + .dma_wr_req_in_ready ( CQC_dma_wr_req_in_ready ), + + .dma_wr_req_out_valid ( CQC_dma_wr_req_out_valid ), + .dma_wr_req_out_head ( CQC_dma_wr_req_out_head ), + .dma_wr_req_out_data ( CQC_dma_wr_req_out_data ), + .dma_wr_req_out_last ( CQC_dma_wr_req_out_last ), + .dma_wr_req_out_ready ( CQC_dma_wr_req_out_ready ) +); + +DMAWrReqChannel DMAWrReqChannel_EQC( //512 to 256 + .clk ( clk ), + .rst ( rst ), + + .dma_wr_req_in_valid ( EQC_dma_wr_req_in_valid ), + .dma_wr_req_in_head ( EQC_dma_wr_req_in_head ), + .dma_wr_req_in_data ( EQC_dma_wr_req_in_data ), + .dma_wr_req_in_last ( EQC_dma_wr_req_in_last ), + .dma_wr_req_in_ready ( EQC_dma_wr_req_in_ready ), + + .dma_wr_req_out_valid ( EQC_dma_wr_req_out_valid ), + .dma_wr_req_out_head ( EQC_dma_wr_req_out_head ), + .dma_wr_req_out_data ( EQC_dma_wr_req_out_data ), + .dma_wr_req_out_last ( EQC_dma_wr_req_out_last ), + .dma_wr_req_out_ready ( EQC_dma_wr_req_out_ready ) +); + +DMAWrReqChannel DMAWrReqChannel_MPT( //512 to 256 + .clk ( clk ), + .rst ( rst ), + + .dma_wr_req_in_valid ( MPT_dma_wr_req_in_valid ), + .dma_wr_req_in_head ( MPT_dma_wr_req_in_head ), + .dma_wr_req_in_data ( MPT_dma_wr_req_in_data ), + .dma_wr_req_in_last ( MPT_dma_wr_req_in_last ), + .dma_wr_req_in_ready ( MPT_dma_wr_req_in_ready ), + + .dma_wr_req_out_valid ( MPT_dma_wr_req_out_valid ), + .dma_wr_req_out_head ( MPT_dma_wr_req_out_head ), + .dma_wr_req_out_data ( MPT_dma_wr_req_out_data ), + .dma_wr_req_out_last ( MPT_dma_wr_req_out_last ), + .dma_wr_req_out_ready ( MPT_dma_wr_req_out_ready ) +); + +DMAWrReqChannel DMAWrReqChannel_MTT( //512 to 256 + .clk ( clk ), + .rst ( rst ), + + .dma_wr_req_in_valid ( MTT_dma_wr_req_in_valid ), + .dma_wr_req_in_head ( MTT_dma_wr_req_in_head ), + .dma_wr_req_in_data ( MTT_dma_wr_req_in_data ), + .dma_wr_req_in_last ( MTT_dma_wr_req_in_last ), + .dma_wr_req_in_ready ( MTT_dma_wr_req_in_ready ), + + .dma_wr_req_out_valid ( MTT_dma_wr_req_out_valid ), + .dma_wr_req_out_head ( MTT_dma_wr_req_out_head ), + .dma_wr_req_out_data ( MTT_dma_wr_req_out_data ), + .dma_wr_req_out_last ( MTT_dma_wr_req_out_last ), + .dma_wr_req_out_ready ( MTT_dma_wr_req_out_ready ) +); + +DMAWrReqChannel DMAWrReqChannel_TX_REQ( //512 to 256 + .clk ( clk ), + .rst ( rst ), + + .dma_wr_req_in_valid ( TX_REQ_dma_wr_req_in_valid ), + .dma_wr_req_in_head ( TX_REQ_dma_wr_req_in_head ), + .dma_wr_req_in_data ( TX_REQ_dma_wr_req_in_data ), + .dma_wr_req_in_last ( TX_REQ_dma_wr_req_in_last ), + .dma_wr_req_in_ready ( TX_REQ_dma_wr_req_in_ready ), + + .dma_wr_req_out_valid ( TX_REQ_dma_wr_req_out_valid ), + .dma_wr_req_out_head ( TX_REQ_dma_wr_req_out_head ), + .dma_wr_req_out_data ( TX_REQ_dma_wr_req_out_data ), + .dma_wr_req_out_last ( TX_REQ_dma_wr_req_out_last ), + .dma_wr_req_out_ready ( TX_REQ_dma_wr_req_out_ready ) +); + +DMAWrReqChannel DMAWrReqChannel_RX_REQ( //512 to 256 + .clk ( clk ), + .rst ( rst ), + + .dma_wr_req_in_valid ( RX_REQ_dma_wr_req_in_valid ), + .dma_wr_req_in_head ( RX_REQ_dma_wr_req_in_head ), + .dma_wr_req_in_data ( RX_REQ_dma_wr_req_in_data ), + .dma_wr_req_in_last ( RX_REQ_dma_wr_req_in_last ), + .dma_wr_req_in_ready ( RX_REQ_dma_wr_req_in_ready ), + + .dma_wr_req_out_valid ( RX_REQ_dma_wr_req_out_valid ), + .dma_wr_req_out_head ( RX_REQ_dma_wr_req_out_head ), + .dma_wr_req_out_data ( RX_REQ_dma_wr_req_out_data ), + .dma_wr_req_out_last ( RX_REQ_dma_wr_req_out_last ), + .dma_wr_req_out_ready ( RX_REQ_dma_wr_req_out_ready ) +); + +DMAWrReqChannel DMAWrReqChannel_RX_RESP( //512 to 256 + .clk ( clk ), + .rst ( rst ), + + .dma_wr_req_in_valid ( RX_RESP_dma_wr_req_in_valid ), + .dma_wr_req_in_head ( RX_RESP_dma_wr_req_in_head ), + .dma_wr_req_in_data ( RX_RESP_dma_wr_req_in_data ), + .dma_wr_req_in_last ( RX_RESP_dma_wr_req_in_last ), + .dma_wr_req_in_ready ( RX_RESP_dma_wr_req_in_ready ), + + .dma_wr_req_out_valid ( RX_RESP_dma_wr_req_out_valid ), + .dma_wr_req_out_head ( RX_RESP_dma_wr_req_out_head ), + .dma_wr_req_out_data ( RX_RESP_dma_wr_req_out_data ), + .dma_wr_req_out_last ( RX_RESP_dma_wr_req_out_last ), + .dma_wr_req_out_ready ( RX_RESP_dma_wr_req_out_ready ) +); + +DMARdRspChannel DMARdRspChannel_CEU( //512 to 256 + .clk ( clk ), + .rst ( rst ), + + .dma_rd_rsp_in_valid ( CEU_dma_rd_rsp_in_valid ), + .dma_rd_rsp_in_head ( CEU_dma_rd_rsp_in_head ), + .dma_rd_rsp_in_data ( CEU_dma_rd_rsp_in_data ), + .dma_rd_rsp_in_last ( CEU_dma_rd_rsp_in_last ), + .dma_rd_rsp_in_ready ( CEU_dma_rd_rsp_in_ready ), + + .dma_rd_rsp_out_valid ( CEU_dma_rd_rsp_out_valid ), + .dma_rd_rsp_out_head ( CEU_dma_rd_rsp_out_head ), + .dma_rd_rsp_out_data ( CEU_dma_rd_rsp_out_data ), + .dma_rd_rsp_out_last ( CEU_dma_rd_rsp_out_last ), + .dma_rd_rsp_out_ready ( CEU_dma_rd_rsp_out_ready ) +); + +DMARdRspChannel DMARdRspChannel_SQ( //512 to 256 + .clk ( clk ), + .rst ( rst ), + + .dma_rd_rsp_in_valid ( SQ_dma_rd_rsp_in_valid ), + .dma_rd_rsp_in_head ( SQ_dma_rd_rsp_in_head ), + .dma_rd_rsp_in_data ( SQ_dma_rd_rsp_in_data ), + .dma_rd_rsp_in_last ( SQ_dma_rd_rsp_in_last ), + .dma_rd_rsp_in_ready ( SQ_dma_rd_rsp_in_ready ), + + .dma_rd_rsp_out_valid ( SQ_dma_rd_rsp_out_valid ), + .dma_rd_rsp_out_head ( SQ_dma_rd_rsp_out_head ), + .dma_rd_rsp_out_data ( SQ_dma_rd_rsp_out_data ), + .dma_rd_rsp_out_last ( SQ_dma_rd_rsp_out_last ), + .dma_rd_rsp_out_ready ( SQ_dma_rd_rsp_out_ready ) +); + +DMARdRspChannel DMARdRspChannel_RQ( //512 to 256 + .clk ( clk ), + .rst ( rst ), + + .dma_rd_rsp_in_valid ( RQ_dma_rd_rsp_in_valid ), + .dma_rd_rsp_in_head ( RQ_dma_rd_rsp_in_head ), + .dma_rd_rsp_in_data ( RQ_dma_rd_rsp_in_data ), + .dma_rd_rsp_in_last ( RQ_dma_rd_rsp_in_last ), + .dma_rd_rsp_in_ready ( RQ_dma_rd_rsp_in_ready ), + + .dma_rd_rsp_out_valid ( RQ_dma_rd_rsp_out_valid ), + .dma_rd_rsp_out_head ( RQ_dma_rd_rsp_out_head ), + .dma_rd_rsp_out_data ( RQ_dma_rd_rsp_out_data ), + .dma_rd_rsp_out_last ( RQ_dma_rd_rsp_out_last ), + .dma_rd_rsp_out_ready ( RQ_dma_rd_rsp_out_ready ) +); + +DMARdRspChannel DMARdRspChannel_QPC( //512 to 256 + .clk ( clk ), + .rst ( rst ), + + .dma_rd_rsp_in_valid ( QPC_dma_rd_rsp_in_valid ), + .dma_rd_rsp_in_head ( QPC_dma_rd_rsp_in_head ), + .dma_rd_rsp_in_data ( QPC_dma_rd_rsp_in_data ), + .dma_rd_rsp_in_last ( QPC_dma_rd_rsp_in_last ), + .dma_rd_rsp_in_ready ( QPC_dma_rd_rsp_in_ready ), + + .dma_rd_rsp_out_valid ( QPC_dma_rd_rsp_out_valid ), + .dma_rd_rsp_out_head ( QPC_dma_rd_rsp_out_head ), + .dma_rd_rsp_out_data ( QPC_dma_rd_rsp_out_data ), + .dma_rd_rsp_out_last ( QPC_dma_rd_rsp_out_last ), + .dma_rd_rsp_out_ready ( QPC_dma_rd_rsp_out_ready ) +); + +DMARdRspChannel DMARdRspChannel_CQC( //512 to 256 + .clk ( clk ), + .rst ( rst ), + + .dma_rd_rsp_in_valid ( CQC_dma_rd_rsp_in_valid ), + .dma_rd_rsp_in_head ( CQC_dma_rd_rsp_in_head ), + .dma_rd_rsp_in_data ( CQC_dma_rd_rsp_in_data ), + .dma_rd_rsp_in_last ( CQC_dma_rd_rsp_in_last ), + .dma_rd_rsp_in_ready ( CQC_dma_rd_rsp_in_ready ), + + .dma_rd_rsp_out_valid ( CQC_dma_rd_rsp_out_valid ), + .dma_rd_rsp_out_head ( CQC_dma_rd_rsp_out_head ), + .dma_rd_rsp_out_data ( CQC_dma_rd_rsp_out_data ), + .dma_rd_rsp_out_last ( CQC_dma_rd_rsp_out_last ), + .dma_rd_rsp_out_ready ( CQC_dma_rd_rsp_out_ready ) +); + +DMARdRspChannel DMARdRspChannel_EQC( //512 to 256 + .clk ( clk ), + .rst ( rst ), + + .dma_rd_rsp_in_valid ( EQC_dma_rd_rsp_in_valid ), + .dma_rd_rsp_in_head ( EQC_dma_rd_rsp_in_head ), + .dma_rd_rsp_in_data ( EQC_dma_rd_rsp_in_data ), + .dma_rd_rsp_in_last ( EQC_dma_rd_rsp_in_last ), + .dma_rd_rsp_in_ready ( EQC_dma_rd_rsp_in_ready ), + + .dma_rd_rsp_out_valid ( EQC_dma_rd_rsp_out_valid ), + .dma_rd_rsp_out_head ( EQC_dma_rd_rsp_out_head ), + .dma_rd_rsp_out_data ( EQC_dma_rd_rsp_out_data ), + .dma_rd_rsp_out_last ( EQC_dma_rd_rsp_out_last ), + .dma_rd_rsp_out_ready ( EQC_dma_rd_rsp_out_ready ) +); + +DMARdRspChannel DMARdRspChannel_MPT( //512 to 256 + .clk ( clk ), + .rst ( rst ), + + .dma_rd_rsp_in_valid ( MPT_dma_rd_rsp_in_valid ), + .dma_rd_rsp_in_head ( MPT_dma_rd_rsp_in_head ), + .dma_rd_rsp_in_data ( MPT_dma_rd_rsp_in_data ), + .dma_rd_rsp_in_last ( MPT_dma_rd_rsp_in_last ), + .dma_rd_rsp_in_ready ( MPT_dma_rd_rsp_in_ready ), + + .dma_rd_rsp_out_valid ( MPT_dma_rd_rsp_out_valid ), + .dma_rd_rsp_out_head ( MPT_dma_rd_rsp_out_head ), + .dma_rd_rsp_out_data ( MPT_dma_rd_rsp_out_data ), + .dma_rd_rsp_out_last ( MPT_dma_rd_rsp_out_last ), + .dma_rd_rsp_out_ready ( MPT_dma_rd_rsp_out_ready ) +); + +DMARdRspChannel DMARdRspChannel_MTT( //512 to 256 + .clk ( clk ), + .rst ( rst ), + + .dma_rd_rsp_in_valid ( MTT_dma_rd_rsp_in_valid ), + .dma_rd_rsp_in_head ( MTT_dma_rd_rsp_in_head ), + .dma_rd_rsp_in_data ( MTT_dma_rd_rsp_in_data ), + .dma_rd_rsp_in_last ( MTT_dma_rd_rsp_in_last ), + .dma_rd_rsp_in_ready ( MTT_dma_rd_rsp_in_ready ), + + .dma_rd_rsp_out_valid ( MTT_dma_rd_rsp_out_valid ), + .dma_rd_rsp_out_head ( MTT_dma_rd_rsp_out_head ), + .dma_rd_rsp_out_data ( MTT_dma_rd_rsp_out_data ), + .dma_rd_rsp_out_last ( MTT_dma_rd_rsp_out_last ), + .dma_rd_rsp_out_ready ( MTT_dma_rd_rsp_out_ready ) +); + +DMARdRspChannel DMARdRspChannel_TX_REQ( //512 to 256 + .clk ( clk ), + .rst ( rst ), + + .dma_rd_rsp_in_valid ( TX_REQ_dma_rd_rsp_in_valid ), + .dma_rd_rsp_in_head ( TX_REQ_dma_rd_rsp_in_head ), + .dma_rd_rsp_in_data ( TX_REQ_dma_rd_rsp_in_data ), + .dma_rd_rsp_in_last ( TX_REQ_dma_rd_rsp_in_last ), + .dma_rd_rsp_in_ready ( TX_REQ_dma_rd_rsp_in_ready ), + + .dma_rd_rsp_out_valid ( TX_REQ_dma_rd_rsp_out_valid ), + .dma_rd_rsp_out_head ( TX_REQ_dma_rd_rsp_out_head ), + .dma_rd_rsp_out_data ( TX_REQ_dma_rd_rsp_out_data ), + .dma_rd_rsp_out_last ( TX_REQ_dma_rd_rsp_out_last ), + .dma_rd_rsp_out_ready ( TX_REQ_dma_rd_rsp_out_ready ) +); + +DMARdRspChannel DMARdRspChannel_TX_RESP( //512 to 256 + .clk ( clk ), + .rst ( rst ), + + .dma_rd_rsp_in_valid ( TX_RESP_dma_rd_rsp_in_valid ), + .dma_rd_rsp_in_head ( TX_RESP_dma_rd_rsp_in_head ), + .dma_rd_rsp_in_data ( TX_RESP_dma_rd_rsp_in_data ), + .dma_rd_rsp_in_last ( TX_RESP_dma_rd_rsp_in_last ), + .dma_rd_rsp_in_ready ( TX_RESP_dma_rd_rsp_in_ready ), + + .dma_rd_rsp_out_valid ( TX_RESP_dma_rd_rsp_out_valid ), + .dma_rd_rsp_out_head ( TX_RESP_dma_rd_rsp_out_head ), + .dma_rd_rsp_out_data ( TX_RESP_dma_rd_rsp_out_data ), + .dma_rd_rsp_out_last ( TX_RESP_dma_rd_rsp_out_last ), + .dma_rd_rsp_out_ready ( TX_RESP_dma_rd_rsp_out_ready ) +); + +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Top/HanGuHTN_Top.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Top/HanGuHTN_Top.v new file mode 100644 index 0000000000000000000000000000000000000000..b5a346e46efcfbd1b3a346ef8ec210d759149485 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Top/HanGuHTN_Top.v @@ -0,0 +1,1297 @@ +/*------------------------------------------- Module Description : Begin ---------------------------------------------- +Name: HanGuHTN_Top +Author: YangFan +Function: Intagrate . +--------------------------------------------- Module Decription : End -----------------------------------------------*/ + +/*------------------------------------------- Timescale Definition : Begin ------------------------------------------*/ +`timescale 1ns / 1ps +/*------------------------------------------- Timescale Definition : End --------------------------------------------*/ + +/*------------------------------------------- Included Files : Begin ------------------------------------------------*/ +`include "protocol_engine_def.vh" +/*------------------------------------------- Included Files : End --------------------------------------------------*/ + +/*------------------------------------------- Local Macros Definition : Begin ---------------------------------------*/ +/*------------------------------------------- Local Macros Definition : End -----------------------------------------*/ + +/*------------------------------------------- Input/Output Definition : Begin ---------------------------------------*/ +module HanGuHTN_Top +#( + parameter INGRESS_CXT_HEAD_WIDTH = 128, + parameter INGRESS_CXT_DATA_WIDTH = 256, + parameter EGRESS_CXT_HEAD_WIDTH = 128, + parameter EGRESS_CXT_DATA_WIDTH = 256, + + parameter INGRESS_MR_HEAD_WIDTH = 128, + parameter INGRESS_MR_DATA_WIDTH = 256, + parameter EGRESS_MR_HEAD_WIDTH = 128, + parameter EGRESS_MR_DATA_WIDTH = 256 +) +( + input wire pcie_clk, + input wire pcie_rst, + + input wire user_clk, + input wire user_rst, + + input wire mac_tx_clk, + input wire mac_tx_rst, + + input wire mac_rx_clk, + input wire mac_rx_rst, + +//Interface with Host + input wire [2:0] cfg_max_payload, + input wire [2:0] cfg_max_read_req, + input wire [12:0] tl_cfg_busdev, + + input wire [1:0] cfg_interrupt_msix_enable, + input wire [1:0] cfg_interrupt_msix_mask, + output wire [31:0] cfg_interrupt_msix_data, + output wire [63:0] cfg_interrupt_msix_address, + output wire cfg_interrupt_msix_int, + input wire cfg_interrupt_msix_sent, + input wire cfg_interrupt_msix_fail, + output wire [2:0] cfg_interrupt_msi_function_number, + + output wire s_axis_rq_tvalid, + output wire s_axis_rq_tlast, + output wire [`PCIEI_KEEP_W-1:0] s_axis_rq_tkeep, + output wire [59:0] s_axis_rq_tuser, + output wire [`PCIEI_DATA_W-1:0] s_axis_rq_tdata, + input wire [3:0] s_axis_rq_tready, + + input wire m_axis_rc_tvalid, + input wire m_axis_rc_tlast, + input wire [`PCIEI_KEEP_W-1:0] m_axis_rc_tkeep, + input wire [74:0] m_axis_rc_tuser, + input wire [`PCIEI_DATA_W-1:0] m_axis_rc_tdata, + output wire m_axis_rc_tready, + + input wire m_axis_cq_tvalid, + input wire m_axis_cq_tlast, + input wire [`PCIEI_KEEP_W-1:0] m_axis_cq_tkeep, + input wire [84:0] m_axis_cq_tuser, + input wire [`PCIEI_DATA_W-1:0] m_axis_cq_tdata, + output wire m_axis_cq_tready, + + output wire s_axis_cc_tvalid, + output wire s_axis_cc_tlast, + output wire [`PCIEI_KEEP_W-1:0] s_axis_cc_tkeep, + output wire [32:0] s_axis_cc_tuser, + output wire [`PCIEI_DATA_W-1:0] s_axis_cc_tdata, + input wire [3:0] s_axis_cc_tready, + +//Interface with Network + output wire mac_tx_valid, + input wire mac_tx_ready, + output wire mac_tx_start, + output wire mac_tx_last, + output wire [`MAC_KEEP_WIDTH - 1 : 0] mac_tx_keep, + output wire mac_tx_user, + output wire [`MAC_DATA_WIDTH - 1 : 0] mac_tx_data, + + input wire mac_rx_valid, + output wire mac_rx_ready, + input wire mac_rx_start, + input wire mac_rx_last, + input wire [`MAC_KEEP_WIDTH - 1 : 0] mac_rx_keep, + input wire mac_rx_user, + input wire [`MAC_DATA_WIDTH - 1 : 0] mac_rx_data +); + +/*------------------------------------------- Input/Output Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Variables Definition : Begin ------------------------------------*/ +wire [63:0] ceu_hcr_in_param; +wire [31:0] ceu_hcr_in_modifier; +wire [63:0] ceu_hcr_out_dma_addr; +wire [31:0] ceu_hcr_token; +wire ceu_hcr_go; +wire ceu_hcr_event; +wire [7:0] ceu_hcr_op_modifier; +wire [11:0] ceu_hcr_op; + +wire [63:0] ceu_hcr_out_param; +wire [7:0] ceu_hcr_status; +wire ceu_hcr_clear; + +wire CEU_dma_rd_req_valid; +wire CEU_dma_rd_req_last; +wire [`DMA_HEAD_WIDTH - 1 : 0] CEU_dma_rd_req_head; +wire [`DMA_DATA_WIDTH - 1 : 0] CEU_dma_rd_req_data; +wire CEU_dma_rd_req_ready; + +wire CEU_dma_rd_rsp_in_valid; +wire CEU_dma_rd_rsp_in_last; +wire [`DMA_HEAD_WIDTH - 1 : 0] CEU_dma_rd_rsp_in_head; +wire [255 : 0] CEU_dma_rd_rsp_in_data; +wire CEU_dma_rd_rsp_in_ready; + +wire CEU_dma_rd_rsp_out_valid; +wire CEU_dma_rd_rsp_out_last; +wire [`DMA_HEAD_WIDTH - 1 : 0] CEU_dma_rd_rsp_out_head; +wire [`DMA_DATA_WIDTH - 1 : 0] CEU_dma_rd_rsp_out_data; +wire CEU_dma_rd_rsp_out_ready; + +wire CEU_dma_wr_req_in_valid; +wire CEU_dma_wr_req_in_last; +wire [`DMA_HEAD_WIDTH - 1 : 0] CEU_dma_wr_req_in_head; +wire [`DMA_DATA_WIDTH - 1 : 0] CEU_dma_wr_req_in_data; +wire CEU_dma_wr_req_in_ready; + +wire CEU_dma_wr_req_out_valid; +wire CEU_dma_wr_req_out_last; +wire [`DMA_HEAD_WIDTH - 1 : 0] CEU_dma_wr_req_out_head; +wire [255 : 0] CEU_dma_wr_req_out_data; +wire CEU_dma_wr_req_out_ready; + +wire QPC_dma_rd_req_valid; +wire [`DMA_HEAD_WIDTH - 1 : 0] QPC_dma_rd_req_head; +wire [`DMA_DATA_WIDTH - 1 : 0] QPC_dma_rd_req_data; +wire QPC_dma_rd_req_last; +wire QPC_dma_rd_req_ready; + +wire QPC_dma_rd_rsp_in_valid; +wire QPC_dma_rd_rsp_in_last; +wire [`DMA_HEAD_WIDTH - 1 : 0] QPC_dma_rd_rsp_in_head; +wire [255 : 0] QPC_dma_rd_rsp_in_data; +wire QPC_dma_rd_rsp_in_ready; + +wire QPC_dma_rd_rsp_out_valid; +wire QPC_dma_rd_rsp_out_last; +wire [`DMA_HEAD_WIDTH - 1 : 0] QPC_dma_rd_rsp_out_head; +wire [`DMA_DATA_WIDTH - 1 : 0] QPC_dma_rd_rsp_out_data; +wire QPC_dma_rd_rsp_out_ready; + +wire QPC_dma_wr_req_in_valid; +wire QPC_dma_wr_req_in_last; +wire [`DMA_HEAD_WIDTH - 1 : 0] QPC_dma_wr_req_in_head; +wire [`DMA_DATA_WIDTH - 1 : 0] QPC_dma_wr_req_in_data; +wire QPC_dma_wr_req_in_ready; + +wire QPC_dma_wr_req_out_valid; +wire QPC_dma_wr_req_out_last; +wire [`DMA_HEAD_WIDTH - 1 : 0] QPC_dma_wr_req_out_head; +wire [255 : 0] QPC_dma_wr_req_out_data; +wire QPC_dma_wr_req_out_ready; + +wire CQC_dma_rd_req_valid; +wire [`DMA_HEAD_WIDTH - 1 : 0] CQC_dma_rd_req_head; +wire [`DMA_DATA_WIDTH - 1 : 0] CQC_dma_rd_req_data; +wire CQC_dma_rd_req_last; +wire CQC_dma_rd_req_ready; + +wire CQC_dma_rd_rsp_in_valid; +wire CQC_dma_rd_rsp_in_last; +wire [`DMA_HEAD_WIDTH - 1 : 0] CQC_dma_rd_rsp_in_head; +wire [255 : 0] CQC_dma_rd_rsp_in_data; +wire CQC_dma_rd_rsp_in_ready; + +wire CQC_dma_rd_rsp_out_valid; +wire CQC_dma_rd_rsp_out_last; +wire [`DMA_HEAD_WIDTH - 1 : 0] CQC_dma_rd_rsp_out_head; +wire [`DMA_DATA_WIDTH - 1 : 0] CQC_dma_rd_rsp_out_data; +wire CQC_dma_rd_rsp_out_ready; + +wire CQC_dma_wr_req_in_valid; +wire CQC_dma_wr_req_in_last; +wire [`DMA_HEAD_WIDTH - 1 : 0] CQC_dma_wr_req_in_head; +wire [`DMA_DATA_WIDTH - 1 : 0] CQC_dma_wr_req_in_data; +wire CQC_dma_wr_req_in_ready; + +wire CQC_dma_wr_req_out_valid; +wire CQC_dma_wr_req_out_last; +wire [`DMA_HEAD_WIDTH - 1 : 0] CQC_dma_wr_req_out_head; +wire [255 : 0] CQC_dma_wr_req_out_data; +wire CQC_dma_wr_req_out_ready; + +wire EQC_dma_rd_req_valid; +wire [`DMA_HEAD_WIDTH - 1 : 0] EQC_dma_rd_req_head; +wire [`DMA_DATA_WIDTH - 1 : 0] EQC_dma_rd_req_data; +wire EQC_dma_rd_req_last; +wire EQC_dma_rd_req_ready; + +wire EQC_dma_rd_rsp_in_valid; +wire EQC_dma_rd_rsp_in_last; +wire [`DMA_HEAD_WIDTH - 1 : 0] EQC_dma_rd_rsp_in_head; +wire [255 : 0] EQC_dma_rd_rsp_in_data; +wire EQC_dma_rd_rsp_in_ready; + +wire EQC_dma_rd_rsp_out_valid; +wire EQC_dma_rd_rsp_out_last; +wire [`DMA_HEAD_WIDTH - 1 : 0] EQC_dma_rd_rsp_out_head; +wire [`DMA_DATA_WIDTH - 1 : 0] EQC_dma_rd_rsp_out_data; +wire EQC_dma_rd_rsp_out_ready; + +wire EQC_dma_wr_req_in_valid; +wire EQC_dma_wr_req_in_last; +wire [`DMA_HEAD_WIDTH - 1 : 0] EQC_dma_wr_req_in_head; +wire [`DMA_DATA_WIDTH - 1 : 0] EQC_dma_wr_req_in_data; +wire EQC_dma_wr_req_in_ready; + +wire EQC_dma_wr_req_out_valid; +wire EQC_dma_wr_req_out_last; +wire [`DMA_HEAD_WIDTH - 1 : 0] EQC_dma_wr_req_out_head; +wire [255 : 0] EQC_dma_wr_req_out_data; +wire EQC_dma_wr_req_out_ready; + +wire MPT_dma_rd_req_valid; +wire [`DMA_HEAD_WIDTH - 1 : 0] MPT_dma_rd_req_head; +wire [`DMA_DATA_WIDTH - 1 : 0] MPT_dma_rd_req_data; +wire MPT_dma_rd_req_last; +wire MPT_dma_rd_req_ready; + +wire MPT_dma_rd_rsp_in_valid; +wire MPT_dma_rd_rsp_in_last; +wire [`DMA_HEAD_WIDTH - 1 : 0] MPT_dma_rd_rsp_in_head; +wire [255 : 0] MPT_dma_rd_rsp_in_data; +wire MPT_dma_rd_rsp_in_ready; + +wire MPT_dma_rd_rsp_out_valid; +wire MPT_dma_rd_rsp_out_last; +wire [`DMA_HEAD_WIDTH - 1 : 0] MPT_dma_rd_rsp_out_head; +wire [`DMA_DATA_WIDTH - 1 : 0] MPT_dma_rd_rsp_out_data; +wire MPT_dma_rd_rsp_out_ready; + +wire MPT_dma_wr_req_in_valid; +wire MPT_dma_wr_req_in_last; +wire [`DMA_HEAD_WIDTH - 1 : 0] MPT_dma_wr_req_in_head; +wire [`DMA_DATA_WIDTH - 1 : 0] MPT_dma_wr_req_in_data; +wire MPT_dma_wr_req_in_ready; + +wire MPT_dma_wr_req_out_valid; +wire MPT_dma_wr_req_out_last; +wire [`DMA_HEAD_WIDTH - 1 : 0] MPT_dma_wr_req_out_head; +wire [255 : 0] MPT_dma_wr_req_out_data; +wire MPT_dma_wr_req_out_ready; + +wire MTT_dma_rd_req_valid; +wire [`DMA_HEAD_WIDTH - 1 : 0] MTT_dma_rd_req_head; +wire [`DMA_DATA_WIDTH - 1 : 0] MTT_dma_rd_req_data; +wire MTT_dma_rd_req_last; +wire MTT_dma_rd_req_ready; + +wire MTT_dma_rd_rsp_in_valid; +wire MTT_dma_rd_rsp_in_last; +wire [`DMA_HEAD_WIDTH - 1 : 0] MTT_dma_rd_rsp_in_head; +wire [255 : 0] MTT_dma_rd_rsp_in_data; +wire MTT_dma_rd_rsp_in_ready; + +wire MTT_dma_rd_rsp_out_valid; +wire MTT_dma_rd_rsp_out_last; +wire [`DMA_HEAD_WIDTH - 1 : 0] MTT_dma_rd_rsp_out_head; +wire [`DMA_DATA_WIDTH - 1 : 0] MTT_dma_rd_rsp_out_data; +wire MTT_dma_rd_rsp_out_ready; + +wire MTT_dma_wr_req_in_valid; +wire MTT_dma_wr_req_in_last; +wire [`DMA_HEAD_WIDTH - 1 : 0] MTT_dma_wr_req_in_head; +wire [`DMA_DATA_WIDTH - 1 : 0] MTT_dma_wr_req_in_data; +wire MTT_dma_wr_req_in_ready; + +wire MTT_dma_wr_req_out_valid; +wire MTT_dma_wr_req_out_last; +wire [`DMA_HEAD_WIDTH - 1 : 0] MTT_dma_wr_req_out_head; +wire [255 : 0] MTT_dma_wr_req_out_data; +wire MTT_dma_wr_req_out_ready; + +wire SQ_dma_rd_req_valid; +wire [`DMA_HEAD_WIDTH - 1 : 0] SQ_dma_rd_req_head; +wire [`DMA_DATA_WIDTH - 1 : 0] SQ_dma_rd_req_data; +wire SQ_dma_rd_req_last; +wire SQ_dma_rd_req_ready; + +wire SQ_dma_rd_rsp_in_valid; +wire SQ_dma_rd_rsp_in_last; +wire [`DMA_HEAD_WIDTH - 1 : 0] SQ_dma_rd_rsp_in_head; +wire [255 : 0] SQ_dma_rd_rsp_in_data; +wire SQ_dma_rd_rsp_in_ready; + +wire SQ_dma_rd_rsp_out_valid; +wire SQ_dma_rd_rsp_out_last; +wire [`DMA_HEAD_WIDTH - 1 : 0] SQ_dma_rd_rsp_out_head; +wire [`DMA_DATA_WIDTH - 1 : 0] SQ_dma_rd_rsp_out_data; +wire SQ_dma_rd_rsp_out_ready; + +wire RQ_dma_rd_req_valid; +wire [`DMA_HEAD_WIDTH - 1 : 0] RQ_dma_rd_req_head; +wire [`DMA_DATA_WIDTH - 1 : 0] RQ_dma_rd_req_data; +wire RQ_dma_rd_req_last; +wire RQ_dma_rd_req_ready; + +wire RQ_dma_rd_rsp_in_valid; +wire RQ_dma_rd_rsp_in_last; +wire [`DMA_HEAD_WIDTH - 1 : 0] RQ_dma_rd_rsp_in_head; +wire [255 : 0] RQ_dma_rd_rsp_in_data; +wire RQ_dma_rd_rsp_in_ready; + +wire RQ_dma_rd_rsp_out_valid; +wire RQ_dma_rd_rsp_out_last; +wire [`DMA_HEAD_WIDTH - 1 : 0] RQ_dma_rd_rsp_out_head; +wire [`DMA_DATA_WIDTH - 1 : 0] RQ_dma_rd_rsp_out_data; +wire RQ_dma_rd_rsp_out_ready; + +wire TX_REQ_dma_wr_req_in_valid; +wire TX_REQ_dma_wr_req_in_last; +wire [`DMA_HEAD_WIDTH - 1 : 0] TX_REQ_dma_wr_req_in_head; +wire [`DMA_DATA_WIDTH - 1 : 0] TX_REQ_dma_wr_req_in_data; +wire TX_REQ_dma_wr_req_in_ready; + +wire TX_REQ_dma_wr_req_out_valid; +wire TX_REQ_dma_wr_req_out_last; +wire [`DMA_HEAD_WIDTH - 1 : 0] TX_REQ_dma_wr_req_out_head; +wire [255 : 0] TX_REQ_dma_wr_req_out_data; +wire TX_REQ_dma_wr_req_out_ready; + +wire RX_REQ_dma_wr_req_in_valid; +wire RX_REQ_dma_wr_req_in_last; +wire [`DMA_HEAD_WIDTH - 1 : 0] RX_REQ_dma_wr_req_in_head; +wire [`DMA_DATA_WIDTH - 1 : 0] RX_REQ_dma_wr_req_in_data; +wire RX_REQ_dma_wr_req_in_ready; + +wire RX_REQ_dma_wr_req_out_valid; +wire RX_REQ_dma_wr_req_out_last; +wire [`DMA_HEAD_WIDTH - 1 : 0] RX_REQ_dma_wr_req_out_head; +wire [255 : 0] RX_REQ_dma_wr_req_out_data; +wire RX_REQ_dma_wr_req_out_ready; + +wire RX_RESP_dma_wr_req_in_valid; +wire RX_RESP_dma_wr_req_in_last; +wire [`DMA_HEAD_WIDTH - 1 : 0] RX_RESP_dma_wr_req_in_head; +wire [`DMA_DATA_WIDTH - 1 : 0] RX_RESP_dma_wr_req_in_data; +wire RX_RESP_dma_wr_req_in_ready; + +wire RX_RESP_dma_wr_req_out_valid; +wire RX_RESP_dma_wr_req_out_last; +wire [`DMA_HEAD_WIDTH - 1 : 0] RX_RESP_dma_wr_req_out_head; +wire [255 : 0] RX_RESP_dma_wr_req_out_data; +wire RX_RESP_dma_wr_req_out_ready; + +wire TX_REQ_dma_rd_req_valid; +wire [`DMA_HEAD_WIDTH - 1 : 0] TX_REQ_dma_rd_req_head; +wire [`DMA_DATA_WIDTH - 1 : 0] TX_REQ_dma_rd_req_data; +wire TX_REQ_dma_rd_req_last; +wire TX_REQ_dma_rd_req_ready; + +wire TX_REQ_dma_rd_rsp_in_valid; +wire TX_REQ_dma_rd_rsp_in_last; +wire [`DMA_HEAD_WIDTH - 1 : 0] TX_REQ_dma_rd_rsp_in_head; +wire [255 : 0] TX_REQ_dma_rd_rsp_in_data; +wire TX_REQ_dma_rd_rsp_in_ready; + +wire TX_REQ_dma_rd_rsp_out_valid; +wire TX_REQ_dma_rd_rsp_out_last; +wire [`DMA_HEAD_WIDTH - 1 : 0] TX_REQ_dma_rd_rsp_out_head; +wire [`DMA_DATA_WIDTH - 1 : 0] TX_REQ_dma_rd_rsp_out_data; +wire TX_REQ_dma_rd_rsp_out_ready; + +wire TX_RESP_dma_rd_req_valid; +wire [`DMA_HEAD_WIDTH - 1 : 0] TX_RESP_dma_rd_req_head; +wire [`DMA_DATA_WIDTH - 1 : 0] TX_RESP_dma_rd_req_data; +wire TX_RESP_dma_rd_req_last; +wire TX_RESP_dma_rd_req_ready; + +wire TX_RESP_dma_rd_rsp_in_valid; +wire TX_RESP_dma_rd_rsp_in_last; +wire [`DMA_HEAD_WIDTH - 1 : 0] TX_RESP_dma_rd_rsp_in_head; +wire [255 : 0] TX_RESP_dma_rd_rsp_in_data; +wire TX_RESP_dma_rd_rsp_in_ready; + +wire TX_RESP_dma_rd_rsp_out_valid; +wire TX_RESP_dma_rd_rsp_out_last; +wire [`DMA_HEAD_WIDTH - 1 : 0] TX_RESP_dma_rd_rsp_out_head; +wire [`DMA_DATA_WIDTH - 1 : 0] TX_RESP_dma_rd_rsp_out_data; +wire TX_RESP_dma_rd_rsp_out_ready; + +wire db_fifo_wen; +wire [63:0] db_fifo_din; +wire db_fifo_prog_full; + +wire db_fifo_ren; +wire [63:0] db_fifo_dout; +wire db_fifo_empty; + +wire [1 * `DMA_RD_CHNL_NUM - 1 : 0] DMA_RD_req_valid; +wire [`DMA_HEAD_WIDTH * `DMA_RD_CHNL_NUM - 1 : 0] DMA_RD_req_head; +wire [`DMA_DATA_WIDTH * `DMA_RD_CHNL_NUM - 1 : 0] DMA_RD_req_data; +wire [1 * `DMA_RD_CHNL_NUM - 1 : 0] DMA_RD_req_last; +wire [1 * `DMA_RD_CHNL_NUM - 1 : 0] DMA_RD_req_ready; + +wire [1 * `DMA_RD_CHNL_NUM - 1 : 0] DMA_RD_rsp_in_valid; +wire [`DMA_HEAD_WIDTH * `DMA_RD_CHNL_NUM - 1 : 0] DMA_RD_rsp_in_head; +wire [256 * `DMA_RD_CHNL_NUM - 1 : 0] DMA_RD_rsp_in_data; +wire [1 * `DMA_RD_CHNL_NUM - 1 : 0] DMA_RD_rsp_in_last; +wire [1 * `DMA_RD_CHNL_NUM - 1 : 0] DMA_RD_rsp_in_ready; + +wire [1 * (`DMA_WR_CHNL_NUM - 1) - 1 : 0] DMA_WR_req_out_valid; +wire [`DMA_HEAD_WIDTH * (`DMA_WR_CHNL_NUM - 1) - 1 : 0] DMA_WR_req_out_head; +wire [256 * (`DMA_WR_CHNL_NUM - 1) - 1 : 0] DMA_WR_req_out_data; +wire [1 * (`DMA_WR_CHNL_NUM - 1) - 1 : 0] DMA_WR_req_out_last; +wire [1 * (`DMA_WR_CHNL_NUM - 1) - 1 : 0] DMA_WR_req_out_ready; +/*------------------------------------------- Local Variables Definition : End --------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : Begin ---------------------------------------*/ +ProtocolEngine_Top ProtocolEngine_Top_Inst( + .user_clk ( user_clk ), + .user_rst ( user_rst ), + + .mac_tx_clk ( mac_tx_clk ), + .mac_tx_rst ( mac_tx_rst ), + + .mac_rx_clk ( mac_rx_clk ), + .mac_rx_rst ( mac_rx_rst ), + + .ceu_hcr_in_param ( ceu_hcr_in_param ), + .ceu_hcr_in_modifier ( ceu_hcr_in_modifier ), + .ceu_hcr_out_dma_addr ( ceu_hcr_out_dma_addr ), + .ceu_hcr_token ( ceu_hcr_token ), + .ceu_hcr_go ( ceu_hcr_go ), + .ceu_hcr_event ( ceu_hcr_event ), + .ceu_hcr_op_modifier ( ceu_hcr_op_modifier ), + .ceu_hcr_op ( ceu_hcr_op ), + + .ceu_hcr_out_param ( ceu_hcr_out_param ), + .ceu_hcr_status ( ceu_hcr_status ), + .ceu_hcr_clear ( ceu_hcr_clear ), + + .CEU_dma_rd_req_valid ( CEU_dma_rd_req_valid ), + .CEU_dma_rd_req_last ( CEU_dma_rd_req_last ), + .CEU_dma_rd_req_head ( CEU_dma_rd_req_head ), + .CEU_dma_rd_req_data ( CEU_dma_rd_req_data ), + .CEU_dma_rd_req_ready ( CEU_dma_rd_req_ready ), + + .CEU_dma_rd_rsp_valid ( CEU_dma_rd_rsp_out_valid ), + .CEU_dma_rd_rsp_last ( CEU_dma_rd_rsp_out_last ), + .CEU_dma_rd_rsp_head ( CEU_dma_rd_rsp_out_head ), + .CEU_dma_rd_rsp_data ( CEU_dma_rd_rsp_out_data ), + .CEU_dma_rd_rsp_ready ( CEU_dma_rd_rsp_out_ready ), + + .CEU_dma_wr_req_valid ( CEU_dma_wr_req_in_valid ), + .CEU_dma_wr_req_last ( CEU_dma_wr_req_in_last ), + .CEU_dma_wr_req_head ( CEU_dma_wr_req_in_head ), + .CEU_dma_wr_req_data ( CEU_dma_wr_req_in_data ), + .CEU_dma_wr_req_ready ( CEU_dma_wr_req_in_ready ), + + .db_fifo_empty ( db_fifo_empty ), + .db_fifo_dout ( db_fifo_dout ), + .db_fifo_rd_en ( db_fifo_ren ), + + .QPC_dma_rd_req_valid ( QPC_dma_rd_req_valid ), + .QPC_dma_rd_req_head ( QPC_dma_rd_req_head ), + .QPC_dma_rd_req_data ( QPC_dma_rd_req_data ), + .QPC_dma_rd_req_last ( QPC_dma_rd_req_last ), + .QPC_dma_rd_req_ready ( QPC_dma_rd_req_ready ), + + .QPC_dma_rd_rsp_valid ( QPC_dma_rd_rsp_out_valid ), + .QPC_dma_rd_rsp_head ( QPC_dma_rd_rsp_out_head ), + .QPC_dma_rd_rsp_data ( QPC_dma_rd_rsp_out_data ), + .QPC_dma_rd_rsp_last ( QPC_dma_rd_rsp_out_last ), + .QPC_dma_rd_rsp_ready ( QPC_dma_rd_rsp_out_ready ), + + .QPC_dma_wr_req_valid ( QPC_dma_wr_req_in_valid ), + .QPC_dma_wr_req_head ( QPC_dma_wr_req_in_head ), + .QPC_dma_wr_req_data ( QPC_dma_wr_req_in_data ), + .QPC_dma_wr_req_last ( QPC_dma_wr_req_in_last ), + .QPC_dma_wr_req_ready ( QPC_dma_wr_req_in_ready ), + + .CQC_dma_rd_req_valid ( CQC_dma_rd_req_valid ), + .CQC_dma_rd_req_head ( CQC_dma_rd_req_head ), + .CQC_dma_rd_req_data ( CQC_dma_rd_req_data ), + .CQC_dma_rd_req_last ( CQC_dma_rd_req_last ), + .CQC_dma_rd_req_ready ( CQC_dma_rd_req_ready ), + + .CQC_dma_rd_rsp_valid ( CQC_dma_rd_rsp_out_valid ), + .CQC_dma_rd_rsp_head ( CQC_dma_rd_rsp_out_head ), + .CQC_dma_rd_rsp_data ( CQC_dma_rd_rsp_out_data ), + .CQC_dma_rd_rsp_last ( CQC_dma_rd_rsp_out_last ), + .CQC_dma_rd_rsp_ready ( CQC_dma_rd_rsp_out_ready ), + + .CQC_dma_wr_req_valid ( CQC_dma_wr_req_in_valid ), + .CQC_dma_wr_req_head ( CQC_dma_wr_req_in_head ), + .CQC_dma_wr_req_data ( CQC_dma_wr_req_in_data ), + .CQC_dma_wr_req_last ( CQC_dma_wr_req_in_last ), + .CQC_dma_wr_req_ready ( CQC_dma_wr_req_in_ready ), + + .EQC_dma_rd_req_valid ( EQC_dma_rd_req_valid ), + .EQC_dma_rd_req_head ( EQC_dma_rd_req_head ), + .EQC_dma_rd_req_data ( EQC_dma_rd_req_data ), + .EQC_dma_rd_req_last ( EQC_dma_rd_req_last ), + .EQC_dma_rd_req_ready ( EQC_dma_rd_req_ready ), + + .EQC_dma_rd_rsp_valid ( EQC_dma_rd_rsp_out_valid ), + .EQC_dma_rd_rsp_head ( EQC_dma_rd_rsp_out_head ), + .EQC_dma_rd_rsp_data ( EQC_dma_rd_rsp_out_data ), + .EQC_dma_rd_rsp_last ( EQC_dma_rd_rsp_out_last ), + .EQC_dma_rd_rsp_ready ( EQC_dma_rd_rsp_out_ready ), + + .EQC_dma_wr_req_valid ( EQC_dma_wr_req_in_valid ), + .EQC_dma_wr_req_head ( EQC_dma_wr_req_in_head ), + .EQC_dma_wr_req_data ( EQC_dma_wr_req_in_data ), + .EQC_dma_wr_req_last ( EQC_dma_wr_req_in_last ), + .EQC_dma_wr_req_ready ( EQC_dma_wr_req_in_ready ), + + .MPT_dma_rd_req_valid ( MPT_dma_rd_req_valid ), + .MPT_dma_rd_req_head ( MPT_dma_rd_req_head ), + .MPT_dma_rd_req_data ( MPT_dma_rd_req_data ), + .MPT_dma_rd_req_last ( MPT_dma_rd_req_last ), + .MPT_dma_rd_req_ready ( MPT_dma_rd_req_ready ), + + .MPT_dma_rd_rsp_valid ( MPT_dma_rd_rsp_out_valid ), + .MPT_dma_rd_rsp_head ( MPT_dma_rd_rsp_out_head ), + .MPT_dma_rd_rsp_data ( MPT_dma_rd_rsp_out_data ), + .MPT_dma_rd_rsp_last ( MPT_dma_rd_rsp_out_last ), + .MPT_dma_rd_rsp_ready ( MPT_dma_rd_rsp_out_ready ), + + .MPT_dma_wr_req_valid ( MPT_dma_wr_req_in_valid ), + .MPT_dma_wr_req_head ( MPT_dma_wr_req_in_head ), + .MPT_dma_wr_req_data ( MPT_dma_wr_req_in_data ), + .MPT_dma_wr_req_last ( MPT_dma_wr_req_in_last ), + .MPT_dma_wr_req_ready ( MPT_dma_wr_req_in_ready ), + + .MTT_dma_rd_req_valid ( MTT_dma_rd_req_valid ), + .MTT_dma_rd_req_head ( MTT_dma_rd_req_head ), + .MTT_dma_rd_req_data ( MTT_dma_rd_req_data ), + .MTT_dma_rd_req_last ( MTT_dma_rd_req_last ), + .MTT_dma_rd_req_ready ( MTT_dma_rd_req_ready ), + + .MTT_dma_rd_rsp_valid ( MTT_dma_rd_rsp_out_valid ), + .MTT_dma_rd_rsp_head ( MTT_dma_rd_rsp_out_head ), + .MTT_dma_rd_rsp_data ( MTT_dma_rd_rsp_out_data ), + .MTT_dma_rd_rsp_last ( MTT_dma_rd_rsp_out_last ), + .MTT_dma_rd_rsp_ready ( MTT_dma_rd_rsp_out_ready ), + + .MTT_dma_wr_req_valid ( MTT_dma_wr_req_in_valid ), + .MTT_dma_wr_req_head ( MTT_dma_wr_req_in_head ), + .MTT_dma_wr_req_data ( MTT_dma_wr_req_in_data ), + .MTT_dma_wr_req_last ( MTT_dma_wr_req_in_last ), + .MTT_dma_wr_req_ready ( MTT_dma_wr_req_in_ready ), + + .SQ_dma_rd_req_valid ( SQ_dma_rd_req_valid ), + .SQ_dma_rd_req_head ( SQ_dma_rd_req_head ), + .SQ_dma_rd_req_data ( SQ_dma_rd_req_data ), + .SQ_dma_rd_req_last ( SQ_dma_rd_req_last ), + .SQ_dma_rd_req_ready ( SQ_dma_rd_req_ready ), + + .SQ_dma_rd_rsp_valid ( SQ_dma_rd_rsp_out_valid ), + .SQ_dma_rd_rsp_head ( SQ_dma_rd_rsp_out_head ), + .SQ_dma_rd_rsp_data ( SQ_dma_rd_rsp_out_data ), + .SQ_dma_rd_rsp_last ( SQ_dma_rd_rsp_out_last ), + .SQ_dma_rd_rsp_ready ( SQ_dma_rd_rsp_out_ready ), + + .RQ_dma_rd_req_valid ( RQ_dma_rd_req_valid ), + .RQ_dma_rd_req_head ( RQ_dma_rd_req_head ), + .RQ_dma_rd_req_data ( RQ_dma_rd_req_data ), + .RQ_dma_rd_req_last ( RQ_dma_rd_req_last ), + .RQ_dma_rd_req_ready ( RQ_dma_rd_req_ready ), + + .RQ_dma_rd_rsp_valid ( RQ_dma_rd_rsp_out_valid ), + .RQ_dma_rd_rsp_head ( RQ_dma_rd_rsp_out_head ), + .RQ_dma_rd_rsp_data ( RQ_dma_rd_rsp_out_data ), + .RQ_dma_rd_rsp_last ( RQ_dma_rd_rsp_out_last ), + .RQ_dma_rd_rsp_ready ( RQ_dma_rd_rsp_out_ready ), + + .TX_REQ_dma_wr_req_valid ( TX_REQ_dma_wr_req_in_valid ), + .TX_REQ_dma_wr_req_last ( TX_REQ_dma_wr_req_in_last ), + .TX_REQ_dma_wr_req_head ( TX_REQ_dma_wr_req_in_head ), + .TX_REQ_dma_wr_req_data ( TX_REQ_dma_wr_req_in_data ), + .TX_REQ_dma_wr_req_ready ( TX_REQ_dma_wr_req_in_ready ), + + .RX_REQ_dma_wr_req_valid ( RX_REQ_dma_wr_req_in_valid ), + .RX_REQ_dma_wr_req_last ( RX_REQ_dma_wr_req_in_last ), + .RX_REQ_dma_wr_req_head ( RX_REQ_dma_wr_req_in_head ), + .RX_REQ_dma_wr_req_data ( RX_REQ_dma_wr_req_in_data ), + .RX_REQ_dma_wr_req_ready ( RX_REQ_dma_wr_req_in_ready ), + + .RX_RESP_dma_wr_req_valid ( RX_RESP_dma_wr_req_in_valid ), + .RX_RESP_dma_wr_req_last ( RX_RESP_dma_wr_req_in_last ), + .RX_RESP_dma_wr_req_head ( RX_RESP_dma_wr_req_in_head ), + .RX_RESP_dma_wr_req_data ( RX_RESP_dma_wr_req_in_data ), + .RX_RESP_dma_wr_req_ready ( RX_RESP_dma_wr_req_in_ready ), + + .TX_REQ_dma_rd_req_valid ( TX_REQ_dma_rd_req_valid ), + .TX_REQ_dma_rd_req_head ( TX_REQ_dma_rd_req_head ), + .TX_REQ_dma_rd_req_data ( TX_REQ_dma_rd_req_data ), + .TX_REQ_dma_rd_req_last ( TX_REQ_dma_rd_req_last ), + .TX_REQ_dma_rd_req_ready ( TX_REQ_dma_rd_req_ready ), + + .TX_REQ_dma_rd_rsp_valid ( TX_REQ_dma_rd_rsp_out_valid ), + .TX_REQ_dma_rd_rsp_head ( TX_REQ_dma_rd_rsp_out_head ), + .TX_REQ_dma_rd_rsp_data ( TX_REQ_dma_rd_rsp_out_data ), + .TX_REQ_dma_rd_rsp_last ( TX_REQ_dma_rd_rsp_out_last ), + .TX_REQ_dma_rd_rsp_ready ( TX_REQ_dma_rd_rsp_out_ready ), + + .TX_RESP_dma_rd_req_valid ( TX_RESP_dma_rd_req_valid ), + .TX_RESP_dma_rd_req_head ( TX_RESP_dma_rd_req_head ), + .TX_RESP_dma_rd_req_data ( TX_RESP_dma_rd_req_data ), + .TX_RESP_dma_rd_req_last ( TX_RESP_dma_rd_req_last ), + .TX_RESP_dma_rd_req_ready ( TX_RESP_dma_rd_req_ready ), + + .TX_RESP_dma_rd_rsp_valid ( TX_RESP_dma_rd_rsp_out_valid ), + .TX_RESP_dma_rd_rsp_head ( TX_RESP_dma_rd_rsp_out_head ), + .TX_RESP_dma_rd_rsp_data ( TX_RESP_dma_rd_rsp_out_data ), + .TX_RESP_dma_rd_rsp_last ( TX_RESP_dma_rd_rsp_out_last ), + .TX_RESP_dma_rd_rsp_ready ( TX_RESP_dma_rd_rsp_out_ready ), + + .mac_tx_valid ( mac_tx_valid ), + .mac_tx_ready ( mac_tx_ready ), + .mac_tx_start ( mac_tx_start ), + .mac_tx_last ( mac_tx_last ), + .mac_tx_keep ( mac_tx_keep ), + .mac_tx_user ( mac_tx_user ), + .mac_tx_data ( mac_tx_data ), + + .mac_rx_valid ( mac_rx_valid ), + .mac_rx_ready ( mac_rx_ready ), + .mac_rx_start ( mac_rx_start ), + .mac_rx_last ( mac_rx_last ), + .mac_rx_keep ( mac_rx_keep ), + .mac_rx_user ( mac_rx_user ), + .mac_rx_data ( mac_rx_data ) +); + +PCIe_Interface PCIe_Interface_Inst( + .pcie_clk ( pcie_clk ), + .pcie_rst_n ( ~pcie_rst ), + .user_clk ( user_clk ), + .user_rst_n ( ~user_rst ), + + .rdma_init_done ( 1'b1 ), + + .s_axis_rq_tvalid ( s_axis_rq_tvalid ), + .s_axis_rq_tlast ( s_axis_rq_tlast ), + .s_axis_rq_tkeep ( s_axis_rq_tkeep ), + .s_axis_rq_tuser ( s_axis_rq_tuser ), + .s_axis_rq_tdata ( s_axis_rq_tdata ), + .s_axis_rq_tready ( s_axis_rq_tready ), + + .m_axis_rc_tvalid ( m_axis_rc_tvalid ), + .m_axis_rc_tlast ( m_axis_rc_tlast ), + .m_axis_rc_tkeep ( m_axis_rc_tkeep ), + .m_axis_rc_tuser ( m_axis_rc_tuser ), + .m_axis_rc_tdata ( m_axis_rc_tdata ), + .m_axis_rc_tready ( m_axis_rc_tready ), + + .m_axis_cq_tvalid ( m_axis_cq_tvalid ), + .m_axis_cq_tlast ( m_axis_cq_tlast ), + .m_axis_cq_tkeep ( m_axis_cq_tkeep ), + .m_axis_cq_tuser ( m_axis_cq_tuser ), + .m_axis_cq_tdata ( m_axis_cq_tdata ), + .m_axis_cq_tready ( m_axis_cq_tready ), + + .s_axis_cc_tvalid ( s_axis_cc_tvalid ), + .s_axis_cc_tlast ( s_axis_cc_tlast ), + .s_axis_cc_tkeep ( s_axis_cc_tkeep ), + .s_axis_cc_tuser ( s_axis_cc_tuser ), + .s_axis_cc_tdata ( s_axis_cc_tdata ), + .s_axis_cc_tready ( s_axis_cc_tready ), + + .cfg_max_payload ( cfg_max_payload ), + .cfg_max_read_req ( cfg_max_read_req ), + .tl_cfg_busdev ( tl_cfg_busdev ), + + .cfg_interrupt_msix_enable ( cfg_interrupt_msix_enable ), + .cfg_interrupt_msix_mask ( cfg_interrupt_msix_mask ), + .cfg_interrupt_msix_data ( cfg_interrupt_msix_data ), + .cfg_interrupt_msix_address ( cfg_interrupt_msix_address ), + .cfg_interrupt_msix_int ( cfg_interrupt_msix_int ), + .cfg_interrupt_msix_sent ( cfg_interrupt_msix_sent ), + .cfg_interrupt_msix_fail ( cfg_interrupt_msix_fail ), + .cfg_interrupt_msi_function_number ( cfg_interrupt_msi_function_number ), + + .pio_hcr_in_param ( ceu_hcr_in_param ), + .pio_hcr_in_modifier ( ceu_hcr_in_modifier ), + .pio_hcr_out_dma_addr ( ceu_hcr_out_dma_addr ), + .pio_hcr_out_param ( ceu_hcr_out_param ), + .pio_hcr_token ( ceu_hcr_token ), + .pio_hcr_status ( ceu_hcr_status ), + .pio_hcr_go ( ceu_hcr_go ), + .pio_hcr_clear ( ceu_hcr_clear ), + .pio_hcr_event ( ceu_hcr_event ), + .pio_hcr_op_modifier ( ceu_hcr_op_modifier ), + .pio_hcr_op ( ceu_hcr_op ), + + .cmd_rst ( ), + + .pio_uar_db_valid ( db_fifo_wen ), + .pio_uar_db_data ( db_fifo_din ), + .pio_uar_db_ready ( !db_fifo_prog_full ), + + .cq_ren ( 'd0 ), + .cq_num ( 'd0 ), + .cq_dout ( ), + + .eq_ren ( 'd0 ), + .eq_num ( 'd0 ), + .eq_dout ( ), + + .pio_eq_int_req_valid ( 'd0 ), + .pio_eq_int_req_num ( 'd0 ), + .pio_eq_int_req_ready ( ), + + .pio_eq_int_rsp_valid ( ), + .pio_eq_int_rsp_data ( ), + .pio_eq_int_rsp_ready ( 'd0 ), + + .m_axi_awaddr ( ), + .m_axi_awvalid ( ), + .m_axi_awready ( 'd0 ), + + .m_axi_wdata ( ), + .m_axi_wstrb ( ), + .m_axi_wvalid ( ), + .m_axi_wready ( 'd0 ), + + .m_axi_bvalid ( 'd0 ), + .m_axi_bready ( ), + + .m_axi_araddr ( ), + .m_axi_arvalid ( ), + .m_axi_arready ( 'd0 ), + + .m_axi_rdata ( 'd0 ), + .m_axi_rvalid ( 'd0 ), + .m_axi_rready ( ), + + .dma_rd_req_valid ( DMA_RD_req_valid ), + .dma_rd_req_last ( DMA_RD_req_last ), + .dma_rd_req_data ( DMA_RD_req_data ), + .dma_rd_req_head ( DMA_RD_req_head ), + .dma_rd_req_ready ( DMA_RD_req_ready ), + + .dma_rd_rsp_valid ( DMA_RD_rsp_in_valid ), + .dma_rd_rsp_last ( DMA_RD_rsp_in_last ), + .dma_rd_rsp_data ( DMA_RD_rsp_in_data ), + .dma_rd_rsp_head ( DMA_RD_rsp_in_head ), + .dma_rd_rsp_ready ( DMA_RD_rsp_in_ready ), + + .dma_wr_req_valid ( DMA_WR_req_out_valid ), + .dma_wr_req_last ( DMA_WR_req_out_last ), + .dma_wr_req_data ( DMA_WR_req_out_data ), + .dma_wr_req_head ( DMA_WR_req_out_head ), + .dma_wr_req_ready ( DMA_WR_req_out_ready ), + + .p2p_upper_valid ( 'd0 ), + .p2p_upper_last ( 'd0 ), + .p2p_upper_data ( 'd0 ), + .p2p_upper_head ( 'd0 ), + .p2p_upper_ready ( ), + + .p2p_down_valid ( ), + .p2p_down_last ( ), + .p2p_down_data ( ), + .p2p_down_head ( ), + .p2p_down_ready ( 'd0 ) +); + +SyncFIFO_Template #( + .FIFO_TYPE ( 0 ), + .FIFO_WIDTH ( 64 ), + .FIFO_DEPTH ( 128 ) +) +DoorbellFIFO_Inst +( + .clk ( user_clk ), + .rst ( user_rst ), + + .wr_en ( db_fifo_wen ), + .din ( db_fifo_din ), + .prog_full ( db_fifo_prog_full ), + + .rd_en ( db_fifo_ren ), + .dout ( db_fifo_dout ), + .empty ( db_fifo_empty ) +); + +DMA_Channel_Top DMA_Channel_Top_Inst +( + .clk ( user_clk ), + .rst ( user_rst ), + + .CEU_dma_wr_req_in_valid ( CEU_dma_wr_req_in_valid ), + .CEU_dma_wr_req_in_head ( CEU_dma_wr_req_in_head ), + .CEU_dma_wr_req_in_data ( CEU_dma_wr_req_in_data ), + .CEU_dma_wr_req_in_last ( CEU_dma_wr_req_in_last ), + .CEU_dma_wr_req_in_ready ( CEU_dma_wr_req_in_ready ), + + .CEU_dma_wr_req_out_valid ( CEU_dma_wr_req_out_valid ), + .CEU_dma_wr_req_out_head ( CEU_dma_wr_req_out_head ), + .CEU_dma_wr_req_out_data ( CEU_dma_wr_req_out_data ), + .CEU_dma_wr_req_out_last ( CEU_dma_wr_req_out_last ), + .CEU_dma_wr_req_out_ready ( CEU_dma_wr_req_out_ready ), + + .QPC_dma_wr_req_in_valid ( QPC_dma_wr_req_in_valid ), + .QPC_dma_wr_req_in_head ( QPC_dma_wr_req_in_head ), + .QPC_dma_wr_req_in_data ( QPC_dma_wr_req_in_data ), + .QPC_dma_wr_req_in_last ( QPC_dma_wr_req_in_last ), + .QPC_dma_wr_req_in_ready ( QPC_dma_wr_req_in_ready ), + + .QPC_dma_wr_req_out_valid ( QPC_dma_wr_req_out_valid ), + .QPC_dma_wr_req_out_head ( QPC_dma_wr_req_out_head ), + .QPC_dma_wr_req_out_data ( QPC_dma_wr_req_out_data ), + .QPC_dma_wr_req_out_last ( QPC_dma_wr_req_out_last ), + .QPC_dma_wr_req_out_ready ( QPC_dma_wr_req_out_ready ), + + .CQC_dma_wr_req_in_valid ( CQC_dma_wr_req_in_valid ), + .CQC_dma_wr_req_in_head ( CQC_dma_wr_req_in_head ), + .CQC_dma_wr_req_in_data ( CQC_dma_wr_req_in_data ), + .CQC_dma_wr_req_in_last ( CQC_dma_wr_req_in_last ), + .CQC_dma_wr_req_in_ready ( CQC_dma_wr_req_in_ready ), + + .CQC_dma_wr_req_out_valid ( CQC_dma_wr_req_out_valid ), + .CQC_dma_wr_req_out_head ( CQC_dma_wr_req_out_head ), + .CQC_dma_wr_req_out_data ( CQC_dma_wr_req_out_data ), + .CQC_dma_wr_req_out_last ( CQC_dma_wr_req_out_last ), + .CQC_dma_wr_req_out_ready ( CQC_dma_wr_req_out_ready ), + + .EQC_dma_wr_req_in_valid ( EQC_dma_wr_req_in_valid ), + .EQC_dma_wr_req_in_head ( EQC_dma_wr_req_in_head ), + .EQC_dma_wr_req_in_data ( EQC_dma_wr_req_in_data ), + .EQC_dma_wr_req_in_last ( EQC_dma_wr_req_in_last ), + .EQC_dma_wr_req_in_ready ( EQC_dma_wr_req_in_ready ), + + .EQC_dma_wr_req_out_valid ( EQC_dma_wr_req_out_valid ), + .EQC_dma_wr_req_out_head ( EQC_dma_wr_req_out_head ), + .EQC_dma_wr_req_out_data ( EQC_dma_wr_req_out_data ), + .EQC_dma_wr_req_out_last ( EQC_dma_wr_req_out_last ), + .EQC_dma_wr_req_out_ready ( EQC_dma_wr_req_out_ready ), + + .MPT_dma_wr_req_in_valid ( MPT_dma_wr_req_in_valid ), + .MPT_dma_wr_req_in_head ( MPT_dma_wr_req_in_head ), + .MPT_dma_wr_req_in_data ( MPT_dma_wr_req_in_data ), + .MPT_dma_wr_req_in_last ( MPT_dma_wr_req_in_last ), + .MPT_dma_wr_req_in_ready ( MPT_dma_wr_req_in_ready ), + + .MPT_dma_wr_req_out_valid ( MPT_dma_wr_req_out_valid ), + .MPT_dma_wr_req_out_head ( MPT_dma_wr_req_out_head ), + .MPT_dma_wr_req_out_data ( MPT_dma_wr_req_out_data ), + .MPT_dma_wr_req_out_last ( MPT_dma_wr_req_out_last ), + .MPT_dma_wr_req_out_ready ( MPT_dma_wr_req_out_ready ), + + .MTT_dma_wr_req_in_valid ( MTT_dma_wr_req_in_valid ), + .MTT_dma_wr_req_in_head ( MTT_dma_wr_req_in_head ), + .MTT_dma_wr_req_in_data ( MTT_dma_wr_req_in_data ), + .MTT_dma_wr_req_in_last ( MTT_dma_wr_req_in_last ), + .MTT_dma_wr_req_in_ready ( MTT_dma_wr_req_in_ready ), + + .MTT_dma_wr_req_out_valid ( MTT_dma_wr_req_out_valid ), + .MTT_dma_wr_req_out_head ( MTT_dma_wr_req_out_head ), + .MTT_dma_wr_req_out_data ( MTT_dma_wr_req_out_data ), + .MTT_dma_wr_req_out_last ( MTT_dma_wr_req_out_last ), + .MTT_dma_wr_req_out_ready ( MTT_dma_wr_req_out_ready ), + + .TX_REQ_dma_wr_req_in_valid ( TX_REQ_dma_wr_req_in_valid ), + .TX_REQ_dma_wr_req_in_head ( TX_REQ_dma_wr_req_in_head ), + .TX_REQ_dma_wr_req_in_data ( TX_REQ_dma_wr_req_in_data ), + .TX_REQ_dma_wr_req_in_last ( TX_REQ_dma_wr_req_in_last ), + .TX_REQ_dma_wr_req_in_ready ( TX_REQ_dma_wr_req_in_ready ), + + .TX_REQ_dma_wr_req_out_valid ( TX_REQ_dma_wr_req_out_valid ), + .TX_REQ_dma_wr_req_out_head ( TX_REQ_dma_wr_req_out_head ), + .TX_REQ_dma_wr_req_out_data ( TX_REQ_dma_wr_req_out_data ), + .TX_REQ_dma_wr_req_out_last ( TX_REQ_dma_wr_req_out_last ), + .TX_REQ_dma_wr_req_out_ready ( TX_REQ_dma_wr_req_out_ready ), + + .RX_REQ_dma_wr_req_in_valid ( RX_REQ_dma_wr_req_in_valid ), + .RX_REQ_dma_wr_req_in_head ( RX_REQ_dma_wr_req_in_head ), + .RX_REQ_dma_wr_req_in_data ( RX_REQ_dma_wr_req_in_data ), + .RX_REQ_dma_wr_req_in_last ( RX_REQ_dma_wr_req_in_last ), + .RX_REQ_dma_wr_req_in_ready ( RX_REQ_dma_wr_req_in_ready ), + + .RX_REQ_dma_wr_req_out_valid ( RX_REQ_dma_wr_req_out_valid ), + .RX_REQ_dma_wr_req_out_head ( RX_REQ_dma_wr_req_out_head ), + .RX_REQ_dma_wr_req_out_data ( RX_REQ_dma_wr_req_out_data ), + .RX_REQ_dma_wr_req_out_last ( RX_REQ_dma_wr_req_out_last ), + .RX_REQ_dma_wr_req_out_ready ( RX_REQ_dma_wr_req_out_ready ), + + .RX_RESP_dma_wr_req_in_valid ( RX_RESP_dma_wr_req_in_valid ), + .RX_RESP_dma_wr_req_in_head ( RX_RESP_dma_wr_req_in_head ), + .RX_RESP_dma_wr_req_in_data ( RX_RESP_dma_wr_req_in_data ), + .RX_RESP_dma_wr_req_in_last ( RX_RESP_dma_wr_req_in_last ), + .RX_RESP_dma_wr_req_in_ready ( RX_RESP_dma_wr_req_in_ready ), + + .RX_RESP_dma_wr_req_out_valid ( RX_RESP_dma_wr_req_out_valid ), + .RX_RESP_dma_wr_req_out_head ( RX_RESP_dma_wr_req_out_head ), + .RX_RESP_dma_wr_req_out_data ( RX_RESP_dma_wr_req_out_data ), + .RX_RESP_dma_wr_req_out_last ( RX_RESP_dma_wr_req_out_last ), + .RX_RESP_dma_wr_req_out_ready ( RX_RESP_dma_wr_req_out_ready ), + + .CEU_dma_rd_rsp_in_valid ( CEU_dma_rd_rsp_in_valid ), + .CEU_dma_rd_rsp_in_head ( CEU_dma_rd_rsp_in_head ), + .CEU_dma_rd_rsp_in_data ( CEU_dma_rd_rsp_in_data ), + .CEU_dma_rd_rsp_in_last ( CEU_dma_rd_rsp_in_last ), + .CEU_dma_rd_rsp_in_ready ( CEU_dma_rd_rsp_in_ready ), + + .CEU_dma_rd_rsp_out_valid ( CEU_dma_rd_rsp_out_valid ), + .CEU_dma_rd_rsp_out_head ( CEU_dma_rd_rsp_out_head ), + .CEU_dma_rd_rsp_out_data ( CEU_dma_rd_rsp_out_data ), + .CEU_dma_rd_rsp_out_last ( CEU_dma_rd_rsp_out_last ), + .CEU_dma_rd_rsp_out_ready ( CEU_dma_rd_rsp_out_ready ), + + .SQ_dma_rd_rsp_in_valid ( SQ_dma_rd_rsp_in_valid ), + .SQ_dma_rd_rsp_in_head ( SQ_dma_rd_rsp_in_head ), + .SQ_dma_rd_rsp_in_data ( SQ_dma_rd_rsp_in_data ), + .SQ_dma_rd_rsp_in_last ( SQ_dma_rd_rsp_in_last ), + .SQ_dma_rd_rsp_in_ready ( SQ_dma_rd_rsp_in_ready ), + + .SQ_dma_rd_rsp_out_valid ( SQ_dma_rd_rsp_out_valid ), + .SQ_dma_rd_rsp_out_head ( SQ_dma_rd_rsp_out_head ), + .SQ_dma_rd_rsp_out_data ( SQ_dma_rd_rsp_out_data ), + .SQ_dma_rd_rsp_out_last ( SQ_dma_rd_rsp_out_last ), + .SQ_dma_rd_rsp_out_ready ( SQ_dma_rd_rsp_out_ready ), + + .RQ_dma_rd_rsp_in_valid ( RQ_dma_rd_rsp_in_valid ), + .RQ_dma_rd_rsp_in_head ( RQ_dma_rd_rsp_in_head ), + .RQ_dma_rd_rsp_in_data ( RQ_dma_rd_rsp_in_data ), + .RQ_dma_rd_rsp_in_last ( RQ_dma_rd_rsp_in_last ), + .RQ_dma_rd_rsp_in_ready ( RQ_dma_rd_rsp_in_ready ), + + .RQ_dma_rd_rsp_out_valid ( RQ_dma_rd_rsp_out_valid ), + .RQ_dma_rd_rsp_out_head ( RQ_dma_rd_rsp_out_head ), + .RQ_dma_rd_rsp_out_data ( RQ_dma_rd_rsp_out_data ), + .RQ_dma_rd_rsp_out_last ( RQ_dma_rd_rsp_out_last ), + .RQ_dma_rd_rsp_out_ready ( RQ_dma_rd_rsp_out_ready ), + + .QPC_dma_rd_rsp_in_valid ( QPC_dma_rd_rsp_in_valid ), + .QPC_dma_rd_rsp_in_head ( QPC_dma_rd_rsp_in_head ), + .QPC_dma_rd_rsp_in_data ( QPC_dma_rd_rsp_in_data ), + .QPC_dma_rd_rsp_in_last ( QPC_dma_rd_rsp_in_last ), + .QPC_dma_rd_rsp_in_ready ( QPC_dma_rd_rsp_in_ready ), + + .QPC_dma_rd_rsp_out_valid ( QPC_dma_rd_rsp_out_valid ), + .QPC_dma_rd_rsp_out_head ( QPC_dma_rd_rsp_out_head ), + .QPC_dma_rd_rsp_out_data ( QPC_dma_rd_rsp_out_data ), + .QPC_dma_rd_rsp_out_last ( QPC_dma_rd_rsp_out_last ), + .QPC_dma_rd_rsp_out_ready ( QPC_dma_rd_rsp_out_ready ), + + .CQC_dma_rd_rsp_in_valid ( CQC_dma_rd_rsp_in_valid ), + .CQC_dma_rd_rsp_in_head ( CQC_dma_rd_rsp_in_head ), + .CQC_dma_rd_rsp_in_data ( CQC_dma_rd_rsp_in_data ), + .CQC_dma_rd_rsp_in_last ( CQC_dma_rd_rsp_in_last ), + .CQC_dma_rd_rsp_in_ready ( CQC_dma_rd_rsp_in_ready ), + + .CQC_dma_rd_rsp_out_valid ( CQC_dma_rd_rsp_out_valid ), + .CQC_dma_rd_rsp_out_head ( CQC_dma_rd_rsp_out_head ), + .CQC_dma_rd_rsp_out_data ( CQC_dma_rd_rsp_out_data ), + .CQC_dma_rd_rsp_out_last ( CQC_dma_rd_rsp_out_last ), + .CQC_dma_rd_rsp_out_ready ( CQC_dma_rd_rsp_out_ready ), + + .EQC_dma_rd_rsp_in_valid ( EQC_dma_rd_rsp_in_valid ), + .EQC_dma_rd_rsp_in_head ( EQC_dma_rd_rsp_in_head ), + .EQC_dma_rd_rsp_in_data ( EQC_dma_rd_rsp_in_data ), + .EQC_dma_rd_rsp_in_last ( EQC_dma_rd_rsp_in_last ), + .EQC_dma_rd_rsp_in_ready ( EQC_dma_rd_rsp_in_ready ), + + .EQC_dma_rd_rsp_out_valid ( EQC_dma_rd_rsp_out_valid ), + .EQC_dma_rd_rsp_out_head ( EQC_dma_rd_rsp_out_head ), + .EQC_dma_rd_rsp_out_data ( EQC_dma_rd_rsp_out_data ), + .EQC_dma_rd_rsp_out_last ( EQC_dma_rd_rsp_out_last ), + .EQC_dma_rd_rsp_out_ready ( EQC_dma_rd_rsp_out_ready ), + + .MPT_dma_rd_rsp_in_valid ( MPT_dma_rd_rsp_in_valid ), + .MPT_dma_rd_rsp_in_head ( MPT_dma_rd_rsp_in_head ), + .MPT_dma_rd_rsp_in_data ( MPT_dma_rd_rsp_in_data ), + .MPT_dma_rd_rsp_in_last ( MPT_dma_rd_rsp_in_last ), + .MPT_dma_rd_rsp_in_ready ( MPT_dma_rd_rsp_in_ready ), + + .MPT_dma_rd_rsp_out_valid ( MPT_dma_rd_rsp_out_valid ), + .MPT_dma_rd_rsp_out_head ( MPT_dma_rd_rsp_out_head ), + .MPT_dma_rd_rsp_out_data ( MPT_dma_rd_rsp_out_data ), + .MPT_dma_rd_rsp_out_last ( MPT_dma_rd_rsp_out_last ), + .MPT_dma_rd_rsp_out_ready ( MPT_dma_rd_rsp_out_ready ), + + .MTT_dma_rd_rsp_in_valid ( MTT_dma_rd_rsp_in_valid ), + .MTT_dma_rd_rsp_in_head ( MTT_dma_rd_rsp_in_head ), + .MTT_dma_rd_rsp_in_data ( MTT_dma_rd_rsp_in_data ), + .MTT_dma_rd_rsp_in_last ( MTT_dma_rd_rsp_in_last ), + .MTT_dma_rd_rsp_in_ready ( MTT_dma_rd_rsp_in_ready ), + + .MTT_dma_rd_rsp_out_valid ( MTT_dma_rd_rsp_out_valid ), + .MTT_dma_rd_rsp_out_head ( MTT_dma_rd_rsp_out_head ), + .MTT_dma_rd_rsp_out_data ( MTT_dma_rd_rsp_out_data ), + .MTT_dma_rd_rsp_out_last ( MTT_dma_rd_rsp_out_last ), + .MTT_dma_rd_rsp_out_ready ( MTT_dma_rd_rsp_out_ready ), + + .TX_REQ_dma_rd_rsp_in_valid ( TX_REQ_dma_rd_rsp_in_valid ), + .TX_REQ_dma_rd_rsp_in_head ( TX_REQ_dma_rd_rsp_in_head ), + .TX_REQ_dma_rd_rsp_in_data ( TX_REQ_dma_rd_rsp_in_data ), + .TX_REQ_dma_rd_rsp_in_last ( TX_REQ_dma_rd_rsp_in_last ), + .TX_REQ_dma_rd_rsp_in_ready ( TX_REQ_dma_rd_rsp_in_ready ), + + .TX_REQ_dma_rd_rsp_out_valid ( TX_REQ_dma_rd_rsp_out_valid ), + .TX_REQ_dma_rd_rsp_out_head ( TX_REQ_dma_rd_rsp_out_head ), + .TX_REQ_dma_rd_rsp_out_data ( TX_REQ_dma_rd_rsp_out_data ), + .TX_REQ_dma_rd_rsp_out_last ( TX_REQ_dma_rd_rsp_out_last ), + .TX_REQ_dma_rd_rsp_out_ready ( TX_REQ_dma_rd_rsp_out_ready ), + + .TX_RESP_dma_rd_rsp_in_valid ( TX_RESP_dma_rd_rsp_in_valid ), + .TX_RESP_dma_rd_rsp_in_head ( TX_RESP_dma_rd_rsp_in_head ), + .TX_RESP_dma_rd_rsp_in_data ( TX_RESP_dma_rd_rsp_in_data ), + .TX_RESP_dma_rd_rsp_in_last ( TX_RESP_dma_rd_rsp_in_last ), + .TX_RESP_dma_rd_rsp_in_ready ( TX_RESP_dma_rd_rsp_in_ready ), + + .TX_RESP_dma_rd_rsp_out_valid ( TX_RESP_dma_rd_rsp_out_valid ), + .TX_RESP_dma_rd_rsp_out_head ( TX_RESP_dma_rd_rsp_out_head ), + .TX_RESP_dma_rd_rsp_out_data ( TX_RESP_dma_rd_rsp_out_data ), + .TX_RESP_dma_rd_rsp_out_last ( TX_RESP_dma_rd_rsp_out_last ), + .TX_RESP_dma_rd_rsp_out_ready ( TX_RESP_dma_rd_rsp_out_ready ) +); +/*------------------------------------------- Submodules Instatiation : End -----------------------------------------*/ + + +/*------------------------------------------- State Machine Definition : Begin --------------------------------------*/ +/*------------------------------------------- State Machine Definition : End ----------------------------------------*/ + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ +assign DMA_RD_req_valid = { TX_RESP_dma_rd_req_valid, + TX_REQ_dma_rd_req_valid, + MTT_dma_rd_req_valid, + MPT_dma_rd_req_valid, + EQC_dma_rd_req_valid, + CQC_dma_rd_req_valid, + QPC_dma_rd_req_valid, + RQ_dma_rd_req_valid, + SQ_dma_rd_req_valid, + CEU_dma_rd_req_valid + }; + +assign DMA_RD_req_head = { TX_RESP_dma_rd_req_head, + TX_REQ_dma_rd_req_head, + MTT_dma_rd_req_head, + MPT_dma_rd_req_head, + EQC_dma_rd_req_head, + CQC_dma_rd_req_head, + QPC_dma_rd_req_head, + RQ_dma_rd_req_head, + SQ_dma_rd_req_head, + CEU_dma_rd_req_head + }; + +assign DMA_RD_req_last = { TX_RESP_dma_rd_req_last, + TX_REQ_dma_rd_req_last, + MTT_dma_rd_req_last, + MPT_dma_rd_req_last, + EQC_dma_rd_req_last, + CQC_dma_rd_req_last, + QPC_dma_rd_req_last, + RQ_dma_rd_req_last, + SQ_dma_rd_req_last, + CEU_dma_rd_req_last + }; + +assign DMA_RD_req_data = { 256'd0, + 256'd0, + 256'd0, + 256'd0, + 256'd0, + 256'd0, + 256'd0, + 256'd0, + 256'd0, + 256'd0 + }; + +assign TX_RESP_dma_rd_req_ready = DMA_RD_req_ready[9]; +assign TX_REQ_dma_rd_req_ready = DMA_RD_req_ready[8]; +assign MTT_dma_rd_req_ready = DMA_RD_req_ready[7]; +assign MPT_dma_rd_req_ready = DMA_RD_req_ready[6]; +assign EQC_dma_rd_req_ready = DMA_RD_req_ready[5]; +assign CQC_dma_rd_req_ready = DMA_RD_req_ready[4]; +assign QPC_dma_rd_req_ready = DMA_RD_req_ready[3]; +assign RQ_dma_rd_req_ready = DMA_RD_req_ready[2]; +assign SQ_dma_rd_req_ready = DMA_RD_req_ready[1]; +assign CEU_dma_rd_req_ready = DMA_RD_req_ready[0]; + +assign TX_RESP_dma_rd_rsp_in_valid = DMA_RD_rsp_in_valid[9]; +assign TX_REQ_dma_rd_rsp_in_valid = DMA_RD_rsp_in_valid[8]; +assign MTT_dma_rd_rsp_in_valid = DMA_RD_rsp_in_valid[7]; +assign MPT_dma_rd_rsp_in_valid = DMA_RD_rsp_in_valid[6]; +assign EQC_dma_rd_rsp_in_valid = DMA_RD_rsp_in_valid[5]; +assign CQC_dma_rd_rsp_in_valid = DMA_RD_rsp_in_valid[4]; +assign QPC_dma_rd_rsp_in_valid = DMA_RD_rsp_in_valid[3]; +assign RQ_dma_rd_rsp_in_valid = DMA_RD_rsp_in_valid[2]; +assign SQ_dma_rd_rsp_in_valid = DMA_RD_rsp_in_valid[1]; +assign CEU_dma_rd_rsp_in_valid = DMA_RD_rsp_in_valid[0]; + +assign TX_RESP_dma_rd_rsp_in_head = DMA_RD_rsp_in_head[10 * `DMA_HEAD_WIDTH - 1 : 9 * `DMA_HEAD_WIDTH]; +assign TX_REQ_dma_rd_rsp_in_head = DMA_RD_rsp_in_head[9 * `DMA_HEAD_WIDTH - 1 : 8 * `DMA_HEAD_WIDTH]; +assign MTT_dma_rd_rsp_in_head = DMA_RD_rsp_in_head[8 * `DMA_HEAD_WIDTH - 1 : 7 * `DMA_HEAD_WIDTH]; +assign MPT_dma_rd_rsp_in_head = DMA_RD_rsp_in_head[7 * `DMA_HEAD_WIDTH - 1 : 6 * `DMA_HEAD_WIDTH]; +assign EQC_dma_rd_rsp_in_head = DMA_RD_rsp_in_head[6 * `DMA_HEAD_WIDTH - 1 : 5 * `DMA_HEAD_WIDTH]; +assign CQC_dma_rd_rsp_in_head = DMA_RD_rsp_in_head[5 * `DMA_HEAD_WIDTH - 1 : 4 * `DMA_HEAD_WIDTH]; +assign QPC_dma_rd_rsp_in_head = DMA_RD_rsp_in_head[4 * `DMA_HEAD_WIDTH - 1 : 3 * `DMA_HEAD_WIDTH]; +assign RQ_dma_rd_rsp_in_head = DMA_RD_rsp_in_head[3 * `DMA_HEAD_WIDTH - 1 : 2 * `DMA_HEAD_WIDTH]; +assign SQ_dma_rd_rsp_in_head = DMA_RD_rsp_in_head[2 * `DMA_HEAD_WIDTH - 1 : 1 * `DMA_HEAD_WIDTH]; +assign CEU_dma_rd_rsp_in_head = DMA_RD_rsp_in_head[1 * `DMA_HEAD_WIDTH - 1 : 0 * `DMA_HEAD_WIDTH]; + +assign TX_RESP_dma_rd_rsp_in_data = DMA_RD_rsp_in_data[10 * 256 - 1 : 9 * 256]; +assign TX_REQ_dma_rd_rsp_in_data = DMA_RD_rsp_in_data[9 * 256 - 1 : 8 * 256]; +assign MTT_dma_rd_rsp_in_data = DMA_RD_rsp_in_data[8 * 256 - 1 : 7 * 256]; +assign MPT_dma_rd_rsp_in_data = DMA_RD_rsp_in_data[7 * 256 - 1 : 6 * 256]; +assign EQC_dma_rd_rsp_in_data = DMA_RD_rsp_in_data[6 * 256 - 1 : 5 * 256]; +assign CQC_dma_rd_rsp_in_data = DMA_RD_rsp_in_data[5 * 256 - 1 : 4 * 256]; +assign QPC_dma_rd_rsp_in_data = DMA_RD_rsp_in_data[4 * 256 - 1 : 3 * 256]; +assign RQ_dma_rd_rsp_in_data = DMA_RD_rsp_in_data[3 * 256 - 1 : 2 * 256]; +assign SQ_dma_rd_rsp_in_data = DMA_RD_rsp_in_data[2 * 256 - 1 : 1 * 256]; +assign CEU_dma_rd_rsp_in_data = DMA_RD_rsp_in_data[1 * 256 - 1 : 0 * 256]; + +assign TX_RESP_dma_rd_rsp_in_last = DMA_RD_rsp_in_last[9]; +assign TX_REQ_dma_rd_rsp_in_last = DMA_RD_rsp_in_last[8]; +assign MTT_dma_rd_rsp_in_last = DMA_RD_rsp_in_last[7]; +assign MPT_dma_rd_rsp_in_last = DMA_RD_rsp_in_last[6]; +assign EQC_dma_rd_rsp_in_last = DMA_RD_rsp_in_last[5]; +assign CQC_dma_rd_rsp_in_last = DMA_RD_rsp_in_last[4]; +assign QPC_dma_rd_rsp_in_last = DMA_RD_rsp_in_last[3]; +assign RQ_dma_rd_rsp_in_last = DMA_RD_rsp_in_last[2]; +assign SQ_dma_rd_rsp_in_last = DMA_RD_rsp_in_last[1]; +assign CEU_dma_rd_rsp_in_last = DMA_RD_rsp_in_last[0]; + +assign DMA_RD_rsp_in_ready = { TX_RESP_dma_rd_rsp_in_ready, + TX_REQ_dma_rd_rsp_in_ready, + MTT_dma_rd_rsp_in_ready, + MPT_dma_rd_rsp_in_ready, + EQC_dma_rd_rsp_in_ready, + CQC_dma_rd_rsp_in_ready, + QPC_dma_rd_rsp_in_ready, + RQ_dma_rd_rsp_in_ready, + SQ_dma_rd_rsp_in_ready, + CEU_dma_rd_rsp_in_ready + }; + + +assign DMA_WR_req_out_valid = { + RX_RESP_dma_wr_req_out_valid, + RX_REQ_dma_wr_req_out_valid, + TX_REQ_dma_wr_req_out_valid, + MTT_dma_wr_req_out_valid, + MPT_dma_wr_req_out_valid, + EQC_dma_wr_req_out_valid, + CQC_dma_wr_req_out_valid, + QPC_dma_wr_req_out_valid, + CEU_dma_wr_req_out_valid + }; + +assign DMA_WR_req_out_head = { + RX_RESP_dma_wr_req_out_head, + RX_REQ_dma_wr_req_out_head, + TX_REQ_dma_wr_req_out_head, + MTT_dma_wr_req_out_head, + MPT_dma_wr_req_out_head, + EQC_dma_wr_req_out_head, + CQC_dma_wr_req_out_head, + QPC_dma_wr_req_out_head, + CEU_dma_wr_req_out_head + }; + +assign DMA_WR_req_out_data = { + RX_RESP_dma_wr_req_out_data, + RX_REQ_dma_wr_req_out_data, + TX_REQ_dma_wr_req_out_data, + MTT_dma_wr_req_out_data, + MPT_dma_wr_req_out_data, + EQC_dma_wr_req_out_data, + CQC_dma_wr_req_out_data, + QPC_dma_wr_req_out_data, + CEU_dma_wr_req_out_data + }; + +assign DMA_WR_req_out_last = { + RX_RESP_dma_wr_req_out_last, + RX_REQ_dma_wr_req_out_last, + TX_REQ_dma_wr_req_out_last, + MTT_dma_wr_req_out_last, + MPT_dma_wr_req_out_last, + EQC_dma_wr_req_out_last, + CQC_dma_wr_req_out_last, + QPC_dma_wr_req_out_last, + CEU_dma_wr_req_out_last + }; + + assign RX_RESP_dma_wr_req_out_ready = DMA_WR_req_out_ready[8]; + assign RX_REQ_dma_wr_req_out_ready = DMA_WR_req_out_ready[7]; + assign TX_REQ_dma_wr_req_out_ready = DMA_WR_req_out_ready[6]; + assign MTT_dma_wr_req_out_ready = DMA_WR_req_out_ready[5]; + assign MPT_dma_wr_req_out_ready = DMA_WR_req_out_ready[4]; + assign EQC_dma_wr_req_out_ready = DMA_WR_req_out_ready[3]; + assign CQC_dma_wr_req_out_ready = DMA_WR_req_out_ready[2]; + assign QPC_dma_wr_req_out_ready = DMA_WR_req_out_ready[1]; + assign CEU_dma_wr_req_out_ready = DMA_WR_req_out_ready[0]; +/*------------------------------------------- Variables Decode : End ------------------------------------------------*/ + +`ifdef ILA_ON +// ila_dma CEU_dma_rd_req ( +// .clk(user_clk), + +// .probe0(CEU_dma_rd_req_valid), +// .probe1(CEU_dma_rd_req_head), +// .probe2(CEU_dma_rd_req_data), +// .probe3(CEU_dma_rd_req_last), +// .probe4(CEU_dma_rd_req_ready) +// ); + +// ila_dma CEU_dma_rd_rsp ( +// .clk(user_clk), + +// .probe0(CEU_dma_rd_rsp_in_valid), +// .probe1(CEU_dma_rd_rsp_in_head), +// .probe2(CEU_dma_rd_rsp_in_data), +// .probe3(CEU_dma_rd_rsp_in_last), +// .probe4(CEU_dma_rd_rsp_in_ready) +// ); + + +// ila_dma TX_REQ_dma_rd_req ( +// .clk(user_clk), + +// .probe0(TX_REQ_dma_rd_req_valid), +// .probe1(TX_REQ_dma_rd_req_head), +// .probe2(TX_REQ_dma_rd_req_data), +// .probe3(TX_REQ_dma_rd_req_last), +// .probe4(TX_REQ_dma_rd_req_ready) +// ); + +// ila_dma TX_REQ_dma_rd_rsp ( +// .clk(user_clk), + +// .probe0(TX_REQ_dma_rd_rsp_in_valid), +// .probe1(TX_REQ_dma_rd_rsp_in_head), +// .probe2(TX_REQ_dma_rd_rsp_in_data), +// .probe3(TX_REQ_dma_rd_rsp_in_last), +// .probe4(TX_REQ_dma_rd_rsp_in_ready) +// ); + +// ila_mac ila_mac_tx_inst( +// .clk(mac_tx_clk), + +// .probe0(mac_tx_valid), +// .probe1(mac_tx_ready), +// .probe2(mac_tx_start), +// .probe3(mac_tx_last), +// .probe4(mac_tx_keep), +// .probe5(mac_tx_data) +// ); + +// ila_mac ila_mac_rx_inst( +// .clk(mac_rx_clk), + +// .probe0(mac_rx_valid), +// .probe1(mac_rx_ready), +// .probe2(mac_rx_start), +// .probe3(mac_rx_last), +// .probe4(mac_rx_keep), +// .probe5(mac_rx_data) +// ); + +// ila_dma qpc_dma_wr_req ( +// .clk(user_clk), + +// .probe0(QPC_dma_wr_req_out_valid), +// .probe1(QPC_dma_wr_req_out_head), +// .probe2(QPC_dma_wr_req_out_data), +// .probe3(QPC_dma_wr_req_out_last), +// .probe4(QPC_dma_wr_req_out_ready) +// ); +`endif + +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Top/ProtocolEngine_Top.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Top/ProtocolEngine_Top.v new file mode 100644 index 0000000000000000000000000000000000000000..be05b57201116ab70b5953de76a539abdca7ff4e --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/Top/ProtocolEngine_Top.v @@ -0,0 +1,1337 @@ +/*------------------------------------------- Module Description : Begin ---------------------------------------------- +Name: ProtocolEngine_Top +Author: YangFan +Function: Integrate RPCSubsystem, QueueSubsystem, TransportSubsystem and ResMgtSubsystem. +--------------------------------------------- Module Decription : End -----------------------------------------------*/ + +/*------------------------------------------- Timescale Definition : Begin ------------------------------------------*/ +`timescale 1ns / 1ps +/*------------------------------------------- Timescale Definition : End --------------------------------------------*/ + +/*------------------------------------------- Included Files : Begin ------------------------------------------------*/ +`include "protocol_engine_def.vh" +/*------------------------------------------- Included Files : End --------------------------------------------------*/ + +/*------------------------------------------- Local Macros Definition : Begin ---------------------------------------*/ +/*------------------------------------------- Local Macros Definition : End -----------------------------------------*/ + +/*------------------------------------------- Input/Output Definition : Begin ---------------------------------------*/ +module ProtocolEngine_Top +#( + parameter INGRESS_CXT_HEAD_WIDTH = 128, + parameter INGRESS_CXT_DATA_WIDTH = 256, + parameter EGRESS_CXT_HEAD_WIDTH = 128, + parameter EGRESS_CXT_DATA_WIDTH = 256, + + parameter INGRESS_MR_HEAD_WIDTH = 128, + parameter INGRESS_MR_DATA_WIDTH = 256, + parameter EGRESS_MR_HEAD_WIDTH = 128, + parameter EGRESS_MR_DATA_WIDTH = 256 +) +( + input wire user_clk, + input wire user_rst, + + input wire mac_tx_clk, + input wire mac_tx_rst, + + input wire mac_rx_clk, + input wire mac_rx_rst, + +//Control Path Interface + input wire [63:0] ceu_hcr_in_param, + input wire [31:0] ceu_hcr_in_modifier, + input wire [63:0] ceu_hcr_out_dma_addr, + input wire [31:0] ceu_hcr_token, + input wire ceu_hcr_go, + input wire ceu_hcr_event, + input wire [7:0] ceu_hcr_op_modifier, + input wire [11:0] ceu_hcr_op, + + output wire [63:0] ceu_hcr_out_param, + output wire [7:0] ceu_hcr_status, + output wire ceu_hcr_clear, + + output wire CEU_dma_rd_req_valid, + output wire CEU_dma_rd_req_last, + output wire [`DMA_HEAD_WIDTH - 1 : 0] CEU_dma_rd_req_head, + output wire [`DMA_DATA_WIDTH - 1 : 0] CEU_dma_rd_req_data, + input wire CEU_dma_rd_req_ready, + + input wire CEU_dma_rd_rsp_valid, + input wire CEU_dma_rd_rsp_last, + input wire [`DMA_HEAD_WIDTH - 1 : 0] CEU_dma_rd_rsp_head, + input wire [`DMA_DATA_WIDTH - 1 : 0] CEU_dma_rd_rsp_data, + output wire CEU_dma_rd_rsp_ready, + + output wire CEU_dma_wr_req_valid, + output wire CEU_dma_wr_req_last, + output wire [`DMA_HEAD_WIDTH - 1 : 0] CEU_dma_wr_req_head, + output wire [`DMA_DATA_WIDTH - 1 : 0] CEU_dma_wr_req_data, + input wire CEU_dma_wr_req_ready, + +//Data Path Interface + + input wire db_fifo_empty, + input wire [63:0] db_fifo_dout, + output wire db_fifo_rd_en, + + output wire QPC_dma_rd_req_valid, + output wire [`DMA_HEAD_WIDTH - 1 : 0] QPC_dma_rd_req_head, + output wire [`DMA_DATA_WIDTH - 1 : 0] QPC_dma_rd_req_data, + output wire QPC_dma_rd_req_last, + input wire QPC_dma_rd_req_ready, + + input wire QPC_dma_rd_rsp_valid, + input wire [`DMA_HEAD_WIDTH - 1 : 0] QPC_dma_rd_rsp_head, + input wire [`DMA_DATA_WIDTH - 1 : 0] QPC_dma_rd_rsp_data, + input wire QPC_dma_rd_rsp_last, + output wire QPC_dma_rd_rsp_ready, + + output wire QPC_dma_wr_req_valid, + output wire [`DMA_HEAD_WIDTH - 1 : 0] QPC_dma_wr_req_head, + output wire [`DMA_DATA_WIDTH - 1 : 0] QPC_dma_wr_req_data, + output wire QPC_dma_wr_req_last, + input wire QPC_dma_wr_req_ready, + + output wire CQC_dma_rd_req_valid, + output wire [`DMA_HEAD_WIDTH - 1 : 0] CQC_dma_rd_req_head, + output wire [`DMA_DATA_WIDTH - 1 : 0] CQC_dma_rd_req_data, + output wire CQC_dma_rd_req_last, + input wire CQC_dma_rd_req_ready, + + input wire CQC_dma_rd_rsp_valid, + input wire [`DMA_HEAD_WIDTH - 1 : 0] CQC_dma_rd_rsp_head, + input wire [`DMA_DATA_WIDTH - 1 : 0] CQC_dma_rd_rsp_data, + input wire CQC_dma_rd_rsp_last, + output wire CQC_dma_rd_rsp_ready, + + output wire CQC_dma_wr_req_valid, + output wire [`DMA_HEAD_WIDTH - 1 : 0] CQC_dma_wr_req_head, + output wire [`DMA_DATA_WIDTH - 1 : 0] CQC_dma_wr_req_data, + output wire CQC_dma_wr_req_last, + input wire CQC_dma_wr_req_ready, + + output wire EQC_dma_rd_req_valid, + output wire [`DMA_HEAD_WIDTH - 1 : 0] EQC_dma_rd_req_head, + output wire [`DMA_DATA_WIDTH - 1 : 0] EQC_dma_rd_req_data, + output wire EQC_dma_rd_req_last, + input wire EQC_dma_rd_req_ready, + + input wire EQC_dma_rd_rsp_valid, + input wire [`DMA_HEAD_WIDTH - 1 : 0] EQC_dma_rd_rsp_head, + input wire [`DMA_DATA_WIDTH - 1 : 0] EQC_dma_rd_rsp_data, + input wire EQC_dma_rd_rsp_last, + output wire EQC_dma_rd_rsp_ready, + + output wire EQC_dma_wr_req_valid, + output wire [`DMA_HEAD_WIDTH - 1 : 0] EQC_dma_wr_req_head, + output wire [`DMA_DATA_WIDTH - 1 : 0] EQC_dma_wr_req_data, + output wire EQC_dma_wr_req_last, + input wire EQC_dma_wr_req_ready, + + output wire MPT_dma_rd_req_valid, + output wire [`DMA_HEAD_WIDTH - 1 : 0] MPT_dma_rd_req_head, + output wire [`DMA_DATA_WIDTH - 1 : 0] MPT_dma_rd_req_data, + output wire MPT_dma_rd_req_last, + input wire MPT_dma_rd_req_ready, + + input wire MPT_dma_rd_rsp_valid, + input wire [`DMA_HEAD_WIDTH - 1 : 0] MPT_dma_rd_rsp_head, + input wire [`DMA_DATA_WIDTH - 1 : 0] MPT_dma_rd_rsp_data, + input wire MPT_dma_rd_rsp_last, + output wire MPT_dma_rd_rsp_ready, + + output wire MPT_dma_wr_req_valid, + output wire [`DMA_HEAD_WIDTH - 1 : 0] MPT_dma_wr_req_head, + output wire [`DMA_DATA_WIDTH - 1 : 0] MPT_dma_wr_req_data, + output wire MPT_dma_wr_req_last, + input wire MPT_dma_wr_req_ready, + + output wire MTT_dma_rd_req_valid, + output wire [`DMA_HEAD_WIDTH - 1 : 0] MTT_dma_rd_req_head, + output wire [`DMA_DATA_WIDTH - 1 : 0] MTT_dma_rd_req_data, + output wire MTT_dma_rd_req_last, + input wire MTT_dma_rd_req_ready, + + input wire MTT_dma_rd_rsp_valid, + input wire [`DMA_HEAD_WIDTH - 1 : 0] MTT_dma_rd_rsp_head, + input wire [`DMA_DATA_WIDTH - 1 : 0] MTT_dma_rd_rsp_data, + input wire MTT_dma_rd_rsp_last, + output wire MTT_dma_rd_rsp_ready, + + output wire MTT_dma_wr_req_valid, + output wire [`DMA_HEAD_WIDTH - 1 : 0] MTT_dma_wr_req_head, + output wire [`DMA_DATA_WIDTH - 1 : 0] MTT_dma_wr_req_data, + output wire MTT_dma_wr_req_last, + input wire MTT_dma_wr_req_ready, + + output wire SQ_dma_rd_req_valid, + output wire [`DMA_HEAD_WIDTH - 1 : 0] SQ_dma_rd_req_head, + output wire [`DMA_DATA_WIDTH - 1 : 0] SQ_dma_rd_req_data, + output wire SQ_dma_rd_req_last, + input wire SQ_dma_rd_req_ready, + + input wire SQ_dma_rd_rsp_valid, + input wire [`DMA_HEAD_WIDTH - 1 : 0] SQ_dma_rd_rsp_head, + input wire [`DMA_DATA_WIDTH - 1 : 0] SQ_dma_rd_rsp_data, + input wire SQ_dma_rd_rsp_last, + output wire SQ_dma_rd_rsp_ready, + + output wire RQ_dma_rd_req_valid, + output wire [`DMA_HEAD_WIDTH - 1 : 0] RQ_dma_rd_req_head, + output wire [`DMA_DATA_WIDTH - 1 : 0] RQ_dma_rd_req_data, + output wire RQ_dma_rd_req_last, + input wire RQ_dma_rd_req_ready, + + input wire RQ_dma_rd_rsp_valid, + input wire [`DMA_HEAD_WIDTH - 1 : 0] RQ_dma_rd_rsp_head, + input wire [`DMA_DATA_WIDTH - 1 : 0] RQ_dma_rd_rsp_data, + input wire RQ_dma_rd_rsp_last, + output wire RQ_dma_rd_rsp_ready, + + output wire TX_REQ_dma_wr_req_valid, + output wire TX_REQ_dma_wr_req_last, + output wire [`DMA_HEAD_WIDTH - 1 : 0] TX_REQ_dma_wr_req_head, + output wire [`DMA_DATA_WIDTH - 1 : 0] TX_REQ_dma_wr_req_data, + input wire TX_REQ_dma_wr_req_ready, + + output wire RX_REQ_dma_wr_req_valid, + output wire RX_REQ_dma_wr_req_last, + output wire [`DMA_HEAD_WIDTH - 1 : 0] RX_REQ_dma_wr_req_head, + output wire [`DMA_DATA_WIDTH - 1 : 0] RX_REQ_dma_wr_req_data, + input wire RX_REQ_dma_wr_req_ready, + + output wire RX_RESP_dma_wr_req_valid, + output wire RX_RESP_dma_wr_req_last, + output wire [`DMA_HEAD_WIDTH - 1 : 0] RX_RESP_dma_wr_req_head, + output wire [`DMA_DATA_WIDTH - 1 : 0] RX_RESP_dma_wr_req_data, + input wire RX_RESP_dma_wr_req_ready, + + output wire TX_REQ_dma_rd_req_valid, + output wire [`DMA_HEAD_WIDTH - 1 : 0] TX_REQ_dma_rd_req_head, + output wire [`DMA_DATA_WIDTH - 1 : 0] TX_REQ_dma_rd_req_data, + output wire TX_REQ_dma_rd_req_last, + input wire TX_REQ_dma_rd_req_ready, + + input wire TX_REQ_dma_rd_rsp_valid, + input wire [`DMA_HEAD_WIDTH - 1 : 0] TX_REQ_dma_rd_rsp_head, + input wire [`DMA_DATA_WIDTH - 1 : 0] TX_REQ_dma_rd_rsp_data, + input wire TX_REQ_dma_rd_rsp_last, + output wire TX_REQ_dma_rd_rsp_ready, + + output wire TX_RESP_dma_rd_req_valid, + output wire [`DMA_HEAD_WIDTH - 1 : 0] TX_RESP_dma_rd_req_head, + output wire [`DMA_DATA_WIDTH - 1 : 0] TX_RESP_dma_rd_req_data, + output wire TX_RESP_dma_rd_req_last, + input wire TX_RESP_dma_rd_req_ready, + + input wire TX_RESP_dma_rd_rsp_valid, + input wire [`DMA_HEAD_WIDTH - 1 : 0] TX_RESP_dma_rd_rsp_head, + input wire [`DMA_DATA_WIDTH - 1 : 0] TX_RESP_dma_rd_rsp_data, + input wire TX_RESP_dma_rd_rsp_last, + output wire TX_RESP_dma_rd_rsp_ready, + +//Interface with MAC + output wire mac_tx_valid, + input wire mac_tx_ready, + output wire mac_tx_start, + output wire mac_tx_last, + output wire [`MAC_KEEP_WIDTH - 1 : 0] mac_tx_keep, + output wire mac_tx_user, + output wire [`MAC_DATA_WIDTH - 1 : 0] mac_tx_data, + + input wire mac_rx_valid, + output wire mac_rx_ready, + input wire mac_rx_start, + input wire mac_rx_last, + input wire [`MAC_KEEP_WIDTH - 1 : 0] mac_rx_keep, + input wire mac_rx_user, + input wire [`MAC_DATA_WIDTH - 1 : 0] mac_rx_data +); + +/*------------------------------------------- Input/Output Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Variables Definition : Begin ------------------------------------*/ +wire SQ_fetch_cxt_ingress_valid; +wire [`SQ_OOO_CXT_INGRESS_HEAD_WIDTH - 1 : 0] SQ_fetch_cxt_ingress_head; +wire [`SQ_OOO_CXT_INGRESS_DATA_WIDTH - 1 : 0] SQ_fetch_cxt_ingress_data; +wire SQ_fetch_cxt_ingress_start; +wire SQ_fetch_cxt_ingress_last; +wire SQ_fetch_cxt_ingress_ready; + +wire SQ_fetch_cxt_egress_valid; +wire [`SQ_OOO_CXT_EGRESS_HEAD_WIDTH - 1 : 0] SQ_fetch_cxt_egress_head; +wire [`SQ_OOO_CXT_EGRESS_DATA_WIDTH - 1 : 0] SQ_fetch_cxt_egress_data; +wire SQ_fetch_cxt_egress_start; +wire SQ_fetch_cxt_egress_last; +wire SQ_fetch_cxt_egress_ready; + +wire TX_REQ_fetch_cxt_ingress_valid; +wire [`TX_REQ_OOO_CXT_INGRESS_HEAD_WIDTH - 1 : 0] TX_REQ_fetch_cxt_ingress_head; +wire [`TX_REQ_OOO_CXT_INGRESS_DATA_WIDTH - 1 : 0] TX_REQ_fetch_cxt_ingress_data; +wire TX_REQ_fetch_cxt_ingress_start; +wire TX_REQ_fetch_cxt_ingress_last; +wire TX_REQ_fetch_cxt_ingress_ready; + +wire TX_REQ_fetch_cxt_egress_valid; +wire [`TX_REQ_OOO_CXT_EGRESS_HEAD_WIDTH - 1 : 0] TX_REQ_fetch_cxt_egress_head; +wire [`TX_REQ_OOO_CXT_EGRESS_DATA_WIDTH - 1 : 0] TX_REQ_fetch_cxt_egress_data; +wire TX_REQ_fetch_cxt_egress_start; +wire TX_REQ_fetch_cxt_egress_last; +wire TX_REQ_fetch_cxt_egress_ready; + +wire RX_REQ_fetch_cxt_ingress_valid; +wire [`RX_REQ_OOO_CXT_INGRESS_HEAD_WIDTH - 1 : 0] RX_REQ_fetch_cxt_ingress_head; +wire [`RX_REQ_OOO_CXT_INGRESS_DATA_WIDTH - 1 : 0] RX_REQ_fetch_cxt_ingress_data; +wire RX_REQ_fetch_cxt_ingress_start; +wire RX_REQ_fetch_cxt_ingress_last; +wire RX_REQ_fetch_cxt_ingress_ready; + +wire RX_REQ_fetch_cxt_egress_valid; +wire [`RX_REQ_OOO_CXT_EGRESS_HEAD_WIDTH - 1 : 0] RX_REQ_fetch_cxt_egress_head; +wire [`RX_REQ_OOO_CXT_EGRESS_DATA_WIDTH - 1 : 0] RX_REQ_fetch_cxt_egress_data; +wire RX_REQ_fetch_cxt_egress_start; +wire RX_REQ_fetch_cxt_egress_last; +wire RX_REQ_fetch_cxt_egress_ready; + +wire RX_RESP_fetch_cxt_ingress_valid; +wire [`RX_RESP_OOO_CXT_INGRESS_HEAD_WIDTH - 1 : 0] RX_RESP_fetch_cxt_ingress_head; +wire [`RX_RESP_OOO_CXT_INGRESS_DATA_WIDTH - 1 : 0] RX_RESP_fetch_cxt_ingress_data; +wire RX_RESP_fetch_cxt_ingress_start; +wire RX_RESP_fetch_cxt_ingress_last; +wire RX_RESP_fetch_cxt_ingress_ready; + +wire RX_RESP_fetch_cxt_egress_valid; +wire [`RX_RESP_OOO_CXT_EGRESS_HEAD_WIDTH - 1 : 0] RX_RESP_fetch_cxt_egress_head; +wire [`RX_RESP_OOO_CXT_EGRESS_DATA_WIDTH - 1 : 0] RX_RESP_fetch_cxt_egress_data; +wire RX_RESP_fetch_cxt_egress_start; +wire RX_RESP_fetch_cxt_egress_last; +wire RX_RESP_fetch_cxt_egress_ready; + +wire SQ_fetch_mr_ingress_valid; +wire [`SQ_OOO_MR_INGRESS_HEAD_WIDTH - 1 : 0] SQ_fetch_mr_ingress_head; +wire [`SQ_OOO_MR_INGRESS_DATA_WIDTH - 1 : 0] SQ_fetch_mr_ingress_data; +wire SQ_fetch_mr_ingress_start; +wire SQ_fetch_mr_ingress_last; +wire SQ_fetch_mr_ingress_ready; + +wire SQ_fetch_mr_egress_valid; +wire [`SQ_OOO_MR_EGRESS_HEAD_WIDTH - 1 : 0] SQ_fetch_mr_egress_head; +wire [`SQ_OOO_MR_EGRESS_DATA_WIDTH - 1 : 0] SQ_fetch_mr_egress_data; +wire SQ_fetch_mr_egress_start; +wire SQ_fetch_mr_egress_last; +wire SQ_fetch_mr_egress_ready; + +wire RQ_fetch_mr_ingress_valid; +wire [`RQ_OOO_MR_INGRESS_HEAD_WIDTH - 1 : 0] RQ_fetch_mr_ingress_head; +wire [`RQ_OOO_MR_INGRESS_DATA_WIDTH - 1 : 0] RQ_fetch_mr_ingress_data; +wire RQ_fetch_mr_ingress_start; +wire RQ_fetch_mr_ingress_last; +wire RQ_fetch_mr_ingress_ready; + +wire RQ_fetch_mr_egress_valid; +wire [`RQ_OOO_MR_EGRESS_HEAD_WIDTH - 1 : 0] RQ_fetch_mr_egress_head; +wire [`RQ_OOO_MR_EGRESS_DATA_WIDTH - 1 : 0] RQ_fetch_mr_egress_data; +wire RQ_fetch_mr_egress_start; +wire RQ_fetch_mr_egress_last; +wire RQ_fetch_mr_egress_ready; + +wire TX_REQ_fetch_mr_ingress_valid; +wire [`TX_REQ_OOO_MR_INGRESS_HEAD_WIDTH - 1 : 0] TX_REQ_fetch_mr_ingress_head; +wire [`TX_REQ_OOO_MR_INGRESS_DATA_WIDTH - 1 : 0] TX_REQ_fetch_mr_ingress_data; +wire TX_REQ_fetch_mr_ingress_start; +wire TX_REQ_fetch_mr_ingress_last; +wire TX_REQ_fetch_mr_ingress_ready; + +wire TX_REQ_fetch_mr_egress_valid; +wire [`TX_REQ_OOO_MR_EGRESS_HEAD_WIDTH - 1 : 0] TX_REQ_fetch_mr_egress_head; +wire [`TX_REQ_OOO_MR_EGRESS_DATA_WIDTH - 1 : 0] TX_REQ_fetch_mr_egress_data; +wire TX_REQ_fetch_mr_egress_start; +wire TX_REQ_fetch_mr_egress_last; +wire TX_REQ_fetch_mr_egress_ready; + +wire RX_RESP_fetch_mr_ingress_valid; +wire [`RX_RESP_OOO_MR_INGRESS_HEAD_WIDTH - 1 : 0] RX_RESP_fetch_mr_ingress_head; +wire [`RX_RESP_OOO_MR_INGRESS_DATA_WIDTH - 1 : 0] RX_RESP_fetch_mr_ingress_data; +wire RX_RESP_fetch_mr_ingress_start; +wire RX_RESP_fetch_mr_ingress_last; +wire RX_RESP_fetch_mr_ingress_ready; + +wire RX_RESP_fetch_mr_egress_valid; +wire [`RX_RESP_OOO_MR_EGRESS_HEAD_WIDTH - 1 : 0] RX_RESP_fetch_mr_egress_head; +wire [`RX_RESP_OOO_MR_EGRESS_DATA_WIDTH - 1 : 0] RX_RESP_fetch_mr_egress_data; +wire RX_RESP_fetch_mr_egress_start; +wire RX_RESP_fetch_mr_egress_last; +wire RX_RESP_fetch_mr_egress_ready; + +wire RX_REQ_fetch_mr_ingress_valid; +wire [`RX_REQ_OOO_MR_INGRESS_HEAD_WIDTH - 1 : 0] RX_REQ_fetch_mr_ingress_head; +wire [`RX_REQ_OOO_MR_INGRESS_DATA_WIDTH - 1 : 0] RX_REQ_fetch_mr_ingress_data; +wire RX_REQ_fetch_mr_ingress_start; +wire RX_REQ_fetch_mr_ingress_last; +wire RX_REQ_fetch_mr_ingress_ready; + +wire RX_REQ_fetch_mr_egress_valid; +wire [`RX_REQ_OOO_MR_EGRESS_HEAD_WIDTH - 1 : 0] RX_REQ_fetch_mr_egress_head; +wire [`RX_REQ_OOO_MR_EGRESS_DATA_WIDTH - 1 : 0] RX_REQ_fetch_mr_egress_data; +wire RX_REQ_fetch_mr_egress_start; +wire RX_REQ_fetch_mr_egress_last; +wire RX_REQ_fetch_mr_egress_ready; + + +wire TX_REQ_sub_wqe_valid; +wire [`WQE_META_WIDTH - 1 : 0] TX_REQ_sub_wqe_meta; +wire TX_REQ_sub_wqe_ready; + +wire TX_inline_insert_req_valid; +wire TX_inline_insert_req_start; +wire TX_inline_insert_req_last; +wire [`INLINE_PAYLOAD_BUFFER_SLOT_NUM_LOG - 1 : 0] TX_inline_insert_req_head; +wire [`INLINE_PAYLOAD_BUFFER_SLOT_WIDTH - 1 : 0] TX_inline_insert_req_data; +wire TX_inline_insert_req_ready; + +wire TX_inline_insert_resp_valid; +wire [`INLINE_PAYLOAD_BUFFER_SLOT_WIDTH - 1 : 0] TX_inline_insert_resp_data; + +wire RQ_wqe_req_valid; +wire [`WQE_META_WIDTH - 1 : 0] RQ_wqe_req_head; +wire RQ_wqe_req_start; +wire RQ_wqe_req_last; +wire RQ_wqe_req_ready; + +wire RQ_wqe_resp_valid; +wire [`WQE_META_WIDTH - 1 : 0] RQ_wqe_resp_head; +wire [`WQE_SEG_WIDTH - 1 : 0] RQ_wqe_resp_data; +wire RQ_wqe_resp_start; +wire RQ_wqe_resp_last; +wire RQ_wqe_resp_ready; + +wire RQ_cache_offset_wen; +wire [`QP_NUM_LOG - 1 : 0] RQ_cache_offset_addr; +wire [`RQ_CACHE_SLOT_NUM_LOG - 1:0] RQ_cache_offset_din; +wire [`RQ_CACHE_SLOT_NUM_LOG - 1:0] RQ_cache_offset_dout; + +wire RQ_offset_wen; +wire [`QP_NUM_LOG - 1 : 0] RQ_offset_addr; +wire [23:0] RQ_offset_din; +wire [23:0] RQ_offset_dout; + +wire RQ_cache_owned_wen; +wire [`RQ_CACHE_CELL_NUM_LOG - 1 : 0] RQ_cache_owned_addr; +wire [`QP_NUM_LOG - 1 : 0] RQ_cache_owned_din; +wire [`QP_NUM_LOG - 1 : 0] RQ_cache_owned_dout; + +wire TX_REQ_cq_req_valid; +wire [`CQ_REQ_HEAD_WIDTH - 1 : 0] TX_REQ_cq_req_head; +wire TX_REQ_cq_req_ready; + +wire TX_REQ_cq_resp_valid; +wire [`CQ_RESP_HEAD_WIDTH - 1 : 0] TX_REQ_cq_resp_head; +wire TX_REQ_cq_resp_ready; + +wire RX_REQ_cq_req_valid; +wire [`CQ_REQ_HEAD_WIDTH - 1 : 0] RX_REQ_cq_req_head; +wire RX_REQ_cq_req_ready; + +wire RX_REQ_cq_resp_valid; +wire [`CQ_RESP_HEAD_WIDTH - 1 : 0] RX_REQ_cq_resp_head; +wire RX_REQ_cq_resp_ready; + +wire RX_RESP_cq_req_valid; +wire [`CQ_REQ_HEAD_WIDTH - 1 : 0] RX_RESP_cq_req_head; +wire RX_RESP_cq_req_ready; + +wire RX_RESP_cq_resp_valid; +wire [`CQ_RESP_HEAD_WIDTH - 1 : 0] RX_RESP_cq_resp_head; +wire RX_RESP_cq_resp_ready; + +wire TX_REQ_eq_req_valid; +wire [`EQ_REQ_HEAD_WIDTH - 1 : 0] TX_REQ_eq_req_head; +wire TX_REQ_eq_req_ready; + +wire TX_REQ_eq_resp_valid; +wire [`EQ_RESP_HEAD_WIDTH - 1 : 0] TX_REQ_eq_resp_head; +wire TX_REQ_eq_resp_ready; + +wire RX_REQ_eq_req_valid; +wire [`EQ_REQ_HEAD_WIDTH - 1 : 0] RX_REQ_eq_req_head; +wire RX_REQ_eq_req_ready; + +wire RX_REQ_eq_resp_valid; +wire [`EQ_RESP_HEAD_WIDTH - 1 : 0] RX_REQ_eq_resp_head; +wire RX_REQ_eq_resp_ready; + +wire RX_RESP_eq_req_valid; +wire [`EQ_REQ_HEAD_WIDTH - 1 : 0] RX_RESP_eq_req_head; +wire RX_RESP_eq_req_ready; + +wire RX_RESP_eq_resp_valid; +wire [`EQ_RESP_HEAD_WIDTH - 1 : 0] RX_RESP_eq_resp_head; +wire RX_RESP_eq_resp_ready; + +wire TX_egress_pkt_valid; +wire [`PKT_META_BUS_WIDTH - 1 : 0] TX_egress_pkt_head; +wire TX_egress_pkt_ready; + +wire TX_non_inline_insert_req_valid; +wire TX_non_inline_insert_req_start; +wire TX_non_inline_insert_req_last; +wire [`MAX_DB_SLOT_NUM_LOG - 1 : 0] TX_non_inline_insert_req_head; +wire [`PACKET_BUFFER_SLOT_WIDTH - 1 : 0] TX_non_inline_insert_req_data; +wire TX_non_inline_insert_req_ready; + +wire TX_non_inline_insert_resp_valid; +wire [`MAX_DB_SLOT_NUM_LOG - 1 : 0] TX_non_inline_insert_resp_data; + +wire TX_insert_req_valid; +wire TX_insert_req_start; +wire TX_insert_req_last; +wire [`MAX_DB_SLOT_NUM_LOG - 1 : 0] TX_insert_req_head; +wire [`PACKET_BUFFER_SLOT_WIDTH - 1 : 0] TX_insert_req_data; +wire TX_insert_req_ready; + +wire TX_insert_resp_valid; +wire [`MAX_DB_SLOT_NUM_LOG - 1 : 0] TX_insert_resp_data; + +wire RX_ingress_pkt_valid; +wire [`PKT_META_BUS_WIDTH - 1 : 0] RX_ingress_pkt_head; +wire RX_ingress_pkt_ready; + +wire RX_delete_req_valid; +wire [`MAX_DB_SLOT_NUM_LOG * 2 - 1 : 0] RX_delete_req_head; +wire RX_delete_req_ready; + +wire RX_delete_resp_valid; +wire RX_delete_resp_start; +wire RX_delete_resp_last; +wire [`PACKET_BUFFER_SLOT_WIDTH - 1 : 0] RX_delete_resp_data; +wire RX_delete_resp_ready; + +/*------------------------------------------- Local Variables Definition : End --------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : Begin ---------------------------------------*/ +QueueSubsystem +#( + .INGRESS_CXT_HEAD_WIDTH ( INGRESS_CXT_HEAD_WIDTH ), + .INGRESS_CXT_DATA_WIDTH ( INGRESS_CXT_DATA_WIDTH ), + .EGRESS_CXT_HEAD_WIDTH ( EGRESS_CXT_HEAD_WIDTH ), + .EGRESS_CXT_DATA_WIDTH ( EGRESS_CXT_DATA_WIDTH ), + + .INGRESS_MR_HEAD_WIDTH ( INGRESS_MR_HEAD_WIDTH ), + .INGRESS_MR_DATA_WIDTH ( INGRESS_MR_DATA_WIDTH ), + .EGRESS_MR_HEAD_WIDTH ( EGRESS_MR_HEAD_WIDTH ), + .EGRESS_MR_DATA_WIDTH ( EGRESS_MR_DATA_WIDTH ) +) +QueueSubsystem_Inst +( + .clk ( user_clk ), + .rst ( user_rst ), + +//SQ Interface + .db_fifo_empty ( db_fifo_empty ), + .db_fifo_dout ( db_fifo_dout ), + .db_fifo_rd_en ( db_fifo_rd_en ), + + .SQ_fetch_cxt_ingress_valid ( SQ_fetch_cxt_ingress_valid ), + .SQ_fetch_cxt_ingress_head ( SQ_fetch_cxt_ingress_head ), + .SQ_fetch_cxt_ingress_data ( SQ_fetch_cxt_ingress_data ), + .SQ_fetch_cxt_ingress_start ( SQ_fetch_cxt_ingress_start ), + .SQ_fetch_cxt_ingress_last ( SQ_fetch_cxt_ingress_last ), + .SQ_fetch_cxt_ingress_ready ( SQ_fetch_cxt_ingress_ready ), + + .SQ_fetch_cxt_egress_valid ( SQ_fetch_cxt_egress_valid ), + .SQ_fetch_cxt_egress_head ( SQ_fetch_cxt_egress_head ), + .SQ_fetch_cxt_egress_data ( SQ_fetch_cxt_egress_data ), + .SQ_fetch_cxt_egress_start ( SQ_fetch_cxt_egress_start ), + .SQ_fetch_cxt_egress_last ( SQ_fetch_cxt_egress_last ), + .SQ_fetch_cxt_egress_ready ( SQ_fetch_cxt_egress_ready ), + + .SQ_fetch_mr_ingress_valid ( SQ_fetch_mr_ingress_valid ), + .SQ_fetch_mr_ingress_head ( SQ_fetch_mr_ingress_head ), + .SQ_fetch_mr_ingress_data ( SQ_fetch_mr_ingress_data ), + .SQ_fetch_mr_ingress_start ( SQ_fetch_mr_ingress_start ), + .SQ_fetch_mr_ingress_last ( SQ_fetch_mr_ingress_last ), + .SQ_fetch_mr_ingress_ready ( SQ_fetch_mr_ingress_ready ), + + .SQ_fetch_mr_egress_valid ( SQ_fetch_mr_egress_valid ), + .SQ_fetch_mr_egress_head ( SQ_fetch_mr_egress_head ), + .SQ_fetch_mr_egress_data ( SQ_fetch_mr_egress_data ), + .SQ_fetch_mr_egress_start ( SQ_fetch_mr_egress_start ), + .SQ_fetch_mr_egress_last ( SQ_fetch_mr_egress_last ), + .SQ_fetch_mr_egress_ready ( SQ_fetch_mr_egress_ready ), + + .SQ_dma_rd_req_valid ( SQ_dma_rd_req_valid ), + .SQ_dma_rd_req_head ( SQ_dma_rd_req_head ), + .SQ_dma_rd_req_data ( SQ_dma_rd_req_data ), + .SQ_dma_rd_req_last ( SQ_dma_rd_req_last ), + .SQ_dma_rd_req_ready ( SQ_dma_rd_req_ready ), + + .SQ_dma_rd_rsp_valid ( SQ_dma_rd_rsp_valid ), + .SQ_dma_rd_rsp_head ( SQ_dma_rd_rsp_head ), + .SQ_dma_rd_rsp_data ( SQ_dma_rd_rsp_data ), + .SQ_dma_rd_rsp_last ( SQ_dma_rd_rsp_last ), + .SQ_dma_rd_rsp_ready ( SQ_dma_rd_rsp_ready ), + + .sub_wqe_valid ( TX_REQ_sub_wqe_valid ), + .sub_wqe_meta ( TX_REQ_sub_wqe_meta ), + .sub_wqe_ready ( TX_REQ_sub_wqe_ready ), + + .insert_req_valid ( TX_inline_insert_req_valid ), + .insert_req_start ( TX_inline_insert_req_start ), + .insert_req_last ( TX_inline_insert_req_last ), + .insert_req_head ( TX_inline_insert_req_head ), + .insert_req_data ( TX_inline_insert_req_data ), + .insert_req_ready ( TX_inline_insert_req_ready ), + + .insert_resp_valid ( TX_inline_insert_resp_valid ), + .insert_resp_data ( TX_inline_insert_resp_data ), + +//RQ Interface + .RQ_wqe_req_valid ( RQ_wqe_req_valid ), + .RQ_wqe_req_head ( RQ_wqe_req_head ), + .RQ_wqe_req_start ( RQ_wqe_req_start ), + .RQ_wqe_req_last ( RQ_wqe_req_last ), + .RQ_wqe_req_ready ( RQ_wqe_req_ready ), + + .RQ_wqe_resp_valid ( RQ_wqe_resp_valid ), + .RQ_wqe_resp_head ( RQ_wqe_resp_head ), + .RQ_wqe_resp_data ( RQ_wqe_resp_data ), + .RQ_wqe_resp_start ( RQ_wqe_resp_start ), + .RQ_wqe_resp_last ( RQ_wqe_resp_last ), + .RQ_wqe_resp_ready ( RQ_wqe_resp_ready ), + + .RQ_cache_offset_wen ( RQ_cache_offset_wen ), + .RQ_cache_offset_addr ( RQ_cache_offset_addr ), + .RQ_cache_offset_din ( RQ_cache_offset_din ), + .RQ_cache_offset_dout ( RQ_cache_offset_dout ), + + .RQ_offset_wen ( RQ_offset_wen ), + .RQ_offset_addr ( RQ_offset_addr ), + .RQ_offset_din ( RQ_offset_din ), + .RQ_offset_dout ( RQ_offset_dout ), + + .RQ_cache_owned_wen ( RQ_cache_owned_wen ), + .RQ_cache_owned_addr ( RQ_cache_owned_addr ), + .RQ_cache_owned_din ( RQ_cache_owned_din ), + .RQ_cache_owned_dout ( RQ_cache_owned_dout ), + + .RQ_fetch_mr_ingress_valid ( RQ_fetch_mr_ingress_valid ), + .RQ_fetch_mr_ingress_head ( RQ_fetch_mr_ingress_head ), + .RQ_fetch_mr_ingress_data ( RQ_fetch_mr_ingress_data ), + .RQ_fetch_mr_ingress_start ( RQ_fetch_mr_ingress_start ), + .RQ_fetch_mr_ingress_last ( RQ_fetch_mr_ingress_last ), + .RQ_fetch_mr_ingress_ready ( RQ_fetch_mr_ingress_ready ), + + .RQ_fetch_mr_egress_valid ( RQ_fetch_mr_egress_valid ), + .RQ_fetch_mr_egress_head ( RQ_fetch_mr_egress_head ), + .RQ_fetch_mr_egress_data ( RQ_fetch_mr_egress_data ), + .RQ_fetch_mr_egress_start ( RQ_fetch_mr_egress_start ), + .RQ_fetch_mr_egress_last ( RQ_fetch_mr_egress_last ), + .RQ_fetch_mr_egress_ready ( RQ_fetch_mr_egress_ready ), + + .RQ_dma_rd_req_valid ( RQ_dma_rd_req_valid ), + .RQ_dma_rd_req_head ( RQ_dma_rd_req_head ), + .RQ_dma_rd_req_data ( RQ_dma_rd_req_data ), + .RQ_dma_rd_req_last ( RQ_dma_rd_req_last ), + .RQ_dma_rd_req_ready ( RQ_dma_rd_req_ready ), + + .RQ_dma_rd_rsp_valid ( RQ_dma_rd_rsp_valid ), + .RQ_dma_rd_rsp_head ( RQ_dma_rd_rsp_head ), + .RQ_dma_rd_rsp_data ( RQ_dma_rd_rsp_data ), + .RQ_dma_rd_rsp_last ( RQ_dma_rd_rsp_last ), + .RQ_dma_rd_rsp_ready ( RQ_dma_rd_rsp_ready ), + +//CQ Interface + .TX_REQ_cq_req_valid ( TX_REQ_cq_req_valid ), + .TX_REQ_cq_req_head ( TX_REQ_cq_req_head ), + .TX_REQ_cq_req_ready ( TX_REQ_cq_req_ready ), + + .TX_REQ_cq_resp_valid ( TX_REQ_cq_resp_valid ), + .TX_REQ_cq_resp_head ( TX_REQ_cq_resp_head ), + .TX_REQ_cq_resp_ready ( TX_REQ_cq_resp_ready ), + + .RX_REQ_cq_req_valid ( RX_REQ_cq_req_valid ), + .RX_REQ_cq_req_head ( RX_REQ_cq_req_head ), + .RX_REQ_cq_req_ready ( RX_REQ_cq_req_ready ), + + .RX_REQ_cq_resp_valid ( RX_REQ_cq_resp_valid ), + .RX_REQ_cq_resp_head ( RX_REQ_cq_resp_head ), + .RX_REQ_cq_resp_ready ( RX_REQ_cq_resp_ready ), + + .RX_RESP_cq_req_valid ( RX_RESP_cq_req_valid ), + .RX_RESP_cq_req_head ( RX_RESP_cq_req_head ), + .RX_RESP_cq_req_ready ( RX_RESP_cq_req_ready ), + + .RX_RESP_cq_resp_valid ( RX_RESP_cq_resp_valid ), + .RX_RESP_cq_resp_head ( RX_RESP_cq_resp_head ), + .RX_RESP_cq_resp_ready ( RX_RESP_cq_resp_ready ), + +//EQ Interface + .TX_REQ_eq_req_valid ( TX_REQ_eq_req_valid ), + .TX_REQ_eq_req_head ( TX_REQ_eq_req_head ), + .TX_REQ_eq_req_ready ( TX_REQ_eq_req_ready ), + + .TX_REQ_eq_resp_valid ( TX_REQ_eq_resp_valid ), + .TX_REQ_eq_resp_head ( TX_REQ_eq_resp_head ), + .TX_REQ_eq_resp_ready ( TX_REQ_eq_resp_ready ), + + .RX_REQ_eq_req_valid ( RX_REQ_eq_req_valid ), + .RX_REQ_eq_req_head ( RX_REQ_eq_req_head ), + .RX_REQ_eq_req_ready ( RX_REQ_eq_req_ready ), + + .RX_REQ_eq_resp_valid ( RX_REQ_eq_resp_valid ), + .RX_REQ_eq_resp_head ( RX_REQ_eq_resp_head ), + .RX_REQ_eq_resp_ready ( RX_REQ_eq_resp_ready ), + + .RX_RESP_eq_req_valid ( RX_RESP_eq_req_valid ), + .RX_RESP_eq_req_head ( RX_RESP_eq_req_head ), + .RX_RESP_eq_req_ready ( RX_RESP_eq_req_ready ), + + .RX_RESP_eq_resp_valid ( RX_RESP_eq_resp_valid ), + .RX_RESP_eq_resp_head ( RX_RESP_eq_resp_head ), + .RX_RESP_eq_resp_ready ( RX_RESP_eq_resp_ready ) +); + +ResMgtSubsystem #( + .INGRESS_CXT_HEAD_WIDTH ( INGRESS_CXT_HEAD_WIDTH ), + .INGRESS_CXT_DATA_WIDTH ( INGRESS_CXT_DATA_WIDTH ), + .EGRESS_CXT_HEAD_WIDTH ( EGRESS_CXT_HEAD_WIDTH ), + .EGRESS_CXT_DATA_WIDTH ( EGRESS_CXT_DATA_WIDTH ), + + .INGRESS_MR_HEAD_WIDTH ( INGRESS_MR_HEAD_WIDTH ), + .INGRESS_MR_DATA_WIDTH ( INGRESS_MR_DATA_WIDTH ), + .EGRESS_MR_HEAD_WIDTH ( EGRESS_MR_HEAD_WIDTH ), + .EGRESS_MR_DATA_WIDTH ( EGRESS_MR_DATA_WIDTH ) +) +ResMgtSubsystem_Inst +( + .clk ( user_clk ), + .rst ( user_rst ), + + .ceu_hcr_in_param ( ceu_hcr_in_param ), + .ceu_hcr_in_modifier ( ceu_hcr_in_modifier ), + .ceu_hcr_out_dma_addr ( ceu_hcr_out_dma_addr ), + .ceu_hcr_token ( ceu_hcr_token ), + .ceu_hcr_go ( ceu_hcr_go ), + .ceu_hcr_event ( ceu_hcr_event ), + .ceu_hcr_op_modifier ( ceu_hcr_op_modifier ), + .ceu_hcr_op ( ceu_hcr_op ), + + .ceu_hcr_out_param ( ceu_hcr_out_param ), + .ceu_hcr_status ( ceu_hcr_status ), + .ceu_hcr_clear ( ceu_hcr_clear ), + + .CEU_dma_rd_req_valid ( CEU_dma_rd_req_valid ), + .CEU_dma_rd_req_last ( CEU_dma_rd_req_last ), + .CEU_dma_rd_req_head ( CEU_dma_rd_req_head ), + .CEU_dma_rd_req_data ( CEU_dma_rd_req_data ), + .CEU_dma_rd_req_ready ( CEU_dma_rd_req_ready ), + + .CEU_dma_rd_rsp_valid ( CEU_dma_rd_rsp_valid ), + .CEU_dma_rd_rsp_last ( CEU_dma_rd_rsp_last ), + .CEU_dma_rd_rsp_head ( CEU_dma_rd_rsp_head ), + .CEU_dma_rd_rsp_data ( CEU_dma_rd_rsp_data ), + .CEU_dma_rd_rsp_ready ( CEU_dma_rd_rsp_ready ), + + .CEU_dma_wr_req_valid ( CEU_dma_wr_req_valid ), + .CEU_dma_wr_req_last ( CEU_dma_wr_req_last ), + .CEU_dma_wr_req_head ( CEU_dma_wr_req_head ), + .CEU_dma_wr_req_data ( CEU_dma_wr_req_data ), + .CEU_dma_wr_req_ready ( CEU_dma_wr_req_ready ), + + .SQ_fetch_cxt_ingress_valid ( SQ_fetch_cxt_ingress_valid ), + .SQ_fetch_cxt_ingress_head ( SQ_fetch_cxt_ingress_head ), + .SQ_fetch_cxt_ingress_data ( SQ_fetch_cxt_ingress_data ), + .SQ_fetch_cxt_ingress_start ( SQ_fetch_cxt_ingress_start ), + .SQ_fetch_cxt_ingress_last ( SQ_fetch_cxt_ingress_last ), + .SQ_fetch_cxt_ingress_ready ( SQ_fetch_cxt_ingress_ready ), + + .SQ_fetch_cxt_egress_valid ( SQ_fetch_cxt_egress_valid ), + .SQ_fetch_cxt_egress_head ( SQ_fetch_cxt_egress_head ), + .SQ_fetch_cxt_egress_data ( SQ_fetch_cxt_egress_data ), + .SQ_fetch_cxt_egress_start ( SQ_fetch_cxt_egress_start ), + .SQ_fetch_cxt_egress_last ( SQ_fetch_cxt_egress_last ), + .SQ_fetch_cxt_egress_ready ( SQ_fetch_cxt_egress_ready ), + + .TX_REQ_fetch_cxt_ingress_valid ( TX_REQ_fetch_cxt_ingress_valid ), + .TX_REQ_fetch_cxt_ingress_head ( TX_REQ_fetch_cxt_ingress_head ), + .TX_REQ_fetch_cxt_ingress_data ( TX_REQ_fetch_cxt_ingress_data ), + .TX_REQ_fetch_cxt_ingress_start ( TX_REQ_fetch_cxt_ingress_start ), + .TX_REQ_fetch_cxt_ingress_last ( TX_REQ_fetch_cxt_ingress_last ), + .TX_REQ_fetch_cxt_ingress_ready ( TX_REQ_fetch_cxt_ingress_ready ), + + .TX_REQ_fetch_cxt_egress_valid ( TX_REQ_fetch_cxt_egress_valid ), + .TX_REQ_fetch_cxt_egress_head ( TX_REQ_fetch_cxt_egress_head ), + .TX_REQ_fetch_cxt_egress_data ( TX_REQ_fetch_cxt_egress_data ), + .TX_REQ_fetch_cxt_egress_start ( TX_REQ_fetch_cxt_egress_start ), + .TX_REQ_fetch_cxt_egress_last ( TX_REQ_fetch_cxt_egress_last ), + .TX_REQ_fetch_cxt_egress_ready ( TX_REQ_fetch_cxt_egress_ready ), + + .RX_REQ_fetch_cxt_ingress_valid ( RX_REQ_fetch_cxt_ingress_valid ), + .RX_REQ_fetch_cxt_ingress_head ( RX_REQ_fetch_cxt_ingress_head ), + .RX_REQ_fetch_cxt_ingress_data ( RX_REQ_fetch_cxt_ingress_data ), + .RX_REQ_fetch_cxt_ingress_start ( RX_REQ_fetch_cxt_ingress_start ), + .RX_REQ_fetch_cxt_ingress_last ( RX_REQ_fetch_cxt_ingress_last ), + .RX_REQ_fetch_cxt_ingress_ready ( RX_REQ_fetch_cxt_ingress_ready ), + + .RX_REQ_fetch_cxt_egress_valid ( RX_REQ_fetch_cxt_egress_valid ), + .RX_REQ_fetch_cxt_egress_head ( RX_REQ_fetch_cxt_egress_head ), + .RX_REQ_fetch_cxt_egress_data ( RX_REQ_fetch_cxt_egress_data ), + .RX_REQ_fetch_cxt_egress_start ( RX_REQ_fetch_cxt_egress_start ), + .RX_REQ_fetch_cxt_egress_last ( RX_REQ_fetch_cxt_egress_last ), + .RX_REQ_fetch_cxt_egress_ready ( RX_REQ_fetch_cxt_egress_ready ), + + .RX_RESP_fetch_cxt_ingress_valid ( RX_RESP_fetch_cxt_ingress_valid ), + .RX_RESP_fetch_cxt_ingress_head ( RX_RESP_fetch_cxt_ingress_head ), + .RX_RESP_fetch_cxt_ingress_data ( RX_RESP_fetch_cxt_ingress_data ), + .RX_RESP_fetch_cxt_ingress_start ( RX_RESP_fetch_cxt_ingress_start ), + .RX_RESP_fetch_cxt_ingress_last ( RX_RESP_fetch_cxt_ingress_last ), + .RX_RESP_fetch_cxt_ingress_ready ( RX_RESP_fetch_cxt_ingress_ready ), + + .RX_RESP_fetch_cxt_egress_valid ( RX_RESP_fetch_cxt_egress_valid ), + .RX_RESP_fetch_cxt_egress_head ( RX_RESP_fetch_cxt_egress_head ), + .RX_RESP_fetch_cxt_egress_data ( RX_RESP_fetch_cxt_egress_data ), + .RX_RESP_fetch_cxt_egress_start ( RX_RESP_fetch_cxt_egress_start ), + .RX_RESP_fetch_cxt_egress_last ( RX_RESP_fetch_cxt_egress_last ), + .RX_RESP_fetch_cxt_egress_ready ( RX_RESP_fetch_cxt_egress_ready ), + + .SQ_fetch_mr_ingress_valid ( SQ_fetch_mr_ingress_valid ), + .SQ_fetch_mr_ingress_head ( SQ_fetch_mr_ingress_head ), + .SQ_fetch_mr_ingress_data ( SQ_fetch_mr_ingress_data ), + .SQ_fetch_mr_ingress_start ( SQ_fetch_mr_ingress_start ), + .SQ_fetch_mr_ingress_last ( SQ_fetch_mr_ingress_last ), + .SQ_fetch_mr_ingress_ready ( SQ_fetch_mr_ingress_ready ), + + .SQ_fetch_mr_egress_valid ( SQ_fetch_mr_egress_valid ), + .SQ_fetch_mr_egress_head ( SQ_fetch_mr_egress_head ), + .SQ_fetch_mr_egress_data ( SQ_fetch_mr_egress_data ), + .SQ_fetch_mr_egress_start ( SQ_fetch_mr_egress_start ), + .SQ_fetch_mr_egress_last ( SQ_fetch_mr_egress_last ), + .SQ_fetch_mr_egress_ready ( SQ_fetch_mr_egress_ready ), + + .RQ_fetch_mr_ingress_valid ( RQ_fetch_mr_ingress_valid ), + .RQ_fetch_mr_ingress_head ( RQ_fetch_mr_ingress_head ), + .RQ_fetch_mr_ingress_data ( RQ_fetch_mr_ingress_data ), + .RQ_fetch_mr_ingress_start ( RQ_fetch_mr_ingress_start ), + .RQ_fetch_mr_ingress_last ( RQ_fetch_mr_ingress_last ), + .RQ_fetch_mr_ingress_ready ( RQ_fetch_mr_ingress_ready ), + + .RQ_fetch_mr_egress_valid ( RQ_fetch_mr_egress_valid ), + .RQ_fetch_mr_egress_head ( RQ_fetch_mr_egress_head ), + .RQ_fetch_mr_egress_data ( RQ_fetch_mr_egress_data ), + .RQ_fetch_mr_egress_start ( RQ_fetch_mr_egress_start ), + .RQ_fetch_mr_egress_last ( RQ_fetch_mr_egress_last ), + .RQ_fetch_mr_egress_ready ( RQ_fetch_mr_egress_ready ), + + .TX_REQ_fetch_mr_ingress_valid ( TX_REQ_fetch_mr_ingress_valid ), + .TX_REQ_fetch_mr_ingress_head ( TX_REQ_fetch_mr_ingress_head ), + .TX_REQ_fetch_mr_ingress_data ( TX_REQ_fetch_mr_ingress_data ), + .TX_REQ_fetch_mr_ingress_start ( TX_REQ_fetch_mr_ingress_start ), + .TX_REQ_fetch_mr_ingress_last ( TX_REQ_fetch_mr_ingress_last ), + .TX_REQ_fetch_mr_ingress_ready ( TX_REQ_fetch_mr_ingress_ready ), + + .TX_REQ_fetch_mr_egress_valid ( TX_REQ_fetch_mr_egress_valid ), + .TX_REQ_fetch_mr_egress_head ( TX_REQ_fetch_mr_egress_head ), + .TX_REQ_fetch_mr_egress_data ( TX_REQ_fetch_mr_egress_data ), + .TX_REQ_fetch_mr_egress_start ( TX_REQ_fetch_mr_egress_start ), + .TX_REQ_fetch_mr_egress_last ( TX_REQ_fetch_mr_egress_last ), + .TX_REQ_fetch_mr_egress_ready ( TX_REQ_fetch_mr_egress_ready ), + + .RX_RESP_fetch_mr_ingress_valid ( RX_RESP_fetch_mr_ingress_valid ), + .RX_RESP_fetch_mr_ingress_head ( RX_RESP_fetch_mr_ingress_head ), + .RX_RESP_fetch_mr_ingress_data ( RX_RESP_fetch_mr_ingress_data ), + .RX_RESP_fetch_mr_ingress_start ( RX_RESP_fetch_mr_ingress_start ), + .RX_RESP_fetch_mr_ingress_last ( RX_RESP_fetch_mr_ingress_last ), + .RX_RESP_fetch_mr_ingress_ready ( RX_RESP_fetch_mr_ingress_ready ), + + .RX_RESP_fetch_mr_egress_valid ( RX_RESP_fetch_mr_egress_valid ), + .RX_RESP_fetch_mr_egress_head ( RX_RESP_fetch_mr_egress_head ), + .RX_RESP_fetch_mr_egress_data ( RX_RESP_fetch_mr_egress_data ), + .RX_RESP_fetch_mr_egress_start ( RX_RESP_fetch_mr_egress_start ), + .RX_RESP_fetch_mr_egress_last ( RX_RESP_fetch_mr_egress_last ), + .RX_RESP_fetch_mr_egress_ready ( RX_RESP_fetch_mr_egress_ready ), + + .RX_REQ_fetch_mr_ingress_valid ( RX_REQ_fetch_mr_ingress_valid ), + .RX_REQ_fetch_mr_ingress_head ( RX_REQ_fetch_mr_ingress_head ), + .RX_REQ_fetch_mr_ingress_data ( RX_REQ_fetch_mr_ingress_data ), + .RX_REQ_fetch_mr_ingress_start ( RX_REQ_fetch_mr_ingress_start ), + .RX_REQ_fetch_mr_ingress_last ( RX_REQ_fetch_mr_ingress_last ), + .RX_REQ_fetch_mr_ingress_ready ( RX_REQ_fetch_mr_ingress_ready ), + + .RX_REQ_fetch_mr_egress_valid ( RX_REQ_fetch_mr_egress_valid ), + .RX_REQ_fetch_mr_egress_head ( RX_REQ_fetch_mr_egress_head ), + .RX_REQ_fetch_mr_egress_data ( RX_REQ_fetch_mr_egress_data ), + .RX_REQ_fetch_mr_egress_start ( RX_REQ_fetch_mr_egress_start ), + .RX_REQ_fetch_mr_egress_last ( RX_REQ_fetch_mr_egress_last ), + .RX_REQ_fetch_mr_egress_ready ( RX_REQ_fetch_mr_egress_ready ), + + .QPC_dma_rd_req_valid ( QPC_dma_rd_req_valid ), + .QPC_dma_rd_req_head ( QPC_dma_rd_req_head ), + .QPC_dma_rd_req_data ( QPC_dma_rd_req_data ), + .QPC_dma_rd_req_last ( QPC_dma_rd_req_last ), + .QPC_dma_rd_req_ready ( QPC_dma_rd_req_ready ), + + .QPC_dma_rd_rsp_valid ( QPC_dma_rd_rsp_valid ), + .QPC_dma_rd_rsp_head ( QPC_dma_rd_rsp_head ), + .QPC_dma_rd_rsp_data ( QPC_dma_rd_rsp_data ), + .QPC_dma_rd_rsp_last ( QPC_dma_rd_rsp_last ), + .QPC_dma_rd_rsp_ready ( QPC_dma_rd_rsp_ready ), + + .QPC_dma_wr_req_valid ( QPC_dma_wr_req_valid ), + .QPC_dma_wr_req_head ( QPC_dma_wr_req_head ), + .QPC_dma_wr_req_data ( QPC_dma_wr_req_data ), + .QPC_dma_wr_req_last ( QPC_dma_wr_req_last ), + .QPC_dma_wr_req_ready ( QPC_dma_wr_req_ready ), + + .CQC_dma_rd_req_valid ( CQC_dma_rd_req_valid ), + .CQC_dma_rd_req_head ( CQC_dma_rd_req_head ), + .CQC_dma_rd_req_data ( CQC_dma_rd_req_data ), + .CQC_dma_rd_req_last ( CQC_dma_rd_req_last ), + .CQC_dma_rd_req_ready ( CQC_dma_rd_req_ready ), + + .CQC_dma_rd_rsp_valid ( CQC_dma_rd_rsp_valid ), + .CQC_dma_rd_rsp_head ( CQC_dma_rd_rsp_head ), + .CQC_dma_rd_rsp_data ( CQC_dma_rd_rsp_data ), + .CQC_dma_rd_rsp_last ( CQC_dma_rd_rsp_last ), + .CQC_dma_rd_rsp_ready ( CQC_dma_rd_rsp_ready ), + + .CQC_dma_wr_req_valid ( CQC_dma_wr_req_valid ), + .CQC_dma_wr_req_head ( CQC_dma_wr_req_head ), + .CQC_dma_wr_req_data ( CQC_dma_wr_req_data ), + .CQC_dma_wr_req_last ( CQC_dma_wr_req_last ), + .CQC_dma_wr_req_ready ( CQC_dma_wr_req_ready ), + + .EQC_dma_rd_req_valid ( EQC_dma_rd_req_valid ), + .EQC_dma_rd_req_head ( EQC_dma_rd_req_head ), + .EQC_dma_rd_req_data ( EQC_dma_rd_req_data ), + .EQC_dma_rd_req_last ( EQC_dma_rd_req_last ), + .EQC_dma_rd_req_ready ( EQC_dma_rd_req_ready ), + + .EQC_dma_rd_rsp_valid ( EQC_dma_rd_rsp_valid ), + .EQC_dma_rd_rsp_head ( EQC_dma_rd_rsp_head ), + .EQC_dma_rd_rsp_data ( EQC_dma_rd_rsp_data ), + .EQC_dma_rd_rsp_last ( EQC_dma_rd_rsp_last ), + .EQC_dma_rd_rsp_ready ( EQC_dma_rd_rsp_ready ), + + .EQC_dma_wr_req_valid ( EQC_dma_wr_req_valid ), + .EQC_dma_wr_req_head ( EQC_dma_wr_req_head ), + .EQC_dma_wr_req_data ( EQC_dma_wr_req_data ), + .EQC_dma_wr_req_last ( EQC_dma_wr_req_last ), + .EQC_dma_wr_req_ready ( EQC_dma_wr_req_ready ), + + .MPT_dma_rd_req_valid ( MPT_dma_rd_req_valid ), + .MPT_dma_rd_req_head ( MPT_dma_rd_req_head ), + .MPT_dma_rd_req_data ( MPT_dma_rd_req_data ), + .MPT_dma_rd_req_last ( MPT_dma_rd_req_last ), + .MPT_dma_rd_req_ready ( MPT_dma_rd_req_ready ), + + .MPT_dma_rd_rsp_valid ( MPT_dma_rd_rsp_valid ), + .MPT_dma_rd_rsp_head ( MPT_dma_rd_rsp_head ), + .MPT_dma_rd_rsp_data ( MPT_dma_rd_rsp_data ), + .MPT_dma_rd_rsp_last ( MPT_dma_rd_rsp_last ), + .MPT_dma_rd_rsp_ready ( MPT_dma_rd_rsp_ready ), + + .MPT_dma_wr_req_valid ( MPT_dma_wr_req_valid ), + .MPT_dma_wr_req_head ( MPT_dma_wr_req_head ), + .MPT_dma_wr_req_data ( MPT_dma_wr_req_data ), + .MPT_dma_wr_req_last ( MPT_dma_wr_req_last ), + .MPT_dma_wr_req_ready ( MPT_dma_wr_req_ready ), + + .MTT_dma_rd_req_valid ( MTT_dma_rd_req_valid ), + .MTT_dma_rd_req_head ( MTT_dma_rd_req_head ), + .MTT_dma_rd_req_data ( MTT_dma_rd_req_data ), + .MTT_dma_rd_req_last ( MTT_dma_rd_req_last ), + .MTT_dma_rd_req_ready ( MTT_dma_rd_req_ready ), + + .MTT_dma_rd_rsp_valid ( MTT_dma_rd_rsp_valid ), + .MTT_dma_rd_rsp_head ( MTT_dma_rd_rsp_head ), + .MTT_dma_rd_rsp_data ( MTT_dma_rd_rsp_data ), + .MTT_dma_rd_rsp_last ( MTT_dma_rd_rsp_last ), + .MTT_dma_rd_rsp_ready ( MTT_dma_rd_rsp_ready ), + + .MTT_dma_wr_req_valid ( MTT_dma_wr_req_valid ), + .MTT_dma_wr_req_head ( MTT_dma_wr_req_head ), + .MTT_dma_wr_req_data ( MTT_dma_wr_req_data ), + .MTT_dma_wr_req_last ( MTT_dma_wr_req_last ), + .MTT_dma_wr_req_ready ( MTT_dma_wr_req_ready ) +); + +RPCSubsystem #( + .INGRESS_CXT_HEAD_WIDTH ( INGRESS_CXT_HEAD_WIDTH ), + .INGRESS_CXT_DATA_WIDTH ( INGRESS_CXT_DATA_WIDTH ), + .EGRESS_CXT_HEAD_WIDTH ( EGRESS_CXT_HEAD_WIDTH ), + .EGRESS_CXT_DATA_WIDTH ( EGRESS_CXT_DATA_WIDTH ), + + .INGRESS_MR_HEAD_WIDTH ( INGRESS_MR_HEAD_WIDTH ), + .INGRESS_MR_DATA_WIDTH ( INGRESS_MR_DATA_WIDTH ), + .EGRESS_MR_HEAD_WIDTH ( EGRESS_MR_HEAD_WIDTH ), + .EGRESS_MR_DATA_WIDTH ( EGRESS_MR_DATA_WIDTH ) +) +RPCSubsystem_Inst +( + .clk ( user_clk ), + .rst ( user_rst ), + + .TX_REQ_sub_wqe_valid ( TX_REQ_sub_wqe_valid ), + .TX_REQ_sub_wqe_meta ( TX_REQ_sub_wqe_meta ), + .TX_REQ_sub_wqe_ready ( TX_REQ_sub_wqe_ready ), + + .TX_REQ_cq_req_valid ( TX_REQ_cq_req_valid ), + .TX_REQ_cq_req_head ( TX_REQ_cq_req_head ), + .TX_REQ_cq_req_ready ( TX_REQ_cq_req_ready ), + + .TX_REQ_cq_resp_valid ( TX_REQ_cq_resp_valid ), + .TX_REQ_cq_resp_head ( TX_REQ_cq_resp_head ), + .TX_REQ_cq_resp_ready ( TX_REQ_cq_resp_ready ), + + .TX_REQ_eq_req_valid ( TX_REQ_eq_req_valid ), + .TX_REQ_eq_req_head ( TX_REQ_eq_req_head ), + .TX_REQ_eq_req_ready ( TX_REQ_eq_req_ready ), + + .TX_REQ_eq_resp_valid ( TX_REQ_eq_resp_valid ), + .TX_REQ_eq_resp_head ( TX_REQ_eq_resp_head ), + .TX_REQ_eq_resp_ready ( TX_REQ_eq_resp_ready ), + + .RQ_wqe_req_valid ( RQ_wqe_req_valid ), + .RQ_wqe_req_head ( RQ_wqe_req_head ), + .RQ_wqe_req_start ( RQ_wqe_req_start ), + .RQ_wqe_req_last ( RQ_wqe_req_last ), + .RQ_wqe_req_ready ( RQ_wqe_req_ready ), + + .RQ_wqe_resp_valid ( RQ_wqe_resp_valid ), + .RQ_wqe_resp_head ( RQ_wqe_resp_head ), + .RQ_wqe_resp_data ( RQ_wqe_resp_data ), + .RQ_wqe_resp_start ( RQ_wqe_resp_start ), + .RQ_wqe_resp_last ( RQ_wqe_resp_last ), + .RQ_wqe_resp_ready ( RQ_wqe_resp_ready ), + + .RQ_cache_offset_wen ( RQ_cache_offset_wen ), + .RQ_cache_offset_addr ( RQ_cache_offset_addr ), + .RQ_cache_offset_din ( RQ_cache_offset_din ), + .RQ_cache_offset_dout ( RQ_cache_offset_dout ), + + .RQ_offset_wen ( RQ_offset_wen ), + .RQ_offset_addr ( RQ_offset_addr ), + .RQ_offset_din ( RQ_offset_din ), + .RQ_offset_dout ( RQ_offset_dout ), + + .RQ_cache_owned_wen ( RQ_cache_owned_wen ), + .RQ_cache_owned_addr ( RQ_cache_owned_addr ), + .RQ_cache_owned_din ( RQ_cache_owned_din ), + .RQ_cache_owned_dout ( RQ_cache_owned_dout ), + + .RX_REQ_cq_req_valid ( RX_REQ_cq_req_valid ), + .RX_REQ_cq_req_head ( RX_REQ_cq_req_head ), + .RX_REQ_cq_req_ready ( RX_REQ_cq_req_ready ), + + .RX_REQ_cq_resp_valid ( RX_REQ_cq_resp_valid ), + .RX_REQ_cq_resp_head ( RX_REQ_cq_resp_head ), + .RX_REQ_cq_resp_ready ( RX_REQ_cq_resp_ready ), + + .RX_REQ_eq_req_valid ( RX_REQ_eq_req_valid ), + .RX_REQ_eq_req_head ( RX_REQ_eq_req_head ), + .RX_REQ_eq_req_ready ( RX_REQ_eq_req_ready ), + + .RX_REQ_eq_resp_valid ( RX_REQ_eq_resp_valid ), + .RX_REQ_eq_resp_head ( RX_REQ_eq_resp_head ), + .RX_REQ_eq_resp_ready ( RX_REQ_eq_resp_ready ), + + .RX_RESP_cq_req_valid ( RX_RESP_cq_req_valid ), + .RX_RESP_cq_req_head ( RX_RESP_cq_req_head ), + .RX_RESP_cq_req_ready ( RX_RESP_cq_req_ready ), + + .RX_RESP_cq_resp_valid ( RX_RESP_cq_resp_valid ), + .RX_RESP_cq_resp_head ( RX_RESP_cq_resp_head ), + .RX_RESP_cq_resp_ready ( RX_RESP_cq_resp_ready ), + + .RX_RESP_eq_req_valid ( RX_RESP_eq_req_valid ), + .RX_RESP_eq_req_head ( RX_RESP_eq_req_head ), + .RX_RESP_eq_req_ready ( RX_RESP_eq_req_ready ), + + .RX_RESP_eq_resp_valid ( RX_RESP_eq_resp_valid ), + .RX_RESP_eq_resp_head ( RX_RESP_eq_resp_head ), + .RX_RESP_eq_resp_ready ( RX_RESP_eq_resp_ready ), + + .TX_REQ_fetch_cxt_ingress_valid ( TX_REQ_fetch_cxt_ingress_valid ), + .TX_REQ_fetch_cxt_ingress_head ( TX_REQ_fetch_cxt_ingress_head ), + .TX_REQ_fetch_cxt_ingress_data ( TX_REQ_fetch_cxt_ingress_data ), + .TX_REQ_fetch_cxt_ingress_start ( TX_REQ_fetch_cxt_ingress_start ), + .TX_REQ_fetch_cxt_ingress_last ( TX_REQ_fetch_cxt_ingress_last ), + .TX_REQ_fetch_cxt_ingress_ready ( TX_REQ_fetch_cxt_ingress_ready ), + + .TX_REQ_fetch_cxt_egress_valid ( TX_REQ_fetch_cxt_egress_valid ), + .TX_REQ_fetch_cxt_egress_head ( TX_REQ_fetch_cxt_egress_head ), + .TX_REQ_fetch_cxt_egress_data ( TX_REQ_fetch_cxt_egress_data ), + .TX_REQ_fetch_cxt_egress_start ( TX_REQ_fetch_cxt_egress_start ), + .TX_REQ_fetch_cxt_egress_last ( TX_REQ_fetch_cxt_egress_last ), + .TX_REQ_fetch_cxt_egress_ready ( TX_REQ_fetch_cxt_egress_ready ), + + .RX_REQ_fetch_cxt_ingress_valid ( RX_REQ_fetch_cxt_ingress_valid ), + .RX_REQ_fetch_cxt_ingress_head ( RX_REQ_fetch_cxt_ingress_head ), + .RX_REQ_fetch_cxt_ingress_data ( RX_REQ_fetch_cxt_ingress_data ), + .RX_REQ_fetch_cxt_ingress_start ( RX_REQ_fetch_cxt_ingress_start ), + .RX_REQ_fetch_cxt_ingress_last ( RX_REQ_fetch_cxt_ingress_last ), + .RX_REQ_fetch_cxt_ingress_ready ( RX_REQ_fetch_cxt_ingress_ready ), + + .RX_REQ_fetch_cxt_egress_valid ( RX_REQ_fetch_cxt_egress_valid ), + .RX_REQ_fetch_cxt_egress_head ( RX_REQ_fetch_cxt_egress_head ), + .RX_REQ_fetch_cxt_egress_data ( RX_REQ_fetch_cxt_egress_data ), + .RX_REQ_fetch_cxt_egress_start ( RX_REQ_fetch_cxt_egress_start ), + .RX_REQ_fetch_cxt_egress_last ( RX_REQ_fetch_cxt_egress_last ), + .RX_REQ_fetch_cxt_egress_ready ( RX_REQ_fetch_cxt_egress_ready ), + + .RX_RESP_fetch_cxt_ingress_valid ( RX_RESP_fetch_cxt_ingress_valid ), + .RX_RESP_fetch_cxt_ingress_head ( RX_RESP_fetch_cxt_ingress_head ), + .RX_RESP_fetch_cxt_ingress_data ( RX_RESP_fetch_cxt_ingress_data ), + .RX_RESP_fetch_cxt_ingress_start ( RX_RESP_fetch_cxt_ingress_start ), + .RX_RESP_fetch_cxt_ingress_last ( RX_RESP_fetch_cxt_ingress_last ), + .RX_RESP_fetch_cxt_ingress_ready ( RX_RESP_fetch_cxt_ingress_ready ), + + .RX_RESP_fetch_cxt_egress_valid ( RX_RESP_fetch_cxt_egress_valid ), + .RX_RESP_fetch_cxt_egress_head ( RX_RESP_fetch_cxt_egress_head ), + .RX_RESP_fetch_cxt_egress_data ( RX_RESP_fetch_cxt_egress_data ), + .RX_RESP_fetch_cxt_egress_start ( RX_RESP_fetch_cxt_egress_start ), + .RX_RESP_fetch_cxt_egress_last ( RX_RESP_fetch_cxt_egress_last ), + .RX_RESP_fetch_cxt_egress_ready ( RX_RESP_fetch_cxt_egress_ready ), + + .TX_REQ_fetch_mr_ingress_valid ( TX_REQ_fetch_mr_ingress_valid ), + .TX_REQ_fetch_mr_ingress_head ( TX_REQ_fetch_mr_ingress_head ), + .TX_REQ_fetch_mr_ingress_data ( TX_REQ_fetch_mr_ingress_data ), + .TX_REQ_fetch_mr_ingress_start ( TX_REQ_fetch_mr_ingress_start ), + .TX_REQ_fetch_mr_ingress_last ( TX_REQ_fetch_mr_ingress_last ), + .TX_REQ_fetch_mr_ingress_ready ( TX_REQ_fetch_mr_ingress_ready ), + + .TX_REQ_fetch_mr_egress_valid ( TX_REQ_fetch_mr_egress_valid ), + .TX_REQ_fetch_mr_egress_head ( TX_REQ_fetch_mr_egress_head ), + .TX_REQ_fetch_mr_egress_data ( TX_REQ_fetch_mr_egress_data ), + .TX_REQ_fetch_mr_egress_start ( TX_REQ_fetch_mr_egress_start ), + .TX_REQ_fetch_mr_egress_last ( TX_REQ_fetch_mr_egress_last ), + .TX_REQ_fetch_mr_egress_ready ( TX_REQ_fetch_mr_egress_ready ), + + .RX_RESP_fetch_mr_ingress_valid ( RX_RESP_fetch_mr_ingress_valid ), + .RX_RESP_fetch_mr_ingress_head ( RX_RESP_fetch_mr_ingress_head ), + .RX_RESP_fetch_mr_ingress_data ( RX_RESP_fetch_mr_ingress_data ), + .RX_RESP_fetch_mr_ingress_start ( RX_RESP_fetch_mr_ingress_start ), + .RX_RESP_fetch_mr_ingress_last ( RX_RESP_fetch_mr_ingress_last ), + .RX_RESP_fetch_mr_ingress_ready ( RX_RESP_fetch_mr_ingress_ready ), + + .RX_RESP_fetch_mr_egress_valid ( RX_RESP_fetch_mr_egress_valid ), + .RX_RESP_fetch_mr_egress_head ( RX_RESP_fetch_mr_egress_head ), + .RX_RESP_fetch_mr_egress_data ( RX_RESP_fetch_mr_egress_data ), + .RX_RESP_fetch_mr_egress_start ( RX_RESP_fetch_mr_egress_start ), + .RX_RESP_fetch_mr_egress_last ( RX_RESP_fetch_mr_egress_last ), + .RX_RESP_fetch_mr_egress_ready ( RX_RESP_fetch_mr_egress_ready ), + + .RX_REQ_fetch_mr_ingress_valid ( RX_REQ_fetch_mr_ingress_valid ), + .RX_REQ_fetch_mr_ingress_head ( RX_REQ_fetch_mr_ingress_head ), + .RX_REQ_fetch_mr_ingress_data ( RX_REQ_fetch_mr_ingress_data ), + .RX_REQ_fetch_mr_ingress_start ( RX_REQ_fetch_mr_ingress_start ), + .RX_REQ_fetch_mr_ingress_last ( RX_REQ_fetch_mr_ingress_last ), + .RX_REQ_fetch_mr_ingress_ready ( RX_REQ_fetch_mr_ingress_ready ), + + .RX_REQ_fetch_mr_egress_valid ( RX_REQ_fetch_mr_egress_valid ), + .RX_REQ_fetch_mr_egress_head ( RX_REQ_fetch_mr_egress_head ), + .RX_REQ_fetch_mr_egress_data ( RX_REQ_fetch_mr_egress_data ), + .RX_REQ_fetch_mr_egress_start ( RX_REQ_fetch_mr_egress_start ), + .RX_REQ_fetch_mr_egress_last ( RX_REQ_fetch_mr_egress_last ), + .RX_REQ_fetch_mr_egress_ready ( RX_REQ_fetch_mr_egress_ready ), + + .TX_REQ_dma_wr_req_valid ( TX_REQ_dma_wr_req_valid ), + .TX_REQ_dma_wr_req_last ( TX_REQ_dma_wr_req_last ), + .TX_REQ_dma_wr_req_head ( TX_REQ_dma_wr_req_head ), + .TX_REQ_dma_wr_req_data ( TX_REQ_dma_wr_req_data ), + .TX_REQ_dma_wr_req_ready ( TX_REQ_dma_wr_req_ready ), + + .RX_REQ_dma_wr_req_valid ( RX_REQ_dma_wr_req_valid ), + .RX_REQ_dma_wr_req_last ( RX_REQ_dma_wr_req_last ), + .RX_REQ_dma_wr_req_head ( RX_REQ_dma_wr_req_head ), + .RX_REQ_dma_wr_req_data ( RX_REQ_dma_wr_req_data ), + .RX_REQ_dma_wr_req_ready ( RX_REQ_dma_wr_req_ready ), + + .RX_RESP_dma_wr_req_valid ( RX_RESP_dma_wr_req_valid ), + .RX_RESP_dma_wr_req_last ( RX_RESP_dma_wr_req_last ), + .RX_RESP_dma_wr_req_head ( RX_RESP_dma_wr_req_head ), + .RX_RESP_dma_wr_req_data ( RX_RESP_dma_wr_req_data ), + .RX_RESP_dma_wr_req_ready ( RX_RESP_dma_wr_req_ready ), + + .TX_REQ_dma_rd_req_valid ( TX_REQ_dma_rd_req_valid ), + .TX_REQ_dma_rd_req_head ( TX_REQ_dma_rd_req_head ), + .TX_REQ_dma_rd_req_data ( TX_REQ_dma_rd_req_data ), + .TX_REQ_dma_rd_req_last ( TX_REQ_dma_rd_req_last ), + .TX_REQ_dma_rd_req_ready ( TX_REQ_dma_rd_req_ready ), + + .TX_REQ_dma_rd_rsp_valid ( TX_REQ_dma_rd_rsp_valid ), + .TX_REQ_dma_rd_rsp_head ( TX_REQ_dma_rd_rsp_head ), + .TX_REQ_dma_rd_rsp_data ( TX_REQ_dma_rd_rsp_data ), + .TX_REQ_dma_rd_rsp_last ( TX_REQ_dma_rd_rsp_last ), + .TX_REQ_dma_rd_rsp_ready ( TX_REQ_dma_rd_rsp_ready ), + + .TX_RESP_dma_rd_req_valid ( TX_RESP_dma_rd_req_valid ), + .TX_RESP_dma_rd_req_head ( TX_RESP_dma_rd_req_head ), + .TX_RESP_dma_rd_req_data ( TX_RESP_dma_rd_req_data ), + .TX_RESP_dma_rd_req_last ( TX_RESP_dma_rd_req_last ), + .TX_RESP_dma_rd_req_ready ( TX_RESP_dma_rd_req_ready ), + + .TX_RESP_dma_rd_rsp_valid ( TX_RESP_dma_rd_rsp_valid ), + .TX_RESP_dma_rd_rsp_head ( TX_RESP_dma_rd_rsp_head ), + .TX_RESP_dma_rd_rsp_data ( TX_RESP_dma_rd_rsp_data ), + .TX_RESP_dma_rd_rsp_last ( TX_RESP_dma_rd_rsp_last ), + .TX_RESP_dma_rd_rsp_ready ( TX_RESP_dma_rd_rsp_ready ), + + .TX_egress_pkt_valid ( TX_egress_pkt_valid ), + .TX_egress_pkt_head ( TX_egress_pkt_head ), + .TX_egress_pkt_ready ( TX_egress_pkt_ready ), + + .TX_insert_req_valid ( TX_non_inline_insert_req_valid ), + .TX_insert_req_start ( TX_non_inline_insert_req_start ), + .TX_insert_req_last ( TX_non_inline_insert_req_last ), + .TX_insert_req_head ( TX_non_inline_insert_req_head ), + .TX_insert_req_data ( TX_non_inline_insert_req_data ), + .TX_insert_req_ready ( TX_non_inline_insert_req_ready ), + + .TX_insert_resp_valid ( TX_non_inline_insert_resp_valid ), + .TX_insert_resp_data ( TX_non_inline_insert_resp_data ), + + .RX_ingress_pkt_valid ( RX_ingress_pkt_valid ), + .RX_ingress_pkt_head ( RX_ingress_pkt_head ), + .RX_ingress_pkt_ready ( RX_ingress_pkt_ready ), + + .RX_delete_req_valid ( RX_delete_req_valid ), + .RX_delete_req_head ( RX_delete_req_head ), + .RX_delete_req_ready ( RX_delete_req_ready ), + + .RX_delete_resp_valid ( RX_delete_resp_valid ), + .RX_delete_resp_start ( RX_delete_resp_start ), + .RX_delete_resp_last ( RX_delete_resp_last ), + .RX_delete_resp_data ( RX_delete_resp_data ), + .RX_delete_resp_ready ( RX_delete_resp_ready ) +); + +TransportSubsystem TransportSubsystem_Inst( + .user_clk ( user_clk ), + .user_rst ( user_rst ), + + .mac_tx_clk ( mac_tx_clk ), + .mac_tx_rst ( mac_tx_rst ), + + .mac_rx_clk ( mac_rx_clk ), + .mac_rx_rst ( mac_rx_rst ), + +//Interface with RPCSubsystem + .TX_egress_pkt_valid ( TX_egress_pkt_valid ), + .TX_egress_pkt_head ( TX_egress_pkt_head ), + .TX_egress_pkt_ready ( TX_egress_pkt_ready ), + + .TX_insert_req_valid ( TX_insert_req_valid ), + .TX_insert_req_start ( TX_insert_req_start ), + .TX_insert_req_last ( TX_insert_req_last ), + .TX_insert_req_head ( TX_insert_req_head ), + .TX_insert_req_data ( TX_insert_req_data ), + .TX_insert_req_ready ( TX_insert_req_ready ), + + .TX_insert_resp_valid ( TX_insert_resp_valid ), + .TX_insert_resp_data ( TX_insert_resp_data ), + + .RX_ingress_pkt_valid ( RX_ingress_pkt_valid ), + .RX_ingress_pkt_head ( RX_ingress_pkt_head ), + .RX_ingress_pkt_ready ( RX_ingress_pkt_ready ), + + .RX_delete_req_valid ( RX_delete_req_valid ), + .RX_delete_req_head ( RX_delete_req_head ), + .RX_delete_req_ready ( RX_delete_req_ready ), + + .RX_delete_resp_valid ( RX_delete_resp_valid ), + .RX_delete_resp_start ( RX_delete_resp_start ), + .RX_delete_resp_last ( RX_delete_resp_last ), + .RX_delete_resp_data ( RX_delete_resp_data ), + .RX_delete_resp_ready ( RX_delete_resp_ready ), + +//Interface with MAC + .mac_tx_valid ( mac_tx_valid ), + .mac_tx_ready ( mac_tx_ready ), + .mac_tx_start ( mac_tx_start ), + .mac_tx_last ( mac_tx_last ), + .mac_tx_keep ( mac_tx_keep ), + .mac_tx_user ( mac_tx_user ), + .mac_tx_data ( mac_tx_data ), + + .mac_rx_valid ( mac_rx_valid ), + .mac_rx_ready ( mac_rx_ready ), + .mac_rx_start ( mac_rx_start ), + .mac_rx_last ( mac_rx_last ), + .mac_rx_keep ( mac_rx_keep ), + .mac_rx_user ( mac_rx_user ), + .mac_rx_data ( mac_rx_data ) +); + + +DynamicBufferInsertArbiter DynamicBufferInsertArbiter_Inst( + .clk ( user_clk ), + .rst ( user_rst ), + + .chnl_0_req_valid ( TX_non_inline_insert_req_valid ), + .chnl_0_req_start ( TX_non_inline_insert_req_start ), + .chnl_0_req_last ( TX_non_inline_insert_req_last ), + .chnl_0_req_head ( TX_non_inline_insert_req_head ), + .chnl_0_req_data ( TX_non_inline_insert_req_data ), + .chnl_0_req_ready ( TX_non_inline_insert_req_ready ), + + .chnl_0_resp_valid ( TX_non_inline_insert_resp_valid ), + .chnl_0_resp_data ( TX_non_inline_insert_resp_data ), + + .chnl_1_req_valid ( TX_inline_insert_req_valid ), + .chnl_1_req_start ( TX_inline_insert_req_start ), + .chnl_1_req_last ( TX_inline_insert_req_last ), + .chnl_1_req_head ( TX_inline_insert_req_head ), + .chnl_1_req_data ( TX_inline_insert_req_data ), + .chnl_1_req_ready ( TX_inline_insert_req_ready ), + + .chnl_1_resp_valid ( TX_inline_insert_resp_valid ), + .chnl_1_resp_data ( TX_inline_insert_resp_data ), + + .insert_req_valid ( TX_insert_req_valid ), + .insert_req_start ( TX_insert_req_start ), + .insert_req_last ( TX_insert_req_last ), + .insert_req_head ( TX_insert_req_head ), + .insert_req_data ( TX_insert_req_data ), + .insert_req_ready ( TX_insert_req_ready ), + + .insert_resp_valid ( TX_insert_resp_valid ), + .insert_resp_data ( TX_insert_resp_data ) +); + +`ifdef ILA_ON +ila_comm_res ila_comm_res_inst( + .clk ( user_clk ), + + .probe0 ( SQ_fetch_cxt_ingress_valid ), + .probe1 ( SQ_fetch_cxt_egress_valid ), + .probe2 ( TX_REQ_fetch_cxt_ingress_valid ), + .probe3 ( TX_REQ_fetch_cxt_egress_valid ), + .probe4 ( RX_REQ_fetch_cxt_ingress_valid ), + .probe5 ( RX_REQ_fetch_cxt_egress_valid ), + .probe6 ( RX_RESP_fetch_cxt_ingress_valid ), + .probe7 ( RX_RESP_fetch_cxt_egress_valid ), + .probe8 ( SQ_fetch_mr_ingress_valid ), + .probe9 ( SQ_fetch_mr_egress_valid ), + .probe10 ( RQ_fetch_mr_ingress_valid ), + .probe11 ( RQ_fetch_mr_egress_valid ), + .probe12 ( TX_REQ_fetch_mr_ingress_valid ), + .probe13 ( TX_REQ_fetch_mr_egress_valid ), + .probe14 ( RX_RESP_fetch_mr_ingress_valid ), + .probe15 ( RX_RESP_fetch_mr_egress_valid ), + .probe16 ( RX_REQ_fetch_mr_ingress_valid ), + .probe17 ( RX_REQ_fetch_mr_egress_valid ) +); +`endif +/*------------------------------------------- Submodules Instatiation : End -----------------------------------------*/ + + +/*------------------------------------------- State Machine Definition : Begin --------------------------------------*/ +/*------------------------------------------- State Machine Definition : End ----------------------------------------*/ + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ +/*------------------------------------------- Variables Decode : End ------------------------------------------------*/ + +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/TransportSubsystem/InOrderCommit.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/TransportSubsystem/InOrderCommit.v new file mode 100644 index 0000000000000000000000000000000000000000..cb5eda251315d1d02f761feaa6bcbe2f5f80217a --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/TransportSubsystem/InOrderCommit.v @@ -0,0 +1,235 @@ +/*------------------------------------------- Module Description : Begin ---------------------------------------------- +Name: InOrderCommit +Author: YangFan +Function: Commit packet in-order. + This thread is triggered by metadata passed from OutOfOrderAccept. It iterates from the start PSN in the metadata, + commits the PSN-continuous packets in the packet buffer until there is a "hole" in the PSN range. +--------------------------------------------- Module Decription : End -----------------------------------------------*/ + +/*------------------------------------------- Timescale Definition : Begin ------------------------------------------*/ +`timescale 1ns / 1ps +/*------------------------------------------- Timescale Definition : End --------------------------------------------*/ + +/*------------------------------------------- Included Files : Begin ------------------------------------------------*/ +`include "ib_constant_def_h.vh" +`include "common_function_def.vh" +`include "transport_subsystem_def.vh" +`include "global_def.vh" +/*------------------------------------------- Included Files : End --------------------------------------------------*/ + +/*------------------------------------------- Input/Output Definition : Begin ---------------------------------------*/ +module InOrderCommit ( + input wire clk, + input wire rst, + +//Metadata from OutOfOrderAccept + input wire i_pkt_meta_empty, + input wire [`PKT_META_WIDTH - 1 : 0] iv_pkt_meta_dout, + output wire o_pkt_meta_rd_en, + + //Delete Packet + output wire o_delete_req_valid, + output wire [`QP_NUM_LOG + `PSN_WIDTH + `RECV_BUFFER_SLOT_NUM_LOG - 1 : 0] ov_delete_req_head, + input wire i_delete_req_ready, + + input wire i_delete_resp_valid, + input wire [`PKT_HEAD_WIDTH - 1 : 0] iv_delete_resp_head, + input wire [`PKT_DATA_WIDTH - 1 : 0] iv_delete_resp_data, + input wire i_delete_resp_start, + input wire i_delete_resp_last, + output wire o_delete_resp_ready, + + //Find a Packet + output wire o_find_req_valid, + output wire [`QP_NUM_LOG + `PSN_WIDTH - 1 : 0] ov_find_req_head, + input wire i_find_resp_valid, + input wire [`PKT_SLOT_NUM_LOG + `RECV_BUFFER_SLOT_NUM_LOG : 0] iv_find_resp_data, + + //EPSN control + output wire [`QP_NUM_LOG - 1 : 0] ov_epsn_rd_index, + input wire [`PSN_WIDTH - 1 : 0] iv_epsn_rd_data, + output wire o_epsn_wr_en, + output wire [`QP_NUM_LOG - 1 : 0] ov_epsn_wr_index, + output wire [`PSN_WIDTH - 1 : 0] ov_epsn_wr_data, + +//Interface with ULP + output wire o_commit_valid, + output wire [`PKT_HEAD_WIDTH - 1 : 0] ov_commit_head, + output wire [`PKT_DATA_WIDTH - 1 : 0] ov_commit_data, + output wire o_commit_start, + output wire o_commit_last, + input wire i_commit_ready +); +/*------------------------------------------- Input/Output Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Variables Definition : Begin ------------------------------------*/ +wire [23:0] wv_qpn; +wire [23:0] wv_commit_lower_bound; +wire [23:0] wv_commit_upper_bound; + +reg [23:0] qv_qpn; +reg [23:0] qv_curPSN; +reg [23:0] qv_commit_lower_bound; +reg [23:0] qv_commit_upper_bound; + +reg q_delete_start; + +/*------------------------------------------- Local Variables Definition : End --------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : Begin ---------------------------------------*/ +//NULL +/*------------------------------------------- Submodules Instatiation : End -----------------------------------------*/ + +/*------------------------------------------- State Machine Definition : Begin --------------------------------------*/ +reg [2:0] ioc_cur_state; +reg [2:0] ioc_next_state; + +parameter [2:0] IOC_IDLE_s = 3'd1, + IOC_COMMIT_s = 3'd2; + +always @(posedge clk or posedge rst) begin + if(rst) begin + ioc_cur_state <= IOC_IDLE_s; + end + else begin + ioc_cur_state <= ioc_next_state; + end +end + +always @(*) begin + case(ioc_cur_state) + IOC_IDLE_s: if(!i_pkt_meta_empty) begin + ioc_next_state = IOC_COMMIT_s; + end + else begin + ioc_next_state = IOC_IDLE_s; + end + IOC_COMMIT_s: if(i_delete_resp_valid && i_delete_resp_last && i_commit_ready) begin + if(qv_curPSN == qv_commit_upper_bound) begin + ioc_next_state = IOC_IDLE_s; + end + else begin + ioc_next_state = IOC_COMMIT_s; + end + end + else begin + ioc_next_state = IOC_COMMIT_s; + end + default: ioc_next_state = IOC_IDLE_s; + endcase +end + +/*------------------------------------------- State Machine Definition : End ----------------------------------------*/ + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ +//-- wv_qpn -- +assign wv_qpn = iv_pkt_meta_dout[`META_QPN_OFFSET]; + +//-- wv_commit_lower_bound -- +assign wv_commit_lower_bound = iv_pkt_meta_dout[`META_LOWER_BOUND_OFFSET]; + +//-- wv_commit_upper_bound -- +assign wv_commit_upper_bound = iv_pkt_meta_dout[`META_UPPER_BOUND_OFFSET]; + +//-- qv_qpn -- +//-- qv_commit_lower_bound -- +//-- qv_commit_upper_bound -- +always @(posedge clk or posedge rst) begin + if(rst) begin + qv_qpn <= 'd0; + qv_commit_lower_bound <= 'd0; + end + else if(ioc_cur_state == IOC_IDLE_s && !i_pkt_meta_empty) begin + qv_qpn <= wv_qpn; + qv_commit_lower_bound <= wv_commit_lower_bound; + qv_commit_upper_bound <= wv_commit_upper_bound; + end + else begin + qv_qpn <= wv_qpn; + qv_commit_lower_bound <= qv_commit_lower_bound; + qv_commit_upper_bound <= qv_commit_upper_bound; + end +end + +//-- qv_curPSN -- +always @(posedge clk or posedge rst) begin + if(rst) begin + qv_curPSN <= 'd0; + end + else if(ioc_cur_state == IOC_IDLE_s && !i_pkt_meta_empty) begin + qv_curPSN <= wv_commit_lower_bound; + end + else if(ioc_cur_state == IOC_COMMIT_s && i_delete_resp_last && i_commit_ready) begin + qv_curPSN <= (qv_curPSN < qv_commit_upper_bound) ? qv_curPSN + 1 : 'd0; + end + else begin + qv_curPSN <= qv_curPSN; + end +end + +//-- q_delete_start -- +always @(posedge clk or posedge rst) begin + if(rst) begin + q_delete_start <= 'd0; + end + else if(ioc_cur_state == IOC_IDLE_s && !i_pkt_meta_empty) begin + q_delete_start <= 'd1; + end + else if(ioc_cur_state == IOC_COMMIT_s && q_delete_start) begin + q_delete_start <= 'd0; + end + else if(ioc_cur_state == IOC_COMMIT_s && i_delete_resp_last && i_commit_ready) begin + q_delete_start <= (ioc_next_state != IOC_IDLE_s) ? 'd1 : 'd0; + end + else begin + q_delete_start <= q_delete_start; + end +end + +//-- o_pkt_meta_rd_en -- +assign o_pkt_meta_rd_en = (ioc_cur_state != IOC_IDLE_s && ioc_next_state == IOC_IDLE_s) && !i_pkt_meta_empty; + +//-- o_delete_req_valid -- +assign o_delete_req_valid = q_delete_start; + +//-- ov_delete_req_head -- +assign ov_delete_req_head = q_delete_start ? {qv_curPSN, qv_qpn} : 'd0; + +//-- o_delete_resp_ready -- +assign o_delete_resp_ready = i_commit_ready; + +//-- o_commit_valid -- +assign o_commit_valid = (ioc_cur_state == IOC_COMMIT_s) && i_delete_resp_valid; + +//-- ov_commit_head -- +assign ov_commit_head = (ioc_cur_state == IOC_COMMIT_s) && i_delete_resp_valid && i_delete_resp_start ? {'d0, iv_delete_resp_head[247:8], iv_delete_resp_head[7:0] - 8'd3} : 'd0; //Remove PSN + +//-- ov_commit_data -- +assign ov_commit_data = (ioc_cur_state == IOC_COMMIT_s) ? iv_delete_resp_data : 'd0; + +//-- o_commit_start -- +assign o_commit_start = (ioc_cur_state == IOC_COMMIT_s) ? i_delete_resp_start : 'd0; + +//-- o_commit_last -- +assign o_commit_last = (ioc_cur_state == IOC_COMMIT_s) ? i_delete_resp_last : 'd0; + +//-- ov_epsn_rd_index -- +assign ov_epsn_rd_index = 'd0; + +//-- o_epsn_wr_en -- +assign o_epsn_wr_en = 'd0; + +//-- ov_epsn_wr_index -- +assign ov_epsn_wr_index = 'd0; + +//-- ov_epsn_wr_data -- +assign ov_epsn_wr_data = 'd0; + +//-- o_find_req_valid -- +assign o_find_req_valid = 'd0; + +//-- ov_find_req_head -- +assign ov_find_req_head = 'd0; + +/*------------------------------------------- Variables Decode : End ------------------------------------------------*/ +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/TransportSubsystem/InOrderInject.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/TransportSubsystem/InOrderInject.v new file mode 100644 index 0000000000000000000000000000000000000000..d5238245d7a5bade1ccea30b6d51e66eaaea38ec --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/TransportSubsystem/InOrderInject.v @@ -0,0 +1,314 @@ +/*------------------------------------------- Module Description : Begin ---------------------------------------------- +Name: InOrderInject +Author: YangFan +Function: Send Packet from ULP. + Transport subsystem does not care about packet type(RC/UC/UD req/resp), it focuses on packet order. +--------------------------------------------- Module Decription : End -----------------------------------------------*/ + +/*------------------------------------------- Timescale Definition : Begin ------------------------------------------*/ +`timescale 1ns / 1ps +/*------------------------------------------- Timescale Definition : End --------------------------------------------*/ + +/*------------------------------------------- Included Files : Begin ------------------------------------------------*/ +`include "ib_constant_def_h.vh" +`include "common_function_def.vh" +`include "transport_subsystem_def.vh" +`include "global_def.vh" +/*------------------------------------------- Included Files : End --------------------------------------------------*/ + +/*------------------------------------------- Input/Output Definition : Begin ---------------------------------------*/ +module InOrderInject ( + input wire clk, + input wire rst, + +//Packet-In + input wire i_packet_in_valid, + input wire [`PKT_HEAD_WIDTH - 1 : 0] iv_packet_in_head, + input wire [`PKT_DATA_WIDTH - 1 : 0] iv_packet_in_data, + input wire i_packet_in_start, + input wire i_packet_in_last, + output reg o_packet_in_ready, + +//NPSN control + output reg o_npsn_wr_en, + output reg [`QP_NUM_LOG - 1 : 0] ov_npsn_wr_index, + output reg [`PSN_WIDTH - 1 : 0] ov_npsn_wr_data, + output wire [`QP_NUM_LOG - 1 : 0] ov_npsn_rd_index, + input wire [`PSN_WIDTH - 1 : 0] iv_npsn_rd_data, + +//Interface with SendBufferMgt(Enqueue Packet) + //No need for ready signal + input wire [`SEND_BUFFER_SLOT_NUM_LOG - 1 : 0] iv_available_slot_num, + output reg o_insert_req_valid, + output reg [`PKT_HEAD_WIDTH - 1 : 0] ov_insert_req_head, + output reg [`PKT_DATA_WIDTH - 1 : 0] ov_insert_req_data, + output reg o_insert_req_start, + output reg o_insert_req_last, + input wire i_insert_req_ready, + +//Interface with TimerControl + output reg o_tc_wr_en, + output reg [`TIMER_CMD_WIDTH - 1 : 0] ov_tc_din, + input wire i_tc_prog_full, + +//Packet-Out + output reg o_packet_out_valid, + output reg [`PKT_HEAD_WIDTH - 1 : 0] ov_packet_out_head, + output reg [`PKT_DATA_WIDTH - 1 : 0] ov_packet_out_data, + output reg o_packet_out_start, + output reg o_packet_out_last, + input wire i_packet_out_ready + +); +/*------------------------------------------- Input/Output Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Variables Definition : Begin ------------------------------------*/ +wire [31:0] wv_payload_len; +wire [2:0] wv_service_type; + +reg [23:0] qv_qpn; +wire [31:0] wv_slot_required; +reg [31:0] qv_slot_required; + +reg q_insert_header; + +/*------------------------------------------- Local Variables Definition : End --------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : Begin ---------------------------------------*/ +//Null +/*------------------------------------------- Submodules Instatiation : End -----------------------------------------*/ + + +/*------------------------------------------- State Machine Definition : Begin --------------------------------------*/ +reg [2:0] ioi_cur_state; +reg [2:0] ioi_next_state; + +parameter [2:0] IOI_IDLE_s = 4'd1, + IOI_UNRELIABLE_s = 4'd2, + IOI_RELIABLE_s = 4'd3; + +always @(posedge clk or posedge rst) begin + if(rst) begin + ioi_cur_state <= IOI_IDLE_s; + end + else begin + ioi_cur_state <= ioi_next_state; + end +end + +always @(*) begin + case(ioi_cur_state) + IOI_IDLE_s: if(i_packet_in_valid) begin + if(wv_service_type == `RC && (wv_slot_required <= iv_available_slot_num)) begin + ioi_next_state = IOI_RELIABLE_s; + end + else if(wv_service_type == `UC || wv_service_type == `UD) begin + ioi_next_state = IOI_UNRELIABLE_s; + end + else begin + ioi_next_state = IOI_IDLE_s; + end + end + else begin + ioi_next_state = IOI_IDLE_s; + end + IOI_UNRELIABLE_s: if(i_packet_in_valid && i_packet_in_last && i_packet_out_ready) begin + ioi_next_state = IOI_IDLE_s; + end + else begin + ioi_next_state = IOI_UNRELIABLE_s; + end + IOI_RELIABLE_s: if(i_packet_in_valid && i_packet_in_last && i_packet_out_ready && !i_tc_prog_full) begin + ioi_next_state = IOI_IDLE_s; + end + else begin + ioi_next_state = IOI_RELIABLE_s; + end + default: ioi_next_state = IOI_IDLE_s; + endcase +end + +/*------------------------------------------- State Machine Definition : End ----------------------------------------*/ + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ +//-- wv_payload_len -- +assign wv_payload_len = iv_packet_in_head[`PAYLOAD_LENGTH_OFFSET]; + +//-- wv_slot_required -- +assign wv_slot_required = (wv_payload_len[5:0] ? (wv_payload_len >> 6) + 1 : (wv_payload_len >> 6)) + 'd1; //+1 for packet header + +//-- wv_service_type -- +assign wv_service_type = iv_packet_in_head[`SERVICE_TYPE_OFFSET]; + +//-- qv_qpn -- +always @(posedge clk or posedge rst) begin + if(rst) begin + qv_qpn <= 'd0; + end + else if(ioi_cur_state == IOI_IDLE_s) begin + qv_qpn <= i_packet_in_valid ? iv_packet_in_head[`QPN_OFFSET] : 'd0; + end + else begin + qv_qpn <= qv_qpn; + end +end + +//-- qv_slot_required -- +always @(posedge clk or posedge rst) begin + if(rst) begin + qv_slot_required <= 'd0; + end + else if(ioi_cur_state == IOI_IDLE_s && i_packet_in_valid) begin + qv_slot_required <= (wv_service_type == `RC) ? wv_slot_required : 'd0; //+1 to store packet header + end + else if(ioi_cur_state == IOI_RELIABLE_s && (qv_slot_required <= iv_available_slot_num) && i_packet_in_valid && o_packet_in_ready) begin + qv_slot_required <= (qv_slot_required > 0) ? qv_slot_required - 'd1 : 'd0; + end + else begin + qv_slot_required <= qv_slot_required; + end +end + +//-- q_insert_header -- +always @(posedge clk or posedge rst) begin + if(rst) begin + q_insert_header <= 'd0; + end + else if(ioi_cur_state == IOI_IDLE_s && i_packet_in_valid && (wv_service_type == `RC) && (wv_slot_required <= iv_available_slot_num)) begin + q_insert_header <= 'd1; + end + else if(ioi_cur_state == IOI_RELIABLE_s && q_insert_header && i_insert_req_ready) begin + q_insert_header <= 'd0; + end + else begin + q_insert_header <= q_insert_header; + end +end + +//-- o_packet_in_ready -- +always @(*) begin + if(rst) begin + o_packet_in_ready = 'd0; + end + else if(ioi_cur_state == IOI_UNRELIABLE_s) begin + o_packet_in_ready = i_packet_out_ready; + end + else if(ioi_cur_state == IOI_RELIABLE_s) begin + if(q_insert_header) begin + o_packet_in_ready = 'd0; + end + else if(i_packet_in_last) begin + o_packet_in_ready = !i_tc_prog_full && i_packet_out_ready && i_insert_req_ready; + end + else begin + o_packet_in_ready = i_packet_out_ready && i_insert_req_ready; + end + end + else begin + o_packet_in_ready = 'd0; + end +end + + +//-- o_npsn_wr_en -- +//-- ov_npsn_wr_index -- +//-- ov_npsn_wr_data -- +always @(*) begin + if(rst) begin + o_npsn_wr_en = 'd0; + ov_npsn_wr_index = 'd0; + ov_npsn_wr_data = 'd0; + end + else if((ioi_cur_state == IOI_UNRELIABLE_s || ioi_cur_state == IOI_RELIABLE_s) && i_packet_in_valid && i_packet_in_last && i_packet_out_ready && !i_tc_prog_full) begin + o_npsn_wr_en = 'd1; + ov_npsn_wr_index = qv_qpn; + ov_npsn_wr_data = iv_npsn_rd_data + 'd1; + end + else begin + o_npsn_wr_en = 'd0; + ov_npsn_wr_index = 'd0; + ov_npsn_wr_data = 'd0; + end +end + +//-- ov_npsn_rd_index -- +assign ov_npsn_rd_index = (ioi_cur_state == IOI_IDLE_s) ? iv_packet_in_head[`SRC_QPN_OFFSET] : qv_qpn; + +//-- o_insert_req_valid -- +//-- ov_insert_req_head -- +//-- ov_insert_req_data -- +//-- o_insert_req_start -- +//-- o_insert_req_last -- +always @(*) begin + if(rst) begin + o_insert_req_valid = 'd0; + ov_insert_req_head = 'd0; + ov_insert_req_data = 'd0; + o_insert_req_start = 'd0; + o_insert_req_last = 'd0; + end + else if(ioi_cur_state == IOI_RELIABLE_s) begin + o_insert_req_valid = q_insert_header ? i_packet_in_valid : (i_packet_in_valid && i_packet_out_ready && i_insert_req_ready); + ov_insert_req_head = q_insert_header ? {qv_slot_required, iv_npsn_rd_data, qv_qpn} : 'd0; + ov_insert_req_data = q_insert_header ? {240'd0, (iv_npsn_rd_data), iv_packet_in_head[247:8], iv_packet_in_head[7:0] + 8'd3} : iv_packet_in_data; + o_insert_req_start = q_insert_header ? i_packet_in_start : 'd0; + o_insert_req_last = q_insert_header ? 'd0 : i_packet_in_last; + end + else begin + o_insert_req_valid = 'd0; + ov_insert_req_head = 'd0; + ov_insert_req_data = 'd0; + o_insert_req_start = 'd0; + o_insert_req_last = 'd0; + end +end + +//-- o_tc_wr_en -- +//-- ov_tc_din -- +always @(posedge clk or posedge rst) begin + if(rst) begin + o_tc_wr_en <= 'd0; + ov_tc_din <= 'd0; + end + else if((ioi_cur_state == IOI_RELIABLE_s) && i_packet_in_valid && i_packet_in_last) begin + o_tc_wr_en <= 'd1; + ov_tc_din <= {`START_TIMER, qv_qpn}; + end + else begin + o_tc_wr_en <= 'd0; + ov_tc_din <= 'd0; + end +end + +//-- o_packet_out_valid -- +//-- ov_packet_out_head -- +//-- ov_packet_out_data -- +//-- o_packet_out_start -- +//-- o_packet_out_last -- +always @(*) begin + if(rst) begin + o_packet_out_valid = 'd0; + ov_packet_out_head = 'd0; + ov_packet_out_data = 'd0; + o_packet_out_start = 'd0; + o_packet_out_last = 'd0; + end + else if(ioi_cur_state == IOI_RELIABLE_s || ioi_cur_state == IOI_UNRELIABLE_s) begin + //Here we must synchronize packet out and insert, it may incur combination loop, hence we add several stream_reg. + o_packet_out_valid = q_insert_header ? 'd0 : (i_packet_in_valid && i_packet_out_ready && i_insert_req_ready); + ov_packet_out_head = o_packet_out_start ? {240'd0, (iv_npsn_rd_data), iv_packet_in_head[247:8], iv_packet_in_head[7:0] + 8'd3} : 'd0; //Append PSN + ov_packet_out_data = o_packet_out_valid ? iv_packet_in_data : 'd0; + o_packet_out_start = q_insert_header ? 'd0 : i_packet_in_start; + o_packet_out_last = q_insert_header ? 'd0 : i_packet_in_last; + end + else begin + o_packet_out_valid = 'd0; + ov_packet_out_head = 'd0; + ov_packet_out_data = 'd0; + o_packet_out_start = 'd0; + o_packet_out_last = 'd0; + end +end + +/*------------------------------------------- Variables Decode : End ------------------------------------------------*/ +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/TransportSubsystem/OutofOrderAccept.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/TransportSubsystem/OutofOrderAccept.v new file mode 100644 index 0000000000000000000000000000000000000000..c3c198a3ed4c50ff52b12abaaab22ab78398c891 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/TransportSubsystem/OutofOrderAccept.v @@ -0,0 +1,914 @@ +/*------------------------------------------- Module Description : Begin ---------------------------------------------- +Name: OutOfOrderAccept +Author: YangFan +Function: Detect out-of-order packet and buffer these packets. + For UC/UD, in-order packet are directly commit to ULP; + For RC, packet are first enqueued, and commit by InOrderCommit, metadata(QPN and PSN) are passed to InOrderCommit. +--------------------------------------------- Module Decription : End -----------------------------------------------*/ + +/*------------------------------------------- Timescale Definition : Begin ------------------------------------------*/ +`timescale 1ns / 1ps +/*------------------------------------------- Timescale Definition : End --------------------------------------------*/ + +/*------------------------------------------- Included Files : Begin ------------------------------------------------*/ +`include "ib_constant_def_h.vh" +`include "common_function_def.vh" +`include "transport_subsystem_def.vh" +`include "global_def.vh" +/*------------------------------------------- Included Files : End --------------------------------------------------*/ + +/*------------------------------------------- Input/Output Definition : Begin ---------------------------------------*/ +module OutOfOrderAccept ( + input wire clk, + input wire rst, + +//Interface with Network + input wire i_packet_in_valid, + input wire [`PKT_HEAD_WIDTH - 1 : 0] iv_packet_in_head, + input wire [`PKT_DATA_WIDTH - 1 : 0] iv_packet_in_data, + input wire i_packet_in_start, + input wire i_packet_in_last, + output reg o_packet_in_ready, + +//EPSN control + output reg [`QP_NUM_LOG - 1 : 0] ov_epsn_rd_index, + input wire [`PSN_WIDTH - 1 : 0] iv_epsn_rd_data, + output reg o_epsn_wr_en, + output reg [`QP_NUM_LOG - 1 : 0] ov_epsn_wr_index, + output reg [`PSN_WIDTH - 1 : 0] ov_epsn_wr_data, + + +//Find nearest received packet + output reg o_find_req_valid, + output reg [`QP_NUM_LOG + `PSN_WIDTH - 1 : 0] ov_find_req_head, + input wire i_find_resp_valid, + input wire [`PKT_SLOT_NUM_LOG + `RECV_BUFFER_SLOT_NUM_LOG : 0] iv_find_resp_data, + +//Interface with PacketBufferMgt + //Enqueue Packet + input wire [`RECV_BUFFER_SLOT_NUM_LOG - 1 : 0] iv_available_slot_num, + output reg o_insert_req_valid, + output reg [`PKT_HEAD_WIDTH - 1 : 0] ov_insert_req_head, + output reg [`PKT_DATA_WIDTH - 1 : 0] ov_insert_req_data, + output reg o_insert_req_start, + output reg o_insert_req_last, + input wire i_insert_req_ready, + +//Interface with ULP(UC/UD packet commit) + output reg o_commit_valid, + output reg [`PKT_HEAD_WIDTH - 1 : 0] ov_commit_head, + output reg [`PKT_DATA_WIDTH - 1 : 0] ov_commit_data, + output reg o_commit_start, + output reg o_commit_last, + input wire i_commit_ready, + +//ACK out + output reg o_ack_out_valid, + output reg [`PKT_HEAD_WIDTH - 1 : 0] ov_ack_out_head, + output reg [`PKT_DATA_WIDTH - 1 : 0] ov_ack_out_data, + output reg o_ack_out_start, + output reg o_ack_out_last, + input wire i_ack_out_ready, + +//Metadata to InOrderCommit + output reg o_pkt_meta_wr_en, + output reg [`PKT_META_WIDTH - 1 : 0] ov_pkt_meta_din, + input wire i_pkt_meta_prog_full + +); +/*------------------------------------------- Input/Output Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Variables Definition : Begin ------------------------------------*/ +wire [2:0] wv_service_type; +wire [`RECV_BUFFER_SLOT_NUM_LOG - 1 : 0] wv_slot_required; +wire [23:0] wv_qpn; +wire [23:0] wv_rpsn; +wire [23:0] wv_epsn; +reg [2:0] qv_service_type; +reg [`RECV_BUFFER_SLOT_NUM_LOG - 1 : 0] qv_slot_required; +reg [23:0] qv_qpn; +reg [23:0] qv_rpsn; +reg [23:0] qv_epsn; +reg [23:0] qv_find_psn; + +reg [15:0] qv_insert_count; + +wire [15:0] wv_payload_len; + +reg q_already_buffered; + +wire [47:0] wv_dstMAC; +wire [47:0] wv_srcMAC; +wire [31:0] wv_dstIP; +wire [31:0] wv_srcIP; +wire [23:0] wv_dstQPN; +wire [23:0] wv_srcQPN; + +reg [47:0] qv_dstMAC; +reg [47:0] qv_srcMAC; +reg [31:0] qv_dstIP; +reg [31:0] qv_srcIP; +reg [23:0] qv_dstQPN; +reg [23:0] qv_srcQPN; + +reg q_loss_detected; + +reg [23:0] qv_retrans_lower_bound; +reg [23:0] qv_retrans_upper_bound; + +reg q_sack_valid; + +reg q_insert_header; + +reg q_locate_loss; + +reg [23:0] qv_find_psn_diff; +/*------------------------------------------- Local Variables Definition : End --------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : Begin ---------------------------------------*/ +//NULL +/*------------------------------------------- Submodules Instatiation : End -----------------------------------------*/ + +/*------------------------------------------- State Machine Definition : Begin --------------------------------------*/ +reg [3:0] ooa_cur_state; +reg [3:0] ooa_next_state; + +parameter [3:0] OOA_IDLE_s = 4'd1, + OOA_UNRELIABLE_JUDGE_s = 4'd2, + OOA_UNRELIABLE_COMMIT_s = 4'd3, + OOA_UNRELIABLE_DROP_s = 4'd4, + OOA_RELIABLE_JUDGE_s = 4'd5, + OOA_RELIABLE_INSERT_s = 4'd6, + OOA_RELIABLE_LOCATE_LOSS_s ='d7, + OOA_RELIABLE_COMMIT_s = 4'd8, + OOA_RELIABLE_DROP_s = 4'd9, + OOA_RELIABLE_ACK_s = 4'd10; + +always @(posedge clk or posedge rst) begin + if(rst) begin + ooa_cur_state <= OOA_IDLE_s; + end + else begin + ooa_cur_state <= ooa_next_state; + end +end + +always @(*) begin + case(ooa_cur_state) + OOA_IDLE_s: if(i_packet_in_valid) begin + if(wv_service_type == `UC || wv_service_type == `UD) begin + ooa_next_state = OOA_UNRELIABLE_JUDGE_s; + end + else if(wv_service_type == `RC) begin + ooa_next_state = OOA_RELIABLE_JUDGE_s; + end + else begin + ooa_next_state = OOA_IDLE_s; + end + end + else begin + ooa_next_state = OOA_IDLE_s; + end + OOA_UNRELIABLE_JUDGE_s: if(wv_rpsn == wv_epsn) begin + ooa_next_state = OOA_UNRELIABLE_COMMIT_s; + end + else begin + ooa_next_state = OOA_UNRELIABLE_DROP_s; + end + OOA_UNRELIABLE_COMMIT_s: if(i_packet_in_valid && i_packet_in_last && i_commit_ready) begin + ooa_next_state = OOA_IDLE_s; + end + else begin + ooa_next_state = OOA_UNRELIABLE_COMMIT_s; + end + OOA_UNRELIABLE_DROP_s: if(i_packet_in_valid && i_packet_in_last) begin + ooa_next_state = OOA_IDLE_s; + end + else begin + ooa_next_state = OOA_UNRELIABLE_DROP_s; + end + OOA_RELIABLE_JUDGE_s: if(qv_rpsn < wv_epsn) begin + ooa_next_state = OOA_RELIABLE_DROP_s; + end + else if(qv_rpsn == wv_epsn) begin + if(i_find_resp_valid && !iv_find_resp_data[`PKT_SLOT_NUM_LOG + `RECV_BUFFER_SLOT_NUM_LOG]) begin + if(qv_slot_required <= iv_available_slot_num) begin + ooa_next_state = OOA_RELIABLE_INSERT_s; + end + else begin + ooa_next_state = OOA_RELIABLE_DROP_s; + end + end + else if(i_find_resp_valid && iv_find_resp_data[`PKT_SLOT_NUM_LOG + `RECV_BUFFER_SLOT_NUM_LOG]) begin + ooa_next_state = OOA_RELIABLE_DROP_s; + end + else begin + ooa_next_state = OOA_RELIABLE_JUDGE_s; + end + end + else if(wv_rpsn > wv_epsn) begin //Complicated, need to precisely decide the lower boundary of loss packets. + if(i_find_resp_valid && !iv_find_resp_data[`PKT_SLOT_NUM_LOG + `RECV_BUFFER_SLOT_NUM_LOG]) begin //We still need to judge whether this packet is duplicate for further decision + if(qv_slot_required <= iv_available_slot_num) begin + ooa_next_state = OOA_RELIABLE_INSERT_s; + end + else begin + ooa_next_state = OOA_RELIABLE_DROP_s; + end + end + else if(i_find_resp_valid && iv_find_resp_data[`PKT_SLOT_NUM_LOG + `RECV_BUFFER_SLOT_NUM_LOG]) begin + ooa_next_state = OOA_RELIABLE_LOCATE_LOSS_s; + end + else begin + ooa_next_state = OOA_RELIABLE_JUDGE_s; + end + end + else begin + ooa_next_state = OOA_RELIABLE_DROP_s; + end + OOA_RELIABLE_LOCATE_LOSS_s: if(i_find_resp_valid) begin + if(!iv_find_resp_data[`PKT_SLOT_NUM_LOG + `RECV_BUFFER_SLOT_NUM_LOG]) begin + if(wv_epsn == qv_find_psn_diff) begin //Lower bound is EPSN + ooa_next_state = OOA_RELIABLE_ACK_s; + end + else begin + ooa_next_state = OOA_RELIABLE_LOCATE_LOSS_s; //Not reach lower bound, continue searching + end + end + else begin + ooa_next_state = OOA_RELIABLE_ACK_s; + end + end + else begin + ooa_next_state = OOA_RELIABLE_LOCATE_LOSS_s; + end + OOA_RELIABLE_INSERT_s: if(i_packet_in_valid && i_packet_in_last) begin + if(q_locate_loss) begin + ooa_next_state = OOA_RELIABLE_LOCATE_LOSS_s; + end + else begin + ooa_next_state = OOA_RELIABLE_COMMIT_s; + end + end + else begin + ooa_next_state = OOA_RELIABLE_INSERT_s; + end + OOA_RELIABLE_DROP_s: if(i_packet_in_valid && i_packet_in_last) begin + ooa_next_state = OOA_RELIABLE_ACK_s; + end + else begin + ooa_next_state = OOA_RELIABLE_DROP_s; + end + OOA_RELIABLE_COMMIT_s: if(i_find_resp_valid) begin + if(iv_find_resp_data[`PKT_SLOT_NUM_LOG + `RECV_BUFFER_SLOT_NUM_LOG]) begin + ooa_next_state = OOA_RELIABLE_COMMIT_s; //Continue searching + end + else begin + ooa_next_state = OOA_RELIABLE_ACK_s; + end + end + else begin + ooa_next_state = OOA_RELIABLE_COMMIT_s; + end + OOA_RELIABLE_ACK_s: if(i_ack_out_ready) begin + ooa_next_state = OOA_IDLE_s; + end + else begin + ooa_next_state = OOA_RELIABLE_ACK_s; + end + default: ooa_next_state = OOA_IDLE_s; + endcase +end + +/*------------------------------------------- State Machine Definition : End ----------------------------------------*/ + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ +//-- wv_dstMAC -- +assign wv_dstMAC = iv_packet_in_head[`DST_MAC_OFFSET]; + +//-- wv_srcMAC -- +assign wv_srcMAC = iv_packet_in_head[`SRC_MAC_OFFSET]; + +//-- wv_dstIP -- +assign wv_dstIP = iv_packet_in_head[`DST_IP_OFFSET]; + +//-- wv_srcIP -- +assign wv_srcIP = iv_packet_in_head[`SRC_IP_OFFSET]; + +//-- wv_dstQPN -- +assign wv_dstQPN = iv_packet_in_head[`DST_QPN_OFFSET]; + +//-- wv_srcQPN -- +assign wv_srcQPN = iv_packet_in_head[`SRC_QPN_OFFSET]; + +//-- q_locate_loss -- +always @(posedge clk or posedge rst) begin + if(rst) begin + q_locate_loss <= 'd0; + end + else if(ooa_cur_state <= OOA_IDLE_s) begin + q_locate_loss <= 'd0; + end + else if(ooa_cur_state == OOA_RELIABLE_JUDGE_s && wv_epsn < qv_rpsn) begin + q_locate_loss <= 'd1; + end + else begin + q_locate_loss <= q_locate_loss; + end +end + +//-- qv_dstMAC -- +//-- qv_srcMAC -- +//-- qv_dstIP -- +//-- qv_srcIP -- +//-- qv_dstQPN -- +//-- qv_srcQPN -- +always @(posedge clk or posedge rst) begin + if(rst) begin + qv_dstMAC <= 'd0; + qv_srcMAC <= 'd0; + qv_dstIP <= 'd0; + qv_srcIP <= 'd0; + qv_dstQPN <= 'd0; + qv_srcQPN <= 'd0; + end + else if(ooa_cur_state == OOA_IDLE_s && i_packet_in_valid) begin + qv_dstMAC <= wv_srcMAC; + qv_srcMAC <= wv_dstMAC; + qv_dstIP <= wv_dstIP; + qv_srcIP <= wv_srcIP; + qv_dstQPN <= wv_srcQPN; + qv_srcQPN <= wv_dstQPN; + end + else begin + qv_dstMAC <= qv_dstMAC; + qv_srcMAC <= qv_srcMAC; + qv_dstIP <= qv_dstIP; + qv_srcIP <= qv_srcIP; + qv_dstQPN <= qv_dstQPN; + qv_srcQPN <= qv_srcQPN; + end +end + +//-- wv_service_type -- +assign wv_service_type = iv_packet_in_head[`SERVICE_TYPE_OFFSET]; + +//-- wv_payload_len -- +assign wv_payload_len = iv_packet_in_head[`PAYLOAD_LENGTH_OFFSET]; + +//-- wv_slot_required -- +assign wv_slot_required = (wv_payload_len[5:0] ? (wv_payload_len >> 6) + 1 : (wv_payload_len >> 6)) + 'd1; //+1 for packet header + +//-- wv_qpn -- +assign wv_qpn = iv_packet_in_head[`QPN_OFFSET]; + +//-- wv_rpsn -- +assign wv_rpsn = iv_packet_in_head[`PSN_OFFSET]; + +//-- wv_epsn -- +assign wv_epsn = iv_epsn_rd_data; + +//-- qv_service_type -- +//-- qv_slot_required -- +//-- qv_qpn -- +//-- qv_rpsn -- +always @(posedge clk or posedge rst) begin + if(rst) begin + qv_service_type <= 'd0; + qv_slot_required <= 'd0; + qv_qpn <= 'd0; + qv_rpsn <= 'd0; + end + else if(ooa_cur_state == OOA_IDLE_s && i_packet_in_valid) begin + qv_service_type <= wv_service_type; + qv_slot_required <= wv_slot_required; + qv_qpn <= wv_qpn; + qv_rpsn <= wv_rpsn; + end + else begin + qv_service_type <= qv_service_type; + qv_slot_required <= qv_slot_required; + qv_qpn <= qv_qpn; + qv_rpsn <= qv_rpsn; + end +end + +//-- qv_epsn -- +always @(posedge clk or posedge rst) begin + if(rst) begin + qv_epsn <= 'd0; + end + else if(ooa_cur_state == OOA_UNRELIABLE_JUDGE_s && wv_rpsn == wv_epsn) begin + qv_epsn <= wv_epsn + 'd1; + end + else if(ooa_cur_state == OOA_RELIABLE_JUDGE_s) begin + if(wv_rpsn < wv_epsn) begin + qv_epsn <= wv_epsn; + end + else if(wv_rpsn == wv_epsn) begin + qv_epsn <= wv_epsn + 'd1; + end + else if(wv_rpsn > wv_epsn) begin + qv_epsn <= wv_epsn; + end + else begin + qv_epsn <= qv_epsn; + end + end + else if(ooa_cur_state == OOA_RELIABLE_COMMIT_s && i_find_resp_valid && iv_find_resp_data[`PKT_SLOT_NUM_LOG + `RECV_BUFFER_SLOT_NUM_LOG]) begin + qv_epsn <= qv_find_psn_diff + 'd1; + end + else begin + qv_epsn <= qv_epsn; + end +end + +//-- o_packet_in_ready -- +always @(*) begin + if(rst) begin + o_packet_in_ready = 'd0; + end + else if(ooa_cur_state == OOA_IDLE_s) begin + o_packet_in_ready = 'd0; + end + else if(ooa_cur_state == OOA_UNRELIABLE_COMMIT_s) begin + o_packet_in_ready = i_commit_ready; + end + else if(ooa_cur_state == OOA_UNRELIABLE_DROP_s) begin + o_packet_in_ready = 'd1; + end + else if(ooa_cur_state == OOA_RELIABLE_INSERT_s) begin + o_packet_in_ready = q_insert_header ? 'd0 : i_insert_req_ready; + end + else if(ooa_cur_state == OOA_RELIABLE_DROP_s) begin + o_packet_in_ready = 'd1; + end + else begin + o_packet_in_ready = 'd0; + end +end + +//-- qv_insert_count -- +always @(posedge clk or posedge rst) begin + if(rst) begin + qv_insert_count <= 'd0; + end + else if(ooa_cur_state == OOA_IDLE_s) begin + qv_insert_count <= 'd0; + end + else if(ooa_cur_state == OOA_RELIABLE_INSERT_s && i_packet_in_valid && i_insert_req_ready) begin + qv_insert_count <= qv_insert_count + 'd1; + end + else begin + qv_insert_count <= qv_insert_count; + end +end + +//-- o_insert_req_valid -- +always @(*) begin + if(rst) begin + o_insert_req_valid = 'd0; + end + else if(ooa_cur_state == OOA_RELIABLE_INSERT_s) begin + o_insert_req_valid = i_packet_in_valid; + end + else begin + o_insert_req_valid = 'd0; + end +end + +//-- ov_insert_req_head -- +always @(*) begin + if(rst) begin + ov_insert_req_head = 'd0; + end + else if(ooa_cur_state == OOA_RELIABLE_INSERT_s && i_packet_in_start) begin + ov_insert_req_head = q_insert_header ? {qv_slot_required, qv_rpsn, qv_qpn} : 'd0; + end + else begin + ov_insert_req_head = 'd0; + end +end + +//-- ov_insert_req_data -- +always @(*) begin + if(rst) begin + ov_insert_req_data = 'd0; + end + else if(ooa_cur_state == OOA_RELIABLE_INSERT_s) begin + if(q_insert_header) begin + ov_insert_req_data = {240'd0, qv_rpsn, iv_packet_in_head[247:8], iv_packet_in_head[7:0]}; + end + else begin + ov_insert_req_data = iv_packet_in_data; + end + end + else begin + ov_insert_req_data = 'd0; + end +end + +//-- o_insert_req_start -- +always @(*) begin + if(rst) begin + o_insert_req_start = 'd0; + end + else if(ooa_cur_state == OOA_RELIABLE_INSERT_s && i_packet_in_start) begin + o_insert_req_start = q_insert_header ? i_packet_in_start : 'd0; + end + else begin + o_insert_req_start = 'd0; + end +end + +//-- o_insert_req_last -- +always @(*) begin + if(rst) begin + o_insert_req_last = 'd0; + end + else if(ooa_cur_state == OOA_RELIABLE_INSERT_s && i_packet_in_last) begin + o_insert_req_last = q_insert_header ? 'd0 : i_packet_in_last; + end + else begin + o_insert_req_last = 'd0; + end +end + +//-- o_commit_valid -- +always @(*) begin + if(rst) begin + o_commit_valid = 'd0; + end + else if(ooa_cur_state == OOA_UNRELIABLE_COMMIT_s) begin + o_commit_valid = i_packet_in_valid; + end + else begin + o_commit_valid = 'd0; + end +end + +//-- ov_commit_head -- +always @(*) begin + if(rst) begin + ov_commit_head = 'd0; + end + else if(ooa_cur_state == OOA_UNRELIABLE_COMMIT_s && i_packet_in_start) begin + ov_commit_head = {'d0, iv_packet_in_head[247:8], iv_packet_in_head[7:0] - 8'd3}; //Remove PSN + end + else begin + ov_commit_head = 'd0; + end +end + +//-- ov_commit_data -- +always @(*) begin + if(rst) begin + ov_commit_data = 'd0; + end + else if(ooa_cur_state == OOA_UNRELIABLE_COMMIT_s) begin + ov_commit_data = iv_packet_in_data; + end + else begin + ov_commit_data = 'd0; + end +end + +//-- o_commit_start -- +always @(*) begin + if(rst) begin + o_commit_start = 'd0; + end + else if(ooa_cur_state == OOA_UNRELIABLE_COMMIT_s && i_packet_in_start) begin + o_commit_start = 'd1; + end + else begin + o_commit_start = 'd0; + end +end + +//-- o_commit_last -- +always @(*) begin + if(rst) begin + o_commit_last = 'd0; + end + else if(ooa_cur_state == OOA_UNRELIABLE_COMMIT_s && i_packet_in_last) begin + o_commit_last = 'd1; + end + else begin + o_commit_last = 'd0; + end +end + +//-- q_sack_valid -- +always @(posedge clk or posedge rst) begin + if(rst) begin + q_sack_valid <= 'd0; + end + else if(ooa_cur_state == OOA_IDLE_s) begin + q_sack_valid <= 'd0; + end + else if(ooa_cur_state == OOA_RELIABLE_JUDGE_s) begin //Only when we receive a OoO packet for the first time do we set this flag + q_sack_valid <= (wv_rpsn > wv_epsn) && i_find_resp_valid && !iv_find_resp_data[`PKT_SLOT_NUM_LOG + `RECV_BUFFER_SLOT_NUM_LOG]; + end + else begin + q_sack_valid <= q_sack_valid; + end +end + +//-- q_loss_detected -- +always @(posedge clk or posedge rst) begin + if(rst) begin + q_loss_detected <= 'd0; + end + else if(ooa_cur_state == OOA_IDLE_s) begin + q_loss_detected <= 'd0; + end + else if(ooa_cur_state == OOA_RELIABLE_LOCATE_LOSS_s) begin + if(i_find_resp_valid && !iv_find_resp_data[`PKT_SLOT_NUM_LOG + `RECV_BUFFER_SLOT_NUM_LOG]) begin //Detect PSN hole + q_loss_detected <= 'd1; + end + else begin + q_loss_detected <= q_loss_detected; + end + end + else begin + q_loss_detected <= 'd0; + end +end + +//-- o_ack_out_valid -- +//-- ov_ack_out_head -- +//-- ov_ack_out_data -- +//-- o_ack_out_start -- +//-- o_ack_out_last -- +always @(*) begin + if(rst) begin + o_ack_out_valid = 'd0; + ov_ack_out_head = 'd0; + ov_ack_out_data = 'd0; + o_ack_out_start = 'd0; + o_ack_out_last = 'd0; + end + else if(ooa_cur_state == OOA_RELIABLE_ACK_s) begin + o_ack_out_valid = 'd1; + ov_ack_out_head = {qv_dstMAC, qv_srcMAC, qv_dstIP, qv_srcIP, qv_dstQPN, 8'd0, qv_srcQPN, {`ACKNOWLEDGE, `RC}, 16'h000d, 8'h1f}; + ov_ack_out_data = {qv_epsn, qv_rpsn, qv_retrans_lower_bound, qv_retrans_upper_bound, {6'd0, q_sack_valid, q_loss_detected}}; //EPSN, SACKed PSN, retrans lower bound, retrans upper bound, loss indicator + o_ack_out_start = 'd1; + o_ack_out_last = 'd1; + end + else begin + o_ack_out_valid = 'd0; + ov_ack_out_head = 'd0; + ov_ack_out_data = 'd0; + o_ack_out_start = 'd0; + o_ack_out_last = 'd0; + end +end + +//-- o_pkt_meta_wr_en -- +//-- ov_pkt_meta_din -- +always @(*) begin + if(rst) begin + o_pkt_meta_wr_en = 'd0; + ov_pkt_meta_din = 'd0; + end + else if(ooa_cur_state == OOA_RELIABLE_COMMIT_s && i_find_resp_valid && !iv_find_resp_data[`PKT_SLOT_NUM_LOG + `RECV_BUFFER_SLOT_NUM_LOG] && !i_pkt_meta_prog_full) begin + o_pkt_meta_wr_en = 'd1; //Only when the expected packet comes do we commit + ov_pkt_meta_din = {(qv_find_psn_diff - 24'd1), qv_rpsn, qv_qpn}; + end + else begin + o_pkt_meta_wr_en = 'd0; + ov_pkt_meta_din = 'd0; + end +end + +//-- ov_epsn_rd_index -- +always @(*) begin + if(rst) begin + ov_epsn_rd_index = 'd0; + end + else if(ooa_cur_state == OOA_IDLE_s && i_packet_in_valid) begin + ov_epsn_rd_index = wv_qpn; + end + else if(ooa_cur_state != OOA_IDLE_s) begin + ov_epsn_rd_index = qv_qpn; + end + else begin + ov_epsn_rd_index = 'd0; + end +end + +//-- o_epsn_wr_en -- +//-- ov_epsn_wr_index -- +//-- ov_epsn_wr_data -- +always @(*) begin + if(rst) begin + o_epsn_wr_en = 'd0; + ov_epsn_wr_index = 'd0; + ov_epsn_wr_data = 'd0; + end + else if(ooa_cur_state == OOA_UNRELIABLE_COMMIT_s && i_packet_in_valid && i_packet_in_start) begin + o_epsn_wr_en = 'd1; + ov_epsn_wr_index = qv_qpn; + ov_epsn_wr_data = qv_epsn; + end + else if(ooa_cur_state == OOA_RELIABLE_INSERT_s && ooa_next_state == OOA_RELIABLE_COMMIT_s) begin + o_epsn_wr_en = 'd1; + ov_epsn_wr_index = qv_qpn; + ov_epsn_wr_data = qv_epsn; + end + else if(ooa_cur_state == OOA_RELIABLE_COMMIT_s && i_find_resp_valid && iv_find_resp_data[`PKT_SLOT_NUM_LOG + `RECV_BUFFER_SLOT_NUM_LOG]) begin + o_epsn_wr_en = 'd1; + ov_epsn_wr_index = qv_qpn; + ov_epsn_wr_data = qv_find_psn_diff + 'd1; + end + else begin + o_epsn_wr_en = 'd0; + ov_epsn_wr_index = 'd0; + ov_epsn_wr_data = 'd0; + end +end + + +//-- qv_find_psn_diff -- +always @(posedge clk or posedge rst) begin + if(rst) begin + qv_find_psn_diff <= 'd0; + end + else if(i_pkt_meta_prog_full) begin //Corner case for Commit + qv_find_psn_diff <= qv_find_psn_diff; + end + else begin + qv_find_psn_diff <= qv_find_psn; + end +end + +//-- qv_find_psn -- +always @(*) begin + if(rst) begin + qv_find_psn = 'd0; + end + else if(ooa_cur_state == OOA_RELIABLE_JUDGE_s && ooa_next_state == OOA_RELIABLE_LOCATE_LOSS_s) begin + qv_find_psn = qv_rpsn - 'd1; + end + else if(ooa_cur_state == OOA_RELIABLE_INSERT_s && o_insert_req_last && i_insert_req_ready && q_locate_loss) begin + qv_find_psn = qv_rpsn - 'd1; + end + else if(ooa_cur_state == OOA_RELIABLE_LOCATE_LOSS_s && i_find_resp_valid && !iv_find_resp_data[`PKT_SLOT_NUM_LOG + `RECV_BUFFER_SLOT_NUM_LOG]) begin + qv_find_psn = qv_find_psn_diff - 'd1; + end + else if(ooa_cur_state == OOA_RELIABLE_INSERT_s && ooa_next_state == OOA_RELIABLE_COMMIT_s) begin + qv_find_psn = qv_epsn; + end + else if(ooa_cur_state == OOA_RELIABLE_COMMIT_s && i_find_resp_valid && iv_find_resp_data[`PKT_SLOT_NUM_LOG + `RECV_BUFFER_SLOT_NUM_LOG]) begin + qv_find_psn = qv_find_psn_diff + 'd1; + end + else begin + qv_find_psn = qv_find_psn_diff; + end +end + +//-- o_find_req_valid -- +always @(*) begin + if(rst) begin + o_find_req_valid = 'd0; + end + else if(ooa_cur_state == OOA_IDLE_s && i_packet_in_valid && (wv_service_type == `RC)) begin + o_find_req_valid = 'd1; + end + else if(ooa_cur_state == OOA_RELIABLE_JUDGE_s && ooa_next_state == OOA_RELIABLE_LOCATE_LOSS_s) begin + o_find_req_valid = 'd1; + end + else if(ooa_cur_state == OOA_RELIABLE_INSERT_s && o_insert_req_last && i_insert_req_ready && q_locate_loss) begin + o_find_req_valid = 'd1; + end + else if(ooa_cur_state == OOA_RELIABLE_LOCATE_LOSS_s && i_find_resp_valid && !iv_find_resp_data[`PKT_SLOT_NUM_LOG + `RECV_BUFFER_SLOT_NUM_LOG]) begin + o_find_req_valid = 'd1; + end + else if(ooa_cur_state == OOA_RELIABLE_INSERT_s && ooa_next_state == OOA_RELIABLE_COMMIT_s) begin + o_find_req_valid = 'd1; + end + else if(ooa_cur_state == OOA_RELIABLE_COMMIT_s && i_find_resp_valid && iv_find_resp_data[`PKT_SLOT_NUM_LOG + `RECV_BUFFER_SLOT_NUM_LOG]) begin + o_find_req_valid = 'd1; + end + else begin + o_find_req_valid = 'd0; + end +end + +//-- ov_find_req_head -- +always @(*) begin + if(rst) begin + ov_find_req_head = 'd0; + end + else if(ooa_cur_state == OOA_IDLE_s && i_packet_in_valid && (wv_service_type == `RC)) begin + ov_find_req_head = {wv_rpsn, wv_qpn}; + end + else if(ooa_cur_state == OOA_IDLE_s && i_packet_in_valid && (wv_service_type == `RC)) begin + ov_find_req_head = {qv_qpn, qv_find_psn}; + end + else if(ooa_cur_state == OOA_RELIABLE_JUDGE_s && ooa_next_state == OOA_RELIABLE_LOCATE_LOSS_s) begin + ov_find_req_head = {qv_qpn, qv_find_psn}; + end + else if(ooa_cur_state == OOA_RELIABLE_INSERT_s && o_insert_req_last && i_insert_req_ready && q_locate_loss) begin + ov_find_req_head = {qv_qpn, qv_find_psn}; + end + else if(ooa_cur_state == OOA_RELIABLE_LOCATE_LOSS_s && i_find_resp_valid && !iv_find_resp_data[`PKT_SLOT_NUM_LOG + `RECV_BUFFER_SLOT_NUM_LOG]) begin + ov_find_req_head = {qv_qpn, qv_find_psn}; + end + else if(ooa_cur_state == OOA_RELIABLE_INSERT_s && ooa_next_state == OOA_RELIABLE_COMMIT_s) begin + ov_find_req_head = {qv_qpn, qv_find_psn}; + end + else if(ooa_cur_state == OOA_RELIABLE_COMMIT_s && i_find_resp_valid && iv_find_resp_data[`PKT_SLOT_NUM_LOG + `RECV_BUFFER_SLOT_NUM_LOG]) begin + ov_find_req_head = {qv_qpn, qv_find_psn}; + end + else begin + o_find_req_valid = 'd0; + end +end + +//-- q_already_buffered -- +always @(posedge clk or posedge rst) begin + if(rst) begin + q_already_buffered <= 'd0; + end + else if(ooa_cur_state == OOA_IDLE_s) begin + q_already_buffered <= q_already_buffered; + end + else if(ooa_cur_state == OOA_RELIABLE_JUDGE_s && wv_rpsn > wv_epsn + 1) begin + q_already_buffered <= i_find_resp_valid && iv_find_resp_data[`PKT_SLOT_NUM_LOG + `RECV_BUFFER_SLOT_NUM_LOG]; + end + else begin + q_already_buffered <= q_already_buffered; + end +end + +//-- qv_retrans_lower_bound -- +always @(posedge clk or posedge rst) begin + if(rst) begin + qv_retrans_lower_bound <= 'd0; + end + else if(ooa_cur_state == OOA_IDLE_s) begin + qv_retrans_lower_bound <= 'd0; + end + else if(ooa_cur_state == OOA_RELIABLE_LOCATE_LOSS_s && i_find_resp_valid && !iv_find_resp_data[`PKT_SLOT_NUM_LOG + `RECV_BUFFER_SLOT_NUM_LOG]) begin + qv_retrans_lower_bound <= qv_find_psn_diff; //Last PSN hole + end + else begin + qv_retrans_lower_bound <= qv_retrans_lower_bound; + end +end + +reg [31:0] qv_loss_count; +//-- qv_loss_count -- +always @(posedge clk or posedge rst) begin + if(rst) begin + qv_loss_count <= 'd0; + end + else if(ooa_cur_state == OOA_IDLE_s) begin + qv_loss_count <= 'd0; + end + else if(ooa_cur_state == OOA_RELIABLE_LOCATE_LOSS_s && i_find_resp_valid && !iv_find_resp_data[`PKT_SLOT_NUM_LOG + `RECV_BUFFER_SLOT_NUM_LOG]) begin + qv_loss_count <= qv_loss_count + 'd1; + end + else begin + qv_loss_count <= qv_loss_count; + end +end + +//-- qv_retrans_upper_bound -- +always @(posedge clk or posedge rst) begin + if(rst) begin + qv_retrans_upper_bound <= 'd0; + end + else if(ooa_cur_state == OOA_IDLE_s) begin + qv_retrans_upper_bound <= 'd0; + end + else if(ooa_cur_state == OOA_RELIABLE_JUDGE_s && (wv_rpsn == wv_epsn + 1)) begin + qv_retrans_upper_bound <= qv_epsn; + end + else if(ooa_cur_state == OOA_RELIABLE_LOCATE_LOSS_s && i_find_resp_valid && !iv_find_resp_data[`PKT_SLOT_NUM_LOG + `RECV_BUFFER_SLOT_NUM_LOG] && qv_loss_count == 0) begin + qv_retrans_upper_bound <= qv_find_psn_diff; + end + else begin + qv_retrans_upper_bound <= qv_retrans_upper_bound; + end +end + +//-- q_insert_header -- +always @(posedge clk or posedge rst) begin + if(rst) begin + q_insert_header <= 'd0; + end + else if(ooa_cur_state == OOA_IDLE_s && i_packet_in_valid && (wv_service_type == `RC) && (wv_slot_required <= iv_available_slot_num)) begin + q_insert_header <= 'd1; + end + else if(ooa_cur_state == OOA_RELIABLE_INSERT_s && q_insert_header && i_insert_req_ready) begin + q_insert_header <= 'd0; + end + else begin + q_insert_header <= q_insert_header; + end +end + +/*------------------------------------------- Variables Decode : End ------------------------------------------------*/ +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/TransportSubsystem/PacketArbiter.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/TransportSubsystem/PacketArbiter.v new file mode 100644 index 0000000000000000000000000000000000000000..bae57449a228c03a1917ad7cab7c590575bc2c7e --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/TransportSubsystem/PacketArbiter.v @@ -0,0 +1,156 @@ +/*------------------------------------------- Module Description : Begin ---------------------------------------------- +Name: PacketArbiter +Author: YangFan +Function: Arbitrate packets from 2 channel. + In current design, we only support 2-channel, no-weight, round-robin arbitration. + In the future, we will extend its function. +--------------------------------------------- Module Decription : End -----------------------------------------------*/ + +/*------------------------------------------- Timescale Definition : Begin ------------------------------------------*/ +`timescale 1ns / 1ps +/*------------------------------------------- Timescale Definition : End --------------------------------------------*/ + +/*------------------------------------------- Included Files : Begin ------------------------------------------------*/ +`include "ib_constant_def_h.vh" +`include "common_function_def.vh" +`include "transport_subsystem_def.vh" +`include "global_def.vh" +/*------------------------------------------- Included Files : End --------------------------------------------------*/ + +`define CHNL_0 0 +`define CHNL_1 1 + +/*------------------------------------------- Input/Output Definition : Begin ---------------------------------------*/ +module PacketArbiter ( + input wire clk, + input wire rst, + + input wire i_channel_0_valid, + input wire [`PKT_HEAD_WIDTH - 1 : 0] iv_channel_0_head, + input wire [`PKT_DATA_WIDTH - 1 : 0] iv_channel_0_data, + input wire i_channel_0_start, + input wire i_channel_0_last, + output wire o_channel_0_ready, + + input wire i_channel_1_valid, + input wire [`PKT_HEAD_WIDTH - 1 : 0] iv_channel_1_head, + input wire [`PKT_DATA_WIDTH - 1 : 0] iv_channel_1_data, + input wire i_channel_1_start, + input wire i_channel_1_last, + output wire o_channel_1_ready, + + output wire o_channel_out_valid, + output wire [`PKT_HEAD_WIDTH - 1 : 0] ov_channel_out_head, + output wire [`PKT_DATA_WIDTH - 1 : 0] ov_channel_out_data, + output wire o_channel_out_start, + output wire o_channel_out_last, + input wire i_channel_out_ready + +); +/*------------------------------------------- Input/Output Definition : End -----------------------------------------*/ +reg last_sch_channel; +/*------------------------------------------- Local Variables Definition : Begin ------------------------------------*/ + +/*------------------------------------------- Local Variables Definition : End --------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : Begin ---------------------------------------*/ +//None +/*------------------------------------------- Submodules Instatiation : End -----------------------------------------*/ + +/*------------------------------------------- State Machine Definition : Begin --------------------------------------*/ +reg [1:0] arbit_cur_state; +reg [1:0] arbit_next_state; + +parameter [1:0] ARBIT_IDLE_s = 2'd1, + ARBIT_CHNL_0 = 2'd2, + ARBIT_CHNL_1 = 2'd3; + +always @(posedge clk or posedge rst) begin + if(rst) begin + arbit_cur_state <= ARBIT_IDLE_s; + end + else begin + arbit_cur_state <= arbit_next_state; + end +end + +always @(*) begin + case(arbit_cur_state) + ARBIT_IDLE_s: if(i_channel_0_valid && last_sch_channel == `CHNL_1) begin + arbit_next_state = ARBIT_CHNL_0; + end + else if(i_channel_1_valid && last_sch_channel == `CHNL_0) begin + arbit_next_state = ARBIT_CHNL_1; + end + else if(i_channel_0_valid && !i_channel_1_valid) begin + arbit_next_state = ARBIT_CHNL_0; + end + else if(i_channel_1_valid && !i_channel_0_valid) begin + arbit_next_state = ARBIT_CHNL_1; + end + else begin + arbit_next_state = ARBIT_IDLE_s; + end + ARBIT_CHNL_0: if(i_channel_0_valid && i_channel_0_last && i_channel_out_ready) begin + arbit_next_state = ARBIT_IDLE_s; + end + else begin + arbit_next_state = ARBIT_CHNL_0; + end + ARBIT_CHNL_1: if(i_channel_1_valid && i_channel_1_last && i_channel_out_ready) begin + arbit_next_state = ARBIT_IDLE_s; + end + else begin + arbit_next_state = ARBIT_CHNL_1; + end + default: arbit_next_state = ARBIT_IDLE_s; + endcase +end + +/*------------------------------------------- State Machine Definition : End ----------------------------------------*/ + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ +//-- last_sch_channel -- +always @(posedge clk or posedge rst) begin + if(rst) begin + last_sch_channel <= `CHNL_0; + end + else if(arbit_cur_state == ARBIT_CHNL_0 && i_channel_0_valid && i_channel_0_last && i_channel_out_ready) begin + last_sch_channel <= `CHNL_0; + end + else if(arbit_cur_state == ARBIT_CHNL_1 && i_channel_1_valid && i_channel_1_last && i_channel_out_ready) begin + last_sch_channel <= `CHNL_1; + end + else begin + last_sch_channel <= last_sch_channel; + end +end + +//-- o_channel_0_ready -- +assign o_channel_0_ready = (arbit_cur_state == ARBIT_CHNL_0) ? i_channel_out_ready : 'd0; + +//-- o_channel_1_ready -- +assign o_channel_1_ready = (arbit_cur_state == ARBIT_CHNL_1) ? i_channel_out_ready : 'd0; + +//-- o_channel_out_valid -- +assign o_channel_out_valid = (arbit_cur_state == ARBIT_CHNL_0) ? i_channel_0_valid : + (arbit_cur_state == ARBIT_CHNL_1) ? i_channel_1_valid : 'd0; + +//-- ov_channel_out_head -- +assign ov_channel_out_head = (arbit_cur_state == ARBIT_CHNL_0) ? iv_channel_0_head : + (arbit_cur_state == ARBIT_CHNL_1) ? iv_channel_1_head : 'd0; + +//-- ov_channel_out_data -- +assign ov_channel_out_data = (arbit_cur_state == ARBIT_CHNL_0) ? iv_channel_0_data : + (arbit_cur_state == ARBIT_CHNL_1) ? iv_channel_1_data : 'd0; + +//-- o_channel_out_start -- +assign o_channel_out_start = (arbit_cur_state == ARBIT_CHNL_0) ? i_channel_0_start : + (arbit_cur_state == ARBIT_CHNL_1) ? i_channel_1_start : 'd0; + +//-- o_channel_out_last -- +assign o_channel_out_last = (arbit_cur_state == ARBIT_CHNL_0) ? i_channel_0_last : + (arbit_cur_state == ARBIT_CHNL_1) ? i_channel_1_last : 'd0; + +/*------------------------------------------- Variables Decode : End ------------------------------------------------*/ +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/TransportSubsystem/PacketBufferMgt.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/TransportSubsystem/PacketBufferMgt.v new file mode 100644 index 0000000000000000000000000000000000000000..e3f331268d801a77d8bb04a8c970bfb7c0986dd2 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/TransportSubsystem/PacketBufferMgt.v @@ -0,0 +1,535 @@ +/*------------------------------------------- Module Description : Begin ---------------------------------------------- +Name: PacketBufferMgt +Author: YangFan +Function: Manage packet buffer. + For reliable transfer, there are several choices to reload lost packet: + 1.Reload packet from on-nic memory; + 2.Reload packet from host memory based on each packet's DMA address; + 3.Reload WQE from host memory and re-execute this WQE. + Our design is aimed at improving loss recovery efficiency, hence we choose to buffer packet on-nic. + + For reliable receive, there are also several choices to deal with out-of-ordered packet: + 1.Buffer these packet and commit them to the ULP in-order; + 2.No buffering and directly commit them to the ULP out-of-order. + IB specification points out that the application should not depend on the order that the packets arrived, indicating that + we could upload the received packet orderless, which saves on-nic memory and computing resources. + However, we still choose to buffer the packet, for 2 reasons: + 1.There exists several applications sensitive to the packet order; + 2.For short message(only one packet), message order is still strongly required +--------------------------------------------- Module Decription : End -----------------------------------------------*/ + +/*------------------------------------------- Timescale Definition : Begin ------------------------------------------*/ +`timescale 1ns / 1ps +/*------------------------------------------- Timescale Definition : End --------------------------------------------*/ + +/*------------------------------------------- Included Files : Begin ------------------------------------------------*/ +`include "ib_constant_def_h.vh" +`include "common_function_def.vh" +`include "transport_subsystem_def.vh" +`include "global_def.vh" +/*------------------------------------------- Included Files : End --------------------------------------------------*/ + +`define GET_PKT 1 +`define DELETE_PKT 2 +`define FIND_PKT 3 +`define NULL 0 + +/*------------------------------------------- Input/Output Definition : Begin ---------------------------------------*/ +module PacketBufferMgt #( + parameter SLOT_WIDTH = 512, + parameter SLOT_NUM = 512, + parameter SLOT_NUM_LOG = log2b(SLOT_NUM - 1) +)( + input wire clk, + input wire rst, + +//Enqueue Packet + output wire [SLOT_NUM_LOG - 1 : 0] ov_available_slot_num, + input wire i_insert_req_valid, + input wire [`PKT_HEAD_WIDTH - 1 : 0] iv_insert_req_head, //{SlotNum, PSN, QPN} + input wire [`PKT_DATA_WIDTH - 1 : 0] iv_insert_req_data, + input wire i_insert_req_start, + input wire i_insert_req_last, + output wire o_insert_req_ready, + +//Delete Packet + input wire i_delete_req_valid, + input wire [`QP_NUM_LOG + `PSN_WIDTH + SLOT_NUM - 1 : 0] iv_delete_req_head, + output wire o_delete_req_ready, + + output wire o_delete_resp_valid, + output wire [`PKT_HEAD_WIDTH - 1 : 0] ov_delete_resp_head, + output wire [`PKT_DATA_WIDTH - 1 : 0] ov_delete_resp_data, + output wire o_delete_resp_start, + output wire o_delete_resp_last, + input wire i_delete_resp_ready, + +//Find a packet, interfaced with producer. + input wire i_find_req_valid_A, + input wire [`QP_NUM_LOG + `PSN_WIDTH - 1 : 0] iv_find_req_head_A, + output wire o_find_resp_valid_A, + output wire [`PKT_SLOT_NUM_LOG + SLOT_NUM_LOG : 0] ov_find_resp_data_A, + +//Find a packet, interfaced with consumer. + input wire i_find_req_valid_B, + input wire [`QP_NUM_LOG + `PSN_WIDTH - 1 : 0] iv_find_req_head_B, + output wire o_find_resp_valid_B, + output wire [`PKT_SLOT_NUM_LOG + SLOT_NUM_LOG : 0] ov_find_resp_data_B, + +//Get a Packet + input wire i_get_req_valid, + input wire [`QP_NUM_LOG + `PSN_WIDTH + SLOT_NUM - 1 : 0] iv_get_req_head, + + output wire o_get_resp_valid, + output wire [`PKT_HEAD_WIDTH - 1 : 0] ov_get_resp_head, + output wire [`PKT_DATA_WIDTH - 1 : 0] ov_get_resp_data, + output wire o_get_resp_start, + output wire o_get_resp_last, + input wire i_get_resp_ready +); +/*------------------------------------------- Input/Output Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Variables Definition : Begin ------------------------------------*/ +reg [31:0] qv_get_resp_count; +reg [31:0] qv_delete_resp_count; +reg [31:0] qv_insert_resp_count; + + +reg q_alloc_valid; +reg [`QP_NUM_LOG + `PSN_WIDTH - 1 : 0] qv_alloc_index; +reg [`PKT_SLOT_NUM_LOG + SLOT_NUM_LOG - 1 : 0] qv_alloc_data; //+8 to store pkt-occupied slot num +wire w_alloc_ready; + +reg q_find_req_valid; +reg [`QP_NUM_LOG + `PSN_WIDTH - 1 : 0] qv_find_req_index; +wire w_find_resp_valid; +wire [`PKT_SLOT_NUM_LOG + SLOT_NUM_LOG - 1 : 0] wv_find_resp_data; + +reg q_recycle_req_valid; +reg [`QP_NUM_LOG + `PSN_WIDTH - 1 : 0] qv_recycle_req_index; +wire w_recycle_req_ready; +wire w_recycle_resp_valid; +wire [`QP_NUM_LOG + `PSN_WIDTH - 1 : 0] wv_recycle_resp_data; + +reg q_insert_req_valid; +reg q_insert_req_start; +reg q_insert_req_last; +reg [SLOT_NUM_LOG - 1 : 0] qv_insert_req_head; +reg [SLOT_WIDTH - 1 : 0] qv_insert_req_data; +wire w_insert_req_ready; +wire w_insert_resp_valid; +wire [SLOT_NUM_LOG - 1 : 0] wv_insert_resp_data; + +reg q_get_req_valid; +reg [SLOT_NUM_LOG * 2 - 1 : 0] qv_get_req_head; +wire w_get_req_ready; +wire w_get_resp_valid; +wire w_get_resp_last; +wire [`PKT_SLOT_NUM_LOG + SLOT_WIDTH - 1 : 0] wv_get_resp_data; +reg q_get_resp_ready; +reg [`PKT_HEAD_WIDTH - 1 : 0] qv_get_resp_head; + +reg q_delete_req_valid; +reg [SLOT_NUM_LOG * 2 - 1 : 0] qv_delete_req_head; +wire w_delete_req_ready; +wire w_delete_resp_valid; +wire w_delete_resp_start; +wire w_delete_resp_last; +wire [SLOT_WIDTH - 1 : 0] wv_delete_resp_data; +reg q_delete_resp_ready; +reg [`PKT_HEAD_WIDTH - 1 : 0] qv_delete_resp_head; + +reg i_get_req_valid_diff; +reg [`QP_NUM_LOG + `PSN_WIDTH + SLOT_NUM - 1 : 0] iv_get_req_head_diff; + +reg i_delete_req_valid_diff; +reg [`QP_NUM_LOG + `PSN_WIDTH + SLOT_NUM - 1 : 0] iv_delete_req_head_diff; + +/*------------------------------------------- Local Variables Definition : End --------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : Begin ---------------------------------------*/ +TransportHashTable +#( + .SLOT_WIDTH(SLOT_NUM_LOG) +) +PacketRecordTable( + .clk(clk), + .rst(rst), + + .i_alloc_valid(q_alloc_valid), + .iv_alloc_index(qv_alloc_index), + .iv_alloc_data(qv_alloc_data), + .o_alloc_ready(w_alloc_ready), + + .i_find_req_valid_A(i_find_req_valid_A), + .iv_find_req_index_A(iv_find_req_head_A), + .o_find_resp_valid_A(o_find_resp_valid_A), + .ov_find_resp_data_A(ov_find_resp_data_A), + + .i_find_req_valid_B(i_find_req_valid_B ? 'd1 : q_find_req_valid), + .iv_find_req_index_B(i_find_req_valid_B ? iv_find_req_head_B : qv_find_req_index), + .o_find_resp_valid_B(w_find_resp_valid), + .ov_find_resp_data_B(wv_find_resp_data), + + .i_recycle_req_valid(q_recycle_req_valid), + .iv_recycle_req_index(qv_recycle_req_index), + .o_recycle_req_ready(w_recycle_req_ready), + .o_recyle_resp_valid(w_recycle_resp_valid), + .ov_recycle_resp_data(wv_recycle_resp_data) +); + +DynamicBuffer +#( + .SLOT_WIDTH(`PKT_DATA_WIDTH), + .SLOT_NUM(SLOT_NUM) +) +PacketBuffer( + .clk(clk), + .rst(rst), + + .ov_available_slot_num(ov_available_slot_num), + + .i_insert_req_valid(q_insert_req_valid), + .i_insert_req_start(q_insert_req_start), + .i_insert_req_last(q_insert_req_last), + .iv_insert_req_head(qv_insert_req_head), + .iv_insert_req_data(qv_insert_req_data), + .o_insert_req_ready(w_insert_req_ready), + .o_insert_resp_valid(w_insert_resp_valid), + .ov_insert_resp_data(wv_insert_resp_data), + + .i_get_req_valid(q_get_req_valid), + .iv_get_req_head(qv_get_req_head), + .o_get_req_ready(w_get_req_ready), + .o_get_resp_valid(w_get_resp_valid), + .o_get_resp_start(w_get_resp_start), + .o_get_resp_last(w_get_resp_last), + .ov_get_resp_data(wv_get_resp_data), + .i_get_resp_ready(q_get_resp_ready), + + .i_delete_req_valid(q_delete_req_valid), + .iv_delete_req_head(qv_delete_req_head), + + .o_delete_req_ready(w_delete_req_ready), + .o_delete_resp_valid(w_delete_resp_valid), + .o_delete_resp_start(w_delete_resp_start), + .o_delete_resp_last(w_delete_resp_last), + .ov_delete_resp_data(wv_delete_resp_data), + .i_delete_resp_ready(q_delete_resp_ready) +); +/*------------------------------------------- Submodules Instatiation : End -----------------------------------------*/ + +/*------------------------------------------- State Machine Definition : Begin --------------------------------------*/ + +/*------------------------------------------- State Machine Definition : End ----------------------------------------*/ + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ +//-- q_insert_req_valid -- +//-- q_insert_req_start -- +//-- q_insert_req_last -- +//-- qv_insert_req_head -- +//-- qv_insert_req_data -- +always @(*) begin + if(rst) begin + q_insert_req_valid = 'd0; + q_insert_req_start = 'd0; + q_insert_req_last = 'd0; + qv_insert_req_head = 'd0; + qv_insert_req_data = 'd0; + end + else begin + q_insert_req_valid = i_insert_req_valid; + qv_insert_req_head = iv_insert_req_head[`REQUIRED_SLOT_NUM_OFFSET]; + qv_insert_req_data = iv_insert_req_data; + q_insert_req_start = i_insert_req_start; + q_insert_req_last = i_insert_req_last; + end +end + +//-- o_insert_req_ready -- +assign o_insert_req_ready = w_insert_req_ready; + +//-- qv_insert_resp_count -- +always @(posedge clk or posedge rst) begin + if(rst) begin + qv_insert_resp_count <= 'd0; + end + else if(i_insert_req_last) begin + qv_insert_resp_count <= 'd0; + end + else if(w_insert_resp_valid) begin + qv_insert_resp_count <= qv_insert_resp_count + 'd1; + end + else begin + qv_insert_resp_count <= qv_insert_resp_count; + end +end + +//-- q_alloc_valid -- +//-- qv_alloc_index -- +//-- qv_alloc_data -- +always @(*) begin + if(rst) begin + q_alloc_valid = 'd0; + qv_alloc_index = 'd0; + qv_alloc_data = 'd0; + end + else if(w_insert_resp_valid && i_insert_req_start) begin //This is a trick for judgement + q_alloc_valid = 'd1; + qv_alloc_index = {iv_insert_req_head[`INSERT_REQ_QPN_OFFSET], iv_insert_req_head[`INSERT_REQ_PSN_OFFSET]}; + qv_alloc_data = {iv_insert_req_head[`REQUIRED_SLOT_NUM_OFFSET], wv_insert_resp_data}; + end + else begin + q_alloc_valid = 'd0; + qv_alloc_index = 'd0; + qv_alloc_data = 'd0; + end +end + +//-- q_find_req_valid -- +//-- qv_find_req_index -- +always @(*) begin + if(rst) begin + q_find_req_valid = 'd0; + qv_find_req_index = 'd0; + end + else if(i_delete_req_valid) begin + q_find_req_valid = 'd1; + qv_find_req_index = {iv_delete_req_head[`DELETE_REQ_QPN_OFFSET], iv_delete_req_head[`DELETE_REQ_PSN_OFFSET]}; + end + else if(i_get_req_valid) begin + q_find_req_valid = 'd1; + qv_find_req_index = {iv_get_req_head[`GET_REQ_QPN_OFFSET], iv_get_req_head[`GET_REQ_PSN_OFFSET]}; + end + else begin + q_find_req_valid = 'd0; + qv_find_req_index = 'd0; + end +end + +//-- o_find_resp_valid_B -- +assign o_find_resp_valid_B = w_find_resp_valid; + +//-- ov_find_resp_data_B -- +assign ov_find_resp_data_B = wv_find_resp_data; + +//-- q_recycle_req_valid -- +//-- qv_recycle_req_index -- +always @(*) begin + if(rst) begin + q_recycle_req_valid = 'd0; + qv_recycle_req_index = 'd0; + end + else if(i_delete_req_valid_diff) begin + q_recycle_req_valid = 'd1; + qv_recycle_req_index = {iv_delete_req_head_diff[`DELETE_REQ_QPN_OFFSET], iv_delete_req_head_diff[`DELETE_REQ_PSN_OFFSET]}; + end + else begin + q_recycle_req_valid = 'd0; + qv_recycle_req_index = 'd0; + end +end + + +//-- i_delete_req_valid_diff -- +//-- iv_delete_req_head_diff -- +always @(posedge clk or posedge rst) begin + if(rst) begin + i_delete_req_valid_diff <= 'd0; + iv_delete_req_head_diff <= 'd0; + end + else begin + i_delete_req_valid_diff <= i_delete_req_valid; + iv_delete_req_head_diff <= iv_delete_req_head; + end +end + +//-- q_delete_req_valid -- +//-- qv_delete_req_head -- +always @(*) begin + if(rst) begin + q_delete_req_valid = 'd0; + qv_delete_req_head = 'd0; + end + else if(i_delete_req_valid_diff) begin + q_delete_req_valid = 'd1; + qv_delete_req_head = {wv_find_resp_data[`PKT_SLOT_NUM_LOG + SLOT_NUM_LOG - 1 : SLOT_NUM_LOG], wv_find_resp_data[SLOT_NUM_LOG - 1 : 0]}; + end + else begin + q_delete_req_valid = 'd0; + qv_delete_req_head = 'd0; + end +end + +//-- qv_delete_resp_head -- +always @(posedge clk or posedge rst) begin + if(rst) begin + qv_delete_resp_head <= 'd0; + end + else if(w_delete_resp_valid && w_delete_resp_start) begin + qv_delete_resp_head <= wv_delete_resp_data; + end + else begin + qv_delete_resp_head <= qv_delete_resp_head; + end +end + +//-- qv_delete_resp_count -- +always @(posedge clk or posedge rst) begin + if(rst) begin + qv_delete_resp_count <= 'd0; + end + else if(w_delete_resp_last && i_delete_resp_ready) begin + qv_delete_resp_count <= 'd0; + end + else if(w_delete_resp_valid && q_delete_resp_ready) begin + qv_delete_resp_count <= qv_delete_resp_count + 1; + end + else begin + qv_delete_resp_count <= qv_delete_resp_count; + end +end + +//-- q_delete_resp_ready -- +always @(*) begin + if(rst) begin + q_delete_resp_ready = 'd0; + end + else if(qv_delete_resp_count == 0) begin + q_delete_resp_ready = 'd1; + end + else begin + q_delete_resp_ready = i_delete_resp_ready; + end +end + +reg q_delete_null; + +//-- q_delete_null -- +always @(posedge clk or posedge rst) begin + if(rst) begin + q_delete_null <= 'd0; + end + else if(w_find_resp_valid && wv_find_resp_data == 'd0) begin + q_delete_null <= 'd1; + end + else if(w_find_resp_valid && wv_find_resp_data != 'd0) begin + q_delete_null <= 'd0; + end + else begin + q_delete_null <= q_delete_null; + end +end + +//-- ov_delete_resp_head -- +assign ov_delete_resp_head = (w_delete_resp_valid && qv_delete_resp_count == 1) ? qv_delete_resp_head : 'd0; + +//-- ov_delete_resp_data -- +assign ov_delete_resp_data = (w_delete_resp_valid && w_delete_resp_start) ? 'd0 : wv_delete_resp_data; + +//-- o_delete_resp_start -- +assign o_delete_resp_start = (w_delete_resp_valid) && (qv_delete_resp_count == 1); + +//-- o_delete_resp_last -- +assign o_delete_resp_last = w_delete_resp_last; + +//-- o_delete_req_ready -- +assign o_delete_req_ready = 'd1; + +//-- o_delete_resp_valid -- +assign o_delete_resp_valid = q_delete_null ? w_delete_resp_valid : + (w_delete_resp_valid && w_delete_resp_start) ? 'd0 : w_delete_resp_valid; + + +//-- i_get_req_valid_diff -- +//-- iv_get_req_head_diff -- +always @(posedge clk or posedge rst) begin + if(rst) begin + i_get_req_valid_diff <= 'd0; + iv_get_req_head_diff <= 'd0; + end + else begin + i_get_req_valid_diff <= i_get_req_valid; + iv_get_req_head_diff <= iv_get_req_head; + end +end + +//-- q_get_req_valid -- +//-- qv_get_req_head -- +always @(*) begin + if(rst) begin + q_get_req_valid = 'd0; + qv_get_req_head = 'd0; + end + else if(i_get_req_valid_diff) begin + q_get_req_valid = 'd1; + qv_get_req_head = {wv_find_resp_data[`PKT_SLOT_NUM_LOG + SLOT_NUM_LOG - 1 : SLOT_NUM_LOG], wv_find_resp_data[SLOT_NUM_LOG - 1 : 0]}; + end + else begin + q_get_req_valid = 'd0; + qv_get_req_head = 'd0; + end +end + +//-- qv_get_resp_head -- +always @(posedge clk or posedge rst) begin + if(rst) begin + qv_get_resp_head <= 'd0; + end + else if(w_get_resp_valid && w_get_resp_start) begin + qv_get_resp_head <= wv_get_resp_data; + end + else begin + qv_get_resp_head <= qv_get_resp_head; + end +end + +//-- qv_get_resp_count -- +always @(posedge clk or posedge rst) begin + if(rst) begin + qv_get_resp_count <= 'd0; + end + else if(w_get_resp_last && i_get_resp_ready) begin + qv_get_resp_count <= 'd0; + end + else if(w_get_resp_valid && q_get_resp_ready) begin + qv_get_resp_count <= qv_get_resp_count + 1; + end + else begin + qv_get_resp_count <= qv_get_resp_count; + end +end + +//-- q_get_resp_ready -- +always @(*) begin + if(rst) begin + q_get_resp_ready = 'd0; + end + else if(qv_get_resp_count == 0) begin + q_get_resp_ready = 'd1; + end + else begin + q_get_resp_ready = i_get_resp_ready; + end +end + +//-- o_get_req_ready -- +assign o_get_req_ready = 'd1; + +//-- o_get_resp_valid -- +assign o_get_resp_valid = (w_get_resp_valid && w_get_resp_start) ? 'd0 : w_get_resp_valid; + +//-- ov_get_resp_head -- +assign ov_get_resp_head = (w_get_resp_valid && qv_get_resp_count == 1) ? qv_get_resp_head : 'd0; + +//-- ov_get_resp_data -- +assign ov_get_resp_data = (w_get_resp_valid && w_get_resp_start) ? 'd0 : wv_get_resp_data; + +//-- o_get_resp_start -- +assign o_get_resp_start = (w_get_resp_valid) && (qv_get_resp_count == 1); + +//-- o_get_resp_last -- +assign o_get_resp_last = w_get_resp_last; + +/*------------------------------------------- Variables Decode : End ------------------------------------------------*/ +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/TransportSubsystem/PacketDistributer.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/TransportSubsystem/PacketDistributer.v new file mode 100644 index 0000000000000000000000000000000000000000..9108917ab1903027224f60029796042527282805 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/TransportSubsystem/PacketDistributer.v @@ -0,0 +1,132 @@ +/*------------------------------------------- Module Description : Begin ---------------------------------------------- +Name: PacketArbiter +Author: YangFan +Function: Arbitrate packets from 2 channel. + In current design, we only support 2-channel, no-weight, round-robin arbitration. + In the future, we will extend its function. +--------------------------------------------- Module Decription : End -----------------------------------------------*/ + +/*------------------------------------------- Timescale Definition : Begin ------------------------------------------*/ +`timescale 1ns / 1ps +/*------------------------------------------- Timescale Definition : End --------------------------------------------*/ + +/*------------------------------------------- Included Files : Begin ------------------------------------------------*/ +`include "ib_constant_def_h.vh" +`include "common_function_def.vh" +`include "transport_subsystem_def.vh" +`include "global_def.vh" +/*------------------------------------------- Included Files : End --------------------------------------------------*/ + +/*------------------------------------------- Input/Output Definition : Begin ---------------------------------------*/ +module PacketDistributer ( + input wire clk, + input wire rst, + + input wire i_recv_valid, + input wire [`PKT_HEAD_WIDTH - 1 : 0] iv_recv_head, + input wire [`PKT_DATA_WIDTH - 1 : 0] iv_recv_data, + input wire i_recv_start, + input wire i_recv_last, + output wire o_recv_ready, + + output wire o_channel_0_out_valid, + output wire [`PKT_HEAD_WIDTH - 1 : 0] ov_channel_0_out_head, + output wire [`PKT_DATA_WIDTH - 1 : 0] ov_channel_0_out_data, + output wire o_channel_0_out_start, + output wire o_channel_0_out_last, + input wire i_channel_0_out_ready, + + output wire o_channel_1_out_valid, + output wire [`PKT_HEAD_WIDTH - 1 : 0] ov_channel_1_out_head, + output wire [`PKT_DATA_WIDTH - 1 : 0] ov_channel_1_out_data, + output wire o_channel_1_out_start, + output wire o_channel_1_out_last, + input wire i_channel_1_out_ready +); +/*------------------------------------------- Input/Output Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Variables Definition : Begin ------------------------------------*/ +wire [4:0] wv_opcode; +/*------------------------------------------- Local Variables Definition : End --------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : Begin ---------------------------------------*/ +//None +/*------------------------------------------- Submodules Instatiation : End -----------------------------------------*/ + +/*------------------------------------------- State Machine Definition : Begin --------------------------------------*/ +reg [1:0] dis_cur_state; +reg [1:0] dis_next_state; + +parameter [1:0] DIS_IDLE_s = 3'd1, + DIS_REQ_s = 3'd2, + DIS_ACK_s = 3'd3; + +always @(posedge clk or posedge rst) begin + if(rst) begin + dis_cur_state <= DIS_IDLE_s; + end + else begin + dis_cur_state <= dis_next_state; + end +end + +always @(*) begin + case(dis_cur_state) + DIS_IDLE_s: if(i_recv_valid && wv_opcode == `ACKNOWLEDGE) begin + dis_next_state = DIS_ACK_s; + end + else if(i_recv_valid && wv_opcode != `ACKNOWLEDGE) begin + dis_next_state = DIS_REQ_s; + end + else begin + dis_next_state = DIS_IDLE_s; + end + DIS_REQ_s: if(i_recv_valid && i_recv_last && i_channel_0_out_ready) begin + dis_next_state = DIS_IDLE_s; + end + else begin + dis_next_state = DIS_REQ_s; + end + DIS_ACK_s: if(i_recv_valid && i_recv_last && i_channel_1_out_ready) begin + dis_next_state = DIS_IDLE_s; + end + else begin + dis_next_state = DIS_ACK_s; + end + default: dis_next_state = DIS_IDLE_s; + endcase +end + +/*------------------------------------------- State Machine Definition : End ----------------------------------------*/ + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ +assign o_recv_ready = (dis_cur_state == DIS_IDLE_s) ? 'd0 : + (dis_cur_state == DIS_REQ_s) ? i_channel_0_out_ready : + (dis_cur_state == DIS_ACK_s) ? i_channel_1_out_ready : 'd0; + +assign o_channel_0_out_valid = (dis_cur_state == DIS_IDLE_s) ? 'd0 : + (dis_cur_state == DIS_REQ_s) ? i_recv_valid : 'd0; +assign ov_channel_0_out_head = (dis_cur_state == DIS_IDLE_s) ? 'd0 : + (dis_cur_state == DIS_REQ_s) ? iv_recv_head : 'd0; +assign ov_channel_0_out_data = (dis_cur_state == DIS_IDLE_s) ? 'd0 : + (dis_cur_state == DIS_REQ_s) ? iv_recv_data : 'd0; +assign o_channel_0_out_start = (dis_cur_state == DIS_IDLE_s) ? 'd0 : + (dis_cur_state == DIS_REQ_s) ? i_recv_start : 'd0; +assign o_channel_0_out_last = (dis_cur_state == DIS_IDLE_s) ? 'd0 : + (dis_cur_state == DIS_REQ_s) ? i_recv_last : 'd0; + +assign o_channel_1_out_valid = (dis_cur_state == DIS_IDLE_s) ? 'd0 : + (dis_cur_state == DIS_ACK_s) ? i_recv_valid : 'd0; +assign ov_channel_1_out_head = (dis_cur_state == DIS_IDLE_s) ? 'd0 : + (dis_cur_state == DIS_ACK_s) ? iv_recv_head : 'd0; +assign ov_channel_1_out_data = (dis_cur_state == DIS_IDLE_s) ? 'd0 : + (dis_cur_state == DIS_ACK_s) ? iv_recv_data : 'd0; +assign o_channel_1_out_start = (dis_cur_state == DIS_IDLE_s) ? 'd0 : + (dis_cur_state == DIS_ACK_s) ? i_recv_start : 'd0; +assign o_channel_1_out_last = (dis_cur_state == DIS_IDLE_s) ? 'd0 : + (dis_cur_state == DIS_ACK_s) ? i_recv_last : 'd0; + +assign wv_opcode = iv_recv_head[`OPCODE_OFFSET]; +/*------------------------------------------- Variables Decode : End ------------------------------------------------*/ +endmodule + diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/TransportSubsystem/PacketDropSim_vrf.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/TransportSubsystem/PacketDropSim_vrf.v new file mode 100644 index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391 diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/TransportSubsystem/PacketLossSim_vrf.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/TransportSubsystem/PacketLossSim_vrf.v new file mode 100644 index 0000000000000000000000000000000000000000..e394fa9b4ab639aa0e9e2f98ce7313db85f1ffd9 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/TransportSubsystem/PacketLossSim_vrf.v @@ -0,0 +1,124 @@ +/*------------------------------------------- Module Description : Begin ---------------------------------------------- +Name: PacketLossSim_vrf +Author: YangFan +Function: Intentially drop some packets(Req or ACK), for verification. +--------------------------------------------- Module Decription : End -----------------------------------------------*/ + +/*------------------------------------------- Timescale Definition : Begin ------------------------------------------*/ +`timescale 1ns / 1ps +/*------------------------------------------- Timescale Definition : End --------------------------------------------*/ + +/*------------------------------------------- Included Files : Begin ------------------------------------------------*/ +`include "ib_constant_def_h.vh" +`include "common_function_def.vh" +`include "transport_subsystem_def.vh" +`include "global_def.vh" +/*------------------------------------------- Included Files : End --------------------------------------------------*/ + +// `define PORT_A_LOSS_CNT 100 //Drop a packet when cnt reaches this threshold +// `define PORT_B_LOSS_CNT 100 + +module PacketLossSim_vrf( + input wire clk, + input wire rst, + +//Port A Interface + input wire i_recv_from_port_A_valid, + input wire [`PKT_HEAD_WIDTH - 1 : 0] iv_recv_from_port_A_head, + input wire [`PKT_DATA_WIDTH - 1 : 0] iv_recv_from_port_A_data, + input wire i_recv_from_port_A_start, + input wire i_recv_from_port_A_last, + output wire o_recv_from_port_A_ready, + + output wire o_send_to_port_A_valid, + output wire [`PKT_HEAD_WIDTH - 1 : 0] ov_send_to_port_A_head, + output wire [`PKT_DATA_WIDTH - 1 : 0] ov_send_to_port_A_data, + output wire o_send_to_port_A_start, + output wire o_send_to_port_A_last, + input wire i_send_to_port_A_ready, + +//Port B Interface + input wire i_recv_from_port_B_valid, + input wire [`PKT_HEAD_WIDTH - 1 : 0] iv_recv_from_port_B_head, + input wire [`PKT_DATA_WIDTH - 1 : 0] iv_recv_from_port_B_data, + input wire i_recv_from_port_B_start, + input wire i_recv_from_port_B_last, + output wire o_recv_from_port_B_ready, + + output wire o_send_to_port_B_valid, + output wire [`PKT_HEAD_WIDTH - 1 : 0] ov_send_to_port_B_head, + output wire [`PKT_DATA_WIDTH - 1 : 0] ov_send_to_port_B_data, + output wire o_send_to_port_B_start, + output wire o_send_to_port_B_last, + input wire i_send_to_port_B_ready +); + +/*------------------------------------------- Local Variables Definition : Begin ------------------------------------*/ +reg [63:0] port_A_cnt; +reg [63:0] port_B_cnt; + +/*------------------------------------------- Local Variables Definition : End --------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : Begin ---------------------------------------*/ +assign o_recv_from_port_A_ready = (port_A_cnt != `PORT_A_LOSS_CNT) ? i_send_to_port_B_ready : 'd1; + +assign o_send_to_port_A_valid = (port_B_cnt != `PORT_B_LOSS_CNT) ? i_recv_from_port_B_valid : 'd0; +assign ov_send_to_port_A_head = (port_B_cnt != `PORT_B_LOSS_CNT) ? iv_recv_from_port_B_head : 'd0; +assign ov_send_to_port_A_data = (port_B_cnt != `PORT_B_LOSS_CNT) ? iv_recv_from_port_B_data : 'd0; +assign o_send_to_port_A_start = (port_B_cnt != `PORT_B_LOSS_CNT) ? i_recv_from_port_B_start : 'd0; +assign o_send_to_port_A_last = (port_B_cnt != `PORT_B_LOSS_CNT) ? i_recv_from_port_B_last : 'd0; + +assign o_recv_from_port_B_ready = (port_B_cnt != `PORT_B_LOSS_CNT) ? i_send_to_port_A_ready : 'd1; + +assign o_send_to_port_B_valid = (port_A_cnt != `PORT_A_LOSS_CNT) ? i_recv_from_port_A_valid : 'd0; +assign ov_send_to_port_B_head = (port_A_cnt != `PORT_A_LOSS_CNT) ? iv_recv_from_port_A_head : 'd0; +assign ov_send_to_port_B_data = (port_A_cnt != `PORT_A_LOSS_CNT) ? iv_recv_from_port_A_data : 'd0; +assign o_send_to_port_B_start = (port_A_cnt != `PORT_A_LOSS_CNT) ? i_recv_from_port_A_start : 'd0; +assign o_send_to_port_B_last = (port_A_cnt != `PORT_A_LOSS_CNT) ? i_recv_from_port_A_last : 'd0; + +always @(posedge clk or posedge rst) begin + if(rst) begin + port_A_cnt <= 'd0; + end + else if(port_A_cnt == `PORT_A_LOSS_CNT) begin + if(i_recv_from_port_A_last) begin + port_A_cnt <= 'd0; + end + else begin + port_A_cnt <= port_A_cnt; + end + end + else begin + if(i_recv_from_port_A_last && i_send_to_port_B_ready) begin + port_A_cnt <= port_A_cnt + 'd1; + end + else begin + port_A_cnt <= port_A_cnt; + end + end +end + +always @(posedge clk or posedge rst) begin + if(rst) begin + port_B_cnt <= 'd0; + end + else if(port_B_cnt == `PORT_B_LOSS_CNT) begin + if(i_recv_from_port_B_last) begin + port_B_cnt <= 'd0; + end + else begin + port_B_cnt <= port_B_cnt; + end + end + else begin + if(i_recv_from_port_B_last && i_send_to_port_A_ready) begin + port_B_cnt <= port_B_cnt + 'd1; + end + else begin + port_B_cnt <= port_B_cnt; + end + end +end +/*------------------------------------------- Submodules Instatiation : End -----------------------------------------*/ + +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/TransportSubsystem/README.md b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/TransportSubsystem/README.md new file mode 100644 index 0000000000000000000000000000000000000000..5d5cfa9d608e5eeeefd83a1c4efa104d1ae47bc4 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/TransportSubsystem/README.md @@ -0,0 +1 @@ +TransportSubsystem diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/TransportSubsystem/RecvControl.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/TransportSubsystem/RecvControl.v new file mode 100644 index 0000000000000000000000000000000000000000..cec8b340cb843c34ae555bf385c080c6f1267214 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/TransportSubsystem/RecvControl.v @@ -0,0 +1,698 @@ +/*------------------------------------------- Module Description : Begin ---------------------------------------------- +Name: RecvControl +Author: YangFan +Function: Wrapper for OutOfOrderAccept, InOrderCommit and PacketBufferMgt. +--------------------------------------------- Module Decription : End -----------------------------------------------*/ + +/*------------------------------------------- Timescale Definition : Begin ------------------------------------------*/ +`timescale 1ns / 1ps +/*------------------------------------------- Timescale Definition : End --------------------------------------------*/ + +/*------------------------------------------- Included Files : Begin ------------------------------------------------*/ +`include "ib_constant_def_h.vh" +`include "common_function_def.vh" +`include "transport_subsystem_def.vh" +`include "global_def.vh" +/*------------------------------------------- Included Files : End --------------------------------------------------*/ + +/*------------------------------------------- Input/Output Definition : Begin ---------------------------------------*/ +module RecvControl #( + parameter SLOT_WIDTH = 512, + parameter SLOT_NUM = 512, + parameter SLOT_NUM_LOG = log2b(SLOT_NUM - 1) +)( + input wire clk, + input wire rst, + +//Interface with Network + input wire i_packet_in_valid, + input wire [`PKT_HEAD_WIDTH - 1 : 0] iv_packet_in_head, + input wire [`PKT_DATA_WIDTH - 1 : 0] iv_packet_in_data, + input wire i_packet_in_start, + input wire i_packet_in_last, + output wire o_packet_in_ready, + +//EPSN control + output wire o_ooa_epsn_wr_en, + output wire [`QP_NUM_LOG - 1 : 0] ov_ooa_epsn_wr_index, + output wire [`PSN_WIDTH - 1 : 0] ov_ooa_epsn_wr_data, + output wire [`QP_NUM_LOG - 1 : 0] ov_ooa_epsn_rd_index, + input wire [`PSN_WIDTH - 1 : 0] iv_ooa_epsn_rd_data, + + output wire [`QP_NUM_LOG - 1 : 0] ov_ioc_epsn_rd_index, + input wire [`PSN_WIDTH - 1 : 0] iv_ioc_epsn_rd_data, + output wire o_ioc_epsn_wr_en, + output wire [`QP_NUM_LOG - 1 : 0] ov_ioc_epsn_wr_index, + output wire [`PSN_WIDTH - 1 : 0] ov_ioc_epsn_wr_data, + +//Interface with ULP + output wire o_commit_valid, + output wire [`PKT_HEAD_WIDTH - 1 : 0] ov_commit_head, + output wire [`PKT_DATA_WIDTH - 1 : 0] ov_commit_data, + output wire o_commit_start, + output wire o_commit_last, + input wire i_commit_ready, + +//ACK out + output wire o_packet_out_valid, + output wire [`PKT_HEAD_WIDTH - 1 : 0] ov_packet_out_head, + output wire [`PKT_DATA_WIDTH - 1 : 0] ov_packet_out_data, + output wire o_packet_out_start, + output wire o_packet_out_last, + input wire i_packet_out_ready + +); +/*------------------------------------------- Input/Output Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Variables Definition : Begin ------------------------------------*/ +wire w_packet_in_valid_in_reg; +wire [`PKT_HEAD_WIDTH - 1 : 0] wv_packet_in_head_in_reg; +wire [`PKT_DATA_WIDTH - 1 : 0] wv_packet_in_data_in_reg; +wire w_packet_in_start_in_reg; +wire w_packet_in_last_in_reg; +wire w_packet_in_ready_in_reg; + +wire w_commit_valid_axis; +wire [`PKT_HEAD_WIDTH - 1 : 0] wv_commit_head_axis; +wire [`PKT_DATA_WIDTH - 1 : 0] wv_commit_data_axis; +wire w_commit_start_axis; +wire w_commit_last_axis; +wire w_commit_ready_axis; + +wire w_packet_out_valid_axis; +wire [`PKT_HEAD_WIDTH - 1 : 0] wv_packet_out_head_axis; +wire [`PKT_DATA_WIDTH - 1 : 0] wv_packet_out_data_axis; +wire w_packet_out_start_axis; +wire w_packet_out_last_axis; +wire w_packet_out_ready_axis; + +wire w_unreliable_pkt_in_valid_axis; +wire [`PKT_HEAD_WIDTH - 1 : 0] wv_unreliable_pkt_in_head_axis; +wire [`PKT_DATA_WIDTH - 1 : 0] wv_unreliable_pkt_in_data_axis; +wire w_unreliable_pkt_in_start_axis; +wire w_unreliable_pkt_in_last_axis; +wire w_unreliable_pkt_in_ready_axis; + +wire w_unreliable_pkt_in_valid_in_reg; +wire [`PKT_HEAD_WIDTH - 1 : 0] wv_unreliable_pkt_in_head_in_reg; +wire [`PKT_DATA_WIDTH - 1 : 0] wv_unreliable_pkt_in_data_in_reg; +wire w_unreliable_pkt_in_start_in_reg; +wire w_unreliable_pkt_in_last_in_reg; +wire w_unreliable_pkt_in_ready_in_reg; + +wire w_reliable_pkt_in_valid_axis; +wire [`PKT_HEAD_WIDTH - 1 : 0] wv_reliable_pkt_in_head_axis; +wire [`PKT_DATA_WIDTH - 1 : 0] wv_reliable_pkt_in_data_axis; +wire w_reliable_pkt_in_start_axis; +wire w_reliable_pkt_in_last_axis; +wire w_reliable_pkt_in_ready_axis; + +wire w_reliable_pkt_in_valid_in_reg; +wire [`PKT_HEAD_WIDTH - 1 : 0] wv_reliable_pkt_in_head_in_reg; +wire [`PKT_DATA_WIDTH - 1 : 0] wv_reliable_pkt_in_data_in_reg; +wire w_reliable_pkt_in_start_in_reg; +wire w_reliable_pkt_in_last_in_reg; +wire w_reliable_pkt_in_ready_in_reg; + + +wire [`SEND_BUFFER_SLOT_NUM_LOG - 1 : 0] wv_available_slot_num; +wire w_insert_req_valid_axis; +wire [`PKT_HEAD_WIDTH - 1 : 0] wv_insert_req_head_axis; +wire [`PKT_DATA_WIDTH - 1 : 0] wv_insert_req_data_axis; +wire w_insert_req_start_axis; +wire w_insert_req_last_axis; +wire w_insert_req_ready_axis; + +wire w_insert_req_valid_in_reg; +wire [`PKT_HEAD_WIDTH - 1 : 0] wv_insert_req_head_in_reg; +wire [`PKT_DATA_WIDTH - 1 : 0] wv_insert_req_data_in_reg; +wire w_insert_req_start_in_reg; +wire w_insert_req_last_in_reg; +wire w_insert_req_ready_in_reg; + +wire w_delete_req_valid_axis; +wire [`QP_NUM_LOG + `PSN_WIDTH + SLOT_NUM - 1 : 0] wv_delete_req_head_axis; +wire w_delete_req_ready_axis; + +wire w_delete_req_valid_in_reg; +wire [`QP_NUM_LOG + `PSN_WIDTH + SLOT_NUM - 1 : 0] wv_delete_req_head_in_reg; +wire w_delete_req_ready_in_reg; + +wire w_delete_resp_valid_axis; +wire [`PKT_HEAD_WIDTH - 1 : 0] wv_delete_resp_head_axis; +wire [`PKT_DATA_WIDTH - 1 : 0] wv_delete_resp_data_axis; +wire w_delete_resp_start_axis; +wire w_delete_resp_last_axis; +wire w_delete_resp_ready_axis; + +wire w_delete_resp_valid_in_reg; +wire [`PKT_HEAD_WIDTH - 1 : 0] wv_delete_resp_head_in_reg; +wire [`PKT_DATA_WIDTH - 1 : 0] wv_delete_resp_data_in_reg; +wire w_delete_resp_start_in_reg; +wire w_delete_resp_last_in_reg; +wire w_delete_resp_ready_in_reg; + +wire w_ooa_find_req_valid_axis; +wire [`QP_NUM_LOG + `PSN_WIDTH - 1 : 0] wv_ooa_find_req_head_axis; +wire w_ooa_find_resp_valid_axis; +wire [`PKT_SLOT_NUM_LOG + SLOT_NUM_LOG : 0] wv_ooa_find_resp_data_axis; + +wire w_ooa_find_req_valid_in_reg; +wire [`QP_NUM_LOG + `PSN_WIDTH - 1 : 0] wv_ooa_find_req_head_in_reg; +wire w_ooa_find_resp_valid_in_reg; +wire [`PKT_SLOT_NUM_LOG + SLOT_NUM_LOG : 0] wv_ooa_find_resp_data_in_reg; + +wire w_ioc_find_req_valid_axis; +wire [`QP_NUM_LOG + `PSN_WIDTH - 1 : 0] wv_ioc_find_req_head_axis; +wire w_ioc_find_resp_valid_axis; +wire [`PKT_SLOT_NUM_LOG + SLOT_NUM_LOG : 0] wv_ioc_find_resp_data_axis; + +wire w_ioc_find_req_valid_in_reg; +wire [`QP_NUM_LOG + `PSN_WIDTH - 1 : 0] wv_ioc_find_req_head_in_reg; +wire w_ioc_find_resp_valid_in_reg; +wire [`PKT_SLOT_NUM_LOG + SLOT_NUM_LOG : 0] wv_ioc_find_resp_data_in_reg; + +wire w_pkt_meta_wr_en; +wire [`PKT_META_WIDTH - 1 : 0] wv_pkt_meta_din; +wire w_pkt_meta_prog_full; +wire w_pkt_meta_rd_en; +wire [`PKT_META_WIDTH - 1 : 0] wv_pkt_meta_dout; +wire w_pkt_meta_empty; + +/*------------------------------------------- Local Variables Definition : End --------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : Begin ---------------------------------------*/ +stream_fifo #( + .TUSER_WIDTH(`PKT_HEAD_WIDTH), + .TDATA_WIDTH(`PKT_DATA_WIDTH) +) +PacketInFIFO_Inst +( + .clk (clk), + .rst_n(~rst), + + .axis_tvalid (i_packet_in_valid), + .axis_tuser (iv_packet_in_head), + .axis_tdata (iv_packet_in_data), + .axis_tstart (i_packet_in_start), + .axis_tlast (i_packet_in_last), + .axis_tready (o_packet_in_ready), + .axis_tkeep ('d0), + + .in_reg_tvalid (w_packet_in_valid_in_reg), + .in_reg_tuser (wv_packet_in_head_in_reg), + .in_reg_tdata (wv_packet_in_data_in_reg), + .in_reg_tstart (w_packet_in_start_in_reg), + .in_reg_tlast (w_packet_in_last_in_reg), + .in_reg_tready (w_packet_in_ready_in_reg), + .in_reg_tkeep (), + .tuser_clear ('d0) +); + +stream_fifo #( + .TUSER_WIDTH(`PKT_HEAD_WIDTH), + .TDATA_WIDTH(`PKT_DATA_WIDTH) +) +UnreliablePktFIFO_Inst +( + .clk (clk), + .rst_n(~rst), + + .axis_tvalid (w_unreliable_pkt_in_valid_axis), + .axis_tuser (wv_unreliable_pkt_in_head_axis), + .axis_tdata (wv_unreliable_pkt_in_data_axis), + .axis_tstart (w_unreliable_pkt_in_start_axis), + .axis_tlast (w_unreliable_pkt_in_last_axis), + .axis_tready (w_unreliable_pkt_in_ready_axis), + .axis_tkeep ('d0), + + .in_reg_tvalid (w_unreliable_pkt_in_valid_in_reg), + .in_reg_tuser (wv_unreliable_pkt_in_head_in_reg), + .in_reg_tdata (wv_unreliable_pkt_in_data_in_reg), + .in_reg_tstart (w_unreliable_pkt_in_start_in_reg), + .in_reg_tlast (w_unreliable_pkt_in_last_in_reg), + .in_reg_tready (w_unreliable_pkt_in_ready_in_reg), + .in_reg_tkeep (), + .tuser_clear ('d0) +); + +stream_fifo #( + .TUSER_WIDTH(`PKT_HEAD_WIDTH), + .TDATA_WIDTH(`PKT_DATA_WIDTH) +) +ReliablePktFIFO_Inst +( + .clk (clk), + .rst_n(~rst), + + .axis_tvalid (w_reliable_pkt_in_valid_axis), + .axis_tuser (wv_reliable_pkt_in_head_axis), + .axis_tdata (wv_reliable_pkt_in_data_axis), + .axis_tstart (w_reliable_pkt_in_start_axis), + .axis_tlast (w_reliable_pkt_in_last_axis), + .axis_tready (w_reliable_pkt_in_ready_axis), + .axis_tkeep ('d0), + + .in_reg_tvalid (w_reliable_pkt_in_valid_in_reg), + .in_reg_tuser (wv_reliable_pkt_in_head_in_reg), + .in_reg_tdata (wv_reliable_pkt_in_data_in_reg), + .in_reg_tstart (w_reliable_pkt_in_start_in_reg), + .in_reg_tlast (w_reliable_pkt_in_last_in_reg), + .in_reg_tready (w_reliable_pkt_in_ready_in_reg), + .in_reg_tkeep (), + .tuser_clear ('d0) +); + +stream_fifo #( + .TUSER_WIDTH(`PKT_HEAD_WIDTH), + .TDATA_WIDTH(`PKT_DATA_WIDTH) +) +CommitFIFO_Inst +( + .clk (clk), + .rst_n(~rst), + + .axis_tvalid (w_commit_valid_axis), + .axis_tuser (wv_commit_head_axis), + .axis_tdata (wv_commit_data_axis), + .axis_tstart (w_commit_start_axis), + .axis_tlast (w_commit_last_axis), + .axis_tready (w_commit_ready_axis), + .axis_tkeep ('d0), + + .in_reg_tvalid (o_commit_valid), + .in_reg_tuser (ov_commit_head), + .in_reg_tdata (ov_commit_data), + .in_reg_tstart (o_commit_start), + .in_reg_tlast (o_commit_last), + .in_reg_tready (i_commit_ready), + .in_reg_tkeep (), + .tuser_clear ('d0) +); + +stream_fifo #( + .TUSER_WIDTH(`PKT_HEAD_WIDTH), + .TDATA_WIDTH(`PKT_DATA_WIDTH) +) +PacketOutFIFO_Inst +( + .clk (clk), + .rst_n(~rst), + + .axis_tvalid (w_packet_out_valid_axis), + .axis_tuser (wv_packet_out_head_axis), + .axis_tdata (wv_packet_out_data_axis), + .axis_tstart (w_packet_out_start_axis), + .axis_tlast (w_packet_out_last_axis), + .axis_tready (w_packet_out_ready_axis), + .axis_tkeep ('d0), + + .in_reg_tvalid (o_packet_out_valid), + .in_reg_tuser (ov_packet_out_head), + .in_reg_tdata (ov_packet_out_data), + .in_reg_tstart (o_packet_out_start), + .in_reg_tlast (o_packet_out_last), + .in_reg_tready (i_packet_out_ready), + .in_reg_tkeep (), + .tuser_clear ('d0) +); + +stream_reg #( + .TUSER_WIDTH(`PKT_HEAD_WIDTH), + .TDATA_WIDTH(`PKT_DATA_WIDTH) +) +InsertStream_Inst +( + .clk (clk), + .rst_n(~rst), + + .axis_tvalid (w_insert_req_valid_axis), + .axis_tuser (wv_insert_req_head_axis), + .axis_tdata (wv_insert_req_data_axis), + .axis_tstart (w_insert_req_start_axis), + .axis_tlast (w_insert_req_last_axis), + .axis_tready (w_insert_req_ready_axis), + .axis_tkeep ('d0), + + .in_reg_tvalid (w_insert_req_valid_in_reg), + .in_reg_tuser (wv_insert_req_head_in_reg), + .in_reg_tdata (wv_insert_req_data_in_reg), + .in_reg_tstart (w_insert_req_start_in_reg), + .in_reg_tlast (w_insert_req_last_in_reg), + .in_reg_tready (w_insert_req_ready_in_reg), + .in_reg_tkeep (), + .tuser_clear ('d0) +); + +stream_reg #( + .TUSER_WIDTH(`PKT_HEAD_WIDTH), + .TDATA_WIDTH(`PKT_DATA_WIDTH) +) +DeleteReqStream_Inst +( + .clk (clk), + .rst_n(~rst), + + .axis_tvalid (w_delete_req_valid_axis), + .axis_tuser (wv_delete_req_head_axis), + .axis_tdata ('d0), + .axis_tstart ('d0), + .axis_tlast ('d0), + .axis_tready (w_delete_req_ready_axis), + .axis_tkeep ('d0), + + .in_reg_tvalid (w_delete_req_valid_in_reg), + .in_reg_tuser (wv_delete_req_head_in_reg), + .in_reg_tdata (wv_delete_req_data_in_reg), + .in_reg_tstart (w_delete_req_start_in_reg), + .in_reg_tlast (w_delete_req_last_in_reg), + .in_reg_tready (w_delete_req_ready_in_reg), + .in_reg_tkeep (), + .tuser_clear ('d0) +); + +stream_reg #( + .TUSER_WIDTH(`PKT_HEAD_WIDTH), + .TDATA_WIDTH(`PKT_DATA_WIDTH) +) +DeleteRespStream_Inst +( + .clk (clk), + .rst_n(~rst), + + .axis_tvalid (w_delete_resp_valid_axis), + .axis_tuser (wv_delete_resp_head_axis), + .axis_tdata (wv_delete_resp_data_axis), + .axis_tstart (w_delete_resp_start_axis), + .axis_tlast (w_delete_resp_last_axis), + .axis_tready (w_delete_resp_ready_axis), + .axis_tkeep ('d0), + + .in_reg_tvalid (w_delete_resp_valid_in_reg), + .in_reg_tuser (wv_delete_resp_head_in_reg), + .in_reg_tdata (wv_delete_resp_data_in_reg), + .in_reg_tstart (w_delete_resp_start_in_reg), + .in_reg_tlast (w_delete_resp_last_in_reg), + .in_reg_tready (w_delete_resp_ready_in_reg), + .in_reg_tkeep (), + .tuser_clear ('d0) +); + +stream_reg #( + .TUSER_WIDTH(`PKT_HEAD_WIDTH), + .TDATA_WIDTH(`PKT_DATA_WIDTH) +) +OOAFindReqStream_Inst +( + .clk (clk), + .rst_n(~rst), + + .axis_tvalid (w_ooa_find_req_valid_axis), + .axis_tuser (wv_ooa_find_req_head_axis), + .axis_tdata ('d0), + .axis_tstart ('d0), + .axis_tlast ('d0), + .axis_tready (), + .axis_tkeep ('d0), + + .in_reg_tvalid (w_ooa_find_req_valid_in_reg), + .in_reg_tuser (wv_ooa_find_req_head_in_reg), + .in_reg_tdata (), + .in_reg_tstart (), + .in_reg_tlast (), + .in_reg_tready ('d1), + .in_reg_tkeep (), + .tuser_clear ('d0) +); + +stream_reg #( + .TUSER_WIDTH(`PKT_HEAD_WIDTH), + .TDATA_WIDTH(`PKT_SLOT_NUM_LOG + SLOT_NUM_LOG + 1) +) +OOAFindRespStream_Inst +( + .clk (clk), + .rst_n(~rst), + + .axis_tvalid (w_ooa_find_resp_valid_axis), + .axis_tuser ('d0), + .axis_tdata (wv_ooa_find_resp_data_axis), + .axis_tstart ('d0), + .axis_tlast ('d0), + .axis_tready (), + .axis_tkeep ('d0), + + .in_reg_tvalid (w_ooa_find_resp_valid_in_reg), + .in_reg_tuser (), + .in_reg_tdata (wv_ooa_find_resp_data_in_reg), + .in_reg_tstart (), + .in_reg_tlast (), + .in_reg_tready ('d1), + .in_reg_tkeep (), + .tuser_clear ('d0) +); + +stream_reg #( + .TUSER_WIDTH(`PKT_HEAD_WIDTH), + .TDATA_WIDTH(`PKT_DATA_WIDTH) +) +IOCFindReqStream_Inst +( + .clk (clk), + .rst_n(~rst), + + .axis_tvalid (w_ioc_find_req_valid_axis), + .axis_tuser (wv_ioc_find_req_head_axis), + .axis_tdata ('d0), + .axis_tstart ('d0), + .axis_tlast ('d0), + .axis_tready (), + .axis_tkeep ('d0), + + .in_reg_tvalid (w_ioc_find_req_valid_in_reg), + .in_reg_tuser (wv_ioc_find_req_head_in_reg), + .in_reg_tdata (), + .in_reg_tstart (), + .in_reg_tlast (), + .in_reg_tready ('d1), + .in_reg_tkeep (), + .tuser_clear ('d0) +); + +stream_reg #( + .TUSER_WIDTH(`PKT_HEAD_WIDTH), + .TDATA_WIDTH(`PKT_SLOT_NUM_LOG + SLOT_NUM_LOG + 1) +) +IOCFindRespStream_Inst +( + .clk (clk), + .rst_n(~rst), + + .axis_tvalid (w_ioc_find_resp_valid_axis), + .axis_tuser ('d0), + .axis_tdata (wv_ioc_find_resp_data_axis), + .axis_tstart ('d0), + .axis_tlast ('d0), + .axis_tready (), + .axis_tkeep ('d0), + + .in_reg_tvalid (w_ioc_find_resp_valid_in_reg), + .in_reg_tuser (), + .in_reg_tdata (wv_ioc_find_resp_data_in_reg), + .in_reg_tstart (), + .in_reg_tlast (), + .in_reg_tready ('d1), + .in_reg_tkeep (), + .tuser_clear ('d0) +); + +OutOfOrderAccept OutOfOrderAccept_Inst( + .clk(clk), + .rst(rst), + + .i_packet_in_valid(w_packet_in_valid_in_reg), + .iv_packet_in_head(wv_packet_in_head_in_reg), + .iv_packet_in_data(wv_packet_in_data_in_reg), + .i_packet_in_start(w_packet_in_start_in_reg), + .i_packet_in_last(w_packet_in_last_in_reg), + .o_packet_in_ready(w_packet_in_ready_in_reg), + + .ov_epsn_rd_index(ov_ooa_epsn_rd_index), + .iv_epsn_rd_data(iv_ooa_epsn_rd_data), + .o_epsn_wr_en(o_ooa_epsn_wr_en), + .ov_epsn_wr_index(ov_ooa_epsn_wr_index), + .ov_epsn_wr_data(ov_ooa_epsn_wr_data), + + .o_find_req_valid(w_ooa_find_req_valid_axis), + .ov_find_req_head(wv_ooa_find_req_head_axis), + .i_find_resp_valid(w_ooa_find_resp_valid_in_reg), + .iv_find_resp_data(wv_ooa_find_resp_data_in_reg), + + .iv_available_slot_num(wv_available_slot_num), + .o_insert_req_valid(w_insert_req_valid_axis), + .ov_insert_req_head(wv_insert_req_head_axis), + .ov_insert_req_data(wv_insert_req_data_axis), + .o_insert_req_start(w_insert_req_start_axis), + .o_insert_req_last(w_insert_req_last_axis), + .i_insert_req_ready(w_insert_req_ready_axis), + + .o_commit_valid(w_unreliable_pkt_in_valid_axis), + .ov_commit_head(wv_unreliable_pkt_in_head_axis), + .ov_commit_data(wv_unreliable_pkt_in_data_axis), + .o_commit_start(w_unreliable_pkt_in_start_axis), + .o_commit_last(w_unreliable_pkt_in_last_axis), + .i_commit_ready(w_unreliable_pkt_in_ready_axis), + + .o_ack_out_valid(w_packet_out_valid_axis), + .ov_ack_out_head(wv_packet_out_head_axis), + .ov_ack_out_data(wv_packet_out_data_axis), + .o_ack_out_start(w_packet_out_start_axis), + .o_ack_out_last(w_packet_out_last_axis), + .i_ack_out_ready(w_packet_out_ready_axis), + + .o_pkt_meta_wr_en(w_pkt_meta_wr_en), + .ov_pkt_meta_din(wv_pkt_meta_din), + .i_pkt_meta_prog_full(w_pkt_meta_prog_full) +); + +InOrderCommit InOrderCommit_Inst( + .clk(clk), + .rst(rst), + + .i_pkt_meta_empty(w_pkt_meta_empty), + .iv_pkt_meta_dout(wv_pkt_meta_dout), + .o_pkt_meta_rd_en(w_pkt_meta_rd_en), + + .ov_epsn_rd_index(ov_ioc_epsn_rd_index), + .iv_epsn_rd_data(iv_ioc_epsn_rd_data), + .o_epsn_wr_en(o_ioc_epsn_wr_en), + .ov_epsn_wr_index(ov_ioc_epsn_wr_index), + .ov_epsn_wr_data(ov_ioc_epsn_wr_data), + + .o_delete_req_valid(w_delete_req_valid_axis), + .ov_delete_req_head(wv_delete_req_head_axis), + .i_delete_req_ready(w_delete_req_ready_axis), + + .i_delete_resp_valid(w_delete_resp_valid_in_reg), + .iv_delete_resp_head(wv_delete_resp_head_in_reg), + .iv_delete_resp_data(wv_delete_resp_data_in_reg), + .i_delete_resp_start(w_delete_resp_start_in_reg), + .i_delete_resp_last(w_delete_resp_last_in_reg), + .o_delete_resp_ready(w_delete_resp_ready_in_reg), + + .o_find_req_valid(w_ioc_find_req_valid_axis), + .ov_find_req_head(wv_ioc_find_req_head_axis), + .i_find_resp_valid(w_ioc_find_resp_valid_in_reg), + .iv_find_resp_data(wv_ioc_find_resp_data_in_reg), + + .o_commit_valid(w_reliable_pkt_in_valid_axis), + .ov_commit_head(wv_reliable_pkt_in_head_axis), + .ov_commit_data(wv_reliable_pkt_in_data_axis), + .o_commit_start(w_reliable_pkt_in_start_axis), + .o_commit_last(w_reliable_pkt_in_last_axis), + .i_commit_ready(w_reliable_pkt_in_ready_axis) +); + +PacketBufferMgt +#( + .SLOT_WIDTH(`PKT_DATA_WIDTH), + .SLOT_NUM(`RECV_BUFFER_SLOT_NUM) +) +PacketBufferMgt_Inst( + .clk(clk), + .rst(rst), + + .ov_available_slot_num(wv_available_slot_num), + .i_insert_req_valid(w_insert_req_valid_in_reg), + .iv_insert_req_head(wv_insert_req_head_in_reg), + .iv_insert_req_data(wv_insert_req_data_in_reg), + .i_insert_req_start(w_insert_req_start_in_reg), + .i_insert_req_last(w_insert_req_last_in_reg), + .o_insert_req_ready(w_insert_req_ready_in_reg), + + .i_delete_req_valid(w_delete_req_valid_in_reg), + .iv_delete_req_head(wv_delete_req_head_in_reg), + .o_delete_req_ready(w_delete_req_ready_in_reg), + + .o_delete_resp_valid(w_delete_resp_valid_axis), + .ov_delete_resp_head(wv_delete_resp_head_axis), + .ov_delete_resp_data(wv_delete_resp_data_axis), + .o_delete_resp_start(w_delete_resp_start_axis), + .o_delete_resp_last(w_delete_resp_last_axis), + .i_delete_resp_ready(w_delete_resp_ready_axis), + + .i_find_req_valid_A(w_ooa_find_req_valid_in_reg), + .iv_find_req_head_A(wv_ooa_find_req_head_in_reg), + .o_find_resp_valid_A(w_ooa_find_resp_valid_axis), + .ov_find_resp_data_A(wv_ooa_find_resp_data_axis), + + .i_find_req_valid_B(w_ioc_find_req_valid_in_reg), + .iv_find_req_head_B(wv_ioc_find_req_head_in_reg), + .o_find_resp_valid_B(w_ioc_find_resp_valid_axis), + .ov_find_resp_data_B(wv_ioc_find_resp_data_axis), + + .i_get_req_valid('d0), + .iv_get_req_head('d0), + + .o_get_resp_valid(), + .ov_get_resp_head(), + .ov_get_resp_data(), + .o_get_resp_start(), + .o_get_resp_last(), + .i_get_resp_ready('d0) +); + +PacketArbiter CommitArbiter_Inst( + .clk(clk), + .rst(rst), + + .i_channel_0_valid(w_unreliable_pkt_in_valid_in_reg), + .iv_channel_0_head(wv_unreliable_pkt_in_head_in_reg), + .iv_channel_0_data(wv_unreliable_pkt_in_data_in_reg), + .i_channel_0_start(w_unreliable_pkt_in_start_in_reg), + .i_channel_0_last(w_unreliable_pkt_in_last_in_reg), + .o_channel_0_ready(w_unreliable_pkt_in_ready_in_reg), + + .i_channel_1_valid(w_reliable_pkt_in_valid_in_reg), + .iv_channel_1_head(wv_reliable_pkt_in_head_in_reg), + .iv_channel_1_data(wv_reliable_pkt_in_data_in_reg), + .i_channel_1_start(w_reliable_pkt_in_start_in_reg), + .i_channel_1_last(w_reliable_pkt_in_last_in_reg), + .o_channel_1_ready(w_reliable_pkt_in_ready_in_reg), + + .o_channel_out_valid(w_commit_valid_axis), + .ov_channel_out_head(wv_commit_head_axis), + .ov_channel_out_data(wv_commit_data_axis), + .o_channel_out_start(w_commit_start_axis), + .o_channel_out_last(w_commit_last_axis), + .i_channel_out_ready(w_commit_ready_axis) +); + +SyncFIFO_Template #( + .FIFO_WIDTH(`PKT_META_WIDTH), + .FIFO_DEPTH(32) +) +PacketMetaDataFIFO_inst +( + .clk(clk), + .rst(rst), + + .wr_en(w_pkt_meta_wr_en), + .din(wv_pkt_meta_din), + .prog_full(w_pkt_meta_prog_full), + .rd_en(w_pkt_meta_rd_en), + .dout(wv_pkt_meta_dout), + .empty(w_pkt_meta_empty), + .data_count() +); + +/*------------------------------------------- Submodules Instatiation : End -----------------------------------------*/ + +/*------------------------------------------- State Machine Definition : Begin --------------------------------------*/ +//Null +/*------------------------------------------- State Machine Definition : End ----------------------------------------*/ + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ +//Null +/*------------------------------------------- Variables Decode : End ------------------------------------------------*/ +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/TransportSubsystem/SelectiveRepeat.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/TransportSubsystem/SelectiveRepeat.v new file mode 100644 index 0000000000000000000000000000000000000000..e6fb71dd7cd47d95740b582c3c76bcd728088ce6 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/TransportSubsystem/SelectiveRepeat.v @@ -0,0 +1,597 @@ +/*------------------------------------------- Module Description : Begin ---------------------------------------------- +Name: SelectiveRepeat +Author: YangFan +Function: Deal with retransmission event. Triggered by two events: + 1. ACK : Release and Retransmit packet. Little penalty on performance. + 2. Timeout : Retransmit packet if timer expires. Huge penalty on performance. +--------------------------------------------- Module Decription : End -----------------------------------------------*/ + +/*------------------------------------------- Timescale Definition : Begin ------------------------------------------*/ +`timescale 1ns / 1ps +/*------------------------------------------- Timescale Definition : End --------------------------------------------*/ + +/*------------------------------------------- Included Files : Begin ------------------------------------------------*/ +`include "ib_constant_def_h.vh" +`include "common_function_def.vh" +`include "transport_subsystem_def.vh" +`include "global_def.vh" +/*------------------------------------------- Included Files : End --------------------------------------------------*/ + +/*------------------------------------------- Input/Output Definition : Begin ---------------------------------------*/ +module SelectiveRepeat #( + parameter SLOT_WIDTH = 512, + parameter SLOT_NUM = 512, + parameter SLOT_NUM_LOG = log2b(SLOT_NUM - 1) +)( + input wire clk, + input wire rst, + + //ACK in + input wire i_ack_in_valid, + input wire [`PKT_HEAD_WIDTH - 1 : 0] iv_ack_in_head, + input wire [`PKT_DATA_WIDTH - 1 : 0] iv_ack_in_data, + input wire i_ack_in_start, + input wire i_ack_in_last, + output wire o_ack_in_ready, + + //Timer event in + //Timer event format : {QPN} + input wire i_timer_event_empty, + input wire [`TIMER_EVENT_WIDTH - 1 : 0] iv_timer_event_dout, + output wire o_timer_event_rd_en, + + //Timer set out + //Timer set format : {ACTION , QPN} + input wire i_timer_set_prog_full, + output reg o_timer_set_wr_en, + output reg ov_timer_set_din, + + //Interface with PacketBufferMgt + output reg o_delete_req_valid, + output reg [`QP_NUM_LOG + `PSN_WIDTH + SLOT_NUM - 1 : 0] ov_delete_req_head, + input wire i_delete_req_ready, + + input wire i_delete_resp_valid, + input wire [`PKT_HEAD_WIDTH - 1 : 0] iv_delete_resp_head, + input wire [`PKT_DATA_WIDTH - 1 : 0] iv_delete_resp_data, + input wire i_delete_resp_start, + input wire i_delete_resp_last, + output wire o_delete_resp_ready, + + output reg o_get_req_valid, + output reg [`QP_NUM_LOG + `PSN_WIDTH + SLOT_NUM - 1 : 0] ov_get_req_head, + input wire i_get_req_ready, + + input wire i_get_resp_valid, + input wire [`PKT_HEAD_WIDTH - 1 : 0] iv_get_resp_head, + input wire [`PKT_DATA_WIDTH - 1 : 0] iv_get_resp_data, + input wire i_get_resp_start, + input wire i_get_resp_last, + output reg o_get_resp_ready, + + //Retransmitted packet out + output reg o_packet_out_valid, + output reg [`PKT_HEAD_WIDTH - 1 : 0] ov_packet_out_head, + output reg [`PKT_DATA_WIDTH - 1 : 0] ov_packet_out_data, + output reg o_packet_out_start, + output reg o_packet_out_last, + input wire i_packet_out_ready, + +//UPSN control + output reg [`QP_NUM_LOG - 1 : 0] ov_upsn_rd_index, + input wire [`PSN_WIDTH - 1 : 0] iv_upsn_rd_data, + output reg o_upsn_wr_en, + output reg [`QP_NUM_LOG - 1 : 0] ov_upsn_wr_index, + output reg [`PSN_WIDTH - 1 : 0] ov_upsn_wr_data +); + +/*------------------------------------------- Input/Output Definition : End -----------------------------------------*/ +wire [23:0] wv_qpn; +reg [23:0] qv_qpn; + +wire [23:0] wv_upsn; +reg [23:0] qv_upsn; + +wire [23:0] wv_epsn; +reg [23:0] qv_epsn; + +wire [23:0] wv_spsn; +reg [23:0] qv_spsn; + +wire [23:0] wv_tpsn; +reg [23:0] qv_tpsn; + +wire w_sack_valid; +reg q_sack_valid; + +wire w_loss_detected; +reg q_loss_detected; + +reg [23:0] qv_curPSN; + +wire [23:0] wv_lower_bound_indicator; +wire [23:0] wv_upper_bound_indicator; + +reg [23:0] qv_lower_bound_indicator; +reg [23:0] qv_upper_bound_indicator; + +reg [23:0] qv_release_upper_bound; +reg [23:0] qv_repeat_upper_bound; + +reg q_get_req_start; +reg q_delete_req_start; + +/*------------------------------------------- Local Variables Definition : Begin ------------------------------------*/ + + +/*------------------------------------------- Local Variables Definition : End --------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : Begin ---------------------------------------*/ +//NULL +/*------------------------------------------- Submodules Instatiation : End -----------------------------------------*/ + +/*------------------------------------------- State Machine Definition : Begin --------------------------------------*/ +reg [2:0] sr_cur_state; +reg [2:0] sr_next_state; + +parameter [2:0] SR_IDLE_s = 4'd1, + SR_JUDGE_s = 4'd2, + SR_CUMULATIVE_RELEASE_s = 4'd3, + SR_SELECTIVE_RELEASE_s = 4'd4, + SR_SELECTIVE_REPEAT_s = 4'd5, + SR_ERROR_s = 4'd6; + +always @(posedge clk or posedge rst) begin + if(rst) begin + sr_cur_state <= SR_IDLE_s; + end + else begin + sr_cur_state <= sr_next_state; + end +end + +always @(*) begin + case(sr_cur_state) + SR_IDLE_s: if(i_ack_in_valid) begin + sr_next_state = SR_JUDGE_s; + end + else if(!i_timer_event_empty) begin + sr_next_state = SR_SELECTIVE_REPEAT_s; + end + else begin + sr_next_state = SR_IDLE_s; + end + SR_JUDGE_s: if(wv_upsn == qv_epsn) begin + if(q_sack_valid) begin + sr_next_state = SR_SELECTIVE_RELEASE_s; + end + else begin + sr_next_state = SR_SELECTIVE_REPEAT_s; + end + end + else if(wv_upsn < qv_epsn) begin + sr_next_state = SR_CUMULATIVE_RELEASE_s; + end + else begin //UPSN cannot exceed EPSN + sr_next_state = SR_ERROR_s; + end + SR_CUMULATIVE_RELEASE_s: if(qv_curPSN == qv_release_upper_bound && i_delete_resp_last) begin + if(q_sack_valid) begin + sr_next_state = SR_SELECTIVE_RELEASE_s; + end + else if(q_loss_detected) begin + sr_next_state = SR_SELECTIVE_REPEAT_s; + end + else begin + sr_next_state = SR_IDLE_s; + end + end + else begin + sr_next_state = SR_CUMULATIVE_RELEASE_s; + end + SR_SELECTIVE_RELEASE_s: if(i_delete_resp_last) begin + if(q_loss_detected) begin + sr_next_state = SR_SELECTIVE_REPEAT_s; + end + else begin + sr_next_state = SR_IDLE_s; + end + end + else begin + sr_next_state = SR_SELECTIVE_RELEASE_s; + end + SR_SELECTIVE_REPEAT_s: if((qv_curPSN == qv_repeat_upper_bound) && i_get_resp_valid && i_get_resp_last && i_packet_out_ready) begin + sr_next_state = SR_IDLE_s; + end + else begin + sr_next_state = SR_SELECTIVE_REPEAT_s; + end + default: sr_next_state = SR_IDLE_s; + endcase +end + +/*------------------------------------------- State Machine Definition : End ----------------------------------------*/ + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ +//-- wv_qpn -- +assign wv_qpn = i_ack_in_valid ? iv_ack_in_head[`QPN_OFFSET] : iv_timer_event_dout[`TIMER_QPN_OFFSET]; + +//-- wv_upsn -- +assign wv_upsn = iv_upsn_rd_data; + +//-- wv_epsn -- +assign wv_epsn = iv_ack_in_data[`EPSN_OFFSET]; + +//-- wv_spsn -- +assign wv_spsn = iv_ack_in_data[`SPSN_OFFSET]; + +//-- wv_tpsn -- +assign wv_tpsn = iv_timer_event_dout[`TPSN_OFFSET]; + +//-- w_sack_valid -- +assign w_sack_valid = iv_ack_in_data[`SACK_OFFSET]; + +//-- w_loss_detected -- +assign w_loss_detected = iv_ack_in_data[`LOSS_OFFSET]; + +//-- wv_lower_bound_indicator -- +assign wv_lower_bound_indicator = iv_ack_in_data[`LOWER_BOUND_OFFSET]; + +//-- wv_upper_bound_indicator -- +assign wv_upper_bound_indicator = iv_ack_in_data[`UPPER_BOUND_OFFSET]; + +//-- qv_qpn -- +//-- qv_spsn -- +//-- qv_upsn -- +//-- qv_epsn -- +//-- q_sack_valid -- +//-- q_loss_detected -- +always @(posedge clk or posedge rst) begin + if(rst) begin + qv_qpn <= 'd0; + qv_spsn <= 'd0; + qv_upsn <= 'd0; + qv_epsn <= 'd0; + qv_tpsn <= 'd0; + qv_lower_bound_indicator <= 'd0; + qv_upper_bound_indicator <= 'd0; + q_sack_valid <= 'd0; + q_loss_detected <= 'd0; + end + else if(sr_cur_state == SR_IDLE_s && !i_ack_in_valid) begin + qv_qpn <= 'd0; + qv_spsn <= 'd0; + qv_upsn <= 'd0; + qv_epsn <= 'd0; + qv_tpsn <= 'd0; + qv_lower_bound_indicator <= 'd0; + qv_upper_bound_indicator <= 'd0; + q_sack_valid <= 'd0; + q_loss_detected <= 'd0; + end + else if(sr_cur_state == SR_IDLE_s && i_ack_in_valid) begin + qv_qpn <= wv_qpn; + qv_spsn <= wv_spsn; + qv_upsn <= wv_upsn; + qv_epsn <= wv_epsn; + qv_tpsn <= wv_tpsn; + qv_lower_bound_indicator <= wv_lower_bound_indicator; + qv_upper_bound_indicator <= wv_upper_bound_indicator; + q_sack_valid <= w_sack_valid; + q_loss_detected <= w_loss_detected; + end + else begin + qv_qpn <= qv_qpn; + qv_spsn <= qv_spsn; + qv_upsn <= qv_upsn; + qv_epsn <= qv_epsn; + qv_tpsn <= qv_tpsn; + qv_lower_bound_indicator <= qv_lower_bound_indicator; + qv_upper_bound_indicator <= qv_upper_bound_indicator; + q_sack_valid <= q_sack_valid; + q_loss_detected <= q_loss_detected; + end +end + +//-- qv_curPSN -- +always @(posedge clk or posedge rst) begin + if(rst) begin + qv_curPSN <= 'd0; + end + else if(sr_cur_state == SR_IDLE_s) begin + if(i_ack_in_valid) begin + qv_curPSN <= 'd0; + end + else if(!i_timer_event_empty) begin + qv_curPSN <= wv_tpsn; + end + else begin + qv_curPSN <= qv_curPSN; + end + end + else if(sr_cur_state == SR_JUDGE_s) begin + if(wv_upsn == qv_epsn) begin + if(q_sack_valid) begin + qv_curPSN <= qv_spsn; + end + else begin + qv_curPSN <= qv_lower_bound_indicator; + end + end + else if(wv_upsn < qv_epsn) begin + qv_curPSN = wv_upsn; + end + else begin //UPSN cannot exceed EPSN + qv_curPSN = `INVALID_PSN; + end + end + else if(sr_cur_state == SR_CUMULATIVE_RELEASE_s) begin + if(qv_curPSN < qv_release_upper_bound) begin + qv_curPSN <= i_delete_resp_last ? qv_curPSN + 'd1 : qv_curPSN; + end + else begin //qv_curPSN == qv_release_upper_bound + qv_curPSN <= !i_delete_resp_last ? qv_curPSN : + q_sack_valid ? qv_spsn : + q_loss_detected ? qv_lower_bound_indicator : 'd0; + end + end + else if(sr_cur_state == SR_SELECTIVE_RELEASE_s) begin + qv_curPSN <= (sr_next_state == SR_SELECTIVE_REPEAT_s) ? qv_lower_bound_indicator : qv_curPSN; + end + else if(sr_cur_state == SR_SELECTIVE_REPEAT_s) begin + if(qv_curPSN < qv_repeat_upper_bound) begin + qv_curPSN <= i_get_req_ready ? qv_curPSN + 'd1 : qv_curPSN; + end + else begin //qv_curPSN == qv_repeat_upper_bound + qv_curPSN <= i_get_req_ready ? 'd0 : qv_curPSN; + end + end + else begin + qv_curPSN <= qv_curPSN; + end +end + +//-- qv_release_upper_bound -- +always @(posedge clk or posedge rst) begin + if(rst) begin + qv_release_upper_bound <= 'd0; + end + else if(sr_cur_state == SR_IDLE_s) begin + qv_release_upper_bound <= 'd0; + end + else if(sr_cur_state == SR_JUDGE_s) begin + if(wv_upsn == qv_epsn) begin + if(q_sack_valid) begin + qv_release_upper_bound <= qv_spsn; + end + else begin + qv_release_upper_bound <= 'd0; + end + end + else if(wv_upsn < qv_epsn) begin + qv_release_upper_bound <= qv_epsn - 'd1; + end + else begin //UPSN cannot exceed EPSN + qv_release_upper_bound <= 'd0; + end + end + else if(sr_cur_state == SR_CUMULATIVE_RELEASE_s) begin + if(qv_curPSN == qv_release_upper_bound && i_delete_resp_last) begin + if(q_sack_valid) begin + qv_release_upper_bound <= qv_spsn; + end + else if(q_loss_detected) begin + qv_release_upper_bound <= 'd0; + end + else begin + qv_release_upper_bound <= 'd0; + end + end + else begin + qv_release_upper_bound <= qv_release_upper_bound; + end + end + else begin + qv_release_upper_bound <= qv_release_upper_bound; + end +end + +//-- qv_repeat_upper_bound -- +always @(posedge clk or posedge rst) begin + if(rst) begin + qv_repeat_upper_bound <= 'd0; + end + else if(sr_cur_state == SR_IDLE_s) begin + if(i_ack_in_valid) begin + qv_repeat_upper_bound <= 'd0; + end + else if(!i_timer_event_empty) begin + qv_repeat_upper_bound <= wv_tpsn; + end + else begin + qv_repeat_upper_bound <= 'd0; + end + end + else if(sr_cur_state == SR_JUDGE_s) begin + qv_repeat_upper_bound <= qv_upper_bound_indicator; + end + else begin + qv_repeat_upper_bound <= 'd0; + end +end + +//-- o_ack_in_ready -- //Always ready, ack lost is negligible +assign o_ack_in_ready = (sr_cur_state != SR_IDLE_s) && (sr_next_state == SR_IDLE_s); + +//-- o_timer_event_rd_en -- //Always read, timer event lost is negligible +assign o_timer_event_rd_en = 'd1; + +//-- o_delete_req_valid -- +//-- ov_delete_req_head -- +always @(*) begin + if(rst) begin + o_delete_req_valid = 'd0; + ov_delete_req_head = 'd0; + end + else if(sr_cur_state == SR_CUMULATIVE_RELEASE_s || sr_cur_state == SR_SELECTIVE_RELEASE_s) begin + o_delete_req_valid = q_delete_req_start ? 'd1 : 'd0; + ov_delete_req_head = {qv_curPSN, qv_qpn}; + end + else begin + o_delete_req_valid = 'd0; + ov_delete_req_head = 'd0; + end +end + +//-- q_delete_req_start -- +always @(posedge clk or posedge rst) begin + if(rst) begin + q_delete_req_start <= 'd0; + end + else if(sr_cur_state == SR_IDLE_s) begin + q_delete_req_start <= 'd0; + end + else if(sr_cur_state == SR_JUDGE_s && (sr_next_state == SR_SELECTIVE_RELEASE_s || sr_next_state == SR_CUMULATIVE_RELEASE_s)) begin + q_delete_req_start <= 'd1; + end + else if(sr_cur_state == SR_SELECTIVE_RELEASE_s || sr_cur_state == SR_CUMULATIVE_RELEASE_s) begin + if(q_delete_req_start) begin + q_delete_req_start <= 'd0; + end + else if(i_delete_resp_valid && i_delete_resp_last) begin + q_delete_req_start <= 'd1; + end + else begin + q_delete_req_start <= q_delete_req_start; + end + end + else begin + q_delete_req_start <= q_delete_req_start; + end +end + +//-- o_delete_resp_ready -- //Always ready since we don't need to transfer deleted packet +assign o_delete_resp_ready = 'd1; + +//-- q_get_req_start -- +always @(posedge clk or posedge rst) begin + if(rst) begin + q_get_req_start <= 'd0; + end + else if(sr_cur_state != SR_SELECTIVE_REPEAT_s && sr_next_state == SR_SELECTIVE_REPEAT_s) begin + q_get_req_start <= 'd1; + end + else if(sr_cur_state == SR_SELECTIVE_REPEAT_s) begin + if(i_get_req_ready) begin + q_get_req_start <= 'd0; + end + else if(i_get_resp_valid && i_get_resp_last && i_packet_out_ready) begin + q_get_req_start <= 'd1; + end + else begin + q_get_req_start <= q_get_req_start; + end + end + else begin + q_get_req_start <= q_get_req_start; + end +end + +//-- o_get_req_valid -- +//-- ov_get_req_head -- +always @(*) begin + if(rst) begin + o_get_req_valid = 'd0; + ov_get_req_head = 'd0; + end + else if(sr_cur_state == SR_SELECTIVE_REPEAT_s) begin + o_get_req_valid = q_get_req_start ? 'd1 : 'd0; + ov_get_req_head = {qv_curPSN, qv_qpn}; + end + else begin + o_get_req_valid = 'd0; + ov_get_req_head = 'd0; + end +end + +//-- o_get_resp_ready -- +always @(*) begin + if(rst) begin + o_get_resp_ready = 'd0; + end + else if(sr_cur_state == SR_SELECTIVE_REPEAT_s && i_packet_out_ready) begin + o_get_resp_ready = 'd1; + end + else begin + o_get_resp_ready = 'd0; + end +end + +//-- o_packet_out_valid -- +//-- ov_packet_out_head -- +//-- ov_packet_out_data -- +//-- o_packet_out_start -- +//-- o_packet_out_last -- +always @(*) begin + if(rst) begin + o_packet_out_valid = 'd0; + ov_packet_out_head = 'd0; + ov_packet_out_data = 'd0; + o_packet_out_start = 'd0; + o_packet_out_last = 'd0; + end + else if(sr_cur_state == SR_SELECTIVE_REPEAT_s) begin + o_packet_out_valid = i_get_resp_valid; + ov_packet_out_head = iv_get_resp_head; + ov_packet_out_data = iv_get_resp_data; + o_packet_out_start = i_get_resp_start; + o_packet_out_last = i_get_resp_last; + end + else begin + o_packet_out_valid = 'd0; + ov_packet_out_head = 'd0; + ov_packet_out_data = 'd0; + o_packet_out_start = 'd0; + o_packet_out_last = 'd0; + end +end + +//-- ov_upsn_rd_index -- +assign ov_upsn_rd_index = (sr_cur_state == SR_IDLE_s) ? wv_qpn : qv_qpn; + +//-- o_upsn_wr_en -- +//-- ov_upsn_wr_index -- +//-- ov_upsn_wr_data -- +always @(*) begin + if(rst) begin + o_upsn_wr_en = 'd0; + ov_upsn_wr_index = 'd0; + ov_upsn_wr_data = 'd0; + end + else if(sr_cur_state == SR_CUMULATIVE_RELEASE_s) begin + o_upsn_wr_en = 'd1; + ov_upsn_wr_index = qv_qpn; + ov_upsn_wr_data = qv_curPSN + 'd1; + end + else begin + o_upsn_wr_en = 'd0; + ov_upsn_wr_index = 'd0; + ov_upsn_wr_data = 'd0; + end +end + +//-- o_timer_set_wr_en -- +//-- ov_timer_set_din -- +always @(*) begin + if(rst) begin + o_timer_set_wr_en = 'd0; + ov_timer_set_din = 'd0; + end + else begin + o_timer_set_wr_en = 'd0; + ov_timer_set_din = 'd0; + end +end + +/*------------------------------------------- Variables Decode : End ------------------------------------------------*/ +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/TransportSubsystem/SendControl.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/TransportSubsystem/SendControl.v new file mode 100644 index 0000000000000000000000000000000000000000..fa0fb1721667f7d11ea90556a30b47c6b0fcbfe3 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/TransportSubsystem/SendControl.v @@ -0,0 +1,780 @@ +/*------------------------------------------- Module Description : Begin ---------------------------------------------- +Name: SendControl +Author: YangFan +Function: Wrapper for InOrderInject, SelectiveRepeat, and PacketBufferMgt. +--------------------------------------------- Module Decription : End -----------------------------------------------*/ + +/*------------------------------------------- Timescale Definition : Begin ------------------------------------------*/ +`timescale 1ns / 1ps +/*------------------------------------------- Timescale Definition : End --------------------------------------------*/ + +/*------------------------------------------- Included Files : Begin ------------------------------------------------*/ +`include "ib_constant_def_h.vh" +`include "common_function_def.vh" +`include "transport_subsystem_def.vh" +`include "global_def.vh" +/*------------------------------------------- Included Files : End --------------------------------------------------*/ + +/*------------------------------------------- Input/Output Definition : Begin ---------------------------------------*/ +module SendControl #( + parameter SLOT_WIDTH = 512, + parameter SLOT_NUM = 512, + parameter SLOT_NUM_LOG = log2b(SLOT_NUM - 1) +)( + input wire clk, + input wire rst, + +//Packet-In + input wire i_packet_in_valid, + input wire [`PKT_HEAD_WIDTH - 1 : 0] iv_packet_in_head, + input wire [`PKT_DATA_WIDTH - 1 : 0] iv_packet_in_data, + input wire i_packet_in_start, + input wire i_packet_in_last, + output wire o_packet_in_ready, + +//NPSN control + output wire o_npsn_wr_en, + output wire [`QP_NUM_LOG - 1 : 0] ov_npsn_wr_index, + output wire [`PSN_WIDTH - 1 : 0] ov_npsn_wr_data, + output wire [`QP_NUM_LOG - 1 : 0] ov_npsn_rd_index, + input wire [`PSN_WIDTH - 1 : 0] iv_npsn_rd_data, + +//Packet-Out + output wire o_packet_out_valid, + output wire [`PKT_HEAD_WIDTH - 1 : 0] ov_packet_out_head, + output wire [`PKT_DATA_WIDTH - 1 : 0] ov_packet_out_data, + output wire o_packet_out_start, + output wire o_packet_out_last, + input wire i_packet_out_ready, + + //ACK in + input wire i_ack_in_valid, + input wire [`PKT_HEAD_WIDTH - 1 : 0] iv_ack_in_head, + input wire [`PKT_DATA_WIDTH - 1 : 0] iv_ack_in_data, + input wire i_ack_in_start, + input wire i_ack_in_last, + output wire o_ack_in_ready, + +//UPSN control + output wire [`QP_NUM_LOG - 1 : 0] ov_upsn_rd_index, + input wire [`PSN_WIDTH - 1 : 0] iv_upsn_rd_data, + output wire o_upsn_wr_en, + output wire [`QP_NUM_LOG - 1 : 0] ov_upsn_wr_index, + output wire [`PSN_WIDTH - 1 : 0] ov_upsn_wr_data +); +/*------------------------------------------- Input/Output Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Variables Definition : Begin ------------------------------------*/ +wire w_packet_in_valid_in_reg; +wire [`PKT_HEAD_WIDTH - 1 : 0] wv_packet_in_head_in_reg; +wire [`PKT_DATA_WIDTH - 1 : 0] wv_packet_in_data_in_reg; +wire w_packet_in_start_in_reg; +wire w_packet_in_last_in_reg; +wire w_packet_in_ready_in_reg; + +wire w_packet_out_valid_axis; +wire [`PKT_HEAD_WIDTH - 1 : 0] wv_packet_out_head_axis; +wire [`PKT_DATA_WIDTH - 1 : 0] wv_packet_out_data_axis; +wire w_packet_out_start_axis; +wire w_packet_out_last_axis; +wire w_packet_out_ready_axis; + +wire w_ack_in_valid_in_reg; +wire [`PKT_HEAD_WIDTH - 1 : 0] wv_ack_in_head_in_reg; +wire [`PKT_DATA_WIDTH - 1 : 0] wv_ack_in_data_in_reg; +wire w_ack_in_start_in_reg; +wire w_ack_in_last_in_reg; +wire w_ack_in_ready_in_reg; + +wire w_inject_valid_axis; +wire [`PKT_HEAD_WIDTH - 1 : 0] wv_inject_head_axis; +wire [`PKT_DATA_WIDTH - 1 : 0] wv_inject_data_axis; +wire w_inject_start_axis; +wire w_inject_last_axis; +wire w_inject_ready_axis; + +wire w_inject_valid_in_reg; +wire [`PKT_HEAD_WIDTH - 1 : 0] wv_inject_head_in_reg; +wire [`PKT_DATA_WIDTH - 1 : 0] wv_inject_data_in_reg; +wire w_inject_start_in_reg; +wire w_inject_last_in_reg; +wire w_inject_ready_in_reg; + +wire w_retrans_valid_axis; +wire [`PKT_HEAD_WIDTH - 1 : 0] wv_retrans_head_axis; +wire [`PKT_DATA_WIDTH - 1 : 0] wv_retrans_data_axis; +wire w_retrans_start_axis; +wire w_retrans_last_axis; +wire w_retrans_ready_axis; + +wire w_retrans_valid_in_reg; +wire [`PKT_HEAD_WIDTH - 1 : 0] wv_retrans_head_in_reg; +wire [`PKT_DATA_WIDTH - 1 : 0] wv_retrans_data_in_reg; +wire w_retrans_start_in_reg; +wire w_retrans_last_in_reg; +wire w_retrans_ready_in_reg; + +wire [`SEND_BUFFER_SLOT_NUM_LOG - 1 : 0] wv_available_slot_num; +wire w_insert_req_valid_axis; +wire [SLOT_NUM - 1 : 0] wv_insert_req_head_axis; +wire [`PKT_DATA_WIDTH - 1 : 0] wv_insert_req_data_axis; +wire w_insert_req_start_axis; +wire w_insert_req_last_axis; +wire w_insert_req_ready_axis; + +wire w_insert_req_valid_in_reg; +wire [SLOT_NUM - 1 : 0] wv_insert_req_head_in_reg; +wire [`PKT_DATA_WIDTH - 1 : 0] wv_insert_req_data_in_reg; +wire w_insert_req_start_in_reg; +wire w_insert_req_last_in_reg; +wire w_insert_req_ready_in_reg; + +wire w_delete_req_valid_axis; +wire [`QP_NUM_LOG + `PSN_WIDTH + SLOT_NUM - 1 : 0] wv_delete_req_head_axis; +wire w_delete_req_ready_axis; + +wire w_delete_req_valid_in_reg; +wire [`QP_NUM_LOG + `PSN_WIDTH + SLOT_NUM - 1 : 0] wv_delete_req_head_in_reg; +wire w_delete_req_ready_in_reg; + +wire w_delete_resp_valid_axis; +wire [`PKT_HEAD_WIDTH - 1 : 0] wv_delete_resp_head_axis; +wire [`PKT_DATA_WIDTH - 1 : 0] wv_delete_resp_data_axis; +wire w_delete_resp_start_axis; +wire w_delete_resp_last_axis; +wire w_delete_resp_ready_axis; + +wire w_delete_resp_valid_in_reg; +wire [`PKT_HEAD_WIDTH - 1 : 0] wv_delete_resp_head_in_reg; +wire [`PKT_DATA_WIDTH - 1 : 0] wv_delete_resp_data_in_reg; +wire w_delete_resp_start_in_reg; +wire w_delete_resp_last_in_reg; +wire w_delete_resp_ready_in_reg; + +wire w_find_req_valid_A_axis; +wire [`QP_NUM_LOG + `PSN_WIDTH - 1 : 0] wv_find_req_head_A_axis; +wire w_find_resp_valid_A_axis; +wire [`PKT_SLOT_NUM_LOG + SLOT_NUM_LOG : 0] wv_find_resp_data_A_axis; + +wire w_find_req_valid_A_in_reg; +wire [`QP_NUM_LOG + `PSN_WIDTH - 1 : 0] wv_find_req_head_A_in_reg; +wire w_find_resp_valid_A_in_reg; +wire [`PKT_SLOT_NUM_LOG + SLOT_NUM_LOG : 0] wv_find_resp_data_A_in_reg; + +wire w_find_req_valid_B_axis; +wire [`QP_NUM_LOG + `PSN_WIDTH - 1 : 0] wv_find_req_head_B_axis; +wire w_find_resp_valid_B_axis; +wire [`PKT_SLOT_NUM_LOG + SLOT_NUM_LOG : 0] wv_find_resp_data_B_axis; + +wire w_find_req_valid_B_in_reg; +wire [`QP_NUM_LOG + `PSN_WIDTH - 1 : 0] wv_find_req_head_B_in_reg; +wire w_find_resp_valid_B_in_reg; +wire [`PKT_SLOT_NUM_LOG + SLOT_NUM_LOG : 0] wv_find_resp_data_B_in_reg; + +wire w_get_req_valid_axis; +wire [`QP_NUM_LOG + `PSN_WIDTH + SLOT_NUM - 1 : 0] wv_get_req_head_axis; + +wire w_get_req_valid_in_reg; +wire [`QP_NUM_LOG + `PSN_WIDTH + SLOT_NUM - 1 : 0] wv_get_req_head_in_reg; + +wire w_get_resp_valid_axis; +wire [`PKT_HEAD_WIDTH - 1 : 0] wv_get_resp_head_axis; +wire [`PKT_DATA_WIDTH - 1 : 0] wv_get_resp_data_axis; +wire w_get_resp_start_axis; +wire w_get_resp_last_axis; +wire w_get_resp_ready_axis; + +wire w_get_resp_valid_in_reg; +wire [`PKT_HEAD_WIDTH - 1 : 0] wv_get_resp_head_in_reg; +wire [`PKT_DATA_WIDTH - 1 : 0] wv_get_resp_data_in_reg; +wire w_get_resp_start_in_reg; +wire w_get_resp_last_in_reg; +wire w_get_resp_ready_in_reg; + +wire w_time_out_empty; +wire [`TIMER_EVENT_WIDTH - 1 : 0] wv_time_out_dout; +wire w_time_out_rd_en; + +wire w_timer_set_prog_full_A; +wire w_timer_set_wr_en_A; +wire [`TIMER_CMD_WIDTH - 1 : 0] wv_timer_set_din_A; + +wire w_timer_set_prog_full_B; +wire w_timer_set_wr_en_B; +wire [`TIMER_CMD_WIDTH - 1 : 0] wv_timer_set_din_B; +/*------------------------------------------- Local Variables Definition : End --------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : Begin ---------------------------------------*/ +stream_fifo #( + .TUSER_WIDTH(`PKT_HEAD_WIDTH), + .TDATA_WIDTH(`PKT_DATA_WIDTH) +) +PacketInFIFO_Inst +( + .clk (clk), + .rst_n(~rst), + + .axis_tvalid (i_packet_in_valid), + .axis_tuser (iv_packet_in_head), + .axis_tdata (iv_packet_in_data), + .axis_tstart (i_packet_in_start), + .axis_tlast (i_packet_in_last), + .axis_tready (o_packet_in_ready), + .axis_tkeep ('d0), + + .in_reg_tvalid (w_packet_in_valid_in_reg), + .in_reg_tuser (wv_packet_in_head_in_reg), + .in_reg_tdata (wv_packet_in_data_in_reg), + .in_reg_tstart (w_packet_in_start_in_reg), + .in_reg_tlast (w_packet_in_last_in_reg), + .in_reg_tready (w_packet_in_ready_in_reg), + .in_reg_tkeep (), + .tuser_clear ('d0) +); + +stream_fifo #( + .TUSER_WIDTH(`PKT_HEAD_WIDTH), + .TDATA_WIDTH(`PKT_DATA_WIDTH) +) +PacketOutFIFO_Inst +( + .clk (clk), + .rst_n(~rst), + + .axis_tvalid (w_packet_out_valid_axis), + .axis_tuser (wv_packet_out_head_axis), + .axis_tdata (wv_packet_out_data_axis), + .axis_tstart (w_packet_out_start_axis), + .axis_tlast (w_packet_out_last_axis), + .axis_tready (w_packet_out_ready_axis), + .axis_tkeep ('d0), + + .in_reg_tvalid (o_packet_out_valid), + .in_reg_tuser (ov_packet_out_head), + .in_reg_tdata (ov_packet_out_data), + .in_reg_tstart (o_packet_out_start), + .in_reg_tlast (o_packet_out_last), + .in_reg_tready (i_packet_out_ready), + .in_reg_tkeep (), + .tuser_clear ('d0) +); + +stream_fifo #( + .TUSER_WIDTH(`PKT_HEAD_WIDTH), + .TDATA_WIDTH(`PKT_DATA_WIDTH) +) +ACKFIFO_Inst +( + .clk (clk), + .rst_n(~rst), + + .axis_tvalid (i_ack_in_valid), + .axis_tuser (iv_ack_in_head), + .axis_tdata (iv_ack_in_data), + .axis_tstart (i_ack_in_start), + .axis_tlast (i_ack_in_last), + .axis_tready (o_ack_in_ready), + .axis_tkeep ('d0), + + .in_reg_tvalid (w_ack_in_valid_in_reg), + .in_reg_tuser (wv_ack_in_head_in_reg), + .in_reg_tdata (wv_ack_in_data_in_reg), + .in_reg_tstart (w_ack_in_start_in_reg), + .in_reg_tlast (w_ack_in_last_in_reg), + .in_reg_tready (w_ack_in_ready_in_reg), + .in_reg_tkeep (), + .tuser_clear ('d0) +); + +stream_fifo #( + .TUSER_WIDTH(`PKT_HEAD_WIDTH), + .TDATA_WIDTH(`PKT_DATA_WIDTH) +) +InjectFIFO_Inst +( + .clk (clk), + .rst_n(~rst), + + .axis_tvalid (w_inject_valid_axis), + .axis_tuser (wv_inject_head_axis), + .axis_tdata (wv_inject_data_axis), + .axis_tstart (w_inject_start_axis), + .axis_tlast (w_inject_last_axis), + .axis_tready (w_inject_ready_axis), + .axis_tkeep ('d0), + + .in_reg_tvalid (w_inject_valid_in_reg), + .in_reg_tuser (wv_inject_head_in_reg), + .in_reg_tdata (wv_inject_data_in_reg), + .in_reg_tstart (w_inject_start_in_reg), + .in_reg_tlast (w_inject_last_in_reg), + .in_reg_tready (w_inject_ready_in_reg), + .in_reg_tkeep (), + .tuser_clear ('d0) +); + +stream_fifo #( + .TUSER_WIDTH(`PKT_HEAD_WIDTH), + .TDATA_WIDTH(`PKT_DATA_WIDTH) +) +RetransFIFO_Inst +( + .clk (clk), + .rst_n(~rst), + + .axis_tvalid (w_retrans_valid_axis), + .axis_tuser (wv_retrans_head_axis), + .axis_tdata (wv_retrans_data_axis), + .axis_tstart (w_retrans_start_axis), + .axis_tlast (w_retrans_last_axis), + .axis_tready (w_retrans_ready_axis), + .axis_tkeep ('d0), + + .in_reg_tvalid (w_retrans_valid_in_reg), + .in_reg_tuser (wv_retrans_head_in_reg), + .in_reg_tdata (wv_retrans_data_in_reg), + .in_reg_tstart (w_retrans_start_in_reg), + .in_reg_tlast (w_retrans_last_in_reg), + .in_reg_tready (w_retrans_ready_in_reg), + .in_reg_tkeep (), + .tuser_clear ('d0) +); + +stream_reg #( + .TUSER_WIDTH(`PKT_HEAD_WIDTH), + .TDATA_WIDTH(`PKT_DATA_WIDTH) +) +InsertStream_Inst +( + .clk (clk), + .rst_n(~rst), + + .axis_tvalid (w_insert_req_valid_axis), + .axis_tuser (wv_insert_req_head_axis), + .axis_tdata (wv_insert_req_data_axis), + .axis_tstart (w_insert_req_start_axis), + .axis_tlast (w_insert_req_last_axis), + .axis_tready (w_insert_req_ready_axis), + .axis_tkeep ('d0), + + .in_reg_tvalid (w_insert_req_valid_in_reg), + .in_reg_tuser (wv_insert_req_head_in_reg), + .in_reg_tdata (wv_insert_req_data_in_reg), + .in_reg_tstart (w_insert_req_start_in_reg), + .in_reg_tlast (w_insert_req_last_in_reg), + .in_reg_tready (w_insert_req_ready_in_reg), + .in_reg_tkeep (), + .tuser_clear ('d0) +); + +stream_reg #( + .TUSER_WIDTH(`PKT_HEAD_WIDTH), + .TDATA_WIDTH(`PKT_DATA_WIDTH) +) +DeleteReqStream_Inst +( + .clk (clk), + .rst_n(~rst), + + .axis_tvalid (w_delete_req_valid_axis), + .axis_tuser (wv_delete_req_head_axis), + .axis_tdata ('d0), + .axis_tstart ('d0), + .axis_tlast ('d0), + .axis_tready (w_delete_req_ready_axis), + .axis_tkeep ('d0), + + .in_reg_tvalid (w_delete_req_valid_in_reg), + .in_reg_tuser (wv_delete_req_head_in_reg), + .in_reg_tdata (wv_delete_req_data_in_reg), + .in_reg_tstart (w_delete_req_start_in_reg), + .in_reg_tlast (w_delete_req_last_in_reg), + .in_reg_tready (w_delete_req_ready_in_reg), + .in_reg_tkeep (), + .tuser_clear ('d0) +); + +stream_reg #( + .TUSER_WIDTH(`PKT_HEAD_WIDTH), + .TDATA_WIDTH(`PKT_DATA_WIDTH) +) +DeleteRespStream_Inst +( + .clk (clk), + .rst_n(~rst), + + .axis_tvalid (w_delete_resp_valid_axis), + .axis_tuser (wv_delete_resp_head_axis), + .axis_tdata (wv_delete_resp_data_axis), + .axis_tstart (w_delete_resp_start_axis), + .axis_tlast (w_delete_resp_last_axis), + .axis_tready (w_delete_resp_ready_axis), + .axis_tkeep ('d0), + + .in_reg_tvalid (w_delete_resp_valid_in_reg), + .in_reg_tuser (wv_delete_resp_head_in_reg), + .in_reg_tdata (wv_delete_resp_data_in_reg), + .in_reg_tstart (w_delete_resp_start_in_reg), + .in_reg_tlast (w_delete_resp_last_in_reg), + .in_reg_tready (w_delete_resp_ready_in_reg), + .in_reg_tkeep (), + .tuser_clear ('d0) +); + +stream_reg #( + .TUSER_WIDTH(`PKT_HEAD_WIDTH), + .TDATA_WIDTH(`PKT_DATA_WIDTH) +) +FindReqStreamA_Inst +( + .clk (clk), + .rst_n(~rst), + + .axis_tvalid (w_find_req_valid_A_axis), + .axis_tuser (wv_find_req_head_A_axis), + .axis_tdata ('d0), + .axis_tstart ('d0), + .axis_tlast ('d0), + .axis_tready (), + .axis_tkeep ('d0), + + .in_reg_tvalid (w_find_req_valid_A_in_reg), + .in_reg_tuser (wv_find_req_head_A_in_reg), + .in_reg_tdata (), + .in_reg_tstart (), + .in_reg_tlast (), + .in_reg_tready ('d1), + .in_reg_tkeep (), + .tuser_clear ('d0) +); + +stream_reg #( + .TUSER_WIDTH(`PKT_HEAD_WIDTH), + .TDATA_WIDTH(`PKT_SLOT_NUM_LOG + SLOT_NUM_LOG + 1) +) +FindRespStreamA_Inst +( + .clk (clk), + .rst_n(~rst), + + .axis_tvalid (w_find_resp_valid_A_axis), + .axis_tuser ('d0), + .axis_tdata (wv_find_resp_data_A_axis), + .axis_tstart ('d0), + .axis_tlast ('d0), + .axis_tready (), + .axis_tkeep ('d0), + + .in_reg_tvalid (w_find_resp_valid_A_in_reg), + .in_reg_tuser (), + .in_reg_tdata (wv_find_resp_head_A_in_reg), + .in_reg_tstart (), + .in_reg_tlast (), + .in_reg_tready ('d1), + .in_reg_tkeep (), + .tuser_clear ('d0) +); + +stream_reg #( + .TUSER_WIDTH(`PKT_HEAD_WIDTH), + .TDATA_WIDTH(`PKT_DATA_WIDTH) +) +FindReqStreamB_Inst +( + .clk (clk), + .rst_n(~rst), + + .axis_tvalid (w_find_req_valid_B_axis), + .axis_tuser (wv_find_req_head_B_axis), + .axis_tdata ('d0), + .axis_tstart ('d0), + .axis_tlast ('d0), + .axis_tready (), + .axis_tkeep ('d0), + + .in_reg_tvalid (w_find_req_valid_B_in_reg), + .in_reg_tuser (wv_find_req_head_B_in_reg), + .in_reg_tdata (), + .in_reg_tstart (), + .in_reg_tlast (), + .in_reg_tready ('d1), + .in_reg_tkeep (), + .tuser_clear ('d0) +); + +stream_reg #( + .TUSER_WIDTH(`PKT_HEAD_WIDTH), + .TDATA_WIDTH(`PKT_SLOT_NUM_LOG + SLOT_NUM_LOG + 1) +) +FindRespStreamB_Inst +( + .clk (clk), + .rst_n(~rst), + + .axis_tvalid (w_find_resp_valid_B_axis), + .axis_tuser ('d0), + .axis_tdata (wv_find_resp_data_B_axis), + .axis_tstart ('d0), + .axis_tlast ('d0), + .axis_tready (), + .axis_tkeep ('d0), + + .in_reg_tvalid (w_find_resp_valid_B_in_reg), + .in_reg_tuser (), + .in_reg_tdata (wv_find_resp_head_B_in_reg), + .in_reg_tstart (), + .in_reg_tlast (), + .in_reg_tready ('d1), + .in_reg_tkeep (), + .tuser_clear ('d0) +); + +stream_reg #( + .TUSER_WIDTH(`PKT_HEAD_WIDTH), + .TDATA_WIDTH(`PKT_DATA_WIDTH) +) +GetReqStream_Inst +( + .clk (clk), + .rst_n(~rst), + + .axis_tvalid (w_get_req_valid_axis), + .axis_tuser (wv_get_req_head_axis), + .axis_tdata ('d0), + .axis_tstart ('d0), + .axis_tlast ('d0), + .axis_tready (), + .axis_tkeep ('d0), + + .in_reg_tvalid (w_get_req_valid_in_reg), + .in_reg_tuser (wv_get_req_head_in_reg), + .in_reg_tdata (), + .in_reg_tstart (), + .in_reg_tlast (), + .in_reg_tready ('d1), + .in_reg_tkeep (), + .tuser_clear ('d0) +); + +stream_reg #( + .TUSER_WIDTH(`PKT_HEAD_WIDTH), + .TDATA_WIDTH(`PKT_DATA_WIDTH) +) +GetRespStream_Inst +( + .clk (clk), + .rst_n(~rst), + + .axis_tvalid (w_get_resp_valid_axis), + .axis_tuser (wv_get_resp_head_axis), + .axis_tdata (wv_get_resp_data_axis), + .axis_tstart (w_get_resp_start_axis), + .axis_tlast (w_get_resp_last_axis), + .axis_tready (w_get_resp_ready_axis), + .axis_tkeep ('d0), + + .in_reg_tvalid (w_get_resp_valid_in_reg), + .in_reg_tuser (wv_get_resp_head_in_reg), + .in_reg_tdata (wv_get_resp_data_in_reg), + .in_reg_tstart (w_get_resp_start_in_reg), + .in_reg_tlast (w_get_resp_last_in_reg), + .in_reg_tready (w_get_resp_ready_in_reg), + .in_reg_tkeep (), + .tuser_clear ('d0) +); + +InOrderInject InOrderInject_Inst( + .clk(clk), + .rst(rst), + + .i_packet_in_valid(w_packet_in_valid_in_reg), + .iv_packet_in_head(wv_packet_in_head_in_reg), + .iv_packet_in_data(wv_packet_in_data_in_reg), + .i_packet_in_start(w_packet_in_start_in_reg), + .i_packet_in_last(w_packet_in_last_in_reg), + .o_packet_in_ready(w_packet_in_ready_in_reg), + + .o_npsn_wr_en(o_npsn_wr_en), + .ov_npsn_wr_index(ov_npsn_wr_index), + .ov_npsn_wr_data(ov_npsn_wr_data), + .ov_npsn_rd_index(ov_npsn_rd_index), + .iv_npsn_rd_data(iv_npsn_rd_data), + + .iv_available_slot_num(wv_available_slot_num), + .o_insert_req_valid(w_insert_req_valid_axis), + .ov_insert_req_head(wv_insert_req_head_axis), + .ov_insert_req_data(wv_insert_req_data_axis), + .o_insert_req_start(w_insert_req_start_axis), + .o_insert_req_last(w_insert_req_last_axis), + .i_insert_req_ready(w_insert_req_ready_axis), + + .i_tc_prog_full(w_timer_set_prog_full_A), + .o_tc_wr_en(w_timer_set_wr_en_A), + .ov_tc_din(wv_timer_set_din_A), + + + .o_packet_out_valid(w_inject_valid_axis), + .ov_packet_out_head(wv_inject_head_axis), + .ov_packet_out_data(wv_inject_data_axis), + .o_packet_out_start(w_inject_start_axis), + .o_packet_out_last(w_inject_last_axis), + .i_packet_out_ready(w_inject_ready_axis) +); + +SelectiveRepeat SelectiveRepeat_Inst( + .clk(clk), + .rst(rst), + + .i_ack_in_valid(w_ack_in_valid_in_reg), + .iv_ack_in_head(wv_ack_in_head_in_reg), + .iv_ack_in_data(wv_ack_in_data_in_reg), + .i_ack_in_start(w_ack_in_start_in_reg), + .i_ack_in_last(w_ack_in_last_in_reg), + .o_ack_in_ready(w_ack_in_ready_in_reg), + + .i_timer_event_empty(w_time_out_empty), + .iv_timer_event_dout(wv_time_out_dout), + .o_timer_event_rd_en(w_time_out_rd_en), + + .i_timer_set_prog_full(w_timer_set_prog_full_B), + .o_timer_set_wr_en(w_timer_set_wr_en_B), + .ov_timer_set_din(wv_timer_set_din_B), + + .o_delete_req_valid(w_delete_req_valid_axis), + .ov_delete_req_head(wv_delete_req_head_axis), + .i_delete_req_ready(w_delete_req_ready_axis), + + .i_delete_resp_valid(w_delete_resp_valid_in_reg), + .iv_delete_resp_head(wv_delete_resp_head_in_reg), + .iv_delete_resp_data(wv_delete_resp_data_in_reg), + .i_delete_resp_start(w_delete_resp_start_in_reg), + .i_delete_resp_last(w_delete_resp_last_in_reg), + .o_delete_resp_ready(w_delete_resp_ready_in_reg), + + .o_get_req_valid(w_get_req_valid_axis), + .ov_get_req_head(wv_get_req_head_axis), + .i_get_req_ready('d1), + + .i_get_resp_valid(w_get_resp_valid_in_reg), + .iv_get_resp_head(wv_get_resp_head_in_reg), + .iv_get_resp_data(wv_get_resp_data_in_reg), + .i_get_resp_start(w_get_resp_start_in_reg), + .i_get_resp_last(w_get_resp_last_in_reg), + .o_get_resp_ready(w_get_resp_ready_in_reg), + + .o_packet_out_valid(w_retrans_valid_axis), + .ov_packet_out_head(wv_retrans_head_axis), + .ov_packet_out_data(wv_retrans_data_axis), + .o_packet_out_start(w_retrans_start_axis), + .o_packet_out_last(w_retrans_last_axis), + .i_packet_out_ready(w_retrans_ready_axis), + + .ov_upsn_rd_index(ov_upsn_rd_index), + .iv_upsn_rd_data(iv_upsn_rd_data), + .o_upsn_wr_en(o_upsn_wr_en), + .ov_upsn_wr_index(ov_upsn_wr_index), + .ov_upsn_wr_data(ov_upsn_wr_data) +); + +PacketBufferMgt +#( + .SLOT_WIDTH(`PKT_DATA_WIDTH), + .SLOT_NUM(`SEND_BUFFER_SLOT_NUM) +) +PacketBufferMgt_Inst( + .clk(clk), + .rst(rst), + + .ov_available_slot_num(wv_available_slot_num), + .i_insert_req_valid(w_insert_req_valid_in_reg), + .iv_insert_req_head(wv_insert_req_head_in_reg), + .iv_insert_req_data(wv_insert_req_data_in_reg), + .i_insert_req_start(w_insert_req_start_in_reg), + .i_insert_req_last(w_insert_req_last_in_reg), + .o_insert_req_ready(w_insert_req_ready_in_reg), + + .i_delete_req_valid(w_delete_req_valid_in_reg), + .iv_delete_req_head(wv_delete_req_head_in_reg), + .o_delete_req_ready(w_delete_req_ready_in_reg), + + .o_delete_resp_valid(w_delete_resp_valid_axis), + .ov_delete_resp_head(wv_delete_resp_head_axis), + .ov_delete_resp_data(wv_delete_resp_data_axis), + .o_delete_resp_start(w_delete_resp_start_axis), + .o_delete_resp_last(w_delete_resp_last_axis), + .i_delete_resp_ready(w_delete_resp_ready_axis), + + .i_find_req_valid_A('d0), + .iv_find_req_head_A('d0), + .o_find_resp_valid_A(), + .ov_find_resp_data_A(), + + .i_find_req_valid_B('d0), + .iv_find_req_head_B('d0), + .o_find_resp_valid_B(), + .ov_find_resp_data_B(), + + .i_get_req_valid(w_get_req_valid_in_reg), + .iv_get_req_head(wv_get_req_head_in_reg), + + .o_get_resp_valid(w_get_resp_valid_axis), + .ov_get_resp_head(wv_get_resp_head_axis), + .ov_get_resp_data(wv_get_resp_data_axis), + .o_get_resp_start(w_get_resp_start_axis), + .o_get_resp_last(w_get_resp_last_axis), + .i_get_resp_ready(w_get_resp_ready_axis) +); + +PacketArbiter PacketArbiter_Inst( + .clk(clk), + .rst(rst), + + .i_channel_0_valid(w_inject_valid_in_reg), + .iv_channel_0_head(wv_inject_head_in_reg), + .iv_channel_0_data(wv_inject_data_in_reg), + .i_channel_0_start(w_inject_start_in_reg), + .i_channel_0_last(w_inject_last_in_reg), + .o_channel_0_ready(w_inject_ready_in_reg), + + .i_channel_1_valid(w_retrans_valid_in_reg), + .iv_channel_1_head(wv_retrans_head_in_reg), + .iv_channel_1_data(wv_retrans_data_in_reg), + .i_channel_1_start(w_retrans_start_in_reg), + .i_channel_1_last(w_retrans_last_in_reg), + .o_channel_1_ready(w_retrans_ready_in_reg), + + .o_channel_out_valid(w_packet_out_valid_axis), + .ov_channel_out_head(wv_packet_out_head_axis), + .ov_channel_out_data(wv_packet_out_data_axis), + .o_channel_out_start(w_packet_out_start_axis), + .o_channel_out_last(w_packet_out_last_axis), + .i_channel_out_ready(w_packet_out_ready_axis) +); + +TimerControl TimerControl_Inst( + .clk(clk), + .rst(rst), + + .i_time_out_empty(w_time_out_empty), + .iv_time_out_dout(wv_time_out_dout), + .o_time_out_rd_en(w_time_out_rd_en), + + .o_timer_set_prog_full_A(w_timer_set_prog_full_A), + .i_timer_set_wr_en_A(w_timer_set_wr_en_A), + .iv_timer_set_din_A(wv_timer_set_din_A), + + .o_timer_set_prog_full_B(w_timer_set_prog_full_B), + .i_timer_set_wr_en_B(w_timer_set_wr_en_B), + .iv_timer_set_din_B(wv_timer_set_din_B) +); + +/*------------------------------------------- Submodules Instatiation : End -----------------------------------------*/ + +/*------------------------------------------- State Machine Definition : Begin --------------------------------------*/ +//Null +/*------------------------------------------- State Machine Definition : End ----------------------------------------*/ + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ +//Null +/*------------------------------------------- Variables Decode : End ------------------------------------------------*/ +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/TransportSubsystem/TimerControl.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/TransportSubsystem/TimerControl.v new file mode 100644 index 0000000000000000000000000000000000000000..07e87674f7de4557cd106c3e922f4c904348a54a --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/TransportSubsystem/TimerControl.v @@ -0,0 +1,110 @@ +/*------------------------------------------- Module Description : Begin ---------------------------------------------- +Name: TimerControl +Author: YangFan +Function: Provides timer for reliable data transfer. +--------------------------------------------- Module Decription : End -----------------------------------------------*/ + +/*------------------------------------------- Timescale Definition : Begin ------------------------------------------*/ +`timescale 1ns / 1ps +/*------------------------------------------- Timescale Definition : End --------------------------------------------*/ + +/*------------------------------------------- Included Files : Begin ------------------------------------------------*/ +`include "ib_constant_def_h.vh" +`include "common_function_def.vh" +`include "transport_subsystem_def.vh" +`include "global_def.vh" +/*------------------------------------------- Included Files : End --------------------------------------------------*/ + +/*------------------------------------------- Input/Output Definition : Begin ---------------------------------------*/ +module TimerControl ( + input wire clk, + input wire rst, + + //Timer event in + //Timer event format : {QPN} + input wire i_time_out_empty, + input wire [`TIMER_EVENT_WIDTH - 1 : 0] iv_time_out_dout, + output wire o_time_out_rd_en, + + //Timer set out + //Timer set format : {ACTION, QPN} + output wire o_timer_set_prog_full_A, + input wire i_timer_set_wr_en_A, + input wire [`TIMER_CMD_WIDTH - 1 : 0] iv_timer_set_din_A, + + output wire o_timer_set_prog_full_B, + input wire i_timer_set_wr_en_B, + input wire [`TIMER_CMD_WIDTH - 1 : 0] iv_timer_set_din_B + +); +/*------------------------------------------- Input/Output Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Variables Definition : Begin ------------------------------------*/ + +/*------------------------------------------- Local Variables Definition : End --------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : Begin ---------------------------------------*/ +SyncFIFO_Template #( + .FIFO_WIDTH(`TIMER_EVENT_WIDTH), + .FIFO_DEPTH(64) +) +TimerEventFIFO_Inst +( + .clk(clk), + .rst(rst), + + .wr_en('d0), + .din('d0), + .prog_full(), + .rd_en(o_time_out_rd_en), + .dout(iv_time_out_dout), + .empty(i_time_out_empty), + .data_count() +); + +SyncFIFO_Template #( + .FIFO_WIDTH(`TIMER_CMD_WIDTH), + .FIFO_DEPTH(64) +) +TimerSet_A_FIFO_Inst +( + .clk(clk), + .rst(rst), + + .wr_en(i_timer_set_wr_en_A), + .din(iv_timer_set_din_A), + .prog_full(o_timer_set_prog_full_A), + .rd_en('d1), + .dout(), + .empty(), + .data_count() +); + +SyncFIFO_Template #( + .FIFO_WIDTH(`TIMER_CMD_WIDTH), + .FIFO_DEPTH(64) +) +TimerSet_B_FIFO_Inst +( + .clk(clk), + .rst(rst), + + .wr_en(i_timer_set_wr_en_B), + .din(iv_timer_set_din_B), + .prog_full(o_timer_set_prog_full_B), + .rd_en('d1), + .dout(), + .empty(), + .data_count() +); + +/*------------------------------------------- Submodules Instatiation : End -----------------------------------------*/ + +/*------------------------------------------- State Machine Definition : Begin --------------------------------------*/ + +/*------------------------------------------- State Machine Definition : End ----------------------------------------*/ + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ + +/*------------------------------------------- Variables Decode : End ------------------------------------------------*/ +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/TransportSubsystem/TransportHashTable.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/TransportSubsystem/TransportHashTable.v new file mode 100644 index 0000000000000000000000000000000000000000..9884fb84a30326868677905f3d3c78e08d6ae063 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/TransportSubsystem/TransportHashTable.v @@ -0,0 +1,267 @@ +/*------------------------------------------- Module Description : Begin ---------------------------------------------- +Name: TransportHashTable +Author: YangFan +Function: Record packet metadata. + Crucial to the retransmission protocol. + 1.When enqueue a packet in normal TX procedure, record the packet's start address; + 2.When require a packet in resend TX procedure, provide the packet's start address. + Key problem is how to allocate and locate a metadata slot based on {QPN + PSN}. + I don't know the best solution, sevveral implementations should be compared. + TransportHashTable should provide a standard interface. +--------------------------------------------- Module Decription : End -----------------------------------------------*/ + +/*------------------------------------------- Timescale Definition : Begin ------------------------------------------*/ +`timescale 1ns / 1ps +/*------------------------------------------- Timescale Definition : End --------------------------------------------*/ + +/*------------------------------------------- Included Files : Begin ------------------------------------------------*/ +`include "ib_constant_def_h.vh" +`include "common_function_def.vh" +`include "transport_subsystem_def.vh" +`include "global_def.vh" +/*------------------------------------------- Included Files : End --------------------------------------------------*/ + +/*------------------------------------------- Input/Output Definition : Begin ---------------------------------------*/ +module TransportHashTable #( + parameter SLOT_NUM = 65536, + parameter SLOT_NUM_LOG = log2b(SLOT_NUM - 1), + parameter SLOT_WIDTH = 9 +)( + input wire clk, + input wire rst, + +//Allocate a HashTable slot and enqueue a packet metadata + input wire i_alloc_valid, + input wire [`QP_NUM_LOG + `PSN_WIDTH - 1 : 0] iv_alloc_index, + input wire [8 + SLOT_WIDTH - 1 : 0] iv_alloc_data, + output reg o_alloc_ready, + +//Provide a HashTable slot content + input wire i_find_req_valid_A, + input wire [`QP_NUM_LOG + `PSN_WIDTH - 1 : 0] iv_find_req_index_A, + output reg o_find_resp_valid_A, + output reg [8 + SLOT_WIDTH : 0] ov_find_resp_data_A, + +//Provide a HashTable slot content + input wire i_find_req_valid_B, + input wire [`QP_NUM_LOG + `PSN_WIDTH - 1 : 0] iv_find_req_index_B, + output reg o_find_resp_valid_B, + output reg [8 + SLOT_WIDTH : 0] ov_find_resp_data_B, + +//Recycle a HashTable slot + input wire i_recycle_req_valid, + input wire [`QP_NUM_LOG + `PSN_WIDTH - 1 : 0] iv_recycle_req_index, + output reg o_recycle_req_ready, + output reg o_recyle_resp_valid, + output reg [SLOT_WIDTH - 1 : 0] ov_recycle_resp_data + +); +/*------------------------------------------- Input/Output Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Variables Definition : Begin ------------------------------------*/ +reg wea; +reg [SLOT_NUM_LOG - 1 : 0] addra; +reg [8 + SLOT_WIDTH : 0] dina; +wire [8 + SLOT_WIDTH : 0] douta; + +reg web; +reg [SLOT_NUM_LOG - 1 : 0] addrb; +reg [8 + SLOT_WIDTH : 0] dinb; +wire [8 + SLOT_WIDTH : 0] doutb; + +reg q_find_req_mandatory_flag_A; +reg q_find_req_mandatory_flag_B; +reg q_recycle_req_mandatory_flag;; +/*------------------------------------------- Local Variables Definition : End --------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : Begin ---------------------------------------*/ +SRAM_TDP_Template #( + .RAM_WIDTH(1 + 8 + `RECV_BUFFER_SLOT_NUM_LOG), + .RAM_DEPTH(65536) +) HashTable_inst( + .clk ( clk ), + .rst ( rst ), + + .wea ( wea ), + .addra ( addra ), + .dina ( dina ), + .douta ( douta ), + + .web ( web ), + .addrb ( addrb ), + .dinb ( dinb ), + .doutb ( doutb ) +); + +/*------------------------------------------- Submodules Instatiation : End -----------------------------------------*/ + +/*------------------------------------------- State Machine Definition : Begin --------------------------------------*/ +//NULL +/*------------------------------------------- State Machine Definition : End ----------------------------------------*/ + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ + +//-- wea -- +//-- addra -- +//-- dina -- +always @(*) begin + if(rst) begin + wea = 'd0; + addra = 'd0; + dina = 'd0; + end + else if(i_alloc_valid) begin + wea = 'd1; + addra = {iv_alloc_index[`PSN_WIDTH + `QP_NUM_LOG - 1 : `PSN_WIDTH], iv_alloc_index[9 : 0]}; //64 QP, each QP occupies 1K slot + dina = {1'b1, iv_alloc_data}; + end + else if(i_find_req_valid_A) begin + wea = 'd0; + addra = {iv_find_req_index_A[`PSN_WIDTH + `QP_NUM_LOG - 1 : `PSN_WIDTH], iv_find_req_index_A[9 : 0]}; //64 QP, each QP occupies 1K slot + dina = 'd0; + end + else begin + wea = 'd0; + addra = 'd0; + dina = 'd0; + end +end + +//-- web -- +//-- addrb -- +//-- dinb -- +always @(*) begin + if(rst) begin + web = 'd0; + addrb = 'd0; + dinb = 'd0; + end + else if(i_recycle_req_valid) begin + web = 'd1; + addrb = {iv_recycle_req_index[`PSN_WIDTH + `QP_NUM_LOG - 1 : `PSN_WIDTH], iv_recycle_req_index[9 : 0]}; //64 QP, each QP occupies 1K slot + dinb = 'd0; + end + else if(i_find_req_valid_B) begin + web = 'd0; + addrb = {iv_find_req_index_B[`PSN_WIDTH + `QP_NUM_LOG - 1 : `PSN_WIDTH], iv_find_req_index_B[9 : 0]}; //64 QP, each QP occupies 1K slot + dinb = 'd0; + end + else begin + web = 'd0; + addrb = 'd0; + dinb = 'd0; + end +end + +//-- o_alloc_ready -- +always @(*) begin + if(rst) begin + o_alloc_ready = 'd0; + end + else begin + o_alloc_ready = 'd1; + end +end + +//-- o_find_resp_valid_A -- +//-- ov_find_resp_data_A -- +always @(*) begin + if(rst) begin + o_find_resp_valid_A = 'd0; + ov_find_resp_data_A = 'd0; + end + else if(q_find_req_mandatory_flag_A) begin + o_find_resp_valid_A = 'd1; + ov_find_resp_data_A = douta; + end + else begin + o_find_resp_valid_A = 'd0; + ov_find_resp_data_A = 'd0; + end +end + +//-- o_find_resp_valid_B -- +//-- ov_find_resp_data_B -- +always @(*) begin + if(rst) begin + o_find_resp_valid_B = 'd0; + ov_find_resp_data_B = 'd0; + end + else if(q_find_req_mandatory_flag_B) begin + o_find_resp_valid_B = 'd1; + ov_find_resp_data_B = doutb; + end + else begin + o_find_resp_valid_B = 'd0; + ov_find_resp_data_B = 'd0; + end +end + +//-- o_recycle_req_ready -- +always @(*) begin + if(rst) begin + o_recycle_req_ready = 'd0; + end + else begin + o_recycle_req_ready = 'd1; + end +end + +//-- o_recyle_resp_valid -- +//-- ov_recycle_resp_data -- +always @(*) begin + if(rst) begin + o_recyle_resp_valid = 'd0; + ov_recycle_resp_data = 'd0; + end + else if(q_find_req_mandatory_flag_B) begin + o_recyle_resp_valid = 'd1; + ov_recycle_resp_data = doutb; + end + else begin + o_recyle_resp_valid = 'd0; + ov_recycle_resp_data = 'd0; + end +end + +//-- q_recycle_req_mandatory_flag -- +always @(posedge clk or posedge rst) begin + if(rst) begin + q_recycle_req_mandatory_flag <= 'd0; + end + else if(i_find_req_valid_B) begin + q_recycle_req_mandatory_flag <= 'd1; + end + else begin + q_recycle_req_mandatory_flag <= 'd0; + end +end + +//-- q_find_req_mandatory_flag_A -- +always @(posedge clk or posedge rst) begin + if(rst) begin + q_find_req_mandatory_flag_A <= 'd0; + end + else if(i_find_req_valid_A) begin + q_find_req_mandatory_flag_A <= 'd1; + end + else begin + q_find_req_mandatory_flag_A <= 'd0; + end +end + +//-- q_find_req_mandatory_flag_B -- +always @(posedge clk or posedge rst) begin + if(rst) begin + q_find_req_mandatory_flag_B <= 'd0; + end + else if(i_find_req_valid_B) begin + q_find_req_mandatory_flag_B <= 'd1; + end + else begin + q_find_req_mandatory_flag_B <= 'd0; + end +end + +/*------------------------------------------- Variables Decode : End ------------------------------------------------*/ +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/TransportSubsystem/TransportSubsystem.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/TransportSubsystem/TransportSubsystem.v new file mode 100644 index 0000000000000000000000000000000000000000..d89ec064adcba35eae87a0aebf8f91fdf9c91d62 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/TransportSubsystem/TransportSubsystem.v @@ -0,0 +1,330 @@ +/*------------------------------------------- Module Description : Begin ---------------------------------------------- +Name: SendControl +Author: YangFan +Function: Wrapper for InOrderInject, SelectiveRepeat, and PacketBufferMgt. +--------------------------------------------- Module Decription : End -----------------------------------------------*/ + +/*------------------------------------------- Timescale Definition : Begin ------------------------------------------*/ +`timescale 1ns / 1ps +/*------------------------------------------- Timescale Definition : End --------------------------------------------*/ + +/*------------------------------------------- Included Files : Begin ------------------------------------------------*/ +`include "protocol_engine_def.vh" +/*------------------------------------------- Included Files : End --------------------------------------------------*/ + +/*------------------------------------------- Input/Output Definition : Begin ---------------------------------------*/ +module TransportSubsystem( + input wire user_clk, + input wire user_rst, + + input wire mac_tx_clk, + input wire mac_tx_rst, + + input wire mac_rx_clk, + input wire mac_rx_rst, + + input wire TX_egress_pkt_valid, + input wire [`PKT_META_BUS_WIDTH - 1 : 0] TX_egress_pkt_head, + output wire TX_egress_pkt_ready, + + input wire TX_insert_req_valid, + input wire TX_insert_req_start, + input wire TX_insert_req_last, + input wire [`MAX_DB_SLOT_NUM_LOG - 1 : 0] TX_insert_req_head, + input wire [`PACKET_BUFFER_SLOT_WIDTH - 1 : 0] TX_insert_req_data, + output wire TX_insert_req_ready, + + output wire TX_insert_resp_valid, + output wire [`MAX_DB_SLOT_NUM_LOG - 1 : 0] TX_insert_resp_data, + + output wire RX_ingress_pkt_valid, + output wire [`PKT_META_BUS_WIDTH - 1 : 0] RX_ingress_pkt_head, + input wire RX_ingress_pkt_ready, + + input wire RX_delete_req_valid, + input wire [`MAX_DB_SLOT_NUM_LOG * 2 - 1 : 0] RX_delete_req_head, + output wire RX_delete_req_ready, + + output wire RX_delete_resp_valid, + output wire RX_delete_resp_start, + output wire RX_delete_resp_last, + output wire [`PACKET_BUFFER_SLOT_WIDTH - 1 : 0] RX_delete_resp_data, + input wire RX_delete_resp_ready, + + output wire mac_tx_valid, + input wire mac_tx_ready, + output wire mac_tx_start, + output wire mac_tx_last, + output wire [`MAC_KEEP_WIDTH - 1 : 0] mac_tx_keep, + output wire mac_tx_user, + output wire [`MAC_DATA_WIDTH - 1 : 0] mac_tx_data, + + input wire mac_rx_valid, + output wire mac_rx_ready, + input wire mac_rx_start, + input wire mac_rx_last, + input wire [`MAC_KEEP_WIDTH - 1 : 0] mac_rx_keep, + input wire mac_rx_user, + input wire [`MAC_DATA_WIDTH - 1 : 0] mac_rx_data +); +/*------------------------------------------- Input/Output Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Variables Definition : Begin ------------------------------------*/ +wire TX_delete_req_valid; +wire [`MAX_DB_SLOT_NUM_LOG * 2 - 1 : 0] TX_delete_req_head; +wire TX_delete_req_ready; + +wire TX_delete_resp_valid; +wire TX_delete_resp_start; +wire TX_delete_resp_last; +wire [`PACKET_BUFFER_SLOT_WIDTH - 1 : 0] TX_delete_resp_data; +wire TX_delete_resp_ready; + +wire RX_insert_req_valid; +wire RX_insert_req_start; +wire RX_insert_req_last; +wire [`MAX_DB_SLOT_NUM_LOG - 1 : 0] RX_insert_req_head; +wire [`PACKET_BUFFER_SLOT_WIDTH - 1 : 0] RX_insert_req_data; +wire RX_insert_req_ready; + +wire RX_insert_resp_valid; +wire [`MAX_DB_SLOT_NUM_LOG - 1 : 0] RX_insert_resp_data; + +wire user_mac_tx_valid; +wire user_mac_tx_ready; +wire user_mac_tx_start; +wire user_mac_tx_last; +wire [`MAC_KEEP_WIDTH - 1 : 0] user_mac_tx_keep; +wire user_mac_tx_user; +wire [`MAC_DATA_WIDTH - 1 : 0] user_mac_tx_data; + +wire user_mac_rx_valid; +wire user_mac_rx_ready; +wire user_mac_rx_start; +wire user_mac_rx_last; +wire [`MAC_KEEP_WIDTH - 1 : 0] user_mac_rx_keep; +wire user_mac_rx_user; +wire [`MAC_DATA_WIDTH - 1 : 0] user_mac_rx_data; +/*------------------------------------------- Local Variables Definition : End --------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : Begin ---------------------------------------*/ +MACEncap MACEncap_Inst( + .clk ( user_clk ), + .rst ( user_rst ), + + .egress_pkt_valid ( TX_egress_pkt_valid ), + .egress_pkt_head ( TX_egress_pkt_head ), + .egress_pkt_ready ( TX_egress_pkt_ready ), + + .delete_req_valid ( TX_delete_req_valid ), + .delete_req_head ( TX_delete_req_head ), + .delete_req_ready ( TX_delete_req_ready ), + + .delete_resp_valid ( TX_delete_resp_valid ), + .delete_resp_start ( TX_delete_resp_start ), + .delete_resp_last ( TX_delete_resp_last ), + .delete_resp_data ( TX_delete_resp_data ), + .delete_resp_ready ( TX_delete_resp_ready ), + + .mac_tx_valid ( user_mac_tx_valid ), + .mac_tx_ready ( user_mac_tx_ready ), + .mac_tx_start ( user_mac_tx_start ), + .mac_tx_last ( user_mac_tx_last ), + .mac_tx_keep ( user_mac_tx_keep ), + .mac_tx_user ( user_mac_tx_user ), + .mac_tx_data ( user_mac_tx_data ) +); + +MACDecap MACDecap_Inst( + .clk ( user_clk ), + .rst ( user_rst ), + + .insert_req_valid ( RX_insert_req_valid ), + .insert_req_start ( RX_insert_req_start ), + .insert_req_last ( RX_insert_req_last ), + .insert_req_head ( RX_insert_req_head ), + .insert_req_data ( RX_insert_req_data ), + .insert_req_ready ( RX_insert_req_ready ), + + .insert_resp_valid ( RX_insert_resp_valid ), + .insert_resp_data ( RX_insert_resp_data ), + + .mac_rx_valid ( user_mac_rx_valid ), + .mac_rx_ready ( user_mac_rx_ready ), + .mac_rx_start ( user_mac_rx_start ), + .mac_rx_last ( user_mac_rx_last ), + .mac_rx_keep ( user_mac_rx_keep ), + .mac_rx_user ( user_mac_rx_user ), + .mac_rx_data ( user_mac_rx_data ), + + .ingress_pkt_valid ( RX_ingress_pkt_valid ), + .ingress_pkt_head ( RX_ingress_pkt_head ), + .ingress_pkt_ready ( RX_ingress_pkt_ready ) +); + +DynamicBuffer +#( + .SLOT_WIDTH ( `PACKET_BUFFER_SLOT_WIDTH ), + .SLOT_NUM ( `PACKET_BUFFER_SLOT_NUM ) +) +TX_PacketBuffer_Inst( + .clk ( user_clk ), + .rst ( user_rst ), + + .ov_available_slot_num ( ), + + .i_insert_req_valid ( TX_insert_req_valid ), + .i_insert_req_start ( TX_insert_req_start ), + .i_insert_req_last ( TX_insert_req_last ), + .iv_insert_req_head ( TX_insert_req_head ), + .iv_insert_req_data ( TX_insert_req_data ), + .o_insert_req_ready ( TX_insert_req_ready ), + + .o_insert_resp_valid ( TX_insert_resp_valid ), + .ov_insert_resp_data ( TX_insert_resp_data ), + + .i_get_req_valid ( 'd0 ), + .iv_get_req_head ( 'd0 ), + .o_get_req_ready ( ), + .o_get_resp_valid ( ), + .o_get_resp_start ( ), + .o_get_resp_last ( ), + .ov_get_resp_data ( ), + .i_get_resp_ready ( 'd0 ), + + .i_delete_req_valid ( TX_delete_req_valid ), + .iv_delete_req_head ( TX_delete_req_head ), + .o_delete_req_ready ( TX_delete_req_ready ), + + .o_delete_resp_valid ( TX_delete_resp_valid ), + .o_delete_resp_start ( TX_delete_resp_start ), + .o_delete_resp_last ( TX_delete_resp_last ), + .ov_delete_resp_data ( TX_delete_resp_data ), + .i_delete_resp_ready ( TX_delete_resp_ready ) +); + +DynamicBuffer +#( + .SLOT_WIDTH ( `PACKET_BUFFER_SLOT_WIDTH ), + .SLOT_NUM ( `PACKET_BUFFER_SLOT_NUM ) +) +RX_PacketBuffer_Inst( + .clk ( user_clk ), + .rst ( user_rst ), + + .ov_available_slot_num ( ), + + .i_insert_req_valid ( RX_insert_req_valid ), + .i_insert_req_start ( RX_insert_req_start ), + .i_insert_req_last ( RX_insert_req_last ), + .iv_insert_req_head ( RX_insert_req_head ), + .iv_insert_req_data ( RX_insert_req_data ), + .o_insert_req_ready ( RX_insert_req_ready ), + + .o_insert_resp_valid ( RX_insert_resp_valid ), + .ov_insert_resp_data ( RX_insert_resp_data ), + + .i_get_req_valid ( 'd0 ), + .iv_get_req_head ( 'd0 ), + .o_get_req_ready ( ), + .o_get_resp_valid ( ), + .o_get_resp_start ( ), + .o_get_resp_last ( ), + .ov_get_resp_data ( ), + .i_get_resp_ready ( 'd0 ), + + .i_delete_req_valid ( RX_delete_req_valid ), + .iv_delete_req_head ( RX_delete_req_head ), + .o_delete_req_ready ( RX_delete_req_ready ), + + .o_delete_resp_valid ( RX_delete_resp_valid ), + .o_delete_resp_start ( RX_delete_resp_start ), + .o_delete_resp_last ( RX_delete_resp_last ), + .ov_delete_resp_data ( RX_delete_resp_data ), + .i_delete_resp_ready ( RX_delete_resp_ready ) +); + +wire [577 - 1 : 0] mac_tx_fifo_dout; +wire mac_tx_fifo_empty; +wire mac_tx_fifo_prog_full; + +assign mac_tx_valid = !mac_tx_fifo_empty; +assign mac_tx_user = 'd0; +assign mac_tx_last = mac_tx_fifo_dout[512 + 64 + 1 - 1 : 512 + 64]; +assign mac_tx_keep = mac_tx_fifo_dout[512 + 64 - 1 : 512]; +assign mac_tx_data = mac_tx_fifo_dout[512 - 1 : 0]; +assign user_mac_tx_ready = !mac_tx_fifo_prog_full; + +//TODO, bug exists + +AsyncFIFO_577w_128d MAC_TX_FIFO ( + .wr_clk ( user_clk ), // input wire wr_clk + .wr_rst ( user_rst ), // input wire wr_rst + .rd_clk ( mac_tx_clk ), // input wire rd_clk + .rd_rst ( mac_tx_rst ), // input wire rd_rst + .din ( {user_mac_tx_last, user_mac_tx_keep, user_mac_tx_data} ), // input wire [576 : 0] din + .wr_en ( user_mac_tx_valid & user_mac_tx_ready ), // input wire wr_en + .rd_en ( mac_tx_ready ), // input wire rd_en + .dout ( mac_tx_fifo_dout ), // output wire [576 : 0] dout + .full ( ), // output wire full + .empty ( mac_tx_fifo_empty ), // output wire empty + .prog_full ( mac_tx_fifo_prog_full ) // output wire prog_full +); + +wire [577 - 1 : 0] mac_rx_fifo_dout; +wire mac_rx_fifo_empty; +wire mac_rx_fifo_prog_full; + +assign user_mac_rx_valid = !mac_rx_fifo_empty; +assign user_mac_rx_user = 'd0; +assign user_mac_rx_last = mac_rx_fifo_dout[512 + 64 + 1 - 1 : 512 + 64]; +assign user_mac_rx_keep = mac_rx_fifo_dout[512 + 64 - 1 : 512]; +assign user_mac_rx_data = mac_rx_fifo_dout[512 - 1 : 0]; +assign mac_rx_ready = !mac_rx_fifo_prog_full; + +AsyncFIFO_577w_128d MAC_RX_FIFO ( + .wr_clk ( user_clk ), // input wire wr_clk + .wr_rst ( user_rst ), // input wire wr_rst + .rd_clk ( mac_rx_clk ), // input wire rd_clk + .rd_rst ( mac_rx_rst ), // input wire rd_rst + .din ( {mac_rx_last, mac_rx_keep, mac_rx_data} ), // input wire [576 : 0] din + .wr_en ( mac_rx_valid && mac_rx_ready ), // input wire wr_en + .rd_en ( !mac_rx_fifo_empty && user_mac_rx_ready ), // input wire rd_en + .dout ( mac_rx_fifo_dout ), // output wire [576 : 0] dout + .full ( ), // output wire full + .empty ( mac_rx_fifo_empty ), // output wire empty + .prog_full ( mac_rx_fifo_prog_full ) // output wire prog_full +); +/*------------------------------------------- Submodules Instatiation : End -----------------------------------------*/ + +/*------------------------------------------- State Machine Definition : Begin --------------------------------------*/ +//Null +/*------------------------------------------- State Machine Definition : End ----------------------------------------*/ + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ +/*------------------------------------------- Variables Decode : End ------------------------------------------------*/ +// `ifdef ILA_ON +// ila_mac ila_mac_tx_inst( +// .clk(user_clk), + +// .probe0(user_mac_tx_valid), +// .probe1(user_mac_tx_ready), +// .probe2(user_mac_tx_start), +// .probe3(user_mac_tx_last), +// .probe4(user_mac_tx_keep), +// .probe5(user_mac_tx_data) +// ); + +// ila_mac ila_mac_rx_inst( +// .clk(user_clk), + +// .probe0(user_mac_rx_valid), +// .probe1(user_mac_rx_ready), +// .probe2(user_mac_rx_start), +// .probe3(user_mac_rx_last), +// .probe4(user_mac_rx_keep), +// .probe5(user_mac_rx_data) +// ); +// `endif + +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/TransportSubsystem/TransportSubsystem_SR.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/TransportSubsystem/TransportSubsystem_SR.v new file mode 100644 index 0000000000000000000000000000000000000000..0982f0e5e16a69b37dd64992e9ba863fbda582b9 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/TransportSubsystem/TransportSubsystem_SR.v @@ -0,0 +1,250 @@ +/*------------------------------------------- Module Description : Begin ---------------------------------------------- +Name: SendControl +Author: YangFan +Function: Wrapper for InOrderInject, SelectiveRepeat, and PacketBufferMgt. +--------------------------------------------- Module Decription : End -----------------------------------------------*/ + +/*------------------------------------------- Timescale Definition : Begin ------------------------------------------*/ +`timescale 1ns / 1ps +/*------------------------------------------- Timescale Definition : End --------------------------------------------*/ + +/*------------------------------------------- Included Files : Begin ------------------------------------------------*/ +`include "ib_constant_def_h.vh" +`include "common_function_def.vh" +`include "transport_subsystem_def.vh" +`include "global_def.vh" +/*------------------------------------------- Included Files : End --------------------------------------------------*/ + +/*------------------------------------------- Input/Output Definition : Begin ---------------------------------------*/ +module TransportSubsystem( + input wire clk, + input wire rst, + +//Upper Layer Protocol Interface + input wire i_inject_from_ulp_valid, + input wire [`PKT_HEAD_WIDTH - 1 : 0] iv_inject_from_ulp_head, + input wire [`PKT_DATA_WIDTH - 1 : 0] iv_inject_from_ulp_data, + input wire i_inject_from_ulp_start, + input wire i_inject_from_ulp_last, + output reg o_inject_from_ulp_ready, + + output wire o_commit_to_ulp_valid, + output wire [`PKT_HEAD_WIDTH - 1 : 0] ov_commit_to_ulp_head, + output wire [`PKT_DATA_WIDTH - 1 : 0] ov_commit_to_ulp_data, + output wire o_commit_to_ulp_start, + output wire o_commit_to_ulp_last, + input wire i_commit_to_ulp_ready, + +//Lower Layer Protocol Interface + output reg o_send_to_llp_valid, + output reg [`PKT_HEAD_WIDTH - 1 : 0] ov_send_to_llp_head, + output reg [`PKT_DATA_WIDTH - 1 : 0] ov_send_to_llp_data, + output reg o_send_to_llp_start, + output reg o_send_to_llp_last, + input wire i_send_to_llp_ready, + + input wire i_recv_from_llp_valid, + input wire [`PKT_HEAD_WIDTH - 1 : 0] iv_recv_from_llp_head, + input wire [`PKT_DATA_WIDTH - 1 : 0] iv_recv_from_llp_data, + input wire i_recv_from_llp_start, + input wire i_recv_from_llp_last, + output wire o_recv_from_llp_ready, + +//PSN Control + output reg o_npsn_wr_en, + output reg [`QP_NUM_LOG - 1 : 0] ov_npsn_wr_index, + output reg [`PSN_WIDTH - 1 : 0] ov_npsn_wr_data, + output wire [`QP_NUM_LOG - 1 : 0] ov_npsn_rd_index, + input wire [`PSN_WIDTH - 1 : 0] iv_npsn_rd_data, + + output reg [`QP_NUM_LOG - 1 : 0] ov_upsn_rd_index, + input wire [`PSN_WIDTH - 1 : 0] iv_upsn_rd_data, + output reg o_upsn_wr_en, + output reg [`QP_NUM_LOG - 1 : 0] ov_upsn_wr_index, + output reg [`PSN_WIDTH - 1 : 0] ov_upsn_wr_data, + + output wire [`QP_NUM_LOG - 1 : 0] ov_ooa_epsn_rd_index, + input wire [`PSN_WIDTH - 1 : 0] iv_ooa_epsn_rd_data, + output wire o_ooa_epsn_wr_en, + output wire [`QP_NUM_LOG - 1 : 0] ov_ooa_epsn_wr_index, + output wire [`PSN_WIDTH - 1 : 0] ov_ooa_epsn_wr_data, + + output reg [`QP_NUM_LOG - 1 : 0] ov_ioc_epsn_rd_index, + input wire [`PSN_WIDTH - 1 : 0] iv_ioc_epsn_rd_data, + output reg o_ioc_epsn_wr_en, + output reg [`QP_NUM_LOG - 1 : 0] ov_ioc_epsn_wr_index, + output reg [`PSN_WIDTH - 1 : 0] ov_ioc_epsn_wr_data +); +/*------------------------------------------- Input/Output Definition : End -----------------------------------------*/ + +/*------------------------------------------- Local Variables Definition : Begin ------------------------------------*/ +wire w_ack_valid; +wire [`PKT_HEAD_WIDTH - 1 : 0] wv_ack_head; +wire [`PKT_DATA_WIDTH - 1 : 0] wv_ack_data; +wire w_ack_start; +wire w_ack_last; +wire w_ack_ready; + +wire w_req_valid; +wire [`PKT_HEAD_WIDTH - 1 : 0] wv_req_head; +wire [`PKT_DATA_WIDTH - 1 : 0] wv_req_data; +wire w_req_start; +wire w_req_last; +wire w_req_ready; + +wire w_send_control_valid; +wire [`PKT_HEAD_WIDTH - 1 : 0] wv_send_control_head; +wire [`PKT_DATA_WIDTH - 1 : 0] wv_send_control_data; +wire w_send_control_start; +wire w_send_control_last; +wire w_send_control_ready; + +wire w_recv_control_valid; +wire [`PKT_HEAD_WIDTH - 1 : 0] wv_recv_control_head; +wire [`PKT_DATA_WIDTH - 1 : 0] wv_recv_control_data; +wire w_recv_control_start; +wire w_recv_control_last; +wire w_recv_control_ready; + +/*------------------------------------------- Local Variables Definition : End --------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : Begin ---------------------------------------*/ +SendControl SendControl_Inst( + .clk(clk), + .rst(rst), + + .i_packet_in_valid(i_inject_from_ulp_valid), + .iv_packet_in_head(iv_inject_from_ulp_head), + .iv_packet_in_data(iv_inject_from_ulp_data), + .i_packet_in_start(i_inject_from_ulp_start), + .i_packet_in_last(i_inject_from_ulp_last), + .o_packet_in_ready(o_inject_from_ulp_ready), + + .o_npsn_wr_en(o_npsn_wr_en), + .ov_npsn_wr_index(ov_npsn_wr_index), + .ov_npsn_wr_data(ov_npsn_wr_data), + .ov_npsn_rd_index(ov_npsn_rd_index), + .iv_npsn_rd_data(iv_npsn_rd_data), + + .o_packet_out_valid(w_send_control_valid), + .ov_packet_out_head(wv_send_control_head), + .ov_packet_out_data(wv_send_control_data), + .o_packet_out_start(w_send_control_start), + .o_packet_out_last(w_send_control_last), + .i_packet_out_ready(w_send_control_ready), + + .i_ack_in_valid(w_ack_valid), + .iv_ack_in_head(wv_ack_head), + .iv_ack_in_data(wv_ack_data), + .i_ack_in_start(w_ack_start), + .i_ack_in_last(w_ack_last), + .o_ack_in_ready(w_ack_ready), + + .ov_upsn_rd_index(ov_upsn_rd_index), + .iv_upsn_rd_data(iv_upsn_rd_data), + .o_upsn_wr_en(o_upsn_wr_en), + .ov_upsn_wr_index(ov_upsn_wr_index), + .ov_upsn_wr_data(ov_upsn_wr_data) +); + +RecvControl RecvControl_Inst( + .clk(clk), + .rst(rst), + + .i_packet_in_valid(w_req_valid), + .iv_packet_in_head(wv_req_head), + .iv_packet_in_data(wv_req_data), + .i_packet_in_start(w_req_start), + .i_packet_in_last(w_req_last), + .o_packet_in_ready(w_req_ready), + + .o_ooa_epsn_wr_en(o_ooa_epsn_wr_en), + .ov_ooa_epsn_wr_index(ov_ooa_epsn_wr_index), + .ov_ooa_epsn_wr_data(ov_ooa_epsn_wr_data), + .ov_ooa_epsn_rd_index(ov_ooa_epsn_rd_index), + .iv_ooa_epsn_rd_data(iv_ooa_epsn_rd_data), + + .ov_ioc_epsn_rd_index(ov_ioc_epsn_rd_index), + .iv_ioc_epsn_rd_data(iv_ioc_epsn_rd_data), + .o_ioc_epsn_wr_en(o_ioc_epsn_wr_en), + .ov_ioc_epsn_wr_index(ov_ioc_epsn_wr_index), + .ov_ioc_epsn_wr_data(ov_ioc_epsn_wr_data), + + .o_commit_valid(o_commit_to_ulp_valid), + .ov_commit_head(ov_commit_to_ulp_head), + .ov_commit_data(ov_commit_to_ulp_data), + .o_commit_start(o_commit_to_ulp_start), + .o_commit_last(o_commit_to_ulp_last), + .i_commit_ready(i_commit_to_ulp_ready), + + .o_packet_out_valid(w_recv_control_valid), + .ov_packet_out_head(wv_recv_control_head), + .ov_packet_out_data(wv_recv_control_data), + .o_packet_out_start(w_recv_control_start), + .o_packet_out_last(w_recv_control_last), + .i_packet_out_ready(w_recv_control_ready) +); + +PacketArbiter PacketArbiter_Inst( + .clk(clk), + .rst(rst), + + .i_channel_0_valid(w_send_control_valid), + .iv_channel_0_head(wv_send_control_head), + .iv_channel_0_data(wv_send_control_data), + .i_channel_0_start(w_send_control_start), + .i_channel_0_last(w_send_control_last), + .o_channel_0_ready(w_send_control_ready), + + .i_channel_1_valid(w_recv_control_valid), + .iv_channel_1_head(wv_recv_control_head), + .iv_channel_1_data(wv_recv_control_data), + .i_channel_1_start(w_recv_control_start), + .i_channel_1_last(w_recv_control_last), + .o_channel_1_ready(w_recv_control_ready), + + .o_channel_out_valid(o_send_to_llp_valid), + .ov_channel_out_head(ov_send_to_llp_head), + .ov_channel_out_data(ov_send_to_llp_data), + .o_channel_out_start(o_send_to_llp_start), + .o_channel_out_last(o_send_to_llp_last), + .i_channel_out_ready(i_send_to_llp_ready) +); + +PacketDistributer PacketDistributer_Inst( + .clk(clk), + .rst(rst), + + .i_recv_valid(i_recv_from_llp_valid), + .iv_recv_head(iv_recv_from_llp_head), + .iv_recv_data(iv_recv_from_llp_data), + .i_recv_start(i_recv_from_llp_start), + .i_recv_last(i_recv_from_llp_last), + .o_recv_ready(o_recv_from_llp_ready), + + .o_channel_0_out_valid(w_req_valid), + .ov_channel_0_out_head(wv_req_head), + .ov_channel_0_out_data(wv_req_data), + .o_channel_0_out_start(w_req_start), + .o_channel_0_out_last(w_req_last), + .i_channel_0_out_ready(w_req_ready), + + .o_channel_1_out_valid(w_ack_valid), + .ov_channel_1_out_head(wv_ack_head), + .ov_channel_1_out_data(wv_ack_data), + .o_channel_1_out_start(w_ack_start), + .o_channel_1_out_last(w_ack_last), + .i_channel_1_out_ready(w_ack_ready) +); + +/*------------------------------------------- Submodules Instatiation : End -----------------------------------------*/ + +/*------------------------------------------- State Machine Definition : Begin --------------------------------------*/ +//Null +/*------------------------------------------- State Machine Definition : End ----------------------------------------*/ + +/*------------------------------------------- Variables Decode : Begin ----------------------------------------------*/ +//Null +/*------------------------------------------- Variables Decode : End ------------------------------------------------*/ + +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/TransportSubsystem/TransportSubsystem_vrf.v b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/TransportSubsystem/TransportSubsystem_vrf.v new file mode 100644 index 0000000000000000000000000000000000000000..081fb5513fe58c257dcfe8df43d350f174da8274 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/hardware/hdl/rtl/TransportSubsystem/TransportSubsystem_vrf.v @@ -0,0 +1,248 @@ +/*------------------------------------------- Module Description : Begin ---------------------------------------------- +Name: TransportSubsystem_vrf +Author: YangFan +Function: Wrapper for TransportSubsystem, for verification. +--------------------------------------------- Module Decription : End -----------------------------------------------*/ + +/*------------------------------------------- Timescale Definition : Begin ------------------------------------------*/ +`timescale 1ns / 1ps +/*------------------------------------------- Timescale Definition : End --------------------------------------------*/ + +/*------------------------------------------- Included Files : Begin ------------------------------------------------*/ +`include "ib_constant_def_h.vh" +`include "common_function_def.vh" +`include "transport_subsystem_def.vh" +`include "global_def.vh" +/*------------------------------------------- Included Files : End --------------------------------------------------*/ + +module TransportSubsystem_vrf( + input wire clk, + input wire rst, + +//Upper Layer Protocol Interface + input wire i_inject_from_ulp_valid, + input wire [`PKT_HEAD_WIDTH - 1 : 0] iv_inject_from_ulp_head, + input wire [`PKT_DATA_WIDTH - 1 : 0] iv_inject_from_ulp_data, + input wire i_inject_from_ulp_start, + input wire i_inject_from_ulp_last, + output reg o_inject_from_ulp_ready, + + output wire o_commit_to_ulp_valid, + output wire [`PKT_HEAD_WIDTH - 1 : 0] ov_commit_to_ulp_head, + output wire [`PKT_DATA_WIDTH - 1 : 0] ov_commit_to_ulp_data, + output wire o_commit_to_ulp_start, + output wire o_commit_to_ulp_last, + input wire i_commit_to_ulp_ready, + +//Lower Layer Protocol Interface + output reg o_send_to_llp_valid, + output reg [`PKT_HEAD_WIDTH - 1 : 0] ov_send_to_llp_head, + output reg [`PKT_DATA_WIDTH - 1 : 0] ov_send_to_llp_data, + output reg o_send_to_llp_start, + output reg o_send_to_llp_last, + input wire i_send_to_llp_ready, + + input wire i_recv_from_llp_valid, + input wire [`PKT_HEAD_WIDTH - 1 : 0] iv_recv_from_llp_head, + input wire [`PKT_DATA_WIDTH - 1 : 0] iv_recv_from_llp_data, + input wire i_recv_from_llp_start, + input wire i_recv_from_llp_last, + output wire o_recv_from_llp_ready +); + +/*------------------------------------------- Local Variables Definition : Begin ------------------------------------*/ +wire w_ingress_valid; +wire [`PKT_HEAD_WIDTH - 1 : 0] wv_ingress_head; +wire [`PKT_DATA_WIDTH - 1 : 0] wv_ingress_data; +wire w_ingress_start; +wire w_ingress_last; +wire w_ingress_ready; + +wire w_egress_valid; +wire [`PKT_HEAD_WIDTH - 1 : 0] wv_egress_head; +wire [`PKT_DATA_WIDTH - 1 : 0] wv_egress_data; +wire w_egress_start; +wire w_egress_last; +wire w_egress_ready; + +wire [`QP_NUM_LOG - 1 : 0] wv_npsn_rd_index; +wire [`PSN_WIDTH - 1 : 0] wv_npsn_rd_data; +wire w_npsn_wr_en; +wire [`QP_NUM_LOG - 1 : 0] wv_npsn_wr_index; +wire [`PSN_WIDTH - 1 : 0] wv_npsn_wr_data; + +wire [`QP_NUM_LOG - 1 : 0] wv_upsn_rd_index; +wire [`PSN_WIDTH - 1 : 0] wv_upsn_rd_data; +wire w_upsn_wr_en; +wire [`QP_NUM_LOG - 1 : 0] wv_upsn_wr_index; +wire [`PSN_WIDTH - 1 : 0] wv_upsn_wr_data; + +wire [`QP_NUM_LOG - 1 : 0] wv_ooa_epsn_rd_index; +wire [`PSN_WIDTH - 1 : 0] wv_ooa_epsn_rd_data; +wire w_ooa_epsn_wr_en; +wire [`QP_NUM_LOG - 1 : 0] wv_ooa_epsn_wr_index; +wire [`PSN_WIDTH - 1 : 0] wv_ooa_epsn_wr_data; + +wire [`QP_NUM_LOG - 1 : 0] wv_ioc_epsn_rd_index; +wire [`PSN_WIDTH - 1 : 0] wv_ioc_epsn_rd_data; +wire w_ioc_epsn_wr_en; +wire [`QP_NUM_LOG - 1 : 0] wv_ioc_epsn_wr_index; +wire [`PSN_WIDTH - 1 : 0] wv_ioc_epsn_wr_data; + +/*------------------------------------------- Local Variables Definition : End --------------------------------------*/ + +/*------------------------------------------- Submodules Instatiation : Begin ---------------------------------------*/ +TransportSubsystem TransportSubsystem_Inst( + .clk(clk), + .rst(rst), + + .i_inject_from_ulp_valid(i_inject_from_ulp_valid), + .iv_inject_from_ulp_head(iv_inject_from_ulp_head), + .iv_inject_from_ulp_data(iv_inject_from_ulp_data), + .i_inject_from_ulp_start(i_inject_from_ulp_start), + .i_inject_from_ulp_last(i_inject_from_ulp_last), + .o_inject_from_ulp_ready(o_inject_from_ulp_ready), + + .o_commit_to_ulp_valid(o_commit_to_ulp_valid), + .ov_commit_to_ulp_head(ov_commit_to_ulp_head), + .ov_commit_to_ulp_data(ov_commit_to_ulp_data), + .o_commit_to_ulp_start(o_commit_to_ulp_start), + .o_commit_to_ulp_last(o_commit_to_ulp_last), + .i_commit_to_ulp_ready(i_commit_to_ulp_ready), + + .o_send_to_llp_valid(w_egress_valid), + .ov_send_to_llp_head(wv_egress_head), + .ov_send_to_llp_data(wv_egress_data), + .o_send_to_llp_start(w_egress_start), + .o_send_to_llp_last(w_egress_last), + .i_send_to_llp_ready(w_egress_ready), + + .i_recv_from_llp_valid(w_ingress_valid), + .iv_recv_from_llp_head(wv_ingress_head), + .iv_recv_from_llp_data(wv_ingress_data), + .i_recv_from_llp_start(w_ingress_start), + .i_recv_from_llp_last(w_ingress_last), + .o_recv_from_llp_ready(w_ingress_ready), + + .o_npsn_wr_en(w_npsn_wr_en), + .ov_npsn_wr_index(wv_npsn_wr_index), + .ov_npsn_wr_data(wv_npsn_wr_data), + .ov_npsn_rd_index(wv_npsn_rd_index), + .iv_npsn_rd_data(wv_npsn_rd_data), + + .ov_upsn_rd_index(wv_upsn_rd_index), + .iv_upsn_rd_data(wv_upsn_rd_data), + .o_upsn_wr_en(w_upsn_wr_en), + .ov_upsn_wr_index(wv_upsn_wr_index), + .ov_upsn_wr_data(wv_upsn_wr_data), + + .ov_ooa_epsn_rd_index(wv_ooa_epsn_rd_index), + .iv_ooa_epsn_rd_data(wv_ooa_epsn_rd_data), + .o_ooa_epsn_wr_en(w_ooa_epsn_wr_en), + .ov_ooa_epsn_wr_index(wv_ooa_epsn_wr_index), + .ov_ooa_epsn_wr_data(wv_ooa_epsn_wr_data), + + .ov_ioc_epsn_rd_index(wv_ioc_epsn_rd_index), + .iv_ioc_epsn_rd_data(wv_ioc_epsn_rd_data), + .o_ioc_epsn_wr_en(w_ioc_epsn_wr_en), + .ov_ioc_epsn_wr_index(wv_ioc_epsn_wr_index), + .ov_ioc_epsn_wr_data(wv_ioc_epsn_wr_data) +); + +PacketEncap PacketEncap_Inst( + .clk(clk), + .rst(rst), + + .i_packet_in_valid(w_egress_valid), + .iv_packet_in_head(wv_egress_head), + .iv_packet_in_data(wv_egress_data), + .i_packet_in_start(w_egress_start), + .i_packet_in_last(w_egress_last), + .o_packet_in_ready(w_egress_ready), + + .o_packet_out_valid(o_send_to_llp_valid), + .ov_packet_out_head(ov_send_to_llp_head), + .ov_packet_out_data(ov_send_to_llp_data), + .o_packet_out_start(o_send_to_llp_start), + .o_packet_out_last(o_send_to_llp_last), + .i_packet_out_ready(i_send_to_llp_ready) +); + +PacketDecap PacketDecap_Inst +( + .clk(clk), + .rst(rst), + + .i_packet_in_valid(i_recv_from_llp_valid), + .iv_packet_in_head(iv_recv_from_llp_head), + .iv_packet_in_data(iv_recv_from_llp_data), + .i_packet_in_start(i_recv_from_llp_start), + .i_packet_in_last(i_recv_from_llp_last), + .o_packet_in_ready(o_recv_from_llp_ready), + + .o_packet_out_valid(w_ingress_valid), + .ov_packet_out_head(wv_ingress_head), + .ov_packet_out_data(wv_ingress_data), + .o_packet_out_start(w_ingress_start), + .o_packet_out_last(w_ingress_last), + .i_packet_out_ready(w_ingress_ready) +); + +SRAM_TDP_Template #( + .RAM_WIDTH(`PSN_WIDTH), + .RAM_DEPTH(`QP_NUM) +) +EPSN_TABLE +( + .clk(clk), + .rst(rst), + + .wea(w_ioc_epsn_wr_en), + .addra(w_ioc_epsn_wr_en ? wv_ioc_epsn_wr_index : wv_ioc_epsn_rd_index), + .dina(wv_ioc_epsn_wr_data), + .douta(wv_ioc_epsn_rd_data), + + .web(w_ooa_epsn_wr_en), + .addrb(w_ooa_epsn_wr_en ? wv_ooa_epsn_wr_index : wv_ooa_epsn_rd_index), + .dinb(wv_ooa_epsn_wr_data), + .doutb(wv_ooa_epsn_rd_data) +); + +SRAM_SDP_Template #( + .RAM_WIDTH(`PSN_WIDTH), + .RAM_DEPTH(`QP_NUM) +) +NPSN_Table +( + .clk(clk), + .rst(rst), + + .wea(w_npsn_wr_en), + .addra(wv_npsn_wr_index), + .dina(wv_npsn_wr_data), + + .addrb(wv_npsn_rd_index), + .doutb(wv_npsn_rd_data) +); + +SRAM_SDP_Template #( + .RAM_WIDTH(`PSN_WIDTH), + .RAM_DEPTH(`QP_NUM) +) +UPSN_Table +( + .clk(clk), + .rst(rst), + + .wea(w_upsn_wr_en), + .addra(wv_upsn_wr_index), + .dina(wv_upsn_wr_data), + + .addrb(wv_upsn_rd_index), + .doutb(wv_upsn_rd_data) +); + + +/*------------------------------------------- Submodules Instatiation : End -----------------------------------------*/ + +endmodule \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/simulator/README.md b/ETH-PLUS_Jingzhao/JingZhao2/simulator/README.md new file mode 100644 index 0000000000000000000000000000000000000000..8b0ecf67b562a79ac673d8ab76aabb24fd513151 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/simulator/README.md @@ -0,0 +1 @@ +A cycle-accurate simulator based GEM-5. \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/software/README.md b/ETH-PLUS_Jingzhao/JingZhao2/software/README.md new file mode 100644 index 0000000000000000000000000000000000000000..bb5354dd1b81668e3019643d6adce8bec023892e --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/software/README.md @@ -0,0 +1 @@ +Drivers and communication library diff --git a/ETH-PLUS_Jingzhao/JingZhao2/software/drivers/README.md b/ETH-PLUS_Jingzhao/JingZhao2/software/drivers/README.md new file mode 100644 index 0000000000000000000000000000000000000000..00bed66ad06aabd6c254ac5785c8f1179390335c --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/software/drivers/README.md @@ -0,0 +1,2 @@ +- ib_hgrnic: kernel space device driver, compatible with Linux v5.3.0; +- libhgrnic: user space device driver. diff --git a/ETH-PLUS_Jingzhao/JingZhao2/software/drivers/ib_hgrnic/hgrnic_allocator.c b/ETH-PLUS_Jingzhao/JingZhao2/software/drivers/ib_hgrnic/hgrnic_allocator.c new file mode 100644 index 0000000000000000000000000000000000000000..ba1af3a255236470eb82acfc9d80b1457e67c42c --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/software/drivers/ib_hgrnic/hgrnic_allocator.c @@ -0,0 +1,280 @@ +/************************************************************** + * @author Kang Ning, NCIC, ICT, CAS + * @date 2021.09.08 + * @file hgrnic_allocator.c + * @note Queue allocator & resource ID allocator for hgrnic. + *************************************************************/ + +#include +#include +#include + +#include "hgrnic_dev.h" + +/** + * @description: Allocate one resource element (UAR, PD, MPT, CQ, QP). + * Trivial bitmap-based allocator + */ +u32 hgrnic_alloc (struct hgrnic_alloc *alloc) +{ + unsigned long flags; + u32 obj; + + spin_lock_irqsave(&alloc->lock, flags); + + obj = find_next_zero_bit(alloc->table, alloc->max, alloc->last); + if (obj >= alloc->max) { + alloc->top = (alloc->top + alloc->max) & alloc->mask; + obj = find_first_zero_bit(alloc->table, alloc->max); + } + + if (obj < alloc->max) { + alloc->last = obj + 1; + if (alloc->last == alloc->max) + alloc->last = 0; + + set_bit(obj, alloc->table); + obj |= alloc->top; + } else + obj = -1; + + spin_unlock_irqrestore(&alloc->lock, flags); + + return obj; +} + +void hgrnic_free (struct hgrnic_alloc *alloc, u32 obj) +{ + unsigned long flags; + + obj &= alloc->max - 1; + + spin_lock_irqsave(&alloc->lock, flags); + + clear_bit(obj, alloc->table); + // alloc->last = min(alloc->last, obj); FIXME: This line is removed because of the BUG on hardware. + alloc->top = (alloc->top + alloc->max) & alloc->mask; + + spin_unlock_irqrestore(&alloc->lock, flags); +} + +/** + * @note Init hgrnic resources number (including PD, UAR, MPT, EQ, CQ, QP). + */ +int hgrnic_alloc_init (struct hgrnic_alloc *alloc, u32 num, u32 mask) { + // int i; + + /* num must be a power of 2 */ + if (num != 1 << (ffs(num) - 1)) { + return -EINVAL; + } + + alloc->last = 0; + alloc->top = 0; + alloc->max = num; + alloc->mask = mask; + spin_lock_init(&alloc->lock); + alloc->table = kmalloc_array(BITS_TO_LONGS(num), sizeof(long), + GFP_KERNEL); + if (!alloc->table) { + return -ENOMEM; + } + + bitmap_zero(alloc->table, num); + + return 0; +} + +/** + * @note Init hgrnic resources (including PD, UAR, MPT). + */ +void hgrnic_alloc_cleanup (struct hgrnic_alloc *alloc) { + kfree(alloc->table); +} + +/* + * Array of pointers with lazy allocation of leaf pages. Callers of + * _get, _set and _clear methods must use a lock or otherwise + * serialize access to the array. + */ + +#define HGRNIC_ARRAY_MASK (PAGE_SIZE / sizeof (void *) - 1) + +/** + * @note Get Resource (QP, CQ) data struct according to resource id. + * @param array Resource table + * @param index Resource id (QPN, CQN) + * @return Data struct pointer of the resources + */ +void *hgrnic_array_get(struct hgrnic_array *array, int index) +{ + int p = (index * sizeof (void *)) >> PAGE_SHIFT; + + if (array->page_list[p].page) + return array->page_list[p].page[index & HGRNIC_ARRAY_MASK]; + else + return NULL; +} + +/** + * @note Set Resource (QP, CQ) data struct according to resource ID. + * @param array Resource table + * @param index Resource ID (QPN, CQN) + * @param value Data struct pointer of the resources + */ +int hgrnic_array_set(struct hgrnic_array *array, int index, void *value) +{ + int p = (index * sizeof (void *)) >> PAGE_SHIFT; + + /* Allocate with GFP_ATOMIC because we'll be called with locks held. */ + if (!array->page_list[p].page) + array->page_list[p].page = (void **) get_zeroed_page(GFP_ATOMIC); + + if (!array->page_list[p].page) + return -ENOMEM; + + array->page_list[p].page[index & HGRNIC_ARRAY_MASK] = value; + ++array->page_list[p].used; + + return 0; +} + +void hgrnic_array_clear(struct hgrnic_array *array, int index) +{ + int p = (index * sizeof (void *)) >> PAGE_SHIFT; + + if (--array->page_list[p].used == 0) { + free_page((unsigned long) array->page_list[p].page); + array->page_list[p].page = NULL; + } else + array->page_list[p].page[index & HGRNIC_ARRAY_MASK] = NULL; + + if (array->page_list[p].used < 0) + pr_debug("Array %p index %d page %d with ref count %d < 0\n", + array, index, p, array->page_list[p].used); +} + +/** + * @note The array is used to find resource data struct according + * to resource number (QPN, CQN) + * @param array resource lookup array. + * @param nent maximum number of resources. + */ +int hgrnic_array_init (struct hgrnic_array *array, int nent) +{ + int npage = (nent * sizeof (void *) + PAGE_SIZE - 1) / PAGE_SIZE; + int i; + + array->page_list = kmalloc_array(npage, sizeof(*array->page_list), + GFP_KERNEL); + if (!array->page_list) + return -ENOMEM; + + for (i = 0; i < npage; ++i) { + array->page_list[i].page = NULL; + array->page_list[i].used = 0; + } + + return 0; +} + +void hgrnic_array_cleanup(struct hgrnic_array *array, int nent) +{ + int i; + + for (i = 0; i < (nent * sizeof (void *) + PAGE_SIZE - 1) / PAGE_SIZE; ++i) + free_page((unsigned long) array->page_list[i].page); + + kfree(array->page_list); +} + +/** + * Handling for queue buffers -- we allocate a bunch of memory and + * register it in a memory region at HCA virtual address 0. If the + * requested size is > max_direct, we split the allocation into + * multiple pages, so we don't require too much contiguous memory. + */ +int hgrnic_buf_alloc(struct hgrnic_dev *dev, int size, + union hgrnic_buf *buf, int *is_direct, struct hgrnic_pd *pd, + int hca_write, struct hgrnic_mr *mr) +{ + int err = -ENOMEM; + int npages, shift; + u64 *dma_list = NULL; + dma_addr_t t; + int i; + + *is_direct = 0; + npages = (size + PAGE_SIZE - 1) / PAGE_SIZE; + shift = PAGE_SHIFT; + + dma_list = kmalloc_array(npages, sizeof(*dma_list), + GFP_KERNEL); + if (!dma_list) + return -ENOMEM; + + buf->page_list = kmalloc_array(npages, + sizeof(*buf->page_list), + GFP_KERNEL); + if (!buf->page_list) + goto err_out; + + for (i = 0; i < npages; ++i) + buf->page_list[i].buf = NULL; + + for (i = 0; i < npages; ++i) { + buf->page_list[i].buf = + dma_alloc_coherent(&dev->pdev->dev, PAGE_SIZE, + &t, GFP_KERNEL); + if (!buf->page_list[i].buf) + goto err_free; + + dma_list[i] = t; + dma_unmap_addr_set(&buf->page_list[i], mapping, t); + + clear_page(buf->page_list[i].buf); + } + + hgrnic_dump("%d", npages); + err = hgrnic_mr_alloc_phys(dev, pd->pd_num, + dma_list, shift, npages, + 0, size, + HGRNIC_MPT_FLAG_LOCAL_READ | + (hca_write ? HGRNIC_MPT_FLAG_LOCAL_WRITE : 0), + mr); + if (err) + goto err_free; + + kfree(dma_list); + + return 0; + +err_free: + hgrnic_buf_free(dev, size, buf, *is_direct, NULL); + +err_out: + kfree(dma_list); + + return err; +} + +void hgrnic_buf_free(struct hgrnic_dev *dev, int size, union hgrnic_buf *buf, + int is_direct, struct hgrnic_mr *mr) +{ + int i; + + if (mr) + hgrnic_free_mr(dev, mr); + + if (is_direct) + dma_free_coherent(&dev->pdev->dev, size, buf->direct.buf, + dma_unmap_addr(&buf->direct, mapping)); + else { + for (i = 0; i < (size + PAGE_SIZE - 1) / PAGE_SIZE; ++i) + dma_free_coherent(&dev->pdev->dev, PAGE_SIZE, + buf->page_list[i].buf, + dma_unmap_addr(&buf->page_list[i], + mapping)); + kfree(buf->page_list); + } +} diff --git a/ETH-PLUS_Jingzhao/JingZhao2/software/drivers/ib_hgrnic/hgrnic_cmd.c b/ETH-PLUS_Jingzhao/JingZhao2/software/drivers/ib_hgrnic/hgrnic_cmd.c new file mode 100644 index 0000000000000000000000000000000000000000..eeb4726ec02913584dc02516bb797805a1b693e9 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/software/drivers/ib_hgrnic/hgrnic_cmd.c @@ -0,0 +1,1241 @@ +/************************************************************** + * @author Kang Ning, NCIC, ICT, CAS + * @date 2021.09.08 + * @file hgrnic_cmd.c + * @note Command for low-level driver to interact with HCA hardware. + *************************************************************/ + +#include +#include +#include +#include +#include +#include +#include +#include + + +#include "hgrnic_cmd.h" + +#define CMD_POLL_TOKEN 0xffff + +enum { + HCR_IN_PARAM_OFFSET = 0x00, + HCR_IN_MODIFIER_OFFSET = 0x08, + HCR_OUT_PARAM_OFFSET = 0x0c, + HCR_TOKEN_OFFSET = 0x14, + HCR_STATUS_OFFSET = 0x18, + + HCR_OPMOD_SHIFT = 12, + HCA_E_BIT = 22, + HCR_GO_BIT = 23 +}; + +enum { + /* initialization and general commands */ + CMD_QUERY_DEV_LIM = 0x3, + CMD_QUERY_ADAPTER = 0x6, + CMD_INIT_HCA = 0x7, + CMD_CLOSE_HCA = 0x8, + // CMD_QUERY_HCA = 0xb, + CMD_INIT_IB = 0x9, + CMD_CLOSE_IB = 0xa, + CMD_SET_IB = 0xc, + + CMD_MAP_ICM = 0xffa, + CMD_UNMAP_ICM = 0xff9, + + /* TPT commands */ + CMD_SW2HW_MPT = 0xd, + // CMD_QUERY_MPT = 0xe, + CMD_HW2SW_MPT = 0xf, + // CMD_READ_MTT = 0x10, + CMD_WRITE_MTT = 0x11, + // CMD_SYNC_TPT = 0x2f, + + /* EQ commands */ + CMD_MAP_EQ = 0x12, + CMD_SW2HW_EQ = 0x13, + CMD_HW2SW_EQ = 0x14, + // CMD_QUERY_EQ = 0x15, + + /* CQ commands */ + CMD_SW2HW_CQ = 0x16, + CMD_HW2SW_CQ = 0x17, + // CMD_QUERY_CQ = 0x18, + CMD_RESIZE_CQ = 0x2c, + + /* QP/EE commands */ + CMD_RST2INIT_QPEE = 0x19, + CMD_INIT2RTR_QPEE = 0x1a, + CMD_RTR2RTS_QPEE = 0x1b, + CMD_RTS2RTS_QPEE = 0x1c, + CMD_SQERR2RTS_QPEE = 0x1d, + CMD_2ERR_QPEE = 0x1e, + CMD_RTS2SQD_QPEE = 0x1f, + CMD_SQD2SQD_QPEE = 0x38, + CMD_SQD2RTS_QPEE = 0x20, + CMD_ERR2RST_QPEE = 0x21, + CMD_QUERY_QPEE = 0x22, + CMD_INIT2INIT_QPEE = 0x2d, + CMD_SUSPEND_QPEE = 0x32, + CMD_UNSUSPEND_QPEE = 0x33, + + /* special QPs and management commands */ + CMD_CONF_SPECIAL_QP = 0x23, + CMD_MAD_IFC = 0x24, + + /* multicast commands */ + CMD_READ_MGM = 0x25, + CMD_WRITE_MGM = 0x26, + CMD_MGID_HASH = 0x27, + + /* miscellaneous commands */ + CMD_DIAG_RPRT = 0x30, + CMD_NOP = 0x31, + + /* debug commands */ + CMD_QUERY_DEBUG_MSG = 0x2a, + CMD_SET_DEBUG_MSG = 0x2b, +}; + + +enum { + CMD_TIME_CLASS_A = 60 * HZ, + CMD_TIME_CLASS_B = 60 * HZ, + CMD_TIME_CLASS_C = 60 * HZ, + CMD_TIME_CLASS_D = 60 * HZ +}; + +enum { + GO_BIT_TIMEOUT = HZ * 10 +}; + + +static inline int go_bit (struct hgrnic_dev *dev) { + u32 r = readl(dev->hcr + HCR_STATUS_OFFSET); + + return r & swab32(1 << HCR_GO_BIT); +} + + +static int hgrnic_cmd_post_hcr (struct hgrnic_dev *dev, u64 in_param, + u64 out_param, u32 in_modifier, + u8 op_modifier, u16 op, u16 token) +{ + if (go_bit(dev)) { + printk("go bit unclear\n"); + return -EAGAIN; + } + + /* + * We use writel (instead of something like memcpy_toio) + * because writes of less than 32 bits to the HCR don't work + * (and some architectures such as ia64 implement memcpy_toio + * in terms of writeb). + */ + __raw_writel((__force u32) cpu_to_le32(in_param >> 32), dev->hcr + 0 * 4); + __raw_writel((__force u32) cpu_to_le32(in_param & 0xfffffffful), dev->hcr + 1 * 4); + __raw_writel((__force u32) cpu_to_le32(in_modifier), dev->hcr + 2 * 4); + __raw_writel((__force u32) cpu_to_le32(out_param >> 32), dev->hcr + 3 * 4); + __raw_writel((__force u32) cpu_to_le32(out_param & 0xfffffffful), dev->hcr + 4 * 4); + __raw_writel((__force u32) cpu_to_le32(token << 16), dev->hcr + 5 * 4); + /* __raw_writel may not order writes. */ + wmb(); + + __raw_writel((__force u32) cpu_to_le32((1 << HCR_GO_BIT) | + (0) | + (op_modifier << HCR_OPMOD_SHIFT) | + op), dev->hcr + 6 * 4); + + + return 0; +} + +static int hgrnic_cmd_post (struct hgrnic_dev *dev, u64 in_param, u64 out_param, + u32 in_modifier, u8 op_modifier, u16 op, u16 token) +{ + int err = 0; + + mutex_lock(&dev->cmd.hcr_mutex); + + err = hgrnic_cmd_post_hcr(dev, in_param, out_param, in_modifier, + op_modifier, op, token); + + mutex_unlock(&dev->cmd.hcr_mutex); + return err; +} + + +static int hgrnic_status_to_errno (u8 status) +{ + static const int trans_table[] = { + [HGRNIC_CMD_STAT_INTERNAL_ERR] = -EIO, + [HGRNIC_CMD_STAT_BAD_OP] = -EPERM, + [HGRNIC_CMD_STAT_BAD_PARAM] = -EINVAL, + [HGRNIC_CMD_STAT_BAD_SYS_STATE] = -ENXIO, + [HGRNIC_CMD_STAT_BAD_RESOURCE] = -EBADF, + [HGRNIC_CMD_STAT_RESOURCE_BUSY] = -EBUSY, + [HGRNIC_CMD_STAT_DDR_MEM_ERR] = -ENOMEM, + [HGRNIC_CMD_STAT_EXCEED_LIM] = -ENOMEM, + [HGRNIC_CMD_STAT_BAD_RES_STATE] = -EBADF, + [HGRNIC_CMD_STAT_BAD_INDEX] = -EBADF, + [HGRNIC_CMD_STAT_BAD_NVMEM] = -EFAULT, + [HGRNIC_CMD_STAT_BAD_QPEE_STATE] = -EINVAL, + [HGRNIC_CMD_STAT_BAD_SEG_PARAM] = -EFAULT, + [HGRNIC_CMD_STAT_REG_BOUND] = -EBUSY, + [HGRNIC_CMD_STAT_LAM_NOT_PRE] = -EAGAIN, + [HGRNIC_CMD_STAT_BAD_PKT] = -EBADMSG, + [HGRNIC_CMD_STAT_BAD_SIZE] = -ENOMEM, + }; + + if (status >= ARRAY_SIZE(trans_table) || + (status != HGRNIC_CMD_STAT_OK + && trans_table[status] == 0)) + return -EINVAL; + + return trans_table[status]; +} + + +static int hgrnic_cmd_poll (struct hgrnic_dev *dev, u64 in_param, + u64 *out_param, int out_is_imm, u32 in_modifier, u8 op_modifier, + u16 op, unsigned long timeout) +{ + int err = 0; + unsigned long end; + u8 status; + + down(&dev->cmd.poll_sem); + + err = hgrnic_cmd_post(dev, in_param, out_param ? *out_param : 0, + in_modifier, op_modifier, op, CMD_POLL_TOKEN); + + if (err) + goto out; + + end = timeout + jiffies; + while (go_bit(dev) && time_before(jiffies, end)) { + set_current_state(TASK_RUNNING); + schedule(); + } + + if (go_bit(dev)) { + err = -EBUSY; + goto out; + } + + if (out_is_imm && out_param) { + *out_param = + (u64) le32_to_cpu((__force __be32) + __raw_readl(dev->hcr + HCR_OUT_PARAM_OFFSET)) << 32 | + (u64) le32_to_cpu((__force __be32) + __raw_readl(dev->hcr + HCR_OUT_PARAM_OFFSET + 4)); + } else if (out_is_imm) { + err = -EINVAL; + goto out; + } + + status = le32_to_cpu((__force __be32) __raw_readl(dev->hcr + HCR_STATUS_OFFSET)) >> 24; + if (status) { + hgrnic_dbg(dev, "Command %02x completed with status %02x\n", + op, status); + err = hgrnic_status_to_errno(status); + } + +out: + up(&dev->cmd.poll_sem); + return err; +} + + +/* Invoke a command with an output mailbox */ +static int hgrnic_cmd_box (struct hgrnic_dev *dev, u64 in_param, + u64 out_param, u32 in_modifier, + u8 op_modifier, u16 op, unsigned long timeout) +{ + return hgrnic_cmd_poll(dev, in_param, &out_param, 0, + in_modifier, op_modifier, op, timeout); +} + +/* Invoke a command with no output parameter */ +static int hgrnic_cmd(struct hgrnic_dev *dev, u64 in_param, u32 in_modifier, + u8 op_modifier, u16 op, unsigned long timeout) +{ + return hgrnic_cmd_box(dev, in_param, 0, in_modifier, + op_modifier, op, timeout); +} + + +int hgrnic_cmd_init (struct hgrnic_dev *dev) { + mutex_init(&dev->cmd.hcr_mutex); + sema_init(&dev->cmd.poll_sem, 1); + + dev->hcr = ioremap(pci_resource_start(dev->pdev, 0) + HGRNIC_HCR_BASE, + HGRNIC_HCR_SIZE); + if (!dev->hcr) { + hgrnic_err(dev, "Couldn't map command register."); + return -ENOMEM; + } + + dev->cmd.pool = dma_pool_create("hgrnic_cmd", &dev->pdev->dev, + HGRNIC_MAILBOX_SIZE, + HGRNIC_MAILBOX_SIZE, 0); + if (!dev->cmd.pool) { + iounmap(dev->hcr); + return -ENOMEM; + } + + return 0; +} + +void hgrnic_cmd_cleanup (struct hgrnic_dev *dev) { + dma_pool_destroy(dev->cmd.pool); + iounmap(dev->hcr); +} + + +struct hgrnic_mailbox *hgrnic_alloc_mailbox (struct hgrnic_dev *dev, + gfp_t gfp_mask) +{ + struct hgrnic_mailbox *mailbox; + + mailbox = kmalloc(sizeof *mailbox, gfp_mask); + if (!mailbox) + return ERR_PTR(-ENOMEM); + + mailbox->buf = dma_pool_alloc(dev->cmd.pool, gfp_mask, &mailbox->dma); + if (!mailbox->buf) { + kfree(mailbox); + return ERR_PTR(-ENOMEM); + } + + return mailbox; +} + +void hgrnic_free_mailbox (struct hgrnic_dev *dev, struct hgrnic_mailbox *mailbox) +{ + if (!mailbox) + return; + + dma_pool_free(dev->cmd.pool, mailbox->buf, mailbox->dma); + kfree(mailbox); +} + + +/** + * @description: + * Command function. + * Get parameters from HCA hardware. + */ +int hgrnic_QUERY_DEV_LIM (struct hgrnic_dev *dev, struct hgrnic_dev_lim *dev_lim) { + + struct hgrnic_mailbox *mailbox; + u32 *outbox; + u8 field; + u16 size; + u64 entry; + int err; + +#define QUERY_DEV_LIM_OUT_SIZE 0x40 + +// Reserved number of resources, 8 Bytes +#define QUERY_DEV_LIM_RSVD_QP_OFFSET 0x00 +#define QUERY_DEV_LIM_RSVD_CQ_OFFSET 0x01 +#define QUERY_DEV_LIM_RSVD_EQ_OFFSET 0x02 +#define QUERY_DEV_LIM_RSVD_MTT_OFFSET 0x03 +#define QUERY_DEV_LIM_RSVD_PD_OFFSET 0x05 +#define QUERY_DEV_LIM_RSVD_LKEY_OFFSET 0x07 + +// Max queue size +#define QUERY_DEV_LIM_MAX_QP_SZ_OFFSET 0x08 +#define QUERY_DEV_LIM_MAX_CQ_SZ_OFFSET 0x0a + +// max number of resources +#define QUERY_DEV_LIM_MAX_QP_OFFSET 0x0c +#define QUERY_DEV_LIM_MAX_CQ_OFFSET 0x0d +#define QUERY_DEV_LIM_MAX_EQ_OFFSET 0x0e +#define QUERY_DEV_LIM_MAX_MPT_OFFSET 0x0f +#define QUERY_DEV_LIM_MAX_PD_OFFSET 0x10 +#define QUERY_DEV_LIM_MAX_GID_OFFSET 0x12 +#define QUERY_DEV_LIM_MAX_PKEY_OFFSET 0x13 + +#define QUERY_DEV_LIM_MAX_MTT_SEG_OFFSET 0x15 + +// size of context +#define QUERY_DEV_LIM_QPC_ENTRY_SZ_OFFSET 0x18 +#define QUERY_DEV_LIM_CQC_ENTRY_SZ_OFFSET 0x1a +#define QUERY_DEV_LIM_EQC_ENTRY_SZ_OFFSET 0x1c +#define QUERY_DEV_LIM_MPT_ENTRY_SZ_OFFSET 0x1e + +// aux +#define QUERY_DEV_LIM_ACK_DELAY_OFFSET 0x20 +#define QUERY_DEV_LIM_MTU_WIDTH_OFFSET 0x21 +#define QUERY_DEV_LIM_VL_PORT_OFFSET 0x23 + +// description size +#define QUERY_DEV_LIM_PAGE_SZ_OFFSET 0x25 +#define QUERY_DEV_LIM_MAX_SG_OFFSET 0x29 +#define QUERY_DEV_LIM_MAX_DESC_SZ_OFFSET 0x2a +#define QUERY_DEV_LIM_MAX_SG_RQ_OFFSET 0x2d +#define QUERY_DEV_LIM_MAX_DESC_SZ_RQ_OFFSET 0x2e + +// ICM space size +#define QUERY_DEV_LIM_MAX_ICM_SZ_OFFSET 0x30 + + + mailbox = hgrnic_alloc_mailbox(dev, GFP_KERNEL); + if (IS_ERR(mailbox)) + return PTR_ERR(mailbox); + outbox = mailbox->buf; + + printk(KERN_INFO PFX "Enter hgrnic_QUERY_DEV_LIM. %lx\n", (long)mailbox->dma); + + err = hgrnic_cmd_box(dev, 0, mailbox->dma, 0, 0, CMD_QUERY_DEV_LIM, + CMD_TIME_CLASS_A); + if (unlikely(err)) { + goto out; + } + + printk(KERN_INFO PFX "Get hgrnic_QUERY_DEV_LIM.\n"); + printk(KERN_INFO PFX "dev lim outbox: \n0x%x 0x%x 0x%x 0x%x \n" + "0x%x 0x%x 0x%x 0x%x\n" + "0x%x 0x%x 0x%x 0x%x\n" + "0x%x 0x%x 0x%x 0x%x\n", + *outbox, *(outbox+1), *(outbox+2), *(outbox+3), + *(outbox+4), *(outbox+5), *(outbox+6), *(outbox+7), + *(outbox+8), *(outbox+9), *(outbox+10), *(outbox+11), + *(outbox+12), *(outbox+13), *(outbox+14), *(outbox+15)); + + + HGRNIC_GET(field, outbox, QUERY_DEV_LIM_RSVD_QP_OFFSET); + dev_lim->reserved_qps = 1 << (field & 0xf); + printk(KERN_INFO PFX "resv_qp: %d", dev_lim->reserved_qps); + + HGRNIC_GET(field, outbox, QUERY_DEV_LIM_RSVD_CQ_OFFSET); + dev_lim->reserved_cqs = 1 << (field & 0xf); + printk(KERN_INFO PFX "resv_cq: %d", dev_lim->reserved_cqs); + + HGRNIC_GET(field, outbox, QUERY_DEV_LIM_RSVD_EQ_OFFSET); + dev_lim->reserved_eqs = 1 << (field & 0xf); + printk(KERN_INFO PFX "resv_eq: %d", dev_lim->reserved_eqs); + + HGRNIC_GET(field, outbox, QUERY_DEV_LIM_RSVD_MTT_OFFSET); + dev_lim->reserved_mtts = 1 << (field & 0xf); + printk(KERN_INFO PFX "resv_mtt: %d", dev_lim->reserved_mtts); + + HGRNIC_GET(field, outbox, QUERY_DEV_LIM_RSVD_PD_OFFSET); + dev_lim->reserved_pds = 1 << (field & 0xf); + printk(KERN_INFO PFX "resv_pd: %d", dev_lim->reserved_pds); + + HGRNIC_GET(field, outbox, QUERY_DEV_LIM_RSVD_LKEY_OFFSET); + dev_lim->reserved_lkey = 1 << (field & 0xf); + printk(KERN_INFO PFX "resv_lkey: %d", dev_lim->reserved_lkey); + + HGRNIC_GET(size, outbox, QUERY_DEV_LIM_MAX_QP_SZ_OFFSET); + dev_lim->max_qp_sz = 1 << size; + printk(KERN_INFO PFX "max_qp_sz: %d", dev_lim->max_qp_sz); + + HGRNIC_GET(size, outbox, QUERY_DEV_LIM_MAX_CQ_SZ_OFFSET); + dev_lim->max_cq_sz = 1 << size; + printk(KERN_INFO PFX "max_cq_sz: %d", dev_lim->max_cq_sz); + + HGRNIC_GET(field, outbox, QUERY_DEV_LIM_MAX_QP_OFFSET); + dev_lim->max_qps = 1 << (field & 0x1f); + printk(KERN_INFO PFX "max_qps: %d", dev_lim->max_qps); + + HGRNIC_GET(field, outbox, QUERY_DEV_LIM_MAX_CQ_OFFSET); + dev_lim->max_cqs = 1 << (field & 0x1f); + printk(KERN_INFO PFX "max_cqs: %d", dev_lim->max_cqs); + + HGRNIC_GET(field, outbox, QUERY_DEV_LIM_MAX_EQ_OFFSET); + dev_lim->max_eqs = 1 << (field & 0x7); + printk(KERN_INFO PFX "max_eqs: %d", dev_lim->max_eqs); + + HGRNIC_GET(field, outbox, QUERY_DEV_LIM_MAX_MPT_OFFSET); + dev_lim->max_mpts = 1 << (field & 0x3f); + printk(KERN_INFO PFX "max_mpts: %d", dev_lim->max_mpts); + + HGRNIC_GET(field, outbox, QUERY_DEV_LIM_MAX_PD_OFFSET); + dev_lim->max_pds = 1 << (field & 0x3f); + printk(KERN_INFO PFX "max_pds: %d", dev_lim->max_pds); + + HGRNIC_GET(field, outbox, QUERY_DEV_LIM_MAX_GID_OFFSET); + dev_lim->max_gids = 1 << (field & 0xf); + printk(KERN_INFO PFX "max_gids: %d", dev_lim->max_gids); + + HGRNIC_GET(field, outbox, QUERY_DEV_LIM_MAX_PKEY_OFFSET); + dev_lim->max_pkeys = 1 << (field & 0xf); + printk(KERN_INFO PFX "max_pkeys: %d", field & 0xf); + + HGRNIC_GET(field, outbox, QUERY_DEV_LIM_MAX_MTT_SEG_OFFSET); + dev_lim->max_mtt_seg = field; + printk(KERN_INFO PFX "max_mtt_seg: %d", dev_lim->max_mtt_seg); + + HGRNIC_GET(size, outbox, QUERY_DEV_LIM_QPC_ENTRY_SZ_OFFSET); + dev_lim->qpc_entry_sz = size; + printk(KERN_INFO PFX "qpc_entry_sz: %d", dev_lim->qpc_entry_sz); + + HGRNIC_GET(size, outbox, QUERY_DEV_LIM_CQC_ENTRY_SZ_OFFSET); + dev_lim->cqc_entry_sz = size; + printk(KERN_INFO PFX "cqc_entry_sz: %d", dev_lim->cqc_entry_sz); + + HGRNIC_GET(size, outbox, QUERY_DEV_LIM_EQC_ENTRY_SZ_OFFSET); + dev_lim->eqc_entry_sz = size; + printk(KERN_INFO PFX "eqc_entry_sz: %d", dev_lim->eqc_entry_sz); + + HGRNIC_GET(size, outbox, QUERY_DEV_LIM_MPT_ENTRY_SZ_OFFSET); + dev_lim->mpt_entry_sz = size; + printk(KERN_INFO PFX "mpt_entry_sz: %d", dev_lim->mpt_entry_sz); + + HGRNIC_GET(field, outbox, QUERY_DEV_LIM_ACK_DELAY_OFFSET); + dev_lim->local_ca_ack_delay = field & 0xf; + printk(KERN_INFO PFX "local_ca_ack_delay: %d", dev_lim->local_ca_ack_delay); + + HGRNIC_GET(field, outbox, QUERY_DEV_LIM_MTU_WIDTH_OFFSET); + dev_lim->max_mtu = field >> 4; + dev_lim->max_port_width = field & 0xf; + printk(KERN_INFO PFX "max_mtu: %d", dev_lim->max_mtu); + printk(KERN_INFO PFX "max_port_width: %d", dev_lim->max_port_width); + + HGRNIC_GET(field, outbox, QUERY_DEV_LIM_VL_PORT_OFFSET); + dev_lim->max_vl = field >> 4; + dev_lim->num_ports = field & 0xf; + printk(KERN_INFO PFX "max_vl: %d", dev_lim->max_vl); + printk(KERN_INFO PFX "num_ports: %d", dev_lim->num_ports); + + HGRNIC_GET(field, outbox, QUERY_DEV_LIM_PAGE_SZ_OFFSET); + dev_lim->min_page_sz = 1 << field; + printk(KERN_INFO PFX "min_page_sz: %d", dev_lim->min_page_sz); + + HGRNIC_GET(field, outbox, QUERY_DEV_LIM_MAX_SG_OFFSET); + dev_lim->max_sg = field; + printk(KERN_INFO PFX "max_sg: %d", dev_lim->max_sg); + + HGRNIC_GET(size, outbox, QUERY_DEV_LIM_MAX_DESC_SZ_OFFSET); + dev_lim->max_desc_sz = size; + printk(KERN_INFO PFX "max_desc_sz: %d", dev_lim->max_desc_sz); + + HGRNIC_GET(field, outbox, QUERY_DEV_LIM_MAX_SG_RQ_OFFSET); + dev_lim->max_sg = min_t(int, field, dev_lim->max_sg); + printk(KERN_INFO PFX "max_sg_rq: %d", field); + + HGRNIC_GET(size, outbox, QUERY_DEV_LIM_MAX_DESC_SZ_RQ_OFFSET); + dev_lim->max_desc_sz = min_t(int, size, dev_lim->max_desc_sz); + printk(KERN_INFO PFX "max_desc_sz_rq: %d", size); + + HGRNIC_GET(entry, outbox, QUERY_DEV_LIM_MAX_ICM_SZ_OFFSET); + dev_lim->max_icm_sz = entry; + printk(KERN_INFO PFX "max_icm_sz: 0x%llx", dev_lim->max_icm_sz); + +out: + hgrnic_free_mailbox(dev, mailbox); + return err; +} + +/** + * @description: + * Command function. + * Query board information of board id. + * !TODO: We may add more information on this command. + */ +int hgrnic_QUERY_ADAPTER (struct hgrnic_dev *dev, u64 *board_id) { + struct hgrnic_mailbox *mailbox; + u32 *outbox; + int err; + +#define QUERY_ADAPTER_OUT_SIZE 0x20 +#define QUERY_ADAPTER_ID_OFFSET 0x18 + + + mailbox = hgrnic_alloc_mailbox(dev, GFP_KERNEL); + if (IS_ERR(mailbox)) { + return PTR_ERR(mailbox); + } + + + outbox = mailbox->buf; + *(outbox) = 0xFF; + *(outbox+1) = 0xFF; + *(outbox+2) = 0xFF; + *(outbox+3) = 0xFF; + err = hgrnic_cmd_box(dev, 0, mailbox->dma, 0, 0, CMD_QUERY_ADAPTER, + CMD_TIME_CLASS_A); + + + if (unlikely(err)) { + goto out; + } + + + HGRNIC_GET(*board_id, outbox, QUERY_ADAPTER_ID_OFFSET); + printk(KERN_INFO PFX "board_id: 0x%llx\n", *board_id); + // printk(KERN_INFO PFX "board id outbox: 0x%x 0x%x 0x%x 0x%x " + // "0x%x 0x%x 0x%x 0x%x.\n", + // *outbox, *(outbox+1), *(outbox+2), *(outbox+3), + // *(outbox+4), *(outbox+5), *(outbox+6), *(outbox+7)); +out: + hgrnic_free_mailbox(dev, mailbox); + return err; +} + +/** + * @description: + * Command function. + * Send ICM virtual address layout to HCA board. + * This command should execute before map ICM virtual <-> physical address. + */ +int hgrnic_INIT_HCA (struct hgrnic_dev *mdev, struct hgrnic_init_hca_param *param) +{ + struct hgrnic_mailbox *mailbox; + __le32 *inbox; + int err; + +#define INIT_HCA_IN_SIZE 0x40 +#define INIT_HCA_QPC_OFFSET 0x008 +#define INIT_HCA_QPC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x00) +#define INIT_HCA_LOG_QP_OFFSET (INIT_HCA_QPC_OFFSET + 0x07) +#define INIT_HCA_CQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x08) +#define INIT_HCA_LOG_CQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x0f) +#define INIT_HCA_EQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x10) +#define INIT_HCA_LOG_EQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x17) + +#define INIT_HCA_TPT_OFFSET 0x030 +#define INIT_HCA_MPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x00) +#define INIT_HCA_LOG_MPT_SZ_OFFSET (INIT_HCA_TPT_OFFSET + 0x07) +#define INIT_HCA_MTT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x08) + + mailbox = hgrnic_alloc_mailbox(mdev, GFP_KERNEL); + if (IS_ERR(mailbox)) + return PTR_ERR(mailbox); + inbox = mailbox->buf; + + memset(inbox, 0, INIT_HCA_IN_SIZE); + + /* QPC/CQC/EQC attributes */ + HGRNIC_PUT(inbox, param->qpc_base, INIT_HCA_QPC_BASE_OFFSET); + HGRNIC_PUT(inbox, param->log_num_qps, INIT_HCA_LOG_QP_OFFSET); + HGRNIC_PUT(inbox, param->cqc_base, INIT_HCA_CQC_BASE_OFFSET); + HGRNIC_PUT(inbox, param->log_num_cqs, INIT_HCA_LOG_CQ_OFFSET); + HGRNIC_PUT(inbox, param->eqc_base, INIT_HCA_EQC_BASE_OFFSET); + HGRNIC_PUT(inbox, param->log_num_eqs, INIT_HCA_LOG_EQ_OFFSET); + + /* TPT attributes */ + HGRNIC_PUT(inbox, param->mpt_base, INIT_HCA_MPT_BASE_OFFSET); + HGRNIC_PUT(inbox, param->log_mpt_sz, INIT_HCA_LOG_MPT_SZ_OFFSET); + HGRNIC_PUT(inbox, param->mtt_base, INIT_HCA_MTT_BASE_OFFSET); + + printk(KERN_INFO PFX "init hca outbox: 0x%x 0x%x 0x%x 0x%x " + "0x%x 0x%x 0x%x 0x%x.\n", + *inbox, *(inbox+1), *(inbox+2), *(inbox+3), + *(inbox+4), *(inbox+5), *(inbox+6), *(inbox+7)); + + printk(KERN_INFO PFX "init hca outbox: 0x%x 0x%x 0x%x 0x%x " + "0x%x 0x%x 0x%x 0x%x.\n", + *(inbox+8), *(inbox+9), *(inbox+10), *(inbox+11), + *(inbox+12), *(inbox+13), *(inbox+14), *(inbox+15)); + + err = hgrnic_cmd(mdev, mailbox->dma, 0, 0, + CMD_INIT_HCA, CMD_TIME_CLASS_D); + + hgrnic_free_mailbox(mdev, mailbox); + return err; +} + +/** + * @description: + * Command function. + * Cancel ICM virtual address layout stored on HCA hardware. + * Execute this command when the driver is ready to exit + * (error or normally). + */ +int hgrnic_CLOSE_HCA (struct hgrnic_dev *dev) { + return hgrnic_cmd(dev, 0, 0, 0, CMD_CLOSE_HCA, CMD_TIME_CLASS_C); +} + +/** + * @description: + * Command function. + * Configure IB network related information (GID, GUID, etc). + * !TODO: We haven't implemented this command yet + */ +int hgrnic_INIT_IB (struct hgrnic_dev *dev, struct hgrnic_init_ib_param *param, + int port) { + struct hgrnic_mailbox *mailbox; + u32 *inbox; + int err; + u32 flags; + +#define INIT_IB_IN_SIZE 56 +#define INIT_IB_FLAGS_OFFSET 0x00 +#define INIT_IB_FLAG_SIG (1 << 18) +#define INIT_IB_FLAG_NG (1 << 17) +#define INIT_IB_FLAG_G0 (1 << 16) +#define INIT_IB_VL_SHIFT 4 +#define INIT_IB_PORT_WIDTH_SHIFT 8 +#define INIT_IB_MTU_SHIFT 12 +#define INIT_IB_MAX_GID_OFFSET 0x06 +#define INIT_IB_MAX_PKEY_OFFSET 0x0a +#define INIT_IB_GUID0_OFFSET 0x10 +#define INIT_IB_NODE_GUID_OFFSET 0x18 +#define INIT_IB_SI_GUID_OFFSET 0x20 + + mailbox = hgrnic_alloc_mailbox(dev, GFP_KERNEL); + if (IS_ERR(mailbox)) + return PTR_ERR(mailbox); + inbox = mailbox->buf; + + memset(inbox, 0, INIT_IB_IN_SIZE); + + flags = 0; + flags |= param->set_guid0 ? INIT_IB_FLAG_G0 : 0; + flags |= param->set_node_guid ? INIT_IB_FLAG_NG : 0; + flags |= param->set_si_guid ? INIT_IB_FLAG_SIG : 0; + flags |= param->vl_cap << INIT_IB_VL_SHIFT; + flags |= param->port_width << INIT_IB_PORT_WIDTH_SHIFT; + flags |= param->mtu_cap << INIT_IB_MTU_SHIFT; + HGRNIC_PUT(inbox, flags, INIT_IB_FLAGS_OFFSET); + + HGRNIC_PUT(inbox, param->gid_cap, INIT_IB_MAX_GID_OFFSET); + HGRNIC_PUT(inbox, param->pkey_cap, INIT_IB_MAX_PKEY_OFFSET); + HGRNIC_PUT(inbox, param->guid0, INIT_IB_GUID0_OFFSET); + HGRNIC_PUT(inbox, param->node_guid, INIT_IB_NODE_GUID_OFFSET); + HGRNIC_PUT(inbox, param->si_guid, INIT_IB_SI_GUID_OFFSET); + + err = hgrnic_cmd(dev, mailbox->dma, port, 0, CMD_INIT_IB, + CMD_TIME_CLASS_A); + + hgrnic_free_mailbox(dev, mailbox); + return err; +} + +/** + * @description: + * Command function. + * Cancel IB network related information (GID, GUID, etc). + * !TODO: We haven't implemented this command yet + */ +int hgrnic_CLOSE_IB (struct hgrnic_dev *dev, int port) { + return hgrnic_cmd(dev, 0, port, 0, CMD_CLOSE_IB, CMD_TIME_CLASS_A); +} + +/** + * @description: + * Command function. + * Cancel IB network related information (GID, GUID, etc). + * !TODO: We haven't implemented this command yet. + */ +int hgrnic_SET_IB (struct hgrnic_dev *dev, struct hgrnic_set_ib_param *param, + int port) { + struct hgrnic_mailbox *mailbox; + u32 *inbox; + int err; + u32 flags = 0; + +#define SET_IB_IN_SIZE 0x40 +#define SET_IB_FLAGS_OFFSET 0x00 +#define SET_IB_FLAG_SIG (1 << 18) +#define SET_IB_FLAG_RQK (1 << 0) +#define SET_IB_CAP_MASK_OFFSET 0x04 +#define SET_IB_SI_GUID_OFFSET 0x08 + + mailbox = hgrnic_alloc_mailbox(dev, GFP_KERNEL); + if (IS_ERR(mailbox)) + return PTR_ERR(mailbox); + inbox = mailbox->buf; + + memset(inbox, 0, SET_IB_IN_SIZE); + + flags |= param->set_si_guid ? SET_IB_FLAG_SIG : 0; + flags |= param->reset_qkey_viol ? SET_IB_FLAG_RQK : 0; + HGRNIC_PUT(inbox, flags, SET_IB_FLAGS_OFFSET); + + HGRNIC_PUT(inbox, param->cap_mask, SET_IB_CAP_MASK_OFFSET); + HGRNIC_PUT(inbox, param->si_guid, SET_IB_SI_GUID_OFFSET); + + err = hgrnic_cmd(dev, mailbox->dma, port, 0, CMD_SET_IB, + CMD_TIME_CLASS_B); + + hgrnic_free_mailbox(dev, mailbox); + return err; +} + +/** + * @description: + * Command function. + * Write ICM address translation table to HCA hardware. The command + * accepts at most HGRNIC_MAILBOX_SIZE / 16 chunks, and 256 pages + * per chunk. + */ +int hgrnic_MAP_ICM (struct hgrnic_dev *dev, struct hgrnic_icm *icm, + u8 type_sel, u64 virt) { + struct hgrnic_mailbox *mailbox; + struct hgrnic_icm_iter iter; + __be64 *pages; + int lg; + int nent = 1; /* chunk index: 1, 0, 3, 2, 5, 4, ... */ + int i; + int err = 0; + int ts = 0; /* total size */ + int tc = 0; /* total chunks (total entries write to hardware) */ + +#define MAP_ICM_MAX_PAGE_NUM_LOG 8 + + mailbox = hgrnic_alloc_mailbox(dev, GFP_KERNEL); + if (IS_ERR(mailbox)) + return PTR_ERR(mailbox); + + memset(mailbox->buf, 0, HGRNIC_MAILBOX_SIZE); + pages = mailbox->buf; + + + for (hgrnic_icm_first(icm, &iter); + !hgrnic_icm_last(&iter); + hgrnic_icm_next(&iter)) { + /* + * We have to pass pages that are aligned to their + * size, so find the least significant 1 in the + * address or size and use that as our log2 size. + */ + lg = ffs(hgrnic_icm_addr(&iter) | hgrnic_icm_size(&iter)) - 1; + if (lg < HGRNIC_ICM_PAGE_SHIFT) { + hgrnic_warn(dev, "Got FW area not aligned to %d (%llx/%lx).\n", + HGRNIC_ICM_PAGE_SIZE, + (unsigned long long) hgrnic_icm_addr(&iter), + hgrnic_icm_size(&iter)); + err = -EINVAL; + goto out; + } + + if (lg > MAP_ICM_MAX_PAGE_NUM_LOG + HGRNIC_ICM_PAGE_SHIFT) { + lg = MAP_ICM_MAX_PAGE_NUM_LOG + HGRNIC_ICM_PAGE_SHIFT; + } + + for (i = 0; i < hgrnic_icm_size(&iter) >> lg; ++i) { + + pages[nent * 2] = cpu_to_be64(virt); + virt += 1ULL << lg; + + pages[nent * 2 + 1] = + cpu_to_be64((hgrnic_icm_addr(&iter) + (i << lg)) | + (1ULL << (lg - HGRNIC_ICM_PAGE_SHIFT))); + ts += 1 << (lg - 10); // Indicate that ts is in KB unit. + ++tc; + + if (nent % 2 == 0) + nent += 3; + else + --nent; + + if (nent >= HGRNIC_MAILBOX_SIZE / 16) { + printk(KERN_INFO PFX "MAP_ICM filled max the mailbox!\n"); + err = hgrnic_cmd(dev, mailbox->dma, (nent - 1), type_sel, CMD_MAP_ICM, + CMD_TIME_CLASS_B); + if (err) + goto out; + nent = 1; + } + } + } + + nent = (nent % 2 == 0) ? nent + 1 : nent - 1; + if (nent) { + for (i = 0; i < nent; ++i) { + printk(KERN_INFO PFX "MAP_ICM: 0x%llx 0x%llx 0x%llx 0x%llx\n", + *(pages + i), *(pages + i + 1), *(pages + i + 2), *(pages + i + 3)); + } + err = hgrnic_cmd(dev, mailbox->dma, nent, type_sel, CMD_MAP_ICM, + CMD_TIME_CLASS_B); + } + + printk(KERN_INFO PFX "Mapped %d chunks/%d KB at %llx for ICM.\n", + tc, ts, (unsigned long long) virt - (ts << 10)); + +out: + hgrnic_free_mailbox(dev, mailbox); + return err; +} + +/** + * @description: + * Command function. + * Write ICM address translation table (one page) to HCA hardware. + */ +int hgrnic_MAP_ICM_page (struct hgrnic_dev *dev, u64 dma_addr, + u8 type_sel, u64 virt) { + struct hgrnic_mailbox *mailbox; + __be64 *inbox; + int err; + + mailbox = hgrnic_alloc_mailbox(dev, GFP_KERNEL); + if (IS_ERR(mailbox)) + return PTR_ERR(mailbox); + inbox = mailbox->buf; + + /* + * When there's odd number of entries, the last entry + * put into the higher address. + */ + inbox[0] = 0; + inbox[1] = 0; + inbox[2] = cpu_to_be64(virt); + inbox[3] = cpu_to_be64(dma_addr | 0x01); + + printk(KERN_INFO PFX "MAP_ICM page inbox: 0x%llx 0x%llx 0x%llx 0x%llx.\n", + *inbox, *(inbox+1), *(inbox+2), *(inbox+3)); + + err = hgrnic_cmd(dev, mailbox->dma, 1, type_sel, CMD_MAP_ICM, + CMD_TIME_CLASS_B); + + hgrnic_free_mailbox(dev, mailbox); + + printk(KERN_INFO PFX "Mapped page at %llx to %llx for ICM.\n", + (unsigned long long) dma_addr, (unsigned long long) virt); + + return err; +} + +/** + * @description: + * Command function. + * Cancel ICM address translation table on HCA hardware. + */ +int hgrnic_UNMAP_ICM (struct hgrnic_dev *dev, u64 virt, + u32 page_count, u8 type_sel) +{ + return hgrnic_cmd(dev, virt, page_count, type_sel, + CMD_UNMAP_ICM, CMD_TIME_CLASS_B); +} + +/** + * @description: + * Command function. + * Send one MPT entry to HCA hardware, using mailbox. + * The parameter format is shown in "struct hgrnic_mpt_entry". + */ +int hgrnic_SW2HW_MPT (struct hgrnic_dev *dev, + struct hgrnic_mailbox *mailbox, int mpt_index) { + return hgrnic_cmd(dev, mailbox->dma, mpt_index, 0, CMD_SW2HW_MPT, + CMD_TIME_CLASS_B); +} + +/** + * @description: + * Command function. + * Cancel one MPT entry from HCA hardware. + */ +int hgrnic_HW2SW_MPT (struct hgrnic_dev *dev, int mpt_index) +{ + return hgrnic_cmd(dev, 0, mpt_index, 0, CMD_HW2SW_MPT, + CMD_TIME_CLASS_B); +} + +/** + * @description: + * Command function. + * Send MTT entries to HCA hardware via the mailbox. + */ +int hgrnic_WRITE_MTT (struct hgrnic_dev *dev, + struct hgrnic_mailbox *mailbox, int num_mtt) +{ + return hgrnic_cmd(dev, mailbox->dma, num_mtt, 0, CMD_WRITE_MTT, + CMD_TIME_CLASS_B); +} + +/** + * @description: + * Command function. + * Send EQ event type flags to HCA hardware. + */ +int hgrnic_MAP_EQ (struct hgrnic_dev *dev, u64 event_mask, + int unmap, int eq_num) { + + printk(KERN_INFO PFX "%s mask %016llx for eqn %d\n", + unmap ? "Clearing" : "Setting", + (unsigned long long) event_mask, eq_num); + + return hgrnic_cmd(dev, event_mask, (unmap << 31) | eq_num, + 0, CMD_MAP_EQ, CMD_TIME_CLASS_B); +} + +/** + * @description: + * Command function. + * Send EQ context to HCA hardware. + * The parameter format is shown in "struct hgrnic_eq_context". + * Note that this command would not be called in this version of code. + */ +int hgrnic_SW2HW_EQ (struct hgrnic_dev *dev, + struct hgrnic_mailbox *mailbox, int eq_num) { + return hgrnic_cmd(dev, mailbox->dma, eq_num, 0, CMD_SW2HW_EQ, + CMD_TIME_CLASS_A); +} + +/** + * @description: + * Command function. + * Cancel EQ context in HCA hardware. + */ +int hgrnic_HW2SW_EQ (struct hgrnic_dev *dev, int eq_num) { + + return hgrnic_cmd(dev, 0, eq_num, 0, CMD_HW2SW_EQ, + CMD_TIME_CLASS_A); +} + +/** + * @description: + * Command function. + * Send CQ context to HCA hardware. + * !FIXME: parameter format should also be included in + * the command. + */ +int hgrnic_SW2HW_CQ (struct hgrnic_dev *dev, + struct hgrnic_mailbox *mailbox, int cq_num) +{ + return hgrnic_cmd(dev, mailbox->dma, cq_num, 0, CMD_SW2HW_CQ, + CMD_TIME_CLASS_A); +} + +/** + * @description: + * Command function. + * Cancel CQ context in HCA hardware. + */ +int hgrnic_HW2SW_CQ (struct hgrnic_dev *dev, int cq_num) +{ + return hgrnic_cmd(dev, 0, cq_num, 0, CMD_HW2SW_CQ, + CMD_TIME_CLASS_A); +} + +/** + * @description: + * Command function. + * Modify CQ queue length (in CQ context) in HCA hardware. + */ +int hgrnic_RESIZE_CQ (struct hgrnic_dev *dev, int cq_num, + u32 lkey, u8 log_size) +{ + struct hgrnic_mailbox *mailbox; + __be32 *inbox; + int err; + +#define RESIZE_CQ_IN_SIZE 0x20 +#define RESIZE_CQ_LOG_SIZE_OFFSET 0x00 +#define RESIZE_CQ_LKEY_OFFSET 0x04 + + mailbox = hgrnic_alloc_mailbox(dev, GFP_KERNEL); + if (IS_ERR(mailbox)) + return PTR_ERR(mailbox); + inbox = mailbox->buf; + + memset(inbox, 0, RESIZE_CQ_IN_SIZE); + /* + * Leave start address fields zeroed out -- hgrnic assumes that + * MRs for CQs always start at virtual address 0. + */ + HGRNIC_PUT(inbox, log_size, RESIZE_CQ_LOG_SIZE_OFFSET); + HGRNIC_PUT(inbox, lkey, RESIZE_CQ_LKEY_OFFSET); + + err = hgrnic_cmd(dev, mailbox->dma, cq_num, 1, CMD_RESIZE_CQ, + CMD_TIME_CLASS_B); + + hgrnic_free_mailbox(dev, mailbox); + return err; +} + +/** + * @description: + * Command function. + * Send QP context to HCA hardware. + * We don't use op_mod == 3, + * because hardware don't support it. + */ +int hgrnic_MODIFY_QP (struct hgrnic_dev *dev, enum ib_qp_state cur, + enum ib_qp_state next, u32 num, struct hgrnic_mailbox *mailbox) +{ + /* op[cur][next] */ + static const u16 op[IB_QPS_ERR + 1][IB_QPS_ERR + 1] = { + [IB_QPS_RESET] = { + [IB_QPS_RESET] = CMD_ERR2RST_QPEE, + [IB_QPS_ERR] = CMD_2ERR_QPEE, + [IB_QPS_INIT] = CMD_RST2INIT_QPEE, + }, + [IB_QPS_INIT] = { + [IB_QPS_RESET] = CMD_ERR2RST_QPEE, + [IB_QPS_ERR] = CMD_2ERR_QPEE, + [IB_QPS_INIT] = CMD_INIT2INIT_QPEE, + [IB_QPS_RTR] = CMD_INIT2RTR_QPEE, + }, + [IB_QPS_RTR] = { + [IB_QPS_RESET] = CMD_ERR2RST_QPEE, + [IB_QPS_ERR] = CMD_2ERR_QPEE, + [IB_QPS_RTS] = CMD_RTR2RTS_QPEE, + }, + [IB_QPS_RTS] = { + [IB_QPS_RESET] = CMD_ERR2RST_QPEE, + [IB_QPS_ERR] = CMD_2ERR_QPEE, + [IB_QPS_RTS] = CMD_RTS2RTS_QPEE, + [IB_QPS_SQD] = CMD_RTS2SQD_QPEE, + }, + [IB_QPS_SQD] = { + [IB_QPS_RESET] = CMD_ERR2RST_QPEE, + [IB_QPS_ERR] = CMD_2ERR_QPEE, + [IB_QPS_RTS] = CMD_SQD2RTS_QPEE, + [IB_QPS_SQD] = CMD_SQD2SQD_QPEE, + }, + [IB_QPS_SQE] = { + [IB_QPS_RESET] = CMD_ERR2RST_QPEE, + [IB_QPS_ERR] = CMD_2ERR_QPEE, + [IB_QPS_RTS] = CMD_SQERR2RTS_QPEE, + }, + [IB_QPS_ERR] = { + [IB_QPS_RESET] = CMD_ERR2RST_QPEE, + [IB_QPS_ERR] = CMD_2ERR_QPEE, + } + }; + + u8 op_mod = 0; + int err; + + err = hgrnic_cmd(dev, mailbox->dma, num, + op_mod, op[cur][next], CMD_TIME_CLASS_C); + return err; +} + +/** + * @description: + * Command function. + * Query QP context from HCA hardware. + */ +int hgrnic_QUERY_QP (struct hgrnic_dev *dev, u32 num, + struct hgrnic_mailbox *mailbox) +{ + return hgrnic_cmd_box(dev, 0, mailbox->dma, num, 0, + CMD_QUERY_QPEE, CMD_TIME_CLASS_A); +} + +/** + * @description: + * Command function. + * Configure special QP (QP0, QP1) context to HCA hardware. + * !TODO: We haven't implemented this command yet. + */ +int hgrnic_CONF_SPECIAL_QP (struct hgrnic_dev *dev, int type, u32 qpn) { + u8 op_mod; + + switch (type) { + case IB_QPT_SMI: + op_mod = 0; + break; + case IB_QPT_GSI: + op_mod = 1; + break; + case IB_QPT_RAW_IPV6: + op_mod = 2; + break; + case IB_QPT_RAW_ETHERTYPE: + op_mod = 3; + break; + default: + return -EINVAL; + } + + return hgrnic_cmd(dev, 0, qpn, op_mod, CMD_CONF_SPECIAL_QP, + CMD_TIME_CLASS_B); +} + +/** + * @description: + * Command function. + * Post MAD packet to HCA hardware, and receive MAD packet accordingly. + * !TODO: We haven't implemented this command yet. + */ +int hgrnic_MAD_IFC (struct hgrnic_dev *dev, int ignore_mkey, int ignore_bkey, + int port, const struct ib_wc *in_wc, const struct ib_grh *in_grh, + const void *in_mad, void *response_mad) { + + struct hgrnic_mailbox *inmailbox, *outmailbox; + void *inbox; + int err; + u32 in_modifier = port; + u8 op_modifier = 0; + +#define MAD_IFC_BOX_SIZE 0x400 +#define MAD_IFC_MY_QPN_OFFSET 0x100 +#define MAD_IFC_RQPN_OFFSET 0x108 +#define MAD_IFC_SL_OFFSET 0x10c +#define MAD_IFC_G_PATH_OFFSET 0x10d +#define MAD_IFC_RLID_OFFSET 0x10e +#define MAD_IFC_PKEY_OFFSET 0x112 +#define MAD_IFC_GRH_OFFSET 0x140 + + inmailbox = hgrnic_alloc_mailbox(dev, GFP_KERNEL); + if (IS_ERR(inmailbox)) + return PTR_ERR(inmailbox); + inbox = inmailbox->buf; + + outmailbox = hgrnic_alloc_mailbox(dev, GFP_KERNEL); + if (IS_ERR(outmailbox)) { + hgrnic_free_mailbox(dev, inmailbox); + return PTR_ERR(outmailbox); + } + + memcpy(inbox, in_mad, 256); + + /* + * Key check traps can't be generated unless we have in_wc to + * tell us where to send the trap. + */ + if (ignore_mkey || !in_wc) + op_modifier |= 0x1; + if (ignore_bkey || !in_wc) + op_modifier |= 0x2; + + if (in_wc) { + u8 val; + + memset(inbox + 256, 0, 256); + + HGRNIC_PUT(inbox, in_wc->qp->qp_num, MAD_IFC_MY_QPN_OFFSET); + HGRNIC_PUT(inbox, in_wc->src_qp, MAD_IFC_RQPN_OFFSET); + + val = in_wc->sl << 4; + HGRNIC_PUT(inbox, val, MAD_IFC_SL_OFFSET); + + val = in_wc->dlid_path_bits | + (in_wc->wc_flags & IB_WC_GRH ? 0x80 : 0); + HGRNIC_PUT(inbox, val, MAD_IFC_G_PATH_OFFSET); + + HGRNIC_PUT(inbox, ib_lid_cpu16(in_wc->slid), MAD_IFC_RLID_OFFSET); + HGRNIC_PUT(inbox, in_wc->pkey_index, MAD_IFC_PKEY_OFFSET); + + if (in_grh) + memcpy(inbox + MAD_IFC_GRH_OFFSET, in_grh, 40); + + op_modifier |= 0x4; + + in_modifier |= ib_lid_cpu16(in_wc->slid) << 16; + } + + err = hgrnic_cmd_box(dev, inmailbox->dma, outmailbox->dma, + in_modifier, op_modifier, + CMD_MAD_IFC, CMD_TIME_CLASS_C); + + if (!err) + memcpy(response_mad, outmailbox->buf, 256); + + hgrnic_free_mailbox(dev, inmailbox); + hgrnic_free_mailbox(dev, outmailbox); + return err; +} + +/** + * @description: + * Command function. + * This is a test command which does nothing. + * !TODO: We haven't implemented this command yet. + * Next, we may test interrupt of HCA hardware. + */ +int hgrnic_NOP (struct hgrnic_dev *dev) { + return hgrnic_cmd(dev, 0, 0x1f, 0, CMD_NOP, msecs_to_jiffies(100)); +} diff --git a/ETH-PLUS_Jingzhao/JingZhao2/software/drivers/ib_hgrnic/hgrnic_cmd.h b/ETH-PLUS_Jingzhao/JingZhao2/software/drivers/ib_hgrnic/hgrnic_cmd.h new file mode 100644 index 0000000000000000000000000000000000000000..06ba7bc201c8bd2587fea0a4b611a5d6de99fe33 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/software/drivers/ib_hgrnic/hgrnic_cmd.h @@ -0,0 +1,216 @@ +/************************************************************** + * @author Kang Ning, NCIC, ICT, CAS + * @date 2021.09.08 + * @file hgrnic_cmd.h + * @note Command for low-level driver to interact with HCA hardware. + *************************************************************/ + +#ifndef __HGRNIC_CMD_H__ +#define __HGRNIC_CMD_H__ + +#include +#include "hgrnic_dev.h" +#include "hgrnic_iface.h" + +#define HGRNIC_MAILBOX_SIZE 4096 + +enum { + /* command completed successfully: */ + HGRNIC_CMD_STAT_OK = 0x00, + /* Internal error (such as a bus error) occurred while processing command: */ + HGRNIC_CMD_STAT_INTERNAL_ERR = 0x01, + /* Operation/command not supported or opcode modifier not supported: */ + HGRNIC_CMD_STAT_BAD_OP = 0x02, + /* Parameter not supported or parameter out of range: */ + HGRNIC_CMD_STAT_BAD_PARAM = 0x03, + /* System not enabled or bad system state: */ + HGRNIC_CMD_STAT_BAD_SYS_STATE = 0x04, + /* Attempt to access reserved or unallocaterd resource: */ + HGRNIC_CMD_STAT_BAD_RESOURCE = 0x05, + /* Requested resource is currently executing a command, or is otherwise busy: */ + HGRNIC_CMD_STAT_RESOURCE_BUSY = 0x06, + /* memory error: */ + HGRNIC_CMD_STAT_DDR_MEM_ERR = 0x07, + /* Required capability exceeds device limits: */ + HGRNIC_CMD_STAT_EXCEED_LIM = 0x08, + /* Resource is not in the appropriate state or ownership: */ + HGRNIC_CMD_STAT_BAD_RES_STATE = 0x09, + /* Index out of range: */ + HGRNIC_CMD_STAT_BAD_INDEX = 0x0a, + /* FW image corrupted: */ + HGRNIC_CMD_STAT_BAD_NVMEM = 0x0b, + /* Attempt to modify a QP/EE which is not in the presumed state: */ + HGRNIC_CMD_STAT_BAD_QPEE_STATE = 0x10, + /* Bad segment parameters (Address/Size): */ + HGRNIC_CMD_STAT_BAD_SEG_PARAM = 0x20, + /* Memory Region has Memory Windows bound to: */ + HGRNIC_CMD_STAT_REG_BOUND = 0x21, + /* HCA local attached memory not present: */ + HGRNIC_CMD_STAT_LAM_NOT_PRE = 0x22, + /* Bad management packet (silently discarded): */ + HGRNIC_CMD_STAT_BAD_PKT = 0x30, + /* More outstanding CQEs in CQ than new CQ size: */ + HGRNIC_CMD_STAT_BAD_SIZE = 0x40 +}; + +enum { + CXT_REGION = 1, + TPT_REGION, +}; + +enum { + DEV_LIM_FLAG_RC = 1 << 0, + DEV_LIM_FLAG_UC = 1 << 1, + DEV_LIM_FLAG_UD = 1 << 2, + DEV_LIM_FLAG_RD = 1 << 3, + DEV_LIM_FLAG_RAW_IPV6 = 1 << 4, + DEV_LIM_FLAG_RAW_ETHER = 1 << 5, + DEV_LIM_FLAG_SRQ = 1 << 6, + DEV_LIM_FLAG_IPOIB_CSUM = 1 << 7, + DEV_LIM_FLAG_BAD_PKEY_CNTR = 1 << 8, + DEV_LIM_FLAG_BAD_QKEY_CNTR = 1 << 9, + DEV_LIM_FLAG_MW = 1 << 16, + DEV_LIM_FLAG_AUTO_PATH_MIG = 1 << 17, + DEV_LIM_FLAG_ATOMIC = 1 << 18, + DEV_LIM_FLAG_RAW_MULTI = 1 << 19, + DEV_LIM_FLAG_UD_AV_PORT_ENFORCE = 1 << 20, + DEV_LIM_FLAG_UD_MULTI = 1 << 21, +}; + +struct hgrnic_mailbox { + dma_addr_t dma; + void *buf; +}; + +struct hgrnic_dev_lim { + int reserved_qps; + int reserved_cqs; + int reserved_eqs; + int reserved_mtts; + int reserved_pds; + u32 reserved_lkey; + + int max_qp_sz; // Supported max number of WQEs in SQ (or RQ) + int max_cq_sz; // Supported max number of CQEs in a CQ + + int max_qps; + int max_cqs; + int max_eqs; + int max_mpts; + int max_pds; + int max_gids; + int max_pkeys; + + int max_mtt_seg; + + // size for every entry + int qpc_entry_sz; + int cqc_entry_sz; + int eqc_entry_sz; + int mpt_entry_sz; + + int local_ca_ack_delay; + int max_mtu; + int max_port_width; + int max_vl; + int num_ports; + + int min_page_sz; + + int max_sg; + int max_desc_sz; + + u64 max_icm_sz; // in byte +}; + + +struct hgrnic_init_hca_param { + u8 log_num_qps; + u8 log_num_cqs; + u8 log_num_eqs; + u8 log_mpt_sz; + + u64 qpc_base; + u64 cqc_base; + u64 eqc_base; + u64 mpt_base; + u64 mtt_base; +}; + +struct hgrnic_init_ib_param { + int port_width; + int vl_cap; + int mtu_cap; + u16 gid_cap; + u16 pkey_cap; + int set_guid0; + u64 guid0; + int set_node_guid; + u64 node_guid; + int set_si_guid; + u64 si_guid; +}; + +struct hgrnic_set_ib_param { + int set_si_guid; + int reset_qkey_viol; + u64 si_guid ; + u32 cap_mask; +}; + +struct hgrnic_icm; + +int hgrnic_cmd_init(struct hgrnic_dev *dev); +void hgrnic_cmd_cleanup(struct hgrnic_dev *dev); + +struct hgrnic_mailbox *hgrnic_alloc_mailbox(struct hgrnic_dev *dev, + gfp_t gfp_mask); +void hgrnic_free_mailbox(struct hgrnic_dev *dev, struct hgrnic_mailbox *mailbox); + + +int hgrnic_QUERY_DEV_LIM (struct hgrnic_dev *dev, struct hgrnic_dev_lim *dev_lim); +int hgrnic_QUERY_ADAPTER (struct hgrnic_dev *dev, u64 *board_id); + +int hgrnic_INIT_HCA (struct hgrnic_dev *dev, struct hgrnic_init_hca_param *param); +int hgrnic_CLOSE_HCA (struct hgrnic_dev *dev); + +int hgrnic_INIT_IB(struct hgrnic_dev *dev, struct hgrnic_init_ib_param *param, + int port); +int hgrnic_CLOSE_IB(struct hgrnic_dev *dev, int port); +int hgrnic_SET_IB(struct hgrnic_dev *dev, struct hgrnic_set_ib_param *param, + int port); + +int hgrnic_MAP_ICM (struct hgrnic_dev *dev, struct hgrnic_icm *icm, + u8 type_sel, u64 virt); +int hgrnic_MAP_ICM_page (struct hgrnic_dev *dev, u64 dma_addr, + u8 type_sel, u64 virt); +int hgrnic_UNMAP_ICM (struct hgrnic_dev *dev, + u64 virt, u32 page_count, u8 type_sel); + +int hgrnic_SW2HW_MPT (struct hgrnic_dev *dev, + struct hgrnic_mailbox *mailbox, int mpt_index); +int hgrnic_HW2SW_MPT (struct hgrnic_dev *dev, int mpt_index); +int hgrnic_WRITE_MTT (struct hgrnic_dev *dev, struct hgrnic_mailbox *mailbox, + int num_mtt); + +int hgrnic_MAP_EQ (struct hgrnic_dev *dev, u64 event_mask, int unmap, + int eq_num); +int hgrnic_SW2HW_EQ (struct hgrnic_dev *dev, struct hgrnic_mailbox *mailbox, + int eq_num); +int hgrnic_HW2SW_EQ (struct hgrnic_dev *dev, int eq_num); + +int hgrnic_SW2HW_CQ (struct hgrnic_dev *dev, struct hgrnic_mailbox *mailbox, + int cq_num); +int hgrnic_HW2SW_CQ (struct hgrnic_dev *dev, int cq_num); +int hgrnic_RESIZE_CQ (struct hgrnic_dev *dev, int cq_num, u32 lkey, u8 log_size); +int hgrnic_MODIFY_QP (struct hgrnic_dev *dev, enum ib_qp_state cur, + enum ib_qp_state next, u32 num, struct hgrnic_mailbox *mailbox); +int hgrnic_QUERY_QP (struct hgrnic_dev *dev, u32 num, + struct hgrnic_mailbox *mailbox); +int hgrnic_CONF_SPECIAL_QP (struct hgrnic_dev *dev, int type, u32 qpn); +int hgrnic_MAD_IFC (struct hgrnic_dev *dev, int ignore_mkey, int ignore_bkey, + int port, const struct ib_wc *in_wc, const struct ib_grh *in_grh, + const void *in_mad, void *response_mad); +int hgrnic_NOP (struct hgrnic_dev *dev); + +#endif /* __HGRNIC_CMD_H__ */ diff --git a/ETH-PLUS_Jingzhao/JingZhao2/software/drivers/ib_hgrnic/hgrnic_cq.c b/ETH-PLUS_Jingzhao/JingZhao2/software/drivers/ib_hgrnic/hgrnic_cq.c new file mode 100644 index 0000000000000000000000000000000000000000..6c13696e61f4c5e37e75b9bc395893145817008f --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/software/drivers/ib_hgrnic/hgrnic_cq.c @@ -0,0 +1,706 @@ +/************************************************************** + * @author Kang Ning, NCIC, ICT, CAS + * @date 2021.09.08 + * @file hgrnic_cq.c + * @note Data structs & functions related to CQ + *************************************************************/ + +#include +#include +#include + +#include + +#include + +#include "hgrnic_dev.h" +#include "hgrnic_cmd.h" +#include "hgrnic_icm.h" + +enum { + HGRNIC_ATOMIC_BYTE_LEN = 8 +}; + +/* + * Must be packed because start is 64 bits but only aligned to 32 bits. + */ +struct hgrnic_cq_context { + __be32 flags; + __be64 start; + __be32 logsize_usrpage; /* | 8-bit | 24-bit | */ + __be32 comp_eqn; + __be32 pd; + __be32 lkey; + __be32 reserved0[4]; + __be32 cqn; + __be32 reserved1[4]; +} __packed; + +#define HGRNIC_CQ_STATUS_OK ( 0 << 28) +#define HGRNIC_CQ_STATUS_OVERFLOW ( 9 << 28) +#define HGRNIC_CQ_STATUS_WRITE_FAIL (10 << 28) +#define HGRNIC_CQ_FLAG_TR ( 1 << 18) +#define HGRNIC_CQ_FLAG_OI ( 1 << 17) +#define HGRNIC_CQ_STATE_DISARMED ( 0 << 8) +#define HGRNIC_CQ_STATE_ARMED ( 1 << 8) +#define HGRNIC_CQ_STATE_ARMED_SOL ( 4 << 8) +#define HGRNIC_EQ_STATE_FIRED (10 << 8) + + +enum { + SYNDROME_LOCAL_LENGTH_ERR = 0x01, + SYNDROME_LOCAL_QP_OP_ERR = 0x02, + SYNDROME_LOCAL_EEC_OP_ERR = 0x03, + SYNDROME_LOCAL_PROT_ERR = 0x04, + SYNDROME_WR_FLUSH_ERR = 0x05, + SYNDROME_MW_BIND_ERR = 0x06, + SYNDROME_BAD_RESP_ERR = 0x10, + SYNDROME_LOCAL_ACCESS_ERR = 0x11, + SYNDROME_REMOTE_INVAL_REQ_ERR = 0x12, + SYNDROME_REMOTE_ACCESS_ERR = 0x13, + SYNDROME_REMOTE_OP_ERR = 0x14, + SYNDROME_RETRY_EXC_ERR = 0x15, + SYNDROME_RNR_RETRY_EXC_ERR = 0x16, + SYNDROME_LOCAL_RDD_VIOL_ERR = 0x20, + SYNDROME_REMOTE_INVAL_RD_REQ_ERR = 0x21, + SYNDROME_REMOTE_ABORTED_ERR = 0x22, + SYNDROME_INVAL_EECN_ERR = 0x23, + SYNDROME_INVAL_EEC_STATE_ERR = 0x24 +}; + +struct hgrnic_cqe { + __le32 my_qpn; + __le32 my_ee; + __le32 rqpn; + u8 sl_ipok; + u8 g_mlpath; + __le16 rlid; + __le32 imm; + __le32 byte_cnt; + __le32 wqe; /* wqe offset in WQ */ + u8 opcode; + u8 is_send; + u8 reserved; + u8 owner; +}; + +struct hgrnic_err_cqe { + __le32 my_qpn; + u32 reserved1[3]; + u8 syndrome; + u8 vendor_err; + __le16 db_cnt; + u32 reserved2; + __le32 wqe; + u8 opcode; + u8 reserved3[2]; + u8 owner; +}; + +#define HGRNIC_CQ_ENTRY_OWNER_SW (0 << 7) +#define HGRNIC_CQ_ENTRY_OWNER_HW (1 << 7) + +#define HGRNIC_TAVOR_CQ_DB_INC_CI (1 << 24) +#define HGRNIC_TAVOR_CQ_DB_REQ_NOT (2 << 24) +#define HGRNIC_TAVOR_CQ_DB_REQ_NOT_SOL (3 << 24) +#define HGRNIC_TAVOR_CQ_DB_SET_CI (4 << 24) +#define HGRNIC_TAVOR_CQ_DB_REQ_NOT_MULT (5 << 24) + +#define HGRNIC_ARBEL_CQ_DB_REQ_NOT_SOL (1 << 24) +#define HGRNIC_ARBEL_CQ_DB_REQ_NOT (2 << 24) +#define HGRNIC_ARBEL_CQ_DB_REQ_NOT_MULT (3 << 24) + +static inline struct hgrnic_cqe *get_cqe_from_buf(struct hgrnic_cq_buf *buf, + int entry) +{ + if (buf->is_direct) + return buf->queue.direct.buf + (entry * sizeof(struct hgrnic_cqe)); + else + return buf->queue.page_list[entry * sizeof(struct hgrnic_cqe) / PAGE_SIZE].buf + + (entry * sizeof(struct hgrnic_cqe)) % PAGE_SIZE; +} + +static inline struct hgrnic_cqe *get_cqe(struct hgrnic_cq *cq, int entry) +{ + return get_cqe_from_buf(&cq->buf, entry); +} + +static inline struct hgrnic_cqe *cqe_sw(struct hgrnic_cqe *cqe) +{ + return HGRNIC_CQ_ENTRY_OWNER_HW & cqe->owner ? NULL : cqe; +} + +static inline struct hgrnic_cqe *next_cqe_sw(struct hgrnic_cq *cq) +{ + return cqe_sw(get_cqe(cq, cq->cons_index & cq->ibcq.cqe)); +} + +static inline void set_cqe_hw(struct hgrnic_cqe *cqe) +{ + cqe->owner = HGRNIC_CQ_ENTRY_OWNER_HW; +} + +static inline void dump_cqe(struct hgrnic_dev *dev, void *cqe_ptr) +{ + __le32 *cqe = cqe_ptr; + + (void) cqe; /* avoid warning if hgrnic_dbg compiled away... */ + hgrnic_dbg(dev, "CQE contents %08x %08x %08x %08x %08x %08x %08x %08x\n", + le32_to_cpu(cqe[0]), le32_to_cpu(cqe[1]), le32_to_cpu(cqe[2]), + le32_to_cpu(cqe[3]), le32_to_cpu(cqe[4]), le32_to_cpu(cqe[5]), + le32_to_cpu(cqe[6]), le32_to_cpu(cqe[7])); +} + +/** + * @param qpn QP need to be cleaned + * @param cq CQ the qp attached to + * Clean qpn from cq. + */ +void hgrnic_cq_clean(struct hgrnic_dev *dev, struct hgrnic_cq *cq, u32 qpn) +{ + struct hgrnic_cqe *cqe; + u32 prod_index; + int i, nfreed = 0; + + spin_lock_irq(&cq->lock); + + /* + * First we need to find the current producer index, so we + * know where to start cleaning from. It doesn't matter if HW + * adds new entries after this loop -- the QP we're worried + * about is already in RESET, so the new entries won't come + * from our QP and therefore don't need to be checked. + */ + for (prod_index = cq->cons_index; + cqe_sw(get_cqe(cq, prod_index & cq->ibcq.cqe)); + ++prod_index) + if (prod_index == cq->cons_index + cq->ibcq.cqe) + break; + + hgrnic_dbg(dev, "Cleaning QPN %06x from CQN %06x; ci %d, pi %d\n", + qpn, cq->cqn, cq->cons_index, prod_index); + + /* + * Now sweep backwards through the CQ, removing CQ entries + * that match our QP by copying older entries on top of them. + */ + while ((int) --prod_index - (int) cq->cons_index >= 0) { + cqe = get_cqe(cq, prod_index & cq->ibcq.cqe); + if (cqe->my_qpn == cpu_to_le32(qpn)) + ++nfreed; + else if (nfreed) + memcpy(get_cqe(cq, (prod_index + nfreed) & cq->ibcq.cqe), + cqe, sizeof(struct hgrnic_cqe)); + } + + if (nfreed) { + for (i = 0; i < nfreed; ++i) + set_cqe_hw(get_cqe(cq, (cq->cons_index + i) & cq->ibcq.cqe)); + wmb(); + cq->cons_index += nfreed; + } + + spin_unlock_irq(&cq->lock); +} + +/** + * + * Migrate CQE to resize buf of same consumer index + */ +void hgrnic_cq_resize_copy_cqes(struct hgrnic_cq *cq) +{ + int i; + + for (i = cq->cons_index; cqe_sw(get_cqe(cq, i & cq->ibcq.cqe)); ++i) + memcpy(get_cqe_from_buf(&cq->resize_buf->buf, + i & cq->resize_buf->cqe), + get_cqe(cq, i & cq->ibcq.cqe), sizeof(struct hgrnic_cqe)); +} + +/** + * @note Allocate buffer for completion Que. + * + * @param buf cq buffer struct + * @param nent type of the resource + */ +int hgrnic_alloc_cq_buf(struct hgrnic_dev *dev, struct hgrnic_cq_buf *buf, + int nent) +{ + int ret; + int i; + + ret = hgrnic_buf_alloc(dev, nent * sizeof(struct hgrnic_cqe), + &buf->queue, &buf->is_direct, + &dev->driver_pd, 1, &buf->mr); + if (ret) + return ret; + + for (i = 0; i < nent; ++i) + set_cqe_hw(get_cqe_from_buf(buf, i)); + + return 0; +} + +void hgrnic_free_cq_buf(struct hgrnic_dev *dev, struct hgrnic_cq_buf *buf, int cqe) +{ + hgrnic_buf_free(dev, (cqe + 1) * sizeof(struct hgrnic_cqe), &buf->queue, + buf->is_direct, &buf->mr); +} + +static void handle_error_cqe(struct hgrnic_dev *dev, struct hgrnic_cq *cq, + struct hgrnic_qp *qp, int wqe_index, int is_send, + struct hgrnic_err_cqe *cqe, + struct ib_wc *entry) +{ + if (cqe->syndrome == SYNDROME_LOCAL_QP_OP_ERR) { + hgrnic_dbg(dev, "local QP operation err " + "(QPN %06x, WQE @ %08x, CQN %06x, consumer index %d)\n", + le32_to_cpu(cqe->my_qpn), le32_to_cpu(cqe->wqe), + cq->cqn, cq->cons_index); + dump_cqe(dev, cqe); + } + + /* + * For completions in error, only work request ID, status + * have to be set. + */ + switch (cqe->syndrome) { + case SYNDROME_LOCAL_LENGTH_ERR: + entry->status = IB_WC_LOC_LEN_ERR; + break; + case SYNDROME_LOCAL_QP_OP_ERR: + entry->status = IB_WC_LOC_QP_OP_ERR; + break; + case SYNDROME_LOCAL_EEC_OP_ERR: + entry->status = IB_WC_LOC_EEC_OP_ERR; + break; + case SYNDROME_LOCAL_PROT_ERR: + entry->status = IB_WC_LOC_PROT_ERR; + break; + case SYNDROME_WR_FLUSH_ERR: + entry->status = IB_WC_WR_FLUSH_ERR; + break; + case SYNDROME_MW_BIND_ERR: + entry->status = IB_WC_MW_BIND_ERR; + break; + case SYNDROME_BAD_RESP_ERR: + entry->status = IB_WC_BAD_RESP_ERR; + break; + case SYNDROME_LOCAL_ACCESS_ERR: + entry->status = IB_WC_LOC_ACCESS_ERR; + break; + case SYNDROME_REMOTE_INVAL_REQ_ERR: + entry->status = IB_WC_REM_INV_REQ_ERR; + break; + case SYNDROME_REMOTE_ACCESS_ERR: + entry->status = IB_WC_REM_ACCESS_ERR; + break; + case SYNDROME_REMOTE_OP_ERR: + entry->status = IB_WC_REM_OP_ERR; + break; + case SYNDROME_RETRY_EXC_ERR: + entry->status = IB_WC_RETRY_EXC_ERR; + break; + case SYNDROME_RNR_RETRY_EXC_ERR: + entry->status = IB_WC_RNR_RETRY_EXC_ERR; + break; + case SYNDROME_LOCAL_RDD_VIOL_ERR: + entry->status = IB_WC_LOC_RDD_VIOL_ERR; + break; + case SYNDROME_REMOTE_INVAL_RD_REQ_ERR: + entry->status = IB_WC_REM_INV_RD_REQ_ERR; + break; + case SYNDROME_REMOTE_ABORTED_ERR: + entry->status = IB_WC_REM_ABORT_ERR; + break; + case SYNDROME_INVAL_EECN_ERR: + entry->status = IB_WC_INV_EECN_ERR; + break; + case SYNDROME_INVAL_EEC_STATE_ERR: + entry->status = IB_WC_INV_EEC_STATE_ERR; + break; + default: + entry->status = IB_WC_GENERAL_ERR; + break; + } + + /* !TODO: unused field */ + entry->vendor_err = cqe->vendor_err; +} + +static inline int hgrnic_poll_one(struct hgrnic_dev *dev, + struct hgrnic_cq *cq, + struct hgrnic_qp **cur_qp, + struct ib_wc *entry) +{ + struct hgrnic_wq *wq; + struct hgrnic_cqe *cqe; + int wqe_index; + int is_error; + int is_send; + int err = 0; + + cqe = next_cqe_sw(cq); + if (!cqe) + return -EAGAIN; + + hgrnic_dbg(dev, "%x/%d: CQE -> QPN %06x, WQE @ %08x\n", + cq->cqn, cq->cons_index, le32_to_cpu(cqe->my_qpn), + le32_to_cpu(cqe->wqe)); + dump_cqe(dev, cqe); + + is_error = (cqe->opcode == HGRNIC_OPCODE_SEND_ERR) || + (cqe->opcode == HGRNIC_OPCODE_RECV_ERR); + is_send = is_error ? (cqe->opcode == HGRNIC_OPCODE_SEND_ERR) + : cqe->is_send; + + if (!*cur_qp || le32_to_cpu(cqe->my_qpn) != (*cur_qp)->qpn) { + /* + * We do not have to take the QP table lock here, + * because CQs will be locked while QPs are removed + * from the table. + */ + *cur_qp = hgrnic_array_get(&dev->qp_table.qp, + le32_to_cpu(cqe->my_qpn) & + (dev->limits.num_qps - 1)); + if (!*cur_qp) { + hgrnic_warn(dev, "CQ entry for unknown QP %06x\n", + le32_to_cpu(cqe->my_qpn) & 0xffffff); + err = -EINVAL; + goto out; + } + } + + entry->qp = &(*cur_qp)->ibqp; + + if (is_send) { + wq = &(*cur_qp)->sq; + wqe_index = le32_to_cpu(cqe->wqe) >> wq->entry_sz_log; + entry->wr_id = (*cur_qp)->sq.wr_id[wqe_index]; + } else { + wq = &(*cur_qp)->rq; + wqe_index = le32_to_cpu(cqe->wqe) >> wq->entry_sz_log; + entry->wr_id = (*cur_qp)->sq.wr_id[wqe_index]; + } + + if (wq) { + /* last_cpl is inited with max-1, + * so we don't have to consider the + * start case. */ + if (wq->last_cpl < wqe_index) + wq->tail += wqe_index - wq->last_cpl; + else + wq->tail += wqe_index + wq->max - wq->last_cpl; + + wq->last_cpl = wqe_index; + } + + if (is_error) { + handle_error_cqe(dev, cq, *cur_qp, wqe_index, is_send, + (struct hgrnic_err_cqe *) cqe, + entry); + goto out; + } + + if (is_send) { + entry->wc_flags = 0; + switch (cqe->opcode) { + case HGRNIC_OPCODE_RDMA_WRITE: + entry->opcode = IB_WC_RDMA_WRITE; + break; + case HGRNIC_OPCODE_RDMA_WRITE_IMM: + entry->opcode = IB_WC_RDMA_WRITE; + entry->wc_flags |= IB_WC_WITH_IMM; + break; + case HGRNIC_OPCODE_SEND: + entry->opcode = IB_WC_SEND; + break; + case HGRNIC_OPCODE_SEND_IMM: + entry->opcode = IB_WC_SEND; + entry->wc_flags |= IB_WC_WITH_IMM; + break; + case HGRNIC_OPCODE_RDMA_READ: + entry->opcode = IB_WC_RDMA_READ; + entry->byte_len = le32_to_cpu(cqe->byte_cnt); + break; + case HGRNIC_OPCODE_ATOMIC_CS: + entry->opcode = IB_WC_COMP_SWAP; + entry->byte_len = HGRNIC_ATOMIC_BYTE_LEN; + break; + case HGRNIC_OPCODE_ATOMIC_FA: + entry->opcode = IB_WC_FETCH_ADD; + entry->byte_len = HGRNIC_ATOMIC_BYTE_LEN; + break; + default: + entry->opcode = HGRNIC_OPCODE_NOP; + break; + } + } else { + entry->byte_len = le32_to_cpu(cqe->byte_cnt); + switch (cqe->opcode & 0x1f) { + case IB_OPCODE_SEND_LAST_WITH_IMMEDIATE: + case IB_OPCODE_SEND_ONLY_WITH_IMMEDIATE: + entry->wc_flags = IB_WC_WITH_IMM; + entry->ex.imm_data = cqe->imm; + entry->opcode = IB_WC_RECV; + break; + case IB_OPCODE_RDMA_WRITE_LAST_WITH_IMMEDIATE: + case IB_OPCODE_RDMA_WRITE_ONLY_WITH_IMMEDIATE: + entry->wc_flags = IB_WC_WITH_IMM; + entry->ex.imm_data = cqe->imm; + entry->opcode = IB_WC_RECV_RDMA_WITH_IMM; + break; + default: + entry->wc_flags = 0; + entry->opcode = IB_WC_RECV; + break; + } + entry->slid = le16_to_cpu(cqe->rlid); + entry->src_qp = le32_to_cpu(cqe->rqpn) & 0xffffff; + + entry->sl = 0; /* This is not used */ + entry->dlid_path_bits = 0; /* This is not used */ + entry->pkey_index = 0; /* This is not used */ + } + + entry->status = IB_WC_SUCCESS; + +out: + set_cqe_hw(cqe); + ++cq->cons_index; + + return err; +} + + +/** + * * ib_poll_cq - poll a CQ for completion(s) + * @cq:the CQ being polled + * @num_entries:maximum number of completions to return + * @wc:array of at least @num_entries &struct ib_wc where completions + * will be returned + * + * If the return value is < 0, an error occurred. + * If the return value is >= 0, it is the number of + * completions returned. If the return value is + * non-negative and < num_entries, then the CQ was + * emptied. + */ +int hgrnic_poll_cq(struct ib_cq *ibcq, int num_entries, + struct ib_wc *entry) +{ + struct hgrnic_dev *dev = to_hgdev(ibcq->device); + struct hgrnic_cq *cq = to_hgcq(ibcq); + struct hgrnic_qp *qp = NULL; + unsigned long flags; + int err = 0; + int npolled; + + spin_lock_irqsave(&cq->lock, flags); + + npolled = 0; +repoll: + while (npolled < num_entries) { + err = hgrnic_poll_one(dev, cq, &qp, + entry + npolled); + if (err) + break; + ++npolled; + } + + /* + * If a CQ resize is in progress and we discovered that the + * old buffer is empty, then peek in the new buffer, and if + * it's not empty, switch to the new buffer and continue + * polling there. + */ + if (unlikely(err == -EAGAIN && cq->resize_buf && + cq->resize_buf->state == CQ_RESIZE_READY)) { + + if (cqe_sw(get_cqe_from_buf(&cq->resize_buf->buf, + cq->cons_index & cq->resize_buf->cqe))) { + struct hgrnic_cq_buf tbuf; + int tcqe; + + tbuf = cq->buf; + tcqe = cq->ibcq.cqe; + cq->buf = cq->resize_buf->buf; + cq->ibcq.cqe = cq->resize_buf->cqe; + + cq->resize_buf->buf = tbuf; + cq->resize_buf->cqe = tcqe; + cq->resize_buf->state = CQ_RESIZE_SWAPPED; + + goto repoll; + } + } + + spin_unlock_irqrestore(&cq->lock, flags); + + return (err == 0 || err == -EAGAIN) ? npolled : err; +} + + +int hgrnic_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags) { + + printk(KERN_INFO PFX "Enter hgrnic_arm_cq! This callback is left empty!\n"); + return 0; +} + +/** + * @description: Allocate cqn and queue(if it is from kernel space) + * @param nent : unmber of cqe supported in the CQ. (may get from userspace driver) + * @param ctx : ctx cq belonged to, is NULL if the caller is from kernel space. + * @param pdn : pd number this cq belonged to. (may get from user space driver) + * @param cq : struct hgrnic_cq allocated for this cq. + */ +int hgrnic_init_cq (struct hgrnic_dev *dev, int nent, + struct hgrnic_ucontext *ctx, u32 pdn, struct hgrnic_cq *cq) +{ + struct hgrnic_mailbox *mailbox; + struct hgrnic_cq_context *cq_context; + int err = -ENOMEM; + + cq->ibcq.cqe = nent - 1; /* cqe is also a mask (pow(2) - 1) */ + cq->is_kernel = !ctx; + + cq->cqn = hgrnic_alloc(&dev->cq_table.alloc); + if (cq->cqn == -1) + return -ENOMEM; + + err = hgrnic_reg_icm(dev, dev->cq_table.table, + cq->cqn, CXT_REGION); + if (err) + goto err_out; + + /* If this is kernel owned CQ, allocated CQ buffer */ + if (cq->is_kernel) { + err = hgrnic_alloc_cq_buf(dev, &cq->buf, nent); + if (err) + goto err_out_icm; + } + + spin_lock_init(&cq->lock); + cq->refcount = 1; + init_waitqueue_head(&cq->wait); + mutex_init(&cq->mutex); + + mailbox = hgrnic_alloc_mailbox(dev, GFP_KERNEL); + if (IS_ERR(mailbox)) + goto err_out_free_mr; + + cq_context = mailbox->buf; + memset(cq_context, 0, sizeof *cq_context); + cq_context->flags = cpu_to_be32(HGRNIC_CQ_STATUS_OK | + HGRNIC_CQ_STATE_DISARMED | + HGRNIC_CQ_FLAG_TR); + cq_context->logsize_usrpage = cpu_to_be32((ffs(nent) - 1) << 24); /* TODO: This logsize needs to be checked */ + cq_context->pd = cpu_to_be32(pdn); + cq_context->lkey = cpu_to_be32(cq->buf.mr.ibmr.lkey); + cq_context->cqn = cpu_to_be32(cq->cqn); + + err = hgrnic_SW2HW_CQ(dev, mailbox, cq->cqn); + if (err) { + hgrnic_warn(dev, "SW2HW_CQ failed (%d)\n", err); + goto err_out_mailbox; + } + hgrnic_dump("0x%x" , be32_to_cpu(cq_context->flags)); + hgrnic_dump("0x%llx", be64_to_cpu(cq_context->start)); + hgrnic_dump("0x%x", be32_to_cpu(cq_context->logsize_usrpage)); + hgrnic_dump("0x%x", be32_to_cpu(cq_context->comp_eqn )); + hgrnic_dump("0x%x", be32_to_cpu(cq_context->pd )); + hgrnic_dump("0x%x", be32_to_cpu(cq_context->lkey )); + hgrnic_dump("0x%x", be32_to_cpu(cq_context->cqn )); + + cq->cons_index = 0; + + hgrnic_free_mailbox(dev, mailbox); + + spin_lock_irq(&dev->cq_table.lock); + if (hgrnic_array_set(&dev->cq_table.cq, + cq->cqn & (dev->limits.num_cqs - 1), + cq)) { + spin_unlock_irq(&dev->cq_table.lock); + goto err_out_free_mr; + } + spin_unlock_irq(&dev->cq_table.lock); + + return 0; + +err_out_mailbox: + hgrnic_free_mailbox(dev, mailbox); + +err_out_free_mr: + if (cq->is_kernel) + hgrnic_free_cq_buf(dev, &cq->buf, cq->ibcq.cqe); + +err_out_icm: + hgrnic_unreg_icm(dev, dev->cq_table.table, cq->cqn, CXT_REGION); + +err_out: + hgrnic_free(&dev->cq_table.alloc, cq->cqn); + + return err; +} + +static inline int get_cq_refcount(struct hgrnic_dev *dev, struct hgrnic_cq *cq) +{ + int c; + + spin_lock_irq(&dev->cq_table.lock); + c = cq->refcount; + spin_unlock_irq(&dev->cq_table.lock); + + return c; +} + +void hgrnic_free_cq(struct hgrnic_dev *dev, + struct hgrnic_cq *cq) +{ + int err; + + err = hgrnic_HW2SW_CQ(dev, cq->cqn); + if (err) + hgrnic_warn(dev, "HW2SW_CQ failed (%d)\n", err); + + + spin_lock_irq(&dev->cq_table.lock); + hgrnic_array_clear(&dev->cq_table.cq, + cq->cqn & (dev->limits.num_cqs - 1)); + --cq->refcount; + spin_unlock_irq(&dev->cq_table.lock); + + wait_event(cq->wait, !get_cq_refcount(dev, cq)); + + if (cq->is_kernel) + hgrnic_free_cq_buf(dev, &cq->buf, cq->ibcq.cqe); + + hgrnic_unreg_icm(dev, dev->cq_table.table, cq->cqn, CXT_REGION); + hgrnic_free(&dev->cq_table.alloc, cq->cqn); +} + +int hgrnic_init_cq_table (struct hgrnic_dev *dev) { + int err; + + spin_lock_init(&dev->cq_table.lock); + + err = hgrnic_alloc_init(&dev->cq_table.alloc, + dev->limits.num_cqs, + (1 << 24) - 1); + if (err) { + return err; + } + + err = hgrnic_array_init(&dev->cq_table.cq, + dev->limits.num_cqs); + if (err) { + hgrnic_alloc_cleanup(&dev->cq_table.alloc); + } + + return err; +} + +void hgrnic_cleanup_cq_table(struct hgrnic_dev *dev) { + hgrnic_array_cleanup(&dev->cq_table.cq, dev->limits.num_cqs); + hgrnic_alloc_cleanup(&dev->cq_table.alloc); +} diff --git a/ETH-PLUS_Jingzhao/JingZhao2/software/drivers/ib_hgrnic/hgrnic_dev.h b/ETH-PLUS_Jingzhao/JingZhao2/software/drivers/ib_hgrnic/hgrnic_dev.h new file mode 100644 index 0000000000000000000000000000000000000000..0f5e453506e778e66039aa282da175b8c67b6b9e --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/software/drivers/ib_hgrnic/hgrnic_dev.h @@ -0,0 +1,420 @@ +/************************************************************** + * @author Kang Ning, NCIC, ICT, CAS + * @date 2021.09.08 + * @file hgrnic_dev.h + * @note Device specific data and useful function + *************************************************************/ + +#ifndef HGRNIC_DEV_H +#define HGRNIC_DEV_H + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "hgrnic_provider.h" +#include "hgrnic_doorbell.h" +#include "hgrnic_iface.h" +#include "hgrnic_icm.h" +#include "hgrnic_en_abi.h" + +#define PCI_VENDOR_ID_ICT 0x10EE +#define PCI_DEVICE_ID_ICT_HANGU_RNIC 0x7028 + +#define HANGU_HCA 0 /* Han GU HCA */ +#define HANGU_RNIC 1 /* HAN GU RNIC */ + + +#define DRV_NAME "ib_hgrnic" +#define PFX DRV_NAME ": " +#define DRV_VERSION "1.0" +#define DRV_RELDATE "April 4, 2021" + +#define HG_GID_SIZE 16 + +#define CONFIG_INFINIBAND_HGRNIC_DEBUG + +#ifdef CONFIG_INFINIBAND_HGRNIC_DEBUG + +#define hgrnic_dbg(mdev, format, arg...) \ + do { \ + dev_printk(KERN_DEBUG, &mdev->pdev->dev, format, ## arg); \ + } while (0) + +#define hgrnic_dump(type, var) printk(KERN_INFO PFX "[%s] " #var ": " type "\n", __FUNCTION__, var) +#define status_dump(var) printk(KERN_INFO PFX "[%s] " var " successful!\n", __FUNCTION__) + +#else /* CONFIG_INFINIBAND_HGRNIC_DEBUG */ + +#define hgrnic_dbg(mdev, format, arg...) do { (void) mdev; } while (0) + +#define hgrnic_dump(type, var) do { ; } while (0) +#define status_dump(type, var) do { ; } while (0) + +#endif /* CONFIG_INFINIBAND_HGRNIC_DEBUG */ + +#define hgrnic_err(mdev, format, arg...) \ + dev_err(&mdev->pdev->dev, format, ## arg) +#define hgrnic_info(mdev, format, arg...) \ + dev_info(&mdev->pdev->dev, format, ## arg) +#define hgrnic_warn(mdev, format, arg...) \ + dev_warn(&mdev->pdev->dev, format, ## arg) + + +enum { + HGRNIC_FLAG_PCIE = 1 << 1 +}; + +enum { + HGRNIC_MAX_PORTS = 1 +}; + + +enum { + HGRNIC_EQ_CONTEXT_SIZE = 0x40, + HGRNIC_CQ_CONTEXT_SIZE = 0x40, + HGRNIC_QP_CONTEXT_SIZE = 0x200, + HGRNIC_RDB_ENTRY_SIZE = 0x20, + HGRNIC_AV_SIZE = 0x20, + HGRNIC_MGM_ENTRY_SIZE = 0x100, + + HGRNIC_MPT_ENTRY_SIZE = 0x40, + HGRNIC_MTT_SEG_SIZE = 0x40 +}; + +enum { + HGRNIC_EQ_CMD, + HGRNIC_EQ_ASYNC, + HGRNIC_EQ_COMP, + HGRNIC_NUM_EQ +}; + +enum { + HGRNIC_OPCODE_NOP = 0x00, + HGRNIC_OPCODE_RDMA_WRITE = 0x08, + HGRNIC_OPCODE_RDMA_WRITE_IMM = 0x09, + HGRNIC_OPCODE_SEND = 0x0a, + HGRNIC_OPCODE_SEND_IMM = 0x0b, + HGRNIC_OPCODE_RDMA_READ = 0x10, + HGRNIC_OPCODE_ATOMIC_CS = 0x11, + HGRNIC_OPCODE_ATOMIC_FA = 0x12, + HGRNIC_OPCODE_BIND_MW = 0x18, + HGRNIC_OPCODE_RECV_ERR = 0xfe, + HGRNIC_OPCODE_SEND_ERR = 0xff, +}; + + +enum { + HGRNIC_CMD_NUM_DBELL_DWORDS = 8 +}; + +struct hgrnic_cmd { + struct dma_pool *pool; + struct mutex hcr_mutex; + struct semaphore poll_sem; + struct semaphore event_sem; + int max_cmds; + spinlock_t context_lock; + int free_head; + // struct hgrnic_cmd_context *context; + u16 token_mask; + // u32 flags; + void __iomem *dbell_map; + u16 dbell_offsets[HGRNIC_CMD_NUM_DBELL_DWORDS]; +}; + +struct hgrnic_limits { + int num_ports; + int vl_cap; + int mtu_cap; + int gid_table_len; + int pkey_table_len; + int local_ca_ack_delay; + int num_uars; + int max_sg; + int num_qps; + int max_wqes; // Supported max number of WQEs in SQ (or RQ) + int max_desc_sz; // Supported maximum descriptor size + int reserved_qps; + int num_cqs; + int max_cqes; /* maximum number of cqe in one CQ */ + int reserved_cqs; + int num_eqs; + int reserved_eqs; + int num_mpts; + int num_mtt_segs; + int mtt_seg_size; // unused now + int reserved_mtts; + int reserved_mrws; + int num_mgms; + int num_amgms; + int reserved_mcgs; + int num_pds; + int reserved_pds; + u32 page_size_cap; + u16 stat_rate_support; + u8 port_width_cap; +}; + +struct hgrnic_alloc { + u32 last; /* last allocated resource. */ + u32 top; /* prefix of resource number */ + u32 max; /* Maximum number of resources. */ + u32 mask; /* Maximum allowed resource number Mask, + * Mask may be bigger than max. */ + spinlock_t lock; + unsigned long *table; /* bitmap table */ +}; + +/* This struct is used to fnd resource + * pointer based on resource ID */ +struct hgrnic_array { + struct { + void **page; + int used; + } *page_list; +}; + +struct hgrnic_uar_table { + struct hgrnic_alloc alloc; +}; + +struct hgrnic_pd_table { + struct hgrnic_alloc alloc; +}; + +struct hgrnic_buddy { + + /** + * We take max_order = 2 as an example: + * Initial state: + * bits[0] : 0 0 0 0 + * bits[1] : 0 0 + * bits[2] : 1 + * When allocate one entry + * bits[0] : (0) 1 0 0 + * bits[1] : 0 1 + * bits[2] : 0 + */ + unsigned long **bits; // bitmap matrix + int *num_free; + int max_order; + spinlock_t lock; +}; + +struct hgrnic_mr_table { + struct hgrnic_alloc mpt_alloc; + struct hgrnic_buddy mtt_buddy; + u64 mtt_base; + u64 mpt_base; + struct hgrnic_icm_table *mtt_table; + struct hgrnic_icm_table *mpt_table; +}; + +struct hgrnic_eq_table { + struct hgrnic_alloc alloc; + void __iomem *clr_int; + u32 clr_mask; + u32 arm_mask; + struct hgrnic_eq eq[HGRNIC_NUM_EQ]; + u64 icm_virt; + struct page *icm_page; + dma_addr_t icm_dma; // bus addr of icm page +}; + +struct hgrnic_cq_table { + struct hgrnic_alloc alloc; /* rescource number allocation */ + spinlock_t lock ; + struct hgrnic_array cq ; + struct hgrnic_icm_table *table; /* ICM space allocation */ +}; + +struct hgrnic_qp_table { + struct hgrnic_alloc alloc; + u32 rdb_base; + int rdb_shift; + int sqp_start; // start qpn of special qp + spinlock_t lock; + struct hgrnic_array qp; // Used to find qp struct based on QPN + struct hgrnic_icm_table *qp_table; +}; + +// defined in hgrnic_main.c +extern struct mutex hgrnic_device_mutex; + + + + +struct hgrnic_dev { + struct ib_device ib_dev; + struct pci_dev *pdev ; + struct hgrnic_endev *endev; + + int hca_type; + unsigned long hgrnic_flags; + + u32 rev_id; + u64 board_id; + + HGRNIC_DECLARE_DOORBELL_LOCK(doorbell_lock) + struct mutex cap_mask_mutex; + + void __iomem *hcr; + void __iomem *kar; + + struct hgrnic_cmd cmd; + struct hgrnic_limits limits; + + struct hgrnic_uar_table uar_table; + struct hgrnic_pd_table pd_table; + struct hgrnic_mr_table mr_table; + struct hgrnic_eq_table eq_table; + struct hgrnic_cq_table cq_table; + struct hgrnic_qp_table qp_table; + + // Resources reserved for driver uses. + struct hgrnic_uar driver_uar; + struct hgrnic_pd driver_pd; + struct hgrnic_mr driver_mr; + + u8 gid[HG_GID_SIZE]; + u8 rate[HGRNIC_MAX_PORTS]; + bool active; +}; + + +extern void __buggy_use_of_HGRNIC_GET(void); +extern void __buggy_use_of_HGRNIC_PUT(void); + +#define HGRNIC_GET(dest, source, offset) \ + do { \ + void *__p = (char *) (source) + (offset); \ + switch (sizeof (dest)) { \ + case 1: (dest) = *(u8 *) __p; break; \ + case 2: (dest) = be16_to_cpup(__p); break; \ + case 4: (dest) = be32_to_cpup(__p); break; \ + case 8: (dest) = be64_to_cpup(__p); break; \ + default: __buggy_use_of_HGRNIC_GET(); \ + } \ + } while (0) + +#define HGRNIC_PUT(dest, source, offset) \ + do { \ + void *__d = ((char *) (dest) + (offset)); \ + switch (sizeof(source)) { \ + case 1: *(u8 *) __d = (source); break; \ + case 2: *(__be16 *) __d = cpu_to_be16(source); break; \ + case 4: *(__be32 *) __d = cpu_to_be32(source); break; \ + case 8: *(__be64 *) __d = cpu_to_be64(source); break; \ + default: __buggy_use_of_HGRNIC_PUT(); \ + } \ + } while (0) + + +u32 hgrnic_alloc(struct hgrnic_alloc *alloc); +void hgrnic_free(struct hgrnic_alloc *alloc, u32 obj); +int hgrnic_alloc_init(struct hgrnic_alloc *alloc, u32 num, u32 mask); +void hgrnic_alloc_cleanup(struct hgrnic_alloc *alloc); +void *hgrnic_array_get(struct hgrnic_array *array, int index); +int hgrnic_array_set(struct hgrnic_array *array, int index, void *value); +void hgrnic_array_clear(struct hgrnic_array *array, int index); +int hgrnic_array_init(struct hgrnic_array *array, int nent); +void hgrnic_array_cleanup(struct hgrnic_array *array, int nent); +int hgrnic_buf_alloc(struct hgrnic_dev *dev, int size, + union hgrnic_buf *buf, int *is_direct, struct hgrnic_pd *pd, + int hca_write, struct hgrnic_mr *mr); +void hgrnic_buf_free(struct hgrnic_dev *dev, int size, union hgrnic_buf *buf, + int is_direct, struct hgrnic_mr *mr); + +int hgrnic_init_uar_table(struct hgrnic_dev *dev); +int hgrnic_init_pd_table(struct hgrnic_dev *dev); +int hgrnic_init_mr_table(struct hgrnic_dev *dev); +int hgrnic_init_cq_table(struct hgrnic_dev *dev); +int hgrnic_init_qp_table(struct hgrnic_dev *dev); +// int hgrnic_init_mcg_table(struct hgrnic_dev *dev); + +void hgrnic_cleanup_uar_table(struct hgrnic_dev *dev); +void hgrnic_cleanup_pd_table(struct hgrnic_dev *dev); +void hgrnic_cleanup_mr_table(struct hgrnic_dev *dev); +void hgrnic_cleanup_cq_table(struct hgrnic_dev *dev); +void hgrnic_cleanup_qp_table(struct hgrnic_dev *dev); +// void hgrnic_cleanup_mcg_table(struct hgrnic_dev *dev); + +int hgrnic_register_device(struct hgrnic_dev *dev); +void hgrnic_unregister_device(struct hgrnic_dev *dev); + +int __hgrnic_restart_one(struct pci_dev *pdev); + +int hgrnic_uar_alloc(struct hgrnic_dev *dev, struct hgrnic_uar *uar); +void hgrnic_uar_free(struct hgrnic_dev *dev, struct hgrnic_uar *uar); + +int hgrnic_pd_alloc(struct hgrnic_dev *dev, int privileged, struct hgrnic_pd *pd); +void hgrnic_pd_free(struct hgrnic_dev *dev, struct hgrnic_pd *pd); + +int hgrnic_write_mtt_size(struct hgrnic_dev *dev); + +struct hgrnic_mtt *hgrnic_alloc_mtt(struct hgrnic_dev *dev, int size); +void hgrnic_free_mtt(struct hgrnic_dev *dev, struct hgrnic_mtt *mtt); +int hgrnic_write_mtt(struct hgrnic_dev *dev, struct hgrnic_mtt *mtt, + int start_index, u64 *buffer_list, int list_len); +struct ib_mr *hgrnic_reg_user_mr(struct ib_pd *pd, u64 start, + u64 length, u64 virt, int acc, struct ib_udata *udata); +int hgrnic_mr_alloc(struct hgrnic_dev *dev, u32 pd, int buffer_size_shift, + u64 iova, u64 total_size, u32 access, struct hgrnic_mr *mr); +int hgrnic_mr_alloc_notrans(struct hgrnic_dev *dev, u32 pd, + u32 access, struct hgrnic_mr *mr); +int hgrnic_mr_alloc_phys(struct hgrnic_dev *dev, u32 pd, + u64 *buffer_list, int buffer_size_shift, + int list_len, u64 iova, u64 total_size, + u32 access, struct hgrnic_mr *mr); +void hgrnic_free_mr(struct hgrnic_dev *dev, struct hgrnic_mr *mr); + +int hgrnic_map_eq_icm(struct hgrnic_dev *dev, u64 icm_virt); +void hgrnic_unmap_eq_icm(struct hgrnic_dev *dev); +int hgrnic_create_cq(struct ib_cq *ibcq, + const struct ib_cq_init_attr *attr, + struct ib_udata *udata); +int hgrnic_poll_cq(struct ib_cq *ibcq, int num_entries, + struct ib_wc *entry); +int hgrnic_arm_cq(struct ib_cq *cq, enum ib_cq_notify_flags flags); +int hgrnic_init_cq(struct hgrnic_dev *dev, int nent, + struct hgrnic_ucontext *ctx, u32 pdn, struct hgrnic_cq *cq); +void hgrnic_free_cq(struct hgrnic_dev *dev, + struct hgrnic_cq *cq); +void hgrnic_cq_clean(struct hgrnic_dev *dev, struct hgrnic_cq *cq, u32 qpn); +void hgrnic_cq_resize_copy_cqes(struct hgrnic_cq *cq); +int hgrnic_alloc_cq_buf(struct hgrnic_dev *dev, struct hgrnic_cq_buf *buf, int nent); +void hgrnic_free_cq_buf(struct hgrnic_dev *dev, struct hgrnic_cq_buf *buf, int cqe); + + +int hgrnic_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask, + struct ib_qp_init_attr *qp_init_attr); +struct ib_qp *hgrnic_create_qp (struct ib_pd *pd, + struct ib_qp_init_attr *init_attr, struct ib_udata *udata); +int hgrnic_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, int attr_mask, + struct ib_udata *udata); +int hgrnic_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr, + const struct ib_send_wr **bad_wr); +int hgrnic_post_receive(struct ib_qp *ibqp, const struct ib_recv_wr *wr, + const struct ib_recv_wr **bad_wr); +int hgrnic_alloc_qp(struct hgrnic_dev *dev, + struct hgrnic_pd *pd, + struct hgrnic_cq *send_cq, + struct hgrnic_cq *recv_cq, + enum ib_qp_type type, + struct ib_qp_cap *cap, + struct hgrnic_qp *qp, + struct ib_udata *udata); +void hgrnic_free_qp(struct hgrnic_dev *dev, struct hgrnic_qp *qp); + + +static inline struct hgrnic_dev *to_hgdev(struct ib_device *ibdev) { + return container_of(ibdev, struct hgrnic_dev, ib_dev); +} + +#endif /* HGRNIC_DEV_H */ diff --git a/ETH-PLUS_Jingzhao/JingZhao2/software/drivers/ib_hgrnic/hgrnic_doorbell.h b/ETH-PLUS_Jingzhao/JingZhao2/software/drivers/ib_hgrnic/hgrnic_doorbell.h new file mode 100644 index 0000000000000000000000000000000000000000..6f64a496350c7d8e94cf9856a1e14787f6908949 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/software/drivers/ib_hgrnic/hgrnic_doorbell.h @@ -0,0 +1,66 @@ +/************************************************************** + * @author Kang Ning, NCIC, ICT, CAS + * @date 2021.09.08 + * @file hgrnic_doorbell.h + * @note Data structs & functions related to doorbell + *************************************************************/ + +#include + + + +#if BITS_PER_LONG == 64 +/* + * Assume that we can just write a 64-bit doorbell atomically. s390 + * actually doesn't have writeq() but S/390 systems don't even have + * PCI so we won't worry about it. + */ + +#define HGRNIC_DECLARE_DOORBELL_LOCK(name) +#define HGRNIC_INIT_DOORBELL_LOCK(ptr) do { } while (0) +#define HGRNIC_GET_DOORBELL_LOCK(ptr) (NULL) + +static inline void hgrnic_write64_raw(__be64 val, void __iomem *dest) +{ + __raw_writeq((__force u64) val, dest); +} + +static inline void hgrnic_write64(u32 hi, u32 lo, void __iomem *dest, + spinlock_t *doorbell_lock) +{ + __raw_writeq((__force u64) cpu_to_le64((u64) hi << 32 | lo), dest); +} + +#else + +/* + * Just fall back to a spinlock to protect the doorbell if + * BITS_PER_LONG is 32 -- there's no portable way to do atomic 64-bit + * MMIO writes. + */ + +#define HGRNIC_DECLARE_DOORBELL_LOCK(name) spinlock_t name; +#define HGRNIC_INIT_DOORBELL_LOCK(ptr) spin_lock_init(ptr) +#define HGRNIC_GET_DOORBELL_LOCK(ptr) (ptr) + +static inline void hgrnic_write64_raw(__be64 val, void __iomem *dest) +{ + __raw_writel(((__force u32 *) &val)[0], dest); + __raw_writel(((__force u32 *) &val)[1], dest + 4); +} + +static inline void hgrnic_write64(u32 hi, u32 lo, void __iomem *dest, + spinlock_t *doorbell_lock) +{ + unsigned long flags; + + hi = (__force u32) cpu_to_le32(hi); + lo = (__force u32) cpu_to_le32(lo); + + spin_lock_irqsave(doorbell_lock, flags); + __raw_writel(lo, dest); + __raw_writel(hi, dest + 4); + spin_unlock_irqrestore(doorbell_lock, flags); +} + +#endif \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/software/drivers/ib_hgrnic/hgrnic_en_abi.h b/ETH-PLUS_Jingzhao/JingZhao2/software/drivers/ib_hgrnic/hgrnic_en_abi.h new file mode 100644 index 0000000000000000000000000000000000000000..66586197d5d536d4b57afc82ee087633062ebdcd --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/software/drivers/ib_hgrnic/hgrnic_en_abi.h @@ -0,0 +1,23 @@ +/************************************************************** + * @author Kang Ning, NCIC, ICT, CAS + * @date 2021.09.08 + * @file hgrnic_abi.h + * @note Device specific data and useful function for ethernet + *************************************************************/ + +#ifndef __HGRNIC_EN_ABI_H__ +#define __HGRNIC_EN_ABI_H__ + +#include +#include +#include + +struct hgrnic_endev { + void __iomem *reg; + void __iomem *msix_tab; + void __iomem *msix_pnd; +}; + +int hgrnic_register_en_driver (struct hgrnic_endev *endev); + +#endif // __HGRNIC_ABI_H__ \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/software/drivers/ib_hgrnic/hgrnic_eq.c b/ETH-PLUS_Jingzhao/JingZhao2/software/drivers/ib_hgrnic/hgrnic_eq.c new file mode 100644 index 0000000000000000000000000000000000000000..6e08dae4e0f7c85279e1692048d7b5f093755286 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/software/drivers/ib_hgrnic/hgrnic_eq.c @@ -0,0 +1,140 @@ +/************************************************************** + * @author Kang Ning, NCIC, ICT, CAS + * @date 2021.09.08 + * @file hgrnic_eq.c + * @note Functions & Data structs related to EQ. + *************************************************************/ + +#include +#include +#include +#include + +#include "hgrnic_dev.h" +#include "hgrnic_cmd.h" +#include "hgrnic_iface.h" + +enum { + HGRNIC_NUM_ASYNC_EQE = 0x80, + HGRNIC_NUM_CMD_EQE = 0x80, + HGRNIC_NUM_SPARE_EQE = 0x80, + HGRNIC_EQ_ENTRY_SIZE = 0x20 +}; + +/* + * Must be packed because start is 64 bits but only aligned to 32 bits. + */ +struct hgrnic_eq_context { + __be32 flags; + __be64 start; + __be32 logsize; + u8 reserved1[7]; + u8 intr; + __be32 pd; + __be32 lkey; + u32 reserved2[2]; + __be32 consumer_index; + __be32 producer_index; + u32 reserved3[4]; +} __packed; + +#define HGRNIC_EQ_STATUS_OK ( 0 << 28) +#define HGRNIC_EQ_OWNER_SW ( 0 << 24) +#define HGRNIC_EQ_OWNER_HW ( 1 << 24) +#define HGRNIC_EQ_FLAG_TR ( 1 << 18) +#define HGRNIC_EQ_FLAG_OI ( 1 << 17) +#define HGRNIC_EQ_STATE_ARMED ( 1 << 8) + +enum { + HGRNIC_EVENT_TYPE_COMP = 0x00, + HGRNIC_EVENT_TYPE_PATH_MIG = 0x01, + HGRNIC_EVENT_TYPE_COMM_EST = 0x02, + HGRNIC_EVENT_TYPE_SQ_DRAINED = 0x03, + HGRNIC_EVENT_TYPE_SRQ_QP_LAST_WQE = 0x13, + HGRNIC_EVENT_TYPE_SRQ_LIMIT = 0x14, + HGRNIC_EVENT_TYPE_CQ_ERROR = 0x04, + HGRNIC_EVENT_TYPE_WQ_CATAS_ERROR = 0x05, + HGRNIC_EVENT_TYPE_EEC_CATAS_ERROR = 0x06, + HGRNIC_EVENT_TYPE_PATH_MIG_FAILED = 0x07, + HGRNIC_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10, + HGRNIC_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11, + HGRNIC_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12, + HGRNIC_EVENT_TYPE_LOCAL_CATAS_ERROR = 0x08, + HGRNIC_EVENT_TYPE_PORT_CHANGE = 0x09, + HGRNIC_EVENT_TYPE_EQ_OVERFLOW = 0x0f, + HGRNIC_EVENT_TYPE_ECC_DETECT = 0x0e, + HGRNIC_EVENT_TYPE_CMD = 0x0a +}; + +#define HGRNIC_ASYNC_EVENT_MASK ((1ULL << HGRNIC_EVENT_TYPE_PATH_MIG) | \ + (1ULL << HGRNIC_EVENT_TYPE_COMM_EST) | \ + (1ULL << HGRNIC_EVENT_TYPE_SQ_DRAINED) | \ + (1ULL << HGRNIC_EVENT_TYPE_CQ_ERROR) | \ + (1ULL << HGRNIC_EVENT_TYPE_WQ_CATAS_ERROR) | \ + (1ULL << HGRNIC_EVENT_TYPE_EEC_CATAS_ERROR) | \ + (1ULL << HGRNIC_EVENT_TYPE_PATH_MIG_FAILED) | \ + (1ULL << HGRNIC_EVENT_TYPE_WQ_INVAL_REQ_ERROR) | \ + (1ULL << HGRNIC_EVENT_TYPE_WQ_ACCESS_ERROR) | \ + (1ULL << HGRNIC_EVENT_TYPE_LOCAL_CATAS_ERROR) | \ + (1ULL << HGRNIC_EVENT_TYPE_PORT_CHANGE) | \ + (1ULL << HGRNIC_EVENT_TYPE_ECC_DETECT)) +#define HGRNIC_SRQ_EVENT_MASK ((1ULL << HGRNIC_EVENT_TYPE_SRQ_CATAS_ERROR) | \ + (1ULL << HGRNIC_EVENT_TYPE_SRQ_QP_LAST_WQE) | \ + (1ULL << HGRNIC_EVENT_TYPE_SRQ_LIMIT)) +#define HGRNIC_CMD_EVENT_MASK (1ULL << HGRNIC_EVENT_TYPE_CMD) + + +#define HGRNIC_EQ_ENTRY_OWNER_SW (0 << 7) +#define HGRNIC_EQ_ENTRY_OWNER_HW (1 << 7) + + + + + +/** + * @param icm_virt virtual address of ICM space + * @note Init EQ table stored in struct hgrnic_dev. + */ +int hgrnic_map_eq_icm (struct hgrnic_dev *dev, u64 icm_virt) { + int ret; + + /* + * We assume that mapping one page is enough for the whole EQ + * context table. Currently we haven't implemented the mechanism + * of EQ. + */ + dev->eq_table.icm_virt = icm_virt; + dev->eq_table.icm_page = alloc_page(GFP_HIGHUSER); // allocate only one page + if (!dev->eq_table.icm_page) { + return -ENOMEM; + } + + // Set the page being accessed by DMA. + dev->eq_table.icm_dma = pci_map_page(dev->pdev, dev->eq_table.icm_page, 0, + PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); + if (pci_dma_mapping_error(dev->pdev, dev->eq_table.icm_dma)) { + __free_page(dev->eq_table.icm_page); + return -ENOMEM; + } + + // Write allocated ICM addr (bus addr, and its attached + // ICM virtual Addr) for EQ to Hardware. + printk(KERN_INFO PFX "Start hgrnic_MAP_ICM_page for EQ.\n"); + ret = hgrnic_MAP_ICM_page(dev, dev->eq_table.icm_dma, + CXT_REGION, icm_virt); + if (ret) { + pci_unmap_page(dev->pdev, dev->eq_table.icm_dma, PAGE_SIZE, + PCI_DMA_BIDIRECTIONAL); + __free_page(dev->eq_table.icm_page); + } + + return ret; +} + +void hgrnic_unmap_eq_icm (struct hgrnic_dev *dev) { + + hgrnic_UNMAP_ICM(dev, dev->eq_table.icm_virt, 1, CXT_REGION); + pci_unmap_page(dev->pdev, dev->eq_table.icm_dma, PAGE_SIZE, + PCI_DMA_BIDIRECTIONAL); + __free_page(dev->eq_table.icm_page); +} diff --git a/ETH-PLUS_Jingzhao/JingZhao2/software/drivers/ib_hgrnic/hgrnic_icm.c b/ETH-PLUS_Jingzhao/JingZhao2/software/drivers/ib_hgrnic/hgrnic_icm.c new file mode 100644 index 0000000000000000000000000000000000000000..642ee24709120337eeb60bcad025b6ec8bd43042 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/software/drivers/ib_hgrnic/hgrnic_icm.c @@ -0,0 +1,563 @@ +/************************************************************** + * @author Kang Ning, NCIC, ICT, CAS + * @date 2021.09.08 + * @file hgrnic_icm.c + * @note 1. Generate ICM memory map layout for HCA. + * 2. ICM utilize functions. + *************************************************************/ + + +#include +#include +#include +#include +#include +#include +#include +#include + +#include "hgrnic_dev.h" +#include "hgrnic_cmd.h" +#include "hgrnic_icm.h" + +enum { + HGRNIC_RES_QP, + HGRNIC_RES_CQ, + HGRNIC_RES_EQ, + HGRNIC_RES_MPT, + HGRNIC_RES_MTT, + HGRNIC_RES_NUM +}; + +enum { + HGRNIC_NUM_EQS = 32, + HGRNIC_NUM_PDS = 1 << 15 +}; + +/* + * We allocate in as big chunks as we can, up to a maximum of 256 KB + * per chunk. + */ +enum { + HGRNIC_ICM_ALLOC_SIZE = 1 << 18, + HGRNIC_TABLE_CHUNK_SIZE = 1 << 18 +}; + +static void hgrnic_free_icm_pages (struct hgrnic_dev *dev, + struct hgrnic_icm_chunk *chunk) +{ + int i; + + if (chunk->nsg > 0) { + pci_unmap_sg(dev->pdev, chunk->mem, chunk->npages, + PCI_DMA_BIDIRECTIONAL); + } + + for (i = 0; i < chunk->npages; ++i) { + __free_pages(sg_page(&chunk->mem[i]), + get_order(chunk->mem[i].length)); + } +} + +static void hgrnic_free_icm_coherent (struct hgrnic_dev *dev, + struct hgrnic_icm_chunk *chunk) { + int i; + + for (i = 0; i < chunk->npages; ++i) { + dma_free_coherent(&dev->pdev->dev, chunk->mem[i].length, + lowmem_page_address(sg_page(&chunk->mem[i])), + sg_dma_address(&chunk->mem[i])); + } +} + +void hgrnic_free_icm (struct hgrnic_dev *dev, + struct hgrnic_icm *icm, int coherent) +{ + struct hgrnic_icm_chunk *chunk, *tmp; + + if (!icm) + return; + + list_for_each_entry_safe(chunk, tmp, &icm->chunk_list, list) { + if (coherent) + hgrnic_free_icm_coherent(dev, chunk); + else + hgrnic_free_icm_pages(dev, chunk); + + kfree(chunk); + } + + kfree(icm); +} + +static int hgrnic_alloc_icm_pages (struct scatterlist *mem, + int order, gfp_t gfp_mask) { + struct page *page; + + /* + * Use __GFP_ZERO because buggy firmware assumes ICM pages are + * cleared, and subtle failures are seen if they aren't. + */ + page = alloc_pages(gfp_mask | __GFP_ZERO, order); + if (!page) { + return -ENOMEM; + } + + sg_set_page(mem, page, PAGE_SIZE << order, 0); + return 0; +} + +/** + * @note Allocate addr for ICM space uses. + * @param mem is the actual physical address (bus addr) + * through which HCA can access the memory. + */ +static int hgrnic_alloc_icm_coherent (struct device *dev, + struct scatterlist *mem, int order, gfp_t gfp_mask) { + void *buf = dma_alloc_coherent(dev, PAGE_SIZE << order, &sg_dma_address(mem), + gfp_mask); + if (!buf) { + return -ENOMEM; + } + + /* set ICM space as zero, in case of HW reads + * invalid data. */ + memset(buf, 0, PAGE_SIZE << order); + + sg_set_buf(mem, buf, PAGE_SIZE << order); + BUG_ON(mem->offset); + sg_dma_len(mem) = PAGE_SIZE << order; /* may be ueless ? */ + return 0; +} + +/** + * @note Allocate npages of pages for ICM space + * @param npages number of pages to be allocated. + */ +struct hgrnic_icm *hgrnic_alloc_icm (struct hgrnic_dev *dev, int npages, + gfp_t gfp_mask, int coherent) { + struct hgrnic_icm *icm; + struct hgrnic_icm_chunk *chunk = NULL; + int cur_order; + int ret; + + /* We use sg_set_buf for coherent allocs, which assumes low memory */ + BUG_ON(coherent && (gfp_mask & __GFP_HIGHMEM)); + + icm = kmalloc(sizeof *icm, gfp_mask & ~(__GFP_HIGHMEM | __GFP_NOWARN)); + if (!icm) + return icm; + + icm->refcount = 0; + INIT_LIST_HEAD(&icm->chunk_list); + + cur_order = get_order(HGRNIC_ICM_ALLOC_SIZE); + + while (npages > 0) { + if (!chunk) { + chunk = kmalloc(sizeof *chunk, + gfp_mask & ~(__GFP_HIGHMEM | __GFP_NOWARN)); + if (!chunk) + goto fail; + + sg_init_table(chunk->mem, HGRNIC_ICM_CHUNK_LEN); + chunk->npages = 0; + chunk->nsg = 0; + list_add_tail(&chunk->list, &icm->chunk_list); + } + + while (1 << cur_order > npages) + --cur_order; + + if (coherent) { + ret = hgrnic_alloc_icm_coherent(&dev->pdev->dev, + &chunk->mem[chunk->npages], + cur_order, gfp_mask); + } else { + ret = hgrnic_alloc_icm_pages(&chunk->mem[chunk->npages], + cur_order, gfp_mask); + } + + if (!ret) { + ++chunk->npages; + + if (coherent) { + ++chunk->nsg; + } else if (chunk->npages == HGRNIC_ICM_CHUNK_LEN) { + chunk->nsg = pci_map_sg(dev->pdev, chunk->mem, + chunk->npages, + PCI_DMA_BIDIRECTIONAL); + + if (chunk->nsg <= 0) + goto fail; + } + + if (chunk->npages == HGRNIC_ICM_CHUNK_LEN) + chunk = NULL; + + npages -= 1 << cur_order; + } else { + --cur_order; + if (cur_order < 0) + goto fail; + } + } + + if (!coherent && chunk) { + chunk->nsg = pci_map_sg(dev->pdev, chunk->mem, + chunk->npages, + PCI_DMA_BIDIRECTIONAL); + + if (chunk->nsg <= 0) + goto fail; + } + + return icm; + +fail: + hgrnic_free_icm(dev, icm, coherent); + return NULL; +} + +/** + * @note Allocate physical address of ICM space, and + * write ICM memory map (ICM virt addr : phy addr) + * into HCA. + * @param table Resource table that records ICM usage. + * @param obj the start addr of one chunk of resource + * @param type_sel type of the resource + */ +int hgrnic_reg_icm (struct hgrnic_dev *dev, + struct hgrnic_icm_table *table, + int obj, u8 type_sel) +{ + int i = (obj & (table->num_obj - 1)) * table->obj_size / HGRNIC_TABLE_CHUNK_SIZE; + int ret = 0; + + mutex_lock(&table->mutex); + + /** + * Since ICM space is allocated at the grantuarlity of Chunk, + * the obj may have been allocated before. + */ + if (table->icm[i]) { + ++table->icm[i]->refcount; + goto out; + } + + /* Get ICM memory from kernel */ + table->icm[i] = hgrnic_alloc_icm(dev, HGRNIC_TABLE_CHUNK_SIZE >> PAGE_SHIFT, + (table->lowmem ? GFP_KERNEL : GFP_HIGHUSER) | + __GFP_NOWARN, table->coherent); + if (!table->icm[i]) { + ret = -ENOMEM; + goto out; + } + + /* Write ICM memory map to HCA. */ + if (hgrnic_MAP_ICM(dev, table->icm[i], type_sel, + table->virt + i * HGRNIC_TABLE_CHUNK_SIZE)) { + hgrnic_free_icm(dev, table->icm[i], table->coherent); + table->icm[i] = NULL; + ret = -ENOMEM; + goto out; + } + + ++table->icm[i]->refcount; + +out: + mutex_unlock(&table->mutex); + return ret; +} + +/** + * @note unmap ICM addr space in HCA hardware and free + * corresponding ICM table entries. + */ +void hgrnic_unreg_icm (struct hgrnic_dev *dev, + struct hgrnic_icm_table *table, int obj, u8 type_sel) +{ + int i; + + i = (obj & (table->num_obj - 1)) * table->obj_size / HGRNIC_TABLE_CHUNK_SIZE; + + mutex_lock(&table->mutex); + + if (--table->icm[i]->refcount == 0) { + hgrnic_UNMAP_ICM(dev, table->virt + i * HGRNIC_TABLE_CHUNK_SIZE, + HGRNIC_TABLE_CHUNK_SIZE / HGRNIC_ICM_PAGE_SIZE, type_sel); + hgrnic_free_icm(dev, table->icm[i], table->coherent); + table->icm[i] = NULL; + } + + mutex_unlock(&table->mutex); +} + + +/** + * @note This function does the following things: + * 1. Allocate a range of ICM space, and + * 2. write its map to HCA hardware. + * @param start start of ICM resource index + * @param end end of ICM resource index + */ +int hgrnic_reg_icm_range(struct hgrnic_dev *dev, + struct hgrnic_icm_table *table, int start, int end, u8 type_sel) +{ + int inc = HGRNIC_TABLE_CHUNK_SIZE / table->obj_size; + int i, err; + + for (i = start; i <= end; i += inc) { + err = hgrnic_reg_icm(dev, table, i, type_sel); + if (err) + goto fail; + } + + return 0; + +fail: + while (i > start) { + i -= inc; + hgrnic_unreg_icm(dev, table, i, type_sel); + } + + return err; +} + +void hgrnic_unreg_icm_range (struct hgrnic_dev *dev, + struct hgrnic_icm_table *table, int start, int end, u8 type_sel) +{ + int i; + + for (i = start; i <= end; + i += HGRNIC_TABLE_CHUNK_SIZE / table->obj_size) { + hgrnic_unreg_icm(dev, table, i, type_sel); + } +} + +/** + * @description: + * Initialize ICM table in software, who stores meta data for HCA resources + * stored in ICM space (like QP, CQ, MPT, MTT). + */ +struct hgrnic_icm_table *hgrnic_alloc_icm_table (struct hgrnic_dev *dev, + u64 virt, int obj_size, int nobj, int reserved, int use_lowmem, + int use_coherent, u8 type_sel) { + struct hgrnic_icm_table *table; + int obj_per_chunk; + int num_icm; + unsigned chunk_size; + int i; + + if (obj_size == 0 || nobj == 0) { + hgrnic_err(dev, "Error! obj_size or nobj is zero.\n"); + return NULL; + } + obj_per_chunk = HGRNIC_TABLE_CHUNK_SIZE / obj_size; + num_icm = DIV_ROUND_UP(nobj, obj_per_chunk); + + table = kmalloc(struct_size(table, icm, num_icm), GFP_KERNEL); + if (!table) { + return NULL; + } + table->virt = virt; + table->num_icm = num_icm; + table->num_obj = nobj; + table->obj_size = obj_size; + table->lowmem = use_lowmem; + table->coherent = use_coherent; + mutex_init(&table->mutex); + + for (i = 0; i < num_icm; ++i) { + table->icm[i] = NULL; + } + + /** + * We currently set reserved size as 0, + * so this code block is useless. + * !TODO: We may delete it in later version. + */ + for (i = 0; i * HGRNIC_TABLE_CHUNK_SIZE < reserved * obj_size; ++i) { + chunk_size = HGRNIC_TABLE_CHUNK_SIZE; + if ((i + 1) * HGRNIC_TABLE_CHUNK_SIZE > nobj * obj_size) { + chunk_size = nobj * obj_size - i * HGRNIC_TABLE_CHUNK_SIZE; + } + + table->icm[i] = hgrnic_alloc_icm(dev, chunk_size >> PAGE_SHIFT, + (use_lowmem ? GFP_KERNEL : GFP_HIGHUSER) | + __GFP_NOWARN, use_coherent); + if (!table->icm[i]) { + goto err; + } + printk(KERN_INFO PFX "Start hgrnic_MAP_ICM.\n"); + if (hgrnic_MAP_ICM(dev, table->icm[i], type_sel, + virt + i * HGRNIC_TABLE_CHUNK_SIZE)) { + hgrnic_free_icm(dev, table->icm[i], table->coherent); + table->icm[i] = NULL; + goto err; + } + + + /* + * Add a reference to this ICM chunk so that it never + * gets freed (since it contains reserved firmware objects). + */ + ++table->icm[i]->refcount; + } + + return table; + +err: + for (i = 0; i < num_icm; ++i) { + if (table->icm[i]) { + hgrnic_UNMAP_ICM(dev, virt + i * HGRNIC_TABLE_CHUNK_SIZE, + HGRNIC_TABLE_CHUNK_SIZE / HGRNIC_ICM_PAGE_SIZE, type_sel); + hgrnic_free_icm(dev, table->icm[i], table->coherent); + } + } + + kfree(table); + + return NULL; +} + +void hgrnic_free_icm_table (struct hgrnic_dev *dev, + struct hgrnic_icm_table *table, u8 type_sel) { + int i; + + for (i = 0; i < table->num_icm; ++i) { + if (table->icm[i]) { + hgrnic_UNMAP_ICM(dev, + table->virt + i * HGRNIC_TABLE_CHUNK_SIZE, + HGRNIC_TABLE_CHUNK_SIZE / HGRNIC_ICM_PAGE_SIZE, type_sel); + hgrnic_free_icm(dev, table->icm[i], table->coherent); + } + } + + kfree(table); +} + + + +s64 hgrnic_make_profile (struct hgrnic_dev *dev, + struct hgrnic_profile *request, struct hgrnic_dev_lim *dev_lim, + struct hgrnic_init_hca_param *init_hca) { + struct hgrnic_resource { + u64 size ; // size of every resource region (in bytes) + u64 start; + int type ; + int num ; // number of entries + int log_num; + }; + + u64 mem_base, mem_avail; + s64 total_size = 0; + struct hgrnic_resource *profile; + int i, j; + + profile = kcalloc(HGRNIC_RES_NUM, sizeof(*profile), GFP_KERNEL); + if (!profile) { + return -ENOMEM; + } + + profile[HGRNIC_RES_QP].size = dev_lim->qpc_entry_sz; + profile[HGRNIC_RES_CQ].size = dev_lim->cqc_entry_sz; + profile[HGRNIC_RES_EQ].size = dev_lim->eqc_entry_sz; + profile[HGRNIC_RES_MPT].size = dev_lim->mpt_entry_sz; + profile[HGRNIC_RES_MTT].size = dev_lim->max_mtt_seg ; + + profile[HGRNIC_RES_QP].num = request->num_qp; + profile[HGRNIC_RES_CQ].num = request->num_cq; + profile[HGRNIC_RES_EQ].num = HGRNIC_NUM_EQS; + profile[HGRNIC_RES_MPT].num = request->num_mpt; + profile[HGRNIC_RES_MTT].num = request->num_mtt; + + for (i = 0; i < HGRNIC_RES_NUM; ++i) { + profile[i].type = i; + profile[i].log_num = max(ffs(profile[i].num) - 1, 0); + profile[i].size *= profile[i].num; + profile[i].size = max(profile[i].size, (u64) PAGE_SIZE); + } + + mem_base = 0; + mem_avail = dev_lim->max_icm_sz; + + /* + * Sort the resources in decreasing order of size. Since they + * all have sizes that are powers of 2, we'll be able to keep + * resources aligned to their size and pack them without gaps + * using the sorted order. + */ + for (i = HGRNIC_RES_NUM; i > 0; --i) + for (j = 1; j < i; ++j) { + if (profile[j].size > profile[j - 1].size) + swap(profile[j], profile[j - 1]); + } + + for (i = 0; i < HGRNIC_RES_NUM; ++i) { + if (profile[i].size) { + profile[i].start = mem_base + total_size; + total_size += profile[i].size; + } + if (total_size > mem_avail) { + hgrnic_err(dev, "Profile requires 0x%llx bytes; " + "won't fit in 0x%llx bytes of context memory.\n", + (unsigned long long) total_size, + (unsigned long long) mem_avail); + kfree(profile); + return -ENOMEM; + } + + if (profile[i].size) + printk(KERN_INFO PFX "profile[%2d]--%2d/%2d @ 0x%16llx " + "(size 0x%8llx)\n", + i, profile[i].type, profile[i].log_num, + (unsigned long long) profile[i].start, + (unsigned long long) profile[i].size); + } + + printk(KERN_INFO PFX "HCA context memory: reserving %d KB\n", + (int) (total_size >> 10)); + + for (i = 0; i < HGRNIC_RES_NUM; ++i) { + switch (profile[i].type) { + case HGRNIC_RES_QP: + dev->limits.num_qps = profile[i].num; + init_hca->qpc_base = profile[i].start; + init_hca->log_num_qps = profile[i].log_num; + break; + case HGRNIC_RES_CQ: + dev->limits.num_cqs = profile[i].num; + init_hca->cqc_base = profile[i].start; + init_hca->log_num_cqs = profile[i].log_num; + break; + case HGRNIC_RES_EQ: + dev->limits.num_eqs = profile[i].num; + init_hca->eqc_base = profile[i].start; + init_hca->log_num_eqs = profile[i].log_num; + break; + case HGRNIC_RES_MPT: + dev->limits.num_mpts = profile[i].num; + dev->mr_table.mpt_base = profile[i].start; + init_hca->mpt_base = profile[i].start; + init_hca->log_mpt_sz = profile[i].log_num; + break; + case HGRNIC_RES_MTT: + dev->limits.num_mtt_segs = profile[i].num; + dev->mr_table.mtt_base = profile[i].start; + init_hca->mtt_base = profile[i].start; + break; + default: + break; + } + } + + /* + * PDs don't take any HCA memory, but we assign them as part + * of the HCA profile anyway. + */ + dev->limits.num_pds = HGRNIC_NUM_PDS; + + kfree(profile); + return total_size; +} diff --git a/ETH-PLUS_Jingzhao/JingZhao2/software/drivers/ib_hgrnic/hgrnic_icm.h b/ETH-PLUS_Jingzhao/JingZhao2/software/drivers/ib_hgrnic/hgrnic_icm.h new file mode 100644 index 0000000000000000000000000000000000000000..e92215d7469f49ece13a8bcf60b445411764b7fa --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/software/drivers/ib_hgrnic/hgrnic_icm.h @@ -0,0 +1,127 @@ +/************************************************************** + * @author Kang Ning, NCIC, ICT, CAS + * @date 2021.09.08 + * @file hgrnic_icm.h + * @note Generate ICM memory map layout for HCA (INIT_HCA would send this layout). + *************************************************************/ + +#ifndef __HGRNIC_ICM_H__ +#define __HGRNIC_ICM_H__ + +#include +#include + +#include "hgrnic_dev.h" +#include "hgrnic_cmd.h" + + +#define HGRNIC_ICM_CHUNK_LEN \ + ((256 - sizeof (struct list_head) - 2 * sizeof (int)) / \ + (sizeof (struct scatterlist))) + +enum { + HGRNIC_ICM_PAGE_SHIFT = 12, + HGRNIC_ICM_PAGE_SIZE = 1 << HGRNIC_ICM_PAGE_SHIFT +}; + +struct hgrnic_profile { + int num_qp; + int num_cq; + int num_mpt; + int num_mtt; +}; + +struct hgrnic_icm_chunk { + struct list_head list; + int npages; /* number of entries of sg list (before merge) */ + int nsg; /* number of entries of sg list (after merge). */ + struct scatterlist mem[HGRNIC_ICM_CHUNK_LEN]; +}; + +struct hgrnic_icm { + struct list_head chunk_list; + int refcount; +}; + +struct hgrnic_icm_table { + u64 virt ; /* start virtual address (ICM space) for this icm resource */ + int num_icm ; /* Number of chunks allocated for this resources in ICM. */ + int num_obj ; /* Number of entries for this kind of resource.(in power of 2) */ + int obj_size; /* Size of the resource (in bytes). */ + int lowmem ; /* If this ICM space is in low memory (It seems that + * we don't need to care about it). */ + int coherent; + struct mutex mutex ; + struct hgrnic_icm *icm[0] ; /* Address list for ICM space, + * one elem in the array stands for the size of one chunk. */ +}; + +struct hgrnic_icm_iter { + struct hgrnic_icm *icm; + struct hgrnic_icm_chunk *chunk; + int page_idx; +}; + +struct hgrnic_dev; +struct hgrnic_dev_lim; +struct hgrnic_init_hca_param; + + +s64 hgrnic_make_profile(struct hgrnic_dev *mdev, struct hgrnic_profile *request, + struct hgrnic_dev_lim *dev_lim, struct hgrnic_init_hca_param *init_hca); + +struct hgrnic_icm *hgrnic_alloc_icm(struct hgrnic_dev *dev, int npages, + gfp_t gfp_mask, int coherent); +void hgrnic_free_icm(struct hgrnic_dev *dev, struct hgrnic_icm *icm, int coherent); + +struct hgrnic_icm_table *hgrnic_alloc_icm_table (struct hgrnic_dev *dev, + u64 virt, int obj_size, int nobj, int reserved, int use_lowmem, + int use_coherent, u8 type_sel); +void hgrnic_free_icm_table (struct hgrnic_dev *dev, + struct hgrnic_icm_table *table, u8 type_sel); +int hgrnic_reg_icm(struct hgrnic_dev *dev, + struct hgrnic_icm_table *table, int obj, u8 type_sel); +void hgrnic_unreg_icm (struct hgrnic_dev *dev, + struct hgrnic_icm_table *table, int obj, u8 type_sel); +int hgrnic_reg_icm_range(struct hgrnic_dev *dev, + struct hgrnic_icm_table *table, int start, int end, u8 type_sel); +void hgrnic_unreg_icm_range(struct hgrnic_dev *dev, + struct hgrnic_icm_table *table, int start, int end, u8 type_sel); + +static inline void hgrnic_icm_first (struct hgrnic_icm *icm, + struct hgrnic_icm_iter *iter) { + iter->icm = icm; + iter->chunk = list_empty(&icm->chunk_list) ? + NULL : list_entry(icm->chunk_list.next, + struct hgrnic_icm_chunk, list); + iter->page_idx = 0; +} + +static inline int hgrnic_icm_last (struct hgrnic_icm_iter *iter) { + return !iter->chunk; +} + +static inline void hgrnic_icm_next (struct hgrnic_icm_iter *iter) { + if (++iter->page_idx >= iter->chunk->nsg) { + if (iter->chunk->list.next == &iter->icm->chunk_list) { + iter->chunk = NULL; + return; + } + + iter->chunk = list_entry(iter->chunk->list.next, + struct hgrnic_icm_chunk, list); + iter->page_idx = 0; + } +} + +static inline dma_addr_t hgrnic_icm_addr (struct hgrnic_icm_iter *iter) { + return sg_dma_address(&iter->chunk->mem[iter->page_idx]); +} + +static inline unsigned long hgrnic_icm_size ( + struct hgrnic_icm_iter *iter) { + return sg_dma_len(&iter->chunk->mem[iter->page_idx]); // "byte" is the unit +} + + +#endif /* __HGRNIC_ICM_H__ */ diff --git a/ETH-PLUS_Jingzhao/JingZhao2/software/drivers/ib_hgrnic/hgrnic_iface.h b/ETH-PLUS_Jingzhao/JingZhao2/software/drivers/ib_hgrnic/hgrnic_iface.h new file mode 100644 index 0000000000000000000000000000000000000000..623d28c3658ef2fc60d98e951c4235b295778202 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/software/drivers/ib_hgrnic/hgrnic_iface.h @@ -0,0 +1,28 @@ +/************************************************************** + * @author Kang Ning, NCIC, ICT, CAS + * @date 2021.09.08 + * @file hgrnic_iface.h + * @note Data structs & functions related to doorbell + *************************************************************/ + +#ifndef __HGRNIC_IFACE_H__ +#define __HGRNIC_IFACE_H__ + +/* ---------------RDMA BAR Space Interface{begin}-------------- */ + +// --------------- BAR 0-1 ---------------// +#define HGRNIC_HCR_BASE 0x00000 +#define HGRNIC_HCR_SIZE 0x01000 +#define HGRNIC_EN_REG_BASE 0x01000 +#define HGRNIC_EN_REG_SIZE 0x00400 +#define HGRNIC_MSIX_TAB_BASE 0x20000 +#define HGRNIC_MSIX_TAB_SIZE 0x01000 +#define HGRNIC_MSIX_PND_BASE 0x30000 +#define HGRNIC_MSIX_PND_SIZE 0x01000 + + +// --------------- BAR 2-3 ---------------// +#define HGRNIC_SEND_DOORBELL 0x00 // Temporary set as 0. +/* --------RDMA BAR Space Interface{end}------- */ + +#endif /* __HGRNIC_IFACE_H__ */ diff --git a/ETH-PLUS_Jingzhao/JingZhao2/software/drivers/ib_hgrnic/hgrnic_main.c b/ETH-PLUS_Jingzhao/JingZhao2/software/drivers/ib_hgrnic/hgrnic_main.c new file mode 100644 index 0000000000000000000000000000000000000000..687ee0db31ef0c23f5f9d9e6d83e78016b006009 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/software/drivers/ib_hgrnic/hgrnic_main.c @@ -0,0 +1,733 @@ +/************************************************************** + * @author Kang Ning, NCIC, ICT, CAS + * @date 2021.08.30 + * @file hgrnic_main.c + * @note Configuration and initialization on the RNIC hardware. + *************************************************************/ + +#include +#include +#include +#include +#include +#include + +// Used to delay a given time to wait the finishes of data transmission +#include + +#include "hgrnic_dev.h" +#include "hgrnic_iface.h" +#include "hgrnic_cmd.h" +#include "hgrnic_icm.h" +#include "hgrnic_register.h" + +MODULE_AUTHOR("Kang Ning"); +MODULE_DESCRIPTION("HanGu RDMA NIC low-level driver"); +MODULE_LICENSE("Dual BSD/GPL"); + + +static int config_rdma = 1; +module_param(config_rdma, int, 0444); +MODULE_PARM_DESC(config_rdma, "Active RDMA function if non-zero."); + +// Protect multi devices from executing +// the code at the same time. +DEFINE_MUTEX(hgrnic_device_mutex); + +#define HGRNIC_DEFAULT_NUM_QP (1 << 16) +#define HGRNIC_DEFAULT_RDB_PER_QP (1 << 2) +#define HGRNIC_DEFAULT_NUM_CQ (1 << 16) +#define HGRNIC_DEFAULT_NUM_MCG (1 << 13) +#define HGRNIC_DEFAULT_NUM_MPT (1 << 17) +#define HGRNIC_DEFAULT_NUM_MTT (1 << 20) +#define HGRNIC_DEFAULT_NUM_UDAV (1 << 15) +#define HGRNIC_DEFAULT_NUM_RESERVED_MTTS (1 << 18) +#define HGRNIC_DEFAULT_NUM_UARC_SIZE (1 << 18) + +static struct hgrnic_profile hca_profile = { + .num_qp = HGRNIC_DEFAULT_NUM_QP, + .num_cq = HGRNIC_DEFAULT_NUM_CQ, + .num_mpt = HGRNIC_DEFAULT_NUM_MPT, + .num_mtt = HGRNIC_DEFAULT_NUM_MTT, +}; + +module_param_named(num_qp, hca_profile.num_qp, int, 0444); +MODULE_PARM_DESC(num_qp, "maximum number of QPs per HCA"); + +module_param_named(num_cq, hca_profile.num_cq, int, 0444); +MODULE_PARM_DESC(num_cq, "maximum number of CQs per HCA"); + +module_param_named(num_mpt, hca_profile.num_mpt, int, 0444); +MODULE_PARM_DESC(num_mpt, + "maximum number of memory protection table entries per HCA"); + +module_param_named(num_mtt, hca_profile.num_mtt, int, 0444); +MODULE_PARM_DESC(num_mtt, + "maximum number of memory translation table segments per HCA"); + +// static int log_mtts_per_seg = ilog2(HGRNIC_MTT_SEG_SIZE / 8); +// module_param_named(log_mtts_per_seg, log_mtts_per_seg, int, 0444); +// MODULE_PARM_DESC(log_mtts_per_seg, "Log2 number of MTT entries per segment (1-5)"); + +static char hgrnic_version[] = + DRV_NAME ": ICT InfiniBand HCA driver v" + DRV_VERSION " (" DRV_RELDATE ")\n"; + +/** + * @description: + * Set PCI burst from the default to 4096. + */ +static int hgrnic_tune_pci (struct hgrnic_dev *hgdev) { + + if (pci_is_pcie(hgdev->pdev)) { + if (pcie_set_readrq(hgdev->pdev, 4096)) { + hgrnic_err(hgdev, "Couldn't write PCI Express read request, " + "aborting.\n"); + return -ENODEV; + } + } else if (hgdev->hgrnic_flags & HGRNIC_FLAG_PCIE) { + hgrnic_info(hgdev, "No PCI Express capability, " + "not setting Max Read Request Size.\n"); + } + + return 0; +} + +static int hgrnic_dev_lim (struct hgrnic_dev *hgdev, struct hgrnic_dev_lim *dev_lim) { + int err; + + hgdev->limits.mtt_seg_size = 8; + + err = hgrnic_QUERY_DEV_LIM(hgdev, dev_lim); + if (err) { + hgrnic_err(hgdev, "QUERY_DEV_LIM command returned %d" + ", aborting.\n", err); + return err; + } + if (dev_lim->min_page_sz > PAGE_SIZE) { + hgrnic_err(hgdev, "HCA minimum page size of %d bigger than " + "kernel PAGE_SIZE of %ld, aborting.\n", + dev_lim->min_page_sz, PAGE_SIZE); + return -ENODEV; + } + if (dev_lim->num_ports > HGRNIC_MAX_PORTS) { + hgrnic_err(hgdev, "HCA has %d ports, but we only support %d, " + "aborting.\n", + dev_lim->num_ports, HGRNIC_MAX_PORTS); + return -ENODEV; + } + + hgdev->limits.reserved_qps = dev_lim->reserved_qps; + hgdev->limits.reserved_cqs = dev_lim->reserved_cqs; + hgdev->limits.reserved_eqs = dev_lim->reserved_eqs; + hgdev->limits.reserved_mtts = dev_lim->reserved_mtts; + hgdev->limits.reserved_mrws = 0; + hgdev->limits.reserved_pds = dev_lim->reserved_pds; + + hgdev->limits.max_wqes = dev_lim->max_qp_sz; + + /** + * Subtract 1 from the limit because we need to allocate a + * spare CQE so the HCA HW can tell the difference between an + * empty CQ and a full CQ. FIXME: What does this mean? + */ + hgdev->limits.max_cqes = dev_lim->max_cq_sz - 1; + + hgdev->limits.num_ports = dev_lim->num_ports; + hgdev->limits.vl_cap = dev_lim->max_vl; + hgdev->limits.mtu_cap = dev_lim->max_mtu; + hgdev->limits.gid_table_len = dev_lim->max_gids; + hgdev->limits.pkey_table_len = dev_lim->max_pkeys; + hgdev->limits.local_ca_ack_delay = dev_lim->local_ca_ack_delay; + /* + * Need to allow for worst case send WQE overhead and check + * whether max_desc_sz imposes a lower limit than max_sg; UD + * send has the biggest overhead. + */ + hgdev->limits.max_sg = 16; + hgdev->limits.max_desc_sz = dev_lim->max_desc_sz; + + hgdev->limits.port_width_cap = dev_lim->max_port_width; + hgdev->limits.page_size_cap = ~(u32) (dev_lim->min_page_sz - 1); + + hgdev->limits.num_uars = 0x1000; + + return 0; +} + + +static int hgrnic_init_icm (struct hgrnic_dev *hgdev, struct hgrnic_dev_lim *dev_lim, + struct hgrnic_init_hca_param *init_hca) { + int err; + + printk(KERN_INFO PFX "Start map_eq_icm.\n"); + err = hgrnic_map_eq_icm(hgdev, init_hca->eqc_base); + if (err) { + hgrnic_err(hgdev, "Failed to map EQ context memory, aborting.\n"); + return err; + } + + printk(KERN_INFO PFX "Start map_qp_icm. resved_qps: %d\n", hgdev->limits.reserved_qps); + hgdev->qp_table.qp_table = hgrnic_alloc_icm_table(hgdev, init_hca->qpc_base, + dev_lim->qpc_entry_sz, hgdev->limits.num_qps, + hgdev->limits.reserved_qps, 0, 0, CXT_REGION); + if (!hgdev->qp_table.qp_table) { + hgrnic_err(hgdev, "Failed to map QP context memory, aborting.\n"); + err = -ENOMEM; + goto err_unmap_eq; + } + + printk(KERN_INFO PFX "Start map_cq_icm. resved_cqs: %d\n", hgdev->limits.reserved_cqs); + hgdev->cq_table.table = hgrnic_alloc_icm_table(hgdev, init_hca->cqc_base, + dev_lim->cqc_entry_sz, hgdev->limits.num_cqs, + hgdev->limits.reserved_cqs, 0, 0, CXT_REGION); + if (!hgdev->cq_table.table) { + hgrnic_err(hgdev, "Failed to map CQ context memory, aborting.\n"); + err = -ENOMEM; + goto err_unmap_qp; + } + + printk(KERN_INFO PFX "Start map_mtt_icm. resved_mtts: %d\n", hgdev->limits.reserved_mtts); + hgdev->limits.reserved_mtts = 0; + hgdev->mr_table.mtt_table = hgrnic_alloc_icm_table(hgdev, init_hca->mtt_base, + hgdev->limits.mtt_seg_size, hgdev->limits.num_mtt_segs, + 1, 1, 0, TPT_REGION); + if (!hgdev->mr_table.mtt_table) { + hgrnic_err(hgdev, "Failed to map MTT context memory, aborting.\n"); + err = -ENOMEM; + goto err_unmap_cq; + } + + printk(KERN_INFO PFX "Start map_mpt_icm. resved_mpt: %d\n", hgdev->limits.reserved_mrws); + hgdev->mr_table.mpt_table = hgrnic_alloc_icm_table(hgdev, init_hca->mpt_base, + dev_lim->mpt_entry_sz, hgdev->limits.num_mpts, + 1, 1, 1, TPT_REGION); + if (!hgdev->mr_table.mpt_table) { + hgrnic_err(hgdev, "Failed to map MPT context memory, aborting.\n"); + err = -ENOMEM; + goto err_unmap_mtt; + } + + return 0; + +err_unmap_mtt: + hgrnic_free_icm_table(hgdev, hgdev->mr_table.mtt_table, TPT_REGION); + +err_unmap_cq: + hgrnic_free_icm_table(hgdev, hgdev->cq_table.table, CXT_REGION); + +err_unmap_qp: + hgrnic_free_icm_table(hgdev, hgdev->qp_table.qp_table, CXT_REGION); + +err_unmap_eq: + hgrnic_unmap_eq_icm(hgdev); + return err; +} + +static void hgrnic_free_icms (struct hgrnic_dev *hgdev) { + + hgrnic_free_icm_table(hgdev, hgdev->mr_table.mpt_table, TPT_REGION); + hgrnic_free_icm_table(hgdev, hgdev->mr_table.mtt_table, TPT_REGION); + hgrnic_free_icm_table(hgdev, hgdev->cq_table.table, CXT_REGION); + hgrnic_free_icm_table(hgdev, hgdev->qp_table.qp_table, CXT_REGION); + hgrnic_unmap_eq_icm(hgdev); +} + +/** + * @description: + * Initialize HCA resource. Write ICM memory layout to + * HCA, and Initialize ICM allocation + * + */ +static int hgrnic_init_hca (struct hgrnic_dev *hgdev) { + int err; + + struct hgrnic_dev_lim dev_lim; + struct hgrnic_init_hca_param init_hca; + s64 icm_size; + + printk(KERN_INFO PFX "Start QUERY ADAPTER.\n"); + + + err = hgrnic_QUERY_ADAPTER(hgdev, &hgdev->board_id); + if (err) { + hgrnic_err(hgdev, "QUERY_ADAPTER command returned %d, aborting.\n", err); + return err; + } + + printk(KERN_INFO PFX "Start dev lim.\n"); + err = hgrnic_dev_lim(hgdev, &dev_lim); + if (err) { + hgrnic_err(hgdev, "QUERY_DEV_LIM returned %d, aborting.\n", err); + return err; + } + + icm_size = hgrnic_make_profile(hgdev, &hca_profile, &dev_lim, &init_hca); + if (icm_size < 0) { + err = icm_size; + return err; + } + printk(KERN_INFO PFX "Start Init_HCA.\n"); + err = hgrnic_INIT_HCA(hgdev, &init_hca); + if (err) { + hgrnic_err(hgdev, "INIT_HCA command returned %d, aborting.\n", err); + return err; + } + + printk(KERN_INFO PFX "Start init_icm.\n"); + err = hgrnic_init_icm(hgdev, &dev_lim, &init_hca); + if (err) { + goto err_close; + } + + return 0; + +err_close: + hgrnic_CLOSE_HCA(hgdev); + return err; +} + +static int hgrnic_setup_hca (struct hgrnic_dev *dev) { + int err; + + HGRNIC_INIT_DOORBELL_LOCK(&dev->doorbell_lock); + + /** + * Initialize UAR Space (PIO BAR2 space) allocator. + */ + printk(KERN_INFO PFX "Start hgrnic_init_uar_table.\n"); + err = hgrnic_init_uar_table(dev); + if (err) { + hgrnic_err(dev, "Failed to initialize " + "user access region table, aborting.\n"); + return err; + } + printk(KERN_INFO PFX "Start hgrnic_uar_alloc.\n"); + err = hgrnic_uar_alloc(dev, &dev->driver_uar); + if (err) { + hgrnic_err(dev, "Failed to allocate driver access region, " + "aborting.\n"); + goto err_uar_table_free; + } + + // Get Kernel Access Region in BAR2. + printk(KERN_INFO PFX "Start ioremap.\n"); + dev->kar = ioremap((phys_addr_t) dev->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE); + if (!dev->kar) { + hgrnic_err(dev, "Couldn't map kernel access region, " + "aborting.\n"); + err = -ENOMEM; + goto err_uar_free; + } + + printk(KERN_INFO PFX "Start hgrnic_init_pd_table.\n"); + err = hgrnic_init_pd_table(dev); + if (err) { + hgrnic_err(dev, "Failed to initialize " + "protection domain table, aborting.\n"); + goto err_kar_unmap; + } + + printk(KERN_INFO PFX "Start hgrnic_init_mr_table.\n"); + err = hgrnic_init_mr_table(dev); + if (err) { + hgrnic_err(dev, "Failed to initialize " + "memory region table, aborting.\n"); + goto err_pd_table_free; + } + + /** + * PD allocation need MR table, so this function must be + * called after init_mr_table. + */ + printk(KERN_INFO PFX "Start hgrnic_pd_alloc.\n"); + err = hgrnic_pd_alloc(dev, 1, &dev->driver_pd); + (dev->driver_pd).ibpd.device = &(dev->ib_dev); + if (err) { + hgrnic_err(dev, "Failed to create driver PD, " + "aborting.\n"); + goto err_mr_table_free; + } + + printk(KERN_INFO PFX "Start hgrnic_init_cq_table.\n"); + err = hgrnic_init_cq_table(dev); + if (err) { + hgrnic_err(dev, "Failed to initialize " + "completion queue table, aborting.\n"); + goto err_pd_free; + } + + printk(KERN_INFO PFX "Start hgrnic_init_qp_table.\n"); + err = hgrnic_init_qp_table(dev); + if (err) { + hgrnic_err(dev, "Failed to initialize " + "queue pair table, aborting.\n"); + goto err_cq_table_free; + } + + return 0; + + +err_cq_table_free: + hgrnic_cleanup_cq_table(dev); + +err_pd_free: + hgrnic_pd_free(dev, &dev->driver_pd); + +err_mr_table_free: + hgrnic_cleanup_mr_table(dev); + +err_pd_table_free: + hgrnic_cleanup_pd_table(dev); + +err_kar_unmap: + iounmap(dev->kar); + +err_uar_free: + hgrnic_uar_free(dev, &dev->driver_uar); + +err_uar_table_free: + hgrnic_cleanup_uar_table(dev); + return err; +} + + + + +#define HANGU_FW_VER(major, minor, subminor) \ + (((u64) (major) << 32) | ((u64) (minor) << 16) | (u64) (subminor)) + +static struct { + u64 latest_fw; + u32 flags; +} hgrnic_hca_table[] = { + [HANGU_RNIC] = { .latest_fw = HANGU_FW_VER(1, 0, 0), + .flags = HGRNIC_FLAG_PCIE } +}; + +static int __hgrnic_init_one (struct pci_dev *pdev, int hca_type) { + int err; + struct hgrnic_dev *hgdev; + struct hgrnic_cq cq; + u8 i; + + printk(KERN_INFO PFX "Initializing %s\n", + pci_name(pdev)); + + err = pci_enable_device(pdev); + if (err) { + dev_err(&pdev->dev, "Cannot enable PCI device, " + "aborting.\n"); + return err; + } + + /** + * Check for BARs. We expect 0: 1MB, 2: 8MB + */ + if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM) || + pci_resource_len(pdev, 0) != 1 << 20) { + dev_err(&pdev->dev, "Missing HCRs, aborting.\n"); + err = -ENODEV; + goto err_disable_pdev; + } + if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) { + dev_err(&pdev->dev, "Missing UAR, aborting.\n"); + err = -ENODEV; + goto err_disable_pdev; + } + + /** + * Set IORESOURCE_BUSY. From now on, BAR resources is dedicated + * to this driver. + */ + err = pci_request_regions(pdev, DRV_NAME); + if (err) { + dev_err(&pdev->dev, "Cannot obtain PCI resources, " + "aborting.\n"); + goto err_disable_pdev; + } + + /** + * Set PCIe device as a master device, which could execute + * DMA ops later. + */ + pci_set_master(pdev); + + /** + * Set DMA mask which PCIe device uses. + */ + err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); + if (err) { + dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask.\n"); + err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); + if (err) { + dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting.\n"); + goto err_free_res; + } + } + err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); + if (err) { + dev_warn(&pdev->dev, "Warning: couldn't set 64-bit " + "consistent PCI DMA mask.\n"); + err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); + if (err) { + dev_err(&pdev->dev, "Can't set consistent PCI DMA mask, " + "aborting.\n"); + goto err_free_res; + } + } + + /** + * We can handle large RDMA requests, so allow larger segments. + * !DEBUG: We don't need it now, maybe fix when debugging. + */ + // dma_set_max_seg_size(&pdev->dev, 1024 * 1024 * 1024); + + hgdev = ib_alloc_device(hgrnic_dev, ib_dev); + if (!hgdev) { + dev_err(&pdev->dev, "Device struct alloc failed, " + "aborting.\n"); + err = -ENOMEM; + goto err_free_res; + } + hgdev->pdev = pdev; + hgdev->hgrnic_flags = hgrnic_hca_table[hca_type].flags; + + /** + * Allocate virtual address to pcie BAR0 space, and allocate + * memory for mailbox. + */ + err = hgrnic_cmd_init(hgdev); + if (err) { + hgrnic_err(hgdev, "Failed to init command interface, aborting.\n"); + goto err_free_dev; + } + + err = hgrnic_tune_pci(hgdev); + if (err) { + goto err_cmd; + } + + hgrnic_init_en_register(hgdev); + + if (config_rdma) { + + printk(KERN_INFO PFX "Start hgrnic_init_hca.\n"); + err = hgrnic_init_hca(hgdev); + if (err) { + goto err_cmd; + } + + printk(KERN_INFO PFX "Start hgrnic_setup_hca.\n"); + err = hgrnic_setup_hca(hgdev); + if (err) { + goto err_close; + } + + /* allocate cq0 in kernel space */ + hgrnic_init_cq(hgdev, 32, NULL, hgdev->driver_pd.pd_num, &cq); + + printk(KERN_INFO PFX "Start hgrnic_register_device.\n"); + err = hgrnic_register_device(hgdev); + if (err) { + goto err_cleanup; + } + } else { + printk(KERN_INFO PFX "RDMA function unconfigured.\n"); + } + + printk(KERN_INFO PFX "Start pci_set_drvdata.\n"); + pci_set_drvdata(pdev, hgdev); + + hgdev->hca_type = hca_type; + hgdev->active = true; + for (i = 0; i < HG_GID_SIZE; ++i) { + hgdev->gid[i] = i; + } + + return 0; + +err_cleanup: + hgrnic_cleanup_qp_table(hgdev); + hgrnic_cleanup_cq_table(hgdev); + + hgrnic_pd_free(hgdev, &hgdev->driver_pd); + + hgrnic_cleanup_mr_table(hgdev); + hgrnic_cleanup_pd_table(hgdev); + hgrnic_cleanup_uar_table(hgdev); + +err_close: + hgrnic_free_icms(hgdev); + hgrnic_CLOSE_HCA(hgdev); + +err_cmd: + hgrnic_cmd_cleanup(hgdev); + +err_free_dev: + ib_dealloc_device(&hgdev->ib_dev); + +err_free_res: + pci_release_regions(pdev); + +err_disable_pdev: + pci_disable_device(pdev); + pci_set_drvdata(pdev, NULL); + return err; +} + + + + +static void __hgrnic_remove_one (struct pci_dev *pdev) { + struct hgrnic_dev *hgdev = pci_get_drvdata(pdev); + + if (hgdev) { + + if (config_rdma) { + printk(KERN_INFO PFX "HGRNIC (IB) driver has been removed. Bye Bye!\n"); + + ib_unregister_device(&hgdev->ib_dev); + + hgrnic_cleanup_qp_table(hgdev); + hgrnic_cleanup_cq_table(hgdev); + hgrnic_pd_free(hgdev, &hgdev->driver_pd); + hgrnic_cleanup_mr_table(hgdev); + hgrnic_cleanup_pd_table(hgdev); + hgrnic_cleanup_uar_table(hgdev); + + hgrnic_free_icms(hgdev); + hgrnic_CLOSE_HCA(hgdev); + } else { + printk(KERN_INFO PFX "HGRNIC (Base) driver has been removed. Bye Bye!\n"); + } + + hgrnic_cmd_cleanup(hgdev); + + ib_dealloc_device(&hgdev->ib_dev); + + pci_release_regions(pdev); + pci_disable_device(pdev); + + pci_set_drvdata(pdev, NULL); + } +} + +int __hgrnic_restart_one (struct pci_dev *pdev) { + struct hgrnic_dev *hgdev; + int hca_type; + + hgdev = pci_get_drvdata(pdev); + if (!hgdev) + return -ENODEV; + hca_type = hgdev->hca_type; + __hgrnic_remove_one(pdev); + return __hgrnic_init_one(pdev, hca_type); +} + +/** + * @description: + * Called when HCA or driver up to initialize the device. + */ +static int hgrnic_init_one (struct pci_dev *pdev, const struct pci_device_id *id) { + int ret; + + mutex_lock(&hgrnic_device_mutex); + + printk_once(KERN_INFO "%s", hgrnic_version); + + if (id->driver_data >= ARRAY_SIZE(hgrnic_hca_table)) { + printk(KERN_ERR PFX "%s has invalid driver data %lx\n", + pci_name(pdev), id->driver_data); + mutex_unlock(&hgrnic_device_mutex); + return -ENODEV; + } + + ret = __hgrnic_init_one(pdev, id->driver_data); + + mutex_unlock(&hgrnic_device_mutex); + + return ret; +} + +/** + * @description: + * Called when Driver or HCA removed. + */ +static void hgrnic_remove_one (struct pci_dev *pdev) { + mutex_lock(&hgrnic_device_mutex); + __hgrnic_remove_one(pdev); + mutex_unlock(&hgrnic_device_mutex); +} + +static const struct pci_device_id hgrnic_pci_table[] = { + { PCI_DEVICE(PCI_VENDOR_ID_ICT, PCI_DEVICE_ID_ICT_HANGU_RNIC), + .driver_data = HANGU_RNIC }, + { 0, } +}; + +MODULE_DEVICE_TABLE(pci, hgrnic_pci_table); + +static struct pci_driver hgrnic_driver = { + .name = DRV_NAME, + .id_table = hgrnic_pci_table, + .probe = hgrnic_init_one, + .remove = hgrnic_remove_one, +}; + +static void __init __hgrnic_check_profile_val (const char *name, + int *pval, int pval_default) { + /* value must be positive and power of 2 */ + int old_pval = *pval; + + if (old_pval <= 0) { + *pval = pval_default; + } else { + *pval = roundup_pow_of_two(old_pval); + } + + if (old_pval != *pval) { + printk(KERN_WARNING PFX "Invalid value %d for %s in module parameter.\n", + old_pval, name); + printk(KERN_WARNING PFX "Corrected %s to %d.\n", name, *pval); + } +} + +#define hgrnic_check_profile_val(name, default) \ + __hgrnic_check_profile_val(#name, &hca_profile.name, default) + +/** + * @description: + * Validate parameters of resource size. + */ +static void __init hgrnic_validate_profile (void) { + hgrnic_check_profile_val(num_qp , HGRNIC_DEFAULT_NUM_QP); + hgrnic_check_profile_val(num_cq , HGRNIC_DEFAULT_NUM_CQ); + hgrnic_check_profile_val(num_mpt, HGRNIC_DEFAULT_NUM_MPT); + hgrnic_check_profile_val(num_mtt, HGRNIC_DEFAULT_NUM_MTT); + + // if ((log_mtts_per_seg < 1) || (log_mtts_per_seg > 5)) { + // printk(KERN_WARNING PFX "bad log_mtts_per_seg (%d). Using default - %d\n", + // log_mtts_per_seg, ilog2(HGRNIC_MTT_SEG_SIZE / 8)); + // log_mtts_per_seg = ilog2(HGRNIC_MTT_SEG_SIZE / 8); + // } +} + +static int __init hgrnic_init (void) { + int ret; + + hgrnic_validate_profile(); + + ret = pci_register_driver(&hgrnic_driver); + if (ret < 0) + return ret; + + return 0; +} + +static void __exit hgrnic_cleanup (void) { + pci_unregister_driver(&hgrnic_driver); +} + +module_init(hgrnic_init); +module_exit(hgrnic_cleanup); diff --git a/ETH-PLUS_Jingzhao/JingZhao2/software/drivers/ib_hgrnic/hgrnic_mr.c b/ETH-PLUS_Jingzhao/JingZhao2/software/drivers/ib_hgrnic/hgrnic_mr.c new file mode 100644 index 0000000000000000000000000000000000000000..df79087624f7a272ab6a84ac16470ae42449f4e5 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/software/drivers/ib_hgrnic/hgrnic_mr.c @@ -0,0 +1,516 @@ +/************************************************************** + * @author Kang Ning, NCIC, ICT, CAS + * @date 2021.09.08 + * @file hgrnic_mr.c + * @note Functions related to Memory region. + *************************************************************/ + +#include +#include + +#include "hgrnic_dev.h" +#include "hgrnic_cmd.h" +#include "hgrnic_icm.h" + +/* + * Must be packed because mtt_seg is 64 bits but only aligned to 32 bits. + */ +struct hgrnic_mpt_entry { + __be32 flags; + __be32 page_size; + __be32 key; + __be32 pd; + __be64 start; + __be64 length; + __be32 lkey; + __be32 window_count; + __be32 window_count_limit; + __be64 mtt_seg; + __be32 mtt_sz; + u32 reserved[2]; +} __packed; + +#define HGRNIC_MPT_FLAG_SW_OWNS (0xfUL << 28) +#define HGRNIC_MPT_FLAG_MIO (1 << 17) +#define HGRNIC_MPT_FLAG_BIND_ENABLE (1 << 15) +#define HGRNIC_MPT_FLAG_PHYSICAL (1 << 9) +#define HGRNIC_MPT_FLAG_REGION (1 << 8) + +#define HGRNIC_MTT_FLAG_PRESENT 1 + +#define HGRNIC_MPT_STATUS_SW 0xF0 +#define HGRNIC_MPT_STATUS_HW 0x00 + +/* + * Buddy allocator for MTT segments (currently not very efficient + * since it doesn't keep a free list and just searches linearly + * through the bitmaps) + */ +static u32 hgrnic_buddy_alloc (struct hgrnic_buddy *buddy, int order) +{ + int o; + int m; /* Number of elements in bits[o] array */ + u32 seg; + + spin_lock(&buddy->lock); + + for (o = order; o <= buddy->max_order; ++o) + if (buddy->num_free[o]) { + m = 1 << (buddy->max_order - o); + seg = find_first_bit(buddy->bits[o], m); + if (seg < m) /* if seg == m, not find set bit */ + goto found; + } + + spin_unlock(&buddy->lock); + return -1; + + found: + clear_bit(seg, buddy->bits[o]); + --buddy->num_free[o]; + + while (o > order) { + --o; + seg <<= 1; + set_bit(seg ^ 1, buddy->bits[o]); // ^ 1: same as + 1 + ++buddy->num_free[o]; + } + + spin_unlock(&buddy->lock); + + seg <<= order; + + return seg; +} + +static void hgrnic_buddy_free(struct hgrnic_buddy *buddy, u32 seg, int order) +{ + seg >>= order; + + spin_lock(&buddy->lock); + + while (test_bit(seg ^ 1, buddy->bits[order])) { + clear_bit(seg ^ 1, buddy->bits[order]); + --buddy->num_free[order]; + seg >>= 1; + ++order; + } + + set_bit(seg, buddy->bits[order]); + ++buddy->num_free[order]; + + spin_unlock(&buddy->lock); +} + +/** + * @note Init buddy allocator for mtt resources. + */ +static int hgrnic_buddy_init (struct hgrnic_buddy *buddy, int max_order) +{ + int i, s; + + buddy->max_order = max_order; + spin_lock_init(&buddy->lock); + + buddy->bits = kcalloc(buddy->max_order + 1, sizeof(long *), + GFP_KERNEL); + buddy->num_free = kcalloc((buddy->max_order + 1), sizeof *buddy->num_free, + GFP_KERNEL); + if (!buddy->bits || !buddy->num_free) + goto err_out; + + for (i = 0; i <= buddy->max_order; ++i) { + s = BITS_TO_LONGS(1 << (buddy->max_order - i)); + buddy->bits[i] = kmalloc_array(s, sizeof(long), GFP_KERNEL); + if (!buddy->bits[i]) + goto err_out_free; + + bitmap_zero(buddy->bits[i], + 1 << (buddy->max_order - i)); + } + + set_bit(0, buddy->bits[buddy->max_order]); + buddy->num_free[buddy->max_order] = 1; + + return 0; + +err_out_free: + for (i = 0; i <= buddy->max_order; ++i) + kfree(buddy->bits[i]); + +err_out: + kfree(buddy->bits); + kfree(buddy->num_free); + + return -ENOMEM; +} + +/** + * @note Clean up buddy allocator for mtt resources. + */ +static void hgrnic_buddy_cleanup (struct hgrnic_buddy *buddy) +{ + int i; + + for (i = 0; i <= buddy->max_order; ++i) + kfree(buddy->bits[i]); + + kfree(buddy->bits); + kfree(buddy->num_free); +} + +/** + * @note This Func completes the following things: + * 1. Allocate a range of ICM virtual addr for mtt, + * 2. Allocate memories associated with ICM virtual addr, and + * 3. Write ICM addr mapping for MTT resources. + * @param order log_size of allocated mtt entry + * @return start index of MTT resources. (log_len is order) + */ +static u32 hgrnic_alloc_mtt_range (struct hgrnic_dev *dev, int order, + struct hgrnic_buddy *buddy) +{ + u32 seg = hgrnic_buddy_alloc(buddy, order); + if (seg == -1) + return -1; + + if (hgrnic_reg_icm_range(dev, dev->mr_table.mtt_table, seg, + seg + (1 << order) - 1, TPT_REGION)) { + hgrnic_buddy_free(buddy, seg, order); + seg = -1; + } + + return seg; +} + +/** + * @note Allocate Space (ICM space) for MTT storage. + * This function Write ICM to HCA. The actually + * allocated size may not be param size. + * + * @param size The required size, the actual allocated + * size must be the power of 2. + */ +static struct hgrnic_mtt *__hgrnic_alloc_mtt (struct hgrnic_dev *dev, + int size, + struct hgrnic_buddy *buddy) +{ + struct hgrnic_mtt *mtt; + int i; + + if (size <= 0) + return ERR_PTR(-EINVAL); + + mtt = kmalloc(sizeof *mtt, GFP_KERNEL); + if (!mtt) + return ERR_PTR(-ENOMEM); + + // Change size into log num + mtt->buddy = buddy; + mtt->order = 0; + for (i = 1; i < size; i <<= 1) // dev->limits.mtt_seg_size / 8 + ++mtt->order; + + mtt->first_index = hgrnic_alloc_mtt_range(dev, mtt->order, buddy); + if (mtt->first_index == -1) { + kfree(mtt); + return ERR_PTR(-ENOMEM); + } + + return mtt; +} + +/** + * @note Allocate MTT from mtt_buddy table + */ +struct hgrnic_mtt *hgrnic_alloc_mtt (struct hgrnic_dev *dev, int size) +{ + return __hgrnic_alloc_mtt(dev, size, &dev->mr_table.mtt_buddy); +} + +/** + * @note Release MTT entries from MTT table (mtt_buddy). + */ +void hgrnic_free_mtt (struct hgrnic_dev *dev, struct hgrnic_mtt *mtt) +{ + if (!mtt) + return; + + hgrnic_buddy_free(mtt->buddy, mtt->first_index, mtt->order); + + hgrnic_unreg_icm_range(dev, dev->mr_table.mtt_table, + mtt->first_index, + mtt->first_index + (1 << mtt->order) - 1, TPT_REGION); + + kfree(mtt); +} + +/** + * @note Write MTT entry into HCA. This function includes + * data layout in mailbox of MTT. + * @param start_index start mtt index + * @param list_len MTT entry number + */ +static int __hgrnic_write_mtt (struct hgrnic_dev *dev, struct hgrnic_mtt *mtt, + int start_index, u64 *buffer_list, int list_len) +{ + struct hgrnic_mailbox *mailbox; + __be64 *mtt_entry; + int err = 0; + int i; + + mailbox = hgrnic_alloc_mailbox(dev, GFP_KERNEL); + if (IS_ERR(mailbox)) { + return PTR_ERR(mailbox); + } + mtt_entry = mailbox->buf; + + while (list_len > 0) { + mtt_entry[0] = 0; + mtt_entry[1] = 0; + mtt_entry[2] = 0; + mtt_entry[3] = cpu_to_be64(start_index); + + printk(KERN_INFO PFX "start_index: 0x%x\n", start_index); + for (i = 0; i < list_len && i < HGRNIC_MAILBOX_SIZE / 8 - 4; i+=4) { + mtt_entry[i + 4] = (i+3) < list_len ? + cpu_to_be64(buffer_list[i+3]) : 0; + mtt_entry[i + 5] = (i+2) < list_len ? + cpu_to_be64(buffer_list[i+2]) : 0; + mtt_entry[i + 6] = (i+1) < list_len ? + cpu_to_be64(buffer_list[i+1]) : 0; + mtt_entry[i + 7] = cpu_to_be64(buffer_list[i]); + printk(KERN_INFO PFX "mtt_entry: 0x%llx 0x%llx 0x%llx 0x%llx\n", + be64_to_cpu(mtt_entry[i + 4]), + be64_to_cpu(mtt_entry[i + 5]), + be64_to_cpu(mtt_entry[i + 6]), + be64_to_cpu(mtt_entry[i + 7])); + + } + + err = hgrnic_WRITE_MTT(dev, mailbox, list_len); // i + 4 + if (err) { + hgrnic_warn(dev, "WRITE_MTT failed (%d)\n", err); + goto out; + } + + list_len -= i; + start_index += i; + buffer_list += i; + } + +out: + hgrnic_free_mailbox(dev, mailbox); + return err; +} + +int hgrnic_write_mtt_size(struct hgrnic_dev *dev) +{ + /* All MTTs must fit in the same page. */ + return (PAGE_SIZE / sizeof (u64)); +} + + +/** + * @note Write MTT to HCA. + */ +int hgrnic_write_mtt (struct hgrnic_dev *dev, struct hgrnic_mtt *mtt, + int start_index, u64 *buffer_list, int list_len) +{ + return __hgrnic_write_mtt(dev, mtt, start_index, buffer_list, list_len); +} + + +/** + * @note Allocate memory region. + * 1. Allocate MPT and write ICM mapping to HCA; + * 2. Write MPT entry to HCA. + * + * @param buffer_size_shift page size the memory region owns. + * @param iova start virt addr of MR + * @param total_size total size of MR + * @param mr MTT may be included here + */ +int hgrnic_mr_alloc (struct hgrnic_dev *dev, u32 pd, int buffer_size_shift, + u64 iova, u64 total_size, u32 access, struct hgrnic_mr *mr) +{ + struct hgrnic_mailbox *mailbox; + struct hgrnic_mpt_entry *mpt_entry; + u32 key; + int err; + + + WARN_ON(buffer_size_shift >= 32); + + key = hgrnic_alloc(&dev->mr_table.mpt_alloc); + if (key == -1) + return -ENOMEM; + + mr->ibmr.rkey = mr->ibmr.lkey = key; + + err = hgrnic_reg_icm(dev, dev->mr_table.mpt_table, + key, TPT_REGION); + if (err) + goto err_out_mpt_free; + + + mailbox = hgrnic_alloc_mailbox(dev, GFP_KERNEL); + if (IS_ERR(mailbox)) { + err = PTR_ERR(mailbox); + goto err_out_table; + } + mpt_entry = mailbox->buf; + + mpt_entry->flags = cpu_to_be32(HGRNIC_MPT_FLAG_SW_OWNS | + HGRNIC_MPT_FLAG_MIO | + HGRNIC_MPT_FLAG_REGION | + access); + + mpt_entry->page_size = cpu_to_be32(1 << buffer_size_shift); /* !TODO: Checkout this variable */ + mpt_entry->key = cpu_to_be32(key); + mpt_entry->pd = cpu_to_be32(pd); + mpt_entry->start = cpu_to_be64(iova); + mpt_entry->length = cpu_to_be64(total_size); + + memset(&mpt_entry->lkey, 0, + sizeof *mpt_entry - offsetof(struct hgrnic_mpt_entry, lkey)); + + if (mr->mtt) + mpt_entry->mtt_seg = cpu_to_be64(mr->mtt->first_index); + + err = hgrnic_SW2HW_MPT(dev, mailbox, + key & (dev->limits.num_mpts - 1)); + if (err) { + hgrnic_warn(dev, "SW2HW_MPT failed (%d)\n", err); + goto err_out_mailbox; + } + hgrnic_dump("0x%x", be32_to_cpu(mpt_entry->flags )); + hgrnic_dump("0x%x", be32_to_cpu(mpt_entry->page_size)); + hgrnic_dump("0x%x", be32_to_cpu(mpt_entry->key )); + hgrnic_dump("0x%x", be32_to_cpu(mpt_entry->pd )); + hgrnic_dump("0x%llx", be64_to_cpu(mpt_entry->start )); + hgrnic_dump("0x%llx", be64_to_cpu(mpt_entry->length )); + hgrnic_dump("0x%llx", be64_to_cpu(mpt_entry->mtt_seg )); + + hgrnic_free_mailbox(dev, mailbox); + return err; + +err_out_mailbox: + hgrnic_free_mailbox(dev, mailbox); + +err_out_table: + hgrnic_unreg_icm(dev, dev->mr_table.mpt_table, key, TPT_REGION); + +err_out_mpt_free: + hgrnic_free(&dev->mr_table.mpt_alloc, key); + return err; +} + +/** + * @note Allocate Memory (no translation). + */ +int hgrnic_mr_alloc_notrans (struct hgrnic_dev *dev, + u32 pd, u32 access, + struct hgrnic_mr *mr) +{ + mr->mtt = NULL; + return hgrnic_mr_alloc(dev, pd, 12, 0, ~0ULL, access, mr); +} + +/** + * @note Allocate Memory (With mtt). + * + * @param buffer_size_shift Size of page in log for + * this MR (MPT entry) + */ +int hgrnic_mr_alloc_phys (struct hgrnic_dev *dev, u32 pd, + u64 *buffer_list, int buffer_size_shift, + int list_len, u64 iova, u64 total_size, + u32 access, struct hgrnic_mr *mr) +{ + int err; + + mr->mtt = hgrnic_alloc_mtt(dev, list_len); + if (IS_ERR(mr->mtt)) + return PTR_ERR(mr->mtt); + + /* Write MTT -> HCA */ + err = hgrnic_write_mtt(dev, mr->mtt, mr->mtt->first_index, buffer_list, list_len); + printk(KERN_INFO PFX "hgrnic_write_mtt: err %d\n", err); + if (err) + goto free_mtt; + + /* Allocate MPT && (Write MPT -> HCA) */ + err = hgrnic_mr_alloc(dev, pd, buffer_size_shift, iova, + total_size, access, mr); + printk(KERN_INFO PFX "hgrnic_mr_alloc: mr->lkey 0x%x, 0x%x\n", mr->ibmr.lkey, mr->mtt->first_index); + if (err) + goto free_mtt; + + return 0; + +free_mtt: + hgrnic_free_mtt(dev, mr->mtt); + return err; +} + +/* Free mr id and its ICM space */ +static void hgrnic_free_region (struct hgrnic_dev *dev, u32 lkey) +{ + hgrnic_unreg_icm(dev, dev->mr_table.mpt_table, + lkey, TPT_REGION); + + hgrnic_free(&dev->mr_table.mpt_alloc, lkey); +} + +/** + * @note + * 1. Write MPT cancel to HCA; + * 2. Free reated MPT resource and unmmap cooresponding ICM space; + * 3. Free related mtt resource and unmmap cooresponding ICM space. + */ +void hgrnic_free_mr(struct hgrnic_dev *dev, struct hgrnic_mr *mr) +{ + int err; + + err = hgrnic_HW2SW_MPT(dev, + mr->ibmr.lkey & (dev->limits.num_mpts - 1)); + if (err) + hgrnic_warn(dev, "HW2SW_MPT failed (%d)\n", err); + + hgrnic_free_region(dev, mr->ibmr.lkey); + hgrnic_free_mtt(dev, mr->mtt); +} + +/** + * @note Initialize Memory region resources (MPT & MTT). + * 1. Init resource table. + */ +int hgrnic_init_mr_table (struct hgrnic_dev *dev) +{ + int err; + + err = hgrnic_alloc_init(&dev->mr_table.mpt_alloc, + dev->limits.num_mpts, + ~0); + if (err) + return err; + + err = hgrnic_buddy_init(&dev->mr_table.mtt_buddy, + fls(dev->limits.num_mtt_segs - 1)); + if (err) + goto err_mtt_buddy; + + return 0; + +err_mtt_buddy: + hgrnic_alloc_cleanup(&dev->mr_table.mpt_alloc); + + return err; +} + +void hgrnic_cleanup_mr_table(struct hgrnic_dev *dev) +{ + hgrnic_buddy_cleanup(&dev->mr_table.mtt_buddy); + hgrnic_alloc_cleanup(&dev->mr_table.mpt_alloc); +} diff --git a/ETH-PLUS_Jingzhao/JingZhao2/software/drivers/ib_hgrnic/hgrnic_pd.c b/ETH-PLUS_Jingzhao/JingZhao2/software/drivers/ib_hgrnic/hgrnic_pd.c new file mode 100644 index 0000000000000000000000000000000000000000..96a4a972428b8fce449269caafa6bc432d01934f --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/software/drivers/ib_hgrnic/hgrnic_pd.c @@ -0,0 +1,39 @@ +/************************************************************** + * @author Kang Ning, NCIC, ICT, CAS + * @date 2021.09.08 + * @file hgrnic_pd.c + * @note Initialize, Allocate, Free and Clean Up protection domain. + *************************************************************/ + +#include + +#include "hgrnic_dev.h" + +int hgrnic_pd_alloc (struct hgrnic_dev *dev, + int privileged, struct hgrnic_pd *pd) +{ + pd->privileged = privileged; + + pd->pd_num = hgrnic_alloc(&dev->pd_table.alloc); + if (pd->pd_num == -1) + return -ENOMEM; + + return 0; +} + +void hgrnic_pd_free(struct hgrnic_dev *dev, struct hgrnic_pd *pd) +{ + hgrnic_free(&dev->pd_table.alloc, pd->pd_num); +} + +// Maximum PD number is 2^24. +int hgrnic_init_pd_table(struct hgrnic_dev *dev) { + return hgrnic_alloc_init(&dev->pd_table.alloc, + dev->limits.num_pds, + (1 << 24) - 1); +} + +void hgrnic_cleanup_pd_table(struct hgrnic_dev *dev) { + /* XXX check if any PDs are still allocated? */ + hgrnic_alloc_cleanup(&dev->pd_table.alloc); +} diff --git a/ETH-PLUS_Jingzhao/JingZhao2/software/drivers/ib_hgrnic/hgrnic_provider.c b/ETH-PLUS_Jingzhao/JingZhao2/software/drivers/ib_hgrnic/hgrnic_provider.c new file mode 100644 index 0000000000000000000000000000000000000000..688bf98544a82cd44c877c0b121d4efdd11ad8d3 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/software/drivers/ib_hgrnic/hgrnic_provider.c @@ -0,0 +1,853 @@ +/************************************************************** + * @author Kang Ning, NCIC, ICT, CAS + * @date 2021.09.08 + * @file hgrnic_provider.c + * @note Functions & Data struct related to interface with ib_uverbs. + *************************************************************/ + +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include "hgrnic_dev.h" +#include "hgrnic_cmd.h" +#include +#include "hgrnic_icm.h" + +/** + * @description: + * API function. + * Query device information. + */ +static int hgrnic_query_device (struct ib_device *ibdev, + struct ib_device_attr *props, + struct ib_udata *uhw) +{ + struct hgrnic_dev *mdev = to_hgdev(ibdev); + + if (uhw->inlen || uhw->outlen) + return -EINVAL; + + memset(props, 0, sizeof *props); + + props->vendor_id = PCI_VENDOR_ID_ICT; + props->vendor_part_id = HANGU_RNIC; + props->max_mr_size = ~0ull; + props->page_size_cap = mdev->limits.page_size_cap; + props->max_qp = mdev->limits.num_qps - mdev->limits.reserved_qps; + props->max_qp_wr = mdev->limits.max_wqes; + props->max_send_sge = mdev->limits.max_sg; + props->max_recv_sge = mdev->limits.max_sg; + props->max_cq = mdev->limits.num_cqs - mdev->limits.reserved_cqs; + props->max_cqe = mdev->limits.max_cqes; + props->max_mr = mdev->limits.num_mpts - mdev->limits.reserved_mrws; + props->max_pd = mdev->limits.num_pds - mdev->limits.reserved_pds; + props->local_ca_ack_delay = mdev->limits.local_ca_ack_delay; + props->max_pkeys = mdev->limits.pkey_table_len; + props->atomic_cap = IB_ATOMIC_NONE; + + /* reserved */ + props->fw_ver = 0; + props->device_cap_flags = 0; + props->hw_ver = 1; // Not involved in design + props->sys_image_guid = 0; // Not involved in design + props->max_sge_rd = 0; + props->max_qp_rd_atom = 0; + props->max_qp_init_rd_atom = 0; + props->max_res_rd_atom = 0; + props->max_srq = 0; + props->max_srq_wr = 0; + props->max_srq_sge = 0; + props->max_mcast_grp = 0; + props->max_mcast_qp_attach = 0; + props->max_total_mcast_qp_attach = 0; + props->max_map_per_fmr = 0; + + return 0; +} + +/** + * @description: + * API function. + * Query port information. + */ +static int hgrnic_query_port (struct ib_device *ibdev, u8 port, + struct ib_port_attr *props) +{ +#define DEVICE_LID 0x1010 + + props->max_msg_sz = 0x80000000; + props->lid = DEVICE_LID; + props->state = IB_PORT_ACTIVE; + + // 1: return "SLEEP"; + // 2: return "POLLING"; + // 3: return "DISABLED"; + // 4: return "PORT_CONFIGURATION TRAINNING"; + // 5: return "LINK_UP"; + // 6: return "LINK_ERROR_RECOVERY"; + // 7: return "PHY TEST"; + props->phys_state = 5; // According to ib_core, 5 is link up + + // 1: return "1"; + // 2: return "4"; + // 4: return "8"; + // 8: return "12"; + props->active_width = 2; + + // 1: 2.5 Gbps"; + // 2: 5.0 Gbps"; + // 4: 10.0 Gbps"; + props->active_speed = 4; + + props->max_mtu = IB_MTU_4096; + props->active_mtu = IB_MTU_4096; + + // 1: return "1"; + // 2: return "2"; + // 3: return "4"; + // 4: return "8"; + // 5: return "15"; + props->max_vl_num = 0; + + props->gid_tbl_len = 1; + + /* Reserved */ + props->subnet_prefix = 0; + props->lmc = 0; + props->sm_lid = 0; + props->sm_sl = 0; + props->subnet_timeout = 0; + props->init_type_reply = 0; + props->port_cap_flags = 0; + props->pkey_tbl_len = 1; + props->bad_pkey_cntr = 0; + props->qkey_viol_cntr = 0; + + return 0; +} + +static int hgrnic_modify_device (struct ib_device *ibdev, int mask, + struct ib_device_modify *props) +{ + if (mask & ~IB_DEVICE_MODIFY_NODE_DESC) + return -EOPNOTSUPP; + + if (mask & IB_DEVICE_MODIFY_NODE_DESC) { + if (mutex_lock_interruptible(&to_hgdev(ibdev)->cap_mask_mutex)) + return -ERESTARTSYS; + memcpy(ibdev->node_desc, props->node_desc, + IB_DEVICE_NODE_DESC_MAX); + mutex_unlock(&to_hgdev(ibdev)->cap_mask_mutex); + } + + return 0; +} + + +/** + * @description: + * API function. + * Query pkey information. + */ +static int hgrnic_query_pkey(struct ib_device *ibdev, + u8 port, u16 index, u16 *pkey) +{ + *pkey = 0x0001; + + return 0; +} + +/** + * @description: + * API function. + * Allocate protection domain. + * This API calls hgrnic_pd_alloc directly. + */ +static int hgrnic_alloc_pd (struct ib_pd *ibpd, struct ib_udata *udata) +{ + struct ib_device *ibdev = ibpd->device; + struct hgrnic_pd *pd = to_hgpd(ibpd); + int err; + + err = hgrnic_pd_alloc(to_hgdev(ibdev), !udata, pd); + if (err) + return err; + + if (udata) { + if (ib_copy_to_udata(udata, &pd->pd_num, sizeof (__u32))) { + hgrnic_pd_free(to_hgdev(ibdev), pd); + return -EFAULT; + } + } + + return 0; +} + +/** + * @description: + * API function. + * Deallocate protection domain. + * This API calls hgrnic_pd_free directly. + */ +static void hgrnic_dealloc_pd (struct ib_pd *pd, + struct ib_udata *udata) { + hgrnic_pd_free(to_hgdev(pd->device), to_hgpd(pd)); +} + + +/** + * @description: + * API function. Called by driver ib_core (or ib_uverbs ?? !TODO) + * Create QP resources. + */ +struct ib_qp *hgrnic_create_qp (struct ib_pd *pd, + struct ib_qp_init_attr *init_attr, + struct ib_udata *udata) +{ + + struct hgrnic_create_qp ucmd; + struct hgrnic_qp *qp; + int err; + + status_dump("enter\n"); + + if (init_attr->create_flags) { + printk(KERN_INFO PFX "Fail to create qp, ENIVAL\n"); + return ERR_PTR(-EINVAL); + } + + switch (init_attr->qp_type) { + case IB_QPT_RC: + case IB_QPT_UC: + case IB_QPT_UD: { + qp = kzalloc(sizeof(*qp), GFP_KERNEL); + if (!qp) { + printk(KERN_INFO PFX "Fail to create qp, ENOMEM\n"); + return ERR_PTR(-ENOMEM); + } + + + if (udata) { + if (ib_copy_from_udata(&ucmd, udata, sizeof ucmd)) { + kfree(qp); + printk(KERN_INFO PFX "Fail to create qp, EFAULT\n"); + return ERR_PTR(-EFAULT); + } + qp->rq.mr.ibmr.lkey = ucmd.rq_lkey; + qp->sq.mr.ibmr.lkey = ucmd.sq_lkey; + } + + err = hgrnic_alloc_qp(to_hgdev(pd->device), to_hgpd(pd), + to_hgcq(init_attr->send_cq), + to_hgcq(init_attr->recv_cq), + init_attr->qp_type, + &init_attr->cap, qp, udata); + qp->rq.mr.ibmr.length = qp->rq.que_size; + qp->sq.mr.ibmr.length = qp->sq.que_size; + qp->ibqp.qp_num = qp->qpn; + break; + } + case IB_QPT_SMI: + case IB_QPT_GSI: + default: + printk(KERN_INFO PFX "hgrnic_create_qp: Don't support Special QPs.\n"); + printk(KERN_INFO PFX "Fail to create qp, ENOSYS\n"); + return ERR_PTR(-ENOSYS); + } + + if (err) { + kfree(qp); + return ERR_PTR(err); + } + + /* pass to user space to assign to hgrnic_qp in user space */ + init_attr->cap.max_send_wr = qp->sq.max; + init_attr->cap.max_recv_wr = qp->rq.max; + init_attr->cap.max_send_sge = qp->sq.max_gs; + init_attr->cap.max_recv_sge = qp->rq.max_gs; + init_attr->cap.max_inline_data = qp->max_inline_data; + + + if(NULL == &qp->ibqp) { + status_dump("NULL QP Error\n"); + } + status_dump("Normal\n"); + + status_dump("exit\n"); + return &qp->ibqp; +} + +static int hgrnic_alloc_ucontext(struct ib_ucontext *uctx, + struct ib_udata *udata) +{ + struct hgrnic_ucontext *context = to_hgucontext(uctx); + struct hgrnic_alloc_ucontext_resp uresp = {}; + struct ib_device *ibdev = uctx->device; + int err; + + if (!(to_hgdev(ibdev)->active)) + return -EAGAIN; + + uresp.qp_tab_size = to_hgdev(ibdev)->limits.num_qps; + + err = hgrnic_uar_alloc(to_hgdev(ibdev), &context->uar); + if (err) + return err; + + if (ib_copy_to_udata(udata, &uresp, sizeof(uresp))) { + hgrnic_uar_free(to_hgdev(ibdev), &context->uar); + return -EFAULT; + } + + return 0; +} + +static void hgrnic_dealloc_ucontext(struct ib_ucontext *context) +{ + hgrnic_uar_free(to_hgdev(context->device), &to_hgucontext(context)->uar); +} + +static int hgrnic_mmap_uar(struct ib_ucontext *context, + struct vm_area_struct *vma) +{ + if (vma->vm_end - vma->vm_start != PAGE_SIZE) + return -EINVAL; + + vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); + + if (io_remap_pfn_range(vma, vma->vm_start, + to_hgucontext(context)->uar.pfn, + PAGE_SIZE, vma->vm_page_prot)) + return -EAGAIN; + + return 0; +} + +static int hgrnic_destroy_qp(struct ib_qp *qp, struct ib_udata *udata) +{ + hgrnic_free_qp(to_hgdev(qp->device), to_hgqp(qp)); + kfree(to_hgqp(qp)); + return 0; +} + +/** + * @note If kernel space calls this function, it will allocate + * buffer for CQ. + */ +int hgrnic_create_cq(struct ib_cq *ibcq, + const struct ib_cq_init_attr *attr, + struct ib_udata *udata) +{ + struct ib_device *ibdev = ibcq->device; + int entries = attr->cqe; /* Required number of cqes in the cq */ + struct hgrnic_create_cq ucmd; + struct hgrnic_cq *cq; + int nent; + int err; + struct hgrnic_ucontext *context = rdma_udata_to_drv_context( + udata, struct hgrnic_ucontext, ibucontext); + + status_dump("enter"); + + if (attr->flags) + return -EINVAL; + + if (entries < 1 || entries > to_hgdev(ibdev)->limits.max_cqes) + return -EINVAL; + + cq = to_hgcq(ibcq); + + if (udata) { + if (ib_copy_from_udata(&ucmd, udata, sizeof(ucmd))) + return -EFAULT; + cq->buf.mr.ibmr.lkey = ucmd.lkey; + } + + /* find the most closest value in power of 2 */ + nent = roundup_pow_of_two(entries + 1); + + err = hgrnic_init_cq(to_hgdev(ibdev), nent, context, + udata ? ucmd.pdn : to_hgdev(ibdev)->driver_pd.pd_num, + cq); + if (err) + return err; + + if (udata && ib_copy_to_udata(udata, &cq->cqn, sizeof(__u32))) { + hgrnic_free_cq(to_hgdev(ibdev), cq); + return -EFAULT; + } + cq->resize_buf = NULL; + + status_dump("exit\n"); + return 0; +} + +static void hgrnic_destroy_cq(struct ib_cq *cq, struct ib_udata *udata) +{ + // printk(KERN_INFO PFX "Enter hgrnic_destroy_cq\n"); + hgrnic_free_cq(to_hgdev(cq->device), to_hgcq(cq)); + // printk(KERN_INFO PFX "Enter hgrnic_destroy_cq\n"); +} + +static struct ib_mr *hgrnic_get_dma_mr(struct ib_pd *pd, int acc) +{ + struct hgrnic_mr *mr; + int err; + + printk(KERN_INFO PFX "Enter hgrnic_get_dma_mr\n"); + mr = kmalloc(sizeof *mr, GFP_KERNEL); + if (!mr) + return ERR_PTR(-ENOMEM); + + err = hgrnic_mr_alloc_notrans(to_hgdev(pd->device), + to_hgpd(pd)->pd_num, + convert_access(acc), mr); + if (err) { + kfree(mr); + return ERR_PTR(err); + } + + mr->umem = NULL; + + printk(KERN_INFO PFX "Exit hgrnic_get_dma_mr\n"); + return &mr->ibmr; +} + +struct ib_mr *hgrnic_reg_user_mr(struct ib_pd *pd, u64 start, + u64 length, u64 virt, int acc, + struct ib_udata *udata) +{ + struct hgrnic_dev *dev = to_hgdev(pd->device); + struct sg_dma_page_iter sg_iter; + struct hgrnic_mr *mr; + struct hgrnic_reg_mr ucmd; + u64 *pages; + int n, i; + int err = 0; + int write_mtt_size; + + status_dump("Enter"); + printk(KERN_INFO PFX "start vaddr 0x%llx, length %lld\n", start, length); + if (udata->inlen < sizeof(ucmd) || + ib_copy_from_udata(&ucmd, udata, sizeof(ucmd))) + return ERR_PTR(-EFAULT); + + mr = kmalloc(sizeof *mr, GFP_KERNEL); + if (!mr) + return ERR_PTR(-ENOMEM); + + /* interface updated in later kernel version */ + mr->umem = ib_umem_get(udata, start, length, acc, + ucmd.mr_attrs & HGRNIC_MR_DMASYNC); + if (IS_ERR(mr->umem)) { + err = PTR_ERR(mr->umem); + goto err; + } + + n = ib_umem_num_pages(mr->umem); + + mr->mtt = hgrnic_alloc_mtt(dev, n); + if (IS_ERR(mr->mtt)) { + err = PTR_ERR(mr->mtt); + goto err_umem; + } + + pages = (u64 *) __get_free_page(GFP_KERNEL); + if (!pages) { + err = -ENOMEM; + goto err_mtt; + } + + i = 0; + n = mr->mtt->first_index; + + write_mtt_size = min(hgrnic_write_mtt_size(dev), (int) (PAGE_SIZE / sizeof *pages)); + + for_each_sg_dma_page(mr->umem->sg_head.sgl, &sg_iter, mr->umem->nmap, 0) { + pages[i++] = sg_page_iter_dma_address(&sg_iter); + printk(KERN_INFO PFX " paddr[%d] 0x%llx\n", i-1, pages[i-1]); + + /* + * Be friendly to write_mtt and pass it chunks + * of appropriate size. + */ + if (i == write_mtt_size) { + err = hgrnic_write_mtt(dev, mr->mtt, n, pages, i); + if (err) + goto mtt_done; + n += i; + i = 0; + } + } + + if (i) + err = hgrnic_write_mtt(dev, mr->mtt, n, pages, i); +mtt_done: + free_page((unsigned long) pages); + if (err) + goto err_mtt; + + err = hgrnic_mr_alloc(dev, to_hgpd(pd)->pd_num, PAGE_SHIFT, virt, length, + convert_access(acc), mr); + + if (err) + goto err_mtt; + + status_dump("exit\n\n"); + return &mr->ibmr; + +err_mtt: + hgrnic_free_mtt(dev, mr->mtt); + +err_umem: + ib_umem_release(mr->umem); + +err: + kfree(mr); + return ERR_PTR(err); +} + +static int hgrnic_dereg_mr(struct ib_mr *mr, struct ib_udata *udata) +{ + struct hgrnic_mr *hgmr = to_hgmr(mr); + + printk(KERN_INFO PFX "Enter hgrnic_dereg_mr\n"); + hgrnic_free_mr(to_hgdev(mr->device), hgmr); + ib_umem_release(hgmr->umem); + kfree(hgmr); + + printk(KERN_INFO PFX "Exit hgrnic_dereg_mr\n"); + return 0; +} + + + +static ssize_t hw_rev_show(struct device *device, + struct device_attribute *attr, char *buf) +{ + struct hgrnic_dev *dev = + rdma_device_to_drv_device(device, struct hgrnic_dev, ib_dev); + + return sprintf(buf, "%x\n", dev->rev_id); +} +static DEVICE_ATTR_RO(hw_rev); + +static ssize_t hca_type_show(struct device *device, + struct device_attribute *attr, + char *buf) +{ + struct hgrnic_dev *dev = + rdma_device_to_drv_device(device, struct hgrnic_dev, ib_dev); + + switch (dev->pdev->device) { + case PCI_DEVICE_ID_ICT_HANGU_RNIC: + return sprintf(buf, "HANGU_RNIC\n"); + default: + return sprintf(buf, "unknown\n"); + } +} +static DEVICE_ATTR_RO(hca_type); + +static ssize_t board_id_show(struct device *device, + struct device_attribute *attr, char *buf) +{ + struct hgrnic_dev *dev = + rdma_device_to_drv_device(device, struct hgrnic_dev, ib_dev); + + return sprintf(buf, "%lld\n", dev->board_id); +} +static DEVICE_ATTR_RO(board_id); + +static struct attribute *hgrnic_dev_attributes[] = { + &dev_attr_hw_rev.attr, + &dev_attr_hca_type.attr, + &dev_attr_board_id.attr, + NULL +}; + +static const struct attribute_group hgrnic_attr_group = { + .attrs = hgrnic_dev_attributes, +}; + + +static int hgrnic_port_immutable(struct ib_device *ibdev, u8 port_num, + struct ib_port_immutable *immutable) +{ + struct ib_port_attr attr; + int err; + + printk(KERN_INFO PFX "Enter hgrnic_port_immutable\n"); + immutable->core_cap_flags = RDMA_CORE_CAP_PROT_IB; + err = ib_query_port(ibdev, port_num, &attr); + if (err) + return err; + + immutable->pkey_tbl_len = attr.pkey_tbl_len; + immutable->gid_tbl_len = attr.gid_tbl_len; + immutable->max_mad_size = 0; + + printk(KERN_INFO PFX "Exit hgrnic_port_immutable\n"); + return 0; +} + +static int hgrnic_query_gid(struct ib_device *ibdev, u8 port, + int index, union ib_gid *gid) +{ + struct hgrnic_dev *dev = to_hgdev(ibdev); + // int i = 0; + + status_dump("enter"); + + memcpy(gid->raw, dev->gid, sizeof(dev->gid)); + + status_dump("exit\n\n"); + return 0; +} + + +static int hgrnic_alloc_resize_buf(struct hgrnic_dev *dev, struct hgrnic_cq *cq, + int entries) +{ + int ret; + + spin_lock_irq(&cq->lock); + if (cq->resize_buf) { + ret = -EBUSY; + goto unlock; + } + + cq->resize_buf = kmalloc(sizeof *cq->resize_buf, GFP_ATOMIC); + if (!cq->resize_buf) { + ret = -ENOMEM; + goto unlock; + } + + cq->resize_buf->state = CQ_RESIZE_ALLOC; + + ret = 0; + +unlock: + spin_unlock_irq(&cq->lock); + + if (ret) + return ret; + + ret = hgrnic_alloc_cq_buf(dev, &cq->resize_buf->buf, entries); + if (ret) { + spin_lock_irq(&cq->lock); + kfree(cq->resize_buf); + cq->resize_buf = NULL; + spin_unlock_irq(&cq->lock); + return ret; + } + + cq->resize_buf->cqe = entries - 1; + + spin_lock_irq(&cq->lock); + cq->resize_buf->state = CQ_RESIZE_READY; + spin_unlock_irq(&cq->lock); + + return 0; +} + +static int hgrnic_resize_cq(struct ib_cq *ibcq, int entries, + struct ib_udata *udata) +{ + struct hgrnic_dev *dev = to_hgdev(ibcq->device); + struct hgrnic_cq *cq = to_hgcq(ibcq); + struct hgrnic_resize_cq ucmd; + u32 lkey; + int ret; + + printk(KERN_INFO PFX "Enter hgrnic_resize_cq\n"); + if (entries < 1 || entries > dev->limits.max_cqes) + return -EINVAL; + + mutex_lock(&cq->mutex); + + entries = roundup_pow_of_two(entries + 1); + if (entries == ibcq->cqe + 1) { + ret = 0; + goto out; + } + + if (cq->is_kernel) { + ret = hgrnic_alloc_resize_buf(dev, cq, entries); + if (ret) + goto out; + lkey = cq->resize_buf->buf.mr.ibmr.lkey; + } else { + if (ib_copy_from_udata(&ucmd, udata, sizeof ucmd)) { + ret = -EFAULT; + goto out; + } + lkey = ucmd.lkey; + } + + ret = hgrnic_RESIZE_CQ(dev, cq->cqn, lkey, ilog2(entries)); + + if (ret) { + if (cq->resize_buf) { + hgrnic_free_cq_buf(dev, &cq->resize_buf->buf, + cq->resize_buf->cqe); + kfree(cq->resize_buf); + spin_lock_irq(&cq->lock); + cq->resize_buf = NULL; + spin_unlock_irq(&cq->lock); + } + goto out; + } + + if (cq->is_kernel) { + struct hgrnic_cq_buf tbuf; + int tcqe; + + spin_lock_irq(&cq->lock); + if (cq->resize_buf->state == CQ_RESIZE_READY) { + hgrnic_cq_resize_copy_cqes(cq); + tbuf = cq->buf; + tcqe = cq->ibcq.cqe; + cq->buf = cq->resize_buf->buf; + cq->ibcq.cqe = cq->resize_buf->cqe; + } else { + tbuf = cq->resize_buf->buf; + tcqe = cq->resize_buf->cqe; + } + + kfree(cq->resize_buf); + cq->resize_buf = NULL; + spin_unlock_irq(&cq->lock); + + hgrnic_free_cq_buf(dev, &tbuf, tcqe); + } else + ibcq->cqe = entries - 1; + +out: + mutex_unlock(&cq->mutex); + + printk(KERN_INFO PFX "Exit hgrnic_resize_cq\n"); + return ret; +} + +/** + * @note The following is the mandatory API. + * query_device, + * query_port + * query_pkey + * alloc_pd + * dealloc_pd + * create_qp + * modify_qp + * destroy_qp + * post_send + * post_recv + * create_cq + * destroy_cq + * poll_cq + * req_notify_cq + * get_dma_mr + * dereg_mr + * get_port_immutable + */ +static const struct ib_device_ops hgrnic_dev_ops = { + .owner = THIS_MODULE, + .driver_id = RDMA_DRIVER_HGRNIC, + .uverbs_abi_ver = HGRNIC_UVERBS_ABI_VERSION, + .uverbs_no_driver_id_binding = 1, + + .query_device = hgrnic_query_device , /* done, void */ + .modify_device = hgrnic_modify_device, /* done, void */ + + .alloc_ucontext = hgrnic_alloc_ucontext , /* done,tested */ + .dealloc_ucontext = hgrnic_dealloc_ucontext, /* done */ + + .query_port = hgrnic_query_port, /* done, void */ + .get_port_immutable = hgrnic_port_immutable, /* done, void */ + .query_gid = hgrnic_query_gid , /* done, void */ + .query_pkey = hgrnic_query_pkey, /* done, void */ + .mmap = hgrnic_mmap_uar , /* done */ + + .alloc_pd = hgrnic_alloc_pd , /* done */ + .dealloc_pd = hgrnic_dealloc_pd, /* done */ + + .create_qp = hgrnic_create_qp , /* done */ + .query_qp = hgrnic_query_qp , /* done */ + .modify_qp = hgrnic_modify_qp , /* done */ + .destroy_qp = hgrnic_destroy_qp, /* done */ + + .post_send = hgrnic_post_send , /* done */ + .post_recv = hgrnic_post_receive, /* done */ + + .create_cq = hgrnic_create_cq , /* done */ + .destroy_cq = hgrnic_destroy_cq, /* done */ + .poll_cq = hgrnic_poll_cq , /* done */ + .req_notify_cq = hgrnic_arm_cq , /* half done */ + .resize_cq = hgrnic_resize_cq , /* done */ + + .get_dma_mr = hgrnic_get_dma_mr , /* done */ + .reg_user_mr = hgrnic_reg_user_mr, /* done */ + .dereg_mr = hgrnic_dereg_mr , /* done */ + + /* tell ib_core size of driver data struct */ + INIT_RDMA_OBJ_SIZE(ib_ah, hgrnic_ah, ibah), + INIT_RDMA_OBJ_SIZE(ib_cq, hgrnic_cq, ibcq), + INIT_RDMA_OBJ_SIZE(ib_pd, hgrnic_pd, ibpd), + INIT_RDMA_OBJ_SIZE(ib_ucontext, hgrnic_ucontext, ibucontext), +}; + + + +/** + * @note Register valid API to kernel for this driver. + */ +int hgrnic_register_device (struct hgrnic_dev *dev) { + int ret; + + dev->ib_dev.uverbs_cmd_mask = + (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) | + (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) | + (1ull << IB_USER_VERBS_CMD_QUERY_PORT) | + (1ull << IB_USER_VERBS_CMD_ALLOC_PD) | + (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) | + (1ull << IB_USER_VERBS_CMD_REG_MR) | + (1ull << IB_USER_VERBS_CMD_DEREG_MR) | + (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) | + (1ull << IB_USER_VERBS_CMD_CREATE_CQ) | + (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) | + (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) | + (1ull << IB_USER_VERBS_CMD_CREATE_QP) | + (1ull << IB_USER_VERBS_CMD_QUERY_QP) | + (1ull << IB_USER_VERBS_CMD_MODIFY_QP) | + (1ull << IB_USER_VERBS_CMD_DESTROY_QP); + dev->ib_dev.node_type = RDMA_NODE_IB_CA; + dev->ib_dev.phys_port_cnt = dev->limits.num_ports; + dev->ib_dev.num_comp_vectors = 1; + dev->ib_dev.dev.parent = &dev->pdev->dev; + + + ib_set_device_ops(&dev->ib_dev, &hgrnic_dev_ops); + + mutex_init(&dev->cap_mask_mutex); + + rdma_set_device_sysfs_group(&dev->ib_dev, &hgrnic_attr_group); + printk(KERN_INFO PFX "Start ib_register_device\n"); + ret = ib_register_device(&dev->ib_dev, "hgrnic%d"); + printk(KERN_INFO PFX "End ib_register_device\n"); + if (ret) + return ret; + + return 0; +} + +void hgrnic_unregister_device (struct hgrnic_dev *dev) +{ + ib_unregister_device(&dev->ib_dev); +} diff --git a/ETH-PLUS_Jingzhao/JingZhao2/software/drivers/ib_hgrnic/hgrnic_provider.h b/ETH-PLUS_Jingzhao/JingZhao2/software/drivers/ib_hgrnic/hgrnic_provider.h new file mode 100644 index 0000000000000000000000000000000000000000..ad308d8af71006802cf49cf6a4df2210f3b485c8 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/software/drivers/ib_hgrnic/hgrnic_provider.h @@ -0,0 +1,253 @@ +/************************************************************** + * @author Kang Ning, NCIC, ICT, CAS + * @date 2021.09.08 + * @file hgrnic_provider.h + * @note Functions & Data struct related to interface with ib_uverbs. + *************************************************************/ + +#ifndef HGRNIC_PROVIDER_H +#define HGRNIC_PROVIDER_H + +#include +#include + +#define HGRNIC_MPT_FLAG_ATOMIC (1 << 3) +#define HGRNIC_MPT_FLAG_REMOTE_WRITE (1 << 1) +#define HGRNIC_MPT_FLAG_REMOTE_READ (1 << 2) +#define HGRNIC_MPT_FLAG_LOCAL_WRITE (1 << 0) +#define HGRNIC_MPT_FLAG_LOCAL_READ (1 << 7) + +struct hgrnic_buf_list { + void *buf; /* Vaddr */ + DEFINE_DMA_UNMAP_ADDR(mapping); /* Bus addr */ +}; + +union hgrnic_buf { + struct hgrnic_buf_list direct; + struct hgrnic_buf_list *page_list; +}; + +struct hgrnic_uar { + unsigned long pfn; + int index; +}; + +struct hgrnic_ucontext { + struct ib_ucontext ibucontext; + struct hgrnic_uar uar; +}; + +struct hgrnic_mtt { + struct hgrnic_buddy *buddy; + int order; /* Actual size in log allocated mtt. */ + u32 first_index; /* MTT first index **/ +}; + +struct hgrnic_mr { + struct ib_mr ibmr; + struct ib_umem *umem; + struct hgrnic_mtt *mtt; +}; + +struct hgrnic_pd { + struct ib_pd ibpd; + u32 pd_num; + int privileged; +}; + +struct hgrnic_eq { + struct hgrnic_dev *dev; + int eqn; + u32 eqn_mask; + u32 cons_index; + u16 msi_x_vector; + u16 msi_x_entry; + int have_irq; + int nent; // Number of EQs in this device (the n-th power of 2) + struct hgrnic_buf_list *page_list; // Allocated memory for Event Queue + struct hgrnic_mr mr; + char irq_name[IB_DEVICE_NAME_MAX]; +}; + +struct hgrnic_ah { + struct ib_ah ibah; + u32 port; /* used port */ + u64 slid; + u64 dlid; + u32 pd ; /* PD for the UD */ +}; + +/* + * Quick description of our CQ/QP locking scheme: + * + * We have one global lock that protects dev->cq/qp_table. Each + * struct hgrnic_cq/qp also has its own lock. An individual qp lock + * may be taken inside of an individual cq lock. Both cqs attached to + * a qp may be locked, with the cq with the lower cqn locked first. + * No other nesting should be done. + * + * Each struct hgrnic_cq/qp also has an ref count, protected by the + * corresponding table lock. The pointer from the cq/qp_table to the + * struct counts as one reference. This reference also is good for + * access through the consumer API, so modifying the CQ/QP etc doesn't + * need to take another reference. Access to a QP because of a + * completion being polled does not need a reference either. + * + * Finally, each struct hgrnic_cq/qp has a wait_queue_head_t for the + * destroy function to sleep on. + * + * This means that access from the consumer API requires nothing but + * taking the struct's lock. + * + * Access because of a completion event should go as follows: + * - lock cq/qp_table and look up struct + * - increment ref count in struct + * - drop cq/qp_table lock + * - lock struct, do your thing, and unlock struct + * - decrement ref count; if zero, wake up waiters + * + * To destroy a CQ/QP, we can do the following: + * - lock cq/qp_table + * - remove pointer and decrement ref count + * - unlock cq/qp_table lock + * - wait_event until ref count is zero + * + * It is the consumer's responsibilty to make sure that no QP + * operations (WQE posting or state modification) are pending when a + * QP is destroyed. Also, the consumer must make sure that calls to + * qp_modify are serialized. Similarly, the consumer is responsible + * for ensuring that no CQ resize operations are pending when a CQ + * is destroyed. + * + * Possible optimizations (wait for profile data to see if/where we + * have locks bouncing between CPUs): + * - split cq/qp table lock into n separate (cache-aligned) locks, + * indexed (say) by the page in the table + * - split QP struct lock into three (one for common info, one for the + * send queue and one for the receive queue) + */ + +struct hgrnic_cq_buf { + union hgrnic_buf queue; + struct hgrnic_mr mr; + int is_direct; +}; + +struct hgrnic_cq_resize { + struct hgrnic_cq_buf buf; + int cqe; /* we actual allocate one + * element larger than cqe */ + enum { + CQ_RESIZE_ALLOC, + CQ_RESIZE_READY, + CQ_RESIZE_SWAPPED + } state; +}; + +struct hgrnic_cq { + struct ib_cq ibcq; /* we actual allocate one + * element larger than ibcq->cqe */ + spinlock_t lock; + int refcount; + int cqn; + u32 cons_index; /* consumer index, point + * to first unpolled cqe. + * Never rotate back. */ + struct hgrnic_cq_buf buf; + struct hgrnic_cq_resize *resize_buf; + int is_kernel; + + wait_queue_head_t wait; + struct mutex mutex; +}; + +struct hgrnic_wq { + spinlock_t lock ; + int max ; // Supported maximum number of WQEs in WQ + unsigned next_ind ; + unsigned last_cpl ; + unsigned head ; /* never roll back, so it need to & (max - 1) when in use */ + unsigned tail ; /* never roll back, so it need to & (max - 1) when in use */ + void *last ; + int max_gs ; + int entry_sz_log ; + int que_size ; /* que_size = max << entry_sz_log */ + + struct hgrnic_mr mr ; /* memory region allocated for work queue */ + u64 *wr_id; /* work request id, used when pooling cqc */ + union hgrnic_buf queue; /* work queue */ +}; + +struct hgrnic_qp { + struct ib_qp ibqp; + int refcount; + u32 qpn; + int is_direct; + u8 port; /* for SQP and memfree use only */ + u8 transport; /* transport type: RC, UD, UC */ + u8 state; + u8 atomic_rd_en; + u8 resp_depth; + + struct hgrnic_wq rq; + struct hgrnic_wq sq; + int max_inline_data; + + u8 mtu_msgmax; + u32 remote_qpn; + u8 min_rnr_timer; + u32 port_num; + u32 psn; + u32 epsn; + + wait_queue_head_t wait; + struct mutex mutex; +}; + +struct hgrnic_sqp { + struct hgrnic_qp qp; + int pkey_index; + u32 qkey; + u32 send_psn; + struct ib_ud_header ud_header; + int header_buf_size; + void *header_buf; + dma_addr_t header_dma; +}; + +static inline u32 convert_access(int acc) +{ + return (acc & IB_ACCESS_REMOTE_ATOMIC ? HGRNIC_MPT_FLAG_ATOMIC : 0) | + (acc & IB_ACCESS_REMOTE_WRITE ? HGRNIC_MPT_FLAG_REMOTE_WRITE : 0) | + (acc & IB_ACCESS_REMOTE_READ ? HGRNIC_MPT_FLAG_REMOTE_READ : 0) | + (acc & IB_ACCESS_LOCAL_WRITE ? HGRNIC_MPT_FLAG_LOCAL_WRITE : 0) | + HGRNIC_MPT_FLAG_LOCAL_READ; +} + +static inline struct hgrnic_ucontext *to_hgucontext(struct ib_ucontext *ibucontext) { + return container_of(ibucontext, struct hgrnic_ucontext, ibucontext); +} + +static inline struct hgrnic_mr *to_hgmr(struct ib_mr *ibmr) { + return container_of(ibmr, struct hgrnic_mr, ibmr); +} + +static inline struct hgrnic_pd *to_hgpd(struct ib_pd *ibpd) { + return container_of(ibpd, struct hgrnic_pd, ibpd); +} + +static inline struct hgrnic_ah *to_hgah(struct ib_ah *ibah) +{ + return container_of(ibah, struct hgrnic_ah, ibah); +} + +static inline struct hgrnic_cq *to_hgcq(struct ib_cq *ibcq) { + return container_of(ibcq, struct hgrnic_cq, ibcq); +} + +static inline struct hgrnic_qp *to_hgqp(struct ib_qp *ibqp) { + return container_of(ibqp, struct hgrnic_qp, ibqp); +} + + +#endif /* HGRNIC_PROVIDER_H */ diff --git a/ETH-PLUS_Jingzhao/JingZhao2/software/drivers/ib_hgrnic/hgrnic_qp.c b/ETH-PLUS_Jingzhao/JingZhao2/software/drivers/ib_hgrnic/hgrnic_qp.c new file mode 100644 index 0000000000000000000000000000000000000000..44f9a8191629374147062c93d7441f2a2747101e --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/software/drivers/ib_hgrnic/hgrnic_qp.c @@ -0,0 +1,1212 @@ +/************************************************************** + * @author Kang Ning, NCIC, ICT, CAS + * @date 2021.08.30 + * @file hgrnic_qp.c + * @note Functions related to QPs. + *************************************************************/ + +#include +#include +#include + +#include + +#include +#include +#include +#include + +#include "hgrnic_dev.h" +#include "hgrnic_cmd.h" +#include "hgrnic_wqe.h" + + +enum { + HGRNIC_QP_STATE_RST = 0, + HGRNIC_QP_STATE_INIT = 1, + HGRNIC_QP_STATE_RTR = 2, + HGRNIC_QP_STATE_RTS = 3, + HGRNIC_QP_STATE_SQE = 4, + HGRNIC_QP_STATE_SQD = 5, + HGRNIC_QP_STATE_ERR = 6, + HGRNIC_QP_STATE_DRAINING = 7 +}; + +enum { + HGRNIC_QP_ST_RC = 0x0, + HGRNIC_QP_ST_UC = 0x1, + HGRNIC_QP_ST_RD = 0x2, + HGRNIC_QP_ST_UD = 0x3, + HGRNIC_QP_ST_RSV = 0x7 +}; + +enum { + HGRNIC_SEND_DOORBELL_FENCE = 1 << 5 +}; + +enum { + HGRNIC_RATE_FULL = 0, + HGRNIC_RATE_QUARTER = 1, + HGRNIC_RATE_EIGHTH = 2, + HGRNIC_RATE_HALF = 3 +}; + +struct hgrnic_qp_path { + __be32 port_pkey ; /* port number is larger than 0 */ + u8 rnr_retry ; + u8 g_mylmc ; /* not used + * [7:7], [6:0] + * has grh mylmc */ + __be16 rlid ; /* not used */ + u8 ackto ; /* ack timeout, not used */ + u8 mgid_index ; /* not used */ + u8 static_rate; /* maximum bandwidth, not used */ + u8 hop_limit ; /* not used */ + __be32 sl_tclass_flowlabel; /* not used */ + u8 rgid[16] ; /* not used */ +} __packed; + +struct hgrnic_qp_context { + __be32 flags; + u8 mtu_msgmax; + u8 rq_entry_sz_log; /* size of one entry in RQ in log format */ + u8 sq_entry_sz_log; /* size of one entry in SQ in log format */ + u8 rlkey_sched_queue; /* not used */ + __be32 usr_page; /* not used */ + __be32 local_qpn; + __be32 remote_qpn; + struct hgrnic_qp_path pri_path; + __be32 reserved1[8]; + __be32 pd; + __be32 wqe_base; /* not used */ + __be32 wqe_lkey; /* not used */ + __be32 reserved2; + __be32 next_send_psn; + __be32 cqn_snd; + __be32 snd_wqe_base_l; /* Send Queue lkey */ + __be32 snd_wqe_len; /* length of Send Queue */ + __be32 last_acked_psn; + __be32 ssn; /* not used */ + __be32 rnr_nextrecvpsn; + __be32 ra_buff_indx; /* not used */ + __be32 cqn_rcv; + __be32 rcv_wqe_base_l; /* Recv Queue lkey */ + __be32 rcv_wqe_len; /* length of Send Queue */ + __be32 qkey; /* not used */ + __be32 rmsn; /* not used */ + __be16 rq_wqe_counter; /* not used */ + __be16 sq_wqe_counter; /* not used */ +} __packed; + +struct hgrnic_qp_param { + __be32 opt_param_mask; + u32 reserved1; + struct hgrnic_qp_context context; +} __packed; + +enum { + HGRNIC_QP_OPTPAR_ALT_ADDR_PATH = 1 << 0, + HGRNIC_QP_OPTPAR_RRE = 1 << 1, + HGRNIC_QP_OPTPAR_RAE = 1 << 2, + HGRNIC_QP_OPTPAR_RWE = 1 << 3, + HGRNIC_QP_OPTPAR_PKEY_INDEX = 1 << 4, + HGRNIC_QP_OPTPAR_Q_KEY = 1 << 5, + HGRNIC_QP_OPTPAR_RNR_TIMEOUT = 1 << 6, + HGRNIC_QP_OPTPAR_PRIMARY_ADDR_PATH = 1 << 7, + HGRNIC_QP_OPTPAR_SRA_MAX = 1 << 8, + HGRNIC_QP_OPTPAR_RRA_MAX = 1 << 9, + HGRNIC_QP_OPTPAR_PM_STATE = 1 << 10, + HGRNIC_QP_OPTPAR_PORT_NUM = 1 << 11, + HGRNIC_QP_OPTPAR_RETRY_COUNT = 1 << 12, + HGRNIC_QP_OPTPAR_ALT_RNR_RETRY = 1 << 13, + HGRNIC_QP_OPTPAR_ACK_TIMEOUT = 1 << 14, + HGRNIC_QP_OPTPAR_RNR_RETRY = 1 << 15, + HGRNIC_QP_OPTPAR_SCHED_QUEUE = 1 << 16 +}; + +static const u8 hgrnic_opcode[] = { + [IB_WR_SEND] = HGRNIC_OPCODE_SEND, + [IB_WR_SEND_WITH_IMM] = HGRNIC_OPCODE_SEND_IMM, + [IB_WR_RDMA_WRITE] = HGRNIC_OPCODE_RDMA_WRITE, + [IB_WR_RDMA_WRITE_WITH_IMM] = HGRNIC_OPCODE_RDMA_WRITE_IMM, + [IB_WR_RDMA_READ] = HGRNIC_OPCODE_RDMA_READ, + [IB_WR_ATOMIC_CMP_AND_SWP] = HGRNIC_OPCODE_ATOMIC_CS, + [IB_WR_ATOMIC_FETCH_AND_ADD] = HGRNIC_OPCODE_ATOMIC_FA, +}; + +static void *get_wqe (struct hgrnic_wq wq, int n) { + return wq.queue.page_list[(n << wq.entry_sz_log) >> PAGE_SHIFT].buf + + ((n << wq.entry_sz_log) & (PAGE_SIZE - 1)); +} + +static void hgrnic_wq_reset(struct hgrnic_wq *wq) +{ + wq->next_ind = 0; + wq->last_cpl = wq->max - 1; + wq->head = 0; + wq->tail = 0; +} + +static int to_hgrnic_state(enum ib_qp_state ib_state) +{ + switch (ib_state) { + case IB_QPS_RESET: return HGRNIC_QP_STATE_RST; + case IB_QPS_INIT: return HGRNIC_QP_STATE_INIT; + case IB_QPS_RTR: return HGRNIC_QP_STATE_RTR; + case IB_QPS_RTS: return HGRNIC_QP_STATE_RTS; + case IB_QPS_SQD: return HGRNIC_QP_STATE_SQD; + case IB_QPS_SQE: return HGRNIC_QP_STATE_SQE; + case IB_QPS_ERR: return HGRNIC_QP_STATE_ERR; + default: return -1; + } +} + +enum { RC, UC, UD, RD, RSV, NUM_TRANS }; + +static int to_hgrnic_st(int transport) +{ + switch (transport) { + case RC: return HGRNIC_QP_ST_RC; + case UC: return HGRNIC_QP_ST_UC; + case UD: return HGRNIC_QP_ST_UD; + case RD: return HGRNIC_QP_ST_RD; + case RSV: return HGRNIC_QP_ST_RSV; + default: return -1; + } +} + + + +static inline enum ib_qp_state to_ib_qp_state(int hgrnic_state) +{ + switch (hgrnic_state) { + case HGRNIC_QP_STATE_RST: return IB_QPS_RESET; + case HGRNIC_QP_STATE_INIT: return IB_QPS_INIT; + case HGRNIC_QP_STATE_RTR: return IB_QPS_RTR; + case HGRNIC_QP_STATE_RTS: return IB_QPS_RTS; + case HGRNIC_QP_STATE_DRAINING: + case HGRNIC_QP_STATE_SQD: return IB_QPS_SQD; + case HGRNIC_QP_STATE_SQE: return IB_QPS_SQE; + case HGRNIC_QP_STATE_ERR: return IB_QPS_ERR; + default: return -1; + } +} + +static inline enum ib_mig_state to_ib_mig_state(int hgrnic_mig_state) +{ + switch (hgrnic_mig_state) { + case 0: return IB_MIG_ARMED; + case 1: return IB_MIG_REARM; + case 3: return IB_MIG_MIGRATED; + default: return -1; + } +} + +static enum ib_rate memfree_rate_to_ib(u8 hgrnic_rate, u8 port_rate) +{ + switch (hgrnic_rate) { + case HGRNIC_RATE_EIGHTH: + return mult_to_ib_rate(port_rate >> 3); + case HGRNIC_RATE_QUARTER: + return mult_to_ib_rate(port_rate >> 2); + case HGRNIC_RATE_HALF: + return mult_to_ib_rate(port_rate >> 1); + case HGRNIC_RATE_FULL: + default: + return mult_to_ib_rate(port_rate); + } +} + +enum ib_rate hgrnic_rate_to_ib(struct hgrnic_dev *dev, u8 hgrnic_rate, u8 port) +{ + /* Handle old Arbel FW */ + if (dev->limits.stat_rate_support == 0x3 && hgrnic_rate) + return IB_RATE_2_5_GBPS; + + return memfree_rate_to_ib(hgrnic_rate, dev->rate[port - 1]); +} + +static void to_rdma_ah_attr(struct hgrnic_dev *dev, + struct rdma_ah_attr *ah_attr, + struct hgrnic_qp_path *path) +{ + u8 port_num = (be32_to_cpu(path->port_pkey) >> 24) & 0x3; + + memset(ah_attr, 0, sizeof(*ah_attr)); + + if (port_num == 0 || port_num > dev->limits.num_ports) + return; + ah_attr->type = rdma_ah_find_type(&dev->ib_dev, port_num); + rdma_ah_set_port_num(ah_attr, port_num); + + rdma_ah_set_dlid(ah_attr, be16_to_cpu(path->rlid)); + rdma_ah_set_sl(ah_attr, be32_to_cpu(path->sl_tclass_flowlabel) >> 28); + rdma_ah_set_path_bits(ah_attr, path->g_mylmc & 0x7f); + rdma_ah_set_static_rate(ah_attr, + hgrnic_rate_to_ib(dev, + path->static_rate & 0xf, + port_num)); + if (path->g_mylmc & (1 << 7)) { + u32 tc_fl = be32_to_cpu(path->sl_tclass_flowlabel); + + rdma_ah_set_grh(ah_attr, NULL, + tc_fl & 0xfffff, + path->mgid_index & + (dev->limits.gid_table_len - 1), + path->hop_limit, + (tc_fl >> 20) & 0xff); + rdma_ah_set_dgid_raw(ah_attr, path->rgid); + } +} + +int hgrnic_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask, + struct ib_qp_init_attr *qp_init_attr) +{ + struct hgrnic_dev *dev = to_hgdev(ibqp->device); + struct hgrnic_qp *qp = to_hgqp(ibqp); + int err = 0; + struct hgrnic_mailbox *mailbox = NULL; + struct hgrnic_qp_param *qp_param; + struct hgrnic_qp_context *context; + int hgrnic_state; + + mutex_lock(&qp->mutex); + + if (qp->state == IB_QPS_RESET) { + qp_attr->qp_state = IB_QPS_RESET; + goto done; + } + + mailbox = hgrnic_alloc_mailbox(dev, GFP_KERNEL); + if (IS_ERR(mailbox)) { + err = PTR_ERR(mailbox); + goto out; + } + + err = hgrnic_QUERY_QP(dev, qp->qpn, mailbox); + if (err) { + hgrnic_warn(dev, "QUERY_QP failed (%d)\n", err); + goto out_mailbox; + } + + qp_param = mailbox->buf; + context = &qp_param->context; + hgrnic_state = be32_to_cpu(context->flags) >> 28; + + qp->state = to_ib_qp_state(hgrnic_state); + qp_attr->qp_state = qp->state; + qp_attr->path_mtu = context->mtu_msgmax >> 5; + qp_attr->qkey = be32_to_cpu(context->qkey); + qp_attr->rq_psn = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff; + qp_attr->sq_psn = be32_to_cpu(context->next_send_psn) & 0xffffff; + qp_attr->dest_qp_num = be32_to_cpu(context->remote_qpn) & 0xffffff; + + qp_attr->path_mig_state = 0; /* reserved */ + + + if (qp->transport == RC || qp->transport == UC) { + to_rdma_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path); + } + + qp_attr->pkey_index = be32_to_cpu(context->pri_path.port_pkey) & 0x7f; + qp_attr->port_num = + (be32_to_cpu(context->pri_path.port_pkey) >> 24) & 0x3; + + /* qp_attr->en_sqd_async_notify is only applicable in modify qp */ + qp_attr->sq_draining = hgrnic_state == HGRNIC_QP_STATE_DRAINING; + + qp_attr->min_rnr_timer = + (be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f; + qp_attr->timeout = context->pri_path.ackto >> 3; + qp_attr->rnr_retry = context->pri_path.rnr_retry >> 5; + +done: + qp_attr->cur_qp_state = qp_attr->qp_state; + qp_attr->cap.max_send_wr = qp->sq.max; + qp_attr->cap.max_recv_wr = qp->rq.max; + qp_attr->cap.max_send_sge = qp->sq.max_gs; + qp_attr->cap.max_recv_sge = qp->rq.max_gs; + qp_attr->cap.max_inline_data = qp->max_inline_data; + + qp_init_attr->cap = qp_attr->cap; + +out_mailbox: + hgrnic_free_mailbox(dev, mailbox); + +out: + mutex_unlock(&qp->mutex); + return err; +} + +static int __hgrnic_modify_qp (struct ib_qp *ibqp, + const struct ib_qp_attr *attr, int attr_mask, + enum ib_qp_state cur_state, enum ib_qp_state new_state, + struct ib_udata *udata) { + + struct hgrnic_dev *dev = to_hgdev(ibqp->device); + struct hgrnic_qp *qp = to_hgqp(ibqp); + struct hgrnic_ucontext *context = rdma_udata_to_drv_context( + udata, struct hgrnic_ucontext, ibucontext); + struct hgrnic_mailbox *mailbox; + struct hgrnic_qp_param *qp_param; + struct hgrnic_qp_context *qp_context; + int err = -EINVAL; + + printk(KERN_INFO PFX "\n\n__hgrnic_modify_qp (QP 0x%x): cur_state %d -> new_state %d.\n", + qp->qpn, cur_state, new_state); + + mailbox = hgrnic_alloc_mailbox(dev, GFP_KERNEL); + if (IS_ERR(mailbox)) + return PTR_ERR(mailbox); + + qp_param = mailbox->buf; + qp_context = &qp_param->context; + memset(qp_param, 0, sizeof *qp_param); + + qp_context->flags = cpu_to_be32((to_hgrnic_state(new_state) << 28) | + (to_hgrnic_st(qp->transport) << 16)); + + if (qp->transport == UD) { + qp->mtu_msgmax = (IB_MTU_4096 << 5) | 11; + } else if (attr_mask & IB_QP_PATH_MTU) { + if (attr->path_mtu < IB_MTU_256 || attr->path_mtu > IB_MTU_4096) { + hgrnic_dbg(dev, "path MTU (%u) is invalid\n", + attr->path_mtu); + goto out_mailbox; + } + qp->mtu_msgmax = (attr->path_mtu << 5) | 31; + } + qp_context->mtu_msgmax = qp->mtu_msgmax; + + qp_context->rq_entry_sz_log = qp->rq.entry_sz_log; + qp_context->sq_entry_sz_log = qp->sq.entry_sz_log; + + if (qp->ibqp.uobject) + qp_context->usr_page = cpu_to_be32(context->uar.index); + else + qp_context->usr_page = cpu_to_be32(dev->driver_uar.index); + + + /* local_qp and remote_qp should be masked with num_qps, + * cause RNIC hardware only supports `num_qps` QP. + */ + qp_context->local_qpn = cpu_to_be32(qp->qpn & (dev->limits.num_qps - 1)); + + if (attr_mask & IB_QP_DEST_QPN) + qp->remote_qpn = attr->dest_qp_num; + qp_context->remote_qpn = cpu_to_be32(qp->remote_qpn & (dev->limits.num_qps - 1)); + + if (attr_mask & IB_QP_PORT) { + /* Port num starts from 1 */ + qp->port_num = attr->port_num << 24; + qp_param->opt_param_mask |= cpu_to_be32(HGRNIC_QP_OPTPAR_PORT_NUM); + } + qp_context->pri_path.port_pkey = cpu_to_be32(qp->port_num); + + // qp_context->pri_path.port_pkey |= cpu_to_be32(attr->pkey_index); + // qp_param->opt_param_mask |= cpu_to_be32(HGRNIC_QP_OPTPAR_PKEY_INDEX); + + // qp_context->pri_path.rnr_retry = cpu_to_be32(attr->rnr_retry << 5); + // qp_param->opt_param_mask |= cpu_to_be32(HGRNIC_QP_OPTPAR_RNR_RETRY); + + qp_context->pd = cpu_to_be32(to_hgpd(ibqp->pd)->pd_num); + + qp_context->wqe_base = 0; + qp_context->wqe_lkey = cpu_to_be32(qp->sq.mr.ibmr.lkey); /* !FIXME: This is a bug on hardware, + and we may fix it laer */ + + if (attr_mask & IB_QP_SQ_PSN) + qp->psn = attr->sq_psn; + qp_context->next_send_psn = cpu_to_be32(qp->psn); +//Modified by YangFan + qp_context->last_acked_psn = cpu_to_be32(qp->psn); + + qp_context->cqn_snd = cpu_to_be32(to_hgcq(ibqp->send_cq)->cqn); + qp_context->snd_wqe_base_l = cpu_to_be32(qp->sq.mr.ibmr.lkey); + qp_context->snd_wqe_len = cpu_to_be32(qp->sq.mr.ibmr.length); + + if (attr_mask & IB_QP_MIN_RNR_TIMER) { + qp->min_rnr_timer = attr->min_rnr_timer << 24; + qp_param->opt_param_mask |= cpu_to_be32(HGRNIC_QP_OPTPAR_RNR_TIMEOUT); + } + qp_context->rnr_nextrecvpsn |= cpu_to_be32(qp->min_rnr_timer); + + if (attr_mask & IB_QP_RQ_PSN) + qp->epsn = attr->rq_psn; + qp_context->rnr_nextrecvpsn |= cpu_to_be32(qp->epsn); + + qp_context->cqn_rcv = cpu_to_be32(to_hgcq(ibqp->recv_cq)->cqn); + qp_context->rcv_wqe_base_l = cpu_to_be32(qp->rq.mr.ibmr.lkey); + qp_context->rcv_wqe_len = cpu_to_be32(qp->rq.mr.ibmr.length); + + err = hgrnic_MODIFY_QP(dev, cur_state, new_state, qp->qpn, mailbox); + if (err) { + hgrnic_warn(dev, "modify QP %d->%d returned %d.\n", + cur_state, new_state, err); + goto out_mailbox; + } + printk(KERN_INFO PFX "----------------------------------"); + hgrnic_dump("0x%x", be32_to_cpu(qp_param->opt_param_mask)); + hgrnic_dump("0x%x", be32_to_cpu(qp_context->flags )); + hgrnic_dump("0x%x", qp_context->mtu_msgmax); + hgrnic_dump("0x%x", qp_context->rq_entry_sz_log); + hgrnic_dump("0x%x", qp_context->sq_entry_sz_log); + hgrnic_dump("0x%x", qp_context->rlkey_sched_queue); + hgrnic_dump("0x%x", be32_to_cpu(qp_context->usr_page )); + hgrnic_dump("0x%x", be32_to_cpu(qp_context->local_qpn )); + hgrnic_dump("0x%x", be32_to_cpu(qp_context->remote_qpn )); + hgrnic_dump("0x%x", be32_to_cpu(qp_context->pri_path.port_pkey)); + hgrnic_dump("0x%x", qp_context->pri_path.rnr_retry); + hgrnic_dump("0x%x", be32_to_cpu(qp_context->pd )); + hgrnic_dump("0x%x", be32_to_cpu(qp_context->wqe_base )); + hgrnic_dump("0x%x", be32_to_cpu(qp_context->wqe_lkey )); + hgrnic_dump("0x%x", be32_to_cpu(qp_context->next_send_psn )); + hgrnic_dump("0x%x", be32_to_cpu(qp_context->cqn_snd )); + hgrnic_dump("0x%x", be32_to_cpu(qp_context->snd_wqe_base_l )); + hgrnic_dump("0x%x", be32_to_cpu(qp_context->snd_wqe_len )); + hgrnic_dump("0x%x", be32_to_cpu(qp_context->last_acked_psn )); + hgrnic_dump("0x%x", be32_to_cpu(qp_context->ssn )); + hgrnic_dump("0x%x", be32_to_cpu(qp_context->rnr_nextrecvpsn)); + hgrnic_dump("0x%x", be32_to_cpu(qp_context->ra_buff_indx )); + hgrnic_dump("0x%x", be32_to_cpu(qp_context->cqn_rcv )); + hgrnic_dump("0x%x", be32_to_cpu(qp_context->rcv_wqe_base_l )); + hgrnic_dump("0x%x", be32_to_cpu(qp_context->rcv_wqe_len )); + hgrnic_dump("0x%x", be32_to_cpu(qp_context->qkey )); + hgrnic_dump("0x%x", be32_to_cpu(qp_context->rmsn )); + hgrnic_dump("0x%x", be32_to_cpu(qp_context->rq_wqe_counter )); + hgrnic_dump("0x%x", be32_to_cpu(qp_context->sq_wqe_counter )); + printk(KERN_INFO PFX "----------------------------------\n\n"); + + qp->state = new_state; + if (attr_mask & IB_QP_PORT) + qp->port = attr->port_num; + + /* + * If we moved a kernel QP to RESET, clean up all old CQ + * entries and reinitialize the QP. + */ + if (new_state == IB_QPS_RESET && !qp->ibqp.uobject) { + hgrnic_cq_clean(dev, to_hgcq(qp->ibqp.recv_cq), qp->qpn); + if (qp->ibqp.send_cq != qp->ibqp.recv_cq) + hgrnic_cq_clean(dev, to_hgcq(qp->ibqp.send_cq), qp->qpn); + + hgrnic_wq_reset(&qp->sq); + qp->sq.last = get_wqe(qp->sq, qp->sq.max - 1); + + hgrnic_wq_reset(&qp->rq); + qp->rq.last = get_wqe(qp->rq, qp->rq.max - 1); + } + +out_mailbox: + hgrnic_free_mailbox(dev, mailbox); + return err; +} + +int hgrnic_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, int attr_mask, + struct ib_udata *udata) +{ + struct hgrnic_dev *dev = to_hgdev(ibqp->device); + struct hgrnic_qp *qp = to_hgqp(ibqp); + enum ib_qp_state cur_state, new_state; + int err = -EINVAL; + + mutex_lock(&qp->mutex); + if (attr_mask & IB_QP_CUR_STATE) + cur_state = attr->cur_qp_state; + else { + spin_lock_irq(&qp->sq.lock); + spin_lock(&qp->rq.lock); + cur_state = qp->state; + spin_unlock(&qp->rq.lock); + spin_unlock_irq(&qp->sq.lock); + } + + new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state; + + /* Check if QP state transformation is OK + !TODO: May be useful later */ + printk(KERN_INFO PFX "Start ib_modify_qp_is_ok.\n"); + if (!ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type, + attr_mask)) { + hgrnic_dbg(dev, "Bad QP transition (transport %d) " + "%d->%d with attr 0x%08x\n", + qp->transport, cur_state, new_state, + attr_mask); + goto out; + } + + if ((attr_mask & IB_QP_PORT) && + (attr->port_num == 0 || attr->port_num > dev->limits.num_ports)) { + hgrnic_dbg(dev, "Port number (%u) is invalid\n", attr->port_num); + goto out; + } + + if (cur_state == new_state && cur_state == IB_QPS_RESET) { + err = 0; + goto out; + } + + err = __hgrnic_modify_qp(ibqp, attr, attr_mask, cur_state, new_state, + udata); + +out: + mutex_unlock(&qp->mutex); + return err; +} + +/** + * @note calculate maximum data size according to the + * maximum descriptor size. + */ +static int hgrnic_max_data_size (struct hgrnic_dev *dev, + struct hgrnic_qp *qp, int desc_sz) +{ + /* + * Calculate the maximum size of WQE s/g segments, excluding + * the next segment and other non-data segments. + */ + int max_data_size = desc_sz - sizeof (struct hgrnic_next_unit); + + switch (qp->transport) { + case UD: + max_data_size -= sizeof (struct hgrnic_ud_unit); + break; + + default: + max_data_size -= sizeof (struct hgrnic_raddr_unit); + break; + } + + return max_data_size; +} + +/* + * Allocate and register buffer for WQEs. qp->rq.max, sq.max, + * rq.max_gs and sq.max_gs must all be assigned. + * hgrnic_alloc_wqe_buf will calculate is_direct, and + * queue + */ +static int hgrnic_alloc_wqe_buf(struct hgrnic_dev *dev, + struct hgrnic_pd *pd, + int *is_direct, + struct hgrnic_wq *wq, + struct ib_udata *udata) +{ + int err; + + wq->wr_id = kmalloc_array(wq->max, sizeof(u64), GFP_KERNEL); + if (!wq->wr_id) + return -ENOMEM; + + printk(KERN_INFO PFX "Start hgrnic_alloc_wqe_buf: hgrnic_buf_alloc"); + err = hgrnic_buf_alloc(dev, PAGE_ALIGN(wq->que_size), + &wq->queue, is_direct, pd, 0, &wq->mr); + if (err) { + kfree(wq->wr_id); + return err; + } + + return 0; +} + +static void hgrnic_free_wqe_buf(struct hgrnic_dev *dev, + int is_direct, + struct hgrnic_wq *wq) +{ + hgrnic_buf_free(dev, PAGE_ALIGN(wq->que_size), + &wq->queue, is_direct, &wq->mr); + kfree(wq->wr_id); +} + + +static int hgrnic_alloc_qp_buf (struct hgrnic_dev *dev, + struct hgrnic_pd *pd, + struct hgrnic_cq *send_cq, + struct hgrnic_cq *recv_cq, + struct hgrnic_qp *qp, + struct ib_udata *udata) +{ + int ret; + int i; + struct hgrnic_next_unit *next; + struct hgrnic_data_unit *scatter; + int size; + + qp->refcount = 1; + init_waitqueue_head(&qp->wait); + mutex_init(&qp->mutex); + qp->state = IB_QPS_RESET; + qp->atomic_rd_en = 0; + qp->resp_depth = 0; + hgrnic_wq_reset(&qp->sq); + hgrnic_wq_reset(&qp->rq); + + spin_lock_init(&qp->sq.lock); + spin_lock_init(&qp->rq.lock); + + ret = hgrnic_reg_icm(dev, dev->qp_table.qp_table, + qp->qpn, CXT_REGION); + if (ret) + return ret; + + /** + * If this is a userspace QP, we're done now. The doorbells + * will be allocated and buffers will be initialized in + * userspace. + */ + if (udata) + return 0; + + printk(KERN_INFO PFX "Start kernel qp processing!\n"); + + /* Allocate queue space for SQ. */ + ret = hgrnic_alloc_wqe_buf(dev, pd, &qp->is_direct, &qp->sq, udata); + if (ret) { + hgrnic_unreg_icm(dev, dev->qp_table.qp_table, qp->qpn, CXT_REGION); + return ret; + } + + /* Allocate queue space for RQ. */ + ret = hgrnic_alloc_wqe_buf(dev, pd, &qp->is_direct, &qp->rq, udata); + if (ret) { + hgrnic_free_wqe_buf(dev, qp->is_direct, &qp->sq); + hgrnic_unreg_icm(dev, dev->qp_table.qp_table, qp->qpn, CXT_REGION); + return ret; + } + + size = (sizeof (struct hgrnic_next_unit) + + qp->rq.max_gs * sizeof (struct hgrnic_data_unit)) / 16; + + for (i = 0; i < qp->rq.max; ++i) { + next = get_wqe(qp->rq, i); + next->nda_nop = cpu_to_le32(((i + 1) & (qp->rq.max - 1)) << + qp->rq.entry_sz_log); + next->ee_nds = cpu_to_le32(size); + + for (scatter = (void *) (next + 1); + (void *) scatter < (void *) next + (1 << qp->rq.entry_sz_log); + ++scatter) + scatter->lkey = cpu_to_le32(HGRNIC_INVAL_LKEY); + } + + for (i = 0; i < qp->sq.max; ++i) { + next = get_wqe(qp->sq, i); + next->nda_nop = cpu_to_be32((((i + 1) & (qp->sq.max - 1)) << + qp->sq.entry_sz_log)); + } + + qp->sq.last = get_wqe(qp->sq, qp->sq.max - 1); + qp->rq.last = get_wqe(qp->rq, qp->rq.max - 1); + + return 0; +} + +static int hgrnic_set_qp_entry_sz (struct hgrnic_dev *dev, struct hgrnic_qp *qp) +{ + int size; + + size = sizeof (struct hgrnic_next_unit) + + qp->rq.max_gs * sizeof (struct hgrnic_data_unit); + + if (size > dev->limits.max_desc_sz) + return -EINVAL; + + for (qp->rq.entry_sz_log = 7; 1 << qp->rq.entry_sz_log < size; + qp->rq.entry_sz_log++); + qp->rq.que_size = qp->rq.max << qp->rq.entry_sz_log; + // qp->rq.mr.ibmr.length = qp->rq.que_size; + // hgrnic_dump("0x%x", qp->rq.mr.ibmr.length); + // hgrnic_dump("0x%x", qp->rq.que_size); + + size = qp->sq.max_gs * sizeof (struct hgrnic_data_unit); + switch (qp->transport) { + case UD: + size += sizeof (struct hgrnic_ud_unit); + break; + case UC: + size += sizeof (struct hgrnic_raddr_unit); + break; + case RC: + size += sizeof (struct hgrnic_raddr_unit); + /* + * An atomic op will require an atomic segment, a + * remote address segment and one scatter entry. + */ + size = max_t(int, size, + sizeof (struct hgrnic_atomic_unit) + + sizeof (struct hgrnic_raddr_unit) + + sizeof (struct hgrnic_data_unit)); + break; + default: + break; + } + + size += sizeof (struct hgrnic_next_unit); + + if (size > dev->limits.max_desc_sz) + return -EINVAL; + + for (qp->sq.entry_sz_log = 7; 1 << qp->sq.entry_sz_log < size; + qp->sq.entry_sz_log++); + qp->sq.que_size = qp->sq.max << qp->sq.entry_sz_log; + // qp->sq.mr.ibmr.length = qp->sq.que_size; + // hgrnic_dump("0x%x", qp->sq.mr.ibmr.length); + // hgrnic_dump("0x%x", qp->sq.que_size); + + return 0; +} + +static int hgrnic_set_qp_size (struct hgrnic_dev *dev, + struct ib_qp_cap *cap, + struct hgrnic_pd *pd, + struct hgrnic_qp *qp) +{ + int max_data_size = hgrnic_max_data_size(dev, qp, dev->limits.max_desc_sz); + + hgrnic_dump("%d", cap->max_send_wr); + hgrnic_dump("%d", cap->max_recv_wr); + hgrnic_dump("%d", cap->max_send_sge); + hgrnic_dump("%d", cap->max_recv_sge); + hgrnic_dump("%d", cap->max_inline_data); + hgrnic_dump("%d", dev->limits.max_wqes); + hgrnic_dump("%d", dev->limits.max_sg); + hgrnic_dump("%d", dev->limits.max_desc_sz); + hgrnic_dump("%d", max_data_size); + + /* Sanity check QP size before proceeding */ + if (cap->max_send_wr > dev->limits.max_wqes || + cap->max_recv_wr > dev->limits.max_wqes || + cap->max_send_sge > dev->limits.max_sg || + cap->max_recv_sge > dev->limits.max_sg || + cap->max_inline_data > max_data_size - sizeof(struct hgrnic_inline_unit)) { + + return -EINVAL; + } + + qp->rq.max = cap->max_recv_wr; + qp->sq.max = cap->max_send_wr; + qp->rq.max_gs = cap->max_recv_sge; + qp->sq.max_gs = cap->max_send_sge; + qp->max_inline_data = cap->max_inline_data; + + return hgrnic_set_qp_entry_sz(dev, qp); +} + +int hgrnic_alloc_qp (struct hgrnic_dev *dev, + struct hgrnic_pd *pd, struct hgrnic_cq *send_cq, + struct hgrnic_cq *recv_cq, enum ib_qp_type type, + struct ib_qp_cap *cap, struct hgrnic_qp *qp, + struct ib_udata *udata) +{ + int err; + + switch (type) { + case IB_QPT_RC: qp->transport = RC; break; + case IB_QPT_UC: qp->transport = UC; break; + case IB_QPT_UD: qp->transport = UD; break; + default: return -EINVAL; + } + + err = hgrnic_set_qp_size(dev, cap, pd, qp); + if (err) + return err; + + qp->qpn = hgrnic_alloc(&dev->qp_table.alloc); + if (qp->qpn == -1) + return -ENOMEM; + + qp->port = 0; /* not specifying any port */ + + err = hgrnic_alloc_qp_buf(dev, pd, send_cq, recv_cq, qp, udata); + if (err) { + hgrnic_free(&dev->qp_table.alloc, qp->qpn); + return err; + } + + spin_lock_irq(&dev->qp_table.lock); + hgrnic_array_set(&dev->qp_table.qp, + qp->qpn & (dev->limits.num_qps - 1), qp); + spin_unlock_irq(&dev->qp_table.lock); + + return 0; +} + +static void hgrnic_lock_cqs(struct hgrnic_cq *send_cq, struct hgrnic_cq *recv_cq) + __acquires(&send_cq->lock) __acquires(&recv_cq->lock) +{ + if (send_cq == recv_cq) { + spin_lock_irq(&send_cq->lock); + __acquire(&recv_cq->lock); + } else if (send_cq->cqn < recv_cq->cqn) { + spin_lock_irq(&send_cq->lock); + spin_lock_nested(&recv_cq->lock, SINGLE_DEPTH_NESTING); + } else { + spin_lock_irq(&recv_cq->lock); + spin_lock_nested(&send_cq->lock, SINGLE_DEPTH_NESTING); + } +} + +static void hgrnic_unlock_cqs(struct hgrnic_cq *send_cq, struct hgrnic_cq *recv_cq) + __releases(&send_cq->lock) __releases(&recv_cq->lock) +{ + if (send_cq == recv_cq) { + __release(&recv_cq->lock); + spin_unlock_irq(&send_cq->lock); + } else if (send_cq->cqn < recv_cq->cqn) { + spin_unlock(&recv_cq->lock); + spin_unlock_irq(&send_cq->lock); + } else { + spin_unlock(&send_cq->lock); + spin_unlock_irq(&recv_cq->lock); + } +} + + + +static inline int get_qp_refcount(struct hgrnic_dev *dev, struct hgrnic_qp *qp) +{ + int c; + + spin_lock_irq(&dev->qp_table.lock); + c = qp->refcount; + spin_unlock_irq(&dev->qp_table.lock); + + return c; +} + +void hgrnic_free_qp(struct hgrnic_dev *dev, + struct hgrnic_qp *qp) +{ + struct hgrnic_cq *send_cq; + struct hgrnic_cq *recv_cq; + struct hgrnic_mailbox *mailbox; + struct hgrnic_qp_param *qp_param; + + send_cq = to_hgcq(qp->ibqp.send_cq); + recv_cq = to_hgcq(qp->ibqp.recv_cq); + + /* + * Lock CQs here, so that CQ polling code can do QP lookup + * without taking a lock. + */ + hgrnic_lock_cqs(send_cq, recv_cq); + + spin_lock(&dev->qp_table.lock); + hgrnic_array_clear(&dev->qp_table.qp, + qp->qpn & (dev->limits.num_qps - 1)); + --qp->refcount; + spin_unlock(&dev->qp_table.lock); + + hgrnic_unlock_cqs(send_cq, recv_cq); + + wait_event(qp->wait, !get_qp_refcount(dev, qp)); + + if (qp->state != IB_QPS_RESET) { + mailbox = hgrnic_alloc_mailbox(dev, GFP_KERNEL); + qp_param = mailbox->buf; + memset(qp_param, 0, sizeof *qp_param); + hgrnic_MODIFY_QP(dev, qp->state, IB_QPS_RESET, qp->qpn, mailbox); + + hgrnic_free_mailbox(dev, mailbox); + } + + + /* + * If this is a userspace QP, the buffers, MR, CQs and so on + * will be cleaned up in userspace, so all we have to do is + * unref the mem-free tables and free the QPN in our table. + */ + if (!qp->ibqp.uobject) { + hgrnic_cq_clean(dev, recv_cq, qp->qpn); + if (send_cq != recv_cq) + hgrnic_cq_clean(dev, send_cq, qp->qpn); + + hgrnic_free_wqe_buf(dev, qp->is_direct, &qp->sq); + hgrnic_free_wqe_buf(dev, qp->is_direct, &qp->rq); + } + + hgrnic_unreg_icm(dev, dev->qp_table.qp_table, qp->qpn, CXT_REGION); + + hgrnic_free(&dev->qp_table.alloc, qp->qpn); +} + +static inline int hgrnic_wq_overflow (struct hgrnic_wq *wq, int nreq, + struct ib_cq *ib_cq) +{ + unsigned cur; + struct hgrnic_cq *cq; + + cur = wq->head - wq->tail; + if (likely(cur + nreq < wq->max)) + return 0; + + cq = to_hgcq(ib_cq); + spin_lock(&cq->lock); + cur = wq->head - wq->tail; + spin_unlock(&cq->lock); + + return cur + nreq >= wq->max; +} + +int hgrnic_post_send (struct ib_qp *ibqp, const struct ib_send_wr *wr, + const struct ib_send_wr **bad_wr) { + + struct hgrnic_dev *dev = to_hgdev(ibqp->device); + struct hgrnic_qp *qp = to_hgqp(ibqp); + + void *cur_wqe ; /* point to current processing wqe */ + void *cur_unit; /* point to current prcessing unit in current wqe */ + void *prev_wqe; + unsigned long flags; + int err = 0; + int nreq; + int i; + int size; + /* + * f0 and size0 are only used if nreq != 0, and they will + * always be initialized the first time through the main loop + * before nreq is incremented. So nreq cannot become non-zero + * without initializing f0 and size0, and they are in fact + * never used uninitialized. + */ + int uninitialized_var(size0); + u32 uninitialized_var(f0); + int ind; + u8 op0 = 0; + + spin_lock_irqsave(&qp->sq.lock, flags); + + ind = qp->sq.head & (qp->sq.max - 1); + + for (nreq = 0; wr; ++nreq, wr = wr->next) { + if (unlikely(nreq == HGRNIC_MAX_WQES_PER_SEND_DB)) { + hgrnic_send_dbell(dev, qp, nreq, size0, f0, op0); + + nreq = 0; + qp->sq.head += HGRNIC_MAX_WQES_PER_SEND_DB; + } + + if (hgrnic_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) { + hgrnic_err(dev, "SQ %06x full (%u head, %u tail," + " %d max, %d nreq)\n", qp->qpn, + qp->sq.head, qp->sq.tail, + qp->sq.max, nreq); + err = -ENOMEM; + *bad_wr = wr; + goto out; + } + + cur_unit = get_wqe(qp->sq, ind); + cur_wqe = cur_unit; + prev_wqe = qp->sq.last; + qp->sq.last = cur_unit; + printk(KERN_INFO PFX "hgrnic_post_send: wqe addr is 0x%llx\n", (u64)cur_wqe); + + memset(cur_unit, 0, sizeof(struct hgrnic_next_unit)); + if (wr->opcode == IB_WR_SEND_WITH_IMM || + wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM) + ((struct hgrnic_next_unit *) cur_unit)->imm = wr->ex.imm_data; + else + ((struct hgrnic_next_unit *) cur_unit)->imm = 0; + + cur_unit += sizeof (struct hgrnic_next_unit); + size = sizeof (struct hgrnic_next_unit) / 16; + + switch (qp->transport) { + case RC: + switch (wr->opcode) { + case IB_WR_RDMA_READ: + case IB_WR_RDMA_WRITE: + case IB_WR_RDMA_WRITE_WITH_IMM: + set_raddr_unit(cur_unit, rdma_wr(wr)->remote_addr, + rdma_wr(wr)->rkey); + cur_unit += sizeof (struct hgrnic_raddr_unit); + size += sizeof (struct hgrnic_raddr_unit) / 16; + break; + + default: + /* No extra segments required for RC sends */ + break; + } + break; + + case UC: + switch (wr->opcode) { + case IB_WR_RDMA_WRITE: + case IB_WR_RDMA_WRITE_WITH_IMM: + set_raddr_unit(cur_unit, rdma_wr(wr)->remote_addr, + rdma_wr(wr)->rkey); + cur_unit += sizeof (struct hgrnic_raddr_unit); + size += sizeof (struct hgrnic_raddr_unit) / 16; + break; + + default: + /* No extra segments required for UC sends */ + break; + } + break; + + case UD: + set_ud_unit(cur_unit, ud_wr(wr)); + cur_unit += sizeof (struct hgrnic_ud_unit); + size += sizeof (struct hgrnic_ud_unit) / 16; + break; + } + + if (wr->num_sge > qp->sq.max_gs) { + hgrnic_err(dev, "too many gathers\n"); + err = -EINVAL; + *bad_wr = wr; + goto out; + } + + for (i = 0; i < wr->num_sge; ++i) { + hgrnic_set_data_unit(cur_unit, wr->sg_list + i); + cur_unit += sizeof (struct hgrnic_data_unit); + size += sizeof (struct hgrnic_data_unit) / 16; + } + + qp->sq.wr_id[ind] = wr->wr_id; + + if (wr->opcode >= ARRAY_SIZE(hgrnic_opcode)) { + hgrnic_err(dev, "opcode invalid\n"); + err = -EINVAL; + *bad_wr = wr; + goto out; + } + + ((struct hgrnic_next_unit *) prev_wqe)->nda_nop = + cpu_to_le32(((ind << qp->sq.entry_sz_log)) | + hgrnic_opcode[wr->opcode]); + ((struct hgrnic_next_unit *) prev_wqe)->ee_nds = + cpu_to_le32(HGRNIC_NEXT_DBD | size | + ((wr->send_flags & IB_SEND_FENCE) ? + HGRNIC_NEXT_FENCE : 0)); + + if (!nreq) { + size0 = size; + op0 = hgrnic_opcode[wr->opcode]; + f0 = wr->send_flags & IB_SEND_FENCE ? + HGRNIC_SEND_DOORBELL_FENCE : 0; + } + + ++ind; + if (unlikely(ind >= qp->sq.max)) + ind -= qp->sq.max; + + /* print one wqe entry, which may be removed later + * !TODO */ + for (i = 0; i < (size * 16); ++i) + printk(KERN_INFO PFX "hgrnic_post_send: wqe[%d]: 0x%x", i, ((u8*)cur_wqe)[i]); + } + +out: + if (likely(nreq)) + hgrnic_send_dbell(dev, qp, nreq, size0, f0, op0); + + spin_unlock_irqrestore(&qp->sq.lock, flags); + return err; +} + +int hgrnic_post_receive(struct ib_qp *ibqp, const struct ib_recv_wr *wr, + const struct ib_recv_wr **bad_wr) +{ + struct hgrnic_dev *dev = to_hgdev(ibqp->device); + struct hgrnic_qp *qp = to_hgqp(ibqp); + unsigned long flags; + int err = 0; + int nreq; + int ind; + int i; + void *wqe; + + spin_lock_irqsave(&qp->rq.lock, flags); + + ind = qp->rq.head & (qp->rq.max - 1); + + for (nreq = 0; wr; ++nreq, wr = wr->next) { + if (hgrnic_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) { + hgrnic_err(dev, "RQ %06x full (%u head, %u tail," + " %d max, %d nreq)\n", qp->qpn, + qp->rq.head, qp->rq.tail, + qp->rq.max, nreq); + err = -ENOMEM; + *bad_wr = wr; + goto out; + } + + wqe = get_wqe(qp->rq, ind); + + ((struct hgrnic_next_unit *) wqe)->flags = 0; + + wqe += sizeof (struct hgrnic_next_unit); + + if (unlikely(wr->num_sge > qp->rq.max_gs)) { + err = -EINVAL; + *bad_wr = wr; + goto out; + } + + for (i = 0; i < wr->num_sge; ++i) { + hgrnic_set_data_unit(wqe, wr->sg_list + i); + wqe += sizeof (struct hgrnic_data_unit); + } + + /* end of data unit */ + if (i < qp->rq.max_gs) + hgrnic_set_data_unit_inval(wqe); + + qp->rq.wr_id[ind] = wr->wr_id; + + ++ind; + if (unlikely(ind >= qp->rq.max)) + ind -= qp->rq.max; + } + +out: + if (likely(nreq)) + qp->rq.head += nreq; + + spin_unlock_irqrestore(&qp->rq.lock, flags); + return err; +} + +int hgrnic_init_qp_table (struct hgrnic_dev *dev) { + int err; + // int i; + + spin_lock_init(&dev->qp_table.lock); + + /* + * We reserve 2 extra QPs per port for the special QPs. The + * special QP for port 1 has to be even, so round up. + */ + dev->qp_table.sqp_start = (dev->limits.reserved_qps + 1) & ~1UL; + err = hgrnic_alloc_init(&dev->qp_table.alloc, + dev->limits.num_qps, + (1 << 24) - 1); + if (err) { + return err; + } + + err = hgrnic_array_init(&dev->qp_table.qp, + dev->limits.num_qps); + if (err) { + hgrnic_alloc_cleanup(&dev->qp_table.alloc); + return err; + } + + return 0; + +} + +void hgrnic_cleanup_qp_table(struct hgrnic_dev *dev) +{ + // int i; + + // for (i = 0; i < 2; ++i) + // hgrnic_CONF_SPECIAL_QP(dev, i, 0); + + hgrnic_array_cleanup(&dev->qp_table.qp, dev->limits.num_qps); + hgrnic_alloc_cleanup(&dev->qp_table.alloc); +} diff --git a/ETH-PLUS_Jingzhao/JingZhao2/software/drivers/ib_hgrnic/hgrnic_register.c b/ETH-PLUS_Jingzhao/JingZhao2/software/drivers/ib_hgrnic/hgrnic_register.c new file mode 100644 index 0000000000000000000000000000000000000000..36b13dd07a3a92f22a3346ca93484c78983fc7ed --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/software/drivers/ib_hgrnic/hgrnic_register.c @@ -0,0 +1,37 @@ +/************************************************************** + * @author Kang Ning, NCIC, ICT, CAS + * @date 2021.09.08 + * @file hgrnic_register.c + * @note Provide interface for ethernet driver registering + *************************************************************/ +#include "hgrnic_register.h" + +static struct hgrnic_dev* hgdev; + +int hgrnic_init_en_register (struct hgrnic_dev* dev) +{ + hgdev = dev; + return 0; +} + +int hgrnic_register_en_driver (struct hgrnic_endev *endev) +{ + + printk(KERN_INFO PFX "Start pci_set_drvdata.\n"); + return 0; + + if (!hgdev->active) + return -1; + + hgdev->endev = endev; + + endev->reg = ioremap(pci_resource_start(hgdev->pdev, 0) + HGRNIC_EN_REG_BASE, + HGRNIC_EN_REG_SIZE); + endev->msix_tab = ioremap(pci_resource_start(hgdev->pdev, 0) + HGRNIC_MSIX_TAB_BASE, + HGRNIC_MSIX_TAB_SIZE); + endev->msix_pnd = ioremap(pci_resource_start(hgdev->pdev, 0) + HGRNIC_MSIX_PND_BASE, + HGRNIC_MSIX_PND_SIZE); + + return 0; +} +EXPORT_SYMBOL(hgrnic_register_en_driver); diff --git a/ETH-PLUS_Jingzhao/JingZhao2/software/drivers/ib_hgrnic/hgrnic_register.h b/ETH-PLUS_Jingzhao/JingZhao2/software/drivers/ib_hgrnic/hgrnic_register.h new file mode 100644 index 0000000000000000000000000000000000000000..a60f0978e5c157f9bafb680dc7b18c0e0987f585 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/software/drivers/ib_hgrnic/hgrnic_register.h @@ -0,0 +1,16 @@ +/************************************************************** + * @author Kang Ning, NCIC, ICT, CAS + * @date 2021.09.08 + * @file hgrnic_register.h + * @note Provide interface for ethernet driver registering + *************************************************************/ + +#ifndef __HGRNIC_REGISTER_H__ +#define __HGRNIC_REGISTER_H__ + +#include "hgrnic_dev.h" + +int hgrnic_init_en_register (struct hgrnic_dev* dev); + + +#endif // __HGRNIC_REGISTER_H__ \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/software/drivers/ib_hgrnic/hgrnic_uar.c b/ETH-PLUS_Jingzhao/JingZhao2/software/drivers/ib_hgrnic/hgrnic_uar.c new file mode 100644 index 0000000000000000000000000000000000000000..edc849cb25c92787e3e64cc75d513d9608660773 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/software/drivers/ib_hgrnic/hgrnic_uar.c @@ -0,0 +1,41 @@ +/************************************************************** + * @author Kang Ning, NCIC, ICT, CAS + * @date 2021.09.08 + * @file hgrnic_uar.c + * @note Functions related to uar space. + *************************************************************/ + +#include /* PAGE_SHIFT */ + +#include "hgrnic_dev.h" + +/** + * @note Allocate one page from BAR2 space(uar space). + */ +int hgrnic_uar_alloc (struct hgrnic_dev *dev, struct hgrnic_uar *uar) +{ + uar->index = hgrnic_alloc(&dev->uar_table.alloc); + if (uar->index == -1) + return -ENOMEM; + + uar->pfn = (pci_resource_start(dev->pdev, 2) >> PAGE_SHIFT) + uar->index; + + return 0; +} + +void hgrnic_uar_free (struct hgrnic_dev *dev, struct hgrnic_uar *uar) +{ + hgrnic_free(&dev->uar_table.alloc, uar->index); +} + +int hgrnic_init_uar_table (struct hgrnic_dev *dev) +{ + printk(KERN_INFO PFX "dev->limits.num_uars is %d\n", dev->limits.num_uars); + return hgrnic_alloc_init(&dev->uar_table.alloc, + dev->limits.num_uars, dev->limits.num_uars - 1); +} + +void hgrnic_cleanup_uar_table (struct hgrnic_dev *dev) +{ + hgrnic_alloc_cleanup(&dev->uar_table.alloc); +} diff --git a/ETH-PLUS_Jingzhao/JingZhao2/software/drivers/ib_hgrnic/hgrnic_wqe.h b/ETH-PLUS_Jingzhao/JingZhao2/software/drivers/ib_hgrnic/hgrnic_wqe.h new file mode 100644 index 0000000000000000000000000000000000000000..74fa60b98be540d32294bb2ca6a7d1ea0af72575 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/software/drivers/ib_hgrnic/hgrnic_wqe.h @@ -0,0 +1,137 @@ +/************************************************************** + * @author Kang Ning, NCIC, ICT, CAS + * @date 2021.08.30 + * @file hgrnic_wqe.h + * @note Functions & data structs related to RDMA WQE. + *************************************************************/ + +#ifndef __HGRNIC_WQE_H__ +#define __HGRNIC_WQE_H__ + +#include + +enum { + HGRNIC_NEXT_DBD = 1 << 7, + HGRNIC_NEXT_FENCE = 1 << 6, + HGRNIC_NEXT_CQ_UPDATE = 1 << 3, + HGRNIC_NEXT_EVENT_GEN = 1 << 2, + HGRNIC_NEXT_SOLICIT = 1 << 1 +}; + +enum { + HGRNIC_INVAL_LKEY = 0x100, + HGRNIC_MAX_WQES_PER_SEND_DB = 255 +}; + +struct hgrnic_next_unit { + __le32 nda_nop; /* [31:6] next WQE [4:0] next opcode */ + __le32 ee_nds; /* [31:8] next EE [7] DBD [6] F [5:0] next WQE size */ + __le32 flags; /* [3] CQ [2] Event [1] Solicit */ + __le32 imm; /* immediate data */ +}; + +struct hgrnic_ud_unit { + __le32 port; + __le16 slid; + __le16 dlid; + __le32 smac_h; + __le32 dmac_h; + u32 rsvd1[4]; + __le32 dqpn; + __le32 qkey; + u32 rsvd2[2]; +}; + +struct hgrnic_raddr_unit { + __le64 raddr; + __le32 rkey; + u32 reserved; +}; + +struct hgrnic_atomic_unit { + __le64 swap_add; + __le64 compare; +}; + +struct hgrnic_inline_unit { + __le32 length; +}; + +struct hgrnic_data_unit { + __le32 byte_count; + __le32 lkey; + __le64 addr; +}; + +static __always_inline void set_raddr_unit(struct hgrnic_raddr_unit *runit, + u64 remote_addr, u32 rkey) +{ + runit->raddr = cpu_to_le64(remote_addr); + runit->rkey = cpu_to_le32(rkey); + runit->reserved = 0; +} + +static __always_inline void set_atomic_seg(struct hgrnic_atomic_unit *aseg, + const struct ib_atomic_wr *wr) +{ + if (wr->wr.opcode == IB_WR_ATOMIC_CMP_AND_SWP) { + aseg->swap_add = cpu_to_be64(wr->swap); + aseg->compare = cpu_to_be64(wr->compare_add); + } else { + aseg->swap_add = cpu_to_be64(wr->compare_add); + aseg->compare = 0; + } +} + +static __always_inline void set_ud_unit(struct hgrnic_ud_unit *uunit, + const struct ib_ud_wr *wr) +{ + struct hgrnic_ah *hgah = to_hgah(wr->ah); + uunit->port = cpu_to_le32(hgah->port); + uunit->slid = cpu_to_le16(hgah->slid & 0xffff); + uunit->smac_h = cpu_to_le32((hgah->slid >> 16) & 0xffffffff); + uunit->dlid = cpu_to_le16(hgah->dlid & 0xffff); + uunit->dmac_h = cpu_to_le32((hgah->dlid >> 16) & 0xffffffff); +} + +static __always_inline void hgrnic_send_dbell(struct hgrnic_dev *dev, struct hgrnic_qp *qp, + int nreq, int size0, u32 f0, u8 op0) +{ + u32 dbhi, dblo; + + dbhi = (qp->qpn << 8) | size0; + dblo = ((qp->sq.head & 0xffff) << 8) | f0 | op0; + + qp->sq.head += nreq; + + wmb(); + hgrnic_write64(dbhi, dblo, dev->kar + HGRNIC_SEND_DOORBELL, + HGRNIC_GET_DOORBELL_LOCK(&dev->doorbell_lock)); + hgrnic_dump("0x%x", dbhi); + hgrnic_dump("0x%x", dblo); +} + +static __always_inline void hgrnic_set_inline_unit (struct hgrnic_inline_unit *unit, + u32 length, u8 *data) +{ + unit->length = (1 << 31) | length; + unit += sizeof(struct hgrnic_inline_unit); + memcpy(unit, data, length); +} + +static __always_inline void hgrnic_set_data_unit (struct hgrnic_data_unit *dunit, + struct ib_sge *sg) +{ + dunit->byte_count = cpu_to_le32(sg->length); + dunit->lkey = cpu_to_le32(sg->lkey); + dunit->addr = cpu_to_le64(sg->addr); +} + +static __always_inline void hgrnic_set_data_unit_inval(struct hgrnic_data_unit *dunit) +{ + dunit->byte_count = 0; + dunit->lkey = cpu_to_le32(HGRNIC_INVAL_LKEY); + dunit->addr = 0; +} + +#endif /* __HGRNIC_WQE_H__ */ diff --git a/ETH-PLUS_Jingzhao/JingZhao2/software/drivers/ib_hgrnic/ib_hgrnic.mod.c b/ETH-PLUS_Jingzhao/JingZhao2/software/drivers/ib_hgrnic/ib_hgrnic.mod.c new file mode 100644 index 0000000000000000000000000000000000000000..bfb36b1b78e339f33881a4c7d859770ff320fbf6 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/software/drivers/ib_hgrnic/ib_hgrnic.mod.c @@ -0,0 +1,29 @@ +#include +#include +#include +#include + +BUILD_SALT; + +MODULE_INFO(vermagic, VERMAGIC_STRING); +MODULE_INFO(name, KBUILD_MODNAME); + +__visible struct module __this_module +__section(.gnu.linkonce.this_module) = { + .name = KBUILD_MODNAME, + .init = init_module, +#ifdef CONFIG_MODULE_UNLOAD + .exit = cleanup_module, +#endif + .arch = MODULE_ARCH_INIT, +}; + +#ifdef CONFIG_RETPOLINE +MODULE_INFO(retpoline, "Y"); +#endif + +MODULE_INFO(depends, "ib_core,ib_uverbs"); + +MODULE_ALIAS("pci:v000010EEd00007028sv*sd*bc*sc*i*"); + +MODULE_INFO(srcversion, "E623B16ED6AEA179A1FE525"); diff --git a/ETH-PLUS_Jingzhao/JingZhao2/software/drivers/ib_hgrnic/include/rdma/hgrnic-abi.h b/ETH-PLUS_Jingzhao/JingZhao2/software/drivers/ib_hgrnic/include/rdma/hgrnic-abi.h new file mode 100644 index 0000000000000000000000000000000000000000..9edf65e826266c10b9e02f49b51e003e2eddbf79 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/software/drivers/ib_hgrnic/include/rdma/hgrnic-abi.h @@ -0,0 +1,84 @@ +/* + *======================= START OF LICENSE NOTICE ======================= + * Copyright (C) 2021 Kang Ning, NCIC, ICT, CAS. + * All Rights Reserved. + * + * NO WARRANTY. THE PRODUCT IS PROVIDED BY DEVELOPER "AS IS" AND ANY + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL DEVELOPER BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER + * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THE PRODUCT, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + *======================== END OF LICENSE NOTICE ======================== + * Primary Author: Kang Ning + * + */ +/** @file + * Configuration and initialization on the RNIC hardware. + * + */ + +#ifndef HGRNIC_ABI_USER_H +#define HGRNIC_ABI_USER_H + +#include + +/* + * Increment this value if any changes that break userspace ABI + * compatibility are made. + */ +#define HGRNIC_UVERBS_ABI_VERSION 1 + +/* + * Make sure that all structs defined in this file remain laid out so + * that they pack the same way on 32-bit and 64-bit architectures (to + * avoid incompatibility between 32-bit userspace and 64-bit kernels). + * In particular do not use pointer types -- pass pointers in __u64 + * instead. + */ +struct hgrnic_alloc_ucontext_resp { + __u32 qp_tab_size; + __u32 reserved; +}; + +struct hgrnic_alloc_pd_resp { + __u32 pdn; + __u32 reserved; +}; + +/* + * Mark the memory region with a DMA attribute that causes + * in-flight DMA to be flushed when the region is written to: + */ +#define HGRNIC_MR_DMASYNC 0x1 + +struct hgrnic_reg_mr { + __u32 mr_attrs; + __u32 reserved; +}; + +struct hgrnic_create_cq { + __u32 lkey; + __u32 pdn; +}; + +struct hgrnic_create_cq_resp { + __u32 cqn; + __u32 reserved; +}; + +struct hgrnic_resize_cq { + __u32 lkey; + __u32 reserved; +}; + +struct hgrnic_create_qp { + __u32 rq_lkey; + __u32 sq_lkey; +}; +#endif /* HGRNIC_ABI_USER_H */ diff --git a/ETH-PLUS_Jingzhao/JingZhao2/software/drivers/ib_hgrnic/include/uapi/rdma/rdma_user_ioctl_cmds.h b/ETH-PLUS_Jingzhao/JingZhao2/software/drivers/ib_hgrnic/include/uapi/rdma/rdma_user_ioctl_cmds.h new file mode 100644 index 0000000000000000000000000000000000000000..91483a6b4a4acc676a5846532612f88803a93cbf --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/software/drivers/ib_hgrnic/include/uapi/rdma/rdma_user_ioctl_cmds.h @@ -0,0 +1,110 @@ +/* + * Copyright (c) 2018, Mellanox Technologies inc. All rights reserved. + * + * This software is available to you under a choice of one of two + * licenses. You may choose to be licensed under the terms of the GNU + * General Public License (GPL) Version 2, available from the file + * COPYING in the main directory of this source tree, or the + * OpenIB.org BSD license below: + * + * Redistribution and use in source and binary forms, with or + * without modification, are permitted provided that the following + * conditions are met: + * + * - Redistributions of source code must retain the above + * copyright notice, this list of conditions and the following + * disclaimer. + * + * - Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials + * provided with the distribution. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#ifndef RDMA_USER_IOCTL_CMDS_H +#define RDMA_USER_IOCTL_CMDS_H + +#include +#include + +/* Documentation/ioctl/ioctl-number.rst */ +#define RDMA_IOCTL_MAGIC 0x1b +#define RDMA_VERBS_IOCTL \ + _IOWR(RDMA_IOCTL_MAGIC, 1, struct ib_uverbs_ioctl_hdr) + +enum { + /* User input */ + UVERBS_ATTR_F_MANDATORY = 1U << 0, + /* + * Valid output bit should be ignored and considered set in + * mandatory fields. This bit is kernel output. + */ + UVERBS_ATTR_F_VALID_OUTPUT = 1U << 1, +}; + +struct ib_uverbs_attr { + __u16 attr_id; /* command specific type attribute */ + __u16 len; /* only for pointers and IDRs array */ + __u16 flags; /* combination of UVERBS_ATTR_F_XXXX */ + union { + struct { + __u8 elem_id; + __u8 reserved; + } enum_data; + __u16 reserved; + } attr_data; + union { + /* + * ptr to command, inline data, idr/fd or + * ptr to __u32 array of IDRs + */ + __aligned_u64 data; + /* Used by FD_IN and FD_OUT */ + __s64 data_s64; + }; +}; + +struct ib_uverbs_ioctl_hdr { + __u16 length; + __u16 object_id; + __u16 method_id; + __u16 num_attrs; + __aligned_u64 reserved1; + __u32 driver_id; + __u32 reserved2; + struct ib_uverbs_attr attrs[0]; +}; + +enum rdma_driver_id { + RDMA_DRIVER_UNKNOWN, + RDMA_DRIVER_MLX5, + RDMA_DRIVER_MLX4, + RDMA_DRIVER_CXGB3, + RDMA_DRIVER_CXGB4, + RDMA_DRIVER_MTHCA, + RDMA_DRIVER_BNXT_RE, + RDMA_DRIVER_OCRDMA, + RDMA_DRIVER_NES, + RDMA_DRIVER_I40IW, + RDMA_DRIVER_VMW_PVRDMA, + RDMA_DRIVER_QEDR, + RDMA_DRIVER_HNS, + RDMA_DRIVER_USNIC, + RDMA_DRIVER_RXE, + RDMA_DRIVER_HFI1, + RDMA_DRIVER_QIB, + RDMA_DRIVER_EFA, + RDMA_DRIVER_SIW, + RDMA_DRIVER_HGRNIC, +}; + +#endif diff --git a/ETH-PLUS_Jingzhao/JingZhao2/software/drivers/libhgrnic/README.md b/ETH-PLUS_Jingzhao/JingZhao2/software/drivers/libhgrnic/README.md new file mode 100644 index 0000000000000000000000000000000000000000..60321822317f11da754c7a44407fb3620dcd9f5c --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/software/drivers/libhgrnic/README.md @@ -0,0 +1,38 @@ +Introduction +============ + +libhgrnic is a userspace driver for Han Gu RNIC. It works +as a plug-in module for libibverbs that allows programs to use +ICT hardware directly from userspace. See the libibverbs package +for more information. Currently, the project is only matched with +libibverbs V1.1.2 + +Using libhgrnic +============== + +libhgrnic will be loaded and used automatically by programs linked with +libibverbs. The ib_hgrnic kernel module must be loaded for HCA devices +to be detected and used. + +How to Compile +============== + +Enter the working directory, executte the command in the following +sequence: + +```bash +aclocal +autoconf +autoheader +mkdir config +libtoolize --automake --copy --debug --force +automake --add-missing +./configure +make && make install +``` + + +Supported Hardware +================== + +libhgrnic currently supports all kind of RNIC of Han Gu series. diff --git a/ETH-PLUS_Jingzhao/JingZhao2/software/drivers/libhgrnic/config.h b/ETH-PLUS_Jingzhao/JingZhao2/software/drivers/libhgrnic/config.h new file mode 100644 index 0000000000000000000000000000000000000000..302fffca772108da4caa192abf1e244833ae64fb --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/software/drivers/libhgrnic/config.h @@ -0,0 +1,89 @@ +/* config.h. Generated from config.h.in by configure. */ +/* config.h.in. Generated from configure.ac by autoheader. */ + +/* Define to 1 if you have the header file. */ +#define HAVE_DLFCN_H 1 + +/* Define to 1 if you have the `ibv_dofork_range' function. */ +#define HAVE_IBV_DOFORK_RANGE 1 + +/* Define to 1 if you have the `ibv_dontfork_range' function. */ +#define HAVE_IBV_DONTFORK_RANGE 1 + +/* Define to 1 if you have the `ibv_read_sysfs_file' function. */ +#define HAVE_IBV_READ_SYSFS_FILE 1 + +/* Define to 1 if you have the `ibv_register_driver' function. */ +#define HAVE_IBV_REGISTER_DRIVER 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_INTTYPES_H 1 + +/* Define to 1 if you have the `ibverbs' library (-libverbs). */ +#define HAVE_LIBIBVERBS 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_MEMORY_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_STDINT_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_STDLIB_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_STRINGS_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_STRING_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_SYS_STAT_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_SYS_TYPES_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_UNISTD_H 1 + +/* Define to 1 if you have the header file. */ +/* #undef HAVE_VALGRIND_MEMCHECK_H */ + +/* Define to the sub-directory where libtool stores uninstalled libraries. */ +#define LT_OBJDIR ".libs/" + +/* Define to 1 to disable Valgrind annotations. */ +#define NVALGRIND 1 + +/* Name of package */ +#define PACKAGE "libhgrnic" + +/* Define to the address where bug reports for this package should be sent. */ +#define PACKAGE_BUGREPORT "kangning18z@ict.ac.cn" + +/* Define to the full name of this package. */ +#define PACKAGE_NAME "libhgrnic" + +/* Define to the full name and version of this package. */ +#define PACKAGE_STRING "libhgrnic 1.0" + +/* Define to the one symbol short name of this package. */ +#define PACKAGE_TARNAME "libhgrnic" + +/* Define to the home page for this package. */ +#define PACKAGE_URL "" + +/* Define to the version of this package. */ +#define PACKAGE_VERSION "1.0" + +/* The size of `long', as computed by sizeof. */ +#define SIZEOF_LONG 8 + +/* Define to 1 if you have the ANSI C header files. */ +#define STDC_HEADERS 1 + +/* Version number of package */ +#define VERSION "1.0" + +/* Define to empty if `const' does not conform to ANSI C. */ +/* #undef const */ diff --git a/ETH-PLUS_Jingzhao/JingZhao2/software/drivers/libhgrnic/src/ah.c b/ETH-PLUS_Jingzhao/JingZhao2/software/drivers/libhgrnic/src/ah.c new file mode 100644 index 0000000000000000000000000000000000000000..efab96f3f31abd0595351288558dc699bef16f30 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/software/drivers/libhgrnic/src/ah.c @@ -0,0 +1,79 @@ +/* + * Copyright (c) 2005 Topspin Communications. All rights reserved. + * + * This software is available to you under a choice of one of two + * licenses. You may choose to be licensed under the terms of the GNU + * General Public License (GPL) Version 2, available from the file + * COPYING in the main directory of this source tree, or the + * OpenIB.org BSD license below: + * + * Redistribution and use in source and binary forms, with or + * without modification, are permitted provided that the following + * conditions are met: + * + * - Redistributions of source code must retain the above + * copyright notice, this list of conditions and the following + * disclaimer. + * + * - Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials + * provided with the distribution. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#if HAVE_CONFIG_H +# include +#endif /* HAVE_CONFIG_H */ + +#include +#include +#include +#include + +#include "hgrnic.h" + +int hgrnic_alloc_av(struct hgrnic_pd *pd, struct ibv_ah_attr *attr, + struct hgrnic_ah *ah) +{ + ah->av = malloc(sizeof *ah->av); + if (!ah->av) + return -1; + + memset(ah->av, 0, sizeof *ah->av); + + ah->av->port_pd = pd->pdn | (attr->port_num << 24); + ah->av->g_slid = attr->src_path_bits; + ah->av->dlid = attr->dlid; + ah->av->msg_sr = (3 << 4) | /* 2K message */ + attr->static_rate; + ah->av->sl_tclass_flowlabel = attr->sl << 28; + if (attr->is_global) { + ah->av->g_slid |= 0x80; + /* XXX get gid_table length */ + ah->av->gid_index = (attr->port_num - 1) * 32 + + attr->grh.sgid_index; + ah->av->hop_limit = attr->grh.hop_limit; + ah->av->sl_tclass_flowlabel |= + (attr->grh.traffic_class << 20) | + attr->grh.flow_label; + memcpy(ah->av->dgid, attr->grh.dgid.raw, 16); + } else { + ah->av->dgid[3] = 2; + } + + return 0; +} + +void hgrnic_free_av(struct hgrnic_ah *ah) +{ + free(ah->av); +} diff --git a/ETH-PLUS_Jingzhao/JingZhao2/software/drivers/libhgrnic/src/buf.c b/ETH-PLUS_Jingzhao/JingZhao2/software/drivers/libhgrnic/src/buf.c new file mode 100644 index 0000000000000000000000000000000000000000..e69248430d6d94071014c01eb329b9156dc988a3 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/software/drivers/libhgrnic/src/buf.c @@ -0,0 +1,83 @@ +/* + * Copyright (c) 2006 Cisco Systems, Inc. All rights reserved. + * + * This software is available to you under a choice of one of two + * licenses. You may choose to be licensed under the terms of the GNU + * General Public License (GPL) Version 2, available from the file + * COPYING in the main directory of this source tree, or the + * OpenIB.org BSD license below: + * + * Redistribution and use in source and binary forms, with or + * without modification, are permitted provided that the following + * conditions are met: + * + * - Redistributions of source code must retain the above + * copyright notice, this list of conditions and the following + * disclaimer. + * + * - Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials + * provided with the distribution. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#if HAVE_CONFIG_H +# include +#endif /* HAVE_CONFIG_H */ + +#include +#include +#include + +#include "hgrnic.h" + +#if !(defined(HAVE_IBV_DONTFORK_RANGE) && defined(HAVE_IBV_DOFORK_RANGE)) + +/* + * If libibverbs isn't exporting these functions, then there's no + * point in doing it here, because the rest of libibverbs isn't going + * to be fork-safe anyway. + */ +static int ibv_dontfork_range(void *base, size_t size) +{ + return 0; +} + +static int ibv_dofork_range(void *base, size_t size) +{ + return 0; +} + +#endif /* HAVE_IBV_DONTFORK_RANGE && HAVE_IBV_DOFORK_RANGE */ + +int hgrnic_alloc_buf(struct hgrnic_buf *buf, size_t size, int page_size) +{ + int ret; + + buf->length = align(size, page_size); + buf->buf = mmap(NULL, buf->length, PROT_READ | PROT_WRITE, + MAP_PRIVATE | MAP_ANONYMOUS, -1, 0); + if (buf->buf == MAP_FAILED) + return errno; + + ret = ibv_dontfork_range(buf->buf, size); + if (ret) + munmap(buf->buf, buf->length); + + return ret; +} + +void hgrnic_free_buf(struct hgrnic_buf *buf) +{ + ibv_dofork_range(buf->buf, buf->length); + munmap(buf->buf, buf->length); +} diff --git a/ETH-PLUS_Jingzhao/JingZhao2/software/drivers/libhgrnic/src/cq.c b/ETH-PLUS_Jingzhao/JingZhao2/software/drivers/libhgrnic/src/cq.c new file mode 100644 index 0000000000000000000000000000000000000000..96bb9782f8752d6fe2e772baa4aa6393690365cb --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/software/drivers/libhgrnic/src/cq.c @@ -0,0 +1,475 @@ +#if HAVE_CONFIG_H +# include +#endif /* HAVE_CONFIG_H */ + +#include +#include +#include +#include +#include + +#include + +#include "hgrnic.h" +#include "wqe.h" + + +enum { + CQ_OK = 0, + CQ_EMPTY = -1, + CQ_POLL_ERR = -2 +}; + +enum { + HGRNIC_CQ_ENTRY_OWNER_SW = 0x00, + HGRNIC_CQ_ENTRY_OWNER_HW = 0x80, + HGRNIC_ERROR_CQE_OPCODE_MASK = 0xfe +}; + +enum { + SYNDROME_LOCAL_LENGTH_ERR = 0x01, + SYNDROME_LOCAL_QP_OP_ERR = 0x02, + SYNDROME_LOCAL_EEC_OP_ERR = 0x03, + SYNDROME_LOCAL_PROT_ERR = 0x04, + SYNDROME_WR_FLUSH_ERR = 0x05, + SYNDROME_MW_BIND_ERR = 0x06, + SYNDROME_BAD_RESP_ERR = 0x10, + SYNDROME_LOCAL_ACCESS_ERR = 0x11, + SYNDROME_REMOTE_INVAL_REQ_ERR = 0x12, + SYNDROME_REMOTE_ACCESS_ERR = 0x13, + SYNDROME_REMOTE_OP_ERR = 0x14, + SYNDROME_RETRY_EXC_ERR = 0x15, + SYNDROME_RNR_RETRY_EXC_ERR = 0x16, + SYNDROME_LOCAL_RDD_VIOL_ERR = 0x20, + SYNDROME_REMOTE_INVAL_RD_REQ_ERR = 0x21, + SYNDROME_REMOTE_ABORTED_ERR = 0x22, + SYNDROME_INVAL_EECN_ERR = 0x23, + SYNDROME_INVAL_EEC_STATE_ERR = 0x24 +}; + +struct hgrnic_cqe { + uint32_t my_qpn; + uint32_t my_ee; + uint32_t rqpn; + uint8_t sl_ipok; + uint8_t g_mlpath; + uint16_t rlid; + uint32_t imm; + uint32_t byte_cnt; + uint32_t wqe; // addr offset of completed wqe + uint8_t opcode; + uint8_t is_send; + uint8_t reserved; + uint8_t owner; +}; + +struct hgrnic_err_cqe { + uint32_t my_qpn; + uint32_t reserved1[3]; + uint8_t syndrome; + uint8_t vendor_err; + uint16_t db_cnt; + uint32_t reserved2; + uint32_t wqe; + uint8_t opcode; + uint8_t reserved3[2]; + uint8_t owner; +}; + +static inline struct hgrnic_cqe *get_cqe(struct hgrnic_cq *cq, int entry) +{ + return cq->buf.buf + entry * HGRNIC_CQ_ENTRY_SIZE; +} + +static inline struct hgrnic_cqe *cqe_sw(struct hgrnic_cq *cq, int i) +{ + struct hgrnic_cqe *cqe = get_cqe(cq, i); + return HGRNIC_CQ_ENTRY_OWNER_HW & cqe->owner ? NULL : cqe; +} + +static inline struct hgrnic_cqe *next_cqe_sw(struct hgrnic_cq *cq) +{ + return cqe_sw(cq, cq->cons_index & cq->cqe_mask); +} + +static inline void set_cqe_hw(struct hgrnic_cqe *cqe) +{ + VALGRIND_MAKE_MEM_UNDEFINED(cqe, sizeof *cqe); + cqe->owner = HGRNIC_CQ_ENTRY_OWNER_HW; +} + +static void dump_cqe(void *cqe_ptr) +{ + uint32_t *cqe = cqe_ptr; + int i; + + //for (i = 0; i < 8; ++i) + // printf(" [%2x] %08x\n", i * 4, ((uint32_t *) cqe)[i]); +} + +static int handle_error_cqe(struct hgrnic_cq *cq, + struct hgrnic_qp *qp, int wqe_index, int is_send, + struct hgrnic_err_cqe *cqe, + struct ibv_wc *wc) +{ + if (cqe->syndrome == SYNDROME_LOCAL_QP_OP_ERR) { + //printf("local QP operation err " + // "(QPN %06x, WQE @ %08x, CQN %06x, index %d)\n", + // ntohl(cqe->my_qpn), ntohl(cqe->wqe), + // cq->cqn, cq->cons_index); + //dump_cqe(cqe); + } + + /* + * For completions in error, only work request ID, status, vendor error + * (and freed resource count for RD) have to be set. + */ + switch (cqe->syndrome) { + case SYNDROME_LOCAL_LENGTH_ERR: + wc->status = IBV_WC_LOC_LEN_ERR; + break; + case SYNDROME_LOCAL_QP_OP_ERR: + wc->status = IBV_WC_LOC_QP_OP_ERR; + break; + case SYNDROME_LOCAL_EEC_OP_ERR: + wc->status = IBV_WC_LOC_EEC_OP_ERR; + break; + case SYNDROME_LOCAL_PROT_ERR: + wc->status = IBV_WC_LOC_PROT_ERR; + break; + case SYNDROME_WR_FLUSH_ERR: + wc->status = IBV_WC_WR_FLUSH_ERR; + break; + case SYNDROME_MW_BIND_ERR: + wc->status = IBV_WC_MW_BIND_ERR; + break; + case SYNDROME_BAD_RESP_ERR: + wc->status = IBV_WC_BAD_RESP_ERR; + break; + case SYNDROME_LOCAL_ACCESS_ERR: + wc->status = IBV_WC_LOC_ACCESS_ERR; + break; + case SYNDROME_REMOTE_INVAL_REQ_ERR: + wc->status = IBV_WC_REM_INV_REQ_ERR; + break; + case SYNDROME_REMOTE_ACCESS_ERR: + wc->status = IBV_WC_REM_ACCESS_ERR; + break; + case SYNDROME_REMOTE_OP_ERR: + wc->status = IBV_WC_REM_OP_ERR; + break; + case SYNDROME_RETRY_EXC_ERR: + wc->status = IBV_WC_RETRY_EXC_ERR; + break; + case SYNDROME_RNR_RETRY_EXC_ERR: + wc->status = IBV_WC_RNR_RETRY_EXC_ERR; + break; + case SYNDROME_LOCAL_RDD_VIOL_ERR: + wc->status = IBV_WC_LOC_RDD_VIOL_ERR; + break; + case SYNDROME_REMOTE_INVAL_RD_REQ_ERR: + wc->status = IBV_WC_REM_INV_RD_REQ_ERR; + break; + case SYNDROME_REMOTE_ABORTED_ERR: + wc->status = IBV_WC_REM_ABORT_ERR; + break; + case SYNDROME_INVAL_EECN_ERR: + wc->status = IBV_WC_INV_EECN_ERR; + break; + case SYNDROME_INVAL_EEC_STATE_ERR: + wc->status = IBV_WC_INV_EEC_STATE_ERR; + break; + default: + wc->status = IBV_WC_GENERAL_ERR; + break; + } + + wc->vendor_err = cqe->vendor_err; + + return 0; +} + +static inline int hgrnic_poll_one(struct hgrnic_cq *cq, + struct hgrnic_qp **cur_qp, + struct ibv_wc *wc) +{ + struct hgrnic_cqe *cqe; + struct hgrnic_wq *wq; + int wqe_index; + int is_error; + int is_send; + int err = 0; + + cqe = next_cqe_sw(cq); + if (!cqe) + return CQ_EMPTY; + + VALGRIND_MAKE_MEM_DEFINED(cqe, sizeof *cqe); + + /* + * Make sure we read CQ entry contents after we've checked the + * ownership bit. + */ + rmb(); + + is_error = (cqe->opcode == HGRNIC_OPCODE_SEND_ERR) || + (cqe->opcode == HGRNIC_OPCODE_RECV_ERR); + is_send = is_error ? (cqe->opcode == HGRNIC_OPCODE_SEND_ERR) + : cqe->is_send; + + //printf("hgrnic_poll_one: get cqe! is_error %d, is_send %d\n", is_error, is_send); + //if ((cq->buf.length / 4096) == 4) { + // printf("lkey 0x%x, cqn 0x%x, mask 0x%x cmp_index %d\n", cq->mr->lkey, cq->cqn, cq->cqe_mask, cq->cons_index); + // printf("CQE vaddr 0x%lx\n", (uint64_t)cq->buf.buf); + // for (int j = 0; j < (cq->buf.length / 4096); ++j) { + // for (int i = 0; i < 2; ++i) { + // printf("\tCurrent CQE address %lx\n : ", (uint64_t)(cq->buf.buf + j * 4096 + i * 32)); + // printf("\tCQ Page Index: %d,\n \t\tCQE Index in Page: %d,\n \t\t\tcqe[0]: 0x%x; cqe[1]: 0x%x; cqe[2]: 0x%x; cqe[3]: 0x%x; cqe[4]: 0x%x; cqe[5]: 0x%x; cqe[6]: 0x%x; cqe[7]: 0x%x\n", + // j, + // i, + // ((uint32_t *)(cq->buf.buf + j * 4096))[i * 8 + 0], + // ((uint32_t *)(cq->buf.buf + j * 4096))[i * 8 + 1], + // ((uint32_t *)(cq->buf.buf + j * 4096))[i * 8 + 2], + // ((uint32_t *)(cq->buf.buf + j * 4096))[i * 8 + 3], + // ((uint32_t *)(cq->buf.buf + j * 4096))[i * 8 + 4], + // ((uint32_t *)(cq->buf.buf + j * 4096))[i * 8 + 5], + // ((uint32_t *)(cq->buf.buf + j * 4096))[i * 8 + 6], + // ((uint32_t *)(cq->buf.buf + j * 4096))[i * 8 + 7]); + // } + // } + //} + + //if(!is_send) { + // printf("Get a recv cqe!\n"); + // printf("is_send %d\n", is_send); + // printf("is_error %d\n", is_error); + //} + + if (!*cur_qp || cqe->my_qpn != (*cur_qp)->ibv_qp.qp_num) { + /* + * We do not have to take the QP table lock here, + * because CQs will be locked while QPs are removed + * from the table. + */ + *cur_qp = hgrnic_find_qp(to_hgctx(cq->ibv_cq.context), cqe->my_qpn); + if (!*cur_qp) { + err = CQ_POLL_ERR; + goto out; + } + } + + wc->qp_num = (*cur_qp)->ibv_qp.qp_num; + + if (is_send) { + wq = &(*cur_qp)->sq; + wqe_index = cqe->wqe >> wq->wqe_shift; + wc->wr_id = (*cur_qp)->sq.wrid[wqe_index]; + } else { + wq = &(*cur_qp)->rq; + wqe_index = cqe->wqe >> wq->wqe_shift; + wc->wr_id = (*cur_qp)->rq.wrid[wqe_index]; + + /* clear valid bit in next_unit */ + memset(wq->buf.buf + cqe->wqe, 0, sizeof(struct hgrnic_next_unit)); + } + + if (wq) { + if (wq->last_comp < wqe_index) + wq->tail += wqe_index - wq->last_comp; + else + wq->tail += wqe_index + wq->max - wq->last_comp; + + if(is_send) { + //fprintf(stderr, "Get a Send CQE:\n\twq->tail = %lx, wq->last_comp = %lx, wqe_index = %lx\n", wq->tail, wq->last_comp, wqe_index); + } + else { + //fprintf(stderr, "Get a Recv CQE:\n\twq->tail = %lx, wq->last_comp = %lx, wqe_index = %lx\n", wq->tail, wq->last_comp, wqe_index); + } + + wq->last_comp = wqe_index; + } + + if (is_error) { + err = handle_error_cqe(cq, *cur_qp, wqe_index, is_send, + (struct hgrnic_err_cqe *) cqe, + wc); + goto out; + } + + if (is_send) { + wc->wc_flags = 0; + switch (cqe->opcode) { + case HGRNIC_OPCODE_RDMA_WRITE: + wc->opcode = IBV_WC_RDMA_WRITE; + break; + case HGRNIC_OPCODE_RDMA_WRITE_IMM: + wc->opcode = IBV_WC_RDMA_WRITE; + wc->wc_flags |= IBV_WC_WITH_IMM; + break; + case HGRNIC_OPCODE_SEND: + wc->opcode = IBV_WC_SEND; + break; + case HGRNIC_OPCODE_SEND_IMM: + wc->opcode = IBV_WC_SEND; + wc->wc_flags |= IBV_WC_WITH_IMM; + break; + case HGRNIC_OPCODE_RDMA_READ: + wc->opcode = IBV_WC_RDMA_READ; + wc->byte_len = cqe->byte_cnt; + break; + case HGRNIC_OPCODE_ATOMIC_CS: + wc->opcode = IBV_WC_COMP_SWAP; + wc->byte_len = cqe->byte_cnt; + break; + case HGRNIC_OPCODE_ATOMIC_FA: + wc->opcode = IBV_WC_FETCH_ADD; + wc->byte_len = cqe->byte_cnt; + break; + case HGRNIC_OPCODE_BIND_MW: + wc->opcode = IBV_WC_BIND_MW; + break; + default: + /* assume it's a send completion */ + wc->opcode = IBV_WC_SEND; + break; + } + } else { + wc->byte_len = cqe->byte_cnt; + switch (cqe->opcode & 0x1f) { + case IBV_OPCODE_SEND_LAST_WITH_IMMEDIATE: + case IBV_OPCODE_SEND_ONLY_WITH_IMMEDIATE: + wc->wc_flags = IBV_WC_WITH_IMM; + wc->imm_data = cqe->imm; + wc->opcode = IBV_WC_RECV; + break; + case IBV_OPCODE_RDMA_WRITE_LAST_WITH_IMMEDIATE: + case IBV_OPCODE_RDMA_WRITE_ONLY_WITH_IMMEDIATE: + wc->wc_flags = IBV_WC_WITH_IMM; + wc->imm_data = cqe->imm; + wc->opcode = IBV_WC_RECV_RDMA_WITH_IMM; + break; + default: + wc->wc_flags = 0; + wc->opcode = IBV_WC_RECV; + break; + } + wc->slid = cqe->rlid; + wc->src_qp = cqe->rqpn & 0xffffff; + + wc->sl = 0; /* This is not used */ + wc->dlid_path_bits = 0; /* This is not used */ + wc->pkey_index = 0; /* This is not used */ + } + + wc->status = IBV_WC_SUCCESS; + +out: + set_cqe_hw(cqe); + ++cq->cons_index; + + return err; +} + +int hgrnic_notify_cq(struct ibv_cq *cq, int solicited_only) { + return 0; +} + +int hgrnic_poll_cq(struct ibv_cq *ibcq, int ne, struct ibv_wc *wc) +{ + struct hgrnic_cq *cq = to_hgcq(ibcq); + struct hgrnic_qp *qp = NULL; + int err = CQ_OK; + int npolled; + + pthread_spin_lock(&cq->lock); + + for (npolled = 0; npolled < ne; ++npolled) { + err = hgrnic_poll_one(cq, &qp, wc + npolled); + if (err != CQ_OK) + break; + } + + pthread_spin_unlock(&cq->lock); + + return err == CQ_POLL_ERR ? err : npolled; +} + +static inline int is_recv_cqe(struct hgrnic_cqe *cqe) +{ + if ((cqe->opcode & HGRNIC_ERROR_CQE_OPCODE_MASK) == + HGRNIC_ERROR_CQE_OPCODE_MASK) + return !(cqe->opcode & 0x01); + else + return !(cqe->is_send & 0x80); +} + +void __hgrnic_cq_clean(struct hgrnic_cq *cq, uint32_t qpn) +{ + struct hgrnic_cqe *cqe; + uint32_t prod_index; + int i, nfreed = 0; + + /* + * First we need to find the current producer index, so we + * know where to start cleaning from. It doesn't matter if HW + * adds new entries after this loop -- the QP we're worried + * about is already in RESET, so the new entries won't come + * from our QP and therefore don't need to be checked. + */ + for (prod_index = cq->cons_index; + cqe_sw(cq, prod_index & cq->ibv_cq.cqe); + ++prod_index) + if (prod_index == cq->cons_index + cq->ibv_cq.cqe) + break; + + /* + * Now sweep backwards through the CQ, removing CQ entries + * that match our QP by copying older entries on top of them. + */ + while ((int) --prod_index - (int) cq->cons_index >= 0) { + cqe = get_cqe(cq, prod_index & cq->ibv_cq.cqe); + //printf("[__hgrnic_cq_clean] my_qpn is 0x%x, qpn is 0x%x\n", cqe->my_qpn, qpn); + if (cqe->my_qpn == qpn) // !TODO: The order need to notice + ++nfreed; + else if (nfreed) + memcpy(get_cqe(cq, (prod_index + nfreed) & cq->ibv_cq.cqe), + cqe, HGRNIC_CQ_ENTRY_SIZE); + } + + if (nfreed) { + for (i = 0; i < nfreed; ++i) + set_cqe_hw(get_cqe(cq, (cq->cons_index + i) & cq->ibv_cq.cqe)); + wmb(); + cq->cons_index += nfreed; + } +} + +void hgrnic_cq_clean(struct hgrnic_cq *cq, uint32_t qpn) +{ + pthread_spin_lock(&cq->lock); + __hgrnic_cq_clean(cq, qpn); + pthread_spin_unlock(&cq->lock); +} + +void hgrnic_cq_resize_copy_cqes(struct hgrnic_cq *cq, void *buf, int old_cqe) +{ + int i; + + for (i = cq->cons_index; cqe_sw(cq, i & old_cqe); ++i) + memcpy(buf + (i & cq->ibv_cq.cqe) * HGRNIC_CQ_ENTRY_SIZE, + get_cqe(cq, i & old_cqe), HGRNIC_CQ_ENTRY_SIZE); +} + +int hgrnic_alloc_cq_buf(struct hgrnic_device *dev, struct hgrnic_buf *buf, int nent) +{ + int i; + + if (hgrnic_alloc_buf(buf, align(nent * HGRNIC_CQ_ENTRY_SIZE, dev->page_size), + dev->page_size)) + return -1; + + for (i = 0; i < nent; ++i) + ((struct hgrnic_cqe *) buf->buf)[i].owner = HGRNIC_CQ_ENTRY_OWNER_HW; + + return 0; +} diff --git a/ETH-PLUS_Jingzhao/JingZhao2/software/drivers/libhgrnic/src/doorbell.h b/ETH-PLUS_Jingzhao/JingZhao2/software/drivers/libhgrnic/src/doorbell.h new file mode 100644 index 0000000000000000000000000000000000000000..a5847afaa988ce3f272cd7a51b078d5a9fa148f5 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/software/drivers/libhgrnic/src/doorbell.h @@ -0,0 +1,80 @@ +/* + * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved. + * + * This software is available to you under a choice of one of two + * licenses. You may choose to be licensed under the terms of the GNU + * General Public License (GPL) Version 2, available from the file + * COPYING in the main directory of this source tree, or the + * OpenIB.org BSD license below: + * + * Redistribution and use in source and binary forms, with or + * without modification, are permitted provided that the following + * conditions are met: + * + * - Redistributions of source code must retain the above + * copyright notice, this list of conditions and the following + * disclaimer. + * + * - Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials + * provided with the distribution. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#ifndef DOORBELL_H +#define DOORBELL_H + +#ifdef __i386__ + +static inline void hgrnic_write64(uint32_t val[2], struct hgrnic_context *ctx, int offset) +{ + /* i386 stack is aligned to 8 bytes, so this should be OK: */ + uint8_t xmmsave[8] __attribute__((aligned(8))); + + asm volatile ( + "movlps %%xmm0,(%0); \n\t" + "movlps (%1),%%xmm0; \n\t" + "movlps %%xmm0,(%2); \n\t" + "movlps (%0),%%xmm0; \n\t" + : + : "r" (xmmsave), "r" (val), "r" (ctx->uar + offset) + : "memory" ); +} + +#elif SIZEOF_LONG == 8 + +#if __BYTE_ORDER == __LITTLE_ENDIAN +# define HGRNIC_PAIR_TO_64(val) ((uint64_t) val[1] << 32 | val[0]) +#elif __BYTE_ORDER == __BIG_ENDIAN +# define HGRNIC_PAIR_TO_64(val) ((uint64_t) val[0] << 32 | val[1]) +#else +# error __BYTE_ORDER not defined +#endif + +static inline void hgrnic_write64(uint32_t val[2], struct hgrnic_context *ctx, int offset) +{ + *(volatile uint64_t *) (ctx->uar + offset) = HGRNIC_PAIR_TO_64(val); +} + +#else + +static inline void hgrnic_write64(uint32_t val[2], struct hgrnic_context *ctx, int offset) +{ + pthread_spin_lock(&ctx->uar_lock); + *(volatile uint32_t *) (ctx->uar + offset) = val[0]; + *(volatile uint32_t *) (ctx->uar + offset + 4) = val[1]; + pthread_spin_unlock(&ctx->uar_lock); +} + +#endif + +#endif /* HGRNIC_H */ diff --git a/ETH-PLUS_Jingzhao/JingZhao2/software/drivers/libhgrnic/src/hgrnic-abi.h b/ETH-PLUS_Jingzhao/JingZhao2/software/drivers/libhgrnic/src/hgrnic-abi.h new file mode 100644 index 0000000000000000000000000000000000000000..93ea45e30d2fe6c61ce80ac1cff26471c0bc5889 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/software/drivers/libhgrnic/src/hgrnic-abi.h @@ -0,0 +1,78 @@ +/* + *======================= START OF LICENSE NOTICE ======================= + * Copyright (C) 2021 Kang Ning, NCIC, ICT, CAS. + * All Rights Reserved. + * + * NO WARRANTY. THE PRODUCT IS PROVIDED BY DEVELOPER "AS IS" AND ANY + * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL DEVELOPER BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER + * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR + * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THE PRODUCT, EVEN + * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + *======================== END OF LICENSE NOTICE ======================== + * Primary Author: Kang Ning + * + */ + +#ifndef HGRNIC_ABI_USER_H +#define HGRNIC_ABI_USER_H + +#include + +#define HGRNIC_UVERBS_ABI_VERSION 1 + +struct hgrnic_alloc_ucontext_resp { + struct ibv_get_context_resp ibv_resp; + __u32 qp_tab_size; + __u32 reserved; +}; + +struct hgrnic_alloc_pd_resp { + struct ibv_alloc_pd_resp ibv_resp; + __u32 pdn; + __u32 reserved; +}; + + +/* + * Mark the memory region with a DMA attribute that causes + * in-flight DMA to be flushed when the region is written to: + */ +#define HGRNIC_MR_DMASYNC 0x1 + +struct hgrnic_reg_mr { + struct ibv_reg_mr ibv_cmd; + __u32 mr_attrs; + __u32 reserved; +}; + +struct hgrnic_create_cq { + struct ibv_create_cq ibv_cmd; + __u32 lkey ; + __u32 pdn ; +}; + +struct hgrnic_create_cq_resp { + struct ibv_create_cq_resp ibv_resp; + __u32 cqn ; + __u32 reserved; +}; + +struct hgrnic_resize_cq { + struct ibv_resize_cq ibv_cmd ; + __u32 lkey ; + __u32 reserved; +}; + +struct hgrnic_create_qp { + struct ibv_create_qp ibv_cmd; + __u32 rq_lkey; + __u32 sq_lkey; +}; + +#endif /* HGRNIC_ABI_USER_H */ \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/software/drivers/libhgrnic/src/hgrnic.c b/ETH-PLUS_Jingzhao/JingZhao2/software/drivers/libhgrnic/src/hgrnic.c new file mode 100644 index 0000000000000000000000000000000000000000..1d217f78bc4a3665ca3be029dda78a19ab46afbf --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/software/drivers/libhgrnic/src/hgrnic.c @@ -0,0 +1,232 @@ +#if HAVE_CONFIG_H +# include +#endif /* HAVE_CONFIG_H */ + +#include +#include +#include +#include +#include +#include +#include + +#ifndef HAVE_IBV_REGISTER_DRIVER +#include +#endif + +#ifndef HAVE_IBV_READ_SYSFS_FILE +#include +#include +#include +#endif + +#include "hgrnic.h" +#include "hgrnic-abi.h" + +#define PCI_VENDOR_ID_ICT 0x10EE +#define PCI_DEVICE_ID_ICT_HANGU_RNIC 0x7028 + +struct { + unsigned vendor; + unsigned device; +} hca_table[] = { + {PCI_VENDOR_ID_ICT, PCI_DEVICE_ID_ICT_HANGU_RNIC}, +}; + +static struct ibv_context_ops hgrnic_ctx_ops = { + .query_device = hgrnic_query_device , // done + .query_port = hgrnic_query_port , // done + .alloc_pd = hgrnic_alloc_pd , // done + .dealloc_pd = hgrnic_free_pd , // done + .reg_mr = hgrnic_reg_mr , // done + .dereg_mr = hgrnic_dereg_mr , // done + .create_cq = hgrnic_create_cq , // done + .poll_cq = hgrnic_poll_cq , // done + .resize_cq = hgrnic_resize_cq , // done + .destroy_cq = hgrnic_destroy_cq , // done + .create_qp = hgrnic_create_qp , // done + .query_qp = hgrnic_query_qp , // done + .modify_qp = hgrnic_modify_qp , // done + .destroy_qp = hgrnic_destroy_qp , // done + .create_ah = hgrnic_create_ah , // done + .destroy_ah = hgrnic_destroy_ah , // done + .attach_mcast = ibv_cmd_attach_mcast, + .detach_mcast = ibv_cmd_detach_mcast, + + .post_send = hgrnic_post_send, // done + .post_recv = hgrnic_post_recv, // done + + .req_notify_cq = hgrnic_notify_cq, + + .create_srq = hgrnic_create_srq , + .query_srq = hgrnic_query_srq , + .post_srq_recv = hgrnic_post_srq_recv, + .modify_srq = hgrnic_modify_srq , + .destroy_srq = hgrnic_destroy_srq +}; + +static struct ibv_context *hgrnic_alloc_context(struct ibv_device *ibdev, int cmd_fd) +{ + struct hgrnic_context *context; + struct ibv_get_context cmd; + struct hgrnic_alloc_ucontext_resp resp; + int i; + + context = calloc(1, sizeof *context); + if (!context) + return NULL; + + context->ibv_ctx.cmd_fd = cmd_fd; + + if (ibv_cmd_get_context(&context->ibv_ctx, &cmd, sizeof cmd, + &resp.ibv_resp, sizeof resp)) + goto err_free; + + context->num_qps = resp.qp_tab_size; + context->qp_table_shift = ffs(context->num_qps) - 1 - HGRNIC_QP_TABLE_BITS; + context->qp_table_mask = (1 << context->qp_table_shift) - 1; + + // context->ibv_ctx.device = ibdev; // !TODO: We may don't need it now. + + pthread_mutex_init(&context->qp_table_mutex, NULL); + for (i = 0; i < HGRNIC_QP_TABLE_SIZE; ++i) + context->qp_table[i].refcnt = 0; + + context->uar = mmap(NULL, to_hgdev(ibdev)->page_size, PROT_WRITE, + MAP_SHARED, cmd_fd, 0); + if (context->uar == MAP_FAILED) + goto err_free; + + pthread_spin_init(&context->uar_lock, PTHREAD_PROCESS_PRIVATE); + + context->pd = hgrnic_alloc_pd(&context->ibv_ctx); + if (!context->pd) + goto err_unmap; + + context->pd->context = &context->ibv_ctx; + + context->ibv_ctx.ops = hgrnic_ctx_ops; + + return &context->ibv_ctx; + +err_unmap: + munmap(context->uar, to_hgdev(ibdev)->page_size); + +err_free: + free(context); + return NULL; +} + +static void hgrnic_free_context(struct ibv_context *ibctx) +{ + struct hgrnic_context *context = to_hgctx(ibctx); + + hgrnic_free_pd(context->pd); + munmap(context->uar, to_hgdev(ibctx->device)->page_size); + free(context); +} + +// assigned to ibverbs by init_func. +static struct ibv_device_ops hgrnic_dev_ops = { + .alloc_context = hgrnic_alloc_context, + .free_context = hgrnic_free_context +}; + +/* + * Keep a private implementation of HAVE_IBV_READ_SYSFS_FILE to handle + * old versions of libibverbs that didn't implement it. This can be + * removed when libibverbs 1.0.3 or newer is available "everywhere." + */ +#ifndef HAVE_IBV_READ_SYSFS_FILE +static int ibv_read_sysfs_file(const char *dir, const char *file, + char *buf, size_t size) +{ + char path[256]; + int fd; + int len; + + snprintf(path, sizeof path, "%s/%s", dir, file); + + fd = open(path, O_RDONLY); + if (fd < 0) + return -1; + + len = read(fd, buf, size); + + close(fd); + + if (len > 0 && buf[len - 1] == '\n') + buf[--len] = '\0'; + + return len; +} +#endif /* HAVE_IBV_READ_SYSFS_FILE */ + +// "ibv_driver_init_func init_func", defined in ibverbs +static struct ibv_device *hgrnic_driver_init(const char *uverbs_sys_path, + int abi_version) +{ + char value[8]; + struct hgrnic_device *dev; + unsigned vendor, device; + int i; + + if (ibv_read_sysfs_file(uverbs_sys_path, "device/vendor", + value, sizeof value) < 0) + return NULL; + sscanf(value, "%i", &vendor); + + if (ibv_read_sysfs_file(uverbs_sys_path, "device/device", + value, sizeof value) < 0) + return NULL; + sscanf(value, "%i", &device); + + for (i = 0; i < sizeof hca_table / sizeof hca_table[0]; ++i) + if (vendor == hca_table[i].vendor && + device == hca_table[i].device) + goto found; + + return NULL; + +found: + if (abi_version > HGRNIC_UVERBS_ABI_VERSION) { + fprintf(stderr, PFX "Fatal: ABI version %d of %s is too new (expected %d)\n", + abi_version, uverbs_sys_path, HGRNIC_UVERBS_ABI_VERSION); + return NULL; + } + + dev = malloc(sizeof *dev); + if (!dev) { + fprintf(stderr, PFX "Fatal: couldn't allocate device for %s\n", + uverbs_sys_path); + return NULL; + } + + dev->ibv_dev.ops = hgrnic_dev_ops; + dev->page_size = sysconf(_SC_PAGESIZE); + + return &dev->ibv_dev; +} + +#ifdef HAVE_IBV_REGISTER_DRIVER +static __attribute__((constructor)) void hgrnic_register_driver(void) +{ + ibv_register_driver("hgrnic", hgrnic_driver_init); +} +#else +/* + * Export the old libsysfs sysfs_class_device-based driver entry point + * if libibverbs does not export an ibv_register_driver() function. + */ +struct ibv_device *openib_driver_init(struct sysfs_class_device *sysdev) +{ + int abi_ver = 0; + char value[8]; + + if (ibv_read_sysfs_file(sysdev->path, "abi_version", + value, sizeof value) > 0) + abi_ver = strtol(value, NULL, 10); + + return hgrnic_driver_init(sysdev->path, abi_ver); +} +#endif /* HAVE_IBV_REGISTER_DRIVER */ diff --git a/ETH-PLUS_Jingzhao/JingZhao2/software/drivers/libhgrnic/src/hgrnic.h b/ETH-PLUS_Jingzhao/JingZhao2/software/drivers/libhgrnic/src/hgrnic.h new file mode 100644 index 0000000000000000000000000000000000000000..e079d0a612622604992781e639916a51074e0172 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/software/drivers/libhgrnic/src/hgrnic.h @@ -0,0 +1,298 @@ +/* + * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved. + * Copyright (c) 2005, 2006 Cisco Systems. All rights reserved. + * + * This software is available to you under a choice of one of two + * licenses. You may choose to be licensed under the terms of the GNU + * General Public License (GPL) Version 2, available from the file + * COPYING in the main directory of this source tree, or the + * OpenIB.org BSD license below: + * + * Redistribution and use in source and binary forms, with or + * without modification, are permitted provided that the following + * conditions are met: + * + * - Redistributions of source code must retain the above + * copyright notice, this list of conditions and the following + * disclaimer. + * + * - Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials + * provided with the distribution. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#ifndef HGRNIC_H +#define HGRNIC_H + +#include + +#include +#include + +#ifdef HAVE_VALGRIND_MEMCHECK_H + +# include + +# if !defined(VALGRIND_MAKE_MEM_DEFINED) || !defined(VALGRIND_MAKE_MEM_UNDEFINED) +# warning "Valgrind support requested, but VALGRIND_MAKE_MEM_(UN)DEFINED not available" +# endif + +#endif /* HAVE_VALGRIND_MEMCHECK_H */ + +#ifndef VALGRIND_MAKE_MEM_DEFINED +# define VALGRIND_MAKE_MEM_DEFINED(addr,len) +#endif + +#ifndef VALGRIND_MAKE_MEM_UNDEFINED +# define VALGRIND_MAKE_MEM_UNDEFINED(addr,len) +#endif + +#ifndef rmb +# define rmb() mb() +#endif + +#ifndef wmb +# define wmb() mb() +#endif + +#define HIDDEN __attribute__((visibility ("hidden"))) + +#define PFX "hgrnic: " + +#define dump_state printf("[%s]: " sta "\n", __FUNCTION__, sta); + +enum { + HGRNIC_CQ_ENTRY_SIZE = 0x20 +}; + +enum { + HGRNIC_QP_TABLE_BITS = 8, + HGRNIC_QP_TABLE_SIZE = 1 << HGRNIC_QP_TABLE_BITS, + HGRNIC_QP_TABLE_MASK = HGRNIC_QP_TABLE_SIZE - 1 +}; + +enum { + HGRNIC_DB_REC_PAGE_SIZE = 4096, + HGRNIC_DB_REC_PER_PAGE = HGRNIC_DB_REC_PAGE_SIZE / 8 +}; + +enum hgrnic_db_type { + HGRNIC_DB_TYPE_INVALID = 0x0, + HGRNIC_DB_TYPE_CQ_SET_CI = 0x1, + HGRNIC_DB_TYPE_CQ_ARM = 0x2, + HGRNIC_DB_TYPE_SQ = 0x3, + HGRNIC_DB_TYPE_RQ = 0x4, + HGRNIC_DB_TYPE_SRQ = 0x5, + HGRNIC_DB_TYPE_GROUP_SEP = 0x7 +}; + +enum { + HGRNIC_OPCODE_NOP = 0x00, + HGRNIC_OPCODE_RDMA_WRITE = 0x08, + HGRNIC_OPCODE_RDMA_WRITE_IMM = 0x09, + HGRNIC_OPCODE_SEND = 0x0a, + HGRNIC_OPCODE_SEND_IMM = 0x0b, + HGRNIC_OPCODE_RDMA_READ = 0x10, + HGRNIC_OPCODE_ATOMIC_CS = 0x11, + HGRNIC_OPCODE_ATOMIC_FA = 0x12, + HGRNIC_OPCODE_BIND_MW = 0x18, + HGRNIC_OPCODE_RECV_ERR = 0xfe, + HGRNIC_OPCODE_SEND_ERR = 0xff +}; + +struct hgrnic_device { + struct ibv_device ibv_dev; + int page_size; +}; + +struct hgrnic_db_table; + +struct hgrnic_context { + struct ibv_context ibv_ctx; + void *uar; + pthread_spinlock_t uar_lock; + struct hgrnic_db_table *db_tab; + struct ibv_pd *pd; // CQ, QP queue buffer belongs to this pd + struct { + struct hgrnic_qp **table; + int refcnt; + } qp_table[HGRNIC_QP_TABLE_SIZE]; + pthread_mutex_t qp_table_mutex; + int num_qps; + int qp_table_shift; // Number of elem in one qp table in log + int qp_table_mask ; // number of elem in one QP table +}; + +struct hgrnic_buf { + void *buf ; // addr + size_t length; +}; + +struct hgrnic_pd { + struct ibv_pd ibv_pd; + pthread_mutex_t ah_mutex; + uint32_t pdn; +}; + +struct hgrnic_cq { + struct ibv_cq ibv_cq; + struct hgrnic_buf buf ; /* queue buffer */ + pthread_spinlock_t lock ; + struct ibv_mr *mr ; + uint32_t cqn ; + uint32_t cons_index; /* comsumer index, point to next consuming cqe, never go down */ + uint32_t cqe_mask ; /* cqe num - 1 */ +}; + +struct hgrnic_wq { + pthread_spinlock_t lock; + int max; + unsigned next_ind; + unsigned last_comp; /* last completed wqe index, always < max */ + unsigned head; /* never go down */ + unsigned tail; /* never go down */ + void *last; + int max_gs; + int wqe_shift; + + int buf_size; + struct hgrnic_buf buf ; + struct ibv_mr *mr ; + + uint64_t *wrid ; +}; + +struct hgrnic_qp { + struct ibv_qp ibv_qp; + int max_inline_data; + struct hgrnic_wq sq; + struct hgrnic_wq rq; +}; + +struct hgrnic_av { + uint32_t port_pd; + uint8_t reserved1; + uint8_t g_slid; + uint16_t dlid; + uint8_t reserved2; + uint8_t gid_index; + uint8_t msg_sr; + uint8_t hop_limit; + uint32_t sl_tclass_flowlabel; + uint32_t dgid[4]; +}; + +struct hgrnic_ah { + struct ibv_ah ibv_ah; + struct hgrnic_av *av; + uint32_t key; +}; + +static inline unsigned long align(unsigned long val, unsigned long align) +{ + return (val + align - 1) & ~(align - 1); +} + +#define to_hgxxx(xxx, type) \ + ((struct hgrnic_##type *) \ + ((void *) ib##xxx - offsetof(struct hgrnic_##type, ibv_##xxx))) + +static inline struct hgrnic_device *to_hgdev(struct ibv_device *ibdev) +{ + return to_hgxxx(dev, device); +} + +static inline struct hgrnic_context *to_hgctx(struct ibv_context *ibctx) +{ + return to_hgxxx(ctx, context); +} + +static inline struct hgrnic_pd *to_hgpd(struct ibv_pd *ibpd) +{ + return to_hgxxx(pd, pd); +} + +static inline struct hgrnic_cq *to_hgcq(struct ibv_cq *ibcq) +{ + return to_hgxxx(cq, cq); +} + +static inline struct hgrnic_qp *to_hgqp(struct ibv_qp *ibqp) +{ + return to_hgxxx(qp, qp); +} + +static inline struct hgrnic_ah *to_hgah(struct ibv_ah *ibah) +{ + return to_hgxxx(ah, ah); +} + +int hgrnic_alloc_buf(struct hgrnic_buf *buf, size_t size, int page_size); +void hgrnic_free_buf(struct hgrnic_buf *buf); + +int hgrnic_query_device(struct ibv_context *context, + struct ibv_device_attr *attr); +int hgrnic_query_port(struct ibv_context *context, uint8_t port, + struct ibv_port_attr *attr); + +struct ibv_pd *hgrnic_alloc_pd(struct ibv_context *context); +int hgrnic_free_pd(struct ibv_pd *pd); + +struct ibv_mr *hgrnic_reg_mr(struct ibv_pd *pd, void *addr, + size_t length, enum ibv_access_flags access); +int hgrnic_dereg_mr(struct ibv_mr *mr); + +struct ibv_cq *hgrnic_create_cq(struct ibv_context *context, int cqe, + struct ibv_comp_channel *channel, + int comp_vector); +int hgrnic_resize_cq(struct ibv_cq *cq, int cqe); +int hgrnic_destroy_cq(struct ibv_cq *cq); +int hgrnic_notify_cq(struct ibv_cq *cq, int solicited_only); +int hgrnic_poll_cq(struct ibv_cq *cq, int ne, struct ibv_wc *wc); +void __hgrnic_cq_clean(struct hgrnic_cq *cq, uint32_t qpn); +void hgrnic_cq_clean(struct hgrnic_cq *cq, uint32_t qpn); +void hgrnic_cq_resize_copy_cqes(struct hgrnic_cq *cq, void *buf, int new_cqe); +int hgrnic_alloc_cq_buf(struct hgrnic_device *dev, struct hgrnic_buf *buf, int nent); + +struct ibv_qp *hgrnic_create_qp(struct ibv_pd *pd, struct ibv_qp_init_attr *attr); +int hgrnic_query_qp(struct ibv_qp *qp, struct ibv_qp_attr *attr, + enum ibv_qp_attr_mask attr_mask, + struct ibv_qp_init_attr *init_attr); +int hgrnic_modify_qp(struct ibv_qp *qp, struct ibv_qp_attr *attr, + enum ibv_qp_attr_mask attr_mask); +int hgrnic_destroy_qp(struct ibv_qp *qp); +void hgrnic_init_qp_indices(struct hgrnic_qp *qp); +int hgrnic_post_send(struct ibv_qp *ibqp, struct ibv_send_wr *wr, + struct ibv_send_wr **bad_wr); +int hgrnic_post_recv(struct ibv_qp *ibqp, struct ibv_recv_wr *wr, + struct ibv_recv_wr **bad_wr); +int hgrnic_alloc_qp_buf(struct ibv_pd *pd, struct ibv_qp_cap *cap, + enum ibv_qp_type type, struct hgrnic_qp *qp); +struct hgrnic_qp *hgrnic_find_qp(struct hgrnic_context *ctx, uint32_t qpn); +int hgrnic_store_qp(struct hgrnic_context *ctx, uint32_t qpn, struct hgrnic_qp *qp); +void hgrnic_clear_qp(struct hgrnic_context *ctx, uint32_t qpn); + +// SRQ related +struct ibv_srq * hgrnic_create_srq(struct ibv_pd *pd, struct ibv_srq_init_attr *srq_init_attr); +int hgrnic_modify_srq(struct ibv_srq *srq, struct ibv_srq_attr *srq_attr, enum ibv_srq_attr_mask srq_attr_mask); +int hgrnic_query_srq(struct ibv_srq *srq, struct ibv_srq_attr *srq_attr); +int hgrnic_destroy_srq(struct ibv_srq *srq); +int hgrnic_post_srq_recv(struct ibv_srq *srq, struct ibv_recv_wr *recv_wr, struct ibv_recv_wr **bad_recv_wr); + +struct ibv_ah *hgrnic_create_ah(struct ibv_pd *pd, struct ibv_ah_attr *attr); +int hgrnic_destroy_ah(struct ibv_ah *ah); +int hgrnic_alloc_av(struct hgrnic_pd *pd, struct ibv_ah_attr *attr, + struct hgrnic_ah *ah); +void hgrnic_free_av(struct hgrnic_ah *ah); + +#endif /* HGRNIC_H */ diff --git a/ETH-PLUS_Jingzhao/JingZhao2/software/drivers/libhgrnic/src/qp.c b/ETH-PLUS_Jingzhao/JingZhao2/software/drivers/libhgrnic/src/qp.c new file mode 100644 index 0000000000000000000000000000000000000000..e3e538c104bb6107f4db64f2d4ca07154315dcd3 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/software/drivers/libhgrnic/src/qp.c @@ -0,0 +1,581 @@ +/* + * Copyright (c) 2005 Topspin Communications. All rights reserved. + * Copyright (c) 2005 Mellanox Technologies Ltd. All rights reserved. + * + * This software is available to you under a choice of one of two + * licenses. You may choose to be licensed under the terms of the GNU + * General Public License (GPL) Version 2, available from the file + * COPYING in the main directory of this source tree, or the + * OpenIB.org BSD license below: + * + * Redistribution and use in source and binary forms, with or + * without modification, are permitted provided that the following + * conditions are met: + * + * - Redistributions of source code must retain the above + * copyright notice, this list of conditions and the following + * disclaimer. + * + * - Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials + * provided with the distribution. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#if HAVE_CONFIG_H +# include +#endif /* HAVE_CONFIG_H */ + +#include +#include +#include +#include +#include + +#include "hgrnic.h" +#include "doorbell.h" +#include "wqe.h" + +enum { + HGRNIC_SEND_DOORBELL_FENCE = 1 << 5 +}; + +static const uint8_t hgrnic_opcode[] = { + [IBV_WR_SEND] = HGRNIC_OPCODE_SEND, + [IBV_WR_SEND_WITH_IMM] = HGRNIC_OPCODE_SEND_IMM, + [IBV_WR_RDMA_WRITE] = HGRNIC_OPCODE_RDMA_WRITE, + [IBV_WR_RDMA_WRITE_WITH_IMM] = HGRNIC_OPCODE_RDMA_WRITE_IMM, + [IBV_WR_RDMA_READ] = HGRNIC_OPCODE_RDMA_READ, + [IBV_WR_ATOMIC_CMP_AND_SWP] = HGRNIC_OPCODE_ATOMIC_CS, + [IBV_WR_ATOMIC_FETCH_AND_ADD] = HGRNIC_OPCODE_ATOMIC_FA, +}; + +static void *get_wqe(struct hgrnic_wq wq, int n) +{ + return wq.buf.buf + (n << wq.wqe_shift); +} + +void hgrnic_init_qp_indices(struct hgrnic_qp *qp) +{ + qp->sq.next_ind = 0; + qp->sq.last_comp = qp->sq.max - 1; + qp->sq.head = 0; + qp->sq.tail = 0; + qp->sq.last = get_wqe(qp->sq, qp->sq.max - 1); + + qp->rq.next_ind = 0; + qp->rq.last_comp = qp->rq.max - 1; + qp->rq.head = 0; + qp->rq.tail = 0; + qp->rq.last = get_wqe(qp->rq, qp->rq.max - 1); +} + +static inline int wq_overflow(struct hgrnic_wq *wq, int nreq, struct hgrnic_cq *cq) +{ + unsigned cur; + + + cur = wq->head - wq->tail; + if (cur + nreq < wq->max) + return 0; + + + pthread_spin_lock(&cq->lock); + cur = wq->head - wq->tail; + pthread_spin_unlock(&cq->lock); + + return cur + nreq >= wq->max; +} + +static inline void set_data_unit (struct hgrnic_data_unit *dunit, + struct ibv_sge *sg) { + dunit->byte_count = sg->length; + dunit->lkey = sg->lkey ; + dunit->addr = sg->addr ; +} + +static inline void hgrnic_set_data_unit_inval(struct hgrnic_data_unit *dunit) +{ + dunit->byte_count = 0; + dunit->lkey = HGRNIC_INVAL_LKEY; + dunit->addr = 0; + //printf("set invalid data unit\n"); +} + +static inline void set_raddr_unit(struct hgrnic_raddr_unit *runit, + uint64_t remote_addr, uint32_t rkey) +{ + runit->raddr = remote_addr; + runit->rkey = rkey; + runit->reserved = 0; +} + +static inline void set_ud_unit(struct hgrnic_ud_unit *uunit, + struct hgrnic_av *av, + uint32_t dst_qpn, uint32_t dst_qkey) +{ + uunit->port = av->port_pd; + uunit->slid = av->g_slid ; + uunit->dlid = av->dlid ; + uunit->dqpn = dst_qpn ; + uunit->qkey = dst_qkey ; +} + +static inline void hgrnic_send_db(struct hgrnic_qp *qp, int nreq, + uint32_t size0, uint32_t f0, uint32_t op0) +{ + uint32_t db[2]; + + db[1] = (qp->ibv_qp.qp_num << 8) | size0; + db[0] = ((qp->sq.head << (qp->sq.wqe_shift-4)) << 8) | f0 | op0; + + wmb(); + hgrnic_write64(db, to_hgctx(qp->ibv_qp.context), HGRNIC_SEND_DOORBELL); + + qp->sq.head += nreq; // never go down + +// printf("Send doorbell[1]: 0x%x\n", db[1]); +// printf("Send doorbell[0]: 0x%x\n", db[0]); +// fprintf(stderr, "Send doorbell[1]: 0x%x\n", db[1]); +// fprintf(stderr, "Send doorbell[0]: 0x%x\n\n\n", db[0]); +} + +int hgrnic_post_send(struct ibv_qp *ibqp, struct ibv_send_wr *wr, + struct ibv_send_wr **bad_wr) +{ + //fprintf(stderr, "Post Send Begin\n"); + struct hgrnic_qp *qp = to_hgqp(ibqp); + + void *cur_unit; /* point to current prcessing unit in current wqe */ + void *prev_wqe; + void *cur_wqe ; /* point to current processing wqe */ + int ret = 0; + int nreq; + int size; + int ind; + int i; + /* + * f0 and op0 cannot be used unless nreq > 0, which means this + * function makes it through the loop at least once. So the + * code inside the if (!size0) will be executed, and f0 and + * op0 will be initialized. So any gcc warning about "may be + * used unitialized" is bogus. + */ + uint32_t f0; + uint32_t op0; + uint32_t size0; + + pthread_spin_lock(&qp->sq.lock); + + ind = qp->sq.head & (qp->sq.max - 1); + + for (nreq = 0; wr; ++nreq, wr = wr->next) { + if (nreq == HGRNIC_MAX_WQES_PER_SEND_DB) { + hgrnic_send_db(qp, nreq, size0, f0, op0); + nreq = 0; + } + + if (wq_overflow(&qp->sq, nreq, to_hgcq(qp->ibv_qp.send_cq))) { + struct hgrnic_wq *wq = &qp->sq; + fprintf(stderr, "wq->head = %x\n", wq->head); + fprintf(stderr, "wq->tail = %x\n", wq->tail); + fprintf(stderr, "wq->max = %x\n", wq->max); + fprintf(stderr, "wq_overflow\n"); + ret = -1; + *bad_wr = wr; + goto out; + } + + cur_wqe = get_wqe(qp->sq, ind); + cur_unit = cur_wqe; + prev_wqe = qp->sq.last; + qp->sq.last = cur_wqe; + + ((struct hgrnic_next_unit *) cur_unit)->flags = + ((wr->send_flags & IBV_SEND_SIGNALED) ? HGRNIC_NEXT_CQ_UPDATE : 0) | + ((wr->send_flags & IBV_SEND_SOLICITED) ? HGRNIC_NEXT_SOLICIT : 0) | + 0; + if (wr->opcode == IBV_WR_SEND_WITH_IMM || + wr->opcode == IBV_WR_RDMA_WRITE_WITH_IMM) + ((struct hgrnic_next_unit *) cur_unit)->imm = wr->imm_data; + + cur_unit += sizeof (struct hgrnic_next_unit); + size = sizeof (struct hgrnic_next_unit) / 16; + + switch (ibqp->qp_type) { + case IBV_QPT_RC: + switch (wr->opcode) { + case IBV_WR_RDMA_WRITE: + case IBV_WR_RDMA_WRITE_WITH_IMM: + case IBV_WR_RDMA_READ: + set_raddr_unit((struct hgrnic_raddr_unit *)cur_unit, + wr->wr.rdma.remote_addr, + wr->wr.rdma.rkey); + cur_unit += sizeof (struct hgrnic_raddr_unit); + size += sizeof (struct hgrnic_raddr_unit) / 16; + break; + + default: + break; + } + break; + + case IBV_QPT_UC: + switch (wr->opcode) { + case IBV_WR_RDMA_WRITE: + case IBV_WR_RDMA_WRITE_WITH_IMM: + set_raddr_unit((struct hgrnic_raddr_unit *)cur_unit, + wr->wr.rdma.remote_addr, + wr->wr.rdma.rkey); + cur_unit += sizeof (struct hgrnic_raddr_unit); + size += sizeof (struct hgrnic_raddr_unit) / 16; + break; + + default: + /* No extra segments required for sends */ + break; + } + break; + + case IBV_QPT_UD: + set_ud_unit( + ((struct hgrnic_ud_unit *)cur_unit), + to_hgah(wr->wr.ud.ah)->av, + wr->wr.ud.remote_qpn, + wr->wr.ud.remote_qkey + ); + cur_unit += sizeof (struct hgrnic_ud_unit); + size += sizeof (struct hgrnic_ud_unit) / 16; + break; + + default: + break; + } + + if (wr->num_sge > qp->sq.max_gs) { + fprintf(stderr, "wr->num_sge > qp->sq.max_gs\n"); + ret = -1; + *bad_wr = wr; + goto out; + } + + if (wr->send_flags & IBV_SEND_INLINE) { + if (wr->num_sge) { + struct hgrnic_inline_unit *inline_unit = cur_unit; + int s = 0; + + cur_unit += sizeof(struct hgrnic_inline_unit); + for (i = 0; i < wr->num_sge; ++i) { + struct ibv_sge *sge = &wr->sg_list[i]; + + s += sge->length; + + if (s > qp->max_inline_data) { + fprintf(stderr, "s > qp->max_inline_data\n"); + ret = -1; + *bad_wr = wr; + goto out; + } + + memcpy(cur_unit, (void *) (uintptr_t) sge->addr, + sge->length); + cur_unit += sge->length; + } + + inline_unit->byte_count = HGRNIC_INLINE_UNIT | s; + size += align(s + sizeof(struct hgrnic_inline_unit), 16) / 16; + } + } else { + for (i = 0; i < wr->num_sge; ++i) { + set_data_unit(cur_unit, &wr->sg_list[i]); + cur_unit += sizeof(struct hgrnic_data_unit); + } + size += wr->num_sge * (sizeof(struct hgrnic_data_unit) / 16); + } + + qp->sq.wrid[ind] = wr->wr_id; + + if (wr->opcode >= sizeof(hgrnic_opcode) / sizeof(hgrnic_opcode[0])) { + fprintf(stderr, "wr->opcode >= sizeof... ...\n"); + ret = -1; + *bad_wr = wr; + goto out; + } + + if (!nreq) { + size0 = size; + op0 = hgrnic_opcode[wr->opcode]; + f0 = wr->send_flags & IBV_SEND_FENCE ? + HGRNIC_SEND_DOORBELL_FENCE : 0; + } else { + ((struct hgrnic_next_unit *) prev_wqe)->nda_nop = + ((ind << (qp->sq.wqe_shift - 4)) << 6) | hgrnic_opcode[wr->opcode]; + ((struct hgrnic_next_unit *) prev_wqe)->ee_nds = + HGRNIC_NEXT_DBD | ((wr->send_flags & IBV_SEND_FENCE) ? HGRNIC_NEXT_FENCE : 0) | + size; + } + + ++ind; + if (ind >= qp->sq.max) + ind -= qp->sq.max; + + //printf ("qp->sq.mr->lkey 0x%x, head %d, wqe_addr 0x%lx, qp->sq addr 0x%lx, wqe_shift %d ind %d max 0x%x, nreq %d\n", + // qp->sq.mr->lkey, qp->sq.head, (uintptr_t)cur_wqe, (uintptr_t)qp->sq.buf.buf, qp->sq.wqe_shift, ind, qp->sq.max, nreq); + // for (int i = 0; i < size * 16 ; ++i) + // printf ("cur_wqe[%d]: 0x%x\n", i, ((uint8_t *)cur_wqe)[i]); + } + +out: + if (nreq) + hgrnic_send_db(qp, nreq, size0, f0, op0); + + //fprintf(stderr, "Post Send End:\n\tnreq = %d, wq->head = %lx, wq->tail = %lx, wq->max = %lx\n", nreq, (&qp->sq)->head, (&qp->sq)->tail, (&qp->sq)->max); + pthread_spin_unlock(&qp->sq.lock); + return ret; +} + +int hgrnic_post_recv(struct ibv_qp *ibqp, struct ibv_recv_wr *wr, + struct ibv_recv_wr **bad_wr) +{ + struct hgrnic_qp *qp = to_hgqp(ibqp); + int ret = 0; + void *wqe; + struct hgrnic_next_unit *wqe_next_unit = NULL; /* pointingg to previous unit */ + uint32_t *tmp_wqe; + int nreq; + int ind; + int i; + + pthread_spin_lock(&qp->rq.lock); + + ind = qp->rq.head & (qp->rq.max - 1); + + for (nreq = 0; wr; ++nreq, wr = wr->next) { + if (wq_overflow(&qp->rq, nreq, to_hgcq(qp->ibv_qp.recv_cq))) { + ret = -1; + *bad_wr = wr; + goto out; + } + + /* fill previous wqe next unit */ + if (wqe_next_unit) { + wqe_next_unit->nda_nop = (ind << (qp->rq.wqe_shift - 4 + 6)) | HGRNIC_NEXT_VALID; // nda is in 16 byte unit; nop is ignored + wqe_next_unit->ee_nds = (wr->num_sge + 1) * sizeof(struct hgrnic_data_unit) / 16; /* Including the invalid data unit; in 16 byte unit */ + } + + wqe = get_wqe(qp->rq, ind); + wqe_next_unit = wqe; + tmp_wqe = wqe; + + ((struct hgrnic_next_unit *) wqe)->nda_nop = HGRNIC_NEXT_VALID; + ((struct hgrnic_next_unit *) wqe)->ee_nds = 0; + ((struct hgrnic_next_unit *) wqe)->flags = 0; + + wqe += sizeof (struct hgrnic_next_unit); + + if (wr->num_sge > qp->rq.max_gs) { + ret = -1; + *bad_wr = wr; + goto out; + } + + for (i = 0; i < wr->num_sge; ++i) { + set_data_unit(wqe, &wr->sg_list[i]); + wqe += sizeof (struct hgrnic_data_unit); + } + + if (i < qp->rq.max_gs) + hgrnic_set_data_unit_inval(wqe); + + qp->rq.wrid[ind] = wr->wr_id; + + ++ind; + if (ind >= qp->rq.max) + ind -= qp->rq.max; + + for (int i = 0; i < 64; ++i) { + //printf("rcv_wqe[%d] 0x%x\n", i, tmp_wqe[i]); + } + } +out: + if (nreq) + qp->rq.head += nreq; + + pthread_spin_unlock(&qp->rq.lock); + return ret; +} + +int hgrnic_alloc_qp_buf(struct ibv_pd *pd, struct ibv_qp_cap *cap, + enum ibv_qp_type type, struct hgrnic_qp *qp) +{ + // struct hgrnic_data_unit *scatter; + // struct hgrnic_next_unit *next; + int max_sq_sge; + int size; + // int i; + + qp->rq.max_gs = cap->max_recv_sge; + qp->sq.max_gs = cap->max_send_sge; + max_sq_sge = align(cap->max_inline_data + sizeof (struct hgrnic_inline_unit), + sizeof (struct hgrnic_data_unit)) / sizeof (struct hgrnic_data_unit); + if (max_sq_sge < cap->max_send_sge) + max_sq_sge = cap->max_send_sge; + + qp->sq.wrid = malloc(qp->sq.max * sizeof (uint64_t)); + if (!qp->sq.wrid) + return -1; + + qp->rq.wrid = malloc(qp->rq.max * sizeof (uint64_t)); + if (!qp->rq.wrid) { + free(qp->sq.wrid); + return -1; + } + + size = sizeof (struct hgrnic_next_unit) + + qp->rq.max_gs * sizeof (struct hgrnic_data_unit); + //printf("rq size is : %d\n", size); + + /* init value is 6, cause we must allow one extra empty + * data unit to identify the end of wqe. So, the minimum + * size of wqe is 1 * next_unit + 2 * data_unit = 48 bytes. */ + for (qp->rq.wqe_shift = 7; 1 << qp->rq.wqe_shift < size; + qp->rq.wqe_shift++) + ; /* nothing */ + + qp->rq.buf_size = qp->rq.max << qp->rq.wqe_shift; + + size = max_sq_sge * sizeof (struct hgrnic_data_unit); + switch (type) { + case IBV_QPT_UD: + size += sizeof (struct hgrnic_ud_unit); + break; + + case IBV_QPT_UC: + size += sizeof (struct hgrnic_raddr_unit); + break; + + case IBV_QPT_RC: + size += sizeof (struct hgrnic_raddr_unit); + /* + * An atomic op will require an atomic segment, a + * remote address segment and one scatter entry. + */ + if (size < (sizeof (struct hgrnic_atomic_seg) + + sizeof (struct hgrnic_raddr_unit) + + sizeof (struct hgrnic_data_unit))) + size = (sizeof (struct hgrnic_atomic_seg) + + sizeof (struct hgrnic_raddr_unit) + + sizeof (struct hgrnic_data_unit)); + break; + + default: + break; + } + + size += sizeof (struct hgrnic_next_unit); + + for (qp->sq.wqe_shift = 7; 1 << qp->sq.wqe_shift < size; + qp->sq.wqe_shift++) + ; /* nothing */ + + qp->sq.buf_size = qp->sq.max << qp->sq.wqe_shift; + + /* Allocate queue space for SQ. */ + if (hgrnic_alloc_buf(&qp->sq.buf, + align(qp->sq.buf_size, to_hgdev(pd->context->device)->page_size), + to_hgdev(pd->context->device)->page_size)) { + free(qp->sq.wrid); + free(qp->rq.wrid); + return -1; + } + + memset(qp->sq.buf.buf, 0, qp->sq.buf_size); + + /* Allocate queue space for RQ. */ + if (qp->rq.buf_size) { // if srq is used, rq buffer size is 0 + if (hgrnic_alloc_buf(&qp->rq.buf, + align(qp->rq.buf_size, to_hgdev(pd->context->device)->page_size), + to_hgdev(pd->context->device)->page_size)) { + hgrnic_free_buf(&qp->sq.buf); + free(qp->rq.wrid); + free(qp->sq.wrid); + return -1; + } + + memset(qp->rq.buf.buf, 0, qp->rq.buf_size); + + //printf("rq buf size is : %d\n", qp->rq.buf_size); + } + + // Initializing RQ queue buffer + // size = (sizeof (struct hgrnic_next_unit) + + // qp->rq.max_gs * sizeof (struct hgrnic_data_unit)) / 16; + + // for (i = 0; i < qp->rq.max; ++i) { + // next = get_wqe(qp->rq, i); + // next->nda_nop = ((i + 1) & (qp->rq.max - 1)) << (qp->rq.wqe_shift - 4 + 6); + // next->ee_nds = size; /* in 16 byte unit */ + + // for (scatter = (void *) (next + 1); + // (void *) scatter < (void *) next + (1 << qp->rq.wqe_shift); + // ++scatter) + // scatter->lkey = HGRNIC_INVAL_LKEY; + // } + + // Initializing SQ queue buffer + // for (i = 0; i < qp->sq.max; ++i) { + // next = get_wqe(qp->sq, i); + // next->nda_nop = (((i + 1) & (qp->sq.max - 1)) << + // qp->sq.wqe_shift) << 6; + // } + + hgrnic_init_qp_indices(qp); + + return 0; +} + +struct hgrnic_qp *hgrnic_find_qp(struct hgrnic_context *ctx, uint32_t qpn) +{ + int tind = (qpn & (ctx->num_qps - 1)) >> ctx->qp_table_shift; + + if (ctx->qp_table[tind].refcnt) + return ctx->qp_table[tind].table[qpn & ctx->qp_table_mask]; + else + return NULL; +} + +/* store qp in qp table */ +int hgrnic_store_qp(struct hgrnic_context *ctx, uint32_t qpn, struct hgrnic_qp *qp) +{ + int tind = (qpn & (ctx->num_qps - 1)) >> ctx->qp_table_shift; // table index + + if (!ctx->qp_table[tind].refcnt) { + ctx->qp_table[tind].table = calloc(ctx->qp_table_mask + 1, + sizeof (struct hgrnic_qp *)); + if (!ctx->qp_table[tind].table) + return -1; + } + + ++ctx->qp_table[tind].refcnt; + ctx->qp_table[tind].table[qpn & ctx->qp_table_mask] = qp; + return 0; +} + +void hgrnic_clear_qp(struct hgrnic_context *ctx, uint32_t qpn) +{ + int tind = (qpn & (ctx->num_qps - 1)) >> ctx->qp_table_shift; + + if (!--ctx->qp_table[tind].refcnt) + free(ctx->qp_table[tind].table); + else + ctx->qp_table[tind].table[qpn & ctx->qp_table_mask] = NULL; +} diff --git a/ETH-PLUS_Jingzhao/JingZhao2/software/drivers/libhgrnic/src/srq.c b/ETH-PLUS_Jingzhao/JingZhao2/software/drivers/libhgrnic/src/srq.c new file mode 100644 index 0000000000000000000000000000000000000000..0e5a7b700a39446fe85e8b9b00c2331047c846e4 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/software/drivers/libhgrnic/src/srq.c @@ -0,0 +1,38 @@ + +#if HAVE_CONFIG_H +# include +#endif /* HAVE_CONFIG_H */ + +#include +#include + +#include "hgrnic.h" +#include "doorbell.h" +#include "wqe.h" + +struct ibv_srq *hgrnic_create_srq(struct ibv_pd *pd, struct ibv_srq_init_attr *srq_init_attr) { + struct ibv_srq *srq; + + srq = malloc(sizeof *srq); + if (!srq) + return NULL; + + return srq; +} + +int hgrnic_modify_srq(struct ibv_srq *srq, struct ibv_srq_attr *srq_attr, enum ibv_srq_attr_mask srq_attr_mask) { + return 1; // not support modify srq +} + +int hgrnic_query_srq(struct ibv_srq *srq, struct ibv_srq_attr *srq_attr) { + return 1; +} + +int hgrnic_destroy_srq(struct ibv_srq *srq) { + free(srq); + return 0; +} + +int hgrnic_post_srq_recv(struct ibv_srq *srq, struct ibv_recv_wr *recv_wr, struct ibv_recv_wr **bad_recv_wr) { + return 0; +} \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/software/drivers/libhgrnic/src/verbs.c b/ETH-PLUS_Jingzhao/JingZhao2/software/drivers/libhgrnic/src/verbs.c new file mode 100644 index 0000000000000000000000000000000000000000..43c09904cc7b4d2852d5a9f328ca1dc711a1d3ba --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/software/drivers/libhgrnic/src/verbs.c @@ -0,0 +1,623 @@ +/* + * Copyright (c) 2005 Topspin Communications. All rights reserved. + * Copyright (c) 2005, 2006 Cisco Systems. All rights reserved. + * + * This software is available to you under a choice of one of two + * licenses. You may choose to be licensed under the terms of the GNU + * General Public License (GPL) Version 2, available from the file + * COPYING in the main directory of this source tree, or the + * OpenIB.org BSD license below: + * + * Redistribution and use in source and binary forms, with or + * without modification, are permitted provided that the following + * conditions are met: + * + * - Redistributions of source code must retain the above + * copyright notice, this list of conditions and the following + * disclaimer. + * + * - Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials + * provided with the distribution. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#define _GNU_SOURCE /* See feature_test_macros(7) */ +#include +#include +#include +#include + +#include +#include +#include +#include + +#define my_ompi_code_path_name "/home/huangtianhao/code/mpi_code_huangtianhao/" + +#include +#include +#include + +#if HAVE_CONFIG_H +#include +#endif /* HAVE_CONFIG_H */ + +#include +#include +#include +#include +#include +#include + +#include "hgrnic.h" +#include "hgrnic-abi.h" + +int hgrnic_query_device(struct ibv_context *context, struct ibv_device_attr *attr) +{ + struct ibv_query_device cmd; + uint64_t raw_fw_ver; + unsigned major, minor, sub_minor; + int ret; + + ret = ibv_cmd_query_device(context, attr, &raw_fw_ver, &cmd, sizeof cmd); + if (ret) + return ret; + + major = (raw_fw_ver >> 32) & 0xffff; + minor = (raw_fw_ver >> 16) & 0xffff; + sub_minor = raw_fw_ver & 0xffff; + + snprintf(attr->fw_ver, sizeof attr->fw_ver, + "%d.%d.%d", major, minor, sub_minor); + + return 0; +} + +int hgrnic_query_port(struct ibv_context *context, uint8_t port, + struct ibv_port_attr *attr) +{ + struct ibv_query_port cmd; + + return ibv_cmd_query_port(context, port, attr, &cmd, sizeof cmd); +} + +struct ibv_pd *hgrnic_alloc_pd(struct ibv_context *context) +{ + struct ibv_alloc_pd cmd; + struct hgrnic_alloc_pd_resp resp; + struct hgrnic_pd *pd; + + pd = malloc(sizeof *pd); + if (!pd) + return NULL; + + if (ibv_cmd_alloc_pd(context, &pd->ibv_pd, &cmd, sizeof cmd, + &resp.ibv_resp, sizeof resp)) + { + free(pd); + return NULL; + } + + pd->pdn = resp.pdn; + + return &pd->ibv_pd; +} + +int hgrnic_free_pd(struct ibv_pd *pd) +{ + int ret; + + ret = ibv_cmd_dealloc_pd(pd); + if (ret) + return ret; + + free(to_hgpd(pd)); + return 0; +} + +/** + * @param dma_sync This is set to 1 when the operation to this MR + * is required that all dma operations before this + * region should be completed. + */ +static struct ibv_mr *__hgrnic_reg_mr(struct ibv_pd *pd, void *addr, + size_t length, uint64_t hca_va, + int access, + int dma_sync) +{ + struct ibv_reg_mr_resp resp; + struct hgrnic_reg_mr cmd; + struct ibv_mr *mr; + int ret; + + /* + * Old kernels just ignore the extra data we pass in with the + * reg_mr command structure, so there's no need to add an ABI + * version check here (and indeed the kernel ABI was not + * incremented due to this change). + */ + cmd.mr_attrs = dma_sync ? HGRNIC_MR_DMASYNC : 0; + cmd.reserved = 0; + + mr = malloc(sizeof *mr); + if (!mr) + return NULL; + + ret = ibv_cmd_reg_mr(pd, addr, length, hca_va, access, mr, + &cmd.ibv_cmd, sizeof cmd, &resp, sizeof resp); + if (ret) + { + free(mr); + return NULL; + } + + return mr; +} + +struct ibv_mr *hgrnic_reg_mr(struct ibv_pd *pd, void *addr, + size_t length, enum ibv_access_flags access) +{ + return __hgrnic_reg_mr(pd, addr, length, (uintptr_t)addr, (int)access, 0); +} + +int hgrnic_dereg_mr(struct ibv_mr *mr) +{ + int ret; + + ret = ibv_cmd_dereg_mr(mr); + if (ret) + return ret; + + free(mr); + return 0; +} + +static int align_cq_size(int cqe) +{ + int nent; + + for (nent = 1; nent < cqe; nent <<= 1) + ; /* nothing */ + + return nent; +} + +struct ibv_cq *hgrnic_create_cq(struct ibv_context *context, int cqe, + struct ibv_comp_channel *channel, + int comp_vector) +{ + struct hgrnic_create_cq cmd; + struct hgrnic_create_cq_resp resp; + struct hgrnic_cq *cq; + int ret; + + /* Sanity check CQ size before proceeding */ + if (cqe > 0x20000) + return NULL; + + cq = malloc(sizeof *cq); + if (!cq) + return NULL; + + cq->cons_index = 0; + + if (pthread_spin_init(&cq->lock, PTHREAD_PROCESS_PRIVATE)) + goto err; + + cqe = align_cq_size(cqe); + cq->cqe_mask = cqe - 1; // cqe is in log size, so (cqe - 1) could be the mask + if (hgrnic_alloc_cq_buf(to_hgdev(context->device), &cq->buf, cqe)) + goto err; + + cq->mr = __hgrnic_reg_mr(to_hgctx(context)->pd, cq->buf.buf, + cqe * HGRNIC_CQ_ENTRY_SIZE, + 0, IBV_ACCESS_LOCAL_WRITE, 1); + if (!cq->mr) + goto err_buf; + + cq->mr->context = context; + + cmd.lkey = cq->mr->lkey; + cmd.pdn = to_hgpd(to_hgctx(context)->pd)->pdn; + ret = ibv_cmd_create_cq(context, cqe - 1, channel, comp_vector, + &cq->ibv_cq, &cmd.ibv_cmd, sizeof cmd, + &resp.ibv_resp, sizeof resp); + if (ret) + goto err_unreg; + + cq->cqn = resp.cqn; + + //printf("create_cq: cqn 0x%x, lkey 0x%x, cq_handle %d\n", cq->cqn, cq->mr->lkey, cq->ibv_cq.handle); + + { + //printf("\033[1;32;40m-------\n"); + //printf("function name:%s, %s\n", __func__, __FILE__); + void *buffer[100]; + memset(buffer, 0, 100 * (sizeof(void *))); + int nptrs = backtrace(buffer, 100); + //printf("backtrace() returned %d addresses\n", nptrs); + // char * file_name[200] = my_ompi_code_path_name; + // sprintf(file_name + strlen(file_name), "hgrnic_create_cq.log", ); + int fd = open(my_ompi_code_path_name "hgrnic_create_cq.log", O_CREAT | O_RDWR | O_APPEND, S_IRWXO); + //printf("fd = %d\n", fd); + + char full_str[1000] = {}; + sprintf(full_str, "pid:%d,tid:%ld,in function:%s\n", getpid(), syscall(__NR_gettid), __func__); + write(fd, full_str, strlen(full_str)); + backtrace_symbols_fd(buffer, nptrs, fd); + close(fd); + //printf("\n-------\033[0;m\n"); + } + { + //printf("pid:%d,tid:%ld,in function:%s\n", getpid(), syscall(__NR_gettid), __func__); + } + + //printf("hgrnic_create_cq create cq cqn 0x%x, handle %u\n", cq->cqn, cq->ibv_cq.handle); + if(0) + { + static int k = 0; + k++; + int q = 2; + if (k == q) + { + printf("k = %d\n",k); + while (1) + { + } + } + } + return &cq->ibv_cq; + +err_unreg: + hgrnic_dereg_mr(cq->mr); + +err_buf: + hgrnic_free_buf(&cq->buf); + +err: + free(cq); + + return NULL; +} + +int hgrnic_resize_cq(struct ibv_cq *ibcq, int cqe) +{ + struct hgrnic_cq *cq = to_hgcq(ibcq); + struct hgrnic_resize_cq cmd; + struct ibv_mr *mr; + struct hgrnic_buf buf; + int old_cqe; + int ret; + + if (cqe > 0x20000) + return EINVAL; + + /* The code block below executes atomically. + hgrnic_poll_one cannot execute at this time. */ + pthread_spin_lock(&cq->lock); + + cqe = align_cq_size(cqe); + cq->cqe_mask = cqe - 1; + if (cqe == ibcq->cqe + 1) + { + ret = 0; + goto out; + } + + ret = hgrnic_alloc_cq_buf(to_hgdev(ibcq->context->device), &buf, cqe); + if (ret) + goto out; + + mr = __hgrnic_reg_mr(to_hgctx(ibcq->context)->pd, buf.buf, + cqe * HGRNIC_CQ_ENTRY_SIZE, + 0, IBV_ACCESS_LOCAL_WRITE, 1); + if (!mr) + { + hgrnic_free_buf(&buf); + ret = ENOMEM; + goto out; + } + + mr->context = ibcq->context; + + old_cqe = ibcq->cqe; /* cqe in ibv_cq can be the mask */ + + cmd.lkey = mr->lkey; + + struct ibv_resize_cq_resp resp; + ret = ibv_cmd_resize_cq(ibcq, cqe - 1, &cmd.ibv_cmd, sizeof cmd, + &resp, sizeof resp); + if (ret) + { + hgrnic_dereg_mr(mr); + hgrnic_free_buf(&buf); + goto out; + } + + hgrnic_cq_resize_copy_cqes(cq, buf.buf, old_cqe); + + hgrnic_dereg_mr(cq->mr); + hgrnic_free_buf(&cq->buf); + + cq->buf = buf; + cq->mr = mr; + +out: + pthread_spin_unlock(&cq->lock); + return ret; +} + +int hgrnic_destroy_cq(struct ibv_cq *cq) +{ + int ret; + + ret = ibv_cmd_destroy_cq(cq); + if (ret) + return ret; + + hgrnic_dereg_mr(to_hgcq(cq)->mr); + hgrnic_free_buf(&to_hgcq(cq)->buf); + free(to_hgcq(cq)); + + return 0; +} + +static int align_queue_size(struct ibv_context *context, int size, int spare) +{ + int ret; + + /* + * If someone asks for a 0-sized queue, presumably they're not + * going to use it. So don't mess with their size. + */ + if (!size) + return 0; + + for (ret = 1; ret < size + spare; ret <<= 1) + ; /* nothing */ + + return ret; +} + +struct ibv_qp *hgrnic_create_qp(struct ibv_pd *pd, struct ibv_qp_init_attr *attr) +{ + //fprintf(stderr, "\033[32m libhgrnic : Enter create qp! \033[0m\n"); + struct hgrnic_create_qp cmd; + struct ibv_create_qp_resp resp; + struct hgrnic_qp *qp; + int ret; + + /* Sanity check QP size before proceeding */ + if (attr->cap.max_send_wr > 65536 || + attr->cap.max_recv_wr > 65536 || + attr->cap.max_send_sge > 64 || + attr->cap.max_recv_sge > 64 || + attr->cap.max_inline_data > 1024) + { + //fprintf(stderr, "\033[31m QP size check failed! \033[0m\n"); + return NULL; + } + + qp = malloc(sizeof *qp); + if (!qp) + return NULL; + +// printf("max_send_wr %d, max_recv_wr %d, max_send_sge %d, max_recv_sge %d\n", +// attr->cap.max_send_wr, attr->cap.max_recv_wr, attr->cap.max_send_sge, attr->cap.max_recv_sge); +// + qp->sq.max = align_queue_size(pd->context, attr->cap.max_send_wr, 0); + qp->rq.max = align_queue_size(pd->context, attr->cap.max_recv_wr, 0); + + if (hgrnic_alloc_qp_buf(pd, &attr->cap, attr->qp_type, qp)) + goto err; + + if (pthread_spin_init(&qp->sq.lock, PTHREAD_PROCESS_PRIVATE) || + pthread_spin_init(&qp->rq.lock, PTHREAD_PROCESS_PRIVATE)) + goto err_free; + + qp->sq.mr = __hgrnic_reg_mr(pd, qp->sq.buf.buf, qp->sq.buf_size, 0, 0, 0); + if (!qp->sq.mr) + goto err_free; + + qp->sq.mr->context = pd->context; + cmd.sq_lkey = qp->sq.mr->lkey; + + if (qp->rq.buf_size) + { + qp->rq.mr = __hgrnic_reg_mr(pd, qp->rq.buf.buf, qp->rq.buf_size, 0, 0, 0); + if (!qp->sq.mr) + goto err_sq_mr_unreg; + + qp->rq.mr->context = pd->context; + cmd.rq_lkey = qp->rq.mr->lkey; + } + + pthread_mutex_lock(&to_hgctx(pd->context)->qp_table_mutex); + //printf("pthread_mutex_lock\n"); + ret = ibv_cmd_create_qp(pd, &qp->ibv_qp, attr, &cmd.ibv_cmd, sizeof cmd, + &resp, sizeof resp); + if (ret) + goto err_rq_mr_unreg; + //printf("ibv_cmd_create_qp qptype = %d, qpn = %u\n", qp->ibv_qp.qp_type, qp->ibv_qp.qp_num); + + ret = hgrnic_store_qp(to_hgctx(pd->context), qp->ibv_qp.qp_num, qp); + if (ret) + goto err_destroy; + pthread_mutex_unlock(&to_hgctx(pd->context)->qp_table_mutex); + //printf("hgrnic_store_qp\n"); + + // qp->sq.max = attr->cap.max_send_wr; + // qp->rq.max = attr->cap.max_recv_wr; + // qp->sq.max_gs = attr->cap.max_send_sge; + // qp->rq.max_gs = attr->cap.max_recv_sge; + qp->max_inline_data = attr->cap.max_inline_data; + + //fprintf(stderr, "\033[32m libhgrnic : Exit create qp! \033[0m\n"); + return &qp->ibv_qp; + +err_destroy: + //fprintf(stderr, "\033[31m libhgrnic : err_destory! \033[0m\n"); + ibv_cmd_destroy_qp(&qp->ibv_qp); + +err_rq_mr_unreg: + //fprintf(stderr, "\033[31m libhgrnic : err_rq_mr_unreg! \033[0m\n"); + pthread_mutex_unlock(&to_hgctx(pd->context)->qp_table_mutex); + if (qp->rq.buf_size) + hgrnic_dereg_mr(qp->rq.mr); + +err_sq_mr_unreg: + //fprintf(stderr, "\033[31m libhgrnic : err_sq_mr_unreg! \033[0m\n"); + hgrnic_dereg_mr(qp->sq.mr); + +err_free: + //fprintf(stderr, "\033[31m libhgrnic : err_free! \033[0m\n"); + free(qp->sq.wrid); + free(qp->rq.wrid); + hgrnic_free_buf(&qp->sq.buf); + hgrnic_free_buf(&qp->rq.buf); + +err: + //fprintf(stderr, "\033[31m libhgrnic : err! \033[0m\n"); + free(qp); + + //fprintf(stderr, "\033[31m libhgrnic : Exit create qp! \033[0m\n"); + return NULL; +} + +int hgrnic_query_qp(struct ibv_qp *qp, struct ibv_qp_attr *attr, + enum ibv_qp_attr_mask attr_mask, + struct ibv_qp_init_attr *init_attr) +{ + struct ibv_query_qp cmd; + + return ibv_cmd_query_qp(qp, attr, attr_mask, init_attr, &cmd, sizeof cmd); +} + +int hgrnic_modify_qp(struct ibv_qp *qp, struct ibv_qp_attr *attr, + enum ibv_qp_attr_mask attr_mask) +{ + struct ibv_modify_qp cmd; + int ret; + + ret = ibv_cmd_modify_qp(qp, attr, attr_mask, &cmd, sizeof cmd); + + if (!ret && + (attr_mask & IBV_QP_STATE) && + attr->qp_state == IBV_QPS_RESET) + { + hgrnic_cq_clean(to_hgcq(qp->recv_cq), qp->qp_num); + if (qp->send_cq != qp->recv_cq) + hgrnic_cq_clean(to_hgcq(qp->send_cq), qp->qp_num); + + hgrnic_init_qp_indices(to_hgqp(qp)); + } + + return ret; +} + +static void hgrnic_lock_cqs(struct ibv_qp *qp) +{ + struct hgrnic_cq *send_cq = to_hgcq(qp->send_cq); + struct hgrnic_cq *recv_cq = to_hgcq(qp->recv_cq); + + if (send_cq == recv_cq) + pthread_spin_lock(&send_cq->lock); + else if (send_cq->cqn < recv_cq->cqn) + { + pthread_spin_lock(&send_cq->lock); + pthread_spin_lock(&recv_cq->lock); + } + else + { + pthread_spin_lock(&recv_cq->lock); + pthread_spin_lock(&send_cq->lock); + } +} + +static void hgrnic_unlock_cqs(struct ibv_qp *qp) +{ + struct hgrnic_cq *send_cq = to_hgcq(qp->send_cq); + struct hgrnic_cq *recv_cq = to_hgcq(qp->recv_cq); + + if (send_cq == recv_cq) + pthread_spin_unlock(&send_cq->lock); + else if (send_cq->cqn < recv_cq->cqn) + { + pthread_spin_unlock(&recv_cq->lock); + pthread_spin_unlock(&send_cq->lock); + } + else + { + pthread_spin_unlock(&send_cq->lock); + pthread_spin_unlock(&recv_cq->lock); + } +} + +int hgrnic_destroy_qp(struct ibv_qp *qp) +{ + int ret; + + pthread_mutex_lock(&to_hgctx(qp->context)->qp_table_mutex); + ret = ibv_cmd_destroy_qp(qp); + if (ret) + { + pthread_mutex_unlock(&to_hgctx(qp->context)->qp_table_mutex); + return ret; + } + + hgrnic_lock_cqs(qp); + + __hgrnic_cq_clean(to_hgcq(qp->recv_cq), qp->qp_num); + if (qp->send_cq != qp->recv_cq) + __hgrnic_cq_clean(to_hgcq(qp->send_cq), qp->qp_num); + + hgrnic_clear_qp(to_hgctx(qp->context), qp->qp_num); + + hgrnic_unlock_cqs(qp); + pthread_mutex_unlock(&to_hgctx(qp->context)->qp_table_mutex); + + hgrnic_dereg_mr(to_hgqp(qp)->sq.mr); + hgrnic_dereg_mr(to_hgqp(qp)->rq.mr); + hgrnic_free_buf(&to_hgqp(qp)->sq.buf); + hgrnic_free_buf(&to_hgqp(qp)->rq.buf); + free(to_hgqp(qp)->sq.wrid); + free(to_hgqp(qp)->rq.wrid); + free(to_hgqp(qp)); + + return 0; +} + +struct ibv_ah *hgrnic_create_ah(struct ibv_pd *pd, struct ibv_ah_attr *attr) +{ + struct hgrnic_ah *ah; + + ah = malloc(sizeof *ah); + if (!ah) + return NULL; + + if (hgrnic_alloc_av(to_hgpd(pd), attr, ah)) + { + free(ah); + return NULL; + } + + return &ah->ibv_ah; +} + +int hgrnic_destroy_ah(struct ibv_ah *ah) +{ + hgrnic_free_av(to_hgah(ah)); + free(to_hgah(ah)); + + return 0; +} diff --git a/ETH-PLUS_Jingzhao/JingZhao2/software/drivers/libhgrnic/src/wqe.h b/ETH-PLUS_Jingzhao/JingZhao2/software/drivers/libhgrnic/src/wqe.h new file mode 100644 index 0000000000000000000000000000000000000000..d3a3737758907b32777328e8864a77734dc001f0 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/software/drivers/libhgrnic/src/wqe.h @@ -0,0 +1,100 @@ +/* + * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved. + * Copyright (c) 2005 Cisco Systems. All rights reserved. + * + * This software is available to you under a choice of one of two + * licenses. You may choose to be licensed under the terms of the GNU + * General Public License (GPL) Version 2, available from the file + * COPYING in the main directory of this source tree, or the + * OpenIB.org BSD license below: + * + * Redistribution and use in source and binary forms, with or + * without modification, are permitted provided that the following + * conditions are met: + * + * - Redistributions of source code must retain the above + * copyright notice, this list of conditions and the following + * disclaimer. + * + * - Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials + * provided with the distribution. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#ifndef WQE_H +#define WQE_H + +enum { + HGRNIC_SEND_DOORBELL = 0x00, + HGRNIC_RECV_DOORBELL = 0x18 +}; + +enum { + HGRNIC_NEXT_DBD = 1 << 7, + HGRNIC_NEXT_FENCE = 1 << 6, + HGRNIC_NEXT_VALID = 1 << 5, // indicate that this next_unit is valid + HGRNIC_NEXT_CQ_UPDATE = 1 << 3, + HGRNIC_NEXT_EVENT_GEN = 1 << 2, + HGRNIC_NEXT_SOLICIT = 1 << 1, +}; + +enum { + HGRNIC_INLINE_UNIT = 1 << 31 +}; + +enum { + HGRNIC_INVAL_LKEY = 0x0, + HGRNIC_MAX_WQES_PER_SEND_DB = 255 +}; + +struct hgrnic_next_unit { + uint32_t nda_nop; /* [31:6] next WQE [4:0] next opcode */ + uint32_t ee_nds; /* [31:8] next EE [7] DBD [6] F [5:0] next WQE size */ + uint32_t flags; /* [3] CQ [2] Event [1] Solicit */ + uint32_t imm; /* immediate data */ +}; + +struct hgrnic_ud_unit { + uint32_t port; + uint16_t slid; + uint16_t dlid; + uint32_t smac_h; + uint32_t dmac_h; + uint32_t rsvd1[4]; + uint32_t dqpn; + uint32_t qkey; + uint32_t rsvd2[2]; +}; + +struct hgrnic_raddr_unit { + uint64_t raddr; + uint32_t rkey; + uint32_t reserved; +}; + +struct hgrnic_atomic_seg { + uint64_t swap_add; + uint64_t compare; +}; + +struct hgrnic_data_unit { + uint32_t byte_count; + uint32_t lkey; + uint64_t addr; +}; + +struct hgrnic_inline_unit { + uint32_t byte_count; +}; + +#endif /* WQE_H */ diff --git a/ETH-PLUS_Jingzhao/JingZhao2/verification/README.md b/ETH-PLUS_Jingzhao/JingZhao2/verification/README.md new file mode 100644 index 0000000000000000000000000000000000000000..8de0a4a0f10d60a1457db741bde47fd8af42abf7 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/verification/README.md @@ -0,0 +1 @@ +Verification platform diff --git a/ETH-PLUS_Jingzhao/JingZhao2/verification/bin/DirectedTesting/csrc/cgproc.10236.json b/ETH-PLUS_Jingzhao/JingZhao2/verification/bin/DirectedTesting/csrc/cgproc.10236.json new file mode 100644 index 0000000000000000000000000000000000000000..63bc094ee296cf0da28c701369cd08a2af797bc6 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/verification/bin/DirectedTesting/csrc/cgproc.10236.json @@ -0,0 +1,19812 @@ +{ + "Modules": { + "async_fifo_v7_96W_16D_memory": { + "start_perf": [ + 22.828517913818359, + 22.060765, + 0.584426, + 527972, + 569804, + 1755951392.998956, + 1910532678121 + ], + "child_modules": { + "async_fifo_v7_96W_16D_blk_mem_gen_v8_4_3": 1, + "FDRE": 96 + }, + "end_perf": [ + 22.829277992248535, + 22.061523999999999, + 0.584426, + 527972, + 569804, + 1910534913975, + 1404454305793, + 0 + ], + "Compiled": "Yes", + "nMops": 0, + "nQuads": 0, + "Compiled Times": 1, + "nRouts": 5 + }, + "uvm_pkg": { + "start_perf": [ + 14.302165985107422, + 13.771710000000001, + 0.34829599999999999, + 523876, + 569804, + 1755951384.472604, + 1885648514651 + ], + "child_modules": {}, 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+1,178 @@ +//CREATE INFORMATION +//---------------------------------------------------------------------------- +// +// (C) COPYRIGHT 2021 BY ICT-HPC CORPORATION ALL RIGHTS RESERVED +// DATE : 2021-04-12 +// AUTHOR : mazhenlong@ncic.ac.cn +// FILENAME : hca_addr_align.sv +// VERSION : v1.0 +// FUNCTION : This file supplies the function of address aligns, other +// component or object can use the common object. +// +//---------------------------------------------------------------------------- + +//CHANGE HISTORY +//---------------------------------------------------------------------------- +// +// AUTHOR DATE VERSION REASON +// mazhenlong 2021-04-12 v1.0 modified from chpp_addr_align +// +//---------------------------------------------------------------------------- + +`ifndef __HCA_ADDR_ALIGN__ +`define __HCA_ADDR_ALIGN__ + +//------------------------------------------------------------------------------ +// +// CLASS: hca_addr_align +// +//------------------------------------------------------------------------------ + +class hca_addr_align #(type T = addr64_typ) extends uvm_object; + + // variables + typedef hca_addr_align #(T) this_typ; + T addr; + hca_math_func math; + + // provide implementations of virtual methods such as get_type_name and create + `uvm_object_param_utils_begin(hca_addr_align #(T)) + `uvm_field_object(math, UVM_DEFAULT) + `uvm_object_utils_end + + // functions and tasks + //------------------------------------------------------------------------------ + // function name : new + // function : constructor + // invoked : be invoked when instantiates hca_addr_align + //------------------------------------------------------------------------------ + function new(string name = "hca_addr_align"); + super.new(name); + math = hca_math_func::type_id::create("math"); + endfunction + + //------------------------------------------------------------------------------ + // function name : addr_align_1byte + // function : judge whether the address is 1 byte aligned + // invoked : be invoked by user + //------------------------------------------------------------------------------ + function bool addr_align_1byte(T addr); + return TRUE; + endfunction : addr_align_1byte + + //------------------------------------------------------------------------------ + // function name : addr_align_2byte + // function : judge whether the address is 2 bytes aligned + // invoked : be invoked by user + //------------------------------------------------------------------------------ + function bool addr_align_2byte(T addr); + if (addr[0] == 'b0) begin + return TRUE; + end + else begin + return FALSE; + end + endfunction : addr_align_2byte + + //------------------------------------------------------------------------------ + // function name : addr_align_4byte + // function : judge whether the address is 4 bytes aligned + // invoked : be invoked by user + //------------------------------------------------------------------------------ + function bool addr_align_4byte(T addr); + if (addr[1:0] == 'b0) begin + return TRUE; + end + else begin + return FALSE; + end + endfunction : addr_align_4byte + + //------------------------------------------------------------------------------ + // function name : addr_align_8byte + // function : judge whether the address is 8 bytes aligned + // invoked : be invoked by user + //------------------------------------------------------------------------------ + function bool addr_align_8byte(T addr); + if (addr[2:0] == 'b0) begin + return TRUE; + end + else begin + return FALSE; + end + endfunction : addr_align_8byte + + //------------------------------------------------------------------------------ + // function name : addr_align_dw + // function : judge whether the address is DW aligned + // invoked : be invoked by user + //------------------------------------------------------------------------------ + function bool addr_align_dw(T addr); + if (addr[`DW_ALIGNED_WIDTH-1:0] == 'b0) begin + return TRUE; + end + else begin + return FALSE; + end + endfunction : addr_align_dw + + //------------------------------------------------------------------------------ + // function name : addr_align_line + // function : judge whether the address is line aligned + // invoked : be invoked by user + //------------------------------------------------------------------------------ + function bool addr_align_line(int line_size, T addr); + bit zero = 0; + int align_bits; + align_bits = math.log_func(line_size/`BYTE_BIT_WIDTH); + //if ((addr & {align_bits{1'b1}}) == 'b0) begin + // return TRUE; + //end + //else begin + // return FALSE; + //end + for (int i = 0; i < align_bits; i++) begin + zero |= addr[i]; + end + return zero ? FALSE : TRUE; + endfunction : addr_align_line + + //------------------------------------------------------------------------------ + // function name : addr_align_border + // function : judge whether the address is line aligned + // invoked : be invoked by user + //------------------------------------------------------------------------------ + function bool addr_align_border(int border_size, T addr); + bit zero = 0; + int align_bits; + align_bits = math.log_func(border_size/`BYTE_BIT_WIDTH); + //if ((addr & {align_bits{1'b1}}) == 'b0) begin + // return TRUE; + //end + //else begin + // return FALSE; + //end + for (int i = 0; i < align_bits; i++) begin + zero |= addr[i]; + end + return zero ? FALSE : TRUE; + endfunction : addr_align_border + + //------------------------------------------------------------------------------ + // function name : next_border_align_addr + // function : judge whether the address is DW aligned + // invoked : be invoked by user + //------------------------------------------------------------------------------ + function T next_border_align_addr(int border_size, T addr); + T addr_tmp; + int align_bits; + align_bits = math.log_func(border_size); + addr_tmp = addr >> align_bits; + addr_tmp++; + addr_tmp <<= align_bits; + return addr_tmp; + endfunction : next_border_align_addr + +endclass : hca_addr_align + +`endif diff --git a/ETH-PLUS_Jingzhao/JingZhao2/verification/src/vrf_HTN/sv/common/hca_addr_table.sv b/ETH-PLUS_Jingzhao/JingZhao2/verification/src/vrf_HTN/sv/common/hca_addr_table.sv new file mode 100644 index 0000000000000000000000000000000000000000..e0b358e867db48f81f7f45734068a33de7bf163b --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/verification/src/vrf_HTN/sv/common/hca_addr_table.sv @@ -0,0 +1,155 @@ +//CREATE INFORMATION +//---------------------------------------------------------------------------- +// +// (C) COPYRIGHT 2021 BY ICT-HPC CORPORATION ALL RIGHTS RESERVED +// DATE : 2021-04-06 +// AUTHOR : mazhenlong@ncic.ac.cn +// FILENAME : hca_addr_table.sv +// FUNCTION : This file supplies the address table of HCA. +// +//---------------------------------------------------------------------------- + +//CHANGE HISTORY +//---------------------------------------------------------------------------- +// +// AUTHOR DATE VERSION REASON +// mazhenlong 2021-04-06 v1.0 create +// +//---------------------------------------------------------------------------- + +`ifndef __HCA_ADDR_TABLE__ +`define __HCA_ADDR_TABLE__ + +class hca_addr_table extends uvm_object; + + rand bit [63:0] qpc_base; + rand bit [7:0] log_num_qps; + rand bit [63:0] cqc_base; + rand bit [7:0] log_num_cqs; + rand bit [63:0] eqc_base; + rand bit [7:0] log_num_eqs; + rand bit [63:0] mpt_base; + rand bit [7:0] log_mpt_sz; + rand bit [63:0] mtt_base; + + rand bit [63:0] inbox_addr; + rand bit [63:0] outbox_addr; + + bit [11:0] config_status; // current command + + // hca_mpt mpt[$]; + bit [`ADDR_WIDTH - 1 : 0] mtt[$]; + + bit [`ADDR_WIDTH - 1 : 0] icm_virt_addr[$]; + bit [`ADDR_WIDTH - 1 : 0] icm_phys_addr[$]; + + bit [`ADDR_WIDTH - 1 : 0] mem_virt_addr[$]; + bit [`ADDR_WIDTH - 1 : 0] mem_phys_addr[$]; + + qp_context qp_list[$]; + + constraint icm_base_addr { + qpc_base == `QPC_OFFSET; + cqc_base == `CQC_OFFSET; + mpt_base == `MPT_OFFSET; + mtt_base == `MTT_OFFSET; + log_num_qps == `LOG_NUM_QPS; + log_num_cqs == `LOG_NUM_CQS; + log_mpt_sz == `LOG_MPT_SZ; + + inbox_addr == `INBOX_ADDR; + outbox_addr == `OUTBOX_ADDR; + } + + `uvm_object_param_utils_begin(hca_addr_table) + `uvm_object_utils_end + + //------------------------------------------------------------------------------ + // function name : new + // function : constructor + // invoked : invoked when instantiates the class + //------------------------------------------------------------------------------ + function new(string name = "hca_addr_table"); + super.new(name); + endfunction: new + + //------------------------------------------------------------------------------ + // task name : gen_base_addr + // function : generate base address of qp context and cq context + // invoked : by user + //------------------------------------------------------------------------------ + task gen_base_addr(); + qpc_base = 64'h0000_0001_0000_0000; + cqc_base = 64'h0; + endtask: gen_base_addr; + + //------------------------------------------------------------------------------ + // task name : map_icm + // function : map icm space address to physical address. + // type: 1 - qp + // 2 - cq + // 3 - mpt + // 4 - mtt + // invoked : by user + //------------------------------------------------------------------------------ + //---------------------------NOTICE: TASK TO BE FIXED!------------------------// + task map_icm(int typ, int page_num, ref bit [`ADDR_WIDTH - 1 : 0] temp_virt_addr, ref bit [`ADDR_WIDTH - 1 : 0] temp_phys_addr); + // bit [`ADDR_WIDTH - 1 : 0] temp_virt_addr; + // bit [`ADDR_WIDTH - 1 : 0] temp_phys_addr; + if (typ == 1) begin + temp_virt_addr = `QPC_OFFSET; + temp_phys_addr = `ICM_BASE + `QPC_OFFSET; + end + else if (typ == 2) begin + temp_virt_addr = `CQC_OFFSET; + temp_phys_addr = `ICM_BASE + `CQC_OFFSET; + end + else if (typ == 3) begin + temp_virt_addr = `MPT_OFFSET; + temp_phys_addr = `ICM_BASE + `MPT_OFFSET; + end + else if (typ == 4) begin + temp_virt_addr = `MTT_OFFSET; + temp_phys_addr = `ICM_BASE + `MTT_OFFSET; + end + for (int i = 0; i < page_num; i++) begin + foreach (icm_virt_addr[j]) begin + if (icm_virt_addr[j] == temp_virt_addr && icm_phys_addr[j] == temp_phys_addr) begin + temp_virt_addr += 4096; + temp_phys_addr += 4096; + end + else if (icm_virt_addr[j] > temp_virt_addr && icm_phys_addr[j] > temp_phys_addr) begin + temp_virt_addr = icm_virt_addr[j] + 4096; + temp_phys_addr = icm_phys_addr[j] + 4096; + end + end + icm_virt_addr.push_back(temp_virt_addr); + icm_phys_addr.push_back(temp_phys_addr); + end + endtask: map_icm + + //------------------------------------------------------------------------------ + // task name : write_mtt + // function : allocate physical address in data page, only one page! + // invoked : by user + //------------------------------------------------------------------------------ + task write_mtt(int page_num, ref bit [`ADDR_WIDTH - 1 : 0] temp_virt_addr, ref bit [`ADDR_WIDTH - 1 : 0] temp_phys_addr); + int j = 0; + temp_virt_addr = 0; + temp_phys_addr = `DATA_BASE; + foreach(mem_phys_addr[i]) begin + if (mem_virt_addr[i] == temp_virt_addr && mem_phys_addr[i] == temp_phys_addr) begin + temp_virt_addr = mem_virt_addr[i] + 4096; + temp_phys_addr = mem_phys_addr[i] + 4096; + end + mem_virt_addr.push_back(temp_virt_addr); + mem_phys_addr.push_back(temp_phys_addr); + j++; + if (j == page_num || j > page_num) begin + break; + end + end + endtask: write_mtt +endclass: hca_addr_table + +`endif \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/verification/src/vrf_HTN/sv/common/hca_check_mem_list.sv b/ETH-PLUS_Jingzhao/JingZhao2/verification/src/vrf_HTN/sv/common/hca_check_mem_list.sv new file mode 100644 index 0000000000000000000000000000000000000000..87f8190803f4f5c4305d8a133297650754975be5 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/verification/src/vrf_HTN/sv/common/hca_check_mem_list.sv @@ -0,0 +1,50 @@ +//CREATE INFORMATION +//----------------------------------------------------------------------------------------------- +// +// (C) COPYRIGHT 2021 BY ICT-HPC CORPORATION ALL RIGHTS RESERVED +// DATE : 2021-09-14 +// AUTHOR : mazhenlong@ncic.ac.cn +// FILENAME : hca_mem_info.sv +// FUNCTION : . +// +//----------------------------------------------------------------------------------------------- + +//CHANGE HISTORY +//----------------------------------------------------------------------------------------------- +// +// AUTHOR DATE VERSION REASON +// mazhenlong 2020-09-14 v1.0 create +// +//----------------------------------------------------------------------------------------------- + +`ifndef __HCA_CHECK_MEM_LIST__ +`define __HCA_CHECK_MEM_LIST__ + +//---------------------------------------------------------------------------- +// +// CLASS: hca_check_mem_list +// +//---------------------------------------------------------------------------- +class hca_check_mem_list extends uvm_object; + + check_mem_unit check_list[][$]; + + `uvm_object_utils_begin(hca_check_mem_list) + `uvm_object_utils_end + + + //------------------------------------------------------------------------------ + // function name : new + // function : constructor + // invoked : invoked when instantiates the class + //------------------------------------------------------------------------------ + function new(string name = "hca_check_mem_list"); + super.new(name); + endfunction + + function init(int host_num); + check_list = new[host_num]; + endfunction: init + +endclass: hca_check_mem_list +`endif \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/verification/src/vrf_HTN/sv/common/hca_comp_queue.sv b/ETH-PLUS_Jingzhao/JingZhao2/verification/src/vrf_HTN/sv/common/hca_comp_queue.sv new file mode 100644 index 0000000000000000000000000000000000000000..1ea023b50a05df0f6a79ed6f51b1331163e3288c --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/verification/src/vrf_HTN/sv/common/hca_comp_queue.sv @@ -0,0 +1,56 @@ +//CREATE INFORMATION +//----------------------------------------------------------------------------------------------- +// +// (C) COPYRIGHT 2021 BY ICT-HPC CORPORATION ALL RIGHTS RESERVED +// DATE : 2021-09-16 +// AUTHOR : mazhenlong@ncic.ac.cn +// FILENAME : hca_comp_queue.sv +// FUNCTION : This file supplies the env of verification of HCA. +// +//----------------------------------------------------------------------------------------------- + +//CHANGE HISTORY +//----------------------------------------------------------------------------------------------- +// +// AUTHOR DATE VERSION REASON +// mazhenlong 2020-09-16 v1.0 create +// +//----------------------------------------------------------------------------------------------- + +`ifndef __HCA_COMP_QUEUE__ +`define __HCA_COMP_QUEUE__ + +//---------------------------------------------------------------------------- +// +// CLASS: hca_comp_queue +// +//---------------------------------------------------------------------------- +class hca_comp_queue extends uvm_object; + + cq_context ctx; + addr header; + addr tail; + addr last_header; + cqe cqe_list[$]; + + `uvm_object_utils_begin(hca_comp_queue) + `uvm_object_utils_end + + + //------------------------------------------------------------------------------ + // function name : new + // function : constructor + // invoked : invoked when instantiates the class + //------------------------------------------------------------------------------ + function new(string name = "hca_comp_queue"); + super.new(name); + endfunction + + task put_cqe(cqe input_cqe); + cqe_list.push_back(input_cqe); + endtask: put_cqe + + // cqe get_cqe() + +endclass: hca_comp_queue +`endif \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/verification/src/vrf_HTN/sv/common/hca_fifo.sv b/ETH-PLUS_Jingzhao/JingZhao2/verification/src/vrf_HTN/sv/common/hca_fifo.sv new file mode 100644 index 0000000000000000000000000000000000000000..ecf0293c4d0a3c0acdd2c22026f3c7df9e8a2bfa --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/verification/src/vrf_HTN/sv/common/hca_fifo.sv @@ -0,0 +1,253 @@ +//CREATE INFORMATION +//---------------------------------------------------------------------------- +// +// (C) COPYRIGHT 2021 BY ICT-HPC CORPORATION ALL RIGHTS RESERVED +// DATE : 2021-03-17 +// AUTHOR : mazhenlong@ncic.ac.cn +// FILENAME : hca_fifo.sv +// FUNCTION : This file supplies the fifo of verification of HCA. +// +//---------------------------------------------------------------------------- + +//CHANGE HISTORY +//---------------------------------------------------------------------------- +// +// AUTHOR DATE VERSION REASON +// mazhenlong 2021-03-17 v1.0 modified from chpp_fifo +// +//---------------------------------------------------------------------------- + +`ifndef __HCA_FIFO__ +`define __HCA_FIFO__ + +//------------------------------------------------------------------------------ +// +// CLASS: hca_fifo +// +//------------------------------------------------------------------------------ + +class hca_fifo #(int width=128) extends uvm_object; + + // variables + // user define + typedef hca_fifo #(width) this_typ; + // memory unit + bit [`BYTE_BIT_WIDTH-1:0] mem[$]; + // depth of memory + int depth; + + // provide implementations of virtual methods such as get_type_name and create + `uvm_object_param_utils_begin(hca_fifo #(width)) + `uvm_field_queue_int(mem, UVM_DEFAULT) + `uvm_field_int(depth, UVM_DEFAULT|UVM_DEC) + `uvm_object_utils_end + + // functions and tasks + //------------------------------------------------------------------------------ + // function name : new + // function : constructor + // invoked : be invoked when instantiates hca_fifo + //------------------------------------------------------------------------------ + function new(string name = "hca_fifo"); + super.new(name); + endfunction + + // declare extern functions and tasks + extern function void push(bit[width/`BYTE_BIT_WIDTH-1:0][`BYTE_BIT_WIDTH-1:0] data); + extern function void push_byte(byte_typ data); + extern function void push_dw(bit[`DW_DATA_WIDTH/`BYTE_BIT_WIDTH-1:0][`BYTE_BIT_WIDTH-1:0] data); + extern function void push_2dw(bit[`TWO_DW_WIDTH/`BYTE_BIT_WIDTH-1:0][`BYTE_BIT_WIDTH-1:0] data); + extern function void push_3dw(bit[`THR_DW_WIDTH/`BYTE_BIT_WIDTH-1:0][`BYTE_BIT_WIDTH-1:0] data); + extern function void push_4dw(bit[`FOU_DW_WIDTH/`BYTE_BIT_WIDTH-1:0][`BYTE_BIT_WIDTH-1:0] data); + extern function bit[width-1:0] pop(); + extern function byte_typ pop_byte(); + extern function dw_typ pop_dw(); + extern function two_dw_typ pop_2dw(); + extern function thr_dw_typ pop_3dw(); + extern function fou_dw_typ pop_4dw(); + + extern function void clean(); + extern function void add_fifo(this_typ fifo); + extern function int get_depth(); + +endclass : hca_fifo + +//------------------------------------------------------------------------------ +// function name : push +// function : push data to mem queue +// invoked : be invoked by user +//------------------------------------------------------------------------------ +function void hca_fifo::push(bit[width/`BYTE_BIT_WIDTH-1:0][`BYTE_BIT_WIDTH-1:0] data); + for (int i = 0; i 0)); + while (f > 0) begin + f >>= 1; + x++; + end + return (x-1); + endfunction: log_func + +endclass : hca_math_func + +`endif diff --git a/ETH-PLUS_Jingzhao/JingZhao2/verification/src/vrf_HTN/sv/common/hca_mem_info.sv b/ETH-PLUS_Jingzhao/JingZhao2/verification/src/vrf_HTN/sv/common/hca_mem_info.sv new file mode 100644 index 0000000000000000000000000000000000000000..7e31b35d979b0613b1bdde2183d0bf44c1a82c90 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/verification/src/vrf_HTN/sv/common/hca_mem_info.sv @@ -0,0 +1,52 @@ +//CREATE INFORMATION +//----------------------------------------------------------------------------------------------- +// +// (C) COPYRIGHT 2021 BY ICT-HPC CORPORATION ALL RIGHTS RESERVED +// DATE : 2021-09-14 +// AUTHOR : mazhenlong@ncic.ac.cn +// FILENAME : hca_mem_info.sv +// FUNCTION : . +// +//----------------------------------------------------------------------------------------------- + +//CHANGE HISTORY +//----------------------------------------------------------------------------------------------- +// +// AUTHOR DATE VERSION REASON +// mazhenlong 2020-09-14 v1.0 create +// +//----------------------------------------------------------------------------------------------- + +`ifndef __HCA_MEM_INFO__ +`define __HCA_MEM_INFO__ + +//---------------------------------------------------------------------------- +// +// CLASS: hca_mem_info +// +//---------------------------------------------------------------------------- +class hca_mem_info extends uvm_object; + + mpt mem_region[][$]; + mtt mem_table[][$]; + + `uvm_object_utils_begin(hca_mem_info) + `uvm_object_utils_end + + + //------------------------------------------------------------------------------ + // function name : new + // function : constructor + // invoked : invoked when instantiates the class + //------------------------------------------------------------------------------ + function new(string name = "hca_mem_info"); + super.new(name); + endfunction + + function init(int host_num); + mem_region = new[host_num]; + mem_table = new[host_num]; + endfunction: init + +endclass: hca_mem_info +`endif \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/verification/src/vrf_HTN/sv/common/hca_memory.sv b/ETH-PLUS_Jingzhao/JingZhao2/verification/src/vrf_HTN/sv/common/hca_memory.sv new file mode 100644 index 0000000000000000000000000000000000000000..1b3087f62bf9357a4c61a94e7a42984f314c7687 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/verification/src/vrf_HTN/sv/common/hca_memory.sv @@ -0,0 +1,386 @@ +//CREATE INFORMATION +//---------------------------------------------------------------------------------------------- +// +// (C) COPYRIGHT 2021 BY ICT-HPC CORPORATION ALL RIGHTS RESERVED +// DATE : 2021-01-16 +// AUTHOR : mazhenlong@ncic.ac.cn +// FILENAME : hca_memory.sv +// FUNCTION : This file supplies the env of verification of HCA. +// +//---------------------------------------------------------------------------------------------- + +//CHANGE HISTORY +//---------------------------------------------------------------------------------------------- +// +// AUTHOR DATE VERSION REASON +// mazhenlong 2021-01-16 v1.0 modified from chpp_memory +// mazhenlong 2021-04-06 v1.1 delete contents related to +// rq addr in chpp +// mazhenlong 2021-04-28 v1.2 delete write_2B, write_4B, write_8B, write_16B, +// read_2B, read_4B, read_8B, read_16B; +// delete hspeed methods +// +//---------------------------------------------------------------------------------------------- + +`ifndef __HCA_MEMORY__ +`define __HCA_MEMORY__ + +typedef class hca_mem_cache; +typedef class hca_mem_line; +typedef class hca_addr_align; +typedef class hca_math_func; +typedef class hca_fifo; + +//------------------------------------------------------------------------------------------------ +// +// CLASS: hca_memory +// +//------------------------------------------------------------------------------------------------ + +class hca_memory #(uint line_size=256) extends uvm_object; + + // varaiables + // this_typ + typedef hca_memory #(line_size) this_typ; + typedef hca_fifo #(line_size) fifo_typ; + //parameter depth = 4096; + // parameter depth = 2147483648 * `QP_NUM; // 2G * `QP_NUM + // parameter ulint depth = 16 * 1024 * 4 * 1024 * 1024 * 1024 * 2; + // parameter depth = 16 * 1024 * 4 * 1024 * 1024 * 1024 * 2; + parameter ulint depth = 2147483648; + // bit [`DEPTH_BIT_WIDTH-1: 0] depth = `DEPTH_BIT_WIDTH{1}; + + // memory unit + bit [line_size-1:0] line; + //bit [line_size-1:0] mem[*]; // associative array + hca_mem_cache #(line_size, depth) mem_cache; + int qp_amount = 16384; + hca_mem_cache #(line_size, depth) qp_data_mem[]; + + // address check + hca_addr_align #(mem_addr_typ) addr_align; + + // mathmatics function + hca_math_func math; + + hca_addr_table addr_table; + + bool PRINT_WRITE_LINE_BYTE = FALSE; + + // provide implementations of virtual methods such as get_type_name and create + `uvm_object_param_utils_begin(hca_memory #(line_size)) + `uvm_field_int(line, UVM_DEFAULT|UVM_HEX) + `uvm_field_object(mem_cache, UVM_DEFAULT) + `uvm_field_object(addr_align, UVM_DEFAULT) + `uvm_field_object(math, UVM_DEFAULT) + `uvm_field_enum(bool, PRINT_WRITE_LINE_BYTE, UVM_DEFAULT) + `uvm_object_utils_end + + // functions and tasks + //------------------------------------------------------------------------------ + // function name : new + // function : constructor + // invoked : be invoked when instantiates hca_memory + //------------------------------------------------------------------------------ + function new(string name = "hca_memory"); + super.new(name); + qp_data_mem = new[qp_amount]; // 16K QPs + for (int i = 0; i < qp_amount; i++) begin + qp_data_mem[i] = hca_mem_cache#(line_size, depth)::type_id::create($sformatf("mem_cache[%0d]", i)); + end + math = hca_math_func::type_id::create("math"); + addr_align = hca_addr_align#(mem_addr_typ)::type_id::create("addr_align"); + mem_cache = hca_mem_cache#(line_size, depth)::type_id::create("mem_cache"); + addr_table = hca_addr_table::type_id::create("addr_table"); + endfunction + + // declare extern functions and tasks + extern function void write_byte(mem_addr_typ addr, byte_typ data); + extern function void write_line(ulint idx, bit[line_size-1:0] data); + extern function void write_block(mem_addr_typ addr, fifo_typ fifo, uint length); + + extern function bit[7:0] read_byte(mem_addr_typ addr); + extern function bit[line_size-1:0] read_line(ulint idx); + extern function hca_fifo #(line_size) read_block(mem_addr_typ addr, uint length); + + extern function void reset(); + extern function ulint get_entry_num(); + +endclass : hca_memory + +//------------------------------------------------------------------------------ +// function name : write_byte +// function : write one byte to memory +// invoked : be invoked by write_block function(), etc. +//------------------------------------------------------------------------------ +function void hca_memory::write_byte(mem_addr_typ addr, byte_typ data); + int byte_idx; + ulint line_idx; + int byte_idx_bits; + bit[line_size/`BYTE_BIT_WIDTH-1:0][`BYTE_BIT_WIDTH-1:0] d_line; + byte_idx_bits = math.log_func(line_size/`BYTE_BIT_WIDTH); + + byte_idx = addr & {byte_idx_bits{1'b1}}; + line_idx = addr >> byte_idx_bits; + d_line = mem_cache.get_entry(line_idx); + d_line[byte_idx] = data; + write_line(line_idx, d_line); +endfunction : write_byte + +//------------------------------------------------------------------------------ +// function name : write_line +// function : write one line to memory +// invoked : be invoked by write_byte function(), etc. +//------------------------------------------------------------------------------ +function void hca_memory::write_line(ulint idx, bit[line_size-1:0] data); + mem_cache.add_entry(idx, data); +endfunction : write_line + +//------------------------------------------------------------------------------ +// function name : write_block +// function : write specified data to memory +// invoked : be invoked by user +//------------------------------------------------------------------------------ +function void hca_memory::write_block(mem_addr_typ addr, fifo_typ fifo, uint length); + ulint line_idx; + int byte_idx_bits; + // `uvm_info("NOTICE", $sformatf("write_block"), UVM_LOW); + byte_idx_bits = math.log_func(line_size/`BYTE_BIT_WIDTH); + + //if (addr_align.addr_align_line(line_size, addr) == TRUE) begin + if ((addr_align.addr_align_line(line_size, addr) == TRUE) && (length > line_size/`BYTE_BIT_WIDTH)) begin + for ( ; length > (line_size/`BYTE_BIT_WIDTH); length-=(line_size/`BYTE_BIT_WIDTH), addr+=(line_size/`BYTE_BIT_WIDTH)) begin + line_idx = addr >> byte_idx_bits; + //`define PRINT_WRITE_LINE_BYTE + PRINT_WRITE_LINE_BYTE = TRUE; + write_line(line_idx, fifo.pop()); + PRINT_WRITE_LINE_BYTE = FALSE; + //`undef PRINT_WRITE_LINE_BYTE + end + for ( ; length > 0; length--, addr++) begin + write_byte(addr, fifo.pop_byte()); + end + end + else begin + for ( ; length > 0; length--, addr++) begin + write_byte(addr, fifo.pop_byte()); + end + end +endfunction : write_block + +//------------------------------------------------------------------------------ +// function name : read_byte +// function : read one byte from memory +// invoked : be invoked by read_block function(), etc. +//------------------------------------------------------------------------------ +function bit[7:0] hca_memory::read_byte(mem_addr_typ addr); + int byte_idx; + ulint line_idx; + int byte_idx_bits; + bit[line_size/`BYTE_BIT_WIDTH-1:0][`BYTE_BIT_WIDTH-1:0] d_line; + byte_typ data; + + if ($test$plusargs("CHPP_MEM_RW_MON")) begin + // `CHPP_PRINT_INFO("PRINT/MEM/RW", $time, $sformatf("Read byte, address = 0x%0h", addr), UVM_MEDIUM) + end + + byte_idx_bits = math.log_func(line_size/`BYTE_BIT_WIDTH); + byte_idx = addr & {byte_idx_bits{1'b1}}; + line_idx = addr >> byte_idx_bits; + d_line = mem_cache.get_entry(line_idx); + data = d_line[byte_idx]; + + if ($test$plusargs("CHPP_MEM_RW_MON")) begin + // `CHPP_PRINT_INFO("PRINT/MEM/RW", $time, $sformatf("Read data = 0x%0h", data), UVM_MEDIUM) + end + + return data; +endfunction : read_byte + +//------------------------------------------------------------------------------ +// function name : read_line +// function : read one line from memory +// invoked : be invoked by user +//------------------------------------------------------------------------------ +function bit[hca_memory::line_size-1:0] hca_memory::read_line(ulint idx); + bit[line_size-1:0] d_line; + d_line = mem_cache.get_entry(idx); + + if ($test$plusargs("CHPP_MEM_RW_MON")) begin + // `CHPP_PRINT_INFO("PRINT/MEM/RW", $time, $sformatf("Read line, line index = %0d", idx), UVM_MEDIUM) + end + if ($test$plusargs("CHPP_MEM_RW_MON")) begin + // `CHPP_PRINT_INFO("PRINT/MEM/RW", $time, $sformatf("Read data = 0x%0h", d_line), UVM_MEDIUM) + end + + return d_line; +endfunction : read_line + +//------------------------------------------------------------------------------ +// function name : read_block +// function : read specified bytes from memory +// invoked : be invoked by user +//------------------------------------------------------------------------------ +//change the return type for vcs_vE-2011.03, #(hca_memory::line_size) can only support by 2012 and later version +//function hca_fifo #(hca_memory::line_size) hca_memory::read_block(mem_addr_typ addr, uint length); +function hca_fifo #(`MEM_LINE_SIZE) hca_memory::read_block(mem_addr_typ addr, uint length); + ulint line_idx; + int byte_idx_bits; + bit[line_size/`BYTE_BIT_WIDTH-1:0][`BYTE_BIT_WIDTH-1:0] d_line; + hca_fifo #(line_size) fifo; + `uvm_info("NOTICE", $sformatf("read_block"), UVM_LOW); + fifo = hca_fifo #(line_size)::type_id::create("fifo"); + byte_idx_bits = math.log_func(line_size/`BYTE_BIT_WIDTH); + + if (addr_align.addr_align_line(line_size, addr) == TRUE) begin + for ( ; length > (line_size/`BYTE_BIT_WIDTH); length-=(line_size/`BYTE_BIT_WIDTH), addr+=(line_size/`BYTE_BIT_WIDTH)) begin + line_idx = addr >> byte_idx_bits; + fifo.push(read_line(line_idx)); // mzlnote + end + for ( ; length > 0; length--, addr++) begin + fifo.push_byte(read_byte(addr)); + end + end + else begin + //for ( ; length > (line_size/`BYTE_BIT_WIDTH); length-=(line_size/`BYTE_BIT_WIDTH), addr+=(line_size/`BYTE_BIT_WIDTH)) begin + for ( ; length > (line_size/`BYTE_BIT_WIDTH); length-=(line_size/`BYTE_BIT_WIDTH)) begin + for (int i = 0; i < line_size/`BYTE_BIT_WIDTH; i++, addr++) begin + d_line[i] = read_byte(addr); + end + fifo.push(d_line); + `uvm_info("NOTICE", $sformatf("d_line in read_block in mem: %h, addr: %h", d_line, addr), UVM_LOW); + end + for ( ; length > 0; length--, addr++) begin + fifo.push_byte(read_byte(addr)); + end + end + return fifo; +endfunction : read_block + +//------------------------------------------------------------------------------ +// +// CLASS: hca_mem_cache +// +//------------------------------------------------------------------------------ + +class hca_mem_cache #(uint line_size=`MEM_LINE_SIZE, ulint depth=2147483648 * 16) extends uvm_object; + typedef hca_mem_cache #(line_size) this_typ; + + // cache lines + // hca_mem_line #(line_size) entries[$]; + bit [`MEM_LINE_SIZE - 1 : 0] entries[ulint]; + // bit [line_size + // mathmatics function + hca_math_func math; + // high speed cache line + hca_mem_line #(line_size) hspeed_entry; + // page size + string page_size; + + // provide implementations of virtual methods such as get_type_name and create + `uvm_object_param_utils_begin(hca_mem_cache #(line_size, depth)) + // `uvm_field_queue_object(entries, UVM_DEFAULT) + `uvm_field_object(math, UVM_DEFAULT) + `uvm_field_object(hspeed_entry, UVM_DEFAULT) + `uvm_field_string(page_size, UVM_DEFAULT) + `uvm_object_utils_end + + // functions and tasks + //------------------------------------------------------------------------------ + // function name : new + // function : constructor + // invoked : be invoked when instantiates hca_mem_cache + //------------------------------------------------------------------------------ + function new(string name = "hca_mem_cache"); + super.new(name); + math = hca_math_func::type_id::create("math"); + hspeed_entry = hca_mem_line#(line_size)::type_id::create("hspeed_entry"); + endfunction + + //------------------------------------------------------------------------------ + // function name : add_entry + // function : add one memory line to the entries + // invoked : be invoked by function get_entry() + //------------------------------------------------------------------------------ + function bool add_entry(ulint idx, ref bit[line_size-1:0] value); + hca_mem_line #(line_size) entry; + + entry = hca_mem_line#(line_size)::type_id::create("entry"); + entries[idx] = value; + endfunction : add_entry + + //------------------------------------------------------------------------------ + // function name : get_entry + // function : get one memory line from the entries + // invoked : be invoked by function read_byte(), write_byte(), etc. + //------------------------------------------------------------------------------ + function bit[line_size-1:0] get_entry(ulint idx); + parameter RAND_WIDTH = 32; + parameter RQ_ENTRY_WIDTH = 64; + hca_mem_line #(line_size) hit; + hca_mem_line #(line_size) unhit; + bit[line_size-1:0] d_init; + bit[line_size-1:0] d_tmp; + uint quotient; + uint remainder; + + quotient = uint'(line_size / RAND_WIDTH); + remainder = uint'(line_size % RAND_WIDTH); + + // hit case + if (entries.exists(idx) == 1) begin + return entries[idx]; + end + else begin + // unhit case + unhit = hca_mem_line#(line_size)::type_id::create("unhit"); + if (remainder == 0) begin + d_init = {quotient{$urandom()}}; + unhit.idx = idx; + unhit.value = d_init; + end + else begin + d_tmp = $urandom() & {remainder{1'b1}}; + d_init = {d_tmp, {quotient{$urandom()}}}; + unhit.idx = idx; + unhit.value = d_init; + end + add_entry(idx, unhit.value); + return unhit.value; + end + endfunction : get_entry +endclass : hca_mem_cache + + +//------------------------------------------------------------------------------ +// +// CLASS: hca_mem_line +// +//------------------------------------------------------------------------------ + +class hca_mem_line #(uint line_size=`MEM_LINE_SIZE) extends uvm_object; + typedef hca_mem_line #(line_size) this_typ; + + // index and cache line + ulint idx; + bit [line_size-1:0] value; + + // provide implementations of virtual methods such as get_type_name and create + `uvm_object_param_utils_begin(hca_mem_line #(line_size)) + `uvm_field_int(idx, UVM_DEFAULT|UVM_DEC) + `uvm_field_int(value, UVM_DEFAULT|UVM_HEX) + `uvm_object_utils_end + + // functions and tasks + //------------------------------------------------------------------------------ + // function name : new + // function : constructor + // invoked : be invoked when instantiates hca_mem_line + //------------------------------------------------------------------------------ + function new(string name = "hca_mem_line"); + super.new(name); + endfunction + +endclass : hca_mem_line + +`endif diff --git a/ETH-PLUS_Jingzhao/JingZhao2/verification/src/vrf_HTN/sv/common/hca_pcie_item.sv b/ETH-PLUS_Jingzhao/JingZhao2/verification/src/vrf_HTN/sv/common/hca_pcie_item.sv new file mode 100644 index 0000000000000000000000000000000000000000..1f729babf664c9a5af914ab58a3ea475f9ed9019 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/verification/src/vrf_HTN/sv/common/hca_pcie_item.sv @@ -0,0 +1,524 @@ +//CREATE INFORMATION +//----------------------------------------------------------------------------------------------- +// +// (C) COPYRIGHT 2021 BY ICT-HPC CORPORATION ALL RIGHTS RESERVED +// DATE : 2020-11-26 +// AUTHOR : mazhenlong@ncic.ac.cn +// FILENAME : hca_pcie_item.sv +// FUNCTION : This file supplies the env of verification of HCA. +// +//----------------------------------------------------------------------------------------------- + +//CHANGE HISTORY +//----------------------------------------------------------------------------------------------- +// +// AUTHOR DATE VERSION REASON +// mazhenlong 2020-11-26 v1.0 create +// mazhenlong 2021-01-14 v1.1 rewrite the class, referring +// to pg023 +// mazhenlong 2021-01-20 v1.2 rewrite members, classified +// by CQ, CC, RQ and RC +// mazhenlong 2021-03-04 v1.3 add gen_cq_desc() +// mazhenlong 2021-04-09 v1.4 add RQ +// mazhenlong 2021-04-12 v1.5 add do_compare function +// mazhenlong 2021-04-29 v1.6 extend constraint c_hcr to query_adapter, +// query_dev_lim, close_hca +// +//----------------------------------------------------------------------------------------------- + +`ifndef __HCA_PCIE_ITEM__ +`define __HCA_PCIE_ITEM__ + +typedef enum { MEM_RD = 4'b0000, + MEM_WR = 4'b0001, + IO_RD = 4'b0010, + IO_WR = 4'b0011, + MEM_FETCH_ADD = 4'b0100, + MEM_UNCON_SWAP = 4'b0101, + MEM_COMP_SWAP = 4'b0110, + LOCKED_RD = 4'b0111, + TYPE0_CONF_RD = 4'b1000, + TYPE1_CONF_RD = 4'b1001, + TYPE0_CONF_WR = 4'b1010, + TYPE1_CONF_WR = 4'b1011, + ANY = 4'b1100, + VENDOR_DEF = 4'b1101, + ATS = 4'b1110, + RESERVED = 4'b1111} e_req_type; + +// typedef enum {CQ, CC, RQ, RC, BASE_REG, RAM_DATA} e_item_type; +typedef enum {INIT, HCR, DOORBELL, DMA_RD, DMA_WR, DMA_RSP, BATCH, INTR, GLOBAL_STOP} e_item_type; + +import uvm_pkg::*; +//---------------------------------------------------------------------------- +// +// CLASS: hca_pcie_item +// +//---------------------------------------------------------------------------- +class hca_pcie_item extends uvm_sequence_item; + + rand e_item_type item_type; + bool is_cq = FALSE; + + rand int host_num = 0; + rand bit [63:0] dma_addr; + rand bit [16:0] dma_length; + rand bit [16:0] inbox_size; + rand int map_type; // 1:qp + // 2:cq + // 3:mpt + // 4:mtt + rand bit [63:0] query_qp_num; + qp_context qp_ctx; + cq_context cq_ctx; + rand bit [63:0] num_mtt; + + doorbell db; + mpt mpt_item; + mtt_unit mtt_item; + icm_base icm_base_struct; + icm_map icm_addr_map; + + // completer request + // content in desc + rand bit [`ADDR_WIDTH-1: 0] cq_addr; + rand bit [1: 0] cq_addr_type; + rand bit [2: 0] cq_attr; + rand bit [2: 0] cq_tc; + rand bit [5: 0] cq_bar_aperture; + rand bit [2: 0] cq_bar_id; + rand bit [7: 0] cq_target_function; + rand bit [7: 0] cq_tag; + rand bit [7: 0] cq_bus; + rand bit [7: 0] cq_device; + rand e_req_type cq_req_type; + rand bit [10: 0] cq_dword_count; + // not in desc + rand bit [127:0] cq_desc; + rand bit [6: 0] cq_rd_dw_size; + + // requester request + rand bit [`ADDR_WIDTH-1: 0] rq_addr; + rand bit [1: 0] rq_addr_type; + rand bit [10: 0] rq_dword_count; + rand e_req_type rq_req_type; + rand bit rq_poisoned_req; + rand bit [7: 0] rq_requester_device; + rand bit [7: 0] rq_requester_bus; + rand bit [7: 0] rq_tag; + rand bit [7: 0] rq_completer_device; + rand bit [7: 0] rq_completer_bus; + rand bit rq_requester_id_en; + rand bit [2: 0] rq_tc; + rand bit [2: 0] rq_attr; + rand bit rq_force_ecrc; + rand bit [3: 0] rq_first_be; + rand bit [3: 0] rq_last_be; + + // requester completion + rand bit [11: 0] rc_addr; + rand bit [3: 0] rc_error_code; + rand bit [14: 0] rc_byte_count; + rand bit rc_locked_read_completion; + rand bit rc_request_completed; + rand bit [10: 0] rc_dword_count; + rand bit [2: 0] rc_completion_status; + rand bit rc_poisoned_completion; + rand bit [7: 0] rc_requester_device; + rand bit [7: 0] rc_requester_bus; + rand bit [7: 0] rc_tag; + rand bit [7: 0] rc_completer_device; + rand bit [7: 0] rc_completer_bus; + rand bit [2: 0] rc_tc; + rand bit [2: 0] rc_attr; + rand bit [3: 0] rc_first_be; + rand bit [3: 0] rc_last_be; + + rand bit [95: 0] rc_desc; + + // completer completion + rand bit [2: 0] cc_attr; + rand bit [2: 0] cc_tc; + rand bit [5: 0] cc_bar_aperture; + rand bit [2: 0] cc_bar_id; + rand bit [7: 0] cc_target_function; + rand bit [7: 0] cc_tag; + rand bit [7: 0] cc_bus; + rand bit [7: 0] cc_device; + + rand bit [6: 0] lower_addr; + rand bit [`DATA_WIDTH-1 : 0] data_payload[$]; + + rand bit [63:0] hcr_in_param; + rand bit [31:0] hcr_in_modifier; + rand bit [63:0] hcr_out_param; + rand bit [15:0] hcr_token; + rand bit hcr_go; + rand bit hcr_e; + rand bit [7:0] hcr_op_modifier; + rand bit [11:0] hcr_op; + + bit [`ADDR_WIDTH-1 : 0] qpc_base; + bit [`ADDR_WIDTH-1 : 0] cqc_base; + bit [`ADDR_WIDTH-1 : 0] eqc_base; + bit [`ADDR_WIDTH-1 : 0] mpt_base; + bit [`ADDR_WIDTH-1 : 0] mtt_base; + + bit [63 : 0] receiving_clock_count; + + // bit is_init_hca_resp; + + bool ig_rq_addr; + bool ig_rq_addr_type; + bool ig_rq_dword_count; + bool ig_rq_req_type; + bool ig_rq_poisoned_req; + bool ig_rq_requester_id; + bool ig_rq_tag; + bool ig_rq_completer_id; + bool ig_rq_rqr_id_en; + bool ig_rq_tc; + bool ig_rq_attr; + bool ig_rq_force_ecrc; + + bool ig_rq; + bool ig_base_reg; + + `uvm_object_utils_begin(hca_pcie_item) + `uvm_field_enum(e_item_type, item_type, UVM_DEFAULT|UVM_HEX|UVM_NOCOMPARE|UVM_NOPRINT) + + `uvm_field_int(rq_addr, UVM_DEFAULT|UVM_HEX|UVM_NOCOMPARE|UVM_NOPRINT) + `uvm_field_int(rq_addr_type, UVM_DEFAULT|UVM_HEX|UVM_NOCOMPARE|UVM_NOPRINT) + `uvm_field_int(rq_dword_count, UVM_DEFAULT|UVM_HEX|UVM_NOCOMPARE|UVM_NOPRINT) + `uvm_field_int(rq_req_type, UVM_DEFAULT|UVM_HEX|UVM_NOCOMPARE|UVM_NOPRINT) + `uvm_field_int(rq_poisoned_req, UVM_DEFAULT|UVM_HEX|UVM_NOCOMPARE|UVM_NOPRINT) + `uvm_field_int(rq_requester_device, UVM_DEFAULT|UVM_HEX|UVM_NOCOMPARE|UVM_NOPRINT) + `uvm_field_int(rq_requester_bus, UVM_DEFAULT|UVM_HEX|UVM_NOCOMPARE|UVM_NOPRINT) + `uvm_field_int(rq_tag, UVM_DEFAULT|UVM_HEX|UVM_NOCOMPARE|UVM_NOPRINT) + `uvm_field_int(rq_completer_device, UVM_DEFAULT|UVM_HEX|UVM_NOCOMPARE|UVM_NOPRINT) + `uvm_field_int(rq_completer_bus, UVM_DEFAULT|UVM_HEX|UVM_NOCOMPARE|UVM_NOPRINT) + `uvm_field_int(rq_requester_id_en, UVM_DEFAULT|UVM_HEX|UVM_NOCOMPARE|UVM_NOPRINT) + `uvm_field_int(rq_tc, UVM_DEFAULT|UVM_HEX|UVM_NOCOMPARE|UVM_NOPRINT) + `uvm_field_int(rq_attr, UVM_DEFAULT|UVM_HEX|UVM_NOCOMPARE|UVM_NOPRINT) + `uvm_field_int(rq_force_ecrc, UVM_DEFAULT|UVM_HEX|UVM_NOCOMPARE|UVM_NOPRINT) + `uvm_field_int(rq_first_be, UVM_DEFAULT|UVM_HEX|UVM_NOCOMPARE|UVM_NOPRINT) + `uvm_field_int(rq_last_be, UVM_DEFAULT|UVM_HEX|UVM_NOCOMPARE|UVM_NOPRINT) + + `uvm_field_int(cq_addr, UVM_DEFAULT|UVM_HEX|UVM_NOCOMPARE|UVM_NOPRINT) + `uvm_field_int(cq_addr_type, UVM_DEFAULT|UVM_HEX|UVM_NOCOMPARE|UVM_NOPRINT) + `uvm_field_int(cq_attr, UVM_DEFAULT|UVM_HEX|UVM_NOCOMPARE|UVM_NOPRINT) + `uvm_field_int(cq_tc, UVM_DEFAULT|UVM_HEX|UVM_NOCOMPARE|UVM_NOPRINT) + `uvm_field_int(cq_bar_aperture, UVM_DEFAULT|UVM_HEX|UVM_NOCOMPARE|UVM_NOPRINT) + `uvm_field_int(cq_bar_id, UVM_DEFAULT|UVM_HEX|UVM_NOCOMPARE|UVM_NOPRINT) + `uvm_field_int(cq_target_function, UVM_DEFAULT|UVM_HEX|UVM_NOCOMPARE|UVM_NOPRINT) + `uvm_field_int(cq_tag, UVM_DEFAULT|UVM_HEX|UVM_NOCOMPARE|UVM_NOPRINT) + `uvm_field_int(cq_bus, UVM_DEFAULT|UVM_HEX|UVM_NOCOMPARE|UVM_NOPRINT) + `uvm_field_int(cq_device, UVM_DEFAULT|UVM_HEX|UVM_NOCOMPARE|UVM_NOPRINT) + `uvm_field_int(cq_req_type, UVM_DEFAULT|UVM_HEX|UVM_NOCOMPARE|UVM_NOPRINT) + `uvm_field_int(cq_dword_count, UVM_DEFAULT|UVM_HEX|UVM_NOCOMPARE|UVM_NOPRINT) + + `uvm_field_int(cc_attr, UVM_DEFAULT|UVM_HEX|UVM_NOCOMPARE|UVM_NOPRINT) + `uvm_field_int(cc_tc, UVM_DEFAULT|UVM_HEX|UVM_NOCOMPARE|UVM_NOPRINT) + `uvm_field_int(cc_bar_aperture, UVM_DEFAULT|UVM_HEX|UVM_NOCOMPARE|UVM_NOPRINT) + `uvm_field_int(cc_bar_id, UVM_DEFAULT|UVM_HEX|UVM_NOCOMPARE|UVM_NOPRINT) + `uvm_field_int(cc_target_function, UVM_DEFAULT|UVM_HEX|UVM_NOCOMPARE|UVM_NOPRINT) + `uvm_field_int(cc_tag, UVM_DEFAULT|UVM_HEX|UVM_NOCOMPARE|UVM_NOPRINT) + `uvm_field_int(cc_bus, UVM_DEFAULT|UVM_HEX|UVM_NOCOMPARE|UVM_NOPRINT) + `uvm_field_int(cc_device, UVM_DEFAULT|UVM_HEX|UVM_NOCOMPARE|UVM_NOPRINT) + + `uvm_field_int(hcr_in_param, UVM_DEFAULT|UVM_HEX|UVM_NOCOMPARE|UVM_NOPRINT) + `uvm_field_int(hcr_in_modifier, UVM_DEFAULT|UVM_HEX|UVM_NOCOMPARE|UVM_NOPRINT) + `uvm_field_int(hcr_out_param, UVM_DEFAULT|UVM_HEX|UVM_NOCOMPARE|UVM_NOPRINT) + `uvm_field_int(hcr_token, UVM_DEFAULT|UVM_HEX|UVM_NOCOMPARE|UVM_NOPRINT) + `uvm_field_int(hcr_go, UVM_DEFAULT|UVM_HEX|UVM_NOCOMPARE|UVM_NOPRINT) + `uvm_field_int(hcr_e, UVM_DEFAULT|UVM_HEX|UVM_NOCOMPARE|UVM_NOPRINT) + `uvm_field_int(hcr_op_modifier, UVM_DEFAULT|UVM_HEX|UVM_NOCOMPARE|UVM_NOPRINT) + `uvm_field_int(hcr_op, UVM_DEFAULT|UVM_HEX|UVM_NOCOMPARE|UVM_NOPRINT) + + `uvm_field_queue_int(data_payload, UVM_DEFAULT| UVM_NOCOMPARE|UVM_NOPRINT) + + `uvm_field_int(map_type, UVM_DEFAULT|UVM_HEX|UVM_NOCOMPARE|UVM_NOPRINT) + + `uvm_field_int(inbox_size, UVM_DEFAULT|UVM_HEX|UVM_NOCOMPARE|UVM_NOPRINT) + + `uvm_field_int(qpc_base, UVM_DEFAULT|UVM_HEX|UVM_NOCOMPARE|UVM_NOPRINT) + `uvm_field_int(cqc_base, UVM_DEFAULT|UVM_HEX|UVM_NOCOMPARE|UVM_NOPRINT) + `uvm_field_int(eqc_base, UVM_DEFAULT|UVM_HEX|UVM_NOCOMPARE|UVM_NOPRINT) + `uvm_field_int(mpt_base, UVM_DEFAULT|UVM_HEX|UVM_NOCOMPARE|UVM_NOPRINT) + `uvm_field_int(mtt_base, UVM_DEFAULT|UVM_HEX|UVM_NOCOMPARE|UVM_NOPRINT) + `uvm_field_int(num_mtt, UVM_DEFAULT|UVM_HEX|UVM_NOCOMPARE|UVM_NOPRINT) + + `uvm_field_int(receiving_clock_count, UVM_DEFAULT|UVM_HEX|UVM_NOCOMPARE|UVM_NOPRINT) + + `uvm_field_enum(bool, ig_rq_addr, UVM_DEFAULT|UVM_HEX|UVM_NOCOMPARE|UVM_NOPRINT) + `uvm_field_enum(bool, ig_rq_addr_type, UVM_DEFAULT|UVM_HEX|UVM_NOCOMPARE|UVM_NOPRINT) + `uvm_field_enum(bool, ig_rq_dword_count, UVM_DEFAULT|UVM_HEX|UVM_NOCOMPARE|UVM_NOPRINT) + `uvm_field_enum(bool, ig_rq_req_type, UVM_DEFAULT|UVM_HEX|UVM_NOCOMPARE|UVM_NOPRINT) + `uvm_field_enum(bool, ig_rq_poisoned_req, UVM_DEFAULT|UVM_HEX|UVM_NOCOMPARE|UVM_NOPRINT) + `uvm_field_enum(bool, ig_rq_requester_id, UVM_DEFAULT|UVM_HEX|UVM_NOCOMPARE|UVM_NOPRINT) + `uvm_field_enum(bool, ig_rq_tag, UVM_DEFAULT|UVM_HEX|UVM_NOCOMPARE|UVM_NOPRINT) + `uvm_field_enum(bool, ig_rq_completer_id, UVM_DEFAULT|UVM_HEX|UVM_NOCOMPARE|UVM_NOPRINT) + `uvm_field_enum(bool, ig_rq_rqr_id_en, UVM_DEFAULT|UVM_HEX|UVM_NOCOMPARE|UVM_NOPRINT) + `uvm_field_enum(bool, ig_rq_tc, UVM_DEFAULT|UVM_HEX|UVM_NOCOMPARE|UVM_NOPRINT) + `uvm_field_enum(bool, ig_rq_attr, UVM_DEFAULT|UVM_HEX|UVM_NOCOMPARE|UVM_NOPRINT) + `uvm_field_enum(bool, ig_rq_force_ecrc, UVM_DEFAULT|UVM_HEX|UVM_NOCOMPARE|UVM_NOPRINT) + `uvm_field_enum(bool, ig_rq, UVM_DEFAULT|UVM_HEX|UVM_NOCOMPARE|UVM_NOPRINT) + `uvm_field_enum(bool, ig_base_reg, UVM_DEFAULT|UVM_HEX|UVM_NOCOMPARE|UVM_NOPRINT) + `uvm_object_utils_end + + constraint c_hcr + { + hcr_go == 1; + hcr_e == 0; + hcr_token == `CMD_POLL_TOKEN; + item_type == HCR; + if (hcr_op == `CMD_INIT_HCA) + { + hcr_in_param == `INBOX_ADDR; + hcr_in_modifier == 0; + hcr_out_param == 0; + hcr_op_modifier == 0; + inbox_size == 64; + } + else if (hcr_op == `CMD_QUERY_ADAPTER) + { + hcr_in_param == 0; + hcr_in_modifier == 0; + hcr_out_param == `OUTBOX_ADDR; + hcr_op_modifier == 0; + } + else if (hcr_op == `CMD_QUERY_DEV_LIM) + { + hcr_in_param == 0; + hcr_in_modifier == 0; + hcr_out_param == `OUTBOX_ADDR; + hcr_op_modifier == 0; + } + else if (hcr_op == `CMD_CLOSE_HCA) + { + hcr_in_param == 0; + hcr_in_modifier == 0; + hcr_out_param == 0; + hcr_op_modifier == 0; + } + else if (hcr_op == `CMD_MAP_ICM) // to be completed + { + hcr_in_param == `INBOX_ADDR; + hcr_in_modifier == 1; + hcr_out_param == 0; + if (map_type == `ICM_QPC_TYP || map_type == `ICM_CQC_TYP || map_type == `ICM_EQC_TYP) + { + hcr_op_modifier == 1; + } + else if (map_type == `ICM_MPT_TYP || map_type == `ICM_MTT_TYP) + { + hcr_op_modifier == 2; + } + inbox_size == ((hcr_in_modifier >> 1) + 1) * 32; + } + else if (hcr_op == `CMD_RST2INIT_QPEE || + hcr_op == `CMD_INIT2RTR_QPEE || + hcr_op == `CMD_RTR2RTS_QPEE || + hcr_op == `CMD_RTS2RTS_QPEE || + hcr_op == `CMD_SQERR2RTS_QPEE || + hcr_op == `CMD_2ERR_QPEE || + hcr_op == `CMD_RTS2SQD_QPEE || + hcr_op == `CMD_SQD2SQD_QPEE || + hcr_op == `CMD_SQD2RTS_QPEE || + hcr_op == `CMD_INIT2INIT_QPEE ) + { + hcr_in_param == `INBOX_ADDR; + hcr_in_modifier == qp_ctx.local_qpn; + hcr_out_param == 0; + hcr_op_modifier == 0; + inbox_size == 192; + } + else if (hcr_op == `CMD_ERR2RST_QPEE) + { + hcr_in_param == 0; + hcr_in_modifier == num_mtt; + hcr_out_param == 0; + hcr_op_modifier == 3; + } + // else if (hcr_op == `CMD_UNMAP_ICM) + // { + + // } + // else if (hcr_op == `CMD_HW2SW_CQ) + // { + + // } + else if (hcr_op == `CMD_SW2HW_CQ) + { + hcr_in_param == `INBOX_ADDR; + // hcr_in_modifier == ; + hcr_out_param == 0; + hcr_op_modifier == 0; + inbox_size == 64; + } + // else if (hcr_op == `CMD_RESIZE_CQ) + // { + + // } + // else if (hcr_op == `CMD_HW2SW_MPT) + // { + + // } + else if (hcr_op == `CMD_SW2HW_MPT) + { + hcr_in_param == `INBOX_ADDR; + hcr_in_modifier == mpt_item.key; + hcr_out_param == 0; + hcr_op_modifier == 0; + inbox_size == 64; + } + else if (hcr_op == `CMD_WRITE_MTT) + { + hcr_in_param == `INBOX_ADDR; + hcr_in_modifier == num_mtt; + hcr_out_param == 0; + hcr_op_modifier == 0; + inbox_size == num_mtt * 64 + 256; + } + else if (hcr_op == `CMD_QUERY_QP) + { + hcr_in_param == 0; + hcr_out_param == `OUTBOX_ADDR; + // hcr_in_modifier == 0; do not set this + hcr_op_modifier == 0; + // inbox_size == 64; + } + } + + constraint c_cq_bar_aperture { + if (cq_bar_id == 3'd0) + cq_bar_aperture == 6'd20; + else if (cq_bar_id == 3'd2) + cq_bar_aperture == 6'd23; + } + + + //------------------------------------------------------------------------------ + // function name : new + // function : constructor + // invoked : invoked when instantiates the class + //------------------------------------------------------------------------------ + function new(string name = "hca_pcie_item"); + super.new(name); + + // ignore rq comparation + ig_rq_addr = TRUE; + ig_rq_addr_type = TRUE; + ig_rq_dword_count = TRUE; + ig_rq_req_type = TRUE; + ig_rq_poisoned_req = TRUE; + ig_rq_requester_id = TRUE; + ig_rq_tag = TRUE; + ig_rq_completer_id = TRUE; + ig_rq_rqr_id_en = TRUE; + ig_rq_tc = TRUE; + ig_rq_attr = TRUE; + ig_rq_force_ecrc = TRUE; + ig_rq = TRUE; + ig_base_reg = TRUE; + endfunction + + //------------------------------------------------------------------------------ + // task name : gen_cq_desc + // function : generate cq descriptor by related variables. + // invoked : invoked by hca_reg_driver + //------------------------------------------------------------------------------ + task gen_cq_desc(); + cq_desc[1:0] = cq_addr_type; + cq_desc[63:2] = cq_addr[63:2]; + cq_desc[74:64] = cq_dword_count; + cq_desc[78:75] = cq_req_type; + cq_desc[79] = 0; + cq_desc[87:80] = cq_device; + cq_desc[95:88] = cq_bus; + cq_desc[103:96] = cq_tag; + cq_desc[111:104] = cq_target_function; + cq_desc[114:112] = cq_bar_id; + cq_desc[120:115] = cq_bar_aperture; + cq_desc[123:121] = cq_tc; + cq_desc[126:124] = cq_attr; + cq_desc[127] = 0; + endtask: gen_cq_desc + + //------------------------------------------------------------------------------ + // task name : gen_rc_desc + // function : generate cq descriptor by related variables. + // invoked : invoked by hca_reg_driver + //------------------------------------------------------------------------------ + task gen_rc_desc(); + + endtask: gen_rc_desc + + //------------------------------------------------------------------------------ + // task name : gen_hcr + // function : generate hcr contents by related variables. + // invoked : invoked by ref model + //------------------------------------------------------------------------------ + task gen_hcr(); + + endtask: gen_hcr + + //------------------------------------------------------------------------------ + // function name : do_compare + // function : compare variables according to user set in scb. + // invoked : by scoreboard + //------------------------------------------------------------------------------ + function bit do_compare(uvm_object rhs, uvm_comparer comparer); + hca_pcie_item rhs_; + do_compare = 1; + if (rhs == null || !$cast(rhs_, rhs)) begin + return 0; + end + do_compare &= super.do_compare(rhs, comparer); + if (ig_rq == FALSE) begin + do_compare &= comparer.compare_field_int("rq_addr", rq_addr, rhs_.rq_addr, 64); // + do_compare &= comparer.compare_field_int("rq_addr_type", rq_addr_type, rhs_.rq_addr_type, 32); + // do_compare &= comparer.compare_field_int("rq_dword_count", rq_addr_type, rhs_.rq_addr_type, 32); + do_compare &= comparer.compare_field_int("rq_dword_count", rq_dword_count, rhs_.rq_dword_count, 32); + do_compare &= comparer.compare_field_int("rq_req_type", rq_req_type, rhs_.rq_req_type, 32); + while (data_payload.size() != 0) begin + int i = 0; + do_compare &= comparer.compare_field($sformatf("data_payload[%0d]", i), data_payload.pop_front(), rhs_.data_payload.pop_front(), 256); + i++; + end + // do_compare &= comparer.compare_field_int("rq_poisoned_req", rq_poisoned_req, rhs_.rq_poisoned_req, 32); + // do_compare &= comparer.compare_field_int("rq_requester_device", rq_requester_device, rhs_.rq_requester_device, 32); + // do_compare &= comparer.compare_field_int("rq_requester_bus", rq_requester_bus, rhs_.rq_requester_bus, 32); + // do_compare &= comparer.compare_field_int("rq_tag", rq_tag, rhs_.rq_tag, 32); + // do_compare &= comparer.compare_field_int("rq_completer_device", rq_completer_device, rhs_.rq_completer_device, 32); + // do_compare &= comparer.compare_field_int("rq_completer_bus", rq_completer_bus, rhs_.rq_completer_bus, 32); + // do_compare &= comparer.compare_field_int("rq_requester_id_en", rq_requester_id_en, rhs_.rq_requester_id_en, 32); + // do_compare &= comparer.compare_field_int("rq_tc", rq_tc, rhs_.rq_tc, 32); + // do_compare &= comparer.compare_field_int("rq_attr", rq_attr, rhs_.rq_attr, 32); + // do_compare &= comparer.compare_field_int("rq_force_ecrc", rq_force_ecrc, rhs_.rq_force_ecrc, 32); + end + if (ig_base_reg == FALSE) begin + // to do + do_compare &= comparer.compare_field("qpc_base", qpc_base, rhs_.qpc_base, `ADDR_WIDTH); + do_compare &= comparer.compare_field("cqc_base", cqc_base, rhs_.cqc_base, `ADDR_WIDTH); + do_compare &= comparer.compare_field("eqc_base", eqc_base, rhs_.eqc_base, `ADDR_WIDTH); + do_compare &= comparer.compare_field("mpt_base", mpt_base, rhs_.mpt_base, `ADDR_WIDTH); + do_compare &= comparer.compare_field("mtt_base", mtt_base, rhs_.mtt_base, `ADDR_WIDTH); + end + return do_compare; + endfunction: do_compare + + + // uvm field macros do not support struct, so a copy function for struct should be manually added + function copy_struct(hca_pcie_item item); + this.qp_ctx = item.qp_ctx; + this.cq_ctx = item.cq_ctx; + this.db = item.db; + this.mpt_item = item.mpt_item; + this.mtt_item = item.mtt_item; + this.icm_base_struct = item.icm_base_struct; + this.icm_addr_map = item.icm_addr_map; + endfunction: copy_struct + +endclass: hca_pcie_item +`endif \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/verification/src/vrf_HTN/sv/common/hca_queue_list.sv b/ETH-PLUS_Jingzhao/JingZhao2/verification/src/vrf_HTN/sv/common/hca_queue_list.sv new file mode 100644 index 0000000000000000000000000000000000000000..ed31f4cfd4c00bba9eb3ad324ba7403660cd3ef4 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/verification/src/vrf_HTN/sv/common/hca_queue_list.sv @@ -0,0 +1,68 @@ +//CREATE INFORMATION +//----------------------------------------------------------------------------------------------- +// +// (C) COPYRIGHT 2021 BY ICT-HPC CORPORATION ALL RIGHTS RESERVED +// DATE : 2021-09-08 +// AUTHOR : mazhenlong@ncic.ac.cn +// FILENAME : hca_queue_list.sv +// FUNCTION : . +// +//----------------------------------------------------------------------------------------------- + +//CHANGE HISTORY +//----------------------------------------------------------------------------------------------- +// +// AUTHOR DATE VERSION REASON +// mazhenlong 2020-09-08 v1.0 create +// +//----------------------------------------------------------------------------------------------- + +`ifndef __HCA_QUEUE_LIST__ +`define __HCA_QUEUE_LIST__ + +//---------------------------------------------------------------------------- +// +// CLASS: hca_queue_list +// +//---------------------------------------------------------------------------- +class hca_queue_list extends uvm_object; + + hca_queue_pair qp_list[][$]; + hca_comp_queue cq_list[][$]; + + `uvm_object_utils_begin(hca_queue_list) + `uvm_object_utils_end + + //------------------------------------------------------------------------------ + // function name : new + // function : constructor + // invoked : invoked when instantiates the class + //------------------------------------------------------------------------------ + function new(string name = "hca_queue_list"); + super.new(name); + endfunction + + function init(int host_num); + qp_list = new[host_num]; + cq_list = new[host_num]; + endfunction: init + + function hca_queue_pair get_qp(int host_id, bit [31:0] qpn); + for (int i = 0; i < qp_list[host_id].size(); i++) begin + if (qpn == qp_list[host_id][i].ctx.local_qpn) begin + return qp_list[host_id][i]; + end + end + `uvm_fatal("GET_QP_ERR", $sformatf("Get QP error! qpn: %h, host_id: %h", qpn, host_id)); + endfunction: get_qp + + function hca_comp_queue get_cq(int host_id, bit [31:0] cqn); + for (int i = 0; i < cq_list[host_id].size(); i++) begin + if (cqn == cq_list[host_id][i].ctx.cqn) begin + return cq_list[host_id][i]; + end + end + `uvm_fatal("GET_CQ_ERR", $sformatf("Get CQ error! cqn: %h", cqn)); + endfunction: get_cq +endclass: hca_queue_list +`endif \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/verification/src/vrf_HTN/sv/common/hca_queue_pair.sv b/ETH-PLUS_Jingzhao/JingZhao2/verification/src/vrf_HTN/sv/common/hca_queue_pair.sv new file mode 100644 index 0000000000000000000000000000000000000000..e41bb7a89942aeb5d0498ec3962a0206eff62460 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/verification/src/vrf_HTN/sv/common/hca_queue_pair.sv @@ -0,0 +1,757 @@ +//CREATE INFORMATION +//----------------------------------------------------------------------------------------------- +// +// (C) COPYRIGHT 2021 BY ICT-HPC CORPORATION ALL RIGHTS RESERVED +// DATE : 2021-09-01 +// AUTHOR : mazhenlong@ncic.ac.cn +// FILENAME : hca_queue_pair.sv +// FUNCTION : This file supplies the env of verification of HCA. +// +//----------------------------------------------------------------------------------------------- + +//CHANGE HISTORY +//----------------------------------------------------------------------------------------------- +// +// AUTHOR DATE VERSION REASON +// mazhenlong 2020-09-01 v1.0 create +// mazhenlong 2021-09-17 v1.1 add RQ support +// +//----------------------------------------------------------------------------------------------- + +`ifndef __HCA_QUEUE_PAIR__ +`define __HCA_QUEUE_PAIR__ + +typedef class hca_queue_list; + +//---------------------------------------------------------------------------- +// +// CLASS: hca_queue_pair +// +//---------------------------------------------------------------------------- +class hca_queue_pair extends uvm_object; + + qp_context ctx; + hca_queue_pair remote_qp; + hca_memory mem; + + int host_id; + bit [10:0] proc_id; + + bit [31:0] sq_byte_size; + bit [31:0] rq_byte_size; + + bit [15:0] sq_desc_byte_size; + bit [15:0] rq_desc_byte_size; + + bool is_connect; + + // header: producer pointer, byte + // tail: consumer pointer, byte + addr sq_header; + addr sq_tail; + addr sq_last_header; + + addr rq_header; + addr rq_tail; + addr rq_last_header; + + wqe sq[$]; + wqe rq[$]; + + `uvm_object_utils_begin(hca_queue_pair) + `uvm_object_utils_end + + + //------------------------------------------------------------------------------ + // function name : new + // function : constructor + // invoked : invoked when instantiates the class + //------------------------------------------------------------------------------ + function new(string name = "hca_queue_pair"); + super.new(name); + sq_header = 0; + sq_tail = 0; + sq_last_header = 0; + rq_header = 0; + rq_tail = 0; + rq_last_header = 0; + is_connect = FALSE; + endfunction: new + + function bit connect(hca_queue_pair qp_b); + remote_qp = qp_b; + qp_b.remote_qp = this; + this.ctx.remote_qpn = qp_b.ctx.local_qpn; + qp_b.ctx.remote_qpn = this.ctx.local_qpn; + this.ctx.rnr_nextrecvpsn = qp_b.ctx.next_send_psn; + qp_b.ctx.rnr_nextrecvpsn = this.ctx.next_send_psn; + this.is_connect = TRUE; + qp_b.is_connect = TRUE; + endfunction: connect + + //------------------------------------------------------------------------------ + // task name : put_wqe + // function : create wqes of one doorbell and deliver them to both memory + // and q_list. + // If operation type is RECEIVE, this task puts WQEs to RQ of + // the remote QP. + // invoked : by create_and_write_wqes in test_direct_param + //------------------------------------------------------------------------------ + task put_wqe( + e_op_type op_que[$], // opcode of each WQE + mpt local_mpt_que[$], // used in data_seg + mpt remote_mpt_que[$], // used in raddr_seg or check queue of RECV + addr local_addr_offset_que[$], // its length should be equal to local_mpt_que + addr remote_addr_offset_que[$], // its length should be equal to remote_mpt_que + hca_queue_list q_list, + hca_check_mem_list check_list, + int sg_num, + int sg_data_cnt + ); + addr desc_byte_len; + e_op_type op_type; + e_op_type next_op_type; + mpt local_mpt; + mpt remote_mpt; + addr local_addr_offset; + addr remote_addr_offset; + // int queue_size = 512 * 1024; + wqe_data_seg_unit data_seg_unit; + mpt local_mpt_que_check[$]; + mpt remote_mpt_que_check[$]; + addr local_addr_offset_que_check[$]; + addr remote_addr_offset_que_check[$]; + int host_id; + int remote_host_id; + bit [10:0] proc_id; + bit [10:0] remote_proc_id; + hca_queue_pair qp; + int wqe_num; + + qp = this; + host_id = this.host_id; + proc_id = this.proc_id; + remote_host_id = remote_qp.host_id; + remote_proc_id = remote_qp.proc_id; + + local_mpt_que_check = local_mpt_que; + remote_mpt_que_check = remote_mpt_que; + local_addr_offset_que_check = local_addr_offset_que; + remote_addr_offset_que_check = remote_addr_offset_que; + wqe_num = op_que.size(); + + next_op_type = op_que.pop_front(); + + if (local_mpt_que.size() != local_addr_offset_que.size()) begin + `uvm_fatal("QUEUE_ERROR", $sformatf("local_mpt_que.size != local_addr_offset_que.size!")); + end + + if (remote_mpt_que.size() != remote_addr_offset_que.size()) begin + `uvm_fatal("QUEUE_ERROR", $sformatf("remote_mpt_que.size != remote_addr_offset_que.size!")); + end + + qp.sq_last_header = qp.sq_header; + + for (int i = 0; i < wqe_num; i++) begin + wqe temp_wqe; + + op_type = next_op_type; + if (op_que.size() != 0) begin // is not the last WQE + next_op_type = op_que.pop_front(); + end + else begin + next_op_type = OP_INIT; + end + + // set WQE length + desc_byte_len = 0; + if (op_type == RECV) begin + desc_byte_len[ctx.rq_entry_sz_log] = 1'b1; + end + else begin + desc_byte_len[ctx.sq_entry_sz_log] = 1'b1; + end + + // set next seg + if (i + 1 == wqe_num) begin // is the last wqe + if (op_type == RECV) begin + temp_wqe.next_seg.next_wqe = 0; + temp_wqe.next_seg.res_0 = 1; + temp_wqe.next_seg.next_opcode = 0; + temp_wqe.next_seg.next_ee = 0; + temp_wqe.next_seg.next_dbd = 0; + temp_wqe.next_seg.next_fence = 0; + temp_wqe.next_seg.next_wqe_size = 0; + temp_wqe.next_seg.cq = 0; + temp_wqe.next_seg.evt = 0; + temp_wqe.next_seg.solicit = 0; + temp_wqe.next_seg.res_1 = 1; + temp_wqe.next_seg.imm_data = 0; + end + else begin + temp_wqe.next_seg.next_wqe = 0; + temp_wqe.next_seg.next_opcode = 0; + temp_wqe.next_seg.next_ee = 0; + temp_wqe.next_seg.next_dbd = 0; + temp_wqe.next_seg.next_fence = 0; + temp_wqe.next_seg.next_wqe_size = 0; + temp_wqe.next_seg.cq = 0; + temp_wqe.next_seg.evt = 0; + temp_wqe.next_seg.solicit = 0; + temp_wqe.next_seg.imm_data = 0; + end + end + else begin // is not the last wqe + case (next_op_type) + WRITE: begin + temp_wqe.next_seg.next_wqe = ((sq_header + desc_byte_len) % sq_byte_size) >> 4; + temp_wqe.next_seg.next_opcode = `VERBS_RDMA_WRITE; + temp_wqe.next_seg.next_wqe_size = sg_num + 2; + end + READ: begin + temp_wqe.next_seg.next_wqe = ((sq_header + desc_byte_len) % sq_byte_size) >> 4; + temp_wqe.next_seg.next_opcode = `VERBS_RDMA_READ; + temp_wqe.next_seg.next_wqe_size = sg_num + 2; + end + SEND: begin + if (qp.ctx.flags[23:16] == `HGHCA_QP_ST_UD) begin + temp_wqe.next_seg.next_wqe = ((sq_header + desc_byte_len) % sq_byte_size) >> 4; + temp_wqe.next_seg.next_opcode = `VERBS_SEND; + temp_wqe.next_seg.next_wqe_size = sg_num + 4; + end + else begin + temp_wqe.next_seg.next_wqe = ((sq_header + desc_byte_len) % sq_byte_size) >> 4; + temp_wqe.next_seg.next_opcode = `VERBS_SEND; + temp_wqe.next_seg.next_wqe_size = sg_num + 1; + end + end + RECV: begin + temp_wqe.next_seg.next_wqe = ((qp.rq_header + desc_byte_len) % rq_byte_size) >> 4; + temp_wqe.next_seg.next_wqe_size = sg_num + 2; + end + default: begin + `uvm_fatal("ILLEGAL_OPCODE", $sformatf("illegal op code in wqe! i: %d, op_que.size: %d.", i, op_que.size())); + end + endcase + end + + // set ud seg + if (qp.ctx.flags[23:16] == `HGHCA_QP_ST_UD) begin + temp_wqe.ud_seg.port = 8'b0101_0101; + temp_wqe.ud_seg.smac = 48'h0102_0304_0506; + temp_wqe.ud_seg.dmac = 48'h0708_090a_0b0c; + temp_wqe.ud_seg.sip = 32'h1234_0000; + temp_wqe.ud_seg.dip = 32'h0000_1234; + temp_wqe.ud_seg.dqpn = remote_qp.ctx.local_qpn; + temp_wqe.ud_seg.qkey = 32'h1234_5678; + end + + // set data seg + for (int data_seg_id = 0; data_seg_id < sg_num; data_seg_id++) begin + local_mpt = local_mpt_que.pop_front(); + local_addr_offset = local_addr_offset_que.pop_front(); + if (local_addr_offset > local_mpt.length) begin + `uvm_fatal("ADDR_ERROR", $sformatf("local address offset exceeds size of MPT! key: %h, offset: %h, size: %h", + local_mpt.key, local_addr_offset, local_mpt.length) + ); + end + data_seg_unit.byte_count = sg_data_cnt; + data_seg_unit.lkey = local_mpt.key; + data_seg_unit.addr = local_mpt.start + local_addr_offset; + `uvm_info("WQE_INFO", $sformatf("wqe_id: %h, data_seg: byte count: %h, lkey: %h, addr: %h, op: %h, qpn: %h, serv_typ: %h, host_id: %h", + i, data_seg_unit.byte_count, data_seg_unit.lkey, data_seg_unit.addr, op_type, ctx.local_qpn, ctx.flags[23:16], host_id), UVM_LOW + ); + temp_wqe.data_seg.push_back(data_seg_unit); + end + + // set raddr seg + case (op_type) + WRITE, + READ: begin + remote_mpt = remote_mpt_que.pop_front(); + remote_addr_offset = remote_addr_offset_que.pop_front(); + if (remote_addr_offset > remote_mpt.length) begin + `uvm_fatal("ADDR_ERROR", $sformatf("remote address offset exceeds size of MPT! key: %h, offset: %h, size: %h", + remote_mpt.key, remote_addr_offset, remote_mpt.length)); + end + temp_wqe.raddr_seg.raddr = remote_mpt.start + remote_addr_offset; + temp_wqe.raddr_seg.rkey = remote_mpt.key; + `uvm_info("WQE_INFO", $sformatf("wqe_id: %h, raddr_seg: rkey: %h, addr: %h, qpn: %h, host_id: %h", + i, temp_wqe.raddr_seg.rkey, temp_wqe.raddr_seg.raddr, ctx.local_qpn, host_id), UVM_LOW + ); + end + SEND, + RECV: begin + // No need to set raddr seg for SEND/RECV + end + default: begin + `uvm_fatal("OP_TYPE_ERR", $sformatf("Illegal op_type: %h", op_type)); + end + endcase + + // set zero seg + if (op_type == RECV) begin + temp_wqe.zero_seg.zero = 0; + end + + if (op_type == RECV) begin + qp.rq.push_back(temp_wqe); + `uvm_info("NOTICE", $sformatf("WQE pushed into rq_wqe_list! op_type: %h, raddr_seg.raddr: %h", op_type, temp_wqe.raddr_seg.raddr), UVM_LOW); + write_wqe_to_mem(qp, temp_wqe, op_type, sg_num); + end + else begin + qp.sq.push_back(temp_wqe); + `uvm_info("NOTICE", $sformatf("WQE pushed into sq_wqe_list! op_type: %h, raddr_seg.raddr: %h", op_type, temp_wqe.raddr_seg.raddr), UVM_LOW); + write_wqe_to_mem(qp, temp_wqe, op_type, sg_num); + end + + // send source address, destination address and length to scoreboard, no need for SEND + if (op_type != SEND) begin + // mpt local_mpt_que_check_copy[$]; + mpt remote_mpt_que_check_copy[$]; + // addr local_addr_offset_que_check_copy[$]; + addr remote_addr_offset_que_check_copy[$]; + for (int data_seg_id = 0; data_seg_id < sg_num; data_seg_id++) begin + // local_mpt_que_check_copy.push_back(local_mpt_que_check.pop_front()); + remote_mpt_que_check_copy.push_back(remote_mpt_que_check.pop_front()); + // local_addr_offset_que_check_copy.push_back(local_addr_offset_que_check.pop_front()); + remote_addr_offset_que_check_copy.push_back(remote_addr_offset_que_check.pop_front()); + end + send_mem_check( + host_id, + remote_host_id, + proc_id, + remote_qp.proc_id, + temp_wqe, + op_type, + // local_mpt_que_check_copy, + remote_mpt_que_check_copy, + // local_addr_offset_que_check_copy, + remote_addr_offset_que_check_copy, + check_list + ); + end + + // send cqe to scoreboard + send_ref_cqe(q_list); + + // modify qp pointer + if (op_type == RECV) begin + qp.rq_header += desc_byte_len; + end + else begin + qp.sq_header += desc_byte_len; + end + // if ((qp.sq_header - qp.sq_tail) > 2048) begin + // `uvm_fatal("QP_OVERLAY", "SQ header exceeds tail!"); + // end + // if ((qp.rq_header - qp.rq_tail) > 2048) begin + // `uvm_fatal("QP_OVERLAY", "RQ header exceeds tail!"); + // end + end + // qp.sq_last_header = qp.sq_header; + `uvm_info("NOTICE", "put_wqe finished!", UVM_HIGH); + endtask: put_wqe + + //------------------------------------------------------------------------------ + // task name : send_ref_cqe + // function : send reference CQE to scoreboard + // invoked : by put_wqe + //------------------------------------------------------------------------------ + task send_ref_cqe(hca_queue_list q_list); + // warning: need to improve + hca_comp_queue snd_cq; + hca_comp_queue rcv_cq; + cqe temp_cqe; + snd_cq = q_list.cq_list[host_id][0]; + snd_cq.put_cqe(temp_cqe); + `uvm_info("NOTICE", "send_ref_cqe finished!", UVM_LOW); + endtask: send_ref_cqe + + //----------------------------------------------------------------------------------- + // task name : send_mem_check + // function : put memory check information of every single WQE into check_list, + // which will be used by scoreboard. + // invoked : by put_wqe + //----------------------------------------------------------------------------------- + task send_mem_check( + int host_id, + int remote_host_id, + bit [10:0] proc_id, + bit [10:0] remote_proc_id, + wqe input_wqe, + e_op_type op_type, + // mpt recv_dst_mpt_que[$], + mpt recv_src_mpt_que[$], + // addr recv_dst_addr_offset_que[$], + addr recv_src_addr_offset_que[$], + hca_check_mem_list check_list + ); + check_mem_unit check_unit; + wqe_data_seg_unit temp_data_seg; + addr offset = 0; + mpt recv_dst_mpt; + mpt recv_src_mpt; + addr recv_dst_addr_offset; + addr recv_src_addr_offset; + + // if op is READ or WRITE, use WQE to check + if (op_type == READ) begin + while (input_wqe.data_seg.size() != 0) begin + temp_data_seg = input_wqe.data_seg.pop_front(); + check_unit.src_host = remote_host_id; + check_unit.dst_host = host_id; + check_unit.length = temp_data_seg.byte_count; + check_unit.src_addr = `PA(proc_id, input_wqe.raddr_seg.raddr) + offset; + check_unit.dst_addr = `PA(proc_id, temp_data_seg.addr); + `uvm_info("MEM_CHECK_NOTICE", $sformatf("send memory check unit, src_addr: %h, dst_addr: %h, length: %h, operation type: %0d", + check_unit.src_addr, check_unit.dst_addr, check_unit.length, op_type), UVM_LOW); + check_list.check_list[host_id].push_back(check_unit); + offset += temp_data_seg.byte_count; + end + end + else if (op_type == WRITE) begin + while (input_wqe.data_seg.size() != 0) begin + temp_data_seg = input_wqe.data_seg.pop_front(); + check_unit.src_host = host_id; + check_unit.dst_host = remote_host_id; + check_unit.length = temp_data_seg.byte_count; + check_unit.src_addr = `PA(proc_id, temp_data_seg.addr); + check_unit.dst_addr = `PA(proc_id, input_wqe.raddr_seg.raddr) + offset; + `uvm_info("MEM_CHECK_NOTICE", $sformatf("send memory check unit, src_addr: %h, dst_addr: %h, operation type: %0d", + check_unit.src_addr, check_unit.dst_addr, op_type), UVM_LOW); + check_list.check_list[host_id].push_back(check_unit); + offset += temp_data_seg.byte_count; + end + end + // if op is RECV, use MPT and WQE to check + else if (op_type == RECV) begin // WARNING + if (input_wqe.data_seg.size() != recv_src_mpt_que.size() || input_wqe.data_seg.size() != recv_src_addr_offset_que.size()) begin + `uvm_fatal("QUEUE_ERROR", $sformatf("queue size error! input_wqe.data_seg.size: %h, recv_src_mpt_que.size: %h, recv_src_addr_offset_que.size: %h", + input_wqe.data_seg.size(), recv_src_mpt_que.size(), recv_src_addr_offset_que.size()) + ); + end + while (input_wqe.data_seg.size() != 0) begin + temp_data_seg = input_wqe.data_seg.pop_front(); + recv_src_mpt = recv_src_mpt_que.pop_front(); + recv_src_addr_offset = recv_src_addr_offset_que.pop_front(); + check_unit.src_host = remote_host_id; + check_unit.dst_host = host_id; + check_unit.length = temp_data_seg.byte_count; + check_unit.src_addr = `PA(remote_proc_id, recv_src_mpt.start) + recv_src_addr_offset; + check_unit.dst_addr = `PA(proc_id, temp_data_seg.addr); + `uvm_info("MEM_CHECK_NOTICE", $sformatf("send memory check unit, src_addr: %h, dst_addr: %h, operation type: %0d", + check_unit.src_addr, check_unit.dst_addr, op_type), UVM_LOW); + check_list.check_list[host_id].push_back(check_unit); + offset += temp_data_seg.byte_count; + end + end + else begin + `uvm_fatal("OP_TYPE_ERR", "Illegal op_type!"); + end + endtask: send_mem_check + + //------------------------------------------------------------------------------ + // task name : write_wqe_to_mem + // function : write one wqe of an operation type into memory space of a + // given QP + // invoked : by put_wqe + //------------------------------------------------------------------------------ + task write_wqe_to_mem(hca_queue_pair qp, wqe temp_wqe, e_op_type op_type, int sg_num); // write ONE wqe to memory + // not support inline seg + addr base_paddr; + addr wqe_offset; + bit [`DATA_WIDTH - 1 : 0] raw_data; + wqe_data_seg_unit data_seg_unit; + int sg_id; + bit [10:0] proc_id; + int host_id; + bit [7 : 0] op; + bit [7 : 0] desc_size; + // int wqe_size; + hca_fifo #(.width(256)) data_fifo; + proc_id = qp.proc_id; + host_id = qp.host_id; + + data_fifo = hca_fifo#(.width(256))::type_id::create("data_fifo"); + + // set wqe_offset and base physical address + if (op_type == RECV) begin + base_paddr = `PA_QP(proc_id, qp.ctx.local_qpn) + `SQ_RQ_GAP; + wqe_offset = qp.rq_header % rq_byte_size; + end + else begin + base_paddr = `PA_QP(proc_id, qp.ctx.local_qpn); + wqe_offset = qp.sq_header % sq_byte_size; + end + + // write wqe + // WRITE/READ WQE: + // next_seg(16B) + raddr_seg(16B) + data_seg(16B x n) + if (op_type == WRITE || op_type == READ) begin + if (op_type == WRITE) begin + op = `VERBS_RDMA_WRITE; + end + else if (op_type == READ) begin + op = `VERBS_RDMA_READ; + end + desc_size = 32 + sg_num * 16; + raw_data = 0; + data_fifo.clean(); + raw_data[127:0] = { + temp_wqe.next_seg.imm_data, + {8'b0}, op, desc_size >> 4, 2'b0, temp_wqe.next_seg.cq, temp_wqe.next_seg.evt, temp_wqe.next_seg.solicit, 1'b0, + temp_wqe.next_seg.next_ee, temp_wqe.next_seg.next_dbd, temp_wqe.next_seg.next_fence, temp_wqe.next_seg.next_wqe_size, + temp_wqe.next_seg.next_wqe, 1'b0, temp_wqe.next_seg.next_opcode + }; + raw_data[255:128] = { + 32'b0, + temp_wqe.raddr_seg.rkey, + temp_wqe.raddr_seg.raddr + }; + data_fifo.push(trans2comb(raw_data)); + raw_data = 0; + sg_id = 0; + while (temp_wqe.data_seg.size() != 0) begin + data_seg_unit = temp_wqe.data_seg.pop_front(); + if (sg_id % 2 == 0) begin + raw_data = 0; + raw_data[127:0] = { + data_seg_unit.addr, + data_seg_unit.lkey, + data_seg_unit.byte_count + }; + end + else begin + raw_data[255:128] = { + data_seg_unit.addr, + data_seg_unit.lkey, + data_seg_unit.byte_count + }; + end + if (temp_wqe.data_seg.size() == 0 || sg_id % 2 == 1) begin + data_fifo.push(trans2comb(raw_data)); + end + sg_id++; + end + mem.write_block(base_paddr + wqe_offset, data_fifo, desc_size); + if (32 + sg_num * 16 > `SQ_WQE_BYTE_LEN) begin + `uvm_fatal("WQE_SZ_ERR", $sformatf("WRITE/READ WQE size error! sg_num: %0d", sg_num)); + end + end + else if (op_type == SEND) begin + op = `VERBS_SEND; + // RC/UC SEND_WQE: + // next_seg(16B) + data_seg (16B x n) + if (qp.ctx.flags[23:16] != `HGHCA_QP_ST_UD) begin // RC/UC + desc_size = 16 + sg_num * 16; + raw_data = 0; + data_fifo.clean(); + raw_data[127:0] = { + temp_wqe.next_seg.imm_data, + {8'b0}, op, desc_size >> 4, 2'b0, temp_wqe.next_seg.cq, temp_wqe.next_seg.evt, temp_wqe.next_seg.solicit, temp_wqe.next_seg.res_1, + temp_wqe.next_seg.next_ee, temp_wqe.next_seg.next_dbd, temp_wqe.next_seg.next_fence, temp_wqe.next_seg.next_wqe_size, + temp_wqe.next_seg.next_wqe, temp_wqe.next_seg.res_0, temp_wqe.next_seg.next_opcode + }; + sg_id = 0; + while (temp_wqe.data_seg.size() != 0) begin + data_seg_unit = temp_wqe.data_seg.pop_front(); + // + if (sg_id % 2 == 0) begin + raw_data[255:128] = { + data_seg_unit.addr, + data_seg_unit.lkey, + data_seg_unit.byte_count + }; + data_fifo.push(trans2comb(raw_data)); + end + else begin + raw_data = 0; + raw_data[127:0] = { + data_seg_unit.addr, + data_seg_unit.lkey, + data_seg_unit.byte_count + }; + if (temp_wqe.data_seg.size() == 0) begin + data_fifo.push(trans2comb(raw_data)); + end + end + sg_id++; + end + mem.write_block(base_paddr + wqe_offset, data_fifo, desc_size); + if (16 + sg_num * 16 > `SQ_WQE_BYTE_LEN) begin + `uvm_fatal("WQE_SZ_ERR", $sformatf("RC/UC SEND WQE size error! sg_num: %0d", sg_num)); + end + end + // UD SEND WQE: + // next_seg(16B) + ud_seg(48B) + data_seg(16B x n) + else if (qp.ctx.flags[23:16] == `HGHCA_QP_ST_UD) begin + desc_size = 64 + sg_num * 16; + raw_data = 0; + data_fifo.clean(); + raw_data[127:0] = { + temp_wqe.next_seg.imm_data, + {8'b0}, op, desc_size >> 16, 2'b0, temp_wqe.next_seg.cq, temp_wqe.next_seg.evt, temp_wqe.next_seg.solicit, temp_wqe.next_seg.res_1, + temp_wqe.next_seg.next_ee, temp_wqe.next_seg.next_dbd, temp_wqe.next_seg.next_fence, temp_wqe.next_seg.next_wqe_size, + temp_wqe.next_seg.next_wqe, temp_wqe.next_seg.res_0, temp_wqe.next_seg.next_opcode + }; + raw_data[255:128] = { + temp_wqe.ud_seg.dmac[47:16], + temp_wqe.ud_seg.smac[47:16], + temp_wqe.ud_seg.dmac[15:0], temp_wqe.ud_seg.smac[15:0], + 24'b0, temp_wqe.ud_seg.port + }; + data_fifo.push(trans2comb(raw_data)); + raw_data = { + 32'b0, + 32'b0, + temp_wqe.ud_seg.qkey, + temp_wqe.ud_seg.dqpn, + 32'b0, + 32'b0, + temp_wqe.ud_seg.dip, + temp_wqe.ud_seg.sip + }; + data_fifo.push(trans2comb(raw_data)); + sg_id = 0; + while (temp_wqe.data_seg.size() != 0) begin + data_seg_unit = temp_wqe.data_seg.pop_front(); + if (sg_id % 2 == 0) begin + raw_data = 0; + raw_data[127:0] = { + data_seg_unit.addr, + data_seg_unit.lkey, + data_seg_unit.byte_count + }; + end + else begin + raw_data[255:128] = { + data_seg_unit.addr, + data_seg_unit.lkey, + data_seg_unit.byte_count + }; + end + if (temp_wqe.data_seg.size() == 0 || sg_id % 2 == 1) begin + data_fifo.push(trans2comb(raw_data)); + end + sg_id++; + end + mem.write_block(base_paddr + wqe_offset, data_fifo, 64 + sg_num * 16); + if (64 + sg_num * 16 > `SQ_WQE_BYTE_LEN) begin + `uvm_fatal("WQE_SZ_ERR", $sformatf("UD SEND WQE size error! sg_num: %0d", sg_num)); + end + end + end + else if (op_type == RECV) begin + desc_size = 32 + sg_num * 16; + // RECV WQE: + // next_seg(16B) + data_seg(16B x n) + zero_seg(16B) + // if (qp.ctx.flags[23:16] != `HGHCA_QP_ST_UD) begin + raw_data = 0; + data_fifo.clean(); + raw_data[127:0] = { + temp_wqe.next_seg.imm_data, + {16'b0}, desc_size >> 4, 2'b0, temp_wqe.next_seg.cq, temp_wqe.next_seg.evt, temp_wqe.next_seg.solicit, temp_wqe.next_seg.res_1, + temp_wqe.next_seg.next_ee, temp_wqe.next_seg.next_dbd, temp_wqe.next_seg.next_fence, temp_wqe.next_seg.next_wqe_size, + temp_wqe.next_seg.next_wqe, temp_wqe.next_seg.res_0, temp_wqe.next_seg.next_opcode + }; + sg_id = 0; + while (temp_wqe.data_seg.size() != 0) begin + data_seg_unit = temp_wqe.data_seg.pop_front(); + if (sg_id % 2 == 0) begin + raw_data[255:128] = { + data_seg_unit.addr, + data_seg_unit.lkey, + data_seg_unit.byte_count + }; + data_fifo.push(trans2comb(raw_data)); + if (temp_wqe.data_seg.size() == 0) begin + raw_data = 0; + raw_data[127:0] = temp_wqe.zero_seg.zero; + data_fifo.push(trans2comb(raw_data)); + end + end + else begin + raw_data = 0; + raw_data[127:0] = { + data_seg_unit.addr, + data_seg_unit.lkey, + data_seg_unit.byte_count + }; + if (temp_wqe.data_seg.size() == 0) begin + raw_data[255:128] = temp_wqe.zero_seg.zero; + data_fifo.push(trans2comb(raw_data)); + end + end + sg_id++; + end + if (sg_id != sg_num) begin + `uvm_fatal("SG_NUM_ERROR", $sformatf("RECV sg_id: %0d, sg_num: %0d", sg_id, sg_num)); + end + mem.write_block(base_paddr + wqe_offset, data_fifo, desc_size); + if (32 + sg_num * 16 > `RQ_WQE_BYTE_LEN) begin + `uvm_fatal("WQE_SZ_ERR", $sformatf("RECV WQE size error! sg_num: %0d", sg_num)); + end + end + if (op_type == RECV) begin + if (wqe_offset + desc_size > rq_byte_size) begin + `uvm_fatal("QUEUE_OVERFLOW", $sformatf("RQ overflow! wqe_offset: %0d, wqe_size: %0d, rq_byte_size: %0d", + wqe_offset, desc_size, rq_byte_size)); + end + end + else begin + if (wqe_offset + desc_size > sq_byte_size) begin + `uvm_fatal("QUEUE_OVERFLOW", $sformatf("SQ overflow! wqe_offset: %0d, wqe_size: %0d, rq_byte_size: %0d", + wqe_offset, desc_size, sq_byte_size)); + end + end + `uvm_info("MEM_INFO", $sformatf("write wqe finished, host_id: %h, addr: %h, op_type: %h", qp.host_id, base_paddr + wqe_offset, op_type), UVM_LOW); + endtask: write_wqe_to_mem + + //------------------------------------------------------------------------------ + // function name : trans2comb + // function : transfer an array to an combination array which can be used + // in hca_fifo + // invoked : by user + //------------------------------------------------------------------------------ + function bit [256/`BYTE_BIT_WIDTH-1:0][`BYTE_BIT_WIDTH-1:0] trans2comb(bit [255:0] raw_data); + bit [256/`BYTE_BIT_WIDTH-1:0][`BYTE_BIT_WIDTH-1:0] result; + for (int i = 0; i < 32; i++) begin + result[i] = raw_data[i * 8 + 7 -: 8]; + end + return result; + endfunction: trans2comb + + //------------------------------------------------------------------------------ + // function name : consume_wqe + // function : update tail pointer, 0: SQ, 1: RQ + // RQ is not supported because of prefetch + // invoked : by user + //------------------------------------------------------------------------------ + function consume_wqe(bit queue); + // set WQE length + addr desc_byte_len; + desc_byte_len = 0; + if (queue == 0) begin + desc_byte_len[ctx.sq_entry_sz_log] = 1'b1; + sq_tail = sq_tail + desc_byte_len; + `uvm_info("QP_NOTICE", $sformatf("consume SQ WQE, qpn: %h, host_id: %h, sq_tail: %h, sq_header: %h, descriptor size: %h", + ctx.local_qpn, host_id, sq_tail, sq_header, desc_byte_len), UVM_LOW + ); + if (sq_tail > sq_header) begin + `uvm_fatal("QUE_ERR", $sformatf("sq_tail exceeds sq_header! qpn: %h, host_id: %h, sq_tail: %h, sq_header: %h", + ctx.local_qpn, host_id, sq_tail, sq_header) + ); + end + end + // else begin + // desc_byte_len[ctx.rq_entry_sz_log] = 1'b1; + // rq_tail = rq_tail + desc_byte_len; + // `uvm_info("QP_NOTICE", $sformatf("consume RQ WQE, qpn: %h, rq_tail: %h, rq_header: %h", ctx.local_qpn, rq_tail, rq_header), UVM_LOW); + // if (rq_tail > rq_header) begin + // `uvm_fatal("QUE_ERR", $sformatf("rq_tail exceeds rq_header! qpn: %h, rq_tail: %h, rq_header: %h", ctx.local_qpn, rq_tail, rq_header)); + // end + // end + endfunction: consume_wqe +endclass: hca_queue_pair +`endif diff --git a/ETH-PLUS_Jingzhao/JingZhao2/verification/src/vrf_HTN/sv/common/hca_virt_addr.sv b/ETH-PLUS_Jingzhao/JingZhao2/verification/src/vrf_HTN/sv/common/hca_virt_addr.sv new file mode 100644 index 0000000000000000000000000000000000000000..c05fe88b97db6aa891634835a055d0a552e0a304 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/verification/src/vrf_HTN/sv/common/hca_virt_addr.sv @@ -0,0 +1,47 @@ +//CREATE INFORMATION +//-------------------------------------------------------------------------------------- +// +// (C) COPYRIGHT 2021 BY ICT-HPC CORPORATION ALL RIGHTS RESERVED +// DATE : 2021-08-22 +// AUTHOR : mazhenlong@ncic.ac.cn +// FILENAME : hca_virt_addr.sv +// FUNCTION : +// +//-------------------------------------------------------------------------------------- + +//CHANGE HISTORY +//-------------------------------------------------------------------------------------- +// +// AUTHOR DATE VERSION REASON +// mazhenlong 2021-08-22 v1.0 create +// +//-------------------------------------------------------------------------------------- + +`ifndef __HCA_VIRT_ADDR__ +`define __HCA_VIRT_ADDR__ + +//---------------------------------------------------------------------------------------- +// +// CLASS: hca_virt_addr +// +//---------------------------------------------------------------------------------------- +class hca_virt_addr extends uvm_object; + bit [63:0] full_addr; + randc bit [31:0] page_align_addr_lo; + randc bit [31:0] page_align_addr_hi; + + `uvm_object_utils_begin(hca_virt_addr) + `uvm_object_utils_end + + constraint c_page_align + { + page_align_addr_lo[11:0] == 0; + } + + function new(string name = "hca_virt_addr"); + super.new(name); + endfunction + +endclass: hca_virt_addr + +`endif \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/verification/src/vrf_HTN/sv/hca_defines.sv b/ETH-PLUS_Jingzhao/JingZhao2/verification/src/vrf_HTN/sv/hca_defines.sv new file mode 100644 index 0000000000000000000000000000000000000000..eaa9884b446466cd5132e8c208a7c75b37cb5af2 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/verification/src/vrf_HTN/sv/hca_defines.sv @@ -0,0 +1,583 @@ +`define QUERY_QP_TEST +//////////////////////////////////////////////////////////// +// width, length and size +//////////////////////////////////////////////////////////// +`define TCQ 1 +`define DATA_WIDTH 256 +`define DMA_HEAD_WIDTH 128 +`define KEEP_WIDTH `DATA_WIDTH / 32 +`define QP_ID_WIDTH 14 +`define TLP_FMT_WIDTH 3 +`define TLP_TYPE_WIDTH 5 +`define TLP_TC_WIDTH 3 +`define QPC_SIZE 128 +`define CQC_SIZE 60 +`define EQC_SIZE 48 +`define PAGE_SIZE 4096 +`define HOST_NUM 2 +`define MEM_LINE_SIZE 256 +`define HCR_BIT_SIZE 224 +`define ADDR_WIDTH 64 +`define CQE_SIZE 32 +`define HCR_BYTE_SIZE 28 +`define DB_BYTE_SIZE 8 +`define DW_BYTE_SIZE 4 +`define DW_BIT_SIZE 32 +`define BYTE_BIT_WIDTH 8 +`define DW_ALIGNED_WIDTH 2 +`define DW_DATA_WIDTH 32 +`define TWO_DW_WIDTH (2 * `DW_DATA_WIDTH) +`define THR_DW_WIDTH (3 * `DW_DATA_WIDTH) +`define FOU_DW_WIDTH (4 * `DW_DATA_WIDTH) + +`define RQ_WQE_BYTE_LEN 128 +`define SQ_WQE_BYTE_LEN 128 + +`define QPC_MTU_256 3'h1 +`define QPC_MTU_512 3'h2 +`define QPC_MTU_1024 3'h3 +`define QPC_MTU_2048 3'h4 +`define QPC_MTU_4096 3'h5 + +/* This signal indicates the (max payload size & max read request size) +* agreed in the communication +* 3'b000 -- 128 B +* 3'b001 -- 256 B +* 3'b010 -- 512 B +* 3'b011 -- 1024B +* 3'b100 -- 2048B +* 3'b101 -- 4096B +*/ +// This field sets the maximum TLP payload size. +// As a Receiver, the logic must handle TLPs as large as the set value. +// As a Transmitter, the logic must not generate TLPs exceeding the set value. +`define MAX_PAYLOAD 3'b001 +// This field sets the maximum Read Request size for the logic as a Requester. +// The logic must not generate Read Requests with size exceeding the set value. +`define MAX_READ_REQ 3'b001 +`define MODIFY_QP_DW_CNT 41 +`define RC_DESC_DW_SIZE 3 +`define LOG_NUM_WIDTH 8 +`define DEPTH_BIT_WIDTH 40 + +`define LOG_NUM_QPS 8'h10 +`define LOG_NUM_CQS 8'h10 +`define LOG_NUM_EQS 8'h05 +`define LOG_MPT_SZ 8'h11 + +`define WQE_NEXT_SEG_DW 4 +`define WQE_DATA_SEG_DW 4 +`define WQE_RADDR_SEG_DW 4 + +`define VRF_SQ_BYTE_SIZE 4096 +`define VRF_RQ_BYTE_SIZE 4096 + +`define MPT_ITEM_SIZE 64 + +//////////////////////////////////////////////////////////// +// address +//////////////////////////////////////////////////////////// +`define HCR_BAR_ADDR `ADDR_WIDTH'h0000_0000_0000_0000 +`define DB_BAR_ADDR `ADDR_WIDTH'h0000_0000_0000_0000 +`define ETH_BAR_ADDR `ADDR_WIDTH'h0000_0000_1000_0000 + +`define INBOX_ADDR `ADDR_WIDTH'h0000_0000_1234_1000 +`define OUTBOX_ADDR `ADDR_WIDTH'h0000_0000_1234_2000 +`define DATA_RECV_BUFF_GAP `ADDR_WIDTH'h0000_0001_0000_0000 +`define SQ_RQ_GAP `ADDR_WIDTH'h0000_0000_0080_0000 + +`define CQ_BASE_VADDR `ADDR_WIDTH'h0000_0000_0010_0000 +`define DATA_BASE_VADDR `ADDR_WIDTH'h + +`define ICM_BASE `ADDR_WIDTH'h0000_1000_0000_0000 // base address of ICM space in memory + +`define MTT_OFFSET `ADDR_WIDTH'h0000_0000_0000_0000 +`define QPC_OFFSET `ADDR_WIDTH'h0000_1000_0000_0000 +`define CQC_OFFSET `ADDR_WIDTH'h0000_2000_0000_0000 +`define MPT_OFFSET `ADDR_WIDTH'h0000_3000_0000_0000 +`define EQC_OFFSET `ADDR_WIDTH'h0000_4000_0000_0000 + +`define DATA_BASE `ADDR_WIDTH'h8000_0000_0000_0000 + +`define MSIX_ITR_VEC_BASE `ADDR_WIDTH'h0000_0000_0000_5400 + +//////////////////////////////////////////////////////////// +// type +//////////////////////////////////////////////////////////// +`define ICM_QPC_TYP 1 +`define ICM_CQC_TYP 2 +`define ICM_EQC_TYP 5 +`define ICM_MPT_TYP 3 +`define ICM_MTT_TYP 4 + +//////////////////////////////////////////////////////////// +// numbers +//////////////////////////////////////////////////////////// +`define MAX_PROC_NUM 2048 + +`define INIT_HCA_INBOX_DW_CNT 16 +`define DEV_LIM_DW_CNT 16 +`define ADAPTER_DW_CNT 8 +`define QPC_DW_CNT 48 + +`define MAX_HOST_NUM 2 +`define MAX_PROC_NUM 2048 +`define MAX_QP_NUM 16384 +`define MAX_DB_NUM 30 +`define MAX_WQE_NUM 4096 +`define MAX_PAGE_NUM 1024 + +`define MTT_ICM_PAGE_LIMIT 512 +`define MPT_ICM_PAGE_LIMIT 512 +`define QPC_ICM_PAGE_LIMIT 1024 +`define CQC_ICM_PAGE_LIMIT 256 + +//////////////////////////////////////////////////////////// +// time +//////////////////////////////////////////////////////////// +`define RST_DELAY 1000 +`define AFTER_RST_DELAY 100000 +`define DL #1 +`define READ_GO_GAP 30 +// `define CFG_COMM_GAP 1000 +`define CFG_GAP 5 // time gap between master driver sends two item to DUT +`define CQE2SCB_GAP 2000 // time gap between slave monitor receives a CQE + // and sends it to scoreboard +`define VALID_GAP 64 +`define READY_GAP 64 +`define PCIE_CLK_PERIOD 10 // nanosecond +`define RDMA_CLK_PERIOD 10 // nanosecond +`define BREAKTIME 5000 +`define PCIE_LATENCY 300 // nanosecond + +//////////////////////////////////////////////////////////// +// code +//////////////////////////////////////////////////////////// +`define PCIE_MEM_RD 4'b0000 +`define PCIE_MEM_WR 4'b0001 +`define CQE_OWNER_SW 8'b0000_0000 +`define CQE_OWNER_HW 8'b1000_0000 + +//////////////////////////////////////////////////////////// +// others +//////////////////////////////////////////////////////////// +`define CMD_POLL_TOKEN 16'hffff_ffff + +`define HCR_BAR_ID 0 +`define DB_BAR_ID 2 + +// `define QPC_BASE_PATH "hca_tb_top.hca_dut.RDMA_Top.ctxmgt.ctxmdata.qv_qpc_base" +// `define CQC_BASE_PATH "hca_tb_top.hca_dut.RDMA_Top.ctxmgt.ctxmdata.qv_cqc_base" +// `define EQC_BASE_PATH "hca_tb_top.hca_dut.RDMA_Top.ctxmgt.ctxmdata.qv_eqc_base" +// `define MPT_BASE_PATH "hca_tb_top.hca_dut.RDMA_Top.VirtToPhys.tptmdata.ceu_tptm_proc.mpt_base" +// `define MTT_BASE_PATH "hca_tb_top.hca_dut.RDMA_Top.VirtToPhys.tptmdata.ceu_tptm_proc.mtt_base" + +//---------------------------{type define}begin--------------------------// +typedef bit [`ADDR_WIDTH-1 : 0] mem_addr_typ; +typedef bit [`BYTE_BIT_WIDTH-1 : 0] byte_typ; +typedef int unsigned uint; +typedef longint unsigned ulint; +typedef enum {FALSE, TRUE} bool; +typedef bit [`ADDR_WIDTH - 1 : 0] addr64_typ; +typedef bit [`ADDR_WIDTH - 1 : 0] addr; + +typedef bit [`DW_DATA_WIDTH-1:0] dw_typ; +typedef bit [`TWO_DW_WIDTH-1:0] two_dw_typ; +typedef bit [`THR_DW_WIDTH-1:0] thr_dw_typ; +typedef bit [`FOU_DW_WIDTH-1:0] fou_dw_typ; + +typedef enum {SERV_INIT, RC, UC, RD, UD} e_service_type; +typedef enum {OP_INIT, WRITE, READ, SEND, RECV} e_op_type; + +typedef bit [10:0] pid_t; + +typedef struct { + bit [7 : 0] nreq; + bit [15 : 0] sq_head; + bit f0; + bit [4 : 0] opcode; + bit [23 : 0] qp_num; + bit [7 : 0] size0; + bit [10 : 0] proc_id; + // int host_id; +} doorbell; + +typedef struct { + bit [31 : 0] opt_param_mask; + bit [31 : 0] flags; + bit [7 : 0] mtu_msgmax; + bit [7 : 0] rq_entry_sz_log; + bit [7 : 0] sq_entry_sz_log; + bit [7 : 0] rlkey_arbel_sched_queue; // no use + bit [31 : 0] usr_page; // no use + bit [31 : 0] local_qpn; + bit [31 : 0] remote_qpn; + bit [31 : 0] port_pkey; + bit [7 : 0] rnr_retry; + bit [7 : 0] g_mylmc; // no use + // bit [15 : 0] rlid; // no use + bit [7 : 0] ackto; // no use + bit [7 : 0] mgid_index; // no use + bit [7 : 0] static_rate; // no use + bit [7 : 0] hop_limit; // no use + bit [31 : 0] sl_tclass_flowlabel; // no use + bit [127 : 0] rgid; // no use + // bit [15 : 0] dlid; + // bit [15 : 0] slid; + bit [47 : 0] smac; + bit [47 : 0] dmac; + bit [31 : 0] sip; + bit [31 : 0] dip; + bit [31 : 0] pd; + bit [31 : 0] wqe_base; // no use + bit [31 : 0] wqe_lkey; // no use + bit [31 : 0] next_send_psn; + bit [31 : 0] cqn_snd; + bit [31 : 0] snd_wqe_base_l; + bit [31 : 0] snd_wqe_len; // total length of SQ in byte + // bit [31 : 0] snd_db_index; // no use + bit [31 : 0] last_acked_psn; + bit [31 : 0] ssn; // no use + bit [31 : 0] rnr_nextrecvpsn; + bit [31 : 0] ra_buff_indx; // no use + bit [31 : 0] cqn_rcv; // no use + bit [31 : 0] rcv_wqe_base_l; + bit [31 : 0] rcv_wqe_len; // total length of RQ in byte + // bit [31 : 0] rcv_db_index; // no use + bit [31 : 0] qkey; + bit [31 : 0] rmsn; // no use + bit [15 : 0] rq_wqe_counter; // no use + bit [15 : 0] sq_wqe_counter; // no use + // addr head; + // addr tail; +} qp_context; + +typedef struct { + bit [31 : 0] flags; + bit [63 : 0] start; + bit [7 : 0] logsize; // log of CQE number + bit [23 : 0] usrpage; + bit [31 : 0] comp_eqn; + bit [31 : 0] pd; + bit [31 : 0] lkey; + bit [31 : 0] cqn; +} cq_context; + +typedef struct { + // flags: // 0xf << 28: HGHCA_MPT_FLAG_SW_OWNS + // 1 << 17: HGHCA_MPT_FLAG_MIO + bit [31 : 0] flags; + bit [31 : 0] page_size; // log(actual size) - 12 + bit [31 : 0] key; // 8 bit random + 24 bit offset + bit [31 : 0] pd; + bit [63 : 0] start; // start virtual address of the memory region + bit [63 : 0] length; + bit [31 : 0] lkey; // no use + bit [31 : 0] window_count; // no use + bit [31 : 0] window_count_limit; // no use + bit [63 : 0] mtt_seg; // start mtt item index + bit [31 : 0] mtt_sz; // no use +} mpt; + +typedef struct { + bit [63 : 0] start_index; + bit [63 : 0] phys_addr[$]; +} mtt_unit; + +typedef struct { + addr index; + addr phys_addr; +} mtt; + +typedef struct { + bit [63 : 0] qpc_base; + bit [7 : 0] log_num_qps; + bit [63 : 0] cqc_base; + bit [7 : 0] log_num_cqs; + bit [63 : 0] eqc_base; + bit [7 : 0] log_num_eqs; + bit [63 : 0] mpt_base; + bit [7 : 0] log_mpt_sz; + bit [63 : 0] mtt_base; +} icm_base; + +typedef struct { + bit [63 : 0] virt[$]; + bit [63 : 0] page[$]; + bit [11 : 0] page_num; +} icm_map; + +//------------------------WQE Begin-----------------------// +typedef struct { + bit [25 : 0] next_wqe; + bit [4 : 0] next_opcode; + bit [23 : 0] next_ee; + bit next_dbd; + bit next_fence; + bit [5 : 0] next_wqe_size; // 16B + bit cq; + bit evt; + bit solicit; + bit [31 : 0] imm_data; + bit res_0; + bit res_1; + bit [27 : 0] res_2; +} wqe_next_seg; + +typedef struct { + bit [31 : 0] byte_num; + bit [7 : 0] data[$]; +} wqe_inline_seg; + +typedef struct { + bit [31 : 0] byte_count; + bit [31 : 0] lkey; + bit [63 : 0] addr; +} wqe_data_seg_unit; + +typedef struct { + bit [63 : 0] raddr; + bit [31 : 0] rkey; +} wqe_raddr_seg; + +typedef struct { + bit [127 : 0] zero; +} wqe_zero_seg; // used in RECV WQE + +typedef struct { + bit [7 : 0] port; + bit [47 : 0] smac; + bit [47 : 0] dmac; + bit [31 : 0] sip; + bit [31 : 0] dip; + bit [31 : 0] dqpn; + bit [31 : 0] qkey; +} wqe_ud_seg; + +typedef struct { + wqe_next_seg next_seg; + wqe_inline_seg inline_seg; + wqe_data_seg_unit data_seg[$]; + wqe_raddr_seg raddr_seg; + wqe_zero_seg zero_seg; + wqe_ud_seg ud_seg; +} wqe; +//------------------------WQE End-----------------------// + +// CQE segments +typedef struct { + bit [31 : 0] my_qpn; + bit [31 : 0] my_ee; + bit [31 : 0] rqpn; + bit [15 : 0] rlid; + bit [7 : 0] g_mlpath; + bit [7 : 0] sl_ipok; + bit [31 : 0] imm_etype_pkey_eec; + bit [31 : 0] byte_cnt; + bit [31 : 0] wqe; + bit [7 : 0] owner; + bit [7 : 0] is_send; + bit [7 : 0] opcode; + bit [7 : 0] vender_err; + bit [7 : 0] syndrome; + bit [15 : 0] db_cnt; +} cqe; + +typedef struct { + int src_host; + int dst_host; + addr src_addr; + addr dst_addr; + int length; +} check_mem_unit; + +//---------------------------{type define}end----------------------------// + +//---------------------------{macro function}begin-----------------------// +`define PA_DATA(PROC_ID, QPN) {5'b0, PROC_ID[10:0], 1'b1, QPN[13:0], 33'b0} +`define PA_CQ(PROC_ID, CQN) {5'b0, PROC_ID[10:0], 15'b1, CQN[12:0], 20'b0} +`define PA_QP(PROC_ID, QPN) {5'b0, PROC_ID[10:0], 10'b1, QPN[13:0], 24'b0} + +`define VA_DATA(QPN) {16'b0, 1'b1, QPN[13:0], 33'b0} +`define VA_CQ(CQN) {16'b0, 15'b1, CQN[12:0], 20'b0} +`define VA_QP(QPN) {16'b0, 10'b1, QPN[13:0], 24'b0} + +`define VA(ADDR) {16'b0, ADDR[47:0]} +`define PA(PROC_ID, ADDR) {5'b0, PROC_ID[10:0], ADDR[47:0]} +//---------------------------{macro function}end-------------------------// + + +// From Kang Ning +//------------------QP STATE BEGIN---------------------// +`define HGHCA_QP_STATE_RST 0 +`define HGHCA_QP_STATE_INIT 1 +`define HGHCA_QP_STATE_RTR 2 +`define HGHCA_QP_STATE_RTS 3 +`define HGHCA_QP_STATE_SQE 4 +`define HGHCA_QP_STATE_SQD 5 +`define HGHCA_QP_STATE_ERR 6 + +`define HGHCA_QP_ST_RC 0 +`define HGHCA_QP_ST_UC 1 +`define HGHCA_QP_ST_RD 2 +`define HGHCA_QP_ST_UD 3 + +`define IB_QP_STATE 32'h0000_0001 +`define IB_QP_CUR_STATE 32'h0000_0002 +`define IB_QP_EN_SQD_ASYNC_NOTIFY 32'h0000_0004 +`define IB_QP_ACCESS_FLAGS 32'h0000_0008 +`define IB_QP_PKEY_INDEX 32'h0000_0010 +`define IB_QP_PORT 32'h0000_0020 +`define IB_QP_QKEY 32'h0000_0040 +`define IB_QP_AV 32'h0000_0080 +`define IB_QP_PATH_MTU 32'h0000_0100 +`define IB_QP_TIMEOUT 32'h0000_0200 +`define IB_QP_RETRY_CNT 32'h0000_0400 +`define IB_QP_RNR_RETRY 32'h0000_0800 +`define IB_QP_RQ_PSN 32'h0000_1000 +`define IB_QP_MAX_QP_RD_ATOMIC 32'h0000_2000 +`define IB_QP_ALT_PATH 32'h0000_4000 +`define IB_QP_MIN_RNR_TIMER 32'h0000_8000 +`define IB_QP_SQ_PSN 32'h0001_0000 +`define IB_QP_MAX_DEST_RD_ATOMIC 32'h0002_0000 +`define IB_QP_PATH_MIG_STATE 32'h0004_0000 +`define IB_QP_CAP 32'h0008_0000 +`define IB_QP_DEST_QPN 32'h0010_0000 +//------------------QP STATE END---------------------// + +//----------------------------{CMD decode}begin--------------------------// +/* -------Write Read local(CEU) relevant CMD{begin}------- */ +// Read +`define CMD_QUERY_DEV_LIM 12'h003 // no in_param, out_param -- outbox +`define CMD_QUERY_ADAPTER 12'h006 // no in_param, out_param -- outbox + +// unrealized, belongs to MAD +`define CMD_INIT_IB 12'h009 // in_param -- inbox, no out_param, in_modifier -- port +`define CMD_CLOSE_IB 12'h00a // no in_param, no out_param, in_modifier -- port +`define CMD_SET_IB 12'h00c // in_param -- inbox, no out_param, in_modifier -- port +`define CMD_CONF_SPECIAL_QP 12'h023 +`define CMD_MAD_IFC 12'h024 +/* -------Write Read local(CEU) relevant CMD{end}------- */ + +/* -------Read Write Context Management CMD{begin}------- */ +// with req data +`define CMD_SW2HW_CQ 12'h016 // in_param -- inbox, no out_param, in_modifier -- cqn +`define CMD_RESIZE_CQ 12'h02c // in_param -- inbox, no out_param, in_modifier -- cqn +`define CMD_SW2HW_EQ 12'h013 // in_param -- inbox, no out_param, in_modifier -- eqn +`define CMD_MAP_EQ 12'h012 // in_param -- event_mask, no out_param, in_modifier -- eqn + +// with || without req data +`define CMD_MODIFY_QP + +// without req data, with resp +`define CMD_HW2SW_CQ 12'h017 // no in_param, no out_param, in_modifier -- cqn +`define CMD_HW2SW_EQ 12'h014 // no in_param, no out_param, in_modifier -- eqn +`define CMD_QUERY_QP 12'h022 // no in_param, out_param -- outbox, in_modifier -- qpn +/* -------Read Write Context Management CMD{end}------- */ + +/* -------Write Virtual to Physical CMD{begin}------- */ +// with req data +`define CMD_SW2HW_MPT 12'h00d // in_param -- inbox, no out_param, in_modifier -- mpt_index +`define CMD_WRITE_MTT 12'h011 // in_param -- inbox, no out_param, in_modifier -- mtt_num + +// without req data, without resp +`define CMD_HW2SW_MPT 12'h00f // no in_param, no out_param, in_modifier -- mpt_index +/* -------Write Virtual to Physical CMD{end}------- */ + +/* -------Write CxtMgt && Virt2Phys CMD{begin}------- */ +// with req data +`define CMD_INIT_HCA 12'h007 // in_param -- inbox, no out_param + +// without req data, without resp +`define CMD_CLOSE_HCA 12'h008 // no in_param, no out_param +/* -------Write CxtMgt && Virt2Phys CMD{end}------- */ + +/* -------Write CxtMgt || Virt2Phys{begin}------- */ +// with req data +`define CMD_MAP_ICM 12'hffa // in_param -- inbox, no out_param, in_modifier -- nent, op_modifier -- module selection +`define CMD_UNMAP_ICM 12'hff9 // in_param -- virt addr, no out_param, in_modifier -- page count, op_modifier -- module selection +/* -------Write CxtMgt || Virt2Phys{end}------- */ + +/* -------Access EQ engine{begin}------- */ +// not realized +`define CMD_NOP +/* -------Access EQ engine{end}------- */ + +/* -------MODIFY_QP -- inbox & no inbox, no outbox{begin}------- */ +`define CMD_RST2INIT_QPEE 12'h019 +`define CMD_INIT2RTR_QPEE 12'h01a +`define CMD_RTR2RTS_QPEE 12'h01b +`define CMD_RTS2RTS_QPEE 12'h01c +`define CMD_SQERR2RTS_QPEE 12'h01d +`define CMD_2ERR_QPEE 12'h01e +`define CMD_RTS2SQD_QPEE 12'h01f +`define CMD_SQD2SQD_QPEE 12'h038 +`define CMD_SQD2RTS_QPEE 12'h020 +`define CMD_ERR2RST_QPEE 12'h021 +`define CMD_INIT2INIT_QPEE 12'h02d +//----------------------------{CMD decode}end----------------------------// + +//--------------{Query device limit}begin--------------// +`define RESVED_QPS 8'h1 // +`define RESVED_CQS 8'h2 +`define RESVED_EQS 8'h3 +`define RESVED_MTTS 8'h4 +`define RESVED_PDS 8'h2 +`define RESVED_LKEYS 8'h0 +`define MAX_QP_SZ 16'd11 // pow(2, 11) wqe num in one queue +`define MAX_CQ_SZ 16'd11 + +`define MAX_QPS 8'd14 +`define MAX_CQS 8'd13 +`define MAX_EQS 8'd0 +`define MAX_MPTS 8'd14 +`define MAX_PDS 8'd12 +`define MAX_GIDS 8'd0 +`define MAX_PKEYS 8'd1 +`define MAX_MTT_SEG 8'd3 // +`define QPC_ENTRY_SZ 16'd256 +// `define CQC_ENTRY_SZ 16'd128 +`define CQC_ENTRY_SZ 16'd64 +`define EQC_ENTRY_SZ 16'd64 +`define MPT_ENTRY_SZ 16'd64 + +// beat two +`define ACK_DELAY 4'h8 +`define MAX_MTU 4'h0 +`define MAX_PORT_WIDTH 4'd1 +`define MAX_VL 4'd15 +`define NUM_PORTS 4'd1 +`define MIN_PAGE_SZ 8'h00 +`define MAX_SG 8'h10 // data seg number +`define MAX_DESC_SZ 16'h0080 // wqe size +`define MAX_SG_RQ 8'h10 +`define MAX_DESC_SZ_RQ 16'h0010 +`define MAX_ICM_SZ 64'h12345678_87650000 +//--------------{Query device limit}end--------------// + +//--------------{Doorbell Opcode}begin---------------// +`define VERBS_SEND 5'b01010 +`define VERBS_SEND_WITH_IMM 5'b01011 +`define VERBS_RDMA_WRITE 5'b01000 +`define VERBS_RDMA_WRITE_WITH_IMM 5'b01001 +`define VERBS_RDMA_READ 5'b10000 +`define VERBS_CMP_AND_SWAP 5'b10001 +`define VERBS_FETCH_AND_ADD 5'b10010 +//--------------{Doorbell Opcode}end-----------------// + +//-----------------{MPT flags}begin------------------// +`define MPT_FLAG_SW_OWNS + +//--------------{Query adapter}begin--------------// +`define BOARD_ID 64'h01234567_89abcdef +//--------------{Query adapter}end--------------// + +// `define wait_signal(chnl) \ +// while(1) begin \ +// wait (chnl); \ +// repeat(2) `TD; \ +// if(chnl) \ +// break; \ +// else \ +// @ (posedge nic_if.clk); \ +// end diff --git a/ETH-PLUS_Jingzhao/JingZhao2/verification/src/vrf_HTN/sv/hca_env.sv b/ETH-PLUS_Jingzhao/JingZhao2/verification/src/vrf_HTN/sv/hca_env.sv new file mode 100644 index 0000000000000000000000000000000000000000..20e9fbd01ede2a72a940224efc850531ef10356e --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/verification/src/vrf_HTN/sv/hca_env.sv @@ -0,0 +1,158 @@ +//CREATE INFORMATION +//-------------------------------------------------------------------------------------- +// +// (C) COPYRIGHT 2021 BY ICT-HPC CORPORATION ALL RIGHTS RESERVED +// DATE : 2021-01-13 +// AUTHOR : mazhenlong@ncic.ac.cn +// FILENAME : hca_env.sv +// FUNCTION : This file supplies the env of verification of HCA. +// +//-------------------------------------------------------------------------------------- + +//CHANGE HISTORY +//-------------------------------------------------------------------------------------- +// +// AUTHOR DATE VERSION REASON +// mazhenlong 2021-01-11 v1.0 create +// mazhenlong 2021-04-01 v1.1 change reg_agt and reg_sqr to mst +// mazhenlong 2021-04-17 v1.2 delete cfg_seq +// +//-------------------------------------------------------------------------------------- + +`ifndef __HCA_ENV__ +`define __HCA_ENV__ + +//---------------------------------------------------------------------------------------- +// +// CLASS: hca_env +// +//---------------------------------------------------------------------------------------- +class hca_env extends uvm_env; + string test_name; + int host_num = 1; + hca_vsequencer vsqr; + + hca_scoreboard scb; + + // memory model + hca_memory mem[]; + + // host model + hca_sub_env sub_env[]; + hca_master_agent mst_agt; + + hca_ref_model rm; + + `uvm_component_utils_begin(hca_env) + `uvm_component_utils_end + + //------------------------------------------------------------------------------ + // function name : new + // function : constructor + // invoked : invoked when instantiates the class + //------------------------------------------------------------------------------ + function new(string name, uvm_component parent); + super.new(name, parent); + endfunction + + //------------------------------------------------------------------------------ + // function name : build_phase + // function : build_phase in uvm library, instantiates memory, reg block, + // adapter and sub_env. + // invoked : automatically by uvm + //------------------------------------------------------------------------------ + function void build_phase(uvm_phase phase); + string inst_name; + + vsqr = hca_vsequencer::type_id::create("vsqr", this); + vsqr.host_num = this.host_num; + + sub_env = new[host_num]; + + `uvm_info("HOST_NUM_INFO", $sformatf("host_num in hca_env: %0d.", host_num), UVM_LOW); + + // instantiate memory for every sub env + mem = new[host_num]; + foreach (mem[i]) begin + mem[i] = hca_memory::type_id::create($sformatf("mem%0d", i)); + end + + // instantiate sub env + for (int i = 0; i < host_num; i++) begin + inst_name = $sformatf("sub_env[%0d]", i); + sub_env[i] = hca_sub_env::type_id::create(inst_name, this); + end + + // instantiate scoreboard + scb = hca_scoreboard::type_id::create("scb", this); + + // instantiate reference model + rm = hca_ref_model::type_id::create("rm", this); + rm.host_num = this.host_num; + + super.build_phase(phase); + endfunction: build_phase + + //------------------------------------------------------------------------------ + // function name : connect_phase + // function : connect_phase in uvm library, point sqr in sub_env to vsqr. + // invoked : automatically by uvm + //------------------------------------------------------------------------------ + function void connect_phase(uvm_phase phase); + string inst_name; + // connect vsqr to sub_env sqr + foreach (sub_env[i]) begin + vsqr.mst_sqr[i] = sub_env[i].mst_agt.mst_sqr; + vsqr.slv_sqr[i] = sub_env[i].slv_agt.slv_sqr; + end + + // connect slave and scoreboard + foreach (sub_env[i]) begin + sub_env[i].slv_agt.slv_mon.port2scb.connect(scb.duv_fifo[i].analysis_export); + end + + // connect master and reference model + foreach (sub_env[i]) begin + sub_env[i].mst_agt.mst_drv.port2rm_cfg.connect(rm.cfg_fifo[i].analysis_export); + sub_env[i].mst_agt.mst_drv.port2rm_comm.connect(rm.comm_fifo[i].analysis_export); + end + + // connect slave and rm + foreach (sub_env[i]) begin + sub_env[i].slv_agt.slv_drv.port2rm.connect(rm.cfg_resp_fifo[i].analysis_export); + end + + // connect ref model and scb + foreach (rm.port2scb[i]) begin + rm.port2scb[i].connect(scb.rm_fifo[i].analysis_export); + end + foreach (mem[i]) begin + $cast(sub_env[i].mem, this.mem[i]); + $cast(rm.mem[i], this.mem[i]); + $cast(scb.mem[i], this.mem[i]); + end + endfunction: connect_phase + + //------------------------------------------------------------------------------ + // task name : configure_phase + // function : configure_phase in uvm library. + // invoked : automatically by uvm + //------------------------------------------------------------------------------ + task configure_phase(uvm_phase phase); + if ($value$plusargs("UVM_TESTNAME=%s", test_name)) begin + if (test_name == "test_reg") begin + + end + end + endtask: configure_phase + + //------------------------------------------------------------------------------ + // task name : connect_phase + // function : main_phase in uvm library. + // invoked : automatically by uvm + //------------------------------------------------------------------------------ + task main_phase(uvm_phase phase); + + endtask: main_phase +endclass +`endif \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/verification/src/vrf_HTN/sv/hca_interface.sv b/ETH-PLUS_Jingzhao/JingZhao2/verification/src/vrf_HTN/sv/hca_interface.sv new file mode 100644 index 0000000000000000000000000000000000000000..fdb72c088455b04095e60f3eac386e62de3ec541 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/verification/src/vrf_HTN/sv/hca_interface.sv @@ -0,0 +1,194 @@ +//CREATE INFORMATION +//---------------------------------------------------------------------------- +// +// (C) COPYRIGHT 2021 BY ICT-HPC CORPORATION ALL RIGHTS RESERVED +// DATE : 2021-01-14 +// AUTHOR : mazhenlong@ncic.ac.cn +// FILENAME : hca_interface.sv +// FUNCTION : This file supplies the interface that communicates with DUT. +// +//---------------------------------------------------------------------------- + +//CHANGE HISTORY +//---------------------------------------------------------------------------- +// +// AUTHOR DATE VERSION REASON +// mazhenlong 2021-01-14 v1.0 create +// mazhenlong 2021-03-24 v1.1 add time delay between dut +// and verification +// +//---------------------------------------------------------------------------- +`timescale 1ns/100ps + +//---------------------------------------------------------------------------- +// +// INTERFACE: hca_interface +// +//---------------------------------------------------------------------------- +interface hca_interface #( + parameter C_DATA_WIDTH = 256, + parameter KEEP_WIDTH = C_DATA_WIDTH /32, + parameter DMA_HEAD_WIDTH = 128, + parameter AXIS_TUSER_WIDTH = 128, + // not visable from other module + parameter PAGE_SIZE_LOG = 12 // which means, 4K per page +); + logic veri_en; + logic global_stop; + + //----------------------------------------------------- + // Verification Side Begin + //----------------------------------------------------- + logic sys_clk; + logic pcie_clk; + logic rdma_clk; + logic user_reset; + logic user_lnk_up; + logic cmd_rst; + /* -------Requester Request{begin}------- */ + /* RQ tuser + * | 59:28 | 27:24 | 23:16 | 15 | 14:13 | 12 | 11 | 10:8 | 7:4 | 3:0 | + * | parity | seq_num | tph_st_tag | tph_indirect_tag_en | tph_type | tph_present | discontinue | addr_offset | last_be | first_be | + * | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | | + */ + logic s_axis_rq_tvalid; + logic s_axis_rq_tlast ; + logic [C_DATA_WIDTH-1:0] s_axis_rq_tdata ; + logic [59 :0] s_axis_rq_tuser ; + logic [KEEP_WIDTH-1 :0] s_axis_rq_tkeep ; + logic s_axis_rq_tready; + /* -------Requester Request{end}------- */ + + /* -------Requester Completion{begin}------- */ + /* RC tuser + * | 74:43 | 42 | 41:38 | 37:34 | 33 | 32 | 31:0 | + * | parity | discontinue | is_eof_1 | is_eof_0 | is_sof_1 | is_sof_0 | byte_en | + * | | ignore | ignore | ignore | ignore | ignore | | + */ + logic m_axis_rc_tvalid; + logic m_axis_rc_tlast ; + logic [C_DATA_WIDTH-1:0] m_axis_rc_tdata ; + logic [74 :0] m_axis_rc_tuser ; + logic [KEEP_WIDTH-1 :0] m_axis_rc_tkeep ; + logic m_axis_rc_tready; + /* -------Requester Completion{end}------- */ + + /* -------Configuration Status Interface{begin}------- */ + logic [ 2:0] max_pyld_sz ;//useful + logic [ 2:0] max_rd_req_sz;//useful + /* -------Configuration Status Interface{end}------- */ + + /* -------Completer Request{begin}------- */ + /* CQ tuser + * | 84:53 | 52:45 | 44:43 | 42 | 41 | 40 | 39:8 | 7:4 | 3:0 | + * | parity | tph_st_tag | tph_type | tph_present | discontinue | sop | byte_en | last_be | first_be | + * | 0 | 0 | 0 | | | | ignore | | | + */ + logic [C_DATA_WIDTH-1:0] m_axis_cq_tdata; + logic [84 :0] m_axis_cq_tuser; + logic m_axis_cq_tlast; + logic [KEEP_WIDTH-1 :0] m_axis_cq_tkeep; + logic m_axis_cq_tvalid; + logic m_axis_cq_tready; + /* -------Completer Request{end}------- */ + + /* -------Completer Completion{begin}------- */ + /* CC tuser + * | 32:1 | 0 | + * | parity | discontinue | + * | ignore | ignore | + */ + logic [C_DATA_WIDTH-1:0] s_axis_cc_tdata; + logic [32 :0] s_axis_cc_tuser; + logic s_axis_cc_tlast; + logic [KEEP_WIDTH-1 :0] s_axis_cc_tkeep; + logic s_axis_cc_tvalid; + logic s_axis_cc_tready; + /* -------Completer Completion{end}------- */ + /////////////////////////////////////////////////////// + // Verification Side End + /////////////////////////////////////////////////////// + + /////////////////////////////////////////////////////// + // DUV Side Begin + /////////////////////////////////////////////////////// + logic s_axis_rq_tvalid_dut; + logic s_axis_rq_tlast_dut; + logic [C_DATA_WIDTH-1:0] s_axis_rq_tdata_dut; + logic [59 :0] s_axis_rq_tuser_dut; + logic [KEEP_WIDTH-1 :0] s_axis_rq_tkeep_dut; + logic s_axis_rq_tready_dut; + + logic m_axis_rc_tvalid_dut; + logic m_axis_rc_tlast_dut; + logic [C_DATA_WIDTH-1:0] m_axis_rc_tdata_dut; + logic [74 :0] m_axis_rc_tuser_dut; + logic [KEEP_WIDTH-1 :0] m_axis_rc_tkeep_dut; + logic m_axis_rc_tready_dut; + + logic [C_DATA_WIDTH-1:0] m_axis_cq_tdata_dut; + logic [84 :0] m_axis_cq_tuser_dut; + logic m_axis_cq_tlast_dut; + logic [KEEP_WIDTH-1 :0] m_axis_cq_tkeep_dut; + logic m_axis_cq_tvalid_dut; + logic m_axis_cq_tready_dut; + + logic [C_DATA_WIDTH-1:0] s_axis_cc_tdata_dut; + logic [32 :0] s_axis_cc_tuser_dut; + logic s_axis_cc_tlast_dut; + logic [KEEP_WIDTH-1 :0] s_axis_cc_tkeep_dut; + logic s_axis_cc_tvalid_dut; + logic s_axis_cc_tready_dut; + /////////////////////////////////////////////////////// + // DUV Side End + /////////////////////////////////////////////////////// + + //----------------------------------------------------------------------------------------------------------------// + // Configuration (CFG) Interface // + //----------------------------------------------------------------------------------------------------------------// + logic [2:0] cfg_max_payload; + logic [2:0] cfg_max_read_req; + + logic [63:0] clock_count; + + initial begin + $printtimescale; + end + + // add a time delay from verification to DUT + always @(*) begin + s_axis_rq_tready_dut <= `DL s_axis_rq_tready; + + m_axis_rc_tvalid_dut <= `DL m_axis_rc_tvalid; + m_axis_rc_tlast_dut <= `DL m_axis_rc_tlast; + m_axis_rc_tdata_dut <= `DL m_axis_rc_tdata; + m_axis_rc_tuser_dut <= `DL m_axis_rc_tuser; + m_axis_rc_tkeep_dut <= `DL m_axis_rc_tkeep; + + m_axis_cq_tdata_dut <= `DL m_axis_cq_tdata; + m_axis_cq_tuser_dut <= `DL m_axis_cq_tuser; + m_axis_cq_tlast_dut <= `DL m_axis_cq_tlast; + m_axis_cq_tkeep_dut <= `DL m_axis_cq_tkeep; + m_axis_cq_tvalid_dut <= `DL m_axis_cq_tvalid; + + s_axis_cc_tready_dut <= `DL s_axis_cc_tready; + end + + always @(*) begin + s_axis_rq_tvalid <= s_axis_rq_tvalid_dut; + s_axis_rq_tlast <= s_axis_rq_tlast_dut; + s_axis_rq_tdata <= s_axis_rq_tdata_dut; + s_axis_rq_tuser <= s_axis_rq_tuser_dut; + s_axis_rq_tkeep <= s_axis_rq_tkeep_dut; + + m_axis_rc_tready <= m_axis_rc_tready_dut; + + m_axis_cq_tready <= m_axis_cq_tready_dut; + + s_axis_cc_tdata <= s_axis_cc_tdata_dut; + s_axis_cc_tuser <= s_axis_cc_tuser_dut; + s_axis_cc_tlast <= s_axis_cc_tlast_dut; + s_axis_cc_tkeep <= s_axis_cc_tkeep_dut; + s_axis_cc_tvalid <= s_axis_cc_tvalid_dut; + end +endinterface: hca_interface \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/verification/src/vrf_HTN/sv/hca_ref_model.sv b/ETH-PLUS_Jingzhao/JingZhao2/verification/src/vrf_HTN/sv/hca_ref_model.sv new file mode 100644 index 0000000000000000000000000000000000000000..acb2d584bfd954074c9413bd0dca1612bf1a5dbf --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/verification/src/vrf_HTN/sv/hca_ref_model.sv @@ -0,0 +1,1202 @@ +//CREATE INFORMATION +//-------------------------------------------------------------------------------------- +// +// (C) COPYRIGHT 2021 BY ICT-HPC CORPORATION ALL RIGHTS RESERVED +// DATE : 2021-04-09 +// AUTHOR : mazhenlong@ncic.ac.cn +// FILENAME : hca_ref_model.sv +// FUNCTION : This file supplies the reference model of DUV. +// +//-------------------------------------------------------------------------------------- + +//CHANGE HISTORY +//-------------------------------------------------------------------------------------- +// +// AUTHOR DATE VERSION REASON +// mazhenlong 2021-04-09 v1.0 create +// mazhenlong 2021-09-17 v1.1 modify format of QP context in QUERY_QP +// +//-------------------------------------------------------------------------------------- + +`ifndef __HCA_REF_MODEL__ +`define __HCA_REF_MODEL__ + +//---------------------------------------------------------------------------------------- +// +// CLASS: hca_ref_model +// +//---------------------------------------------------------------------------------------- +class hca_ref_model extends uvm_component; + + uvm_tlm_analysis_fifo #(hca_pcie_item, hca_ref_model) cfg_fifo[]; // from master driver + hca_pcie_item cfg_fifo_item[]; + uvm_analysis_port #(hca_pcie_item) port2scb[]; + + uvm_tlm_analysis_fifo #(hca_pcie_item, hca_ref_model) cfg_resp_fifo[]; // from slave driver + hca_pcie_item cfg_resp_fifo_item[]; + + uvm_tlm_analysis_fifo #(hca_pcie_item, hca_ref_model) comm_fifo[]; // from slave driver + hca_pcie_item comm_fifo_item[]; + + hca_memory mem[]; + int host_num = 1; + hca_queue_list q_list; + hca_icm_vaddr icm_vaddr; + hca_mem_info mem_info; + + + bit [`ADDR_WIDTH - 1 : 0] qpc_virt_addr[][$]; + bit [`ADDR_WIDTH - 1 : 0] cqc_virt_addr[][$]; + bit [`ADDR_WIDTH - 1 : 0] eqc_virt_addr[][$]; + bit [`ADDR_WIDTH - 1 : 0] mpt_virt_addr[][$]; + bit [`ADDR_WIDTH - 1 : 0] mtt_virt_addr[][$]; + + mpt mpt_item[][$]; + + bit [`ADDR_WIDTH - 1 : 0] mtt_item_index[][$]; // icm virtual address of mtt item + bit [`ADDR_WIDTH - 1 : 0] data_phys_addr[][$]; + + mtt mem_table[][$]; + + icm_base icm_base_addr[]; + qp_context qpc[][$]; + cq_context cqc[][$]; + + int max_payload_size; + int max_read_req_size; + + `uvm_component_utils_begin(hca_ref_model) + `uvm_component_utils_end + + //------------------------------------------------------------------------------ + // function name : new + // function : constructor + // invoked : be invoked when instantiates hca_ref_model + //------------------------------------------------------------------------------ + function new(string name, uvm_component parent); + super.new(name, parent); + endfunction + + //------------------------------------------------------------------------------ + // function name : build_phase + // function : build phase in uvm library, instantiates variables + // invoked : be invoked by uvm automaticly + //------------------------------------------------------------------------------ + function void build_phase(uvm_phase phase); + + string array_element; + super.build_phase(phase); + + cfg_fifo = new[host_num]; + cfg_fifo_item = new[host_num]; + + cfg_resp_fifo = new[host_num]; + cfg_resp_fifo_item = new[host_num]; + + comm_fifo = new[host_num]; + comm_fifo_item = new[host_num]; + + port2scb = new[host_num]; + + icm_base_addr = new[host_num]; + qpc_virt_addr = new[host_num]; + cqc_virt_addr = new[host_num]; + eqc_virt_addr = new[host_num]; + mpt_virt_addr = new[host_num]; + mtt_virt_addr = new[host_num]; + + data_phys_addr = new[host_num]; + qpc = new[host_num]; + cqc = new[host_num]; + mtt_item_index = new[host_num]; + mpt_item = new[host_num]; + + mem = new[host_num]; + mem_table = new[host_num]; + + for (int i = 0; i < host_num; i++) begin + $sformat(array_element, "cfg_fifo[%0d]", i); + cfg_fifo[i] = new(array_element, this); + end + + for (int i = 0; i < host_num; i++) begin + $sformat(array_element, "cfg_resp_fifo[%0d]", i); + cfg_resp_fifo[i] = new(array_element, this); + end + + for (int i = 0; i < host_num; i++) begin + $sformat(array_element, "comm_fifo[%0d]", i); + comm_fifo[i] = new(array_element, this); + end + + for (int i = 0; i < host_num; i++) begin + $sformat(array_element, "port2scb[%0d]", i); + port2scb[i] = new(array_element, this); + end + + if (!uvm_config_db#(hca_queue_list)::get(this, "", "q_list", q_list)) begin + `uvm_fatal("NOQLIST", {"q_list must be set for: ",get_full_name(),".q_list"}); + end + if (!uvm_config_db#(hca_icm_vaddr)::get(this, "", "icm_vaddr", icm_vaddr)) begin + `uvm_fatal("NOQLIST", {"icm vaddr must be set for: ",get_full_name(),".icm_vaddr"}); + end + if (!uvm_config_db#(hca_mem_info)::get(this, "", "mem_info", mem_info)) begin + `uvm_fatal("NOQLIST", {"mem info must be set for: ",get_full_name(),".mem_info"}); + end + case(`MAX_PAYLOAD) + 3'b000: begin + max_payload_size = 128; + end + 3'b010: begin + max_payload_size = 256; + end + 3'b011: begin + max_payload_size = 512; + end + 3'b100: begin + max_payload_size = 1024; + end + 3'b101: begin + max_payload_size = 4096; + end + endcase + + case(`MAX_READ_REQ) + 3'b000: begin + max_read_req_size = 128; + end + 3'b010: begin + max_read_req_size = 256; + end + 3'b011: begin + max_read_req_size = 512; + end + 3'b100: begin + max_read_req_size = 1024; + end + 3'b101: begin + max_read_req_size = 4096; + end + endcase + + endfunction: build_phase + + function void connect_phase(uvm_phase phase); + super.connect_phase(phase); + endfunction: connect_phase + + //------------------------------------------------------------------------------ + // task name : run_phase + // function : run phase in uvm library, sends the pcie items to scoreboard + // invoked : be invoked by uvm automaticly + //------------------------------------------------------------------------------ + task run_phase(uvm_phase phase); + super.run_phase(phase); + `uvm_info("NOTICE", "ref model run_phase begin!", UVM_LOW); + // forever begin //wrong! + for (int i = 0; i < host_num; i++) begin + fork + automatic int j = i; + while (1) begin + `uvm_info("NOTICE", "cfg_fifo_item ready to get in ref model!", UVM_LOW); + cfg_fifo[j].get(cfg_fifo_item[j]); + `uvm_info("NOTICE", "cfg_fifo_item get in ref model!", UVM_LOW); + if (cfg_fifo_item[j].item_type == GLOBAL_STOP) begin + `uvm_info("NOTICE", "global stop cfg_fifo_item get in ref model!", UVM_LOW); + break; + end + process_cfg_item(cfg_fifo_item[j], j); + // `uvm_info("NOTICE", "process cfg item finished in ref model!", UVM_LOW); + listen_inbox(cfg_fifo_item[j], j); + end + while (1) begin + comm_fifo[j].get(comm_fifo_item[j]); + `uvm_info("NOTICE", "comm_fifo_item get in ref model!", UVM_LOW); + if (comm_fifo_item[j].item_type == GLOBAL_STOP) begin + `uvm_info("NOTICE", "global stop comm_fifo_item get in ref model!", UVM_LOW); + break; + end + // process_db(comm_fifo_item[j].db.proc_id, j, comm_fifo_item[j].db); + end + join_none + end + wait fork; + `uvm_info("NOTICE", "ref model run_phase end!", UVM_LOW); + // end + endtask: run_phase + + //------------------------------------------------------------------------------ + // task name : process_cfg_item + // function : process config item received and send dma requests to scoreboard. + // invoked : by run_phase() + //------------------------------------------------------------------------------ + task process_cfg_item(hca_pcie_item cfg_item, int host_id); + hca_pcie_item exp_item; + bit [`DATA_WIDTH-1 : 0] temp_data; + case (cfg_item.hcr_op) + `CMD_INIT_HCA: begin + icm_base_addr[host_id] = cfg_item.icm_base_struct; + send_read_mbx_req(host_id, `INIT_HCA_INBOX_DW_CNT, cfg_item.rq_tag); + `uvm_info("NOTICE", "init hca finished in ref model", UVM_LOW); + end + `CMD_QUERY_DEV_LIM: begin + exp_item = hca_pcie_item::type_id::create("query_dev_lim_item"); + exp_item.rq_addr = `OUTBOX_ADDR; + exp_item.rq_addr_type = 0; + exp_item.rq_dword_count = `DEV_LIM_DW_CNT; + exp_item.rq_req_type = MEM_WR; + exp_item.rq_poisoned_req = 0; + exp_item.rq_requester_device = 0; // ? + exp_item.rq_requester_bus = 0; + exp_item.rq_tag = cfg_item.rq_tag; + exp_item.rq_completer_device = 0; + exp_item.rq_completer_bus = 0; + exp_item.rq_requester_id_en = 0; + exp_item.rq_tc = 0; + exp_item.rq_attr = 0; + exp_item.rq_force_ecrc = 0; + temp_data = { + `RESVED_QPS, `RESVED_CQS, `RESVED_EQS, `RESVED_MTTS, + 8'd0, `RESVED_PDS, 8'd0, `RESVED_LKEYS, + `MAX_QP_SZ, `MAX_CQ_SZ, + `MAX_QPS, `MAX_CQS, `MAX_EQS, `MAX_MPTS, + `MAX_PDS, 8'd0, `MAX_GIDS, `MAX_PKEYS, + 8'd0, `MAX_MTT_SEG, 16'd0, + `QPC_ENTRY_SZ, `CQC_ENTRY_SZ, + `EQC_ENTRY_SZ, `MPT_ENTRY_SZ + }; + exp_item.data_payload.push_back(big_endian_trans(temp_data)); + temp_data = { + 4'd0, `ACK_DELAY, `MAX_MTU, `MAX_PORT_WIDTH, 8'd0, `MAX_VL, `NUM_PORTS, + 8'd0, `MIN_PAGE_SZ, 16'd0, + 8'd0, `MAX_SG, `MAX_DESC_SZ, + 8'd0, `MAX_SG_RQ, `MAX_DESC_SZ_RQ, + `MAX_ICM_SZ, + 32'd0, + 32'd0 + }; + exp_item.data_payload.push_back(big_endian_trans(temp_data)); + port2scb[host_id].write(exp_item); + `uvm_info("NOTICE", "query dev lim finished in ref model", UVM_LOW); + end + `CMD_QUERY_ADAPTER: begin + exp_item = hca_pcie_item::type_id::create("query_adapter_item"); + exp_item.rq_addr = `OUTBOX_ADDR; + exp_item.rq_addr_type = 0; + exp_item.rq_dword_count = `ADAPTER_DW_CNT; + exp_item.rq_req_type = MEM_WR; + exp_item.rq_poisoned_req = 0; + exp_item.rq_requester_device = 0; // ? + exp_item.rq_requester_bus = 0; + exp_item.rq_tag = cfg_item.rq_tag; + exp_item.rq_completer_device = 0; + exp_item.rq_completer_bus = 0; + exp_item.rq_requester_id_en = 0; + exp_item.rq_tc = 0; + exp_item.rq_attr = 0; + exp_item.rq_force_ecrc = 0; + temp_data = { + 32'd0, + 32'd0, + 32'd0, + 32'd0, + 32'd0, + 32'd0, + `BOARD_ID + }; + exp_item.data_payload.push_back(big_endian_trans(temp_data)); + port2scb[host_id].write(exp_item); + `uvm_info("NOTICE", "query adapter finished in ref model", UVM_LOW); + end + `CMD_MAP_ICM: begin // check and modify + if (cfg_item.icm_addr_map.virt.size == 0) begin + `uvm_fatal("EMPTY_MAP_ICM", "cfg_item.icm_addr_map.virt is empty!"); + end + // currently not support unmap_icm, so virtual address can be simply pushed + if (cfg_item.map_type == `ICM_QPC_TYP) begin + for (int i = 0; i < cfg_item.icm_addr_map.page_num; i++) begin + qpc_virt_addr[host_id].push_back(cfg_item.icm_addr_map.virt.pop_front()); + end + end + else if (cfg_item.map_type == `ICM_CQC_TYP) begin + for (int i = 0; i < cfg_item.icm_addr_map.page_num; i++) begin + cqc_virt_addr[host_id].push_back(cfg_item.icm_addr_map.virt.pop_front()); + end + end + else if (cfg_item.map_type == `ICM_MPT_TYP) begin + for (int i = 0; i < cfg_item.icm_addr_map.page_num; i++) begin + mpt_virt_addr[host_id].push_back(cfg_item.icm_addr_map.virt.pop_front()); + end + end + else if (cfg_item.map_type == `ICM_MTT_TYP) begin + for (int i = 0; i < cfg_item.icm_addr_map.page_num; i++) begin + mtt_virt_addr[host_id].push_back(cfg_item.icm_addr_map.virt.pop_front()); + end + end + else if (cfg_item.map_type == `ICM_EQC_TYP) begin + for (int i = 0; i `MAX_HOST_NUM) begin + `uvm_fatal("PARAM_ERROR", "host num maximum exceeded!"); + end + if (!$value$plusargs("DB_NUM=%d", db_num)) begin + `uvm_fatal("PARAM_ERROR", "doorbell num not get!"); + end + if (db_num > `MAX_DB_NUM) begin + `uvm_fatal("PARAM_ERROR", "doorbell num maximum exceeded!"); + end + endfunction: new + + //------------------------------------------------------------------------------ + // function name : build_phase + // function : build phase in uvm library, instantiates the two imps + // invoked : be invoked by uvm automaticly + //------------------------------------------------------------------------------ + function void build_phase(uvm_phase phase); + string array_element; + + super.build_phase(phase); + + // instantiate duv_fifo + duv_fifo = new[host_num]; + for (int i = 0; i < host_num; i++) begin + $sformat(array_element, "duv_fifo[%0d]", i); + duv_fifo[i] = new(array_element, this); + end + + // instantiate duv_fifo_item + duv_fifo_item = new[host_num]; + for (int i = 0; i < host_num; i++) begin + $sformat(array_element, "duv_fifo_item[%0d]", i); + duv_fifo_item[i] = hca_pcie_item::type_id::create(array_element, this); + end + + // instantiate rm_fifo + rm_fifo = new[host_num]; + for (int i = 0; i < host_num; i++) begin + $sformat(array_element, "rm_fifo[%0d]", i); + rm_fifo[i] = new(array_element, this); + end + + // instantiate rm_fifo_item + rm_fifo_item = new[host_num]; + for (int i = 0; i < host_num; i++) begin + $sformat(array_element, "rm_fifo_item[%0d]", i); + rm_fifo_item[i] = hca_pcie_item::type_id::create(array_element, this); + end + + mem = new[host_num]; + + if (!uvm_config_db#(hca_queue_list)::get(this, "", "q_list", q_list)) begin + `uvm_fatal("NOQLIST", {"queue list must be set for: ",get_full_name(),".q_list"}); + end + + if (!uvm_config_db#(hca_check_mem_list)::get(this, "", "check_list", check_mem_list)) begin + `uvm_fatal("NOQLIST", {"check list must be set for: ",get_full_name(),".check_mem_list"}); + end + + if(!uvm_config_db#(mailbox)::get(null, get_full_name(), "glb_stop_mbx", glb_stop_mbx)) begin + `uvm_fatal("NO_MBX", "mailbox not get in scoreboard!"); + end + + // src_data_fifo = hca_fifo#(.width(256))::type_id::create("src_data_fifo"); + // dst_data_fifo = hca_fifo#(.width(256))::type_id::create("dst_data_fifo"); + + // instantiate comparer + item_comparer = new(); + + stall_flag = new[host_num]; + for (int i = 0; i < host_num; i++) begin + stall_flag[i] = 0; + end + endfunction: build_phase + + //------------------------------------------------------------------------------ + // task name : run_phase + // function : run phase in uvm library + // invoked : be invoked by uvm automaticly + //------------------------------------------------------------------------------ + virtual task run_phase(uvm_phase phase); + bit check_rm_duv_result = 0; + phase.raise_objection(this); + super.run_phase(phase); + for (int db_id = 0; db_id < db_num; db_id++) begin + for (int i = 0; i < host_num; i++) begin + fork + automatic int j = i; + begin + `uvm_info("NOTICE", "main part of run_phase in scb begin!", UVM_LOW); + while (1) begin + duv_fifo[j].get(duv_fifo_item[j]); + `uvm_info("SCB_NOTICE", $sformatf("Item got by scb! host_id: %h", j), UVM_LOW); + + // If SCB receives a INTR when reference CQE queue is not empty, fail + if (duv_fifo_item[j].item_type == INTR) begin + `uvm_info("SCB_NOTICE", $sformatf("INTR got by scb! host_id: %h", j), UVM_LOW); + stall_flag[j] = 1; + if (q_list.cq_list[j][0].cqe_list.size() != 0) begin + if (check_stall() == 1) begin + `uvm_fatal("DEAD", "Heart stopped!"); + end + else begin + `uvm_info("SCB_NOTICE", $sformatf("cqe_list not clear, stall checking passed! host_id: %h", j), UVM_LOW); + continue; + end + end + else begin + `uvm_info("SCB_NOTICE", $sformatf("cqe_list clear! host_id: %h", j), UVM_LOW); + break; + end + end + stall_flag[j] = 0; + `uvm_info("SCB_NOTICE", $sformatf("CQE got by scb! host_id: %h", j), UVM_LOW); + check_cqe(duv_fifo_item[j], j); + q_list.cq_list[j][0].cqe_list.pop_front(); + // `uvm_info("CQE_NOTICE", $sformatf("ref CQE got by scb! host_id: %h", j), UVM_LOW); + `uvm_info("CQE_NOTICE", $sformatf("ref cqe remaining: %0d! host_id: %h", q_list.cq_list[j][0].cqe_list.size(), j), UVM_LOW); + end + end + join_none + end + wait fork; + set_global_stop(); + judge(); + for (int i = 0; i < host_num; i++) begin + duv_fifo[i].flush(); + stall_flag[i] = 0; + end + `uvm_info("GLB_STOP_INFO", $sformatf("batch finished! db_id: %h", db_id), UVM_LOW); + end + `uvm_info("GLB_STOP_INFO", $sformatf("verification finished!"), UVM_LOW); + // end_time = get_sys_time(); + phase.drop_objection(this); + endtask: run_phase + + function void pre_abort(); + `uvm_info("NOTICE", "SOCREBOARD!!", UVM_LOW); + super.pre_abort; + endfunction: pre_abort + + //------------------------------------------------------------------------------ + // task name : check_rm_duv + // function : check pcie items fro DUV and ref model + // invoked : by run_phase + //------------------------------------------------------------------------------ + task check_rm_duv(int id); + bool check_result; + check_result = rm_fifo_item[id].compare(duv_fifo_item[id], item_comparer); + if (check_result == FALSE) begin + `uvm_fatal(get_type_name(), $sformatf("Check in error in PORT %0d!!!\n rm_fifo_item.rq_addr: %h, duv_fifo_item.rq_addr: %h", + id, rm_fifo_item[id].rq_addr, duv_fifo_item[id].rq_addr)); + end + else begin + `uvm_info("CHECK_INFO", "DUV RM match!", UVM_LOW); + end + endtask: check_rm_duv + + task judge(); + for (int i = 0; i < host_num; i++) begin + int total_data_amount = 0; + while (check_mem_list.check_list[i].size() != 0) begin + check_mem_unit check_unit; + check_unit = check_mem_list.check_list[i].pop_front(); + if (check_mem(check_unit.src_host, check_unit.src_addr, check_unit.dst_host, check_unit.dst_addr, check_unit.length) == 0) begin + `uvm_fatal("CHECK_MEM_ERROR", $sformatf("source: %h, destination: %h, length: %d", check_unit.src_addr, check_unit.dst_addr, check_unit.length)); + end + else begin + total_data_amount += check_unit.length; + end + end + `uvm_info("CHECK_INFO", $sformatf("check complete, host[%0d] data count: %0d", i, total_data_amount), UVM_LOW); + end + endtask: judge + + function int check_stall(); + // If all hosts receive INTR, the system is down + for (int i = 0; i < host_num; i++) begin + if (stall_flag[i] == 0) begin + return 0; + end + end + return 1; + endfunction: check_stall + + function bit check_mem(int src_host_id, addr src_addr, int dst_host_id, addr dst_addr, int length); + bit [255:0] src_data; + bit [255:0] dst_data; + int fifo_width = 32; + int offset = 0; + src_data_fifo = mem[src_host_id].read_block(src_addr, length); + dst_data_fifo = mem[dst_host_id].read_block(dst_addr, length); + while (src_data_fifo.get_depth() != 0) begin + src_data = src_data_fifo.pop(); + dst_data = dst_data_fifo.pop(); + `uvm_info("CHECK_INFO", $sformatf("src_host_id: %h, src_addr: %h, src_data: %h, dst_host_id: %h, dst_addr: %h, dst_data: %h, length: %d ", + src_host_id, src_addr + offset, src_data, dst_host_id, dst_addr + offset, dst_data, length), UVM_LOW); + offset = offset + fifo_width; + if (src_data != dst_data) begin + return 0; + end + else begin + `uvm_info("CHECK_INFO", "check correct!", UVM_LOW); + end + end + return 1; + endfunction: check_mem + + task set_global_stop(); + glb_stop_mbx.put(1); + `uvm_info("GLB_STOP_INFO", "global stop signal set by scoreboard!", UVM_LOW); + endtask: set_global_stop + + function bit check_cqe(hca_pcie_item cqe_item, int host_id); + cqe cqe; + bit [255:0] temp_data; + bit [31:0] cqn; + hca_comp_queue cq; + hca_queue_pair qp; + + cqn = {19'b0, cqe_item.rq_addr[32:20]}; + + // check if error CQE + temp_data = cqe_item.data_payload.pop_front(); + cqe.my_qpn = temp_data[31:0]; + cqe.rqpn = temp_data[95:64]; + cqe.syndrome = temp_data[135:128]; + cqe.vender_err = temp_data[143:136]; + cqe.db_cnt = temp_data[159:144]; + cqe.wqe = temp_data[223:192]; + cqe.opcode = temp_data[231:224]; + cqe.is_send = temp_data[239:232]; + cqe.owner = temp_data[255:248]; + if (cqe.is_send == 1) begin + if (cqe.opcode != 8'h00 && + cqe.opcode != 8'h08 && + cqe.opcode != 8'h09 && + cqe.opcode != 8'h0a && + cqe.opcode != 8'h0b && + cqe.opcode != 8'h10 && + cqe.opcode != 8'h11 && + cqe.opcode != 8'h12 && + cqe.opcode != 8'h18) begin + `uvm_fatal("CQE_ERR", $sformatf("send CQE error! host_id: %h, QP number: %h, syndrome: %h, opcode: %h", host_id, cqe.my_qpn, cqe.syndrome, cqe.opcode)); + end + end + else begin + if (cqe.opcode != 8'h02 && + cqe.opcode != 8'h03 && + cqe.opcode != 8'h04 && + cqe.opcode != 8'h05 && + cqe.opcode != 8'h09 && + cqe.opcode != 8'h0b) begin + `uvm_fatal("CQE_ERR", $sformatf("recv CQE error! host_id: %h, QP number: %h, syndrome: %h, opcode: %h", host_id, cqe.my_qpn, cqe.syndrome, cqe.opcode)); + end + end + + cq = q_list.get_cq(host_id, cqn); + // if (cq.header % (32 * (2 ** cq.ctx.logsize)) == {44'b0, cqe_item.rq_addr[19:0]}) begin + // cq.header += 32; + // end + // else begin + // `uvm_fatal("CQE_ERR", $sformatf("CQE address error! host_id: %h, cqn: %h, header: %h, addr: %h", host_id, cqn, cq.header, cqe_item.rq_addr)); + // end + + // check cqn + qp = q_list.get_qp(host_id, cqe.my_qpn); + if (cqe.is_send == 1) begin + if (qp.ctx.cqn_snd != cqn) begin + `uvm_fatal("CQE_ERR", $sformatf("send CQ number mismatch! qp.ctx.cqn_snd: %h, addr_cqn: %h, CQ context CQN: %h", qp.ctx.cqn_snd, cqn, cq.ctx.cqn)); + end + end + else begin + if (qp.ctx.cqn_rcv != cqn) begin + `uvm_fatal("CQE_ERR", $sformatf("recv CQ number mismatch! qp.ctx.cqn_rcv: %h, addr_cqn: %h, CQ context CQN: %h", qp.ctx.cqn_rcv, cqn, cq.ctx.cqn)); + end + end + endfunction: check_cqe + + function string get_sys_time(); + string sys_time; + int fp; + $system("date +%Y-%m-%d' '%H:%M:%S > sys_time"); + fp = $fopen("sys_time", "r"); + $fgets(sys_time, fp); + $fclose(fp); + $system("rm sys_time"); + return sys_time; + endfunction: get_sys_time +endclass: hca_scoreboard +`endif \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/verification/src/vrf_HTN/sv/hca_sub_env.sv b/ETH-PLUS_Jingzhao/JingZhao2/verification/src/vrf_HTN/sv/hca_sub_env.sv new file mode 100644 index 0000000000000000000000000000000000000000..3b438ad4c6071fb69ebc17e73e0aee9e43505a7b --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/verification/src/vrf_HTN/sv/hca_sub_env.sv @@ -0,0 +1,71 @@ +//CREATE INFORMATION +//---------------------------------------------------------------------------- +// +// (C) COPYRIGHT 2021 BY ICT-HPC CORPORATION ALL RIGHTS RESERVED +// DATE : 2021-01-27 +// AUTHOR : mazhenlong@ncic.ac.cn +// FILENAME : hca_sub_env.sv +// FUNCTION : This file supplies the env of verification of HCA. +// +//---------------------------------------------------------------------------- + + +//CHANGE HISTORY +//---------------------------------------------------------------------------- +// +// AUTHOR DATE VERSION REASON +// mazhenlong 2021-01-27 v1.0 create +// +//---------------------------------------------------------------------------- + +`ifndef __HCA_SUB_ENV__ +`define __HCA_SUB_ENV__ + +//------------------------------------------------------------------------------ +// +// CLASS: hca_sub_env +// +//------------------------------------------------------------------------------ +class hca_sub_env extends uvm_env; + hca_master_agent mst_agt; + hca_slave_agent slv_agt; + hca_memory mem; + + `uvm_component_utils_begin(hca_sub_env) + `uvm_field_object(mst_agt, UVM_DEFAULT) + `uvm_field_object(slv_agt, UVM_DEFAULT) + `uvm_component_utils_end + + //------------------------------------------------------------------------------ + // function name : new + // function : constructor + // invoked : invoked when instantiates the class + //------------------------------------------------------------------------------ + function new(string name, uvm_component parent); + super.new(name, parent); + endfunction: new + + //------------------------------------------------------------------------------ + // function name : build_phase + // function : build_phase in uvm library, instantiates agents + // invoked : invoked by uvm automatically + //------------------------------------------------------------------------------ + function void build_phase(uvm_phase phase); + super.build_phase(phase); + mst_agt = hca_master_agent::type_id::create("mst_agt", this); + slv_agt = hca_slave_agent::type_id::create("slv_agt", this); + endfunction: build_phase + + //------------------------------------------------------------------------------ + // task name : pre_reset_phase + // function : point mem in agent to this.mem + // invoked : invoked by uvm automatically + //------------------------------------------------------------------------------ + task pre_reset_phase(uvm_phase phase); + super.pre_reset_phase(phase); + // $cast(mst_agt.if, this.v_if); + $cast(mst_agt.mem, this.mem); + $cast(slv_agt.mem, this.mem); + endtask: pre_reset_phase +endclass: hca_sub_env +`endif \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/verification/src/vrf_HTN/sv/hca_vsequence.sv b/ETH-PLUS_Jingzhao/JingZhao2/verification/src/vrf_HTN/sv/hca_vsequence.sv new file mode 100644 index 0000000000000000000000000000000000000000..3511dbb88f900cb4ebd65edcb15fb4f8fa690efa --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/verification/src/vrf_HTN/sv/hca_vsequence.sv @@ -0,0 +1,193 @@ +//CREATE INFORMATION +//------------------------------------------------------------------------------------------ +// +// (C) COPYRIGHT 2021 BY ICT-HPC CORPORATION ALL RIGHTS RESERVED +// DATE : 2021-03-17 +// AUTHOR : mazhenlong@ncic.ac.cn +// FILENAME : hca_vsequence.sv +// FUNCTION : This file supplies the virtual sequence of verification of HCA. +// +//------------------------------------------------------------------------------------------ + +//CHANGE HISTORY +//------------------------------------------------------------------------------------------ +// +// AUTHOR DATE VERSION REASON +// mazhenlong 2021-03-17 v1.0 create +// mazhenlong 2021-04-19 v1.1 change launching cfg_seq from `uvm_do_on +// to cfg_seq.start +// mazhenlong 2021-04-20 v1.2 change pre_do() to pre_body(), for difference +// between them see https://www.chipverify.com/uvm/how-to-execute-sequences-via-start-method +// +//------------------------------------------------------------------------------------------ + +`ifndef __HCA_VSEQ__ +`define __HCA_VSEQ__ + +//-------------------------------------------------------------------------------------------- +// +// CLASS: hca_vsequence +// +//-------------------------------------------------------------------------------------------- +class hca_vsequence extends uvm_sequence; + hca_pcie_item recv_item; + hca_pcie_item cfg_item_que[][$]; + hca_pcie_item comm_item_que[][$]; + hca_config_sequence cfg_seq[]; + hca_slave_sequence slv_seq[]; + hca_comm_sequence comm_seq[]; + mailbox cfg_mbx[]; + mailbox comm_mbx[]; + semaphore cfg_comm_sem[]; + semaphore comm_cfg_sem[]; + + int host_num = 1; + + `uvm_object_utils_begin(hca_vsequence) + `uvm_object_utils_end + + `uvm_declare_p_sequencer(hca_vsequencer) + + //------------------------------------------------------------------------------ + // function name : new + // function : constructor + // invoked : invoked when instantiates the class + //------------------------------------------------------------------------------ + function new(string name = "hca_vsequence"); + + endfunction: new + + function init(int host_num); + string array_element; + this.host_num = host_num; + cfg_item_que = new[host_num]; + comm_item_que = new[host_num]; + + cfg_seq = new[host_num]; + slv_seq = new[host_num]; + comm_seq = new[host_num]; + + cfg_mbx = new[host_num]; + comm_mbx = new[host_num]; + + cfg_comm_sem = new[host_num]; + comm_cfg_sem = new[host_num]; + + for (int i = 0; i < host_num; i++) begin + cfg_comm_sem[i] = new(1); + comm_cfg_sem[i] = new(1); + end + + for (int i = 0; i < host_num; i++) begin + cfg_mbx[i] = new(); + comm_mbx[i] = new(); + end + for (int i = 0; i < host_num; i++) begin + array_element = $sformatf("cfg_seq[%0d]", i); + cfg_seq[i] = hca_config_sequence::type_id::create(array_element, ,get_full_name); + end + for (int i = 0; i < host_num; i++) begin + array_element = $sformatf("slv_seq[%0d]", i); + slv_seq[i] = hca_slave_sequence::type_id::create(array_element, , get_full_name); + slv_seq[i].host_id = i; + end + for (int i = 0; i < host_num; i++) begin + array_element = $sformatf("comm_seq[%0d]", i); + comm_seq[i] = hca_comm_sequence::type_id::create(array_element, , get_full_name); + end + endfunction: init + + //------------------------------------------------------------------------------ + // task name : pre_body + // function : send cfg item to cfg seq + // invoked : invoked by UVM automatically + //------------------------------------------------------------------------------ + virtual task pre_body(); + + endtask: pre_body + + //------------------------------------------------------------------------------ + // task name : body + // function : generate cfg_seq and slv_seq + // invoked : invoked by UVM automatically + //------------------------------------------------------------------------------ + virtual task body(); + for (int i = 0; i < host_num; i++) begin + fork + automatic int j = i; + begin + while (1) begin + hca_pcie_item cfg_item; + comm_cfg_sem[j].get(1); + `uvm_info("NOTICE", $sformatf("config thread begin! host_id: %0d.", j), UVM_LOW); + while (1) begin + cfg_mbx[j].get(cfg_item); + if (cfg_item.item_type == BATCH) begin + `uvm_info("NOTICE", "BATCH item received by vseq in config! Go to communication!", UVM_LOW); + cfg_comm_sem[j].put(1); + break; + end + else if (cfg_item.item_type == GLOBAL_STOP) begin + `uvm_info("NOTICE", "GLOBAL_STOP item received by vseq in config!", UVM_LOW); + cfg_seq[j].cfg_item_que.push_back(cfg_item); + cfg_seq[j].start(p_sequencer.mst_sqr[j], , , 1); + cfg_comm_sem[j].put(1); + break; + end + else if (cfg_item.item_type == HCR) begin + `uvm_info("NOTICE", "config item received by vseq in config!", UVM_LOW); + cfg_seq[j].cfg_item_que.push_back(cfg_item); + cfg_seq[j].start(p_sequencer.mst_sqr[j], , , 1); + end + else begin + `uvm_fatal("ITEM TYPE ERROR", "wrong item type!"); + end + end + if (cfg_item.item_type == GLOBAL_STOP) begin + `uvm_info("NOTICE", "vsequence config thread ends!", UVM_LOW); + break; + end + end + end + begin + cfg_comm_sem[j].get(1); + while (1) begin + hca_pcie_item comm_item; + cfg_comm_sem[j].get(1); + `uvm_info("NOTICE", "comm thread begin!", UVM_LOW); + while (1) begin + comm_mbx[j].get(comm_item); + if (comm_item.item_type == DOORBELL) begin + `uvm_info("NOTICE", "doorbell item received by vseq in comm!", UVM_LOW); + // slv_seq[j].stop = 1; + comm_seq[j].comm_item_que.push_back(comm_item); + comm_seq[j].start(p_sequencer.mst_sqr[j], , , 1); + end + else if (comm_item.item_type == BATCH) begin + `uvm_info("NOTICE", "BATCH item received by vseq in comm! Go to Configuration!", UVM_LOW); + comm_cfg_sem[j].put(1); + break; + end + else if (comm_item.item_type == GLOBAL_STOP) begin + `uvm_info("NOTICE", "GLOBAL_STOP item received by vseq in comm!", UVM_LOW); + comm_cfg_sem[j].put(1); + break; + end + else begin + `uvm_fatal("ITEM TYPE ERROR", "wrong item type!"); + end + end + if (comm_item.item_type == GLOBAL_STOP) begin + `uvm_info("NOTICE", "vsequence comm thread ends!", UVM_LOW); + break; + end + end + end + slv_seq[j].start(p_sequencer.slv_sqr[j], , , 1); + join_none + end + wait fork; + `uvm_info("NOTICE", "vsequence body end!", UVM_LOW); + endtask: body +endclass: hca_vsequence +`endif \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/verification/src/vrf_HTN/sv/hca_vsequencer.sv b/ETH-PLUS_Jingzhao/JingZhao2/verification/src/vrf_HTN/sv/hca_vsequencer.sv new file mode 100644 index 0000000000000000000000000000000000000000..604a41698b5aeee38da04e5b814367254bb91397 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/verification/src/vrf_HTN/sv/hca_vsequencer.sv @@ -0,0 +1,71 @@ +//CREATE INFORMATION +//---------------------------------------------------------------------------- +// +// (C) COPYRIGHT 2021 BY ICT-HPC CORPORATION ALL RIGHTS RESERVED +// DATE : 2021-03-17 +// AUTHOR : mazhenlong@ncic.ac.cn +// FILENAME : hca_vsequencer.sv +// FUNCTION : This file supplies the virtual sequencer of verification of HCA. +// +//---------------------------------------------------------------------------- + +//CHANGE HISTORY +//---------------------------------------------------------------------------- +// +// AUTHOR DATE VERSION REASON +// mazhenlong 2021-03-25 v1.0 create +// +//---------------------------------------------------------------------------- + +`ifndef __HCA_VSEQUENCER__ +`define __HCA_VSEQUENCER__ + +//------------------------------------------------------------------------------ +// +// CLASS: hca_vsequencer +// +//------------------------------------------------------------------------------ +class hca_vsequencer extends uvm_sequencer; + hca_slave_sequencer slv_sqr[]; + hca_master_sequencer mst_sqr[]; + int host_num = 1; + + `uvm_component_utils_begin(hca_vsequencer) + `uvm_component_utils_end + + //------------------------------------------------------------------------------ + // function name : new + // function : constructor + // invoked : invoked when instantiates the class + //------------------------------------------------------------------------------ + function new(string name = "hca_vsequencer", uvm_component parent = null); + super.new(name, parent); + endfunction: new + + //------------------------------------------------------------------------------ + // function name : build_phase + // function : build_phase in uvm library, instantiate config sequencer and + // slave sequencer. + // invoked : invoked by uvm automatically + //------------------------------------------------------------------------------ + function void build_phase(uvm_phase phase); + string array_element; + super.build_phase(phase); + + slv_sqr = new[host_num]; + // instantiate slv_sqr + for (int i = 0; i < host_num; i++) begin + array_element = $sformatf("slv_sqr[%0d]", i); + slv_sqr[i] = hca_slave_sequencer::type_id::create(array_element, this); + end + + mst_sqr = new[host_num]; + // instantiate mst_sqr + for (int i = 0; i < host_num; i++) begin + array_element = $sformatf("mst_sqr[%0d]", i); + mst_sqr[i] = hca_master_sequencer::type_id::create(array_element, this); + end + endfunction: build_phase +endclass + +`endif \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/verification/src/vrf_HTN/sv/master/hca_master_agent.sv b/ETH-PLUS_Jingzhao/JingZhao2/verification/src/vrf_HTN/sv/master/hca_master_agent.sv new file mode 100644 index 0000000000000000000000000000000000000000..8da6b5675685938e9e86f123b1a8cd630aa082ab --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/verification/src/vrf_HTN/sv/master/hca_master_agent.sv @@ -0,0 +1,73 @@ +//CREATE INFORMATION +//-------------------------------------------------------------------------------------- +// +// (C) COPYRIGHT 2021 BY ICT-HPC CORPORATION ALL RIGHTS RESERVED +// DATE : 2021-01-19 +// AUTHOR : mazhenlong@ncic.ac.cn +// FILENAME : hca_master_agent.sv +// FUNCTION : This file supplies the agent that accesses HCR and doorbell +// registers of HCA. +// +//-------------------------------------------------------------------------------------- + +//CHANGE HISTORY +//-------------------------------------------------------------------------------------- +// +// AUTHOR DATE VERSION REASON +// mazhenlong 2021-01-19 v1.0 create +// mazhenlong 2021-04-01 v1.1 change filename and reg_* to mst_* +// +//-------------------------------------------------------------------------------------- + +`ifndef __HCA_MASTER_AGENT__ +`define __HCA_MASTER_AGENT__ + +//------------------------------------------------------------------------------ +// +// CLASS: hca_master_agent +// +//------------------------------------------------------------------------------ +class hca_master_agent extends uvm_agent; + hca_master_sequencer mst_sqr; + hca_master_driver mst_drv; + hca_memory mem; + mailbox cmd_done; + + + `uvm_component_utils_begin(hca_master_agent) + `uvm_component_utils_end + + //------------------------------------------------------------------------------ + // function name : new + // function : constructor + // invoked : invoked when instantiates the class + //------------------------------------------------------------------------------ + function new(string name, uvm_component parent); + super.new(name, parent); + endfunction: new + + //------------------------------------------------------------------------------ + // function name : build_phase + // function : build_phase in uvm library, instantiates sequencer and driver. + // invoked : automatically by uvm + //------------------------------------------------------------------------------ + function void build_phase(uvm_phase phase); + super.build_phase(phase); + mst_sqr = hca_master_sequencer::type_id::create("mst_sqr", this); + mst_drv = hca_master_driver::type_id::create("mst_drv", this); + cmd_done = new(); + uvm_config_db#(mailbox)::set(this, "*", "mbx_cmd_done", cmd_done); + // `uvm_info("PARAM_INFO", $sformatf("uvm_config_db set finished! full name: %s.", get_full_name()), UVM_LOW); + // uvm_config_db#(mailbox)::set(this, "", "mbx_cmd_done", cmd_done); + endfunction: build_phase + + //------------------------------------------------------------------------------ + // function name : connect_phase + // function : connect_phase in uvm library, connect sequencer and driver. + // invoked : automatically by uvm + //------------------------------------------------------------------------------ + function void connect_phase(uvm_phase phase); + mst_drv.seq_item_port.connect(mst_sqr.seq_item_export); + endfunction: connect_phase +endclass: hca_master_agent +`endif \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/verification/src/vrf_HTN/sv/master/hca_master_driver.sv b/ETH-PLUS_Jingzhao/JingZhao2/verification/src/vrf_HTN/sv/master/hca_master_driver.sv new file mode 100644 index 0000000000000000000000000000000000000000..df0ee9b8e26e31506b7867ef4f890dfebc35e1f3 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/verification/src/vrf_HTN/sv/master/hca_master_driver.sv @@ -0,0 +1,463 @@ +//CREATE INFORMATION +//-------------------------------------------------------------------------------------- +// +// (C) COPYRIGHT 2021 BY ICT-HPC CORPORATION ALL RIGHTS RESERVED +// DATE : 2021-01-19 +// AUTHOR : mazhenlong@ncic.ac.cn +// FILENAME : hca_master_driver.sv +// FUNCTION : This file supplies the driver of registers, transferring a pcie +// packet to signals on ports of DUT. +// +//-------------------------------------------------------------------------------------- + +//CHANGE HISTORY +//-------------------------------------------------------------------------------------- +// +// AUTHOR DATE VERSION REASON +// mazhenlong 2021-01-19 v1.0 create +// mazhenlong 2021-03-03 v1.1 rewrite drive_reg_item +// mazhenlong 2021-03-22 v1.2 finish the procedure of receiving read +// response +// mazhenlong 2021-04-01 v1.3 change filename and reg_* to mst_* +// mazhenlong 2022-01-28 v2 add multi host support: v_if[] +// +//-------------------------------------------------------------------------------------- + + +`ifndef __HCA_MASTER_DRIVER__ +`define __HCA_MASTER_DRIVER__ + +//---------------------------------------------------------------------------------------- +// +// CLASS: hca_master_driver +// +//---------------------------------------------------------------------------------------- +class hca_master_driver extends uvm_driver #(hca_pcie_item); + virtual hca_interface v_if; + hca_pcie_item req_item; + + // hca_memory mem; + + mailbox cmd_done; + + uvm_analysis_port #(hca_pcie_item) port2rm_cfg; + uvm_analysis_port #(hca_pcie_item) port2rm_comm; + + `uvm_component_utils_begin(hca_master_driver) + `uvm_component_utils_end + + //------------------------------------------------------------------------------ + // function name : new + // function : constructor + // invoked : invoked when instantiates the class + //------------------------------------------------------------------------------ + function new(string name, uvm_component parent); + super.new(name, parent); + endfunction: new + + //------------------------------------------------------------------------------ + // function name : build_phase + // function : build_phase in uvm library, instantiates port and get virtual + // interface. + // invoked : automatically by uvm + //------------------------------------------------------------------------------ + function void build_phase(uvm_phase phase); + super.build_phase(phase); + + if (!uvm_config_db#(virtual hca_interface)::get(this, "", "virtual_if", v_if)) begin + `uvm_fatal("NOVIF", {"virtual interface must be set for: ",get_full_name(),".v_if!"}); + end + port2rm_cfg = new("port2rm_cfg", this); + port2rm_comm = new("port2rm_comm", this); + // cmd_done = new(); + // uvm_config_db#(mailbox)::set(uvm_root::get(), "*.env.sub_env[*].mst_agt.mst_sqr*", "mbx_cmd_done", cmd_done); + // `uvm_info("PARAM_INFO", $sformatf("uvm_config_db get waiting! full name: %s.", get_full_name()), UVM_LOW); + if(!uvm_config_db#(mailbox)::get(null, get_full_name(), "mbx_cmd_done", cmd_done)) begin + `uvm_fatal("NO_MBX", "mailbox not get in master_driver!"); + end + // `uvm_info("NOTICE", {"build phase finished in ", get_full_name}, UVM_LOW) + endfunction: build_phase + + //------------------------------------------------------------------------------ + // task name : run_phase + // function : run_phase in uvm library, sends the pcie items to DUT + // invoked : invoked by uvm automaticly + //------------------------------------------------------------------------------ + task run_phase(uvm_phase phase); + phase.raise_objection(this); + `uvm_info("NOTICE", {"run phase begin in ", get_full_name}, UVM_LOW) + @ (posedge v_if.veri_en); + `uvm_info("NOTICE", {"veri_en enabled in ", get_full_name}, UVM_LOW); + forever begin + @ (posedge v_if.pcie_clk); + `uvm_info("NOTICE", "before get_next_item...", UVM_LOW); + seq_item_port.get_next_item(req_item); + `uvm_info("NOTICE", {"req_item get in ", get_full_name}, UVM_LOW); + // if (req_item.item_type == DOORBELL) begin + // if (req_item.db.host_id == 0) begin + // for (int i = 0; i < `CFG_COMM_GAP; i++) begin + // @ (posedge v_if.pcie_clk); + // end + // end + // end + drive_item(req_item); + if (req_item.item_type == GLOBAL_STOP) begin + `uvm_info("NOTICE", "global stop item received in master driver!", UVM_LOW); + v_if.global_stop = 1'b1; + seq_item_port.item_done(); + break; + end + seq_item_port.item_done(); + for (int i = 0; i < `CFG_GAP; i++) begin + @ (posedge v_if.pcie_clk); + end + end + `uvm_info("NOTICE", "master driver run_phase end!", UVM_LOW); + phase.drop_objection(this); + endtask: run_phase + + //------------------------------------------------------------------------------ + // task name : drive_item + // function : send the pcie items to DUT + // invoked : invoked by run_phase + //------------------------------------------------------------------------------ + task drive_item(hca_pcie_item req_item); + bit [`DATA_WIDTH-1: 0] temp_wr_data; + bit [`DATA_WIDTH-1: 0] temp_rd_data; + hca_pcie_item item2rm; + + bit [31:0] parity; + int i, j, m, n; + int sent_dw_num = 0; + + // send req_item to reference model + item2rm = hca_pcie_item::type_id::create("item2rm"); + // item2rm.item_type == DMA_RD; + item2rm.copy(req_item); + item2rm.copy_struct(req_item); + if (item2rm.item_type == HCR) begin + // `uvm_info("NOTICE", "config item send to ref model from master driver begin!", UVM_LOW); + port2rm_cfg.write(item2rm); + // `uvm_info("NOTICE", "config item send to ref model from master driver finish!", UVM_LOW); + end + else if (item2rm.item_type == DOORBELL) begin + // `uvm_info("NOTICE", "comm item send to ref model from master driver begin!", UVM_LOW); + port2rm_comm.write(item2rm); + // `uvm_info("NOTICE", "comm item send to ref model from master driver finish!", UVM_LOW); + end + else if (item2rm.item_type == GLOBAL_STOP) begin + port2rm_comm.write(item2rm); + port2rm_cfg.write(item2rm); + `uvm_info("NOTICE", "global stop item sent to ref model!", UVM_LOW); + return; + end + else begin + `uvm_fatal("ITEM_TYPE_ERROR", $sformatf("illegal item_type in master driver! item2rm item_type: %h", item2rm.item_type)); + end + // `uvm_info("NOTICE", {"port2rm write finished in ", get_full_name}, UVM_LOW); + + + // drive signal to duv + if (req_item.cq_req_type == MEM_WR) begin + `uvm_info("NOTICE", {"MEM_WR begin in ", get_full_name()}, UVM_LOW) + if (req_item.item_type == HCR) begin + drive_hcr_item(req_item); + end + else if (req_item.item_type == DOORBELL) begin + drive_db_item(req_item); + end + else begin + `uvm_error("ILG_REQ_TYP", "illegal master driver input req item type!"); + end + // drive_item_to_dut(req_item); + end + else begin + `uvm_error("ILG_REQ_TYP", "illegal master driver input req item cq_req_type!"); + end + endtask: drive_item + + //------------------------------------------------------------------------------ + // task name : drive_hcr_item + // function : send the pcie items containint hcr content to DUT + // invoked : invoked by drive_item + //------------------------------------------------------------------------------ + task drive_hcr_item(hca_pcie_item req_item); + bit [`DATA_WIDTH-1: 0] temp_wr_data; + bit [`DATA_WIDTH-1: 0] temp_rd_data; + bit [63:0] temp_addr; + bit [31:0] parity; + int i, j, m, n; + int sent_dw_num = 0; + `uvm_info("NOTICE", {"drive HCR item begin in ", get_full_name()}, UVM_LOW); + temp_addr = req_item.cq_addr; + temp_wr_data = req_item.data_payload.pop_front(); + for (int i = 0; i < `HCR_BYTE_SIZE / `DW_BYTE_SIZE; i++) begin + // `uvm_info("NOTICE", {"MEM_WR beat ", get_full_name()}, UVM_LOW) + // set tlast + v_if.m_axis_cq_tlast = 1'b1; + + // set tvalid + v_if.m_axis_cq_tvalid <= 1'b1; + + // set tkeep + v_if.m_axis_cq_tkeep = 8'b0001_1111; + + // set tdata + v_if.m_axis_cq_tdata[1:0] = req_item.cq_addr_type; + v_if.m_axis_cq_tdata[63:2] = temp_addr[63:2]; + v_if.m_axis_cq_tdata[74:64] = 11'b000_0000_0001; + v_if.m_axis_cq_tdata[78:75] = req_item.cq_req_type; + v_if.m_axis_cq_tdata[79] = 1'b0; + v_if.m_axis_cq_tdata[87:80] = req_item.cq_device; + v_if.m_axis_cq_tdata[95:88] = req_item.cq_bus; + v_if.m_axis_cq_tdata[103:96] = req_item.cq_tag; + v_if.m_axis_cq_tdata[111:104] = req_item.cq_target_function; + v_if.m_axis_cq_tdata[114:112] = req_item.cq_bar_id; + v_if.m_axis_cq_tdata[120:115] = req_item.cq_bar_aperture; + v_if.m_axis_cq_tdata[123:121] = req_item.cq_tc; + v_if.m_axis_cq_tdata[126:124] = req_item.cq_attr; + v_if.m_axis_cq_tdata[127] = 1'b0; + v_if.m_axis_cq_tdata[159:128] = temp_wr_data[i * 32 + 31 -: 32]; + v_if.m_axis_cq_tdata[255:160] = 0; + + temp_addr = temp_addr + 4; + + // set tuser + /* CQ tuser + * | 84:53 | 52:45 | 44:43 | 42 | 41 | 40 | 39:8 | 7:4 | 3:0 | + * | parity | tph_st_tag | tph_type | tph_present | discontinue | sop | byte_en | last_be | first_be | + * | | 0 | 0 | ignore | ignore | | ignore | | | + */ + for (m = 0; m < 32; m++) begin + for (n = 0; n < 8; n++) begin + if (v_if.m_axis_cq_tdata[m * 8 + n] == 1'b1) begin + parity[m] = ~parity[m]; + end + end + end + v_if.m_axis_cq_tuser[84:53] = parity; + v_if.m_axis_cq_tuser[52:41] = 0; + v_if.m_axis_cq_tuser[40] = 1'b1; + v_if.m_axis_cq_tuser[39:8] = 0; + v_if.m_axis_cq_tuser[7:4] = 4'b1111; // last be + v_if.m_axis_cq_tuser[3:0] = 4'b1111; // first be + + while (1) begin + @ (posedge v_if.pcie_clk); + if (v_if.m_axis_cq_tready == 1'b1) begin + break; + end + end + end + v_if.m_axis_cq_tvalid = 1'b0; + wait_clear(); + cmd_done.put(1'b1); // inform config sequence hardware finished + endtask: drive_hcr_item + + //------------------------------------------------------------------------------ + // task name : wait_clear + // function : wait go bit of hcr register turning from 1 to 0 + // invoked : invoked by drive_hcr_item + //------------------------------------------------------------------------------ + task wait_clear(); + int read_go_gap = `READ_GO_GAP; + int read_go_counter; + bit go; + bit [7:0] status; + int threshold; + int i; + string seq_name; + read_go_counter = 0; + threshold = 100; + while (1) begin + @ (posedge v_if.pcie_clk); + read_go_counter++; + if (read_go_counter > read_go_gap) begin + read_go_counter = 0; + check_status(go, status); + if (status != 0) begin + if (!$value$plusargs("HCA_CASE_NAME=%s", seq_name)) begin + `uvm_fatal("hca_master_driver", "HCA_CASE_NAME not get!"); + end + if (seq_name != "test_ilg_op") begin + `uvm_fatal("ilg_op", "status abnormal!"); + end + end + if (go == 0) begin // if cmd excuted successfully + `uvm_info("CONFIG_INFO", "CMD go cleared!", UVM_LOW); + break; + end + else begin + `uvm_info("CONFIG_INFO", "CMD go uncleared!", UVM_LOW); + i++; + if (i >= threshold) begin + `uvm_fatal("CONFIG_ERR", "config too long!"); + end + end + end + end + endtask: wait_clear + + //------------------------------------------------------------------------------ + // task name : check_status + // function : read go and status fields of HCR register to check the execution + // status of the cmd. + // invoked : invoked by wait_clear + //------------------------------------------------------------------------------ + task check_status(ref bit go, ref bit [7:0] status); + // bit go; + bit [63:0] temp_addr = `HCR_BAR_ADDR + 24; + int parity; + bit [7:0] tag = 8'h12; + int i, j, m, n; + + fork + // send read req + begin + parity = 0; + + // set tvalid + v_if.m_axis_cq_tvalid = 1'b1; + + // set tlast + v_if.m_axis_cq_tlast = 1; + + // set tkeep + v_if.m_axis_cq_tkeep = 8'b0000_1111; + + // set tdata + v_if.m_axis_cq_tdata[1:0] = 0; + v_if.m_axis_cq_tdata[63:2] = temp_addr[63:2]; + v_if.m_axis_cq_tdata[76:64] = 8'b0000_0001; + v_if.m_axis_cq_tdata[78:75] = MEM_RD; + v_if.m_axis_cq_tdata[79] = 1'b0; + v_if.m_axis_cq_tdata[87:80] = 0; + v_if.m_axis_cq_tdata[95:88] = 0; + v_if.m_axis_cq_tdata[103:96] = tag; + v_if.m_axis_cq_tdata[111:104] = 0; + v_if.m_axis_cq_tdata[114:112] = 0; + v_if.m_axis_cq_tdata[120:115] = 28; + v_if.m_axis_cq_tdata[123:121] = 0; + v_if.m_axis_cq_tdata[126:124] = 0; + v_if.m_axis_cq_tdata[127] = 1'b0; + v_if.m_axis_cq_tdata[255:128] = 0; + + // set tuser + /* CQ tuser + * | 84:53 | 52:45 | 44:43 | 42 | 41 | 40 | 39:8 | 7:4 | 3:0 | + * | parity | tph_st_tag | tph_type | tph_present | discontinue | sop | byte_en | last_be | first_be | + * | | 0 | 0 | ignore | ignore | | ignore | | | + */ + for (m = 0; m < 32; m++) begin + for (n = 0; n < 8; n++) begin + if (v_if.m_axis_cq_tdata[m * 8 + n] == 1'b1) begin + parity[m] = ~parity[m]; + end + end + end + v_if.m_axis_cq_tuser[84:53] = parity; + v_if.m_axis_cq_tuser[52:41] = 0; + v_if.m_axis_cq_tuser[40] = 1'b1; + v_if.m_axis_cq_tuser[39:8] = 0; + v_if.m_axis_cq_tuser[7:4] = 4'b1111; // last be + v_if.m_axis_cq_tuser[3:0] = 4'b1111; // first be + + while (1) begin + @ (posedge v_if.pcie_clk); + if (v_if.m_axis_cq_tready == 1'b1) begin + break; + end + end + v_if.m_axis_cq_tvalid = 1'b0; + // `uvm_info("NOTICE", {"MEM_RD req sent finished ... ", get_full_name()}, UVM_LOW); + end + + // recieve response + begin + v_if.s_axis_cc_tready = 1'b1; + // judge valid data + // WARNING: possibly get wrong response! + while (1) begin + @ (posedge v_if.pcie_clk); + if (v_if.s_axis_cc_tvalid == 1'b1 && v_if.s_axis_cc_tdata[71:64] == tag) begin + break; + end + end + v_if.s_axis_cc_tready = 1'b0; + go = v_if.s_axis_cc_tdata[119]; + status = v_if.s_axis_cc_tdata[127:120]; + end + join + // return go; + endtask: check_status + + task drive_db_item(hca_pcie_item req_item); // currently only support 64B doorbell + bit [`DATA_WIDTH-1: 0] temp_wr_data; + bit [63:0] temp_addr; + bit [31:0] parity; + int i, j, m, n; + `uvm_info("NOTICE", {"db req begin in ", get_full_name()}, UVM_LOW) + temp_addr = req_item.cq_addr; + temp_wr_data = req_item.data_payload.pop_front(); + + // different from driving hcr, driving doorbell only needs one beat + // set tlast + v_if.m_axis_cq_tlast = 1'b1; + + // set tvalid + v_if.m_axis_cq_tvalid <= 1'b1; + + // set tkeep + v_if.m_axis_cq_tkeep = 8'b0011_1111; + + // set tdata + v_if.m_axis_cq_tdata[1:0] = req_item.cq_addr_type; + v_if.m_axis_cq_tdata[63:2] = temp_addr[63:2]; + v_if.m_axis_cq_tdata[76:64] = 8'h02; + v_if.m_axis_cq_tdata[78:75] = req_item.cq_req_type; + v_if.m_axis_cq_tdata[79] = 1'b0; + v_if.m_axis_cq_tdata[87:80] = req_item.cq_device; + v_if.m_axis_cq_tdata[95:88] = req_item.cq_bus; + v_if.m_axis_cq_tdata[103:96] = req_item.cq_tag; + v_if.m_axis_cq_tdata[111:104] = req_item.cq_target_function; + v_if.m_axis_cq_tdata[114:112] = req_item.cq_bar_id; + v_if.m_axis_cq_tdata[120:115] = req_item.cq_bar_aperture; + v_if.m_axis_cq_tdata[123:121] = req_item.cq_tc; + v_if.m_axis_cq_tdata[126:124] = req_item.cq_attr; + v_if.m_axis_cq_tdata[127] = 1'b0; + v_if.m_axis_cq_tdata[191:128] = temp_wr_data[63:0]; + v_if.m_axis_cq_tdata[255:192] = 0; + + temp_addr = temp_addr + 4; + + // set tuser + /* CQ tuser + * | 84:53 | 52:45 | 44:43 | 42 | 41 | 40 | 39:8 | 7:4 | 3:0 | + * | parity | tph_st_tag | tph_type | tph_present | discontinue | sop | byte_en | last_be | first_be | + * | | 0 | 0 | ignore | ignore | | ignore | | | + */ + for (m = 0; m < 32; m++) begin + for (n = 0; n < 8; n++) begin + if (v_if.m_axis_cq_tdata[m * 8 + n] == 1'b1) begin + parity[m] = ~parity[m]; + end + end + end + v_if.m_axis_cq_tuser[84:53] = parity; + v_if.m_axis_cq_tuser[52:41] = 0; + v_if.m_axis_cq_tuser[40] = 1'b1; + v_if.m_axis_cq_tuser[39:8] = 0; + v_if.m_axis_cq_tuser[7:4] = 4'b1111; // last be + v_if.m_axis_cq_tuser[3:0] = 4'b1111; // first be + + while (1) begin + @ (posedge v_if.pcie_clk); + if (v_if.m_axis_cq_tready == 1'b1) begin + break; + end + end + + v_if.m_axis_cq_tvalid = 1'b0; + endtask: drive_db_item +endclass: hca_master_driver +`endif \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/verification/src/vrf_HTN/sv/master/hca_master_monitor.sv b/ETH-PLUS_Jingzhao/JingZhao2/verification/src/vrf_HTN/sv/master/hca_master_monitor.sv new file mode 100644 index 0000000000000000000000000000000000000000..2fa2afbeb276d65028d994682723fcf897abdd84 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/verification/src/vrf_HTN/sv/master/hca_master_monitor.sv @@ -0,0 +1,43 @@ +//CREATE INFORMATION +//---------------------------------------------------------------------------- +// +// (C) COPYRIGHT 2021 BY ICT-HPC CORPORATION ALL RIGHTS RESERVED +// DATE : 2021-03-15 +// AUTHOR : mazhenlong@ncic.ac.cn +// FILENAME : hca_master_monitor.sv +// FUNCTION : This file supplies the env of verification of HCA. +// +//---------------------------------------------------------------------------- + +//CHANGE HISTORY +//---------------------------------------------------------------------------- +// +// AUTHOR DATE VERSION REASON +// mazhenlong 2021-03-15 v1.0 create +// +//---------------------------------------------------------------------------- + +`ifndef __HCA_MASTER_MONITOR__ +`define __HCA_MASTER_MONITOR__ + +//---------------------------------------------------------------------------- +// +// CLASS: hca_master_monitor +// +//---------------------------------------------------------------------------- +class hca_master_monitor extends uvm_monitor; + virtual hca_interface v_if; + + `uvm_component_utils_begin(hca_master_monitor) + `uvm_component_utils_end + + //------------------------------------------------------------------------------ + // function name : new + // function : constructor + // invoked : invoked when instantiates the class + //------------------------------------------------------------------------------ + function new(string name, uvm_component parent); + super.new(name, parent); + endfunction: new +endclass: hca_master_monitor +`endif \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/verification/src/vrf_HTN/sv/master/hca_master_sequencer.sv b/ETH-PLUS_Jingzhao/JingZhao2/verification/src/vrf_HTN/sv/master/hca_master_sequencer.sv new file mode 100644 index 0000000000000000000000000000000000000000..554461e7d7141f65dc00f17150a895acd3df586f --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/verification/src/vrf_HTN/sv/master/hca_master_sequencer.sv @@ -0,0 +1,51 @@ +//CREATE INFORMATION +//---------------------------------------------------------------------------- +// +// (C) COPYRIGHT 2021 BY ICT-HPC CORPORATION ALL RIGHTS RESERVED +// DATE : 2021-01-19 +// AUTHOR : mazhenlong@ncic.ac.cn +// FILENAME : hca_maseter_sequencer.sv +// FUNCTION : This file supplies the sequencer of registers, passing items +// to driver. +// +//---------------------------------------------------------------------------- + +//CHANGE HISTORY +//---------------------------------------------------------------------------- +// +// AUTHOR DATE VERSION REASON +// mazhenlong 2021-01-19 v1.0 create +// +//---------------------------------------------------------------------------- + +`ifndef __HCA_MASTER_SEQUENCER__ +`define __HCA_MASTER_SEQUENCER__ + +//------------------------------------------------------------------------------ +// +// CLASS: hca_master_sequencer +// +//------------------------------------------------------------------------------ +class hca_master_sequencer extends uvm_sequencer #(hca_pcie_item); + `uvm_component_utils_begin(hca_master_sequencer) + `uvm_component_utils_end + + //------------------------------------------------------------------------------ + // function name : new + // function : constructor + // invoked : invoked when instantiates the class + //------------------------------------------------------------------------------ + function new(string name, uvm_component parent); + super.new(name, parent); + endfunction: new + + //------------------------------------------------------------------------------ + // function name : build_phase + // function : build_phase in uvm library, instantiates sequencer and driver. + // invoked : automatically by uvm + //------------------------------------------------------------------------------ + function void build_phase(uvm_phase phase); + super.build_phase(phase); + endfunction: build_phase +endclass: hca_master_sequencer +`endif \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/verification/src/vrf_HTN/sv/master/regs/hca_reg2pcie_adapter.sv b/ETH-PLUS_Jingzhao/JingZhao2/verification/src/vrf_HTN/sv/master/regs/hca_reg2pcie_adapter.sv new file mode 100644 index 0000000000000000000000000000000000000000..81c2879b9ef3901f668a961429db27ea91c29dca --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/verification/src/vrf_HTN/sv/master/regs/hca_reg2pcie_adapter.sv @@ -0,0 +1,133 @@ +//CREATE INFORMATION +//---------------------------------------------------------------------------- +// +// (C) COPYRIGHT 2021 BY ICT-HPC CORPORATION ALL RIGHTS RESERVED +// DATE : 2021-01-14 +// AUTHOR : mazhenlong@ncic.ac.cn +// FILENAME : hca_reg2pcie_adapter.sv +// FUNCTION : This file supplies the adapter that transfers r/w of regs to +// pcie pkts. +// +//---------------------------------------------------------------------------- + +//CHANGE HISTORY +//---------------------------------------------------------------------------- +// +// AUTHOR DATE VERSION REASON +// mazhenlong 2021-01-14 v1.0 create +// mazhenlong 2021-04-09 v1.1 add hcr contents generation +// +//---------------------------------------------------------------------------- + +`ifndef __HCA_REG2PCIE_ADAPTER__ +`define __HCA_REG2PCIE_ADAPTER__ +//`include "hca_defines.sv" + +//------------------------------------------------------------------------------ +// +// CLASS: hca_reg2pcie_adapter +// +//------------------------------------------------------------------------------ +class hca_reg2pcie_adapter extends uvm_reg_adapter; + `uvm_object_utils_begin(hca_reg2pcie_adapter) + `uvm_object_utils_end + + //------------------------------------------------------------------------------ + // function name : new + // function : constructor + // invoked : invoked when instantiates the class + //------------------------------------------------------------------------------ + function new(string name = "hca_reg2pcie_adapter"); + super.new(name); + endfunction + + //------------------------------------------------------------------------------ + // function name : reg2bus + // function : transfer register items to pcie items + // invoked : invoked when read or write reg models + //------------------------------------------------------------------------------ + function uvm_sequence_item reg2bus(const ref uvm_reg_bus_op rw); + string test_name; + hca_pcie_item bus; + bus = hca_pcie_item::type_id::create("hca_pcie_item"); + + if (rw.kind == UVM_READ) begin + bus.cq_addr = rw.addr; + bus.cq_addr_type = 0; + bus.cq_attr = 0; // not sure + bus.cq_tc = 0; //not sure + bus.cq_target_function = 0; //not sure + bus.cq_tag = 0; //not sure + bus.cq_bus = 0; //not sure + bus.cq_device = 0; //not sure + bus.cq_req_type = MEM_RD; + bus.cq_dword_count = 7; + bus.is_reg_req = 1; + if (rw.addr == `HCR_BAR_ADDR) begin + bus.cq_bar_id = 0; + bus.cq_bar_aperture = 28; + bus.cq_rd_dw_size = 7; + end + else if (rw.addr >= `DB_BAR_ADDR && rw.addr <= `DB_BAR_ADDR + 8 * 1024 * 1024) begin + bus.cq_bar_id = 2; + bus.cq_bar_aperture = 23; + end + bus.gen_cq_desc(); + end + else if (rw.kind == UVM_WRITE) begin + bus.cq_addr = rw.addr; + bus.cq_addr_type = 0; //not sure + bus.cq_attr = 0; //not sure + bus.cq_tc = 0; //not sure + bus.cq_target_function = 0; //not sure + bus.cq_tag = 0; //not sure + bus.cq_bus = 0; //not sure + bus.cq_req_type = MEM_WR; + bus.cq_dword_count = 7; + bus.is_reg_req = 1; + if (rw.addr == `HCR_BAR_ADDR) begin + bus.cq_bar_id = 0; + bus.cq_bar_aperture = 28; + end + else if (rw.addr >= `DB_BAR_ADDR && rw.addr <= `DB_BAR_ADDR + 8 * 1024 * 1024) begin + bus.cq_bar_id = 2; + bus.cq_bar_aperture = 23; + end + bus.data_payload.push_back({0, rw.data}); + bus.gen_cq_desc(); + + // generate hcr contents + bus.hcr_in_param[63:32] = rw.data[31:0] ; + bus.hcr_in_param[31:0] = rw.data[63:32] ; + bus.hcr_in_modifier = rw.data[95:64] ; + bus.hcr_out_param[63:32] = rw.data[127:96] ; + bus.hcr_out_param[31:0] = rw.data[159:128]; + bus.hcr_token = rw.data[191:176]; + bus.hcr_e = rw.data[214] ; + bus.hcr_go = rw.data[215] ; + bus.hcr_op_modifier = rw.data[211:204]; + bus.hcr_op = rw.data[203:192]; + end + return bus; + endfunction + + //------------------------------------------------------------------------------ + // function name : bus2reg + // function : transfer pcie items to reg items + // invoked : invoked when received read or write requests from DUT + //------------------------------------------------------------------------------ + function void bus2reg(uvm_sequence_item bus_item, ref uvm_reg_bus_op rw); + hca_pcie_item bus; + if (!$cast(bus, bus_item)) begin + `uvm_fatal("CAST_FAILED", "Failed to cast bus_item to bus!"); + return; + end + if (bus.cq_req_type == MEM_RD) begin + rw.kind = UVM_READ; + rw.addr = {bus.cq_addr, 2'b0}; + rw.data = bus.data_payload.pop_front(); + rw.status = UVM_IS_OK; + end + endfunction: bus2reg +endclass +`endif diff --git a/ETH-PLUS_Jingzhao/JingZhao2/verification/src/vrf_HTN/sv/master/regs/hca_reg_block_db.sv b/ETH-PLUS_Jingzhao/JingZhao2/verification/src/vrf_HTN/sv/master/regs/hca_reg_block_db.sv new file mode 100644 index 0000000000000000000000000000000000000000..5c67ba2a1af1dcc971feb27feafe4aa47d2eb72c --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/verification/src/vrf_HTN/sv/master/regs/hca_reg_block_db.sv @@ -0,0 +1,111 @@ +//CREATE INFORMATION +//---------------------------------------------------------------------------- +// +// (C) COPYRIGHT 2021 BY ICT-HPC CORPORATION ALL RIGHTS RESERVED +// DATE : 2021-01-12 +// AUTHOR : mazhenlong@ncic.ac.cn +// FILENAME : hca_reg_block_db.sv +// FUNCTION : This file supplies the function of simulating the registers +// about Doorbell. +// +//---------------------------------------------------------------------------- + +//CHANGE HISTORY +//---------------------------------------------------------------------------- +// +// AUTHOR DATE VERSION REASON +// mazhenlong 2021-01-12 v1.0 create +// +//---------------------------------------------------------------------------- + +`ifndef __HCA_REG_BLOCK_DB__ +`define __HCA_REG_BLOCK_DB__ +typedef class reg_db; + +//------------------------------------------------------------------------------ +// +// CLASS: hca_reg_block_db +// +//------------------------------------------------------------------------------ +class hca_reg_block_db extends uvm_reg_block; + `uvm_object_utils(hca_reg_block_db) + int user_num; + reg_db reg_db_inst; + + //------------------------------------------------------------------------------ + // function name : new + // function : constructor + // invoked : invoked when instantiates the class + //------------------------------------------------------------------------------ + function new(string name = "reg_block_db"); + super.new(name, UVM_NO_COVERAGE); + endfunction: new + + //------------------------------------------------------------------------------ + // function name : build + // function : create regs, configure regs, build regs and map regs + // invoked : invoked by user + //------------------------------------------------------------------------------ + virtual function void build(); + int i; + // create default map + default_map = create_map("default_map", 0, 256, UVM_BIG_ENDIAN, 1); + // !!!probable to recycle memory space!!! + for (i = 0; i < `MAX_PROC_NUM; i++) begin + // create registers + reg_db_inst = reg_db::type_id::create($sformatf("doorbell%0d", i)); + // configure registers + reg_db_inst.configure(this, null, ""); + // build registers + reg_db_inst.build(); + // add registers to default map + default_map.add_reg(reg_db_inst, 'h18 + `PAGE_SIZE * i, "RW"); + end + endfunction: build +endclass: hca_reg_block_db + +//------------------------------------------------------------------------------ +// +// CLASS: reg_db +// +//------------------------------------------------------------------------------ +class reg_db extends uvm_reg; + `uvm_object_utils(reg_db) + rand uvm_reg_field nreq; + rand uvm_reg_field sq_head; + rand uvm_reg_field f0; + rand uvm_reg_field opcode; + rand uvm_reg_field qp_num; + rand uvm_reg_field size0; + + //------------------------------------------------------------------------------ + // function name : new + // function : constructor + // invoked : invoked when instantiates the class + //------------------------------------------------------------------------------ + function new(string name = "reg_db"); + super.new(name, 64, UVM_NO_COVERAGE); + endfunction: new + + //------------------------------------------------------------------------------ + // function name : build + // function : create fields, configure fields + // invoked : invoked by user + //------------------------------------------------------------------------------ + virtual function void build(); + nreq = uvm_reg_field::type_id::create("nreq"); + sq_head = uvm_reg_field::type_id::create("sq_head"); + f0 = uvm_reg_field::type_id::create("f0"); + opcode = uvm_reg_field::type_id::create("opcode"); + qp_num = uvm_reg_field::type_id::create("qp_num"); + size0 = uvm_reg_field::type_id::create("size0"); + // parameters: parent, size, lsb pos, access, volatile, reset value, has reset, is rand, individually accessible + // nreq.configure(this, 8, 0, "RW", 0, 0, 1, 0, 0); + // sq_head.configure(this, 16, 8, "RW", 0, 0, 1, 0, 0); + // f0.configure(this, 1, 29, "RW", 0, 0, 1, 0, 0); + // opcode.configure(this, 5, 24, "RW", 0, 0, 1, 0, 0); + // qp_num.configure(this, 24, 55, "RW", 0, 0, 1, 0, 0); + // size0.configure(this, 8, 56, "RW", 0, 0, 1, 0, 0); + endfunction: build +endclass: reg_db +`endif diff --git a/ETH-PLUS_Jingzhao/JingZhao2/verification/src/vrf_HTN/sv/master/regs/hca_reg_block_hcr.sv b/ETH-PLUS_Jingzhao/JingZhao2/verification/src/vrf_HTN/sv/master/regs/hca_reg_block_hcr.sv new file mode 100644 index 0000000000000000000000000000000000000000..231aeba3a003dfe57e53614def6425313cc32845 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/verification/src/vrf_HTN/sv/master/regs/hca_reg_block_hcr.sv @@ -0,0 +1,154 @@ +//CREATE INFORMATION +//---------------------------------------------------------------------------- +// +// (C) COPYRIGHT 2021 BY ICT-HPC CORPORATION ALL RIGHTS RESERVED +// DATE : 2021-01-13 +// AUTHOR : mazhenlong@ncic.ac.cn +// FILENAME : hca_reg_block_hcr.sv +// FUNCTION : This file supplies the function of simulating the HCR register. +// +//---------------------------------------------------------------------------- + +//CHANGE HISTORY +//---------------------------------------------------------------------------- +// +// AUTHOR DATE VERSION REASON +// mazhenlong 2021-01-13 v1.0 create +// +//---------------------------------------------------------------------------- + +`ifndef __HCA_REG_BLOCK_HCR__ +`define __HCA_REG_BLOCK_HCR__ +typedef class reg_hcr; + +//------------------------------------------------------------------------------ +// +// CLASS: hca_reg_block_hcr +// +//------------------------------------------------------------------------------ +class hca_reg_block_hcr extends uvm_reg_block; + `uvm_object_utils(hca_reg_block_hcr) + + reg_hcr reg_hcr_inst; + + //------------------------------------------------------------------------------ + // function name : new + // function : constructor + // invoked : invoked when instantiates the class + //------------------------------------------------------------------------------ + function new(string name = "hcr_reg_block_hcr"); + super.new(name, UVM_NO_COVERAGE); + endfunction: new + + //------------------------------------------------------------------------------ + // function name : build + // function : create fields, configure fields + // invoked : invoked by user + //------------------------------------------------------------------------------ + virtual function void build(); + // create default map + // | name | base address | system bus byte width | big/little endian | byte address enable| + default_map = create_map("default_map", 64'h0000_0000_0008_0000, 32, UVM_BIG_ENDIAN, 1); + // create registers + reg_hcr_inst = reg_hcr::type_id::create("reg_hcr"); + // configure registers + reg_hcr_inst.configure(this, null, ""); + // build registers + reg_hcr_inst.build(); + // add registers to default_map + default_map.add_reg(reg_hcr_inst, 0, "RW"); + endfunction: build +endclass: hca_reg_block_hcr + +//------------------------------------------------------------------------------ +// +// CLASS: hca_reg_block_hcr +// +//------------------------------------------------------------------------------ +class reg_hcr extends uvm_reg; + `uvm_object_utils(reg_hcr) + rand uvm_reg_field in_param; + rand uvm_reg_field in_modifier; + rand uvm_reg_field out_param; + rand uvm_reg_field token; + rand uvm_reg_field status; + rand uvm_reg_field go; + rand uvm_reg_field e; + rand uvm_reg_field op_modifier_a; + rand uvm_reg_field op_modifier_b; + rand uvm_reg_field op_a; + rand uvm_reg_field op_b; + + rand uvm_reg_field op_modifier; + rand uvm_reg_field op; + + //------------------------------------------------------------------------------ + // function name : new + // function : constructor + // invoked : invoked when instantiates the class + //------------------------------------------------------------------------------ + function new(string name = "reg_hcr"); + // | reg name | reg width | coverage | + super.new(name, 224, UVM_NO_COVERAGE); + endfunction: new + + //------------------------------------------------------------------------------ + // function name : build + // function : create fields, configure fields + // invoked : invoked by user + //------------------------------------------------------------------------------ + virtual function void build(); + // create fields + in_param = uvm_reg_field::type_id::create("in_param"); + in_modifier = uvm_reg_field::type_id::create("in_modifier"); + out_param = uvm_reg_field::type_id::create("out_param"); + token = uvm_reg_field::type_id::create("token"); + status = uvm_reg_field::type_id::create("status"); + go = uvm_reg_field::type_id::create("go"); + e = uvm_reg_field::type_id::create("e"); + op_modifier_a = uvm_reg_field::type_id::create("op_modifier_a"); + op_modifier_b = uvm_reg_field::type_id::create("op_modifier_b"); + op_a = uvm_reg_field::type_id::create("op_a"); + op_b = uvm_reg_field::type_id::create("op_b"); + + op_modifier = uvm_reg_field::type_id::create("op_modifier"); + op = uvm_reg_field::type_id::create("op"); + + + + // configure fields + in_param.configure(this, 64, 0, "RW", 0, 0, 1, 0, 0); + in_modifier.configure(this, 32, 64, "RW", 0, 0, 1, 0, 0); + out_param.configure(this, 64, 96, "RW", 0, 0, 1, 0, 0); + token.configure(this, 16, 168, "RW", 0, 0, 1, 0, 0); + status.configure(this, 8, 192, "RW", 0, 0, 1, 0, 0); + go.configure(this, 1, 207, "RW", 0, 0, 1, 0, 0); + e.configure(this, 1, 206, "RW", 0, 0, 1, 0, 0); + op_modifier_a.configure(this, 4, 200, "RW", 0, 0, 1, 0, 0); + op_modifier_b.configure(this, 4, 212, "RW", 0, 0, 1, 0, 0); + op_a.configure(this, 4, 208, "RW", 0, 0, 1, 0, 0); + op_b.configure(this, 8, 216, "RW", 0, 0, 1, 0, 0); + + // in_param.configure(this, 64, 0, "RW", 0, 0, 1, 0, 0); + // in_modifier.configure(this, 32, 64, "RW", 0, 0, 1, 0, 0); + // out_param.configure(this, 64, 96, "RW", 0, 0, 1, 0, 0); + // token.configure(this, 16, 160, "RW", 0, 0, 1, 0, 0); + // status.configure(this, 8, 192, "RW", 0, 0, 1, 0, 0); + // go.configure(this, 1, 207, "RW", 0, 0, 1, 0, 0); + // e.configure(this, 1, 206, "RW", 0, 0, 1, 0, 0); + // op_modifier.configure(this, 8, 200, "RW", 0, 0, 1, 0, 0); + // op.configure(this, 12, 208, "RW", 0, 0, 1, 0, 0); + + // in_param.configure(this, 64, 56, "RW", 0, 0, 1, 0, 0); + // in_modifier.configure(this, 32, 88, "RW", 0, 0, 1, 0, 0); + // out_param.configure(this, 64, 152, "RW", 0, 0, 1, 0, 0); + // token.configure(this, 16, 168, "RW", 0, 0, 1, 0, 0); + + // status.configure(this, 8, 192, "RW", 0, 0, 1, 0, 0); + // go.configure(this, 1, 207, "RW", 0, 0, 1, 0, 0); + // e.configure(this, 1, 206, "RW", 0, 0, 1, 0, 0); + // op_modifier.configure(this, 8, 212, "RW", 0, 0, 1, 0, 0); + // op.configure(this, 12, 216, "RW", 0, 0, 1, 0, 0); + endfunction: build +endclass: reg_hcr +`endif diff --git a/ETH-PLUS_Jingzhao/JingZhao2/verification/src/vrf_HTN/sv/sequence/hca_comm_sequence.sv b/ETH-PLUS_Jingzhao/JingZhao2/verification/src/vrf_HTN/sv/sequence/hca_comm_sequence.sv new file mode 100644 index 0000000000000000000000000000000000000000..9aae499c0d4a003485cf85db507598e83c93f67d --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/verification/src/vrf_HTN/sv/sequence/hca_comm_sequence.sv @@ -0,0 +1,93 @@ +//CREATE INFORMATION +//---------------------------------------------------------------------------- +// +// (C) COPYRIGHT 2021 BY ICT-HPC CORPORATION ALL RIGHTS RESERVED +// DATE : 2021-06-25 +// AUTHOR : mazhenlong@ncic.ac.cn +// FILENAME : hca_comm_sequence.sv +// FUNCTION : This file supplies the sequence of communication verification. +// +//---------------------------------------------------------------------------- + +//CHANGE HISTORY +//---------------------------------------------------------------------------- +// +// AUTHOR DATE VERSION REASON +// mazhenlong 2021-06-25 v1.0 create +// +//---------------------------------------------------------------------------- + +`ifndef __HCA_COMM_SEQUENCE__ +`define __HCA_COMM_SEQUENCE__ + +//------------------------------------------------------------------------------ +// +// CLASS: hca_comm_sequence +// +//------------------------------------------------------------------------------ +class hca_comm_sequence extends uvm_sequence #(hca_pcie_item); + hca_pcie_item comm_item_que[$]; + hca_pcie_item comm_item; + + string seq_name; + + `uvm_object_utils(hca_comm_sequence) + + //------------------------------------------------------------------------------ + // function name : new + // function : constructor + // invoked : invoked when instantiates the class + //------------------------------------------------------------------------------ + function new(string name = "hca_comm_sequence"); + super.new(name); + comm_item = hca_pcie_item::type_id::create("comm_item"); + endfunction: new + + //------------------------------------------------------------------------------ + // task name : pre_body + // function : cast the register model passed in to reg_blk_hcr + // invoked : be invoked by uvm + //------------------------------------------------------------------------------ + virtual task pre_body(); + // $cast(reg_blk_hcr, model); + endtask: pre_body + + //------------------------------------------------------------------------------ + // task name : body + // function : generate pcie items + // invoked : invoked by uvm automatically + //------------------------------------------------------------------------------ + task body(); + bit [`DATA_WIDTH-1 : 0] temp_data; + bit cmd_result; + // get case name + // if (!$value$plusargs("HCA_CASE_NAME=%s", seq_name)) begin + // `uvm_warning("hca_comm_sequence", "HCA_CASE_NAME not get!") + // end + while (comm_item_que.size != 0) begin + comm_item = comm_item_que.pop_front(); + start_item(comm_item); + // set descriptor + comm_item.cq_addr = `DB_BAR_ADDR + {comm_item.db.proc_id, 12'b0}; + comm_item.cq_addr_type = 0; //not sure + comm_item.cq_attr = 0; //not sure + comm_item.cq_tc = 0; //not sure + comm_item.cq_target_function = 0; //not sure + comm_item.cq_tag = 0; //not sure + comm_item.cq_bus = 0; //not sure + comm_item.cq_req_type = MEM_WR; + comm_item.cq_dword_count = 2; // WARNING: should be modified! + comm_item.cq_bar_id = `DB_BAR_ID; + comm_item.cq_bar_aperture = 22; + comm_item.item_type = DOORBELL; + temp_data = { + {192'b0}, + {comm_item.db.qp_num, comm_item.db.size0}, + {comm_item.db.nreq, comm_item.db.sq_head, 2'b0, comm_item.db.f0, comm_item.db.opcode}}; + comm_item.data_payload.push_back(temp_data); + `uvm_info("NOTICE", $sformatf("input doorbell: %h", temp_data), UVM_LOW); + finish_item(comm_item); + end + endtask: body +endclass: hca_comm_sequence +`endif \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/verification/src/vrf_HTN/sv/sequence/hca_config_sequence.sv b/ETH-PLUS_Jingzhao/JingZhao2/verification/src/vrf_HTN/sv/sequence/hca_config_sequence.sv new file mode 100644 index 0000000000000000000000000000000000000000..e57969d920cc621868ea2ae5b14107fd3b05e9d4 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/verification/src/vrf_HTN/sv/sequence/hca_config_sequence.sv @@ -0,0 +1,523 @@ +//CREATE INFORMATION +//---------------------------------------------------------------------------- +// +// (C) COPYRIGHT 2021 BY ICT-HPC CORPORATION ALL RIGHTS RESERVED +// DATE : 2021-03-26 +// AUTHOR : mazhenlong@ncic.ac.cn +// FILENAME : hca_config_sequence.sv +// FUNCTION : This file supplies the sequence of configuration verification. +// +//---------------------------------------------------------------------------- + +//CHANGE HISTORY +//---------------------------------------------------------------------------- +// +// AUTHOR DATE VERSION REASON +// mazhenlong 2021-03-26 v1.0 create +// mazhenlong 2021-04-06 v1.1 add gen_inbox +// mazhenlong 2021-05-10 v1.2 change class type from uvm_reg_sequence +// to uvm_sequence and delete register model +// mazhenlong 2021-07-23 v1.3 optimize code, split large functions and +// tasks +// +//---------------------------------------------------------------------------- + +`ifndef __HCA_CONFIG_SEQUENCE__ +`define __HCA_CONFIG_SEQUENCE__ + +//------------------------------------------------------------------------------ +// +// CLASS: hca_config_sequence +// +//------------------------------------------------------------------------------ +class hca_config_sequence extends uvm_sequence #(hca_pcie_item); + // hca_reg_block_hcr reg_blk_hcr; + hca_pcie_item cfg_item_que[$]; + hca_pcie_item cfg_item; + // uvm_tlm_analysis_fifo #(hca_pcie_item) cfg_fifo; + hca_memory mem; + hca_fifo #(.width(256)) data_fifo; + string seq_name; + + mailbox cmd_done; + + // addr temp_virt_addr; + // addr temp_phys_addr; + + `uvm_object_utils(hca_config_sequence) + + //------------------------------------------------------------------------------ + // function name : new + // function : constructor + // invoked : invoked when instantiates the class + //------------------------------------------------------------------------------ + function new(string name = "hca_config_sequence"); + super.new(name); + // cfg_item = hca_pcie_item::type_id::create("cfg_item"); + data_fifo = hca_fifo#(.width(256))::type_id::create("data_fifo"); + // cfg_fifo = new("cfg_fifo"); + endfunction: new + + //------------------------------------------------------------------------------ + // task name : pre_body + // function : cast the register model passed in to reg_blk_hcr + // invoked : be invoked by uvm + //------------------------------------------------------------------------------ + virtual task pre_body(); + // get case name + if(!uvm_config_db#(mailbox)::get(null, get_full_name(), "mbx_cmd_done", cmd_done)) begin + `uvm_fatal("NO_MBX", $sformatf("mailbox not get in config_sequence! full name: %s, m_sequencer: %s.", get_full_name(), m_sequencer.get_full_name())); + end + endtask: pre_body + + //------------------------------------------------------------------------------ + // task name : body + // function : generate pcie items + // invoked : invoked by uvm automatically + //------------------------------------------------------------------------------ + task body(); + bit [`DATA_WIDTH-1 : 0] temp_data; + bit cmd_result; + while (cfg_item_que.size() != 0) begin + `uvm_info("NOTICE", "processing config item in config sequence", UVM_LOW); + cfg_item = cfg_item_que.pop_front(); + `uvm_info("NOTICE", "config item got in config sequence", UVM_LOW); + start_item(cfg_item); + if (cfg_item.item_type == HCR) begin + `uvm_info("ITEM_INFO", "HCR item received in config sequence", UVM_LOW); + // print_begin_info(cfg_item); + write_inbox(cfg_item); + set_cq_payload(cfg_item); + finish_item(cfg_item); + + // synchronize with master driver and DUT, wati until clear + cmd_done.get(cmd_result); + end + else if (cfg_item.item_type == GLOBAL_STOP) begin + `uvm_info("ITEM_INFO", "GLOBAL_STOP item received by config sequence!", UVM_LOW); + finish_item(cfg_item); + end + else if (cfg_item.item_type == INTR) begin + `uvm_info("ITEM_INFO", "INTR item received by config sequence!", UVM_LOW); + finish_item(cfg_item); + + end + else begin + `uvm_fatal("ITEM_TYP_ERR", $sformatf("Illegal cfg_item type! item_type: %h.", cfg_item.item_type)); + end + end + `uvm_info("NOTICE", "cfg_item finished in config_sequence!", UVM_LOW); + endtask: body + + task write_inbox(hca_pcie_item item); + bit [256/`BYTE_BIT_WIDTH-1:0][`BYTE_BIT_WIDTH-1:0] inbox_data; + hca_pcie_item temp_item; + temp_item = hca_pcie_item::type_id::create("temp_item"); + temp_item.copy(item); + temp_item.copy_struct(item); + data_fifo.clean(); + + case (temp_item.hcr_op) + `CMD_INIT_HCA: begin + for (int i = 0; i < 8; i++) begin + inbox_data[i] = 0; + end + for (int i = 0; i < 7; i++) begin + inbox_data[i + 8] = temp_item.icm_base_struct.qpc_base[63 - i * 8 -: 8]; // big endian + end + inbox_data[15] = temp_item.icm_base_struct.log_num_qps; + for (int i = 0; i < 7; i++) begin + inbox_data[i + 16] = temp_item.icm_base_struct.cqc_base[63 - i * 8 -: 8]; + end + inbox_data[23] = temp_item.icm_base_struct.log_num_cqs; + for (int i = 0; i < 7; i++) begin + inbox_data[i + 24] = temp_item.icm_base_struct.eqc_base[63 - i * 8 -: 8]; + end + inbox_data[31] = temp_item.icm_base_struct.log_num_eqs; // DW full + data_fifo.push(inbox_data); + inbox_data = 0; + + for (int i = 0; i < 16; i++) begin + inbox_data[i] = 0; + end + for (int i = 0; i < 7; i++) begin + inbox_data[i + 16] = temp_item.icm_base_struct.mpt_base[63 - i * 8 -: 8]; + end + inbox_data[23] = temp_item.icm_base_struct.log_mpt_sz; + for (int i = 0; i < 8; i++) begin // ?? + inbox_data[i + 24] = temp_item.icm_base_struct.mtt_base[63 - i * 8 -: 8]; + end + data_fifo.push(inbox_data); + inbox_data = 0; + end + `CMD_MAP_ICM: begin + // warning: not support multichunk + bit [63:0] temp; + for (int i = 0; i < 16; i++) begin + inbox_data[i] = 0; + end + + temp = temp_item.icm_addr_map.virt.pop_front(); + for (int i = 0; i < 8; i++) begin + inbox_data[i + 16] = temp[63 - i * 8 -: 8]; + end + + temp = temp_item.icm_addr_map.page.pop_front(); + for (int i = 0; i < 6; i++) begin + inbox_data[i + 24] = temp[63 - i * 8 -: 8]; + end + + inbox_data[30] = {temp[15:12], temp_item.icm_addr_map.page_num[11:8]}; + inbox_data[31] = temp_item.icm_addr_map.page_num[7:0]; + data_fifo.push(inbox_data); + end + `CMD_RST2INIT_QPEE , + `CMD_INIT2RTR_QPEE , + `CMD_RTR2RTS_QPEE , + `CMD_RTS2RTS_QPEE , + `CMD_SQERR2RTS_QPEE , + `CMD_2ERR_QPEE , + `CMD_RTS2SQD_QPEE , + `CMD_SQD2SQD_QPEE , + `CMD_SQD2RTS_QPEE , + `CMD_INIT2INIT_QPEE: begin + for (int i = 0; i < 4; i++) begin + inbox_data[i] = temp_item.qp_ctx.opt_param_mask[31 - i * 8 -: 8]; + end + for (int i = 0; i < 4; i++) begin + inbox_data[i + 4] = 0; + end + for (int i = 0; i < 4; i++) begin + inbox_data[i + 8] = temp_item.qp_ctx.flags[31 - i * 8 -: 8]; + end + inbox_data[12] = temp_item.qp_ctx.mtu_msgmax; + inbox_data[13] = temp_item.qp_ctx.rq_entry_sz_log; + inbox_data[14] = temp_item.qp_ctx.sq_entry_sz_log; + inbox_data[15] = temp_item.qp_ctx.rlkey_arbel_sched_queue; + for (int i = 0; i < 4; i++) begin + inbox_data[i + 16] = temp_item.qp_ctx.usr_page[31 - i * 8 -: 8]; + end + for (int i = 0; i < 4; i++) begin + inbox_data[i + 20] = temp_item.qp_ctx.local_qpn[31 - i * 8 -: 8]; + end + for (int i = 0; i < 4; i++) begin + inbox_data[i + 24] = temp_item.qp_ctx.remote_qpn[31 - i * 8 -: 8]; + end + for (int i = 0; i < 4; i++) begin + inbox_data[i + 28] = temp_item.qp_ctx.port_pkey[31 - i * 8 -: 8]; + end + data_fifo.push(inbox_data); + inbox_data = 0; + + inbox_data[0] = temp_item.qp_ctx.rnr_retry; + inbox_data[1] = temp_item.qp_ctx.g_mylmc; + inbox_data[2] = 0; // temp_item.qp_ctx.rlid[15:8]; + inbox_data[3] = 0; // temp_item.qp_ctx.rlid[7:0]; + inbox_data[4] = temp_item.qp_ctx.ackto; + inbox_data[5] = temp_item.qp_ctx.mgid_index; + inbox_data[6] = temp_item.qp_ctx.static_rate; + inbox_data[7] = temp_item.qp_ctx.hop_limit; + for (int i = 0; i < 4; i++) begin + inbox_data[i + 8] = temp_item.qp_ctx.sl_tclass_flowlabel[31 - i * 8 -: 8]; + end + for (int i = 0; i < 16; i++) begin + inbox_data[i + 12] = temp_item.qp_ctx.rgid[127 - i * 8 -: 8]; + end + inbox_data[28] = temp_item.qp_ctx.dmac[15:8]; + inbox_data[29] = temp_item.qp_ctx.dmac[7:0]; + inbox_data[30] = temp_item.qp_ctx.smac[15:8]; + inbox_data[31] = temp_item.qp_ctx.smac[7:0]; + data_fifo.push(inbox_data); + inbox_data = 0; + + for (int i = 0; i < 4; i++) begin + inbox_data[i] = temp_item.qp_ctx.smac[47 - i * 8 -: 8]; + end + for (int i = 0; i < 4; i++) begin + inbox_data[i + 4] = temp_item.qp_ctx.dmac[47 - i * 8 -: 8]; + end + for (int i = 0; i < 4; i++) begin + inbox_data[i + 8] = temp_item.qp_ctx.sip[31 - i * 8 -: 8]; + end + for (int i = 0; i < 4; i++) begin + inbox_data[i + 12] = temp_item.qp_ctx.dip[31 - i * 8 -: 8]; + end + for (int i = 0; i < 12; i++) begin + inbox_data[i + 16] = 0; + end + for (int i = 0; i < 4; i++) begin + inbox_data[i + 28] = temp_item.qp_ctx.pd[31 - i * 8 -: 8]; + end + data_fifo.push(inbox_data); + inbox_data = 0; + + for (int i = 0; i < 4; i++) begin + inbox_data[i] = temp_item.qp_ctx.wqe_base[31 - i * 8 -: 8]; + end + for (int i = 0; i < 4; i++) begin + inbox_data[i + 4] = temp_item.qp_ctx.wqe_lkey[31 - i * 8 -: 8]; + end + for (int i = 0; i < 4; i++) begin + inbox_data[i + 8] = 0; + end + for (int i = 0; i < 4; i++) begin + inbox_data[i + 12] = temp_item.qp_ctx.next_send_psn[31 - i * 8 -: 8]; + end + for (int i = 0; i < 4; i++) begin + inbox_data[i + 16] = temp_item.qp_ctx.cqn_snd[31 - i * 8 -: 8]; + end + for (int i = 0; i < 4; i++) begin + inbox_data[i + 20] = temp_item.qp_ctx.snd_wqe_base_l[31 - i * 8 -: 8]; + end + for (int i = 0; i < 4; i++) begin + inbox_data[i + 24] = temp_item.qp_ctx.snd_wqe_len[31 - i * 8 -: 8]; + end + for (int i = 0; i < 4; i++) begin + inbox_data[i + 28] = temp_item.qp_ctx.last_acked_psn[31 - i * 8 -: 8]; + end + data_fifo.push(inbox_data); + inbox_data = 0; + + for (int i = 0; i < 4; i++) begin + inbox_data[i] = temp_item.qp_ctx.ssn[31 - i * 8 -: 8]; + end + for (int i = 0; i < 4; i++) begin + inbox_data[i + 4] = temp_item.qp_ctx.rnr_nextrecvpsn[31 - i * 8 -: 8]; + end + for (int i = 0; i < 4; i++) begin + inbox_data[i + 8] = temp_item.qp_ctx.ra_buff_indx[31 - i * 8 -: 8]; + end + for (int i = 0; i < 4; i++) begin + inbox_data[i + 12] = temp_item.qp_ctx.cqn_rcv[31 - i * 8 -: 8]; + end + for (int i = 0; i < 4; i++) begin + inbox_data[i + 16] = temp_item.qp_ctx.rcv_wqe_base_l[31 - i * 8 -: 8]; + end + for (int i = 0; i < 4; i++) begin + inbox_data[i + 20] = temp_item.qp_ctx.rcv_wqe_len[31 - i * 8 -: 8]; + end + for (int i = 0; i < 4; i++) begin + inbox_data[i + 24] = temp_item.qp_ctx.qkey[31 - i * 8 -: 8]; + end + for (int i = 0; i < 4; i++) begin + inbox_data[i + 28] = temp_item.qp_ctx.rmsn[31 - i * 8 -: 8]; + end + data_fifo.push(inbox_data); + inbox_data = 0; + + for (int i = 0; i < 28; i++) begin + inbox_data[i] = 0; + end + inbox_data[28] = temp_item.qp_ctx.rq_wqe_counter[15:8]; + inbox_data[29] = temp_item.qp_ctx.rq_wqe_counter[7:0]; + inbox_data[30] = temp_item.qp_ctx.sq_wqe_counter[15:8]; + inbox_data[31] = temp_item.qp_ctx.sq_wqe_counter[7:0]; + data_fifo.push(inbox_data); + inbox_data = 0; + end + `CMD_WRITE_MTT: begin + int beat_num; + addr temp_phys_addr; + data_fifo.clean(); + // calculate beat num + if (temp_item.inbox_size % 256 == 0) begin + beat_num = temp_item.inbox_size / 256; + end + else begin + beat_num = temp_item.inbox_size / 256 + 1; + end + + for (int j = 0; j < beat_num; j++) begin + // write start index + if (j == 0) begin + for (int i = 0; i < 24; i++) begin + inbox_data[i] = 0; + end + for (int i = 0; i < 8; i++) begin + inbox_data[i + 24] = temp_item.mtt_item.start_index[63 - i * 8 -: 8]; + end + data_fifo.push(inbox_data); + inbox_data = 0; + end + else begin + for (int i = 0; i < 4; i++) begin + if (temp_item.mtt_item.phys_addr.size() != 0) begin + temp_phys_addr = temp_item.mtt_item.phys_addr.pop_front(); + for (int k = 0; k < 8; k++) begin + inbox_data[24 - 8 * i + k] = temp_phys_addr[63 - k * 8 -: 8]; + end + end + else begin + break; + end + end + data_fifo.push(inbox_data); + inbox_data = 0; + end + end + end + `CMD_SW2HW_MPT: begin + for (int i = 0; i < 4; i++) begin + inbox_data[i] = temp_item.mpt_item.flags[31 - i * 8 -: 8]; + end + for (int i = 0; i < 4; i++) begin + inbox_data[i + 4] = temp_item.mpt_item.page_size[31 - i * 8 -: 8]; + end + for (int i = 0; i < 4; i++) begin + inbox_data[i + 8] = temp_item.mpt_item.key[31 - i * 8 -: 8]; + end + for (int i = 0; i < 4; i++) begin + inbox_data[i + 12] = temp_item.mpt_item.pd[31 - i * 8 -: 8]; + end + for (int i = 0; i < 8; i++) begin + inbox_data[i + 16] = temp_item.mpt_item.start[63 - i * 8 -: 8]; + end + for (int i = 0; i < 8; i++) begin + inbox_data[i + 24] = temp_item.mpt_item.length[63 - i * 8 -: 8]; + end + data_fifo.push(inbox_data); + inbox_data = 0; + for (int i = 0; i < 4; i++) begin + inbox_data[i] = temp_item.mpt_item.lkey[31 - i * 8 -: 8]; + end + for (int i = 0; i < 4; i++) begin + inbox_data[i + 4] = temp_item.mpt_item.window_count[31 - i * 8 -: 8]; + end + for (int i = 0; i < 4; i++) begin + inbox_data[i + 8] = temp_item.mpt_item.window_count_limit[31 - i * 8 -: 8]; + end + for (int i = 0; i < 8; i++) begin + inbox_data[i + 12] = temp_item.mpt_item.mtt_seg[63 - i * 8 -: 8]; + end + for (int i = 0; i < 4; i++) begin + inbox_data[i + 20] = temp_item.mpt_item.mtt_sz[31 - i * 8 -: 8]; + end + data_fifo.push(inbox_data); + inbox_data = 0; + end + `CMD_SW2HW_CQ: begin + for (int i = 0; i < 4; i++) begin + inbox_data[i] = temp_item.cq_ctx.flags[31 - i * 8 -: 8]; + end + for (int i = 0; i < 8; i++) begin + inbox_data[i + 4] = temp_item.cq_ctx.start[63 - i * 8 -: 8]; + end + inbox_data[12] = temp_item.cq_ctx.logsize; + for (int i = 0; i < 3; i++) begin + inbox_data[i + 13] = temp_item.cq_ctx.usrpage[23 - i * 8 -: 8]; + end + for (int i = 0; i < 4; i++) begin + inbox_data[i + 16] = temp_item.cq_ctx.comp_eqn[31 - i * 8 -: 8]; + end + for (int i = 0; i < 4; i++) begin + inbox_data[i + 20] = temp_item.cq_ctx.pd[31 - i * 8 -: 8]; + end + for (int i = 0; i < 4; i++) begin + inbox_data[i + 24] = temp_item.cq_ctx.lkey[31 - i * 8 -: 8]; + end + for (int i = 0; i < 4; i++) begin + inbox_data[i + 28] = 0; + end + data_fifo.push(inbox_data); + inbox_data = 0; + + for (int i = 0; i < 12; i++) begin + inbox_data[i] = 0; + end + for (int i = 0; i < 4; i++) begin + inbox_data[i + 12] = temp_item.cq_ctx.cqn[31 - i * 8 -: 8]; + end + for (int i = 0; i < 16; i++) begin + inbox_data[i + 16] = 0; + end + data_fifo.push(inbox_data); + end + endcase + + // write content in data_fifo into inbox + if (temp_item.inbox_size != 0 ) begin + mem.write_block(`INBOX_ADDR, data_fifo, temp_item.inbox_size); + end + endtask: write_inbox + + task set_cq_payload(hca_pcie_item item); + // set cq descriptor and data_payload, which will become cq_tdata + bit [`DATA_WIDTH - 1 : 0] temp_data; + item.cq_addr = `HCR_BAR_ADDR; + item.cq_addr_type = 0; //not sure + item.cq_attr = 0; //not sure + item.cq_tc = 0; //not sure + item.cq_target_function = 0; //not sure + item.cq_tag = 0; //not sure + item.cq_bus = 0; //not sure + item.cq_req_type = MEM_WR; + item.cq_dword_count = 7; + item.cq_bar_id = `HCR_BAR_ID; + item.cq_bar_aperture = 28; + temp_data = { + {32'b0}, + {8'b0, item.hcr_go, item.hcr_e, 2'b0, item.hcr_op_modifier, item.hcr_op}, + {item.hcr_token, 16'b0}, + {item.hcr_out_param[31:0]}, + {item.hcr_out_param[63:32]}, + {item.hcr_in_modifier}, + {item.hcr_in_param[31:0]}, + {item.hcr_in_param[63:32]}}; + item.data_payload.push_back(temp_data); + `uvm_info("NOTICE", $sformatf("input hcr: %h", temp_data), UVM_LOW); + endtask: set_cq_payload + + task print_begin_info(hca_pcie_item cfg_item); + case (cfg_item.hcr_op) + `CMD_INIT_HCA: begin + `uvm_info("CMD_BEGIN_NOTICE", "init hca begin!", UVM_LOW); + end + `CMD_CLOSE_HCA: begin + `uvm_info("CMD_BEGIN_NOTICE", "close hca begin!", UVM_LOW); + end + `CMD_QUERY_ADAPTER: begin + `uvm_info("CMD_BEGIN_NOTICE", "query adapter begin!", UVM_LOW); + end + `CMD_QUERY_DEV_LIM: begin + `uvm_info("CMD_BEGIN_NOTICE", "query dev lim begin!", UVM_LOW); + end + `CMD_QUERY_QP: begin + `uvm_info("CMD_BEGIN_NOTICE", "query qp begin!", UVM_LOW); + end + `CMD_MAP_ICM: begin + `uvm_info("CMD_BEGIN_NOTICE", "map icm begin!", UVM_LOW); + end + `CMD_RST2INIT_QPEE, + `CMD_INIT2RTR_QPEE, + `CMD_RTR2RTS_QPEE, + `CMD_RTS2RTS_QPEE, + `CMD_SQERR2RTS_QPEE, + `CMD_2ERR_QPEE, + `CMD_RTS2SQD_QPEE, + `CMD_SQD2SQD_QPEE, + `CMD_SQD2RTS_QPEE, + `CMD_INIT2INIT_QPEE: begin + `uvm_info("CMD_BEGIN_NOTICE", "modify qp begin!", UVM_LOW); + end + `CMD_WRITE_MTT: begin + `uvm_info("CMD_BEGIN_NOTICE", "write mtt begin!", UVM_LOW); + end + `CMD_SW2HW_MPT: begin + `uvm_info("CMD_BEGIN_NOTICE", "sw2hw mpt begin!", UVM_LOW); + end + `CMD_SW2HW_CQ: begin + `uvm_info("CMD_BEGIN_NOTICE", "sw2hw cq begin!", UVM_LOW); + end + default: begin + // if (seq_name != "test_ilg_op") begin + // `uvm_fatal("HCR_OP_ERROR", $sformatf("Illegal hcr opcode! hcr_op: %h", cfg_item.hcr_op)); + // end + // else begin + // `uvm_info("CMD_BEGIN_NOTICE", "test illegal op begin!", UVM_LOW); + // end + `uvm_fatal("HCR_OP_ERROR", $sformatf("Illegal hcr opcode! hcr_op: %h", cfg_item.hcr_op)); + end + endcase + endtask: print_begin_info +endclass: hca_config_sequence +`endif diff --git a/ETH-PLUS_Jingzhao/JingZhao2/verification/src/vrf_HTN/sv/sequence/hca_slave_sequence.sv b/ETH-PLUS_Jingzhao/JingZhao2/verification/src/vrf_HTN/sv/sequence/hca_slave_sequence.sv new file mode 100644 index 0000000000000000000000000000000000000000..ecd5b599364758e9506e1760bc0622f4413b4e51 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/verification/src/vrf_HTN/sv/sequence/hca_slave_sequence.sv @@ -0,0 +1,350 @@ +//CREATE INFORMATION +//---------------------------------------------------------------------------- +// +// (C) COPYRIGHT 2021 BY ICT-HPC CORPORATION ALL RIGHTS RESERVED +// DATE : 2021-04-22 +// AUTHOR : mazhenlong@ncic.ac.cn +// FILENAME : hca_slave_sequence.sv +// FUNCTION : This file supplies the sequence of slave side in verification, +// including send DMA read response. +// +//---------------------------------------------------------------------------- + +//CHANGE HISTORY +//---------------------------------------------------------------------------- +// +// AUTHOR DATE VERSION REASON +// mazhenlong 2021-04-22 v1.0 create +// mazhenlong 2021-04-29 v1.1 add processing logic for +// mem write +// +//---------------------------------------------------------------------------- + +`ifndef __HCA_SLAVE_SEQUENCE__ +`define __HCA_SLAVE_SEQUENCE__ + +//------------------------------------------------------------------------------ +// +// CLASS: hca_slave_sequence +// +//------------------------------------------------------------------------------ + +class hca_slave_sequence extends uvm_sequence #(hca_pcie_item); + hca_memory mem; + hca_fifo #(`MEM_LINE_SIZE) fifo; + // hca_pcie_item received_item; + hca_pcie_item sent_item; + int max_payload_size; + int max_read_req_size; + // virtual hca_interface v_if; + bit stop = 0; + hca_queue_list q_list; + int host_id; + + bit [`MEM_LINE_SIZE-1: 0] temp_data; + + `uvm_object_utils_begin(hca_slave_sequence) + `uvm_object_utils_end + + `uvm_declare_p_sequencer(hca_slave_sequencer) + + //------------------------------------------------------------------------------ + // function name : new + // function : constructor + // invoked : be invoked when instantiates hca_slave_sequence + //------------------------------------------------------------------------------ + function new(string name = "hca_slave_sequence"); + super.new(name); + case(`MAX_PAYLOAD) // write request, not read response + 3'b000: begin + max_payload_size = 128; + end + 3'b010: begin + max_payload_size = 256; + end + 3'b011: begin + max_payload_size = 512; + end + 3'b100: begin + max_payload_size = 1024; + end + 3'b101: begin + max_payload_size = 4096; + end + endcase + + case(`MAX_READ_REQ) + 3'b000: begin + max_read_req_size = 128; + end + 3'b010: begin + max_read_req_size = 256; + end + 3'b011: begin + max_read_req_size = 512; + end + 3'b100: begin + max_read_req_size = 1024; + end + 3'b101: begin + max_read_req_size = 4096; + end + endcase + + // if(!uvm_config_db #(virtual hca_interface)::get(null, get_full_name(), "virtual_if", v_if)) + // `uvm_fatal("NOVIF",{"virtual interface must be set for: ",get_full_name(),".vif"}); + endfunction: new + + virtual task pre_body(); + if(!uvm_config_db#(hca_queue_list)::get(null, get_full_name(), "q_list", q_list)) begin + `uvm_fatal("GET_ERR", $sformatf("q_list not get in slave_sequence! full name: %s, m_sequencer: %s.", get_full_name(), m_sequencer.get_full_name())); + end + endtask: pre_body + + //------------------------------------------------------------------------------ + // function name : body + // function : receive items from sequencer and generate DMA response to DUV. + // invoked : be invoked by uvm + //------------------------------------------------------------------------------ + virtual task body(); + while (1) begin + hca_pcie_item received_item; + `uvm_info("NOTICE", $sformatf("fifo used: %0d", p_sequencer.item_collected_fifo.used()), UVM_HIGH); + p_sequencer.item_collected_fifo.get(received_item); + if (received_item.item_type == GLOBAL_STOP) begin + `uvm_info("NOTICE", "global stop item received in slave sequence!", UVM_LOW); + sent_item = hca_pcie_item::type_id::create("sent_item"); + start_item(sent_item); + sent_item.item_type = GLOBAL_STOP; + finish_item(sent_item); + `uvm_info("NOTICE", "global stop item sent to slave driver!", UVM_LOW); + break; + end + if (received_item.rq_req_type == MEM_RD) begin + int i; + sent_item = hca_pcie_item::type_id::create("sent_item"); + start_item(sent_item); + // `uvm_info("NOTICE", $sformatf("memory read process begin in slave sequence"), UVM_LOW); + + // set rc descriptor field values in sent_item + sent_item.item_type = DMA_RSP; + + // set rc_addr + i = 0; + while (received_item.rq_first_be[i] == 0) begin + i++; + end + sent_item.rc_addr = received_item.rq_addr[11:0] + i; + + sent_item.rc_error_code = 0; // depends on memory read result + sent_item.rc_byte_count = get_byte_count(received_item.rq_dword_count, received_item.rq_first_be, received_item.rq_last_be); + sent_item.rc_locked_read_completion = 0; // if is a resp to a locked read set to 1, otherwise 0 + sent_item.rc_request_completed = 1; // indicates the end of the completions of a request + sent_item.rc_dword_count = received_item.rq_dword_count; + sent_item.rc_completion_status = 3'b000; + sent_item.rc_poisoned_completion = 0; // unclear the use + sent_item.rc_requester_device = received_item.rq_requester_device; + sent_item.rc_requester_bus = received_item.rq_requester_bus; + sent_item.rc_tag = received_item.rq_tag; + sent_item.rc_completer_device = 0; + sent_item.rc_completer_bus = 0; + sent_item.rc_tc = 0; + sent_item.rc_attr = 0; + sent_item.rc_first_be = received_item.rq_first_be; + sent_item.rc_last_be = received_item.rq_last_be; + // read contents from mem + fifo = mem.read_block(received_item.rq_addr, received_item.rq_dword_count * 4); + `uvm_info("NOTICE", $sformatf("mem read finished. addr = %h, dword_count: %h, byte_count: %h, first_be: %h, last_be: %h", + received_item.rq_addr, received_item.rq_dword_count, sent_item.rc_byte_count, sent_item.rc_first_be, sent_item.rc_last_be), UVM_LOW + ); + while (fifo.get_depth() != 0) begin + temp_data = fifo.pop(); + // `uvm_info("NOTICE", $sformatf("read data content: %h", temp_data), UVM_HIGH); + sent_item.data_payload.push_back(temp_data); + end + finish_item(sent_item); + + if (received_item.rq_addr[47:38] == 10'b1) begin + hca_queue_pair qp; + bit [31:0] qpn; + qpn = {18'b0, received_item.rq_addr[37:24]}; + qp = q_list.get_qp(host_id, qpn); + //qp.consume_wqe(received_item.rq_addr[23]); + //`uvm_info("QP_NOTICE", $sformatf("consume WQE, host_id: %0d, addr: %h", host_id, received_item.rq_addr), UVM_LOW); + end + end + else if (received_item.rq_req_type == MEM_WR) begin + // do not need to send response to duv + int length; + addr start_addr; + hca_fifo #(.width(256)) temp_fifo; + temp_fifo = hca_fifo #(.width(256))::type_id::create("temp_fifo"); + while (received_item.data_payload.size() != 0) begin + temp_data = received_item.data_payload.pop_front(); + temp_fifo.push(temp_data); + `uvm_info("NOTICE", $sformatf("write data: %h, addr: %h", temp_data, received_item.rq_addr), UVM_LOW); + end + + // consider last_be and first_be + length = received_item.rq_dword_count * 4; + start_addr = received_item.rq_addr; + // for (int idx = 0; idx < 4; idx++) begin + // if (received_item.rq_first_be[idx] == 0) begin + // start_addr++; + // length--; + // temp_fifo.pop_byte(); + // end + // else begin + // break; + // end + // end + // for (int idx = 0; idx < 4; idx++) begin + // if (received_item.rq_first_be[3 - idx] == 0) begin + + // end + // end + if (check_be(received_item.rq_first_be, received_item.rq_last_be) == 0) begin + `uvm_fatal("BE_ERR", $sformatf("RQ BE error! first_be: %b, last_be: %b", + received_item.rq_first_be, received_item.rq_last_be)); + end + + case (received_item.rq_first_be) + 4'b1111: begin + start_addr = received_item.rq_addr; + length = length; + end + 4'b1110: begin + start_addr = received_item.rq_addr + 1; + temp_fifo.pop_byte(); + length -= 1; + end + 4'b1100: begin + start_addr = received_item.rq_addr + 2; + temp_fifo.pop_byte(); + temp_fifo.pop_byte(); + length -= 2; + end + 4'b1000: begin + start_addr = received_item.rq_addr + 3; + temp_fifo.pop_byte(); + temp_fifo.pop_byte(); + temp_fifo.pop_byte(); + length -= 3; + end + 4'b0001: begin + start_addr = received_item.rq_addr; + length = 1; + end + 4'b0011: begin + start_addr = received_item.rq_addr; + length = 2; + end + 4'b0111: begin + start_addr = received_item.rq_addr; + length = 3; + end + 4'b0110: begin + start_addr = received_item.rq_addr + 1; + length = 2; + temp_fifo.pop_byte(); + end + 4'b0010: begin + start_addr = received_item.rq_addr + 1; + length = 1; + temp_fifo.pop_byte(); + end + 4'b0100: begin + start_addr = received_item.rq_addr + 2; + length = 1; + temp_fifo.pop_byte(); + temp_fifo.pop_byte(); + end + default: begin + `uvm_fatal("BE_ERROR", $sformatf("rq_first_be error: %h", received_item.rq_first_be)); + end + endcase + + case (received_item.rq_last_be) + 4'b1111: begin + length = length; + end + 4'b0111: begin + length -= 1; + end + 4'b0011: begin + length -= 2; + end + 4'b0001: begin + length -= 3; + end + 4'b0000: begin + if (length <= 4) begin + end + else begin + `uvm_fatal("BE_ERROR", $sformatf("rq_last_be error, last be: %h, first be: %h", received_item.rq_last_be, received_item.rq_first_be)); + end + end + default: begin + `uvm_fatal("BE_ERROR", $sformatf("rq_last_be error: %h", received_item.rq_last_be)); + end + endcase + + mem.write_block(start_addr, temp_fifo, length); + end + else begin + `uvm_error("PCIE_REQ_TYPE_ERR", "received item request type illegal in slave sequence!"); + end + end + `uvm_info("GLB_STOP_INFO", "slave sequence body end!", UVM_LOW); + endtask: body + + function int get_byte_count(int dw_cnt, bit [3:0] first_be, bit [3:0] last_be); + int byte_cnt = dw_cnt * 4; + int i = 0; + while (first_be[i] == 0) begin + i++; + end + byte_cnt = byte_cnt - i; + if (last_be == 0) begin + return byte_cnt; + end + else begin + i = 0; + while (last_be[3 - i] == 0) begin + i++; + end + byte_cnt = byte_cnt - i; + return byte_cnt; + end + endfunction: get_byte_count + + function bit check_be(bit [3:0] first_be, bit [3:0] last_be); + bit [7:0] be; + int start = 0; + int last = 7; + be = {last_be, first_be}; + for (int i = 0; i < 8; i++) begin + if (be[i] == 1) begin + start = i; + break; + end + end + for (int i = 0; i < 8; i++) begin + if (be[7 - i] == 1) begin + last = 7 - i; + break; + end + end + for (int i = start; i < last; i++) begin + if (be[i] == 0) begin + return 0; + end + end + + if (first_be == 0) begin + return 0; + end + return 1; + endfunction: check_be +endclass: hca_slave_sequence +`endif diff --git a/ETH-PLUS_Jingzhao/JingZhao2/verification/src/vrf_HTN/sv/sequence/test_db_seq.sv b/ETH-PLUS_Jingzhao/JingZhao2/verification/src/vrf_HTN/sv/sequence/test_db_seq.sv new file mode 100644 index 0000000000000000000000000000000000000000..8a6a363f9c02b04da4b2a54c617ef826b2082dc7 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/verification/src/vrf_HTN/sv/sequence/test_db_seq.sv @@ -0,0 +1,32 @@ +//CREATE INFORMATION +//---------------------------------------------------------------------------- +// +// (C) COPYRIGHT 2021 BY ICT-HPC CORPORATION ALL RIGHTS RESERVED +// DATE : 2021-01-14 +// AUTHOR : mazhenlong@ncic.ac.cn +// FILENAME : test_db_seq.sv +// FUNCTION : This file supplies the task of verifying the doorbell register. +// +//---------------------------------------------------------------------------- + +//CHANGE HISTORY +//---------------------------------------------------------------------------- +// +// AUTHOR DATE VERSION REASON +// mazhenlong 2021-01-14 v1.0 create +// +//---------------------------------------------------------------------------- + +`ifndef __TEST_DB_SEQ__ +`define __TEST_DB_SEQ__ + +//------------------------------------------------------------------------------ +// +// CLASS: test_db_seq +// +//------------------------------------------------------------------------------ +class test_db_seq extends uvm_reg_sequence; + string testname; + +endclass +`endif \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/verification/src/vrf_HTN/sv/sequence/test_hcr_seq.sv b/ETH-PLUS_Jingzhao/JingZhao2/verification/src/vrf_HTN/sv/sequence/test_hcr_seq.sv new file mode 100644 index 0000000000000000000000000000000000000000..d155b39ce7fb963db743830ba070652f9a362ed9 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/verification/src/vrf_HTN/sv/sequence/test_hcr_seq.sv @@ -0,0 +1,83 @@ +//CREATE INFORMATION +//---------------------------------------------------------------------------- +// +// (C) COPYRIGHT 2021 BY ICT-HPC CORPORATION ALL RIGHTS RESERVED +// DATE : 2021-01-14 +// AUTHOR : mazhenlong@ncic.ac.cn +// FILENAME : test_hcr_seq.sv +// FUNCTION : This file supplies the task of verifying the HCR register. +// +//---------------------------------------------------------------------------- + +//CHANGE HISTORY +//---------------------------------------------------------------------------- +// +// AUTHOR DATE VERSION REASON +// mazhenlong 2021-01-14 v1.0 create +// +//---------------------------------------------------------------------------- + +`ifndef __TEST_HCR_SEQ__ +`define __TEST_HCR_SEQ__ + +//------------------------------------------------------------------------------ +// +// CLASS: test_hcr_seq +// +//------------------------------------------------------------------------------ +class test_hcr_seq extends uvm_reg_sequence; + string test_name; + hca_reg_block_hcr reg_block_hcr; + + `uvm_object_utils(test_hcr_seq) + + //------------------------------------------------------------------------------ + // function name : new + // function : constructor + // invoked : invoked when instantiates the class + //------------------------------------------------------------------------------ + function new(string name = "test_hcr_seq"); + super.new(name); + endfunction: new + + //------------------------------------------------------------------------------ + // function name : pre_body + // function : cast the register model passed in to reg_block_hcr + // invoked : be invoked by uvm + //------------------------------------------------------------------------------ + virtual task pre_body(); + $cast(reg_block_hcr, model); + endtask : pre_body + + //------------------------------------------------------------------------------ + // function name : body + // function : write the reg randomly, read and compare + // invoked : invoked by uvm + //------------------------------------------------------------------------------ + virtual task body(); + uvm_reg_data_t data, rd_data; + uvm_status_e status; + // data[`HCR_SIZE-1: 0] = {$urandom(), $urandom(), $urandom(), $urandom(), + // $urandom(), $urandom(), $urandom()}; + bit [7:0] temp_data; + int i; + for (i = 0; i < `HCR_BYTE_SIZE; i++) begin + data[i * 8 + 7 -: 8] = i; + end + //data[`HCR_BIT_SIZE-1: 0] = {8'h12, 8'h34, 8'h56, 8'h78, 8'h12, 8'h34, 8'h56}; + reg_block_hcr.reg_hcr_inst.write(status, data, .parent(this)); + reg_block_hcr.reg_hcr_inst.mirror(status, UVM_CHECK, .parent(this)); + rd_data = reg_block_hcr.reg_hcr_inst.get(); + if (data[`HCR_BIT_SIZE-1: 0] != rd_data[`HCR_BIT_SIZE-1: 0]) begin + `uvm_error(get_type_name(), "HCR REGISTER MISMATCH!") + end + reg_block_hcr.reg_hcr_inst.write(status, ~data, .parent(this)); + reg_block_hcr.reg_hcr_inst.mirror(status, UVM_CHECK, .parent(this)); + rd_data = reg_block_hcr.reg_hcr_inst.get(); + if (~data[`HCR_BIT_SIZE-1: 0] != rd_data[`HCR_BIT_SIZE-1: 0]) begin + `uvm_error(get_type_name(), "HCR REGISTER MISMATCH!") + end + `uvm_info("NOTICE", {get_full_name(), " body end!"}, UVM_LOW) + endtask: body +endclass: test_hcr_seq +`endif \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/verification/src/vrf_HTN/sv/slave/hca_slave_agent.sv b/ETH-PLUS_Jingzhao/JingZhao2/verification/src/vrf_HTN/sv/slave/hca_slave_agent.sv new file mode 100644 index 0000000000000000000000000000000000000000..e82709a09ac568d970eb33706ecfcbe87ea633e9 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/verification/src/vrf_HTN/sv/slave/hca_slave_agent.sv @@ -0,0 +1,80 @@ +//CREATE INFORMATION +//---------------------------------------------------------------------------- +// +// (C) COPYRIGHT 2021 BY ICT-HPC CORPORATION ALL RIGHTS RESERVED +// DATE : 2021-03-15 +// AUTHOR : mazhenlong@ncic.ac.cn +// FILENAME : hca_slave_agent.sv +// FUNCTION : This file supplies the function of slave side of HCA verification. +// +//---------------------------------------------------------------------------- + +//CHANGE HISTORY +//---------------------------------------------------------------------------- +// +// AUTHOR DATE VERSION REASON +// mazhenlong 2021-03-15 v1.0 create +// +//---------------------------------------------------------------------------- + +`ifndef __HCA_SLAVE_AGENT__ +`define __HCA_SLAVE_AGENT__ + +//------------------------------------------------------------------------------ +// +// CLASS: hca_slave_agent +// +//------------------------------------------------------------------------------ +class hca_slave_agent extends uvm_agent; + hca_slave_monitor slv_mon; + hca_slave_driver slv_drv; + hca_slave_sequencer slv_sqr; + hca_memory mem; + `uvm_component_utils_begin(hca_slave_agent) + `uvm_component_utils_end + + //------------------------------------------------------------------------------ + // function name : new + // function : constructor + // invoked : invoked when instantiates the class + //------------------------------------------------------------------------------ + function new(string name, uvm_component parent); + super.new(name, parent); + endfunction: new + + //------------------------------------------------------------------------------ + // function name : build_phase + // function : build slave driver, slave monitor and slave sequencer + // invoked : by uvm automatically + //------------------------------------------------------------------------------ + function void build_phase(uvm_phase phase); + super.build_phase(phase); + slv_drv = hca_slave_driver::type_id::create("slv_drv", this); + slv_mon = hca_slave_monitor::type_id::create("slv_mon", this); + slv_sqr = hca_slave_sequencer::type_id::create("slv_sqr", this); + endfunction: build_phase + + //------------------------------------------------------------------------------ + // function name : connect_phase + // function : connect slave driver and slave sequencer, slave monitor and + // slave sequencer + // invoked : by uvm automatically + //------------------------------------------------------------------------------ + function void connect_phase(uvm_phase phase); + slv_drv.seq_item_port.connect(slv_sqr.seq_item_export); + slv_mon.seq_port.connect(slv_sqr.item_collected_fifo.analysis_export); + endfunction: connect_phase + + //------------------------------------------------------------------------------ + // task name : reset_phase + // function : reset_phase in uvm lib + // invoked : by uvm automatically + //------------------------------------------------------------------------------ + task reset_phase(uvm_phase phase); + super.reset_phase(phase); + $cast(slv_drv.mem, this.mem); + $cast(slv_mon.mem, this.mem); + endtask: reset_phase + +endclass: hca_slave_agent +`endif \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/verification/src/vrf_HTN/sv/slave/hca_slave_driver.sv b/ETH-PLUS_Jingzhao/JingZhao2/verification/src/vrf_HTN/sv/slave/hca_slave_driver.sv new file mode 100644 index 0000000000000000000000000000000000000000..e265e97d6514d6ea445cb1a6b94f1b64dbc88430 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/verification/src/vrf_HTN/sv/slave/hca_slave_driver.sv @@ -0,0 +1,368 @@ +//CREATE INFORMATION +//----------------------------------------------------------------------------------------- +// +// (C) COPYRIGHT 2021 BY ICT-HPC CORPORATION ALL RIGHTS RESERVED +// DATE : 2021-04-07 +// AUTHOR : mazhenlong@ncic.ac.cn +// FILENAME : hca_slave_driver.sv +// FUNCTION : This file supplies the function of slave side of HCA verification. +// +//----------------------------------------------------------------------------------------- + +//CHANGE HISTORY +//----------------------------------------------------------------------------------------- +// +// AUTHOR DATE VERSION REASON +// mazhenlong 2021-04-07 v1.0 create +// mazhenlong 2021-12-22 v1.1 add random gap when sending DMA response +// +//----------------------------------------------------------------------------------------- + +`ifndef __HCA_SLAVE_DRIVER__ +`define __HCA_SLAVE_DRIVER__ + +//------------------------------------------------------------------------------ +// +// CLASS: hca_slave_driver +// +//------------------------------------------------------------------------------ +class hca_slave_driver extends uvm_driver #(hca_pcie_item); + + hca_memory mem; + + virtual hca_interface v_if; + + uvm_analysis_port #(hca_pcie_item) port2rm; + + hca_pcie_item resp_item; + + hca_pcie_item pcie_in_flight_queue[$]; + + `uvm_component_utils_begin(hca_slave_driver) + `uvm_component_utils_end + + //------------------------------------------------------------------------------ + // function name : new + // function : constructor + // invoked : invoked when instantiates the class + //------------------------------------------------------------------------------ + function new(string name, uvm_component parent); + super.new(name, parent); + endfunction: new + + //------------------------------------------------------------------------------ + // function name : build_phase + // function : build_phase in uvm library, instantiates sequencer and driver. + // invoked : automatically by uvm + //------------------------------------------------------------------------------ + function void build_phase(uvm_phase phase); + super.build_phase(phase); + if (!uvm_config_db#(virtual hca_interface)::get(this, "", "virtual_if", v_if)) begin + `uvm_fatal("NOVIF", {"virtual interface must be set for: ",get_full_name(),".v_if!"}); + end + port2rm = new("port2rm", this); + endfunction: build_phase + + //------------------------------------------------------------------------------ + // task name : run_phase + // function : run_phase in uvm library, sends the pcie items to DUT + // invoked : invoked by uvm automaticly + //------------------------------------------------------------------------------ + task run_phase(uvm_phase phase); + phase.raise_objection(this); + `uvm_info("NOTICE", {"run_phase begin in ", get_full_name()}, UVM_LOW); + @ (posedge v_if.veri_en); + fork + forever begin + @ (posedge v_if.pcie_clk); + seq_item_port.get_next_item(resp_item); + if (resp_item.item_type == GLOBAL_STOP) begin + `uvm_info("NOTICE", "global stop item received by slave driver!", UVM_LOW); + seq_item_port.item_done(); + break; + end + seq_item_port.item_done(); + resp_item.receiving_clock_count = v_if.clock_count; + pcie_in_flight_queue.push_back(resp_item); + end + forever begin + @ (posedge v_if.pcie_clk); + if (pcie_in_flight_queue.size() > 0) begin + if (pcie_in_flight_queue[0].receiving_clock_count + `PCIE_LATENCY > v_if.clock_count) begin + resp_item = pcie_in_flight_queue.pop_front(); + drive_resp_item(resp_item); + end + end + end + join_any + `uvm_info("NOTICE", "slave driver run_phase end!", UVM_LOW); + phase.drop_objection(this); + endtask: run_phase + + //------------------------------------------------------------------------------ + // task name : drive_resp_item + // function : send the pcie items to DUT and reference model + // invoked : by run_phase + //------------------------------------------------------------------------------ + //-------------------NOTICE: ONLY NO MORE THAN 2048 BYTES---------------------// + task drive_resp_item(hca_pcie_item item); + int sent_dw_num; + int beat_num; + bit [255:0] temp_data; + int j, m, n; + bit [31:0] parity; + + hca_pcie_item item2rm; + item2rm = hca_pcie_item::type_id::create("item2rm", this); + item2rm.copy(item); + // port2rm.write(item2rm); + + if (item.item_type == DMA_RSP) begin + // `uvm_info("NOTICE", "slv drv to scb sent!", UVM_LOW); + sent_dw_num = 0; + beat_num = 0; + while (sent_dw_num < item.rc_dword_count) begin // NOTICE!! SHOULD USE DW COUNT INSDEAD OF BYTE COUNT!!! + + // set tlast + if (beat_num == 0) begin // first beat + if (item.rc_dword_count > 5) begin + v_if.m_axis_rc_tlast = 0; + end + else begin + v_if.m_axis_rc_tlast = 1; + end + end + else begin // other beats + if (sent_dw_num + 8 < item.rc_dword_count) begin + v_if.m_axis_rc_tlast = 0; + end + else begin + v_if.m_axis_rc_tlast = 1; + end + end + + // set tvalid and incontinuous gap + if ($test$plusargs("VALID_GAP")) begin + for (int i = 0; i < $urandom_range(`VALID_GAP); i++) begin + v_if.m_axis_rc_tvalid = 0; + @ (posedge v_if.pcie_clk); + end + end + v_if.m_axis_rc_tvalid = 1; + + // set tkeep + if (v_if.m_axis_rc_tlast != 1) begin // is not the last beat + v_if.m_axis_rc_tkeep = 8'b1111_1111; + end + else begin // is the last beat + if (item.rc_dword_count == 5) begin // fully fill the last beat(also is the first beat) + v_if.m_axis_rc_tkeep = 8'b1111_1111; + end + else if ((beat_num != 0) && (sent_dw_num + 8 == item.rc_dword_count)) begin // fully fill the last beat(not the first beat) + v_if.m_axis_rc_tkeep = 8'b1111_1111; + end + else begin // not fully fill the last beat + if (beat_num == 0) begin // is the first beat + v_if.m_axis_rc_tkeep[2:0] = 3'b111; + for (int i = 0; i < 5; i++) begin + if (i > item.rc_dword_count) begin + v_if.m_axis_rc_tkeep[i + 3] = 0; + end + else begin + v_if.m_axis_rc_tkeep[i + 3] = 1; + end + end + end + else begin // is not the first beat + for (int i = 0; i < 8; i++) begin + if (sent_dw_num + i > item.rc_dword_count) begin + v_if.m_axis_rc_tkeep[i] = 0; + end + else begin + v_if.m_axis_rc_tkeep[i] = 1; + end + end + end + end + end + + // set tdata + // set descriptor + if (beat_num == 0) begin + v_if.m_axis_rc_tdata[11:0] = item.rc_addr; + v_if.m_axis_rc_tdata[15:12] = item.rc_error_code; + v_if.m_axis_rc_tdata[28:16] = item.rc_byte_count; + v_if.m_axis_rc_tdata[29] = item.rc_locked_read_completion; + v_if.m_axis_rc_tdata[30] = item.rc_request_completed; + v_if.m_axis_rc_tdata[31] = 0; + v_if.m_axis_rc_tdata[42:32] = item.rc_dword_count; + v_if.m_axis_rc_tdata[45:43] = item.rc_completion_status; + v_if.m_axis_rc_tdata[46] = item.rc_poisoned_completion; + v_if.m_axis_rc_tdata[47] = 0; + v_if.m_axis_rc_tdata[55:48] = item.rc_requester_device; + v_if.m_axis_rc_tdata[63:56] = item.rc_requester_bus; + v_if.m_axis_rc_tdata[71:64] = item.rc_tag; + v_if.m_axis_rc_tdata[79:72] = item.rc_completer_device; + v_if.m_axis_rc_tdata[87:80] = item.rc_completer_bus; + v_if.m_axis_rc_tdata[88] = 0; + v_if.m_axis_rc_tdata[91:89] = item.rc_tc; + v_if.m_axis_rc_tdata[94:92] = item.rc_attr; + v_if.m_axis_rc_tdata[95] = 0; + end + // set payload + if (beat_num == 0) begin // first beat + temp_data = item.data_payload.pop_front; + v_if.m_axis_rc_tdata[255:96] = temp_data[159:0]; + end + else begin // later beats + v_if.m_axis_rc_tdata[95:0] = temp_data[255:160]; + // if (item.data_payload.size() != 0) begin + // if (sent_dw_num + 8 < item.rc_dword_count) begin + // temp_data = item.data_payload.pop_front; + // v_if.m_axis_rc_tdata[255:96] = temp_data[159:0]; + // end + // else begin + // v_if.m_axis_rc_tdata[255:96] = 0; + // end + if (sent_dw_num + 3 <= item.rc_dword_count) begin + temp_data = item.data_payload.pop_front; + v_if.m_axis_rc_tdata[255:96] = temp_data[159:0]; + end + else begin + v_if.m_axis_rc_tdata[255:96] = 0; + end + end + `uvm_info("NOTICE", $sformatf("RC tdata: %h", v_if.m_axis_rc_tdata), UVM_LOW); + + // remember to check data amount + + // set start byte enable + // v_if.m_axis_rc_tuser[31:0] = 32'hffff_ffff; // byte enable + // if (beat_num == 0) begin + // v_if.m_axis_rc_tuser[15:0] = {item.rc_first_be, 12'hfff}; + // end + + // // set end byte enable + // if (item.rc_last_be != 0) begin + // if (v_if.m_axis_rc_tlast == 1) begin + // int i = 7; + // while (v_if.m_axis_rc_tlast[i] == 0) begin + // i--; + // end + // v_if.m_axis_rc_tuser[i * 4 + 3 -: 4] = item.rc_last_be; + // end + // else begin + // if (beat_num == 0) begin + // v_if.m_axis_rc_tuser[31:16] = 16'hffff; + // end + // else begin + // v_if.m_axis_rc_tuser[31:0] = 32'hffff_ffff; + // end + // end + // end + // else begin + // v_if.m_axis_rc_tuser[31:16] = 0; + // end + + // set byte enable + // only ONE DW + if (item.rc_last_be == 0) begin + // check correctness + if (item.rc_byte_count > 4 || beat_num != 0) begin + `uvm_fatal("BYTE_CNT_ERROR", $sformatf("rc_byte_count does not fit 1! rc_byte_count: %h, beat_num: %0d", item.rc_byte_count, beat_num)); + end + // set start byte enable + v_if.m_axis_rc_tuser[31:0] = {16'h0000, item.rc_first_be, 12'hfff}; + end + // multiple DW, only one beat + else if (beat_num == 0 && v_if.m_axis_rc_tlast == 1) begin + int i; + // check correctness + if (item.rc_byte_count > 20 || beat_num != 0 || item.rc_byte_count <= 4) begin + `uvm_fatal("BYTE_CNT_ERROR", $sformatf("rc_byte_count does not fit 2! item.rc_byte_count: %h, beat_num: %0d", item.rc_byte_count, beat_num)); + end + v_if.m_axis_rc_tuser[31:0] = 32'hffff_ffff; + // set start byte enable + v_if.m_axis_rc_tuser[15:0] = {item.rc_first_be, 12'hfff}; + // set end byte enable + i = 7; + while (v_if.m_axis_rc_tkeep[i] == 0) begin + v_if.m_axis_rc_tuser[i * 4 + 3 -: 4] = 4'h0; + i--; + end + v_if.m_axis_rc_tuser[i * 4 + 3 -: 4] = item.rc_last_be; + if (i <= 4) begin + `uvm_fatal("I_ERROR", $sformatf("i error! i: %0d", i)); + end + end + // multiple beats + else begin + // the first beat + if (beat_num == 0) begin + v_if.m_axis_rc_tuser[31:0] = {16'hffff, item.rc_first_be, 12'hfff}; + end + // the last beat + else if (v_if.m_axis_rc_tlast == 1) begin + int i; + i = 7; + v_if.m_axis_rc_tuser[31:0] = 32'hffff_ffff; + while (v_if.m_axis_rc_tkeep[i] == 0) begin + v_if.m_axis_rc_tuser[i * 4 + 3 -: 4] = 4'h0; + i--; + end + v_if.m_axis_rc_tuser[i * 4 + 3 -: 4] = item.rc_last_be; + end + // middle beat + else begin + v_if.m_axis_rc_tuser[31:0] = 32'hffff_ffff; + end + end + + if (beat_num == 0) begin // is_sof_0 + v_if.m_axis_rc_tuser[32] = 1; + end + else begin + v_if.m_axis_rc_tuser[32] = 0; + end + v_if.m_axis_rc_tuser[33] = 0; // is_sof_1, only when straddle is open, what is straddle? + if (v_if.m_axis_rc_tlast == 0) begin // is_eof + v_if.m_axis_rc_tuser[37:34] = 0; + v_if.m_axis_rc_tuser[41:38] = 0; + end + else begin + v_if.m_axis_rc_tuser[37:34] = 4'b1111; + v_if.m_axis_rc_tuser[41:38] = 0; + end + v_if.m_axis_rc_tuser[42] = 0; // discontinue + for (m = 0; m < 32; m++) begin + for (n = 0; n < 8; n++) begin + if (v_if.m_axis_rc_tdata[m * 8 + n] == 1'b1) begin + parity[m] = ~parity[m]; + end + end + end + v_if.m_axis_rc_tuser[74:43] = parity; + + // set beat num and sent dw num + if (beat_num == 0) begin + sent_dw_num = sent_dw_num + 5; + end + else begin + sent_dw_num = sent_dw_num + 8; + end + beat_num++; + while (1) begin + @ (posedge v_if.pcie_clk); + if (v_if.m_axis_rc_tready == 1'b1) begin + break; + end + end + end + v_if.m_axis_rc_tvalid = 0; + end + else begin + `uvm_error("ITEM_TYPE_ERR", "received pcie item illegal!"); + end + endtask: drive_resp_item +endclass: hca_slave_driver +`endif diff --git a/ETH-PLUS_Jingzhao/JingZhao2/verification/src/vrf_HTN/sv/slave/hca_slave_monitor.sv b/ETH-PLUS_Jingzhao/JingZhao2/verification/src/vrf_HTN/sv/slave/hca_slave_monitor.sv new file mode 100644 index 0000000000000000000000000000000000000000..02fc1b85a4380934fe92c5bc9ccbd0f58a945c9d --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/verification/src/vrf_HTN/sv/slave/hca_slave_monitor.sv @@ -0,0 +1,318 @@ +//CREATE INFORMATION +//---------------------------------------------------------------------------------------------- +// +// (C) COPYRIGHT 2021 BY ICT-HPC CORPORATION ALL RIGHTS RESERVED +// DATE : 2021-04-07 +// AUTHOR : mazhenlong@ncic.ac.cn +// FILENAME : hca_slave_monitor.sv +// FUNCTION : This file supplies the function of receiving DMA requests from +// virtual interface and transform it into hca_pcie_items. +// +//---------------------------------------------------------------------------------------------- + +//CHANGE HISTORY +//---------------------------------------------------------------------------------------------- +// +// AUTHOR DATE VERSION REASON +// mazhenlong 2021-04-07 v1.0 create +// mazhenlong 2021-06-30 v1.1 add judgement of icm access, if the received +// item accesses icm space, do not send it to scb +// +//---------------------------------------------------------------------------------------------- + +`ifndef __HCA_SLAVE_MONITOR__ +`define __HCA_SLAVE_MONITOR__ + +//------------------------------------------------------------------------------ +// +// CLASS: hca_slave_monitor +// +//------------------------------------------------------------------------------ +class hca_slave_monitor extends uvm_monitor; + hca_pcie_item received_item; + hca_pcie_item item_to_scb; + hca_pcie_item item_to_sqr; + hca_pcie_item item_to_sqr_mbx; + hca_pcie_item probe_item_to_scb; + hca_pcie_item pcie_in_flight_queue[$]; + virtual hca_interface vif; + uvm_analysis_port #(hca_pcie_item) seq_port; // to sequencer + uvm_analysis_port #(hca_pcie_item) port2scb; // duv data + // uvm_analysis_port #(hca_pcie_item) port2scb_probe; + // uvm_analysis_port #(hca_pcie_item) port2rm; + mailbox mon2seq_mbx; + + hca_memory mem; + + `uvm_component_utils_begin(hca_slave_monitor) + `uvm_component_utils_end + + //------------------------------------------------------------------------------ + // function name : new + // function : constructor + // invoked : invoked when instantiates the class + //------------------------------------------------------------------------------ + function new(string name, uvm_component parent); + super.new(name, parent); + endfunction: new + + //------------------------------------------------------------------------------ + // function name : build_phase + // function : build_phase in uvm lib + // invoked : by uvm automatically + //------------------------------------------------------------------------------ + function void build_phase(uvm_phase phase); + super.build_phase(phase); + if(!uvm_config_db #(virtual hca_interface)::get(this, "", "virtual_if", vif)) begin + `uvm_fatal("NOVIF",{"virtual interface must be set for: ",get_full_name(),".vif"}); + end + item_to_sqr = hca_pcie_item::type_id::create("item_to_sqr", this); + item_to_scb = hca_pcie_item::type_id::create("item_to_scb", this); + item_to_sqr_mbx = hca_pcie_item::type_id::create("item_to_sqr_mbx", this); + seq_port = new("seq_port", this); + port2scb = new("port2scb", this); + mon2seq_mbx = new(); + uvm_config_db#(mailbox)::set(uvm_root::get(), "*", "mon2seq_mbx", mon2seq_mbx); + `uvm_info("NOTICE", "global stop mailbox send finished!", UVM_LOW); + endfunction: build_phase + + //------------------------------------------------------------------------------ + // task name : run_phase + // function : run_phase in uvm lib + // invoked : by uvm automatically + //------------------------------------------------------------------------------ + task run_phase(uvm_phase phase); + int beat_num; + int received_dw_num; + int heartbeat = 0; + bit [`DATA_WIDTH-1: 0] temp_data; + phase.raise_objection(this); + super.run_phase(phase); + @ (posedge vif.veri_en); + vif.s_axis_rq_tready = 1; + fork + // generate duv item + forever begin + bit [3:0] first_be; + bit [3:0] last_be; + hca_pcie_item item_to_sqr_mbx; + while (1) begin + @ (posedge vif.pcie_clk); + if (vif.s_axis_rq_tvalid == 1 || vif.global_stop == 1) begin + break; + end + end + + received_item = hca_pcie_item::type_id::create("received_item", this); + + if (vif.global_stop == 1) begin + `uvm_info("GLB_STOP_INFO", "global stop signal received in slave monitor!", UVM_LOW); + received_item.item_type = GLOBAL_STOP; + seq_port.write(received_item); + `uvm_info("GLB_STOP_INFO", "global stop item sent to slave sequencer!", UVM_LOW); + break; + end + + //----------------process received dma req-----------------// + `uvm_info("NOTICE", "DMA req processing begin!", UVM_LOW); + if (vif.s_axis_rq_tdata[78:75] == `PCIE_MEM_RD) begin + `uvm_info("NOTICE", $sformatf("received dma read request! addr: %h", {vif.s_axis_rq_tdata[63:2], 2'b0}), UVM_LOW); + received_item.item_type = DMA_RD; + received_item.rq_req_type = MEM_RD; + received_item.rq_addr = {vif.s_axis_rq_tdata[63:2], 2'b0}; + received_item.rq_dword_count = vif.s_axis_rq_tdata[74:64]; + received_item.rq_req_type = vif.s_axis_rq_tdata[78:75]; + received_item.rq_poisoned_req = vif.s_axis_rq_tdata[79]; + received_item.rq_requester_device = vif.s_axis_rq_tdata[87:80]; + received_item.rq_requester_bus = vif.s_axis_rq_tdata[95:88]; + received_item.rq_tag = vif.s_axis_rq_tdata[103:96]; + received_item.rq_completer_device = vif.s_axis_rq_tdata[111:104]; + received_item.rq_completer_bus = vif.s_axis_rq_tdata[119:112]; + received_item.rq_requester_id_en = vif.s_axis_rq_tdata[120]; + received_item.rq_tc = vif.s_axis_rq_tdata[123:121]; + received_item.rq_attr = vif.s_axis_rq_tdata[126:124]; + received_item.rq_force_ecrc = vif.s_axis_rq_tdata[127]; + received_item.rq_first_be = vif.s_axis_rq_tuser[3:0]; + received_item.rq_last_be = vif.s_axis_rq_tuser[7:4]; + if (vif.s_axis_rq_tlast != 1) begin + `uvm_fatal("RQ_ERR", "RD rq_tlast error!"); + end + end + else if (vif.s_axis_rq_tdata[78:75] == `PCIE_MEM_WR) begin + `uvm_info("NOTICE", $sformatf("received dma write request! addr: %h, dw count: %h, first be: %h, last be: %h", + {vif.s_axis_rq_tdata[63:2], 2'b0}, vif.s_axis_rq_tdata[74:64], vif.s_axis_rq_tuser[3:0], + vif.s_axis_rq_tuser[7:4]), UVM_LOW + ); + beat_num = 0; + received_dw_num = 0; + received_item.item_type = DMA_WR; + received_item.rq_req_type = MEM_WR; + received_item.rq_addr = {vif.s_axis_rq_tdata[63:2], 2'b0}; + received_item.rq_dword_count = vif.s_axis_rq_tdata[74:64]; + received_item.rq_req_type = vif.s_axis_rq_tdata[78:75]; + received_item.rq_poisoned_req = vif.s_axis_rq_tdata[79]; + received_item.rq_requester_device = vif.s_axis_rq_tdata[87:80]; + received_item.rq_requester_bus = vif.s_axis_rq_tdata[95:88]; + received_item.rq_tag = vif.s_axis_rq_tdata[103:96]; + received_item.rq_completer_device = vif.s_axis_rq_tdata[111:104]; + received_item.rq_completer_bus = vif.s_axis_rq_tdata[119:112]; + received_item.rq_requester_id_en = vif.s_axis_rq_tdata[120]; + received_item.rq_tc = vif.s_axis_rq_tdata[123:121]; + received_item.rq_attr = vif.s_axis_rq_tdata[126:124]; + received_item.rq_force_ecrc = vif.s_axis_rq_tdata[127]; + + received_item.rq_first_be = vif.s_axis_rq_tuser[3:0]; + received_item.rq_last_be = vif.s_axis_rq_tuser[7:4]; + `uvm_info("NOTICE", $sformatf("Write dw count: %h", received_item.rq_dword_count), UVM_LOW); + + while (1) begin + if (vif.s_axis_rq_tlast != 1) begin // not the last beat + if (beat_num == 0) begin // is the first beat + temp_data[127:0] = vif.s_axis_rq_tdata[255:128]; + end + else begin // is not the first beat + temp_data[255:128] = vif.s_axis_rq_tdata[127:0]; + received_item.data_payload.push_back(temp_data); + `uvm_info("NOTICE", $sformatf("item data payload push: %h", temp_data), UVM_LOW); + temp_data[127:0] = vif.s_axis_rq_tdata[255:128]; + end + end + else begin // the last beat + if (beat_num == 0) begin + temp_data[127:0] = vif.s_axis_rq_tdata[255:128]; + temp_data[255:128] = 0; + received_item.data_payload.push_back(temp_data); + `uvm_info("NOTICE", $sformatf("item data payload push: %h", temp_data), UVM_LOW); + end + else begin + if (received_dw_num + 4 < received_item.rq_dword_count) begin + temp_data[255:128] = vif.s_axis_rq_tdata[127:0]; + received_item.data_payload.push_back(temp_data); + `uvm_info("NOTICE", $sformatf("item data payload push: %h", temp_data), UVM_LOW); + temp_data[127:0] = vif.s_axis_rq_tdata[255:128]; + temp_data[255:128] = 0; + received_item.data_payload.push_back(temp_data); + `uvm_info("NOTICE", $sformatf("item data payload push: %h", temp_data), UVM_LOW); + end + else begin + temp_data[255:128] = vif.s_axis_rq_tdata[127:0]; + received_item.data_payload.push_back(temp_data); + `uvm_info("NOTICE", $sformatf("item data payload push: %h", temp_data), UVM_LOW); + end + end + end + if (beat_num == 0) begin + received_dw_num += 4; + end + else begin + received_dw_num += 8; + end + beat_num++; + + if (received_dw_num < received_item.rq_dword_count) begin + if (vif.s_axis_rq_tlast == 1 && + vif.s_axis_rq_tvalid == 1 && + vif.s_axis_rq_tready == 1) begin + if (vif.s_axis_rq_tlast == 1) begin + `uvm_fatal("RQ_ERR", $sformatf("WR rq_tlast error, should NOT be 1! received_dw_num: %h, received_item.rq_dword_count: %h", + received_dw_num, received_item.rq_dword_count)); + end + end + while (1) begin + @ (posedge vif.pcie_clk); + if (vif.s_axis_rq_tvalid == 1) begin + break; + end + end + end + else begin + if (vif.s_axis_rq_tlast == 1) begin + break; + end + else begin + `uvm_fatal("RQ_ERR", $sformatf("WR rq_tlast error! received_dw_num: %h, received_item.rq_dword_count: %h", + received_dw_num, received_item.rq_dword_count)); + end + end + end + end + else begin + `uvm_fatal("RQ_ERR", $sformatf("RQ type error, rq_tdata: %h", vif.s_axis_rq_tdata)); + end + + received_item.receiving_clock_count = vif.clock_count; + pcie_in_flight_queue.push_back(received_item); + + // if received item does not fall into icm space, send item to scoreboard + if (send2scb(received_item.rq_addr) == 1) begin + fork + begin + hca_pcie_item item_to_scb_cqe; + item_to_scb_cqe = hca_pcie_item::type_id::create("item_to_scb_cqe", this); + item_to_scb_cqe.copy(received_item); + port2scb.write(item_to_scb_cqe); + end + join_none + end + end + + // if the first item in the waiting queue has been pending for `PCIE_LATENCY, send it to the sequencer + begin + while (1) begin + @ (posedge vif.pcie_clk); + if (pcie_in_flight_queue.size() > 0) begin + if (pcie_in_flight_queue[0].receiving_clock_count + `PCIE_LATENCY > vif.clock_count) begin + // send received item to slave sequence + received_item = pcie_in_flight_queue.pop_front(); + item_to_sqr.copy(received_item); + seq_port.write(item_to_sqr); + item_to_sqr_mbx.copy(received_item); + mon2seq_mbx.put(item_to_sqr_mbx); + end + end + if (vif.global_stop == 1) begin + break; + end + end + end + + // detect block + begin + heartbeat = 0; + while (1) begin + @ (posedge vif.pcie_clk); + if (vif.global_stop == 1) begin + break; + end + if (vif.s_axis_rq_tvalid == 1) begin + heartbeat = 0; + end + else begin + heartbeat++; + if (heartbeat > `BREAKTIME) begin + hca_pcie_item item_to_scb; + item_to_scb = hca_pcie_item::type_id::create("item_to_scb", this); + item_to_scb.item_type = INTR; + heartbeat = 0; + port2scb.write(item_to_scb); + end + end + end + end + join + `uvm_info("NOTICE", "\033[47;40mslave monitor run_phase stop!\033[0m", UVM_LOW); + phase.drop_objection(this); + endtask: run_phase + + function bit send2scb(addr rq_addr); + if (rq_addr[47:33] == 15'b1) begin // if is CQ address + `uvm_info("SLV_MON_NOTICE", $sformatf("slave monitor sends cqe to SCB, address: %h", rq_addr), UVM_LOW); + return 1; + end + else begin + `uvm_info("SLV_MON_NOTICE", $sformatf("Not CQE, slave monitor does not send item to SCB, address: %h", rq_addr), UVM_LOW); + return 0; + end + endfunction: send2scb +endclass: hca_slave_monitor +`endif \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/verification/src/vrf_HTN/sv/slave/hca_slave_sequencer.sv b/ETH-PLUS_Jingzhao/JingZhao2/verification/src/vrf_HTN/sv/slave/hca_slave_sequencer.sv new file mode 100644 index 0000000000000000000000000000000000000000..580ed8bebc24928970f469adbbdb1908cf67e0de --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/verification/src/vrf_HTN/sv/slave/hca_slave_sequencer.sv @@ -0,0 +1,54 @@ +//CREATE INFORMATION +//---------------------------------------------------------------------------- +// +// (C) COPYRIGHT 2021 BY ICT-HPC CORPORATION ALL RIGHTS RESERVED +// DATE : 2021-04-07 +// AUTHOR : mazhenlong@ncic.ac.cn +// FILENAME : hca_slave_sequencer.sv +// FUNCTION : This file supplies the function of slave side of HCA verification. +// +//---------------------------------------------------------------------------- + +//CHANGE HISTORY +//---------------------------------------------------------------------------- +// +// AUTHOR DATE VERSION REASON +// mazhenlong 2021-04-07 v1.0 create +// +//---------------------------------------------------------------------------- + +`ifndef __HCA_SLAVE_SEQUENCER__ +`define __HCA_SLAVE_SEQUENCER__ + +//------------------------------------------------------------------------------ +// +// CLASS: hca_slave_driver +// +//------------------------------------------------------------------------------ +class hca_slave_sequencer extends uvm_sequencer #(hca_pcie_item); + hca_memory mem; + uvm_tlm_analysis_fifo #(hca_pcie_item, hca_slave_sequencer) item_collected_fifo; + `uvm_component_utils_begin(hca_slave_sequencer) + `uvm_component_utils_end + + //------------------------------------------------------------------------------ + // function name : new + // function : constructor + // invoked : invoked when instantiates the class + //------------------------------------------------------------------------------ + function new(string name, uvm_component parent); + super.new(name, parent); + endfunction: new + + //------------------------------------------------------------------------------ + // function name : build_phase + // function : build_phase in uvm lib + // invoked : by uvm automatically + //------------------------------------------------------------------------------ + function void build_phase(uvm_phase phase); + super.build_phase(phase); + item_collected_fifo = new ("item_collected_fifo", this); + endfunction: build_phase + +endclass: hca_slave_sequencer +`endif \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/verification/src/vrf_HTN/sv/test/hca_config_agent.sv b/ETH-PLUS_Jingzhao/JingZhao2/verification/src/vrf_HTN/sv/test/hca_config_agent.sv new file mode 100644 index 0000000000000000000000000000000000000000..fe9c06b02ce05998e4f05581c5b9b2f6efed4ee6 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/verification/src/vrf_HTN/sv/test/hca_config_agent.sv @@ -0,0 +1,395 @@ +//CREATE INFORMATION +//----------------------------------------------------------------------------------------------- +// +// (C) COPYRIGHT 2021 BY ICT-HPC CORPORATION ALL RIGHTS RESERVED +// DATE : 2021-10-21 +// AUTHOR : mazhenlong@ncic.ac.cn +// FILENAME : hca_config_agent.sv +// FUNCTION : This class implements configuration of HCA +// +//----------------------------------------------------------------------------------------------- + +//CHANGE HISTORY +//----------------------------------------------------------------------------------------------- +// +// AUTHOR DATE VERSION REASON +// mazhenlong 2020-10-21 v1.0 create +// +//----------------------------------------------------------------------------------------------- + +`ifndef __HCA_CONFIG_AGENT__ +`define __HCA_CONFIG_AGENT__ + +//---------------------------------------------------------------------------- +// +// CLASS: hca_config_agent +// +//---------------------------------------------------------------------------- +class hca_config_agent extends uvm_object; + + hca_vsequence vseq; + hca_icm_vaddr icm_vaddr; + hca_mem_info mem_info; + hca_pcie_item pcie_item; + + `uvm_object_utils_begin(hca_config_agent) + `uvm_object_utils_end + + //------------------------------------------------------------------------------ + // function name : new + // function : constructor + // invoked : invoked when instantiates the class + //------------------------------------------------------------------------------ + function new(string name = "hca_config_agent"); + super.new(name); + endfunction + + function init(hca_vsequence input_vseq, hca_icm_vaddr input_icm_vaddr, hca_mem_info input_mem_info); + this.vseq = input_vseq; + this.icm_vaddr = input_icm_vaddr; + this.mem_info = input_mem_info; + endfunction: init + + task init_hca(int host_id); + hca_pcie_item init_hca_item; + init_hca_item = hca_pcie_item::type_id::create($sformatf("init_hca_item[%0d]", host_id)); + assert (init_hca_item.randomize() with {hcr_op == `CMD_INIT_HCA;}) + else begin + `uvm_fatal("RANDOMIZE_ERROR", "randomize error in init hca!"); + end + init_hca_item.icm_base_struct.qpc_base = `QPC_OFFSET; + init_hca_item.icm_base_struct.cqc_base = `CQC_OFFSET; + init_hca_item.icm_base_struct.eqc_base = `EQC_OFFSET; + init_hca_item.icm_base_struct.mpt_base = `MPT_OFFSET; + init_hca_item.icm_base_struct.mtt_base = `MTT_OFFSET; + init_hca_item.icm_base_struct.log_num_qps = `LOG_NUM_QPS; + init_hca_item.icm_base_struct.log_num_cqs = `LOG_NUM_CQS; + init_hca_item.icm_base_struct.log_num_eqs = `LOG_NUM_EQS; + init_hca_item.icm_base_struct.log_mpt_sz = `LOG_MPT_SZ; + if (vseq.cfg_mbx[host_id].try_put(init_hca_item) == 0) begin + `uvm_fatal("TRY_PUT_ERR", $sformatf("init hca error! host_id: %h.", host_id)); + end + endtask: init_hca + + function bit [63:0] map_icm(int host_id, int m_type, int page_num); // m_type: 1: qp context; 2: cq context; 3: mpt; 4: mtt; + // return the virtual address of the mapped page in ICM space; + hca_pcie_item map_icm_item; + bit [63:0] temp_virt_addr; + bit [63:0] temp_phys_addr; + // addr start_virt_addr; + int i; + bit flag = 0; + if (page_num > 12'b11111111) begin + `uvm_fatal("PAGE_NUM_ERROR", "illegal page_num in map_icm!"); + end + if (m_type == `ICM_QPC_TYP) begin + icm_vaddr.qpc_page_mapped[host_id] += page_num; + icm_vaddr.qpc_cap_left[host_id] += `PAGE_SIZE * page_num; + if (icm_vaddr.qpc_page_mapped[host_id] > icm_vaddr.qpc_page_limit[host_id]) begin + `uvm_fatal("ICM_ERR", $sformatf("QPC ICM page num exceeds limitation! Page used: %0d", icm_vaddr.qpc_page_mapped[host_id])); + end + + temp_virt_addr = `QPC_OFFSET; + foreach (icm_vaddr.qpc_virt_addr[host_id][i]) begin + if (icm_vaddr.qpc_virt_addr[host_id][i] == temp_virt_addr) begin + temp_virt_addr += `PAGE_SIZE; + end + else begin + if (icm_vaddr.qpc_virt_addr[host_id][i] >= temp_virt_addr + page_num * `PAGE_SIZE) begin + // start_virt_addr = temp_virt_addr; + for (int j = 0; j < page_num; j++) begin + icm_vaddr.qpc_virt_addr[host_id].insert(i, temp_virt_addr + j * `PAGE_SIZE); + flag = 1; + end + break; + end + end + end + if (flag == 0) begin + for (int j; j < page_num; j++) begin + icm_vaddr.qpc_virt_addr[host_id].push_back(temp_virt_addr + j * `PAGE_SIZE); + end + end + end + else if (m_type == `ICM_CQC_TYP) begin + icm_vaddr.cqc_page_mapped[host_id] += page_num; + icm_vaddr.cqc_cap_left[host_id] += `PAGE_SIZE * page_num; + if (icm_vaddr.cqc_page_mapped[host_id] > icm_vaddr.cqc_page_limit[host_id]) begin + `uvm_fatal("ICM_ERR", $sformatf("CQC ICM page num exceeds limitation! Page used: %0d", icm_vaddr.cqc_page_mapped[host_id])); + end + + temp_virt_addr = `CQC_OFFSET; + foreach (icm_vaddr.cqc_virt_addr[host_id][i]) begin + if (icm_vaddr.cqc_virt_addr[host_id][i] == temp_virt_addr) begin + temp_virt_addr += `PAGE_SIZE; + end + else begin + if (icm_vaddr.cqc_virt_addr[host_id][i] >= temp_virt_addr + page_num * `PAGE_SIZE) begin + for (int j = 0; j < page_num; j++) begin + icm_vaddr.cqc_virt_addr[host_id].insert(i, temp_virt_addr + j * `PAGE_SIZE); + flag = 1; + end + break; + end + end + end + if (flag == 0) begin + for (int j; j < page_num; j++) begin + icm_vaddr.cqc_virt_addr[host_id].push_back(temp_virt_addr + j * `PAGE_SIZE); + end + end + end + else if (m_type == `ICM_MPT_TYP) begin + icm_vaddr.mpt_page_mapped[host_id] += page_num; + icm_vaddr.mpt_cap_left[host_id] += `PAGE_SIZE * page_num; + if (icm_vaddr.mpt_page_mapped[host_id] > icm_vaddr.mpt_page_limit[host_id]) begin + `uvm_fatal("ICM_ERR", $sformatf("MPT ICM page num exceeds limitation! Page used: %0d", icm_vaddr.mpt_page_mapped[host_id])); + end + + temp_virt_addr = `MPT_OFFSET; + foreach (icm_vaddr.mpt_virt_addr[host_id][i]) begin + if (icm_vaddr.mpt_virt_addr[host_id][i] == temp_virt_addr) begin + temp_virt_addr += `PAGE_SIZE; + end + else begin + if (icm_vaddr.mpt_virt_addr[host_id][i] >= temp_virt_addr + page_num * `PAGE_SIZE) begin + for (int j = 0; j < page_num; j++) begin + icm_vaddr.mpt_virt_addr[host_id].insert(i, temp_virt_addr + j * `PAGE_SIZE); + flag = 1; + end + break; + end + end + end + if (flag == 0) begin + for (int j; j < page_num; j++) begin + icm_vaddr.mpt_virt_addr[host_id].push_back(temp_virt_addr + j * `PAGE_SIZE); + end + end + end + else if (m_type == `ICM_MTT_TYP) begin + icm_vaddr.mtt_page_mapped[host_id] += page_num; + icm_vaddr.mtt_cap_left[host_id] += `PAGE_SIZE * page_num; + if (icm_vaddr.mtt_page_mapped[host_id] > icm_vaddr.mtt_page_limit[host_id]) begin + `uvm_fatal("ICM_ERR", $sformatf("MTT ICM page num exceeds limitation! Page used: %0d", icm_vaddr.mtt_page_mapped[host_id])); + end + + temp_virt_addr = `MTT_OFFSET; + foreach (icm_vaddr.mtt_virt_addr[host_id][i]) begin + if (icm_vaddr.mtt_virt_addr[host_id][i] == temp_virt_addr) begin + temp_virt_addr += `PAGE_SIZE; + end + else begin + if (icm_vaddr.mtt_virt_addr[host_id][i] >= temp_virt_addr + page_num * `PAGE_SIZE) begin + for (int j = 0; j < page_num; j++) begin + icm_vaddr.mtt_virt_addr[host_id].insert(i, temp_virt_addr + j * `PAGE_SIZE); + flag = 1; + end + break; + end + end + end + if (flag == 0) begin + for (int j; j < page_num; j++) begin + icm_vaddr.mtt_virt_addr[host_id].push_back(temp_virt_addr + j * `PAGE_SIZE); + end + end + if (icm_vaddr.mtt_virt_addr[host_id].size() > 512) begin + `uvm_fatal("ICM_PAGE_EXCEED", "ICM overwrite!"); + end + end + else if (m_type == `ICM_EQC_TYP) begin + temp_virt_addr = `EQC_OFFSET; + foreach (icm_vaddr.eqc_virt_addr[host_id][i]) begin + if (icm_vaddr.eqc_virt_addr[host_id][i] == temp_virt_addr) begin + temp_virt_addr += `PAGE_SIZE; + end + else begin + if (icm_vaddr.eqc_virt_addr[host_id][i] >= temp_virt_addr + page_num * `PAGE_SIZE) begin + for (int j = 0; j < page_num; j++) begin + icm_vaddr.eqc_virt_addr[host_id].insert(i, temp_virt_addr + j * `PAGE_SIZE); + flag = 1; + end + break; + end + end + end + if (flag == 0) begin + for (int j; j < page_num; j++) begin + icm_vaddr.eqc_virt_addr[host_id].push_back(temp_virt_addr + j * `PAGE_SIZE); + end + end + end + else begin + `uvm_fatal("ILG_INPUT", "illegal m_type in map_icm!"); + end + + map_icm_item = hca_pcie_item::type_id::create("map_icm_item"); + assert(map_icm_item.randomize() with {hcr_op == `CMD_MAP_ICM; map_type == m_type;}) + else begin + `uvm_fatal("RANDOMIZE_ERROR", "randomize error in map icm!"); + end + for (int i = 0; i < page_num; i++) begin + map_icm_item.icm_addr_map.virt.push_back(temp_virt_addr + i * `PAGE_SIZE); + map_icm_item.icm_addr_map.page.push_back(temp_virt_addr + `ICM_BASE + i * `PAGE_SIZE); + end + map_icm_item.icm_addr_map.page_num = page_num; + vseq.cfg_mbx[host_id].try_put(map_icm_item); + return temp_virt_addr; + endfunction: map_icm + + //------------------------------------------------------------------------------ + // task name : modify_qp + // function : generate and send modify qp item. + // invoked : by gen_item + //------------------------------------------------------------------------------ + task modify_qp(int host_id, qp_context qp_ctx); + hca_pcie_item modify_qp_item; + modify_qp_item = hca_pcie_item::type_id::create("modify_qp_item"); + modify_qp_item.qp_ctx = qp_ctx; + assert(modify_qp_item.randomize() with {hcr_op == `CMD_RTR2RTS_QPEE;})// qp_num == 2;}; + else begin + `uvm_fatal("RANDOMIZE_ERROR", "randomize error in modify qp!"); + end + vseq.cfg_mbx[host_id].try_put(modify_qp_item); + endtask: modify_qp + + //------------------------------------------------------------------------------ + // task name : query_qp + // function : generate and send query qp item. + // invoked : by gen_item + //------------------------------------------------------------------------------ + task query_qp(int host_id, int qpn); + hca_pcie_item query_qp_item; + query_qp_item = hca_pcie_item::type_id::create("query_qp_item"); + assert(query_qp_item.randomize() with {hcr_op == `CMD_QUERY_QP; hcr_in_modifier == qpn;}) + else begin + `uvm_fatal("RANDOMIZE_ERROR", "randomize error in query qp!"); + end + vseq.cfg_mbx[host_id].try_put(query_qp_item); + endtask: query_qp + + task sw2hw_cq(int host_id, cq_context cq_ctx); + hca_pcie_item sw2hw_cq_item; + bit [31:0] cqn; + icm_vaddr.cqc_cap_left[host_id] -= `CQC_ENTRY_SZ; + if (icm_vaddr.cqc_cap_left[host_id] < 0) begin + `uvm_fatal("ICM_ERR", $sformatf("ICM CAPACITY OUT!")); + end + + sw2hw_cq_item = hca_pcie_item::type_id::create("sw2hw_cq_item"); + sw2hw_cq_item.cq_ctx = cq_ctx; + cqn = cq_ctx.cqn; + assert(sw2hw_cq_item.randomize() with {hcr_op == `CMD_SW2HW_CQ; hcr_in_modifier == cq_ctx.cqn;}) + else begin + `uvm_fatal("RANDOMIZE_ERROR", "randomize error in sw2hw cq!"); + end + if (vseq.cfg_mbx[host_id].try_put(sw2hw_cq_item) == 0) begin + `uvm_fatal("TRY_PUT_ERROR", "try_put failed in sw2hw_cq in config_agent!"); + end; + endtask: sw2hw_cq + + // phys addr must be 4K aligned!!!! + function addr write_mtt(int host_id, addr phys_addr, int page_num, int temp = 0); + hca_pcie_item write_mtt_item; + addr phys_addr_pcie; + mtt temp_mtt; + addr temp_index; + + icm_vaddr.mtt_cap_left[host_id] = icm_vaddr.mtt_cap_left[host_id] - page_num * 8; + if (icm_vaddr.mtt_cap_left[host_id] < 0) begin + `uvm_fatal("ICM_ERR", $sformatf("MTT capacity out!")); + end + + write_mtt_item = hca_pcie_item::type_id::create("write_mtt_item"); + assert(write_mtt_item.randomize() with {hcr_op == `CMD_WRITE_MTT; num_mtt == page_num;}) + else begin + `uvm_fatal("RANDOMIZE_ERROR", "randomize error in write mtt!"); + end + if (page_num > 255) begin + `uvm_fatal("WRITE_MTT_ERR", "maximum page num exceeded!"); + end + // calculate start index + temp_index = mem_info.mem_table[host_id].size(); + + // send write mtt pcie item to sequence + write_mtt_item.mtt_item.start_index = temp_index; + phys_addr_pcie = phys_addr; + // `uvm_info("MTT_NOTICE", $sformatf("write_mtt start index: %h", temp_index), UVM_LOW); + for (int i = 0; i < page_num; i++) begin + write_mtt_item.mtt_item.phys_addr.push_back(phys_addr_pcie); + // `uvm_info("MTT_NOTICE", $sformatf("write_mtt phys addr: %h", phys_addr_pcie), UVM_LOW); + phys_addr_pcie += `PAGE_SIZE; + end + vseq.cfg_mbx[host_id].try_put(write_mtt_item); + + // push mtt items to queue + temp_mtt.index = temp_index; + temp_mtt.phys_addr = phys_addr; + for (int i = 0; i < page_num; i++) begin + mem_info.mem_table[host_id].push_back(temp_mtt); + temp_mtt.index++; + temp_mtt.phys_addr += `PAGE_SIZE; + end + return temp_index; + endfunction: write_mtt + + task close_hca(int host_id); + hca_pcie_item close_hca_item; + `uvm_info("NOTICE", "close hca begin in test", UVM_LOW); + close_hca_item = hca_pcie_item::type_id::create("close_hca_item"); + assert(close_hca_item.randomize() with {hcr_op == `CMD_CLOSE_HCA;}) + else begin + `uvm_fatal("RANDOMIZE_ERROR", "randomize error in close hca!"); + end + vseq.cfg_mbx[host_id].try_put(close_hca_item); + endtask: close_hca + + //------------------------------------------------------------------------------ + // func name : query_adapter + // function : query device id + // invoked : by gen_item + //------------------------------------------------------------------------------ + task query_adapter(int host_id); + hca_pcie_item query_adapter_item; + query_adapter_item = hca_pcie_item::type_id::create("query_adapter_item"); + assert(query_adapter_item.randomize() with {hcr_op == `CMD_QUERY_ADAPTER;}) + else begin + `uvm_fatal("RANDOMIZE_ERROR", "randomize error in query adapter!"); + end + vseq.cfg_mbx[host_id].try_put(query_adapter_item); + endtask: query_adapter + + //------------------------------------------------------------------------------ + // func name : query_dev_lim + // function : query device limit information + // invoked : by gen_item + //------------------------------------------------------------------------------ + task query_dev_lim(int host_id); + hca_pcie_item quety_dev_lim_item; + quety_dev_lim_item = hca_pcie_item::type_id::create("quety_dev_lim_item"); + assert(quety_dev_lim_item.randomize() with {hcr_op == `CMD_QUERY_DEV_LIM;}) + else begin + `uvm_fatal("RANDOMIZE_ERROR", "randomize error in query dev lim!"); + end + vseq.cfg_mbx[host_id].try_put(quety_dev_lim_item); + endtask: query_dev_lim + + task sw2hw_mpt(int host_id, mpt mpt_item); + icm_vaddr.mpt_cap_left[host_id] -= `MPT_ENTRY_SZ; + if (icm_vaddr.mpt_cap_left[host_id] < 0) begin + `uvm_fatal("ICM_ERR", $sformatf("MPT capacity out!")); + end + + pcie_item = hca_pcie_item::type_id::create("pcie_item"); + pcie_item.mpt_item = mpt_item; + assert(pcie_item.randomize() with {hcr_op == `CMD_SW2HW_MPT;}) + else begin + `uvm_fatal("RANDOMIZE_ERROR", "randomize error in sw2hw mpt!"); + end + vseq.cfg_mbx[host_id].try_put(pcie_item); + mem_info.mem_region[host_id].push_back(mpt_item); + endtask: sw2hw_mpt + +endclass: hca_config_agent +`endif \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/verification/src/vrf_HTN/sv/test/test_config.sv b/ETH-PLUS_Jingzhao/JingZhao2/verification/src/vrf_HTN/sv/test/test_config.sv new file mode 100644 index 0000000000000000000000000000000000000000..cabd9d9f84fd1f21f72cf6f74c9054d69407b817 --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/verification/src/vrf_HTN/sv/test/test_config.sv @@ -0,0 +1,389 @@ +//CREATE INFORMATION +//---------------------------------------------------------------------------- +// +// (C) COPYRIGHT 2021 BY ICT-HPC CORPORATION ALL RIGHTS RESERVED +// DATE : 2021-03-17 +// AUTHOR : mazhenlong@ncic.ac.cn +// FILENAME : test_config.sv +// FUNCTION : This file supplies the case for testing configuration of HCA. +// +//---------------------------------------------------------------------------- + +//CHANGE HISTORY +//---------------------------------------------------------------------------- +// +// AUTHOR DATE VERSION REASON +// mazhenlong 2021-03-17 v1.0 create +// mazhenlong 2021-04-29 v1.1 extend gen_item to all cmds +// mazhenlong 2021-06-26 v1.2 add address management +// add communication test +// +//---------------------------------------------------------------------------- + +`ifndef __TEST_CONFIG__ +`define __TEST_CONFIG__ + +//------------------------------------------------------------------------------ +// +// CLASS: test_config +// +//------------------------------------------------------------------------------ +class test_config extends uvm_test; + string seq_name; + hca_env env; + hca_vsequence vseq; + hca_pcie_item pcie_item; + hca_fifo #(.width(256)) data_fifo; + bit [256/`BYTE_BIT_WIDTH-1:0][`BYTE_BIT_WIDTH-1:0] data; + int host_num = 1; + + bit [`ADDR_WIDTH - 1 : 0] qpc_virt_addr[][$]; + bit [`ADDR_WIDTH - 1 : 0] cqc_virt_addr[][$]; + bit [`ADDR_WIDTH - 1 : 0] mpt_virt_addr[][$]; + bit [`ADDR_WIDTH - 1 : 0] mtt_virt_addr[][$]; + + bit [`ADDR_WIDTH - 1 : 0] data_virt_addr[][$]; + bit [`ADDR_WIDTH - 1 : 0] data_phys_addr[][$]; + + `uvm_component_utils(test_config) + + //------------------------------------------------------------------------------ + // function name : new + // function : constructor + // invoked : invoked when instantiates the class + //------------------------------------------------------------------------------ + function new(string name = "test_config", uvm_component parent=null); + super.new(name,parent); + endfunction : new + + //------------------------------------------------------------------------------ + // function name : build_phase + // function : build_phase in uvm library, instantiates env and sequence. + // invoked : automatically by uvm + //------------------------------------------------------------------------------ + virtual function void build_phase(uvm_phase phase); + super.build_phase(phase); + qpc_virt_addr = new[host_num]; + cqc_virt_addr = new[host_num]; + mpt_virt_addr = new[host_num]; + mtt_virt_addr = new[host_num]; + data_phys_addr = new[host_num]; + env = hca_env::type_id::create("env", this); + vseq = hca_vsequence::type_id::create("vseq", this); + if (!$value$plusargs("HCA_CASE_NAME=%s", seq_name)) begin + `uvm_warning("test_config", "SEQ_NAME NOT GET!") + end + data_fifo = hca_fifo#(.width(256))::type_id::create("data_fifo"); + endfunction: build_phase + + //------------------------------------------------------------------------------ + // function name : connect_phase + // function : connect_phase in uvm library, connect mem in env with in seq + // invoked : automatically by uvm + //------------------------------------------------------------------------------ + function void connect_phase(uvm_phase phase); + string test_name; + super.connect_phase(phase); + for (int i = 0; i < host_num; i++) begin + vseq.cfg_seq[i].mem = env.mem[i]; + end + endfunction: connect_phase + + //------------------------------------------------------------------------------ + // task name : main_phase + // function : main_phase in uvm library, start vseq. + // invoked : automatically by uvm + //------------------------------------------------------------------------------ + task main_phase(uvm_phase phase); + // super.main_phase(phase); + phase.raise_objection(this); + gen_item(); + `uvm_info("NOTICE", "generate item finished!", UVM_LOW) + vseq.starting_phase = phase; + for (int i = 0; i < host_num; i++) begin + vseq.cfg_seq[i].mem = env.mem[i]; + vseq.slv_seq[i].mem = env.mem[i]; + end + vseq.start(env.vsqr, , , 1); + `uvm_info("NOTICE", "vseq finished!", UVM_LOW) + phase.drop_objection(this); + endtask: main_phase + + //------------------------------------------------------------------------------ + // task name : gen_item + // function : generate initial item. + // invoked : by build_phase + //------------------------------------------------------------------------------ + task gen_item(); + case (seq_name) + "test_db_seq": begin + doorbell db; + post_db(db); + end + "test_init_hca_seq": begin + init_hca(); + end + "test_close_hca_seq": begin + init_hca(); + close_hca(); + end + "test_query_adapter_seq": begin + query_adapter(); + end + "test_query_dev_lim_seq": begin + query_dev_lim(); + end + "test_query_dev_info_seq": begin + query_dev_lim(); + query_adapter(); + init_hca(); + end + "test_map_icm_seq": begin + init_hca(); + map_icm(1); + map_icm(2); + map_icm(3); + map_icm(4); + end + "test_unmap_icm_seq": begin + pcie_item.randomize() with {hcr_op == `CMD_UNMAP_ICM;}; + end + "test_hw2sw_cq_seq": begin + pcie_item.randomize() with {hcr_op == `CMD_HW2SW_CQ;}; + end + "test_sw2hw_cq_seq": begin + pcie_item.randomize() with {hcr_op == `CMD_SW2HW_CQ;}; + end + "test_modify_qp_seq": begin + qp_context qp_ctx; + init_hca(); + map_icm(1); // map icm space for qp + // modify_qp(create_qpc()); + query_qp(2); + end + // "test_modify_qp_rst_seq": begin + + // end + // "test_resize_cq_seq": begin + // pcie_item.randomize() with {hcr_op == `CMD_RESIZE_CQ;}; + // end + // "test_hw2sw_mpt_seq": begin + // pcie_item.randomize() with {hcr_op == `CMD_HW2SW_MPT;}; + // end + // "test_sw2hw_mpt_seq": begin + // pcie_item.randomize() with {hcr_op == `CMD_SW2HW_MPT;}; + // end + // "test_write_mtt_seq": begin + // write_mtt(); + // end + // "test_full_cmd_seq": begin + // init_hca(); + + // end + "test_comm_seq": begin + simple_comm(); + end + "test_random_comm": begin + + end + endcase + endtask: gen_item + + task init_hca(); + hca_pcie_item init_hca_item; + init_hca_item = hca_pcie_item::type_id::create("init_hca_item", this); + init_hca_item.randomize() with {hcr_op == `CMD_INIT_HCA;}; + init_hca_item.icm_base_struct.qpc_base = `QPC_OFFSET; + init_hca_item.icm_base_struct.cqc_base = `CQC_OFFSET; + init_hca_item.icm_base_struct.eqc_base = `EQC_OFFSET; + init_hca_item.icm_base_struct.mpt_base = `MPT_OFFSET; + init_hca_item.icm_base_struct.mtt_base = `MTT_OFFSET; + init_hca_item.icm_base_struct.log_num_qps = `LOG_NUM_QPS; + init_hca_item.icm_base_struct.log_num_cqs = `LOG_NUM_CQS; + init_hca_item.icm_base_struct.log_num_eqs = `LOG_NUM_EQS; + init_hca_item.icm_base_struct.log_mpt_sz = `LOG_MPT_SZ; + vseq.cfg_item_que[0].push_back(init_hca_item); + endtask: init_hca + + function bit [63:0] map_icm(int m_type); // m_type: 1: qp context; 2: cq context; 3: mpt; 4: mtt; + // return the virtual address of the mapped page in ICM space; + // currently support only one page + hca_pcie_item map_icm_item; + bit [63:0] temp_virt_addr; + bit [63:0] temp_phys_addr; + int i; + bit flag = 0; + + if (m_type == 1) begin + temp_virt_addr = `QPC_OFFSET; + foreach (qpc_virt_addr[0][i]) begin + if (qpc_virt_addr[0][i] == temp_virt_addr) begin + temp_virt_addr += 4096; + end + else begin + qpc_virt_addr[0].insert(i, temp_virt_addr); + flag = 1; + break; + end + end + if (flag == 0) begin + qpc_virt_addr[0].push_back(temp_virt_addr); + end + end + else if (m_type == 2) begin + temp_virt_addr = `CQC_OFFSET; + foreach (cqc_virt_addr[0][i]) begin + if (cqc_virt_addr[0][i] == temp_virt_addr) begin + temp_virt_addr += 4096; + end + else begin + cqc_virt_addr[0].insert(i, temp_virt_addr); + flag = 1; + break; + end + end + if (flag == 0) begin + cqc_virt_addr[0].push_back(temp_virt_addr); + end + end + else if (m_type == 3) begin + temp_virt_addr = `MPT_OFFSET; + foreach (mpt_virt_addr[0][i]) begin + if (mpt_virt_addr[0][i] == temp_virt_addr) begin + temp_virt_addr += 4096; + end + else begin + mpt_virt_addr[0].insert(i, temp_virt_addr); + flag = 1; + break; + end + end + if (flag == 0) begin + mpt_virt_addr[0].push_back(temp_virt_addr); + end + end + else if (m_type == 4) begin + temp_virt_addr = `MTT_OFFSET; + foreach (mtt_virt_addr[0][i]) begin + if (mtt_virt_addr[0][i] == temp_virt_addr) begin + temp_virt_addr += 4096; + end + else begin + mtt_virt_addr[0].insert(i, temp_virt_addr); + flag = 1; + break; + end + end + if (flag == 0) begin + mtt_virt_addr[0].push_back(temp_virt_addr); + end + end + else begin + `uvm_fatal("ILG_INPUT", "illegal m_type in map_icm!"); + end + + map_icm_item = hca_pcie_item::type_id::create("map_icm_item", this); + map_icm_item.randomize() with {hcr_op == `CMD_MAP_ICM; map_type == m_type;}; + map_icm_item.icm_addr_map.virt.push_back(temp_virt_addr); + map_icm_item.icm_addr_map.page.push_back(temp_virt_addr + `ICM_BASE); + map_icm_item.icm_addr_map.page_num = 1; + vseq.cfg_item_que[0].push_back(map_icm_item); + return temp_virt_addr; + endfunction: map_icm + + //------------------------------------------------------------------------------ + // task name : modify_qp + // function : generate and send modify qp item. + // invoked : by gen_item + //------------------------------------------------------------------------------ + task modify_qp(qp_context qp_ctx); + pcie_item = hca_pcie_item::type_id::create("pcie_item", this); + pcie_item.qp_ctx = qp_ctx; + pcie_item.randomize() with {hcr_op == `CMD_RST2INIT_QPEE;};// qp_num == 2;}; + + vseq.cfg_item_que[0].push_back(pcie_item); + endtask: modify_qp + + //------------------------------------------------------------------------------ + // task name : query_qp + // function : generate and send query qp item. + // invoked : by gen_item + //------------------------------------------------------------------------------ + task query_qp(int qpn); + pcie_item = hca_pcie_item::type_id::create("pcie_item", this); + pcie_item.randomize() with {hcr_op == `CMD_QUERY_QP; hcr_in_modifier == qpn;}; + vseq.cfg_item_que[0].push_back(pcie_item); + endtask: query_qp + + function bit [63:0] write_mtt(bit [63:0] start_index); // input is the ICM virtual address of mtt item + // currently not support modify mtt item + int i; + bit [63:0] temp = `DATA_BASE; + pcie_item = hca_pcie_item::type_id::create("pcie_item", this); + pcie_item.randomize() with {hcr_op == `CMD_WRITE_MTT; num_mtt == 1;}; + pcie_item.mtt_item.start_index = start_index; + foreach (data_phys_addr[0][i]) begin + if (temp == data_phys_addr[0][i]) begin + temp += 4096; + end + end + data_phys_addr[0].push_back(temp); + pcie_item.mtt_item.phys_addr.push_back(temp); + vseq.cfg_item_que[0].push_back(pcie_item); + `uvm_info("MTT_MOTICE", $sformatf("write_mtt phys addr: %h", temp), UVM_LOW); + `uvm_info("MTT_MOTICE", $sformatf("write_mtt start index: %h", start_index), UVM_LOW); + return temp; + endfunction: write_mtt + + task close_hca(); + `uvm_info("NOTICE", "close hca begin in test", UVM_LOW); + pcie_item = hca_pcie_item::type_id::create("pcie_item", this); + pcie_item.randomize() with {hcr_op == `CMD_CLOSE_HCA;}; + vseq.cfg_item_que[0].push_back(pcie_item); + endtask: close_hca + + //------------------------------------------------------------------------------ + // func name : query_adapter + // function : query device id + // invoked : by gen_item + //------------------------------------------------------------------------------ + task query_adapter(); + pcie_item = hca_pcie_item::type_id::create("pcie_item", this); + pcie_item.randomize() with {hcr_op == `CMD_QUERY_ADAPTER;}; + vseq.cfg_item_que[0].push_back(pcie_item); + endtask: query_adapter + + //------------------------------------------------------------------------------ + // func name : query_dev_lim + // function : query device limit information + // invoked : by gen_item + //------------------------------------------------------------------------------ + task query_dev_lim(); + pcie_item = hca_pcie_item::type_id::create("pcie_item", this); + pcie_item.randomize() with {hcr_op == `CMD_QUERY_DEV_LIM;}; + vseq.cfg_item_que[0].push_back(pcie_item); + endtask: query_dev_lim + + task sw2hw_mpt(mpt mpt_item); + pcie_item = hca_pcie_item::type_id::create("pcie_item", this); + pcie_item.mpt_item = mpt_item; + pcie_item.randomize() with {hcr_op == `CMD_SW2HW_MPT;}; + vseq.cfg_item_que[0].push_back(pcie_item); + endtask: sw2hw_mpt + + task post_db(doorbell db); + pcie_item = hca_pcie_item::type_id::create("db_item", this); + pcie_item.item_type = DOORBELL; + pcie_item.db = db; + vseq.comm_item_que[0].push_back(pcie_item); + endtask: post_db + + function bit [256/`BYTE_BIT_WIDTH-1:0][`BYTE_BIT_WIDTH-1:0] trans2comb(bit [255:0] raw_data); + bit [256/`BYTE_BIT_WIDTH-1:0][`BYTE_BIT_WIDTH-1:0] result; + for (int i = 0; i < 32; i++) begin + result[i] = raw_data[i * 8 + 7 -: 8]; + end + return result; + endfunction +endclass: test_config +`endif \ No newline at end of file diff --git a/ETH-PLUS_Jingzhao/JingZhao2/verification/src/vrf_HTN/sv/test/test_direct_param.sv b/ETH-PLUS_Jingzhao/JingZhao2/verification/src/vrf_HTN/sv/test/test_direct_param.sv new file mode 100644 index 0000000000000000000000000000000000000000..ee4999f374cb7799ee481a209e3eb802d800329c --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/verification/src/vrf_HTN/sv/test/test_direct_param.sv @@ -0,0 +1,1120 @@ +//CREATE INFORMATION +//---------------------------------------------------------------------------- +// +// (C) COPYRIGHT 2021 BY ICT-HPC CORPORATION ALL RIGHTS RESERVED +// DATE : 2021-07-30 +// AUTHOR : mazhenlong@ncic.ac.cn +// FILENAME : test_direct_param.sv +// FUNCTION : This file supplies the case for testing configuration of HCA. +// +//---------------------------------------------------------------------------- + +//CHANGE HISTORY +//---------------------------------------------------------------------------- +// +// AUTHOR DATE VERSION REASON +// mazhenlong 2021-07-30 v1.0 create +// mazhenlong 2022-07-03 v1.1 fix wqe start address bug +// +//---------------------------------------------------------------------------- + +`ifndef __TEST_DIRECT_PARAM__ +`define __TEST_DIRECT_PARAM__ + +//------------------------------------------------------------------------------ +// +// CLASS: test_direct +// +//------------------------------------------------------------------------------ +class test_direct_param extends uvm_test; + string seq_name; + // string serv_type; + // string comm_type; + string data_unit; + hca_env env; + hca_vsequence vseq; + hca_pcie_item pcie_item; + hca_fifo #(.width(256)) data_fifo; + bit [256/`BYTE_BIT_WIDTH-1:0][`BYTE_BIT_WIDTH-1:0] data; + int host_num; + int proc_num; + int db_num; + int wqe_num; + int page_num; + int sg_num; + int rc_qp_num; + string case_id; + int uc_qp_num; + int ud_qp_num; + int write_wqe_num; + int read_wqe_num; + int send_wqe_num; + int recv_wqe_num; + hca_queue_list q_list; + hca_icm_vaddr icm_vaddr; + hca_mem_info mem_info; + hca_math_func math; + hca_config_agent cfg_agt; + hca_check_mem_list check_list; + mailbox glb_stop_mbx; + int max_sg_num = 6; + string begin_time; + string end_time; + int fp; + + bit [31:0] wqe_data_count; // data amount in every WQE + int raw_data_cnt; + int sg_data_cnt; // data amount in every sg entry + + `uvm_component_utils(test_direct_param) + + //------------------------------------------------------------------------------ + // function name : new + // function : constructor + // invoked : invoked when instantiates the class + //------------------------------------------------------------------------------ + function new(string name = "test_direct_param", uvm_component parent=null); + super.new(name,parent); + endfunction : new + + //------------------------------------------------------------------------------ + // function name : build_phase + // function : build_phase in uvm library, instantiates env and sequence. + // invoked : automatically by uvm + //------------------------------------------------------------------------------ + virtual function void build_phase(uvm_phase phase); + super.build_phase(phase); + + begin_time = get_sys_time(); + + // if (!$value$plusargs("CASE_NAME=%s", seq_name)) begin + // `uvm_fatal("PARAM_ERROR", "seq name not get!"); + // end + + if (!$value$plusargs("HOST_NUM=%d", host_num)) begin + `uvm_fatal("PARAM_ERROR", "host num not get!"); + end + if (host_num > `MAX_HOST_NUM) begin + `uvm_fatal("PARAM_ERROR", "host num maximum exceeded!"); + end + + if (!$value$plusargs("CASEID=%s", case_id)) begin + `uvm_fatal("PARAM_ERROR", "case_id not get!"); + end + + if (!$value$plusargs("PROC_NUM=%d", proc_num)) begin + `uvm_fatal("PARAM_ERROR", "process num not get!"); + end + if (proc_num > `MAX_PROC_NUM) begin + `uvm_fatal("PARAM_ERROR", "process num maximum exceeded!"); + end + if (proc_num < 2) begin + `uvm_fatal("PARAM_ERROR", "process num should be larger than 1!"); + end + + if (!$value$plusargs("DB_NUM=%d", db_num)) begin + `uvm_fatal("PARAM_ERROR", "doorbell num not get!"); + end + if (db_num > `MAX_DB_NUM) begin + `uvm_fatal("PARAM_ERROR", "doorbell num maximum exceeded!"); + end + + // if (!$value$plusargs("HCA_PAGE_NUM=%d", page_num)) begin + // `uvm_fatal("PARAM_ERROR", "page num not get!"); + // end + // if(page_num > `MAX_PAGE_NUM) begin + // `uvm_fatal("PARAM_ERROR", "page num maximum exceeded!"); + // end + + if (!$value$plusargs("DATA_CNT=%d", raw_data_cnt)) begin + `uvm_fatal("PARAM_ERROR", "sg_data_count not get!"); + end + + if (!$value$plusargs("DATA_UNIT=%s", data_unit)) begin + `uvm_fatal("PARAM_ERROR", "data_unit not get!"); + end + if (data_unit == "B") begin + sg_data_cnt = raw_data_cnt; + end + else if (data_unit == "KB") begin + sg_data_cnt = raw_data_cnt * 1024; + end + else if (data_unit == "MB") begin + sg_data_cnt = raw_data_cnt * 1024 * 1024; + end + else if (data_unit == "GB") begin + sg_data_cnt = raw_data_cnt * 1024 * 1024 * 1024; + end + else begin + `uvm_fatal("PARAM_ERROR", "Illegal data_unit!"); + end + + if (!$value$plusargs("SG_NUM=%d", sg_num)) begin + `uvm_fatal("PARAM_ERROR", "sg num not get!"); + end + if (sg_num > max_sg_num) begin + `uvm_fatal("PARAM_ERROR", $sformatf("sg num exceeds maximum: %0d, set: %0d!", max_sg_num, sg_num)); + end + + if (!$value$plusargs("RC_QP_NUM=%d", rc_qp_num)) begin + `uvm_fatal("PARAM_ERROR", "RC QP num not get!"); + end + if (!$value$plusargs("UC_QP_NUM=%d", uc_qp_num)) begin + `uvm_fatal("PARAM_ERROR", "UC QP num not get!"); + end + if (!$value$plusargs("UD_QP_NUM=%d", ud_qp_num)) begin + `uvm_fatal("PARAM_ERROR", "UD QP num not get!"); + end + if (rc_qp_num + uc_qp_num + ud_qp_num > `MAX_QP_NUM) begin + `uvm_fatal("PARAM_ERROR", $sformatf("Too many QPs!")); + end + + if (!$value$plusargs("WRITE_WQE_NUM=%d", write_wqe_num)) begin + `uvm_fatal("PARAM_ERROR", "WRITE WQE num not get!"); + end + if (!$value$plusargs("READ_WQE_NUM=%d", read_wqe_num)) begin + `uvm_fatal("PARAM_ERROR", "READ WQE num not get!"); + end + if (!$value$plusargs("SEND_WQE_NUM=%d", send_wqe_num)) begin + `uvm_fatal("PARAM_ERROR", "SEND WQE num not get!"); + end + if (!$value$plusargs("RECV_WQE_NUM=%d", recv_wqe_num)) begin + `uvm_fatal("PARAM_ERROR", "RECV WQE num not get!"); + end + if (send_wqe_num != recv_wqe_num) begin + `uvm_fatal("PARAM_ERROR", "send_wqe_num != recv_wqe_num!"); + end + if (write_wqe_num + read_wqe_num + send_wqe_num > `MAX_WQE_NUM) begin + `uvm_fatal("PARAM_ERROR", "Too many WQEs!"); + end + + wqe_num = write_wqe_num + recv_wqe_num + read_wqe_num + send_wqe_num; + + env = hca_env::type_id::create("env", this); + env.host_num = this.host_num; + vseq = hca_vsequence::type_id::create("vseq", this); + vseq.init(this.host_num); + data_fifo = hca_fifo#(.width(256))::type_id::create("data_fifo"); + math = hca_math_func::type_id::create("math"); + + q_list = hca_queue_list::type_id::create("q_list"); + q_list.init(host_num); + + icm_vaddr = hca_icm_vaddr::type_id::create("icm_vaddr"); + icm_vaddr.init(host_num); + + mem_info = hca_mem_info::type_id::create("mem_info"); + mem_info.init(host_num); + + cfg_agt = hca_config_agent::type_id::create("cfg_agt"); + cfg_agt.init(vseq, icm_vaddr, mem_info); + + check_list = hca_check_mem_list::type_id::create("check_list"); + check_list.init(host_num); + + glb_stop_mbx = new(); + uvm_config_db#(mailbox)::set(uvm_root::get(), "*.env.scb*", "glb_stop_mbx", glb_stop_mbx); + `uvm_info("NOTICE", "global stop mailbox send finished!", UVM_LOW); + + uvm_config_db#(hca_queue_list)::set(uvm_root::get(), "*.env.rm*", "q_list", q_list); + `uvm_info("NOTICE", "queue list sent to rm finished!", UVM_LOW); + + uvm_config_db#(hca_queue_list)::set(uvm_root::get(), "*.slv_*", "q_list", q_list); + `uvm_info("NOTICE", "queue list sent to slave finished!", UVM_LOW); + + uvm_config_db#(hca_icm_vaddr)::set(uvm_root::get(), "*.env.rm*", "icm_vaddr", icm_vaddr); + `uvm_info("NOTICE", "icm vaddr send finished!", UVM_LOW); + + uvm_config_db#(hca_mem_info)::set(uvm_root::get(), "*.env.rm*", "mem_info", mem_info); + `uvm_info("NOTICE", "mem info send finished!", UVM_LOW); + + uvm_config_db#(hca_queue_list)::set(uvm_root::get(), "*.env.scb", "q_list", q_list); + `uvm_info("NOTICE", "q_list send finished!", UVM_LOW); + + uvm_config_db#(hca_check_mem_list)::set(uvm_root::get(), "*.env.scb", "check_list", check_list); + `uvm_info("NOTICE", "check_list send finished!", UVM_LOW); + + endfunction: build_phase + + //------------------------------------------------------------------------------ + // function name : connect_phase + // function : connect_phase in uvm library, connect mem in env with in seq + // invoked : automatically by uvm + //------------------------------------------------------------------------------ + function void connect_phase(uvm_phase phase); + string test_name; + super.connect_phase(phase); + + for (int i = 0; i < host_num; i++) begin + vseq.cfg_seq[i].mem = env.mem[i]; + vseq.slv_seq[i].mem = env.mem[i]; + end + endfunction: connect_phase + + //------------------------------------------------------------------------------ + // task name : main_phase + // function : main_phase in uvm library, start vseq. + // invoked : automatically by uvm + //------------------------------------------------------------------------------ + task main_phase(uvm_phase phase); + // super.main_phase(phase); + phase.raise_objection(this); + fork + begin + wqe_data_count = sg_num * sg_data_cnt; + test_direct(); + `uvm_info("NOTICE", "generate item finished!", UVM_LOW) + end + begin + vseq.starting_phase = phase; + vseq.start(env.vsqr, , , 1); + `uvm_info("NOTICE", "vseq finished!", UVM_LOW) + end + join + phase.drop_objection(this); + endtask: main_phase + + //------------------------------------------------------------------------------ + // function name : report_phase + // function : print result and time + // invoked : automatically by uvm + //------------------------------------------------------------------------------ + function void report_phase(uvm_phase phase); + super.report_phase(phase); + end_time = get_sys_time(); + `uvm_info("TIME_INFO", $sformatf("begin time: %s", begin_time), UVM_LOW); + `uvm_info("TIME_INFO", $sformatf("end time: %s", end_time), UVM_LOW); + endfunction: report_phase + + function string get_sys_time(); + string sys_time; + int fp; + $system("date +%Y-%m-%d' '%H:%M:%S > sys_time"); + fp = $fopen("sys_time", "r"); + $fgets(sys_time, fp); + $fclose(fp); + $system("rm sys_time"); + return sys_time; + endfunction: get_sys_time + + //------------------------------------------------------------------------------ + // task name : test_direct + // function : initialize HCA, create CQs and QPs, connect QPs, write data, + // write WQEs, send doorbell + // invoked : by gen_item_seq + //------------------------------------------------------------------------------ + task test_direct(); + int proc_id = 1; + + // initialize HCA + for (int host_id = 0; host_id < host_num; host_id++) begin + cfg_agt.query_adapter(host_id); + cfg_agt.init_hca(host_id); + // cfg_agt.write_ivt(host_id); + end + + // create EQ, CQ and QP + for (int host_id = 0; host_id < host_num; host_id++) begin + fork + automatic int a_host_id = host_id; + begin + e_service_type service_type; + addr cqc_start_addr; + addr qpc_start_addr; + hca_queue_pair qp; + hca_comp_queue temp_cq; + bit [31:0] pd; + + // create RC QPs + for (int i = 0; i < rc_qp_num; i++) begin + pd = $urandom(); + service_type = RC; + + // create CQ + // cqc_start_addr = cfg_agt.map_icm(a_host_id, `ICM_CQC_TYP, 1); // is this enough? + temp_cq = create_cq(proc_id, a_host_id, pd); + + // create QP, should data MR be created here? + // qpc_start_addr = cfg_agt.map_icm(a_host_id, `ICM_QPC_TYP, 1); // is this enough? + qp = create_qp(proc_id, a_host_id, pd, service_type, temp_cq, temp_cq); + end + + // create UC QPs + for (int i = 0; i < uc_qp_num; i++) begin + pd = $urandom(); + service_type = UC; + + // create CQ + // cqc_start_addr = cfg_agt.map_icm(a_host_id, `ICM_CQC_TYP, 1); // is this enough? + temp_cq = create_cq(proc_id, a_host_id, pd); + + // create QP, should data MR be created here? + // qpc_start_addr = cfg_agt.map_icm(a_host_id, `ICM_QPC_TYP, 1); // is this enough? + qp = create_qp(proc_id, a_host_id, pd, service_type, temp_cq, temp_cq); + end + + // create UD QPs + for (int i = 0; i < ud_qp_num; i++) begin + pd = $urandom(); + service_type = UD; + + // create CQ + // cqc_start_addr = cfg_agt.map_icm(a_host_id, `ICM_CQC_TYP, 1); // is this enough? + temp_cq = create_cq(proc_id, a_host_id, pd); + + // create QP, should data MR be created here? + // qpc_start_addr = cfg_agt.map_icm(a_host_id, `ICM_QPC_TYP, 1); // is this enough? + qp = create_qp(proc_id, a_host_id, pd, service_type, temp_cq, temp_cq); + end + end + join_none + end + wait fork; + + // connect QP, QP[2n] in host 0 is connected with QP[2n+1] in host 1 and vice versa + // WARNING: only support TWO hosts + // QPs of UD should not be connected, but this can be ignored here + for (int i = 0; i < q_list.qp_list[0].size(); i++) begin + hca_queue_pair qp_a; + hca_queue_pair qp_b; + int flag = 0; + qp_a = q_list.qp_list[0][i]; + // if (qp_a.ctx.flags[15:0] != 16'h0000 || qp_a.ctx.flags[15:0] != 16'h0001) begin + // continue; + // end + if (qp_a.ctx.local_qpn % 2 == 0) begin + for (int j = 0; j < q_list.qp_list[1].size(); j++) begin + if (q_list.qp_list[1][j].ctx.local_qpn == qp_a.ctx.local_qpn + 1) begin + qp_b = q_list.qp_list[1][j]; + connect_qp(0, qp_a, 1, qp_b); + flag = 1; + break; + end + end + // if not found qp_b + if (flag == 0) begin + `uvm_fatal("CONNECT_QP_ERR", $sformatf("qp_b not found! qp_a: %h", qp_a.ctx.local_qpn)); + end + end + else begin + for (int j = 0; j < q_list.qp_list[1].size(); j++) begin + if (q_list.qp_list[1][j].ctx.local_qpn == qp_a.ctx.local_qpn - 1) begin + qp_b = q_list.qp_list[1][j]; + connect_qp(0, qp_a, 1, qp_b); + flag = 1; + break; + end + end + // if not found qp_b + if (flag == 0) begin + `uvm_fatal("CONNECT_QP_ERR", $sformatf("qp_b not found! qp_a: %h", qp_a.ctx.local_qpn)); + end + end + `ifdef QUERY_QP_TEST + cfg_agt.query_qp(0, qp_a.ctx.local_qpn); + cfg_agt.query_qp(1, qp_b.ctx.local_qpn); + `endif + end + + // write data into data region + for (int host_id = 0; host_id < host_num; host_id++) begin + for (int i = 0; i < q_list.qp_list[host_id].size(); i++) begin + hca_queue_pair qp; + addr data_paddr; + addr data_vaddr; + qp = q_list.qp_list[host_id][i]; + data_paddr = `PA_DATA(proc_id, qp.ctx.local_qpn); + data_vaddr = `VA(data_paddr); + write_test_data(host_id, data_paddr, db_num * wqe_data_count * wqe_num); + end + `uvm_info("NOTICE", "write test data finished!", UVM_LOW); + end + + for (int db_id = 0; db_id < db_num; db_id++) begin + // create data MR, create WQE and write + for (int host_id = 0; host_id < host_num; host_id++) begin + // for every QP + for (int i = 0; i < q_list.qp_list[host_id].size(); i++) begin + fork + automatic int j = i; + begin + hca_queue_pair qp; + qp = q_list.qp_list[host_id][j]; + create_and_write_wqes(qp, db_id, wqe_data_count, send_wqe_num, recv_wqe_num, read_wqe_num, write_wqe_num, sg_num, sg_data_cnt); + end + join_none + end + wait fork; + end + + for (int host_id = 0; host_id < host_num; host_id++) begin + hca_pcie_item batch_item; + batch_item = hca_pcie_item::type_id::create("BATCH_ITEM", this); + batch_item.item_type = BATCH; + vseq.cfg_mbx[host_id].put(batch_item); + end + + // write doorbell + for (int host_id = 0; host_id < host_num; host_id++) begin + + //only host 0 can send + if (host_id == 1) begin + break; + end + + fork + automatic int a_host_id = host_id; + // for every host + begin + for (int i = 0; i < q_list.qp_list[a_host_id].size(); i++) begin + fork + automatic int j = i; + begin + hca_queue_pair qp; + bit [4:0] opcode; + qp = q_list.qp_list[a_host_id][j]; + if (send_wqe_num != 0) begin + opcode = `VERBS_SEND; + send_db(a_host_id, proc_id, db_id, qp, opcode); + end + else if (write_wqe_num != 0 && qp.ctx.flags[23:16] != `HGHCA_QP_ST_UD) begin + opcode = `VERBS_RDMA_WRITE; + send_db(a_host_id, proc_id, db_id, qp, opcode); + end + else if (read_wqe_num != 0 && qp.ctx.flags[23:16] == `HGHCA_QP_ST_RC) begin + opcode = `VERBS_RDMA_READ; + send_db(a_host_id, proc_id, db_id, qp, opcode); + end + else begin + `uvm_info("DB_INFO", $sformatf("useless QP! qpn: %h", qp.ctx.local_qpn), UVM_LOW); + end + end + join_none + end + wait fork; + end + join_none + end + wait fork; + + global_stop(db_id, db_num); + for (int host_id = 0; host_id < host_num; host_id++) begin + hca_pcie_item batch_item; + batch_item = hca_pcie_item::type_id::create("BATCH_ITEM", this); + batch_item.item_type = BATCH; + vseq.comm_mbx[host_id].put(batch_item); + end + end + endtask: test_direct + + //------------------------------------------------------------------------------ + // task name : create_and_write_wqes + // function : create memory regions for data and generate WQEs of a certain + // communication type in one QP, cmd parameters should not be used + // in this function. + // this task should be implemented in hca_queue_pair + // invoked : by test_direct + //------------------------------------------------------------------------------ + function create_and_write_wqes( + hca_queue_pair qp, + int db_id, + bit [31:0] wqe_data_count, + int send_wqe_num, + int recv_wqe_num, + int read_wqe_num, + int write_wqe_num, + int sg_num, + bit [31:0] sg_entry_data_count + ); + mpt local_mpt; + mpt remote_mpt; + mpt sq_local_mpt_que[$]; // sg entry mpt in SQ data seg + mpt sq_remote_mpt_que[$]; + mpt rq_send_mpt_que[$]; + mpt rq_recv_mpt_que[$]; + addr sq_local_offset_que[$]; + addr sq_remote_offset_que[$]; + addr rq_send_offset_que[$]; + addr rq_recv_offset_que[$]; + e_op_type sq_op_que[$]; + e_op_type rq_op_que[$]; + hca_queue_pair remote_qp; + bit [31:0] remote_qpn; + + int remote_host_id; + int host_id; + bit [10:0] proc_id; + // int sq_wqe_num = send_wqe_num + read_wqe_num + write_wqe_num; + + host_id = qp.host_id; + proc_id = qp.proc_id; + remote_qp = qp.remote_qp; + // remote_qpn = remote_qp.ctx.local_qpn; + + + if (host_id == 0) begin + remote_host_id = 1; + end + else begin + remote_host_id = 0; + end + + // host 1 is not sender + if (host_id == 1) begin + return; + end + + /*------------------------------------------------------------------ + // MEMORY SPACE FOR NETWORK DATA + // RC: + // | SEND | RECEIVE | WRITE | READ | + // UC: + // | SEND | RECEIVE | WRITE | + // UD: + // | SEND | RECEIVE | + ------------------------------------------------------------------*/ + // create data memory regions and put WQEs into mpt queue + for (int wqe_id = 0; wqe_id < send_wqe_num + recv_wqe_num + write_wqe_num + read_wqe_num; wqe_id++) begin + if (wqe_id < send_wqe_num) begin // SEND + // start physical address of THIS DOORBELL + addr src_paddr = `PA_DATA(proc_id, qp.ctx.local_qpn) + db_id * this.wqe_num * wqe_data_count; + addr src_vaddr = `VA(src_paddr); + // start physical address of RECV buffer corresponding to SEND above + addr dst_paddr = `PA_DATA(proc_id, qp.ctx.remote_qpn) + `DATA_RECV_BUFF_GAP + db_id * this.wqe_num * wqe_data_count; + addr dst_vaddr = `VA(dst_paddr); + for (int sg_id = 0; sg_id < sg_num; sg_id++) begin + // create MR for sending data + local_mpt = create_mr( + host_id, + proc_id, + sg_entry_data_count, + src_vaddr + wqe_id * wqe_data_count + sg_id * sg_entry_data_count, + qp.ctx.pd, + `PAGE_SIZE, + FALSE, + 8'b1000_0111 + ); + sq_local_mpt_que.push_back(local_mpt); + rq_send_mpt_que.push_back(local_mpt); + + // set sg entry address offset relative to start address of memory region + sq_local_offset_que.push_back(src_vaddr + wqe_id * wqe_data_count + sg_id * sg_entry_data_count - local_mpt.start); + rq_send_offset_que.push_back(src_vaddr + wqe_id * wqe_data_count + sg_id * sg_entry_data_count - local_mpt.start); + end + sq_op_que.push_back(SEND); + for (int sg_id = 0; sg_id < sg_num; sg_id++) begin + // create MR for data buffer + remote_mpt = create_mr( + remote_host_id, + proc_id, + sg_entry_data_count, + dst_vaddr + wqe_id * wqe_data_count + sg_id * sg_entry_data_count, + remote_qp.ctx.pd, + `PAGE_SIZE, + FALSE, + 8'b1000_0111 + ); + rq_recv_mpt_que.push_back(remote_mpt); + rq_recv_offset_que.push_back(dst_vaddr + wqe_id * wqe_data_count + sg_id * sg_entry_data_count - remote_mpt.start); + end + rq_op_que.push_back(RECV); + end + else if (wqe_id < send_wqe_num + recv_wqe_num) begin // RECEIVE + // no need to work here + end + else if (wqe_id < send_wqe_num + recv_wqe_num + write_wqe_num) begin // WRITE + // start physical address of WRITE source data + addr src_paddr = `PA_DATA(proc_id, qp.ctx.local_qpn) + db_id * this.wqe_num * wqe_data_count; + addr src_vaddr = `VA(src_paddr); + // start physical address of WRITE buffer in receiver side + addr dst_paddr = `PA_DATA(proc_id, qp.ctx.remote_qpn) + `DATA_RECV_BUFF_GAP + db_id * this.wqe_num * wqe_data_count; + addr dst_vaddr = `VA(dst_paddr); + + if (qp.ctx.flags[23:16] == `HGHCA_QP_ST_UD) begin + break; + end + // create data mpt and recv mpt + for (int sg_id = 0; sg_id < sg_num; sg_id++) begin + local_mpt = create_mr( + host_id, + proc_id, + sg_entry_data_count, + src_vaddr + wqe_id * wqe_data_count + sg_id * sg_entry_data_count, + qp.ctx.pd, + `PAGE_SIZE, + FALSE, + 8'b1000_0111 + ); + sq_local_mpt_que.push_back(local_mpt); + sq_local_offset_que.push_back(src_vaddr + wqe_id * wqe_data_count + sg_id * sg_entry_data_count - local_mpt.start); + end + remote_mpt = create_mr( + remote_host_id, + proc_id, + wqe_data_count, + dst_vaddr + wqe_id * wqe_data_count, + remote_qp.ctx.pd, + `PAGE_SIZE, + FALSE, + 8'b1000_0111 + ); + sq_remote_mpt_que.push_back(remote_mpt); + sq_remote_offset_que.push_back(dst_vaddr + wqe_id * wqe_data_count - remote_mpt.start); + + sq_op_que.push_back(WRITE); + end + else if (wqe_id < send_wqe_num + recv_wqe_num + write_wqe_num + read_wqe_num) begin // READ + // start physical address of READ source data + addr src_paddr = `PA_DATA(proc_id, qp.ctx.remote_qpn) + db_id * this.wqe_num * wqe_data_count; + addr src_vaddr = `VA(src_paddr); + // start physical address of READ buffer + addr dst_paddr = `PA_DATA(proc_id, qp.ctx.local_qpn) + `DATA_RECV_BUFF_GAP + db_id * this.wqe_num * wqe_data_count; + addr dst_vaddr = `VA(dst_paddr); + + if (qp.ctx.flags[23:16] == `HGHCA_QP_ST_UD || qp.ctx.flags[23:16] == `HGHCA_QP_ST_UC) begin + break; + end + + // create data mpt and buffer mpt + remote_mpt = create_mr( + remote_host_id, + proc_id, + wqe_data_count, + src_vaddr + wqe_id * wqe_data_count, + remote_qp.ctx.pd, + `PAGE_SIZE, + FALSE, + 8'b1000_0111 + ); + sq_remote_mpt_que.push_back(remote_mpt); + sq_remote_offset_que.push_back(src_vaddr + wqe_id * wqe_data_count - remote_mpt.start); + + for (int sg_id = 0; sg_id < sg_num; sg_id++) begin + local_mpt = create_mr( + host_id, + proc_id, + sg_entry_data_count, + dst_vaddr + wqe_id * wqe_data_count + sg_id * sg_entry_data_count, + qp.ctx.pd, + `PAGE_SIZE, + FALSE, + 8'b1000_0111 + ); + sq_local_mpt_que.push_back(local_mpt); + sq_local_offset_que.push_back(dst_vaddr + wqe_id * wqe_data_count + sg_id * sg_entry_data_count - local_mpt.start); + end + sq_op_que.push_back(READ); + end + else begin + `uvm_fatal("WQE_ID_ERR", $sformatf("wqe_id error! wqe_id: %d", wqe_id)); + end + end + `uvm_info("INIT_INFO", $sformatf("data memory region created! QP number: %h.", qp.ctx.local_qpn), UVM_LOW); + // put SQ WQEs + qp.put_wqe( + sq_op_que, + sq_local_mpt_que, + sq_remote_mpt_que, + sq_local_offset_que, + sq_remote_offset_que, + q_list, + check_list, + sg_num, + sg_entry_data_count + ); + // put RQ WQEs + remote_qp.put_wqe( + rq_op_que, + rq_recv_mpt_que, + rq_send_mpt_que, + rq_recv_offset_que, + rq_send_offset_que, + q_list, + check_list, + sg_num, + sg_entry_data_count + ); + endfunction: create_and_write_wqes + + //------------------------------------------------------------------------------ + // task name : global_stop + // function : receive global stop signal from scoreboard and inform virtual + // sequence of global stop + // invoked : by test_direct + //------------------------------------------------------------------------------ + task global_stop(int db_id, int db_num); + int temp_num; + hca_pcie_item glb_stop_item; + `uvm_info("GLB_STOP_INFO", $sformatf("before getting global stop signal"), UVM_LOW); + glb_stop_mbx.get(temp_num); + if (db_id + 1 != db_num) begin + `uvm_info("GLB_STOP_INFO", $sformatf("db_id: %h, db_num: %h", db_id, db_num), UVM_LOW) + return; + end + else begin + `uvm_info("GLB_STOP_INFO", $sformatf("global stop signal get in test! db_id: %h, db_num: %h", db_id, db_num), UVM_LOW); + glb_stop_item = hca_pcie_item::type_id::create("glb_stop_item", this); + glb_stop_item.item_type = GLOBAL_STOP; + foreach(vseq.cfg_mbx[i]) begin + hca_pcie_item glb_stop_item_cfg; + glb_stop_item_cfg = hca_pcie_item::type_id::create($sformatf("glb_stop_item_cfg[%0d]", i), this); + glb_stop_item_cfg.copy(glb_stop_item); + vseq.cfg_mbx[i].put(glb_stop_item_cfg); + `uvm_info("GLB_STOP_INFO", $sformatf("glb_stop_item sent to vseq.cfg_mbx[%0d]", i), UVM_LOW); + end + foreach(vseq.comm_mbx[i]) begin + vseq.comm_mbx[i].put(glb_stop_item); + `uvm_info("GLB_STOP_INFO", $sformatf("glb_stop_item sent to vseq.comm_mbx[%0d]", i), UVM_LOW); + end + end + endtask: global_stop + + //------------------------------------------------------------------------------ + // task name : connect_qp + // function : 1) modify QP context in q_list.qp_list + // 2) send modify_qp command to dut + // invoked : by single_process_cfg + //------------------------------------------------------------------------------ + function bit connect_qp(int host_id_a, hca_queue_pair qp_a, int host_id_b, hca_queue_pair qp_b); + // local.next_send_psn == local.unacked_psn == remote.next_recv_psn + qp_a.ctx.remote_qpn = qp_b.ctx.local_qpn; + qp_b.ctx.remote_qpn = qp_a.ctx.local_qpn; + qp_a.ctx.rnr_nextrecvpsn = qp_b.ctx.next_send_psn; + qp_b.ctx.rnr_nextrecvpsn = qp_a.ctx.next_send_psn; + + qp_a.connect(qp_b); + + cfg_agt.modify_qp(host_id_a, qp_a.ctx); + cfg_agt.modify_qp(host_id_b, qp_b.ctx); + `uvm_info("CONNECT_QP_INFO", + $sformatf("QP connected! host_a: %h, qp_a: %h, host_b: %h, qp_b: %h", + host_id_a, qp_a.ctx.local_qpn, host_id_b, qp_b.ctx.local_qpn), + UVM_LOW + ); + endfunction: connect_qp + + //------------------------------------------------------------------------------ + // task name : send_db + // function : create a doorbell and send it to virtual sequence + // invoked : by single_process + //------------------------------------------------------------------------------ + task send_db(int host_id, bit [10:0] proc_id, int db_id, hca_queue_pair qp, bit [4:0] op_code); + hca_pcie_item doorbell_item; + bit [15:0] first_wqe_byte_offset; + doorbell db; + doorbell_item = hca_pcie_item::type_id::create("doorbell_item", this); + first_wqe_byte_offset = qp.sq_last_header % qp.sq_byte_size; + // What is this? + if (first_wqe_byte_offset[3:0] != 0) begin + `uvm_fatal("QP_ERR", $sformatf("first_wqe_byte_offset is not zero! host_id: %h, qpn: %h, sq_tail: %h", + host_id, qp.ctx.local_qpn, qp.sq_tail)); + end + db.sq_head = first_wqe_byte_offset[15:4]; + // first_wqe_byte_offset = db_id * this.wqe_num * `SQ_WQE_BYTE_LEN; + // db.sq_head = db_id * this.wqe_num * `SQ_WQE_BYTE_LEN; + db.f0 = 0; + db.opcode = op_code; + db.qp_num = qp.ctx.local_qpn; + // db.host_id = host_id; + + // set size0 + if (qp.ctx.flags[23:16] == `HGHCA_QP_ST_UD) begin + if (op_code == `VERBS_SEND) begin + db.size0 = sg_num + 4; + end + else begin + `uvm_fatal("OP TYPE ERROR", $sformatf("op type error! qpn: %h, host id: %h, op code: %h", qp.ctx.local_qpn, host_id, op_code)); + end + end + else begin + if (op_code == `VERBS_SEND) begin + db.size0 = sg_num + 1; + end + else begin + db.size0 = sg_num + 2; + end + end + db.proc_id = proc_id; + doorbell_item.item_type = DOORBELL; + doorbell_item.db = db; + if (vseq.comm_mbx[host_id].try_put(doorbell_item) == 0) begin + `uvm_fatal("MAILBOX_PUT_ERROR", "put comm item fail!") + end + `uvm_info("NOTICE", $sformatf("send doorbell finished! host id: %h, QP number: %h", host_id, db.qp_num), UVM_LOW); + endtask: send_db + + function hca_queue_pair create_qp( + bit [10:0] proc_id, + int host_id, + bit [31:0] pd, + e_service_type serv_typ, + hca_comp_queue send_cq, + hca_comp_queue recv_cq + ); + //bit [31:0] qp_num = 0; + bit [31:0] qp_num = 0; + qp_context qpc; + mpt sq_mpt; + mpt rq_mpt; + addr qp_start_vaddr; + int qp_vaddr_offset; + addr temp_addr; + hca_queue_pair qp; + + for (int i = 0; i < q_list.qp_list[host_id].size(); i++) begin + if (q_list.qp_list[host_id][i].ctx.local_qpn == qp_num) begin + qp_num++; + end + end + + qp_vaddr_offset = qp_num * `MAX_DESC_SZ * `MAX_QP_SZ; + qp_start_vaddr = `VA_QP(qp_num); + // create qp mr + `uvm_info("NOTICE", $sformatf("before create mr, qp_num: %h, start_vaddr: %h", qp_num, qp_start_vaddr), UVM_LOW); + sq_mpt = create_mr(host_id, proc_id, `VRF_SQ_BYTE_SIZE, qp_start_vaddr, pd, `PAGE_SIZE, TRUE, 8'b1000_0011); + rq_mpt = create_mr(host_id, proc_id, `VRF_RQ_BYTE_SIZE, qp_start_vaddr + `SQ_RQ_GAP, pd, `PAGE_SIZE, TRUE, 8'b1000_0011); + + if (icm_vaddr.qpc_cap_left[host_id] < `QPC_ENTRY_SZ) begin + cfg_agt.map_icm(host_id, `ICM_QPC_TYP, 1); + end + icm_vaddr.qpc_cap_left[host_id] -= `QPC_ENTRY_SZ; + if (icm_vaddr.qpc_cap_left[host_id] < 0) begin + `uvm_fatal("ICM_ERR", $sformatf("ICM CAPACITY OUT!")); + end + // set QP context + qpc.opt_param_mask = $urandom(); + qpc.flags[31:28] = 4'b0011; + qpc.flags[27:24] = 4'b0000; + qpc.flags[15:0] = 16'b0; + case (serv_typ) + RC: begin + qpc.flags[23:16] = 8'h00; + end + UC: begin + qpc.flags[23:16] = 8'h01; + end + RD: begin + qpc.flags[23:16] = 8'h02; + end + UD: begin + qpc.flags[23:16] = 8'h03; + end + default: begin + `uvm_fatal("CREATE_QP_ERR", "invalid service type!"); + end + endcase + qpc.mtu_msgmax = {`QPC_MTU_4096, 5'b11111}; + qpc.rq_entry_sz_log = math.log_func(`RQ_WQE_BYTE_LEN); + qpc.sq_entry_sz_log = math.log_func(`SQ_WQE_BYTE_LEN); + qpc.local_qpn = qp_num; + qpc.remote_qpn = qp_num; + qpc.port_pkey = 0; + qpc.rnr_retry = 0; + qpc.smac = {48'h123456789abc}; + qpc.dmac = {48'hcba987654321}; + qpc.sip = {32'ha0b1c2d3}; + qpc.dip = {32'hd4c5b6a7}; + qpc.pd = pd; + qpc.next_send_psn = $urandom(); + qpc.cqn_snd = send_cq.ctx.cqn; + qpc.cqn_rcv = recv_cq.ctx.cqn; + qpc.snd_wqe_base_l = sq_mpt.key; + qpc.snd_wqe_len = `VRF_SQ_BYTE_SIZE; + qpc.last_acked_psn = qpc.next_send_psn; + qpc.rnr_nextrecvpsn = qpc.next_send_psn; + qpc.rcv_wqe_base_l = rq_mpt.key; + qpc.rcv_wqe_len = `VRF_RQ_BYTE_SIZE; + cfg_agt.modify_qp(host_id, qpc); + + qp = hca_queue_pair::type_id::create($sformatf("qp%0d", qpc.local_qpn)); + qp.ctx = qpc; + qp.host_id = host_id; + qp.proc_id = proc_id; + qp.mem = env.mem[host_id]; + qp.sq_byte_size = `VRF_SQ_BYTE_SIZE; + qp.rq_byte_size = `VRF_RQ_BYTE_SIZE; + // qp.sq_header = 0; + // qp.sq_tail = 0; + q_list.qp_list[host_id].push_back(qp); + `uvm_info("CREATE_QP_INFO", $sformatf("create QP finished! host_id: %h, QP num: %0d, PD: %h, SQ Key: %h, RQ Key: %h", + host_id, qp.ctx.local_qpn, qpc.pd, sq_mpt.key, rq_mpt.key), UVM_LOW); + return qp; + endfunction: create_qp + + function hca_comp_queue create_cq(bit [10:0] proc_id, int host_id, bit [31:0] pd); + cq_context cqc; + mpt cq_mpt; + addr cq_start_vaddr; + bit [31:0] cqn = 0; + hca_comp_queue cq; + + // allocate cq number + for (int i = 0; i < q_list.cq_list[host_id].size(); i++) begin + if (q_list.cq_list[host_id][i].ctx.cqn == cqn) begin + cqn++; + end + end + + cq_start_vaddr = `VA_CQ(cqn); + + cq_mpt = create_mr(host_id, proc_id, 4096, cq_start_vaddr, pd, `PAGE_SIZE, TRUE, 8'b1000_0011); + + cqc.flags = 32'h0004_0000; + cqc.start = cq_start_vaddr; + cqc.logsize = 8'h06; + cqc.usrpage = 0; + cqc.comp_eqn = 0; + cqc.pd = cq_mpt.pd; + cqc.lkey = cq_mpt.key; + cqc.cqn = cqn; + + if (icm_vaddr.cqc_cap_left[host_id] < `CQC_ENTRY_SZ) begin + cfg_agt.map_icm(host_id, `ICM_CQC_TYP, 1); + end + + cq = hca_comp_queue::type_id::create($sformatf("cq%0d", cqn)); + cq.ctx = cqc; + cq.header = 0; + cq.tail = 0; + q_list.cq_list[host_id].push_back(cq); + + cfg_agt.sw2hw_cq(host_id, cqc); + return cq; + endfunction: create_cq + + function mpt create_mr( + int host_id, + input bit [10:0] proc_id, + input bit [63:0] size, + input addr start_vaddr, + input bit [31:0] pd, + input bit [31:0] page_size, + input bool is_zbva, + // 0, ON_DEMAND, ZERO_BASED, MW_BIND, REMOTE_ATOMIC, REMOTE_READ, REMOTE_WRITE, LOCAL_WRITE + input bit [7:0] auth_flag + ); + mpt new_mpt; + int mtt_num; + int mtt_page_num; + addr temp_addr; + addr mtt_icm_addr; + addr mtt_icm_idx; + addr mpt_icm_addr; + addr mr_size; + mtt temp_mtt_item; + addr mtt_seg; + + for (int i = 0; i < 32; i++) begin + if (page_size[i] == 1) begin + if (i < 12) begin + `uvm_fatal("ILLEGAL_PAGESIZE", "page_size illegal in create_mr()!"); + end + else begin + new_mpt.page_size = i - 12; + break; + end + end + end + + // set amount of mtt entries and size of memory region + // if (size % page_size == 0) begin + // mtt_num = size / page_size; + // end + // else begin + // mtt_num = size / page_size + 1; + // end + if ((size + start_vaddr[11:0]) % page_size == 0) begin + mtt_num = (size + start_vaddr[11:0]) / page_size; + mr_size = mtt_num * `PAGE_SIZE; + end + else begin + mtt_num = (size + start_vaddr[11:0]) / page_size + 1; + mr_size = mtt_num * `PAGE_SIZE; + end + + // set amount of pages for mtt in ICM space + if (mtt_num % 512 == 0) begin + mtt_page_num = mtt_num / 512; + end + else begin + mtt_page_num = mtt_num / 512 + 1; + end + + // allocate space for MTT in ICM space + if (icm_vaddr.mtt_cap_left[host_id] < mtt_num * 8) begin + mtt_icm_addr = cfg_agt.map_icm(host_id, `ICM_MTT_TYP, mtt_page_num); + end + + // allocate space for MPT in ICM space + if (icm_vaddr.mpt_cap_left[host_id] < `MPT_ITEM_SIZE) begin + mpt_icm_addr = cfg_agt.map_icm(host_id, `ICM_MPT_TYP, 1); + end + + // write MTT entries of new MR + // number of MTT entries should be no larger than 255, or otherwise configuration would fail + for (int mtt_num_sent = 0; mtt_num_sent < mtt_num; mtt_num_sent = mtt_num_sent + 255) begin + // mtt seg is the header index of the whole MR mtt entries + if (mtt_num_sent == 0) begin + if (mtt_num <= 255) begin + mtt_seg = cfg_agt.write_mtt(host_id, {5'b0, proc_id, start_vaddr[47:12], 12'b0}, mtt_num); + end + else begin + mtt_seg = cfg_agt.write_mtt(host_id, {5'b0, proc_id, start_vaddr[47:12], 12'b0}, 255); + end + end + else if (mtt_num_sent + 255 <= mtt_num) begin + cfg_agt.write_mtt(host_id, {5'b0, proc_id, start_vaddr[47:12], 12'b0} + mtt_num_sent * 4096, 255); + end + else begin + cfg_agt.write_mtt(host_id, {5'b0, proc_id, start_vaddr[47:12], 12'b0} + mtt_num_sent * 4096, mtt_num - mtt_num_sent); + end + end + + ///////////////////////////////////////////////////////////////////////// + // SW_OWNS MIO BIND_ENABLE PHYSICAL REGION LOCAL_WRITE REMOTE_WRITE REMOTE_READ REMOTE_ATOMIC MW_BIND ZERO_BASED ON_DEMAND + new_mpt.flags = {16'hf002, auth_flag}; // 32'b1111_0000_0000_0010_0000_0001_1000_0011 + new_mpt.length = mr_size; + if (is_zbva == TRUE) begin + new_mpt.start = 0; + end + else begin + new_mpt.start = {start_vaddr[63:12], 12'b0}; + end + new_mpt.pd = pd; + new_mpt.mtt_seg = mtt_seg; + new_mpt.key = mem_info.mem_region[host_id].size(); + + cfg_agt.sw2hw_mpt(host_id, new_mpt); + `uvm_info("CREATE_MR_NOTICE", + $sformatf("create mr success! host_id: %h, key: %h, input start vaddr: %h, MR start vaddr: %h, input size: %h, MR size: %h, pd: %h, page size: %h", + host_id, new_mpt.key, start_vaddr, new_mpt.start, size, mr_size, pd, page_size), UVM_LOW); + return new_mpt; + endfunction: create_mr + + function write_test_data(int host_id, addr phys_addr, bit [31:0] data_cnt); + bit [256/`BYTE_BIT_WIDTH-1:0][`BYTE_BIT_WIDTH-1:0] write_data; + int beat_num; + write_data = 0; + if (data_cnt[4:0] == 0) begin + beat_num = data_cnt[31:5]; + end + else begin + beat_num = data_cnt[31:5] + 1; + end + for (int i = 0; i < beat_num; i++) begin + for (int j = 0; j < 32; j++) begin + // write_data[j] = (i * 32 + j) % 256; + write_data[j] = $urandom(); + end + data_fifo.push(write_data); + `uvm_info("DATA_NOTICE", $sformatf("write data: %h, phys_addr: %h, data count: %h, beat_id: %h, host id: %h", + write_data, phys_addr, data_cnt, i, host_id), UVM_LOW + ); + write_data = 0; + end + env.mem[host_id].write_block(phys_addr, data_fifo, data_cnt); + `uvm_info("TEST_NOTICE", $sformatf("send data start physical addr: %h, data count: %0d, host id: %h", phys_addr, data_cnt, host_id), UVM_LOW); + data_fifo.clean(); + endfunction: write_test_data +endclass: test_direct_param +`endif diff --git a/ETH-PLUS_Jingzhao/JingZhao2/verification/src/vrf_HTN/vrf_hdl/hca_dut.v b/ETH-PLUS_Jingzhao/JingZhao2/verification/src/vrf_HTN/vrf_hdl/hca_dut.v new file mode 100644 index 0000000000000000000000000000000000000000..1f265ac5d9eeab6c59ab42b37332700aac7444aa --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/verification/src/vrf_HTN/vrf_hdl/hca_dut.v @@ -0,0 +1,280 @@ +//CREATE INFORMATION +//---------------------------------------------------------------------------- +// +// (C) COPYRIGHT 2021 BY ICT-HPC CORPORATION ALL RIGHTS RESERVED +// DATE : 2021-01-18 +// AUTHOR : mazhenlong@ncic.ac.cn +// FILENAME : hca_dut.v +// FUNCTION : This file supplies the top module of HCA. +// +//---------------------------------------------------------------------------- + +//CHANGE HISTORY +//---------------------------------------------------------------------------- +// +// AUTHOR DATE VERSION REASON +// mazhenlong 2021-01-18 v1.0 create +// mazhenlong 2021-05-12 v1.1 add self-loop-back +// mazhenlong 2022-01-27 v2 add multi-host +// +//---------------------------------------------------------------------------- + +`ifndef __HCA_DUT__ +`define __HCA_DUT__ +//------------------------------------------------------------------------------ +// +// MODULE: hca_dut +// +//------------------------------------------------------------------------------ +`include "protocol_engine_def.vh" + +module hca_dut #( + parameter C_DATA_WIDTH = `DATA_WIDTH, // RX/TX interface data width + parameter KEEP_WIDTH = C_DATA_WIDTH / 32, + parameter DMA_HEAD_WIDTH = `DMA_HEAD_WIDTH, + parameter NIC_DATA_WIDTH = 256, + parameter NIC_KEEP_WIDTH = 32, + parameter LINK_LAYER_USER_WIDTH = 7 +)( + //---------------------------------------------------------- + // Control Interface + //---------------------------------------------------------- + input a_sys_clk, + input a_pcie_clk, + input a_rdma_clk, + input a_user_reset, + input a_user_lnk_up, + output a_cmd_rst, + + //---------------------------------------------------------- + // Host A RDMA Interface + //---------------------------------------------------------- + input [2:0] a_cfg_max_payload, + input [2:0] a_cfg_max_read_req, + + output a_s_axis_rq_tlast, + output [C_DATA_WIDTH-1:0] a_s_axis_rq_tdata, + output [59:0] a_s_axis_rq_tuser, + output [KEEP_WIDTH-1:0] a_s_axis_rq_tkeep, + input a_s_axis_rq_tready, + output a_s_axis_rq_tvalid, + + input [C_DATA_WIDTH-1:0] a_m_axis_rc_tdata, + input [74:0] a_m_axis_rc_tuser, + input a_m_axis_rc_tlast, + input [KEEP_WIDTH-1:0] a_m_axis_rc_tkeep, + input a_m_axis_rc_tvalid, + output a_m_axis_rc_tready, + + input [C_DATA_WIDTH-1:0] a_m_axis_cq_tdata, + input [84:0] a_m_axis_cq_tuser, + input a_m_axis_cq_tlast, + input [KEEP_WIDTH-1:0] a_m_axis_cq_tkeep, + input a_m_axis_cq_tvalid, + output a_m_axis_cq_tready, + + output [C_DATA_WIDTH-1:0] a_s_axis_cc_tdata, + output [32:0] a_s_axis_cc_tuser, + output a_s_axis_cc_tlast, + output [KEEP_WIDTH-1:0] a_s_axis_cc_tkeep, + output a_s_axis_cc_tvalid, + input a_s_axis_cc_tready, + + //---------------------------------------------------------- + // Host B RDMA Interface + //---------------------------------------------------------- + input b_sys_clk, + input b_pcie_clk, + input b_rdma_clk, + input b_user_reset, + input b_user_lnk_up, + output b_cmd_rst, + + input [2:0] b_cfg_max_payload, + input [2:0] b_cfg_max_read_req, + + output b_s_axis_rq_tlast, + output [C_DATA_WIDTH-1:0] b_s_axis_rq_tdata, + output [59:0] b_s_axis_rq_tuser, + output [KEEP_WIDTH-1:0] b_s_axis_rq_tkeep, + input b_s_axis_rq_tready, + output b_s_axis_rq_tvalid, + + input [C_DATA_WIDTH-1:0] b_m_axis_rc_tdata, + input [74:0] b_m_axis_rc_tuser, + input b_m_axis_rc_tlast, + input [KEEP_WIDTH-1:0] b_m_axis_rc_tkeep, + input b_m_axis_rc_tvalid, + output b_m_axis_rc_tready, + + input [C_DATA_WIDTH-1:0] b_m_axis_cq_tdata, + input [84:0] b_m_axis_cq_tuser, + input b_m_axis_cq_tlast, + input [KEEP_WIDTH-1:0] b_m_axis_cq_tkeep, + input b_m_axis_cq_tvalid, + output b_m_axis_cq_tready, + + output [C_DATA_WIDTH-1:0] b_s_axis_cc_tdata, + output [32:0] b_s_axis_cc_tuser, + output b_s_axis_cc_tlast, + output [KEEP_WIDTH-1:0] b_s_axis_cc_tkeep, + output b_s_axis_cc_tvalid, + input b_s_axis_cc_tready +); + + wire w_hpc_a2b_valid; + wire w_hpc_a2b_last ; + wire [NIC_DATA_WIDTH - 1 : 0] wv_hpc_a2b_data; + wire [NIC_KEEP_WIDTH - 1 : 0] wv_hpc_a2b_keep; + wire w_hpc_a2b_ready; + wire w_hpc_a2b_start; + wire [LINK_LAYER_USER_WIDTH - 1 : 0] wv_hpc_a2b_user; + + wire w_hpc_b2a_valid; + wire w_hpc_b2a_last ; + wire [NIC_DATA_WIDTH - 1 : 0] wv_hpc_b2a_data; + wire [NIC_KEEP_WIDTH - 1 : 0] wv_hpc_b2a_keep; + wire w_hpc_b2a_ready; + wire w_hpc_b2a_start; + wire [LINK_LAYER_USER_WIDTH - 1 : 0] wv_hpc_b2a_user; + + wire w_eth_a2b_valid; + wire w_eth_a2b_last ; + wire [`MAC_DATA_WIDTH - 1 : 0] wv_eth_a2b_data; + wire [`MAC_KEEP_WIDTH - 1 : 0] wv_eth_a2b_keep; + wire w_eth_a2b_ready; + wire w_eth_a2b_start; + wire [0 : 0] wv_eth_a2b_user; + + wire w_eth_b2a_valid; + wire w_eth_b2a_last ; + wire [`MAC_DATA_WIDTH - 1 : 0] wv_eth_b2a_data; + wire [`MAC_KEEP_WIDTH - 1 : 0] wv_eth_b2a_keep; + wire w_eth_b2a_ready; + wire w_eth_b2a_start; + wire [0 : 0] wv_eth_b2a_user; + +HanGuHTN_Top NIC_a ( + .pcie_clk ( a_pcie_clk ), + .pcie_rst ( a_user_reset ), + + .user_clk ( a_rdma_clk ), + .user_rst ( a_user_reset ), + + .mac_tx_clk ( a_rdma_clk ), + .mac_tx_rst ( a_user_reset ), + + .mac_rx_clk ( a_rdma_clk ), + .mac_rx_rst ( a_user_reset ), + + .cfg_max_payload ( a_cfg_max_payload ), + .cfg_max_read_req ( a_cfg_max_read_req ), + + .s_axis_rq_tvalid ( a_s_axis_rq_tvalid ), + .s_axis_rq_tlast ( a_s_axis_rq_tlast ), + .s_axis_rq_tkeep ( a_s_axis_rq_tkeep ), + .s_axis_rq_tuser ( a_s_axis_rq_tuser ), + .s_axis_rq_tdata ( a_s_axis_rq_tdata ), + .s_axis_rq_tready ( a_s_axis_rq_tready ), + + .m_axis_rc_tvalid ( a_m_axis_rc_tvalid ), + .m_axis_rc_tlast ( a_m_axis_rc_tlast ), + .m_axis_rc_tkeep ( a_m_axis_rc_tkeep ), + .m_axis_rc_tuser ( a_m_axis_rc_tuser ), + .m_axis_rc_tdata ( a_m_axis_rc_tdata ), + .m_axis_rc_tready ( a_m_axis_rc_tready ), + + .m_axis_cq_tvalid ( a_m_axis_cq_tvalid ), + .m_axis_cq_tlast ( a_m_axis_cq_tlast ), + .m_axis_cq_tkeep ( a_m_axis_cq_tkeep ), + .m_axis_cq_tuser ( a_m_axis_cq_tuser ), + .m_axis_cq_tdata ( a_m_axis_cq_tdata ), + .m_axis_cq_tready ( a_m_axis_cq_tready ), + + .s_axis_cc_tvalid ( a_s_axis_cc_tvalid ), + .s_axis_cc_tlast ( a_s_axis_cc_tlast ), + .s_axis_cc_tkeep ( a_s_axis_cc_tkeep ), + .s_axis_cc_tuser ( a_s_axis_cc_tuser ), + .s_axis_cc_tdata ( a_s_axis_cc_tdata ), + .s_axis_cc_tready ( a_s_axis_cc_tready ), + + .mac_tx_valid ( w_eth_a2b_valid ), + .mac_tx_ready ( w_eth_a2b_ready ), + .mac_tx_start ( w_eth_a2b_start ), + .mac_tx_last ( w_eth_a2b_last ), + .mac_tx_keep ( wv_eth_a2b_keep ), + .mac_tx_user ( wv_eth_a2b_user ), + .mac_tx_data ( wv_eth_a2b_data ), + + .mac_rx_valid ( w_eth_b2a_valid ), + .mac_rx_ready ( w_eth_b2a_ready ), + .mac_rx_start ( w_eth_b2a_start ), + .mac_rx_last ( w_eth_b2a_last ), + .mac_rx_keep ( wv_eth_b2a_keep ), + .mac_rx_user ( wv_eth_b2a_user ), + .mac_rx_data ( wv_eth_b2a_data ) +); + +HanGuHTN_Top NIC_b ( + .pcie_clk ( a_pcie_clk ), + .pcie_rst ( a_user_reset ), + + .user_clk ( a_rdma_clk ), + .user_rst ( a_user_reset ), + + .mac_tx_clk ( a_rdma_clk ), + .mac_tx_rst ( a_user_reset ), + + .mac_rx_clk ( a_rdma_clk ), + .mac_rx_rst ( a_user_reset ), + + .cfg_max_payload ( b_cfg_max_payload ), + .cfg_max_read_req ( b_cfg_max_read_req ), + + .s_axis_rq_tvalid ( b_s_axis_rq_tvalid ), + .s_axis_rq_tlast ( b_s_axis_rq_tlast ), + .s_axis_rq_tkeep ( b_s_axis_rq_tkeep ), + .s_axis_rq_tuser ( b_s_axis_rq_tuser ), + .s_axis_rq_tdata ( b_s_axis_rq_tdata ), + .s_axis_rq_tready ( b_s_axis_rq_tready ), + + .m_axis_rc_tvalid ( b_m_axis_rc_tvalid ), + .m_axis_rc_tlast ( b_m_axis_rc_tlast ), + .m_axis_rc_tkeep ( b_m_axis_rc_tkeep ), + .m_axis_rc_tuser ( b_m_axis_rc_tuser ), + .m_axis_rc_tdata ( b_m_axis_rc_tdata ), + .m_axis_rc_tready ( b_m_axis_rc_tready ), + + .m_axis_cq_tvalid ( b_m_axis_cq_tvalid ), + .m_axis_cq_tlast ( b_m_axis_cq_tlast ), + .m_axis_cq_tkeep ( b_m_axis_cq_tkeep ), + .m_axis_cq_tuser ( b_m_axis_cq_tuser ), + .m_axis_cq_tdata ( b_m_axis_cq_tdata ), + .m_axis_cq_tready ( b_m_axis_cq_tready ), + + .s_axis_cc_tvalid ( b_s_axis_cc_tvalid ), + .s_axis_cc_tlast ( b_s_axis_cc_tlast ), + .s_axis_cc_tkeep ( b_s_axis_cc_tkeep ), + .s_axis_cc_tuser ( b_s_axis_cc_tuser ), + .s_axis_cc_tdata ( b_s_axis_cc_tdata ), + .s_axis_cc_tready ( b_s_axis_cc_tready ), + + .mac_tx_valid ( w_eth_b2a_valid ), + .mac_tx_ready ( w_eth_b2a_ready ), + .mac_tx_start ( w_eth_b2a_start ), + .mac_tx_last ( w_eth_b2a_last ), + .mac_tx_keep ( wv_eth_b2a_keep ), + .mac_tx_user ( wv_eth_b2a_user ), + .mac_tx_data ( wv_eth_b2a_data ), + + .mac_rx_valid ( w_eth_a2b_valid ), + .mac_rx_ready ( w_eth_a2b_ready ), + .mac_rx_start ( w_eth_a2b_start ), + .mac_rx_last ( w_eth_a2b_last ), + .mac_rx_keep ( wv_eth_a2b_keep ), + .mac_rx_user ( wv_eth_a2b_user ), + .mac_rx_data ( wv_eth_a2b_data ) +); + +endmodule: hca_dut +`endif diff --git a/ETH-PLUS_Jingzhao/JingZhao2/verification/src/vrf_HTN/vrf_hdl/hca_tb_top.v b/ETH-PLUS_Jingzhao/JingZhao2/verification/src/vrf_HTN/vrf_hdl/hca_tb_top.v new file mode 100644 index 0000000000000000000000000000000000000000..7d95bc12c4d7b4aa9b7e45d95ebe22787b87371f --- /dev/null +++ b/ETH-PLUS_Jingzhao/JingZhao2/verification/src/vrf_HTN/vrf_hdl/hca_tb_top.v @@ -0,0 +1,355 @@ +`timescale 1ns/100ps +//CREATE INFORMATION +//------------------------------------------------------------------------------------ +// +// (C) COPYRIGHT 2021 BY ICT-HPC CORPORATION ALL RIGHTS RESERVED +// DATE : 2021-01-26 +// AUTHOR : mazhenlong@ncic.ac.cn +// FILENAME : hca_tb_top.v +// FUNCTION : This file supplies the top module of testbench of HCA. +// +//------------------------------------------------------------------------------------ + +//CHANGE HISTORY +//------------------------------------------------------------------------------------ +// +// AUTHOR DATE VERSION REASON +// mazhenlong 2021-01-26 v1.0 create +// mazhenlong 2021-03-22 v1.1 add `RST_DELAY and `AFTER_RST_DELAY +// mazhenlong 2021-03-24 v1.2 change ports connected to dut to _dut +// mazhenlong 2022-01-27 v2 support multi host +// mazhenlong 2022-09-14 v3 expand line width from 256 to 1024 +// +//------------------------------------------------------------------------------------ + +`ifndef __HCA_TB_TOP__ +`define __HCA_TB_TOP__ + +//------------------------------------------------------------------------------------ +// +// MODULE: hca_tb_top +// +//------------------------------------------------------------------------------------ +module hca_tb_top #( + parameter C_DATA_WIDTH = `DATA_WIDTH, + parameter KEEP_WIDTH = C_DATA_WIDTH / 32, + parameter DMA_HEAD_WIDTH = 128, + parameter AXIS_TUSER_WIDTH = 128, + parameter PAGE_SIZE_LOG = 12 +); + import uvm_pkg::*; // this line can be deleted with everything doing well, no idea about this. + + hca_interface #( + .C_DATA_WIDTH (C_DATA_WIDTH), + .KEEP_WIDTH (`DATA_WIDTH / 32), // C_DATA_WIDTH /32 + .DMA_HEAD_WIDTH (DMA_HEAD_WIDTH), + .AXIS_TUSER_WIDTH(AXIS_TUSER_WIDTH), + .PAGE_SIZE_LOG (PAGE_SIZE_LOG) + ) hca_if_a(); + + hca_interface #( + .C_DATA_WIDTH (C_DATA_WIDTH), + .KEEP_WIDTH (`DATA_WIDTH / 32), // C_DATA_WIDTH /32 + .DMA_HEAD_WIDTH (DMA_HEAD_WIDTH), + .AXIS_TUSER_WIDTH(AXIS_TUSER_WIDTH), + .PAGE_SIZE_LOG (PAGE_SIZE_LOG) + ) hca_if_b(); + + hca_dut #( + .C_DATA_WIDTH(C_DATA_WIDTH), // RX/TX interface data width + .KEEP_WIDTH (`DATA_WIDTH / 32), + .DMA_HEAD_WIDTH(DMA_HEAD_WIDTH) + ) dut ( + .a_sys_clk (hca_if_a.sys_clk ), + .a_pcie_clk (hca_if_a.pcie_clk ), + .a_rdma_clk (hca_if_a.rdma_clk ), + .a_user_reset (hca_if_a.user_reset ), + .a_user_lnk_up (hca_if_a.user_lnk_up ), + .a_cmd_rst (hca_if_a.cmd_rst ), + + .a_cfg_max_payload (hca_if_a.cfg_max_payload ), + .a_cfg_max_read_req (hca_if_a.cfg_max_read_req ), + + .a_s_axis_rq_tlast (hca_if_a.s_axis_rq_tlast_dut ), + .a_s_axis_rq_tdata (hca_if_a.s_axis_rq_tdata_dut ), + .a_s_axis_rq_tuser (hca_if_a.s_axis_rq_tuser_dut ), + .a_s_axis_rq_tkeep (hca_if_a.s_axis_rq_tkeep_dut ), + .a_s_axis_rq_tready (hca_if_a.s_axis_rq_tready_dut ), + .a_s_axis_rq_tvalid (hca_if_a.s_axis_rq_tvalid_dut ), + + .a_m_axis_rc_tdata (hca_if_a.m_axis_rc_tdata_dut ), + .a_m_axis_rc_tuser (hca_if_a.m_axis_rc_tuser_dut ), + .a_m_axis_rc_tlast (hca_if_a.m_axis_rc_tlast_dut ), + .a_m_axis_rc_tkeep (hca_if_a.m_axis_rc_tkeep_dut ), + .a_m_axis_rc_tvalid (hca_if_a.m_axis_rc_tvalid_dut ), + .a_m_axis_rc_tready (hca_if_a.m_axis_rc_tready_dut ), + + .a_m_axis_cq_tdata (hca_if_a.m_axis_cq_tdata_dut ), + .a_m_axis_cq_tuser (hca_if_a.m_axis_cq_tuser_dut ), + .a_m_axis_cq_tlast (hca_if_a.m_axis_cq_tlast_dut ), + .a_m_axis_cq_tkeep (hca_if_a.m_axis_cq_tkeep_dut ), + .a_m_axis_cq_tvalid (hca_if_a.m_axis_cq_tvalid_dut ), + .a_m_axis_cq_tready (hca_if_a.m_axis_cq_tready_dut ), + + .a_s_axis_cc_tdata (hca_if_a.s_axis_cc_tdata_dut ), + .a_s_axis_cc_tuser (hca_if_a.s_axis_cc_tuser_dut ), + .a_s_axis_cc_tlast (hca_if_a.s_axis_cc_tlast_dut ), + .a_s_axis_cc_tkeep (hca_if_a.s_axis_cc_tkeep_dut ), + .a_s_axis_cc_tvalid (hca_if_a.s_axis_cc_tvalid_dut ), + .a_s_axis_cc_tready (hca_if_a.s_axis_cc_tready_dut ), + + .b_sys_clk (hca_if_b.sys_clk ), + .b_pcie_clk (hca_if_b.pcie_clk ), + .b_rdma_clk (hca_if_b.rdma_clk ), + .b_user_reset (hca_if_b.user_reset ), + .b_user_lnk_up (hca_if_b.user_lnk_up ), + .b_cmd_rst (hca_if_b.cmd_rst ), + + .b_cfg_max_payload (hca_if_b.cfg_max_payload ), + .b_cfg_max_read_req (hca_if_b.cfg_max_read_req ), + + .b_s_axis_rq_tlast (hca_if_b.s_axis_rq_tlast_dut ), + .b_s_axis_rq_tdata (hca_if_b.s_axis_rq_tdata_dut ), + .b_s_axis_rq_tuser (hca_if_b.s_axis_rq_tuser_dut ), + .b_s_axis_rq_tkeep (hca_if_b.s_axis_rq_tkeep_dut ), + .b_s_axis_rq_tready (hca_if_b.s_axis_rq_tready_dut ), + .b_s_axis_rq_tvalid (hca_if_b.s_axis_rq_tvalid_dut ), + + .b_m_axis_rc_tdata (hca_if_b.m_axis_rc_tdata_dut ), + .b_m_axis_rc_tuser (hca_if_b.m_axis_rc_tuser_dut ), + .b_m_axis_rc_tlast (hca_if_b.m_axis_rc_tlast_dut ), + .b_m_axis_rc_tkeep (hca_if_b.m_axis_rc_tkeep_dut ), + .b_m_axis_rc_tvalid (hca_if_b.m_axis_rc_tvalid_dut ), + .b_m_axis_rc_tready (hca_if_b.m_axis_rc_tready_dut ), + + .b_m_axis_cq_tdata (hca_if_b.m_axis_cq_tdata_dut ), + .b_m_axis_cq_tuser (hca_if_b.m_axis_cq_tuser_dut ), + .b_m_axis_cq_tlast (hca_if_b.m_axis_cq_tlast_dut ), + .b_m_axis_cq_tkeep (hca_if_b.m_axis_cq_tkeep_dut ), + .b_m_axis_cq_tvalid (hca_if_b.m_axis_cq_tvalid_dut ), + .b_m_axis_cq_tready (hca_if_b.m_axis_cq_tready_dut ), + + .b_s_axis_cc_tdata (hca_if_b.s_axis_cc_tdata_dut ), + .b_s_axis_cc_tuser (hca_if_b.s_axis_cc_tuser_dut ), + .b_s_axis_cc_tlast (hca_if_b.s_axis_cc_tlast_dut ), + .b_s_axis_cc_tkeep (hca_if_b.s_axis_cc_tkeep_dut ), + .b_s_axis_cc_tvalid (hca_if_b.s_axis_cc_tvalid_dut ), + .b_s_axis_cc_tready (hca_if_b.s_axis_cc_tready_dut ) + ); + + function string get_time(); + string current_time; + int fp; + $system("date +%Y-%m-%d' '%H:%M:%S > temp_time"); + fp = $fopen("temp_time", "r"); + $fgets(current_time, fp); + $fclose(fp); + $system("rm temp_time"); + return current_time; + endfunction: get_time + + class report_catcher extends uvm_report_catcher; + string begin_time; + string end_time; + int fp; + string case_id; + int a; + string filename; + virtual function action_e catch(); + if (get_severity() == UVM_FATAL) begin + if ($value$plusargs("CASEID=%s", case_id)); + filename = $sformatf("end_time%s", case_id); + $system({"date +%Y-%m-%d' '%H:%M:%S > ", filename}); + fp = $fopen(filename, "r"); + $fgets(end_time, fp); + $fclose(fp); + $system($sformatf("rm %s", filename)); + `uvm_info("TIME_INFO", $sformatf("begin time: %s", begin_time), UVM_LOW); + `uvm_info("TIME_INFO", $sformatf("end time: %s", end_time), UVM_LOW); + $system($sformatf("%s >> fatal_case", case_id)); + end + return THROW; + endfunction: catch + endclass: report_catcher + + initial begin + report_catcher catcher; + string begin_time; + string end_time; + int fp; + + $system("date +%Y-%m-%d' '%H:%M:%S > begin_time"); + fp = $fopen("begin_time", "r"); + $fgets(begin_time, fp); + $fclose(fp); + $system("rm begin_time"); + catcher = new(); + + catcher.begin_time = begin_time; + + // if UVM_FATAL is produced, get system time in catcher + uvm_report_cb::add(null, catcher); + run_test(); + + // if verification ends successfully, get system time here + $system("date +%Y-%m-%d' '%H:%M:%S > end_time"); + fp = $fopen("end", "r"); + $fgets(end_time, fp); + $fclose(fp); + $system("rm end_time"); + `uvm_info("TIME_INFO", $sformatf("begin time: %s", begin_time), UVM_LOW); + `uvm_info("TIME_INFO", $sformatf("end time: %s", end_time), UVM_LOW); + end + + initial begin + uvm_config_db#(virtual hca_interface)::set(uvm_root::get(), "*.env.sub_env[0]*", "virtual_if", hca_if_a); + uvm_config_db#(virtual hca_interface)::set(uvm_root::get(), "*.env.sub_env[1]*", "virtual_if", hca_if_b); + end + + initial begin + hca_if_a.user_reset <= 1'b1; + hca_if_a.user_lnk_up <= 1'b0; + hca_if_a.veri_en <= 1'b0; + hca_if_a.global_stop <= 1'b0; + # `RST_DELAY; + hca_if_a.user_reset <= 1'b0; + hca_if_a.user_lnk_up <= 1'b1; + `uvm_info("NOTICE", "reset finished...", UVM_LOW) + # `AFTER_RST_DELAY; + `uvm_info("NOTICE", "verification enabled...", UVM_LOW) + hca_if_a.veri_en <= 1'b1; + hca_if_a.clock_count <= 0; + end + + initial begin + hca_if_b.user_reset <= 1'b1; + hca_if_b.user_lnk_up <= 1'b0; + hca_if_b.veri_en <= 1'b0; + hca_if_b.global_stop <= 1'b0; + # `RST_DELAY; + hca_if_b.user_reset <= 1'b0; + hca_if_b.user_lnk_up <= 1'b1; + `uvm_info("NOTICE", "reset finished...", UVM_LOW); + # `AFTER_RST_DELAY; + `uvm_info("NOTICE", "verification enabled...", UVM_LOW); + hca_if_b.veri_en <= 1'b1; + hca_if_b.clock_count <= 0; + end + + initial begin + hca_if_a.m_axis_cq_tdata <= 1'b0; + hca_if_a.m_axis_cq_tuser <= 1'b0; + hca_if_a.m_axis_cq_tlast <= 1'b0; + hca_if_a.m_axis_cq_tkeep <= 1'b0; + hca_if_a.m_axis_cq_tvalid <= 1'b0; + + hca_if_a.s_axis_cc_tready <= 1'b0; + + hca_if_a.m_axis_rc_tdata <= 1'b0; + hca_if_a.m_axis_rc_tuser <= 1'b0; + hca_if_a.m_axis_rc_tlast <= 1'b0; + hca_if_a.m_axis_rc_tkeep <= 1'b0; + hca_if_a.m_axis_rc_tvalid <= 1'b0; + + hca_if_a.s_axis_rq_tready <= 1'b0; + end + + initial begin + hca_if_b.m_axis_cq_tdata <= 1'b0; + hca_if_b.m_axis_cq_tuser <= 1'b0; + hca_if_b.m_axis_cq_tlast <= 1'b0; + hca_if_b.m_axis_cq_tkeep <= 1'b0; + hca_if_b.m_axis_cq_tvalid <= 1'b0; + + hca_if_b.s_axis_cc_tready <= 1'b0; + + hca_if_b.m_axis_rc_tdata <= 1'b0; + hca_if_b.m_axis_rc_tuser <= 1'b0; + hca_if_b.m_axis_rc_tlast <= 1'b0; + hca_if_b.m_axis_rc_tkeep <= 1'b0; + hca_if_b.m_axis_rc_tvalid <= 1'b0; + + hca_if_b.s_axis_rq_tready <= 1'b0; + end + + initial begin + `ifndef SIMULATION + `uvm_fatal("NO_DEF", "SIMULATION not defined!"); + `else + `uvm_info("DEF_INFO", "SIMULATION defined!", UVM_LOW); + `endif + // `ifndef FPGA_V7_VALIDATE + // `uvm_fatal("NO_DEF", "FPGA_V7_VALIDATE not defined!"); + // `else + // `uvm_info("DEF_INFO", "FPGA_V7_VALIDATE defined!", UVM_LOW); + // `endif + end + + + // clock driver + initial begin + hca_if_a.sys_clk <= 1'b1; + hca_if_a.pcie_clk <= 1'b1; + hca_if_a.rdma_clk <= 1'b1; + hca_if_b.sys_clk <= 1'b1; + hca_if_b.pcie_clk <= 1'b1; + hca_if_b.rdma_clk <= 1'b1; + end + always begin + #(`PCIE_CLK_PERIOD / 2); + hca_if_a.pcie_clk <= ~hca_if_a.pcie_clk; + hca_if_b.pcie_clk <= ~hca_if_b.pcie_clk; + end + always begin + #(`RDMA_CLK_PERIOD / 2); + hca_if_a.sys_clk <= ~hca_if_a.sys_clk; + hca_if_b.sys_clk <= ~hca_if_b.sys_clk; + end + always begin + #(`RDMA_CLK_PERIOD / 2); + hca_if_a.rdma_clk <= ~hca_if_a.rdma_clk; + hca_if_b.rdma_clk <= ~hca_if_b.rdma_clk; + end + +reg clk_td; +always @(posedge hca_if_a.sys_clk or negedge hca_if_a.sys_clk) begin + clk_td <= #1 hca_if_a.sys_clk; +end + +always @ (posedge hca_if_a.sys_clk) begin + hca_if_a.clock_count = hca_if_a.clock_count++; +end + +always @ (posedge hca_if_b.sys_clk) begin + hca_if_b.clock_count = hca_if_b.clock_count++; +end + + // initial begin + // $fsdbDumpvars(0, hca_tb_top); + // $fsdbDumpon(); + // $fsdbDumpMDA(); + // end + + initial begin + $vcdpluson(); + $vcdplusmemon(); + $vcdplusautoflushon(); + end + + initial begin + /* This signal indicates the max payload size & max read request size + * agreed in the communication + * 3'b000 -- 128 B + * 3'b001 -- 256 B + * 3'b010 -- 512 B + * 3'b011 -- 1024B + * 3'b100 -- 2048B + * 3'b101 -- 4096B + */ + hca_if_a.cfg_max_payload <= `MAX_PAYLOAD; + hca_if_a.cfg_max_read_req <= `MAX_READ_REQ; + hca_if_b.cfg_max_payload <= `MAX_PAYLOAD; + hca_if_b.cfg_max_read_req <= `MAX_READ_REQ; + end +endmodule: hca_tb_top +`endif diff --git a/ETH-PLUS_Jingzhao/README.md b/ETH-PLUS_Jingzhao/README.md new file mode 100644 index 0000000000000000000000000000000000000000..b906952a4abf18b2db3c6b6b0055339ce242570e --- /dev/null +++ b/ETH-PLUS_Jingzhao/README.md @@ -0,0 +1,43 @@ +# JingZhao: An Open-Source Framework for Rapid NIC Prototyping + +JingZhao is an open-sourced framework for NIC prototyping, which could be leveraged to +rapidly implement and verify a domain-specific NIC. JingZhao is developed by Institute of Computing Technology, Chinese Academy of Sciences, and is the first open-source RDMA NIC solution completely compatible to the standard OFED communication library. The RNIC was also taped out using TSMC's 28nm process to validate our design. + +For design considerations and principles in detail, see [our paper](https://arxiv.org/pdf/2410.08476). + +## Sub-directories Overview + +``` +|---JingZhao1 # first version +|---JingZhao2 + |---benchmark + |---documents + |---hardware + | |---fpga + | |---hdl # hardware design of JingZhao + |---simulator # RNIC architecture simulator based on Gem5 + |---drivers + | |---ib_hgrnic # user-space driver + | |---libhgrnic # kernel-space driver + |---verification + |---bin # verification configuration scripts + |---src # source files of verification framework +``` + +## Hardware Design + +## RTL Simulation + +JingZhao project provides RTL simulation framework written in SystemVerilog in directory `JingZhao2/verification`. `JingZhao2/verification/bin/Makefile` defines the parameters for compilation and test case. + +To use the framework, make sure your system has VCS and UVM installed. + +Compile the framework by `make com`. Then run the verification by `make run`. This command runs a script defining communication patterns in the verification. The verification generates a log file named `run.log` and a waveform file named `wave.vpd`. The waveform file can be opened using DVE, a waveform viewer embedded in VCS. + +## Gem5 Simulation + +To quickly evaluate the performance of a NIC hardware design before implemented in RTL, JingZhao provides a NIC simulator. The project is in directory `JingZhao2/simulator/RNIC_Simulator`. The simulator is written mainly in C++, based on Gem5. For details, see the simulator submodule. + +## LICENSE + +Copyright © 2020-2025 Institute of Computing Technology, Chinese Academy of Sciences. \ No newline at end of file