Add Repo: ModRetro_oss-chromatic-console-fpga

ModRetro_oss-chromatic-console-fpga/CHANGELOG.md

@@ -0,0 +1,101 @@
+## v18.8
+
+### Changed
+- Enable audio until ESP32 can configure the FPGA
+
+### Fixed
+- IO0/En control sometimes fails to boot the ESP32
+- The FPGA sometimes resets during play
+
+## v18.7
+
+### Fixed
+- Custom sprite palettes distinguish betwen obj0 and obj1
+
+## v18.6
+
+### Added
+- Support for streaming audio over USB.
+- Support for custom palettes to override existing palette after boot.
+
+### Changed
+- Inverted audio polarity
+
+## Fixed
+- Reworked the design of frame blending
+
+## v18.5
+
+### Added
+- Support for streaming on macOS and Discord.
+
+### Changed
+- The default palettes changed for `A + B + Right` and `A + B + Left`. All credit to **rayjt9**.
+- Tuned settings for the Chromatic Power Core.
+
+### Fixed
+- LED indicator light now correct for AA, USB, and Chromatic Power Core use cases.
+- Fixed an issue where the clock would skip in titles with an RTC (e.g. Pokemon Crystal).
+- Fixed an issue where save data could be lost in some titles (e.g. Pokemon Crystal).
+- Streaming no longer requires flipping the video in OBS.
+- Miscellaneous compatibility fixes.
+
+## v18.4
+
+### Added
+- Option to ignore diagonal inputs from the D-Pad
+- Option to use the background palette 0 color (prevents screen transition flash)
+- Option to set low battery icon display behavior
+
+### Changed
+- Tuned battery thresholds for 1.2V NiMH AA's
+
+### Fixed
+- Reduce backlight flashing when power source is nearly depleted
+- Support for Kirby Tilt-n-Tumble
+- Improved Chromatic firmware version detection
+- Support streaming to Linux platforms
+
+## v18.0
+
+### Changed
+- Improved button debouncing.
+
+### Fixed
+- Fully mute game audio when speaker wheel is turned to minimum.
+- Silent mode mutes all device audio output.
+- Suppress invalid DPAD inputs to correct character sprite glitch.
+- Color decoding bug corrected (greyscale check).
+
+## v17.0
+
+### Note
+The MCU must be updated to v0.12.X or newer as the underlying communication protocol changed.
+
+### Changed
+- Enable backlight switch on independent from MCU communication.
+- Supports updated UART protocol.
+
+## v16.0
+
+### Note
+The version of the IDE was switched to Gowin IDE v1.9.9.03. This resolves a synthensis bug which resulted in a palette flickering issue. Do not build with Gowin IDE v1.9.9.02 or older going forward.
+
+### Added
+- Reset the FPGA core when a cartridge is removed.
+- Add hotkey for reset (Menu+A+B+Start+Select).
+- Add hotkeys for brightness (Menu+Left/Right).
+
+### Changed
+- Only show icon overlays when the OSD is off.
+- USB CDC descriptors for Linux & macOS.
+
+### Fixed
+- Improved AA/LiPo detection logic to resolve critical battery false positives.
+- Fixes palette flickering issue seen on some games like Tetris.
+
+## v13.1
+This is the first production release.
+
+## v13.0 and older
+A preliminary engineering release.

ModRetro_oss-chromatic-console-fpga/CODE_OF_CONDUCT.md

@@ -0,0 +1,135 @@
+
+# Contributor Covenant Code of Conduct
+
+## Our Pledge
+
+We as members, contributors, and leaders pledge to make participation in our
+community a harassment-free experience for everyone, regardless of age, body
+size, visible or invisible disability, ethnicity, sex characteristics, gender
+identity and expression, level of experience, education, socio-economic status,
+nationality, personal appearance, race, caste, color, religion, or sexual
+identity and orientation.
+
+We pledge to act and interact in ways that contribute to an open, welcoming,
+diverse, inclusive, and healthy community.
+
+## Our Standards
+
+Examples of behavior that contributes to a positive environment for our
+community include:
+
+* Demonstrating empathy and kindness toward other people
+* Being respectful of differing opinions, viewpoints, and experiences
+* Giving and gracefully accepting constructive feedback
+* Accepting responsibility and apologizing to those affected by our mistakes,
+  and learning from the experience
+* Focusing on what is best not just for us as individuals, but for the overall
+  community
+
+Examples of unacceptable behavior include:
+
+* The use of sexualized language or imagery, and sexual attention or advances of
+  any kind
+* Trolling, insulting or derogatory comments, and personal or political attacks
+* Public or private harassment
+* Publishing others' private information, such as a physical or email address,
+  without their explicit permission
+* Other conduct which could reasonably be considered inappropriate in a
+  professional setting
+
+## Enforcement Responsibilities
+
+Community leaders are responsible for clarifying and enforcing our standards of
+acceptable behavior and will take appropriate and fair corrective action in
+response to any behavior that they deem inappropriate, threatening, offensive,
+or harmful.
+
+Community leaders have the right and responsibility to remove, edit, or reject
+comments, commits, code, wiki edits, issues, and other contributions that are
+not aligned to this Code of Conduct, and will communicate reasons for moderation
+decisions when appropriate.
+
+## Scope
+
+This Code of Conduct applies within all community spaces, and also applies when
+an individual is officially representing the community in public spaces.
+Examples of representing our community include using an official email address,
+posting via an official social media account, or acting as an appointed
+representative at an online or offline event.
+
+## Enforcement
+
+Instances of abusive, harassing, or otherwise unacceptable behavior may be
+reported to the community leaders responsible for enforcement at
+[INSERT CONTACT METHOD].
+All complaints will be reviewed and investigated promptly and fairly.
+
+All community leaders are obligated to respect the privacy and security of the
+reporter of any incident.
+
+## Enforcement Guidelines
+
+Community leaders will follow these Community Impact Guidelines in determining
+the consequences for any action they deem in violation of this Code of Conduct:
+
+### 1. Correction
+
+**Community Impact**: Use of inappropriate language or other behavior deemed
+unprofessional or unwelcome in the community.
+
+**Consequence**: A private, written warning from community leaders, providing
+clarity around the nature of the violation and an explanation of why the
+behavior was inappropriate. A public apology may be requested.
+
+### 2. Warning
+
+**Community Impact**: A violation through a single incident or series of
+actions.
+
+**Consequence**: A warning with consequences for continued behavior. No
+interaction with the people involved, including unsolicited interaction with
+those enforcing the Code of Conduct, for a specified period of time. This
+includes avoiding interactions in community spaces as well as external channels
+like social media. Violating these terms may lead to a temporary or permanent
+ban.
+
+### 3. Temporary Ban
+
+**Community Impact**: A serious violation of community standards, including
+sustained inappropriate behavior.
+
+**Consequence**: A temporary ban from any sort of interaction or public
+communication with the community for a specified period of time. No public or
+private interaction with the people involved, including unsolicited interaction
+with those enforcing the Code of Conduct, is allowed during this period.
+Violating these terms may lead to a permanent ban.
+
+### 4. Permanent Ban
+
+**Community Impact**: Demonstrating a pattern of violation of community
+standards, including sustained inappropriate behavior, harassment of an
+individual, or aggression toward or disparagement of classes of individuals.
+
+**Consequence**: A permanent ban from any sort of public interaction within the
+community.
+
+## Attribution
+
+This Code of Conduct is adapted from the [Contributor Covenant][homepage],
+version 2.1, available at
+[https://www.contributor-covenant.org/version/2/1/code_of_conduct.html][v2.1].
+
+Community Impact Guidelines were inspired by
+[Mozilla's code of conduct enforcement ladder][Mozilla CoC].
+
+For answers to common questions about this code of conduct, see the FAQ at
+[https://www.contributor-covenant.org/faq][FAQ]. Translations are available at
+[https://www.contributor-covenant.org/translations][translations].
+
+[homepage]: https://www.contributor-covenant.org
+[v2.1]: https://www.contributor-covenant.org/version/2/1/code_of_conduct.html
+[Mozilla CoC]: https://github.com/mozilla/diversity
+[FAQ]: https://www.contributor-covenant.org/faq
+[translations]: https://www.contributor-covenant.org/translations
+
+

ModRetro_oss-chromatic-console-fpga/CONTRIBUTING.md

@@ -0,0 +1 @@
+Please check back later. We will populate this soon.

ModRetro_oss-chromatic-console-fpga/README.md

@@ -0,0 +1,77 @@
+# Chromatic FPGA
+This repository houses the ModRetro Chromatic's FPGA design files.
+
+For more information about the ModRetro Chromatic, please see visit [ModRetro.com](https://modretro.com/).
+
+## Setup
+
+### Repository
+
+This project builds upon the open source work provided by the Game Boy `MiSTer` project. When checking out this repository, make sure to run the following command as this repository submodules the Game Boy `MiSTer` project.
+
+```bash
+git submodule update --init --recursive
+```
+
+### Gowin Development Environment
+
+**The Gowin FPGA Designer v1.9.9.03 must be used.** Using Gowin IDE v1.9.10.X or newer is currently not supported by this build.
+
+You will also need to apply for a local license with Gowin through their website:
+https://www.gowinsemi.com/en/support/license
+
+The license expires after one year and will require reactivation.
+
+You will receive an email within a few minutes with a `.lic` file attached. Run the Gowin IDE and install the license when it prompts you. You'll need to close and re-open the GOWIN IDE if everything was successful.
+
+## Building
+Once in the IDE, load `evt1_x2.gprj` project and click on the green recycle-like button icon to run synthesis and PnR. This will take about 5-10 minutes to complete.
+
+## Flashing
+Flashing can be performed using the official [Gowin Programmer](https://www.gowinsemi.com/en/) software or the [`openFPGALoader`](https://github.com/trabucayre/openFPGALoader) utility through the Chromatic's USB interface. The Gowin Programmer requires the installation of the GWU2X device driver.
+
+Note:
+1. The Chromatic must be powered on for either tool to detect the FPGA. This means the power switch is in the **ON** position.
+2. If using `openFPGALoader`, the tool must be compiled with support for the Gowin GWU2X cable.
+
+### Example Using `openFPGALoader`
+**Detect the Chromatic FPGA While Powered On**
+```bash
+openFPGALoader --detect --cable gwu2x
+```
+
+You will see an output similar to:
+```
+empty
+User requested: 6000000 real frequency is 6000000
+index 0:
+        idcode 0x1281b
+        manufacturer Gowin
+        family GW5A
+        model  GW5A-25
+        irlength 8
+```
+
+**Flashing the Chromatic**
+
+```bash
+openFPGALoader --write-flash --cable gwu2x --reset <file>
+```
+
+Here, `<file>` refers to the generated bitstream file. This file can be found at `esp32t/impl/pnr/evt1_x2.fs`.
+
+## Custom Modifications
+
+When modifying the RTL design, please also update the 14-bit FPGA version within [esp32t/src/rtl/BSP/system_monitor.sv] around line 384 (see `version`).
+
+This will ensure you can always using the [ModRetro Update Tool](https://modretro.com/pages/downloads#mrupdater) to restore your Chromatic to the latest official release.
+
+## Issues
+Please submit all issues and bug reports through our [Contact Form](https://modretro.com/pages/contact).
+
+## Attributions
+- [GOWIN Semiconductor](https://www.gowinsemi.com/en/)
+- [MiSTer](https://github.com/MiSTer-devel/Gameboy_MiSTer)
+
+## Special Thanks
+- [rayjt9] For their palette improvements to the BootROM.

ModRetro_oss-chromatic-console-fpga/esp32t/build.tcl

@@ -0,0 +1,51 @@
+add_file -type verilog "src/fifo1k/fifo1k.v"
+add_file -type verilog "src/gowin_adc/gowin_adc.v"
+add_file -type verilog "src/rtl/BSP/ST7785_init.v"
+add_file -type verilog "src/rtl/BSP/ST7785_panel_master.v"
+add_file -type verilog "src/rtl/BSP/adc_wrap.v"
+add_file -type verilog "src/rtl/BSP/aud_system_top.v"
+add_file -type verilog "src/rtl/BSP/gb_burst_write.v"
+add_file -type verilog "src/rtl/BSP/i2c_master.sv"
+add_file -type verilog "src/rtl/BSP/mem_system_top.sv"
+add_file -type verilog "src/rtl/BSP/mm_burst_read_to_stream.v"
+add_file -type verilog "src/rtl/BSP/mm_burst_write.v"
+add_file -type verilog "src/rtl/BSP/mpmc.v"
+add_file -type verilog "src/rtl/BSP/polling_master.v"
+add_file -type verilog "src/rtl/BSP/qspi_slave.v"
+add_file -type verilog "src/rtl/BSP/system_monitor.v"
+add_file -type verilog "src/rtl/BSP/tlv320_init.v"
+add_file -type verilog "src/rtl/BSP/uart/fixed_point_divider/fixed_point_divider.v"
+add_file -type verilog "src/rtl/BSP/uart/uart.v"
+add_file -type verilog "src/rtl/BSP/uart/usb_uart_config.v"
+add_file -type verilog "src/rtl/BSP/vid_system_top.v"
+add_file -type verilog "src/rtl/BSP/vid_tpg.v"
+add_file -type verilog "src/rtl/EMU/CORE/cheatcodes.sv"
+add_file -type verilog "src/rtl/EMU/CORE/dpramV.v"
+add_file -type verilog "src/rtl/EMU/CORE/dpram_difV.v"
+add_file -type verilog "src/rtl/EMU/CORE/gb.v"
+add_file -type verilog "src/Gameboy_MiSTer/rtl/hdma.v"
+add_file -type verilog "src/rtl/EMU/CORE/link.v"
+add_file -type verilog "src/rtl/EMU/CORE/sprites.v"
+add_file -type verilog "src/Gameboy_MiSTer/rtl/timer.v"
+add_file -type verilog "src/rtl/EMU/CORE/video.v"
+add_file -type verilog "src/rtl/EMU/cart.v"
+add_file -type verilog "src/rtl/EMU/emu_system_top.v"
+add_file -type vhdl "src/rtl/BSP/MultiPortRamCtrl.vhd"
+add_file -type vhdl "src/rtl/BSP/PSRAMBIST_Burst.vhd"
+add_file -type vhdl "src/rtl/BSP/PSRAMController.vhd"
+add_file -type vhdl "src/rtl/BSP/uart/uart_rx.vhd"
+add_file -type vhdl "src/rtl/BSP/uart/uart_tx.vhd"
+add_file -type vhdl "src/rtl/EMU/CORE/T80/GBse.vhd"
+add_file -type vhdl "src/Gameboy_MiSTer/rtl/T80/T80.vhd"
+add_file -type vhdl "src/Gameboy_MiSTer/rtl/T80/T80_ALU.vhd"
+add_file -type vhdl "src/rtl/EMU/CORE/T80/T80_MCode.vhd"
+add_file -type vhdl "src/Gameboy_MiSTer/rtl/T80/T80_Pack.vhd"
+add_file -type vhdl "src/Gameboy_MiSTer/rtl/T80/T80_Reg.vhd"
+add_file -type vhdl "src/rtl/EMU/CORE/bus_savestates.vhd"
+add_file -type vhdl "src/Gameboy_MiSTer/rtl/gb_savestates.vhd"
+add_file -type vhdl "src/Gameboy_MiSTer/rtl/gb_statemanager.vhd"
+add_file -type vhdl "src/rtl/EMU/CORE/gbc_snd.vhd"
+add_file -type vhdl "src/Gameboy_MiSTer/rtl/reg_savestates.vhd"
+add_file -type vhdl "src/rtl/EMU/CORE/speedcontrol.vhd"
+add_file -type other "src/rtl/BSP/tlv320regs.hex"
+

ModRetro_oss-chromatic-console-fpga/esp32t/build_evt1_x2.tcl

@@ -0,0 +1,50 @@
+source build.tcl
+set_device GW5A-EV25UG256CC1/I0 -device_version A 
+set_option -synthesis_tool gowinsynthesis
+set_option -top_module top
+set_option -verilog_std sysv2017
+set_option -vhdl_std vhd2008
+set_option -rw_check_on_ram 1
+set_option -use_sspi_as_gpio 1
+set_option -power_on_reset_monitor 1
+set_option -use_i2c_as_gpio 1
+set_option -use_cpu_as_gpio 1
+set_option -multi_boot 0
+set_option -bit_format bin
+set_option -bg_programming jtag_sspi_qsspi
+set_option -output_base_name evt1_x2_v07
+set_option -use_mspi_as_gpio 1
+add_file -type verilog  "src/board/evt1_x2/header.vh"
+add_file -type cst      "src/board/evt1_x2/evt1_x2.cst"
+add_file -type sdc      "src/board/evt1_x2/evt1_x2.sdc"
+#add_file -type gao      "src/psram.rao"
+
+#add_file -type verilog "src/rtl/USB/USBUVC/usbuvc_top.v"
+#add_file -type verilog "src/rtl/USB/USBUVC/Gowin_PLL_UVC/Gowin_PLL_UVC.v"
+#add_file -type verilog "src/rtl/USB/USBUVC/usb_video/usb_defs.v"
+#add_file -type verilog "src/rtl/USB/USBUVC/usb_video/usb_descriptor_video.v"
+#add_file -type verilog "src/rtl/USB/USBUVC/usb_video/uvc_defs.v"
+#add_file -type verilog "src/rtl/USB/USBUVC/usb_device_controller/usb_device_controller.v"
+#add_file -type verilog "src/rtl/USB/USBUVC/usb2_0_softphy/usb2_0_softphy_top.v"
+#add_file -type verilog "src/rtl/USB/USBUVC/usb2_0_softphy/usb2_0_softphy_name.v"
+#add_file -type verilog "src/rtl/USB/USBUVC/usb2_0_softphy/usb2_0_softphy_encryption.v"
+#add_file -type verilog "src/rtl/USB/USBUVC/usb2_0_softphy/static_macro_define.v"
+
+add_file -type verilog "src/rtl/USB/USBUVCUART/usbuvcuart_top.v"
+add_file -type verilog "src/rtl/USB/USBUVCUART/Gowin_PLL_UVC/Gowin_PLL_UVC.v"
+add_file -type verilog "src/rtl/USB/USBUVCUART/usb_video/usb_defs.v"
+add_file -type verilog "src/rtl/USB/USBUVCUART/usb_video/usb_descriptor_video.v"
+add_file -type verilog "src/rtl/USB/USBUVCUART/usb_video/uvc_defs.v"
+add_file -type verilog "src/rtl/USB/USBUVCUART/usb_device_controller/usb_device_controller.v"
+add_file -type verilog "src/rtl/USB/USBUVCUART/usb2_0_softphy/usb2_0_softphy_top.v"
+add_file -type verilog "src/rtl/USB/USBUVCUART/usb2_0_softphy/usb2_0_softphy_name.v"
+add_file -type verilog "src/rtl/USB/USBUVCUART/usb2_0_softphy/usb2_0_softphy_encryption.v"
+add_file -type verilog "src/rtl/USB/USBUVCUART/usb2_0_softphy/static_macro_define.v"
+add_file -type verilog "src/rtl/USB/USBUVCUART/uart/uart.v"
+add_file -type verilog "src/rtl/USB/USBUVCUART/sync_fifo/usb_fifo.v"
+add_file -type verilog "src/rtl/USB/USBUVCUART/sync_fifo/sync_rx_pkt_fifo.v"
+add_file -type verilog "src/rtl/USB/USBUVCUART/sync_fifo/sync_tx_pkt_fifo.v"
+
+add_file -type verilog "src/gowin_pll_preevt/gowin_pll.v"
+add_file -type verilog "src/top.v"
+run all

ModRetro_oss-chromatic-console-fpga/esp32t/impl/evt1_x2_process_config.json

@@ -0,0 +1,88 @@
+{
+ "BACKGROUND_PROGRAMMING" : "jtag_sspi_qsspi",
+ "COMPRESS" : false,
+ "CPU" : true,
+ "CRC_CHECK" : true,
+ "Clock_Route_Order" : 1,
+ "Correct_Hold_Violation" : true,
+ "DONE" : false,
+ "DOWNLOAD_SPEED" : "210/2",
+ "Disable_Insert_Pad" : false,
+ "ENABLE_CTP" : false,
+ "ENABLE_MERGE_MODE" : false,
+ "ENCRYPTION_KEY" : false,
+ "ENCRYPTION_KEY_TEXT" : "00000000000000000000000000000000",
+ "ERROR_DECTION_AND_CORRECTION" : false,
+ "ERROR_DECTION_ONLY" : false,
+ "ERROR_INJECTION" : false,
+ "EXTERNAL_MASTER_CONFIG_CLOCK" : false,
+ "Enable_DSRM" : false,
+ "FORMAT" : "binary",
+ "FREQUENCY_DIVIDER" : "1",
+ "Generate_Constraint_File_of_Ports" : false,
+ "Generate_IBIS_File" : false,
+ "Generate_Plain_Text_Timing_Report" : false,
+ "Generate_Post_PNR_Simulation_Model_File" : false,
+ "Generate_Post_Place_File" : false,
+ "Generate_SDF_File" : false,
+ "Generate_VHDL_Post_PNR_Simulation_Model_File" : false,
+ "Global_Freq" : "default",
+ "GwSyn_Loop_Limit" : 2000,
+ "HOTBOOT" : false,
+ "I2C" : true,
+ "I2C_SLAVE_ADDR" : "00",
+ "IncludePath" : [
+
+ ],
+ "Incremental_Compile" : "",
+ "Initialize_Primitives" : false,
+ "JTAG" : false,
+ "MODE_IO" : false,
+ "MSPI" : true,
+ "MSPI_JUMP" : false,
+ "MULTIBOOT_ADDRESS_WIDTH" : "24",
+ "MULTIBOOT_MODE" : "Normal",
+ "MULTIBOOT_SPI_FLASH_ADDRESS" : "000000",
+ "MULTIJUMP_ADDRESS_WIDTH" : "24",
+ "MULTIJUMP_MODE" : "Normal",
+ "MULTIJUMP_SPI_FLASH_ADDRESS" : "000000",
+ "Multi_Boot" : false,
+ "OUTPUT_BASE_NAME" : "evt1_x2",
+ "POWER_ON_RESET_MONITOR" : true,
+ "PRINT_BSRAM_VALUE" : true,
+ "PROGRAM_DONE_BYPASS" : false,
+ "PlaceInRegToIob" : true,
+ "PlaceIoRegToIob" : true,
+ "PlaceOutRegToIob" : true,
+ "Place_Option" : "0",
+ "Process_Configuration_Verion" : "1.0",
+ "Promote_Physical_Constraint_Warning_to_Error" : true,
+ "READY" : false,
+ "RECONFIG_N" : false,
+ "Ram_RW_Check" : true,
+ "Replicate_Resources" : false,
+ "Report_Auto-Placed_Io_Information" : false,
+ "Route_Maxfan" : 23,
+ "Route_Option" : "1",
+ "Run_Timing_Driven" : true,
+ "SECURE_MODE" : false,
+ "SECURITY_BIT" : true,
+ "SEU_HANDLER" : false,
+ "SEU_HANDLER_CHECKSUM" : false,
+ "SEU_HANDLER_MODE" : "auto",
+ "SSPI" : true,
+ "STOP_SEU_HANDLER" : false,
+ "Show_All_Warnings" : false,
+ "Synthesize_tool" : "GowinSyn",
+ "TclPre" : "",
+ "TopModule" : "top",
+ "USERCODE" : "1337D00D",
+ "Unused_Pin" : "As_input_tri_stated_with_pull_up",
+ "VCCAUX" : "3.3",
+ "VCCX" : "3.3",
+ "VHDL_Standard" : "VHDL_Std_2008",
+ "Verilog_Standard" : "Vlg_Std_Sysv2017",
+ "WAKE_UP" : "0",
+ "show_all_warnings" : false,
+ "turn_off_bg" : false
+}

ModRetro_oss-chromatic-console-fpga/esp32t/src/board/evt1_x2/evt1_x2.sdc

@@ -0,0 +1,34 @@
+create_generated_clock -name xclk2 -source [get_ports {CLK_FPGA}] -master_clock exclk -divide_by 1 -multiply_by 4 [get_pins {u_Gowin_PLL/PLLA_inst/CLKOUT0}]
+create_generated_clock -name pclk -source [get_ports {CLK_FPGA}] -master_clock exclk -divide_by 1 -multiply_by 1 [get_pins {u_Gowin_PLL/PLLA_inst/CLKOUT1}]
+create_generated_clock -name hclk -source [get_ports {CLK_FPGA}] -master_clock exclk -divide_by 2 -multiply_by 1 [get_pins {u_Gowin_PLL/PLLA_inst/CLKOUT2}]
+create_generated_clock -name gclk -source [get_ports {CLK_FPGA}] -master_clock exclk -divide_by 4 -multiply_by 1 [get_pins {u_Gowin_PLL/PLLA_inst/CLKOUT3}]
+create_generated_clock -name xclk -source [get_ports {CLK_FPGA}] -master_clock exclk -divide_by 1 -multiply_by 2 [get_pins {u_Gowin_PLL/PLLA_inst/CLKOUT4}]
+
+create_clock -name sclk -period 25 [get_ports {QSPI_CLK}]
+create_clock -name exclk -period 29.802322 [get_ports {CLK_FPGA}]
+
+set_clock_groups -asynchronous -group [get_clocks {pclk}] -group [get_clocks {hclk}]
+set_clock_groups -asynchronous -group [get_clocks {pclk}] -group [get_clocks {gclk}]
+set_clock_groups -asynchronous -group [get_clocks {hclk}] -group [get_clocks {gclk}]
+
+set_max_delay -from [get_ports {CART_D[*]}] -to [get_clocks {hclk}] 13
+set_max_delay -from [get_clocks {hclk}] -to  [get_ports {CART_A[*]}] 14
+set_max_delay -from [get_clocks {hclk}] -to  [get_ports {CART_WR}] 14
+set_max_delay -from [get_clocks {hclk}] -to  [get_ports {CART_RD}] 14
+set_max_delay -from [get_clocks {hclk}] -to  [get_ports {CART_CS}] 14
+set_max_delay -from [get_clocks {hclk}] -to  [get_ports {LINK_SD}] 14
+set_max_delay -from [get_clocks {hclk}] -to  [get_ports {CART_D[*]}] 14
+
+create_clock -name ck24 -period 41.666667 -waveform {0 20.833333} [get_ports {CLK_24MHz}]
+
+set_clock_groups -asynchronous -group [get_clocks {pclk}] -group [get_clocks {hclk}]
+set_clock_groups -asynchronous -group [get_clocks {pclk}] -group [get_clocks {gclk}]
+set_clock_groups -asynchronous -group [get_clocks {hclk}] -group [get_clocks {gclk}]
+
+// USB Clocks
+create_generated_clock -name PHY_CLKOUT -source [get_ports {CLK_24MHz}] -master_clock ck24 -divide_by 16 -multiply_by 40 [get_pins {u_usb_top/u_Gowin_PLL_USB/PLLA_inst/CLKOUT1}]
+create_generated_clock -name fclk_960M -source [get_ports {CLK_24MHz}] -master_clock ck24 -divide_by 1 -multiply_by 40 [get_nets {u_usb_top/fclk_960M}]
+create_generated_clock -name clk24p -source [get_ports {CLK_24MHz}] -master_clock ck24 -divide_by 1 -multiply_by 1 [get_pins {u_usb_top/u_Gowin_PLL_USB/PLLA_inst/CLKOUT2}]
+create_clock -name usbintsclk -period 8 -waveform {0 4} [get_nets {u_usb_top/u_USB_SoftPHY_Top/usb2_0_softphy/u_usb_20_phy_utmi/u_usb2_0_softphy/u_usb_phy_hs/sclk}] -add
+set_clock_groups -asynchronous -group [get_clocks {PHY_CLKOUT}] -group [get_clocks {fclk_960M}]
+set_clock_groups -asynchronous -group [get_clocks {PHY_CLKOUT}] -group [get_clocks {usbintsclk}]

ModRetro_oss-chromatic-console-fpga/esp32t/src/fifo1k/fifo1k.v

@@ -0,0 +1,642 @@
+//
+//Written by GowinSynthesis
+//Tool Version "V1.9.9 (64-bit)"
+//Sat Feb 24 20:59:00 2024
+
+//Source file index table:
+//file0 "\C:/gh/Experimental1/esp32t/src/fifo1k/temp/FIFO/fifo_define.v"
+//file1 "\C:/gh/Experimental1/esp32t/src/fifo1k/temp/FIFO/fifo_parameter.v"
+//file2 "\C:/Gowin/Gowin_V1.9.9_x64/IDE/ipcore/FIFO/data/edc.v"
+//file3 "\C:/Gowin/Gowin_V1.9.9_x64/IDE/ipcore/FIFO/data/fifo.v"
+//file4 "\C:/Gowin/Gowin_V1.9.9_x64/IDE/ipcore/FIFO/data/fifo_top.v"
+`timescale 100 ps/100 ps
+`pragma protect begin_protected
+`pragma protect version="2.3"
+`pragma protect author="default"
+`pragma protect author_info="default"
+`pragma protect encrypt_agent="GOWIN"
+`pragma protect encrypt_agent_info="GOWIN Encrypt Version 2.3"
+
+`pragma protect encoding=(enctype="base64", line_length=76, bytes=256)
+`pragma protect key_keyowner="GOWIN",key_keyname="GWK2023-09",key_method="rsa"
+`pragma protect key_block
+agRQjXaqnlxj1I23WV89ifd8tJyCShyjSY4mC+CuxmW0lVJnGLoZmv55Hw9LpOiKlJiQVjHmKwxl
+5p9cY/0RXhjU7r6QPRq48IQo17/imUCgK2yhmlcewi9M2D6Nn4nFU8vkW9CHhbBDjEUpyel62HAD
+mUSiI3nt2/QmHtdV3ZWM0i20xOdyNWHJM3UclvCVN9fyxGra+bhGUB4QUD6eebtRASB3CDK2APWD
+jjv1E1wMc3TrBX9UuucmEkmuBy6nLg33qFz+1u32tBEKwsVUNMdZNkxfulxVua6LfrjV1Jyg2eI2
+3su5rM8b81AHIfrV0AAaouv2Ggo0x+/n5GzfEg==
+
+`pragma protect encoding=(enctype="base64", line_length=76, bytes=31776)
+`pragma protect data_keyowner="default-ip-vendor"
+`pragma protect data_keyname="default-ip-key"
+`pragma protect data_method="aes128-cfb"
+`pragma protect data_block
+NkA8qi1wsYUw6AOcAXafPfifaUimR5DGReK0spUFmRXUYf2oEAeQGRakjjSTjPt9kqF3ftRLH9Lh
+c8At/XhS2CaLnBxducUAXDvIgPcJ3+zyHHk3phg+OwbIqw7F71+3tfjn1c1Eu0aR6yUC142Uxl45
+IvuLwpJbY0vPdL2te1nY2pspcZ1bGKxqgtbZzhEWEqA+Xjx2jRm4xrd1mi5OD78VAY6ITP+Ajz4R
+WWGYRXZIohfkMt4mpE9DmemnH/BEfZJ+bkiOMVKQFvd4hnV+RAu+mAMXnikVG/w8lwhGFVkIS/lS
+Pv6wmh/iYE/MLXJBJSQG7J4SguSIb18uY8bHBy6BQXQRkP9PnSJV0A/PI4QSqUyBw5s2Q9+9p7lg
+2hwAwQCRQWy4y0cxYW6I7DdSbJgn2rqEF7+eOCpnuCI0OnQp3PVKYsMvFFCZYQB3p4CoA39iUwjo
+0qxzBr0iRmVEKXQcxYHWOphs2bOwS5GY7mq0/7vgS+0ezyxJw3dcMBmsc3FzIKWj8Ogh+8hz92it
+o6K0cMHVgnSqSBLFOUbAlYVJ8NmMC+EY56UK2Bl6Srt5zI9gyOzoyNryXXqsmppGhcFKSQDG1w7c
+zKXnFtcrmPm/OfMJQHd7yvFXbkV0Ml8qTawmzI6AB1OwEcSnrttjGFxPdi4liIJY2g3Tx0UWNR4w
+B8qVVxN64GoQ+ACc1+znQwSv8lvdPlwNEq7VURg5QwlNKiLiB+OsPo3MpGZZdWCDZPDc2Rnqv/mh
+yMd/xqUyL2fpopzCY0mrgxRqj+bCm71CWf1O/aM2VCIAUOk7XV+r7YBF4uvvybLkrdUwuBNa3tf4
+OhfxHo15danUfGILnYOdMW1QYG1/VqLkHC/CJQj45huu8iTE2rpd5FZ5tGmHXLlgqudIfqhCOCsV
+XJOSGfonQ/Celv2SUXJ5xRbpePylgacvafkfTcGpulysQPnsC2MNCJKc2XEqAsakIj3adV5PjAMr
+D5UhNgJEI5WnsRVOn6a56zT04p5OlyKWMjsRxFJd3MFt6wG6GaQOSIwSW1FujynE6wGVHjdvfeZt
+aZtOMzCw8styHJ3olc/wN/vfD5CtGK4v+N9zMecd9NvqSN9zU+GIw1H/evvdsMlYG63QE5DEx/c5
++tADINbEIQGbYSi/WHobVnSwDhvBXTTmJOBwUvAAbsPnBYdKc9QI96aG3Ms1FsTIFQ1/zjMpwy7Q
+RzZlmlGbIfLzTFdZ3cytJRtDV12ZGcEl6aRDUGMTnCzu9OUcUkRgtZDcvoeloUUpE3Q/WwZo83Aa
+ycHSkH1QV1cb+1/PmvjONo2HQKZUXDlwo7FKziY39vWL0RNkGfE1ttT1RHp7lqoWtV4qMiU5WwR4
+Cfz00dbEo6RDL/T6CFaAHnNZlvNTzEiu80nXRSSE42naLwdQZcZYxt3Mh1h4iAHjULbzp3Fny4WB
+qc20uVvYMryVVs941t0TSfjr+ZtgqAv1xevb5qnBtxOu1GovXW41jiaPf/c5OxeYM2hJLrjoEVGA
+x0HltfaLglOAQNzfNuLTQJlbGmGYHBQEQlOhNG8x8kyOsbvtaSxPaNHnPxbTiY8vQumVmkJ9rx3r
+ZqwNzmLMS71VSqG+9NoGDmIM8IXo4acwZnDuXOsH1j7tVum7K2f2FCVFNn/q7c/kj3g7sG6eRPZ0
+7+oU99xgxS5KinlzFhl7mFYo28g3D6HSz0yW7ysvM34c7xl48UQ5/5JV4yVNrslTrNOoQ+jZ5TqR
+9vxnNE9LPPcTOsmH04RVxEH0G4l+dtgvmnd9oapqmUEO9NXBsuCe9g9KvHIYiUWQUxOKQ3TwbjDh
+EKQTfX8edJ757EzdeCHRBQzzTyZzrtvnL0mgvAmKZo7V8zU4B6rARHKhba1JrkqaX6b0e3H3xBTh
+FYhZiVLcn/o3VwrYV9wbODCu4SNKBwiQz0zwuIepiPXWI/1zKlD5qbWZ09gO9QhpcIsLMwT4GHhI
+VtFgeqcf+FmWiQpeSI4arXX1XBm6c98tPPR+itJj54/HnQMk4wxW/luBhKqKT1MPrUuPIgif31O3
+SLtg6M/bGNCoNgiOClKuNEl341LJBXWCy1BmPLgr/bsJxVjliOQ/PpNxJEV81ygjXhx80LKdR37+
+s4B7yjCBUlBfm7+rea+hQ8xjdtjvw1lhc7E7QDHG5VpThnQCHT81Xuzhve88SPldyFBItumIgWYs
+Wcii+MJ+YX3ZOv2uoadF3f7HHt0iaJpVPWGOoymQRQyeRU22bky9okzjEX9wCQMWdMDu/Q9gL4Ec
+MAqwX+VVTbQhZwOpUFrDr6EIaedOo2EslPcJ5H6Nf6GezHA909tq6Gh2quP/hsBjQzvqNcZ3PmQc
+6hNJ33E7RGVWrnK++3j4jqSv6N0mlzoREfxXn0JSW0FibhwxKu74TC7oneWZUw1VNyCIuZBVxbBL
+0f+pyaDryv6BOwTwsSJJzW08LPYI0Xqyr5YOky1G16mONFbGzAFXQit4EeqG34XM5JcteAzpBldW
+TsBO7ss2nEFljZkxE+6lUQZy6iZfMxYwx7VxoZV2v/9IEnLC5XB3qyOTSnNOsgW9e1IBbLHC7Ws3
+eRcWgvNfi0y6ju4ayfYlOrUblOPDeh71Eq9B8oTz1Qe/E+bs5s8xMvTBk7BAswvCMh2NbCV+qH0Z
+FpixmNNU7FaW2RiCYhwcrLRhAj/AmLMhmfKbpyxElW23dUebqdI6yntJIy1GfT8cPL7N+7guLxCf
+IQoyq7FH73vi3cPO0vn84GKX9lbMZwQPNYmgQnmhevGUKUx665XioKYP5wEuzq9qPimaRig/TNBM
+74U16Z6d3Oj/CloXLObDEBscaoGJ5BAkcrZJRrw1YftVejHQ09Y5R4fW9rtZEvktRIP9xZ1D0WXT
+AMNmJh5VXJLTp/DJ3k4eIDLwI6alcXoSi7k5XeSDKBWibBkWeIuc9JMZzIdqG780GQ8DZAJKpjeL
+KUEn+xssbiIAowBgwUn08kdMMt2xCjHn4d8JuFRzFfng/B8jgUmOYD993D76OjtKQxmzKFGMCA0g
+rnars1JYZ15+8NphOR3JdeVIi+lPSz9EM2VE1ilpIWFQ1p8xaGwtjsBoMM8mTTmbGlNI2F/2J5hT
+Zt9qIemyfzNrfhJ6pisyRY1rgBNnb3lPF1jAqHq4udxQucDTINtqdota9ny/i0LBl5r0ikKNyg0M
+XnzYZV4pWHmNh+wt2/RYLnQfdHbeHacN95WfpA5CXFA3tTtVzh8RHU7NPIos6C6ZM0zLXgQCtf4S
+EHPwLPVfptNs2Zp5v4RHPVPePIPzV7YZbp6RNJCS3CTXfWwiawpevAuUKIRx2e4c1Xp92zlP3BAZ
+hPOvgQXMwjlKfegRZFBmPhmkfpPUH5SRWII6tVKbMakBDmE8FQLGeiEUiBrjXdyUuA6vRpkMuCXu
+J+pKBhqWiHk1M25VshbDMAC2pIlxCJbox/DRCNVgL9Qcx6RhgSvEkPxsQjeQR5hzSbx17OmTIMo+
+J7ftfiuQ/I7YcVV9j45mEG7lAMFsINRV/Xa8YVL5ACcmMWIaneKqfaBr13j453d/FlRIsj7otmAN
+4ybUuKTSpVazWJ/0yM+tsVtIXPnpbFo79qHDPxPbgbYMcJQo9742la4bnB/5nFbBrG6a6wMkiRNz
+11OY/bwtInzxmHQ5QcumhxUKFdQmd/lqfzigdwRGhqs7JiwmAvCQyStX020Nd/S2z4ihZ5biZORw
+ZAupPBkdXBTAPnNeCWQZGqdBkInkvIy54oCV78aBnbvz+hY94/0CqGujYkcQNxowjtGYjSs/e6XL
+EOeusHA4IZ9nB3NCa5dsd+JeNH61US6AaYpaLtHaBwi7VJ3XnZL7n1WmF6Egp04VH1lKX08FJn13
+VTP5LAkgLe/DxE2Dcs/hLe5MDmP9RE3ykoPJU9e423ErD4SLs0OWxYAzr0YmWUFT44OrVb0SXaY4
+8iYxtWRgoe4vttBezwVa+Tevdp57n6pwKia2OPAPmPKlhalJbZ54Fooz3GPaaaeT8v2lYVzWT9+L
+kn9GZLb0ApCpIZGg+yZ+SEkPMTG9rRSo4WQoRmOoQ6i1AA8Ettp66J5RTNOQr3ZY/lqQwN97UviP
+N4Ykjpw4e1khcyxf55psE2pzzN23q63/XPl353oi1doCIhgYuWFeJPUl6+nAqLXuJdHTCyZrZ8U4
+sjdozBy/wlQoRZtdEVQHjUJdAf6FvoP73nupp4fvGQ2iaW4E5ojNec3cSAlPEYd8D6XFSzEIoSbw
+hVZxrJzt1rfFJgovsuPnMFHdDGTyHLEXNbJ+5gMVINa4plpy6KdV4h+kQKTOfhcwGys8JMkiwXmi
+65cskpqqo8f+cS4Ssn4WobC8LwsK0jyEXemUhh3cDbE8hzYlcUfNuFzNN8NRMtfZ3Yzgbpj+4YFF
+/IcvIfrNed/w4q+V51HkbcXLbQDXxHcDQjs9WlTpUfrC2DHZ/LK/uhjHjdLYOEXA/ml+VZ0CcRUZ
+pK49w7JK+07N4vsrgaGkhBbDKgtYcwny28SYpPFFYiGyi7YNjM0bmHJmg1fedcLnXhAIVS53l0pN
+CqRWdjMz0ebIkIDeHIzniqnFGb5RppZGmu9vJvPYPbVbVrPEY5jTsk6mO+JWjP767IY1sjcB9ni0
+dG6VkLo7KCJD9Wp9Jyx3yLqihohLZ3nFdSAClK76KQg1oswQnDE8uOBqb7LZXnU6GBfaExnIMehx
+mGwZX8RqKLsz8oALW/IZcA8zjIOBByKdQecQ8I3x0DKxluIW4Bm0E0FNuBU7yDDZ9jItFMh+soRD
++abMQ64pQwFCNqSQLWnASj6RF7Q5oB01SY2CpWBBitrT/mIn0fGaVizxsBRzwnBMX6582Shw2Pt7
+RmEcxM1jh97igK5i/5XOdZjGcnZ2A52Q3ZBevMi1ArIHgs4ULtoGFagtSPztt4z1ldvackHkt3SQ
+QTldJwWKwOVDN/dSqXfVhUn/AnX6VY0n7xF1LLzMQynriCbxmnTpOSRoBOZpVOWLQJH0voeMEcFC
+kmEP8ZJPmOVn6Z+4kmGTChS+zvhvJ+QHj3f0FukED2CzoArk2IccKL9qaPBM+SmvVuH4ACPp2yjz
+G3yeR+m2Wvbsix+CStbb1YoQmLpITlR1vxKtv8prt9/ty2IWRPLQaQupqyJRTLHfGB0hY2+eVrcY
+bkmtdWjAkqxNh3enSZHdtGbxjthJz6+/ClwdTQncCAQmsQwonnlUn0S3kwr8II8vOroe1sZwVBSU
+lURI2JRhDS6E9IkjQW/hnox4MfooakZ4/QXwKbEhacaHcrCXfJwIZNGE7bO8ZjPCClalf4djBidC
+UWtx3eC6OTeipVZSjiXk8YdXkJItUoXfFDTE/JUa6iVqrLThZ/HGb2/TXuiUlx/ByO7mqPksRvAa
+AOFLAb5ZhzVjAJljwlxvJK5GcvxxuxCuSwejAValbHnaAHDa8loz+fSmraydjAPJSo9guaBr/CAc
+teyOP9cxVodazAI+abmi2y6ezgAcWMUjKDveQdhTv17qJP8Qu8BIt1DNMx3KLqwS8Nqfi/P6bdPI
+/STLMrFwZngB1tdU0MUuCFCnPaUPzZUL128om6nw43RW4veptU+GX4om6JWCVnodA77EPCslTac0
+iMQVHbL7TQa/b6SNQ/BB4QpPnrrbGQNbUiPa4NxpEsUiVY9qylCR5GGdo6ZWz0XU1N/1V1/eJUpV
+lnHxQOcAoBItHK19UYq3nkR5IPzyndLNysYMAeF/o87ZWHR+Y0/nkFtTowC16No5BDvBJrtDu8iO
+rpEGLbNBExNl1yvt0xhgnSGbSAP1ZwKtLjqZZviBtqkqk251dJw/3OPy+PaCYJ8b3UdWwerHLjHD
+dTsdQb/ylgbMhmqANlnm+ZQreDbrZ86rkd9dOr6nPmriQEN7vBxOwOOb2Sd6cNBFmPI9PlhTDfV1
+VFCPiRp2BPQN93PTpB8YZKBzXoSwrCWWQDw6IHBzPBOoObJS8FBYICiV4IEp0kH9iJbBwm29aHgi
+ovwXMYJbCOvF8oU+h+k63rbb59PF5FjuFvJHjS5QWH92X7HaYeBhV1RpokjTrzMSd4mNqLu+/jnc
+yGnV1Jih+gZSW9ZHZfteCRnH/x0VRC+OAEC/uAaxd/Ab2PXUrUDtd33knpFquKElu23/aeLTJ2xE
+DVMq3JuNar16gvmJXE1MJbmdFwghSgBjvlbKFl2oma9ieLKtohyq0tuPBFJXkmPEEETkItzKWOdN
+sLjMqvngNHe6cbmiqT4kRcXC8BHDY/dLzpaYIwDS0I9CtBu7rBetdG2SWIt0qIUM9IrItdRGm0KQ
+uBirQ0jShkIyF67164dlHxAhpJM8dMXIZc8lvFPymeTLcfPXBRUrHlDQOhEft7/C572B/lsq5RC6
+KUgyotlsfQ/w++/ii+kX7iqJlDLbP00WNSfoCGp6WpQMoMeXgz5VpSk4+NRq3xcQM48Diblhp4VY
+0ZKAX4h8hjB2a1n/IiqfUwHMXEvays5gvh5xV1Jmh8hqmgDfk1wSznHNGa4CigFIw5LV2ZAevUvS
+ueOT0NEC4B5P4xcr1488rYtHWp9DkxNYFDR9TCm3cSuxBnSzynTQkB2rxD76QZSLWRd+ifz2a8ai
+EntbaRXtpj5DTovLIyzNaA03MoqT2Ob859x0Osm7F2oIJpUpW7UN7AW7yArHjHtuDBlG7wYPN1/6
+j8uE0vnlKNwm2S9Bz0ThFcg1LbUCY1FX0e3z3hqacm9TTxw2OYKg++5TAzUQtGgyRVyoymXQJh4q
+1BIaD7blb98FLrjhsB7GxDqYmrXKL2eherh5CM6vV3r5BdA0M+H2VSv+jFxXBqrswsowABI/4BWg
+eWrn1ttdTTD1IcDWfJqbqYEJCtPWYBjUF0wDk2GZ6k49R62HYpzqDw6WikhlFpkFMJkHpuMGaJu+
+KLN6uW1E2bIZdlc3Wm3Qt5g5lH2Dx1OW+OFjjBMUTVYnxrHmHzGo/Eq00XI1TlNRu/teKVhvn4uj
+4Nyg2cW6AMxmlfHL3CEbbhuLPzWdbqd4JC/VA3YbgZ7rO52l1lRuALxLOWlXv+PdnrKZNFKtj2ho
+NkTC1jEl+WHAPTpX3xMCDIdPTc1164y+631M8IAaltE6Vkyf7ANuYOEHgFU6s70za4vQrI7khRhI
+KmnHZgbEqXYM7+VAdturWNpNkqMme9uhVdZnG9iMoRKNRZkD22lZ7Avxkb9e6rAm4b7jtLi+CaVi
+BmQ3hh3B9zxnzHCAvlTLqE9rGRE8A57Q4Y8j1fggAl2fTtDakwPIKBcsy8aZJbw6WQcaU0SqES+z
+up1h7ssZ4u9d60vLWx+XW/FLpzbdFC8ji81pnLD3M7UnDqbZL1HOvH1GjNkzp+rSMHD464caQPfM
+yhKvmzJ9VlTuumgfKhYy/Na8mcKAeNeQj5e2LIhOys1o9L07wE4BdGpXAWRN9OKU7h6UAADzg6/d
+M9NgKRaqT8yTX6etVO33K2cKjVqmj0+FzgC+5wnVMUPgCqduV54LCCv6mKZSr2vmFHNQAjmVSsA+
+xX+0T/vA2MlnKPnSq3TDhUqVdpPI/SHTlp7rygylPX+sT0ku7zw3OVTLkdzwhCquapUTYhGH6yQ4
+VYdOf25P9XjFWAwKSLaiXbCwKTr+IH9Pk/aGOhtAc6ZtAmEzKJdMz+HWOLMzKzuqhsi0ap4j8fby
+hysbLRjvZrcuIjoBa4q845dPy8nSwpc7wwBwBUsZaBefSLErrpZoxGXdob9UPQ3FhUG21s3K3wnk
+DlXFuFz6Xo3iGBlR8zoKCCVjBNS80Jc45+Yyb8XvzMPWNXl6uf2y8HSH+E+nUFj0XjooYMKdkT3f
+RLQQDPIAgfJdF+FgUNX3atqlBGpdlHEUCjMWQ/IPvFjawhPirz1VM9CG8z+f6j2bG4Nehvm6bCpi
+MXDmduvQgL4QLEKgXcotVsWuTmWh2NdP1a9qaC5VHt95YTG+wk1w4sTpsLtSInZXLKq60hbfi5qk
+1+H81soS6Ogy0hK1VSf5WqnK/SzhCAo63gLcb7ILdk+YcD2a6Dg71o+OhiQQH/MejibnQnXA5Pzu
+oH58xnYFHb0BNHl/095qf1bZQ1gISdmt5FC75ggk9/rDGxsyN0bprCyfhcToZbFnikwrV0ETQfvW
+rwunicM1sMGM0SvCLi4sdR9slxbEHVx+L11aW1+a+1G40sVqn5Bj3nWqNiOwmdkGiksLxwG6/V3i
+rCoew67Cucnwa5NlBKCVesGXLL9nPRJOk5Wbt02+5BIpgipXIp2bRQDZ+Vyb39wJkPWJDVnJVelA
+GF8l0W4UpPcT0jOqJz2BhmNpi3+uiwJcBwvBHv10PlCi225+eKWJIhT1/HTwx6npy/ATk1kEpSxB
+XuCo6W5naEbIItGk+Ief1EeQnFbm+XkpLqllEZrzqljdh1yFzzCIv+7W+MwVo/Ls2CKCKp+K2J12
+GhdGqUxwW8y94XSsbkOhdWYmz+65kHaIQYS/1dSEO2kKwqi4QihpgOlWWfSsiq6Z01V0dPCJuC2J
+Gu2KZqeabFabp+u8xbeLW46rX5IaqOhKCTH3fFbSzeK2+MXv51gQ4tYRmd8FPD7IIAS/6W9EaFAy
+YHWmpPQD0ScPQCN2HNK3EzZkbgwzcosEpiDQ2+OYGKc8P+9uJiL0VHW320xZPRFwNAYcN1rK5aVG
+glHV44GJSHgttGJIJZR2YCKyjhfqQmBia7n4wYnCncWe/w6QLRlPtYmkRRe4q3tEpU7eh4LzOisd
+FfDBCjd1cLxGm0ipiQsmLYq0w/sbh51KwpoiVe7U0EGffAGb3ZbN20vFIx6dFG+KUv6ozMZDDCkq
+lnY2niwxJObgHUvFCDdCP/rwuWuWfrqXuY2nOApJuqrS/QpAJSR7yX5Uacxvgl7zSgLqSbsCYIVv
+2+jBXXCDeuQGC8N87LMl+lL2XFpTBVsNmv6hoDCHqMj4lWLrbV5T2nNwkHSMK7MqXO45FeAIyG8l
+cM1BnzBe27hI87xX9eHNwSlDTVxnVr3WfRqLMmf0DkLcqKvgmDbcGNSenbRMPFkFVm1YDJpfghnM
+z7Rl8eBd3a4cmkemCdfPhx783uRKIapglFg1r+ie5APc6FPi5kNyqwj6RO6CJKEaN1yHRpOptRD3
+biNREXH9uYgZ41ku+X9xg4aEFgey2EFrLzXmkdPbtK/Zmm6Xga7kni/g69aRjG/jr4/wkZqmOyOm
+MBuNNY/Sq2qeuHJpMSYENkq56PJ92UBeQairv/FrcQuPHLHDqXxWLDvTjcFK62UxY44xPNUfQnpl
+fult/a6R2G6rBuaxWrC3eXDdmfDcCSp7+NK547J3qrv5np8UEEfzVWf7FXDcE3F6pbRJTQXB76cn
+DtrBJa8v4zdaKiy6i8o2AiC47EL1qYKWBlobVueIFFxnUNtTfX/wh8Zr4woeUyeTEylCktTdptxx
+vmoORIfbl6HFoU9mF7/t2xrcqnvSXINe9m0HO7l6xwwvFLuw2ghm32OvMUhhgSGqVzewVYW2AIMw
+LX6VzrjG4zyu1ZaIEVkzJHnMS5G8PiKxX1AjGjOYn+7PIV4I22TWzoGjrDNhZOWHtbX9r3Fw6HYt
+1na00onSQ6IpGwSXDD5ZBgfwFjhclCbvO8CgToZStTzYqom6XVTr4jBH0mesd3gTvHH8ablemW41
+aiizqlQnm5SAslHAYMyirs7FUC575F1V1T2L2PNqFeNdL36vfjrKVLzNWhndpruphYI9R/JcxmIj
+LicJUXyJn3uoEcimqPI9umPxOVZSb9mEsDF7ibSEKkBG8iIHeK9ZpiYG8DFzsGaFNNK4PNI12fmf
+LpXXek828AO0tRYV8aXGdSFYFBj5Wu61/H4gck9/otoUjyo/4w2ka1L5NYda1Y274SXw7FnBw6EN
+r+a0v/HZpYk2eHgFRSsGZIr0Hto/YC3HNzkuCZQd6OHQ9Y4rXejtgLtuox5M8AEYyEjHga6xh3TV
+8Z+BZNu4iN5CRwBPtHddW3pm3G1D26GKr58MOKGQd6HQBgZ6QvNV6ktjahqNeDIblrVSmVxM6A1t
+xGCeHBInOLK+QqfgGdBgkQ1xEJQRRQzXjy2q1lsugt6PkyTtUxKzuTKPN1Ay4NyZc1Iuj78gDFTP
+DqNUEhzp4YcWneWfvQSvGMwMx24K3dz+TMhCAGIp9eMN4YwNb4slqrE6AXlUNoFHS9ISXlqlveYd
+GQsE0/kbuFOayZFssHA8HFY6S3o7kjzWXPZ/nUqlTZbr+n2VA6q2M46GlgNP21DdFB136/vMz4KF
+LTJZ1bZAGqcmpYozJlBfyz/+s/CzW/1TxP9SZgkX7qxp0tqCsmscdcr1V8OoHULCybfBVSckIWXC
++x+XVA98t6lmBH6ugFslYbPcGy/yO0o/0T5A0PoFNCcqsFC5d3JICPxJ4cHRSrAO+dffqAEbrqPN
+yVPh46PZOyPksy82mC7DNBpZiycQMkYn3MFyHHJRwu/wSI25STXeW3jv1NYyVcOUKJD8xoCKUKB0
+rPyPfdHBmqi3bzA61EaaepN6U08aflowWJdxSdSC7hjiDyh4g9Guygsx6UTXUcm9tPZBF+6bHyDz
+0BfLPZM5g/puKlCelRaPBo6BRLBC5iUBuoKeHyI9dbRC3iH+n4DuveUgnA/sU/WUt96AwzlKHkv6
+ylbR8cJQ0tT8e0WFc3piQW+x192FqgpntRZB0Foy3g+JuNoquGuN94WfQmGn3GU9K634ehFkDgUn
+7r76Wd75yVSXfY6IsLpAzCzKNSY1pVyQrJAdo+3ghJoFOllGQTfor6ppF6+d104XbqHPBFAeq51P
+vIS8DUduCaObnMp6LXQG8Q0TCBjPkDoeQaXsDnABRMZ67MlWMEVq37FF8Z47SwuxO9Juk809yEwS
+wtKvSPmtsHIZUpy+sI5DR1ObIC1tr2mEyGKLmcL1PALgobJUbyL8i0euEap60CGWf2mP7M6aT5FV
+45jFfEY0OWAsX9eka2rwhAq4zh4mm8kOm2dMS4AXIa0qAi4SrFZRJxklfDtuKyVWbFGoXkIXhZxG
+G6cD6Xo4XTw0WBZVyKk4OL2iEsnzfBwLUDc2IMk5rd5HB2SlLVu0eq+QP+ShmyJNu9pDh1uQWbC4
+qgJZQR9jNB7eXroamDfN2MSz4IG3A4pNtBGSB0S4GX1wiPVQbNkrR4MQwSgh/EMGF4K24Q9F5hCA
+fxq7kmhpIdlElGVyHFEToGUfIkKMBNinlDBBLafWMmONc8XdsyGO1UJ6BR8972+uRRTZHr3XAOSZ
+NF2HXEI93KijoKBTzb+L/ngn9kQkMHluBsRbSGTbSyti2TV3RrdIyyLHEm+2b6rNOPYHCMFwmuGW
+CFe6cAREGCGpvg0Je/sLhK03qZVykzVOpt+bPqR+PwAJlp7nl/Fz1oGVy4h/33AFp41caFX3fwlU
+dcUzbaUJRfcAlorWGssmZWivMsPR8Negx6OJPRztk9sd+vLQ3csHxjRsUNFiXTfM8Ebx0NQmsJfj
+wYxStjvaRb8BppKKJU08jbMlYM4Xwu+vSMfjO2bDsY4AnYvYAWIWwDfIZryaBuOJYFTuVtycJXdm
+hCXk2LU/8BQBx1JNa+yWI7P5tynwJKfjCC9ya1SegvNZ1r0YomWWXFmPNVj8sLoIDlp3g3CIFDWM
+v7mBVTB491y9J1n29oc4znErrSvlospfW455XYAVIFPuYGasvnkaUXoDIeUDRbxBM+fF/RcKpd04
+u6mSuwQXjYxJtRF9yLIkSIUh5xwTZTkKZpFMH4HENhyFBbIifkBpYmA4VRxvsIQqnm/506uuS587
+HplTeX7OPeXW5RXkwiTXhQPoZlmpDD274h7tUfL/vcfz6aWYQJWid7drZJ4h+GAhIxvxugcKuxro
+eJSKtoVJTHgO5mMHyVvO9MlJVqiv5D0GtdithTo3ETKRW/aRfFtD1uFl7K51fYmxKe2QjvL8Ry9P
+JSvQlxyZa4rKE5+PnmyGWbClzwPyv6F1Cp6WHLdx8uZQKznB7lRBb17AlVGso9Fk7qJUwWruE0Gv
+rw0niNgjdkucBmrCby/pXKD105IzUx/gk0HcOh/1q4KsTUrgKhPHYFFYJ38EM4ulTGfgchPPB+79
+umWN+dvnCSE+0j8O0UrtkIeJK5S2sNcZWwUbdi4/Ktf6+xEuANa9QssOREjL+DLILmUW5hnaLB8y
+q647Dt6kBtdZjxOgr4SfCvVmaqUciPC6jFst70gMaryapbgz6DdUIKkXwVid/kxlBQxNu/Ms/bR6
+GcClkwnchkNrLyOM5liPxHv8NYg+F1yGJv9t4Tu0xS81Xr60fJP7Y598/tW6KM8vYjBP/SJBpW/L
+5XkqWtcd65V6cthfYt39SWMzk4zG6st5MDPt7QE2Xg6ugTeHMckWtRA2WEScqiIw4OLlx0MBzfSf
+bjk9MId7StETzskQXe3AU9JMfu6JbAR6ZREWkyrtziAXB0icpG1XvXeSbam/T9mcmgI+hM05WBIv
+UccWso32ggXk3SaGoksnN86XlSCjsnnlJ38AD3NPL5OCvh1JT4QW1WfWhAydoTxFEnH/zT9TnPK/
+0k0BDv+fULTCJFFP4272immw5LvoimFMrgIJqPu28E0/hwrBVw5UU9MQxo2pDFJTWd7Smj93JOHp
+kYP1KOVnMCtyyqPcelKove0j/1lD5CMjXunHYAPunOEFPB6iZTiwpcOQQX3CoTKXEh4RYcztD1LA
+85JVcQS3mHWzlh5bsoWcngLVXIyGNGheJFZPSNdip7Jl+vYEst2gPFFCqagc+ImWvxeRDCm/fcpg
+s99HS673r6U681i50bLsp3kQDM9C29NYph6Dy9FRB1L/NeDN/b5MFQF4CS/CqIFdh9RWqMcyvkmc
+AO1UNvy9kXXrkn6BiAScFlT+LhVSsxoXp8AZtNpkv31dck7du9j8+563ENHdLH78ql+Xke1B3r8q
+2pHkUNU9SM+v80vH5Ib8iNe8n36XtXtY9HY78FhPPMklOg5n57obyIvRpAC56ZEvj7OQAXbVQrNc
+nkh7Z4FQ0bOohOvwsI3P9awqAZjQbsk0mPX5Q3glnx2SV0rRvv4XyYHHIIsJqzs0UNmVt/PLlkqP
+aUDnBRwm0IvtJwntgbHvaUKE3OCgq3H4lz9QbUYdpRTQMEne355NPhQbto02kCrNYfHhTGtVU6Nz
+XCtDVW9yF32PyBS4ckX1LiJ3MMRoMQhLFMQGgK5Ah5WrXinaSCvgRvs5X1EzUjKJrY9pMM2a1/KE
+Xm7HlfAJ2gZqSKiWhM9o/r4FoyxQY+KEDvL5bwqLM6BxFJJAUPTeyMu6idIBQye/SKGF6UDQ8tT5
+6bgqmL2Q21AN6ylJV9cxtyMzJUAEFE8jLJa8pEchhAkctXEPQHOKYbDkxaEelISrOwojYBnnQRfX
+XxBa8Qv3MS7VogHmNoA0+akuIMEvJ5iH7i+j/uepLW2UPof+lUbzRW3dawOJzxwexpZ6SShfAEha
+zP451cXelxiDdzMl0237U8JWpRdIRsGqt9MyeJ3tSXINuH2S9Qn0w/lChYc2jyM7ceCXycUlISE4
+0j2bKfTbb+EshSsFg6d5j1cBFnOupoqEdyFKWBP0EuaABuxK5ZdfyT6PweEXF62MuOcCN6wqgadt
+qdpWGaI1GMc291diQ/7fbHOGVBH2l3VQEljbqvSIjNQsr3JqiFpfsVumaxZKL8gbeiHIO3a44giD
+lVvqQMG9pyeSieq8ml5LR4616ymiCnQHvPfe6+rJesOvOxXOaW1EesnjiQTQFpd/ANExh+awbY4w
+9jybMQjm+1dJ8L9mloofr+zc6hsjFEE7znM6d7hVgAMj8KJDBxRfSAuxfW3fh0GBkPc3gi6ZDDu5
+5xCMS9JI6tl6gAiGM+Hq2pY0MlMGsDJzYvivoeJQHFitGZGNZK2Klq3OCeTGW/oa5mdq3gv6Czir
+FXkkfyphNfecEjimwqRcUV3AOuI0LJIUjyUemH24cMbA5eip1M+AnvRhpVU8RiuX0sD0pHb5sqVh
+3b9qaviBcI6AGo5irMvpYxRnc3ya8SrJWPZNmNLaSZU33lytcBKazRcpGS0MSPcfKYX++3yq1Bj9
+QIc1TqnE2qDXrWlQVuolxZkllXHWHr6mKALLeQBDxDQjj52ZoO9rMvdmzNHQbW3MRe1zypZG0w2N
+1xBIO8y6537woTRRjLj0ZtBQvGdVwQixI+Fdkmy5geHV3eZaNX9l738a/C7QPcd1/4KL/sngAMHV
+uFSJrhuImVaC0iPQuAnaImmn6NPi0+6C5NAshF7sPNptsjmHNeocNysXrBdqmAtrxZIP3AQTPaTe
+LNNIZAwDh42RcAqsu0PhwDZ6L50LHFFwn7YAh2goCqaTRlAYKCAfGTF+j4u7x0g/f/R5VKzSKCAZ
+VmhAIDoDUg6xAJpUagxzPXPNIog6rLRpZuouE8h37kQvq1LFo2B+Rd1UNq8dm8ZPRi41eVs9R3jY
+JJsJbfeEc2zLIbonBi6EJMrhK3xNRDopYg7lG/rsrQTb8PWggz5JwbkpAmwTvRVaQ/8XtVgcvxZM
+yx3n23S8+9ILnZopbJvbKaaiFthp/bNFrAU9To+1ElkrERiCs1qlu4ayNobcK+EKct8WyJJ62Wbi
+ytv4AFV8O/KcLlVTnIPG53P5gESP2ob7M3Re66jUrjGsHE/62g8JMg7KQu2HoT2yTEvyCt9Uukei
+UI02Uo2cAw7YCpa+XETzir9whWZP/bz7OqdDnCPhSY3E+1inGOYeDynpYCbLwtEZ2HDuQEnZtSFb
+77/Xv7o2GCOYGgIaHUuaP/KRSNXqyrdmlU7gew432OeUUARRYILgXW3YqjFvLD7VrzkHq16gmcgY
+Mk442vSuGLDnMPuJ+8Z1U2xXODUyeDCKGkIBF8Ezxxo+19r1cdzyp6+a+OPTaeVlOA1CwTc+et8K
+voX9djTM/hTM5OMM9/i/xjij2GAdz3wJOGHLeaisVhUPhM6Y+tm9ilHrwxRVSTOk9sqK3cEbkFTz
+GmJG4EKzTJ0XVo/xTbu6JkQN0fT0YpQVym7OhRsoIWvtPUwZZvg44lbcOwfON8ab5BEwdAtTrC1Z
+5p7i0qYFB+hjunCl2r8Ucww1+OM5RyMRN5m4Ki4tfejpW7hQ0zS5v1iE2nQBGZwpmQbclfOzsX8x
+nw3FvOBxKR0c2E+DQYv9dAIvlXcCN9Qs+l72l1bvxZnPHgNplCq8LGWMZLEytB4IMqAl8rbXmiZ3
+fqrAQ5S0d6EwqAt6SgVSAmbhul3xQjW1+FRTfv/akqvPyk+XIkPgX8AOifSEsmWfekK//FFSmMCf
+8v+qDeQUPiv3fYMoD8mIlPf2RnpZSMKm2e21DIB1ktBDQZmsbMx0+DKMyqnR+qz9CfdOs/KL1G4q
+XE5jSc80Zhm2UjzUwqHY3pVRGzkj7gVbFOrNaF/uRve99YovfF4PCL9khhHYFyTtkZwkcjwBLbl0
+XqU9BDK1G5ZjBF3rfCeHjwIry8VQnOezuN0tDymjIw1Qt3qLo31BXOLIh2Wwgs1xeJbV0GYM8JWK
+9w8WBSG4bMg7tGw2c5dfJenaA98y4vxcOsRmuZ3PA+cpL4qwNrRfGQT3oTPT5UaXjSC8TB/ww+I6
+lPUCuSu9wCzeq4nfonT14uUqTUa+SntbGzXMPJrGM6IyBktPmO6gyAOKNYEivtY4W04OiJDwOkVa
+ChCYJc++xb8Nf1waQidJNRCoc4p5JFIa/jZE6keYjPLLEijIE+DxE0RhxXq2hitMts10b+DAUe/F
+Jm1b3UNd+ZZ/UJLlnup4cU1hsjpviYyCdtqgA0NtFAQ4B5SrB8QbxOYljH8Y3cdcSYNEGqABRsMc
+RRk+kMdbGfNLFMGuerHWbtlJGi2GxDvyeAJdPzaPMEJxWyfWDPCOcmRMhj4MM9/p/9BBFpaE2Kxu
+Oij+8swRhWQj28dbY/XFgDCcjctLxto9QfJPAqftBHQyhiV7bQsq/O2LR+TCJ+Y/OLr4nyfbanM5
+O9kW5GhFjupX31jjuS75LVg8KtjD9xe3+UN7oZi5s8BQl7R8Wg1ChgcWohKm4741SRMo13MpwBl5
+bjHPKcVm4leN+OfdBAM2mWVXTpcxjvC3yRSbiWIaDOF2L3IJB1ylYpkTbQIcOAzxoLOyXyMzdcTk
+/Bd0sv2wunxz7w9foDb+szThUyNHNomUlplGOceiETGfshkKfABN4fcV/6oTetxEbU+5d45QEPRj
+XmIvNnQwBycC97kRCC+dg96fHo6JCBk1mHp6MIagBtVFLDXPPiC9x18AWqE7t47AOVNCye9GqjBG
+mCHpgoRoOS53g/SPeatVoCTv6GyJEGLbNZ1wiBZzDOeED4SlGXFmdr1wmIrveLQZzrXvUl8395Vp
+bSwun4CIgp8CzuId188WTlaL3FmOcqYALO33wuGATZtsBZIAkqZeAGRsndU+RkQJzO5QUKhT2UUH
+iyuSvjh6/JWp8FAKYhM7EMFL4ReOALfxLpUAlVZCP19BaZ9w6Qx+ARfqlj4JQN5YY7HAX/cnDEio
+fNz8JFXEi2rKP77IBWubIygA82kdGuibIb1uSC63YRJtdfKMATtyUfVD3MFsyDLVd4oikWKZBh/h
+d/o4LHLUAw4Xr92ey9d9DpwJca46qKL3x4MEyxupDGihVL5hvwOmayyVRGYSTzIsPXuWDsRzy9oJ
+B8v9W4d7W4ul6+RFChrq9w5u24oR9En52RCLeVIBAxvA6YUrc2tkLXKycfwNruGTWaK2p1Baj99S
+/vA29n9FZ/PWHhrBVDoPpZPSoVA9ndJogaPkBQF3Tlj6fpQxGkaP3zPat0stVncJF31+EDQk4N8E
+DQGs2l5iRO7zSY5vzJoUkSat1XF7+H5r/8vyiByztBy0U2NydyGE/FA4Z69g92bqLJTgq5BNjP6U
+CO1ZNQx9MmoeG5tkCJ1j/c/edikTuhmNosvg6QUYLxiWnYUoedFYPvvvxRPo9U59fRc0UJmH/RT0
+juPpFpZUwNOv1ZrGdf1pvunKqclJUCceFf5ic7ILcNYNcPZwtjELeEG68f5fzFA3ZwgC6ATi//su
+Iw5qY/LKxgtAhUC4Ezswt2ZbeiXJ4Dy7O3rrZnbmypqJ/vCArHxzLxjlol0iaq8p/Aj78flszWuk
+KVBr3PRsQuCglBW0if77bKN+dks2tAlwlYkvKOsfR7nOnR3bF7kyxVSW6lTdmxexUz5GD4TpXYfz
+d5UT0Ji8HeTufsfeYUFpGv0o+8qDyr7Nv61rI4b9EdC0mU6ykaANxH7OJzC31sb5ZM9T7iRnCYZA
+hNpN6EwS/73tK/ZAJFl400dnPpWjLYaWBWYxYb+AxZABQrpHdI2D0bHacu9julaJv41N6OB0IbyC
+XI+ehrTfrqn+KD7aziosdSt+QH8pax+OWJYXdo3bZT2a+tx9cVYwrBnMa+1iZBhXS5cxfgT564pA
+OW1ZAI1tRJwOlQUgY5DTRwOYtwQM3OxPvbFB8XQP0yYhMg5rhYRBK0Q1T5o4tft8QiTOuGBC58ow
+hA9fMgu1YwnJArJ5ZGVSKpKBypZlC22NFGfDjV6p6220BhFLIMnCyds0ISB+GEJPeSU2t3td7sZN
+ja7xege1LUmjDp5ndADHqMwwljBZ79+u4mINInteisgKHdTkqr8G4tn0Vnv5JL8gcjDLC9QVXnW6
++u0EdYTpf8YGQ7mSYEimFh9Sz95FCiGmCdwIxTOPRAc7qqpRiKHlyECCXLfMOeMax36WtuEEDgae
+fOPNNMqmIs2R3beuo+Zd6rdmuIkqz1FVwyY75jSyW6Z89KpPvi86JO+D/FpL3+DSuAalBg7/nDZf
+kO0O2pZRyid+ym+8J5janWayLyfgWGWqwpoNYwvc7QYCTpKV+ZdnKXLwRSc5mjE5zc2ldLYtKCDI
+PzkBJgebBdGo/XGiqHpOMRw99F2xaqtWIONvDlLtrGc2hAPX1vuupvnqezbcw9eyq2KneArBKMQ4
+jCz2/GUvr6SLh1fQRQPgyL0L8mHzZ13FUACs0aKniSDynJ9jIR/fp/xgQW+svKKbV4lYnz9YmfYo
+dOwncZ1r2OvI0rfjevYs8u9A/02xMCeCHujwsIPBvDOTXteLosR/L52/bfXJn+munqnsvju2rtlv
+4pdFV1L3sSCXIUjZcjBwZdcJ/b7Mkp4OlYShB3ayt31Hno9y/S+7WwjbzxvNqUMMjIQxMQ7rMWI6
+M0bOY2K2NrBvCCnuw9dAbiHr/g7VRLKUCYZLrYMKcV555KIUri4r22O3hYcHRVxT1ZmVWRdh0bt1
+PGCoRGbLsBNXDYi5sTy+Ez5mILOXSwIOhy/NkZbC22cXs9yBtDAKIYqmewegRdx3CkkXkSNynM0A
+EmG5FpZXDeg/EWFUIffQqJ0RoSIx8LCmTNVga3sicxCdKmtT5A3IK3Cl9pitaPYYw3vt8hBz5bXQ
+CZyg4OZ7W2MKII0UZfbd8b0D6SmZfGVjUBKr8io/zUflVyVNQz6ELEq7HpZ6GSxWKX7lSkZDZQ1n
+Vp1rL2YKwtNS/OD7GDGCW4ZiuIhmUBaGm/YGA0NJOcPY+xrByrSo+qymmsb2Xm3GM0Z7yWgVcQNy
+gvXJ/h5qOWhahlmVyihQL645UTkBhV526u9jpECTXboAnOkgGs/wZ3cNL5qqkPAt/cgcI++/cdeW
+L9Bn7S7Ds7xv5M1uREn5VhTAj0x7fKm+spLIbMYTLN6GMS2kPiGJ2SDGZarK6VfDZIcwVOVxWsBS
+Vh7cEFeYBAWbJTzSfwIflWkXnTNETn5a5ruSHGoqal810KmQYeN4jTiOR82nY0+LYBOdSGjEUQ3C
+QG+WTrs3jhhDh+hXGxGSJtHJPGPFAliag6ShcvZJKL4wpOFshtxgyMKndanFnwGFZ5UmVDcmJ3ec
+AK3YzD/cKtMgS3XXPWc1yaWZXqMPSj5GAXPjo4lt2jImudcvkXAEaHxbDC+r8lvbRSCs69zdvA8t
+HJ+aAXMGIERHMqiDyeBKjqap6wGJp2hzLWTfTpyj0HcC0tKP206PjBNyDo61WfNcudtuZ9zi204n
+eDp/8wF46ATPJoVlL+LmcrfGNSns2323LR05oGazLyfp+khsvrJqN2fXZU1WRHGCpvvTGYz8yJih
+gZiZXsUnjEtFhnjY1yayKUipLWbuPg/cwJOVZaZst2bJBoSzVq4gVImaAk8irl46FXDI+tBUWYW/
+yZF5Heb6Xw+c2d7n3FCOv8zyVGQzWbwSsh0zeZwfvIxMFdDpPYVcWaegXzZwlJivfER+U6d/JFSf
+Z23DdwPdaxx7P1N4wTxLreswXfVCrxBEuaoZDHejFd8tK6d85e1xO9s6CWgnoMFYDMV0vIaZQnls
+qyX/dlmy/8kmF5BZ03gxslrewCZsTeUnk9bI/oprLF9X9vlq/mYgGJ9n0BH9TGtXW0yCSN40NCdZ
+n981svP2DNAbQwGG8j2VVcpLddVxIU8bgnYhZlQw5NQm3l7kEgDcrT0bjfWqIwjWaTqFKpbcKf55
+w+IqenyeRKMtTNn4PF5rGx/D4PXvwEHXzhlamGCIfaX53I/nQI4fB5Lcf8XFRZRyvsAqbha0GNjj
+Gl1rBkAg3OF2BC+AI7vVb5Tik6xRFH7IlVbX1/+v571yiozXKtJe32b1hUdbcVBAYmJ6xatOUC7I
+YgBzIb69DKRDVAFpUpCY8D7ciss9SLPIVnt6R+hXANF6KV2HgESepbsOIKAQiwMzb3BoLkYis2xt
+ulxVGbzc8AAWlW8XEx9FaRfStdbQU4IiTqfQla3ZnwDfPEwP808fafztlIj8PRPD+mnLZo3+0Hft
+fNt2DmYM1EksGvIGq1T2E26aNfVQtPz97TWORAAtRxMZa8UJRCuDEDg7QWHT0H0VJEoAnKXP018r
+RHeE5AxtCj5z7wO0mBqWF7NVRLv/a1eNbAkEn9MX5jAA+RyMHrHJGhBAGADvfhIj3ieFifxVpkR3
+kLv2nCKqjfLVt7pGfHTU/6/GpKXVhXmqwHwsoY6k/ELCISNiqAt8Cin0iGne9I/BVEJ37X1OnYhG
+EG7Tn3lbWcnnnzfoo2ENrNCgDVkViaXxMbVpMPIrHeGkLvZjNNBiVm0/emj+BmwiD3U0WmBDXRzU
+HkXHhEuyqCV/JqfGt1iMG7YtU2g8auMIbBH+GGY4YlGaxYTUMWjA4gNcRKOi0vckgtaDZL9U2P2Y
+g5ObmZogEttjxVXmn80HZk9UODCrKilCixM0wv2Xnp7Mvi1uGn+wC/h+rkr2yoi2Q1CIz4+IxuBr
+LmEPUc3HKZyN9cHMGttu/c4ab37V0qT//nUmhJvr8nlc7gf+ChACWCeNA6XUC5jknaPgTWsUfAUO
+OxZSspRSP/SjaY+qFGX/3JR4vWk8KVcrBwnJcGgyb12hIkHXYSb5PM2eh5NUQNsFl8YojthEku5P
+I7b6nVhiczeCRu1K9RKj253H+XOXRWHMmbh53IwzHaQZQwOfHSrmknB91hSgCIqZsOhKanoghLNb
+/fhO4Zp0fsZmXUzOvlEMEVElO9BhuhzMl0wvZnCVE32MWxgE37is7SBGTyjgJRVjMj/NhW+5Cfx5
+TVNPjuRY7vHTQf/8os8z/DwZZKEjxlAKsc9x19JPxs0M3uKRufH3b9HSEOVr15xdc96kLbuWqCqt
+lUEkGrHF97/SFBF3A/LJbxAyWN085G8i24/RGIicge+VGKhSyJsz0GDx5bO8oaGLQj+Vcw/97DUL
+g+OCQHRhmbfVELssFWCXs3MxkbG8W4zpLF0Y9aqy2yqB6XVHhfCueqrYEua+NFNpDakY+D6Gws+G
+VuzHlOZnm/QpgAwWm6hpKo9/pSHixa/romPFRhvPUA+/yFJqeX58Vb8OsqTzVqh+3oLbwAX6CFTV
+P415v7LNfuUsvlPhr9busPQS653b0LBg4pPvJ8uoSP293fuLTwk0aDwYxoFlcy38vaNl7MdhskhL
+lfEVitrzd/mlNRdKwscWLIC8AHKeUlxz7rwLma2niwfPQB25iiypALebqyZuP/GVSaNRNeRj5rRa
+H7gZ+S/sQ5y8z5XKGy3sGAjPzGa0Uuzxt89AtXUpzxcjCN95GuBUKDWJHTFHioSjExNOLuk4cuYr
+KFcZiJl2C3jqYpolSdlkwMSulFxuqs++8hNvwjHwZ6cb4Tz9zmyPF1gnZ9XOLAMwdOsTOJ/oS8pP
+kCUyF+ytfDYoSWmSWQNK84qlEILLk6jz+z0icFdy80feVS0pS1hX13Q9X0lFvqtYrP6ik253leRI
+MEWJGwRexF0jmx1aVRl9C/ee6jz1mcGvz+hu+yIWDW/nuZkBkMahpMAmp4xwOfQ41L58gS3AJC8z
+LKwVE8wzfVjsWx0V5uROUyG8ot8OA8nIk9RdlwnX3c2PgO8Jkr/aIq+PQPhljgyN70+UunSANXN8
+S2SNH9Xfo9+xsDFdeNss2Z3Es6iKsUCwsfLdIPeH6AqeB9ncU6K3UoqH5gIhpWqxS6IYcK2Q2ib8
+gvp5WYP1e2vPNpya81AYsYgfv4yG2fy6NtzqpbcZfffy7Fdd+IK8j1Q6NhR/ajkTQHkYeMqJwBqp
+IJRjnAPwQnXwzxA7mK7ekhUI9lGVakSHlKdiNFbJ2MXufrQ12DGAPK8cX3HLWvFDg0vaiHrFbzY8
+dzHJC8IgwO9hFTDBLZS+U0SCrQpKlZuWjgG5Jj8LVWgJsORp4PGx5UPs3HdJ7AQ2896qo1QcEH7E
+HI3ekkQPJJ+OthtUSuHE267QOdeqRxMKzxkqXQ2z13EcUwwho4aBE1TxRaDCrtItgzGOL9pebopb
+XfvUJSPwoQo3OiWJSVZtHxm33862HEiPHKAhnD0cmboCb2uoFDLgGOupkIAgyATzUcN2qCmIlvj2
+SYr+V0wLwasNDSyZTT+/F4CsDB5oDb6eMPPwYPzAOd801vtpNZ7Nmcubht6rAYpTi21owrZ8MMXJ
+pxWT549jlCpZeDP6n4vztdxbHHvMin105a+9ZAVk+Xky1KX3213RcPMfq7e64JZsKEO7Am+1tyZm
+oX5NYxrfjj7g25mTdIpy4zq0CPy3Ey2VSfpFqejCMVkggULXYVTpV1KZTsBWs3B5liQMmcl7e+uQ
+XHvv8MszWuHPNEaagCxuUnx4BmeerNXSOjBaKnkEzZjd5tJJkyeVbTYF6L3IJytAoLvJjBhWydAR
+8WlmRIxcLhTS/oAdS+MPiEMIrdMgkrWtVIVWX2j5C/Q0YbBrfiNq6pqW+NiqVo4jcxWNeISVc3jo
+voZ2BDgJWx6dR0EryxQHtq28J/YpVfImFbvQnhZMB1yoBx3gvG1Y7CrXfLsoarlWuoqJXX4jX4zo
+CM7R1z8ztsaVwY21spKH64Hte6tDq6fR2wE9lkmbEKthxPVmRQTvQQpdB/hn5b8bxDyvoq0uNq8x
+5WMirrgvAgoz10jbk1J4mVAjXZvZf3X1+2jCJ/uJfPQ2eMHshl3LszOI8EJNGwstrlK2ZoHUccAM
+yWVLubb3NrQnQ9oKzkB7RmafPjKuX5pscdXzwDsSFH46MMyysaLYrZBp6ne2cGvZPpiCMKp/Hx6a
+g6TPNuzshLkQ0KlCml54pZeAZ5NnxnJUCXh33P/r14xH+lw+2aR6zDxUpM1Pe5JcVu8Al/oDyw8X
+r86cS5AVoW5Z1SjuBevO4dkHuJh9y7yP+9LzH+D27o86UrWumexIq+v62veP8878Q9TeBD4mzIQT
+pxzu8B4nsx2hXLYZ3kCcRF5A0SMrfvkpUvw0tv5ZLzbGvR5NSHc36Hvc1A/S7PnAJ9C5PNQ9RtN1
+EKI1ReQYSyvhuTq3SVssBGUhsi0vPfFinWpbryK2tzKLE4nhR2pgE44EGf6mf9Ps4yAdU5wciDs8
+ZfDylugMqKxYQvik1KBxElL44LRQ0K9y4EKDLRICnFhpybX+fCe9IUi2q24slIwUILlsNqnaHXV7
+cT1bPdESDc0OfjsbUHNKeRE3DL1j80SPU9kLoao0bOIoR8H6kv3EfH8e5WXedisX/tmvIIoZR0tf
+MTIOq7T2jLVH6vNdKFKfCMXHQ3ka/t5WrajAPoaQ+F98MzvVg7ZoadJ1KUWaqit5uAYb9RGSHZSI
+4uMvlnspuShPa4HIzeBzdMhmqK/0+k6c386oQKSYJVqlVC/WJNRnJ5B8kCWXqfijlwrAedsS4A0D
+ZH7pUunOJL0OPS4+CLRoCkW855nT+nxWVe0Hanwpp6bCmUQ32i71jRioVXYtpmfNTHQpsCvHxTw8
+HGVg27sKTaTyf+kjwU9rAKHy3oPrGEzqXwRLXotIEMxM8gwYIwR5XtgIuRolnCtx0eZpvlrVuV2w
+KDRxT3g12wqAAPIOit7FE7XqvsiGbaAv7EtwCSimCN+vAeBoRTs8MLYhIbUhHFizRvZjNksM+GG7
+FFyARBOXojRAtehwMZxLUnLHZ7QbvyOAiBCWU3zZXnNtbkOT+10eOFrEU0i8KR0BUlqx3Ylm2rsb
+jsGFjGY5HTMYoAvcYvNK+6cMZzq1Xq9qFYOTrqzc2t2NIi9q8aJQArryP6w9EjkRMKn7TQ0MQwYQ
++CG+BzQjXdts3Fl+gLgIWzTcs2U+wrNObNlY5nE9ejJF/ICBhO3HecAK4bUFkx4Sd7jOcT/wmBaM
+sh+nZwtkx60zkQ1LqJejB8cuxfUSFAMfylEyyItH01bD5jDj8uWxkWJMpn4maW68DVW7Vf0HqQI/
+mE9AgI6AAf2HW/m3UYI8v0XmIMqAE3TalOCTHzi3PRZznz7wkE4pXqOIFcs/rnutsbUITixEFfeN
+543kxR7KXpZmPOqqFNaNxx0Q1r0FRoQbsgR6a6TM+qka2Zvu7yLaE3Hd9EcRiNJuf7oKnzV2+I6g
+q5iIK6q8fOluFgPhy+E3cToy2Vkv+z3AkgU6KsQRy/oYQxinLzauXCg631IJkxbkNIseUPopmdbQ
+ArjIQU/ATl/JaiTsuutAAMCKkRWqfntWGd1tTGdnmp4RDhu3h/Fl+zspPmK5IKrsFwZwMtJkcSiA
+bAijgUrOGbCSBDYXKen7Ikkme2R9iDbrumPhh2hL7LWyHe42V8muLVqUo1b92zNPVrttmGg/1ttN
+SzQaK0l2dC2JcLXa/JlNdSauKiaZ/ptG5P1Z6YTDpvgZ9LGOFLCOyKRcbnJpxPhtrsFDrgvvvjMT
+wAGg43gp/QN/v47nBjb62nZq4Xj3wJ1egFaWUFj1BJTpbS5UXfKnp3lmf2/fVqPG35wgYNwk5g8L
+Hgg97pXQuOLr6/Pgchz5I+B95L6i8T/mE2DBUTJe3yd99BVydp2/UUHEP1lBhXNp1Fn8oCb5GxO4
+HeuvKxd4EL3sbleMdPws9VQ5ouTLafYtdEzNn3uN/jy5qbFPk8dO27PdSgsKWmMSRxen8NwRzGp+
+Ih86evEQixeXNRZjdBbUrKQvV0F2ZmNGcWsyr7JXBeW7lcCbczcSmY2e5fad4UhVKxMesmElmjDG
+37XX9HdcVrdPGE0IKsB3Ac4yADwwvbhm3l73Ekv4zEsBVLp49aUPXE6LOr5OFmpev1jxtM1kabFw
+mobF8oOE10jecHpTPXLC3/hK1ESsXn7ppCh42v3i28gIEOIPixL8rtMQv4TwTvp6mhGpr4lJ91A7
+28nPTEuJw/YpDuPdaM7FwzHtsDTTAghuGTDmb/o6EO4wJdvlOsVyKlBXe79xHKqryV6l3hSmoCfE
+tAD+kZ5qRPbF+bLdzhBam48t41pA4dYX6uANuiTLspL8wXlgsaK1W20qvRv32sIlDATMr71t5+ZP
+/dACXg1vHh75vW6BmiVXg9r8J5DJ5omdAuZZ1rkfwKeDMevIrp+gTQdfsZyjNA/x45/opnZZEsHR
+0/XIrDvBvwFL9WNfZsziHCueTQzDXQBUGlC9JL9EouoM4LI5/tCXao3Z72FIvACAkTCD1LyPw/K/
+YhY/4+Cb6jLw5lh4vrPIztBA1a1qP27l06wUyDRI+VYdK/gwULbTP/6/xYMnN+pZxeMhuRZe9Bs+
+e/W4AJhgwMlwpEm8YJIixoofUPKnc4Khv7zobxeBKWwl/gnw+70hOl6M6Se5vx8xoEqvTKZLD+ZI
+UzRQh9dFTCD/QXT6b+WuFYRyYb453lNjmvMBz5jM4G42W6A9+cbmsEygtdMDVCas9paQti+3uQb4
+DzVVQyan09i0dXTXvFc3ACtIexUnnVXrfu65SB0/aqgKc2bbO/KQJupYraVf5zNv5HJtzwm770vU
+exfkZUT2bG//zddJhfcsDW5xXYGUQztk7kPG4XJ1vKRl1CFjqCeJRtKpLWDw/YqpXxy1vYA4OIII
+Oz+BExh7hramuE/QxYtremh2YraB9Qi40Z/gM2dR8DnJg9QsfKgLXXMm5zrS8WFTWezv22JpAted
+qAqcH5czfdZFMjlziEs4vzolAyDCxo1oFKIvm+ybcXVcKSebf3Qw6A05mHoT14UuTpJM3B2T3sGc
+TH2TkUkbfeg+xmJWtad5+FIinLDZ2WWaMP2NATk2AFRFH+6wcdhIGhCH052QaEYYlWOaxhUN5/MI
+h71hRMwXWDlwaSJ0Y6tQy2aE0c4+pR3h5y39xZItAxmHuBrYIpbHmxZAOIKFKU3nfOxlFLtcwheo
+Ij5jVcKg00Pk64OW9rHk2hMQTenxHrZdszJT1fMXY8jXJU0eeXOWFJRzBzV0NJS/t6KufpsAcC8m
+CpWGUQ1zX84o3ndRk2JL9X/yV7209BmySrD8IaJoUlW66IVDF1ghbDITUHZHB9xQsh+Lh0G31JIQ
+pfLxovdhPHY/uFSH19+kp4gEllhcp2RbziXwWuL/YtZUkPg2d2zq2hxnOIQzrqP0iQNsMDyRLtiL
+K8JSs8/gESyVubAxnKB1Hs6dCbP00CA0RRV3Vc39Zt8DqerIZqQ4pMmcLuZ5+n33hoxG0R9EQelL
+E9W37xTSHG0shpytzv4/bI94s7Udrmiku1+qOQUabu8OitWu/9KgBiVI+LC3yTpgVHlqeAVmCxI4
+6dngkGaYxZFupmMeyZqkWfwdCvdRwT+7G2bIkayVpWd4EBsn79/z0UT5KgOcLKNhCnGwa0bdKGeA
+Q0TKfyj83NTYVykibHVEs6oB4rjtKsVl1EQr2V2CN4ptblHUAgs387rZpaMrhxAknBjxUo7s1Ids
+cJ1R50Zxbo2A2RtJTYMD13oVusRqWoNWiZ5YvR/qs81ljXYY5+D3amHekmueOx0pvIc5IUptvPTI
+NPq1DJyOJ6E/uQP4ftXG3CeVaU57IfJegkBicf1Jl8Bu/e4mxdDCCc+O/78dkQHxG4BAeI39FB+o
+mULzFD1YHIX0gRALQeebrz9BkTg+M6gnec4Z6TNeCbtukDObtHYk/2fDGisIMRNX2xm+aZzYMbH6
+iSvpS+6zLJUeuFYncdoNkTujEv5TTKxGDGovOr2PXPCENKgXxxcTPb+WX3VQK3M3iMDBnAoKKymM
+pTIL2rlHRAqXwZ838MT+UzbMMeGhf8YN402UCp1cId6yeatTC+sf4Kjbx2ZUEq4MdI4TCppmNwhY
+24FgoelQUjuuQn/RPozBs2BN8VRwYJP2hTgXYMhTMdiskEh2y60NfxrHhU19n2mYyIAj4hX8BtdC
+ifFEaXbzcxQ2J+52ciP5BMMFMPJvo9URePAP6p9QHh0TGrwhx9MeCVOEuXcgCyJehk3YXJbjfwuc
+azgRr+6Z1wYsQqSayiq2do97g4ldi3Jxucdlhch5fH54Q4+J1pDtScKBr7iKX8JuLInFwo/Mr6lI
+qeR45H58k2W3vwj5xZ47zQE4CSrFZBRl4LO+YQB0UdUi0+iTa5XKhtVOWQg2WjXtOu/7T/d0rgYg
+E8AkCkdBt5wdFzxLdvcvjeYgIZPTocXi4IyD3pg+lls904cbS7anClNeS9LxKeFDSharPH/VRoE6
+TRJ7BQuRZraa7RKL0rAXW5NT9VPAyEanRKK2tzQLixWFC6GR7HckdrUXrpJQrl7pB7CJwEIxPx/X
+DYSG9typ4z7XXm6AiOnyMdpMt4EShyi5WUXzovZEOONn5tzoFG7VXUbDenC77Fz6qvrFyNeVpVxX
+d2e3x9FvY32grcrwb43CI0HJsSUSYnwpxg5qK1jLg26thCpjmAqO1GLTrW0b2ycObAD+ZmylpIrY
+TouTmz+1d4HYSzIy3Z7WJceUnDBE4Q2rVywuGolazk8zGwiO6SEsjcltNKIOsiFbUraLJ6XsjNsU
+IDTz7N+z4TifTRZEMVh2E9H7IXsKC+Txo0S69uUnGzqMAzc51w/HMV1H5igAPWPF493+2d/+mjnf
+5fDzCDQhTlnLcnRP34HDeSggLzqJGoTu35Rubtc3I91Niea3cidI+LzBPkHPNNKdBnTEqI867dQQ
+G3gx08XsPAh14vkq48nwE/W4S4ODmrcBkftg2sM5osubj2+RRIPLVLSXgs6Vttc+I85Hcst7YiOL
+jghxLvYGh5wiWixfDDILQkRG5dsveZnD7vC/6sgeXxvNy+EGEFvtOE0t+1IgN661nL4B/JO9y3ks
+QevEDddIuqrrA9CIVWVhNoYKLOo1zolQHL4d8Bi5iwsHCOyoA7mv4zA6RJGnJaFi7X5UQTOT9YXo
+kbvT06PAfSgjc3Zc85DO30poLz1p0NnHr20bTHXOS59I7ybCFixMhBp+fs4jIzjstqEAYu9fJGB6
+th1Ej6YQH9VkOz4xcWXzyEsKhiCjVbyo1zqSkzVfNPCtSkjlkEM6dntiYVGBRjEVIqX0Wg40Rf3Y
+w0l8m9JdjdzKdH17Fees0w1SK/Zam1WXIZ8xWB7yFsyYHyZMP/bAW/zOt3+iDtANgKCME1C/sgmW
+CQDuODQN+tAdkIKP9KqWfHgAYlDNnGIvaiFRpxzpZGEYv+c1mCKPYQ8I1n1z68gOQ8O/QLNzypTr
+MUDjtu3pMEpZ0MgVEUdc2YggF4oenN7SNerKY3zE7FWDfYIH2fo2znHL8RXcvUjIt+1avWTB48ST
+uW4R72Nnxq7rbcTwky9PMpx7mgIdPaVPGxJ40wttySDOvCCZ2MeZQI6TYssNzilKL2QXYzHNuU01
+To9kI7eAvsD+T2pUhsryrwxwGa2Bo9fwjcjN5XWXOSvLkKyQPuij+9LhK943EjDFLaLaMoPC7llD
+RyswsRu1hpn3WPTQYgHcypQXqkvyj1AzKe9jzyznI0qq2DfM547kOM6/vyC83PYgO2DR9TXpmLDk
+5DU5iFkpJ3IUYXlPFKDit9XAAfRymUgdmG2zzmRROkvGqlkBFAyT+NV9rursmR1kIkOU5kUWuY36
+XXCCs5FCUdcJOeRdz5+MgCB1L162Pu3/H1evKrAnFMFJOOqL9lNjEyd2IxV+gqEyDJMjlrPp2CMx
+E4F9PdxlP0/NfTESSWw8Nfa94m8nuTlY1V4cvxSj5TXhiT254sZc5pRM15fx4oCbJq6nWVi+p/x7
+FotxA8tSo+oeShlb7kid2C1Iy7JFKq0BaoTnqWAY+z7iQ7tQdZCHrheM4b0GOVkhRwK7UVlWAjTt
+D6TOA7ltsY3sjdTuaLf8v3IF11QrJFPBOOXwC1BTz+LugGZK1plBUtCh3vaaNGLN1y40hXPZ+RGW
+Onh3ZtUH4Wrz3/REh4PtTeTUJKnt14+V9pEnfUTiq86M5EijxP8m/nnghUNs/lpZFqGqY1uJjZm1
+oK/7exM0V0sHZYUU9AZDBrTxk3bJgtY1ntmeuu7xJ24pCJx32Rc+tNnD02BoUvbZhQaeFwWHVVSd
+CsT3vX5q7oBIHnQjMTYKpaP4ofCYPTR5jHQQ/VexsOUZLS23h0oIlPY9pUqvFgWr73i8DSVC9d/t
+DnbICZ5c7q2PC0HIkQGu53c0WtEFBEop2AxYNy/BHm+R/R/GJbleFY87dFgIGdCZq0uKqHB5DtE+
+5947nEEI1tZLhUKyEKTQJxvyn4+6PoXqhyOL69P48XZ9WDC0YmrxstnAyQA0hXkPFp/olWPY6VZf
+AjFBL0UJdII7Il4TbPA+dsfP3AxtJ+LoxIQEdfV/Euh6nc/zC7WBDX6juJppRiRdk2Po8BJ1Ktbz
+Q3JEnLU9oacY8szmezbH0Ar2vWHcI4tQkMhFNC+vBSK/kjN1b+C6dKM1dlbuUeAcMJlAf7/Cy5xJ
+OGryy/bZW/ZzDKBhKKJx2JDGCfQ3O1EEeOtTeuBQlVC42KrRhuurEx4wBAJArinSHVtRLnbmMV54
+vv/Yv4cg0U7DEIYKmCoHFYcEiQcvWKtcQq6W53wGtVPlGB5h/JbmOmPMSzrXp/gkd2Ics1X8eVYl
+CpY5GBRuwxXL1EQRBGp6l1Bd2YYkZKctEQ0IQqaEtXbbNrrHQptAOT8x2VcijnIFNDH2IqzAzqKM
+jXHp4hsvBSPW7eNlyIfJMYloemor5w+m5sJw3AzXYIBlYM2ff3c+Urv0eU9CDNxhFTFjB5RqNzBY
+c0EScpzaldxt1D6kAQs0KVxr06t+Mukms5i/zSaa71bwGL9SV43YQQIgZuEm8Cqh8od+Ox6SbJsy
+qfPNtChB4+ObzNpwax8MBtJk9lsx7xvpIFE2Brbs2S807sEPJAM3wtsAOSVsh9Kzul7oi32GnU9I
+OZcg6d1BBrN3jz6QzyOWrkVQEJCq2QnFYDAkVOeb4oq+qKM/OVmhAWCJ5d5+ildCcep3x4eaIKuW
+d10NUPfCUdO4ItLLClbNxTpvtimP6v9t3v9OZRfdneJrAFNoZZod2kyp/85ewyxqe4AiC2RyGV+P
+HKvALvL2F8BNINnLLiQaPvV9LCbQgtz24RiZXzRerJA2nho85YekEWM+YAc5iJIx1YaE1MkrjPzG
+LrYzHold3I9Hx6PSYoL3S/FnoNtCe2gbNzFWODQqkWiUhZ9+DcABiwfjqWmL0DSdv4mzvA4WTGbo
+DpES6wntv0XF/Oi1NbZ7DrcbuVvfdxFFZS4Z4vHD7AajyCaNiUdNuvgoBt7NdV75pgGzyu38jqTL
+brGAIlSpDMJ0UdA9GoCV+xtw3v8EsMkg6vD6qYz5TQPdVTbxeiSuOasKIXSpsi/AUns4ySglIL/n
+21LqUa/zTDlWLDz9TYHujhJ7QAHWy/oA8IeZ4G3ffYifz5LZ7sBBDLwElRpMBDvRJZOXV+RxGhTI
+4ht+H4ls99vJ+D8dVIXVR4js5VHb8qRJJ0Iqp09lySM/rN/s30D9PT4vIu8CMlfoVEfwel8bwqmZ
+bKIBfhzoReortiCd8+kfppB4Hkml8uo5gZR9yjhQkE27kMe74xhhpxIaAAcTbgUyeYJNq5H3EWJy
+4NCIaPxmnib5ETEMV37+z2Iz9tsRx02rvpEC443x4OoaeShuS3il5oOkf1ynxPviNtmWq5mz4xw4
+CjVBExTjQW3zX+IgT4YrKmt0Jo0ZM7JD+llL4UxbomLonDLDCt89yCW/6K+bSouDWk5epJ7fmAuC
+Eigz5okFBP1J8FAfC65VIV7ZjSdbH+UiE5dsk92304hQ99U4apTWyoUVKsBQdf+RqA5CyxHolnJ6
+MF7F/dt7A/ggmrZ/hJFH2jIFJCv76/DUq+BHCo1jmH0Mn6cneOcuoMLuWLkEv0iV2g3SFLEhgwM8
+qJUvepi34ncWsQ5lUdhSE89tSKp6HVGNr0pX++T4YvxZkytnDdt9B1j7yiSVh7JIlbp3d0MtwATd
+nhKtQ7wDFlJvz5Nb656fYZ2qqAH073+HFYwvylG5ilTCGU1VeHCgJLgLRnL6JH9sGstxbICZ1B1+
+jgZeuTq+7diE4OsHS/lBlzRSEwYvcCI3hjuR0BhHWbHLfxL/5CUcUuoG3RkdTYtZzWDFeQ8bpNyL
+v/0GjZ4h3v0gQFHj/Ca/+khPxOz1oVqJG+FD5NGVUtSpKuvWRpeGGZH93+bf9h0+BH4gNaenJtHW
+sUanndqcESRIPJeY6Tbr9djipvkWls4Kc+l2DpqfXE0MvXHn49nf4DFNnEXV0oypCKv4piximKEg
+9OK1Kuhdi2j6dpKzsxjpVJbnEwap2c0Wz1y8AXbi7hC2LCCvAY6JmaJ3KD4YsR0TfPG/wdBEu5PL
+qGSPq47wWOoRprmYPBbjrShEtqop9WWxVrTl5GEYC8CUMzKAXa8ClddeKpvPScKcdQFGYzMllGGm
+GXrhQgQtJ8MPNtSp69N7Yn2zmZlUPUV5B6AswS1V0A5bJSTJ3832Qm3S8mynKsqg/zeuTEBmFX7N
+cBsO6INZxga+ITnJ9kUqyCmynTt39999yRP9jB14VERljc+hiGAwfXCj/hwp61wMTxX9pL+UtFYL
+4LYkOW/eaooq65bz0RKSflkHjMUM5EohE4nrq7my3LCaWQ3+VTjZ7wqEK/KLuy1TpgstRkq0fu0v
+p1KGHElH/1ZmFDdcWURQK6aNOwa6ngeOldlS4VX40jNSp0nxiuYmLQRdECfvCseozerV267ch3kD
+lNrPAxMed+EiYVMiUSrYwT2aCAn5fy7tFIcNx6W8SiCKoZLcIa5s2fm9rTmatCc2VSAScsqEkqNT
+GLsll1xf2YzotWsYU4Deu04VvPS2tfPdCRlGMMS4656g0CXteBx41A+36EP8YEDrPGn8jGCKBPgf
+G2RSZA8VCf6/iuqqJWBpRmSxjq35wrZetzPaLBBNmhuJAKxcgjTvGnYdOlqC7+Syjm7zm5X4p5S7
+pAnUXP0N91DpD6ehELo8NlSr6wB4b8htx2OBJVLcw7S1ijhN/292zyOdV502452CPreJFQt9o4wz
+N4tYkL2KrCXABZsOSEZktWKla3fb6r4rX1dAm5uZjBJX4+yMJ8Qty+5ZGwLzuYDFU+AsS/zSMswG
+G2X1fkaXvSyF6clVe3qKy6Vp2qCJNclzz4vDgJzXDVsdi8fUfmVoJ1NoDN0p02JgykZ3i9bnVq/m
+SDDfsLPShWCWoBIvWBlTDGEgV9IY8RlgwUHbC5Ody2rcQV2xycaaZe3Wkrkp8dngHSOlnPXigbrX
+/agw5Sg2z8NmzWRdr25FCq8W2Dgor/Gl+uSqRPCCS3Rk9bFRqxl90SFl1LqVusFUW+hMglCrfuCQ
+RBl5zoR4i7RHuh1dt+WF6FE53YBlJyffM/Ve6/6DfuoRkc1zeZ3yHNS/5DKukfN4A8x/yktdstZf
+FbuFR0t9G37LVQnDD9v01Hy5L90juNRqzxeM+/9cp0T4xHM4GfYKjkR2ASpUTBHYVEle4nIBdQ2Z
+ygwomovFkseFg2zHBvKz69XIXgJSKSO0BHA+tLTUXSyY6veUtW/qiUPJt0hpdO8MYOJiDrLc763S
+iw6xgw54AFimOO+5KLBmeNER35K2ITDNikT527qD8YQyLYkM9QgxqfiW6pS6EZQ89vU6ZILXbiuA
+tqeSbN+gYneiwmQUL8N6mOGCVBUARBTPmYurtKEQwGPNBRRDq8QBmQKxtK87y2MMNoD6J5epAR1v
+FIv8N4HLNeDwko0/tvSQuobFbrhG94EB7IxidLgQsRIyK07xrvmC1ZHei3fky4hN4eX6GMSZa2HX
++GfAVcklliw45bzWp+FFWWmofoxrkQauRey9/Ex4jTIY6e+2e8L+08tKg3WyeFcKTj2pu8SkZaYl
+eUqPJZNQAsYP1ggRyeoFVcJpBJwpF3mgEBkrMXUjBCNugAIUIer9wAKVVUvojuFegf2I8J4XqscZ
+jVqsCE6Qpxcd1H1BXwgv2CIbr/R73Y6yaVKDgQ+Q+ZEijVOOCXr5tSTAbMs1s5ORoJaa8t56sB9z
+FTu1zqbVRJ1wLzXlurQQM4XYXDcYliKZjUhYQCGQKaBzBtzX4CK8+sbzX/o4zbe3sA8PyCZtSdL8
+pqUOm3k/zonSy+V+e9REfAiuCZwDRo6qOXwTzLow4m1qa0kNkzwUMKmjQbBblr1A85zGukOUvPvA
+96W7ZlmaEnaPYhmm5i648SLOinjv0tsX00ku76URmdIS14GOYQkoWCXFA623cb6mJovaz6Xecc9v
+HbyjBuKVFOy8AQ9u6ToQoFlLfGa8WDw8J6tz9uATRlTTqBdelUpdZtGECGnF8cM5g2oTOCiCoV5J
+lE2scDyXkjyzEHna6I/740uQbbQgTyr8eOaflYJjDydsaSUPxslX08GLS0SaueBFdO3rPMzQqyVV
+Ylkyvdjj0wWBO75RBtx+ssusoveW7Fey5APlVBdRSrImJIGYeN0c8vULxkQDAOc6Z8H+1SAPftSx
+EHA5l+op+YKAhlEFlOdBYIj7r2V43YKkJNHmCW1yAJwogJPgwok50AXFit//QrHOrauDndE8BwIb
+p9MV10fYnyUQuaSf8qeyPPVX6F/FlynRiQx5mw1/RRy/OWJYvtUGGP2lKDa6q9bxVTbi18FhEuPb
+LoUKA4+Zwf71UbzGBNhJaol89PTBDS/GW0auHZrIUMCDhwErMqHYpj91tyLiT87woPJMQiEl4m3w
+vWzEkmiEAiyl/UMFwqAbQW3XQzDnO3WmeJJbeoYVrLVPBumCn5ne9l077kfF+YyJ99ESMZePMTW+
++Pc7YpcJDF2SuEXOzo3iNi6nxupUEd22Pw/Kdg3d96yCr1nnNqmfO1Xup+OTEeyy8dWFpFfDfvy0
+k2O2lTE/PpWIO3IICy56naoD5yOGvEnRGNBbWPhxsRxttoP0FsEh5QB7o3jG22NVkPlRLcvLpeGi
+FgEH72WJQDXE6svXnx3leooI9TOVZwQseaRP1kl5LK7bJGzGetf5maPuCmF6RJzIkIAFG0HU8eyC
+2WsIUgeKV/sIWIXOMtzVHAzyjnm4zgXC9NUZjDM8wyLTf4fPQbMtwPk579tZbvE8WbAn0+QKm0JH
+C+M5+5+QzuTb8sQx/Ew1QUAKve20S+ac6HHP4WG0S9iFAP7DM7OMifqX+1LYHzrQ/e/psuqyLgN4
+nw9uwfWJ9Jf1Fo5gBQwGjfd792OJisidrSMdVWQfoDcjQIuN7ceEU5iMYvYUsozW4CbAydRabThe
+lKZ9hJRP7y/xYYKBB/A0SOCfHkPj8ifvhSYWZEZ8H26hTCW1A8UTddMOho/4yi5+EdrdajtQK6c1
+MySVuxucYP/awnaC4xz6InBC+IU8ic+pJp8I+bnrA+4Kx5kee/5uQTHr95DfWAkvqSHamDmcG0Jy
+FyGkIyv8ceF6TN1Z/hHQZUL8pqU1fii+dabEK1/0fv00BaDpeMayjiHa7z5LoetqKh1BpxXwe1KO
+i8VtNExUxCV5U5hbHFroEPjuH0dUrleXhTjyQasE8GWMqu7pfQJI0pFtbi/U2xSOTDOFgXbQwy6i
+78HQ1xsN0AKzLW+SxhiNSyeo08LLzTM406RFyMYslVwlr5qbZyYgkaIKv7GYMCDHLvIBfWI+Ef3k
+NxHLNuSaWFdPYmpFmlwMHFtxEp2Pnapu6LRXaEsK4pBy+Li1OGSzVwkVpwv35iod6YdoGdCYikd9
+Ap/4HphMHe2tkPb6FHou5k48BrxDytGnU5uMaQxZOdij3xCKDfbkLtpuDS1sv0OSjvkQWDcjIvhz
+b/U2apzpMtxvciY3PZsL9sIZsjX1/afRNfTk/RvR/c+rAjcqPCYKnKhrTd6bIVgmUhBJs8lQSven
+MwTS/jWxDC4c4kehkQw9CXAHb6pQZT3YozXNN6vD6py5whEJj/LV4+UkkR14kAsh/DPr6fOWiu8p
+rWPtR4OcSZ33XjRJF9+VGVEiuT365ZpKIMEXBRXzQCMih7t+hnaLXzcJ9oHNOPth2ziidpURR/Xz
+EVf36IsOiri24WclgYYoqt0yuRiGE+rFwni//zYxDvC4bVzq73HrrqwB/l9H38Iv70Kuj1gshtsZ
+ZyUQwNtG56bMwV9epZ7wWyMbAee2hVHa7Bm0bRmm4nO5XqA+T/983EaK8ZM+6IWK+pdDXJ2yZMGy
+Wd0aK/OO90cMs7y+BhVDyGeVw3JD7YXggCSTNqfM3ZArJkT5KzPF1YS+iUDzBh2Oakwia2DQOYr6
+qns7rkfww4kzINthEikXtr0SyrCzD/eCsGABrltfbhMlH1SdfpbALLYQlIirJMG6mdVo++KuXgYM
+5L4rwHoeRQwRf3c6e9nK9dhbiDRS2xyyACyrQOp93XilXINL4F36tnKX1tCMT/dfY7BGyUzfW/je
+JI2ideU1vPlQPXKHUaQbPU+zi1HfBKUopXhOBE4EVOGCWt0/1+Iwv0Mp04eeo0irlSlrO4GLe8QH
+GqhaG1NgP2sIWo+n/OWrv72ZStj7PjUxYBCrUbuE9ssvDB+4zRGFhzx961YTFqZ2riYWUQSEtwPR
+ob9ddddj63dlYxFACMs9znY3yEA5xPYqadqlMHtS+JEq/pHJUpOF//oL4FOW9NScYcPWj1ka9iTs
+Yw36YvAiGhRq8C+AM+f41DYwaLNWKP9JW/HY32upHr73MAFXloNyJ4PbluOcaFWeRxr+MSWj9ETM
+Apd43htejrL4j4hR1LVypEpf6kTlUA/yNSaMuc7sC5TvZVmd+Be3h6n3A3NA4HAOZNZNcj44iM0N
+z4s2jXqG2FfjHCe0sBTWRC/urhLpTFXJ3gy5OFkTkuS00FcUKH66F+0gcmtMNnV2/yzohyecz49E
+MLogILlJdniy79G22Xo7eG1AiTW8X7qJlbWHuUTC1KqWSldncywijLpYzvZpQKOeQBnG0f3kFxSa
+CEr/GhBarldbV3+G6+q5HdeuUgoVkYDvoCbDbgP1ZiYwvGRIo3TAoUranYJ+RkC0ToW4RVEftB+M
+U+cuae0uvxBCLYCtymRZkPpl8sxAEOpuIT7BYDjAsZCXMD/yAo8kNnvSFHjjQuLBbBsLf9Nrrqkx
+M/rXbj4r9lylCUKb/PRb4oxLKKCv39dAKDrwKtwlDif3uaw3Vrt13FXTuDL6exoKaouRmeTZdP0W
+Wq8izF18ijRxnX27WrASNQvfr3yw7bMvPedDNHI25357LPmG7xmAUKHISt+e1f/fnqY2fp6dO+ul
+7mL5Pt7R3nEU1U0IS02TdPr37jSZOvYMlC8fMPm30KAxvCZQCzj2wq2z0YBzma448pwbWR82nHwa
+EMnGAp6+Oi5kss0PMORle5EbAeVJcmcmAdRwnpMXNQwoW1n5aEsskFWom7ggcdQVNtJr0xDsxoH3
+DLXzRmcRFPN+7pwNetRW6YPshR4HDKzHplmrdW/wVdMa/OgXWTuIZDNJwDgUjpzif9EMNobKTVTg
+CQ/fWhV/UwGD2cieu0jrsXRvzxHS8VBQnOursRsCNJSGCpz0r50u62qfoLnObOuuzoLnk1x7QgXg
+pVJevVKSuvFOHFCYd52dyMmhPPa2BB/QiChUxA3sjMjMFppu/WglSVGP8TdhWREyd7paQegAt9ms
+ejctecVMlrlqmDwwQqEqWkP5dZwF7XAhOSt18KFGIILO11gXROgwgxQV0Jn0HNIDoQ1xH6jlrjGN
+rpc6GHgigNSi5Tk1ea9zWDu3nWdP5Felu5R6Y6B4h4CxGXagveo8oFf63eecOUZkDnDGHlvko1o7
+PqRK+7wydNQusu06uvZdNKYETxgHNrdELCfUXfNABcdvC9RJcVaAkt3AD7G2mEf9+FXW0+xiRtx6
+x6rLsSMxzWY8CF9m7uJTzujDhY0l15wsCbOc82ga60M3XWnKrgGlhTwIqYMN9UX8/ygh4KT8x+Bm
+y8cNr4Ktau1ja2jwDRrt5eHZEnx3qNrw97QsUX61FMx1VxLYzB1bMELGvszAXKXRybbLrwgVDGrO
+tlTlyF6sD9rTgeOJu0hRHEjUEO/JknCaN/oknMTiBkUlfBO0/LeuUwzGwLZZnnO2F4NrWgeUzm+S
+8kHDM1/dwCNwAx3caZICvHZsRlSXulhCh4TjGfnAGzWpc/SHBLnrNXdOQ2P7uqnmkzQD9nOcjjCO
+BlIsHCSTHuaRwIvJ16WgsI7q9m+rY55SAyjKi241TZoyL+yQRJNLzz07FzLLs49CrbMwRRXnmCl+
+dFHFe6apRT/WMWxmuGgTqa0NmTBvqC8C7FSuJ7YqCZyBXnRWj5buf0m1ZioOtQJdb0lHQpMhimBn
+dZYqFCgJLRyKSlPp35Y94nAE2WFLftPEHi+Rw1q5HYtjO8ObgaexVGvMZO3GoJzj0Fhg/oa3TOip
+ng9ZPoTLfOxGeViYusr4IAEbEsseEGfuzmnSOe4EmUMH7/aUWeWBeTkxoCSmL0DuYRchOy6LiWrw
+J6S+7i7PhN5vlJZLl4L0rbe/O4Iydq+u2LCsBqBKmgsunZdeCWAwNN//X/WAh17pj02/A6Fg3WV4
+4E39kKsB3pMZSWDclz9psmWDUl3bkk/LoRQn/y9bjMULqA1fv1sIGIGxNbKAbcM9NjCjCpb1xi4E
+ZiSPq57VmOkSrUxhBXbmXyHMsKESCH6ZB7KK00j1HtKce2r/kbaVdlNmSjTuZgue4jXT24QnOA0m
+gyFzpK7Umqzp35IDq3hkChllwUBKZcN4AphVByaEWJFkmfRzQ37FeDkXepizPftwrtisU750KL11
+zEZPJVFwHdPo2d1uwsryf98fT5hUSGYJ5DAwb74Ej0VmSF7uMGzB+Bs5cY3qnq6BveSb3m3fighS
+Z4W9X7BPTOJOxyy9TNf3C0+F/DmBytDOrEYQpGqc8yIsWN4JaknOhNhw5qznrccehS9P59GH9rNE
+cqXw77gfcg272hYw6BcOnPi595yJA7zSkqrtUGLyN1ShTtz0BqDe9XasTUzPKrpfkL/IBcWSmHLw
+0PMdSw7OvwcVdjEKFb0mywwgLKPJxj9uEMQxaXh7DIx9K++Y0DlCYC36Qs7x2yPj995TdbHSZ7MD
+Bah3m+lx4xQRWhNO0fXmxJAgKgiCVR20hSB3JRtUsn4TkVjfKozadojPMmqVAZpM3s3FCGoz70lO
+mGt3aHms/Q8VTNDKIQvvya8rY5lt9SwM4FBzc9xcl8KsSknRhuW5wNzDt9iPWLMLt7VM8uGKehh6
+bzhLQOm1c2rGYleuSZYBTu6puFSsLoukOHtIObAQrhLmyyyls5mNH5iZ6bV5uDcRzAmy2ausS6hr
+jUu52ncuGQC1FP9soc3gjZ3LWeamDpoViKJRKGaeM+31Ygf3wfvZYMtiCKtMrynLGrX/h4tZNwKj
+T7cxEJym4IXVYulXuIxhtkDidNtyVX6kOeS0YgeFAomx+0Pi7isy8wN01uT4UhawIqBXilaGVh5a
+miSMtbgn4QLy6CGjqN5kBMN6GGaDZdSpatoVNBD76Q3alPzI4pd/R31VFd+vfExGJvM4ES1HCso1
+zJqsXJFNyt7NEOyPbDy6tgx2cEoWoLEinfpjptSjRHjOaxf3p+IHdMq+5RTboDajSt0B2lR8Ist1
+Z1XtDIRQlQVVRmO/WJpZOJKij7usT5N109q9loq8wAKfrB2MUjxgqfIBhae3CQw1j9hiQqhFuvDG
+3Yo4HJhyiAf4zgv+l7YKWsUmQVJJiDpl+p07fk7guJdxwmdpJTp4JVgm5AnX3BfEZ9wiAw3WFxvp
+6X4PqUEO9DKcE6Ab0wT5oYoWaAk5qIfu234bye0LGtZQtTit4fTHS+ckA+eNVM0oO/WMlL4zlDbg
+9Nrd4arqKBkwChJ+2DMsvfIJA1JH1vsbjkh4v69x4OXU7Mk1n+JMoiB2iw4cNZhhbCUiF7IIlLjR
+WiqIrM9HTOZx/InFXxaOrfa4Rn76+/neBCQdAvyjlIr25C4SfMzZnGpDWQ+yTc5nuK0gBd7LO3zu
+t0T6jiypkuFXs8Jmhz3fOPjs/VsmmrBzLr1NHLnb5RDymB/SDLj+5nOZMlD6jTscBIBf85NL2jjZ
+gGVLhOb6qdhAwThGmgqsU8PP4oag8+UDqr5GeAhOho891xeaosaO6ETE/xn2h9rYa2ebDSfuIXb/
+N+TjTh7T2koeM8Yk7JOph2M/glyNn+yLoJXtpffE4nHzuJf+3p9IoA04d3D/UuRA+hEbwIWAnirw
+ZxO0CXyZovL/X+RrUIOVDaqR1kMYc++HbGBWn6gjl9ochJPiNEctlkSvqdjXiSk5KG24YqiQhMny
+Q7rEa7UdlLbxZiqRUgcmr7eDeSrccLPkZlMYwtRXgzXUIDpKn08QPdZ3iMG6qZh5h8f3ax24iKei
+m8lMGAOUCyYYrH45iJhLq0ae+qGNz4iWpiHBxFVZbyKd15ZLl6ZNkpxIsIESGHprZ7WViK8n6AtN
+87EXqBdTxOPzqDJ2mWeYt0egP5Syp9KxATdbJRhaZLMPksxyLokwpwlHUrhy0kn7Rvb8hMbt4vff
+tkCEhFPmdg0T3tRC3Z3EF9QSI0IsZm1L5RYPCskQ3K6XcNYuVfR3HofIfEkHk87X4kB2go6YPeKV
+1EG/HYqKt2e7DB8Mn6ttKV1UsQxzqLtHIUvx2cP5NNruqm+E3fs+sbYX5eyLqHjTLd4PxGGqFn+N
+FzQt4YC9etc4sKEhUNzKKIAB02gxENZW6qLyBVRB4CzRmVRZyd5/6AZRoQ4CBUq+lYSs/l2hKMNq
+MxPJdz2QOiOSKHnRXDQRQIQzROc9Yjpi3CjPqMaf5xNLwJyuk52mZcrGn3BGt/duIkre6yv6DNxQ
+HAnjLQgUy6Oso77slNYZOFDO30no/h4ofVoqZi3/9Fez/qi+Y2OAT85Wbi1nI6+2JxjzyDOueSUl
+ykTkGhNr1L4dmJxFXa3I1c6xyvxyThT6ecVvRwQIlHeQlzsBsoBLgbNgzWz6SU/mXyi9BCMALjjj
+zCAHPSCysFt4CUhSxx1FhKpS4EesIgqlDib083epN/haZcLxJhuGMlRp/qxjsnhPHHF0KRV6N+QV
+RXfMYmgKYIaDxJMxU5rS1PWVX2F7iXJ2TP8Smc7iRwoORuVOJ+JyMY9gMwPWc2r/a+fTgRoJUVKe
+bn34Ch8wBNF5U79Us8bf2RWfvJLzXLZSkvh4WuJeAk6WqFdvmAWhhY4raoCfXettxdgFqBBtRA7W
+6NvNr84CnlIW6PCEU7pL0Nfl4rVW2TK7YfaNiB6Z9/uHFYUXeLS+ftbpVDewEuxocecoLNzi450E
+pyRWSIx9yWxYUhCC6BdiXcTE024wwMsCBTkOlTJbVYgP3GYjym+2qG1ryhi8sS7KKfCjfZO69Myr
+46dKV3rWFwPkx/75h1apNuz89ukL1Xz+Q7WUwR162tK3Rc+Hq+YJB160TPC8es8uMDlE1PGGrGHW
+rFkXzXCE66tnIBBh1e3yXOV7LkE99a4otErg9THsDdCoLPhyv+UKsBCvREPTXinBuDo4Enh1BRP3
+qp7WePb94/fXtFyTyBlGp1YYu1hnJU9YtKILJl3QeORsy58zJ6sabCcP9UGbdEyyUrL6Dx++S/VB
+4ksFKeTbBk5r2EhzkUJ1dJUytnsC1RGjVBWilhEOKWT44JVFZP9Sv4PZ0B6flOAQUhf4HaiQqOxh
+MHv2bHrFdPQ63tv33qaNEgbfYEuRd+pfWUQGppj7ep6iw4yYtpLcvu5C/uaRTuxS79zxarim21mX
+vhqCGDLFfMELSYumH6VWOgek8+9t+PJy+LgRbEuXTu5qeWHbnC70gmvfm8NYyqqftI8zKH60c8E8
+CC55Ac1UC7aJk0txigt0YoQNhHYuq7XvGAqI/4tBeItZGlJR1IqxNgdwEoJClBIbRPqVq9m4wBJp
+H2vUTCeVLC7qbGY/+iLBNEJDF8cZdmCqrBHu3txpMZSl7kVAhU7917lpCXyu7WxDyjd9sG/IIZzx
+TEWM6Q45/TipNK+jeyJtVWEETAxMuK6ozripSEudSnhfuXaCYP1po92OTXP23Kv0y8kRZucsamNi
+nYuJjEQPh2LxqbyI0dIyZGU6H+1BvuH+JPPLWcrVWfrv7vOB5X9X/g8tGe/9rZjYuOT9HCah3fnU
+j9SG0PK6bviygdx37xL0rNFyUep+S3QannBj3y1AfilNAuuKycrWVRzJmQmpOa7O93WHuwlwj0oS
++fBX7u5MB6bbeB+bJ/6hEYS7T4s2ggoDi1+8tgBfMlVPT7v0KXLDM5L8inV5eyD9xRByqUc0e5mZ
+ZpNyyuLgGMDB2WgXOxHFnSzHhWQpLCGgJI0J3hcTlnBnz3u/8a7EF8Cuo9ovlgLEjx4yRUjASJtR
+Z5gLcrphgKsPmApuwrNyyW/IJ8plVWxZa/ZiDoxkdh0deoy5SGC5yXnS7Q74vfYg/cSF7k1Z0uOj
+xsyFA4i7yZBKZp2umSDXgDLUn/EjJfOQvAi6Vva2y9qjPsdyBo/ftQYkXDUisy/AoO7MCj3Y+IS9
+pcUMY1R5n/yhh/oLTJtxqOuQ+DkCwbDDxT+fgjsr9zry5Kswx8KqV5+dg66goIp9HoQHXwZipiKM
+YLkZYUh6j5/Ayi0VuCab4VAko7YSpoOpQIzXvk8tz6Iy6exLrYXy0oOvx5S+336PLFimMLwoRkHI
+4/vnf1iq4rLERoB9aJqzX/DJzJJvApiukr+tutGokHrb7LdD834rNecH6/Oe0CRTMXrRD3K+QxWP
+OsWE7Esht1MEFi017fHfDCTeYHmePj5nJT90THfdm6z7OoB0wRSMMQVk/qfHHc9Ko4EmlFns/cJ8
+kb4Jne9sQQLkV+EnN4hSmElq0G4AOkJwl8NSZacTeQq+mX9H1gpMB+B1eW2tVa80w2UWYalyqFsO
+3kmCHcBsBZVMrmjj7cvRsDeNaYnLxTUYxG/RxDHooCxrOqZTLADCEXRgmrg/y0yUE5ldEu2NsT76
+1vthdRhqvSdW1GtO1gUCBu0NDEaM3dWHwi/JNOpSW7CEhOTY7xYKwCC3uRrf8HuySHkGDjtbWNrN
+S9wKioZ4r1FKSO+EmISstDHpLx5o9Zc5svulfMjOcOnFu4TNuq4MRBInbw2uPUmPCKKQi/dqVJ8h
+M1E5LLvahEE6duLCIEpPN94XI2K1jADi9jpiPbrrkSLycKWachRlPjWAjaBTXDEOsmud8lBnmAHD
+WJWC2dwN/hcE7LL8bt3C3+mz3dNqxXKkNo0+avJkC+HOnxZI5sR9/ZGarQSuQYGJ/JFxHWaWRQeo
+58iyiQyKCqS1fqtinV9xblO6A526zExniCMW8NbdBuC7D8CtNIvjk8TqEZtWpLRuvVmJwEMV6boV
+h5sAyXmIUyVP28EUbw1XE3yWha45qKG+LZydTrPYJJTMachhHIWbR3ISsDMPr9kfFuEDn0Z4MAFG
+FnG0QGMT31HqDAIMBz/D74EmYwUAXI4jifYrBWvQJM/X7/9plAaEscnzykrsFBE67QWDog75TQPp
+4d1OaBWidIlVmaxeGJRv1VMWcNi2tHOKrfP6g4s6QO+nNr60Yg5UdZGxgSgp6CT+3uAjUaZtjKqX
+U9aQvOHDYhCsmHE1tGQNgFrmRHHQSYmS71lX2ChbHkNt5DSjh1CXaGCRXO2iYrB9voC59MthK7x6
+yUVNABnJftDZgrTqXwOu6Ib7SZ+/z5EoaRn9MA+WBC5hsYv6hBG2QpPOruoApqzP+fWOYf5Wh/JZ
+hgQI5ZFDI/1xWTP8DxFfORuAfBbg/rOXBFCWC3xH3TGcJbOo9S8U3OJ9pQLbgzmYjS61tJqkSK10
+W27XcQsRC4ljufS/llO9EfkrVth+iGxghCtW
+`pragma protect end_protected
+module fifo1k (
+  Data,
+  WrReset,
+  RdReset,
+  WrClk,
+  RdClk,
+  WrEn,
+  RdEn,
+  Almost_Full,
+  Q,
+  Empty,
+  Full
+)
+;
+input [15:0] Data;
+input WrReset;
+input RdReset;
+input WrClk;
+input RdClk;
+input WrEn;
+input RdEn;
+output Almost_Full;
+output [15:0] Q;
+output Empty;
+output Full;
+wire VCC;
+wire GND;
+  \~fifo.fifo1k  fifo_inst (
+    .RdClk(RdClk),
+    .RdReset(RdReset),
+    .WrClk(WrClk),
+    .WrReset(WrReset),
+    .WrEn(WrEn),
+    .RdEn(RdEn),
+    .Data(Data[15:0]),
+    .Full(Full),
+    .Almost_Full(Almost_Full),
+    .Empty(Empty),
+    .Q(Q[15:0])
+);
+  VCC VCC_cZ (
+    .V(VCC)
+);
+  GND GND_cZ (
+    .G(GND)
+);
+  GSR GSR (
+    .GSRI(VCC) 
+);
+endmodule /* fifo1k */

ModRetro_oss-chromatic-console-fpga/esp32t/src/gowin_adc/gowin_adc.v

@@ -0,0 +1,60 @@
+//Copyright (C)2014-2023 Gowin Semiconductor Corporation.
+//All rights reserved.
+//File Title: IP file
+//GOWIN Version: V1.9.9 Beta-4
+//Part Number: GW5A-EV25UG256CES
+//Device: GW5A-25
+//Device Version: A
+//Created Time: Tue Oct 31 16:08:09 2023
+
+module Gowin_ADC (adcrdy, adcvalue, mdrp_rdata, vsenctl, adcen, clk, drstn, adcreqi, adcmode, mdrp_clk, mdrp_wdata, mdrp_a_inc, mdrp_opcode);
+
+output adcrdy;
+output [13:0] adcvalue;
+output [7:0] mdrp_rdata;
+input [2:0] vsenctl;
+input adcen;
+input clk;
+input drstn;
+input adcreqi;
+input adcmode;
+input mdrp_clk;
+input [7:0] mdrp_wdata;
+input mdrp_a_inc;
+input [1:0] mdrp_opcode;
+
+ADC adc_inst (
+    .ADCRDY(adcrdy),
+    .ADCVALUE(adcvalue),
+    .MDRP_RDATA(mdrp_rdata),
+    .VSENCTL(vsenctl),
+    .ADCEN(adcen),
+    .CLK(clk),
+    .DRSTN(drstn),
+    .ADCREQI(adcreqi),
+    .ADCMODE(adcmode),
+    .MDRP_CLK(mdrp_clk),
+    .MDRP_WDATA(mdrp_wdata),
+    .MDRP_A_INC(mdrp_a_inc),
+    .MDRP_OPCODE(mdrp_opcode)
+);
+
+defparam adc_inst.CLK_SEL = 1'b0;
+defparam adc_inst.DIV_CTL = 2'd0;
+defparam adc_inst.BUF_EN = 12'b010000001001;
+defparam adc_inst.BUF_BK0_VREF_EN = 1'b0;
+defparam adc_inst.BUF_BK1_VREF_EN = 1'b0;
+defparam adc_inst.BUF_BK2_VREF_EN = 1'b0;
+defparam adc_inst.BUF_BK3_VREF_EN = 1'b0;
+defparam adc_inst.BUF_BK4_VREF_EN = 1'b0;
+defparam adc_inst.BUF_BK5_VREF_EN = 1'b0;
+defparam adc_inst.BUF_BK6_VREF_EN = 1'b0;
+defparam adc_inst.BUF_BK7_VREF_EN = 1'b0;
+defparam adc_inst.CSR_ADC_MODE = 1'b1;
+defparam adc_inst.CSR_VSEN_CTRL = 3'd0;
+defparam adc_inst.CSR_SAMPLE_CNT_SEL = 3'd4;
+defparam adc_inst.CSR_RATE_CHANGE_CTRL = 3'd4;
+defparam adc_inst.CSR_FSCAL = 10'd653;
+defparam adc_inst.CSR_OFFSET = 12'd0;
+
+endmodule //Gowin_ADC

ModRetro_oss-chromatic-console-fpga/esp32t/src/gowin_pll_preevt/gowin_pll.v

@@ -0,0 +1,138 @@
+//Copyright (C)2014-2024 Gowin Semiconductor Corporation.
+//All rights reserved.
+//File Title: IP file
+//Tool Version: V1.9.9.02
+//Part Number: GW5A-EV25UG256CES
+//Device: GW5A-25
+//Device Version: A
+//Created Time: Wed Apr 24 22:27:40 2024
+
+module Gowin_PLL (lock, clkout0, clkout1, clkout2, clkout3, clkout4, clkin, reset);
+
+output lock;
+output clkout0;
+output clkout1;
+output clkout2;
+output clkout3;
+output clkout4;
+input clkin;
+input reset;
+
+wire clkout5;
+wire clkout6;
+wire clkfbout;
+wire [7:0] mdrdo;
+wire gw_gnd;
+
+assign gw_gnd = 1'b0;
+
+PLLA PLLA_inst (
+    .LOCK(lock),
+    .CLKOUT0(clkout0),
+    .CLKOUT1(clkout1),
+    .CLKOUT2(clkout2),
+    .CLKOUT3(clkout3),
+    .CLKOUT4(clkout4),
+    .CLKOUT5(clkout5),
+    .CLKOUT6(clkout6),
+    .CLKFBOUT(clkfbout),
+    .MDRDO(mdrdo),
+    .CLKIN(clkin),
+    .CLKFB(gw_gnd),
+    .RESET(reset),
+    .PLLPWD(gw_gnd),
+    .RESET_I(gw_gnd),
+    .RESET_O(gw_gnd),
+    .PSSEL({gw_gnd,gw_gnd,gw_gnd}),
+    .PSDIR(gw_gnd),
+    .PSPULSE(gw_gnd),
+    .SSCPOL(gw_gnd),
+    .SSCON(gw_gnd),
+    .SSCMDSEL({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd}),
+    .SSCMDSEL_FRAC({gw_gnd,gw_gnd,gw_gnd}),
+    .MDCLK(gw_gnd),
+    .MDOPC({gw_gnd,gw_gnd}),
+    .MDAINC(gw_gnd),
+    .MDWDI({gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd,gw_gnd})
+);
+
+defparam PLLA_inst.FCLKIN = "33.554";
+defparam PLLA_inst.IDIV_SEL = 1;
+defparam PLLA_inst.FBDIV_SEL = 1;
+defparam PLLA_inst.ODIV0_SEL = 6;
+defparam PLLA_inst.ODIV1_SEL = 24;
+defparam PLLA_inst.ODIV2_SEL = 48;
+defparam PLLA_inst.ODIV3_SEL = 96;
+defparam PLLA_inst.ODIV4_SEL = 12;
+defparam PLLA_inst.ODIV5_SEL = 8;
+defparam PLLA_inst.ODIV6_SEL = 8;
+defparam PLLA_inst.MDIV_SEL = 24;
+defparam PLLA_inst.MDIV_FRAC_SEL = 0;
+defparam PLLA_inst.ODIV0_FRAC_SEL = 0;
+defparam PLLA_inst.CLKOUT0_EN = "TRUE";
+defparam PLLA_inst.CLKOUT1_EN = "TRUE";
+defparam PLLA_inst.CLKOUT2_EN = "TRUE";
+defparam PLLA_inst.CLKOUT3_EN = "TRUE";
+defparam PLLA_inst.CLKOUT4_EN = "TRUE";
+defparam PLLA_inst.CLKOUT5_EN = "FALSE";
+defparam PLLA_inst.CLKOUT6_EN = "FALSE";
+defparam PLLA_inst.CLKFB_SEL = "INTERNAL";
+defparam PLLA_inst.CLKOUT0_DT_DIR = 1'b1;
+defparam PLLA_inst.CLKOUT1_DT_DIR = 1'b1;
+defparam PLLA_inst.CLKOUT2_DT_DIR = 1'b1;
+defparam PLLA_inst.CLKOUT3_DT_DIR = 1'b1;
+defparam PLLA_inst.CLKOUT0_DT_STEP = 0;
+defparam PLLA_inst.CLKOUT1_DT_STEP = 0;
+defparam PLLA_inst.CLKOUT2_DT_STEP = 0;
+defparam PLLA_inst.CLKOUT3_DT_STEP = 0;
+defparam PLLA_inst.CLK0_IN_SEL = 1'b0;
+defparam PLLA_inst.CLK0_OUT_SEL = 1'b0;
+defparam PLLA_inst.CLK1_IN_SEL = 1'b0;
+defparam PLLA_inst.CLK1_OUT_SEL = 1'b0;
+defparam PLLA_inst.CLK2_IN_SEL = 1'b0;
+defparam PLLA_inst.CLK2_OUT_SEL = 1'b0;
+defparam PLLA_inst.CLK3_IN_SEL = 1'b0;
+defparam PLLA_inst.CLK3_OUT_SEL = 1'b0;
+defparam PLLA_inst.CLK4_IN_SEL = 2'b00;
+defparam PLLA_inst.CLK4_OUT_SEL = 1'b0;
+defparam PLLA_inst.CLK5_IN_SEL = 1'b0;
+defparam PLLA_inst.CLK5_OUT_SEL = 1'b0;
+defparam PLLA_inst.CLK6_IN_SEL = 1'b0;
+defparam PLLA_inst.CLK6_OUT_SEL = 1'b0;
+defparam PLLA_inst.DYN_DPA_EN = "FALSE";
+defparam PLLA_inst.CLKOUT0_PE_COARSE = 0;
+defparam PLLA_inst.CLKOUT0_PE_FINE = 0;
+defparam PLLA_inst.CLKOUT1_PE_COARSE = 0;
+defparam PLLA_inst.CLKOUT1_PE_FINE = 0;
+defparam PLLA_inst.CLKOUT2_PE_COARSE = 0;
+defparam PLLA_inst.CLKOUT2_PE_FINE = 0;
+defparam PLLA_inst.CLKOUT3_PE_COARSE = 0;
+defparam PLLA_inst.CLKOUT3_PE_FINE = 0;
+defparam PLLA_inst.CLKOUT4_PE_COARSE = 0;
+defparam PLLA_inst.CLKOUT4_PE_FINE = 0;
+defparam PLLA_inst.CLKOUT5_PE_COARSE = 0;
+defparam PLLA_inst.CLKOUT5_PE_FINE = 0;
+defparam PLLA_inst.CLKOUT6_PE_COARSE = 0;
+defparam PLLA_inst.CLKOUT6_PE_FINE = 0;
+defparam PLLA_inst.DYN_PE0_SEL = "FALSE";
+defparam PLLA_inst.DYN_PE1_SEL = "FALSE";
+defparam PLLA_inst.DYN_PE2_SEL = "FALSE";
+defparam PLLA_inst.DYN_PE3_SEL = "FALSE";
+defparam PLLA_inst.DYN_PE4_SEL = "FALSE";
+defparam PLLA_inst.DYN_PE5_SEL = "FALSE";
+defparam PLLA_inst.DYN_PE6_SEL = "FALSE";
+defparam PLLA_inst.DE0_EN = "FALSE";
+defparam PLLA_inst.DE1_EN = "FALSE";
+defparam PLLA_inst.DE2_EN = "FALSE";
+defparam PLLA_inst.DE3_EN = "FALSE";
+defparam PLLA_inst.DE4_EN = "FALSE";
+defparam PLLA_inst.DE5_EN = "FALSE";
+defparam PLLA_inst.DE6_EN = "FALSE";
+defparam PLLA_inst.RESET_I_EN = "FALSE";
+defparam PLLA_inst.RESET_O_EN = "FALSE";
+defparam PLLA_inst.ICP_SEL = 6'bXXXXXX;
+defparam PLLA_inst.LPF_RES = 3'bXXX;
+defparam PLLA_inst.LPF_CAP = 2'b00;
+defparam PLLA_inst.SSC_EN = "FALSE";
+
+endmodule //Gowin_PLL

ModRetro_oss-chromatic-console-fpga/esp32t/src/rtl/BSP/MultiPortRamCtrl.vhd

@@ -0,0 +1,219 @@
+-----------------------------------------------------------------
+--------------- MultiPortPSRAM Package  -------------------------
+-----------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.all;  
+use IEEE.numeric_std.all;     
+
+package pMultiPortPSRAM is
+
+   constant RAMPORTCOUNT : integer := 5;
+
+   type tRAMIn_request         is array(0 to RAMPORTCOUNT - 1) of std_logic;
+   type tRAMIn_RnW             is array(0 to RAMPORTCOUNT - 1) of std_logic;
+   type tRAMIn_addr            is array(0 to RAMPORTCOUNT - 1) of std_logic_vector(22 downto 0);
+   type tRAMIn_din             is array(0 to RAMPORTCOUNT - 1) of std_logic_vector(15 downto 0);
+   type tRAMIn_burst_length    is array(0 to RAMPORTCOUNT - 1) of unsigned(10 downto 0);
+   
+   type tRAMOut_writeNext      is array(0 to RAMPORTCOUNT - 1) of std_logic;
+   type tRAMOut_done           is array(0 to RAMPORTCOUNT - 1) of std_logic;
+   type tRAMOut_dout_valid     is array(0 to RAMPORTCOUNT - 1) of std_logic;
+
+end package;
+
+-----------------------------------------------------------------
+--------------- MultiPortPSRAM Mux   ----------------------------
+-----------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.all;     
+
+use work.pMultiPortPSRAM.all;
+
+entity MultiPortRamCtrl is 
+   generic
+   (
+      ISSIMU : boolean := false
+   );
+   port 
+   (
+      clk_sys              : in    std_logic;
+      clk_fsys             : in    std_logic;
+      rst                  : in    std_logic;
+      
+      RAMIn_request        : in    tRAMIn_request;   
+      RAMIn_RnW            : in    tRAMIn_RnW;         
+      RAMIn_addr           : in    tRAMIn_addr;        
+      RAMIn_din            : in    tRAMIn_din;         
+      RAMIn_burst_length   : in    tRAMIn_burst_length;
+                                   
+      RAMOut_writeNext     : out   tRAMOut_writeNext;        
+      RAMOut_done          : out   tRAMOut_done;             
+      RAMOut_dout_valid    : out   tRAMOut_dout_valid;       
+      
+      ram_ready            : out   std_logic;
+      ram_dout             : out   std_logic_vector(15 downto 0); 
+      
+      psram_clk            : out   std_logic;
+      psram_cs_n           : out   std_logic;
+      psram_rwds           : inout std_logic := 'Z';
+      psram_dq             : inout std_logic_vector(7 downto 0) := (others => 'Z')
+   );   
+end entity;
+
+architecture arch of MultiPortRamCtrl is
+
+   -- statemachine
+   type tstate is
+   (
+      IDLE,
+      WAITRAM
+   );
+   signal state            : tstate := IDLE;
+   
+   signal rrb              : integer range 0 to RAMPORTCOUNT - 1;
+   signal req_latched      : std_logic_vector(0 to RAMPORTCOUNT) := (others => '0');
+   signal lastIndex        : integer range 0 to RAMPORTCOUNT - 1;
+
+   -- controller
+   signal req_read         : std_logic := '0';
+   signal req_write        : std_logic := '0';
+   signal addr             : std_logic_vector(22 downto 0) := (others => '0');
+   signal din              : std_logic_vector(15 downto 0); 
+   signal burst_length     : unsigned(10 downto 0) := (others => '0'); -- in bytes
+
+   signal writeNext        : std_logic;
+   signal done             : std_logic; 
+   signal dout_valid       : std_logic;
+   
+   
+begin
+
+   din          <= RAMIn_din(lastIndex);
+   
+   process (all)
+   begin
+      
+      for i in 0 to RAMPORTCOUNT - 1 loop
+         RAMOut_done(i)       <= '0';
+         RAMOut_dout_valid(i) <= '0';
+         RAMOut_writeNext(i)  <= '0';
+      end loop;
+      
+      if (state = WAITRAM) then
+         if (done = '1')       then  RAMOut_done(lastIndex)       <= '1'; end if;
+         if (dout_valid = '1') then  RAMOut_dout_valid(lastIndex) <= '1'; end if;
+         if (writeNext = '1')  then  RAMOut_writeNext(lastIndex)  <= '1'; end if;
+      end if;
+      
+   end process;
+
+   process (clk_sys)
+      variable activeRequest : std_logic;
+      variable activeIndex   : integer range 0 to RAMPORTCOUNT - 1;
+   begin
+      if rising_edge(clk_sys) then
+      
+         req_read  <= '0';
+         req_write <= '0';
+      
+         -- request handling -> any active, but round robin has priority
+         activeRequest := '0';
+         for i in 0 to RAMPORTCOUNT - 1 loop
+            if (RAMIn_request(i) = '1') then
+               req_latched(i) <= '1';
+            end if;
+               
+            if (RAMIn_request(i) = '1' or req_latched(i) = '1') then
+               activeRequest := '1';
+               activeIndex   := i;
+            end if;
+            
+         end loop;
+         
+         if (req_latched(rrb) = '1') then
+            activeIndex := rrb;
+         end if;
+         
+         
+         if (rst = '1') then
+         
+            state       <= IDLE;
+            req_latched <= (others => '0');
+            
+         else
+
+            -- main statemachine
+            case (state) is
+               when IDLE =>
+                  
+                  lastIndex    <= activeIndex;
+                  
+                  -- round robin
+                  if (rrb < RAMPORTCOUNT - 1) then
+                     rrb <= rrb + 1;
+                  else
+                     rrb <= 0;
+                  end if;
+                  
+                  if (activeRequest = '1' and ram_ready = '1') then
+                  
+                     state                    <= WAITRAM;
+                     req_latched(activeIndex) <= '0';
+                     
+                     if (RAMIn_RnW(activeIndex) = '1') then
+                        req_read <= '1';
+                     else
+                        req_write <= '1';
+                     end if;                     
+                      
+                     burst_length  <= RAMIn_burst_length(activeIndex);
+                     addr          <= RAMIn_addr(activeIndex);
+                     
+                  end if;   
+                     
+               when WAITRAM =>
+                  if (done = '1') then
+                     state <= IDLE;
+                  end if;
+              
+            end case;
+            
+         end if;
+
+      end if;
+   end process;
+
+   iPsramController : entity work.PSRAMController 
+   generic map
+   (
+        ISSIMU      => ISSIMU
+   )
+   port map
+   (
+      clk_sys       => clk_sys,      
+      clk_fsys      => clk_fsys,
+      rst           => rst,      
+      req_read      => req_read,          
+      req_write     => req_write,        
+      addr          => addr,         
+      din           => din,
+      burst_length  => burst_length,
+                    
+      ready         => ram_ready, 
+      writeNext     => writeNext,
+      dout          => ram_dout, 
+      dout_valid    => dout_valid,
+      done          => done,         
+                    
+      psram_clk     => psram_clk,   
+      psram_rwds    => psram_rwds,
+      psram_dq      => psram_dq,  
+      psram_cs_n    => psram_cs_n 
+   );
+   
+end architecture;
+
+

ModRetro_oss-chromatic-console-fpga/esp32t/src/rtl/BSP/PSRAMBIST_Burst.vhd

@@ -0,0 +1,174 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.all;     
+
+entity PSRAMBIST_Burst is 
+   generic
+   (
+      BIST_BURSTLENGTH : integer range 1 to 512 := 512;
+      SHORTTEST        : boolean := true
+   );
+   port 
+   (
+      clk                  : in  std_logic;
+      rst                  : in  std_logic;
+      
+      test_finished        : out std_logic := '0';                  
+      test_failed          : out std_logic := '0';                           
+      
+      ram_req_read         : out std_logic := '0';
+      ram_req_write        : out std_logic := '0';
+      ram_addr             : out std_logic_vector(22 downto 0) := (others => '0');
+      ram_din              : out std_logic_vector(15 downto 0) := (others => '0');
+      burst_length         : out unsigned(10 downto 0);
+      ram_ready            : in  std_logic; 
+      ram_writeNext        : in  std_logic; 
+      ram_done             : in  std_logic; 
+      ram_dout             : in  std_logic_vector(15 downto 0);
+      ram_dout_valid       : in  std_logic
+   );   
+end entity;
+
+architecture arch of PSRAMBIST_Burst is
+
+   type tState is 
+   (  
+      WRITE_START,
+      WRITE_WAIT,
+      READ_START,
+      READ_WAIT,
+      TESTDONE
+   ); 
+   signal state  : tState := WRITE_START;  
+   
+   type tTesttype is 
+   (  
+      ALTERNATING,
+      COUNT,
+      ONES,
+      ZEROS
+   ); 
+   signal testtype  : tTesttype := ALTERNATING; 
+   
+   signal addr_cnt  : unsigned(21 downto 0) := (others => '0');
+   signal burst_cnt : unsigned(9 downto 0);
+   
+begin
+
+   burst_length <= to_unsigned(BIST_BURSTLENGTH * 2, 11);
+
+   process (clk)
+   begin
+      if rising_edge(clk) then
+      
+         ram_req_read  <= '0';
+         ram_req_write <= '0';
+         
+         if (rst = '1') then
+            state         <= WRITE_START;
+            testtype      <= ALTERNATING;
+            addr_cnt      <= (others => '0');
+            ram_din       <= x"AA55";
+            test_finished <= '0';
+            test_failed   <= '0';
+         else
+
+            case (state) is
+         
+               when WRITE_START | READ_START =>
+                  if (ram_ready = '1') then
+                     if (state = WRITE_START) then
+                        state         <= WRITE_WAIT;
+                        ram_req_write <= '1';
+                     else
+                        state         <= READ_WAIT;
+                        ram_req_read  <= '1';
+                     end if;
+                     
+                     ram_addr   <= std_logic_vector(addr_cnt) & '0';
+                     addr_cnt   <= addr_cnt + 1;
+                     burst_cnt  <= to_unsigned(BIST_BURSTLENGTH, 10);
+                     
+                     if (SHORTTEST = true) then
+                        addr_cnt   <= addr_cnt + (512 * BIST_BURSTLENGTH) + 1;
+                     end if;
+                     
+                     case (testtype) is
+                        when ALTERNATING => ram_din <= not ram_din;
+                        when COUNT       => ram_din <= std_logic_vector(addr_cnt(15 downto 0));
+                        when ONES        => ram_din <= (others => '1');
+                        when ZEROS       => ram_din <= (others => '0');
+                     end case;
+                  end if;
+                  
+               when WRITE_WAIT =>
+                  if (ram_done = '1') then
+                     state <= WRITE_START;
+                     if ((SHORTTEST = true and addr_cnt(addr_cnt'left) = '1') or (SHORTTEST = false and addr_cnt = 0)) then
+                        state    <= READ_START;
+                        addr_cnt <= (others => '0');
+                        ram_din  <= x"AA55";
+                     end if;
+                  end if;
+                  
+                  if (ram_writeNext = '1') then
+--                   for debug/bring-up, not used by the controller
+--                   ram_addr      <= std_logic_vector(unsigned(ram_addr) + 2);
+                     if (SHORTTEST = false) then
+                        addr_cnt   <= addr_cnt + 1;
+                     end if;
+                     case (testtype) is
+                        when ALTERNATING => ram_din <= not ram_din;
+                        when COUNT       => ram_din <= std_logic_vector(unsigned(ram_din) + 1);
+                        when ONES        => ram_din <= (others => '1');
+                        when ZEROS       => ram_din <= (others => '0');
+                     end case;
+                  end if;
+               
+               when READ_WAIT =>
+                  if (ram_done = '1') then
+                     state <= READ_START;
+                     if ((SHORTTEST = true and addr_cnt(addr_cnt'left) = '1') or (SHORTTEST = false and addr_cnt = 0)) then
+                        state    <= WRITE_START;
+                        addr_cnt <= (others => '0');
+                        case (testtype) is
+                           when ALTERNATING => testtype <= COUNT;
+                           when COUNT       => testtype <= ONES; 
+                           when ONES        => testtype <= ZEROS;
+                           when ZEROS       => state <= TESTDONE;
+                        end case;
+                     end if;
+                  end if;
+                        
+                  if (ram_dout_valid = '1') then
+                     if (ram_done = '0') then
+                        if (SHORTTEST = false) then
+                           addr_cnt   <= addr_cnt + 1;
+                        end if;
+                        case (testtype) is
+                           when ALTERNATING => ram_din <= not ram_din;
+                           when COUNT       => ram_din <= std_logic_vector(unsigned(ram_din) + 1);
+                           when ONES        => ram_din <= (others => '1');
+                           when ZEROS       => ram_din <= (others => '0');
+                        end case;
+                     end if;
+                     
+                     if (ram_dout /= ram_din) then
+                        test_failed <= '1';
+                     end if;
+                     
+                  end if;
+                 
+               when TESTDONE =>
+                  test_finished <= '1';
+         
+            end case;
+            
+         end if;
+      
+      end if;
+   end process;
+   
+end architecture;
+
+

ModRetro_oss-chromatic-console-fpga/esp32t/src/rtl/BSP/PSRAMController.vhd

@@ -0,0 +1,716 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.all;     
+
+entity PSRAMController is 
+   generic
+   (
+      ISSIMU             : boolean := false;
+   
+      IODELAY_SETTING : integer_vector := (
+          0 => 0,  -- DQ0
+          1 => 0,  -- DQ1
+          2 => 0,  -- DQ2
+          3 => 0,  -- DQ3
+          4 => 0,  -- DQ4
+          5 => 0,  -- DQ5
+          6 => 0,  -- DQ6
+          7 => 0,  -- DQ7
+          8 => 0,  -- CLK
+          9 => 0,   -- CS_N,
+          10 => 0   -- RWDS,
+      );
+   
+      READLATENCY        : integer range 3 to 7 := 5; -- verified in simulation for all options
+      WRITELATENCY       : integer range 3 to 7 := 5; -- verified in simulation for all options
+      CFG0_LT            : std_logic := '0';                      -- default startup values, changes not verified
+      CFG0_DRIVESTRENGTH : std_logic_vector(1 downto 0) := "00";  -- testing increased drive strength (01 is default)
+      CFG4_RF            : std_logic := '0';                      -- default startup values, changes not verified
+      CFG4_PASR          : std_logic_vector(2 downto 0) := "000"; -- default startup values, changes not verified
+      CFG8_RBX           : std_logic := '1';                      -- read across 1k border
+      CFG8_BT            : std_logic := '1';                      -- default startup values, changes not verified
+      CFG8_BL            : std_logic_vector(1 downto 0) := "11"   -- increase to 1k byte wrap (01 default)
+   );
+   port 
+   (
+      clk_sys              : in    std_logic;
+      clk_fsys             : in    std_logic;
+      rst                  : in    std_logic;
+      
+      req_read             : in    std_logic;
+      req_write            : in    std_logic;
+      addr                 : in    std_logic_vector(22 downto 0);
+      din                  : in    std_logic_vector(15 downto 0); 
+      burst_length         : in    unsigned(10 downto 0); -- in bytes
+      
+      cfg_0_LT             : out   std_logic;
+      cfg_0_readLatency    : out   std_logic_vector(2 downto 0);
+      cfg_0_driveStrength  : out   std_logic_vector(1 downto 0);
+      cfg_1_ULP            : out   std_logic;
+      cfg_1_VendorID       : out   std_logic_vector(4 downto 0);
+      cfg_2_GB             : out   std_logic;
+      cfg_2_DevID          : out   std_logic_vector(1 downto 0);
+      cfg_2_Density        : out   std_logic_vector(2 downto 0);
+      cfg_3_RBXen          : out   std_logic;
+      cfg_3_VCC            : out   std_logic;
+      cfg_3_SRF            : out   std_logic;
+      cfg_4_writeLatency   : out   std_logic_vector(2 downto 0);
+      cfg_4_RF             : out   std_logic;
+      cfg_4_PASR           : out   std_logic_vector(2 downto 0);
+      cfg_8_RBX            : out   std_logic;
+      cfg_8_BT             : out   std_logic;
+      cfg_8_BL             : out   std_logic_vector(1 downto 0);
+
+      ready                : out   std_logic := '0';
+      writeNext            : out   std_logic := '0';
+      done                 : out   std_logic := '0'; 
+      dout_valid           : out   std_logic := '0';
+      dout                 : out   std_logic_vector(15 downto 0) := (others => '0'); 
+               
+      psram_clk            : out   std_logic;
+      psram_cs_n           : out   std_logic;
+      psram_rwds           : inout std_logic := 'Z';
+      psram_dq             : inout std_logic_vector(7 downto 0) := (others => 'Z')
+   );   
+end entity;
+
+architecture arch of PSRAMController is
+
+   type tState is 
+   (  
+      RESET,
+      CONFIGWRITE_NEXT,
+      CONFIGWRITE_START,
+      CONFIGWRITE,
+      CONFIGREAD_NEXT,
+      CONFIGREAD_START,
+      CONFIGREAD,
+      IDLE,
+      READING,
+      READVAL,
+      WRITING,
+      WRITE_NEWROW
+   ); 
+   signal state  : tState := RESET;  
+   
+   signal configwrite_addr : std_logic_vector(3 downto 0) := x"0";
+   signal configread_addr  : std_logic_vector(3 downto 0) := x"0";
+   
+   signal startup_cnt      : integer range 0 to 50000 := 0; -- adjust for clock speed
+   
+   signal dq_shiftreg      : std_logic_vector(63 downto 0) := (others => '0');
+   signal step             : integer range 0 to 15;
+   
+   signal burst_count      : unsigned(10 downto 0);
+   signal writeburst       : std_logic := '0';
+   signal addr_nextRow     : std_logic_vector(12 downto 0);
+   signal row_count        : unsigned(8 downto 0);
+   
+   signal clock_ena        : std_logic := '0';
+   signal oe_dq_n          : std_logic := '1';
+   signal oe_rwds_n        : std_logic := '1';
+   signal cs_ena_n         : std_logic := '1';
+   
+   signal rwds_out_rising  : std_logic := '1';
+   signal rwds_out_falling : std_logic := '1';
+   
+   signal rwds_in_Q   : std_logic_vector(3 downto 0);
+
+   signal psram_dq_o     : std_logic_vector(7 downto 0);
+   
+   signal dq_in_adjustH   : std_logic_vector(7 downto 0);
+   signal dq_in_adjustL   : std_logic_vector(7 downto 0);
+
+   signal dq_in_Q0     : std_logic_vector(7 downto 0);
+   signal dq_in_Q1     : std_logic_vector(7 downto 0);
+   signal dq_in_Q2    : std_logic_vector(7 downto 0);
+   signal dq_in_Q3    : std_logic_vector(7 downto 0);
+   
+   signal oddr_rwds_data   : std_logic;
+   signal oddr_rwds_enaN   : std_logic;
+   signal oddr_dq_data     : std_logic_vector(7 downto 0);
+   signal oddr_dq_data_dly : std_logic_vector(7 downto 0);
+   signal oddr_dq_enaN     : std_logic_vector(7 downto 0);
+   
+   signal psram_clk_dly    : std_logic;
+   signal psram_cs_n_dly   : std_logic;
+   signal oddr_rwds_data_dly : std_logic;
+   signal psram_rwds_o     : std_logic;
+   
+   signal receiving_data   : std_logic;
+   
+   component IDDR is
+   PORT (
+      Q0 : OUT std_logic;
+      Q1 : OUT std_logic;   
+      D : IN std_logic;
+      CLK: IN std_logic
+   );
+   end component;
+
+   component IDES4 is
+   PORT (
+      D     : IN std_logic;
+      FCLK  : IN std_logic;
+      PCLK  : IN std_logic;
+      CALIB : IN std_logic;
+      RESET : IN std_logic;
+      Q0    : OUT std_logic;
+      Q1    : OUT std_logic;
+      Q2    : OUT std_logic;
+      Q3    : OUT std_logic
+   );
+   end component;
+
+   component OSER4 is
+   GENERIC (
+        HWL : string := "false"; --"true"; "false"
+        TXCLK_POL : bit := '0' --'0':Rising edge output; '1':Falling edge output
+   );
+   PORT (
+      D0    : IN std_logic;
+      D1    : IN std_logic;
+      D2    : IN std_logic;
+      D3    : IN std_logic;
+      TX0   : IN std_logic; -- active low
+      TX1   : IN std_logic; -- active low
+      FCLK  : IN std_logic;
+      PCLK  : IN std_logic;
+      RESET : IN std_logic;
+      Q0    : OUT std_logic;
+      Q1    : OUT std_logic
+   );
+   end component;
+        
+   component ODDR is
+   GENERIC ( 
+       TXCLK_POL : bit := '0' --'0':Rising edge output; '1':Falling edge output        
+   );   
+   PORT ( 
+      Q0 : OUT std_logic;   
+      Q1 : OUT std_logic;   
+      D0 : IN std_logic;
+      D1 : IN std_logic;
+      TX : IN std_logic;
+      CLK : IN std_logic
+   );   
+   end component;
+   
+    component IODELAY is
+    GENERIC (
+        C_STATIC_DLY : integer:=0
+    );
+    PORT (
+        DO      : OUT std_logic;
+        DF      : OUT std_logic;
+        DI      : IN std_logic;
+        SDTAP   : IN std_logic;
+        DLYSTEP : IN std_logic_vector(7 downto 0);
+        VALUE   : IN std_logic
+    );
+    end component;
+   
+begin
+
+   u_iodelay_psram_cs_n : IODELAY 
+   generic map
+   (
+      C_STATIC_DLY => IODELAY_SETTING(9)
+   )
+   port map
+   (
+        DO      => psram_cs_n,
+        DF      => open,
+        DI      => psram_cs_n_dly,
+        SDTAP   => '0',
+        DLYSTEP => 8x"0",
+        VALUE   => '0'
+   );
+   
+    oser4_psram_cs_n : OSER4 port map
+    (
+        PCLK    => clk_sys,
+        FCLK    => clk_fsys,
+        RESET   => rst,
+        TX0     => '0',
+        TX1     => '0',
+        D0      => cs_ena_n,
+        D1      => cs_ena_n,
+        D2      => cs_ena_n,
+        D3      => cs_ena_n,
+        Q0      => psram_cs_n_dly,
+        Q1      => open
+    );
+
+   u_iodelay_psram_clk : IODELAY 
+   generic map
+   (
+      C_STATIC_DLY => IODELAY_SETTING(8)
+   )
+   port map
+   (
+        DO      => psram_clk,
+        DF      => open,
+        DI      => psram_clk_dly,
+        SDTAP   => '0',
+        DLYSTEP => 8x"0",
+        VALUE   => '0'
+   );
+
+    oser4_psram_clk : OSER4 port map
+    (
+        PCLK    => clk_sys,
+        FCLK    => clk_fsys,
+        RESET   => rst,
+        TX0     => '0',
+        TX1     => '0',
+        D0      => '0',
+        D1      => clock_ena,
+        D2      => clock_ena,
+        D3      => '0',
+        Q0      => psram_clk_dly,
+        Q1      => open
+    );
+
+   u_iodelay_psram_rwds : IODELAY 
+   generic map
+   (
+      C_STATIC_DLY => IODELAY_SETTING(10)
+   )
+   port map
+   (
+        DO      => oddr_rwds_data,
+        DF      => open,
+        DI      => oddr_rwds_data_dly,
+        SDTAP   => '0',
+        DLYSTEP => 8x"0",
+        VALUE   => '0'
+   );
+
+    oser4_psram_rwds : OSER4 port map
+    (
+        PCLK    => clk_sys,
+        FCLK    => clk_fsys,
+        RESET   => rst,
+        TX0     => oe_rwds_n,
+        TX1     => oe_rwds_n,
+        D0      => rwds_out_rising,
+        D1      => rwds_out_rising,
+        D2      => rwds_out_falling,
+        D3      => rwds_out_falling,
+        Q0      => oddr_rwds_data_dly,
+        Q1      => oddr_rwds_enaN
+    );
+
+   psram_rwds <= oddr_rwds_data when (oddr_rwds_enaN = '0') else 'Z';
+   
+   gdq : for i in 0 to 7 generate
+   begin
+      
+   u_iodelay_dq : IODELAY 
+   generic map
+   (
+      C_STATIC_DLY => IODELAY_SETTING(i)
+   )
+   port map
+   (
+        DO      => oddr_dq_data_dly(i),
+        DF      => open,
+        DI      => oddr_dq_data(i),
+        SDTAP   => '0',
+        DLYSTEP => 8x"0",
+        VALUE   => '0'
+   );
+
+    oser4_dq : OSER4 
+       generic map
+       (
+          HWL => "false",
+          TXCLK_POL => '0'
+       )
+    port map
+    (
+        PCLK    => clk_sys,
+        FCLK    => clk_fsys,
+        RESET   => rst,
+        TX0     => oe_dq_n,
+        TX1     => oe_dq_n,
+        D0      => dq_shiftreg(56 + i),
+        D1      => dq_shiftreg(56 + i),
+        D2      => dq_shiftreg(48 + i),
+        D3      => dq_shiftreg(48 + i),
+        Q0      => oddr_dq_data(i),
+        Q1      => oddr_dq_enaN(i)
+    );
+      psram_dq(i) <= oddr_dq_data_dly(i) when (oddr_dq_enaN(i) = '0') else 'Z';
+/*
+    -- Cleanup L/H from memory sim model
+    process (psram_dq(i)) 
+    begin
+      case psram_dq(i) is
+        when 'L' => psram_dq_o(i) <= '0';
+        when 'H' => psram_dq_o(i) <= '1';
+        when others => psram_dq_o(i) <= psram_dq(i);
+      end case;
+    end process;
+*/
+    -- Register these here to improve timing
+    process (clk_sys)
+    begin
+        if rising_edge(clk_sys) then
+          -- Delay enable by 1 cycle
+            if (rst = '1') then
+                receiving_data  <= '0';
+            else
+                if(rwds_in_Q(2) or rwds_in_Q(0)) then
+                    receiving_data <= '1';
+                else
+                    receiving_data <= '0';
+                end if;
+            end if;
+          
+          case rwds_in_Q is
+            when "0011" => 
+               if (ISSIMU = true) then
+                  if (dq_in_Q1(0) /= '0' and dq_in_Q1(0) /= '1') then
+                     dq_in_adjustL <= x"AB";
+                     dq_in_adjustH <= x"CD";
+                  else
+                     dq_in_adjustL <= dq_in_Q1;
+                     dq_in_adjustH <= dq_in_Q3;
+                  end if;
+               else
+                  dq_in_adjustL <= dq_in_Q0;
+                  dq_in_adjustH <= dq_in_Q2;
+               end if;
+            when "0001" => 
+                dq_in_adjustL <= dq_in_Q0;
+                dq_in_adjustH <= dq_in_Q2; 
+            when "1001" => 
+                dq_in_adjustL <= dq_in_Q0;
+                dq_in_adjustH <= dq_in_Q2;
+            when "0110" => 
+                dq_in_adjustL <= dq_in_Q1;
+                dq_in_adjustH <= dq_in_Q3;
+            when others => 
+                dq_in_adjustL <= dq_in_Q3;
+                dq_in_adjustH <= dq_in_Q2;
+          end case;
+        end if;
+    end process;
+
+    ides4_dq : IDES4 port map
+    (
+        D     => psram_dq(i),
+        PCLK  => clk_sys,
+        FCLK  => clk_fsys,
+        CALIB => '0',
+        RESET => rst,
+        Q0  => dq_in_Q0(i),
+        Q1  => dq_in_Q1(i),
+        Q2  => dq_in_Q2(i),
+        Q3  => dq_in_Q3(i)
+    );
+
+   end generate;
+/*   
+    -- Cleanup L/H from memory sim model
+    process (psram_rwds) 
+    begin
+      case psram_rwds is
+        when 'L' => psram_rwds_o <= '0';
+        when 'H' => psram_rwds_o <= '1';
+        when others => psram_rwds_o <= psram_rwds;
+      end case;
+    end process;
+*/
+   ides4_psram_rwds : IDES4 port map
+   (
+      D     => psram_rwds,
+      PCLK  => clk_sys,
+      FCLK  => clk_fsys,
+      CALIB => '0',
+      RESET => rst,
+      Q0  => rwds_in_Q(0),
+      Q1  => rwds_in_Q(1),
+      Q2  => rwds_in_Q(2),
+      Q3  => rwds_in_Q(3)
+   );
+   
+   ready <= '1' when (state = IDLE and cfg_1_VendorID = 5x"0D") else '0';
+   
+   writeNext <= '1' when (state = WRITING and writeburst = '1' and burst_count > 2) else '0';
+   
+   process (clk_sys)
+   begin
+      if rising_edge(clk_sys) then
+      
+         done        <= '0';
+         dout_valid  <= '0';
+         dq_shiftreg <= dq_shiftreg(47 downto 0) & 16x"0";
+         
+         if (step < 15) then
+            step <= step + 1;
+         end if;
+      
+         if (rst = '1') then
+            state            <= RESET;
+            startup_cnt      <= 0;
+            configread_addr  <= x"0";
+            configwrite_addr <= x"F";
+            step             <= 0;
+            cs_ena_n         <= '1';
+            clock_ena        <= '0';
+            oe_dq_n          <= '1';
+            oe_rwds_n        <= '1';
+         else
+
+            case (state) is
+         
+               when RESET =>
+                  if (startup_cnt < 50000) then
+                     startup_cnt <= startup_cnt + 1;
+                  else
+                     state     <= CONFIGWRITE_NEXT;
+                     step      <= 0;
+                  end if;
+                  
+               when CONFIGWRITE_NEXT =>
+                  if (step >= 8) then
+                     state     <= CONFIGWRITE_START;
+                     cs_ena_n  <= '0';
+                     step      <= 0;
+                  end if;
+               
+               when CONFIGWRITE_START =>
+                  state        <= CONFIGWRITE;
+                  dq_shiftreg  <= x"C0C0000000000000";
+                  oe_dq_n      <= '0';
+                  clock_ena    <= '1';
+                  dq_shiftreg(19 downto 16) <= configwrite_addr;
+                  case (configwrite_addr) is
+                     
+                     when  x"F" =>
+                        dq_shiftreg      <= (others => '1');
+                        
+                     when x"0" =>
+                        dq_shiftreg(15 downto 8) <= "00" & CFG0_LT & std_logic_vector(to_unsigned(READLATENCY - 3,3)) & CFG0_DRIVESTRENGTH;
+                        
+                     when x"4" =>
+                        dq_shiftreg(15 downto 8) <= "0000" & CFG4_RF & CFG4_PASR;   
+                        case (WRITELATENCY) is
+                           when 3 => dq_shiftreg(15 downto 13) <= "000";
+                           when 4 => dq_shiftreg(15 downto 13) <= "100";
+                           when 5 => dq_shiftreg(15 downto 13) <= "010";
+                           when 6 => dq_shiftreg(15 downto 13) <= "110";
+                           when 7 => dq_shiftreg(15 downto 13) <= "001";
+                           when others => null;
+                        end case;
+                        
+                     when x"8" =>
+                        dq_shiftreg(15 downto 8) <= "0000" & CFG8_RBX & CFG8_BT & CFG8_BL;
+                        
+                     when others => null;
+                        
+                  end case;
+                  
+               when CONFIGWRITE =>
+                  if (step = 4) then
+                     
+                     state        <= CONFIGWRITE_NEXT;
+                     clock_ena    <= '0';
+                     oe_dq_n      <= '1';
+                     cs_ena_n     <= '1';
+                     
+                     case (configwrite_addr) is
+                     
+                        when  x"F" =>
+                           configwrite_addr <= x"0";
+                           state            <= RESET;
+                           startup_cnt      <= 0;
+                           
+                        when x"0" =>
+                           configwrite_addr         <= x"4";
+                           
+                        when x"4" =>
+                           configwrite_addr         <= x"8"; 
+                           
+                        when x"8" =>
+                           state                    <= CONFIGREAD_NEXT;
+                           
+                        when others => null;
+                        
+                     end case;
+                     
+                  end if; 
+                  
+               when CONFIGREAD_NEXT =>
+                  if (step >= 8) then
+                     state     <= CONFIGREAD_START;
+                     cs_ena_n  <= '0';
+                     step      <= 0;
+                  end if;
+                  
+               when CONFIGREAD_START =>
+                  state        <= CONFIGREAD;
+                  dq_shiftreg  <= x"4040000000000000";
+                  oe_dq_n      <= '0';
+                  clock_ena    <= '1';
+                  dq_shiftreg(19 downto 16) <= configread_addr;
+                  
+               when CONFIGREAD =>
+                  if (step = 3) then
+                     oe_dq_n      <= '1';
+                  end if;
+                  if (step > 9 and receiving_data = '1') then
+                     
+                     state     <= CONFIGREAD_NEXT;
+                     step      <= 0;
+                     cs_ena_n  <= '1';
+                     clock_ena <= '0';
+   
+                     case (configread_addr) is
+                        when x"0" => 
+                           configread_addr     <= x"1"; 
+                           cfg_0_LT            <= dq_in_adjustL(5);
+                           cfg_0_readLatency   <= dq_in_adjustL(4 downto 2);
+                           cfg_0_driveStrength <= dq_in_adjustL(1 downto 0);
+                           
+                        when x"1" => 
+                           configread_addr <= x"2";
+                           cfg_1_ULP       <= dq_in_adjustL(7);  
+                           cfg_1_VendorID  <= dq_in_adjustL(4 downto 0); 
+                           
+                        when x"2" => 
+                           configread_addr <= x"3";
+                           cfg_2_GB        <= dq_in_adjustL(7);  
+                           cfg_2_DevID     <= dq_in_adjustL(4 downto 3);    
+                           cfg_2_Density   <= dq_in_adjustL(2 downto 0); 
+                           
+                        when x"3" => 
+                           configread_addr <= x"4";
+                           cfg_3_RBXen     <= dq_in_adjustL(7);     
+                           cfg_3_VCC       <= dq_in_adjustL(6);     
+                           cfg_3_SRF       <= dq_in_adjustL(5);  
+                           
+                        when x"4" => 
+                           configread_addr    <= x"8";
+                           cfg_4_writeLatency <= dq_in_adjustL(7 downto 5); 
+                           cfg_4_RF           <= dq_in_adjustL(3); 
+                           cfg_4_PASR         <= dq_in_adjustL(2 downto 0); 
+                           
+                        when x"8" => 
+                           state     <= IDLE;
+                           cfg_8_RBX <= dq_in_adjustL(3); 
+                           cfg_8_BT  <= dq_in_adjustL(2);
+                           cfg_8_BL  <= dq_in_adjustL(1 downto 0);
+                        
+                        when others => null;
+                        
+                     end case;
+                  end if;
+                  
+               when IDLE =>
+                  oe_rwds_n    <= '1';
+                  oe_dq_n      <= '1';
+                  clock_ena    <= '0';
+                  cs_ena_n     <= '1';
+                  writeburst   <= '0';
+                  burst_count  <= burst_length;
+                  addr_nextRow <= std_logic_vector(unsigned(addr(22 downto 10)) + 1);
+                  row_count    <= 9x"1FF" - unsigned(addr(9 downto 1));
+                  if (req_read = '1' or req_write = '1') then
+                     if (req_read = '1') then
+                        state       <= READING;
+                        dq_shiftreg(63 downto 48) <= x"2020";
+                     else
+                        state       <= WRITING;
+                        dq_shiftreg(63 downto 48) <= x"A0A0";
+                     end if;
+                     dq_shiftreg(47 downto 0) <= 9x"0" & addr(22 downto 1) & '0' & 16x"0";
+                     cs_ena_n    <= '0';
+                     clock_ena   <= '1';
+                     oe_dq_n     <= '0';
+                     step        <= 1;
+                  end if;
+                  
+               when READING =>
+                  if (step = 3) then
+                     oe_dq_n <= '1';
+                  elsif (step > 9 and rwds_in_Q(3) /= rwds_in_Q(1)) then
+                     if (burst_count = 1) then
+                        state     <= IDLE;
+                        done      <= '1';
+                        cs_ena_n  <= '1';
+                        clock_ena <= '0';
+                     else
+                        state <= READVAL;
+                     end if;
+                  end if;
+                  
+               when READVAL =>
+                  if (receiving_data = '1') then
+                     dout_valid  <= '1';
+                     dout        <= dq_in_adjustH & dq_in_adjustL;
+                     if (burst_count <= 2) then
+                        state     <= IDLE;
+                        done      <= '1';
+                        cs_ena_n  <= '1';
+                        clock_ena <= '0';
+                     else
+                        burst_count <= burst_count - 2;
+                     end if;
+                  end if;
+               
+               when WRITING =>
+                  if (step = 1 + WRITELATENCY) then
+                     writeburst <= '1';
+                  end if;
+                  if (writeburst = '1') then
+                     oe_dq_n                    <= '0';
+                     oe_rwds_n                  <= '0';
+                     rwds_out_rising            <= '0'; --todo: byte mask together with addr bit 0 in case of single byte write
+                     rwds_out_falling           <= '0'; --todo: byte mask together with addr bit 0 in case of single byte write
+                     dq_shiftreg(63 downto 48)  <= din(7 downto 0) & din(15 downto 8); 
+                     
+                     row_count <= row_count - 1;
+                     if (row_count = 0) then
+                        state      <= WRITE_NEWROW;
+                        writeburst <= '0';
+                        step       <= 0;
+                     end if;
+                     
+                     if (burst_count <= 2) then
+                        state                   <= IDLE;
+                        done                    <= '1';
+                     else
+                        burst_count <= burst_count - 2;
+                     end if;
+                  end if;
+                  
+               when WRITE_NEWROW =>
+                  oe_dq_n     <= '1';
+                  oe_rwds_n   <= '1';
+                  clock_ena   <= '0';
+                  cs_ena_n    <= '1';
+                  if (step = 4) then
+                     state       <= WRITING;
+                     dq_shiftreg(63 downto 48) <= x"A0A0";
+                     dq_shiftreg(47 downto 0) <= 9x"0" & addr_nextRow & 10x"0" & 16x"0";
+                     cs_ena_n    <= '0';
+                     clock_ena   <= '1';
+                     oe_dq_n     <= '0';
+                     step        <= 1;
+                  end if;
+                  
+         
+            end case;
+            
+         end if;
+      
+      end if;
+   end process;
+   
+end architecture;
+
+

ModRetro_oss-chromatic-console-fpga/esp32t/src/rtl/BSP/ST7785_init.v

@@ -0,0 +1,181 @@
+module ST7785_init #(parameter ISSIMU=0)
+(
+    input       clk,
+    input       reset,
+    output      LCD_SCK,
+    output reg  LCD_CS,
+    output reg  LCD_SDA_SDI,
+    output reg  LCD_RST,
+    output reg  LCD_INIT_DONE
+);
+
+    parameter CLK_DIV_2N = 6;
+
+    wire clk_out_ne;
+    clock_div #(
+        .DIV_2N(CLK_DIV_2N)) 
+    c1 (
+        .clk_in(clk), 
+        .reset(reset),
+        .clk_out(sck),
+        .clk_out_ne(clk_out_ne)
+    );
+    
+    reg       cs;
+    assign LCD_SCK = ~cs ? sck : 1'd0;
+
+    localparam DATA_MAX_CNT = 127;
+    
+    wire[23:0] RESETSTART = ISSIMU ? 2000 : 0;
+    wire[23:0] RESETEND   = ISSIMU ? 3000 : 80000;
+    wire[23:0] DELAYMAX   = ISSIMU ? 5000 : 90000;
+    wire[17:0] DELAYEND   = ISSIMU ? 18'd500 : 18'd2560;
+
+    reg[8:0] sets[127:0] /* synthesis syn_romstyle = "distributed_rom" */;
+    reg[6:0] data_cnt;
+    reg[4:0] bit_cnt;
+    reg[23:0] delay_cnt;
+
+    initial begin
+        $readmemb("regs.bin", sets);
+    end
+
+    always @(posedge clk or posedge reset) begin
+        if(reset)
+            LCD_RST <= 1'd1;
+        else
+            if(clk_out_ne)
+                case (delay_cnt)
+                    RESETSTART: LCD_RST <= 0;
+                    RESETEND  : LCD_RST <= 1;
+                endcase
+    end
+
+    always @(posedge clk)
+        if(clk_out_ne)
+            if ((data_cnt < DATA_MAX_CNT) && (delay_cnt == DELAYMAX)) 
+            begin
+                if (bit_cnt < 9)
+                    bit_cnt <= bit_cnt + 1'd1;
+                else 
+                    bit_cnt <= 'd0;
+            end
+            else
+                bit_cnt <= 'd0;
+                
+    reg [8:0] txdata;   
+    always@(posedge clk)
+        if(clk_out_ne)
+            txdata <= sets[data_cnt];
+        
+    reg [17:0] delay_cnt2;
+        
+    reg [7:0] datasr;
+    reg [7:0] max_cnt;
+    always@(posedge clk)
+    begin
+        LCD_CS <= cs;
+    end
+    
+    always@(posedge clk)
+        if(clk_out_ne)
+        begin
+            if(delay_cnt != DELAYMAX)
+            begin
+                data_cnt    <= 'd0;
+                datasr      <= 'd0;
+                cs          <= 'd1;
+                LCD_SDA_SDI <= 'd0;
+                delay_cnt2   <= 'd0;
+                max_cnt     <= DATA_MAX_CNT - 'd4;
+            end
+            else
+                if(bit_cnt == 0)
+                begin
+                    if (data_cnt < max_cnt)     
+                    begin
+                        cs <= 1'd0;
+                        datasr <= txdata[7:0];
+                        LCD_SDA_SDI <= txdata[8];
+                        data_cnt <= data_cnt + 1'd1;
+                    end
+                    else
+                    begin
+                        cs <= 1'd1;
+                        if(delay_cnt2 < DELAYEND)
+                            delay_cnt2 <= delay_cnt2 + 1'd1;
+                        else
+                            max_cnt <= DATA_MAX_CNT;
+                    end
+                end
+                else
+                begin
+                    if(bit_cnt < 9)
+                    begin
+                        datasr <= {datasr[6:0], 1'd0};
+                        LCD_SDA_SDI <= datasr[7];
+                    end
+                    else
+                    begin
+                        cs <= 1'd1;
+                    end
+                end
+        end
+
+    always @(posedge clk or posedge reset)
+        if(reset)
+            delay_cnt <= 'd0;
+        else
+            if(clk_out_ne)
+                if (delay_cnt < DELAYMAX)
+                    delay_cnt <= delay_cnt + 1'd1;
+
+    always@(posedge clk or posedge reset)
+        if(reset)
+            LCD_INIT_DONE <= 1'd0;
+        else
+            if(data_cnt < DATA_MAX_CNT)
+                LCD_INIT_DONE <= 1'd0;
+            else
+                LCD_INIT_DONE <= 1'd1;
+
+endmodule
+
+module clock_div
+    #(
+        parameter SIZE = 8,
+        parameter DIV_2N = 1
+    )
+    (
+        input clk_in,
+        input reset,
+        output reg clk_out = 'd0,
+        output reg clk_out_ne,
+        output reg clk_out_pe
+    );
+
+    reg [SIZE - 1:0] counter = DIV_2N - 1;
+
+    always @(posedge clk_in) begin
+        if(reset)
+        begin
+            counter <= 'd0;
+            clk_out <= 'd0;
+            clk_out_ne <= 1'd0;
+            
+        end
+        else        
+        begin
+            clk_out_ne <= 1'd0;
+
+            if (counter == 0) begin
+                counter <= DIV_2N - 1;
+                clk_out <= !clk_out;
+                if(~clk_out)
+                    clk_out_ne <= 1'd1;
+            end
+            else
+                counter <= counter - 'd1;
+        end
+    end
+endmodule

ModRetro_oss-chromatic-console-fpga/esp32t/src/rtl/BSP/ST7785_panel_master.v

@@ -0,0 +1,267 @@
+module ST7785_panel_master(
+    input               gClk,
+    input               nRST,
+
+    input               hClk,
+    input       [17:0]  hColorPixel,
+    input       [17:0]  hColorPixelUVC,
+    input               lcd_on,
+    input               hVsync,
+    input               hHsync,
+    input               hValid,
+    input               LCD_EN,
+    output  reg         LCD_DE,
+    output  reg         LCD_HSYNC,
+    output  reg         LCD_VSYNC,
+    output  reg         LCD_GENLOCK,
+    output  reg [5:0]   LCD_DB,
+    output  reg         LCD_ENABLE_UVC,
+    output  reg [17:0]  LCD_DB_UVC
+);
+    
+    parameter       H_Lw             = 16'd30; 
+    parameter       H_Pixel_Valid    = 16'd720; 
+    parameter       H_FrontPorch     = 16'd129;
+    parameter       H_BackPorch      = 16'd32;  
+
+    parameter       PixelForHS       = H_Lw + H_Pixel_Valid + H_FrontPorch + H_BackPorch;
+    
+    parameter       V_Lw             = 16'd2;
+    parameter       V_Pixel_Valid    = 16'd144;
+    parameter       V_FrontPorch     = 16'd2; // was 64
+    parameter       V_BackPorch      = 16'd10;
+
+    parameter       PixelForVS       = V_Pixel_Valid + V_FrontPorch + V_BackPorch;
+
+    reg                 gLcdOn_r1;
+    reg                 gLcdOn_r2;
+    always@(posedge gClk)
+    begin
+        gLcdOn_r1 <= lcd_on;
+        gLcdOn_r2 <= gLcdOn_r1;
+    end
+
+    reg                 gVs_r1;
+    reg                 gVs_r2;
+    always@(posedge gClk)
+    begin
+        gVs_r1 <= hVsync;
+        gVs_r2 <= gVs_r1;
+    end
+
+    reg hgVs_r1;
+    reg hgVs_r2;
+    always@(posedge hClk)
+    begin
+        hgVs_r1 <= hVsync;
+        hgVs_r2 <= hgVs_r1;
+    end
+    wire hGbVsync = hgVs_r1 & ~hgVs_r2;
+    
+    reg [15:0] hs_sr;
+    always@(posedge hClk)
+        hs_sr <= {hs_sr[14:0], hHsync};
+    wire gbhsync = hs_sr[15] & ~hs_sr[14];
+    reg valid_r1;
+    always@(posedge hClk)
+        valid_r1 <= hValid;
+        
+
+    wire [17:0] color_pixeluvc;
+    wire [17:0] color_pixelp;
+    
+    localparam DEPTH = 1024;
+    reg [35:0] lineBuffer [DEPTH-1:0];
+    reg [35:0]  lineBuffer_q;
+
+    reg [9:0]   lineBuffer_wa;
+    reg [7:0]   lineBuffer_wrCount;
+    reg [9:0]   lineBuffer_ra;
+    reg [7:0]   lineBuffer_rdCount;
+    
+    always@(posedge hClk)
+    begin
+        if(hGbVsync)
+        begin
+            lineBuffer_wrCount <= 'd0;
+            lineBuffer_wa      <= 'd0;
+        end
+        else
+            if(gbhsync)
+                lineBuffer_wrCount <= 'd0;
+            else
+                if(hValid)
+                    if(lineBuffer_wrCount <= 8'd159)
+                    begin
+                        lineBuffer_wrCount  <= lineBuffer_wrCount + 1'd1;
+                        if(lineBuffer_wa < DEPTH - 1'd1)
+                            lineBuffer_wa       <= lineBuffer_wa + 1'd1;
+                        else
+                            lineBuffer_wa       <= 'd0;
+                    end
+    end
+    
+    reg         [11:0]  H_PixelCount;
+    reg         [11:0]  V_PixelCount;
+    reg         [15:0]  frameCount;
+    wire  LCD_DEI =    ( H_PixelCount > H_BackPorch + H_Lw ) && ( H_PixelCount <= H_Pixel_Valid + H_BackPorch + H_Lw ) && (V_PixelCount < V_Pixel_Valid + V_Lw + V_FrontPorch) && (V_PixelCount >= V_Lw + V_FrontPorch);      
+
+    always@(posedge hClk)
+        if(hValid&&(lineBuffer_wrCount <= 8'd159))
+            lineBuffer[lineBuffer_wa]  <=  {hColorPixelUVC, hColorPixel};
+
+    reg [1:0] phase;
+    reg [7:0] hoffset;
+    localparam OFFSET = 41;
+    reg pGbVsync;
+    reg pGbVsync_r1;
+    wire pGbVsyncRising = pGbVsync & ~pGbVsync_r1;
+    always@(posedge gClk)
+    begin
+        pGbVsync <= hVsync;
+        pGbVsync_r1 <= pGbVsync;
+    end
+    
+    always@(posedge gClk)
+    begin
+        if(pGbVsyncRising)
+        begin
+            lineBuffer_ra       <= 'd0;
+            lineBuffer_rdCount  <= 'd0;
+            phase               <= 'd2;
+        end
+        else
+            if(~LCD_HSYNC)
+            begin
+                phase <= 'd2;
+                hoffset <= 'd0;
+                lineBuffer_rdCount <= 'd0;
+            end
+            else
+            begin
+                if(phase < 3'd2)
+                    phase <= phase + 1'd1;
+                else
+                    phase <= 'd0;
+
+                if((LCD_DEI) && LCD_VSYNC && (phase == 'd2))
+                    if(hoffset < OFFSET)
+                        hoffset <= hoffset + 1'd1;
+                    
+                if((LCD_DEI) && (V_PixelCount >= V_Lw + V_FrontPorch) && (phase == 'd1))
+                begin
+                    if(hoffset >= OFFSET)
+                        if(lineBuffer_rdCount <= 8'd159)
+                        begin
+                            if(lineBuffer_ra < DEPTH - 1'd1)
+                                lineBuffer_ra <= lineBuffer_ra + 1'd1;
+                            else
+                                lineBuffer_ra <= 'd0;
+                            lineBuffer_rdCount <= lineBuffer_rdCount + 1'd1;
+                        end
+                end
+            end
+    end
+                
+    always@(posedge gClk)
+        lineBuffer_q <= lineBuffer[lineBuffer_ra];
+
+    assign color_pixeluvc = lineBuffer_q[35:18];
+    assign color_pixelp = lineBuffer_q[17:0];
+
+    localparam FINE_OFFSET = 11'd418;
+    reg [10:0] fineDelay;
+    // LCD scanout is several rows behind the emulator
+    // Need to delay the falling edge of lcd_on
+    //
+    // When we get falling edge of lcd_on, scanout remaining rows
+    // then enter 
+    reg lcd_on_aligned;
+    reg lcd_on_aligned_r1;
+    reg lcd_on_aligned_r2;
+    wire frameDone = (V_PixelCount >= V_Pixel_Valid + V_Lw + V_FrontPorch)&&~LCD_HSYNC;    
+    always@(posedge gClk)
+        if((gVs_r1 & ~gVs_r2)|(lcd_on_aligned_r1 & ~lcd_on_aligned_r2))
+            fineDelay <= 'd0;
+        else
+            if(fineDelay != FINE_OFFSET)
+                fineDelay <= fineDelay + 1'd1;
+
+    reg delayed;
+    always@(posedge gClk)
+        delayed <= (fineDelay == (FINE_OFFSET - 1'd1)) ? 1'd1 : 1'd0;
+
+    always@(posedge gClk)
+    begin
+        if((V_PixelCount == 0) || frameDone)
+        lcd_on_aligned <= lcd_on;
+        lcd_on_aligned_r1 <= lcd_on_aligned;
+        lcd_on_aligned_r2 <= lcd_on_aligned_r1;
+    end
+
+    always @(posedge gClk)begin
+        if( !nRST || delayed || ~lcd_on_aligned) begin
+            V_PixelCount      <=  0;
+            H_PixelCount      <=  'd0;
+            frameCount        <=  16'd0;
+        end
+        else 
+            if(  H_PixelCount == PixelForHS )
+            begin
+            V_PixelCount      <=  V_PixelCount + 1'b1;
+            H_PixelCount      <=  'd0;
+            end
+        else if(  V_PixelCount >= (PixelForVS + V_Lw) ) begin
+            V_PixelCount      <=  'd0;
+            H_PixelCount      <=  'd0;
+            frameCount        <=  frameCount + 1'd1;
+            end
+        else begin
+            H_PixelCount      <=  H_PixelCount + 1'b1;
+        end
+    end
+      
+    reg LCD_DEI_r1;
+    reg LCD_DEI_r2;
+    reg LCD_VSYNC_r1;
+    always@(posedge gClk)
+    begin
+        LCD_DEI_r1 <= LCD_DEI;
+        LCD_DEI_r2 <= LCD_DEI_r1;
+        LCD_DE <= LCD_DEI_r2;
+        LCD_HSYNC <= H_PixelCount < H_Lw ? 1'b0 : 1'b1;
+        LCD_VSYNC <= (V_PixelCount >= 0)&&(V_PixelCount < V_Lw)  ? 1'b0 : 1'b1;
+        LCD_VSYNC_r1 <= LCD_VSYNC;
+        if(LCD_VSYNC & ~LCD_VSYNC_r1)
+            LCD_GENLOCK <= ~LCD_GENLOCK;
+
+        if((hoffset >= OFFSET) && lcd_on_aligned)
+        begin
+            if(LCD_EN)
+            begin
+                if(phase == 2)
+                    LCD_DB <= color_pixelp[17:12]; // Blue
+                if(phase == 1)
+                    LCD_DB <= color_pixelp[11:6]; // Green
+                if(phase == 0)
+                    LCD_DB <= color_pixelp[5:0]; // Red
+
+                LCD_DB_UVC <= color_pixeluvc;
+                LCD_ENABLE_UVC <= LCD_DEI_r2;
+            end
+            else
+            begin
+                LCD_DB          <= {6{1'b1}};
+                LCD_DB_UVC      <= {18{1'b1}};
+                LCD_ENABLE_UVC  <= LCD_DEI_r2;
+            end
+        end
+        else
+        begin
+            LCD_DB <= 'd0;
+            LCD_DB_UVC <= 'd0;
+            LCD_ENABLE_UVC <= 1'd0;
+        end
+    end
+
+endmodule

ModRetro_oss-chromatic-console-fpga/esp32t/src/rtl/BSP/adc_wrap.v

@@ -0,0 +1,85 @@
+// adc_wrap.v
+
+module adc_wrap(
+    input               clk,
+    input   reset_n,
+    input               hAdcReq_ext,
+    output  reg [13:0]  hAdcValue_r1,
+    output  reg         hAdcReady_r1,
+    input   VBAT_ADC_P,
+    input   VBAT_ADC_N
+);
+
+    wire hAdcReady;
+    wire [13:0] hAdcValue;
+    reg [1:0] hAdcState;
+
+    always@(posedge clk)
+    begin
+        if((hAdcState == 2'd2)&&hAdcReady)
+        begin
+            hAdcReady_r1    <=  1'd1;
+            hAdcValue_r1    <=  hAdcValue;
+        end
+        else
+            hAdcReady_r1    <=  1'd0;
+    end
+    
+    wire [7:0] mdrp_rdata_o;
+
+    TLVDS_IBUF_ADC u_IBUF_ADC(
+        .I(VBAT_ADC_P),
+        .IB(VBAT_ADC_N),
+        .ADCEN(1'd1)
+    );
+
+
+    wire adcen_i = reset_n;
+    wire hAdcReq = (hAdcState == 2'd1);
+
+    always@(posedge clk)
+        if(~reset_n)
+            hAdcState <= 'd0;
+        else
+            case(hAdcState)
+            2'd0 :
+                if(hAdcReq_ext)
+                    hAdcState <= 2'd1;
+            2'd1 : 
+                if(~hAdcReady)
+                    hAdcState <= 2'd2;
+            2'd2 :
+            begin            
+                if(hAdcReady)
+                hAdcState <= 2'd3;
+                else
+                    if(hAdcReq_ext)
+                        hAdcState <= 2'd1;
+            end
+            2'd3 :
+                hAdcState <= 2'd0;
+            endcase
+
+    reg adcen;
+    always@(posedge clk or negedge reset_n)
+        if(~reset_n)
+            adcen <= 1'd0;
+        else
+            adcen <= 1'd1;
+    Gowin_ADC u_Gowin_ADC (
+        .clk(clk), //input clk
+        .drstn(adcen_i ), //input drstn
+        .adcrdy(hAdcReady), //output adcrdy
+        .adcvalue(hAdcValue), //output [13:0] adcvalue
+        .vsenctl(3'b010), //input [2:0] vsenctl
+        .adcen(adcen), //input adcen
+        .adcreqi(hAdcReq), //input adcreqi
+        .adcmode(1'd1), //input adcmode 1 = Voltage, 0 = temperature
+        .mdrp_clk(1'd0), //input mdrp_clk
+        .mdrp_rdata(mdrp_rdata_o), //output [7:0] mdrp_rdata
+        .mdrp_wdata(8'd0), //input [7:0] mdrp_wdata
+        .mdrp_a_inc(1'd0), //input mdrp_a_inc
+        .mdrp_opcode(2'd0) //input [1:0] mdrp_opcode
+    );
+
+endmodule

ModRetro_oss-chromatic-console-fpga/esp32t/src/rtl/BSP/aud_system_top.v

@@ -0,0 +1,154 @@
+// aud_system_top.v
+
+module aud_system_top(
+    input               gClk,
+    input               hClk,
+    input               reset_n,
+    input   [15:0]      left,
+    input   [15:0]      right,
+    input               software_mute,
+
+    output  [7:0]       volume,
+    output              hHeadphones,
+    output  [7:0]       pmic_sys_status,
+
+    output              AUD_BCLK,
+    output              AUD_DIN,
+    input               AUD_DOUT,
+    output              AUD_MCLK,
+    output              AUD_RESET,
+    output   reg        AUD_WCLK,
+
+    inout               SCL,
+    inout               SDA
+);
+
+    reg [31:0] stereo_sr;
+    reg [4:0] count;
+
+    reg gClkHalf;
+    always@(posedge gClk)
+        gClkHalf <= ~gClkHalf;
+
+    wire [7:0] hpgpio;
+    assign hHeadphones = hpgpio[1];
+
+    wire mute = (software_mute | volume > 8'h76);
+
+    wire [15:0] left_m =  mute ? 16'd0 : -left;
+    wire [15:0] right_m = mute ? 16'd0 : -right;
+
+    reg [16:0] gMonoSpeaker;
+    always @(posedge gClk)
+        if(reset_n)
+            gMonoSpeaker <= left_m + right_m;
+
+    always @(posedge gClkHalf or negedge reset_n) begin
+        if (~reset_n) begin
+            count <= 5'd0;
+        end
+        else
+        begin
+            if (count == 5'd0) begin
+                count <= 5'd31;
+                AUD_WCLK <= 1'b1;
+                stereo_sr <= ~hHeadphones ? {16'd0,gMonoSpeaker[16:1]} :
+                    { right_m[15:0],left_m[15:0] };
+            end
+            else begin
+                count <= count - 1'd1;
+                if(count == 5'd16)
+                    AUD_WCLK <= 1'b0;
+                stereo_sr <= {stereo_sr[30:0], 1'b0};
+            end
+        end
+    end
+
+    assign AUD_MCLK     = gClk;
+    assign AUD_BCLK     = ~gClkHalf;
+    assign AUD_DIN      = stereo_sr[31];
+    assign AUD_RESET    = reset_n;
+
+    parameter I2C_DATA_WIDTH = 8;
+    parameter REGISTER_WIDTH = 8;
+    parameter ADDRESS_WIDTH = 7;
+
+    wire    [I2C_DATA_WIDTH-1:0]     i2c_miso_data;  // output
+    wire                             i2c_busy;       // output
+
+    wire                             tlv320_init_done;
+    wire                             tlv320_i2c_enable;
+    wire                             tlv320_i2c_read_write;
+    wire     [I2C_DATA_WIDTH-1:0]    tlv320_i2c_mosi_data;
+    wire     [REGISTER_WIDTH-1:0]    tlv320_i2c_register_address;
+    wire     [ADDRESS_WIDTH-1:0]     tlv320_i2c_device_address;
+
+    wire                             pol_i2c_enable;
+    wire                             pol_i2c_read_write;
+    wire     [I2C_DATA_WIDTH-1:0]    pol_i2c_mosi_data;
+    wire     [REGISTER_WIDTH-1:0]    pol_i2c_register_address;
+    wire     [ADDRESS_WIDTH-1:0]     pol_i2c_device_address;
+
+    wire                             i2c_enable = tlv320_init_done ? pol_i2c_enable : tlv320_i2c_enable;
+    wire                             i2c_read_write = tlv320_init_done ? pol_i2c_read_write : tlv320_i2c_read_write;
+    wire     [I2C_DATA_WIDTH-1:0]    i2c_mosi_data = tlv320_init_done ? pol_i2c_mosi_data : tlv320_i2c_mosi_data;
+    wire     [REGISTER_WIDTH-1:0]    i2c_register_address = tlv320_init_done ? pol_i2c_register_address : tlv320_i2c_register_address;
+    wire     [ADDRESS_WIDTH-1:0]     i2c_device_address = tlv320_init_done ? pol_i2c_device_address : tlv320_i2c_device_address;
+
+    // Initializes the Audio codec
+    tlv320_init u_tlv320_init(
+        .pclk(hClk),
+        .vb_rst(~reset_n),
+        .i2c_busy(i2c_busy),
+        .tlv320_init_done(tlv320_init_done),
+
+        .i2c_enable(tlv320_i2c_enable),
+        .i2c_read_write(tlv320_i2c_read_write),
+        .i2c_mosi_data(tlv320_i2c_mosi_data),
+        .i2c_register_address(tlv320_i2c_register_address),
+        .i2c_device_address(tlv320_i2c_device_address)
+    );
+
+    polling_master u_pol_master(
+        .clk(hClk),
+        .rst(~reset_n),
+        .i2c_busy(i2c_busy),
+        .enable(tlv320_init_done),
+        .mute(software_mute),
+
+        .volume(volume),
+        .gpio(hpgpio),
+        .pmic_sys_status(pmic_sys_status),
+
+        .i2c_enable(pol_i2c_enable),
+        .i2c_miso_data(i2c_miso_data),
+        .i2c_read_write(pol_i2c_read_write),
+        .i2c_mosi_data(pol_i2c_mosi_data),
+        .i2c_register_address(pol_i2c_register_address),
+        .i2c_device_address(pol_i2c_device_address)
+    );
+
+    i2c_master #(
+        .DATA_WIDTH(I2C_DATA_WIDTH),
+        .REGISTER_WIDTH(REGISTER_WIDTH),
+        .ADDRESS_WIDTH(ADDRESS_WIDTH)
+    )
+    i2c_master_inst(
+        .clock                  (hClk),
+        .reset_n                (reset_n),
+        .enable                 (i2c_enable),
+        .read_write             (i2c_read_write),
+        .mosi_data              (i2c_mosi_data),
+        .register_address       (i2c_register_address),
+        .device_address         (i2c_device_address),
+        .divider                (16'd20),
+
+        .miso_data              (i2c_miso_data),
+        .busy                   (i2c_busy),
+
+        .external_serial_data   (SDA),
+        .external_serial_clock  (SCL)
+    );
+
+
+endmodule

ModRetro_oss-chromatic-console-fpga/esp32t/src/rtl/BSP/button_debounce.v

@@ -0,0 +1,42 @@
+module button_debouncer 
+(
+   input      clk,              
+   input      unfiltered, 
+   output reg filtered
+);
+
+   parameter HIGHBIT = 14;
+   
+   reg [HIGHBIT:0] count;
+   reg button_state;
+
+   reg [2:0] input_sampling; 
+
+   always @(posedge clk) begin
+      input_sampling <= {input_sampling[1:0], unfiltered};
+      
+      if (~filtered) begin
+         if (~input_sampling[2]) begin 
+            count <= 'd0;
+         end else if (~count[HIGHBIT]) begin
+            count <= count + 1;
+         end
+         if (count[HIGHBIT]) begin
+            filtered <= 1'b1;
+            count <= 'd0;
+         end
+      end else begin
+         if (input_sampling[2]) begin 
+            count <= 'd0;
+         end else if (~count[HIGHBIT]) begin
+            count <= count + 1;
+         end
+         if (count[HIGHBIT]) begin
+            filtered <= 1'b0;
+            count <= 'd0;
+         end
+      end
+      
+   end
+
+endmodule

ModRetro_oss-chromatic-console-fpga/esp32t/src/rtl/BSP/gb_burst_write.v

@@ -0,0 +1,70 @@
+// gb_burst_write.v
+
+// Converts GB video data into a burst write to PSRAM
+module gb_burst_write(
+    input               hClk,
+    input               hVsync,
+    input               hNewLine,
+    input   [22:0]      hAddress,
+    input               hWrite,
+    input   [15:0]      hData,
+                        
+    input               xClk,
+    input               xRdEn,
+    input               xRamReady,
+    output  reg         xMcuReqWrite,
+                        
+    output  [15:0]      xDout,
+    output  reg [22:0]  xAddress
+);
+
+    reg hLineToggle = 0;
+    reg hRamReady = 0;
+
+    always@(posedge hClk)
+    begin
+        if (hNewLine) begin
+            hRamReady   <= xRamReady;
+            hLineToggle <= ~hLineToggle;
+        end
+    end
+
+    reg hVsync_r1;
+    always@(posedge hClk)
+        hVsync_r1 <= hVsync;
+        
+    wire fifo_rst = ~hVsync_r1 & hVsync;
+
+    wire fifo_empty;
+    wire fifo_full;
+    wire fifo_almost_full;
+    fifo1k u_fifo1k(
+        .Data(hData), //input [15:0] Data
+        .WrReset(fifo_rst), //input WrReset
+        .RdReset(fifo_rst), //input RdReset
+        .WrClk(hClk), //input WrClk
+        .RdClk(xClk), //input RdClk
+        .WrEn(hWrite & hRamReady), //input WrEn
+        .RdEn(xRdEn | xMcuReqWrite), //input RdEn
+        .Q(xDout), //output [15:0] Q
+        .Almost_Full(fifo_almost_full), //output Almost_Full
+        .Empty(fifo_empty), //output Empty
+        // Full is on the write clock domain
+        // Won't update when QSPI CS is high
+        .Full(fifo_full) //output Full
+    );
+    
+    reg [3:0] xLine_sr;
+    always@(posedge xClk)
+        xLine_sr <= {xLine_sr[2:0], hLineToggle};
+    
+    always@(posedge xClk)
+    begin
+        xMcuReqWrite <= 1'd0;
+        if(xLine_sr[3] != xLine_sr[2]) begin
+            xMcuReqWrite <= xRamReady && (~fifo_empty);
+            xAddress     <= hAddress[22:0];
+        end
+    end
+    
+endmodule

ModRetro_oss-chromatic-console-fpga/esp32t/src/rtl/BSP/i2c_master.sv

@@ -0,0 +1,634 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company:  www.circuitden.com
+// Engineer: Artin Isagholian
+//           artinisagholian@gmail.com
+// 
+// Create Date: 01/20/2021 05:47:22 PM
+// Design Name: 
+// Module Name: i2c_master
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+module i2c_master#(
+    parameter DATA_WIDTH      = 16,
+    parameter REGISTER_WIDTH  = 16,
+    parameter ADDRESS_WIDTH   = 7
+)(
+    input   wire                            clock,
+    input   wire                            reset_n,
+    input   wire                            enable,
+    input   wire                            read_write,
+    input   wire    [DATA_WIDTH-1:0]        mosi_data,
+    input   wire    [REGISTER_WIDTH-1:0]    register_address,
+    input   wire    [ADDRESS_WIDTH-1:0]     device_address,
+    input   wire    [15:0]                  divider,
+    output  reg     [DATA_WIDTH-1:0]        miso_data,
+    output  reg                             busy,
+    inout                                   external_serial_data,
+    inout                                   external_serial_clock
+);
+
+        localparam  S_IDLE                  =   15'b100000000000000;
+        localparam  S_START                 =   15'b010000000000000;
+        localparam  S_WRITE_ADDR_W          =   15'b001000000000000;
+        localparam  S_CHECK_ACK             =   15'b000100000000000;
+        localparam  S_WRITE_REG_ADDR        =   15'b000010000000000;
+        localparam  S_RESTART               =   15'b000001000000000;
+        localparam  S_WRITE_ADDR_R          =   15'b000000100000000;
+        localparam  S_READ_REG              =   15'b000000010000000;
+        localparam  S_SEND_NACK             =   15'b000000001000000;
+        localparam  S_SEND_STOP             =   15'b000000000100000;
+        localparam  S_WRITE_REG_DATA        =   15'b000000000010000;
+        localparam  S_WRITE_REG_ADDR_MSB    =   15'b000000000001000;
+        localparam  S_WRITE_REG_DATA_MSB    =   15'b000000000000100;
+        localparam  S_READ_REG_MSB          =   15'b000000000000010;
+        localparam  S_SEND_ACK              =   15'b000000000000001;
+
+        reg [14:0]                      state;
+        reg [14:0]                      _state;
+        reg [14:0]                      post_state;
+        reg [14:0]                      _post_state;
+
+reg                             serial_clock;
+logic                           _serial_clock;
+reg     [ADDRESS_WIDTH:0]       saved_device_address;
+logic   [ADDRESS_WIDTH:0]       _saved_device_address;
+reg     [REGISTER_WIDTH-1:0]    saved_register_address;
+logic   [REGISTER_WIDTH-1:0]    _saved_register_address;
+reg     [DATA_WIDTH-1:0]        saved_mosi_data;
+logic   [DATA_WIDTH-1:0]        _saved_mosi_data;
+reg     [1:0]                   process_counter;
+logic   [1:0]                   _process_counter;
+reg     [7:0]                   bit_counter;
+logic   [7:0]                   _bit_counter;
+reg                             serial_data;
+logic                           _serial_data;
+reg                             post_serial_data;
+logic                           _post_serial_data;
+reg                             last_acknowledge;
+logic                           _last_acknowledge;
+logic                           _saved_read_write;
+reg                             saved_read_write;
+reg     [15:0]                  divider_counter;
+logic   [15:0]                  _divider_counter;
+reg                             divider_tick;
+logic   [DATA_WIDTH-1:0]        _miso_data;
+logic                           _busy;
+logic                           serial_data_output_enable;
+logic                           serial_clock_output_enable;
+
+
+assign external_serial_clock    =   (serial_clock_output_enable)  ?   serial_clock  :   1'bz;
+assign external_serial_data     =   (serial_data_output_enable)   ?   serial_data   :   1'bz;
+
+always_comb begin
+    _state                  =   state;
+    _post_state             =   post_state;
+    _process_counter        =   process_counter;
+    _bit_counter            =   bit_counter;
+    _last_acknowledge       =   last_acknowledge;
+    _miso_data              =   miso_data;
+    _saved_read_write       =   saved_read_write;
+    _busy                   =   busy;
+    _divider_counter        =   divider_counter;
+    _saved_register_address =   saved_register_address;
+    _saved_device_address   =   saved_device_address;
+    _saved_mosi_data        =   saved_mosi_data;
+    _serial_data            =   serial_data;
+    _serial_clock           =   serial_clock;
+    _post_serial_data       =   post_serial_data;
+
+    if (divider_counter == divider) begin
+        _divider_counter    =   0;
+        divider_tick        =   1;
+    end
+    else begin
+        _divider_counter    =   divider_counter + 1;
+        divider_tick        =   0;
+    end
+
+    if ((state!=S_IDLE) && (state!=S_CHECK_ACK) && (state!=S_READ_REG) && (state!=S_READ_REG_MSB)) begin
+        serial_data_output_enable   =   1;
+    end
+    else begin
+        serial_data_output_enable   =   0;
+    end
+
+    if (state!=S_IDLE && process_counter!=1 && process_counter!=2) begin
+        serial_clock_output_enable   =   1;
+    end
+    else begin
+        serial_clock_output_enable   =   0;
+    end
+
+    case (state)
+        S_IDLE: begin
+            _process_counter        =   0;
+            _bit_counter            =   0;
+            _last_acknowledge       =   0;
+            _busy                   =   0;
+            _saved_read_write       =   read_write;
+            _saved_register_address =   register_address;
+            _saved_device_address   =   {device_address,1'b0};
+            _saved_mosi_data        =   mosi_data;
+            _serial_data            =   1;
+            _serial_clock           =   1;
+
+            if (enable) begin
+                _state      =   S_START;
+                _post_state =   S_WRITE_ADDR_W;
+                _busy       =   1;
+            end
+        end
+        S_START: begin
+            if (divider_tick) begin
+                case (process_counter)
+                    0: begin
+                        _process_counter    =   1;
+                    end
+                    1: begin
+                        _serial_data        =   0;
+                        _process_counter    =   2;
+                    end
+                    2:  begin
+                        _bit_counter        =   8;
+                        _process_counter    =   3;
+                    end
+                    3:  begin
+                        _serial_clock       =   0;
+                        _process_counter    =   0;
+                        _state              =   post_state;
+                        _serial_data        =   saved_device_address[ADDRESS_WIDTH];
+                    end
+                endcase
+            end
+        end
+        S_WRITE_ADDR_W: begin
+            if (divider_tick) begin
+                case (process_counter)
+                    0: begin
+                        _serial_clock       =   1;
+                        _process_counter    =   1;
+                    end
+                    1: begin
+                        if (external_serial_clock == 1) begin
+                            _process_counter    =   2;
+                        end
+                    end
+                    2: begin
+                        _serial_clock       =   0;
+                        _bit_counter        =   bit_counter -   1;
+                        _process_counter    =   3;
+                    end
+                    3: begin
+                        if (bit_counter == 0) begin
+                            _post_serial_data   =   saved_register_address[REGISTER_WIDTH-1];
+
+                            if (REGISTER_WIDTH == 16) begin
+                                _post_state =   S_WRITE_REG_ADDR_MSB;
+                            end
+                            else begin
+                                _post_state =   S_WRITE_REG_ADDR;
+                            end
+
+                            _state          =   S_CHECK_ACK;
+                            _bit_counter    =   8;
+                        end
+                        else begin
+                            _serial_data    =   saved_device_address[bit_counter-1];
+                        end
+                        _process_counter    =   0;
+                    end
+                endcase
+            end
+        end
+        S_CHECK_ACK: begin
+            if (divider_tick) begin
+                case (process_counter)
+                    0: begin
+                        _serial_clock       =   1;
+                        _process_counter    =   1;
+                    end
+                    1: begin
+                        if (external_serial_clock == 1) begin
+                            _last_acknowledge   =   0;
+                            _process_counter    =   2;
+                        end
+                    end
+                    2: begin
+                        _serial_clock   =   0;
+
+                        if (external_serial_data == 0) begin
+                            _last_acknowledge   =   1;
+                        end
+                        _process_counter    =   3;
+                    end
+                    3:  begin
+                        if (last_acknowledge == 1) begin
+                            _last_acknowledge   =   0;
+                            _serial_data        =   post_serial_data;
+                            _state              =   post_state;
+                        end
+                        else begin
+                            _state  =   S_IDLE;
+                        end
+                        _process_counter =   0;
+                    end
+                endcase
+            end
+        end
+        S_WRITE_REG_ADDR_MSB: begin
+            if (divider_tick) begin
+                case (process_counter)
+                    0: begin
+                        _serial_clock       =   1;
+                        _process_counter    =   1;
+                    end
+                    1: begin
+                        if (external_serial_clock == 1) begin
+                            _last_acknowledge   =   0;
+                            _process_counter    =   2;
+                        end
+                    end
+                    2: begin
+                        _serial_clock       =   0;
+                        _bit_counter        =   bit_counter - 1;
+                        _process_counter    =   3;
+                    end
+                    3: begin
+                        if (bit_counter == 0) begin
+                            _post_state         =   S_WRITE_REG_ADDR;
+                            _post_serial_data   =   saved_register_address[7];
+                            _bit_counter        =   8;
+                            _serial_data        =   0;
+                            _state              =   S_CHECK_ACK;
+                        end
+                        else begin
+                            _serial_data        =   saved_register_address[bit_counter+3'd7];
+                        end
+                        _process_counter        =   0;
+                    end
+                endcase
+            end
+        end
+        S_WRITE_REG_ADDR: begin
+            if (divider_tick) begin
+                case (process_counter)
+                    0: begin
+                        _serial_clock       =   1;
+                        _process_counter    =   1;
+                    end
+                    1: begin
+                        if (external_serial_clock == 1) begin
+                            _last_acknowledge   =   0;
+                            _process_counter    =   2;
+                        end
+                    end
+                    2: begin
+                        _serial_clock       =   0;
+                        _bit_counter        =   bit_counter - 1;
+                        _process_counter    =   3;
+                    end
+                    3: begin
+                        if (bit_counter == 0) begin
+                            if (read_write == 0) begin
+                                if (DATA_WIDTH == 16) begin
+                                    _post_state         =   S_WRITE_REG_DATA_MSB;
+                                    _post_serial_data   =   saved_mosi_data[15];
+                                end
+                                else begin
+                                    _post_state         =   S_WRITE_REG_DATA;
+                                    _post_serial_data   =   saved_mosi_data[7];
+                                end
+                            end
+                            else begin
+                                _post_state         =   S_RESTART;
+                                _post_serial_data   =   1;
+                            end
+                            _bit_counter    =   8;
+                            _serial_data    =   0;
+                            _state          =   S_CHECK_ACK;
+                        end
+                        else begin
+                            _serial_data    =   saved_register_address[bit_counter-1];
+                        end
+                        _process_counter    =   0;
+                    end
+                endcase
+            end
+        end
+        S_WRITE_REG_DATA_MSB: begin
+            if (divider_tick) begin
+                case (process_counter)
+                    0: begin
+                        _serial_clock       =   1;
+                        _process_counter    =   1;
+                    end
+                    1: begin
+                        if (external_serial_clock == 1) begin
+                            _last_acknowledge   =   1;
+                            _process_counter    =   2;
+                        end
+                    end
+                    2: begin
+                        _serial_clock       =   0;
+                        _bit_counter        =   bit_counter - 1;
+                        _process_counter    =   3;
+                    end
+                    3: begin
+                        if (bit_counter == 0) begin
+                            _state              =   S_CHECK_ACK;
+                            _post_state         =   S_WRITE_REG_DATA;
+                            _post_serial_data   =   saved_mosi_data[7];
+                            _bit_counter        =   8;
+                            _serial_data        =   0;
+                        end
+                        else begin
+                            _serial_data        =   saved_mosi_data[bit_counter+3'd7];
+                        end
+                        _process_counter        =   0;
+                    end
+                endcase
+            end
+        end
+        S_WRITE_REG_DATA: begin
+            if (divider_tick) begin
+                case (process_counter)
+                    0: begin
+                        _serial_clock       =   1;
+                        _process_counter    =   1;
+                    end
+                    1: begin
+                        if (external_serial_clock == 1) begin
+                            _last_acknowledge   =   0;
+                            _process_counter    =   2;
+                        end
+                    end
+                    2: begin
+                        _serial_clock       =   0;
+                        _bit_counter        =   bit_counter - 1;
+                        _process_counter    =   3;
+                    end
+                    3: begin
+                        if (bit_counter == 0) begin
+                            _state              =   S_CHECK_ACK;
+                            _post_state         =   S_SEND_STOP;
+                            _post_serial_data   =   0;
+                            _bit_counter        =   8;
+                            _serial_data        =   0;
+                        end
+                        else begin
+                            _serial_data        =   saved_mosi_data[bit_counter-1];
+                        end
+                        _process_counter        =   0;
+                    end
+                endcase
+            end
+        end
+        S_RESTART: begin
+            if (divider_tick) begin
+                case (process_counter)
+                    0: begin
+                        _process_counter    =   1;
+                    end
+                    1: begin
+                        _process_counter    =   2;
+                        _serial_clock       =   1;
+                    end
+                    2: begin
+                        _process_counter    =   3;
+                    end
+                    3: begin
+                        _state                      =   S_START;
+                        _post_state                 =   S_WRITE_ADDR_R;
+                        _saved_device_address[0]    =   1;
+                        _process_counter            =   0;
+                    end
+                endcase
+            end
+        end
+        S_WRITE_ADDR_R: begin
+            if (divider_tick) begin
+                case (process_counter)
+                    0: begin
+                        _serial_clock       =   1;
+                        _process_counter    =   1;
+                    end
+                    1: begin
+                        if (external_serial_clock == 1) begin
+                            _last_acknowledge   =   0;
+                            _process_counter    =   2;
+                        end
+                    end
+                    2: begin
+                        _serial_clock       =   0;
+                        _bit_counter        =   bit_counter - 1;
+                        _process_counter    =   3;
+                    end
+                    3: begin
+                        if (bit_counter == 0) begin
+                            if (DATA_WIDTH == 16) begin
+                                _post_state         =   S_READ_REG_MSB;
+                                _post_serial_data   =   0;
+                            end
+                            else begin
+                                _post_state         =   S_READ_REG;
+                                _post_serial_data   =   0;
+                            end
+                            _state          =   S_CHECK_ACK;
+                            _bit_counter    =   8;
+                        end
+                        else begin
+                            _serial_data    =   saved_device_address[bit_counter-1];
+                        end
+                        _process_counter    =   0;
+                    end
+                endcase
+            end
+        end
+        S_READ_REG_MSB: begin
+            if (divider_tick) begin
+                case (process_counter)
+                    0: begin
+                        _serial_clock       =   1;
+                        _process_counter    =   1;
+                    end
+                    1: begin
+                        if (external_serial_clock == 1) begin
+                            _last_acknowledge   =   0;
+                            _process_counter    =   2;
+                        end
+                    end
+                    2: begin
+                        _serial_clock               =   0;
+                        //sample data on this rising edge of scl
+                        _miso_data[bit_counter+7]   =   external_serial_data;
+                        _bit_counter                =   bit_counter - 1;
+                        _process_counter            =   3;
+                    end
+                    3: begin
+                        if (bit_counter == 0) begin
+                            _post_state     =   S_READ_REG;
+                            _state          =   S_SEND_ACK;
+                            _bit_counter    =   8;
+                            _serial_data    =   0;
+                        end
+                        _process_counter    =   0;
+                    end
+                endcase
+            end
+        end
+        S_READ_REG: begin
+            if (divider_tick) begin
+                case (process_counter)
+                    0: begin
+                        _serial_clock       =   1;
+                        _process_counter    =   1;
+                    end
+                    1: begin
+                        if (external_serial_clock) begin
+                            _last_acknowledge   =   0;
+                            _process_counter    =   2;
+                        end
+                    end
+                    2: begin
+                        _serial_clock       =   0;
+                        //sample data on this rising edge of scl
+                        _miso_data[bit_counter-1]   =   external_serial_data;
+                        _bit_counter                =   bit_counter - 1;
+                        _process_counter    =   3;
+                    end
+                    3: begin
+                        if (bit_counter == 0) begin
+                            _state          =   S_SEND_NACK;
+                            _serial_data    =   0;
+                        end
+                        _process_counter    =   0;
+                    end
+                endcase
+            end
+        end
+        S_SEND_NACK: begin
+            if (divider_tick) begin
+                case (process_counter)
+                    0: begin
+                        _serial_clock       =   1;
+                        _serial_data        =   1;
+                        _process_counter    =   1;
+                    end
+                    1: begin
+                        if (external_serial_clock) begin
+                            _last_acknowledge   =   0;
+                            _process_counter    =   2;
+                        end
+                    end
+                    2: begin
+                        _process_counter    =   3;
+                        _serial_clock       =   0;
+                    end
+                    3: begin
+                        _state              =   S_SEND_STOP;
+                        _process_counter    =   0;
+                        _serial_data        =   0;
+                    end
+                endcase
+            end
+        end
+        S_SEND_ACK: begin
+            if (divider_tick) begin
+                case (process_counter)
+                    0: begin
+                        _serial_clock       =   1;
+                        _process_counter    =   1;
+                        _serial_data        =   0;
+                    end
+                    1: begin
+                        if (external_serial_clock) begin
+                            _process_counter    =   2;
+                        end
+                    end
+                    2: begin
+                        _process_counter    =   3;
+                        _serial_clock       =   0;
+                    end
+                    3: begin
+                        _state              =   post_state;
+                        _process_counter    =   0;
+                    end
+                endcase
+            end
+        end
+        S_SEND_STOP: begin
+            if (divider_tick) begin
+                case (process_counter)
+                    0: begin
+                        _serial_clock       =   1;
+                        _process_counter    =   1;
+                    end
+                    1: begin
+                        if (external_serial_clock == 1) begin
+                            _process_counter    =   2;
+                        end
+                    end
+                    2: begin
+                        _process_counter    =   3;
+                        _serial_data        =   1;
+                    end
+                    3: begin
+                        _state  =   S_IDLE;
+                    end
+                endcase
+            end
+        end
+    endcase
+end
+
+always_ff @(posedge clock) begin
+    if (!reset_n) begin
+        state                   <=  S_IDLE;
+        post_state              <=  S_IDLE;
+        process_counter         <=  0;
+        bit_counter             <=  0;
+        last_acknowledge        <=  0;
+        miso_data               <=  0;
+        saved_read_write        <=  0;
+        divider_counter         <=  0;
+        saved_device_address    <=  0;
+        saved_register_address  <=  0;
+        saved_mosi_data         <=  0;
+        serial_clock            <=  0;
+        serial_data             <=  0;
+        saved_mosi_data         <=  0;
+        post_serial_data        <=  0;
+        busy                    <=  0;
+    end
+    else begin
+        state                   <=  _state;
+        post_state              <=  _post_state;
+        process_counter         <=  _process_counter;
+        bit_counter             <=  _bit_counter;
+        last_acknowledge        <=  _last_acknowledge;
+        miso_data               <=  _miso_data;
+        saved_read_write        <=  _saved_read_write;
+        divider_counter         <=  _divider_counter;
+        saved_device_address    <=  _saved_device_address;
+        saved_register_address  <=  _saved_register_address;
+        saved_mosi_data         <=  _saved_mosi_data;
+        serial_clock            <=  _serial_clock;
+        serial_data             <=  _serial_data;
+        post_serial_data        <=  _post_serial_data;
+        busy                    <=  _busy;
+    end
+ end
+    
+endmodule

ModRetro_oss-chromatic-console-fpga/esp32t/src/rtl/BSP/mem_system_top.sv

@@ -0,0 +1,236 @@
+// mem_system_top.v
+
+module mem_system_top #(parameter ISSIMU=0)
+(
+    input               xClk,
+    input               fClk,
+    input               hClk,
+    input               reset,
+    
+    input               QSPI_CLK,
+    input               QSPI_MOSI,
+    input               QSPI_MISO,
+    input               QSPI_CS,
+    input               QSPI_WP,
+    input               QSPI_HD,
+
+    output              PS_CE_N,
+    output              PS_CLK,
+    inout   [7:0]       PS_DQ,
+    inout               PS_DQS,
+    
+    input               hGBNewLine,
+    input   [22:0]      hGBAddress,
+    input               hGBWrite,
+    input   [15:0]      hGBData,
+    
+    input               hValid,
+    input               hHsync,
+    input               hVsync,
+    output              qMenuInit,
+    output  [15:0]      hWrBurstQ,
+    output  [15:0]      hWrBurstQ2,
+    
+    output              BIST_failed,
+    output              BIST_finished
+);
+    
+    localparam RAMPORTCOUNT = 5;
+    localparam RAMPORT_BIST = 0;
+    localparam RAMPORT_QSPI = 1;
+    localparam RAMPORT_FBRD = 2;
+    localparam RAMPORT_FBWR = 3;
+    localparam RAMPORT_FBRDOSD = 4;
+    
+    typedef logic tRAMIn_request     [RAMPORTCOUNT];
+    typedef logic tRAMIn_RnW         [RAMPORTCOUNT];
+    typedef logic [22:0] tRAMIn_addr        [RAMPORTCOUNT];
+    typedef logic [15:0] tRAMIn_din         [RAMPORTCOUNT];
+    typedef logic [10:0] tRAMIn_burst_length[RAMPORTCOUNT];
+                  
+    typedef logic tRAMOut_writeNext   [RAMPORTCOUNT];
+    typedef logic tRAMOut_done        [RAMPORTCOUNT];
+    typedef logic tRAMOut_dout_valid  [RAMPORTCOUNT];
+
+    tRAMIn_request      RAMIn_request;     
+    tRAMIn_RnW          RAMIn_RnW;     
+    tRAMIn_addr         RAMIn_addr;     
+    tRAMIn_din          RAMIn_din;     
+    tRAMIn_burst_length RAMIn_burst_length; 
+                            
+    tRAMOut_writeNext   RAMOut_writeNext; 
+    tRAMOut_done        RAMOut_done; 
+    tRAMOut_dout_valid  RAMOut_dout_valid; 
+   
+    wire BIST_req_read;
+    wire BIST_req_write;
+    assign RAMIn_request[RAMPORT_BIST] = BIST_req_read | BIST_req_write;
+    assign RAMIn_RnW[RAMPORT_BIST]     = BIST_req_read;
+    
+    assign RAMIn_RnW[RAMPORT_QSPI]          = 1'b0;
+    assign RAMIn_burst_length[RAMPORT_QSPI] = 11'd1024;
+    
+    assign RAMIn_RnW[RAMPORT_FBRD]          = 1'b1;
+    assign RAMIn_burst_length[RAMPORT_FBRD] = 11'd320;
+    assign RAMIn_din[RAMPORT_FBRD] = 16'd0;   
+
+    assign RAMIn_RnW[RAMPORT_FBRDOSD]          = 1'b1;
+    assign RAMIn_burst_length[RAMPORT_FBRDOSD] = 11'd320;
+    assign RAMIn_din[RAMPORT_FBRDOSD] = 16'd0;   
+
+    assign RAMIn_RnW[RAMPORT_FBWR]          = 1'b0;
+    assign RAMIn_burst_length[RAMPORT_FBWR] = 11'd320;
+
+    wire RAM_ready;
+    wire [15:0] RAM_dout;    
+    
+    MultiPortRamCtrl #(ISSIMU)
+    iMultiPortRamCtrl
+    (
+       .clk_sys            (xClk),      
+       .clk_fsys           (fClk),
+       .rst                (reset),      
+       
+       .RAMIn_request      (RAMIn_request),  
+       .RAMIn_RnW          (RAMIn_RnW),         
+       .RAMIn_addr         (RAMIn_addr),        
+       .RAMIn_din          (RAMIn_din),         
+       .RAMIn_burst_length (RAMIn_burst_length),
+            
+       .RAMOut_writeNext   (RAMOut_writeNext),   
+       .RAMOut_done        (RAMOut_done),        
+       .RAMOut_dout_valid  (RAMOut_dout_valid),  
+ 
+       .ram_ready          (RAM_ready), 
+       .ram_dout           (RAM_dout),  
+            
+       .psram_clk          (PS_CLK), 
+       .psram_cs_n         (PS_CE_N),
+       .psram_rwds         (PS_DQS),
+       .psram_dq           (PS_DQ)
+    );
+    
+    PSRAMBIST_Burst #(
+        .BIST_BURSTLENGTH(512), 
+        .SHORTTEST(1)
+        )
+    iPSRAMBIST_Burst
+    (
+       .clk                  (xClk),  
+       .rst                  (reset),
+                                    
+       .test_finished        (BIST_finished),   
+       .test_failed          (BIST_failed),
+                                    
+       .ram_req_read         (BIST_req_read),
+       .ram_req_write        (BIST_req_write),
+       .ram_addr             (RAMIn_addr[RAMPORT_BIST]),    
+       .ram_din              (RAMIn_din[RAMPORT_BIST]),
+       .burst_length         (RAMIn_burst_length[RAMPORT_BIST]),
+       .ram_ready            (RAM_ready),
+       .ram_writeNext        (RAMOut_writeNext[RAMPORT_BIST]),
+       .ram_done             (RAMOut_done[RAMPORT_BIST]),
+       .ram_dout             (RAM_dout),
+       .ram_dout_valid       (RAMOut_dout_valid[RAMPORT_BIST])
+    );  
+
+    wire [15:0] qData;
+    wire [31:0] qAddress;
+    wire qDataValid;
+
+    QSPI_Slave u_QSPI_Slave(
+        .QSPI_CLK(QSPI_CLK),
+        .QSPI_CS(QSPI_CS),
+        .QSPI_MOSI(QSPI_MOSI),
+        .QSPI_MISO(QSPI_MISO),
+        .QSPI_WP(QSPI_WP),
+        .QSPI_HD(QSPI_HD),
+        
+        .qMenuInit(qMenuInit),
+        .qDataValid(qDataValid),
+        .qData(qData),
+        .qAddress(qAddress)
+    );
+
+    mm_burst_write u_mm_burst_write(
+        .QSPI_CLK(QSPI_CLK),
+        .QSPI_CS(QSPI_CS),
+        .qAddress(qAddress),
+        .qDataValid(qDataValid),
+        .qData(qData),
+
+        .xClk(xClk),
+        // Standard FIFO uses xRegWrite here (not FWFT FIFO)
+        .xRdEn(RAMOut_writeNext[RAMPORT_QSPI]),
+        .xRamReady(BIST_finished),
+        .xMcuReqWrite(RAMIn_request[RAMPORT_QSPI]),
+        .xDout(RAMIn_din[RAMPORT_QSPI]),
+        .xAddress(RAMIn_addr[RAMPORT_QSPI])
+    );
+    
+    mm_burst_read_to_stream #(
+        .base_pointer(23'h10000)
+    )   u_mm_burst_read_to_stream(
+        .hClk(hClk),
+        .hVsync(hVsync),
+        .hHsync(hHsync),
+        .hValid(hValid),
+        .xClk(xClk),
+        
+        .xRamReady(BIST_finished),
+        .xStreamValid(RAMOut_dout_valid[RAMPORT_FBRD]),
+        .xStreamData(RAM_dout),
+        .xWrBurstDone(RAMOut_done[RAMPORT_FBRD]),
+        .xGbReqRead(RAMIn_request[RAMPORT_FBRD]),
+        
+        .hWrBurstQ(hWrBurstQ),
+        .xGbAddress(RAMIn_addr[RAMPORT_FBRD])
+    );
+
+    reg hVsync_r1;
+    reg hHsync_r1;
+    reg hValid_r1;
+    always@(posedge hClk)
+        begin
+        hVsync_r1 <= hVsync;
+        hHsync_r1 <= hHsync;
+        hValid_r1 <= hValid;
+    end
+
+    mm_burst_read_to_stream #(
+        .base_pointer(23'h0)
+    ) u_mm_burst_read_to_stream_osd(
+        .hClk(hClk),
+        .hVsync(hVsync_r1),
+        .hHsync(hHsync_r1),
+        .hValid(hValid_r1),
+        .xClk(xClk),
+                
+        .xRamReady(BIST_finished),
+        .xStreamValid(RAMOut_dout_valid[RAMPORT_FBRDOSD]),
+        .xStreamData(RAM_dout),
+        .xWrBurstDone(RAMOut_done[RAMPORT_FBRDOSD]),
+        .xGbReqRead(RAMIn_request[RAMPORT_FBRDOSD]),
+        
+        .hWrBurstQ(hWrBurstQ2),
+        .xGbAddress(RAMIn_addr[RAMPORT_FBRDOSD])
+    );
+
+    
+    gb_burst_write u_gb_burst_write(
+        .hClk(hClk),
+        .hVsync(hVsync),
+        .hNewLine(hGBNewLine),
+        .hAddress(hGBAddress),
+        .hWrite(hGBWrite),
+        .hData(hGBData),
+
+        .xClk(xClk),
+        .xRdEn(RAMOut_writeNext[RAMPORT_FBWR]),
+        .xRamReady(BIST_finished),
+        .xMcuReqWrite(RAMIn_request[RAMPORT_FBWR]),
+        .xDout(RAMIn_din[RAMPORT_FBWR]),
+        .xAddress(RAMIn_addr[RAMPORT_FBWR])
+    );
+    
+endmodule

ModRetro_oss-chromatic-console-fpga/esp32t/src/rtl/BSP/mm_burst_read_to_stream.v

@@ -0,0 +1,110 @@
+// mm_burst_read_to_stream.v
+//
+// Generates an output stream aligned with the input timings
+// by performing memory mapped burst reads
+
+module mm_burst_read_to_stream #(
+    parameter base_pointer = 23'h0
+)
+(
+    input               hClk,
+    input               hVsync,
+    input               hHsync,
+    input               hValid,
+    input               xClk,    
+        
+    input               xRamReady,
+    input               xStreamValid,
+    input       [15:0]  xStreamData,
+    input               xWrBurstDone,
+    output  reg         xGbReqRead,
+    
+    output  reg [15:0]  hWrBurstQ,
+    output  reg [22:0]  xGbAddress
+    
+);
+
+    localparam LINE_DEPTH = 160;
+
+    reg [15:0] lineRam [LINE_DEPTH-1:0];//23039:0];
+    initial begin : init_RAM
+      integer i;
+      for (i = 0; i < LINE_DEPTH; i = i + 1) lineRam[i] = 16'b0;
+    end
+    
+    reg [14:0] xLineRam_wa;
+    reg [14:0] hLineRam_ra;
+
+    reg hVsync_r1;
+    always@(posedge hClk)
+        hVsync_r1 <= hVsync;
+
+    reg hHsync_r1;
+    always@(posedge hClk)
+        hHsync_r1 <= hHsync;
+        
+    wire hStartOfFrame = ~hVsync_r1 & hVsync;
+    always@(posedge hClk)
+        hHsync_r1 <= hHsync;
+    wire hStartOfLine = ~hHsync_r1 & hHsync;
+
+    always@(posedge hClk)
+        if(hStartOfFrame)
+            hLineRam_ra <= 'd0;
+        else
+            if(hValid)
+            begin
+                if (hLineRam_ra < LINE_DEPTH) 
+                    hLineRam_ra <= hLineRam_ra + 1'd1;
+            end
+            else
+                if(hStartOfLine)
+                    hLineRam_ra <= 'd0;
+        
+    always@(posedge hClk)
+        hWrBurstQ <= lineRam[hLineRam_ra];
+
+    always@(posedge xClk)
+        if(xStreamValid)
+            lineRam[xLineRam_wa] <= xStreamData;
+    
+    always@(posedge xClk)
+    begin
+        if(xStreamValid)
+            xLineRam_wa <= xLineRam_wa + 1'd1;
+         
+        if(xWrBurstDone)
+            xLineRam_wa <= 'd0;
+    end
+
+    // TODO - cleanup CDC
+            
+    reg [3:0] xHsync_sr;
+    always@(posedge xClk)
+        xHsync_sr <= {xHsync_sr[2:0], hHsync};
+    wire xEndOfLine = xHsync_sr[3:2] == 2'b10;
+
+    reg [3:0] xVsync_sr;
+    always@(posedge xClk)
+        xVsync_sr <= {xVsync_sr[2:0], hVsync};
+    wire xStartOfFrame = xVsync_sr[3:2] == 2'b01;
+
+    always@(posedge xClk)
+    begin
+        xGbReqRead <= 1'd0;
+        if(xEndOfLine || xStartOfFrame)
+            xGbReqRead <= xRamReady;
+    end
+
+    always@(posedge xClk)
+    begin
+        if(xStartOfFrame)
+        begin
+            xGbAddress <= base_pointer;
+        end
+        else
+            if(xEndOfLine)
+                xGbAddress <= xGbAddress + 2*LINE_DEPTH;
+    end
+
+endmodule

ModRetro_oss-chromatic-console-fpga/esp32t/src/rtl/BSP/mm_burst_write.v

@@ -0,0 +1,52 @@
+// mm_burst_write.v
+
+// Converts QSPI memory mapped transfer into a burst write to PSRAM
+module mm_burst_write(
+    input           QSPI_CLK,
+    input           QSPI_CS,
+    input   [31:0]  qAddress,
+    input           qDataValid,
+    input   [15:0]  qData,
+    
+    input           xClk,
+    input           xRdEn,
+    input           xRamReady,
+    output  reg     xMcuReqWrite,
+    
+    output  [15:0]  xDout,
+    output  [22:0]  xAddress
+);
+
+    assign xAddress = qAddress[22:0];
+
+    wire fifo_empty;
+    wire fifo_full;
+    wire fifo_almost_full;
+    fifo1k u_fifo1k(
+        .Data(qData), //input [15:0] Data
+        .WrReset(1'd0), //input WrReset
+        .RdReset(1'd0), //input RdReset
+        .WrClk(~QSPI_CLK), //input WrClk
+        .RdClk(xClk), //input RdClk
+        .WrEn(qDataValid), //input WrEn
+        .RdEn(xRdEn | xMcuReqWrite), //input RdEn
+        .Q(xDout), //output [15:0] Q
+        .Almost_Full(fifo_almost_full), //output Almost_Full
+        .Empty(fifo_empty), //output Empty
+        // Full is on the write clock domain
+        // Won't update when QSPI CS is high
+        .Full(fifo_full) //output Full
+    );
+    
+    reg [3:0] xCS_sr;
+    always@(posedge xClk)
+        xCS_sr <= {xCS_sr[2:0], QSPI_CS};
+    
+    always@(posedge xClk)
+    begin
+        xMcuReqWrite <= 1'd0;
+        if(xCS_sr[3:2] == 2'b01)
+            xMcuReqWrite <= xRamReady;      
+    end
+    
+endmodule

ModRetro_oss-chromatic-console-fpga/esp32t/src/rtl/BSP/mpmc.v

@@ -0,0 +1,71 @@
+// mpmc.v
+
+module mpmc(
+    input xClk,
+    
+    // PSRAM interface
+    input               xPsramReady,
+    input               xPsramDone,
+    output  reg         xPsramReqRead,
+    output  reg         xPsramReqWrite,
+    output  reg [31:0]  xMemAddress,
+    output  reg [10:0]  xBurstLength,
+    
+    // Port 1 (MCU writes)
+    input               xMcuReqWrite,
+    output              xMcuActive,
+    input [31:0]        xMcuAddress,
+    input [10:0]        xMcuBurstLength,
+
+    // Port 2 (Emulation reads)
+    input               xGbReqRead,
+    output              xGbActive,
+    input [31:0]        xGbAddress,
+    input [10:0]        xGbBurstLength
+);
+
+    reg [1:0]               xActiveChannel;
+    assign xMcuActive   =   xActiveChannel == 2'b01;
+    assign xGbActive    =   xActiveChannel == 2'b10;
+
+    wire xGrantMCU  = xMcuReqWrite  && xPsramReady;
+    // MCU gets priority in case of a tie
+    wire xGrantGB   = xGbReqRead    && xPsramReady && ~xMcuReqWrite;
+
+    always@(posedge xClk)
+    begin
+        xPsramReqRead   <= xGrantGB;
+        xPsramReqWrite  <= xGrantMCU;
+    end
+
+    always@(posedge xClk)
+        if(xGrantGB)
+        begin
+            xMemAddress <= xGbAddress;
+            xBurstLength <= xGbBurstLength;
+        end
+        else
+        begin
+            xMemAddress <= xMcuAddress;
+            xBurstLength <= xMcuBurstLength;
+        end
+    
+    always@(posedge xClk)
+    begin
+        case(xActiveChannel)
+            // Idle
+            2'b00 : 
+            begin
+                if(xGrantMCU)
+                    xActiveChannel <= 2'b01;
+                else
+                    if(xGbReqRead && xPsramReady)
+                        xActiveChannel <= 2'b10;
+            end
+            // MCU or GB
+            default :
+                if(xPsramDone)
+                    xActiveChannel <= 2'b00;
+        endcase
+    end
+endmodule

ModRetro_oss-chromatic-console-fpga/esp32t/src/rtl/BSP/overlayBatteryBack.vhd

@@ -0,0 +1,34 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.all;     
+
+entity overlayBatteryBack is 
+   port 
+   (
+      screenX       : in  unsigned(7 downto 0);
+      screenY       : in  unsigned(7 downto 0);
+      overlayActive : out std_logic
+   );   
+end entity;
+
+architecture arch of overlayBatteryBack is
+   
+begin
+
+   process (all)
+   begin
+      
+      overlayActive <= '0';
+      
+      if (screenX >= 141 and screenX <= 157 and screenY >= 3 and screenY <= 18) then
+         overlayActive <= '1';
+         if (screenX = 157 and (screenY = 3 or screenY = 18)) then overlayActive <= '0'; end if;
+         if (screenX = 141 and                 screenY = 18)  then overlayActive <= '0'; end if;
+      end if;
+  
+   end process;
+
+   
+end architecture;
+
+

ModRetro_oss-chromatic-console-fpga/esp32t/src/rtl/BSP/overlayBatteryFront.vhd

@@ -0,0 +1,56 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.all;     
+
+entity overlayBatteryFront is 
+   port 
+   (
+      screenX       : in  unsigned(7 downto 0);
+      screenY       : in  unsigned(7 downto 0);
+      overlayActive : out std_logic
+   );   
+end entity;
+
+architecture arch of overlayBatteryFront is
+
+   type tpixeldata is array (0 to 15) of std_logic_vector(0 to 16);
+   constant pixeldata : tpixeldata := 
+   (
+      "01111111111111110",
+      "10000000000000001",
+      "10000000000000001",
+      "10000000000000001",
+      "10000000000000001",
+      "10001111111110001",
+      "10001000000010001",
+      "10001010000011001",
+      "10001010000011001",
+      "10001000000010001",
+      "10001111111110001",
+      "10000000000000001",
+      "10000000000000001",
+      "10000000000000001",
+      "10000000000000001",
+      "01111111111111110"
+   );
+
+   
+begin
+
+   process (all)
+   begin
+      
+      overlayActive <= '0';
+      
+      if (screenX >= 140 and screenX <= 156 and screenY >= 2 and screenY <= 17) then
+         if (pixeldata(to_integer(screenY) - 2)(to_integer(screenX) - 140) = '1') then
+            overlayActive <= '1';
+         end if;
+      end if;
+  
+   end process;
+
+   
+end architecture;
+
+

ModRetro_oss-chromatic-console-fpga/esp32t/src/rtl/BSP/overlayDebug.vhd

@@ -0,0 +1,121 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.all;     
+
+entity overlayDebug is 
+   port 
+   (
+      screenX       : in  unsigned(1 downto 0);
+      screenY       : in  unsigned(2 downto 0);
+      number        : in  unsigned(3 downto 0);
+      overlayActive : out std_logic
+   );   
+end entity;
+
+architecture arch of overlayDebug is
+
+   type tpixeldata is array (0 to 4) of std_logic_vector(0 to 2);
+   type tpixelarray is array(0 to 15) of tpixeldata;
+   constant pixelarray : tpixelarray := 
+   (
+      ( "111", -- 0
+        "101",
+        "101",
+        "101",
+        "111"),
+      ( "010", -- 1
+        "110",
+        "010",
+        "010",
+        "010"),
+      ( "111", -- 2
+        "001",
+        "111",
+        "100",
+        "111"),
+      ( "111", -- 3
+        "001",
+        "111",
+        "001",
+        "111"),
+      ( "101", -- 4
+        "101",
+        "111",
+        "001",
+        "001"),
+      ( "111", -- 5
+        "100",
+        "111",
+        "001",
+        "111"),
+      ( "111", -- 6
+        "100",
+        "111",
+        "101",
+        "111"),
+      ( "111", -- 7
+        "001",
+        "001",
+        "001",
+        "001"),
+      ( "111", -- 8
+        "101",
+        "111",
+        "101",
+        "111"),
+      ( "111", -- 9
+        "101",
+        "111",
+        "001",
+        "111"),
+      ( "111", -- A
+        "101",
+        "111",
+        "101",
+        "101"),
+      ( "110", -- B
+        "101",
+        "111",
+        "101",
+        "110"),
+      ( "111", -- C
+        "100",
+        "100",
+        "100",
+        "111"),
+      ( "110", -- D
+        "101",
+        "101",
+        "101",
+        "110"),  
+      ( "111", -- E
+        "100",
+        "111",
+        "100",
+        "111"), 
+      ( "111", -- F
+        "100",
+        "111",
+        "100",
+        "100")
+   );
+   
+begin
+
+   process (all)
+   begin
+      
+      overlayActive <= '0';
+      
+      if (screenX < 3 and screenY < 5) then
+         if (pixelarray(to_integer(number))(to_integer(screenY))(to_integer(screenX)) = '1') then
+            overlayActive <= '1';
+         end if;
+      end if;
+  
+   end process;
+
+   
+end architecture;
+
+

ModRetro_oss-chromatic-console-fpga/esp32t/src/rtl/BSP/overlayTimerBack.vhd

@@ -0,0 +1,34 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.all;     
+
+entity overlayTimerBack is 
+   port 
+   (
+      screenX       : in  unsigned(7 downto 0);
+      screenY       : in  unsigned(7 downto 0);
+      overlayActive : out std_logic
+   );   
+end entity;
+
+architecture arch of overlayTimerBack is
+
+begin
+
+   process (all)
+   begin
+      
+      overlayActive <= '0';
+      
+      if (screenX >= 2 and screenX <= 40 and screenY >= 3 and screenY <= 18) then
+         overlayActive <= '1';
+         if (screenX = 40 and (screenY = 3 or screenY = 18)) then overlayActive <= '0'; end if;
+         if (screenX = 2  and                 screenY = 18)  then overlayActive <= '0'; end if;
+      end if;
+  
+   end process;
+
+   
+end architecture;
+
+

ModRetro_oss-chromatic-console-fpga/esp32t/src/rtl/BSP/overlayTimerFront.vhd

@@ -0,0 +1,33 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.all;     
+
+entity overlayTimerFront is 
+   port 
+   (
+      screenX       : in  unsigned(7 downto 0);
+      screenY       : in  unsigned(7 downto 0);
+      overlayActive : out std_logic
+   );   
+end entity;
+
+architecture arch of overlayTimerFront is
+
+begin
+
+   process (all)
+   begin
+      
+      overlayActive <= '0';
+      
+      if (screenX >= 1 and screenX <= 39 and screenY >= 2 and screenY <= 17) then
+         if ( screenX = 1 or screenX = 39   or  screenY = 2 or screenY = 17)  then overlayActive <= '1'; end if;
+         if ((screenX = 1 or screenX = 39) and (screenY = 2 or screenY = 17)) then overlayActive <= '0'; end if;
+      end if;
+  
+   end process;
+
+   
+end architecture;
+
+

ModRetro_oss-chromatic-console-fpga/esp32t/src/rtl/BSP/overlayTimerNumber.vhd

@@ -0,0 +1,101 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.numeric_std.all;     
+
+entity overlayTimerNumber is 
+   port 
+   (
+      screenX       : in  unsigned(1 downto 0);
+      screenY       : in  unsigned(2 downto 0);
+      number        : in  unsigned(3 downto 0);
+      overlayActive : out std_logic
+   );   
+end entity;
+
+architecture arch of overlayTimerNumber is
+
+   type tpixeldata is array (0 to 4) of std_logic_vector(0 to 2);
+   type tpixelarray is array(0 to 11) of tpixeldata;
+   constant pixelarray : tpixelarray := 
+   (
+      ( "111", -- 0
+        "101",
+        "101",
+        "101",
+        "111"),
+      ( "010", -- 1
+        "110",
+        "010",
+        "010",
+        "010"),
+      ( "111", -- 2
+        "001",
+        "111",
+        "100",
+        "111"),
+      ( "111", -- 3
+        "001",
+        "111",
+        "001",
+        "111"),
+      ( "101", -- 4
+        "101",
+        "111",
+        "001",
+        "001"),
+      ( "111", -- 5
+        "100",
+        "111",
+        "001",
+        "111"),
+      ( "111", -- 6
+        "100",
+        "111",
+        "101",
+        "111"),
+      ( "111", -- 7
+        "001",
+        "001",
+        "001",
+        "001"),
+      ( "111", -- 8
+        "101",
+        "111",
+        "101",
+        "111"),
+      ( "111", -- 9
+        "101",
+        "111",
+        "001",
+        "111"),
+      ( "000", -- :
+        "100",
+        "000",
+        "100",
+        "000"),
+      ( "000", -- .
+        "000",
+        "000",
+        "000",
+        "100")
+   );
+   
+begin
+
+   process (all)
+   begin
+      
+      overlayActive <= '0';
+      
+      if (screenX < 3 and screenY < 5 and number < 12) then
+         if (pixelarray(to_integer(number))(to_integer(screenY))(to_integer(screenX)) = '1') then
+            overlayActive <= '1';
+         end if;
+      end if;
+  
+   end process;
+
+   
+end architecture;
+
+

ModRetro_oss-chromatic-console-fpga/esp32t/src/rtl/BSP/polling_master.v

@@ -0,0 +1,368 @@
+// polling_master.v
+// Poll TLV320 Audio codec
+/// Read volume wheel value (Page0 R117 bits 6:0)
+/// Read GPIO (headphone attached) value(Page0 R51 bit1)
+//// Toggle headphone or speaker
+
+// Poll BQ24296MRGER PMIC state
+/// I2C address 0x6B
+/// Write R02 = 10111100 is 0xBC (3008mA)
+/// Read  R08 System Status Reg
+/// Read  R09 New Fault Register
+
+// Poll ATSHA204A encryption
+
+module polling_master#(
+    parameter I2C_DATA_WIDTH = 8,
+    parameter REGISTER_WIDTH = 8,
+    parameter ADDRESS_WIDTH = 7
+)(
+    input                                   clk,
+    input                                   rst,
+    input                                   i2c_busy,
+    input                                   enable,
+    input                                   mute,
+    
+    input           [7:0]                   i2c_miso_data,
+
+    output  reg [7:0]                       volume,
+    output  reg [7:0]                       gpio,
+    output  reg [7:0]                       pmic_sys_status,
+    output  reg [7:0]                       new_fault,
+    output  reg [7:0]                       inlim,
+    output  reg [7:0]                       chargeCurrent,
+    
+    output  reg                             i2c_enable,
+    output  reg                             i2c_read_write,
+    output  reg     [I2C_DATA_WIDTH-1:0]    i2c_mosi_data,
+    output  reg     [REGISTER_WIDTH-1:0]    i2c_register_address,
+    output  reg     [ADDRESS_WIDTH-1:0]     i2c_device_address
+    
+);
+
+    reg [7:0] scount;
+    reg [7:0] regindex;
+    
+    localparam CODEC = 7'h18;
+    localparam PMIC = 7'h6B;
+    
+    reg [15:0] state;
+    localparam S_VOLUME       = 16'h0001;
+    localparam S_HP_GPIO      = 16'h0002;
+    localparam S_HP_EN0       = 16'h0004;
+    localparam S_HP_EN1       = 16'h0008;
+    localparam S_HP_SWPWRDOWN = 16'h0010;
+    localparam S_HP_EN2       = 16'h0020;
+    localparam S_HP_EN3       = 16'h0040;
+    localparam S_HP_EN4       = 16'h0080;
+    localparam S_SYS_STATUS   = 16'h0100;
+    localparam S_NEW_FAULT    = 16'h0200;
+    localparam S_INLIM        = 16'h0400;
+    localparam S_CHARGEWRITE  = 16'h0800;
+    localparam S_CHARGEREAD   = 16'h1000;
+    localparam S_IDLE         = 16'h2000;
+
+    reg txActive;
+
+    always@(posedge clk)
+    begin
+        if(rst)
+        begin
+            scount               <= 'd0;
+            i2c_read_write       <= 'd0;
+            i2c_register_address <= 'd0;
+            i2c_mosi_data        <= 'd0;
+            i2c_device_address   <= CODEC;
+            i2c_enable           <= 'd0;
+            regindex             <= 'd0;
+            state                <= S_IDLE;
+        end
+        else
+            case(state)
+            S_IDLE:
+            begin
+                i2c_enable       <= 'd0;
+                txActive         <= 1'd0;
+                i2c_read_write   <= 'd1; // Read
+                if(~i2c_busy && enable)
+                begin
+                    state                <= S_VOLUME;
+                    i2c_device_address   <= CODEC;
+                    i2c_register_address <= 8'd117; // Volume
+                end
+            end
+            S_VOLUME:
+            begin
+                if(i2c_busy)
+                begin
+                    txActive         <= 1'd1;
+                    i2c_enable       <= 'd0;
+                end
+                else
+                    if(txActive)
+                    begin
+                        i2c_read_write   <= 'd1; // Read
+                        state                <= S_HP_GPIO;
+                        i2c_register_address <= 8'd51; // HP Status
+                        i2c_device_address   <= CODEC;
+                        volume               <= i2c_miso_data;
+                        txActive             <= 1'd0;
+                    end
+                    else
+                        i2c_enable       <= 'd1;
+            end
+            S_HP_GPIO:
+            begin
+                if(i2c_busy)
+                begin
+                    txActive         <= 1'd1;
+                    i2c_enable       <= 'd0;
+                end
+                else
+                    if(txActive)
+                    begin
+                        gpio                 <= i2c_miso_data;
+                        state                <= S_HP_EN0;
+                        i2c_read_write       <= 'd0; // Write
+                        i2c_register_address <= 8'd00; // Page select
+                        i2c_mosi_data        <= 8'd01; // Page 1
+                        i2c_device_address   <= CODEC;
+                        txActive             <= 1'd0;
+                    end
+                    else
+                        i2c_enable           <= 'd1;
+            end
+            S_HP_EN0:
+            begin
+                if(i2c_busy)
+                begin
+                    txActive         <= 1'd1;
+                    i2c_enable       <= 'd0;
+                end
+                else
+                    if(txActive)
+                    begin
+                        state                <= S_HP_EN1;
+                        i2c_read_write       <= 'd0; // Write
+                        i2c_register_address <= 8'h26; // Left Analog Volume to SPK
+                        if(gpio[1])
+                            i2c_mosi_data        <= 8'h7F; // Mute Speaker (use headphones)
+                        else
+                            i2c_mosi_data        <= 8'h00; // Enable speaker (use speaker)
+                        i2c_device_address   <= CODEC;
+                        txActive             <= 1'd0;
+                    end
+                    else
+                        i2c_enable           <= 'd1;
+            end
+             S_HP_EN1:
+            begin
+                if(i2c_busy)
+                begin
+                    txActive         <= 1'd1;
+                    i2c_enable       <= 'd0;
+                end
+                else
+                    if(txActive)
+                    begin
+                        state                <= S_HP_SWPWRDOWN;
+                        i2c_read_write       <= 'd0; // Write
+                        i2c_register_address <= 8'h1F; // Headphone Driver
+                        if(gpio[1])
+                            i2c_mosi_data        <= 8'hC4; // Enable driver (use headphones)
+                        else
+                            i2c_mosi_data        <= 8'h04; // 04 Disable driver (use speaker)
+
+                        i2c_device_address   <= CODEC;
+                        txActive             <= 1'd0;
+                    end
+                    else
+                        i2c_enable           <= 'd1;
+            end
+             S_HP_SWPWRDOWN:
+            begin
+                if(i2c_busy)
+                begin
+                    txActive         <= 1'd1;
+                    i2c_enable       <= 'd0;
+                end
+                else
+                    if(txActive)
+                    begin
+                        state                <= S_HP_EN2;
+                        i2c_read_write       <= 'd0; // Write
+                        i2c_register_address <= 8'h2E; // Headphone Driver
+                        if(mute)
+                            i2c_mosi_data        <= 8'h80; // software power down - enabled
+                        else
+                            i2c_mosi_data        <= 8'h00; // software power down - disabled
+
+                        i2c_device_address   <= CODEC;
+                        txActive             <= 1'd0;
+                    end
+                    else
+                        i2c_enable           <= 'd1;
+            end
+             S_HP_EN2:
+            begin
+                if(i2c_busy)
+                begin
+                    txActive         <= 1'd1;
+                    i2c_enable       <= 'd0;
+                end
+                else
+                    if(txActive)
+                    begin
+                        state                <= S_HP_EN3;
+                        i2c_read_write       <= 'd0; // Write
+                        i2c_register_address <= 8'd00; // Page select
+                        i2c_mosi_data        <= 8'd00; // Page 0
+                        i2c_device_address   <= CODEC;
+                        txActive             <= 1'd0;
+                    end
+                    else
+                        i2c_enable           <= 'd1;
+            end
+            S_HP_EN3:
+            begin
+                if(i2c_busy)
+                begin
+                    txActive         <= 1'd1;
+                    i2c_enable       <= 'd0;
+                end
+                else
+                    if(txActive)
+                    begin
+                        state                <= S_HP_EN4;
+                        i2c_read_write       <= 'd0; // Write
+                        i2c_register_address <= 8'h3F; // DAC Data-Path setup
+                        if(gpio[1])
+                            i2c_mosi_data        <= 8'hD4; // Power up both dacs
+                        else
+                            i2c_mosi_data        <= 8'h90; // Power down right DAC, speaker mix both channel
+                        i2c_device_address   <= CODEC;
+                        txActive             <= 1'd0;
+                    end
+                    else
+                        i2c_enable           <= 'd1;
+            end
+            S_HP_EN4:
+            begin
+                if(i2c_busy)
+                begin
+                    txActive         <= 1'd1;
+                    i2c_enable       <= 'd0;
+                end
+                else
+                    if(txActive)
+                    begin
+                        i2c_read_write       <= 'd1; // Read
+                        state                <= S_SYS_STATUS;
+                        i2c_register_address <= 8'd08; // System Status
+                        i2c_device_address   <= PMIC;
+                        txActive             <= 1'd0;
+                    end
+                    else
+                        i2c_enable           <= 'd1;
+            end
+            S_SYS_STATUS:
+            begin
+                if(i2c_busy)
+                begin
+                    txActive         <= 1'd1;
+                    i2c_enable       <= 'd0;
+                end
+                else
+                    if(txActive)
+                    begin
+                        i2c_read_write       <= 'd1; // Read
+                        state                <= S_NEW_FAULT;
+                        i2c_register_address <= 8'd09; // Fault Status
+                        i2c_device_address   <= PMIC;
+                        pmic_sys_status      <= i2c_miso_data;
+                        txActive             <= 1'd0;
+                    end
+                    else
+                        i2c_enable           <= 'd1;
+            end
+            S_NEW_FAULT:
+            begin
+                if(i2c_busy)
+                begin
+                    txActive         <= 1'd1;
+                    i2c_enable       <= 'd0;
+                end
+                else
+                    if(txActive)
+                    begin
+                        i2c_read_write       <= 'd1; // Read
+                        state                <= S_INLIM;
+                        i2c_register_address <= 8'd00; // Input Limit
+                        i2c_device_address   <= PMIC;
+                        new_fault            <= i2c_miso_data;
+                        txActive             <= 1'd0;
+                    end
+                    else
+                        i2c_enable           <= 'd1;
+            end
+            S_INLIM:
+            begin
+                if(i2c_busy)
+                begin
+                    txActive         <= 1'd1;
+                    i2c_enable       <= 'd0;
+                end
+                else
+                    if(txActive)
+                    begin
+                        i2c_read_write       <= 'd0; // Write
+                        state                <= S_CHARGEWRITE;
+                        i2c_register_address <= 8'd02; // Charge Current Control
+                        i2c_device_address   <= PMIC;
+                        inlim                <= i2c_miso_data;
+                        i2c_mosi_data        <= 8'h20;
+                        txActive             <= 1'd0;
+                    end
+                    else
+                        i2c_enable           <= 'd1;
+            end
+            S_CHARGEWRITE:
+            begin
+                if(i2c_busy)
+                begin
+                    txActive         <= 1'd1;
+                    i2c_enable       <= 'd0;
+                end
+                else
+                    if(txActive)
+                    begin
+                        i2c_read_write       <= 'd1; // Read
+                        state                <= S_CHARGEREAD;
+                        i2c_register_address <= 8'd02; // Charge Current Control
+                        i2c_device_address   <= PMIC;
+                        txActive             <= 1'd0;
+                    end
+                    else
+                        i2c_enable           <= 'd1;
+            end
+            S_CHARGEREAD:
+            begin
+                if(i2c_busy)
+                begin
+                    txActive         <= 1'd1;
+                    i2c_enable       <= 'd0;
+                end
+                else
+                    if(txActive)
+                    begin
+                        state                <= S_IDLE;
+                        txActive             <= 1'd0;
+                        chargeCurrent        <= i2c_miso_data;
+                    end
+                    else
+                        i2c_enable           <= 'd1;
+            end
+            endcase
+    end
+
+endmodule

ModRetro_oss-chromatic-console-fpga/esp32t/src/rtl/BSP/qspi_slave.v

@@ -0,0 +1,116 @@
+// QSPI_Slave.v
+
+module QSPI_Slave(
+    input               QSPI_CLK,
+    input               QSPI_CS,
+    input               QSPI_MOSI,
+    input               QSPI_MISO,
+    input               QSPI_WP,
+    input               QSPI_HD,
+    
+    output              qMenuInit,
+    output              qDataValid,
+    output      [15:0]  qData,
+    output  reg [31:0]  qAddress = 'd0,
+    output  reg [9:0]   qLength = 'd0,
+    output  reg         qCommand = 'd0
+);
+
+    reg qAddReady = 'd0;
+    reg qLenReady = 'd0;
+
+    reg [3:0] qPins_r1 = 'd0;
+    reg [7:0] qDataByte = 'd0;
+    reg qCyclePhase = 'd0;
+
+    reg qValid = 'd0;
+    wire [3:0] qPins = {
+                    QSPI_HD,
+                    QSPI_WP,
+                    QSPI_MISO,
+                    QSPI_MOSI};
+
+    reg [7:0] qCycleCount = 'd0;
+
+    reg qMenuInit1 = 1'd0;
+    reg qMenuInit2 = 1'd0;
+    assign qMenuInit = qMenuInit2;
+
+    always@(posedge QSPI_CLK or posedge QSPI_CS)
+    begin
+        if(QSPI_CS)
+        begin
+            qCyclePhase <= 1'd0;
+            qValid      <= 1'd0;
+            qCycleCount <= 1'd0;
+            qCommand    <= 1'd0;
+            qAddReady   <= 1'd0;
+            qLenReady   <= 1'd0;
+        end
+        else
+        begin
+            if(qCycleCount <= 50)
+                qCycleCount   <= qCycleCount + 1'd1;
+            
+            // Command
+            if(qCycleCount == 0)
+                qCommand <= QSPI_MOSI;
+
+            if((qCycleCount >= 1) && (qCycleCount <= 10))
+                qLength <= {qLength[8:0], QSPI_MOSI};
+                
+            if((qCycleCount >= 11) && (qCycleCount <= 42))
+                qAddress <= {qAddress[30:0], QSPI_MOSI};
+                
+            if(qCycleCount == 11)
+                qLenReady <= 1'd1;
+            else
+                qLenReady <= 1'd0;
+
+            if(qCycleCount == 43)
+            begin
+                qAddReady <= 1'd1;
+                if(qAddress == 0) // first row
+                begin
+                    qMenuInit1  <=  1'd1;
+                    if(qMenuInit1)
+                        qMenuInit2 <= 1'd1;
+                end
+            end
+            else
+                qAddReady <= 1'd0;
+                
+            // QSPI data
+            if(qCycleCount >= 46)
+            begin
+                qCyclePhase      <= ~qCyclePhase;
+                if(qCyclePhase)
+                begin
+                    qDataByte   <= {qPins_r1,qPins};
+                    qValid      <= 1'd1;
+                end
+                else
+                begin
+                    qPins_r1    <= qPins;
+                    qValid      <= 1'd0;
+                end
+            end
+        end
+    end
+
+    reg [7:0] qDataByte_r1 = 'd0;
+    reg QSPI_VALID_phase = 'd0;
+    always@(posedge QSPI_CLK or posedge QSPI_CS)
+        if(QSPI_CS)
+            QSPI_VALID_phase <= 'd0;
+        else
+            if(qValid)
+            begin
+                qDataByte_r1 <= qDataByte;
+                QSPI_VALID_phase <= ~QSPI_VALID_phase;
+            end
+
+    assign qDataValid = qValid&QSPI_VALID_phase;
+    assign qData = {qDataByte,qDataByte_r1};
+
+endmodule

ModRetro_oss-chromatic-console-fpga/esp32t/src/rtl/BSP/system_monitor.sv

@@ -0,0 +1,519 @@
+// system_monitor.v
+
+module system_monitor(
+    input               clk,
+    input               reset,
+    input               BTN_A,
+    input               BTN_B,
+    input               BTN_DPAD_DOWN,
+    input               BTN_DPAD_LEFT,
+    input               BTN_DPAD_RIGHT,
+    input               BTN_DPAD_UP,
+    input               BTN_MENU, // pressed = 0
+    input               BTN_SEL,
+    input               BTN_START,
+    // Controls external mux into ADC
+    output  reg         menuDisabled,
+    output  reg         ADC_SEL,
+    output  reg         hAdcReq_ext,
+    input               LCD_INIT_DONE,
+    output  reg         LCD_PWM,
+    output  reg         LCD_BACKLIGHT_INIT = 1'd0,
+    input               hAdcReady_r1,
+    input   [13:0]      hAdcValue_r1,
+    input   [8:0]       hButtons,
+    output  reg [8:0]   MCU_buttons,
+    input   [6:0]       hVolume,
+    input   [7:0]       pmic_sys_status,
+    input               hHeadphones,
+    input               gSecondEna,
+    input               gHalfSecondEna,
+    output  reg         low_battery,
+    output  reg         LED_Green,
+    output  reg         LED_Red,
+    output  reg         LED_Yellow,
+    output  reg         LED_White,
+    output  reg [15:0]  system_control,
+    output  reg [31:0]  debug_system,
+    output  reg [63:0]  paletteBGIn,
+    output  reg [63:0]  paletteOBJ0In,
+    output  reg [63:0]  paletteOBJ1In,
+    input               gbc_mode,
+    input   [63:0]      gpd,
+    input   [7:0]       uart_rx_data,
+    input               uart_rx_val,
+    input               uart_tx_busy,
+    output  [7:0]       uart_tx_data,
+    output              uart_tx_val
+);
+
+    wire    [6:0]   rx_address;
+    wire    [79:0]  rx_data;
+    wire            rx_data_val;
+
+    reg [15:0] btnMenu_sr;
+    reg btnMenu_r1;
+    reg btnMenu_r2;
+
+    reg [15:0] btnDown_sr;
+    reg btnDown_r1;
+    reg btnDown_r2;
+
+    reg [15:0] btnUp_sr;
+    reg btnUp_r1;
+    reg btnUp_r2;
+
+    reg [15:0] btnLeft_sr;
+    reg btnLeft_r1;
+    reg btnLeft_r2;
+
+    reg [15:0] btnRight_sr;
+    reg btnRight_r1;
+    reg btnRight_r2;
+
+    reg btnStart_r1;
+    reg btnStart_r2;
+    reg btnSelect_r1;
+    reg btnSelect_r2;
+    reg btnA_r1;
+    reg btnA_r2;
+    reg btnB_r1;
+    reg btnB_r2;
+
+    reg pressed;
+    reg [3:0] brightness = 4'd3;
+    reg [1:0] blockBrightnessReceive;
+
+    reg request_buttons  = 1'b0;
+    reg request_version  = 1'b0;
+    reg updateBrightness = 1'b0;
+    reg request_gpd     = 1'b0;
+
+    reg lowpowerBacklight = 1'b0;
+    reg [3:0] lowerpowerOldBL;
+    reg request_SystemStatusExtended = 1'b0;
+
+    reg [13:0] volt;
+    wire       bat_is_LI;
+
+    always@(posedge clk or posedge reset)
+    begin
+        if(reset) begin
+            system_control <= 16'd0;
+            MCU_buttons    <= 9'd0;
+            request_gpd   <= 1'b0;
+        end else begin
+            request_buttons              <= 1'b0;
+            request_version              <= 1'b0;
+            updateBrightness             <= 1'b0;
+            request_SystemStatusExtended <= 1'b0;
+
+            if (gHalfSecondEna) begin
+               LCD_BACKLIGHT_INIT  <= 1'd1;
+            end
+
+            if(rx_data_val)
+            begin
+                if(rx_address == 7'hD) begin
+                    request_gpd <= 1'b1;
+                end
+                if(rx_address == 7'hC) begin
+                    if (rx_data[63]) begin
+                        paletteOBJ1In <= rx_data[63:0];
+                    end else begin
+                        paletteOBJ0In <= rx_data[63:0];
+                    end
+                end
+                if(rx_address == 7'hB) begin
+                    paletteBGIn <= rx_data[63:0];
+                end
+                if(rx_address == 7'd9) begin
+                    MCU_buttons <= rx_data[8:0];
+                end
+                if(rx_address == 7'd6) begin
+                    request_version <= 1'b1;
+                end
+                if(rx_address == 7'd5) begin
+                    if (blockBrightnessReceive == 2'd0) begin
+                        brightness      <=  rx_data[13:0];
+                    end else begin
+                        blockBrightnessReceive <= blockBrightnessReceive - 1;
+                    end
+                end
+                if(rx_address == 7'd4) begin
+                    system_control  <=  rx_data[15:0];
+                end
+                if(rx_address == 7'd2) begin
+                    request_buttons <= 1'b1;
+                end
+            end
+
+            if (menuDisabled) begin
+                if((btnLeft_sr[15:0] == 16'h8000)&&~btnMenu_r2) begin
+                    if(brightness >= 1)
+                    begin
+                        brightness <= brightness - 9'd1;
+                        pressed <= 1'd0;
+                        blockBrightnessReceive <= 2'd3;
+                        updateBrightness <= 1'b1;
+                    end
+                end
+                if((btnRight_sr[15:0] == 16'h8000)&&~btnMenu_r2) begin
+                    if(brightness != 15)
+                    begin
+                        pressed <= 1'd0;
+                        brightness <= brightness + 9'd1;
+                        blockBrightnessReceive <= 2'd3;
+                        updateBrightness <= 1'b1;
+                    end
+                end
+            end
+
+            if (lowpowerBacklight) begin
+               brightness       <= 4'd0;
+               updateBrightness <= 1'b0;
+            end
+
+            if (volt >= 700) begin // ~1.8V
+               if (~lowpowerBacklight && ~bat_is_LI && volt < 979) begin // below 2.55 V
+                  request_SystemStatusExtended <= 1'b1;
+                  lowpowerBacklight            <= 1'b1;
+                  lowerpowerOldBL              <= brightness;
+               end
+
+               if (lowpowerBacklight && ~bat_is_LI && volt > 1293) begin // above 3.4 V
+                  request_SystemStatusExtended <= 1'b1;
+                  lowpowerBacklight            <= 1'b0;
+                  brightness                   <= lowerpowerOldBL;
+               end
+            end
+
+            if (write_done && tx_channel == 9 && request_gpd) begin
+                request_gpd <= 1'b0; // Clear after sending once
+            end
+
+        end
+    end
+
+    reg menuDown = 1'b0;
+    always@(posedge clk)
+    begin
+        if(reset) begin
+            menuDisabled <= 1'b1;
+        end else begin
+            btnMenu_r1 <= BTN_MENU;
+            btnMenu_r2 <= btnMenu_r1;
+            btnMenu_sr <= {btnMenu_sr[14:0], btnMenu_r2};
+            if(btnMenu_sr[15:0] == 16'h8000) begin
+               menuDown <= 1'b1;
+            end
+            if(btnMenu_sr[15:0] == 16'h7FFF && menuDown) begin
+               menuDisabled <= ~menuDisabled;
+               menuDown     <= 1'b0;
+            end
+
+            if (btnA_r2 | btnB_r2 | btnDown_r2 | btnUp_r2 | btnLeft_r2 | btnRight_r2 | btnSelect_r2 | btnStart_r2) menuDown <= 1'b0;
+
+            btnDown_r1 <= BTN_DPAD_DOWN;
+            btnDown_r2 <= btnDown_r1;
+            btnDown_sr <= {btnDown_sr[14:0], btnDown_r2};
+
+            btnUp_r1 <= BTN_DPAD_UP;
+            btnUp_r2 <= btnUp_r1;
+            btnUp_sr <= {btnUp_sr[14:0], btnUp_r2};
+
+            btnLeft_r1 <= BTN_DPAD_LEFT;
+            btnLeft_r2 <= btnLeft_r1;
+            btnLeft_sr <= {btnLeft_sr[14:0], btnLeft_r2};
+
+            btnRight_r1 <= BTN_DPAD_RIGHT;
+            btnRight_r2 <= btnRight_r1;
+            btnRight_sr <= {btnRight_sr[14:0], btnRight_r2};
+
+            btnSelect_r1 <= BTN_SEL;
+            btnSelect_r2 <= btnSelect_r1;
+
+            btnStart_r1 <= BTN_START;
+            btnStart_r2 <= btnStart_r1;
+
+            btnA_r1 <= BTN_A;
+            btnA_r2 <= btnA_r1;
+
+            btnB_r1 <= BTN_B;
+            btnB_r2 <= btnB_r1;
+
+        end
+    end
+
+    reg [7:0] lcdcount;
+    always@(posedge clk)
+        if(lcdcount < 448)
+            lcdcount <= lcdcount + 1'd1;
+        else
+            lcdcount <= 'd0;
+
+    assign LCD_PWM = LCD_INIT_DONE&LCD_BACKLIGHT_INIT ? (lcdcount <= {brightness[3:0], 4'd0}) : 1'd0;
+
+
+    // 8.388608Mhz clock -> ~119.2ns
+    // 0.005s / 119.2ns = 41946
+
+    localparam ADC_INTERVAL_CYCLES = 'd41946;
+    reg [15:0] adc_timer;
+    reg [9:0] startup_cnt;            // wait for ~4 seconds to have stable measurements
+    reg signed [10:0] startup_select; // measure if AA or lithium is used, negative -> LI, positive -> AA
+    reg startup_done = 1'b0;
+
+    always@(posedge clk) begin
+        if(adc_timer < ADC_INTERVAL_CYCLES) begin
+            adc_timer <= adc_timer + 1'd1;
+            hAdcReq_ext <= 'd0;
+            // Toggle the mux slightly ahead of starting the measurement
+            if (startup_done) begin
+                ADC_SEL <= startup_select[10];
+            end else if(adc_timer == ADC_INTERVAL_CYCLES - 1000) begin
+                ADC_SEL <= ~ADC_SEL;
+            end
+        end else begin
+            adc_timer <= 'd0;
+            hAdcReq_ext <= 'd1;
+        end
+    end
+
+   assign     bat_is_LI = startup_select[10];
+   reg [21:0] volt_sum;
+   reg [8:0]  volt_cnt;
+   reg        transmitVolt;
+
+   wire [13:0] VOLTAGE_FULL   = bat_is_LI ? 14'd1423 : 14'd1367; //  3.75V LI : 3.6V AA
+   wire [13:0] VOLTAGE_CRIT   = bat_is_LI ? 14'd1145 : 14'd997;  //  3.0V  LI : 2.6V AA
+   wire [13:0] VOLTAGE_RED    = bat_is_LI ? 14'd1182 : 14'd1071; //  3.1V  LI : 2.8V AA
+
+   reg blink;
+
+   always@(posedge clk or posedge reset) begin
+
+      if(reset) begin
+         low_battery    <= 1'd0;
+         LED_Red        <= 1'd0;
+         LED_Green      <= 1'd0;
+         LED_Yellow     <= 1'd0;
+         blink          <= 1'd0;
+         volt           <= 14'd0;
+         volt_sum       <= 22'd0;
+         volt_cnt       <=  9'd0;
+         startup_cnt    <= 11'd0;
+         startup_select <= 11'd0;
+         startup_done   <= 1'b0;
+         transmitVolt   <= 1'b0;
+      end else begin
+
+         transmitVolt <= 1'b0;
+
+         debug_system <= {1'd0 , startup_select,  6'd0, volt };
+
+         if(hAdcReady_r1) begin
+            if (~startup_cnt[9]) begin // wait for ~4 seconds to have stable measurements
+               startup_cnt <= startup_cnt + 1'd1;
+            end
+
+            if (startup_done) begin // average values for determined type only
+               volt_sum <= volt_sum + hAdcValue_r1;
+               volt_cnt <= volt_cnt + 1;
+            end else if (startup_cnt[9] && hAdcValue_r1 >= 700) begin // measure if AA or lithium is used, negative -> LI, positive -> AA
+               if (ADC_SEL) begin
+                  startup_select <= startup_select - 1'd1;
+               end else begin
+                  startup_select <= startup_select + 1'd1;
+               end
+            end
+
+            if (startup_select > 11'sd127 || startup_select < -11'sd127) begin // determine type based on which delivered higher values for some seconds
+               startup_done <= 1'b1;
+            end
+         end
+
+         if (volt_cnt[8]) begin
+            volt_sum    <= 22'd0;
+            volt_cnt    <=  9'd0;
+            volt        <= volt_sum[21:8];
+            transmitVolt <= 1'b1;
+         end
+
+         if (gSecondEna) blink <= ~blink;
+
+         low_battery <= 1'd0;
+         LED_Red     <= 1'd0;
+         LED_Green   <= 1'd0;
+         LED_Yellow  <= 1'd0;
+         LED_White   <= 1'd0;
+
+         if (volt >= 700) begin // ~1.8V
+
+            if (pmic_sys_status[2]) begin // charging
+
+               if(bat_is_LI && volt < VOLTAGE_FULL) begin
+                  LED_White   <= 1'd1;
+               end
+
+            end else begin
+
+               if(volt < VOLTAGE_RED) begin
+                  low_battery <= 1'd1;
+                  if (blink) LED_Red <= 1'd1;
+               end
+
+            end
+
+         end
+      end
+   end
+
+    wire [6:0] tx_address;
+    wire       write;
+
+    wire [13:0] buttons = {
+        4'd0,
+        menuDisabled,
+        ~BTN_MENU,
+        BTN_DPAD_DOWN,
+        BTN_DPAD_LEFT,
+        BTN_DPAD_RIGHT,
+        BTN_DPAD_UP,
+        BTN_A,
+        BTN_B,
+        BTN_SEL,
+        BTN_START
+    };
+
+    reg [13:0] version = {
+        1'd0,  // 1 bit reserved
+        1'd0,  // 1 bit debug,
+        6'd8,  // 6 bits minor version
+        6'd18  // 6 bits major version
+    };
+
+    localparam  NUM_CH = 10;
+    wire [$clog2(NUM_CH)-1:0] tx_channel;
+
+    wire [NUM_CH-1:0] channelsNewDataValid =
+    {
+        request_gpd,                                  // Game Palette Data
+        ~menuDisabled | request_SystemStatusExtended, // System Status Extended
+        ~menuDisabled,                                // reserved
+        ~menuDisabled | request_version,              // version info
+        ~menuDisabled,                                // pmic sys status
+        ~menuDisabled,                                // System Control
+        ~menuDisabled | updateBrightness,             // Audio + Brightness
+        ~menuDisabled | request_buttons,              // Buttons
+        (~menuDisabled & transmitVolt & bat_is_LI),   // Lithium
+        (~menuDisabled & transmitVolt & ~bat_is_LI)   // AA
+    };
+
+    wire [13:0] audio_brightness = {2'd0, brightness, hHeadphones, hVolume};
+    wire [13:0] mic_sys_status = {6'd0 , pmic_sys_status};
+
+    wire [7:0] tx_byteCount = (tx_channel == 0) ? 8'd2 : // AA
+                              (tx_channel == 1) ? 8'd2 : // Lithium
+                              (tx_channel == 2) ? 8'd2 : // Buttons
+                              (tx_channel == 3) ? 8'd2 : // Audio + Brightness
+                              (tx_channel == 4) ? 8'd2 : // System Control
+                              (tx_channel == 5) ? 8'd2 : // pmic sys status
+                              (tx_channel == 6) ? 8'd2 : // version info
+                              (tx_channel == 7) ? 8'd4 : // reserved
+                              (tx_channel == 8) ? 8'd4 : // System Status Extended
+                              (tx_channel == 9) ? 8'd8 : // BG Palette Data
+                              8'd1;
+
+    wire [7:0] tx_bytepos;
+
+    wire [7:0] tx_senddata = (tx_channel == 0 && tx_bytepos == 0) ? {2'd0, volt[13:8]} : // AA
+                             (tx_channel == 0 && tx_bytepos == 1) ? volt[7:0] :
+
+                             (tx_channel == 1 && tx_bytepos == 0) ? {2'd0, volt[13:8]} : // Lithium
+                             (tx_channel == 1 && tx_bytepos == 1) ? volt[7:0] :
+
+                             (tx_channel == 2 && tx_bytepos == 0) ? {2'd0, buttons[13:8]} : // Buttons
+                             (tx_channel == 2 && tx_bytepos == 1) ? buttons[7:0] :
+
+                             (tx_channel == 3 && tx_bytepos == 0) ? {2'd0, audio_brightness[13:8]} : // Audio + Brightness
+                             (tx_channel == 3 && tx_bytepos == 1) ? audio_brightness[7:0] :
+
+                             (tx_channel == 4 && tx_bytepos == 0) ? {2'd0, system_control[13:8]} : // System Control
+                             (tx_channel == 4 && tx_bytepos == 1) ? system_control[7:0] :
+
+                             (tx_channel == 5 && tx_bytepos == 0) ? {2'd0, mic_sys_status[13:8]} : // pmic sys status
+                             (tx_channel == 5 && tx_bytepos == 1) ? mic_sys_status[7:0]  :
+
+                             (tx_channel == 6 && tx_bytepos == 0) ? {2'd0, version[13:8]} : // version info
+                             (tx_channel == 6 && tx_bytepos == 1) ? version[7:0] :
+
+                             (tx_channel == 7 && tx_bytepos == 0) ? 8'd0 : // reserved
+                             (tx_channel == 7 && tx_bytepos == 1) ? 8'd0 :
+                             (tx_channel == 7 && tx_bytepos == 2) ? 8'd0 :
+                             (tx_channel == 7 && tx_bytepos == 3) ? 8'd0 :
+
+                             (tx_channel == 8 && tx_bytepos == 0) ? {6'd0, gbc_mode, lowpowerBacklight} : // System Status Extended
+                             (tx_channel == 8 && tx_bytepos == 1) ? 8'd0 :
+                             (tx_channel == 8 && tx_bytepos == 2) ? 8'd0 :
+                             (tx_channel == 8 && tx_bytepos == 3) ? 8'd0 :
+
+                             (tx_channel == 9 && tx_bytepos == 0) ? gpd[7:0] : // Combined Game Palette Data
+                             (tx_channel == 9 && tx_bytepos == 1) ? gpd[15:8] :
+                             (tx_channel == 9 && tx_bytepos == 2) ? gpd[23:16] :
+                             (tx_channel == 9 && tx_bytepos == 3) ? gpd[31:24] :
+                             (tx_channel == 9 && tx_bytepos == 4) ? gpd[39:32] :
+                             (tx_channel == 9 && tx_bytepos == 5) ? gpd[47:40] :
+                             (tx_channel == 9 && tx_bytepos == 6) ? gpd[55:48] :
+                             (tx_channel == 9 && tx_bytepos == 7) ? gpd[63:56] :
+                             8'd0;
+
+    wire uartDisabled;
+
+    system_monitor_arbiter
+    #(
+        .NUM_CH(NUM_CH)
+    ) u_system_monitor_arbiter
+    (
+        .clk(clk),
+        .reset(reset),
+        .uartDisabled(uartDisabled),
+        .menuDisabled(menuDisabled),
+        .channelsNewDataValid(channelsNewDataValid),
+        .uart_tx_busy(uart_tx_busy),
+        .tx_address(tx_address),
+        .tx_channel(tx_channel),
+        .write_done(write_done),
+        .write(write)
+    );
+
+    uart_packet_wrapper_tx u_uart_packet_wrapper_tx
+    (
+        .clk(clk),
+        .reset(reset),
+        .uart_tx_busy(uart_tx_busy),
+        .uart_tx_data(uart_tx_data),
+        .uart_tx_val(uart_tx_val),
+        .uartDisabled(uartDisabled),
+        .menuDisabled(menuDisabled),
+        .write(write),
+        .write_done(write_done),
+        .tx_address(tx_address),
+        .tx_byteCount(tx_byteCount),
+        .tx_bytepos(tx_bytepos),
+        .tx_senddata(tx_senddata)
+    );
+
+    uart_packet_wrapper_rx u_uart_packet_wrapper_rx
+    (
+        .clk(clk),
+        .reset(reset),
+        .uart_rx_val(uart_rx_val),
+        .uart_rx_data(uart_rx_data),
+        .uartDisabled(uartDisabled),
+        .rx_address(rx_address),
+        .rx_data(rx_data),
+        .rx_data_val(rx_data_val)
+    );
+
+endmodule

ModRetro_oss-chromatic-console-fpga/esp32t/src/rtl/BSP/system_monitor_arbiter.sv

@@ -0,0 +1,106 @@
+
+module system_monitor_arbiter
+#(
+    parameter   NUM_CH = 8
+)
+(
+    input                            clk,
+    input                            reset,
+    input       [NUM_CH-1:0]         channelsNewDataValid,
+    input                            menuDisabled,
+    input                            uart_tx_busy,
+    input                            write_done,
+    output                           uartDisabled,
+    output      [$clog2(NUM_CH)-1:0] tx_channel,
+    output  reg [6:0]                tx_address = 'd0,
+    output  reg                      write
+);
+
+    reg         channelsDataRefreshRequest [NUM_CH-1:0] = '{default: 0};    
+    reg [$clog2(NUM_CH)-1:0]    active_channel = 'd0;
+    reg [$clog2(NUM_CH)-1:0]    next_channel = 'd0;
+    reg                         write_active;
+    reg                         arbiter_active;
+    reg                         button_next = 1'b0;
+    
+    
+    assign tx_channel = active_channel;
+    
+    genvar g;
+    generate
+        for(g = 0; g < NUM_CH; g++)
+        begin : channels
+            always@(posedge clk)
+            begin
+                if(channelsNewDataValid[g])
+                begin
+                    channelsDataRefreshRequest[g] <= 1'd1;
+                end
+                else
+                    if((active_channel == g)&&(write_done))
+                        channelsDataRefreshRequest[g] <= 1'd0;
+            end
+        end
+    endgenerate
+    
+    assign  uartDisabled = ~arbiter_active;
+    always@(posedge clk or posedge reset)
+    begin
+        if(reset)
+        begin
+            active_channel <= 'd0;
+            write          <= 'd0;
+            write_active   <= 'd0;
+            arbiter_active <= 'd0;
+        end
+        else
+        begin
+            arbiter_active <= 1'd1;
+                
+            if((channelsDataRefreshRequest[active_channel] == 'd0) & arbiter_active)
+            begin
+                if(active_channel < NUM_CH - 1)
+                    active_channel <= active_channel + 1'd1;
+                else
+                    active_channel <= 'd0;
+            end
+            else
+            begin
+                if(~write_active & arbiter_active)
+                begin
+                    if(~uart_tx_busy)
+                    begin
+                        write_active    <= 1'd1;
+                        write           <= 1'd1;
+                        tx_address      <= active_channel;
+                    end
+                end
+                else
+                begin
+                    write   <=  1'd0;
+                    if(write_done)
+                    begin
+                        if(menuDisabled)
+                            arbiter_active <= 1'd0;
+                        
+                        write_active    <= 1'd0;
+
+                        button_next <= ~button_next;
+                        if (button_next) begin
+                            active_channel <= 'd2;
+                        end else begin
+                            if(next_channel < NUM_CH - 1) begin
+                                next_channel   <= next_channel + 1'd1;
+                                active_channel <= next_channel + 1'd1;
+                            end else begin
+                                next_channel   <= 'd0;
+                                active_channel <= 'd0;
+                            end
+                        end
+                    end
+                end
+            end
+        end
+    end
+
+endmodule

ModRetro_oss-chromatic-console-fpga/esp32t/src/rtl/BSP/tlv320_init.v

@@ -0,0 +1,90 @@
+// tlv320_init.v
+// Contains a ROM with a default register set, masters I2C controller
+
+module tlv320_init#(
+    parameter I2C_DATA_WIDTH = 8,
+    parameter REGISTER_WIDTH = 8,
+    parameter ADDRESS_WIDTH = 7
+
+)(
+    input                                   pclk,
+    input                                   vb_rst,
+    input                                   i2c_busy,
+    
+    output  reg                             tlv320_init_done,
+    output  reg                             i2c_enable,
+    output  reg                             i2c_read_write,
+    output  reg     [I2C_DATA_WIDTH-1:0]    i2c_mosi_data,
+    output  reg     [REGISTER_WIDTH-1:0]    i2c_register_address,
+    output  reg     [ADDRESS_WIDTH-1:0]     i2c_device_address
+    
+);
+
+    localparam numregs = 64; 
+    localparam numregsactual = 64; 
+    reg [15:0] tlv320regs [numregs-1:0] /* synthesis syn_romstyle = "distributed_rom" */;
+    initial
+    begin
+        $readmemh("tlv320regs.hex", tlv320regs);
+    end
+
+    reg [7:0] scount;
+    reg [7:0] regindex;
+    reg [23:0] regvalue;
+    always@(posedge pclk)
+        regvalue <= tlv320regs[regindex];
+        
+    always@(posedge pclk)
+    begin
+        if(vb_rst)
+        begin
+            scount               <= 'd0;
+            i2c_read_write       <= 'd0;
+            i2c_register_address <= 'd0;
+            i2c_mosi_data        <= 'd0;
+            i2c_device_address   <= 'd0;
+            i2c_enable           <= 'd0;
+            regindex             <= 'd0;
+            tlv320_init_done     <= 'd0;
+        end
+        else
+            case(scount)
+            0:
+            begin
+                i2c_read_write       <= 'd0;
+                i2c_register_address <= regvalue[15:8];
+                i2c_mosi_data        <= regvalue[7:0];
+                i2c_device_address   <= 7'h18;
+                i2c_enable           <= 'd0;
+                scount               <= scount + 1'd1;
+            end
+            1:
+                // if master is not busy start a write
+                if(~i2c_busy)
+                begin
+                    i2c_enable           <= 'd1;
+                    scount               <= scount + 1'd1;
+                end
+            2:
+                // once busy set enable low
+                if(i2c_busy)
+                begin
+                    i2c_enable           <= 'd0;
+                    scount               <= scount + 1'd1;
+                end
+            3:
+                // if master is not busy start next write
+                if(~i2c_busy)
+                begin
+                    if(regindex < numregsactual)
+                    begin
+                        scount               <= 'd0;
+                        regindex             <= regindex + 1'd1;
+                    end
+                    else
+                        tlv320_init_done     <= 1'd1;
+                end
+            endcase
+    end
+
+endmodule

ModRetro_oss-chromatic-console-fpga/esp32t/src/rtl/BSP/uart/fixed_point_divider/fixed_point_divider.v

@@ -0,0 +1,1034 @@
+//
+//Written by GowinSynthesis
+//Product Version "GowinSynthesis V1.9.7.02Beta"
+//Mon May 10 08:46:21 2021
+
+//Source file index table:
+//file0 "\C:/Gowin/Gowin_V1.9.7.02Beta/IDE/ipcore/DIVIDER/data/div_wrap.v"
+//file1 "\C:/Gowin/Gowin_V1.9.7.02Beta/IDE/ipcore/DIVIDER/data/qdiv.v"
+`timescale 100 ps/100 ps
+`pragma protect begin_protected
+`pragma protect version=1
+`pragma protect author="default"
+`pragma protect author_info="default"
+`pragma protect encrypt_agent="Synplify encryptP1735.pl"
+`pragma protect encrypt_agent_info="Synplify encryptP1735.pl Version 1.1"
+
+`pragma protect encoding=(enctype="base64", line_length=76, bytes=256)
+`pragma protect key_keyowner="Synplicity",key_keyname="SYNP05_001",key_method="rsa"
+`pragma protect key_block
+cPxCVdqShOKMVODCtgrX+saJA4lUi6pqLB/etOubKoIdCF8IrYOcExBq/0AkWHaLUjVBousKuzG0
+S4fQfBaqJLZnAC82l+T0u9WmrqOXlT2IOUDldwjB7LzHmMp4YfKWZzr5I6w8+8yzOnQ7mtp/0pEE
+XcYyjhFQqXo/2XF1NIAK0zpErSoPFqddhcmsh8QsByB7ElvKzi6mN37AEm9cOudVnrFac+0O9D27
+yajVKSMhqua+xXsISR3edP53Sf4BpLFZEg+MdP04nrCYQ0DpNo51TUXUa+EIuY1KRVgkMvYUN4UF
+mKzo34Urj1sgE8iFK8AkFSKOlFUyadE8d2PSCA==
+
+`pragma protect encoding=(enctype="base64", line_length=76, bytes=256)
+`pragma protect key_keyowner="GoWin",key_keyname="GoWin001",key_method="rsa"
+`pragma protect key_block
+Iw3lr6I/oWZcWltqZAe9KSWENcaLkk8/jTQH2Mn8DS1KghgJ6Bg7I6CPnLpTr8UL8YpJOW6k3fUI
+WM2rSpWrPFxFxCG3Kk0xDRh4BW8AlJhcTpU23K3aoLESkSW/QwBustwHoAr6jdwxlEnwjUcEut5s
+kIUfn2xU2MZn144DTqfFXdn6NISuvGVAi+yP9ek5AYIzJ9cmy7aA/XoHxQCr20XnCr6j3hK3E4m2
+AppW89TDhOd+uu712G8RkIl2qutqW9yH0kFLDkmn2vzdZC0MPbYJpPBp8wufw+FuDF/b7VqLJLVj
+7SFr1enRbf3V1b4PHQBnBNW+hNHXQUiiQwJ65w==
+
+`pragma protect encoding=(enctype="base64", line_length=76, bytes=54608)
+`pragma protect data_keyowner="default-ip-vendor"
+`pragma protect data_keyname="default-ip-key"
+`pragma protect data_method="aes128-cbc"
+`pragma protect data_block
+EA4aT09nCsww/OO6RGfoGejTtTTgFHa0PFigO8OFdvGI1fOWv+CIXSV0MBtrCJbN24j9k+Bcq+3u
+jN1J9lf4BEbCT/uNsvEBOBKzjZAYMFh4upXQQ7KAXV0P4QRTrsh+3rwCx9yoK7AwuoNlE0pHuLKr
+8J73SF4OMYaVLbSqmqhnskCKh/fikmM/CiJkHse700iJo/oU/5W8PhtmeN/fsxPWKaBmJIZ3qmdV
+bXWZb4PXEYgQZveyui/FdBc+ZrGJFZlomo5J2u2IYPisjffjV956T87PwLiGwaemTd83QX38HfIU
+u2W+lzQcoVWSBYB/VQC0XN/eu23hDflFzVThpNsVTD7ZCT7xdPx7Hjzc84mSwPXeN4TB4/Y1/SlY
+8LmbrB11NvCVBFN3d/rmxhN5bWUnVexyOX7/nGCU0q6yeV3Z+ZuR3iDdag92R2l87j6VPXj8a7LA
+qrLalPlL1nlBLDD3kFZ72e0uFWN5eOmZsi4naFQxWERizSrFa+xE9ZpPuqPPYkkzWvCwk4jy14Zn
+gdXLg14KxP2q5GWIt7PgvCe/0BY9Rc92I9DuUW5MxGo3Ss+jwsVXhbz7myVAJER9QpGCL4D8P98B
+3ZRCVzIr8e7dBPVbVcIpy7zJ4ytdVWr5XJuwFdevKgJsuIZKitaWxB6O1cpUBiY7malgYsXUZXGy
+FNOIG5xDaGdjsxDdobYyKzgu0NeQWJGe/oqk2aeBxeNebx75TMAy8E4ZyY8sNzjgOIeDuu4VIfrC
+Io1S2VmJuDQWKVk0PYG1qpj9fHz7kIB5olSO4rKjz1wVQfpwOqIU2BOddJJfygC3AKA3Gd7M8neu
+OPxav/8jhIFOb2pbbjXvr3QP1mVlhj2r7O01Q6DJW5LM3xj/KXE7QK9V+yKp8Jh9nJ2ts5ZdmEYV
+rMDZ+Pu3eCV77sibxTKhDQhMneslwILWnx3he6HQ6crmWUYvLxhJjTP/ZR0wsmbJNISuZmo7c19F
+tIzOB1hl6eH9qR1/uwU0MTLrXeXggjuTJYu7Sf9WjcqKKjLbqEibDJTLBbdDOHLBq/302I4G+53j
+JxEznBUG0WKKB0U+AIYpbNjCsc5J0j0GBvNy+r/z6CrRI+z8oVsDDvyFxjrpZk8/UY69x7+Q6FLT
+1mDfA//b+71SoxCp5AuDBqYUJ5KDIcBeVbrY7OiWiS197NYE0ithKppNhlXsuFfKfagQyUWt/Ns2
+aP4Iph+FYVORky56sPcsAcMszMgALHy/e5VsOC22HGUlswGXFfgXeCEDkDFKhsAC5e9JGF9CqoGU
+DA7veL5EUUf9Ck/uCojE8RPjswZ8K/sl419oBLXTEwBoTiWueymrYQ2roYXjGyJGcEVGhTl/Ljpz
+AdyGOkmXG+9ceWwzq5r6if5KRnbIuXy5djuQVq4b051zjJEEz6gmTZvVtsDzvk50nM+1V6YYFufx
+CB72d1rzHGb90u74Kk6TAW0KKNDUomfKqlmjItysK035e9+UkcFRhqOW3iY6Y6C5vzqe5P5pznXI
+e1drkSEwfgfghn5pUEl01idVFnXx9TPVv7dnMMuQ2ZbwRtBGQ6EqaCiFRZyb4vxT4wDLdFXouUXi
+OJnjKh/+NthYn1xGq+2eq8wjfq9EZxxg+RS0x5ftuf5AGAdm29jpEQef61a5GXVTwERzVEQcpQUa
+dQLXWsr0GAxt/3ZEw5wuestckwFkr9B3CmTbqggpVy9dvhovy37qEYB2kByWOZvgDkQSiPeLYoMe
+QIJxDgAvyPIg12UrKoq0y+OLhidTnw9eKs8VWnXEMj7JHPoxmRjz2UVo8HUr4Vy+o6RPjbSMMxZ1
+F6gH/O/qPNHN/yeqqmt9imaEeqW4kB9XlaeEasUm51EqPwuieioGZqq/baGG2iNmBH8OOJQpPrds
+7BETRjzLnczJsgOLSUrOXoclVKVavQDtnm//CaJDjN7iofjpXY5KIIWntqEa/s+q+1EUSrVKwly9
+t7Cm24c7iJAsBcytkLbLz40IDNZgZ0l4VyfGlwqO0it3Ni0SGGir+2+iJQz5ZuMv8miTqv4GqO5P
+ke2JUuxpF4QL9mk2GhHw539bOTXdDbYO1NvtNvHsErme5BMN7T+2JpfxK6qGqi3DOIC9ZP8bgByr
+OiTn8LSHihNMjZc4//1iaw3MT01GlbZiy1TiRAFb6/LTYqypsi7ZhlokJuxpKLBBfNP78QzexDNP
+RM6HvlHQ5YHz5HncAPy3vD+qqwG/A3T2976yYELeKZuoeB46QdMMa5GE0Aj0ZzMWmIiKTdCD+/9p
+02SF4zkqKBNWoex8mD1u5LOPRXs3+eLJPGYiFWZo3LG9RZyTRzoCYdTSJowZCEjiYi3QdHeId051
+XRMpMGU2bLR+eWCWEBaIsLHgc1WG4aDy2x22jY3HVD5+qRjWH4gnEqlIT/FWKqki12qVe/W895HX
+ows26GNz8UQSX7898DeRcXrGkPIRmvCcI8cQ/sHAm1uJhsl9e4hUbpPthkM1sM/5DJ5ixn4O9HYm
+3TBrO8UIY0tnvMxJG5u1ShSglCRSGjIxjQDkHhFrl5C0h+RmoMBqOY10I7c1jp4XVx3Fvhba/sUq
+xGbf7FFoKEXnBqRf/BXsk8t+X0Ff7Y7ln+jskoEFCn71RBDKO/7l8ebInvvaTbttOcz2B/667BPx
+8GdjiBMulaoQjcWcS6Hr3YN5NT4lg7VNtnyg1/B7ht2NdgqGyyvFBru/KV1HuPv9Sf4SpS5b7ZEC
+4Jh5RJmCxuTrq4tOK7UWCHIUgSMQvFX7U4e0H15QJnVMNlJXWoZcJHNzSJDSK18qhkq0039So6Vr
++AS0tV1I+M1kk6R0M1L5rRR11h1Wp7VjyNoZg4R53VtYxOvI93oduBPJRZX3nraDWN5c5zKC8IwL
+lsONb/SyAasz7YkxUi8wdPVdpU0rSJ27+iuV60j5V4eDaBCAjNqVrM6J9XGwP0CmcrWH5by8FTW7
+Jp8Cjia4bP8rOV5oi9QptV2zr6TSXxfT+46ruZjWQDEIoA100Fdpq1EQxXKIzO+/Otuuk9DvDu6t
+MQGVwgEfFNjeuw++Tr4DYGtElVZ0FKUaoY6yvw+Fqvc+9Vz5rrcUl0Pk60pg8elI3OCoztxygrp2
+RFQN6dqPmbO3Z49GZvgmchw62tdnoFCTHLe0uOBer0OE5QzXmuZ/Hjdrx67cQwhiMiQkp8LF9/Oc
+f+n9kkYx43WJfoTNPWu5VswHyPF9ssp22QI6NJFxYu8FmRwpttT6FCV/onWADehMDAgLh9cXBlLo
+ZNWiyZny+0ZfPWGnZ1ifbXDG7GCS5xRSue2JAMQQjK8WWWP0nJZFMIdB3rZsh8iE58ar0NxT5KsL
+02gdJzStUlW+9vyuqbMXzb/SzHMEFalmLQIfXQPqjZ8drvt8EQmUTCj1t8CNJZhrreVTvAHClA2D
+y2PKTxsvsImaxsTCd5mmTfie3/Gby6/icwMzOJ6eO/yr4EciZG7uJoQ/Rud7gLjSVTutTrg0cLpA
+tqXeqSbcwQcZkscrOv8Z5Bsb49rGCFhjk/L8T28yeUS7uA02iNGZRzxCM6LX8Xbnt7ceE9MSWVxN
+bzRoyi/mA9Qh/mbErAurJDzNJFkZ2SmnAVKB0WNr/wlzg+a+IiV2VUK1EhPwlrNm+LBk364RG6yw
+sBR+1sLyk+MNq2CZvvLhNAGxtVsBd2cyJxVEyYS55VTIpOW7Es4efu14laxkuqEAl/gUdj/e3HWI
+9/sUZXMnguHK9so8/kLbONQV8dClGi1P9W5PmhjFFpMTW0+4fzIaL/xIYvH434r1OV0aUaxS9zy/
+PQXK/IWydYKjs1bw6uTYPfa9zLMD0j/Y5GAAEbKjrd2cWUHhOwEoAwNBLOfytavfEgMpxLlm1yf/
+n33au7dwSflmpBHkzVEr+Zlt189c1OdT+mvpO9pYwy51thz0aWVlybYU73gzeDclTUIhhelcMAWo
++sdLliELJNgEUUsSfOR8X+coAXrG0GsilawFbHp5oC7q9MaLTjsfkDQDn0KQgFFMNRkP+rqI7yeF
+8jCF0QOPzqBAuCVhAVkGpVlrXjyhvnHMC3bPXl+fVa1ZF0aEc7Y/pfPFUgrROsWTP/sF6QdqyQyf
+hYLLkk1/8jzoxZlxhcZ1IiAt0Vp0n24VCFNhdMcboQZV3RIHjfWsniBUcyr+oHDxz/C1Cr284po1
+zvP8OHY2BDyvMEMDHyfBMA0dz6L4QprjlfmKxwI+YGp6Jl6eRHZsnKKSY2wUTmb7K56sR9h964Vg
+12zM2XbkZ23Y5V0q9Yakju1mlmmLhJFyL/AQw3GrvS08fzz2TroePysj3kBYMA+f2u1v6IRypJVH
+nhKo5bKbGhqLEIM0Gp+KmhMyn/DN9TseN/laRdKS4G2ea/zuZO/dpEuW0xaNXEQPXPbhNijJf2J7
+CwvwCLBkhA5RqCivDDWGwFn9wzqQYTUovuaSOfJOEq192dNWWJSX7WJdMsuJ9vyqg+2xG9/lcD+v
+1LC0xiBoZ3lldJoB/A+IWI3vs8B+wZ3kpeZJyVzscS39/7sRsz2v2ZQxWWjnjATtB/UbsoDmS5uo
+BaoqiMakYhn+NKMoOH+ybbehB68dSOyxL6A1PrKR4Pn3RxzGXLGtByEIYOEEx0uvPo4fUdhsw1Wl
+Psss49YAMnZ/Gyhaa1Ol2103TZskl9P8luhiMH5JZQJrY1YebU5nsM9x9oh69NAHu7t2pVwAaT5z
+hWtsZD5EfH/5DiYM8n3jafA4DlaMa8Mm2ztKdhCPbvSszdmBLTMB73sgca/BpMKVrtHURXSe0Qyx
+jq86aMHwUbty3BJKPdmEyNdEVE+aBrfP2vtyHWC9BjWSqs1Hx41Ra7ZPnOi5OWyaNAYyp5X9ttXZ
+p8w8LPgRMsdwB31GdjC1BiLH42MlAPDNcshaxcrNDjZIUNZ/I8Ng4mwTFaRhQa9fwbfqVwTZdXxk
+SUa+WZi1G4b+iPDnjzzvDTET8zgX5bjNeLLy/zf5AN/IJlDUQqtzygP3Mn1kfzyeLFlwoorre7sa
+ckXhPVAyvtFnA4GBPnyIrAozyfpnSnhHVwPCQO+Cy5YkpclQf/kpdCaJRRGdKuSZG7BV4eK+YLNx
+SlF8hMD7Z2PaPLk8Tnq7RlUm9VR8Z9Q4nAuX7oQijpjD4uczTUhmSxUUvrHjUDzQ7yC0SIJ4U9zK
+eyIxibv1qmnxe4fTmxyBG7M4jFgyMQsjAyOtV78UTg9B8YoxN78rwu8g8m2qbbUdgWmw+cgdrmcF
+Kd21ne/IfclTU3qKChTDDt4VXBi/Xs8grMqLBoKr6cC+rr5y4Fy1Tzq4KetZhtmgWvM600McfbYU
+Kb1SLU8l9aVhl7ZucbSpAF3yw+vxTtupsTv8P1fAuliZ4n1Or894hGQGUnqCUkBCAyC7ItS5DSlN
+WLmXL6coA5fX+MvGJnK/Z0fXF7fqaQz4r/rKk6e5uYNlcu5TAzI6gOTdNeTnciGlT3FHbNrAoiYK
+WSgWk761dJG2CmpY1WqbYPk4wT+l5GhgWC78KbRIIGv0fnvDHwqZVPB7eEJdVQuCrXreJbTYW21A
+dMGnH8FLcV+bDy6IC5esjKdBciZLu4aS0y4ix/cpHYtVFxwICKpKZmiC98mkiFcjDNrr4FVFdV7d
+aVWtYlTikfRquosv7mnXJ4+69Xe9ZRspEstlHvleTtpY1Ov0zLbP/EDRS+NXmKlrHgPRFk0rA60y
+17V1iAVW3ZDjDuxE1iYxjh9AZp4lEbg3y18FLZXu+gcZYuQuZGj2lCCcEb7RAWhkRloapQ71TnQF
+zxcxyOkZcPpR6zD8dNUPeJJ3U/pmTOhGhYkMw/svm03O2sKU/CopPEylymUCsp6h0q2kkTNlDsIO
+1l8tPOoBbmnt0nYv73SL5eAvp9z5hVEpzB9z/nHEG+SUQVs1UclXoKPy8OrK+SmYCCOtIysWLGnz
+22eCfpBK0mq6qy4c89h+EKlevdvNsej1T6pIGwGVTvhyDOWYi3t33zUX1eZCEslng3fTLwc0SvnN
+2jJFUH7P8ONWYMMBBfD0jYURQGTWhdr3nViGNEfwtUTVdx1n2aBH3RmY02tcthl9Lg/FRzGYU3ea
+W61Zi7j549uwSEcQ9THLpE4cF7HxXZLYM9fynsbjLOrI1rUoIR2xOv2PwSemnocmZ3SpUAlYlOHb
+7NrQsdbPhtdRyEqS5fDYEI88EgcFzT9dVajeVjdBMEzKWa67ABRnlJnpy98A/e2Sr4oDeMiJr9Au
+O/hm4lk47X8zC7A+WmfXy9OieDjrC+JitSti+WMDNuEsIG8+w5zAojz7bEahaGBppN0c0wyYBB6S
+3eBaUleqUFoaTWOBtC2ICJdB4tyL5OAcWEhaExnP05z/Dmu0DLOoYzJ1Fo9ekiVFR/Wo2cUsKGAs
+RGeJ/Fo/OYYFH8mIqcadC1QalQx6YCDsFEMzmzW5o9azJkFY38sxXQ7Z/kd/JBudNBxKhsWETdHq
+WtwMNGmfX57KBrwoaQSLiZLT89mCO+1SmCrsBfykQpXiIO3yz3JhgcmY5LCLWd+yNABwC/fcSVkh
+712BkYCjYssktsj1AxobPyCdJ7iM7k5rCiIcv3p8jfY7Es4ZEVhH+9OcPNBuTG/zRU4bkBLWeo9F
+K34nyiWGO4AoCfbmsVRYi3UNY2v5BMTtAVXidfMgTxqTMHFnvFscLSP221EO5RVZ3AHyV8BYMM53
+7mX3OzhqE9qBnRF0S8XLJO0WA7W7ZFjFxVrDt4uzBrA62PNREmyCd4OqJOUz6btDYI+0KQ737+49
+uNqNjp0rUKKsaG5uOZCngdAIadG63MLK6JpnFI/MMyFsxl+jK0PR61cr1QR+sTAqOf1EHZkv1OYn
+adqgKyYG0z2ZlBNpdLEUw7XTthhPGqF9eettrWG4DLVVk/laLvUNI5a1ohhWJIfclgVXAV6fkrsX
+Au8iTk8P3Z4Rl3+YryZUhzveD1B+SZzD5kJ53uhoDJc3lK/HbMVyqOQxLDLTboxtShDxc7m4exNX
+oSDqMjpWIqiG4I1wT+iPCX1djxwxvQzEgit/EKyj0QBy6oMTat2WBe+7R4tLMC4aqgcD4BYCzm1x
+Qrs4gmI+P5ryPgtfMEaBb4I4azeHPJmKYnAGEblBNPBehfvuBPCm2YXyw6vtlqaLQsOznKlX9Mi8
+6KVELyng3TKi6S7+lU727np1i+j3RPcy2xlyp1zrFGu5zHaasBFQ2Yr4bmjRV5Few4kE4DWv7z6y
+22LfoEkLxGnvSyQfI6dSujRhv2BQG5R1DiWrQ4hvLPCpwpsV9iS5zpmRHeZ6NXYHG9m1wMr/eT28
+czjO3ZKGeShh6QQZ4+7cHgYMGmiU9NztfYCrilwVBh5L16Fq3yBeDuJixBCBQnFpOgkeYFUPRjUa
+FMTfb9DWqK76zElSK1+Y3aEqoJpo7ij6PhyrFfTlxJYIFustQppqvoxvlh9mS6tBP1OvkBje3TrW
+4fYB4/d5HAxN6ds+IJC116tIKrzs1PIHXNsYoxUkCF9ghwXn9AFJFxO8iXRmBjO6cc5MhA1bpUIi
+ccgmqyN0CZ87oSlQv9mXCwFpblC2P0HauSpJJtEvdGWJJRhAC3DETHwniXqKjnLO9mfxEOn+5Ox8
+NTclktiwzyy4Xou+nFZ66RqXuJsHQDYYK16D+wj/pdvfKKOJvEFcLGmHuaNQjip8q91Wq7NG6IVv
+vYIjot3PJCfWdI3lnb/uy//MxTpV2lon813/SDjO7sPZJOB3wt1YcWWl1J9jkTvWaZIOdDH6bWD+
+J/dgx/ZcUu6BtmbFUVlkrzv7cxiWCSMy+2X6/+pIOKPXKc4JXgpxxppFaLK0FulstZnu0MRMOElz
+88vwdCWj7idxwpU44/JrZ0ZkqBcRrKXHjnXldjKEoNSMIAy2INbVW4Xx6QZFJPKlDqlPi6GBAGAQ
+4Y+VoNORe5R9JrozSsIQqJvRPHi6lYauK7z8XjezvsKNiqY+/qwPTS8mGNW+/WuoMSzDXEPotAlw
+8BR/sKJdNnSXKzCM0ydjI+ZwFAbW/KPlXzknYcy7Z63VJD0rVPECCv+zz5QyIHWD+U9RT8kJjDR4
+au6AgWhiF7g63ByCUKTXy9AlTYLBlrhNuQgrDzIvvnFa7LmHA/eyov/Yoi03l+S1Tf6dZ6/e3OVY
+L6olekAztNbi8ibIG4J5+Dd3W1KGe5TRyWjQCfVjur+FaoZjqQmbfILexndrVUPlfcOsrQhzdI1Z
+AHnil/anQgBz40GFfPWvM1Oywh9NeCZoZU/naJz2B9B79UbI7Fsx9xTtRDh9UrGYwvqMSzrjLJFz
+byTjrq5xjoaMHTwAUnrTLLzQq286ci2wcYsVGwEEo5j+e0s7zterHQv7A1lA3LCWZl0f8DdeKjpM
+GpBK3Dha5ZlcTbIHgaTgnmoIP6nPX84Fwk97WUJ4VHHikKT0P453gudcbD/F3JosA0NSzL8BYIT5
+jqoDrlCNSnfvMHs69T6lmubr3KjwQs4VsVudPMmCEwJEdTbq144phl8qoGGAccj5RrpIXNsCuSrD
+h5ASK/7hCGt5a6xxxLhzArh4yZzR0d0DoZ+TvUApq2Le82ltAW88o+q90iHhor7CW9X+jmEUuzkq
+IAftYuptTFrlZEDt4qPaxJSj/bB4LTDdxl/oCTrBTXh63nz6kkk75dClgmBzAq4kYpULpVEWK0uY
+UXvBaEBelW1+bwI/4hvc+4djSZozLb4V132uPAGDjwfUFqc8R02xlLzlfU+nqu7zZ4Gvs6RQjmqH
+FQu0xobjN4k9NTIhrq9YJzDNT0P+Jolfb6rCElU7ObDbIi0u06z5aMrzEWItAkWVL9SoAQCmEjj6
+J1GHsSo4w8dLwxw/TZf7RYvFbMzJkwXXiCSQ5J4N/anoSvEhSMeBZxY+Qhshs53mCEKvg5Ahu2Yq
+0oVWx1+Ks+nUpbJ1/q9y3H0mssVjNhgmkjqoP0Y3+7aIt+pc5yGjBRx99PA3Nxox95ZbUlKIDjyI
+FRAkUcwXudw+LFYQTUFmUh6qGChHzr5Xt5e3H4RTUnjMBNp0k4wXpgK3yXJbyU5qwOMxyeJ0WggC
+r9/P6jCeief4y5sr6Kwy4wEVrXpyh6TTSvwQbR5pBz3/f0roJqHYwUv4+kLxUzVL1DU1ZY+pz92y
+wGnmDn/RUg4K6O9uMiOXzl01dlYuHmLUweJesqJBrwarM4aYpT4DsVaFMkZFbbTnCeLijTHZiPVH
+jpArBRTfBpXf5KUBBroZgS4UgVFZ9dz0GPBucDAj6z7RBnRQX3HGrwM9uS7xAvDsBv029MM/A/Ri
+/3p5FknGwhJIvJgz4GXWYljaIHvA4vneKY0tski7/ADzYfvSLK/ZRCi8QIbYYXpapJ+KpHX+L+/I
+MZRfmUrxJmdJDDpyEqW8Rwl8sJLuubbqla6Pl4cjYM6Rza21EH7/qlzQAZaF1I/cYPZyjoj1CKLA
+ETP/vxqGP7663oXDyapQvErHiuuqh41mcl7r008M955Nu7o8iRAkfmHh+YGMlqjkQcUiakRkD6HZ
+1QA9620mhZ/lpPBDfxzqHktGjKRDjJ3w4ZhAbftrM8drJk6jHL3e26DZFyRcq4FIpxljLF7tbdy8
+ij55zc+Fie6PV1FRrGCmlMgNnEM2Fc9ByOBXKUCHDx8xltbkKs0NUf6CJuNTh8dmj9n9PG4S1W9M
+WUz+m577xz5NBZzoPcuYiZGTA2DLBzzzbLjurlUONAWSLlgJTeN/G/usw0iLKpNwNhmmS/0zkEYC
+1A9Eoc4SduSZ+qfkTqGcl1Ko30sJfpBcYw1u0JvN5EeYtwX7ig35aC/sFhfY1RGHlHszAxfM7Q+y
+VAmOLhPkwCqhkjyyZ5E1LLuEqyqLPGWtNK/CftQikIn1qhc7tS4Th5xk16kXcWbJ2yTJ+b6piwwp
+UdmHCBIrtKHq2/8rOp90M0wbLZS4192nWzKCuCmeLsrXVVkCB8ipX/hXc6mPV/3vl3zeY5S8TDdt
+xLcaFYDYTCe0l3zVLyXRoTcaP3TbA9gtFwsh/qrvE9RjVA5TvxiC6kEJrdWJxTPUWWC+axC6zJCr
+y36jSvnsz1zLnzn5yzqRLBb2AtkncuuyK9xvx1uHav2tdUV/4/GejMtnwjCHQYk5e8D4FCJRRxNV
+9NqmeHu2rbUviC9QbRL5Iil455T71/9drTSg1Mh9VzjBjO8NaLv447j/24Xl3CQFI89cAutxb0nm
+3p5Om/Xb6gaBwkH7FGkitQ8axJxkqkjHF5IcYbrDHBmOgBnRxZHHRWOh37EgAkd1AtUlCXH88qHw
+uSFWUncZ4KrTCY9rouOzxaDbzftwYAD1aTl8tGiwMvx7DTX8OPHdyK+XNieclwmkJiBPiwL6UcU7
+k3QVpDy7sviGl9n25T74qplZPqwcnazPC7iGJslg3wvyxlf4QYQcqhQSMoLttdG+T3bnx7AFwJHK
+4M4EhZANiBmG7HJYM7qfly7lzwMCo1gyfmnWnuGiJyW2VkoYiumwUK5urL0igk94CemVgvdkX7q6
+lmTiii4GPAF9XX1BhOfaAZF5fUIN+aFt/sSn5Wtu6Haf/k0cRLkvUq58ePqfmL7jisLcUGugpG1E
+sBvk70gvyOmyD1oME4J8MH1dLaQAiyU3Zrs8/CIhCv8cDzrvPjCPnQ6YzcDV6k2+FDY6f/W909f7
+hhodpVFTPwQNHgmHeppnb8QV7SBhgfcoXG632ysBSiEL/UhD32o55xTqyw7D5renHWM8P6kYXMkC
+zZCJO/2oRE4Nc3p91D1zLD3yL1MH8CHq52Tp1hJuEfduSRkgXlconSAGmFIM8luBXkznwh5Nu6cw
+XI9zTlcTDxdkdcozWvXHvt7mxQlp94DzRZpdpdTzEtsw38/BytZEuY22lnl/geqtd1q2RnDMwEbz
+9FTtQ+b2aXa8e51AkMA+LVFTCwsDIKj/ebmpssQQEB7bxkiv4owhZEaFECINWFI8NOjja6yPHONv
+UaIOU/ltni8BuDQLAKfF0Fgd7nxocP7BfCHSaJCbhM+ITXzY6TkNzpXM6lyJGbyQatXjey8Y6P4c
+zdSSWJU0BEjUF7bAk7VeORu760si4bYJnrgYBWUeEt2oc9q97HCogDVuXwxtAEwSKGXreOq0kbLW
+BM3hXPRbBYStFe1MMjxU+6vtwQ0ZlQWICLfOGZBQZjIP7W8pjI+A0bRHT9di+t/wZNugum2+x8rI
+hLVYlbLhmVhJG1EpmAj2L/JsYDOGiOK/ETasi4H+4clXHYwJ6TT++Li+JkFh/7pOuBslOZdv5J/N
+N/1frPuMERCcxGetABwbejr8W4hqHL9XTtzTxlPglkMa71glgEsvjh5DzNT6tah02MiYvhBBAPtg
+BEjo+ENoH7625EmVDzdENeokn9UxRC7bUtBteZZFWvslxVdhfEJj8QRAZYKVwu+3tTSQEL4TlcAL
+2M0mNekWOHpeijLezfoX/wVqV7Qpn6W+PvHIWgaEYE5rC14Tme0qEai7pKruLy1lr//be5EyZpK3
+HzqZB7n4UX6YHqqq5Ohne4r672RYNjuzb/2zeXNnMSfEaWjyM0fn60ogG+Fh11WdSnhmo1wdZQHz
+OeqLa07Jc7UEzirMuDPjRqGN95+TQ8ppqMpGdvAYmT/RjxQAVXQIj+6znKc0U7Q2BLpiWJLbcQ95
+23DLwUwK/W93Pmq8x46qhwLNW+b5amySGN4L8Mq/zPx1ArjTrcpvoZIB3lBxoN0HmZzqKOgAsoVk
+kLdroE9bM9xdoCizABQcpWmwtA1hJIdLEgyWbL6EqSBt8lu4sCWTU3n1FLXKl1xGK7TDOgwJ2Y/b
+QmLuKKEshDtAaO9KIJAuASpvnRh9T6PZYpEWxKxAGBB+7UAf4Kj6QpGwUaHAidlN1PQOiwambPgT
+d5gpilzjlgnQCFV859IzuUSYSs8Rwg4kkRkx8RorFUYnmz8IacuuA25RpunB/+ufK24o+x4rX54e
+rNYbdQfvBgBSdfnQOdkSSpuIEm+wegWLlxclJFZGju+klTpJwr0Wvg3VUDSdsr9dcE9xkrFNbaJf
+KwYJmGfzB39J5hFFe3b4iNIMOvAhpZHCeSqvkFLhX4uskOY0d7AaRO3Xe26OA+eujELHXW69w+Kq
+qE0WhRGslCh1KB00wri0oDFo1zzoxpXLyEGin2UIGe6oH4Q8LsuH+gmM6FKXnrartsI10sETP6+V
+q2FfkyQwGOKO90EEWhSlOTJ3B0CoSoXrbhGxNzJ8h/+dl1+JZFo6Nyoaesuz7q4G51tcFlFtX0VU
+pi41dsi4Q+2pRedKtyo5/Ax75TkZru6pyC4vcUBQ782UU4Hw8nawXHorwQLyUlgun3N88Aa2UhYG
+UL4960Es1qUeiVuc88CXnMqV7GPSVcZefnSiv2jAd4hOiNCxcGqdNYAfJHKvioXqbRbOMKYsDZYd
+2wtzrnkzjAyTs5/liQkJqGi4z3+Grm0Z0cGtmWo65LYSIAfEdWBK0bOgQEKt5H3QOO062ih2SDWc
++FXLAjYe45N/PC0dqI0OyVGqeCZUn9/DK9494w/+8UeQXK6ZUZ7ZBCdUymFsJYtK1qaf5CTJM5Oc
+oKyf/C+nD162mjcXVjFnA+hnZMfGCuQNooXMOxYmAfk/it2Zvjl6cbGijfyn6EEB+vkSaP0F/XTY
+0PlQFlMjRbNLDFStrNVxIhL88gKztbPJ0cECQZneAHxvGtOvxOtjaxErRwmkbXXRPWOoxWWMx1TX
+3Fuxumt7BXoEkpSjyQmep/jQW4d74tUTAAgV/nhJcs+6XVwREaC57njr+dVP+mCamKDMu1M1pQTL
+SSsZqvXHNOiESIKRTdLUMuLYGtknJ+DZOqaP0mxN1xFwFmOYkoyEkC0x6BhQKkcsA6tk47+XYJvL
+sJW3WRQiC5CWorCW3pSAjGV/wG6gu17jqu1bSn0vBMqgJXOKsBmGKuFOIfsjsQO+YgA0ZZup42Jv
+DSIlWofFeliMHLaPYFkIYZgOw/ZnJGIml/JcqqwKfdbKWv1/gD+04YVv4ipcsdKYRSx7KTuXeHnY
+ubN+7sa18ScAynArkfUKA8yth9n0iIPXLwLv2+PcToL9y2QOPoXBi0EhsH4LUwJALp51cFupvECS
+j5033c+sX7a7mPMcyfZV1jrZ2+OdYqNTU4HnPgp2SGf4BaR90eZ3rE/SLt72uCfW6/fm/7uHuRSm
+xLZhFj9cb3TsER7vJXeiYfcjM7NhWXItL/sDI2H8IbvzJ5x8H7oWiA4YaIIPrSEHEQ91BpU2uAzz
+tBGLZpyTyfhlF1JHbyhZWQK2jDcEu20nAC/WAjlkTyWJFuCr56e1sxjufuDO9jZPImjFffISNSxG
+9Y3QGjRGnoLzQKVVFYS/G93lWzz2iCO2Qzr58H7g9m7tc/9/fjRknQhL+Jl/fIzwvtBQbyMoN9Wi
+ktgQgj44WvwEz8vxI8bfXDE6NbHsN9+JjNqw6/oQ3r7vh5pzeuY5WI5/LYI30/b9b77S33zv12Gi
+j3qtM8rlbLRbheASC26wTWj442+CqGjTC+FsvbcsPUXg0kN528uM/Vd9CqqV433XG+g678tacJQp
+YxjpfJuiqHWNo5W6KVNVPwr14Vri6ZypyHug77Xrpq4SMuB+xn7dIG2BcKun2BRf+8WhCIJF9dzQ
+4e5wK8ki94SdzICw0QGVtIayoyHqRWA5XIf3KyKk1w2503NSfwN4GQwmKkc3JAKky9I+HFFPO6cC
+5UkdkHot574QED4D3alyw1Ss7D3/gjKaveZfcF8EipX3hoGQTA3ILeytktiVaoFhsu2vn4qVskJ2
+7/odZNm4faXhJ3++R91JlJeCaHZIsiyjih9p0c3vyWBJ2WPHWSJp1MPsuEWm98ZbsCPK6g4bJXk9
+669o2Nj0HSsRn3MTBS13F1kZTEM4yydBsZiFkH05UPVQam0/RwGVnGtMlMLp8aL+ynzBCwGerplO
+Qrj9uPq6L7zR93Vo05NuNEcYJDPLGyUs5wvNgyKLwJkRWmZJmXFTcgOvBV8SZ4jDrzqhd7JYSEh+
+JDXu+HpWUis24lqq2hf2wa7Gv4VOVCtgwGLOEW3DBsCNxdY9gTeG3aBr0K7+CGYdbNIej0ueEkPq
+RJeDhyRFHDPSlPDwLQ809XhQMooyVIsL2QKzmIS1WwvfZFNSvGzfLBXpeX5rbQS9fP3fH0N1nRb3
+OWLMg/WTPXLRrnc4Y1Fd7aZtPHnzeiBaus5BHhE8n781ViumpUJvZvOLOXkJ3U5uCZ2u6hYB2+JD
+rWeQWw5+9Mkq1GnKEJFzbtIB5N2L8WYFh2c3TLtRrQwhPdPtt6eQumXJ8ZkSHwRKrXyPZlL8+kQG
+EtMzRAJdd/u6ioKMV/7faxiXwHlbrRCdHBbpU8ablB/rndMCxSpglKauDb0/9X8motQhTaFC3nc7
+KlMtgYTFQ88AznJhCrV8e8TISsDe9kVt344+Q6nmQ7fLq/4HhofAIPQwdAqJMhvpkt0PUvPfLok5
+CuzH3aisON2DvW3nK4nw+w7nx4gSohIR+Em9E7eKiCWFcf+LyyP1poRO4AQcw46mIiYZURLq7Ucu
+Ihgjxl/AqRlQeEC1pAQv3sFZ5R+GwGetgclyzAItVWNR/M3uekgp7TFnJmu+XO1LI2azhlc/uoFy
+n2sQnmwuLH/+4fM7CwKbpIBx5L7x6HHRZJxbtDZrw65cit4RIC6+UbEciXPcxzd6KMiEcw+AJmzM
+NHSy0t8kcyjAlyJQ46mBclBnOsgIXDlu/rKRJ3Rqle7yR677/yj6LMp0vvs0eR4tBsKEMQaZeEuw
+Y/fQtqyhz3aTvzZHLGUH3t4fhMPnmurwmXsVojdOzAGPSTxLInsIUWFNF9Vs6mTsz2SULPUUKPzK
+xmR62WWbGGR9XZlGNMqz83YzIM4s3ASDMID7t58Kp3aPHaUi5qdA2clq8IobD3aHkkTEm3blE3+1
+Xz24cpk/xFHTPf9dxpe/PS5k3ijXLZ1dExHPQXAR9gxhPN8tO/88FujimV/4lWaeENp6kyjRkPQn
+ZBMYrLDUQ4qAHukdjBqPqWhODCuyW0chgJ40Kjkd56CpjqBX7Dxk88VXfOBTDZEYW88a0jIP8ltz
+lgok+P0Opl1RirOsQIPn/0JaNc29FjfCuLysLVGk3BYc7xPBq3eRTk/oTsRwBBGb7pM8KwZ1NTY+
+xjv0JrKIroRkEzJ3XkiI0XgY0m7C3sloFo+DGYj0DS9/25GTmeUOoN7tZMD+8nIKtvusaE6JlzpI
+A8MHieQg4TTq70BUyp0yWNIljpzEgyDYnH/uHYbDNTs+yoTOcj9bY1gt+XwWc0wSFsB5SFYO5LNt
+mXJzKmSDL5uCgvC9juDpjg/9sTisWywPwaE8X/DSHAvmu8ALUYnnqZoPljsBSY0cErTcDTr7XpcH
+qHa+ywoaiW2IDZpl8wGEy4uHqzKvZoMwCRKPgzFGaZSb6675AlmesCL1wa34FpCAP1fMFzQGp9zO
+MVx5CJolVQHNEWIh6Cco5Y8pNrpm42qbOvPbqb322ZBq5QkLXgyuIWrJ+1K5nxVRse3YSyQMHkO9
+sFwwyT7hi7IgMePZBDWH+zm9ZiWym+GfjnQ/Ospk89dvTyxBVes4uMUGKKStKHYW8/68mhFQJIXY
+5It7TQJV277WU4OlWvQyA3MZxLJUwqia3fAR+Bjb9sU/q315pAQru1D5r7he8xG8i6V58klzqDcW
+bm0fUN5KdKjeSHReUTs/yu7DF74yj+CS2cOdF7zI2tTPBirgFjMlzZUBz5l0L8G74CAKP3Soc/Hb
+Cv59eB+2kxtEmtmNrenqe7j5hIOuM6AuZTnI5mf4Dqhko8+y68sbW5W85vmMLfngttmClx+cuOo5
+DLdUOTpQ46juAwxDRgYlly1d5RxkodAsHci3X1HFvpC66pAdumbhrnUsoMtbwogRcoqXGVvWYoBw
+Y8mp4hN2LMRDG/0ae555vKlnDGzt4twCTlIHU6sZUPE7Z5WNgf50BhnCJDaKVtYEvQAvB1hUEsah
+jXJxwolvKEPH5XUej3oSn/FAqq0Y526CK9ZTxZJQDZvO69epm8CeSOma7LuYJpZSe6ITQb6SY1Nc
+wdl18s10RpHVLK0DNIzoNqI1WXp7SJuCKHjr9qa9JrdGu4QJCceuswT2ixgiUp8MHhXVvUCVo+MU
+Ym/O4XwtHns5W4fGpfqz/6WklSBb0/Jkyx1AaqK1ERPRmqFx5+R6RXRwVijcKVYbPSmm05ASYVN3
+WNXETSW19F6r7Rt+CADjriNqAJxY6f1MTYEvH6lMh8a3RwnvbLjr8/N4egf3G6u1RR7YcgEzMBq3
+BeHeDjzTIHFIMwnXorcyPLyS6UyMMvrFH/pfdTFhsBVY4KSaMFzbBof6C04CSJpsEY2xdXCdpGZf
+iGc3c159DNnL5ULJF4ErZtDnTbPoWU9gBUsM8XPG6RBa8a8lvpSbES81graeinzR0fEvmlVswwpq
+u6YeyG0k4nX0byeSVfD4pQbcFkLi7XV3K7d17amVG1QpZJHSPQLyHnVA2sAmrnniX7l4uj0yqfau
+xZF+Ro4bLZSCV+ljyRbOz2cetipRwZdt3csTyjWkgRgStT9KggBwb/IEEEvoJrUHNVoxGMQj91+E
+/VCWGnijgSzh8XiEAJ3HQGvRll2yv5bV4HUwhwXPf1em9otP8VK0uogpF1H+GxqkmSQzwg2mEUwM
+Hupl+sipRzxL1gvpTS6d4hEMYKrmKyrRV15eAgvoRlMuK8J8q26ulFVfmEAuO3bnmar8MSPHVLnx
+3H+swD72xGhd1emIitbSawJSpf4d14uZKaKyEIoX4B8iz/uKKnZQCqGGrngDMEzpH4a+3/NtpyI/
+5JeS+lEDYDOLfYgfSjci+I4BEiDqn8iaRKxRJpBndbCzHa7Uf585DTrrjLRgGAflBhRpGY38xJhv
+xyDvRcmuanHfvOLdQKOpMPH/Yw1KSimA6V/tHLrqbnKemkzIOG7dV8yqMJMMRvX5JbEhrnhpd+x8
+gzVPRVlvEQn5pHQ0pnFLjr306cdFj0sh6q1iYOXtFVNFFOePihXtcHJ7irdF4EDDZfNO2hYLfPOC
+woZ4dIvlh4pUHTqJwnQ8YfNLYqysJ177C7uF/+I87vXBJxL/b4XQLsvH9sZkG1mY8wqciGM2oSFh
+YGhE4xJ6iFQGFhEO9ezjaIiNu5d72bmJh7mVesZ4j1FzEw3ALWt+hqGJCwJvkikkdatOIEunINy/
+g4sB61iLlqzA3srv+nMTutSPwrB+Zuxw9/5+RE9KMU8Zy0ARieBN96hTh2ZUJpYcR5FKqwWSoYnZ
+5aTt29+tActyT80OQczyLAcu60eL19y/ihsA/JZY8UpqRnl6R3XbcztfrqhEIGhGecjJ0V/JZ4kV
+uFESO8juPCQ7dB5XCz8Ld2BUgdoxoKtr2mHYeV3ODJXR7IweNeeRUCAWrYwz8ER5YUQ2HmqfyuvK
+lYVndfqff6RqiVqvP1MtP+QKWeH45acDfdyJXjAFRM92ZcfF2WOXfeXnx4KcG86s7u51Scx4dm+h
+argQoLAtBM/tCTvimRsOkMQ+Wy880t63T5oBJrsLhouwtvNpBlfOvqjpMkeX7uO2RBso/oH1CJzb
+kztqnNJ3fEblBgRBLBfC8bJ6cVr3SwZZxEIY7DIxuse2CDvi8qRAHOu6RrrurrUfp4toCa5r7CcV
+zt++o0eeh84EZ+jzkm5NULmKhdQvm8+/DdBKjdZgdnQcDhb7DG0XfMIpVtO/1ajMruxHOImItSuQ
+KHzmTWBRGV6UdY9q/yhp+sW1afwaFzSqWr+OGkkDAp9QZc5SSQr7aW6PE/S38p7kPvArKQ6hh5p5
+qZk7VEKoBgBseopR7d1VRuYv1fvjct8VpoQbdkKHXM1eDCKCDKzDxFGtFvKoDReFzXBd54fRwWTs
+wy5d1BRVn2aSezUBnfyRwOsJQY/uL0fGCQLOQoifMyNXVXuyDvwhHPQI9RKSZmCJauFuT1I8SW9C
+Ysp9Ws8BX6xiqzmZghsUz8d0dZueOx851Mtjyse5v7o9jAhe+qut2u2EuntiFThkJa/R1NR/LNLT
+pP1kzxLRKAFhJVQqJXVTdAiFMUjBA4L0CI2peaAUN3M93y4djOn/3/06ytgzKYvUYfmVXxS/17E0
+BbLgyHbWgtK5OX2aTC2idVDmM2F+KuDY898E1bhw+Nm25JWQ/hRoIMpeejFU7Zvy9WrexGgiAWwY
+LfXqiJ+l9dCkuZOHQS7ZJ/M/FrI7f2IX1dNlHyvlqljuws2i5+oprUwhAbFnkX9g1zfi/imeh1+k
+v4hzgUwnQPTEnJSmzhQeccmh7avsg737NFL/42bpEZeP99wWhu58SV6CSyxUe00Knz0zxJnT82Me
+B4gi/Ut4cgnx48roUqPmZosuV/MhfAmp54yFgXPKrDrML2lCqdkZZFNbSBd/wlnmd8kRh0b0SndU
+X2ystQ34ENOppC8GTka3sZ+n9h7HQ/iMSyEt6B0ZCgofnf6aIACJuhisV5U7OJihnjOAR7vlZAeF
+BVPyQfa99Ye8eXfKS8bEiUEweL8NeIDEY0Ev1t6RZY5eooNHb8HRQ/ZSAOXO2pbDVM4UxYzoY7Dr
+k1WyUQrdOHs1x1kqNBocvB6RfgwUSeWpHZGMMXl8yDoiQ6dHlUrDmBanLnQvqWDzI3QSkcacSG+I
+SbDk5pMnJTdmmpYIzBmd7IX473ZKQ1wmea8jS8yMnn2Rd0NTHO9EEFiMhlolWTZevibCAKDkiHoo
+btFIOoeOXFQrN4y0Tp7Wmno524zHCz57QtMn8t4RQpAbyfYmKJftNlGa+h9Oi1TF4Ei9ZUv+0I3W
+AixBgdOE7ZVw0qqt/EC7YAx+qOQeNs7Ad58RcbNC0WhVqsB2lsKYCy+UUssCDqIlvcOnn83Iw4K3
+aytmcV5UY1HB0M4udIPyr/Y3MLpRc2peP7eP74FN591RRsEkBb+Q4Ps1BWGIZbuK+/v9/LaKrKDG
+UVgd2aiYFba2Bjhi5l/3JX3G1N+tfG7Qskw57oEm1v4BoyMEb9VWA+Cfkt5VVy+R7IcKPCHwKd2z
+fOf9DwNeeMjDK6ProDoQfkDdYYOxoqWUcrqHrxZBXFSXX32iXLmoO3ND4zRgR7kBuuR1ewSAqAfF
+EMT4jKey8uM7r5jbWD0/E3y/ZB5vKE3hKwVc4dI3I7Ce1Qe1PE3J/8tNadztt265aIxTS8OMOG/8
+TFbtZjXVuhADEf6DGevt5TGwC4u18enEEdHbp6RTxbtnkJDq+RBnh8LPPtl6ACZ04b6kW6J9Qz/Y
+Ah/wGttOY6WaE5k5aSRznQlvBlfyyIgSooLUUncwvqXUmTn59zDlP0JeGw70psG2mPRYL75/g3Ud
+zTIGG9Yph1psZTJzrGCJFimpSod4kmytKTXothLggf1Ec5SyiUOts8lz59dmxOnqNLiR68YNernK
+2UUmns/1jcM/zqXdxqHHFya1dsjW+x3NpUXG4PoU/92opLwn2UEsqp3AZRGD/Ll8bcYk5J7sQQxS
+JGyM3pMLyhOHw0Frvpqwn4DomfXjXNHvqyaI4ipKbW5g3BIfI7skvHG9hFplKfoVZNTCj4dAJAby
+itXePH2uzQVMN1fAOQsa4OTU/RY/xxpgna961SnKvQwUNFEMCEVTEM8E7GVqMB2VJzZf+1RgnKWx
+GSkokDaxckL2ktYSd+t4i0faKvzgLIlxWnvE8Gn3iQDmVaCz674ZaDpmHQjZlc2HIReH3GGWFuwd
+U6XuaaxQXNmcMS1sUEpHDt14Zn+KhQUQlE8Ael08e916g2cK6a/LFHy9R5qYmKi/MU1aULG/plz0
+ZG5dgrvh78T8I+U8U4X5yGDwgcGpwP4pu4UT9+YX9KCxTCSILD/FppWa7ZCmuplF+3PXtmS8uDU6
+F6c4yeu7ygIF86DdsM0y9sl/2iuRfV7pelHCswQuQnYpgzDL7H13BjiOB7x0MumYfLohYrGrjNPI
+OmdHr3P6QYaT263k3wGoHzRBC/emb0g1ISaY4hCzKCVq0zPDniI99DyDdiciL6h1Hzp6e4D0LISG
+S8VoW0dVGxEdtatsutCo+UATzmwWHI6Zm1cnRd/BueaXzwPfvmmx3YtJQDpeStki+5B2V1h5KdM6
+5nr0CRMSFvDZam2YOmkG3mJ2dvMFgEGYR67s30YvNvXfJi8054NE+9fZCoNCnTmDJDDfGfm0U024
+FQC4P/apvIve6T0SugSqOqrOybo3cA2T6g/tNqcG237PEcBGuPMD+FSzS9xBsNyCSKSa4mxstF9p
+y2rbLOZG5aUmTtNOH7ymCbLijNP0krPlz7hZ/jzetlxUetptDVPoRXWIPQVxuIAi3xE2FiK+Rk2Z
+Kkwa8rbiLJSUp7DQaXcE3Ii78tOE2AIFw+JbpJCxLzHkRajf3Z/y4HkggylJ/V/Bn5CWTQFdbFy4
+J3/S3M2/kiaJyRbd84bNndYYulQtBhzjSUxvupQ89lj0Di9Vj9y6EBcC9EfQ/sfqhkFJuUYJWudS
+sauRtoQOzTGQ8nhSII4UWCKcJhzZidAuyo62VZ/myfkXKFBRCe7B4ksRxFG/JQoWu1wW1eOZlS71
+nAHg8FK36MVjWCLMeP2TGI4ieFP1P9tpJe4rXfI+xN3ZGL9Vc5DDdgqWexQeVEFhJs5WXuvTpdIr
+IE4ZNg6zPnPK3YIzGetblzw4iKGPTZ89jcG7d1DwPdSyR53mWUhq8xAuu4gtPHx3Ce8IKlgf4pV0
+Ufscz9sTD+J95ShP41KGIp8U1AvPJj162dmRPTPQpkzQkBjSoxgqLobFWt2PmG+oAQpwONwCmZP+
+h2Wn9KScb5igkralwKsnIZkat2DQXZ7msVpfdNuKk93Hz89TRzc9HxBiv8YgJuWb7QcoD5dOvoPr
+cr7S8NlSlUd+VxolrEJs2tcfzSlC1NgnOnsouZjZ9bdTAHt8IUWOCQIjG3jQBEsXl+siDxa55DgF
+leZ4BKtjJpwZHt1Qo0z2NHxicg4RAdQuxP/9rb5t+DlYvUX6/A4SgRRAg/6y+L2iAinL68f5R9sC
+P8TRQKrqTS5yYI2dZ4LS/iVHFQ3Q82UG7U6Bg5gNLQnda0D1r6WqQcgJ6nDatmbL1ceP82yFqSnn
+dKp9jMSOB/09WXARyFxYMF5cVWfIGuLXDR+mJ8QhVJ8QwWa4HwiFBCHXRP+77/wP6LwBivoAQlbG
+Qjvv7E5EecexNTQYkpCwt+P8zmGdHWjOEIqXn+YtCC6/2GOG8vQUQioLd5Am9QDyZrgJhmI7PvPO
+Nrzf1bp20Z5kyGgG+w3magJSxUlo0y+NS5uYthfk/hXvb9Skea1hLhTjfIiql1TZvGCo7crEZuTO
+H6v6kqqqP2kPGI5qGT27Qeau3mHDUoBm9I0VopmcC56JRvpTJPaXTQn552obEpaxbWy4dZLAMDjV
+ZCAx2SyFMe7n2UhvntmWFICkSI9qgtnC19pQsU517/4dG6Hpe2om/XQvk/4NtzKlBtps1uxUG7F2
+n11fEK2QFIpCj/kk8nW/M4d2qWPQntmvo/3VmyxqqD5W8ExoGzTSROz8LGRiJkBBeKmgsStKrECI
+3wpkJOVLCtwhAwTXk32XZqgat9Vcm26dGivfePjm+hQ5BtyLCGwcg15zni0LH1X518dI7uiNnNaB
+VFVFLRWNd5nL+EenZibzWlKsFqSdVLsUgeJlhQH26PYg+s+KOy/5bmYqWQOmtSkam56oMeH+sw5Y
+FqZekfdxDfqygfnOMuVU2uq2STlvcECTNxdI5dym8qUowYPfLJfWUh562WYHLnwBn3BH/CinbupA
+N5MzVlawP5u3nppX1A5c046ZgHnIGi67DkIvbZf2snE2CTbw/zvB/VMBsOQluv0SCxamynN2uRpM
+95mXp0zcsQqyG5aN4VNtmXmha7TQ4Sb1H6evnyBFAJbt3I6lvKJt1QdZeFFuGVH2061VtXrFK5TP
+foVryML2yKE2w4TIFMM+PGge69js4GGjP8Kn+DNzRBP+TGH4i5k5RA3LcKupwUGYcLOURYM8A+zR
+tGqjACIaGGhXcYxLGd1mkdKuIO+VmPCK+9YVmZFoQRO1R/goo6u6FIPQWq3S/TzV+orP27SCa0fs
+dnQbjuA7Bq1MuDjjqYa0b4FaGwTN9iTzaO6sFfpQDgUpEjM4lEw8aMpPAYx9PQcMJ7np6jKf7uE+
+W14NwOv71b/WmN/mv8F9ghZqMl/PvKJ+g3hTGuaOzbWS64vjerqFudfJ9IoutxGN1bboTmm8IiAK
+Ts0CpNn0CyzauCSp7Kyn3uDxycakT277FnxSSYBkkBiIQfosaHY4ixRGhQMlVtFfkwxG+W2/hMKJ
+utLSXL3aArQVKNPEy3ZGCd0vzUHjMqKWgtyPVGmRm5SLog+gfPN7I55gZqr0VssWvU/vIIVspQ2z
+IeuGUJyLrLp3manKtTvXfPHasxg/H+ajoPIzGGOKPAZyl7yaisJFuFRlTX9G4vW9VeQ9o250rmYo
+HxBvssCcD2nz+cISCumNJspxfbFx7uWPoHe02kmMW9wvdrB/ArNC1Qlurl648gP+AqmV2sqjWhsb
+QOxg9VBiivz38mZ1E1StdJxMNHJyxW40WlEjnBHiIMQkdGsAkFmjz1I7rVTvOAGD+SM6Ouv4tOEm
+ytbGEnD0OnfT11f2Qhgebvn0yzTezpcoaXPXDV/LOso7l1KMeo4Q5yIMMU5gLVogA6aQk4s6kStF
+ei99TBT6FGuESl6frvRFkBjsb4N/cuRZKXal6q7EZeiFvf+bjV6h/C7Hc9Hsr58U0NLBLPjDnfc/
+EVWDGhTjH3lUKzRAgmPtI/7lqg3ziZN3OsCIiFyI38ANR1GpG5UwLwdTC912VU1LLgxQyFuwKi9P
+osYo3xu/Eua5+8qmgZojZ44aP4G9BqU0hueQkfwNY1HfKDpue4UVnbItN0ytd3yGFld/aQizdE6N
+i0KPg1o+MiaoOkSr5r9GVV+5cfGMLkoecZWKKFpHPvr3S/lu0W435ZOeusfpaeI3e7IurXuMBWio
+IlZxWr0JAbzVJ/+3GlcH0btVwD10uNF5ixmQVkEtvAtX1F146gM7OxbCGIm0xRldgC4sE3dZOGQ9
+0FOxQAg9D+WbsegF+VdkiNZpP5Mvx+7JxR+Oq8B/taIyN391oFUHMJVZFXXWcpLugM+yBrqAMwgu
+h1RwG0dPzpkwoVmiVaJGaK9TZA4Bi2TaWzdI8zS7R9ASlRJvRhoLubwTlDdGyn9Yh0Bo/Wn5Q6S6
+rFCzl8YuJyWowNIi3YSkp4aXawvqU1FttaNMR5/Q0Jl8A81kMJJ0QdUcLw6/JAmAYnLuCsN1nFXr
+OgPFNLjMR4gvtcwsg/i2VCkqWbovMJZPkg1O+kap0y76DBZLm6mlvaz7jAuQFkX98cbPrdJBp4f1
+0zmM1rlAaK37fZvvjbaFJ3mhdx4LWE7bv9LJCXD3wZfeWOLuubq4ggN6cjY0xlzXiYUXOyg+ViPq
+a8c1F9IFF3H3jgCbppLn6+vizfGD4ADk7Zi18UukIQoMWwD0CVT+nAS14vjwkLRU0q5RwTMkyVOG
+Fyoda1Nv8ChSuKjR44z7PFhIhl08Jbo7VPtMnxLfPb4URbRGHtesqq5X54SUGL9msAaIO6uGlYwl
+AXiyt3xz1h2XurppGQr8jpvRWdH798uMM1QH2RbGJ/b7TAi+0QsHIXzv0wTVHcpJM7btO+GC2i2D
+4e2au4rWhhkzrwQmzDfAQceuotN8k5DxC92zZ7D0j7iFZoNSRKwuPGzSLjm8KgAGAyzCccJuYcRR
+sihgFhcjMqeF/RneMkPh4xOAyPvZvqieID5moBzb/lYnmHv0WufSg+7KhrexXzgSYdaaFA1CjLAT
+odhzRZdSna2nC8gtih2zVVnxHfKra2XDCMx+h0nly2whXJpqR5fuRSojI88y+zFPOupr7IETF10s
+8NAxewbuBsZBCj1oDJZlLaLoZ+KIL+U/pU98j1xT6QBrBbvidYkat3KMCqoA/ga8fgI0exJAawhG
+/cHgcMehzfnUC1gKAKGTly+XWoknC1jGkF7/vFu6Dakgeklr+wdyHCctRALPz2OSMzF3J69N+RD4
+DH9bTj7cWxhDyC++WmQ68dzIPwAzR71PwI8f79fu7m7v6MkEVkhytct89GkwHhq3RbIu6rX3BgSt
+m9Yi3Y2R7+xch6Ba9kyfoTN/kSBXAef70IUi8lR/0CQ1cIZRMbAC+evZT5cfdt9vS9v4c4B1/9Tg
+aIdFWJC3AV1Hm7IFMzy6xpw5JIc/cy0SE0d8mZoFnY6ZeC+NmewBOW87XOF6Xt26+Y5xLsAwkHnb
+Atrl9ysktYT9SjQFqP1slygaVhugbHUILI+NMzZs7YB/KiNwL7BZ5bhIcLfEDZ97rSYkK1cj6IOg
+6BANe+/jWkKpbudy/8t2MxyXEN7Bz1fm/ywt0UKcGk6ZcrfEtcFwpu7fcDbcWKCY8jgN6Z3+IZXI
+mGGAVaknHxAE3nS2eWrUkTtYEGA+BUXscX1BcYW0AT5cu0aAqPko6xt55O7/i9Gt6ZerAvaCsfah
+QIfo+688ZJTgXtdCwK/eETrz3050sVHwvYlkLVC0JbSFhWC+DemNcQ2781JSE0PhVgFUCI4Fix1S
+6KfK5zt9Cshn5QDEQsqsT5SU/JTHIHHI/yM99O4LHGRe3cK+E6SEwQ2GmINzTbxVJfyRO4wJsewX
+b1vwDx2LN+U45+YCsfMqajt2gJc/nEy3sixgwgUwpyOIRK0Ze58x7ryrM3vSCLl0TiPEbSHEzM6R
+22PwYD3iO1QUQht+lAnSN8kehAfPZp2pFyp2sBLHke1zVjUlzHCFC0xKx7v7Bz3vPhkGh3RECWrM
+weap01gdC5aza1R+1y1ajKRhLA+deiNPdHNVmgHmowMI5ZgLc/s5cIXrJIIMY5LD9mlYjQ3d0/vW
+PFBLvQD7yLsUX5Z0ScPGTE/tI+287mdK0mGuNurrnu9OsSwUBitBoX13eSoiyWE2HxcTrq96o/qQ
+hBkn6tPCSuDYE+/jptPnzgk6tTuenmRJDga9Y6WFX7I9ueoZN4WDu0uRJP3ZccIiJPzF+vxk1ZhS
+moFDRyKO/sL1JGuEU+xbENFdOhbuyjaJtNZS5NLmldx5sxZmQBVw+f/FkzX41UnmzY2Tnh2CfcIT
+OAU8aYittGJM0ZveITxZht1LrztyCPmH5V7V6wT9cSh1i/sSV7VfWHvFcGJAd42D/pBUI02DbmES
+2K0js7A9YIBodmvfDT8yjueCnzQGKYPl/j2I5jQfVxC+7MZq4oYz0mDb0KeTmSfWRC0TSfnDjnH+
+nzdPwzPATAUpnTI5YgvIZhTl9cdeNOm9IzPVMrbj6IsNl3cHvC5UohaeyCK4Zeb6WJjBVu6Y+68U
+UMUiui2naBqyv3+b/tWup1dFAlyw5fZScBKAZeZ6GcLBTxmuG9pm49/CfIV9tZtFpVh/H629dluk
+54vZePRRrtf9qw29gyjn/i2O/Xr9nhnQgC1UbqF7yz844Y5DByLRafCJwn6CFqmExRf4cLYap4tD
+WwhpNTh32bjaI+2FUYkwQVO90P0+A4ot5jtYKxlwF/qfiY2Eea9c+CmszVACc/5WuPTl9HKQD9V0
+OoYLaQdcVnrHuWk6FVlv+YAtJvV+2Wo07XnnAJJLFbdO8jcysEXQb6jy74pEmHLjBmsW6xYO9Q5A
+YHwooWSDtpL1FTJgtHN5CcHZUptHGrawXP5ww9U5VC3LwXmLiDcdPwRbBTDb34q9kK2qF4syFJ/i
+0fUErbq7jf6RrohZ5FLXLmU+255YXCseAeXvAjsZEhddZiOspfb9httORW+0K6AsBLxd8LUtamz/
+H2DEe0uCbIVG/J0rsTNA2Csq0yo7AeusbJY2CFwaKCWc2x4J7pWSU0tNehLOPvTXXjFgnvsJicGs
+1x+H63VUI5pFYyn70G9cmoD5lW5aTiVgjlZBz8geuL/Ju8Np9EQOrGDf24pexNJhXLjSRpBr3OmK
+89GivUVUQQX297f4OKp9AAeOT/Jp8y4M5w/7bHexv/FTWbA/wMdNrL4wpkdp1OGzI1Z7cxmroTLk
+vUdB96xRmIaLsM/9TFf4GtgyJ1XmQknGiC8WgQDM1yvcMTwkskI2zJ67/lEWmQqaaZDyY0POrtqL
+b1crgT1sZD1rT0O4teGDWqMnmQ2wbtrs6t+Joc92Lv225H21yTcqLIePu/4RdfUUOmam0LFKTwoJ
+H+SNE3b+489vc1FqhoyDEks8NyORN/c9ONUc6fbcz9DAo1qfz/fvIiiG1d7VIhwwjDyng1i3J7oa
+weG9CVLfITu+4WOMoNDPOx30vOax2O6I3eHCPuRnu8hJW7O5Yc5JRKeRJbNkmKM+E9nTkqr4Fiy7
+tUbx1R+K8tBmcw2dy3l8UdWbos/B2yrO+J19xrhLssyRyT94YUgIOpjKids5bU8snyk2N4t5rdWp
+lL5+MH4lBdCePCU9ZVJJ92bTjXmj6jRPfSntgjXK+NGmvvejYaSa05Jk0ujg4wgo9Gd/lfQDzgR3
+JpOHlJrpVavguLS4TwHapWqizg4ATyssEqjQoNWyIKNxOQKBObNpf3+yb1W9qP65zh/PnPpmYWUj
+naeiX2e0XeAaVRRwcOcXjRo0s8ovZr4Xn1QUmBl6YcpqXtvntLrirf5poSFXx67r1tTMdjJW4DCT
+unvk7IqAv//R33jQ2eDYxTLQ2nM7vrAejKk09uS76hv/h8YxjJNAkkPN8ul6QNsCbbREbGrzB5xa
+mcOgJ5LHd2TgZKa6Nnnz+2LQ5l2jL0jurJUEHIW5PkskWekBMH08foN1b8PbatgQhbAnFL34alu0
+c90mWhW6ZeHfvi7V/5MY2b+j6jthpbG53czC3PyHUEcDfT+rNpssvFcxs0GLF4LqC97PeohaxSFW
+VRNM6SK2e1rUAqzco8JB6qI9ecoNEN41FB8+pKP+UuPN31MyOlId2Iv6ZCuuHT8Q53RmySBlyHOM
+YUjUu5SCPTuyiw78Sg5e4/6+wC3FHaFgDkYR7INRvanFhpXxYfJNYlXza5A0R1DQpDDFPT4HVWhL
+tbnC4vdbloX9C68TitxpuWxajSWQ0uJB6zZ8koCqjCB8/NVEg2I+wd9jxUTZYkYNNterAPtwGXDt
+DUp8C5R1EQHxJ2QigV4Twz8y/4aWrtVvYFYEKXzOG9NxGnWDVAyUdfgM3D0PuROtTPHOr2ZwgLFw
+Yl4yMtxhG2sf2fZOtNhkF1bCRF5e6IBabLzuldyt5d/9j8TWIu+PKfJROUsB+olqeJDqPy1E6kVt
+xIj/VckHZsFiq58Zgd77TNzbEGB5QAdk2ecQevIkKwvcPXUlgLk8BdvItkoy8LYK8G46aYek9qWc
+vKcWwFH1I1NAkoGIle8QXfsaeY2/19rM8YjVJ77tfVPHOYcRfhCS9KKqocr2yP8Ev16wPfNoQWzq
+L+O6eV8Q+qTBS5DD1rNhUZfZibJ3C3fllSj92pC8UFsbtKuK0VAcdt7e/b2LFsAX3+PCqpp2rrh1
+ccqT/mN11F+E3dbdUtCgdje0e0aBlmdJNK3S8uDno2lIYmgu39FsZ6eX8QkQc57CVicsoGPC5gQZ
+7l7B1kvwlitA9bZd40SwUekr2Lcbfti5IcWapjhLHjgZ4xhT3WcuVF9BXpFRjBa/LsSjj7Acrnt7
+GbbTonYU1cOh8+3erwvRgU4L+LCFwV2lFhcJX6nV2BsQU+2SKd3X3Ex1uHWoYysVi6vkx/da2aK0
+k+lEVon8cTOA6FylfxqriMSXWPMg2UL4PXX+nsTZiIQlverepr+7BEiAgYU87kzpNbekO0YOcVQx
+1OdG79qxRuL8ADz3WffU9weE9i7Tni0g8lMJYMjBFlDliyErpJXMradahmJdyTzJHw8YiBpl9eYv
+5VedMjwud4Qoo1iUOCQHXLsO/xHfhwQiTXaCvxlA3O640QOh9ILCdtNPGAbYPSdCHmNkP2lNoxTD
+nycM66tq+IaFCZYDUJwPamyOKNHym4KWmz3XCSuK7zPEpTNpIDWwzkLJzB56BwdUOVrX/tTI7tXJ
+aJ8S4s3QvsDc1IC74nS3taZ/FqhDhJpJGSgtNG2J5NHIEspYY2AUu053Xs5KHt8PC8PAxza37n7/
+/hTBKtyQ9vEMCscThT6Lwsb0J1As8RRWrM2jXPdZtS1D33Yh/Gb9pA5B6jNsJ5y7go9BKDGm0B+0
+7I2TbgqQvRM1Focw6Wl1F3hEOg6z+OEdv4RlEDcaeYDmOORjHg3EHnf+cJGg9iyjnHVp94kHN8w9
+roCbHWtO63q1z7lGYqwno6vKSs0GxFzm4faXuCQ7DjL4xJJwW+hK3vIABOO//Ntd1msZsNDzXvea
+WAAEaUZQ5jUB1FZSnBHTdQrB5ldmhQ8dkjrkJjMu8FNlQmiH88H4Qxos6iOA0huC15NTthi/70Nm
+s+5IZGsiWCQbMXUuNW1Vi5EJxlCjs/xex47G0eRYAbvEqc5S4KPn+2HzMGxvrc+gTEgVE2aepwyO
+QZJUh2gK97Ii8aUrR8aRiiJzNxBUsJyDP4LUEYg7ZXeA3ZA2w8PmgNvzegIVhXI64GDQrsK3PeZk
+qhZCYHPfV36lCGbsC9HGo7p87wTrQJJDq+suwpeXKeOhm3QFvrRyW0lWKeO2ZvqtTRvprUj2v58F
+WvPz5qIWQ2L+oJIMB8pXNSh6TDtrSSnA7ahs+fGqtPSoCA6IdJO3JLWhfvtstECE1fheMkclfena
+SnoO9HRHQNkglNo0xDKSiFrEXj/hE2k9TiPYsmvRXmAm7EQ+Zl/11aoSo0LAi3P4mYBStJNrhHkd
+qmygEjG6T3pH4BmZqTlatme57KSTz1nPJWstjrIGy0vEUnOBmClrz530HlnNdlQl7bgyKdmvfQrV
+QgswTJJhE3DTbbuN12mZXsJSRS7BYsJXy7CRL+ESHoX7OGjQqCfWAEOzTjeA3atGZGheM+zKxg8q
+iaM9gjzBFaHtY5dgH0BFwBxd1WmR8L7bI16NV1V7d9FGewrTsnaUCgHdkGzsyTIbpMyE4q/vfYZY
+h0oHaPFIb7WKy/6HunL7ZgCzL70UMY6+VnjxilC1d43Xguc91aDH0TT7BNlWEFR1I8+P/+REeM9K
+6GGBmXCAuhTNAqYS4K1qnCYNbI6586uFIc6KNNLki9TSIotK3LwsYlpcqTwZYh6rSR5CBe3I0mm2
+2IPeNTRSOhSFF/sRoRYjAU5Mu46yhOk6N/X0ue7De2/KJPevJvdhMjgsdfQ5ndqyvpLWY2qbiLPD
+acvuvysOK1tJboRav+XPrNdBLdM6HNMRdtPPboe8w8p2Tb2yNM/uWE1v+ZFW14Korcta8D+LgzSp
+hmtPel1eg9XnzkzO6sXrfBVn5zL0EAIFxRxBzsSCk05Zd/JarhjtEzmUxiXQn93MIqf5XiGyRU8+
+7Db3nD8NObcM0Puxc3GQKiU6jicqX6tm3EoQ4AyYqgiLUzAWOdsnwXBqIRVhOCbfWon0kK0i6Y18
+pxMAbGjYFRq4+b4UxZvElU/UupqR+dkvGOJsUFT4sguk/CnEkdb1VArNEqLUK7GBKVNMR0hG07OI
+SWhC/hasg7PmXlMXlsnZdQuKRj7+rPP8ESgWx7hkkWAa4SArHmh2ChNBU7Q/pbMfiKSHPCN89yZO
+D3l/ct0rfQBTo5/40sgVFDycgx6Eucz2alZyqotScoeRkDmtsTU4q/EBw23l1oeFbHrOksDA6skf
+MfIxye8Tk0xfzRfrNkdaB2HFBJHw0u1o1+gN1lGTV0gkpOXScWRZ924P9xzEfGCIRU1zPLTmuksi
+TuNKpGox6tw5tKOYz/skGUVfQSswSvP5umfBN23b3o28SNnsYL8txWB0VXQSiHBiA4unfPZ2d2p4
+fD3MQQreQma//TiklaiEHLFhSMADpbboqfdMIYD8+mZ/MRe6pBgDkut3A68A2++yt68Rv/5zfJoi
+tyCOtIjPJYZqvhWOsdRNAEUmva786RxsKALU0d+RaQL/NAQYyT7oThC6qKrtaEYTX4uYJcUhrK41
+Xj+wGV6KTGvKts6pnmQXbSSzzcpvUmnsBa1p6I+ffNM600w5DQhtOqNeVqVvhhKrJ8oqsCbPj/dc
+2AHXcOGZQwuwjMhiYLZs1TISm7hlMnc/ButE+rRVxcSsWXGuuvFDpHe7CGh79KEEB/U1m/Hv0xWw
+yaolH39FJV6moNtht49TqCMrNPc7w/LTA5VrtsBL6prd1WXkDwpSMoaoS1diCWuWRZoG7Wt3djij
+SNKlx2ol4bRC9uRRC5ThLkiuQhqf9ez7l32Og0h8iWxrGMLXorbU1HI0N5FEAEWVLtxiLhgKCE/V
+gX5hIjczfRt6ongqVtN9x51affP5AqvPWi+GjbIZ7pJLn6HYkCnNFQaM/HJRrLPBLnmPnO9cW5p2
+m0fzfAesCa/8357da/ljmoc7h5E6u2X8p68WTbLVniluhV1tJgaQJxa/JBSmFu70pDLYCFanWV48
+C2HL4GshtUUVEE/Obq6538fo66Pmx8tSg7GKv3PuMeL5wMwhYRnWv300crIbPhLGe/IHpmH1lw2c
+NGxaYk7tbNOlPG8ICsOv+YqJkVCnCzUHSGclzC2qeuaVI6nnTRDPg/HF0emEHQJQrnqKV6PNaDzD
+YlbWxdgNL1B4UIxRdzlAbGwRit4da0965nnqh19mbjTUAWoG81IbNqi+RAvTGt5oPuq7pWq0Og6v
+IaaZosEBOUtABXAlOfuwPt5I4869rm9PkpoF+LvGcQm7fmOOc7DyohVYlAueGN0LKhFBVlSW6ZDP
+/8D6pu05ON62BRdEZijVaEfBAvpBJOS6PKqGY8B8eWTU+zy8kCVqSdposfhw9l+n8p99niQzHfYj
+badLP51NJngJxORQspdD3ynQ6f1xdkZEgTia9ORE5yBroaNmZpuGgSyFbCLRxNGdlW+PndKjDbeZ
+kvavEAKSTqb/zaIERmxXYEN4ikAEPmDP9pZMxCylf8UyYVveR0FoSnwy3XtHBggQUnm/uED6Laa4
+mLjKHItwuU3VOcF87hzpAEVrJqYBGL5cRwxj/CGQZje+xw4S3kJZR/2rAZ5uznuERUodoURWIu9B
+pBN49w14IwIlffZ0VpDSbz+38qWvGRtiJWefRWeL8y/kIcFNBRWyozl/tOFqMyy1yygFeLf4Hnyh
+iuD2MvQBf7/kYxTjKHFOrBY2xOzW4XrvAvRIuBbUSkRPAHZUXzAZ8fQ5mws7oDiO6F//7JoQZNsW
+FkIXB7ocr+2Gdg52aHCvQnbS+SEeceydfgtpEL6tawGId+VwV4Sw1MA8L+wxURWNhMjS9XfsrMSl
+/asGB2MSfCP/8ZeoSgf6SxVef5iBP49RKEuw1z8whAcnkeAD4IJyCnkKj1lxyWQyRFTb7w+FzYvw
+VOZDJdgsriK5PEp0KQEuL6oehVFfX4SMNrxm1HFW70BMl5mnIwGclwouDqW5ISV7cBx3SChfG5wm
+j1KHcz88dV+b+0VVf1TBYyInD42g51oQWCZp4xkXn/iPrOjcTVSMLFq9FQwBpC9uhki42fsoBta3
+I8VqnKMoA36nvfEmZlw7c8bbxrTzj8qUwYIcqeu26YfiJPsV9IMviPPtPMLHYiAJgqBSX2a1sVSd
+T1jmBEWeYekgolQvZlGSP00mrWbfzFg8IKe2bnUaiD1BYhqWPwRZPrLQBr41qPeL7LyAG8gX8x0n
+un8ADBv2BRRORwmyo0s+XG09ZiOaDcWZXAJIwUzfbTIxwP+jH7VpiNvNl32hv2pPGmpj8u6aVy2a
+Ur82u93xatZyOK7es955CDWRcpoiSNOt+N/F+gWt27E6u3PpF/xYY4I/XDsT8vUpoxX98evLMVoU
+edINxzIOJbUsCwaLVrCCrYE+6/328lqnYntyQsD3gE3FfLzCI7ebgfNmunzvnli2Z5+l5TA2nnhn
+If7a/5G1gF3PzHN0LtvyuE5JP3m2XeTtCF9MjpwtpGqKGmkIXaiwDO4q/MBDQrlaYhjtwDPA6ONH
+1ZN1u5aWnNJDf3aj9KkizsJGJmpk9srVzEY1NgI01wOc6tsI0yGoUbWD+ulL0FaFF7F4NrvkTAJw
+SXDi5q+87cn37URXykGeLRBkTPaVpR4KHcA4Wv5TOa0rRYth+11r9LsfM7ZeNoXJUp1bBcn+1JNr
+u1YIxD35CfSBTHdaYwJkiHzn0sfMHdDPaWl/Rc8jyk1+gttoGcsuWaaUawegurQig8H70QJ+mje6
+31+Yrt+HwykFe3k3GOebLtEaVqwM2X3qPAC7sdfCHFOw4YeBTNe10MPJ/5VYLOylDEA/UpAchxbl
+LWu0do1ThlhkyjkWnYAfllEwGnloVFwXQOCnPYDeVXe9Jr2RHt4vGaPb81c5MJMQzTnN3SeK5NnR
+zCmPqNpkKZxgaX8TE+8n1wBugno+2hCUAufiABN5zbYd3+N2455wrdgFFI8d+D7mUfqXGW2tA0/+
+otJt9Nk20SEWK3LlBpVYDNhWTKxD8RWLW6gU7yC+LavPSYUtjLktRJGQk/DwioG1cZlHOiKUyBRi
+Z5Cx++sDp4ENMOMaLzRXuBY3FTiQkMy/K+dYW/VpjN+HAQoRUbiWoih5QsiYb5juOANFwpVMnxam
+/8Tr0p1IEtmj5qcviYnrZWmlhgZc6+37xbzynWN8Jrx5IbPbwgUiU7yWSZFqdxY/FP38a83rDAm+
+eQZ/ctdx9fJMSeeRlP5k2gbd1ad7z1u+1YHbgNJKWDhuTIReJ0idCwFCCYtpG+SJlkT+ZRY/pLZP
+SlGanUJzxPXK+AEDb0OIRGOd/LEysOtIXO8MwjMxRmyXvwfIyFMzYPWS6AMqHb788Hs7AeQEjNKt
+KbuWRhM75BX7chh7YaMY1YfhcElQ56l7T5M1i3JCp5aA4mDJgLv3x88EwiS6poKBjErdFUExbq1P
+cdp/wPe71GAEJluBShigKhoRdWqBYllq23y5hbCEpgrlXZ037Z67xYnQkqkvqswqBFwRX2eYUX/6
+6uNZUajWuj3XtPVnUFpFKTfMnWdOjy6vXmNp4tpBFA2aYCMByd8DVUP7nmIT37bKOgq/fhGFjKkq
+4RR/Os95u1Hkxa1LJD48YdWjdLAiGKFzqIgLPxtNzSGba7JAzXtGWGlVMiAW3rtSpgcoe3UMp0Fy
+xVcoQhENnPaIVkaSU//DizzIZZiGoNOMRxFnPEZraV69ttejDXqXXXQo4d2Ss6Lmk/YgJv1VfLZp
+94y3aRHqlhR4WGtNznxjQvfVe9Mm27DuhxJRafh68NqVQ+ds+4GnQ9Guud/zbTtNk/aBLFCGE2L3
+ad9//TFJnNm7CVP4XTS7Zv1WI2W5iQTKI7zFs51MwoN9Hlya0rjOttUYKv5/xqf4KFIicwm3BDSq
+VpDwaSB6+DTrNpFBUBlT6WOb6W8gR3gIPpshTFS+9uNVUqFRY9cy4YKgedV724cNr7HvzGBS8uRZ
++sPSzvU0cCH+uon5ncvi2mVd9RdwhTFgJMEfVTZzifAq/wKGc2SjyFs88mufRp5WpksApinoYSBS
+jEUjE1JDtQuVeAeQOUzjiiOFsv4DHPJf6r6ZNcBf0H4FiYGwyTBozxQfiRN00qmbmcLwELld9NyQ
+03YPXj8ijjTsauGlAYHM+upAqUBR/kJ5vU1QkupjVJgO+OnuxKR55LKyFPTSMWU0k4mc7oGphlyD
+Q9uXZbq4b3phdNpKvR1z95M7c2zeOSVFLMXPdQr+j1jmOS9N4oDOd0oK+oaVTR5GzR8PIsIgrMtT
+1TwhdC4ROJYflYCkmnTHfvPswXn2MaZeknmC3wCLqiirzeMBFQGyTaw7P5IJfpNM7tjcMyWqvNaX
+EcqRet4TDQQPGaomtmPqSBai/nt7qsm0R8WUHWzhSOWrPt/7mgYsiC0VS6WB9ya2G4XyG4oLRKui
+weHbB0ttS7ZLK7KoMRZdX71vN/gEAC4q56oj6h0LLWnKZD//NZrHlEITST3/bqTcTDaokwZ/PpsT
+A55R28nr/9mI35OnrQDHVRm8fjlQ1GPslBX92nMsBkSMi9A6WkUOaDNpFdDHh3TgNSWIe3Ph2xz3
+wVz3YOpKcSo2A1VhmI8cscxAIIvXc/Uye06SJ7RQR3C955CJI63HRFpdJUu7VMCfNrAUO9loEBrB
+JMwihZbdpTmAdJ+meFcQmb4QfDdjqdl7lTY2iBNLfmuBdCkT/Z8zs8mACVw8kGyNoerLbe2miHs1
+NRGQGlf3wVYIB7YHS+6X/SzmLqn6MCCdU06L45GU2zOCm/PfustQgqbJmXchCiYB4A2+eJA+w6hT
+Faqkvsec3Obzt3oZgtTRFREYs0vXYT7h5r/VGb9WCWIgJiebCn0C27BuSABy4xIG7nblie5jvmud
+vLaC42Bn/cQPxCHVK7h/VpqZVbRI3dlwx7mBbMI6P6afzcuARpiidrIcFf3+10qr7Vwxpjaidt3Q
+SMLtKbIdQKe6M9IIPUtEHVW29lS8L30f1I1w5JWk/cM4M5yJgOL1hv6Off4aIKNZGgIPis8gjMZL
+75uPr85jfUCk85tGeU7b2eS0b0bQsYHoOEJQwAHNJXcx88bQwBnsRklQHOa6B0atllMZwFJJmTi5
+ZtqqRZACJ7GH4vYCbicdmJvkpV9GWPu5PJ+h+Yp9IK9ubsPgHbx6EXLmXqXgOEy8OkoNqS8VzKvs
+OmkvGQzAVdJcmAxIzTvDUbceFC8GyBp6cNCvUY6dV9ZY7++Cc4VhqAubwfW2sqY/rKHzpCo3rqxW
+2DcTB8SXFWynYuMvGjRpel4vS4pMtW/7+NZUGJqr1M7AYCnOddiNG1vykhgkvGzzTlrP1vKEEfVI
+NihtVkRLBfpmacy4h3gyWkyOPHXYQjKBj644UeWFrOmety/QG1ZLPwfMg50gWoFJSAhi1BJsuVJE
+dTLeEv9sR0dGuCXxqHLIFmLh+vtnYmzjiqIkp7XU8y1Vdud2Q6/a/6MeKSbr1XcCCaxcHr8C8giC
+LCenJgCi5aq6YzNtOh5dY8yMXssLBc+JWPnx6Z5fLhHoP95ixDR6d5s9x3ahZ6slppurB4fo1SNd
+wodzrOEnorH4PRMDVOQsREELIavWbjMN1XPjg7kh3CWpsHN86I98DpANM1X7ooN69Lm1SPW/+7rl
+U4O/rtLaxMM8CndLv+LrZmYFExim4P9TKTdjZ0O+g1geFIbjk5Wc14TOBD54BiJXK5Njzq+eLkVU
+58QCVPej4TcrOhVufE3waydaI/nAV0T/r03HdtH+JFF0XJ0EgTCfUZZ5RFAjhzXWTX7WhiqqklhW
+SyI9fFYi1hemXouk32KQZd0W9K00kQDYAAoZ6FRwghlOQsiXEBNWzoas/+wsJS/rsCrKhPNi61Hl
+7P3qttIX5gv+B6yCArWLugJqn47elxb1J22JOP0EI8vxFauwwdMI78HlQxumNq/+37cuQK7wJQrO
+qRRNukubSUIsCi0kbIr69e9p4dqiWRBSTEV3tDqw3b1L+WDSkRWxAsqO1w8HSwk87QDUJPhqvRv4
+upsRMSlH50w3dbTTlODn03ZeC2xdldkVcDoy2u1LM7VCO1BN49Ssa6/7oW8B13GaBe9Wy7juRjVp
+80oS9MSweCBLMMo2SyGEyT6dgc+Qk2e+KPggd7qa59RL5vS7JC1UOFseuHWPZdR6nhhOLeTGY8qU
+rAcurReTEh3DiYKinirKzHP8YTbo8W/s7sWdio+a6MyPDzVmW/uqVrw4qGdK6PlArPrlpqnqkL+A
+1fjrHXPJEMnf0VoFy2n67LtS9AjVrRNuKvKlUDAzjiG6AeW76DH7QikF44tTBBzkr47v5VAMYb7P
+MjQmxN090gj5shwHzThEK3TwTSN9J2MAfB2a8xnl2Nn8XgaD0oAQn80fLJFzvEKFEkngcZTsfY5l
+8DWN6nPj6/LszP7GS1X1iosDvBnhDOA/YPupBIoYYE56Krlx7gEaaGMwH4eUwVakuIN4ZEEEbsGq
+wUH4nXfW0IreMlPG0m0RL9NVwJPHM+XrP2XM5wxqP//qkGIOeA4YzkUISqWv/xgk1rmlznrujEIb
+Lja1zN2Ro/Vvj9r7J+nEJghVs1Po8l+G2tdAIprstgUWHPko6IRuDvnk9w3WVz8yWy5BRFdM1VI+
+tkBO0c1enPdjcQPSowVEgx/yNx9mk39idTpnrF6JVO+fPbkTqtjJkzC5Hsebg8zK+GYrCW/Xmu15
+4Wks5ho2Pd9iPAX21ByawVo75bSa4tpuBIPRMXyo8dwPpnQnqF0XUMyGV8S1BSdsq4Bc1n1sUJfg
+Z89hNqCmi+KckH/VnlwCmKk+WK9f0lDa6gDJ1RFyGzHzs/3d46PShSp+tdTdwvFlbvoV3JSwWZtT
+CnqoWfCEnnsgI3+FVtQHyEj1Cj3K40diuqLyCyTI313oNUF+QJsBaMte1UvilZKdnjyHq1dd8My7
+cSxw/qgoqqj6V6CjkmzrUxHolObU2PQ2dB7GdQqfn3pMTWCkg5JbXSmjCiTzm1eSfUKCt9ZW/PY6
+3WzUSEs2FmaKMqhqyUoVHZBBYI3MQvCk2ihNDLg95Fc8S/7iQcRYF1QNVxdlNHZh4zoZ9CACI/HK
+FRoLUtYgbN9UgU6S0D0XQwxqwpJ65zZRd6UbatKNIojCl1oKYcOeQAEjRARL1nzIdspNjJI3wGZi
+X4VSNxZxfgCySlz4L66BqyIiiMAwhG3qR+2E4ag/VIMc30VLg06gYm7UtVzR6HfDRhh/Omb6bT3T
+IkGDlDcVzMiv/ZC8s0GzGFmmqVZYcnqlvdlHN84GxDcWn0nLQcBJ2z+5WzzUAJXLvuW1jzeKfpod
+1+gEisB1FtFQYBS+3Fh18wXXfM+ztcHdgYEPletMaMinDQOG/gmcWdv+9wkU689oszYzzHavC/mD
+5ION5uylpQzeTmIeakkiQpjmIyd7uVsR05u9HUZs3oLzoMWo8MYP2hfvtxKkf5cBpR194DFucDwp
+4hlqeV/1jOWnZPGtZONv4y9PY3y9RUcBn+R4VBBniL1m1OP4RtXUuBeGsRd9HwRropVA2RMx4AMa
+bOKR/BCVem7u4xtAnavZmNSci46ciRyQEvztmxhVHLmCLYTe1UWLi5SdhKGgfULyhOrxYujOmtec
+2QzO228G0qZai5eHXKQ5OlGBfJJ1fJ+JX6k4BZL/t7CwVPTIxHuMvGF8t4VAziHQcg+G6fPadtKg
+y8eacI0DNzdJ0EI+Oa072Gp2/nJ9nI3KBL7UxzALYwQd+/rEP3gOqOBK2yCwEgD3Ei5DnIeV0Ntv
+NziledkeYQmVMk9HjHc6sgU203BtMSkRmp90j5aFhxSlu6PxavIWAirPfJgiXqColT86zf/A9eCo
+gjFgPEAPtv2KW+lafJ2JN2AngxBQRO3HbHrXAbbfXcgLXaRHm3RBKPlMqULFl2Hfl6t3tjz0wWD9
+xJmi6ngfaAb9Ck06DPrbCraAhjVtad1ibqheCedK4fb65lNyauIRYnCAfUmuk91bx4tV3xdZL1fn
++PzGZtLKrq9ybG9UxEwDHa4cErgE+1Q7L/PV3KgfNyTN7pmHAgmcHBB894/5il4L5KsdU6XL2y38
+TnXXZw2EGUiZgrP2N9kevIVXiCaUqemx/V0wMYARDaGiLNSEhvim1pjydhdUSmGfv4KwW7dn9PEo
+MkwQRdTaUyJiB7YkxqJLqnoh1rl5DytJ6LPiblY7fAhoD0gDI2vLTycd+vG6OSmFXVB3uTn4JZZw
+MtSpI4hxlR+AxX/3y1NlnNS1F0s9A3T9MFLzY7xg6ikG5Qo160SUI3+IgfL/eu/5upWCFtUward4
+FNC+nSioDyz+l5GB8Dv5FzOjDeeIRQeW6hS2+NLb/fV/uPhvQBl+ClJ3leivXWVYI74nwZJo58Os
+kzXugrzC5h14F+/uVlO/tzBDptHujikqVwDIHq8tJLdSNfcWkp5o5V5/jNZwCyJTEZJDrp5VogSM
+HWPLwXu8eq3e39kGAETEKJzizn4GoEDzLANE24k19Q1Dltcj50l95z5ElGDPna1RUvwAt4Imxe8T
+84NmEpoSaQOAsb/LJIXi/xBalpzTbGKe89qTDLv1QAOs5ciBheQdssUEsmFLXVjguVXgD3ALduVg
+uWLf+3V9r4B9tscVxJb2RaESmsWOD+z38gmaxtYgMwYdqi9fZreVOC+t++alZHqwL/eIhYdmZPGV
+DHw+ULIUzZO5GhfuG8juV8wQTq1fTeWnANf2ztslmvLb9vWH8KnrzDxRnyHP9vGqSeOOqj3SxIl3
+K9Zv61BcY0yheXW5FkLOl0mkYKshzkSAi6Lmd3Y6PTJzRItWgGV9PYR4aLYSQcy63umhJoYr4hpz
+fhfEdGFxy5LVI51dcpb6anrE1uxsunTeFax5JTHNVfekHKdnNFZ0u0wHnGYEG2YYaVIpNi7kdmHg
+jJAU4+XyDqneFFgR+DcjSIw9qK00/k+PHz5EqVys7lE9xIztDmkebZzE5rpDSqnuAuXi3c/QAPWE
+nngZhPXrzgLrT53jvkRwjAcPISTpoYEYTJIg6oFf62Shh/aW1DaCcN50NIJTBKaH5/qwhEuidvzM
+rFiHL9P/XQu2G9tMk9cJz1hAnEY8WCGX6YIouPMP/VJZ8uhIJDPAPISwwSyw/Mu1tkkCEv1rNYZm
+oc9dDnLwehL9YPLXWKi4+sXGO/A/7kAnzBgMESg51swaoDwMRJmhn30Py/bdnVulXZswG1y3tE/c
+5qe9bj1JZ0E68JorQgEazK0p4wSEQQAsY/0VC6bnEmAt3PIyJ8T8I+hh0tOhZEpG0JPNOHQL5Ky4
+Pp/qWy2KecqrRsA9/uIe5E32I4WMjs+8qiuO3Hsfqfq5FY2LM0Ca6YXWLnGqB9dhw/yiN7rNaoI1
+qveSFkBkYwJQTnkyERhsFW39HyXuW1Fqg9AwHYDXSgV6wg/ldrG7Km+szUDZFdsbm7s2CmgS6Ohp
++GPHzFYEvD9Orb7poEf3AVVFnpcNO788/PqzgM0/9qjhUAJmEzsJvjJWJiMsQBZl2kPycYIpfIcE
+xqVkEiMO6/6tPbmOMF3o78PR4Qd3Dlj6t6FE3HSllu3/orHjJlNQjJ43FjkZCx8DhLQYmBLfEN+q
+KqeNXfZ6UBwYQYcIM0vq+3Th1ShKVxM3kgNlLVdXSifoG2Kq6K/CIPlbF7YLagPXXidmpiybtHhG
+wX8OyyYzHEgmzW29FB46klccDSXM3ZbHI592DswVABFquZyKug7ONq8fSWhmiMBQL7GF917Dg/X7
+4Jr0yFZOa4LBM7b6QeD+l0nCOmgRsCwFrIzI0QNTReZF9dx0h6IZZucw7AIysHVxnPTvPa8DvUWj
+8XMnQg1GILgdQ7vGzOvX9yqDgYwLB40z0Hon9AU51g6N3aMdGmTKzBt7R4xf11nQAxJswOvGGDIt
+bI2kCczAMPJ2nkIZzqEEN1ov6KHB2bBS7SXguMookk0xDqaC2Ret+liSoNXAgVqivjHHGV95Y7vh
+AyBLmvm3xh97hOvTsPJguAaeXIzQsGglAsE6wieww7eqNHsa1Kp+YCDWypFeocsDIv1k5gBuyBKx
+zjhYScAAbhySO/y6k4NKgPXfKirzcrsDekgKfmt6ld856xxVGQxhhW+j+CxubKijRNjQ5ZRzgKj4
+aw6Yqz2rwXuqu8/FQyvhSG2L4s5wZa7c6Rge4Np8bVT/ktw/VNiTrrPecWc30NDn51RCgTO9PRQ2
+NtIwDgyVeO2hng/2rvCL/pXgHyB7WQ1K4KVzdLRcmqgX28X93xIaex75O+QwpzPkdp2Pd+CfBhHY
+5MyGU1k/lNXxsFclnqU64Se5lVkRE/rhLzHmjA+mzMFSej4tUFO7oTNsnR6DVsLKL6pNJ2JQRIes
+qD+cy8UvzUtA5hHr+HRT2c4C/O6T93n8PLc7K/ZVVzFcB+SIORm0rOMJVVJTqrWlpAC/dnhfx+N+
+ZbFFbwriomTeQd/A+qmET7uopN5RFAVSb5WokDfJwA4SkKCoikFTu1tuTMRNj/lpA3PGQ2LFNoQE
+M9TNvyny67gNP+4BYbBkp2nvMp102++hsDKCrnBbiwaHRZ3aRw7ATBIo6r7u0ZlunVuID0cRJIkH
+zQgtiQNEQgwMsQ/fzUTbyhFuQsUEKnyfwtJaGfT+5V7kVZzKjD3ge19LUiv/mNuD3yUXhMOeWfRe
+pUJE4IFvcpscrQPehOoOd7hRUcWH0f/le6G3fK6lmBZneGsxxLipB9S6xFpeBUH3FMZzXJN2KIVN
+WG++kKurRLC5ez/xqjbkdlYGVPtA0Zys3sOq7kxMAOdGNlRfo2UHdGVehJoRTyQ+nUhF+kSTelXj
+CzOE55cC4qX07kXevlq09jTzYoI/26Y7QxCSya7+tuzu0orKJ4V9JB+3O1cadrh3zSRnudDoG9vG
+Co9vfnLS0Mb11fJ8uwehtO3OyHOESaLM5WA2KRHIhi/8/4E19ZtxGXoAidjqaGOrE3MF1iyE/yK1
+M4fQAKnNsx/DkbUQV1FHOhir87+my9zATuLOl+85qhDdekCGjMXbZq+t4Ft2XhkOd1xrY1OIiY2W
+pPK6Qx86l7NTJ0QxG7CHe51CBnHgWcYSw+NS16GBi2+uT65NzcXTAdWtbXpDsl5Y+Z7xMKLRfXPK
+LeRx5q80i1InoYEt0FVIyZ8IcwXo3v3+4W1ZqIyF05h5C9phxe0eNXvqi4FkVdwaXLGanyYnyhkO
+Jt0VtHRZjPZ3c4p0GCFEPoYUj33kaIwqkCgeUybrRdpCcmYKt4LgYRqYX6he5DGDjBEj2LtvyVLA
+eCLOCfzqDcmlDvnDkotXizhQMsB/FPwsjo2G6/x58AH1FH3MWbrtbTuJjaZhI3FgRSMADUGhgF1m
+wg8tQ0Kf18nNmY7eQMX6SdsPTc/BZQ+xkVvFZUGB40whpOoq8QmI9wCKakbS21akGZUNXY94k+C8
+/Il8AeBTdnygmqvr3mstQhjgE9IQ+U4/kLd1f2gNRgeEry/1cgAZ5AthjAqTmXKdcLs9t6scM5Ct
+j5vSl7KBR/UXiKvM6yC2vpTTblq6VrvYBEPQZBwNRA1lh/IV2DqA1Sp+yzLBM1OmciwqWQNSAeJy
+igKrUpE9Zi9LsEcV8M7VwIGHntnJaVW2tqaipahWWZJ0W1SBVSU5SNCdjgrX4LGHkBHNn4jpmVHB
+tbkTxA3HnxmCjyLaFZGsnyNjw965GltJVkZO/hy2snEIEmv5yf2Frxd8QXfCrXBQdxywSZG9lyHL
+ha0BGGictH1xd1qs20rikjK2g9D3m/FASjq02FRCn/9KlrbqyzgGDWBYqHY2lypzSanZqiDI7n/Z
+TuLbR8/KeLrl3yv41H8+X2m2llM+EEEAp2Rj/8Kbg6sjB4ajrvRNZ45MS+cjnDIl9cs0e0wsBBq/
+6Rwgwu4/Nsak9wOIoFQO8WryqWCq9VcfmWh4ak9qWncYGLsHSv2Gx8VGtco0t5BvX1SWsZFty71J
+BlgT0V8e8eZyo/vdCl1Ob9sVPs10Mx8+D+kTp1EPES1uUt55UdJ1+F4Aa13yuD1ezm4TFEXeuG7e
+gLxTGN1uFyod34bBdjxMiic53+a6Xk3Qu18YvWUn5MTDleduVGPUynVltNwsk+nUKd6ocTG2fm+2
+8137PWlxHDhGksUS5RYjIawVORz0W571iqKIpqogw7Lpl6WnHx8RfpfSfrIYF0ekOiRVYlmi0MAU
+lUhBOqf0bAI0w2wbjNGd7jGONf8RlUIZUaqVzrs6nNT9LvfK5mN6ekIdX1de7pSutZLY1WskvpiX
+xicmXNMCmeI+pXQzdYBPp8bcI9n0u8/NEMLpveL6kde+6pF1EKw1BuyRUab9iK0OfH10HlIGQp4E
+BsK/p8QFC+JCFCRIduNrzPOUtloulAPCHxlCEQUmLhs5RGoXzn+EOcHvEaieb2+tqE/sPUnZRy9Z
+fIMb3XLLGZyGv/9Rn50O4W1R5vH8REN4zUprZTSEUJVOEuSrfomPDnMOvCPb2mlwRXxg4ZzlUzEP
+jHTSSFOoC4E0FPL39/deXlmlmc76DyyU7zdqphpfQDWTY9r0CWCHtUFmKemf6mWh7jZGeNlpyl1+
+klQIJGTB4usX+byL1lKNz9N+VYhwtI3FAUIxn7ibTUOYBv7x8bQUJznQTe81iIIYRrzluAt1Gic7
+Vb7hhd3GFOR8njM5e8u/JrEKluPhz2oebXL5nJTlCDpTTRDMEHVcEvm9s3nRuQvcDLybkKvRH14n
+kq13Y43Wk3qVG9dbq1pbhqMkNBBpTtAxIiEWfcNQT2FzG4XdlW9e2qLaXMfdeFkJAp6QUofbpsI9
+ACUGt8M0nAdx90QNHSaaNxn2wZQTQMpn9AZG1wjafvq4hS/CZitAI4dAlUxN0F9dOVC3OKswUtQX
+GCT+huQ7H9mqV/xlpWcGim0kwP7vsSNtg1NjFW8LNfQs351NTGU9VTwY6KXJ9U3J4FzOVZc+4Drb
+Nla4ByRTUfqJxiSxS8khDp4sOi901H8i1k2TG1xdIWKwT+XthBxV7lGSd11ez2Fbv5/QhbtqLYqS
+3biAFU9JK0UtBGt4OJexK74A4HeDsf4+7kY6dx4ZqkXm99UoEllNFF0oRlGDOq1qagtvQj3Ot6uu
+H19uSGWDax8rCw2GFhunQSc91HA2cn+txZ7aoKJhleyYhe0aVZc87i1GrNpIxH5PJK6KbL3veWL7
+x2MCTS25ulLnj+N/sz+2ppX4+UroEejE+6er8v4oEvi4N2b/xeDtSadGbm+MNBCp3y38IJhRiyKQ
+CJ+GKmOjVktMOaLVUYpXZwuqV9R+kX+fAJUL8WUXQN9E36ckaVDCujiplXOPw9PyeBMBQmP1LiVY
+q5N0FP0x8Wib7gxfVghAAHr7M4gSMJBdQxVl2NDRkwizByhWewsk+KqO24+MuYNM+cxtlxJaqq7w
+V6SODQgjlnWxweJD1P2chpzc7d7giThLpoxVCcWkle8gzvzRd0Xur/OIFe/nHLQ22JZOq93fngPI
+cjIoAwGB7TJscEzj1yqoAqvXBq/OrsZFhVuozhvMCTPlgUX+I2SrrGJTqFnGxaAg6rDD61Y+IHyW
+Bd2DzyR1eRVlyhzEJctzdAB4iw92YzBE6yuPzcsQ1C1cfsLdUXu/P9YZfn9Xio6AM+1/KZFPnNQ3
+QWDbIwebBK7FjDUg772ASGGVnSaM/Sa5OsPEC5VT5Hmp875fMnp6kwvxdVAc/XFXcBBFH+Sg+2zY
+vAQq+Itucwr2caXo4bcHLNkdfdT7sl7XQX+IFDqpG+zYAx8CXA0ZB/Ip1MMEE3jgTgJ2wjU6Z3IW
+4DOgKyuw01PjPt/P6IfUrjoVFmrDd0OpZqP/M4vQKv5VAqVn5E307xZRrHzLetuMpTXfmOC33n09
+L7VNRPS/6hQHeftDblwtES1fkZEOfrLuUK2kxgxHnBG60oF1PNA5Hpaz+FosJuyFsb9+HfAL5OPt
+n4pKwijm/Z6HY7fHb8e2sVjktAHSLxEhG8HEvr1CRkHVL2XTY1uHyjd71H0TFlYC6EnNbH47Z5d+
+Ij9nYJwmbToar8H1UIK4SPitU4sKmPpXEB5UUF2wINglgW/eY55dKfI46N6spppxF2fmmW1ZzVks
+bn4/gWpxam/bUpqXNKyLmBks8ZhAMYC52/6OFEa1v5IoG9BM0pX+cxBSZjhfVbMkYKraageWf1J9
+jpNRBqS9EtnM56k1rx+wStD7nUa9Y9/TAKbOjCS82/rgCMQCwAjvWhLGQHw+vmJGMORjycCC52or
+FXZ5TnEyxBzysjbScPINJE2QiOZKk/UcpC0QDi8RlCW5xODzL5ht4K2YDA3ztry7tRfphNoo7a8k
+DwlhDAnJVsweYVkV/4pxcetZZXUdnQj1KAwWL/n3xQV3V6D1R8aZYSvdQL72FcwDGlGxM2pvDadO
+fAqT/un3SWEFFczFiRZiBlPUB8wRgcgRoA9HbJHRPFqfaamkxElMoH1PogFkuocvOjcKUwVZNjPQ
+O6TR1VO6Urn5WvrhVj1rCXHDqeZM+RUiyTW9kww42K2x1i/mzDUOERdbMg0mlWfDdgtj/aNaP6oN
+894dnV4HnnS0dw9ie9GpLsZ7L4NCN9Bfl9ouaK92o3sAoWOOz6aDZtp87C0NQFl601SOPTYdZfar
+g7PYbK2wd5QWxRnkdtWth8FN/luPRdlSKNulVDYWBxJq6/rPFbg8xUrHGZz2d2BHmCorZ8Nl5Fh3
+meCiFTLG1j4VGiL7h96oyka077H570Tgl3/PH0grABPk9VJpMVCKQjY7scMo3pvCZIi17o7JA4Jw
+o4T5WVSpSSQfXqs8BAvdqRSc6WshtBqPfFwHOkzKGruUZF0TDDMZ0APGXP066mPsbKZb8KOUARyR
+AZ1LDy2Ii9GPcc4ueIaMd7pVVmgXOAAFIq6BBjE7m7zlj2SKgcvUs2UJtu0HVLS2i59G67bo4bot
+Yny5+wPb3vqzAFvkuHTHyyy6Oc9+92/qrgKMM0xX1Kl9uhZ5CfHyHGkGgrPphEX6Dz10IraaY5U3
+71Ug885gqnWxGeOxmECE8uibaaf04qp1eS5cdXD1MAZAaU7quRhmil9T8PUSf5g66ArclryIkP4m
+8LpENb9DOFT5RDwPN6mb5tmevMET5SNpI94WymqEd8/DtYl6LnVbAhXFELczBO+nb2EK0fQBR0aC
+RU/3eShVeRmA45btoG3oEbUx6p8IVFNy/IwaBJcJNdAC6w3FbEuI44KVeJaB5ItGx7DLSC+PzocI
+IDM5wmW0rx2XjFZ8ve8PQfJZaGfF20JbQJW3C01FbTpzEPBdiLX5R1tLiumEwwc20y5o4YFivc4Z
+qGAl+vEXkKQ2NeFYE/DLXDAJdh+Ld2sEjp6nCVFIGw/8R/31jpzahbGyKHYRsGhah6TGCoRH2nHJ
+hb2G+kPFH4ITF0qp3r8by09qnYVIzNurf3AZztmSG4ZD3M6m4V15tB8eOgcibFor6nnS+EZ7lvoE
+7hGStb5AzX+/sdMlI2jd3mNTayCFHef5TEDa8un2Pyi49KULCbdt+pYtmKQyzJ2WtAQ4T4EhmlI2
+Dif8+oaM4e2ftm9CLjUg/HAkb/ecD5DbSRB89+sIvFfSh1jlaEISu1lUIEw/dGQKRIbq2w509bpo
+LHMcHY5cV5VjX0Oh1jwLMt7E07oFdQTf3B+RdAkHCXUhzhRjDyN98kYQNWLBVaj3hf2dV26afscq
+hoCumubrBDPVQLSVOw6INUthBC7hF82y1jKTSMhExBBpoe2CgxxPmIpyJFIRR4w0AHfTW+/+y/nb
+xNT6QrWWGAqmWCfMBT0Ntd+MDcDRSCWoQxzYg0nJ7H49QTCB4BVNaGr3Xm2d+RUX08XOJRepkRIo
+uQ2q05SAlT1jQkjJ+pg7ncpayhb1uaxB1BLNFkzVv7vF/9rnLQ+cw1bZhgiT1IHgzLvyl3zOsRgk
+RX1560dAGvWO3t2NOvdtZuOrFGQnnsPhJUBOGUcdXBOR0VNHXGg4qv8hffHNvsJKk+ElIf5mywWK
+o1PPEVnsr3mvZs4PVitfTl2ecu2EfVdyr1tA1aDnKiFsFbI7T3/GsXyyKtgOIsjNMwgnSAjQmHVa
+RxjjT1JlVXogenOB/jMR+wguSlPOCHtBRlNsV7CO+07ZFqmRl+BwICQfPoDQd4COVXX7ju8Mh9nB
+eqEOFwF4bt7X6ddop4MhHk9qg+mQLmKImUwEehmCCP5uIBtwWWNWJ+zG6XlMipDdU9z73Aj3Bx6G
+upazmmkxgsseDyzXFAfq/DAxK2jhFkOJgWE3uizAoE2fDcxs4Wqofv26LsK96XaDap31VilTq/8q
+xv80gHkcKMxws3ZPS1clx++QrAYa1SinLnJOUwiDWHLLKdMjb4wiyvhXTZ93aZc2tSkPBLdKxzJK
+HSD0hMnkxliHLXcxtN9X5Xwlrjjnbg+6unXjiyaBf46xOn17pBAjB21W6rVraLCFW/4zEms4GVX0
+VVY7jSqVvMbTM9ukCOg4kWj/HvIZEk0jqGCtcr8U2VTR4H7GW5+xMErl84APhLwThoPqluwOq9U0
+nWQkZVEJa7vYaKhGKy04ugfxx5FGwZ3B1zS5U88t1LRfz0i8/5/H6AM4IwrbbJMIpWh4ytyrfVvA
+yXjucT7VmQKeJlkK9zB6VSrmEIfOAcYc/1b8PxSKnnxjO/COrOCndbfW6kaBw8j2APWiaSR0J63h
+qhALfFK90TV/75MK1sGB1IYNh2hWnY2h8yZm5bCXWKvPJoXnwaj4+2LUpJYacPi08zbFySzKpp8J
+JviMuX+6l5BirS241p/ZOGuU1K3n0/DGqcMAQHZ/CX6t8NgT6ETBG2dDYedITbEiT/af4pO72aul
+WYZiHiztsskJLKXB+xN7F+jMkGdPmPs9nmpBJF67VdnR+Nemmv00I+iPMWZTPgS2iXS7yzpBMWJg
+4xgVoE8EQ+/lwbPS/tWMeHl6pT1+yD6zsFBX369ca02ET5NSJZzOuIe1eD37YTALIBDzB4By8z+H
+/IJtl5md+MBU8KnSmH2Jo3vSMyxQXnYmLDvl685bf5XhfXcEVBC0Ofz5vt+LTR8yfaw/2Rzb/elW
+84pWSZRSqKqeR/YncgX78nIvKp58YeVGOHdqbKOnrCarjKw864aIQqowJwqKXdyDjCqT8sU0oeRf
+r56bJUT0w/Av8SG25SCPxEj+Anj57+8EFCyxH2IbJFnN4k33j6+h5/bzhQAjA1urzidOHB9Qt3Aq
+eNlj9QRpogPMyL2A4yBmzVU07AIWOzAOa0EcTxtWbwyJ/FoJLVCeUcr/CpWNmVZEDIQMosEP+dn0
+F3HDpS4s3Y6+kzgDL92UWuq2KB/4f2gd8KWRkWazJeQgD89bmvij+/JH6W/4eWFk7+jZY4+Yu7Z7
+7gIHxi37Fn4X4FIiHVh32FYTy4hrpWa3Zf7LlrSoLSWRmWWE6DqFnxnpmAWpvPbeH3u4TxkbaKLv
+22quvi7a2k25qFf3+eaXJYuvWxVEWX9EuPsh/0D/KIMf/jtYHgwItn5+b4mkMWnvXw/7NS38fgMF
+tI83sfhipK6ZcZysxYqM7KodZ9kMY0psPecY5Yg+caofre2Skf4Aut462MQfIoiKXaHD+fwCDLF5
+7tvKcHsN6O33oh82qmRG0FvuiGyNM7O/7mvQeYL5j6+HdVODgAfxbETPfZvp9/nrljDnxiMJMyug
+dmxsTKpQTEbNoCd56e3SwPLEGDstFTb6ZPFsKWFqyZdvmAO8iSdAjribn+Fkwilo/Xg1+owKspXn
+tBL6CYEcvNeagybfFqjcTynrYhBjW3DgtaG79UBbAtqFbrw2dlDbkE2t/Hhf2iw0XbZcBrpfHTkQ
+3j00ourtqEO3ceFF8T4LUrDosPthdkzQjNQGaBK7Nb3+XMXQKhiPMf8enU9GB21XigcuF4MliSbs
+Ox0nKGuLAoerYgSoMKFveIGGpTaeahrt+hz0NQH0FOnyTmR41Oraaog/9MfHl5swBXXKrgtkJC7t
+w1VxPzQGM/2IycY36V6iuZx9apTIsOuMMPL8EjBqOA19VhDRXvKjsDYatBwvAg9MDFF6L6DMBNox
+fXi+QAZjxQs6FCKdhM5GZzR9a1WwmntMsuLOq6EcCVB1hQ976maCeQTrOKZxae0lOakeKEmChJ+E
+a+PlCcgvFeVEMxap3MERfnm1UOfy1yUJ4nErYMg3PkZ/65oSwy2lwX5Tlz0pP0JGWUbPi03X8FAI
+6TOGzGYcq5hm5nryfyvqs//NvNe2wEW2Fgfe93ssbLOtl0X5cyKnziJ/KtGZ87A41EQrNtZ1mSsM
+8FwkDW1Yl/4kbb5+9jYZcTJAv7u25jYRDQ0aA00vOpDVlnk2AtOwZqm0hmtnMyYnM6Ehq2fKsG7M
+O5I3sOHsKtLnwVpGeTvWkoiiHCKGEv0nh5T3Smot479MgOBFh3hNcNhNrDNoOL1K6guiU0ifYJv8
+/myBALMAR4B7GQzllohmlXl59+DHrvzmcOk+mOQOPza8UmYHgXF3IdbDu1lZpVEjkEy3yYmNyoIl
+CZuf6+qVoHDvlnBYivnKA2HrIPBk6qaRyQciCLCxxaROJxw3yw5OhdZv8nYYhu4FQic/y7lGLPVg
++ZhLcuq2ki025++BP1m9t6GLhkQ7Mj4CfyrKHMJd8a3lFITsrp+Q7K+1DkFGd67flO+l4fHq2dbz
+sJsbL3oHZxRdrhlO3sKVrtIW1J7JImEr5uDP/MRObKAM/2QFHRHPn+c/umNHdmhaypziNVNYZTMn
+pHm7Ms/fT/FCV5N47P34C5KOqSVbeTcQjU1P4eNiEpIxmxNvywyldfdxzKg0ehQMjQrgjxsezNkA
+5XHi1ej19pDXAx6IOMEth8qVFi+6zfd3xjIeTtja7X+1j2BH3Il5meS7sYdU1l18UI2vHC9bAgmo
+6rNDKywdnoYOcEqVvSvQgN+6RMTUpmowy2o86GtrGodbQ/hl8B8BART5EVy80OlehZFlCd2rj1dz
+TpsNmLkw5bL6coA1+TG1s+0h4wZj/42scSMK9BMmD2b22uqkP/vvXmaD8jcu5G17FzOljMlZfELt
+DEMuVSOWSXMgoV+BfgqEWjSNQlOw1zJfl+SPBk/hLPCXRtQ7X8MX9KjHewTWK6mpmJpA638shm2k
+tlRb//76gsFafnHlDImnIcWqMXTgaMGJBTpmICuB7fZ67ruD2Tvxq7iS5ZZtI3Gcc7ZKzIIMRI3u
+JhIPntJxKyJwRgTv4b1KCfluuELfrtTbI4rpaN2Go1AA2KSixf6PrZRyuPr0PW3MKSBr6C0O9NyZ
+3kSONNkswiPiqmYCNxUT9VYi6HVF6/VzyeFtj9XeDzoBRph4L+hL2BlT8VBQW+B6TJNvOXjOhHcc
+EbUnM+MIO883efbS7r0Xijn50H1+bCykRjbDWKWuGm9/ERZsP7m8bP4kVZkjsIlZXgLSgo+A2XCO
+/P/5ghFZesqXuYDK30gv5J2lJ7kf/KY3MfGHbIHRP1lyRg0TyKJkfkGz6xc3/fbTmmabj4e1ZH+B
+BGzXAvRsG311wiHQWhh69wKbfnzAAQtp0sIQPqLy/4CFaWBDchGdMxMkDJxX9qmhGMqdBqFmUIwz
+4duVJh8E5D0p7fUD0Vref5C43Ay1brrtr4CBpJBFXga0JPHHtbfNiocNbkRotAO/6wADDXFIJIcw
+qts2cNTssZMchbAcqCOnWfw56+NcxMzf1S/iCraPGRyjp0hLWy91miCAlWPBguSZOMBRxcKXwG4J
+ujxnMRDqTXGct4m5bwTGIcN31Q+RFdqrT+zPenNtfLb5VFcI52oZJAuGXcaE8oNt3hK3W39ba2A+
+8kp9PpxoP1olq5ZXh+5Pg4hPsF/krsE7J+G8OxtdahTZd/OleXWOwiQ1LqLZxwpFMMHRxLH2Ya8m
+97qG3wNaM10pf1oFlCBECbqu3hqv24/XkJE3pVwtMUs0FZNiEx8LSF8BvrQKc2MKgTZojx0tZZGC
+7CbuAdMl2JQic1KOHKng8JPa0o2n//knBO9fJbkcsP9VUfLYNKoa+MvrpNydg4fCxqa3XYBchOLA
+Jg6KKADKK63Cfl9V2dFyiK5AsxwboDegVF2mpwDsQSdRTygR47z2ZI5KdYo6Tkcm7DCVAIADj5Qw
+KrCI4VMVRtNcUZkvWLPbyMNZB0TsmzJEJuM6PUXd5yZ+DcJGiTbO99s3lmkdzmMG0wc2AjhDd37l
+UE+WcInmfmypjQiCuhey+RcIqOM1Km/ixevMzEYICAmfGU1QGs3e7wDnz9Gc92I1M8rgHKAzimqe
+oaMCChKDTcv9OlPhsxQxlozovcZyvr4jzz7xTX0h4oqFRLxargFBLADoizi3Xbe7G92olJ7mUqJL
+VgEoDsP21XYfUSy37LotnHRJwc4Utk/9ndBXfG3i5f8I5gGwFw2HmAZ7e349bNk/5peF4BnK90kC
+AdIBJCKC3ktofe8wUwFu52WeRCvmUhp7rdLj0zpFHPqXwnUwNdS52K4RAXnpG7WV4kq3oN3kJ+bQ
+p8zEx3cXD3a5oQpnP7lqvP0eYocJcJz05GAeDG4Cey5c4XBuMyrULb/0RiD7MWQbsNTeL+Soy/N9
+ri9QcIF5gZWLTCM93otAxHxQINHKjvKpawNMkcigiWM27DTYKgE76husvCn53Z5B27uvgLmTtFk7
++zGGOOEiWyxRVd8btLvqqkPjQCXTP4LR5hP3BssbAtsCXQVP3CctYqZJ2dwSyjIS/Y9eudv0VgLS
+QoWk2USmlF4blFLhwJooF/knVyHRidTa2TNgOkTfY0IGgWoQKiuKf+m1Xfyu2Jt9JXV4RhIdKQG8
+vzcHDY3LJo/kgnY5KWuA3ZdDik005WxHHfxVSjOJkzfy1ZJOQ1hxUhZoWGiW8V/GpT4NMHftA8HD
+3sYuPWL8hvz2k15Dhu8h49JnaP627xQ+TSVaK6QnSDgDevI+wz3aUJ14ZGjrrYtH06Q0odu7DYAh
+n7szhrAqX6WP4p2kA5iklAVK/zaZgRD8rgi3uoRMn2bakgYBtfL7TLREmEOAw4qUeFsL9Y+bo8ps
+cay+jKGHPKUAXEK2TlRe3Bm0kaOW054jyvG8mNyduiwZht0ZP/M2rVz6v9aQ0Hh2OqErzNGEGzVz
+ZpeWijlopWrT79sJAOq8zLqlhQVtQNHTRNhnx0AZM5q0caGRe58HhAGGetL4YbkWqlUiyCGLL6s7
+64vggWTbUMXFfcufCwfEYZU5KwYabKRTrw3meJGncK7U/9YV+BELhQ/rnyBMD+y1/F/I0ZYHb4jf
+nn00MrYYgrcHETYJR27occpkz/DlQQZDoIYxlouAQ8qixm8XzfybqsWoKzsKHhf6S03ScWGroroP
+VHULJ56wdg8W3H7QgtO4nz6N7SqJOCkdfP+E94YuhM6kyhpleRfbtJMtpAzCm3IQGy7jUAG+eZwt
+gxOW+unEwvsOGDjb9PRfkby7+0il8VXzCzM9ZP1Tr+FOykbTJetOZSwg1XJn6XcEpG+FYtNvmEFi
+QETu9rGa3Pa/oONxEN0NXz2ymJ0z2LqVPp8IxoEvoQslXulmR/3nXMO2LvdiUlC1tUTMTvHGh69b
+wQiXj6moSsygGXGveX/ci5tQiKXfkSdjCdtNNLzfTKxmQv8aGCSnvRlaOXFPTew1zbr3MN4+8GqV
+xX+hx+L9dQUWL9VmmWj38wjvP1FMZlseIUlzgosBDmTd6sKs7UqyFq3ZCRnekVSMoEvYy3bhGo9T
+3pvpOPSlRxMjee6qx9KjwYwEEGx5UY13nyhnDnSbmC/8a2JVgWgEijvziT4/0tuIeEnV5CPJwIIi
+zEbYfjchSJOdBU8Qoo9E1OXGiK7qUa1fZva2jdBQKDCTlW9VDcRmCgRTliJgRZ4jNDByI+tnLNia
+IUkhue7Ws130BoG1Q+ehUL9FU2PleptT7mteV/JbKTIj+edEv+/8Vo/OHvzkd6pqQTvu6nHv3km0
+kSdbQVL22L6ukCva6tga6pPI05G/butoCU7lPhezcc9D2A7BqI1cSRiwWVcqWY1JEpvRFiStbV8E
+Kg0qqKqGBs+/BuZNsNb98u4CpJoRTWVnq2oTEf4+j202k7i1FbATKs4bVMQN0n5NfpDhSl4zOvEh
+WW1GqcNJrCyWu24SRW3aQtyXwW6GZkig8rHA9fh2yOfR600F8lecrJShZyq9fwzebOF0y6DTXyCA
+XQnqzbdjfNmzCzsVsiwgTfKggH1GioloMCx2Da2eQMBAdAm5KrZfJNeadmXadRHiS24e9wwmhns4
+7i+81lLmzad5YjR6MGMtwkOVdp9lbGzfahImzqZWeF9eGz0TWII/n+S9+jpqVXqbeI9YPmP670EJ
+aBxh2lzWuIw+pAP5gw+3eXv/SY0vktp2L8gnE8mmgVhcbS/sGnBHyNVEy+paankrxhlf1AKxb0WB
+CxgdNJsUCL0KRD8IBwORC67b0mQod4MFaWlkijUAWCttS3swEf7I/afFkscb8dGRBzwB2baYHfsf
+TYSYxzjgXgUXLILEPzvdnlgmuE45iqm3bjYq7BGVxgJDKNyD6+94DMya6vF39HVTaKZE0UxLa1kp
+1Y6zpV3vIb2JvdMiDjZaU9pEowCqsM+OSQFS3/fHu9x6SbPg53VVbBhlKceGe2estK0OU8758zqv
+i8ePcaAy9OXf46MjqPoCziqAKtgcicS6qxFAZNItP14WaDA1wdAWwmNQaw52zuf7RpS5ELvcpZbg
+k2UBbvFX+B+hFQ30B8LIyuzpQ2CPc1yH6Yi9+ckVH7l1bpvNj6OjX5XnCHawv3KU+oIBaFI6zSYy
+HvVtSatef5xKdmX85ipLTCFuotWoGVeoRloMR+JmQczTRdk8JlrZaWJeBTRu50bKa5WlLEU4W1p1
+fLe+KFBItgJWjb24wR4MUQdOaHDXNXKWUe63enYpGBvy5sRsW9Mey53QpJVQRErUQtW9DKgNGbvy
+uzuCZWIgrLJ++jz/dnpmoyVqt8mYb+0vAyWTzB2bmgN+x49Lb3rdH50gxnJFiIgW7tQOfePopoM8
+oQfzwoXMznUFF9gq4LBRCLmOeXfV3byn823Z1A5zZo+fqxXyEO13ftbVe8UdL2pG4OiMeGiKHuoq
+oHcHBfleFKYCfl0Kgu81yyr23NNobCMKvwy2E4nJO0Qnuk3ue5Z3rMKAlHSjqinho8McbBFaTQXP
+guuZJoOQR2xpcojE8lU5jg43XpVoKAKPkyFA5gdVUrKFt3UBNaOoIDyOlgA316lFofAJWNuN9rvd
+S8QE5MdwL67DeqBQBf5EMjapnvaprV+xvyEK/iP+1acvz5SDvNNUybShC1YNMvwETV/uEg6fu5Vh
+FeKC4xrPZxzUxjQ8VwnxdRFbHBQ7Gioiss517oxI8Ic7K4VAOka20etPXayByeFkYjyWbf+eONUb
+GhsZq/s5cgx4hlKQ6/Ijx/QjvNZ3fedZHwGaxTx/G6pJglOAI36OaqHlv0nwzNtCeWjtbQGeuJrG
+XG16fCZc4KFwictWRkj93aCOtNSDvEIGtwehM39C4eg7vST4PxRLW5aNpuGPNHBDKZIZemwci2Ig
+0AWrMf9I8TsLiIQJEBCajjpK19eG/o7Xp4ba01x1gzudk28uIwLK2vzqGk+pSZe9/TbLJqSr1oDf
+1FJ+Z648nKIN+lUQyKvW0M/Te7vsKICtIhH2vHogtl3n2SFPkkLtq0yaSNC6JpYzSFNuWjQDI+FI
+xVq/cLv0rgAEv+VQp63CwiSzFktDveAARdMetwWR9l4LnAg+qbQPzYOMEaIIvmBdMf0n2PKB6WQW
+PBbURCwfseRTklv6z9l1Qm2rg23knsbuHT3Jq/BY/MObQN3Qg1fxl0vER3TFH4RQd7E+zWfXIbRu
+cCN67VBKJ/EI8p+qIAmMXk0/hmXSnw0IA7DruW2Aw06VWnMm7IwF2cSfqGERPxab5P1EzCBco4uj
+X48v5AZwkoBSKO9vtQaiWaAA85a2gJ7CJefCzvqJTlQ6YSg8E6WXlvqzAQFwBlVeKxaOTvr6CC4O
+DQ1ElI22nwFQfM/pNxQ0jzU5IVoOPcu2fg85PX9jmc28r/i/toXuTN4GsEXZ4frJz+fE+/3iD9Ia
+9rLFMXsGDq2yvDD+FLIRmoLs//WMtqpyo5JYuAbYu4uq1RvArGY3gkyq9OatP7Dx93Wuox02Kjne
+svhUC1oCaD3a3vYCGi0A39/JyIU5xISS7XJ86DXcY3UFPxFQBRAVncCprvOqYKbQm+cJ7WfQntm6
+DyJfUCUrs+lqiHe6M7QsLdYCm8Bo5QQAvdZmfTfotAUQ0C4TNUPbZeyggb8N2MiMg9JMrKMtTfeu
+nR+HBpTPe6ndh2kfj9eiocG+7h3Pnvf8p7tly9AeWGVY1aY+PHurEI8S/CxUk/HlNJjvtGY0x+Bn
+fAsVrx8y2aLckH6YfLl+v91e649s0GrGY2K322o9S+j7fAolb/FUv1oEk2YM5Dwxy/7QIk0FHJ/2
+wNnsxdTSVtIUPf53UEXpegUWIPNn3/2FtIf5TpA0OFYHDw0wDqBsn/k7JhX2fBpkO6udSoN3xtwZ
+0fspV1Q/ZnzLKVHSDmJIFVqgymKW8EZ35D1GTmGFR9nCeBm86/FulOjFd+sLkqalJnlHUPs02D+n
+n1MbmEDD7ObRUr+sxnk7DgM87TF13wFRzJ6/YD3Svg/xvXtLP9J2v3OBUsfHmXdF08Ek3e8/a3LI
+n3qEe+mOOVIspppRIRC9SoFJtbGrRXEUY20bdYYW2+sgkxODumqtThw6epkl1hKaiDgJ7QlGJYdU
+ujx81/AZGUHaxNKEj3bjURn98q+VKUWtpeSqC0n5oeUiqEvyB5qG9A/9BLiy1NJYgluigIiO7nBi
+cQZdWK3u0qzwpvfq7BEDhOAL/PomRI6YIB9TGLhmxx/gTSU772x5wPUtjJouCNi2MrvnKWiwKWqZ
+4fSwsE8+/ScnGM5pIgEqQ7Z7TluC5IMBlTvIx2kHI5daa3qz0CukdIYXSfxxinGGtnITglrM6T1y
+wvAIt9pLEOwrF3ZgbxE7K2e3T+72x30wx+ANDCvX4fPf/hrZ8yBr7KnO8jgI8lL/L5u4U2fY9eOs
+tLAbD6qi9zmJ0MWbn8ORjG12cQVFLAzWluSdh3Ck8m+Zie9pNATT4As9X9HcwyAvhSLoRuso7g05
+4xf5Jr83c001bTxZKv5e/XFquGQjxyQGKtIF/90SUH6c6FVRbCJWCzfi4I3zEWYWUJsAnt8XHtt+
+bUX2GcLjFgtXx7f0OjJAoaUv6010JOv7OwvANFteUUxDpVGVg7q2OWNvtnjYEVUZbehIb3qCo/U6
+nWNp6pTXylDhaT0buktF1MolKK1xF+i/KH0Z5cz6zyr1V+lLZHavK1q2bJ4PTFwvDPepav/86TTQ
+2iipN4UAz6hh/Kxx0PaoWx6IJ3UD/S7xK5XIE5c7yzh3UucGF9ce0slKHi4fZbLS1dot4ridvrq6
+ELuTlih3JjYLEFu+37Hnwe14Km87Wc0BodejH4GcJCAbtvS1mfNeNrPL58VI/UXUEMKuTUqr01bB
+aDAJk90QZdIeEAzDmVgRcx8tbuPocI70XAs0YdkUXMweYgI5WHN88eNPN8CH4SV/1QiEI1oWA3Tf
+P8c/pxEzAPvJXSxW11/bu0p/CRyOWDQQFh8ZDeK3ppezWwrjbIkS+qpmn+Qw7inQlw+xak63/Xnc
+L6e7YQifo3dMRmigFVr764Fbire5iO4/BDT6ewn6urJ2qjjSafsiKnOTfUrarZbhmxVaB2hCUJ40
+z7WL1CxnKBBYbRFURuSnb6Jc94FazYyPSdDxrOEEuioYXRMdT6mTqoHjQZd/m5eUsaTVKUQixFnY
+VxaYkFJ9VlgNKgrf72cyGzqDnxdhPJnqhSnMF5R0D/VNGMOFQaXsxsrXHJClVVTssdwsFkp3odhh
+4bzyNnQr/ywJsu/P7EBc3D9xsaj4SWJRZCRhMXnLj9WiJ1ZAPrmXnWlZ82VEnqrsC1sSutGNOeIi
+uKJhRaBwTcugYKiex6r6/1nv3jenkNenqa4BYabS4vFFFWIrmnvUOhNd7fH8noKAJwhBLsIxApeg
+bo8Ns65B+m9toyk1uvshrrH/tI1r4Go85Gbc9WQdhBoCVhZ31mJnqvcvfgtaOKoS5iHfVtKGulrg
+asfvKTsm+VSe2NtuiHlb2eFtOYpVnyQHoedoLxeVYd6ON/J+SRM65W03RMP5pi7TqVc+20qY9oPf
+iPl4XQsgXlJlKgM/wOS4PrXE8Jra3Z2EQrrhFCuKguRfPIlc+oRgZvECE25UtPe/ps3RyZHlcsiD
+vsRZ4p0kJQqfei/X6aFf5JInJGBpgYs9Wq5J1A8vOSuuVo9QYGbqAOJqUpnrtI2nQRE858O/07B8
+SP6//jdhcFONU/iENU3G72m2+Iq/JxrUCNxMPXYbGEpQiuVfT1yAWQgYWnWYyqqbPtz4+sEiptpx
+HTLiimtddDgGIBab8n8oWawPg5k6tFFSlf4gOMVsIBvCYN1MtpVs1hobWsAbmmYw3RBTgTG9CbUc
+1HMOd2iCCPcLjd+eJ0V8SFfRC2jpWaPFpG29IpHpvyFIHaZ39qFbZAAx+iZej6pmWVxEZUE9scFA
+/H3wggYoaYUo7yvC9uJ0D/g+H3cBA1ViZTJue4TvZqJQzPXqa56ZNdUcOW3KptxjP+ivmUK+lTKJ
++POx/58c84tMDGpsnHcIWOf0mefkc1JWO2MpklDIlvp4RUMcxyCgIosN34vHfzSmy+EjBnWWl9AE
+4gsQepD0Hh2qAL4NhVNPIdgPZvSoW86d3ACav6G4uTc2X40WzYqzZvv0uXY/rHC5ncQSHIAiylLv
+AoDReXQ/E21NAFtN9NZvMutw5sVFytRKT9jFwgI5brsKBmQxcRGZn49niY9pLoVW1sgMV4s3iYB1
+w6rcXA6lVxz/rgnYVc0r5Xf308gJB8G5vDb6Fsbg2IAaeqMcmAGtecce/Vl8DvEL2OfGkiFG6qFD
+YdGxl8PgQesHak2Z1N24zXkP3X9/TGdVR3CZrn5t0q7tjDPQ2FVQU0uAV558boiJLPhjJAolND0Y
+TM1E65cC3PAMP+9MjCTaUX6s5/C47f1w/QlD3WPhfNLPmPnuYNGco/0Bq2mHG15hrRv2qvd2wHhc
+aJGPjLFareXLdd14y8gyLijYAepRGRivpVpDh6k3YVpfupaSbV1Ld37ZmRe1CWHvyqqUxR471Xtu
+EeBgaU9fcyqyuh+07a5yYLS9bL4TWJZf8aucWwUgxRyVXo9w3F6oBW8R0GNEztBphRtFnNvLyBGB
+x2BE6C6dMtM4kEtVFG5+xDzXgM0SdIpxSW9tVhLlryZQGdJe34w7ACPOZXGhjhrj8M8Cbb0wHWpV
+n2bCp/95RrQJimpgaIWK+s/rSASlQbj+8p51qNfX2/k10QxRO6lV5+Syfave/YLpEW8ERRlY79xz
+3D5jgr5w+5lGv7t1TcuNgJVvt9u+JxaMIeas9KD359c+mq8Telsdx2HrRpNSpL8J30BASNccel5K
+gy4TAQA1WrvefWgEN5AjENaJqwd6mx+d+op6inH/fgldHhYfs0FGSwHggt0D7yuA3PvPs9kY038a
+p+Mq9Dg5Qnqs4Be8SZtvAS+3Em/V/Aug3Z3wtmGtVwlnAtFZq31b7GXp+N4Re2za2ymAAIRpVySx
+l8A5mePEYr2n6lNXvnXathoXvVBDLjSWmGDeFyIXYLb4nRS5WQV2glkfmaSrV+l4F3qp7Buf7ize
+QFtN/8kWdPtpMwXu3HKzCnlFhcjkGangdl1rhRFIALsHy1/txpYntItk6Zcb8ak42p+Ma1SSuy/g
+pZvasqMbHBuuGjBlQzYYgu50zTRYQpt2o02PZ11ksK8j2wJGirbilAftXloHc+fSEwALmomEznlW
+dtAsT0+0o3FWGaCNmzCD6XlXqclZRq+i3KIc1nRRXaeVeA2DGiAEm469AZ20HtA823a3kVptzAom
+katb0292fYtTeiEv+ZrCUajjAB1qzot+JMsJrSHTw5tqHSbFG31TXpiGR1uAI4d+j2C44I5bRNMl
+IrghC9gPZPUTYDg/Rr8rqRCsSLqjqPZTfcfgJRuBPAVqtJY2plTeus5piApF9c9gXUpZav7WtN4M
+G2QKiWi0vIGQA+UoIfLsKc1wntBnbfW98O0rxW2XmkOLwmhhIOn/+Wg1iJRqbSUq9IMeAghKXrMv
+xmepJrZbMIfucRHcbyu6cU63MRn+wX0SCCcN6GVEDm1eIPcOb1UOKb0d26RKDpRX94U+ZfswAznc
+F5UJiJY0B8sImLWnd+meEvczjGE4gFRLne1hBKRfKoAo5YQSSBtZZOhRqu5X/Ywxmrz63bctFfm4
+5YnJ43xjW5e3ON6iM23XJtI0Et4TiAEXQdXzRzb/kI2jU8CUuhbiQBmV6QJsc0Lk03o2WYHvMq1S
+oWXYqzfo5uYRLI3fQWXnHBX3qbxyPLunnA9N1NcdacltWfADUHoub9qfUr3sfA5Dx/tvLOMiNO3i
+jOMhLmXAX5SGzJA0sCVbfuLVOEnwJvTVVUHUL13n0ZaZs4LjQs1q2lBJ/2VxWONqcB2uU1ncdDwv
+7lkz8CLIJJHdO15dIWEIZM/SoYOM+0gbO2jBjVoYpRGDt3PpuvbPs0wQAh7a86yVHnxjbnOm9BZl
+ujk+UcEDhwOdPbXh0qfyUlWltx6SY0NXN3mqUNv9KJyVTGB0LCeCRK13RmAxlVjl4PTbl0F3GLLY
+rRa2UglcUkS5THvQ3HZOFYj0jvs/U1Bf0Q5p8Oi6mNO3b7fmPsj7glBqD9H3fXa/LjnB6ENUIATC
+xKXN+5WaTumbn1gTlimN6UZ+m8Z+097t+qK+itO4J3GnZJ99+ClmbjK6uHIlhm8WuJOlj9W4ksiz
+tyeNT0OSRctz5sUWTAnBm4V56KRHUigXOoWkZrT21MylnwQazBSTzP/sCc6f0Yd/fNrDw6/nqY1F
+vb+fVGYiF+o9jD3jtQRG+8Vd12ablYvfn9ig6rWXAIHa0rxnhDkVfB6r3YmYv6iOzNirL2DocBs4
+4S6rHD7gj9S7m99I5l1XH96Qd79bBy5F3snoQK9HdR7n4U8PhD7uxuGyHi0v7rJv5ix5VouFdchf
+O+iVjtTsWLkEewZZRtBKrSFuGhmQfKlEwL30NvNPc4dEmpOZM6w74/LPeTuBDkrM+8e4LmE57SRR
+IynNwCB9jWrZrqR2+mgOnALj84BuDovc3aJXi+dgeOIDc9twtUSV10fQS0eCJ9cf7Z9DMr3dZJPr
+AWZgEuVo4c+XWEAUWJQZkvCVS+7BnpGwUrScI+6PJn0R92vWDqMheP0/BCI2y7J6xILgVRQjbuiX
+zjG16aMmjy/P4FR8bV3f/VZHyvntaUd+zLrVo628il1iC2n2K3GGspwztbOivqnorse3AOiINXwl
+HlQ/+wmywfnIcdIJUqXyATBOG2OuJQ01jMyn6e9SHcgp36TUf4Le6ZNmHohdoaGN1hTZdkTIdCG7
+6PcvJnFrNfza6C1SuznqhT3BBWWO3xkzMAr7ohH8D1Fnyl9AvFywThVouAZ6/aOVrNf5ATgWcb7M
+PLVFOtXI/Y8xBdNuqIIfpgprc4XEf8matiTYFFArgXBP6Ex6/0+GcSLq4YioQTvvZamIOgg+/NBV
+iDbOjP+iP7yd67W9kitYoNYvf6HnmCRjvv60w60e/Wl8UZk69vHs5KwWjYsJX9SGN3suFM2boM3r
+mI5NRhBwIc+twUDOC26gERovnxhV3m01aTjbBzQiTeosivEQlsatbQXhMM48mKNZnRlKdJo0SaFp
+udw6D3BB2qxQXT1n+hMrqE4itGVuzG1Vrt/u0CM2/4rdXxZdB1cDIJHsi5bNLlzvIXzmlnOHgoFS
+9uwYpaI436+4yG2VMsqVg56CsXuqY/bgzHit+f5KjxI6wTMwO9Nhc4X5Ef249Zc7q3RkLrIkn4Mu
+h8wBgdYcKkHmeG02ISSWVQL8VdHj9QT24agmtdALVJBe7imstudY5LcPzA/52fzSE3U1GB+Ama3J
+/5f0ZZpEgL6iC90G+ZkLOD3sNYA4taIyw3gveCXMyx7WKJ/6rZSR5v9YNHTpgSsZGTsfJJHkTjxP
+PSgGKBhwguZWpEvexxFGnVMhVIfGYt73PmHWNbY3TmvEz8KyPeOgYmouD3y3os7cxep/Y4eqGswl
+AKlO9SvXzMyVLHKVBaN7lfNu9J1TqQYEBfq2cV+rXlm/DB1F+Oo3hRMZ3MOZTmSkyF1DkMT96C+B
+OYWw0nO7683oI2kCd5bVJNaVHKhJpsu7q98kXLNpKD/RtI25jYJ7a0qYJNxcn5CbQ03OUoQSPWyt
+kKH3jKSVra6mwB1kwSX9YscwxVKZQI91UIttKyElt0SixXwkJnJExP6aVku8mO+YGfRiD1y1yWLC
+3+x6BNs5lOk3vEOn/DApwF5rwBjFaLbhVIuHBZKiwZPvrNMf33FA+t0qRKuK58Su6f175s9OSSKj
+kMHBeA34pGDZ+CmG7KDIAzmt6/QQRehQciGuWwu6ZytSeWl6pB1OxhSEI7FbW0WjI3MLFpqtca4o
+h4GeoSo7NbE1IMajiceKn4Nq6wCgrNHcAi+ZuJFFrdx41kIypPu8L3IRCCZu6YxSxF8kggOHPhdN
+qszomd2ML6scgle87uwudfjnu3AxXlUDPdRdhhyoWusqBfokiaDMuBlvvODhsnWIXsneQxL7FbO7
+AgvjkDcuxGSIMpG1Ox9AY/0tQSEaVJk44YsaVm64QtfacqF4n3fXvu94+R5GgckSn2Rnkmv347F9
+utizQSbnzeH/H19tUYa2LFZ4hewIFvzgo3cG0yz4avhQyYeK3D5vPxWO83XCpXsiTVSsbiRO3o5/
+r0UZAuBq0gb1hsCNH/1zhCOkVAbWka7hsxzIP7ruVeo8a/ZqTeLgjKCZL2g3xfR0MyAm4nRjHd+d
+SbfxPlvWZolDSnO8ZPzTvTUqBHL+ZJC6Uw7KJV6C3dAYe5se7051DFODB+XHuO/iZgl/yJ2S6/ef
+QA07LOWDcJ3ZfU5FYMlsJmhKPXF0oeJ5hH5bKRMG9lSX5PHZniSinFYXF2PZY1H1U18t6I7gyJwe
+A9UMQz2NS1aKjDDGEFpwdo4ecGnEBTRwUDQQb8/EUF/o2oZJdX41KvEMP8Orim7ja4tuzgkIe0jE
+ErxSHgGpq/TnyqdolxjZEa3v1AWXB7OCKU2Vbf0N/Rofu2MutLCT4iJpgO3KSk7piaO3a9EsK73S
+t1zllzMc3XIDYjT7gEoMgt0brdncILHdaiuljc7C5tr+Tbc7aPMrskoquzEU5TXGLMxD20sFMVql
+stHU92L6YkhDLm722wjSFsng9NDV12Q9hz5LoId1B3QGNEbLHbvf2JzqUQmCvSa15BDsgU1PMTtg
+feXSyfvCYifW3SWpVe7PRNQ34bI21485YM3/gDcNBuw9TsG7gR20+gxIoWsI+SjxPX1QvrGmXY7S
+paXOAMeXDDMATbgbOsAEQ+vLIsfrF3SfKEq12I1iXw2PDtF+YVZRJxEPl+sqTMj2ul/GCq4rTcBR
+WlWCXnTuR91dcoLo+UAw9I40MgRatUJOJ2NANVmt7KvukkkWM5TyPqI00IoKUaePOdT8eqK7sJC7
+qurfq/s0OrQIjt99ZswgEaR99ChmhtP80bqOvELy8L/en3QCMCM5g3MNghBzblwXqqmX1oeJGQzc
+quhKSmc7GjotPzpcLJqlwqpEeHps2JOWoLhkZV7QbdckR9IV8wtSGzGiHKuVL3Gkve8RGknlOPJW
+oIFl34A+DjORBiSCm2if5I5EfBpdm7/Q5oWq66isykTDruBYzcgK3rQIMMVzP1RqtYth0wK6f5lm
+P0DFEqETLAQ8YZ5RcEHvrEcTLrmxkpH0CRyD2WmcKla+SpO8IXbFeDi92ryRKHo0K+Wi7bQo36n2
+Atkr6c8Kx2Bz5s+f4WAlvLzGgfN1Kefm4LGb2ErBk45FIXpa0vJPeJF1nwp30PAPpunMU+Mx/bDa
+GGWLIvrT4aezUG3dLMvjEor67iDB6bhM8cKA4pQJyvxK8EXZDezcebnJgK9LIuqTwjJId/kaAXT6
+s4HVWZqhflmmRXtKshDdyvyfd3MCPCr+zj1Vx7NQ2mg4dvgF8Vb151MkvsH50Ds3AVtynwK+zYHo
+fxRjkxvwQc2KFq2lhP1Fkhxgsik+uB2Lnd9rwySR0sZRreQCRrmglRM+y31rC/OnMYYSueQE+IwO
+EP7NZfq5Vk4GsVo+38ypx1IeU/YwyX3aYJX2vQkXrjkA/bjd7PFOU1vE70+2SSRE9CexZH6+lXvV
+pIVu1FECK9fsHGOn8YAHk9iboysr9SXPAMSCozRO1LiDGI2GQ2KtsAgh23IVnpNDSeP8yHHMckt+
+e6qVaSqzadpzqVS4BcWPDEw/YMPVfi/Pk1qxBAkf4AWYnV0JZYt6eExg199lDnu7fVAzSkS6XpEM
+OrGfahCNP5pNIBpc6Aqm8czythmadkWFCbX/b+rUV/HyqlZyoD7b7WuYQvii0TN5sXmSs1M9BstY
+C9BjfX64oZ4rqCXDl5G+uL0+YNcui++Y4CbdT3+84wCq7rU//NQSjtkHg2iZ1oP17nfIgA9NkU6X
+5tHfaHs+wj5+JFqapl+m/qfOHHVsynacRolpnrgaYNG6X4r161WRLs1e5Km2j9bGU0gUjsbpxahY
+Hlbp+QZuMfEw8Z2xSohfdeNcRbdmq27w/Nugx+6PQPhyy0/HFJxkirNwZbpcExPPScoZK8id6rAB
+SA693LcSH0Bwal+qMrEhwFqX8Xx09JJeJyTj6ciK8CHjf0d84K5C22eEW9r0yn1konzP6R2apYZg
+v54P/2B/2VsW33dULGSl96cOTBwHxzZTgXSvvap8ojRcn8md+nbBx2E3GcZJ/QYEFo9UtWborK1b
+okEC3pKNbvs3L6Etqap2XGbGYmjfCGPtKGm4hEcE1w1/E5aJtSmC9UHWHl6mCFzWzHA4euInowZK
+XBG0X7PgktY5ZSoDbeFIVmPAH0ZhMr3LBYndLsl02d5Bv9jlRE74fVEnBDdHygPXw1wm6ts3pBIW
+reNZkf3nqFwdsv603IJn03b3n30FTTiDfhoCLW3WdBPVIAnHlqEP/+xV5ocIl1h7lz+osRwR335z
+SrqmdalpVNbfJLmjn2tKGPbreEGAOKdWCpI2bIIAcxyOiZE1xO/eqEvs+1oXbG/h+xr3CA3wz1Xi
+5UVT1oONmpB/6HyGnWQHmcnm7hesm4uT3uhuzwbObq6i8xS/kGY/7J8NCGloDK0n2NkdvOJaigLS
+KUdME9Lc76dBfgRNJR/nV3yVTqrZt2XJNKAUxrqH1bTKSlV5TCQ9+WZP+xuV/9jjC4XwU5WdjFsD
+MX91Te0A0EkMwv9v7pygoQO1uSzK+mPX1Q2pnMH2DpwEonM2yBPrHVdcgtuQxjrsRGlf8UwHLd6F
+DXUGASP2/dCkW+b2jAC88RBmyzKhblbFXcOVONmM6F8E+e1Cr4SvVjYzp9CpVg9Je/5R1nh0Yyqi
+svsuzbMxwr7Q8bFKAcMHIflkSbDHGUOxD0NxHLDCb2FCIeuoa1lsh1YETHDrXl2yi6FOHLshRyh1
+jJc5esgWgrHjLqXobS94BhIY/cdh9YBZDrJgTkF2f8vDGiuqompzw+r5pZZp1//xjdwJ/gRrPiOh
+JMEsxOYIyhNSFVVULSBLixJt1fXCjXLcF3QQolf5KRz2Nnu/Z54cD1xTWAkPyRozUAz2KjxXG3Mw
+x5Zwg61XPDkfTCk/E4vjjDBfn7pqv2prNocDMQ16yWf7mRlRO0GNLvBtplDJjAmyZIKz9qRp8y+7
+I6R64hDgyM+Y7skiOtBd2gQVCQYarTdyoX0aBHNxyMNz86ubgTmZX8EB4g6PjudF4JaaCPtRg26L
+HR9DYHZI0wCTv2pzuPoc0nFys7PGrwnlgny6f2fhIGcRZzhyYaOsqNqELOF3kRe2vdh2+kxxdFnn
+eY5FWTHIlRVZTeHL20jFWfuSW3K5aSU2pqW+ZXbDVYs540RKYsNFO+UXiwokbJ2XRbSvvj/jfqac
+MAFSmKwb6Q0UUFxXsm4a4ceLlqKKIUs6LRnvMAEetcxP50pLORkISCAVy0jcrusCmNr+O2RjoXyK
+vypQjRLhujmsvcInmRmS0W6YMUZXHc6+35yAsykLm68WHZ3VVWPvbZfXoX4QLUdriYLTCbBf2up4
+Vf01hFKPzYasq1MSaYPdzhOp1jLh/QQeMWh3d9VrGr3Xom2xwAf8AvI+la8CE87Zv7fLAgGFnERW
+5SQLLwkZlQhhg03Miggb/uNUnG513L08ngHYfcHKzaHfIllG9MLIvNKaZxR0nR+zYDK5HQ8nTYG4
+i55yl4ZRWYiuod1NaPG/JewEc9NFMPwI63k/CZAPumVSEABFDOObP2qbSXglyLuyEDTh/AYsXKCM
+eBk7R2xYS06XpiAAcYGqQtBBu7t804WFr/9zXZSu+koD/QYVo58E2jmWZqOd6zlvbhWFhrybYBIp
+KNzv8p2VgsNQwGGituOsxda+qUgbDuv7MFVy//E4p6+r5kkyO3FDarX+iXe+qy8juqFLxVv1sJue
+LaWoFS2f3vM9Byj0zcNE/Idi1EWJikubET6c7TREihkef80HXJQiF2AsY1UWn8qVaDHguINcjeKG
+U37CwHz4kOott0wLlp+cq65d3vwXGLDb6PUVlB5vnXT30CayQTxl/fbPK5+f7Q6MNXbY6vdKA2bP
+l9goNUgws1e8T2+f/DLiaK4wgP/e/ql9v8NWJku3tE8SUGIHYuUfj78uYr05QFoRovpMNfSzKG/m
+U/mmbQHXVI3AR2NRfuJX80JDu38vn5QQ6W1qo1R7lEFk66nZnywvIUqcWgUd71NGXmOdjTFP344j
+UDYkVOpqNfkwgIH7LKPSeBFO2pwZ3AnZ8OHNARRcRWG5yTykPdNwa7KcfkavlcfbNJcbQMd2ystI
+g1hhnLBs/9OXrH6+gFEdiJ4/VTJCrplfLRjk1NmlDDGo6nt3Mc6UI62RyVlunHwr4bBy/tJefrjm
+l7axO+zNovGLxgZaxYKp0rW1AmpG3j0zgsuXqFd/1P9X0MWYTFQ1a1XQQgd85dTy2PWmBoEuZLjx
+ONBKUPC4yzo6s5OGJ1Cxjn7Fzfa5fD3uawZGi2ZCZHX7TWbOg/Yl2VqpQe6mc740EBNAbXn6Ddj8
+5bHkDQQ1mPVd9kdTNSPIdrGw/T+f4Cpy1b+ZiakoUEd8eBQNi1chfUqoNio6qAf081Xzq9TOykcH
+SxzjKNdke0hshXMd9wIiW2FBYbSHN9H7FXg80HaoamqfBsh4KWaJ4Dt3YBbjAe1Lv9pCqG+aJZIm
+ie41J3ZrghX2C5+xj1hhtI7HenaXwaVQ4pTF4HU6SQGL+vlwH8+Q7igzSLEq/LUk9Qx+pGDCAoEt
+bmXSLDqVXLIcF5o5B4dxIj2yPa6NWjnxou8naMlRgaFLJtblXWpv3iCLjOMnMBvIWxFiHNXu+nOB
+Hb24AOcg5AwPUrAoqZLQAx1+FSWWJ5uasMoCmu4AXx+ZdqtPEZTjiGmAMAl96EF1K7xKAf2IY15v
+UiWiEirXMPIeoGCaCtMHYNUI61bsDLzUiLkFwhI5FLbQMhlZjobYKvln51WWHiDjgFyPUyRSWtAK
+OrQS1NP9AMXA8oYd3B5iI1Or9S1HeRRyMaTMgSh0QAQNgl1Ow26hyE2Afsu2Av7uQ25MxnuHI8iG
+SMWWCa/892aQuJkAe2eB3FkUlkP8ru0kBcKAXJGiCr7OflfeO55HjyPiAabdr61cL81q5z/KXDyQ
+j/YGcCTHFVBFpuFuzJ7ZGGg8Yrw/NpGZSRNtUbPj0FxDJ6VAETVIaS4keiuXpjoYi0yct99P/isA
+51bS5r/v8rRr3qlf60dGwFhdLtQ9JQQOxnnzzUg3g4dpAAuy2rvisEit5xacTlZ3NOULHztcMcXU
+Dgh3bxllmoRxFxVSHwMYFbL3eLZoQzBDYI2NFrqTUfzBV+MUCyfkYfgyabJnfTYp987W/XqSdGF4
+N092J41SFc9f/cN2I6Kr3n4vDsf3iGCew8BkT6lkhkNWwKmkwRvH2E7j1dOfF5FLmZPae23iKoJn
+uXni4TGhHzoyftlZMzs2ja9ftIiDltmI8brKPJcPphPM4FMpOyC4Glm9txplwSRrQhqQIYTuANGT
+59433Ydo3oTATtk+droerCTR5PEwK+ILJlWljz38CLbPS4pnM+LDsWXBoyIDILjN8HgKqeVSxy7e
+FQ0Lg9PSUIKMbRXvMGCWB1M7GnrDx9Eit+pSQjezVGwOw3lEWGHRdPbUk85b9fjYQQDn943/1+o8
+hh/+PfaKnLGRzfIP8Bi+kRBTDhCppTvLzRWnWpf0MFXdhPyU0Vvjw4cRCPTEw08JLRywEpywztp3
+11yeKa39OPyxEzbCiL1Vz5qfHZRaKjeFhEHcmguO0divy5+ljg/7CfXpNz6rU0rko9I+nSpcfcrJ
+kWWHUx8IilNA0a2FChr0Qf8Ko+z3KqO3TClmyKjhzh/cLYJjNaTpStww7GLV/nUMTCboN8dLx4pb
+5/Tlm4r6Fy8fGYOCmKzqK1Q9sW5DAseYaEpAcJJGZcNTgb/e0ZVz2jae0TZKt3UbscN4xICINZOB
+y0o75Q02hpGJrChISGPFc/6YzxHs2a1EqnybDEdIqXR89zgeK+zQT/JEUUcbrZ27oz0EGh3UQIyF
+qS4IfO6gB1nH+SqSsnNRjlgMCeTQywWxybXHg202ZPY/wRiUynQPGrerAyal9/WHHMPtje/QvKaP
+uu1SEoa6H2pyR2IbLOWER3JvTlfJube49eaP8NckelPmE3WQ9uQfV2LoyKLGZr16t5zlJNcLLMT+
+GLMunRsX0AOKMvFi/kgL5UDd/V0dDg9oX8DNRYIn8Io0shprCSk/K2F+135cboGBAfrbEcyugHDQ
+Z1NwOOwp4SSv3StQk/l2YhqHgAJLtw9wSMPKDJTerwo0ib8yOrVQ2jwAatbwBpt1HwR9RWo1ch5i
+6raTgxuapO7SEntZ/J5BxMQ4r51dqmEkox6c3vWI/G31Q4T0lqt8g+Xys3oKCDQwsI8+Vscd/HRp
+wu3kZbuMowxbB364NM8kT1k2ZxtfuTJ/cx2l8RAvwj4oZZ/GVzUPsX9sRIT4IFHkCE7EHVHL1eSj
+2FLgZSIPLCju2saIDIzO+2IDLSZZoXH0nTUSttAytgTGh2NlyjmMra60YUL7ypMfFFt9iWpBLNUb
+OTYX61pX9ePPl8QG4U9HCtnp5gANhe/nvszdfVMpi6d3Z0fyhqh0/Mg2jjvGKaZbILKuv77udUPb
+FOxQGLQ3JUdAmZ+kqVMi88dTGeobBLyEqY3fDs61/7qkHrmU6TYn8zhKSH2ZqV7ONEw1NEgi1jxr
+/tvZXACpbc7xPFKfaXM/RJh+EnpHiB3NDXzpmj9Y7rrNw/TpQd7qDRNucM5r4dTQYnSO7hhbd4er
+lAubzOaxFsCkXVIugkn1jGn0flu+x/+YczWUkOZyUD8w7DgvGM4PzQsCfu4RrGJNBoCHMnOvli1d
+JHU5uKLIkWtQVtltt/2TNA6R7u3dh1DxJfMHCMkD4Yh+zUxiaDkAG4X/yAxzRWt0vFQVdY4x/u0H
+pi1j9ANwZin4oWrWaB5bioOtBPeqHvjljivCV73XakshKR49LoVk80gkFpDsHNkATqqDcKBejt62
+c/I6e3mY2gGO38ysZS6t3ZwKvZPGvpNHxb2PalsX/6r05kl3IwVopqw9mQpHlKMiXVVis7YgUwkv
+AMNuOowfcQ9qLkmG8Y7PPqzZwG1ECPGL7uprYx63Td/Afjsbh9dh1cfr1xZ/m8KwotlyQ99rGnJi
+exn6sbiLxxlT2zd5DHvRGVADZVbnTgUg1XsPyGkc2S2sdNzlBC9fTC3iVEYo9FimMfl+VeXVHv5D
+BuJHvQMt4khu8rpdEvRhgtjn/hwq+X82oZk0fs/xR7Usq1Vv4a47d/yjy3sAp62F7v+4kGamvgEI
+MjItAaVUri29rkFDSq5vN7wabp3q9ON30NJiIDviy76XkgFGVOcTM7/74ZYFjPU/kAiBo5t0Mh2A
+6J06kXhD06I+LtZ+XbdIPElhMKK2kVmfX/UHoVG0InD4ccY4uPw22J4u3S1hFu4tOeqUI/DrYtW1
+kLOyrm11/u0oD5Oh1MOnbYrC6uHnXtnv8YM1IHQH++d0I8yho14ddi9gfOf10f0h2gR8tS74Qw+l
+LC1Vlyn32Mi0s0J7ymvcO8H23JzgUJgPCZd15lLzqwrs5EHlk7/0T/InfS3gktSHUxSNfkCpvDPl
+BXFI9hJZ1aQPKHOvjSrdYmhAhk92wuP4ABfWANFT/K0XkopFFgiwqarbl30hTkGlkOjHmJF7Va5j
+JSl73h853B2gWYrw9PKIC+Wu0DGGIQcD+xg72/XezX+CnMK/BCGKUI+8giV8Bd5EA3ihz2uJ5EvH
+cuAg5Xh7b2oZgeXbFDO1lcTEDskPIctVH318esIFijcCBq7g0I2kVmi+L/EA0NASxkzqcQ2FvpAF
+wcytYxN/R7ZA1d6fpxsBntTsUT6Bdo3SfIh7Kqe3l4quDza63LxzteL0ATTgR70GvjxoL+hTWVM0
+SQ0L0PJdiqxafhLXf2a8SbtBRbcUUkUmCmEjHi+31lDepIJXRQW/x6LPn0DqBe1HKdp834MFLECg
+KcWORZncc7mVvcHRecqNCDUhv6c5sHwbWWHolNGT7/MCQXQqE5aPagN5C1JTy5qx9Ndne0WEwyWJ
+t82EjnJy0IkvGTSVjHGVgZGftyckXjNKgvsjGwMeOm/J0sTepl3lh1pRIsnZMThQGmHTSiv5n9tn
+WC7zUfy6geZ6danTpYy9oGMvO7K/E2MjATpI1x8v6P7nVxZxehj/MQLMBgm7xWvaQRmsV8+uT+GY
+C/kqSOQ9ohPlUdDaVI9Dl5FTLMPT4fQAwOrd2k0tJOu5q0FzKb6zeAAZC6dMBUkJpcrxWALx0wPP
+FeQ6hEFBeGfZGpU0qZvSOKRbPrMkVoLYXY9wRyxLblXfcPHvg3YJwA9TdwU3k6MLyx1GIYx97N6Q
+pU/NCaukR6wzNLRskb4IjnTvVyTCMzje92Ai0o3plJTpds3sx8Z6ihEE1s1teNSRsWm6dzkYahtG
+7Q4jGoQ7B79nKnMFdGl0oU2oGlU208UBHIro3GIXWaVZ/HdsmjFe0QIPosUBKNcRte+z4Sc4pV5b
+2iNWLzL984DOywwYc9dYy8VL1NOSImSFVbDv3AECc8zEEX9D1IUTJk4aOCU+AkasWdY6mDywmZ+D
+Qdj5r4qCABl/kbI07p5p5ukkvjdHpYbr98/nS58H6ImO8b19NN511nLc8N8zGP3BMTTHs3OqBQV7
+T3ZwmDHMx4QxCGdFMDH0wpi1pcSA/LS0I6NcJLa2QH28zKlSAWEbFHQ+P4BgG59xxpmtj8tbSN+C
+h6qPUY/hemB8yCNNHdTUU4rM2ZJ8IAjar4N+4RVJUbGTgwhZEPvntq6vbGkCkXbigqAA6ikxK65j
++9UJfrPWA7IGRYpjBd5AwTtJSE2Kgi/dXUhnM8oJecfx6scX5egOq4/UxjchytabGB1dVuv/MLkK
+26JrBE8G08hRy0PFL1g2+fJHOquhuiyuEt9Emo6sK/zr1IY3bLflolXFeUSpM/8Xebdh8Q4xraQA
+7kYCOrmguZjaLawg3qGw+fRQPmfw9CiFnroG2cLMzL7iIsGY3WG1sS7d2ebgPKldY+4c5gKzfmZn
+I23v8u50WAUkJWP7BzaaIginlhqO7p4JmBHTGbpZlFPEfuAT6ASAGBdW645xQ83uOY8joP1eXrLu
+/qm5V4tM6MyajN4zjCBxMGdOoGnCr/+qGqq+XEP/173Fii52T/+6SCpYajJ3WoBSe3kBgSobvZTs
+5PoWtnLN6jq1DfXKvLQPnR+2d417PM7NvxkWA2DRE9/CTpeiia7J5Z0k4or+2QGHIvj8JE44KRQX
+7SOGfT8aLF9wgvuFDz7r6bow5TTr+jBUak3kzOU/+YZcA9Nuimbn1E//vz7IuP8DEL2xy7xLjYB0
+J8pftH2fNL4ECUt3Jvgrv440P3q4YNiERGkUp3nrSrADZ1dmvGYmR5qgKP3eN8RarJ5klOlP9EiI
+xnyW1dHG2TJrZdD0UfdftjrMA9dmuKxoaF11nrDS637mDZtMBtb98gohFONFQ//jYWWzsAy6LbWv
+vzwrEfawRi6oAxwM8oSJ9iPYRYTtNWJZnbbb2JyqbrRDhKbMvhZc8xSyFLXYuzvFLOZvzI97cQ0k
+rg8jfehUms4ZE2Z1xHAAiwObpwRJrRqNVEuqvw6DRDYDW496u3SAU7ED3N2x1yGNf+DAUjVLcz3R
+pLCaGcFOCM7CFDcWMX+t6zkykdjcTOKJi4aS5nZmO9Ei2WyXW9OOpOQYtXNUCLbZjIYTc5zyh//5
+dRuma3HOTiMbiIigeKGNIQJjMoqhB4BsOHGZAPMDmmteVsUDCQvuE33wLTLituwT1uQVd1KBTEWv
+d8UHLKmtuutczo9YCEClsSo/dJm0hQn/LXJeSwDtXzgQVGHvHF7W1OSlN3BtdQ1f28quEzU9a2hM
+ek5AaVapXTAo1bQSBieyGy6CaDp6xOF9qZGV5xW/CAucl+rs28qt//OfJB1CkqekJEq/6VcUdyn6
+CHJVOKli2N/1qaukHob0iaWfzyyd5hpgEmnIzAMerSLYLxANqRm33VPeVFeJd8NveFHhJnbzK0JP
+TpzfKKMUCQPowkaWPmJUQKCxhaFdkm6eWtSzk7rpbfAOMsNgchicQcv0IojBGl97N1y9lSndDvPE
+SFUVmQUXr3HzQcVc/LvwJzcYYAXacnxDJ3GT4VrxJH77HnryYCqhSwjZ8s5m6OCxb6UpgHQXmPFt
+dTZeplsKTo7IvFFwaW8nDgEkrjv0HPI/5NAN6UjuI1VHjr0d+B6G6iXFbssdcEjsFMhyowopitKS
+MVYrsbVucRkb4PTtAq9H+Xkz7GRzhrBFpDEORficehT/DeTLWwaA2iffNNitMd+rQF9FUEFez/PO
+564wQuERYkEq1vvpYqaW6VWZ3vqyZr5lqrsYkOaB9iQNpdMspm0ldj9PS7RJuvHc5W7lYdQx2wbB
+TdUiEB6uUoareO4NP8k4EA9Y0MiXScyghj94QEFCqrol1A7c140jtR2e7LTSO0teekRHO+ZdHnUx
+Q8qNiTFMPB2poOV2wI3QH7yOMRZDYDuROkIr3N9xhJGupkN2oq3q+JSaaq/hPdHQ8twVMj7gRkIl
+p2amMwO3ry7LOMXICk6pWe7RS9uBd3Pp0Irpmzhqp38E3RoNnoEdeC4F8YjAu+XNaM5yS70mpEtx
+6ciDH8Qj+0wlL2DSjnR9hiKpEVgoUgAjEH7/kVdeg0xOMeT1vvRg5Xovq4FIpQUvEzcyDIgBKSuo
+kU5G2TWzO7MLzFIevrPF3vFlyvxZF1rtiOrpffzB1X4dEhuk8TMTVyy7MElb5YbtGRQZKMLgDKnR
++sPLsJY6fI4UGkhW0PD279amuBATcx2XAUoPWJ6nZKhyEq4GpRHVLZAwwu3wxbD/wNmrZD/r2WzQ
+C0ZHwEswyK8pDk09BSdiGyIvFJDeKXjEWEi1XlotoO/0/0Xn+cgNAi+SUeZBz1VrWyDNtCLYEcNm
+UAndcyyy0aWdpzKjyV2vHuajlLZ+GOFCwMEr57nPHM1xDlUOPMBqrfWimJ0l+3Pt9HsOer/VgXuF
+b/+ta3VXM0f59UYMAr2O+XCPqZUd+gDChmqCaBkIijx48+nzk0n2so8iL6XJ2oEYIDlkVi4mfQ/y
+7OLgbExLc/47wdMF4sfaOWfYa74pkfik6Scku6SOJ0wU3WK+N5lo1aTbjhPwvhIvg4J1MaCLawUh
+ez0GfR2dc+UElnDxf9ZdaAVr3wjPPA0AbFvMz9VZeiW6yMWujjpLAtRgLCZfYT3/41rpons6pjsD
+Hj2P9vJjy0h+0j7yiYdRmVWzWLAvSy33WIHjRK2uj2isoaE1UDG0enibwB6kZHlAy82NPeJDvRQ3
+HjlEcB007ZZukMixCtvdmnPWXnfeJeCIIwHNJyRFV2LcTRHR2PjEo6cvbQlUwFdrA2xwby+izDIM
+AxbNDxdBGcL9k/e93BpzIga45WxCSd1jy4x4CqDRJJACmclDpIt2/CaqtlxHRf8an4unDOpf87t5
+HQ8mJsMfr/hHFSAU25DvNntfhmQ59i3M3lJNcq7fNNMX5aMPaX6PzHHBdYz43q/cETlp3umq8+U7
+gt5hVq3AZqKuYje/vPgLOu/FdO5kO0Fn5dKVVQTP4z8ebwqXsb6Q99Y0lkXKvFhlQTUVe91BTfNt
+b9kXltPUdxlN3ti8ybmORcWulDgNAgVmgPxADyTgw1u7ley4VkTE1X0g+0M1xBg+S5UvxFRDrDFf
+MNPdKaT2mTF6XzpLof2Xf2GYDnVhRpCHA4688rNxIAmwIKYd9nC52d2GXhTiD1hiFANQ0NtFYpLR
+I1OLiVzAUEoWc+UQFtc5KL2JGoYxZJEIQDBBPml3zvqWjO/GtVzyYabRuXzjEKolx+KR54Mgvfvj
+k6E/NTl1YVi1ctZlNSqLhuOU9+E0iQH4Zk36SS3StGXKIj3fhTaKtcetJ+jL3Gsa0YKA+AHTFUNv
++FhPFSIhq6Ea2D9TMVpT5dQRJTBZ2p2aE4xH0hpWGtWd3L6wrv8aDs62qkObyBu7BH7oRSZfFAGb
+1R9O1YVDZvv2MUold7iQJkjGEosFJ6LrEo/RgOcIHZNUGbQyT0oRA3Khx5bEkIPdv8REww+RLqJI
+0N/PllHVyPy6gqwfwuA8C0ylZq3NyZ+SJl/dMD6Pk8TgDppfYHdERHwRhG6QGHJKjTwc13ZEivC2
+EMS73hXqOk59WIAt5aNrQ8B9JWTIv3egw8jO3Gha4jbDp2fss2eQ0DkZtHS2/foXY6pHaGKkxNeQ
+w/EYTBZCGPxbRRSf8ZTasEyEKbjj45bM063JxRkj1omH5c68ZOPnd3VCMVs7pEva5cM24PQ3ePJn
+L3ppamEzfzfBlBXo/SE5zCUeU5NRx6YzNe3JdIHTkutGHetM7krJdNh8CSCO4xzFk79YDDTqdxfy
+8h+hcb2YKXNim1taVwOhWBGu0H2cBuUeh2fwMGIq9YTATpV5PFwmX3+Gvz/JTGr2cXYXpxp6vIR2
+EEVUawYFz4R6MhwNbb1jaobpg+JnFQu76Xz4eiRL2lJnR83C48RSp7DZaubhcCIHDN4B62qt4UdH
+s+GaoDyk3h+FdckyCPbxPRdV5y3+5EHYGb5AAC2+N5TaOZmECZbaD4Jfjo1Xi63SDa/tbxruV0Cg
+bVxp853Y5iyUPk77Ns5n1woNu6OgqM4VYQxKV6pSGQJut283QSo+ezWAklMXNJL4Nk/eaZk3zSR0
+NGDyRWgB4QZHVRV9YmbT1mJynuYzyJZKhxfQJIHPJuMDyFLMIq+doh3QexZ2zCGKTZ2WCc9uN6Ic
+wu4=
+`pragma protect end_protected
+module Fixed_Point_Divider_Top (
+  dividend,
+  divisor,
+  start,
+  clk,
+  quotient_out,
+  complete
+)
+;
+input [31:0] dividend;
+input [31:0] divisor;
+input start;
+input clk;
+output [31:0] quotient_out;
+output complete;
+wire VCC;
+wire GND;
+  \~qdiv.Fixed_Point_Divider_Top  u_fra_div (
+    .clk(clk),
+    .start(start),
+    .dividend(dividend[31:0]),
+    .divisor(divisor[31:0]),
+    .complete(complete),
+    .quotient_out(quotient_out[31:0])
+);
+  VCC VCC_cZ (
+    .V(VCC)
+);
+  GND GND_cZ (
+    .G(GND)
+);
+  GSR GSR (
+    .GSRI(VCC) 
+);
+endmodule /* Fixed_Point_Divider_Top */

ModRetro_oss-chromatic-console-fpga/esp32t/src/rtl/BSP/uart/uart.v

@@ -0,0 +1,142 @@
+//
+// File name          :uart.v
+// Module name        :uart.v
+// Created by         :GaoYun Semi
+// Author             :(Winson)
+// Created On         :2020-11-05 14:26 GuangZhou
+// Last Modified      :
+// Update Count       :2020-11-05 14:26
+// Description        :
+//----------------------------------------------------------------------
+//===========================================
+module UART2 
+#(    parameter CLK_FREQ    = 30'd60000000 // set system clock frequency in Hz
+      //parameter BAUD_RATE   = 4000000   // baud rate value
+     // parameter P_PARITY_BIT  = "none"   // legal values: "none", "even", "odd", "mark", "space"
+)
+(
+    input              CLK        , // clock
+    input              RST        , // reset
+        // UART INTERFACE
+    output             UART_TXD   ,
+    input              UART_RXD   ,
+    output             UART_RTS   , // when UART_RTS = 0, UART This Device Ready to receive.
+    input              UART_CTS   , // when UART_CTS = 0, UART Opposite Device Ready to receive.
+        // UART Control Reg
+    input  [31:0]      BAUD_RATE ,
+    input  [7:0]       PARITY_BIT,
+    input  [7:0]       STOP_BIT  ,
+    input  [7:0]       DATA_BITS ,
+        // USER DATA INPUT INTERFACE
+    input   [15:0]     TX_DATA    , //
+    input              TX_DATA_VAL, // when TX_DATA_VAL = 1, data on TX_DATA will be transmit, DATA_SEND can set to 1 only when BUSY = 0
+    output             TX_BUSY    , // when BUSY = 1 transiever is busy, you must not set DATA_SEND to 1
+        // USER FIFO CONTROL INTERFACE
+    output  [15:0]     RX_DATA    , //
+    output             RX_DATA_VAL  //
+);
+
+
+    reg  [3:0] uart_rxd_shreg     ;
+    reg        uart_rxd_debounced ;
+    reg  [3:0] uart_cts_shreg     ;
+    reg        uart_cts_debounced ;
+    wire       uart_tx_busy       ;
+    wire [31:0]div_out ;
+    wire       div_cmpl;
+    wire  [1:0] div_correct = 'd3;
+
+    wire [23:0] divider_value = 'd72;// = CLK_FREQ/(15*BAUD_RATE);
+    // -------------------------------------------------------------------------
+    // UART DIVIDER VALUE
+    // -------------------------------------------------------------------------
+    //always @(posedge CLK or posedge RST) begin
+    //    if (RST) begin
+    //        divider_value <= 24'd0;
+    //    end
+    //    else begin
+    //        //divider_value <= CLK_FREQ/(15*BAUD_RATE);
+    //        divider_value <= CLK_FREQ/(BAUD_RATE);
+    //    end
+    //end
+    // -------------------------------------------------------------------------
+    // UART RXD DEBAUNCER
+    // -------------------------------------------------------------------------
+    always @(posedge CLK or posedge RST) begin
+        if (RST) begin
+            uart_rxd_shreg <= 4'hF;
+            uart_rxd_debounced <= 1'b1;
+        end
+        else begin
+            uart_rxd_shreg <= {UART_RXD, uart_rxd_shreg[3:1]};
+            uart_rxd_debounced <= uart_rxd_shreg[0]|uart_rxd_shreg[1]|uart_rxd_shreg[2]|uart_rxd_shreg[3];
+        end
+    end
+
+    always @(posedge CLK or posedge RST) begin
+        if (RST) begin
+            uart_cts_shreg <= 4'hF;
+            uart_cts_debounced <= 1'b1;
+        end
+        else begin
+            uart_cts_shreg <= {UART_CTS, uart_cts_shreg[3:1]};
+            uart_cts_debounced <= uart_cts_shreg[0]|uart_cts_shreg[1]|uart_cts_shreg[2]|uart_cts_shreg[3];
+        end
+    end
+
+    assign UART_RTS  = 1'b0;
+    assign TX_BUSY   = uart_tx_busy | UART_CTS;
+
+    // -------------------------------------------------------------------------
+    // UART TRANSMITTER
+    // -------------------------------------------------------------------------
+    UART_TX 
+    //#( .P_PARITY_BIT (P_PARITY_BIT)) 
+        uart_tx_inst (
+            .CLK         (CLK         )
+           ,.RST         (RST         )
+            // UART INTERFACE
+           //,.UART_CLK_EN (uart_clk_en )
+           ,.UART_TXD    (UART_TXD    )
+            // UART PARAMETER
+           //,.UART_PARITY_BIT (UART_PARITY_BIT  )
+           //,.UART_DATA_BIT   (UART_DATA_BIT    )
+           ,.PARITY_BIT  (PARITY_BIT)
+           ,.STOP_BIT    (STOP_BIT  )//0: 1 stop bit  1: 1.5 stop bit 2: 2 stop bit
+           ,.DATA_BITS   (DATA_BITS )//5 6 7 8 16
+           ,.DIVIDER_VALUE(divider_value )//16'd37
+           ,.DIV_CORRECT(div_correct  )//16'd37
+
+            // USER DATA INPUT INTERFACE
+           ,.DATA_IN     (TX_DATA     )
+           ,.DATA_SEND   (TX_DATA_VAL )
+           ,.BUSY        (uart_tx_busy)
+    );
+
+    // -------------------------------------------------------------------------
+    // UART RECEIVER
+    // ------------------------------------------------------------------------- 
+    UART_RX 
+    #( .P_PARITY_BIT ("odd")) 
+        uart_rx_inst (
+            .CLK         (CLK                )
+           ,.RST         (RST                )
+           // UART INTERFACE
+           //,.UART_CLK_EN (uart_clk_en        )
+           ,.UART_RXD    (uart_rxd_debounced )
+            // UART PARAMETER
+           //,.UART_PARITY_BIT (UART_PARITY_BIT  )
+           //,.UART_DATA_BIT (UART_DATA_BIT  )
+           ,.PARITY_BIT  (PARITY_BIT )
+           ,.STOP_BIT    (STOP_BIT   )//0: 1 stop bit  1: 1.5 stop bit 2: 2 stop bit
+           ,.DATA_BITS   (DATA_BITS  )//5 6 7 8 16
+           ,.DIVIDER_VALUE(divider_value)//
+           ,.DIV_CORRECT(div_correct  )//16'd37
+            // USER DATA INPUT INTERFACE
+           ,.DATA_OUT    (RX_DATA    )
+           ,.DATA_VLD    (RX_DATA_VAL)
+           ,.FRAME_ERROR (           )
+    );
+
+
+endmodule

ModRetro_oss-chromatic-console-fpga/esp32t/src/rtl/BSP/uart/uart_rx.vhd

@@ -0,0 +1,497 @@
+--------------------------------------------------------------------------------
+-- PROJECT: SIMPLE UART FOR FPGA
+--------------------------------------------------------------------------------
+-- MODULE:  UART RECEIVER
+-- AUTHORS: Jakub Cabal <jakubcabal@gmail.com>
+-- lICENSE: The MIT License (MIT)
+-- WEBSITE: https://github.com/jakubcabal/uart_for_fpga
+--------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+entity UART_RX is
+    Generic (
+        P_PARITY_BIT  : string := "none" -- legal values: "none", "even", "odd", "mark", "space"
+    );
+    Port (
+        CLK         : in  std_logic; -- system clock
+        RST         : in  std_logic; -- high active synchronous reset
+        -- UART INTERFACE
+        --UART_CLK_EN : in  std_logic; -- oversampling (15x) UART clock enable
+        UART_RXD    : in  std_logic;
+        -- UART PARAMETER
+        PARITY_BIT  : in  std_logic_vector(7 downto 0);
+        STOP_BIT    : in  std_logic_vector(7 downto 0);
+        DATA_BITS   : in  std_logic_vector(7 downto 0);
+        DIVIDER_VALUE : in  std_logic_vector(23 downto 0);
+        DIV_CORRECT  : in  std_logic_vector(1 downto 0);
+        -- USER DATA OUTPUT INTERFACE
+        DATA_OUT    : out std_logic_vector(15 downto 0);
+        DATA_VLD    : out std_logic; -- when DATA_VLD = 1, data on DATA_OUT are valid
+        FRAME_ERROR : out std_logic  -- when FRAME_ERROR = 1, stop bit was invalid, current and next data may be invalid
+    );
+end UART_RX;
+
+architecture FULL of UART_RX is
+
+    signal rx_clk_en          : std_logic;
+    signal rx_hf_clk_en       : std_logic;
+    signal rx_ticks           : unsigned(23 downto 0);
+    signal rx_clk_divider_en  : std_logic;
+    signal rx_data            : std_logic_vector(15 downto 0);
+    signal parity_bit_reg     : std_logic_vector(7 downto 0);
+    signal stop_bit_reg       : std_logic_vector(7 downto 0);
+    signal data_bits_reg      : std_logic_vector(7 downto 0);
+    signal divider_value_reg  : std_logic_vector(23 downto 0);
+    signal div_correct_reg    : std_logic_vector(1 downto 0);
+    signal rx_bit_count       : unsigned(3 downto 0);
+    signal rx_bit_count_en    : std_logic;
+    signal rx_data_shreg_en   : std_logic;
+    signal rx_parity_bit      : std_logic;
+    signal rx_parity_error    : std_logic;
+    signal parity_temp        : std_logic;
+    signal rx_parity_check_en : std_logic;
+    signal rx_output_reg_en   : std_logic;
+    signal rx_busy            : std_logic;
+    signal uart_ticks         : unsigned(15 downto 0);
+    signal uart_clk_en        : std_logic;
+
+    type state is (idle, startbit, databits, paritybit, stopbit, stopbit15, stopbit2);
+    signal rx_pstate : state;
+    signal rx_nstate : state;
+
+begin
+
+    -- -------------------------------------------------------------------------
+    -- UART RECEIVER CLOCK DIVIDER
+    -- -------------------------------------------------------------------------
+
+    uart_rx_sample_clk : process (CLK)
+    begin
+        if (rising_edge(CLK)) then
+            if (RST = '1') then
+                uart_ticks <= (others => '0');
+                uart_clk_en <= '0';
+            else
+                if (uart_ticks = (unsigned(divider_value_reg) - 1)) then
+                    uart_ticks <= (others => '0');
+                    uart_clk_en <= '1';
+                else
+                    uart_ticks <= uart_ticks + 1;
+                    uart_clk_en <= '0';
+                end if;
+            end if;
+         end if;
+    end process;
+
+    uart_rx_clk_divider : process (CLK)
+    begin
+        if (rising_edge(CLK)) then
+            if (rx_clk_divider_en = '1') then
+                --if (uart_clk_en = '1') then
+                    --if (rx_ticks = "1110") then
+                if ((rx_bit_count(1 downto 0) = "01") AND (div_correct_reg(1 downto 1) = "1")) then
+                    if (rx_ticks = (unsigned(divider_value_reg))) then
+                        rx_ticks <= (others => '0');
+                        rx_clk_en <= '0';
+                        rx_hf_clk_en <= '1';
+                    --elsif (rx_ticks = "0111") then
+                    elsif (rx_ticks = (unsigned(divider_value_reg) srl 1)) then
+                        rx_ticks <= rx_ticks + 1;
+                        rx_clk_en <= '1';
+                        rx_hf_clk_en <= '1';
+                    else
+                        rx_ticks <= rx_ticks + 1;
+                        rx_clk_en <= '0';
+                        rx_hf_clk_en <= '0';
+                    end if;
+                elsif ((rx_bit_count(1 downto 0) = "10") AND (div_correct_reg(1 downto 0) = "11")) then
+                    if (rx_ticks = (unsigned(divider_value_reg))) then
+                        rx_ticks <= (others => '0');
+                        rx_clk_en <= '0';
+                        rx_hf_clk_en <= '1';
+                    --elsif (rx_ticks = "0111") then
+                    elsif (rx_ticks = (unsigned(divider_value_reg) srl 1)) then
+                        rx_ticks <= rx_ticks + 1;
+                        rx_clk_en <= '1';
+                        rx_hf_clk_en <= '1';
+                    else
+                        rx_ticks <= rx_ticks + 1;
+                        rx_clk_en <= '0';
+                        rx_hf_clk_en <= '0';
+                    end if;
+                 elsif ((rx_bit_count(1 downto 0) = "11") AND (div_correct_reg(1 downto 0) /= "00")) then
+                    if (rx_ticks = (unsigned(divider_value_reg))) then
+                        rx_ticks <= (others => '0');
+                        rx_clk_en <= '0';
+                        rx_hf_clk_en <= '1';
+                    --elsif (rx_ticks = "0111") then
+                    elsif (rx_ticks = (unsigned(divider_value_reg) srl 1)) then
+                        rx_ticks <= rx_ticks + 1;
+                        rx_clk_en <= '1';
+                        rx_hf_clk_en <= '1';
+                    else
+                        rx_ticks <= rx_ticks + 1;
+                        rx_clk_en <= '0';
+                        rx_hf_clk_en <= '0';
+                    end if;
+                else
+                    if (rx_ticks = (unsigned(divider_value_reg) - 1)) then
+                        rx_ticks <= (others => '0');
+                        rx_clk_en <= '0';
+                        rx_hf_clk_en <= '1';
+                    --elsif (rx_ticks = "0111") then
+                    elsif (rx_ticks = (unsigned(divider_value_reg) srl 1)) then
+                        rx_ticks <= rx_ticks + 1;
+                        rx_clk_en <= '1';
+                        rx_hf_clk_en <= '1';
+                    else
+                        rx_ticks <= rx_ticks + 1;
+                        rx_clk_en <= '0';
+                        rx_hf_clk_en <= '0';
+                    end if;
+                end if;
+                --else
+                --    rx_ticks <= rx_ticks;
+                --    rx_clk_en <= '0';
+                --    rx_hf_clk_en <= '0';
+                --end if;
+            else
+                rx_ticks <= (others => '0');
+                rx_clk_en <= '0';
+                rx_hf_clk_en <= '0';
+            end if;
+        end if;
+    end process;
+
+    -- -------------------------------------------------------------------------
+    -- UART RECEIVER BIT COUNTER
+    -- -------------------------------------------------------------------------
+
+    uart_rx_bit_counter : process (CLK)
+    begin
+        if (rising_edge(CLK)) then
+            if (RST = '1') then
+                rx_bit_count <= (others => '0');
+            elsif (rx_bit_count_en = '1' AND rx_clk_en = '1') then
+                if (rx_bit_count = "1111") then
+                    rx_bit_count <= (others => '0');
+                else
+                    rx_bit_count <= rx_bit_count + 1;
+                end if;
+            elsif (rx_bit_count_en = '0') then
+                rx_bit_count <= (others => '0');
+            end if;
+        end if;
+    end process;
+
+    -- -------------------------------------------------------------------------
+    -- UART RECEIVER DATA SHIFT REGISTER
+    -- -------------------------------------------------------------------------
+
+    uart_rx_data_shift_reg : process (CLK)
+    begin
+        if (rising_edge(CLK)) then
+            if (RST = '1') then
+                rx_data <= (others => '0');
+            elsif (rx_clk_en = '1' AND rx_data_shreg_en = '1') then
+                if (data_bits_reg = "00000101") then
+                    rx_data <= "00000000000" & UART_RXD & rx_data(4 downto 1);
+                elsif (data_bits_reg = "00000110") then
+                    rx_data <= "0000000000" & UART_RXD & rx_data(5 downto 1);
+                elsif (data_bits_reg = "00000111") then
+                    rx_data <= "000000000" & UART_RXD & rx_data(6 downto 1);
+                elsif (data_bits_reg = "00001000") then
+                    rx_data <= "00000000" & UART_RXD & rx_data(7 downto 1);
+                else
+                    rx_data <= UART_RXD & rx_data(15 downto 1);
+                end if;
+            end if;
+        end if;
+    end process;
+
+    DATA_OUT <= rx_data;
+
+    uart_rx_ctrl_reg : process (CLK)
+    begin
+        if (rising_edge(CLK)) then
+            if (RST = '1') then
+                parity_bit_reg <= (others => '0');
+                stop_bit_reg   <= (others => '0');
+                data_bits_reg  <= (others => '0');
+                divider_value_reg  <= (others => '0');
+                div_correct_reg <= "00";
+            elsif (rx_busy = '0') then
+                parity_bit_reg <= PARITY_BIT;
+                stop_bit_reg   <= STOP_BIT;
+                data_bits_reg  <= DATA_BITS;
+                divider_value_reg  <= DIVIDER_VALUE;
+                div_correct_reg <= DIV_CORRECT;
+                --divider_value_reg  <= "00100000";
+            end if;
+        end if;
+    end process;
+    -- -------------------------------------------------------------------------
+    -- UART RECEIVER PARITY GENERATOR AND CHECK
+    -- -------------------------------------------------------------------------
+
+    --uart_rx_parity_g : if (P_PARITY_BIT /= "none") generate
+    --    uart_rx_parity_gen_i: entity work.UART_PARITY
+    --    generic map (
+    --        DATA_WIDTH  => 8,
+    --        PARITY_TYPE => P_PARITY_BIT
+    --    )
+    --    port map (
+    --        DATA_IN     => rx_data,
+    --        PARITY_OUT  => rx_parity_bit
+    --    );
+    --end generate;
+
+    parity_gen : process (CLK)
+    begin
+        if (rising_edge(CLK)) then
+            if (RST = '1') then
+                parity_temp <= '0';
+            elsif (parity_bit_reg = "00000000") then --none
+                parity_temp <= '0';
+            elsif (parity_bit_reg = "00000001") then --odd
+                if (rx_pstate = startbit) then
+                    parity_temp <= '1';
+                elsif (rx_bit_count_en = '1' AND rx_clk_en = '1') then
+                    parity_temp <= parity_temp XOR UART_RXD;
+                end if;
+            elsif (parity_bit_reg = "00000010") then --even
+                if (rx_pstate = startbit) then
+                    parity_temp <= '0';
+                elsif (rx_bit_count_en = '1' AND rx_clk_en = '1') then
+                    parity_temp <= parity_temp XOR UART_RXD;
+                end if;
+            elsif (parity_bit_reg = "00000011") then --mark
+                parity_temp <= '1';
+            elsif (parity_bit_reg = "00000100") then --space
+                parity_temp <= '0';
+            end if;
+        end if;
+    end process;
+
+        uart_rx_parity_check_reg : process (CLK)
+        begin
+            if (rising_edge(CLK)) then
+                if (RST = '1') then
+                    rx_parity_error <= '0';
+                elsif (rx_parity_check_en = '1') then
+                    --rx_parity_error <= rx_parity_bit XOR UART_RXD;
+                    if (parity_bit_reg = "00000000") then
+                        rx_parity_error <= '0';
+                    else
+                        rx_parity_error <= parity_temp XOR UART_RXD;
+                    end if;
+                end if;
+            end if;
+        end process;
+
+    --uart_rx_noparity_g : if (PARITY_BIT = "none") generate
+    --    rx_parity_error <= '0';
+    --end generate;
+
+    -- -------------------------------------------------------------------------
+    -- UART RECEIVER OUTPUT REGISTER
+    -- -------------------------------------------------------------------------
+
+    uart_rx_output_reg : process (CLK)
+    begin
+        if (rising_edge(CLK)) then
+            if (RST = '1') then
+                DATA_VLD <= '0';
+                FRAME_ERROR <= '0';
+            else
+                if (rx_output_reg_en = '1') then
+                    DATA_VLD <= NOT rx_parity_error AND UART_RXD;
+                    FRAME_ERROR <= NOT UART_RXD;
+                else
+                    DATA_VLD <= '0';
+                    FRAME_ERROR <= '0';
+                end if;
+            end if;
+        end if;
+    end process;
+
+    -- -------------------------------------------------------------------------
+    -- UART RECEIVER FSM
+    -- -------------------------------------------------------------------------
+
+    -- PRESENT STATE REGISTER
+    process (CLK)
+    begin
+        if (rising_edge(CLK)) then
+            if (RST = '1') then
+                rx_pstate <= idle;
+            else
+                rx_pstate <= rx_nstate;
+            end if;
+        end if;
+    end process;
+
+    -- NEXT STATE AND OUTPUTS LOGIC
+    process (rx_pstate, UART_RXD,  rx_hf_clk_en, rx_clk_en, rx_bit_count, data_bits_reg, parity_bit_reg, stop_bit_reg)
+    begin
+        case rx_pstate is
+
+            when idle =>
+                rx_output_reg_en <= '0';
+                rx_bit_count_en <= '0';
+                rx_data_shreg_en <= '0';
+                rx_clk_divider_en <= '0';
+                rx_parity_check_en <= '0';
+                rx_busy <= '0';
+                if (UART_RXD = '0') then
+                    rx_nstate <= startbit;
+                else
+                    rx_nstate <= idle;
+                end if;
+
+            when startbit =>
+                rx_output_reg_en <= '0';
+                rx_bit_count_en <= '0';
+                rx_data_shreg_en <= '0';
+                rx_clk_divider_en <= '1';
+                rx_parity_check_en <= '0';
+                rx_busy <= '1';
+
+                if (rx_clk_en = '1') then
+                    rx_nstate <= databits;
+                else
+                    rx_nstate <= startbit;
+                end if;
+
+            when databits =>
+                rx_output_reg_en <= '0';
+                rx_bit_count_en <= '1';
+                rx_data_shreg_en <= '1';
+                rx_clk_divider_en <= '1';
+                rx_parity_check_en <= '0';
+                rx_busy <= '1';
+
+                --if ((rx_clk_en = '1') AND (rx_bit_count = "111")) then
+                if (rx_clk_en = '1') then
+                    if ((data_bits_reg = "00000101") AND (rx_bit_count = "0100")) then --data bit 5
+                        if (parity_bit_reg = "00000000") then
+                            rx_nstate <= stopbit;
+                        else
+                            rx_nstate <= paritybit;
+                        end if ;
+                    elsif ((data_bits_reg = "00000110") AND (rx_bit_count = "0101")) then --data bit 6
+                        if (parity_bit_reg = "00000000") then
+                            rx_nstate <= stopbit;
+                        else
+                            rx_nstate <= paritybit;
+                        end if ;
+                    elsif ((data_bits_reg = "00000111") AND (rx_bit_count = "0110")) then --data bit 7
+                        if (parity_bit_reg = "00000000") then
+                            rx_nstate <= stopbit;
+                        else
+                            rx_nstate <= paritybit;
+                        end if ;
+                    elsif ((data_bits_reg = "00001000") AND (rx_bit_count = "0111")) then --data bit 8
+                        if (parity_bit_reg = "00000000") then
+                            rx_nstate <= stopbit;
+                        else
+                            rx_nstate <= paritybit;
+                        end if ;
+                    elsif ((data_bits_reg = "00010000") AND (rx_bit_count = "1111")) then --data bit 16
+                        if (parity_bit_reg = "00000000") then
+                            rx_nstate <= stopbit;
+                        else
+                            rx_nstate <= paritybit;
+                        end if ;
+                    else
+                        rx_nstate <= databits;
+                    end if;
+                else
+                    rx_nstate <= databits;
+                end if;
+
+            when paritybit =>
+                rx_output_reg_en <= '0';
+                rx_bit_count_en <= '0';
+                rx_data_shreg_en <= '0';
+                rx_clk_divider_en <= '1';
+                rx_parity_check_en <= '1';
+                rx_busy <= '1';
+
+                if (rx_clk_en = '1') then
+                    rx_nstate <= stopbit;
+                else
+                    rx_nstate <= paritybit;
+                end if;
+
+            when stopbit =>
+                rx_bit_count_en <= '0';
+                rx_data_shreg_en <= '0';
+                rx_clk_divider_en <= '1';
+                rx_parity_check_en <= '0';
+                rx_busy <= '1';
+
+                if (rx_clk_en = '1') then
+                    if (stop_bit_reg = "00000000") then --Stop bit 1
+                        rx_nstate <= idle;
+                        rx_output_reg_en <= '1';
+                    elsif (stop_bit_reg = "00000001") then --Stop bit 1.5
+                        rx_nstate <= stopbit15;
+                        rx_output_reg_en <= '0';
+                    elsif (stop_bit_reg = "00000010") then --Stop bit 2
+                        rx_nstate <= stopbit2;
+                        rx_output_reg_en <= '0';
+                    else
+                        rx_nstate <= idle;
+                        rx_output_reg_en <= '1';
+                    end if;
+                else
+                    rx_nstate <= stopbit;
+                    rx_output_reg_en <= '0';
+                end if;
+
+            when stopbit15 =>
+                rx_bit_count_en <= '0';
+                rx_data_shreg_en <= '0';
+                rx_clk_divider_en <= '1';
+                rx_parity_check_en <= '0';
+                rx_busy <= '1';
+
+                if (rx_hf_clk_en = '1') then
+                    rx_nstate <= idle;
+                    rx_output_reg_en <= '1';
+                else
+                    rx_nstate <= stopbit15;
+                    rx_output_reg_en <= '0';
+                end if;
+
+            when stopbit2 =>
+                rx_bit_count_en <= '0';
+                rx_data_shreg_en <= '0';
+                rx_clk_divider_en <= '1';
+                rx_parity_check_en <= '0';
+                rx_busy <= '1';
+
+                if (rx_clk_en = '1') then
+                    rx_nstate <= idle;
+                    rx_output_reg_en <= '1';
+                else
+                    rx_nstate <= stopbit2;
+                    rx_output_reg_en <= '0';
+                end if;
+
+            when others =>
+                rx_output_reg_en <= '0';
+                rx_bit_count_en <= '0';
+                rx_data_shreg_en <= '0';
+                rx_clk_divider_en <= '0';
+                rx_parity_check_en <= '0';
+                rx_nstate <= idle;
+
+        end case;
+    end process;
+
+end FULL;

ModRetro_oss-chromatic-console-fpga/esp32t/src/rtl/BSP/uart/uart_tx.vhd

@@ -0,0 +1,518 @@
+--------------------------------------------------------------------------------
+-- PROJECT: SIMPLE UART FOR FPGA
+--------------------------------------------------------------------------------
+-- MODULE:  UART TRANSMITTER
+-- AUTHORS: Jakub Cabal <jakubcabal@gmail.com>
+-- lICENSE: The MIT License (MIT)
+-- WEBSITE: https://github.com/jakubcabal/uart_for_fpga
+--------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.NUMERIC_STD.ALL;
+
+entity UART_TX is
+    --Generic (
+        --PARITY_BIT  : string := "none" -- legal values: "none", "even", "odd", "mark", "space"
+    --);
+    Port (
+        CLK         : in  std_logic; -- system clock
+        RST         : in  std_logic; -- high active synchronous reset
+        -- UART INTERFACE
+        --UART_CLK_EN : in  std_logic; -- oversampling (15x) UART clock enable
+        UART_TXD    : out std_logic;
+        -- UART PARAMETER
+        PARITY_BIT  : in  std_logic_vector(7 downto 0);
+        STOP_BIT    : in  std_logic_vector(7 downto 0);
+        DATA_BITS   : in  std_logic_vector(7 downto 0);
+        DIVIDER_VALUE : in  std_logic_vector(23 downto 0);
+        DIV_CORRECT  : in  std_logic_vector(1 downto 0);
+        -- USER DATA INPUT INTERFACE
+        DATA_IN     : in  std_logic_vector(15 downto 0);
+        DATA_SEND   : in  std_logic; -- when DATA_SEND = 1, data on DATA_IN will be transmit, DATA_SEND can set to 1 only when BUSY = 0
+        BUSY        : out std_logic  -- when BUSY = 1 transiever is busy, you must not set DATA_SEND to 1
+    );
+end UART_TX;
+
+architecture FULL of UART_TX is
+
+    signal tx_clk_en         : std_logic;
+    signal tx_hf_clk_en      : std_logic;
+    signal tx_clk_divider_en : std_logic;
+    signal tx_ticks          : unsigned(23 downto 0);
+    signal tx_data           : std_logic_vector(15 downto 0);
+    signal parity_bit_reg    : std_logic_vector(7 downto 0);
+    signal stop_bit_reg      : std_logic_vector(7 downto 0);
+    signal data_bits_reg     : std_logic_vector(7 downto 0);
+    signal divider_value_reg : std_logic_vector(23 downto 0);
+    signal div_correct_reg   : std_logic_vector(1 downto 0);
+    signal tx_bit_count      : unsigned(3 downto 0);
+    signal tx_bit_count_en   : std_logic;
+    signal tx_busy           : std_logic;
+    signal tx_parity_bit     : std_logic;
+    signal parity_temp       : std_logic;
+    signal tx_data_out_sel   : std_logic_vector(1 downto 0);
+    signal uart_ticks        : unsigned(15 downto 0);
+    signal uart_clk_en       : std_logic;
+
+    type state is (idle, txsync, startbit, databits, paritybit, stopbit, stopbit15, stopbit2);
+    signal tx_pstate : state;
+    signal tx_nstate : state;
+
+begin
+
+    BUSY <= tx_busy OR DATA_SEND;
+
+    -- -------------------------------------------------------------------------
+    -- UART TRANSMITTER CLOCK DIVIDER
+    -- -------------------------------------------------------------------------
+
+    uart_tx_sample_clk : process (CLK)
+    begin
+        if (rising_edge(CLK)) then
+            if (RST = '1') then
+                uart_ticks <= (others => '0');
+                uart_clk_en <= '0';
+            else
+                if (uart_ticks = (unsigned(divider_value_reg) - 1)) then
+                    uart_ticks <= (others => '0');
+                    uart_clk_en <= '1';
+                else
+                    uart_ticks <= uart_ticks + 1;
+                    uart_clk_en <= '0';
+                end if;
+            end if;
+         end if;
+    end process;
+
+    uart_tx_clk_divider : process (CLK)
+    begin
+        if (rising_edge(CLK)) then
+            if (tx_clk_divider_en = '1') then
+                --if (uart_clk_en = '1') thediv
+                    --if (tx_ticks = "1110") then
+                 if ((tx_bit_count(1 downto 0) = "01") AND (div_correct_reg(1 downto 1) = "1")) then
+                    if (tx_ticks = (unsigned(divider_value_reg))) then
+                        tx_ticks <= (others => '0');
+                        tx_clk_en <= '0';
+                        tx_hf_clk_en <= '0';
+                    --elsif (tx_ticks = "0001") then
+                    elsif (tx_ticks = "000000000000000000000001") then
+                        tx_ticks <= tx_ticks + 1;
+                        tx_clk_en <= '1';
+                        tx_hf_clk_en <= '1';
+                    --elsif (tx_ticks = "1001") then
+                    elsif (tx_ticks = (unsigned(divider_value_reg) srl 1) + 1) then
+                        tx_ticks <= tx_ticks + 1;
+                        tx_clk_en <= '0';
+                        tx_hf_clk_en <= '1';
+                    else
+                        tx_ticks <= tx_ticks + 1;
+                        tx_clk_en <= '0';
+                        tx_hf_clk_en <= '0';
+                    end if;
+                 elsif ((tx_bit_count(1 downto 0) = "10") AND (div_correct_reg(1 downto 0) = "11")) then
+                    if (tx_ticks = (unsigned(divider_value_reg))) then
+                        tx_ticks <= (others => '0');
+                        tx_clk_en <= '0';
+                        tx_hf_clk_en <= '0';
+                    --elsif (tx_ticks = "0001") then
+                    elsif (tx_ticks = "000000000000000000000001") then
+                        tx_ticks <= tx_ticks + 1;
+                        tx_clk_en <= '1';
+                        tx_hf_clk_en <= '1';
+                    --elsif (tx_ticks = "1001") then
+                    elsif (tx_ticks = (unsigned(divider_value_reg) srl 1) + 1) then
+                        tx_ticks <= tx_ticks + 1;
+                        tx_clk_en <= '0';
+                        tx_hf_clk_en <= '1';
+                    else
+                        tx_ticks <= tx_ticks + 1;
+                        tx_clk_en <= '0';
+                        tx_hf_clk_en <= '0';
+                    end if;
+                 elsif ((tx_bit_count(1 downto 0) = "11") AND (div_correct_reg(1 downto 0) /= "00")) then
+                    if (tx_ticks = (unsigned(divider_value_reg))) then
+                        tx_ticks <= (others => '0');
+                        tx_clk_en <= '0';
+                        tx_hf_clk_en <= '0';
+                    --elsif (tx_ticks = "0001") then
+                    elsif (tx_ticks = "000000000000000000000001") then
+                        tx_ticks <= tx_ticks + 1;
+                        tx_clk_en <= '1';
+                        tx_hf_clk_en <= '1';
+                    --elsif (tx_ticks = "1001") then
+                    elsif (tx_ticks = (unsigned(divider_value_reg) srl 1) + 1) then
+                        tx_ticks <= tx_ticks + 1;
+                        tx_clk_en <= '0';
+                        tx_hf_clk_en <= '1';
+                    else
+                        tx_ticks <= tx_ticks + 1;
+                        tx_clk_en <= '0';
+                        tx_hf_clk_en <= '0';
+                    end if;
+                else
+                    if (tx_ticks = (unsigned(divider_value_reg) - 1)) then
+                        tx_ticks <= (others => '0');
+                        tx_clk_en <= '0';
+                        tx_hf_clk_en <= '0';
+                    --elsif (tx_ticks = "0001") then
+                    elsif (tx_ticks = "000000000000000000000001") then
+                        tx_ticks <= tx_ticks + 1;
+                        tx_clk_en <= '1';
+                        tx_hf_clk_en <= '1';
+                    --elsif (tx_ticks = "1001") then
+                    elsif (tx_ticks = (unsigned(divider_value_reg) srl 1) + 1) then
+                        tx_ticks <= tx_ticks + 1;
+                        tx_clk_en <= '0';
+                        tx_hf_clk_en <= '1';
+                    else
+                        tx_ticks <= tx_ticks + 1;
+                        tx_clk_en <= '0';
+                        tx_hf_clk_en <= '0';
+                    end if;
+                end if;
+                --else
+                --    tx_ticks <= tx_ticks;
+                --    tx_clk_en <= '0';
+                --    tx_hf_clk_en <= '0';
+                --end if;
+            else
+                tx_ticks <= (others => '0');
+                tx_clk_en <= '0';
+                tx_hf_clk_en <= '0';
+            end if;
+        end if;
+    end process;
+
+    -- -------------------------------------------------------------------------
+    -- UART TRANSMITTER INPUT DATA REGISTER
+    -- -------------------------------------------------------------------------
+
+    uart_tx_input_data_reg : process (CLK)
+    begin
+        if (rising_edge(CLK)) then
+            if (RST = '1') then
+                tx_data <= (others => '0');
+            elsif (DATA_SEND = '1' AND tx_busy = '0') then
+                tx_data <= DATA_IN;
+            end if;
+        end if;
+    end process;
+
+    uart_tx_ctrl_reg : process (CLK)
+    begin
+        if (rising_edge(CLK)) then
+            if (RST = '1') then
+                parity_bit_reg <= (others => '0');
+                stop_bit_reg  <= (others => '0');
+                data_bits_reg <= "00001000";
+                divider_value_reg <= "000000000000000000100000";
+                div_correct_reg <= "00";
+            elsif ((tx_pstate = txsync) or (tx_pstate = idle)) then
+            --else
+                parity_bit_reg <= PARITY_BIT;
+                stop_bit_reg   <= STOP_BIT;
+                data_bits_reg  <= DATA_BITS;
+                divider_value_reg <= DIVIDER_VALUE;
+                div_correct_reg <= DIV_CORRECT;
+            end if;
+        end if;
+    end process;
+    -- -------------------------------------------------------------------------
+    -- UART TRANSMITTER BIT COUNTER
+    -- -------------------------------------------------------------------------
+
+    uart_tx_bit_counter : process (CLK)
+    begin
+        if (rising_edge(CLK)) then
+            if (RST = '1') then
+                tx_bit_count <= (others => '0');
+            elsif (tx_bit_count_en = '1' AND tx_clk_en = '1') then
+                if (tx_bit_count = "1111") then
+                    tx_bit_count <= (others => '0');
+                else
+                    tx_bit_count <= tx_bit_count + 1;
+                end if;
+            elsif (tx_bit_count_en = '0') then
+                tx_bit_count <= (others => '0');
+            end if;
+        end if;
+    end process;
+
+    -- -------------------------------------------------------------------------
+    -- UART TRANSMITTER PARITY GENERATOR
+    -- -------------------------------------------------------------------------
+
+    --uart_tx_parity_g : if (PARITY_BIT /= "none") generate
+    --uart_tx_parity_g uart_tx_parity_gen_i: entity work.UART_PARITY
+    --    generic map (
+    --        DATA_WIDTH  => 8,
+    --        PARITY_TYPE => PARITY_BIT
+    --    )
+    --    port map (
+    --        DATA_IN     => tx_data,
+    --        PARITY_OUT  => tx_parity_bit
+    --    );
+    --end generate;
+
+    --uart_tx_noparity_g : if (PARITY_BIT = "none") generate
+    --    tx_parity_bit <= 'Z';
+    --end generate;
+
+    tx_parity_bit <= parity_temp;
+    -- -------------------------------------------------------------------------
+    -- UART TRANSMITTER OUTPUT DATA REGISTER
+    -- -------------------------------------------------------------------------
+
+    uart_tx_output_data_reg : process (CLK)
+    begin
+        if (rising_edge(CLK)) then
+            if (RST = '1') then
+                UART_TXD <= '1';
+            else
+                case tx_data_out_sel is
+                    when "01" => -- START BIT
+                        UART_TXD <= '0';
+                    when "10" => -- DATA BITS
+                        UART_TXD <= tx_data(to_integer(tx_bit_count));
+                    when "11" => -- PARITY BIT
+                        UART_TXD <= tx_parity_bit;
+                    when others => -- STOP BIT OR IDLE
+                        UART_TXD <= '1';
+                end case;
+            end if;
+        end if;
+    end process;
+
+    -- -------------------------------------------------------------------------
+    -- UART PARITY GEN
+    -- -------------------------------------------------------------------------
+    parity_gen : process (CLK)
+    begin
+        if (rising_edge(CLK)) then
+            if (RST = '1') then
+                parity_temp <= '0';
+            elsif (parity_bit_reg = "00000000") then --none
+                parity_temp <= '0';
+            elsif (parity_bit_reg = "00000001") then --odd
+                if (tx_pstate = startbit) then
+                    parity_temp <= '1';
+                elsif (tx_bit_count_en = '1' AND tx_clk_en = '1') then
+                    parity_temp <= parity_temp XOR tx_data(to_integer(tx_bit_count));
+                end if;
+            elsif (parity_bit_reg = "00000010") then --even
+                if (tx_pstate = startbit) then
+                    parity_temp <= '0';
+                elsif (tx_bit_count_en = '1' AND tx_clk_en = '1') then
+                    parity_temp <= parity_temp XOR tx_data(to_integer(tx_bit_count));
+                end if;
+            elsif (parity_bit_reg = "00000011") then --mark
+                parity_temp <= '1';
+            elsif (parity_bit_reg = "00000100") then --space
+                parity_temp <= '0';
+            end if;
+        end if;
+    end process;
+    -- -------------------------------------------------------------------------
+    -- UART TRANSMITTER FSM
+    -- -------------------------------------------------------------------------
+
+    -- PRESENT STATE REGISTER
+    --process (CLK)
+    --begin
+    --    if (rising_edge(CLK)) then
+    --        if (RST = '1') then
+    --            tx_pstate <= idle;
+    --        else
+    --            tx_pstate <= tx_nstate;
+    --        end if;
+    --    end if;
+    --end process;
+
+    -- NEXT STATE AND OUTPUTS LOGIC
+    -- process (tx_pstate, DATA_SEND, tx_hf_clk_en, tx_clk_en, tx_bit_count)
+    process (CLK)
+    begin
+        if (rising_edge(CLK)) then
+            if (RST = '1') then
+                tx_pstate <= idle;
+            else
+                case tx_pstate is
+                    when idle =>
+                        tx_busy <= '0';
+                        tx_data_out_sel <= "00";
+                        tx_bit_count_en <= '0';
+                        tx_clk_divider_en <= '0';
+                
+                        if (DATA_SEND = '1') then
+                            tx_pstate <= txsync;
+                        else
+                            tx_pstate <= idle;
+                        end if;
+                
+                    when txsync =>
+                        tx_busy <= '1';
+                        tx_data_out_sel <= "00";
+                        tx_bit_count_en <= '0';
+                        tx_clk_divider_en <= '1';
+                
+                        --if (stop_bit_reg = "00000000") then
+                        --    if (tx_clk_en = '1') then
+                        --        tx_pstate <= startbit;
+                        --    else
+                        --        tx_pstate <= txsync;
+                        --    end if;
+                        --elsif (stop_bit_reg = "00000001") then
+                        --    if (tx_hf_clk_en = '1') then
+                        --        tx_pstate <= startbit;
+                        --    else
+                        --        tx_pstate <= txsync;
+                        --    end if;
+                        --elsif (stop_bit_reg = "00000010") then
+                        --    if (tx_clk_en = '1') then
+                        --        tx_pstate <= startbit;
+                        --    else
+                        --        tx_pstate <= txsync;
+                        --    end if;
+                        --end if;
+                            if (tx_clk_en = '1') then
+                                tx_pstate <= startbit;
+                            else
+                                tx_pstate <= txsync;
+                            end if;
+                    when startbit =>
+                        tx_busy <= '1';
+                        tx_data_out_sel <= "01";
+                        tx_bit_count_en <= '0';
+                        tx_clk_divider_en <= '1';
+                
+                        if (tx_clk_en = '1') then
+                            tx_pstate <= databits;
+                        else
+                            tx_pstate <= startbit;
+                        end if;
+                
+                    when databits =>
+                        tx_busy <= '1';
+                        tx_data_out_sel <= "10";
+                        tx_bit_count_en <= '1';
+                        tx_clk_divider_en <= '1';
+                
+                        --if ((tx_clk_en = '1') AND (tx_bit_count = "111")) then
+                        if (tx_clk_en = '1') then
+                            if ((data_bits_reg = "00000101") AND (tx_bit_count = "0100")) then --5 bit
+                                if (parity_bit_reg = "00000000") then
+                                    tx_pstate <= stopbit;
+                                else
+                                    tx_pstate <= paritybit;
+                                end if ;
+                            elsif ((data_bits_reg = "00000110") AND (tx_bit_count = "0101")) then --6 bit
+                                if (parity_bit_reg = "00000000") then
+                                    tx_pstate <= stopbit;
+                                else
+                                    tx_pstate <= paritybit;
+                                end if ;
+                            elsif ((data_bits_reg = "00000111") AND (tx_bit_count = "0110")) then --7 bit
+                                if (parity_bit_reg = "00000000") then
+                                    tx_pstate <= stopbit;
+                                else
+                                    tx_pstate <= paritybit;
+                                end if ;
+                            elsif ((data_bits_reg = "00001000") AND (tx_bit_count = "0111")) then --8 bit
+                                if (parity_bit_reg = "00000000") then
+                                    tx_pstate <= stopbit;
+                                else
+                                    tx_pstate <= paritybit;
+                                end if ;
+                            elsif ((data_bits_reg = "00010000") AND (tx_bit_count = "1111")) then --16 bit
+                                if (parity_bit_reg = "00000000") then
+                                    tx_pstate <= stopbit;
+                                else
+                                    tx_pstate <= paritybit;
+                                end if ;
+                            else
+                                tx_pstate <= databits;
+                            end if ;
+                        else
+                            tx_pstate <= databits;
+                        end if;
+                
+                    when paritybit =>
+                        tx_busy <= '1';
+                        tx_data_out_sel <= "11";
+                        tx_bit_count_en <= '0';
+                        tx_clk_divider_en <= '1';
+                
+                        if (tx_clk_en = '1') then
+                            tx_pstate <= stopbit;
+                        else
+                            tx_pstate <= paritybit;
+                        end if;
+                
+                    when stopbit =>
+                        tx_data_out_sel <= "00";
+                        tx_bit_count_en <= '0';
+                        tx_clk_divider_en <= '1';
+                        if (stop_bit_reg = "00000000") then
+                            tx_busy <= '0';
+                            if (DATA_SEND = '1') then
+                                tx_pstate <= txsync;
+                            elsif (tx_clk_en = '1') then
+                                tx_pstate <= idle;
+                            else
+                                tx_pstate <= stopbit;
+                            end if;
+                        elsif (stop_bit_reg = "00000001") then
+                            tx_busy <= '1';
+                            if (tx_clk_en = '1') then
+                                tx_pstate <= stopbit15;
+                            else
+                                tx_pstate <= stopbit;
+                            end if;
+                        elsif (stop_bit_reg = "00000010") then
+                            if (tx_clk_en = '1') then
+                                tx_pstate <= stopbit2;
+                            else
+                                tx_pstate <= stopbit;
+                            end if;
+                        end if;
+                
+                    when stopbit15 =>
+                        tx_data_out_sel <= "00";
+                        tx_bit_count_en <= '0';
+                        tx_clk_divider_en <= '1';
+                        tx_busy <= '0';
+                        if (DATA_SEND = '1') then
+                            tx_pstate <= txsync;
+                        elsif (tx_hf_clk_en = '1') then
+                            tx_pstate <= idle;
+                        else
+                            tx_pstate <= stopbit15;
+                        end if;
+                
+                    when stopbit2 =>
+                        tx_data_out_sel <= "00";
+                        tx_bit_count_en <= '0';
+                        tx_clk_divider_en <= '1';
+                        tx_busy <= '0';
+                        if (DATA_SEND = '1') then
+                            tx_pstate <= txsync;
+                        elsif (tx_clk_en = '1') then
+                            tx_pstate <= idle;
+                        else
+                            tx_pstate <= stopbit2;
+                        end if;
+                
+                    when others =>
+                        tx_busy <= '1';
+                        tx_data_out_sel <= "00";
+                        tx_bit_count_en <= '0';
+                        tx_clk_divider_en <= '0';
+                        tx_pstate <= idle;
+                end case;
+            end if;
+        end if;
+    end process;
+
+end FULL;

ModRetro_oss-chromatic-console-fpga/esp32t/src/rtl/BSP/uart/usb_uart_config.v

@@ -0,0 +1,277 @@
+//
+// File name          :uart.v
+// Module name        :uart.v
+// Created by         :GaoYun Semi
+// Author             :(Winson)
+// Created On         :2020-11-05 14:26 GuangZhou
+// Last Modified      :
+// Update Count       :2020-11-05 14:26
+// Description        :
+//----------------------------------------------------------------------
+//===========================================
+module usb_uart_config 
+(
+    input              PHY_CLKOUT        ,// clock
+    input              RESET_IN          ,// reset
+    input              setup_active      ,
+    input   [3:0]      endpt_sel         ,
+    input              usb_rxval         ,
+    input              usb_rxact         ,
+    input   [7:0]      usb_rxdat         ,
+    input              usb_txact         ,
+    input              usb_txpop         ,
+    output  [11:0]     usb_txdat_len_o   ,
+    output  [7:0]      endpt0_dat_o      ,
+    output             endpt0_send_o     ,
+    output             uart1_en_o        ,
+    output  [31:0]     uart1_BAUD_RATE_o ,
+    output  [7:0]      uart1_PARITY_BIT_o,
+    output  [7:0]      uart1_STOP_BIT_o  ,
+    output  [7:0]      uart1_DATA_BITS_o,
+    output  reg [15:0] s_ctl_sig
+
+);
+
+parameter ENDPT_UART_CONFIG =4'h0;
+parameter ENDPT_UART1_DATA  =4'h1;
+parameter ENDPT_UART2_DATA  =4'h2;
+parameter ENDPT_UART3_DATA  =4'h3;
+parameter ENDPT_I2C1        =4'h4;
+parameter ENDPT_I2C2        =4'h5;
+parameter ENDPT_I2C3        =4'h6;
+parameter ENDPT_I2C4        =4'h7;
+parameter ENDPT_PARALLEL20  =4'h8;
+
+
+localparam  SET_LINE_CODING = 8'h20;
+localparam  GET_LINE_CODING = 8'h21;
+localparam  SET_CONTROL_LINE_STATE = 8'h22;
+
+reg [7:0] stage;
+reg [7:0] sub_stage;
+reg [7:0] s_req_type;
+reg [7:0] s_req_code;
+reg [15:0]s_set_len;
+reg [15:0]s_interface_num;
+reg       s_uart1_en;
+
+reg [31:0]s_dte1_rate;
+reg [7:0] s_char1_format;
+reg [7:0] s_parity1_type;
+reg [7:0] s_data1_bits;
+reg [7:0] s_char2_format;
+reg [7:0] s_parity2_type;
+reg [7:0] s_data2_bits;
+reg [31:0]s_dte3_rate;
+reg [7:0] s_char3_format;
+reg [7:0] s_parity3_type;
+reg [7:0] s_data3_bits;
+reg [7:0] endpt0_dat;
+reg       endpt0_send;
+
+assign uart1_en_o=s_uart1_en;
+assign uart1_BAUD_RATE_o=s_dte1_rate;
+assign uart1_PARITY_BIT_o=s_parity1_type;
+assign uart1_STOP_BIT_o=s_char1_format;
+assign uart1_DATA_BITS_o=s_data1_bits;
+assign endpt0_dat_o=endpt0_dat;
+assign endpt0_send_o=endpt0_send;
+assign usb_txdat_len_o=12'd7;
+
+always @(posedge PHY_CLKOUT,posedge RESET_IN) begin
+    if (RESET_IN) begin
+        stage <= 8'd0;
+        sub_stage <= 8'd0;
+        s_req_type <= 8'd0;
+        s_req_code <= 8'd0;
+        s_ctl_sig <= 16'd0;
+        s_set_len <= 16'd0;
+        s_interface_num<= 16'd0;
+        s_dte1_rate <= 32'd115200;
+        s_char1_format <= 8'd0;
+        s_parity1_type <= 8'd0;
+        s_data1_bits <= 8'd8;
+        endpt0_send <= 1'd0;
+        endpt0_dat  <= 8'd0;
+        s_uart1_en <= 1'b0;
+    end
+    else begin
+        if (setup_active) begin
+            if (usb_rxval) begin
+                case (stage)
+                    8'd0 : begin
+                        s_req_type <= usb_rxdat;
+                        stage <= stage + 8'd1;
+                        sub_stage <= 8'd0;
+                        endpt0_send <= 1'd0;
+                    end
+                    8'd1 : begin
+                        s_req_code <= usb_rxdat;
+                        stage <= stage + 8'd1;
+                    end
+                    8'd2 : begin
+                        if (s_req_code == SET_CONTROL_LINE_STATE) begin
+                            s_ctl_sig[7:0] <= usb_rxdat;
+                        end
+                        stage <= stage + 8'd1;
+                    end
+                    8'd3 : begin
+                        if (s_req_code == SET_CONTROL_LINE_STATE) begin
+                            s_ctl_sig[15:8] <= usb_rxdat;
+                        end
+                        stage <= stage + 8'd1;
+                    end
+                    8'd4 : begin
+                        stage <= stage + 8'd1;
+                        if (s_req_code == SET_LINE_CODING) begin
+                            s_interface_num[7:0] <= usb_rxdat;
+                        end
+                        else if (s_req_code == SET_CONTROL_LINE_STATE) begin
+                            s_interface_num[7:0] <= usb_rxdat;
+                        end
+                    end
+                    8'd5 : begin
+                        stage <= stage + 8'd1;
+                        if (s_req_code == SET_LINE_CODING) begin
+                            s_interface_num[15:8] <= usb_rxdat;
+                        end
+                        else if (s_req_code == SET_CONTROL_LINE_STATE) begin
+                            s_interface_num[15:8] <= usb_rxdat;
+                        end
+
+                    end
+                    8'd6 : begin
+                        if (s_req_code == SET_LINE_CODING) begin
+                            s_set_len[7:0] <= usb_rxdat;
+                        end
+                        else if (s_req_code == GET_LINE_CODING) begin
+                            s_set_len[7:0] <= usb_rxdat;
+                            if (s_interface_num == 16'd0) begin
+                                endpt0_send <= 1'd1;
+                            end
+                        end
+                        else if (s_req_code == SET_CONTROL_LINE_STATE) begin
+                            if (s_interface_num == 16'd0) begin
+                                s_uart1_en <= s_ctl_sig[0];
+                            end
+                        end
+                        stage <= stage + 8'd1;
+                    end
+                    8'd7 : begin
+                        if (s_req_code == SET_LINE_CODING) begin
+                            s_set_len[15:8] <= usb_rxdat;
+                        end
+                        else if (s_req_code == GET_LINE_CODING) begin
+                            s_set_len[15:8] <= usb_rxdat;
+                            if (s_interface_num == 16'd0) begin
+                                endpt0_send <= 1'd1;
+                                endpt0_dat <= s_dte1_rate[7:0];
+                            end
+                        end
+                        stage <= stage + 8'd1;
+                        sub_stage <= 8'd0;
+                    end
+                    8'd8 : begin
+                        stage <= stage;
+                    end
+                endcase
+            end
+        end
+        else if (s_req_code == SET_LINE_CODING) begin
+            stage <= 8'd0;
+            if ((usb_rxact)&&(endpt_sel ==ENDPT_UART_CONFIG)) begin
+                if (usb_rxval) begin
+                    sub_stage <= sub_stage + 8'd1;
+                    if(s_interface_num==0)begin
+                        if (sub_stage <= 3) begin
+                            s_dte1_rate <= {usb_rxdat,s_dte1_rate[31:8]};
+                        end
+                        else if (sub_stage == 4) begin
+                            s_char1_format <= usb_rxdat;
+                        end
+                        else if (sub_stage == 5) begin
+                            s_parity1_type <= usb_rxdat;
+                        end
+                        else if (sub_stage == 6) begin
+                            s_data1_bits <= usb_rxdat;
+                        end
+                    end
+                end
+            end
+        end
+        else if (s_req_code == GET_LINE_CODING) begin
+            stage <= 8'd0;
+            if ((usb_txact)&&(endpt_sel ==ENDPT_UART_CONFIG)) begin
+                if (endpt0_send == 1'b1) begin
+                    if (usb_txpop) begin
+                        sub_stage <= sub_stage + 8'd1;
+                    end
+                    if (s_req_code == GET_LINE_CODING) begin
+                       /* if (sub_stage <= 0) begin //old controller version
+                            endpt0_dat <= s_dte_rate[7:0];
+                        end
+                        else if (sub_stage == 1) begin
+                            endpt0_dat <= s_dte_rate[15:8];
+                        end
+                        else if (sub_stage == 2) begin
+                            endpt0_dat <= s_dte_rate[23:16];
+                        end
+                        else if (sub_stage == 3) begin
+                            endpt0_dat <= s_dte_rate[31:24];
+                        end
+                        else if (sub_stage == 4) begin
+                            endpt0_dat <= s_char_format;
+                        end
+                        else if (sub_stage == 5) begin
+                            endpt0_dat <= s_parity_type;
+                        end
+                        else if (sub_stage == 6) begin
+                            endpt0_dat <= s_data_bits;
+                        end
+                        else begin
+                            endpt0_send <= 1'b0;
+                        end*/
+                        if (usb_txpop) begin// new controller version
+                            if(s_interface_num==0)begin
+                                if (sub_stage <= 0) begin
+                                    endpt0_dat <= s_dte1_rate[15:8];
+                                end
+                                else if (sub_stage == 1) begin
+                                    endpt0_dat <= s_dte1_rate[23:16];
+                                end
+                                else if (sub_stage == 2) begin
+                                    endpt0_dat <= s_dte1_rate[31:24];
+                                end
+                                else if (sub_stage == 3) begin
+                                    endpt0_dat <= s_char1_format;
+                                end
+                                else if (sub_stage == 4) begin
+                                    endpt0_dat <= s_parity1_type;
+                                end
+                                else if (sub_stage == 5) begin
+                                    endpt0_dat <= s_data1_bits;
+                                end
+                                else if (sub_stage == 6) begin
+                                    endpt0_send <= 1'b0;
+                                end
+                                else begin
+                                    endpt0_send <= 1'b0;
+                                end
+                            end
+                        end
+                    end
+                end
+            end
+            else begin
+                sub_stage <= 8'd0;
+            end
+        end
+        else begin
+             stage <= 8'd0;
+             sub_stage <= 8'd0;
+        end
+    end
+end
+
+ 
+endmodule

ModRetro_oss-chromatic-console-fpga/esp32t/src/rtl/BSP/uart_packet_wrapper_rx.sv

@@ -0,0 +1,99 @@
+
+module uart_packet_wrapper_rx(
+    input               clk,
+    input               reset,
+    input   [7:0]       uart_rx_data,
+    input               uart_rx_val,
+    input               uartDisabled,
+    output  reg [6:0]   rx_address,
+    output  reg [79:0]  rx_data,
+    output  reg         rx_data_val
+);
+
+    localparam  RX_IDLE        =   3'd1;
+    localparam  RX_ADDR        =   3'd2;
+    localparam  RX_COUNT       =   3'd3;
+    localparam  RX_DATA        =   3'd4;
+    localparam  RX_CRC         =   3'd5;    
+    localparam  RX_ERROR       =   3'd6;    
+
+    reg [2:0] rx_state;
+    reg [7:0] rx_count;
+    reg [7:0] crc;
+    always@(posedge clk or posedge reset)
+    begin
+        if(reset) begin
+            rx_state <= RX_IDLE;
+        end else begin
+        
+            rx_data_val <=  1'd0;
+        
+            case(rx_state)
+            
+                  RX_IDLE    :
+                     if((uart_rx_val)&&(uart_rx_data == 8'h8F))
+                        rx_state <= RX_ADDR;
+                        
+                  RX_ADDR    :
+                     if(uart_rx_val) begin
+                         rx_state <= RX_COUNT;
+                         rx_address  <=  uart_rx_data[6:0];
+                     end
+                     
+                  RX_COUNT    :
+                     if(uart_rx_val) begin
+                         rx_state <= RX_DATA;
+                         rx_count <= uart_rx_data;
+                     end
+                     
+                  RX_DATA   :
+                     if(uart_rx_val) begin
+                         if (rx_count < 8'd2) begin
+                             rx_state <= RX_CRC;
+                         end else begin
+                             rx_count <= rx_count - 1'd1;
+                         end
+                         rx_data <= {rx_data[71:0], uart_rx_data};
+                     end
+                     
+                  RX_CRC   :
+                     if(uart_rx_val) begin
+                        if (crc == uart_rx_data) begin
+                           rx_data_val <=  1'd1;
+                           rx_state    <= RX_IDLE;
+                        end else begin
+                           rx_state <= RX_ERROR;
+                        end
+                     end
+                     
+                  RX_ERROR :
+                     rx_state    <= RX_IDLE;
+                        
+                  default :
+                     rx_state <= RX_IDLE;
+            endcase
+        end
+    end
+    
+    // CRC-8-SAE J1850 parameters
+    parameter POLY = 8'h1D; // Polynomial: x^8 + x^5 + x^4 + 1
+    reg [3:0] bit_count;
+    
+    always @(posedge clk) begin
+        if (rx_state == RX_IDLE && ~uart_rx_val) begin
+            crc <= 8'hFF;
+            bit_count <= 4'd0;
+        end else if (uart_rx_val) begin
+            bit_count <= 4'd8;
+            crc <= crc ^ uart_rx_data;
+        end else if (bit_count > 0) begin
+            bit_count <= bit_count - 1'd1;
+            if (crc[7]) begin
+                crc <= {crc[6:0], 1'b0} ^ POLY;
+            end else begin
+                crc <= {crc[6:0], 1'b0};
+            end
+        end
+    end
+
+endmodule

ModRetro_oss-chromatic-console-fpga/esp32t/src/rtl/BSP/uart_packet_wrapper_tx.sv

@@ -0,0 +1,162 @@
+
+module uart_packet_wrapper_tx(
+    input               clk,
+    input               reset,
+    input               uart_tx_busy,
+    output  reg [7:0]   uart_tx_data,
+    output  reg         uart_tx_val,
+    output              write_done,
+    input               write,
+    input               menuDisabled,
+    input               uartDisabled,
+    input       [6:0]   tx_address,
+    input       [7:0]   tx_byteCount,
+    output reg  [7:0]   tx_bytepos,
+    input       [7:0]   tx_senddata
+);
+
+    // Extra rate limiter between UART bytes
+    reg [3:0] cnt = 'd0;
+    always@(posedge clk)
+        cnt <= cnt + 1'd1;
+
+    localparam  TX_IDLE        =   4'd1;
+    localparam  TX_ADDR        =   4'd2;
+    localparam  TX_COUNT       =   4'd3;
+    localparam  TX_DATA        =   4'd4;
+    localparam  TX_CRC         =   4'd5;
+    localparam  TX_DONE        =   4'd6;
+    localparam  TX_SLEEP       =   4'd7;
+    localparam  TX_AWAKE       =   4'd8;
+    localparam  TX_START       =   4'd9;
+
+    reg [4:0] tx_state;
+    reg [7:0] bytecount;
+    
+    always@(posedge clk or posedge reset) begin
+        if(reset)
+            tx_state <= TX_IDLE;
+        else begin
+            if(uartDisabled)
+                tx_state <= TX_IDLE;
+            else begin
+                case(tx_state)
+                    
+                    TX_IDLE    :
+                        if (menuDisabled) begin
+                           tx_state <= TX_SLEEP;
+                        end else if(~uart_tx_busy&&write) begin
+                            tx_state <= TX_ADDR;
+                        end
+                            
+                    TX_ADDR    :
+                        if((~uart_tx_busy)&&(cnt == 'd0))
+                            tx_state <= TX_COUNT;       
+                            
+                    TX_COUNT    :
+                        if((~uart_tx_busy)&&(cnt == 'd0)) begin
+                            bytecount     <= tx_byteCount;
+                            tx_bytepos    <= 8'd0;
+                            tx_state <= TX_DATA;
+                        end
+                           
+                    TX_DATA   :
+                        if((~uart_tx_busy)&&(cnt == 'd0)) begin
+                            if (bytecount == 8'd1) begin
+                                tx_state <= TX_CRC; 
+                            end else begin
+                                bytecount  <= bytecount - 1'd1;
+                                tx_bytepos <= tx_bytepos + 1'd1;
+                            end
+                        end
+                            
+                    TX_CRC   :
+                        if((~uart_tx_busy)&&(cnt == 'd0))
+                            tx_state <= TX_DONE;
+                            
+                    TX_DONE   :
+                        if((~uart_tx_busy)&&(cnt == 'd0))
+                            tx_state <= TX_IDLE;
+                         
+                    TX_SLEEP :
+                        if(~uart_tx_busy&&write) begin
+                            tx_state <= TX_AWAKE;
+                            bytecount <= 8'd20; // test show about 15 bytes are lost after sleep
+                        end
+                            
+                    TX_AWAKE   :
+                        if((~uart_tx_busy)&&(cnt == 'd0)) begin
+                            if (bytecount == 8'd1) begin
+                                tx_state <= TX_START; 
+                            end else begin
+                                bytecount  <= bytecount - 1'd1;
+                            end
+                        end
+                        
+                    TX_START:
+                        if((~uart_tx_busy)&&(cnt == 'd0))
+                            tx_state <= TX_ADDR;
+                         
+                    default :
+                        tx_state <= TX_IDLE;
+                endcase
+            end
+        end
+    end
+    
+    always@(posedge clk) 
+    begin
+        uart_tx_val <=  1'd0;
+        if(~uart_tx_busy&~uartDisabled) begin
+            if(tx_state == TX_IDLE | tx_state == TX_SLEEP) begin
+                uart_tx_val <= write;
+            end else begin
+                if((cnt == 'd0)&&(tx_state != TX_DONE)) begin
+                    uart_tx_val <=  1'd1;
+                end
+            end
+        end
+    end
+    
+    assign write_done = tx_state == TX_DONE && (~uart_tx_busy)&&(cnt == 'd0);
+    
+    reg [7:0] crc;
+    
+    always@(posedge clk)
+    begin
+        case(tx_state)
+            TX_IDLE:       uart_tx_data    <=  8'h8F; //Magic header
+            TX_ADDR:       uart_tx_data    <=  {1'd0,tx_address[6:0]};
+            TX_COUNT:      uart_tx_data    <=  tx_byteCount;
+            TX_DATA:       uart_tx_data    <=  tx_senddata;
+            TX_CRC:        uart_tx_data    <=  crc;
+            TX_SLEEP:      uart_tx_data    <=  8'h00;
+            TX_AWAKE:      uart_tx_data    <=  8'h00;
+            TX_START:      uart_tx_data    <=  8'h8F; //Magic header
+            default:       uart_tx_data    <=  8'hCA;
+        endcase
+    end
+    
+    // CRC-8-SAE J1850 parameters
+    parameter POLY = 8'h1D; // Polynomial: x^8 + x^5 + x^4 + 1
+    reg [3:0] bit_count;
+    
+    always @(posedge clk) begin
+        if (tx_state == TX_IDLE && ~write) begin
+            crc <= 8'hFF;
+            bit_count <= 4'd0;
+        end else if (uart_tx_val && tx_state != TX_SLEEP && tx_state != TX_AWAKE && tx_state != TX_START) begin
+            bit_count <= 4'd8;
+            crc <= crc ^ uart_tx_data;
+        end else if (bit_count > 0) begin
+            bit_count <= bit_count - 1'd1;
+            if (crc[7]) begin
+                crc <= {crc[6:0], 1'b0} ^ POLY;
+            end else begin
+                crc <= {crc[6:0], 1'b0};
+            end
+        end
+    end
+    
+
+endmodule

ModRetro_oss-chromatic-console-fpga/esp32t/src/rtl/BSP/vid_system_top.sv

@@ -0,0 +1,476 @@
+// vid_system_top.v
+
+module vid_system_top #(parameter ISSIMU=0)
+(
+    input               gClk,
+    input               hClk,
+    input               pClk,
+    input               reset,
+
+    input               BTN_MENU,
+    output reg          slideOutActive,
+
+    output [5:0]        LCD_DB,
+    output              LCD_ENABLE_UVC,
+    output [17:0]       LCD_DB_UVC,
+    output              LCD_DOTCLK,
+    output              LCD_ENABLE,
+    output              LCD_HSYNC,
+    output              LCD_RESET,
+    output              LCD_SPI_CSX,
+    output              LCD_SPI_SCLK,
+    output              LCD_SPI_SDA,
+    input               LCD_TE,
+    input               LCD_EN,
+    output              LCD_GENLOCK,
+    output              LCD_VSYNC,
+
+    input               frameBlendEnable,
+    input               colorCorrectionEnableLCD,
+    input               colorCorrectionEnableUVC,
+    input               voltageLow,
+    input [1:0]         lowBattDispMode,
+    input               showTimer,
+    input               runTimer,
+    input               resetTimer,
+    input               gSecondEna,
+    input               gPercentEna,
+    input [31:0]        debug_system,
+    input               debug_system_on,
+
+    output              hGBNewLine,
+    output reg [22:0]   hGBAddress,
+    output              hGBWrite,
+    output  [15:0]      hGBData,
+
+    output              hValid,
+    output              hHsync,
+    output              hVsync,
+    input [15:0]        hWrBurstQ,
+    input [15:0]        hWrBurstQ2,
+    output  reg         hDrawOSD,
+
+    output              LCD_INIT_DONE,
+    input               gb_lcd_clkena,
+    input [14:0]        gb_lcd_data,
+    input [1:0]         gb_lcd_mode,
+    input               gb_lcd_on,
+    input               gb_lcd_vsync
+
+);
+
+    ODDR u_ODDR(
+        .Q0(LCD_DOTCLK),
+        .Q1(),
+        .D0(1'd1),
+        .D1(1'd0),
+        .TX(1'd1),
+        .CLK(gClk)
+    );
+
+
+    ST7785_init #(ISSIMU)
+    u_ST7785_init(
+        .clk(pClk),
+        .reset(reset),
+        .LCD_CS(LCD_SPI_CSX),
+        .LCD_SCK(LCD_SPI_SCLK),
+        .LCD_SDA_SDI(LCD_SPI_SDA),
+        .LCD_RST(LCD_RESET),
+        .LCD_INIT_DONE(LCD_INIT_DONE)
+    );
+
+    wire [14:0] hColorPixel;
+    assign hHsync = gb_lcd_mode[1];
+    assign hVsync = gb_lcd_vsync;
+
+
+    reg hHsync_r1;
+    reg hVsync_r1;
+    always@(posedge hClk)
+    begin
+        hHsync_r1 <= hHsync;
+        hVsync_r1 <= hVsync;
+    end
+
+    reg hGBFrameBufferNum;
+    always@(posedge hClk)
+    begin
+        if(hVsync&~hVsync_r1)
+        begin
+           hGBAddress        <= 23'h10000;
+        end
+        else
+            if(hGBNewLine&~hVsync)
+                hGBAddress <= hGBAddress + 'd320;
+    end
+
+    assign  hGBWrite    = gb_lcd_clkena;
+    assign  hGBNewLine  = ~hHsync&hHsync_r1;
+    assign  hGBData     = {1'd0, gb_lcd_data[14:0]};
+
+    reg [7:0] screenX;
+    reg [7:0] screenY;
+    always@(posedge hClk) begin
+        if (hHsync&~hHsync_r1) begin
+            screenX <= 8'd0;
+            screenY <= screenY + 1'd1;
+        end else if (gb_lcd_clkena) begin
+            screenX <= screenX + 1'd1;
+        end
+
+        if(hVsync&~hVsync_r1) begin
+            hDrawOSD <= ~BTN_MENU;
+            screenY  <= 8'd0;
+        end
+    end
+        
+    wire [6:0] sum_r = {hWrBurstQ[4:0],1'd0} + {gb_lcd_data[4:0],1'd0};
+    wire [6:0] sum_g = {hWrBurstQ[9:5],1'd0} + {gb_lcd_data[9:5],1'd0};
+    wire [6:0] sum_b = {hWrBurstQ[14:10],1'd0} + {gb_lcd_data[14:10],1'd0};
+
+    wire [5:0]  game_r  =   frameBlendEnable ? sum_r[6:1] : {gb_lcd_data[4:0],1'b0};
+    wire [5:0]  game_g  =   frameBlendEnable ? sum_g[6:1] : {gb_lcd_data[9:5],1'b0};
+    wire [5:0]  game_b  =   frameBlendEnable ? sum_b[6:1] : {gb_lcd_data[14:10],1'b0};
+    
+    wire [17:0] psel = {game_b,game_g,game_r};
+
+    // OSD and overlay
+    reg [17:0] overlayColor;
+    reg overlayActive;
+    reg overlayCrush;
+    
+    wire overlayActive_batteryFront;
+    wire overlayActive_batteryBack;
+    wire overlayActive_TimerFront;
+    wire overlayActive_TimerBack;
+    wire overlayActive_TimerNumber;
+    wire overlayActive_debug;
+    
+    overlayBatteryFront u_overlayBatteryFront
+    (
+       .screenX       (screenX),
+       .screenY       (screenY),
+       .overlayActive (overlayActive_batteryFront)
+    );     
+    
+    overlayBatteryBack u_overlayBatteryBack
+    (
+       .screenX       (screenX),
+       .screenY       (screenY),
+       .overlayActive (overlayActive_batteryBack)
+    ); 
+    
+    overlayTimerFront u_overlayTimerFront
+    (
+       .screenX       (screenX),
+       .screenY       (screenY),
+       .overlayActive (overlayActive_TimerFront)
+    );     
+    
+    overlayTimerBack u_overlayTimerBack
+    (
+       .screenX       (screenX),
+       .screenY       (screenY),
+       .overlayActive (overlayActive_TimerBack)
+    ); 
+    
+    reg [3:0] timePL = 4'd0;
+    reg [3:0] timePH = 4'd0;
+    reg [3:0] timeSL = 4'd0;
+    reg [3:0] timeSH = 4'd0;
+    reg [3:0] timeML = 4'd0;
+    reg [3:0] timeMH = 4'd0;
+    reg [3:0] timeHL = 4'd0;
+    
+    // Flash the low battery indicator when configured
+    localparam LB_VIS_SHOW  = 2'b00;
+    localparam LB_VIS_BLINK = 2'b01;
+    localparam LB_VIS_HIDE  = 2'b10;
+    localparam LB_VIS_RSVD  = 2'b11;
+
+    typedef enum reg {
+        LBB_HIDE = 1'b0,
+        LBB_SHOW = 1'b1
+    } low_batt_blink_state_t;
+
+    low_batt_blink_state_t LBBState = LBB_HIDE;
+    reg showLowBatt = 0;
+
+    always@(posedge gClk) begin
+        if (runTimer && gPercentEna) begin
+            if (timePL == 4'd9) begin
+               timePH <= timePH + 1'd1;
+               timePL <= 4'd0;
+            end else begin
+               timePL <= timePL + 1'd1;
+            end
+        end
+        
+        if (runTimer && gSecondEna) begin
+            timePL <= 4'd0;
+            timePH <= 4'd0;
+            if (timeSL == 4'd9) begin
+               timeSL <= 4'd0;
+               if (timeSH == 4'd5) begin
+                  timeSH <= 4'd0;
+                  if (timeML == 4'd9) begin
+                     timeML <= 4'd0;
+                     if (timeMH == 4'd5) begin
+                        timeMH <= 4'd0;
+                        if (timeHL == 4'd9) begin
+                           timePL <= 4'd9;
+                           timePH <= 4'd9;
+                           timeSL <= 4'd9;
+                           timeSH <= 4'd5;
+                           timeML <= 4'd9;
+                           timeMH <= 4'd5;
+                           timeHL <= 4'd9;
+                        end else begin
+                           timeHL <= timeHL + 1'd1;
+                        end
+                     end else begin
+                        timeMH <= timeMH + 1'd1;
+                     end
+                  end else begin
+                     timeML <= timeML + 1'd1;
+                  end
+               end else begin
+                  timeSH <= timeSH + 1'd1;
+               end
+            end else begin
+               timeSL <= timeSL + 1'd1;
+            end
+        end
+        
+        if (resetTimer) begin
+            timePL <= 4'd0;
+            timePH <= 4'd0;
+            timeSL <= 4'd0;
+            timeSH <= 4'd0;
+            timeML <= 4'd0;
+            timeMH <= 4'd0;
+            timeHL <= 4'd0;
+        end
+
+        if ( lowBattDispMode == LB_VIS_BLINK ) begin
+            if (gSecondEna == 1) begin
+                case (LBBState)
+                    LBB_HIDE: begin
+                        LBBState <= LBB_SHOW;
+                    end
+
+                    LBB_SHOW: begin
+                        LBBState <= LBB_HIDE;
+                    end
+                endcase
+            end
+
+            showLowBatt <= (LBBState == LBB_SHOW);
+        end else if ( lowBattDispMode == LB_VIS_HIDE ) begin
+            LBBState <= LBB_HIDE;
+            showLowBatt <= 0;
+        end else begin
+            LBBState <= LBB_HIDE;
+            showLowBatt <= ((lowBattDispMode == LB_VIS_SHOW) || (lowBattDispMode == LB_VIS_RSVD));
+        end
+
+
+    end
+    
+    wire [1:0] screenXNumber = (screenX >=  4 && screenX <=  6) ? (screenX -  4) :
+                               (screenX >=  8 && screenX <=  8) ? (screenX -  8) :
+                               (screenX >= 10 && screenX <= 13) ? (screenX - 10) :
+                               (screenX >= 14 && screenX <= 17) ? (screenX - 14) :
+                               (screenX >= 18 && screenX <= 18) ? (screenX - 18) :
+                               (screenX >= 20 && screenX <= 23) ? (screenX - 20) :
+                               (screenX >= 24 && screenX <= 27) ? (screenX - 24) :
+                               (screenX >= 28 && screenX <= 28) ? (screenX - 28) :
+                               (screenX >= 30 && screenX <= 33) ? (screenX - 30) :
+                               (screenX >= 34 && screenX <= 37) ? (screenX - 34) :
+                               2'd3;
+
+    wire [2:0] screenYNumber = (screenY >= 8 && screenY <= 12) ? (screenY - 8) :
+                               3'd7;
+   
+    wire [3:0] screenNumber =  (screenX >=  4 && screenX <=  6) ? timeHL :
+                               (screenX >=  8 && screenX <=  8) ? 4'd10 :
+                               (screenX >= 10 && screenX <= 13) ? timeMH :
+                               (screenX >= 14 && screenX <= 17) ? timeML :
+                               (screenX >= 18 && screenX <= 18) ? 4'd10 :
+                               (screenX >= 20 && screenX <= 23) ? timeSH :
+                               (screenX >= 24 && screenX <= 27) ? timeSL :
+                               (screenX >= 28 && screenX <= 28) ? 4'd11 :
+                               (screenX >= 30 && screenX <= 33) ? timePH :
+                               (screenX >= 34 && screenX <= 37) ? timePL :
+                               4'd15;
+   
+    overlayTimerNumber u_overlayTimerNumber
+    (
+       .screenX       (screenXNumber),
+       .screenY       (screenYNumber),
+       .number        (screenNumber),
+       .overlayActive (overlayActive_TimerNumber)
+    ); 
+    
+    
+    
+   wire [1:0] debugXNumber = (screenX >=  0 && screenX <=  3) ? (screenX -  0) :
+                             (screenX >=  4 && screenX <=  7) ? (screenX -  4) :
+                             (screenX >=  8 && screenX <= 11) ? (screenX -  8) :
+                             (screenX >= 12 && screenX <= 15) ? (screenX - 12) :
+                             (screenX >= 16 && screenX <= 19) ? (screenX - 16) :
+                             (screenX >= 20 && screenX <= 23) ? (screenX - 20) :
+                             (screenX >= 24 && screenX <= 27) ? (screenX - 24) :
+                             (screenX >= 28 && screenX <= 31) ? (screenX - 28) :
+                             2'd3;
+
+    wire [2:0] debugYNumber = (screenY >= 136) ? (screenY - 136) :
+                               3'd7;
+   
+    wire [3:0] debugNumber =  (screenX >=  0 && screenX <=  3) ? debug_system[31:28] :
+                              (screenX >=  4 && screenX <=  7) ? debug_system[27:24] :
+                              (screenX >=  8 && screenX <= 11) ? debug_system[23:20] :
+                              (screenX >= 12 && screenX <= 15) ? debug_system[19:16] :
+                              (screenX >= 16 && screenX <= 19) ? debug_system[15:12] :
+                              (screenX >= 20 && screenX <= 23) ? debug_system[11: 8] :
+                              (screenX >= 24 && screenX <= 27) ? debug_system[ 7: 4] :
+                              (screenX >= 28 && screenX <= 31) ? debug_system[ 3: 0] :
+                              4'd15;
+   
+    overlayDebug u_overlayDebug
+    (
+       .screenX       (debugXNumber),
+       .screenY       (debugYNumber),
+       .number        (debugNumber),
+       .overlayActive (overlayActive_debug)
+    ); 
+    
+    
+    wire osdTransparent = (hWrBurstQ2 == 16'hF81F) ? 1'd1 : 1'd0;
+
+    always@(posedge hClk)
+    begin
+        overlayColor  <= {hWrBurstQ2[4:0],hWrBurstQ2[0],hWrBurstQ2[10:6],hWrBurstQ2[6],hWrBurstQ2[15:11],hWrBurstQ2[11]};
+        overlayActive <= hDrawOSD & ~osdTransparent;  
+        overlayCrush  <= hDrawOSD & osdTransparent;
+        
+        if (~hDrawOSD) begin
+            if (debug_system_on && overlayActive_debug) begin
+               overlayColor  <= {6'h00, 6'h00, 6'h00}; // black
+               overlayActive <= 1'b1;
+            end else if (debug_system_on && screenX <= 31 && screenY >= 136) begin
+               overlayColor  <= {6'h3F, 6'h3F, 6'h3F}; // white
+               overlayActive <= 1'b1;            
+            end else if (voltageLow && showLowBatt && overlayActive_batteryFront) begin
+               overlayColor  <= {6'h00, 6'h00, 6'h3F}; // red
+               overlayActive <= 1'b1;
+            end else if (showTimer && (overlayActive_TimerFront || overlayActive_TimerNumber)) begin
+               overlayColor  <= {6'h3F, 6'h3F, 6'h3F}; // white
+               overlayActive <= 1'b1;
+            end else if ((voltageLow && showLowBatt && overlayActive_batteryBack) || (showTimer && overlayActive_TimerBack)) begin
+               overlayCrush  <= 1'b1;
+            end
+        end
+    end
+
+    // High = Blue
+    // Mid = Green
+    // LSBs == Red
+
+    wire hValidCorrected;
+    wire hHsyncCorrected;
+    wire hVsyncCorrected;
+    wire [17:0] hColorPixelCorrected;
+    wire [17:0] hColorPixelUVCCorrected;
+
+    color_correction u_color_correction(
+        .hClk(hClk),
+        .hValid(gb_lcd_clkena),
+        .hHsync(gb_lcd_mode[1]),
+        .hVsync(gb_lcd_vsync),
+        .hCorrectLCD(colorCorrectionEnableLCD),
+        .hCorrectUVC(colorCorrectionEnableUVC),
+        .hColorPixel(psel),
+        .hValidCorrected(hValidCorrected),
+        .hHsyncCorrected(hHsyncCorrected),
+        .hVsyncCorrected(hVsyncCorrected),
+        .hColorPixelCorrected(hColorPixelCorrected),
+        .hColorPixelUVCCorrected(hColorPixelUVCCorrected)
+    );
+    
+    wire [17:0] hColorPixelLCD = overlayCrush ? {2'd0,hColorPixelCorrected[17:14],2'd0,hColorPixelCorrected[11:8],2'd0,hColorPixelCorrected[5:2]} : 
+                                 overlayActive ? overlayColor : hColorPixelCorrected;
+                                 
+    wire [17:0] hColorPixelUVC = overlayCrush ? {2'd0,hColorPixelUVCCorrected[17:14],2'd0,hColorPixelUVCCorrected[11:8],2'd0,hColorPixelUVCCorrected[5:2]} : 
+                                 overlayActive ? overlayColor : hColorPixelUVCCorrected;
+
+    ST7785_panel_master u_ST7785_panel_master(
+        .gClk(gClk),
+        .nRST(LCD_INIT_DONE),
+        .hClk(hClk),
+        .hValid(hValidCorrected),
+        .hHsync(hHsyncCorrected),
+        .hVsync(hVsyncCorrected),
+        .hColorPixel(hColorPixelLCD),
+        .hColorPixelUVC(hColorPixelUVC),
+
+        .lcd_on(gb_lcd_on),
+        .LCD_EN(LCD_EN),
+        .LCD_DE(LCD_ENABLE),
+        .LCD_HSYNC(LCD_HSYNC),
+        .LCD_VSYNC(LCD_VSYNC),
+        .LCD_GENLOCK(LCD_GENLOCK),
+        .LCD_DB(LCD_DB),
+        .LCD_ENABLE_UVC(LCD_ENABLE_UVC),
+        .LCD_DB_UVC(LCD_DB_UVC)
+    );
+
+endmodule
+
+module color_correction(
+    input                     hClk,
+
+    input                     hCorrectLCD,
+    input                     hCorrectUVC,
+
+    input                     hValid,
+    input                     hHsync,
+    input                     hVsync,
+    input       [17:0]        hColorPixel,
+
+    output  reg               hValidCorrected,
+    output  reg               hHsyncCorrected,
+    output  reg               hVsyncCorrected,
+    output  reg [17:0]        hColorPixelCorrected,
+    output  reg [17:0]        hColorPixelUVCCorrected
+);
+
+    wire [5:0] red = hColorPixel[5:0];
+    wire [5:0] green = hColorPixel[11:6];
+    wire [5:0] blue = hColorPixel[17:12];
+
+    wire [9:0] r10 = (red * 'd13) + (green * 'd2) + blue; // 999
+    wire [7:0] g8 = (green * 'd3) + blue; // 252
+    wire [9:0] b10 = (red * 'd3) + (green * 'd2) + (blue * 'd11); // 1008
+
+    wire [15:0] rlcd1 = red[5:1]  * 'd216  + green[5:1] * 'd30;
+    wire [15:0] rlcd2 = blue[5:1] * 'd25;
+    wire [15:0] rlcd3 = ( rlcd1 < rlcd2 ) ? 'd0 : rlcd1 - rlcd2;
+    wire [15:0] glcd = red[5:1] * 'd39  + green[5:1] * 'd137 +  blue[5:1] * 'd24;//620 + 1054 + 217 = 1891
+    wire [15:0] blcd = red[5:1] * 'd21  + green[5:1] * 'd24 +  blue[5:1] * 'd125;//620 + 1054 + 217 = 1891
+
+    wire [5:0] blcdc = blcd[13] ? 6'h3F : blcd[12:7];
+    wire [5:0] glcdc = glcd[13] ? 6'h3F : glcd[12:7];
+    wire [5:0] rlcdc = rlcd3[13] ? 6'h3F : rlcd3[12:7];
+
+    always@(posedge hClk)
+    begin
+        hValidCorrected <= hValid;
+        hHsyncCorrected <= hHsync;
+        hVsyncCorrected <= hVsync;
+        hColorPixelCorrected    <= ~hCorrectLCD ? {blue, green, red} : {blcdc, glcdc, rlcdc};
+        hColorPixelUVCCorrected <= ~hCorrectUVC ? {blue, green, red} : {b10[9:4], g8[7:2], r10[9:4]};
+    end
+
+endmodule

ModRetro_oss-chromatic-console-fpga/esp32t/src/rtl/BSP/vid_system_top.v

@@ -0,0 +1,484 @@
+// vid_system_top.v
+
+module vid_system_top #(parameter ISSIMU=0)
+(
+    input               gClk,
+    input               hClk,
+    input               pClk,
+    input               reset,
+
+    input               BTN_MENU,
+    output reg          slideOutActive,
+
+    output [5:0]        LCD_DB,
+    output              LCD_ENABLE_UVC,
+    output [17:0]       LCD_DB_UVC,
+    output              LCD_DOTCLK,
+    output              LCD_ENABLE,
+    output              LCD_HSYNC,
+    output              LCD_RESET,
+    output              LCD_SPI_CSX,
+    output              LCD_SPI_SCLK,
+    output              LCD_SPI_SDA,
+    input               LCD_TE,
+    input               LCD_EN,
+    output              LCD_GENLOCK,
+    output              LCD_VSYNC,
+
+    input               frameBlendEnable,
+    input               colorCorrectionEnableLCD,
+    input               colorCorrectionEnableUVC,
+    input               voltageLow,
+    input [1:0]         lowBattDispMode,
+    input               showTimer,
+    input               runTimer,
+    input               resetTimer,
+    input               gSecondEna,
+    input               gPercentEna,
+    input [31:0]        debug_system,
+    input               debug_system_on,
+
+    output              hGBNewLine,
+    output reg [22:0]   hGBAddress,
+    output              hGBWrite,
+    output  [15:0]      hGBData,
+
+    output              hValid,
+    output              hHsync,
+    output              hVsync,
+    input [15:0]        hWrBurstQ,
+    input [15:0]        hWrBurstQ2,
+    output  reg         hDrawOSD,
+
+    output              LCD_INIT_DONE,
+    input               gb_lcd_clkena,
+    input [14:0]        gb_lcd_data,
+    input [1:0]         gb_lcd_mode,
+    input               gb_lcd_on,
+    input               gb_lcd_vsync
+
+);
+
+    ODDR u_ODDR(
+        .Q0(LCD_DOTCLK),
+        .Q1(),
+        .D0(1'd1),
+        .D1(1'd0),
+        .TX(1'd1),
+        .CLK(gClk)
+    );
+
+
+    ST7785_init #(ISSIMU)
+    u_ST7785_init(
+        .clk(pClk),
+        .reset(reset),
+        .LCD_CS(LCD_SPI_CSX),
+        .LCD_SCK(LCD_SPI_SCLK),
+        .LCD_SDA_SDI(LCD_SPI_SDA),
+        .LCD_RST(LCD_RESET),
+        .LCD_INIT_DONE(LCD_INIT_DONE)
+    );
+
+    wire [14:0] hColorPixel;
+    assign hHsync = gb_lcd_mode[1];
+    assign hVsync = gb_lcd_vsync;
+
+
+    reg hHsync_r1;
+    reg hVsync_r1;
+    always@(posedge hClk)
+    begin
+        hHsync_r1 <= hHsync;
+        hVsync_r1 <= hVsync;
+    end
+
+    reg hGBFrameBufferNum;
+    always@(posedge hClk)
+    begin
+        if(hVsync&~hVsync_r1)
+        begin
+           hGBAddress        <= 23'h10000;
+        end
+        else
+            if(hGBNewLine&~hVsync)
+                hGBAddress <= hGBAddress + 'd320;
+    end
+
+    assign  hGBWrite    = gb_lcd_clkena;
+    assign  hGBNewLine  = ~hHsync&hHsync_r1;
+    assign  hGBData     = {1'd0, gb_lcd_data[14:0]};
+
+    reg [7:0] screenX;
+    reg [7:0] screenY;
+    always@(posedge hClk) begin
+        if (hHsync&~hHsync_r1) begin
+            screenX <= 8'd0;
+            screenY <= screenY + 1'd1;
+        end else if (gb_lcd_clkena) begin
+            screenX <= screenX + 1'd1;
+        end
+
+        if(hVsync&~hVsync_r1) begin
+            hDrawOSD <= ~BTN_MENU;
+            screenY  <= 8'd0;
+        end
+    end
+        
+/* 50% blend
+    wire [6:0] sum_r = {hWrBurstQ[4:0],1'd0} + {gb_lcd_data[4:0],1'd0};
+    wire [6:0] sum_g = {hWrBurstQ[9:5],1'd0} + {gb_lcd_data[9:5],1'd0};
+    wire [6:0] sum_b = {hWrBurstQ[14:10],1'd0} + {gb_lcd_data[14:10],1'd0};
+*/
+/* 25% blend
+*/
+    wire [6:0] sum_r = hWrBurstQ[4:0] + {gb_lcd_data[4:0],1'd0} + gb_lcd_data[4:0];
+    wire [6:0] sum_g = hWrBurstQ[9:5] + {gb_lcd_data[9:5],1'd0} + gb_lcd_data[9:5];
+    wire [6:0] sum_b = hWrBurstQ[14:10] + {gb_lcd_data[14:10],1'd0} + gb_lcd_data[14:10];
+/* 12.5% blend
+*/
+    wire [5:0]  game_r  =   frameBlendEnable ? sum_r[6:1] : {gb_lcd_data[4:0],1'b0};
+    wire [5:0]  game_g  =   frameBlendEnable ? sum_g[6:1] : {gb_lcd_data[9:5],1'b0};
+    wire [5:0]  game_b  =   frameBlendEnable ? sum_b[6:1] : {gb_lcd_data[14:10],1'b0};
+    
+    wire [17:0] psel = {game_b,game_g,game_r};
+
+    // OSD and overlay
+    reg [17:0] overlayColor;
+    reg overlayActive;
+    reg overlayCrush;
+    
+    wire overlayActive_batteryFront;
+    wire overlayActive_batteryBack;
+    wire overlayActive_TimerFront;
+    wire overlayActive_TimerBack;
+    wire overlayActive_TimerNumber;
+    wire overlayActive_debug;
+    
+    overlayBatteryFront u_overlayBatteryFront
+    (
+       .screenX       (screenX),
+       .screenY       (screenY),
+       .overlayActive (overlayActive_batteryFront)
+    );     
+    
+    overlayBatteryBack u_overlayBatteryBack
+    (
+       .screenX       (screenX),
+       .screenY       (screenY),
+       .overlayActive (overlayActive_batteryBack)
+    ); 
+    
+    overlayTimerFront u_overlayTimerFront
+    (
+       .screenX       (screenX),
+       .screenY       (screenY),
+       .overlayActive (overlayActive_TimerFront)
+    );     
+    
+    overlayTimerBack u_overlayTimerBack
+    (
+       .screenX       (screenX),
+       .screenY       (screenY),
+       .overlayActive (overlayActive_TimerBack)
+    ); 
+    
+    reg [3:0] timePL = 4'd0;
+    reg [3:0] timePH = 4'd0;
+    reg [3:0] timeSL = 4'd0;
+    reg [3:0] timeSH = 4'd0;
+    reg [3:0] timeML = 4'd0;
+    reg [3:0] timeMH = 4'd0;
+    reg [3:0] timeHL = 4'd0;
+    
+    // Flash the low battery indicator when configured
+    localparam LB_VIS_SHOW  = 2'b00;
+    localparam LB_VIS_BLINK = 2'b01;
+    localparam LB_VIS_HIDE  = 2'b10;
+    localparam LB_VIS_RSVD  = 2'b11;
+
+    typedef enum reg {
+        LBB_HIDE = 1'b0,
+        LBB_SHOW = 1'b1
+    } low_batt_blink_state_t;
+
+    low_batt_blink_state_t LBBState = LBB_HIDE;
+    reg showLowBatt = 0;
+
+    always@(posedge gClk) begin
+        if (runTimer && gPercentEna) begin
+            if (timePL == 4'd9) begin
+               timePH <= timePH + 1'd1;
+               timePL <= 4'd0;
+            end else begin
+               timePL <= timePL + 1'd1;
+            end
+        end
+        
+        if (runTimer && gSecondEna) begin
+            timePL <= 4'd0;
+            timePH <= 4'd0;
+            if (timeSL == 4'd9) begin
+               timeSL <= 4'd0;
+               if (timeSH == 4'd5) begin
+                  timeSH <= 4'd0;
+                  if (timeML == 4'd9) begin
+                     timeML <= 4'd0;
+                     if (timeMH == 4'd5) begin
+                        timeMH <= 4'd0;
+                        if (timeHL == 4'd9) begin
+                           timePL <= 4'd9;
+                           timePH <= 4'd9;
+                           timeSL <= 4'd9;
+                           timeSH <= 4'd5;
+                           timeML <= 4'd9;
+                           timeMH <= 4'd5;
+                           timeHL <= 4'd9;
+                        end else begin
+                           timeHL <= timeHL + 1'd1;
+                        end
+                     end else begin
+                        timeMH <= timeMH + 1'd1;
+                     end
+                  end else begin
+                     timeML <= timeML + 1'd1;
+                  end
+               end else begin
+                  timeSH <= timeSH + 1'd1;
+               end
+            end else begin
+               timeSL <= timeSL + 1'd1;
+            end
+        end
+        
+        if (resetTimer) begin
+            timePL <= 4'd0;
+            timePH <= 4'd0;
+            timeSL <= 4'd0;
+            timeSH <= 4'd0;
+            timeML <= 4'd0;
+            timeMH <= 4'd0;
+            timeHL <= 4'd0;
+        end
+
+        if ( lowBattDispMode == LB_VIS_BLINK ) begin
+            if (gSecondEna == 1) begin
+                case (LBBState)
+                    LBB_HIDE: begin
+                        LBBState <= LBB_SHOW;
+                    end
+
+                    LBB_SHOW: begin
+                        LBBState <= LBB_HIDE;
+                    end
+                endcase
+            end
+
+            showLowBatt <= (LBBState == LBB_SHOW);
+        end else if ( lowBattDispMode == LB_VIS_HIDE ) begin
+            LBBState <= LBB_HIDE;
+            showLowBatt <= 0;
+        end else begin
+            LBBState <= LBB_HIDE;
+            showLowBatt <= ((lowBattDispMode == LB_VIS_SHOW) || (lowBattDispMode == LB_VIS_RSVD));
+        end
+
+
+    end
+    
+    wire [1:0] screenXNumber = (screenX >=  4 && screenX <=  6) ? (screenX -  4) :
+                               (screenX >=  8 && screenX <=  8) ? (screenX -  8) :
+                               (screenX >= 10 && screenX <= 13) ? (screenX - 10) :
+                               (screenX >= 14 && screenX <= 17) ? (screenX - 14) :
+                               (screenX >= 18 && screenX <= 18) ? (screenX - 18) :
+                               (screenX >= 20 && screenX <= 23) ? (screenX - 20) :
+                               (screenX >= 24 && screenX <= 27) ? (screenX - 24) :
+                               (screenX >= 28 && screenX <= 28) ? (screenX - 28) :
+                               (screenX >= 30 && screenX <= 33) ? (screenX - 30) :
+                               (screenX >= 34 && screenX <= 37) ? (screenX - 34) :
+                               2'd3;
+
+    wire [2:0] screenYNumber = (screenY >= 8 && screenY <= 12) ? (screenY - 8) :
+                               3'd7;
+   
+    wire [3:0] screenNumber =  (screenX >=  4 && screenX <=  6) ? timeHL :
+                               (screenX >=  8 && screenX <=  8) ? 4'd10 :
+                               (screenX >= 10 && screenX <= 13) ? timeMH :
+                               (screenX >= 14 && screenX <= 17) ? timeML :
+                               (screenX >= 18 && screenX <= 18) ? 4'd10 :
+                               (screenX >= 20 && screenX <= 23) ? timeSH :
+                               (screenX >= 24 && screenX <= 27) ? timeSL :
+                               (screenX >= 28 && screenX <= 28) ? 4'd11 :
+                               (screenX >= 30 && screenX <= 33) ? timePH :
+                               (screenX >= 34 && screenX <= 37) ? timePL :
+                               4'd15;
+   
+    overlayTimerNumber u_overlayTimerNumber
+    (
+       .screenX       (screenXNumber),
+       .screenY       (screenYNumber),
+       .number        (screenNumber),
+       .overlayActive (overlayActive_TimerNumber)
+    ); 
+    
+    
+    
+   wire [1:0] debugXNumber = (screenX >=  0 && screenX <=  3) ? (screenX -  0) :
+                             (screenX >=  4 && screenX <=  7) ? (screenX -  4) :
+                             (screenX >=  8 && screenX <= 11) ? (screenX -  8) :
+                             (screenX >= 12 && screenX <= 15) ? (screenX - 12) :
+                             (screenX >= 16 && screenX <= 19) ? (screenX - 16) :
+                             (screenX >= 20 && screenX <= 23) ? (screenX - 20) :
+                             (screenX >= 24 && screenX <= 27) ? (screenX - 24) :
+                             (screenX >= 28 && screenX <= 31) ? (screenX - 28) :
+                             2'd3;
+
+    wire [2:0] debugYNumber = (screenY >= 136) ? (screenY - 136) :
+                               3'd7;
+   
+    wire [3:0] debugNumber =  (screenX >=  0 && screenX <=  3) ? debug_system[31:28] :
+                              (screenX >=  4 && screenX <=  7) ? debug_system[27:24] :
+                              (screenX >=  8 && screenX <= 11) ? debug_system[23:20] :
+                              (screenX >= 12 && screenX <= 15) ? debug_system[19:16] :
+                              (screenX >= 16 && screenX <= 19) ? debug_system[15:12] :
+                              (screenX >= 20 && screenX <= 23) ? debug_system[11: 8] :
+                              (screenX >= 24 && screenX <= 27) ? debug_system[ 7: 4] :
+                              (screenX >= 28 && screenX <= 31) ? debug_system[ 3: 0] :
+                              4'd15;
+   
+    overlayDebug u_overlayDebug
+    (
+       .screenX       (debugXNumber),
+       .screenY       (debugYNumber),
+       .number        (debugNumber),
+       .overlayActive (overlayActive_debug)
+    ); 
+    
+    
+    wire osdTransparent = (hWrBurstQ2 == 16'hF81F) ? 1'd1 : 1'd0;
+
+    always@(posedge hClk)
+    begin
+        overlayColor  <= {hWrBurstQ2[4:0],hWrBurstQ2[0],hWrBurstQ2[10:6],hWrBurstQ2[6],hWrBurstQ2[15:11],hWrBurstQ2[11]};
+        overlayActive <= hDrawOSD & ~osdTransparent;  
+        overlayCrush  <= hDrawOSD & osdTransparent;
+        
+        if (~hDrawOSD) begin
+            if (debug_system_on && overlayActive_debug) begin
+               overlayColor  <= {6'h00, 6'h00, 6'h00}; // black
+               overlayActive <= 1'b1;
+            end else if (debug_system_on && screenX <= 31 && screenY >= 136) begin
+               overlayColor  <= {6'h3F, 6'h3F, 6'h3F}; // white
+               overlayActive <= 1'b1;            
+            end else if (voltageLow && showLowBatt && overlayActive_batteryFront) begin
+               overlayColor  <= {6'h00, 6'h00, 6'h3F}; // red
+               overlayActive <= 1'b1;
+            end else if (showTimer && (overlayActive_TimerFront || overlayActive_TimerNumber)) begin
+               overlayColor  <= {6'h3F, 6'h3F, 6'h3F}; // white
+               overlayActive <= 1'b1;
+            end else if ((voltageLow && showLowBatt && overlayActive_batteryBack) || (showTimer && overlayActive_TimerBack)) begin
+               overlayCrush  <= 1'b1;
+            end
+        end
+    end
+
+    // High = Blue
+    // Mid = Green
+    // LSBs == Red
+
+    wire hValidCorrected;
+    wire hHsyncCorrected;
+    wire hVsyncCorrected;
+    wire [17:0] hColorPixelCorrected;
+    wire [17:0] hColorPixelUVCCorrected;
+
+    color_correction u_color_correction(
+        .hClk(hClk),
+        .hValid(gb_lcd_clkena),
+        .hHsync(gb_lcd_mode[1]),
+        .hVsync(gb_lcd_vsync),
+        .hCorrectLCD(colorCorrectionEnableLCD),
+        .hCorrectUVC(colorCorrectionEnableUVC),
+        .hColorPixel(psel),
+        .hValidCorrected(hValidCorrected),
+        .hHsyncCorrected(hHsyncCorrected),
+        .hVsyncCorrected(hVsyncCorrected),
+        .hColorPixelCorrected(hColorPixelCorrected),
+        .hColorPixelUVCCorrected(hColorPixelUVCCorrected)
+    );
+    
+    wire [17:0] hColorPixelLCD = overlayCrush ? {2'd0,hColorPixelCorrected[17:14],2'd0,hColorPixelCorrected[11:8],2'd0,hColorPixelCorrected[5:2]} : 
+                                 overlayActive ? overlayColor : hColorPixelCorrected;
+                                 
+    wire [17:0] hColorPixelUVC = overlayCrush ? {2'd0,hColorPixelUVCCorrected[17:14],2'd0,hColorPixelUVCCorrected[11:8],2'd0,hColorPixelUVCCorrected[5:2]} : 
+                                 overlayActive ? overlayColor : hColorPixelUVCCorrected;
+
+    ST7785_panel_master u_ST7785_panel_master(
+        .gClk(gClk),
+        .nRST(LCD_INIT_DONE),
+        .hClk(hClk),
+        .hValid(hValidCorrected),
+        .hHsync(hHsyncCorrected),
+        .hVsync(hVsyncCorrected),
+        .hColorPixel(hColorPixelLCD),
+        .hColorPixelUVC(hColorPixelUVC),
+
+        .lcd_on(gb_lcd_on),
+        .LCD_EN(LCD_EN),
+        .LCD_DE(LCD_ENABLE),
+        .LCD_HSYNC(LCD_HSYNC),
+        .LCD_VSYNC(LCD_VSYNC),
+        .LCD_GENLOCK(LCD_GENLOCK),
+        .LCD_DB(LCD_DB),
+        .LCD_ENABLE_UVC(LCD_ENABLE_UVC),
+        .LCD_DB_UVC(LCD_DB_UVC)
+    );
+
+endmodule
+
+module color_correction(
+    input                     hClk,
+
+    input                     hCorrectLCD,
+    input                     hCorrectUVC,
+
+    input                     hValid,
+    input                     hHsync,
+    input                     hVsync,
+    input       [17:0]        hColorPixel,
+
+    output  reg               hValidCorrected,
+    output  reg               hHsyncCorrected,
+    output  reg               hVsyncCorrected,
+    output  reg [17:0]        hColorPixelCorrected,
+    output  reg [17:0]        hColorPixelUVCCorrected
+);
+
+    wire [5:0] red = hColorPixel[5:0];
+    wire [5:0] green = hColorPixel[11:6];
+    wire [5:0] blue = hColorPixel[17:12];
+
+    wire [9:0] r10 = (red * 'd13) + (green * 'd2) + blue; // 999
+    wire [7:0] g8 = (green * 'd3) + blue; // 252
+    wire [9:0] b10 = (red * 'd3) + (green * 'd2) + (blue * 'd11); // 1008
+
+    wire [15:0] rlcd1 = red[5:1]  * 'd216  + green[5:1] * 'd30;
+    wire [15:0] rlcd2 = blue[5:1] * 'd25;
+    wire [15:0] rlcd3 = ( rlcd1 < rlcd2 ) ? 'd0 : rlcd1 - rlcd2;
+    wire [15:0] glcd = red[5:1] * 'd39  + green[5:1] * 'd137 +  blue[5:1] * 'd24;//620 + 1054 + 217 = 1891
+    wire [15:0] blcd = red[5:1] * 'd21  + green[5:1] * 'd24 +  blue[5:1] * 'd125;//620 + 1054 + 217 = 1891
+
+    wire [5:0] blcdc = blcd[13] ? 6'h3F : blcd[12:7];
+    wire [5:0] glcdc = glcd[13] ? 6'h3F : glcd[12:7];
+    wire [5:0] rlcdc = rlcd3[13] ? 6'h3F : rlcd3[12:7];
+
+    always@(posedge hClk)
+    begin
+        hValidCorrected <= hValid;
+        hHsyncCorrected <= hHsync;
+        hVsyncCorrected <= hVsync;
+        hColorPixelCorrected    <= ~hCorrectLCD ? {blue, green, red} : {blcdc, glcdc, rlcdc};
+        hColorPixelUVCCorrected <= ~hCorrectUVC ? {blue, green, red} : {b10[9:4], g8[7:2], r10[9:4]};
+    end
+
+endmodule

ModRetro_oss-chromatic-console-fpga/esp32t/src/rtl/BSP/vid_tpg.v

@@ -0,0 +1,69 @@
+// vid_tpg.v
+
+module vid_tpg(
+    input               hclk,
+    input               reset,
+    output  reg [14:0]  color_pixel,
+    output  reg         vs,
+    output  reg         hs,
+    output  reg         valid,
+    
+    output  reg         hGBNewLine,
+    output  reg [22:0]  hGBAddress,
+    output  reg         hGBWrite
+);
+
+    reg [11:0] xcounter;
+    reg [11:0] ycounter;
+    reg [1:0] frameCnt; 
+    
+    always@(posedge hclk) begin : Timing
+        hGBWrite   <= 1'b0;
+        hGBNewLine <= 1'b0;
+    
+        if(reset)
+        begin
+            xcounter <= 'd0;
+            ycounter <= 'd0; 
+            frameCnt <= 'd0;       
+        end
+        else
+        begin
+            if(xcounter < 1824-1)
+                xcounter <= xcounter + 1'd1;
+            else
+            begin
+                hGBAddress <= hGBAddress + 320;
+                xcounter   <= 'd0;
+                if(ycounter < 154)
+                    ycounter <= ycounter + 1'd1;
+                else begin
+                    ycounter <= 'd0;
+                    frameCnt <= frameCnt + 1;
+                    if (frameCnt == 2) frameCnt <= 'd0;
+                    hGBAddress <= 23'h010000;
+                end
+            end
+        end
+        
+        if (valid)
+            hGBWrite   <= 1'b1;
+        
+        if (xcounter == 640 && ycounter < 144)
+            hGBNewLine <= 1'b1;
+    end
+
+    always@(posedge hclk)
+    begin
+        case (frameCnt)
+            0 : color_pixel <= {5'b0, 5'b0, ycounter[4:0]};//gb_lcd_data;
+            1 : color_pixel <= {5'b0, ycounter[4:0], 5'b0};//gb_lcd_data;
+            2 : color_pixel <= {ycounter[4:0], 5'b0, 5'b0};//gb_lcd_data;
+        endcase
+        
+        vs <= ycounter == 12'd153;//gb_lcd_vsync;
+        hs <= xcounter < 1006;//gb_lcd_mode[1];
+        valid <= (xcounter >= 1) && (xcounter <= 640) && xcounter[0] && xcounter[1] && (ycounter < 144);//gb_lcd_clkena;
+    end
+
+endmodule

ModRetro_oss-chromatic-console-fpga/esp32t/src/rtl/EMU/CORE/BootROMs/README.md

@@ -0,0 +1,9 @@
+# Building the BootROM
+
+1. Install RGBDS v0.6 (see https://rgbds.gbdev.io/)
+
+2. Ensure that RGBDS is on your path.
+
+3. Run `make && make bootroms && make clean`
+
+Note: The BootROM is restricted to 2048 bytes to limit impact on BlockRAM.

ModRetro_oss-chromatic-console-fpga/esp32t/src/rtl/EMU/CORE/BootROMs/cgb_boot_hex.txt

@@ -0,0 +1,128 @@
+31 FE FF CD B4 04 26 FE 0E A0 22 0D 20 FC 0E 10 
+21 30 FF 22 2F 0D 20 FB E0 C1 E0 80 3E 80 E0 26 
+E0 11 3E F3 E0 12 E0 25 3E 77 E0 24 3E FC E0 47 
+11 04 01 21 10 80 1A 47 CD 88 04 13 7B FE 34 20 
+F5 CD 1D 05 3E 01 E0 4F CD B4 04 CD 64 07 CC E1 
+04 06 03 21 C2 98 16 03 3E 08 0E 10 CD 7B 00 82 
+0D 20 F9 D6 2F D5 11 10 00 19 D1 05 20 EC 15 28 
+17 15 3E 37 2E A7 01 01 01 18 E1 F5 3E 01 E0 4F 
+36 08 AF E0 4F F1 22 C9 11 76 04 0E 08 21 81 FF 
+AF 2F 22 22 CD 69 07 1A 13 22 1A 13 22 AF 22 22 
+22 22 0D 20 EC CD 80 06 3E 91 E0 40 CD 64 07 28 
+0C 3E 83 CD B3 04 06 05 CD AC 04 18 24 CD 2A 05 
+3E 01 E0 C2 06 01 CD AC 04 3E 83 CD B3 04 06 05 
+CD AC 04 3E C1 CD B3 04 CD A4 06 21 C2 FF 35 20 
+F7 CD 53 05 CD 5F 07 28 01 04 3E 11 18 10 D0 00 
+98 A0 12 D0 00 80 00 40 00 00 00 00 00 00 E0 50 
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
+00 88 16 36 D1 DB F2 3C 8C 92 3D 5C 58 C9 3E 70 
+1D 59 69 19 35 A8 14 AA 75 95 99 34 6F 15 FF 97 
+4B 90 17 10 39 F7 F6 A2 49 4E 43 68 E0 8B F0 CE 
+0C 29 E8 B7 86 9A 52 01 9D 71 9C BD 5D 6D 67 3F 
+6B B3 46 28 A5 C6 D3 27 61 18 66 6A BF 0D F4 B3 
+46 28 A5 C6 D3 27 61 18 66 6A BF 0D F4 B3 00 04 
+05 23 22 03 1F 0F 0A 05 13 24 87 25 1E 2C 15 20 
+1F 14 05 21 0D 0E 05 1D 05 12 09 03 02 1A 19 19 
+29 2A 1A 2D 2A 2D 24 26 9A 2A 1E 29 22 22 05 2A 
+06 05 21 19 2A 2A 28 02 10 19 2A 2A 05 00 27 24 
+16 19 06 20 0C 24 0B 27 12 27 18 1F 32 11 2E 06 
+1B 00 2F 29 29 00 00 13 22 17 12 1D 42 45 46 41 
+41 52 42 45 4B 45 4B 20 52 2D 55 52 41 52 20 49 
+4E 41 49 4C 49 43 45 20 52 20 20 E8 90 90 90 A0 
+A0 A0 C0 C0 C0 48 48 48 00 00 00 D8 D8 D8 28 28 
+28 60 60 60 D0 D0 D0 80 40 40 20 E0 E0 20 10 10 
+18 20 20 20 E8 E8 E0 20 E0 10 88 10 80 80 40 20 
+20 38 20 20 90 20 20 A0 98 98 48 1E 1E 58 88 88 
+10 20 20 10 20 20 18 E0 E0 00 18 18 00 00 00 08 
+90 B0 90 A0 B0 A0 C0 B0 C0 80 B0 40 88 20 68 DE 
+00 70 DE 20 78 98 B6 48 80 E0 50 20 B8 E0 88 B0 
+10 20 00 10 20 E0 18 E0 18 00 18 E0 20 A8 E0 20 
+18 E0 00 C8 18 E0 00 E0 40 20 18 E0 E0 18 30 20 
+E0 E8 FF 7F BF 32 D0 00 00 00 9F 63 79 42 B0 15 
+CB 04 FF 7F 31 6E 4A 45 00 00 FF 7F EF 1B 00 02 
+00 00 FF 7F 1F 42 F2 1C 00 00 FF 7F 94 52 4A 29 
+00 00 FF 7F FF 03 2F 01 00 00 FF 7F EF 03 D6 01 
+00 00 FF 7F B5 42 C8 3D 00 00 74 7E FF 03 80 01 
+00 00 FF 67 AC 77 13 1A 6B 2D D6 7E FF 4B 75 21 
+00 00 FF 53 5F 4A 52 7E 00 00 FF 4F D2 7E 4C 3A 
+E0 1C ED 03 FF 7F 5F 25 00 00 6A 03 1F 02 FF 03 
+FF 7F FF 7F DF 01 12 01 00 00 1F 23 5F 03 F2 00 
+09 00 FF 7F EA 03 1F 01 00 00 9F 29 1A 00 0C 00 
+00 00 FF 7F 7F 02 1F 00 00 00 FF 7F E0 03 06 02 
+20 01 FF 7F EB 7E 1F 00 00 7C FF 7F FF 3F 00 7E 
+1F 00 FF 7F FF 03 1F 00 00 00 FF 03 1F 00 0C 00 
+00 00 FF 7F 3F 03 93 01 00 00 00 00 00 42 7F 03 
+FF 7F FF 7F 8C 7E 00 7C 00 00 FF 7F EF 1B 80 61 
+00 00 03 90 0F 18 00 78 81 09 12 15 54 93 3C 42 
+B9 A5 B9 A5 42 3C FF 7F 4F 77 C7 22 9F 03 7D 01 
+1D 24 38 6D 00 55 60 6D CD 8B 04 3E 04 0E 00 CB 
+20 F5 CB 11 F1 CB 11 3D 20 F5 79 22 23 22 23 C9 
+E5 21 0F FF CB 86 CB 46 28 FC E1 C9 CD A4 06 05 
+20 FA C9 C9 21 00 80 AF 22 CB 6C 28 FA C9 CD C1 
+04 1A A1 47 1C 1C 1A 1D 1D A1 CB 37 B0 CB 41 28 
+02 CB 37 23 22 CB 31 C9 CD DB 04 CD BE 04 1C 7B 
+C9 11 00 00 21 80 80 1A 13 47 E6 0F 28 08 4F 1A 
+22 23 13 0D 20 F9 CB 30 78 E6 0F 28 0A 4F 1A 13 
+22 23 0D 20 FB 18 E0 11 04 01 0E F0 CD D8 04 C6 
+16 5F CD D8 04 D6 16 5F FE 1C 20 EE 23 11 6E 04 
+0E 08 1A 13 22 23 0D 20 F9 C9 3E 01 E0 4F 16 1A 
+06 02 CD AC 04 21 C0 98 0E 03 7E FE 0F 28 05 34 
+E6 07 28 03 23 18 F3 7D F6 1F 6F 23 0D 20 EB 15 
+20 DE C9 CD 64 07 28 05 3E C1 CD B3 04 06 20 0E 
+20 21 81 FF C5 2A 5F 3A 57 01 21 04 7B E6 1F FE 
+1F 20 01 0D 7B FE E0 38 09 7A E6 03 FE 03 20 02 
+CB A9 7A E6 7C FE 7C 20 02 CB 90 7B 81 22 7A 88 
+22 C1 0D 20 CF CD 80 06 05 20 C4 3E 02 E0 70 21 
+00 D0 CD B7 04 3C CD 94 06 CD 99 06 CD 94 06 AF 
+E0 70 2F E0 00 57 59 2E 0D FA 43 01 CB 7F CC D9 
+05 CB 7F E0 4C F0 80 47 28 02 F0 C1 AF 4F 61 C9 
+21 61 04 4F 06 00 09 7E C9 3E 01 E0 6C CD 04 06 
+CB 7F C4 47 07 CB BF 47 80 80 47 F0 C1 A7 28 05 
+CD D0 05 18 01 78 CD A0 04 CD 5B 06 3E 04 11 08 
+00 2E 7C C9 21 4B 01 7E FE 33 28 05 3D 20 42 18 
+0C 2E 44 2A FE 30 20 39 7E FE 31 20 34 2E 34 0E 
+10 AF 86 2C 0D 20 FB E0 80 47 21 00 02 7D D6 5E 
+C8 2A B8 20 F8 7D D6 42 38 0E E5 7D C6 7A 6F 7E 
+E1 4F FA 37 01 B9 20 E5 7D C6 5D 6F 78 E0 80 7E 
+C9 AF C9 21 D9 02 06 00 4F 09 C9 CD 53 06 1E 00 
+2A E5 21 72 03 4F 09 16 08 0E 6A CD 89 06 E1 CB 
+5B 20 04 1E 08 18 E9 4E 21 72 03 09 16 08 18 05 
+21 81 FF 16 40 1E 00 0E 68 3E 80 B3 E2 0C 2A E2 
+15 20 FB C9 E0 4F 21 EE 00 0E 51 06 05 2A E2 0C 
+05 20 FA C9 FA 43 01 CB 7F C0 3E 20 E0 00 F0 00 
+2F E6 0F C8 2E 00 2C 1F 30 FC 3E 10 E0 00 F0 00 
+2F 17 17 E6 0C 85 6F F0 C1 BD C8 7D E0 C1 C5 D5 
+CD D0 05 CD 53 06 2C 2C 4E 21 73 03 09 3A FE 7F 
+20 02 23 23 F5 2A E5 21 81 FF CD 3D 07 2E 83 CD 
+3D 07 E1 E0 87 2A E5 21 82 FF CD 3D 07 2E 84 CD 
+3D 07 E1 E0 88 F1 28 02 23 23 F0 BB E6 DE 47 2A 
+E6 DE 80 47 FA BC FF CB 97 4E CB 91 89 1F EA BC 
+FF 78 1F EA BB FF 2D 2A E0 BF 2A E0 C0 2A E0 85 
+2A E0 86 CD 80 06 3E 30 E0 C2 D1 C1 C9 11 08 00 
+4B 77 19 0D 20 FB C9 F5 3E 19 EA 10 99 21 2F 99 
+0E 0C 3D 28 08 32 0D 20 F9 2E 0F 18 F5 F1 C9 F0 
+50 CB 47 C9 3E 02 CB 4F C9 E5 CD 5F 07 28 09 21 
+84 04 7B BD 20 02 13 13 E1 C9 00 00 00 00 00 00 
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 

ModRetro_oss-chromatic-console-fpga/esp32t/src/rtl/EMU/CORE/T80/GBse.vhd

@@ -0,0 +1,266 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 300 started tidyup
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- Z80 compatible microprocessor core, synchronous top level with clock enable
+-- Different timing than the original z80
+-- Inputs needs to be synchronous and outputs may glitch
+--
+-- Version : 0240
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0235 : First release
+--
+--      0236 : Added T2Write generic
+--
+--      0237 : Fixed T2Write with wait state
+--
+--      0238 : Updated for T80 interface change
+--
+--      0240 : Updated for T80 interface change
+--
+--      0242 : Updated for T80 interface change
+--
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use work.T80_Pack.all;
+
+use work.pBus_savestates.all;
+use work.pReg_savestates.all;
+
+entity GBse is
+	generic(
+		T2Write : integer := 2;  -- 0 => WR_n active in T3, 1 => WR_n active in T2, Other => WR_n active in T2+T3
+		IOWait : integer := 1   -- 0 => Single cycle I/O, 1 => Std I/O cycle
+	);
+	port(
+		RESET_n           : in     std_logic;
+		CLK_n             : in     std_logic;
+		CLKEN             : in     std_logic;
+		WAIT_n            : in     std_logic;
+		INT_n             : in     std_logic;
+		NMI_n             : in     std_logic;
+		BUSRQ_n           : in     std_logic;
+		M1_n              : out    std_logic;
+		MREQ_n            : buffer std_logic;
+		IORQ_n            : buffer std_logic;
+		RD_n              : buffer std_logic;
+		WR_n              : buffer std_logic;
+		RFSH_n            : out    std_logic;
+		HALT_n            : out    std_logic;
+		BUSAK_n           : out    std_logic;
+		STOP              : out    std_logic;
+        WRITE_CYCLE       : out    std_logic;
+        TSTATE1           : out    std_logic;
+        TSTATE2           : out    std_logic;
+        TSTATE3           : out    std_logic;
+        TSTATE4           : out    std_logic;
+		TSTATEo           : out    std_logic_vector(2 downto 0);
+		A                 : out    std_logic_vector(15 downto 0);
+		DI                : in     std_logic_vector(7 downto 0);
+		DO                : out    std_logic_vector(7 downto 0);
+		isGBC             : in     std_logic; -- Gameboy Color
+		-- savestates              
+		SaveStateBus_Din  : in     std_logic_vector(BUS_buswidth-1 downto 0);
+		SaveStateBus_Adr  : in     std_logic_vector(BUS_busadr-1 downto 0);
+		SaveStateBus_wren : in     std_logic;
+		SaveStateBus_rst  : in     std_logic;
+		SaveStateBus_Dout : out    std_logic_vector(BUS_buswidth-1 downto 0)
+	);
+end GBse;
+
+architecture rtl of GBse is
+
+	signal IntCycle_n   : std_logic;
+	signal NoRead       : std_logic;
+	signal Write        : std_logic;
+	signal IORQ         : std_logic;
+	signal DI_Reg       : std_logic_vector(7 downto 0);
+	signal MCycle       : std_logic_vector(2 downto 0);
+	signal TState       : std_logic_vector(2 downto 0);
+
+	-- savestates
+	type t_reg_wired_or is array(0 to 1) of std_logic_vector(63 downto 0);
+	signal reg_wired_or : t_reg_wired_or;
+	
+	signal SS_GBSE      : std_logic_vector(REG_SAVESTATE_GBSE.upper downto REG_SAVESTATE_GBSE.lower);
+	signal SS_GBSE_BACK : std_logic_vector(REG_SAVESTATE_GBSE.upper downto REG_SAVESTATE_GBSE.lower);
+
+begin
+
+	iREG_SAVESTATE_GBSE : entity work.eReg_Savestate generic map ( REG_SAVESTATE_GBSE ) port map (CLK_n, SaveStateBus_Din, SaveStateBus_Adr, SaveStateBus_wren, SaveStateBus_rst, reg_wired_or(0), SS_GBSE_BACK, SS_GBSE);  
+    WRITE_CYCLE               <= Write;
+    TSTATE1                   <= '1' when TState = "001" else '0';
+    TSTATE2                   <= '1' when TState = "010" else '0';
+    TSTATE3                   <= '1' when TState = "011" else '0';
+    TSTATE4                   <= '1' when TState = "100" else '0';
+    TSTATEo                   <= TState;
+	SS_GBSE_BACK(0)           <= RD_n;
+	SS_GBSE_BACK(1)           <= WR_n;
+	SS_GBSE_BACK(2)           <= IORQ_n;
+	SS_GBSE_BACK(3)           <= MREQ_n;
+	SS_GBSE_BACK(11 downto 4) <= DI_Reg;
+	
+	process (reg_wired_or)
+		variable wired_or : std_logic_vector(63 downto 0);
+	begin
+		wired_or := reg_wired_or(0);
+		for i in 1 to (reg_wired_or'length - 1) loop
+			wired_or := wired_or or reg_wired_or(i);
+		end loop;
+		SaveStateBus_Dout <= wired_or;
+	end process;
+
+	u0 : T80
+		generic map
+	(
+			Mode      => 3,
+			IOWait    => IOWait,
+			Flag_S    => 0,
+			Flag_P    => 0,
+			Flag_X    => 0,
+			Flag_Y    => 0,
+			Flag_C    => 4,
+			Flag_H    => 5,
+			Flag_N    => 6,
+			Flag_Z    => 7
+		)
+		port map(
+			CEN        => CLKEN,
+			M1_n       => M1_n,
+			IORQ       => IORQ,
+			NoRead     => NoRead,
+			Write      => Write,
+			RFSH_n     => RFSH_n,
+			HALT_n     => HALT_n,
+			Stop       => STOP,
+			WAIT_n     => Wait_n,
+			INT_n      => INT_n,
+			NMI_n      => NMI_n,
+			RESET_n    => RESET_n,
+			BUSRQ_n    => BUSRQ_n,
+			BUSAK_n    => BUSAK_n,
+			CLK_n      => CLK_n,
+			A          => A,
+			DInst      => DI,
+			DI         => DI_Reg,
+			DO         => DO,
+			MC         => MCycle,
+			TS         => TState,
+			IntCycle_n => IntCycle_n,
+			isGBC      => isGBC,
+			-- savestates
+			SaveStateBus_Din  => SaveStateBus_Din, 
+			SaveStateBus_Adr  => SaveStateBus_Adr, 
+			SaveStateBus_wren => SaveStateBus_wren,
+			SaveStateBus_rst  => SaveStateBus_rst, 
+			SaveStateBus_Dout => reg_wired_or(1)
+		);
+
+	process (CLK_n)
+	begin
+		if CLK_n'event and CLK_n = '1' then
+			if RESET_n = '0' then
+				RD_n   <=  SS_GBSE(0);           -- '1';
+				WR_n   <=  SS_GBSE(1);           -- '1';
+				IORQ_n <=  SS_GBSE(2);           -- '1';
+				MREQ_n <=  SS_GBSE(3);           -- '1';
+				DI_Reg <=  SS_GBSE(11 downto 4); -- "00000000";
+			elsif CLKEN = '1' then
+				RD_n <= '1';
+				WR_n <= '1';
+				IORQ_n <= '1';
+				MREQ_n <= '1';
+				if MCycle = "001" then
+					if TState = "001" or TState = "010" then
+						RD_n <= not IntCycle_n;
+						MREQ_n <= not IntCycle_n;
+					end if;
+					if TState = "011" then
+						MREQ_n <= '0';
+					end if;
+				elsif MCycle = "011" and IntCycle_n = '0' then
+					if TState = "010" then
+						IORQ_n <= '0'; -- Acknowledge IRQ
+					end if;
+				else
+					if (TState = "001" or TState = "010") and (NoRead = '0' and Write = '0') then
+						RD_n <= '0';
+						IORQ_n <= not IORQ;
+						MREQ_n <= IORQ;
+					end if;
+					if T2Write = 0 then
+						if TState = "010" and Write = '1' then
+							WR_n <= '0';
+							IORQ_n <= not IORQ;
+							MREQ_n <= IORQ;
+						end if;
+					elsif T2Write = 1 then
+						if (TState = "001" or (TState = "010" and Wait_n = '0')) and Write = '1' then
+							WR_n <= '0';
+							IORQ_n <= not IORQ;
+							MREQ_n <= IORQ;
+						end if;
+					else
+						if (TState = "001" or TState = "010") and Write = '1' then
+							WR_n <= '0';
+							IORQ_n <= not IORQ;
+							MREQ_n <= IORQ;
+						end if;
+					end if;
+				end if;
+				if TState = "011" and Wait_n = '1' then
+					DI_Reg <= DI;
+				end if;
+			end if;
+		end if;
+	end process;
+
+end;

ModRetro_oss-chromatic-console-fpga/esp32t/src/rtl/EMU/CORE/T80/T80.vhd

@@ -0,0 +1,1341 @@
+-- ****
+-- T80(b) core. In an effort to merge and maintain bug fixes ....
+--
+--
+-- Ver 303 add undocumented DDCB and FDCB opcodes by TobiFlex 20.04.2010
+-- Ver 302 fixed IO cycle timing, tested thanks to Alessandro.
+-- Ver 301 parity flag is just parity for 8080, also overflow for Z80, by Sean Riddle
+-- Ver 300 started tidyup. Rmoved some auto_wait bits from 0247 which caused problems
+--
+-- MikeJ March 2005
+-- Latest version from www.fpgaarcade.com (original www.opencores.org)
+--
+-- ****
+--
+-- Z80 compatible microprocessor core
+--
+-- Version : 0247
+--
+-- Copyright (c) 2001-2002 Daniel Wallner (jesus@opencores.org)
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- Please report bugs to the author, but before you do so, please
+-- make sure that this is not a derivative work and that
+-- you have the latest version of this file.
+--
+-- The latest version of this file can be found at:
+--      http://www.opencores.org/cvsweb.shtml/t80/
+--
+-- Limitations :
+--
+-- File history :
+--
+--      0208 : First complete release
+--
+--      0210 : Fixed wait and halt
+--
+--      0211 : Fixed Refresh addition and IM 1
+--
+--      0214 : Fixed mostly flags, only the block instructions now fail the zex regression test
+--
+--      0232 : Removed refresh address output for Mode > 1 and added DJNZ M1_n fix by Mike Johnson
+--
+--      0235 : Added clock enable and IM 2 fix by Mike Johnson
+--
+--      0237 : Changed 8080 I/O address output, added IntE output
+--
+--      0238 : Fixed (IX/IY+d) timing and 16 bit ADC and SBC zero flag
+--
+--      0240 : Added interrupt ack fix by Mike Johnson, changed (IX/IY+d) timing and changed flags in GB mode
+--
+--      0242 : Added I/O wait, fixed refresh address, moved some registers to RAM
+--
+--      0247 : Fixed bus req/ack cycle
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use work.T80_Pack.all;
+
+use work.pBus_savestates.all;
+use work.pReg_savestates.all;
+
+entity T80 is
+	generic(
+		Mode   : integer := 0;  -- 0 => Z80, 1 => Fast Z80, 2 => 8080, 3 => GB
+		IOWait : integer := 0;  -- 1 => Single cycle I/O, 1 => Std I/O cycle
+		Flag_C : integer := 0;
+		Flag_N : integer := 1;
+		Flag_P : integer := 2;
+		Flag_X : integer := 3;
+		Flag_H : integer := 4;
+		Flag_Y : integer := 5;
+		Flag_Z : integer := 6;
+		Flag_S : integer := 7
+	);
+	port(
+		RESET_n         : in  std_logic;
+		CLK_n           : in  std_logic;
+		CEN             : in  std_logic;
+		WAIT_n          : in  std_logic;
+		INT_n           : in  std_logic;
+		NMI_n           : in  std_logic;
+		BUSRQ_n         : in  std_logic;
+		M1_n            : buffer std_logic;
+		IORQ            : out std_logic;
+		NoRead          : out std_logic;
+		Write           : out std_logic;
+		RFSH_n          : buffer std_logic;
+		HALT_n          : out std_logic;
+		BUSAK_n         : out std_logic;
+		A               : buffer std_logic_vector(15 downto 0);
+		DInst           : in  std_logic_vector(7 downto 0);
+		DI              : in  std_logic_vector(7 downto 0);
+		DO              : buffer std_logic_vector(7 downto 0);
+		MC              : out std_logic_vector(2 downto 0);
+		TS              : out std_logic_vector(2 downto 0);
+		IntCycle_n      : out std_logic;
+		IntE            : out std_logic;
+		Stop            : out 	 std_logic;
+		isGBC           : in  std_logic := '0'; -- Gameboy Color
+		-- savestates              
+		SaveStateBus_Din  : in  std_logic_vector(BUS_buswidth-1 downto 0);
+		SaveStateBus_Adr  : in  std_logic_vector(BUS_busadr-1 downto 0);
+		SaveStateBus_wren : in  std_logic;
+		SaveStateBus_rst  : in  std_logic;
+		SaveStateBus_Dout : out std_logic_vector(BUS_buswidth-1 downto 0)
+	);
+end T80;
+
+architecture rtl of T80 is
+
+	-- Registers
+	signal ACC, F               : std_logic_vector(7 downto 0);
+	signal Ap, Fp               : std_logic_vector(7 downto 0);
+	signal I                    : std_logic_vector(7 downto 0);
+	signal R                    : unsigned(7 downto 0);
+	signal SP, PC               : unsigned(15 downto 0);
+
+	signal RegDIH               : std_logic_vector(7 downto 0);
+	signal RegDIL               : std_logic_vector(7 downto 0);
+	signal RegBusA              : std_logic_vector(15 downto 0);
+	signal RegBusB              : std_logic_vector(15 downto 0);
+	signal RegBusC              : std_logic_vector(15 downto 0);
+	signal RegAddrA_r           : std_logic_vector(2 downto 0);
+	signal RegAddrA             : std_logic_vector(2 downto 0);
+	signal RegAddrB_r           : std_logic_vector(2 downto 0);
+	signal RegAddrB             : std_logic_vector(2 downto 0);
+	signal RegAddrC             : std_logic_vector(2 downto 0);
+	signal RegWEH               : std_logic;
+	signal RegWEL               : std_logic;
+	signal Alternate            : std_logic;
+
+	-- Help Registers
+	signal TmpAddr              : std_logic_vector(15 downto 0);        -- Temporary address register
+	signal TmpAddr2             : std_logic_vector(15 downto 0);        -- Temporary address register
+	signal IR                   : std_logic_vector(7 downto 0);         -- Instruction register
+	signal IR_muxed             : std_logic_vector(7 downto 0);         -- Used for Mode = 3(GB) to sample IR in TState3 instead of TState2
+	signal ISet                 : std_logic_vector(1 downto 0);         -- Instruction set selector
+	signal RegBusA_r            : std_logic_vector(15 downto 0);
+
+	signal ID16                 : signed(15 downto 0);
+	signal Save_Mux             : std_logic_vector(7 downto 0);
+
+	signal TState               : unsigned(2 downto 0);
+	signal MCycle               : std_logic_vector(2 downto 0);
+	signal IntE_FF1             : std_logic;
+	signal IntE_FF2             : std_logic;
+	signal Halt_FF              : std_logic;
+	signal BusReq_s             : std_logic;
+	signal BusAck               : std_logic;
+	signal ClkEn                : std_logic;
+	signal NMI_s                : std_logic;
+	signal OldNMI_n             : std_logic;
+	signal INT_s                : std_logic;
+	signal IStatus              : std_logic_vector(1 downto 0);
+
+	signal DI_Reg               : std_logic_vector(7 downto 0);
+	signal T_Res                : std_logic;
+	signal XY_State             : std_logic_vector(1 downto 0);
+	signal Pre_XY_F_M           : std_logic_vector(2 downto 0);
+	signal NextIs_XY_Fetch      : std_logic;
+	signal XY_Ind               : std_logic;
+	signal No_BTR               : std_logic;
+	signal BTR_r                : std_logic;
+	signal Auto_Wait            : std_logic;
+	signal Auto_Wait_t1         : std_logic;
+	signal Auto_Wait_t2         : std_logic;
+	signal IncDecZ              : std_logic;
+
+	-- ALU signals
+	signal BusB                 : std_logic_vector(7 downto 0);
+	signal BusA                 : std_logic_vector(7 downto 0);
+	signal ALU_Q                : std_logic_vector(7 downto 0);
+	signal F_Out                : std_logic_vector(7 downto 0);
+
+	-- Registered micro code outputs
+	signal Read_To_Reg_r        : std_logic_vector(4 downto 0);
+	signal Arith16_r            : std_logic;
+	signal Z16_r                : std_logic;
+	signal ALU_Op_r             : std_logic_vector(3 downto 0);
+	signal Save_ALU_r           : std_logic;
+	signal PreserveC_r          : std_logic;
+	signal MCycles              : std_logic_vector(2 downto 0);
+
+	-- Micro code outputs
+	signal MCycles_d            : std_logic_vector(2 downto 0);
+	signal TStates              : std_logic_vector(2 downto 0);
+	signal IntCycle             : std_logic;
+	signal NMICycle             : std_logic;
+	signal Inc_PC               : std_logic;
+	signal Inc_WZ               : std_logic;
+	signal IncDec_16            : std_logic_vector(3 downto 0);
+	signal Prefix               : std_logic_vector(1 downto 0);
+	signal Read_To_Acc          : std_logic;
+	signal Read_To_Reg          : std_logic;
+	signal Set_BusB_To          : std_logic_vector(3 downto 0);
+	signal Set_BusA_To          : std_logic_vector(3 downto 0);
+	signal ALU_Op               : std_logic_vector(3 downto 0);
+	signal Save_ALU             : std_logic;
+	signal Rot_Akku             : std_logic;
+	signal PreserveC            : std_logic;
+	signal Arith16              : std_logic;
+	signal Set_Addr_To          : std_logic_vector(2 downto 0);
+	signal Jump                 : std_logic;
+	signal JumpE                : std_logic;
+	signal JumpXY               : std_logic;
+	signal Call                 : std_logic;
+	signal RstP                 : std_logic;
+	signal LDZ                  : std_logic;
+	signal LDW                  : std_logic;
+	signal LDSPHL               : std_logic;
+	signal LDHLSP               : std_logic;
+	signal ADDSPdd					 : std_logic;
+	signal IORQ_i               : std_logic;
+	signal Special_LD           : std_logic_vector(2 downto 0);
+	signal ExchangeDH           : std_logic;
+	signal ExchangeRp           : std_logic;
+	signal ExchangeAF           : std_logic;
+	signal ExchangeRS           : std_logic;
+	signal I_DJNZ               : std_logic;
+	signal I_CPL                : std_logic;
+	signal I_CCF                : std_logic;
+	signal I_SCF                : std_logic;
+	signal I_RETN               : std_logic;
+	signal I_BT                 : std_logic;
+	signal I_BC                 : std_logic;
+	signal I_BTR                : std_logic;
+	signal I_RLD                : std_logic;
+	signal I_RRD                : std_logic;
+	signal I_INRC               : std_logic;
+	signal SetDI                : std_logic;
+	signal SetEI                : std_logic;
+	signal IMode                : std_logic_vector(1 downto 0);
+	signal Halt                 : std_logic;
+	signal XYbit_undoc          : std_logic;
+
+	signal updateIR             : std_logic; -- Used for Mode = 3(GB) to sample IR in TState3 instead of TState2
+
+	-- savestates
+	type t_reg_wired_or is array(0 to 4) of std_logic_vector(63 downto 0);
+	signal reg_wired_or : t_reg_wired_or;
+
+	signal SS_1      : std_logic_vector(REG_SAVESTATE_T80_1.upper downto REG_SAVESTATE_T80_1.lower);
+	signal SS_1_BACK : std_logic_vector(REG_SAVESTATE_T80_1.upper downto REG_SAVESTATE_T80_1.lower);	
+	signal SS_2      : std_logic_vector(REG_SAVESTATE_T80_2.upper downto REG_SAVESTATE_T80_2.lower);
+	signal SS_2_BACK : std_logic_vector(REG_SAVESTATE_T80_2.upper downto REG_SAVESTATE_T80_2.lower);	
+	signal SS_3      : std_logic_vector(REG_SAVESTATE_T80_3.upper downto REG_SAVESTATE_T80_3.lower);
+	signal SS_3_BACK : std_logic_vector(REG_SAVESTATE_T80_3.upper downto REG_SAVESTATE_T80_3.lower);	
+	signal SS_4      : std_logic_vector(REG_SAVESTATE_T80_4.upper downto REG_SAVESTATE_T80_4.lower);
+	signal SS_4_BACK : std_logic_vector(REG_SAVESTATE_T80_4.upper downto REG_SAVESTATE_T80_4.lower);
+
+begin
+
+	iREG_SAVESTATE_T80_1 : entity work.eReg_Savestate generic map ( REG_SAVESTATE_T80_1 ) port map (CLK_n, SaveStateBus_Din, SaveStateBus_Adr, SaveStateBus_wren, SaveStateBus_rst, reg_wired_or(1), SS_1_BACK, SS_1);  
+	iREG_SAVESTATE_T80_2 : entity work.eReg_Savestate generic map ( REG_SAVESTATE_T80_2 ) port map (CLK_n, SaveStateBus_Din, SaveStateBus_Adr, SaveStateBus_wren, SaveStateBus_rst, reg_wired_or(2), SS_2_BACK, SS_2);  
+	iREG_SAVESTATE_T80_3 : entity work.eReg_Savestate generic map ( REG_SAVESTATE_T80_3 ) port map (CLK_n, SaveStateBus_Din, SaveStateBus_Adr, SaveStateBus_wren, SaveStateBus_rst, reg_wired_or(3), SS_3_BACK, SS_3);  
+	iREG_SAVESTATE_T80_4 : entity work.eReg_Savestate generic map ( REG_SAVESTATE_T80_4 ) port map (CLK_n, SaveStateBus_Din, SaveStateBus_Adr, SaveStateBus_wren, SaveStateBus_rst, reg_wired_or(4), SS_4_BACK, SS_4);  
+
+	process (reg_wired_or)
+		variable wired_or : std_logic_vector(63 downto 0);
+	begin
+		wired_or := reg_wired_or(0);
+		for i in 1 to (reg_wired_or'length - 1) loop
+			wired_or := wired_or or reg_wired_or(i);
+		end loop;
+		SaveStateBus_Dout <= wired_or;
+	end process;
+
+	mcode : T80_MCode
+		generic map(
+			Mode   => Mode,
+			Flag_C => Flag_C,
+			Flag_N => Flag_N,
+			Flag_P => Flag_P,
+			Flag_X => Flag_X,
+			Flag_H => Flag_H,
+			Flag_Y => Flag_Y,
+			Flag_Z => Flag_Z,
+			Flag_S => Flag_S)
+		port map(
+			IR          => IR_muxed,
+			ISet        => ISet,
+			MCycle      => MCycle,
+			F           => F,
+			NMICycle    => NMICycle,
+			IntCycle    => IntCycle,
+			XY_State    => XY_State,
+			MCycles     => MCycles_d,
+			TStates     => TStates,
+			Prefix      => Prefix,
+			Inc_PC      => Inc_PC,
+			Inc_WZ      => Inc_WZ,
+			IncDec_16   => IncDec_16,
+			Read_To_Acc => Read_To_Acc,
+			Read_To_Reg => Read_To_Reg,
+			Set_BusB_To => Set_BusB_To,
+			Set_BusA_To => Set_BusA_To,
+			ALU_Op      => ALU_Op,
+			Save_ALU    => Save_ALU,
+			Rot_Akku    => Rot_Akku,
+			PreserveC   => PreserveC,
+			Arith16     => Arith16,
+			Set_Addr_To => Set_Addr_To,
+			IORQ        => IORQ_i,
+			Jump        => Jump,
+			JumpE       => JumpE,
+			JumpXY      => JumpXY,
+			Call        => Call,
+			RstP        => RstP,
+			LDZ         => LDZ,
+			LDW         => LDW,
+			LDSPHL      => LDSPHL,
+			LDHLSP		=> LDHLSP,
+			ADDSPdd		=> ADDSPdd,
+			Special_LD  => Special_LD,
+			ExchangeDH  => ExchangeDH,
+			ExchangeRp  => ExchangeRp,
+			ExchangeAF  => ExchangeAF,
+			ExchangeRS  => ExchangeRS,
+			I_DJNZ      => I_DJNZ,
+			I_CPL       => I_CPL,
+			I_CCF       => I_CCF,
+			I_SCF       => I_SCF,
+			I_RETN      => I_RETN,
+			I_BT        => I_BT,
+			I_BC        => I_BC,
+			I_BTR       => I_BTR,
+			I_RLD       => I_RLD,
+			I_RRD       => I_RRD,
+			I_INRC      => I_INRC,
+			SetDI       => SetDI,
+			SetEI       => SetEI,
+			IMode       => IMode,
+			Halt        => Halt,
+			NoRead      => NoRead,
+			Write       => Write,
+			XYbit_undoc => XYbit_undoc);
+
+	alu : T80_ALU
+		generic map(
+			Mode   => Mode,
+			Flag_C => Flag_C,
+			Flag_N => Flag_N,
+			Flag_P => Flag_P,
+			Flag_X => Flag_X,
+			Flag_H => Flag_H,
+			Flag_Y => Flag_Y,
+			Flag_Z => Flag_Z,
+			Flag_S => Flag_S)
+		port map(
+			Arith16 => Arith16_r,
+			Z16     => Z16_r,
+			ALU_Op  => ALU_Op_r,
+			Rot_Akku    => Rot_Akku,
+			IR      => IR_muxed(5 downto 0),
+			ISet    => ISet,
+			BusA    => BusA,
+			BusB    => BusB,
+			F_In    => F,
+			Q       => ALU_Q,
+			F_Out   => F_Out);
+
+	ClkEn <= CEN and not BusAck;
+
+	T_Res <= '1' when TState = unsigned(TStates) else '0';
+
+	NextIs_XY_Fetch <= '1' when XY_State /= "00" and XY_Ind = '0' and
+							((Set_Addr_To = aXY) or
+							(MCycle = "001" and IR = "11001011") or
+							(MCycle = "001" and IR = "00110110")) else '0';
+
+	Save_Mux <= BusB when ExchangeRp = '1' else
+		DI_Reg when Save_ALU_r = '0' else
+		ALU_Q;
+
+
+	SS_1_BACK(15 downto  0) <= std_logic_vector(PC);
+	SS_1_BACK(31 downto 16) <= A 		  ;
+	SS_1_BACK(47 downto 32) <= TmpAddr ;
+	SS_1_BACK(55 downto 48) <= IR 	  ;
+	SS_1_BACK(57 downto 56) <= ISet 	  ;
+	SS_1_BACK(59 downto 58) <= XY_State;
+	SS_1_BACK(61 downto 60) <= IStatus ;
+	
+	SS_2_BACK( 7 downto  0) <= DO;
+	SS_2_BACK(15 downto  8) <= ACC;
+	SS_2_BACK(23 downto 16) <= Ap;
+	SS_2_BACK(31 downto 24) <= Fp;
+	SS_2_BACK(39 downto 32) <= I ;
+	SS_2_BACK(47 downto 40) <= std_logic_vector(R);
+	SS_2_BACK(50 downto 48) <= MCycles;
+	
+	SS_3_BACK(15 downto  0) <= std_logic_vector(SP);
+	SS_3_BACK(20 downto 16) <= Read_To_Reg_r;
+	SS_3_BACK(28 downto 21) <= F 				;
+	SS_3_BACK(29)           <= Arith16_r 	;
+	SS_3_BACK(30)           <= BTR_r 		;
+	SS_3_BACK(31)           <= Z16_r 		;
+	SS_3_BACK(35 downto 32) <= ALU_Op_r 	;
+	SS_3_BACK(36) 			   <= Save_ALU_r 	;
+	SS_3_BACK(37) 			   <= PreserveC_r ;
+	SS_3_BACK(38) 			   <= XY_Ind 		;
+
+	IR_muxed <= DInst when (updateIR = '1') else IR;
+
+	process (CLK_n)
+	variable temp_c : unsigned(8 downto 0);
+	variable temp_h : unsigned(4 downto 0);
+	begin
+		if CLK_n'event and CLK_n = '1' then
+			if RESET_n = '0' then
+
+				PC 				<= unsigned(SS_1(15 downto  0)); -- (others => '0');  -- Program Counter
+				A 					<= SS_1(31 downto 16); -- (others => '0');
+				TmpAddr 			<= SS_1(47 downto 32); -- (others => '0');
+				IR 				<= SS_1(55 downto 48); -- "00000000";
+				ISet 				<= SS_1(57 downto 56); -- "00";
+				XY_State 		<= SS_1(59 downto 58); -- "00";
+				IStatus 			<= SS_1(61 downto 60); -- "00";
+				MCycles 			<= SS_2(50 downto 48); -- "000";
+				DO 				<= SS_2( 7 downto  0); -- "00000000";
+										 
+				ACC 				<= SS_2(15 downto  8); -- (others => '0');
+				if Mode = 3 then -- this is what Gameboy should be using, but it's ignored because overwritten down below, why?
+				F <= "11110000";
+			else
+				F <= (others => '1');
+			end if;
+				Ap 				<= SS_2(23 downto 16); -- (others => '1');
+				Fp 				<= SS_2(31 downto 24); -- (others => '1');
+				I 					<= SS_2(39 downto 32); -- (others => '0');
+				R 					<= unsigned(SS_2(47 downto 40)); -- (others => '0');
+				SP 				<= unsigned(SS_3(15 downto  0)); -- (others => '1');
+				Alternate 		<= '0'; -- unused in gameboy
+
+				Read_To_Reg_r 	<= SS_3(20 downto 16); -- "00000";
+				F 					<= SS_3(28 downto 21); -- (others => '1');
+				Arith16_r 		<= SS_3(29); 			  -- '0';
+				BTR_r 			<= SS_3(30); 			  -- '0';
+				Z16_r 			<= SS_3(31); 			  -- '0';
+				ALU_Op_r 		<= SS_3(35 downto 32); -- "0000";
+				Save_ALU_r 		<= SS_3(36); 			-- '0';
+				PreserveC_r 	<= SS_3(37); 			-- '0';
+				XY_Ind 			<= SS_3(38); 			-- '0';
+
+				updateIR <= '0';
+
+			elsif ClkEn = '1' then
+
+				updateIR <= '0';
+				if (updateIR = '1') then
+					IR <= DInst;
+				end if;
+
+			ALU_Op_r <= "0000";
+			Save_ALU_r <= '0';
+			Read_To_Reg_r <= "00000";
+
+			MCycles <= MCycles_d;
+			
+			if LDHLSP = '1' and MCycle = "011" and TState = 1 then
+			   temp_c := unsigned('0'&SP(7 downto 0))+unsigned('0'&Save_Mux);
+				temp_h := unsigned('0'&SP(3 downto 0))+unsigned('0'&Save_Mux(3 downto 0));
+				F(Flag_Z) <= '0';	
+				F(Flag_N) <= '0';
+				F(Flag_H) <= temp_h(4);
+				F(Flag_C) <= temp_c(8);
+			end if;
+			
+			if ADDSPdd = '1' and TState = 1 then
+			   temp_c := unsigned('0'&SP(7 downto 0))+unsigned('0'&Save_Mux);
+				temp_h := unsigned('0'&SP(3 downto 0))+unsigned('0'&Save_Mux(3 downto 0));
+				F(Flag_Z) <= '0';	
+				F(Flag_N) <= '0';
+				F(Flag_H) <= temp_h(4);
+				F(Flag_C) <= temp_c(8);
+			end if;
+
+      if Mode = 3 then
+        IStatus <= "10";
+			elsif IMode /= "11" then
+				IStatus <= IMode;
+			end if;
+
+			Arith16_r <= Arith16;
+			PreserveC_r <= PreserveC;
+			if ISet = "10" and ALU_OP(2) = '0' and ALU_OP(0) = '1' and MCycle = "011" then
+				Z16_r <= '1';
+			else
+				Z16_r <= '0';
+			end if;
+
+			if (MCycle /= "001" and TState = 2 and Wait_n = '1') or (MCycle = "001" and ((Mode = 3 and TState = 3) or (Mode /= 3 and TState = 4))) then
+				if IncDec_16(2 downto 0) = "111" then
+					if IncDec_16(3) = '1' then
+						SP <= SP - 1;
+					else
+						SP <= SP + 1;
+					end if;
+				end if;
+			end if;
+
+			if MCycle  = "001" and TState(2) = '0' then
+			-- MCycle = 1 and TState = 1, 2, or 3
+
+				if TState = 2 and Wait_n = '1' then
+					if Mode < 2 then
+						A(7 downto 0) <= std_logic_vector(R);
+						A(15 downto 8) <= I;
+						R(6 downto 0) <= R(6 downto 0) + 1;
+					end if;
+
+					if Jump = '0' and Call = '0' and NMICycle = '0' and IntCycle = '0' and not (Halt_FF = '1' or Halt = '1')
+						and not (Mode = 3 and IntE_FF1 = '1' and INT_s = '1' and Prefix = "00") then --GB: Run NOP instead of instruction if INT_s is active here
+						PC <= PC + 1;
+					end if;
+
+					if IntCycle = '1' and IStatus = "01" then
+						IR <= "11111111";
+					elsif Halt_FF = '1' or (IntCycle = '1' and IStatus = "10") or NMICycle = '1'
+							or (Mode = 3 and IntE_FF1 = '1' and INT_s = '1' and Prefix = "00") then --GB: Run NOP instead of instruction if INT_s is active here
+						IR <= "00000000";
+					else
+						if Mode = 3 then
+							updateIR <= '1';
+						else
+							IR <= DInst;
+						end if;
+					end if;
+
+					ISet <= "00";
+					if Prefix /= "00" then
+						if Prefix = "11" then
+							if IR(5) = '1' then
+								XY_State <= "10";
+							else
+								XY_State <= "01";
+							end if;
+						else
+							if Prefix = "10" then
+								XY_State <= "00";
+								XY_Ind <= '0';
+							end if;
+							ISet <= Prefix;
+						end if;
+					else
+						XY_State <= "00";
+						XY_Ind <= '0';
+					end if;
+				end if;
+
+			else
+			-- either (MCycle > 1) OR (MCycle = 1 AND TState > 3)
+
+				if MCycle = "110" then
+					XY_Ind <= '1';
+					if Prefix = "01" then
+						ISet <= "01";
+					end if;
+				end if;
+
+				if T_Res = '1' then
+					BTR_r <= (I_BT or I_BC or I_BTR) and not No_BTR;
+					if Jump = '1' then
+            A(15 downto 8) <= DI_Reg;
+            A(7 downto 0) <= TmpAddr(7 downto 0);
+            PC(15 downto 8) <= unsigned(DI_Reg);
+            PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
+					elsif JumpXY = '1' then
+						A <= RegBusC;
+						PC <= unsigned(RegBusC);
+					elsif Call = '1' or RstP = '1' then
+						A <= TmpAddr;
+						PC <= unsigned(TmpAddr);
+					elsif MCycle = MCycles and NMICycle = '1' then
+						A <= "0000000001100110";
+						PC <= "0000000001100110";
+					elsif ((Mode /= 3 and MCycle = "011") or (Mode = 3 and MCycle = "100")) 
+							and IntCycle = '1' and IStatus = "10" then
+            A(15 downto 8) <= I;
+            A(7 downto 0) <= TmpAddr(7 downto 0);
+            PC(15 downto 8) <= unsigned(I);
+            PC(7 downto 0) <= unsigned(TmpAddr(7 downto 0));
+					else
+						case Set_Addr_To is
+						when aXY =>
+							if XY_State = "00" then
+								A <= RegBusC;
+							else
+								if NextIs_XY_Fetch = '1' then
+									A <= std_logic_vector(PC);
+								else
+									A <= TmpAddr;
+								end if;
+							end if;
+						when aIOA =>
+							if Mode = 3 then
+								-- Memory map I/O on GBZ80
+								A(15 downto 8) <= (others => '1');
+							elsif Mode = 2 then
+								-- Duplicate I/O address on 8080
+								A(15 downto 8) <= DI_Reg;
+							else
+								A(15 downto 8) <= ACC;
+							end if;
+							A(7 downto 0) <= DI_Reg;
+						when aSP =>
+							A <= std_logic_vector(SP);
+						when aBC =>
+							if Mode = 3 and IORQ_i = '1' then
+								-- Memory map I/O on GBZ80
+								A(15 downto 8) <= (others => '1');
+								A(7 downto 0) <= RegBusC(7 downto 0);
+							else
+								A <= RegBusC;
+							end if;
+						when aDE =>
+							A <= RegBusC;
+						when aZI =>
+							if Inc_WZ = '1' then
+								A <= std_logic_vector(unsigned(TmpAddr) + 1);
+							else
+								A(15 downto 8) <= DI_Reg;
+								A(7 downto 0) <= TmpAddr(7 downto 0);
+							end if;
+						when others =>
+							A <= std_logic_vector(PC);
+						end case;
+					end if;
+
+					Save_ALU_r <= Save_ALU;
+					ALU_Op_r <= ALU_Op;
+					
+					if Mode = 3 then
+						if I_CPL = '1' then
+							-- CPL
+							ACC <= not ACC;
+							F(Flag_H) <= '1';
+							F(Flag_N) <= '1';
+						end if;
+						if I_CCF = '1' then
+							-- CCF
+							F(Flag_C) <= not F(Flag_C);
+							F(Flag_H) <= '0';
+							F(Flag_N) <= '0';
+						end if;
+						if I_SCF = '1' then
+							-- SCF
+							F(Flag_C) <= '1';
+							F(Flag_H) <= '0';
+							F(Flag_N) <= '0';
+						end if;
+					else
+						if I_CPL = '1' then
+							-- CPL
+							ACC <= not ACC;
+							F(Flag_Y) <= not ACC(5);
+							F(Flag_H) <= '1';
+							F(Flag_X) <= not ACC(3);
+							F(Flag_N) <= '1';
+						end if;
+						if I_CCF = '1' then
+							-- CCF
+							F(Flag_C) <= not F(Flag_C);
+							F(Flag_Y) <= ACC(5);
+							F(Flag_H) <=  F(Flag_C);
+							F(Flag_X) <= ACC(3);
+							F(Flag_N) <= '0';
+						end if;
+						if I_SCF = '1' then
+							-- SCF
+							F(Flag_C) <= '1';
+							F(Flag_Y) <= ACC(5);
+							F(Flag_H) <= '0';
+							F(Flag_X) <= ACC(3);
+							F(Flag_N) <= '0';
+						end if;
+					end if;
+
+
+				end if;
+
+				if TState = 2 and Wait_n = '1' then
+					if ISet = "01" and MCycle = "111" then
+						if Mode = 3 then
+							updateIR <= '1';
+						else
+							IR <= DInst;
+						end if;
+					end if;
+					if JumpE = '1' then
+						PC <= unsigned(signed(PC) + signed(DI_Reg));
+					elsif Inc_PC = '1' then
+						PC <= PC + 1;
+					end if;
+					if BTR_r = '1' then
+						PC <= PC - 2;
+					end if;
+					if RstP = '1' then
+						TmpAddr <= (others =>'0');
+						TmpAddr(5 downto 3) <= IR(5 downto 3);
+					end if;
+				end if;
+				if TState = 3 and MCycle = "110" then
+					if (Mode = 3) then
+						TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DInst));
+					else
+						TmpAddr <= std_logic_vector(signed(RegBusC) + signed(DI_Reg));
+					end if;
+				end if;
+
+				if ADDSPdd = '1' and TState = 2 then
+				   TmpAddr<=std_logic_vector(SP);
+					SP <= unsigned(signed(SP)+signed(Save_Mux));
+				end if;
+
+				if LDSPHL = '1' then
+					SP <= unsigned(RegBusC);
+				end if;
+				if ExchangeAF = '1' then
+					Ap <= ACC;
+					ACC <= Ap;
+					Fp <= F;
+					F <= Fp;
+				end if;
+				if ExchangeRS = '1' then
+					Alternate <= not Alternate;
+				end if;
+			end if;
+
+			if TState = 3 then
+				if LDZ = '1' then
+					if (Mode = 3) then
+						TmpAddr(7 downto 0) <= DInst;
+					else
+						TmpAddr(7 downto 0) <= DI_Reg;
+					end if;
+				end if;
+				if LDW = '1' then
+					if (Mode = 3) then
+						TmpAddr(15 downto 8) <= DInst;
+					else
+						TmpAddr(15 downto 8) <= DI_Reg;
+					end if;
+				end if;
+
+				if Special_LD(2) = '1' then
+					case Special_LD(1 downto 0) is
+					when "00" =>
+						ACC <= I;
+						F(Flag_P) <= IntE_FF2;
+					when "01" =>
+						ACC <= std_logic_vector(R);
+						F(Flag_P) <= IntE_FF2;
+					when "10" =>
+						I <= ACC;
+					when others =>
+						R <= unsigned(ACC);
+					end case;
+				end if;
+			end if;
+
+			if (I_DJNZ = '0' and Save_ALU_r = '1') or ALU_Op_r = "1001" then
+				if Mode = 3 then
+					F(6) <= F_Out(6);
+					F(5) <= F_Out(5);
+					F(7) <= F_Out(7);
+					if PreserveC_r = '0' then
+						F(4) <= F_Out(4);
+					end if;
+				else
+					F(7 downto 1) <= F_Out(7 downto 1);
+					if PreserveC_r = '0' then
+						F(Flag_C) <= F_Out(0);
+					end if;
+				end if;
+			end if;
+			if T_Res = '1' and I_INRC = '1' then
+				F(Flag_H) <= '0';
+				F(Flag_N) <= '0';
+				if DI_Reg(7 downto 0) = "00000000" then
+					F(Flag_Z) <= '1';
+				else
+					F(Flag_Z) <= '0';
+				end if;
+				F(Flag_S) <= DI_Reg(7);
+				F(Flag_P) <= not (DI_Reg(0) xor DI_Reg(1) xor DI_Reg(2) xor DI_Reg(3) xor
+					DI_Reg(4) xor DI_Reg(5) xor DI_Reg(6) xor DI_Reg(7));
+			end if;
+
+			if TState = 1 then
+				DO <= BusB;
+				if I_RLD = '1' then
+					DO(3 downto 0) <= BusA(3 downto 0);
+					DO(7 downto 4) <= BusB(3 downto 0);
+				end if;
+				if I_RRD = '1' then
+					DO(3 downto 0) <= BusB(7 downto 4);
+					DO(7 downto 4) <= BusA(3 downto 0);
+				end if;
+			end if;
+
+			if T_Res = '1' then
+				Read_To_Reg_r(3 downto 0) <= Set_BusA_To;
+				Read_To_Reg_r(4) <= Read_To_Reg;
+				if Read_To_Acc = '1' then
+					Read_To_Reg_r(3 downto 0) <= "0111";
+					Read_To_Reg_r(4) <= '1';
+				end if;
+			end if;
+
+			if TState = 1 and I_BT = '1' then
+				F(Flag_X) <= ALU_Q(3);
+				F(Flag_Y) <= ALU_Q(1);
+				F(Flag_H) <= '0';
+				F(Flag_N) <= '0';
+			end if;
+			if I_BC = '1' or I_BT = '1' then
+				F(Flag_P) <= IncDecZ;
+			end if;
+
+			if (TState = 1 and Save_ALU_r = '0') or
+				(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
+				case Read_To_Reg_r is
+				when "10111" =>
+					ACC <= Save_Mux;
+				when "10110" =>
+					DO <= Save_Mux;
+				when "11000" =>
+					SP(7 downto 0) <= unsigned(Save_Mux);
+				when "11001" =>
+					SP(15 downto 8) <= unsigned(Save_Mux);
+				when "11011" =>
+					if Mode = 3 then
+						F(7 downto 4) <= Save_Mux(7 downto 4);
+						F(3 downto 0) <= "0000"; -- bit 3 to 0 always return 0
+					else
+						F <= Save_Mux;
+					end if;
+				when others =>
+				end case;
+				if XYbit_undoc='1' then
+					DO <= ALU_Q;
+				end if;
+			end if;
+
+		end if;
+
+		end if;
+
+	end process;
+
+---------------------------------------------------------------------------
+--
+-- BC('), DE('), HL('), IX and IY
+--
+---------------------------------------------------------------------------
+	
+	SS_4_BACK(15 downto  0) <= RegBusA_r ;
+	SS_4_BACK(18 downto 16) <= "000"; -- unused now
+	SS_4_BACK(21 downto 19) <= RegAddrA_r;
+	SS_4_BACK(24 downto 22) <= "000"; -- unused now
+	SS_4_BACK(27 downto 25) <= RegAddrB_r;
+	SS_4_BACK(30 downto 28) <= RegAddrC  ;
+	SS_4_BACK(31)           <= IncDecZ   ;
+	
+	process (CLK_n)
+	begin
+		if CLK_n'event and CLK_n = '1' then
+			if RESET_n = '0' then
+			
+				RegBusA_r  <= SS_4(15 downto  0); -- (others => '0');
+				RegAddrA_r <= SS_4(21 downto 19); -- (others => '0');
+				RegAddrB_r <= SS_4(27 downto 25); -- (others => '0');
+				RegAddrC   <= SS_4(30 downto 28); -- (others => '0');
+				IncDecZ    <= SS_4(31); 			 -- '0';
+			
+			elsif ClkEn = '1' then
+				-- Bus A / Write
+				RegAddrA_r <= Alternate & Set_BusA_To(2 downto 1);
+				if XY_Ind = '0' and XY_State /= "00" and Set_BusA_To(2 downto 1) = "10" then
+					RegAddrA_r <= XY_State(1) & "11";
+				end if;
+
+				-- Bus B
+				RegAddrB_r <= Alternate & Set_BusB_To(2 downto 1);
+				if XY_Ind = '0' and XY_State /= "00" and Set_BusB_To(2 downto 1) = "10" then
+					RegAddrB_r <= XY_State(1) & "11";
+				end if;
+
+				-- Address from register
+				RegAddrC <= Alternate & Set_Addr_To(1 downto 0);
+				-- Jump (HL), LD SP,HL
+				if (JumpXY = '1' or LDSPHL = '1') then
+					RegAddrC <= Alternate & "10";
+				end if;
+				if ((JumpXY = '1' or LDSPHL = '1') and XY_State /= "00") or (MCycle = "110") then
+					RegAddrC <= XY_State(1) & "11";
+				end if;
+
+				if I_DJNZ = '1' and Save_ALU_r = '1' and Mode < 2 then
+					IncDecZ <= F_Out(Flag_Z);
+				end if;
+				if (TState = 2 or (TState = 3 and MCycle = "001")) and IncDec_16(2 downto 0) = "100" then
+					if ID16 = 0 then
+						IncDecZ <= '0';
+					else
+						IncDecZ <= '1';
+					end if;
+				end if;
+
+				RegBusA_r <= RegBusA;
+			end if;
+		end if;
+	end process;
+
+	RegAddrA <=
+			-- 16 bit increment/decrement
+			Alternate & IncDec_16(1 downto 0) when (TState = 2 or
+				(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and XY_State = "00" else
+			XY_State(1) & "11" when (TState = 2 or
+				(TState = 3 and MCycle = "001" and IncDec_16(2) = '1')) and IncDec_16(1 downto 0) = "10" else
+			-- EX HL,DL
+			Alternate & "10" when ExchangeDH = '1' and TState = 3 else
+			Alternate & "01" when ExchangeDH = '1' and TState = 4 else
+			-- LDHLSP
+			"010" when LDHLSP = '1' and TState = 4 else
+			-- Bus A / Write
+			RegAddrA_r;
+
+	RegAddrB <=
+			-- EX HL,DL
+			Alternate & "01" when ExchangeDH = '1' and TState = 3 else
+			-- Bus B
+			RegAddrB_r;
+
+	ID16 <= signed(RegBusA) - 1 when IncDec_16(3) = '1' else
+			signed(RegBusA) + 1;
+
+	process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r,
+			ExchangeDH, IncDec_16, MCycle, TState, Wait_n,LDHLSP)
+	begin
+		RegWEH <= '0';
+		RegWEL <= '0';
+		if (TState = 1 and Save_ALU_r = '0') or
+			(Save_ALU_r = '1' and ALU_OP_r /= "0111") then
+			case Read_To_Reg_r is
+			when "10000" | "10001" | "10010" | "10011" | "10100" | "10101" =>
+				RegWEH <= not Read_To_Reg_r(0);
+				RegWEL <= Read_To_Reg_r(0);
+			when others =>
+			end case;
+		end if;
+
+		if ExchangeDH = '1' and (TState = 3 or TState = 4) then
+			RegWEH <= '1';
+			RegWEL <= '1';
+		end if;
+		
+		if LDHLSP = '1' and MCycle = "010" and TState = 4 then
+			RegWEH <= '1';
+			RegWEL <= '1';
+		end if;
+
+		if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
+			case IncDec_16(1 downto 0) is
+			when "00" | "01" | "10" =>
+				RegWEH <= '1';
+				RegWEL <= '1';
+			when others =>
+			end case;
+		end if;
+	end process;
+
+	TmpAddr2 <= std_logic_vector(unsigned(signed(SP) + signed(Save_Mux)));
+
+	process (Save_Mux, RegBusB, RegBusA_r, ID16,
+			ExchangeDH, IncDec_16, MCycle, TState, Wait_n, LDHLSP, SP, TmpAddr2)
+	begin
+		RegDIH <= Save_Mux;
+		RegDIL <= Save_Mux;
+		
+		if LDHLSP = '1' and MCycle = "010" and TState = 4 then
+			RegDIH <= TmpAddr2(15 downto 8);
+			RegDIL <= TmpAddr2(7 downto 0);
+		end if;
+		
+		if ExchangeDH = '1' and TState = 3 then
+			RegDIH <= RegBusB(15 downto 8);
+			RegDIL <= RegBusB(7 downto 0);
+		end if;
+		if ExchangeDH = '1' and TState = 4 then
+			RegDIH <= RegBusA_r(15 downto 8);
+			RegDIL <= RegBusA_r(7 downto 0);
+		end if;
+
+		if IncDec_16(2) = '1' and ((TState = 2 and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
+			RegDIH <= std_logic_vector(ID16(15 downto 8));
+			RegDIL <= std_logic_vector(ID16(7 downto 0));
+		end if;
+	end process;
+
+	Regs : T80_Reg
+		port map(
+			RESET_n => RESET_n,
+			Clk => CLK_n,
+			CEN => ClkEn,
+			WEH => RegWEH,
+			WEL => RegWEL,
+			AddrA => RegAddrA,
+			AddrB => RegAddrB,
+			AddrC => RegAddrC,
+			DIH => RegDIH,
+			DIL => RegDIL,
+			DOAH => RegBusA(15 downto 8),
+			DOAL => RegBusA(7 downto 0),
+			DOBH => RegBusB(15 downto 8),
+			DOBL => RegBusB(7 downto 0),
+			DOCH => RegBusC(15 downto 8),
+			DOCL => RegBusC(7 downto 0),
+			-- savestates
+			SaveStateBus_Din  => SaveStateBus_Din, 
+			SaveStateBus_Adr  => SaveStateBus_Adr, 
+			SaveStateBus_wren => SaveStateBus_wren,
+			SaveStateBus_rst  => SaveStateBus_rst, 
+			SaveStateBus_Dout => reg_wired_or(0)
+		);
+
+---------------------------------------------------------------------------
+--
+-- Buses
+--
+---------------------------------------------------------------------------
+
+	SS_4_BACK(39 downto 32)  <= BusA;
+	SS_4_BACK(47 downto 40)  <= BusB;
+
+	process (CLK_n)
+	begin
+		if CLK_n'event and CLK_n = '1' then
+			
+			if RESET_n = '0' then
+			
+				BusA <= SS_4(39 downto 32); --(others => '0');
+				BusB <= SS_4(47 downto 40); --(others => '0');
+			
+			elsif ClkEn = '1' then
+			case Set_BusB_To is
+			when "0111" =>
+				BusB <= ACC;
+			when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
+				if Set_BusB_To(0) = '1' then
+					BusB <= RegBusB(7 downto 0);
+				else
+					BusB <= RegBusB(15 downto 8);
+				end if;
+			when "0110" =>
+				BusB <= DI_Reg;
+			when "1000" =>
+				BusB <= std_logic_vector(SP(7 downto 0));
+			when "1001" =>
+				BusB <= std_logic_vector(SP(15 downto 8));
+			when "1010" =>
+				BusB <= "00000001";
+			when "1011" =>
+				BusB <= F;
+			when "1100" =>
+				BusB <= std_logic_vector(PC(7 downto 0));
+			when "1101" =>
+				BusB <= std_logic_vector(PC(15 downto 8));
+			when "1110" =>
+				BusB <= "00000000";
+			when others =>
+				BusB <= "--------";
+			end case;
+
+			case Set_BusA_To is
+			when "0111" =>
+				BusA <= ACC;
+			when "0000" | "0001" | "0010" | "0011" | "0100" | "0101" =>
+				if Set_BusA_To(0) = '1' then
+					BusA <= RegBusA(7 downto 0);
+				else
+					BusA <= RegBusA(15 downto 8);
+				end if;
+			when "0110" =>
+				BusA <= DI_Reg;
+			when "1000" =>
+				BusA <= std_logic_vector(SP(7 downto 0));
+			when "1001" =>
+				BusA <= std_logic_vector(SP(15 downto 8));
+			when "1010" =>
+				BusA <= "00000000";
+			when others =>
+				BusA <= "--------";
+			end case;
+			if XYbit_undoc='1' then
+				BusA <= DI_Reg;
+				BusB <= DI_Reg;
+			end if;
+			end if;
+		end if;
+	end process;
+
+---------------------------------------------------------------------------
+--
+-- Generate external control signals
+--
+---------------------------------------------------------------------------
+
+	SS_4_BACK(48)  <= RFSH_n;
+
+	process (CLK_n)
+	begin
+		if CLK_n'event and CLK_n = '1' then
+			if RESET_n = '0' then
+				RFSH_n <= SS_4(48); --'1';
+			elsif CEN = '1' then
+			if MCycle = "001" and ((TState = 2  and Wait_n = '1') or TState = 3) then
+				RFSH_n <= '0';
+			else
+				RFSH_n <= '1';
+			end if;
+			end if;
+		end if;
+	end process;
+
+	MC <= std_logic_vector(MCycle);
+	TS <= std_logic_vector(TState);
+	DI_Reg <= DI;
+	HALT_n <= not Halt_FF;
+	BUSAK_n <= not BusAck;
+	IntCycle_n <= not IntCycle;
+	IntE <= IntE_FF1;
+	IORQ <= IORQ_i;
+	Stop <= I_DJNZ;
+
+-------------------------------------------------------------------------
+--
+-- Syncronise inputs
+--
+-------------------------------------------------------------------------
+
+	SS_4_BACK(49) <= BusReq_s;
+	SS_4_BACK(50) <= INT_s;   
+	SS_4_BACK(51) <= NMI_s;   
+	SS_4_BACK(52) <= OldNMI_n;
+
+	process (CLK_n)
+	begin
+		if CLK_n'event and CLK_n = '1' then
+			if RESET_n = '0' then
+				BusReq_s <= SS_4(49); -- '0';
+				INT_s    <= SS_4(50); -- '0';
+				NMI_s    <= SS_4(51); -- '0';
+				OldNMI_n <= SS_4(52); -- '0';
+			elsif CEN = '1' then
+				BusReq_s <= not BUSRQ_n;
+				INT_s <= not INT_n;
+				if NMICycle = '1' then
+					NMI_s <= '0';
+				elsif NMI_n = '0' and OldNMI_n = '1' then
+					NMI_s <= '1';
+				end if;
+				OldNMI_n <= NMI_n;
+			end if;
+		end if;
+	end process;
+
+-------------------------------------------------------------------------
+--
+-- Main state machine
+--
+-------------------------------------------------------------------------
+
+	SS_3_BACK(41 downto 39) 	<= MCycle 		;
+	SS_3_BACK(44 downto 42) 	<= std_logic_vector(TState);
+	SS_3_BACK(47 downto 45) 	<= Pre_XY_F_M  ;
+	SS_3_BACK(48) 					<= Halt_FF 		;
+	SS_3_BACK(49) 					<= BusAck  		;
+	SS_3_BACK(50) 					<= NMICycle 	;
+	SS_3_BACK(51) 					<= IntCycle 	;
+	SS_3_BACK(52) 					<= IntE_FF1 	;
+	SS_3_BACK(53) 					<= IntE_FF2 	;
+	SS_3_BACK(54) 					<= No_BTR 		;
+	SS_3_BACK(55) 					<= Auto_Wait_t1;
+	SS_3_BACK(56) 					<= Auto_Wait_t2;
+	SS_3_BACK(57) 					<= M1_n 			;
+
+	process (CLK_n)
+	begin
+		if CLK_n'event and CLK_n = '1' then
+		if RESET_n = '0' then
+				MCycle 			<= SS_3(41 downto 39); -- "001";
+				TState 			<= unsigned(SS_3(44 downto 42)); -- "000";
+				Pre_XY_F_M  	<= SS_3(47 downto 45); -- "000";
+				Halt_FF 			<= SS_3(48); -- '0';
+				BusAck  			<= SS_3(49); -- '0';
+				NMICycle 		<= SS_3(50); -- '0';
+				IntCycle 		<= SS_3(51); -- '0';
+				IntE_FF1 		<= SS_3(52); -- '0';
+				IntE_FF2 		<= SS_3(53); -- '0';
+				No_BTR 			<= SS_3(54); -- '0';
+				Auto_Wait_t1 	<= SS_3(55); -- '0';
+				Auto_Wait_t2 	<= SS_3(56); -- '0';
+				M1_n 				<= SS_3(57); -- '1';
+			elsif CEN = '1' then
+			Auto_Wait_t1 <= Auto_Wait;
+			Auto_Wait_t2 <= Auto_Wait_t1;
+			No_BTR <= (I_BT and (not IR(4) or not F(Flag_P))) or
+					(I_BC and (not IR(4) or F(Flag_Z) or not F(Flag_P))) or
+					(I_BTR and (not IR(4) or F(Flag_Z)));
+			if TState = 1 then
+				if (Mode = 3 and INT_n = '0' and isGBC = '0') then
+					Halt_FF <= '0'; --GB: Exit Halt here so interrupt or next instruction starts earlier
+				end if;
+			end if;
+			if TState = 2 then
+				if SetEI = '1' then
+					IntE_FF1 <= '1';
+					IntE_FF2 <= '1';
+				end if;
+				if I_RETN = '1' then
+					IntE_FF1 <= IntE_FF2;
+				end if;
+			end if;
+			if TState = 3 then
+				if SetDI = '1' then
+					IntE_FF1 <= '0';
+					IntE_FF2 <= '0';
+				end if;
+			end if;
+			if IntCycle = '1' or NMICycle = '1' then
+				Halt_FF <= '0';
+			end if;
+			if MCycle = "001" and TState = 2 and Wait_n = '1' then
+				M1_n <= '1';
+			end if;
+			if BusReq_s = '1' and BusAck = '1' then
+			else
+				BusAck <= '0';
+				if TState = 2 and Wait_n = '0' then
+				elsif T_Res = '1' then
+					if Halt = '1' and  ( not(Mode = 3 and INT_n = '0' and IntE_FF1 = '0')) then  -- halt bug when Mode = 3 , INT_n = '0' and IME=0
+						Halt_FF <= '1';
+					end if;
+					if BusReq_s = '1' then
+						BusAck <= '1';
+					else
+						TState <= "001";
+						if (IntCycle = '1' and Mode = 3) then -- GB: read interrupt at MCycle 3
+							if (MCycle = "010") then
+								M1_n <= '0';
+							else
+								M1_n <= '1';
+							end if;
+						end if;
+						if NextIs_XY_Fetch = '1' then
+							MCycle <= "110";
+							Pre_XY_F_M <= MCycle;
+							if IR = "00110110" and Mode = 0 then
+								Pre_XY_F_M <= "010";
+							end if;
+						elsif (MCycle = "111") or
+							(MCycle = "110" and Mode = 1 and ISet /= "01") then
+							MCycle <= std_logic_vector(unsigned(Pre_XY_F_M) + 1);
+						elsif (MCycle = MCycles) or
+							No_BTR = '1' or
+							(MCycle = "010" and I_DJNZ = '1' and IncDecZ = '1') then
+							M1_n <= '0';
+							MCycle <= "001";
+							IntCycle <= '0';
+							NMICycle <= '0';
+							if NMI_s = '1' and Prefix = "00" then
+								NMICycle <= '1';
+								IntE_FF1 <= '0';
+							elsif (IntE_FF1 = '1' and INT_s = '1')  and Prefix = "00" and SetEI = '0'
+									and ((MCycle = "001" and Halt_FF = '0') or Mode /= 3) then -- GB: Interrupt only on single cycle instructions and not Halted
+								IntCycle <= '1';
+								IntE_FF1 <= '0';
+								IntE_FF2 <= '0';
+							elsif (Halt_FF = '1' and INT_s = '1' and Mode = 3) then
+								Halt_FF <= '0';
+							end if;
+						else
+							MCycle <= std_logic_vector(unsigned(MCycle) + 1);
+						end if;
+					end if;
+				else
+					if Auto_Wait = '1' nand Auto_Wait_t2 = '0' then
+
+						TState <= TState + 1;
+					end if;
+				end if;
+			end if;
+			if TState = 0 then
+				M1_n <= '0';
+			end if;
+			end if;
+		end if;
+	end process;
+
+	process (IntCycle, NMICycle, MCycle)
+	begin
+		Auto_Wait <= '0';
+		if (Mode /= 3 and (IntCycle = '1' or NMICycle = '1')) then
+			if MCycle = "001" then
+				Auto_Wait <= '1';
+			end if;
+		end if;
+	end process;
+
+end;