Add Repo: zhan6841_FPGA-Accelerator-for-AES-LeNet-VGG16

zhan6841_FPGA-Accelerator-for-AES-LeNet-VGG16/AES/AES_DEC.v

@@ -0,0 +1,85 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 12/05/2017 04:35:07 AM
+// Design Name: 
+// Module Name: AES_DEC
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module AES_DEC(
+    Din, Key, Dout, Drdy, Krdy, RSTn, EN, CLK, BSY, Dvld
+    );
+    input  [127:0] Din;  // Data input
+      input  [127:0] Key;  // Key input
+      output [127:0] Dout; // Data output
+      input  Drdy;         // Data input ready
+      input  Krdy;         // Key input ready
+      input  RSTn;         // Reset (Low active)
+      input  EN;           // AES circuit enable
+      input  CLK;          // System clock
+      output BSY;          // Busy signal
+      output Dvld;         // Data output valid
+    
+      reg  [127:0] Drg;    // Data register
+      reg  [127:0] Krg;    // Key register
+      reg  [127:0] KrgX;   // Temporary key Register
+      reg  [9:0]   Rrg;    // Round counter
+      reg  Dvldrg, BSYrg;
+      wire [127:0] Dnext, Knext;
+    
+      DecCore DC (Drg, KrgX, Rrg, Dnext, Knext);
+    
+      assign Dvld = Dvldrg;
+      assign Dout = Drg;
+      assign BSY  = BSYrg;
+    
+      always @(posedge CLK) begin
+        if (RSTn == 0) begin
+          Rrg    <= 10'b1000000000;
+          Dvldrg <= 0;
+          BSYrg  <= 0;
+        end
+        else if (EN == 1) begin
+          if (BSYrg == 0) begin
+            if (Krdy == 1) begin
+              Krg    <= Key;
+              KrgX   <= Key;
+              Dvldrg <= 0;
+            end
+            else if (Drdy == 1) begin
+              KrgX   <= Knext;
+              Drg    <= Din ^ Krg;
+              Rrg <= {Rrg[0], Rrg[9:1]};
+              Dvldrg <= 0;
+              BSYrg  <= 1;
+            end
+          end
+          else begin
+            Drg <= Dnext;
+            if (Rrg[9] == 1) begin
+              KrgX   <= Krg;
+              Dvldrg <= 1;
+              BSYrg  <= 0;
+            end
+            else begin
+              Rrg    <= {Rrg[0], Rrg[9:1]};
+              KrgX   <= Knext;
+            end
+          end
+        end
+      end   
+endmodule

zhan6841_FPGA-Accelerator-for-AES-LeNet-VGG16/AES/AES_ENC.v

@@ -0,0 +1,85 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 12/05/2017 04:34:04 AM
+// Design Name: 
+// Module Name: AES_ENC
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module AES_ENC(
+    Din, Key, Dout, Drdy, Krdy, RSTn, EN, CLK, BSY, Dvld
+    );
+    input  [127:0] Din;  // Data input
+      input  [127:0] Key;  // Key input
+      output [127:0] Dout; // Data output
+      input  Drdy;         // Data input ready
+      input  Krdy;         // Key input ready
+      input  RSTn;         // Reset (Low active)
+      input  EN;           // AES circuit enable
+      input  CLK;          // System clock
+      output BSY;          // Busy signal
+      output Dvld;         // Data output valid
+    
+      reg  [127:0] Drg;    // Data register
+      reg  [127:0] Krg;    // Key register
+      reg  [127:0] KrgX;   // Temporary key Register
+      reg  [9:0]   Rrg;    // Round counter
+      reg  Dvldrg, BSYrg;
+      wire [127:0] Dnext, Knext;
+    
+      EncCore EC (Drg, KrgX, Rrg, Dnext, Knext);
+    
+      assign Dvld = Dvldrg;
+      assign Dout = Drg;
+      assign BSY  = BSYrg;
+    
+      always @(posedge CLK) begin
+        if (RSTn == 0) begin
+          Rrg    <= 10'b0000000001;
+          Dvldrg <= 0;
+          BSYrg  <= 0;
+        end
+        else if (EN == 1) begin
+           if (BSYrg == 0) begin
+            if (Krdy == 1) begin
+              Krg    <= Key;
+              KrgX   <= Key;
+              Dvldrg <= 0;
+            end
+            else if (Drdy == 1) begin
+              Rrg    <= {Rrg[8:0], Rrg[9]};
+              KrgX   <= Knext;
+              Drg    <= Din ^ Krg;
+              Dvldrg <= 0;
+              BSYrg  <= 1;
+            end
+          end
+          else begin
+            Drg <= Dnext;
+            if (Rrg[0] == 1) begin
+              KrgX   <= Krg;
+              Dvldrg <= 1;
+              BSYrg  <= 0;
+            end
+            else begin
+              Rrg    <= {Rrg[8:0], Rrg[9]};
+              KrgX   <= Knext;
+            end
+          end
+        end
+      end
+endmodule

zhan6841_FPGA-Accelerator-for-AES-LeNet-VGG16/AES/DecCore.v

@@ -0,0 +1,74 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 12/05/2017 04:33:03 AM
+// Design Name: 
+// Module Name: DecCore
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module DecCore(
+    di, ki, Rrg, do, ko
+    );
+    input  [127:0] di;
+      input  [127:0] ki;
+      input  [9:0]   Rrg;
+      output [127:0] do;
+      output [127:0] ko;
+    
+      wire   [127:0] sb, sr, mx, dx;
+      wire   [31:0]  so;
+    
+      InvMixColumns MX3 (di[127:96], mx[127:96]);
+      InvMixColumns MX2 (di[ 95:64], mx[ 95:64]);
+      InvMixColumns MX1 (di[ 63:32], mx[ 63:32]);
+      InvMixColumns MX0 (di[ 31: 0], mx[ 31: 0]);
+    
+      assign dx = (Rrg[8] == 1)? di: mx;
+      assign sr = {dx[127:120], dx[ 23: 16], dx[ 47: 40], dx[ 71: 64],
+                   dx[ 95: 88], dx[119:112], dx[ 15:  8], dx[ 39: 32],
+                   dx[ 63: 56], dx[ 87: 80], dx[111:104], dx[  7:  0],
+                   dx[ 31: 24], dx[ 55: 48], dx[ 79: 72], dx[103: 96]};
+    
+      InvSubBytes SB3 (sr[127:96], sb[127:96]);
+      InvSubBytes SB2 (sr[ 95:64], sb[ 95:64]);
+      InvSubBytes SB1 (sr[ 63:32], sb[ 63:32]);
+      InvSubBytes SB0 (sr[ 31: 0], sb[ 31: 0]);
+    
+      assign do = sb ^ ki;
+    
+      function [7:0] rcon;
+      input [9:0] x;
+        casex (x)
+          10'bxxxxxxxxx1: rcon = 8'h01;
+          10'bxxxxxxxx1x: rcon = 8'h02;
+          10'bxxxxxxx1xx: rcon = 8'h04;
+          10'bxxxxxx1xxx: rcon = 8'h08;
+          10'bxxxxx1xxxx: rcon = 8'h10;
+          10'bxxxx1xxxxx: rcon = 8'h20;
+          10'bxxx1xxxxxx: rcon = 8'h40;
+          10'bxx1xxxxxxx: rcon = 8'h80;
+          10'bx1xxxxxxxx: rcon = 8'h1b;
+          10'b1xxxxxxxxx: rcon = 8'h36;
+        endcase
+      endfunction
+    
+      SubBytes SBK ({ko[23:16], ko[15:8], ko[7:0], ko[31:24]}, so);
+      assign ko[127:96] = ki[127:96] ^ {so[31:24] ^ rcon(Rrg), so[23: 0]};
+      assign ko[ 95:64] = ki[ 95:64] ^ ki[127:96];
+      assign ko[ 63:32] = ki[ 63:32] ^ ki[ 95:64];
+      assign ko[ 31: 0] = ki[ 31: 0] ^ ki[ 63:32];
+endmodule

zhan6841_FPGA-Accelerator-for-AES-LeNet-VGG16/AES/EncCore.v

@@ -0,0 +1,74 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 12/05/2017 04:31:23 AM
+// Design Name: 
+// Module Name: EncCore
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module EncCore(
+    di, ki, Rrg, do, ko
+    );
+    input  [127:0] di;
+      input  [127:0] ki;
+      input  [9:0]   Rrg;
+      output [127:0] do;
+      output [127:0] ko;
+    
+      wire   [127:0] sb, sr, mx;
+      wire   [31:0]  so;
+    
+      SubBytes SB3 (di[127:96], sb[127:96]);
+      SubBytes SB2 (di[ 95:64], sb[ 95:64]);
+      SubBytes SB1 (di[ 63:32], sb[ 63:32]);
+      SubBytes SB0 (di[ 31: 0], sb[ 31: 0]);
+    
+      assign sr = {sb[127:120], sb[ 87: 80], sb[ 47: 40], sb[  7:  0],
+                   sb[ 95: 88], sb[ 55: 48], sb[ 15:  8], sb[103: 96],
+                   sb[ 63: 56], sb[ 23: 16], sb[111:104], sb[ 71: 64],
+                   sb[ 31: 24], sb[119:112], sb[ 79: 72], sb[ 39: 32]};
+    
+      MixColumns MX3 (sr[127:96], mx[127:96]);
+      MixColumns MX2 (sr[ 95:64], mx[ 95:64]);
+      MixColumns MX1 (sr[ 63:32], mx[ 63:32]);
+      MixColumns MX0 (sr[ 31: 0], mx[ 31: 0]);
+    
+      assign do = ((Rrg[0] == 1)? sr: mx) ^ ki;
+    
+      function [7:0] rcon;
+      input [9:0] x;
+        casex (x)
+          10'bxxxxxxxxx1: rcon = 8'h01;
+          10'bxxxxxxxx1x: rcon = 8'h02;
+          10'bxxxxxxx1xx: rcon = 8'h04;
+          10'bxxxxxx1xxx: rcon = 8'h08;
+          10'bxxxxx1xxxx: rcon = 8'h10;
+          10'bxxxx1xxxxx: rcon = 8'h20;
+          10'bxxx1xxxxxx: rcon = 8'h40;
+          10'bxx1xxxxxxx: rcon = 8'h80;
+          10'bx1xxxxxxxx: rcon = 8'h1b;
+          10'b1xxxxxxxxx: rcon = 8'h36;
+        endcase
+      endfunction
+    
+      SubBytes SBK ({ki[23:16], ki[15:8], ki[7:0], ki[31:24]}, so);
+    
+      assign ko[127:96] = ki[127:96] ^ {so[31:24] ^ rcon(Rrg), so[23: 0]};
+      assign ko[ 95:64] = ki[ 95:64] ^ ko[127:96];
+      assign ko[ 63:32] = ki[ 63:32] ^ ko[ 95:64];
+      assign ko[ 31: 0] = ki[ 31: 0] ^ ko[ 63:32];
+endmodule

zhan6841_FPGA-Accelerator-for-AES-LeNet-VGG16/AES/InvMixColumns.v

@@ -0,0 +1,83 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 12/05/2017 04:28:25 AM
+// Design Name: 
+// Module Name: InvMixColumns
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module InvMixColumns(
+    x, y
+    );
+    input  [31:0]  x;
+    output [31:0]  y;
+    
+    wire [7:0] a3, a2, a1, a0, b3, b2, b1, b0;
+    wire [7:0] c3, c2, c1, c0, d3, d2, d1, d0;
+    
+    assign a3 = x[31:24];
+    assign a2 = x[23:16];
+    assign a1 = x[15: 8];
+    assign a0 = x[ 7: 0];
+    
+    assign b3 = a3 ^ a2;
+    assign b2 = a2 ^ a1;
+    assign b1 = a1 ^ a0;
+    assign b0 = a0 ^ a3;
+    
+    assign c3 = {a2[7] ^ b1[7] ^ b3[6],
+                 a2[6] ^ b1[6] ^ b3[5],
+                 a2[5] ^ b1[5] ^ b3[4],
+                 a2[4] ^ b1[4] ^ b3[3] ^ b3[7],
+                 a2[3] ^ b1[3] ^ b3[2] ^ b3[7],
+                 a2[2] ^ b1[2] ^ b3[1],
+                 a2[1] ^ b1[1] ^ b3[0] ^ b3[7],
+                 a2[0] ^ b1[0] ^ b3[7]};
+    assign c2 = {a3[7] ^ b1[7] ^ b2[6],
+                 a3[6] ^ b1[6] ^ b2[5],
+                 a3[5] ^ b1[5] ^ b2[4],
+                 a3[4] ^ b1[4] ^ b2[3] ^ b2[7],
+                 a3[3] ^ b1[3] ^ b2[2] ^ b2[7],
+                 a3[2] ^ b1[2] ^ b2[1],
+                 a3[1] ^ b1[1] ^ b2[0] ^ b2[7],
+                 a3[0] ^ b1[0] ^ b2[7]};
+    assign c1 = {a0[7] ^ b3[7] ^ b1[6],
+                 a0[6] ^ b3[6] ^ b1[5],
+                 a0[5] ^ b3[5] ^ b1[4],
+                 a0[4] ^ b3[4] ^ b1[3] ^ b1[7],
+                 a0[3] ^ b3[3] ^ b1[2] ^ b1[7],
+                 a0[2] ^ b3[2] ^ b1[1],
+                 a0[1] ^ b3[1] ^ b1[0] ^ b1[7],
+                 a0[0] ^ b3[0] ^ b1[7]};
+    assign c0 = {a1[7] ^ b3[7] ^ b0[6],
+                 a1[6] ^ b3[6] ^ b0[5],
+                 a1[5] ^ b3[5] ^ b0[4],
+                 a1[4] ^ b3[4] ^ b0[3] ^ b0[7],
+                 a1[3] ^ b3[3] ^ b0[2] ^ b0[7],
+                 a1[2] ^ b3[2] ^ b0[1],
+                 a1[1] ^ b3[1] ^ b0[0] ^ b0[7],
+                 a1[0] ^ b3[0] ^ b0[7]};
+    assign d3 = {c3[5], c3[4], c3[3] ^ c3[7], c3[2] ^ c3[7] ^ c3[6],
+                 c3[1] ^ c3[6], c3[0] ^ c3[7], c3[7] ^ c3[6], c3[6]};
+    assign d2 = {c2[5], c2[4], c2[3] ^ c2[7], c2[2] ^ c2[7] ^ c2[6],
+                 c2[1] ^ c2[6], c2[0] ^ c2[7], c2[7] ^ c2[6], c2[6]};
+    assign d1 = {c1[5], c1[4], c1[3] ^ c1[7], c1[2] ^ c1[7] ^ c1[6],
+                 c1[1] ^ c1[6], c1[0] ^ c1[7], c1[7] ^ c1[6], c1[6]};
+    assign d0 = {c0[5], c0[4], c0[3] ^ c0[7], c0[2] ^ c0[7] ^ c0[6],
+                 c0[1] ^ c0[6], c0[0] ^ c0[7], c0[7] ^ c0[6], c0[6]};
+    assign y  = {d3 ^ d1 ^ c3, d2 ^ d0 ^ c2, d3 ^ d1 ^ c1, d2 ^ d0 ^ c0};
+endmodule

zhan6841_FPGA-Accelerator-for-AES-LeNet-VGG16/AES/InvSubBytes.v

@@ -0,0 +1,68 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 12/05/2017 04:19:48 AM
+// Design Name: 
+// Module Name: InvSubBytes
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module InvSubBytes(
+    x, y
+    );
+    input  [31:0] x;
+    output [31:0] y;
+    
+    function [7:0] S;
+    input    [7:0] x;
+      case (x)
+          0:S= 82;   1:S=  9;   2:S=106;   3:S=213;   4:S= 48;   5:S= 54;   6:S=165;   7:S= 56;
+          8:S=191;   9:S= 64;  10:S=163;  11:S=158;  12:S=129;  13:S=243;  14:S=215;  15:S=251;
+         16:S=124;  17:S=227;  18:S= 57;  19:S=130;  20:S=155;  21:S= 47;  22:S=255;  23:S=135;
+         24:S= 52;  25:S=142;  26:S= 67;  27:S= 68;  28:S=196;  29:S=222;  30:S=233;  31:S=203;
+         32:S= 84;  33:S=123;  34:S=148;  35:S= 50;  36:S=166;  37:S=194;  38:S= 35;  39:S= 61;
+         40:S=238;  41:S= 76;  42:S=149;  43:S= 11;  44:S= 66;  45:S=250;  46:S=195;  47:S= 78;
+         48:S=  8;  49:S= 46;  50:S=161;  51:S=102;  52:S= 40;  53:S=217;  54:S= 36;  55:S=178;
+         56:S=118;  57:S= 91;  58:S=162;  59:S= 73;  60:S=109;  61:S=139;  62:S=209;  63:S= 37;
+         64:S=114;  65:S=248;  66:S=246;  67:S=100;  68:S=134;  69:S=104;  70:S=152;  71:S= 22;
+         72:S=212;  73:S=164;  74:S= 92;  75:S=204;  76:S= 93;  77:S=101;  78:S=182;  79:S=146;
+         80:S=108;  81:S=112;  82:S= 72;  83:S= 80;  84:S=253;  85:S=237;  86:S=185;  87:S=218;
+         88:S= 94;  89:S= 21;  90:S= 70;  91:S= 87;  92:S=167;  93:S=141;  94:S=157;  95:S=132;
+         96:S=144;  97:S=216;  98:S=171;  99:S=  0; 100:S=140; 101:S=188; 102:S=211; 103:S= 10;
+        104:S=247; 105:S=228; 106:S= 88; 107:S=  5; 108:S=184; 109:S=179; 110:S= 69; 111:S=  6;
+        112:S=208; 113:S= 44; 114:S= 30; 115:S=143; 116:S=202; 117:S= 63; 118:S= 15; 119:S=  2;
+        120:S=193; 121:S=175; 122:S=189; 123:S=  3; 124:S=  1; 125:S= 19; 126:S=138; 127:S=107;
+        128:S= 58; 129:S=145; 130:S= 17; 131:S= 65; 132:S= 79; 133:S=103; 134:S=220; 135:S=234;
+        136:S=151; 137:S=242; 138:S=207; 139:S=206; 140:S=240; 141:S=180; 142:S=230; 143:S=115;
+        144:S=150; 145:S=172; 146:S=116; 147:S= 34; 148:S=231; 149:S=173; 150:S= 53; 151:S=133;
+        152:S=226; 153:S=249; 154:S= 55; 155:S=232; 156:S= 28; 157:S=117; 158:S=223; 159:S=110;
+        160:S= 71; 161:S=241; 162:S= 26; 163:S=113; 164:S= 29; 165:S= 41; 166:S=197; 167:S=137;
+        168:S=111; 169:S=183; 170:S= 98; 171:S= 14; 172:S=170; 173:S= 24; 174:S=190; 175:S= 27;
+        176:S=252; 177:S= 86; 178:S= 62; 179:S= 75; 180:S=198; 181:S=210; 182:S=121; 183:S= 32;
+        184:S=154; 185:S=219; 186:S=192; 187:S=254; 188:S=120; 189:S=205; 190:S= 90; 191:S=244;
+        192:S= 31; 193:S=221; 194:S=168; 195:S= 51; 196:S=136; 197:S=  7; 198:S=199; 199:S= 49;
+        200:S=177; 201:S= 18; 202:S= 16; 203:S= 89; 204:S= 39; 205:S=128; 206:S=236; 207:S= 95;
+        208:S= 96; 209:S= 81; 210:S=127; 211:S=169; 212:S= 25; 213:S=181; 214:S= 74; 215:S= 13;
+        216:S= 45; 217:S=229; 218:S=122; 219:S=159; 220:S=147; 221:S=201; 222:S=156; 223:S=239;
+        224:S=160; 225:S=224; 226:S= 59; 227:S= 77; 228:S=174; 229:S= 42; 230:S=245; 231:S=176;
+        232:S=200; 233:S=235; 234:S=187; 235:S= 60; 236:S=131; 237:S= 83; 238:S=153; 239:S= 97;
+        240:S= 23; 241:S= 43; 242:S=  4; 243:S=126; 244:S=186; 245:S=119; 246:S=214; 247:S= 38;
+        248:S=225; 249:S=105; 250:S= 20; 251:S= 99; 252:S= 85; 253:S= 33; 254:S= 12; 255:S=125; 
+      endcase
+    endfunction
+    
+    assign y = {S(x[31:24]), S(x[23:16]), S(x[15: 8]), S(x[ 7: 0])};
+endmodule

zhan6841_FPGA-Accelerator-for-AES-LeNet-VGG16/AES/MixColumns.v

@@ -0,0 +1,73 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 12/05/2017 04:23:29 AM
+// Design Name: 
+// Module Name: MixColumns
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module MixColumns(
+    x, y
+    );
+    input  [31:0]  x;
+    output [31:0]  y;
+    
+    wire [7:0] a3, a2, a1, a0, b3, b2, b1, b0;
+    
+    assign a3 = x[31:24];
+    assign a2 = x[23:16];
+    assign a1 = x[15: 8];
+    assign a0 = x[ 7: 0];
+    
+    assign b3 = a3 ^ a2;
+    assign b2 = a2 ^ a1;
+    assign b1 = a1 ^ a0;
+    assign b0 = a0 ^ a3;
+    
+    assign y = {a2[7] ^ b1[7] ^ b3[6],
+                a2[6] ^ b1[6] ^ b3[5],
+                a2[5] ^ b1[5] ^ b3[4],
+                a2[4] ^ b1[4] ^ b3[3] ^ b3[7],
+                a2[3] ^ b1[3] ^ b3[2] ^ b3[7],
+                a2[2] ^ b1[2] ^ b3[1],
+                a2[1] ^ b1[1] ^ b3[0] ^ b3[7],
+                a2[0] ^ b1[0] ^ b3[7],
+                a3[7] ^ b1[7] ^ b2[6],
+                a3[6] ^ b1[6] ^ b2[5],
+                a3[5] ^ b1[5] ^ b2[4],
+                a3[4] ^ b1[4] ^ b2[3] ^ b2[7],
+                a3[3] ^ b1[3] ^ b2[2] ^ b2[7],
+                a3[2] ^ b1[2] ^ b2[1],
+                a3[1] ^ b1[1] ^ b2[0] ^ b2[7],
+                a3[0] ^ b1[0] ^ b2[7],
+                a0[7] ^ b3[7] ^ b1[6],
+                a0[6] ^ b3[6] ^ b1[5],
+                a0[5] ^ b3[5] ^ b1[4],
+                a0[4] ^ b3[4] ^ b1[3] ^ b1[7],
+                a0[3] ^ b3[3] ^ b1[2] ^ b1[7],
+                a0[2] ^ b3[2] ^ b1[1],
+                a0[1] ^ b3[1] ^ b1[0] ^ b1[7],
+                a0[0] ^ b3[0] ^ b1[7],
+                a1[7] ^ b3[7] ^ b0[6],
+                a1[6] ^ b3[6] ^ b0[5],
+                a1[5] ^ b3[5] ^ b0[4],
+                a1[4] ^ b3[4] ^ b0[3] ^ b0[7],
+                a1[3] ^ b3[3] ^ b0[2] ^ b0[7],
+                a1[2] ^ b3[2] ^ b0[1],
+                a1[1] ^ b3[1] ^ b0[0] ^ b0[7],
+                a1[0] ^ b3[0] ^ b0[7]};
+endmodule

zhan6841_FPGA-Accelerator-for-AES-LeNet-VGG16/AES/README.md

@@ -0,0 +1 @@
+

zhan6841_FPGA-Accelerator-for-AES-LeNet-VGG16/AES/SubBytes.v

@@ -0,0 +1,68 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 12/05/2017 04:10:53 AM
+// Design Name: 
+// Module Name: SubBytes
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module SubBytes(
+    x, y
+    );
+    input  [31:0] x;
+    output [31:0] y;
+        
+    function [7:0] S;
+    input    [7:0] x;
+      case (x)
+          0:S= 99;   1:S=124;   2:S=119;   3:S=123;   4:S=242;   5:S=107;   6:S=111;   7:S=197;
+          8:S= 48;   9:S=  1;  10:S=103;  11:S= 43;  12:S=254;  13:S=215;  14:S=171;  15:S=118;
+         16:S=202;  17:S=130;  18:S=201;  19:S=125;  20:S=250;  21:S= 89;  22:S= 71;  23:S=240;
+         24:S=173;  25:S=212;  26:S=162;  27:S=175;  28:S=156;  29:S=164;  30:S=114;  31:S=192;
+         32:S=183;  33:S=253;  34:S=147;  35:S= 38;  36:S= 54;  37:S= 63;  38:S=247;  39:S=204;
+         40:S= 52;  41:S=165;  42:S=229;  43:S=241;  44:S=113;  45:S=216;  46:S= 49;  47:S= 21;
+         48:S=  4;  49:S=199;  50:S= 35;  51:S=195;  52:S= 24;  53:S=150;  54:S=  5;  55:S=154;
+         56:S=  7;  57:S= 18;  58:S=128;  59:S=226;  60:S=235;  61:S= 39;  62:S=178;  63:S=117;
+         64:S=  9;  65:S=131;  66:S= 44;  67:S= 26;  68:S= 27;  69:S=110;  70:S= 90;  71:S=160;
+         72:S= 82;  73:S= 59;  74:S=214;  75:S=179;  76:S= 41;  77:S=227;  78:S= 47;  79:S=132;
+         80:S= 83;  81:S=209;  82:S=  0;  83:S=237;  84:S= 32;  85:S=252;  86:S=177;  87:S= 91;
+         88:S=106;  89:S=203;  90:S=190;  91:S= 57;  92:S= 74;  93:S= 76;  94:S= 88;  95:S=207;
+         96:S=208;  97:S=239;  98:S=170;  99:S=251; 100:S= 67; 101:S= 77; 102:S= 51; 103:S=133;
+        104:S= 69; 105:S=249; 106:S=  2; 107:S=127; 108:S= 80; 109:S= 60; 110:S=159; 111:S=168;
+        112:S= 81; 113:S=163; 114:S= 64; 115:S=143; 116:S=146; 117:S=157; 118:S= 56; 119:S=245;
+        120:S=188; 121:S=182; 122:S=218; 123:S= 33; 124:S= 16; 125:S=255; 126:S=243; 127:S=210;
+        128:S=205; 129:S= 12; 130:S= 19; 131:S=236; 132:S= 95; 133:S=151; 134:S= 68; 135:S= 23;
+        136:S=196; 137:S=167; 138:S=126; 139:S= 61; 140:S=100; 141:S= 93; 142:S= 25; 143:S=115;
+        144:S= 96; 145:S=129; 146:S= 79; 147:S=220; 148:S= 34; 149:S= 42; 150:S=144; 151:S=136;
+        152:S= 70; 153:S=238; 154:S=184; 155:S= 20; 156:S=222; 157:S= 94; 158:S= 11; 159:S=219;
+        160:S=224; 161:S= 50; 162:S= 58; 163:S= 10; 164:S= 73; 165:S=  6; 166:S= 36; 167:S= 92;
+        168:S=194; 169:S=211; 170:S=172; 171:S= 98; 172:S=145; 173:S=149; 174:S=228; 175:S=121;
+        176:S=231; 177:S=200; 178:S= 55; 179:S=109; 180:S=141; 181:S=213; 182:S= 78; 183:S=169;
+        184:S=108; 185:S= 86; 186:S=244; 187:S=234; 188:S=101; 189:S=122; 190:S=174; 191:S=  8;
+        192:S=186; 193:S=120; 194:S= 37; 195:S= 46; 196:S= 28; 197:S=166; 198:S=180; 199:S=198;
+        200:S=232; 201:S=221; 202:S=116; 203:S= 31; 204:S= 75; 205:S=189; 206:S=139; 207:S=138;
+        208:S=112; 209:S= 62; 210:S=181; 211:S=102; 212:S= 72; 213:S=  3; 214:S=246; 215:S= 14;
+        216:S= 97; 217:S= 53; 218:S= 87; 219:S=185; 220:S=134; 221:S=193; 222:S= 29; 223:S=158;
+        224:S=225; 225:S=248; 226:S=152; 227:S= 17; 228:S=105; 229:S=217; 230:S=142; 231:S=148;
+        232:S=155; 233:S= 30; 234:S=135; 235:S=233; 236:S=206; 237:S= 85; 238:S= 40; 239:S=223;
+        240:S=140; 241:S=161; 242:S=137; 243:S= 13; 244:S=191; 245:S=230; 246:S= 66; 247:S=104;
+        248:S= 65; 249:S=153; 250:S= 45; 251:S= 15; 252:S=176; 253:S= 84; 254:S=187; 255:S= 22;
+      endcase
+    endfunction
+    
+    assign y = {S(x[31:24]), S(x[23:16]), S(x[15: 8]), S(x[ 7: 0])};
+endmodule

zhan6841_FPGA-Accelerator-for-AES-LeNet-VGG16/AES/aes.c

@@ -0,0 +1,6 @@
+
+
+/***************************** Include Files *******************************/
+#include "aes.h"
+
+/************************** Function Definitions ***************************/

zhan6841_FPGA-Accelerator-for-AES-LeNet-VGG16/AES/aes.h

@@ -0,0 +1,88 @@
+
+#ifndef AES_H
+#define AES_H
+
+
+/****************** Include Files ********************/
+#include "xil_types.h"
+#include "xstatus.h"
+
+#define AES_S00_AXI_SLV_REG0_OFFSET 0
+#define AES_S00_AXI_SLV_REG1_OFFSET 4
+#define AES_S00_AXI_SLV_REG2_OFFSET 8
+#define AES_S00_AXI_SLV_REG3_OFFSET 12
+#define AES_S00_AXI_SLV_REG4_OFFSET 16
+#define AES_S00_AXI_SLV_REG5_OFFSET 20
+#define AES_S00_AXI_SLV_REG6_OFFSET 24
+#define AES_S00_AXI_SLV_REG7_OFFSET 28
+#define AES_S00_AXI_SLV_REG8_OFFSET 32
+#define AES_S00_AXI_SLV_REG9_OFFSET 36
+#define AES_S00_AXI_SLV_REG10_OFFSET 40
+#define AES_S00_AXI_SLV_REG11_OFFSET 44
+#define AES_S00_AXI_SLV_REG12_OFFSET 48
+
+
+/**************************** Type Definitions *****************************/
+/**
+ *
+ * Write a value to a AES register. A 32 bit write is performed.
+ * If the component is implemented in a smaller width, only the least
+ * significant data is written.
+ *
+ * @param   BaseAddress is the base address of the AESdevice.
+ * @param   RegOffset is the register offset from the base to write to.
+ * @param   Data is the data written to the register.
+ *
+ * @return  None.
+ *
+ * @note
+ * C-style signature:
+ * 	void AES_mWriteReg(u32 BaseAddress, unsigned RegOffset, u32 Data)
+ *
+ */
+#define AES_mWriteReg(BaseAddress, RegOffset, Data) \
+  	Xil_Out32((BaseAddress) + (RegOffset), (u32)(Data))
+
+/**
+ *
+ * Read a value from a AES register. A 32 bit read is performed.
+ * If the component is implemented in a smaller width, only the least
+ * significant data is read from the register. The most significant data
+ * will be read as 0.
+ *
+ * @param   BaseAddress is the base address of the AES device.
+ * @param   RegOffset is the register offset from the base to write to.
+ *
+ * @return  Data is the data from the register.
+ *
+ * @note
+ * C-style signature:
+ * 	u32 AES_mReadReg(u32 BaseAddress, unsigned RegOffset)
+ *
+ */
+#define AES_mReadReg(BaseAddress, RegOffset) \
+    Xil_In32((BaseAddress) + (RegOffset))
+
+/************************** Function Prototypes ****************************/
+/**
+ *
+ * Run a self-test on the driver/device. Note this may be a destructive test if
+ * resets of the device are performed.
+ *
+ * If the hardware system is not built correctly, this function may never
+ * return to the caller.
+ *
+ * @param   baseaddr_p is the base address of the AES instance to be worked on.
+ *
+ * @return
+ *
+ *    - XST_SUCCESS   if all self-test code passed
+ *    - XST_FAILURE   if any self-test code failed
+ *
+ * @note    Caching must be turned off for this function to work.
+ * @note    Self test may fail if data memory and device are not on the same bus.
+ *
+ */
+XStatus AES_Reg_SelfTest(void * baseaddr_p);
+
+#endif // AES_H

zhan6841_FPGA-Accelerator-for-AES-LeNet-VGG16/AES/aes_selftest.c

@@ -0,0 +1,60 @@
+
+/***************************** Include Files *******************************/
+#include "aes.h"
+#include "xparameters.h"
+#include "stdio.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions ***************************/
+#define READ_WRITE_MUL_FACTOR 0x10
+
+/************************** Function Definitions ***************************/
+/**
+ *
+ * Run a self-test on the driver/device. Note this may be a destructive test if
+ * resets of the device are performed.
+ *
+ * If the hardware system is not built correctly, this function may never
+ * return to the caller.
+ *
+ * @param   baseaddr_p is the base address of the AESinstance to be worked on.
+ *
+ * @return
+ *
+ *    - XST_SUCCESS   if all self-test code passed
+ *    - XST_FAILURE   if any self-test code failed
+ *
+ * @note    Caching must be turned off for this function to work.
+ * @note    Self test may fail if data memory and device are not on the same bus.
+ *
+ */
+XStatus AES_Reg_SelfTest(void * baseaddr_p)
+{
+	u32 baseaddr;
+	int write_loop_index;
+	int read_loop_index;
+	int Index;
+
+	baseaddr = (u32) baseaddr_p;
+
+	xil_printf("******************************\n\r");
+	xil_printf("* User Peripheral Self Test\n\r");
+	xil_printf("******************************\n\n\r");
+
+	/*
+	 * Write to user logic slave module register(s) and read back
+	 */
+	xil_printf("User logic slave module test...\n\r");
+
+	for (write_loop_index = 0 ; write_loop_index < 4; write_loop_index++)
+	  AES_mWriteReg (baseaddr, write_loop_index*4, (write_loop_index+1)*READ_WRITE_MUL_FACTOR);
+	for (read_loop_index = 0 ; read_loop_index < 4; read_loop_index++)
+	  if ( AES_mReadReg (baseaddr, read_loop_index*4) != (read_loop_index+1)*READ_WRITE_MUL_FACTOR){
+	    xil_printf ("Error reading register value at address %x\n", (int)baseaddr + read_loop_index*4);
+	    return XST_FAILURE;
+	  }
+
+	xil_printf("   - slave register write/read passed\n\n\r");
+
+	return XST_SUCCESS;
+}

zhan6841_FPGA-Accelerator-for-AES-LeNet-VGG16/LeNet/LeNet.c

@@ -0,0 +1,6 @@
+
+
+/***************************** Include Files *******************************/
+#include "LeNet.h"
+
+/************************** Function Definitions ***************************/

zhan6841_FPGA-Accelerator-for-AES-LeNet-VGG16/LeNet/LeNet.h

@@ -0,0 +1,81 @@
+
+#ifndef LENET_H
+#define LENET_H
+
+
+/****************** Include Files ********************/
+#include "xil_types.h"
+#include "xstatus.h"
+
+#define LENET_S00_AXI_SLV_REG0_OFFSET 0
+#define LENET_S00_AXI_SLV_REG1_OFFSET 4
+#define LENET_S00_AXI_SLV_REG2_OFFSET 8
+#define LENET_S00_AXI_SLV_REG3_OFFSET 12
+#define LENET_S00_AXI_SLV_REG4_OFFSET 16
+#define LENET_S00_AXI_SLV_REG5_OFFSET 20
+
+
+/**************************** Type Definitions *****************************/
+/**
+ *
+ * Write a value to a LENET register. A 32 bit write is performed.
+ * If the component is implemented in a smaller width, only the least
+ * significant data is written.
+ *
+ * @param   BaseAddress is the base address of the LENETdevice.
+ * @param   RegOffset is the register offset from the base to write to.
+ * @param   Data is the data written to the register.
+ *
+ * @return  None.
+ *
+ * @note
+ * C-style signature:
+ * 	void LENET_mWriteReg(u32 BaseAddress, unsigned RegOffset, u32 Data)
+ *
+ */
+#define LENET_mWriteReg(BaseAddress, RegOffset, Data) \
+  	Xil_Out32((BaseAddress) + (RegOffset), (u32)(Data))
+
+/**
+ *
+ * Read a value from a LENET register. A 32 bit read is performed.
+ * If the component is implemented in a smaller width, only the least
+ * significant data is read from the register. The most significant data
+ * will be read as 0.
+ *
+ * @param   BaseAddress is the base address of the LENET device.
+ * @param   RegOffset is the register offset from the base to write to.
+ *
+ * @return  Data is the data from the register.
+ *
+ * @note
+ * C-style signature:
+ * 	u32 LENET_mReadReg(u32 BaseAddress, unsigned RegOffset)
+ *
+ */
+#define LENET_mReadReg(BaseAddress, RegOffset) \
+    Xil_In32((BaseAddress) + (RegOffset))
+
+/************************** Function Prototypes ****************************/
+/**
+ *
+ * Run a self-test on the driver/device. Note this may be a destructive test if
+ * resets of the device are performed.
+ *
+ * If the hardware system is not built correctly, this function may never
+ * return to the caller.
+ *
+ * @param   baseaddr_p is the base address of the LENET instance to be worked on.
+ *
+ * @return
+ *
+ *    - XST_SUCCESS   if all self-test code passed
+ *    - XST_FAILURE   if any self-test code failed
+ *
+ * @note    Caching must be turned off for this function to work.
+ * @note    Self test may fail if data memory and device are not on the same bus.
+ *
+ */
+XStatus LENET_Reg_SelfTest(void * baseaddr_p);
+
+#endif // LENET_H

zhan6841_FPGA-Accelerator-for-AES-LeNet-VGG16/LeNet/LeNet_selftest.c

@@ -0,0 +1,60 @@
+
+/***************************** Include Files *******************************/
+#include "LeNet.h"
+#include "xparameters.h"
+#include "stdio.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions ***************************/
+#define READ_WRITE_MUL_FACTOR 0x10
+
+/************************** Function Definitions ***************************/
+/**
+ *
+ * Run a self-test on the driver/device. Note this may be a destructive test if
+ * resets of the device are performed.
+ *
+ * If the hardware system is not built correctly, this function may never
+ * return to the caller.
+ *
+ * @param   baseaddr_p is the base address of the LENETinstance to be worked on.
+ *
+ * @return
+ *
+ *    - XST_SUCCESS   if all self-test code passed
+ *    - XST_FAILURE   if any self-test code failed
+ *
+ * @note    Caching must be turned off for this function to work.
+ * @note    Self test may fail if data memory and device are not on the same bus.
+ *
+ */
+XStatus LENET_Reg_SelfTest(void * baseaddr_p)
+{
+	u32 baseaddr;
+	int write_loop_index;
+	int read_loop_index;
+	int Index;
+
+	baseaddr = (u32) baseaddr_p;
+
+	xil_printf("******************************\n\r");
+	xil_printf("* User Peripheral Self Test\n\r");
+	xil_printf("******************************\n\n\r");
+
+	/*
+	 * Write to user logic slave module register(s) and read back
+	 */
+	xil_printf("User logic slave module test...\n\r");
+
+	for (write_loop_index = 0 ; write_loop_index < 4; write_loop_index++)
+	  LENET_mWriteReg (baseaddr, write_loop_index*4, (write_loop_index+1)*READ_WRITE_MUL_FACTOR);
+	for (read_loop_index = 0 ; read_loop_index < 4; read_loop_index++)
+	  if ( LENET_mReadReg (baseaddr, read_loop_index*4) != (read_loop_index+1)*READ_WRITE_MUL_FACTOR){
+	    xil_printf ("Error reading register value at address %x\n", (int)baseaddr + read_loop_index*4);
+	    return XST_FAILURE;
+	  }
+
+	xil_printf("   - slave register write/read passed\n\n\r");
+
+	return XST_SUCCESS;
+}

zhan6841_FPGA-Accelerator-for-AES-LeNet-VGG16/LeNet/README.md

@@ -0,0 +1 @@
+

zhan6841_FPGA-Accelerator-for-AES-LeNet-VGG16/LeNet/complete.v

@@ -0,0 +1,116 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 01/02/2018 02:18:44 AM
+// Design Name: 
+// Module Name: complete
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+`define OUTPUT_NODE 10
+`define DATA_SIZE 8
+
+module complete(
+    clk, rst, complete_en, result_bram_douta,
+    result_bram_ena, result_bram_addra,
+    result,
+    complete_finish
+    );
+    input clk;
+    input rst;
+    input complete_en;
+    input [`DATA_SIZE-1:0] result_bram_douta;
+    output reg result_bram_ena;
+    output reg [14:0] result_bram_addra;
+    output reg [`DATA_SIZE*`OUTPUT_NODE-1:0] result;
+    output reg complete_finish;
+    
+    parameter fc2_result_base = 18900;
+    
+    integer count = 0,
+            circle = 0,
+            data_begin = 0;
+            
+    reg [2:0] state;
+    //reg [`DATA_SIZE*`OUTPUT_NODE-1:0] tempresult;
+    //assign result = tempresult;
+            
+    parameter S_IDLE  = 3'b100,
+              S_CHECK = 3'b010,
+              S_LOAD  = 3'b001;
+    
+    always@(posedge clk)
+    begin
+        if(rst == 1'b1)
+        begin
+            result_bram_ena <= 1'b0;
+            circle <= 0;
+            count <= 0;
+            state <= S_IDLE;
+        end
+        else
+        begin
+            if(complete_en == 1'b1)
+            begin
+                case(state)
+                    S_IDLE:
+                    begin
+                        circle <= 0;
+                        count <= 0;
+                        complete_finish <= 1'b0;
+                        state <= S_CHECK;
+                    end
+                    S_CHECK:
+                    begin
+                        if(count == `OUTPUT_NODE)
+                        begin
+                            count <= 0;
+                            circle <= 0;
+                            complete_finish <= 1'b1;
+                            state <= S_IDLE;
+                        end
+                        else
+                        begin
+                            circle <= 0;
+                            state <= S_LOAD;
+                        end
+                    end
+                    S_LOAD:
+                    begin
+                        if(circle == 0)
+                        begin
+                            result_bram_ena <= 1'b1;
+                            result_bram_addra <= fc2_result_base + count;
+                            circle <= circle + 1;
+                        end
+                        else if(circle == 3)
+                        begin
+                            data_begin = `DATA_SIZE * (`OUTPUT_NODE - count) - 1;
+                            result[data_begin-:8] <= result_bram_douta;
+                            count <= count + 1;
+                            circle <= 0;
+                            result_bram_ena <= 1'b0;
+                            state <= S_CHECK;
+                        end
+                        else
+                        begin
+                            circle <= circle + 1;
+                        end
+                    end
+                endcase
+            end
+        end
+    end
+endmodule

zhan6841_FPGA-Accelerator-for-AES-LeNet-VGG16/LeNet/conv_1.v

@@ -0,0 +1,278 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 12/30/2017 05:44:43 PM
+// Design Name: 
+// Module Name: conv_1
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+`define INPUT_NODE 784
+`define IMAGE_SIZE 28
+`define NUM_CHANNELS 1
+`define CONV1_DEEP 20
+`define CONV1_SIZE 5
+`define CONV1_OUTPUT 24
+`define DATA_SIZE 8
+
+module conv_1(
+    clk, rst, conv_1_en, bias_weights_bram_douta, input_bram_douta, graph,
+    bias_weights_bram_ena, bias_weights_bram_addra,
+    result_bram_ena, result_bram_wea, result_bram_addra, result_bram_dina,
+    input_bram_ena, input_bram_addra,
+    conv_1_finish
+    );
+    input clk;
+    input rst;
+    input conv_1_en;
+    input [`DATA_SIZE-1:0] bias_weights_bram_douta;
+    input [`DATA_SIZE-1:0] input_bram_douta;
+    input [4:0] graph;
+    output reg bias_weights_bram_ena;
+    output reg [18:0] bias_weights_bram_addra;
+    output reg result_bram_ena;
+    output reg result_bram_wea;
+    output reg [14:0] result_bram_addra;
+    output reg [`DATA_SIZE-1:0] result_bram_dina;
+    output reg input_bram_ena;
+    output reg [12:0] input_bram_addra;
+    output reg conv_1_finish;
+    
+    //reg [4:0] filter;
+    //reg [4:0] row;
+    //reg [4:0] column;
+    
+    integer filter = 0,
+            channel = 0,
+            row = 0,
+            column = 0,
+            count = 0;
+    
+    reg [`DATA_SIZE*`CONV1_SIZE*`CONV1_SIZE-1:0] matrix1;
+    reg [`DATA_SIZE*`CONV1_SIZE*`CONV1_SIZE-1:0] matrix2;
+    reg [`DATA_SIZE-1:0] bias;
+    reg relu_1_en;
+    wire [`DATA_SIZE-1:0] dout;
+    reg [`DATA_SIZE-1:0] result;
+    
+    multi_add conv_1_ma(
+        .matrix1(matrix1),
+        .matrix2(matrix2),
+        .bias(bias),
+        .relu_1_en(relu_1_en),
+        .dout(dout)
+    );
+    
+    reg [6:0] state;
+    
+    parameter S_IDLE          = 7'b1000000,
+              S_CHECK         = 7'b0100000,
+              S_LOAD_WEIGHTS  = 7'b0010000,
+              S_LOAD_BIAS     = 7'b0001000,
+              S_LOAD_DATA     = 7'b0000100,
+              S_CONVOLUTE     = 7'b0000010,
+              S_STORE_RESULT  = 7'b0000001;
+    
+    integer data_begin = 0;
+    integer circle = 0;
+    
+    parameter conv1_weights_base = 0,
+              conv1_bias_base = 430500,
+              conv1_result_base = 0;
+    
+    always@(posedge clk)
+    begin
+        if(rst == 1'b1)
+        begin
+            state <= S_IDLE;
+            bias_weights_bram_ena <= 1'b0;
+            result_bram_ena <= 1'b0;
+            result_bram_wea <= 1'b0;
+            input_bram_ena <= 1'b0;
+        end
+        else
+        begin
+            if(conv_1_en == 1'b1)
+            begin
+                case(state)
+                    S_IDLE:
+                    begin
+                        filter <= 0;
+                        channel <= 0;
+                        row <= 0;
+                        column <= 0;
+                        matrix1 <= 0;
+                        matrix2 <= 0;
+                        bias <= 0;
+                        relu_1_en <= 1'b0;
+                        result <= 0;
+                        conv_1_finish <= 1'b0;
+                        state <= S_CHECK;
+                    end
+                    S_CHECK:
+                    begin
+                        if(filter == `CONV1_DEEP)
+                        begin
+                            bias_weights_bram_ena <= 1'b0;
+                            result_bram_ena <= 1'b0;
+                            result_bram_wea <= 1'b0;
+                            input_bram_ena <= 1'b0;
+                            conv_1_finish <= 1'b1;
+                            state <= S_IDLE;
+                        end
+                        else
+                        begin
+                            circle <= 0;
+                            count <= 0;
+                            state <= S_LOAD_WEIGHTS;
+                        end
+                    end
+                    S_LOAD_WEIGHTS:
+                    begin
+                        if(count < `CONV1_SIZE*`CONV1_SIZE)
+                        begin
+                            if(circle == 0)
+                            begin
+                                bias_weights_bram_ena <= 1'b1;
+                                bias_weights_bram_addra <= conv1_weights_base + count;
+                                circle <= circle + 1;
+                            end
+                            else if(circle == 3)
+                            begin
+                                data_begin = `DATA_SIZE * (`CONV1_SIZE * `CONV1_SIZE - count) - 1;
+                                matrix2[data_begin-:8] <= bias_weights_bram_douta;
+                                count <= count + 1;
+                                circle <= 0;
+                            end
+                            else
+                            begin
+                                circle <= circle + 1;
+                            end
+                        end
+                        else
+                        begin
+                            circle <= 0;
+                            count <= 0;
+                            bias_weights_bram_ena <= 1'b0;
+                            state <= S_LOAD_BIAS;
+                        end
+                    end
+                    S_LOAD_BIAS:
+                    begin
+                        if(circle == 0)
+                        begin
+                            bias_weights_bram_ena <= 1'b1;
+                            bias_weights_bram_addra <= conv1_bias_base + filter;
+                            circle <= circle + 1;
+                        end
+                        else if(circle == 3)
+                        begin
+                            bias <= bias_weights_bram_douta;
+                            circle <= 0;
+                            count <= 0;
+                            bias_weights_bram_ena <= 1'b0;
+                            state <= S_LOAD_DATA;
+                        end
+                        else
+                        begin
+                            circle <= circle + 1;
+                        end
+                    end
+                    S_LOAD_DATA:
+                    begin
+                        if(count < `CONV1_SIZE * `CONV1_SIZE)
+                        begin
+                            if(circle == 0)
+                            begin
+                                input_bram_ena <= 1'b1;
+                                input_bram_addra <= graph * `INPUT_NODE + (row + count / `CONV1_SIZE) * `IMAGE_SIZE + column + count % `CONV1_SIZE;
+                                circle <= circle + 1;
+                            end
+                            else if(circle == 3)
+                            begin
+                                data_begin = `DATA_SIZE * (`CONV1_SIZE * `CONV1_SIZE - count) - 1;
+                                matrix1[data_begin-:8] <= input_bram_douta;
+                                count <= count + 1;
+                                circle <= 0;
+                            end
+                            else
+                            begin
+                                circle <= circle + 1;
+                            end
+                        end
+                        else
+                        begin
+                            circle <= 0;
+                            count <= 0;
+                            input_bram_ena <= 1'b0;
+                            relu_1_en <= 1'b0;
+                            state <= S_CONVOLUTE;
+                        end
+                    end
+                    S_CONVOLUTE:
+                    begin
+                        result <= dout;
+                        circle <= 0;
+                        state <= S_STORE_RESULT;
+                    end
+                    S_STORE_RESULT:
+                    begin
+                        if(circle == 0)
+                        begin
+                            result_bram_ena <= 1'b1;
+                            result_bram_wea <= 1'b1;
+                            result_bram_addra <= conv1_result_base + filter * `CONV1_OUTPUT * `CONV1_OUTPUT + row * `CONV1_OUTPUT + column;
+                            result_bram_dina <= result;
+                            circle <= circle + 1;
+                        end
+                        else if(circle == 3)
+                        begin
+                            result_bram_ena <= 1'b0;
+                            result_bram_wea <= 1'b0;
+                            circle <= 0;
+                            if(column == `CONV1_OUTPUT - 1)
+                            begin
+                                if(row == `CONV1_OUTPUT - 1)
+                                begin
+                                    if(channel == `NUM_CHANNELS - 1)
+                                    begin
+                                        filter <= filter + 1;
+                                    end
+                                    channel <= (channel + 1) % `NUM_CHANNELS;
+                                end
+                                row <= (row + 1) % `CONV1_OUTPUT;
+                            end
+                            column <= (column + 1) % `CONV1_OUTPUT;
+                            state <= S_CHECK;
+                        end
+                        else
+                        begin
+                            circle <= circle + 1;
+                        end
+                    end
+                    default:
+                    begin
+                        state <= S_IDLE;
+                        bias_weights_bram_ena <= 1'b0;
+                        result_bram_ena <= 1'b0;
+                        result_bram_wea <= 1'b0;
+                        input_bram_ena <= 1'b0;
+                    end
+                endcase
+            end
+        end
+    end
+    
+endmodule

zhan6841_FPGA-Accelerator-for-AES-LeNet-VGG16/LeNet/conv_2.v

@@ -0,0 +1,275 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 01/01/2018 08:32:31 PM
+// Design Name: 
+// Module Name: conv_2
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+`define CONV1_DEEP 20
+`define CONV2_DEEP 50
+`define CONV2_SIZE 5
+`define CONV2_INPUT 12
+`define CONV2_OUTPUT 8
+`define DATA_SIZE 8
+
+module conv_2(
+    clk, rst, conv_2_en, bias_weights_bram_douta, result_bram_douta,
+    bias_weights_bram_ena, bias_weights_bram_addra,
+    result_bram_ena, result_bram_wea, result_bram_addra, result_bram_dina,
+    conv_2_finish
+    );
+    input clk;
+    input rst;
+    input conv_2_en;
+    input [`DATA_SIZE-1:0] bias_weights_bram_douta;
+    input [`DATA_SIZE-1:0] result_bram_douta;
+    output reg bias_weights_bram_ena;
+    output reg [18:0] bias_weights_bram_addra;
+    output reg result_bram_ena;
+    output reg result_bram_wea;
+    output reg [14:0] result_bram_addra;
+    output reg [`DATA_SIZE-1:0] result_bram_dina;
+    output reg conv_2_finish;
+    
+    integer filter = 0,
+            channel = 0,
+            row = 0,
+            column = 0,
+            count = 0;
+    
+    reg [`DATA_SIZE*`CONV2_SIZE*`CONV2_SIZE-1:0] matrix1;
+    reg [`DATA_SIZE*`CONV2_SIZE*`CONV2_SIZE-1:0] matrix2;
+    reg [`DATA_SIZE-1:0] bias;
+    reg relu_1_en;
+    wire [`DATA_SIZE-1:0] dout;
+    reg [`DATA_SIZE-1:0] result;
+    
+    multi_add conv_2_ma(
+        .matrix1(matrix1),
+        .matrix2(matrix2),
+        .bias(bias),
+        .relu_1_en(relu_1_en),
+        .dout(dout)
+    );
+    
+    reg [6:0] state;
+    
+    parameter S_IDLE          = 7'b1000000,
+              S_CHECK         = 7'b0100000,
+              S_LOAD_WEIGHTS  = 7'b0010000,
+              S_LOAD_BIAS     = 7'b0001000,
+              S_LOAD_DATA     = 7'b0000100,
+              S_CONVOLUTE     = 7'b0000010,
+              S_STORE_RESULT  = 7'b0000001;
+    
+    integer data_begin = 0;
+    integer circle = 0;
+    
+    parameter pool1_result_base = 11520,
+              conv2_weights_base = 500,
+              conv2_bias_base = 430520,
+              conv2_result_base = 14400;
+              
+    always@(posedge clk)
+    begin
+        if(rst == 1'b1)
+        begin
+            state <= S_IDLE;
+            bias_weights_bram_ena <= 1'b0;
+            result_bram_ena <= 1'b0;
+            result_bram_wea <= 1'b0;
+        end
+        else
+        begin
+            if(conv_2_en == 1'b1)
+            begin
+                case(state)
+                    S_IDLE:
+                    begin
+                        filter <= 0;
+                        channel <= 0;
+                        row <= 0;
+                        column <= 0;
+                        matrix1 <= 0;
+                        matrix2 <= 0;
+                        bias <= 0;
+                        relu_1_en <= 1'b0;
+                        result <= 0;
+                        conv_2_finish <= 1'b0;
+                        state <= S_CHECK;
+                    end
+                    S_CHECK:
+                    begin
+                        if(filter == `CONV2_DEEP)
+                        begin
+                            bias_weights_bram_ena <= 1'b0;
+                            result_bram_ena <= 1'b0;
+                            result_bram_wea <= 1'b0;
+                            conv_2_finish <= 1'b1;
+                            state <= S_IDLE;
+                        end
+                        else
+                        begin
+                            circle <= 0;
+                            count <= 0;
+                            state <= S_LOAD_WEIGHTS;
+                        end
+                    end
+                    S_LOAD_WEIGHTS:
+                    begin
+                        if(count < `CONV2_SIZE*`CONV2_SIZE)
+                        begin
+                            if(circle == 0)
+                            begin
+                                bias_weights_bram_ena <= 1'b1;
+                                bias_weights_bram_addra <= conv2_weights_base + count;
+                                circle <= circle + 1;
+                            end
+                            else if(circle == 3)
+                            begin
+                                data_begin = `DATA_SIZE * (`CONV2_SIZE * `CONV2_SIZE - count) - 1;
+                                matrix2[data_begin-:8] <= bias_weights_bram_douta;
+                                count <= count + 1;
+                                circle <= 0;
+                            end
+                            else
+                            begin
+                                circle <= circle + 1;
+                            end
+                        end
+                        else
+                        begin
+                            circle <= 0;
+                            count <= 0;
+                            bias_weights_bram_ena <= 1'b0;
+                            state <= S_LOAD_BIAS;
+                        end
+                    end
+                    S_LOAD_BIAS:
+                    begin
+                        if(channel == 0)
+                        begin
+                            if(circle == 0)
+                            begin
+                                bias_weights_bram_ena <= 1'b1;
+                                bias_weights_bram_addra <= conv2_bias_base + filter;
+                                circle <= circle + 1;
+                            end
+                            else if(circle == 3)
+                            begin
+                                bias <= bias_weights_bram_douta;
+                                circle <= 0;
+                                count <= 0;
+                                bias_weights_bram_ena <= 1'b0;
+                                state <= S_LOAD_DATA;
+                            end
+                            else
+                            begin
+                                circle <= circle + 1;
+                            end
+                        end
+                        else
+                        begin
+                            bias <= result;
+                            state <= S_LOAD_DATA;
+                        end
+                    end
+                    S_LOAD_DATA:
+                    begin
+                        if(count < `CONV2_SIZE * `CONV2_SIZE)
+                        begin
+                            if(circle == 0)
+                            begin
+                                result_bram_ena <= 1'b1;
+                                result_bram_addra <= pool1_result_base + channel * `CONV2_INPUT * `CONV2_INPUT + (row + count / `CONV2_SIZE) * `CONV2_INPUT + column + count % `CONV2_SIZE;
+                                circle <= circle + 1;
+                            end
+                            else if(circle == 3)
+                            begin
+                                data_begin = `DATA_SIZE * (`CONV2_SIZE * `CONV2_SIZE - count) - 1;
+                                matrix1[data_begin-:8] <= result_bram_douta;
+                                count <= count + 1;
+                                circle <= 0;
+                            end
+                            else
+                            begin
+                                circle <= circle + 1;
+                            end
+                        end
+                        else
+                        begin
+                            circle <= 0;
+                            count <= 0;
+                            result_bram_ena <= 1'b0;
+                            relu_1_en <= 1'b0;
+                            state <= S_CONVOLUTE;
+                        end
+                    end
+                    S_CONVOLUTE:
+                    begin
+                        result <= dout;
+                        circle <= 0;
+                        state <= S_STORE_RESULT;
+                    end
+                    S_STORE_RESULT:
+                    begin
+                        if(circle == 0)
+                        begin
+                            result_bram_ena <= 1'b1;
+                            result_bram_wea <= 1'b1;
+                            result_bram_addra <= conv2_result_base + filter * `CONV2_OUTPUT * `CONV2_OUTPUT + row * `CONV2_OUTPUT + column;
+                            result_bram_dina <= result;
+                            circle <= circle + 1;
+                        end
+                        else if(circle == 3)
+                        begin
+                            result_bram_ena <= 1'b0;
+                            result_bram_wea <= 1'b0;
+                            circle <= 0;
+                            if(column == `CONV2_OUTPUT - 1)
+                            begin
+                                if(row == `CONV2_OUTPUT - 1)
+                                begin
+                                    if(channel == `CONV1_DEEP - 1)
+                                    begin
+                                        filter <= filter + 1;
+                                    end
+                                    channel <= (channel + 1) % `CONV1_DEEP;
+                                end
+                                row <= (row + 1) % `CONV2_OUTPUT;
+                            end
+                            column <= (column + 1) % `CONV2_OUTPUT;
+                            state <= S_CHECK;
+                        end
+                        else
+                        begin
+                            circle <= circle + 1;
+                        end
+                    end
+                    default:
+                    begin
+                        state <= S_IDLE;
+                        bias_weights_bram_ena <= 1'b0;
+                        result_bram_ena <= 1'b0;
+                        result_bram_wea <= 1'b0;
+                    end
+                endcase
+            end
+        end
+    end
+
+endmodule

zhan6841_FPGA-Accelerator-for-AES-LeNet-VGG16/LeNet/fc_1.v

@@ -0,0 +1,272 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 12/31/2017 08:00:24 AM
+// Design Name: 
+// Module Name: fc_1
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+`define FC1_SIZE 500
+`define CONV2_DEEP 50
+`define POOL2_OUTPUT 4
+`define DATA_SIZE 8
+
+module fc_1(
+    clk, rst, fc_1_en, bias_weights_bram_douta, result_bram_douta,
+    bias_weights_bram_ena, bias_weights_bram_addra,
+    result_bram_ena, result_bram_wea, result_bram_addra, result_bram_dina,
+    fc_1_finish
+    );
+    input clk;
+    input rst;
+    input fc_1_en;
+    input [`DATA_SIZE-1:0] bias_weights_bram_douta;
+    input [`DATA_SIZE-1:0] result_bram_douta;
+    output reg bias_weights_bram_ena;
+    output reg [18:0] bias_weights_bram_addra;
+    output reg result_bram_ena;
+    output reg result_bram_wea;
+    output reg [14:0] result_bram_addra;
+    output reg [`DATA_SIZE-1:0] result_bram_dina;
+    output reg fc_1_finish;
+    
+    reg [`DATA_SIZE*25-1:0] matrix1;
+    reg [`DATA_SIZE*25-1:0] matrix2;
+    reg [`DATA_SIZE-1:0] bias;
+    reg relu_1_en;
+    wire [`DATA_SIZE-1:0] dout;
+    reg [`DATA_SIZE-1:0] result;
+    
+    multi_add fc_1_ma(
+        .matrix1(matrix1),
+        .matrix2(matrix2),
+        .bias(bias),
+        .relu_1_en(relu_1_en),
+        .dout(dout)
+    );
+    
+    reg [6:0] state;
+    
+    parameter S_IDLE         = 7'b1000000,
+              S_CHECK        = 7'b0100000,
+              S_LOAD_WEIGHTS = 7'b0010000,
+              S_LOAD_BIAS    = 7'b0001000,
+              S_LOAD_DATA    = 7'b0000100,
+              S_MULTI_ADD    = 7'b0000010,
+              S_STORE_RESULT = 7'b0000001;
+              
+    integer count = 0,
+            row = 0,
+            column = 0,
+            circle = 0,
+            data_begin = 0;
+            
+    parameter pool2_result_base = 17600,
+              fc1_weights_base = 25500,
+              fc1_bias_base = 430570,
+              fc1_result_base = 18400;
+              
+    always@(posedge clk)
+    begin
+        if(rst == 1'b1)
+        begin
+            state <= S_IDLE;
+            bias_weights_bram_ena <= 1'b0;
+            result_bram_ena <= 1'b0;
+            result_bram_wea <= 1'b0;
+        end
+        else
+        begin
+            if(fc_1_en == 1'b1)
+            begin
+                case(state)
+                    S_IDLE:
+                    begin
+                        row <= 0;
+                        column <= 0;
+                        matrix1 <= 0;
+                        matrix2 <= 0;
+                        bias <= 0;
+                        relu_1_en <= 1'b1;
+                        result <= 0;
+                        fc_1_finish <= 1'b0;
+                        state <= S_CHECK;
+                    end
+                    S_CHECK:
+                    begin
+                        if(row == `FC1_SIZE)
+                        begin
+                            bias_weights_bram_ena <= 1'b0;
+                            result_bram_ena <= 1'b0;
+                            result_bram_wea <= 1'b0;
+                            relu_1_en <= 1'b0;
+                            fc_1_finish <= 1'b1;
+                            state <= S_IDLE;
+                        end
+                        else
+                        begin
+                            circle <= 0;
+                            count <= 0;
+                            result <= 0;
+                            state <= S_LOAD_WEIGHTS;
+                        end
+                    end
+                    S_LOAD_WEIGHTS:
+                    begin
+                        if(count < 25)
+                        begin
+                            if(circle == 0)
+                            begin
+                                bias_weights_bram_ena <= 1'b1;
+                                bias_weights_bram_addra <= fc1_weights_base + row * `CONV2_DEEP * `POOL2_OUTPUT * `POOL2_OUTPUT + column;
+                                circle <= circle + 1;
+                            end
+                            else if(circle == 3)
+                            begin
+                                data_begin = `DATA_SIZE * (25 - count) - 1;
+                                matrix2[data_begin-:8] <= bias_weights_bram_douta;
+                                count <= count + 1;
+                                column <= column + 1;
+                                circle <= 0;
+                            end
+                            else
+                            begin
+                                circle <= circle + 1;
+                            end
+                        end
+                        else
+                        begin
+                            circle <= 0;
+                            count <= 0;
+                            column <= column - 25;
+                            bias_weights_bram_ena <= 1'b0;
+                            state <= S_LOAD_BIAS;
+                        end
+                    end
+                    S_LOAD_BIAS:
+                    begin
+                        if(column < 25)
+                            begin
+                            if(circle == 0)
+                            begin
+                                bias_weights_bram_ena <= 1'b1;
+                                bias_weights_bram_addra <= fc1_bias_base + row;
+                                circle <= circle + 1;
+                            end
+                            else if(circle == 3)
+                            begin
+                                bias <= bias_weights_bram_douta;
+                                circle <= 0;
+                                count <= 0;
+                                bias_weights_bram_ena <= 1'b0;
+                                state <= S_LOAD_DATA;
+                            end
+                            else
+                            begin
+                                circle <= circle + 1;
+                            end
+                        end
+                        else
+                        begin
+                            bias <= result;
+                            state <= S_LOAD_DATA;
+                        end
+                    end
+                    S_LOAD_DATA:
+                    begin
+                        if(count < 25)
+                        begin
+                            if(circle == 0)
+                            begin
+                                result_bram_ena <= 1'b1;
+                                result_bram_addra <= pool2_result_base + column;
+                                circle <= circle + 1;
+                            end
+                            else if(circle == 3)
+                            begin
+                                data_begin = `DATA_SIZE * (25 - count) - 1;
+                                matrix1[data_begin-:8] <= result_bram_douta;
+                                count <= count + 1;
+                                column <= column + 1;
+                                circle <= 0;
+                            end
+                            else
+                            begin
+                                circle <= circle + 1;
+                            end
+                        end
+                        else
+                        begin
+                            circle <= 0;
+                            count <= 0;
+                            result_bram_ena <= 1'b0;
+                            relu_1_en <= 1'b1;
+                            state <= S_MULTI_ADD;
+                        end
+                    end
+                    S_MULTI_ADD:
+                    begin
+                        result <= result + dout;
+                        if(column == `CONV2_DEEP * `POOL2_OUTPUT * `POOL2_OUTPUT)
+                        begin
+                            circle <= 0;
+                            state <= S_STORE_RESULT;
+                        end
+                        else
+                        begin
+                            circle <= 0;
+                            count <= 0;
+                            state <= S_LOAD_WEIGHTS;
+                        end
+                    end
+                    S_STORE_RESULT:
+                    begin
+                        if(circle == 0)
+                        begin
+                            result_bram_ena <= 1'b1;
+                            result_bram_wea <= 1'b1;
+                            result_bram_addra <= fc1_result_base + row;
+                            result_bram_dina <= result;
+                            circle <= circle + 1;
+                        end
+                        else if(circle == 3)
+                        begin
+                            result_bram_ena <= 1'b0;
+                            result_bram_wea <= 1'b0;
+                            circle <= 0;
+                            column <= 0;
+                            count <= 0;
+                            row <= row + 1;
+                            state <= S_CHECK;
+                        end
+                        else
+                        begin
+                            circle <= circle + 1;
+                        end
+                    end
+                    default:
+                    begin
+                        state <= S_IDLE;
+                        bias_weights_bram_ena <= 1'b0;
+                        result_bram_ena <= 1'b0;
+                        result_bram_wea <= 1'b0;
+                    end
+                endcase
+            end
+        end
+    end
+    
+endmodule

zhan6841_FPGA-Accelerator-for-AES-LeNet-VGG16/LeNet/fc_2.v

@@ -0,0 +1,276 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 01/02/2018 12:22:35 AM
+// Design Name: 
+// Module Name: fc_2
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+`define FC1_SIZE 500
+`define FC2_SIZE 10
+`define DATA_SIZE 8
+
+module fc_2(
+    clk, rst, fc_2_en, bias_weights_bram_douta, result_bram_douta,
+    bias_weights_bram_ena, bias_weights_bram_addra,
+    result_bram_ena, result_bram_wea, result_bram_addra, result_bram_dina,
+    fc_2_finish,
+    out_result
+    );
+    input clk;
+    input rst;
+    input fc_2_en;
+    input [`DATA_SIZE-1:0] bias_weights_bram_douta;
+    input [`DATA_SIZE-1:0] result_bram_douta;
+    output reg bias_weights_bram_ena;
+    output reg [18:0] bias_weights_bram_addra;
+    output reg result_bram_ena;
+    output reg result_bram_wea;
+    output reg [14:0] result_bram_addra;
+    output reg [`DATA_SIZE-1:0] result_bram_dina;
+    output reg fc_2_finish;
+    output reg [79:0] out_result;
+    
+    reg [`DATA_SIZE*25-1:0] matrix1;
+    reg [`DATA_SIZE*25-1:0] matrix2;
+    reg [`DATA_SIZE-1:0] bias;
+    reg relu_1_en;
+    wire [`DATA_SIZE-1:0] dout;
+    reg [`DATA_SIZE-1:0] result;
+    
+    multi_add fc_1_ma(
+        .matrix1(matrix1),
+        .matrix2(matrix2),
+        .bias(bias),
+        .relu_1_en(relu_1_en),
+        .dout(dout)
+    );
+
+    reg [6:0] state;
+    
+    parameter S_IDLE         = 7'b1000000,
+              S_CHECK        = 7'b0100000,
+              S_LOAD_WEIGHTS = 7'b0010000,
+              S_LOAD_BIAS    = 7'b0001000,
+              S_LOAD_DATA    = 7'b0000100,
+              S_MULTI_ADD    = 7'b0000010,
+              S_STORE_RESULT = 7'b0000001;
+              
+    integer count = 0,
+            row = 0,
+            column = 0,
+            circle = 0,
+            data_begin = 0;
+            
+    parameter fc1_result_base = 18400,
+              fc2_weights_base = 425500,
+              fc2_bias_base = 431070,
+              fc2_result_base = 18900;
+              
+    always@(posedge clk)
+    begin
+        if(rst == 1'b1)
+        begin
+            state <= S_IDLE;
+            bias_weights_bram_ena <= 1'b0;
+            result_bram_ena <= 1'b0;
+            result_bram_wea <= 1'b0;
+        end
+        else
+        begin
+            if(fc_2_en == 1'b1)
+            begin
+                case(state)
+                    S_IDLE:
+                    begin
+                        row <= 0;
+                        column <= 0;
+                        matrix1 <= 0;
+                        matrix2 <= 0;
+                        bias <= 0;
+                        relu_1_en <= 1'b0;
+                        result <= 0;
+                        fc_2_finish <= 1'b0;
+                        state <= S_CHECK;
+                    end
+                    S_CHECK:
+                    begin
+                        if(row == `FC2_SIZE)
+                        begin
+                            bias_weights_bram_ena <= 1'b0;
+                            result_bram_ena <= 1'b0;
+                            result_bram_wea <= 1'b0;
+                            relu_1_en <= 1'b0;
+                            fc_2_finish <= 1'b1;
+                            state <= S_IDLE;
+                        end
+                        else
+                        begin
+                            circle <= 0;
+                            count <= 0;
+                            result <= 0;
+                            state <= S_LOAD_WEIGHTS;
+                        end
+                    end
+                    S_LOAD_WEIGHTS:
+                    begin
+                        if(count < 25)
+                        begin
+                            if(circle == 0)
+                            begin
+                                bias_weights_bram_ena <= 1'b1;
+                                bias_weights_bram_addra <= fc2_weights_base + row * `FC1_SIZE + column;
+                                circle <= circle + 1;
+                            end
+                            else if(circle == 3)
+                            begin
+                                data_begin = `DATA_SIZE * (25 - count) - 1;
+                                matrix2[data_begin-:8] <= bias_weights_bram_douta;
+                                count <= count + 1;
+                                column <= column + 1;
+                                circle <= 0;
+                            end
+                            else
+                            begin
+                                circle <= circle + 1;
+                            end
+                        end
+                        else
+                        begin
+                            circle <= 0;
+                            count <= 0;
+                            column <= column - 25;
+                            bias_weights_bram_ena <= 1'b0;
+                            state <= S_LOAD_BIAS;
+                        end
+                    end
+                    S_LOAD_BIAS:
+                    begin
+                        if(column < 25)
+                            begin
+                            if(circle == 0)
+                            begin
+                                bias_weights_bram_ena <= 1'b1;
+                                bias_weights_bram_addra <= fc2_bias_base + row;
+                                circle <= circle + 1;
+                            end
+                            else if(circle == 3)
+                            begin
+                                bias <= bias_weights_bram_douta;
+                                circle <= 0;
+                                count <= 0;
+                                bias_weights_bram_ena <= 1'b0;
+                                state <= S_LOAD_DATA;
+                            end
+                            else
+                            begin
+                                circle <= circle + 1;
+                            end
+                        end
+                        else
+                        begin
+                            bias <= result;
+                            state <= S_LOAD_DATA;
+                        end
+                    end
+                    S_LOAD_DATA:
+                    begin
+                        if(count < 25)
+                        begin
+                            if(circle == 0)
+                            begin
+                                result_bram_ena <= 1'b1;
+                                result_bram_addra <= fc1_result_base + column;
+                                circle <= circle + 1;
+                            end
+                            else if(circle == 3)
+                            begin
+                                data_begin = `DATA_SIZE * (25 - count) - 1;
+                                matrix1[data_begin-:8] <= result_bram_douta;
+                                count <= count + 1;
+                                column <= column + 1;
+                                circle <= 0;
+                            end
+                            else
+                            begin
+                                circle <= circle + 1;
+                            end
+                        end
+                        else
+                        begin
+                            circle <= 0;
+                            count <= 0;
+                            result_bram_ena <= 1'b0;
+                            relu_1_en <= 1'b0;
+                            state <= S_MULTI_ADD;
+                        end
+                    end
+                    S_MULTI_ADD:
+                    begin
+                        result <= result + dout;
+                        if(column == `FC1_SIZE)
+                        begin
+                            circle <= 0;
+                            state <= S_STORE_RESULT;
+                        end
+                        else
+                        begin
+                            circle <= 0;
+                            count <= 0;
+                            state <= S_LOAD_WEIGHTS;
+                        end
+                    end
+                    S_STORE_RESULT:
+                    begin
+                        if(circle == 0)
+                        begin
+                            result_bram_ena <= 1'b1;
+                            result_bram_wea <= 1'b1;
+                            result_bram_addra <= fc1_result_base + row;
+                            result_bram_dina <= result;
+                            circle <= circle + 1;
+                        end
+                        else if(circle == 3)
+                        begin
+                            $display("%b", result);
+                            data_begin = 8 * (10 - row) - 1;
+                            out_result[data_begin-:8] <= result;
+                            result_bram_ena <= 1'b0;
+                            result_bram_wea <= 1'b0;
+                            circle <= 0;
+                            column <= 0;
+                            count <= 0;
+                            row <= row + 1;
+                            state <= S_CHECK;
+                        end
+                        else
+                        begin
+                            circle <= circle + 1;
+                        end
+                    end
+                    default:
+                    begin
+                        state <= S_IDLE;
+                        bias_weights_bram_ena <= 1'b0;
+                        result_bram_ena <= 1'b0;
+                        result_bram_wea <= 1'b0;
+                    end
+                endcase
+            end
+        end
+    end
+       
+endmodule

zhan6841_FPGA-Accelerator-for-AES-LeNet-VGG16/LeNet/lenet_top.v

@@ -0,0 +1,583 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 12/30/2017 01:39:54 AM
+// Design Name: 
+// Module Name: lenet_top
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+// LeNet parameters
+`define INPUT_NODE 784
+`define OUTPUT_NODE 10
+`define LAYER1_NODE 500
+`define LAYER2_NODE 500
+`define IMAGE_SIZE 28
+`define NUM_CHANNELS 1
+`define NUM_LABELS 10
+
+// Conv1
+`define CONV1_DEEP 20
+`define CONV1_SIZE 5
+`define CONV1_OUTPUT 24
+
+// Conv2
+`define CONV2_DEEP 50
+`define CONV2_SIZE 5
+`define CONV2_OUTPUT 8
+
+// Fc
+`define FC1_SIZE 500
+
+// fixed point
+`define DATA_SIZE 8
+
+module lenet_top(
+    clk, rst, start, graph, result, lenet_finish
+    );
+    input clk;
+    input rst;
+    input start;
+    input [4:0] graph;
+    output [`DATA_SIZE*`OUTPUT_NODE-1:0] result;
+    output lenet_finish;
+    
+    reg finish;
+    assign lenet_finish = finish;
+    
+    reg bias_weights_bram_ena;
+    reg [0:0] bias_weights_bram_wea;
+    reg [18:0] bias_weights_bram_addra;
+    reg [7:0] bias_weights_bram_dina = 8'b0;
+    wire [7:0] bias_weights_bram_douta;
+    
+    reg result_bram_ena;
+    reg [0:0] result_bram_wea;
+    reg [14:0] result_bram_addra;
+    reg [7:0] result_bram_dina;
+    wire [7:0] result_bram_douta;
+    
+    reg input_bram_ena;
+    reg [0:0] input_bram_wea;
+    reg [12:0] input_bram_addra;
+    reg [7:0] input_bram_dina = 8'b0;
+    wire [7:0] input_bram_douta;
+    
+    blk_mem_gen_0 bias_weights_bram (
+      .clka(clk),    // input wire clka
+      .ena(bias_weights_bram_ena),      // input wire ena
+      .wea(bias_weights_bram_wea),      // input wire [0 : 0] wea
+      .addra(bias_weights_bram_addra),  // input wire [18 : 0] addra
+      .dina(bias_weights_bram_dina),    // input wire [7 : 0] dina
+      .douta(bias_weights_bram_douta)  // output wire [7 : 0] douta
+    );
+    
+    blk_mem_gen_1 result_bram (
+      .clka(clk),    // input wire clka
+      .ena(result_bram_ena),      // input wire ena
+      .wea(result_bram_wea),      // input wire [0 : 0] wea
+      .addra(result_bram_addra),  // input wire [14 : 0] addra
+      .dina(result_bram_dina),    // input wire [7 : 0] dina
+      .douta(result_bram_douta)  // output wire [7 : 0] douta
+    );
+    
+    blk_mem_gen_2 input_bram (
+      .clka(clk),    // input wire clka
+      .ena(input_bram_ena),      // input wire ena
+      .wea(input_bram_wea),      // input wire [0 : 0] wea
+      .addra(input_bram_addra),  // input wire [12 : 0] addra
+      .dina(input_bram_dina),    // input wire [7 : 0] dina
+      .douta(input_bram_douta)  // output wire [7 : 0] douta
+    );
+    
+    reg conv_1_en;
+    wire conv_1_finish;
+    reg pool_1_en;
+    wire pool_1_finish;
+    reg conv_2_en;
+    wire conv_2_finish;
+    reg pool_2_en;
+    wire pool_2_finish;
+    reg fc_1_en;
+    wire fc_1_finish;
+    reg relu_1_en;
+    reg fc_2_en;
+    wire fc_2_finish;
+    reg complete_en;
+    wire complete_finish;
+    
+    // conv1
+    wire conv_1_bias_weights_bram_ena;
+    //wire [0:0] conv_1_bias_weights_bram_wea;
+    wire [18:0] conv_1_bias_weights_bram_addra;
+    //wire [7:0] conv_1_bias_weights_bram_dina;
+    reg [7:0] conv_1_bias_weights_bram_douta;
+    wire conv_1_result_bram_ena;
+    wire [0:0] conv_1_result_bram_wea; 
+    wire [14:0] conv_1_result_bram_addra;
+    wire [7:0] conv_1_result_bram_dina;
+    //reg [7:0] conv_1_result_bram_douta;
+    wire conv_1_input_bram_ena;
+    //wire [0:0] conv_1_input_bram_wea; 
+    wire [12:0] conv_1_input_bram_addra;
+    //wire [7:0] conv_1_input_bram_dina;
+    reg [7:0] conv_1_input_bram_douta;
+    
+    conv_1 u_conv_1(
+        .clk(clk),
+        .rst(rst),
+        .conv_1_en(conv_1_en),
+        .bias_weights_bram_douta(conv_1_bias_weights_bram_douta),
+        .input_bram_douta(conv_1_input_bram_douta),
+        .graph(graph),
+        .bias_weights_bram_ena(conv_1_bias_weights_bram_ena),
+        .bias_weights_bram_addra(conv_1_bias_weights_bram_addra),
+        .result_bram_ena(conv_1_result_bram_ena),
+        .result_bram_wea(conv_1_result_bram_wea),
+        .result_bram_addra(conv_1_result_bram_addra),
+        .result_bram_dina(conv_1_result_bram_dina),
+        .input_bram_ena(conv_1_input_bram_ena),
+        .input_bram_addra(conv_1_input_bram_addra),
+        .conv_1_finish(conv_1_finish)
+    );
+    
+    // pool1
+    //wire pool_1_bias_weights_bram_ena;
+    //wire [0:0] pool_1_bias_weights_bram_wea;
+    //wire [18:0] pool_1_bias_weights_bram_addra;
+    //wire [7:0] pool_1_bias_weights_bram_dina;
+    //wire [7:0] pool_1_bias_weights_bram_douta;
+    wire pool_1_result_bram_ena;
+    wire [0:0] pool_1_result_bram_wea; 
+    wire [14:0] pool_1_result_bram_addra;
+    wire [7:0] pool_1_result_bram_dina;
+    reg [7:0] pool_1_result_bram_douta;
+    
+    pool_1 u_pool_1(
+        .clk(clk),
+        .rst(rst),
+        .pool_1_en(pool_1_en),
+        .result_bram_douta(pool_1_result_bram_douta),
+        .result_bram_ena(pool_1_result_bram_ena),
+        .result_bram_wea(pool_1_result_bram_wea),
+        .result_bram_addra(pool_1_result_bram_addra),
+        .result_bram_dina(pool_1_result_bram_dina),
+        .pool_1_finish(pool_1_finish)
+    );
+    
+    // conv2
+    wire conv_2_bias_weights_bram_ena;
+    //wire [0:0] conv_2_bias_weights_bram_wea;
+    wire [18:0] conv_2_bias_weights_bram_addra;
+    //wire [7:0] conv_2_bias_weights_bram_dina;
+    reg [7:0] conv_2_bias_weights_bram_douta;
+    wire conv_2_result_bram_ena;
+    wire [0:0] conv_2_result_bram_wea; 
+    wire [14:0] conv_2_result_bram_addra;
+    wire [7:0] conv_2_result_bram_dina;
+    reg [7:0] conv_2_result_bram_douta;
+    
+    conv_2 u_conv_2(
+        .clk(clk),
+        .rst(rst),
+        .conv_2_en(conv_2_en),
+        .bias_weights_bram_douta(conv_2_bias_weights_bram_douta),
+        .result_bram_douta(conv_2_result_bram_douta),
+        .bias_weights_bram_ena(conv_2_bias_weights_bram_ena),
+        .bias_weights_bram_addra(conv_2_bias_weights_bram_addra),
+        .result_bram_ena(conv_2_result_bram_ena),
+        .result_bram_wea(conv_2_result_bram_wea),
+        .result_bram_addra(conv_2_result_bram_addra),
+        .result_bram_dina(conv_2_result_bram_dina),
+        .conv_2_finish(conv_2_finish)
+    );
+    
+    // pool2
+    //wire pool_2_bias_weights_bram_ena;
+    //wire [0:0] pool_2_bias_weights_bram_wea;
+    //wire [18:0] pool_2_bias_weights_bram_addra;
+    //wire [7:0] pool_2_bias_weights_bram_dina;
+    //wire [7:0] pool_2_bias_weights_bram_douta;
+    wire pool_2_result_bram_ena;
+    wire [0:0] pool_2_result_bram_wea; 
+    wire [14:0] pool_2_result_bram_addra;
+    wire [7:0] pool_2_result_bram_dina;
+    reg [7:0] pool_2_result_bram_douta;
+    
+    pool_2 u_pool_2(
+        .clk(clk),
+        .rst(rst),
+        .pool_2_en(pool_2_en),
+        .result_bram_douta(pool_2_result_bram_douta),
+        .result_bram_ena(pool_2_result_bram_ena),
+        .result_bram_wea(pool_2_result_bram_wea),
+        .result_bram_addra(pool_2_result_bram_addra),
+        .result_bram_dina(pool_2_result_bram_dina),
+        .pool_2_finish(pool_2_finish)
+    );
+    
+    // fc1
+    wire fc_1_bias_weights_bram_ena;
+    //wire [0:0] fc_1_bias_weights_bram_wea;
+    wire [18:0] fc_1_bias_weights_bram_addra;
+    //wire [7:0] fc_1_bias_weights_bram_dina;
+    reg [7:0] fc_1_bias_weights_bram_douta;
+    wire fc_1_result_bram_ena;
+    wire [0:0] fc_1_result_bram_wea; 
+    wire [14:0] fc_1_result_bram_addra;
+    wire [7:0] fc_1_result_bram_dina;
+    reg [7:0] fc_1_result_bram_douta;    
+    
+    fc_1 u_fc_1(
+        .clk(clk),
+        .rst(rst),
+        .fc_1_en(fc_1_en),
+        .bias_weights_bram_douta(fc_1_bias_weights_bram_douta),
+        .result_bram_douta(fc_1_result_bram_douta),
+        .bias_weights_bram_ena(fc_1_bias_weights_bram_ena),
+        .bias_weights_bram_addra(fc_1_bias_weights_bram_addra),
+        .result_bram_ena(fc_1_result_bram_ena),
+        .result_bram_wea(fc_1_result_bram_wea),
+        .result_bram_addra(fc_1_result_bram_addra),
+        .result_bram_dina(fc_1_result_bram_dina),
+        .fc_1_finish(fc_1_finish)
+    );
+    
+    // fc2
+    wire fc_2_bias_weights_bram_ena;
+    //wire [0:0] fc_2_bias_weights_bram_wea;
+    wire [18:0] fc_2_bias_weights_bram_addra;
+    //wire [7:0] fc_2_bias_weights_bram_dina;
+    reg [7:0] fc_2_bias_weights_bram_douta;
+    wire fc_2_result_bram_ena;
+    wire [0:0] fc_2_result_bram_wea; 
+    wire [14:0] fc_2_result_bram_addra;
+    wire [7:0] fc_2_result_bram_dina;
+    reg [7:0] fc_2_result_bram_douta;
+    
+    fc_2 u_fc_2(
+        .clk(clk),
+        .rst(rst),
+        .fc_2_en(fc_2_en),
+        .bias_weights_bram_douta(fc_2_bias_weights_bram_douta),
+        .result_bram_douta(fc_2_result_bram_douta),
+        .bias_weights_bram_ena(fc_2_bias_weights_bram_ena),
+        .bias_weights_bram_addra(fc_2_bias_weights_bram_addra),
+        .result_bram_ena(fc_2_result_bram_ena),
+        .result_bram_wea(fc_2_result_bram_wea),
+        .result_bram_addra(fc_2_result_bram_addra),
+        .result_bram_dina(fc_2_result_bram_dina),
+        .fc_2_finish(fc_2_finish),
+        .out_result(result)
+    );  
+    
+    // complete
+    wire complete_result_bram_ena;
+    wire [14:0] complete_result_bram_addra;
+    reg [7:0] complete_result_bram_douta;
+    wire [`DATA_SIZE*`OUTPUT_NODE-1:0] tempresult;
+    reg [`DATA_SIZE*`OUTPUT_NODE-1:0] result_1;
+    
+    //assign result = result_1;
+    
+    complete u_complete(
+        .clk(clk),
+        .rst(rst),
+        .complete_en(complete_en),
+        .result_bram_douta(complete_result_bram_douta),
+        .result_bram_ena(complete_result_bram_ena),
+        .result_bram_addra(complete_result_bram_addra),
+        .result(tempresult),
+        .complete_finish(complete_finish)
+    );
+    
+    // States
+    reg [7:0] state;
+    parameter S_IDLE   = 8'b10000000,
+              S_CONV_1 = 8'b01000000,
+              S_POOL_1 = 8'b00100000,
+              S_CONV_2 = 8'b00010000,
+              S_POOL_2 = 8'b00001000,
+              S_FC_1   = 8'b00000100,
+              S_FC_2   = 8'b00000010,
+              COMPLETE = 8'b00000001;
+    
+    always@(posedge clk)
+    begin
+        if(rst == 1'b1)
+        begin
+            state <= S_IDLE;
+            //finish <= 1'b1;
+            conv_1_en <= 1'b0;
+            pool_1_en <= 1'b0;
+            conv_2_en <= 1'b0;
+            pool_2_en <= 1'b0;
+            fc_1_en <= 1'b0;
+            relu_1_en <= 1'b0;
+            fc_2_en <= 1'b0;
+            result_1 <= 0;
+            complete_en <= 1'b0;
+        end
+        else
+        begin
+            case (state)
+                S_IDLE:
+                begin
+                    if(start == 1'b1)
+                    begin
+                        finish <= 1'b0;
+                        //result_1 <= 0;
+                        conv_1_en <= 1'b1;
+                        relu_1_en <= 1'b0;
+                        state <= S_CONV_1;
+                    end
+                    else
+                    begin
+                        state <= S_IDLE;
+                    end
+                end
+                S_CONV_1:
+                begin
+                    if(conv_1_finish == 1'b1)
+                    begin
+                        pool_1_en <= 1'b1;
+                        conv_1_en <= 1'b0;
+                        relu_1_en <= 1'b0;
+                        state <= S_POOL_1; 
+                    end
+                end
+                S_POOL_1:
+                begin
+                    if(pool_1_finish == 1'b1)
+                    begin
+                        conv_2_en <= 1'b1;
+                        pool_1_en <= 1'b0;
+                        relu_1_en <= 1'b0;
+                        state <= S_CONV_2;
+                    end
+                end
+                S_CONV_2:
+                begin
+                    if(conv_2_finish == 1'b1)
+                    begin
+                        pool_2_en <= 1'b1;
+                        conv_2_en <= 1'b0;
+                        relu_1_en <= 1'b0;
+                        state <= S_POOL_2;
+                    end
+                end
+                S_POOL_2:
+                begin
+                    if(pool_2_finish == 1'b1)
+                    begin
+                        fc_1_en <= 1'b1;
+                        pool_2_en <= 1'b0;
+                        relu_1_en <= 1'b1;
+                        state <= S_FC_1;
+                    end
+                end
+                S_FC_1:
+                begin
+                    if(fc_1_finish == 1'b1)
+                    begin
+                        fc_2_en <= 1'b1;
+                        fc_1_en <= 1'b0;
+                        relu_1_en <= 1'b0;
+                        state <= S_FC_2;
+                    end
+                end
+                S_FC_2:
+                begin
+                    if(fc_2_finish == 1'b1)
+                    begin
+                        complete_en <= 1'b1;
+                        fc_2_en <= 1'b0;
+                        relu_1_en <= 1'b0;
+                        state <= COMPLETE;
+                    end
+                end
+                COMPLETE:
+                begin
+                    if(complete_finish == 1'b1)
+                    begin
+                        result_1 <= tempresult;
+                        state <= S_IDLE;
+                        complete_en <= 1'b0;
+                        finish <= 1'b1;
+                    end
+                end
+                default:
+                begin
+                    state <= S_IDLE;
+                    conv_1_en <= 1'b0;
+                    pool_1_en <= 1'b0;
+                    conv_2_en <= 1'b0;
+                    pool_2_en <= 1'b0;
+                    fc_1_en <= 1'b0;
+                    relu_1_en <= 1'b0;
+                    fc_2_en <= 1'b0;
+                    complete_en <= 1'b0;
+                end
+            endcase
+        end
+    end
+    
+    // bias_weights_bram
+    always@(*)
+    begin
+        if(rst == 1'b1)
+        begin
+            bias_weights_bram_ena = 1'b0;
+            bias_weights_bram_wea = 1'b0;
+        end
+        else
+        begin
+            case (state)
+            S_CONV_1:
+            begin
+                bias_weights_bram_ena = conv_1_bias_weights_bram_ena;
+                bias_weights_bram_wea = 1'b0;
+                bias_weights_bram_addra = conv_1_bias_weights_bram_addra;
+                conv_1_bias_weights_bram_douta = bias_weights_bram_douta;
+            end
+            S_CONV_2:
+            begin
+                bias_weights_bram_ena = conv_2_bias_weights_bram_ena;
+                bias_weights_bram_wea = 1'b0;
+                bias_weights_bram_addra = conv_2_bias_weights_bram_addra;
+                conv_2_bias_weights_bram_douta = bias_weights_bram_douta;
+            end
+            S_FC_1:
+            begin
+                bias_weights_bram_ena = fc_1_bias_weights_bram_ena;
+                bias_weights_bram_wea = 1'b0;
+                bias_weights_bram_addra = fc_1_bias_weights_bram_addra;
+                fc_1_bias_weights_bram_douta = bias_weights_bram_douta;
+            end
+            S_FC_2:
+            begin
+                bias_weights_bram_ena = fc_2_bias_weights_bram_ena;
+                bias_weights_bram_wea = 1'b0;
+                bias_weights_bram_addra = fc_2_bias_weights_bram_addra;  
+                fc_2_bias_weights_bram_douta = bias_weights_bram_douta;
+            end
+            default:
+            begin
+                bias_weights_bram_ena = 1'b0;
+                bias_weights_bram_wea = 1'b0;
+            end
+            endcase
+        end
+    end
+    
+    // result_bram
+    always@(*)
+    begin
+        if(rst == 1'b1)
+        begin
+            result_bram_ena = 1'b0;
+            result_bram_wea = 1'b0;
+        end
+        else
+        begin
+            case(state)
+                S_CONV_1:
+                begin
+                    result_bram_ena = conv_1_result_bram_ena;
+                    result_bram_wea = conv_1_result_bram_wea;
+                    result_bram_addra = conv_1_result_bram_addra;
+                    result_bram_dina = conv_1_result_bram_dina;           
+                end
+                S_POOL_1:
+                begin
+                    result_bram_ena = pool_1_result_bram_ena;
+                    result_bram_wea = pool_1_result_bram_wea;
+                    result_bram_addra = pool_1_result_bram_addra;
+                    result_bram_dina = pool_1_result_bram_dina;
+                    pool_1_result_bram_douta = result_bram_douta;
+                end
+                S_CONV_2:
+                begin
+                    result_bram_ena = conv_2_result_bram_ena;
+                    result_bram_wea = conv_2_result_bram_wea;
+                    result_bram_addra = conv_2_result_bram_addra;
+                    result_bram_dina = conv_2_result_bram_dina;           
+                    conv_2_result_bram_douta = result_bram_douta;         
+                end
+                S_POOL_2:
+                begin
+                    result_bram_ena = pool_2_result_bram_ena;
+                    result_bram_wea = pool_2_result_bram_wea;
+                    result_bram_addra = pool_2_result_bram_addra;
+                    result_bram_dina = pool_2_result_bram_dina;    
+                    pool_2_result_bram_douta = result_bram_douta;                
+                end
+                S_FC_1:
+                begin
+                    result_bram_ena = fc_1_result_bram_ena;
+                    result_bram_wea = fc_1_result_bram_wea;
+                    result_bram_addra = fc_1_result_bram_addra;
+                    result_bram_dina = fc_1_result_bram_dina;   
+                    fc_1_result_bram_douta = result_bram_douta;                 
+                end
+                S_FC_2:
+                begin
+                    result_bram_ena = fc_2_result_bram_ena;
+                    result_bram_wea = fc_2_result_bram_wea;
+                    result_bram_addra = fc_2_result_bram_addra;
+                    result_bram_dina = fc_2_result_bram_dina;      
+                    fc_2_result_bram_douta = result_bram_douta;              
+                end
+                COMPLETE:
+                begin
+                    result_bram_ena = complete_result_bram_ena;
+                    result_bram_addra = complete_result_bram_addra;
+                    complete_result_bram_douta = result_bram_douta;
+                end
+                default:
+                begin
+                    result_bram_ena = 1'b0;
+                    result_bram_wea = 1'b0;
+                end
+            endcase
+        end
+    end
+    
+    // input_bram
+    always@(*)
+    begin
+        if(rst == 1'b1)
+        begin
+            input_bram_ena = 1'b0;
+            input_bram_wea = 1'b0;
+        end
+        else
+        begin
+            if(state == S_CONV_1)
+            begin
+                input_bram_ena = conv_1_input_bram_ena;
+                input_bram_wea = 1'b0;
+                input_bram_addra = conv_1_input_bram_addra;
+                conv_1_input_bram_douta = input_bram_douta;
+            end
+            else
+            begin
+                input_bram_ena = 1'b0;
+                input_bram_wea = 1'b0;
+            end
+        end
+    end
+    
+endmodule

zhan6841_FPGA-Accelerator-for-AES-LeNet-VGG16/LeNet/max_pool.v

@@ -0,0 +1,39 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 12/31/2017 07:38:39 AM
+// Design Name: 
+// Module Name: max_pool
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+`define DATA_SIZE 8
+
+module max_pool(
+    din, dout
+    );
+    input [4*`DATA_SIZE-1:0] din;
+    output [`DATA_SIZE-1:0] dout;
+    
+    wire [`DATA_SIZE-1:0] max_1;
+    wire [`DATA_SIZE-1:0] max_2;
+    
+    assign max_1 = ((din[4*`DATA_SIZE-1] == 1'b1) && (din[3*`DATA_SIZE-1] == 1'b0) || ((din[4*`DATA_SIZE-1] == din[3*`DATA_SIZE-1]) && (din[4*`DATA_SIZE-1:3*`DATA_SIZE] < din[3*`DATA_SIZE-1:2*`DATA_SIZE]))) ? din[3*`DATA_SIZE-1:2*`DATA_SIZE] : din[4*`DATA_SIZE-1:3*`DATA_SIZE];
+    
+    assign max_2 = ((max_1[`DATA_SIZE-1] == 1'b1) && (din[2*`DATA_SIZE-1] == 1'b0) || ((max_1[`DATA_SIZE-1] == din[2*`DATA_SIZE-1]) && (max_1 < din[2*`DATA_SIZE-1:`DATA_SIZE]))) ? din[2*`DATA_SIZE-1:`DATA_SIZE] : max_1;
+    
+    assign dout = ((max_2[`DATA_SIZE-1] == 1'b1) && (din[`DATA_SIZE-1] == 1'b0) || ((max_2[`DATA_SIZE-1] == din[`DATA_SIZE-1]) && (max_2 < din[`DATA_SIZE-1:0]))) ? din[`DATA_SIZE-1:0] : max_2;
+    
+endmodule

zhan6841_FPGA-Accelerator-for-AES-LeNet-VGG16/LeNet/multi_add.v

@@ -0,0 +1,72 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 12/31/2017 08:47:25 AM
+// Design Name: 
+// Module Name: multi_add
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+`define LENGTH 5
+`define WIDTH 5
+`define DATA_SIZE 8
+
+module multi_add(
+    matrix1, matrix2, bias, relu_1_en, dout
+    );
+    input [`DATA_SIZE*`LENGTH*`WIDTH-1:0] matrix1;
+    input [`DATA_SIZE*`LENGTH*`WIDTH-1:0] matrix2;
+    input [`DATA_SIZE-1:0] bias;
+    input relu_1_en;
+    output [`DATA_SIZE-1:0] dout;
+    
+    reg [2*`DATA_SIZE-1:0] temp;
+    reg sign;
+    reg [`DATA_SIZE-1:0] item1;
+    reg [`DATA_SIZE-1:0] item2;
+    reg [2*(`DATA_SIZE-1)-1:0] midvalue;
+    reg [`DATA_SIZE-1:0] result;
+    wire [`DATA_SIZE-1:0] relu_result;
+    
+    relu_1 ma_relu(
+        .din(result),
+        .dout(relu_result)
+    );
+    
+    integer i = 0;
+    integer data_begin = 0;
+    
+    assign dout = (relu_1_en == 1'b1) ? relu_result : result;
+    
+    always@(*)
+    begin
+        temp = 8'b0;
+        sign = 1'b0;
+        item1 = 8'b0;
+        item2 = 8'b0;
+        midvalue = 14'b0;
+        for(i = 0; i < `LENGTH*`WIDTH; i = i + 1)
+        begin
+            data_begin = `DATA_SIZE * (`LENGTH * `WIDTH - i) - 1;
+            sign = matrix1[data_begin] ^ matrix2[data_begin];
+            item1 = (matrix1[data_begin] == 1'b0) ? matrix1[data_begin-:8] : {matrix1[data_begin], ~matrix1[(data_begin-1)-:7] + 1'b1};
+            item2 = (matrix2[data_begin] == 1'b0) ? matrix2[data_begin-:8] : {matrix2[data_begin], ~matrix2[(data_begin-1)-:7] + 1'b1};
+            midvalue = item1[`DATA_SIZE-2:0] * item2[`DATA_SIZE-2:0];
+            temp = temp + {sign, midvalue, 1'b0};
+        end
+        temp = temp + {bias, 8'b0};
+        result = temp >> 8;
+    end
+endmodule

zhan6841_FPGA-Accelerator-for-AES-LeNet-VGG16/LeNet/pool_1.v

@@ -0,0 +1,189 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 12/30/2017 01:09:48 AM
+// Design Name: 
+// Module Name: pool_1
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+`define CONV1_DEEP 20
+`define POOL1_INPUT 24
+`define POOL1_OUTPUT 12
+`define POOL1_SIZE 2
+`define DATA_SIZE 8
+
+module pool_1(
+    clk, rst, pool_1_en, result_bram_douta,
+    result_bram_ena, result_bram_wea, result_bram_addra, result_bram_dina,
+    pool_1_finish
+    );
+    input clk;
+    input rst;
+    input pool_1_en;
+    input [`DATA_SIZE-1:0] result_bram_douta;
+    output reg result_bram_ena;
+    output reg result_bram_wea;
+    output reg [14:0] result_bram_addra;
+    output reg [`DATA_SIZE-1:0] result_bram_dina;
+    output reg pool_1_finish;
+    
+    reg [4*`DATA_SIZE-1:0] din;
+    wire [`DATA_SIZE-1:0] dout;
+    
+    reg [`DATA_SIZE-1:0] result;
+    
+    max_pool pool_1_mp(
+        .din(din),
+        .dout(dout)
+    );
+    
+    reg [4:0] state;
+    
+    parameter S_IDLE         = 5'b10000,
+              S_CHECK        = 5'b01000,
+              S_LOAD_DATA    = 5'b00100,
+              S_POOLING      = 5'b00010,
+              S_STORE_RESULT = 5'b00001;
+              
+    integer count = 0,
+            circle = 0,
+            channel = 0,
+            row = 0,
+            column = 0,
+            data_begin = 0;
+            
+    parameter conv1_result_base = 0,
+              pool1_result_base = 11520;
+    
+    always@(posedge clk)
+    begin
+        if(rst == 1'b1)
+        begin
+            state <= S_IDLE;
+            result_bram_ena <= 1'b0;
+            result_bram_wea <= 1'b0;
+        end
+        else
+        begin
+            if(pool_1_en == 1'b1)
+            begin
+                case(state)
+                    S_IDLE:
+                    begin
+                        channel <= 0;
+                        circle <= 0;
+                        row <= 0;
+                        column <= 0;
+                        din <= 0;
+                        result <= 0;
+                        pool_1_finish <= 1'b0;
+                        state <= S_CHECK;
+                    end
+                    S_CHECK:
+                    begin
+                        if(channel == `CONV1_DEEP)
+                        begin
+                            result_bram_ena <= 1'b0;
+                            result_bram_wea <= 1'b0;
+                            pool_1_finish <= 1'b1;
+                            state <= S_IDLE;
+                        end
+                        else
+                        begin
+                            circle <= 0;
+                            count <= 0;
+                            state <= S_LOAD_DATA;
+                        end
+                    end
+                    S_LOAD_DATA:
+                    begin
+                        if(count < `POOL1_SIZE * `POOL1_SIZE)
+                        begin
+                            if(circle == 0)
+                            begin
+                                result_bram_ena <= 1'b1;
+                                result_bram_addra <= conv1_result_base + channel * `POOL1_INPUT * `POOL1_INPUT + (row + (count / `POOL1_SIZE)) * `POOL1_INPUT + column + count % `POOL1_SIZE;
+                                circle <= circle + 1;
+                            end
+                            else if(circle == 3)
+                            begin
+                                data_begin = `DATA_SIZE * (`POOL1_SIZE * `POOL1_SIZE - count) - 1;
+                                din[data_begin-:`DATA_SIZE] <= result_bram_douta;
+                                count <= count + 1;
+                                circle <= 0;
+                            end
+                            else
+                            begin
+                                circle <= circle + 1;
+                            end
+                        end
+                        else
+                        begin
+                            circle <= 0;
+                            count <= 0;
+                            result_bram_ena <= 1'b0;
+                            state <= S_POOLING;
+                        end
+                    end
+                    S_POOLING:
+                    begin
+                        result <= dout;
+                        circle <= 0;
+                        state <= S_STORE_RESULT;
+                    end
+                    S_STORE_RESULT:
+                    begin
+                        if(circle == 0)
+                        begin
+                            result_bram_ena <= 1'b1;
+                            result_bram_wea <= 1'b1;
+                            result_bram_addra <= pool1_result_base + channel * `POOL1_OUTPUT * `POOL1_OUTPUT + row * `POOL1_OUTPUT + column;
+                            result_bram_dina <= result;
+                            circle <= circle + 1;
+                        end
+                        else if(circle == 3)
+                        begin
+                            result_bram_ena <= 1'b0;
+                            result_bram_wea <= 1'b0;
+                            circle <= 0;
+                            if(column == `POOL1_OUTPUT - 1)
+                            begin
+                                if(row == `POOL1_OUTPUT - 1)
+                                begin
+                                    channel <= channel + 1;
+                                end
+                                row <= (row + 1) % `POOL1_OUTPUT;
+                            end
+                            column <= (column + 1) % `POOL1_OUTPUT;
+                            state <= S_CHECK;
+                        end
+                        else
+                        begin
+                            circle <= circle + 1;
+                        end
+                    end
+                    default:
+                    begin
+                        state <= S_IDLE;
+                        result_bram_ena <= 1'b0;
+                        result_bram_wea <= 1'b0;
+                    end
+                endcase
+            end
+        end
+    end
+    
+endmodule

zhan6841_FPGA-Accelerator-for-AES-LeNet-VGG16/LeNet/pool_2.v

@@ -0,0 +1,189 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 01/01/2018 09:13:10 PM
+// Design Name: 
+// Module Name: pool_2
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+`define CONV2_DEEP 50
+`define POOL2_INPUT 8
+`define POOL2_OUTPUT 4
+`define POOL2_SIZE 2
+`define DATA_SIZE 8
+
+module pool_2(
+    clk, rst, pool_2_en, result_bram_douta,
+    result_bram_ena, result_bram_wea, result_bram_addra, result_bram_dina,
+    pool_2_finish
+    );
+    input clk;
+    input rst;
+    input pool_2_en;
+    input [`DATA_SIZE-1:0] result_bram_douta;
+    output reg result_bram_ena;
+    output reg result_bram_wea;
+    output reg [14:0] result_bram_addra;
+    output reg [`DATA_SIZE-1:0] result_bram_dina;
+    output reg pool_2_finish;
+    
+    reg [4*`DATA_SIZE-1:0] din;
+    wire [`DATA_SIZE-1:0] dout;
+    
+    reg [`DATA_SIZE-1:0] result;
+    
+    max_pool pool_2_mp(
+        .din(din),
+        .dout(dout)
+    );
+    
+    reg [4:0] state;
+    
+    parameter S_IDLE         = 5'b10000,
+              S_CHECK        = 5'b01000,
+              S_LOAD_DATA    = 5'b00100,
+              S_POOLING      = 5'b00010,
+              S_STORE_RESULT = 5'b00001;
+              
+    integer count = 0,
+            circle = 0,
+            channel = 0,
+            row = 0,
+            column = 0,
+            data_begin = 0;
+            
+    parameter conv2_result_base = 14400,
+              pool2_result_base = 17600;
+    
+    always@(posedge clk)
+    begin
+        if(rst == 1'b1)
+        begin
+            state <= S_IDLE;
+            result_bram_ena <= 1'b0;
+            result_bram_wea <= 1'b0;
+        end
+        else
+        begin
+            if(pool_2_en == 1'b1)
+            begin
+                case(state)
+                    S_IDLE:
+                    begin
+                        channel <= 0;
+                        circle <= 0;
+                        row <= 0;
+                        column <= 0;
+                        din <= 0;
+                        result <= 0;
+                        pool_2_finish <= 1'b0;
+                        state <= S_CHECK;
+                    end
+                    S_CHECK:
+                    begin
+                        if(channel == `CONV2_DEEP)
+                        begin
+                            result_bram_ena <= 1'b0;
+                            result_bram_wea <= 1'b0;
+                            pool_2_finish <= 1'b1;
+                            state <= S_IDLE;
+                        end
+                        else
+                        begin
+                            circle <= 0;
+                            count <= 0;
+                            state <= S_LOAD_DATA;
+                        end
+                    end
+                    S_LOAD_DATA:
+                    begin
+                        if(count < `POOL2_SIZE * `POOL2_SIZE)
+                        begin
+                            if(circle == 0)
+                            begin
+                                result_bram_ena <= 1'b1;
+                                result_bram_addra <= conv2_result_base + channel * `POOL2_INPUT * `POOL2_INPUT + (row + (count / `POOL2_SIZE)) * `POOL2_INPUT + column + count % `POOL2_SIZE;
+                                circle <= circle + 1;
+                            end
+                            else if(circle == 3)
+                            begin
+                                data_begin = `DATA_SIZE * (`POOL2_SIZE * `POOL2_SIZE - count) - 1;
+                                din[data_begin-:`DATA_SIZE] <= result_bram_douta;
+                                count <= count + 1;
+                                circle <= 0;
+                            end
+                            else
+                            begin
+                                circle <= circle + 1;
+                            end
+                        end
+                        else
+                        begin
+                            circle <= 0;
+                            count <= 0;
+                            result_bram_ena <= 1'b0;
+                            state <= S_POOLING;
+                        end
+                    end
+                    S_POOLING:
+                    begin
+                        result <= dout;
+                        circle <= 0;
+                        state <= S_STORE_RESULT;
+                    end
+                    S_STORE_RESULT:
+                    begin
+                        if(circle == 0)
+                        begin
+                            result_bram_ena <= 1'b1;
+                            result_bram_wea <= 1'b1;
+                            result_bram_addra <= pool2_result_base + channel * `POOL2_OUTPUT * `POOL2_OUTPUT + row * `POOL2_OUTPUT + column;
+                            result_bram_dina <= result;
+                            circle <= circle + 1;
+                        end
+                        else if(circle == 3)
+                        begin
+                            result_bram_ena <= 1'b0;
+                            result_bram_wea <= 1'b0;
+                            circle <= 0;
+                            if(column == `POOL2_OUTPUT - 1)
+                            begin
+                                if(row == `POOL2_OUTPUT - 1)
+                                begin
+                                    channel <= channel + 1;
+                                end
+                                row <= (row + 1) % `POOL2_OUTPUT;
+                            end
+                            column <= (column + 1) % `POOL2_OUTPUT;
+                            state <= S_CHECK;
+                        end
+                        else
+                        begin
+                            circle <= circle + 1;
+                        end
+                    end
+                    default:
+                    begin
+                        state <= S_IDLE;
+                        result_bram_ena <= 1'b0;
+                        result_bram_wea <= 1'b0;
+                    end
+                endcase
+            end
+        end
+    end
+    
+endmodule

zhan6841_FPGA-Accelerator-for-AES-LeNet-VGG16/LeNet/relu_1.v

@@ -0,0 +1,31 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 12/31/2017 07:55:17 AM
+// Design Name: 
+// Module Name: relu_1
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+`define DATA_SIZE 8
+
+module relu_1(
+    din, dout
+    );
+    input [`DATA_SIZE-1:0] din;
+    output [`DATA_SIZE-1:0] dout;
+    
+    assign dout = (din[`DATA_SIZE-1] == 1'b1) ? 8'b0 : din;
+endmodule

zhan6841_FPGA-Accelerator-for-AES-LeNet-VGG16/README.md

@@ -0,0 +1,4 @@
+# FPGA-Accelerator-for-AES-LeNet-VGG16
+AES: the verilog code are from http://www.aoki.ecei.tohoku.ac.jp/crypto/web/cores.html  
+LeNet:  
+VGG16: Bugs exist  

zhan6841_FPGA-Accelerator-for-AES-LeNet-VGG16/VGG16/README.md

@@ -0,0 +1 @@
+

zhan6841_FPGA-Accelerator-for-AES-LeNet-VGG16/VGG16/bram_top.v

@@ -0,0 +1,212 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 01/24/2018 11:39:15 PM
+// Design Name: 
+// Module Name: bram_top
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+`define DATA_SIZE 8
+
+module bram_top(
+    clk, rst,
+    loaddma_start, base_addr, num,
+    doutb_in,
+    data_ena, data_wea, data_addra, data_dina,
+    storedma_start, 
+    clkb_out, rstb_out, enb_out, web_out, addrb_out, dinb_out,
+    loaddma_finish,
+    vgg16_bram_douta,
+    storedma_finish
+    );
+    input clk;
+    input rst;
+    input loaddma_start;
+    input [19:0] base_addr;
+    input [31:0] num;
+    input [31:0] doutb_in;
+    input data_ena;
+    input [0:0] data_wea;
+    input [19:0] data_addra;
+    input [7:0] data_dina;
+    input storedma_start;
+    output clkb_out;
+    output rstb_out;
+    output reg enb_out;
+    output reg [3:0] web_out;
+    output reg [31:0] addrb_out;
+    output reg [31:0] dinb_out;
+    output reg loaddma_finish;
+    output [7:0] vgg16_bram_douta;
+    output reg storedma_finish;
+    
+    reg vgg16_bram_ena;
+    reg [0:0] vgg16_bram_wea;
+    reg [19:0] vgg16_bram_addra;
+    reg [7:0] vgg16_bram_dina;
+    // wire [7:0] vgg16_bram_douta;
+    
+    assign clkb_out = clk,
+           rstb_out = rst;
+    
+    blk_mem_gen_0 vgg16_bram (
+      .clka(clk),    // input wire clka
+      .ena(vgg16_bram_ena),      // input wire ena
+      .wea(vgg16_bram_wea),      // input wire [0 : 0] wea
+      .addra(vgg16_bram_addra),  // input wire [19 : 0] addra
+      .dina(vgg16_bram_dina),    // input wire [7 : 0] dina
+      .douta(vgg16_bram_douta)  // output wire [7 : 0] douta
+    );
+    
+    reg [2:0] state;
+    parameter S_IDLE = 3'b100,
+              S_LOAD_DMA = 3'b010,
+              S_STORE_DMA = 3'b001;
+              
+    reg [31:0] count;
+    
+    integer circle = 0,
+            databegin = 0,
+            total = 0;
+              
+    always@(posedge clk)
+    begin
+        if(rst == 1'b1)
+        begin
+            vgg16_bram_ena <= 1'b0;
+            vgg16_bram_wea <= 1'b0;
+            vgg16_bram_addra <= 20'b0;
+            vgg16_bram_dina <= 8'b0;
+            state <= S_IDLE;
+            enb_out <= 1'b0;
+            web_out <= 4'b0;
+            addrb_out <= 32'b0;
+            dinb_out <= 32'b0;
+            loaddma_finish <= 1'b0;
+        end
+        else
+        begin
+            case (state)
+                S_IDLE:
+                begin
+                    if(loaddma_start == 1'b1)
+                    begin
+                        enb_out <= 1'b1;
+                        addrb_out <= 32'b0;
+                        vgg16_bram_ena <= 1'b1;
+                        vgg16_bram_wea <= 1'b1;
+                        vgg16_bram_addra <= base_addr;
+                        count <= 32'b0;
+                        circle <= 0;
+                        state <= S_LOAD_DMA;
+                        loaddma_finish <= 1'b0;
+                    end
+                    else if(storedma_start == 1'b1)
+                    begin
+                        enb_out <= 1'b1;
+                        web_out <= 4'b1;
+                        addrb_out <= 32'b0;
+                        dinb_out <= 32'b0;
+                        vgg16_bram_ena <= 1'b1;
+                        vgg16_bram_addra <= base_addr;
+                        count <= 32'b0;
+                        circle <= 0;
+                        total <= 0;
+                        storedma_finish <= 1'b0;
+                        state <= S_STORE_DMA;
+                    end
+                    else
+                    begin
+                        vgg16_bram_ena <= data_ena;
+                        vgg16_bram_wea <= data_wea;
+                        vgg16_bram_addra <= data_addra;
+                        vgg16_bram_dina <= data_dina;
+                        state <= S_IDLE;
+                    end
+                end
+                S_LOAD_DMA:
+                begin
+                    if(count == num)
+                    begin
+                        count <= 32'b0;
+                        state <= S_IDLE;
+                        enb_out <= 1'b0;
+                        addrb_out <= 32'b0;
+                        circle <= 0;
+                        vgg16_bram_ena <= 1'b0;
+                        vgg16_bram_wea <= 1'b0;
+                        vgg16_bram_addra <= 20'b0;
+                        loaddma_finish <= 1'b1;
+                    end
+                    else
+                    begin
+                        databegin = `DATA_SIZE * (4 - circle) - 1;
+                        vgg16_bram_dina <= doutb_in[databegin-:8];
+                        vgg16_bram_addra <= vgg16_bram_addra + count[19:0];
+                        count <= count + 32'b1;
+                        circle = circle + 1;
+                        if(circle == 4)
+                        begin
+                            circle <= 0;
+                            addrb_out <= addrb_out + 32'b1;
+                        end
+                    end
+                end
+                S_STORE_DMA:
+                begin
+                    if(circle == 2)
+                    begin
+                        if(count == num)
+                        begin
+                            state <= S_IDLE;
+                            enb_out <= 1'b0;
+                            web_out <= 4'b0;
+                            addrb_out <= 32'b0;
+                            dinb_out <= 32'b0;
+                            vgg16_bram_ena <= 1'b0;
+                            vgg16_bram_addra <= 20'b0;
+                            count <= 32'b0;
+                            total <= 0;
+                            storedma_finish <= 1'b1;
+                        end
+                        else
+                        begin
+                            databegin = `DATA_SIZE * (4 - total) - 1;
+                            dinb_out[databegin-:8] <= vgg16_bram_douta;
+                            vgg16_bram_addra <= vgg16_bram_addra + 20'b1;
+                            count <= count + 32'b1;
+                            total = total + 1;
+                            if(total == 4)
+                            begin
+                                total <= 0;
+                                addrb_out <= addrb_out + 32'b1;
+                            end
+                        end
+                        circle <= 0;
+                    end
+                    else
+                    begin
+                        circle <= circle + 1;
+                    end
+                end
+                default:
+                begin
+                    state <= S_IDLE;
+                end
+            endcase
+        end
+    end
+endmodule

zhan6841_FPGA-Accelerator-for-AES-LeNet-VGG16/VGG16/conv.v

@@ -0,0 +1,555 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 01/21/2018 10:25:44 PM
+// Design Name: 
+// Module Name: conv
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+`define DATA_SIZE 8
+`define CONV_SIZE 3
+
+module conv(
+    clk, rst, conv_en, addbefore, vgg16_bram_douta, 
+    weight_base_addr, bias_base_addr, data_base_addr, result_base_addr,
+    rownum, columnnum, channelnum, filternum,
+    vgg16_bram_ena, vgg16_bram_wea, vgg16_bram_addra, vgg16_bram_dina,
+    conv_finish
+    );
+    input clk;
+    input rst;
+    input conv_en;
+    input addbefore;
+    input [7:0] vgg16_bram_douta;
+    input [19:0] weight_base_addr;
+    input [19:0] bias_base_addr;
+    input [19:0] data_base_addr;
+    input [19:0] result_base_addr;
+    input [9:0] rownum;
+    input [9:0] columnnum;
+    input [9:0] channelnum;
+    input [9:0] filternum;
+    output reg vgg16_bram_ena;
+    output reg [0:0] vgg16_bram_wea;
+    output reg [19:0] vgg16_bram_addra;
+    output reg [7:0] vgg16_bram_dina;
+    output reg conv_finish;
+    
+    reg [`DATA_SIZE*`CONV_SIZE*`CONV_SIZE-1:0] matrix1;
+    reg [`DATA_SIZE*`CONV_SIZE*`CONV_SIZE-1:0] matrix2;
+    reg [`DATA_SIZE-1:0] bias;
+    reg relu_en;
+    wire [`DATA_SIZE-1:0] dout;
+    
+    mult_add conv_ma(
+        .matrix1(matrix1), 
+        .matrix2(matrix2), 
+        .bias(bias), 
+        .relu_en(relu_en), 
+        .dout(dout)
+    );
+    
+    // reg [9:0] row;
+    // reg [9:0] column;
+    // reg [9:0] channel;
+    // reg [9:0] filter;
+    integer row = 0,
+            column = 0,
+            channel = 0,
+            filter = 0,
+            count = 0,
+            circle = 0,
+            databegin = 0;
+            
+    reg [`DATA_SIZE-1:0] result;
+    
+    reg [6:0] state;  
+    parameter S_IDLE         = 7'b1000000,
+              S_CHECK        = 7'b0100000,
+              S_LOAD_WEIGHTS = 7'b0010000,
+              S_LOAD_BIAS    = 7'b0001000,
+              S_LOAD_DATA    = 7'b0000100,
+              S_CONVOLUTE    = 7'b0000010,
+              S_STORE_RESULT = 7'b0000001;
+    
+    always@(posedge clk)
+    begin
+        if(rst == 1'b1)
+        begin
+            state <= S_IDLE;
+            vgg16_bram_ena <= 1'b0;
+            vgg16_bram_wea <= 1'b0;
+            row <= 0;
+            column <= 0;
+            channel <= 0;
+            filter <= 0;
+            count <= 0;
+            circle <= 0;
+        end
+        else
+        begin
+            if(conv_en == 1'b1)
+                begin
+                case (state)
+                    S_IDLE:
+                    begin
+                        row <= 0;
+                        column <= 0;
+                        channel <= 0;
+                        filter <= 0;
+                        count <= 0;
+                        circle <= 0;
+                        matrix1 <= 0;
+                        matrix2 <= 0;
+                        bias <= 0;
+                        relu_en <= 0;
+                        result <= 0;
+                        conv_finish <= 1'b0;
+                        state <= S_CHECK;
+                    end
+                    S_CHECK:
+                    begin
+                        if(filter == filternum)
+                        begin
+                            vgg16_bram_ena <= 1'b0;
+                            vgg16_bram_wea <= 1'b0;
+                            conv_finish <= 1'b1;
+                            state <= S_IDLE;
+                        end
+                        else
+                        begin
+                            circle <= 0;
+                            count <= 0;
+                            state <= S_LOAD_WEIGHTS;
+                        end
+                    end
+                    S_LOAD_WEIGHTS:
+                    begin
+                        if(count < `CONV_SIZE * `CONV_SIZE)
+                        begin
+                            if(circle == 0)
+                            begin
+                                vgg16_bram_ena <= 1'b1;
+                                vgg16_bram_addra <= weight_base_addr + filter * `CONV_SIZE * `CONV_SIZE * {10'b0, channelnum} + channel * `CONV_SIZE * `CONV_SIZE + count;
+                                circle <= circle + 1;
+                            end
+                            else if(circle == 2)
+                            begin
+                                databegin = `DATA_SIZE * (`CONV_SIZE * `CONV_SIZE - count) - 1;
+                                matrix2[databegin-:8] <= vgg16_bram_douta;
+                                count <= count + 1;
+                                circle <= 0;
+                            end
+                            else
+                            begin
+                                circle <= circle + 1;
+                            end
+                        end
+                        else
+                        begin
+                            circle <= 0;
+                            count <= 0;
+                            vgg16_bram_ena <= 1'b0;
+                            state <= S_LOAD_BIAS;
+                        end
+                    end
+                    S_LOAD_BIAS:
+                    begin
+                        if(channel == 0)
+                        begin
+                            if(circle == 0)
+                            begin
+                                vgg16_bram_ena <= 1'b1;
+                                vgg16_bram_addra <= bias_base_addr + filter;
+                                circle <= circle + 1;
+                            end
+                            else if(circle == 2)
+                            begin
+                                bias <= vgg16_bram_douta;
+                                circle <= 0;
+                                count <= 0;
+                                vgg16_bram_ena <= 1'b0;
+                                state <= S_LOAD_DATA;
+                            end
+                            else
+                            begin
+                                circle <= circle + 1;
+                            end
+                        end
+                        else
+                        begin
+                            bias <= result;
+                            state <= S_LOAD_DATA;
+                        end
+                    end
+                    S_LOAD_DATA:
+                    begin
+                        if(row > 0 && row < rownum - 10'b1 && column > 0 && column < columnnum - 10'b1)
+                        begin
+                            if(count < `CONV_SIZE * `CONV_SIZE)
+                            begin
+                                if(circle == 0)
+                                begin
+                                    vgg16_bram_ena <= 1'b1;
+                                    vgg16_bram_addra <= data_base_addr + channel * rownum * columnnum + ((row-1) + count / `CONV_SIZE) * rownum + (column-1) + count % `CONV_SIZE;
+                                    circle <= circle + 1;
+                                end
+                                else if(circle == 2)
+                                begin
+                                    databegin = `DATA_SIZE * (`CONV_SIZE * `CONV_SIZE - count) - 1;
+                                    matrix1[databegin-:8] <= vgg16_bram_douta;
+                                    count <= count + 1;
+                                    circle <= 0;
+                                end
+                                else
+                                begin
+                                    circle <= circle + 1;
+                                end
+                            end
+                            else
+                            begin
+                                circle <= 0;
+                                count <= 0;
+                                vgg16_bram_ena <= 1'b0;
+                                relu_en <= 1'b1;
+                                state <= S_CONVOLUTE;
+                            end
+                        end
+                        else if(row == 0)
+                        begin
+                            if(column == 0)
+                            begin
+                                if(count < (`CONV_SIZE - 1) * (`CONV_SIZE - 1))
+                                begin
+                                    if(circle == 0)
+                                    begin
+                                        vgg16_bram_ena <= 1'b1;
+                                        vgg16_bram_addra <= data_base_addr + channel * rownum * columnnum + (count / (`CONV_SIZE-1)) * rownum + column + count % (`CONV_SIZE-1);
+                                        circle <= circle + 1;
+                                    end
+                                    else if(circle == 2)
+                                    begin
+                                        databegin = `DATA_SIZE * (`CONV_SIZE * (`CONV_SIZE - 1) - (count/(`CONV_SIZE-1)+1) - count) - 1;
+                                        matrix1[databegin-:8] <= vgg16_bram_douta;
+                                        count <= count + 1;
+                                        circle <= 0;
+                                    end
+                                    else
+                                    begin
+                                        circle <= circle + 1;
+                                    end
+                                end
+                                else
+                                begin
+                                    matrix1[71:40] <= 32'b0;
+                                    matrix1[23:16] <= 8'b0;
+                                    circle <= 0;
+                                    count <= 0;
+                                    vgg16_bram_ena <= 1'b0;
+                                    relu_en <= 1'b1;
+                                    state <= S_CONVOLUTE;
+                                end
+                            end
+                            else if(column == columnnum - 10'b1)
+                            begin
+                                if(count < (`CONV_SIZE - 1) * (`CONV_SIZE - 1))
+                                begin
+                                    if(circle == 0)
+                                    begin
+                                        vgg16_bram_ena <= 1'b1;
+                                        vgg16_bram_addra <= data_base_addr + channel * rownum * columnnum + (count / (`CONV_SIZE-1)) * rownum + (column-1) + count % (`CONV_SIZE-1);
+                                        circle <= circle + 1;
+                                    end
+                                    else if(circle == 2)
+                                    begin
+                                        databegin = `DATA_SIZE * (`CONV_SIZE * (`CONV_SIZE - 1) - count/(`CONV_SIZE-1) - count) - 1;
+                                        matrix1[databegin-:8] <= vgg16_bram_douta;
+                                        count <= count + 1;
+                                        circle <= 0;
+                                    end
+                                    else
+                                    begin
+                                        circle <= circle + 1;
+                                    end
+                                end
+                                else
+                                begin
+                                    matrix1[71:48] <= 24'b0;
+                                    matrix1[31:24] <= 8'b0;
+                                    matrix1[7:0] <= 8'b0;
+                                    circle <= 0;
+                                    count <= 0;
+                                    vgg16_bram_ena <= 1'b0;
+                                    relu_en <= 1'b1;
+                                    state <= S_CONVOLUTE;
+                                end
+                            end
+                            else
+                            begin
+                                if(count < `CONV_SIZE * (`CONV_SIZE - 1))
+                                begin
+                                    if(circle == 0)
+                                    begin
+                                        vgg16_bram_ena <= 1'b1;
+                                        vgg16_bram_addra <= data_base_addr + channel * rownum * columnnum + (count / `CONV_SIZE) * rownum + (column-1) + count % `CONV_SIZE;
+                                        circle <= circle + 1;
+                                    end
+                                    else if(circle == 2)
+                                    begin
+                                        databegin = `DATA_SIZE * (`CONV_SIZE * (`CONV_SIZE - 1) - count) - 1;
+                                        matrix1[databegin-:8] <= vgg16_bram_douta;
+                                        count <= count + 1;
+                                        circle <= 0;
+                                    end
+                                    else
+                                    begin
+                                        circle <= circle + 1;
+                                    end
+                                end
+                                else
+                                begin
+                                    matrix1[71:48] <= 24'b0;
+                                    circle <= 0;
+                                    count <= 0;
+                                    vgg16_bram_ena <= 1'b0;
+                                    relu_en <= 1'b1;
+                                    state <= S_CONVOLUTE;
+                                end
+                            end
+                        end
+                        else if(row == rownum - 10'b1)
+                        begin
+                            if(column == 0)
+                            begin
+                                if(count < (`CONV_SIZE - 1) * (`CONV_SIZE - 1))
+                                begin
+                                    if(circle == 0)
+                                    begin
+                                        vgg16_bram_ena <= 1'b1;
+                                        vgg16_bram_addra <= data_base_addr + channel * rownum * columnnum + ((row-1) + count / (`CONV_SIZE-1)) * rownum + column + count % (`CONV_SIZE-1);
+                                        circle <= circle + 1;
+                                    end
+                                    else if(circle == 2)
+                                    begin
+                                        databegin = `DATA_SIZE * (`CONV_SIZE * `CONV_SIZE - (count/(`CONV_SIZE-1)+1) - count) - 1;
+                                        matrix1[databegin-:8] <= vgg16_bram_douta;
+                                        count <= count + 1;
+                                        circle <= 0;
+                                    end
+                                    else
+                                    begin
+                                        circle <= circle + 1;
+                                    end
+                                end
+                                else
+                                begin
+                                    matrix1[71:64] <= 8'b0;
+                                    matrix1[47:40] <= 8'b0;
+                                    matrix1[23:0] <= 24'b0;
+                                    circle <= 0;
+                                    count <= 0;
+                                    vgg16_bram_ena <= 1'b0;
+                                    relu_en <= 1'b1;
+                                    state <= S_CONVOLUTE;
+                                end
+                            end
+                            else if(column == columnnum - 10'b1)
+                            begin
+                                if(count < (`CONV_SIZE - 1) * (`CONV_SIZE - 1))
+                                begin
+                                    if(circle == 0)
+                                    begin
+                                        vgg16_bram_ena <= 1'b1;
+                                        vgg16_bram_addra <= data_base_addr + channel * rownum * columnnum + ((row-1) + count / (`CONV_SIZE-1)) * rownum + (column-1) + count % (`CONV_SIZE-1);
+                                        circle <= circle + 1;
+                                    end
+                                    else if(circle == 2)
+                                    begin
+                                        databegin = `DATA_SIZE * (`CONV_SIZE * `CONV_SIZE - count/(`CONV_SIZE-1) - count) - 1;
+                                        matrix1[databegin-:8] <= vgg16_bram_douta;
+                                        count <= count + 1;
+                                        circle <= 0;
+                                    end
+                                    else
+                                    begin
+                                        circle <= circle + 1;
+                                    end
+                                end
+                                else
+                                begin
+                                    matrix1[55:48] <= 8'b0;
+                                    matrix1[31:0] <= 32'b0;
+                                    circle <= 0;
+                                    count <= 0;
+                                    vgg16_bram_ena <= 1'b0;
+                                    relu_en <= 1'b1;
+                                    state <= S_CONVOLUTE;
+                                end
+                            end
+                            else
+                            begin
+                                if(count < `CONV_SIZE * (`CONV_SIZE - 1))
+                                begin
+                                    if(circle == 0)
+                                    begin
+                                        vgg16_bram_ena <= 1'b1;
+                                        vgg16_bram_addra <= data_base_addr + channel * rownum * columnnum + ((row-1) + count / `CONV_SIZE) * rownum + (column-1) + count % `CONV_SIZE;
+                                        circle <= circle + 1;
+                                    end
+                                    else if(circle == 2)
+                                    begin
+                                        databegin = `DATA_SIZE * (`CONV_SIZE * `CONV_SIZE - count) - 1;
+                                        matrix1[databegin-:8] <= vgg16_bram_douta;
+                                        count <= count + 1;
+                                        circle <= 0;
+                                    end
+                                    else
+                                    begin
+                                        circle <= circle + 1;
+                                    end
+                                end
+                                else
+                                begin
+                                    matrix1[23:0] <= 24'b0;
+                                    circle <= 0;
+                                    count <= 0;
+                                    vgg16_bram_ena <= 1'b0;
+                                    relu_en <= 1'b1;
+                                    state <= S_CONVOLUTE;
+                                end
+                            end
+                        end
+                    end
+                    S_CONVOLUTE:
+                    begin
+                        result <= dout;
+                        circle <= 0;
+                        state <= S_STORE_RESULT;
+                    end
+                    S_STORE_RESULT:
+                    begin
+                        if(addbefore == 1'b1)
+                        begin
+                            if(circle == 0)
+                            begin
+                                vgg16_bram_ena <= 1'b1;
+                                vgg16_bram_addra <= result_base_addr + filter * rownum * columnnum + row * rownum + column;
+                                circle <= circle + 1;
+                            end
+                            else if(circle == 2)
+                            begin
+                                vgg16_bram_dina <= result + vgg16_bram_douta;
+                                vgg16_bram_wea <= 1'b1;
+                                vgg16_bram_addra <= result_base_addr + filter * rownum * columnnum + row * rownum + column;
+                                circle <= circle + 1;
+                            end
+                            else if(circle == 3)
+                            begin
+                                vgg16_bram_ena <= 1'b0;
+                                vgg16_bram_wea <= 1'b0;
+                                circle <= 0;
+                                if(column == columnnum - 10'b1)
+                                begin
+                                    if(row == rownum - 10'b1)
+                                    begin
+                                        if(channel == channelnum - 10'b1)
+                                        begin
+                                            filter <= filter + 1;
+                                            channel <= 0;
+                                        end
+                                        else
+                                        begin
+                                            channel <= channel + 1;
+                                        end
+                                        row <= 0;
+                                    end
+                                    else
+                                    begin
+                                        row <= row + 1;
+                                    end
+                                    column <= 0;
+                                end
+                                else
+                                begin
+                                    column <= column + 1;
+                                end
+                                state <= S_CHECK;
+                            end
+                            else
+                            begin
+                                circle <= circle + 1;
+                            end
+                        end
+                        else
+                        begin
+                            if(circle == 0)
+                            begin
+                                vgg16_bram_ena <= 1'b1;
+                                vgg16_bram_wea <= 1'b1;
+                                vgg16_bram_addra <= result_base_addr + filter * rownum * columnnum + row * rownum + column;
+                                vgg16_bram_dina <= result;
+                                circle <= circle + 1;
+                            end
+                            else if(circle == 2)
+                            begin
+                                vgg16_bram_ena <= 1'b0;
+                                vgg16_bram_wea <= 1'b0;
+                                circle <= 0;
+                                if(column == columnnum - 10'b1)
+                                begin
+                                    if(row == rownum - 10'b1)
+                                    begin
+                                        if(channel == channelnum - 10'b1)
+                                        begin
+                                            filter <= filter + 1;
+                                            channel <= 0;
+                                        end
+                                        else
+                                        begin
+                                            channel <= channel + 1;
+                                        end
+                                        row <= 0;
+                                    end
+                                    else
+                                    begin
+                                        row <= row + 1;
+                                    end
+                                    column <= 0;
+                                end
+                                else
+                                begin
+                                    column <= column + 1;
+                                end
+                                state <= S_CHECK;
+                            end
+                            else
+                            begin
+                                circle <= circle + 1;
+                            end
+                        end
+                    end
+                    default:
+                    begin
+                        state <= S_IDLE;
+                        vgg16_bram_ena <= 1'b0;
+                        vgg16_bram_wea <= 1'b0;
+                    end
+                endcase
+            end
+        end
+    end
+    
+endmodule

zhan6841_FPGA-Accelerator-for-AES-LeNet-VGG16/VGG16/fc.v

@@ -0,0 +1,252 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 01/26/2018 08:39:53 AM
+// Design Name: 
+// Module Name: fc
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+`define DATA_SIZE 8
+`define CONV_SIZE 3
+
+module fc(
+    clk, rst, fc_en, 
+    weight_base_addr, bias_base_addr, data_base_addr, result_base_addr, rownum, columnnum,
+    vgg16_bram_douta, 
+    vgg16_bram_ena, vgg16_bram_wea, vgg16_bram_addra, vgg16_bram_dina, 
+    fc_finish
+    );
+    input clk;
+    input rst;
+    input fc_en;
+    input [19:0] weight_base_addr;
+    input [19:0] bias_base_addr;
+    input [19:0] data_base_addr;
+    input [19:0] result_base_addr;
+    input [9:0] rownum;
+    input [14:0] columnnum;
+    input [`DATA_SIZE-1:0] vgg16_bram_douta;
+    output reg vgg16_bram_ena;
+    output reg vgg16_bram_wea;
+    output reg [19:0] vgg16_bram_addra;
+    output reg [`DATA_SIZE-1:0] vgg16_bram_dina;
+    output reg fc_finish;
+    
+    reg [`DATA_SIZE*`CONV_SIZE*`CONV_SIZE-1:0] matrix1;
+    reg [`DATA_SIZE*`CONV_SIZE*`CONV_SIZE-1:0] matrix2;
+    reg [`DATA_SIZE-1:0] bias;
+    reg relu_en;
+    wire [`DATA_SIZE-1:0] dout;
+    reg [`DATA_SIZE-1:0] result;
+    
+    mult_add fc_ma(
+        .matrix1(matrix1),
+        .matrix2(matrix2),
+        .bias(bias),
+        .relu_en(relu_en),
+        .dout(dout)
+    );
+    
+    reg [6:0] state;
+    
+    parameter S_IDLE         = 7'b1000000,
+              S_CHECK        = 7'b0100000,
+              S_LOAD_WEIGHTS = 7'b0010000,
+              S_LOAD_BIAS    = 7'b0001000,
+              S_LOAD_DATA    = 7'b0000100,
+              S_MULTI_ADD    = 7'b0000010,
+              S_STORE_RESULT = 7'b0000001;
+              
+    integer count = 0,
+            row = 0,
+            column = 0,
+            circle = 0,
+            databegin = 0;
+            
+    always@(posedge clk)
+    begin
+        if(rst == 1'b1)
+        begin
+            state <= S_IDLE;
+            vgg16_bram_ena <= 1'b0;
+            vgg16_bram_wea <= 1'b0;
+        end
+        else
+        begin
+            if(fc_en == 1'b1)
+            begin
+                case (state)
+                    S_IDLE:
+                    begin
+                        row <= 0;
+                        column <= 0;
+                        matrix1 <= 0;
+                        matrix2 <= 0;
+                        bias <= 0;
+                        relu_en <= 0;
+                        result <= 0;
+                        fc_finish <= 0;
+                        state <= S_CHECK;
+                    end
+                    S_CHECK:
+                    begin
+                        if(row == rownum)
+                        begin
+                            vgg16_bram_ena <= 1'b0;
+                            vgg16_bram_wea <= 1'b0;
+                            relu_en <= 1'b0;
+                            fc_finish <= 1'b1;
+                            state <= S_IDLE;
+                        end
+                        else
+                        begin
+                            circle <= 0;
+                            count <= 0;
+                            result <= 0;
+                            state <= S_LOAD_WEIGHTS;
+                        end
+                    end
+                    S_LOAD_WEIGHTS:
+                    begin
+                        if(count < `CONV_SIZE * `CONV_SIZE)
+                        begin
+                            if(circle == 0)
+                            begin
+                                vgg16_bram_ena <= 1'b1;
+                                vgg16_bram_addra <= weight_base_addr + row * rownum + column;
+                                circle <= circle + 1;
+                            end
+                            else if(circle == 2)
+                            begin
+                                databegin = `DATA_SIZE * (`CONV_SIZE * `CONV_SIZE - count) - 1;
+                                matrix2[databegin-:8] <= vgg16_bram_douta;
+                                count <= count + 1;
+                                circle <= 0;
+                            end
+                            else
+                            begin
+                                circle <= circle + 1;
+                            end
+                        end
+                        else
+                        begin
+                            circle <= 0;
+                            count <= 0;
+                            column <= column - `CONV_SIZE * `CONV_SIZE;
+                            vgg16_bram_ena <= 1'b0;
+                            state <= S_LOAD_BIAS;
+                        end
+                    end
+                    S_LOAD_BIAS:
+                    begin
+                        if(column < `CONV_SIZE * `CONV_SIZE)
+                        begin
+                            if(circle == 0)
+                            begin
+                                vgg16_bram_ena <= 1'b1;
+                                vgg16_bram_addra <= bias_base_addr + row;
+                                circle <= circle + 1;
+                            end
+                            else if(circle == 2)
+                            begin
+                                bias <= vgg16_bram_douta;
+                                circle <= 0;
+                                count <= 0;
+                                vgg16_bram_ena <= 1'b0;
+                                state <= S_LOAD_DATA;
+                            end
+                        end
+                        else
+                        begin
+                            bias <= result;
+                            state <= S_LOAD_DATA;
+                        end
+                    end
+                    S_LOAD_DATA:
+                    begin
+                        if(count < `CONV_SIZE * `CONV_SIZE)
+                        begin
+                            if(circle == 0)
+                            begin
+                                vgg16_bram_ena <= 1'b1;
+                                vgg16_bram_addra <= data_base_addr + column;
+                                circle <= circle + 1;
+                            end
+                            else if(circle == 3)
+                            begin
+                                databegin = `DATA_SIZE * (`CONV_SIZE * `CONV_SIZE - count) - 1;
+                                matrix1[databegin-:8] <= vgg16_bram_douta;
+                                count <= count + 1;
+                                circle <= 0;
+                                column <= column + 1;
+                            end
+                            else
+                            begin
+                                circle <= circle + 1;
+                            end
+                        end
+                    end
+                    S_MULTI_ADD:
+                    begin
+                        result <= result + dout;
+                        if(column == columnnum)
+                        begin
+                            circle <= 0;
+                            state <= S_STORE_RESULT;
+                        end
+                        else
+                        begin
+                            circle <= 0;
+                            count <= 0;
+                            state <= S_LOAD_WEIGHTS;
+                        end
+                    end
+                    S_STORE_RESULT:
+                    begin
+                        if(circle == 0)
+                        begin
+                            vgg16_bram_ena <= 1'b1;
+                            vgg16_bram_wea <= 1'b1;
+                            vgg16_bram_addra <= result_base_addr + row;
+                            vgg16_bram_dina <= result;
+                            circle <= circle + 1;
+                        end
+                        else if(circle == 2)
+                        begin
+                            vgg16_bram_ena <= 1'b0;
+                            vgg16_bram_wea <= 1'b0;
+                            circle <= 0;
+                            column <= 0;
+                            count <= 0;
+                            row <= row + 1;
+                            state <= S_CHECK;
+                        end
+                        else
+                        begin
+                            circle <= circle + 1;
+                        end
+                    end
+                    default:
+                    begin
+                        state <= S_IDLE;
+                        vgg16_bram_ena <= 1'b0;
+                        vgg16_bram_wea <= 1'b0;
+                    end
+                endcase
+            end
+        end
+    end
+endmodule

zhan6841_FPGA-Accelerator-for-AES-LeNet-VGG16/VGG16/max_pool.v

@@ -0,0 +1,38 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 01/21/2018 09:49:17 PM
+// Design Name: 
+// Module Name: max_pool
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+`define DATA_SIZE 8
+
+module max_pool(
+    din, dout
+    );
+    input [4*`DATA_SIZE-1:0] din;
+    output [`DATA_SIZE-1:0] dout;
+    
+    wire [`DATA_SIZE-1:0] max_1;
+    wire [`DATA_SIZE-1:0] max_2;
+    
+    assign max_1 = ((din[4*`DATA_SIZE-1] == 1'b1) && (din[3*`DATA_SIZE-1] == 1'b0) || ((din[4*`DATA_SIZE-1] == din[3*`DATA_SIZE-1]) && (din[4*`DATA_SIZE-1:3*`DATA_SIZE] < din[3*`DATA_SIZE-1:2*`DATA_SIZE]))) ? din[3*`DATA_SIZE-1:2*`DATA_SIZE] : din[4*`DATA_SIZE-1:3*`DATA_SIZE];
+    
+    assign max_2 = ((max_1[`DATA_SIZE-1] == 1'b1) && (din[2*`DATA_SIZE-1] == 1'b0) || ((max_1[`DATA_SIZE-1] == din[2*`DATA_SIZE-1]) && (max_1 < din[2*`DATA_SIZE-1:`DATA_SIZE]))) ? din[2*`DATA_SIZE-1:`DATA_SIZE] : max_1;
+    
+    assign dout = ((max_2[`DATA_SIZE-1] == 1'b1) && (din[`DATA_SIZE-1] == 1'b0) || ((max_2[`DATA_SIZE-1] == din[`DATA_SIZE-1]) && (max_2 < din[`DATA_SIZE-1:0]))) ? din[`DATA_SIZE-1:0] : max_2;
+endmodule

zhan6841_FPGA-Accelerator-for-AES-LeNet-VGG16/VGG16/mult_add.v

@@ -0,0 +1,73 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 01/20/2018 03:04:16 AM
+// Design Name: 
+// Module Name: mult_add
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+`define LENGTH 3
+`define WIDTH 3
+`define DATA_SIZE 8
+
+module mult_add(
+    matrix1, matrix2, bias, relu_en, dout
+    );
+    input [`DATA_SIZE*`LENGTH*`WIDTH-1:0] matrix1;
+    input [`DATA_SIZE*`LENGTH*`WIDTH-1:0] matrix2;
+    input [`DATA_SIZE-1:0] bias;
+    input relu_en;
+    output [`DATA_SIZE-1:0] dout;
+    
+    reg [2*`DATA_SIZE-1:0] temp;
+    reg sign;
+    reg [`DATA_SIZE-1:0] item1;
+    reg [`DATA_SIZE-1:0] item2;
+    reg [2*(`DATA_SIZE-1)-1:0] midvalue;
+    reg [`DATA_SIZE-1:0] result;
+    wire [`DATA_SIZE-1:0] relu_result;
+    
+    relu ma_relu(
+        .din(result),
+        .dout(relu_result)
+    );
+    
+    integer i = 0;
+    integer data_begin = 0;
+    
+    assign dout = (relu_en == 1'b1) ? relu_result : result;
+    
+    always@(*)
+    begin
+        temp = 8'b0;
+        sign = 1'b0;
+        item1 = 8'b0;
+        item2 = 8'b0;
+        midvalue = 14'b0;
+        for(i = 0; i < `LENGTH*`WIDTH; i = i + 1)
+        begin
+            data_begin = `DATA_SIZE * (`LENGTH * `WIDTH - i) - 1;
+            sign = matrix1[data_begin] ^ matrix2[data_begin];
+            item1 = (matrix1[data_begin] == 1'b0) ? matrix1[data_begin-:8] : {matrix1[data_begin], ~matrix1[(data_begin-1)-:7] + 1'b1};
+            item2 = (matrix2[data_begin] == 1'b0) ? matrix2[data_begin-:8] : {matrix2[data_begin], ~matrix2[(data_begin-1)-:7] + 1'b1};
+            midvalue = item1[`DATA_SIZE-2:0] * item2[`DATA_SIZE-2:0];
+            temp = temp + {sign, midvalue, 1'b0};
+        end
+        temp = temp + {bias, 8'b0};
+        result = temp >> 8;
+    end
+    
+endmodule

zhan6841_FPGA-Accelerator-for-AES-LeNet-VGG16/VGG16/pool.v

@@ -0,0 +1,198 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 01/26/2018 08:05:24 AM
+// Design Name: 
+// Module Name: pool
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+`define DATA_SIZE 8
+`define POOL_SIZE 2
+
+module pool(
+    clk, rst, pool_en,
+    rownum, columnnum, channelnum,  
+    data_base_addr, result_base_addr, 
+    vgg16_bram_douta,
+    vgg16_bram_ena, vgg16_bram_wea, vgg16_bram_addra, vgg16_bram_dina, 
+    pool_finish
+    );
+    input clk;
+    input rst;
+    input pool_en;
+    input [9:0] rownum;
+    input [9:0] columnnum;
+    input [9:0] channelnum;
+    input [19:0] data_base_addr;
+    input [19:0] result_base_addr;
+    input [`DATA_SIZE-1:0] vgg16_bram_douta;
+    output reg vgg16_bram_ena;
+    output reg vgg16_bram_wea;
+    output reg [19:0] vgg16_bram_addra;
+    output reg [`DATA_SIZE-1:0] vgg16_bram_dina;
+    output reg pool_finish;
+    
+    reg [4*`DATA_SIZE-1:0] din;
+    wire [`DATA_SIZE-1:0] dout;
+    
+    reg [`DATA_SIZE-1:0] result;
+    
+    max_pool pool_mp(
+        .din(din),
+        .dout(dout)
+    );
+    
+    reg [4:0] state;
+    
+    parameter S_IDLE         = 5'b10000,
+              S_CHECK        = 5'b01000,
+              S_LOAD_DATA    = 5'b00100,
+              S_POOLING      = 5'b00010,
+              S_STORE_RESULT = 5'b00001;
+              
+    integer count = 0,
+            circle = 0,
+            row = 0,
+            column = 0,
+            channel = 0,
+            databegin = 0;
+            
+    always@(posedge clk)
+    begin
+        if(rst == 1'b1)
+        begin
+           state <= S_IDLE;
+           vgg16_bram_ena <= 1'b0;
+           vgg16_bram_wea <= 1'b0; 
+        end
+        else
+        begin
+            if(pool_en == 1'b1)
+            begin
+                case (state)
+                    S_IDLE:
+                    begin
+                        channel <= 0;
+                        circle <= 0;
+                        row <= 0;
+                        column <= 0;
+                        din <= 0;
+                        result <= 0;
+                        pool_finish <= 1'b0;
+                        state <= S_CHECK;
+                    end
+                    S_CHECK:
+                    begin
+                        if(channel == channelnum)
+                        begin
+                            vgg16_bram_ena <= 1'b0;
+                            vgg16_bram_wea <= 1'b0;
+                            pool_finish <= 1'b1;
+                            state <= S_IDLE;
+                        end
+                        else
+                        begin
+                            circle <= 0;
+                            count <= 0;
+                            state <= S_LOAD_DATA;
+                        end
+                    end
+                    S_LOAD_DATA:
+                    begin
+                        if(count < `POOL_SIZE * `POOL_SIZE)
+                        begin
+                            if(circle == 0)
+                            begin
+                                vgg16_bram_ena <= 1'b1;
+                                vgg16_bram_addra <= data_base_addr + channel * rownum * columnnum + (row*2 + (count / `POOL_SIZE)) * rownum + column*2 + count % `POOL_SIZE;
+                                circle <= circle + 1;
+                            end
+                            else if(circle == 2)
+                            begin
+                                databegin = `DATA_SIZE * (`POOL_SIZE * `POOL_SIZE - count) - 1;
+                                din[databegin-:8] <= vgg16_bram_douta;
+                                count <= count + 1;
+                                circle <= 0;
+                            end
+                            else
+                            begin
+                                circle <= circle + 1;
+                            end
+                        end
+                        else
+                        begin
+                            circle <= 0;
+                            count <= 0;
+                            vgg16_bram_ena <= 1'b0;
+                            state <= S_POOLING;
+                        end
+                    end
+                    S_POOLING:
+                    begin
+                        result <= dout;
+                        circle <= 0;
+                        state <= S_STORE_RESULT;
+                    end
+                    S_STORE_RESULT:
+                    begin
+                        if(circle == 0)
+                        begin
+                            vgg16_bram_ena <= 1'b1;
+                            vgg16_bram_wea <= 1'b1;
+                            vgg16_bram_addra <= result_base_addr + channel * rownum * columnnum + row * rownum + column;
+                            vgg16_bram_dina <= result;
+                            circle <= circle + 1;
+                        end
+                        else if(circle == 2)
+                        begin
+                            vgg16_bram_ena <= 1'b0;
+                            vgg16_bram_wea <= 1'b0;
+                            circle <= 0;
+                            if(column == columnnum - 10'b1)
+                            begin
+                                if(row == rownum - 10'b1)
+                                begin
+                                    row <= 0;
+                                    channel <= channel + 1;
+                                end
+                                else
+                                begin
+                                    row <= row + 1;
+                                end
+                                column <= 0;
+                            end
+                            else
+                            begin
+                                column <= column + 1;
+                            end
+                        end
+                        else
+                        begin
+                            circle <= circle + 1;
+                        end
+                    end
+                    default:
+                    begin
+                        state <= S_IDLE;
+                        vgg16_bram_ena <= 1'b0;
+                        vgg16_bram_wea <= 1'b0;
+                    end 
+                endcase
+            end
+        end
+    end
+    
+endmodule

zhan6841_FPGA-Accelerator-for-AES-LeNet-VGG16/VGG16/relu.v

@@ -0,0 +1,31 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 01/21/2018 09:44:48 PM
+// Design Name: 
+// Module Name: relu
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+`define DATA_SIZE 8
+
+module relu(
+    din, dout
+    );
+    input [`DATA_SIZE-1:0] din;
+    output [`DATA_SIZE-1:0] dout;
+    
+    assign dout = (din[`DATA_SIZE-1] == 1'b1) ? 8'b0 : din;
+endmodule

zhan6841_FPGA-Accelerator-for-AES-LeNet-VGG16/VGG16/vgg16.c

@@ -0,0 +1,6 @@
+
+
+/***************************** Include Files *******************************/
+#include "vgg16.h"
+
+/************************** Function Definitions ***************************/

zhan6841_FPGA-Accelerator-for-AES-LeNet-VGG16/VGG16/vgg16.h

@@ -0,0 +1,85 @@
+
+#ifndef VGG16_H
+#define VGG16_H
+
+
+/****************** Include Files ********************/
+#include "xil_types.h"
+#include "xstatus.h"
+
+#define VGG16_S00_AXI_SLV_REG0_OFFSET 0
+#define VGG16_S00_AXI_SLV_REG1_OFFSET 4
+#define VGG16_S00_AXI_SLV_REG2_OFFSET 8
+#define VGG16_S00_AXI_SLV_REG3_OFFSET 12
+#define VGG16_S00_AXI_SLV_REG4_OFFSET 16
+#define VGG16_S00_AXI_SLV_REG5_OFFSET 20
+#define VGG16_S00_AXI_SLV_REG6_OFFSET 24
+#define VGG16_S00_AXI_SLV_REG7_OFFSET 28
+#define VGG16_S00_AXI_SLV_REG8_OFFSET 32
+#define VGG16_S00_AXI_SLV_REG9_OFFSET 36
+
+
+/**************************** Type Definitions *****************************/
+/**
+ *
+ * Write a value to a VGG16 register. A 32 bit write is performed.
+ * If the component is implemented in a smaller width, only the least
+ * significant data is written.
+ *
+ * @param   BaseAddress is the base address of the VGG16device.
+ * @param   RegOffset is the register offset from the base to write to.
+ * @param   Data is the data written to the register.
+ *
+ * @return  None.
+ *
+ * @note
+ * C-style signature:
+ * 	void VGG16_mWriteReg(u32 BaseAddress, unsigned RegOffset, u32 Data)
+ *
+ */
+#define VGG16_mWriteReg(BaseAddress, RegOffset, Data) \
+  	Xil_Out32((BaseAddress) + (RegOffset), (u32)(Data))
+
+/**
+ *
+ * Read a value from a VGG16 register. A 32 bit read is performed.
+ * If the component is implemented in a smaller width, only the least
+ * significant data is read from the register. The most significant data
+ * will be read as 0.
+ *
+ * @param   BaseAddress is the base address of the VGG16 device.
+ * @param   RegOffset is the register offset from the base to write to.
+ *
+ * @return  Data is the data from the register.
+ *
+ * @note
+ * C-style signature:
+ * 	u32 VGG16_mReadReg(u32 BaseAddress, unsigned RegOffset)
+ *
+ */
+#define VGG16_mReadReg(BaseAddress, RegOffset) \
+    Xil_In32((BaseAddress) + (RegOffset))
+
+/************************** Function Prototypes ****************************/
+/**
+ *
+ * Run a self-test on the driver/device. Note this may be a destructive test if
+ * resets of the device are performed.
+ *
+ * If the hardware system is not built correctly, this function may never
+ * return to the caller.
+ *
+ * @param   baseaddr_p is the base address of the VGG16 instance to be worked on.
+ *
+ * @return
+ *
+ *    - XST_SUCCESS   if all self-test code passed
+ *    - XST_FAILURE   if any self-test code failed
+ *
+ * @note    Caching must be turned off for this function to work.
+ * @note    Self test may fail if data memory and device are not on the same bus.
+ *
+ */
+XStatus VGG16_Reg_SelfTest(void * baseaddr_p);
+
+#endif // VGG16_H

zhan6841_FPGA-Accelerator-for-AES-LeNet-VGG16/VGG16/vgg16_selftest.c

@@ -0,0 +1,60 @@
+
+/***************************** Include Files *******************************/
+#include "vgg16.h"
+#include "xparameters.h"
+#include "stdio.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions ***************************/
+#define READ_WRITE_MUL_FACTOR 0x10
+
+/************************** Function Definitions ***************************/
+/**
+ *
+ * Run a self-test on the driver/device. Note this may be a destructive test if
+ * resets of the device are performed.
+ *
+ * If the hardware system is not built correctly, this function may never
+ * return to the caller.
+ *
+ * @param   baseaddr_p is the base address of the VGG16instance to be worked on.
+ *
+ * @return
+ *
+ *    - XST_SUCCESS   if all self-test code passed
+ *    - XST_FAILURE   if any self-test code failed
+ *
+ * @note    Caching must be turned off for this function to work.
+ * @note    Self test may fail if data memory and device are not on the same bus.
+ *
+ */
+XStatus VGG16_Reg_SelfTest(void * baseaddr_p)
+{
+	u32 baseaddr;
+	int write_loop_index;
+	int read_loop_index;
+	int Index;
+
+	baseaddr = (u32) baseaddr_p;
+
+	xil_printf("******************************\n\r");
+	xil_printf("* User Peripheral Self Test\n\r");
+	xil_printf("******************************\n\n\r");
+
+	/*
+	 * Write to user logic slave module register(s) and read back
+	 */
+	xil_printf("User logic slave module test...\n\r");
+
+	for (write_loop_index = 0 ; write_loop_index < 4; write_loop_index++)
+	  VGG16_mWriteReg (baseaddr, write_loop_index*4, (write_loop_index+1)*READ_WRITE_MUL_FACTOR);
+	for (read_loop_index = 0 ; read_loop_index < 4; read_loop_index++)
+	  if ( VGG16_mReadReg (baseaddr, read_loop_index*4) != (read_loop_index+1)*READ_WRITE_MUL_FACTOR){
+	    xil_printf ("Error reading register value at address %x\n", (int)baseaddr + read_loop_index*4);
+	    return XST_FAILURE;
+	  }
+
+	xil_printf("   - slave register write/read passed\n\n\r");
+
+	return XST_SUCCESS;
+}

zhan6841_FPGA-Accelerator-for-AES-LeNet-VGG16/VGG16/vgg16_top.v

@@ -0,0 +1,790 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 01/24/2018 09:57:07 PM
+// Design Name: 
+// Module Name: vgg16_top
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module vgg16_top(
+    clk, rst,
+    layer, vgg16_start, addbefore, 
+    loaddma_start, base_addr, num, 
+    doutb_in,
+    storedma_start,
+    clkb_out, rstb_out, enb_out, web_out, addrb_out, dinb_out,
+    loaddma_finish,
+    storedma_finish,
+    vgg16_finish
+    );
+    input clk;
+    input rst;
+    input [4:0] layer;
+    input vgg16_start;
+    input addbefore;
+    input loaddma_start;
+    input [19:0] base_addr;
+    input [31:0] num;
+    input [31:0] doutb_in;
+    input storedma_start;
+    output clkb_out;
+    output rstb_out;
+    output enb_out;
+    output [3:0] web_out;
+    output [31:0] addrb_out;
+    output [31:0] dinb_out;
+    output loaddma_finish;
+    output storedma_finish;
+    output reg vgg16_finish;
+    
+    reg vgg16_bram_ena;
+    reg vgg16_bram_wea;
+    reg [19:0] vgg16_bram_addra;
+    reg [`DATA_SIZE-1:0] vgg16_bram_dina;
+    
+    wire [`DATA_SIZE:0] vgg16_bram_douta;
+    
+    bram_top vgg16_bram(
+        .clk(clk), 
+        .rst(rst),
+        .loaddma_start(loaddma_start), 
+        .base_addr(base_addr), 
+        .num(num),
+        .doutb_in(doutb_in),
+        .data_ena(vgg16_bram_ena), 
+        .data_wea(vgg16_bram_wea), 
+        .data_addra(vgg16_bram_addra), 
+        .data_dina(vgg16_bram_dina),
+        .storedma_start(storedma_start), 
+        .clkb_out(clkb_out), 
+        .rstb_out(rstb_out), 
+        .enb_out(enb_out), 
+        .web_out(web_out), 
+        .addrb_out(addrb_out), 
+        .dinb_out(dinb_out),
+        .loaddma_finish(loaddma_finish),
+        .vgg16_bram_douta(vgg16_bram_douta),
+        .storedma_finish(storedma_finish)
+    );
+    
+    reg [9:0] rownum;
+    reg [9:0] columnnum;
+    reg [9:0] channelnum;
+    reg [9:0] filternum;
+    reg [19:0] weight_base_addr;
+    reg [19:0] bias_base_addr;
+    reg [19:0] data_base_addr;
+    reg [19:0] result_base_addr;
+    
+    reg conv_en;
+    reg [`DATA_SIZE-1:0] conv_vgg16_bram_douta;
+    wire conv_vgg16_bram_ena;
+    wire [0:0] conv_vgg16_bram_wea;
+    wire [19:0] conv_vgg16_bram_addra;
+    wire [`DATA_SIZE-1:0] conv_vgg16_bram_dina;
+    wire conv_finish;
+    
+    conv vgg16_conv(
+        .clk(clk), 
+        .rst(rst), 
+        .conv_en(conv_en), 
+        .vgg16_bram_douta(conv_vgg16_bram_douta), 
+        .weight_base_addr(weight_base_addr), 
+        .bias_base_addr(bias_base_addr), 
+        .data_base_addr(data_base_addr), 
+        .result_base_addr(result_base_addr),
+        .rownum(rownum), 
+        .columnnum(columnnum), 
+        .channelnum(channelnum), 
+        .filternum(filternum),
+        .vgg16_bram_ena(conv_vgg16_bram_ena), 
+        .vgg16_bram_wea(conv_vgg16_bram_wea), 
+        .vgg16_bram_addra(conv_vgg16_bram_addra), 
+        .vgg16_bram_dina(conv_vgg16_bram_dina),
+        .conv_finish(conv_finish)
+    );
+    
+    reg pool_en;
+    reg [`DATA_SIZE-1:0] pool_vgg16_bram_douta;
+    wire pool_vgg16_bram_ena;
+    wire [0:0] pool_vgg16_bram_wea;
+    wire [19:0] pool_vgg16_bram_addra;
+    wire [`DATA_SIZE-1:0] pool_vgg16_bram_dina;
+    wire pool_finish;
+    
+    pool vgg16_pool(
+        .clk(clk), 
+        .rst(rst), 
+        .pool_en(pool_en),
+        .rownum(rownum), 
+        .columnnum(columnnum), 
+        .channelnum(channelnum),  
+        .data_base_addr(data_base_addr), 
+        .result_base_addr(result_base_addr), 
+        .vgg16_bram_douta(pool_vgg16_bram_douta),
+        .vgg16_bram_ena(pool_vgg16_bram_ena), 
+        .vgg16_bram_wea(pool_vgg16_bram_wea), 
+        .vgg16_bram_addra(pool_vgg16_bram_addra), 
+        .vgg16_bram_dina(pool_vgg16_bram_dina), 
+        .pool_finish(pool_finish)
+    );
+    
+    reg fc_en;
+    reg [`DATA_SIZE-1:0] fc_vgg16_bram_douta;
+    wire fc_vgg16_bram_ena;
+    wire [0:0] fc_vgg16_bram_wea;
+    wire [19:0] fc_vgg16_bram_addra;
+    wire [`DATA_SIZE-1:0] fc_vgg16_bram_dina;
+    wire fc_finish;
+    
+    reg [14:0] fc_columnnum;
+    
+    fc vgg16_fc(
+        .clk(clk), 
+        .rst(rst), 
+        .fc_en(fc_en), 
+        .weight_base_addr(weight_base_addr), 
+        .bias_base_addr(bias_base_addr), 
+        .data_base_addr(data_base_addr), 
+        .result_base_addr(result_base_addr), 
+        .rownum(rownum), 
+        .columnnum(fc_columnnum),
+        .vgg16_bram_douta(fc_vgg16_bram_douta), 
+        .vgg16_bram_ena(fc_vgg16_bram_ena), 
+        .vgg16_bram_wea(fc_vgg16_bram_wea), 
+        .vgg16_bram_addra(fc_vgg16_bram_addra), 
+        .vgg16_bram_dina(fc_vgg16_bram_dina), 
+        .fc_finish(fc_finish)
+    );
+    
+    parameter conv1_1_data_base_addr   = 0,
+              conv1_1_weight_base_addr = 150528,
+              conv1_1_bias_base_addr   = 150636,
+              conv1_1_result_base_addr = 150640;
+    
+    parameter conv1_2_data_base_addr   = 0,
+              conv1_2_weight_base_addr = 200704,
+              conv1_2_bias_base_addr   = 200848,
+              conv1_2_result_base_addr = 200852;
+    
+    parameter conv2_data_base_addr   = 0,
+              conv2_weight_base_addr = 200704,
+              conv2_bias_base_addr   = 203008,
+              conv2_result_base_addr = 203024;
+    
+    parameter conv3_data_base_addr   = 0,
+              conv3_weight_base_addr = 200704,
+              conv3_bias_base_addr   = 237568,
+              conv3_result_base_addr = 237632;
+    
+    parameter conv4_data_base_addr   = 0,
+              conv4_weight_base_addr = 200704,
+              conv4_bias_base_addr   = 348160,
+              conv4_result_base_addr = 348224;
+    
+    parameter conv5_data_base_addr   = 0,
+              conv5_weight_base_addr = 100352,
+              conv5_bias_base_addr   = 395264,
+              conv5_result_base_addr = 395328;
+    
+    parameter pool1_data_base_addr   = 0,
+              pool1_result_base_addr = 200704;
+    
+    parameter pool2_data_base_addr   = 0,
+              pool2_result_base_addr = 200704;
+    
+    parameter pool3_data_base_addr   = 0,
+              pool3_result_base_addr = 200704;
+    
+    parameter pool4_data_base_addr   = 0,
+              pool4_result_base_addr = 200704;
+    
+    parameter pool5_data_base_addr   = 0,
+              pool5_result_base_addr = 100352;
+    
+    parameter fc1_data_base_addr   = 0,
+              fc1_weight_base_addr = 25088,
+              fc1_bias_base_addr   = 426496,
+              fc1_result_base_addr = 426512;
+    
+    parameter fc2_data_base_addr   = 0,
+              fc2_weight_base_addr = 4096,
+              fc2_bias_base_addr   = 528384,
+              fc2_result_base_addr = 528512;
+    
+    parameter fc3_data_base_addr   = 0,
+              fc3_weight_base_addr = 4096,
+              fc3_bias_base_addr   = 516096,
+              fc3_result_base_addr = 516221;
+    
+    reg [21:0] state;
+    
+    parameter S_IDLE     = 22'b1000_0000_0000_0000_0000_00,
+              S_CONV1_1  = 22'b0100_0000_0000_0000_0000_00,
+              S_CONV1_2  = 22'b0010_0000_0000_0000_0000_00,
+              S_POOL1    = 22'b0001_0000_0000_0000_0000_00,
+              S_CONV2_1  = 22'b0000_1000_0000_0000_0000_00,
+              S_CONV2_2  = 22'b0000_0100_0000_0000_0000_00,
+              S_POOL2    = 22'b0000_0010_0000_0000_0000_00,
+              S_CONV3_1  = 22'b0000_0001_0000_0000_0000_00,
+              S_CONV3_2  = 22'b0000_0000_1000_0000_0000_00,
+              S_CONV3_3  = 22'b0000_0000_0100_0000_0000_00,
+              S_POOL3    = 22'b0000_0000_0010_0000_0000_00,
+              S_CONV4_1  = 22'b0000_0000_0001_0000_0000_00,
+              S_CONV4_2  = 22'b0000_0000_0000_1000_0000_00,
+              S_CONV4_3  = 22'b0000_0000_0000_0100_0000_00,
+              S_POOL4    = 22'b0000_0000_0000_0010_0000_00,
+              S_CONV5_1  = 22'b0000_0000_0000_0001_0000_00,
+              S_CONV5_2  = 22'b0000_0000_0000_0000_1000_00,
+              S_CONV5_3  = 22'b0000_0000_0000_0000_0100_00,
+              S_POOL5    = 22'b0000_0000_0000_0000_0010_00,
+              S_FC1      = 22'b0000_0000_0000_0000_0001_00,
+              S_FC2      = 22'b0000_0000_0000_0000_0000_10,
+              S_FC3      = 22'b0000_0000_0000_0000_0000_01;
+              
+    always@(posedge clk)
+    begin
+        if(rst == 1'b1)
+        begin
+            state <= S_IDLE;
+            conv_en <= 1'b0;
+            pool_en <= 1'b0;
+            fc_en <= 1'b0;
+        end
+        else
+        begin
+            case (state)
+                S_IDLE:
+                begin
+                    if(vgg16_start == 1'b1)
+                    begin
+                        vgg16_finish <= 1'b0;
+                        case (layer)
+                            5'b00000:  // 0  conv1_1
+                            begin
+                                conv_en <= 1'b1;
+                                weight_base_addr <= conv1_1_weight_base_addr;
+                                bias_base_addr <= conv1_1_bias_base_addr;
+                                data_base_addr <= conv1_1_data_base_addr;
+                                result_base_addr <= conv1_1_result_base_addr;
+                                rownum <= 10'd224;
+                                columnnum <= 10'd224;
+                                channelnum <= 10'd3;
+                                filternum <= 10'd4;
+                                state <= S_CONV1_1;
+                            end
+                            5'b00001:  // 1  conv1_2
+                            begin
+                                conv_en <= 1'b1;    
+                                weight_base_addr <= conv1_2_weight_base_addr;
+                                bias_base_addr <= conv1_2_bias_base_addr;
+                                data_base_addr <= conv1_2_data_base_addr;
+                                result_base_addr <= conv1_2_result_base_addr;
+                                rownum <= 10'd224;
+                                columnnum <= 10'd224;
+                                channelnum <= 10'd4;
+                                filternum <= 10'd4;     
+                                state <= S_CONV1_2;
+                            end
+                            5'b00010:  // 2  pool1
+                            begin
+                                pool_en <= 1'b1;
+                                rownum <= 10'd112;
+                                columnnum <= 10'd112;
+                                channelnum <= 10'd4;
+                                data_base_addr <= pool1_data_base_addr;
+                                result_base_addr <= pool1_result_base_addr;
+                                state <= S_POOL1;
+                            end
+                            5'b00011:  // 3  conv2_1
+                            begin
+                                conv_en <= 1'b1;
+                                weight_base_addr <= conv2_weight_base_addr;
+                                bias_base_addr <= conv2_bias_base_addr;
+                                data_base_addr <= conv2_data_base_addr;
+                                result_base_addr <= conv2_result_base_addr;
+                                rownum <= 10'd112;
+                                columnnum <= 10'd112;
+                                channelnum <= 10'd16;
+                                filternum <= 10'd16;    
+                                state <= S_CONV2_1;
+                            end
+                            5'b00100:  // 4  conv2_2
+                            begin
+                                conv_en <= 1'b1;
+                                weight_base_addr <= conv2_weight_base_addr;
+                                bias_base_addr <= conv2_bias_base_addr;
+                                data_base_addr <= conv2_data_base_addr;
+                                result_base_addr <= conv2_result_base_addr;
+                                rownum <= 10'd112;
+                                columnnum <= 10'd112;
+                                channelnum <= 10'd16;
+                                filternum <= 10'd16; 
+                                state <= S_CONV2_2;
+                            end
+                            5'b00101:  // 5  pool2
+                            begin
+                                pool_en <= 1'b1;
+                                rownum <= 10'd56;
+                                columnnum <= 10'd56;
+                                channelnum <= 10'd16;
+                                data_base_addr <= pool2_data_base_addr;
+                                result_base_addr <= pool2_result_base_addr;
+                                state <= S_POOL2;
+                            end
+                            5'b00110:  // 6  conv3_1
+                            begin
+                                conv_en <= 1'b1;
+                                weight_base_addr <= conv3_weight_base_addr;
+                                bias_base_addr <= conv3_bias_base_addr;
+                                data_base_addr <= conv3_data_base_addr;
+                                result_base_addr <= conv3_result_base_addr;
+                                rownum <= 10'd56;
+                                columnnum <= 10'd56;
+                                channelnum <= 10'd64;
+                                filternum <= 10'd64; 
+                                state <= S_CONV3_1;
+                            end
+                            5'b00111:  // 7  conv3_2
+                            begin
+                                conv_en <= 1'b1;
+                                weight_base_addr <= conv3_weight_base_addr;
+                                bias_base_addr <= conv3_bias_base_addr;
+                                data_base_addr <= conv3_data_base_addr;
+                                result_base_addr <= conv3_result_base_addr;
+                                rownum <= 10'd56;
+                                columnnum <= 10'd56;
+                                channelnum <= 10'd64;
+                                filternum <= 10'd64; 
+                                state <= S_CONV3_2;
+                            end
+                            5'b01000:  // 8  conv3_3
+                            begin
+                                conv_en <= 1'b1;
+                                weight_base_addr <= conv3_weight_base_addr;
+                                bias_base_addr <= conv3_bias_base_addr;
+                                data_base_addr <= conv3_data_base_addr;
+                                result_base_addr <= conv3_result_base_addr;
+                                rownum <= 10'd56;
+                                columnnum <= 10'd56;
+                                channelnum <= 10'd64;
+                                filternum <= 10'd64; 
+                                state <= S_CONV3_3;
+                            end
+                            5'b01001:  // 9  pool3
+                            begin
+                                pool_en <= 1'b1;
+                                rownum <= 10'd28;
+                                columnnum <= 10'd28;
+                                channelnum <= 10'd64;
+                                data_base_addr <= pool3_data_base_addr;
+                                result_base_addr <= pool3_result_base_addr;
+                                state <= S_POOL3;
+                            end
+                            5'b01010:  // 10 conv4_1
+                            begin
+                                conv_en <= 1'b1;
+                                weight_base_addr <= conv4_weight_base_addr;
+                                bias_base_addr <= conv4_bias_base_addr;
+                                data_base_addr <= conv4_data_base_addr;
+                                result_base_addr <= conv4_result_base_addr;
+                                rownum <= 10'd28;
+                                columnnum <= 10'd28;
+                                channelnum <= 10'd256;
+                                filternum <= 10'd64; 
+                                state <= S_CONV4_1;
+                            end
+                            5'b01011:  // 11 conv4_2
+                            begin
+                                conv_en <= 1'b1;
+                                weight_base_addr <= conv4_weight_base_addr;
+                                bias_base_addr <= conv4_bias_base_addr;
+                                data_base_addr <= conv4_data_base_addr;
+                                result_base_addr <= conv4_result_base_addr;
+                                rownum <= 10'd28;
+                                columnnum <= 10'd28;
+                                channelnum <= 10'd256;
+                                filternum <= 10'd64; 
+                                state <= S_CONV4_2;
+                            end
+                            5'b01100:  // 12 conv4_3
+                            begin
+                                conv_en <= 1'b1;
+                                weight_base_addr <= conv4_weight_base_addr;
+                                bias_base_addr <= conv4_bias_base_addr;
+                                data_base_addr <= conv4_data_base_addr;
+                                result_base_addr <= conv4_result_base_addr;
+                                rownum <= 10'd28;
+                                columnnum <= 10'd28;
+                                channelnum <= 10'd256;
+                                filternum <= 10'd64; 
+                                state <= S_CONV4_3;
+                            end
+                            5'b01101:  // 13 pool4
+                            begin
+                                pool_en <= 1'b1;
+                                rownum <= 10'd14;
+                                columnnum <= 10'd14;
+                                channelnum <= 10'd256;
+                                data_base_addr <= pool4_data_base_addr;
+                                result_base_addr <= pool4_result_base_addr;
+                                state <= S_POOL4;
+                            end
+                            5'b01110:  // 14 conv5_1
+                            begin
+                                conv_en <= 1'b1;
+                                weight_base_addr <= conv5_weight_base_addr;
+                                bias_base_addr <= conv5_bias_base_addr;
+                                data_base_addr <= conv5_data_base_addr;
+                                result_base_addr <= conv5_result_base_addr;
+                                rownum <= 10'd14;
+                                columnnum <= 10'd14;
+                                channelnum <= 10'd512;
+                                filternum <= 10'd64; 
+                                state <= S_CONV5_1;
+                            end
+                            5'b01111:  // 15 conv5_2
+                            begin
+                                conv_en <= 1'b1;
+                                weight_base_addr <= conv5_weight_base_addr;
+                                bias_base_addr <= conv5_bias_base_addr;
+                                data_base_addr <= conv5_data_base_addr;
+                                result_base_addr <= conv5_result_base_addr;
+                                rownum <= 10'd14;
+                                columnnum <= 10'd14;
+                                channelnum <= 10'd512;
+                                filternum <= 10'd64; 
+                                state <= S_CONV5_2;
+                            end
+                            5'b10000:  // 16 conv5_3
+                            begin
+                                conv_en <= 1'b1;
+                                weight_base_addr <= conv5_weight_base_addr;
+                                bias_base_addr <= conv5_bias_base_addr;
+                                data_base_addr <= conv5_data_base_addr;
+                                result_base_addr <= conv5_result_base_addr;
+                                rownum <= 10'd14;
+                                columnnum <= 10'd14;
+                                channelnum <= 10'd512;
+                                filternum <= 10'd64; 
+                                state <= S_CONV5_3;
+                            end
+                            5'b10001:  // 17 pool5
+                            begin
+                                pool_en <= 1'b1;
+                                rownum <= 10'd7;
+                                columnnum <= 10'd7;
+                                channelnum <= 10'd512;
+                                data_base_addr <= pool5_data_base_addr;
+                                result_base_addr <= pool5_result_base_addr;
+                                state <= S_POOL5;
+                            end
+                            5'b10010:  // 18 fc1
+                            begin
+                                fc_en <= 1'b1;
+                                weight_base_addr <= fc1_weight_base_addr;
+                                bias_base_addr <= fc1_bias_base_addr;
+                                data_base_addr <= fc1_data_base_addr;
+                                result_base_addr <= fc1_result_base_addr;
+                                rownum <= 10'd16;
+                                fc_columnnum <= 15'd25088;
+                                state <= S_FC1;
+                            end
+                            5'b10011:  // 19 fc2
+                            begin
+                                fc_en <= 1'b1;
+                                weight_base_addr <= fc2_weight_base_addr;
+                                bias_base_addr <= fc2_bias_base_addr;
+                                data_base_addr <= fc2_data_base_addr;
+                                result_base_addr <= fc2_result_base_addr;
+                                rownum <= 10'd128;
+                                fc_columnnum <= 15'd4096;
+                                state <= S_FC2;
+                            end
+                            5'b10100:  // 20 fc3
+                            begin
+                                fc_en <= 1'b1;
+                                weight_base_addr <= fc3_weight_base_addr;
+                                bias_base_addr <= fc3_bias_base_addr;
+                                data_base_addr <= fc3_data_base_addr;
+                                result_base_addr <= fc3_result_base_addr;
+                                rownum <= 10'd125;
+                                fc_columnnum <= 15'd4096;
+                                state <= S_FC3;
+                            end
+                            default:
+                            begin
+                                conv_en <= 1'b0;
+                                pool_en <= 1'b0;
+                                fc_en <= 1'b0;
+                                state <= S_IDLE;
+                            end
+                        endcase
+                    end
+                    else
+                    begin
+                        vgg16_finish <= 1'b0;
+                        state <= S_IDLE;
+                    end
+                end
+                S_CONV1_1:
+                begin
+                    if(conv_finish == 1'b1)
+                    begin
+                        conv_en <= 1'b0;
+                        vgg16_finish <= 1'b1;
+                        state <= S_IDLE;
+                    end
+                end
+                S_CONV1_2:
+                begin
+                    if(conv_finish == 1'b1)
+                    begin
+                        conv_en <= 1'b0;
+                        vgg16_finish <= 1'b1;
+                        state <= S_IDLE;
+                    end
+                end
+                S_POOL1:
+                begin
+                    if(pool_finish == 1'b1)
+                    begin
+                        pool_en <= 1'b0;
+                        vgg16_finish <= 1'b1;
+                        state <= S_IDLE;
+                    end
+                end
+                S_CONV2_1:
+                begin
+                    if(conv_finish == 1'b1)
+                    begin
+                        conv_en <= 1'b0;
+                        vgg16_finish <= 1'b1;
+                        state <= S_IDLE;
+                    end
+                end
+                S_CONV2_2:
+                begin
+                    if(conv_finish == 1'b1)
+                    begin
+                        conv_en <= 1'b0;
+                        vgg16_finish <= 1'b1;
+                        state <= S_IDLE;
+                    end
+                end
+                S_POOL2:
+                begin
+                    if(pool_finish == 1'b1)
+                    begin
+                        pool_en <= 1'b0;
+                        vgg16_finish <= 1'b1;
+                        state <= S_IDLE;
+                    end
+                end
+                S_CONV3_1:
+                begin
+                    if(conv_finish == 1'b1)
+                    begin
+                        conv_en <= 1'b0;
+                        vgg16_finish <= 1'b1;
+                        state <= S_IDLE;
+                    end
+                end
+                S_CONV3_2:
+                begin
+                    if(conv_finish == 1'b1)
+                    begin
+                        conv_en <= 1'b0;
+                        vgg16_finish <= 1'b1;
+                        state <= S_IDLE;
+                    end
+                end
+                S_CONV3_3:
+                begin
+                    if(conv_finish == 1'b1)
+                    begin
+                        conv_en <= 1'b0;
+                        vgg16_finish <= 1'b1;
+                        state <= S_IDLE;
+                    end
+                end
+                S_POOL3:
+                begin
+                    if(pool_finish == 1'b1)
+                    begin
+                        pool_en <= 1'b0;
+                        vgg16_finish <= 1'b1;
+                        state <= S_IDLE;
+                    end
+                end
+                S_CONV4_1:
+                begin
+                    if(conv_finish == 1'b1)
+                    begin
+                        conv_en <= 1'b0;
+                        vgg16_finish <= 1'b1;
+                        state <= S_IDLE;
+                    end
+                end
+                S_CONV4_2:
+                begin
+                    if(conv_finish == 1'b1)
+                    begin
+                        conv_en <= 1'b0;
+                        vgg16_finish <= 1'b1;
+                        state <= S_IDLE;
+                    end
+                end
+                S_CONV4_3:
+                begin
+                    if(conv_finish == 1'b1)
+                    begin
+                        conv_en <= 1'b0;
+                        vgg16_finish <= 1'b1;
+                        state <= S_IDLE;
+                    end
+                end
+                S_POOL4:
+                begin
+                    if(pool_finish == 1'b1)
+                    begin
+                        pool_en <= 1'b0;
+                        vgg16_finish <= 1'b1;
+                        state <= S_IDLE;
+                    end
+                end
+                S_CONV5_1:
+                begin
+                    if(conv_finish == 1'b1)
+                    begin
+                        conv_en <= 1'b0;
+                        vgg16_finish <= 1'b1;
+                        state <= S_IDLE;
+                    end
+                end
+                S_CONV5_2:
+                begin
+                    if(conv_finish == 1'b1)
+                    begin
+                        conv_en <= 1'b0;
+                        vgg16_finish <= 1'b1;
+                        state <= S_IDLE;
+                    end
+                end
+                S_CONV5_3:
+                begin
+                    if(conv_finish == 1'b1)
+                    begin
+                        conv_en <= 1'b0;
+                        vgg16_finish <= 1'b1;
+                        state <= S_IDLE;
+                    end
+                end
+                S_POOL5:
+                begin
+                    if(pool_finish == 1'b1)
+                    begin
+                        pool_en <= 1'b0;
+                        vgg16_finish <= 1'b1;
+                        state <= S_IDLE;
+                    end
+                end
+                S_FC1:
+                begin
+                    if(fc_finish == 1'b1)
+                    begin
+                        fc_en <= 1'b0;
+                        vgg16_finish <= 1'b1;
+                        state <= S_IDLE;
+                    end
+                end
+                S_FC2:
+                begin
+                    if(fc_finish == 1'b1)
+                    begin
+                        fc_en <= 1'b0;
+                        vgg16_finish <= 1'b1;
+                        state <= S_IDLE;
+                    end
+                end
+                S_FC3:
+                begin
+                    if(fc_finish == 1'b1)
+                    begin
+                        fc_en <= 1'b0;
+                        vgg16_finish <= 1'b1;
+                        state <= S_IDLE;
+                    end
+                end
+                default:
+                begin
+                    state <= S_IDLE;
+                    conv_en <= 1'b0;
+                    pool_en <= 1'b0;
+                    fc_en <= 1'b0;
+                end
+            endcase
+        end
+    end
+    
+    // vgg16_bram
+    always@(posedge clk)
+    begin
+        if(rst == 1'b1)
+        begin
+            vgg16_bram_ena <= 1'b0;
+            vgg16_bram_wea <= 1'b0;
+        end
+        else
+        begin
+            if(state == S_CONV1_1 || state == S_CONV1_2 || 
+               state == S_CONV2_1 || state == S_CONV2_2 || 
+               state == S_CONV3_1 || state == S_CONV3_2 || state == S_CONV3_3 || 
+               state == S_CONV4_1 || state == S_CONV4_2 || state == S_CONV4_3 || 
+               state == S_CONV5_1 || state == S_CONV5_2 || state == S_CONV5_3)
+            begin
+                vgg16_bram_ena = conv_vgg16_bram_ena;
+                vgg16_bram_wea = conv_vgg16_bram_wea;
+                vgg16_bram_addra = conv_vgg16_bram_addra;
+                vgg16_bram_dina = conv_vgg16_bram_dina;
+                conv_vgg16_bram_douta = vgg16_bram_douta;
+            end
+            else if(state == S_POOL1 || state == S_POOL2 || state == S_POOL3 || state == S_POOL4 || state == S_POOL5)
+            begin
+                vgg16_bram_ena = pool_vgg16_bram_ena;
+                vgg16_bram_wea = pool_vgg16_bram_wea;
+                vgg16_bram_addra = pool_vgg16_bram_addra;
+                vgg16_bram_dina = pool_vgg16_bram_dina;
+                pool_vgg16_bram_douta = vgg16_bram_douta;
+            end
+            else if(state == S_FC1 || state == S_FC2 || state == S_FC3)
+            begin
+                vgg16_bram_ena = fc_vgg16_bram_ena;
+                vgg16_bram_wea = fc_vgg16_bram_wea;
+                vgg16_bram_addra = fc_vgg16_bram_addra;
+                vgg16_bram_dina = fc_vgg16_bram_dina;
+                fc_vgg16_bram_douta = vgg16_bram_douta;
+            end
+            else
+            begin
+                vgg16_bram_ena <= 1'b0;
+                vgg16_bram_wea <= 1'b0;
+            end
+        end
+    end
+    
+endmodule