Add Repo: Frogwells_fpga_design (part 2)

Frogwells_fpga_design/基于FPGA、DDR3和USB2.0的图像采集系统/debug/ddr_test/rtl/traffic_gen/afifo.v

@@ -0,0 +1,266 @@
+//*****************************************************************************
+// (c) Copyright 2008-2009 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+//*****************************************************************************
+//   ____  ____
+//  /   /\/   /
+// /___/  \  /    Vendor: Xilinx
+// \   \   \/     Version: %version
+//  \   \         Application: MIG
+//  /   /         Filename: afifo.v
+// /___/   /\     Date Last Modified: $Date: 2011/06/02 07:16:32 $
+// \   \  /  \    Date Created: Oct 21 2008
+//  \___\/\___\
+//
+//Device: Spartan6
+//Design Name: DDR/DDR2/DDR3/LPDDR 
+//Purpose:  A generic synchronous fifo.
+//Reference:
+//Revision History:
+
+//*****************************************************************************
+
+`timescale 1ps/1ps
+
+module afifo #
+(
+ parameter TCQ           = 100,
+ parameter DSIZE = 32,
+ parameter FIFO_DEPTH = 16,
+ parameter ASIZE = 4,
+ parameter SYNC = 1   // only has always '1' logic.
+)
+(
+input              wr_clk, 
+input              rst,
+input              wr_en,
+input [DSIZE-1:0]  wr_data,
+input              rd_en, 
+input              rd_clk, 
+output [DSIZE-1:0] rd_data,
+output reg         full,
+output reg         empty,
+output reg         almost_full
+);
+
+// memory array
+reg [DSIZE-1:0] mem [0:FIFO_DEPTH-1];
+
+//Read Capture Logic
+// if Sync = 1, then no need to remove metastability logic because wrclk = rdclk
+reg [ASIZE:0] rd_gray_nxt;
+reg [ASIZE:0]    rd_gray;
+reg [ASIZE:0]    rd_capture_ptr;
+reg [ASIZE:0]    pre_rd_capture_gray_ptr;
+reg [ASIZE:0]    rd_capture_gray_ptr;
+reg [ASIZE:0]    wr_gray;
+reg [ASIZE:0] wr_gray_nxt;
+
+reg [ASIZE:0] wr_capture_ptr;
+reg [ASIZE:0] pre_wr_capture_gray_ptr;
+reg [ASIZE:0] wr_capture_gray_ptr;
+wire [ASIZE:0] buf_avail;
+wire [ASIZE:0] buf_filled;
+wire [ASIZE-1:0] wr_addr, rd_addr;
+
+reg [ASIZE:0]   wr_ptr, rd_ptr;
+integer i,j,k;
+
+
+// for design that use the same clock for both read and write
+generate
+if (SYNC == 1) begin: RDSYNC
+   always @ (rd_ptr)
+     rd_capture_ptr = rd_ptr;
+end
+endgenerate
+
+
+
+//capture the wr_gray_pointers to rd_clk domains and convert the gray pointers to binary pointers 
+// before do comparison.
+
+
+  
+// if Sync = 1, then no need to remove metastability logic because wrclk = rdclk
+generate
+if (SYNC == 1) begin: WRSYNC
+always @ (wr_ptr)
+    wr_capture_ptr = wr_ptr;
+end
+endgenerate
+
+// dualport ram 
+// Memory (RAM) that holds the contents of the FIFO
+
+
+assign wr_addr = wr_ptr;
+assign rd_data = mem[rd_addr];
+always @(posedge wr_clk)
+begin
+if (wr_en && !full)
+  mem[wr_addr] <= #TCQ wr_data;
+
+end
+
+
+// Read Side Logic
+
+
+assign rd_addr = rd_ptr[ASIZE-1:0];
+assign rd_strobe = rd_en && !empty;
+
+integer n;
+reg [ASIZE:0] rd_ptr_tmp;
+    // change the binary pointer to gray pointer
+always @ (rd_ptr)
+begin
+//  rd_gray_nxt[ASIZE] = rd_ptr_tmp[ASIZE];
+//  for (n=0; n < ASIZE; n=n+1) 
+//       rd_gray_nxt[n] = rd_ptr_tmp[n] ^ rd_ptr_tmp[n+1];
+
+  rd_gray_nxt[ASIZE] = rd_ptr[ASIZE];
+  for (n=0; n < ASIZE; n=n+1) 
+       rd_gray_nxt[n] = rd_ptr[n] ^ rd_ptr[n+1];
+
+    
+    
+end       
+
+
+always @(posedge rd_clk)
+begin
+if (rst)
+   begin
+        rd_ptr <= #TCQ 'b0;
+        rd_gray <= #TCQ 'b0;
+   end
+else begin
+    if (rd_strobe)
+        rd_ptr <= #TCQ rd_ptr + 1;
+        
+    rd_ptr_tmp <= #TCQ rd_ptr;
+        
+    // change the binary pointer to gray pointer
+    rd_gray <= #TCQ rd_gray_nxt;
+end
+
+end
+
+//generate empty signal
+assign buf_filled = wr_capture_ptr - rd_ptr;
+               
+always @ (posedge rd_clk )
+begin
+   if (rst)
+        empty <= #TCQ 1'b1;
+   else if ((buf_filled == 0) || (buf_filled == 1 && rd_strobe))
+        empty <= #TCQ 1'b1;
+   else
+        empty <= #TCQ 1'b0;
+end        
+
+
+// write side logic;
+
+reg [ASIZE:0] wbin;
+wire [ASIZE:0] wgraynext, wbinnext;
+
+
+
+always @(posedge rd_clk)
+begin
+if (rst)
+   begin
+        wr_ptr <= #TCQ 'b0;
+        wr_gray <= #TCQ 'b0;
+   end
+else begin
+    if (wr_en)
+        wr_ptr <= #TCQ wr_ptr + 1;
+        
+    // change the binary pointer to gray pointer
+    wr_gray <= #TCQ wr_gray_nxt;
+end
+
+end
+
+
+// change the write pointer to gray pointer
+always @ (wr_ptr)
+begin
+    wr_gray_nxt[ASIZE] = wr_ptr[ASIZE];
+    for (n=0; n < ASIZE; n=n+1)
+       wr_gray_nxt[n] = wr_ptr[n] ^ wr_ptr[n+1];
+end       
+// calculate how many buf still available
+assign buf_avail = (rd_capture_ptr + FIFO_DEPTH) - wr_ptr;
+
+always @ (posedge wr_clk )
+begin
+   if (rst) 
+        full <= #TCQ 1'b0;
+   else if ((buf_avail == 0) || (buf_avail == 1 && wr_en))
+        full <= #TCQ 1'b1;
+   else
+        full <= #TCQ 1'b0;
+end        
+
+
+always @ (posedge wr_clk )
+begin
+   if (rst) 
+        almost_full <= #TCQ 1'b0;
+   else if ((buf_avail == FIFO_DEPTH - 2 ) || ((buf_avail == FIFO_DEPTH -3) && wr_en))
+        almost_full <= #TCQ 1'b1;
+   else
+        almost_full <= #TCQ 1'b0;
+end        
+
+endmodule
+
+

Frogwells_fpga_design/基于FPGA、DDR3和USB2.0的图像采集系统/debug/ddr_test/rtl/traffic_gen/cmd_gen.v

@@ -0,0 +1,941 @@
+//*****************************************************************************
+// (c) Copyright 2008-2009 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+//*****************************************************************************
+//   ____  ____
+//  /   /\/   /
+// /___/  \  /    Vendor: Xilinx
+// \   \   \/     Version: %version
+//  \   \         Application: MIG
+//  /   /         Filename: cmd_gen.v
+// /___/   /\     Date Last Modified: $Date: 2011/05/27 15:50:26 $
+// \   \  /  \    Date Created: Oct 21 2008
+//  \___\/\___\
+//
+//Device: Spartan6
+//Design Name: DDR/DDR2/DDR3/LPDDR
+//Purpose:  This module genreates different type of commands, address,
+//          burst_length to mcb_flow_control module.
+//Reference:
+//Revision History:
+//                  Nov14 2008. Added constraints  for generating PRBS_BL when
+//                         generated address is too close to end of address space.
+//                         The BL will be force to 1 to avoid across other port's space.
+//                  April 2 2009 Fixed Sequential Address Circuit to avoide generate any address
+//                               beyond the allowed address range.		  
+//                  Oct 22 2009  Fixed BRAM interface.
+//                               Fixed run_traffic stop and go problem.
+//                               Merged V6 and SP6 specific requirements.
+//								 Modified syntax for VHDL Formality comparison.
+//*****************************************************************************
+
+`timescale 1ps/1ps
+
+`define RD              3'b001;
+`define RDP             3'b011;
+`define WR              3'b000;
+`define WRP             3'b010;
+`define REFRESH         3'b100;
+
+
+module cmd_gen #
+  (
+   parameter TCQ           = 100,
+
+   parameter FAMILY = "SPARTAN6",
+   parameter MEM_BURST_LEN = 8,
+   parameter PORT_MODE = "BI_MODE",
+   parameter NUM_DQ_PINS   = 8,
+   parameter DATA_PATTERN  = "DGEN_ALL", // "DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
+   parameter CMD_PATTERN  = "CGEN_ALL",    // "CGEN_RPBS","CGEN_FIXED",  "CGEN_BRAM", "CGEN_SEQUENTIAL", "CGEN_ALL",
+   parameter ADDR_WIDTH    = 30,
+   parameter DWIDTH        = 32,
+   parameter PIPE_STAGES   = 0,
+   parameter MEM_COL_WIDTH = 10,       // memory column width
+   parameter PRBS_EADDR_MASK_POS = 32'hFFFFD000,
+   parameter PRBS_SADDR_MASK_POS =  32'h00002000,
+   parameter PRBS_EADDR = 32'h00002000,
+   parameter PRBS_SADDR  = 32'h00002000
+   )
+  (
+   input           clk_i,
+   input [9:0]          rst_i,
+   input           run_traffic_i,
+  // runtime parameter
+  input [6:0]               rd_buff_avail_i,
+  input                     force_wrcmd_gen_i,
+   input [31:0]             start_addr_i,   // define the start of address
+   input [31:0]             end_addr_i,
+   input [31:0]             cmd_seed_i,    // same seed apply to all addr_prbs_gen, bl_prbs_gen, instr_prbs_gen
+   input [31:0]             data_seed_i,
+   input                    load_seed_i,   //
+   // upper layer inputs to determine the command bus and data pattern
+   // internal traffic generator initialize the memory with
+   input [2:0]              addr_mode_i,  // "00" = bram; takes the address from bram output
+                                          // "01" = fixed address from the fixed_addr input
+                                          // "10" = psuedo ramdom pattern; generated from internal 64 bit LFSR
+                                          // "11" = sequential
+
+   input [3:0]              data_mode_i,  // 4'b0010:address as data
+                                          // 4'b0011:DGEN_HAMMER
+                                          // 4'b0100:DGEN_NEIGHBOUR
+                                          // 4'b0101:DGEN_WALKING1
+                                          // 4'b0110:DGEN_WALKING0
+                                          // 4'b0111:PRBS_DATA
+
+  // for each instr_mode, traffic gen fill up with a predetermined pattern before starting the instr_pattern that defined
+  // in the instr_mode input. The runtime mode will be automatically loaded inside when it is in
+   input [3:0]              instr_mode_i, // "0000" = bram; takes instruction from bram output
+                                          // "0001" = fixed instr from fixed instr input
+                                          // "0010" = R/W
+                                          // "0011" = RP/WP
+                                          // "0100" = R/RP/W/WP
+                                          // "0101" = R/RP/W/WP/REF
+                                          // "0110" = PRBS
+
+
+   input [1:0]              bl_mode_i,  // "00" = bram;   takes the burst length from bram output
+                                        // "01" = fixed , takes the burst length from the fixed_bl input
+                                        // "10" = psuedo ramdom pattern; generated from internal 16 bit LFSR
+
+   input                    mode_load_i,
+
+   // fixed pattern inputs interface
+   input [5:0]              fixed_bl_i,      // range from 1 to 64
+   input [2:0]              fixed_instr_i,   //RD              3'b001
+                                            //RDP             3'b011
+                                            //WR              3'b000
+                                            //WRP             3'b010
+                                            //REFRESH         3'b100
+   input [31:0]             fixed_addr_i, // only upper 30 bits will be used
+   // BRAM FIFO input
+   input [31:0]             bram_addr_i,  //
+   input [2:0]              bram_instr_i,
+   input [5:0]              bram_bl_i,
+   input                    bram_valid_i,
+   output                   bram_rdy_o,
+
+   input                    reading_rd_data_i,
+   // mcb_flow_control interface
+   input           rdy_i,
+
+   output  [31:0]  addr_o,     // generated address
+   output  [2:0]   instr_o,    // generated instruction
+   output  [5:0]   bl_o,       // generated instruction
+//   output reg [31:0]  m_addr_o,
+   output          cmd_o_vld      // valid commands when asserted
+  );
+
+   localparam PRBS_ADDR_WIDTH = 32;
+   localparam INSTR_PRBS_WIDTH = 16;
+   localparam BL_PRBS_WIDTH    = 16;
+
+localparam BRAM_DATAL_MODE       =    4'b0000;
+localparam FIXED_DATA_MODE       =    4'b0001;
+localparam ADDR_DATA_MODE        =    4'b0010;
+localparam HAMMER_DATA_MODE      =    4'b0011;
+localparam NEIGHBOR_DATA_MODE    =    4'b0100;
+localparam WALKING1_DATA_MODE    =    4'b0101;
+localparam WALKING0_DATA_MODE    =    4'b0110;
+localparam PRBS_DATA_MODE        =    4'b0111;
+
+reg [10:0] INC_COUNTS;
+reg [2:0]  addr_mode_reg;
+reg [1:0]  bl_mode_reg;
+
+reg [31:0] addr_counts;
+reg [31:0] addr_counts_next_r;
+
+wire  [14:0]  prbs_bl;
+reg [2:0] instr_out;
+wire [14:0] prbs_instr_a;
+wire [14:0] prbs_instr_b;
+
+reg  [5:0]   prbs_brlen;
+
+wire [31:0] prbs_addr;
+wire [31:0] seq_addr;
+wire [31:0] fixed_addr;
+reg [31:0] addr_out ;
+reg [5:0]  bl_out;
+reg [5:0] bl_out_reg;
+reg mode_load_d1;
+reg mode_load_d2;
+reg mode_load_pulse;
+wire [41:0] pipe_data_o;
+wire     cmd_clk_en;
+
+wire     pipe_out_vld;
+reg [15:0] end_addr_range;
+
+reg force_bl1;
+reg A0_G_E0;
+reg A1_G_E1;
+reg A2_G_E2;
+reg A3_G_E3;
+reg AC3_G_E3;
+reg AC2_G_E2;
+reg AC1_G_E1;
+reg bl_out_clk_en;
+reg [41:0] pipe_data_in;
+reg instr_vld;
+reg bl_out_vld;
+reg pipe_data_in_vld;
+reg gen_addr_larger ;
+    reg [6:0] buf_avail_r;
+    reg [6:0] rd_data_received_counts;
+    reg [6:0] rd_data_counts_asked;
+
+    reg [15:0] rd_data_received_counts_total;
+reg instr_vld_dly1;
+reg first_load_pulse;
+reg mem_init_done;
+reg refresh_cmd_en ;
+reg [9:0] refresh_timer;
+reg       refresh_prbs;
+reg       cmd_vld;
+reg run_traffic_r;
+reg run_traffic_pulse;
+always @ (posedge clk_i)
+begin
+     run_traffic_r <= #TCQ run_traffic_i;
+     if (  run_traffic_i &&   ~run_traffic_r )
+          run_traffic_pulse <= #TCQ 1'b1;
+     else
+          run_traffic_pulse <= #TCQ 1'b0;
+end     
+     
+
+// commands go through pipeline inserters
+assign addr_o       = pipe_data_o[31:0];
+assign instr_o      = pipe_data_o[34:32];
+assign bl_o         = pipe_data_o[40:35];
+
+
+assign cmd_o_vld    = pipe_data_o[41] & run_traffic_r;
+assign pipe_out_vld = pipe_data_o[41] & run_traffic_r;
+
+
+assign pipe_data_o = pipe_data_in;
+
+always @(posedge clk_i) begin                    
+
+     instr_vld        <=  #TCQ  (cmd_clk_en | (mode_load_pulse & first_load_pulse));
+     bl_out_clk_en    <=  #TCQ  (cmd_clk_en | (mode_load_pulse & first_load_pulse));
+     bl_out_vld       <=  #TCQ  bl_out_clk_en;
+     pipe_data_in_vld <=  #TCQ  instr_vld;
+ end
+
+always @ (posedge clk_i) begin
+ if (rst_i[0])
+    first_load_pulse <= #TCQ 1'b1;
+ else if (mode_load_pulse)
+    first_load_pulse <= #TCQ 1'b0;
+ else
+    first_load_pulse <= #TCQ first_load_pulse;
+ end
+ 
+generate
+if (CMD_PATTERN == "CGEN_BRAM")  begin: cv1
+
+always @(posedge clk_i) begin 
+    cmd_vld          <=  #TCQ (cmd_clk_en ); 
+                   
+end
+end endgenerate
+
+
+generate
+if (CMD_PATTERN != "CGEN_BRAM")  begin: cv2
+
+always @(posedge clk_i) begin 
+    cmd_vld          <=  #TCQ (cmd_clk_en | (mode_load_pulse & first_load_pulse )); 
+                   
+end
+end endgenerate
+
+ 
+assign cmd_clk_en =  ( rdy_i & pipe_out_vld & run_traffic_i ||  mode_load_pulse && (CMD_PATTERN == "CGEN_BRAM"));
+ 
+
+ 
+integer i;
+generate
+if (FAMILY == "SPARTAN6")  begin: pipe_in_s6
+    always @ (posedge clk_i) begin
+    if (rst_i[0])
+       pipe_data_in[31:0] <= #TCQ    start_addr_i;
+    else if (instr_vld)
+         if (gen_addr_larger && (addr_mode_reg == 3'b100 || addr_mode_reg == 3'b010)) 
+            if (DWIDTH == 32)
+              pipe_data_in[31:0] <= #TCQ  {end_addr_i[31:8],8'h0};
+            else if (DWIDTH == 64)
+              pipe_data_in[31:0] <= #TCQ  {end_addr_i[31:9],9'h0};
+            else
+              pipe_data_in[31:0] <= #TCQ  {end_addr_i[31:10],10'h0};
+            
+         else begin
+             if (DWIDTH == 32)
+              pipe_data_in[31:0] <= #TCQ    {addr_out[31:2],2'b00} ;
+             else if (DWIDTH == 64)
+              pipe_data_in[31:0] <= #TCQ    {addr_out[31:3],3'b000} ;
+             else if (DWIDTH == 128)
+              pipe_data_in[31:0] <= #TCQ    {addr_out[31:4],4'b0000} ;
+             end
+end
+
+end endgenerate
+
+generate
+if (FAMILY == "VIRTEX6")  begin: pipe_in_v6
+    always @ (posedge clk_i) begin
+    if (rst_i[1])
+       pipe_data_in[31:0] <= #TCQ    start_addr_i;
+    else if (instr_vld)
+       // address
+      if (gen_addr_larger && (addr_mode_reg == 3'b100 || addr_mode_reg == 3'b010)) //(AC3_G_E3 && AC2_G_E2 && AC1_G_E1  )
+              pipe_data_in[31:0] <= #TCQ  {end_addr_i[31:8],8'h0};
+      else if ((NUM_DQ_PINS >= 128) && (NUM_DQ_PINS <=  144))
+      begin
+         if (MEM_BURST_LEN == 8)
+            pipe_data_in[31:0] <= #TCQ    {addr_out[31:7], 7'b0000000};
+         else      
+            pipe_data_in[31:0] <= #TCQ    {addr_out[31:6], 6'b000000};
+       end
+            
+      else if ((NUM_DQ_PINS >= 64) && (NUM_DQ_PINS < 128))
+            begin
+
+         if (MEM_BURST_LEN == 8)
+            pipe_data_in[31:0] <= #TCQ    {addr_out[31:6], 6'b000000};
+         else
+         pipe_data_in[31:0] <= #TCQ    {addr_out[31:5], 5'b00000};
+       end
+         
+      else if ((NUM_DQ_PINS == 32) || (NUM_DQ_PINS == 40) || (NUM_DQ_PINS == 48) || (NUM_DQ_PINS == 56))
+            begin
+
+         if (MEM_BURST_LEN == 8)     
+            pipe_data_in[31:0] <= #TCQ    {addr_out[31:5], 5'b00000};
+         else
+         pipe_data_in[31:0] <= #TCQ    {addr_out[31:4], 4'b0000};
+       end
+         
+      else if ((NUM_DQ_PINS == 16) || (NUM_DQ_PINS == 24))
+         if (MEM_BURST_LEN == 8)     
+            pipe_data_in[31:0] <= #TCQ    {addr_out[31:4], 4'b0000};
+         else
+         pipe_data_in[31:0] <= #TCQ    {addr_out[31:3], 3'b000};
+         
+      else if ((NUM_DQ_PINS == 8) )
+         if (MEM_BURST_LEN == 8)             
+            pipe_data_in[31:0] <= #TCQ    {addr_out[31:3], 3'b000};
+         else
+         pipe_data_in[31:0] <= #TCQ    {addr_out[31:2], 2'b00};
+         
+end
+
+end endgenerate
+
+
+//generate
+//if (FAMILY == "VIRTEX6")  begin: pipe_m_addr_o
+//    always @ (posedge clk_i) begin
+//    if (rst_i[1])
+//       m_addr_o[31:0] <= #TCQ    start_addr_i;
+//    else if (instr_vld)
+//      if (gen_addr_larger && (addr_mode_reg == 3'b100 || addr_mode_reg == 3'b010)) //(AC3_G_E3 && AC2_G_E2 && AC1_G_E1  )
+//              m_addr_o[31:0] <= #TCQ  {end_addr_i[31:8],8'h0};
+//      else if ((NUM_DQ_PINS >= 128 && NUM_DQ_PINS < 256))  
+//         m_addr_o <= #TCQ  {addr_out[31:6], 6'b00000} ;
+//              
+//      else if ((NUM_DQ_PINS >= 64 && NUM_DQ_PINS < 128))  
+//         m_addr_o <= #TCQ  {addr_out[31:5], 5'b00000} ;
+//         
+//      else if ((NUM_DQ_PINS == 32) || (NUM_DQ_PINS == 40) || (NUM_DQ_PINS == 48) || (NUM_DQ_PINS == 56))
+//         m_addr_o[31:0] <= #TCQ    {addr_out[31:4], 4'b0000};
+//      else if ((NUM_DQ_PINS == 16) || (NUM_DQ_PINS == 24))
+//         m_addr_o[31:0] <= #TCQ    {addr_out[31:3], 3'b000};
+//      else if ((NUM_DQ_PINS == 8) )
+//         m_addr_o[31:0] <= #TCQ    {addr_out[31:2], 2'b00};
+//end
+//
+//end endgenerate
+reg force_wrcmd_gen;
+   always @ (posedge clk_i) begin
+    if (rst_i[0])
+         force_wrcmd_gen <= #TCQ  1'b0;
+    else if (buf_avail_r == 63)
+         force_wrcmd_gen <= #TCQ  1'b0;
+    else if (instr_vld_dly1 && pipe_data_in[32]== 1 && pipe_data_in[41:35] > 16)
+         force_wrcmd_gen <= #TCQ  1'b1;
+    end
+
+reg [3:0]instr_mode_reg;
+ always @ (posedge clk_i)
+ begin
+      instr_mode_reg <= #TCQ  instr_mode_i;
+ end 
+reg force_smallvalue;
+ always @ (posedge clk_i)
+ begin
+    if (rst_i[2]) begin
+       pipe_data_in[40:32] <= #TCQ    'b0;
+       force_smallvalue <= #TCQ  1'b0;
+       end
+    else if (instr_vld) begin
+      if (instr_mode_reg == 0) begin
+              pipe_data_in[34:32] <= #TCQ    instr_out;
+              end
+      else if (instr_out[2]) begin
+              pipe_data_in[34:32] <= #TCQ    3'b100;
+              end
+        //
+      else if ( FAMILY == "SPARTAN6" && PORT_MODE == "RD_MODE")
+      begin
+            pipe_data_in[34:32] <= #TCQ  {instr_out[2:1],1'b1};
+              end
+            
+      else if ((force_wrcmd_gen || buf_avail_r <=  15) && FAMILY == "SPARTAN6" &&  PORT_MODE != "RD_MODE")
+      begin
+            pipe_data_in[34:32] <= #TCQ    {instr_out[2],2'b00};
+              end
+      else begin
+             pipe_data_in[34:32] <= #TCQ    instr_out; 
+              end
+
+   //********* condition the generated bl value except if TG is programmed for BRAM interface'
+   // if the generated address is close to end address range, the bl_out will be altered to 1.
+     if (bl_mode_i[1:0] == 2'b00)                                        // if programmed BRAM interface
+          pipe_data_in[40:35] <=  #TCQ   bl_out;
+     else if (FAMILY == "VIRTEX6")
+              pipe_data_in[40:35] <=  #TCQ   bl_out;
+     else if (force_bl1 && (bl_mode_reg == 2'b10 ) && FAMILY == "SPARTAN6") //PRBS_BL
+
+      pipe_data_in[40:35] <=  #TCQ   6'b000001;
+     else if ((buf_avail_r[5:0]  >= 6'b111100 && buf_avail_r[6] == 1'b0) && pipe_data_in[32] == 1'b1 && FAMILY == "SPARTAN6")         //read instructon
+
+
+       begin
+        if (bl_mode_reg == 2'b10)
+            force_smallvalue    <= #TCQ  ~force_smallvalue;
+      
+        if ((buf_avail_r[6] && bl_mode_reg == 2'b10))
+
+
+             pipe_data_in[40:35] <= #TCQ    {2'b0,bl_out[3:1],1'b1};
+        else
+            pipe_data_in[40:35] <=   #TCQ  bl_out;
+        end
+   else if (buf_avail_r  < 64 && rd_buff_avail_i >= 0 && instr_out[0] == 1'b1 && (bl_mode_reg == 2'b10 )) 
+         if (FAMILY == "SPARTAN6")
+         pipe_data_in[40:35] <=  #TCQ   {2'b0,bl_out[3:0] + 1};
+         else
+            pipe_data_in[40:35] <=   #TCQ  bl_out;
+
+    end  //else instr_vld
+ end // always
+
+always @ (posedge clk_i) 
+begin
+     if (rst_i[2])
+        pipe_data_in[41] <=  #TCQ   'b0;
+     else if (cmd_vld)
+        pipe_data_in[41] <=  #TCQ   instr_vld;//instr_vld;
+     else if (rdy_i && pipe_out_vld)
+        pipe_data_in[41] <=  #TCQ   1'b0;
+ end
+
+ always @ (posedge clk_i)
+    instr_vld_dly1  <=  #TCQ instr_vld;
+
+always @ (posedge clk_i) begin
+ if (rst_i[0]) begin
+    rd_data_counts_asked <= #TCQ  'b0;
+  end else if (instr_vld_dly1 && pipe_data_in[32]== 1) begin
+    if (pipe_data_in[40:35] == 0)
+       rd_data_counts_asked <=  #TCQ rd_data_counts_asked + (64) ;
+    else
+       rd_data_counts_asked <=  #TCQ rd_data_counts_asked + (pipe_data_in[40:35]) ;
+
+    end
+ end
+
+always @ (posedge clk_i) begin
+ if (rst_i[0]) begin
+     rd_data_received_counts <= #TCQ  'b0;
+     rd_data_received_counts_total <= #TCQ  'b0;
+  end else if(reading_rd_data_i) begin
+     rd_data_received_counts <= #TCQ  rd_data_received_counts + 1;
+     rd_data_received_counts_total <= #TCQ  rd_data_received_counts_total + 1;
+     end
+ end
+
+ // calculate how many buf still available
+ always @ (posedge clk_i)
+     buf_avail_r <= #TCQ  (rd_data_received_counts + 64) - rd_data_counts_asked;
+
+localparam BRAM_ADDR       = 2'b00;
+localparam FIXED_ADDR      = 2'b01;
+localparam PRBS_ADDR       = 2'b10;
+localparam SEQUENTIAL_ADDR = 2'b11;
+
+// registered the mode settings
+always @ (posedge clk_i) begin
+   if (rst_i[3])
+        if (CMD_PATTERN == "CGEN_BRAM")
+         addr_mode_reg  <= #TCQ    3'b000;
+        else                                     
+         addr_mode_reg  <= #TCQ    3'b011;
+   else if (mode_load_pulse)
+         addr_mode_reg  <= #TCQ    addr_mode_i;
+end
+
+always @ (posedge clk_i) begin
+   if (mode_load_pulse) begin
+        bl_mode_reg    <= #TCQ    bl_mode_i ;
+   end
+   mode_load_d1         <= #TCQ    mode_load_i;
+   mode_load_d2         <= #TCQ    mode_load_d1;
+end
+
+always @ (posedge clk_i)
+     mode_load_pulse <= #TCQ  mode_load_d1 & ~mode_load_d2;
+
+// MUX the addr pattern out depending on the addr_mode setting
+
+// "000" = bram; takes the address from bram output
+// "001" = fixed address from the fixed_addr input
+// "010" = psuedo ramdom pattern; generated from internal 64 bit LFSR
+// "011" = sequential
+// "100" = mode that used for prbs addr , prbs bl and prbs data
+//always @(addr_mode_reg,prbs_addr,seq_addr,fixed_addr,bram_addr_i,data_mode_i)
+always @ (posedge clk_i) begin
+if (rst_i[3])
+  addr_out <= #TCQ    start_addr_i;
+else
+   case({addr_mode_reg})
+         3'b000: addr_out <= #TCQ    bram_addr_i;
+         3'b001: addr_out <= #TCQ    fixed_addr;
+         3'b010: addr_out <= #TCQ    prbs_addr;
+         3'b011: addr_out <= #TCQ    {2'b0,seq_addr[29:0]};
+         3'b100: addr_out <= #TCQ    {2'b00,seq_addr[6:2],seq_addr[23:0]};//{prbs_addr[31:6],6'b000000} ;
+         3'b101: addr_out <= #TCQ    {prbs_addr[31:20],seq_addr[19:0]} ;
+
+         default : addr_out <= #TCQ    'b0;
+   endcase
+end
+
+//  ADDR PRBS GENERATION
+generate
+if (CMD_PATTERN == "CGEN_PRBS" || CMD_PATTERN == "CGEN_ALL" ) begin: gen_prbs_addr
+cmd_prbs_gen #
+  ( 
+    .TCQ               (TCQ),
+    .FAMILY      (FAMILY),
+    .ADDR_WIDTH          (32),
+    .DWIDTH     (DWIDTH),
+    .PRBS_WIDTH (32),
+    .SEED_WIDTH (32),
+    .PRBS_EADDR_MASK_POS          (PRBS_EADDR_MASK_POS ),
+    .PRBS_SADDR_MASK_POS           (PRBS_SADDR_MASK_POS  ),
+    .PRBS_EADDR         (PRBS_EADDR),
+    .PRBS_SADDR          (PRBS_SADDR )
+   )
+   addr_prbs_gen
+  (
+   .clk_i            (clk_i),
+   .clk_en           (cmd_clk_en),
+   .prbs_seed_init   (mode_load_pulse),
+   .prbs_seed_i      (cmd_seed_i[31:0]),
+   .prbs_o           (prbs_addr)
+  );
+end
+endgenerate
+
+always @ (posedge clk_i) begin
+if (addr_out[31:8] >= end_addr_i[31:8])
+    gen_addr_larger <=     1'b1;
+else
+    gen_addr_larger <=     1'b0;
+end
+
+generate
+if (FAMILY == "SPARTAN6" ) begin : INC_COUNTS_S
+always @ (posedge clk_i)
+if (mem_init_done)
+    INC_COUNTS <= #TCQ  (DWIDTH/8)*(bl_out_reg);
+else  begin
+    if (fixed_bl_i == 0)
+       INC_COUNTS <= #TCQ  (DWIDTH/8)*(64);
+    else
+       INC_COUNTS <= #TCQ  (DWIDTH/8)*(fixed_bl_i);
+    end
+end
+endgenerate
+//converting string to integer
+//localparam MEM_BURST_INT = (MEM_BURST_LEN == "8")? 8 : 4;
+localparam MEM_BURST_INT = MEM_BURST_LEN ;
+
+
+generate
+if (FAMILY == "VIRTEX6" ) begin : INC_COUNTS_V
+    always @ (posedge clk_i) begin
+    
+if ( (NUM_DQ_PINS >= 128 && NUM_DQ_PINS <= 144))       //256
+     INC_COUNTS <= #TCQ  64 * (MEM_BURST_INT/4);
+    
+else if ( (NUM_DQ_PINS >= 64 && NUM_DQ_PINS < 128))       //256
+     INC_COUNTS <= #TCQ  32 * (MEM_BURST_INT/4);
+else if ((NUM_DQ_PINS >= 32) && (NUM_DQ_PINS < 64))   //128
+     INC_COUNTS <= #TCQ  16 * (MEM_BURST_INT/4)   ;
+else if ((NUM_DQ_PINS == 16) || (NUM_DQ_PINS == 24))  //64
+     INC_COUNTS <= #TCQ  8 * (MEM_BURST_INT/4);
+else if ((NUM_DQ_PINS == 8) )
+     INC_COUNTS <= #TCQ  4 * (MEM_BURST_INT/4);
+end
+end
+endgenerate
+
+generate
+// Sequential Address pattern
+// It is generated when rdy_i is valid and write command is valid and bl_cmd is valid.
+reg [31:0] end_addr_r;
+
+always @ (posedge clk_i) begin
+     end_addr_r <= #TCQ  end_addr_i - DWIDTH/8*fixed_bl_i +1;
+end
+
+always @ (posedge clk_i) begin
+if (addr_out[31:24] >= end_addr_r[31:24])
+    AC3_G_E3 <= #TCQ    1'b1;
+else
+    AC3_G_E3 <= #TCQ    1'b0;
+
+if (addr_out[23:16] >= end_addr_r[23:16])
+    AC2_G_E2 <= #TCQ    1'b1;
+else
+    AC2_G_E2 <= #TCQ    1'b0;
+
+if (addr_out[15:8] >= end_addr_r[15:8])
+    AC1_G_E1 <= #TCQ    1'b1;
+else
+    AC1_G_E1 <= #TCQ    1'b0;
+end
+
+//if (CMD_PATTERN == "CGEN_SEQUENTIAL" || CMD_PATTERN == "CGEN_ALL" ) begin : seq_addr_gen
+    assign seq_addr = addr_counts;
+
+reg mode_load_pulse_r1;
+
+always @ (posedge clk_i)
+begin
+    mode_load_pulse_r1 <= #TCQ  mode_load_pulse;
+
+end
+
+always @ (posedge clk_i)
+    end_addr_range <= #TCQ    end_addr_i[15:0] - (DWIDTH/8 *bl_out_reg) + 1   ;
+
+always @ (posedge clk_i)
+    addr_counts_next_r <= #TCQ    addr_counts  + INC_COUNTS   ;
+
+reg cmd_clk_en_r;
+always @ (posedge clk_i)
+  cmd_clk_en_r <= #TCQ  cmd_clk_en;
+always @ (posedge clk_i) begin
+   if (rst_i[4]) begin
+        addr_counts <= #TCQ    start_addr_i;
+        mem_init_done <= #TCQ  1'b0;
+  end else if (cmd_clk_en_r || mode_load_pulse_r1)
+    if(addr_counts_next_r>= end_addr_i) begin
+                addr_counts <= #TCQ    start_addr_i;
+                mem_init_done <= #TCQ  1'b1;
+    end else if(addr_counts < end_addr_r)  // address counts get incremented by burst_length and port size each wr command generated
+                addr_counts <= #TCQ    addr_counts + INC_COUNTS;
+end
+
+ // end begin
+//end
+endgenerate
+
+generate
+// Fixed Address pattern
+if (CMD_PATTERN == "CGEN_FIXED" || CMD_PATTERN == "CGEN_ALL" ) begin : fixed_addr_gen
+    assign fixed_addr = (DWIDTH == 32)?  {fixed_addr_i[31:2],2'b0} :
+                        (DWIDTH == 64)?  {fixed_addr_i[31:3],3'b0}:
+                        (DWIDTH <= 128)? {fixed_addr_i[31:4],4'b0}:
+                        (DWIDTH <= 256)? {fixed_addr_i[31:5],5'b0}:
+                                         {fixed_addr_i[31:6],6'b0};
+  end
+endgenerate
+
+generate
+// BRAM Address pattern
+if (CMD_PATTERN == "CGEN_BRAM" || CMD_PATTERN == "CGEN_ALL" ) begin : bram_addr_gen
+assign bram_rdy_o = run_traffic_i & cmd_clk_en & bram_valid_i | mode_load_pulse;
+end
+endgenerate
+
+///////////////////////////////////////////////////////////////////////////
+//  INSTR COMMAND GENERATION
+
+// tap points are 3,2
+//`define RD              3'b001
+//`define RDP             3'b011
+//`define WR              3'b000
+//`define WRP             3'b010
+//`define REFRESH         3'b100
+// use 14 stages  1 sr16; tap position 1,3,5,14
+
+reg [9:0]force_rd_counts;
+reg force_rd;
+always @ (posedge clk_i) begin
+if (rst_i[4])
+    force_rd_counts <= #TCQ  'b0;
+else if (instr_vld) begin
+    force_rd_counts <= #TCQ  force_rd_counts + 1;
+    end
+end
+
+always @ (posedge clk_i) begin
+if (rst_i[4])
+    force_rd <= #TCQ  1'b0;
+else if (force_rd_counts[3])
+    force_rd <= #TCQ  1'b1;
+else
+    force_rd <= #TCQ  1'b0;
+end
+
+
+// adding refresh timer to limit the amount of issuing refresh command.
+always @ (posedge clk_i) begin
+if (rst_i[4])
+   refresh_timer <= #TCQ  'b0;
+else
+   refresh_timer <= #TCQ  refresh_timer + 1'b1;
+
+end
+
+always @ (posedge clk_i) begin
+if (rst_i[4])
+   refresh_cmd_en <= #TCQ  'b0;
+//else if (refresh_timer >= 12'hff0 && refresh_timer <= 12'hfff)
+else if (refresh_timer == 10'h3ff)
+
+   refresh_cmd_en <= #TCQ  'b1;
+else if (cmd_clk_en && refresh_cmd_en)
+   refresh_cmd_en <= #TCQ  'b0;
+
+end   
+
+always @ (posedge clk_i) begin
+if (FAMILY == "SPARTAN6")
+    refresh_prbs <= #TCQ  prbs_instr_b[3] & refresh_cmd_en;
+else
+    refresh_prbs <= #TCQ  1'b0;
+end    
+  //synthesis translate_off
+always @ (instr_mode_i)
+  if(instr_mode_i  >2 && FAMILY == "VIRTEX6") begin
+   $display("Error ! Not valid instruction mode");
+   $stop;
+   end
+  //synthesis translate_on
+
+always @ (posedge clk_i) begin
+   case(instr_mode_i)
+         0: instr_out <= #TCQ    bram_instr_i;
+         1: instr_out <= #TCQ    fixed_instr_i;
+         2: instr_out <= #TCQ    {2'b00,(prbs_instr_a[0] | force_rd)};
+         3: instr_out <= #TCQ    {2'b0,prbs_instr_a[0]};  //:  WP/RP
+         4: instr_out <= #TCQ    {1'b0,prbs_instr_b[0], prbs_instr_a[0]};  //  W/WP/R/RP.
+         // may be add another PRBS for generating REFRESH
+//         5: instr_out <= #TCQ    {prbs_instr_b[3],prbs_instr_b[0], prbs_instr_a[0]};  // W/WP/R/RP/REFRESH W/WP/R/RP/REFRESH
+         5: instr_out <= #TCQ    {refresh_prbs ,prbs_instr_b[0], prbs_instr_a[0]};  // W/WP/R/RP/REFRESH W/WP/R/RP/REFRESH
+
+
+         default : instr_out <= #TCQ    {2'b00,prbs_instr_a[0]};
+   endcase
+end
+
+generate  // PRBS INSTRUCTION generation
+// use two PRBS generators and tap off 1 bit from each to create more randomness for
+// generating actual read/write commands
+if (CMD_PATTERN == "CGEN_PRBS" || CMD_PATTERN == "CGEN_ALL" ) begin: gen_prbs_instr
+cmd_prbs_gen #
+  (
+    .TCQ               (TCQ),
+    .PRBS_CMD    ("INSTR"),
+    .ADDR_WIDTH  (32),
+    .SEED_WIDTH  (15),
+    .PRBS_WIDTH  (20)
+   )
+   instr_prbs_gen_a
+  (
+   .clk_i              (clk_i),
+   .clk_en             (cmd_clk_en),
+   .prbs_seed_init     (load_seed_i),
+   .prbs_seed_i        (cmd_seed_i[14:0]),
+   .prbs_o             (prbs_instr_a)
+  );
+
+cmd_prbs_gen #
+  (
+    .PRBS_CMD    ("INSTR"),
+    .SEED_WIDTH  (15),
+    .PRBS_WIDTH  (20)
+   )
+   instr_prbs_gen_b
+  (
+   .clk_i              (clk_i),
+   .clk_en             (cmd_clk_en),
+   .prbs_seed_init     (load_seed_i),
+   .prbs_seed_i        (cmd_seed_i[16:2]),
+   .prbs_o             (prbs_instr_b)
+  );
+end
+endgenerate
+
+///////////////////////////////////////////////////////////////////////////////////////////////////////////////
+// BURST LENGTH GENERATION
+// burst length code = user burst length input - 1
+// mcb_flow_control does the minus before sending out to mcb\
+// when filling up the memory, need to make sure bl doesn't go beyound its upper limit boundary
+//assign force_bl1 = (addr_out[31:0] >= (end_addr_i[31:0] - 4*64)) ? 1'b1: 1'b0;
+// for neighbour pattern, need to limit the bl to make sure it is within column size boundary.
+
+// check bl validity
+
+always @ (posedge clk_i) begin
+if (addr_out[31:24] >= end_addr_i[31:24])
+    A3_G_E3 <= #TCQ    1'b1;
+else
+    A3_G_E3 <= #TCQ    1'b0;
+
+if (addr_out[23:16] >= end_addr_i[23:16])
+    A2_G_E2 <= #TCQ    1'b1;
+else
+    A2_G_E2 <= #TCQ    1'b0;
+
+if (addr_out[15:8] >= end_addr_i[15:8])
+    A1_G_E1 <= #TCQ    1'b1;
+else
+    A1_G_E1 <= #TCQ    1'b0;
+
+if (addr_out[7:0] > end_addr_i[7:0] - DWIDTH/8* bl_out + 1)
+    A0_G_E0 <= #TCQ    1'b1;
+else
+    A0_G_E0 <= #TCQ    1'b0;
+end
+
+always @(addr_out,bl_out,end_addr_i,rst_i,buf_avail_r) begin
+    if (rst_i[5])
+        force_bl1 =   1'b0;
+    else if (((addr_out + bl_out* (DWIDTH/8)) >= end_addr_i) || (buf_avail_r  <= 50 && PORT_MODE == "RD_MODE"))
+        force_bl1 =   1'b1;
+    else
+        force_bl1 =   1'b0;
+end
+
+always @(posedge clk_i) begin
+   if (rst_i[6])
+       bl_out_reg <= #TCQ    fixed_bl_i;
+   else if (bl_out_vld)
+       bl_out_reg <= #TCQ    bl_out;
+end
+
+always @ (posedge clk_i) begin
+   if (mode_load_pulse)
+        bl_out <= #TCQ    fixed_bl_i ;
+   else if (cmd_clk_en) begin
+     case({bl_mode_reg})
+         0: bl_out <= #TCQ    bram_bl_i  ;
+         1: bl_out <= #TCQ    fixed_bl_i ;
+         2: bl_out <= #TCQ    prbs_brlen;
+         default : bl_out <= #TCQ    6'h1;
+     endcase
+   end
+end
+
+  //synthesis translate_off
+always @ (bl_out)
+  if(bl_out >2 && FAMILY == "VIRTEX6") begin
+   $display("Error ! Not valid burst length");
+   $stop;
+   end
+  //synthesis translate_on
+
+generate
+if (CMD_PATTERN == "CGEN_PRBS" || CMD_PATTERN == "CGEN_ALL" ) begin: gen_prbs_bl
+cmd_prbs_gen #
+      (
+    .TCQ               (TCQ),      
+    .FAMILY      (FAMILY),
+    .PRBS_CMD    ("BLEN"),
+    .ADDR_WIDTH  (32),
+    .SEED_WIDTH  (15),
+    .PRBS_WIDTH  (20)
+   )
+   bl_prbs_gen
+  (
+   .clk_i             (clk_i),
+   .clk_en            (cmd_clk_en),
+   .prbs_seed_init    (load_seed_i),
+   .prbs_seed_i       (cmd_seed_i[16:2]),
+   .prbs_o            (prbs_bl)
+  );
+end
+
+always @ (prbs_bl)
+if (FAMILY == "SPARTAN6")  // supports 1 throug 64
+    prbs_brlen =  (prbs_bl[5:0] == 6'b000000) ? 6'b000001: prbs_bl[5:0];
+else // VIRTEX6 only supports 1 or 2 burst on user ports
+     prbs_brlen =  6'b000010;
+endgenerate
+
+endmodule

Frogwells_fpga_design/基于FPGA、DDR3和USB2.0的图像采集系统/debug/ddr_test/rtl/traffic_gen/cmd_prbs_gen.v

@@ -0,0 +1,251 @@
+//*****************************************************************************
+// (c) Copyright 2008-2009 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+//*****************************************************************************
+//   ____  ____
+//  /   /\/   /
+// /___/  \  /    Vendor: Xilinx
+// \   \   \/     Version: %version
+//  \   \         Application: MIG
+//  /   /         Filename: cmd_prbs_gen.v
+// /___/   /\     Date Last Modified:
+// \   \  /  \    Date Created:
+//  \___\/\___\
+//
+//Device: Spartan6
+//Design Name: DDR/DDR2/DDR3/LPDDR
+//Purpose:  This moduel use LFSR to generate random address, isntructions
+//          or burst_length.
+//Reference:
+//Revision History:     1.1 Added condition to zero out the LSB address bits according to
+//                      DWIDTH and FAMILY. 7/9/2009       
+//
+//*****************************************************************************
+
+`timescale 1ps/1ps
+
+module cmd_prbs_gen #
+  (
+   parameter TCQ           = 100,
+   parameter FAMILY     = "SPARTAN6",
+   parameter ADDR_WIDTH = 29,
+   parameter DWIDTH     = 32,
+   parameter PRBS_CMD   = "ADDRESS", // "INSTR", "BLEN","ADDRESS"
+   parameter PRBS_WIDTH = 64,          //   64,15,20
+   parameter SEED_WIDTH = 32,           //   32,15,4
+
+   parameter PRBS_EADDR_MASK_POS = 32'hFFFFD000,
+   parameter PRBS_SADDR_MASK_POS =  32'h00002000,
+   parameter PRBS_EADDR  = 32'h00002000,
+   parameter PRBS_SADDR  = 32'h00002000
+   )
+  (
+   input         clk_i,
+   input         prbs_seed_init,  // when high the prbs_x_seed will be loaded
+   input         clk_en,
+   input [SEED_WIDTH-1:0]  prbs_seed_i,
+
+   output[SEED_WIDTH-1:0]  prbs_o     // generated address
+  );
+
+wire[ADDR_WIDTH - 1:0] ZEROS;
+reg [SEED_WIDTH - 1:0] prbs;
+reg [PRBS_WIDTH :1] lfsr_q;
+
+assign ZEROS = 'b0;
+//
+//**************************************************************
+//####################################################################################################################
+//                                                                                                                   #
+//                                                                                                                   #
+// 64 taps: [64,63,61,60]: {{8'b01011000}, {56'b0}}                                                                  #
+//  upper 32 bits are loadable                                                                                       #
+//                                                                                                                   #
+//
+//
+//     ........................................................................................
+//         ^                  ^                      ^             ^                          |
+//         |   ____           |  ___     ___         | ___         |  ___     ___     ___     |
+//         |   |   |   |---|<-  |   |   |   | |---|<- |   |  |---|<- |   |...|   |   |   |    |  The first 32 bits are parallel loadable.
+//         ----|64 |<--|xor|<-- |63 |-->|62 |-|xor|<--|61 |<-|xor|<--|60 |...|33 |<--|1|<<--
+//             |___|    ---     |___|   |___|  ---    |___|   ---    |___|...|___|   |___|
+//
+//
+//                                           <<-- shifting  --
+//#####################################################################################################################
+
+// use SRLC32E for lower 32 stages and 32 registers for upper 32 stages.
+// we need to provide 30 bits addres. SRLC32 has only one bit output.
+// address seed will be loaded to upper 32 bits.
+//
+//  parallel load and serial shift out to  LFSR  during INIT time
+
+generate
+  if(PRBS_CMD == "ADDRESS" && PRBS_WIDTH == 64) begin :gen64_taps
+    always @ (posedge clk_i) begin
+      if(prbs_seed_init) begin//reset it to a known good state to prevent it locks up
+        lfsr_q <= #TCQ {31'b0,prbs_seed_i};
+      end else if(clk_en) begin
+        lfsr_q[64] <= #TCQ lfsr_q[64] ^ lfsr_q[63];
+        lfsr_q[63] <= #TCQ lfsr_q[62];
+        lfsr_q[62] <= #TCQ lfsr_q[64] ^ lfsr_q[61];
+        lfsr_q[61] <= #TCQ lfsr_q[64] ^ lfsr_q[60];
+        lfsr_q[60:2] <= #TCQ lfsr_q[59:1];
+        lfsr_q[1] <= #TCQ lfsr_q[64];
+      end
+    end
+
+    always @(lfsr_q[32:1]) begin
+      prbs = lfsr_q[32:1];
+    end
+  end
+endgenerate
+
+function integer logb2;
+  input [31:0] in;
+  integer i;
+  begin
+    i = in;
+      for(logb2=1; i>0; logb2=logb2+1)
+        i = i >> 1;
+  end
+endfunction
+
+generate
+  if(PRBS_CMD == "ADDRESS" && PRBS_WIDTH == 32) begin :gen32_taps
+    always @ (posedge clk_i) begin
+      if(prbs_seed_init) begin //reset it to a known good state to prevent it locks up
+        lfsr_q <= #TCQ {prbs_seed_i};
+      end else if(clk_en) begin
+        lfsr_q[32:9] <= #TCQ lfsr_q[31:8];
+        lfsr_q[8]    <= #TCQ lfsr_q[32] ^ lfsr_q[7];
+        lfsr_q[7]    <= #TCQ lfsr_q[32] ^ lfsr_q[6];
+        lfsr_q[6:4]  <= #TCQ lfsr_q[5:3];
+
+        lfsr_q[3]    <= #TCQ lfsr_q[32] ^ lfsr_q[2];
+        lfsr_q[2]    <= #TCQ lfsr_q[1] ;
+        lfsr_q[1]    <= #TCQ lfsr_q[32];
+      end
+    end
+
+    integer i;
+    always @(lfsr_q[32:1]) begin
+    
+     if (FAMILY == "SPARTAN6" ) begin  // for 32 bits
+    
+      for(i = logb2(DWIDTH) + 1; i <= SEED_WIDTH - 1; i = i + 1)
+
+       if(PRBS_SADDR_MASK_POS[i] == 1)
+          prbs[i] = PRBS_SADDR[i] | lfsr_q[i+1];
+       else if(PRBS_EADDR_MASK_POS[i] == 1)
+          prbs[i] = PRBS_EADDR[i] & lfsr_q[i+1];
+       else
+          prbs[i] =  lfsr_q[i+1];
+          
+       prbs[logb2(DWIDTH )  :0] = {logb2(DWIDTH ) + 1{1'b0}};         
+
+      end
+    else begin
+     for(i = logb2(DWIDTH)-4; i <= SEED_WIDTH - 1; i = i + 1)
+       if(PRBS_SADDR_MASK_POS[i] == 1)
+          prbs[i] = PRBS_SADDR[i] | lfsr_q[i+1];
+       else if(PRBS_EADDR_MASK_POS[i] == 1)
+          prbs[i] = PRBS_EADDR[i] & lfsr_q[i+1];
+       else
+          prbs[i] =  lfsr_q[i+1];
+     prbs[logb2(DWIDTH)-5:0] = {logb2(DWIDTH) - 4{1'b0}};
+
+    end  
+ 
+  end  
+end endgenerate
+
+//////////////////////////////////////////////////////////////////////////
+//####################################################################################################################
+//                                                                                                                   #
+//                                                                                                                   #
+// 15 taps: [15,14]:                                                                                                 #
+//                                                                                         #
+//                                                                                                                   #
+//
+//
+//         .............................................................
+//         ^                  ^              .                           ^
+//         |   ____           |  ___     ___     ___     ___     ___     |
+//         |   |   |   |---|<-  |   |   |   |   |   |...|   |   |   |    |
+//         ----|15 |<--|xor|<-- |14 |<--|13 |<--|12 |...|2  |<--|1  |<<--
+//             |___|    ---     |___|   |___|   |___|...|___|   |___|
+//
+//
+//                                           <<-- shifting  --
+//#####################################################################################################################
+
+generate
+  if(PRBS_CMD == "INSTR" | PRBS_CMD == "BLEN") begin :gen20_taps
+    always @(posedge clk_i) begin
+      if(prbs_seed_init) begin//reset it to a known good state to prevent it locks up
+        lfsr_q <= #TCQ {5'b0,prbs_seed_i[14:0]};
+      end else if(clk_en) begin
+        lfsr_q[20]   <= #TCQ lfsr_q[19];
+        lfsr_q[19]   <= #TCQ lfsr_q[18];
+
+        lfsr_q[18]   <= #TCQ lfsr_q[20] ^lfsr_q[17];
+
+        lfsr_q[17:2] <= #TCQ lfsr_q[16:1];
+        lfsr_q[1]    <= #TCQ lfsr_q[20];
+      end
+    end
+
+    always @ (lfsr_q[SEED_WIDTH - 1:1], ZEROS) begin
+        prbs = {ZEROS[SEED_WIDTH - 1:7],lfsr_q[6:1]};
+    end
+  end
+endgenerate
+
+assign prbs_o = prbs;
+
+endmodule

Frogwells_fpga_design/基于FPGA、DDR3和USB2.0的图像采集系统/debug/ddr_test/rtl/traffic_gen/data_prbs_gen.v

@@ -0,0 +1,127 @@
+//*****************************************************************************
+// (c) Copyright 2008-2009 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+//*****************************************************************************
+//   ____  ____
+//  /   /\/   /
+// /___/  \  /    Vendor: Xilinx
+// \   \   \/     Version: %version
+//  \   \         Application: MIG
+//  /   /         Filename: data_prbs_gen.v
+// /___/   /\     Date Last Modified: $Date: 2011/06/02 07:16:33 $
+// \   \  /  \    Date Created: Fri Sep 01 2006
+//  \___\/\___\
+//
+//Device: Spartan6
+//Design Name: DDR/DDR2/DDR3/LPDDR 
+//Purpose:  This module is used LFSR to generate random data for memory 
+//          data write or memory data read comparison.The first data is 
+//          seeded by the input prbs_seed_i which is connected to memory address.
+//Reference:
+//Revision History:
+//*****************************************************************************
+
+`timescale 1ps/1ps
+
+module data_prbs_gen #
+  (
+    parameter TCQ           = 100,
+
+    parameter EYE_TEST   = "FALSE",
+    parameter PRBS_WIDTH = 32,                                                                       // "SEQUENTIAL_BUrst_i"
+    parameter SEED_WIDTH = 32    
+   )
+  (
+   input           clk_i,
+   input           clk_en,
+   input           rst_i,
+   input [31:0] prbs_fseed_i,
+   input           prbs_seed_init,  // when high the prbs_x_seed will be loaded
+   input [PRBS_WIDTH - 1:0]  prbs_seed_i,
+   
+   output  [PRBS_WIDTH - 1:0]  prbs_o     // generated address
+  );
+  
+reg [PRBS_WIDTH - 1 :0] prbs;  
+reg [PRBS_WIDTH :1] lfsr_q;
+integer i;
+
+
+
+always @ (posedge clk_i)
+begin
+   if (prbs_seed_init && EYE_TEST == "FALSE"  || rst_i )  //reset it to a known good state to prevent it locks up
+//   if (rst_i )  //reset it to a known good state to prevent it locks up
+
+      begin
+        lfsr_q <= #TCQ  {prbs_seed_i + prbs_fseed_i[31:0] + 32'h55555555};
+
+      end
+   else   if (clk_en) begin
+     
+        lfsr_q[32:9] <= #TCQ  lfsr_q[31:8];
+        lfsr_q[8]    <= #TCQ  lfsr_q[32] ^ lfsr_q[7];
+        lfsr_q[7]    <= #TCQ  lfsr_q[32] ^ lfsr_q[6];
+        lfsr_q[6:4]  <= #TCQ  lfsr_q[5:3];
+        
+        lfsr_q[3]    <= #TCQ  lfsr_q[32] ^ lfsr_q[2];
+        lfsr_q[2]    <= #TCQ  lfsr_q[1] ;
+        lfsr_q[1]    <= #TCQ  lfsr_q[32];
+       
+        
+         end
+end
+ 
+always @ (lfsr_q[PRBS_WIDTH:1]) begin
+       prbs = lfsr_q[PRBS_WIDTH:1];
+end
+
+assign prbs_o = prbs;
+
+endmodule
+   
+         

Frogwells_fpga_design/基于FPGA、DDR3和USB2.0的图像采集系统/debug/ddr_test/rtl/traffic_gen/init_mem_pattern_ctr.v

@@ -0,0 +1,692 @@
+//*****************************************************************************
+// (c) Copyright 2008-2009 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+//*****************************************************************************
+//   ____  ____
+//  /   /\/   /
+// /___/  \  /    Vendor: Xilinx
+// \   \   \/     Version: %version
+//  \   \         Application: MIG
+//  /   /         Filename: init_mem_pattern_ctr.v
+// /___/   /\     Date Last Modified: $Date: 2011/06/02 07:16:33 $
+// \   \  /  \    Date Created: Fri Sep 01 2006
+//  \___\/\___\
+//
+//Device: Spartan6
+//Design Name: DDR/DDR2/DDR3/LPDDR 
+//Purpose: This moduel has a small FSM to control the operation of 
+//         mcb_traffic_gen module.It first fill up the memory with a selected 
+//         DATA pattern and then starts the memory testing state.
+//Reference:
+//Revision History: 1.1 Modify to allow data_mode_o to be controlled by parameter DATA_MODE
+//                      and the fixed_bl_o is fixed at 64 if data_mode_o == PRBA and FAMILY == "SPARTAN6"
+//                      The fixed_bl_o in Virtex6 is determined by the MEM_BURST_LENGTH.
+//                  1.2 10-1-2009 Added parameter TST_MEM_INSTR_MODE to select instruction pattern during 
+//                      memory testing phase.	   
+//                  1.3    05/19/2010 If MEM_BURST_LEN value is passed with value of zero, it is treated as
+//                                    "OTF" Burst Mode and TG will only generate BL 8 traffic.
+
+
+//*****************************************************************************
+
+`timescale 1ps/1ps
+
+
+
+
+
+module init_mem_pattern_ctr #
+  (
+   parameter TCQ           = 100,  
+   parameter FAMILY         = "SPARTAN6",      // VIRTEX6, SPARTAN6
+   parameter TST_MEM_INSTR_MODE = "R_W_INSTR_MODE", // Spartan6 Available commands: 
+                                                    // "FIXED_INSTR_R_MODE", "FIXED_INSTR_W_MODE"
+                                                    // "R_W_INSTR_MODE", "RP_WP_INSTR_MODE 
+                                                    // "R_RP_W_WP_INSTR_MODE", "R_RP_W_WP_REF_INSTR_MODE"
+                                                    // Virtex 6 Available commands:
+                                                    // "FIXED_INSTR_R_MODE" - Only Read commands will be generated.
+                                                    // "FIXED_INSTR_W_MODE" -- Only Write commands will be generated.
+                                                    // "R_W_INSTR_MODE"     - Random Read/Write commands will be generated.
+   parameter MEM_BURST_LEN  = 8,                    // VIRTEX 6 Option. 
+   parameter CMD_PATTERN    = "CGEN_ALL",           // "CGEN_ALL" option generates all available
+                                                    // commands pattern.
+   parameter BEGIN_ADDRESS  = 32'h00000000, 
+   parameter END_ADDRESS  = 32'h00000fff,   
+   parameter ADDR_WIDTH     = 30,
+   parameter DWIDTH        = 32,
+   parameter CMD_SEED_VALUE   = 32'h12345678,
+   parameter DATA_SEED_VALUE  = 32'hca345675,
+   parameter DATA_MODE     = 4'b0010,
+   parameter PORT_MODE     = "BI_MODE", // V6 Option: "BI_MODE"; SP6 Option: "WR_MODE", "RD_MODE", "BI_MODE"
+   parameter EYE_TEST      = "FALSE"  // set EYE_TEST = "TRUE" to probe memory signals.
+                                      // Traffic Generator will only write to one single location and no
+                                      // read transactions will be generated.
+   
+   )
+  (
+   input           clk_i,
+   input           rst_i,
+   
+   input [ADDR_WIDTH-1:0]   mcb_cmd_addr_i,
+   input [5:0]    mcb_cmd_bl_i,
+   input          mcb_cmd_en_i,
+   input [2:0]    mcb_cmd_instr_i,        
+   input          mcb_wr_en_i,
+   input          vio_modify_enable,            // 0: default to ADDR as DATA PATTERN. No runtime change in data mode.
+                                                // 1: enable exteral VIO to control the data_mode pattern
+                                                //    and address mode pattern during runtime.
+   input [2:0]    vio_data_mode_value,
+   input [2:0]    vio_addr_mode_value,
+   input [1:0]    vio_bl_mode_value,
+   input [5:0]    vio_fixed_bl_value,  // valid range is:  from 1 to 64.
+   
+   input           mcb_init_done_i,
+   input           cmp_error,
+   output reg          run_traffic_o,
+  // runtime parameter
+   output [31:0]             start_addr_o,   // define the start of address
+   output [31:0]             end_addr_o,
+   output [31:0]             cmd_seed_o,    // same seed apply to all addr_prbs_gen, bl_prbs_gen, instr_prbs_gen
+   output [31:0]             data_seed_o,
+   output  reg                  load_seed_o,   // 
+   // upper layer inputs to determine the command bus and data pattern
+   // internal traffic generator initialize the memory with 
+   output reg [2:0]              addr_mode_o,  // "00" = bram; takes the address from bram output
+                                          // "001" = fixed address from the fixed_addr input
+                                          // "010" = psuedo ramdom pattern; generated from internal 64 bit LFSR
+                                          // "011" = sequential
+  
+  
+  // for each instr_mode, traffic gen fill up with a predetermined pattern before starting the instr_pattern that defined
+  // in the instr_mode input. The runtime mode will be automatically loaded inside when it is in 
+   output reg [3:0]              instr_mode_o, // "0000" = Fixed
+                                              // "0001" = bram; takes instruction from bram output
+                                              // "0010" = R/W
+                                              // "0011" = RP/WP
+                                              // "0100" = R/RP/W/WP
+                                              // "0101" = R/RP/W/WP/REF
+                                       
+                                        
+   output reg [1:0]              bl_mode_o,    // "00" = bram;   takes the burst length from bram output
+                                        // "01" = fixed , takes the burst length from the fixed_bl input
+                                        // "10" = psuedo ramdom pattern; generated from internal 16 bit LFSR
+   
+   output reg [3:0]              data_mode_o,   // "00" = bram; 
+                                         // "01" = fixed data from the fixed_data input
+                                         // "10" = psuedo ramdom pattern; generated from internal 32 bit LFSR
+                                         // "11" = sequential using the addrs as the starting data pattern
+   output reg                   mode_load_o,
+ 
+   // fixed pattern inputs interface
+   output reg [5:0]              fixed_bl_o,      // range from 1 to 64
+   output reg [2:0]              fixed_instr_o,   //RD              3'b001
+                                            //RDP             3'b011
+                                            //WR              3'b000
+                                            //WRP             3'b010
+                                            //REFRESH         3'b100
+   output  [31:0]             fixed_addr_o // only upper 30 bits will be used
+   
+  );
+
+   //FSM State Defination
+parameter IDLE           = 5'b00001,
+          INIT_MEM_WRITE = 5'b00010,
+          INIT_MEM_READ  = 5'b00100,
+          TEST_MEM       = 5'b01000,
+          CMP_ERROR      = 5'b10000;
+
+
+localparam BRAM_ADDR       = 2'b00;
+localparam FIXED_ADDR      = 2'b01;
+localparam PRBS_ADDR       = 2'b10;
+localparam SEQUENTIAL_ADDR = 2'b11;
+
+localparam  BRAM_INSTR_MODE        =    4'b0000;
+localparam  FIXED_INSTR_MODE         =   4'b0001;
+localparam  R_W_INSTR_MODE          =   4'b0010;
+localparam  RP_WP_INSTR_MODE        =   4'b0011;
+localparam R_RP_W_WP_INSTR_MODE     =   4'b0100;
+localparam R_RP_W_WP_REF_INSTR_MODE =   4'b0101;
+                                     
+localparam BRAM_BL_MODE          =   2'b00;
+localparam FIXED_BL_MODE         =   2'b01;
+localparam PRBS_BL_MODE          =   2'b10;
+
+localparam BRAM_DATAL_MODE       =    4'b0000;
+localparam FIXED_DATA_MODE       =    4'b0001;
+localparam ADDR_DATA_MODE        =    4'b0010;                                     
+localparam HAMMER_DATA_MODE      =    4'b0011;
+localparam NEIGHBOR_DATA_MODE    =    4'b0100;
+localparam WALKING1_DATA_MODE    =    4'b0101;
+localparam WALKING0_DATA_MODE    =    4'b0110;
+localparam PRBS_DATA_MODE        =    4'b0111;
+
+// type fixed instruction
+localparam  RD_INSTR       =  3'b001;
+localparam  RDP_INSTR      =  3'b011;
+localparam  WR_INSTR       =  3'b000;
+
+localparam  WRP_INSTR      =  3'b010;
+localparam  REFRESH_INSTR  =  3'b100;
+localparam  NOP_WR_INSTR   =  3'b101;
+
+
+reg [4:0] current_state;
+reg [4:0] next_state;
+reg       mcb_init_done_reg;
+reg       mcb_init_done_reg1;
+reg AC2_G_E2,AC1_G_E1,AC3_G_E3;
+reg upper_end_matched;
+reg [31:0] end_boundary_addr;     
+reg [31:0] mcb_cmd_addr_r;
+
+reg mcb_cmd_en_r;
+//reg [ADDR_WIDTH-1:0] mcb_cmd_addr_r;
+reg [5:0] mcb_cmd_bl_r;
+reg lower_end_matched;   
+reg end_addr_reached;
+reg run_traffic;
+reg bram_mode_enable;
+wire tst_matched;
+reg [31:0] current_address;
+reg [5:0]  fix_bl_value;
+reg [3:0] data_mode_sel;
+reg [2:0] addr_mode_sel;
+reg [1:0] bl_mode_sel;
+reg [2:0] addr_mode;
+reg [10:0] INC_COUNTS;
+wire [5:0] FIXEDBL;
+wire [3:0] test_mem_instr_mode;
+
+assign test_mem_instr_mode = (TST_MEM_INSTR_MODE == "BRAM_INSTR_MODE")               ? 4'b0000:
+                             (TST_MEM_INSTR_MODE == "FIXED_INSTR_R_MODE"  ||
+                              TST_MEM_INSTR_MODE == "FIXED_INSTR_W_MODE")              ? 4'b0001:
+                             (TST_MEM_INSTR_MODE == "R_W_INSTR_MODE")                                    ? 4'b0010:
+                             (TST_MEM_INSTR_MODE == "RP_WP_INSTR_MODE"         && FAMILY == "SPARTAN6")  ? 4'b0011:
+                             (TST_MEM_INSTR_MODE == "R_RP_W_WP_INSTR_MODE"     && FAMILY == "SPARTAN6")  ? 4'b0100:
+                             (TST_MEM_INSTR_MODE == "R_RP_W_WP_REF_INSTR_MODE" && FAMILY == "SPARTAN6")  ? 4'b0101:
+                             4'b0010;
+
+
+
+
+assign FIXEDBL = 64; // This is fixed for current Spartan 6 Example Design
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+generate
+if (FAMILY == "SPARTAN6" ) begin : INC_COUNTS_S
+    
+always @ (posedge clk_i)
+    INC_COUNTS <= (DWIDTH/8);
+    
+end
+endgenerate
+
+
+
+
+
+
+generate
+if (FAMILY == "VIRTEX6" ) begin : INC_COUNTS_V
+always @ (posedge clk_i)
+begin
+if ( (DWIDTH >= 256 && DWIDTH <= 576))          // 64  144
+     INC_COUNTS <= 32  ;
+else if ((DWIDTH >= 128) && (DWIDTH <= 224))    // 32 dq pins or 566 dq pins
+     INC_COUNTS <= 16     ;
+else if ((DWIDTH == 64) || (DWIDTH == 96))      // 16 dq pins or 24 dqpins
+     INC_COUNTS <= 8  ;
+else if ((DWIDTH == 32) )      // 8 dq pins 
+     INC_COUNTS <= 4 ;
+end
+end
+endgenerate
+
+
+always @ (posedge clk_i)
+begin
+if (rst_i)
+    current_address <= BEGIN_ADDRESS;
+else if (mcb_wr_en_i && (current_state == INIT_MEM_WRITE && (PORT_MODE == "WR_MODE" || PORT_MODE == "BI_MODE"))
+         || (mcb_wr_en_i && (current_state == IDLE && PORT_MODE == "RD_MODE")) )
+    current_address <= current_address + INC_COUNTS;
+else
+    current_address <= current_address;
+
+end    
+
+
+always @ (posedge clk_i)
+begin
+  if (current_address[29:24] >= end_boundary_addr[29:24])
+      AC3_G_E3 <= 1'b1;
+  else
+      AC3_G_E3 <= 1'b0;
+  
+  
+    if (current_address[23:16] >= end_boundary_addr[23:16])
+      AC2_G_E2 <= 1'b1;
+  else
+      AC2_G_E2 <= 1'b0;
+  
+  if (current_address[15:8] >= end_boundary_addr[15:8])
+      AC1_G_E1 <= 1'b1;
+else
+      AC1_G_E1 <= 1'b0;
+  
+  
+end
+always @(posedge clk_i)
+begin
+if (rst_i)
+     upper_end_matched <= 1'b0;
+ 
+ else if (mcb_cmd_en_i)
+     upper_end_matched <= AC3_G_E3 & AC2_G_E2 & AC1_G_E1;
+end   
+
+wire [6:0] FIXED_BL_VALUE;
+assign FIXED_BL_VALUE = (FAMILY == "VIRTEX6" && (MEM_BURST_LEN == 8 || MEM_BURST_LEN == 0)) ? 2 :
+                        (FAMILY == "VIRTEX6" && MEM_BURST_LEN == 4) ? 1 :
+                         FIXEDBL;
+
+always @(posedge clk_i)
+begin
+//   end_boundary_addr <= (END_ADDRESS[31:0] - (DWIDTH/8)*FIXEDBL +1) ;
+     end_boundary_addr <= (END_ADDRESS[31:0] - (DWIDTH/8) +1) ;
+
+end   
+
+
+
+always @(posedge clk_i)
+begin
+  if (current_address[7:0] >= end_boundary_addr[7:0])
+
+   lower_end_matched <= 1'b1;
+  else
+   lower_end_matched <= 1'b0;
+  
+end   
+
+
+always @(posedge clk_i)
+begin
+  if (mcb_cmd_en_i )
+   mcb_cmd_addr_r <= mcb_cmd_addr_i;
+end   
+
+
+always @(posedge clk_i)
+begin
+  if (mcb_cmd_en_i)
+   mcb_cmd_bl_r <= mcb_cmd_bl_i;
+end   
+
+always @(posedge clk_i)
+begin
+   if ((upper_end_matched && lower_end_matched && FAMILY == "SPARTAN6" && DWIDTH == 32) ||
+      (upper_end_matched && lower_end_matched && FAMILY == "SPARTAN6" && DWIDTH == 64) ||   
+      (upper_end_matched && DWIDTH == 128 && FAMILY == "SPARTAN6") ||
+      (upper_end_matched && lower_end_matched && FAMILY == "VIRTEX6"))
+      end_addr_reached <= 1'b1;
+   else    
+      end_addr_reached <= 1'b0;
+
+end 
+
+ 
+assign tst_matched = upper_end_matched & lower_end_matched;
+
+assign   fixed_addr_o = 32'h00001234;
+
+
+
+ always @ (posedge clk_i)
+ begin
+      mcb_init_done_reg1 <= mcb_init_done_i;
+      mcb_init_done_reg <= mcb_init_done_reg1;
+end
+
+ always @ (posedge clk_i)
+       run_traffic_o <= run_traffic;
+
+
+ 
+ always @ (posedge clk_i)
+ begin
+    if (rst_i)
+        current_state <= 5'b00001;
+    else
+        current_state <= next_state;
+ end
+
+   assign          start_addr_o  = BEGIN_ADDRESS;//BEGIN_ADDRESS;
+   assign          end_addr_o    = END_ADDRESS;
+   assign          cmd_seed_o    = CMD_SEED_VALUE;
+   assign          data_seed_o   = DATA_SEED_VALUE;
+
+
+reg [2:0] syn1_vio_data_mode_value;
+reg [2:0] syn1_vio_addr_mode_value;
+
+
+ always @ (posedge clk_i)
+ begin
+   if (rst_i) begin
+        syn1_vio_data_mode_value <= 3'b011;
+        syn1_vio_addr_mode_value <= 2'b11;
+       end        
+ else if (vio_modify_enable == 1'b1) begin
+   syn1_vio_data_mode_value <= vio_data_mode_value;
+   syn1_vio_addr_mode_value <= vio_addr_mode_value;
+   end
+ end
+ 
+
+ always @ (posedge clk_i)
+ begin
+ if (rst_i) begin
+       data_mode_sel <= DATA_MODE;//ADDR_DATA_MODE;
+       addr_mode_sel <= 2'b11;
+       end
+ else if (vio_modify_enable == 1'b1) begin
+       data_mode_sel <= syn1_vio_data_mode_value[2:0];
+       addr_mode_sel <= vio_addr_mode_value;
+       end
+ end
+
+ always @ (posedge clk_i)
+ begin
+ if (rst_i  || FAMILY == "VIRTEX6") 
+       fix_bl_value <= FIXED_BL_VALUE;//ADDR_DATA_MODE;
+
+ else if (vio_modify_enable == 1'b1) begin
+       fix_bl_value <= vio_fixed_bl_value;
+       end
+ end
+
+ always @ (posedge clk_i)
+ begin
+ if (rst_i || (FAMILY == "VIRTEX6")) 
+      if  (FAMILY == "VIRTEX6")
+         bl_mode_sel <= FIXED_BL_MODE;
+      else
+       bl_mode_sel <= PRBS_BL_MODE;
+ else if (vio_modify_enable == 1'b1) begin
+       bl_mode_sel <= vio_bl_mode_value;
+       end
+ end
+
+
+
+
+
+always @ (posedge clk_i)
+begin
+    data_mode_o   <= data_mode_sel;
+    addr_mode_o   <= addr_mode;
+    
+    // assuming if vio_modify_enable is enabled and vio_addr_mode_value is set to zero
+    // user wants to have bram interface.
+    if (syn1_vio_addr_mode_value == 0 && vio_modify_enable == 1'b1)
+        bram_mode_enable <=  1'b1;
+    else
+        bram_mode_enable <=  1'b0;
+    
+ end
+ 
+
+always @ (*)
+begin
+             load_seed_o   = 1'b0;
+             if (CMD_PATTERN == "CGEN_BRAM" || bram_mode_enable )
+                 addr_mode = 'b0;
+             else
+                 addr_mode   = SEQUENTIAL_ADDR;
+
+             if (CMD_PATTERN == "CGEN_BRAM" || bram_mode_enable )
+                 instr_mode_o = 'b0;
+             else
+                 instr_mode_o   = FIXED_INSTR_MODE;
+
+
+             if (CMD_PATTERN == "CGEN_BRAM" || bram_mode_enable )
+                 bl_mode_o = 'b0;
+             else
+                 bl_mode_o   = FIXED_BL_MODE;
+
+           
+             
+             if (FAMILY == "VIRTEX6")
+                 fixed_bl_o = FIXED_BL_VALUE;
+                                                 // PRBS mode
+             else if (data_mode_o[2:0] == 3'b111 && FAMILY == "SPARTAN6")
+                 fixed_bl_o = 64;  // Our current PRBS algorithm wants to maximize the range bl from 1 to 64.
+             else
+                  fixed_bl_o    = fix_bl_value;
+                 
+                 
+                 
+             mode_load_o   = 1'b0;
+             run_traffic = 1'b0;   
+             next_state = IDLE;
+
+             if (PORT_MODE == "RD_MODE") begin
+               fixed_instr_o = RD_INSTR;
+             end
+              else if( PORT_MODE == "WR_MODE" || PORT_MODE == "BI_MODE") begin
+               fixed_instr_o = WR_INSTR;
+             end
+             
+case(current_state)
+   IDLE:  
+        begin
+         if(mcb_init_done_reg )   //rdp_rdy_i comes from read_data path
+            begin
+              if (PORT_MODE == "WR_MODE" || PORT_MODE == "BI_MODE") begin
+                 next_state = INIT_MEM_WRITE;
+              mode_load_o = 1'b1;
+              run_traffic = 1'b0;
+              load_seed_o   = 1'b1;
+             end
+              else if (PORT_MODE == "RD_MODE" && end_addr_reached) begin
+                    next_state = TEST_MEM;
+                    mode_load_o = 1'b1;
+                    run_traffic = 1'b1;
+              load_seed_o   = 1'b1;
+                    
+              end
+            end
+         else
+              begin
+              next_state = IDLE;
+              run_traffic = 1'b0;
+              load_seed_o   = 1'b0;
+              
+              end
+         
+         end
+   INIT_MEM_WRITE:  begin
+   
+         if (end_addr_reached  && EYE_TEST == "FALSE"  )
+            begin
+               next_state = TEST_MEM;
+               mode_load_o = 1'b1;
+               load_seed_o   = 1'b1;
+               run_traffic = 1'b1;
+               
+            end   
+          else
+             begin
+               next_state = INIT_MEM_WRITE;
+              run_traffic = 1'b1; 
+              mode_load_o = 1'b0;
+              load_seed_o   = 1'b0;
+              if (EYE_TEST == "TRUE")  
+                addr_mode   = FIXED_ADDR;
+              else if (CMD_PATTERN == "CGEN_BRAM" || bram_mode_enable )
+                addr_mode = 'b0;
+              else
+                addr_mode   = SEQUENTIAL_ADDR;
+              
+             end  
+         
+        end
+      
+   INIT_MEM_READ:  begin
+   
+         if (end_addr_reached  )
+            begin
+               next_state = TEST_MEM;
+               mode_load_o = 1'b1;
+              load_seed_o   = 1'b1;
+               
+            end   
+          else
+             begin
+               next_state = INIT_MEM_READ;
+              run_traffic = 1'b0; 
+              mode_load_o = 1'b0;
+              load_seed_o   = 1'b0;
+              
+             end  
+         
+        end
+   TEST_MEM: begin  
+         if (cmp_error)
+               next_state = CMP_ERROR;
+               
+         else
+           next_state = TEST_MEM;
+           run_traffic = 1'b1;
+       
+
+           if (PORT_MODE == "BI_MODE" && TST_MEM_INSTR_MODE == "FIXED_INSTR_W_MODE")
+                fixed_instr_o = WR_INSTR;
+           else if (PORT_MODE == "BI_MODE" && TST_MEM_INSTR_MODE == "FIXED_INSTR_R_MODE")
+                fixed_instr_o = RD_INSTR;                
+           else if (PORT_MODE == "RD_MODE")
+              fixed_instr_o = RD_INSTR;
+           
+           else if( PORT_MODE == "WR_MODE") 
+              fixed_instr_o = WR_INSTR;
+           
+        
+             if (FAMILY == "VIRTEX6")
+                 fixed_bl_o = fix_bl_value;
+             else if ((data_mode_o == 3'b111) && (FAMILY == "SPARTAN6"))
+                 fixed_bl_o = 64;  // Our current PRBS algorithm wants to maximize the range bl from 1 to 64.
+             else
+            fixed_bl_o    = fix_bl_value;
+                 
+           bl_mode_o     = bl_mode_sel;//FIXED_BL_MODE;//PRBS_BL_MODE;//PRBS_BL_MODE; //FIXED_BL_MODE;
+
+              if (bl_mode_o == PRBS_BL_MODE)  
+                addr_mode   = PRBS_ADDR;
+              else
+                addr_mode   = addr_mode_sel;
+
+           
+           
+           if(PORT_MODE == "BI_MODE") begin
+               if(CMD_PATTERN == "CGEN_BRAM" || bram_mode_enable )
+                   instr_mode_o  = BRAM_INSTR_MODE;
+               else
+                   instr_mode_o  = test_mem_instr_mode;//R_RP_W_WP_REF_INSTR_MODE;//FIXED_INSTR_MODE;//R_W_INSTR_MODE;//R_RP_W_WP_INSTR_MODE;//R_W_INSTR_MODE;//R_W_INSTR_MODE; //FIXED_INSTR_MODE;//
+              end
+           else if (PORT_MODE == "RD_MODE" || PORT_MODE == "WR_MODE") begin
+               instr_mode_o  = FIXED_INSTR_MODE;
+           end
+              
+         end
+   
+   
+   
+
+   
+   CMP_ERROR: 
+        begin
+               next_state = CMP_ERROR;
+               bl_mode_o     = bl_mode_sel;//PRBS_BL_MODE;//PRBS_BL_MODE; //FIXED_BL_MODE;
+               fixed_instr_o = RD_INSTR;
+               addr_mode   = SEQUENTIAL_ADDR;//PRBS_ADDR;//PRBS_ADDR;//PRBS_ADDR;//SEQUENTIAL_ADDR;   
+               if(CMD_PATTERN == "CGEN_BRAM" || bram_mode_enable )
+                   instr_mode_o  = BRAM_INSTR_MODE;//
+               else
+                   instr_mode_o  = test_mem_instr_mode;//FIXED_INSTR_MODE;//R_W_INSTR_MODE;//R_RP_W_WP_INSTR_MODE;//R_W_INSTR_MODE;//R_W_INSTR_MODE; //FIXED_INSTR_MODE;//
+               
+               run_traffic = 1'b1;       // ?? keep it running or stop if error happened
+
+        end
+   default:
+          begin
+            next_state = IDLE;       
+           //run_traffic = 1'b0;              
+
+        end
+  
+ endcase
+ end
+
+
+
+
+endmodule

Frogwells_fpga_design/基于FPGA、DDR3和USB2.0的图像采集系统/debug/ddr_test/rtl/traffic_gen/mcb_flow_control.v

@@ -0,0 +1,634 @@
+//*****************************************************************************
+// (c) Copyright 2008-2009 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+//*****************************************************************************
+//   ____  ____
+//  /   /\/   /
+// /___/  \  /    Vendor: Xilinx
+// \   \   \/     Version: %version
+//  \   \         Application: MIG
+//  /   /         Filename: mcb_flow_control.v
+// /___/   /\     Date Last Modified: $Date: 2011/06/02 07:16:33 $
+// \   \  /  \    Date Created: 
+//  \___\/\___\
+//
+//Device: Spartan6
+//Design Name: DDR/DDR2/DDR3/LPDDR 
+//Purpose: This module is the main flow control between cmd_gen.v, 
+//         write_data_path and read_data_path modules.
+//Design Name: DDR/DDR2/DDR3/LPDDR 
+//Reference:
+//Revision History:
+//*****************************************************************************
+
+`timescale 1ps/1ps
+
+module mcb_flow_control #
+  (
+    parameter TCQ           = 100,
+    parameter FAMILY = "SPARTAN6"
+  )
+  ( 
+   input     clk_i, 
+   input [9:0]    rst_i,
+   // interface to cmd_gen, pipeline inserter
+   output  reg     cmd_rdy_o, 
+   input        cmd_valid_i, 
+   input [2:0]  cmd_i, 
+   input [31:0] addr_i, 
+   input [5:0]  bl_i,
+
+   
+   // interface to mcb_cmd port
+   input                  mcb_cmd_full,
+   output reg [2:0]           cmd_o, 
+   output reg [31:0]          addr_o, 
+   output reg [5:0]           bl_o,
+   output                 cmd_en_o,   // interface to write data path module
+   input                  last_word_wr_i,
+   input                  wdp_rdy_i, 
+   output                 wdp_valid_o, 
+   output                 wdp_validB_o, 
+   output                 wdp_validC_o,   
+   
+   output  [31:0]          wr_addr_o, 
+   output  [5:0]           wr_bl_o,
+   // interface to read data path module
+   input                   last_word_rd_i,
+   input                   rdp_rdy_i, 
+   output                  rdp_valid_o, 
+   output  [31:0]           rd_addr_o, 
+   output [5:0]            rd_bl_o
+   );
+   
+   //FSM State Defination
+localparam READY    = 5'b00001,
+          READ     = 5'b00010,
+          WRITE    = 5'b00100,
+          CMD_WAIT = 5'b01000,
+          REFRESH_ST = 5'b10000; 
+
+localparam RD     =         3'b001;
+localparam RDP    =         3'b011;
+localparam WR     =         3'b000;
+localparam WRP    =         3'b010;
+localparam REFRESH =        3'b100;
+localparam NOP     =        3'b101;  // this defination is local to this traffic gen and is not defined
+
+
+reg cmd_fifo_rdy;
+wire cmd_rd;
+wire cmd_wr;         // need equation
+wire cmd_others;
+reg  push_cmd;
+reg  xfer_cmd;
+reg  rd_vld  ;  
+reg  wr_vld;
+reg  cmd_rdy;
+reg [2:0]   cmd_reg; 
+reg [31:0]  addr_reg; 
+reg [5:0]   bl_reg;
+
+reg       rdp_valid;
+(*EQUIVALENT_REGISTER_REMOVAL="NO"*) reg   wdp_valid,wdp_validB,wdp_validC;
+
+reg [4:0] current_state;
+reg [4:0] next_state;
+reg [3:0] tstpointA;
+reg push_cmd_r;
+reg wait_done;
+reg cmd_en_r1 ;
+reg wr_in_progress;
+reg tst_cmd_rdy_o;
+
+
+
+
+//  mcb_command bus outputs
+assign cmd_en_o = cmd_en_r1;
+
+always @ (posedge clk_i) begin
+
+    cmd_rdy_o <= #TCQ  cmd_rdy;
+    tst_cmd_rdy_o <= #TCQ  cmd_rdy;
+    
+end
+
+always @ (posedge clk_i)
+begin
+if (rst_i[8])
+    cmd_en_r1 <= #TCQ  1'b0;
+else if ( xfer_cmd)
+    cmd_en_r1 <= #TCQ  1'b1;
+ else if (!mcb_cmd_full)
+    cmd_en_r1 <= #TCQ  1'b0;
+ 
+ end
+
+always @ (posedge clk_i)
+begin
+if (rst_i[9])
+    cmd_fifo_rdy <= #TCQ  1'b1;
+else if (xfer_cmd)
+    cmd_fifo_rdy <= #TCQ  1'b0;
+else if (!mcb_cmd_full)    
+    cmd_fifo_rdy <= #TCQ  1'b1;
+end
+
+always @ (posedge clk_i)
+begin
+if (rst_i[9]) begin
+    addr_o <= #TCQ  'b0;
+    cmd_o  <= #TCQ  'b0;
+    bl_o   <= #TCQ  'b0;
+end
+else if (xfer_cmd ) begin
+    addr_o <= #TCQ  addr_reg;           
+    if (FAMILY == "SPARTAN6")
+        cmd_o <= #TCQ  cmd_reg;
+    else
+        cmd_o  <= #TCQ  {2'b00,cmd_reg[0]};
+    bl_o   <= #TCQ  bl_reg;
+end
+
+end
+
+// go directly to wr_datapath and rd_datapath modules 
+       assign  wr_addr_o = addr_i;
+       assign  rd_addr_o = addr_i;
+assign rd_bl_o   = bl_i ;
+assign wr_bl_o   = bl_i ;
+
+assign wdp_valid_o = wdp_valid;
+assign wdp_validB_o = wdp_validB;
+assign wdp_validC_o = wdp_validC;
+
+assign rdp_valid_o = rdp_valid;
+
+
+// internal control siganls
+
+always @ (posedge clk_i)
+begin
+if (rst_i[8])
+   wait_done <= #TCQ  1'b1;
+else if (push_cmd_r)
+   wait_done <=  #TCQ 1'b1;
+else if (cmd_rdy_o && cmd_valid_i && FAMILY == "SPARTAN6")
+   wait_done <=  #TCQ 1'b0;
+
+
+end
+
+//  
+
+
+always @ (posedge clk_i)
+     begin
+     push_cmd_r  <= #TCQ push_cmd;
+    // push_cmd_r2 <= #TCQ push_cmd_r;
+     end
+always @ (posedge clk_i)
+ if (push_cmd)
+   begin
+        cmd_reg <=    #TCQ cmd_i;
+        addr_reg <= #TCQ addr_i;
+        bl_reg   <= #TCQ bl_i - 1;
+        
+end
+ 
+ 
+   
+//--Command Decodes--
+assign  cmd_wr     = ((cmd_i == WR  | cmd_i == WRP) & cmd_valid_i )  ? 1'b1 : 1'b0;
+assign  cmd_rd     = ((cmd_i == RD | cmd_i == RDP) & cmd_valid_i) ? 1'b1 : 1'b0;
+assign  cmd_others = ((cmd_i[2] == 1'b1)& cmd_valid_i && (FAMILY == "SPARTAN6")) ? 1'b1 : 1'b0;
+
+    
+reg cmd_wr_pending_r1;  
+reg cmd_rd_pending_r1;  
+
+always @ (posedge clk_i)
+begin
+if (rst_i[0])
+    cmd_wr_pending_r1 <= #TCQ 1'b0;
+
+//else if (current_state == WRITE && last_word_wr_i && !cmd_fifo_rdy)
+//else if ( last_word_wr_i && !cmd_fifo_rdy)
+else if ( last_word_wr_i )
+
+
+    cmd_wr_pending_r1 <= #TCQ 1'b1;
+else if (push_cmd)//xfer_cmd)
+    cmd_wr_pending_r1 <= #TCQ 1'b0;
+end    
+
+
+// corner case if fixed read command with fixed bl 64
+
+always @ (posedge clk_i)
+begin
+if (cmd_rd & push_cmd)
+    cmd_rd_pending_r1 <= #TCQ 1'b1;
+else if (xfer_cmd)
+    cmd_rd_pending_r1 <= #TCQ 1'b0;
+
+end    
+
+ always @ (posedge clk_i)
+ begin
+if (rst_i[0])
+   wr_in_progress <= #TCQ  1'b0;
+else if (last_word_wr_i)   
+   wr_in_progress <= #TCQ  1'b0;   
+else if (current_state == WRITE)   
+   wr_in_progress <= #TCQ  1'b1;
+
+
+end
+ always @ (posedge clk_i)
+ begin
+    if (rst_i[0])
+        current_state <= #TCQ  4'b0001;
+    else
+        current_state <= #TCQ next_state;
+ end
+
+// mcb_flow_control statemachine
+always @ (*)
+begin
+               push_cmd  = 1'b0;
+               xfer_cmd = 1'b0;
+               
+               wdp_valid = 1'b0;
+               wdp_validB = 1'b0;
+               wdp_validC = 1'b0;
+               
+               rdp_valid = 1'b0;
+               cmd_rdy = 1'b0;
+               next_state = current_state;
+case(current_state)
+   READY:  
+        begin
+         if(rdp_rdy_i & cmd_rd & cmd_fifo_rdy)   //rdp_rdy_i comes from read_data path
+
+            begin
+              next_state = READ;
+              push_cmd = 1'b1;
+              xfer_cmd = 1'b0;
+              rdp_valid = 1'b1;
+              
+            end
+         else if (wdp_rdy_i & cmd_wr & cmd_fifo_rdy)
+             begin
+              next_state = WRITE;
+               push_cmd = 1'b1;
+               wdp_valid     = 1'b1;
+               wdp_validB = 1'b1;
+               wdp_validC = 1'b1;
+               
+             end 
+         else if ( cmd_others & cmd_fifo_rdy)
+             begin
+              next_state = REFRESH_ST;
+               push_cmd = 1'b1;
+               xfer_cmd = 1'b0;
+               
+             end 
+             
+         else
+              begin
+              next_state = READY;
+              push_cmd = 1'b0;
+              end
+              
+              
+         if (cmd_fifo_rdy)
+             cmd_rdy = 1'b1;
+         else
+             cmd_rdy = 1'b0;
+         
+         
+         end
+         
+   REFRESH_ST : begin
+   
+         if (rdp_rdy_i && cmd_rd && cmd_fifo_rdy  )
+            begin
+               next_state = READ;
+               push_cmd = 1'b1;
+               rdp_valid = 1'b1;
+               wdp_valid = 1'b0;
+               xfer_cmd = 1'b1;
+              // tstpointA    = 4'b0101;
+               
+            end   
+          else if (cmd_fifo_rdy && cmd_wr && wdp_rdy_i )
+             begin
+               next_state = WRITE;
+               push_cmd = 1'b1;
+               xfer_cmd = 1'b1;
+               
+               wdp_valid     = 1'b1;
+               wdp_validB    = 1'b1;
+               wdp_validC    = 1'b1;
+               
+             //   tstpointA    = 4'b0110;
+              
+             end
+            
+          else if (cmd_fifo_rdy && cmd_others)
+             begin
+               push_cmd = 1'b1;
+               xfer_cmd = 1'b1;
+             end
+          else if (!cmd_fifo_rdy)
+
+             begin
+               next_state = CMD_WAIT;
+               tstpointA    = 4'b1001;
+               
+             end  
+          else
+               next_state = READ; 
+ 
+ 
+               
+          if (cmd_fifo_rdy && ((rdp_rdy_i && cmd_rd) || (wdp_rdy_i && cmd_wr) || (cmd_others)))
+              cmd_rdy = 1'b1;
+         else 
+              cmd_rdy = 1'b0;
+          
+         
+   
+          end
+   READ:  begin
+   
+         if (rdp_rdy_i && cmd_rd && cmd_fifo_rdy  )
+            begin
+               next_state = READ;
+               push_cmd = 1'b1;
+               rdp_valid = 1'b1;
+               wdp_valid = 1'b0;
+               xfer_cmd = 1'b1;
+               tstpointA    = 4'b0101;
+               
+            end   
+          else if (cmd_fifo_rdy && cmd_wr && wdp_rdy_i )
+             begin
+               next_state = WRITE;
+               push_cmd = 1'b1;
+               xfer_cmd = 1'b1;
+               
+               wdp_valid     = 1'b1;
+               wdp_validB    = 1'b1;
+               wdp_validC    = 1'b1;
+               
+                tstpointA    = 4'b0110;
+              
+             end
+            
+         else if (!rdp_rdy_i )
+            begin
+               next_state = READ; 
+               push_cmd  = 1'b0;
+                 xfer_cmd  = 1'b0;
+              
+               tstpointA    = 4'b0111;
+              
+               wdp_valid = 1'b0;
+               wdp_validB = 1'b0;
+               wdp_validC    = 1'b0;
+               rdp_valid = 1'b0;
+            end                       
+          else if (last_word_rd_i && cmd_others && cmd_fifo_rdy )
+
+             begin
+               next_state = REFRESH_ST;
+               push_cmd = 1'b1;
+               xfer_cmd = 1'b1;
+               wdp_valid = 1'b0;
+               wdp_validB = 1'b0;
+               wdp_validC    = 1'b0;
+               rdp_valid = 1'b0;
+               tstpointA    = 4'b1000;
+              
+             end
+          else if (!cmd_fifo_rdy || !wdp_rdy_i)
+
+             begin
+               next_state = CMD_WAIT;
+               tstpointA    = 4'b1001;
+               
+             end  
+          else
+               next_state = READ; 
+ 
+ 
+               
+          if ((rdp_rdy_i && cmd_rd || cmd_wr && wdp_rdy_i || cmd_others) && cmd_fifo_rdy)
+             cmd_rdy = wait_done;//1'b1;
+         else 
+              cmd_rdy = 1'b0;
+          
+        
+        end
+   WRITE: begin  // for write, always wait until the last_word_wr 
+         if (cmd_fifo_rdy &&  cmd_rd && rdp_rdy_i && last_word_wr_i)
+               begin
+               next_state = READ;
+               push_cmd = 1'b1;
+               xfer_cmd = 1'b1;
+               rdp_valid     = 1'b1;
+               tstpointA    = 4'b0000;
+               end
+          else if (!wdp_rdy_i || (wdp_rdy_i && cmd_wr && cmd_fifo_rdy && last_word_wr_i) )
+               begin
+               next_state = WRITE;
+               tstpointA    = 4'b0001;
+               
+               if (cmd_wr && last_word_wr_i) begin
+                  wdp_valid     = 1'b1;
+                  wdp_validB = 1'b1;
+                  wdp_validC    = 1'b1;
+                  
+               end
+               else begin
+                  wdp_valid     = 1'b0;
+                  wdp_validB = 1'b0;
+               wdp_validC    = 1'b0;
+                  
+               end
+               
+               if (last_word_wr_i ) begin
+                  push_cmd = 1'b1;
+                  xfer_cmd = 1'b1;
+               end
+               else begin
+                  push_cmd = 1'b0;
+                  xfer_cmd = 1'b0;
+               end
+                             
+               end
+          else if (last_word_wr_i && cmd_others && cmd_fifo_rdy)
+             begin
+               next_state = REFRESH_ST;
+               push_cmd = 1'b1;
+               xfer_cmd = 1'b1;
+               tstpointA    = 4'b0010;
+               
+               wdp_valid = 1'b0;
+               wdp_validB = 1'b0;
+               wdp_validC    = 1'b0;
+               
+               rdp_valid = 1'b0;
+               
+             end
+               
+          else if (!cmd_fifo_rdy && last_word_wr_i || !rdp_rdy_i || (!cmd_valid_i && wait_done) )
+
+               begin
+               next_state = CMD_WAIT;
+               push_cmd = 1'b0;
+               xfer_cmd = 1'b0;
+               tstpointA    = 4'b0011;
+               
+               end
+          
+          else begin
+                  next_state = WRITE;
+               tstpointA    = 4'b0100;
+                  
+               end
+
+         // need to include rdp_rdy_i to prevent sending read command if
+         // read_data_port fifo is full in MCB
+   if (last_word_wr_i && (cmd_others || rdp_rdy_i && cmd_rd || cmd_wr && wdp_rdy_i) && cmd_fifo_rdy)
+             cmd_rdy = wait_done;//1'b1;
+         else 
+             cmd_rdy = 1'b0;
+         
+              
+         end
+   
+   
+   
+
+   
+   CMD_WAIT: if (!cmd_fifo_rdy || wr_in_progress)
+               begin
+               next_state = CMD_WAIT;
+               cmd_rdy = 1'b0;
+               tstpointA    = 4'b1010;
+               
+               end
+             else if (cmd_fifo_rdy && rdp_rdy_i && cmd_rd)
+               begin
+               next_state = READ;
+               push_cmd = 1'b1;
+               xfer_cmd = 1'b1;
+               cmd_rdy = 1'b1;
+               rdp_valid     = 1'b1;
+               
+               tstpointA    = 4'b1011;
+               end
+             else if (cmd_fifo_rdy  && cmd_wr && (wait_done || cmd_wr_pending_r1))
+
+               begin
+               next_state = WRITE;
+               push_cmd = 1'b1;
+               xfer_cmd = 1'b1;                                   
+               wdp_valid     = 1'b1;
+               wdp_validB = 1'b1;
+               wdp_validC    = 1'b1;
+               
+               cmd_rdy = 1'b1;
+               tstpointA    = 4'b1100;
+               
+               end
+             else if (cmd_fifo_rdy &&  cmd_others)
+               begin
+               next_state = REFRESH_ST;
+               push_cmd = 1'b1;  /////////////////
+               xfer_cmd = 1'b1;   
+               tstpointA    = 4'b1101;
+               cmd_rdy = 1'b1;
+               
+               end
+             else
+               begin
+               next_state = CMD_WAIT;
+               tstpointA    = 4'b1110;
+               
+               if ((wdp_rdy_i && rdp_rdy_i))
+                  cmd_rdy = 1'b1;
+               else
+                  cmd_rdy = 1'b0;
+                  
+                  
+               end
+     
+               
+   default:
+          begin
+           push_cmd = 1'b0;
+           xfer_cmd = 1'b0;
+           
+           wdp_valid = 1'b0;
+           wdp_validB = 1'b0;
+           wdp_validC    = 1'b0;
+           next_state = READY;              
+         //  cmd_rdy = 1'b0;
+                    
+                         
+
+         end
+   
+ endcase
+ end
+   
+endmodule 

Frogwells_fpga_design/基于FPGA、DDR3和USB2.0的图像采集系统/debug/ddr_test/rtl/traffic_gen/mcb_traffic_gen.v

@@ -0,0 +1,756 @@
+//*****************************************************************************
+// (c) Copyright 2008-2009 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+//*****************************************************************************
+//   ____  ____
+//  /   /\/   /
+// /___/  \  /    Vendor: Xilinx
+// \   \   \/     Version: %version
+//  \   \         Application: MEMC
+//  /   /         Filename: mcb_traffic_gen.v
+// /___/   /\     Date Last Modified: $Date:
+// \   \  /  \    Date Created:
+//  \___\/\___\
+//
+//Device: Spartan6/Virtex6
+//Design Name: mcb_traffic_gen
+//Purpose: This is top level module of memory traffic generator which can
+//         generate different CMD_PATTERN and DATA_PATTERN to Spartan 6
+//         hard memory controller core.
+//Reference:
+//Revision History:     1.1      Brought out internal signals cmp_data and cmp_error as outputs.
+//                      1.2    7/1/2009  Added EYE_TEST parameter for signal SI probing.
+//                      1.3    10/1/2009 Added dq_error_bytelane_cmp,cumlative_dq_lane_error signals for V6.
+//                                       Any comparison error on user read data bus are mapped back to 
+//                                       dq bus.  The cumulative_dq_lane_error accumulate any errors on
+//                                       DQ bus. And the dq_error_bytelane_cmp shows error during current 
+//                                       command cycle. The error can be cleared by input signal "manual_clear_error".
+//                      1.4    04/10/2010 Removed local generated version of  mcb_rd_empty and mcb_wr_full in TG.
+//                      1.5    05/19/2010 If MEM_BURST_LEN value is passed with value of zero, it is treated as
+//                                        "OTF" Burst Mode and TG will only generate BL 8 traffic.
+
+//*****************************************************************************
+`timescale 1ps/1ps
+
+module mcb_traffic_gen #
+  (
+   parameter TCQ           = 100,            // SIMULATION tCQ delay.
+   parameter FAMILY        = "SPARTAN6",     // "VIRTEX6", "SPARTAN6"
+   parameter SIMULATION    = "FALSE",
+   parameter MEM_BURST_LEN = 8,               // For VIRTEX6 Only in this traffic gen.
+                                              // This traffic gen doesn't support DDR3 OTF Burst mode.
+
+   parameter PORT_MODE     = "BI_MODE",       // SPARTAN6: "BI_MODE", "WR_MODE", "RD_MODE"
+                                              // VIRTEX6: "BI_MODE"
+   parameter DATA_PATTERN  = "DGEN_ALL", // "DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"
+   parameter CMD_PATTERN   = "CGEN_ALL",     // "CGEN_RPBS","CGEN_FIXED",  "CGEN_BRAM", "CGEN_SEQUENTIAL", "CGEN_ALL",
+
+   parameter ADDR_WIDTH    = 30,             // Spartan 6 Addr width is 30
+
+   parameter CMP_DATA_PIPE_STAGES = 0,       // parameter for MPMC, it should always set to 0
+
+   // memory type specific
+   parameter MEM_COL_WIDTH = 10,             // memory column width
+   parameter NUM_DQ_PINS   = 16,             // Spartan 6 Options: 4,8,16;
+                                             // Virtex 6 DDR2/DDR3 Options: 8,16,24,32,.....144
+   parameter DQ_ERROR_WIDTH = 1,
+
+   parameter SEL_VICTIM_LINE = 3,            // SEL_VICTIM_LINE LINE is one of the DQ pins is selected to be different than hammer pattern
+                                             // SEL_VICTIM_LINE is only for V6.
+                                             // Virtex 6 option: 8,9,16,17,32,36,64,72
+   parameter DWIDTH        = 32,             //NUM_DQ_PINS*4,         // Spartan 6 Options: 32,64,128;
+                                             // Virtex 6 Always: 4* NUM_DQ_PINS
+
+
+   // the following parameter is to limit the range of generated PRBS Address
+   //
+   //      e.g PRBS_SADDR_MASK_POS = 32'h0000_7000   the bit 14:12 of PRBS_SADDR will be ORed with
+   //          PRBS_SADDR          = 32'h0000_5000   the LFSR[14:12] to add the starting address offset.
+
+   //          PRBS_EADDR          = 32'h0000_7fff
+   //          PRBS_EADDR_MASK_POS = 32'hffff_7000 => mark all the leading 0's in PRBS_EADDR to 1 to
+   //                                                 zero out the LFSR[31:15]
+
+   parameter PRBS_EADDR_MASK_POS = 32'hFFFFD000,
+   parameter PRBS_SADDR_MASK_POS =  32'h00002000,
+   parameter PRBS_EADDR = 32'h00002000,
+   parameter PRBS_SADDR = 32'h00005000,
+   parameter EYE_TEST   = "FALSE"  // set EYE_TEST = "TRUE" to probe memory signals.
+                                   // Traffic Generator will only write to one single location and no
+                                   // read transactions will be generated.
+
+
+ )
+
+ (
+
+   input                    clk_i,
+   input                    rst_i,
+   input                    run_traffic_i,
+   input                    manual_clear_error,
+  // *** runtime parameter ***
+   input [31:0]             start_addr_i,   // define the start of address
+   input [31:0]             end_addr_i,     // define upper limit addressboundary
+   input [31:0]             cmd_seed_i,     // seed for cmd PRBS generators
+   input [31:0]             data_seed_i,    // data seed will be added to generated address
+                                            // for PRBS data generation
+    // seed for cmd PRBS generators
+   input                    load_seed_i,   //  when asserted the cmd_seed and data_seed inputs will be registered.
+
+   // upper layer inputs to determine the command bus and data pattern
+   // internal traffic generator initialize the memory with
+   input [2:0]              addr_mode_i,  // "00" = bram; takes the address from bram interface
+                                          // "01" = fixed address from the fixed_addr input
+                                          // "10" = psuedo ramdom pattern; generated from internal 64 bit LFSR
+                                          // "11" = sequential
+
+
+  // for each instr_mode, traffic gen fill up with a predetermined pattern before starting the instr_pattern that defined
+  // in the instr_mode input. The runtime mode will be automatically loaded inside when it is in
+   input [3:0]              instr_mode_i, // "0000" = Fixed
+                                          // "0001" = bram; takes instruction from bram output
+                                          // "0010" = R/W
+                                          // "0011" = RP/WP
+                                          // "0100" = R/RP/W/WP
+                                          // "0101" = R/RP/W/WP/REF
+                                          // "0110" = PRBS
+
+
+   input [1:0]              bl_mode_i,    // "00" = bram;   takes the burst length from bram output
+                                          // "01" = fixed , takes the burst length from the fixed_bl input
+                                          // "10" = psuedo ramdom pattern; generated from internal 16 bit LFSR
+
+   input [3:0]              data_mode_i,   // "000" = address as data
+                                           // "001" = hammer
+                                           // "010" = neighbour
+                                           // "011" = prbs
+                                           // "100" = walking 0's
+                                           // "101" = walking 1's
+                                           // "110" =
+                                           // "111" =
+
+   input                    mode_load_i,
+
+   // fixed pattern inputs interface
+   input [5:0]              fixed_bl_i,      // range from 1 to 64
+   input [2:0]              fixed_instr_i,   //RD              3'b001
+                                             //RDP             3'b011
+                                             //WR              3'b000
+                                             //WRP             3'b010
+                                             //REFRESH         3'b100
+
+
+   input [31:0]             fixed_addr_i,       // only upper 30 bits will be used
+   input [DWIDTH-1:0]       fixed_data_i, // 
+
+   // BRAM interface.
+                                          //   bram bus formats:
+                                          //   Only SP6 has been tested.
+   input [38:0]             bram_cmd_i,   //  {{bl}, {cmd}, {address[28:2]}}
+   input                    bram_valid_i,
+   output                   bram_rdy_o,  //
+
+   /////////////////////////////////////////////////////////////////////////////
+   //  MCB INTERFACE
+   // interface to mcb command port
+   output                   mcb_cmd_en_o,
+   output [2:0]             mcb_cmd_instr_o,
+   output [ADDR_WIDTH-1:0]  mcb_cmd_addr_o,
+   output [5:0]             mcb_cmd_bl_o,      // this output is for Spartan 6
+
+   input                    mcb_cmd_full_i,
+
+   // interface to mcb wr data port
+   output                   mcb_wr_en_o,
+   output [DWIDTH-1:0]      mcb_wr_data_o,
+   output                   mcb_wr_data_end_o,
+   output [(DWIDTH/8) - 1:0]  mcb_wr_mask_o,
+
+   input                    mcb_wr_full_i,
+   input [6:0]              mcb_wr_fifo_counts,
+
+   // interface to mcb rd data port
+   output                   mcb_rd_en_o,
+   input [DWIDTH-1:0]       mcb_rd_data_i,
+   input                    mcb_rd_empty_i,
+   input [6:0]              mcb_rd_fifo_counts,
+   /////////////////////////////////////////////////////////////////////////////
+   // status feedback
+   input                    counts_rst,
+   output reg [47:0]        wr_data_counts,
+   output reg [47:0]        rd_data_counts,
+   output                   cmp_error,
+   output                   cmp_data_valid,
+   output                   error,       // asserted whenever the read back data is not correct.
+   output  [64 + (2*DWIDTH - 1):0]            error_status ,// TBD how signals mapped
+   output [DWIDTH-1:0]      cmp_data,
+   output [DWIDTH-1:0]      mem_rd_data,
+   
+   
+   // **** V6 Signals
+   output [DQ_ERROR_WIDTH - 1:0] dq_error_bytelane_cmp,   // V6: real time compare error byte lane
+   output [DQ_ERROR_WIDTH - 1:0] cumlative_dq_lane_error  // V6: latched error byte lane that occure on
+                                                       //     first error
+   
+
+
+  );
+
+localparam MEM_BLEN =  (MEM_BURST_LEN == 4) ? 4 :
+                       (MEM_BURST_LEN == 8) ? 8 :
+                        8;
+
+   wire [DWIDTH-1:0]        rdpath_rd_data_i;
+   wire                     rdpath_data_valid_i;
+   wire                     mcb_wr_en;
+   wire                     cmd2flow_valid;
+   wire [2:0]               cmd2flow_cmd;
+   wire [31:0]              cmd2flow_addr;
+   wire [5:0]               cmd2flow_bl;
+   wire                     last_word_rd;
+   wire                     last_word_wr;
+   wire                     flow2cmd_rdy;
+   wire [31:0]              wr_addr;
+   wire [31:0]              rd_addr;
+   wire [5:0]               wr_bl;
+   wire [5:0]               rd_bl;
+   reg                      run_traffic_reg;
+wire wr_validB, wr_valid,wr_validC;
+wire [31:0] bram_addr_i;
+wire [2:0] bram_instr_i;
+wire [5:0] bram_bl_i;
+reg AC2_G_E2,AC1_G_E1,AC3_G_E3;
+reg upper_end_matched;
+reg [7:0] end_boundary_addr;
+reg lower_end_matched;
+wire [31:0] addr_o;
+wire [31:0] m_addr;
+wire dcount_rst;
+wire [31:0] rd_addr_error;
+wire rd_rdy;
+//wire cmp_error;
+wire  cmd_full;
+wire rd_mdata_fifo_rd_en;
+wire rd_mdata_fifo_empty;
+wire rd_mdata_fifo_afull;
+wire [DWIDTH-1:0] rd_v6_mdata;
+
+//
+wire [31:0]       cmp_addr;
+wire [5:0]       cmp_bl;
+// synthesis attribute keep of rst_ra is "true";
+// synthesis attribute keep of rst_rb is "true";
+
+reg [9:0]         rst_ra,rst_rb;
+// synthesis attribute keep of mcb_wr_full_r1 is "true";
+// synthesis attribute keep of mcb_wr_full_r2 is "true";
+
+reg mcb_wr_full_r1,mcb_wr_full_r2;
+reg mcb_rd_empty_r;
+wire force_wrcmd_gen;
+wire [6:0] rd_buff_avail;
+
+reg [3:0] data_mode_r_a;
+reg [3:0] data_mode_r_b;
+reg [3:0] data_mode_r_c;
+reg        rd_mdata_afull_set;
+reg error_access_range = 1'b0;
+  //synthesis translate_off
+
+  initial begin
+    if((MEM_BURST_LEN !== 4) && (MEM_BURST_LEN !== 8)) begin
+      $display("Current Traffic Generator logic does not support OTF (On The Fly) Burst Mode!");
+      $display("If memory is set to OTF (On The Fly) , Traffic Generator only generates BL8 traffic");
+      
+    end
+  end
+
+always @ (mcb_cmd_en_o,mcb_cmd_addr_o,mcb_cmd_bl_o,end_addr_i)
+
+if (mcb_cmd_en_o && (mcb_cmd_addr_o + mcb_cmd_bl_o * (DWIDTH/8)) > end_addr_i[ADDR_WIDTH-1:0])
+   begin
+   $display("Error ! Data access beyond address range");
+   error_access_range = 1'b1;
+   $stop;
+   end
+
+  //synthesis translate_on
+
+wire mcb_rd_empty;
+assign     mcb_rd_empty = mcb_rd_empty_i;
+
+
+
+
+wire mcb_wr_full;
+assign     mcb_wr_full = mcb_wr_full_i;
+
+
+always @ (posedge clk_i)
+begin
+    data_mode_r_a <= #TCQ data_mode_i;
+    data_mode_r_b <= #TCQ data_mode_i;
+    data_mode_r_c <= #TCQ data_mode_i;
+end
+always @ (posedge clk_i)
+begin
+if (rst_ra[0])
+    mcb_wr_full_r1 <= #TCQ 1'b0;
+else if (mcb_wr_fifo_counts >= 63) begin
+    mcb_wr_full_r1 <= #TCQ 1'b1;
+    mcb_wr_full_r2 <= #TCQ 1'b1;
+    end
+else begin
+    mcb_wr_full_r1 <= #TCQ 1'b0;
+    mcb_wr_full_r2 <= #TCQ 1'b0;
+    end
+end
+
+
+always @ (posedge clk_i)
+begin
+if (rst_ra[0])
+    mcb_rd_empty_r <= #TCQ 1'b1;
+
+else if (mcb_rd_fifo_counts <= 1)
+    mcb_rd_empty_r <= #TCQ 1'b1;
+else
+    mcb_rd_empty_r <= #TCQ 1'b0;
+end
+
+
+
+// synthesis attribute MAX_FANOUT of rst_ra is 20;
+// synthesis attribute MAX_FANOUT of rst_rb is 20;
+
+
+//reg GSR = 1'b0;
+   always @(posedge clk_i)
+   begin
+         rst_ra <= #TCQ {rst_i,rst_i,rst_i,rst_i,rst_i,rst_i,rst_i,rst_i,rst_i,rst_i};
+         rst_rb <= #TCQ {rst_i,rst_i,rst_i,rst_i,rst_i,rst_i,rst_i,rst_i,rst_i,rst_i};
+
+   end
+   // register it . Just in case the calling modules didn't syn with clk_i
+   always @(posedge clk_i)
+   begin
+       run_traffic_reg <= #TCQ run_traffic_i;
+   end
+
+   assign bram_addr_i = {bram_cmd_i[29:0],2'b00};
+   assign bram_instr_i = bram_cmd_i[32:30];
+   assign bram_bl_i[5:0] = bram_cmd_i[38:33];
+
+
+//
+//
+assign dcount_rst = counts_rst | rst_ra[0];
+always @ (posedge clk_i)
+begin
+  if (dcount_rst)
+      wr_data_counts <= #TCQ 'b0;
+  else if (mcb_wr_en)
+      wr_data_counts <= #TCQ wr_data_counts + DWIDTH/8;
+
+end
+
+always @ (posedge clk_i)
+begin
+  if (dcount_rst)
+      rd_data_counts <= #TCQ 'b0;
+  else if (mcb_rd_en_o)
+      rd_data_counts <= #TCQ rd_data_counts + DWIDTH/8;
+
+end
+
+
+
+// ****  for debug
+// this part of logic is to check there are no commands been duplicated or dropped
+// in the cmd_flow_control logic
+generate
+if (SIMULATION == "TRUE") begin: cmd_check
+reg fifo_error;
+wire [31:0] xfer_addr;
+wire cmd_fifo_rd;
+
+assign cmd_fifo_wr =  flow2cmd_rdy & cmd2flow_valid;
+
+always @ (posedge clk_i)
+begin
+if ( mcb_cmd_en_o)
+   if ( xfer_addr != mcb_cmd_addr_o)
+      fifo_error <= #TCQ 1'b1;
+   else
+      fifo_error <= #TCQ 1'b0;
+
+end
+
+wire cmd_fifo_empty;
+assign cmd_fifo_rd = mcb_cmd_en_o & ~mcb_cmd_full_i & ~cmd_fifo_empty;
+
+  afifo #
+   (.TCQ           (TCQ),
+    .DSIZE         (38),
+    .FIFO_DEPTH    (16),
+    .ASIZE         (4),
+    .SYNC          (1)  // set the SYNC to 1 because rd_clk = wr_clk to reduce latency
+
+
+   )
+   cmd_fifo
+   (
+    .wr_clk        (clk_i),
+    .rst           (rst_ra[0]),
+    .wr_en         (cmd_fifo_wr),
+    .wr_data       ({cmd2flow_bl,cmd2flow_addr}),
+    .rd_en         (cmd_fifo_rd),
+    .rd_clk        (clk_i),
+    .rd_data       ({xfer_cmd_bl,xfer_addr}),
+    .full          (cmd_fifo_full),
+    .empty         (cmd_fifo_empty)
+
+   );
+
+
+end
+endgenerate
+
+reg [31:0] end_addr_r;
+ always @ (posedge clk_i)
+    end_addr_r <= end_addr_i;
+
+
+   cmd_gen
+     #(
+       .TCQ                 (TCQ),
+       .FAMILY               (FAMILY)     ,
+       .MEM_BURST_LEN     (MEM_BLEN),
+       .PORT_MODE            (PORT_MODE),
+       
+       .NUM_DQ_PINS          (NUM_DQ_PINS),
+       .DATA_PATTERN         (DATA_PATTERN),
+       .CMD_PATTERN          (CMD_PATTERN),
+       .ADDR_WIDTH            (ADDR_WIDTH),
+       .DWIDTH               (DWIDTH),
+       .MEM_COL_WIDTH  (MEM_COL_WIDTH),
+       .PRBS_EADDR_MASK_POS          (PRBS_EADDR_MASK_POS ),
+       .PRBS_SADDR_MASK_POS           (PRBS_SADDR_MASK_POS  ),
+       .PRBS_EADDR         (PRBS_EADDR),
+       .PRBS_SADDR          (PRBS_SADDR )
+
+       )
+   u_c_gen
+     (
+      .clk_i              (clk_i),
+      .rst_i               (rst_ra),
+      .rd_buff_avail_i        (rd_buff_avail),
+      .reading_rd_data_i (mcb_rd_en_o),
+      .force_wrcmd_gen_i (force_wrcmd_gen),
+      .run_traffic_i    (run_traffic_reg),
+      .start_addr_i     (start_addr_i),
+      .end_addr_i       (end_addr_r),
+      .cmd_seed_i       (cmd_seed_i),
+      .data_seed_i      (data_seed_i),
+      .load_seed_i      (load_seed_i),
+      .addr_mode_i      (addr_mode_i),
+      .data_mode_i        (data_mode_r_a),
+
+      .instr_mode_i     (instr_mode_i),
+      .bl_mode_i        (bl_mode_i),
+      .mode_load_i      (mode_load_i),
+   // fixed pattern inputs interface
+      .fixed_bl_i       (fixed_bl_i),
+      .fixed_addr_i     (fixed_addr_i),
+      .fixed_instr_i    (fixed_instr_i),
+   // BRAM FIFO input : Holist vector inputs
+
+      .bram_addr_i      (bram_addr_i),
+      .bram_instr_i     (bram_instr_i ),
+      .bram_bl_i        (bram_bl_i ),
+      .bram_valid_i     (bram_valid_i ),
+      .bram_rdy_o       (bram_rdy_o   ),
+
+      .rdy_i            (flow2cmd_rdy),
+      .instr_o          (cmd2flow_cmd),
+      .addr_o           (cmd2flow_addr),
+      .bl_o             (cmd2flow_bl),
+//      .m_addr_o         (m_addr),
+      .cmd_o_vld        (cmd2flow_valid)
+
+      );
+
+assign mcb_cmd_addr_o = addr_o[ADDR_WIDTH-1:0];
+
+
+
+assign cmd_full = mcb_cmd_full_i;
+   mcb_flow_control #
+     (
+       .TCQ           (TCQ),
+       .FAMILY  (FAMILY)
+       
+     )
+   mcb_control
+     (
+      .clk_i            (clk_i),
+      .rst_i            (rst_ra),
+
+      .cmd_rdy_o        (flow2cmd_rdy),
+      .cmd_valid_i      (cmd2flow_valid),
+      .cmd_i            (cmd2flow_cmd),
+      .addr_i           (cmd2flow_addr),
+      .bl_i             (cmd2flow_bl),
+      // interface to mcb_cmd port
+      .mcb_cmd_full        (cmd_full),// (~rd_rdy ), // mcb_cmd_full
+//      .mcb_cmd_empty        ( ),
+      .cmd_o                 (mcb_cmd_instr_o),
+      .addr_o                (addr_o),//(mcb_cmd_instr_o),
+      .bl_o                  (mcb_cmd_bl_o),
+      .cmd_en_o              (mcb_cmd_en_o),//(mcb_cmd_bl_o),
+   // interface to write data path module
+
+      .last_word_wr_i         (last_word_wr),
+      .wdp_rdy_i            (wr_rdy),//(wr_rdy),
+      .wdp_valid_o          (wr_valid),
+      .wdp_validB_o         (wr_validB),
+      .wdp_validC_o         (wr_validC),
+
+      .wr_addr_o            (wr_addr),
+      .wr_bl_o              (wr_bl),
+   // interface to read data path module
+
+      .last_word_rd_i         (last_word_rd),
+      .rdp_rdy_i            (rd_rdy),// (rd_rdy),
+      .rdp_valid_o           (rd_valid),
+      .rd_addr_o            (rd_addr),
+      .rd_bl_o              (rd_bl)
+
+      );
+
+
+   afifo #
+   (
+   
+    .TCQ           (TCQ),
+    .DSIZE         (DWIDTH),
+    .FIFO_DEPTH    (32),
+    .ASIZE         (5),
+    .SYNC          (1)  // set the SYNC to 1 because rd_clk = wr_clk to reduce latency 
+   
+   
+   )
+   rd_mdata_fifo
+   (
+    .wr_clk        (clk_i),
+    .rst           (rst_rb[0]),
+    .wr_en         (!mcb_rd_empty),
+    .wr_data       (mcb_rd_data_i),
+    .rd_en         (mcb_rd_en_o),
+    .rd_clk        (clk_i),
+    .rd_data       (rd_v6_mdata),
+    .full          (),
+    .almost_full   (rd_mdata_fifo_afull),
+    .empty         (rd_mdata_fifo_empty)
+   
+   );
+
+
+wire cmd_rd_en;
+
+always @ (posedge clk_i)
+begin
+if (rst_rb[0])
+   rd_mdata_afull_set <= #TCQ 1'b0;
+else if (rd_mdata_fifo_afull)
+   rd_mdata_afull_set <= #TCQ 1'b1;
+end
+assign cmd_rd_en = ~mcb_cmd_full_i & mcb_cmd_en_o;
+
+
+assign rdpath_data_valid_i =(FAMILY == "VIRTEX6" && MEM_BLEN == 4) ? (!rd_mdata_fifo_empty & rd_mdata_afull_set) :!mcb_rd_empty ;
+assign rdpath_rd_data_i =(FAMILY == "VIRTEX6" && MEM_BLEN == 4) ? rd_v6_mdata : mcb_rd_data_i ;
+
+generate
+if (PORT_MODE == "RD_MODE" || PORT_MODE == "BI_MODE")  begin : RD_PATH
+   read_data_path
+     #(
+       .TCQ           (TCQ),
+       .FAMILY            (FAMILY)  ,
+       .MEM_BURST_LEN     (MEM_BLEN),
+
+       .CMP_DATA_PIPE_STAGES (CMP_DATA_PIPE_STAGES),
+       .ADDR_WIDTH        (ADDR_WIDTH),
+       .SEL_VICTIM_LINE   (SEL_VICTIM_LINE),
+       .DATA_PATTERN      (DATA_PATTERN),
+       .DWIDTH            (DWIDTH),
+       .NUM_DQ_PINS       (NUM_DQ_PINS),
+       .DQ_ERROR_WIDTH    (DQ_ERROR_WIDTH),
+       .MEM_COL_WIDTH     (MEM_COL_WIDTH)
+
+       )
+   read_data_path
+     (
+      .clk_i              (clk_i),
+      .rst_i              (rst_rb),
+      .manual_clear_error (manual_clear_error),
+      .cmd_rdy_o          (rd_rdy),
+      .cmd_valid_i        (rd_valid),
+      .prbs_fseed_i         (data_seed_i),
+      .cmd_sent                 (mcb_cmd_instr_o),
+      .bl_sent                  (mcb_cmd_bl_o),
+      .cmd_en_i              (cmd_rd_en),
+
+      .data_mode_i        (data_mode_r_b),
+      .last_word_rd_o         (last_word_rd),
+//      .m_addr_i               (m_addr),
+      .fixed_data_i         (fixed_data_i),
+
+      .addr_i                 (rd_addr),
+      .bl_i                   (rd_bl),
+      .data_rdy_o             (mcb_rd_en_o),
+      
+      .data_valid_i           (rdpath_data_valid_i),
+      .data_i                 (rdpath_rd_data_i), 
+      
+      
+      .data_error_o           (cmp_error),
+      .cmp_data_valid         (cmp_data_valid),
+      .cmp_data_o             (cmp_data),
+      .rd_mdata_o             (mem_rd_data ),
+      .cmp_addr_o             (cmp_addr),
+      .cmp_bl_o               (cmp_bl),
+      .force_wrcmd_gen_o      (force_wrcmd_gen),
+      .rd_buff_avail_o        (rd_buff_avail),
+      .dq_error_bytelane_cmp     (dq_error_bytelane_cmp),
+      .cumlative_dq_lane_error_r   (cumlative_dq_lane_error)
+
+      );
+
+end
+else begin: WR_ONLY_PATH
+
+   assign cmp_error = 1'b0;
+end   
+endgenerate
+
+
+
+
+
+generate
+if (PORT_MODE == "WR_MODE" || PORT_MODE == "BI_MODE") begin : WR_PATH
+
+   write_data_path
+     #(
+     
+       .TCQ           (TCQ),
+       .FAMILY  (FAMILY),
+       .MEM_BURST_LEN     (MEM_BLEN),
+       .ADDR_WIDTH        (ADDR_WIDTH),
+       .DATA_PATTERN      (DATA_PATTERN),
+       .DWIDTH            (DWIDTH),
+       .NUM_DQ_PINS       (NUM_DQ_PINS),
+       .SEL_VICTIM_LINE   (SEL_VICTIM_LINE),
+       .MEM_COL_WIDTH     (MEM_COL_WIDTH),
+       .EYE_TEST          (EYE_TEST)
+
+       )
+   write_data_path
+     (
+      .clk_i(clk_i),
+      .rst_i            (rst_rb),
+      .cmd_rdy_o            (wr_rdy),
+      .cmd_valid_i          (wr_valid),
+      .cmd_validB_i          (wr_validB),
+      .cmd_validC_i          (wr_validC),
+      .prbs_fseed_i         (data_seed_i),
+      .data_mode_i          (data_mode_r_c),
+      .last_word_wr_o       (last_word_wr),
+//      .m_addr_i             (m_addr),//(rd_addr),
+      .fixed_data_i         (fixed_data_i),
+      .addr_i               (wr_addr),
+      .bl_i                 (wr_bl),
+      .data_rdy_i           (!mcb_wr_full),
+      .data_valid_o         (mcb_wr_en),
+      .data_o               (mcb_wr_data_o),
+      .data_mask_o          (mcb_wr_mask_o),
+      .data_wr_end_o           (mcb_wr_data_end_o)
+      );
+   
+end
+endgenerate
+
+assign  mcb_wr_en_o = mcb_wr_en;
+
+
+
+   tg_status
+     #(
+     
+       .TCQ           (TCQ),
+       .DWIDTH            (DWIDTH)
+       )
+   tg_status
+     (
+      .clk_i              (clk_i),
+      .rst_i              (rst_ra[2]),
+      .manual_clear_error (manual_clear_error),
+      .data_error_i       (cmp_error),
+      .cmp_data_i         (cmp_data),
+      .rd_data_i          (mem_rd_data ),
+      .cmp_addr_i         (cmp_addr),
+      .cmp_bl_i           (cmp_bl),
+      .mcb_cmd_full_i     (mcb_cmd_full_i),
+      .mcb_wr_full_i      (mcb_wr_full),           // mcb_wr_full_r2 ???
+      .mcb_rd_empty_i     (mcb_rd_empty),
+      .error_status       (error_status),
+      .error              (error)
+      );
+
+
+endmodule // mcb_traffic_gen

Frogwells_fpga_design/基于FPGA、DDR3和USB2.0的图像采集系统/debug/ddr_test/rtl/traffic_gen/rd_data_gen.v

@@ -0,0 +1,343 @@
+//*****************************************************************************
+// (c) Copyright 2008-2009 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+//*****************************************************************************
+//   ____  ____
+//  /   /\/   /
+// /___/  \  /    Vendor: Xilinx
+// \   \   \/     Version: %version
+//  \   \         Application: MIG
+//  /   /         Filename: rd_data_gen.v
+// /___/   /\     Date Last Modified: 
+// \   \  /  \    Date Created: 
+//  \___\/\___\
+//
+//Device: Spartan6
+//Design Name: DDR/DDR2/DDR3/LPDDR 
+//Purpose: This module has all the timing control for generating "compare data" 
+//         to compare the read data from memory.
+//Reference:
+//Revision History:
+//*****************************************************************************
+
+`timescale 1ps/1ps
+
+module rd_data_gen #
+   (
+   parameter TCQ           = 100,
+   parameter FAMILY = "SPARTAN6", // "SPARTAN6", "VIRTEX6"
+   parameter MEM_BURST_LEN = 8,
+
+   parameter ADDR_WIDTH = 32,
+   parameter BL_WIDTH = 6,
+   parameter DWIDTH = 32,
+   parameter DATA_PATTERN = "DGEN_ALL", //"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"  
+   parameter NUM_DQ_PINS   = 8,
+   parameter SEL_VICTIM_LINE = 3,  // VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
+   
+   parameter COLUMN_WIDTH = 10
+   
+ )
+ (
+   input   clk_i,                 //
+   input [4:0]  rst_i, 
+   input [31:0] prbs_fseed_i,
+   input [3:0]  data_mode_i,   // "00" = bram; 
+   
+   output  cmd_rdy_o,             // ready to receive command. It should assert when data_port is ready at the                                        // beginning and will be deasserted once see the cmd_valid_i is asserted. 
+                                  // And then it should reasserted when 
+                                  // it is generating the last_word.
+   input   cmd_valid_i,           // when both cmd_valid_i and cmd_rdy_o is high, the command  is valid.
+   output  last_word_o,   
+   
+//   input [ADDR_WIDTH-1:0] m_addr_i, // generated address used to determine data pattern.
+   input [DWIDTH-1:0] fixed_data_i,   
+   input [ADDR_WIDTH-1:0] addr_i, // generated address used to determine data pattern.
+   input [BL_WIDTH-1:0]   bl_i,   // generated burst length for control the burst data
+   output                 user_bl_cnt_is_1_o,
+   input   data_rdy_i,           // connect from mcb_wr_full when used as wr_data_gen in sp6
+                                 // connect from mcb_rd_empty when used as rd_data_gen in sp6
+                                 // connect from rd_data_valid in v6
+                                 // When both data_rdy and data_valid is asserted, the ouput data is valid.
+   output   reg data_valid_o,       // connect to wr_en or rd_en and is asserted whenever the 
+                                 // pattern is available.
+   output  [DWIDTH-1:0] data_o, // generated data pattern   
+   input  rd_mdata_en
+);  
+// 
+
+
+
+wire [31:0]       prbs_data; 
+reg              cmd_start;
+reg [31:0]        adata; 
+reg [31:0]        hdata; 
+reg [31:0]        ndata; 
+reg [31:0]        w1data; 
+reg [NUM_DQ_PINS*4-1:0]        v6_w1data; 
+
+reg [31:0]        w0data; 
+reg [DWIDTH-1:0] data;
+reg               cmd_rdy;
+reg               data_valid;
+reg [6:0]user_burst_cnt;
+reg       data_rdy_r1,data_rdy_r2;   
+reg       next_count_is_one;
+reg       cmd_valid_r1;
+reg [31:0] w3data;
+
+assign data_port_fifo_rdy = data_rdy_i;
+
+//assign cmd_start = cmd_valid_i & cmd_rdy ;
+always @ (posedge clk_i)
+begin
+      data_rdy_r1 <= #TCQ data_rdy_i;
+      data_rdy_r2 <= #TCQ data_rdy_r1;
+      cmd_valid_r1 <= #TCQ cmd_valid_i;
+end      
+
+always @ (posedge clk_i)
+begin
+if (user_burst_cnt == 2 && data_rdy_i)
+     next_count_is_one <= #TCQ 1'b1;
+else
+     next_count_is_one <= #TCQ 1'b0;
+end
+
+reg user_bl_cnt_is_1;
+assign user_bl_cnt_is_1_o = user_bl_cnt_is_1;
+always @ (posedge clk_i)
+begin
+if ((user_burst_cnt == 2 && data_port_fifo_rdy && FAMILY == "SPARTAN6")
+    || (user_burst_cnt == 2 && data_port_fifo_rdy &&  FAMILY == "VIRTEX6")
+   )
+
+     user_bl_cnt_is_1 <= #TCQ 1'b1;
+else
+     user_bl_cnt_is_1 <= #TCQ 1'b0;
+end
+
+
+reg cmd_start_b;
+always @(cmd_valid_i,cmd_valid_r1,cmd_rdy,user_bl_cnt_is_1,rd_mdata_en)
+begin
+   if (FAMILY == "SPARTAN6") begin
+       cmd_start = cmd_valid_i & cmd_rdy ;
+       cmd_start_b = cmd_valid_i & cmd_rdy ;
+       end
+   else if (MEM_BURST_LEN == 4 && FAMILY == "VIRTEX6")  begin
+       cmd_start =  rd_mdata_en;  //  need to wait for extra cycle for data coming out from rd_post_fifo in V6 interface
+       cmd_start_b =  rd_mdata_en;  //  need to wait for extra cycle for data coming out from rd_post_fifo in V6 interface
+           end
+   else if (MEM_BURST_LEN == 8 && FAMILY == "VIRTEX6")   begin
+       
+       cmd_start = (~cmd_valid_r1 & cmd_valid_i) | user_bl_cnt_is_1;  //  need to wait for extra cycle for data coming out from rd_post_fifo in V6 interface
+       cmd_start_b = (~cmd_valid_r1 & cmd_valid_i) | user_bl_cnt_is_1;  //  need to wait for extra cycle for data coming out from rd_post_fifo in V6 interface
+       end
+
+end
+
+
+// counter to count user burst length
+always @( posedge clk_i)
+begin
+  if ( rst_i[0] )
+    user_burst_cnt <= #TCQ   'd0;
+  else if(cmd_start)  begin
+       if (bl_i == 6'b000000)
+          user_burst_cnt <= #TCQ 7'b1000000;
+       else
+          user_burst_cnt <= #TCQ bl_i;
+      end
+  else if(data_port_fifo_rdy) 
+     if (user_burst_cnt != 6'd0)
+        user_burst_cnt <= #TCQ   user_burst_cnt - 1'b1;
+     else
+        user_burst_cnt <= #TCQ   'd0;
+        
+end
+
+reg u_bcount_2;
+always @ (posedge clk_i)
+begin
+if ((user_burst_cnt == 2  && data_rdy_i )|| (cmd_start && bl_i == 1))
+    u_bcount_2 <= #TCQ   1'b1;
+else if (last_word_o)
+    u_bcount_2 <= #TCQ   1'b0;
+end    
+
+assign  last_word_o = u_bcount_2 & data_rdy_i;
+
+
+
+
+// cmd_rdy_o assert when the dat fifo is not full and deassert once cmd_valid_i
+// is assert and reassert during the last data
+
+//data_valid_o logic
+
+
+
+assign cmd_rdy_o = cmd_rdy;
+
+always @( posedge clk_i)
+begin
+  if ( rst_i[0] )
+    cmd_rdy <= #TCQ   1'b1;
+  else if (cmd_start)
+       cmd_rdy <= #TCQ   1'b0;
+  else if  ((data_port_fifo_rdy && user_burst_cnt == 1)) 
+      cmd_rdy <= #TCQ   1'b1;
+  
+
+end
+
+
+
+always @ (posedge clk_i)
+begin
+  if (rst_i[0])  
+    data_valid <= #TCQ   'd0;
+  else if (user_burst_cnt == 6'd1 && data_port_fifo_rdy)
+    data_valid <= #TCQ   1'b0;
+  else if(( user_burst_cnt >= 6'd1) || cmd_start) 
+    data_valid <= #TCQ   1'b1;
+end
+
+
+always @ (data_valid, data_port_fifo_rdy)
+if (FAMILY == "SPARTAN6")
+    data_valid_o = data_valid;
+else
+    data_valid_o = data_port_fifo_rdy;
+
+
+
+generate
+if (FAMILY == "SPARTAN6") begin : SP6_DGEN
+sp6_data_gen #
+ 
+( 
+   .TCQ               (TCQ),
+   .ADDR_WIDTH      (32 ),
+   .BL_WIDTH        (BL_WIDTH       ),
+   .DWIDTH          (DWIDTH       ),
+   .DATA_PATTERN    (DATA_PATTERN  ),
+   .NUM_DQ_PINS      (NUM_DQ_PINS  ),
+   .COLUMN_WIDTH     (COLUMN_WIDTH)
+   
+ )
+ sp6_data_gen
+ (
+   .clk_i              (clk_i         ),        
+   .rst_i              (rst_i[1]         ), 
+   .data_rdy_i         (data_rdy_i    ),
+   .prbs_fseed_i       (prbs_fseed_i),
+   
+   .data_mode_i        (data_mode_i   ),  
+   .cmd_startA         (cmd_start    ),  
+   .cmd_startB         (cmd_start    ),   
+   .cmd_startC         (cmd_start    ),   
+   .cmd_startD         (cmd_start    ),   
+   .cmd_startE         (cmd_start    ),
+   .fixed_data_i         (fixed_data_i),
+   
+   .addr_i             (addr_i        ),       
+   .user_burst_cnt     (user_burst_cnt),
+   .fifo_rdy_i         (data_port_fifo_rdy    ),   
+   .data_o             (data_o        )  
+  );
+
+end
+endgenerate
+generate
+if (FAMILY == "VIRTEX6") begin : V6_DGEN
+v6_data_gen #
+ 
+(  
+   .TCQ               (TCQ),
+   .ADDR_WIDTH      (32 ),
+   .BL_WIDTH        (BL_WIDTH       ),    
+   .MEM_BURST_LEN   (MEM_BURST_LEN),
+   .DWIDTH          (DWIDTH       ),
+   .DATA_PATTERN    (DATA_PATTERN  ),
+   .NUM_DQ_PINS      (NUM_DQ_PINS  ),
+   .SEL_VICTIM_LINE   (SEL_VICTIM_LINE),
+   
+   .COLUMN_WIDTH     (COLUMN_WIDTH)
+   
+ )
+ v6_data_gen
+ (
+   .clk_i              (clk_i         ),        
+   .rst_i              (rst_i[1]      ),
+   .data_rdy_i         (data_rdy_i    ),
+   .prbs_fseed_i       (prbs_fseed_i),
+   
+   .data_mode_i        (data_mode_i   ),  
+   .cmd_startA         (cmd_start    ),  
+   .cmd_startB         (cmd_start    ),   
+   .cmd_startC         (cmd_start    ),   
+   .cmd_startD         (cmd_start    ),   
+   .cmd_startE         (cmd_start    ),   
+   .m_addr_i           (addr_i),//(m_addr_i        ),          
+   .fixed_data_i       (fixed_data_i),
+
+   .addr_i             (addr_i        ),       
+   .user_burst_cnt     (user_burst_cnt),
+   .fifo_rdy_i         (data_port_fifo_rdy    ),   
+   .data_o             (data_o        )
+  );
+
+end
+endgenerate
+
+
+
+
+
+endmodule 

Frogwells_fpga_design/基于FPGA、DDR3和USB2.0的图像采集系统/debug/ddr_test/rtl/traffic_gen/read_data_path.v

@@ -0,0 +1,513 @@
+//*****************************************************************************
+// (c) Copyright 2008-2009 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+//
+//*****************************************************************************
+//   ____  ____
+//  /   /\/   /
+// /___/  \  /    Vendor: Xilinx
+// \   \   \/     Version: %version
+//  \   \         Application: MIG
+//  /   /         Filename: read_data_path.v
+// /___/   /\     Date Last Modified: 
+// \   \  /  \    Date Created: 
+//  \___\/\___\
+//
+//Device: Spartan6
+//Design Name: DDR/DDR2/DDR3/LPDDR 
+//Purpose: This is top level of read path and also consist of comparison logic
+//         for read data. 
+//Reference:
+//Revision History:
+//*****************************************************************************
+
+`timescale 1ps/1ps
+
+module read_data_path #(
+   parameter TCQ           = 100,
+
+   parameter FAMILY = "VIRTEX6",
+   parameter MEM_BURST_LEN = 8,
+   parameter ADDR_WIDTH = 32,
+   parameter CMP_DATA_PIPE_STAGES = 3,
+   parameter DWIDTH = 32,
+   parameter DATA_PATTERN = "DGEN_ALL", //"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"  
+   parameter NUM_DQ_PINS   = 8,
+   parameter DQ_ERROR_WIDTH = 1,
+   parameter SEL_VICTIM_LINE = 3,  // VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
+   
+   parameter MEM_COL_WIDTH = 10
+   
+    )
+    (
+      
+   
+   input                  clk_i, 
+   input [9:0]                 rst_i,
+   input                  manual_clear_error,
+   output                 cmd_rdy_o, 
+   input                  cmd_valid_i, 
+   input [31:0]           prbs_fseed_i,
+   
+   input [3:0]            data_mode_i,
+   input [2:0]           cmd_sent, 
+   input [5:0]           bl_sent  ,
+   input                 cmd_en_i ,
+//   input [31:0]           m_addr_i, 
+   input [DWIDTH-1:0]     fixed_data_i,    
+   input [31:0]           addr_i, 
+   input [5:0]            bl_i,
+   
+   
+   output                 data_rdy_o, 
+   input                  data_valid_i,
+   input [DWIDTH-1:0]     data_i,
+   output                 last_word_rd_o,
+   output                 data_error_o,                  //data_error on user data bus side
+   output [DWIDTH-1:0]    cmp_data_o,
+   output [DWIDTH-1:0]    rd_mdata_o ,
+   output                 cmp_data_valid,
+   output [31:0]          cmp_addr_o,
+   output [5 :0]          cmp_bl_o,
+   output                 force_wrcmd_gen_o,
+   output [6:0]           rd_buff_avail_o,
+   output [DQ_ERROR_WIDTH - 1:0] dq_error_bytelane_cmp,   // V6: real time compare error byte lane
+   output  [DQ_ERROR_WIDTH - 1:0] cumlative_dq_lane_error_r  // V6: latched error byte lane that occure on
+                                                       //     first error
+    
+   );
+
+   wire                   gen_rdy; 
+   wire                   gen_valid; 
+   wire [31:0]  gen_addr; 
+   wire [5:0]    gen_bl;
+
+   wire                   cmp_rdy; 
+   wire                   cmp_valid; 
+   wire [31:0]  cmp_addr; 
+   wire [5:0]    cmp_bl;
+
+   reg                    data_error;
+   wire [DWIDTH-1:0]      cmp_data;
+   reg  [DWIDTH-1:0]      cmp_data_r;
+   reg  [DWIDTH-1:0]      cmp_data_r2;
+   reg  [DWIDTH-1:0]      cmp_data_r3;
+   reg  [DWIDTH-1:0]      cmp_data_r4;
+   reg                    last_word_rd;
+   reg [5:0]              bl_counter;
+   wire                   cmd_rdy;
+   wire                   user_bl_cnt_is_1;
+   wire                   data_rdy;
+   reg [DWIDTH:0] delayed_data;
+   wire                  rd_mdata_en;
+   reg [DWIDTH-1:0]      rd_data_r;
+   reg [DWIDTH-1:0]      rd_data_r2;
+   reg [DWIDTH-1:0]      rd_data_r3;
+   reg [DWIDTH-1:0]      rd_data_r4;
+   reg                   force_wrcmd_gen;
+   reg                   wait_bl_end;
+   reg                   wait_bl_end_r1;
+reg l_data_error ;
+reg u_data_error;
+reg v6_data_cmp_valid;
+wire [DWIDTH -1 :0] rd_v6_mdata;
+reg [DWIDTH -1 :0] rd_v6_mdata_r1;
+reg [DWIDTH -1 :0] rd_v6_mdata_r2;
+reg [DWIDTH -1 :0] rd_v6_mdata_r3;
+reg [DWIDTH -1 :0] rd_v6_mdata_r4;
+reg [DWIDTH -1 :0] cmpdata_r;
+wire [DWIDTH -1 :0] rd_mdata;
+wire                rd_mdata_fifo_empty;
+ reg cmp_data_en;
+
+
+wire [ DQ_ERROR_WIDTH-1:0] dq_lane_error;
+reg [ DQ_ERROR_WIDTH-1:0] dq_lane_error_r1;
+reg [ DQ_ERROR_WIDTH-1:0] dq_lane_error_r2;
+wire [ DQ_ERROR_WIDTH-1:0] cum_dq_lane_error_mask;
+wire [ DQ_ERROR_WIDTH-1:0] cumlative_dq_lane_error_c;
+reg [ DQ_ERROR_WIDTH-1:0] cumlative_dq_lane_error_reg;
+
+reg data_valid_r;
+
+  
+      always @ (posedge clk_i) begin
+             wait_bl_end_r1 <= #TCQ wait_bl_end;
+             rd_data_r <= #TCQ data_i;
+             rd_data_r2 <= #TCQ rd_data_r;
+             rd_data_r3 <= #TCQ rd_data_r2;
+             rd_data_r4 <= #TCQ rd_data_r3;
+      end
+  
+   assign force_wrcmd_gen_o = force_wrcmd_gen;
+  reg [7:0]         force_wrcmd_timeout_cnts ;
+
+   always @ (posedge clk_i) begin
+    if (rst_i[0])
+         force_wrcmd_gen <= #TCQ 1'b0;
+    else if ((wait_bl_end == 1'b0 &&  wait_bl_end_r1 == 1'b1) || force_wrcmd_timeout_cnts == 8'b11111111)
+         force_wrcmd_gen <= #TCQ 1'b0;
+   
+    else if ((cmd_valid_i && bl_i > 16) || wait_bl_end )
+         force_wrcmd_gen <= #TCQ 1'b1;
+    end
+
+  
+   always @ (posedge clk_i) begin
+    if (rst_i[0])
+        force_wrcmd_timeout_cnts <= #TCQ 'b0;
+    else if (wait_bl_end == 1'b0 &&  wait_bl_end_r1 == 1'b1)
+        force_wrcmd_timeout_cnts <= #TCQ 'b0;
+        
+    else if (force_wrcmd_gen)
+        force_wrcmd_timeout_cnts <= #TCQ force_wrcmd_timeout_cnts + 1;
+   end
+   
+   always @ (posedge clk_i)
+    if (rst_i[0])
+         wait_bl_end <= #TCQ 1'b0;
+    else if (force_wrcmd_timeout_cnts == 8'b11111111)
+         wait_bl_end <= #TCQ 1'b0;
+    
+    else if (gen_rdy && gen_valid && gen_bl > 16)
+         wait_bl_end <= #TCQ 1'b1;
+    else if (wait_bl_end && user_bl_cnt_is_1)
+         wait_bl_end <= #TCQ 1'b0;
+   
+   
+   assign cmd_rdy_o = cmd_rdy;
+   read_posted_fifo #(
+           .TCQ               (TCQ),
+           .FAMILY    (FAMILY),
+           .MEM_BURST_LEN (MEM_BURST_LEN),
+           .ADDR_WIDTH(32),
+           .BL_WIDTH(6)
+           )
+   read_postedfifo(
+                    .clk_i              (clk_i),
+                    .rst_i                (rst_i[0]),
+                    .cmd_rdy_o          (cmd_rdy      ),
+                    .cmd_valid_i        (cmd_valid_i    ),
+                    .data_valid_i         (data_rdy        ),  // input to
+                    .addr_i             (addr_i         ),
+                    .bl_i               (bl_i           ),
+                    
+                    .cmd_sent           (cmd_sent),
+                    .bl_sent            (bl_sent ),
+                    .cmd_en_i           (cmd_en_i),
+                    
+                    .user_bl_cnt_is_1   (user_bl_cnt_is_1),
+                    .gen_rdy_i          (gen_rdy        ),
+                    .gen_valid_o        (gen_valid      ),
+                    .gen_addr_o         (gen_addr       ),
+                    .gen_bl_o           (gen_bl         ),
+                    .rd_buff_avail_o      (rd_buff_avail_o),
+                    .rd_mdata_fifo_empty    (rd_mdata_fifo_empty),
+                    .rd_mdata_en            (rd_mdata_en)
+                    );
+
+
+ 
+   
+   rd_data_gen #(
+              .TCQ               (TCQ),
+              .FAMILY  (FAMILY),
+              .MEM_BURST_LEN    (MEM_BURST_LEN),
+              .NUM_DQ_PINS (NUM_DQ_PINS), 
+              .SEL_VICTIM_LINE   (SEL_VICTIM_LINE),
+   
+              .DATA_PATTERN  (DATA_PATTERN),
+              .DWIDTH(DWIDTH),
+              .COLUMN_WIDTH     (MEM_COL_WIDTH)
+              
+              )
+   rd_datagen(
+            .clk_i              (clk_i          ),
+            .rst_i              (rst_i[4:0]),            
+            .prbs_fseed_i       (prbs_fseed_i),
+            .data_mode_i        (data_mode_i    ),            
+            .cmd_rdy_o          (gen_rdy        ),
+            .cmd_valid_i        (gen_valid      ),  
+            .last_word_o        (last_word_rd_o ),  
+            
+//            .m_addr_i           (m_addr_i       ),
+            .fixed_data_i         (fixed_data_i),
+            
+            .addr_i             (gen_addr       ),
+            .bl_i               (gen_bl         ),
+            .user_bl_cnt_is_1_o   (user_bl_cnt_is_1),
+            .data_rdy_i         (data_valid_i        ),  // input to
+            .data_valid_o       (cmp_valid      ),
+            .data_o             (cmp_data       ),
+            .rd_mdata_en          (rd_mdata_en)
+            );
+
+
+   afifo #
+   (
+    .TCQ           (TCQ),
+    .DSIZE         (DWIDTH),
+    .FIFO_DEPTH    (32),
+    .ASIZE         (5),
+    .SYNC          (1)  // set the SYNC to 1 because rd_clk = wr_clk to reduce latency 
+   
+   
+   )
+   rd_mdata_fifo
+   (
+    .wr_clk        (clk_i),
+    .rst           (rst_i[0]),
+    .wr_en         (data_valid_i),
+    .wr_data       (data_i),
+    .rd_en         (rd_mdata_en),
+    .rd_clk        (clk_i),
+    .rd_data       (rd_v6_mdata),
+    .full          (),
+    .empty         (rd_mdata_fifo_empty),
+    .almost_full   ()
+   );
+
+always @ (posedge clk_i)
+begin
+//    delayed_data <= #TCQ {cmp_valid & data_valid_i,cmp_data};
+    cmp_data_r <= #TCQ cmp_data;
+    cmp_data_r2 <= #TCQ cmp_data_r;
+    cmp_data_r3 <= #TCQ cmp_data_r2;
+    cmp_data_r4 <= #TCQ cmp_data_r3;
+end
+
+assign rd_mdata_o = rd_mdata;
+
+assign rd_mdata = (FAMILY == "SPARTAN6") ? rd_data_r3: 
+                  (FAMILY == "VIRTEX6" && MEM_BURST_LEN == 4)? rd_v6_mdata_r2:
+                  rd_data_r;
+
+assign cmp_data_valid = (FAMILY == "SPARTAN6") ? cmp_data_en :
+                        (FAMILY == "VIRTEX6" && MEM_BURST_LEN == 4)? v6_data_cmp_valid :data_valid_i;
+
+
+
+   
+assign        cmp_data_o  = (FAMILY == "SPARTAN6") ? cmp_data_r3 : cmp_data_r2;
+assign        cmp_addr_o  = gen_addr;
+assign        cmp_bl_o    = gen_bl;
+
+
+   
+assign data_rdy_o = data_rdy;
+assign data_rdy = cmp_valid & data_valid_i;
+
+ always @ (posedge clk_i)
+    v6_data_cmp_valid <= #TCQ rd_mdata_en;
+
+
+ always @ (posedge clk_i)
+       cmp_data_en <= #TCQ data_rdy;
+
+ generate
+ if (FAMILY == "SPARTAN6") begin: gen_error_1
+   always @ (posedge clk_i)
+     begin
+       if (cmp_data_en)
+           l_data_error <= #TCQ (rd_data_r[DWIDTH/2-1:0] !== cmp_data_r[DWIDTH/2-1:0]);           
+        else
+           l_data_error <= #TCQ 1'b0;
+
+       if (cmp_data_en)
+           u_data_error <= #TCQ (rd_data_r[DWIDTH-1:DWIDTH/2] !== cmp_data_r[DWIDTH-1:DWIDTH/2]);           
+        else
+           u_data_error <= #TCQ 1'b0;
+
+       data_error <= #TCQ l_data_error | u_data_error;
+      //synthesis translate_off
+      if (data_error)
+        $display ("ERROR: Expected data=%h and recieved data= %h @ %t" ,cmp_data_r4, rd_data_r4, $time);
+      //synthesis translate_on
+        
+     end
+
+end
+endgenerate
+wire [NUM_DQ_PINS/2 - 1:0] error_byte;   
+reg [NUM_DQ_PINS/2 - 1:0] error_byte_r1;   
+
+genvar i;
+ generate
+ if (FAMILY == "VIRTEX6" && MEM_BURST_LEN == 4) begin: gen_error_2
+
+
+    for (i = 0; i < NUM_DQ_PINS/2; i = i + 1) begin: gen_cmp
+      assign error_byte[i] 
+               = (~rd_mdata_fifo_empty && rd_mdata_en && (rd_v6_mdata[8*(i+1)-1:8*i] !== cmp_data[8*(i+1)-1:8*i]) );  
+
+
+    end
+
+always @ (posedge clk_i)
+begin
+  rd_v6_mdata_r1 <= rd_v6_mdata;
+  rd_v6_mdata_r2 <= rd_v6_mdata_r1;
+  rd_v6_mdata_r3 <= rd_v6_mdata_r2;
+  rd_v6_mdata_r4 <= rd_v6_mdata_r3;
+end
+
+always @ (posedge clk_i)
+begin
+    if (rst_i[1] || manual_clear_error) begin
+    
+      error_byte_r1 <= #TCQ 'b0;
+      data_error <= #TCQ 1'b0;
+      end
+    else begin
+      error_byte_r1 <= #TCQ error_byte;
+      data_error <= #TCQ | error_byte_r1;
+    
+    
+      //synthesis translate_off
+      if (data_error)
+        $display ("ERROR: Expected data=%h and recieved data= %h @ %t" ,cmp_data_r2,rd_v6_mdata_r2,$time);
+      //synthesis translate_on
+    end
+
+end
+
+  // remap the app_rd_data error byte locastion to dq bus side.
+    for ( i = 0; i < DQ_ERROR_WIDTH; i = i+1) begin: gen_dq_error_map
+        assign dq_lane_error[i] = (error_byte_r1[i] | error_byte_r1[i+DQ_ERROR_WIDTH] |
+                              error_byte_r1[i+ (NUM_DQ_PINS*2/8)] | 
+                              error_byte_r1[i+ (NUM_DQ_PINS*3/8)]);
+                              
+        assign cumlative_dq_lane_error_c[i] =  cumlative_dq_lane_error_r[i] | dq_lane_error_r1[i];
+    end                         
+
+                    
+always @ (posedge clk_i)
+begin
+    if (rst_i[1] || manual_clear_error) begin
+    
+      dq_lane_error_r1 <= #TCQ 'b0;
+      dq_lane_error_r2 <= #TCQ 'b0;
+      data_valid_r <= #TCQ 1'b0;
+      cumlative_dq_lane_error_reg <= #TCQ 'b0;
+      end
+    else begin
+      data_valid_r <= #TCQ data_valid_i;
+    
+      dq_lane_error_r1 <= #TCQ dq_lane_error;
+      cumlative_dq_lane_error_reg <= #TCQ cumlative_dq_lane_error_c;
+    end
+end
+end
+//end
+endgenerate
+     
+ generate
+ if (FAMILY == "VIRTEX6" && MEM_BURST_LEN == 8) begin: gen_error_3
+    for (i = 0; i < NUM_DQ_PINS/2; i = i + 1) begin: gen_cmp
+      assign error_byte[i] 
+               = (data_valid_i && (data_i[8*(i+1)-1:8*i] !== cmp_data[8*(i+1)-1:8*i]) );  
+    end
+    
+    
+    
+    
+always @ (posedge clk_i)
+begin
+    if (rst_i[1] || manual_clear_error) begin
+    
+      error_byte_r1 <= #TCQ 'b0;
+      data_error <= #TCQ 1'b0;
+      end
+    else begin
+
+    error_byte_r1 <= #TCQ error_byte;
+    data_error <= #TCQ | error_byte_r1;
+    
+      //synthesis translate_off
+    if (data_error)
+        $display ("ERROR: Expected data=%h and recieved data= %h @ %t" ,cmp_data_r2,rd_data_r2,$time);
+      //synthesis translate_on
+      
+    end
+end
+
+
+    for ( i = 0; i < DQ_ERROR_WIDTH; i = i+1) begin: gen_dq_error_map
+        assign dq_lane_error[i] = (error_byte_r1[i] | error_byte_r1[i+DQ_ERROR_WIDTH] |
+                              error_byte_r1[i+ (NUM_DQ_PINS*2/8)] | 
+                              error_byte_r1[i+ (NUM_DQ_PINS*3/8)]);
+                              
+        assign cumlative_dq_lane_error_c[i] =  cumlative_dq_lane_error_r[i] | dq_lane_error_r1[i];
+    end                         
+
+
+always @ (posedge clk_i)
+begin
+    if (rst_i[1] || manual_clear_error) begin
+    
+      dq_lane_error_r1 <= #TCQ 'b0;
+      dq_lane_error_r2 <= #TCQ 'b0;
+      data_valid_r <= #TCQ 1'b0;
+      cumlative_dq_lane_error_reg <= #TCQ 'b0;
+      end
+    else begin
+      data_valid_r <= #TCQ data_valid_i;
+      dq_lane_error_r1 <= #TCQ dq_lane_error;
+      cumlative_dq_lane_error_reg <= #TCQ cumlative_dq_lane_error_c;
+    end
+end
+end
+//end
+endgenerate
+    
+assign cumlative_dq_lane_error_r = cumlative_dq_lane_error_reg;     
+assign dq_error_bytelane_cmp = dq_lane_error_r1;     
+assign data_error_o = data_error;
+
+     
+endmodule 
+

Frogwells_fpga_design/基于FPGA、DDR3和USB2.0的图像采集系统/debug/ddr_test/rtl/traffic_gen/read_posted_fifo.v

@@ -0,0 +1,264 @@
+//*****************************************************************************
+// (c) Copyright 2008-2009 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+//*****************************************************************************
+//   ____  ____
+//  /   /\/   /
+// /___/  \  /    Vendor: Xilinx
+// \   \   \/     Version: %version
+//  \   \         Application: MIG
+//  /   /         Filename: read_posted_fifo.v
+// /___/   /\     Date Last Modified: 
+// \   \  /  \    Date Created: 
+//  \___\/\___\
+//
+//Device: Spartan6
+//Design Name: DDR/DDR2/DDR3/LPDDR 
+//Purpose: This module instantiated by read_data_path module and sits between 
+//         mcb_flow_control module and read_data_gen module to buffer up the 
+//         commands that has sent to memory controller.
+//Reference:
+//Revision History:
+//                  2010/01/09/   Corrected dfifo_has_enough_room threshold logic.
+//                                It has to set higher in Read Only port.
+//*****************************************************************************
+`timescale 1ps/1ps
+   
+  module read_posted_fifo #
+  (
+   parameter TCQ           = 100,  
+   parameter FAMILY     = "SPARTAN6",  
+   parameter MEM_BURST_LEN = 4,
+
+   parameter ADDR_WIDTH = 32,
+   parameter BL_WIDTH = 6
+  )
+  (
+   input                   clk_i, 
+   input                   rst_i,
+   output reg                 cmd_rdy_o, 
+   input                   cmd_valid_i, 
+   input                   data_valid_i,
+   input [ADDR_WIDTH-1:0]  addr_i, 
+   input [BL_WIDTH-1:0]    bl_i,
+   input                   user_bl_cnt_is_1,
+   input [2:0]           cmd_sent, 
+   input [5:0]           bl_sent  ,
+   input                 cmd_en_i ,
+   
+   
+   input                   gen_rdy_i, 
+   output                  gen_valid_o, 
+   output [ADDR_WIDTH-1:0] gen_addr_o, 
+   output [BL_WIDTH-1:0]   gen_bl_o,
+   output [6:0]           rd_buff_avail_o,
+   input                   rd_mdata_fifo_empty,
+   output                  rd_mdata_en
+
+   ); 
+  
+reg empty_r;
+reg rd_first_data;
+  
+   wire full;
+   wire empty;
+   wire wr_en;
+   reg rd_en;
+   reg data_valid_r;
+   reg user_bl_cnt_not_1;
+    reg [6:0] buf_avail_r;
+    reg [6:0] rd_data_received_counts;
+    reg [6:0] rd_data_counts_asked;
+    
+      reg dfifo_has_enough_room;
+    reg [1:0] wait_cnt;
+    reg wait_done;
+
+  assign rd_mdata_en = rd_en;
+
+   assign rd_buff_avail_o = buf_avail_r;
+   always @ (posedge clk_i)
+       cmd_rdy_o <= #TCQ !full  & dfifo_has_enough_room & wait_done;
+
+   always @ (posedge clk_i)
+   begin
+   if (rst_i)
+       wait_cnt <= #TCQ 'b0;
+   else if (cmd_rdy_o && cmd_valid_i)
+       wait_cnt <= #TCQ 2'b10;
+   else if (wait_cnt > 0)
+         wait_cnt <= #TCQ wait_cnt - 1;
+       
+   end
+   
+   always @(posedge clk_i)
+   begin
+   if (rst_i)
+      wait_done <= #TCQ 1'b1;
+   else if (cmd_rdy_o && cmd_valid_i)
+      wait_done <= #TCQ 1'b0;
+   else if (wait_cnt == 0)
+      wait_done <= #TCQ 1'b1;
+   else
+      wait_done <= #TCQ 1'b0;
+   
+   end
+   
+   reg dfifo_has_enough_room_d1;
+   always @ (posedge clk_i)
+   begin // prbs_blen from cmd_gen is random, it can be two 64 in consecutive
+         // the logic here to prevent cmd_gen send any further read command if
+         // any large bl command has been sent.
+         
+       dfifo_has_enough_room <= #TCQ (buf_avail_r >= 62  ) ? 1'b1: 1'b0;
+
+       dfifo_has_enough_room_d1 <= #TCQ dfifo_has_enough_room ;
+   end
+   
+   
+   assign wr_en    = cmd_valid_i & !full  & dfifo_has_enough_room_d1 & wait_done;
+
+   
+   always @ (posedge clk_i)
+       data_valid_r <= #TCQ data_valid_i;
+  
+  
+  always @ (posedge clk_i)
+  begin
+  if (data_valid_i && user_bl_cnt_is_1)  // current count is 1 and data_is_valie, then next cycle is not 1
+     user_bl_cnt_not_1 <= #TCQ 1'b1;
+  else     
+     user_bl_cnt_not_1 <= #TCQ 1'b0;
+  end  
+ 
+ always @ (posedge clk_i)
+ begin
+ if (rst_i) begin
+    rd_data_counts_asked <= #TCQ 'b0;
+    end
+ else if (cmd_en_i && cmd_sent[0] == 1) begin
+
+    rd_data_counts_asked <= #TCQ rd_data_counts_asked + (bl_sent + 7'b0000001) ;
+
+    end
+ end
+
+ always @ (posedge clk_i)
+ begin
+ if (rst_i) begin
+     rd_data_received_counts <= #TCQ 'b0;
+     end
+ else if (data_valid_i) begin
+     rd_data_received_counts <= #TCQ rd_data_received_counts + 1;
+     end     
+ end
+ 
+ // calculate how many buf still available
+ always @ (posedge clk_i)
+                  // MCB FIFO size is 64.
+                  // buf_available is calculated by:
+                  // FIFO DEPTH - ( Write Poitner - Read Pointer)
+     buf_avail_r <= #TCQ 64 - (rd_data_counts_asked - rd_data_received_counts);
+ 
+ 
+   
+   always @(gen_rdy_i, empty,empty_r,rd_mdata_fifo_empty,rd_first_data ,data_valid_i,data_valid_r,user_bl_cnt_not_1)
+   begin
+        if (FAMILY == "SPARTAN6")
+            rd_en = gen_rdy_i & !empty;
+        else 
+             if ( MEM_BURST_LEN == 4)
+                   rd_en = (~empty & empty_r & ~rd_first_data) | (~rd_mdata_fifo_empty & ~empty ) | (user_bl_cnt_not_1 & data_valid_i);
+             else
+                   rd_en = (data_valid_i & ~data_valid_r) | (user_bl_cnt_not_1 & data_valid_i);
+   
+        end
+   
+   always @ (posedge clk_i)
+        empty_r <= #TCQ empty;
+        
+   always @ (posedge clk_i)
+   begin 
+   if (rst_i)
+       rd_first_data <= #TCQ 1'b0;
+   else if (~empty && empty_r)
+       rd_first_data <= #TCQ 1'b1;
+   end   
+
+       
+   
+   assign gen_valid_o = !empty;
+   afifo #
+   (
+    .TCQ               (TCQ),
+    .DSIZE         (BL_WIDTH+ADDR_WIDTH),
+    .FIFO_DEPTH    (16),
+    .ASIZE         (4),
+    .SYNC          (1)  // set the SYNC to 1 because rd_clk = wr_clk to reduce latency 
+   
+   
+   )
+   rd_fifo
+   (
+    .wr_clk        (clk_i),
+    .rst           (rst_i),
+    .wr_en         (wr_en),
+    .wr_data       ({bl_i,addr_i}),
+    .rd_en         (rd_en),
+    .rd_clk        (clk_i),
+    .rd_data       ({gen_bl_o,gen_addr_o}),
+    .full          (full),
+    .empty         (empty),
+    .almost_full   ()
+   
+   );
+   
+   
+   
+   
+   
+endmodule 

Frogwells_fpga_design/基于FPGA、DDR3和USB2.0的图像采集系统/debug/ddr_test/rtl/traffic_gen/sp6_data_gen.v

@@ -0,0 +1,781 @@
+//*****************************************************************************
+// (c) Copyright 2008-2009 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+//*****************************************************************************
+//   ____  ____
+//  /   /\/   /
+// /___/  \  /    Vendor: Xilinx
+// \   \   \/     Version: %version
+//  \   \         Application: MIG
+//  /   /         Filename: data_gen.v
+// /___/   /\     Date Last Modified: 
+// \   \  /  \    Date Created: 
+//  \___\/\___\
+//
+//Device: Spartan6
+//Design Name: DDR/DDR2/DDR3/LPDDR 
+//Purpose: This module generates different data pattern as described in 
+//         parameter DATA_PATTERN and is set up for Spartan 6 family.
+//Reference:
+//Revision History:
+//*****************************************************************************
+
+`timescale 1ps/1ps
+
+module sp6_data_gen #
+ 
+( 
+   parameter TCQ           = 100,  
+   parameter ADDR_WIDTH = 32,
+   parameter BL_WIDTH = 6,
+   parameter DWIDTH = 32,
+   parameter DATA_PATTERN = "DGEN_ALL", //"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"  
+   parameter NUM_DQ_PINS   = 8,
+   parameter COLUMN_WIDTH = 10
+   
+ )
+ (
+   input   clk_i,                 //
+   input   rst_i, 
+   input [31:0] prbs_fseed_i,
+   
+   input [3:0]  data_mode_i,   // "00" = bram; 
+   input        data_rdy_i,
+   input   cmd_startA,  
+   input   cmd_startB,         
+   input   cmd_startC,         
+   input   cmd_startD,         
+   input   cmd_startE,         
+   input [DWIDTH-1:0]     fixed_data_i,    
+
+   input [ADDR_WIDTH-1:0]  addr_i,          // generated address used to determine data pattern.
+   input [6:0]    user_burst_cnt,   // generated burst length for control the burst data
+   
+   input   fifo_rdy_i,           // connect from mcb_wr_full when used as wr_data_gen
+                                 // connect from mcb_rd_empty when used as rd_data_gen
+                                 // When both data_rdy and data_valid is asserted, the ouput data is valid.
+   output  [DWIDTH-1:0] data_o   // generated data pattern   
+);  
+// 
+wire [31:0]       prbs_data; 
+
+reg [31:0]         adata; 
+reg [DWIDTH-1:0]   hdata; 
+reg [DWIDTH-1:0]   ndata; 
+reg [DWIDTH - 1:0] w1data; 
+reg [DWIDTH-1:0] data;
+reg burst_count_reached2;
+
+reg               data_valid;
+reg [2:0] walk_cnt;
+reg [ADDR_WIDTH-1:0] user_address;
+
+
+integer i,j;
+reg [BL_WIDTH-1:0] user_bl;
+reg [7:0] BLANK;
+
+reg [7:0] SHIFT_0;
+reg [7:0] SHIFT_1;
+reg [7:0] SHIFT_2;
+reg [7:0] SHIFT_3;
+reg [7:0] SHIFT_4;
+reg [7:0] SHIFT_5;
+reg [7:0] SHIFT_6;
+reg [7:0] SHIFT_7;
+reg [31:0] SHIFTB_0 ; 
+reg [31:0] SHIFTB_1;
+reg [31:0] SHIFTB_2;
+reg [31:0] SHIFTB_3;
+reg [31:0] SHIFTB_4;
+reg [31:0] SHIFTB_5;
+reg [31:0] SHIFTB_6;
+reg [31:0] SHIFTB_7;
+reg [3:0] TSTB;
+//*********************************************************************************************
+
+
+
+
+
+assign data_o = data;
+
+generate 
+
+if (DWIDTH==32) begin: data_out32
+always @ (adata,hdata,ndata,w1data,prbs_data,data_mode_i,fixed_data_i)
+begin
+   case(data_mode_i)
+       //  4'b0000: data = 32'b0;       //reserved
+         4'b0001: data = fixed_data_i;       // fixed
+         4'b0010: data = adata;  // address as data
+         4'b0011: data = hdata;  // DGEN_HAMMER
+         4'b0100: data = ndata;  // DGEN_NEIGHBOUR
+         4'b0101: data = w1data; // DGEN_WALKING1
+         4'b0110: data = w1data; // DGEN_WALKING0
+         4'b0111: data = prbs_data;
+         default : data = 'b0;
+   endcase
+end        
+end
+
+endgenerate
+
+generate 
+if (DWIDTH==64) begin: data_out64
+always @ (adata,hdata,ndata,w1data,prbs_data,data_mode_i,fixed_data_i)
+begin
+   case(data_mode_i) 
+         4'b0000: data = 'b0;                 //reserved
+         4'b0001: data = fixed_data_i;                 // fixed
+         4'b0010: data = {adata,adata};       // address as data
+         4'b0011: data = hdata;       // DGEN_HAMMER
+         4'b0100: data = ndata;       // DGEN_NEIGHBOUR
+         4'b0101: data = w1data;     // DGEN_WALKING1
+         4'b0110: data = w1data;     // DGEN_WALKING0
+         4'b0111: data = {prbs_data,prbs_data};
+         default : data = 'b0;
+   endcase
+end        
+end
+endgenerate
+
+generate 
+if (DWIDTH==128) begin: data_out128
+always @ (adata,hdata,ndata,w1data,prbs_data,data_mode_i,fixed_data_i)
+begin
+   case(data_mode_i)
+         4'b0000: data = 'b0;       //reserved
+         4'b0001: data = fixed_data_i;       // fixed
+         4'b0010: data = {adata,adata,adata,adata};       // address as data
+         4'b0011: data = hdata;       // DGEN_HAMMER
+         4'b0100: data = ndata;       // DGEN_NEIGHBOUR
+         4'b0101: data = w1data;   // DGEN_WALKING1
+         4'b0110: data = w1data;   // DGEN_WALKING0
+         4'b0111: data = {prbs_data,prbs_data,prbs_data,prbs_data};
+         default : data = 'b0;
+   endcase
+end        
+end
+endgenerate
+
+
+// WALKING ONES:
+
+generate
+if ((DWIDTH == 64) ||(DWIDTH == 128))  begin: SHIFT_VALUE
+   
+always @ (data_mode_i) begin
+  if (data_mode_i == 3'b101 || data_mode_i == 3'b100) begin // WALKING ONE
+    BLANK   = 8'h00;
+    SHIFT_0 = 8'h01;
+    SHIFT_1 = 8'h02;    
+    SHIFT_2 = 8'h04;    
+    SHIFT_3 = 8'h08;    
+    SHIFT_4 = 8'h10;    
+    SHIFT_5 = 8'h20;    
+    SHIFT_6 = 8'h40;    
+    SHIFT_7 = 8'h80;    
+    
+    end
+    else if (data_mode_i == 3'b100)begin // NEIGHBOR ONE
+    BLANK   = 8'h00;
+    SHIFT_0 = 8'h01;
+    SHIFT_1 = 8'h02;    
+    SHIFT_2 = 8'h04;    
+    SHIFT_3 = 8'h08;    
+    SHIFT_4 = 8'h10;    
+    SHIFT_5 = 8'h20;    
+    SHIFT_6 = 8'h40;    
+    SHIFT_7 = 8'h80;    
+    end       
+    
+
+
+    else if (data_mode_i == 3'b110) begin  // WALKING ZERO
+    BLANK   = 8'hff;
+    SHIFT_0 = 8'hfe;
+    SHIFT_1 = 8'hfd;    
+    SHIFT_2 = 8'hfb;    
+    SHIFT_3 = 8'hf7;    
+    SHIFT_4 = 8'hef;    
+    SHIFT_5 = 8'hdf;    
+    SHIFT_6 = 8'hbf;    
+    SHIFT_7 = 8'h7f;    
+    end   
+    else begin
+    BLANK   = 8'hff;
+    SHIFT_0 = 8'hfe;
+    SHIFT_1 = 8'hfd;    
+    SHIFT_2 = 8'hfb;    
+    SHIFT_3 = 8'hf7;    
+    SHIFT_4 = 8'hef;    
+    SHIFT_5 = 8'hdf;    
+    SHIFT_6 = 8'hbf;    
+    SHIFT_7 = 8'h7f;    
+    end   
+
+end
+end
+endgenerate
+
+always @ (data_mode_i) begin
+
+if (data_mode_i == 3'b101 ) begin // WALKING ONE
+   
+    SHIFTB_0 = 32'h0002_0001;
+    SHIFTB_1 = 32'h0008_0004;    
+    SHIFTB_2 = 32'h0020_0010;    
+    SHIFTB_3 = 32'h0080_0040;    
+    SHIFTB_4 = 32'h0200_0100;    
+    SHIFTB_5 = 32'h0800_0400;    
+    SHIFTB_6 = 32'h2000_1000;    
+    SHIFTB_7 = 32'h8000_4000;    
+    end
+else if (data_mode_i == 3'b100)begin // NEIGHBOR ONE
+   
+    SHIFTB_0 = 32'h0000_0001;
+    SHIFTB_1 = 32'h0000_0002;    
+    SHIFTB_2 = 32'h0000_0004;    
+    SHIFTB_3 = 32'h0000_0008;    
+    SHIFTB_4 = 32'h0000_0010;    
+    SHIFTB_5 = 32'h0000_0020;    
+    SHIFTB_6 = 32'h0000_0040;    
+    SHIFTB_7 = 32'h0000_0080;    
+    end    
+    
+else begin  // WALKING ZERO
+    SHIFTB_0 = 32'hfffd_fffe;
+    SHIFTB_1 = 32'hfff7_fffb;    
+    SHIFTB_2 = 32'hffdf_ffef;    
+    SHIFTB_3 = 32'hff7f_ffbf;    
+    SHIFTB_4 = 32'hfdff_feff;    
+    SHIFTB_5 = 32'hf7ff_fbff;    
+    SHIFTB_6 = 32'hdfff_efff;    
+    SHIFTB_7 = 32'h7fff_bfff;    
+    end
+
+end
+
+
+
+
+
+reg [DWIDTH-1:0] tmpdata ;
+reg ndata_rising;
+reg shift_en;
+generate
+if (DWIDTH == 32 && (DATA_PATTERN == "DGEN_WALKING0" || DATA_PATTERN == "DGEN_WALKING1" ||
+    DATA_PATTERN == "DGEN_ALL"))  begin : WALKING_ONE_32_PATTERN
+
+  always @ (posedge clk_i)
+  begin
+   if (rst_i) begin
+        w1data <= #TCQ  'b0;
+        ndata_rising <= #TCQ  1'b1;
+        shift_en <= #TCQ  1'b0;
+        end
+   else if((fifo_rdy_i && user_burst_cnt != 6'd0) || cmd_startC )
+      if (NUM_DQ_PINS == 16) 
+      begin
+         if(cmd_startC) 
+           begin
+                      case (addr_i[4:2])
+                      0: w1data <= #TCQ    SHIFTB_0;
+                      1: w1data <= #TCQ    SHIFTB_1;
+                      2: w1data <= #TCQ    SHIFTB_2;
+                      3: w1data <= #TCQ    SHIFTB_3;
+                      4: w1data <= #TCQ    SHIFTB_4;
+                      5: w1data <= #TCQ    SHIFTB_5;
+                      6: w1data <= #TCQ    SHIFTB_6;
+                      7: w1data <= #TCQ    SHIFTB_7;
+                      
+                      default :w1data <= #TCQ    SHIFTB_0;
+                      endcase   
+                      
+                      ndata_rising <= #TCQ  1'b0;
+           end  //(NUM_DQ_PINS == 16) (cmd_startC)  
+         else //shifting
+            if (data_mode_i == 3'b100) 
+              w1data <= #TCQ    {16'h0000,w1data[14:0],w1data[15]};
+            else
+              w1data <= #TCQ    {w1data[29:16],w1data[31:30],w1data[13:0],w1data[15:14]}; 
+              
+              
+      end  //(DQ_PINS == 16 
+      else if (NUM_DQ_PINS == 8) begin
+         if(cmd_startC)  // loading data pattern according the incoming address
+            begin
+                       case (addr_i[2])
+                        0: w1data <= #TCQ    SHIFTB_0;
+                        1: w1data <= #TCQ    SHIFTB_1;
+                        default :w1data <= #TCQ    SHIFTB_0;
+                       endcase 
+            end // (cmd_startC)   
+        else  // Shifting
+          // need neigbour pattern ********************
+                w1data <= #TCQ    {w1data[27:24],w1data[31:28],w1data[19:16],w1data[23:20],
+                                w1data[11:8] ,w1data[15:12],w1data[3:0]  ,w1data[7:4]}; 
+                      
+      end //(NUM_DQ_PINS == 8)
+      else if (NUM_DQ_PINS == 4) begin   // NUM_DQ_PINS == 4   
+          // need neigbour pattern ********************      
+             if (data_mode_i == 3'b100) 
+               w1data <= #TCQ    32'h0804_0201;
+             else
+               w1data <= #TCQ    32'h8421_8421;
+      end // (NUM_DQ_PINS_4    
+           
+  end
+end
+endgenerate // DWIDTH == 32
+
+generate
+if (DWIDTH == 64 && (DATA_PATTERN == "DGEN_WALKING0" || DATA_PATTERN == "DGEN_WALKING1"
+    || DATA_PATTERN == "DGEN_ALL"))  begin : WALKING_ONE_64_PATTERN
+
+  always @ (posedge clk_i)
+  begin
+   if (rst_i)
+        w1data <= #TCQ  'b0;
+   
+   else if((fifo_rdy_i && user_burst_cnt != 6'd0) || cmd_startC )
+
+    
+    
+      if (NUM_DQ_PINS == 16) 
+      begin
+         if(cmd_startC)
+           begin
+
+             case (addr_i[4:3])
+
+             
+                 0: begin 
+                    //  7:0
+                    w1data[2*DWIDTH/4-1:0*DWIDTH/4]    <= #TCQ    SHIFTB_0; 
+                    w1data[4*DWIDTH/4-1:2*DWIDTH/4]    <= #TCQ    SHIFTB_1;
+ 
+                    end
+                 1:  begin 
+                    w1data[2*DWIDTH/4-1:0*DWIDTH/4]    <= #TCQ    SHIFTB_2; 
+                    w1data[4*DWIDTH/4-1:2*DWIDTH/4]    <= #TCQ    SHIFTB_3;
+                    end
+                    
+                 2: begin 
+                    w1data[2*DWIDTH/4-1:0*DWIDTH/4]    <= #TCQ    SHIFTB_4; 
+                    w1data[4*DWIDTH/4-1:2*DWIDTH/4]    <= #TCQ    SHIFTB_5;
+                    end
+                 3:  begin 
+                    w1data[2*DWIDTH/4-1:0*DWIDTH/4]    <= #TCQ    SHIFTB_6; 
+                    w1data[4*DWIDTH/4-1:2*DWIDTH/4]    <= #TCQ    SHIFTB_7;
+                    
+                    end
+                     
+                    
+               default :begin
+                    w1data <= #TCQ  BLANK;    //15:8 
+                    end
+                    
+             endcase         
+
+                      
+           end  //(NUM_DQ_PINS == 16) (cmd_startC)      
+         else begin  //shifting
+             if (data_mode_i == 3'b100) 
+               begin
+                 w1data[63:48] <= #TCQ    {16'h0000};
+                 w1data[47:32] <= #TCQ    {w1data[45:32],w1data[47:46]};
+                 w1data[31:16] <= #TCQ    {16'h0000};
+                 w1data[15:0]  <= #TCQ    {w1data[13:0],w1data[15:14]};
+                 
+               end
+            else
+
+              w1data[DWIDTH - 1:0] <= #TCQ    {
+                                          w1data[4*DWIDTH/4 - 5:4*DWIDTH/4 - 16],
+                                          w1data[4*DWIDTH/4 - 1 :4*DWIDTH/4 - 4],                                                    
+                                                        
+                                          w1data[3*DWIDTH/4 - 5:3*DWIDTH/4 - 16],
+                                          w1data[3*DWIDTH/4 - 1 :3*DWIDTH/4 - 4],                                                                                                        
+
+                                          w1data[2*DWIDTH/4 - 5:2*DWIDTH/4 - 16],
+                                          w1data[2*DWIDTH/4 - 1 :2*DWIDTH/4 - 4],
+ 
+                                          w1data[1*DWIDTH/4 - 5:1*DWIDTH/4 - 16],
+                                          w1data[1*DWIDTH/4 - 1 :1*DWIDTH/4 - 4]                                                    
+                                          
+                                          };   
+                                                    
+              
+         end    
+              
+      end  //(DQ_PINS == 16 
+      else if (NUM_DQ_PINS == 8) begin
+         if(cmd_startC)  // loading data pattern according the incoming address
+
+                 if (data_mode_i == 3'b100)  
+                 
+                   case (addr_i[3])
+                 
+                   
+                       0:  w1data <= #TCQ    {
+                                   BLANK,SHIFT_3,BLANK,SHIFT_2,
+                                   BLANK,SHIFT_1,BLANK,SHIFT_0
+                                   };                        
+                         
+                       1:  w1data <= #TCQ    {
+                                   BLANK,SHIFT_7,BLANK,SHIFT_6,
+                                   BLANK,SHIFT_5,BLANK,SHIFT_4
+                                   };                        
+                    
+                       default :begin
+                         w1data <= #TCQ    'b0;    //15:8 
+                    end
+                    
+                    endcase         
+
+                  else
+                  w1data <= #TCQ    {32'h8040_2010,32'h0804_0201};  //**** checked
+         else  // Shifting
+                 if (data_mode_i == 3'b100)  
+         
+               begin
+                 w1data[63:56] <= #TCQ    {8'h00};
+                 w1data[55:48] <= #TCQ    {w1data[51:48],w1data[55:52]};
+                 
+                 w1data[47:40] <= #TCQ    {8'h00};                 
+                 w1data[39:32] <= #TCQ    {w1data[35:32],w1data[39:36]};
+                 
+                 w1data[31:24] <= #TCQ    {8'h00};
+                 w1data[23:16] <= #TCQ    {w1data[19:16],w1data[23:20]};
+                 
+                 w1data[15:8]  <= #TCQ    {8'h00};
+                 w1data[7:0]  <= #TCQ    {w1data[3:0],w1data[7:4]};
+                 
+               end
+                 else
+                      w1data <= #TCQ    w1data; 
+      end //(NUM_DQ_PINS == 8)
+      else if (NUM_DQ_PINS == 4) // NUM_DQ_PINS == 4   
+            if (data_mode_i == 3'b100)  
+               w1data <= #TCQ    64'h0804_0201_0804_0201;
+            else
+               w1data <= #TCQ    64'h8421_8421_8421_8421; 
+           
+  end
+end
+endgenerate
+
+generate
+
+if (DWIDTH == 128 && (DATA_PATTERN == "DGEN_WALKING0" || DATA_PATTERN == "DGEN_WALKING1" || DATA_PATTERN == "DGEN_ALL"))  begin : WALKING_ONE_128_PATTERN
+
+  always @ (posedge clk_i)
+  begin
+   if (rst_i)
+        w1data <= #TCQ  'b0;
+   
+   else if((fifo_rdy_i && user_burst_cnt != 6'd0) || cmd_startC )
+
+    
+    
+      if (NUM_DQ_PINS == 16) 
+      begin
+         if(cmd_startC)
+           begin
+             case (addr_i[4])
+
+             
+                 0: begin 
+                    
+                    w1data[1*DWIDTH/4-1:0*DWIDTH/4]    <= #TCQ  SHIFTB_0;
+                    w1data[2*DWIDTH/4-1:1*DWIDTH/4]    <= #TCQ  SHIFTB_1;   //  32                                       
+                    w1data[3*DWIDTH/4-1:2*DWIDTH/4]    <= #TCQ  SHIFTB_2;                    
+                    w1data[4*DWIDTH/4-1:3*DWIDTH/4]    <= #TCQ  SHIFTB_3;
+                    
+                    
+                    end
+                 1:  begin 
+                 
+                    w1data[1*DWIDTH/4-1:0*DWIDTH/4]    <= #TCQ  SHIFTB_4;
+                    w1data[2*DWIDTH/4-1:1*DWIDTH/4]    <= #TCQ  SHIFTB_5;   //  32                                       
+                    w1data[3*DWIDTH/4-1:2*DWIDTH/4]    <= #TCQ  SHIFTB_6;                    
+                    w1data[4*DWIDTH/4-1:3*DWIDTH/4]    <= #TCQ  SHIFTB_7;
+                 
+                    end
+ 
+              default :begin
+                    w1data <= #TCQ  BLANK;    //15:8 
+                    
+                    end
+                    
+             endcase         
+                      
+           end  //(NUM_DQ_PINS == 16) (cmd_startC)      
+         else begin  //shifting
+              if (data_mode_i == 3'b100) 
+               begin
+                 w1data[127:112] <= #TCQ    {16'h0000};
+                 w1data[111:96] <= #TCQ    {w1data[107:96],w1data[111:108]};
+                 w1data[95:80] <= #TCQ    {16'h0000};
+                 w1data[79:64] <= #TCQ    {w1data[75:64],w1data[79:76]};
+
+
+                 w1data[63:48] <= #TCQ    {16'h0000};
+                 w1data[47:32] <= #TCQ    {w1data[43:32],w1data[47:44]};
+                 w1data[31:16] <= #TCQ    {16'h0000};
+                 w1data[15:0] <= #TCQ    {w1data[11:0],w1data[15:12]};
+                 
+               end
+              else begin
+              w1data[DWIDTH - 1:0]             <= #TCQ  {
+                                                    w1data[4*DWIDTH/4 - 9:4*DWIDTH/4 - 16],
+                                                    w1data[4*DWIDTH/4 - 1 :4*DWIDTH/4 - 8],                                                    
+                                                    w1data[4*DWIDTH/4 - 25:4*DWIDTH/4 -32],
+                                                    w1data[4*DWIDTH/4 - 17:4*DWIDTH/4 -24], 
+                                                    
+                                                    w1data[3*DWIDTH/4 - 9:3*DWIDTH/4 - 16],
+                                                    w1data[3*DWIDTH/4 - 1 :3*DWIDTH/4 - 8],                                                                                                        
+                                                    w1data[3*DWIDTH/4 - 25:3*DWIDTH/4 - 32],
+                                                    w1data[3*DWIDTH/4 - 17:3*DWIDTH/4 - 24],
+
+                                                    w1data[2*DWIDTH/4 - 9:2*DWIDTH/4 - 16],
+                                                    w1data[2*DWIDTH/4 - 1 :2*DWIDTH/4 - 8],                                                                                                        
+                                                    w1data[2*DWIDTH/4 - 25:2*DWIDTH/4 - 32],
+                                                    w1data[2*DWIDTH/4 - 17:2*DWIDTH/4 - 24],
+
+
+                                                    w1data[1*DWIDTH/4 - 9:1*DWIDTH/4 - 16],
+                                                    w1data[1*DWIDTH/4 - 1 :1*DWIDTH/4 - 8],                                                    
+                                                    w1data[1*DWIDTH/4 - 25:1*DWIDTH/4 - 32],
+                                                    w1data[1*DWIDTH/4 - 17 :1*DWIDTH/4 - 24]
+                                                    };
+             end
+            
+         end    
+              
+      end  //(DQ_PINS == 16 
+      else if (NUM_DQ_PINS == 8) begin
+         if(cmd_startC)  // loading data pattern according the incoming address
+            begin
+                        if (data_mode_i == 3'b100)  
+                         w1data <= #TCQ    {
+                                          BLANK,SHIFT_7,BLANK,SHIFT_6,
+                                          BLANK,SHIFT_5,BLANK,SHIFT_4,
+                                          BLANK,SHIFT_3,BLANK,SHIFT_2,
+                                          BLANK,SHIFT_1,BLANK,SHIFT_0
+                                          };                        
+                        else
+                       //  w1data <= #TCQ    {32'h8040_2010,32'h0804_0201,32'h8040_2010,32'h0804_0201};
+                         w1data <= #TCQ    {
+                                          SHIFT_7,SHIFT_6,SHIFT_5,SHIFT_4,
+                                          SHIFT_3,SHIFT_2,SHIFT_1,SHIFT_0,
+                                          SHIFT_7,SHIFT_6,SHIFT_5,SHIFT_4,
+                                          SHIFT_3,SHIFT_2,SHIFT_1,SHIFT_0
+                                          };
+                                          
+                                          
+            end // (cmd_startC)   
+        else  // Shifting
+         
+                 begin
+               
+                      w1data <= #TCQ    w1data;//{w1data[96:64], w1data[127:97],w1data[31:0], w1data[63:32]}; 
+                 end // else
+      end //(NUM_DQ_PINS == 8)
+      else  
+         if (data_mode_i == 3'b100)  
+          w1data <= #TCQ    128'h0804_0201_0804_0201_0804_0201_0804_0201;       
+         else
+          w1data <= #TCQ    128'h8421_8421_8421_8421_8421_8421_8421_8421; 
+           
+  end
+end
+endgenerate
+ 
+// HAMMER_PATTERN: Alternating 1s and 0s on DQ pins 
+//                 => the rsing data pattern will be    32'b11111111_11111111_11111111_11111111
+//                 => the falling data pattern will be  32'b00000000_00000000_00000000_00000000
+generate
+if ( DWIDTH == 32 &&( DATA_PATTERN == "DGEN_HAMMER" || DATA_PATTERN == "DGEN_ALL"))  begin : HAMMER_PATTERN_32
+  always @ (posedge clk_i)
+  begin
+    if (rst_i)  
+      hdata <= #TCQ    'd0;
+    else if((fifo_rdy_i && user_burst_cnt != 6'd0) || cmd_startC ) begin
+      if (NUM_DQ_PINS == 16)
+           hdata <= #TCQ    32'h0000_FFFF;
+      else if (NUM_DQ_PINS == 8)
+           hdata <= #TCQ    32'h00FF_00FF;
+      else if (NUM_DQ_PINS == 4)     // NUM_DQ_PINS == 4    
+           hdata <= #TCQ    32'h0F0F_0F0F;
+    end
+  end
+end
+endgenerate
+
+
+generate
+if ( DWIDTH == 64 && (DATA_PATTERN == "DGEN_HAMMER" || DATA_PATTERN == "DGEN_ALL"))  begin : HAMMER_PATTERN_64
+  always @ (posedge clk_i)
+  begin
+    if (rst_i)  
+      hdata <= #TCQ    'd0;
+    else if((fifo_rdy_i && user_burst_cnt != 6'd0) || cmd_startC )
+      if (NUM_DQ_PINS == 16)
+           hdata <= #TCQ    64'h0000FFFF_0000FFFF;
+      else if (NUM_DQ_PINS == 8)
+           hdata <= #TCQ    64'h00FF00FF_00FF00FF;
+      else if (NUM_DQ_PINS == 4)     // NUM_DQ_PINS == 4    
+           hdata <= #TCQ    64'h0F0F_0F0F_0F0F_0F0F;
+    
+  end
+end
+endgenerate
+
+
+generate
+if ( DWIDTH == 128 && (DATA_PATTERN == "DGEN_HAMMER" || DATA_PATTERN == "DGEN_ALL"))  begin : HAMMER_PATTERN_128
+  always @ (posedge clk_i)
+  begin
+    if (rst_i)  
+      hdata <= #TCQ    'd0;
+    else if((fifo_rdy_i && user_burst_cnt != 6'd0) || cmd_startC )
+      if (NUM_DQ_PINS == 16)
+           hdata <= #TCQ    128'h0000FFFF_0000FFFF_0000FFFF_0000FFFF;
+      else if (NUM_DQ_PINS == 8)
+           hdata <= #TCQ    128'h00FF00FF_00FF00FF_00FF00FF_00FF00FF;        
+      else if (NUM_DQ_PINS == 4)     // NUM_DQ_PINS == 4    
+           hdata <= #TCQ    128'h0F0F_0F0F_0F0F_0F0F_0F0F_0F0F_0F0F_0F0F;        
+    
+  end
+end
+endgenerate
+
+
+always @ (w1data,hdata)
+begin
+for (i=0; i <= DWIDTH - 1; i= i+1)
+   ndata[i] = hdata[i] ^ w1data[i];
+   
+         end
+
+
+
+
+// HAMMER_PATTERN_MINUS: generate walking HAMMER  data pattern except 1 bit for the whole burst. The incoming addr_i[5:2] determine 
+// the position of the pin driving oppsite polarity
+//  addr_i[6:2] = 5'h0f ; 32 bit data port
+//                 => the rsing data pattern will be    32'b11111111_11111111_01111111_11111111
+//                 => the falling data pattern will be  32'b00000000_00000000_00000000_00000000
+
+// ADDRESS_PATTERN: use the address as the 1st data pattern for the whole burst. For example
+// Dataport 32 bit width with starting addr_i  = 30'h12345678, user burst length 4
+//                 => the 1st data pattern :     32'h12345678
+//                 => the 2nd data pattern :     32'h12345679
+//                 => the 3rd data pattern :     32'h1234567a
+//                 => the 4th data pattern :     32'h1234567b
+generate
+
+//data_rdy_i
+
+if (DATA_PATTERN == "DGEN_ADDR"  || DATA_PATTERN == "DGEN_ALL")  begin : ADDRESS_PATTERN
+//data_o logic
+always @ (posedge clk_i)
+begin
+  if (cmd_startD) 
+    adata <= #TCQ    addr_i;
+  else if(fifo_rdy_i && data_rdy_i && user_burst_cnt > 6'd1) 
+         if (DWIDTH == 128)
+                 adata <= #TCQ    adata + 16;
+         else if (DWIDTH == 64)
+                 adata <= #TCQ    adata + 8;
+         else     // DWIDTH == 32   
+                 adata <= #TCQ    adata + 4;
+end
+end
+endgenerate
+ 
+ 
+// PRBS_PATTERN: use the address as the PRBS seed data pattern for the whole burst. For example
+// Dataport 32 bit width with starting addr_i = 30'h12345678, user burst length 4
+//                
+
+generate
+if (DATA_PATTERN == "DGEN_PRBS"  || DATA_PATTERN == "DGEN_ALL")  begin : PRBS_PATTERN
+       
+//   PRBS DATA GENERATION
+// xor all the tap positions before feedback to 1st stage.
+
+
+
+assign data_clk_en = fifo_rdy_i && data_rdy_i && user_burst_cnt > 6'd1;
+
+
+data_prbs_gen #
+  (
+    .TCQ        (TCQ),
+    .PRBS_WIDTH (32),  
+    .SEED_WIDTH (32)
+   )
+   data_prbs_gen
+  (
+   .clk_i            (clk_i),
+   .clk_en           (data_clk_en),
+   .rst_i            (rst_i),
+   .prbs_fseed_i     (prbs_fseed_i),
+   .prbs_seed_init   (cmd_startE),
+   .prbs_seed_i      (addr_i[31:0]),
+   .prbs_o           (prbs_data)
+
+  );       
+end        
+endgenerate
+
+ 
+endmodule 

Frogwells_fpga_design/基于FPGA、DDR3和USB2.0的图像采集系统/debug/ddr_test/rtl/traffic_gen/tg_status.v

@@ -0,0 +1,128 @@
+//*****************************************************************************
+// (c) Copyright 2008-2009 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+//*****************************************************************************
+//   ____  ____
+//  /   /\/   /
+// /___/  \  /    Vendor: Xilinx
+// \   \   \/     Version: %version
+//  \   \         Application: MIG
+//  /   /         Filename: tg_status.v
+// /___/   /\     Date Last Modified: 
+// \   \  /  \    Date Created: 
+//  \___\/\___\
+//
+//Device: Spartan6
+//Design Name: DDR/DDR2/DDR3/LPDDR 
+//Purpose:  This module compare the memory read data agaisnt compare data that generated from data_gen module.
+//          Error signal will be asserted if the comparsion is not equal.
+//Reference:
+//Revision History:
+//*****************************************************************************
+
+`timescale 1ps/1ps
+
+
+module tg_status #(
+   parameter TCQ           = 100,  
+
+   parameter DWIDTH = 32
+    )
+    (
+      
+   
+   input                            clk_i  ,        
+   input                            rst_i ,
+   input                            manual_clear_error,
+   input                            data_error_i ,  
+   input [DWIDTH-1:0]               cmp_data_i,     
+   input [DWIDTH-1:0]               rd_data_i ,     
+   input [31:0]                     cmp_addr_i ,    
+   input [5:0]                      cmp_bl_i ,      
+   input                            mcb_cmd_full_i ,
+   input                            mcb_wr_full_i,  
+   input                            mcb_rd_empty_i, 
+   output reg [64 + (2*DWIDTH - 1):0]   error_status,   
+   output                           error                  
+  );
+
+reg data_error_r;
+reg error_set;
+assign  error = error_set;
+
+always @ (posedge clk_i)
+    data_error_r <= #TCQ  data_error_i;
+
+always @ (posedge clk_i)
+begin
+
+if (rst_i || manual_clear_error) begin
+   error_status <= #TCQ  'b0;
+   error_set    <= #TCQ  1'b0;
+end
+else begin
+  // latch the first error only
+  if (data_error_i && ~data_error_r && ~error_set ) begin
+     error_status[31:0]  <= #TCQ  cmp_addr_i;
+     error_status[37:32] <= #TCQ  cmp_bl_i;
+     error_status[40] <= #TCQ  mcb_cmd_full_i;
+     error_status[41] <= #TCQ  mcb_wr_full_i;
+     error_status[42] <= #TCQ  mcb_rd_empty_i;
+     error_set <= #TCQ  1'b1;
+     error_status[64 + (DWIDTH - 1)  :64]           <= #TCQ  cmp_data_i;
+     error_status[64 + (2*DWIDTH - 1):64 + DWIDTH]  <= #TCQ  rd_data_i;
+   
+  end
+
+  error_status[39:38]  <= #TCQ  'b0;    // reserved
+  error_status[63:43] <= #TCQ  'b0;    // reserved
+
+
+end end
+    
+endmodule 
+

Frogwells_fpga_design/基于FPGA、DDR3和USB2.0的图像采集系统/debug/ddr_test/rtl/traffic_gen/wr_data_gen.v

@@ -0,0 +1,410 @@
+//*****************************************************************************
+// (c) Copyright 2008-2009 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+//*****************************************************************************
+//   ____  ____
+//  /   /\/   /
+// /___/  \  /    Vendor: Xilinx
+// \   \   \/     Version: %version
+//  \   \         Application: MIG
+//  /   /         Filename: wr_data_gen.v
+// /___/   /\     Date Last Modified: 
+// \   \  /  \    Date Created: 
+//  \___\/\___\
+//
+//Device: Spartan6
+//Design Name: DDR/DDR2/DDR3/LPDDR 
+//Purpose:
+//Reference:
+//Revision History:
+//*****************************************************************************
+
+`timescale 1ps/1ps
+
+module wr_data_gen #
+ 
+(  
+   parameter TCQ           = 100,  
+   parameter FAMILY = "SPARTAN6", // "SPARTAN6", "VIRTEX6"
+   parameter MEM_BURST_LEN = 8,
+
+   parameter MODE  = "WR", //"WR", "RD"
+   parameter ADDR_WIDTH = 32,
+   parameter BL_WIDTH = 6,
+   parameter DWIDTH = 32,
+   parameter DATA_PATTERN = "DGEN_PRBS", //"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"  
+   parameter NUM_DQ_PINS   = 8,
+   parameter SEL_VICTIM_LINE = 3,  // VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
+   
+   parameter COLUMN_WIDTH = 10,
+   parameter EYE_TEST   = "FALSE"
+   
+ )
+ (
+   input   clk_i,                 //
+   input [4:0]  rst_i, 
+   input [31:0] prbs_fseed_i,
+   
+   input [3:0]  data_mode_i,   // "00" = bram; 
+   
+   output  cmd_rdy_o,             // ready to receive command. It should assert when data_port is ready at the                                        // beginning and will be deasserted once see the cmd_valid_i is asserted. 
+                                  // And then it should reasserted when 
+                                  // it is generating the last_word.
+   input   cmd_valid_i,           // when both cmd_valid_i and cmd_rdy_o is high, the command  is valid.
+   input   cmd_validB_i, 
+   input   cmd_validC_i, 
+   
+   output  last_word_o,   
+   
+ //  input [5:0] port_data_counts_i,// connect to data port fifo counts
+//   input [ADDR_WIDTH-1:0] m_addr_i,
+   input [DWIDTH-1:0] fixed_data_i,   
+
+   input [ADDR_WIDTH-1:0] addr_i, // generated address used to determine data pattern.
+   input [BL_WIDTH-1:0]   bl_i,   // generated burst length for control the burst data
+   
+   input   data_rdy_i,          // connect from mcb_wr_full when used as wr_data_gen
+                                 // connect from mcb_rd_empty when used as rd_data_gen
+                                 // When both data_rdy and data_valid is asserted, the ouput data is valid.
+   output    data_valid_o,        // connect to wr_en or rd_en and is asserted whenever the 
+                                 // pattern is available.
+   output  [DWIDTH-1:0] data_o, // generated data pattern   
+   output  reg          data_wr_end_o
+   
+   
+);  
+// 
+
+
+reg [DWIDTH-1:0] data;
+
+
+
+(*EQUIVALENT_REGISTER_REMOVAL="NO"*) reg   cmd_rdy,cmd_rdyB, cmd_rdyC,cmd_rdyD,cmd_rdyE,cmd_rdyF;
+(*EQUIVALENT_REGISTER_REMOVAL="NO"*) reg   cmd_start,cmd_startB,cmd_startC,cmd_startD,cmd_startE,cmd_startF;
+
+
+
+
+reg burst_count_reached2;
+
+reg               data_valid;
+reg [6:0]user_burst_cnt;
+reg [2:0] walk_cnt;
+
+wire fifo_not_full;
+integer i,j;
+reg [31:0] w3data;
+
+assign fifo_not_full = data_rdy_i;
+
+always @( posedge clk_i)
+begin
+if ((user_burst_cnt == 2 || (cmd_start && bl_i == 1 && FAMILY == "VIRTEX6")) && (fifo_not_full))
+    data_wr_end_o <= #TCQ  1'b1;
+else
+    data_wr_end_o <= #TCQ  1'b0;
+end
+
+always @ (posedge clk_i)
+begin
+cmd_start  <= #TCQ  cmd_validC_i & cmd_rdyC ;
+cmd_startB <= #TCQ  cmd_valid_i & cmd_rdyB;
+cmd_startC <= #TCQ  cmd_validB_i & cmd_rdyC;
+cmd_startD <= #TCQ  cmd_validB_i & cmd_rdyD;  
+cmd_startE <= #TCQ  cmd_validB_i & cmd_rdyE;  
+cmd_startF <= #TCQ  cmd_validB_i & cmd_rdyF;  
+end
+
+
+// counter to count user burst length
+always @( posedge clk_i)
+begin
+  if ( rst_i[0] )
+    user_burst_cnt <= #TCQ 'd0;
+  else if(cmd_start) 
+    if (FAMILY == "SPARTAN6") begin
+       if (bl_i == 6'b000000)
+          user_burst_cnt <= #TCQ 7'b1000000;
+       else
+     user_burst_cnt <= #TCQ bl_i;
+       
+       end
+        else
+     user_burst_cnt <= #TCQ bl_i;
+  else if(fifo_not_full) 
+     if (user_burst_cnt != 6'd0)
+       user_burst_cnt <= #TCQ user_burst_cnt - 1'b1;
+     else
+        user_burst_cnt <=#TCQ 'd0;
+        
+end
+
+reg u_bcount_2;
+wire last_word_t;
+always @ (posedge clk_i)
+begin
+if ((user_burst_cnt == 2  && fifo_not_full )|| (cmd_startC && bl_i == 1))
+    u_bcount_2 <= #TCQ 1'b1;
+else if (last_word_o)
+    u_bcount_2 <= #TCQ 1'b0;
+end    
+
+
+
+assign  last_word_o = u_bcount_2 & fifo_not_full;
+
+// cmd_rdy_o assert when the dat fifo is not full and deassert once cmd_valid_i
+// is assert and reassert during the last data
+
+assign cmd_rdy_o = cmd_rdy & fifo_not_full;
+
+
+always @( posedge clk_i)
+begin
+  if ( rst_i[0] )
+    cmd_rdy <= #TCQ 1'b1;
+  else if (cmd_start)
+     if (bl_i == 1)
+        cmd_rdy <= #TCQ 1'b1;
+     else
+       cmd_rdy <= #TCQ 1'b0;
+  else if  ((user_burst_cnt == 6'd2 && fifo_not_full ) )
+
+      cmd_rdy <= #TCQ 1'b1;
+  
+
+end
+
+always @( posedge clk_i)
+begin
+  if ( rst_i [0])
+    cmd_rdyB <= #TCQ 1'b1;
+  else if (cmd_startB)
+     if (bl_i == 1)
+        cmd_rdyB <= #TCQ 1'b1;
+     else
+       cmd_rdyB <= #TCQ 1'b0;
+  else if  ((user_burst_cnt == 6'd2 && fifo_not_full ) )
+
+
+      cmd_rdyB <= #TCQ 1'b1;
+  
+
+end
+
+always @( posedge clk_i)
+begin
+  if ( rst_i[0] )
+    cmd_rdyC <= #TCQ 1'b1;
+  else if (cmd_startC)
+     if (bl_i == 1)
+        cmd_rdyC <= #TCQ 1'b1;
+     else
+       cmd_rdyC <= #TCQ 1'b0;
+  else if  ((user_burst_cnt == 6'd2 && fifo_not_full ) )
+
+
+      cmd_rdyC <= #TCQ 1'b1;
+  
+
+end
+
+always @( posedge clk_i)
+begin
+  if ( rst_i[0] )
+    cmd_rdyD <= #TCQ 1'b1;
+  else if (cmd_startD)
+     if (bl_i == 1)
+        cmd_rdyD <= #TCQ  1'b1;
+     else
+       cmd_rdyD <= #TCQ 1'b0;
+  else if  ((user_burst_cnt == 6'd2 && fifo_not_full ) ) 
+
+
+      cmd_rdyD <= #TCQ 1'b1;
+  
+
+end
+
+always @( posedge clk_i)
+begin
+  if ( rst_i[0] )
+    cmd_rdyE <= #TCQ 1'b1;
+  else if (cmd_startE)
+     if (bl_i == 1)
+        cmd_rdyE <= #TCQ 1'b1;
+     else
+       cmd_rdyE <= #TCQ 1'b0;
+  else if  ((user_burst_cnt == 6'd2 && fifo_not_full ) ) 
+
+
+      cmd_rdyE <= #TCQ 1'b1;
+  
+
+end
+
+
+
+always @( posedge clk_i)
+begin
+  if ( rst_i[0] )
+    cmd_rdyF <= #TCQ 1'b1;
+  else if (cmd_startF)
+     if (bl_i == 1)
+        cmd_rdyF <= #TCQ 1'b1;
+     else
+       cmd_rdyF <= #TCQ 1'b0;
+  else if  ((user_burst_cnt == 6'd2 && fifo_not_full ) )
+
+      cmd_rdyF <= #TCQ 1'b1;
+  
+
+end
+
+
+
+always @ (posedge clk_i)
+begin
+  if (rst_i[1])  
+    data_valid <= #TCQ 'd0;
+  else if(cmd_start) 
+    data_valid <= #TCQ 1'b1;
+  else if (fifo_not_full && user_burst_cnt <= 6'd1)  
+    data_valid <= #TCQ 1'b0;
+end
+
+assign data_valid_o = data_valid & fifo_not_full;
+
+
+generate
+if (FAMILY == "SPARTAN6")  begin : SP6_WDGEN
+
+sp6_data_gen #
+ 
+( 
+   .TCQ             (TCQ),
+   .ADDR_WIDTH      (32 ),
+   
+   .BL_WIDTH        (BL_WIDTH       ),
+   .DWIDTH          (DWIDTH       ),
+   .DATA_PATTERN    (DATA_PATTERN  ),
+   .NUM_DQ_PINS      (NUM_DQ_PINS  ),
+   .COLUMN_WIDTH     (COLUMN_WIDTH)
+   
+ )
+ sp6_data_gen
+ (
+   .clk_i              (clk_i         ),        
+   .rst_i              (rst_i[1]         ), 
+   .data_rdy_i         (data_rdy_i    ),
+   .prbs_fseed_i       (prbs_fseed_i),
+   
+   .data_mode_i        (data_mode_i   ),  
+   .cmd_startA         (cmd_start    ),  
+   .cmd_startB         (cmd_startB    ),   
+   .cmd_startC         (cmd_startC    ),   
+   .cmd_startD         (cmd_startD    ),   
+   .cmd_startE         (cmd_startE    ),   
+   .fixed_data_i         (fixed_data_i),
+   
+   .addr_i             (addr_i        ),       
+   .user_burst_cnt     (user_burst_cnt),
+   .fifo_rdy_i         (fifo_not_full    ),   
+   .data_o             (data_o        )  
+  );
+end
+
+
+endgenerate
+
+generate
+if (FAMILY ==  "VIRTEX6")  begin : V6_WDGEN
+
+v6_data_gen #                                 
+ 
+(  
+   .TCQ               (TCQ),
+   .ADDR_WIDTH      (32 ),
+   .BL_WIDTH        (BL_WIDTH       ),
+   .DWIDTH          (DWIDTH       ),
+   .MEM_BURST_LEN     (MEM_BURST_LEN),
+   
+   .DATA_PATTERN    (DATA_PATTERN  ),
+   .NUM_DQ_PINS      (NUM_DQ_PINS  ),
+   .SEL_VICTIM_LINE   (SEL_VICTIM_LINE),
+   
+   .COLUMN_WIDTH     (COLUMN_WIDTH),
+    .EYE_TEST   (EYE_TEST)
+   
+ )                 
+ v6_data_gen
+ (
+   .clk_i              (clk_i         ),        
+   .rst_i              (rst_i[1]      ),
+   .data_rdy_i         (data_rdy_i    ),
+   .prbs_fseed_i       (prbs_fseed_i),
+   
+   .data_mode_i        (data_mode_i   ),  
+   .cmd_startA         (cmd_start    ),  
+   .cmd_startB         (cmd_startB    ),   
+   .cmd_startC         (cmd_startC    ),   
+   .cmd_startD         (cmd_startD    ),   
+   .cmd_startE         (cmd_startE    ),   
+   .m_addr_i           (addr_i/*m_addr_i*/),          
+   .fixed_data_i         (fixed_data_i),
+
+   .addr_i             (addr_i        ),       
+   .user_burst_cnt     (user_burst_cnt),
+   .fifo_rdy_i         (fifo_not_full    ),   
+   .data_o             (data_o        )
+  );
+end
+endgenerate
+
+ 
+endmodule 

Frogwells_fpga_design/基于FPGA、DDR3和USB2.0的图像采集系统/debug/ddr_test/rtl/traffic_gen/write_data_path.v

@@ -0,0 +1,157 @@
+//*****************************************************************************
+// (c) Copyright 2008-2009 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+//*****************************************************************************
+//   ____  ____
+//  /   /\/   /
+// /___/  \  /    Vendor: Xilinx
+// \   \   \/     Version: %version
+//  \   \         Application: MIG
+//  /   /         Filename: write_data_path.v
+// /___/   /\     Date Last Modified: 
+// \   \  /  \    Date Created: 
+//  \___\/\___\
+//
+//Device: Spartan6
+//Design Name: DDR/DDR2/DDR3/LPDDR 
+//Purpose: This is top level of write path . 
+
+//Reference:
+//Revision History:
+//*****************************************************************************
+
+`timescale 1ps/1ps
+
+
+module write_data_path #(
+   parameter TCQ           = 100,  
+   parameter FAMILY = "SPARTAN6",
+   parameter ADDR_WIDTH = 32,
+   parameter MEM_BURST_LEN = 8,
+   parameter DWIDTH = 32,
+   parameter DATA_PATTERN = "DGEN_ALL", //"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL"  
+   parameter NUM_DQ_PINS   = 8,
+   parameter SEL_VICTIM_LINE = 3,  // VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern
+   
+   parameter MEM_COL_WIDTH = 10,
+   parameter EYE_TEST   = "FALSE"
+   
+    )
+    (
+   
+   input     clk_i, 
+   input [9:0]    rst_i,
+   output    cmd_rdy_o, 
+   input     cmd_valid_i, 
+   input     cmd_validB_i, 
+   input     cmd_validC_i, 
+   input [31:0] prbs_fseed_i,
+   input [3:0]  data_mode_i,
+//   input [31:0] m_addr_i,
+   input [DWIDTH-1:0]     fixed_data_i,    
+
+   input [31:0] addr_i, 
+   input [5:0]   bl_i,
+
+//   input [5:0]            port_data_counts_i,// connect to data port fifo counts
+   
+   input                  data_rdy_i, 
+   output                 data_valid_o,
+   output                 last_word_wr_o,
+   output [DWIDTH-1:0] data_o,   
+   output [(DWIDTH/8) - 1:0] data_mask_o,
+   output                    data_wr_end_o
+   
+   );
+
+wire data_valid;
+reg cmd_rdy;
+
+  assign data_valid_o = data_valid & data_rdy_i;          
+  assign data_mask_o = 'b0;  // for now 
+         
+
+   wr_data_gen #(
+              .TCQ               (TCQ),
+              .FAMILY            (FAMILY),
+              .NUM_DQ_PINS       (NUM_DQ_PINS), 
+              .MEM_BURST_LEN     (MEM_BURST_LEN),
+              
+              .SEL_VICTIM_LINE   (SEL_VICTIM_LINE),
+              .DATA_PATTERN  (DATA_PATTERN),
+              .DWIDTH           (DWIDTH),
+              .COLUMN_WIDTH     (MEM_COL_WIDTH),
+              .EYE_TEST         (EYE_TEST)
+              
+              )
+   wr_data_gen(
+            .clk_i              (clk_i          ),
+            .rst_i              (rst_i[9:5]),
+            .prbs_fseed_i       (prbs_fseed_i),
+            
+            .data_mode_i        (data_mode_i    ),
+            .cmd_rdy_o          (cmd_rdy_o      ),
+            .cmd_valid_i        (cmd_valid_i    ),
+            .cmd_validB_i        (cmd_validB_i    ),
+            .cmd_validC_i        (cmd_validC_i    ),
+            
+            .last_word_o        (last_word_wr_o ),
+       //     .port_data_counts_i (port_data_counts_i),
+//            .m_addr_i             (m_addr_i         ),
+            .fixed_data_i         (fixed_data_i),
+       
+            .addr_i             (addr_i         ),
+            .bl_i               (bl_i           ),
+            .data_rdy_i         (data_rdy_i     ),
+            .data_valid_o       ( data_valid  ),
+            .data_o             (data_o         ),
+            .data_wr_end_o         (data_wr_end_o)
+            );
+   
+   
+   
+endmodule 

Frogwells_fpga_design/基于FPGA、DDR3和USB2.0的图像采集系统/debug/ddr_test/sim/functional/isim.tcl

@@ -0,0 +1,72 @@
+###############################################################################
+## (c) Copyright 2009 Xilinx, Inc. All rights reserved.
+##
+## This file contains confidential and proprietary information
+## of Xilinx, Inc. and is protected under U.S. and
+## international copyright and other intellectual property
+## laws.
+##
+## DISCLAIMER
+## This disclaimer is not a license and does not grant any
+## rights to the materials distributed herewith. Except as
+## otherwise provided in a valid license issued to you by
+## Xilinx, and to the maximum extent permitted by applicable
+## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+## (2) Xilinx shall not be liable (whether in contract or tort,
+## including negligence, or under any other theory of
+## liability) for any loss or damage of any kind or nature
+## related to, arising under or in connection with these
+## materials, including for any direct, or any indirect,
+## special, incidental, or consequential loss or damage
+## (including loss of data, profits, goodwill, or any type of
+## loss or damage suffered as a result of any action brought
+## by a third party) even if such damage or loss was
+## reasonably foreseeable or Xilinx had been advised of the
+## possibility of the same.
+##
+## CRITICAL APPLICATIONS
+## Xilinx products are not designed or intended to be fail-
+## safe, or for use in any application requiring fail-safe
+## performance, such as life-support or safety devices or
+## systems, Class III medical devices, nuclear facilities,
+## applications related to the deployment of airbags, or any
+## other applications that could lead to death, personal
+## injury, or severe property or environmental damage
+## (individually and collectively, "Critical
+## Applications"). Customer assumes the sole risk and
+## liability of any use of Xilinx products in Critical
+## Applications, subject only to applicable laws and
+## regulations governing limitations on product liability.
+##
+## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+## PART OF THIS FILE AT ALL TIMES.
+##
+###############################################################################
+##   ____  ____
+##  /   /\/   /
+## /___/  \  /    Vendor             : Xilinx
+## \   \   \/     Version            : 3.92
+##  \   \         Application	     : MIG
+##  /   /         Filename           : isim.tcl
+## /___/   /\     Date Last Modified : $Date: 2011/06/02 07:16:58 $
+## \   \  /  \    Date Created       : Mon Mar 2 2009
+##  \___\/\___\
+##
+## Device          : Spartan-6
+## Design Name     : DDR/DDR2/DDR3/LPDDR
+## Purpose         : To give commands to ISIM Simulator through batch mode
+## Assumptions:
+##      - Simulation takes place in \sim folder of MIG output directory
+## Reference       :
+## Revision History:
+###############################################################################
+
+onerror {resume}
+isim set radix hex
+wave add /sim_tb_top
+run 200 us
+quit

Frogwells_fpga_design/基于FPGA、DDR3和USB2.0的图像采集系统/debug/ddr_test/sim/functional/readme.txt

@@ -0,0 +1,122 @@
+###############################################################################
+## (c) Copyright 2009 Xilinx, Inc. All rights reserved.
+##
+## This file contains confidential and proprietary information
+## of Xilinx, Inc. and is protected under U.S. and
+## international copyright and other intellectual property
+## laws.
+##
+## DISCLAIMER
+## This disclaimer is not a license and does not grant any
+## rights to the materials distributed herewith. Except as
+## otherwise provided in a valid license issued to you by
+## Xilinx, and to the maximum extent permitted by applicable
+## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+## (2) Xilinx shall not be liable (whether in contract or tort,
+## including negligence, or under any other theory of
+## liability) for any loss or damage of any kind or nature
+## related to, arising under or in connection with these
+## materials, including for any direct, or any indirect,
+## special, incidental, or consequential loss or damage
+## (including loss of data, profits, goodwill, or any type of
+## loss or damage suffered as a result of any action brought
+## by a third party) even if such damage or loss was
+## reasonably foreseeable or Xilinx had been advised of the
+## possibility of the same.
+##
+## CRITICAL APPLICATIONS
+## Xilinx products are not designed or intended to be fail-
+## safe, or for use in any application requiring fail-safe
+## performance, such as life-support or safety devices or
+## systems, Class III medical devices, nuclear facilities,
+## applications related to the deployment of airbags, or any
+## other applications that could lead to death, personal
+## injury, or severe property or environmental damage
+## (individually and collectively, "Critical
+## Applications"). Customer assumes the sole risk and
+## liability of any use of Xilinx products in Critical
+## Applications, subject only to applicable laws and
+## regulations governing limitations on product liability.
+##
+## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+## PART OF THIS FILE AT ALL TIMES.
+##
+###############################################################################
+##   ____  ____
+##  /   /\/   /
+## /___/  \  /    Vendor             : Xilinx
+## \   \   \/     Version            : 3.92
+##  \   \         Application	     : MIG
+##  /   /         Filename           : readme.txt
+## /___/   /\     Date Last Modified : $Date: 2011/06/02 07:16:58 $
+## \   \  /  \    Date Created       : Mon Oct 19 2009
+##  \___\/\___\
+##
+## Device          : Spartan-6
+## Design Name     : DDR/DDR2/DDR3/LPDDR
+## Purpose         : Steps to run simulation using ISIM/Modelsim simualtor in this folder
+## Assumptions:
+##      - Simulation takes place in \sim\<functional/timing> folder of MIG output directory
+## Reference       :
+## Revision History:
+###############################################################################
+
+The sim/functional folder has files to perform functional simulation of the design.
+
+1. Simulation using Modelsim simulator
+
+A) sim.do File :
+   
+   1) The 'sim.do' file has commands to compile and simulate memory interface
+      design and run the simulation for specified period of time. 
+    
+   2) It has the syntax to Map the required libraries.
+      Also, $XILINX environment variable must be set in order to compile glbl.v file
+
+   3) Displays the waveforms that are listed with "add wave" command.
+     
+B) Steps to run the Modelsim simulation:
+
+   1) The user should invoke the Modelsim simulator GUI.
+   2) Change the present working directory path to the sim/functional folder.
+      In Transcript window, at Modelsim prompt, type the following command to 
+      change directory path.
+           cd <sim/functional directory path>
+
+   2) Run the simulation using sim.do file.
+      At Modelsim prompt, type the following command:
+           do sim.do      
+
+   3) To exit simulation, type the following command at Modelsim prompt:
+           quit -f
+
+   4) Verify the transcript file for the memory transactions.
+
+
+2. Simulation using ISIM simulator
+  
+A) Following files are provided :
+   
+   1) The '.prj' file contains the list of all the files associated with the design.
+      It also contains the hdl, library and the source file name.       
+    
+   2) The '.tcl' file contains the Tcl commands for simulation and 
+      resume on error. 
+
+   3) The 'isim.bat' has commands which use '.prj' and '.tcl' files. 
+
+     
+B) Steps to run the ISIM simulation:
+
+   The user should execute the file isim.bat, which does the following steps:
+   1) Compiles, elaborates the design and generates the simulation executable using
+      the fuse command in 'isim.bat' file.
+
+   2) Invokes the ISIM GUI.
+
+   3) User can add required signals from objects window to the waveform viewer and run 
+      simulation for specified time using the command "run <time>" in ISIM GUI.

Frogwells_fpga_design/基于FPGA、DDR3和USB2.0的图像采集系统/debug/ddr_test/sim/functional/sim_tb_top.v

@@ -0,0 +1,300 @@
+//*****************************************************************************
+// (c) Copyright 2009 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+//*****************************************************************************
+//   ____  ____
+//  /   /\/   /
+// /___/  \  /   Vendor             : Xilinx
+// \   \   \/    Version            : 3.92
+//  \   \        Application        : MIG
+//  /   /        Filename           : sim_tb_top.v
+// /___/   /\    Date Last Modified : $Date: 2011/06/02 07:16:58 $
+// \   \  /  \   Date Created       : Mon Mar 2 2009
+//  \___\/\___\
+//
+// Device      : Spartan-6
+// Design Name : DDR/DDR2/DDR3/LPDDR
+// Purpose     : This is the simulation testbench which is used to verify the
+//               design. The basic clocks and resets to the interface are
+//               generated here. This also connects the memory interface to the
+//               memory model.
+//*****************************************************************************
+
+`timescale 1ps/1ps
+module sim_tb_top;
+
+// ========================================================================== //
+// Parameters                                                                 //
+// ========================================================================== //
+   parameter DEBUG_EN                = 0;
+   localparam DBG_WR_STS_WIDTH       = 32;
+   localparam DBG_RD_STS_WIDTH       = 32;
+   localparam  C3_P1_MASK_SIZE           =16;
+   localparam  C3_P1_DATA_PORT_SIZE      =128;
+   	parameter C3_MEMCLK_PERIOD     = 3200;
+   parameter C3_RST_ACT_LOW        = 0;
+   parameter C3_INPUT_CLK_TYPE     = "SINGLE_ENDED";
+   parameter C3_NUM_DQ_PINS        = 16;
+   parameter C3_MEM_ADDR_WIDTH     = 14;
+   parameter C3_MEM_BANKADDR_WIDTH = 3;
+   parameter C3_MEM_ADDR_ORDER     = "ROW_BANK_COLUMN"; 
+      parameter C3_P0_MASK_SIZE       = 16;
+   parameter C3_P0_DATA_PORT_SIZE  = 128;
+   parameter C3_CALIB_SOFT_IP      = "TRUE";
+   parameter C3_SIMULATION      = "TRUE";
+   parameter C3_HW_TESTING      = "FALSE";
+
+// ========================================================================== //
+// Signal Declarations                                                        //
+// ========================================================================== //
+ // Clocks
+   reg                              c3_sys_clk;
+   wire                             c3_sys_clk_p;
+   wire                             c3_sys_clk_n;
+// System Reset
+   reg                              c3_sys_rst;
+   wire                             c3_sys_rst_i;
+
+// Design-Top Port Map   
+   wire [C3_MEM_ADDR_WIDTH-1:0]    mcb3_dram_a;
+   wire [C3_MEM_BANKADDR_WIDTH-1:0]  mcb3_dram_ba;  
+   wire                             mcb3_dram_ck;  
+   wire                             mcb3_dram_ck_n;
+   wire [C3_NUM_DQ_PINS-1:0]        mcb3_dram_dq;   
+   wire                             mcb3_dram_dqs;  
+   wire                             mcb3_dram_dqs_n;
+   wire                             mcb3_dram_dm; 
+   wire                             mcb3_dram_ras_n; 
+   wire                             mcb3_dram_cas_n; 
+   wire                             mcb3_dram_we_n;  
+   wire                             mcb3_dram_cke; 
+   wire                             mcb3_dram_odt;
+   wire                             mcb3_dram_reset_n; 
+
+   wire                             mcb3_dram_udqs;    // for X16 parts
+   wire                             mcb3_dram_udqs_n;  // for X16 parts
+   wire                             mcb3_dram_udm;     // for X16 parts
+
+// Error & Calib Signals
+   wire                             error;
+   wire                             calib_done;
+   wire				    rzq3;   wire				    zio3;
+   
+// ========================================================================== //
+// Clocks Generation                                                          //
+// ========================================================================== //
+
+   initial
+      c3_sys_clk = 1'b0;
+   always
+      #(C3_MEMCLK_PERIOD/2) c3_sys_clk = ~c3_sys_clk;
+
+   assign                c3_sys_clk_p = c3_sys_clk;
+   assign                c3_sys_clk_n = ~c3_sys_clk;
+
+// ========================================================================== //
+// Reset Generation                                                           //
+// ========================================================================== //
+ 
+   initial begin
+      c3_sys_rst = 1'b0;		
+      #20000;
+      c3_sys_rst = 1'b1;
+   end
+   assign c3_sys_rst_i = C3_RST_ACT_LOW ? c3_sys_rst : ~c3_sys_rst;
+
+// ========================================================================== //
+// Error Grouping                                                           //
+// ========================================================================== //
+
+
+
+
+   
+
+   
+   // The PULLDOWN component is connected to the ZIO signal primarily to avoid the
+// unknown state in simulation. In real hardware, ZIO should be a no connect(NC) pin.
+   PULLDOWN zio_pulldown3 (.O(zio3));   PULLDOWN rzq_pulldown3 (.O(rzq3));
+   
+
+// ========================================================================== //
+// DESIGN TOP INSTANTIATION                                                    //
+// ========================================================================== //
+
+
+
+example_top #(
+
+.C3_P0_MASK_SIZE       (C3_P0_MASK_SIZE      ),
+.C3_P0_DATA_PORT_SIZE  (C3_P0_DATA_PORT_SIZE ),
+.C3_MEMCLK_PERIOD      (C3_MEMCLK_PERIOD),
+.C3_RST_ACT_LOW        (C3_RST_ACT_LOW),
+.C3_INPUT_CLK_TYPE     (C3_INPUT_CLK_TYPE),
+
+ 
+.DEBUG_EN              (DEBUG_EN),
+
+.C3_MEM_ADDR_ORDER     (C3_MEM_ADDR_ORDER    ),
+.C3_NUM_DQ_PINS        (C3_NUM_DQ_PINS       ),
+.C3_MEM_ADDR_WIDTH     (C3_MEM_ADDR_WIDTH    ),
+.C3_MEM_BANKADDR_WIDTH (C3_MEM_BANKADDR_WIDTH),
+
+.C3_HW_TESTING         (C3_HW_TESTING),
+.C3_SIMULATION         (C3_SIMULATION),
+.C3_CALIB_SOFT_IP      (C3_CALIB_SOFT_IP )
+)
+design_top (
+
+    .c3_sys_clk           (c3_sys_clk),
+  .c3_sys_rst_i           (c3_sys_rst_i),                        
+
+  .mcb3_dram_dq           (mcb3_dram_dq),  
+  .mcb3_dram_a            (mcb3_dram_a),  
+  .mcb3_dram_ba           (mcb3_dram_ba),
+  .mcb3_dram_ras_n        (mcb3_dram_ras_n),                        
+  .mcb3_dram_cas_n        (mcb3_dram_cas_n),                        
+  .mcb3_dram_we_n         (mcb3_dram_we_n),                          
+  .mcb3_dram_odt          (mcb3_dram_odt),
+  .mcb3_dram_cke          (mcb3_dram_cke),                          
+  .mcb3_dram_ck           (mcb3_dram_ck),                          
+  .mcb3_dram_ck_n         (mcb3_dram_ck_n),       
+  .mcb3_dram_dqs          (mcb3_dram_dqs),                          
+  .mcb3_dram_dqs_n        (mcb3_dram_dqs_n),
+    .calib_done                               (calib_done),
+  .error                                    (error),	
+  .mcb3_dram_udqs         (mcb3_dram_udqs),    // for X16 parts                        
+  .mcb3_dram_udqs_n       (mcb3_dram_udqs_n),  // for X16 parts
+  .mcb3_dram_udm          (mcb3_dram_udm),     // for X16 parts
+  .mcb3_dram_dm           (mcb3_dram_dm),
+     .mcb3_rzq               (rzq3),  
+        
+     .mcb3_zio               (zio3),
+	
+  .mcb3_dram_reset_n      (mcb3_dram_reset_n)
+);      
+
+
+
+// ========================================================================== //
+// Memory model instances                                                     // 
+// ========================================================================== //
+
+   generate
+   if(C3_NUM_DQ_PINS == 16) begin : MEM_INST3
+     ddr3_model_c3 u_mem_c3(
+      .ck         (mcb3_dram_ck),
+      .ck_n       (mcb3_dram_ck_n),
+      .cke        (mcb3_dram_cke),
+      .cs_n       (1'b0),
+      .ras_n      (mcb3_dram_ras_n),
+      .cas_n      (mcb3_dram_cas_n),
+      .we_n       (mcb3_dram_we_n),
+      .dm_tdqs    ({mcb3_dram_udm,mcb3_dram_dm}),
+      .ba         (mcb3_dram_ba),
+      .addr       (mcb3_dram_a),
+      .dq         (mcb3_dram_dq),
+      .dqs        ({mcb3_dram_udqs,mcb3_dram_dqs}),
+      .dqs_n      ({mcb3_dram_udqs_n,mcb3_dram_dqs_n}),
+      .tdqs_n     (),
+      .odt        (mcb3_dram_odt),
+      .rst_n      (mcb3_dram_reset_n)
+      );
+   end else begin
+     ddr3_model_c3 u_mem_c3(
+      .ck         (mcb3_dram_ck),
+      .ck_n       (mcb3_dram_ck_n),
+      .cke        (mcb3_dram_cke),
+      .cs_n       (1'b0),
+      .ras_n      (mcb3_dram_ras_n),
+      .cas_n      (mcb3_dram_cas_n),
+      .we_n       (mcb3_dram_we_n),
+      .dm_tdqs    (mcb3_dram_dm),
+      .ba         (mcb3_dram_ba),
+      .addr       (mcb3_dram_a),
+      .dq         (mcb3_dram_dq),
+      .dqs        (mcb3_dram_dqs),
+      .dqs_n      (mcb3_dram_dqs_n),
+      .tdqs_n     (),
+      .odt        (mcb3_dram_odt),
+      .rst_n      (mcb3_dram_reset_n)
+     );
+  end
+endgenerate
+
+// ========================================================================== //
+// Reporting the test case status 
+// ========================================================================== //
+   initial
+   begin : Logging
+      fork
+         begin : calibration_done
+            wait (calib_done);
+            $display("Calibration Done");
+            #50000000;
+            if (!error) begin
+               $display("TEST PASSED");
+            end   
+            else begin
+               $display("TEST FAILED: DATA ERROR");		 
+            end
+            disable calib_not_done;
+	    $finish;
+         end	 
+         
+         begin : calib_not_done
+            #200000000;
+            if (!calib_done) begin
+               $display("TEST FAILED: INITIALIZATION DID NOT COMPLETE");
+            end
+            disable calibration_done;
+	    $finish;
+         end
+      join	 
+   end      
+
+endmodule

Frogwells_fpga_design/基于FPGA、DDR3和USB2.0的图像采集系统/debug/ddr_test/synth/mem_interface_top_synp.sdc

@@ -0,0 +1,37 @@
+# Synplicity, Inc. constraint file
+# Written on Mon Jun 27 15:50:39 2005
+
+define_attribute          {v:work.example_top} syn_hier {hard}
+define_attribute          {v:work.infrastructure} syn_hier {hard}
+define_attribute          {v:work.memc_tb_top} syn_hier {hard}
+define_attribute          {v:work.memc_wrapper} syn_hier {hard}
+define_attribute          {v:work.iodrp_controller} syn_hier {hard}
+define_attribute          {v:work.iodrp_mcb_controller} syn_hier {hard}
+define_attribute          {v:work.mcb_raw_wrapper} syn_hier {hard}
+define_attribute          {v:work.mcb_soft_calibration} syn_hier {hard}
+define_attribute          {v:work.mcb_soft_calibration_top} syn_hier {hard}
+define_attribute          {v:work.mcb_ui_top} syn_hier {hard}
+define_attribute          {v:work.afifo} syn_hier {hard}
+define_attribute          {v:work.cmd_gen} syn_hier {hard}
+define_attribute          {v:work.cmd_prbs_gen} syn_hier {hard}
+define_attribute          {v:work.data_prbs_gen} syn_hier {hard}
+define_attribute          {v:work.init_mem_pattern_ctr} syn_hier {hard}
+define_attribute          {v:work.mcb_flow_control} syn_hier {hard}
+define_attribute          {v:work.mcb_traffic_gen} syn_hier {hard}
+define_attribute          {v:work.rd_data_gen} syn_hier {hard}
+define_attribute          {v:work.read_data_path} syn_hier {hard}
+define_attribute          {v:work.read_posted_fifo} syn_hier {hard}
+define_attribute          {v:work.sp6_data_gen} syn_hier {hard}
+define_attribute          {v:work.tg_status} syn_hier {hard}
+define_attribute          {v:work.v6_data_gen} syn_hier {hard}
+define_attribute          {v:work.wr_data_gen} syn_hier {hard}
+define_attribute          {v:work.write_data_path} syn_hier {hard}
+
+# clock Constraints
+define_clock -disable -name {memc3_infrastructure_inst} -period 3200 -clockgroup default_clkgroup_1
+define_clock          -name {memc3_infrastructure_inst.SYS_CLK_INST} -period 3200 -clockgroup default_clkgroup_2
+define_clock -disable -name {memc3_infrastructure_inst.u_pll_adv} -period 3200 -clockgroup default_clkgroup_3
+
+
+
+

Frogwells_fpga_design/基于FPGA、DDR3和USB2.0的图像采集系统/debug/ddr_test/synth/script_synp.tcl

@@ -0,0 +1,57 @@
+project -new 
+add_file -verilog "../rtl/example_top.v"
+add_file -verilog "../rtl/infrastructure.v"
+add_file -verilog "../rtl/memc_tb_top.v"
+add_file -verilog "../rtl/memc_wrapper.v"
+add_file -verilog "../rtl/mcb_controller/iodrp_controller.v"
+add_file -verilog "../rtl/mcb_controller/iodrp_mcb_controller.v"
+add_file -verilog "../rtl/mcb_controller/mcb_raw_wrapper.v"
+add_file -verilog "../rtl/mcb_controller/mcb_soft_calibration.v"
+add_file -verilog "../rtl/mcb_controller/mcb_soft_calibration_top.v"
+add_file -verilog "../rtl/mcb_controller/mcb_ui_top.v"
+add_file -verilog "../rtl/traffic_gen/afifo.v"
+add_file -verilog "../rtl/traffic_gen/cmd_gen.v"
+add_file -verilog "../rtl/traffic_gen/cmd_prbs_gen.v"
+add_file -verilog "../rtl/traffic_gen/data_prbs_gen.v"
+add_file -verilog "../rtl/traffic_gen/init_mem_pattern_ctr.v"
+add_file -verilog "../rtl/traffic_gen/mcb_flow_control.v"
+add_file -verilog "../rtl/traffic_gen/mcb_traffic_gen.v"
+add_file -verilog "../rtl/traffic_gen/rd_data_gen.v"
+add_file -verilog "../rtl/traffic_gen/read_data_path.v"
+add_file -verilog "../rtl/traffic_gen/read_posted_fifo.v"
+add_file -verilog "../rtl/traffic_gen/sp6_data_gen.v"
+add_file -verilog "../rtl/traffic_gen/tg_status.v"
+add_file -verilog "../rtl/traffic_gen/v6_data_gen.v"
+add_file -verilog "../rtl/traffic_gen/wr_data_gen.v"
+add_file -verilog "../rtl/traffic_gen/write_data_path.v"
+add_file -constraint "../synth/mem_interface_top_synp.sdc"
+impl -add rev_1
+set_option -technology spartan6
+set_option -part xc6slx45
+set_option -package csg324
+set_option -speed_grade -2
+set_option -default_enum_encoding default
+#AXI_ENABLE synp definition is not required for Native Interface
+set_option -symbolic_fsm_compiler 1
+set_option -resource_sharing 0
+set_option -use_fsm_explorer 0
+set_option -top_module "example_top"
+set_option -frequency 312.5
+set_option -fanout_limit 1000
+set_option -disable_io_insertion 0
+set_option -pipe 1
+set_option -fixgatedclocks 0
+set_option -retiming 0
+set_option -modular 0
+set_option -update_models_cp 0
+set_option -verification_mode 0
+set_option -write_verilog 0
+set_option -write_vhdl 0
+set_option -write_apr_constraint 0
+project -result_file "../synth/rev_1/example_top.edf"
+set_option -vlog_std v2001
+set_option -auto_constrain_io 0
+impl -active "../synth/rev_1"
+project -run
+project -save
+

Frogwells_fpga_design/基于FPGA、DDR3和USB2.0的图像采集系统/debug/ov5640-vga-usb-normal/_ngo/cs_icon_pro/icon_pro.vhd

@@ -0,0 +1,29 @@
+-------------------------------------------------------------------------------
+-- Copyright (c) 2017 Xilinx, Inc.
+-- All Rights Reserved
+-------------------------------------------------------------------------------
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /    Vendor     : Xilinx
+-- \   \   \/     Version    : 14.7
+--  \   \         Application: XILINX CORE Generator
+--  /   /         Filename   : icon_pro.vhd
+-- /___/   /\     Timestamp  : Sun Jun 25 16:19:20 �й���׼ʱ�� 2017
+-- \   \  /  \
+--  \___\/\___\
+--
+-- Design Name: VHDL Synthesis Wrapper
+-------------------------------------------------------------------------------
+-- This wrapper is used to integrate with Project Navigator and PlanAhead
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+ENTITY icon_pro IS
+  port (
+    CONTROL0: inout std_logic_vector(35 downto 0));
+END icon_pro;
+
+ARCHITECTURE icon_pro_a OF icon_pro IS
+BEGIN
+
+END icon_pro_a;

Frogwells_fpga_design/基于FPGA、DDR3和USB2.0的图像采集系统/debug/ov5640-vga-usb-normal/_ngo/cs_icon_pro/icon_pro_flist.txt

@@ -0,0 +1,11 @@
+# Output products list for <icon_pro>
+icon_pro.gise
+icon_pro.ngc
+icon_pro.ucf
+icon_pro.vhd
+icon_pro.vho
+icon_pro.xco
+icon_pro.xise
+icon_pro_flist.txt
+icon_pro_readme.txt
+icon_pro_xmdf.tcl

Frogwells_fpga_design/基于FPGA、DDR3和USB2.0的图像采集系统/debug/ov5640-vga-usb-normal/_ngo/cs_icon_pro/icon_pro_readme.txt

@@ -0,0 +1,46 @@
+The following files were generated for 'icon_pro' in directory
+E:\05_USB\26_ov5640_vga\26_ov5640_vga_normal\_ngo\cs_icon_pro\
+
+XCO file generator:
+   Generate an XCO file for compatibility with legacy flows.
+
+   * icon_pro.xco
+
+Creates an implementation netlist:
+   Creates an implementation netlist for the IP.
+
+   * icon_pro.ngc
+   * icon_pro.ucf
+   * icon_pro.vhd
+   * icon_pro.vho
+
+Creates an HDL instantiation template:
+   Creates an HDL instantiation template for the IP.
+
+   * icon_pro.vho
+
+Generate ISE metadata:
+   Create a metadata file for use when including this core in ISE designs
+
+   * icon_pro_xmdf.tcl
+
+Generate ISE subproject:
+   Create an ISE subproject for use when including this core in ISE designs
+
+   * icon_pro.gise
+   * icon_pro.xise
+
+Deliver Readme:
+   Readme file for the IP.
+
+   * icon_pro_readme.txt
+
+Generate FLIST file:
+   Text file listing all of the output files produced when a customized core was
+   generated in the CORE Generator.
+
+   * icon_pro_flist.txt
+
+Please see the Xilinx CORE Generator online help for further details on
+generated files and how to use them.
+

Frogwells_fpga_design/基于FPGA、DDR3和USB2.0的图像采集系统/debug/ov5640-vga-usb-normal/_ngo/cs_icon_pro/icon_pro_xmdf.tcl

@@ -0,0 +1,67 @@
+# The package naming convention is <core_name>_xmdf
+package provide icon_pro_xmdf 1.0
+
+# This includes some utilities that support common XMDF operations
+package require utilities_xmdf
+
+# Define a namespace for this package. The name of the name space
+# is <core_name>_xmdf
+namespace eval ::icon_pro_xmdf {
+# Use this to define any statics
+}
+
+# Function called by client to rebuild the params and port arrays
+# Optional when the use context does not require the param or ports
+# arrays to be available.
+proc ::icon_pro_xmdf::xmdfInit { instance } {
+# Variable containing name of library into which module is compiled
+# Recommendation: <module_name>
+# Required
+utilities_xmdf::xmdfSetData $instance Module Attributes Name icon_pro
+}
+# ::icon_pro_xmdf::xmdfInit
+
+# Function called by client to fill in all the xmdf* data variables
+# based on the current settings of the parameters
+proc ::icon_pro_xmdf::xmdfApplyParams { instance } {
+
+set fcount 0
+# Array containing libraries that are assumed to exist
+# Examples include unisim and xilinxcorelib
+# Optional
+# In this example, we assume that the unisim library will
+# be available to the simulation and synthesis tool
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
+utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path icon_pro.ngc
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path icon_pro.ucf
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type ucf
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path icon_pro.vhd
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path icon_pro.vho
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl_template
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path icon_pro.xco
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path icon_pro_xmdf.tcl
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module icon_pro
+incr fcount
+
+}
+
+# ::gen_comp_name_xmdf::xmdfApplyParams

Frogwells_fpga_design/基于FPGA、DDR3和USB2.0的图像采集系统/debug/ov5640-vga-usb-normal/_ngo/cs_ila_pro_0/ila_pro_0.vhd

@@ -0,0 +1,37 @@
+-------------------------------------------------------------------------------
+-- Copyright (c) 2017 Xilinx, Inc.
+-- All Rights Reserved
+-------------------------------------------------------------------------------
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /    Vendor     : Xilinx
+-- \   \   \/     Version    : 14.7
+--  \   \         Application: XILINX CORE Generator
+--  /   /         Filename   : ila_pro_0.vhd
+-- /___/   /\     Timestamp  : Sun Jun 25 16:22:15 �й���׼ʱ�� 2017
+-- \   \  /  \
+--  \___\/\___\
+--
+-- Design Name: VHDL Synthesis Wrapper
+-------------------------------------------------------------------------------
+-- This wrapper is used to integrate with Project Navigator and PlanAhead
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+ENTITY ila_pro_0 IS
+  port (
+    CONTROL: inout std_logic_vector(35 downto 0);
+    CLK: in std_logic;
+    TRIG0: in std_logic_vector(3 downto 0);
+    TRIG1: in std_logic_vector(3 downto 0);
+    TRIG2: in std_logic_vector(10 downto 0);
+    TRIG3: in std_logic_vector(9 downto 0);
+    TRIG4: in std_logic_vector(15 downto 0);
+    TRIG5: in std_logic_vector(4 downto 0);
+    TRIG6: in std_logic_vector(63 downto 0));
+END ila_pro_0;
+
+ARCHITECTURE ila_pro_0_a OF ila_pro_0 IS
+BEGIN
+
+END ila_pro_0_a;

Frogwells_fpga_design/基于FPGA、DDR3和USB2.0的图像采集系统/debug/ov5640-vga-usb-normal/_ngo/cs_ila_pro_0/ila_pro_0_flist.txt

@@ -0,0 +1,12 @@
+# Output products list for <ila_pro_0>
+ila_pro_0.cdc
+ila_pro_0.gise
+ila_pro_0.ngc
+ila_pro_0.ucf
+ila_pro_0.vhd
+ila_pro_0.vho
+ila_pro_0.xco
+ila_pro_0.xise
+ila_pro_0_flist.txt
+ila_pro_0_readme.txt
+ila_pro_0_xmdf.tcl

Frogwells_fpga_design/基于FPGA、DDR3和USB2.0的图像采集系统/debug/ov5640-vga-usb-normal/_ngo/cs_ila_pro_0/ila_pro_0_readme.txt

@@ -0,0 +1,47 @@
+The following files were generated for 'ila_pro_0' in directory
+E:\05_USB\26_ov5640_vga\26_ov5640_vga_normal\_ngo\cs_ila_pro_0\
+
+XCO file generator:
+   Generate an XCO file for compatibility with legacy flows.
+
+   * ila_pro_0.xco
+
+Creates an implementation netlist:
+   Creates an implementation netlist for the IP.
+
+   * ila_pro_0.cdc
+   * ila_pro_0.ngc
+   * ila_pro_0.ucf
+   * ila_pro_0.vhd
+   * ila_pro_0.vho
+
+Creates an HDL instantiation template:
+   Creates an HDL instantiation template for the IP.
+
+   * ila_pro_0.vho
+
+Generate ISE metadata:
+   Create a metadata file for use when including this core in ISE designs
+
+   * ila_pro_0_xmdf.tcl
+
+Generate ISE subproject:
+   Create an ISE subproject for use when including this core in ISE designs
+
+   * ila_pro_0.gise
+   * ila_pro_0.xise
+
+Deliver Readme:
+   Readme file for the IP.
+
+   * ila_pro_0_readme.txt
+
+Generate FLIST file:
+   Text file listing all of the output files produced when a customized core was
+   generated in the CORE Generator.
+
+   * ila_pro_0_flist.txt
+
+Please see the Xilinx CORE Generator online help for further details on
+generated files and how to use them.
+

Frogwells_fpga_design/基于FPGA、DDR3和USB2.0的图像采集系统/debug/ov5640-vga-usb-normal/_ngo/cs_ila_pro_0/ila_pro_0_xmdf.tcl

@@ -0,0 +1,71 @@
+# The package naming convention is <core_name>_xmdf
+package provide ila_pro_0_xmdf 1.0
+
+# This includes some utilities that support common XMDF operations
+package require utilities_xmdf
+
+# Define a namespace for this package. The name of the name space
+# is <core_name>_xmdf
+namespace eval ::ila_pro_0_xmdf {
+# Use this to define any statics
+}
+
+# Function called by client to rebuild the params and port arrays
+# Optional when the use context does not require the param or ports
+# arrays to be available.
+proc ::ila_pro_0_xmdf::xmdfInit { instance } {
+# Variable containing name of library into which module is compiled
+# Recommendation: <module_name>
+# Required
+utilities_xmdf::xmdfSetData $instance Module Attributes Name ila_pro_0
+}
+# ::ila_pro_0_xmdf::xmdfInit
+
+# Function called by client to fill in all the xmdf* data variables
+# based on the current settings of the parameters
+proc ::ila_pro_0_xmdf::xmdfApplyParams { instance } {
+
+set fcount 0
+# Array containing libraries that are assumed to exist
+# Examples include unisim and xilinxcorelib
+# Optional
+# In this example, we assume that the unisim library will
+# be available to the simulation and synthesis tool
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
+utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ila_pro_0.cdc
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ila_pro_0.ngc
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ila_pro_0.ucf
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type ucf
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ila_pro_0.vhd
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ila_pro_0.vho
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl_template
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ila_pro_0.xco
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path ila_pro_0_xmdf.tcl
+utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
+incr fcount
+
+utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module ila_pro_0
+incr fcount
+
+}
+
+# ::gen_comp_name_xmdf::xmdfApplyParams

Frogwells_fpga_design/基于FPGA、DDR3和USB2.0的图像采集系统/debug/ov5640-vga-usb-normal/camera_capture.v

@@ -0,0 +1,198 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Module Name:    camera_capture 
+//////////////////////////////////////////////////////////////////////////////////
+module camera_capture(
+	input reg_conf_done,	
+	input camera_pclk,
+   input camera_href,
+	input camera_vsync,
+	input [7:0] camera_data,	
+	output reg ddr_wren,                             //ddr cameraд���ź�, ��д
+	output reg [63:0] ddr_data_camera,               //ddr camera�����
+	output reg ddr_addr_wr_set,                      //ddr ��ַ��λ�ź�,�߸�λddr��д��ַ
+	output reg [11:0] camera_h_count,            //only for chipscope debug
+	output reg [10:0] camera_v_count,             //only for chipscope debug
+	output reg [1:0] frame_switch,
+	input output_done ,
+	input nframe      
+);
+
+//reg ddr_wren;
+//reg [63:0] ddr_data_camera;
+//reg ddr_addr_wr_set;
+
+reg [63:0] camera_data_reg;
+reg [3:0] counter;
+
+reg camera_vsync_buf1;
+reg camera_vsync_buf2;
+reg flag_data ;
+reg [7:0]camera_data_buf ;
+reg [2:0]nframe_counter ;
+reg nframe_flag   ;
+reg output_done_buf1 ;
+reg output_done_buf2 ;
+reg output_done_flag ;
+reg output_done_buf_flag = 1 ;
+reg change_nframe_switch;
+reg change_nframe_switch_buf1;
+reg change_nframe_switch_buf2;
+/*always @ ( posedge camera_pclk  )
+	begin
+		change_nframe_switch_buf1 <= frame_switch[0] ;
+		change_nframe_switch_buf2 <= change_nframe_switch_buf1 ;
+		change_nframe_switch      <= change_nframe_switch_buf1 ^ change_nframe_switch_buf2;
+	end*/
+always @ ( posedge camera_pclk or posedge nframe )
+	begin
+		if ( nframe )
+			output_done_buf_flag <= 0 ;
+		else
+			if ( output_done_flag )
+				output_done_buf_flag <= 1  ;
+			
+	end
+always @ ( posedge camera_pclk or posedge nframe  )
+	begin
+		if ( nframe )
+			begin
+				output_done_buf1 <= 0 ;
+				output_done_buf2 <= 0 ;
+				output_done_flag <= 0 ;
+			end
+		else
+			begin
+				output_done_buf1 <= output_done ;
+				output_done_buf2 <= output_done_buf1 ;
+				output_done_flag <= output_done_buf2 && output_done_buf1 ;
+			end
+	end
+//always @ ( posedge camera_pclk  )
+//	begin
+//		if ( camera_vsync_buf1&~camera_vsync_buf2)
+//			begin
+//		    camera_data_buf <= 8'h00 ;
+//			 flag_data       <= 0   ;
+//			end
+//		else
+//			if ( camera_v_count== 1 )
+//				begin
+//						{camera_data_buf,flag_data} <= {camera_data_buf,flag_data} + 1 ;
+//				end
+//			else
+//				if ( camera_v_count== 720 )
+//				begin
+//					 {camera_data_buf,flag_data} <= {camera_data_buf,flag_data} + camera_href ;
+//				end
+//				else
+//					if ( camera_v_count== 2 )
+//						begin
+//							camera_data_buf <= 8'h00 ;
+//						end
+//					else
+//						if ( camera_v_count== 3 )
+//							begin
+//								camera_data_buf <= 8'hBB ;
+//							end
+//						else
+//							begin
+//								camera_data_buf <= 8'h00 ;
+//							end
+//	end
+
+
+//����camera���  
+always @(posedge camera_pclk)
+begin
+	 if (!reg_conf_done) 
+       camera_h_count<=1;
+	 else if((camera_href==1'b1) & (camera_vsync==1'b0))  
+       camera_h_count<=camera_h_count+1'b1;	  
+	 else 
+	 	 camera_h_count<=1;
+ 
+end
+reg v_buf1;
+reg v_buf2;
+reg v_buf_flag;
+always @ ( posedge camera_pclk )
+	begin
+		v_buf1 <= (camera_href==1'b1) & (camera_vsync==1'b0) ;
+		v_buf2 <= v_buf1 ;
+		v_buf_flag <= v_buf2 && (~v_buf1) ;
+	end
+//����camera���
+always @(posedge camera_pclk)
+begin
+	 if (camera_vsync_buf2&~camera_vsync_buf1) 
+		begin
+       camera_v_count<=1;
+		 //camera_data_buf <= 0 ;
+		end
+	 else if(camera_h_count == 2560)
+		begin
+       camera_v_count<=camera_v_count+1'b1;
+		 //camera_data_buf <= camera_data_buf + 1 ;
+		 end 
+	 else 
+	 	 camera_v_count<=camera_v_count;
+		 
+end
+	
+//����camera���ݴ洢��DDR�е������ź� 8->64
+always @(posedge camera_pclk)
+begin
+	 if (!reg_conf_done) begin 
+			camera_data_reg<=0;
+			ddr_wren<=1'b0;
+			counter<=0;
+	 end	
+	 else if((camera_href==1'b1) & (camera_vsync==1'b0) )begin//& (output_done_buf_flag == 1) ) begin   
+		   if(counter<7) begin                              //��ȡǰ0~6��camera����	  
+				 camera_data_reg<={camera_data_reg[55:0],camera_data};
+				 counter<=counter+1'b1;
+				 ddr_wren<=1'b0;
+			end
+			else begin                                       //��ȡ��7��camera����		  
+				 ddr_data_camera<={camera_data_reg[55:0],camera_data};
+				 camera_data_reg<=0;
+				 counter<=0; 
+			    ddr_wren<=1'b1;                              //���յ�8��bytes����,����ddrд�ź�				 
+			end
+	  end
+	  else begin
+				camera_data_reg<=0;
+				ddr_wren<=1'b0;
+				counter<=0;
+	  end
+end
+
+//----------------------------------------------------
+//����camera���ݴ洢�ĵ�ַ��λ�ź�
+  always @(posedge camera_pclk)
+   if (!reg_conf_done) begin
+	    camera_vsync_buf1<=1'b0;
+		 camera_vsync_buf2<=1'b0;
+	    ddr_addr_wr_set<=1'b0;
+		 frame_switch<=0;
+		 nframe_counter <= 0 ;
+		 nframe_flag <= 0 ;
+   end
+   else begin
+		 camera_vsync_buf1<=camera_vsync;
+		 camera_vsync_buf2<=camera_vsync_buf1;
+       if (camera_vsync_buf2&(~camera_vsync_buf1))      //���vsync���½���,ddr��д��ַ��λ
+			ddr_addr_wr_set<=~ddr_addr_wr_set;
+//		   ddr_addr_wr_set<=1'b1;
+//		 else
+//		   ddr_addr_wr_set<=1'b0;
+
+       if (camera_vsync_buf1& (~camera_vsync_buf2) )      //���vsync���Ͻ���,Frame����д�ĵ�ַ�ռ佻��
+		   frame_switch<=frame_switch + output_done_buf_flag;
+   
+   end
+
+		
+endmodule
+

Frogwells_fpga_design/基于FPGA、DDR3和USB2.0的图像采集系统/debug/ov5640-vga-usb-normal/chipscope_icon.v

@@ -0,0 +1,27 @@
+///////////////////////////////////////////////////////////////////////////////
+// Copyright (c) 2015 Xilinx, Inc.
+// All Rights Reserved
+///////////////////////////////////////////////////////////////////////////////
+//   ____  ____
+//  /   /\/   /
+// /___/  \  /    Vendor     : Xilinx
+// \   \   \/     Version    : 14.7
+//  \   \         Application: Xilinx CORE Generator
+//  /   /         Filename   : chipscope_icon.v
+// /___/   /\     Timestamp  : Mon Apr 20 14:17:02 �й���׼ʱ�� 2015
+// \   \  /  \
+//  \___\/\___\
+//
+// Design Name: Verilog Synthesis Wrapper
+///////////////////////////////////////////////////////////////////////////////
+// This wrapper is used to integrate with Project Navigator and PlanAhead
+
+`timescale 1ns/1ps
+
+module chipscope_icon(
+    CONTROL0) /* synthesis syn_black_box syn_noprune=1 */;
+
+
+inout [35 : 0] CONTROL0;
+
+endmodule

Frogwells_fpga_design/基于FPGA、DDR3和USB2.0的图像采集系统/debug/ov5640-vga-usb-normal/chipscope_ila.v

@@ -0,0 +1,31 @@
+///////////////////////////////////////////////////////////////////////////////
+// Copyright (c) 2015 Xilinx, Inc.
+// All Rights Reserved
+///////////////////////////////////////////////////////////////////////////////
+//   ____  ____
+//  /   /\/   /
+// /___/  \  /    Vendor     : Xilinx
+// \   \   \/     Version    : 14.7
+//  \   \         Application: Xilinx CORE Generator
+//  /   /         Filename   : chipscope_ila.v
+// /___/   /\     Timestamp  : Mon Apr 20 14:20:30 �й���׼ʱ�� 2015
+// \   \  /  \
+//  \___\/\___\
+//
+// Design Name: Verilog Synthesis Wrapper
+///////////////////////////////////////////////////////////////////////////////
+// This wrapper is used to integrate with Project Navigator and PlanAhead
+
+`timescale 1ns/1ps
+
+module chipscope_ila(
+    CONTROL,
+    CLK,
+    TRIG0) /* synthesis syn_black_box syn_noprune=1 */;
+
+
+inout [35 : 0] CONTROL;
+input CLK;
+input [255 : 0] TRIG0;
+
+endmodule

Frogwells_fpga_design/基于FPGA、DDR3和USB2.0的图像采集系统/debug/ov5640-vga-usb-normal/ipcore_dir/create_ddr.tcl

@@ -0,0 +1,37 @@
+##
+## Core Generator Run Script, generator for Project Navigator create command
+##
+
+proc findRtfPath { relativePath } {
+   set xilenv ""
+   if { [info exists ::env(XILINX) ] } {
+      if { [info exists ::env(MYXILINX)] } {
+         set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ]
+      } else {
+         set xilenv $::env(XILINX)
+      }
+   }
+   foreach path [ split $xilenv $::xilinx::path_sep ] {
+      set fullPath [ file join $path $relativePath ]
+      if { [ file exists $fullPath ] } {
+         return $fullPath
+      }
+   }
+   return ""
+}
+
+source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ]
+
+set result [ run_cg_create "xilinx.com:ip:mig:3.92" "ddr" "MIG Virtex-6 and Spartan-6" "MIG Virtex-6 and Spartan-6 (xilinx.com:ip:mig:3.92) generated by Project Navigator" xc6slx45-2csg324 Verilog ]
+
+if { $result == 0 } {
+   puts "Core Generator create command completed successfully."
+} elseif { $result == 1 } {
+   puts "Core Generator create command failed."
+} elseif { $result == 3 || $result == 4 } {
+   # convert 'version check' result to real return range, bypassing any messages.
+   set result [ expr $result - 3 ]
+} else {
+   puts "Core Generator create cancelled."
+}
+exit $result

Frogwells_fpga_design/基于FPGA、DDR3和USB2.0的图像采集系统/debug/ov5640-vga-usb-normal/ipcore_dir/create_ff.tcl

@@ -0,0 +1,37 @@
+##
+## Core Generator Run Script, generator for Project Navigator create command
+##
+
+proc findRtfPath { relativePath } {
+   set xilenv ""
+   if { [info exists ::env(XILINX) ] } {
+      if { [info exists ::env(MYXILINX)] } {
+         set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ]
+      } else {
+         set xilenv $::env(XILINX)
+      }
+   }
+   foreach path [ split $xilenv $::xilinx::path_sep ] {
+      set fullPath [ file join $path $relativePath ]
+      if { [ file exists $fullPath ] } {
+         return $fullPath
+      }
+   }
+   return ""
+}
+
+source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ]
+
+set result [ run_cg_create "xilinx.com:ip:mig:3.92" "ff" "MIG Virtex-6 and Spartan-6" "MIG Virtex-6 and Spartan-6 (xilinx.com:ip:mig:3.92) generated by Project Navigator" xc6slx45-2csg324 Verilog ]
+
+if { $result == 0 } {
+   puts "Core Generator create command completed successfully."
+} elseif { $result == 1 } {
+   puts "Core Generator create command failed."
+} elseif { $result == 3 || $result == 4 } {
+   # convert 'version check' result to real return range, bypassing any messages.
+   set result [ expr $result - 3 ]
+} else {
+   puts "Core Generator create cancelled."
+}
+exit $result

Frogwells_fpga_design/基于FPGA、DDR3和USB2.0的图像采集系统/debug/ov5640-vga-usb-normal/ipcore_dir/create_ffgg.tcl

@@ -0,0 +1,37 @@
+##
+## Core Generator Run Script, generator for Project Navigator create command
+##
+
+proc findRtfPath { relativePath } {
+   set xilenv ""
+   if { [info exists ::env(XILINX) ] } {
+      if { [info exists ::env(MYXILINX)] } {
+         set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ]
+      } else {
+         set xilenv $::env(XILINX)
+      }
+   }
+   foreach path [ split $xilenv $::xilinx::path_sep ] {
+      set fullPath [ file join $path $relativePath ]
+      if { [ file exists $fullPath ] } {
+         return $fullPath
+      }
+   }
+   return ""
+}
+
+source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ]
+
+set result [ run_cg_create "xilinx.com:ip:mig:3.92" "ffgg" "MIG Virtex-6 and Spartan-6" "MIG Virtex-6 and Spartan-6 (xilinx.com:ip:mig:3.92) generated by Project Navigator" xc6slx45-2csg324 Verilog ]
+
+if { $result == 0 } {
+   puts "Core Generator create command completed successfully."
+} elseif { $result == 1 } {
+   puts "Core Generator create command failed."
+} elseif { $result == 3 || $result == 4 } {
+   # convert 'version check' result to real return range, bypassing any messages.
+   set result [ expr $result - 3 ]
+} else {
+   puts "Core Generator create cancelled."
+}
+exit $result

Frogwells_fpga_design/基于FPGA、DDR3和USB2.0的图像采集系统/debug/ov5640-vga-usb-normal/ipcore_dir/create_fgg.tcl

@@ -0,0 +1,37 @@
+##
+## Core Generator Run Script, generator for Project Navigator create command
+##
+
+proc findRtfPath { relativePath } {
+   set xilenv ""
+   if { [info exists ::env(XILINX) ] } {
+      if { [info exists ::env(MYXILINX)] } {
+         set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ]
+      } else {
+         set xilenv $::env(XILINX)
+      }
+   }
+   foreach path [ split $xilenv $::xilinx::path_sep ] {
+      set fullPath [ file join $path $relativePath ]
+      if { [ file exists $fullPath ] } {
+         return $fullPath
+      }
+   }
+   return ""
+}
+
+source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ]
+
+set result [ run_cg_create "xilinx.com:ip:mig:3.92" "fgg" "MIG Virtex-6 and Spartan-6" "MIG Virtex-6 and Spartan-6 (xilinx.com:ip:mig:3.92) generated by Project Navigator" xc6slx45-2csg324 Verilog ]
+
+if { $result == 0 } {
+   puts "Core Generator create command completed successfully."
+} elseif { $result == 1 } {
+   puts "Core Generator create command failed."
+} elseif { $result == 3 || $result == 4 } {
+   # convert 'version check' result to real return range, bypassing any messages.
+   set result [ expr $result - 3 ]
+} else {
+   puts "Core Generator create cancelled."
+}
+exit $result

Frogwells_fpga_design/基于FPGA、DDR3和USB2.0的图像采集系统/debug/ov5640-vga-usb-normal/ipcore_dir/create_jj.tcl

@@ -0,0 +1,37 @@
+##
+## Core Generator Run Script, generator for Project Navigator create command
+##
+
+proc findRtfPath { relativePath } {
+   set xilenv ""
+   if { [info exists ::env(XILINX) ] } {
+      if { [info exists ::env(MYXILINX)] } {
+         set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ]
+      } else {
+         set xilenv $::env(XILINX)
+      }
+   }
+   foreach path [ split $xilenv $::xilinx::path_sep ] {
+      set fullPath [ file join $path $relativePath ]
+      if { [ file exists $fullPath ] } {
+         return $fullPath
+      }
+   }
+   return ""
+}
+
+source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ]
+
+set result [ run_cg_create "xilinx.com:ip:mig:3.92" "jj" "MIG Virtex-6 and Spartan-6" "MIG Virtex-6 and Spartan-6 (xilinx.com:ip:mig:3.92) generated by Project Navigator" xc6slx45-2csg324 Verilog ]
+
+if { $result == 0 } {
+   puts "Core Generator create command completed successfully."
+} elseif { $result == 1 } {
+   puts "Core Generator create command failed."
+} elseif { $result == 3 || $result == 4 } {
+   # convert 'version check' result to real return range, bypassing any messages.
+   set result [ expr $result - 3 ]
+} else {
+   puts "Core Generator create cancelled."
+}
+exit $result

Frogwells_fpga_design/基于FPGA、DDR3和USB2.0的图像采集系统/debug/ov5640-vga-usb-normal/ipcore_dir/create_pixel_fifo.tcl

@@ -0,0 +1,37 @@
+##
+## Core Generator Run Script, generator for Project Navigator create command
+##
+
+proc findRtfPath { relativePath } {
+   set xilenv ""
+   if { [info exists ::env(XILINX) ] } {
+      if { [info exists ::env(MYXILINX)] } {
+         set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ]
+      } else {
+         set xilenv $::env(XILINX)
+      }
+   }
+   foreach path [ split $xilenv $::xilinx::path_sep ] {
+      set fullPath [ file join $path $relativePath ]
+      if { [ file exists $fullPath ] } {
+         return $fullPath
+      }
+   }
+   return ""
+}
+
+source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ]
+
+set result [ run_cg_create "xilinx.com:ip:fifo_generator:9.3" "pixel_fifo" "FIFO Generator" "FIFO Generator (xilinx.com:ip:fifo_generator:9.3) generated by Project Navigator" xc6slx45-2csg324 Verilog ]
+
+if { $result == 0 } {
+   puts "Core Generator create command completed successfully."
+} elseif { $result == 1 } {
+   puts "Core Generator create command failed."
+} elseif { $result == 3 || $result == 4 } {
+   # convert 'version check' result to real return range, bypassing any messages.
+   set result [ expr $result - 3 ]
+} else {
+   puts "Core Generator create cancelled."
+}
+exit $result

Frogwells_fpga_design/基于FPGA、DDR3和USB2.0的图像采集系统/debug/ov5640-vga-usb-normal/ipcore_dir/pixel_fifo.v

@@ -0,0 +1,489 @@
+/*******************************************************************************
+*     This file is owned and controlled by Xilinx and must be used solely      *
+*     for design, simulation, implementation and creation of design files      *
+*     limited to Xilinx devices or technologies. Use with non-Xilinx           *
+*     devices or technologies is expressly prohibited and immediately          *
+*     terminates your license.                                                 *
+*                                                                              *
+*     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY     *
+*     FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES.  BY     *
+*     PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE              *
+*     IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS       *
+*     MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY       *
+*     CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY        *
+*     RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY        *
+*     DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE    *
+*     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR           *
+*     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF          *
+*     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A    *
+*     PARTICULAR PURPOSE.                                                      *
+*                                                                              *
+*     Xilinx products are not intended for use in life support appliances,     *
+*     devices, or systems.  Use in such applications are expressly             *
+*     prohibited.                                                              *
+*                                                                              *
+*     (c) Copyright 1995-2017 Xilinx, Inc.                                     *
+*     All rights reserved.                                                     *
+*******************************************************************************/
+// You must compile the wrapper file pixel_fifo.v when simulating
+// the core, pixel_fifo. When compiling the wrapper file, be sure to
+// reference the XilinxCoreLib Verilog simulation library. For detailed
+// instructions, please refer to the "CORE Generator Help".
+
+// The synthesis directives "translate_off/translate_on" specified below are
+// supported by Xilinx, Mentor Graphics and Synplicity synthesis
+// tools. Ensure they are correct for your synthesis tool(s).
+
+`timescale 1ns/1ps
+
+module pixel_fifo(
+  rst,
+  wr_clk,
+  rd_clk,
+  din,
+  wr_en,
+  rd_en,
+  dout,
+  full,
+  empty,
+  prog_full
+);
+
+input rst;
+input wr_clk;
+input rd_clk;
+input [63 : 0] din;
+input wr_en;
+input rd_en;
+output [63 : 0] dout;
+output full;
+output empty;
+output prog_full;
+
+// synthesis translate_off
+
+  FIFO_GENERATOR_V9_3 #(
+    .C_ADD_NGC_CONSTRAINT(0),
+    .C_APPLICATION_TYPE_AXIS(0),
+    .C_APPLICATION_TYPE_RACH(0),
+    .C_APPLICATION_TYPE_RDCH(0),
+    .C_APPLICATION_TYPE_WACH(0),
+    .C_APPLICATION_TYPE_WDCH(0),
+    .C_APPLICATION_TYPE_WRCH(0),
+    .C_AXI_ADDR_WIDTH(32),
+    .C_AXI_ARUSER_WIDTH(1),
+    .C_AXI_AWUSER_WIDTH(1),
+    .C_AXI_BUSER_WIDTH(1),
+    .C_AXI_DATA_WIDTH(64),
+    .C_AXI_ID_WIDTH(4),
+    .C_AXI_RUSER_WIDTH(1),
+    .C_AXI_TYPE(0),
+    .C_AXI_WUSER_WIDTH(1),
+    .C_AXIS_TDATA_WIDTH(64),
+    .C_AXIS_TDEST_WIDTH(4),
+    .C_AXIS_TID_WIDTH(8),
+    .C_AXIS_TKEEP_WIDTH(4),
+    .C_AXIS_TSTRB_WIDTH(4),
+    .C_AXIS_TUSER_WIDTH(4),
+    .C_AXIS_TYPE(0),
+    .C_COMMON_CLOCK(0),
+    .C_COUNT_TYPE(0),
+    .C_DATA_COUNT_WIDTH(7),
+    .C_DEFAULT_VALUE("BlankString"),
+    .C_DIN_WIDTH(64),
+    .C_DIN_WIDTH_AXIS(1),
+    .C_DIN_WIDTH_RACH(32),
+    .C_DIN_WIDTH_RDCH(64),
+    .C_DIN_WIDTH_WACH(32),
+    .C_DIN_WIDTH_WDCH(64),
+    .C_DIN_WIDTH_WRCH(2),
+    .C_DOUT_RST_VAL("0"),
+    .C_DOUT_WIDTH(64),
+    .C_ENABLE_RLOCS(0),
+    .C_ENABLE_RST_SYNC(1),
+    .C_ERROR_INJECTION_TYPE(0),
+    .C_ERROR_INJECTION_TYPE_AXIS(0),
+    .C_ERROR_INJECTION_TYPE_RACH(0),
+    .C_ERROR_INJECTION_TYPE_RDCH(0),
+    .C_ERROR_INJECTION_TYPE_WACH(0),
+    .C_ERROR_INJECTION_TYPE_WDCH(0),
+    .C_ERROR_INJECTION_TYPE_WRCH(0),
+    .C_FAMILY("spartan6"),
+    .C_FULL_FLAGS_RST_VAL(1),
+    .C_HAS_ALMOST_EMPTY(0),
+    .C_HAS_ALMOST_FULL(0),
+    .C_HAS_AXI_ARUSER(0),
+    .C_HAS_AXI_AWUSER(0),
+    .C_HAS_AXI_BUSER(0),
+    .C_HAS_AXI_RD_CHANNEL(0),
+    .C_HAS_AXI_RUSER(0),
+    .C_HAS_AXI_WR_CHANNEL(0),
+    .C_HAS_AXI_WUSER(0),
+    .C_HAS_AXIS_TDATA(0),
+    .C_HAS_AXIS_TDEST(0),
+    .C_HAS_AXIS_TID(0),
+    .C_HAS_AXIS_TKEEP(0),
+    .C_HAS_AXIS_TLAST(0),
+    .C_HAS_AXIS_TREADY(1),
+    .C_HAS_AXIS_TSTRB(0),
+    .C_HAS_AXIS_TUSER(0),
+    .C_HAS_BACKUP(0),
+    .C_HAS_DATA_COUNT(0),
+    .C_HAS_DATA_COUNTS_AXIS(0),
+    .C_HAS_DATA_COUNTS_RACH(0),
+    .C_HAS_DATA_COUNTS_RDCH(0),
+    .C_HAS_DATA_COUNTS_WACH(0),
+    .C_HAS_DATA_COUNTS_WDCH(0),
+    .C_HAS_DATA_COUNTS_WRCH(0),
+    .C_HAS_INT_CLK(0),
+    .C_HAS_MASTER_CE(0),
+    .C_HAS_MEMINIT_FILE(0),
+    .C_HAS_OVERFLOW(0),
+    .C_HAS_PROG_FLAGS_AXIS(0),
+    .C_HAS_PROG_FLAGS_RACH(0),
+    .C_HAS_PROG_FLAGS_RDCH(0),
+    .C_HAS_PROG_FLAGS_WACH(0),
+    .C_HAS_PROG_FLAGS_WDCH(0),
+    .C_HAS_PROG_FLAGS_WRCH(0),
+    .C_HAS_RD_DATA_COUNT(0),
+    .C_HAS_RD_RST(0),
+    .C_HAS_RST(1),
+    .C_HAS_SLAVE_CE(0),
+    .C_HAS_SRST(0),
+    .C_HAS_UNDERFLOW(0),
+    .C_HAS_VALID(0),
+    .C_HAS_WR_ACK(0),
+    .C_HAS_WR_DATA_COUNT(0),
+    .C_HAS_WR_RST(0),
+    .C_IMPLEMENTATION_TYPE(2),
+    .C_IMPLEMENTATION_TYPE_AXIS(1),
+    .C_IMPLEMENTATION_TYPE_RACH(1),
+    .C_IMPLEMENTATION_TYPE_RDCH(1),
+    .C_IMPLEMENTATION_TYPE_WACH(1),
+    .C_IMPLEMENTATION_TYPE_WDCH(1),
+    .C_IMPLEMENTATION_TYPE_WRCH(1),
+    .C_INIT_WR_PNTR_VAL(0),
+    .C_INTERFACE_TYPE(0),
+    .C_MEMORY_TYPE(1),
+    .C_MIF_FILE_NAME("BlankString"),
+    .C_MSGON_VAL(1),
+    .C_OPTIMIZATION_MODE(0),
+    .C_OVERFLOW_LOW(0),
+    .C_PRELOAD_LATENCY(1),
+    .C_PRELOAD_REGS(0),
+    .C_PRIM_FIFO_TYPE("512x72"),
+    .C_PROG_EMPTY_THRESH_ASSERT_VAL(2),
+    .C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022),
+    .C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(1022),
+    .C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1022),
+    .C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(1022),
+    .C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1022),
+    .C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(1022),
+    .C_PROG_EMPTY_THRESH_NEGATE_VAL(3),
+    .C_PROG_EMPTY_TYPE(0),
+    .C_PROG_EMPTY_TYPE_AXIS(0),
+    .C_PROG_EMPTY_TYPE_RACH(0),
+    .C_PROG_EMPTY_TYPE_RDCH(0),
+    .C_PROG_EMPTY_TYPE_WACH(0),
+    .C_PROG_EMPTY_TYPE_WDCH(0),
+    .C_PROG_EMPTY_TYPE_WRCH(0),
+    .C_PROG_FULL_THRESH_ASSERT_VAL(10),
+    .C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),
+    .C_PROG_FULL_THRESH_ASSERT_VAL_RACH(1023),
+    .C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023),
+    .C_PROG_FULL_THRESH_ASSERT_VAL_WACH(1023),
+    .C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023),
+    .C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(1023),
+    .C_PROG_FULL_THRESH_NEGATE_VAL(9),
+    .C_PROG_FULL_TYPE(1),
+    .C_PROG_FULL_TYPE_AXIS(0),
+    .C_PROG_FULL_TYPE_RACH(0),
+    .C_PROG_FULL_TYPE_RDCH(0),
+    .C_PROG_FULL_TYPE_WACH(0),
+    .C_PROG_FULL_TYPE_WDCH(0),
+    .C_PROG_FULL_TYPE_WRCH(0),
+    .C_RACH_TYPE(0),
+    .C_RD_DATA_COUNT_WIDTH(7),
+    .C_RD_DEPTH(128),
+    .C_RD_FREQ(1),
+    .C_RD_PNTR_WIDTH(7),
+    .C_RDCH_TYPE(0),
+    .C_REG_SLICE_MODE_AXIS(0),
+    .C_REG_SLICE_MODE_RACH(0),
+    .C_REG_SLICE_MODE_RDCH(0),
+    .C_REG_SLICE_MODE_WACH(0),
+    .C_REG_SLICE_MODE_WDCH(0),
+    .C_REG_SLICE_MODE_WRCH(0),
+    .C_SYNCHRONIZER_STAGE(2),
+    .C_UNDERFLOW_LOW(0),
+    .C_USE_COMMON_OVERFLOW(0),
+    .C_USE_COMMON_UNDERFLOW(0),
+    .C_USE_DEFAULT_SETTINGS(0),
+    .C_USE_DOUT_RST(1),
+    .C_USE_ECC(0),
+    .C_USE_ECC_AXIS(0),
+    .C_USE_ECC_RACH(0),
+    .C_USE_ECC_RDCH(0),
+    .C_USE_ECC_WACH(0),
+    .C_USE_ECC_WDCH(0),
+    .C_USE_ECC_WRCH(0),
+    .C_USE_EMBEDDED_REG(0),
+    .C_USE_FIFO16_FLAGS(0),
+    .C_USE_FWFT_DATA_COUNT(0),
+    .C_VALID_LOW(0),
+    .C_WACH_TYPE(0),
+    .C_WDCH_TYPE(0),
+    .C_WR_ACK_LOW(0),
+    .C_WR_DATA_COUNT_WIDTH(7),
+    .C_WR_DEPTH(128),
+    .C_WR_DEPTH_AXIS(1024),
+    .C_WR_DEPTH_RACH(16),
+    .C_WR_DEPTH_RDCH(1024),
+    .C_WR_DEPTH_WACH(16),
+    .C_WR_DEPTH_WDCH(1024),
+    .C_WR_DEPTH_WRCH(16),
+    .C_WR_FREQ(1),
+    .C_WR_PNTR_WIDTH(7),
+    .C_WR_PNTR_WIDTH_AXIS(10),
+    .C_WR_PNTR_WIDTH_RACH(4),
+    .C_WR_PNTR_WIDTH_RDCH(10),
+    .C_WR_PNTR_WIDTH_WACH(4),
+    .C_WR_PNTR_WIDTH_WDCH(10),
+    .C_WR_PNTR_WIDTH_WRCH(4),
+    .C_WR_RESPONSE_LATENCY(1),
+    .C_WRCH_TYPE(0)
+  )
+  inst (
+    .RST(rst),
+    .WR_CLK(wr_clk),
+    .RD_CLK(rd_clk),
+    .DIN(din),
+    .WR_EN(wr_en),
+    .RD_EN(rd_en),
+    .DOUT(dout),
+    .FULL(full),
+    .EMPTY(empty),
+    .PROG_FULL(prog_full),
+    .BACKUP(),
+    .BACKUP_MARKER(),
+    .CLK(),
+    .SRST(),
+    .WR_RST(),
+    .RD_RST(),
+    .PROG_EMPTY_THRESH(),
+    .PROG_EMPTY_THRESH_ASSERT(),
+    .PROG_EMPTY_THRESH_NEGATE(),
+    .PROG_FULL_THRESH(),
+    .PROG_FULL_THRESH_ASSERT(),
+    .PROG_FULL_THRESH_NEGATE(),
+    .INT_CLK(),
+    .INJECTDBITERR(),
+    .INJECTSBITERR(),
+    .ALMOST_FULL(),
+    .WR_ACK(),
+    .OVERFLOW(),
+    .ALMOST_EMPTY(),
+    .VALID(),
+    .UNDERFLOW(),
+    .DATA_COUNT(),
+    .RD_DATA_COUNT(),
+    .WR_DATA_COUNT(),
+    .PROG_EMPTY(),
+    .SBITERR(),
+    .DBITERR(),
+    .M_ACLK(),
+    .S_ACLK(),
+    .S_ARESETN(),
+    .M_ACLK_EN(),
+    .S_ACLK_EN(),
+    .S_AXI_AWID(),
+    .S_AXI_AWADDR(),
+    .S_AXI_AWLEN(),
+    .S_AXI_AWSIZE(),
+    .S_AXI_AWBURST(),
+    .S_AXI_AWLOCK(),
+    .S_AXI_AWCACHE(),
+    .S_AXI_AWPROT(),
+    .S_AXI_AWQOS(),
+    .S_AXI_AWREGION(),
+    .S_AXI_AWUSER(),
+    .S_AXI_AWVALID(),
+    .S_AXI_AWREADY(),
+    .S_AXI_WID(),
+    .S_AXI_WDATA(),
+    .S_AXI_WSTRB(),
+    .S_AXI_WLAST(),
+    .S_AXI_WUSER(),
+    .S_AXI_WVALID(),
+    .S_AXI_WREADY(),
+    .S_AXI_BID(),
+    .S_AXI_BRESP(),
+    .S_AXI_BUSER(),
+    .S_AXI_BVALID(),
+    .S_AXI_BREADY(),
+    .M_AXI_AWID(),
+    .M_AXI_AWADDR(),
+    .M_AXI_AWLEN(),
+    .M_AXI_AWSIZE(),
+    .M_AXI_AWBURST(),
+    .M_AXI_AWLOCK(),
+    .M_AXI_AWCACHE(),
+    .M_AXI_AWPROT(),
+    .M_AXI_AWQOS(),
+    .M_AXI_AWREGION(),
+    .M_AXI_AWUSER(),
+    .M_AXI_AWVALID(),
+    .M_AXI_AWREADY(),
+    .M_AXI_WID(),
+    .M_AXI_WDATA(),
+    .M_AXI_WSTRB(),
+    .M_AXI_WLAST(),
+    .M_AXI_WUSER(),
+    .M_AXI_WVALID(),
+    .M_AXI_WREADY(),
+    .M_AXI_BID(),
+    .M_AXI_BRESP(),
+    .M_AXI_BUSER(),
+    .M_AXI_BVALID(),
+    .M_AXI_BREADY(),
+    .S_AXI_ARID(),
+    .S_AXI_ARADDR(),
+    .S_AXI_ARLEN(),
+    .S_AXI_ARSIZE(),
+    .S_AXI_ARBURST(),
+    .S_AXI_ARLOCK(),
+    .S_AXI_ARCACHE(),
+    .S_AXI_ARPROT(),
+    .S_AXI_ARQOS(),
+    .S_AXI_ARREGION(),
+    .S_AXI_ARUSER(),
+    .S_AXI_ARVALID(),
+    .S_AXI_ARREADY(),
+    .S_AXI_RID(),
+    .S_AXI_RDATA(),
+    .S_AXI_RRESP(),
+    .S_AXI_RLAST(),
+    .S_AXI_RUSER(),
+    .S_AXI_RVALID(),
+    .S_AXI_RREADY(),
+    .M_AXI_ARID(),
+    .M_AXI_ARADDR(),
+    .M_AXI_ARLEN(),
+    .M_AXI_ARSIZE(),
+    .M_AXI_ARBURST(),
+    .M_AXI_ARLOCK(),
+    .M_AXI_ARCACHE(),
+    .M_AXI_ARPROT(),
+    .M_AXI_ARQOS(),
+    .M_AXI_ARREGION(),
+    .M_AXI_ARUSER(),
+    .M_AXI_ARVALID(),
+    .M_AXI_ARREADY(),
+    .M_AXI_RID(),
+    .M_AXI_RDATA(),
+    .M_AXI_RRESP(),
+    .M_AXI_RLAST(),
+    .M_AXI_RUSER(),
+    .M_AXI_RVALID(),
+    .M_AXI_RREADY(),
+    .S_AXIS_TVALID(),
+    .S_AXIS_TREADY(),
+    .S_AXIS_TDATA(),
+    .S_AXIS_TSTRB(),
+    .S_AXIS_TKEEP(),
+    .S_AXIS_TLAST(),
+    .S_AXIS_TID(),
+    .S_AXIS_TDEST(),
+    .S_AXIS_TUSER(),
+    .M_AXIS_TVALID(),
+    .M_AXIS_TREADY(),
+    .M_AXIS_TDATA(),
+    .M_AXIS_TSTRB(),
+    .M_AXIS_TKEEP(),
+    .M_AXIS_TLAST(),
+    .M_AXIS_TID(),
+    .M_AXIS_TDEST(),
+    .M_AXIS_TUSER(),
+    .AXI_AW_INJECTSBITERR(),
+    .AXI_AW_INJECTDBITERR(),
+    .AXI_AW_PROG_FULL_THRESH(),
+    .AXI_AW_PROG_EMPTY_THRESH(),
+    .AXI_AW_DATA_COUNT(),
+    .AXI_AW_WR_DATA_COUNT(),
+    .AXI_AW_RD_DATA_COUNT(),
+    .AXI_AW_SBITERR(),
+    .AXI_AW_DBITERR(),
+    .AXI_AW_OVERFLOW(),
+    .AXI_AW_UNDERFLOW(),
+    .AXI_AW_PROG_FULL(),
+    .AXI_AW_PROG_EMPTY(),
+    .AXI_W_INJECTSBITERR(),
+    .AXI_W_INJECTDBITERR(),
+    .AXI_W_PROG_FULL_THRESH(),
+    .AXI_W_PROG_EMPTY_THRESH(),
+    .AXI_W_DATA_COUNT(),
+    .AXI_W_WR_DATA_COUNT(),
+    .AXI_W_RD_DATA_COUNT(),
+    .AXI_W_SBITERR(),
+    .AXI_W_DBITERR(),
+    .AXI_W_OVERFLOW(),
+    .AXI_W_UNDERFLOW(),
+    .AXI_B_INJECTSBITERR(),
+    .AXI_W_PROG_FULL(),
+    .AXI_W_PROG_EMPTY(),
+    .AXI_B_INJECTDBITERR(),
+    .AXI_B_PROG_FULL_THRESH(),
+    .AXI_B_PROG_EMPTY_THRESH(),
+    .AXI_B_DATA_COUNT(),
+    .AXI_B_WR_DATA_COUNT(),
+    .AXI_B_RD_DATA_COUNT(),
+    .AXI_B_SBITERR(),
+    .AXI_B_DBITERR(),
+    .AXI_B_OVERFLOW(),
+    .AXI_B_UNDERFLOW(),
+    .AXI_AR_INJECTSBITERR(),
+    .AXI_B_PROG_FULL(),
+    .AXI_B_PROG_EMPTY(),
+    .AXI_AR_INJECTDBITERR(),
+    .AXI_AR_PROG_FULL_THRESH(),
+    .AXI_AR_PROG_EMPTY_THRESH(),
+    .AXI_AR_DATA_COUNT(),
+    .AXI_AR_WR_DATA_COUNT(),
+    .AXI_AR_RD_DATA_COUNT(),
+    .AXI_AR_SBITERR(),
+    .AXI_AR_DBITERR(),
+    .AXI_AR_OVERFLOW(),
+    .AXI_AR_UNDERFLOW(),
+    .AXI_AR_PROG_FULL(),
+    .AXI_AR_PROG_EMPTY(),
+    .AXI_R_INJECTSBITERR(),
+    .AXI_R_INJECTDBITERR(),
+    .AXI_R_PROG_FULL_THRESH(),
+    .AXI_R_PROG_EMPTY_THRESH(),
+    .AXI_R_DATA_COUNT(),
+    .AXI_R_WR_DATA_COUNT(),
+    .AXI_R_RD_DATA_COUNT(),
+    .AXI_R_SBITERR(),
+    .AXI_R_DBITERR(),
+    .AXI_R_OVERFLOW(),
+    .AXI_R_UNDERFLOW(),
+    .AXIS_INJECTSBITERR(),
+    .AXI_R_PROG_FULL(),
+    .AXI_R_PROG_EMPTY(),
+    .AXIS_INJECTDBITERR(),
+    .AXIS_PROG_FULL_THRESH(),
+    .AXIS_PROG_EMPTY_THRESH(),
+    .AXIS_DATA_COUNT(),
+    .AXIS_WR_DATA_COUNT(),
+    .AXIS_RD_DATA_COUNT(),
+    .AXIS_SBITERR(),
+    .AXIS_DBITERR(),
+    .AXIS_OVERFLOW(),
+    .AXIS_UNDERFLOW(),
+    .AXIS_PROG_FULL(),
+    .AXIS_PROG_EMPTY()
+  );
+
+// synthesis translate_on
+
+endmodule

Frogwells_fpga_design/基于FPGA、DDR3和USB2.0的图像采集系统/debug/ov5640-vga-usb-normal/ipcore_dir/pixel_fifo/doc/fifo_generator_v9_3_readme.txt

@@ -0,0 +1,236 @@
+CHANGE LOG for LogiCORE FIFO Generator V9.3 Rev 1
+
+                    Release Date: December 18, 2012
+--------------------------------------------------------------------------------
+
+Table of Contents
+
+1. INTRODUCTION 
+2. DEVICE SUPPORT    
+3. NEW FEATURE HISTORY   
+4. RESOLVED ISSUES 
+5. KNOWN ISSUES & LIMITATIONS 
+6. TECHNICAL SUPPORT & FEEDBACK
+7. CORE RELEASE HISTORY 
+8. LEGAL DISCLAIMER 
+
+--------------------------------------------------------------------------------  
+
+
+1. INTRODUCTION
+
+For installation instructions for this release, please go to:
+
+   http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm
+
+For system requirements:
+
+   http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm
+
+This file contains release notes for the Xilinx LogiCORE IP FIFO Generator v9.3 Rev 1
+solution. For the latest core updates, see the product page at:
+ 
+   http://www.xilinx.com/products/ipcenter/FIFO_Generator.htm
+
+................................................................................
+
+
+2. DEVICE SUPPORT
+
+
+  2.1 ISE 
+   
+    The following device families are supported by the core for this release.
+    
+    
+    All 7 Series devices
+    Zynq-7000 devices
+    All Virtex-6 devices
+    All Spartan-6 devices
+    All Virtex-5 devices
+    All Spartan-3 devices
+    All Virtex-4 devices
+  
+  
+  2.2 Vivado 
+  
+    All 7 Series devices
+    Zynq-7000 devices
+
+................................................................................
+
+
+3. NEW FEATURE HISTORY
+
+
+  3.1 ISE 
+  
+    - ISE 14.4 software support
+
+  
+  3.2 Vivado
+  
+    - 2012.4 software support
+    - IP level constraint for Built-in FIFO reset synchronizer
+
+................................................................................
+
+
+4. RESOLVED ISSUES 
+
+
+  4.1 ISE 
+
+    - N/A
+
+
+  4.2 Vivado 
+
+    - N/A
+
+
+................................................................................
+
+
+5. KNOWN ISSUES & LIMITATIONS 
+
+
+  5.1 ISE 
+  
+    The following are known issues for v9.3 Rev 1 of this core at time of release:
+  
+    1. Importing an XCO file alters the XCO configurations
+  
+       Description: In the FIFO Generator GUI, after importing an XCO file (Independent clock, distributed memory configuration)
+       into a Virtex-4 CORE Generator project, if the FIFO type is changed to "Independent Clocks, Built-in FIFO" in page 1, 
+       page 2 does not correctly offer the Read Clock Frequency and Write Clock Frequency options as it should.
+    
+       CR 467240
+       AR 31379
+  
+    2. Status flags after the first write to Common Clock Built-in FIFO not guaranteed
+  
+       Description: When using Common Clock Built-in FIFO configuration with asynchronous reset for Virtex-6 FPGA,
+       correct behavior of the FIFO status flags cannot be guaranteed after the first write.
+    
+       Workaround: To work around this issue, synchronize the negative edge of reset to RDCLK/WRCLK.
+       For more information and additional workaround see Answer Record 41099.
+  
+  5.2 Vivado 
+
+    The following are known issues for v9.3 Rev 1 of this core at time of release:
+     
+    1. Description: When Trying to upgrade to latest version of FIFO Generator from older verions, following error message is seen 
+       ERROR: [Common 17-69] Command failed: invalid command name "puts" and Auto Upgradation does not work.
+      
+       CR 665836
+
+The most recent information, including known issues, workarounds, and
+resolutions for this version is provided in the IP Release Notes User Guide
+located at 
+
+   www.xilinx.com/support/documentation/user_guides/xtp025.pdf 
+
+................................................................................
+
+
+6. TECHNICAL SUPPORT & FEEDBACK
+
+To obtain technical support, create a WebCase at www.xilinx.com/support.
+Questions are routed to a team with expertise using this product.  
+
+Xilinx provides technical support for use of this product when used
+according to the guidelines described in the core documentation, and
+cannot guarantee timing, functionality, or support of this product for
+designs that do not follow specified guidelines.
+
+................................................................................
+
+
+7. CORE RELEASE HISTORY 
+
+Date        By            Version      Description
+================================================================================
+12/18/2012  Xilinx, Inc.  9.3 Rev 1    ISE 14.4 and Vivado 2012.4 support; IP level constraint for Built-in FIFO reset synchronizer
+10/16/2012  Xilinx, Inc.  9.3          ISE 14.3 and Vivado 2012.3 support; Clock Enable support for AXI4 Stream FIFO
+07/25/2012  Xilinx, Inc.  9.2          ISE 14.2 and Vivado 2012.2 support; Accurate data count support for AXI4 Stream Packet FIFO
+04/24/2012  Xilinx, Inc.  9.1          ISE 14.1 and Vivado 2012.1 support; Defense Grade 7 Series and Zynq devices, and Automotive Zynq device support
+                                       AXI FIFO data width support up to 4096; Programmable Full/Empty as sideband signals for AXI FIFO
+01/18/2012  Xilinx, Inc.  8.4          ISE 13.4 support and Packet FIFO feature addition; Artix-7 Lower Power and Automotive Artix-7 device support
+10/19/2011  Xilinx, Inc.  8.3          ISE 13.3 support and QVirtex-6L device support
+06/22/2011  Xilinx, Inc.  8.2          ISE 13.2 support and Kintex-7L, Virtex-7L, Artix-7 and Zynq-7000 device support
+03/01/2011  Xilinx, Inc.  8.1          ISE 13.1 support and Virtex-7 and Kintex-7 device support; Wiring Logic and Register Slice Support
+10/29/2010  Xilinx, Inc.  7.3          ISE 13.0.2 support
+09/21/2010  Xilinx, Inc.  7.2          ISE 12.3 support; AXI4 Support
+07/30/2010  Xilinx, Inc.  7.1          ISE 13.0.1 support
+06/18/2010  Xilinx, Inc.  6.2          ISE 12.2 support
+04/19/2010  Xilinx, Inc.  6.1          ISE 12.1 support
+12/02/2009  Xilinx, Inc.  5.3 rev 1    ISE 11.4 support; Spartan-6 Low Power and Automotive Spartan-6 Device support
+09/16/2009  Xilinx, Inc.  5.3          Update to add 11.3; Virtex-6 Low Power and Virtex-6 HXT Device support
+06/24/2009  Xilinx, Inc.  5.2          Update to add 11.2 and Virtex-6 CXT device support
+04/24/2009  Xilinx, Inc.  5.1          Update to add 11.1 and Virtex-6 and Spartan-6 device support
+09/19/2008  Xilinx, Inc.  4.4          Update to add 10.1 SP3 and Virtex-5 TXT device support and miscellaneous bug fixes
+03/24/2008  Xilinx, Inc.  4.3          Update to add 10.1 support and miscellaneous bug fixes
+10/03/2007  Xilinx, Inc.  4.2          Support for FWFT for Block RAM and Distributed RAM Common Clock FIFOs
+08/08/2007  Xilinx, Inc.  4.1          Update to add 9.2i support; Revised to v4.1; ECC support for block RAM FIFO
+04/02/2007  Xilinx, Inc.  3.3          Update to add 9.1i support; Revised to v3.3; Spartan-3A and Spartan-3A DSP support; ECC support
+09/21/2006  Xilinx, Inc.  3.2          Revised to v3.2; Spartan-3 and Virtex-4 automotive device support
+07/13/2006  Xilinx, Inc.  3.1          Update to add 8.2i support; Revised to v3.1; Virtex-5 support
+01/11/2006  Xilinx, Inc.  2.3          Update to add 8.1i support; Revised to v2.3
+08/31/2005  Xilinx, Inc.  2.2          Update to add 7.1i SP4 support; Revised to v2.2
+04/28/2005  Xilinx, Inc.  2.1          Update to add 7.1i SP1 support; Revised to v2.1
+11/04/2004  Xilinx, Inc.  2.0          Update to add 6.3i support; Revised to v2.0
+05/21/2004  Xilinx, Inc.  1.1          Revised to v1.1; Virtex-4 support
+04/23/2004  Xilinx, Inc.  1.0          Update to add 6.2i support; First release
+================================================================================
+
+................................................................................
+
+
+8. LEGAL DISCLAIMER
+
+(c) Copyright 2002 - 2012 Xilinx, Inc. All rights reserved.
+
+  This file contains confidential and proprietary information
+  of Xilinx, Inc. and is protected under U.S. and
+  international copyright and other intellectual property
+  laws.
+
+  DISCLAIMER
+  This disclaimer is not a license and does not grant any
+  rights to the materials distributed herewith. Except as
+  otherwise provided in a valid license issued to you by
+  Xilinx, and to the maximum extent permitted by applicable
+  law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+  (2) Xilinx shall not be liable (whether in contract or tort,
+  including negligence, or under any other theory of
+  liability) for any loss or damage of any kind or nature
+  related to, arising under or in connection with these
+  materials, including for any direct, or any indirect,
+  special, incidental, or consequential loss or damage
+  (including loss of data, profits, goodwill, or any type of
+  loss or damage suffered as a result of any action brought
+  by a third party) even if such damage or loss was
+  reasonably foreseeable or Xilinx had been advised of the
+  possibility of the same. 
+
+  CRITICAL APPLICATIONS
+  Xilinx products are not designed or intended to be fail-
+  safe, or for use in any application requiring fail-safe
+  performance, such as life-support or safety devices or
+  systems, Class III medical devices, nuclear facilities,
+  applications related to the deployment of airbags, or any
+  other applications that could lead to death, personal
+  injury, or severe property or environmental damage
+  (individually and collectively, "Critical 
+  Applications"). Customer assumes the sole risk and 
+  liability of any use of Xilinx products in Critical 
+  Applications, subject only to applicable laws and 
+  regulations governing limitations on product liability. 
+ 
+  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+  PART OF THIS FILE AT ALL TIMES.

Frogwells_fpga_design/基于FPGA、DDR3和USB2.0的图像采集系统/debug/ov5640-vga-usb-normal/ipcore_dir/pixel_fifo/example_design/pixel_fifo_exdes.vhd

@@ -0,0 +1,142 @@
+--------------------------------------------------------------------------------
+--
+-- FIFO Generator Core - core top file for implementation
+--
+--------------------------------------------------------------------------------
+--
+-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--------------------------------------------------------------------------------
+--
+-- Filename: pixel_fifo_exdes.vhd
+--
+-- Description:
+--   This is the FIFO core wrapper with BUFG instances for clock connections.
+--
+--------------------------------------------------------------------------------
+-- Library Declarations
+--------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+
+library unisim;
+use unisim.vcomponents.all;
+
+--------------------------------------------------------------------------------
+-- Entity Declaration
+--------------------------------------------------------------------------------
+entity pixel_fifo_exdes is
+   PORT (
+           WR_CLK                    : IN  std_logic;
+     	   RD_CLK                    : IN  std_logic;
+           RST                       : IN  std_logic;
+           PROG_FULL                 : OUT std_logic;
+           WR_EN 		     : IN  std_logic;
+           RD_EN                     : IN  std_logic;
+           DIN                       : IN  std_logic_vector(64-1 DOWNTO 0);
+           DOUT                      : OUT std_logic_vector(64-1 DOWNTO 0);
+           FULL                      : OUT std_logic;
+           EMPTY                     : OUT std_logic);
+
+end pixel_fifo_exdes;
+
+
+
+architecture xilinx of pixel_fifo_exdes is
+
+  signal wr_clk_i : std_logic;
+  signal rd_clk_i : std_logic;
+
+
+
+  component pixel_fifo is
+   PORT (
+           WR_CLK                    : IN  std_logic;
+     	   RD_CLK                    : IN  std_logic;
+           RST                       : IN  std_logic;
+           PROG_FULL                 : OUT std_logic;
+           WR_EN 		     : IN  std_logic;
+           RD_EN                     : IN  std_logic;
+           DIN                       : IN  std_logic_vector(64-1 DOWNTO 0);
+           DOUT                      : OUT std_logic_vector(64-1 DOWNTO 0);
+           FULL                      : OUT std_logic;
+           EMPTY                     : OUT std_logic);
+
+  end component;
+
+
+begin
+
+  wr_clk_buf: bufg
+    PORT map(
+      i => WR_CLK,
+      o => wr_clk_i
+      );
+
+  rd_clk_buf: bufg
+    PORT map(
+      i => RD_CLK,
+      o => rd_clk_i
+      );
+
+
+  exdes_inst : pixel_fifo 
+    PORT MAP (
+           WR_CLK                    => wr_clk_i,
+           RD_CLK                    => rd_clk_i,
+           RST                       => rst,
+           PROG_FULL                 => prog_full,
+           WR_EN 		     => wr_en,
+           RD_EN                     => rd_en,
+           DIN                       => din,
+           DOUT                      => dout,
+           FULL                      => full,
+           EMPTY                     => empty);
+
+end xilinx;

Frogwells_fpga_design/基于FPGA、DDR3和USB2.0的图像采集系统/debug/ov5640-vga-usb-normal/ipcore_dir/pixel_fifo/fifo_generator_v9_3_readme.txt

@@ -0,0 +1,236 @@
+CHANGE LOG for LogiCORE FIFO Generator V9.3 Rev 1
+
+                    Release Date: December 18, 2012
+--------------------------------------------------------------------------------
+
+Table of Contents
+
+1. INTRODUCTION 
+2. DEVICE SUPPORT    
+3. NEW FEATURE HISTORY   
+4. RESOLVED ISSUES 
+5. KNOWN ISSUES & LIMITATIONS 
+6. TECHNICAL SUPPORT & FEEDBACK
+7. CORE RELEASE HISTORY 
+8. LEGAL DISCLAIMER 
+
+--------------------------------------------------------------------------------  
+
+
+1. INTRODUCTION
+
+For installation instructions for this release, please go to:
+
+   http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm
+
+For system requirements:
+
+   http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm
+
+This file contains release notes for the Xilinx LogiCORE IP FIFO Generator v9.3 Rev 1
+solution. For the latest core updates, see the product page at:
+ 
+   http://www.xilinx.com/products/ipcenter/FIFO_Generator.htm
+
+................................................................................
+
+
+2. DEVICE SUPPORT
+
+
+  2.1 ISE 
+   
+    The following device families are supported by the core for this release.
+    
+    
+    All 7 Series devices
+    Zynq-7000 devices
+    All Virtex-6 devices
+    All Spartan-6 devices
+    All Virtex-5 devices
+    All Spartan-3 devices
+    All Virtex-4 devices
+  
+  
+  2.2 Vivado 
+  
+    All 7 Series devices
+    Zynq-7000 devices
+
+................................................................................
+
+
+3. NEW FEATURE HISTORY
+
+
+  3.1 ISE 
+  
+    - ISE 14.4 software support
+
+  
+  3.2 Vivado
+  
+    - 2012.4 software support
+    - IP level constraint for Built-in FIFO reset synchronizer
+
+................................................................................
+
+
+4. RESOLVED ISSUES 
+
+
+  4.1 ISE 
+
+    - N/A
+
+
+  4.2 Vivado 
+
+    - N/A
+
+
+................................................................................
+
+
+5. KNOWN ISSUES & LIMITATIONS 
+
+
+  5.1 ISE 
+  
+    The following are known issues for v9.3 Rev 1 of this core at time of release:
+  
+    1. Importing an XCO file alters the XCO configurations
+  
+       Description: In the FIFO Generator GUI, after importing an XCO file (Independent clock, distributed memory configuration)
+       into a Virtex-4 CORE Generator project, if the FIFO type is changed to "Independent Clocks, Built-in FIFO" in page 1, 
+       page 2 does not correctly offer the Read Clock Frequency and Write Clock Frequency options as it should.
+    
+       CR 467240
+       AR 31379
+  
+    2. Status flags after the first write to Common Clock Built-in FIFO not guaranteed
+  
+       Description: When using Common Clock Built-in FIFO configuration with asynchronous reset for Virtex-6 FPGA,
+       correct behavior of the FIFO status flags cannot be guaranteed after the first write.
+    
+       Workaround: To work around this issue, synchronize the negative edge of reset to RDCLK/WRCLK.
+       For more information and additional workaround see Answer Record 41099.
+  
+  5.2 Vivado 
+
+    The following are known issues for v9.3 Rev 1 of this core at time of release:
+     
+    1. Description: When Trying to upgrade to latest version of FIFO Generator from older verions, following error message is seen 
+       ERROR: [Common 17-69] Command failed: invalid command name "puts" and Auto Upgradation does not work.
+      
+       CR 665836
+
+The most recent information, including known issues, workarounds, and
+resolutions for this version is provided in the IP Release Notes User Guide
+located at 
+
+   www.xilinx.com/support/documentation/user_guides/xtp025.pdf 
+
+................................................................................
+
+
+6. TECHNICAL SUPPORT & FEEDBACK
+
+To obtain technical support, create a WebCase at www.xilinx.com/support.
+Questions are routed to a team with expertise using this product.  
+
+Xilinx provides technical support for use of this product when used
+according to the guidelines described in the core documentation, and
+cannot guarantee timing, functionality, or support of this product for
+designs that do not follow specified guidelines.
+
+................................................................................
+
+
+7. CORE RELEASE HISTORY 
+
+Date        By            Version      Description
+================================================================================
+12/18/2012  Xilinx, Inc.  9.3 Rev 1    ISE 14.4 and Vivado 2012.4 support; IP level constraint for Built-in FIFO reset synchronizer
+10/16/2012  Xilinx, Inc.  9.3          ISE 14.3 and Vivado 2012.3 support; Clock Enable support for AXI4 Stream FIFO
+07/25/2012  Xilinx, Inc.  9.2          ISE 14.2 and Vivado 2012.2 support; Accurate data count support for AXI4 Stream Packet FIFO
+04/24/2012  Xilinx, Inc.  9.1          ISE 14.1 and Vivado 2012.1 support; Defense Grade 7 Series and Zynq devices, and Automotive Zynq device support
+                                       AXI FIFO data width support up to 4096; Programmable Full/Empty as sideband signals for AXI FIFO
+01/18/2012  Xilinx, Inc.  8.4          ISE 13.4 support and Packet FIFO feature addition; Artix-7 Lower Power and Automotive Artix-7 device support
+10/19/2011  Xilinx, Inc.  8.3          ISE 13.3 support and QVirtex-6L device support
+06/22/2011  Xilinx, Inc.  8.2          ISE 13.2 support and Kintex-7L, Virtex-7L, Artix-7 and Zynq-7000 device support
+03/01/2011  Xilinx, Inc.  8.1          ISE 13.1 support and Virtex-7 and Kintex-7 device support; Wiring Logic and Register Slice Support
+10/29/2010  Xilinx, Inc.  7.3          ISE 13.0.2 support
+09/21/2010  Xilinx, Inc.  7.2          ISE 12.3 support; AXI4 Support
+07/30/2010  Xilinx, Inc.  7.1          ISE 13.0.1 support
+06/18/2010  Xilinx, Inc.  6.2          ISE 12.2 support
+04/19/2010  Xilinx, Inc.  6.1          ISE 12.1 support
+12/02/2009  Xilinx, Inc.  5.3 rev 1    ISE 11.4 support; Spartan-6 Low Power and Automotive Spartan-6 Device support
+09/16/2009  Xilinx, Inc.  5.3          Update to add 11.3; Virtex-6 Low Power and Virtex-6 HXT Device support
+06/24/2009  Xilinx, Inc.  5.2          Update to add 11.2 and Virtex-6 CXT device support
+04/24/2009  Xilinx, Inc.  5.1          Update to add 11.1 and Virtex-6 and Spartan-6 device support
+09/19/2008  Xilinx, Inc.  4.4          Update to add 10.1 SP3 and Virtex-5 TXT device support and miscellaneous bug fixes
+03/24/2008  Xilinx, Inc.  4.3          Update to add 10.1 support and miscellaneous bug fixes
+10/03/2007  Xilinx, Inc.  4.2          Support for FWFT for Block RAM and Distributed RAM Common Clock FIFOs
+08/08/2007  Xilinx, Inc.  4.1          Update to add 9.2i support; Revised to v4.1; ECC support for block RAM FIFO
+04/02/2007  Xilinx, Inc.  3.3          Update to add 9.1i support; Revised to v3.3; Spartan-3A and Spartan-3A DSP support; ECC support
+09/21/2006  Xilinx, Inc.  3.2          Revised to v3.2; Spartan-3 and Virtex-4 automotive device support
+07/13/2006  Xilinx, Inc.  3.1          Update to add 8.2i support; Revised to v3.1; Virtex-5 support
+01/11/2006  Xilinx, Inc.  2.3          Update to add 8.1i support; Revised to v2.3
+08/31/2005  Xilinx, Inc.  2.2          Update to add 7.1i SP4 support; Revised to v2.2
+04/28/2005  Xilinx, Inc.  2.1          Update to add 7.1i SP1 support; Revised to v2.1
+11/04/2004  Xilinx, Inc.  2.0          Update to add 6.3i support; Revised to v2.0
+05/21/2004  Xilinx, Inc.  1.1          Revised to v1.1; Virtex-4 support
+04/23/2004  Xilinx, Inc.  1.0          Update to add 6.2i support; First release
+================================================================================
+
+................................................................................
+
+
+8. LEGAL DISCLAIMER
+
+(c) Copyright 2002 - 2012 Xilinx, Inc. All rights reserved.
+
+  This file contains confidential and proprietary information
+  of Xilinx, Inc. and is protected under U.S. and
+  international copyright and other intellectual property
+  laws.
+
+  DISCLAIMER
+  This disclaimer is not a license and does not grant any
+  rights to the materials distributed herewith. Except as
+  otherwise provided in a valid license issued to you by
+  Xilinx, and to the maximum extent permitted by applicable
+  law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+  WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+  AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+  BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+  INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+  (2) Xilinx shall not be liable (whether in contract or tort,
+  including negligence, or under any other theory of
+  liability) for any loss or damage of any kind or nature
+  related to, arising under or in connection with these
+  materials, including for any direct, or any indirect,
+  special, incidental, or consequential loss or damage
+  (including loss of data, profits, goodwill, or any type of
+  loss or damage suffered as a result of any action brought
+  by a third party) even if such damage or loss was
+  reasonably foreseeable or Xilinx had been advised of the
+  possibility of the same. 
+
+  CRITICAL APPLICATIONS
+  Xilinx products are not designed or intended to be fail-
+  safe, or for use in any application requiring fail-safe
+  performance, such as life-support or safety devices or
+  systems, Class III medical devices, nuclear facilities,
+  applications related to the deployment of airbags, or any
+  other applications that could lead to death, personal
+  injury, or severe property or environmental damage
+  (individually and collectively, "Critical 
+  Applications"). Customer assumes the sole risk and 
+  liability of any use of Xilinx products in Critical 
+  Applications, subject only to applicable laws and 
+  regulations governing limitations on product liability. 
+ 
+  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+  PART OF THIS FILE AT ALL TIMES.

Frogwells_fpga_design/基于FPGA、DDR3和USB2.0的图像采集系统/debug/ov5640-vga-usb-normal/ipcore_dir/pixel_fifo/implement/planAhead_ise.tcl

@@ -0,0 +1,67 @@
+# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+
+
+set device xc6slx45csg324-2
+set projName pixel_fifo
+set design pixel_fifo
+set projDir [file dirname [info script]]
+create_project $projName $projDir/results/$projName -part $device -force
+set_property design_mode RTL [current_fileset -srcset]
+set top_module pixel_fifo_exdes
+add_files -norecurse {../../example_design/pixel_fifo_exdes.vhd}
+add_files -norecurse {./pixel_fifo.ngc}
+import_files -fileset [get_filesets constrs_1] -force -norecurse {../../example_design/pixel_fifo_exdes.xdc}
+set_property top pixel_fifo_exdes [get_property srcset [current_run]]
+synth_design
+opt_design 
+place_design 
+route_design 
+write_sdf -rename_top_module pixel_fifo_exdes -file routed.sdf 
+write_verilog -nolib -mode timesim -sdf_anno false -rename_top_module pixel_fifo_exdes routed.v
+report_timing -nworst 30 -path_type full -file routed.twr
+report_drc -file report.drc
+write_bitstream -bitgen_options {-g UnconstrainedPins:Allow}

Frogwells_fpga_design/基于FPGA、DDR3和USB2.0的图像采集系统/debug/ov5640-vga-usb-normal/ipcore_dir/pixel_fifo/simulation/functional/vcs_session.tcl

@@ -0,0 +1,77 @@
+#--------------------------------------------------------------------------------
+#--
+#-- FIFO Generator Core Demo Testbench 
+#--
+#--------------------------------------------------------------------------------
+# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# Filename: vcs_session.tcl
+#
+# Description:
+#   This is the VCS wave form file.
+#
+#--------------------------------------------------------------------------------
+if { ![gui_is_db_opened -db {pixel_fifo.vpd}] } {
+	gui_open_db -design V1 -file pixel_fifo.vpd -nosource
+}
+gui_set_precision 1ps
+gui_set_time_units 1ps
+
+
+gui_open_window Wave
+gui_sg_create pixel_fifo_Group
+gui_list_add_group -id Wave.1 {pixel_fifo_Group}
+
+gui_sg_addsignal -group pixel_fifo_Group /pixel_fifo_tb/pixel_fifo_synth_inst/pixel_fifo_inst/RST
+gui_sg_addsignal -group pixel_fifo_Group  WRITE -divider
+gui_sg_addsignal -group pixel_fifo_Group /pixel_fifo_tb/pixel_fifo_synth_inst/pixel_fifo_inst/WR_CLK
+gui_sg_addsignal -group pixel_fifo_Group /pixel_fifo_tb/pixel_fifo_synth_inst/pixel_fifo_inst/WR_EN
+gui_sg_addsignal -group pixel_fifo_Group /pixel_fifo_tb/pixel_fifo_synth_inst/pixel_fifo_inst/FULL
+gui_sg_addsignal -group pixel_fifo_Group  READ -divider
+gui_sg_addsignal -group pixel_fifo_Group /pixel_fifo_tb/pixel_fifo_synth_inst/pixel_fifo_inst/RD_CLK
+gui_sg_addsignal -group pixel_fifo_Group /pixel_fifo_tb/pixel_fifo_synth_inst/pixel_fifo_inst/RD_EN
+gui_sg_addsignal -group pixel_fifo_Group /pixel_fifo_tb/pixel_fifo_synth_inst/pixel_fifo_inst/EMPTY
+gui_zoom -window Wave.1 -full

Frogwells_fpga_design/基于FPGA、DDR3和USB2.0的图像采集系统/debug/ov5640-vga-usb-normal/ipcore_dir/pixel_fifo/simulation/functional/wave_isim.tcl

@@ -0,0 +1,68 @@
+#--------------------------------------------------------------------------------
+#--
+#-- FIFO Generator Core Demo Testbench 
+#--
+#--------------------------------------------------------------------------------
+# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# Filename: wave_isim.tcl
+#
+# Description:
+#   This is the ISIM wave form file.
+#
+#--------------------------------------------------------------------------------
+wcfg new
+isim set radix hex
+wave add /pixel_fifo_tb/pixel_fifo_synth_inst/pixel_fifo_inst/RST
+wave add /pixel_fifo_tb/pixel_fifo_synth_inst/pixel_fifo_inst/WR_CLK
+wave add /pixel_fifo_tb/pixel_fifo_synth_inst/pixel_fifo_inst/WR_EN
+wave add /pixel_fifo_tb/pixel_fifo_synth_inst/pixel_fifo_inst/FULL
+wave add /pixel_fifo_tb/pixel_fifo_synth_inst/pixel_fifo_inst/RD_CLK
+wave add /pixel_fifo_tb/pixel_fifo_synth_inst/pixel_fifo_inst/RD_EN
+wave add /pixel_fifo_tb/pixel_fifo_synth_inst/pixel_fifo_inst/EMPTY
+run all
+quit
+

Frogwells_fpga_design/基于FPGA、DDR3和USB2.0的图像采集系统/debug/ov5640-vga-usb-normal/ipcore_dir/pixel_fifo/simulation/functional/wave_ncsim.sv

@@ -0,0 +1,70 @@
+#--------------------------------------------------------------------------------
+#--
+#-- FIFO Generator Core Demo Testbench 
+#--
+#--------------------------------------------------------------------------------
+# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+# 
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+# 
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+# 
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+# 
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+# Filename: wave_ncsim.sv
+#
+# Description:
+#   This is the IUS wave form file.
+#
+#--------------------------------------------------------------------------------
+
+window new WaveWindow  -name  "Waves for FIFO Generator Example Design"
+waveform  using  "Waves for FIFO Generator Example Design"
+
+waveform add -signals /pixel_fifo_tb/pixel_fifo_synth_inst/pixel_fifo_inst/RST
+waveform add -label WRITE
+waveform add -signals /pixel_fifo_tb/pixel_fifo_synth_inst/pixel_fifo_inst/WR_CLK
+waveform add -signals /pixel_fifo_tb/pixel_fifo_synth_inst/pixel_fifo_inst/WR_EN
+waveform add -signals /pixel_fifo_tb/pixel_fifo_synth_inst/pixel_fifo_inst/FULL
+waveform add -label READ
+waveform add -signals /pixel_fifo_tb/pixel_fifo_synth_inst/pixel_fifo_inst/RD_CLK
+waveform add -signals /pixel_fifo_tb/pixel_fifo_synth_inst/pixel_fifo_inst/RD_EN
+waveform add -signals /pixel_fifo_tb/pixel_fifo_synth_inst/pixel_fifo_inst/EMPTY
+console submit -using simulator -wait no "run"

Frogwells_fpga_design/基于FPGA、DDR3和USB2.0的图像采集系统/debug/ov5640-vga-usb-normal/ipcore_dir/pixel_fifo/simulation/pixel_fifo_dgen.vhd

@@ -0,0 +1,123 @@
+--------------------------------------------------------------------------------
+--
+-- FIFO Generator Core Demo Testbench 
+--
+--------------------------------------------------------------------------------
+--
+-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--------------------------------------------------------------------------------
+--
+-- Filename: pixel_fifo_dgen.vhd
+--
+-- Description:
+--   Used for write interface stimulus generation
+--
+--------------------------------------------------------------------------------
+-- Library Declarations
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.all;
+USE IEEE.std_logic_arith.all;
+USE IEEE.std_logic_misc.all;
+
+LIBRARY work;
+USE work.pixel_fifo_pkg.ALL;
+
+ENTITY pixel_fifo_dgen IS
+  GENERIC (
+	    C_DIN_WIDTH   : INTEGER := 32;
+	    C_DOUT_WIDTH  : INTEGER := 32;
+	    C_CH_TYPE     : INTEGER := 0;
+	    TB_SEED       : INTEGER := 2
+	 );
+  PORT (
+        RESET     : IN STD_LOGIC;
+        WR_CLK    : IN STD_LOGIC;
+        PRC_WR_EN : IN STD_LOGIC;
+        FULL      : IN STD_LOGIC;  
+        WR_EN     : OUT STD_LOGIC;      
+        WR_DATA   : OUT STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0)
+       );
+END ENTITY;
+
+
+ARCHITECTURE fg_dg_arch OF pixel_fifo_dgen IS
+ 
+  CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
+  CONSTANT LOOP_COUNT   : INTEGER := divroundup(C_DATA_WIDTH,8);
+  
+  SIGNAL pr_w_en        : STD_LOGIC := '0';
+  SIGNAL rand_num       : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 DOWNTO 0);
+  SIGNAL wr_data_i      : STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
+ BEGIN
+  
+   WR_EN   <= PRC_WR_EN ;
+   WR_DATA <= wr_data_i AFTER 50 ns;
+
+  ----------------------------------------------
+  -- Generation of DATA
+  ----------------------------------------------
+  gen_stim:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
+    rd_gen_inst1:pixel_fifo_rng
+    GENERIC MAP(
+    	       WIDTH => 8,
+               SEED  => TB_SEED+N
+               )
+    PORT MAP(
+              CLK        => WR_CLK,
+	      RESET      => RESET,
+              RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
+              ENABLE     => pr_w_en
+            );
+  END GENERATE; 
+
+     pr_w_en <= PRC_WR_EN AND NOT FULL;
+     wr_data_i <= rand_num(C_DIN_WIDTH-1 DOWNTO 0);
+
+
+END ARCHITECTURE;

Frogwells_fpga_design/基于FPGA、DDR3和USB2.0的图像采集系统/debug/ov5640-vga-usb-normal/ipcore_dir/pixel_fifo/simulation/pixel_fifo_dverif.vhd

@@ -0,0 +1,159 @@
+--------------------------------------------------------------------------------
+--
+-- FIFO Generator Core Demo Testbench 
+--
+--------------------------------------------------------------------------------
+--
+-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--------------------------------------------------------------------------------
+--
+-- Filename: pixel_fifo_dverif.vhd
+--
+-- Description:
+--   Used for FIFO read interface stimulus generation and data checking
+--
+--------------------------------------------------------------------------------
+-- Library Declarations
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.all;
+USE IEEE.std_logic_arith.all;
+USE IEEE.std_logic_misc.all;
+
+LIBRARY work;
+USE work.pixel_fifo_pkg.ALL;
+
+ENTITY pixel_fifo_dverif IS
+  GENERIC(
+   C_DIN_WIDTH        : INTEGER := 0;
+   C_DOUT_WIDTH       : INTEGER := 0;
+   C_USE_EMBEDDED_REG : INTEGER := 0;
+   C_CH_TYPE          : INTEGER := 0;
+   TB_SEED            : INTEGER := 2
+  );
+  PORT(
+       RESET          : IN STD_LOGIC;
+       RD_CLK         : IN STD_LOGIC;
+       PRC_RD_EN      : IN STD_LOGIC;
+       EMPTY          : IN STD_LOGIC;
+       DATA_OUT       : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
+       RD_EN          : OUT STD_LOGIC;
+       DOUT_CHK       : OUT STD_LOGIC
+      );
+END ENTITY;
+
+
+ARCHITECTURE fg_dv_arch OF pixel_fifo_dverif IS
+ 
+ CONSTANT C_DATA_WIDTH    : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
+ CONSTANT EXTRA_WIDTH     : INTEGER := if_then_else(C_CH_TYPE = 2,1,0);
+ CONSTANT LOOP_COUNT      : INTEGER := divroundup(C_DATA_WIDTH+EXTRA_WIDTH,8);
+
+ SIGNAL expected_dout     : STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
+ SIGNAL data_chk          : STD_LOGIC := '1';
+ SIGNAL rand_num          : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 downto 0);
+ SIGNAL rd_en_i           : STD_LOGIC := '0';
+ SIGNAL pr_r_en           : STD_LOGIC := '0';
+ SIGNAL rd_en_d1          : STD_LOGIC := '0';
+BEGIN
+
+ 
+  DOUT_CHK <= data_chk;
+  RD_EN    <= rd_en_i;
+  rd_en_i  <= PRC_RD_EN;
+  
+ 
+  data_fifo_chk:IF(C_CH_TYPE /=2) GENERATE 
+  -------------------------------------------------------
+  -- Expected data generation and checking for data_fifo
+  -------------------------------------------------------
+      PROCESS (RD_CLK,RESET)
+      BEGIN
+        IF (RESET = '1') THEN
+          rd_en_d1 <= '0';
+        ELSIF (RD_CLK'event AND RD_CLK='1') THEN
+          IF(EMPTY = '0' AND rd_en_i='1' AND rd_en_d1 = '0') THEN
+            rd_en_d1 <= '1';
+          END IF;
+        END IF;
+      END PROCESS;
+   
+      pr_r_en       <= rd_en_i AND NOT EMPTY AND rd_en_d1;
+      expected_dout <= rand_num(C_DOUT_WIDTH-1 DOWNTO 0);
+
+    gen_num:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
+      rd_gen_inst2:pixel_fifo_rng
+      GENERIC MAP(
+      	        WIDTH => 8,
+                SEED  => TB_SEED+N
+                 )
+      PORT MAP(
+                CLK        => RD_CLK,
+	        RESET      => RESET,
+                RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
+                ENABLE     => pr_r_en 	    
+              );
+    END GENERATE;    
+    
+      PROCESS (RD_CLK,RESET)
+      BEGIN
+        IF(RESET = '1') THEN
+          data_chk <= '0';
+        ELSIF (RD_CLK'event AND RD_CLK='1') THEN
+          IF((EMPTY = '0') AND (rd_en_i = '1' AND rd_en_d1 = '1')) THEN
+            IF(DATA_OUT = expected_dout) THEN
+              data_chk <= '0';
+            ELSE
+              data_chk <= '1';
+            END IF;
+          END IF;
+        END IF;
+      END PROCESS;
+  END GENERATE data_fifo_chk;
+
+END ARCHITECTURE;

Frogwells_fpga_design/基于FPGA、DDR3和USB2.0的图像采集系统/debug/ov5640-vga-usb-normal/ipcore_dir/pixel_fifo/simulation/pixel_fifo_pctrl.vhd

@@ -0,0 +1,541 @@
+
+--------------------------------------------------------------------------------
+--
+-- FIFO Generator Core Demo Testbench 
+--
+--------------------------------------------------------------------------------
+--
+-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
+-- 
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+-- 
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+-- 
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+-- 
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--------------------------------------------------------------------------------
+--
+-- Filename: pixel_fifo_pctrl.vhd
+--
+-- Description:
+--   Used for protocol control on write and read interface stimulus and status generation
+--
+--------------------------------------------------------------------------------
+-- Library Declarations
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.std_logic_unsigned.all;
+USE IEEE.std_logic_arith.all;
+USE IEEE.std_logic_misc.all;
+
+LIBRARY work;
+USE work.pixel_fifo_pkg.ALL;
+
+ENTITY pixel_fifo_pctrl IS
+  GENERIC(
+   AXI_CHANNEL         : STRING  :="NONE";
+   C_APPLICATION_TYPE  : INTEGER := 0;
+   C_DIN_WIDTH         : INTEGER := 0;
+   C_DOUT_WIDTH        : INTEGER := 0;
+   C_WR_PNTR_WIDTH     : INTEGER := 0;
+   C_RD_PNTR_WIDTH     : INTEGER := 0;
+   C_CH_TYPE           : INTEGER := 0;
+   FREEZEON_ERROR      : INTEGER := 0;
+   TB_STOP_CNT         : INTEGER := 2;
+   TB_SEED             : INTEGER := 2
+  );
+  PORT(
+       RESET_WR        : IN STD_LOGIC;
+       RESET_RD        : IN STD_LOGIC;
+       WR_CLK          : IN STD_LOGIC;
+       RD_CLK          : IN STD_LOGIC;
+       FULL            : IN STD_LOGIC;
+       EMPTY           : IN STD_LOGIC;
+       ALMOST_FULL     : IN STD_LOGIC;
+       ALMOST_EMPTY    : IN STD_LOGIC;
+       DATA_IN         : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
+       DATA_OUT        : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
+       DOUT_CHK        : IN STD_LOGIC;
+       PRC_WR_EN       : OUT STD_LOGIC;
+       PRC_RD_EN       : OUT STD_LOGIC;
+       RESET_EN        : OUT STD_LOGIC;
+       SIM_DONE        : OUT STD_LOGIC;
+       STATUS          : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+      );
+END ENTITY;
+
+
+ARCHITECTURE fg_pc_arch OF pixel_fifo_pctrl IS
+ 
+ CONSTANT C_DATA_WIDTH   : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
+ CONSTANT LOOP_COUNT     : INTEGER := divroundup(C_DATA_WIDTH,8);
+ CONSTANT D_WIDTH_DIFF   :   INTEGER := log2roundup(C_DOUT_WIDTH/C_DIN_WIDTH);
+
+ SIGNAL data_chk_i       : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
+ SIGNAL full_chk_i       : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
+ SIGNAL empty_chk_i      : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
+ SIGNAL status_i         : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
+ SIGNAL status_d1_i      : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
+ SIGNAL wr_en_gen        : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
+ SIGNAL rd_en_gen        : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
+ SIGNAL wr_cntr          : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0)   := (OTHERS => '0');
+ SIGNAL full_as_timeout  : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0)   := (OTHERS => '0');
+ SIGNAL full_ds_timeout  : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
+ SIGNAL rd_cntr          : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0)   := (OTHERS => '0'); 
+ SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0)  := (OTHERS => '0'); 
+ SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0'); 
+ SIGNAL wr_en_i          : STD_LOGIC := '0';
+ SIGNAL rd_en_i          : STD_LOGIC := '0';
+ SIGNAL state            : STD_LOGIC := '0';
+ SIGNAL wr_control       : STD_LOGIC := '0';
+ SIGNAL rd_control       : STD_LOGIC := '0';
+ SIGNAL stop_on_err      : STD_LOGIC := '0';
+ SIGNAL sim_stop_cntr    : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8);
+ SIGNAL sim_done_i       : STD_LOGIC := '0';
+ SIGNAL rdw_gt_wrw       : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
+ SIGNAL wrw_gt_rdw       : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
+ SIGNAL rd_activ_cont    : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0');
+ SIGNAL prc_we_i         : STD_LOGIC := '0';
+ SIGNAL prc_re_i         : STD_LOGIC := '0';
+ SIGNAL reset_en_i       : STD_LOGIC := '0';
+ SIGNAL sim_done_d1      : STD_LOGIC := '0';
+ SIGNAL sim_done_wr1     : STD_LOGIC := '0';
+ SIGNAL sim_done_wr2     : STD_LOGIC := '0'; 
+ SIGNAL empty_d1         : STD_LOGIC := '0';
+ SIGNAL empty_wr_dom1    : STD_LOGIC := '0';
+ SIGNAL state_d1         : STD_LOGIC := '0';
+ SIGNAL state_rd_dom1    : STD_LOGIC := '0';
+ SIGNAL rd_en_d1         : STD_LOGIC := '0';
+ SIGNAL rd_en_wr1        : STD_LOGIC := '0';
+ SIGNAL wr_en_d1         : STD_LOGIC := '0';
+ SIGNAL wr_en_rd1        : STD_LOGIC := '0';
+ SIGNAL full_chk_d1      : STD_LOGIC := '0';
+ SIGNAL full_chk_rd1     : STD_LOGIC := '0';
+ SIGNAL empty_wr_dom2    : STD_LOGIC := '0';
+
+ SIGNAL state_rd_dom2    : STD_LOGIC := '0';
+ SIGNAL state_rd_dom3    : STD_LOGIC := '0';
+ SIGNAL rd_en_wr2        : STD_LOGIC := '0';
+ SIGNAL wr_en_rd2        : STD_LOGIC := '0';
+ SIGNAL full_chk_rd2     : STD_LOGIC := '0';
+ SIGNAL reset_en_d1      : STD_LOGIC := '0';
+ SIGNAL reset_en_rd1     : STD_LOGIC := '0';
+ SIGNAL reset_en_rd2     : STD_LOGIC := '0';
+
+ SIGNAL data_chk_wr_d1   : STD_LOGIC := '0';
+ SIGNAL data_chk_rd1     : STD_LOGIC := '0';
+ SIGNAL data_chk_rd2     : STD_LOGIC := '0';
+ SIGNAL post_rst_dly_wr  : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
+ SIGNAL post_rst_dly_rd  : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
+BEGIN
+ status_i  <= data_chk_i & full_chk_rd2 & empty_chk_i & '0' & '0';
+ STATUS    <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high);
+
+ prc_we_i <= wr_en_i  WHEN sim_done_wr2 = '0' ELSE '0';
+ prc_re_i <= rd_en_i  WHEN sim_done_i   = '0' ELSE '0';
+
+ SIM_DONE   <= sim_done_i;
+ rdw_gt_wrw <= (OTHERS => '1');
+ wrw_gt_rdw <= (OTHERS => '1');
+
+ PROCESS(RD_CLK)
+ BEGIN
+   IF (RD_CLK'event AND RD_CLK='1') THEN
+     IF(prc_re_i = '1') THEN
+       rd_activ_cont <= rd_activ_cont + "1";
+     END IF;
+   END IF;
+ END PROCESS;
+
+
+ PROCESS(sim_done_i)
+ BEGIN
+    assert sim_done_i = '0'
+    report "Simulation Complete for:" & AXI_CHANNEL
+    severity note;
+ END PROCESS;
+
+-----------------------------------------------------
+-- SIM_DONE SIGNAL GENERATION
+-----------------------------------------------------
+PROCESS (RD_CLK,RESET_RD)
+BEGIN
+    IF(RESET_RD = '1') THEN
+      --sim_done_i <= '0';
+    ELSIF(RD_CLK'event AND RD_CLK='1') THEN
+      IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN
+     	sim_done_i <= '1';
+      END IF;
+    END IF;
+END PROCESS;
+
+ -- TB Timeout/Stop
+ fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE
+   PROCESS (RD_CLK)
+   BEGIN
+       IF (RD_CLK'event AND RD_CLK='1') THEN
+         IF(state_rd_dom2 = '0' AND state_rd_dom3 = '1') THEN
+           sim_stop_cntr <= sim_stop_cntr - "1";
+         END IF;
+       END IF;
+   END PROCESS;
+ END GENERATE fifo_tb_stop_run;
+
+
+  -- Stop when error found
+  PROCESS (RD_CLK)
+  BEGIN
+    IF (RD_CLK'event AND RD_CLK='1') THEN
+      IF(sim_done_i = '0') THEN
+        status_d1_i <= status_i OR status_d1_i;
+      END IF;
+      IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN
+        stop_on_err <= '1';
+      END IF;
+    END IF;
+  END PROCESS;
+  -----------------------------------------------------
+
+  -----------------------------------------------------
+  -- CHECKS FOR FIFO
+  -----------------------------------------------------
+
+
+  PROCESS(RD_CLK,RESET_RD)
+  BEGIN
+    IF(RESET_RD = '1') THEN
+      post_rst_dly_rd <= (OTHERS => '1');
+    ELSIF (RD_CLK'event AND RD_CLK='1') THEN
+      post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4);
+    END IF;
+  END PROCESS;
+  
+  PROCESS(WR_CLK,RESET_WR)
+  BEGIN
+    IF(RESET_WR = '1') THEN
+      post_rst_dly_wr <= (OTHERS => '1');
+    ELSIF (WR_CLK'event AND WR_CLK='1') THEN
+      post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4);
+    END IF;
+  END PROCESS;
+
+
+  -- FULL de-assert Counter
+  PROCESS(WR_CLK,RESET_WR) 
+  BEGIN
+    IF(RESET_WR = '1') THEN
+      full_ds_timeout <= (OTHERS => '0');
+    ELSIF(WR_CLK'event AND WR_CLK='1') THEN
+      IF(state = '1') THEN
+        IF(rd_en_wr2 = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN
+          full_ds_timeout <= full_ds_timeout + '1';
+        END IF;
+      ELSE
+  	full_ds_timeout <= (OTHERS => '0');
+      END IF;
+    END IF;
+  END PROCESS;
+   
+ 
+ -- EMPTY deassert counter
+  PROCESS(RD_CLK,RESET_RD) 
+  BEGIN
+    IF(RESET_RD = '1') THEN
+      empty_ds_timeout <= (OTHERS => '0');
+    ELSIF(RD_CLK'event AND RD_CLK='1') THEN
+      IF(state = '0') THEN
+        IF(wr_en_rd2 = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN
+          empty_ds_timeout <= empty_ds_timeout + '1';
+        END IF;
+      ELSE
+  	empty_ds_timeout <= (OTHERS => '0');
+      END IF;
+    END IF;
+  END PROCESS;
+
+  -- Full check signal generation
+  PROCESS(WR_CLK,RESET_WR) 
+  BEGIN
+    IF(RESET_WR = '1') THEN
+      full_chk_i <= '0';
+    ELSIF(WR_CLK'event AND WR_CLK='1') THEN
+      IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
+        full_chk_i <= '0';
+      ELSE
+        full_chk_i <= AND_REDUCE(full_as_timeout) OR 
+		      AND_REDUCE(full_ds_timeout);
+      END IF;
+    END IF;
+  END PROCESS;
+
+  -- Empty checks
+  PROCESS(RD_CLK,RESET_RD) 
+  BEGIN
+    IF(RESET_RD = '1') THEN
+      empty_chk_i <= '0';
+    ELSIF(RD_CLK'event AND RD_CLK='1') THEN
+      IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
+        empty_chk_i <= '0';
+      ELSE
+        empty_chk_i <= AND_REDUCE(empty_as_timeout) OR 
+		       AND_REDUCE(empty_ds_timeout);
+      END IF;
+    END IF;
+  END PROCESS;
+
+  fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE
+    PRC_WR_EN  <= prc_we_i  AFTER 50 ns;
+    PRC_RD_EN  <= prc_re_i  AFTER 100 ns;
+    data_chk_i <= dout_chk;
+  END GENERATE fifo_d_chk;
+  -----------------------------------------------------
+ 
+
+ -----------------------------------------------------
+ -- SYNCHRONIZERS B/W WRITE AND READ DOMAINS
+ -----------------------------------------------------
+   PROCESS(WR_CLK,RESET_WR)
+   BEGIN
+     IF(RESET_WR = '1') THEN
+       empty_wr_dom1  <= '1';
+       empty_wr_dom2  <= '1';
+       state_d1       <= '0';
+       wr_en_d1       <= '0';
+       rd_en_wr1      <= '0';
+       rd_en_wr2      <= '0';
+       full_chk_d1    <= '0';
+       reset_en_d1    <= '0';
+       sim_done_wr1   <= '0';
+       sim_done_wr2   <= '0';
+     ELSIF (WR_CLK'event AND WR_CLK='1') THEN
+       sim_done_wr1   <= sim_done_d1;
+       sim_done_wr2   <= sim_done_wr1;
+       reset_en_d1    <= reset_en_i;
+       state_d1       <= state;
+       empty_wr_dom1  <= empty_d1;
+       empty_wr_dom2  <= empty_wr_dom1;
+       wr_en_d1       <= wr_en_i;
+       rd_en_wr1      <= rd_en_d1;
+       rd_en_wr2      <= rd_en_wr1;
+       full_chk_d1    <= full_chk_i;
+     END IF;
+   END PROCESS;
+
+   PROCESS(RD_CLK,RESET_RD)
+   BEGIN
+     IF(RESET_RD = '1') THEN
+         empty_d1       <= '1';
+         state_rd_dom1  <= '0';
+         state_rd_dom2  <= '0';
+         state_rd_dom3  <= '0';
+         wr_en_rd1      <= '0';
+         wr_en_rd2      <= '0';
+         rd_en_d1       <= '0';
+         full_chk_rd1   <= '0';
+         full_chk_rd2   <= '0';
+         reset_en_rd1   <= '0';
+         reset_en_rd2   <= '0';
+         sim_done_d1    <= '0';
+     ELSIF (RD_CLK'event AND RD_CLK='1') THEN
+         sim_done_d1    <= sim_done_i;
+         reset_en_rd1   <= reset_en_d1;
+         reset_en_rd2   <= reset_en_rd1;
+         empty_d1       <= EMPTY;
+         rd_en_d1       <= rd_en_i;
+         state_rd_dom1  <= state_d1;
+         state_rd_dom2  <= state_rd_dom1;
+         state_rd_dom3  <= state_rd_dom2;
+         wr_en_rd1      <= wr_en_d1;
+         wr_en_rd2      <= wr_en_rd1;
+         full_chk_rd1   <= full_chk_d1;
+         full_chk_rd2   <= full_chk_rd1;
+     END IF;
+   END PROCESS;
+   
+   RESET_EN   <= reset_en_rd2;
+ 
+
+   data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE  
+    -----------------------------------------------------
+    -- WR_EN GENERATION
+    -----------------------------------------------------
+    gen_rand_wr_en:pixel_fifo_rng
+    GENERIC MAP(
+    	         WIDTH => 8,
+                 SEED  => TB_SEED+1
+               )
+    PORT MAP(
+              CLK        => WR_CLK,
+              RESET      => RESET_WR,
+              RANDOM_NUM => wr_en_gen,
+              ENABLE     => '1'
+            );
+
+    PROCESS(WR_CLK,RESET_WR)
+    BEGIN
+      IF(RESET_WR = '1') THEN
+        wr_en_i   <=  '0';
+      ELSIF(WR_CLK'event AND WR_CLK='1') THEN
+        IF(state = '1') THEN
+          wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control;
+        ELSE
+          wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4)); 
+        END IF;
+      END IF;
+    END PROCESS;
+    
+    -----------------------------------------------------
+    -- WR_EN CONTROL
+    -----------------------------------------------------
+    PROCESS(WR_CLK,RESET_WR)
+    BEGIN
+      IF(RESET_WR = '1') THEN
+        wr_cntr         <= (OTHERS => '0');
+	wr_control      <= '1';
+	full_as_timeout <= (OTHERS => '0');
+      ELSIF(WR_CLK'event AND WR_CLK='1') THEN
+	IF(state = '1') THEN
+	  IF(wr_en_i = '1') THEN
+	    wr_cntr <= wr_cntr + "1";
+	  END IF;
+	  full_as_timeout <= (OTHERS => '0');
+	ELSE
+	  wr_cntr <= (OTHERS => '0');
+	  IF(rd_en_wr2 = '0') THEN
+	    IF(wr_en_i = '1') THEN
+  	      full_as_timeout <= full_as_timeout + "1";
+  	    END IF;
+	  ELSE 
+	    full_as_timeout <= (OTHERS => '0');
+	  END IF;
+	END IF;
+
+	wr_control <= NOT wr_cntr(wr_cntr'high);
+
+      END IF;
+    END PROCESS;
+
+    -----------------------------------------------------
+    -- RD_EN GENERATION
+    -----------------------------------------------------
+    gen_rand_rd_en:pixel_fifo_rng
+    GENERIC MAP(
+    	         WIDTH => 8,
+                 SEED  => TB_SEED
+               )
+    PORT MAP(
+              CLK        => RD_CLK,
+              RESET      => RESET_RD,
+              RANDOM_NUM => rd_en_gen,
+              ENABLE     => '1'
+            );
+
+    PROCESS(RD_CLK,RESET_RD)
+    BEGIN
+      IF(RESET_RD = '1') THEN
+	rd_en_i    <= '0';
+      ELSIF(RD_CLK'event AND RD_CLK='1') THEN
+        IF(state_rd_dom2 = '0') THEN
+  	    rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4));
+        ELSE
+          rd_en_i <= rd_en_gen(0) OR rd_en_gen(6);
+        END IF;
+      END IF;
+    END PROCESS;
+
+    -----------------------------------------------------
+    -- RD_EN CONTROL
+    -----------------------------------------------------
+    PROCESS(RD_CLK,RESET_RD)
+    BEGIN
+      IF(RESET_RD = '1') THEN
+        rd_cntr    <= (OTHERS => '0');
+	rd_control <= '1';
+	empty_as_timeout <= (OTHERS => '0');
+      ELSIF(RD_CLK'event AND RD_CLK='1') THEN
+	IF(state_rd_dom2 = '0') THEN
+	  IF(rd_en_i = '1') THEN
+	    rd_cntr <= rd_cntr + "1";
+	  END IF;
+	  empty_as_timeout <= (OTHERS => '0');
+	ELSE
+	  rd_cntr <= (OTHERS => '0');
+	  IF(wr_en_rd2 = '0') THEN
+	    IF(rd_en_i = '1') THEN
+  	      empty_as_timeout <= empty_as_timeout + "1";
+  	    END IF;
+	  ELSE 
+	    empty_as_timeout <= (OTHERS => '0');
+	  END IF;
+	END IF;
+	
+	rd_control <= NOT rd_cntr(rd_cntr'high);
+
+      END IF;
+    END PROCESS;
+
+    -----------------------------------------------------
+    -- STIMULUS CONTROL
+    -----------------------------------------------------
+    PROCESS(WR_CLK,RESET_WR)
+    BEGIN
+      IF(RESET_WR = '1') THEN
+        state      <= '0';
+	reset_en_i <= '0';
+      ELSIF(WR_CLK'event AND WR_CLK='1') THEN
+        CASE state IS
+          WHEN '0' => 
+            IF(FULL = '1' AND empty_wr_dom2 = '0') THEN
+              state      <= '1';
+	      reset_en_i <= '0';
+    	    END IF;
+          WHEN '1' => 
+            IF(empty_wr_dom2 = '1' AND FULL = '0') THEN
+              state    	 <= '0';
+	      reset_en_i <= '1';
+    	    END IF;
+          WHEN OTHERS => state <= state;
+	END CASE;
+      END IF;
+    END PROCESS;
+  END GENERATE data_fifo_en;
+
+END ARCHITECTURE;