diff --git "a/Frogwells_fpga_design/\345\237\272\344\272\216FPGA\343\200\201DDR3\345\222\214USB2.0\347\232\204\345\233\276\345\203\217\351\207\207\351\233\206\347\263\273\347\273\237/debug/ddr_test/rtl/traffic_gen/afifo.v" "b/Frogwells_fpga_design/\345\237\272\344\272\216FPGA\343\200\201DDR3\345\222\214USB2.0\347\232\204\345\233\276\345\203\217\351\207\207\351\233\206\347\263\273\347\273\237/debug/ddr_test/rtl/traffic_gen/afifo.v" new file mode 100644 index 0000000000000000000000000000000000000000..4edbafa8051e4275377c4b32d099ed8737104dad --- /dev/null +++ "b/Frogwells_fpga_design/\345\237\272\344\272\216FPGA\343\200\201DDR3\345\222\214USB2.0\347\232\204\345\233\276\345\203\217\351\207\207\351\233\206\347\263\273\347\273\237/debug/ddr_test/rtl/traffic_gen/afifo.v" @@ -0,0 +1,266 @@ +//***************************************************************************** +// (c) Copyright 2008-2009 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: %version +// \ \ Application: MIG +// / / Filename: afifo.v +// /___/ /\ Date Last Modified: $Date: 2011/06/02 07:16:32 $ +// \ \ / \ Date Created: Oct 21 2008 +// \___\/\___\ +// +//Device: Spartan6 +//Design Name: DDR/DDR2/DDR3/LPDDR +//Purpose: A generic synchronous fifo. +//Reference: +//Revision History: + +//***************************************************************************** + +`timescale 1ps/1ps + +module afifo # +( + parameter TCQ = 100, + parameter DSIZE = 32, + parameter FIFO_DEPTH = 16, + parameter ASIZE = 4, + parameter SYNC = 1 // only has always '1' logic. +) +( +input wr_clk, +input rst, +input wr_en, +input [DSIZE-1:0] wr_data, +input rd_en, +input rd_clk, +output [DSIZE-1:0] rd_data, +output reg full, +output reg empty, +output reg almost_full +); + +// memory array +reg [DSIZE-1:0] mem [0:FIFO_DEPTH-1]; + +//Read Capture Logic +// if Sync = 1, then no need to remove metastability logic because wrclk = rdclk +reg [ASIZE:0] rd_gray_nxt; +reg [ASIZE:0] rd_gray; +reg [ASIZE:0] rd_capture_ptr; +reg [ASIZE:0] pre_rd_capture_gray_ptr; +reg [ASIZE:0] rd_capture_gray_ptr; +reg [ASIZE:0] wr_gray; +reg [ASIZE:0] wr_gray_nxt; + +reg [ASIZE:0] wr_capture_ptr; +reg [ASIZE:0] pre_wr_capture_gray_ptr; +reg [ASIZE:0] wr_capture_gray_ptr; +wire [ASIZE:0] buf_avail; +wire [ASIZE:0] buf_filled; +wire [ASIZE-1:0] wr_addr, rd_addr; + +reg [ASIZE:0] wr_ptr, rd_ptr; +integer i,j,k; + + +// for design that use the same clock for both read and write +generate +if (SYNC == 1) begin: RDSYNC + always @ (rd_ptr) + rd_capture_ptr = rd_ptr; +end +endgenerate + + + +//capture the wr_gray_pointers to rd_clk domains and convert the gray pointers to binary pointers +// before do comparison. + + + +// if Sync = 1, then no need to remove metastability logic because wrclk = rdclk +generate +if (SYNC == 1) begin: WRSYNC +always @ (wr_ptr) + wr_capture_ptr = wr_ptr; +end +endgenerate + +// dualport ram +// Memory (RAM) that holds the contents of the FIFO + + +assign wr_addr = wr_ptr; +assign rd_data = mem[rd_addr]; +always @(posedge wr_clk) +begin +if (wr_en && !full) + mem[wr_addr] <= #TCQ wr_data; + +end + + +// Read Side Logic + + +assign rd_addr = rd_ptr[ASIZE-1:0]; +assign rd_strobe = rd_en && !empty; + +integer n; +reg [ASIZE:0] rd_ptr_tmp; + // change the binary pointer to gray pointer +always @ (rd_ptr) +begin +// rd_gray_nxt[ASIZE] = rd_ptr_tmp[ASIZE]; +// for (n=0; n < ASIZE; n=n+1) +// rd_gray_nxt[n] = rd_ptr_tmp[n] ^ rd_ptr_tmp[n+1]; + + rd_gray_nxt[ASIZE] = rd_ptr[ASIZE]; + for (n=0; n < ASIZE; n=n+1) + rd_gray_nxt[n] = rd_ptr[n] ^ rd_ptr[n+1]; + + + +end + + +always @(posedge rd_clk) +begin +if (rst) + begin + rd_ptr <= #TCQ 'b0; + rd_gray <= #TCQ 'b0; + end +else begin + if (rd_strobe) + rd_ptr <= #TCQ rd_ptr + 1; + + rd_ptr_tmp <= #TCQ rd_ptr; + + // change the binary pointer to gray pointer + rd_gray <= #TCQ rd_gray_nxt; +end + +end + +//generate empty signal +assign buf_filled = wr_capture_ptr - rd_ptr; + +always @ (posedge rd_clk ) +begin + if (rst) + empty <= #TCQ 1'b1; + else if ((buf_filled == 0) || (buf_filled == 1 && rd_strobe)) + empty <= #TCQ 1'b1; + else + empty <= #TCQ 1'b0; +end + + +// write side logic; + +reg [ASIZE:0] wbin; +wire [ASIZE:0] wgraynext, wbinnext; + + + +always @(posedge rd_clk) +begin +if (rst) + begin + wr_ptr <= #TCQ 'b0; + wr_gray <= #TCQ 'b0; + end +else begin + if (wr_en) + wr_ptr <= #TCQ wr_ptr + 1; + + // change the binary pointer to gray pointer + wr_gray <= #TCQ wr_gray_nxt; +end + +end + + +// change the write pointer to gray pointer +always @ (wr_ptr) +begin + wr_gray_nxt[ASIZE] = wr_ptr[ASIZE]; + for (n=0; n < ASIZE; n=n+1) + wr_gray_nxt[n] = wr_ptr[n] ^ wr_ptr[n+1]; +end +// calculate how many buf still available +assign buf_avail = (rd_capture_ptr + FIFO_DEPTH) - wr_ptr; + +always @ (posedge wr_clk ) +begin + if (rst) + full <= #TCQ 1'b0; + else if ((buf_avail == 0) || (buf_avail == 1 && wr_en)) + full <= #TCQ 1'b1; + else + full <= #TCQ 1'b0; +end + + +always @ (posedge wr_clk ) +begin + if (rst) + almost_full <= #TCQ 1'b0; + else if ((buf_avail == FIFO_DEPTH - 2 ) || ((buf_avail == FIFO_DEPTH -3) && wr_en)) + almost_full <= #TCQ 1'b1; + else + almost_full <= #TCQ 1'b0; +end + +endmodule + + diff --git "a/Frogwells_fpga_design/\345\237\272\344\272\216FPGA\343\200\201DDR3\345\222\214USB2.0\347\232\204\345\233\276\345\203\217\351\207\207\351\233\206\347\263\273\347\273\237/debug/ddr_test/rtl/traffic_gen/cmd_gen.v" "b/Frogwells_fpga_design/\345\237\272\344\272\216FPGA\343\200\201DDR3\345\222\214USB2.0\347\232\204\345\233\276\345\203\217\351\207\207\351\233\206\347\263\273\347\273\237/debug/ddr_test/rtl/traffic_gen/cmd_gen.v" new file mode 100644 index 0000000000000000000000000000000000000000..fe7753a69e77248e505540c6c2b06fc4abf19242 --- /dev/null +++ "b/Frogwells_fpga_design/\345\237\272\344\272\216FPGA\343\200\201DDR3\345\222\214USB2.0\347\232\204\345\233\276\345\203\217\351\207\207\351\233\206\347\263\273\347\273\237/debug/ddr_test/rtl/traffic_gen/cmd_gen.v" @@ -0,0 +1,941 @@ +//***************************************************************************** +// (c) Copyright 2008-2009 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: %version +// \ \ Application: MIG +// / / Filename: cmd_gen.v +// /___/ /\ Date Last Modified: $Date: 2011/05/27 15:50:26 $ +// \ \ / \ Date Created: Oct 21 2008 +// \___\/\___\ +// +//Device: Spartan6 +//Design Name: DDR/DDR2/DDR3/LPDDR +//Purpose: This module genreates different type of commands, address, +// burst_length to mcb_flow_control module. +//Reference: +//Revision History: +// Nov14 2008. Added constraints for generating PRBS_BL when +// generated address is too close to end of address space. +// The BL will be force to 1 to avoid across other port's space. +// April 2 2009 Fixed Sequential Address Circuit to avoide generate any address +// beyond the allowed address range. +// Oct 22 2009 Fixed BRAM interface. +// Fixed run_traffic stop and go problem. +// Merged V6 and SP6 specific requirements. +// Modified syntax for VHDL Formality comparison. +//***************************************************************************** + +`timescale 1ps/1ps + +`define RD 3'b001; +`define RDP 3'b011; +`define WR 3'b000; +`define WRP 3'b010; +`define REFRESH 3'b100; + + +module cmd_gen # + ( + parameter TCQ = 100, + + parameter FAMILY = "SPARTAN6", + parameter MEM_BURST_LEN = 8, + parameter PORT_MODE = "BI_MODE", + parameter NUM_DQ_PINS = 8, + parameter DATA_PATTERN = "DGEN_ALL", // "DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL" + parameter CMD_PATTERN = "CGEN_ALL", // "CGEN_RPBS","CGEN_FIXED", "CGEN_BRAM", "CGEN_SEQUENTIAL", "CGEN_ALL", + parameter ADDR_WIDTH = 30, + parameter DWIDTH = 32, + parameter PIPE_STAGES = 0, + parameter MEM_COL_WIDTH = 10, // memory column width + parameter PRBS_EADDR_MASK_POS = 32'hFFFFD000, + parameter PRBS_SADDR_MASK_POS = 32'h00002000, + parameter PRBS_EADDR = 32'h00002000, + parameter PRBS_SADDR = 32'h00002000 + ) + ( + input clk_i, + input [9:0] rst_i, + input run_traffic_i, + // runtime parameter + input [6:0] rd_buff_avail_i, + input force_wrcmd_gen_i, + input [31:0] start_addr_i, // define the start of address + input [31:0] end_addr_i, + input [31:0] cmd_seed_i, // same seed apply to all addr_prbs_gen, bl_prbs_gen, instr_prbs_gen + input [31:0] data_seed_i, + input load_seed_i, // + // upper layer inputs to determine the command bus and data pattern + // internal traffic generator initialize the memory with + input [2:0] addr_mode_i, // "00" = bram; takes the address from bram output + // "01" = fixed address from the fixed_addr input + // "10" = psuedo ramdom pattern; generated from internal 64 bit LFSR + // "11" = sequential + + input [3:0] data_mode_i, // 4'b0010:address as data + // 4'b0011:DGEN_HAMMER + // 4'b0100:DGEN_NEIGHBOUR + // 4'b0101:DGEN_WALKING1 + // 4'b0110:DGEN_WALKING0 + // 4'b0111:PRBS_DATA + + // for each instr_mode, traffic gen fill up with a predetermined pattern before starting the instr_pattern that defined + // in the instr_mode input. The runtime mode will be automatically loaded inside when it is in + input [3:0] instr_mode_i, // "0000" = bram; takes instruction from bram output + // "0001" = fixed instr from fixed instr input + // "0010" = R/W + // "0011" = RP/WP + // "0100" = R/RP/W/WP + // "0101" = R/RP/W/WP/REF + // "0110" = PRBS + + + input [1:0] bl_mode_i, // "00" = bram; takes the burst length from bram output + // "01" = fixed , takes the burst length from the fixed_bl input + // "10" = psuedo ramdom pattern; generated from internal 16 bit LFSR + + input mode_load_i, + + // fixed pattern inputs interface + input [5:0] fixed_bl_i, // range from 1 to 64 + input [2:0] fixed_instr_i, //RD 3'b001 + //RDP 3'b011 + //WR 3'b000 + //WRP 3'b010 + //REFRESH 3'b100 + input [31:0] fixed_addr_i, // only upper 30 bits will be used + // BRAM FIFO input + input [31:0] bram_addr_i, // + input [2:0] bram_instr_i, + input [5:0] bram_bl_i, + input bram_valid_i, + output bram_rdy_o, + + input reading_rd_data_i, + // mcb_flow_control interface + input rdy_i, + + output [31:0] addr_o, // generated address + output [2:0] instr_o, // generated instruction + output [5:0] bl_o, // generated instruction +// output reg [31:0] m_addr_o, + output cmd_o_vld // valid commands when asserted + ); + + localparam PRBS_ADDR_WIDTH = 32; + localparam INSTR_PRBS_WIDTH = 16; + localparam BL_PRBS_WIDTH = 16; + +localparam BRAM_DATAL_MODE = 4'b0000; +localparam FIXED_DATA_MODE = 4'b0001; +localparam ADDR_DATA_MODE = 4'b0010; +localparam HAMMER_DATA_MODE = 4'b0011; +localparam NEIGHBOR_DATA_MODE = 4'b0100; +localparam WALKING1_DATA_MODE = 4'b0101; +localparam WALKING0_DATA_MODE = 4'b0110; +localparam PRBS_DATA_MODE = 4'b0111; + +reg [10:0] INC_COUNTS; +reg [2:0] addr_mode_reg; +reg [1:0] bl_mode_reg; + +reg [31:0] addr_counts; +reg [31:0] addr_counts_next_r; + +wire [14:0] prbs_bl; +reg [2:0] instr_out; +wire [14:0] prbs_instr_a; +wire [14:0] prbs_instr_b; + +reg [5:0] prbs_brlen; + +wire [31:0] prbs_addr; +wire [31:0] seq_addr; +wire [31:0] fixed_addr; +reg [31:0] addr_out ; +reg [5:0] bl_out; +reg [5:0] bl_out_reg; +reg mode_load_d1; +reg mode_load_d2; +reg mode_load_pulse; +wire [41:0] pipe_data_o; +wire cmd_clk_en; + +wire pipe_out_vld; +reg [15:0] end_addr_range; + +reg force_bl1; +reg A0_G_E0; +reg A1_G_E1; +reg A2_G_E2; +reg A3_G_E3; +reg AC3_G_E3; +reg AC2_G_E2; +reg AC1_G_E1; +reg bl_out_clk_en; +reg [41:0] pipe_data_in; +reg instr_vld; +reg bl_out_vld; +reg pipe_data_in_vld; +reg gen_addr_larger ; + reg [6:0] buf_avail_r; + reg [6:0] rd_data_received_counts; + reg [6:0] rd_data_counts_asked; + + reg [15:0] rd_data_received_counts_total; +reg instr_vld_dly1; +reg first_load_pulse; +reg mem_init_done; +reg refresh_cmd_en ; +reg [9:0] refresh_timer; +reg refresh_prbs; +reg cmd_vld; +reg run_traffic_r; +reg run_traffic_pulse; +always @ (posedge clk_i) +begin + run_traffic_r <= #TCQ run_traffic_i; + if ( run_traffic_i && ~run_traffic_r ) + run_traffic_pulse <= #TCQ 1'b1; + else + run_traffic_pulse <= #TCQ 1'b0; +end + + +// commands go through pipeline inserters +assign addr_o = pipe_data_o[31:0]; +assign instr_o = pipe_data_o[34:32]; +assign bl_o = pipe_data_o[40:35]; + + +assign cmd_o_vld = pipe_data_o[41] & run_traffic_r; +assign pipe_out_vld = pipe_data_o[41] & run_traffic_r; + + +assign pipe_data_o = pipe_data_in; + +always @(posedge clk_i) begin + + instr_vld <= #TCQ (cmd_clk_en | (mode_load_pulse & first_load_pulse)); + bl_out_clk_en <= #TCQ (cmd_clk_en | (mode_load_pulse & first_load_pulse)); + bl_out_vld <= #TCQ bl_out_clk_en; + pipe_data_in_vld <= #TCQ instr_vld; + end + +always @ (posedge clk_i) begin + if (rst_i[0]) + first_load_pulse <= #TCQ 1'b1; + else if (mode_load_pulse) + first_load_pulse <= #TCQ 1'b0; + else + first_load_pulse <= #TCQ first_load_pulse; + end + +generate +if (CMD_PATTERN == "CGEN_BRAM") begin: cv1 + +always @(posedge clk_i) begin + cmd_vld <= #TCQ (cmd_clk_en ); + +end +end endgenerate + + +generate +if (CMD_PATTERN != "CGEN_BRAM") begin: cv2 + +always @(posedge clk_i) begin + cmd_vld <= #TCQ (cmd_clk_en | (mode_load_pulse & first_load_pulse )); + +end +end endgenerate + + +assign cmd_clk_en = ( rdy_i & pipe_out_vld & run_traffic_i || mode_load_pulse && (CMD_PATTERN == "CGEN_BRAM")); + + + +integer i; +generate +if (FAMILY == "SPARTAN6") begin: pipe_in_s6 + always @ (posedge clk_i) begin + if (rst_i[0]) + pipe_data_in[31:0] <= #TCQ start_addr_i; + else if (instr_vld) + if (gen_addr_larger && (addr_mode_reg == 3'b100 || addr_mode_reg == 3'b010)) + if (DWIDTH == 32) + pipe_data_in[31:0] <= #TCQ {end_addr_i[31:8],8'h0}; + else if (DWIDTH == 64) + pipe_data_in[31:0] <= #TCQ {end_addr_i[31:9],9'h0}; + else + pipe_data_in[31:0] <= #TCQ {end_addr_i[31:10],10'h0}; + + else begin + if (DWIDTH == 32) + pipe_data_in[31:0] <= #TCQ {addr_out[31:2],2'b00} ; + else if (DWIDTH == 64) + pipe_data_in[31:0] <= #TCQ {addr_out[31:3],3'b000} ; + else if (DWIDTH == 128) + pipe_data_in[31:0] <= #TCQ {addr_out[31:4],4'b0000} ; + end +end + +end endgenerate + +generate +if (FAMILY == "VIRTEX6") begin: pipe_in_v6 + always @ (posedge clk_i) begin + if (rst_i[1]) + pipe_data_in[31:0] <= #TCQ start_addr_i; + else if (instr_vld) + // address + if (gen_addr_larger && (addr_mode_reg == 3'b100 || addr_mode_reg == 3'b010)) //(AC3_G_E3 && AC2_G_E2 && AC1_G_E1 ) + pipe_data_in[31:0] <= #TCQ {end_addr_i[31:8],8'h0}; + else if ((NUM_DQ_PINS >= 128) && (NUM_DQ_PINS <= 144)) + begin + if (MEM_BURST_LEN == 8) + pipe_data_in[31:0] <= #TCQ {addr_out[31:7], 7'b0000000}; + else + pipe_data_in[31:0] <= #TCQ {addr_out[31:6], 6'b000000}; + end + + else if ((NUM_DQ_PINS >= 64) && (NUM_DQ_PINS < 128)) + begin + + if (MEM_BURST_LEN == 8) + pipe_data_in[31:0] <= #TCQ {addr_out[31:6], 6'b000000}; + else + pipe_data_in[31:0] <= #TCQ {addr_out[31:5], 5'b00000}; + end + + else if ((NUM_DQ_PINS == 32) || (NUM_DQ_PINS == 40) || (NUM_DQ_PINS == 48) || (NUM_DQ_PINS == 56)) + begin + + if (MEM_BURST_LEN == 8) + pipe_data_in[31:0] <= #TCQ {addr_out[31:5], 5'b00000}; + else + pipe_data_in[31:0] <= #TCQ {addr_out[31:4], 4'b0000}; + end + + else if ((NUM_DQ_PINS == 16) || (NUM_DQ_PINS == 24)) + if (MEM_BURST_LEN == 8) + pipe_data_in[31:0] <= #TCQ {addr_out[31:4], 4'b0000}; + else + pipe_data_in[31:0] <= #TCQ {addr_out[31:3], 3'b000}; + + else if ((NUM_DQ_PINS == 8) ) + if (MEM_BURST_LEN == 8) + pipe_data_in[31:0] <= #TCQ {addr_out[31:3], 3'b000}; + else + pipe_data_in[31:0] <= #TCQ {addr_out[31:2], 2'b00}; + +end + +end endgenerate + + +//generate +//if (FAMILY == "VIRTEX6") begin: pipe_m_addr_o +// always @ (posedge clk_i) begin +// if (rst_i[1]) +// m_addr_o[31:0] <= #TCQ start_addr_i; +// else if (instr_vld) +// if (gen_addr_larger && (addr_mode_reg == 3'b100 || addr_mode_reg == 3'b010)) //(AC3_G_E3 && AC2_G_E2 && AC1_G_E1 ) +// m_addr_o[31:0] <= #TCQ {end_addr_i[31:8],8'h0}; +// else if ((NUM_DQ_PINS >= 128 && NUM_DQ_PINS < 256)) +// m_addr_o <= #TCQ {addr_out[31:6], 6'b00000} ; +// +// else if ((NUM_DQ_PINS >= 64 && NUM_DQ_PINS < 128)) +// m_addr_o <= #TCQ {addr_out[31:5], 5'b00000} ; +// +// else if ((NUM_DQ_PINS == 32) || (NUM_DQ_PINS == 40) || (NUM_DQ_PINS == 48) || (NUM_DQ_PINS == 56)) +// m_addr_o[31:0] <= #TCQ {addr_out[31:4], 4'b0000}; +// else if ((NUM_DQ_PINS == 16) || (NUM_DQ_PINS == 24)) +// m_addr_o[31:0] <= #TCQ {addr_out[31:3], 3'b000}; +// else if ((NUM_DQ_PINS == 8) ) +// m_addr_o[31:0] <= #TCQ {addr_out[31:2], 2'b00}; +//end +// +//end endgenerate +reg force_wrcmd_gen; + always @ (posedge clk_i) begin + if (rst_i[0]) + force_wrcmd_gen <= #TCQ 1'b0; + else if (buf_avail_r == 63) + force_wrcmd_gen <= #TCQ 1'b0; + else if (instr_vld_dly1 && pipe_data_in[32]== 1 && pipe_data_in[41:35] > 16) + force_wrcmd_gen <= #TCQ 1'b1; + end + +reg [3:0]instr_mode_reg; + always @ (posedge clk_i) + begin + instr_mode_reg <= #TCQ instr_mode_i; + end +reg force_smallvalue; + always @ (posedge clk_i) + begin + if (rst_i[2]) begin + pipe_data_in[40:32] <= #TCQ 'b0; + force_smallvalue <= #TCQ 1'b0; + end + else if (instr_vld) begin + if (instr_mode_reg == 0) begin + pipe_data_in[34:32] <= #TCQ instr_out; + end + else if (instr_out[2]) begin + pipe_data_in[34:32] <= #TCQ 3'b100; + end + // + else if ( FAMILY == "SPARTAN6" && PORT_MODE == "RD_MODE") + begin + pipe_data_in[34:32] <= #TCQ {instr_out[2:1],1'b1}; + end + + else if ((force_wrcmd_gen || buf_avail_r <= 15) && FAMILY == "SPARTAN6" && PORT_MODE != "RD_MODE") + begin + pipe_data_in[34:32] <= #TCQ {instr_out[2],2'b00}; + end + else begin + pipe_data_in[34:32] <= #TCQ instr_out; + end + + //********* condition the generated bl value except if TG is programmed for BRAM interface' + // if the generated address is close to end address range, the bl_out will be altered to 1. + if (bl_mode_i[1:0] == 2'b00) // if programmed BRAM interface + pipe_data_in[40:35] <= #TCQ bl_out; + else if (FAMILY == "VIRTEX6") + pipe_data_in[40:35] <= #TCQ bl_out; + else if (force_bl1 && (bl_mode_reg == 2'b10 ) && FAMILY == "SPARTAN6") //PRBS_BL + + pipe_data_in[40:35] <= #TCQ 6'b000001; + else if ((buf_avail_r[5:0] >= 6'b111100 && buf_avail_r[6] == 1'b0) && pipe_data_in[32] == 1'b1 && FAMILY == "SPARTAN6") //read instructon + + + begin + if (bl_mode_reg == 2'b10) + force_smallvalue <= #TCQ ~force_smallvalue; + + if ((buf_avail_r[6] && bl_mode_reg == 2'b10)) + + + pipe_data_in[40:35] <= #TCQ {2'b0,bl_out[3:1],1'b1}; + else + pipe_data_in[40:35] <= #TCQ bl_out; + end + else if (buf_avail_r < 64 && rd_buff_avail_i >= 0 && instr_out[0] == 1'b1 && (bl_mode_reg == 2'b10 )) + if (FAMILY == "SPARTAN6") + pipe_data_in[40:35] <= #TCQ {2'b0,bl_out[3:0] + 1}; + else + pipe_data_in[40:35] <= #TCQ bl_out; + + end //else instr_vld + end // always + +always @ (posedge clk_i) +begin + if (rst_i[2]) + pipe_data_in[41] <= #TCQ 'b0; + else if (cmd_vld) + pipe_data_in[41] <= #TCQ instr_vld;//instr_vld; + else if (rdy_i && pipe_out_vld) + pipe_data_in[41] <= #TCQ 1'b0; + end + + always @ (posedge clk_i) + instr_vld_dly1 <= #TCQ instr_vld; + +always @ (posedge clk_i) begin + if (rst_i[0]) begin + rd_data_counts_asked <= #TCQ 'b0; + end else if (instr_vld_dly1 && pipe_data_in[32]== 1) begin + if (pipe_data_in[40:35] == 0) + rd_data_counts_asked <= #TCQ rd_data_counts_asked + (64) ; + else + rd_data_counts_asked <= #TCQ rd_data_counts_asked + (pipe_data_in[40:35]) ; + + end + end + +always @ (posedge clk_i) begin + if (rst_i[0]) begin + rd_data_received_counts <= #TCQ 'b0; + rd_data_received_counts_total <= #TCQ 'b0; + end else if(reading_rd_data_i) begin + rd_data_received_counts <= #TCQ rd_data_received_counts + 1; + rd_data_received_counts_total <= #TCQ rd_data_received_counts_total + 1; + end + end + + // calculate how many buf still available + always @ (posedge clk_i) + buf_avail_r <= #TCQ (rd_data_received_counts + 64) - rd_data_counts_asked; + +localparam BRAM_ADDR = 2'b00; +localparam FIXED_ADDR = 2'b01; +localparam PRBS_ADDR = 2'b10; +localparam SEQUENTIAL_ADDR = 2'b11; + +// registered the mode settings +always @ (posedge clk_i) begin + if (rst_i[3]) + if (CMD_PATTERN == "CGEN_BRAM") + addr_mode_reg <= #TCQ 3'b000; + else + addr_mode_reg <= #TCQ 3'b011; + else if (mode_load_pulse) + addr_mode_reg <= #TCQ addr_mode_i; +end + +always @ (posedge clk_i) begin + if (mode_load_pulse) begin + bl_mode_reg <= #TCQ bl_mode_i ; + end + mode_load_d1 <= #TCQ mode_load_i; + mode_load_d2 <= #TCQ mode_load_d1; +end + +always @ (posedge clk_i) + mode_load_pulse <= #TCQ mode_load_d1 & ~mode_load_d2; + +// MUX the addr pattern out depending on the addr_mode setting + +// "000" = bram; takes the address from bram output +// "001" = fixed address from the fixed_addr input +// "010" = psuedo ramdom pattern; generated from internal 64 bit LFSR +// "011" = sequential +// "100" = mode that used for prbs addr , prbs bl and prbs data +//always @(addr_mode_reg,prbs_addr,seq_addr,fixed_addr,bram_addr_i,data_mode_i) +always @ (posedge clk_i) begin +if (rst_i[3]) + addr_out <= #TCQ start_addr_i; +else + case({addr_mode_reg}) + 3'b000: addr_out <= #TCQ bram_addr_i; + 3'b001: addr_out <= #TCQ fixed_addr; + 3'b010: addr_out <= #TCQ prbs_addr; + 3'b011: addr_out <= #TCQ {2'b0,seq_addr[29:0]}; + 3'b100: addr_out <= #TCQ {2'b00,seq_addr[6:2],seq_addr[23:0]};//{prbs_addr[31:6],6'b000000} ; + 3'b101: addr_out <= #TCQ {prbs_addr[31:20],seq_addr[19:0]} ; + + default : addr_out <= #TCQ 'b0; + endcase +end + +// ADDR PRBS GENERATION +generate +if (CMD_PATTERN == "CGEN_PRBS" || CMD_PATTERN == "CGEN_ALL" ) begin: gen_prbs_addr +cmd_prbs_gen # + ( + .TCQ (TCQ), + .FAMILY (FAMILY), + .ADDR_WIDTH (32), + .DWIDTH (DWIDTH), + .PRBS_WIDTH (32), + .SEED_WIDTH (32), + .PRBS_EADDR_MASK_POS (PRBS_EADDR_MASK_POS ), + .PRBS_SADDR_MASK_POS (PRBS_SADDR_MASK_POS ), + .PRBS_EADDR (PRBS_EADDR), + .PRBS_SADDR (PRBS_SADDR ) + ) + addr_prbs_gen + ( + .clk_i (clk_i), + .clk_en (cmd_clk_en), + .prbs_seed_init (mode_load_pulse), + .prbs_seed_i (cmd_seed_i[31:0]), + .prbs_o (prbs_addr) + ); +end +endgenerate + +always @ (posedge clk_i) begin +if (addr_out[31:8] >= end_addr_i[31:8]) + gen_addr_larger <= 1'b1; +else + gen_addr_larger <= 1'b0; +end + +generate +if (FAMILY == "SPARTAN6" ) begin : INC_COUNTS_S +always @ (posedge clk_i) +if (mem_init_done) + INC_COUNTS <= #TCQ (DWIDTH/8)*(bl_out_reg); +else begin + if (fixed_bl_i == 0) + INC_COUNTS <= #TCQ (DWIDTH/8)*(64); + else + INC_COUNTS <= #TCQ (DWIDTH/8)*(fixed_bl_i); + end +end +endgenerate +//converting string to integer +//localparam MEM_BURST_INT = (MEM_BURST_LEN == "8")? 8 : 4; +localparam MEM_BURST_INT = MEM_BURST_LEN ; + + +generate +if (FAMILY == "VIRTEX6" ) begin : INC_COUNTS_V + always @ (posedge clk_i) begin + +if ( (NUM_DQ_PINS >= 128 && NUM_DQ_PINS <= 144)) //256 + INC_COUNTS <= #TCQ 64 * (MEM_BURST_INT/4); + +else if ( (NUM_DQ_PINS >= 64 && NUM_DQ_PINS < 128)) //256 + INC_COUNTS <= #TCQ 32 * (MEM_BURST_INT/4); +else if ((NUM_DQ_PINS >= 32) && (NUM_DQ_PINS < 64)) //128 + INC_COUNTS <= #TCQ 16 * (MEM_BURST_INT/4) ; +else if ((NUM_DQ_PINS == 16) || (NUM_DQ_PINS == 24)) //64 + INC_COUNTS <= #TCQ 8 * (MEM_BURST_INT/4); +else if ((NUM_DQ_PINS == 8) ) + INC_COUNTS <= #TCQ 4 * (MEM_BURST_INT/4); +end +end +endgenerate + +generate +// Sequential Address pattern +// It is generated when rdy_i is valid and write command is valid and bl_cmd is valid. +reg [31:0] end_addr_r; + +always @ (posedge clk_i) begin + end_addr_r <= #TCQ end_addr_i - DWIDTH/8*fixed_bl_i +1; +end + +always @ (posedge clk_i) begin +if (addr_out[31:24] >= end_addr_r[31:24]) + AC3_G_E3 <= #TCQ 1'b1; +else + AC3_G_E3 <= #TCQ 1'b0; + +if (addr_out[23:16] >= end_addr_r[23:16]) + AC2_G_E2 <= #TCQ 1'b1; +else + AC2_G_E2 <= #TCQ 1'b0; + +if (addr_out[15:8] >= end_addr_r[15:8]) + AC1_G_E1 <= #TCQ 1'b1; +else + AC1_G_E1 <= #TCQ 1'b0; +end + +//if (CMD_PATTERN == "CGEN_SEQUENTIAL" || CMD_PATTERN == "CGEN_ALL" ) begin : seq_addr_gen + assign seq_addr = addr_counts; + +reg mode_load_pulse_r1; + +always @ (posedge clk_i) +begin + mode_load_pulse_r1 <= #TCQ mode_load_pulse; + +end + +always @ (posedge clk_i) + end_addr_range <= #TCQ end_addr_i[15:0] - (DWIDTH/8 *bl_out_reg) + 1 ; + +always @ (posedge clk_i) + addr_counts_next_r <= #TCQ addr_counts + INC_COUNTS ; + +reg cmd_clk_en_r; +always @ (posedge clk_i) + cmd_clk_en_r <= #TCQ cmd_clk_en; +always @ (posedge clk_i) begin + if (rst_i[4]) begin + addr_counts <= #TCQ start_addr_i; + mem_init_done <= #TCQ 1'b0; + end else if (cmd_clk_en_r || mode_load_pulse_r1) + if(addr_counts_next_r>= end_addr_i) begin + addr_counts <= #TCQ start_addr_i; + mem_init_done <= #TCQ 1'b1; + end else if(addr_counts < end_addr_r) // address counts get incremented by burst_length and port size each wr command generated + addr_counts <= #TCQ addr_counts + INC_COUNTS; +end + + // end begin +//end +endgenerate + +generate +// Fixed Address pattern +if (CMD_PATTERN == "CGEN_FIXED" || CMD_PATTERN == "CGEN_ALL" ) begin : fixed_addr_gen + assign fixed_addr = (DWIDTH == 32)? {fixed_addr_i[31:2],2'b0} : + (DWIDTH == 64)? {fixed_addr_i[31:3],3'b0}: + (DWIDTH <= 128)? {fixed_addr_i[31:4],4'b0}: + (DWIDTH <= 256)? {fixed_addr_i[31:5],5'b0}: + {fixed_addr_i[31:6],6'b0}; + end +endgenerate + +generate +// BRAM Address pattern +if (CMD_PATTERN == "CGEN_BRAM" || CMD_PATTERN == "CGEN_ALL" ) begin : bram_addr_gen +assign bram_rdy_o = run_traffic_i & cmd_clk_en & bram_valid_i | mode_load_pulse; +end +endgenerate + +/////////////////////////////////////////////////////////////////////////// +// INSTR COMMAND GENERATION + +// tap points are 3,2 +//`define RD 3'b001 +//`define RDP 3'b011 +//`define WR 3'b000 +//`define WRP 3'b010 +//`define REFRESH 3'b100 +// use 14 stages 1 sr16; tap position 1,3,5,14 + +reg [9:0]force_rd_counts; +reg force_rd; +always @ (posedge clk_i) begin +if (rst_i[4]) + force_rd_counts <= #TCQ 'b0; +else if (instr_vld) begin + force_rd_counts <= #TCQ force_rd_counts + 1; + end +end + +always @ (posedge clk_i) begin +if (rst_i[4]) + force_rd <= #TCQ 1'b0; +else if (force_rd_counts[3]) + force_rd <= #TCQ 1'b1; +else + force_rd <= #TCQ 1'b0; +end + + +// adding refresh timer to limit the amount of issuing refresh command. +always @ (posedge clk_i) begin +if (rst_i[4]) + refresh_timer <= #TCQ 'b0; +else + refresh_timer <= #TCQ refresh_timer + 1'b1; + +end + +always @ (posedge clk_i) begin +if (rst_i[4]) + refresh_cmd_en <= #TCQ 'b0; +//else if (refresh_timer >= 12'hff0 && refresh_timer <= 12'hfff) +else if (refresh_timer == 10'h3ff) + + refresh_cmd_en <= #TCQ 'b1; +else if (cmd_clk_en && refresh_cmd_en) + refresh_cmd_en <= #TCQ 'b0; + +end + +always @ (posedge clk_i) begin +if (FAMILY == "SPARTAN6") + refresh_prbs <= #TCQ prbs_instr_b[3] & refresh_cmd_en; +else + refresh_prbs <= #TCQ 1'b0; +end + //synthesis translate_off +always @ (instr_mode_i) + if(instr_mode_i >2 && FAMILY == "VIRTEX6") begin + $display("Error ! Not valid instruction mode"); + $stop; + end + //synthesis translate_on + +always @ (posedge clk_i) begin + case(instr_mode_i) + 0: instr_out <= #TCQ bram_instr_i; + 1: instr_out <= #TCQ fixed_instr_i; + 2: instr_out <= #TCQ {2'b00,(prbs_instr_a[0] | force_rd)}; + 3: instr_out <= #TCQ {2'b0,prbs_instr_a[0]}; //: WP/RP + 4: instr_out <= #TCQ {1'b0,prbs_instr_b[0], prbs_instr_a[0]}; // W/WP/R/RP. + // may be add another PRBS for generating REFRESH +// 5: instr_out <= #TCQ {prbs_instr_b[3],prbs_instr_b[0], prbs_instr_a[0]}; // W/WP/R/RP/REFRESH W/WP/R/RP/REFRESH + 5: instr_out <= #TCQ {refresh_prbs ,prbs_instr_b[0], prbs_instr_a[0]}; // W/WP/R/RP/REFRESH W/WP/R/RP/REFRESH + + + default : instr_out <= #TCQ {2'b00,prbs_instr_a[0]}; + endcase +end + +generate // PRBS INSTRUCTION generation +// use two PRBS generators and tap off 1 bit from each to create more randomness for +// generating actual read/write commands +if (CMD_PATTERN == "CGEN_PRBS" || CMD_PATTERN == "CGEN_ALL" ) begin: gen_prbs_instr +cmd_prbs_gen # + ( + .TCQ (TCQ), + .PRBS_CMD ("INSTR"), + .ADDR_WIDTH (32), + .SEED_WIDTH (15), + .PRBS_WIDTH (20) + ) + instr_prbs_gen_a + ( + .clk_i (clk_i), + .clk_en (cmd_clk_en), + .prbs_seed_init (load_seed_i), + .prbs_seed_i (cmd_seed_i[14:0]), + .prbs_o (prbs_instr_a) + ); + +cmd_prbs_gen # + ( + .PRBS_CMD ("INSTR"), + .SEED_WIDTH (15), + .PRBS_WIDTH (20) + ) + instr_prbs_gen_b + ( + .clk_i (clk_i), + .clk_en (cmd_clk_en), + .prbs_seed_init (load_seed_i), + .prbs_seed_i (cmd_seed_i[16:2]), + .prbs_o (prbs_instr_b) + ); +end +endgenerate + +/////////////////////////////////////////////////////////////////////////////////////////////////////////////// +// BURST LENGTH GENERATION +// burst length code = user burst length input - 1 +// mcb_flow_control does the minus before sending out to mcb\ +// when filling up the memory, need to make sure bl doesn't go beyound its upper limit boundary +//assign force_bl1 = (addr_out[31:0] >= (end_addr_i[31:0] - 4*64)) ? 1'b1: 1'b0; +// for neighbour pattern, need to limit the bl to make sure it is within column size boundary. + +// check bl validity + +always @ (posedge clk_i) begin +if (addr_out[31:24] >= end_addr_i[31:24]) + A3_G_E3 <= #TCQ 1'b1; +else + A3_G_E3 <= #TCQ 1'b0; + +if (addr_out[23:16] >= end_addr_i[23:16]) + A2_G_E2 <= #TCQ 1'b1; +else + A2_G_E2 <= #TCQ 1'b0; + +if (addr_out[15:8] >= end_addr_i[15:8]) + A1_G_E1 <= #TCQ 1'b1; +else + A1_G_E1 <= #TCQ 1'b0; + +if (addr_out[7:0] > end_addr_i[7:0] - DWIDTH/8* bl_out + 1) + A0_G_E0 <= #TCQ 1'b1; +else + A0_G_E0 <= #TCQ 1'b0; +end + +always @(addr_out,bl_out,end_addr_i,rst_i,buf_avail_r) begin + if (rst_i[5]) + force_bl1 = 1'b0; + else if (((addr_out + bl_out* (DWIDTH/8)) >= end_addr_i) || (buf_avail_r <= 50 && PORT_MODE == "RD_MODE")) + force_bl1 = 1'b1; + else + force_bl1 = 1'b0; +end + +always @(posedge clk_i) begin + if (rst_i[6]) + bl_out_reg <= #TCQ fixed_bl_i; + else if (bl_out_vld) + bl_out_reg <= #TCQ bl_out; +end + +always @ (posedge clk_i) begin + if (mode_load_pulse) + bl_out <= #TCQ fixed_bl_i ; + else if (cmd_clk_en) begin + case({bl_mode_reg}) + 0: bl_out <= #TCQ bram_bl_i ; + 1: bl_out <= #TCQ fixed_bl_i ; + 2: bl_out <= #TCQ prbs_brlen; + default : bl_out <= #TCQ 6'h1; + endcase + end +end + + //synthesis translate_off +always @ (bl_out) + if(bl_out >2 && FAMILY == "VIRTEX6") begin + $display("Error ! Not valid burst length"); + $stop; + end + //synthesis translate_on + +generate +if (CMD_PATTERN == "CGEN_PRBS" || CMD_PATTERN == "CGEN_ALL" ) begin: gen_prbs_bl +cmd_prbs_gen # + ( + .TCQ (TCQ), + .FAMILY (FAMILY), + .PRBS_CMD ("BLEN"), + .ADDR_WIDTH (32), + .SEED_WIDTH (15), + .PRBS_WIDTH (20) + ) + bl_prbs_gen + ( + .clk_i (clk_i), + .clk_en (cmd_clk_en), + .prbs_seed_init (load_seed_i), + .prbs_seed_i (cmd_seed_i[16:2]), + .prbs_o (prbs_bl) + ); +end + +always @ (prbs_bl) +if (FAMILY == "SPARTAN6") // supports 1 throug 64 + prbs_brlen = (prbs_bl[5:0] == 6'b000000) ? 6'b000001: prbs_bl[5:0]; +else // VIRTEX6 only supports 1 or 2 burst on user ports + prbs_brlen = 6'b000010; +endgenerate + +endmodule diff --git "a/Frogwells_fpga_design/\345\237\272\344\272\216FPGA\343\200\201DDR3\345\222\214USB2.0\347\232\204\345\233\276\345\203\217\351\207\207\351\233\206\347\263\273\347\273\237/debug/ddr_test/rtl/traffic_gen/cmd_prbs_gen.v" "b/Frogwells_fpga_design/\345\237\272\344\272\216FPGA\343\200\201DDR3\345\222\214USB2.0\347\232\204\345\233\276\345\203\217\351\207\207\351\233\206\347\263\273\347\273\237/debug/ddr_test/rtl/traffic_gen/cmd_prbs_gen.v" new file mode 100644 index 0000000000000000000000000000000000000000..ed2442ef5df3f0a2a046f02d067c97c3515a8520 --- /dev/null +++ "b/Frogwells_fpga_design/\345\237\272\344\272\216FPGA\343\200\201DDR3\345\222\214USB2.0\347\232\204\345\233\276\345\203\217\351\207\207\351\233\206\347\263\273\347\273\237/debug/ddr_test/rtl/traffic_gen/cmd_prbs_gen.v" @@ -0,0 +1,251 @@ +//***************************************************************************** +// (c) Copyright 2008-2009 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: %version +// \ \ Application: MIG +// / / Filename: cmd_prbs_gen.v +// /___/ /\ Date Last Modified: +// \ \ / \ Date Created: +// \___\/\___\ +// +//Device: Spartan6 +//Design Name: DDR/DDR2/DDR3/LPDDR +//Purpose: This moduel use LFSR to generate random address, isntructions +// or burst_length. +//Reference: +//Revision History: 1.1 Added condition to zero out the LSB address bits according to +// DWIDTH and FAMILY. 7/9/2009 +// +//***************************************************************************** + +`timescale 1ps/1ps + +module cmd_prbs_gen # + ( + parameter TCQ = 100, + parameter FAMILY = "SPARTAN6", + parameter ADDR_WIDTH = 29, + parameter DWIDTH = 32, + parameter PRBS_CMD = "ADDRESS", // "INSTR", "BLEN","ADDRESS" + parameter PRBS_WIDTH = 64, // 64,15,20 + parameter SEED_WIDTH = 32, // 32,15,4 + + parameter PRBS_EADDR_MASK_POS = 32'hFFFFD000, + parameter PRBS_SADDR_MASK_POS = 32'h00002000, + parameter PRBS_EADDR = 32'h00002000, + parameter PRBS_SADDR = 32'h00002000 + ) + ( + input clk_i, + input prbs_seed_init, // when high the prbs_x_seed will be loaded + input clk_en, + input [SEED_WIDTH-1:0] prbs_seed_i, + + output[SEED_WIDTH-1:0] prbs_o // generated address + ); + +wire[ADDR_WIDTH - 1:0] ZEROS; +reg [SEED_WIDTH - 1:0] prbs; +reg [PRBS_WIDTH :1] lfsr_q; + +assign ZEROS = 'b0; +// +//************************************************************** +//#################################################################################################################### +// # +// # +// 64 taps: [64,63,61,60]: {{8'b01011000}, {56'b0}} # +// upper 32 bits are loadable # +// # +// +// +// ........................................................................................ +// ^ ^ ^ ^ | +// | ____ | ___ ___ | ___ | ___ ___ ___ | +// | | | |---|<- | | | | |---|<- | | |---|<- | |...| | | | | The first 32 bits are parallel loadable. +// ----|64 |<--|xor|<-- |63 |-->|62 |-|xor|<--|61 |<-|xor|<--|60 |...|33 |<--|1|<<-- +// |___| --- |___| |___| --- |___| --- |___|...|___| |___| +// +// +// <<-- shifting -- +//##################################################################################################################### + +// use SRLC32E for lower 32 stages and 32 registers for upper 32 stages. +// we need to provide 30 bits addres. SRLC32 has only one bit output. +// address seed will be loaded to upper 32 bits. +// +// parallel load and serial shift out to LFSR during INIT time + +generate + if(PRBS_CMD == "ADDRESS" && PRBS_WIDTH == 64) begin :gen64_taps + always @ (posedge clk_i) begin + if(prbs_seed_init) begin//reset it to a known good state to prevent it locks up + lfsr_q <= #TCQ {31'b0,prbs_seed_i}; + end else if(clk_en) begin + lfsr_q[64] <= #TCQ lfsr_q[64] ^ lfsr_q[63]; + lfsr_q[63] <= #TCQ lfsr_q[62]; + lfsr_q[62] <= #TCQ lfsr_q[64] ^ lfsr_q[61]; + lfsr_q[61] <= #TCQ lfsr_q[64] ^ lfsr_q[60]; + lfsr_q[60:2] <= #TCQ lfsr_q[59:1]; + lfsr_q[1] <= #TCQ lfsr_q[64]; + end + end + + always @(lfsr_q[32:1]) begin + prbs = lfsr_q[32:1]; + end + end +endgenerate + +function integer logb2; + input [31:0] in; + integer i; + begin + i = in; + for(logb2=1; i>0; logb2=logb2+1) + i = i >> 1; + end +endfunction + +generate + if(PRBS_CMD == "ADDRESS" && PRBS_WIDTH == 32) begin :gen32_taps + always @ (posedge clk_i) begin + if(prbs_seed_init) begin //reset it to a known good state to prevent it locks up + lfsr_q <= #TCQ {prbs_seed_i}; + end else if(clk_en) begin + lfsr_q[32:9] <= #TCQ lfsr_q[31:8]; + lfsr_q[8] <= #TCQ lfsr_q[32] ^ lfsr_q[7]; + lfsr_q[7] <= #TCQ lfsr_q[32] ^ lfsr_q[6]; + lfsr_q[6:4] <= #TCQ lfsr_q[5:3]; + + lfsr_q[3] <= #TCQ lfsr_q[32] ^ lfsr_q[2]; + lfsr_q[2] <= #TCQ lfsr_q[1] ; + lfsr_q[1] <= #TCQ lfsr_q[32]; + end + end + + integer i; + always @(lfsr_q[32:1]) begin + + if (FAMILY == "SPARTAN6" ) begin // for 32 bits + + for(i = logb2(DWIDTH) + 1; i <= SEED_WIDTH - 1; i = i + 1) + + if(PRBS_SADDR_MASK_POS[i] == 1) + prbs[i] = PRBS_SADDR[i] | lfsr_q[i+1]; + else if(PRBS_EADDR_MASK_POS[i] == 1) + prbs[i] = PRBS_EADDR[i] & lfsr_q[i+1]; + else + prbs[i] = lfsr_q[i+1]; + + prbs[logb2(DWIDTH ) :0] = {logb2(DWIDTH ) + 1{1'b0}}; + + end + else begin + for(i = logb2(DWIDTH)-4; i <= SEED_WIDTH - 1; i = i + 1) + if(PRBS_SADDR_MASK_POS[i] == 1) + prbs[i] = PRBS_SADDR[i] | lfsr_q[i+1]; + else if(PRBS_EADDR_MASK_POS[i] == 1) + prbs[i] = PRBS_EADDR[i] & lfsr_q[i+1]; + else + prbs[i] = lfsr_q[i+1]; + prbs[logb2(DWIDTH)-5:0] = {logb2(DWIDTH) - 4{1'b0}}; + + end + + end +end endgenerate + +////////////////////////////////////////////////////////////////////////// +//#################################################################################################################### +// # +// # +// 15 taps: [15,14]: # +// # +// # +// +// +// ............................................................. +// ^ ^ . ^ +// | ____ | ___ ___ ___ ___ ___ | +// | | | |---|<- | | | | | |...| | | | | +// ----|15 |<--|xor|<-- |14 |<--|13 |<--|12 |...|2 |<--|1 |<<-- +// |___| --- |___| |___| |___|...|___| |___| +// +// +// <<-- shifting -- +//##################################################################################################################### + +generate + if(PRBS_CMD == "INSTR" | PRBS_CMD == "BLEN") begin :gen20_taps + always @(posedge clk_i) begin + if(prbs_seed_init) begin//reset it to a known good state to prevent it locks up + lfsr_q <= #TCQ {5'b0,prbs_seed_i[14:0]}; + end else if(clk_en) begin + lfsr_q[20] <= #TCQ lfsr_q[19]; + lfsr_q[19] <= #TCQ lfsr_q[18]; + + lfsr_q[18] <= #TCQ lfsr_q[20] ^lfsr_q[17]; + + lfsr_q[17:2] <= #TCQ lfsr_q[16:1]; + lfsr_q[1] <= #TCQ lfsr_q[20]; + end + end + + always @ (lfsr_q[SEED_WIDTH - 1:1], ZEROS) begin + prbs = {ZEROS[SEED_WIDTH - 1:7],lfsr_q[6:1]}; + end + end +endgenerate + +assign prbs_o = prbs; + +endmodule diff --git "a/Frogwells_fpga_design/\345\237\272\344\272\216FPGA\343\200\201DDR3\345\222\214USB2.0\347\232\204\345\233\276\345\203\217\351\207\207\351\233\206\347\263\273\347\273\237/debug/ddr_test/rtl/traffic_gen/data_prbs_gen.v" "b/Frogwells_fpga_design/\345\237\272\344\272\216FPGA\343\200\201DDR3\345\222\214USB2.0\347\232\204\345\233\276\345\203\217\351\207\207\351\233\206\347\263\273\347\273\237/debug/ddr_test/rtl/traffic_gen/data_prbs_gen.v" new file mode 100644 index 0000000000000000000000000000000000000000..d4d3ea0cdeb17ce8911000b7759cc39a4d568b0a --- /dev/null +++ "b/Frogwells_fpga_design/\345\237\272\344\272\216FPGA\343\200\201DDR3\345\222\214USB2.0\347\232\204\345\233\276\345\203\217\351\207\207\351\233\206\347\263\273\347\273\237/debug/ddr_test/rtl/traffic_gen/data_prbs_gen.v" @@ -0,0 +1,127 @@ +//***************************************************************************** +// (c) Copyright 2008-2009 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: %version +// \ \ Application: MIG +// / / Filename: data_prbs_gen.v +// /___/ /\ Date Last Modified: $Date: 2011/06/02 07:16:33 $ +// \ \ / \ Date Created: Fri Sep 01 2006 +// \___\/\___\ +// +//Device: Spartan6 +//Design Name: DDR/DDR2/DDR3/LPDDR +//Purpose: This module is used LFSR to generate random data for memory +// data write or memory data read comparison.The first data is +// seeded by the input prbs_seed_i which is connected to memory address. +//Reference: +//Revision History: +//***************************************************************************** + +`timescale 1ps/1ps + +module data_prbs_gen # + ( + parameter TCQ = 100, + + parameter EYE_TEST = "FALSE", + parameter PRBS_WIDTH = 32, // "SEQUENTIAL_BUrst_i" + parameter SEED_WIDTH = 32 + ) + ( + input clk_i, + input clk_en, + input rst_i, + input [31:0] prbs_fseed_i, + input prbs_seed_init, // when high the prbs_x_seed will be loaded + input [PRBS_WIDTH - 1:0] prbs_seed_i, + + output [PRBS_WIDTH - 1:0] prbs_o // generated address + ); + +reg [PRBS_WIDTH - 1 :0] prbs; +reg [PRBS_WIDTH :1] lfsr_q; +integer i; + + + +always @ (posedge clk_i) +begin + if (prbs_seed_init && EYE_TEST == "FALSE" || rst_i ) //reset it to a known good state to prevent it locks up +// if (rst_i ) //reset it to a known good state to prevent it locks up + + begin + lfsr_q <= #TCQ {prbs_seed_i + prbs_fseed_i[31:0] + 32'h55555555}; + + end + else if (clk_en) begin + + lfsr_q[32:9] <= #TCQ lfsr_q[31:8]; + lfsr_q[8] <= #TCQ lfsr_q[32] ^ lfsr_q[7]; + lfsr_q[7] <= #TCQ lfsr_q[32] ^ lfsr_q[6]; + lfsr_q[6:4] <= #TCQ lfsr_q[5:3]; + + lfsr_q[3] <= #TCQ lfsr_q[32] ^ lfsr_q[2]; + lfsr_q[2] <= #TCQ lfsr_q[1] ; + lfsr_q[1] <= #TCQ lfsr_q[32]; + + + end +end + +always @ (lfsr_q[PRBS_WIDTH:1]) begin + prbs = lfsr_q[PRBS_WIDTH:1]; +end + +assign prbs_o = prbs; + +endmodule + + diff --git "a/Frogwells_fpga_design/\345\237\272\344\272\216FPGA\343\200\201DDR3\345\222\214USB2.0\347\232\204\345\233\276\345\203\217\351\207\207\351\233\206\347\263\273\347\273\237/debug/ddr_test/rtl/traffic_gen/init_mem_pattern_ctr.v" "b/Frogwells_fpga_design/\345\237\272\344\272\216FPGA\343\200\201DDR3\345\222\214USB2.0\347\232\204\345\233\276\345\203\217\351\207\207\351\233\206\347\263\273\347\273\237/debug/ddr_test/rtl/traffic_gen/init_mem_pattern_ctr.v" new file mode 100644 index 0000000000000000000000000000000000000000..ea72f62b424d880a3d010c7fcc98b7de3e4cc8cb --- /dev/null +++ "b/Frogwells_fpga_design/\345\237\272\344\272\216FPGA\343\200\201DDR3\345\222\214USB2.0\347\232\204\345\233\276\345\203\217\351\207\207\351\233\206\347\263\273\347\273\237/debug/ddr_test/rtl/traffic_gen/init_mem_pattern_ctr.v" @@ -0,0 +1,692 @@ +//***************************************************************************** +// (c) Copyright 2008-2009 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: %version +// \ \ Application: MIG +// / / Filename: init_mem_pattern_ctr.v +// /___/ /\ Date Last Modified: $Date: 2011/06/02 07:16:33 $ +// \ \ / \ Date Created: Fri Sep 01 2006 +// \___\/\___\ +// +//Device: Spartan6 +//Design Name: DDR/DDR2/DDR3/LPDDR +//Purpose: This moduel has a small FSM to control the operation of +// mcb_traffic_gen module.It first fill up the memory with a selected +// DATA pattern and then starts the memory testing state. +//Reference: +//Revision History: 1.1 Modify to allow data_mode_o to be controlled by parameter DATA_MODE +// and the fixed_bl_o is fixed at 64 if data_mode_o == PRBA and FAMILY == "SPARTAN6" +// The fixed_bl_o in Virtex6 is determined by the MEM_BURST_LENGTH. +// 1.2 10-1-2009 Added parameter TST_MEM_INSTR_MODE to select instruction pattern during +// memory testing phase. +// 1.3 05/19/2010 If MEM_BURST_LEN value is passed with value of zero, it is treated as +// "OTF" Burst Mode and TG will only generate BL 8 traffic. + + +//***************************************************************************** + +`timescale 1ps/1ps + + + + + +module init_mem_pattern_ctr # + ( + parameter TCQ = 100, + parameter FAMILY = "SPARTAN6", // VIRTEX6, SPARTAN6 + parameter TST_MEM_INSTR_MODE = "R_W_INSTR_MODE", // Spartan6 Available commands: + // "FIXED_INSTR_R_MODE", "FIXED_INSTR_W_MODE" + // "R_W_INSTR_MODE", "RP_WP_INSTR_MODE + // "R_RP_W_WP_INSTR_MODE", "R_RP_W_WP_REF_INSTR_MODE" + // Virtex 6 Available commands: + // "FIXED_INSTR_R_MODE" - Only Read commands will be generated. + // "FIXED_INSTR_W_MODE" -- Only Write commands will be generated. + // "R_W_INSTR_MODE" - Random Read/Write commands will be generated. + parameter MEM_BURST_LEN = 8, // VIRTEX 6 Option. + parameter CMD_PATTERN = "CGEN_ALL", // "CGEN_ALL" option generates all available + // commands pattern. + parameter BEGIN_ADDRESS = 32'h00000000, + parameter END_ADDRESS = 32'h00000fff, + parameter ADDR_WIDTH = 30, + parameter DWIDTH = 32, + parameter CMD_SEED_VALUE = 32'h12345678, + parameter DATA_SEED_VALUE = 32'hca345675, + parameter DATA_MODE = 4'b0010, + parameter PORT_MODE = "BI_MODE", // V6 Option: "BI_MODE"; SP6 Option: "WR_MODE", "RD_MODE", "BI_MODE" + parameter EYE_TEST = "FALSE" // set EYE_TEST = "TRUE" to probe memory signals. + // Traffic Generator will only write to one single location and no + // read transactions will be generated. + + ) + ( + input clk_i, + input rst_i, + + input [ADDR_WIDTH-1:0] mcb_cmd_addr_i, + input [5:0] mcb_cmd_bl_i, + input mcb_cmd_en_i, + input [2:0] mcb_cmd_instr_i, + input mcb_wr_en_i, + input vio_modify_enable, // 0: default to ADDR as DATA PATTERN. No runtime change in data mode. + // 1: enable exteral VIO to control the data_mode pattern + // and address mode pattern during runtime. + input [2:0] vio_data_mode_value, + input [2:0] vio_addr_mode_value, + input [1:0] vio_bl_mode_value, + input [5:0] vio_fixed_bl_value, // valid range is: from 1 to 64. + + input mcb_init_done_i, + input cmp_error, + output reg run_traffic_o, + // runtime parameter + output [31:0] start_addr_o, // define the start of address + output [31:0] end_addr_o, + output [31:0] cmd_seed_o, // same seed apply to all addr_prbs_gen, bl_prbs_gen, instr_prbs_gen + output [31:0] data_seed_o, + output reg load_seed_o, // + // upper layer inputs to determine the command bus and data pattern + // internal traffic generator initialize the memory with + output reg [2:0] addr_mode_o, // "00" = bram; takes the address from bram output + // "001" = fixed address from the fixed_addr input + // "010" = psuedo ramdom pattern; generated from internal 64 bit LFSR + // "011" = sequential + + + // for each instr_mode, traffic gen fill up with a predetermined pattern before starting the instr_pattern that defined + // in the instr_mode input. The runtime mode will be automatically loaded inside when it is in + output reg [3:0] instr_mode_o, // "0000" = Fixed + // "0001" = bram; takes instruction from bram output + // "0010" = R/W + // "0011" = RP/WP + // "0100" = R/RP/W/WP + // "0101" = R/RP/W/WP/REF + + + output reg [1:0] bl_mode_o, // "00" = bram; takes the burst length from bram output + // "01" = fixed , takes the burst length from the fixed_bl input + // "10" = psuedo ramdom pattern; generated from internal 16 bit LFSR + + output reg [3:0] data_mode_o, // "00" = bram; + // "01" = fixed data from the fixed_data input + // "10" = psuedo ramdom pattern; generated from internal 32 bit LFSR + // "11" = sequential using the addrs as the starting data pattern + output reg mode_load_o, + + // fixed pattern inputs interface + output reg [5:0] fixed_bl_o, // range from 1 to 64 + output reg [2:0] fixed_instr_o, //RD 3'b001 + //RDP 3'b011 + //WR 3'b000 + //WRP 3'b010 + //REFRESH 3'b100 + output [31:0] fixed_addr_o // only upper 30 bits will be used + + ); + + //FSM State Defination +parameter IDLE = 5'b00001, + INIT_MEM_WRITE = 5'b00010, + INIT_MEM_READ = 5'b00100, + TEST_MEM = 5'b01000, + CMP_ERROR = 5'b10000; + + +localparam BRAM_ADDR = 2'b00; +localparam FIXED_ADDR = 2'b01; +localparam PRBS_ADDR = 2'b10; +localparam SEQUENTIAL_ADDR = 2'b11; + +localparam BRAM_INSTR_MODE = 4'b0000; +localparam FIXED_INSTR_MODE = 4'b0001; +localparam R_W_INSTR_MODE = 4'b0010; +localparam RP_WP_INSTR_MODE = 4'b0011; +localparam R_RP_W_WP_INSTR_MODE = 4'b0100; +localparam R_RP_W_WP_REF_INSTR_MODE = 4'b0101; + +localparam BRAM_BL_MODE = 2'b00; +localparam FIXED_BL_MODE = 2'b01; +localparam PRBS_BL_MODE = 2'b10; + +localparam BRAM_DATAL_MODE = 4'b0000; +localparam FIXED_DATA_MODE = 4'b0001; +localparam ADDR_DATA_MODE = 4'b0010; +localparam HAMMER_DATA_MODE = 4'b0011; +localparam NEIGHBOR_DATA_MODE = 4'b0100; +localparam WALKING1_DATA_MODE = 4'b0101; +localparam WALKING0_DATA_MODE = 4'b0110; +localparam PRBS_DATA_MODE = 4'b0111; + +// type fixed instruction +localparam RD_INSTR = 3'b001; +localparam RDP_INSTR = 3'b011; +localparam WR_INSTR = 3'b000; + +localparam WRP_INSTR = 3'b010; +localparam REFRESH_INSTR = 3'b100; +localparam NOP_WR_INSTR = 3'b101; + + +reg [4:0] current_state; +reg [4:0] next_state; +reg mcb_init_done_reg; +reg mcb_init_done_reg1; +reg AC2_G_E2,AC1_G_E1,AC3_G_E3; +reg upper_end_matched; +reg [31:0] end_boundary_addr; +reg [31:0] mcb_cmd_addr_r; + +reg mcb_cmd_en_r; +//reg [ADDR_WIDTH-1:0] mcb_cmd_addr_r; +reg [5:0] mcb_cmd_bl_r; +reg lower_end_matched; +reg end_addr_reached; +reg run_traffic; +reg bram_mode_enable; +wire tst_matched; +reg [31:0] current_address; +reg [5:0] fix_bl_value; +reg [3:0] data_mode_sel; +reg [2:0] addr_mode_sel; +reg [1:0] bl_mode_sel; +reg [2:0] addr_mode; +reg [10:0] INC_COUNTS; +wire [5:0] FIXEDBL; +wire [3:0] test_mem_instr_mode; + +assign test_mem_instr_mode = (TST_MEM_INSTR_MODE == "BRAM_INSTR_MODE") ? 4'b0000: + (TST_MEM_INSTR_MODE == "FIXED_INSTR_R_MODE" || + TST_MEM_INSTR_MODE == "FIXED_INSTR_W_MODE") ? 4'b0001: + (TST_MEM_INSTR_MODE == "R_W_INSTR_MODE") ? 4'b0010: + (TST_MEM_INSTR_MODE == "RP_WP_INSTR_MODE" && FAMILY == "SPARTAN6") ? 4'b0011: + (TST_MEM_INSTR_MODE == "R_RP_W_WP_INSTR_MODE" && FAMILY == "SPARTAN6") ? 4'b0100: + (TST_MEM_INSTR_MODE == "R_RP_W_WP_REF_INSTR_MODE" && FAMILY == "SPARTAN6") ? 4'b0101: + 4'b0010; + + + + +assign FIXEDBL = 64; // This is fixed for current Spartan 6 Example Design + + + + + + + + + + + + + + +generate +if (FAMILY == "SPARTAN6" ) begin : INC_COUNTS_S + +always @ (posedge clk_i) + INC_COUNTS <= (DWIDTH/8); + +end +endgenerate + + + + + + +generate +if (FAMILY == "VIRTEX6" ) begin : INC_COUNTS_V +always @ (posedge clk_i) +begin +if ( (DWIDTH >= 256 && DWIDTH <= 576)) // 64 144 + INC_COUNTS <= 32 ; +else if ((DWIDTH >= 128) && (DWIDTH <= 224)) // 32 dq pins or 566 dq pins + INC_COUNTS <= 16 ; +else if ((DWIDTH == 64) || (DWIDTH == 96)) // 16 dq pins or 24 dqpins + INC_COUNTS <= 8 ; +else if ((DWIDTH == 32) ) // 8 dq pins + INC_COUNTS <= 4 ; +end +end +endgenerate + + +always @ (posedge clk_i) +begin +if (rst_i) + current_address <= BEGIN_ADDRESS; +else if (mcb_wr_en_i && (current_state == INIT_MEM_WRITE && (PORT_MODE == "WR_MODE" || PORT_MODE == "BI_MODE")) + || (mcb_wr_en_i && (current_state == IDLE && PORT_MODE == "RD_MODE")) ) + current_address <= current_address + INC_COUNTS; +else + current_address <= current_address; + +end + + +always @ (posedge clk_i) +begin + if (current_address[29:24] >= end_boundary_addr[29:24]) + AC3_G_E3 <= 1'b1; + else + AC3_G_E3 <= 1'b0; + + + if (current_address[23:16] >= end_boundary_addr[23:16]) + AC2_G_E2 <= 1'b1; + else + AC2_G_E2 <= 1'b0; + + if (current_address[15:8] >= end_boundary_addr[15:8]) + AC1_G_E1 <= 1'b1; +else + AC1_G_E1 <= 1'b0; + + +end +always @(posedge clk_i) +begin +if (rst_i) + upper_end_matched <= 1'b0; + + else if (mcb_cmd_en_i) + upper_end_matched <= AC3_G_E3 & AC2_G_E2 & AC1_G_E1; +end + +wire [6:0] FIXED_BL_VALUE; +assign FIXED_BL_VALUE = (FAMILY == "VIRTEX6" && (MEM_BURST_LEN == 8 || MEM_BURST_LEN == 0)) ? 2 : + (FAMILY == "VIRTEX6" && MEM_BURST_LEN == 4) ? 1 : + FIXEDBL; + +always @(posedge clk_i) +begin +// end_boundary_addr <= (END_ADDRESS[31:0] - (DWIDTH/8)*FIXEDBL +1) ; + end_boundary_addr <= (END_ADDRESS[31:0] - (DWIDTH/8) +1) ; + +end + + + +always @(posedge clk_i) +begin + if (current_address[7:0] >= end_boundary_addr[7:0]) + + lower_end_matched <= 1'b1; + else + lower_end_matched <= 1'b0; + +end + + +always @(posedge clk_i) +begin + if (mcb_cmd_en_i ) + mcb_cmd_addr_r <= mcb_cmd_addr_i; +end + + +always @(posedge clk_i) +begin + if (mcb_cmd_en_i) + mcb_cmd_bl_r <= mcb_cmd_bl_i; +end + +always @(posedge clk_i) +begin + if ((upper_end_matched && lower_end_matched && FAMILY == "SPARTAN6" && DWIDTH == 32) || + (upper_end_matched && lower_end_matched && FAMILY == "SPARTAN6" && DWIDTH == 64) || + (upper_end_matched && DWIDTH == 128 && FAMILY == "SPARTAN6") || + (upper_end_matched && lower_end_matched && FAMILY == "VIRTEX6")) + end_addr_reached <= 1'b1; + else + end_addr_reached <= 1'b0; + +end + + +assign tst_matched = upper_end_matched & lower_end_matched; + +assign fixed_addr_o = 32'h00001234; + + + + always @ (posedge clk_i) + begin + mcb_init_done_reg1 <= mcb_init_done_i; + mcb_init_done_reg <= mcb_init_done_reg1; +end + + always @ (posedge clk_i) + run_traffic_o <= run_traffic; + + + + always @ (posedge clk_i) + begin + if (rst_i) + current_state <= 5'b00001; + else + current_state <= next_state; + end + + assign start_addr_o = BEGIN_ADDRESS;//BEGIN_ADDRESS; + assign end_addr_o = END_ADDRESS; + assign cmd_seed_o = CMD_SEED_VALUE; + assign data_seed_o = DATA_SEED_VALUE; + + +reg [2:0] syn1_vio_data_mode_value; +reg [2:0] syn1_vio_addr_mode_value; + + + always @ (posedge clk_i) + begin + if (rst_i) begin + syn1_vio_data_mode_value <= 3'b011; + syn1_vio_addr_mode_value <= 2'b11; + end + else if (vio_modify_enable == 1'b1) begin + syn1_vio_data_mode_value <= vio_data_mode_value; + syn1_vio_addr_mode_value <= vio_addr_mode_value; + end + end + + + always @ (posedge clk_i) + begin + if (rst_i) begin + data_mode_sel <= DATA_MODE;//ADDR_DATA_MODE; + addr_mode_sel <= 2'b11; + end + else if (vio_modify_enable == 1'b1) begin + data_mode_sel <= syn1_vio_data_mode_value[2:0]; + addr_mode_sel <= vio_addr_mode_value; + end + end + + always @ (posedge clk_i) + begin + if (rst_i || FAMILY == "VIRTEX6") + fix_bl_value <= FIXED_BL_VALUE;//ADDR_DATA_MODE; + + else if (vio_modify_enable == 1'b1) begin + fix_bl_value <= vio_fixed_bl_value; + end + end + + always @ (posedge clk_i) + begin + if (rst_i || (FAMILY == "VIRTEX6")) + if (FAMILY == "VIRTEX6") + bl_mode_sel <= FIXED_BL_MODE; + else + bl_mode_sel <= PRBS_BL_MODE; + else if (vio_modify_enable == 1'b1) begin + bl_mode_sel <= vio_bl_mode_value; + end + end + + + + + +always @ (posedge clk_i) +begin + data_mode_o <= data_mode_sel; + addr_mode_o <= addr_mode; + + // assuming if vio_modify_enable is enabled and vio_addr_mode_value is set to zero + // user wants to have bram interface. + if (syn1_vio_addr_mode_value == 0 && vio_modify_enable == 1'b1) + bram_mode_enable <= 1'b1; + else + bram_mode_enable <= 1'b0; + + end + + +always @ (*) +begin + load_seed_o = 1'b0; + if (CMD_PATTERN == "CGEN_BRAM" || bram_mode_enable ) + addr_mode = 'b0; + else + addr_mode = SEQUENTIAL_ADDR; + + if (CMD_PATTERN == "CGEN_BRAM" || bram_mode_enable ) + instr_mode_o = 'b0; + else + instr_mode_o = FIXED_INSTR_MODE; + + + if (CMD_PATTERN == "CGEN_BRAM" || bram_mode_enable ) + bl_mode_o = 'b0; + else + bl_mode_o = FIXED_BL_MODE; + + + + if (FAMILY == "VIRTEX6") + fixed_bl_o = FIXED_BL_VALUE; + // PRBS mode + else if (data_mode_o[2:0] == 3'b111 && FAMILY == "SPARTAN6") + fixed_bl_o = 64; // Our current PRBS algorithm wants to maximize the range bl from 1 to 64. + else + fixed_bl_o = fix_bl_value; + + + + mode_load_o = 1'b0; + run_traffic = 1'b0; + next_state = IDLE; + + if (PORT_MODE == "RD_MODE") begin + fixed_instr_o = RD_INSTR; + end + else if( PORT_MODE == "WR_MODE" || PORT_MODE == "BI_MODE") begin + fixed_instr_o = WR_INSTR; + end + +case(current_state) + IDLE: + begin + if(mcb_init_done_reg ) //rdp_rdy_i comes from read_data path + begin + if (PORT_MODE == "WR_MODE" || PORT_MODE == "BI_MODE") begin + next_state = INIT_MEM_WRITE; + mode_load_o = 1'b1; + run_traffic = 1'b0; + load_seed_o = 1'b1; + end + else if (PORT_MODE == "RD_MODE" && end_addr_reached) begin + next_state = TEST_MEM; + mode_load_o = 1'b1; + run_traffic = 1'b1; + load_seed_o = 1'b1; + + end + end + else + begin + next_state = IDLE; + run_traffic = 1'b0; + load_seed_o = 1'b0; + + end + + end + INIT_MEM_WRITE: begin + + if (end_addr_reached && EYE_TEST == "FALSE" ) + begin + next_state = TEST_MEM; + mode_load_o = 1'b1; + load_seed_o = 1'b1; + run_traffic = 1'b1; + + end + else + begin + next_state = INIT_MEM_WRITE; + run_traffic = 1'b1; + mode_load_o = 1'b0; + load_seed_o = 1'b0; + if (EYE_TEST == "TRUE") + addr_mode = FIXED_ADDR; + else if (CMD_PATTERN == "CGEN_BRAM" || bram_mode_enable ) + addr_mode = 'b0; + else + addr_mode = SEQUENTIAL_ADDR; + + end + + end + + INIT_MEM_READ: begin + + if (end_addr_reached ) + begin + next_state = TEST_MEM; + mode_load_o = 1'b1; + load_seed_o = 1'b1; + + end + else + begin + next_state = INIT_MEM_READ; + run_traffic = 1'b0; + mode_load_o = 1'b0; + load_seed_o = 1'b0; + + end + + end + TEST_MEM: begin + if (cmp_error) + next_state = CMP_ERROR; + + else + next_state = TEST_MEM; + run_traffic = 1'b1; + + + if (PORT_MODE == "BI_MODE" && TST_MEM_INSTR_MODE == "FIXED_INSTR_W_MODE") + fixed_instr_o = WR_INSTR; + else if (PORT_MODE == "BI_MODE" && TST_MEM_INSTR_MODE == "FIXED_INSTR_R_MODE") + fixed_instr_o = RD_INSTR; + else if (PORT_MODE == "RD_MODE") + fixed_instr_o = RD_INSTR; + + else if( PORT_MODE == "WR_MODE") + fixed_instr_o = WR_INSTR; + + + if (FAMILY == "VIRTEX6") + fixed_bl_o = fix_bl_value; + else if ((data_mode_o == 3'b111) && (FAMILY == "SPARTAN6")) + fixed_bl_o = 64; // Our current PRBS algorithm wants to maximize the range bl from 1 to 64. + else + fixed_bl_o = fix_bl_value; + + bl_mode_o = bl_mode_sel;//FIXED_BL_MODE;//PRBS_BL_MODE;//PRBS_BL_MODE; //FIXED_BL_MODE; + + if (bl_mode_o == PRBS_BL_MODE) + addr_mode = PRBS_ADDR; + else + addr_mode = addr_mode_sel; + + + + if(PORT_MODE == "BI_MODE") begin + if(CMD_PATTERN == "CGEN_BRAM" || bram_mode_enable ) + instr_mode_o = BRAM_INSTR_MODE; + else + instr_mode_o = test_mem_instr_mode;//R_RP_W_WP_REF_INSTR_MODE;//FIXED_INSTR_MODE;//R_W_INSTR_MODE;//R_RP_W_WP_INSTR_MODE;//R_W_INSTR_MODE;//R_W_INSTR_MODE; //FIXED_INSTR_MODE;// + end + else if (PORT_MODE == "RD_MODE" || PORT_MODE == "WR_MODE") begin + instr_mode_o = FIXED_INSTR_MODE; + end + + end + + + + + + CMP_ERROR: + begin + next_state = CMP_ERROR; + bl_mode_o = bl_mode_sel;//PRBS_BL_MODE;//PRBS_BL_MODE; //FIXED_BL_MODE; + fixed_instr_o = RD_INSTR; + addr_mode = SEQUENTIAL_ADDR;//PRBS_ADDR;//PRBS_ADDR;//PRBS_ADDR;//SEQUENTIAL_ADDR; + if(CMD_PATTERN == "CGEN_BRAM" || bram_mode_enable ) + instr_mode_o = BRAM_INSTR_MODE;// + else + instr_mode_o = test_mem_instr_mode;//FIXED_INSTR_MODE;//R_W_INSTR_MODE;//R_RP_W_WP_INSTR_MODE;//R_W_INSTR_MODE;//R_W_INSTR_MODE; //FIXED_INSTR_MODE;// + + run_traffic = 1'b1; // ?? keep it running or stop if error happened + + end + default: + begin + next_state = IDLE; + //run_traffic = 1'b0; + + end + + endcase + end + + + + +endmodule diff --git "a/Frogwells_fpga_design/\345\237\272\344\272\216FPGA\343\200\201DDR3\345\222\214USB2.0\347\232\204\345\233\276\345\203\217\351\207\207\351\233\206\347\263\273\347\273\237/debug/ddr_test/rtl/traffic_gen/mcb_flow_control.v" "b/Frogwells_fpga_design/\345\237\272\344\272\216FPGA\343\200\201DDR3\345\222\214USB2.0\347\232\204\345\233\276\345\203\217\351\207\207\351\233\206\347\263\273\347\273\237/debug/ddr_test/rtl/traffic_gen/mcb_flow_control.v" new file mode 100644 index 0000000000000000000000000000000000000000..193848b63348ea31af46127a818a150fd8a22bf8 --- /dev/null +++ "b/Frogwells_fpga_design/\345\237\272\344\272\216FPGA\343\200\201DDR3\345\222\214USB2.0\347\232\204\345\233\276\345\203\217\351\207\207\351\233\206\347\263\273\347\273\237/debug/ddr_test/rtl/traffic_gen/mcb_flow_control.v" @@ -0,0 +1,634 @@ +//***************************************************************************** +// (c) Copyright 2008-2009 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: %version +// \ \ Application: MIG +// / / Filename: mcb_flow_control.v +// /___/ /\ Date Last Modified: $Date: 2011/06/02 07:16:33 $ +// \ \ / \ Date Created: +// \___\/\___\ +// +//Device: Spartan6 +//Design Name: DDR/DDR2/DDR3/LPDDR +//Purpose: This module is the main flow control between cmd_gen.v, +// write_data_path and read_data_path modules. +//Design Name: DDR/DDR2/DDR3/LPDDR +//Reference: +//Revision History: +//***************************************************************************** + +`timescale 1ps/1ps + +module mcb_flow_control # + ( + parameter TCQ = 100, + parameter FAMILY = "SPARTAN6" + ) + ( + input clk_i, + input [9:0] rst_i, + // interface to cmd_gen, pipeline inserter + output reg cmd_rdy_o, + input cmd_valid_i, + input [2:0] cmd_i, + input [31:0] addr_i, + input [5:0] bl_i, + + + // interface to mcb_cmd port + input mcb_cmd_full, + output reg [2:0] cmd_o, + output reg [31:0] addr_o, + output reg [5:0] bl_o, + output cmd_en_o, // interface to write data path module + input last_word_wr_i, + input wdp_rdy_i, + output wdp_valid_o, + output wdp_validB_o, + output wdp_validC_o, + + output [31:0] wr_addr_o, + output [5:0] wr_bl_o, + // interface to read data path module + input last_word_rd_i, + input rdp_rdy_i, + output rdp_valid_o, + output [31:0] rd_addr_o, + output [5:0] rd_bl_o + ); + + //FSM State Defination +localparam READY = 5'b00001, + READ = 5'b00010, + WRITE = 5'b00100, + CMD_WAIT = 5'b01000, + REFRESH_ST = 5'b10000; + +localparam RD = 3'b001; +localparam RDP = 3'b011; +localparam WR = 3'b000; +localparam WRP = 3'b010; +localparam REFRESH = 3'b100; +localparam NOP = 3'b101; // this defination is local to this traffic gen and is not defined + + +reg cmd_fifo_rdy; +wire cmd_rd; +wire cmd_wr; // need equation +wire cmd_others; +reg push_cmd; +reg xfer_cmd; +reg rd_vld ; +reg wr_vld; +reg cmd_rdy; +reg [2:0] cmd_reg; +reg [31:0] addr_reg; +reg [5:0] bl_reg; + +reg rdp_valid; +(*EQUIVALENT_REGISTER_REMOVAL="NO"*) reg wdp_valid,wdp_validB,wdp_validC; + +reg [4:0] current_state; +reg [4:0] next_state; +reg [3:0] tstpointA; +reg push_cmd_r; +reg wait_done; +reg cmd_en_r1 ; +reg wr_in_progress; +reg tst_cmd_rdy_o; + + + + +// mcb_command bus outputs +assign cmd_en_o = cmd_en_r1; + +always @ (posedge clk_i) begin + + cmd_rdy_o <= #TCQ cmd_rdy; + tst_cmd_rdy_o <= #TCQ cmd_rdy; + +end + +always @ (posedge clk_i) +begin +if (rst_i[8]) + cmd_en_r1 <= #TCQ 1'b0; +else if ( xfer_cmd) + cmd_en_r1 <= #TCQ 1'b1; + else if (!mcb_cmd_full) + cmd_en_r1 <= #TCQ 1'b0; + + end + +always @ (posedge clk_i) +begin +if (rst_i[9]) + cmd_fifo_rdy <= #TCQ 1'b1; +else if (xfer_cmd) + cmd_fifo_rdy <= #TCQ 1'b0; +else if (!mcb_cmd_full) + cmd_fifo_rdy <= #TCQ 1'b1; +end + +always @ (posedge clk_i) +begin +if (rst_i[9]) begin + addr_o <= #TCQ 'b0; + cmd_o <= #TCQ 'b0; + bl_o <= #TCQ 'b0; +end +else if (xfer_cmd ) begin + addr_o <= #TCQ addr_reg; + if (FAMILY == "SPARTAN6") + cmd_o <= #TCQ cmd_reg; + else + cmd_o <= #TCQ {2'b00,cmd_reg[0]}; + bl_o <= #TCQ bl_reg; +end + +end + +// go directly to wr_datapath and rd_datapath modules + assign wr_addr_o = addr_i; + assign rd_addr_o = addr_i; +assign rd_bl_o = bl_i ; +assign wr_bl_o = bl_i ; + +assign wdp_valid_o = wdp_valid; +assign wdp_validB_o = wdp_validB; +assign wdp_validC_o = wdp_validC; + +assign rdp_valid_o = rdp_valid; + + +// internal control siganls + +always @ (posedge clk_i) +begin +if (rst_i[8]) + wait_done <= #TCQ 1'b1; +else if (push_cmd_r) + wait_done <= #TCQ 1'b1; +else if (cmd_rdy_o && cmd_valid_i && FAMILY == "SPARTAN6") + wait_done <= #TCQ 1'b0; + + +end + +// + + +always @ (posedge clk_i) + begin + push_cmd_r <= #TCQ push_cmd; + // push_cmd_r2 <= #TCQ push_cmd_r; + end +always @ (posedge clk_i) + if (push_cmd) + begin + cmd_reg <= #TCQ cmd_i; + addr_reg <= #TCQ addr_i; + bl_reg <= #TCQ bl_i - 1; + +end + + + +//--Command Decodes-- +assign cmd_wr = ((cmd_i == WR | cmd_i == WRP) & cmd_valid_i ) ? 1'b1 : 1'b0; +assign cmd_rd = ((cmd_i == RD | cmd_i == RDP) & cmd_valid_i) ? 1'b1 : 1'b0; +assign cmd_others = ((cmd_i[2] == 1'b1)& cmd_valid_i && (FAMILY == "SPARTAN6")) ? 1'b1 : 1'b0; + + +reg cmd_wr_pending_r1; +reg cmd_rd_pending_r1; + +always @ (posedge clk_i) +begin +if (rst_i[0]) + cmd_wr_pending_r1 <= #TCQ 1'b0; + +//else if (current_state == WRITE && last_word_wr_i && !cmd_fifo_rdy) +//else if ( last_word_wr_i && !cmd_fifo_rdy) +else if ( last_word_wr_i ) + + + cmd_wr_pending_r1 <= #TCQ 1'b1; +else if (push_cmd)//xfer_cmd) + cmd_wr_pending_r1 <= #TCQ 1'b0; +end + + +// corner case if fixed read command with fixed bl 64 + +always @ (posedge clk_i) +begin +if (cmd_rd & push_cmd) + cmd_rd_pending_r1 <= #TCQ 1'b1; +else if (xfer_cmd) + cmd_rd_pending_r1 <= #TCQ 1'b0; + +end + + always @ (posedge clk_i) + begin +if (rst_i[0]) + wr_in_progress <= #TCQ 1'b0; +else if (last_word_wr_i) + wr_in_progress <= #TCQ 1'b0; +else if (current_state == WRITE) + wr_in_progress <= #TCQ 1'b1; + + +end + always @ (posedge clk_i) + begin + if (rst_i[0]) + current_state <= #TCQ 4'b0001; + else + current_state <= #TCQ next_state; + end + +// mcb_flow_control statemachine +always @ (*) +begin + push_cmd = 1'b0; + xfer_cmd = 1'b0; + + wdp_valid = 1'b0; + wdp_validB = 1'b0; + wdp_validC = 1'b0; + + rdp_valid = 1'b0; + cmd_rdy = 1'b0; + next_state = current_state; +case(current_state) + READY: + begin + if(rdp_rdy_i & cmd_rd & cmd_fifo_rdy) //rdp_rdy_i comes from read_data path + + begin + next_state = READ; + push_cmd = 1'b1; + xfer_cmd = 1'b0; + rdp_valid = 1'b1; + + end + else if (wdp_rdy_i & cmd_wr & cmd_fifo_rdy) + begin + next_state = WRITE; + push_cmd = 1'b1; + wdp_valid = 1'b1; + wdp_validB = 1'b1; + wdp_validC = 1'b1; + + end + else if ( cmd_others & cmd_fifo_rdy) + begin + next_state = REFRESH_ST; + push_cmd = 1'b1; + xfer_cmd = 1'b0; + + end + + else + begin + next_state = READY; + push_cmd = 1'b0; + end + + + if (cmd_fifo_rdy) + cmd_rdy = 1'b1; + else + cmd_rdy = 1'b0; + + + end + + REFRESH_ST : begin + + if (rdp_rdy_i && cmd_rd && cmd_fifo_rdy ) + begin + next_state = READ; + push_cmd = 1'b1; + rdp_valid = 1'b1; + wdp_valid = 1'b0; + xfer_cmd = 1'b1; + // tstpointA = 4'b0101; + + end + else if (cmd_fifo_rdy && cmd_wr && wdp_rdy_i ) + begin + next_state = WRITE; + push_cmd = 1'b1; + xfer_cmd = 1'b1; + + wdp_valid = 1'b1; + wdp_validB = 1'b1; + wdp_validC = 1'b1; + + // tstpointA = 4'b0110; + + end + + else if (cmd_fifo_rdy && cmd_others) + begin + push_cmd = 1'b1; + xfer_cmd = 1'b1; + end + else if (!cmd_fifo_rdy) + + begin + next_state = CMD_WAIT; + tstpointA = 4'b1001; + + end + else + next_state = READ; + + + + if (cmd_fifo_rdy && ((rdp_rdy_i && cmd_rd) || (wdp_rdy_i && cmd_wr) || (cmd_others))) + cmd_rdy = 1'b1; + else + cmd_rdy = 1'b0; + + + + end + READ: begin + + if (rdp_rdy_i && cmd_rd && cmd_fifo_rdy ) + begin + next_state = READ; + push_cmd = 1'b1; + rdp_valid = 1'b1; + wdp_valid = 1'b0; + xfer_cmd = 1'b1; + tstpointA = 4'b0101; + + end + else if (cmd_fifo_rdy && cmd_wr && wdp_rdy_i ) + begin + next_state = WRITE; + push_cmd = 1'b1; + xfer_cmd = 1'b1; + + wdp_valid = 1'b1; + wdp_validB = 1'b1; + wdp_validC = 1'b1; + + tstpointA = 4'b0110; + + end + + else if (!rdp_rdy_i ) + begin + next_state = READ; + push_cmd = 1'b0; + xfer_cmd = 1'b0; + + tstpointA = 4'b0111; + + wdp_valid = 1'b0; + wdp_validB = 1'b0; + wdp_validC = 1'b0; + rdp_valid = 1'b0; + end + else if (last_word_rd_i && cmd_others && cmd_fifo_rdy ) + + begin + next_state = REFRESH_ST; + push_cmd = 1'b1; + xfer_cmd = 1'b1; + wdp_valid = 1'b0; + wdp_validB = 1'b0; + wdp_validC = 1'b0; + rdp_valid = 1'b0; + tstpointA = 4'b1000; + + end + else if (!cmd_fifo_rdy || !wdp_rdy_i) + + begin + next_state = CMD_WAIT; + tstpointA = 4'b1001; + + end + else + next_state = READ; + + + + if ((rdp_rdy_i && cmd_rd || cmd_wr && wdp_rdy_i || cmd_others) && cmd_fifo_rdy) + cmd_rdy = wait_done;//1'b1; + else + cmd_rdy = 1'b0; + + + end + WRITE: begin // for write, always wait until the last_word_wr + if (cmd_fifo_rdy && cmd_rd && rdp_rdy_i && last_word_wr_i) + begin + next_state = READ; + push_cmd = 1'b1; + xfer_cmd = 1'b1; + rdp_valid = 1'b1; + tstpointA = 4'b0000; + end + else if (!wdp_rdy_i || (wdp_rdy_i && cmd_wr && cmd_fifo_rdy && last_word_wr_i) ) + begin + next_state = WRITE; + tstpointA = 4'b0001; + + if (cmd_wr && last_word_wr_i) begin + wdp_valid = 1'b1; + wdp_validB = 1'b1; + wdp_validC = 1'b1; + + end + else begin + wdp_valid = 1'b0; + wdp_validB = 1'b0; + wdp_validC = 1'b0; + + end + + if (last_word_wr_i ) begin + push_cmd = 1'b1; + xfer_cmd = 1'b1; + end + else begin + push_cmd = 1'b0; + xfer_cmd = 1'b0; + end + + end + else if (last_word_wr_i && cmd_others && cmd_fifo_rdy) + begin + next_state = REFRESH_ST; + push_cmd = 1'b1; + xfer_cmd = 1'b1; + tstpointA = 4'b0010; + + wdp_valid = 1'b0; + wdp_validB = 1'b0; + wdp_validC = 1'b0; + + rdp_valid = 1'b0; + + end + + else if (!cmd_fifo_rdy && last_word_wr_i || !rdp_rdy_i || (!cmd_valid_i && wait_done) ) + + begin + next_state = CMD_WAIT; + push_cmd = 1'b0; + xfer_cmd = 1'b0; + tstpointA = 4'b0011; + + end + + else begin + next_state = WRITE; + tstpointA = 4'b0100; + + end + + // need to include rdp_rdy_i to prevent sending read command if + // read_data_port fifo is full in MCB + if (last_word_wr_i && (cmd_others || rdp_rdy_i && cmd_rd || cmd_wr && wdp_rdy_i) && cmd_fifo_rdy) + cmd_rdy = wait_done;//1'b1; + else + cmd_rdy = 1'b0; + + + end + + + + + + CMD_WAIT: if (!cmd_fifo_rdy || wr_in_progress) + begin + next_state = CMD_WAIT; + cmd_rdy = 1'b0; + tstpointA = 4'b1010; + + end + else if (cmd_fifo_rdy && rdp_rdy_i && cmd_rd) + begin + next_state = READ; + push_cmd = 1'b1; + xfer_cmd = 1'b1; + cmd_rdy = 1'b1; + rdp_valid = 1'b1; + + tstpointA = 4'b1011; + end + else if (cmd_fifo_rdy && cmd_wr && (wait_done || cmd_wr_pending_r1)) + + begin + next_state = WRITE; + push_cmd = 1'b1; + xfer_cmd = 1'b1; + wdp_valid = 1'b1; + wdp_validB = 1'b1; + wdp_validC = 1'b1; + + cmd_rdy = 1'b1; + tstpointA = 4'b1100; + + end + else if (cmd_fifo_rdy && cmd_others) + begin + next_state = REFRESH_ST; + push_cmd = 1'b1; ///////////////// + xfer_cmd = 1'b1; + tstpointA = 4'b1101; + cmd_rdy = 1'b1; + + end + else + begin + next_state = CMD_WAIT; + tstpointA = 4'b1110; + + if ((wdp_rdy_i && rdp_rdy_i)) + cmd_rdy = 1'b1; + else + cmd_rdy = 1'b0; + + + end + + + default: + begin + push_cmd = 1'b0; + xfer_cmd = 1'b0; + + wdp_valid = 1'b0; + wdp_validB = 1'b0; + wdp_validC = 1'b0; + next_state = READY; + // cmd_rdy = 1'b0; + + + + end + + endcase + end + +endmodule diff --git "a/Frogwells_fpga_design/\345\237\272\344\272\216FPGA\343\200\201DDR3\345\222\214USB2.0\347\232\204\345\233\276\345\203\217\351\207\207\351\233\206\347\263\273\347\273\237/debug/ddr_test/rtl/traffic_gen/mcb_traffic_gen.v" "b/Frogwells_fpga_design/\345\237\272\344\272\216FPGA\343\200\201DDR3\345\222\214USB2.0\347\232\204\345\233\276\345\203\217\351\207\207\351\233\206\347\263\273\347\273\237/debug/ddr_test/rtl/traffic_gen/mcb_traffic_gen.v" new file mode 100644 index 0000000000000000000000000000000000000000..556305ac66ff63fe83dd97fefa71a6ca707a756b --- /dev/null +++ "b/Frogwells_fpga_design/\345\237\272\344\272\216FPGA\343\200\201DDR3\345\222\214USB2.0\347\232\204\345\233\276\345\203\217\351\207\207\351\233\206\347\263\273\347\273\237/debug/ddr_test/rtl/traffic_gen/mcb_traffic_gen.v" @@ -0,0 +1,756 @@ +//***************************************************************************** +// (c) Copyright 2008-2009 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: %version +// \ \ Application: MEMC +// / / Filename: mcb_traffic_gen.v +// /___/ /\ Date Last Modified: $Date: +// \ \ / \ Date Created: +// \___\/\___\ +// +//Device: Spartan6/Virtex6 +//Design Name: mcb_traffic_gen +//Purpose: This is top level module of memory traffic generator which can +// generate different CMD_PATTERN and DATA_PATTERN to Spartan 6 +// hard memory controller core. +//Reference: +//Revision History: 1.1 Brought out internal signals cmp_data and cmp_error as outputs. +// 1.2 7/1/2009 Added EYE_TEST parameter for signal SI probing. +// 1.3 10/1/2009 Added dq_error_bytelane_cmp,cumlative_dq_lane_error signals for V6. +// Any comparison error on user read data bus are mapped back to +// dq bus. The cumulative_dq_lane_error accumulate any errors on +// DQ bus. And the dq_error_bytelane_cmp shows error during current +// command cycle. The error can be cleared by input signal "manual_clear_error". +// 1.4 04/10/2010 Removed local generated version of mcb_rd_empty and mcb_wr_full in TG. +// 1.5 05/19/2010 If MEM_BURST_LEN value is passed with value of zero, it is treated as +// "OTF" Burst Mode and TG will only generate BL 8 traffic. + +//***************************************************************************** +`timescale 1ps/1ps + +module mcb_traffic_gen # + ( + parameter TCQ = 100, // SIMULATION tCQ delay. + parameter FAMILY = "SPARTAN6", // "VIRTEX6", "SPARTAN6" + parameter SIMULATION = "FALSE", + parameter MEM_BURST_LEN = 8, // For VIRTEX6 Only in this traffic gen. + // This traffic gen doesn't support DDR3 OTF Burst mode. + + parameter PORT_MODE = "BI_MODE", // SPARTAN6: "BI_MODE", "WR_MODE", "RD_MODE" + // VIRTEX6: "BI_MODE" + parameter DATA_PATTERN = "DGEN_ALL", // "DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL" + parameter CMD_PATTERN = "CGEN_ALL", // "CGEN_RPBS","CGEN_FIXED", "CGEN_BRAM", "CGEN_SEQUENTIAL", "CGEN_ALL", + + parameter ADDR_WIDTH = 30, // Spartan 6 Addr width is 30 + + parameter CMP_DATA_PIPE_STAGES = 0, // parameter for MPMC, it should always set to 0 + + // memory type specific + parameter MEM_COL_WIDTH = 10, // memory column width + parameter NUM_DQ_PINS = 16, // Spartan 6 Options: 4,8,16; + // Virtex 6 DDR2/DDR3 Options: 8,16,24,32,.....144 + parameter DQ_ERROR_WIDTH = 1, + + parameter SEL_VICTIM_LINE = 3, // SEL_VICTIM_LINE LINE is one of the DQ pins is selected to be different than hammer pattern + // SEL_VICTIM_LINE is only for V6. + // Virtex 6 option: 8,9,16,17,32,36,64,72 + parameter DWIDTH = 32, //NUM_DQ_PINS*4, // Spartan 6 Options: 32,64,128; + // Virtex 6 Always: 4* NUM_DQ_PINS + + + // the following parameter is to limit the range of generated PRBS Address + // + // e.g PRBS_SADDR_MASK_POS = 32'h0000_7000 the bit 14:12 of PRBS_SADDR will be ORed with + // PRBS_SADDR = 32'h0000_5000 the LFSR[14:12] to add the starting address offset. + + // PRBS_EADDR = 32'h0000_7fff + // PRBS_EADDR_MASK_POS = 32'hffff_7000 => mark all the leading 0's in PRBS_EADDR to 1 to + // zero out the LFSR[31:15] + + parameter PRBS_EADDR_MASK_POS = 32'hFFFFD000, + parameter PRBS_SADDR_MASK_POS = 32'h00002000, + parameter PRBS_EADDR = 32'h00002000, + parameter PRBS_SADDR = 32'h00005000, + parameter EYE_TEST = "FALSE" // set EYE_TEST = "TRUE" to probe memory signals. + // Traffic Generator will only write to one single location and no + // read transactions will be generated. + + + ) + + ( + + input clk_i, + input rst_i, + input run_traffic_i, + input manual_clear_error, + // *** runtime parameter *** + input [31:0] start_addr_i, // define the start of address + input [31:0] end_addr_i, // define upper limit addressboundary + input [31:0] cmd_seed_i, // seed for cmd PRBS generators + input [31:0] data_seed_i, // data seed will be added to generated address + // for PRBS data generation + // seed for cmd PRBS generators + input load_seed_i, // when asserted the cmd_seed and data_seed inputs will be registered. + + // upper layer inputs to determine the command bus and data pattern + // internal traffic generator initialize the memory with + input [2:0] addr_mode_i, // "00" = bram; takes the address from bram interface + // "01" = fixed address from the fixed_addr input + // "10" = psuedo ramdom pattern; generated from internal 64 bit LFSR + // "11" = sequential + + + // for each instr_mode, traffic gen fill up with a predetermined pattern before starting the instr_pattern that defined + // in the instr_mode input. The runtime mode will be automatically loaded inside when it is in + input [3:0] instr_mode_i, // "0000" = Fixed + // "0001" = bram; takes instruction from bram output + // "0010" = R/W + // "0011" = RP/WP + // "0100" = R/RP/W/WP + // "0101" = R/RP/W/WP/REF + // "0110" = PRBS + + + input [1:0] bl_mode_i, // "00" = bram; takes the burst length from bram output + // "01" = fixed , takes the burst length from the fixed_bl input + // "10" = psuedo ramdom pattern; generated from internal 16 bit LFSR + + input [3:0] data_mode_i, // "000" = address as data + // "001" = hammer + // "010" = neighbour + // "011" = prbs + // "100" = walking 0's + // "101" = walking 1's + // "110" = + // "111" = + + input mode_load_i, + + // fixed pattern inputs interface + input [5:0] fixed_bl_i, // range from 1 to 64 + input [2:0] fixed_instr_i, //RD 3'b001 + //RDP 3'b011 + //WR 3'b000 + //WRP 3'b010 + //REFRESH 3'b100 + + + input [31:0] fixed_addr_i, // only upper 30 bits will be used + input [DWIDTH-1:0] fixed_data_i, // + + // BRAM interface. + // bram bus formats: + // Only SP6 has been tested. + input [38:0] bram_cmd_i, // {{bl}, {cmd}, {address[28:2]}} + input bram_valid_i, + output bram_rdy_o, // + + ///////////////////////////////////////////////////////////////////////////// + // MCB INTERFACE + // interface to mcb command port + output mcb_cmd_en_o, + output [2:0] mcb_cmd_instr_o, + output [ADDR_WIDTH-1:0] mcb_cmd_addr_o, + output [5:0] mcb_cmd_bl_o, // this output is for Spartan 6 + + input mcb_cmd_full_i, + + // interface to mcb wr data port + output mcb_wr_en_o, + output [DWIDTH-1:0] mcb_wr_data_o, + output mcb_wr_data_end_o, + output [(DWIDTH/8) - 1:0] mcb_wr_mask_o, + + input mcb_wr_full_i, + input [6:0] mcb_wr_fifo_counts, + + // interface to mcb rd data port + output mcb_rd_en_o, + input [DWIDTH-1:0] mcb_rd_data_i, + input mcb_rd_empty_i, + input [6:0] mcb_rd_fifo_counts, + ///////////////////////////////////////////////////////////////////////////// + // status feedback + input counts_rst, + output reg [47:0] wr_data_counts, + output reg [47:0] rd_data_counts, + output cmp_error, + output cmp_data_valid, + output error, // asserted whenever the read back data is not correct. + output [64 + (2*DWIDTH - 1):0] error_status ,// TBD how signals mapped + output [DWIDTH-1:0] cmp_data, + output [DWIDTH-1:0] mem_rd_data, + + + // **** V6 Signals + output [DQ_ERROR_WIDTH - 1:0] dq_error_bytelane_cmp, // V6: real time compare error byte lane + output [DQ_ERROR_WIDTH - 1:0] cumlative_dq_lane_error // V6: latched error byte lane that occure on + // first error + + + + ); + +localparam MEM_BLEN = (MEM_BURST_LEN == 4) ? 4 : + (MEM_BURST_LEN == 8) ? 8 : + 8; + + wire [DWIDTH-1:0] rdpath_rd_data_i; + wire rdpath_data_valid_i; + wire mcb_wr_en; + wire cmd2flow_valid; + wire [2:0] cmd2flow_cmd; + wire [31:0] cmd2flow_addr; + wire [5:0] cmd2flow_bl; + wire last_word_rd; + wire last_word_wr; + wire flow2cmd_rdy; + wire [31:0] wr_addr; + wire [31:0] rd_addr; + wire [5:0] wr_bl; + wire [5:0] rd_bl; + reg run_traffic_reg; +wire wr_validB, wr_valid,wr_validC; +wire [31:0] bram_addr_i; +wire [2:0] bram_instr_i; +wire [5:0] bram_bl_i; +reg AC2_G_E2,AC1_G_E1,AC3_G_E3; +reg upper_end_matched; +reg [7:0] end_boundary_addr; +reg lower_end_matched; +wire [31:0] addr_o; +wire [31:0] m_addr; +wire dcount_rst; +wire [31:0] rd_addr_error; +wire rd_rdy; +//wire cmp_error; +wire cmd_full; +wire rd_mdata_fifo_rd_en; +wire rd_mdata_fifo_empty; +wire rd_mdata_fifo_afull; +wire [DWIDTH-1:0] rd_v6_mdata; + +// +wire [31:0] cmp_addr; +wire [5:0] cmp_bl; +// synthesis attribute keep of rst_ra is "true"; +// synthesis attribute keep of rst_rb is "true"; + +reg [9:0] rst_ra,rst_rb; +// synthesis attribute keep of mcb_wr_full_r1 is "true"; +// synthesis attribute keep of mcb_wr_full_r2 is "true"; + +reg mcb_wr_full_r1,mcb_wr_full_r2; +reg mcb_rd_empty_r; +wire force_wrcmd_gen; +wire [6:0] rd_buff_avail; + +reg [3:0] data_mode_r_a; +reg [3:0] data_mode_r_b; +reg [3:0] data_mode_r_c; +reg rd_mdata_afull_set; +reg error_access_range = 1'b0; + //synthesis translate_off + + initial begin + if((MEM_BURST_LEN !== 4) && (MEM_BURST_LEN !== 8)) begin + $display("Current Traffic Generator logic does not support OTF (On The Fly) Burst Mode!"); + $display("If memory is set to OTF (On The Fly) , Traffic Generator only generates BL8 traffic"); + + end + end + +always @ (mcb_cmd_en_o,mcb_cmd_addr_o,mcb_cmd_bl_o,end_addr_i) + +if (mcb_cmd_en_o && (mcb_cmd_addr_o + mcb_cmd_bl_o * (DWIDTH/8)) > end_addr_i[ADDR_WIDTH-1:0]) + begin + $display("Error ! Data access beyond address range"); + error_access_range = 1'b1; + $stop; + end + + //synthesis translate_on + +wire mcb_rd_empty; +assign mcb_rd_empty = mcb_rd_empty_i; + + + + +wire mcb_wr_full; +assign mcb_wr_full = mcb_wr_full_i; + + +always @ (posedge clk_i) +begin + data_mode_r_a <= #TCQ data_mode_i; + data_mode_r_b <= #TCQ data_mode_i; + data_mode_r_c <= #TCQ data_mode_i; +end +always @ (posedge clk_i) +begin +if (rst_ra[0]) + mcb_wr_full_r1 <= #TCQ 1'b0; +else if (mcb_wr_fifo_counts >= 63) begin + mcb_wr_full_r1 <= #TCQ 1'b1; + mcb_wr_full_r2 <= #TCQ 1'b1; + end +else begin + mcb_wr_full_r1 <= #TCQ 1'b0; + mcb_wr_full_r2 <= #TCQ 1'b0; + end +end + + +always @ (posedge clk_i) +begin +if (rst_ra[0]) + mcb_rd_empty_r <= #TCQ 1'b1; + +else if (mcb_rd_fifo_counts <= 1) + mcb_rd_empty_r <= #TCQ 1'b1; +else + mcb_rd_empty_r <= #TCQ 1'b0; +end + + + +// synthesis attribute MAX_FANOUT of rst_ra is 20; +// synthesis attribute MAX_FANOUT of rst_rb is 20; + + +//reg GSR = 1'b0; + always @(posedge clk_i) + begin + rst_ra <= #TCQ {rst_i,rst_i,rst_i,rst_i,rst_i,rst_i,rst_i,rst_i,rst_i,rst_i}; + rst_rb <= #TCQ {rst_i,rst_i,rst_i,rst_i,rst_i,rst_i,rst_i,rst_i,rst_i,rst_i}; + + end + // register it . Just in case the calling modules didn't syn with clk_i + always @(posedge clk_i) + begin + run_traffic_reg <= #TCQ run_traffic_i; + end + + assign bram_addr_i = {bram_cmd_i[29:0],2'b00}; + assign bram_instr_i = bram_cmd_i[32:30]; + assign bram_bl_i[5:0] = bram_cmd_i[38:33]; + + +// +// +assign dcount_rst = counts_rst | rst_ra[0]; +always @ (posedge clk_i) +begin + if (dcount_rst) + wr_data_counts <= #TCQ 'b0; + else if (mcb_wr_en) + wr_data_counts <= #TCQ wr_data_counts + DWIDTH/8; + +end + +always @ (posedge clk_i) +begin + if (dcount_rst) + rd_data_counts <= #TCQ 'b0; + else if (mcb_rd_en_o) + rd_data_counts <= #TCQ rd_data_counts + DWIDTH/8; + +end + + + +// **** for debug +// this part of logic is to check there are no commands been duplicated or dropped +// in the cmd_flow_control logic +generate +if (SIMULATION == "TRUE") begin: cmd_check +reg fifo_error; +wire [31:0] xfer_addr; +wire cmd_fifo_rd; + +assign cmd_fifo_wr = flow2cmd_rdy & cmd2flow_valid; + +always @ (posedge clk_i) +begin +if ( mcb_cmd_en_o) + if ( xfer_addr != mcb_cmd_addr_o) + fifo_error <= #TCQ 1'b1; + else + fifo_error <= #TCQ 1'b0; + +end + +wire cmd_fifo_empty; +assign cmd_fifo_rd = mcb_cmd_en_o & ~mcb_cmd_full_i & ~cmd_fifo_empty; + + afifo # + (.TCQ (TCQ), + .DSIZE (38), + .FIFO_DEPTH (16), + .ASIZE (4), + .SYNC (1) // set the SYNC to 1 because rd_clk = wr_clk to reduce latency + + + ) + cmd_fifo + ( + .wr_clk (clk_i), + .rst (rst_ra[0]), + .wr_en (cmd_fifo_wr), + .wr_data ({cmd2flow_bl,cmd2flow_addr}), + .rd_en (cmd_fifo_rd), + .rd_clk (clk_i), + .rd_data ({xfer_cmd_bl,xfer_addr}), + .full (cmd_fifo_full), + .empty (cmd_fifo_empty) + + ); + + +end +endgenerate + +reg [31:0] end_addr_r; + always @ (posedge clk_i) + end_addr_r <= end_addr_i; + + + cmd_gen + #( + .TCQ (TCQ), + .FAMILY (FAMILY) , + .MEM_BURST_LEN (MEM_BLEN), + .PORT_MODE (PORT_MODE), + + .NUM_DQ_PINS (NUM_DQ_PINS), + .DATA_PATTERN (DATA_PATTERN), + .CMD_PATTERN (CMD_PATTERN), + .ADDR_WIDTH (ADDR_WIDTH), + .DWIDTH (DWIDTH), + .MEM_COL_WIDTH (MEM_COL_WIDTH), + .PRBS_EADDR_MASK_POS (PRBS_EADDR_MASK_POS ), + .PRBS_SADDR_MASK_POS (PRBS_SADDR_MASK_POS ), + .PRBS_EADDR (PRBS_EADDR), + .PRBS_SADDR (PRBS_SADDR ) + + ) + u_c_gen + ( + .clk_i (clk_i), + .rst_i (rst_ra), + .rd_buff_avail_i (rd_buff_avail), + .reading_rd_data_i (mcb_rd_en_o), + .force_wrcmd_gen_i (force_wrcmd_gen), + .run_traffic_i (run_traffic_reg), + .start_addr_i (start_addr_i), + .end_addr_i (end_addr_r), + .cmd_seed_i (cmd_seed_i), + .data_seed_i (data_seed_i), + .load_seed_i (load_seed_i), + .addr_mode_i (addr_mode_i), + .data_mode_i (data_mode_r_a), + + .instr_mode_i (instr_mode_i), + .bl_mode_i (bl_mode_i), + .mode_load_i (mode_load_i), + // fixed pattern inputs interface + .fixed_bl_i (fixed_bl_i), + .fixed_addr_i (fixed_addr_i), + .fixed_instr_i (fixed_instr_i), + // BRAM FIFO input : Holist vector inputs + + .bram_addr_i (bram_addr_i), + .bram_instr_i (bram_instr_i ), + .bram_bl_i (bram_bl_i ), + .bram_valid_i (bram_valid_i ), + .bram_rdy_o (bram_rdy_o ), + + .rdy_i (flow2cmd_rdy), + .instr_o (cmd2flow_cmd), + .addr_o (cmd2flow_addr), + .bl_o (cmd2flow_bl), +// .m_addr_o (m_addr), + .cmd_o_vld (cmd2flow_valid) + + ); + +assign mcb_cmd_addr_o = addr_o[ADDR_WIDTH-1:0]; + + + +assign cmd_full = mcb_cmd_full_i; + mcb_flow_control # + ( + .TCQ (TCQ), + .FAMILY (FAMILY) + + ) + mcb_control + ( + .clk_i (clk_i), + .rst_i (rst_ra), + + .cmd_rdy_o (flow2cmd_rdy), + .cmd_valid_i (cmd2flow_valid), + .cmd_i (cmd2flow_cmd), + .addr_i (cmd2flow_addr), + .bl_i (cmd2flow_bl), + // interface to mcb_cmd port + .mcb_cmd_full (cmd_full),// (~rd_rdy ), // mcb_cmd_full +// .mcb_cmd_empty ( ), + .cmd_o (mcb_cmd_instr_o), + .addr_o (addr_o),//(mcb_cmd_instr_o), + .bl_o (mcb_cmd_bl_o), + .cmd_en_o (mcb_cmd_en_o),//(mcb_cmd_bl_o), + // interface to write data path module + + .last_word_wr_i (last_word_wr), + .wdp_rdy_i (wr_rdy),//(wr_rdy), + .wdp_valid_o (wr_valid), + .wdp_validB_o (wr_validB), + .wdp_validC_o (wr_validC), + + .wr_addr_o (wr_addr), + .wr_bl_o (wr_bl), + // interface to read data path module + + .last_word_rd_i (last_word_rd), + .rdp_rdy_i (rd_rdy),// (rd_rdy), + .rdp_valid_o (rd_valid), + .rd_addr_o (rd_addr), + .rd_bl_o (rd_bl) + + ); + + + afifo # + ( + + .TCQ (TCQ), + .DSIZE (DWIDTH), + .FIFO_DEPTH (32), + .ASIZE (5), + .SYNC (1) // set the SYNC to 1 because rd_clk = wr_clk to reduce latency + + + ) + rd_mdata_fifo + ( + .wr_clk (clk_i), + .rst (rst_rb[0]), + .wr_en (!mcb_rd_empty), + .wr_data (mcb_rd_data_i), + .rd_en (mcb_rd_en_o), + .rd_clk (clk_i), + .rd_data (rd_v6_mdata), + .full (), + .almost_full (rd_mdata_fifo_afull), + .empty (rd_mdata_fifo_empty) + + ); + + +wire cmd_rd_en; + +always @ (posedge clk_i) +begin +if (rst_rb[0]) + rd_mdata_afull_set <= #TCQ 1'b0; +else if (rd_mdata_fifo_afull) + rd_mdata_afull_set <= #TCQ 1'b1; +end +assign cmd_rd_en = ~mcb_cmd_full_i & mcb_cmd_en_o; + + +assign rdpath_data_valid_i =(FAMILY == "VIRTEX6" && MEM_BLEN == 4) ? (!rd_mdata_fifo_empty & rd_mdata_afull_set) :!mcb_rd_empty ; +assign rdpath_rd_data_i =(FAMILY == "VIRTEX6" && MEM_BLEN == 4) ? rd_v6_mdata : mcb_rd_data_i ; + +generate +if (PORT_MODE == "RD_MODE" || PORT_MODE == "BI_MODE") begin : RD_PATH + read_data_path + #( + .TCQ (TCQ), + .FAMILY (FAMILY) , + .MEM_BURST_LEN (MEM_BLEN), + + .CMP_DATA_PIPE_STAGES (CMP_DATA_PIPE_STAGES), + .ADDR_WIDTH (ADDR_WIDTH), + .SEL_VICTIM_LINE (SEL_VICTIM_LINE), + .DATA_PATTERN (DATA_PATTERN), + .DWIDTH (DWIDTH), + .NUM_DQ_PINS (NUM_DQ_PINS), + .DQ_ERROR_WIDTH (DQ_ERROR_WIDTH), + .MEM_COL_WIDTH (MEM_COL_WIDTH) + + ) + read_data_path + ( + .clk_i (clk_i), + .rst_i (rst_rb), + .manual_clear_error (manual_clear_error), + .cmd_rdy_o (rd_rdy), + .cmd_valid_i (rd_valid), + .prbs_fseed_i (data_seed_i), + .cmd_sent (mcb_cmd_instr_o), + .bl_sent (mcb_cmd_bl_o), + .cmd_en_i (cmd_rd_en), + + .data_mode_i (data_mode_r_b), + .last_word_rd_o (last_word_rd), +// .m_addr_i (m_addr), + .fixed_data_i (fixed_data_i), + + .addr_i (rd_addr), + .bl_i (rd_bl), + .data_rdy_o (mcb_rd_en_o), + + .data_valid_i (rdpath_data_valid_i), + .data_i (rdpath_rd_data_i), + + + .data_error_o (cmp_error), + .cmp_data_valid (cmp_data_valid), + .cmp_data_o (cmp_data), + .rd_mdata_o (mem_rd_data ), + .cmp_addr_o (cmp_addr), + .cmp_bl_o (cmp_bl), + .force_wrcmd_gen_o (force_wrcmd_gen), + .rd_buff_avail_o (rd_buff_avail), + .dq_error_bytelane_cmp (dq_error_bytelane_cmp), + .cumlative_dq_lane_error_r (cumlative_dq_lane_error) + + ); + +end +else begin: WR_ONLY_PATH + + assign cmp_error = 1'b0; +end +endgenerate + + + + + +generate +if (PORT_MODE == "WR_MODE" || PORT_MODE == "BI_MODE") begin : WR_PATH + + write_data_path + #( + + .TCQ (TCQ), + .FAMILY (FAMILY), + .MEM_BURST_LEN (MEM_BLEN), + .ADDR_WIDTH (ADDR_WIDTH), + .DATA_PATTERN (DATA_PATTERN), + .DWIDTH (DWIDTH), + .NUM_DQ_PINS (NUM_DQ_PINS), + .SEL_VICTIM_LINE (SEL_VICTIM_LINE), + .MEM_COL_WIDTH (MEM_COL_WIDTH), + .EYE_TEST (EYE_TEST) + + ) + write_data_path + ( + .clk_i(clk_i), + .rst_i (rst_rb), + .cmd_rdy_o (wr_rdy), + .cmd_valid_i (wr_valid), + .cmd_validB_i (wr_validB), + .cmd_validC_i (wr_validC), + .prbs_fseed_i (data_seed_i), + .data_mode_i (data_mode_r_c), + .last_word_wr_o (last_word_wr), +// .m_addr_i (m_addr),//(rd_addr), + .fixed_data_i (fixed_data_i), + .addr_i (wr_addr), + .bl_i (wr_bl), + .data_rdy_i (!mcb_wr_full), + .data_valid_o (mcb_wr_en), + .data_o (mcb_wr_data_o), + .data_mask_o (mcb_wr_mask_o), + .data_wr_end_o (mcb_wr_data_end_o) + ); + +end +endgenerate + +assign mcb_wr_en_o = mcb_wr_en; + + + + tg_status + #( + + .TCQ (TCQ), + .DWIDTH (DWIDTH) + ) + tg_status + ( + .clk_i (clk_i), + .rst_i (rst_ra[2]), + .manual_clear_error (manual_clear_error), + .data_error_i (cmp_error), + .cmp_data_i (cmp_data), + .rd_data_i (mem_rd_data ), + .cmp_addr_i (cmp_addr), + .cmp_bl_i (cmp_bl), + .mcb_cmd_full_i (mcb_cmd_full_i), + .mcb_wr_full_i (mcb_wr_full), // mcb_wr_full_r2 ??? + .mcb_rd_empty_i (mcb_rd_empty), + .error_status (error_status), + .error (error) + ); + + +endmodule // mcb_traffic_gen diff --git "a/Frogwells_fpga_design/\345\237\272\344\272\216FPGA\343\200\201DDR3\345\222\214USB2.0\347\232\204\345\233\276\345\203\217\351\207\207\351\233\206\347\263\273\347\273\237/debug/ddr_test/rtl/traffic_gen/rd_data_gen.v" "b/Frogwells_fpga_design/\345\237\272\344\272\216FPGA\343\200\201DDR3\345\222\214USB2.0\347\232\204\345\233\276\345\203\217\351\207\207\351\233\206\347\263\273\347\273\237/debug/ddr_test/rtl/traffic_gen/rd_data_gen.v" new file mode 100644 index 0000000000000000000000000000000000000000..31885fc5a848eb409a1a8290134c346af42d0417 --- /dev/null +++ "b/Frogwells_fpga_design/\345\237\272\344\272\216FPGA\343\200\201DDR3\345\222\214USB2.0\347\232\204\345\233\276\345\203\217\351\207\207\351\233\206\347\263\273\347\273\237/debug/ddr_test/rtl/traffic_gen/rd_data_gen.v" @@ -0,0 +1,343 @@ +//***************************************************************************** +// (c) Copyright 2008-2009 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: %version +// \ \ Application: MIG +// / / Filename: rd_data_gen.v +// /___/ /\ Date Last Modified: +// \ \ / \ Date Created: +// \___\/\___\ +// +//Device: Spartan6 +//Design Name: DDR/DDR2/DDR3/LPDDR +//Purpose: This module has all the timing control for generating "compare data" +// to compare the read data from memory. +//Reference: +//Revision History: +//***************************************************************************** + +`timescale 1ps/1ps + +module rd_data_gen # + ( + parameter TCQ = 100, + parameter FAMILY = "SPARTAN6", // "SPARTAN6", "VIRTEX6" + parameter MEM_BURST_LEN = 8, + + parameter ADDR_WIDTH = 32, + parameter BL_WIDTH = 6, + parameter DWIDTH = 32, + parameter DATA_PATTERN = "DGEN_ALL", //"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL" + parameter NUM_DQ_PINS = 8, + parameter SEL_VICTIM_LINE = 3, // VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern + + parameter COLUMN_WIDTH = 10 + + ) + ( + input clk_i, // + input [4:0] rst_i, + input [31:0] prbs_fseed_i, + input [3:0] data_mode_i, // "00" = bram; + + output cmd_rdy_o, // ready to receive command. It should assert when data_port is ready at the // beginning and will be deasserted once see the cmd_valid_i is asserted. + // And then it should reasserted when + // it is generating the last_word. + input cmd_valid_i, // when both cmd_valid_i and cmd_rdy_o is high, the command is valid. + output last_word_o, + +// input [ADDR_WIDTH-1:0] m_addr_i, // generated address used to determine data pattern. + input [DWIDTH-1:0] fixed_data_i, + input [ADDR_WIDTH-1:0] addr_i, // generated address used to determine data pattern. + input [BL_WIDTH-1:0] bl_i, // generated burst length for control the burst data + output user_bl_cnt_is_1_o, + input data_rdy_i, // connect from mcb_wr_full when used as wr_data_gen in sp6 + // connect from mcb_rd_empty when used as rd_data_gen in sp6 + // connect from rd_data_valid in v6 + // When both data_rdy and data_valid is asserted, the ouput data is valid. + output reg data_valid_o, // connect to wr_en or rd_en and is asserted whenever the + // pattern is available. + output [DWIDTH-1:0] data_o, // generated data pattern + input rd_mdata_en +); +// + + + +wire [31:0] prbs_data; +reg cmd_start; +reg [31:0] adata; +reg [31:0] hdata; +reg [31:0] ndata; +reg [31:0] w1data; +reg [NUM_DQ_PINS*4-1:0] v6_w1data; + +reg [31:0] w0data; +reg [DWIDTH-1:0] data; +reg cmd_rdy; +reg data_valid; +reg [6:0]user_burst_cnt; +reg data_rdy_r1,data_rdy_r2; +reg next_count_is_one; +reg cmd_valid_r1; +reg [31:0] w3data; + +assign data_port_fifo_rdy = data_rdy_i; + +//assign cmd_start = cmd_valid_i & cmd_rdy ; +always @ (posedge clk_i) +begin + data_rdy_r1 <= #TCQ data_rdy_i; + data_rdy_r2 <= #TCQ data_rdy_r1; + cmd_valid_r1 <= #TCQ cmd_valid_i; +end + +always @ (posedge clk_i) +begin +if (user_burst_cnt == 2 && data_rdy_i) + next_count_is_one <= #TCQ 1'b1; +else + next_count_is_one <= #TCQ 1'b0; +end + +reg user_bl_cnt_is_1; +assign user_bl_cnt_is_1_o = user_bl_cnt_is_1; +always @ (posedge clk_i) +begin +if ((user_burst_cnt == 2 && data_port_fifo_rdy && FAMILY == "SPARTAN6") + || (user_burst_cnt == 2 && data_port_fifo_rdy && FAMILY == "VIRTEX6") + ) + + user_bl_cnt_is_1 <= #TCQ 1'b1; +else + user_bl_cnt_is_1 <= #TCQ 1'b0; +end + + +reg cmd_start_b; +always @(cmd_valid_i,cmd_valid_r1,cmd_rdy,user_bl_cnt_is_1,rd_mdata_en) +begin + if (FAMILY == "SPARTAN6") begin + cmd_start = cmd_valid_i & cmd_rdy ; + cmd_start_b = cmd_valid_i & cmd_rdy ; + end + else if (MEM_BURST_LEN == 4 && FAMILY == "VIRTEX6") begin + cmd_start = rd_mdata_en; // need to wait for extra cycle for data coming out from rd_post_fifo in V6 interface + cmd_start_b = rd_mdata_en; // need to wait for extra cycle for data coming out from rd_post_fifo in V6 interface + end + else if (MEM_BURST_LEN == 8 && FAMILY == "VIRTEX6") begin + + cmd_start = (~cmd_valid_r1 & cmd_valid_i) | user_bl_cnt_is_1; // need to wait for extra cycle for data coming out from rd_post_fifo in V6 interface + cmd_start_b = (~cmd_valid_r1 & cmd_valid_i) | user_bl_cnt_is_1; // need to wait for extra cycle for data coming out from rd_post_fifo in V6 interface + end + +end + + +// counter to count user burst length +always @( posedge clk_i) +begin + if ( rst_i[0] ) + user_burst_cnt <= #TCQ 'd0; + else if(cmd_start) begin + if (bl_i == 6'b000000) + user_burst_cnt <= #TCQ 7'b1000000; + else + user_burst_cnt <= #TCQ bl_i; + end + else if(data_port_fifo_rdy) + if (user_burst_cnt != 6'd0) + user_burst_cnt <= #TCQ user_burst_cnt - 1'b1; + else + user_burst_cnt <= #TCQ 'd0; + +end + +reg u_bcount_2; +always @ (posedge clk_i) +begin +if ((user_burst_cnt == 2 && data_rdy_i )|| (cmd_start && bl_i == 1)) + u_bcount_2 <= #TCQ 1'b1; +else if (last_word_o) + u_bcount_2 <= #TCQ 1'b0; +end + +assign last_word_o = u_bcount_2 & data_rdy_i; + + + + +// cmd_rdy_o assert when the dat fifo is not full and deassert once cmd_valid_i +// is assert and reassert during the last data + +//data_valid_o logic + + + +assign cmd_rdy_o = cmd_rdy; + +always @( posedge clk_i) +begin + if ( rst_i[0] ) + cmd_rdy <= #TCQ 1'b1; + else if (cmd_start) + cmd_rdy <= #TCQ 1'b0; + else if ((data_port_fifo_rdy && user_burst_cnt == 1)) + cmd_rdy <= #TCQ 1'b1; + + +end + + + +always @ (posedge clk_i) +begin + if (rst_i[0]) + data_valid <= #TCQ 'd0; + else if (user_burst_cnt == 6'd1 && data_port_fifo_rdy) + data_valid <= #TCQ 1'b0; + else if(( user_burst_cnt >= 6'd1) || cmd_start) + data_valid <= #TCQ 1'b1; +end + + +always @ (data_valid, data_port_fifo_rdy) +if (FAMILY == "SPARTAN6") + data_valid_o = data_valid; +else + data_valid_o = data_port_fifo_rdy; + + + +generate +if (FAMILY == "SPARTAN6") begin : SP6_DGEN +sp6_data_gen # + +( + .TCQ (TCQ), + .ADDR_WIDTH (32 ), + .BL_WIDTH (BL_WIDTH ), + .DWIDTH (DWIDTH ), + .DATA_PATTERN (DATA_PATTERN ), + .NUM_DQ_PINS (NUM_DQ_PINS ), + .COLUMN_WIDTH (COLUMN_WIDTH) + + ) + sp6_data_gen + ( + .clk_i (clk_i ), + .rst_i (rst_i[1] ), + .data_rdy_i (data_rdy_i ), + .prbs_fseed_i (prbs_fseed_i), + + .data_mode_i (data_mode_i ), + .cmd_startA (cmd_start ), + .cmd_startB (cmd_start ), + .cmd_startC (cmd_start ), + .cmd_startD (cmd_start ), + .cmd_startE (cmd_start ), + .fixed_data_i (fixed_data_i), + + .addr_i (addr_i ), + .user_burst_cnt (user_burst_cnt), + .fifo_rdy_i (data_port_fifo_rdy ), + .data_o (data_o ) + ); + +end +endgenerate +generate +if (FAMILY == "VIRTEX6") begin : V6_DGEN +v6_data_gen # + +( + .TCQ (TCQ), + .ADDR_WIDTH (32 ), + .BL_WIDTH (BL_WIDTH ), + .MEM_BURST_LEN (MEM_BURST_LEN), + .DWIDTH (DWIDTH ), + .DATA_PATTERN (DATA_PATTERN ), + .NUM_DQ_PINS (NUM_DQ_PINS ), + .SEL_VICTIM_LINE (SEL_VICTIM_LINE), + + .COLUMN_WIDTH (COLUMN_WIDTH) + + ) + v6_data_gen + ( + .clk_i (clk_i ), + .rst_i (rst_i[1] ), + .data_rdy_i (data_rdy_i ), + .prbs_fseed_i (prbs_fseed_i), + + .data_mode_i (data_mode_i ), + .cmd_startA (cmd_start ), + .cmd_startB (cmd_start ), + .cmd_startC (cmd_start ), + .cmd_startD (cmd_start ), + .cmd_startE (cmd_start ), + .m_addr_i (addr_i),//(m_addr_i ), + .fixed_data_i (fixed_data_i), + + .addr_i (addr_i ), + .user_burst_cnt (user_burst_cnt), + .fifo_rdy_i (data_port_fifo_rdy ), + .data_o (data_o ) + ); + +end +endgenerate + + + + + +endmodule diff --git "a/Frogwells_fpga_design/\345\237\272\344\272\216FPGA\343\200\201DDR3\345\222\214USB2.0\347\232\204\345\233\276\345\203\217\351\207\207\351\233\206\347\263\273\347\273\237/debug/ddr_test/rtl/traffic_gen/read_data_path.v" "b/Frogwells_fpga_design/\345\237\272\344\272\216FPGA\343\200\201DDR3\345\222\214USB2.0\347\232\204\345\233\276\345\203\217\351\207\207\351\233\206\347\263\273\347\273\237/debug/ddr_test/rtl/traffic_gen/read_data_path.v" new file mode 100644 index 0000000000000000000000000000000000000000..8ce533a895d0fdbbcf303d72b0ce54b1ca83b056 --- /dev/null +++ "b/Frogwells_fpga_design/\345\237\272\344\272\216FPGA\343\200\201DDR3\345\222\214USB2.0\347\232\204\345\233\276\345\203\217\351\207\207\351\233\206\347\263\273\347\273\237/debug/ddr_test/rtl/traffic_gen/read_data_path.v" @@ -0,0 +1,513 @@ +//***************************************************************************** +// (c) Copyright 2008-2009 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: %version +// \ \ Application: MIG +// / / Filename: read_data_path.v +// /___/ /\ Date Last Modified: +// \ \ / \ Date Created: +// \___\/\___\ +// +//Device: Spartan6 +//Design Name: DDR/DDR2/DDR3/LPDDR +//Purpose: This is top level of read path and also consist of comparison logic +// for read data. +//Reference: +//Revision History: +//***************************************************************************** + +`timescale 1ps/1ps + +module read_data_path #( + parameter TCQ = 100, + + parameter FAMILY = "VIRTEX6", + parameter MEM_BURST_LEN = 8, + parameter ADDR_WIDTH = 32, + parameter CMP_DATA_PIPE_STAGES = 3, + parameter DWIDTH = 32, + parameter DATA_PATTERN = "DGEN_ALL", //"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL" + parameter NUM_DQ_PINS = 8, + parameter DQ_ERROR_WIDTH = 1, + parameter SEL_VICTIM_LINE = 3, // VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern + + parameter MEM_COL_WIDTH = 10 + + ) + ( + + + input clk_i, + input [9:0] rst_i, + input manual_clear_error, + output cmd_rdy_o, + input cmd_valid_i, + input [31:0] prbs_fseed_i, + + input [3:0] data_mode_i, + input [2:0] cmd_sent, + input [5:0] bl_sent , + input cmd_en_i , +// input [31:0] m_addr_i, + input [DWIDTH-1:0] fixed_data_i, + input [31:0] addr_i, + input [5:0] bl_i, + + + output data_rdy_o, + input data_valid_i, + input [DWIDTH-1:0] data_i, + output last_word_rd_o, + output data_error_o, //data_error on user data bus side + output [DWIDTH-1:0] cmp_data_o, + output [DWIDTH-1:0] rd_mdata_o , + output cmp_data_valid, + output [31:0] cmp_addr_o, + output [5 :0] cmp_bl_o, + output force_wrcmd_gen_o, + output [6:0] rd_buff_avail_o, + output [DQ_ERROR_WIDTH - 1:0] dq_error_bytelane_cmp, // V6: real time compare error byte lane + output [DQ_ERROR_WIDTH - 1:0] cumlative_dq_lane_error_r // V6: latched error byte lane that occure on + // first error + + ); + + wire gen_rdy; + wire gen_valid; + wire [31:0] gen_addr; + wire [5:0] gen_bl; + + wire cmp_rdy; + wire cmp_valid; + wire [31:0] cmp_addr; + wire [5:0] cmp_bl; + + reg data_error; + wire [DWIDTH-1:0] cmp_data; + reg [DWIDTH-1:0] cmp_data_r; + reg [DWIDTH-1:0] cmp_data_r2; + reg [DWIDTH-1:0] cmp_data_r3; + reg [DWIDTH-1:0] cmp_data_r4; + reg last_word_rd; + reg [5:0] bl_counter; + wire cmd_rdy; + wire user_bl_cnt_is_1; + wire data_rdy; + reg [DWIDTH:0] delayed_data; + wire rd_mdata_en; + reg [DWIDTH-1:0] rd_data_r; + reg [DWIDTH-1:0] rd_data_r2; + reg [DWIDTH-1:0] rd_data_r3; + reg [DWIDTH-1:0] rd_data_r4; + reg force_wrcmd_gen; + reg wait_bl_end; + reg wait_bl_end_r1; +reg l_data_error ; +reg u_data_error; +reg v6_data_cmp_valid; +wire [DWIDTH -1 :0] rd_v6_mdata; +reg [DWIDTH -1 :0] rd_v6_mdata_r1; +reg [DWIDTH -1 :0] rd_v6_mdata_r2; +reg [DWIDTH -1 :0] rd_v6_mdata_r3; +reg [DWIDTH -1 :0] rd_v6_mdata_r4; +reg [DWIDTH -1 :0] cmpdata_r; +wire [DWIDTH -1 :0] rd_mdata; +wire rd_mdata_fifo_empty; + reg cmp_data_en; + + +wire [ DQ_ERROR_WIDTH-1:0] dq_lane_error; +reg [ DQ_ERROR_WIDTH-1:0] dq_lane_error_r1; +reg [ DQ_ERROR_WIDTH-1:0] dq_lane_error_r2; +wire [ DQ_ERROR_WIDTH-1:0] cum_dq_lane_error_mask; +wire [ DQ_ERROR_WIDTH-1:0] cumlative_dq_lane_error_c; +reg [ DQ_ERROR_WIDTH-1:0] cumlative_dq_lane_error_reg; + +reg data_valid_r; + + + always @ (posedge clk_i) begin + wait_bl_end_r1 <= #TCQ wait_bl_end; + rd_data_r <= #TCQ data_i; + rd_data_r2 <= #TCQ rd_data_r; + rd_data_r3 <= #TCQ rd_data_r2; + rd_data_r4 <= #TCQ rd_data_r3; + end + + assign force_wrcmd_gen_o = force_wrcmd_gen; + reg [7:0] force_wrcmd_timeout_cnts ; + + always @ (posedge clk_i) begin + if (rst_i[0]) + force_wrcmd_gen <= #TCQ 1'b0; + else if ((wait_bl_end == 1'b0 && wait_bl_end_r1 == 1'b1) || force_wrcmd_timeout_cnts == 8'b11111111) + force_wrcmd_gen <= #TCQ 1'b0; + + else if ((cmd_valid_i && bl_i > 16) || wait_bl_end ) + force_wrcmd_gen <= #TCQ 1'b1; + end + + + always @ (posedge clk_i) begin + if (rst_i[0]) + force_wrcmd_timeout_cnts <= #TCQ 'b0; + else if (wait_bl_end == 1'b0 && wait_bl_end_r1 == 1'b1) + force_wrcmd_timeout_cnts <= #TCQ 'b0; + + else if (force_wrcmd_gen) + force_wrcmd_timeout_cnts <= #TCQ force_wrcmd_timeout_cnts + 1; + end + + always @ (posedge clk_i) + if (rst_i[0]) + wait_bl_end <= #TCQ 1'b0; + else if (force_wrcmd_timeout_cnts == 8'b11111111) + wait_bl_end <= #TCQ 1'b0; + + else if (gen_rdy && gen_valid && gen_bl > 16) + wait_bl_end <= #TCQ 1'b1; + else if (wait_bl_end && user_bl_cnt_is_1) + wait_bl_end <= #TCQ 1'b0; + + + assign cmd_rdy_o = cmd_rdy; + read_posted_fifo #( + .TCQ (TCQ), + .FAMILY (FAMILY), + .MEM_BURST_LEN (MEM_BURST_LEN), + .ADDR_WIDTH(32), + .BL_WIDTH(6) + ) + read_postedfifo( + .clk_i (clk_i), + .rst_i (rst_i[0]), + .cmd_rdy_o (cmd_rdy ), + .cmd_valid_i (cmd_valid_i ), + .data_valid_i (data_rdy ), // input to + .addr_i (addr_i ), + .bl_i (bl_i ), + + .cmd_sent (cmd_sent), + .bl_sent (bl_sent ), + .cmd_en_i (cmd_en_i), + + .user_bl_cnt_is_1 (user_bl_cnt_is_1), + .gen_rdy_i (gen_rdy ), + .gen_valid_o (gen_valid ), + .gen_addr_o (gen_addr ), + .gen_bl_o (gen_bl ), + .rd_buff_avail_o (rd_buff_avail_o), + .rd_mdata_fifo_empty (rd_mdata_fifo_empty), + .rd_mdata_en (rd_mdata_en) + ); + + + + + rd_data_gen #( + .TCQ (TCQ), + .FAMILY (FAMILY), + .MEM_BURST_LEN (MEM_BURST_LEN), + .NUM_DQ_PINS (NUM_DQ_PINS), + .SEL_VICTIM_LINE (SEL_VICTIM_LINE), + + .DATA_PATTERN (DATA_PATTERN), + .DWIDTH(DWIDTH), + .COLUMN_WIDTH (MEM_COL_WIDTH) + + ) + rd_datagen( + .clk_i (clk_i ), + .rst_i (rst_i[4:0]), + .prbs_fseed_i (prbs_fseed_i), + .data_mode_i (data_mode_i ), + .cmd_rdy_o (gen_rdy ), + .cmd_valid_i (gen_valid ), + .last_word_o (last_word_rd_o ), + +// .m_addr_i (m_addr_i ), + .fixed_data_i (fixed_data_i), + + .addr_i (gen_addr ), + .bl_i (gen_bl ), + .user_bl_cnt_is_1_o (user_bl_cnt_is_1), + .data_rdy_i (data_valid_i ), // input to + .data_valid_o (cmp_valid ), + .data_o (cmp_data ), + .rd_mdata_en (rd_mdata_en) + ); + + + afifo # + ( + .TCQ (TCQ), + .DSIZE (DWIDTH), + .FIFO_DEPTH (32), + .ASIZE (5), + .SYNC (1) // set the SYNC to 1 because rd_clk = wr_clk to reduce latency + + + ) + rd_mdata_fifo + ( + .wr_clk (clk_i), + .rst (rst_i[0]), + .wr_en (data_valid_i), + .wr_data (data_i), + .rd_en (rd_mdata_en), + .rd_clk (clk_i), + .rd_data (rd_v6_mdata), + .full (), + .empty (rd_mdata_fifo_empty), + .almost_full () + ); + +always @ (posedge clk_i) +begin +// delayed_data <= #TCQ {cmp_valid & data_valid_i,cmp_data}; + cmp_data_r <= #TCQ cmp_data; + cmp_data_r2 <= #TCQ cmp_data_r; + cmp_data_r3 <= #TCQ cmp_data_r2; + cmp_data_r4 <= #TCQ cmp_data_r3; +end + +assign rd_mdata_o = rd_mdata; + +assign rd_mdata = (FAMILY == "SPARTAN6") ? rd_data_r3: + (FAMILY == "VIRTEX6" && MEM_BURST_LEN == 4)? rd_v6_mdata_r2: + rd_data_r; + +assign cmp_data_valid = (FAMILY == "SPARTAN6") ? cmp_data_en : + (FAMILY == "VIRTEX6" && MEM_BURST_LEN == 4)? v6_data_cmp_valid :data_valid_i; + + + + +assign cmp_data_o = (FAMILY == "SPARTAN6") ? cmp_data_r3 : cmp_data_r2; +assign cmp_addr_o = gen_addr; +assign cmp_bl_o = gen_bl; + + + +assign data_rdy_o = data_rdy; +assign data_rdy = cmp_valid & data_valid_i; + + always @ (posedge clk_i) + v6_data_cmp_valid <= #TCQ rd_mdata_en; + + + always @ (posedge clk_i) + cmp_data_en <= #TCQ data_rdy; + + generate + if (FAMILY == "SPARTAN6") begin: gen_error_1 + always @ (posedge clk_i) + begin + if (cmp_data_en) + l_data_error <= #TCQ (rd_data_r[DWIDTH/2-1:0] !== cmp_data_r[DWIDTH/2-1:0]); + else + l_data_error <= #TCQ 1'b0; + + if (cmp_data_en) + u_data_error <= #TCQ (rd_data_r[DWIDTH-1:DWIDTH/2] !== cmp_data_r[DWIDTH-1:DWIDTH/2]); + else + u_data_error <= #TCQ 1'b0; + + data_error <= #TCQ l_data_error | u_data_error; + //synthesis translate_off + if (data_error) + $display ("ERROR: Expected data=%h and recieved data= %h @ %t" ,cmp_data_r4, rd_data_r4, $time); + //synthesis translate_on + + end + +end +endgenerate +wire [NUM_DQ_PINS/2 - 1:0] error_byte; +reg [NUM_DQ_PINS/2 - 1:0] error_byte_r1; + +genvar i; + generate + if (FAMILY == "VIRTEX6" && MEM_BURST_LEN == 4) begin: gen_error_2 + + + for (i = 0; i < NUM_DQ_PINS/2; i = i + 1) begin: gen_cmp + assign error_byte[i] + = (~rd_mdata_fifo_empty && rd_mdata_en && (rd_v6_mdata[8*(i+1)-1:8*i] !== cmp_data[8*(i+1)-1:8*i]) ); + + + end + +always @ (posedge clk_i) +begin + rd_v6_mdata_r1 <= rd_v6_mdata; + rd_v6_mdata_r2 <= rd_v6_mdata_r1; + rd_v6_mdata_r3 <= rd_v6_mdata_r2; + rd_v6_mdata_r4 <= rd_v6_mdata_r3; +end + +always @ (posedge clk_i) +begin + if (rst_i[1] || manual_clear_error) begin + + error_byte_r1 <= #TCQ 'b0; + data_error <= #TCQ 1'b0; + end + else begin + error_byte_r1 <= #TCQ error_byte; + data_error <= #TCQ | error_byte_r1; + + + //synthesis translate_off + if (data_error) + $display ("ERROR: Expected data=%h and recieved data= %h @ %t" ,cmp_data_r2,rd_v6_mdata_r2,$time); + //synthesis translate_on + end + +end + + // remap the app_rd_data error byte locastion to dq bus side. + for ( i = 0; i < DQ_ERROR_WIDTH; i = i+1) begin: gen_dq_error_map + assign dq_lane_error[i] = (error_byte_r1[i] | error_byte_r1[i+DQ_ERROR_WIDTH] | + error_byte_r1[i+ (NUM_DQ_PINS*2/8)] | + error_byte_r1[i+ (NUM_DQ_PINS*3/8)]); + + assign cumlative_dq_lane_error_c[i] = cumlative_dq_lane_error_r[i] | dq_lane_error_r1[i]; + end + + +always @ (posedge clk_i) +begin + if (rst_i[1] || manual_clear_error) begin + + dq_lane_error_r1 <= #TCQ 'b0; + dq_lane_error_r2 <= #TCQ 'b0; + data_valid_r <= #TCQ 1'b0; + cumlative_dq_lane_error_reg <= #TCQ 'b0; + end + else begin + data_valid_r <= #TCQ data_valid_i; + + dq_lane_error_r1 <= #TCQ dq_lane_error; + cumlative_dq_lane_error_reg <= #TCQ cumlative_dq_lane_error_c; + end +end +end +//end +endgenerate + + generate + if (FAMILY == "VIRTEX6" && MEM_BURST_LEN == 8) begin: gen_error_3 + for (i = 0; i < NUM_DQ_PINS/2; i = i + 1) begin: gen_cmp + assign error_byte[i] + = (data_valid_i && (data_i[8*(i+1)-1:8*i] !== cmp_data[8*(i+1)-1:8*i]) ); + end + + + + +always @ (posedge clk_i) +begin + if (rst_i[1] || manual_clear_error) begin + + error_byte_r1 <= #TCQ 'b0; + data_error <= #TCQ 1'b0; + end + else begin + + error_byte_r1 <= #TCQ error_byte; + data_error <= #TCQ | error_byte_r1; + + //synthesis translate_off + if (data_error) + $display ("ERROR: Expected data=%h and recieved data= %h @ %t" ,cmp_data_r2,rd_data_r2,$time); + //synthesis translate_on + + end +end + + + for ( i = 0; i < DQ_ERROR_WIDTH; i = i+1) begin: gen_dq_error_map + assign dq_lane_error[i] = (error_byte_r1[i] | error_byte_r1[i+DQ_ERROR_WIDTH] | + error_byte_r1[i+ (NUM_DQ_PINS*2/8)] | + error_byte_r1[i+ (NUM_DQ_PINS*3/8)]); + + assign cumlative_dq_lane_error_c[i] = cumlative_dq_lane_error_r[i] | dq_lane_error_r1[i]; + end + + +always @ (posedge clk_i) +begin + if (rst_i[1] || manual_clear_error) begin + + dq_lane_error_r1 <= #TCQ 'b0; + dq_lane_error_r2 <= #TCQ 'b0; + data_valid_r <= #TCQ 1'b0; + cumlative_dq_lane_error_reg <= #TCQ 'b0; + end + else begin + data_valid_r <= #TCQ data_valid_i; + dq_lane_error_r1 <= #TCQ dq_lane_error; + cumlative_dq_lane_error_reg <= #TCQ cumlative_dq_lane_error_c; + end +end +end +//end +endgenerate + +assign cumlative_dq_lane_error_r = cumlative_dq_lane_error_reg; +assign dq_error_bytelane_cmp = dq_lane_error_r1; +assign data_error_o = data_error; + + +endmodule + diff --git "a/Frogwells_fpga_design/\345\237\272\344\272\216FPGA\343\200\201DDR3\345\222\214USB2.0\347\232\204\345\233\276\345\203\217\351\207\207\351\233\206\347\263\273\347\273\237/debug/ddr_test/rtl/traffic_gen/read_posted_fifo.v" "b/Frogwells_fpga_design/\345\237\272\344\272\216FPGA\343\200\201DDR3\345\222\214USB2.0\347\232\204\345\233\276\345\203\217\351\207\207\351\233\206\347\263\273\347\273\237/debug/ddr_test/rtl/traffic_gen/read_posted_fifo.v" new file mode 100644 index 0000000000000000000000000000000000000000..3d59101289a9d5dcac82e13c661de0a3ba538aad --- /dev/null +++ "b/Frogwells_fpga_design/\345\237\272\344\272\216FPGA\343\200\201DDR3\345\222\214USB2.0\347\232\204\345\233\276\345\203\217\351\207\207\351\233\206\347\263\273\347\273\237/debug/ddr_test/rtl/traffic_gen/read_posted_fifo.v" @@ -0,0 +1,264 @@ +//***************************************************************************** +// (c) Copyright 2008-2009 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: %version +// \ \ Application: MIG +// / / Filename: read_posted_fifo.v +// /___/ /\ Date Last Modified: +// \ \ / \ Date Created: +// \___\/\___\ +// +//Device: Spartan6 +//Design Name: DDR/DDR2/DDR3/LPDDR +//Purpose: This module instantiated by read_data_path module and sits between +// mcb_flow_control module and read_data_gen module to buffer up the +// commands that has sent to memory controller. +//Reference: +//Revision History: +// 2010/01/09/ Corrected dfifo_has_enough_room threshold logic. +// It has to set higher in Read Only port. +//***************************************************************************** +`timescale 1ps/1ps + + module read_posted_fifo # + ( + parameter TCQ = 100, + parameter FAMILY = "SPARTAN6", + parameter MEM_BURST_LEN = 4, + + parameter ADDR_WIDTH = 32, + parameter BL_WIDTH = 6 + ) + ( + input clk_i, + input rst_i, + output reg cmd_rdy_o, + input cmd_valid_i, + input data_valid_i, + input [ADDR_WIDTH-1:0] addr_i, + input [BL_WIDTH-1:0] bl_i, + input user_bl_cnt_is_1, + input [2:0] cmd_sent, + input [5:0] bl_sent , + input cmd_en_i , + + + input gen_rdy_i, + output gen_valid_o, + output [ADDR_WIDTH-1:0] gen_addr_o, + output [BL_WIDTH-1:0] gen_bl_o, + output [6:0] rd_buff_avail_o, + input rd_mdata_fifo_empty, + output rd_mdata_en + + ); + +reg empty_r; +reg rd_first_data; + + wire full; + wire empty; + wire wr_en; + reg rd_en; + reg data_valid_r; + reg user_bl_cnt_not_1; + reg [6:0] buf_avail_r; + reg [6:0] rd_data_received_counts; + reg [6:0] rd_data_counts_asked; + + reg dfifo_has_enough_room; + reg [1:0] wait_cnt; + reg wait_done; + + assign rd_mdata_en = rd_en; + + assign rd_buff_avail_o = buf_avail_r; + always @ (posedge clk_i) + cmd_rdy_o <= #TCQ !full & dfifo_has_enough_room & wait_done; + + always @ (posedge clk_i) + begin + if (rst_i) + wait_cnt <= #TCQ 'b0; + else if (cmd_rdy_o && cmd_valid_i) + wait_cnt <= #TCQ 2'b10; + else if (wait_cnt > 0) + wait_cnt <= #TCQ wait_cnt - 1; + + end + + always @(posedge clk_i) + begin + if (rst_i) + wait_done <= #TCQ 1'b1; + else if (cmd_rdy_o && cmd_valid_i) + wait_done <= #TCQ 1'b0; + else if (wait_cnt == 0) + wait_done <= #TCQ 1'b1; + else + wait_done <= #TCQ 1'b0; + + end + + reg dfifo_has_enough_room_d1; + always @ (posedge clk_i) + begin // prbs_blen from cmd_gen is random, it can be two 64 in consecutive + // the logic here to prevent cmd_gen send any further read command if + // any large bl command has been sent. + + dfifo_has_enough_room <= #TCQ (buf_avail_r >= 62 ) ? 1'b1: 1'b0; + + dfifo_has_enough_room_d1 <= #TCQ dfifo_has_enough_room ; + end + + + assign wr_en = cmd_valid_i & !full & dfifo_has_enough_room_d1 & wait_done; + + + always @ (posedge clk_i) + data_valid_r <= #TCQ data_valid_i; + + + always @ (posedge clk_i) + begin + if (data_valid_i && user_bl_cnt_is_1) // current count is 1 and data_is_valie, then next cycle is not 1 + user_bl_cnt_not_1 <= #TCQ 1'b1; + else + user_bl_cnt_not_1 <= #TCQ 1'b0; + end + + always @ (posedge clk_i) + begin + if (rst_i) begin + rd_data_counts_asked <= #TCQ 'b0; + end + else if (cmd_en_i && cmd_sent[0] == 1) begin + + rd_data_counts_asked <= #TCQ rd_data_counts_asked + (bl_sent + 7'b0000001) ; + + end + end + + always @ (posedge clk_i) + begin + if (rst_i) begin + rd_data_received_counts <= #TCQ 'b0; + end + else if (data_valid_i) begin + rd_data_received_counts <= #TCQ rd_data_received_counts + 1; + end + end + + // calculate how many buf still available + always @ (posedge clk_i) + // MCB FIFO size is 64. + // buf_available is calculated by: + // FIFO DEPTH - ( Write Poitner - Read Pointer) + buf_avail_r <= #TCQ 64 - (rd_data_counts_asked - rd_data_received_counts); + + + + always @(gen_rdy_i, empty,empty_r,rd_mdata_fifo_empty,rd_first_data ,data_valid_i,data_valid_r,user_bl_cnt_not_1) + begin + if (FAMILY == "SPARTAN6") + rd_en = gen_rdy_i & !empty; + else + if ( MEM_BURST_LEN == 4) + rd_en = (~empty & empty_r & ~rd_first_data) | (~rd_mdata_fifo_empty & ~empty ) | (user_bl_cnt_not_1 & data_valid_i); + else + rd_en = (data_valid_i & ~data_valid_r) | (user_bl_cnt_not_1 & data_valid_i); + + end + + always @ (posedge clk_i) + empty_r <= #TCQ empty; + + always @ (posedge clk_i) + begin + if (rst_i) + rd_first_data <= #TCQ 1'b0; + else if (~empty && empty_r) + rd_first_data <= #TCQ 1'b1; + end + + + + assign gen_valid_o = !empty; + afifo # + ( + .TCQ (TCQ), + .DSIZE (BL_WIDTH+ADDR_WIDTH), + .FIFO_DEPTH (16), + .ASIZE (4), + .SYNC (1) // set the SYNC to 1 because rd_clk = wr_clk to reduce latency + + + ) + rd_fifo + ( + .wr_clk (clk_i), + .rst (rst_i), + .wr_en (wr_en), + .wr_data ({bl_i,addr_i}), + .rd_en (rd_en), + .rd_clk (clk_i), + .rd_data ({gen_bl_o,gen_addr_o}), + .full (full), + .empty (empty), + .almost_full () + + ); + + + + + +endmodule diff --git "a/Frogwells_fpga_design/\345\237\272\344\272\216FPGA\343\200\201DDR3\345\222\214USB2.0\347\232\204\345\233\276\345\203\217\351\207\207\351\233\206\347\263\273\347\273\237/debug/ddr_test/rtl/traffic_gen/sp6_data_gen.v" "b/Frogwells_fpga_design/\345\237\272\344\272\216FPGA\343\200\201DDR3\345\222\214USB2.0\347\232\204\345\233\276\345\203\217\351\207\207\351\233\206\347\263\273\347\273\237/debug/ddr_test/rtl/traffic_gen/sp6_data_gen.v" new file mode 100644 index 0000000000000000000000000000000000000000..c15e13afbb80505697b8f6621d75c9747acca199 --- /dev/null +++ "b/Frogwells_fpga_design/\345\237\272\344\272\216FPGA\343\200\201DDR3\345\222\214USB2.0\347\232\204\345\233\276\345\203\217\351\207\207\351\233\206\347\263\273\347\273\237/debug/ddr_test/rtl/traffic_gen/sp6_data_gen.v" @@ -0,0 +1,781 @@ +//***************************************************************************** +// (c) Copyright 2008-2009 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: %version +// \ \ Application: MIG +// / / Filename: data_gen.v +// /___/ /\ Date Last Modified: +// \ \ / \ Date Created: +// \___\/\___\ +// +//Device: Spartan6 +//Design Name: DDR/DDR2/DDR3/LPDDR +//Purpose: This module generates different data pattern as described in +// parameter DATA_PATTERN and is set up for Spartan 6 family. +//Reference: +//Revision History: +//***************************************************************************** + +`timescale 1ps/1ps + +module sp6_data_gen # + +( + parameter TCQ = 100, + parameter ADDR_WIDTH = 32, + parameter BL_WIDTH = 6, + parameter DWIDTH = 32, + parameter DATA_PATTERN = "DGEN_ALL", //"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL" + parameter NUM_DQ_PINS = 8, + parameter COLUMN_WIDTH = 10 + + ) + ( + input clk_i, // + input rst_i, + input [31:0] prbs_fseed_i, + + input [3:0] data_mode_i, // "00" = bram; + input data_rdy_i, + input cmd_startA, + input cmd_startB, + input cmd_startC, + input cmd_startD, + input cmd_startE, + input [DWIDTH-1:0] fixed_data_i, + + input [ADDR_WIDTH-1:0] addr_i, // generated address used to determine data pattern. + input [6:0] user_burst_cnt, // generated burst length for control the burst data + + input fifo_rdy_i, // connect from mcb_wr_full when used as wr_data_gen + // connect from mcb_rd_empty when used as rd_data_gen + // When both data_rdy and data_valid is asserted, the ouput data is valid. + output [DWIDTH-1:0] data_o // generated data pattern +); +// +wire [31:0] prbs_data; + +reg [31:0] adata; +reg [DWIDTH-1:0] hdata; +reg [DWIDTH-1:0] ndata; +reg [DWIDTH - 1:0] w1data; +reg [DWIDTH-1:0] data; +reg burst_count_reached2; + +reg data_valid; +reg [2:0] walk_cnt; +reg [ADDR_WIDTH-1:0] user_address; + + +integer i,j; +reg [BL_WIDTH-1:0] user_bl; +reg [7:0] BLANK; + +reg [7:0] SHIFT_0; +reg [7:0] SHIFT_1; +reg [7:0] SHIFT_2; +reg [7:0] SHIFT_3; +reg [7:0] SHIFT_4; +reg [7:0] SHIFT_5; +reg [7:0] SHIFT_6; +reg [7:0] SHIFT_7; +reg [31:0] SHIFTB_0 ; +reg [31:0] SHIFTB_1; +reg [31:0] SHIFTB_2; +reg [31:0] SHIFTB_3; +reg [31:0] SHIFTB_4; +reg [31:0] SHIFTB_5; +reg [31:0] SHIFTB_6; +reg [31:0] SHIFTB_7; +reg [3:0] TSTB; +//********************************************************************************************* + + + + + +assign data_o = data; + +generate + +if (DWIDTH==32) begin: data_out32 +always @ (adata,hdata,ndata,w1data,prbs_data,data_mode_i,fixed_data_i) +begin + case(data_mode_i) + // 4'b0000: data = 32'b0; //reserved + 4'b0001: data = fixed_data_i; // fixed + 4'b0010: data = adata; // address as data + 4'b0011: data = hdata; // DGEN_HAMMER + 4'b0100: data = ndata; // DGEN_NEIGHBOUR + 4'b0101: data = w1data; // DGEN_WALKING1 + 4'b0110: data = w1data; // DGEN_WALKING0 + 4'b0111: data = prbs_data; + default : data = 'b0; + endcase +end +end + +endgenerate + +generate +if (DWIDTH==64) begin: data_out64 +always @ (adata,hdata,ndata,w1data,prbs_data,data_mode_i,fixed_data_i) +begin + case(data_mode_i) + 4'b0000: data = 'b0; //reserved + 4'b0001: data = fixed_data_i; // fixed + 4'b0010: data = {adata,adata}; // address as data + 4'b0011: data = hdata; // DGEN_HAMMER + 4'b0100: data = ndata; // DGEN_NEIGHBOUR + 4'b0101: data = w1data; // DGEN_WALKING1 + 4'b0110: data = w1data; // DGEN_WALKING0 + 4'b0111: data = {prbs_data,prbs_data}; + default : data = 'b0; + endcase +end +end +endgenerate + +generate +if (DWIDTH==128) begin: data_out128 +always @ (adata,hdata,ndata,w1data,prbs_data,data_mode_i,fixed_data_i) +begin + case(data_mode_i) + 4'b0000: data = 'b0; //reserved + 4'b0001: data = fixed_data_i; // fixed + 4'b0010: data = {adata,adata,adata,adata}; // address as data + 4'b0011: data = hdata; // DGEN_HAMMER + 4'b0100: data = ndata; // DGEN_NEIGHBOUR + 4'b0101: data = w1data; // DGEN_WALKING1 + 4'b0110: data = w1data; // DGEN_WALKING0 + 4'b0111: data = {prbs_data,prbs_data,prbs_data,prbs_data}; + default : data = 'b0; + endcase +end +end +endgenerate + + +// WALKING ONES: + +generate +if ((DWIDTH == 64) ||(DWIDTH == 128)) begin: SHIFT_VALUE + +always @ (data_mode_i) begin + if (data_mode_i == 3'b101 || data_mode_i == 3'b100) begin // WALKING ONE + BLANK = 8'h00; + SHIFT_0 = 8'h01; + SHIFT_1 = 8'h02; + SHIFT_2 = 8'h04; + SHIFT_3 = 8'h08; + SHIFT_4 = 8'h10; + SHIFT_5 = 8'h20; + SHIFT_6 = 8'h40; + SHIFT_7 = 8'h80; + + end + else if (data_mode_i == 3'b100)begin // NEIGHBOR ONE + BLANK = 8'h00; + SHIFT_0 = 8'h01; + SHIFT_1 = 8'h02; + SHIFT_2 = 8'h04; + SHIFT_3 = 8'h08; + SHIFT_4 = 8'h10; + SHIFT_5 = 8'h20; + SHIFT_6 = 8'h40; + SHIFT_7 = 8'h80; + end + + + + else if (data_mode_i == 3'b110) begin // WALKING ZERO + BLANK = 8'hff; + SHIFT_0 = 8'hfe; + SHIFT_1 = 8'hfd; + SHIFT_2 = 8'hfb; + SHIFT_3 = 8'hf7; + SHIFT_4 = 8'hef; + SHIFT_5 = 8'hdf; + SHIFT_6 = 8'hbf; + SHIFT_7 = 8'h7f; + end + else begin + BLANK = 8'hff; + SHIFT_0 = 8'hfe; + SHIFT_1 = 8'hfd; + SHIFT_2 = 8'hfb; + SHIFT_3 = 8'hf7; + SHIFT_4 = 8'hef; + SHIFT_5 = 8'hdf; + SHIFT_6 = 8'hbf; + SHIFT_7 = 8'h7f; + end + +end +end +endgenerate + +always @ (data_mode_i) begin + +if (data_mode_i == 3'b101 ) begin // WALKING ONE + + SHIFTB_0 = 32'h0002_0001; + SHIFTB_1 = 32'h0008_0004; + SHIFTB_2 = 32'h0020_0010; + SHIFTB_3 = 32'h0080_0040; + SHIFTB_4 = 32'h0200_0100; + SHIFTB_5 = 32'h0800_0400; + SHIFTB_6 = 32'h2000_1000; + SHIFTB_7 = 32'h8000_4000; + end +else if (data_mode_i == 3'b100)begin // NEIGHBOR ONE + + SHIFTB_0 = 32'h0000_0001; + SHIFTB_1 = 32'h0000_0002; + SHIFTB_2 = 32'h0000_0004; + SHIFTB_3 = 32'h0000_0008; + SHIFTB_4 = 32'h0000_0010; + SHIFTB_5 = 32'h0000_0020; + SHIFTB_6 = 32'h0000_0040; + SHIFTB_7 = 32'h0000_0080; + end + +else begin // WALKING ZERO + SHIFTB_0 = 32'hfffd_fffe; + SHIFTB_1 = 32'hfff7_fffb; + SHIFTB_2 = 32'hffdf_ffef; + SHIFTB_3 = 32'hff7f_ffbf; + SHIFTB_4 = 32'hfdff_feff; + SHIFTB_5 = 32'hf7ff_fbff; + SHIFTB_6 = 32'hdfff_efff; + SHIFTB_7 = 32'h7fff_bfff; + end + +end + + + + + +reg [DWIDTH-1:0] tmpdata ; +reg ndata_rising; +reg shift_en; +generate +if (DWIDTH == 32 && (DATA_PATTERN == "DGEN_WALKING0" || DATA_PATTERN == "DGEN_WALKING1" || + DATA_PATTERN == "DGEN_ALL")) begin : WALKING_ONE_32_PATTERN + + always @ (posedge clk_i) + begin + if (rst_i) begin + w1data <= #TCQ 'b0; + ndata_rising <= #TCQ 1'b1; + shift_en <= #TCQ 1'b0; + end + else if((fifo_rdy_i && user_burst_cnt != 6'd0) || cmd_startC ) + if (NUM_DQ_PINS == 16) + begin + if(cmd_startC) + begin + case (addr_i[4:2]) + 0: w1data <= #TCQ SHIFTB_0; + 1: w1data <= #TCQ SHIFTB_1; + 2: w1data <= #TCQ SHIFTB_2; + 3: w1data <= #TCQ SHIFTB_3; + 4: w1data <= #TCQ SHIFTB_4; + 5: w1data <= #TCQ SHIFTB_5; + 6: w1data <= #TCQ SHIFTB_6; + 7: w1data <= #TCQ SHIFTB_7; + + default :w1data <= #TCQ SHIFTB_0; + endcase + + ndata_rising <= #TCQ 1'b0; + end //(NUM_DQ_PINS == 16) (cmd_startC) + else //shifting + if (data_mode_i == 3'b100) + w1data <= #TCQ {16'h0000,w1data[14:0],w1data[15]}; + else + w1data <= #TCQ {w1data[29:16],w1data[31:30],w1data[13:0],w1data[15:14]}; + + + end //(DQ_PINS == 16 + else if (NUM_DQ_PINS == 8) begin + if(cmd_startC) // loading data pattern according the incoming address + begin + case (addr_i[2]) + 0: w1data <= #TCQ SHIFTB_0; + 1: w1data <= #TCQ SHIFTB_1; + default :w1data <= #TCQ SHIFTB_0; + endcase + end // (cmd_startC) + else // Shifting + // need neigbour pattern ******************** + w1data <= #TCQ {w1data[27:24],w1data[31:28],w1data[19:16],w1data[23:20], + w1data[11:8] ,w1data[15:12],w1data[3:0] ,w1data[7:4]}; + + end //(NUM_DQ_PINS == 8) + else if (NUM_DQ_PINS == 4) begin // NUM_DQ_PINS == 4 + // need neigbour pattern ******************** + if (data_mode_i == 3'b100) + w1data <= #TCQ 32'h0804_0201; + else + w1data <= #TCQ 32'h8421_8421; + end // (NUM_DQ_PINS_4 + + end +end +endgenerate // DWIDTH == 32 + +generate +if (DWIDTH == 64 && (DATA_PATTERN == "DGEN_WALKING0" || DATA_PATTERN == "DGEN_WALKING1" + || DATA_PATTERN == "DGEN_ALL")) begin : WALKING_ONE_64_PATTERN + + always @ (posedge clk_i) + begin + if (rst_i) + w1data <= #TCQ 'b0; + + else if((fifo_rdy_i && user_burst_cnt != 6'd0) || cmd_startC ) + + + + if (NUM_DQ_PINS == 16) + begin + if(cmd_startC) + begin + + case (addr_i[4:3]) + + + 0: begin + // 7:0 + w1data[2*DWIDTH/4-1:0*DWIDTH/4] <= #TCQ SHIFTB_0; + w1data[4*DWIDTH/4-1:2*DWIDTH/4] <= #TCQ SHIFTB_1; + + end + 1: begin + w1data[2*DWIDTH/4-1:0*DWIDTH/4] <= #TCQ SHIFTB_2; + w1data[4*DWIDTH/4-1:2*DWIDTH/4] <= #TCQ SHIFTB_3; + end + + 2: begin + w1data[2*DWIDTH/4-1:0*DWIDTH/4] <= #TCQ SHIFTB_4; + w1data[4*DWIDTH/4-1:2*DWIDTH/4] <= #TCQ SHIFTB_5; + end + 3: begin + w1data[2*DWIDTH/4-1:0*DWIDTH/4] <= #TCQ SHIFTB_6; + w1data[4*DWIDTH/4-1:2*DWIDTH/4] <= #TCQ SHIFTB_7; + + end + + + default :begin + w1data <= #TCQ BLANK; //15:8 + end + + endcase + + + end //(NUM_DQ_PINS == 16) (cmd_startC) + else begin //shifting + if (data_mode_i == 3'b100) + begin + w1data[63:48] <= #TCQ {16'h0000}; + w1data[47:32] <= #TCQ {w1data[45:32],w1data[47:46]}; + w1data[31:16] <= #TCQ {16'h0000}; + w1data[15:0] <= #TCQ {w1data[13:0],w1data[15:14]}; + + end + else + + w1data[DWIDTH - 1:0] <= #TCQ { + w1data[4*DWIDTH/4 - 5:4*DWIDTH/4 - 16], + w1data[4*DWIDTH/4 - 1 :4*DWIDTH/4 - 4], + + w1data[3*DWIDTH/4 - 5:3*DWIDTH/4 - 16], + w1data[3*DWIDTH/4 - 1 :3*DWIDTH/4 - 4], + + w1data[2*DWIDTH/4 - 5:2*DWIDTH/4 - 16], + w1data[2*DWIDTH/4 - 1 :2*DWIDTH/4 - 4], + + w1data[1*DWIDTH/4 - 5:1*DWIDTH/4 - 16], + w1data[1*DWIDTH/4 - 1 :1*DWIDTH/4 - 4] + + }; + + + end + + end //(DQ_PINS == 16 + else if (NUM_DQ_PINS == 8) begin + if(cmd_startC) // loading data pattern according the incoming address + + if (data_mode_i == 3'b100) + + case (addr_i[3]) + + + 0: w1data <= #TCQ { + BLANK,SHIFT_3,BLANK,SHIFT_2, + BLANK,SHIFT_1,BLANK,SHIFT_0 + }; + + 1: w1data <= #TCQ { + BLANK,SHIFT_7,BLANK,SHIFT_6, + BLANK,SHIFT_5,BLANK,SHIFT_4 + }; + + default :begin + w1data <= #TCQ 'b0; //15:8 + end + + endcase + + else + w1data <= #TCQ {32'h8040_2010,32'h0804_0201}; //**** checked + else // Shifting + if (data_mode_i == 3'b100) + + begin + w1data[63:56] <= #TCQ {8'h00}; + w1data[55:48] <= #TCQ {w1data[51:48],w1data[55:52]}; + + w1data[47:40] <= #TCQ {8'h00}; + w1data[39:32] <= #TCQ {w1data[35:32],w1data[39:36]}; + + w1data[31:24] <= #TCQ {8'h00}; + w1data[23:16] <= #TCQ {w1data[19:16],w1data[23:20]}; + + w1data[15:8] <= #TCQ {8'h00}; + w1data[7:0] <= #TCQ {w1data[3:0],w1data[7:4]}; + + end + else + w1data <= #TCQ w1data; + end //(NUM_DQ_PINS == 8) + else if (NUM_DQ_PINS == 4) // NUM_DQ_PINS == 4 + if (data_mode_i == 3'b100) + w1data <= #TCQ 64'h0804_0201_0804_0201; + else + w1data <= #TCQ 64'h8421_8421_8421_8421; + + end +end +endgenerate + +generate + +if (DWIDTH == 128 && (DATA_PATTERN == "DGEN_WALKING0" || DATA_PATTERN == "DGEN_WALKING1" || DATA_PATTERN == "DGEN_ALL")) begin : WALKING_ONE_128_PATTERN + + always @ (posedge clk_i) + begin + if (rst_i) + w1data <= #TCQ 'b0; + + else if((fifo_rdy_i && user_burst_cnt != 6'd0) || cmd_startC ) + + + + if (NUM_DQ_PINS == 16) + begin + if(cmd_startC) + begin + case (addr_i[4]) + + + 0: begin + + w1data[1*DWIDTH/4-1:0*DWIDTH/4] <= #TCQ SHIFTB_0; + w1data[2*DWIDTH/4-1:1*DWIDTH/4] <= #TCQ SHIFTB_1; // 32 + w1data[3*DWIDTH/4-1:2*DWIDTH/4] <= #TCQ SHIFTB_2; + w1data[4*DWIDTH/4-1:3*DWIDTH/4] <= #TCQ SHIFTB_3; + + + end + 1: begin + + w1data[1*DWIDTH/4-1:0*DWIDTH/4] <= #TCQ SHIFTB_4; + w1data[2*DWIDTH/4-1:1*DWIDTH/4] <= #TCQ SHIFTB_5; // 32 + w1data[3*DWIDTH/4-1:2*DWIDTH/4] <= #TCQ SHIFTB_6; + w1data[4*DWIDTH/4-1:3*DWIDTH/4] <= #TCQ SHIFTB_7; + + end + + default :begin + w1data <= #TCQ BLANK; //15:8 + + end + + endcase + + end //(NUM_DQ_PINS == 16) (cmd_startC) + else begin //shifting + if (data_mode_i == 3'b100) + begin + w1data[127:112] <= #TCQ {16'h0000}; + w1data[111:96] <= #TCQ {w1data[107:96],w1data[111:108]}; + w1data[95:80] <= #TCQ {16'h0000}; + w1data[79:64] <= #TCQ {w1data[75:64],w1data[79:76]}; + + + w1data[63:48] <= #TCQ {16'h0000}; + w1data[47:32] <= #TCQ {w1data[43:32],w1data[47:44]}; + w1data[31:16] <= #TCQ {16'h0000}; + w1data[15:0] <= #TCQ {w1data[11:0],w1data[15:12]}; + + end + else begin + w1data[DWIDTH - 1:0] <= #TCQ { + w1data[4*DWIDTH/4 - 9:4*DWIDTH/4 - 16], + w1data[4*DWIDTH/4 - 1 :4*DWIDTH/4 - 8], + w1data[4*DWIDTH/4 - 25:4*DWIDTH/4 -32], + w1data[4*DWIDTH/4 - 17:4*DWIDTH/4 -24], + + w1data[3*DWIDTH/4 - 9:3*DWIDTH/4 - 16], + w1data[3*DWIDTH/4 - 1 :3*DWIDTH/4 - 8], + w1data[3*DWIDTH/4 - 25:3*DWIDTH/4 - 32], + w1data[3*DWIDTH/4 - 17:3*DWIDTH/4 - 24], + + w1data[2*DWIDTH/4 - 9:2*DWIDTH/4 - 16], + w1data[2*DWIDTH/4 - 1 :2*DWIDTH/4 - 8], + w1data[2*DWIDTH/4 - 25:2*DWIDTH/4 - 32], + w1data[2*DWIDTH/4 - 17:2*DWIDTH/4 - 24], + + + w1data[1*DWIDTH/4 - 9:1*DWIDTH/4 - 16], + w1data[1*DWIDTH/4 - 1 :1*DWIDTH/4 - 8], + w1data[1*DWIDTH/4 - 25:1*DWIDTH/4 - 32], + w1data[1*DWIDTH/4 - 17 :1*DWIDTH/4 - 24] + }; + end + + end + + end //(DQ_PINS == 16 + else if (NUM_DQ_PINS == 8) begin + if(cmd_startC) // loading data pattern according the incoming address + begin + if (data_mode_i == 3'b100) + w1data <= #TCQ { + BLANK,SHIFT_7,BLANK,SHIFT_6, + BLANK,SHIFT_5,BLANK,SHIFT_4, + BLANK,SHIFT_3,BLANK,SHIFT_2, + BLANK,SHIFT_1,BLANK,SHIFT_0 + }; + else + // w1data <= #TCQ {32'h8040_2010,32'h0804_0201,32'h8040_2010,32'h0804_0201}; + w1data <= #TCQ { + SHIFT_7,SHIFT_6,SHIFT_5,SHIFT_4, + SHIFT_3,SHIFT_2,SHIFT_1,SHIFT_0, + SHIFT_7,SHIFT_6,SHIFT_5,SHIFT_4, + SHIFT_3,SHIFT_2,SHIFT_1,SHIFT_0 + }; + + + end // (cmd_startC) + else // Shifting + + begin + + w1data <= #TCQ w1data;//{w1data[96:64], w1data[127:97],w1data[31:0], w1data[63:32]}; + end // else + end //(NUM_DQ_PINS == 8) + else + if (data_mode_i == 3'b100) + w1data <= #TCQ 128'h0804_0201_0804_0201_0804_0201_0804_0201; + else + w1data <= #TCQ 128'h8421_8421_8421_8421_8421_8421_8421_8421; + + end +end +endgenerate + +// HAMMER_PATTERN: Alternating 1s and 0s on DQ pins +// => the rsing data pattern will be 32'b11111111_11111111_11111111_11111111 +// => the falling data pattern will be 32'b00000000_00000000_00000000_00000000 +generate +if ( DWIDTH == 32 &&( DATA_PATTERN == "DGEN_HAMMER" || DATA_PATTERN == "DGEN_ALL")) begin : HAMMER_PATTERN_32 + always @ (posedge clk_i) + begin + if (rst_i) + hdata <= #TCQ 'd0; + else if((fifo_rdy_i && user_burst_cnt != 6'd0) || cmd_startC ) begin + if (NUM_DQ_PINS == 16) + hdata <= #TCQ 32'h0000_FFFF; + else if (NUM_DQ_PINS == 8) + hdata <= #TCQ 32'h00FF_00FF; + else if (NUM_DQ_PINS == 4) // NUM_DQ_PINS == 4 + hdata <= #TCQ 32'h0F0F_0F0F; + end + end +end +endgenerate + + +generate +if ( DWIDTH == 64 && (DATA_PATTERN == "DGEN_HAMMER" || DATA_PATTERN == "DGEN_ALL")) begin : HAMMER_PATTERN_64 + always @ (posedge clk_i) + begin + if (rst_i) + hdata <= #TCQ 'd0; + else if((fifo_rdy_i && user_burst_cnt != 6'd0) || cmd_startC ) + if (NUM_DQ_PINS == 16) + hdata <= #TCQ 64'h0000FFFF_0000FFFF; + else if (NUM_DQ_PINS == 8) + hdata <= #TCQ 64'h00FF00FF_00FF00FF; + else if (NUM_DQ_PINS == 4) // NUM_DQ_PINS == 4 + hdata <= #TCQ 64'h0F0F_0F0F_0F0F_0F0F; + + end +end +endgenerate + + +generate +if ( DWIDTH == 128 && (DATA_PATTERN == "DGEN_HAMMER" || DATA_PATTERN == "DGEN_ALL")) begin : HAMMER_PATTERN_128 + always @ (posedge clk_i) + begin + if (rst_i) + hdata <= #TCQ 'd0; + else if((fifo_rdy_i && user_burst_cnt != 6'd0) || cmd_startC ) + if (NUM_DQ_PINS == 16) + hdata <= #TCQ 128'h0000FFFF_0000FFFF_0000FFFF_0000FFFF; + else if (NUM_DQ_PINS == 8) + hdata <= #TCQ 128'h00FF00FF_00FF00FF_00FF00FF_00FF00FF; + else if (NUM_DQ_PINS == 4) // NUM_DQ_PINS == 4 + hdata <= #TCQ 128'h0F0F_0F0F_0F0F_0F0F_0F0F_0F0F_0F0F_0F0F; + + end +end +endgenerate + + +always @ (w1data,hdata) +begin +for (i=0; i <= DWIDTH - 1; i= i+1) + ndata[i] = hdata[i] ^ w1data[i]; + + end + + + + +// HAMMER_PATTERN_MINUS: generate walking HAMMER data pattern except 1 bit for the whole burst. The incoming addr_i[5:2] determine +// the position of the pin driving oppsite polarity +// addr_i[6:2] = 5'h0f ; 32 bit data port +// => the rsing data pattern will be 32'b11111111_11111111_01111111_11111111 +// => the falling data pattern will be 32'b00000000_00000000_00000000_00000000 + +// ADDRESS_PATTERN: use the address as the 1st data pattern for the whole burst. For example +// Dataport 32 bit width with starting addr_i = 30'h12345678, user burst length 4 +// => the 1st data pattern : 32'h12345678 +// => the 2nd data pattern : 32'h12345679 +// => the 3rd data pattern : 32'h1234567a +// => the 4th data pattern : 32'h1234567b +generate + +//data_rdy_i + +if (DATA_PATTERN == "DGEN_ADDR" || DATA_PATTERN == "DGEN_ALL") begin : ADDRESS_PATTERN +//data_o logic +always @ (posedge clk_i) +begin + if (cmd_startD) + adata <= #TCQ addr_i; + else if(fifo_rdy_i && data_rdy_i && user_burst_cnt > 6'd1) + if (DWIDTH == 128) + adata <= #TCQ adata + 16; + else if (DWIDTH == 64) + adata <= #TCQ adata + 8; + else // DWIDTH == 32 + adata <= #TCQ adata + 4; +end +end +endgenerate + + +// PRBS_PATTERN: use the address as the PRBS seed data pattern for the whole burst. For example +// Dataport 32 bit width with starting addr_i = 30'h12345678, user burst length 4 +// + +generate +if (DATA_PATTERN == "DGEN_PRBS" || DATA_PATTERN == "DGEN_ALL") begin : PRBS_PATTERN + +// PRBS DATA GENERATION +// xor all the tap positions before feedback to 1st stage. + + + +assign data_clk_en = fifo_rdy_i && data_rdy_i && user_burst_cnt > 6'd1; + + +data_prbs_gen # + ( + .TCQ (TCQ), + .PRBS_WIDTH (32), + .SEED_WIDTH (32) + ) + data_prbs_gen + ( + .clk_i (clk_i), + .clk_en (data_clk_en), + .rst_i (rst_i), + .prbs_fseed_i (prbs_fseed_i), + .prbs_seed_init (cmd_startE), + .prbs_seed_i (addr_i[31:0]), + .prbs_o (prbs_data) + + ); +end +endgenerate + + +endmodule diff --git "a/Frogwells_fpga_design/\345\237\272\344\272\216FPGA\343\200\201DDR3\345\222\214USB2.0\347\232\204\345\233\276\345\203\217\351\207\207\351\233\206\347\263\273\347\273\237/debug/ddr_test/rtl/traffic_gen/tg_status.v" "b/Frogwells_fpga_design/\345\237\272\344\272\216FPGA\343\200\201DDR3\345\222\214USB2.0\347\232\204\345\233\276\345\203\217\351\207\207\351\233\206\347\263\273\347\273\237/debug/ddr_test/rtl/traffic_gen/tg_status.v" new file mode 100644 index 0000000000000000000000000000000000000000..7be5b39a85225215c5104ecb7f760b63285239dd --- /dev/null +++ "b/Frogwells_fpga_design/\345\237\272\344\272\216FPGA\343\200\201DDR3\345\222\214USB2.0\347\232\204\345\233\276\345\203\217\351\207\207\351\233\206\347\263\273\347\273\237/debug/ddr_test/rtl/traffic_gen/tg_status.v" @@ -0,0 +1,128 @@ +//***************************************************************************** +// (c) Copyright 2008-2009 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: %version +// \ \ Application: MIG +// / / Filename: tg_status.v +// /___/ /\ Date Last Modified: +// \ \ / \ Date Created: +// \___\/\___\ +// +//Device: Spartan6 +//Design Name: DDR/DDR2/DDR3/LPDDR +//Purpose: This module compare the memory read data agaisnt compare data that generated from data_gen module. +// Error signal will be asserted if the comparsion is not equal. +//Reference: +//Revision History: +//***************************************************************************** + +`timescale 1ps/1ps + + +module tg_status #( + parameter TCQ = 100, + + parameter DWIDTH = 32 + ) + ( + + + input clk_i , + input rst_i , + input manual_clear_error, + input data_error_i , + input [DWIDTH-1:0] cmp_data_i, + input [DWIDTH-1:0] rd_data_i , + input [31:0] cmp_addr_i , + input [5:0] cmp_bl_i , + input mcb_cmd_full_i , + input mcb_wr_full_i, + input mcb_rd_empty_i, + output reg [64 + (2*DWIDTH - 1):0] error_status, + output error + ); + +reg data_error_r; +reg error_set; +assign error = error_set; + +always @ (posedge clk_i) + data_error_r <= #TCQ data_error_i; + +always @ (posedge clk_i) +begin + +if (rst_i || manual_clear_error) begin + error_status <= #TCQ 'b0; + error_set <= #TCQ 1'b0; +end +else begin + // latch the first error only + if (data_error_i && ~data_error_r && ~error_set ) begin + error_status[31:0] <= #TCQ cmp_addr_i; + error_status[37:32] <= #TCQ cmp_bl_i; + error_status[40] <= #TCQ mcb_cmd_full_i; + error_status[41] <= #TCQ mcb_wr_full_i; + error_status[42] <= #TCQ mcb_rd_empty_i; + error_set <= #TCQ 1'b1; + error_status[64 + (DWIDTH - 1) :64] <= #TCQ cmp_data_i; + error_status[64 + (2*DWIDTH - 1):64 + DWIDTH] <= #TCQ rd_data_i; + + end + + error_status[39:38] <= #TCQ 'b0; // reserved + error_status[63:43] <= #TCQ 'b0; // reserved + + +end end + +endmodule + diff --git "a/Frogwells_fpga_design/\345\237\272\344\272\216FPGA\343\200\201DDR3\345\222\214USB2.0\347\232\204\345\233\276\345\203\217\351\207\207\351\233\206\347\263\273\347\273\237/debug/ddr_test/rtl/traffic_gen/v6_data_gen.v" "b/Frogwells_fpga_design/\345\237\272\344\272\216FPGA\343\200\201DDR3\345\222\214USB2.0\347\232\204\345\233\276\345\203\217\351\207\207\351\233\206\347\263\273\347\273\237/debug/ddr_test/rtl/traffic_gen/v6_data_gen.v" new file mode 100644 index 0000000000000000000000000000000000000000..8e4a552bf7297a546aa33290cfe891b5a9296561 --- /dev/null +++ "b/Frogwells_fpga_design/\345\237\272\344\272\216FPGA\343\200\201DDR3\345\222\214USB2.0\347\232\204\345\233\276\345\203\217\351\207\207\351\233\206\347\263\273\347\273\237/debug/ddr_test/rtl/traffic_gen/v6_data_gen.v" @@ -0,0 +1,3045 @@ +//***************************************************************************** +// (c) Copyright 2008-2009 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: %version +// \ \ Application: MIG +// / / Filename: data_gen.v +// /___/ /\ Date Last Modified: +// \ \ / \ Date Created: +// \___\/\___\ +// +//Device: Virtex6 +//Design Name: DDR2/DDR3/QDDR +//Purpose: This module generates different data pattern as described in +// parameter DATA_PATTERN and is set up for Virtex 6 family. +//Reference: +//Revision History: 18/7/2011 Fixed DGEN_NEIGHBOR in generate statement . +//***************************************************************************** + +`timescale 1ps/1ps +`ifndef TCQ + `define TCQ 100 +`endif + +module v6_data_gen # + +( parameter TCQ = 100, + parameter EYE_TEST = "FALSE", + parameter ADDR_WIDTH = 32, + parameter MEM_BURST_LEN = 8, + parameter BL_WIDTH = 6, + parameter DWIDTH = 32, + parameter DATA_PATTERN = "DGEN_ALL", //"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL" + parameter NUM_DQ_PINS = 8, + parameter COLUMN_WIDTH = 10, + parameter SEL_VICTIM_LINE = 3 // VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern +// parameter [287:0] ALL_1 = {288{1'b1}}, +// parameter [287:0] ALL_0 = {288{1'b0}} + + + ) + ( + input clk_i, // + input rst_i, + input [31:0] prbs_fseed_i, + + input [3:0] data_mode_i, // "00" = bram; + input data_rdy_i, + input cmd_startA, + input cmd_startB, + input cmd_startC, + input cmd_startD, + input cmd_startE, + + input [ADDR_WIDTH-1:0] m_addr_i, // generated address used to determine data pattern. + input [DWIDTH-1:0] fixed_data_i, + + input [ADDR_WIDTH-1:0] addr_i, // generated address used to determine data pattern. + input [6:0] user_burst_cnt, // generated burst length for control the burst data + + input fifo_rdy_i, // connect from mcb_wr_full when used as wr_data_gen + // connect from mcb_rd_empty when used as rd_data_gen + // When both data_rdy and data_valid is asserted, the ouput data is valid. + output [NUM_DQ_PINS*4-1:0] data_o // generated data pattern +); +// +wire [31:0] prbs_data; +reg [35:0] acounts; + +wire [NUM_DQ_PINS*4-1:0] adata; +reg [NUM_DQ_PINS*4-1:0] hdata; +reg [NUM_DQ_PINS*4-1:0] hdata_c; + +reg [NUM_DQ_PINS*4-1:0] ndata; +reg [NUM_DQ_PINS*4-1:0] w1data; +reg [NUM_DQ_PINS*4-1:0] w1trash; + +reg [NUM_DQ_PINS*4-1:0] w0data; +reg [NUM_DQ_PINS*4-1:0] data; + + +reg burst_count_reached2; + +reg data_valid; +reg [2:0] walk_cnt; +reg [ADDR_WIDTH-1:0] user_address; +reg sel_w1gen_logic; +wire [4*NUM_DQ_PINS -1 :0] ZEROS; +wire [4*NUM_DQ_PINS -1 :0] ONES; +reg [7:0] BLANK; + +reg [7:0] SHIFT_0; +reg [7:0] SHIFT_1; +reg [7:0] SHIFT_2; +reg [7:0] SHIFT_3; +reg [7:0] SHIFT_4; +reg [7:0] SHIFT_5; +reg [7:0] SHIFT_6; +reg [7:0] SHIFT_7; +reg [4*NUM_DQ_PINS -1 :0] sel_victimline_r; +wire data_clk_en; +wire [NUM_DQ_PINS*4-1:0] full_prbs_data; +reg [NUM_DQ_PINS*4-1:0] h_prbsdata; +//wire [4*NUM_DQ_PINS - 1:3*NUM_DQ_PINS] ALL_1 = + +assign ZEROS = 'b0; +assign ONES = 'b1; + + +integer i,j,k; +reg [BL_WIDTH-1:0] user_bl; + + +//********************************************************************************************* +localparam BRAM_DATAL_MODE = 4'b0000; +localparam FIXED_DATA_MODE = 4'b0001; +localparam ADDR_DATA_MODE = 4'b0010; +localparam HAMMER_DATA_MODE = 4'b0011; +localparam NEIGHBOR_DATA_MODE = 4'b0100; +localparam WALKING1_DATA_MODE = 4'b0101; +localparam WALKING0_DATA_MODE = 4'b0110; +localparam PRBS_DATA_MODE = 4'b0111; + +assign data_o = data; + +//assign full_prbs_data = {prbs_data,prbs_data,prbs_data,prbs_data,prbs_data,prbs_data,prbs_data,prbs_data,prbs_data}; +assign full_prbs_data = {DWIDTH/32{prbs_data}}; + +reg [3:0] data_mode_rr_a; +reg [3:0] data_mode_rr_b; +reg [3:0] data_mode_rr_c; + +always @ (posedge clk_i) +begin + data_mode_rr_a <= #TCQ data_mode_i; + data_mode_rr_b <= #TCQ data_mode_i; + data_mode_rr_c <= #TCQ data_mode_i; + +end + + +always @ (data_mode_i,rst_i) begin + if (data_mode_i == 3'b101 || data_mode_i == 3'b100 || rst_i) begin // WALKING ONE + BLANK = 8'h00; + SHIFT_0 = 8'h01; + SHIFT_1 = 8'h02; + SHIFT_2 = 8'h04; + SHIFT_3 = 8'h08; + SHIFT_4 = 8'h10; + SHIFT_5 = 8'h20; + SHIFT_6 = 8'h40; + SHIFT_7 = 8'h80; + + end + else begin // WALKING ZERO + BLANK = 8'hff; + SHIFT_0 = 8'hfe; + SHIFT_1 = 8'hfd; + SHIFT_2 = 8'hfb; + SHIFT_3 = 8'hf7; + SHIFT_4 = 8'hef; + SHIFT_5 = 8'hdf; + SHIFT_6 = 8'hbf; + SHIFT_7 = 8'h7f; + end + +end + + +always @ (data_mode_rr_a,fixed_data_i,h_prbsdata,adata,hdata,ndata,w1data,full_prbs_data) +begin + case(data_mode_rr_a) + 4'b0000: data = h_prbsdata; + 4'b0001: data = fixed_data_i; // "000" = address as data + 4'b0010: data = adata; // "000" = address as data + 4'b0011: data = hdata; // "001" = hammer + 4'b0100: data = ndata; // "010" = neighbour + 4'b0101: data = w1data; // "100" = walking 0's + 4'b0110: data = w1data; // /"101" = walking 1's + 4'b0111: data = full_prbs_data;//{prbs_data,prbs_data,prbs_data,prbs_data}; // "011" = prbs + default : data = 'b0; + endcase +end +//always @ (data_mode_rr_a,fixed_data_i,h_prbsdata,adata,hdata,ndata,w1data,full_prbs_data) +//begin +// +// data = w1data; +//end +function [4*NUM_DQ_PINS-1:0] Data_Gen (input integer i ); + integer j; + begin + j = i/2; + Data_Gen = {4*NUM_DQ_PINS{1'b0}}; + if(i %2) begin + Data_Gen[(0*NUM_DQ_PINS+j*8)+:8] = 8'b00010000; + Data_Gen[(1*NUM_DQ_PINS+j*8)+:8] = 8'b00100000; + Data_Gen[(2*NUM_DQ_PINS+j*8)+:8] = 8'b01000000; + Data_Gen[(3*NUM_DQ_PINS+j*8)+:8] = 8'b10000000; + + end else begin + Data_Gen[(0*NUM_DQ_PINS+j*8)+:8] = 8'b00000001; + Data_Gen[(1*NUM_DQ_PINS+j*8)+:8] = 8'b00000010; + Data_Gen[(2*NUM_DQ_PINS+j*8)+:8] = 8'b00000100; + Data_Gen[(3*NUM_DQ_PINS+j*8)+:8] = 8'b00001000; + + end + + + end +endfunction + + +/* + + +function [4*NUM_DQ_PINS-1:0] Data_Gen (input integer i, + input [3:0] data_mode); + integer j; + begin + j = i/2; + Data_Gen = {4*NUM_DQ_PINS{1'b0}}; + if(data_mode == 4'b0101) begin // Walking 1 pattern + if(i %2) begin + Data_Gen[(0*NUM_DQ_PINS+j*8)+:8] = 8'b00010000; + Data_Gen[(1*NUM_DQ_PINS+j*8)+:8] = 8'b00100000; + Data_Gen[(2*NUM_DQ_PINS+j*8)+:8] = 8'b01000000; + Data_Gen[(3*NUM_DQ_PINS+j*8)+:8] = 8'b10000000; + end else begin + Data_Gen[(0*NUM_DQ_PINS+j*8)+:8] = 8'b00000001; + Data_Gen[(1*NUM_DQ_PINS+j*8)+:8] = 8'b00000010; + Data_Gen[(2*NUM_DQ_PINS+j*8)+:8] = 8'b00000100; + Data_Gen[(3*NUM_DQ_PINS+j*8)+:8] = 8'b00001000; + end + end else begin // Walking 0 pattern + if(i %2) begin + Data_Gen[(0*NUM_DQ_PINS+j*8)+:8] = 8'b11101111; + Data_Gen[(1*NUM_DQ_PINS+j*8)+:8] = 8'b11011111; + Data_Gen[(2*NUM_DQ_PINS+j*8)+:8] = 8'b10111111; + Data_Gen[(3*NUM_DQ_PINS+j*8)+:8] = 8'b01111111; + end else begin + Data_Gen[(0*NUM_DQ_PINS+j*8)+:8] = 8'b11111110; + Data_Gen[(1*NUM_DQ_PINS+j*8)+:8] = 8'b11111101; + Data_Gen[(2*NUM_DQ_PINS+j*8)+:8] = 8'b11111011; + Data_Gen[(3*NUM_DQ_PINS+j*8)+:8] = 8'b11110111; + end + end + end +endfunction +*/ +function [4*NUM_DQ_PINS-1:0] Data_GenW0 (input integer i); + integer j; + begin + j = i/2; + Data_GenW0 = {4*NUM_DQ_PINS{1'b1}}; + + if(i %2) begin + Data_GenW0[(0*NUM_DQ_PINS+j*8)+:8] = 8'b11101111; + Data_GenW0[(1*NUM_DQ_PINS+j*8)+:8] = 8'b11011111; + Data_GenW0[(2*NUM_DQ_PINS+j*8)+:8] = 8'b10111111; + Data_GenW0[(3*NUM_DQ_PINS+j*8)+:8] = 8'b01111111; + + end else begin + Data_GenW0[(0*NUM_DQ_PINS+j*8)+:8] = 8'b11111110; + Data_GenW0[(1*NUM_DQ_PINS+j*8)+:8] = 8'b11111101; + Data_GenW0[(2*NUM_DQ_PINS+j*8)+:8] = 8'b11111011; + Data_GenW0[(3*NUM_DQ_PINS+j*8)+:8] = 8'b11110111; + + end + + + end +endfunction +always @ (posedge clk_i) begin + if (data_mode_rr_c[2:0] == 3'b101 || data_mode_rr_c[2:0] == 3'b100 || data_mode_rr_c[2:0] == 3'b110) // WALKING ONES + sel_w1gen_logic <= #TCQ 1'b1; + else + sel_w1gen_logic <= #TCQ 1'b0; +end + +// WALKING ONES, WALKING ZEROS; HAMMER GENERATION +generate +if (NUM_DQ_PINS == 8 && (DATA_PATTERN == "DGEN_NEIGHBOR" || DATA_PATTERN == "DGEN_WALKING1" || DATA_PATTERN == "DGEN_WALKING0" || DATA_PATTERN == "DGEN_ALL")) begin : WALKING_ONE_8_PATTERN + +always @ (posedge clk_i) +begin +if( (fifo_rdy_i ) || cmd_startC ) + + + if (cmd_startC ) + begin + if (sel_w1gen_logic) begin // 1b WALKING ONES + + //****************** (NUM_DQ_PINS == 8) + + // first 8 pins + case (addr_i[3]) + + 0: begin + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(0); + else + w1data <= #TCQ Data_GenW0(0); + + end + 1: begin + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(1); + else + w1data <= #TCQ Data_GenW0(1); + end + default :begin + w1data[4*NUM_DQ_PINS-1:0*NUM_DQ_PINS ] <= #TCQ 'b0; + end + + endcase + + end // 1b data_mode WALKING ONE + + end // 1c + else if( MEM_BURST_LEN == 8) begin + + w1data[4*NUM_DQ_PINS - 1:3*NUM_DQ_PINS] <= #TCQ {w1data[4*NUM_DQ_PINS - 5:3*NUM_DQ_PINS ],w1data[4*NUM_DQ_PINS - 1:4*NUM_DQ_PINS - 4]}; + w1data[3*NUM_DQ_PINS - 1:2*NUM_DQ_PINS] <= #TCQ {w1data[3*NUM_DQ_PINS - 5:2*NUM_DQ_PINS ],w1data[3*NUM_DQ_PINS - 1:3*NUM_DQ_PINS - 4]}; + w1data[2*NUM_DQ_PINS - 1:1*NUM_DQ_PINS] <= #TCQ {w1data[2*NUM_DQ_PINS - 5:1*NUM_DQ_PINS ],w1data[2*NUM_DQ_PINS - 1:2*NUM_DQ_PINS - 4]}; + w1data[1*NUM_DQ_PINS - 1:0*NUM_DQ_PINS] <= #TCQ {w1data[1*NUM_DQ_PINS - 5:0*NUM_DQ_PINS ],w1data[1*NUM_DQ_PINS - 1:1*NUM_DQ_PINS - 4]}; + + + end + + end // always +end // endgenerate +endgenerate // NUM_DQ_PINS == 8 + + + +generate +if (NUM_DQ_PINS == 16 && (DATA_PATTERN == "DGEN_NEIGHBOR" || DATA_PATTERN == "DGEN_WALKING1" || DATA_PATTERN == "DGEN_WALKING0" || DATA_PATTERN == "DGEN_ALL")) begin : WALKING_ONE_16_PATTERN + +always @ (posedge clk_i) +begin +if( (fifo_rdy_i ) || cmd_startC ) + + + if (cmd_startC ) + begin + if (sel_w1gen_logic) begin // 1a WALKING ONES + case (addr_i[4:3]) + + 0: begin // 8 pins + + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(0); + else + w1data <= #TCQ Data_GenW0(0); + + + end + 1: begin + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(1); + else + w1data <= #TCQ Data_GenW0(1); + + + end + 2: begin // 16 pins + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(2); + else + w1data <= #TCQ Data_GenW0(2); + + + end + + 3: begin + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(3); + else + w1data <= #TCQ Data_GenW0(3); + + + end + + + default :begin + w1data[4*NUM_DQ_PINS-1:0*NUM_DQ_PINS ] <= #TCQ 'b0; + end + + endcase + + end // 1a data_mode WALKING ONE + + end // 1b StartC + else if( MEM_BURST_LEN == 8) begin + + + w1data[4*NUM_DQ_PINS - 1:3*NUM_DQ_PINS] <= #TCQ {w1data[4*NUM_DQ_PINS - 5:3*NUM_DQ_PINS ],w1data[4*NUM_DQ_PINS - 1:4*NUM_DQ_PINS - 4]}; + w1data[3*NUM_DQ_PINS - 1:2*NUM_DQ_PINS] <= #TCQ {w1data[3*NUM_DQ_PINS - 5:2*NUM_DQ_PINS ],w1data[3*NUM_DQ_PINS - 1:3*NUM_DQ_PINS - 4]}; + w1data[2*NUM_DQ_PINS - 1:1*NUM_DQ_PINS] <= #TCQ {w1data[2*NUM_DQ_PINS - 5:1*NUM_DQ_PINS ],w1data[2*NUM_DQ_PINS - 1:2*NUM_DQ_PINS - 4]}; + w1data[1*NUM_DQ_PINS - 1:0*NUM_DQ_PINS] <= #TCQ {w1data[1*NUM_DQ_PINS - 5:0*NUM_DQ_PINS ],w1data[1*NUM_DQ_PINS - 1:1*NUM_DQ_PINS - 4]}; + + + + end + + end +end //1d +endgenerate // NUM_DQ_PINS == 16 + + + + + + generate + if ((NUM_DQ_PINS == 24 ) && (DATA_PATTERN == "DGEN_WALKING1" || DATA_PATTERN == "DGEN_WALKING0" || DATA_PATTERN == "DGEN_NEIGHBOR" + || DATA_PATTERN == "DGEN_ALL")) begin : WALKING_ONE_24_PATTERN + always @ (posedge clk_i) begin + + + if( (fifo_rdy_i ) || cmd_startC ) + if (cmd_startC ) begin + if (sel_w1gen_logic) begin + case (addr_i[7:3]) + + + 0, 6, 12, + 18, 24, 30 : + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(0); + else + w1data <= #TCQ Data_GenW0(0); + + 1, 7, 13, + 19, 25, 31 : + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(1); + else + w1data <= #TCQ Data_GenW0(1); + + 2,8,14,20,26 : + + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(2); + else + w1data <= #TCQ Data_GenW0(2); + + + + 3,9,15,21,27 : + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(3); + else + w1data <=#TCQ Data_GenW0(3); + + 4, 10, + 16, 22, 28 : + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(4); + else + w1data <= #TCQ Data_GenW0(4); + 5, 11, + 17, 23, 29 : + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(5); + else + w1data <= #TCQ Data_GenW0(5); + + default : + w1data[4*NUM_DQ_PINS-1:0*NUM_DQ_PINS ] <= #TCQ 'b0; + + endcase + end + end + else if ( MEM_BURST_LEN == 8) begin + w1data[4*NUM_DQ_PINS - 1:3*NUM_DQ_PINS] <= #TCQ {w1data[4*NUM_DQ_PINS - 5:3*NUM_DQ_PINS ],w1data[4*NUM_DQ_PINS - 1:4*NUM_DQ_PINS - 4]}; + w1data[3*NUM_DQ_PINS - 1:2*NUM_DQ_PINS] <= #TCQ {w1data[3*NUM_DQ_PINS - 5:2*NUM_DQ_PINS ],w1data[3*NUM_DQ_PINS - 1:3*NUM_DQ_PINS - 4]}; + w1data[2*NUM_DQ_PINS - 1:1*NUM_DQ_PINS] <= #TCQ {w1data[2*NUM_DQ_PINS - 5:1*NUM_DQ_PINS ],w1data[2*NUM_DQ_PINS - 1:2*NUM_DQ_PINS - 4]}; + w1data[1*NUM_DQ_PINS - 1:0*NUM_DQ_PINS] <= #TCQ {w1data[1*NUM_DQ_PINS - 5:0*NUM_DQ_PINS ],w1data[1*NUM_DQ_PINS - 1:1*NUM_DQ_PINS - 4]}; + end + end + end + endgenerate + + generate + if (NUM_DQ_PINS == 32 && (DATA_PATTERN == "DGEN_NEIGHBOR" || DATA_PATTERN == "DGEN_WALKING1" || DATA_PATTERN == "DGEN_WALKING0" || DATA_PATTERN == "DGEN_ALL")) begin : WALKING_ONE_32_PATTERN + always @ (posedge clk_i) begin + if( (fifo_rdy_i ) || cmd_startC ) + if (cmd_startC ) begin + if (sel_w1gen_logic) begin + case (addr_i[6:4]) + 0: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(0); + else + w1data <= #TCQ Data_GenW0(0); + + 1: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(1); + else + w1data <= #TCQ Data_GenW0(1); + + 2: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(2); + else + w1data <= #TCQ Data_GenW0(2); + + 3: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(3); + else + w1data <= #TCQ Data_GenW0(3); + + 4: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(4); + else + w1data <= #TCQ Data_GenW0(4); + + 5: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(5); + else + w1data <= #TCQ Data_GenW0(5); + + 6: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(6); + else + w1data <= #TCQ Data_GenW0(6); + + 7: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(7); + else + w1data <= #TCQ Data_GenW0(7); + + endcase + end + end + else if ( MEM_BURST_LEN == 8) begin + w1data[4*NUM_DQ_PINS - 1:3*NUM_DQ_PINS] <= #TCQ {w1data[4*NUM_DQ_PINS - 5:3*NUM_DQ_PINS ],w1data[4*NUM_DQ_PINS - 1:4*NUM_DQ_PINS - 4]}; + w1data[3*NUM_DQ_PINS - 1:2*NUM_DQ_PINS] <= #TCQ {w1data[3*NUM_DQ_PINS - 5:2*NUM_DQ_PINS ],w1data[3*NUM_DQ_PINS - 1:3*NUM_DQ_PINS - 4]}; + w1data[2*NUM_DQ_PINS - 1:1*NUM_DQ_PINS] <= #TCQ {w1data[2*NUM_DQ_PINS - 5:1*NUM_DQ_PINS ],w1data[2*NUM_DQ_PINS - 1:2*NUM_DQ_PINS - 4]}; + w1data[1*NUM_DQ_PINS - 1:0*NUM_DQ_PINS] <= #TCQ {w1data[1*NUM_DQ_PINS - 5:0*NUM_DQ_PINS ],w1data[1*NUM_DQ_PINS - 1:1*NUM_DQ_PINS - 4]}; + end + end + end + endgenerate + + + generate + if ((NUM_DQ_PINS == 40 ) && (DATA_PATTERN == "DGEN_NEIGHBOR" || DATA_PATTERN == "DGEN_WALKING1" || DATA_PATTERN == "DGEN_WALKING0" || DATA_PATTERN == "DGEN_ALL")) begin : WALKING_ONE_40_PATTERN + always @ (posedge clk_i) begin + + + if( (fifo_rdy_i ) || cmd_startC ) + if (cmd_startC ) begin + if (sel_w1gen_logic) begin + case (addr_i[7:4]) + + 0, 10: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(0); + else + w1data <= #TCQ Data_GenW0(0); + + 1, 11: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(1); + else + w1data <= #TCQ Data_GenW0(1); + + 2, 12: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(2); + else + w1data <= #TCQ Data_GenW0(2); + + 3, 13: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(3); + else + w1data <= #TCQ Data_GenW0(3); + + 4, 14: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(4); + else + w1data <= #TCQ Data_GenW0(4); + + 5, 15: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(5); + else + w1data <= #TCQ Data_GenW0(5); + + 6: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(6); + else + w1data <= #TCQ Data_GenW0(6); + + 7: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(7); + else + w1data <= #TCQ Data_GenW0(7); + + 8: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(8); + else + w1data <= #TCQ Data_GenW0(8); + + 9: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(9); + else + w1data <= #TCQ Data_GenW0(9); + default : + w1data[4*NUM_DQ_PINS-1:0*NUM_DQ_PINS ] <= #TCQ 'b0; + + endcase + end + end + else if ( MEM_BURST_LEN == 8) begin + w1data[4*NUM_DQ_PINS - 1:3*NUM_DQ_PINS] <= #TCQ {w1data[4*NUM_DQ_PINS - 5:3*NUM_DQ_PINS ],w1data[4*NUM_DQ_PINS - 1:4*NUM_DQ_PINS - 4]}; + w1data[3*NUM_DQ_PINS - 1:2*NUM_DQ_PINS] <= #TCQ {w1data[3*NUM_DQ_PINS - 5:2*NUM_DQ_PINS ],w1data[3*NUM_DQ_PINS - 1:3*NUM_DQ_PINS - 4]}; + w1data[2*NUM_DQ_PINS - 1:1*NUM_DQ_PINS] <= #TCQ {w1data[2*NUM_DQ_PINS - 5:1*NUM_DQ_PINS ],w1data[2*NUM_DQ_PINS - 1:2*NUM_DQ_PINS - 4]}; + w1data[1*NUM_DQ_PINS - 1:0*NUM_DQ_PINS] <= #TCQ {w1data[1*NUM_DQ_PINS - 5:0*NUM_DQ_PINS ],w1data[1*NUM_DQ_PINS - 1:1*NUM_DQ_PINS - 4]}; + end + end + end + endgenerate + + generate + if ((NUM_DQ_PINS == 48 ) && (DATA_PATTERN == "DGEN_NEIGHBOR" || DATA_PATTERN == "DGEN_WALKING1" || DATA_PATTERN == "DGEN_WALKING0" || DATA_PATTERN == "DGEN_ALL")) begin : WALKING_ONE_48_PATTERN + always @ (posedge clk_i) begin + + + if( (fifo_rdy_i ) || cmd_startC ) + if (cmd_startC ) begin + if (sel_w1gen_logic) begin + case (addr_i[7:4]) + + 0, 12: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(0); + else + w1data <= #TCQ Data_GenW0(0); + + 1, 13: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(1); + else + w1data <= #TCQ Data_GenW0(1); + + 2, 14: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(2); + else + w1data <= #TCQ Data_GenW0(2); + + 3, 15: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(3); + else + w1data <= #TCQ Data_GenW0(3); + + 4: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(4); + else + w1data <= #TCQ Data_GenW0(4); + + 5: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(5); + else + w1data <= #TCQ Data_GenW0(5); + + 6: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(6); + else + w1data <= #TCQ Data_GenW0(6); + + 7: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(7); + else + w1data <= #TCQ Data_GenW0(7); + + 8: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(8); + else + w1data <= #TCQ Data_GenW0(8); + + 9: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(9); + else + w1data <= #TCQ Data_GenW0(9); + + 10: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(10); + else + w1data <= #TCQ Data_GenW0(10); + + 11: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(11); + else + w1data <= #TCQ Data_GenW0(11); + + + default : + w1data[4*NUM_DQ_PINS-1:0*NUM_DQ_PINS ] <= #TCQ 'b0; + + + endcase + end + end + else if ( MEM_BURST_LEN == 8) begin + w1data[4*NUM_DQ_PINS - 1:3*NUM_DQ_PINS] <= #TCQ {w1data[4*NUM_DQ_PINS - 5:3*NUM_DQ_PINS ],w1data[4*NUM_DQ_PINS - 1:4*NUM_DQ_PINS - 4]}; + w1data[3*NUM_DQ_PINS - 1:2*NUM_DQ_PINS] <= #TCQ {w1data[3*NUM_DQ_PINS - 5:2*NUM_DQ_PINS ],w1data[3*NUM_DQ_PINS - 1:3*NUM_DQ_PINS - 4]}; + w1data[2*NUM_DQ_PINS - 1:1*NUM_DQ_PINS] <= #TCQ {w1data[2*NUM_DQ_PINS - 5:1*NUM_DQ_PINS ],w1data[2*NUM_DQ_PINS - 1:2*NUM_DQ_PINS - 4]}; + w1data[1*NUM_DQ_PINS - 1:0*NUM_DQ_PINS] <= #TCQ {w1data[1*NUM_DQ_PINS - 5:0*NUM_DQ_PINS ],w1data[1*NUM_DQ_PINS - 1:1*NUM_DQ_PINS - 4]}; + end + end + end + endgenerate + + + generate + if ((NUM_DQ_PINS == 56 ) && (DATA_PATTERN == "DGEN_NEIGHBOR" || DATA_PATTERN == "DGEN_WALKING1" || DATA_PATTERN == "DGEN_WALKING0" || DATA_PATTERN == "DGEN_ALL")) begin : WALKING_ONE_56_PATTERN + always @ (posedge clk_i) begin + + + if( (fifo_rdy_i ) || cmd_startC ) + if (cmd_startC ) begin + if (sel_w1gen_logic) begin + case (addr_i[8:5]) + 0, 14: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(0); + else + w1data <= #TCQ Data_GenW0(0); + + + 1, 15: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(1); + else + w1data <= #TCQ Data_GenW0(1); + + + 2: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(2); + else + w1data <= #TCQ Data_GenW0(2); + + + 3: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(3); + else + w1data <= #TCQ Data_GenW0(3); + + + 4: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(4); + else + w1data <= #TCQ Data_GenW0(4); + + + 5: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(5); + else + w1data <= #TCQ Data_GenW0(5); + + + 6: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(6); + else + w1data <= #TCQ Data_GenW0(6); + + + 7: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(7); + else + w1data <= #TCQ Data_GenW0(7); + + + 8: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(8); + else + w1data <= #TCQ Data_GenW0(8); + + + 9: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(9); + else + w1data <= #TCQ Data_GenW0(9); + + + 10: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(10); + else + w1data <= #TCQ Data_GenW0(10); + + + 11: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(11); + else + w1data <= #TCQ Data_GenW0(11); + + + 12: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(12); + else + w1data <= #TCQ Data_GenW0(12); + + + 13: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(13); + else + w1data <= #TCQ Data_GenW0(13); + default : + w1data[4*NUM_DQ_PINS-1:0*NUM_DQ_PINS ] <= #TCQ 'b0; + + endcase + end + end + else if ( MEM_BURST_LEN == 8) begin + w1data[4*NUM_DQ_PINS - 1:3*NUM_DQ_PINS] <= #TCQ {w1data[4*NUM_DQ_PINS - 5:3*NUM_DQ_PINS ],w1data[4*NUM_DQ_PINS - 1:4*NUM_DQ_PINS - 4]}; + w1data[3*NUM_DQ_PINS - 1:2*NUM_DQ_PINS] <= #TCQ {w1data[3*NUM_DQ_PINS - 5:2*NUM_DQ_PINS ],w1data[3*NUM_DQ_PINS - 1:3*NUM_DQ_PINS - 4]}; + w1data[2*NUM_DQ_PINS - 1:1*NUM_DQ_PINS] <= #TCQ {w1data[2*NUM_DQ_PINS - 5:1*NUM_DQ_PINS ],w1data[2*NUM_DQ_PINS - 1:2*NUM_DQ_PINS - 4]}; + w1data[1*NUM_DQ_PINS - 1:0*NUM_DQ_PINS] <= #TCQ {w1data[1*NUM_DQ_PINS - 5:0*NUM_DQ_PINS ],w1data[1*NUM_DQ_PINS - 1:1*NUM_DQ_PINS - 4]}; + end + end + end + endgenerate + + generate + if ((NUM_DQ_PINS == 64 ) && (DATA_PATTERN == "DGEN_NEIGHBOR" || DATA_PATTERN == "DGEN_WALKING1" || DATA_PATTERN == "DGEN_WALKING0" || DATA_PATTERN == "DGEN_ALL")) begin : WALKING_ONE_64_PATTERN + always @ (posedge clk_i) begin + + + if( (fifo_rdy_i ) || cmd_startC ) + if (cmd_startC ) begin + if (sel_w1gen_logic) begin + case (addr_i[8:5]) + + 0: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(0); + else + w1data <= #TCQ Data_GenW0(0); + + 1: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(1); + else + w1data <= #TCQ Data_GenW0(1); + + 2: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(2); + else + w1data <= #TCQ Data_GenW0(2); + + 3: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(3); + else + w1data <= #TCQ Data_GenW0(3); + + 4: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(4); + else + w1data <= #TCQ Data_GenW0(4); + + 5: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(5); + else + w1data <= #TCQ Data_GenW0(5); + + 6: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(6); + else + w1data <= #TCQ Data_GenW0(6); + + 7: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(7); + else + w1data <= #TCQ Data_GenW0(7); + + 8: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(8); + else + w1data <= #TCQ Data_GenW0(8); + + 9: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(9); + else + w1data <= #TCQ Data_GenW0(9); + + 10: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(10); + else + w1data <= #TCQ Data_GenW0(10); + + 11: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(11); + else + w1data <= #TCQ Data_GenW0(11); + + 12: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(12); + else + w1data <= #TCQ Data_GenW0(12); + + 13: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(13); + else + w1data <= #TCQ Data_GenW0(13); + + 14: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(14); + else + w1data <= #TCQ Data_GenW0(14); + + 15: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(15); + else + w1data <= #TCQ Data_GenW0(15); + + default : + w1data[4*NUM_DQ_PINS-1:0*NUM_DQ_PINS ] <= #TCQ 'b0; + + endcase + end + end + else if ( MEM_BURST_LEN == 8) begin + w1data[4*NUM_DQ_PINS - 1:3*NUM_DQ_PINS] <= #TCQ {w1data[4*NUM_DQ_PINS - 5:3*NUM_DQ_PINS ],w1data[4*NUM_DQ_PINS - 1:4*NUM_DQ_PINS - 4]}; + w1data[3*NUM_DQ_PINS - 1:2*NUM_DQ_PINS] <= #TCQ {w1data[3*NUM_DQ_PINS - 5:2*NUM_DQ_PINS ],w1data[3*NUM_DQ_PINS - 1:3*NUM_DQ_PINS - 4]}; + w1data[2*NUM_DQ_PINS - 1:1*NUM_DQ_PINS] <= #TCQ {w1data[2*NUM_DQ_PINS - 5:1*NUM_DQ_PINS ],w1data[2*NUM_DQ_PINS - 1:2*NUM_DQ_PINS - 4]}; + w1data[1*NUM_DQ_PINS - 1:0*NUM_DQ_PINS] <= #TCQ {w1data[1*NUM_DQ_PINS - 5:0*NUM_DQ_PINS ],w1data[1*NUM_DQ_PINS - 1:1*NUM_DQ_PINS - 4]}; + end + end + end + endgenerate + + generate + if ((NUM_DQ_PINS == 72 ) && (DATA_PATTERN == "DGEN_NEIGHBOR" || DATA_PATTERN == "DGEN_WALKING1" || DATA_PATTERN == "DGEN_WALKING0" || DATA_PATTERN == "DGEN_ALL")) begin : WALKING_ONE_72_PATTERN + always @ (posedge clk_i) begin + + + if( (fifo_rdy_i ) || cmd_startC ) + if (cmd_startC ) begin + if (sel_w1gen_logic) begin + case (addr_i[9:5]) + + 0, 18: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(0); + else + w1data <= #TCQ Data_GenW0(0); + + 1, 19: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(1); + else + w1data <= #TCQ Data_GenW0(1); + + 2, 20: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(2); + else + w1data <= #TCQ Data_GenW0(2); + + 3, 21: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(3); + else + w1data <= #TCQ Data_GenW0(3); + + 4, 22: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(4); + else + w1data <= #TCQ Data_GenW0(4); + + 5, 23: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(5); + else + w1data <= #TCQ Data_GenW0(5); + + 6, 24: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(6); + else + w1data <= #TCQ Data_GenW0(6); + + 7, 25: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(7); + else + w1data <= #TCQ Data_GenW0(7); + + 8, 26: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(8); + else + w1data <= #TCQ Data_GenW0(8); + + 9, 27: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(9); + else + w1data <= #TCQ Data_GenW0(9); + + 10, 28: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(10); + else + w1data <= #TCQ Data_GenW0(10); + + 11, 29: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(11); + else + w1data <= #TCQ Data_GenW0(11); + + 12, 30: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(12); + else + w1data <= #TCQ Data_GenW0(12); + + 13, 31: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(13); + else + w1data <= #TCQ Data_GenW0(13); + + 14: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(14); + else + w1data <= #TCQ Data_GenW0(14); + + 15: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(15); + else + w1data <= #TCQ Data_GenW0(15); + + 16: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(16); + else + w1data <= #TCQ Data_GenW0(16); + + 17: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(17); + else + w1data <= #TCQ Data_GenW0(17); + default : + w1data[4*NUM_DQ_PINS-1:0*NUM_DQ_PINS ] <= #TCQ 'b0; + + endcase + end + end + else if ( MEM_BURST_LEN == 8) begin + w1data[4*NUM_DQ_PINS - 1:3*NUM_DQ_PINS] <= #TCQ {w1data[4*NUM_DQ_PINS - 5:3*NUM_DQ_PINS ],w1data[4*NUM_DQ_PINS - 1:4*NUM_DQ_PINS - 4]}; + w1data[3*NUM_DQ_PINS - 1:2*NUM_DQ_PINS] <= #TCQ {w1data[3*NUM_DQ_PINS - 5:2*NUM_DQ_PINS ],w1data[3*NUM_DQ_PINS - 1:3*NUM_DQ_PINS - 4]}; + w1data[2*NUM_DQ_PINS - 1:1*NUM_DQ_PINS] <= #TCQ {w1data[2*NUM_DQ_PINS - 5:1*NUM_DQ_PINS ],w1data[2*NUM_DQ_PINS - 1:2*NUM_DQ_PINS - 4]}; + w1data[1*NUM_DQ_PINS - 1:0*NUM_DQ_PINS] <= #TCQ {w1data[1*NUM_DQ_PINS - 5:0*NUM_DQ_PINS ],w1data[1*NUM_DQ_PINS - 1:1*NUM_DQ_PINS - 4]}; + end + end + end + endgenerate + + generate + if ((NUM_DQ_PINS == 80 ) && (DATA_PATTERN == "DGEN_NEIGHBOR" || DATA_PATTERN == "DGEN_WALKING1" || DATA_PATTERN == "DGEN_WALKING0" || DATA_PATTERN == "DGEN_ALL")) begin : WALKING_ONE_80_PATTERN + always @ (posedge clk_i) begin + + + if( (fifo_rdy_i ) || cmd_startC ) + if (cmd_startC ) begin + if (sel_w1gen_logic) begin + case (addr_i[9:5]) + 0, 20: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(0); + else + w1data <= #TCQ Data_GenW0(0); + + 1, 21: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(1); + else + w1data <= #TCQ Data_GenW0(1); + + 2, 22: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(2); + else + w1data <= #TCQ Data_GenW0(2); + + 3, 23: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(3); + else + w1data <= #TCQ Data_GenW0(3); + + 4, 24: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(4); + else + w1data <= #TCQ Data_GenW0(4); + + 5, 25: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(5); + else + w1data <= #TCQ Data_GenW0(5); + + 6, 26: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(6); + else + w1data <= #TCQ Data_GenW0(6); + + 7, 27: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(7); + else + w1data <= #TCQ Data_GenW0(7); + + 8, 28: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(8); + else + w1data <= #TCQ Data_GenW0(8); + + 9, 29: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(9); + else + w1data <= #TCQ Data_GenW0(9); + + 10, 30: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(10); + else + w1data <= #TCQ Data_GenW0(10); + + 11, 31: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(11); + else + w1data <= #TCQ Data_GenW0(11); + + 12: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(12); + else + w1data <= #TCQ Data_GenW0(12); + + 13: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(13); + else + w1data <= #TCQ Data_GenW0(13); + + 14: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(14); + else + w1data <= #TCQ Data_GenW0(14); + + 15: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(15); + else + w1data <= #TCQ Data_GenW0(15); + + 16: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(16); + else + w1data <= #TCQ Data_GenW0(16); + + 17: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(17); + else + w1data <= #TCQ Data_GenW0(17); + + 18: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(18); + else + w1data <= #TCQ Data_GenW0(18); + + 19: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(19); + else + w1data <= #TCQ Data_GenW0(19); + default : + w1data[4*NUM_DQ_PINS-1:0*NUM_DQ_PINS ] <= #TCQ 'b0; + + endcase + end + end + else if ( MEM_BURST_LEN == 8) begin + w1data[4*NUM_DQ_PINS - 1:3*NUM_DQ_PINS] <= #TCQ {w1data[4*NUM_DQ_PINS - 5:3*NUM_DQ_PINS ],w1data[4*NUM_DQ_PINS - 1:4*NUM_DQ_PINS - 4]}; + w1data[3*NUM_DQ_PINS - 1:2*NUM_DQ_PINS] <= #TCQ {w1data[3*NUM_DQ_PINS - 5:2*NUM_DQ_PINS ],w1data[3*NUM_DQ_PINS - 1:3*NUM_DQ_PINS - 4]}; + w1data[2*NUM_DQ_PINS - 1:1*NUM_DQ_PINS] <= #TCQ {w1data[2*NUM_DQ_PINS - 5:1*NUM_DQ_PINS ],w1data[2*NUM_DQ_PINS - 1:2*NUM_DQ_PINS - 4]}; + w1data[1*NUM_DQ_PINS - 1:0*NUM_DQ_PINS] <= #TCQ {w1data[1*NUM_DQ_PINS - 5:0*NUM_DQ_PINS ],w1data[1*NUM_DQ_PINS - 1:1*NUM_DQ_PINS - 4]}; + end + end + end + endgenerate + + + generate + if ((NUM_DQ_PINS == 88 ) && (DATA_PATTERN == "DGEN_NEIGHBOR" || DATA_PATTERN == "DGEN_WALKING1" || DATA_PATTERN == "DGEN_WALKING0" || DATA_PATTERN == "DGEN_ALL")) begin : WALKING_ONE_88_PATTERN + always @ (posedge clk_i) begin + + + if( (fifo_rdy_i ) || cmd_startC ) + if (cmd_startC ) begin + if (sel_w1gen_logic) begin + case (addr_i[9:5]) + + 0, 22: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(0); + else + w1data <= #TCQ Data_GenW0(0); + + 1, 23: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(1); + else + w1data <= #TCQ Data_GenW0(1); + + 2, 24: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(2); + else + w1data <= #TCQ Data_GenW0(2); + + 3, 25: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(3); + else + w1data <= #TCQ Data_GenW0(3); + + 4, 26: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(4); + else + w1data <= #TCQ Data_GenW0(4); + + 5, 27: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(5); + else + w1data <= #TCQ Data_GenW0(5); + + 6, 28: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(6); + else + w1data <= #TCQ Data_GenW0(6); + + 7, 29: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(7); + else + w1data <= #TCQ Data_GenW0(7); + + 8, 30: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(8); + else + w1data <= #TCQ Data_GenW0(8); + + 9, 31: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(9); + else + w1data <= #TCQ Data_GenW0(9); + + 10: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(10); + else + w1data <= #TCQ Data_GenW0(10); + + 11: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(11); + else + w1data <= #TCQ Data_GenW0(11); + + 12: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(12); + else + w1data <= #TCQ Data_GenW0(12); + + 13: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(13); + else + w1data <= #TCQ Data_GenW0(13); + + 14: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(14); + else + w1data <= #TCQ Data_GenW0(14); + + 15: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(15); + else + w1data <= #TCQ Data_GenW0(15); + + 16: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(16); + else + w1data <= #TCQ Data_GenW0(16); + + 17: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(17); + else + w1data <= #TCQ Data_GenW0(17); + + 18: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(18); + else + w1data <= #TCQ Data_GenW0(18); + + 19: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(19); + else + w1data <= #TCQ Data_GenW0(19); + + 20: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(20); + else + w1data <= #TCQ Data_GenW0(20); + + 21: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(21); + else + w1data <= #TCQ Data_GenW0(21); + default : + w1data[4*NUM_DQ_PINS-1:0*NUM_DQ_PINS ] <= #TCQ 'b0; + + endcase + end + end + else if ( MEM_BURST_LEN == 8) begin + w1data[4*NUM_DQ_PINS - 1:3*NUM_DQ_PINS] <= #TCQ {w1data[4*NUM_DQ_PINS - 5:3*NUM_DQ_PINS ],w1data[4*NUM_DQ_PINS - 1:4*NUM_DQ_PINS - 4]}; + w1data[3*NUM_DQ_PINS - 1:2*NUM_DQ_PINS] <= #TCQ {w1data[3*NUM_DQ_PINS - 5:2*NUM_DQ_PINS ],w1data[3*NUM_DQ_PINS - 1:3*NUM_DQ_PINS - 4]}; + w1data[2*NUM_DQ_PINS - 1:1*NUM_DQ_PINS] <= #TCQ {w1data[2*NUM_DQ_PINS - 5:1*NUM_DQ_PINS ],w1data[2*NUM_DQ_PINS - 1:2*NUM_DQ_PINS - 4]}; + w1data[1*NUM_DQ_PINS - 1:0*NUM_DQ_PINS] <= #TCQ {w1data[1*NUM_DQ_PINS - 5:0*NUM_DQ_PINS ],w1data[1*NUM_DQ_PINS - 1:1*NUM_DQ_PINS - 4]}; + end + end + end + endgenerate + + generate + if ((NUM_DQ_PINS == 96 ) && (DATA_PATTERN == "DGEN_NEIGHBOR" || DATA_PATTERN == "DGEN_WALKING1" || DATA_PATTERN == "DGEN_WALKING0" || DATA_PATTERN == "DGEN_ALL")) begin : WALKING_ONE_96_PATTERN + always @ (posedge clk_i) begin + + + if( (fifo_rdy_i ) || cmd_startC ) + if (cmd_startC ) begin + if (sel_w1gen_logic) begin + case (addr_i[9:5]) + + 0, 24: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(0); + else + w1data <= #TCQ Data_GenW0(0); + + 1, 25: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(1); + else + w1data <= #TCQ Data_GenW0(1); + + 2, 26: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(2); + else + w1data <= #TCQ Data_GenW0(2); + + 3, 27: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(3); + else + w1data <= #TCQ Data_GenW0(3); + + 4, 28: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(4); + else + w1data <= #TCQ Data_GenW0(4); + + 5, 29: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(5); + else + w1data <= #TCQ Data_GenW0(5); + + 6, 30: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(6); + else + w1data <= #TCQ Data_GenW0(6); + + 7, 31: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(7); + else + w1data <= #TCQ Data_GenW0(7); + + 8: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(8); + else + w1data <= #TCQ Data_GenW0(8); + + 9: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(9); + else + w1data <= #TCQ Data_GenW0(9); + + 10: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(10); + else + w1data <= #TCQ Data_GenW0(10); + + 11: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(11); + else + w1data <= #TCQ Data_GenW0(11); + + 12: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(12); + else + w1data <= #TCQ Data_GenW0(12); + + 13: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(13); + else + w1data <= #TCQ Data_GenW0(13); + + 14: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(14); + else + w1data <= #TCQ Data_GenW0(14); + + 15: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(15); + else + w1data <= #TCQ Data_GenW0(15); + + 16: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(16); + else + w1data <= #TCQ Data_GenW0(16); + + 17: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(17); + else + w1data <= #TCQ Data_GenW0(17); + + 18: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(18); + else + w1data <= #TCQ Data_GenW0(18); + + 19: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(19); + else + w1data <= #TCQ Data_GenW0(19); + + 20: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(20); + else + w1data <= #TCQ Data_GenW0(20); + + 21: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(21); + else + w1data <= #TCQ Data_GenW0(21); + + 22: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(22); + else + w1data <= #TCQ Data_GenW0(22); + + 23: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(23); + else + w1data <= #TCQ Data_GenW0(23); + default : + w1data[4*NUM_DQ_PINS-1:0*NUM_DQ_PINS ] <= #TCQ 'b0; + + endcase + end + end + else if ( MEM_BURST_LEN == 8) begin + w1data[4*NUM_DQ_PINS - 1:3*NUM_DQ_PINS] <= #TCQ {w1data[4*NUM_DQ_PINS - 5:3*NUM_DQ_PINS ],w1data[4*NUM_DQ_PINS - 1:4*NUM_DQ_PINS - 4]}; + w1data[3*NUM_DQ_PINS - 1:2*NUM_DQ_PINS] <= #TCQ {w1data[3*NUM_DQ_PINS - 5:2*NUM_DQ_PINS ],w1data[3*NUM_DQ_PINS - 1:3*NUM_DQ_PINS - 4]}; + w1data[2*NUM_DQ_PINS - 1:1*NUM_DQ_PINS] <= #TCQ {w1data[2*NUM_DQ_PINS - 5:1*NUM_DQ_PINS ],w1data[2*NUM_DQ_PINS - 1:2*NUM_DQ_PINS - 4]}; + w1data[1*NUM_DQ_PINS - 1:0*NUM_DQ_PINS] <= #TCQ {w1data[1*NUM_DQ_PINS - 5:0*NUM_DQ_PINS ],w1data[1*NUM_DQ_PINS - 1:1*NUM_DQ_PINS - 4]}; + end + end + end + endgenerate + + generate + if ((NUM_DQ_PINS == 104 ) && (DATA_PATTERN == "DGEN_NEIGHBOR" || DATA_PATTERN == "DGEN_WALKING1" || DATA_PATTERN == "DGEN_WALKING0" || DATA_PATTERN == "DGEN_ALL")) begin : WALKING_ONE_104_PATTERN + always @ (posedge clk_i) begin + + + if( (fifo_rdy_i ) || cmd_startC ) + if (cmd_startC ) begin + if (sel_w1gen_logic) begin + case (addr_i[9:5]) + 0, 26: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(0); + else + w1data <= #TCQ Data_GenW0(0); + + 1, 27: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(1); + else + w1data <= #TCQ Data_GenW0(1); + + 2, 28: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(2); + else + w1data <= #TCQ Data_GenW0(2); + + 3, 29: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(3); + else + w1data <= #TCQ Data_GenW0(3); + + 4, 30: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(4); + else + w1data <= #TCQ Data_GenW0(4); + + 5, 31: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(5); + else + w1data <= #TCQ Data_GenW0(5); + 6 : + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(6); + else + w1data <= #TCQ Data_GenW0(6); + + 7: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(7); + else + w1data <= #TCQ Data_GenW0(7); + + 8: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(8); + else + w1data <= #TCQ Data_GenW0(8); + + 9: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(9); + else + w1data <= #TCQ Data_GenW0(9); + + 10: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(10); + else + w1data <= #TCQ Data_GenW0(10); + + 11: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(11); + else + w1data <= #TCQ Data_GenW0(11); + + 12: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(12); + else + w1data <= #TCQ Data_GenW0(12); + + 13: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(13); + else + w1data <= #TCQ Data_GenW0(13); + + 14: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(14); + else + w1data <= #TCQ Data_GenW0(14); + + 15: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(15); + else + w1data <= #TCQ Data_GenW0(15); + + 16: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(16); + else + w1data <= #TCQ Data_GenW0(16); + + 17: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(17); + else + w1data <= #TCQ Data_GenW0(17); + + 18: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(18); + else + w1data <= #TCQ Data_GenW0(18); + + 19: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(19); + else + w1data <= #TCQ Data_GenW0(19); + + 20: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(20); + else + w1data <= #TCQ Data_GenW0(20); + + 21: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(21); + else + w1data <= #TCQ Data_GenW0(21); + + 22: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(22); + else + w1data <= #TCQ Data_GenW0(22); + + 23: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(23); + else + w1data <= #TCQ Data_GenW0(23); + + 24: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(24); + else + w1data <= #TCQ Data_GenW0(24); + + 25: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(25); + else + w1data <= #TCQ Data_GenW0(25); + default : + w1data[4*NUM_DQ_PINS-1:0*NUM_DQ_PINS ] <= #TCQ 'b0; + endcase + end + end + else if ( MEM_BURST_LEN == 8) begin + w1data[4*NUM_DQ_PINS - 1:3*NUM_DQ_PINS] <= #TCQ {w1data[4*NUM_DQ_PINS - 5:3*NUM_DQ_PINS ],w1data[4*NUM_DQ_PINS - 1:4*NUM_DQ_PINS - 4]}; + w1data[3*NUM_DQ_PINS - 1:2*NUM_DQ_PINS] <= #TCQ {w1data[3*NUM_DQ_PINS - 5:2*NUM_DQ_PINS ],w1data[3*NUM_DQ_PINS - 1:3*NUM_DQ_PINS - 4]}; + w1data[2*NUM_DQ_PINS - 1:1*NUM_DQ_PINS] <= #TCQ {w1data[2*NUM_DQ_PINS - 5:1*NUM_DQ_PINS ],w1data[2*NUM_DQ_PINS - 1:2*NUM_DQ_PINS - 4]}; + w1data[1*NUM_DQ_PINS - 1:0*NUM_DQ_PINS] <= #TCQ {w1data[1*NUM_DQ_PINS - 5:0*NUM_DQ_PINS ],w1data[1*NUM_DQ_PINS - 1:1*NUM_DQ_PINS - 4]}; + end + end + end + endgenerate + + generate + if((NUM_DQ_PINS == 112 ) && (DATA_PATTERN == "DGEN_NEIGHBOR" || DATA_PATTERN == "DGEN_WALKING1" || DATA_PATTERN == "DGEN_WALKING0" || DATA_PATTERN == "DGEN_ALL")) begin : WALKING_ONE_112_PATTERN + always @ (posedge clk_i) begin + + + if( (fifo_rdy_i ) || cmd_startC ) + if (cmd_startC ) begin + if (sel_w1gen_logic) begin + case (addr_i[9:5]) + 0, 28: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(0); + else + w1data <= #TCQ Data_GenW0(0); + + 1, 29: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(1); + else + w1data <= #TCQ Data_GenW0(1); + + 2, 30: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(2); + else + w1data <= #TCQ Data_GenW0(2); + + 3, 31: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(3); + else + w1data <= #TCQ Data_GenW0(3); + + 4: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(4); + else + w1data <= #TCQ Data_GenW0(4); + + 5: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(5); + else + w1data <= #TCQ Data_GenW0(5); + + + + 6 : + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(6); + else + w1data <= #TCQ Data_GenW0(6); + + 7: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(7); + else + w1data <= #TCQ Data_GenW0(7); + + 8: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(8); + else + w1data <= #TCQ Data_GenW0(8); + + 9: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(9); + else + w1data <= #TCQ Data_GenW0(9); + + 10: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(10); + else + w1data <= #TCQ Data_GenW0(10); + + 11: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(11); + else + w1data <= #TCQ Data_GenW0(11); + + 12: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(12); + else + w1data <= #TCQ Data_GenW0(12); + + 13: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(13); + else + w1data <= #TCQ Data_GenW0(13); + + 14: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(14); + else + w1data <= #TCQ Data_GenW0(14); + + 15: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(15); + else + w1data <= #TCQ Data_GenW0(15); + + 16: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(16); + else + w1data <= #TCQ Data_GenW0(16); + + 17: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(17); + else + w1data <= #TCQ Data_GenW0(17); + + 18: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(18); + else + w1data <= #TCQ Data_GenW0(18); + + 19: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(19); + else + w1data <= #TCQ Data_GenW0(19); + + 20: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(20); + else + w1data <= #TCQ Data_GenW0(20); + + 21: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(21); + else + w1data <= #TCQ Data_GenW0(21); + + 22: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(22); + else + w1data <= #TCQ Data_GenW0(22); + + 23: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(23); + else + w1data <= #TCQ Data_GenW0(23); + + 24: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(24); + else + w1data <= #TCQ Data_GenW0(24); + + 25: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(25); + else + w1data <= #TCQ Data_GenW0(25); + + + 26: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(26); + else + w1data <= #TCQ Data_GenW0(26); + + 27: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(27); + else + w1data <= #TCQ Data_GenW0(27); + default : + w1data[4*NUM_DQ_PINS-1:0*NUM_DQ_PINS ] <= #TCQ 'b0; + endcase + end + end + else if ( MEM_BURST_LEN == 8) begin + w1data[4*NUM_DQ_PINS - 1:3*NUM_DQ_PINS] <= #TCQ {w1data[4*NUM_DQ_PINS - 5:3*NUM_DQ_PINS ],w1data[4*NUM_DQ_PINS - 1:4*NUM_DQ_PINS - 4]}; + w1data[3*NUM_DQ_PINS - 1:2*NUM_DQ_PINS] <= #TCQ {w1data[3*NUM_DQ_PINS - 5:2*NUM_DQ_PINS ],w1data[3*NUM_DQ_PINS - 1:3*NUM_DQ_PINS - 4]}; + w1data[2*NUM_DQ_PINS - 1:1*NUM_DQ_PINS] <= #TCQ {w1data[2*NUM_DQ_PINS - 5:1*NUM_DQ_PINS ],w1data[2*NUM_DQ_PINS - 1:2*NUM_DQ_PINS - 4]}; + w1data[1*NUM_DQ_PINS - 1:0*NUM_DQ_PINS] <= #TCQ {w1data[1*NUM_DQ_PINS - 5:0*NUM_DQ_PINS ],w1data[1*NUM_DQ_PINS - 1:1*NUM_DQ_PINS - 4]}; + end + end + end + endgenerate + + + + generate + if ((NUM_DQ_PINS == 120 ) && (DATA_PATTERN == "DGEN_NEIGHBOR" || DATA_PATTERN == "DGEN_WALKING1" || DATA_PATTERN == "DGEN_WALKING0" || DATA_PATTERN == "DGEN_ALL")) begin : WALKING_ONE_120_PATTERN + always @ (posedge clk_i) begin + + + if( (fifo_rdy_i ) || cmd_startC ) + if (cmd_startC ) begin + if (sel_w1gen_logic) begin + case (addr_i[9:5]) + 0, 30: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(0); + else + w1data <= #TCQ Data_GenW0(0); + + 1, 31: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(1); + else + w1data <= #TCQ Data_GenW0(1); + + 2: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(2); + else + w1data <= #TCQ Data_GenW0(2); + + 3: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(3); + else + w1data <= #TCQ Data_GenW0(3); + 4: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(4); + else + w1data <= #TCQ Data_GenW0(4); + + 5: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(5); + else + w1data <= #TCQ Data_GenW0(5); + 6 : + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(6); + else + w1data <= #TCQ Data_GenW0(6); + 7: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(7); + else + w1data <= #TCQ Data_GenW0(7); + 8: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(8); + else + w1data <= #TCQ Data_GenW0(8); + + 9: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(9); + else + w1data <= #TCQ Data_GenW0(9); + + 10: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(10); + else + w1data <= #TCQ Data_GenW0(10); + + 11: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(11); + else + w1data <= #TCQ Data_GenW0(11); + + 12: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(12); + else + w1data <= #TCQ Data_GenW0(12); + + 13: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(13); + else + w1data <= #TCQ Data_GenW0(13); + + 14: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(14); + else + w1data <= #TCQ Data_GenW0(14); + + 15: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(15); + else + w1data <= #TCQ Data_GenW0(15); + + 16: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(16); + else + w1data <= #TCQ Data_GenW0(16); + + 17: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(17); + else + w1data <= #TCQ Data_GenW0(17); + + 18: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(18); + else + w1data <= #TCQ Data_GenW0(18); + + 19: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(19); + else + w1data <= #TCQ Data_GenW0(19); + + 20: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(20); + else + w1data <= #TCQ Data_GenW0(20); + + 21: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(21); + else + w1data <= #TCQ Data_GenW0(21); + + 22: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(22); + else + w1data <= #TCQ Data_GenW0(22); + + 23: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(23); + else + w1data <= #TCQ Data_GenW0(23); + + 24: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(24); + else + w1data <= #TCQ Data_GenW0(24); + + 25: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(25); + else + w1data <= #TCQ Data_GenW0(25); + + + 26: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(26); + else + w1data <= #TCQ Data_GenW0(26); + + 27: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(27); + else + w1data <= #TCQ Data_GenW0(27); + + + 28: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(28); + else + w1data <= #TCQ Data_GenW0(28); + + 29: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(29); + else + w1data <= #TCQ Data_GenW0(29); + default : + w1data[4*NUM_DQ_PINS-1:0*NUM_DQ_PINS ] <= #TCQ 'b0; + endcase + end + end + else if ( MEM_BURST_LEN == 8) begin + w1data[4*NUM_DQ_PINS - 1:3*NUM_DQ_PINS] <= #TCQ {w1data[4*NUM_DQ_PINS - 5:3*NUM_DQ_PINS ],w1data[4*NUM_DQ_PINS - 1:4*NUM_DQ_PINS - 4]}; + w1data[3*NUM_DQ_PINS - 1:2*NUM_DQ_PINS] <= #TCQ {w1data[3*NUM_DQ_PINS - 5:2*NUM_DQ_PINS ],w1data[3*NUM_DQ_PINS - 1:3*NUM_DQ_PINS - 4]}; + w1data[2*NUM_DQ_PINS - 1:1*NUM_DQ_PINS] <= #TCQ {w1data[2*NUM_DQ_PINS - 5:1*NUM_DQ_PINS ],w1data[2*NUM_DQ_PINS - 1:2*NUM_DQ_PINS - 4]}; + w1data[1*NUM_DQ_PINS - 1:0*NUM_DQ_PINS] <= #TCQ {w1data[1*NUM_DQ_PINS - 5:0*NUM_DQ_PINS ],w1data[1*NUM_DQ_PINS - 1:1*NUM_DQ_PINS - 4]}; + end + end + end + endgenerate + + generate + if ((NUM_DQ_PINS == 128 ) && (DATA_PATTERN == "DGEN_NEIGHBOR" || DATA_PATTERN == "DGEN_WALKING1" || DATA_PATTERN == "DGEN_WALKING0" || DATA_PATTERN == "DGEN_ALL")) begin : WALKING_ONE_128_PATTERN + always @ (posedge clk_i) begin + + + if( (fifo_rdy_i ) || cmd_startC ) + if (cmd_startC ) begin + if (sel_w1gen_logic) begin + case (addr_i[10:6]) + + 0: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(0); + else + w1data <= #TCQ Data_GenW0(0); + + 1: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(1); + else + w1data <= #TCQ Data_GenW0(1); + + 2: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(2); + else + w1data <= #TCQ Data_GenW0(2); + + 3: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(3); + else + w1data <= #TCQ Data_GenW0(3); + 4: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(4); + else + w1data <= #TCQ Data_GenW0(4); + + 5: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(5); + else + w1data <= #TCQ Data_GenW0(5); + + 6 : + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(6); + else + w1data <= #TCQ Data_GenW0(6); + + 7: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(7); + else + w1data <= #TCQ Data_GenW0(7); + + 8: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(8); + else + w1data <= #TCQ Data_GenW0(8); + + 9: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(9); + else + w1data <= #TCQ Data_GenW0(9); + + 10: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(10); + else + w1data <= #TCQ Data_GenW0(10); + + 11: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(11); + else + w1data <= #TCQ Data_GenW0(11); + + 12: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(12); + else + w1data <= #TCQ Data_GenW0(12); + + 13: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(13); + else + w1data <= #TCQ Data_GenW0(13); + + 14: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(14); + else + w1data <= #TCQ Data_GenW0(14); + + 15: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(15); + else + w1data <= #TCQ Data_GenW0(15); + + 16: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(16); + else + w1data <= #TCQ Data_GenW0(16); + + 17: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(17); + else + w1data <= #TCQ Data_GenW0(17); + + 18: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(18); + else + w1data <= #TCQ Data_GenW0(18); + + 19: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(19); + else + w1data <= #TCQ Data_GenW0(19); + + 20: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(20); + else + w1data <= #TCQ Data_GenW0(20); + + 21: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(21); + else + w1data <= #TCQ Data_GenW0(21); + + 22: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(22); + else + w1data <= #TCQ Data_GenW0(22); + + 23: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(23); + else + w1data <= #TCQ Data_GenW0(23); + + 24: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(24); + else + w1data <= #TCQ Data_GenW0(24); + + 25: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(25); + else + w1data <= #TCQ Data_GenW0(25); + + + 26: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(26); + else + w1data <= #TCQ Data_GenW0(26); + + 27: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(27); + else + w1data <= #TCQ Data_GenW0(27); + + + 28: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(28); + else + w1data <= #TCQ Data_GenW0(28); + + 29: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(29); + else + w1data <= #TCQ Data_GenW0(29); + + 30: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(30); + else + w1data <= #TCQ Data_GenW0(30); + + 31: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(31); + else + w1data <= #TCQ Data_GenW0(31); + default : + w1data[4*NUM_DQ_PINS-1:0*NUM_DQ_PINS ] <= #TCQ 'b0; + endcase + end + end + else if ( MEM_BURST_LEN == 8) begin + w1data[4*NUM_DQ_PINS - 1:3*NUM_DQ_PINS] <= #TCQ {w1data[4*NUM_DQ_PINS - 5:3*NUM_DQ_PINS ],w1data[4*NUM_DQ_PINS - 1:4*NUM_DQ_PINS - 4]}; + w1data[3*NUM_DQ_PINS - 1:2*NUM_DQ_PINS] <= #TCQ {w1data[3*NUM_DQ_PINS - 5:2*NUM_DQ_PINS ],w1data[3*NUM_DQ_PINS - 1:3*NUM_DQ_PINS - 4]}; + w1data[2*NUM_DQ_PINS - 1:1*NUM_DQ_PINS] <= #TCQ {w1data[2*NUM_DQ_PINS - 5:1*NUM_DQ_PINS ],w1data[2*NUM_DQ_PINS - 1:2*NUM_DQ_PINS - 4]}; + w1data[1*NUM_DQ_PINS - 1:0*NUM_DQ_PINS] <= #TCQ {w1data[1*NUM_DQ_PINS - 5:0*NUM_DQ_PINS ],w1data[1*NUM_DQ_PINS - 1:1*NUM_DQ_PINS - 4]}; + end + end + end + endgenerate + + generate + if ((NUM_DQ_PINS == 136 ) && (DATA_PATTERN == "DGEN_NEIGHBOR" || DATA_PATTERN == "DGEN_WALKING1" || DATA_PATTERN == "DGEN_WALKING0" || DATA_PATTERN == "DGEN_ALL")) begin : WALKING_ONE_136_PATTERN + always @ (posedge clk_i) begin + + + if( (fifo_rdy_i ) || cmd_startC ) + if (cmd_startC ) begin + if (sel_w1gen_logic) begin + case (addr_i[11:6]) + + 0: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(0); + else + w1data <= #TCQ Data_GenW0(0); + + + 1, 35: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(1); + else + w1data <= #TCQ Data_GenW0(1); + + + 2, 36: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(2); + else + w1data <= #TCQ Data_GenW0(2); + + + 3, 37: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(3); + else + w1data <= #TCQ Data_GenW0(3); + + + 4, 38: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(4); + else + w1data <= #TCQ Data_GenW0(4); + + + 5, 39: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(5); + else + w1data <= #TCQ Data_GenW0(5); + + + 6, 40: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(6); + else + w1data <= #TCQ Data_GenW0(6); + + + 7, 41: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(7); + else + w1data <= #TCQ Data_GenW0(7); + + + 8, 42: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(8); + else + w1data <= #TCQ Data_GenW0(8); + + + 9, 43: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(9); + else + w1data <= #TCQ Data_GenW0(9); + + + 10, 44: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(10); + else + w1data <= #TCQ Data_GenW0(10); + + + 11, 45: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(11); + else + w1data <= #TCQ Data_GenW0(11); + + + 12, 46: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(12); + else + w1data <= #TCQ Data_GenW0(12); + + + 13, 47: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(13); + else + w1data <= #TCQ Data_GenW0(13); + + + 14, 48: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(14); + else + w1data <= #TCQ Data_GenW0(14); + + + 15, 49: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(15); + else + w1data <= #TCQ Data_GenW0(15); + + + 16, 50: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(16); + else + w1data <= #TCQ Data_GenW0(16); + + + 17, 51: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(17); + else + w1data <= #TCQ Data_GenW0(17); + + + 18, 52: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(18); + else + w1data <= #TCQ Data_GenW0(18); + + + 19, 53: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(19); + else + w1data <= #TCQ Data_GenW0(19); + + + 20, 54: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(20); + else + w1data <= #TCQ Data_GenW0(20); + + + 21, 55: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(21); + else + w1data <= #TCQ Data_GenW0(21); + + + 22, 56: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(22); + else + w1data <= #TCQ Data_GenW0(22); + + + 23, 57: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(23); + else + w1data <= #TCQ Data_GenW0(23); + + + 24, 58: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(24); + else + w1data <= #TCQ Data_GenW0(24); + + + 25, 59: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(25); + else + w1data <= #TCQ Data_GenW0(25); + + + 26, 60: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(26); + else + w1data <= #TCQ Data_GenW0(26); + + + 27, 61: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(27); + else + w1data <= #TCQ Data_GenW0(27); + + + 28, 62: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(28); + else + w1data <= #TCQ Data_GenW0(28); + + + 29, 63: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(29); + else + w1data <= #TCQ Data_GenW0(29); + + + 30: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(30); + else + w1data <= #TCQ Data_GenW0(30); + + + 31: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(31); + else + w1data <= #TCQ Data_GenW0(31); + + + 32: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(32); + else + w1data <= #TCQ Data_GenW0(32); + + + 33: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(33); + else + w1data <= #TCQ Data_GenW0(33); + default : + w1data[4*NUM_DQ_PINS-1:0*NUM_DQ_PINS ] <= #TCQ 'b0; + endcase + end + end + else if ( MEM_BURST_LEN == 8) begin + w1data[4*NUM_DQ_PINS - 1:3*NUM_DQ_PINS] <= #TCQ {w1data[4*NUM_DQ_PINS - 5:3*NUM_DQ_PINS ],w1data[4*NUM_DQ_PINS - 1:4*NUM_DQ_PINS - 4]}; + w1data[3*NUM_DQ_PINS - 1:2*NUM_DQ_PINS] <= #TCQ {w1data[3*NUM_DQ_PINS - 5:2*NUM_DQ_PINS ],w1data[3*NUM_DQ_PINS - 1:3*NUM_DQ_PINS - 4]}; + w1data[2*NUM_DQ_PINS - 1:1*NUM_DQ_PINS] <= #TCQ {w1data[2*NUM_DQ_PINS - 5:1*NUM_DQ_PINS ],w1data[2*NUM_DQ_PINS - 1:2*NUM_DQ_PINS - 4]}; + w1data[1*NUM_DQ_PINS - 1:0*NUM_DQ_PINS] <= #TCQ {w1data[1*NUM_DQ_PINS - 5:0*NUM_DQ_PINS ],w1data[1*NUM_DQ_PINS - 1:1*NUM_DQ_PINS - 4]}; + end + end + end + endgenerate + + generate + if ((NUM_DQ_PINS == 144 ) && (DATA_PATTERN == "DGEN_NEIGHBOR" || DATA_PATTERN == "DGEN_WALKING1" || DATA_PATTERN == "DGEN_WALKING0" || DATA_PATTERN == "DGEN_ALL")) begin : WALKING_ONE_144_PATTERN + always @ (posedge clk_i) begin + + + if( (fifo_rdy_i ) || cmd_startC ) + if (cmd_startC ) begin + if (sel_w1gen_logic) begin + case (addr_i[11:6]) + + 0, 36: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(0); + else + w1data <= #TCQ Data_GenW0(0); + + + 1, 37 : + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(1); + else + w1data <= #TCQ Data_GenW0(1); + + + 2, 38: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(2); + else + w1data <= #TCQ Data_GenW0(2); + + + 3, 39 : + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(3); + else + w1data <= #TCQ Data_GenW0(3); + 4, 40 : + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(4); + else + w1data <= #TCQ Data_GenW0(4); + 5, 41: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(5); + else + w1data <= #TCQ Data_GenW0(5); + 6, 42: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(6); + else + w1data <= #TCQ Data_GenW0(6); + 7, 43: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(7); + else + w1data <= #TCQ Data_GenW0(7); + 8, 44: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(8); + else + w1data <= #TCQ Data_GenW0(8); + 9, 45: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(9); + else + w1data <= #TCQ Data_GenW0(9); + 10, 46: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(10); + else + w1data <= #TCQ Data_GenW0(10); + 11, 47 : + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(11); + else + w1data <= #TCQ Data_GenW0(11); + 12, 48 : + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(12); + else + w1data <= #TCQ Data_GenW0(12); + 13, 49 : + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(13); + else + w1data <= #TCQ Data_GenW0(13); + 14, 50: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(14); + else + w1data <= #TCQ Data_GenW0(14); + 15, 51 : + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(15); + else + w1data <= #TCQ Data_GenW0(15); + 16, 52 : + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(16); + else + w1data <= #TCQ Data_GenW0(16); + 17 , 53: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(17); + else + w1data <= #TCQ Data_GenW0(17); + 18, 54: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(18); + else + w1data <= #TCQ Data_GenW0(18); + 19, 55: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(19); + else + w1data <= #TCQ Data_GenW0(19); + 20, 56: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(20); + else + w1data <= #TCQ Data_GenW0(20); + 21, 57: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(21); + else + w1data <= #TCQ Data_GenW0(21); + 22, 58: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(22); + else + w1data <= #TCQ Data_GenW0(22); + 23, 59: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(23); + else + w1data <= #TCQ Data_GenW0(23); + 24, 60: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(24); + else + w1data <= #TCQ Data_GenW0(24); + 25, 61: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(25); + else + w1data <= #TCQ Data_GenW0(25); + 26, 62: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(26); + else + w1data <= #TCQ Data_GenW0(26); + 27, 63: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(27); + else + w1data <= #TCQ Data_GenW0(27); + 28: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(28); + else + w1data <= #TCQ Data_GenW0(28); + + 29: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(29); + else + w1data <= #TCQ Data_GenW0(29); + + 30: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(30); + else + w1data <= #TCQ Data_GenW0(30); + + 31: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(31); + else + w1data <= #TCQ Data_GenW0(31); + 32: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(32); + else + w1data <= #TCQ Data_GenW0(32); + 33: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(33); + else + w1data <= #TCQ Data_GenW0(33); + 34: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(34); + else + w1data <= #TCQ Data_GenW0(34); + 35: + if (data_mode_i == 4'b0101) + w1data <= #TCQ Data_Gen(35); + else + w1data <= #TCQ Data_GenW0(35); + + default : + w1data[4*NUM_DQ_PINS-1:0*NUM_DQ_PINS ] <= #TCQ 'b0; + + endcase + end + end + else if ( MEM_BURST_LEN == 8) begin + w1data[4*NUM_DQ_PINS - 1:3*NUM_DQ_PINS] <= #TCQ {w1data[4*NUM_DQ_PINS - 5:3*NUM_DQ_PINS ],w1data[4*NUM_DQ_PINS - 1:4*NUM_DQ_PINS - 4]}; + w1data[3*NUM_DQ_PINS - 1:2*NUM_DQ_PINS] <= #TCQ {w1data[3*NUM_DQ_PINS - 5:2*NUM_DQ_PINS ],w1data[3*NUM_DQ_PINS - 1:3*NUM_DQ_PINS - 4]}; + w1data[2*NUM_DQ_PINS - 1:1*NUM_DQ_PINS] <= #TCQ {w1data[2*NUM_DQ_PINS - 5:1*NUM_DQ_PINS ],w1data[2*NUM_DQ_PINS - 1:2*NUM_DQ_PINS - 4]}; + w1data[1*NUM_DQ_PINS - 1:0*NUM_DQ_PINS] <= #TCQ {w1data[1*NUM_DQ_PINS - 5:0*NUM_DQ_PINS ],w1data[1*NUM_DQ_PINS - 1:1*NUM_DQ_PINS - 4]}; + end + end + end + endgenerate + + + + +// HAMMER_PATTERN_MINUS: generate walking HAMMER data pattern except 1 bit for the whole burst. The incoming addr_i[5:2] determine +// the position of the pin driving oppsite polarity +// addr_i[6:2] = 5'h0f ; 32 bit data port +// => the rsing data pattern will be 32'b11111111_11111111_01111111_11111111 +// => the falling data pattern will be 32'b00000000_00000000_00000000_00000000 + + +//always @ (NUM_DQ_PINS,SEL_VICTIM_LINE) begin +always @ (posedge clk_i) begin + +for (i=0; i <= 4*NUM_DQ_PINS - 1; i= i+1) + if (i == SEL_VICTIM_LINE || (i-NUM_DQ_PINS) == SEL_VICTIM_LINE || + (i-(NUM_DQ_PINS*2)) == SEL_VICTIM_LINE || (i-(NUM_DQ_PINS*3)) == SEL_VICTIM_LINE) + hdata[i] <= #TCQ 1'b1; + else if ( i >= 0 && i <= 1*NUM_DQ_PINS - 1) + hdata[i] <= #TCQ 1'b1; + else if ( i >= 1*NUM_DQ_PINS && i <= 2*NUM_DQ_PINS - 1) + hdata[i] <= #TCQ 1'b0; + else if ( i >= 2*NUM_DQ_PINS && i <= 3*NUM_DQ_PINS - 1) + hdata[i] <= #TCQ 1'b1; + else if ( i >= 3*NUM_DQ_PINS && i <= 4*NUM_DQ_PINS - 1) + hdata[i] <= #TCQ 1'b0; + else + hdata[i] <= 1'b1; + + +end + + +always @ (w1data,hdata) +begin +for (i=0; i <= 4*NUM_DQ_PINS - 1; i= i+1) + ndata[i] = hdata[i] ^ w1data[i]; + + end + + +always @ (full_prbs_data,hdata,SEL_VICTIM_LINE) +begin +for (i=0; i <= 4*NUM_DQ_PINS - 1; i= i+1) + if (i == SEL_VICTIM_LINE || (i-NUM_DQ_PINS) == SEL_VICTIM_LINE || + (i-(NUM_DQ_PINS*2)) == SEL_VICTIM_LINE || (i-(NUM_DQ_PINS*3)) == SEL_VICTIM_LINE) + + h_prbsdata[i] = full_prbs_data[SEL_VICTIM_LINE]; + else + h_prbsdata[i] = hdata[i]; + + + end + + + +// ADDRESS_PATTERN: use the address as the 1st data pattern for the whole burst. For example +// Dataport 32 bit width with starting addr_i = 32'h12345678, user burst length 4 +// => the 1st data pattern : 32'h12345678 +// => the 2nd data pattern : 32'h12345679 +// => the 3rd data pattern : 32'h1234567a +// => the 4th data pattern : 32'h1234567b +generate + +if (DATA_PATTERN == "DGEN_ADDR" || DATA_PATTERN == "DGEN_ALL") begin : ADDRESS_PATTERN +always @ (posedge clk_i) +begin + if (cmd_startD) + acounts[35:0] <= #TCQ {4'b0000,addr_i}; + else if (fifo_rdy_i && data_rdy_i && MEM_BURST_LEN == 8 ) + if (NUM_DQ_PINS == 8) + acounts <= #TCQ acounts + 4; + else if (NUM_DQ_PINS == 16 || NUM_DQ_PINS == 24) + acounts <= #TCQ acounts + 8; + else if (NUM_DQ_PINS >= 32 && NUM_DQ_PINS < 64) + acounts <= #TCQ acounts + 16; + + else if (NUM_DQ_PINS >= 64 && NUM_DQ_PINS < 128 ) + acounts <= #TCQ acounts + 32; + + else if (NUM_DQ_PINS >= 128 && NUM_DQ_PINS < 256 ) + acounts <= #TCQ acounts + 64; + + +end + +assign adata = {DWIDTH/32{acounts[31:0]}}; +end +endgenerate + + +// PRBS_PATTERN: use the address as the PRBS seed data pattern for the whole burst. For example +// Dataport 32 bit width with starting addr_i = 30'h12345678, user burst length 4 +// +// +// +// + +generate +// When doing eye_test, traffic gen only does write and want to +// keep the prbs random and address is fixed at a location. +if (EYE_TEST == "TRUE") begin : d_clk_en1 +assign data_clk_en = 1'b1;//fifo_rdy_i && data_rdy_i && user_burst_cnt > 6'd1; +end +endgenerate + +generate +if (EYE_TEST == "FALSE") begin : d_clk_en2 +assign data_clk_en = fifo_rdy_i && data_rdy_i && user_burst_cnt > 6'd1; +end +endgenerate + +generate +if (DATA_PATTERN == "DGEN_PRBS" || DATA_PATTERN == "DGEN_ALL") begin : PRBS_PATTERN + +// PRBS DATA GENERATION +// xor all the tap positions before feedback to 1st stage. + + +data_prbs_gen # + ( + .PRBS_WIDTH (32), + .SEED_WIDTH (32), + .EYE_TEST (EYE_TEST) + ) + data_prbs_gen + ( + .clk_i (clk_i), + .rst_i (rst_i), + .clk_en (data_clk_en), + + .prbs_fseed_i (prbs_fseed_i), + .prbs_seed_init (cmd_startE), + .prbs_seed_i ({m_addr_i[6],m_addr_i[31],m_addr_i[8],m_addr_i[22],m_addr_i[9],m_addr_i[24],m_addr_i[21],m_addr_i[23], + m_addr_i[18],m_addr_i[10],m_addr_i[20],m_addr_i[17],m_addr_i[13],m_addr_i[16],m_addr_i[12],m_addr_i[4], + m_addr_i[15:0]}),//(m_addr_i[31:0]), + .prbs_o (prbs_data) + + ); +end +endgenerate + + +endmodule + diff --git "a/Frogwells_fpga_design/\345\237\272\344\272\216FPGA\343\200\201DDR3\345\222\214USB2.0\347\232\204\345\233\276\345\203\217\351\207\207\351\233\206\347\263\273\347\273\237/debug/ddr_test/rtl/traffic_gen/wr_data_gen.v" "b/Frogwells_fpga_design/\345\237\272\344\272\216FPGA\343\200\201DDR3\345\222\214USB2.0\347\232\204\345\233\276\345\203\217\351\207\207\351\233\206\347\263\273\347\273\237/debug/ddr_test/rtl/traffic_gen/wr_data_gen.v" new file mode 100644 index 0000000000000000000000000000000000000000..0de2046ca7854dfb5f6d67b88e68c9a53b68e028 --- /dev/null +++ "b/Frogwells_fpga_design/\345\237\272\344\272\216FPGA\343\200\201DDR3\345\222\214USB2.0\347\232\204\345\233\276\345\203\217\351\207\207\351\233\206\347\263\273\347\273\237/debug/ddr_test/rtl/traffic_gen/wr_data_gen.v" @@ -0,0 +1,410 @@ +//***************************************************************************** +// (c) Copyright 2008-2009 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: %version +// \ \ Application: MIG +// / / Filename: wr_data_gen.v +// /___/ /\ Date Last Modified: +// \ \ / \ Date Created: +// \___\/\___\ +// +//Device: Spartan6 +//Design Name: DDR/DDR2/DDR3/LPDDR +//Purpose: +//Reference: +//Revision History: +//***************************************************************************** + +`timescale 1ps/1ps + +module wr_data_gen # + +( + parameter TCQ = 100, + parameter FAMILY = "SPARTAN6", // "SPARTAN6", "VIRTEX6" + parameter MEM_BURST_LEN = 8, + + parameter MODE = "WR", //"WR", "RD" + parameter ADDR_WIDTH = 32, + parameter BL_WIDTH = 6, + parameter DWIDTH = 32, + parameter DATA_PATTERN = "DGEN_PRBS", //"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL" + parameter NUM_DQ_PINS = 8, + parameter SEL_VICTIM_LINE = 3, // VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern + + parameter COLUMN_WIDTH = 10, + parameter EYE_TEST = "FALSE" + + ) + ( + input clk_i, // + input [4:0] rst_i, + input [31:0] prbs_fseed_i, + + input [3:0] data_mode_i, // "00" = bram; + + output cmd_rdy_o, // ready to receive command. It should assert when data_port is ready at the // beginning and will be deasserted once see the cmd_valid_i is asserted. + // And then it should reasserted when + // it is generating the last_word. + input cmd_valid_i, // when both cmd_valid_i and cmd_rdy_o is high, the command is valid. + input cmd_validB_i, + input cmd_validC_i, + + output last_word_o, + + // input [5:0] port_data_counts_i,// connect to data port fifo counts +// input [ADDR_WIDTH-1:0] m_addr_i, + input [DWIDTH-1:0] fixed_data_i, + + input [ADDR_WIDTH-1:0] addr_i, // generated address used to determine data pattern. + input [BL_WIDTH-1:0] bl_i, // generated burst length for control the burst data + + input data_rdy_i, // connect from mcb_wr_full when used as wr_data_gen + // connect from mcb_rd_empty when used as rd_data_gen + // When both data_rdy and data_valid is asserted, the ouput data is valid. + output data_valid_o, // connect to wr_en or rd_en and is asserted whenever the + // pattern is available. + output [DWIDTH-1:0] data_o, // generated data pattern + output reg data_wr_end_o + + +); +// + + +reg [DWIDTH-1:0] data; + + + +(*EQUIVALENT_REGISTER_REMOVAL="NO"*) reg cmd_rdy,cmd_rdyB, cmd_rdyC,cmd_rdyD,cmd_rdyE,cmd_rdyF; +(*EQUIVALENT_REGISTER_REMOVAL="NO"*) reg cmd_start,cmd_startB,cmd_startC,cmd_startD,cmd_startE,cmd_startF; + + + + +reg burst_count_reached2; + +reg data_valid; +reg [6:0]user_burst_cnt; +reg [2:0] walk_cnt; + +wire fifo_not_full; +integer i,j; +reg [31:0] w3data; + +assign fifo_not_full = data_rdy_i; + +always @( posedge clk_i) +begin +if ((user_burst_cnt == 2 || (cmd_start && bl_i == 1 && FAMILY == "VIRTEX6")) && (fifo_not_full)) + data_wr_end_o <= #TCQ 1'b1; +else + data_wr_end_o <= #TCQ 1'b0; +end + +always @ (posedge clk_i) +begin +cmd_start <= #TCQ cmd_validC_i & cmd_rdyC ; +cmd_startB <= #TCQ cmd_valid_i & cmd_rdyB; +cmd_startC <= #TCQ cmd_validB_i & cmd_rdyC; +cmd_startD <= #TCQ cmd_validB_i & cmd_rdyD; +cmd_startE <= #TCQ cmd_validB_i & cmd_rdyE; +cmd_startF <= #TCQ cmd_validB_i & cmd_rdyF; +end + + +// counter to count user burst length +always @( posedge clk_i) +begin + if ( rst_i[0] ) + user_burst_cnt <= #TCQ 'd0; + else if(cmd_start) + if (FAMILY == "SPARTAN6") begin + if (bl_i == 6'b000000) + user_burst_cnt <= #TCQ 7'b1000000; + else + user_burst_cnt <= #TCQ bl_i; + + end + else + user_burst_cnt <= #TCQ bl_i; + else if(fifo_not_full) + if (user_burst_cnt != 6'd0) + user_burst_cnt <= #TCQ user_burst_cnt - 1'b1; + else + user_burst_cnt <=#TCQ 'd0; + +end + +reg u_bcount_2; +wire last_word_t; +always @ (posedge clk_i) +begin +if ((user_burst_cnt == 2 && fifo_not_full )|| (cmd_startC && bl_i == 1)) + u_bcount_2 <= #TCQ 1'b1; +else if (last_word_o) + u_bcount_2 <= #TCQ 1'b0; +end + + + +assign last_word_o = u_bcount_2 & fifo_not_full; + +// cmd_rdy_o assert when the dat fifo is not full and deassert once cmd_valid_i +// is assert and reassert during the last data + +assign cmd_rdy_o = cmd_rdy & fifo_not_full; + + +always @( posedge clk_i) +begin + if ( rst_i[0] ) + cmd_rdy <= #TCQ 1'b1; + else if (cmd_start) + if (bl_i == 1) + cmd_rdy <= #TCQ 1'b1; + else + cmd_rdy <= #TCQ 1'b0; + else if ((user_burst_cnt == 6'd2 && fifo_not_full ) ) + + cmd_rdy <= #TCQ 1'b1; + + +end + +always @( posedge clk_i) +begin + if ( rst_i [0]) + cmd_rdyB <= #TCQ 1'b1; + else if (cmd_startB) + if (bl_i == 1) + cmd_rdyB <= #TCQ 1'b1; + else + cmd_rdyB <= #TCQ 1'b0; + else if ((user_burst_cnt == 6'd2 && fifo_not_full ) ) + + + cmd_rdyB <= #TCQ 1'b1; + + +end + +always @( posedge clk_i) +begin + if ( rst_i[0] ) + cmd_rdyC <= #TCQ 1'b1; + else if (cmd_startC) + if (bl_i == 1) + cmd_rdyC <= #TCQ 1'b1; + else + cmd_rdyC <= #TCQ 1'b0; + else if ((user_burst_cnt == 6'd2 && fifo_not_full ) ) + + + cmd_rdyC <= #TCQ 1'b1; + + +end + +always @( posedge clk_i) +begin + if ( rst_i[0] ) + cmd_rdyD <= #TCQ 1'b1; + else if (cmd_startD) + if (bl_i == 1) + cmd_rdyD <= #TCQ 1'b1; + else + cmd_rdyD <= #TCQ 1'b0; + else if ((user_burst_cnt == 6'd2 && fifo_not_full ) ) + + + cmd_rdyD <= #TCQ 1'b1; + + +end + +always @( posedge clk_i) +begin + if ( rst_i[0] ) + cmd_rdyE <= #TCQ 1'b1; + else if (cmd_startE) + if (bl_i == 1) + cmd_rdyE <= #TCQ 1'b1; + else + cmd_rdyE <= #TCQ 1'b0; + else if ((user_burst_cnt == 6'd2 && fifo_not_full ) ) + + + cmd_rdyE <= #TCQ 1'b1; + + +end + + + +always @( posedge clk_i) +begin + if ( rst_i[0] ) + cmd_rdyF <= #TCQ 1'b1; + else if (cmd_startF) + if (bl_i == 1) + cmd_rdyF <= #TCQ 1'b1; + else + cmd_rdyF <= #TCQ 1'b0; + else if ((user_burst_cnt == 6'd2 && fifo_not_full ) ) + + cmd_rdyF <= #TCQ 1'b1; + + +end + + + +always @ (posedge clk_i) +begin + if (rst_i[1]) + data_valid <= #TCQ 'd0; + else if(cmd_start) + data_valid <= #TCQ 1'b1; + else if (fifo_not_full && user_burst_cnt <= 6'd1) + data_valid <= #TCQ 1'b0; +end + +assign data_valid_o = data_valid & fifo_not_full; + + +generate +if (FAMILY == "SPARTAN6") begin : SP6_WDGEN + +sp6_data_gen # + +( + .TCQ (TCQ), + .ADDR_WIDTH (32 ), + + .BL_WIDTH (BL_WIDTH ), + .DWIDTH (DWIDTH ), + .DATA_PATTERN (DATA_PATTERN ), + .NUM_DQ_PINS (NUM_DQ_PINS ), + .COLUMN_WIDTH (COLUMN_WIDTH) + + ) + sp6_data_gen + ( + .clk_i (clk_i ), + .rst_i (rst_i[1] ), + .data_rdy_i (data_rdy_i ), + .prbs_fseed_i (prbs_fseed_i), + + .data_mode_i (data_mode_i ), + .cmd_startA (cmd_start ), + .cmd_startB (cmd_startB ), + .cmd_startC (cmd_startC ), + .cmd_startD (cmd_startD ), + .cmd_startE (cmd_startE ), + .fixed_data_i (fixed_data_i), + + .addr_i (addr_i ), + .user_burst_cnt (user_burst_cnt), + .fifo_rdy_i (fifo_not_full ), + .data_o (data_o ) + ); +end + + +endgenerate + +generate +if (FAMILY == "VIRTEX6") begin : V6_WDGEN + +v6_data_gen # + +( + .TCQ (TCQ), + .ADDR_WIDTH (32 ), + .BL_WIDTH (BL_WIDTH ), + .DWIDTH (DWIDTH ), + .MEM_BURST_LEN (MEM_BURST_LEN), + + .DATA_PATTERN (DATA_PATTERN ), + .NUM_DQ_PINS (NUM_DQ_PINS ), + .SEL_VICTIM_LINE (SEL_VICTIM_LINE), + + .COLUMN_WIDTH (COLUMN_WIDTH), + .EYE_TEST (EYE_TEST) + + ) + v6_data_gen + ( + .clk_i (clk_i ), + .rst_i (rst_i[1] ), + .data_rdy_i (data_rdy_i ), + .prbs_fseed_i (prbs_fseed_i), + + .data_mode_i (data_mode_i ), + .cmd_startA (cmd_start ), + .cmd_startB (cmd_startB ), + .cmd_startC (cmd_startC ), + .cmd_startD (cmd_startD ), + .cmd_startE (cmd_startE ), + .m_addr_i (addr_i/*m_addr_i*/), + .fixed_data_i (fixed_data_i), + + .addr_i (addr_i ), + .user_burst_cnt (user_burst_cnt), + .fifo_rdy_i (fifo_not_full ), + .data_o (data_o ) + ); +end +endgenerate + + +endmodule diff --git "a/Frogwells_fpga_design/\345\237\272\344\272\216FPGA\343\200\201DDR3\345\222\214USB2.0\347\232\204\345\233\276\345\203\217\351\207\207\351\233\206\347\263\273\347\273\237/debug/ddr_test/rtl/traffic_gen/write_data_path.v" "b/Frogwells_fpga_design/\345\237\272\344\272\216FPGA\343\200\201DDR3\345\222\214USB2.0\347\232\204\345\233\276\345\203\217\351\207\207\351\233\206\347\263\273\347\273\237/debug/ddr_test/rtl/traffic_gen/write_data_path.v" new file mode 100644 index 0000000000000000000000000000000000000000..a4e822dbeaddb419d86a2f538efaa590f16d250b --- /dev/null +++ "b/Frogwells_fpga_design/\345\237\272\344\272\216FPGA\343\200\201DDR3\345\222\214USB2.0\347\232\204\345\233\276\345\203\217\351\207\207\351\233\206\347\263\273\347\273\237/debug/ddr_test/rtl/traffic_gen/write_data_path.v" @@ -0,0 +1,157 @@ +//***************************************************************************** +// (c) Copyright 2008-2009 Xilinx, Inc. All rights reserved. +// +// This file contains confidential and proprietary information +// of Xilinx, Inc. and is protected under U.S. and +// international copyright and other intellectual property +// laws. +// +// DISCLAIMER +// This disclaimer is not a license and does not grant any +// rights to the materials distributed herewith. Except as +// otherwise provided in a valid license issued to you by +// Xilinx, and to the maximum extent permitted by applicable +// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +// (2) Xilinx shall not be liable (whether in contract or tort, +// including negligence, or under any other theory of +// liability) for any loss or damage of any kind or nature +// related to, arising under or in connection with these +// materials, including for any direct, or any indirect, +// special, incidental, or consequential loss or damage +// (including loss of data, profits, goodwill, or any type of +// loss or damage suffered as a result of any action brought +// by a third party) even if such damage or loss was +// reasonably foreseeable or Xilinx had been advised of the +// possibility of the same. +// +// CRITICAL APPLICATIONS +// Xilinx products are not designed or intended to be fail- +// safe, or for use in any application requiring fail-safe +// performance, such as life-support or safety devices or +// systems, Class III medical devices, nuclear facilities, +// applications related to the deployment of airbags, or any +// other applications that could lead to death, personal +// injury, or severe property or environmental damage +// (individually and collectively, "Critical +// Applications"). Customer assumes the sole risk and +// liability of any use of Xilinx products in Critical +// Applications, subject only to applicable laws and +// regulations governing limitations on product liability. +// +// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +// PART OF THIS FILE AT ALL TIMES. +// +//***************************************************************************** +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version: %version +// \ \ Application: MIG +// / / Filename: write_data_path.v +// /___/ /\ Date Last Modified: +// \ \ / \ Date Created: +// \___\/\___\ +// +//Device: Spartan6 +//Design Name: DDR/DDR2/DDR3/LPDDR +//Purpose: This is top level of write path . + +//Reference: +//Revision History: +//***************************************************************************** + +`timescale 1ps/1ps + + +module write_data_path #( + parameter TCQ = 100, + parameter FAMILY = "SPARTAN6", + parameter ADDR_WIDTH = 32, + parameter MEM_BURST_LEN = 8, + parameter DWIDTH = 32, + parameter DATA_PATTERN = "DGEN_ALL", //"DGEN__HAMMER", "DGEN_WALING1","DGEN_WALING0","DGEN_ADDR","DGEN_NEIGHBOR","DGEN_PRBS","DGEN_ALL" + parameter NUM_DQ_PINS = 8, + parameter SEL_VICTIM_LINE = 3, // VICTIM LINE is one of the DQ pins is selected to be different than hammer pattern + + parameter MEM_COL_WIDTH = 10, + parameter EYE_TEST = "FALSE" + + ) + ( + + input clk_i, + input [9:0] rst_i, + output cmd_rdy_o, + input cmd_valid_i, + input cmd_validB_i, + input cmd_validC_i, + input [31:0] prbs_fseed_i, + input [3:0] data_mode_i, +// input [31:0] m_addr_i, + input [DWIDTH-1:0] fixed_data_i, + + input [31:0] addr_i, + input [5:0] bl_i, + +// input [5:0] port_data_counts_i,// connect to data port fifo counts + + input data_rdy_i, + output data_valid_o, + output last_word_wr_o, + output [DWIDTH-1:0] data_o, + output [(DWIDTH/8) - 1:0] data_mask_o, + output data_wr_end_o + + ); + +wire data_valid; +reg cmd_rdy; + + assign data_valid_o = data_valid & data_rdy_i; + assign data_mask_o = 'b0; // for now + + + wr_data_gen #( + .TCQ (TCQ), + .FAMILY (FAMILY), + .NUM_DQ_PINS (NUM_DQ_PINS), + .MEM_BURST_LEN (MEM_BURST_LEN), + + .SEL_VICTIM_LINE (SEL_VICTIM_LINE), + .DATA_PATTERN (DATA_PATTERN), + .DWIDTH (DWIDTH), + .COLUMN_WIDTH (MEM_COL_WIDTH), + .EYE_TEST (EYE_TEST) + + ) + wr_data_gen( + .clk_i (clk_i ), + .rst_i (rst_i[9:5]), + .prbs_fseed_i (prbs_fseed_i), + + .data_mode_i (data_mode_i ), + .cmd_rdy_o (cmd_rdy_o ), + .cmd_valid_i (cmd_valid_i ), + .cmd_validB_i (cmd_validB_i ), + .cmd_validC_i (cmd_validC_i ), + + .last_word_o (last_word_wr_o ), + // .port_data_counts_i (port_data_counts_i), +// .m_addr_i (m_addr_i ), + .fixed_data_i (fixed_data_i), + + .addr_i (addr_i ), + .bl_i (bl_i ), + .data_rdy_i (data_rdy_i ), + .data_valid_o ( data_valid ), + .data_o (data_o ), + .data_wr_end_o (data_wr_end_o) + ); + + + +endmodule diff --git "a/Frogwells_fpga_design/\345\237\272\344\272\216FPGA\343\200\201DDR3\345\222\214USB2.0\347\232\204\345\233\276\345\203\217\351\207\207\351\233\206\347\263\273\347\273\237/debug/ddr_test/sim/functional/ddr3_model_c3.v" "b/Frogwells_fpga_design/\345\237\272\344\272\216FPGA\343\200\201DDR3\345\222\214USB2.0\347\232\204\345\233\276\345\203\217\351\207\207\351\233\206\347\263\273\347\273\237/debug/ddr_test/sim/functional/ddr3_model_c3.v" new file mode 100644 index 0000000000000000000000000000000000000000..1f7c4f4986807ad92259472d6662558c8b42d99c --- /dev/null +++ "b/Frogwells_fpga_design/\345\237\272\344\272\216FPGA\343\200\201DDR3\345\222\214USB2.0\347\232\204\345\233\276\345\203\217\351\207\207\351\233\206\347\263\273\347\273\237/debug/ddr_test/sim/functional/ddr3_model_c3.v" @@ -0,0 +1,2674 @@ +/**************************************************************************************** +* +* File Name: ddr3.v +* Version: 1.61 +* Model: BUS Functional +* +* Dependencies: ddr3_model_parameters_c3.vh +* +* Description: Micron SDRAM DDR3 (Double Data Rate 3) +* +* Limitation: - doesn't check for average refresh timings +* - positive ck and ck_n edges are used to form internal clock +* - positive dqs and dqs_n edges are used to latch data +* - test mode is not modeled +* - Duty Cycle Corrector is not modeled +* - Temperature Compensated Self Refresh is not modeled +* - DLL off mode is not modeled. +* +* Note: - Set simulator resolution to "ps" accuracy +* - Set DEBUG = 0 to disable $display messages +* +* Disclaimer This software code and all associated documentation, comments or other +* of Warranty: information (collectively "Software") is provided "AS IS" without +* warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY +* DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +* TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES +* OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT +* WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE +* OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE. +* FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR +* THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS, +* ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE +* OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI, +* ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT, +* INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING, +* WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, +* OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE +* THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH +* DAMAGES. Because some jurisdictions prohibit the exclusion or +* limitation of liability for consequential or incidental damages, the +* above limitation may not apply to you. +* +* Copyright 2003 Micron Technology, Inc. All rights reserved. +* +* Rev Author Date Changes +* --------------------------------------------------------------------------------------- +* 0.41 JMK 05/12/06 Removed auto-precharge to power down error check. +* 0.42 JMK 08/25/06 Created internal clock using ck and ck_n. +* TDQS can only be enabled in EMR for x8 configurations. +* CAS latency is checked vs frequency when DLL locks. +* Improved checking of DQS during writes. +* Added true BL4 operation. +* 0.43 JMK 08/14/06 Added checking for setting reserved bits in Mode Registers. +* Added ODTS Readout. +* Replaced tZQCL with tZQinit and tZQoper +* Fixed tWRPDEN and tWRAPDEN during BC4MRS and BL4MRS. +* Added tRFC checking for Refresh to Power-Down Re-Entry. +* Added tXPDLL checking for Power-Down Exit to Refresh to Power-Down Entry +* Added Clock Frequency Change during Precharge Power-Down. +* Added -125x speed grades. +* Fixed tRCD checking during Write. +* 1.00 JMK 05/11/07 Initial release +* 1.10 JMK 06/26/07 Fixed ODTH8 check during BLOTF +* Removed temp sensor readout from MPR +* Updated initialization sequence +* Updated timing parameters +* 1.20 JMK 09/05/07 Updated clock frequency change +* Added ddr3_dimm module +* 1.30 JMK 01/23/08 Updated timing parameters +* 1.40 JMK 12/02/08 Added support for DDR3-1866 and DDR3-2133 +* renamed ddr3_dimm.v to ddr3_module.v and added SODIMM support. +* Added multi-chip package model support in ddr3_mcp.v +* 1.50 JMK 05/04/08 Added 1866 and 2133 speed grades. +* 1.60 MYY 07/10/09 Merging of 1.50 version and pre-1.0 version changes +* 1.61 SPH 12/10/09 Only check tIH for cmd_addr if CS# LOW +*****************************************************************************************/ +// DO NOT CHANGE THE TIMESCALE +// MAKE SURE YOUR SIMULATOR USES "PS" RESOLUTION +`timescale 1ps / 1ps + +// model flags +// `define MODEL_PASR + +module ddr3_model_c3( + rst_n, + ck, + ck_n, + cke, + cs_n, + ras_n, + cas_n, + we_n, + dm_tdqs, + ba, + addr, + dq, + dqs, + dqs_n, + tdqs_n, + odt +); + + `include "ddr3_model_parameters_c3.vh" + + parameter check_strict_mrbits = 1; + parameter check_strict_timing = 1; + parameter feature_pasr = 1; + parameter feature_truebl4 = 0; + + // text macros + `define DQ_PER_DQS DQ_BITS/DQS_BITS + `define BANKS (1<= 2. \nBL_MAX = %d", BL_MAX); + if ((1< BL_MAX) + $display("%m ERROR: 2^BO_BITS cannot be greater than BL_MAX parameter."); + + $timeformat (-12, 1, " ps", 1); + seed = RANDOM_SEED; + + ck_cntr = 0; + end + + function integer get_rtt_wr; + input [1:0] rtt; + begin + get_rtt_wr = RZQ/{rtt[0], rtt[1], 1'b0}; + end + endfunction + + function integer get_rtt_nom; + input [2:0] rtt; + begin + case (rtt) + 1: get_rtt_nom = RZQ/4; + 2: get_rtt_nom = RZQ/2; + 3: get_rtt_nom = RZQ/6; + 4: get_rtt_nom = RZQ/12; + 5: get_rtt_nom = RZQ/8; + default : get_rtt_nom = 0; + endcase + end + endfunction + + // calculate the absolute value of a real number + function real abs_value; + input arg; + real arg; + begin + if (arg < 0.0) + abs_value = -1.0 * arg; + else + abs_value = arg; + end + endfunction + + function integer ceil; + input number; + real number; + + // LMR 4.1.7 + // When either operand of a relational expression is a real operand then the other operand shall be converted + // to an equivalent real value, and the expression shall be interpreted as a comparison between two real values. + if (number > $rtoi(number)) + ceil = $rtoi(number) + 1; + else + ceil = number; + endfunction + + function integer floor; + input number; + real number; + + // LMR 4.1.7 + // When either operand of a relational expression is a real operand then the other operand shall be converted + // to an equivalent real value, and the expression shall be interpreted as a comparison between two real values. + if (number < $rtoi(number)) + floor = $rtoi(number) - 1; + else + floor = number; + endfunction + +`ifdef MAX_MEM + + function integer open_bank_file( input integer bank ); + integer fd; + reg [2048:1] filename; + begin + $sformat( filename, "%0s/%m.%0d", tmp_model_dir, bank ); + + fd = $fopen(filename, "w+"); + if (fd == 0) + begin + $display("%m: at time %0t ERROR: failed to open %0s.", $time, filename); + $finish; + end + else + begin + if (DEBUG) $display("%m: at time %0t INFO: opening %0s.", $time, filename); + open_bank_file = fd; + end + + end + endfunction + + function [RFF_BITS:1] read_from_file( + input integer fd, + input integer index + ); + integer code; + integer offset; + reg [1024:1] msg; + reg [RFF_BITS:1] read_value; + + begin + offset = index * RFF_CHUNK; + code = $fseek( fd, offset, 0 ); + // $fseek returns 0 on success, -1 on failure + if (code != 0) + begin + $display("%m: at time %t ERROR: fseek to %d failed", $time, offset); + $finish; + end + + code = $fscanf(fd, "%z", read_value); + // $fscanf returns number of items read + if (code != 1) + begin + if ($ferror(fd,msg) != 0) + begin + $display("%m: at time %t ERROR: fscanf failed at %d", $time, index); + $display(msg); + $finish; + end + else + read_value = 'hx; + end + + /* when reading from unwritten portions of the file, 0 will be returned. + * Use 0 in bit 1 as indicator that invalid data has been read. + * A true 0 is encoded as Z. + */ + if (read_value[1] === 1'bz) + // true 0 encoded as Z, data is valid + read_value[1] = 1'b0; + else if (read_value[1] === 1'b0) + // read from file section that has not been written + read_value = 'hx; + + read_from_file = read_value; + end + endfunction + + task write_to_file( + input integer fd, + input integer index, + input [RFF_BITS:1] data + ); + integer code; + integer offset; + + begin + offset = index * RFF_CHUNK; + code = $fseek( fd, offset, 0 ); + if (code != 0) + begin + $display("%m: at time %t ERROR: fseek to %d failed", $time, offset); + $finish; + end + + // encode a valid data + if (data[1] === 1'bz) + data[1] = 1'bx; + else if (data[1] === 1'b0) + data[1] = 1'bz; + + $fwrite( fd, "%z", data ); + end + endtask +`else + function get_index; + input [`MAX_BITS-1:0] addr; + begin : index + get_index = 0; + for (memory_index=0; memory_index>(ROW_BITS+COL_BITS-BL_BITS)); + if (!banks[ba]) begin //bank is selected to keep + address[i] = address[memory_index]; + memory[i] = memory[memory_index]; + i = i + 1; + end + end + // clean up the unused banks + for (memory_index=i; memory_index TRAS_MAX) $display ("%m: at time %t ERROR: tRAS maximum violation during %s to bank %d", $time, cmd_string[cmd], bank); + if ($time - tm_bank_activate[bank] < TRAS_MIN) $display ("%m: at time %t ERROR: tRAS minimum violation during %s to bank %d", $time, cmd_string[cmd], bank);end + {1'bx, SAME_BANK , ACTIVATE , ACTIVATE } : begin if ($time - tm_bank_activate[bank] < TRC) $display ("%m: at time %t ERROR: tRC violation during %s to bank %d", $time, cmd_string[cmd], bank); end + {1'bx, SAME_BANK , ACTIVATE , WRITE } , + {1'bx, SAME_BANK , ACTIVATE , READ } : ; // tRCD is checked outside this task + {1'b0, DIFF_BANK , ACTIVATE , ACTIVATE } : begin if (($time - tm_activate < TRRD) || (ck_cntr - ck_activate < TRRD_TCK)) $display ("%m: at time %t ERROR: tRRD violation during %s to bank %d", $time, cmd_string[cmd], bank); end + {1'b1, DIFF_BANK , ACTIVATE , ACTIVATE } : begin if (($time - tm_group_activate[bank[1]] < TRRD) || (ck_cntr - ck_group_activate[bank[1]] < TRRD_TCK)) $display ("%m: at time %t ERROR: tRRD violation during %s to bank %d", $time, cmd_string[cmd], bank); end + {1'b1, DIFF_GROUP, ACTIVATE , ACTIVATE } : begin if (($time - tm_activate < TRRD_DG) || (ck_cntr - ck_activate < TRRD_DG_TCK)) $display ("%m: at time %t ERROR: tRRD_DG violation during %s to bank %d", $time, cmd_string[cmd], bank); end + {1'bx, DIFF_BANK , ACTIVATE , REFRESH } : begin if ($time - tm_activate < TRC) $display ("%m: at time %t ERROR: tRC violation during %s", $time, cmd_string[cmd]); end + {1'bx, DIFF_BANK , ACTIVATE , PWR_DOWN } : begin if (ck_cntr - ck_activate < TACTPDEN) $display ("%m: at time %t ERROR: tACTPDEN violation during %s", $time, cmd_string[cmd]); end + + // write + {1'bx, SAME_BANK , WRITE , PRECHARGE} : begin if (($time - tm_bank_write_end[bank] < TWR) || (ck_cntr - ck_bank_write[bank] <= write_latency + burst_length/2)) $display ("%m: at time %t ERROR: tWR violation during %s to bank %d", $time, cmd_string[cmd], bank); end + {1'b0, DIFF_BANK , WRITE , WRITE } : begin if (ck_cntr - ck_write < TCCD) $display ("%m: at time %t ERROR: tCCD violation during %s to bank %d", $time, cmd_string[cmd], bank); end + {1'b1, DIFF_BANK , WRITE , WRITE } : begin if (ck_cntr - ck_group_write[bank[1]] < TCCD) $display ("%m: at time %t ERROR: tCCD violation during %s to bank %d", $time, cmd_string[cmd], bank); end + {1'b0, DIFF_BANK , WRITE , READ } : begin if (ck_cntr - ck_write < write_latency + burst_length/2 + TWTR_TCK - additive_latency) $display ("%m: at time %t ERROR: tWTR violation during %s to bank %d", $time, cmd_string[cmd], bank); end + {1'b1, DIFF_BANK , WRITE , READ } : begin if (ck_cntr - ck_group_write[bank[1]] < write_latency + burst_length/2 + TWTR_TCK - additive_latency) $display ("%m: at time %t ERROR: tWTR violation during %s to bank %d", $time, cmd_string[cmd], bank); end + {1'b1, DIFF_GROUP, WRITE , WRITE } : begin if (ck_cntr - ck_write < TCCD_DG) $display ("%m: at time %t ERROR: tCCD_DG violation during %s to bank %d", $time, cmd_string[cmd], bank); end + {1'b1, DIFF_GROUP, WRITE , READ } : begin if (ck_cntr - ck_write < write_latency + burst_length/2 + TWTR_DG_TCK - additive_latency) $display ("%m: at time %t ERROR: tWTR_DG violation during %s to bank %d", $time, cmd_string[cmd], bank); end + {1'bx, DIFF_BANK , WRITE , PWR_DOWN } : begin if (($time - tm_write_end < TWR) || (ck_cntr - ck_write < write_latency + burst_length/2)) $display ("%m: at time %t ERROR: tWRPDEN violation during %s", $time, cmd_string[cmd]); end + + // read + {1'bx, SAME_BANK , READ , PRECHARGE} : begin if (($time - tm_bank_read_end[bank] < TRTP) || (ck_cntr - ck_bank_read[bank] < additive_latency + TRTP_TCK)) $display ("%m: at time %t ERROR: tRTP violation during %s to bank %d", $time, cmd_string[cmd], bank); end + {1'b0, DIFF_BANK , READ , WRITE } : ; // tRTW is checked outside this task + {1'b1, DIFF_BANK , READ , WRITE } : ; // tRTW is checked outside this task + {1'b0, DIFF_BANK , READ , READ } : begin if (ck_cntr - ck_read < TCCD) $display ("%m: at time %t ERROR: tCCD violation during %s to bank %d", $time, cmd_string[cmd], bank); end + {1'b1, DIFF_BANK , READ , READ } : begin if (ck_cntr - ck_group_read[bank[1]] < TCCD) $display ("%m: at time %t ERROR: tCCD violation during %s to bank %d", $time, cmd_string[cmd], bank); end + {1'b1, DIFF_GROUP, READ , WRITE } : ; // tRTW is checked outside this task + {1'b1, DIFF_GROUP, READ , READ } : begin if (ck_cntr - ck_read < TCCD_DG) $display ("%m: at time %t ERROR: tCCD_DG violation during %s to bank %d", $time, cmd_string[cmd], bank); end + {1'bx, DIFF_BANK , READ , PWR_DOWN } : begin if (ck_cntr - ck_read < read_latency + 5) $display ("%m: at time %t ERROR: tRDPDEN violation during %s", $time, cmd_string[cmd]); end + + // zq + {1'bx, DIFF_BANK , ZQ , LOAD_MODE} : ; // 1 tCK + {1'bx, DIFF_BANK , ZQ , REFRESH } , + {1'bx, DIFF_BANK , ZQ , PRECHARGE} , + {1'bx, DIFF_BANK , ZQ , ACTIVATE } , + {1'bx, DIFF_BANK , ZQ , ZQ } , + {1'bx, DIFF_BANK , ZQ , PWR_DOWN } , + {1'bx, DIFF_BANK , ZQ , SELF_REF } : begin if (ck_cntr - ck_zqinit < TZQINIT) $display ("%m: at time %t ERROR: tZQinit violation during %s", $time, cmd_string[cmd]); + if (ck_cntr - ck_zqoper < TZQOPER) $display ("%m: at time %t ERROR: tZQoper violation during %s", $time, cmd_string[cmd]); + if (ck_cntr - ck_zqcs < TZQCS) $display ("%m: at time %t ERROR: tZQCS violation during %s", $time, cmd_string[cmd]); end + + // power down + {1'bx, DIFF_BANK , PWR_DOWN , LOAD_MODE} , + {1'bx, DIFF_BANK , PWR_DOWN , REFRESH } , + {1'bx, DIFF_BANK , PWR_DOWN , PRECHARGE} , + {1'bx, DIFF_BANK , PWR_DOWN , ACTIVATE } , + {1'bx, DIFF_BANK , PWR_DOWN , WRITE } , + {1'bx, DIFF_BANK , PWR_DOWN , ZQ } : begin if (($time - tm_power_down < TXP) || (ck_cntr - ck_power_down < TXP_TCK)) $display ("%m: at time %t ERROR: tXP violation during %s", $time, cmd_string[cmd]); end + {1'bx, DIFF_BANK , PWR_DOWN , READ } : begin if (($time - tm_power_down < TXP) || (ck_cntr - ck_power_down < TXP_TCK)) $display ("%m: at time %t ERROR: tXP violation during %s", $time, cmd_string[cmd]); + else if (($time - tm_slow_exit_pd < TXPDLL) || (ck_cntr - ck_slow_exit_pd < TXPDLL_TCK)) $display ("%m: at time %t ERROR: tXPDLL violation during %s", $time, cmd_string[cmd]); end + {1'bx, DIFF_BANK , PWR_DOWN , PWR_DOWN } , + {1'bx, DIFF_BANK , PWR_DOWN , SELF_REF } : begin if (($time - tm_power_down < TXP) || (ck_cntr - ck_power_down < TXP_TCK)) $display ("%m: at time %t ERROR: tXP violation during %s", $time, cmd_string[cmd]); + if ((tm_power_down > tm_refresh) && ($time - tm_refresh < TRFC_MIN)) $display ("%m: at time %t ERROR: tRFC violation during %s", $time, cmd_string[cmd]); + if ((tm_refresh > tm_power_down) && (($time - tm_power_down < TXPDLL) || (ck_cntr - ck_power_down < TXPDLL_TCK))) $display ("%m: at time %t ERROR: tXPDLL violation during %s", $time, cmd_string[cmd]); + if (($time - tm_cke_cmd < TCKE) || (ck_cntr - ck_cke_cmd < TCKE_TCK)) $display ("%m: at time %t ERROR: tCKE violation on CKE", $time); end + + // self refresh + {1'bx, DIFF_BANK , SELF_REF , LOAD_MODE} , + {1'bx, DIFF_BANK , SELF_REF , REFRESH } , + {1'bx, DIFF_BANK , SELF_REF , PRECHARGE} , + {1'bx, DIFF_BANK , SELF_REF , ACTIVATE } , + {1'bx, DIFF_BANK , SELF_REF , WRITE } , + {1'bx, DIFF_BANK , SELF_REF , ZQ } : begin if (($time - tm_self_refresh < TXS) || (ck_cntr - ck_self_refresh < TXS_TCK)) $display ("%m: at time %t ERROR: tXS violation during %s", $time, cmd_string[cmd]); end + {1'bx, DIFF_BANK , SELF_REF , READ } : begin if (ck_cntr - ck_self_refresh < TXSDLL) $display ("%m: at time %t ERROR: tXSDLL violation during %s", $time, cmd_string[cmd]); end + {1'bx, DIFF_BANK , SELF_REF , PWR_DOWN } , + {1'bx, DIFF_BANK , SELF_REF , SELF_REF } : begin if (($time - tm_self_refresh < TXS) || (ck_cntr - ck_self_refresh < TXS_TCK)) $display ("%m: at time %t ERROR: tXS violation during %s", $time, cmd_string[cmd]); + if (($time - tm_cke_cmd < TCKE) || (ck_cntr - ck_cke_cmd < TCKE_TCK)) $display ("%m: at time %t ERROR: tCKE violation on CKE", $time); end + endcase + end + endtask + + task cmd_task; + input cke; + input [2:0] cmd; + input [BA_BITS-1:0] bank; + input [ADDR_BITS-1:0] addr; + reg [`BANKS:0] i; + integer j; + reg [`BANKS:0] tfaw_cntr; + reg [COL_BITS-1:0] col; + reg group; + begin + // tRFC max check + if (!er_trfc_max && !in_self_refresh) begin + if ($time - tm_refresh > TRFC_MAX && check_strict_timing) begin + $display ("%m: at time %t ERROR: tRFC maximum violation during %s", $time, cmd_string[cmd]); + er_trfc_max = 1; + end + end + if (cke) begin + if ((cmd < NOP) && (cmd != PRECHARGE)) begin + if (($time - tm_txpr < TXPR) || (ck_cntr - ck_txpr < TXPR_TCK)) + $display ("%m: at time %t ERROR: tXPR violation during %s", $time, cmd_string[cmd]); + for (j=0; j<=SELF_REF; j=j+1) begin + chk_err(SAME_BANK , bank, j, cmd); + chk_err(DIFF_BANK , bank, j, cmd); + chk_err(DIFF_GROUP, bank, j, cmd); + end + end + case (cmd) + LOAD_MODE : begin + if (|odt_pipeline) + $display ("%m: at time %t ERROR: ODTL violation during %s", $time, cmd_string[cmd]); + if (odt_state) + $display ("%m: at time %t ERROR: ODT must be off prior to %s", $time, cmd_string[cmd]); + + if (|active_bank) begin + $display ("%m: at time %t ERROR: %s Failure. All banks must be Precharged.", $time, cmd_string[cmd]); + if (STOP_ON_ERROR) $stop(0); + end else begin + if (DEBUG) $display ("%m: at time %t INFO: %s %d", $time, cmd_string[cmd], bank); + if (bank>>2) begin + $display ("%m: at time %t ERROR: %s %d Illegal value. Reserved bank bits must be programmed to zero", $time, cmd_string[cmd], bank); + end + case (bank) + 0 : begin + // Burst Length + if (addr[1:0] == 2'b00) begin + burst_length = 8; + blotf = 0; + truebl4 = 0; + if (DEBUG) $display ("%m: at time %t INFO: %s %d Burst Length = %d", $time, cmd_string[cmd], bank, burst_length); + end else if (addr[1:0] == 2'b01) begin + burst_length = 8; + blotf = 1; + truebl4 = 0; + if (DEBUG) $display ("%m: at time %t INFO: %s %d Burst Length = Select via A12", $time, cmd_string[cmd], bank); + end else if (addr[1:0] == 2'b10) begin + burst_length = 4; + blotf = 0; + truebl4 = 0; + if (DEBUG) $display ("%m: at time %t INFO: %s %d Burst Length = Fixed %d (chop)", $time, cmd_string[cmd], bank, burst_length); + end else if (feature_truebl4 && (addr[1:0] == 2'b11)) begin + burst_length = 4; + blotf = 0; + truebl4 = 1; + if (DEBUG) $display ("%m: at time %t INFO: %s %d Burst Length = True %d", $time, cmd_string[cmd], bank, burst_length); + end else begin + $display ("%m: at time %t ERROR: %s %d Illegal Burst Length = %d", $time, cmd_string[cmd], bank, addr[1:0]); + end + // Burst Order + burst_order = addr[3]; + if (!burst_order) begin + if (DEBUG) $display ("%m: at time %t INFO: %s %d Burst Order = Sequential", $time, cmd_string[cmd], bank); + end else if (burst_order) begin + if (DEBUG) $display ("%m: at time %t INFO: %s %d Burst Order = Interleaved", $time, cmd_string[cmd], bank); + end else begin + $display ("%m: at time %t ERROR: %s %d Illegal Burst Order = %d", $time, cmd_string[cmd], bank, burst_order); + end + // CAS Latency + cas_latency = {addr[2],addr[6:4]} + 4; + set_latency; + if ((cas_latency >= CL_MIN) && (cas_latency <= CL_MAX)) begin + if (DEBUG) $display ("%m: at time %t INFO: %s %d CAS Latency = %d", $time, cmd_string[cmd], bank, cas_latency); + end else begin + $display ("%m: at time %t ERROR: %s %d Illegal CAS Latency = %d", $time, cmd_string[cmd], bank, cas_latency); + end + // Reserved + if (addr[7] !== 0 && check_strict_mrbits) begin + $display ("%m: at time %t ERROR: %s %d Illegal value. Reserved address bits must be programmed to zero", $time, cmd_string[cmd], bank); + end + // DLL Reset + dll_reset = addr[8]; + if (!dll_reset) begin + if (DEBUG) $display ("%m: at time %t INFO: %s %d DLL Reset = Normal", $time, cmd_string[cmd], bank); + end else if (dll_reset) begin + if (DEBUG) $display ("%m: at time %t INFO: %s %d DLL Reset = Reset DLL", $time, cmd_string[cmd], bank); + dll_locked = 0; + init_dll_reset = 1; + ck_dll_reset <= ck_cntr; + end else begin + $display ("%m: at time %t ERROR: %s %d Illegal DLL Reset = %d", $time, cmd_string[cmd], bank, dll_reset); + end + + // Write Recovery + if (addr[11:9] == 0) begin + write_recovery = 16; + end else if (addr[11:9] < 4) begin + write_recovery = addr[11:9] + 4; + end else begin + write_recovery = 2*addr[11:9]; + end + + if ((write_recovery >= WR_MIN) && (write_recovery <= WR_MAX)) begin + if (DEBUG) $display ("%m: at time %t INFO: %s %d Write Recovery = %d", $time, cmd_string[cmd], bank, write_recovery); + end else begin + $display ("%m: at time %t ERROR: %s %d Illegal Write Recovery = %d", $time, cmd_string[cmd], bank, write_recovery); + end + // Power Down Mode + low_power = !addr[12]; + if (!low_power) begin + if (DEBUG) $display ("%m: at time %t INFO: %s %d Power Down Mode = DLL on", $time, cmd_string[cmd], bank); + end else if (low_power) begin + if (DEBUG) $display ("%m: at time %t INFO: %s %d Power Down Mode = DLL off", $time, cmd_string[cmd], bank); + end else begin + $display ("%m: at time %t ERROR: %s %d Illegal Power Down Mode = %d", $time, cmd_string[cmd], bank, low_power); + end + // Reserved + if (ADDR_BITS>13 && addr[13] !== 0 && check_strict_mrbits) begin + $display ("%m: at time %t ERROR: %s %d Illegal value. Reserved address bits must be programmed to zero", $time, cmd_string[cmd], bank); + end + end + 1 : begin + // DLL Enable + dll_en = !addr[0]; + if (!dll_en) begin + if (DEBUG) $display ("%m: at time %t INFO: %s %d DLL Enable = Disabled", $time, cmd_string[cmd], bank); + if (check_strict_mrbits) $display ("%m: at time %t WARNING: %s %d DLL off mode is not modeled", $time, cmd_string[cmd], bank); + end else if (dll_en) begin + if (DEBUG) $display ("%m: at time %t INFO: %s %d DLL Enable = Enabled", $time, cmd_string[cmd], bank); + end else begin + $display ("%m: at time %t ERROR: %s %d Illegal DLL Enable = %d", $time, cmd_string[cmd], bank, dll_en); + end + // Output Drive Strength + if ({addr[5], addr[1]} == 2'b00) begin + if (DEBUG) $display ("%m: at time %t INFO: %s %d Output Drive Strength = %d Ohm", $time, cmd_string[cmd], bank, RZQ/6); + end else if ({addr[5], addr[1]} == 2'b01) begin + if (DEBUG) $display ("%m: at time %t INFO: %s %d Output Drive Strength = %d Ohm", $time, cmd_string[cmd], bank, RZQ/7); + end else if ({addr[5], addr[1]} == 2'b11) begin + if (DEBUG) $display ("%m: at time %t INFO: %s %d Output Drive Strength = %d Ohm", $time, cmd_string[cmd], bank, RZQ/5); + end else begin + $display ("%m: at time %t ERROR: %s %d Illegal Output Drive Strength = %d", $time, cmd_string[cmd], bank, {addr[5], addr[1]}); + end + // ODT Rtt (Rtt_NOM) + odt_rtt_nom = {addr[9], addr[6], addr[2]}; + if (odt_rtt_nom == 3'b000) begin + if (DEBUG) $display ("%m: at time %t INFO: %s %d ODT Rtt = Disabled", $time, cmd_string[cmd], bank); + odt_en = 0; + end else if ((odt_rtt_nom < 4) || ((!addr[7] || (addr[7] && addr[12])) && (odt_rtt_nom < 6))) begin + if (DEBUG) $display ("%m: at time %t INFO: %s %d ODT Rtt = %d Ohm", $time, cmd_string[cmd], bank, get_rtt_nom(odt_rtt_nom)); + odt_en = 1; + end else begin + $display ("%m: at time %t ERROR: %s %d Illegal ODT Rtt = %d", $time, cmd_string[cmd], bank, odt_rtt_nom); + odt_en = 0; + end + // Report the additive latency value + al = addr[4:3]; + set_latency; + if (al == 0) begin + if (DEBUG) $display ("%m: at time %t INFO: %s %d Additive Latency = %d", $time, cmd_string[cmd], bank, al); + end else if ((al >= AL_MIN) && (al <= AL_MAX)) begin + if (DEBUG) $display ("%m: at time %t INFO: %s %d Additive Latency = CL - %d", $time, cmd_string[cmd], bank, al); + end else begin + $display ("%m: at time %t ERROR: %s %d Illegal Additive Latency = %d", $time, cmd_string[cmd], bank, al); + end + // Write Levelization + write_levelization = addr[7]; + if (!write_levelization) begin + if (DEBUG) $display ("%m: at time %t INFO: %s %d Write Levelization = Disabled", $time, cmd_string[cmd], bank); + end else if (write_levelization) begin + if (DEBUG) $display ("%m: at time %t INFO: %s %d Write Levelization = Enabled", $time, cmd_string[cmd], bank); + end else begin + $display ("%m: at time %t ERROR: %s %d Illegal Write Levelization = %d", $time, cmd_string[cmd], bank, write_levelization); + end + // Reserved + if (addr[8] !== 0 && check_strict_mrbits) begin + $display ("%m: at time %t ERROR: %s %d Illegal value. Reserved address bits must be programmed to zero", $time, cmd_string[cmd], bank); + end + // Reserved + if (addr[10] !== 0 && check_strict_mrbits) begin + $display ("%m: at time %t ERROR: %s %d Illegal value. Reserved address bits must be programmed to zero", $time, cmd_string[cmd], bank); + end + // TDQS Enable + tdqs_en = addr[11]; + if (!tdqs_en) begin + if (DEBUG) $display ("%m: at time %t INFO: %s %d TDQS Enable = Disabled", $time, cmd_string[cmd], bank); + end else if (tdqs_en) begin + if (8 == DQ_BITS) begin + if (DEBUG) $display ("%m: at time %t INFO: %s %d TDQS Enable = Enabled", $time, cmd_string[cmd], bank); + end + else begin + $display ("%m: at time %t WARNING: %s %d Illegal TDQS Enable. TDQS only exists on a x8 part", $time, cmd_string[cmd], bank); + tdqs_en = 0; + end + end else begin + $display ("%m: at time %t ERROR: %s %d Illegal TDQS Enable = %d", $time, cmd_string[cmd], bank, tdqs_en); + end + // Output Enable + out_en = !addr[12]; + if (!out_en) begin + if (DEBUG) $display ("%m: at time %t INFO: %s %d Qoff = Disabled", $time, cmd_string[cmd], bank); + end else if (out_en) begin + if (DEBUG) $display ("%m: at time %t INFO: %s %d Qoff = Enabled", $time, cmd_string[cmd], bank); + end else begin + $display ("%m: at time %t ERROR: %s %d Illegal Qoff = %d", $time, cmd_string[cmd], bank, out_en); + end + // Reserved + if (ADDR_BITS>13 && addr[13] !== 0 && check_strict_mrbits) begin + $display ("%m: at time %t ERROR: %s %d Illegal value. Reserved address bits must be programmed to zero", $time, cmd_string[cmd], bank); + end + end + 2 : begin + if (feature_pasr) begin + // Partial Array Self Refresh + pasr = addr[2:0]; + case (pasr) + 3'b000 : if (DEBUG) $display ("%m: at time %t INFO: %s %d Partial Array Self Refresh = Bank 0-7", $time, cmd_string[cmd], bank); + 3'b001 : if (DEBUG) $display ("%m: at time %t INFO: %s %d Partial Array Self Refresh = Bank 0-3", $time, cmd_string[cmd], bank); + 3'b010 : if (DEBUG) $display ("%m: at time %t INFO: %s %d Partial Array Self Refresh = Bank 0-1", $time, cmd_string[cmd], bank); + 3'b011 : if (DEBUG) $display ("%m: at time %t INFO: %s %d Partial Array Self Refresh = Bank 0", $time, cmd_string[cmd], bank); + 3'b100 : if (DEBUG) $display ("%m: at time %t INFO: %s %d Partial Array Self Refresh = Bank 2-7", $time, cmd_string[cmd], bank); + 3'b101 : if (DEBUG) $display ("%m: at time %t INFO: %s %d Partial Array Self Refresh = Bank 4-7", $time, cmd_string[cmd], bank); + 3'b110 : if (DEBUG) $display ("%m: at time %t INFO: %s %d Partial Array Self Refresh = Bank 6-7", $time, cmd_string[cmd], bank); + 3'b111 : if (DEBUG) $display ("%m: at time %t INFO: %s %d Partial Array Self Refresh = Bank 7", $time, cmd_string[cmd], bank); + default : $display ("%m: at time %t ERROR: %s %d Illegal Partial Array Self Refresh = %d", $time, cmd_string[cmd], bank, pasr); + endcase + end + else + if (addr[2:0] !== 0 && check_strict_mrbits) begin + $display ("%m: at time %t ERROR: %s %d Illegal value. Reserved address bits must be programmed to zero", $time, cmd_string[cmd], bank); + end + // CAS Write Latency + cas_write_latency = addr[5:3]+5; + set_latency; + if ((cas_write_latency >= CWL_MIN) && (cas_write_latency <= CWL_MAX)) begin + if (DEBUG) $display ("%m: at time %t INFO: %s %d CAS Write Latency = %d", $time, cmd_string[cmd], bank, cas_write_latency); + end else begin + $display ("%m: at time %t ERROR: %s %d Illegal CAS Write Latency = %d", $time, cmd_string[cmd], bank, cas_write_latency); + end + // Auto Self Refresh Method + asr = addr[6]; + if (!asr) begin + if (DEBUG) $display ("%m: at time %t INFO: %s %d Auto Self Refresh = Disabled", $time, cmd_string[cmd], bank); + end else if (asr) begin + if (DEBUG) $display ("%m: at time %t INFO: %s %d Auto Self Refresh = Enabled", $time, cmd_string[cmd], bank); + if (check_strict_mrbits) $display ("%m: at time %t WARNING: %s %d Auto Self Refresh is not modeled", $time, cmd_string[cmd], bank); + end else begin + $display ("%m: at time %t ERROR: %s %d Illegal Auto Self Refresh = %d", $time, cmd_string[cmd], bank, asr); + end + // Self Refresh Temperature + srt = addr[7]; + if (!srt) begin + if (DEBUG) $display ("%m: at time %t INFO: %s %d Self Refresh Temperature = Normal", $time, cmd_string[cmd], bank); + end else if (srt) begin + if (DEBUG) $display ("%m: at time %t INFO: %s %d Self Refresh Temperature = Extended", $time, cmd_string[cmd], bank); + if (check_strict_mrbits) $display ("%m: at time %t WARNING: %s %d Self Refresh Temperature is not modeled", $time, cmd_string[cmd], bank); + end else begin + $display ("%m: at time %t ERROR: %s %d Illegal Self Refresh Temperature = %d", $time, cmd_string[cmd], bank, srt); + end + if (asr && srt) + $display ("%m: at time %t ERROR: %s %d SRT must be set to 0 when ASR is enabled.", $time, cmd_string[cmd], bank); + // Reserved + if (addr[8] !== 0 && check_strict_mrbits) begin + $display ("%m: at time %t ERROR: %s %d Illegal value. Reserved address bits must be programmed to zero", $time, cmd_string[cmd], bank); + end + // Dynamic ODT (Rtt_WR) + odt_rtt_wr = addr[10:9]; + if (odt_rtt_wr == 2'b00) begin + if (DEBUG) $display ("%m: at time %t INFO: %s %d Dynamic ODT = Disabled", $time, cmd_string[cmd], bank); + dyn_odt_en = 0; + end else if ((odt_rtt_wr > 0) && (odt_rtt_wr < 3)) begin + if (DEBUG) $display ("%m: at time %t INFO: %s %d Dynamic ODT Rtt = %d Ohm", $time, cmd_string[cmd], bank, get_rtt_wr(odt_rtt_wr)); + dyn_odt_en = 1; + end else begin + $display ("%m: at time %t ERROR: %s %d Illegal Dynamic ODT = %d", $time, cmd_string[cmd], bank, odt_rtt_wr); + dyn_odt_en = 0; + end + // Reserved + if (ADDR_BITS>13 && addr[13:11] !== 0 && check_strict_mrbits) begin + $display ("%m: at time %t ERROR: %s %d Illegal value. Reserved address bits must be programmed to zero", $time, cmd_string[cmd], bank); + end + end + 3 : begin + mpr_select = addr[1:0]; + // MultiPurpose Register Select + if (mpr_select == 2'b00) begin + if (DEBUG) $display ("%m: at time %t INFO: %s %d MultiPurpose Register Select = Pre-defined pattern", $time, cmd_string[cmd], bank); + end else begin + if (check_strict_mrbits) $display ("%m: at time %t ERROR: %s %d Illegal MultiPurpose Register Select = %d", $time, cmd_string[cmd], bank, mpr_select); + end + // MultiPurpose Register Enable + mpr_en = addr[2]; + if (!mpr_en) begin + if (DEBUG) $display ("%m: at time %t INFO: %s %d MultiPurpose Register Enable = Disabled", $time, cmd_string[cmd], bank); + end else if (mpr_en) begin + if (DEBUG) $display ("%m: at time %t INFO: %s %d MultiPurpose Register Enable = Enabled", $time, cmd_string[cmd], bank); + end else begin + $display ("%m: at time %t ERROR: %s %d Illegal MultiPurpose Register Enable = %d", $time, cmd_string[cmd], bank, mpr_en); + end + // Reserved + if (ADDR_BITS>13 && addr[13:3] !== 0 && check_strict_mrbits) begin + $display ("%m: at time %t ERROR: %s %d Illegal value. Reserved address bits must be programmed to zero", $time, cmd_string[cmd], bank); + end + end + endcase + if (dyn_odt_en && write_levelization) + $display ("%m: at time %t ERROR: Dynamic ODT is not available during Write Leveling mode.", $time); + init_mode_reg[bank] = 1; + mode_reg[bank] = addr; + tm_load_mode <= $time; + ck_load_mode <= ck_cntr; + end + end + REFRESH : begin + if (mpr_en) begin + $display ("%m: at time %t ERROR: %s Failure. Multipurpose Register must be disabled.", $time, cmd_string[cmd]); + if (STOP_ON_ERROR) $stop(0); + end else if (|active_bank) begin + $display ("%m: at time %t ERROR: %s Failure. All banks must be Precharged.", $time, cmd_string[cmd]); + if (STOP_ON_ERROR) $stop(0); + end else begin + if (DEBUG) $display ("%m: at time %t INFO: %s", $time, cmd_string[cmd]); + er_trfc_max = 0; + ref_cntr = ref_cntr + 1; + tm_refresh <= $time; + ck_refresh <= ck_cntr; + end + end + PRECHARGE : begin + if (addr[AP]) begin + if (DEBUG) $display ("%m: at time %t INFO: %s All", $time, cmd_string[cmd]); + end + // PRECHARGE command will be treated as a NOP if there is no open row in that bank (idle state), + // or if the previously open row is already in the process of precharging + if (|active_bank) begin + if (($time - tm_txpr < TXPR) || (ck_cntr - ck_txpr < TXPR_TCK)) + $display ("%m: at time %t ERROR: tXPR violation during %s", $time, cmd_string[cmd]); + if (mpr_en) begin + $display ("%m: at time %t ERROR: %s Failure. Multipurpose Register must be disabled.", $time, cmd_string[cmd]); + if (STOP_ON_ERROR) $stop(0); + end else begin + for (i=0; i<`BANKS; i=i+1) begin + if (active_bank[i]) begin + if (addr[AP] || (i == bank)) begin + + for (j=0; j<=SELF_REF; j=j+1) begin + chk_err(SAME_BANK, i, j, cmd); + chk_err(DIFF_BANK, i, j, cmd); + end + + if (auto_precharge_bank[i]) begin + $display ("%m: at time %t ERROR: %s Failure. Auto Precharge is scheduled to bank %d.", $time, cmd_string[cmd], i); + if (STOP_ON_ERROR) $stop(0); + end else begin + if (DEBUG) $display ("%m: at time %t INFO: %s bank %d", $time, cmd_string[cmd], i); + active_bank[i] = 1'b0; + tm_bank_precharge[i] <= $time; + tm_precharge <= $time; + ck_precharge <= ck_cntr; + end + end + end + end + end + end + end + ACTIVATE : begin + tfaw_cntr = 0; + for (i=0; i<`BANKS; i=i+1) begin + if ($time - tm_bank_activate[i] < TFAW) begin + tfaw_cntr = tfaw_cntr + 1; + end + end + if (tfaw_cntr > 3) begin + $display ("%m: at time %t ERROR: tFAW violation during %s to bank %d", $time, cmd_string[cmd], bank); + end + + if (mpr_en) begin + $display ("%m: at time %t ERROR: %s Failure. Multipurpose Register must be disabled.", $time, cmd_string[cmd]); + if (STOP_ON_ERROR) $stop(0); + end else if (!init_done) begin + $display ("%m: at time %t ERROR: %s Failure. Initialization sequence is not complete.", $time, cmd_string[cmd]); + if (STOP_ON_ERROR) $stop(0); + end else if (active_bank[bank]) begin + $display ("%m: at time %t ERROR: %s Failure. Bank %d must be Precharged.", $time, cmd_string[cmd], bank); + if (STOP_ON_ERROR) $stop(0); + end else begin + if (addr >= 1< AP + if (col >= 1< AP + if (col >= 1< TPD_MAX) + $display ("%m: at time %t ERROR: tPD maximum violation during Power Down Exit", $time); + if (DEBUG) $display ("%m: at time %t INFO: Power Down Exit", $time); + in_power_down = 0; + if ((active_bank == 0) && low_power) begin // precharge power down with dll off + if (ck_cntr - ck_odt < write_latency - 1) + $display ("%m: at time %t WARNING: tANPD violation during Power Down Exit. Synchronous or asynchronous change in termination resistance is possible.", $time); + tm_slow_exit_pd <= $time; + ck_slow_exit_pd <= ck_cntr; + end + tm_power_down <= $time; + ck_power_down <= ck_cntr; + end + if (in_self_refresh) begin + if (($time - tm_freq_change < TCKSRX) || (ck_cntr - ck_freq_change < TCKSRX_TCK)) + $display ("%m: at time %t ERROR: tCKSRX violation during Self Refresh Exit", $time); + if (ck_cntr - ck_cke_cmd < TCKESR_TCK) + $display ("%m: at time %t ERROR: tCKESR violation during Self Refresh Exit", $time); + if ($time - tm_cke < TISXR) + $display ("%m: at time %t ERROR: tISXR violation during Self Refresh Exit", $time); + if (DEBUG) $display ("%m: at time %t INFO: Self Refresh Exit", $time); + in_self_refresh = 0; + ck_dll_reset <= ck_cntr; + ck_self_refresh <= ck_cntr; + tm_self_refresh <= $time; + tm_refresh <= $time; + end + end + endcase + if ((prev_cke !== 1) && (cmd !== NOP)) begin + $display ("%m: at time %t ERROR: NOP or Deselect is required when CKE goes active.", $time); + end + + if (!init_done) begin + case (init_step) + 0 : begin + if ($time - tm_rst_n < 500000000 && check_strict_timing) + $display ("%m at time %t WARNING: 500 us is required after RST_N goes inactive before CKE goes active.", $time); + tm_txpr <= $time; + ck_txpr <= ck_cntr; + init_step = init_step + 1; + end + 1 : if (dll_en) init_step = init_step + 1; + 2 : begin + if (&init_mode_reg && init_dll_reset && zq_set) begin + if (DEBUG) $display ("%m: at time %t INFO: Initialization Sequence is complete", $time); + init_done = 1; + end + end + endcase + end + end else if (prev_cke) begin + if ((!init_done) && (init_step > 1)) begin + $display ("%m: at time %t ERROR: CKE must remain active until the initialization sequence is complete.", $time); + if (STOP_ON_ERROR) $stop(0); + end + case (cmd) + REFRESH : begin + if ($time - tm_txpr < TXPR) + $display ("%m: at time %t ERROR: tXPR violation during %s", $time, cmd_string[SELF_REF]); + for (j=0; j<=SELF_REF; j=j+1) begin + chk_err(DIFF_BANK, bank, j, SELF_REF); + end + + if (mpr_en) begin + $display ("%m: at time %t ERROR: Self Refresh Failure. Multipurpose Register must be disabled.", $time); + if (STOP_ON_ERROR) $stop(0); + end else if (|active_bank) begin + $display ("%m: at time %t ERROR: Self Refresh Failure. All banks must be Precharged.", $time); + if (STOP_ON_ERROR) $stop(0); + end else if (odt_state) begin + $display ("%m: at time %t ERROR: Self Refresh Failure. ODT must be off prior to entering Self Refresh", $time); + if (STOP_ON_ERROR) $stop(0); + end else if (!init_done) begin + $display ("%m: at time %t ERROR: Self Refresh Failure. Initialization sequence is not complete.", $time); + if (STOP_ON_ERROR) $stop(0); + end else begin + if (DEBUG) $display ("%m: at time %t INFO: Self Refresh Enter", $time); + if (feature_pasr) + // Partial Array Self Refresh + case (pasr) + 3'b000 : ;//keep Bank 0-7 + 3'b001 : begin if (DEBUG) $display("%m: at time %t INFO: Banks 4-7 will be lost due to Partial Array Self Refresh", $time); erase_banks(8'hF0); end + 3'b010 : begin if (DEBUG) $display("%m: at time %t INFO: Banks 2-7 will be lost due to Partial Array Self Refresh", $time); erase_banks(8'hFC); end + 3'b011 : begin if (DEBUG) $display("%m: at time %t INFO: Banks 1-7 will be lost due to Partial Array Self Refresh", $time); erase_banks(8'hFE); end + 3'b100 : begin if (DEBUG) $display("%m: at time %t INFO: Banks 0-1 will be lost due to Partial Array Self Refresh", $time); erase_banks(8'h03); end + 3'b101 : begin if (DEBUG) $display("%m: at time %t INFO: Banks 0-3 will be lost due to Partial Array Self Refresh", $time); erase_banks(8'h0F); end + 3'b110 : begin if (DEBUG) $display("%m: at time %t INFO: Banks 0-5 will be lost due to Partial Array Self Refresh", $time); erase_banks(8'h3F); end + 3'b111 : begin if (DEBUG) $display("%m: at time %t INFO: Banks 0-6 will be lost due to Partial Array Self Refresh", $time); erase_banks(8'h7F); end + endcase + in_self_refresh = 1; + dll_locked = 0; + end + end + NOP : begin + // entering precharge power down with dll off and tANPD has not been satisfied + if (low_power && (active_bank == 0) && |odt_pipeline) + $display ("%m: at time %t WARNING: tANPD violation during %s. Synchronous or asynchronous change in termination resistance is possible.", $time, cmd_string[PWR_DOWN]); + if ($time - tm_txpr < TXPR) + $display ("%m: at time %t ERROR: tXPR violation during %s", $time, cmd_string[PWR_DOWN]); + for (j=0; j<=SELF_REF; j=j+1) begin + chk_err(DIFF_BANK, bank, j, PWR_DOWN); + end + + if (mpr_en) begin + $display ("%m: at time %t ERROR: Power Down Failure. Multipurpose Register must be disabled.", $time); + if (STOP_ON_ERROR) $stop(0); + end else if (!init_done) begin + $display ("%m: at time %t ERROR: Power Down Failure. Initialization sequence is not complete.", $time); + if (STOP_ON_ERROR) $stop(0); + end else begin + if (DEBUG) begin + if (|active_bank) begin + $display ("%m: at time %t INFO: Active Power Down Enter", $time); + end else begin + $display ("%m: at time %t INFO: Precharge Power Down Enter", $time); + end + end + in_power_down = 1; + end + end + default : begin + $display ("%m: at time %t ERROR: NOP, Deselect, or Refresh is required when CKE goes inactive.", $time); + end + endcase + end else if (in_self_refresh || in_power_down) begin + if ((ck_cntr - ck_cke_cmd <= TCPDED) && (cmd !== NOP)) + $display ("%m: at time %t ERROR: tCPDED violation during Power Down or Self Refresh Entry. NOP or Deselect is required.", $time); + end + prev_cke = cke; + + end + endtask + + task data_task; + reg [BA_BITS-1:0] bank; + reg [ROW_BITS-1:0] row; + reg [COL_BITS-1:0] col; + integer i; + integer j; + begin + + if (diff_ck) begin + for (i=0; i<32; i=i+1) begin + if (dq_in_valid && dll_locked && ($time - tm_dqs_neg[i] < $rtoi(TDSS*tck_avg))) + $display ("%m: at time %t ERROR: tDSS violation on %s bit %d", $time, dqs_string[i/16], i%16); + if (check_write_dqs_high[i]) + $display ("%m: at time %t ERROR: %s bit %d latching edge required during the preceding clock period.", $time, dqs_string[i/16], i%16); + end + check_write_dqs_high <= 0; + end else begin + for (i=0; i<32; i=i+1) begin + if (dll_locked && dq_in_valid) begin + tm_tdqss = abs_value(1.0*tm_ck_pos - tm_dqss_pos[i]); + if ((tm_tdqss < tck_avg/2.0) && (tm_tdqss > TDQSS*tck_avg)) + $display ("%m: at time %t ERROR: tDQSS violation on %s bit %d", $time, dqs_string[i/16], i%16); + end + if (check_write_dqs_low[i]) + $display ("%m: at time %t ERROR: %s bit %d latching edge required during the preceding clock period", $time, dqs_string[i/16], i%16); + end + check_write_preamble <= 0; + check_write_postamble <= 0; + check_write_dqs_low <= 0; + end + + if (wr_pipeline[0] || rd_pipeline[0]) begin + bank = ba_pipeline[0]; + row = row_pipeline[0]; + col = col_pipeline[0]; + burst_cntr = 0; + memory_read(bank, row, col, memory_data); + end + + // burst counter + if (burst_cntr < burst_length) begin + burst_position = col ^ burst_cntr; + if (!burst_order) begin + burst_position[BO_BITS-1:0] = col + burst_cntr; + end + burst_cntr = burst_cntr + 1; + end + + // write dqs counter + if (wr_pipeline[WDQS_PRE + 1]) begin + wdqs_cntr = WDQS_PRE + bl_pipeline[WDQS_PRE + 1] + WDQS_PST - 1; + end + // write dqs + if ((wr_pipeline[2]) && (wdq_cntr == 0)) begin //write preamble + check_write_preamble <= ({DQS_BITS{1'b1}}<<16) | {DQS_BITS{1'b1}}; + end + if (wdqs_cntr > 1) begin // write data + if ((wdqs_cntr - WDQS_PST)%2) begin + check_write_dqs_high <= ({DQS_BITS{1'b1}}<<16) | {DQS_BITS{1'b1}}; + end else begin + check_write_dqs_low <= ({DQS_BITS{1'b1}}<<16) | {DQS_BITS{1'b1}}; + end + end + if (wdqs_cntr == WDQS_PST) begin // write postamble + check_write_postamble <= ({DQS_BITS{1'b1}}<<16) | {DQS_BITS{1'b1}}; + end + if (wdqs_cntr > 0) begin + wdqs_cntr = wdqs_cntr - 1; + end + + // write dq + if (dq_in_valid) begin // write data + bit_mask = 0; + if (diff_ck) begin + for (i=0; i>(burst_position*DQ_BITS); + if (DEBUG) $display ("%m: at time %t INFO: WRITE @ DQS= bank = %h row = %h col = %h data = %h",$time, bank, row, (-1*BL_MAX & col) + burst_position, dq_temp); + if (burst_cntr%BL_MIN == 0) begin + memory_write(bank, row, col, memory_data); + end + end + if (wr_pipeline[1]) begin + wdq_cntr = bl_pipeline[1]; + end + if (wdq_cntr > 0) begin + wdq_cntr = wdq_cntr - 1; + dq_in_valid = 1'b1; + end else begin + dq_in_valid = 1'b0; + dqs_in_valid <= 1'b0; + for (i=0; i<31; i=i+1) begin + wdqs_pos_cntr[i] <= 0; + end + end + if (wr_pipeline[0]) begin + b2b_write <= 1'b0; + end + if (wr_pipeline[2]) begin + if (dqs_in_valid) begin + b2b_write <= 1'b1; + end + dqs_in_valid <= 1'b1; + wr_burst_length = bl_pipeline[2]; + end + + // read dqs enable counter + if (rd_pipeline[RDQSEN_PRE]) begin + rdqsen_cntr = RDQSEN_PRE + bl_pipeline[RDQSEN_PRE] + RDQSEN_PST - 1; + end + if (rdqsen_cntr > 0) begin + rdqsen_cntr = rdqsen_cntr - 1; + dqs_out_en = 1'b1; + end else begin + dqs_out_en = 1'b0; + end + + // read dqs counter + if (rd_pipeline[RDQS_PRE]) begin + rdqs_cntr = RDQS_PRE + bl_pipeline[RDQS_PRE] + RDQS_PST - 1; + end + // read dqs + if (((rd_pipeline>>1 & {RDQS_PRE{1'b1}}) > 0) && (rdq_cntr == 0)) begin //read preamble + dqs_out = 1'b0; + end else if (rdqs_cntr > RDQS_PST) begin // read data + dqs_out = rdqs_cntr - RDQS_PST; + end else if (rdqs_cntr > 0) begin // read postamble + dqs_out = 1'b0; + end else begin + dqs_out = 1'b1; + end + if (rdqs_cntr > 0) begin + rdqs_cntr = rdqs_cntr - 1; + end + + // read dq enable counter + if (rd_pipeline[RDQEN_PRE]) begin + rdqen_cntr = RDQEN_PRE + bl_pipeline[RDQEN_PRE] + RDQEN_PST; + end + if (rdqen_cntr > 0) begin + rdqen_cntr = rdqen_cntr - 1; + dq_out_en = 1'b1; + end else begin + dq_out_en = 1'b0; + end + // read dq + if (rd_pipeline[0]) begin + rdq_cntr = bl_pipeline[0]; + end + if (rdq_cntr > 0) begin // read data + if (mpr_en) begin +`ifdef MPR_DQ0 // DQ0 output MPR data, other DQ low + if (mpr_select == 2'b00) begin // Calibration Pattern + dq_temp = {DQS_BITS{{`DQ_PER_DQS-1{1'b0}}, calibration_pattern[burst_position]}}; + end else if (odts_readout && (mpr_select == 2'b11)) begin // Temp Sensor (ODTS) + dq_temp = {DQS_BITS{{`DQ_PER_DQS-1{1'b0}}, temp_sensor[burst_position]}}; + end else begin // Reserved + dq_temp = {DQS_BITS{{`DQ_PER_DQS-1{1'b0}}, 1'bx}}; + end +`else // all DQ output MPR data + if (mpr_select == 2'b00) begin // Calibration Pattern + dq_temp = {DQS_BITS{{`DQ_PER_DQS{calibration_pattern[burst_position]}}}}; + end else if (odts_readout && (mpr_select == 2'b11)) begin // Temp Sensor (ODTS) + dq_temp = {DQS_BITS{{`DQ_PER_DQS{temp_sensor[burst_position]}}}}; + end else begin // Reserved + dq_temp = {DQS_BITS{{`DQ_PER_DQS{1'bx}}}}; + end +`endif + if (DEBUG) $display ("%m: at time %t READ @ DQS MultiPurpose Register %d, col = %d, data = %b", $time, mpr_select, burst_position, dq_temp[0]); + end else begin + dq_temp = memory_data>>(burst_position*DQ_BITS); + if (DEBUG) $display ("%m: at time %t INFO: READ @ DQS= bank = %h row = %h col = %h data = %h",$time, bank, row, (-1*BL_MAX & col) + burst_position, dq_temp); + end + dq_out = dq_temp; + rdq_cntr = rdq_cntr - 1; + end else begin + dq_out = {DQ_BITS{1'b1}}; + end + + // delay signals prior to output + if (RANDOM_OUT_DELAY && (dqs_out_en || (|dqs_out_en_dly) || dq_out_en || (|dq_out_en_dly))) begin + for (i=0; i dqsck[i] + TQH*tck_avg + TDQSQ) begin + dqsck_max = dqsck[i] + TQH*tck_avg + TDQSQ; + end + dqsck_min = -1*TDQSCK; + if (dqsck_min < dqsck[i] - TQH*tck_avg - TDQSQ) begin + dqsck_min = dqsck[i] - TQH*tck_avg - TDQSQ; + end + + // DQSQ requirements + // 1.) less than tDQSQ + // 2.) greater than 0 + // 3.) greater than tQH from the previous DQS edge + dqsq_min = 0; + if (dqsq_min < dqsck[i] - TQH*tck_avg) begin + dqsq_min = dqsck[i] - TQH*tck_avg; + end + if (dqsck_min == dqsck_max) begin + dqsck[i] = dqsck_min; + end else begin + dqsck[i] = $dist_uniform(seed, dqsck_min, dqsck_max); + end + dqsq_max = TDQSQ + dqsck[i]; + + dqs_out_en_dly[i] <= #(tck_avg/2) dqs_out_en; + dqs_out_dly[i] <= #(tck_avg/2 + dqsck[i]) dqs_out; + if (!write_levelization) begin + for (j=0; j<`DQ_PER_DQS; j=j+1) begin + dq_out_en_dly[i*`DQ_PER_DQS + j] <= #(tck_avg/2) dq_out_en; + if (dqsq_min == dqsq_max) begin + dq_out_dly [i*`DQ_PER_DQS + j] <= #(tck_avg/2 + dqsq_min) dq_out[i*`DQ_PER_DQS + j]; + end else begin + dq_out_dly [i*`DQ_PER_DQS + j] <= #(tck_avg/2 + $dist_uniform(seed, dqsq_min, dqsq_max)) dq_out[i*`DQ_PER_DQS + j]; + end + end + end + end + end else begin + out_delay = tck_avg/2; + dqs_out_en_dly <= #(out_delay) {DQS_BITS{dqs_out_en}}; + dqs_out_dly <= #(out_delay) {DQS_BITS{dqs_out }}; + if (write_levelization !== 1'b1) begin + dq_out_en_dly <= #(out_delay) {DQ_BITS {dq_out_en }}; + dq_out_dly <= #(out_delay) {DQ_BITS {dq_out }}; + end + end + end + endtask + + always @ (posedge rst_n_in) begin : reset + integer i; + if (rst_n_in) begin + if ($time < 200000000 && check_strict_timing) + $display ("%m at time %t WARNING: 200 us is required before RST_N goes inactive.", $time); + if (cke_in !== 1'b0) + $display ("%m: at time %t ERROR: CKE must be inactive when RST_N goes inactive.", $time); + if ($time - tm_cke < 10000) + $display ("%m: at time %t ERROR: CKE must be maintained inactive for 10 ns before RST_N goes inactive.", $time); + + // clear memory +`ifdef MAX_MEM + // verification group does not erase memory + // for (banki = 0; banki < `BANKS; banki = banki + 1) begin + // $fclose(memfd[banki]); + // memfd[banki] = open_bank_file(banki); + // end +`else + memory_used <= 0; //erase memory +`endif + + end + end + + always @(negedge rst_n_in or posedge diff_ck or negedge diff_ck) begin : main + integer i; + if (!rst_n_in) begin + reset_task; + end else begin + if (!in_self_refresh && (diff_ck !== 1'b0) && (diff_ck !== 1'b1)) + $display ("%m: at time %t ERROR: CK and CK_N are not allowed to go to an unknown state.", $time); + data_task; + + // Clock Frequency Change is legal: + // 1.) During Self Refresh + // 2.) During Precharge Power Down (DLL on or off) + if (in_self_refresh || (in_power_down && (active_bank == 0))) begin + if (diff_ck) begin + tjit_per_rtime = $time - tm_ck_pos - tck_avg; + end else begin + tjit_per_rtime = $time - tm_ck_neg - tck_avg; + end + if (dll_locked && (abs_value(tjit_per_rtime) > TJIT_PER)) begin + if ((tm_ck_pos - tm_cke_cmd < TCKSRE) || (ck_cntr - ck_cke_cmd < TCKSRE_TCK)) + $display ("%m: at time %t ERROR: tCKSRE violation during Self Refresh or Precharge Power Down Entry", $time); + if (odt_state) begin + $display ("%m: at time %t ERROR: Clock Frequency Change Failure. ODT must be off prior to Clock Frequency Change.", $time); + if (STOP_ON_ERROR) $stop(0); + end else begin + if (DEBUG) $display ("%m: at time %t INFO: Clock Frequency Change detected. DLL Reset is Required.", $time); + tm_freq_change <= $time; + ck_freq_change <= ck_cntr; + dll_locked = 0; + end + end + end + + if (diff_ck) begin + // check setup of command signals + if ($time > TIS) begin + if ($time - tm_cke < TIS) + $display ("%m: at time %t ERROR: tIS violation on CKE by %t", $time, tm_cke + TIS - $time); + if (cke_in) begin + for (i=0; i<22; i=i+1) begin + if ($time - tm_cmd_addr[i] < TIS) + $display ("%m: at time %t ERROR: tIS violation on %s by %t", $time, cmd_addr_string[i], tm_cmd_addr[i] + TIS - $time); + end + end + end + + // update current state + if (dll_locked) begin + if (mr_chk == 0) begin + mr_chk = 1; + end else if (init_mode_reg[0] && (mr_chk == 1)) begin + // check CL value against the clock frequency + if (cas_latency*tck_avg < CL_TIME && check_strict_timing) + $display ("%m: at time %t ERROR: CAS Latency = %d is illegal @tCK(avg) = %f", $time, cas_latency, tck_avg); + // check WR value against the clock frequency + if (ceil(write_recovery*tck_avg) < TWR) + $display ("%m: at time %t ERROR: Write Recovery = %d is illegal @tCK(avg) = %f", $time, write_recovery, tck_avg); + // check the CWL value against the clock frequency + if (check_strict_timing) begin + case (cas_write_latency) + 5 : if (tck_avg < 2500.0) $display ("%m: at time %t ERROR: CWL = %d is illegal @tCK(avg) = %f", $time, cas_write_latency, tck_avg); + 6 : if ((tck_avg < 1875.0) || (tck_avg >= 2500.0)) $display ("%m: at time %t ERROR: CWL = %d is illegal @tCK(avg) = %f", $time, cas_write_latency, tck_avg); + 7 : if ((tck_avg < 1500.0) || (tck_avg >= 1875.0)) $display ("%m: at time %t ERROR: CWL = %d is illegal @tCK(avg) = %f", $time, cas_write_latency, tck_avg); + 8 : if ((tck_avg < 1250.0) || (tck_avg >= 1500.0)) $display ("%m: at time %t ERROR: CWL = %d is illegal @tCK(avg) = %f", $time, cas_write_latency, tck_avg); + 9 : if ((tck_avg < 15e3/14) || (tck_avg >= 1250.0)) $display ("%m: at time %t ERROR: CWL = %d is illegal @tCK(avg) = %f", $time, cas_write_latency, tck_avg); + 10: if ((tck_avg < 937.5) || (tck_avg >= 15e3/14)) $display ("%m: at time %t ERROR: CWL = %d is illegal @tCK(avg) = %f", $time, cas_write_latency, tck_avg); + default : $display ("%m: at time %t ERROR: CWL = %d is illegal @tCK(avg) = %f", $time, cas_write_latency, tck_avg); + endcase + // check the CL value against the clock frequency + if (!valid_cl(cas_latency, cas_write_latency)) + $display ("%m: at time %t ERROR: CAS Latency = %d is not valid when CAS Write Latency = %d", $time, cas_latency, cas_write_latency); + end + mr_chk = 2; + end + end else if (!in_self_refresh) begin + mr_chk = 0; + if (ck_cntr - ck_dll_reset == TDLLK) begin + dll_locked = 1; + end + end + + if (|auto_precharge_bank) begin + for (i=0; i<`BANKS; i=i+1) begin + // Write with Auto Precharge Calculation + // 1. Meet minimum tRAS requirement + // 2. Write Latency PLUS BL/2 cycles PLUS WR after Write command + if (write_precharge_bank[i]) begin + if ($time - tm_bank_activate[i] >= TRAS_MIN) begin + if (ck_cntr - ck_bank_write[i] >= write_latency + burst_length/2 + write_recovery) begin + if (DEBUG) $display ("%m: at time %t INFO: Auto Precharge bank %d", $time, i); + write_precharge_bank[i] = 0; + active_bank[i] = 0; + auto_precharge_bank[i] = 0; + tm_bank_precharge[i] = $time; + tm_precharge = $time; + ck_precharge = ck_cntr; + end + end + end + // Read with Auto Precharge Calculation + // 1. Meet minimum tRAS requirement + // 2. Additive Latency plus 4 cycles after Read command + // 3. tRTP after the last 8-bit prefetch + if (read_precharge_bank[i]) begin + if (($time - tm_bank_activate[i] >= TRAS_MIN) && (ck_cntr - ck_bank_read[i] >= additive_latency + TRTP_TCK)) begin + read_precharge_bank[i] = 0; + // In case the internal precharge is pushed out by tRTP, tRP starts at the point where + // the internal precharge happens (not at the next rising clock edge after this event). + if ($time - tm_bank_read_end[i] < TRTP) begin + if (DEBUG) $display ("%m: at time %t INFO: Auto Precharge bank %d", tm_bank_read_end[i] + TRTP, i); + active_bank[i] <= #(tm_bank_read_end[i] + TRTP - $time) 0; + auto_precharge_bank[i] <= #(tm_bank_read_end[i] + TRTP - $time) 0; + tm_bank_precharge[i] <= #(tm_bank_read_end[i] + TRTP - $time) tm_bank_read_end[i] + TRTP; + tm_precharge <= #(tm_bank_read_end[i] + TRTP - $time) tm_bank_read_end[i] + TRTP; + ck_precharge = ck_cntr; + end else begin + if (DEBUG) $display ("%m: at time %t INFO: Auto Precharge bank %d", $time, i); + active_bank[i] = 0; + auto_precharge_bank[i] = 0; + tm_bank_precharge[i] = $time; + tm_precharge = $time; + ck_precharge = ck_cntr; + end + end + end + end + end + + // respond to incoming command + if (cke_in ^ prev_cke) begin + tm_cke_cmd <= $time; + ck_cke_cmd <= ck_cntr; + end + + cmd_task(cke_in, cmd_n_in, ba_in, addr_in); + if ((cmd_n_in == WRITE) || (cmd_n_in == READ)) begin + al_pipeline[2*additive_latency] = 1'b1; + end + if (al_pipeline[0]) begin + // check tRCD after additive latency + if ((rd_pipeline[2*cas_latency - 1]) && ($time - tm_bank_activate[ba_pipeline[2*cas_latency - 1]] < TRCD)) + $display ("%m: at time %t ERROR: tRCD violation during %s", $time, cmd_string[READ]); + if ((wr_pipeline[2*cas_write_latency + 1]) && ($time - tm_bank_activate[ba_pipeline[2*cas_write_latency + 1]] < TRCD)) + $display ("%m: at time %t ERROR: tRCD violation during %s", $time, cmd_string[WRITE]); + // check tWTR after additive latency + if (rd_pipeline[2*cas_latency - 1]) begin //{ + if (truebl4) begin //{ + i = ba_pipeline[2*cas_latency - 1]; + if ($time - tm_group_write_end[i[1]] < TWTR) + $display ("%m: at time %t ERROR: tWTR violation during %s", $time, cmd_string[READ]); + if ($time - tm_write_end < TWTR_DG) + $display ("%m: at time %t ERROR: tWTR_DG violation during %s", $time, cmd_string[READ]); + end else begin + if ($time - tm_write_end < TWTR) + $display ("%m: at time %t ERROR: tWTR violation during %s", $time, cmd_string[READ]); + end + end + end + if (rd_pipeline) begin + if (rd_pipeline[2*cas_latency - 1]) begin + tm_bank_read_end[ba_pipeline[2*cas_latency - 1]] <= $time; + end + end + for (i=0; i<`BANKS; i=i+1) begin + if ((ck_cntr - ck_bank_write[i] > write_latency) && (ck_cntr - ck_bank_write[i] <= write_latency + burst_length/2)) begin + tm_bank_write_end[i] <= $time; + tm_group_write_end[i[1]] <= $time; + tm_write_end <= $time; + end + end + + // clk pin is disabled during self refresh + if (!in_self_refresh && tm_ck_pos ) begin + tjit_cc_time = $time - tm_ck_pos - tck_i; + tck_i = $time - tm_ck_pos; + tck_avg = tck_avg - tck_sample[ck_cntr%TDLLK]/$itor(TDLLK); + tck_avg = tck_avg + tck_i/$itor(TDLLK); + tck_sample[ck_cntr%TDLLK] = tck_i; + tjit_per_rtime = tck_i - tck_avg; + + if (dll_locked && check_strict_timing) begin + // check accumulated error + terr_nper_rtime = 0; + for (i=0; i<12; i=i+1) begin + terr_nper_rtime = terr_nper_rtime + tck_sample[i] - tck_avg; + terr_nper_rtime = abs_value(terr_nper_rtime); + case (i) + 0 :; + 1 : if (terr_nper_rtime - TERR_2PER >= 1.0) $display ("%m: at time %t ERROR: tERR(2per) violation by %f ps.", $time, terr_nper_rtime - TERR_2PER); + 2 : if (terr_nper_rtime - TERR_3PER >= 1.0) $display ("%m: at time %t ERROR: tERR(3per) violation by %f ps.", $time, terr_nper_rtime - TERR_3PER); + 3 : if (terr_nper_rtime - TERR_4PER >= 1.0) $display ("%m: at time %t ERROR: tERR(4per) violation by %f ps.", $time, terr_nper_rtime - TERR_4PER); + 4 : if (terr_nper_rtime - TERR_5PER >= 1.0) $display ("%m: at time %t ERROR: tERR(5per) violation by %f ps.", $time, terr_nper_rtime - TERR_5PER); + 5 : if (terr_nper_rtime - TERR_6PER >= 1.0) $display ("%m: at time %t ERROR: tERR(6per) violation by %f ps.", $time, terr_nper_rtime - TERR_6PER); + 6 : if (terr_nper_rtime - TERR_7PER >= 1.0) $display ("%m: at time %t ERROR: tERR(7per) violation by %f ps.", $time, terr_nper_rtime - TERR_7PER); + 7 : if (terr_nper_rtime - TERR_8PER >= 1.0) $display ("%m: at time %t ERROR: tERR(8per) violation by %f ps.", $time, terr_nper_rtime - TERR_8PER); + 8 : if (terr_nper_rtime - TERR_9PER >= 1.0) $display ("%m: at time %t ERROR: tERR(9per) violation by %f ps.", $time, terr_nper_rtime - TERR_9PER); + 9 : if (terr_nper_rtime - TERR_10PER >= 1.0) $display ("%m: at time %t ERROR: tERR(10per) violation by %f ps.", $time, terr_nper_rtime - TERR_10PER); + 10 : if (terr_nper_rtime - TERR_11PER >= 1.0) $display ("%m: at time %t ERROR: tERR(11per) violation by %f ps.", $time, terr_nper_rtime - TERR_11PER); + 11 : if (terr_nper_rtime - TERR_12PER >= 1.0) $display ("%m: at time %t ERROR: tERR(12per) violation by %f ps.", $time, terr_nper_rtime - TERR_12PER); + endcase + end + + // check tCK min/max/jitter + if (abs_value(tjit_per_rtime) - TJIT_PER >= 1.0) + $display ("%m: at time %t ERROR: tJIT(per) violation by %f ps.", $time, abs_value(tjit_per_rtime) - TJIT_PER); + if (abs_value(tjit_cc_time) - TJIT_CC >= 1.0) + $display ("%m: at time %t ERROR: tJIT(cc) violation by %f ps.", $time, abs_value(tjit_cc_time) - TJIT_CC); + if (TCK_MIN - tck_avg >= 1.0) + $display ("%m: at time %t ERROR: tCK(avg) minimum violation by %f ps.", $time, TCK_MIN - tck_avg); + if (tck_avg - TCK_MAX >= 1.0) + $display ("%m: at time %t ERROR: tCK(avg) maximum violation by %f ps.", $time, tck_avg - TCK_MAX); + + // check tCL + if (tm_ck_neg - $time < TCL_ABS_MIN*tck_avg) + $display ("%m: at time %t ERROR: tCL(abs) minimum violation on CLK by %t", $time, TCL_ABS_MIN*tck_avg - tm_ck_neg + $time); + if (tcl_avg < TCL_AVG_MIN*tck_avg) + $display ("%m: at time %t ERROR: tCL(avg) minimum violation on CLK by %t", $time, TCL_AVG_MIN*tck_avg - tcl_avg); + if (tcl_avg > TCL_AVG_MAX*tck_avg) + $display ("%m: at time %t ERROR: tCL(avg) maximum violation on CLK by %t", $time, tcl_avg - TCL_AVG_MAX*tck_avg); + end + + // calculate the tch avg jitter + tch_avg = tch_avg - tch_sample[ck_cntr%TDLLK]/$itor(TDLLK); + tch_avg = tch_avg + tch_i/$itor(TDLLK); + tch_sample[ck_cntr%TDLLK] = tch_i; + tjit_ch_rtime = tch_i - tch_avg; + duty_cycle = tch_avg/tck_avg; + + // update timers/counters + tcl_i <= $time - tm_ck_neg; + end + + prev_odt <= odt_in; + // update timers/counters + ck_cntr <= ck_cntr + 1; + tm_ck_pos = $time; + end else begin + // clk pin is disabled during self refresh + if (!in_self_refresh) begin + if (dll_locked && check_strict_timing) begin + if ($time - tm_ck_pos < TCH_ABS_MIN*tck_avg) + $display ("%m: at time %t ERROR: tCH(abs) minimum violation on CLK by %t", $time, TCH_ABS_MIN*tck_avg - $time + tm_ck_pos); + if (tch_avg < TCH_AVG_MIN*tck_avg) + $display ("%m: at time %t ERROR: tCH(avg) minimum violation on CLK by %t", $time, TCH_AVG_MIN*tck_avg - tch_avg); + if (tch_avg > TCH_AVG_MAX*tck_avg) + $display ("%m: at time %t ERROR: tCH(avg) maximum violation on CLK by %t", $time, tch_avg - TCH_AVG_MAX*tck_avg); + end + + // calculate the tcl avg jitter + tcl_avg = tcl_avg - tcl_sample[ck_cntr%TDLLK]/$itor(TDLLK); + tcl_avg = tcl_avg + tcl_i/$itor(TDLLK); + tcl_sample[ck_cntr%TDLLK] = tcl_i; + + // update timers/counters + tch_i <= $time - tm_ck_pos; + end + tm_ck_neg = $time; + end + + // on die termination + if (odt_en || dyn_odt_en) begin + // odt pin is disabled during self refresh + if (!in_self_refresh && diff_ck) begin + if ($time - tm_odt < TIS) + $display ("%m: at time %t ERROR: tIS violation on ODT by %t", $time, tm_odt + TIS - $time); + if (prev_odt ^ odt_in) begin + if (!dll_locked) + $display ("%m: at time %t WARNING: tDLLK violation during ODT transition.", $time); + if (($time - tm_load_mode < TMOD) || (ck_cntr - ck_load_mode < TMOD_TCK)) + $display ("%m: at time %t ERROR: tMOD violation during ODT transition", $time); + if (ck_cntr - ck_zqinit < TZQINIT) + $display ("%m: at time %t ERROR: TZQinit violation during ODT transition", $time); + if (ck_cntr - ck_zqoper < TZQOPER) + $display ("%m: at time %t ERROR: TZQoper violation during ODT transition", $time); + if (ck_cntr - ck_zqcs < TZQCS) + $display ("%m: at time %t ERROR: tZQcs violation during ODT transition", $time); + // if (($time - tm_slow_exit_pd < TXPDLL) || (ck_cntr - ck_slow_exit_pd < TXPDLL_TCK)) + // $display ("%m: at time %t ERROR: tXPDLL violation during ODT transition", $time); + if (ck_cntr - ck_self_refresh < TXSDLL) + $display ("%m: at time %t ERROR: tXSDLL violation during ODT transition", $time); + if (in_self_refresh) + $display ("%m: at time %t ERROR: Illegal ODT transition during Self Refresh.", $time); + if (!odt_in && (ck_cntr - ck_odt < ODTH4)) + $display ("%m: at time %t ERROR: ODTH4 violation during ODT transition", $time); + if (!odt_in && (ck_cntr - ck_odth8 < ODTH8)) + $display ("%m: at time %t ERROR: ODTH8 violation during ODT transition", $time); + if (($time - tm_slow_exit_pd < TXPDLL) || (ck_cntr - ck_slow_exit_pd < TXPDLL_TCK)) + $display ("%m: at time %t WARNING: tXPDLL during ODT transition. Synchronous or asynchronous change in termination resistance is possible.", $time); + + // async ODT mode applies: + // 1.) during precharge power down with DLL off + // 2.) if tANPD has not been satisfied + // 3.) until tXPDLL has been satisfied + if ((in_power_down && low_power && (active_bank == 0)) || ($time - tm_slow_exit_pd < TXPDLL) || (ck_cntr - ck_slow_exit_pd < TXPDLL_TCK)) begin + odt_state = odt_in; + if (DEBUG && odt_en) $display ("%m: at time %t INFO: Async On Die Termination Rtt_NOM = %d Ohm", $time, {32{odt_state}} & get_rtt_nom(odt_rtt_nom)); + if (odt_state) begin + odt_state_dly <= #(TAONPD) odt_state; + end else begin + odt_state_dly <= #(TAOFPD) odt_state; + end + // sync ODT mode applies: + // 1.) during normal operation + // 2.) during active power down + // 3.) during precharge power down with DLL on + end else begin + odt_pipeline[2*(write_latency - 2)] = 1'b1; // ODTLon, ODTLoff + end + ck_odt <= ck_cntr; + end + end + if (odt_pipeline[0]) begin + odt_state = ~odt_state; + if (DEBUG && odt_en) $display ("%m: at time %t INFO: Sync On Die Termination Rtt_NOM = %d Ohm", $time, {32{odt_state}} & get_rtt_nom(odt_rtt_nom)); + if (odt_state) begin + odt_state_dly <= #(TAON) odt_state; + end else begin + odt_state_dly <= #(TAOF*tck_avg) odt_state; + end + end + if (rd_pipeline[RDQSEN_PRE]) begin + odt_cntr = 1 + RDQSEN_PRE + bl_pipeline[RDQSEN_PRE] + RDQSEN_PST - 1; + end + if (odt_cntr > 0) begin + if (odt_state) begin + $display ("%m: at time %t ERROR: On Die Termination must be OFF during Read data transfer.", $time); + end + odt_cntr = odt_cntr - 1; + end + if (dyn_odt_en && odt_state) begin + if (DEBUG && (dyn_odt_state ^ dyn_odt_pipeline[0])) + $display ("%m: at time %t INFO: Sync On Die Termination Rtt_WR = %d Ohm", $time, {32{dyn_odt_pipeline[0]}} & get_rtt_wr(odt_rtt_wr)); + dyn_odt_state = dyn_odt_pipeline[0]; + end + dyn_odt_state_dly <= #(TADC*tck_avg) dyn_odt_state; + end + + if (cke_in && write_levelization) begin + for (i=0; i>1; + wr_pipeline = wr_pipeline>>1; + rd_pipeline = rd_pipeline>>1; + for (i=0; i<`MAX_PIPE; i=i+1) begin + bl_pipeline[i] = bl_pipeline[i+1]; + ba_pipeline[i] = ba_pipeline[i+1]; + row_pipeline[i] = row_pipeline[i+1]; + col_pipeline[i] = col_pipeline[i+1]; + end + end + if (|odt_pipeline || |dyn_odt_pipeline) begin + odt_pipeline = odt_pipeline>>1; + dyn_odt_pipeline = dyn_odt_pipeline>>1; + end + end + end + + // receiver(s) + task dqs_even_receiver; + input [3:0] i; + reg [63:0] bit_mask; + begin + bit_mask = {`DQ_PER_DQS{1'b1}}<<(i*`DQ_PER_DQS); + if (dqs_even[i]) begin + if (tdqs_en) begin // tdqs disables dm + dm_in_pos[i] = 1'b0; + end else begin + dm_in_pos[i] = dm_in[i]; + end + dq_in_pos = (dq_in & bit_mask) | (dq_in_pos & ~bit_mask); + end + end + endtask + + always @(posedge dqs_even[ 0]) dqs_even_receiver( 0); + always @(posedge dqs_even[ 1]) dqs_even_receiver( 1); + always @(posedge dqs_even[ 2]) dqs_even_receiver( 2); + always @(posedge dqs_even[ 3]) dqs_even_receiver( 3); + always @(posedge dqs_even[ 4]) dqs_even_receiver( 4); + always @(posedge dqs_even[ 5]) dqs_even_receiver( 5); + always @(posedge dqs_even[ 6]) dqs_even_receiver( 6); + always @(posedge dqs_even[ 7]) dqs_even_receiver( 7); + always @(posedge dqs_even[ 8]) dqs_even_receiver( 8); + always @(posedge dqs_even[ 9]) dqs_even_receiver( 9); + always @(posedge dqs_even[10]) dqs_even_receiver(10); + always @(posedge dqs_even[11]) dqs_even_receiver(11); + always @(posedge dqs_even[12]) dqs_even_receiver(12); + always @(posedge dqs_even[13]) dqs_even_receiver(13); + always @(posedge dqs_even[14]) dqs_even_receiver(14); + always @(posedge dqs_even[15]) dqs_even_receiver(15); + + task dqs_odd_receiver; + input [3:0] i; + reg [63:0] bit_mask; + begin + bit_mask = {`DQ_PER_DQS{1'b1}}<<(i*`DQ_PER_DQS); + if (dqs_odd[i]) begin + if (tdqs_en) begin // tdqs disables dm + dm_in_neg[i] = 1'b0; + end else begin + dm_in_neg[i] = dm_in[i]; + end + dq_in_neg = (dq_in & bit_mask) | (dq_in_neg & ~bit_mask); + end + end + endtask + + always @(posedge dqs_odd[ 0]) dqs_odd_receiver( 0); + always @(posedge dqs_odd[ 1]) dqs_odd_receiver( 1); + always @(posedge dqs_odd[ 2]) dqs_odd_receiver( 2); + always @(posedge dqs_odd[ 3]) dqs_odd_receiver( 3); + always @(posedge dqs_odd[ 4]) dqs_odd_receiver( 4); + always @(posedge dqs_odd[ 5]) dqs_odd_receiver( 5); + always @(posedge dqs_odd[ 6]) dqs_odd_receiver( 6); + always @(posedge dqs_odd[ 7]) dqs_odd_receiver( 7); + always @(posedge dqs_odd[ 8]) dqs_odd_receiver( 8); + always @(posedge dqs_odd[ 9]) dqs_odd_receiver( 9); + always @(posedge dqs_odd[10]) dqs_odd_receiver(10); + always @(posedge dqs_odd[11]) dqs_odd_receiver(11); + always @(posedge dqs_odd[12]) dqs_odd_receiver(12); + always @(posedge dqs_odd[13]) dqs_odd_receiver(13); + always @(posedge dqs_odd[14]) dqs_odd_receiver(14); + always @(posedge dqs_odd[15]) dqs_odd_receiver(15); + + // Processes to check hold and pulse width of control signals + always @(posedge rst_n_in) begin + if ($time > 100000) begin + if (tm_rst_n + 100000 > $time) + $display ("%m: at time %t ERROR: RST_N pulse width violation by %t", $time, tm_rst_n + 100000 - $time); + end + tm_rst_n = $time; + end + always @(cke_in) begin + if (rst_n_in) begin + if ($time > TIH) begin + if ($time - tm_ck_pos < TIH) + $display ("%m: at time %t ERROR: tIH violation on CKE by %t", $time, tm_ck_pos + TIH - $time); + end + if ($time - tm_cke < TIPW) + $display ("%m: at time %t ERROR: tIPW violation on CKE by %t", $time, tm_cke + TIPW - $time); + end + tm_cke = $time; + end + always @(odt_in) begin + if (rst_n_in && odt_en && !in_self_refresh) begin + if ($time - tm_ck_pos < TIH) + $display ("%m: at time %t ERROR: tIH violation on ODT by %t", $time, tm_ck_pos + TIH - $time); + if ($time - tm_odt < TIPW) + $display ("%m: at time %t ERROR: tIPW violation on ODT by %t", $time, tm_odt + TIPW - $time); + end + tm_odt = $time; + end + + task cmd_addr_timing_check; + input i; + reg [4:0] i; + begin + if (rst_n_in && prev_cke) begin + if ((i == 0) && ($time - tm_ck_pos < TIH)) // always check tIH for CS# + $display ("%m: at time %t ERROR: tIH violation on %s by %t", $time, cmd_addr_string[i], tm_ck_pos + TIH - $time); + if ((i > 0) && (cs_n_in == 0) &&($time - tm_ck_pos < TIH)) // Only check tIH for cmd_addr if CS# is low + $display ("%m: at time %t ERROR: tIH violation on %s by %t", $time, cmd_addr_string[i], tm_ck_pos + TIH - $time); + if ($time - tm_cmd_addr[i] < TIPW) + $display ("%m: at time %t ERROR: tIPW violation on %s by %t", $time, cmd_addr_string[i], tm_cmd_addr[i] + TIPW - $time); + end + tm_cmd_addr[i] = $time; + end + endtask + + always @(cs_n_in ) cmd_addr_timing_check( 0); + always @(ras_n_in ) cmd_addr_timing_check( 1); + always @(cas_n_in ) cmd_addr_timing_check( 2); + always @(we_n_in ) cmd_addr_timing_check( 3); + always @(ba_in [ 0]) cmd_addr_timing_check( 4); + always @(ba_in [ 1]) cmd_addr_timing_check( 5); + always @(ba_in [ 2]) cmd_addr_timing_check( 6); + always @(addr_in[ 0]) cmd_addr_timing_check( 7); + always @(addr_in[ 1]) cmd_addr_timing_check( 8); + always @(addr_in[ 2]) cmd_addr_timing_check( 9); + always @(addr_in[ 3]) cmd_addr_timing_check(10); + always @(addr_in[ 4]) cmd_addr_timing_check(11); + always @(addr_in[ 5]) cmd_addr_timing_check(12); + always @(addr_in[ 6]) cmd_addr_timing_check(13); + always @(addr_in[ 7]) cmd_addr_timing_check(14); + always @(addr_in[ 8]) cmd_addr_timing_check(15); + always @(addr_in[ 9]) cmd_addr_timing_check(16); + always @(addr_in[10]) cmd_addr_timing_check(17); + always @(addr_in[11]) cmd_addr_timing_check(18); + always @(addr_in[12]) cmd_addr_timing_check(19); + always @(addr_in[13]) cmd_addr_timing_check(20); + always @(addr_in[14]) cmd_addr_timing_check(21); + always @(addr_in[15]) cmd_addr_timing_check(22); + + // Processes to check setup and hold of data signals + task dm_timing_check; + input i; + reg [3:0] i; + begin + if (dqs_in_valid) begin + if ($time - tm_dqs[i] < TDH) + $display ("%m: at time %t ERROR: tDH violation on DM bit %d by %t", $time, i, tm_dqs[i] + TDH - $time); + if (check_dm_tdipw[i]) begin + if ($time - tm_dm[i] < TDIPW) + $display ("%m: at time %t ERROR: tDIPW violation on DM bit %d by %t", $time, i, tm_dm[i] + TDIPW - $time); + end + end + check_dm_tdipw[i] <= 1'b0; + tm_dm[i] = $time; + end + endtask + + always @(dm_in[ 0]) dm_timing_check( 0); + always @(dm_in[ 1]) dm_timing_check( 1); + always @(dm_in[ 2]) dm_timing_check( 2); + always @(dm_in[ 3]) dm_timing_check( 3); + always @(dm_in[ 4]) dm_timing_check( 4); + always @(dm_in[ 5]) dm_timing_check( 5); + always @(dm_in[ 6]) dm_timing_check( 6); + always @(dm_in[ 7]) dm_timing_check( 7); + always @(dm_in[ 8]) dm_timing_check( 8); + always @(dm_in[ 9]) dm_timing_check( 9); + always @(dm_in[10]) dm_timing_check(10); + always @(dm_in[11]) dm_timing_check(11); + always @(dm_in[12]) dm_timing_check(12); + always @(dm_in[13]) dm_timing_check(13); + always @(dm_in[14]) dm_timing_check(14); + always @(dm_in[15]) dm_timing_check(15); + + task dq_timing_check; + input i; + reg [5:0] i; + begin + if (dqs_in_valid) begin + if ($time - tm_dqs[i/`DQ_PER_DQS] < TDH) + $display ("%m: at time %t ERROR: tDH violation on DQ bit %d by %t", $time, i, tm_dqs[i/`DQ_PER_DQS] + TDH - $time); + if (check_dq_tdipw[i]) begin + if ($time - tm_dq[i] < TDIPW) + $display ("%m: at time %t ERROR: tDIPW violation on DQ bit %d by %t", $time, i, tm_dq[i] + TDIPW - $time); + end + end + check_dq_tdipw[i] <= 1'b0; + tm_dq[i] = $time; + end + endtask + + always @(dq_in[ 0]) dq_timing_check( 0); + always @(dq_in[ 1]) dq_timing_check( 1); + always @(dq_in[ 2]) dq_timing_check( 2); + always @(dq_in[ 3]) dq_timing_check( 3); + always @(dq_in[ 4]) dq_timing_check( 4); + always @(dq_in[ 5]) dq_timing_check( 5); + always @(dq_in[ 6]) dq_timing_check( 6); + always @(dq_in[ 7]) dq_timing_check( 7); + always @(dq_in[ 8]) dq_timing_check( 8); + always @(dq_in[ 9]) dq_timing_check( 9); + always @(dq_in[10]) dq_timing_check(10); + always @(dq_in[11]) dq_timing_check(11); + always @(dq_in[12]) dq_timing_check(12); + always @(dq_in[13]) dq_timing_check(13); + always @(dq_in[14]) dq_timing_check(14); + always @(dq_in[15]) dq_timing_check(15); + always @(dq_in[16]) dq_timing_check(16); + always @(dq_in[17]) dq_timing_check(17); + always @(dq_in[18]) dq_timing_check(18); + always @(dq_in[19]) dq_timing_check(19); + always @(dq_in[20]) dq_timing_check(20); + always @(dq_in[21]) dq_timing_check(21); + always @(dq_in[22]) dq_timing_check(22); + always @(dq_in[23]) dq_timing_check(23); + always @(dq_in[24]) dq_timing_check(24); + always @(dq_in[25]) dq_timing_check(25); + always @(dq_in[26]) dq_timing_check(26); + always @(dq_in[27]) dq_timing_check(27); + always @(dq_in[28]) dq_timing_check(28); + always @(dq_in[29]) dq_timing_check(29); + always @(dq_in[30]) dq_timing_check(30); + always @(dq_in[31]) dq_timing_check(31); + always @(dq_in[32]) dq_timing_check(32); + always @(dq_in[33]) dq_timing_check(33); + always @(dq_in[34]) dq_timing_check(34); + always @(dq_in[35]) dq_timing_check(35); + always @(dq_in[36]) dq_timing_check(36); + always @(dq_in[37]) dq_timing_check(37); + always @(dq_in[38]) dq_timing_check(38); + always @(dq_in[39]) dq_timing_check(39); + always @(dq_in[40]) dq_timing_check(40); + always @(dq_in[41]) dq_timing_check(41); + always @(dq_in[42]) dq_timing_check(42); + always @(dq_in[43]) dq_timing_check(43); + always @(dq_in[44]) dq_timing_check(44); + always @(dq_in[45]) dq_timing_check(45); + always @(dq_in[46]) dq_timing_check(46); + always @(dq_in[47]) dq_timing_check(47); + always @(dq_in[48]) dq_timing_check(48); + always @(dq_in[49]) dq_timing_check(49); + always @(dq_in[50]) dq_timing_check(50); + always @(dq_in[51]) dq_timing_check(51); + always @(dq_in[52]) dq_timing_check(52); + always @(dq_in[53]) dq_timing_check(53); + always @(dq_in[54]) dq_timing_check(54); + always @(dq_in[55]) dq_timing_check(55); + always @(dq_in[56]) dq_timing_check(56); + always @(dq_in[57]) dq_timing_check(57); + always @(dq_in[58]) dq_timing_check(58); + always @(dq_in[59]) dq_timing_check(59); + always @(dq_in[60]) dq_timing_check(60); + always @(dq_in[61]) dq_timing_check(61); + always @(dq_in[62]) dq_timing_check(62); + always @(dq_in[63]) dq_timing_check(63); + + task dqs_pos_timing_check; + input i; + reg [4:0] i; + reg [3:0] j; + begin + if (write_levelization && i<16) begin + if (ck_cntr - ck_load_mode < TWLMRD) + $display ("%m: at time %t ERROR: tWLMRD violation on DQS bit %d positive edge.", $time, i); + if (($time - tm_ck_pos < TWLS) || ($time - tm_ck_neg < TWLS)) + $display ("%m: at time %t WARNING: tWLS violation on DQS bit %d positive edge. Indeterminate CK capture is possible.", $time, i); + if (DEBUG) + $display ("%m: at time %t Write Leveling @ DQS ck = %b", $time, diff_ck); + dq_out_en_dly[i*`DQ_PER_DQS] <= #(TWLO) 1'b1; + dq_out_dly[i*`DQ_PER_DQS] <= #(TWLO) diff_ck; + for (j=1; j<`DQ_PER_DQS; j=j+1) begin + dq_out_en_dly[i*`DQ_PER_DQS+j] <= #(TWLO + TWLOE) 1'b1; + dq_out_dly[i*`DQ_PER_DQS+j] <= #(TWLO + TWLOE) 1'b0; + end + end + if (dqs_in_valid && ((wdqs_pos_cntr[i] < wr_burst_length/2) || b2b_write)) begin + if (dqs_in[i] ^ prev_dqs_in[i]) begin + if (dll_locked) begin + if (check_write_preamble[i]) begin + if ($time - tm_dqs_pos[i] < $rtoi(TWPRE*tck_avg)) + $display ("%m: at time %t ERROR: tWPRE violation on &s bit %d", $time, dqs_string[i/16], i%16); + end else if (check_write_postamble[i]) begin + if ($time - tm_dqs_neg[i] < $rtoi(TWPST*tck_avg)) + $display ("%m: at time %t ERROR: tWPST violation on %s bit %d", $time, dqs_string[i/16], i%16); + end else begin + if ($time - tm_dqs_neg[i] < $rtoi(TDQSL*tck_avg)) + $display ("%m: at time %t ERROR: tDQSL violation on %s bit %d", $time, dqs_string[i/16], i%16); + end + end + if ($time - tm_dm[i%16] < TDS) + $display ("%m: at time %t ERROR: tDS violation on DM bit %d by %t", $time, i, tm_dm[i%16] + TDS - $time); + if (!dq_out_en) begin + for (j=0; j<`DQ_PER_DQS; j=j+1) begin + if ($time - tm_dq[(i%16)*`DQ_PER_DQS+j] < TDS) + $display ("%m: at time %t ERROR: tDS violation on DQ bit %d by %t", $time, i*`DQ_PER_DQS+j, tm_dq[(i%16)*`DQ_PER_DQS+j] + TDS - $time); + check_dq_tdipw[(i%16)*`DQ_PER_DQS+j] <= 1'b1; + end + end + if ((wdqs_pos_cntr[i] < wr_burst_length/2) && !b2b_write) begin + wdqs_pos_cntr[i] <= wdqs_pos_cntr[i] + 1; + end else begin + wdqs_pos_cntr[i] <= 1; + end + check_dm_tdipw[i%16] <= 1'b1; + check_write_preamble[i] <= 1'b0; + check_write_postamble[i] <= 1'b0; + check_write_dqs_low[i] <= 1'b0; + tm_dqs[i%16] <= $time; + end else begin + $display ("%m: at time %t ERROR: Invalid latching edge on %s bit %d", $time, dqs_string[i/16], i%16); + end + end + tm_dqss_pos[i] <= $time; + tm_dqs_pos[i] = $time; + prev_dqs_in[i] <= dqs_in[i]; + end + endtask + + always @(posedge dqs_in[ 0]) dqs_pos_timing_check( 0); + always @(posedge dqs_in[ 1]) dqs_pos_timing_check( 1); + always @(posedge dqs_in[ 2]) dqs_pos_timing_check( 2); + always @(posedge dqs_in[ 3]) dqs_pos_timing_check( 3); + always @(posedge dqs_in[ 4]) dqs_pos_timing_check( 4); + always @(posedge dqs_in[ 5]) dqs_pos_timing_check( 5); + always @(posedge dqs_in[ 6]) dqs_pos_timing_check( 6); + always @(posedge dqs_in[ 7]) dqs_pos_timing_check( 7); + always @(posedge dqs_in[ 8]) dqs_pos_timing_check( 8); + always @(posedge dqs_in[ 9]) dqs_pos_timing_check( 9); + always @(posedge dqs_in[10]) dqs_pos_timing_check(10); + always @(posedge dqs_in[11]) dqs_pos_timing_check(11); + always @(posedge dqs_in[12]) dqs_pos_timing_check(12); + always @(posedge dqs_in[13]) dqs_pos_timing_check(13); + always @(posedge dqs_in[14]) dqs_pos_timing_check(14); + always @(posedge dqs_in[15]) dqs_pos_timing_check(15); + always @(negedge dqs_in[16]) dqs_pos_timing_check(16); + always @(negedge dqs_in[17]) dqs_pos_timing_check(17); + always @(negedge dqs_in[18]) dqs_pos_timing_check(18); + always @(negedge dqs_in[19]) dqs_pos_timing_check(19); + always @(negedge dqs_in[20]) dqs_pos_timing_check(20); + always @(negedge dqs_in[21]) dqs_pos_timing_check(21); + always @(negedge dqs_in[22]) dqs_pos_timing_check(22); + always @(negedge dqs_in[23]) dqs_pos_timing_check(23); + always @(negedge dqs_in[24]) dqs_pos_timing_check(24); + always @(negedge dqs_in[25]) dqs_pos_timing_check(25); + always @(negedge dqs_in[26]) dqs_pos_timing_check(26); + always @(negedge dqs_in[27]) dqs_pos_timing_check(27); + always @(negedge dqs_in[28]) dqs_pos_timing_check(28); + always @(negedge dqs_in[29]) dqs_pos_timing_check(29); + always @(negedge dqs_in[30]) dqs_pos_timing_check(30); + always @(negedge dqs_in[31]) dqs_pos_timing_check(31); + + task dqs_neg_timing_check; + input i; + reg [4:0] i; + reg [3:0] j; + begin + if (write_levelization && i<16) begin + if (ck_cntr - ck_load_mode < TWLDQSEN) + $display ("%m: at time %t ERROR: tWLDQSEN violation on DQS bit %d.", $time, i); + if ($time - tm_dqs_pos[i] < $rtoi(TDQSH*tck_avg)) + $display ("%m: at time %t ERROR: tDQSH violation on DQS bit %d by %t", $time, i, tm_dqs_pos[i] + TDQSH*tck_avg - $time); + end + if (dqs_in_valid && (wdqs_pos_cntr[i] > 0) && check_write_dqs_high[i]) begin + if (dqs_in[i] ^ prev_dqs_in[i]) begin + if (dll_locked) begin + if ($time - tm_dqs_pos[i] < $rtoi(TDQSH*tck_avg)) + $display ("%m: at time %t ERROR: tDQSH violation on %s bit %d", $time, dqs_string[i/16], i%16); + if ($time - tm_ck_pos < $rtoi(TDSH*tck_avg)) + $display ("%m: at time %t ERROR: tDSH violation on %s bit %d", $time, dqs_string[i/16], i%16); + end + if ($time - tm_dm[i%16] < TDS) + $display ("%m: at time %t ERROR: tDS violation on DM bit %d by %t", $time, i, tm_dm[i%16] + TDS - $time); + if (!dq_out_en) begin + for (j=0; j<`DQ_PER_DQS; j=j+1) begin + if ($time - tm_dq[(i%16)*`DQ_PER_DQS+j] < TDS) + $display ("%m: at time %t ERROR: tDS violation on DQ bit %d by %t", $time, i*`DQ_PER_DQS+j, tm_dq[(i%16)*`DQ_PER_DQS+j] + TDS - $time); + check_dq_tdipw[(i%16)*`DQ_PER_DQS+j] <= 1'b1; + end + end + check_dm_tdipw[i%16] <= 1'b1; + tm_dqs[i%16] <= $time; + end else begin + $display ("%m: at time %t ERROR: Invalid latching edge on %s bit %d", $time, dqs_string[i/16], i%16); + end + end + check_write_dqs_high[i] <= 1'b0; + tm_dqs_neg[i] = $time; + prev_dqs_in[i] <= dqs_in[i]; + end + endtask + + always @(negedge dqs_in[ 0]) dqs_neg_timing_check( 0); + always @(negedge dqs_in[ 1]) dqs_neg_timing_check( 1); + always @(negedge dqs_in[ 2]) dqs_neg_timing_check( 2); + always @(negedge dqs_in[ 3]) dqs_neg_timing_check( 3); + always @(negedge dqs_in[ 4]) dqs_neg_timing_check( 4); + always @(negedge dqs_in[ 5]) dqs_neg_timing_check( 5); + always @(negedge dqs_in[ 6]) dqs_neg_timing_check( 6); + always @(negedge dqs_in[ 7]) dqs_neg_timing_check( 7); + always @(negedge dqs_in[ 8]) dqs_neg_timing_check( 8); + always @(negedge dqs_in[ 9]) dqs_neg_timing_check( 9); + always @(negedge dqs_in[10]) dqs_neg_timing_check(10); + always @(negedge dqs_in[11]) dqs_neg_timing_check(11); + always @(negedge dqs_in[12]) dqs_neg_timing_check(12); + always @(negedge dqs_in[13]) dqs_neg_timing_check(13); + always @(negedge dqs_in[14]) dqs_neg_timing_check(14); + always @(negedge dqs_in[15]) dqs_neg_timing_check(15); + always @(posedge dqs_in[16]) dqs_neg_timing_check(16); + always @(posedge dqs_in[17]) dqs_neg_timing_check(17); + always @(posedge dqs_in[18]) dqs_neg_timing_check(18); + always @(posedge dqs_in[19]) dqs_neg_timing_check(19); + always @(posedge dqs_in[20]) dqs_neg_timing_check(20); + always @(posedge dqs_in[21]) dqs_neg_timing_check(21); + always @(posedge dqs_in[22]) dqs_neg_timing_check(22); + always @(posedge dqs_in[23]) dqs_neg_timing_check(23); + always @(posedge dqs_in[24]) dqs_neg_timing_check(24); + always @(posedge dqs_in[25]) dqs_neg_timing_check(25); + always @(posedge dqs_in[26]) dqs_neg_timing_check(26); + always @(posedge dqs_in[27]) dqs_neg_timing_check(27); + always @(posedge dqs_in[28]) dqs_neg_timing_check(28); + always @(posedge dqs_in[29]) dqs_neg_timing_check(29); + always @(posedge dqs_in[30]) dqs_neg_timing_check(30); + always @(posedge dqs_in[31]) dqs_neg_timing_check(31); + +endmodule diff --git "a/Frogwells_fpga_design/\345\237\272\344\272\216FPGA\343\200\201DDR3\345\222\214USB2.0\347\232\204\345\233\276\345\203\217\351\207\207\351\233\206\347\263\273\347\273\237/debug/ddr_test/sim/functional/ddr3_model_parameters_c3.vh" "b/Frogwells_fpga_design/\345\237\272\344\272\216FPGA\343\200\201DDR3\345\222\214USB2.0\347\232\204\345\233\276\345\203\217\351\207\207\351\233\206\347\263\273\347\273\237/debug/ddr_test/sim/functional/ddr3_model_parameters_c3.vh" new file mode 100644 index 0000000000000000000000000000000000000000..4b66341cd1cbe0a5e2f143cfa49c2d650d15486f --- /dev/null +++ "b/Frogwells_fpga_design/\345\237\272\344\272\216FPGA\343\200\201DDR3\345\222\214USB2.0\347\232\204\345\233\276\345\203\217\351\207\207\351\233\206\347\263\273\347\273\237/debug/ddr_test/sim/functional/ddr3_model_parameters_c3.vh" @@ -0,0 +1,1944 @@ +/**************************************************************************************** +* +* Disclaimer This software code and all associated documentation, comments or other +* of Warranty: information (collectively "Software") is provided "AS IS" without +* warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY +* DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED +* TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES +* OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT +* WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE +* OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE. +* FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR +* THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS, +* ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE +* OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI, +* ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT, +* INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING, +* WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, +* OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE +* THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH +* DAMAGES. Because some jurisdictions prohibit the exclusion or +* limitation of liability for consequential or incidental damages, the +* above limitation may not apply to you. +* +* Copyright 2003 Micron Technology, Inc. All rights reserved. +* +****************************************************************************************/ + + // Parameters current with 1Gb and 2Gb datasheet rev D + + // Timing parameters based on Speed Grade + + +`ifdef x2Gb // 2Gb parameters + + // SYMBOL UNITS DESCRIPTION + // ------ ----- ----------- + `ifdef sg093 // sg093 is equivalent to the JEDEC DDR3-2133 (14-14-14) speed bin + parameter TCK_MIN = 935; // tCK ps Minimum Clock Cycle Time + parameter TJIT_PER = 50; // tJIT(per) ps Period JItter + parameter TJIT_CC = 100; // tJIT(cc) ps Cycle to Cycle jitter + parameter TERR_2PER = 74; // tERR(2per) ps Accumulated Error (2-cycle) + parameter TERR_3PER = 87; // tERR(3per) ps Accumulated Error (3-cycle) + parameter TERR_4PER = 97; // tERR(4per) ps Accumulated Error (4-cycle) + parameter TERR_5PER = 105; // tERR(5per) ps Accumulated Error (5-cycle) + parameter TERR_6PER = 111; // tERR(6per) ps Accumulated Error (6-cycle) + parameter TERR_7PER = 116; // tERR(7per) ps Accumulated Error (7-cycle) + parameter TERR_8PER = 121; // tERR(8per) ps Accumulated Error (8-cycle) + parameter TERR_9PER = 125; // tERR(9per) ps Accumulated Error (9-cycle) + parameter TERR_10PER = 128; // tERR(10per)ps Accumulated Error (10-cycle) + parameter TERR_11PER = 132; // tERR(11per)ps Accumulated Error (11-cycle) + parameter TERR_12PER = 134; // tERR(12per)ps Accumulated Error (12-cycle) + parameter TDS = 5; // tDS ps DQ and DM input setup time relative to DQS + parameter TDH = 20; // tDH ps DQ and DM input hold time relative to DQS + parameter TDQSQ = 70; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access + parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition + parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) + parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) + parameter TDQSCK = 180; // tDQSCK ps DQS output access time from CK/CK# + parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width + parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width + parameter TDIPW = 280; // tDIPW ps DQ and DM input Pulse Width + parameter TIPW = 470; // tIPW ps Control and Address input Pulse Width + parameter TIS = 35; // tIS ps Input Setup Time + parameter TIH = 75; // tIH ps Input Hold Time + parameter TRAS_MIN = 33000; // tRAS ps Minimum Active to Precharge command time + parameter TRC = 48090; // tRC ps Active to Active/Auto Refresh command time + parameter TRCD = 13090; // tRCD ps Active to Read/Write command time + parameter TRP = 13090; // tRP ps Precharge command period + parameter TXP = 6000; // tXP ps Exit power down to a valid command + parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width + parameter TAON = 180; // tAON ps RTT turn-on from ODTLon reference + parameter TWLS = 122; // tWLS ps Setup time for tDQS flop + parameter TWLH = 122; // tWLH ps Hold time of tDQS flop + parameter TWLO = 7500; // tWLO ps Write levelization output delay + parameter TAA_MIN = 13090; // TAA ps Internal READ command to first data + parameter CL_TIME = 13090; // CL ps Minimum CAS Latency + `elsif sg093E // sg093E is equivalent to the JEDEC DDR3-2133 (13-13-13) speed bin + parameter TCK_MIN = 935; // tCK ps Minimum Clock Cycle Time + parameter TJIT_PER = 50; // tJIT(per) ps Period JItter + parameter TJIT_CC = 100; // tJIT(cc) ps Cycle to Cycle jitter + parameter TERR_2PER = 74; // tERR(2per) ps Accumulated Error (2-cycle) + parameter TERR_3PER = 87; // tERR(3per) ps Accumulated Error (3-cycle) + parameter TERR_4PER = 97; // tERR(4per) ps Accumulated Error (4-cycle) + parameter TERR_5PER = 105; // tERR(5per) ps Accumulated Error (5-cycle) + parameter TERR_6PER = 111; // tERR(6per) ps Accumulated Error (6-cycle) + parameter TERR_7PER = 116; // tERR(7per) ps Accumulated Error (7-cycle) + parameter TERR_8PER = 121; // tERR(8per) ps Accumulated Error (8-cycle) + parameter TERR_9PER = 125; // tERR(9per) ps Accumulated Error (9-cycle) + parameter TERR_10PER = 128; // tERR(10per)ps Accumulated Error (10-cycle) + parameter TERR_11PER = 132; // tERR(11per)ps Accumulated Error (11-cycle) + parameter TERR_12PER = 134; // tERR(12per)ps Accumulated Error (12-cycle) + parameter TDS = 5; // tDS ps DQ and DM input setup time relative to DQS + parameter TDH = 20; // tDH ps DQ and DM input hold time relative to DQS + parameter TDQSQ = 70; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access + parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition + parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) + parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) + parameter TDQSCK = 175; // tDQSCK ps DQS output access time from CK/CK# + parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width + parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width + parameter TDIPW = 280; // tDIPW ps DQ and DM input Pulse Width + parameter TIPW = 470; // tIPW ps Control and Address input Pulse Width + parameter TIS = 35; // tIS ps Input Setup Time + parameter TIH = 75; // tIH ps Input Hold Time + parameter TRAS_MIN = 33000; // tRAS ps Minimum Active to Precharge command time + parameter TRC = 47155; // tRC ps Active to Active/Auto Refresh command time + parameter TRCD = 12155; // tRCD ps Active to Read/Write command time + parameter TRP = 12155; // tRP ps Precharge command period + parameter TXP = 6000; // tXP ps Exit power down to a valid command + parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width + parameter TAON = 180; // tAON ps RTT turn-on from ODTLon reference + parameter TWLS = 122; // tWLS ps Setup time for tDQS flop + parameter TWLH = 122; // tWLH ps Hold time of tDQS flop + parameter TWLO = 7500; // tWLO ps Write levelization output delay + parameter TAA_MIN = 12155; // TAA ps Internal READ command to first data + parameter CL_TIME = 12155; // CL ps Minimum CAS Latency + `elsif sg093F // sg093F is equivalent to the JEDEC DDR3-2133 (12-12-12) speed bin + parameter TCK_MIN = 935; // tCK ps Minimum Clock Cycle Time + parameter TJIT_PER = 50; // tJIT(per) ps Period JItter + parameter TJIT_CC = 100; // tJIT(cc) ps Cycle to Cycle jitter + parameter TERR_2PER = 74; // tERR(2per) ps Accumulated Error (2-cycle) + parameter TERR_3PER = 87; // tERR(3per) ps Accumulated Error (3-cycle) + parameter TERR_4PER = 97; // tERR(4per) ps Accumulated Error (4-cycle) + parameter TERR_5PER = 105; // tERR(5per) ps Accumulated Error (5-cycle) + parameter TERR_6PER = 111; // tERR(6per) ps Accumulated Error (6-cycle) + parameter TERR_7PER = 116; // tERR(7per) ps Accumulated Error (7-cycle) + parameter TERR_8PER = 121; // tERR(8per) ps Accumulated Error (8-cycle) + parameter TERR_9PER = 125; // tERR(9per) ps Accumulated Error (9-cycle) + parameter TERR_10PER = 128; // tERR(10per)ps Accumulated Error (10-cycle) + parameter TERR_11PER = 132; // tERR(11per)ps Accumulated Error (11-cycle) + parameter TERR_12PER = 134; // tERR(12per)ps Accumulated Error (12-cycle) + parameter TDS = 5; // tDS ps DQ and DM input setup time relative to DQS + parameter TDH = 20; // tDH ps DQ and DM input hold time relative to DQS + parameter TDQSQ = 70; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access + parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition + parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) + parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) + parameter TDQSCK = 175; // tDQSCK ps DQS output access time from CK/CK# + parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width + parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width + parameter TDIPW = 280; // tDIPW ps DQ and DM input Pulse Width + parameter TIPW = 470; // tIPW ps Control and Address input Pulse Width + parameter TIS = 35; // tIS ps Input Setup Time + parameter TIH = 75; // tIH ps Input Hold Time + parameter TRAS_MIN = 33000; // tRAS ps Minimum Active to Precharge command time + parameter TRC = 46220; // tRC ps Active to Active/Auto Refresh command time + parameter TRCD = 11220; // tRCD ps Active to Read/Write command time + parameter TRP = 11220; // tRP ps Precharge command period + parameter TXP = 6000; // tXP ps Exit power down to a valid command + parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width + parameter TAON = 180; // tAON ps RTT turn-on from ODTLon reference + parameter TWLS = 122; // tWLS ps Setup time for tDQS flop + parameter TWLH = 122; // tWLH ps Hold time of tDQS flop + parameter TWLO = 7500; // tWLO ps Write levelization output delay + parameter TAA_MIN = 11220; // TAA ps Internal READ command to first data + parameter CL_TIME = 11220; // CL ps Minimum CAS Latency + `elsif sg107 // sg107 is equivalent to the JEDEC DDR3-1866 (13-13-13) speed bin + parameter TCK_MIN = 1070; // tCK ps Minimum Clock Cycle Time + parameter TJIT_PER = 60; // tJIT(per) ps Period JItter + parameter TJIT_CC = 120; // tJIT(cc) ps Cycle to Cycle jitter + parameter TERR_2PER = 88; // tERR(2per) ps Accumulated Error (2-cycle) + parameter TERR_3PER = 105; // tERR(3per) ps Accumulated Error (3-cycle) + parameter TERR_4PER = 117; // tERR(4per) ps Accumulated Error (4-cycle) + parameter TERR_5PER = 126; // tERR(5per) ps Accumulated Error (5-cycle) + parameter TERR_6PER = 133; // tERR(6per) ps Accumulated Error (6-cycle) + parameter TERR_7PER = 139; // tERR(7per) ps Accumulated Error (7-cycle) + parameter TERR_8PER = 145; // tERR(8per) ps Accumulated Error (8-cycle) + parameter TERR_9PER = 150; // tERR(9per) ps Accumulated Error (9-cycle) + parameter TERR_10PER = 154; // tERR(10per)ps Accumulated Error (10-cycle) + parameter TERR_11PER = 158; // tERR(11per)ps Accumulated Error (11-cycle) + parameter TERR_12PER = 161; // tERR(12per)ps Accumulated Error (12-cycle) + parameter TDS = 10; // tDS ps DQ and DM input setup time relative to DQS + parameter TDH = 20; // tDH ps DQ and DM input hold time relative to DQS + parameter TDQSQ = 80; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access + parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition + parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) + parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) + parameter TDQSCK = 200; // tDQSCK ps DQS output access time from CK/CK# + parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width + parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width + parameter TDIPW = 320; // tDIPW ps DQ and DM input Pulse Width + parameter TIPW = 535; // tIPW ps Control and Address input Pulse Width + parameter TIS = 50; // tIS ps Input Setup Time + parameter TIH = 100; // tIH ps Input Hold Time + parameter TRAS_MIN = 34000; // tRAS ps Minimum Active to Precharge command time + parameter TRC = 48910; // tRC ps Active to Active/Auto Refresh command time + parameter TRCD = 13910; // tRCD ps Active to Read/Write command time + parameter TRP = 13910; // tRP ps Precharge command period + parameter TXP = 6000; // tXP ps Exit power down to a valid command + parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width + parameter TAON = 200; // tAON ps RTT turn-on from ODTLon reference + parameter TWLS = 140; // tWLS ps Setup time for tDQS flop + parameter TWLH = 140; // tWLH ps Hold time of tDQS flop + parameter TWLO = 7500; // tWLO ps Write levelization output delay + parameter TAA_MIN = 13910; // TAA ps Internal READ command to first data + parameter CL_TIME = 13910; // CL ps Minimum CAS Latency + `elsif sg107E // sg107E is equivalent to the JEDEC DDR3-1866 (12-12-12) speed bin + parameter TCK_MIN = 1070; // tCK ps Minimum Clock Cycle Time + parameter TJIT_PER = 60; // tJIT(per) ps Period JItter + parameter TJIT_CC = 120; // tJIT(cc) ps Cycle to Cycle jitter + parameter TERR_2PER = 88; // tERR(2per) ps Accumulated Error (2-cycle) + parameter TERR_3PER = 105; // tERR(3per) ps Accumulated Error (3-cycle) + parameter TERR_4PER = 117; // tERR(4per) ps Accumulated Error (4-cycle) + parameter TERR_5PER = 126; // tERR(5per) ps Accumulated Error (5-cycle) + parameter TERR_6PER = 133; // tERR(6per) ps Accumulated Error (6-cycle) + parameter TERR_7PER = 139; // tERR(7per) ps Accumulated Error (7-cycle) + parameter TERR_8PER = 145; // tERR(8per) ps Accumulated Error (8-cycle) + parameter TERR_9PER = 150; // tERR(9per) ps Accumulated Error (9-cycle) + parameter TERR_10PER = 154; // tERR(10per)ps Accumulated Error (10-cycle) + parameter TERR_11PER = 158; // tERR(11per)ps Accumulated Error (11-cycle) + parameter TERR_12PER = 161; // tERR(12per)ps Accumulated Error (12-cycle) + parameter TDS = 10; // tDS ps DQ and DM input setup time relative to DQS + parameter TDH = 20; // tDH ps DQ and DM input hold time relative to DQS + parameter TDQSQ = 80; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access + parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition + parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) + parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) + parameter TDQSCK = 200; // tDQSCK ps DQS output access time from CK/CK# + parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width + parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width + parameter TDIPW = 320; // tDIPW ps DQ and DM input Pulse Width + parameter TIPW = 535; // tIPW ps Control and Address input Pulse Width + parameter TIS = 50; // tIS ps Input Setup Time + parameter TIH = 100; // tIH ps Input Hold Time + parameter TRAS_MIN = 34000; // tRAS ps Minimum Active to Precharge command time + parameter TRC = 47840; // tRC ps Active to Active/Auto Refresh command time + parameter TRCD = 12840; // tRCD ps Active to Read/Write command time + parameter TRP = 12840; // tRP ps Precharge command period + parameter TXP = 6000; // tXP ps Exit power down to a valid command + parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width + parameter TAON = 200; // tAON ps RTT turn-on from ODTLon reference + parameter TWLS = 140; // tWLS ps Setup time for tDQS flop + parameter TWLH = 140; // tWLH ps Hold time of tDQS flop + parameter TWLO = 7500; // tWLO ps Write levelization output delay + parameter TAA_MIN = 12840; // TAA ps Internal READ command to first data + parameter CL_TIME = 12840; // CL ps Minimum CAS Latency + `elsif sg107F // sg107F is equivalent to the JEDEC DDR3-1866 (11-11-11) speed bin + parameter TCK_MIN = 1070; // tCK ps Minimum Clock Cycle Time + parameter TJIT_PER = 60; // tJIT(per) ps Period JItter + parameter TJIT_CC = 120; // tJIT(cc) ps Cycle to Cycle jitter + parameter TERR_2PER = 88; // tERR(2per) ps Accumulated Error (2-cycle) + parameter TERR_3PER = 105; // tERR(3per) ps Accumulated Error (3-cycle) + parameter TERR_4PER = 117; // tERR(4per) ps Accumulated Error (4-cycle) + parameter TERR_5PER = 126; // tERR(5per) ps Accumulated Error (5-cycle) + parameter TERR_6PER = 133; // tERR(6per) ps Accumulated Error (6-cycle) + parameter TERR_7PER = 139; // tERR(7per) ps Accumulated Error (7-cycle) + parameter TERR_8PER = 145; // tERR(8per) ps Accumulated Error (8-cycle) + parameter TERR_9PER = 150; // tERR(9per) ps Accumulated Error (9-cycle) + parameter TERR_10PER = 154; // tERR(10per)ps Accumulated Error (10-cycle) + parameter TERR_11PER = 158; // tERR(11per)ps Accumulated Error (11-cycle) + parameter TERR_12PER = 161; // tERR(12per)ps Accumulated Error (12-cycle) + parameter TDS = 10; // tDS ps DQ and DM input setup time relative to DQS + parameter TDH = 20; // tDH ps DQ and DM input hold time relative to DQS + parameter TDQSQ = 80; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access + parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition + parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) + parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) + parameter TDQSCK = 200; // tDQSCK ps DQS output access time from CK/CK# + parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width + parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width + parameter TDIPW = 320; // tDIPW ps DQ and DM input Pulse Width + parameter TIPW = 535; // tIPW ps Control and Address input Pulse Width + parameter TIS = 50; // tIS ps Input Setup Time + parameter TIH = 100; // tIH ps Input Hold Time + parameter TRAS_MIN = 34000; // tRAS ps Minimum Active to Precharge command time + parameter TRC = 46770; // tRC ps Active to Active/Auto Refresh command time + parameter TRCD = 11770; // tRCD ps Active to Read/Write command time + parameter TRP = 11770; // tRP ps Precharge command period + parameter TXP = 6000; // tXP ps Exit power down to a valid command + parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width + parameter TAON = 200; // tAON ps RTT turn-on from ODTLon reference + parameter TWLS = 140; // tWLS ps Setup time for tDQS flop + parameter TWLH = 140; // tWLH ps Hold time of tDQS flop + parameter TWLO = 7500; // tWLO ps Write levelization output delay + parameter TAA_MIN = 11770; // TAA ps Internal READ command to first data + parameter CL_TIME = 11770; // CL ps Minimum CAS Latency + `elsif sg125E // sg125E is equivalent to the JEDEC DDR3-1600 (10-10-10) speed bin + parameter TCK_MIN = 1250; // tCK ps Minimum Clock Cycle Time + parameter TJIT_PER = 70; // tJIT(per) ps Period JItter + parameter TJIT_CC = 140; // tJIT(cc) ps Cycle to Cycle jitter + parameter TERR_2PER = 103; // tERR(2per) ps Accumulated Error (2-cycle) + parameter TERR_3PER = 122; // tERR(3per) ps Accumulated Error (3-cycle) + parameter TERR_4PER = 136; // tERR(4per) ps Accumulated Error (4-cycle) + parameter TERR_5PER = 147; // tERR(5per) ps Accumulated Error (5-cycle) + parameter TERR_6PER = 155; // tERR(6per) ps Accumulated Error (6-cycle) + parameter TERR_7PER = 163; // tERR(7per) ps Accumulated Error (7-cycle) + parameter TERR_8PER = 169; // tERR(8per) ps Accumulated Error (8-cycle) + parameter TERR_9PER = 175; // tERR(9per) ps Accumulated Error (9-cycle) + parameter TERR_10PER = 180; // tERR(10per)ps Accumulated Error (10-cycle) + parameter TERR_11PER = 184; // tERR(11per)ps Accumulated Error (11-cycle) + parameter TERR_12PER = 188; // tERR(12per)ps Accumulated Error (12-cycle) + parameter TDS = 10; // tDS ps DQ and DM input setup time relative to DQS + parameter TDH = 45; // tDH ps DQ and DM input hold time relative to DQS + parameter TDQSQ = 100; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access + parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition + parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) + parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) + parameter TDQSCK = 225; // tDQSCK ps DQS output access time from CK/CK# + parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width + parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width + parameter TDIPW = 360; // tDIPW ps DQ and DM input Pulse Width + parameter TIPW = 560; // tIPW ps Control and Address input Pulse Width + parameter TIS = 170; // tIS ps Input Setup Time + parameter TIH = 120; // tIH ps Input Hold Time + parameter TRAS_MIN = 35000; // tRAS ps Minimum Active to Precharge command time + parameter TRC = 47500; // tRC ps Active to Active/Auto Refresh command time + parameter TRCD = 12500; // tRCD ps Active to Read/Write command time + parameter TRP = 12500; // tRP ps Precharge command period + parameter TXP = 6000; // tXP ps Exit power down to a valid command + parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width + parameter TAON = 250; // tAON ps RTT turn-on from ODTLon reference + parameter TWLS = 165; // tWLS ps Setup time for tDQS flop + parameter TWLH = 165; // tWLH ps Hold time of tDQS flop + parameter TWLO = 7500; // tWLO ps Write levelization output delay + parameter TAA_MIN = 12500; // TAA ps Internal READ command to first data + parameter CL_TIME = 12500; // CL ps Minimum CAS Latency + `elsif sg125 // sg125 is equivalent to the JEDEC DDR3-1600 (11-11-11) speed bin + parameter TCK_MIN = 1250; // tCK ps Minimum Clock Cycle Time + parameter TJIT_PER = 70; // tJIT(per) ps Period JItter + parameter TJIT_CC = 140; // tJIT(cc) ps Cycle to Cycle jitter + parameter TERR_2PER = 103; // tERR(2per) ps Accumulated Error (2-cycle) + parameter TERR_3PER = 122; // tERR(3per) ps Accumulated Error (3-cycle) + parameter TERR_4PER = 136; // tERR(4per) ps Accumulated Error (4-cycle) + parameter TERR_5PER = 147; // tERR(5per) ps Accumulated Error (5-cycle) + parameter TERR_6PER = 155; // tERR(6per) ps Accumulated Error (6-cycle) + parameter TERR_7PER = 163; // tERR(7per) ps Accumulated Error (7-cycle) + parameter TERR_8PER = 169; // tERR(8per) ps Accumulated Error (8-cycle) + parameter TERR_9PER = 175; // tERR(9per) ps Accumulated Error (9-cycle) + parameter TERR_10PER = 180; // tERR(10per)ps Accumulated Error (10-cycle) + parameter TERR_11PER = 184; // tERR(11per)ps Accumulated Error (11-cycle) + parameter TERR_12PER = 188; // tERR(12per)ps Accumulated Error (12-cycle) + parameter TDS = 10; // tDS ps DQ and DM input setup time relative to DQS + parameter TDH = 45; // tDH ps DQ and DM input hold time relative to DQS + parameter TDQSQ = 100; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access + parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition + parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) + parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) + parameter TDQSCK = 225; // tDQSCK ps DQS output access time from CK/CK# + parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width + parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width + parameter TDIPW = 360; // tDIPW ps DQ and DM input Pulse Width + parameter TIPW = 560; // tIPW ps Control and Address input Pulse Width + parameter TIS = 170; // tIS ps Input Setup Time + parameter TIH = 120; // tIH ps Input Hold Time + parameter TRAS_MIN = 35000; // tRAS ps Minimum Active to Precharge command time + parameter TRC = 48750; // tRC ps Active to Active/Auto Refresh command time + parameter TRCD = 13750; // tRCD ps Active to Read/Write command time + parameter TRP = 13750; // tRP ps Precharge command period + parameter TXP = 6000; // tXP ps Exit power down to a valid command + parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width + parameter TAON = 250; // tAON ps RTT turn-on from ODTLon reference + parameter TWLS = 165; // tWLS ps Setup time for tDQS flop + parameter TWLH = 165; // tWLH ps Hold time of tDQS flop + parameter TWLO = 7500; // tWLO ps Write levelization output delay + parameter TAA_MIN = 13750; // TAA ps Internal READ command to first data + parameter CL_TIME = 13750; // CL ps Minimum CAS Latency + `elsif sg15E // sg15E is equivalent to the JEDEC DDR3-1333H (9-9-9) speed bin + parameter TCK_MIN = 1500; // tCK ps Minimum Clock Cycle Time + parameter TJIT_PER = 80; // tJIT(per) ps Period JItter + parameter TJIT_CC = 160; // tJIT(cc) ps Cycle to Cycle jitter + parameter TERR_2PER = 118; // tERR(2per) ps Accumulated Error (2-cycle) + parameter TERR_3PER = 140; // tERR(3per) ps Accumulated Error (3-cycle) + parameter TERR_4PER = 155; // tERR(4per) ps Accumulated Error (4-cycle) + parameter TERR_5PER = 168; // tERR(5per) ps Accumulated Error (5-cycle) + parameter TERR_6PER = 177; // tERR(6per) ps Accumulated Error (6-cycle) + parameter TERR_7PER = 186; // tERR(7per) ps Accumulated Error (7-cycle) + parameter TERR_8PER = 193; // tERR(8per) ps Accumulated Error (8-cycle) + parameter TERR_9PER = 200; // tERR(9per) ps Accumulated Error (9-cycle) + parameter TERR_10PER = 205; // tERR(10per)ps Accumulated Error (10-cycle) + parameter TERR_11PER = 210; // tERR(11per)ps Accumulated Error (11-cycle) + parameter TERR_12PER = 215; // tERR(12per)ps Accumulated Error (12-cycle) + parameter TDS = 30; // tDS ps DQ and DM input setup time relative to DQS + parameter TDH = 65; // tDH ps DQ and DM input hold time relative to DQS + parameter TDQSQ = 125; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access + parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition + parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time) + parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time) + parameter TDQSCK = 255; // tDQSCK ps DQS output access time from CK/CK# + parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width + parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width + parameter TDIPW = 400; // tDIPW ps DQ and DM input Pulse Width + parameter TIPW = 620; // tIPW ps Control and Address input Pulse Width + parameter TIS = 190; // tIS ps Input Setup Time + parameter TIH = 140; // tIH ps Input Hold Time + parameter TRAS_MIN = 36000; // tRAS ps Minimum Active to Precharge command time + parameter TRC = 49500; // tRC ps Active to Active/Auto Refresh command time + parameter TRCD = 13500; // tRCD ps Active to Read/Write command time + parameter TRP = 13500; // tRP ps Precharge command period + parameter TXP = 6000; // tXP ps Exit power down to a valid command + parameter TCKE = 5625; // tCKE ps CKE minimum high or low pulse width + parameter TAON = 250; // tAON ps RTT turn-on from ODTLon reference + parameter TWLS = 195; // tWLS ps Setup time for tDQS flop + parameter TWLH = 195; // tWLH ps Hold time of tDQS flop + parameter TWLO = 9000; // tWLO ps Write levelization output delay + parameter TAA_MIN = 13500; // TAA ps Internal READ command to first data + parameter CL_TIME = 13500; // CL ps Minimum CAS Latency + `elsif sg15 // sg15 is equivalent to the JEDEC DDR3-1333J (10-10-10) speed bin + parameter TCK_MIN = 1500; // tCK ps Minimum Clock Cycle Time + parameter TJIT_PER = 80; // tJIT(per) ps Period JItter + parameter TJIT_CC = 160; // tJIT(cc) ps Cycle to Cycle jitter + parameter TERR_2PER = 118; // tERR(2per) ps Accumulated Error (2-cycle) + parameter TERR_3PER = 140; // tERR(3per) ps Accumulated Error (3-cycle) + parameter TERR_4PER = 155; // tERR(4per) ps Accumulated Error (4-cycle) + parameter TERR_5PER = 168; // tERR(5per) ps Accumulated Error (5-cycle) + parameter TERR_6PER = 177; // tERR(6per) ps Accumulated Error (6-cycle) + parameter TERR_7PER = 186; // tERR(7per) ps Accumulated Error (7-cycle) + parameter TERR_8PER = 193; // tERR(8per) ps Accumulated Error (8-cycle) + parameter TERR_9PER = 200; // tERR(9per) ps Accumulated Error (9-cycle) + parameter TERR_10PER = 205; // tERR(10per)ps Accumulated Error (10-cycle) + parameter TERR_11PER = 210; // tERR(11per)ps Accumulated Error (11-cycle) + parameter TERR_12PER = 215; // tERR(12per)ps Accumulated Error (12-cycle) + parameter TDS = 30; // tDS ps DQ and DM input setup time relative to DQS + parameter TDH = 65; // tDH ps DQ and DM input hold time relative to DQS + parameter TDQSQ = 125; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access + parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition + parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time) + parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time) + parameter TDQSCK = 255; // tDQSCK ps DQS output access time from CK/CK# + parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width + parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width + parameter TDIPW = 400; // tDIPW ps DQ and DM input Pulse Width + parameter TIPW = 620; // tIPW ps Control and Address input Pulse Width + parameter TIS = 190; // tIS ps Input Setup Time + parameter TIH = 140; // tIH ps Input Hold Time + parameter TRAS_MIN = 36000; // tRAS ps Minimum Active to Precharge command time + parameter TRC = 51000; // tRC ps Active to Active/Auto Refresh command time + parameter TRCD = 15000; // tRCD ps Active to Read/Write command time + parameter TRP = 15000; // tRP ps Precharge command period + parameter TXP = 6000; // tXP ps Exit power down to a valid command + parameter TCKE = 5625; // tCKE ps CKE minimum high or low pulse width + parameter TAON = 250; // tAON ps RTT turn-on from ODTLon reference + parameter TWLS = 195; // tWLS ps Setup time for tDQS flop + parameter TWLH = 195; // tWLH ps Hold time of tDQS flop + parameter TWLO = 9000; // tWLO ps Write levelization output delay + parameter TAA_MIN = 15000; // TAA ps Internal READ command to first data + parameter CL_TIME = 15000; // CL ps Minimum CAS Latency + `elsif sg187E // sg187E is equivalent to the JEDEC DDR3-1066F (7-7-7) speed bin + parameter TCK_MIN = 1875; // tCK ps Minimum Clock Cycle Time + parameter TJIT_PER = 90; // tJIT(per) ps Period JItter + parameter TJIT_CC = 180; // tJIT(cc) ps Cycle to Cycle jitter + parameter TERR_2PER = 132; // tERR(2per) ps Accumulated Error (2-cycle) + parameter TERR_3PER = 157; // tERR(3per) ps Accumulated Error (3-cycle) + parameter TERR_4PER = 175; // tERR(4per) ps Accumulated Error (4-cycle) + parameter TERR_5PER = 188; // tERR(5per) ps Accumulated Error (5-cycle) + parameter TERR_6PER = 200; // tERR(6per) ps Accumulated Error (6-cycle) + parameter TERR_7PER = 209; // tERR(7per) ps Accumulated Error (7-cycle) + parameter TERR_8PER = 217; // tERR(8per) ps Accumulated Error (8-cycle) + parameter TERR_9PER = 224; // tERR(9per) ps Accumulated Error (9-cycle) + parameter TERR_10PER = 231; // tERR(10per)ps Accumulated Error (10-cycle) + parameter TERR_11PER = 237; // tERR(11per)ps Accumulated Error (11-cycle) + parameter TERR_12PER = 242; // tERR(12per)ps Accumulated Error (12-cycle) + parameter TDS = 75; // tDS ps DQ and DM input setup time relative to DQS + parameter TDH = 100; // tDH ps DQ and DM input hold time relative to DQS + parameter TDQSQ = 150; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access + parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition + parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time) + parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time) + parameter TDQSCK = 300; // tDQSCK ps DQS output access time from CK/CK# + parameter TQSH = 0.38; // tQSH tCK DQS Output High Pulse Width + parameter TQSL = 0.38; // tQSL tCK DQS Output Low Pulse Width + parameter TDIPW = 490; // tDIPW ps DQ and DM input Pulse Width + parameter TIPW = 780; // tIPW ps Control and Address input Pulse Width + parameter TIS = 275; // tIS ps Input Setup Time + parameter TIH = 200; // tIH ps Input Hold Time + parameter TRAS_MIN = 37500; // tRAS ps Minimum Active to Precharge command time + parameter TRC = 50625; // tRC ps Active to Active/Auto Refresh command time + parameter TRCD = 13125; // tRCD ps Active to Read/Write command time + parameter TRP = 13125; // tRP ps Precharge command period + parameter TXP = 7500; // tXP ps Exit power down to a valid command + parameter TCKE = 5625; // tCKE ps CKE minimum high or low pulse width + parameter TAON = 300; // tAON ps RTT turn-on from ODTLon reference + parameter TWLS = 245; // tWLS ps Setup time for tDQS flop + parameter TWLH = 245; // tWLH ps Hold time of tDQS flop + parameter TWLO = 9000; // tWLO ps Write levelization output delay + parameter TAA_MIN = 13125; // TAA ps Internal READ command to first data + parameter CL_TIME = 13125; // CL ps Minimum CAS Latency + `elsif sg187 // sg187 is equivalent to the JEDEC DDR3-1066G (8-8-8) speed bin + parameter TCK_MIN = 1875; // tCK ps Minimum Clock Cycle Time + parameter TJIT_PER = 90; // tJIT(per) ps Period JItter + parameter TJIT_CC = 180; // tJIT(cc) ps Cycle to Cycle jitter + parameter TERR_2PER = 132; // tERR(2per) ps Accumulated Error (2-cycle) + parameter TERR_3PER = 157; // tERR(3per) ps Accumulated Error (3-cycle) + parameter TERR_4PER = 175; // tERR(4per) ps Accumulated Error (4-cycle) + parameter TERR_5PER = 188; // tERR(5per) ps Accumulated Error (5-cycle) + parameter TERR_6PER = 200; // tERR(6per) ps Accumulated Error (6-cycle) + parameter TERR_7PER = 209; // tERR(7per) ps Accumulated Error (7-cycle) + parameter TERR_8PER = 217; // tERR(8per) ps Accumulated Error (8-cycle) + parameter TERR_9PER = 224; // tERR(9per) ps Accumulated Error (9-cycle) + parameter TERR_10PER = 231; // tERR(10per)ps Accumulated Error (10-cycle) + parameter TERR_11PER = 237; // tERR(11per)ps Accumulated Error (11-cycle) + parameter TERR_12PER = 242; // tERR(12per)ps Accumulated Error (12-cycle) + parameter TDS = 75; // tDS ps DQ and DM input setup time relative to DQS + parameter TDH = 100; // tDH ps DQ and DM input hold time relative to DQS + parameter TDQSQ = 150; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access + parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition + parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time) + parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time) + parameter TDQSCK = 300; // tDQSCK ps DQS output access time from CK/CK# + parameter TQSH = 0.38; // tQSH tCK DQS Output High Pulse Width + parameter TQSL = 0.38; // tQSL tCK DQS Output Low Pulse Width + parameter TDIPW = 490; // tDIPW ps DQ and DM input Pulse Width + parameter TIPW = 780; // tIPW ps Control and Address input Pulse Width + parameter TIS = 275; // tIS ps Input Setup Time + parameter TIH = 200; // tIH ps Input Hold Time + parameter TRAS_MIN = 37500; // tRAS ps Minimum Active to Precharge command time + parameter TRC = 52500; // tRC ps Active to Active/Auto Refresh command time + parameter TRCD = 15000; // tRCD ps Active to Read/Write command time + parameter TRP = 15000; // tRP ps Precharge command period + parameter TXP = 7500; // tXP ps Exit power down to a valid command + parameter TCKE = 5625; // tCKE ps CKE minimum high or low pulse width + parameter TAON = 300; // tAON ps RTT turn-on from ODTLon reference + parameter TWLS = 245; // tWLS ps Setup time for tDQS flop + parameter TWLH = 245; // tWLH ps Hold time of tDQS flop + parameter TWLO = 9000; // tWLO ps Write levelization output delay + parameter TAA_MIN = 15000; // TAA ps Internal READ command to first data + parameter CL_TIME = 15000; // CL ps Minimum CAS Latency + `elsif sg25E // sg25E is equivalent to the JEDEC DDR3-800D (5-5-5) speed bin + parameter TCK_MIN = 2500; // tCK ps Minimum Clock Cycle Time + parameter TJIT_PER = 100; // tJIT(per) ps Period JItter + parameter TJIT_CC = 200; // tJIT(cc) ps Cycle to Cycle jitter + parameter TERR_2PER = 147; // tERR(2per) ps Accumulated Error (2-cycle) + parameter TERR_3PER = 175; // tERR(3per) ps Accumulated Error (3-cycle) + parameter TERR_4PER = 194; // tERR(4per) ps Accumulated Error (4-cycle) + parameter TERR_5PER = 209; // tERR(5per) ps Accumulated Error (5-cycle) + parameter TERR_6PER = 222; // tERR(6per) ps Accumulated Error (6-cycle) + parameter TERR_7PER = 232; // tERR(7per) ps Accumulated Error (7-cycle) + parameter TERR_8PER = 241; // tERR(8per) ps Accumulated Error (8-cycle) + parameter TERR_9PER = 249; // tERR(9per) ps Accumulated Error (9-cycle) + parameter TERR_10PER = 257; // tERR(10per)ps Accumulated Error (10-cycle) + parameter TERR_11PER = 263; // tERR(11per)ps Accumulated Error (11-cycle) + parameter TERR_12PER = 269; // tERR(12per)ps Accumulated Error (12-cycle) + parameter TDS = 125; // tDS ps DQ and DM input setup time relative to DQS + parameter TDH = 150; // tDH ps DQ and DM input hold time relative to DQS + parameter TDQSQ = 200; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access + parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition + parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time) + parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time) + parameter TDQSCK = 400; // tDQSCK ps DQS output access time from CK/CK# + parameter TQSH = 0.38; // tQSH tCK DQS Output High Pulse Width + parameter TQSL = 0.38; // tQSL tCK DQS Output Low Pulse Width + parameter TDIPW = 600; // tDIPW ps DQ and DM input Pulse Width + parameter TIPW = 900; // tIPW ps Control and Address input Pulse Width + parameter TIS = 350; // tIS ps Input Setup Time + parameter TIH = 275; // tIH ps Input Hold Time + parameter TRAS_MIN = 37500; // tRAS ps Minimum Active to Precharge command time + parameter TRC = 50000; // tRC ps Active to Active/Auto Refresh command time + parameter TRCD = 12500; // tRCD ps Active to Read/Write command time + parameter TRP = 12500; // tRP ps Precharge command period + parameter TXP = 7500; // tXP ps Exit power down to a valid command + parameter TCKE = 7500; // tCKE ps CKE minimum high or low pulse width + parameter TAON = 400; // tAON ps RTT turn-on from ODTLon reference + parameter TWLS = 325; // tWLS ps Setup time for tDQS flop + parameter TWLH = 325; // tWLH ps Hold time of tDQS flop + parameter TWLO = 9000; // tWLO ps Write levelization output delay + parameter TAA_MIN = 12500; // TAA ps Internal READ command to first data + parameter CL_TIME = 12500; // CL ps Minimum CAS Latency + `else `define sg25 // sg25 is equivalent to the JEDEC DDR3-800E (6-6-6) speed bin + parameter TCK_MIN = 2500; // tCK ps Minimum Clock Cycle Time + parameter TJIT_PER = 100; // tJIT(per) ps Period JItter + parameter TJIT_CC = 200; // tJIT(cc) ps Cycle to Cycle jitter + parameter TERR_2PER = 147; // tERR(2per) ps Accumulated Error (2-cycle) + parameter TERR_3PER = 175; // tERR(3per) ps Accumulated Error (3-cycle) + parameter TERR_4PER = 194; // tERR(4per) ps Accumulated Error (4-cycle) + parameter TERR_5PER = 209; // tERR(5per) ps Accumulated Error (5-cycle) + parameter TERR_6PER = 222; // tERR(6per) ps Accumulated Error (6-cycle) + parameter TERR_7PER = 232; // tERR(7per) ps Accumulated Error (7-cycle) + parameter TERR_8PER = 241; // tERR(8per) ps Accumulated Error (8-cycle) + parameter TERR_9PER = 249; // tERR(9per) ps Accumulated Error (9-cycle) + parameter TERR_10PER = 257; // tERR(10per)ps Accumulated Error (10-cycle) + parameter TERR_11PER = 263; // tERR(11per)ps Accumulated Error (11-cycle) + parameter TERR_12PER = 269; // tERR(12per)ps Accumulated Error (12-cycle) + parameter TDS = 125; // tDS ps DQ and DM input setup time relative to DQS + parameter TDH = 150; // tDH ps DQ and DM input hold time relative to DQS + parameter TDQSQ = 200; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access + parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition + parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time) + parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time) + parameter TDQSCK = 400; // tDQSCK ps DQS output access time from CK/CK# + parameter TQSH = 0.38; // tQSH tCK DQS Output High Pulse Width + parameter TQSL = 0.38; // tQSL tCK DQS Output Low Pulse Width + parameter TDIPW = 600; // tDIPW ps DQ and DM input Pulse Width + parameter TIPW = 900; // tIPW ps Control and Address input Pulse Width + parameter TIS = 350; // tIS ps Input Setup Time + parameter TIH = 275; // tIH ps Input Hold Time + parameter TRAS_MIN = 37500; // tRAS ps Minimum Active to Precharge command time + parameter TRC = 52500; // tRC ps Active to Active/Auto Refresh command time + parameter TRCD = 15000; // tRCD ps Active to Read/Write command time + parameter TRP = 15000; // tRP ps Precharge command period + parameter TXP = 7500; // tXP ps Exit power down to a valid command + parameter TCKE = 7500; // tCKE ps CKE minimum high or low pulse width + parameter TAON = 400; // tAON ps RTT turn-on from ODTLon reference + parameter TWLS = 325; // tWLS ps Setup time for tDQS flop + parameter TWLH = 325; // tWLH ps Hold time of tDQS flop + parameter TWLO = 9000; // tWLO ps Write levelization output delay + parameter TAA_MIN = 15000; // TAA ps Internal READ command to first data + parameter CL_TIME = 15000; // CL ps Minimum CAS Latency + `endif + + `ifdef x16 + `ifdef sg093 + parameter TRRD = 6000; // tRRD ps (2KB page size) Active bank a to Active bank b command time + parameter TFAW = 35000; // tFAW ps (2KB page size) Four Bank Activate window + `elsif sg093E + parameter TRRD = 6000; // tRRD ps (2KB page size) Active bank a to Active bank b command time + parameter TFAW = 35000; // tFAW ps (2KB page size) Four Bank Activate window + `elsif sg093F + parameter TRRD = 6000; // tRRD ps (2KB page size) Active bank a to Active bank b command time + parameter TFAW = 35000; // tFAW ps (2KB page size) Four Bank Activate window + `elsif sg107 + parameter TRRD = 6000; // tRRD ps (2KB page size) Active bank a to Active bank b command time + parameter TFAW = 35000; // tFAW ps (2KB page size) Four Bank Activate window + `elsif sg107E + parameter TRRD = 6000; // tRRD ps (2KB page size) Active bank a to Active bank b command time + parameter TFAW = 35000; // tFAW ps (2KB page size) Four Bank Activate window + `elsif sg107F + parameter TRRD = 6000; // tRRD ps (2KB page size) Active bank a to Active bank b command time + parameter TFAW = 35000; // tFAW ps (2KB page size) Four Bank Activate window + `elsif sg125E + parameter TRRD = 7500; // tRRD ps (2KB page size) Active bank a to Active bank b command time + parameter TFAW = 40000; // tFAW ps (2KB page size) Four Bank Activate window + `elsif sg125 + parameter TRRD = 7500; // tRRD ps (2KB page size) Active bank a to Active bank b command time + parameter TFAW = 40000; // tFAW ps (2KB page size) Four Bank Activate window + `elsif sg15E + parameter TRRD = 7500; // tRRD ps (2KB page size) Active bank a to Active bank b command time + parameter TFAW = 45000; // tFAW ps (2KB page size) Four Bank Activate window + `elsif sg15 + parameter TRRD = 7500; // tRRD ps (2KB page size) Active bank a to Active bank b command time + parameter TFAW = 45000; // tFAW ps (2KB page size) Four Bank Activate window + `else // sg187E, sg187, sg25, sg25E + parameter TRRD = 10000; // tRRD ps (2KB page size) Active bank a to Active bank b command time + parameter TFAW = 50000; // tFAW ps (2KB page size) Four Bank Activate window + `endif + `else // x4, x8 + `ifdef sg093 + parameter TRRD = 5000; // tRRD ps (1KB page size) Active bank a to Active bank b command time + parameter TFAW = 25000; // tFAW ps (1KB page size) Four Bank Activate window + `elsif sg093E + parameter TRRD = 5000; // tRRD ps (1KB page size) Active bank a to Active bank b command time + parameter TFAW = 25000; // tFAW ps (1KB page size) Four Bank Activate window + `elsif sg093F + parameter TRRD = 5000; // tRRD ps (1KB page size) Active bank a to Active bank b command time + parameter TFAW = 25000; // tFAW ps (1KB page size) Four Bank Activate window + `elsif sg107 + parameter TRRD = 5000; // tRRD ps (1KB page size) Active bank a to Active bank b command time + parameter TFAW = 25000; // tFAW ps (1KB page size) Four Bank Activate window + `elsif sg107E + parameter TRRD = 5000; // tRRD ps (1KB page size) Active bank a to Active bank b command time + parameter TFAW = 25000; // tFAW ps (1KB page size) Four Bank Activate window + `elsif sg107F + parameter TRRD = 5000; // tRRD ps (1KB page size) Active bank a to Active bank b command time + parameter TFAW = 25000; // tFAW ps (1KB page size) Four Bank Activate window + `elsif sg125E + parameter TRRD = 6000; // tRRD ps (1KB page size) Active bank a to Active bank b command time + parameter TFAW = 30000; // tFAW ps (1KB page size) Four Bank Activate window + `elsif sg125 + parameter TRRD = 6000; // tRRD ps (1KB page size) Active bank a to Active bank b command time + parameter TFAW = 30000; // tFAW ps (1KB page size) Four Bank Activate window + `elsif sg15E + parameter TRRD = 6000; // tRRD ps (1KB page size) Active bank a to Active bank b command time + parameter TFAW = 30000; // tFAW ps (1KB page size) Four Bank Activate window + `elsif sg15 + parameter TRRD = 6000; // tRRD ps (1KB page size) Active bank a to Active bank b command time + parameter TFAW = 30000; // tFAW ps (1KB page size) Four Bank Activate window + `elsif sg187E + parameter TRRD = 7500; // tRRD ps (1KB page size) Active bank a to Active bank b command time + parameter TFAW = 37500; // tFAW ps (1KB page size) Four Bank Activate window + `elsif sg187 + parameter TRRD = 7500; // tRRD ps (1KB page size) Active bank a to Active bank b command time + parameter TFAW = 37500; // tFAW ps (1KB page size) Four Bank Activate window + `else // sg25, sg25E + parameter TRRD = 10000; // tRRD ps (1KB page size) Active bank a to Active bank b command time + parameter TFAW = 40000; // tFAW ps (1KB page size) Four Bank Activate window + `endif + `endif + + // Timing Parameters + + // Mode Register + parameter CL_MIN = 5; // CL tCK Minimum CAS Latency + parameter CL_MAX = 14; // CL tCK Maximum CAS Latency + parameter AL_MIN = 0; // AL tCK Minimum Additive Latency + parameter AL_MAX = 2; // AL tCK Maximum Additive Latency + parameter WR_MIN = 5; // WR tCK Minimum Write Recovery + parameter WR_MAX = 16; // WR tCK Maximum Write Recovery + parameter BL_MIN = 4; // BL tCK Minimum Burst Length + parameter BL_MAX = 8; // BL tCK Minimum Burst Length + parameter CWL_MIN = 5; // CWL tCK Minimum CAS Write Latency + parameter CWL_MAX = 10; // CWL tCK Maximum CAS Write Latency + + // Clock + parameter TCK_MAX = 3300; // tCK ps Maximum Clock Cycle Time + parameter TCH_AVG_MIN = 0.47; // tCH tCK Minimum Clock High-Level Pulse Width + parameter TCL_AVG_MIN = 0.47; // tCL tCK Minimum Clock Low-Level Pulse Width + parameter TCH_AVG_MAX = 0.53; // tCH tCK Maximum Clock High-Level Pulse Width + parameter TCL_AVG_MAX = 0.53; // tCL tCK Maximum Clock Low-Level Pulse Width + parameter TCH_ABS_MIN = 0.43; // tCH tCK Minimum Clock High-Level Pulse Width + parameter TCL_ABS_MIN = 0.43; // tCL tCK Maximum Clock Low-Level Pulse Width + parameter TCKE_TCK = 3; // tCKE tCK CKE minimum high or low pulse width + parameter TAA_MAX = 20000; // TAA ps Internal READ command to first data + + // Data OUT + parameter TQH = 0.38; // tQH ps DQ output hold time from DQS, DQS# + // Data Strobe OUT + parameter TRPRE = 0.90; // tRPRE tCK DQS Read Preamble + parameter TRPST = 0.30; // tRPST tCK DQS Read Postamble + // Data Strobe IN + parameter TDQSH = 0.45; // tDQSH tCK DQS input High Pulse Width + parameter TDQSL = 0.45; // tDQSL tCK DQS input Low Pulse Width + parameter TWPRE = 0.90; // tWPRE tCK DQS Write Preamble + parameter TWPST = 0.30; // tWPST tCK DQS Write Postamble + // Command and Address + parameter TZQCS = 64; // tZQCS tCK ZQ Cal (Short) time + parameter TZQINIT = 512; // tZQinit tCK ZQ Cal (Long) time + parameter TZQOPER = 256; // tZQoper tCK ZQ Cal (Long) time + parameter TCCD = 4; // tCCD tCK Cas to Cas command delay + parameter TCCD_DG = 2; // tCCD_DG tCK Cas to Cas command delay to different group + parameter TRAS_MAX = 60e9; // tRAS ps Maximum Active to Precharge command time + parameter TWR = 15000; // tWR ps Write recovery time + parameter TMRD = 4; // tMRD tCK Load Mode Register command cycle time + parameter TMOD = 15000; // tMOD ps LOAD MODE to non-LOAD MODE command cycle time + parameter TMOD_TCK = 12; // tMOD tCK LOAD MODE to non-LOAD MODE command cycle time + parameter TRRD_TCK = 4; // tRRD tCK Active bank a to Active bank b command time + parameter TRRD_DG = 3000; // tRRD_DG ps Active bank a to Active bank b command time to different group + parameter TRRD_DG_TCK = 2; // tRRD_DG tCK Active bank a to Active bank b command time to different group + parameter TRTP = 7500; // tRTP ps Read to Precharge command delay + parameter TRTP_TCK = 4; // tRTP tCK Read to Precharge command delay + parameter TWTR = 7500; // tWTR ps Write to Read command delay + parameter TWTR_DG = 3750; // tWTR_DG ps Write to Read command delay to different group + parameter TWTR_TCK = 4; // tWTR tCK Write to Read command delay + parameter TWTR_DG_TCK = 2; // tWTR_DG tCK Write to Read command delay to different group + parameter TDLLK = 512; // tDLLK tCK DLL locking time + // Refresh - 2Gb + parameter TRFC_MIN = 160000; // tRFC ps Refresh to Refresh Command interval minimum value + parameter TRFC_MAX =70312500; // tRFC ps Refresh to Refresh Command Interval maximum value + // Power Down + parameter TXP_TCK = 3; // tXP tCK Exit power down to a valid command + parameter TXPDLL = 24000; // tXPDLL ps Exit precharge power down to READ or WRITE command (DLL-off mode) + parameter TXPDLL_TCK = 10; // tXPDLL tCK Exit precharge power down to READ or WRITE command (DLL-off mode) + parameter TACTPDEN = 1; // tACTPDEN tCK Timing of last ACT command to power down entry + parameter TPRPDEN = 1; // tPREPDEN tCK Timing of last PRE command to power down entry + parameter TREFPDEN = 1; // tARPDEN tCK Timing of last REFRESH command to power down entry + parameter TCPDED = 1; // tCPDED tCK Command pass disable/enable delay + parameter TPD_MAX =TRFC_MAX; // tPD ps Power-down entry-to-exit timing + parameter TXPR = 170000; // tXPR ps Exit Reset from CKE assertion to a valid command + parameter TXPR_TCK = 5; // tXPR tCK Exit Reset from CKE assertion to a valid command + // Self Refresh + parameter TXS = 170000; // tXS ps Exit self refesh to a non-read or write command + parameter TXS_TCK = 5; // tXS tCK Exit self refesh to a non-read or write command + parameter TXSDLL = TDLLK; // tXSRD tCK Exit self refresh to a read or write command + parameter TISXR = TIS; // tISXR ps CKE setup time during self refresh exit. + parameter TCKSRE = 10000; // tCKSRE ps Valid Clock requirement after self refresh entry (SRE) + parameter TCKSRE_TCK = 5; // tCKSRE tCK Valid Clock requirement after self refresh entry (SRE) + parameter TCKSRX = 10000; // tCKSRX ps Valid Clock requirement prior to self refresh exit (SRX) + parameter TCKSRX_TCK = 5; // tCKSRX tCK Valid Clock requirement prior to self refresh exit (SRX) + parameter TCKESR_TCK = 4; // tCKESR tCK Minimum CKE low width for Self Refresh entry to exit timing + // ODT + parameter TAOF = 0.7; // tAOF tCK RTT turn-off from ODTLoff reference + parameter TAONPD = 8500; // tAONPD ps Asynchronous RTT turn-on delay (Power-Down with DLL frozen) + parameter TAOFPD = 8500; // tAONPD ps Asynchronous RTT turn-off delay (Power-Down with DLL frozen) + parameter ODTH4 = 4; // ODTH4 tCK ODT minimum HIGH time after ODT assertion or write (BL4) + parameter ODTH8 = 6; // ODTH8 tCK ODT minimum HIGH time after write (BL8) + parameter TADC = 0.7; // tADC tCK RTT dynamic change skew + // Write Levelization + parameter TWLMRD = 40; // tWLMRD tCK First DQS pulse rising edge after tDQSS margining mode is programmed + parameter TWLDQSEN = 25; // tWLDQSEN tCK DQS/DQS delay after tDQSS margining mode is programmed + parameter TWLOE = 2000; // tWLOE ps Write levelization output error + + // Size Parameters based on Part Width + + `ifdef x4 + parameter DM_BITS = 1; // Set this parameter to control how many Data Mask bits are used + parameter ADDR_BITS = 15; // MAX Address Bits + parameter ROW_BITS = 15; // Set this parameter to control how many Address bits are used + parameter COL_BITS = 11; // Set this parameter to control how many Column bits are used + parameter DQ_BITS = 4; // Set this parameter to control how many Data bits are used **Same as part bit width** + parameter DQS_BITS = 1; // Set this parameter to control how many Dqs bits are used + `elsif x8 + parameter DM_BITS = 1; // Set this parameter to control how many Data Mask bits are used + parameter ADDR_BITS = 15; // MAX Address Bits + parameter ROW_BITS = 15; // Set this parameter to control how many Address bits are used + parameter COL_BITS = 10; // Set this parameter to control how many Column bits are used + parameter DQ_BITS = 8; // Set this parameter to control how many Data bits are used **Same as part bit width** + parameter DQS_BITS = 1; // Set this parameter to control how many Dqs bits are used + `else `define x16 + parameter DM_BITS = 2; // Set this parameter to control how many Data Mask bits are used + parameter ADDR_BITS = 14; // MAX Address Bits + parameter ROW_BITS = 14; // Set this parameter to control how many Address bits are used + parameter COL_BITS = 10; // Set this parameter to control how many Column bits are used + parameter DQ_BITS = 16; // Set this parameter to control how many Data bits are used **Same as part bit width** + parameter DQS_BITS = 2; // Set this parameter to control how many Dqs bits are used + `endif + + // Size Parameters + parameter BA_BITS = 3; // Set this parmaeter to control how many Bank Address bits are used + parameter MEM_BITS = 15; // Set this parameter to control how many write data bursts can be stored in memory. The default is 2^10=1024. + parameter AP = 10; // the address bit that controls auto-precharge and precharge-all + parameter BC = 12; // the address bit that controls burst chop + parameter BL_BITS = 3; // the number of bits required to count to BL_MAX + parameter BO_BITS = 2; // the number of Burst Order Bits + + `ifdef QUAD_RANK + `define DUAL_RANK // also define DUAL_RANK + parameter CS_BITS = 4; // Number of Chip Select Bits + parameter RANKS = 4; // Number of Chip Selects + `elsif DUAL_RANK + parameter CS_BITS = 2; // Number of Chip Select Bits + parameter RANKS = 2; // Number of Chip Selects + `else + parameter CS_BITS = 2; // Number of Chip Select Bits + parameter RANKS = 1; // Number of Chip Selects + `endif + + // Simulation parameters + parameter RZQ = 240; // termination resistance + parameter PRE_DEF_PAT = 8'hAA; // value returned during mpr pre-defined pattern readout + parameter STOP_ON_ERROR = 1; // If set to 1, the model will halt on command sequence/major errors + parameter DEBUG = 1; // Turn on Debug messages + parameter BUS_DELAY = 0; // delay in nanoseconds + parameter RANDOM_OUT_DELAY = 0; // If set to 1, the model will put a random amount of delay on DQ/DQS during reads + parameter RANDOM_SEED = 711689044; //seed value for random generator. + + parameter RDQSEN_PRE = 2; // DQS driving time prior to first read strobe + parameter RDQSEN_PST = 1; // DQS driving time after last read strobe + parameter RDQS_PRE = 2; // DQS low time prior to first read strobe + parameter RDQS_PST = 1; // DQS low time after last read strobe + parameter RDQEN_PRE = 0; // DQ/DM driving time prior to first read data + parameter RDQEN_PST = 0; // DQ/DM driving time after last read data + parameter WDQS_PRE = 2; // DQS half clock periods prior to first write strobe + parameter WDQS_PST = 1; // DQS half clock periods after last write strobe + + // check for legal cas latency based on the cas write latency + function valid_cl; + input [3:0] cl; + input [3:0] cwl; + + case ({cwl, cl}) + `ifdef sg093 + {4'd5, 4'd6 }, + {4'd6, 4'd7 }, + {4'd6, 4'd8 }, + {4'd7, 4'd9 }, + {4'd7, 4'd10}, + {4'd8, 4'd11}, + {4'd9, 4'd13}, + {4'd10, 4'd14}: valid_cl = 1; + `elsif sg093E + {4'd5, 4'd5 }, + {4'd5, 4'd6 }, + {4'd6, 4'd7 }, + {4'd6, 4'd8 }, + {4'd7, 4'd9 }, + {4'd7, 4'd10}, + {4'd8, 4'd10}, + {4'd8, 4'd11}, + {4'd9, 4'd12}, + {4'd9, 4'd13}, + {4'd10, 4'd13}, + {4'd10, 4'd14}: valid_cl = 1; + `elsif sg093F + {4'd5, 4'd5 }, + {4'd5, 4'd6 }, + {4'd6, 4'd6 }, + {4'd6, 4'd7 }, + {4'd6, 4'd8 }, + {4'd7, 4'd8 }, + {4'd7, 4'd9 }, + {4'd7, 4'd10}, + {4'd8, 4'd9 }, + {4'd8, 4'd10}, + {4'd8, 4'd11}, + {4'd9, 4'd11}, + {4'd9, 4'd12}, + {4'd9, 4'd13}, + {4'd10, 4'd12}, + {4'd10, 4'd13}, + {4'd10, 4'd14}: valid_cl = 1; + `elsif sg107 + {4'd5, 4'd6 }, + {4'd6, 4'd8 }, + {4'd7, 4'd10}, + {4'd9, 4'd13}: valid_cl = 1; + `elsif sg107E + {4'd5, 4'd6 }, + {4'd6, 4'd7 }, + {4'd6, 4'd8 }, + {4'd7, 4'd9 }, + {4'd7, 4'd10}, + {4'd8, 4'd11}, + {4'd9, 4'd12}, + {4'd9, 4'd13}: valid_cl = 1; + `elsif sg107F + {4'd5, 4'd5 }, + {4'd5, 4'd6 }, + {4'd6, 4'd7 }, + {4'd6, 4'd8 }, + {4'd7, 4'd8 }, + {4'd7, 4'd9 }, + {4'd7, 4'd10}, + {4'd8, 4'd10}, + {4'd8, 4'd11}, + {4'd9, 4'd11}, + {4'd9, 4'd12}, + {4'd9, 4'd13}: valid_cl = 1; + `elsif sg125E + {4'd5, 4'd5 }, + {4'd5, 4'd6 }, + {4'd6, 4'd7 }, + {4'd6, 4'd8 }, + {4'd7, 4'd9 }, + {4'd7, 4'd10}, + {4'd8, 4'd10}, + {4'd8, 4'd11}: valid_cl = 1; + `elsif sg125 + {4'd5, 4'd5 }, + {4'd5, 4'd6 }, + {4'd6, 4'd7 }, + {4'd6, 4'd8 }, + {4'd7, 4'd9 }, + {4'd7, 4'd10}, + {4'd8, 4'd11}: valid_cl = 1; + `elsif sg15E + {4'd5, 4'd5 }, + {4'd5, 4'd6 }, + {4'd6, 4'd7 }, + {4'd6, 4'd8 }, + {4'd7, 4'd9 }, + {4'd7, 4'd10}: valid_cl = 1; + `elsif sg15 + {4'd5, 4'd5 }, + {4'd5, 4'd6 }, + {4'd6, 4'd8 }, + {4'd7, 4'd10}: valid_cl = 1; + `elsif sg187E + {4'd5, 4'd5 }, + {4'd5, 4'd6 }, + {4'd6, 4'd7 }, + {4'd6, 4'd8 }: valid_cl = 1; + `elsif sg187 + {4'd5, 4'd5 }, + {4'd5, 4'd6 }, + {4'd6, 4'd8 }: valid_cl = 1; + `elsif sg25E + {4'd5, 4'd5 }, + {4'd5, 4'd6 }: valid_cl = 1; + `elsif sg25 + {4'd5, 4'd5 }, + {4'd5, 4'd6 }: valid_cl = 1; + `endif + default : valid_cl = 0; + endcase + endfunction + + // find the minimum valid cas write latency + function [3:0] min_cwl; + input period; + real period; + min_cwl = (period >= 2500.0) ? 5: + (period >= 1875.0) ? 6: + (period >= 1500.0) ? 7: + (period >= 1250.0) ? 8: + (period >= 1070.0) ? 9: + 10; // (period >= 935) + endfunction + + // find the minimum valid cas latency + function [3:0] min_cl; + input period; + real period; + reg [3:0] cwl; + reg [3:0] cl; + begin + cwl = min_cwl(period); + for (cl=CL_MAX; cl>=CL_MIN; cl=cl-1) begin + if (valid_cl(cl, cwl)) begin + min_cl = cl; + end + end + end + endfunction + + +`else `define x1Gb // 1Gb parts + + // SYMBOL UNITS DESCRIPTION + // ------ ----- ----------- + `ifdef sg093 // sg093 is equivalent to the JEDEC DDR3-2133 (14-14-14) speed bin + parameter TCK_MIN = 935; // tCK ps Minimum Clock Cycle Time + parameter TJIT_PER = 50; // tJIT(per) ps Period JItter + parameter TJIT_CC = 100; // tJIT(cc) ps Cycle to Cycle jitter + parameter TERR_2PER = 74; // tERR(2per) ps Accumulated Error (2-cycle) + parameter TERR_3PER = 87; // tERR(3per) ps Accumulated Error (3-cycle) + parameter TERR_4PER = 97; // tERR(4per) ps Accumulated Error (4-cycle) + parameter TERR_5PER = 105; // tERR(5per) ps Accumulated Error (5-cycle) + parameter TERR_6PER = 111; // tERR(6per) ps Accumulated Error (6-cycle) + parameter TERR_7PER = 116; // tERR(7per) ps Accumulated Error (7-cycle) + parameter TERR_8PER = 121; // tERR(8per) ps Accumulated Error (8-cycle) + parameter TERR_9PER = 125; // tERR(9per) ps Accumulated Error (9-cycle) + parameter TERR_10PER = 128; // tERR(10per)ps Accumulated Error (10-cycle) + parameter TERR_11PER = 132; // tERR(11per)ps Accumulated Error (11-cycle) + parameter TERR_12PER = 134; // tERR(12per)ps Accumulated Error (12-cycle) + parameter TDS = 5; // tDS ps DQ and DM input setup time relative to DQS + parameter TDH = 20; // tDH ps DQ and DM input hold time relative to DQS + parameter TDQSQ = 70; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access + parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition + parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) + parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) + parameter TDQSCK = 180; // tDQSCK ps DQS output access time from CK/CK# + parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width + parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width + parameter TDIPW = 280; // tDIPW ps DQ and DM input Pulse Width + parameter TIPW = 470; // tIPW ps Control and Address input Pulse Width + parameter TIS = 35; // tIS ps Input Setup Time + parameter TIH = 75; // tIH ps Input Hold Time + parameter TRAS_MIN = 33000; // tRAS ps Minimum Active to Precharge command time + parameter TRC = 48090; // tRC ps Active to Active/Auto Refresh command time + parameter TRCD = 13090; // tRCD ps Active to Read/Write command time + parameter TRP = 13090; // tRP ps Precharge command period + parameter TXP = 6000; // tXP ps Exit power down to a valid command + parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width + parameter TAON = 180; // tAON ps RTT turn-on from ODTLon reference + parameter TWLS = 122; // tWLS ps Setup time for tDQS flop + parameter TWLH = 122; // tWLH ps Hold time of tDQS flop + parameter TWLO = 7500; // tWLO ps Write levelization output delay + parameter TAA_MIN = 13090; // TAA ps Internal READ command to first data + parameter CL_TIME = 13090; // CL ps Minimum CAS Latency + `elsif sg093E // sg093E is equivalent to the JEDEC DDR3-2133 (13-13-13) speed bin + parameter TCK_MIN = 935; // tCK ps Minimum Clock Cycle Time + parameter TJIT_PER = 50; // tJIT(per) ps Period JItter + parameter TJIT_CC = 100; // tJIT(cc) ps Cycle to Cycle jitter + parameter TERR_2PER = 74; // tERR(2per) ps Accumulated Error (2-cycle) + parameter TERR_3PER = 87; // tERR(3per) ps Accumulated Error (3-cycle) + parameter TERR_4PER = 97; // tERR(4per) ps Accumulated Error (4-cycle) + parameter TERR_5PER = 105; // tERR(5per) ps Accumulated Error (5-cycle) + parameter TERR_6PER = 111; // tERR(6per) ps Accumulated Error (6-cycle) + parameter TERR_7PER = 116; // tERR(7per) ps Accumulated Error (7-cycle) + parameter TERR_8PER = 121; // tERR(8per) ps Accumulated Error (8-cycle) + parameter TERR_9PER = 125; // tERR(9per) ps Accumulated Error (9-cycle) + parameter TERR_10PER = 128; // tERR(10per)ps Accumulated Error (10-cycle) + parameter TERR_11PER = 132; // tERR(11per)ps Accumulated Error (11-cycle) + parameter TERR_12PER = 134; // tERR(12per)ps Accumulated Error (12-cycle) + parameter TDS = 5; // tDS ps DQ and DM input setup time relative to DQS + parameter TDH = 20; // tDH ps DQ and DM input hold time relative to DQS + parameter TDQSQ = 70; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access + parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition + parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) + parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) + parameter TDQSCK = 175; // tDQSCK ps DQS output access time from CK/CK# + parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width + parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width + parameter TDIPW = 280; // tDIPW ps DQ and DM input Pulse Width + parameter TIPW = 470; // tIPW ps Control and Address input Pulse Width + parameter TIS = 35; // tIS ps Input Setup Time + parameter TIH = 75; // tIH ps Input Hold Time + parameter TRAS_MIN = 33000; // tRAS ps Minimum Active to Precharge command time + parameter TRC = 47155; // tRC ps Active to Active/Auto Refresh command time + parameter TRCD = 12155; // tRCD ps Active to Read/Write command time + parameter TRP = 12155; // tRP ps Precharge command period + parameter TXP = 6000; // tXP ps Exit power down to a valid command + parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width + parameter TAON = 180; // tAON ps RTT turn-on from ODTLon reference + parameter TWLS = 122; // tWLS ps Setup time for tDQS flop + parameter TWLH = 122; // tWLH ps Hold time of tDQS flop + parameter TWLO = 7500; // tWLO ps Write levelization output delay + parameter TAA_MIN = 12155; // TAA ps Internal READ command to first data + parameter CL_TIME = 12155; // CL ps Minimum CAS Latency + `elsif sg093F // sg093F is equivalent to the JEDEC DDR3-2133 (12-12-12) speed bin + parameter TCK_MIN = 935; // tCK ps Minimum Clock Cycle Time + parameter TJIT_PER = 50; // tJIT(per) ps Period JItter + parameter TJIT_CC = 100; // tJIT(cc) ps Cycle to Cycle jitter + parameter TERR_2PER = 74; // tERR(2per) ps Accumulated Error (2-cycle) + parameter TERR_3PER = 87; // tERR(3per) ps Accumulated Error (3-cycle) + parameter TERR_4PER = 97; // tERR(4per) ps Accumulated Error (4-cycle) + parameter TERR_5PER = 105; // tERR(5per) ps Accumulated Error (5-cycle) + parameter TERR_6PER = 111; // tERR(6per) ps Accumulated Error (6-cycle) + parameter TERR_7PER = 116; // tERR(7per) ps Accumulated Error (7-cycle) + parameter TERR_8PER = 121; // tERR(8per) ps Accumulated Error (8-cycle) + parameter TERR_9PER = 125; // tERR(9per) ps Accumulated Error (9-cycle) + parameter TERR_10PER = 128; // tERR(10per)ps Accumulated Error (10-cycle) + parameter TERR_11PER = 132; // tERR(11per)ps Accumulated Error (11-cycle) + parameter TERR_12PER = 134; // tERR(12per)ps Accumulated Error (12-cycle) + parameter TDS = 5; // tDS ps DQ and DM input setup time relative to DQS + parameter TDH = 20; // tDH ps DQ and DM input hold time relative to DQS + parameter TDQSQ = 70; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access + parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition + parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) + parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) + parameter TDQSCK = 175; // tDQSCK ps DQS output access time from CK/CK# + parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width + parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width + parameter TDIPW = 280; // tDIPW ps DQ and DM input Pulse Width + parameter TIPW = 470; // tIPW ps Control and Address input Pulse Width + parameter TIS = 35; // tIS ps Input Setup Time + parameter TIH = 75; // tIH ps Input Hold Time + parameter TRAS_MIN = 33000; // tRAS ps Minimum Active to Precharge command time + parameter TRC = 46220; // tRC ps Active to Active/Auto Refresh command time + parameter TRCD = 11220; // tRCD ps Active to Read/Write command time + parameter TRP = 11220; // tRP ps Precharge command period + parameter TXP = 6000; // tXP ps Exit power down to a valid command + parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width + parameter TAON = 180; // tAON ps RTT turn-on from ODTLon reference + parameter TWLS = 122; // tWLS ps Setup time for tDQS flop + parameter TWLH = 122; // tWLH ps Hold time of tDQS flop + parameter TWLO = 7500; // tWLO ps Write levelization output delay + parameter TAA_MIN = 11220; // TAA ps Internal READ command to first data + parameter CL_TIME = 11220; // CL ps Minimum CAS Latency + `elsif sg107 // sg107 is equivalent to the JEDEC DDR3-1866 (13-13-13) speed bin + parameter TCK_MIN = 1070; // tCK ps Minimum Clock Cycle Time + parameter TJIT_PER = 60; // tJIT(per) ps Period JItter + parameter TJIT_CC = 120; // tJIT(cc) ps Cycle to Cycle jitter + parameter TERR_2PER = 88; // tERR(2per) ps Accumulated Error (2-cycle) + parameter TERR_3PER = 105; // tERR(3per) ps Accumulated Error (3-cycle) + parameter TERR_4PER = 117; // tERR(4per) ps Accumulated Error (4-cycle) + parameter TERR_5PER = 126; // tERR(5per) ps Accumulated Error (5-cycle) + parameter TERR_6PER = 133; // tERR(6per) ps Accumulated Error (6-cycle) + parameter TERR_7PER = 139; // tERR(7per) ps Accumulated Error (7-cycle) + parameter TERR_8PER = 145; // tERR(8per) ps Accumulated Error (8-cycle) + parameter TERR_9PER = 150; // tERR(9per) ps Accumulated Error (9-cycle) + parameter TERR_10PER = 154; // tERR(10per)ps Accumulated Error (10-cycle) + parameter TERR_11PER = 158; // tERR(11per)ps Accumulated Error (11-cycle) + parameter TERR_12PER = 161; // tERR(12per)ps Accumulated Error (12-cycle) + parameter TDS = 10; // tDS ps DQ and DM input setup time relative to DQS + parameter TDH = 20; // tDH ps DQ and DM input hold time relative to DQS + parameter TDQSQ = 80; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access + parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition + parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) + parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) + parameter TDQSCK = 200; // tDQSCK ps DQS output access time from CK/CK# + parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width + parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width + parameter TDIPW = 320; // tDIPW ps DQ and DM input Pulse Width + parameter TIPW = 535; // tIPW ps Control and Address input Pulse Width + parameter TIS = 50; // tIS ps Input Setup Time + parameter TIH = 100; // tIH ps Input Hold Time + parameter TRAS_MIN = 34000; // tRAS ps Minimum Active to Precharge command time + parameter TRC = 48910; // tRC ps Active to Active/Auto Refresh command time + parameter TRCD = 13910; // tRCD ps Active to Read/Write command time + parameter TRP = 13910; // tRP ps Precharge command period + parameter TXP = 6000; // tXP ps Exit power down to a valid command + parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width + parameter TAON = 200; // tAON ps RTT turn-on from ODTLon reference + parameter TWLS = 140; // tWLS ps Setup time for tDQS flop + parameter TWLH = 140; // tWLH ps Hold time of tDQS flop + parameter TWLO = 7500; // tWLO ps Write levelization output delay + parameter TAA_MIN = 13910; // TAA ps Internal READ command to first data + parameter CL_TIME = 13910; // CL ps Minimum CAS Latency + `elsif sg107E // sg107E is equivalent to the JEDEC DDR3-1866 (12-12-12) speed bin + parameter TCK_MIN = 1070; // tCK ps Minimum Clock Cycle Time + parameter TJIT_PER = 60; // tJIT(per) ps Period JItter + parameter TJIT_CC = 120; // tJIT(cc) ps Cycle to Cycle jitter + parameter TERR_2PER = 88; // tERR(2per) ps Accumulated Error (2-cycle) + parameter TERR_3PER = 105; // tERR(3per) ps Accumulated Error (3-cycle) + parameter TERR_4PER = 117; // tERR(4per) ps Accumulated Error (4-cycle) + parameter TERR_5PER = 126; // tERR(5per) ps Accumulated Error (5-cycle) + parameter TERR_6PER = 133; // tERR(6per) ps Accumulated Error (6-cycle) + parameter TERR_7PER = 139; // tERR(7per) ps Accumulated Error (7-cycle) + parameter TERR_8PER = 145; // tERR(8per) ps Accumulated Error (8-cycle) + parameter TERR_9PER = 150; // tERR(9per) ps Accumulated Error (9-cycle) + parameter TERR_10PER = 154; // tERR(10per)ps Accumulated Error (10-cycle) + parameter TERR_11PER = 158; // tERR(11per)ps Accumulated Error (11-cycle) + parameter TERR_12PER = 161; // tERR(12per)ps Accumulated Error (12-cycle) + parameter TDS = 10; // tDS ps DQ and DM input setup time relative to DQS + parameter TDH = 20; // tDH ps DQ and DM input hold time relative to DQS + parameter TDQSQ = 80; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access + parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition + parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) + parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) + parameter TDQSCK = 200; // tDQSCK ps DQS output access time from CK/CK# + parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width + parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width + parameter TDIPW = 320; // tDIPW ps DQ and DM input Pulse Width + parameter TIPW = 535; // tIPW ps Control and Address input Pulse Width + parameter TIS = 50; // tIS ps Input Setup Time + parameter TIH = 100; // tIH ps Input Hold Time + parameter TRAS_MIN = 34000; // tRAS ps Minimum Active to Precharge command time + parameter TRC = 47840; // tRC ps Active to Active/Auto Refresh command time + parameter TRCD = 12840; // tRCD ps Active to Read/Write command time + parameter TRP = 12840; // tRP ps Precharge command period + parameter TXP = 6000; // tXP ps Exit power down to a valid command + parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width + parameter TAON = 200; // tAON ps RTT turn-on from ODTLon reference + parameter TWLS = 140; // tWLS ps Setup time for tDQS flop + parameter TWLH = 140; // tWLH ps Hold time of tDQS flop + parameter TWLO = 7500; // tWLO ps Write levelization output delay + parameter TAA_MIN = 12840; // TAA ps Internal READ command to first data + parameter CL_TIME = 12840; // CL ps Minimum CAS Latency + `elsif sg107F // sg107F is equivalent to the JEDEC DDR3-1866 (11-11-11) speed bin + parameter TCK_MIN = 1070; // tCK ps Minimum Clock Cycle Time + parameter TJIT_PER = 60; // tJIT(per) ps Period JItter + parameter TJIT_CC = 120; // tJIT(cc) ps Cycle to Cycle jitter + parameter TERR_2PER = 88; // tERR(2per) ps Accumulated Error (2-cycle) + parameter TERR_3PER = 105; // tERR(3per) ps Accumulated Error (3-cycle) + parameter TERR_4PER = 117; // tERR(4per) ps Accumulated Error (4-cycle) + parameter TERR_5PER = 126; // tERR(5per) ps Accumulated Error (5-cycle) + parameter TERR_6PER = 133; // tERR(6per) ps Accumulated Error (6-cycle) + parameter TERR_7PER = 139; // tERR(7per) ps Accumulated Error (7-cycle) + parameter TERR_8PER = 145; // tERR(8per) ps Accumulated Error (8-cycle) + parameter TERR_9PER = 150; // tERR(9per) ps Accumulated Error (9-cycle) + parameter TERR_10PER = 154; // tERR(10per)ps Accumulated Error (10-cycle) + parameter TERR_11PER = 158; // tERR(11per)ps Accumulated Error (11-cycle) + parameter TERR_12PER = 161; // tERR(12per)ps Accumulated Error (12-cycle) + parameter TDS = 10; // tDS ps DQ and DM input setup time relative to DQS + parameter TDH = 20; // tDH ps DQ and DM input hold time relative to DQS + parameter TDQSQ = 80; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access + parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition + parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) + parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) + parameter TDQSCK = 200; // tDQSCK ps DQS output access time from CK/CK# + parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width + parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width + parameter TDIPW = 320; // tDIPW ps DQ and DM input Pulse Width + parameter TIPW = 535; // tIPW ps Control and Address input Pulse Width + parameter TIS = 50; // tIS ps Input Setup Time + parameter TIH = 100; // tIH ps Input Hold Time + parameter TRAS_MIN = 34000; // tRAS ps Minimum Active to Precharge command time + parameter TRC = 46770; // tRC ps Active to Active/Auto Refresh command time + parameter TRCD = 11770; // tRCD ps Active to Read/Write command time + parameter TRP = 11770; // tRP ps Precharge command period + parameter TXP = 6000; // tXP ps Exit power down to a valid command + parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width + parameter TAON = 200; // tAON ps RTT turn-on from ODTLon reference + parameter TWLS = 140; // tWLS ps Setup time for tDQS flop + parameter TWLH = 140; // tWLH ps Hold time of tDQS flop + parameter TWLO = 7500; // tWLO ps Write levelization output delay + parameter TAA_MIN = 11770; // TAA ps Internal READ command to first data + parameter CL_TIME = 11770; // CL ps Minimum CAS Latency + `elsif sg125E // sg125E is equivalent to the JEDEC DDR3-1600 (10-10-10) speed bin + parameter TCK_MIN = 1250; // tCK ps Minimum Clock Cycle Time + parameter TJIT_PER = 70; // tJIT(per) ps Period JItter + parameter TJIT_CC = 140; // tJIT(cc) ps Cycle to Cycle jitter + parameter TERR_2PER = 103; // tERR(2per) ps Accumulated Error (2-cycle) + parameter TERR_3PER = 122; // tERR(3per) ps Accumulated Error (3-cycle) + parameter TERR_4PER = 136; // tERR(4per) ps Accumulated Error (4-cycle) + parameter TERR_5PER = 147; // tERR(5per) ps Accumulated Error (5-cycle) + parameter TERR_6PER = 155; // tERR(6per) ps Accumulated Error (6-cycle) + parameter TERR_7PER = 163; // tERR(7per) ps Accumulated Error (7-cycle) + parameter TERR_8PER = 169; // tERR(8per) ps Accumulated Error (8-cycle) + parameter TERR_9PER = 175; // tERR(9per) ps Accumulated Error (9-cycle) + parameter TERR_10PER = 180; // tERR(10per)ps Accumulated Error (10-cycle) + parameter TERR_11PER = 184; // tERR(11per)ps Accumulated Error (11-cycle) + parameter TERR_12PER = 188; // tERR(12per)ps Accumulated Error (12-cycle) + parameter TDS = 10; // tDS ps DQ and DM input setup time relative to DQS + parameter TDH = 45; // tDH ps DQ and DM input hold time relative to DQS + parameter TDQSQ = 100; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access + parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition + parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) + parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) + parameter TDQSCK = 225; // tDQSCK ps DQS output access time from CK/CK# + parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width + parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width + parameter TDIPW = 360; // tDIPW ps DQ and DM input Pulse Width + parameter TIPW = 560; // tIPW ps Control and Address input Pulse Width + parameter TIS = 170; // tIS ps Input Setup Time + parameter TIH = 120; // tIH ps Input Hold Time + parameter TRAS_MIN = 35000; // tRAS ps Minimum Active to Precharge command time + parameter TRC = 47500; // tRC ps Active to Active/Auto Refresh command time + parameter TRCD = 12500; // tRCD ps Active to Read/Write command time + parameter TRP = 12500; // tRP ps Precharge command period + parameter TXP = 6000; // tXP ps Exit power down to a valid command + parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width + parameter TAON = 250; // tAON ps RTT turn-on from ODTLon reference + parameter TWLS = 165; // tWLS ps Setup time for tDQS flop + parameter TWLH = 165; // tWLH ps Hold time of tDQS flop + parameter TWLO = 7500; // tWLO ps Write levelization output delay + parameter TAA_MIN = 12500; // TAA ps Internal READ command to first data + parameter CL_TIME = 12500; // CL ps Minimum CAS Latency + `elsif sg125 // sg125 is equivalent to the JEDEC DDR3-1600 (11-11-11) speed bin + parameter TCK_MIN = 1250; // tCK ps Minimum Clock Cycle Time + parameter TJIT_PER = 70; // tJIT(per) ps Period JItter + parameter TJIT_CC = 140; // tJIT(cc) ps Cycle to Cycle jitter + parameter TERR_2PER = 103; // tERR(2per) ps Accumulated Error (2-cycle) + parameter TERR_3PER = 122; // tERR(3per) ps Accumulated Error (3-cycle) + parameter TERR_4PER = 136; // tERR(4per) ps Accumulated Error (4-cycle) + parameter TERR_5PER = 147; // tERR(5per) ps Accumulated Error (5-cycle) + parameter TERR_6PER = 155; // tERR(6per) ps Accumulated Error (6-cycle) + parameter TERR_7PER = 163; // tERR(7per) ps Accumulated Error (7-cycle) + parameter TERR_8PER = 169; // tERR(8per) ps Accumulated Error (8-cycle) + parameter TERR_9PER = 175; // tERR(9per) ps Accumulated Error (9-cycle) + parameter TERR_10PER = 180; // tERR(10per)ps Accumulated Error (10-cycle) + parameter TERR_11PER = 184; // tERR(11per)ps Accumulated Error (11-cycle) + parameter TERR_12PER = 188; // tERR(12per)ps Accumulated Error (12-cycle) + parameter TDS = 10; // tDS ps DQ and DM input setup time relative to DQS + parameter TDH = 45; // tDH ps DQ and DM input hold time relative to DQS + parameter TDQSQ = 100; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access + parameter TDQSS = 0.27; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition + parameter TDSS = 0.18; // tDSS tCK DQS falling edge to CLK rising (setup time) + parameter TDSH = 0.18; // tDSH tCK DQS falling edge from CLK rising (hold time) + parameter TDQSCK = 225; // tDQSCK ps DQS output access time from CK/CK# + parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width + parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width + parameter TDIPW = 360; // tDIPW ps DQ and DM input Pulse Width + parameter TIPW = 560; // tIPW ps Control and Address input Pulse Width + parameter TIS = 170; // tIS ps Input Setup Time + parameter TIH = 120; // tIH ps Input Hold Time + parameter TRAS_MIN = 35000; // tRAS ps Minimum Active to Precharge command time + parameter TRC = 48750; // tRC ps Active to Active/Auto Refresh command time + parameter TRCD = 13125; // tRCD ps Active to Read/Write command time + parameter TRP = 13125; // tRP ps Precharge command period + parameter TXP = 6000; // tXP ps Exit power down to a valid command + parameter TCKE = 5000; // tCKE ps CKE minimum high or low pulse width + parameter TAON = 250; // tAON ps RTT turn-on from ODTLon reference + parameter TWLS = 165; // tWLS ps Setup time for tDQS flop + parameter TWLH = 165; // tWLH ps Hold time of tDQS flop + parameter TWLO = 7500; // tWLO ps Write levelization output delay + parameter TAA_MIN = 13125; // TAA ps Internal READ command to first data + parameter CL_TIME = 13125; // CL ps Minimum CAS Latency + `elsif sg15E // sg15E is equivalent to the JEDEC DDR3-1333H (9-9-9) speed bin + parameter TCK_MIN = 1500; // tCK ps Minimum Clock Cycle Time + parameter TJIT_PER = 80; // tJIT(per) ps Period JItter + parameter TJIT_CC = 160; // tJIT(cc) ps Cycle to Cycle jitter + parameter TERR_2PER = 118; // tERR(2per) ps Accumulated Error (2-cycle) + parameter TERR_3PER = 140; // tERR(3per) ps Accumulated Error (3-cycle) + parameter TERR_4PER = 155; // tERR(4per) ps Accumulated Error (4-cycle) + parameter TERR_5PER = 168; // tERR(5per) ps Accumulated Error (5-cycle) + parameter TERR_6PER = 177; // tERR(6per) ps Accumulated Error (6-cycle) + parameter TERR_7PER = 186; // tERR(7per) ps Accumulated Error (7-cycle) + parameter TERR_8PER = 193; // tERR(8per) ps Accumulated Error (8-cycle) + parameter TERR_9PER = 200; // tERR(9per) ps Accumulated Error (9-cycle) + parameter TERR_10PER = 205; // tERR(10per)ps Accumulated Error (10-cycle) + parameter TERR_11PER = 210; // tERR(11per)ps Accumulated Error (11-cycle) + parameter TERR_12PER = 215; // tERR(12per)ps Accumulated Error (12-cycle) + parameter TDS = 30; // tDS ps DQ and DM input setup time relative to DQS + parameter TDH = 65; // tDH ps DQ and DM input hold time relative to DQS + parameter TDQSQ = 125; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access + parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition + parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time) + parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time) + parameter TDQSCK = 255; // tDQSCK ps DQS output access time from CK/CK# + parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width + parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width + parameter TDIPW = 400; // tDIPW ps DQ and DM input Pulse Width + parameter TIPW = 620; // tIPW ps Control and Address input Pulse Width + parameter TIS = 190; // tIS ps Input Setup Time + parameter TIH = 140; // tIH ps Input Hold Time + parameter TRAS_MIN = 36000; // tRAS ps Minimum Active to Precharge command time + parameter TRC = 49500; // tRC ps Active to Active/Auto Refresh command time + parameter TRCD = 13125; // tRCD ps Active to Read/Write command time + parameter TRP = 13125; // tRP ps Precharge command period + parameter TXP = 6000; // tXP ps Exit power down to a valid command + parameter TCKE = 5625; // tCKE ps CKE minimum high or low pulse width + parameter TAON = 250; // tAON ps RTT turn-on from ODTLon reference + parameter TWLS = 195; // tWLS ps Setup time for tDQS flop + parameter TWLH = 195; // tWLH ps Hold time of tDQS flop + parameter TWLO = 9000; // tWLO ps Write levelization output delay + parameter TAA_MIN = 13125; // TAA ps Internal READ command to first data + parameter CL_TIME = 13125; // CL ps Minimum CAS Latency + `elsif sg15 // sg15 is equivalent to the JEDEC DDR3-1333J (10-10-10) speed bin + parameter TCK_MIN = 1500; // tCK ps Minimum Clock Cycle Time + parameter TJIT_PER = 80; // tJIT(per) ps Period JItter + parameter TJIT_CC = 160; // tJIT(cc) ps Cycle to Cycle jitter + parameter TERR_2PER = 118; // tERR(2per) ps Accumulated Error (2-cycle) + parameter TERR_3PER = 140; // tERR(3per) ps Accumulated Error (3-cycle) + parameter TERR_4PER = 155; // tERR(4per) ps Accumulated Error (4-cycle) + parameter TERR_5PER = 168; // tERR(5per) ps Accumulated Error (5-cycle) + parameter TERR_6PER = 177; // tERR(6per) ps Accumulated Error (6-cycle) + parameter TERR_7PER = 186; // tERR(7per) ps Accumulated Error (7-cycle) + parameter TERR_8PER = 193; // tERR(8per) ps Accumulated Error (8-cycle) + parameter TERR_9PER = 200; // tERR(9per) ps Accumulated Error (9-cycle) + parameter TERR_10PER = 205; // tERR(10per)ps Accumulated Error (10-cycle) + parameter TERR_11PER = 210; // tERR(11per)ps Accumulated Error (11-cycle) + parameter TERR_12PER = 215; // tERR(12per)ps Accumulated Error (12-cycle) + parameter TDS = 30; // tDS ps DQ and DM input setup time relative to DQS + parameter TDH = 65; // tDH ps DQ and DM input hold time relative to DQS + parameter TDQSQ = 125; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access + parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition + parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time) + parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time) + parameter TDQSCK = 255; // tDQSCK ps DQS output access time from CK/CK# + parameter TQSH = 0.40; // tQSH tCK DQS Output High Pulse Width + parameter TQSL = 0.40; // tQSL tCK DQS Output Low Pulse Width + parameter TDIPW = 400; // tDIPW ps DQ and DM input Pulse Width + parameter TIPW = 620; // tIPW ps Control and Address input Pulse Width + parameter TIS = 190; // tIS ps Input Setup Time + parameter TIH = 140; // tIH ps Input Hold Time + parameter TRAS_MIN = 36000; // tRAS ps Minimum Active to Precharge command time + parameter TRC = 51000; // tRC ps Active to Active/Auto Refresh command time + parameter TRCD = 15000; // tRCD ps Active to Read/Write command time + parameter TRP = 15000; // tRP ps Precharge command period + parameter TXP = 6000; // tXP ps Exit power down to a valid command + parameter TCKE = 5625; // tCKE ps CKE minimum high or low pulse width + parameter TAON = 250; // tAON ps RTT turn-on from ODTLon reference + parameter TWLS = 195; // tWLS ps Setup time for tDQS flop + parameter TWLH = 195; // tWLH ps Hold time of tDQS flop + parameter TWLO = 9000; // tWLO ps Write levelization output delay + parameter TAA_MIN = 15000; // TAA ps Internal READ command to first data + parameter CL_TIME = 15000; // CL ps Minimum CAS Latency + `elsif sg187E // sg187E is equivalent to the JEDEC DDR3-1066F (7-7-7) speed bin + parameter TCK_MIN = 1875; // tCK ps Minimum Clock Cycle Time + parameter TJIT_PER = 90; // tJIT(per) ps Period JItter + parameter TJIT_CC = 180; // tJIT(cc) ps Cycle to Cycle jitter + parameter TERR_2PER = 132; // tERR(2per) ps Accumulated Error (2-cycle) + parameter TERR_3PER = 157; // tERR(3per) ps Accumulated Error (3-cycle) + parameter TERR_4PER = 175; // tERR(4per) ps Accumulated Error (4-cycle) + parameter TERR_5PER = 188; // tERR(5per) ps Accumulated Error (5-cycle) + parameter TERR_6PER = 200; // tERR(6per) ps Accumulated Error (6-cycle) + parameter TERR_7PER = 209; // tERR(7per) ps Accumulated Error (7-cycle) + parameter TERR_8PER = 217; // tERR(8per) ps Accumulated Error (8-cycle) + parameter TERR_9PER = 224; // tERR(9per) ps Accumulated Error (9-cycle) + parameter TERR_10PER = 231; // tERR(10per)ps Accumulated Error (10-cycle) + parameter TERR_11PER = 237; // tERR(11per)ps Accumulated Error (11-cycle) + parameter TERR_12PER = 242; // tERR(12per)ps Accumulated Error (12-cycle) + parameter TDS = 75; // tDS ps DQ and DM input setup time relative to DQS + parameter TDH = 100; // tDH ps DQ and DM input hold time relative to DQS + parameter TDQSQ = 150; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access + parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition + parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time) + parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time) + parameter TDQSCK = 300; // tDQSCK ps DQS output access time from CK/CK# + parameter TQSH = 0.38; // tQSH tCK DQS Output High Pulse Width + parameter TQSL = 0.38; // tQSL tCK DQS Output Low Pulse Width + parameter TDIPW = 490; // tDIPW ps DQ and DM input Pulse Width + parameter TIPW = 780; // tIPW ps Control and Address input Pulse Width + parameter TIS = 275; // tIS ps Input Setup Time + parameter TIH = 200; // tIH ps Input Hold Time + parameter TRAS_MIN = 37500; // tRAS ps Minimum Active to Precharge command time + parameter TRC = 50625; // tRC ps Active to Active/Auto Refresh command time + parameter TRCD = 13125; // tRCD ps Active to Read/Write command time + parameter TRP = 13125; // tRP ps Precharge command period + parameter TXP = 7500; // tXP ps Exit power down to a valid command + parameter TCKE = 5625; // tCKE ps CKE minimum high or low pulse width + parameter TAON = 300; // tAON ps RTT turn-on from ODTLon reference + parameter TWLS = 245; // tWLS ps Setup time for tDQS flop + parameter TWLH = 245; // tWLH ps Hold time of tDQS flop + parameter TWLO = 9000; // tWLO ps Write levelization output delay + parameter TAA_MIN = 13125; // TAA ps Internal READ command to first data + parameter CL_TIME = 13125; // CL ps Minimum CAS Latency + `elsif sg187 // sg187 is equivalent to the JEDEC DDR3-1066G (8-8-8) speed bin + parameter TCK_MIN = 1875; // tCK ps Minimum Clock Cycle Time + parameter TJIT_PER = 90; // tJIT(per) ps Period JItter + parameter TJIT_CC = 180; // tJIT(cc) ps Cycle to Cycle jitter + parameter TERR_2PER = 132; // tERR(2per) ps Accumulated Error (2-cycle) + parameter TERR_3PER = 157; // tERR(3per) ps Accumulated Error (3-cycle) + parameter TERR_4PER = 175; // tERR(4per) ps Accumulated Error (4-cycle) + parameter TERR_5PER = 188; // tERR(5per) ps Accumulated Error (5-cycle) + parameter TERR_6PER = 200; // tERR(6per) ps Accumulated Error (6-cycle) + parameter TERR_7PER = 209; // tERR(7per) ps Accumulated Error (7-cycle) + parameter TERR_8PER = 217; // tERR(8per) ps Accumulated Error (8-cycle) + parameter TERR_9PER = 224; // tERR(9per) ps Accumulated Error (9-cycle) + parameter TERR_10PER = 231; // tERR(10per)ps Accumulated Error (10-cycle) + parameter TERR_11PER = 237; // tERR(11per)ps Accumulated Error (11-cycle) + parameter TERR_12PER = 242; // tERR(12per)ps Accumulated Error (12-cycle) + parameter TDS = 75; // tDS ps DQ and DM input setup time relative to DQS + parameter TDH = 100; // tDH ps DQ and DM input hold time relative to DQS + parameter TDQSQ = 150; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access + parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition + parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time) + parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time) + parameter TDQSCK = 300; // tDQSCK ps DQS output access time from CK/CK# + parameter TQSH = 0.38; // tQSH tCK DQS Output High Pulse Width + parameter TQSL = 0.38; // tQSL tCK DQS Output Low Pulse Width + parameter TDIPW = 490; // tDIPW ps DQ and DM input Pulse Width + parameter TIPW = 780; // tIPW ps Control and Address input Pulse Width + parameter TIS = 275; // tIS ps Input Setup Time + parameter TIH = 200; // tIH ps Input Hold Time + parameter TRAS_MIN = 37500; // tRAS ps Minimum Active to Precharge command time + parameter TRC = 52500; // tRC ps Active to Active/Auto Refresh command time + parameter TRCD = 15000; // tRCD ps Active to Read/Write command time + parameter TRP = 15000; // tRP ps Precharge command period + parameter TXP = 7500; // tXP ps Exit power down to a valid command + parameter TCKE = 5625; // tCKE ps CKE minimum high or low pulse width + parameter TAON = 300; // tAON ps RTT turn-on from ODTLon reference + parameter TWLS = 245; // tWLS ps Setup time for tDQS flop + parameter TWLH = 245; // tWLH ps Hold time of tDQS flop + parameter TWLO = 9000; // tWLO ps Write levelization output delay + parameter TAA_MIN = 15000; // TAA ps Internal READ command to first data + parameter CL_TIME = 15000; // CL ps Minimum CAS Latency + `elsif sg25E // sg25E is equivalent to the JEDEC DDR3-800E (5-5-5) speed bin + parameter TCK_MIN = 2500; // tCK ps Minimum Clock Cycle Time + parameter TJIT_PER = 100; // tJIT(per) ps Period JItter + parameter TJIT_CC = 200; // tJIT(cc) ps Cycle to Cycle jitter + parameter TERR_2PER = 147; // tERR(2per) ps Accumulated Error (2-cycle) + parameter TERR_3PER = 175; // tERR(3per) ps Accumulated Error (3-cycle) + parameter TERR_4PER = 194; // tERR(4per) ps Accumulated Error (4-cycle) + parameter TERR_5PER = 209; // tERR(5per) ps Accumulated Error (5-cycle) + parameter TERR_6PER = 222; // tERR(6per) ps Accumulated Error (6-cycle) + parameter TERR_7PER = 232; // tERR(7per) ps Accumulated Error (7-cycle) + parameter TERR_8PER = 241; // tERR(8per) ps Accumulated Error (8-cycle) + parameter TERR_9PER = 249; // tERR(9per) ps Accumulated Error (9-cycle) + parameter TERR_10PER = 257; // tERR(10per)ps Accumulated Error (10-cycle) + parameter TERR_11PER = 263; // tERR(11per)ps Accumulated Error (11-cycle) + parameter TERR_12PER = 269; // tERR(12per)ps Accumulated Error (12-cycle) + parameter TDS = 125; // tDS ps DQ and DM input setup time relative to DQS + parameter TDH = 150; // tDH ps DQ and DM input hold time relative to DQS + parameter TDQSQ = 200; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access + parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition + parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time) + parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time) + parameter TDQSCK = 400; // tDQSCK ps DQS output access time from CK/CK# + parameter TQSH = 0.38; // tQSH tCK DQS Output High Pulse Width + parameter TQSL = 0.38; // tQSL tCK DQS Output Low Pulse Width + parameter TDIPW = 600; // tDIPW ps DQ and DM input Pulse Width + parameter TIPW = 900; // tIPW ps Control and Address input Pulse Width + parameter TIS = 350; // tIS ps Input Setup Time + parameter TIH = 275; // tIH ps Input Hold Time + parameter TRAS_MIN = 37500; // tRAS ps Minimum Active to Precharge command time + parameter TRC = 50000; // tRC ps Active to Active/Auto Refresh command time + parameter TRCD = 12500; // tRCD ps Active to Read/Write command time + parameter TRP = 12500; // tRP ps Precharge command period + parameter TXP = 7500; // tXP ps Exit power down to a valid command + parameter TCKE = 7500; // tCKE ps CKE minimum high or low pulse width + parameter TAON = 400; // tAON ps RTT turn-on from ODTLon reference + parameter TWLS = 325; // tWLS ps Setup time for tDQS flop + parameter TWLH = 325; // tWLH ps Hold time of tDQS flop + parameter TWLO = 9000; // tWLO ps Write levelization output delay + parameter TAA_MIN = 12500; // TAA ps Internal READ command to first data + parameter CL_TIME = 12500; // CL ps Minimum CAS Latency + `else `define sg25 // sg25 is equivalent to the JEDEC DDR3-800 (6-6-6) speed bin + parameter TCK_MIN = 2500; // tCK ps Minimum Clock Cycle Time + parameter TJIT_PER = 100; // tJIT(per) ps Period JItter + parameter TJIT_CC = 200; // tJIT(cc) ps Cycle to Cycle jitter + parameter TERR_2PER = 147; // tERR(2per) ps Accumulated Error (2-cycle) + parameter TERR_3PER = 175; // tERR(3per) ps Accumulated Error (3-cycle) + parameter TERR_4PER = 194; // tERR(4per) ps Accumulated Error (4-cycle) + parameter TERR_5PER = 209; // tERR(5per) ps Accumulated Error (5-cycle) + parameter TERR_6PER = 222; // tERR(6per) ps Accumulated Error (6-cycle) + parameter TERR_7PER = 232; // tERR(7per) ps Accumulated Error (7-cycle) + parameter TERR_8PER = 241; // tERR(8per) ps Accumulated Error (8-cycle) + parameter TERR_9PER = 249; // tERR(9per) ps Accumulated Error (9-cycle) + parameter TERR_10PER = 257; // tERR(10per)ps Accumulated Error (10-cycle) + parameter TERR_11PER = 263; // tERR(11per)ps Accumulated Error (11-cycle) + parameter TERR_12PER = 269; // tERR(12per)ps Accumulated Error (12-cycle) + parameter TDS = 125; // tDS ps DQ and DM input setup time relative to DQS + parameter TDH = 150; // tDH ps DQ and DM input hold time relative to DQS + parameter TDQSQ = 200; // tDQSQ ps DQS-DQ skew, DQS to last DQ valid, per group, per access + parameter TDQSS = 0.25; // tDQSS tCK Rising clock edge to DQS/DQS# latching transition + parameter TDSS = 0.20; // tDSS tCK DQS falling edge to CLK rising (setup time) + parameter TDSH = 0.20; // tDSH tCK DQS falling edge from CLK rising (hold time) + parameter TDQSCK = 400; // tDQSCK ps DQS output access time from CK/CK# + parameter TQSH = 0.38; // tQSH tCK DQS Output High Pulse Width + parameter TQSL = 0.38; // tQSL tCK DQS Output Low Pulse Width + parameter TDIPW = 600; // tDIPW ps DQ and DM input Pulse Width + parameter TIPW = 900; // tIPW ps Control and Address input Pulse Width + parameter TIS = 350; // tIS ps Input Setup Time + parameter TIH = 275; // tIH ps Input Hold Time + parameter TRAS_MIN = 37500; // tRAS ps Minimum Active to Precharge command time + parameter TRC = 52500; // tRC ps Active to Active/Auto Refresh command time + parameter TRCD = 15000; // tRCD ps Active to Read/Write command time + parameter TRP = 15000; // tRP ps Precharge command period + parameter TXP = 7500; // tXP ps Exit power down to a valid command + parameter TCKE = 7500; // tCKE ps CKE minimum high or low pulse width + parameter TAON = 400; // tAON ps RTT turn-on from ODTLon reference + parameter TWLS = 325; // tWLS ps Setup time for tDQS flop + parameter TWLH = 325; // tWLH ps Hold time of tDQS flop + parameter TWLO = 9000; // tWLO ps Write levelization output delay + parameter TAA_MIN = 15000; // TAA ps Internal READ command to first data + parameter CL_TIME = 15000; // CL ps Minimum CAS Latency + `endif + + `ifdef x16 + `ifdef sg093 + parameter TRRD = 6000; // tRRD ps (2KB page size) Active bank a to Active bank b command time + parameter TFAW = 35000; // tFAW ps (2KB page size) Four Bank Activate window + `elsif sg093E + parameter TRRD = 6000; // tRRD ps (2KB page size) Active bank a to Active bank b command time + parameter TFAW = 35000; // tFAW ps (2KB page size) Four Bank Activate window + `elsif sg093F + parameter TRRD = 6000; // tRRD ps (2KB page size) Active bank a to Active bank b command time + parameter TFAW = 35000; // tFAW ps (2KB page size) Four Bank Activate window + `elsif sg107 + parameter TRRD = 6000; // tRRD ps (2KB page size) Active bank a to Active bank b command time + parameter TFAW = 35000; // tFAW ps (2KB page size) Four Bank Activate window + `elsif sg107E + parameter TRRD = 6000; // tRRD ps (2KB page size) Active bank a to Active bank b command time + parameter TFAW = 35000; // tFAW ps (2KB page size) Four Bank Activate window + `elsif sg107F + parameter TRRD = 6000; // tRRD ps (2KB page size) Active bank a to Active bank b command time + parameter TFAW = 35000; // tFAW ps (2KB page size) Four Bank Activate window + `elsif sg125E + parameter TRRD = 7500; // tRRD ps (2KB page size) Active bank a to Active bank b command time + parameter TFAW = 40000; // tFAW ps (2KB page size) Four Bank Activate window + `elsif sg125 + parameter TRRD = 7500; // tRRD ps (2KB page size) Active bank a to Active bank b command time + parameter TFAW = 40000; // tFAW ps (2KB page size) Four Bank Activate window + `elsif sg15E + parameter TRRD = 7500; // tRRD ps (2KB page size) Active bank a to Active bank b command time + parameter TFAW = 45000; // tFAW ps (2KB page size) Four Bank Activate window + `elsif sg15 + parameter TRRD = 7500; // tRRD ps (2KB page size) Active bank a to Active bank b command time + parameter TFAW = 45000; // tFAW ps (2KB page size) Four Bank Activate window + `elsif sg187E + parameter TRRD = 10000; // tRRD ps (2KB page size) Active bank a to Active bank b command time + parameter TFAW = 50000; // tFAW ps (2KB page size) Four Bank Activate window + `elsif sg187 + parameter TRRD = 10000; // tRRD ps (2KB page size) Active bank a to Active bank b command time + parameter TFAW = 50000; // tFAW ps (2KB page size) Four Bank Activate window + `elsif sg25E + parameter TRRD = 10000; // tRRD ps (2KB page size) Active bank a to Active bank b command time + parameter TFAW = 50000; // tFAW ps (2KB page size) Four Bank Activate window + `else // sg25 + parameter TRRD = 10000; // tRRD ps (2KB page size) Active bank a to Active bank b command time + parameter TFAW = 50000; // tFAW ps (2KB page size) Four Bank Activate window + `endif + `else // x4, x8 + `ifdef sg093 + parameter TRRD = 5000; // tRRD ps (1KB page size) Active bank a to Active bank b command time + parameter TFAW = 25000; // tFAW ps (1KB page size) Four Bank Activate window + `elsif sg093E + parameter TRRD = 5000; // tRRD ps (1KB page size) Active bank a to Active bank b command time + parameter TFAW = 25000; // tFAW ps (1KB page size) Four Bank Activate window + `elsif sg093F + parameter TRRD = 5000; // tRRD ps (1KB page size) Active bank a to Active bank b command time + parameter TFAW = 25000; // tFAW ps (1KB page size) Four Bank Activate window + `elsif sg107 + parameter TRRD = 5000; // tRRD ps (1KB page size) Active bank a to Active bank b command time + parameter TFAW = 25000; // tFAW ps (1KB page size) Four Bank Activate window + `elsif sg107E + parameter TRRD = 5000; // tRRD ps (1KB page size) Active bank a to Active bank b command time + parameter TFAW = 25000; // tFAW ps (1KB page size) Four Bank Activate window + `elsif sg107F + parameter TRRD = 5000; // tRRD ps (1KB page size) Active bank a to Active bank b command time + parameter TFAW = 25000; // tFAW ps (1KB page size) Four Bank Activate window + `elsif sg125E + parameter TRRD = 6000; // tRRD ps (1KB page size) Active bank a to Active bank b command time + parameter TFAW = 30000; // tFAW ps (1KB page size) Four Bank Activate window + `elsif sg125 + parameter TRRD = 6000; // tRRD ps (1KB page size) Active bank a to Active bank b command time + parameter TFAW = 30000; // tFAW ps (1KB page size) Four Bank Activate window + `elsif sg15E + parameter TRRD = 6000; // tRRD ps (1KB page size) Active bank a to Active bank b command time + parameter TFAW = 30000; // tFAW ps (1KB page size) Four Bank Activate window + `elsif sg15 + parameter TRRD = 6000; // tRRD ps (1KB page size) Active bank a to Active bank b command time + parameter TFAW = 30000; // tFAW ps (1KB page size) Four Bank Activate window + `elsif sg187E + parameter TRRD = 7500; // tRRD ps (1KB page size) Active bank a to Active bank b command time + parameter TFAW = 37500; // tFAW ps (1KB page size) Four Bank Activate window + `elsif sg187 + parameter TRRD = 7500; // tRRD ps (1KB page size) Active bank a to Active bank b command time + parameter TFAW = 37500; // tFAW ps (1KB page size) Four Bank Activate window + `elsif sg25E + parameter TRRD = 10000; // tRRD ps (1KB page size) Active bank a to Active bank b command time + parameter TFAW = 40000; // tFAW ps (1KB page size) Four Bank Activate window + `else // sg25 + parameter TRRD = 10000; // tRRD ps (1KB page size) Active bank a to Active bank b command time + parameter TFAW = 40000; // tFAW ps (1KB page size) Four Bank Activate window + `endif + `endif + + // Timing Parameters + + // Mode Register + parameter CL_MIN = 5; // CL tCK Minimum CAS Latency + parameter CL_MAX = 14; // CL tCK Maximum CAS Latency + parameter AL_MIN = 0; // AL tCK Minimum Additive Latency + parameter AL_MAX = 2; // AL tCK Maximum Additive Latency + parameter WR_MIN = 5; // WR tCK Minimum Write Recovery + parameter WR_MAX = 16; // WR tCK Maximum Write Recovery + parameter BL_MIN = 4; // BL tCK Minimum Burst Length + parameter BL_MAX = 8; // BL tCK Minimum Burst Length + parameter CWL_MIN = 5; // CWL tCK Minimum CAS Write Latency + parameter CWL_MAX = 10; // CWL tCK Maximum CAS Write Latency + + // Clock + parameter TCK_MAX = 3300; // tCK ps Maximum Clock Cycle Time + parameter TCH_AVG_MIN = 0.47; // tCH tCK Minimum Clock High-Level Pulse Width + parameter TCL_AVG_MIN = 0.47; // tCL tCK Minimum Clock Low-Level Pulse Width + parameter TCH_AVG_MAX = 0.53; // tCH tCK Maximum Clock High-Level Pulse Width + parameter TCL_AVG_MAX = 0.53; // tCL tCK Maximum Clock Low-Level Pulse Width + parameter TCH_ABS_MIN = 0.43; // tCH tCK Minimum Clock High-Level Pulse Width + parameter TCL_ABS_MIN = 0.43; // tCL tCK Maximum Clock Low-Level Pulse Width + parameter TCKE_TCK = 3; // tCKE tCK CKE minimum high or low pulse width + parameter TAA_MAX = 20000; // TAA ps Internal READ command to first data + + // Data OUT + parameter TQH = 0.38; // tQH ps DQ output hold time from DQS, DQS# + // Data Strobe OUT + parameter TRPRE = 0.90; // tRPRE tCK DQS Read Preamble + parameter TRPST = 0.30; // tRPST tCK DQS Read Postamble + // Data Strobe IN + parameter TDQSH = 0.45; // tDQSH tCK DQS input High Pulse Width + parameter TDQSL = 0.45; // tDQSL tCK DQS input Low Pulse Width + parameter TWPRE = 0.90; // tWPRE tCK DQS Write Preamble + parameter TWPST = 0.30; // tWPST tCK DQS Write Postamble + // Command and Address + parameter TZQCS = 64; // tZQCS tCK ZQ Cal (Short) time + parameter TZQINIT = 512; // tZQinit tCK ZQ Cal (Long) time + parameter TZQOPER = 256; // tZQoper tCK ZQ Cal (Long) time + parameter TCCD = 4; // tCCD tCK Cas to Cas command delay + parameter TCCD_DG = 2; // tCCD_DG tCK Cas to Cas command delay to different group + parameter TRAS_MAX = 60e9; // tRAS ps Maximum Active to Precharge command time + parameter TWR = 15000; // tWR ps Write recovery time + parameter TMRD = 4; // tMRD tCK Load Mode Register command cycle time + parameter TMOD = 15000; // tMOD ps LOAD MODE to non-LOAD MODE command cycle time + parameter TMOD_TCK = 12; // tMOD tCK LOAD MODE to non-LOAD MODE command cycle time + parameter TRRD_TCK = 4; // tRRD tCK Active bank a to Active bank b command time + parameter TRRD_DG = 3000; // tRRD_DG ps Active bank a to Active bank b command time to different group + parameter TRRD_DG_TCK = 2; // tRRD_DG tCK Active bank a to Active bank b command time to different group + parameter TRTP = 7500; // tRTP ps Read to Precharge command delay + parameter TRTP_TCK = 4; // tRTP tCK Read to Precharge command delay + parameter TWTR = 7500; // tWTR ps Write to Read command delay + parameter TWTR_DG = 3750; // tWTR_DG ps Write to Read command delay to different group + parameter TWTR_TCK = 4; // tWTR tCK Write to Read command delay + parameter TWTR_DG_TCK = 2; // tWTR_DG tCK Write to Read command delay to different group + parameter TDLLK = 512; // tDLLK tCK DLL locking time + // Refresh - 1Gb + parameter TRFC_MIN = 110000; // tRFC ps Refresh to Refresh Command interval minimum value + parameter TRFC_MAX =70312500; // tRFC ps Refresh to Refresh Command Interval maximum value + // Power Down + parameter TXP_TCK = 3; // tXP tCK Exit power down to a valid command + parameter TXPDLL = 24000; // tXPDLL ps Exit precharge power down to READ or WRITE command (DLL-off mode) + parameter TXPDLL_TCK = 10; // tXPDLL tCK Exit precharge power down to READ or WRITE command (DLL-off mode) + parameter TACTPDEN = 1; // tACTPDEN tCK Timing of last ACT command to power down entry + parameter TPRPDEN = 1; // tPREPDEN tCK Timing of last PRE command to power down entry + parameter TREFPDEN = 1; // tARPDEN tCK Timing of last REFRESH command to power down entry + parameter TCPDED = 1; // tCPDED tCK Command pass disable/enable delay + parameter TPD_MAX =TRFC_MAX; // tPD ps Power-down entry-to-exit timing + parameter TXPR = 120000; // tXPR ps Exit Reset from CKE assertion to a valid command + parameter TXPR_TCK = 5; // tXPR tCK Exit Reset from CKE assertion to a valid command + // Self Refresh + parameter TXS = 120000; // tXS ps Exit self refesh to a non-read or write command + parameter TXS_TCK = 5; // tXS tCK Exit self refesh to a non-read or write command + parameter TXSDLL = TDLLK; // tXSRD tCK Exit self refresh to a read or write command + parameter TISXR = TIS; // tISXR ps CKE setup time during self refresh exit. + parameter TCKSRE = 10000; // tCKSRE ps Valid Clock requirement after self refresh entry (SRE) + parameter TCKSRE_TCK = 5; // tCKSRE tCK Valid Clock requirement after self refresh entry (SRE) + parameter TCKSRX = 10000; // tCKSRX ps Valid Clock requirement prior to self refresh exit (SRX) + parameter TCKSRX_TCK = 5; // tCKSRX tCK Valid Clock requirement prior to self refresh exit (SRX) + parameter TCKESR_TCK = 4; // tCKESR tCK Minimum CKE low width for Self Refresh entry to exit timing + // ODT + parameter TAOF = 0.7; // tAOF tCK RTT turn-off from ODTLoff reference + parameter TAONPD = 8500; // tAONPD ps Asynchronous RTT turn-on delay (Power-Down with DLL frozen) + parameter TAOFPD = 8500; // tAONPD ps Asynchronous RTT turn-off delay (Power-Down with DLL frozen) + parameter ODTH4 = 4; // ODTH4 tCK ODT minimum HIGH time after ODT assertion or write (BL4) + parameter ODTH8 = 6; // ODTH8 tCK ODT minimum HIGH time after write (BL8) + parameter TADC = 0.7; // tADC tCK RTT dynamic change skew + // Write Levelization + parameter TWLMRD = 40; // tWLMRD tCK First DQS pulse rising edge after tDQSS margining mode is programmed + parameter TWLDQSEN = 25; // tWLDQSEN tCK DQS/DQS delay after tDQSS margining mode is programmed + parameter TWLOE = 2000; // tWLOE ps Write levelization output error + + // Size Parameters based on Part Width + + `ifdef x4 + parameter DM_BITS = 1; // Set this parameter to control how many Data Mask bits are used + parameter ADDR_BITS = 14; // MAX Address Bits + parameter ROW_BITS = 14; // Set this parameter to control how many Address bits are used + parameter COL_BITS = 11; // Set this parameter to control how many Column bits are used + parameter DQ_BITS = 4; // Set this parameter to control how many Data bits are used **Same as part bit width** + parameter DQS_BITS = 1; // Set this parameter to control how many Dqs bits are used + `elsif x8 + parameter DM_BITS = 1; // Set this parameter to control how many Data Mask bits are used + parameter ADDR_BITS = 14; // MAX Address Bits + parameter ROW_BITS = 14; // Set this parameter to control how many Address bits are used + parameter COL_BITS = 10; // Set this parameter to control how many Column bits are used + parameter DQ_BITS = 8; // Set this parameter to control how many Data bits are used **Same as part bit width** + parameter DQS_BITS = 1; // Set this parameter to control how many Dqs bits are used + `else `define x16 + parameter DM_BITS = 2; // Set this parameter to control how many Data Mask bits are used + parameter ADDR_BITS = 13; // MAX Address Bits + parameter ROW_BITS = 13; // Set this parameter to control how many Address bits are used + parameter COL_BITS = 10; // Set this parameter to control how many Column bits are used + parameter DQ_BITS = 16; // Set this parameter to control how many Data bits are used **Same as part bit width** + parameter DQS_BITS = 2; // Set this parameter to control how many Dqs bits are used + `endif + + // Size Parameters + parameter BA_BITS = 3; // Set this parmaeter to control how many Bank Address bits are used + parameter MEM_BITS = 15; // Set this parameter to control how many write data bursts can be stored in memory. The default is 2^10=1024. + parameter AP = 10; // the address bit that controls auto-precharge and precharge-all + parameter BC = 12; // the address bit that controls burst chop + parameter BL_BITS = 3; // the number of bits required to count to BL_MAX + parameter BO_BITS = 2; // the number of Burst Order Bits + + `ifdef QUAD_RANK + `define DUAL_RANK // also define DUAL_RANK + parameter CS_BITS = 4; // Number of Chip Select Bits + parameter RANKS = 4; // Number of Chip Selects + `elsif DUAL_RANK + parameter CS_BITS = 2; // Number of Chip Select Bits + parameter RANKS = 2; // Number of Chip Selects + `else + parameter CS_BITS = 2; // Number of Chip Select Bits + parameter RANKS = 1; // Number of Chip Selects + `endif + + // Simulation parameters + parameter RZQ = 240; // termination resistance + parameter PRE_DEF_PAT = 8'hAA; // value returned during mpr pre-defined pattern readout + parameter STOP_ON_ERROR = 1; // If set to 1, the model will halt on command sequence/major errors + parameter DEBUG = 1; // Turn on Debug messages + parameter BUS_DELAY = 0; // delay in nanoseconds + parameter RANDOM_OUT_DELAY = 0; // If set to 1, the model will put a random amount of delay on DQ/DQS during reads + parameter RANDOM_SEED = 711689044; //seed value for random generator. + + parameter RDQSEN_PRE = 2; // DQS driving time prior to first read strobe + parameter RDQSEN_PST = 1; // DQS driving time after last read strobe + parameter RDQS_PRE = 2; // DQS low time prior to first read strobe + parameter RDQS_PST = 1; // DQS low time after last read strobe + parameter RDQEN_PRE = 0; // DQ/DM driving time prior to first read data + parameter RDQEN_PST = 0; // DQ/DM driving time after last read data + parameter WDQS_PRE = 2; // DQS half clock periods prior to first write strobe + parameter WDQS_PST = 1; // DQS half clock periods after last write strobe + + // check for legal cas latency based on the cas write latency + function valid_cl; + input [3:0] cl; + input [3:0] cwl; + + case ({cwl, cl}) + `ifdef sg093 + {4'd5, 4'd6 }, + {4'd6, 4'd7 }, + {4'd6, 4'd8 }, + {4'd7, 4'd9 }, + {4'd7, 4'd10}, + {4'd8, 4'd11}, + {4'd9, 4'd13}, + {4'd10, 4'd14}: valid_cl = 1; + `elsif sg093E + {4'd5, 4'd5 }, + {4'd5, 4'd6 }, + {4'd6, 4'd7 }, + {4'd6, 4'd8 }, + {4'd7, 4'd9 }, + {4'd7, 4'd10}, + {4'd8, 4'd10}, + {4'd8, 4'd11}, + {4'd9, 4'd12}, + {4'd9, 4'd13}, + {4'd10, 4'd13}, + {4'd10, 4'd14}: valid_cl = 1; + `elsif sg093F + {4'd5, 4'd5 }, + {4'd5, 4'd6 }, + {4'd6, 4'd6 }, + {4'd6, 4'd7 }, + {4'd6, 4'd8 }, + {4'd7, 4'd8 }, + {4'd7, 4'd9 }, + {4'd7, 4'd10}, + {4'd8, 4'd9 }, + {4'd8, 4'd10}, + {4'd8, 4'd11}, + {4'd9, 4'd11}, + {4'd9, 4'd12}, + {4'd9, 4'd13}, + {4'd10, 4'd12}, + {4'd10, 4'd13}, + {4'd10, 4'd14}: valid_cl = 1; + `elsif sg107 + {4'd5, 4'd6 }, + {4'd6, 4'd8 }, + {4'd7, 4'd10}, + {4'd9, 4'd13}: valid_cl = 1; + `elsif sg107E + {4'd5, 4'd6 }, + {4'd6, 4'd7 }, + {4'd6, 4'd8 }, + {4'd7, 4'd9 }, + {4'd7, 4'd10}, + {4'd8, 4'd11}, + {4'd9, 4'd12}, + {4'd9, 4'd13}: valid_cl = 1; + `elsif sg107F + {4'd5, 4'd5 }, + {4'd5, 4'd6 }, + {4'd6, 4'd7 }, + {4'd6, 4'd8 }, + {4'd7, 4'd8 }, + {4'd7, 4'd9 }, + {4'd7, 4'd10}, + {4'd8, 4'd10}, + {4'd8, 4'd11}, + {4'd9, 4'd11}, + {4'd9, 4'd12}, + {4'd9, 4'd13}: valid_cl = 1; + `elsif sg125E + {4'd5, 4'd5 }, + {4'd5, 4'd6 }, + {4'd6, 4'd7 }, + {4'd6, 4'd8 }, + {4'd7, 4'd9 }, + {4'd7, 4'd10}, + {4'd8, 4'd10}, + {4'd8, 4'd11}: valid_cl = 1; + `elsif sg125 + {4'd5, 4'd5 }, + {4'd5, 4'd6 }, + {4'd6, 4'd7 }, + {4'd6, 4'd8 }, + {4'd7, 4'd9 }, + {4'd7, 4'd10}, + {4'd8, 4'd11}: valid_cl = 1; + `elsif sg15E + {4'd5, 4'd5 }, + {4'd5, 4'd6 }, + {4'd6, 4'd7 }, + {4'd6, 4'd8 }, + {4'd7, 4'd9 }, + {4'd7, 4'd10}: valid_cl = 1; + `elsif sg15 + {4'd5, 4'd5 }, + {4'd5, 4'd6 }, + {4'd6, 4'd8 }, + {4'd7, 4'd10}: valid_cl = 1; + `elsif sg187E + {4'd5, 4'd5 }, + {4'd5, 4'd6 }, + {4'd6, 4'd7 }, + {4'd6, 4'd8 }: valid_cl = 1; + `elsif sg187 + {4'd5, 4'd5 }, + {4'd5, 4'd6 }, + {4'd6, 4'd8 }: valid_cl = 1; + `elsif sg25E + {4'd5, 4'd5 }, + {4'd5, 4'd6 }: valid_cl = 1; + `elsif sg25 + {4'd5, 4'd5 }, + {4'd5, 4'd6 }: valid_cl = 1; + `endif + default : valid_cl = 0; + endcase + endfunction + + // find the minimum valid cas write latency + function [3:0] min_cwl; + input period; + real period; + min_cwl = (period >= 2500.0) ? 5: + (period >= 1875.0) ? 6: + (period >= 1500.0) ? 7: + (period >= 1250.0) ? 8: + (period >= 1070.0) ? 9: + 10; // (period >= 935) + endfunction + + // find the minimum valid cas latency + function [3:0] min_cl; + input period; + real period; + reg [3:0] cwl; + reg [3:0] cl; + begin + cwl = min_cwl(period); + for (cl=CL_MAX; cl>=CL_MIN; cl=cl-1) begin + if (valid_cl(cl, cwl)) begin + min_cl = cl; + end + end + end + endfunction + +`endif diff --git "a/Frogwells_fpga_design/\345\237\272\344\272\216FPGA\343\200\201DDR3\345\222\214USB2.0\347\232\204\345\233\276\345\203\217\351\207\207\351\233\206\347\263\273\347\273\237/debug/ddr_test/sim/functional/isim.tcl" "b/Frogwells_fpga_design/\345\237\272\344\272\216FPGA\343\200\201DDR3\345\222\214USB2.0\347\232\204\345\233\276\345\203\217\351\207\207\351\233\206\347\263\273\347\273\237/debug/ddr_test/sim/functional/isim.tcl" new file mode 100644 index 0000000000000000000000000000000000000000..b1e3d6cc91b3e27ea83dab2f100e3a5f60654ea7 --- /dev/null +++ "b/Frogwells_fpga_design/\345\237\272\344\272\216FPGA\343\200\201DDR3\345\222\214USB2.0\347\232\204\345\233\276\345\203\217\351\207\207\351\233\206\347\263\273\347\273\237/debug/ddr_test/sim/functional/isim.tcl" @@ -0,0 +1,72 @@ +############################################################################### +## (c) Copyright 2009 Xilinx, Inc. All rights reserved. +## +## This file contains confidential and proprietary information +## of Xilinx, Inc. and is protected under U.S. and +## international copyright and other intellectual property +## laws. +## +## DISCLAIMER +## This disclaimer is not a license and does not grant any +## rights to the materials distributed herewith. Except as +## otherwise provided in a valid license issued to you by +## Xilinx, and to the maximum extent permitted by applicable +## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +## (2) Xilinx shall not be liable (whether in contract or tort, +## including negligence, or under any other theory of +## liability) for any loss or damage of any kind or nature +## related to, arising under or in connection with these +## materials, including for any direct, or any indirect, +## special, incidental, or consequential loss or damage +## (including loss of data, profits, goodwill, or any type of +## loss or damage suffered as a result of any action brought +## by a third party) even if such damage or loss was +## reasonably foreseeable or Xilinx had been advised of the +## possibility of the same. +## +## CRITICAL APPLICATIONS +## Xilinx products are not designed or intended to be fail- +## safe, or for use in any application requiring fail-safe +## performance, such as life-support or safety devices or +## systems, Class III medical devices, nuclear facilities, +## applications related to the deployment of airbags, or any +## other applications that could lead to death, personal +## injury, or severe property or environmental damage +## (individually and collectively, "Critical +## Applications"). Customer assumes the sole risk and +## liability of any use of Xilinx products in Critical +## Applications, subject only to applicable laws and +## regulations governing limitations on product liability. +## +## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +## PART OF THIS FILE AT ALL TIMES. +## +############################################################################### +## ____ ____ +## / /\/ / +## /___/ \ / Vendor : Xilinx +## \ \ \/ Version : 3.92 +## \ \ Application : MIG +## / / Filename : isim.tcl +## /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:58 $ +## \ \ / \ Date Created : Mon Mar 2 2009 +## \___\/\___\ +## +## Device : Spartan-6 +## Design Name : DDR/DDR2/DDR3/LPDDR +## Purpose : To give commands to ISIM Simulator through batch mode +## Assumptions: +## - Simulation takes place in \sim folder of MIG output directory +## Reference : +## Revision History: +############################################################################### + +onerror {resume} +isim set radix hex +wave add /sim_tb_top +run 200 us +quit diff --git "a/Frogwells_fpga_design/\345\237\272\344\272\216FPGA\343\200\201DDR3\345\222\214USB2.0\347\232\204\345\233\276\345\203\217\351\207\207\351\233\206\347\263\273\347\273\237/debug/ddr_test/sim/functional/readme.txt" "b/Frogwells_fpga_design/\345\237\272\344\272\216FPGA\343\200\201DDR3\345\222\214USB2.0\347\232\204\345\233\276\345\203\217\351\207\207\351\233\206\347\263\273\347\273\237/debug/ddr_test/sim/functional/readme.txt" new file mode 100644 index 0000000000000000000000000000000000000000..866c6e4c07589926bc91c1cce8c6abafe7c252d6 --- /dev/null +++ "b/Frogwells_fpga_design/\345\237\272\344\272\216FPGA\343\200\201DDR3\345\222\214USB2.0\347\232\204\345\233\276\345\203\217\351\207\207\351\233\206\347\263\273\347\273\237/debug/ddr_test/sim/functional/readme.txt" @@ -0,0 +1,122 @@ +############################################################################### +## (c) Copyright 2009 Xilinx, Inc. All rights reserved. +## +## This file contains confidential and proprietary information +## of Xilinx, Inc. and is protected under U.S. and +## international copyright and other intellectual property +## laws. +## +## DISCLAIMER +## This disclaimer is not a license and does not grant any +## rights to the materials distributed herewith. Except as +## otherwise provided in a valid license issued to you by +## Xilinx, and to the maximum extent permitted by applicable +## law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND +## WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES +## AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING +## BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- +## INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and +## (2) Xilinx shall not be liable (whether in contract or tort, +## including negligence, or under any other theory of +## liability) for any loss or damage of any kind or nature +## related to, arising under or in connection with these +## materials, including for any direct, or any indirect, +## special, incidental, or consequential loss or damage +## (including loss of data, profits, goodwill, or any type of +## loss or damage suffered as a result of any action brought +## by a third party) even if such damage or loss was +## reasonably foreseeable or Xilinx had been advised of the +## possibility of the same. +## +## CRITICAL APPLICATIONS +## Xilinx products are not designed or intended to be fail- +## safe, or for use in any application requiring fail-safe +## performance, such as life-support or safety devices or +## systems, Class III medical devices, nuclear facilities, +## applications related to the deployment of airbags, or any +## other applications that could lead to death, personal +## injury, or severe property or environmental damage +## (individually and collectively, "Critical +## Applications"). Customer assumes the sole risk and +## liability of any use of Xilinx products in Critical +## Applications, subject only to applicable laws and +## regulations governing limitations on product liability. +## +## THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS +## PART OF THIS FILE AT ALL TIMES. +## +############################################################################### +## ____ ____ +## / /\/ / +## /___/ \ / Vendor : Xilinx +## \ \ \/ Version : 3.92 +## \ \ Application : MIG +## / / Filename : readme.txt +## /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:58 $ +## \ \ / \ Date Created : Mon Oct 19 2009 +## \___\/\___\ +## +## Device : Spartan-6 +## Design Name : DDR/DDR2/DDR3/LPDDR +## Purpose : Steps to run simulation using ISIM/Modelsim simualtor in this folder +## Assumptions: +## - Simulation takes place in \sim\ folder of MIG output directory +## Reference : +## Revision History: +############################################################################### + +The sim/functional folder has files to perform functional simulation of the design. + +1. Simulation using Modelsim simulator + +A) sim.do File : + + 1) The 'sim.do' file has commands to compile and simulate memory interface + design and run the simulation for specified period of time. + + 2) It has the syntax to Map the required libraries. + Also, $XILINX environment variable must be set in order to compile glbl.v file + + 3) Displays the waveforms that are listed with "add wave" command. + +B) Steps to run the Modelsim simulation: + + 1) The user should invoke the Modelsim simulator GUI. + 2) Change the present working directory path to the sim/functional folder. + In Transcript window, at Modelsim prompt, type the following command to + change directory path. + cd + + 2) Run the simulation using sim.do file. + At Modelsim prompt, type the following command: + do sim.do + + 3) To exit simulation, type the following command at Modelsim prompt: + quit -f + + 4) Verify the transcript file for the memory transactions. + + +2. Simulation using ISIM simulator + +A) Following files are provided : + + 1) The '.prj' file contains the list of all the files associated with the design. + It also contains the hdl, library and the source file name. + + 2) The '.tcl' file contains the Tcl commands for simulation and + resume on error. + + 3) The 'isim.bat' has commands which use '.prj' and '.tcl' files. + + +B) Steps to run the ISIM simulation: + + The user should execute the file isim.bat, which does the following steps: + 1) Compiles, elaborates the design and generates the simulation executable using + the fuse command in 'isim.bat' file. + + 2) Invokes the ISIM GUI. + + 3) User can add required signals from objects window to the waveform viewer and run + simulation for specified time using the command "run